
zephyr.elf:     file format elf32-littlearm


Disassembly of section rom_start:

00000000 <_vector_start>:
#include <syscalls/z_errno_mrsh.c>

#else
int *z_impl_z_errno(void)
{
	return &_current->errno_var;
   0:	20000b80 	.word	0x20000b80
}
   4:	00001419 	.word	0x00001419
   8:	00004347 	.word	0x00004347
   c:	000013ed 	.word	0x000013ed
  10:	000013ed 	.word	0x000013ed
  14:	000013ed 	.word	0x000013ed
  18:	000013ed 	.word	0x000013ed
	...
  2c:	000010f5 	.word	0x000010f5
  30:	000013ed 	.word	0x000013ed
  34:	00000000 	.word	0x00000000
  38:	000010a1 	.word	0x000010a1
  3c:	000013ed 	.word	0x000013ed

00000040 <_irq_vector_table>:
  40:	000011ad 000011ad 000011ad 000011ad     ................
  50:	000011ad 000011ad 000011ad 000011ad     ................
  60:	000011ad 000011ad 000011ad 000011ad     ................
  70:	000011ad 000011ad 000011ad 000011ad     ................
  80:	000011ad 000011ad 000011ad 000011ad     ................
  90:	000011ad 000011ad 000011ad 000011ad     ................
  a0:	000011ad 000011ad 000011ad 000011ad     ................
  b0:	000011ad 000011ad 000011ad 000011ad     ................
  c0:	000011ad 000011ad 000011ad 000011ad     ................
  d0:	000011ad 000011ad 000011ad              ............

Disassembly of section text:

000000dc <__aeabi_uldivmod>:
      dc:	b953      	cbnz	r3, f4 <__aeabi_uldivmod+0x18>
      de:	b94a      	cbnz	r2, f4 <__aeabi_uldivmod+0x18>
      e0:	2900      	cmp	r1, #0
      e2:	bf08      	it	eq
      e4:	2800      	cmpeq	r0, #0
      e6:	bf1c      	itt	ne
      e8:	f04f 31ff 	movne.w	r1, #4294967295
      ec:	f04f 30ff 	movne.w	r0, #4294967295
      f0:	f000 b96c 	b.w	3cc <__aeabi_idiv0>
      f4:	f1ad 0c08 	sub.w	ip, sp, #8
      f8:	e96d ce04 	strd	ip, lr, [sp, #-16]!
      fc:	f000 f806 	bl	10c <__udivmoddi4>
     100:	f8dd e004 	ldr.w	lr, [sp, #4]
     104:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
     108:	b004      	add	sp, #16
     10a:	4770      	bx	lr

0000010c <__udivmoddi4>:
     10c:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
     110:	9e08      	ldr	r6, [sp, #32]
     112:	460d      	mov	r5, r1
     114:	4604      	mov	r4, r0
     116:	468e      	mov	lr, r1
     118:	2b00      	cmp	r3, #0
     11a:	f040 8082 	bne.w	222 <CONFIG_FLASH_SIZE+0x22>
     11e:	428a      	cmp	r2, r1
     120:	4617      	mov	r7, r2
     122:	d946      	bls.n	1b2 <CONFIG_NRF52_ANOMALY_132_DELAY_US+0x68>
     124:	fab2 f282 	clz	r2, r2
     128:	b14a      	cbz	r2, 13e <__udivmoddi4+0x32>
     12a:	f1c2 0120 	rsb	r1, r2, #32
     12e:	fa05 f302 	lsl.w	r3, r5, r2
     132:	fa20 f101 	lsr.w	r1, r0, r1
     136:	4097      	lsls	r7, r2
     138:	ea41 0e03 	orr.w	lr, r1, r3
     13c:	4094      	lsls	r4, r2
     13e:	ea4f 4817 	mov.w	r8, r7, lsr #16
     142:	0c23      	lsrs	r3, r4, #16
     144:	fbbe fcf8 	udiv	ip, lr, r8
     148:	b2b9      	uxth	r1, r7
     14a:	fb08 ee1c 	mls	lr, r8, ip, lr
     14e:	ea43 430e 	orr.w	r3, r3, lr, lsl #16
     152:	fb0c f001 	mul.w	r0, ip, r1
     156:	4298      	cmp	r0, r3
     158:	d90a      	bls.n	170 <CONFIG_NRF52_ANOMALY_132_DELAY_US+0x26>
     15a:	18fb      	adds	r3, r7, r3
     15c:	f10c 35ff 	add.w	r5, ip, #4294967295
     160:	f080 8116 	bcs.w	390 <CONFIG_FLASH_SIZE+0x190>
     164:	4298      	cmp	r0, r3
     166:	f240 8113 	bls.w	390 <CONFIG_FLASH_SIZE+0x190>
     16a:	f1ac 0c02 	sub.w	ip, ip, #2
     16e:	443b      	add	r3, r7
     170:	1a1b      	subs	r3, r3, r0
     172:	b2a4      	uxth	r4, r4
     174:	fbb3 f0f8 	udiv	r0, r3, r8
     178:	fb08 3310 	mls	r3, r8, r0, r3
     17c:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
     180:	fb00 f101 	mul.w	r1, r0, r1
     184:	42a1      	cmp	r1, r4
     186:	d909      	bls.n	19c <CONFIG_NRF52_ANOMALY_132_DELAY_US+0x52>
     188:	193c      	adds	r4, r7, r4
     18a:	f100 33ff 	add.w	r3, r0, #4294967295
     18e:	f080 8101 	bcs.w	394 <CONFIG_FLASH_SIZE+0x194>
     192:	42a1      	cmp	r1, r4
     194:	f240 80fe 	bls.w	394 <CONFIG_FLASH_SIZE+0x194>
     198:	3802      	subs	r0, #2
     19a:	443c      	add	r4, r7
     19c:	1a64      	subs	r4, r4, r1
     19e:	ea40 400c 	orr.w	r0, r0, ip, lsl #16
     1a2:	2100      	movs	r1, #0
     1a4:	b11e      	cbz	r6, 1ae <CONFIG_NRF52_ANOMALY_132_DELAY_US+0x64>
     1a6:	40d4      	lsrs	r4, r2
     1a8:	2300      	movs	r3, #0
     1aa:	e9c6 4300 	strd	r4, r3, [r6]
     1ae:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
     1b2:	b902      	cbnz	r2, 1b6 <CONFIG_NRF52_ANOMALY_132_DELAY_US+0x6c>
     1b4:	deff      	udf	#255	; 0xff
     1b6:	fab2 f282 	clz	r2, r2
     1ba:	2a00      	cmp	r2, #0
     1bc:	d14f      	bne.n	25e <CONFIG_FLASH_SIZE+0x5e>
     1be:	1bcb      	subs	r3, r1, r7
     1c0:	ea4f 4e17 	mov.w	lr, r7, lsr #16
     1c4:	fa1f f887 	uxth.w	r8, r7
     1c8:	2101      	movs	r1, #1
     1ca:	fbb3 fcfe 	udiv	ip, r3, lr
     1ce:	0c25      	lsrs	r5, r4, #16
     1d0:	fb0e 331c 	mls	r3, lr, ip, r3
     1d4:	ea45 4503 	orr.w	r5, r5, r3, lsl #16
     1d8:	fb08 f30c 	mul.w	r3, r8, ip
     1dc:	42ab      	cmp	r3, r5
     1de:	d907      	bls.n	1f0 <CONFIG_NRF52_ANOMALY_132_DELAY_US+0xa6>
     1e0:	197d      	adds	r5, r7, r5
     1e2:	f10c 30ff 	add.w	r0, ip, #4294967295
     1e6:	d202      	bcs.n	1ee <CONFIG_NRF52_ANOMALY_132_DELAY_US+0xa4>
     1e8:	42ab      	cmp	r3, r5
     1ea:	f200 80e7 	bhi.w	3bc <CONFIG_FLASH_SIZE+0x1bc>
     1ee:	4684      	mov	ip, r0
     1f0:	1aed      	subs	r5, r5, r3
     1f2:	b2a3      	uxth	r3, r4
     1f4:	fbb5 f0fe 	udiv	r0, r5, lr
     1f8:	fb0e 5510 	mls	r5, lr, r0, r5
     1fc:	ea43 4405 	orr.w	r4, r3, r5, lsl #16
     200:	fb08 f800 	mul.w	r8, r8, r0
     204:	45a0      	cmp	r8, r4
     206:	d907      	bls.n	218 <CONFIG_FLASH_SIZE+0x18>
     208:	193c      	adds	r4, r7, r4
     20a:	f100 33ff 	add.w	r3, r0, #4294967295
     20e:	d202      	bcs.n	216 <CONFIG_FLASH_SIZE+0x16>
     210:	45a0      	cmp	r8, r4
     212:	f200 80d7 	bhi.w	3c4 <CONFIG_FLASH_SIZE+0x1c4>
     216:	4618      	mov	r0, r3
     218:	eba4 0408 	sub.w	r4, r4, r8
     21c:	ea40 400c 	orr.w	r0, r0, ip, lsl #16
     220:	e7c0      	b.n	1a4 <CONFIG_NRF52_ANOMALY_132_DELAY_US+0x5a>
     222:	428b      	cmp	r3, r1
     224:	d908      	bls.n	238 <CONFIG_FLASH_SIZE+0x38>
     226:	2e00      	cmp	r6, #0
     228:	f000 80af 	beq.w	38a <CONFIG_FLASH_SIZE+0x18a>
     22c:	2100      	movs	r1, #0
     22e:	e9c6 0500 	strd	r0, r5, [r6]
     232:	4608      	mov	r0, r1
     234:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
     238:	fab3 f183 	clz	r1, r3
     23c:	2900      	cmp	r1, #0
     23e:	d14b      	bne.n	2d8 <CONFIG_FLASH_SIZE+0xd8>
     240:	42ab      	cmp	r3, r5
     242:	d302      	bcc.n	24a <CONFIG_FLASH_SIZE+0x4a>
     244:	4282      	cmp	r2, r0
     246:	f200 80b7 	bhi.w	3b8 <CONFIG_FLASH_SIZE+0x1b8>
     24a:	1a84      	subs	r4, r0, r2
     24c:	eb65 0303 	sbc.w	r3, r5, r3
     250:	2001      	movs	r0, #1
     252:	469e      	mov	lr, r3
     254:	2e00      	cmp	r6, #0
     256:	d0aa      	beq.n	1ae <CONFIG_NRF52_ANOMALY_132_DELAY_US+0x64>
     258:	e9c6 4e00 	strd	r4, lr, [r6]
     25c:	e7a7      	b.n	1ae <CONFIG_NRF52_ANOMALY_132_DELAY_US+0x64>
     25e:	f1c2 0c20 	rsb	ip, r2, #32
     262:	fa01 f302 	lsl.w	r3, r1, r2
     266:	4097      	lsls	r7, r2
     268:	fa20 f00c 	lsr.w	r0, r0, ip
     26c:	ea4f 4e17 	mov.w	lr, r7, lsr #16
     270:	fa21 fc0c 	lsr.w	ip, r1, ip
     274:	4318      	orrs	r0, r3
     276:	fbbc f1fe 	udiv	r1, ip, lr
     27a:	0c05      	lsrs	r5, r0, #16
     27c:	fb0e cc11 	mls	ip, lr, r1, ip
     280:	fa1f f887 	uxth.w	r8, r7
     284:	ea45 450c 	orr.w	r5, r5, ip, lsl #16
     288:	fb01 f308 	mul.w	r3, r1, r8
     28c:	42ab      	cmp	r3, r5
     28e:	fa04 f402 	lsl.w	r4, r4, r2
     292:	d909      	bls.n	2a8 <CONFIG_FLASH_SIZE+0xa8>
     294:	197d      	adds	r5, r7, r5
     296:	f101 3cff 	add.w	ip, r1, #4294967295
     29a:	f080 808b 	bcs.w	3b4 <CONFIG_FLASH_SIZE+0x1b4>
     29e:	42ab      	cmp	r3, r5
     2a0:	f240 8088 	bls.w	3b4 <CONFIG_FLASH_SIZE+0x1b4>
     2a4:	3902      	subs	r1, #2
     2a6:	443d      	add	r5, r7
     2a8:	1aeb      	subs	r3, r5, r3
     2aa:	b285      	uxth	r5, r0
     2ac:	fbb3 f0fe 	udiv	r0, r3, lr
     2b0:	fb0e 3310 	mls	r3, lr, r0, r3
     2b4:	ea45 4503 	orr.w	r5, r5, r3, lsl #16
     2b8:	fb00 f308 	mul.w	r3, r0, r8
     2bc:	42ab      	cmp	r3, r5
     2be:	d907      	bls.n	2d0 <CONFIG_FLASH_SIZE+0xd0>
     2c0:	197d      	adds	r5, r7, r5
     2c2:	f100 3cff 	add.w	ip, r0, #4294967295
     2c6:	d271      	bcs.n	3ac <CONFIG_FLASH_SIZE+0x1ac>
     2c8:	42ab      	cmp	r3, r5
     2ca:	d96f      	bls.n	3ac <CONFIG_FLASH_SIZE+0x1ac>
     2cc:	3802      	subs	r0, #2
     2ce:	443d      	add	r5, r7
     2d0:	1aeb      	subs	r3, r5, r3
     2d2:	ea40 4101 	orr.w	r1, r0, r1, lsl #16
     2d6:	e778      	b.n	1ca <CONFIG_NRF52_ANOMALY_132_DELAY_US+0x80>
     2d8:	f1c1 0c20 	rsb	ip, r1, #32
     2dc:	408b      	lsls	r3, r1
     2de:	fa22 f70c 	lsr.w	r7, r2, ip
     2e2:	431f      	orrs	r7, r3
     2e4:	fa20 f40c 	lsr.w	r4, r0, ip
     2e8:	fa05 f301 	lsl.w	r3, r5, r1
     2ec:	ea4f 4e17 	mov.w	lr, r7, lsr #16
     2f0:	fa25 f50c 	lsr.w	r5, r5, ip
     2f4:	431c      	orrs	r4, r3
     2f6:	0c23      	lsrs	r3, r4, #16
     2f8:	fbb5 f9fe 	udiv	r9, r5, lr
     2fc:	fa1f f887 	uxth.w	r8, r7
     300:	fb0e 5519 	mls	r5, lr, r9, r5
     304:	ea43 4505 	orr.w	r5, r3, r5, lsl #16
     308:	fb09 fa08 	mul.w	sl, r9, r8
     30c:	45aa      	cmp	sl, r5
     30e:	fa02 f201 	lsl.w	r2, r2, r1
     312:	fa00 f301 	lsl.w	r3, r0, r1
     316:	d908      	bls.n	32a <CONFIG_FLASH_SIZE+0x12a>
     318:	197d      	adds	r5, r7, r5
     31a:	f109 30ff 	add.w	r0, r9, #4294967295
     31e:	d247      	bcs.n	3b0 <CONFIG_FLASH_SIZE+0x1b0>
     320:	45aa      	cmp	sl, r5
     322:	d945      	bls.n	3b0 <CONFIG_FLASH_SIZE+0x1b0>
     324:	f1a9 0902 	sub.w	r9, r9, #2
     328:	443d      	add	r5, r7
     32a:	eba5 050a 	sub.w	r5, r5, sl
     32e:	b2a4      	uxth	r4, r4
     330:	fbb5 f0fe 	udiv	r0, r5, lr
     334:	fb0e 5510 	mls	r5, lr, r0, r5
     338:	ea44 4405 	orr.w	r4, r4, r5, lsl #16
     33c:	fb00 f808 	mul.w	r8, r0, r8
     340:	45a0      	cmp	r8, r4
     342:	d907      	bls.n	354 <CONFIG_FLASH_SIZE+0x154>
     344:	193c      	adds	r4, r7, r4
     346:	f100 35ff 	add.w	r5, r0, #4294967295
     34a:	d22d      	bcs.n	3a8 <CONFIG_FLASH_SIZE+0x1a8>
     34c:	45a0      	cmp	r8, r4
     34e:	d92b      	bls.n	3a8 <CONFIG_FLASH_SIZE+0x1a8>
     350:	3802      	subs	r0, #2
     352:	443c      	add	r4, r7
     354:	ea40 4009 	orr.w	r0, r0, r9, lsl #16
     358:	eba4 0408 	sub.w	r4, r4, r8
     35c:	fba0 8902 	umull	r8, r9, r0, r2
     360:	454c      	cmp	r4, r9
     362:	46c6      	mov	lr, r8
     364:	464d      	mov	r5, r9
     366:	d319      	bcc.n	39c <CONFIG_FLASH_SIZE+0x19c>
     368:	d016      	beq.n	398 <CONFIG_FLASH_SIZE+0x198>
     36a:	b15e      	cbz	r6, 384 <CONFIG_FLASH_SIZE+0x184>
     36c:	ebb3 020e 	subs.w	r2, r3, lr
     370:	eb64 0405 	sbc.w	r4, r4, r5
     374:	fa04 fc0c 	lsl.w	ip, r4, ip
     378:	40ca      	lsrs	r2, r1
     37a:	ea4c 0202 	orr.w	r2, ip, r2
     37e:	40cc      	lsrs	r4, r1
     380:	e9c6 2400 	strd	r2, r4, [r6]
     384:	2100      	movs	r1, #0
     386:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
     38a:	4631      	mov	r1, r6
     38c:	4630      	mov	r0, r6
     38e:	e70e      	b.n	1ae <CONFIG_NRF52_ANOMALY_132_DELAY_US+0x64>
     390:	46ac      	mov	ip, r5
     392:	e6ed      	b.n	170 <CONFIG_NRF52_ANOMALY_132_DELAY_US+0x26>
     394:	4618      	mov	r0, r3
     396:	e701      	b.n	19c <CONFIG_NRF52_ANOMALY_132_DELAY_US+0x52>
     398:	4543      	cmp	r3, r8
     39a:	d2e6      	bcs.n	36a <CONFIG_FLASH_SIZE+0x16a>
     39c:	ebb8 0e02 	subs.w	lr, r8, r2
     3a0:	eb69 0507 	sbc.w	r5, r9, r7
     3a4:	3801      	subs	r0, #1
     3a6:	e7e0      	b.n	36a <CONFIG_FLASH_SIZE+0x16a>
     3a8:	4628      	mov	r0, r5
     3aa:	e7d3      	b.n	354 <CONFIG_FLASH_SIZE+0x154>
     3ac:	4660      	mov	r0, ip
     3ae:	e78f      	b.n	2d0 <CONFIG_FLASH_SIZE+0xd0>
     3b0:	4681      	mov	r9, r0
     3b2:	e7ba      	b.n	32a <CONFIG_FLASH_SIZE+0x12a>
     3b4:	4661      	mov	r1, ip
     3b6:	e777      	b.n	2a8 <CONFIG_FLASH_SIZE+0xa8>
     3b8:	4608      	mov	r0, r1
     3ba:	e74b      	b.n	254 <CONFIG_FLASH_SIZE+0x54>
     3bc:	f1ac 0c02 	sub.w	ip, ip, #2
     3c0:	443d      	add	r5, r7
     3c2:	e715      	b.n	1f0 <CONFIG_NRF52_ANOMALY_132_DELAY_US+0xa6>
     3c4:	3802      	subs	r0, #2
     3c6:	443c      	add	r4, r7
     3c8:	e726      	b.n	218 <CONFIG_FLASH_SIZE+0x18>
     3ca:	bf00      	nop

000003cc <__aeabi_idiv0>:
     3cc:	4770      	bx	lr
     3ce:	bf00      	nop

000003d0 <main>:
void main(void)
{

//NRF_P0->PIN_CNF[29] = GPIO_PIN_CNF_MCUSEL_NetworkMCU << GPIO_PIN_CNF_MCUSEL_Pos;

	printk("Hello World!\n");
     3d0:	4801      	ldr	r0, [pc, #4]	; (3d8 <main+0x8>)
     3d2:	f003 be85 	b.w	40e0 <printk>
     3d6:	bf00      	nop
     3d8:	00004ee8 	.word	0x00004ee8

000003dc <char_out>:

static int char_out(int c, void *ctx_p)
{
	struct out_context *ctx = ctx_p;

	ctx->count++;
     3dc:	680b      	ldr	r3, [r1, #0]
     3de:	3301      	adds	r3, #1
     3e0:	600b      	str	r3, [r1, #0]
	return _char_out(c);
     3e2:	4b01      	ldr	r3, [pc, #4]	; (3e8 <char_out+0xc>)
     3e4:	681b      	ldr	r3, [r3, #0]
     3e6:	4718      	bx	r3
     3e8:	20000000 	.word	0x20000000

000003ec <__printk_hook_install>:
	_char_out = fn;
     3ec:	4b01      	ldr	r3, [pc, #4]	; (3f4 <__printk_hook_install+0x8>)
     3ee:	6018      	str	r0, [r3, #0]
}
     3f0:	4770      	bx	lr
     3f2:	bf00      	nop
     3f4:	20000000 	.word	0x20000000

000003f8 <vprintk>:
#endif
	}
}
#else
void vprintk(const char *fmt, va_list ap)
{
     3f8:	b507      	push	{r0, r1, r2, lr}
     3fa:	460b      	mov	r3, r1
	struct out_context ctx = { 0 };
     3fc:	2100      	movs	r1, #0
{
     3fe:	4602      	mov	r2, r0
	struct out_context ctx = { 0 };
     400:	9101      	str	r1, [sp, #4]
#ifdef CONFIG_PRINTK_SYNC
	k_spinlock_key_t key = k_spin_lock(&lock);
#endif

	cbvprintf(char_out, &ctx, fmt, ap);
     402:	4803      	ldr	r0, [pc, #12]	; (410 <CONFIG_MAIN_STACK_SIZE+0x10>)
     404:	a901      	add	r1, sp, #4
     406:	f000 f8eb 	bl	5e0 <cbvprintf>

#ifdef CONFIG_PRINTK_SYNC
	k_spin_unlock(&lock, key);
#endif
}
     40a:	b003      	add	sp, #12
     40c:	f85d fb04 	ldr.w	pc, [sp], #4
     410:	000003dd 	.word	0x000003dd

00000414 <process_event>:
 * regions.
 */
static void process_event(struct onoff_manager *mgr,
			  int evt,
			  k_spinlock_key_t key)
{
     414:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
	sys_slist_t clients;
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     418:	f8b0 9018 	ldrh.w	r9, [r0, #24]
	__ASSERT_NO_MSG(evt != EVT_NOP);

	/* If this is a nested call record the event for processing in
	 * the top invocation.
	 */
	if (processing) {
     41c:	f019 0808 	ands.w	r8, r9, #8
{
     420:	4604      	mov	r4, r0
     422:	4693      	mov	fp, r2
	if (processing) {
     424:	d00d      	beq.n	442 <process_event+0x2e>
		if (evt == EVT_COMPLETE) {
     426:	2901      	cmp	r1, #1
			mgr->flags |= ONOFF_FLAG_COMPLETE;
     428:	bf0c      	ite	eq
     42a:	f049 0910 	orreq.w	r9, r9, #16
		} else {
			__ASSERT_NO_MSG(evt == EVT_RECHECK);

			mgr->flags |= ONOFF_FLAG_RECHECK;
     42e:	f049 0920 	orrne.w	r9, r9, #32
     432:	f8a0 9018 	strh.w	r9, [r0, #24]
	__asm__ volatile(
		"cpsie i;"
		"isb"
		: : : "memory");
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	__asm__ volatile(
     436:	f38b 8811 	msr	BASEPRI, fp
     43a:	f3bf 8f6f 	isb	sy
		state = mgr->flags & ONOFF_STATE_MASK;
	} while (evt != EVT_NOP);

out:
	k_spin_unlock(&mgr->lock, key);
}
     43e:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     442:	f009 0907 	and.w	r9, r9, #7
		if (evt == EVT_RECHECK) {
     446:	2902      	cmp	r1, #2
     448:	d107      	bne.n	45a <process_event+0x46>
			evt = process_recheck(mgr);
     44a:	4620      	mov	r0, r4
     44c:	f003 fe55 	bl	40fa <process_recheck>
		if (evt == EVT_NOP) {
     450:	2800      	cmp	r0, #0
     452:	d0f0      	beq.n	436 <process_event+0x22>
		if (evt == EVT_COMPLETE) {
     454:	2801      	cmp	r0, #1
     456:	8b23      	ldrh	r3, [r4, #24]
     458:	d150      	bne.n	4fc <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x14>
			res = mgr->last_res;
     45a:	6967      	ldr	r7, [r4, #20]
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     45c:	8b21      	ldrh	r1, [r4, #24]
	if (res < 0) {
     45e:	2f00      	cmp	r7, #0
     460:	da15      	bge.n	48e <process_event+0x7a>
		*clients = mgr->clients;
     462:	6825      	ldr	r5, [r4, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     464:	f021 0107 	bic.w	r1, r1, #7
 * @param list A pointer on the list to initialize
 */
static inline void sys_slist_init(sys_slist_t *list)
{
	list->head = NULL;
	list->tail = NULL;
     468:	e9c4 8800 	strd	r8, r8, [r4]
     46c:	f041 0101 	orr.w	r1, r1, #1
	mgr->flags = (state & ONOFF_STATE_MASK)
     470:	8321      	strh	r1, [r4, #24]
		onoff_transition_fn transit = NULL;
     472:	2600      	movs	r6, #0
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     474:	8b21      	ldrh	r1, [r4, #24]
     476:	f001 0a07 	and.w	sl, r1, #7
				   && !sys_slist_is_empty(&mgr->monitors);
     47a:	45ca      	cmp	sl, r9
     47c:	d002      	beq.n	484 <process_event+0x70>
		if (do_monitors
     47e:	68a3      	ldr	r3, [r4, #8]
     480:	2b00      	cmp	r3, #0
     482:	d15c      	bne.n	53e <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x56>
		    || !sys_slist_is_empty(&clients)
     484:	b90d      	cbnz	r5, 48a <process_event+0x76>
		    || (transit != NULL)) {
     486:	2e00      	cmp	r6, #0
     488:	d074      	beq.n	574 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x8c>
     48a:	2300      	movs	r3, #0
     48c:	e058      	b.n	540 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x58>
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     48e:	f001 0307 	and.w	r3, r1, #7
		   || (state == ONOFF_STATE_RESETTING)) {
     492:	1f5a      	subs	r2, r3, #5
	} else if ((state == ONOFF_STATE_TO_ON)
     494:	2a01      	cmp	r2, #1
     496:	d820      	bhi.n	4da <process_event+0xc6>
		*clients = mgr->clients;
     498:	f021 0107 	bic.w	r1, r1, #7
		if (state == ONOFF_STATE_TO_ON) {
     49c:	2b06      	cmp	r3, #6
		*clients = mgr->clients;
     49e:	6825      	ldr	r5, [r4, #0]
	list->head = NULL;
     4a0:	b289      	uxth	r1, r1
	list->tail = NULL;
     4a2:	e9c4 8800 	strd	r8, r8, [r4]
		if (state == ONOFF_STATE_TO_ON) {
     4a6:	d10c      	bne.n	4c2 <process_event+0xae>
 *
 * @return A pointer on the first node of the list (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_head(sys_slist_t *list)
{
	return list->head;
     4a8:	2d00      	cmp	r5, #0
     4aa:	462b      	mov	r3, r5
     4ac:	bf38      	it	cc
     4ae:	2300      	movcc	r3, #0
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
     4b0:	b12b      	cbz	r3, 4be <process_event+0xaa>
				mgr->refs += 1U;
     4b2:	8b62      	ldrh	r2, [r4, #26]
 *
 * @return a pointer on the next node (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_next_no_check(sys_snode_t *node);

Z_GENLIST_PEEK_NEXT_NO_CHECK(slist, snode)
     4b4:	681b      	ldr	r3, [r3, #0]
     4b6:	3201      	adds	r2, #1
     4b8:	8362      	strh	r2, [r4, #26]
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
     4ba:	2b00      	cmp	r3, #0
     4bc:	d1f8      	bne.n	4b0 <process_event+0x9c>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     4be:	f041 0102 	orr.w	r1, r1, #2
	mgr->flags = (state & ONOFF_STATE_MASK)
     4c2:	8321      	strh	r1, [r4, #24]
		if (process_recheck(mgr) != EVT_NOP) {
     4c4:	4620      	mov	r0, r4
     4c6:	f003 fe18 	bl	40fa <process_recheck>
     4ca:	4606      	mov	r6, r0
     4cc:	2800      	cmp	r0, #0
     4ce:	d0d1      	beq.n	474 <process_event+0x60>
			mgr->flags |= ONOFF_FLAG_RECHECK;
     4d0:	8b23      	ldrh	r3, [r4, #24]
     4d2:	f043 0320 	orr.w	r3, r3, #32
     4d6:	8323      	strh	r3, [r4, #24]
     4d8:	e7cb      	b.n	472 <process_event+0x5e>
	} else if (state == ONOFF_STATE_TO_OFF) {
     4da:	2b04      	cmp	r3, #4
     4dc:	d10c      	bne.n	4f8 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x10>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     4de:	f021 0107 	bic.w	r1, r1, #7
     4e2:	b289      	uxth	r1, r1
	mgr->flags = (state & ONOFF_STATE_MASK)
     4e4:	8321      	strh	r1, [r4, #24]
		if (process_recheck(mgr) != EVT_NOP) {
     4e6:	4620      	mov	r0, r4
     4e8:	f003 fe07 	bl	40fa <process_recheck>
     4ec:	4605      	mov	r5, r0
     4ee:	2800      	cmp	r0, #0
     4f0:	d0bf      	beq.n	472 <process_event+0x5e>
			mgr->flags |= ONOFF_FLAG_RECHECK;
     4f2:	f041 0120 	orr.w	r1, r1, #32
     4f6:	8321      	strh	r1, [r4, #24]
     4f8:	2500      	movs	r5, #0
     4fa:	e7ba      	b.n	472 <process_event+0x5e>
		} else if (evt == EVT_START) {
     4fc:	2803      	cmp	r0, #3
     4fe:	d109      	bne.n	514 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x2c>
			transit = mgr->transitions->start;
     500:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     502:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->start;
     506:	6816      	ldr	r6, [r2, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     508:	f043 0306 	orr.w	r3, r3, #6
	mgr->flags = (state & ONOFF_STATE_MASK)
     50c:	8323      	strh	r3, [r4, #24]
}
     50e:	2500      	movs	r5, #0
		res = 0;
     510:	462f      	mov	r7, r5
     512:	e7af      	b.n	474 <process_event+0x60>
		} else if (evt == EVT_STOP) {
     514:	2804      	cmp	r0, #4
     516:	d106      	bne.n	526 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x3e>
			transit = mgr->transitions->stop;
     518:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     51a:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->stop;
     51e:	6856      	ldr	r6, [r2, #4]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     520:	f043 0304 	orr.w	r3, r3, #4
     524:	e7f2      	b.n	50c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x24>
		} else if (evt == EVT_RESET) {
     526:	2805      	cmp	r0, #5
     528:	d106      	bne.n	538 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x50>
			transit = mgr->transitions->reset;
     52a:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     52c:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->reset;
     530:	6896      	ldr	r6, [r2, #8]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     532:	f043 0305 	orr.w	r3, r3, #5
     536:	e7e9      	b.n	50c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x24>
     538:	2500      	movs	r5, #0
		onoff_transition_fn transit = NULL;
     53a:	462e      	mov	r6, r5
     53c:	e7e8      	b.n	510 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x28>
				   && !sys_slist_is_empty(&mgr->monitors);
     53e:	2301      	movs	r3, #1
			uint32_t flags = mgr->flags | ONOFF_FLAG_PROCESSING;
     540:	f041 0108 	orr.w	r1, r1, #8
			mgr->flags = flags;
     544:	8321      	strh	r1, [r4, #24]
     546:	f38b 8811 	msr	BASEPRI, fp
     54a:	f3bf 8f6f 	isb	sy
			if (do_monitors) {
     54e:	bb03      	cbnz	r3, 592 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xaa>
	while (!sys_slist_is_empty(list)) {
     550:	2d00      	cmp	r5, #0
     552:	d133      	bne.n	5bc <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xd4>
			if (transit != NULL) {
     554:	b116      	cbz	r6, 55c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x74>
				transit(mgr, transition_complete);
     556:	4921      	ldr	r1, [pc, #132]	; (5dc <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xf4>)
     558:	4620      	mov	r0, r4
     55a:	47b0      	blx	r6
	__asm__ volatile(
     55c:	f04f 0320 	mov.w	r3, #32
     560:	f3ef 8b11 	mrs	fp, BASEPRI
     564:	f383 8812 	msr	BASEPRI_MAX, r3
     568:	f3bf 8f6f 	isb	sy
			mgr->flags &= ~ONOFF_FLAG_PROCESSING;
     56c:	8b23      	ldrh	r3, [r4, #24]
     56e:	f023 0308 	bic.w	r3, r3, #8
     572:	8323      	strh	r3, [r4, #24]
		if ((mgr->flags & ONOFF_FLAG_COMPLETE) != 0) {
     574:	8b23      	ldrh	r3, [r4, #24]
     576:	06da      	lsls	r2, r3, #27
     578:	d528      	bpl.n	5cc <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xe4>
			mgr->flags &= ~ONOFF_FLAG_COMPLETE;
     57a:	f023 0310 	bic.w	r3, r3, #16
     57e:	8323      	strh	r3, [r4, #24]
			evt = EVT_COMPLETE;
     580:	2101      	movs	r1, #1
		state = mgr->flags & ONOFF_STATE_MASK;
     582:	f8b4 9018 	ldrh.w	r9, [r4, #24]
     586:	f009 0907 	and.w	r9, r9, #7
	} while (evt != EVT_NOP);
     58a:	2900      	cmp	r1, #0
     58c:	f47f af5b 	bne.w	446 <process_event+0x32>
out:
     590:	e751      	b.n	436 <process_event+0x22>
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
     592:	68a1      	ldr	r1, [r4, #8]
     594:	2900      	cmp	r1, #0
     596:	d0db      	beq.n	550 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x68>
	return node->next;
     598:	680b      	ldr	r3, [r1, #0]
		mon->callback(mgr, mon, state, res);
     59a:	f8d1 b004 	ldr.w	fp, [r1, #4]
     59e:	2b00      	cmp	r3, #0
     5a0:	bf38      	it	cc
     5a2:	2300      	movcc	r3, #0
     5a4:	4699      	mov	r9, r3
     5a6:	4652      	mov	r2, sl
     5a8:	463b      	mov	r3, r7
     5aa:	4620      	mov	r0, r4
     5ac:	47d8      	blx	fp
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
     5ae:	f1b9 0f00 	cmp.w	r9, #0
     5b2:	d0cd      	beq.n	550 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x68>
     5b4:	f8d9 3000 	ldr.w	r3, [r9]
Z_GENLIST_PEEK_NEXT_NO_CHECK(slist, snode)
     5b8:	4649      	mov	r1, r9
     5ba:	e7ee      	b.n	59a <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xb2>
 *
 * @return A pointer to the first node of the list
 */
static inline sys_snode_t *sys_slist_get_not_empty(sys_slist_t *list);

Z_GENLIST_GET_NOT_EMPTY(slist, snode)
     5bc:	4629      	mov	r1, r5
		notify_one(mgr, cli, state, res);
     5be:	463b      	mov	r3, r7
     5c0:	4652      	mov	r2, sl
     5c2:	4620      	mov	r0, r4
     5c4:	682d      	ldr	r5, [r5, #0]
     5c6:	f003 fdb4 	bl	4132 <notify_one>
     5ca:	e7c1      	b.n	550 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x68>
		} else if ((mgr->flags & ONOFF_FLAG_RECHECK) != 0) {
     5cc:	f013 0120 	ands.w	r1, r3, #32
			mgr->flags &= ~ONOFF_FLAG_RECHECK;
     5d0:	bf1e      	ittt	ne
     5d2:	f023 0320 	bicne.w	r3, r3, #32
     5d6:	8323      	strhne	r3, [r4, #24]
			evt = EVT_RECHECK;
     5d8:	2102      	movne	r1, #2
     5da:	e7d2      	b.n	582 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x9a>
     5dc:	0000415f 	.word	0x0000415f

000005e0 <cbvprintf>:

	return (int)count;
}

int cbvprintf(cbprintf_cb out, void *ctx, const char *fp, va_list ap)
{
     5e0:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     5e4:	b091      	sub	sp, #68	; 0x44
     5e6:	468b      	mov	fp, r1
     5e8:	9002      	str	r0, [sp, #8]
     5ea:	4692      	mov	sl, r2
     5ec:	461c      	mov	r4, r3
	char buf[CONVERTED_BUFLEN];
	size_t count = 0;
     5ee:	2500      	movs	r5, #0
		return rc; \
	} \
	count += rc; \
} while (false)

	while (*fp != 0) {
     5f0:	f89a 0000 	ldrb.w	r0, [sl]
     5f4:	b908      	cbnz	r0, 5fa <cbvprintf+0x1a>
			OUTC(' ');
			--width;
		}
	}

	return count;
     5f6:	4628      	mov	r0, r5
     5f8:	e35e      	b.n	cb8 <CONFIG_ISR_STACK_SIZE+0x4b8>
		if (*fp != '%') {
     5fa:	2825      	cmp	r0, #37	; 0x25
     5fc:	f10a 0701 	add.w	r7, sl, #1
     600:	d007      	beq.n	612 <cbvprintf+0x32>
			OUTC('%');
     602:	9b02      	ldr	r3, [sp, #8]
     604:	4659      	mov	r1, fp
     606:	4798      	blx	r3
     608:	2800      	cmp	r0, #0
     60a:	f2c0 8355 	blt.w	cb8 <CONFIG_ISR_STACK_SIZE+0x4b8>
     60e:	3501      	adds	r5, #1
			break;
     610:	e210      	b.n	a34 <CONFIG_ISR_STACK_SIZE+0x234>
		} state = {
     612:	2218      	movs	r2, #24
     614:	2100      	movs	r1, #0
     616:	a80a      	add	r0, sp, #40	; 0x28
     618:	f003 fec1 	bl	439e <memset>
	if (*sp == '%') {
     61c:	f89a 3001 	ldrb.w	r3, [sl, #1]
     620:	2b25      	cmp	r3, #37	; 0x25
     622:	d078      	beq.n	716 <cbvprintf+0x136>
     624:	2200      	movs	r2, #0
     626:	4694      	mov	ip, r2
     628:	4616      	mov	r6, r2
     62a:	4696      	mov	lr, r2
     62c:	4610      	mov	r0, r2
     62e:	4639      	mov	r1, r7
		switch (*sp) {
     630:	f817 3b01 	ldrb.w	r3, [r7], #1
     634:	2b2b      	cmp	r3, #43	; 0x2b
     636:	f000 809d 	beq.w	774 <cbvprintf+0x194>
     63a:	f200 8094 	bhi.w	766 <cbvprintf+0x186>
     63e:	2b20      	cmp	r3, #32
     640:	f000 809b 	beq.w	77a <cbvprintf+0x19a>
     644:	2b23      	cmp	r3, #35	; 0x23
     646:	f000 809a 	beq.w	77e <cbvprintf+0x19e>
     64a:	b128      	cbz	r0, 658 <cbvprintf+0x78>
     64c:	f89d 0030 	ldrb.w	r0, [sp, #48]	; 0x30
     650:	f040 0004 	orr.w	r0, r0, #4
     654:	f88d 0030 	strb.w	r0, [sp, #48]	; 0x30
     658:	f1be 0f00 	cmp.w	lr, #0
     65c:	d005      	beq.n	66a <cbvprintf+0x8a>
     65e:	f89d 0030 	ldrb.w	r0, [sp, #48]	; 0x30
     662:	f040 0008 	orr.w	r0, r0, #8
     666:	f88d 0030 	strb.w	r0, [sp, #48]	; 0x30
     66a:	b12e      	cbz	r6, 678 <cbvprintf+0x98>
     66c:	f89d 0030 	ldrb.w	r0, [sp, #48]	; 0x30
     670:	f040 0010 	orr.w	r0, r0, #16
     674:	f88d 0030 	strb.w	r0, [sp, #48]	; 0x30
     678:	f1bc 0f00 	cmp.w	ip, #0
     67c:	d005      	beq.n	68a <cbvprintf+0xaa>
     67e:	f89d 0030 	ldrb.w	r0, [sp, #48]	; 0x30
     682:	f040 0020 	orr.w	r0, r0, #32
     686:	f88d 0030 	strb.w	r0, [sp, #48]	; 0x30
     68a:	b12a      	cbz	r2, 698 <cbvprintf+0xb8>
     68c:	f89d 2030 	ldrb.w	r2, [sp, #48]	; 0x30
     690:	f042 0240 	orr.w	r2, r2, #64	; 0x40
     694:	f88d 2030 	strb.w	r2, [sp, #48]	; 0x30
	if (conv->flag_zero && conv->flag_dash) {
     698:	f89d 2030 	ldrb.w	r2, [sp, #48]	; 0x30
     69c:	f002 0044 	and.w	r0, r2, #68	; 0x44
     6a0:	2844      	cmp	r0, #68	; 0x44
     6a2:	d103      	bne.n	6ac <cbvprintf+0xcc>
		conv->flag_zero = false;
     6a4:	f36f 1286 	bfc	r2, #6, #1
     6a8:	f88d 2030 	strb.w	r2, [sp, #48]	; 0x30
	conv->width_present = true;
     6ac:	f89d 2030 	ldrb.w	r2, [sp, #48]	; 0x30
	if (*sp == '*') {
     6b0:	2b2a      	cmp	r3, #42	; 0x2a
	conv->width_present = true;
     6b2:	f042 0280 	orr.w	r2, r2, #128	; 0x80
     6b6:	f88d 2030 	strb.w	r2, [sp, #48]	; 0x30
	if (*sp == '*') {
     6ba:	d17b      	bne.n	7b4 <cbvprintf+0x1d4>
		conv->width_star = true;
     6bc:	f89d 2031 	ldrb.w	r2, [sp, #49]	; 0x31
     6c0:	f042 0201 	orr.w	r2, r2, #1
     6c4:	1c4b      	adds	r3, r1, #1
     6c6:	f88d 2031 	strb.w	r2, [sp, #49]	; 0x31
	conv->prec_present = (*sp == '.');
     6ca:	781a      	ldrb	r2, [r3, #0]
     6cc:	2a2e      	cmp	r2, #46	; 0x2e
     6ce:	f89d 2031 	ldrb.w	r2, [sp, #49]	; 0x31
     6d2:	bf0c      	ite	eq
     6d4:	2101      	moveq	r1, #1
     6d6:	2100      	movne	r1, #0
     6d8:	f361 0241 	bfi	r2, r1, #1, #1
     6dc:	f88d 2031 	strb.w	r2, [sp, #49]	; 0x31
	if (!conv->prec_present) {
     6e0:	d174      	bne.n	7cc <cbvprintf+0x1ec>
	if (*sp == '*') {
     6e2:	785a      	ldrb	r2, [r3, #1]
     6e4:	2a2a      	cmp	r2, #42	; 0x2a
     6e6:	d06a      	beq.n	7be <cbvprintf+0x1de>
     6e8:	3301      	adds	r3, #1
	size_t val = 0;
     6ea:	2100      	movs	r1, #0
		val = 10U * val + *sp++ - '0';
     6ec:	260a      	movs	r6, #10
			(((unsigned)c) <= (unsigned)'~'));
}

static inline int isdigit(int a)
{
	return (int)(((unsigned)(a)-(unsigned)'0') < 10U);
     6ee:	4618      	mov	r0, r3
     6f0:	f810 2b01 	ldrb.w	r2, [r0], #1
     6f4:	f1a2 0730 	sub.w	r7, r2, #48	; 0x30
	while (isdigit((int)(unsigned char)*sp)) {
     6f8:	2f09      	cmp	r7, #9
     6fa:	f240 808e 	bls.w	81a <CONFIG_ISR_STACK_SIZE+0x1a>
	conv->unsupported |= ((conv->prec_value < 0)
     6fe:	f89d 2030 	ldrb.w	r2, [sp, #48]	; 0x30
	conv->prec_value = prec;
     702:	910e      	str	r1, [sp, #56]	; 0x38
	conv->unsupported |= ((conv->prec_value < 0)
     704:	f3c2 0040 	ubfx	r0, r2, #1, #1
     708:	ea40 71d1 	orr.w	r1, r0, r1, lsr #31
     70c:	f361 0241 	bfi	r2, r1, #1, #1
     710:	f88d 2030 	strb.w	r2, [sp, #48]	; 0x30
	return sp;
     714:	e05a      	b.n	7cc <cbvprintf+0x1ec>
		conv->specifier = *sp++;
     716:	f10a 0702 	add.w	r7, sl, #2
     71a:	f88d 3033 	strb.w	r3, [sp, #51]	; 0x33
		if (conv->width_star) {
     71e:	f89d 3031 	ldrb.w	r3, [sp, #49]	; 0x31
     722:	07d9      	lsls	r1, r3, #31
     724:	f140 8149 	bpl.w	9ba <CONFIG_ISR_STACK_SIZE+0x1ba>
			width = va_arg(ap, int);
     728:	f854 9b04 	ldr.w	r9, [r4], #4
			if (width < 0) {
     72c:	f1b9 0f00 	cmp.w	r9, #0
     730:	da07      	bge.n	742 <cbvprintf+0x162>
				conv->flag_dash = true;
     732:	f89d 2030 	ldrb.w	r2, [sp, #48]	; 0x30
     736:	f042 0204 	orr.w	r2, r2, #4
     73a:	f88d 2030 	strb.w	r2, [sp, #48]	; 0x30
				width = -width;
     73e:	f1c9 0900 	rsb	r9, r9, #0
		if (conv->prec_star) {
     742:	075a      	lsls	r2, r3, #29
     744:	f140 8142 	bpl.w	9cc <CONFIG_ISR_STACK_SIZE+0x1cc>
			int arg = va_arg(ap, int);
     748:	f854 8b04 	ldr.w	r8, [r4], #4
			if (arg < 0) {
     74c:	f1b8 0f00 	cmp.w	r8, #0
     750:	f280 8141 	bge.w	9d6 <CONFIG_ISR_STACK_SIZE+0x1d6>
				conv->prec_present = false;
     754:	f89d 3031 	ldrb.w	r3, [sp, #49]	; 0x31
     758:	f36f 0341 	bfc	r3, #1, #1
     75c:	f88d 3031 	strb.w	r3, [sp, #49]	; 0x31
		int precision = -1;
     760:	f04f 38ff 	mov.w	r8, #4294967295
     764:	e137      	b.n	9d6 <CONFIG_ISR_STACK_SIZE+0x1d6>
		switch (*sp) {
     766:	2b2d      	cmp	r3, #45	; 0x2d
     768:	d00c      	beq.n	784 <cbvprintf+0x1a4>
     76a:	2b30      	cmp	r3, #48	; 0x30
     76c:	f47f af6d 	bne.w	64a <cbvprintf+0x6a>
			conv->flag_zero = true;
     770:	2201      	movs	r2, #1
	} while (loop);
     772:	e75c      	b.n	62e <cbvprintf+0x4e>
			conv->flag_plus = true;
     774:	f04f 0e01 	mov.w	lr, #1
     778:	e759      	b.n	62e <cbvprintf+0x4e>
			conv->flag_space = true;
     77a:	2601      	movs	r6, #1
     77c:	e757      	b.n	62e <cbvprintf+0x4e>
			conv->flag_hash = true;
     77e:	f04f 0c01 	mov.w	ip, #1
     782:	e754      	b.n	62e <cbvprintf+0x4e>
		switch (*sp) {
     784:	2001      	movs	r0, #1
     786:	e752      	b.n	62e <cbvprintf+0x4e>
		val = 10U * val + *sp++ - '0';
     788:	fb0c 0202 	mla	r2, ip, r2, r0
     78c:	3a30      	subs	r2, #48	; 0x30
     78e:	4633      	mov	r3, r6
     790:	461e      	mov	r6, r3
     792:	f816 0b01 	ldrb.w	r0, [r6], #1
     796:	f1a0 0730 	sub.w	r7, r0, #48	; 0x30
	while (isdigit((int)(unsigned char)*sp)) {
     79a:	2f09      	cmp	r7, #9
     79c:	d9f4      	bls.n	788 <cbvprintf+0x1a8>
	if (sp != wp) {
     79e:	4299      	cmp	r1, r3
     7a0:	d093      	beq.n	6ca <cbvprintf+0xea>
		conv->unsupported |= ((conv->width_value < 0)
     7a2:	f89d 1030 	ldrb.w	r1, [sp, #48]	; 0x30
		conv->width_value = width;
     7a6:	920d      	str	r2, [sp, #52]	; 0x34
				      || (width != (size_t)conv->width_value));
     7a8:	0fd2      	lsrs	r2, r2, #31
		conv->unsupported |= ((conv->width_value < 0)
     7aa:	f362 0141 	bfi	r1, r2, #1, #1
     7ae:	f88d 1030 	strb.w	r1, [sp, #48]	; 0x30
     7b2:	e78a      	b.n	6ca <cbvprintf+0xea>
     7b4:	460b      	mov	r3, r1
	size_t val = 0;
     7b6:	2200      	movs	r2, #0
		val = 10U * val + *sp++ - '0';
     7b8:	f04f 0c0a 	mov.w	ip, #10
     7bc:	e7e8      	b.n	790 <cbvprintf+0x1b0>
		conv->prec_star = true;
     7be:	f89d 2031 	ldrb.w	r2, [sp, #49]	; 0x31
     7c2:	f042 0204 	orr.w	r2, r2, #4
     7c6:	f88d 2031 	strb.w	r2, [sp, #49]	; 0x31
		return ++sp;
     7ca:	3302      	adds	r3, #2
	switch (*sp) {
     7cc:	461f      	mov	r7, r3
     7ce:	f817 2b01 	ldrb.w	r2, [r7], #1
     7d2:	2a6c      	cmp	r2, #108	; 0x6c
     7d4:	d041      	beq.n	85a <CONFIG_ISR_STACK_SIZE+0x5a>
     7d6:	d825      	bhi.n	824 <CONFIG_ISR_STACK_SIZE+0x24>
     7d8:	2a68      	cmp	r2, #104	; 0x68
     7da:	d02b      	beq.n	834 <CONFIG_ISR_STACK_SIZE+0x34>
     7dc:	2a6a      	cmp	r2, #106	; 0x6a
     7de:	d046      	beq.n	86e <CONFIG_ISR_STACK_SIZE+0x6e>
     7e0:	2a4c      	cmp	r2, #76	; 0x4c
     7e2:	d04c      	beq.n	87e <CONFIG_ISR_STACK_SIZE+0x7e>
     7e4:	461f      	mov	r7, r3
	conv->specifier = *sp++;
     7e6:	f817 2b01 	ldrb.w	r2, [r7], #1
     7ea:	f89d 3031 	ldrb.w	r3, [sp, #49]	; 0x31
     7ee:	f88d 2033 	strb.w	r2, [sp, #51]	; 0x33
	switch (conv->specifier) {
     7f2:	2a78      	cmp	r2, #120	; 0x78
     7f4:	f200 80d9 	bhi.w	9aa <CONFIG_ISR_STACK_SIZE+0x1aa>
     7f8:	2a57      	cmp	r2, #87	; 0x57
     7fa:	d84d      	bhi.n	898 <CONFIG_ISR_STACK_SIZE+0x98>
     7fc:	2a41      	cmp	r2, #65	; 0x41
     7fe:	d003      	beq.n	808 <CONFIG_ISR_STACK_SIZE+0x8>
     800:	3a45      	subs	r2, #69	; 0x45
     802:	2a02      	cmp	r2, #2
     804:	f200 80d1 	bhi.w	9aa <CONFIG_ISR_STACK_SIZE+0x1aa>
		conv->specifier_cat = SPECIFIER_FP;
     808:	f89d 3032 	ldrb.w	r3, [sp, #50]	; 0x32
     80c:	2204      	movs	r2, #4
     80e:	f362 0302 	bfi	r3, r2, #0, #3
     812:	f88d 3032 	strb.w	r3, [sp, #50]	; 0x32
			unsupported = true;
     816:	2301      	movs	r3, #1
			break;
     818:	e09e      	b.n	958 <CONFIG_ISR_STACK_SIZE+0x158>
		val = 10U * val + *sp++ - '0';
     81a:	fb06 2101 	mla	r1, r6, r1, r2
     81e:	3930      	subs	r1, #48	; 0x30
     820:	4603      	mov	r3, r0
     822:	e764      	b.n	6ee <cbvprintf+0x10e>
	switch (*sp) {
     824:	2a74      	cmp	r2, #116	; 0x74
     826:	d026      	beq.n	876 <CONFIG_ISR_STACK_SIZE+0x76>
     828:	2a7a      	cmp	r2, #122	; 0x7a
     82a:	d1db      	bne.n	7e4 <cbvprintf+0x204>
		conv->length_mod = LENGTH_Z;
     82c:	f89d 3031 	ldrb.w	r3, [sp, #49]	; 0x31
     830:	2206      	movs	r2, #6
     832:	e00d      	b.n	850 <CONFIG_ISR_STACK_SIZE+0x50>
		if (*++sp == 'h') {
     834:	785a      	ldrb	r2, [r3, #1]
     836:	2a68      	cmp	r2, #104	; 0x68
     838:	f89d 2031 	ldrb.w	r2, [sp, #49]	; 0x31
     83c:	d106      	bne.n	84c <CONFIG_ISR_STACK_SIZE+0x4c>
			conv->length_mod = LENGTH_HH;
     83e:	2101      	movs	r1, #1
			conv->length_mod = LENGTH_LL;
     840:	f361 02c6 	bfi	r2, r1, #3, #4
     844:	f88d 2031 	strb.w	r2, [sp, #49]	; 0x31
			++sp;
     848:	1c9f      	adds	r7, r3, #2
     84a:	e7cc      	b.n	7e6 <cbvprintf+0x206>
			conv->length_mod = LENGTH_H;
     84c:	4613      	mov	r3, r2
     84e:	2202      	movs	r2, #2
		conv->length_mod = LENGTH_T;
     850:	f362 03c6 	bfi	r3, r2, #3, #4
     854:	f88d 3031 	strb.w	r3, [sp, #49]	; 0x31
		break;
     858:	e7c5      	b.n	7e6 <cbvprintf+0x206>
		if (*++sp == 'l') {
     85a:	785a      	ldrb	r2, [r3, #1]
     85c:	2a6c      	cmp	r2, #108	; 0x6c
     85e:	f89d 2031 	ldrb.w	r2, [sp, #49]	; 0x31
     862:	d101      	bne.n	868 <CONFIG_ISR_STACK_SIZE+0x68>
			conv->length_mod = LENGTH_LL;
     864:	2104      	movs	r1, #4
     866:	e7eb      	b.n	840 <CONFIG_ISR_STACK_SIZE+0x40>
			conv->length_mod = LENGTH_L;
     868:	4613      	mov	r3, r2
     86a:	2203      	movs	r2, #3
     86c:	e7f0      	b.n	850 <CONFIG_ISR_STACK_SIZE+0x50>
		conv->length_mod = LENGTH_J;
     86e:	f89d 3031 	ldrb.w	r3, [sp, #49]	; 0x31
     872:	2205      	movs	r2, #5
     874:	e7ec      	b.n	850 <CONFIG_ISR_STACK_SIZE+0x50>
		conv->length_mod = LENGTH_T;
     876:	f89d 3031 	ldrb.w	r3, [sp, #49]	; 0x31
     87a:	2207      	movs	r2, #7
     87c:	e7e8      	b.n	850 <CONFIG_ISR_STACK_SIZE+0x50>
		conv->unsupported = true;
     87e:	f8bd 3030 	ldrh.w	r3, [sp, #48]	; 0x30
     882:	f423 43f0 	bic.w	r3, r3, #30720	; 0x7800
     886:	f023 0302 	bic.w	r3, r3, #2
     88a:	f443 4380 	orr.w	r3, r3, #16384	; 0x4000
     88e:	f043 0302 	orr.w	r3, r3, #2
     892:	f8ad 3030 	strh.w	r3, [sp, #48]	; 0x30
		break;
     896:	e7a6      	b.n	7e6 <cbvprintf+0x206>
     898:	f1a2 0158 	sub.w	r1, r2, #88	; 0x58
     89c:	2920      	cmp	r1, #32
     89e:	f200 8084 	bhi.w	9aa <CONFIG_ISR_STACK_SIZE+0x1aa>
     8a2:	a001      	add	r0, pc, #4	; (adr r0, 8a8 <CONFIG_ISR_STACK_SIZE+0xa8>)
     8a4:	f850 f021 	ldr.w	pc, [r0, r1, lsl #2]
     8a8:	0000096d 	.word	0x0000096d
     8ac:	000009ab 	.word	0x000009ab
     8b0:	000009ab 	.word	0x000009ab
     8b4:	000009ab 	.word	0x000009ab
     8b8:	000009ab 	.word	0x000009ab
     8bc:	000009ab 	.word	0x000009ab
     8c0:	000009ab 	.word	0x000009ab
     8c4:	000009ab 	.word	0x000009ab
     8c8:	000009ab 	.word	0x000009ab
     8cc:	00000809 	.word	0x00000809
     8d0:	000009ab 	.word	0x000009ab
     8d4:	0000096d 	.word	0x0000096d
     8d8:	0000092d 	.word	0x0000092d
     8dc:	00000809 	.word	0x00000809
     8e0:	00000809 	.word	0x00000809
     8e4:	00000809 	.word	0x00000809
     8e8:	000009ab 	.word	0x000009ab
     8ec:	0000092d 	.word	0x0000092d
     8f0:	000009ab 	.word	0x000009ab
     8f4:	000009ab 	.word	0x000009ab
     8f8:	000009ab 	.word	0x000009ab
     8fc:	000009ab 	.word	0x000009ab
     900:	00000975 	.word	0x00000975
     904:	0000096d 	.word	0x0000096d
     908:	00000991 	.word	0x00000991
     90c:	000009ab 	.word	0x000009ab
     910:	000009ab 	.word	0x000009ab
     914:	00000991 	.word	0x00000991
     918:	000009ab 	.word	0x000009ab
     91c:	0000096d 	.word	0x0000096d
     920:	000009ab 	.word	0x000009ab
     924:	000009ab 	.word	0x000009ab
     928:	0000096d 	.word	0x0000096d
		conv->specifier_cat = SPECIFIER_SINT;
     92c:	f89d 1032 	ldrb.w	r1, [sp, #50]	; 0x32
     930:	2001      	movs	r0, #1
		if (conv->length_mod == LENGTH_UPPER_L) {
     932:	f003 0378 	and.w	r3, r3, #120	; 0x78
		conv->specifier_cat = SPECIFIER_UINT;
     936:	f360 0102 	bfi	r1, r0, #0, #3
		if (conv->length_mod == LENGTH_UPPER_L) {
     93a:	2b40      	cmp	r3, #64	; 0x40
		conv->specifier_cat = SPECIFIER_UINT;
     93c:	f88d 1032 	strb.w	r1, [sp, #50]	; 0x32
			conv->invalid = true;
     940:	bf02      	ittt	eq
     942:	f89d 1030 	ldrbeq.w	r1, [sp, #48]	; 0x30
     946:	f041 0101 	orreq.w	r1, r1, #1
     94a:	f88d 1030 	strbeq.w	r1, [sp, #48]	; 0x30
		if (conv->specifier == 'c') {
     94e:	2a63      	cmp	r2, #99	; 0x63
     950:	d131      	bne.n	9b6 <CONFIG_ISR_STACK_SIZE+0x1b6>
			unsupported = (conv->length_mod != LENGTH_NONE);
     952:	3b00      	subs	r3, #0
     954:	bf18      	it	ne
     956:	2301      	movne	r3, #1
	conv->unsupported |= unsupported;
     958:	f89d 2030 	ldrb.w	r2, [sp, #48]	; 0x30
     95c:	f3c2 0140 	ubfx	r1, r2, #1, #1
     960:	430b      	orrs	r3, r1
     962:	f363 0241 	bfi	r2, r3, #1, #1
     966:	f88d 2030 	strb.w	r2, [sp, #48]	; 0x30
	return sp;
     96a:	e6d8      	b.n	71e <cbvprintf+0x13e>
		conv->specifier_cat = SPECIFIER_UINT;
     96c:	f89d 1032 	ldrb.w	r1, [sp, #50]	; 0x32
     970:	2002      	movs	r0, #2
     972:	e7de      	b.n	932 <CONFIG_ISR_STACK_SIZE+0x132>
		conv->specifier_cat = SPECIFIER_PTR;
     974:	f89d 2032 	ldrb.w	r2, [sp, #50]	; 0x32
		if (conv->length_mod == LENGTH_UPPER_L) {
     978:	f003 0378 	and.w	r3, r3, #120	; 0x78
     97c:	f1a3 0040 	sub.w	r0, r3, #64	; 0x40
		conv->specifier_cat = SPECIFIER_PTR;
     980:	2103      	movs	r1, #3
     982:	f361 0202 	bfi	r2, r1, #0, #3
		if (conv->length_mod == LENGTH_UPPER_L) {
     986:	4243      	negs	r3, r0
		conv->specifier_cat = SPECIFIER_PTR;
     988:	f88d 2032 	strb.w	r2, [sp, #50]	; 0x32
		if (conv->length_mod == LENGTH_UPPER_L) {
     98c:	4143      	adcs	r3, r0
     98e:	e7e3      	b.n	958 <CONFIG_ISR_STACK_SIZE+0x158>
		conv->specifier_cat = SPECIFIER_PTR;
     990:	f89d 2032 	ldrb.w	r2, [sp, #50]	; 0x32
     994:	2103      	movs	r1, #3
		if (conv->length_mod != LENGTH_NONE) {
     996:	f013 0f78 	tst.w	r3, #120	; 0x78
		conv->specifier_cat = SPECIFIER_PTR;
     99a:	f361 0202 	bfi	r2, r1, #0, #3
     99e:	f88d 2032 	strb.w	r2, [sp, #50]	; 0x32
		if (conv->length_mod != LENGTH_NONE) {
     9a2:	bf14      	ite	ne
     9a4:	2301      	movne	r3, #1
     9a6:	2300      	moveq	r3, #0
     9a8:	e7d6      	b.n	958 <CONFIG_ISR_STACK_SIZE+0x158>
		conv->invalid = true;
     9aa:	f89d 3030 	ldrb.w	r3, [sp, #48]	; 0x30
     9ae:	f043 0301 	orr.w	r3, r3, #1
     9b2:	f88d 3030 	strb.w	r3, [sp, #48]	; 0x30
	bool unsupported = false;
     9b6:	2300      	movs	r3, #0
     9b8:	e7ce      	b.n	958 <CONFIG_ISR_STACK_SIZE+0x158>
		} else if (conv->width_present) {
     9ba:	f99d 2030 	ldrsb.w	r2, [sp, #48]	; 0x30
     9be:	2a00      	cmp	r2, #0
			width = conv->width_value;
     9c0:	bfb4      	ite	lt
     9c2:	f8dd 9034 	ldrlt.w	r9, [sp, #52]	; 0x34
		int width = -1;
     9c6:	f04f 39ff 	movge.w	r9, #4294967295
     9ca:	e6ba      	b.n	742 <cbvprintf+0x162>
		} else if (conv->prec_present) {
     9cc:	079b      	lsls	r3, r3, #30
     9ce:	f57f aec7 	bpl.w	760 <cbvprintf+0x180>
			precision = conv->prec_value;
     9d2:	f8dd 8038 	ldr.w	r8, [sp, #56]	; 0x38
			= (enum length_mod_enum)conv->length_mod;
     9d6:	f89d 2031 	ldrb.w	r2, [sp, #49]	; 0x31
		conv->pad0_value = 0;
     9da:	2300      	movs	r3, #0
		conv->pad0_pre_exp = 0;
     9dc:	e9cd 330d 	strd	r3, r3, [sp, #52]	; 0x34
			= (enum specifier_cat_enum)conv->specifier_cat;
     9e0:	f89d 3032 	ldrb.w	r3, [sp, #50]	; 0x32
		enum specifier_cat_enum specifier_cat
     9e4:	f003 0307 	and.w	r3, r3, #7
		if (specifier_cat == SPECIFIER_SINT) {
     9e8:	2b01      	cmp	r3, #1
			= (enum length_mod_enum)conv->length_mod;
     9ea:	f3c2 02c3 	ubfx	r2, r2, #3, #4
		if (specifier_cat == SPECIFIER_SINT) {
     9ee:	d136      	bne.n	a5e <CONFIG_ISR_STACK_SIZE+0x25e>
			switch (length_mod) {
     9f0:	1ed3      	subs	r3, r2, #3
     9f2:	2b04      	cmp	r3, #4
     9f4:	d820      	bhi.n	a38 <CONFIG_ISR_STACK_SIZE+0x238>
     9f6:	e8df f003 	tbb	[pc, r3]
     9fa:	0703      	.short	0x0703
     9fc:	1f07      	.short	0x1f07
     9fe:	1f          	.byte	0x1f
     9ff:	00          	.byte	0x00
					value->sint = va_arg(ap, long);
     a00:	f854 0b04 	ldr.w	r0, [r4], #4
				value->sint = (short)value->sint;
     a04:	17c1      	asrs	r1, r0, #31
     a06:	e004      	b.n	a12 <CONFIG_ISR_STACK_SIZE+0x212>
					(sint_value_type)va_arg(ap, intmax_t);
     a08:	3407      	adds	r4, #7
     a0a:	f024 0407 	bic.w	r4, r4, #7
				value->sint =
     a0e:	e8f4 0102 	ldrd	r0, r1, [r4], #8
				value->sint = (short)value->sint;
     a12:	e9cd 010a 	strd	r0, r1, [sp, #40]	; 0x28
		if (conv->invalid || conv->unsupported) {
     a16:	f89d 3030 	ldrb.w	r3, [sp, #48]	; 0x30
     a1a:	f013 0603 	ands.w	r6, r3, #3
     a1e:	d054      	beq.n	aca <CONFIG_ISR_STACK_SIZE+0x2ca>
			OUTS(sp, fp);
     a20:	9802      	ldr	r0, [sp, #8]
     a22:	463b      	mov	r3, r7
     a24:	4652      	mov	r2, sl
     a26:	4659      	mov	r1, fp
     a28:	f003 fc67 	bl	42fa <outs>
     a2c:	2800      	cmp	r0, #0
     a2e:	f2c0 8143 	blt.w	cb8 <CONFIG_ISR_STACK_SIZE+0x4b8>
     a32:	4405      	add	r5, r0
			continue;
     a34:	46ba      	mov	sl, r7
     a36:	e5db      	b.n	5f0 <cbvprintf+0x10>
					(sint_value_type)va_arg(ap, ptrdiff_t);
     a38:	f854 0b04 	ldr.w	r0, [r4], #4
			if (length_mod == LENGTH_HH) {
     a3c:	2a01      	cmp	r2, #1
					(sint_value_type)va_arg(ap, ptrdiff_t);
     a3e:	ea4f 71e0 	mov.w	r1, r0, asr #31
     a42:	e9cd 010a 	strd	r0, r1, [sp, #40]	; 0x28
			if (length_mod == LENGTH_HH) {
     a46:	d105      	bne.n	a54 <CONFIG_ISR_STACK_SIZE+0x254>
				value->uint = (unsigned char)value->uint;
     a48:	f89d 3028 	ldrb.w	r3, [sp, #40]	; 0x28
				value->uint = (unsigned short)value->uint;
     a4c:	930a      	str	r3, [sp, #40]	; 0x28
     a4e:	2300      	movs	r3, #0
     a50:	930b      	str	r3, [sp, #44]	; 0x2c
     a52:	e7e0      	b.n	a16 <CONFIG_ISR_STACK_SIZE+0x216>
			} else if (length_mod == LENGTH_H) {
     a54:	2a02      	cmp	r2, #2
     a56:	d1de      	bne.n	a16 <CONFIG_ISR_STACK_SIZE+0x216>
				value->sint = (short)value->sint;
     a58:	f9bd 0028 	ldrsh.w	r0, [sp, #40]	; 0x28
     a5c:	e7d2      	b.n	a04 <CONFIG_ISR_STACK_SIZE+0x204>
		} else if (specifier_cat == SPECIFIER_UINT) {
     a5e:	2b02      	cmp	r3, #2
     a60:	d123      	bne.n	aaa <CONFIG_ISR_STACK_SIZE+0x2aa>
			switch (length_mod) {
     a62:	1ed3      	subs	r3, r2, #3
     a64:	2b04      	cmp	r3, #4
     a66:	d813      	bhi.n	a90 <CONFIG_ISR_STACK_SIZE+0x290>
     a68:	e8df f003 	tbb	[pc, r3]
     a6c:	120a0a03 	.word	0x120a0a03
     a70:	12          	.byte	0x12
     a71:	00          	.byte	0x00
					value->uint = (wchar_t)va_arg(ap,
     a72:	6820      	ldr	r0, [r4, #0]
     a74:	900a      	str	r0, [sp, #40]	; 0x28
     a76:	2100      	movs	r1, #0
     a78:	1d23      	adds	r3, r4, #4
     a7a:	910b      	str	r1, [sp, #44]	; 0x2c
					(uint_value_type)va_arg(ap, size_t);
     a7c:	461c      	mov	r4, r3
     a7e:	e7ca      	b.n	a16 <CONFIG_ISR_STACK_SIZE+0x216>
					(uint_value_type)va_arg(ap,
     a80:	3407      	adds	r4, #7
     a82:	f024 0307 	bic.w	r3, r4, #7
				value->uint =
     a86:	e8f3 0102 	ldrd	r0, r1, [r3], #8
     a8a:	e9cd 010a 	strd	r0, r1, [sp, #40]	; 0x28
				break;
     a8e:	e7f5      	b.n	a7c <CONFIG_ISR_STACK_SIZE+0x27c>
					(uint_value_type)va_arg(ap, size_t);
     a90:	f854 3b04 	ldr.w	r3, [r4], #4
     a94:	930a      	str	r3, [sp, #40]	; 0x28
			if (length_mod == LENGTH_HH) {
     a96:	2a01      	cmp	r2, #1
					(uint_value_type)va_arg(ap, size_t);
     a98:	f04f 0300 	mov.w	r3, #0
     a9c:	930b      	str	r3, [sp, #44]	; 0x2c
			if (length_mod == LENGTH_HH) {
     a9e:	d0d3      	beq.n	a48 <CONFIG_ISR_STACK_SIZE+0x248>
			} else if (length_mod == LENGTH_H) {
     aa0:	2a02      	cmp	r2, #2
     aa2:	d1b8      	bne.n	a16 <CONFIG_ISR_STACK_SIZE+0x216>
				value->uint = (unsigned short)value->uint;
     aa4:	f8bd 3028 	ldrh.w	r3, [sp, #40]	; 0x28
     aa8:	e7d0      	b.n	a4c <CONFIG_ISR_STACK_SIZE+0x24c>
		} else if (specifier_cat == SPECIFIER_FP) {
     aaa:	2b04      	cmp	r3, #4
     aac:	d107      	bne.n	abe <CONFIG_ISR_STACK_SIZE+0x2be>
			if (length_mod == LENGTH_UPPER_L) {
     aae:	3407      	adds	r4, #7
     ab0:	f024 0407 	bic.w	r4, r4, #7
     ab4:	e8f4 0102 	ldrd	r0, r1, [r4], #8
				value->ldbl = va_arg(ap, long double);
     ab8:	e9cd 010a 	strd	r0, r1, [sp, #40]	; 0x28
     abc:	e7ab      	b.n	a16 <CONFIG_ISR_STACK_SIZE+0x216>
		} else if (specifier_cat == SPECIFIER_PTR) {
     abe:	2b03      	cmp	r3, #3
			value->ptr = va_arg(ap, void *);
     ac0:	bf04      	itt	eq
     ac2:	f854 3b04 	ldreq.w	r3, [r4], #4
     ac6:	930a      	streq	r3, [sp, #40]	; 0x28
     ac8:	e7a5      	b.n	a16 <CONFIG_ISR_STACK_SIZE+0x216>
		switch (conv->specifier) {
     aca:	f89d 0033 	ldrb.w	r0, [sp, #51]	; 0x33
     ace:	2878      	cmp	r0, #120	; 0x78
     ad0:	d8b0      	bhi.n	a34 <CONFIG_ISR_STACK_SIZE+0x234>
     ad2:	2862      	cmp	r0, #98	; 0x62
     ad4:	d822      	bhi.n	b1c <CONFIG_ISR_STACK_SIZE+0x31c>
     ad6:	2825      	cmp	r0, #37	; 0x25
     ad8:	f43f ad93 	beq.w	602 <cbvprintf+0x22>
     adc:	2858      	cmp	r0, #88	; 0x58
     ade:	d1a9      	bne.n	a34 <CONFIG_ISR_STACK_SIZE+0x234>
			bps = encode_uint(value->uint, conv, buf, bpe);
     ae0:	f10d 0326 	add.w	r3, sp, #38	; 0x26
     ae4:	9300      	str	r3, [sp, #0]
     ae6:	e9dd 010a 	ldrd	r0, r1, [sp, #40]	; 0x28
     aea:	ab04      	add	r3, sp, #16
     aec:	aa0c      	add	r2, sp, #48	; 0x30
     aee:	f003 fbb9 	bl	4264 <encode_uint>
     af2:	4682      	mov	sl, r0
			if (precision >= 0) {
     af4:	f1b8 0f00 	cmp.w	r8, #0
     af8:	f10d 0026 	add.w	r0, sp, #38	; 0x26
     afc:	db0c      	blt.n	b18 <CONFIG_ISR_STACK_SIZE+0x318>
				conv->flag_zero = false;
     afe:	f89d 2030 	ldrb.w	r2, [sp, #48]	; 0x30
				size_t len = bpe - bps;
     b02:	eba0 030a 	sub.w	r3, r0, sl
				conv->flag_zero = false;
     b06:	f36f 1286 	bfc	r2, #6, #1
				if (len < (size_t)precision) {
     b0a:	4598      	cmp	r8, r3
				conv->flag_zero = false;
     b0c:	f88d 2030 	strb.w	r2, [sp, #48]	; 0x30
				if (len < (size_t)precision) {
     b10:	d902      	bls.n	b18 <CONFIG_ISR_STACK_SIZE+0x318>
					conv->pad0_value = precision - (int)len;
     b12:	eba8 0303 	sub.w	r3, r8, r3
     b16:	930d      	str	r3, [sp, #52]	; 0x34
		const char *bpe = buf + sizeof(buf);
     b18:	4680      	mov	r8, r0
     b1a:	e03d      	b.n	b98 <CONFIG_ISR_STACK_SIZE+0x398>
     b1c:	3863      	subs	r0, #99	; 0x63
     b1e:	2815      	cmp	r0, #21
     b20:	d888      	bhi.n	a34 <CONFIG_ISR_STACK_SIZE+0x234>
     b22:	a101      	add	r1, pc, #4	; (adr r1, b28 <CONFIG_ISR_STACK_SIZE+0x328>)
     b24:	f851 f020 	ldr.w	pc, [r1, r0, lsl #2]
     b28:	00000ba9 	.word	0x00000ba9
     b2c:	00000c0d 	.word	0x00000c0d
     b30:	00000a35 	.word	0x00000a35
     b34:	00000a35 	.word	0x00000a35
     b38:	00000a35 	.word	0x00000a35
     b3c:	00000a35 	.word	0x00000a35
     b40:	00000c0d 	.word	0x00000c0d
     b44:	00000a35 	.word	0x00000a35
     b48:	00000a35 	.word	0x00000a35
     b4c:	00000a35 	.word	0x00000a35
     b50:	00000a35 	.word	0x00000a35
     b54:	00000c6b 	.word	0x00000c6b
     b58:	00000c39 	.word	0x00000c39
     b5c:	00000c3d 	.word	0x00000c3d
     b60:	00000a35 	.word	0x00000a35
     b64:	00000a35 	.word	0x00000a35
     b68:	00000b81 	.word	0x00000b81
     b6c:	00000a35 	.word	0x00000a35
     b70:	00000c39 	.word	0x00000c39
     b74:	00000a35 	.word	0x00000a35
     b78:	00000a35 	.word	0x00000a35
     b7c:	00000c39 	.word	0x00000c39
			if (precision >= 0) {
     b80:	f1b8 0f00 	cmp.w	r8, #0
			bps = (const char *)value->ptr;
     b84:	f8dd a028 	ldr.w	sl, [sp, #40]	; 0x28
			if (precision >= 0) {
     b88:	db0a      	blt.n	ba0 <CONFIG_ISR_STACK_SIZE+0x3a0>
				len = strnlen(bps, precision);
     b8a:	4641      	mov	r1, r8
     b8c:	4650      	mov	r0, sl
     b8e:	f003 fbf2 	bl	4376 <strnlen>
			bpe = bps + len;
     b92:	eb0a 0800 	add.w	r8, sl, r0
		char sign = 0;
     b96:	2600      	movs	r6, #0
		if (bps == NULL) {
     b98:	f1ba 0f00 	cmp.w	sl, #0
     b9c:	d10c      	bne.n	bb8 <CONFIG_ISR_STACK_SIZE+0x3b8>
     b9e:	e749      	b.n	a34 <CONFIG_ISR_STACK_SIZE+0x234>
				len = strlen(bps);
     ba0:	4650      	mov	r0, sl
     ba2:	f003 fbe1 	bl	4368 <strlen>
     ba6:	e7f4      	b.n	b92 <CONFIG_ISR_STACK_SIZE+0x392>
			buf[0] = CHAR_IS_SIGNED ? value->sint : value->uint;
     ba8:	9b0a      	ldr	r3, [sp, #40]	; 0x28
     baa:	f88d 3010 	strb.w	r3, [sp, #16]
			break;
     bae:	2600      	movs	r6, #0
			bpe = buf + 1;
     bb0:	f10d 0811 	add.w	r8, sp, #17
			bps = buf;
     bb4:	f10d 0a10 	add.w	sl, sp, #16
		size_t nj_len = (bpe - bps);
     bb8:	eba8 030a 	sub.w	r3, r8, sl
		if (sign != 0) {
     bbc:	b106      	cbz	r6, bc0 <CONFIG_ISR_STACK_SIZE+0x3c0>
			nj_len += 1U;
     bbe:	3301      	adds	r3, #1
		if (conv->altform_0c) {
     bc0:	f89d 2032 	ldrb.w	r2, [sp, #50]	; 0x32
     bc4:	06d0      	lsls	r0, r2, #27
     bc6:	d56b      	bpl.n	ca0 <CONFIG_ISR_STACK_SIZE+0x4a0>
			nj_len += 2U;
     bc8:	3302      	adds	r3, #2
		if (conv->pad_fp) {
     bca:	0652      	lsls	r2, r2, #25
		nj_len += conv->pad0_value;
     bcc:	990d      	ldr	r1, [sp, #52]	; 0x34
			nj_len += conv->pad0_pre_exp;
     bce:	bf48      	it	mi
     bd0:	9a0e      	ldrmi	r2, [sp, #56]	; 0x38
		nj_len += conv->pad0_value;
     bd2:	440b      	add	r3, r1
			nj_len += conv->pad0_pre_exp;
     bd4:	bf48      	it	mi
     bd6:	189b      	addmi	r3, r3, r2
		if (width > 0) {
     bd8:	f1b9 0f00 	cmp.w	r9, #0
     bdc:	dd79      	ble.n	cd2 <CONFIG_ISR_STACK_SIZE+0x4d2>
			if (!conv->flag_dash) {
     bde:	f89d 2030 	ldrb.w	r2, [sp, #48]	; 0x30
			width -= (int)nj_len;
     be2:	eba9 0903 	sub.w	r9, r9, r3
			if (!conv->flag_dash) {
     be6:	f3c2 0380 	ubfx	r3, r2, #2, #1
     bea:	9303      	str	r3, [sp, #12]
     bec:	0753      	lsls	r3, r2, #29
     bee:	d470      	bmi.n	cd2 <CONFIG_ISR_STACK_SIZE+0x4d2>
				if (conv->flag_zero) {
     bf0:	0650      	lsls	r0, r2, #25
     bf2:	d564      	bpl.n	cbe <CONFIG_ISR_STACK_SIZE+0x4be>
					if (sign != 0) {
     bf4:	b146      	cbz	r6, c08 <CONFIG_ISR_STACK_SIZE+0x408>
						OUTC(sign);
     bf6:	9b02      	ldr	r3, [sp, #8]
     bf8:	4659      	mov	r1, fp
     bfa:	4630      	mov	r0, r6
     bfc:	4798      	blx	r3
     bfe:	2800      	cmp	r0, #0
     c00:	db5a      	blt.n	cb8 <CONFIG_ISR_STACK_SIZE+0x4b8>
						sign = 0;
     c02:	9b03      	ldr	r3, [sp, #12]
						OUTC(sign);
     c04:	3501      	adds	r5, #1
						sign = 0;
     c06:	461e      	mov	r6, r3
					pad = '0';
     c08:	2330      	movs	r3, #48	; 0x30
     c0a:	e059      	b.n	cc0 <CONFIG_ISR_STACK_SIZE+0x4c0>
			if (conv->flag_plus) {
     c0c:	071e      	lsls	r6, r3, #28
     c0e:	d411      	bmi.n	c34 <CONFIG_ISR_STACK_SIZE+0x434>
				sign = ' ';
     c10:	f013 0610 	ands.w	r6, r3, #16
     c14:	bf18      	it	ne
     c16:	2620      	movne	r6, #32
			sint = value->sint;
     c18:	e9dd 230a 	ldrd	r2, r3, [sp, #40]	; 0x28
			if (sint < 0) {
     c1c:	2a00      	cmp	r2, #0
     c1e:	f173 0100 	sbcs.w	r1, r3, #0
     c22:	f6bf af5d 	bge.w	ae0 <CONFIG_ISR_STACK_SIZE+0x2e0>
				value->uint = (uint_value_type)-sint;
     c26:	4252      	negs	r2, r2
     c28:	eb63 0343 	sbc.w	r3, r3, r3, lsl #1
     c2c:	e9cd 230a 	strd	r2, r3, [sp, #40]	; 0x28
				sign = '-';
     c30:	262d      	movs	r6, #45	; 0x2d
     c32:	e755      	b.n	ae0 <CONFIG_ISR_STACK_SIZE+0x2e0>
				sign = '+';
     c34:	262b      	movs	r6, #43	; 0x2b
     c36:	e7ef      	b.n	c18 <CONFIG_ISR_STACK_SIZE+0x418>
		switch (conv->specifier) {
     c38:	2600      	movs	r6, #0
     c3a:	e751      	b.n	ae0 <CONFIG_ISR_STACK_SIZE+0x2e0>
			if (value->ptr != NULL) {
     c3c:	980a      	ldr	r0, [sp, #40]	; 0x28
     c3e:	b348      	cbz	r0, c94 <CONFIG_ISR_STACK_SIZE+0x494>
				bps = encode_uint((uintptr_t)value->ptr, conv,
     c40:	f10d 0326 	add.w	r3, sp, #38	; 0x26
     c44:	9300      	str	r3, [sp, #0]
     c46:	aa0c      	add	r2, sp, #48	; 0x30
     c48:	ab04      	add	r3, sp, #16
     c4a:	2100      	movs	r1, #0
     c4c:	f003 fb0a 	bl	4264 <encode_uint>
				conv->altform_0c = true;
     c50:	f8bd 3032 	ldrh.w	r3, [sp, #50]	; 0x32
     c54:	f003 03ef 	and.w	r3, r3, #239	; 0xef
     c58:	f443 43f0 	orr.w	r3, r3, #30720	; 0x7800
     c5c:	f043 0310 	orr.w	r3, r3, #16
				bps = encode_uint((uintptr_t)value->ptr, conv,
     c60:	4682      	mov	sl, r0
				conv->altform_0c = true;
     c62:	f8ad 3032 	strh.w	r3, [sp, #50]	; 0x32
		char sign = 0;
     c66:	2600      	movs	r6, #0
				goto prec_int_pad0;
     c68:	e744      	b.n	af4 <CONFIG_ISR_STACK_SIZE+0x2f4>
				store_count(conv, value->ptr, count);
     c6a:	9b0a      	ldr	r3, [sp, #40]	; 0x28
	switch ((enum length_mod_enum)conv->length_mod) {
     c6c:	2a07      	cmp	r2, #7
     c6e:	f63f aee1 	bhi.w	a34 <CONFIG_ISR_STACK_SIZE+0x234>
     c72:	e8df f002 	tbb	[pc, r2]
     c76:	040d      	.short	0x040d
     c78:	08080d06 	.word	0x08080d06
     c7c:	0d0d      	.short	0x0d0d
		*(signed char *)dp = (signed char)count;
     c7e:	701d      	strb	r5, [r3, #0]
		break;
     c80:	e6d8      	b.n	a34 <CONFIG_ISR_STACK_SIZE+0x234>
		*(short *)dp = (short)count;
     c82:	801d      	strh	r5, [r3, #0]
		break;
     c84:	e6d6      	b.n	a34 <CONFIG_ISR_STACK_SIZE+0x234>
		*(intmax_t *)dp = (intmax_t)count;
     c86:	4628      	mov	r0, r5
     c88:	17e9      	asrs	r1, r5, #31
     c8a:	e9c3 0100 	strd	r0, r1, [r3]
		break;
     c8e:	e6d1      	b.n	a34 <CONFIG_ISR_STACK_SIZE+0x234>
		*(ptrdiff_t *)dp = (ptrdiff_t)count;
     c90:	601d      	str	r5, [r3, #0]
		break;
     c92:	e6cf      	b.n	a34 <CONFIG_ISR_STACK_SIZE+0x234>
			bpe = bps + 5;
     c94:	f8df 80c4 	ldr.w	r8, [pc, #196]	; d5c <CONFIG_ISR_STACK_SIZE+0x55c>
     c98:	4606      	mov	r6, r0
			bps = "(nil)";
     c9a:	f1a8 0a05 	sub.w	sl, r8, #5
     c9e:	e78b      	b.n	bb8 <CONFIG_ISR_STACK_SIZE+0x3b8>
		} else if (conv->altform_0) {
     ca0:	0711      	lsls	r1, r2, #28
			nj_len += 1U;
     ca2:	bf48      	it	mi
     ca4:	3301      	addmi	r3, #1
     ca6:	e790      	b.n	bca <CONFIG_ISR_STACK_SIZE+0x3ca>
					OUTC(pad);
     ca8:	4618      	mov	r0, r3
     caa:	9303      	str	r3, [sp, #12]
     cac:	4659      	mov	r1, fp
     cae:	9b02      	ldr	r3, [sp, #8]
     cb0:	4798      	blx	r3
     cb2:	2800      	cmp	r0, #0
     cb4:	9b03      	ldr	r3, [sp, #12]
     cb6:	da04      	bge.n	cc2 <CONFIG_ISR_STACK_SIZE+0x4c2>
#undef OUTS
#undef OUTC
}
     cb8:	b011      	add	sp, #68	; 0x44
     cba:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
				char pad = ' ';
     cbe:	2320      	movs	r3, #32
     cc0:	444d      	add	r5, r9
     cc2:	464a      	mov	r2, r9
				while (width-- > 0) {
     cc4:	2a00      	cmp	r2, #0
     cc6:	eba5 0109 	sub.w	r1, r5, r9
     cca:	f109 39ff 	add.w	r9, r9, #4294967295
     cce:	dceb      	bgt.n	ca8 <CONFIG_ISR_STACK_SIZE+0x4a8>
     cd0:	460d      	mov	r5, r1
		if (sign != 0) {
     cd2:	b136      	cbz	r6, ce2 <CONFIG_ISR_STACK_SIZE+0x4e2>
			OUTC(sign);
     cd4:	9b02      	ldr	r3, [sp, #8]
     cd6:	4659      	mov	r1, fp
     cd8:	4630      	mov	r0, r6
     cda:	4798      	blx	r3
     cdc:	2800      	cmp	r0, #0
     cde:	dbeb      	blt.n	cb8 <CONFIG_ISR_STACK_SIZE+0x4b8>
     ce0:	3501      	adds	r5, #1
			if (conv->altform_0c | conv->altform_0) {
     ce2:	f89d 3032 	ldrb.w	r3, [sp, #50]	; 0x32
     ce6:	06d9      	lsls	r1, r3, #27
     ce8:	d401      	bmi.n	cee <CONFIG_ISR_STACK_SIZE+0x4ee>
     cea:	071a      	lsls	r2, r3, #28
     cec:	d506      	bpl.n	cfc <CONFIG_ISR_STACK_SIZE+0x4fc>
				OUTC('0');
     cee:	9b02      	ldr	r3, [sp, #8]
     cf0:	4659      	mov	r1, fp
     cf2:	2030      	movs	r0, #48	; 0x30
     cf4:	4798      	blx	r3
     cf6:	2800      	cmp	r0, #0
     cf8:	dbde      	blt.n	cb8 <CONFIG_ISR_STACK_SIZE+0x4b8>
     cfa:	3501      	adds	r5, #1
			if (conv->altform_0c) {
     cfc:	f89d 3032 	ldrb.w	r3, [sp, #50]	; 0x32
     d00:	06db      	lsls	r3, r3, #27
     d02:	d507      	bpl.n	d14 <CONFIG_ISR_STACK_SIZE+0x514>
				OUTC(conv->specifier);
     d04:	f89d 0033 	ldrb.w	r0, [sp, #51]	; 0x33
     d08:	9b02      	ldr	r3, [sp, #8]
     d0a:	4659      	mov	r1, fp
     d0c:	4798      	blx	r3
     d0e:	2800      	cmp	r0, #0
     d10:	dbd2      	blt.n	cb8 <CONFIG_ISR_STACK_SIZE+0x4b8>
     d12:	3501      	adds	r5, #1
			while (pad_len-- > 0) {
     d14:	9e0d      	ldr	r6, [sp, #52]	; 0x34
     d16:	442e      	add	r6, r5
     d18:	1b73      	subs	r3, r6, r5
     d1a:	2b00      	cmp	r3, #0
     d1c:	dc16      	bgt.n	d4c <CONFIG_ISR_STACK_SIZE+0x54c>
			OUTS(bps, bpe);
     d1e:	9802      	ldr	r0, [sp, #8]
     d20:	4643      	mov	r3, r8
     d22:	4652      	mov	r2, sl
     d24:	4659      	mov	r1, fp
     d26:	f003 fae8 	bl	42fa <outs>
     d2a:	2800      	cmp	r0, #0
     d2c:	dbc4      	blt.n	cb8 <CONFIG_ISR_STACK_SIZE+0x4b8>
     d2e:	4405      	add	r5, r0
		while (width > 0) {
     d30:	44a9      	add	r9, r5
     d32:	eba9 0305 	sub.w	r3, r9, r5
     d36:	2b00      	cmp	r3, #0
     d38:	f77f ae7c 	ble.w	a34 <CONFIG_ISR_STACK_SIZE+0x234>
			OUTC(' ');
     d3c:	9b02      	ldr	r3, [sp, #8]
     d3e:	4659      	mov	r1, fp
     d40:	2020      	movs	r0, #32
     d42:	4798      	blx	r3
     d44:	2800      	cmp	r0, #0
     d46:	dbb7      	blt.n	cb8 <CONFIG_ISR_STACK_SIZE+0x4b8>
     d48:	3501      	adds	r5, #1
			--width;
     d4a:	e7f2      	b.n	d32 <CONFIG_ISR_STACK_SIZE+0x532>
				OUTC('0');
     d4c:	9b02      	ldr	r3, [sp, #8]
     d4e:	4659      	mov	r1, fp
     d50:	2030      	movs	r0, #48	; 0x30
     d52:	4798      	blx	r3
     d54:	2800      	cmp	r0, #0
     d56:	dbaf      	blt.n	cb8 <CONFIG_ISR_STACK_SIZE+0x4b8>
     d58:	3501      	adds	r5, #1
     d5a:	e7dd      	b.n	d18 <CONFIG_ISR_STACK_SIZE+0x518>
     d5c:	00004efb 	.word	0x00004efb

00000d60 <pm_state_notify>:
/*
 * Function called to notify when the system is entering / exiting a
 * power state
 */
static inline void pm_state_notify(bool entering_state)
{
     d60:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
     d64:	4605      	mov	r5, r0
     d66:	f04f 0320 	mov.w	r3, #32
     d6a:	f3ef 8611 	mrs	r6, BASEPRI
     d6e:	f383 8812 	msr	BASEPRI_MAX, r3
     d72:	f3bf 8f6f 	isb	sy
	struct pm_notifier *notifier;
	k_spinlock_key_t pm_notifier_key;
	void (*callback)(enum pm_state state);

	pm_notifier_key = k_spin_lock(&pm_notifier_lock);
	SYS_SLIST_FOR_EACH_CONTAINER(&pm_notifiers, notifier, _node) {
     d76:	4b10      	ldr	r3, [pc, #64]	; (db8 <pm_state_notify+0x58>)
     d78:	681c      	ldr	r4, [r3, #0]
     d7a:	2c00      	cmp	r4, #0
     d7c:	bf38      	it	cc
     d7e:	2400      	movcc	r4, #0
     d80:	b19c      	cbz	r4, daa <pm_state_notify+0x4a>
		} else {
			callback = notifier->state_exit;
		}

		if (callback) {
			callback(z_power_states[_current_cpu->id].state);
     d82:	4f0e      	ldr	r7, [pc, #56]	; (dbc <pm_state_notify+0x5c>)
     d84:	f8df 8038 	ldr.w	r8, [pc, #56]	; dc0 <pm_state_notify+0x60>
     d88:	f04f 090c 	mov.w	r9, #12
			callback = notifier->state_exit;
     d8c:	e9d4 3201 	ldrd	r3, r2, [r4, #4]
     d90:	2d00      	cmp	r5, #0
     d92:	bf08      	it	eq
     d94:	4613      	moveq	r3, r2
		if (callback) {
     d96:	b12b      	cbz	r3, da4 <pm_state_notify+0x44>
			callback(z_power_states[_current_cpu->id].state);
     d98:	f898 2014 	ldrb.w	r2, [r8, #20]
     d9c:	fb09 f202 	mul.w	r2, r9, r2
     da0:	5cb8      	ldrb	r0, [r7, r2]
     da2:	4798      	blx	r3
Z_GENLIST_PEEK_NEXT_NO_CHECK(slist, snode)
     da4:	6824      	ldr	r4, [r4, #0]
	SYS_SLIST_FOR_EACH_CONTAINER(&pm_notifiers, notifier, _node) {
     da6:	2c00      	cmp	r4, #0
     da8:	d1f0      	bne.n	d8c <pm_state_notify+0x2c>
	__asm__ volatile(
     daa:	f386 8811 	msr	BASEPRI, r6
     dae:	f3bf 8f6f 	isb	sy
		}
	}
	k_spin_unlock(&pm_notifier_lock, pm_notifier_key);
}
     db2:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
     db6:	bf00      	nop
     db8:	200001c0 	.word	0x200001c0
     dbc:	200001cc 	.word	0x200001cc
     dc0:	20000334 	.word	0x20000334

00000dc4 <atomic_test_and_set_bit.constprop.0>:
 *
 * @return true if the bit was set, false if it wasn't.
 */
static inline bool atomic_test_and_set_bit(atomic_t *target, int bit)
{
	atomic_val_t mask = ATOMIC_MASK(bit);
     dc4:	f000 031f 	and.w	r3, r0, #31
     dc8:	2201      	movs	r2, #1
     dca:	409a      	lsls	r2, r3
 *
 * @return Previous value of @a target.
 */
static inline atomic_val_t atomic_or(atomic_t *target, atomic_val_t value)
{
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
     dcc:	4b0a      	ldr	r3, [pc, #40]	; (df8 <atomic_test_and_set_bit.constprop.0+0x34>)
     dce:	f3bf 8f5b 	dmb	ish
	atomic_val_t old;

	old = atomic_or(ATOMIC_ELEM(target, bit), mask);
     dd2:	0940      	lsrs	r0, r0, #5
     dd4:	eb03 0080 	add.w	r0, r3, r0, lsl #2
     dd8:	e850 3f00 	ldrex	r3, [r0]
     ddc:	ea43 0102 	orr.w	r1, r3, r2
     de0:	e840 1c00 	strex	ip, r1, [r0]
     de4:	f1bc 0f00 	cmp.w	ip, #0
     de8:	d1f6      	bne.n	dd8 <atomic_test_and_set_bit.constprop.0+0x14>
     dea:	f3bf 8f5b 	dmb	ish

	return (old & mask) != 0;
     dee:	421a      	tst	r2, r3
}
     df0:	bf14      	ite	ne
     df2:	2001      	movne	r0, #1
     df4:	2000      	moveq	r0, #0
     df6:	4770      	bx	lr
     df8:	200001d8 	.word	0x200001d8

00000dfc <pm_system_resume>:

void pm_system_resume(void)
{
     dfc:	b530      	push	{r4, r5, lr}
	uint8_t id = _current_cpu->id;
     dfe:	4b1d      	ldr	r3, [pc, #116]	; (e74 <pm_system_resume+0x78>)
     e00:	7d1d      	ldrb	r5, [r3, #20]
 *
 * @return Previous value of @a target.
 */
static inline atomic_val_t atomic_and(atomic_t *target, atomic_val_t value)
{
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
     e02:	f3bf 8f5b 	dmb	ish
	atomic_val_t mask = ATOMIC_MASK(bit);
     e06:	f005 031f 	and.w	r3, r5, #31
     e0a:	2201      	movs	r2, #1
     e0c:	409a      	lsls	r2, r3
     e0e:	4b1a      	ldr	r3, [pc, #104]	; (e78 <pm_system_resume+0x7c>)
	old = atomic_and(ATOMIC_ELEM(target, bit), ~mask);
     e10:	0969      	lsrs	r1, r5, #5
{
     e12:	b085      	sub	sp, #20
     e14:	43d0      	mvns	r0, r2
     e16:	eb03 0381 	add.w	r3, r3, r1, lsl #2
     e1a:	e853 1f00 	ldrex	r1, [r3]
     e1e:	ea01 0400 	and.w	r4, r1, r0
     e22:	e843 4c00 	strex	ip, r4, [r3]
     e26:	f1bc 0f00 	cmp.w	ip, #0
     e2a:	d1f6      	bne.n	e1a <pm_system_resume+0x1e>
     e2c:	f3bf 8f5b 	dmb	ish
	 * that caused the wake. This hook will be called from the ISR.
	 * For such CPU LPS states, do post operations and restores here.
	 * The kernel scheduler will get control after the ISR finishes
	 * and it may schedule another thread.
	 */
	if (atomic_test_and_clear_bit(z_post_ops_required, id)) {
     e30:	4211      	tst	r1, r2
     e32:	d017      	beq.n	e64 <pm_system_resume+0x68>
		exit_pos_ops(z_power_states[id]);
     e34:	4c11      	ldr	r4, [pc, #68]	; (e7c <pm_system_resume+0x80>)
     e36:	220c      	movs	r2, #12
     e38:	fb02 4205 	mla	r2, r2, r5, r4
     e3c:	ca07      	ldmia	r2, {r0, r1, r2}
     e3e:	ab01      	add	r3, sp, #4
     e40:	e883 0007 	stmia.w	r3, {r0, r1, r2}
	if (pm_power_state_exit_post_ops != NULL) {
     e44:	4a0e      	ldr	r2, [pc, #56]	; (e80 <pm_system_resume+0x84>)
     e46:	b17a      	cbz	r2, e68 <pm_system_resume+0x6c>
		pm_power_state_exit_post_ops(info);
     e48:	e893 0007 	ldmia.w	r3, {r0, r1, r2}
     e4c:	f003 fac6 	bl	43dc <pm_power_state_exit_post_ops>
		pm_state_notify(false);
     e50:	2000      	movs	r0, #0
     e52:	f7ff ff85 	bl	d60 <pm_state_notify>
		z_power_states[id] = (struct pm_state_info){PM_STATE_ACTIVE,
     e56:	230c      	movs	r3, #12
     e58:	436b      	muls	r3, r5
     e5a:	2200      	movs	r2, #0
     e5c:	18e1      	adds	r1, r4, r3
     e5e:	50e2      	str	r2, [r4, r3]
     e60:	e9c1 2201 	strd	r2, r2, [r1, #4]
			0, 0};
	}
}
     e64:	b005      	add	sp, #20
     e66:	bd30      	pop	{r4, r5, pc}
     e68:	f382 8811 	msr	BASEPRI, r2
     e6c:	f3bf 8f6f 	isb	sy
		"cpsie i;"
		: : : "memory", "cc");
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
}
     e70:	e7ee      	b.n	e50 <pm_system_resume+0x54>
     e72:	bf00      	nop
     e74:	20000334 	.word	0x20000334
     e78:	200001c8 	.word	0x200001c8
     e7c:	200001cc 	.word	0x200001cc
     e80:	000043dd 	.word	0x000043dd

00000e84 <pm_system_suspend>:

	return ret;
}

bool pm_system_suspend(int32_t ticks)
{
     e84:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	bool ret = true;
	uint8_t id = _current_cpu->id;
     e88:	4b37      	ldr	r3, [pc, #220]	; (f68 <pm_system_suspend+0xe4>)
     e8a:	f8df 80f4 	ldr.w	r8, [pc, #244]	; f80 <pm_system_suspend+0xfc>
     e8e:	7d1c      	ldrb	r4, [r3, #20]
{
     e90:	b088      	sub	sp, #32
     e92:	4607      	mov	r7, r0

	SYS_PORT_TRACING_FUNC_ENTER(pm, system_suspend, ticks);

	if (!atomic_test_and_set_bit(z_power_states_forced, id)) {
     e94:	4620      	mov	r0, r4
     e96:	f7ff ff95 	bl	dc4 <atomic_test_and_set_bit.constprop.0>
     e9a:	b960      	cbnz	r0, eb6 <pm_system_suspend+0x32>
		z_power_states[id] = pm_policy_next_state(id, ticks);
     e9c:	466e      	mov	r6, sp
     e9e:	463a      	mov	r2, r7
     ea0:	4621      	mov	r1, r4
     ea2:	4630      	mov	r0, r6
     ea4:	f003 fa40 	bl	4328 <pm_policy_next_state>
     ea8:	e896 0007 	ldmia.w	r6, {r0, r1, r2}
     eac:	250c      	movs	r5, #12
     eae:	fb05 8504 	mla	r5, r5, r4, r8
     eb2:	e885 0007 	stmia.w	r5, {r0, r1, r2}
	}

	if (z_power_states[id].state == PM_STATE_ACTIVE) {
     eb6:	230c      	movs	r3, #12
     eb8:	4363      	muls	r3, r4
     eba:	eb08 0203 	add.w	r2, r8, r3
     ebe:	f818 0003 	ldrb.w	r0, [r8, r3]
     ec2:	0965      	lsrs	r5, r4, #5
     ec4:	f004 061f 	and.w	r6, r4, #31
     ec8:	b3c8      	cbz	r0, f3e <pm_system_suspend+0xba>
				   z_power_states[id].state);
		ret = false;
		goto end;
	}

	if (ticks != K_TICKS_FOREVER) {
     eca:	1c7b      	adds	r3, r7, #1
     ecc:	d00f      	beq.n	eee <pm_system_suspend+0x6a>
		} else {
			return t * ((uint64_t)to_hz / from_hz);
		}
	} else {
		if (result32) {
			return (uint32_t)((t * to_hz + off) / from_hz);
     ece:	f8d2 e008 	ldr.w	lr, [r2, #8]
     ed2:	4826      	ldr	r0, [pc, #152]	; (f6c <pm_system_suspend+0xe8>)
     ed4:	4a26      	ldr	r2, [pc, #152]	; (f70 <pm_system_suspend+0xec>)
     ed6:	f44f 4c00 	mov.w	ip, #32768	; 0x8000
     eda:	2100      	movs	r1, #0
     edc:	2300      	movs	r3, #0
     ede:	fbec 010e 	umlal	r0, r1, ip, lr
     ee2:	f7ff f8fb 	bl	dc <__aeabi_uldivmod>
		/*
		 * We need to set the timer to interrupt a little bit early to
		 * accommodate the time required by the CPU to fully wake up.
		 */
		z_set_timeout_expiry(ticks -
     ee6:	2101      	movs	r1, #1
     ee8:	1a38      	subs	r0, r7, r0
     eea:	f003 fe49 	bl	4b80 <z_set_timeout_expiry>
	 * state. We don't want to be scheduled out yet, first we need
	 * to send a notification about leaving the idle state. So,
	 * we lock the scheduler here and unlock just after we have
	 * sent the notification in pm_system_resume().
	 */
	k_sched_lock();
     eee:	f002 fc7d 	bl	37ec <k_sched_lock>
	pm_stats_start();
	/* Enter power state */
	pm_state_notify(true);
     ef2:	2001      	movs	r0, #1
     ef4:	f7ff ff34 	bl	d60 <pm_state_notify>
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
     ef8:	f3bf 8f5b 	dmb	ish
     efc:	4b1d      	ldr	r3, [pc, #116]	; (f74 <pm_system_suspend+0xf0>)
 *
 * @return N/A
 */
static inline void atomic_set_bit(atomic_t *target, int bit)
{
	atomic_val_t mask = ATOMIC_MASK(bit);
     efe:	2201      	movs	r2, #1
     f00:	40b2      	lsls	r2, r6
     f02:	eb03 0385 	add.w	r3, r3, r5, lsl #2
     f06:	e853 1f00 	ldrex	r1, [r3]
     f0a:	4311      	orrs	r1, r2
     f0c:	e843 1000 	strex	r0, r1, [r3]
     f10:	2800      	cmp	r0, #0
     f12:	d1f8      	bne.n	f06 <pm_system_suspend+0x82>
     f14:	f3bf 8f5b 	dmb	ish
	atomic_set_bit(z_post_ops_required, id);
	pm_state_set(z_power_states[id]);
     f18:	230c      	movs	r3, #12
     f1a:	fb03 8404 	mla	r4, r3, r4, r8
     f1e:	e894 0007 	ldmia.w	r4, {r0, r1, r2}
     f22:	ab05      	add	r3, sp, #20
     f24:	e883 0007 	stmia.w	r3, {r0, r1, r2}
	if (pm_power_state_set != NULL) {
     f28:	4a13      	ldr	r2, [pc, #76]	; (f78 <pm_system_suspend+0xf4>)
     f2a:	b11a      	cbz	r2, f34 <pm_system_suspend+0xb0>
		pm_power_state_set(info);
     f2c:	e893 0007 	ldmia.w	r3, {r0, r1, r2}
     f30:	f003 fa41 	bl	43b6 <pm_power_state_set>
	if (atomic_add(&z_cpus_active, 1) == 0) {
		pm_resume_devices();
	}
#endif
	pm_stats_update(z_power_states[id].state);
	pm_system_resume();
     f34:	f7ff ff62 	bl	dfc <pm_system_resume>
	k_sched_unlock();
     f38:	f002 fde6 	bl	3b08 <k_sched_unlock>
	bool ret = true;
     f3c:	2001      	movs	r0, #1
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
     f3e:	4a0f      	ldr	r2, [pc, #60]	; (f7c <pm_system_suspend+0xf8>)
     f40:	f3bf 8f5b 	dmb	ish
	atomic_val_t mask = ATOMIC_MASK(bit);
     f44:	2301      	movs	r3, #1
     f46:	40b3      	lsls	r3, r6
	(void)atomic_and(ATOMIC_ELEM(target, bit), ~mask);
     f48:	43db      	mvns	r3, r3
     f4a:	eb02 0585 	add.w	r5, r2, r5, lsl #2
     f4e:	e855 2f00 	ldrex	r2, [r5]
     f52:	401a      	ands	r2, r3
     f54:	e845 2100 	strex	r1, r2, [r5]
     f58:	2900      	cmp	r1, #0
     f5a:	d1f8      	bne.n	f4e <pm_system_suspend+0xca>
     f5c:	f3bf 8f5b 	dmb	ish
				   z_power_states[id].state);

end:
	atomic_clear_bit(z_power_states_forced, id);
	return ret;
}
     f60:	b008      	add	sp, #32
     f62:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
     f66:	bf00      	nop
     f68:	20000334 	.word	0x20000334
     f6c:	000f423f 	.word	0x000f423f
     f70:	000f4240 	.word	0x000f4240
     f74:	200001c8 	.word	0x200001c8
     f78:	000043b7 	.word	0x000043b7
     f7c:	200001d8 	.word	0x200001d8
     f80:	200001cc 	.word	0x200001cc

00000f84 <z_arm_cpu_idle_init>:
 * void z_arm_cpu_idle_init(void);
 */

SECTION_FUNC(TEXT, z_arm_cpu_idle_init)
#if defined(CONFIG_CPU_CORTEX_M)
	ldr	r1, =_SCB_SCR
     f84:	4901      	ldr	r1, [pc, #4]	; (f8c <z_arm_cpu_idle_init+0x8>)
	movs.n	r2, #_SCR_INIT_BITS
     f86:	2210      	movs	r2, #16
	str	r2, [r1]
     f88:	600a      	str	r2, [r1, #0]
#endif
	bx	lr
     f8a:	4770      	bx	lr
	ldr	r1, =_SCB_SCR
     f8c:	e000ed10 	.word	0xe000ed10

00000f90 <arch_cpu_idle>:
	 * before entering low power state.
	 *
	 * Set PRIMASK before configuring BASEPRI to prevent interruption
	 * before wake-up.
	 */
	cpsid	i
     f90:	b672      	cpsid	i

	/*
	 * Set wake-up interrupt priority to the lowest and synchronise to
	 * ensure that this is visible to the WFI instruction.
	 */
	eors.n	r0, r0
     f92:	4040      	eors	r0, r0
	msr	BASEPRI, r0
     f94:	f380 8811 	msr	BASEPRI, r0
	isb
     f98:	f3bf 8f6f 	isb	sy

	/*
	 * Wait for all memory transactions to complete before entering low
	 * power state.
	 */
	dsb
     f9c:	f3bf 8f4f 	dsb	sy

	/* Enter low power state */
	wfi
     fa0:	bf30      	wfi

	/*
	 * Clear PRIMASK and flush instruction buffer to immediately service
	 * the wake-up interrupt.
	 */
	cpsie	i
     fa2:	b662      	cpsie	i
	isb
     fa4:	f3bf 8f6f 	isb	sy

	bx	lr
     fa8:	4770      	bx	lr
     faa:	bf00      	nop

00000fac <arch_cpu_atomic_idle>:

	/*
	 * Lock PRIMASK while sleeping: wfe will still get interrupted by
	 * incoming interrupts but the CPU will not service them right away.
	 */
	cpsid	i
     fac:	b672      	cpsid	i
	cpsie	i
_irq_disabled:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* r1: zero, for setting BASEPRI (needs a register) */
	eors.n	r1, r1
     fae:	4049      	eors	r1, r1

	/* unlock BASEPRI so wfe gets interrupted by incoming interrupts */
	msr	BASEPRI, r1
     fb0:	f381 8811 	msr	BASEPRI, r1

	wfe
     fb4:	bf20      	wfe

	msr	BASEPRI, r0
     fb6:	f380 8811 	msr	BASEPRI, r0
	cpsie	i
     fba:	b662      	cpsie	i
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
	bx	lr
     fbc:	4770      	bx	lr
     fbe:	bf00      	nop

00000fc0 <arch_irq_enable>:
#define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
#define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)

void arch_irq_enable(unsigned int irq)
{
	NVIC_EnableIRQ((IRQn_Type)irq);
     fc0:	b243      	sxtb	r3, r0
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
     fc2:	2b00      	cmp	r3, #0
     fc4:	db08      	blt.n	fd8 <arch_irq_enable+0x18>
  {
    __COMPILER_BARRIER();
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
     fc6:	2201      	movs	r2, #1
     fc8:	f000 001f 	and.w	r0, r0, #31
     fcc:	fa02 f000 	lsl.w	r0, r2, r0
     fd0:	095b      	lsrs	r3, r3, #5
     fd2:	4a02      	ldr	r2, [pc, #8]	; (fdc <arch_irq_enable+0x1c>)
     fd4:	f842 0023 	str.w	r0, [r2, r3, lsl #2]
}
     fd8:	4770      	bx	lr
     fda:	bf00      	nop
     fdc:	e000e100 	.word	0xe000e100

00000fe0 <arch_irq_is_enabled>:
	NVIC_DisableIRQ((IRQn_Type)irq);
}

int arch_irq_is_enabled(unsigned int irq)
{
	return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq));
     fe0:	4b05      	ldr	r3, [pc, #20]	; (ff8 <arch_irq_is_enabled+0x18>)
     fe2:	0942      	lsrs	r2, r0, #5
     fe4:	f000 001f 	and.w	r0, r0, #31
     fe8:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
     fec:	2301      	movs	r3, #1
     fee:	fa03 f000 	lsl.w	r0, r3, r0
}
     ff2:	4010      	ands	r0, r2
     ff4:	4770      	bx	lr
     ff6:	bf00      	nop
     ff8:	e000e100 	.word	0xe000e100

00000ffc <z_arm_irq_priority_set>:
	 */
	__ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1),
		 "invalid priority %d for %d irq! values must be less than %lu\n",
		 prio - _IRQ_PRIO_OFFSET, irq,
		 BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
	NVIC_SetPriority((IRQn_Type)irq, prio);
     ffc:	b243      	sxtb	r3, r0
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
  if ((int32_t)(IRQn) >= 0)
     ffe:	2b00      	cmp	r3, #0
  {
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1000:	bfa8      	it	ge
    1002:	f103 4360 	addge.w	r3, r3, #3758096384	; 0xe0000000
		prio += _IRQ_PRIO_OFFSET;
    1006:	f101 0101 	add.w	r1, r1, #1
  }
  else
  {
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    100a:	bfb8      	it	lt
    100c:	4b06      	ldrlt	r3, [pc, #24]	; (1028 <CONFIG_FPROTECT_BLOCK_SIZE+0x28>)
    100e:	ea4f 1141 	mov.w	r1, r1, lsl #5
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1012:	bfac      	ite	ge
    1014:	f503 4361 	addge.w	r3, r3, #57600	; 0xe100
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1018:	f000 000f 	andlt.w	r0, r0, #15
    101c:	b2c9      	uxtb	r1, r1
    101e:	bfb4      	ite	lt
    1020:	5419      	strblt	r1, [r3, r0]
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1022:	f883 1300 	strbge.w	r1, [r3, #768]	; 0x300
}
    1026:	4770      	bx	lr
    1028:	e000ed14 	.word	0xe000ed14

0000102c <z_SysNmiOnReset>:
_ASM_FILE_PROLOGUE

GTEXT(z_SysNmiOnReset)

SECTION_FUNC(TEXT, z_SysNmiOnReset)
    wfi
    102c:	bf30      	wfi
    b z_SysNmiOnReset
    102e:	f7ff bffd 	b.w	102c <z_SysNmiOnReset>
    1032:	bf00      	nop

00001034 <z_arm_prep_c>:

#define VECTOR_ADDRESS ((uintptr_t)_vector_start)

static inline void relocate_vector_table(void)
{
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    1034:	4a0b      	ldr	r2, [pc, #44]	; (1064 <z_arm_prep_c+0x30>)
 * This routine prepares for the execution of and runs C code.
 *
 * @return N/A
 */
void z_arm_prep_c(void)
{
    1036:	b508      	push	{r3, lr}
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    1038:	4b0b      	ldr	r3, [pc, #44]	; (1068 <z_arm_prep_c+0x34>)
    103a:	f022 027f 	bic.w	r2, r2, #127	; 0x7f
    103e:	609a      	str	r2, [r3, #8]
  \details Acts as a special kind of Data Memory Barrier.
           It completes when all explicit memory accesses before this instruction complete.
 */
__STATIC_FORCEINLINE void __DSB(void)
{
  __ASM volatile ("dsb 0xF":::"memory");
    1040:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    1044:	f3bf 8f6f 	isb	sy
	SCB->CPACR &= (~(CPACR_CP10_Msk | CPACR_CP11_Msk));
    1048:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
    104c:	f422 0270 	bic.w	r2, r2, #15728640	; 0xf00000
    1050:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
	relocate_vector_table();
#if defined(CONFIG_CPU_HAS_FPU)
	z_arm_floating_point_init();
#endif
	z_bss_zero();
    1054:	f002 fa04 	bl	3460 <z_bss_zero>
	z_data_copy();
    1058:	f002 fe7e 	bl	3d58 <z_data_copy>
#if ((defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)) && defined(CONFIG_INIT_STACKS))
	z_arm_init_stacks();
#endif
	z_arm_interrupt_init();
    105c:	f000 f9d0 	bl	1400 <z_arm_interrupt_init>
	z_cstart();
    1060:	f002 fa08 	bl	3474 <z_cstart>
    1064:	00000000 	.word	0x00000000
    1068:	e000ed00 	.word	0xe000ed00

0000106c <arch_swap>:
 * as BASEPRI is not available.
 */
int arch_swap(unsigned int key)
{
	/* store off key and return value */
	_current->arch.basepri = key;
    106c:	4a09      	ldr	r2, [pc, #36]	; (1094 <arch_swap+0x28>)
	_current->arch.swap_return_value = _k_neg_eagain;
    106e:	490a      	ldr	r1, [pc, #40]	; (1098 <arch_swap+0x2c>)
	_current->arch.basepri = key;
    1070:	6893      	ldr	r3, [r2, #8]
	_current->arch.swap_return_value = _k_neg_eagain;
    1072:	6809      	ldr	r1, [r1, #0]
    1074:	6799      	str	r1, [r3, #120]	; 0x78

#if defined(CONFIG_CPU_CORTEX_M)
	/* set pending bit to make sure we will take a PendSV exception */
	SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    1076:	4909      	ldr	r1, [pc, #36]	; (109c <arch_swap+0x30>)
	_current->arch.basepri = key;
    1078:	6758      	str	r0, [r3, #116]	; 0x74
	SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    107a:	684b      	ldr	r3, [r1, #4]
    107c:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
    1080:	604b      	str	r3, [r1, #4]
	__asm__ volatile(
    1082:	2300      	movs	r3, #0
    1084:	f383 8811 	msr	BASEPRI, r3
    1088:	f3bf 8f6f 	isb	sy
#endif

	/* Context switch is performed here. Returning implies the
	 * thread has been context-switched-in again.
	 */
	return _current->arch.swap_return_value;
    108c:	6893      	ldr	r3, [r2, #8]
}
    108e:	6f98      	ldr	r0, [r3, #120]	; 0x78
    1090:	4770      	bx	lr
    1092:	bf00      	nop
    1094:	20000334 	.word	0x20000334
    1098:	00004ed0 	.word	0x00004ed0
    109c:	e000ed00 	.word	0xe000ed00

000010a0 <z_arm_pendsv>:
    pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_INSTRUMENT_THREAD_SWITCHING */

    /* load _kernel into r1 and current k_thread into r2 */
    ldr r1, =_kernel
    10a0:	4912      	ldr	r1, [pc, #72]	; (10ec <z_arm_pendsv+0x4c>)
    ldr r2, [r1, #_kernel_offset_to_current]
    10a2:	688a      	ldr	r2, [r1, #8]
    /* Store LSB of LR (EXC_RETURN) to the thread's 'mode' word. */
    strb lr, [r2, #_thread_offset_to_mode_exc_return]
#endif

    /* addr of callee-saved regs in thread in r0 */
    ldr r0, =_thread_offset_to_callee_saved
    10a4:	f04f 0030 	mov.w	r0, #48	; 0x30
    add r0, r2
    10a8:	4410      	add	r0, r2

    /* save callee-saved + psp in thread */
#if defined(CONFIG_CPU_CORTEX_M)
    mrs ip, PSP
    10aa:	f3ef 8c09 	mrs	ip, PSP
    mov r6, r11
    mov r7, ip
    /* store r8-12 */
    stmea r0!, {r3-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    stmia r0, {v1-v8, ip}
    10ae:	e880 1ff0 	stmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}

    /* Protect the kernel state while we play with the thread lists */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    10b2:	2020      	movs	r0, #32
    msr BASEPRI_MAX, r0
    10b4:	f380 8812 	msr	BASEPRI_MAX, r0
    isb /* Make the effect of disabling interrupts be realized immediately */
    10b8:	f3bf 8f6f 	isb	sy
     * the new thread is context-switched in since all decisions
     * to pend PendSV have been taken with the current kernel
     * state and this is what we're handling currently.
     */
#if defined(CONFIG_CPU_CORTEX_M)
    ldr v4, =_SCS_ICSR
    10bc:	4f0c      	ldr	r7, [pc, #48]	; (10f0 <z_arm_pendsv+0x50>)
    ldr v3, =_SCS_ICSR_UNPENDSV
    10be:	f04f 6600 	mov.w	r6, #134217728	; 0x8000000
#endif

    /* _kernel is still in r1 */

    /* fetch the thread to run from the ready queue cache */
    ldr r2, [r1, #_kernel_offset_to_ready_q_cache]
    10c2:	69ca      	ldr	r2, [r1, #28]

    str r2, [r1, #_kernel_offset_to_current]
    10c4:	608a      	str	r2, [r1, #8]
     * has been handled.
     */

    /* _SCS_ICSR is still in v4 and _SCS_ICSR_UNPENDSV in v3 */
#if defined(CONFIG_CPU_CORTEX_M)
    str v3, [v4, #0]
    10c6:	603e      	str	r6, [r7, #0]

    ldr r0, [r4]
    movs.n r3, #0
    str r3, [r4]
#else
    ldr r0, [r2, #_thread_offset_to_basepri]
    10c8:	6f50      	ldr	r0, [r2, #116]	; 0x74
    movs r3, #0
    10ca:	2300      	movs	r3, #0
    str r3, [r2, #_thread_offset_to_basepri]
    10cc:	6753      	str	r3, [r2, #116]	; 0x74
    /* restore r4-r7, go back 9*4 bytes to the start of the stored block */
    subs r0, #36
    ldmia r0!, {r4-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    /* restore BASEPRI for the incoming thread */
    msr BASEPRI, r0
    10ce:	f380 8811 	msr	BASEPRI, r0
    isb
#endif

#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
    /* Re-program dynamic memory map */
    push {r2,lr}
    10d2:	b504      	push	{r2, lr}
    mov r0, r2 /* _current thread */
    10d4:	4610      	mov	r0, r2
    bl z_arm_configure_dynamic_mpu_regions
    10d6:	f000 fa29 	bl	152c <z_arm_configure_dynamic_mpu_regions>
    pop {r2,lr}
    10da:	e8bd 4004 	ldmia.w	sp!, {r2, lr}
    isb

#endif

    /* load callee-saved + psp from thread */
    add r0, r2, #_thread_offset_to_callee_saved
    10de:	f102 0030 	add.w	r0, r2, #48	; 0x30
    ldmia r0, {v1-v8, ip}
    10e2:	e890 1ff0 	ldmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
    msr PSP, ip
    10e6:	f38c 8809 	msr	PSP, ip

    /*
     * Cortex-M: return from PendSV exception
     * Cortex-R: return to the caller (z_arm_{exc,int}_exit, or z_arm_svc)
     */
    bx lr
    10ea:	4770      	bx	lr
    ldr r1, =_kernel
    10ec:	20000334 	.word	0x20000334
    ldr v4, =_SCS_ICSR
    10f0:	e000ed04 	.word	0xe000ed04

000010f4 <z_arm_svc>:
  bne _stack_frame_endif
_stack_frame_msp:
  mrs r0, MSP
_stack_frame_endif:
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    tst lr, #_EXC_RETURN_SPSEL_Msk /* did we come from thread mode ? */
    10f4:	f01e 0f04 	tst.w	lr, #4
    ite eq  /* if zero (equal), came from handler mode */
    10f8:	bf0c      	ite	eq
        mrseq r0, MSP   /* handler mode, stack frame is on MSP */
    10fa:	f3ef 8008 	mrseq	r0, MSP
        mrsne r0, PSP   /* thread mode, stack frame is on PSP */
    10fe:	f3ef 8009 	mrsne	r0, PSP
#endif


    /* Figure out what SVC call number was invoked */

    ldr r1, [r0, #24]   /* grab address of PC from stack frame */
    1102:	6981      	ldr	r1, [r0, #24]
     */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    subs r1, r1, #2
    ldrb r1, [r1]
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    ldrb r1, [r1, #-2]
    1104:	f811 1c02 	ldrb.w	r1, [r1, #-2]
#endif
    bne _oops

#endif /* CONFIG_USERSPACE */

    cmp r1, #2
    1108:	2902      	cmp	r1, #2
    beq _oops
    110a:	d0ff      	beq.n	110c <_oops>

0000110c <_oops>:
    /* exception return is done in z_arm_int_exit() */
    b z_arm_int_exit
#endif

_oops:
    push {r0, lr}
    110c:	b501      	push	{r0, lr}
    bl z_do_kernel_oops
    110e:	f003 f912 	bl	4336 <z_do_kernel_oops>
    /* return from SVC exception is done here */
    pop {r0, pc}
    1112:	bd01      	pop	{r0, pc}

00001114 <arch_new_thread>:

#if defined(CONFIG_CPU_CORTEX_M)
	/* force ARM mode by clearing LSB of address */
	iframe->pc &= 0xfffffffe;
#endif
	iframe->a1 = (uint32_t)entry;
    1114:	f842 3c20 	str.w	r3, [r2, #-32]
	iframe->a2 = (uint32_t)p1;
    1118:	9b00      	ldr	r3, [sp, #0]
    111a:	f842 3c1c 	str.w	r3, [r2, #-28]
	iframe->pc &= 0xfffffffe;
    111e:	490a      	ldr	r1, [pc, #40]	; (1148 <arch_new_thread+0x34>)
	iframe->a3 = (uint32_t)p2;
    1120:	9b01      	ldr	r3, [sp, #4]
    1122:	f842 3c18 	str.w	r3, [r2, #-24]
	iframe->a4 = (uint32_t)p3;
    1126:	9b02      	ldr	r3, [sp, #8]
    1128:	f842 3c14 	str.w	r3, [r2, #-20]
	iframe->pc &= 0xfffffffe;
    112c:	f021 0101 	bic.w	r1, r1, #1

#if defined(CONFIG_CPU_CORTEX_M)
	iframe->xpsr =
    1130:	f04f 7380 	mov.w	r3, #16777216	; 0x1000000
    1134:	f842 3c04 	str.w	r3, [r2, #-4]
	iframe->pc &= 0xfffffffe;
    1138:	f842 1c08 	str.w	r1, [r2, #-8]
	iframe->xpsr |= T_BIT;
#endif /* CONFIG_COMPILER_ISA_THUMB2 */
#endif /* CONFIG_CPU_CORTEX_M */

	thread->callee_saved.psp = (uint32_t)iframe;
	thread->arch.basepri = 0;
    113c:	2300      	movs	r3, #0
	iframe = Z_STACK_PTR_TO_FRAME(struct __basic_sf, stack_ptr);
    113e:	3a20      	subs	r2, #32
	thread->callee_saved.psp = (uint32_t)iframe;
    1140:	6502      	str	r2, [r0, #80]	; 0x50
	thread->arch.basepri = 0;
    1142:	6743      	str	r3, [r0, #116]	; 0x74
#endif
	/*
	 * initial values in all other registers/thread entries are
	 * irrelevant.
	 */
}
    1144:	4770      	bx	lr
    1146:	bf00      	nop
    1148:	00004251 	.word	0x00004251

0000114c <z_check_thread_stack_fail>:
 *         thread stack corruption, otherwise return 0.
 */
uint32_t z_check_thread_stack_fail(const uint32_t fault_addr, const uint32_t psp)
{
#if defined(CONFIG_MULTITHREADING)
	const struct k_thread *thread = _current;
    114c:	4a0b      	ldr	r2, [pc, #44]	; (117c <z_check_thread_stack_fail+0x30>)
{
    114e:	4603      	mov	r3, r0
	const struct k_thread *thread = _current;
    1150:	6890      	ldr	r0, [r2, #8]

	if (thread == NULL) {
    1152:	b190      	cbz	r0, 117a <z_check_thread_stack_fail+0x2e>
			return thread->stack_info.start;
		}
	}
#else /* CONFIG_USERSPACE */
#if defined(CONFIG_MULTITHREADING)
	if (IS_MPU_GUARD_VIOLATION(thread->stack_info.start - guard_len,
    1154:	f113 0f16 	cmn.w	r3, #22
    1158:	6e40      	ldr	r0, [r0, #100]	; 0x64
    115a:	d005      	beq.n	1168 <z_check_thread_stack_fail+0x1c>
    115c:	f1a0 0220 	sub.w	r2, r0, #32
    1160:	429a      	cmp	r2, r3
    1162:	d806      	bhi.n	1172 <z_check_thread_stack_fail+0x26>
    1164:	4283      	cmp	r3, r0
    1166:	d204      	bcs.n	1172 <z_check_thread_stack_fail+0x26>
    1168:	4281      	cmp	r1, r0
    116a:	bf2c      	ite	cs
    116c:	2100      	movcs	r1, #0
    116e:	2101      	movcc	r1, #1
    1170:	e000      	b.n	1174 <z_check_thread_stack_fail+0x28>
    1172:	2100      	movs	r1, #0
    1174:	2900      	cmp	r1, #0
		return (uint32_t)Z_THREAD_STACK_BUFFER(z_main_stack);
	}
#endif
#endif /* CONFIG_USERSPACE */

	return 0;
    1176:	bf08      	it	eq
    1178:	2000      	moveq	r0, #0
}
    117a:	4770      	bx	lr
    117c:	20000334 	.word	0x20000334

00001180 <arch_switch_to_main_thread>:
#endif /* CONFIG_FPU */
}

void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr,
				k_thread_entry_t _main)
{
    1180:	b508      	push	{r3, lr}
	z_arm_prepare_switch_to_main();

	_current = main_thread;
    1182:	4b09      	ldr	r3, [pc, #36]	; (11a8 <arch_switch_to_main_thread+0x28>)
    1184:	6098      	str	r0, [r3, #8]
{
    1186:	460d      	mov	r5, r1
    1188:	4614      	mov	r4, r2
#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
	/*
	 * If stack protection is enabled, make sure to set it
	 * before jumping to thread entry function
	 */
	z_arm_configure_dynamic_mpu_regions(main_thread);
    118a:	f000 f9cf 	bl	152c <z_arm_configure_dynamic_mpu_regions>

	/*
	 * Set PSP to the highest address of the main stack
	 * before enabling interrupts and jumping to main.
	 */
	__asm__ volatile (
    118e:	4620      	mov	r0, r4
    1190:	f385 8809 	msr	PSP, r5
    1194:	2100      	movs	r1, #0
    1196:	b663      	cpsie	if
    1198:	f381 8811 	msr	BASEPRI, r1
    119c:	f3bf 8f6f 	isb	sy
    11a0:	2200      	movs	r2, #0
    11a2:	2300      	movs	r3, #0
    11a4:	f003 f854 	bl	4250 <z_thread_entry>
	:
	: "r" (_main), "r" (stack_ptr)
	: "r0" /* not to be overwritten by msr PSP, %1 */
	);

	CODE_UNREACHABLE;
    11a8:	20000334 	.word	0x20000334

000011ac <_isr_wrapper>:
 * @return N/A
 */
SECTION_FUNC(TEXT, _isr_wrapper)

#if defined(CONFIG_CPU_CORTEX_M)
	push {r0,lr}		/* r0, lr are now the first items on the stack */
    11ac:	b501      	push	{r0, lr}
	 * Disable interrupts to prevent nesting while exiting idle state. This
	 * is only necessary for the Cortex-M because it is the only ARM
	 * architecture variant that automatically enables interrupts when
	 * entering an ISR.
	 */
	cpsid i  /* PRIMASK = 1 */
    11ae:	b672      	cpsid	i
#endif

	/* is this a wakeup from idle ? */
	ldr r2, =_kernel
    11b0:	4a0b      	ldr	r2, [pc, #44]	; (11e0 <_isr_wrapper+0x34>)
	/* requested idle duration, in ticks */
	ldr r0, [r2, #_kernel_offset_to_idle]
    11b2:	6990      	ldr	r0, [r2, #24]
	cmp r0, #0
    11b4:	2800      	cmp	r0, #0
	str r1, [r2, #_kernel_offset_to_idle]
	bl z_pm_save_idle_exit
_idle_state_cleared:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	ittt ne
    11b6:	bf1e      	ittt	ne
	movne	r1, #0
    11b8:	2100      	movne	r1, #0
		/* clear kernel idle state */
		strne	r1, [r2, #_kernel_offset_to_idle]
    11ba:	6191      	strne	r1, [r2, #24]
		blne	z_pm_save_idle_exit
    11bc:	f003 fc0a 	blne	49d4 <z_pm_save_idle_exit>
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
	cpsie i		/* re-enable interrupts (PRIMASK = 0) */
    11c0:	b662      	cpsie	i
#endif

#endif /* CONFIG_PM */

#if defined(CONFIG_CPU_CORTEX_M)
	mrs r0, IPSR	/* get exception number */
    11c2:	f3ef 8005 	mrs	r0, IPSR
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r1, =16
	subs r0, r1	/* get IRQ number */
	lsls r0, #3	/* table is 8-byte wide */
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	sub r0, r0, #16	/* get IRQ number */
    11c6:	f1a0 0010 	sub.w	r0, r0, #16
	lsl r0, r0, #3	/* table is 8-byte wide */
    11ca:	ea4f 00c0 	mov.w	r0, r0, lsl #3
	lsl r1, r1, #3
	cmp r0, r1
	bge spurious_continue
#endif /* !CONFIG_CPU_CORTEX_M */

	ldr r1, =_sw_isr_table
    11ce:	4905      	ldr	r1, [pc, #20]	; (11e4 <_isr_wrapper+0x38>)
	add r1, r1, r0	/* table entry: ISRs must have their MSB set to stay
    11d0:	4401      	add	r1, r0
			 * in thumb mode */

	ldm r1!,{r0,r3}	/* arg in r0, ISR in r3 */
    11d2:	c909      	ldmia	r1!, {r0, r3}
	blx r3		/* call ISR */
    11d4:	4798      	blx	r3

#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	pop {r0, r3}
	mov lr, r3
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	pop {r0, lr}
    11d6:	e8bd 4001 	ldmia.w	sp!, {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

	/* Use 'bx' instead of 'b' because 'bx' can jump further, and use
	 * 'bx' instead of 'blx' because exception return is done in
	 * z_arm_int_exit() */
	ldr r1, =z_arm_int_exit
    11da:	4903      	ldr	r1, [pc, #12]	; (11e8 <_isr_wrapper+0x3c>)
	bx r1
    11dc:	4708      	bx	r1
    11de:	0000      	.short	0x0000
	ldr r2, =_kernel
    11e0:	20000334 	.word	0x20000334
	ldr r1, =_sw_isr_table
    11e4:	00004c74 	.word	0x00004c74
	ldr r1, =z_arm_int_exit
    11e8:	000011ed 	.word	0x000011ed

000011ec <z_arm_exc_exit>:
 */

SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_exc_exit)

#ifdef CONFIG_PREEMPT_ENABLED
	ldr r3, =_kernel
    11ec:	4b04      	ldr	r3, [pc, #16]	; (1200 <_EXIT_EXC+0x2>)

	ldr r1, [r3, #_kernel_offset_to_current]
    11ee:	6899      	ldr	r1, [r3, #8]
	ldr r0, [r3, #_kernel_offset_to_ready_q_cache]
    11f0:	69d8      	ldr	r0, [r3, #28]
	cmp r0, r1
    11f2:	4288      	cmp	r0, r1
	beq _EXIT_EXC
    11f4:	d003      	beq.n	11fe <_EXIT_EXC>

	/* context switch required, pend the PendSV exception */
	ldr r1, =_SCS_ICSR
    11f6:	4903      	ldr	r1, [pc, #12]	; (1204 <_EXIT_EXC+0x6>)
	ldr r2, =_SCS_ICSR_PENDSV
    11f8:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
	str r2, [r1]
    11fc:	600a      	str	r2, [r1, #0]

000011fe <_EXIT_EXC>:
#else
	pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_STACK_SENTINEL */

	bx lr
    11fe:	4770      	bx	lr
	ldr r3, =_kernel
    1200:	20000334 	.word	0x20000334
	ldr r1, =_SCS_ICSR
    1204:	e000ed04 	.word	0xe000ed04

00001208 <mem_manage_fault>:
 *
 * @return error code to identify the fatal error reason
 */
static uint32_t mem_manage_fault(z_arch_esf_t *esf, int from_hard_fault,
			      bool *recoverable)
{
    1208:	b538      	push	{r3, r4, r5, lr}
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	uint32_t mmfar = -EINVAL;

	PR_FAULT_INFO("***** MPU FAULT *****");

	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
    120a:	4b19      	ldr	r3, [pc, #100]	; (1270 <mem_manage_fault+0x68>)
{
    120c:	4614      	mov	r4, r2
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
    120e:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Stacking error (context area might be"
			" not valid)");
	}
	if ((SCB->CFSR & SCB_CFSR_MUNSTKERR_Msk) != 0) {
    1210:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Unstacking error");
	}
	if ((SCB->CFSR & SCB_CFSR_DACCVIOL_Msk) != 0) {
    1212:	6a9a      	ldr	r2, [r3, #40]	; 0x28
{
    1214:	4605      	mov	r5, r0
	if ((SCB->CFSR & SCB_CFSR_DACCVIOL_Msk) != 0) {
    1216:	0790      	lsls	r0, r2, #30
    1218:	d519      	bpl.n	124e <mem_manage_fault+0x46>
		 * The MMFAR address is valid only if this bit is 1.
		 *
		 * Software must follow this sequence because another higher
		 * priority exception might change the MMFAR value.
		 */
		uint32_t temp = SCB->MMFAR;
    121a:	6b58      	ldr	r0, [r3, #52]	; 0x34

		if ((SCB->CFSR & SCB_CFSR_MMARVALID_Msk) != 0) {
    121c:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    121e:	0612      	lsls	r2, r2, #24
    1220:	d515      	bpl.n	124e <mem_manage_fault+0x46>
			mmfar = temp;
			PR_EXC("  MMFAR Address: 0x%x", mmfar);
			if (from_hard_fault != 0) {
    1222:	b119      	cbz	r1, 122c <mem_manage_fault+0x24>
				/* clear SCB_MMAR[VALID] to reset */
				SCB->CFSR &= ~SCB_CFSR_MMARVALID_Msk;
    1224:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    1226:	f022 0280 	bic.w	r2, r2, #128	; 0x80
    122a:	629a      	str	r2, [r3, #40]	; 0x28
			}
		}
	}
	if ((SCB->CFSR & SCB_CFSR_IACCVIOL_Msk) != 0) {
    122c:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Instruction Access Violation");
	}
#if defined(CONFIG_ARMV7_M_ARMV8_M_FP)
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    122e:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	 * crossed into an area beyond the thread stack.]
	 *
	 * Data Access Violation errors may or may not be caused by
	 * thread stack overflows.
	 */
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) ||
    1230:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    1232:	06d1      	lsls	r1, r2, #27
    1234:	d40e      	bmi.n	1254 <mem_manage_fault+0x4c>
		(SCB->CFSR & SCB_CFSR_DACCVIOL_Msk)) {
    1236:	6a9b      	ldr	r3, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) ||
    1238:	079a      	lsls	r2, r3, #30
    123a:	d40b      	bmi.n	1254 <mem_manage_fault+0x4c>
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    123c:	2000      	movs	r0, #0
		"without stack guard, user-mode or null-pointer detection\n");
#endif /* CONFIG_MPU_STACK_GUARD || CONFIG_USERSPACE */
	}

	/* clear MMFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_MEMFAULTSR_Msk;
    123e:	4a0c      	ldr	r2, [pc, #48]	; (1270 <mem_manage_fault+0x68>)
    1240:	6a93      	ldr	r3, [r2, #40]	; 0x28
    1242:	f043 03ff 	orr.w	r3, r3, #255	; 0xff
    1246:	6293      	str	r3, [r2, #40]	; 0x28

	/* Assess whether system shall ignore/recover from this MPU fault. */
	*recoverable = memory_fault_recoverable(esf, true);
    1248:	2300      	movs	r3, #0
    124a:	7023      	strb	r3, [r4, #0]

	return reason;
}
    124c:	bd38      	pop	{r3, r4, r5, pc}
	uint32_t mmfar = -EINVAL;
    124e:	f06f 0015 	mvn.w	r0, #21
    1252:	e7eb      	b.n	122c <mem_manage_fault+0x24>
		if (SCB->ICSR & SCB_ICSR_RETTOBASE_Msk) {
    1254:	4b06      	ldr	r3, [pc, #24]	; (1270 <mem_manage_fault+0x68>)
    1256:	685b      	ldr	r3, [r3, #4]
    1258:	051b      	lsls	r3, r3, #20
    125a:	d5ef      	bpl.n	123c <mem_manage_fault+0x34>
			uint32_t min_stack_ptr = z_check_thread_stack_fail(mmfar,
    125c:	4629      	mov	r1, r5
    125e:	f7ff ff75 	bl	114c <z_check_thread_stack_fail>
			if (min_stack_ptr) {
    1262:	2800      	cmp	r0, #0
    1264:	d0ea      	beq.n	123c <mem_manage_fault+0x34>
  \details Assigns the given value to the Process Stack Pointer (PSP).
  \param [in]    topOfProcStack  Process Stack Pointer value to set
 */
__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
{
  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
    1266:	f380 8809 	msr	PSP, r0
				reason = K_ERR_STACK_CHK_FAIL;
    126a:	2002      	movs	r0, #2
    126c:	e7e7      	b.n	123e <mem_manage_fault+0x36>
    126e:	bf00      	nop
    1270:	e000ed00 	.word	0xe000ed00

00001274 <bus_fault.isra.0>:
{
	uint32_t reason = K_ERR_CPU_EXCEPTION;

	PR_FAULT_INFO("***** BUS FAULT *****");

	if (SCB->CFSR & SCB_CFSR_STKERR_Msk) {
    1274:	4b0d      	ldr	r3, [pc, #52]	; (12ac <bus_fault.isra.0+0x38>)
    1276:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Stacking error");
	}
	if (SCB->CFSR & SCB_CFSR_UNSTKERR_Msk) {
    1278:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Unstacking error");
	}
	if (SCB->CFSR & SCB_CFSR_PRECISERR_Msk) {
    127a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    127c:	0592      	lsls	r2, r2, #22
    127e:	d508      	bpl.n	1292 <bus_fault.isra.0+0x1e>
		 * The BFAR address is valid only if this bit is 1.
		 *
		 * Software must follow this sequence because another
		 * higher priority exception might change the BFAR value.
		 */
		STORE_xFAR(bfar, SCB->BFAR);
    1280:	6b9a      	ldr	r2, [r3, #56]	; 0x38

		if ((SCB->CFSR & SCB_CFSR_BFARVALID_Msk) != 0) {
    1282:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    1284:	0412      	lsls	r2, r2, #16
    1286:	d504      	bpl.n	1292 <bus_fault.isra.0+0x1e>
			PR_EXC("  BFAR Address: 0x%x", bfar);
			if (from_hard_fault != 0) {
    1288:	b118      	cbz	r0, 1292 <bus_fault.isra.0+0x1e>
				/* clear SCB_CFSR_BFAR[VALID] to reset */
				SCB->CFSR &= ~SCB_CFSR_BFARVALID_Msk;
    128a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    128c:	f422 4200 	bic.w	r2, r2, #32768	; 0x8000
    1290:	629a      	str	r2, [r3, #40]	; 0x28
			}
		}
	}
	if (SCB->CFSR & SCB_CFSR_IMPRECISERR_Msk) {
    1292:	4b06      	ldr	r3, [pc, #24]	; (12ac <bus_fault.isra.0+0x38>)
    1294:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Imprecise data bus error");
	}
	if ((SCB->CFSR & SCB_CFSR_IBUSERR_Msk) != 0) {
    1296:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    1298:	05d2      	lsls	r2, r2, #23
		PR_FAULT_INFO("  Instruction bus error");
#if !defined(CONFIG_ARMV7_M_ARMV8_M_FP)
	}
#else
	} else if (SCB->CFSR & SCB_CFSR_LSPERR_Msk) {
    129a:	bf58      	it	pl
    129c:	6a9a      	ldrpl	r2, [r3, #40]	; 0x28
		SYSMPU->CESR &= ~sperr;
	}
#endif /* defined(CONFIG_ARM_MPU) && defined(CONFIG_CPU_HAS_NXP_MPU) */

	/* clear BFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
    129e:	6a9a      	ldr	r2, [r3, #40]	; 0x28

	*recoverable = memory_fault_recoverable(esf, true);
    12a0:	2000      	movs	r0, #0
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
    12a2:	f442 427f 	orr.w	r2, r2, #65280	; 0xff00
    12a6:	629a      	str	r2, [r3, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf, true);
    12a8:	7008      	strb	r0, [r1, #0]

	return reason;
}
    12aa:	4770      	bx	lr
    12ac:	e000ed00 	.word	0xe000ed00

000012b0 <usage_fault.isra.0>:
	uint32_t reason = K_ERR_CPU_EXCEPTION;

	PR_FAULT_INFO("***** USAGE FAULT *****");

	/* bits are sticky: they stack and must be reset */
	if ((SCB->CFSR & SCB_CFSR_DIVBYZERO_Msk) != 0) {
    12b0:	4b07      	ldr	r3, [pc, #28]	; (12d0 <usage_fault.isra.0+0x20>)
    12b2:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Division by zero");
	}
	if ((SCB->CFSR & SCB_CFSR_UNALIGNED_Msk) != 0) {
    12b4:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		 */
		reason = K_ERR_STACK_CHK_FAIL;
#endif /* CONFIG_BUILTIN_STACK_GUARD */
	}
#endif /* CONFIG_ARMV8_M_MAINLINE */
	if ((SCB->CFSR & SCB_CFSR_NOCP_Msk) != 0) {
    12b6:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  No coprocessor instructions");
	}
	if ((SCB->CFSR & SCB_CFSR_INVPC_Msk) != 0) {
    12b8:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Illegal load of EXC_RETURN into PC");
	}
	if ((SCB->CFSR & SCB_CFSR_INVSTATE_Msk) != 0) {
    12ba:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Illegal use of the EPSR");
	}
	if ((SCB->CFSR & SCB_CFSR_UNDEFINSTR_Msk) != 0) {
    12bc:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Attempt to execute undefined instruction");
	}

	/* clear UFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    12be:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    12c0:	ea6f 4202 	mvn.w	r2, r2, lsl #16
    12c4:	ea6f 4212 	mvn.w	r2, r2, lsr #16
    12c8:	629a      	str	r2, [r3, #40]	; 0x28

	return reason;
}
    12ca:	2000      	movs	r0, #0
    12cc:	4770      	bx	lr
    12ce:	bf00      	nop
    12d0:	e000ed00 	.word	0xe000ed00

000012d4 <z_arm_fault>:
 * @param callee_regs Callee-saved registers (R4-R11, PSP)
 *
 */
void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return,
	_callee_saved_t *callee_regs)
{
    12d4:	b570      	push	{r4, r5, r6, lr}
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    12d6:	4b3e      	ldr	r3, [pc, #248]	; (13d0 <z_arm_fault+0xfc>)
    12d8:	685b      	ldr	r3, [r3, #4]
{
    12da:	b08a      	sub	sp, #40	; 0x28
    12dc:	460d      	mov	r5, r1
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    12de:	f3c3 0308 	ubfx	r3, r3, #0, #9
    12e2:	2600      	movs	r6, #0
    12e4:	f386 8811 	msr	BASEPRI, r6
    12e8:	f3bf 8f6f 	isb	sy
	if ((exc_return & EXC_RETURN_INDICATOR_PREFIX) !=
    12ec:	f002 417f 	and.w	r1, r2, #4278190080	; 0xff000000
    12f0:	f1b1 4f7f 	cmp.w	r1, #4278190080	; 0xff000000
    12f4:	d111      	bne.n	131a <z_arm_fault+0x46>
	if ((exc_return & EXC_RETURN_MODE_THREAD) &&
    12f6:	f002 010c 	and.w	r1, r2, #12
    12fa:	2908      	cmp	r1, #8
    12fc:	d00d      	beq.n	131a <z_arm_fault+0x46>
		if (exc_return & EXC_RETURN_MODE_THREAD) {
    12fe:	0712      	lsls	r2, r2, #28
    1300:	d401      	bmi.n	1306 <z_arm_fault+0x32>
			ptr_esf = (z_arch_esf_t *)msp;
    1302:	4605      	mov	r5, r0
			*nested_exc = true;
    1304:	2601      	movs	r6, #1
	*recoverable = false;
    1306:	2200      	movs	r2, #0
    1308:	3b03      	subs	r3, #3
    130a:	f88d 2007 	strb.w	r2, [sp, #7]
	switch (fault) {
    130e:	2b03      	cmp	r3, #3
    1310:	d857      	bhi.n	13c2 <z_arm_fault+0xee>
    1312:	e8df f003 	tbb	[pc, r3]
    1316:	4e04      	.short	0x4e04
    1318:	4b52      	.short	0x4b52
		return NULL;
    131a:	4635      	mov	r5, r6
    131c:	e7f3      	b.n	1306 <z_arm_fault+0x32>
	if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk) != 0) {
    131e:	4b2c      	ldr	r3, [pc, #176]	; (13d0 <z_arm_fault+0xfc>)
    1320:	6adc      	ldr	r4, [r3, #44]	; 0x2c
    1322:	f014 0402 	ands.w	r4, r4, #2
    1326:	d14c      	bne.n	13c2 <z_arm_fault+0xee>
	} else if ((SCB->HFSR & SCB_HFSR_DEBUGEVT_Msk) != 0) {
    1328:	6ada      	ldr	r2, [r3, #44]	; 0x2c
    132a:	2a00      	cmp	r2, #0
    132c:	db18      	blt.n	1360 <z_arm_fault+0x8c>
	} else if ((SCB->HFSR & SCB_HFSR_FORCED_Msk) != 0) {
    132e:	6adb      	ldr	r3, [r3, #44]	; 0x2c
    1330:	005b      	lsls	r3, r3, #1
    1332:	d515      	bpl.n	1360 <z_arm_fault+0x8c>
	uint16_t fault_insn = *(ret_addr - 1);
    1334:	69ab      	ldr	r3, [r5, #24]
	if (((fault_insn & 0xff00) == _SVC_OPCODE) &&
    1336:	f833 2c02 	ldrh.w	r2, [r3, #-2]
    133a:	f64d 7302 	movw	r3, #57090	; 0xdf02
    133e:	429a      	cmp	r2, r3
    1340:	d00d      	beq.n	135e <z_arm_fault+0x8a>
		} else if (SCB_MMFSR != 0) {
    1342:	f103 4360 	add.w	r3, r3, #3758096384	; 0xe0000000
    1346:	f603 6326 	addw	r3, r3, #3622	; 0xe26
    134a:	781b      	ldrb	r3, [r3, #0]
    134c:	b303      	cbz	r3, 1390 <z_arm_fault+0xbc>
			reason = mem_manage_fault(esf, 1, recoverable);
    134e:	f10d 0207 	add.w	r2, sp, #7
    1352:	2101      	movs	r1, #1
		reason = mem_manage_fault(esf, 0, recoverable);
    1354:	4628      	mov	r0, r5
    1356:	f7ff ff57 	bl	1208 <mem_manage_fault>
    135a:	4604      	mov	r4, r0
		break;
    135c:	e000      	b.n	1360 <z_arm_fault+0x8c>
			reason = esf->basic.r0;
    135e:	682c      	ldr	r4, [r5, #0]
#ifdef CONFIG_DEBUG_COREDUMP
	z_arm_coredump_fault_sp = POINTER_TO_UINT(esf);
#endif

	reason = fault_handle(esf, fault, &recoverable);
	if (recoverable) {
    1360:	f89d 3007 	ldrb.w	r3, [sp, #7]
    1364:	b993      	cbnz	r3, 138c <z_arm_fault+0xb8>
		return;
	}

	/* Copy ESF */
#if !defined(CONFIG_EXTRA_EXCEPTION_INFO)
	memcpy(&esf_copy, esf, sizeof(z_arch_esf_t));
    1366:	2220      	movs	r2, #32
    1368:	4629      	mov	r1, r5
    136a:	a802      	add	r0, sp, #8
    136c:	f003 f80c 	bl	4388 <memcpy>
	/* Overwrite stacked IPSR to mark a nested exception,
	 * or a return to Thread mode. Note that this may be
	 * required, if the retrieved ESF contents are invalid
	 * due to, for instance, a stacking error.
	 */
	if (nested_exc) {
    1370:	9b09      	ldr	r3, [sp, #36]	; 0x24
    1372:	b346      	cbz	r6, 13c6 <z_arm_fault+0xf2>
		if ((esf_copy.basic.xpsr & IPSR_ISR_Msk) == 0) {
    1374:	f3c3 0208 	ubfx	r2, r3, #0, #9
    1378:	b922      	cbnz	r2, 1384 <z_arm_fault+0xb0>
			esf_copy.basic.xpsr |= IPSR_ISR_Msk;
    137a:	ea6f 2353 	mvn.w	r3, r3, lsr #9
    137e:	ea6f 2343 	mvn.w	r3, r3, lsl #9
		}
	} else {
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    1382:	9309      	str	r3, [sp, #36]	; 0x24
	}

	z_arm_fatal_error(reason, &esf_copy);
    1384:	a902      	add	r1, sp, #8
    1386:	4620      	mov	r0, r4
    1388:	f002 ffd3 	bl	4332 <z_arm_fatal_error>
}
    138c:	b00a      	add	sp, #40	; 0x28
    138e:	bd70      	pop	{r4, r5, r6, pc}
		} else if (SCB_BFSR != 0) {
    1390:	4b10      	ldr	r3, [pc, #64]	; (13d4 <z_arm_fault+0x100>)
    1392:	781b      	ldrb	r3, [r3, #0]
    1394:	b12b      	cbz	r3, 13a2 <z_arm_fault+0xce>
			reason = bus_fault(esf, 1, recoverable);
    1396:	f10d 0107 	add.w	r1, sp, #7
    139a:	2001      	movs	r0, #1
		reason = bus_fault(esf, 0, recoverable);
    139c:	f7ff ff6a 	bl	1274 <bus_fault.isra.0>
    13a0:	e7db      	b.n	135a <z_arm_fault+0x86>
		} else if (SCB_UFSR != 0) {
    13a2:	4b0d      	ldr	r3, [pc, #52]	; (13d8 <z_arm_fault+0x104>)
    13a4:	881b      	ldrh	r3, [r3, #0]
    13a6:	b29b      	uxth	r3, r3
    13a8:	2b00      	cmp	r3, #0
    13aa:	d0d9      	beq.n	1360 <z_arm_fault+0x8c>
		reason = usage_fault(esf);
    13ac:	f7ff ff80 	bl	12b0 <usage_fault.isra.0>
    13b0:	e7d3      	b.n	135a <z_arm_fault+0x86>
		reason = mem_manage_fault(esf, 0, recoverable);
    13b2:	f10d 0207 	add.w	r2, sp, #7
    13b6:	2100      	movs	r1, #0
    13b8:	e7cc      	b.n	1354 <z_arm_fault+0x80>
		reason = bus_fault(esf, 0, recoverable);
    13ba:	f10d 0107 	add.w	r1, sp, #7
    13be:	2000      	movs	r0, #0
    13c0:	e7ec      	b.n	139c <z_arm_fault+0xc8>
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    13c2:	2400      	movs	r4, #0
    13c4:	e7cc      	b.n	1360 <z_arm_fault+0x8c>
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    13c6:	f423 73ff 	bic.w	r3, r3, #510	; 0x1fe
    13ca:	f023 0301 	bic.w	r3, r3, #1
    13ce:	e7d8      	b.n	1382 <z_arm_fault+0xae>
    13d0:	e000ed00 	.word	0xe000ed00
    13d4:	e000ed29 	.word	0xe000ed29
    13d8:	e000ed2a 	.word	0xe000ed2a

000013dc <z_arm_fault_init>:
 */
void z_arm_fault_init(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
    13dc:	4a02      	ldr	r2, [pc, #8]	; (13e8 <z_arm_fault_init+0xc>)
    13de:	6953      	ldr	r3, [r2, #20]
    13e0:	f043 0310 	orr.w	r3, r3, #16
    13e4:	6153      	str	r3, [r2, #20]
	 * Stack to attempt to descend into secure region, in which case a
	 * Secure Hard Fault will occur and we can track the fault from there.
	 */
	SCB->CCR |= SCB_CCR_STKOFHFNMIGN_Msk;
#endif /* CONFIG_BUILTIN_STACK_GUARD */
}
    13e6:	4770      	bx	lr
    13e8:	e000ed00 	.word	0xe000ed00

000013ec <z_arm_bus_fault>:
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_exc_spurious)

	mrs r0, MSP
    13ec:	f3ef 8008 	mrs	r0, MSP
	mrs r1, PSP
    13f0:	f3ef 8109 	mrs	r1, PSP
	push {r0, lr}
    13f4:	b501      	push	{r0, lr}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	push {r4-r11}
#endif
	mov  r3, sp /* pointer to _callee_saved_t */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
	mov r2, lr /* EXC_RETURN */
    13f6:	4672      	mov	r2, lr
	bl z_arm_fault
    13f8:	f7ff ff6c 	bl	12d4 <z_arm_fault>
	 * in this routine. Therefore, we can just reset
	 * the MSP to its value prior to entering the function
	 */
	add sp, #40
#endif
	pop {r0, pc}
    13fc:	bd01      	pop	{r0, pc}
    13fe:	bf00      	nop

00001400 <z_arm_interrupt_init>:
    1400:	4804      	ldr	r0, [pc, #16]	; (1414 <z_arm_interrupt_init+0x14>)
 * @return N/A
 */

void z_arm_interrupt_init(void)
{
	int irq = 0;
    1402:	2300      	movs	r3, #0
    1404:	2120      	movs	r1, #32
    1406:	18c2      	adds	r2, r0, r3

	for (; irq < CONFIG_NUM_IRQS; irq++) {
    1408:	3301      	adds	r3, #1
    140a:	2b27      	cmp	r3, #39	; 0x27
    140c:	f882 1300 	strb.w	r1, [r2, #768]	; 0x300
    1410:	d1f9      	bne.n	1406 <z_arm_interrupt_init+0x6>
		NVIC_SetPriority((IRQn_Type)irq, _IRQ_PRIO_OFFSET);
	}
}
    1412:	4770      	bx	lr
    1414:	e000e100 	.word	0xe000e100

00001418 <__start>:
 */
SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
    /* Reset CONTROL register */
    movs.n r0, #0
    1418:	2000      	movs	r0, #0
    msr CONTROL, r0
    141a:	f380 8814 	msr	CONTROL, r0
    isb
    141e:	f3bf 8f6f 	isb	sy
#endif /* CONFIG_CPU_CORTEX_M_HAS_SPLIM */

#endif /* CONFIG_INIT_ARCH_HW_AT_BOOT */

#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
    bl z_arm_platform_init
    1422:	f003 fbd1 	bl	4bc8 <z_arm_platform_init>
#endif

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
#if defined(CONFIG_CPU_HAS_ARM_MPU)
    /* Disable MPU */
    movs.n r0, #0
    1426:	2000      	movs	r0, #0
    ldr r1, =_SCS_MPU_CTRL
    1428:	490d      	ldr	r1, [pc, #52]	; (1460 <__start+0x48>)
    str r0, [r1]
    142a:	6008      	str	r0, [r1, #0]
    dsb
    142c:	f3bf 8f4f 	dsb	sy
#endif /* CONFIG_CPU_HAS_ARM_MPU */
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    1430:	480c      	ldr	r0, [pc, #48]	; (1464 <__start+0x4c>)
    msr msp, r0
    1432:	f380 8808 	msr	MSP, r0

    /* Initialize core architecture registers and system blocks */
    bl z_arm_init_arch_hw_at_boot
    1436:	f000 f829 	bl	148c <z_arm_init_arch_hw_at_boot>

    /* lock interrupts: will get unlocked when switch to main task */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    143a:	2020      	movs	r0, #32
    msr BASEPRI, r0
    143c:	f380 8811 	msr	BASEPRI, r0

    /*
     * Set PSP and use it to boot without using MSP, so that it
     * gets set to z_interrupt_stacks during initialization.
     */
    ldr r0, =z_interrupt_stacks
    1440:	4809      	ldr	r0, [pc, #36]	; (1468 <__start+0x50>)
    ldr r1, =CONFIG_ISR_STACK_SIZE + MPU_GUARD_ALIGN_AND_SIZE
    1442:	f44f 6102 	mov.w	r1, #2080	; 0x820
    adds r0, r0, r1
    1446:	1840      	adds	r0, r0, r1
    msr PSP, r0
    1448:	f380 8809 	msr	PSP, r0
    mrs r0, CONTROL
    144c:	f3ef 8014 	mrs	r0, CONTROL
    movs r1, #2
    1450:	2102      	movs	r1, #2
    orrs r0, r1 /* CONTROL_SPSEL_Msk */
    1452:	4308      	orrs	r0, r1
    msr CONTROL, r0
    1454:	f380 8814 	msr	CONTROL, r0
    /*
     * When changing the stack pointer, software must use an ISB instruction
     * immediately after the MSR instruction. This ensures that instructions
     * after the ISB instruction execute using the new stack pointer.
     */
    isb
    1458:	f3bf 8f6f 	isb	sy
    /*
     * 'bl' jumps the furthest of the branch instructions that are
     * supported on all platforms. So it is used when jumping to z_arm_prep_c
     * (even though we do not intend to return).
     */
    bl z_arm_prep_c
    145c:	f7ff fdea 	bl	1034 <z_arm_prep_c>
    ldr r1, =_SCS_MPU_CTRL
    1460:	e000ed94 	.word	0xe000ed94
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    1464:	20000b80 	.word	0x20000b80
    ldr r0, =z_interrupt_stacks
    1468:	20000d00 	.word	0x20000d00

0000146c <z_arm_clear_arm_mpu_config>:
void z_arm_clear_arm_mpu_config(void)
{
	int i;

	int num_regions =
		((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos);
    146c:	4a06      	ldr	r2, [pc, #24]	; (1488 <z_arm_clear_arm_mpu_config+0x1c>)
    146e:	6811      	ldr	r1, [r2, #0]

	for (i = 0; i < num_regions; i++) {
    1470:	2300      	movs	r3, #0
	int num_regions =
    1472:	f3c1 2107 	ubfx	r1, r1, #8, #8
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
  MPU->RNR = rnr;
  MPU->RASR = 0U;
    1476:	4618      	mov	r0, r3
	for (i = 0; i < num_regions; i++) {
    1478:	428b      	cmp	r3, r1
    147a:	d100      	bne.n	147e <z_arm_clear_arm_mpu_config+0x12>
		ARM_MPU_ClrRegion(i);
	}
}
    147c:	4770      	bx	lr
  MPU->RNR = rnr;
    147e:	6093      	str	r3, [r2, #8]
  MPU->RASR = 0U;
    1480:	6110      	str	r0, [r2, #16]
	for (i = 0; i < num_regions; i++) {
    1482:	3301      	adds	r3, #1
    1484:	e7f8      	b.n	1478 <z_arm_clear_arm_mpu_config+0xc>
    1486:	bf00      	nop
    1488:	e000ed90 	.word	0xe000ed90

0000148c <z_arm_init_arch_hw_at_boot>:
 * components and core registers.
 *
 * @return N/A
 */
void z_arm_init_arch_hw_at_boot(void)
{
    148c:	b508      	push	{r3, lr}
  __ASM volatile ("cpsid i" : : : "memory");
    148e:	b672      	cpsid	i
  \details Assigns the given value to the Fault Mask register.
  \param [in]    faultMask  Fault Mask value to set
 */
__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
{
  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
    1490:	2300      	movs	r3, #0
    1492:	f383 8813 	msr	FAULTMASK, r3

	/* Initialize System Control Block components */

#if defined(CONFIG_CPU_HAS_ARM_MPU) || defined(CONFIG_CPU_HAS_NXP_MPU)
	/* Clear MPU region configuration */
	z_arm_clear_arm_mpu_config();
    1496:	f7ff ffe9 	bl	146c <z_arm_clear_arm_mpu_config>
#endif /* CONFIG_CPU_HAS_ARM_MPU */

	/* Disable NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
		NVIC->ICER[i] = 0xFFFFFFFF;
    149a:	4b14      	ldr	r3, [pc, #80]	; (14ec <z_arm_init_arch_hw_at_boot+0x60>)
    149c:	f04f 32ff 	mov.w	r2, #4294967295
    14a0:	f8c3 2080 	str.w	r2, [r3, #128]	; 0x80
    14a4:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
    14a8:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
    14ac:	f8c3 208c 	str.w	r2, [r3, #140]	; 0x8c
    14b0:	f8c3 2090 	str.w	r2, [r3, #144]	; 0x90
    14b4:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
    14b8:	f8c3 2098 	str.w	r2, [r3, #152]	; 0x98
    14bc:	f8c3 209c 	str.w	r2, [r3, #156]	; 0x9c
	}
	/* Clear pending NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) {
		NVIC->ICPR[i] = 0xFFFFFFFF;
    14c0:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
    14c4:	f8c3 2184 	str.w	r2, [r3, #388]	; 0x184
    14c8:	f8c3 2188 	str.w	r2, [r3, #392]	; 0x188
    14cc:	f8c3 218c 	str.w	r2, [r3, #396]	; 0x18c
    14d0:	f8c3 2190 	str.w	r2, [r3, #400]	; 0x190
    14d4:	f8c3 2194 	str.w	r2, [r3, #404]	; 0x194
    14d8:	f8c3 2198 	str.w	r2, [r3, #408]	; 0x198
    14dc:	f8c3 219c 	str.w	r2, [r3, #412]	; 0x19c
  __ASM volatile ("cpsie i" : : : "memory");
    14e0:	b662      	cpsie	i
  __ASM volatile ("dsb 0xF":::"memory");
    14e2:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    14e6:	f3bf 8f6f 	isb	sy
	/* Restore Interrupts */
	__enable_irq();

	__DSB();
	__ISB();
}
    14ea:	bd08      	pop	{r3, pc}
    14ec:	e000e100 	.word	0xe000e100

000014f0 <z_impl_k_thread_abort>:
#include <wait_q.h>
#include <sys/__assert.h>

void z_impl_k_thread_abort(k_tid_t thread)
{
	if (_current == thread) {
    14f0:	4b06      	ldr	r3, [pc, #24]	; (150c <z_impl_k_thread_abort+0x1c>)
    14f2:	689b      	ldr	r3, [r3, #8]
    14f4:	4283      	cmp	r3, r0
    14f6:	d107      	bne.n	1508 <z_impl_k_thread_abort+0x18>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    14f8:	f3ef 8305 	mrs	r3, IPSR
		if (arch_is_in_isr()) {
    14fc:	b123      	cbz	r3, 1508 <z_impl_k_thread_abort+0x18>
			 * should no longer run after we return, so
			 * Trigger PendSV, in case we are in one of the
			 * situations where the isr check is true but there
			 * is not an implicit scheduler invocation.
			 */
			SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    14fe:	4a04      	ldr	r2, [pc, #16]	; (1510 <z_impl_k_thread_abort+0x20>)
    1500:	6853      	ldr	r3, [r2, #4]
    1502:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
    1506:	6053      	str	r3, [r2, #4]
		}
	}

	z_thread_abort(thread);
    1508:	f002 bbd4 	b.w	3cb4 <z_thread_abort>
    150c:	20000334 	.word	0x20000334
    1510:	e000ed00 	.word	0xe000ed00

00001514 <z_arm_configure_static_mpu_regions>:
	/* Configure the static MPU regions within firmware SRAM boundaries.
	 * Start address of the image is given by _image_ram_start. The end
	 * of the firmware SRAM area is marked by __kernel_ram_end, taking
	 * into account the unused SRAM area, as well.
	 */
	arm_core_mpu_configure_static_mpu_regions(static_regions,
    1514:	4b02      	ldr	r3, [pc, #8]	; (1520 <z_arm_configure_static_mpu_regions+0xc>)
    1516:	4a03      	ldr	r2, [pc, #12]	; (1524 <z_arm_configure_static_mpu_regions+0x10>)
    1518:	4803      	ldr	r0, [pc, #12]	; (1528 <z_arm_configure_static_mpu_regions+0x14>)
    151a:	2101      	movs	r1, #1
    151c:	f000 b868 	b.w	15f0 <arm_core_mpu_configure_static_mpu_regions>
    1520:	20010000 	.word	0x20010000
    1524:	20000000 	.word	0x20000000
    1528:	00004dd8 	.word	0x00004dd8

0000152c <z_arm_configure_dynamic_mpu_regions>:
#endif /* CONFIG_USERSPACE */
	{
		/* A supervisor thread only has the normal thread stack to
		 * protect with a stack guard.
		 */
		guard_start = thread->stack_info.start - guard_size;
    152c:	6e42      	ldr	r2, [r0, #100]	; 0x64
	}

	__ASSERT(region_num < _MAX_DYNAMIC_MPU_REGIONS_NUM,
		"Out-of-bounds error for dynamic region map.");

	dynamic_regions[region_num].start = guard_start;
    152e:	4b05      	ldr	r3, [pc, #20]	; (1544 <z_arm_configure_dynamic_mpu_regions+0x18>)
		guard_start = thread->stack_info.start - guard_size;
    1530:	3a20      	subs	r2, #32
	dynamic_regions[region_num].start = guard_start;
    1532:	601a      	str	r2, [r3, #0]
	dynamic_regions[region_num].size = guard_size;
	dynamic_regions[region_num].attr = K_MEM_PARTITION_P_RO_U_NA;
    1534:	4a04      	ldr	r2, [pc, #16]	; (1548 <z_arm_configure_dynamic_mpu_regions+0x1c>)
    1536:	2120      	movs	r1, #32
    1538:	e9c3 1201 	strd	r1, r2, [r3, #4]

	region_num++;
#endif /* CONFIG_MPU_STACK_GUARD */

	/* Configure the dynamic MPU regions */
	arm_core_mpu_configure_dynamic_mpu_regions(dynamic_regions,
    153c:	4618      	mov	r0, r3
    153e:	2101      	movs	r1, #1
    1540:	f000 b860 	b.w	1604 <arm_core_mpu_configure_dynamic_mpu_regions>
    1544:	200001dc 	.word	0x200001dc
    1548:	150b0000 	.word	0x150b0000

0000154c <mpu_configure_regions>:
 * sanity check of the memory regions to be programmed.
 */
static int mpu_configure_regions(const struct z_arm_mpu_partition
	regions[], uint8_t regions_num, uint8_t start_reg_index,
	bool do_sanity_check)
{
    154c:	b5f0      	push	{r4, r5, r6, r7, lr}
#endif /* CPU_CORTEX_M0PLUS | CPU_CORTEX_M3 | CPU_CORTEX_M4 */
}

static inline void set_region_number(uint32_t index)
{
	MPU->RNR = index;
    154e:	4f1e      	ldr	r7, [pc, #120]	; (15c8 <mpu_configure_regions+0x7c>)
	int i;
	int reg_index = start_reg_index;

	for (i = 0; i < regions_num; i++) {
    1550:	2600      	movs	r6, #0
    1552:	428e      	cmp	r6, r1
    1554:	db01      	blt.n	155a <mpu_configure_regions+0xe>
		/* Increment number of programmed MPU indices. */
		reg_index++;
	}

	return reg_index;
}
    1556:	4610      	mov	r0, r2
    1558:	bdf0      	pop	{r4, r5, r6, r7, pc}
		if (regions[i].size == 0U) {
    155a:	6844      	ldr	r4, [r0, #4]
    155c:	b384      	cbz	r4, 15c0 <mpu_configure_regions+0x74>
		if (do_sanity_check &&
    155e:	b153      	cbz	r3, 1576 <mpu_configure_regions+0x2a>
	 * and greater or equal to the minimum
	 * MPU region size. Start address of the
	 * partition must align with size.
	 */
	int partition_is_valid =
		((part->size & (part->size - 1U)) == 0U)
    1560:	f104 3cff 	add.w	ip, r4, #4294967295
		&&
		(part->size >= CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)
		&&
    1564:	ea14 0f0c 	tst.w	r4, ip
    1568:	d118      	bne.n	159c <mpu_configure_regions+0x50>
		&&
    156a:	2c1f      	cmp	r4, #31
    156c:	d916      	bls.n	159c <mpu_configure_regions+0x50>
		((part->start & (part->size - 1U)) == 0U);
    156e:	6805      	ldr	r5, [r0, #0]
		&&
    1570:	ea1c 0f05 	tst.w	ip, r5
    1574:	d112      	bne.n	159c <mpu_configure_regions+0x50>
 * to that power-of-two value.
 */
static inline uint32_t size_to_mpu_rasr_size(uint32_t size)
{
	/* The minimal supported region size is 32 bytes */
	if (size <= 32U) {
    1576:	2c20      	cmp	r4, #32
	region_conf.base = new_region->start;
    1578:	6805      	ldr	r5, [r0, #0]
	get_region_attr_from_mpu_partition_info(&region_conf.attr,
    157a:	f8d0 c008 	ldr.w	ip, [r0, #8]
		reg_index = mpu_configure_region(reg_index, &regions[i]);
    157e:	b2d2      	uxtb	r2, r2
    1580:	d90f      	bls.n	15a2 <mpu_configure_regions+0x56>
	/*
	 * A size value greater than 2^31 could not be handled by
	 * round_up_to_next_power_of_two() properly. We handle
	 * it separately here.
	 */
	if (size > (1UL << 31)) {
    1582:	f1b4 4f00 	cmp.w	r4, #2147483648	; 0x80000000
    1586:	d80e      	bhi.n	15a6 <mpu_configure_regions+0x5a>
		return REGION_4G;
	}

	return ((32 - __builtin_clz(size - 1U) - 2 + 1) << MPU_RASR_SIZE_Pos) &
    1588:	3c01      	subs	r4, #1
    158a:	fab4 f484 	clz	r4, r4
    158e:	f1c4 041f 	rsb	r4, r4, #31
    1592:	0064      	lsls	r4, r4, #1
	if (index > (get_num_regions() - 1U)) {
    1594:	2a07      	cmp	r2, #7
#if defined(CONFIG_CPU_CORTEX_R)
	(void) size;

	p_attr->rasr = attr->rasr_attr;
#else
	p_attr->rasr = attr->rasr_attr | size_to_mpu_rasr_size(size);
    1596:	ea4c 0404 	orr.w	r4, ip, r4
    159a:	d906      	bls.n	15aa <mpu_configure_regions+0x5e>
			return -EINVAL;
    159c:	f06f 0215 	mvn.w	r2, #21
    15a0:	e7d9      	b.n	1556 <mpu_configure_regions+0xa>
		return REGION_32B;
    15a2:	2408      	movs	r4, #8
    15a4:	e7f6      	b.n	1594 <mpu_configure_regions+0x48>
		return REGION_4G;
    15a6:	243e      	movs	r4, #62	; 0x3e
    15a8:	e7f4      	b.n	1594 <mpu_configure_regions+0x48>
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    15aa:	f025 051f 	bic.w	r5, r5, #31
				| MPU_RBAR_VALID_Msk | index;
    15ae:	4315      	orrs	r5, r2
    15b0:	f045 0510 	orr.w	r5, r5, #16
	MPU->RASR = region_conf->attr.rasr | MPU_RASR_ENABLE_Msk;
    15b4:	f044 0401 	orr.w	r4, r4, #1
    15b8:	60ba      	str	r2, [r7, #8]
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    15ba:	60fd      	str	r5, [r7, #12]
		reg_index++;
    15bc:	3201      	adds	r2, #1
	MPU->RASR = region_conf->attr.rasr | MPU_RASR_ENABLE_Msk;
    15be:	613c      	str	r4, [r7, #16]
	for (i = 0; i < regions_num; i++) {
    15c0:	3601      	adds	r6, #1
    15c2:	300c      	adds	r0, #12
    15c4:	e7c5      	b.n	1552 <mpu_configure_regions+0x6>
    15c6:	bf00      	nop
    15c8:	e000ed90 	.word	0xe000ed90

000015cc <arm_core_mpu_enable>:
void arm_core_mpu_enable(void)
{
	/* Enable MPU and use the default memory map as a
	 * background region for privileged software access.
	 */
	MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
    15cc:	4b03      	ldr	r3, [pc, #12]	; (15dc <arm_core_mpu_enable+0x10>)
    15ce:	2205      	movs	r2, #5
    15d0:	605a      	str	r2, [r3, #4]
  __ASM volatile ("dsb 0xF":::"memory");
    15d2:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    15d6:	f3bf 8f6f 	isb	sy

	/* Make sure that all the registers are set before proceeding */
	__DSB();
	__ISB();
}
    15da:	4770      	bx	lr
    15dc:	e000ed90 	.word	0xe000ed90

000015e0 <arm_core_mpu_disable>:
  __ASM volatile ("dmb 0xF":::"memory");
    15e0:	f3bf 8f5f 	dmb	sy
{
	/* Force any outstanding transfers to complete before disabling MPU */
	__DMB();

	/* Disable MPU */
	MPU->CTRL = 0;
    15e4:	4b01      	ldr	r3, [pc, #4]	; (15ec <arm_core_mpu_disable+0xc>)
    15e6:	2200      	movs	r2, #0
    15e8:	605a      	str	r2, [r3, #4]
}
    15ea:	4770      	bx	lr
    15ec:	e000ed90 	.word	0xe000ed90

000015f0 <arm_core_mpu_configure_static_mpu_regions>:
 * @brief configure fixed (static) MPU regions.
 */
void arm_core_mpu_configure_static_mpu_regions(const struct z_arm_mpu_partition
	static_regions[], const uint8_t regions_num,
	const uint32_t background_area_start, const uint32_t background_area_end)
{
    15f0:	b510      	push	{r4, lr}
static int mpu_configure_static_mpu_regions(const struct z_arm_mpu_partition
	static_regions[], const uint8_t regions_num,
	const uint32_t background_area_base,
	const uint32_t background_area_end)
{
	int mpu_reg_index = static_regions_num;
    15f2:	4c03      	ldr	r4, [pc, #12]	; (1600 <arm_core_mpu_configure_static_mpu_regions+0x10>)
	 * programmed on top of SRAM region configuration.
	 */
	ARG_UNUSED(background_area_base);
	ARG_UNUSED(background_area_end);

	mpu_reg_index = mpu_configure_regions(static_regions,
    15f4:	2301      	movs	r3, #1
    15f6:	7822      	ldrb	r2, [r4, #0]
    15f8:	f7ff ffa8 	bl	154c <mpu_configure_regions>
		regions_num, mpu_reg_index, true);

	static_regions_num = mpu_reg_index;
    15fc:	7020      	strb	r0, [r4, #0]
					       background_area_start, background_area_end) == -EINVAL) {

		__ASSERT(0, "Configuring %u static MPU regions failed\n",
			regions_num);
	}
}
    15fe:	bd10      	pop	{r4, pc}
    1600:	2000036c 	.word	0x2000036c

00001604 <arm_core_mpu_configure_dynamic_mpu_regions>:
/**
 * @brief configure dynamic MPU regions.
 */
void arm_core_mpu_configure_dynamic_mpu_regions(const struct z_arm_mpu_partition
	dynamic_regions[], uint8_t regions_num)
{
    1604:	b508      	push	{r3, lr}

	/* In ARMv7-M architecture the dynamic regions are
	 * programmed on top of existing SRAM region configuration.
	 */

	mpu_reg_index = mpu_configure_regions(dynamic_regions,
    1606:	4a08      	ldr	r2, [pc, #32]	; (1628 <arm_core_mpu_configure_dynamic_mpu_regions+0x24>)
    1608:	2300      	movs	r3, #0
    160a:	7812      	ldrb	r2, [r2, #0]
    160c:	f7ff ff9e 	bl	154c <mpu_configure_regions>
		regions_num, mpu_reg_index, false);

	if (mpu_reg_index != -EINVAL) {
    1610:	f110 0f16 	cmn.w	r0, #22
    1614:	d003      	beq.n	161e <arm_core_mpu_configure_dynamic_mpu_regions+0x1a>
  MPU->RNR = rnr;
    1616:	4b05      	ldr	r3, [pc, #20]	; (162c <arm_core_mpu_configure_dynamic_mpu_regions+0x28>)
  MPU->RASR = 0U;
    1618:	2200      	movs	r2, #0

		/* Disable the non-programmed MPU regions. */
		for (int i = mpu_reg_index; i < get_num_regions(); i++) {
    161a:	2807      	cmp	r0, #7
    161c:	dd00      	ble.n	1620 <arm_core_mpu_configure_dynamic_mpu_regions+0x1c>
		== -EINVAL) {

		__ASSERT(0, "Configuring %u dynamic MPU regions failed\n",
			regions_num);
	}
}
    161e:	bd08      	pop	{r3, pc}
  MPU->RNR = rnr;
    1620:	6098      	str	r0, [r3, #8]
  MPU->RASR = 0U;
    1622:	611a      	str	r2, [r3, #16]
    1624:	3001      	adds	r0, #1
    1626:	e7f8      	b.n	161a <arm_core_mpu_configure_dynamic_mpu_regions+0x16>
    1628:	2000036c 	.word	0x2000036c
    162c:	e000ed90 	.word	0xe000ed90

00001630 <z_arm_mpu_init>:
 */
int z_arm_mpu_init(void)
{
	uint32_t r_index;

	if (mpu_config.num_regions > get_num_regions()) {
    1630:	4913      	ldr	r1, [pc, #76]	; (1680 <z_arm_mpu_init+0x50>)
    1632:	6808      	ldr	r0, [r1, #0]
    1634:	2808      	cmp	r0, #8
{
    1636:	b510      	push	{r4, lr}
	if (mpu_config.num_regions > get_num_regions()) {
    1638:	d81e      	bhi.n	1678 <z_arm_mpu_init+0x48>
		return -1;
	}

	LOG_DBG("total region count: %d", get_num_regions());

	arm_core_mpu_disable();
    163a:	f7ff ffd1 	bl	15e0 <arm_core_mpu_disable>
    163e:	4c11      	ldr	r4, [pc, #68]	; (1684 <z_arm_mpu_init+0x54>)
    1640:	6849      	ldr	r1, [r1, #4]

	/* Architecture-specific configuration */
	mpu_init();

	/* Program fixed regions configured at SOC definition. */
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    1642:	2200      	movs	r2, #0
    1644:	4290      	cmp	r0, r2
    1646:	f101 010c 	add.w	r1, r1, #12
    164a:	d105      	bne.n	1658 <z_arm_mpu_init+0x28>
		region_init(r_index, &mpu_config.mpu_regions[r_index]);
	}

	/* Update the number of programmed MPU regions. */
	static_regions_num = mpu_config.num_regions;
    164c:	4b0e      	ldr	r3, [pc, #56]	; (1688 <z_arm_mpu_init+0x58>)
    164e:	7018      	strb	r0, [r3, #0]


	arm_core_mpu_enable();
    1650:	f7ff ffbc 	bl	15cc <arm_core_mpu_enable>
		(MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos ==
		NUM_MPU_REGIONS,
		"Invalid number of MPU regions\n");
#endif /* CORTEX_M0PLUS || CPU_CORTEX_M3 || CPU_CORTEX_M4 */

	return 0;
    1654:	2000      	movs	r0, #0
}
    1656:	bd10      	pop	{r4, pc}
    1658:	60a2      	str	r2, [r4, #8]
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    165a:	f851 3c0c 	ldr.w	r3, [r1, #-12]
    165e:	f023 031f 	bic.w	r3, r3, #31
				| MPU_RBAR_VALID_Msk | index;
    1662:	4313      	orrs	r3, r2
    1664:	f043 0310 	orr.w	r3, r3, #16
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    1668:	60e3      	str	r3, [r4, #12]
	MPU->RASR = region_conf->attr.rasr | MPU_RASR_ENABLE_Msk;
    166a:	f851 3c04 	ldr.w	r3, [r1, #-4]
    166e:	f043 0301 	orr.w	r3, r3, #1
    1672:	6123      	str	r3, [r4, #16]
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    1674:	3201      	adds	r2, #1
    1676:	e7e5      	b.n	1644 <z_arm_mpu_init+0x14>
		return -1;
    1678:	f04f 30ff 	mov.w	r0, #4294967295
    167c:	e7eb      	b.n	1656 <z_arm_mpu_init+0x26>
    167e:	bf00      	nop
    1680:	00004de4 	.word	0x00004de4
    1684:	e000ed90 	.word	0xe000ed90
    1688:	2000036c 	.word	0x2000036c

0000168c <__stdout_hook_install>:

static int (*_stdout_hook)(int) = _stdout_hook_default;

void __stdout_hook_install(int (*hook)(int))
{
	_stdout_hook = hook;
    168c:	4b01      	ldr	r3, [pc, #4]	; (1694 <__stdout_hook_install+0x8>)
    168e:	6018      	str	r0, [r3, #0]
}
    1690:	4770      	bx	lr
    1692:	bf00      	nop
    1694:	20000004 	.word	0x20000004

00001698 <nordicsemi_nrf52_init>:
	__asm__ volatile(
    1698:	f04f 0320 	mov.w	r3, #32
    169c:	f3ef 8211 	mrs	r2, BASEPRI
    16a0:	f383 8812 	msr	BASEPRI_MAX, r3
    16a4:	f3bf 8f6f 	isb	sy

	key = irq_lock();

#ifdef CONFIG_NRF_ENABLE_ICACHE
	/* Enable the instruction cache */
	NRF_NVMC->ICACHECNF = NVMC_ICACHECNF_CACHEEN_Msk;
    16a8:	4906      	ldr	r1, [pc, #24]	; (16c4 <nordicsemi_nrf52_init+0x2c>)
    16aa:	2301      	movs	r3, #1
    16ac:	f8c1 3540 	str.w	r3, [r1, #1344]	; 0x540
#endif

#if NRF_POWER_HAS_DCDCEN
NRF_STATIC_INLINE void nrf_power_dcdcen_set(NRF_POWER_Type * p_reg, bool enable)
{
    p_reg->DCDCEN = (enable ? POWER_DCDCEN_DCDCEN_Enabled : POWER_DCDCEN_DCDCEN_Disabled) <<
    16b0:	f04f 4180 	mov.w	r1, #1073741824	; 0x40000000
    16b4:	f8c1 3578 	str.w	r3, [r1, #1400]	; 0x578
	__asm__ volatile(
    16b8:	f382 8811 	msr	BASEPRI, r2
    16bc:	f3bf 8f6f 	isb	sy
	NMI_INIT();

	irq_unlock(key);

	return 0;
}
    16c0:	2000      	movs	r0, #0
    16c2:	4770      	bx	lr
    16c4:	4001e000 	.word	0x4001e000

000016c8 <sys_arch_reboot>:
    *p_gpregret = val;
    16c8:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    16cc:	b2c0      	uxtb	r0, r0
    16ce:	f8c3 051c 	str.w	r0, [r3, #1308]	; 0x51c
  __ASM volatile ("dsb 0xF":::"memory");
    16d2:	f3bf 8f4f 	dsb	sy
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
  __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                       buffered write are completed before reset */
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    16d6:	4905      	ldr	r1, [pc, #20]	; (16ec <sys_arch_reboot+0x24>)
    16d8:	4b05      	ldr	r3, [pc, #20]	; (16f0 <sys_arch_reboot+0x28>)
    16da:	68ca      	ldr	r2, [r1, #12]
    16dc:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    16e0:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    16e2:	60cb      	str	r3, [r1, #12]
    16e4:	f3bf 8f4f 	dsb	sy
                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
  __DSB();                                                          /* Ensure completion of memory access */

  for(;;)                                                           /* wait until reset */
  {
    __NOP();
    16e8:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    16ea:	e7fd      	b.n	16e8 <sys_arch_reboot+0x20>
    16ec:	e000ed00 	.word	0xe000ed00
    16f0:	05fa0004 	.word	0x05fa0004

000016f4 <arch_busy_wait>:

#else // NRFX_CHECK(NRFX_DELAY_DWT_BASED)

NRF_STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us)
{
    if (time_us == 0)
    16f4:	b120      	cbz	r0, 1700 <arch_busy_wait+0xc>
    };

    typedef void (* delay_func_t)(uint32_t);
    const delay_func_t delay_cycles =
        // Set LSB to 1 to execute the code in the Thumb mode.
        (delay_func_t)((((uint32_t)delay_machine_code) | 1));
    16f6:	4b03      	ldr	r3, [pc, #12]	; (1704 <arch_busy_wait+0x10>)
    uint32_t cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ;
    delay_cycles(cycles);
    16f8:	0180      	lsls	r0, r0, #6
    16fa:	f043 0301 	orr.w	r3, r3, #1
    16fe:	4718      	bx	r3

void arch_busy_wait(uint32_t time_us)
{
	nrfx_coredep_delay_us(time_us);
}
    1700:	4770      	bx	lr
    1702:	bf00      	nop
    1704:	00004dd0 	.word	0x00004dd0

00001708 <onoff_stop>:
}

static clock_control_subsys_t get_subsys(struct onoff_manager *mgr)
{
	struct nrf_clock_control_data *data = CLOCK_DEVICE->data;
	size_t offset = (size_t)(mgr - data->mgr);
    1708:	4a0e      	ldr	r2, [pc, #56]	; (1744 <onoff_stop+0x3c>)
	return (clock_control_subsys_t)offset;
}

static void onoff_stop(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    170a:	b570      	push	{r4, r5, r6, lr}
	size_t offset = (size_t)(mgr - data->mgr);
    170c:	1a84      	subs	r4, r0, r2
    170e:	10a3      	asrs	r3, r4, #2
    1710:	4c0d      	ldr	r4, [pc, #52]	; (1748 <onoff_stop+0x40>)
    1712:	435c      	muls	r4, r3
{
    1714:	4605      	mov	r5, r0
    1716:	b2e4      	uxtb	r4, r4
	err = set_off_state(&subdata->flags, ctx);
    1718:	200c      	movs	r0, #12
    171a:	fb00 2004 	mla	r0, r0, r4, r2
{
    171e:	460e      	mov	r6, r1
	err = set_off_state(&subdata->flags, ctx);
    1720:	2140      	movs	r1, #64	; 0x40
    1722:	4408      	add	r0, r1
    1724:	f002 fe6e 	bl	4404 <set_off_state>
	if (err < 0) {
    1728:	1e01      	subs	r1, r0, #0
    172a:	db05      	blt.n	1738 <onoff_stop+0x30>
	get_sub_config(dev, type)->stop();
    172c:	4b07      	ldr	r3, [pc, #28]	; (174c <onoff_stop+0x44>)
    172e:	eb03 04c4 	add.w	r4, r3, r4, lsl #3
    1732:	6863      	ldr	r3, [r4, #4]
    1734:	4798      	blx	r3
	return 0;
    1736:	2100      	movs	r1, #0
	int res;

	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
	notify(mgr, res);
    1738:	4628      	mov	r0, r5
    173a:	4633      	mov	r3, r6
}
    173c:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	notify(mgr, res);
    1740:	4718      	bx	r3
    1742:	bf00      	nop
    1744:	200001f8 	.word	0x200001f8
    1748:	b6db6db7 	.word	0xb6db6db7
    174c:	00004e1c 	.word	0x00004e1c

00001750 <onoff_start>:
	notify(mgr, 0);
}

static void onoff_start(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    1750:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	size_t offset = (size_t)(mgr - data->mgr);
    1754:	4e10      	ldr	r6, [pc, #64]	; (1798 <onoff_start+0x48>)
    1756:	1b84      	subs	r4, r0, r6
    1758:	10a3      	asrs	r3, r4, #2
    175a:	4c10      	ldr	r4, [pc, #64]	; (179c <onoff_start+0x4c>)
    175c:	435c      	muls	r4, r3
    175e:	b2e4      	uxtb	r4, r4
	err = set_starting_state(&subdata->flags, ctx);
    1760:	250c      	movs	r5, #12
    1762:	4365      	muls	r5, r4
{
    1764:	4680      	mov	r8, r0
	err = set_starting_state(&subdata->flags, ctx);
    1766:	f105 0040 	add.w	r0, r5, #64	; 0x40
{
    176a:	460f      	mov	r7, r1
	err = set_starting_state(&subdata->flags, ctx);
    176c:	4430      	add	r0, r6
    176e:	2140      	movs	r1, #64	; 0x40
    1770:	f002 fe61 	bl	4436 <set_starting_state>
	if (err < 0) {
    1774:	1e01      	subs	r1, r0, #0
    1776:	db09      	blt.n	178c <onoff_start+0x3c>
	subdata->cb = cb;
    1778:	4a09      	ldr	r2, [pc, #36]	; (17a0 <onoff_start+0x50>)
    177a:	1973      	adds	r3, r6, r5
	subdata->user_data = user_data;
    177c:	e9c3 270e 	strd	r2, r7, [r3, #56]	; 0x38
	 get_sub_config(dev, type)->start();
    1780:	4b08      	ldr	r3, [pc, #32]	; (17a4 <onoff_start+0x54>)
    1782:	f853 3034 	ldr.w	r3, [r3, r4, lsl #3]
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
			  onoff_started_callback, notify, CTX_ONOFF);
	if (err < 0) {
		notify(mgr, err);
	}
}
    1786:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
	 get_sub_config(dev, type)->start();
    178a:	4718      	bx	r3
		notify(mgr, err);
    178c:	4640      	mov	r0, r8
    178e:	463b      	mov	r3, r7
}
    1790:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
		notify(mgr, err);
    1794:	4718      	bx	r3
    1796:	bf00      	nop
    1798:	200001f8 	.word	0x200001f8
    179c:	b6db6db7 	.word	0xb6db6db7
    17a0:	00004499 	.word	0x00004499
    17a4:	00004e1c 	.word	0x00004e1c

000017a8 <clk_init>:
	static const struct onoff_transitions transitions = {
		.start = onoff_start,
		.stop = onoff_stop
	};

	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    17a8:	2200      	movs	r2, #0
{
    17aa:	b570      	push	{r4, r5, r6, lr}
	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    17ac:	2101      	movs	r1, #1
{
    17ae:	4604      	mov	r4, r0
	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    17b0:	4610      	mov	r0, r2
    17b2:	f7ff fc23 	bl	ffc <z_arm_irq_priority_set>
		    nrfx_isr, nrfx_power_clock_irq_handler, 0);
	irq_enable(DT_INST_IRQN(0));
    17b6:	2000      	movs	r0, #0
    17b8:	f7ff fc02 	bl	fc0 <arch_irq_enable>

	nrfx_err = nrfx_clock_init(clock_event_handler);
    17bc:	480f      	ldr	r0, [pc, #60]	; (17fc <clk_init+0x54>)
    17be:	f001 f8bf 	bl	2940 <nrfx_clock_init>
	if (nrfx_err != NRFX_SUCCESS) {
    17c2:	4b0f      	ldr	r3, [pc, #60]	; (1800 <clk_init+0x58>)
    17c4:	4298      	cmp	r0, r3
    17c6:	d115      	bne.n	17f4 <clk_init+0x4c>
		struct nrf_clock_control_data *data = dev->data;

		z_nrf_clock_calibration_init(data->mgr);
	}

	nrfx_clock_enable();
    17c8:	f003 f833 	bl	4832 <nrfx_clock_enable>

	for (enum clock_control_nrf_type i = 0;
		i < CLOCK_CONTROL_NRF_TYPE_COUNT; i++) {
		struct nrf_clock_control_sub_data *subdata =
						get_sub_data(dev, i);
    17cc:	6926      	ldr	r6, [r4, #16]

		err = onoff_manager_init(get_onoff_manager(dev, i),
    17ce:	490d      	ldr	r1, [pc, #52]	; (1804 <clk_init+0x5c>)
    17d0:	4630      	mov	r0, r6
    17d2:	f002 fce1 	bl	4198 <onoff_manager_init>
					 &transitions);
		if (err < 0) {
    17d6:	2800      	cmp	r0, #0
    17d8:	db0b      	blt.n	17f2 <clk_init+0x4a>
			return err;
		}

		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    17da:	2501      	movs	r5, #1
    17dc:	6435      	str	r5, [r6, #64]	; 0x40
						get_sub_data(dev, i);
    17de:	6924      	ldr	r4, [r4, #16]
		err = onoff_manager_init(get_onoff_manager(dev, i),
    17e0:	4908      	ldr	r1, [pc, #32]	; (1804 <clk_init+0x5c>)
    17e2:	f104 001c 	add.w	r0, r4, #28
    17e6:	f002 fcd7 	bl	4198 <onoff_manager_init>
		if (err < 0) {
    17ea:	2800      	cmp	r0, #0
    17ec:	db01      	blt.n	17f2 <clk_init+0x4a>
		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    17ee:	64e5      	str	r5, [r4, #76]	; 0x4c
	}

	return 0;
    17f0:	2000      	movs	r0, #0
}
    17f2:	bd70      	pop	{r4, r5, r6, pc}
		return -EIO;
    17f4:	f06f 0004 	mvn.w	r0, #4
    17f8:	e7fb      	b.n	17f2 <clk_init+0x4a>
    17fa:	bf00      	nop
    17fc:	0000183d 	.word	0x0000183d
    1800:	0bad0000 	.word	0x0bad0000
    1804:	00004e2c 	.word	0x00004e2c

00001808 <clkstarted_handle.constprop.0>:
static void clkstarted_handle(const struct device *dev,
    1808:	4601      	mov	r1, r0
	clock_control_cb_t callback = sub_data->cb;
    180a:	230c      	movs	r3, #12
    180c:	4809      	ldr	r0, [pc, #36]	; (1834 <clkstarted_handle.constprop.0+0x2c>)
    180e:	434b      	muls	r3, r1
static void clkstarted_handle(const struct device *dev,
    1810:	b570      	push	{r4, r5, r6, lr}
	clock_control_cb_t callback = sub_data->cb;
    1812:	18c4      	adds	r4, r0, r3
	void *user_data = sub_data->user_data;
    1814:	e9d4 560e 	ldrd	r5, r6, [r4, #56]	; 0x38
	sub_data->cb = NULL;
    1818:	2200      	movs	r2, #0
	set_on_state(&sub_data->flags);
    181a:	3340      	adds	r3, #64	; 0x40
	sub_data->cb = NULL;
    181c:	63a2      	str	r2, [r4, #56]	; 0x38
	set_on_state(&sub_data->flags);
    181e:	4418      	add	r0, r3
    1820:	f002 fe27 	bl	4472 <set_on_state>
	if (callback) {
    1824:	b12d      	cbz	r5, 1832 <clkstarted_handle.constprop.0+0x2a>
		callback(dev, (clock_control_subsys_t)type, user_data);
    1826:	4632      	mov	r2, r6
    1828:	462b      	mov	r3, r5
    182a:	4803      	ldr	r0, [pc, #12]	; (1838 <clkstarted_handle.constprop.0+0x30>)
}
    182c:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		callback(dev, (clock_control_subsys_t)type, user_data);
    1830:	4718      	bx	r3
}
    1832:	bd70      	pop	{r4, r5, r6, pc}
    1834:	200001f8 	.word	0x200001f8
    1838:	00004c14 	.word	0x00004c14

0000183c <clock_event_handler>:
	switch (event) {
    183c:	b110      	cbz	r0, 1844 <clock_event_handler+0x8>
    183e:	2801      	cmp	r0, #1
    1840:	d004      	beq.n	184c <clock_event_handler+0x10>
    1842:	4770      	bx	lr
		if (GET_STATUS(data->flags) == CLOCK_CONTROL_STATUS_STARTING) {
    1844:	4b03      	ldr	r3, [pc, #12]	; (1854 <clock_event_handler+0x18>)
    1846:	6c1b      	ldr	r3, [r3, #64]	; 0x40
    1848:	075b      	lsls	r3, r3, #29
    184a:	d101      	bne.n	1850 <clock_event_handler+0x14>
		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_LFCLK);
    184c:	f7ff bfdc 	b.w	1808 <clkstarted_handle.constprop.0>
}
    1850:	4770      	bx	lr
    1852:	bf00      	nop
    1854:	200001f8 	.word	0x200001f8

00001858 <generic_hfclk_start>:
{
    1858:	b508      	push	{r3, lr}
	__asm__ volatile(
    185a:	f04f 0320 	mov.w	r3, #32
    185e:	f3ef 8111 	mrs	r1, BASEPRI
    1862:	f383 8812 	msr	BASEPRI_MAX, r3
    1866:	f3bf 8f6f 	isb	sy
	hfclk_users |= HF_USER_GENERIC;
    186a:	4a12      	ldr	r2, [pc, #72]	; (18b4 <generic_hfclk_start+0x5c>)
    186c:	6813      	ldr	r3, [r2, #0]
    186e:	f043 0002 	orr.w	r0, r3, #2
	if (hfclk_users & HF_USER_BT) {
    1872:	f013 0301 	ands.w	r3, r3, #1
	hfclk_users |= HF_USER_GENERIC;
    1876:	6010      	str	r0, [r2, #0]
	if (hfclk_users & HF_USER_BT) {
    1878:	d00c      	beq.n	1894 <generic_hfclk_start+0x3c>
            break;
        case NRF_CLOCK_DOMAIN_HFCLK:
            if (p_clk_src != NULL)
            {
                (*(nrf_clock_hfclk_t *)p_clk_src) =
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    187a:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    187e:	f8d2 340c 	ldr.w	r3, [r2, #1036]	; 0x40c
                                        >> CLOCK_HFCLKSTAT_SRC_Pos);
            }
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    1882:	f8d2 240c 	ldr.w	r2, [r2, #1036]	; 0x40c
		if (type == NRF_CLOCK_HFCLK_HIGH_ACCURACY) {
    1886:	f013 0301 	ands.w	r3, r3, #1
    188a:	d003      	beq.n	1894 <generic_hfclk_start+0x3c>
			set_on_state(get_hf_flags());
    188c:	480a      	ldr	r0, [pc, #40]	; (18b8 <generic_hfclk_start+0x60>)
    188e:	f002 fdf0 	bl	4472 <set_on_state>
			already_started = true;
    1892:	2301      	movs	r3, #1
	__asm__ volatile(
    1894:	f381 8811 	msr	BASEPRI, r1
    1898:	f3bf 8f6f 	isb	sy
	if (already_started) {
    189c:	b123      	cbz	r3, 18a8 <generic_hfclk_start+0x50>
}
    189e:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
		clkstarted_handle(CLOCK_DEVICE,
    18a2:	2000      	movs	r0, #0
    18a4:	f7ff bfb0 	b.w	1808 <clkstarted_handle.constprop.0>
}
    18a8:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_start(void)
{
    nrfx_clock_start(NRF_CLOCK_DOMAIN_HFCLK);
    18ac:	2001      	movs	r0, #1
    18ae:	f001 b857 	b.w	2960 <nrfx_clock_start>
    18b2:	bf00      	nop
    18b4:	20000248 	.word	0x20000248
    18b8:	20000238 	.word	0x20000238

000018bc <lfclk_start>:
{
    18bc:	b510      	push	{r4, lr}
	if (!once) {
    18be:	4c07      	ldr	r4, [pc, #28]	; (18dc <lfclk_start+0x20>)
    18c0:	7823      	ldrb	r3, [r4, #0]
    18c2:	b92b      	cbnz	r3, 18d0 <lfclk_start+0x14>
		arch_syscall_invoke1(*(uintptr_t *)&usec_to_wait, K_SYSCALL_K_BUSY_WAIT);
		return;
	}
#endif
	compiler_barrier();
	z_impl_k_busy_wait(usec_to_wait);
    18c4:	f44f 70a5 	mov.w	r0, #330	; 0x14a
    18c8:	f003 f978 	bl	4bbc <z_impl_k_busy_wait>
		once = true;
    18cc:	2301      	movs	r3, #1
    18ce:	7023      	strb	r3, [r4, #0]
}
    18d0:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    nrfx_clock_start(NRF_CLOCK_DOMAIN_LFCLK);
    18d4:	2000      	movs	r0, #0
    18d6:	f001 b843 	b.w	2960 <nrfx_clock_start>
    18da:	bf00      	nop
    18dc:	2000036d 	.word	0x2000036d

000018e0 <generic_hfclk_stop>:
    18e0:	4b09      	ldr	r3, [pc, #36]	; (1908 <generic_hfclk_stop+0x28>)
    18e2:	f3bf 8f5b 	dmb	ish
    18e6:	e853 2f00 	ldrex	r2, [r3]
    18ea:	f022 0102 	bic.w	r1, r2, #2
    18ee:	e843 1000 	strex	r0, r1, [r3]
    18f2:	2800      	cmp	r0, #0
    18f4:	d1f7      	bne.n	18e6 <generic_hfclk_stop+0x6>
    18f6:	f3bf 8f5b 	dmb	ish
	if (atomic_and(&hfclk_users, ~HF_USER_GENERIC) & HF_USER_BT) {
    18fa:	07d3      	lsls	r3, r2, #31
    18fc:	d402      	bmi.n	1904 <generic_hfclk_stop+0x24>
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_stop(void)
{
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLK);
    18fe:	2001      	movs	r0, #1
    1900:	f001 b87a 	b.w	29f8 <nrfx_clock_stop>
}
    1904:	4770      	bx	lr
    1906:	bf00      	nop
    1908:	20000248 	.word	0x20000248

0000190c <api_blocking_start>:
{
    190c:	b51f      	push	{r0, r1, r2, r3, r4, lr}
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    190e:	2200      	movs	r2, #0
    1910:	2301      	movs	r3, #1
    1912:	e9cd 2302 	strd	r2, r3, [sp, #8]
	err = api_start(dev, subsys, blocking_start_callback, &sem);
    1916:	4a09      	ldr	r2, [pc, #36]	; (193c <api_blocking_start+0x30>)
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    1918:	f8cd d000 	str.w	sp, [sp]
	err = api_start(dev, subsys, blocking_start_callback, &sem);
    191c:	466b      	mov	r3, sp
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    191e:	f8cd d004 	str.w	sp, [sp, #4]
	err = api_start(dev, subsys, blocking_start_callback, &sem);
    1922:	f002 fddc 	bl	44de <api_start>
	if (err < 0) {
    1926:	2800      	cmp	r0, #0
    1928:	db05      	blt.n	1936 <api_blocking_start+0x2a>
		/* coverity[OVERRUN] */
		return (int) arch_syscall_invoke3(*(uintptr_t *)&sem, parm0.split.lo, parm0.split.hi, K_SYSCALL_K_SEM_TAKE);
	}
#endif
	compiler_barrier();
	return z_impl_k_sem_take(sem, timeout);
    192a:	f44f 4280 	mov.w	r2, #16384	; 0x4000
    192e:	2300      	movs	r3, #0
    1930:	4668      	mov	r0, sp
    1932:	f001 fed7 	bl	36e4 <z_impl_k_sem_take>
}
    1936:	b005      	add	sp, #20
    1938:	f85d fb04 	ldr.w	pc, [sp], #4
    193c:	000044b1 	.word	0x000044b1

00001940 <z_nrf_clock_control_lf_on>:
{
    1940:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
	return __atomic_exchange_n(target, value, __ATOMIC_SEQ_CST);
    1944:	493a      	ldr	r1, [pc, #232]	; (1a30 <z_nrf_clock_control_lf_on+0xf0>)
    1946:	f3bf 8f5b 	dmb	ish
    194a:	4606      	mov	r6, r0
    194c:	2201      	movs	r2, #1
    194e:	e851 3f00 	ldrex	r3, [r1]
    1952:	e841 2000 	strex	r0, r2, [r1]
    1956:	2800      	cmp	r0, #0
    1958:	d1f9      	bne.n	194e <z_nrf_clock_control_lf_on+0xe>
    195a:	f3bf 8f5b 	dmb	ish
	if (atomic_set(&on, 1) == 0) {
    195e:	b933      	cbnz	r3, 196e <z_nrf_clock_control_lf_on+0x2e>
 */
static inline void sys_notify_init_spinwait(struct sys_notify *notify)
{
	__ASSERT_NO_MSG(notify != NULL);

	*notify = (struct sys_notify){
    1960:	4934      	ldr	r1, [pc, #208]	; (1a34 <z_nrf_clock_control_lf_on+0xf4>)
		err = onoff_request(mgr, &cli);
    1962:	4835      	ldr	r0, [pc, #212]	; (1a38 <z_nrf_clock_control_lf_on+0xf8>)
    1964:	604b      	str	r3, [r1, #4]
    1966:	60cb      	str	r3, [r1, #12]
    1968:	608a      	str	r2, [r1, #8]
    196a:	f002 fc28 	bl	41be <onoff_request>
	switch (start_mode) {
    196e:	1e73      	subs	r3, r6, #1
    1970:	2b01      	cmp	r3, #1
    1972:	d832      	bhi.n	19da <z_nrf_clock_control_lf_on+0x9a>
	if ((mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE) &&
    1974:	2e01      	cmp	r6, #1
    1976:	d107      	bne.n	1988 <z_nrf_clock_control_lf_on+0x48>
    return clk_src;
}

NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(NRF_CLOCK_Type const * p_reg)
{
    return (nrf_clock_lfclk_t)((p_reg->LFCLKSRCCOPY & CLOCK_LFCLKSRCCOPY_SRC_Msk)
    1978:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    197c:	f8d3 341c 	ldr.w	r3, [r3, #1052]	; 0x41c
    1980:	f003 0303 	and.w	r3, r3, #3
	    (target_type == NRF_CLOCK_LFCLK_Xtal) &&
    1984:	2b01      	cmp	r3, #1
    1986:	d028      	beq.n	19da <z_nrf_clock_control_lf_on+0x9a>
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    1988:	f003 f81e 	bl	49c8 <k_is_in_isr>
    198c:	4604      	mov	r4, r0
    198e:	b918      	cbnz	r0, 1998 <z_nrf_clock_control_lf_on+0x58>
 */
static inline bool k_is_pre_kernel(void)
{
	extern bool z_sys_post_kernel; /* in init.c */

	return !z_sys_post_kernel;
    1990:	4b2a      	ldr	r3, [pc, #168]	; (1a3c <z_nrf_clock_control_lf_on+0xfc>)
	int key = isr_mode ? irq_lock() : 0;
    1992:	781b      	ldrb	r3, [r3, #0]
    1994:	2b00      	cmp	r3, #0
    1996:	d144      	bne.n	1a22 <z_nrf_clock_control_lf_on+0xe2>
	__asm__ volatile(
    1998:	f04f 0320 	mov.w	r3, #32
    199c:	f3ef 8511 	mrs	r5, BASEPRI
    19a0:	f383 8812 	msr	BASEPRI_MAX, r3
    19a4:	f3bf 8f6f 	isb	sy
    19a8:	2401      	movs	r4, #1
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    19aa:	4f25      	ldr	r7, [pc, #148]	; (1a40 <z_nrf_clock_control_lf_on+0x100>)
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    19ac:	f8df 8094 	ldr.w	r8, [pc, #148]	; 1a44 <z_nrf_clock_control_lf_on+0x104>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    19b0:	f8df 9094 	ldr.w	r9, [pc, #148]	; 1a48 <z_nrf_clock_control_lf_on+0x108>
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    19b4:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    19b8:	f8d2 3418 	ldr.w	r3, [r2, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    19bc:	f8d2 2418 	ldr.w	r2, [r2, #1048]	; 0x418
    19c0:	03d2      	lsls	r2, r2, #15
    19c2:	d50c      	bpl.n	19de <z_nrf_clock_control_lf_on+0x9e>
                                        >> CLOCK_LFCLKSTAT_SRC_Pos);
    19c4:	f003 0303 	and.w	r3, r3, #3
	while (!(nrfx_clock_is_running(d, (void *)&type)
    19c8:	2b01      	cmp	r3, #1
    19ca:	d001      	beq.n	19d0 <z_nrf_clock_control_lf_on+0x90>
		     || (mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE)))) {
    19cc:	2e01      	cmp	r6, #1
    19ce:	d106      	bne.n	19de <z_nrf_clock_control_lf_on+0x9e>
	if (isr_mode) {
    19d0:	b30c      	cbz	r4, 1a16 <z_nrf_clock_control_lf_on+0xd6>
	__asm__ volatile(
    19d2:	f385 8811 	msr	BASEPRI, r5
    19d6:	f3bf 8f6f 	isb	sy
}
    19da:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
			if (isr_mode || !IS_ENABLED(CONFIG_MULTITHREADING)) {
    19de:	b1ac      	cbz	r4, 1a0c <z_nrf_clock_control_lf_on+0xcc>
 *
 * @return N/A
 */
static inline void k_cpu_atomic_idle(unsigned int key)
{
	arch_cpu_atomic_idle(key);
    19e0:	4628      	mov	r0, r5
    19e2:	f7ff fae3 	bl	fac <arch_cpu_atomic_idle>
    return (nrf_clock_lfclk_t)(p_reg->LFCLKSRC);
    19e6:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    19ea:	f8d2 3518 	ldr.w	r3, [r2, #1304]	; 0x518
		if ((target_type ==  NRF_CLOCK_LFCLK_Xtal)
    19ee:	2b00      	cmp	r3, #0
    19f0:	d1e0      	bne.n	19b4 <z_nrf_clock_control_lf_on+0x74>
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    19f2:	6839      	ldr	r1, [r7, #0]
		    && nrf_clock_event_check(NRF_CLOCK,
    19f4:	2900      	cmp	r1, #0
    19f6:	d0dd      	beq.n	19b4 <z_nrf_clock_control_lf_on+0x74>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    19f8:	603b      	str	r3, [r7, #0]
#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE void nrf_event_readback(void * p_event_reg)
{
#if NRFX_CHECK(NRFX_EVENT_READBACK_ENABLED) && !defined(NRF51)
    (void)*((volatile uint32_t *)(p_event_reg));
    19fa:	683b      	ldr	r3, [r7, #0]
    p_reg->LFCLKSRC = (uint32_t)(source);
    19fc:	2301      	movs	r3, #1
    19fe:	f8c2 3518 	str.w	r3, [r2, #1304]	; 0x518
    1a02:	f8c8 3180 	str.w	r3, [r8, #384]	; 0x180
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    1a06:	f8c9 3000 	str.w	r3, [r9]
}
    1a0a:	e7d3      	b.n	19b4 <z_nrf_clock_control_lf_on+0x74>
	return z_impl_k_sleep(timeout);
    1a0c:	2100      	movs	r1, #0
    1a0e:	2021      	movs	r0, #33	; 0x21
    1a10:	f002 f930 	bl	3c74 <z_impl_k_sleep>
	return k_sleep(Z_TIMEOUT_MS(ms));
    1a14:	e7e7      	b.n	19e6 <z_nrf_clock_control_lf_on+0xa6>
    p_reg->INTENSET = mask;
    1a16:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    1a1a:	2202      	movs	r2, #2
    1a1c:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
}
    1a20:	e7db      	b.n	19da <z_nrf_clock_control_lf_on+0x9a>
    p_reg->INTENCLR = mask;
    1a22:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    1a26:	2202      	movs	r2, #2
    1a28:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
	int key = isr_mode ? irq_lock() : 0;
    1a2c:	4605      	mov	r5, r0
}
    1a2e:	e7bc      	b.n	19aa <z_nrf_clock_control_lf_on+0x6a>
    1a30:	2000024c 	.word	0x2000024c
    1a34:	200001e8 	.word	0x200001e8
    1a38:	20000214 	.word	0x20000214
    1a3c:	2000077f 	.word	0x2000077f
    1a40:	40000104 	.word	0x40000104
    1a44:	e000e100 	.word	0xe000e100
    1a48:	40000008 	.word	0x40000008

00001a4c <rtt_console_init>:

	return character;
}

static int rtt_console_init(const struct device *d)
{
    1a4c:	b510      	push	{r4, lr}
	ARG_UNUSED(d);

	__printk_hook_install(rtt_console_out);
    1a4e:	4c04      	ldr	r4, [pc, #16]	; (1a60 <rtt_console_init+0x14>)
    1a50:	4620      	mov	r0, r4
    1a52:	f7fe fccb 	bl	3ec <__printk_hook_install>
	__stdout_hook_install(rtt_console_out);
    1a56:	4620      	mov	r0, r4
    1a58:	f7ff fe18 	bl	168c <__stdout_hook_install>

	return 0;
}
    1a5c:	2000      	movs	r0, #0
    1a5e:	bd10      	pop	{r4, pc}
    1a60:	00001a65 	.word	0x00001a65

00001a64 <rtt_console_out>:
{
    1a64:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
    1a66:	4e14      	ldr	r6, [pc, #80]	; (1ab8 <rtt_console_out+0x54>)
	char c = (char)character;
    1a68:	f88d 0007 	strb.w	r0, [sp, #7]
{
    1a6c:	4604      	mov	r4, r0
	char c = (char)character;
    1a6e:	2503      	movs	r5, #3
		SEGGER_RTT_LOCK();
    1a70:	f3ef 8711 	mrs	r7, BASEPRI
    1a74:	f04f 0120 	mov.w	r1, #32
    1a78:	f381 8811 	msr	BASEPRI, r1
		cnt = SEGGER_RTT_WriteNoLock(0, &c, 1);
    1a7c:	2201      	movs	r2, #1
    1a7e:	f10d 0107 	add.w	r1, sp, #7
    1a82:	2000      	movs	r0, #0
    1a84:	f001 fc72 	bl	336c <SEGGER_RTT_WriteNoLock>
		SEGGER_RTT_UNLOCK();
    1a88:	f387 8811 	msr	BASEPRI, r7
		if (cnt) {
    1a8c:	b120      	cbz	r0, 1a98 <rtt_console_out+0x34>
			host_present = true;
    1a8e:	2301      	movs	r3, #1
    1a90:	7033      	strb	r3, [r6, #0]
}
    1a92:	4620      	mov	r0, r4
    1a94:	b003      	add	sp, #12
    1a96:	bdf0      	pop	{r4, r5, r6, r7, pc}
		} else if (host_present) {
    1a98:	7833      	ldrb	r3, [r6, #0]
    1a9a:	2b00      	cmp	r3, #0
    1a9c:	d0f9      	beq.n	1a92 <rtt_console_out+0x2e>
			if (max_cnt) {
    1a9e:	3d01      	subs	r5, #1
    1aa0:	d008      	beq.n	1ab4 <rtt_console_out+0x50>
	if (!IS_ENABLED(CONFIG_MULTITHREADING) || k_is_in_isr()) {
    1aa2:	f002 ff91 	bl	49c8 <k_is_in_isr>
    1aa6:	2800      	cmp	r0, #0
    1aa8:	d1e2      	bne.n	1a70 <rtt_console_out+0xc>
    1aaa:	2100      	movs	r1, #0
    1aac:	2042      	movs	r0, #66	; 0x42
    1aae:	f002 f8e1 	bl	3c74 <z_impl_k_sleep>
		SEGGER_RTT_LOCK();
    1ab2:	e7dd      	b.n	1a70 <rtt_console_out+0xc>
				host_present = false;
    1ab4:	7035      	strb	r5, [r6, #0]
    1ab6:	e7ec      	b.n	1a92 <rtt_console_out+0x2e>
    1ab8:	2000036e 	.word	0x2000036e

00001abc <gpio_nrfx_pin_interrupt_configure>:

static int gpio_nrfx_pin_interrupt_configure(const struct device *port,
					     gpio_pin_t pin,
					     enum gpio_int_mode mode,
					     enum gpio_int_trig trig)
{
    1abc:	b530      	push	{r4, r5, lr}
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
    1abe:	6840      	ldr	r0, [r0, #4]
    1ac0:	7b04      	ldrb	r4, [r0, #12]
    1ac2:	f001 051f 	and.w	r5, r1, #31
	nrfx_err_t err;

	if (mode == GPIO_INT_MODE_DISABLED) {
    1ac6:	f5b2 5f00 	cmp.w	r2, #8192	; 0x2000
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
    1aca:	ea45 1544 	orr.w	r5, r5, r4, lsl #5
{
    1ace:	b085      	sub	sp, #20
    1ad0:	f04f 0400 	mov.w	r4, #0
	if (mode == GPIO_INT_MODE_DISABLED) {
    1ad4:	d104      	bne.n	1ae0 <gpio_nrfx_pin_interrupt_configure+0x24>
		nrfx_gpiote_trigger_disable(abs_pin);
    1ad6:	4628      	mov	r0, r5
    1ad8:	f001 fa38 	bl	2f4c <nrfx_gpiote_trigger_disable>
		return -EIO;
	}

	nrfx_gpiote_trigger_enable(abs_pin, true);

	return 0;
    1adc:	2000      	movs	r0, #0
    1ade:	e02e      	b.n	1b3e <gpio_nrfx_pin_interrupt_configure+0x82>
	if (mode == GPIO_INT_MODE_LEVEL) {
    1ae0:	f5b2 4f80 	cmp.w	r2, #16384	; 0x4000
	nrfx_gpiote_trigger_config_t trigger_config = {
    1ae4:	e9cd 4402 	strd	r4, r4, [sp, #8]
	if (mode == GPIO_INT_MODE_LEVEL) {
    1ae8:	d12b      	bne.n	1b42 <gpio_nrfx_pin_interrupt_configure+0x86>
		return trig == GPIO_INT_TRIG_LOW ? NRFX_GPIOTE_TRIGGER_LOW :
    1aea:	f5b3 3f00 	cmp.w	r3, #131072	; 0x20000
    1aee:	bf0c      	ite	eq
    1af0:	2304      	moveq	r3, #4
    1af2:	2305      	movne	r3, #5
	nrfx_gpiote_trigger_config_t trigger_config = {
    1af4:	f88d 3008 	strb.w	r3, [sp, #8]
	if (!(BIT(pin) & get_port_cfg(port)->edge_sense) &&
    1af8:	6883      	ldr	r3, [r0, #8]
    1afa:	fa23 f101 	lsr.w	r1, r3, r1
    1afe:	07c9      	lsls	r1, r1, #31
    1b00:	d42b      	bmi.n	1b5a <gpio_nrfx_pin_interrupt_configure+0x9e>
    1b02:	f5b2 3fa0 	cmp.w	r2, #81920	; 0x14000
    1b06:	d128      	bne.n	1b5a <gpio_nrfx_pin_interrupt_configure+0x9e>
}

NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin)
{
    uint32_t pin_number = *p_pin;
    *p_pin = pin_number & 0x1F;
    1b08:	f005 031f 	and.w	r3, r5, #31
    return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
    1b0c:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    1b10:	f04f 42a0 	mov.w	r2, #1342177280	; 0x50000000
    1b14:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
	    (mode == GPIO_INT_MODE_EDGE) &&
    1b18:	07db      	lsls	r3, r3, #31
    1b1a:	d41e      	bmi.n	1b5a <gpio_nrfx_pin_interrupt_configure+0x9e>
		err = nrfx_gpiote_channel_get(abs_pin, &ch);
    1b1c:	f10d 0407 	add.w	r4, sp, #7
    1b20:	4621      	mov	r1, r4
    1b22:	4628      	mov	r0, r5
    1b24:	f001 f980 	bl	2e28 <nrfx_gpiote_channel_get>
		if (err == NRFX_ERROR_INVALID_PARAM) {
    1b28:	4b14      	ldr	r3, [pc, #80]	; (1b7c <gpio_nrfx_pin_interrupt_configure+0xc0>)
    1b2a:	4298      	cmp	r0, r3
    1b2c:	d114      	bne.n	1b58 <gpio_nrfx_pin_interrupt_configure+0x9c>
			err = nrfx_gpiote_channel_alloc(&ch);
    1b2e:	4620      	mov	r0, r4
    1b30:	f001 f9c4 	bl	2ebc <nrfx_gpiote_channel_alloc>
			if (err != NRFX_SUCCESS) {
    1b34:	4b12      	ldr	r3, [pc, #72]	; (1b80 <gpio_nrfx_pin_interrupt_configure+0xc4>)
    1b36:	4298      	cmp	r0, r3
    1b38:	d00e      	beq.n	1b58 <gpio_nrfx_pin_interrupt_configure+0x9c>
				return -ENOMEM;
    1b3a:	f06f 000b 	mvn.w	r0, #11
}
    1b3e:	b005      	add	sp, #20
    1b40:	bd30      	pop	{r4, r5, pc}
	return trig == GPIO_INT_TRIG_BOTH ? NRFX_GPIOTE_TRIGGER_TOGGLE :
    1b42:	f5b3 2fc0 	cmp.w	r3, #393216	; 0x60000
    1b46:	d005      	beq.n	1b54 <gpio_nrfx_pin_interrupt_configure+0x98>
    1b48:	f5b3 3f00 	cmp.w	r3, #131072	; 0x20000
    1b4c:	bf0c      	ite	eq
    1b4e:	2302      	moveq	r3, #2
    1b50:	2301      	movne	r3, #1
    1b52:	e7cf      	b.n	1af4 <gpio_nrfx_pin_interrupt_configure+0x38>
    1b54:	2303      	movs	r3, #3
    1b56:	e7cd      	b.n	1af4 <gpio_nrfx_pin_interrupt_configure+0x38>
		trigger_config.p_in_channel = &ch;
    1b58:	9403      	str	r4, [sp, #12]
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    1b5a:	2300      	movs	r3, #0
    1b5c:	4619      	mov	r1, r3
    1b5e:	aa02      	add	r2, sp, #8
    1b60:	4628      	mov	r0, r5
    1b62:	f001 f825 	bl	2bb0 <nrfx_gpiote_input_configure>
	if (err != NRFX_SUCCESS) {
    1b66:	4b06      	ldr	r3, [pc, #24]	; (1b80 <gpio_nrfx_pin_interrupt_configure+0xc4>)
    1b68:	4298      	cmp	r0, r3
    1b6a:	d104      	bne.n	1b76 <gpio_nrfx_pin_interrupt_configure+0xba>
	nrfx_gpiote_trigger_enable(abs_pin, true);
    1b6c:	2101      	movs	r1, #1
    1b6e:	4628      	mov	r0, r5
    1b70:	f001 f9aa 	bl	2ec8 <nrfx_gpiote_trigger_enable>
    1b74:	e7b2      	b.n	1adc <gpio_nrfx_pin_interrupt_configure+0x20>
		return -EIO;
    1b76:	f06f 0004 	mvn.w	r0, #4
    1b7a:	e7e0      	b.n	1b3e <gpio_nrfx_pin_interrupt_configure+0x82>
    1b7c:	0bad0004 	.word	0x0bad0004
    1b80:	0bad0000 	.word	0x0bad0000

00001b84 <gpio_nrfx_init>:
}

#define GPIOTE_NODE DT_INST(0, nordic_nrf_gpiote)

static int gpio_nrfx_init(const struct device *port)
{
    1b84:	b510      	push	{r4, lr}
	nrfx_err_t err;

	if (nrfx_gpiote_is_init()) {
    1b86:	f001 f989 	bl	2e9c <nrfx_gpiote_is_init>
    1b8a:	4604      	mov	r4, r0
    1b8c:	b968      	cbnz	r0, 1baa <gpio_nrfx_init+0x26>
		return 0;
	}

	err = nrfx_gpiote_init(0/*not used*/);
    1b8e:	f001 f95d 	bl	2e4c <nrfx_gpiote_init>
	if (err != NRFX_SUCCESS) {
    1b92:	4b08      	ldr	r3, [pc, #32]	; (1bb4 <gpio_nrfx_init+0x30>)
    1b94:	4298      	cmp	r0, r3
    1b96:	d10a      	bne.n	1bae <gpio_nrfx_init+0x2a>
		return -EIO;
	}

	nrfx_gpiote_global_callback_set(nrfx_gpio_handler, NULL);
    1b98:	4807      	ldr	r0, [pc, #28]	; (1bb8 <gpio_nrfx_init+0x34>)
    1b9a:	4621      	mov	r1, r4
    1b9c:	f001 f93e 	bl	2e1c <nrfx_gpiote_global_callback_set>

	IRQ_CONNECT(DT_IRQN(GPIOTE_NODE), DT_IRQ(GPIOTE_NODE, priority),
    1ba0:	4622      	mov	r2, r4
    1ba2:	2105      	movs	r1, #5
    1ba4:	2006      	movs	r0, #6
    1ba6:	f7ff fa29 	bl	ffc <z_arm_irq_priority_set>
		return 0;
    1baa:	2000      	movs	r0, #0
		    nrfx_isr, nrfx_gpiote_irq_handler, 0);

	return 0;
}
    1bac:	bd10      	pop	{r4, pc}
		return -EIO;
    1bae:	f06f 0004 	mvn.w	r0, #4
    1bb2:	e7fb      	b.n	1bac <gpio_nrfx_init+0x28>
    1bb4:	0bad0000 	.word	0x0bad0000
    1bb8:	00001bbd 	.word	0x00001bbd

00001bbc <nrfx_gpio_handler>:
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    1bbc:	0943      	lsrs	r3, r0, #5
{
    1bbe:	b570      	push	{r4, r5, r6, lr}
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    1bc0:	d118      	bne.n	1bf4 <nrfx_gpio_handler+0x38>
					const struct device *port,
					uint32_t pins)
{
	struct gpio_callback *cb, *tmp;

	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    1bc2:	4b0d      	ldr	r3, [pc, #52]	; (1bf8 <nrfx_gpio_handler+0x3c>)
    1bc4:	6859      	ldr	r1, [r3, #4]
    1bc6:	b1a9      	cbz	r1, 1bf4 <nrfx_gpio_handler+0x38>
    1bc8:	680c      	ldr	r4, [r1, #0]
		if (cb->pin_mask & pins) {
			__ASSERT(cb->handler, "No callback handler!");
			cb->handler(port, cb, cb->pin_mask & pins);
    1bca:	4e0c      	ldr	r6, [pc, #48]	; (1bfc <nrfx_gpio_handler+0x40>)
	gpio_fire_callbacks(list, port, BIT(pin));
    1bcc:	2501      	movs	r5, #1
    1bce:	2c00      	cmp	r4, #0
    1bd0:	fa05 f500 	lsl.w	r5, r5, r0
	return node->next;
    1bd4:	bf38      	it	cc
    1bd6:	2400      	movcc	r4, #0
		if (cb->pin_mask & pins) {
    1bd8:	688a      	ldr	r2, [r1, #8]
    1bda:	402a      	ands	r2, r5
    1bdc:	d002      	beq.n	1be4 <nrfx_gpio_handler+0x28>
			cb->handler(port, cb, cb->pin_mask & pins);
    1bde:	684b      	ldr	r3, [r1, #4]
    1be0:	4630      	mov	r0, r6
    1be2:	4798      	blx	r3
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    1be4:	b134      	cbz	r4, 1bf4 <nrfx_gpio_handler+0x38>
    1be6:	6823      	ldr	r3, [r4, #0]
    1be8:	2b00      	cmp	r3, #0
    1bea:	bf38      	it	cc
    1bec:	2300      	movcc	r3, #0
Z_GENLIST_PEEK_NEXT_NO_CHECK(slist, snode)
    1bee:	4621      	mov	r1, r4
    1bf0:	461c      	mov	r4, r3
    1bf2:	e7f1      	b.n	1bd8 <nrfx_gpio_handler+0x1c>
}
    1bf4:	bd70      	pop	{r4, r5, r6, pc}
    1bf6:	bf00      	nop
    1bf8:	20000250 	.word	0x20000250
    1bfc:	00004c2c 	.word	0x00004c2c

00001c00 <gpio_nrfx_pin_configure>:
{
    1c00:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
	const struct gpio_nrfx_cfg *cfg = get_port_cfg(port);
    1c04:	6847      	ldr	r7, [r0, #4]
	nrfx_gpiote_pin_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    1c06:	7b3b      	ldrb	r3, [r7, #12]
    1c08:	f001 051f 	and.w	r5, r1, #31
{
    1c0c:	b085      	sub	sp, #20
    1c0e:	460e      	mov	r6, r1
	nrfx_gpiote_pin_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    1c10:	ea45 1543 	orr.w	r5, r5, r3, lsl #5
	if (flags == GPIO_DISCONNECTED) {
    1c14:	4614      	mov	r4, r2
    1c16:	b9ca      	cbnz	r2, 1c4c <gpio_nrfx_pin_configure+0x4c>
	err = nrfx_gpiote_channel_get(pin, &ch);
    1c18:	a902      	add	r1, sp, #8
    1c1a:	4628      	mov	r0, r5
    1c1c:	f001 f904 	bl	2e28 <nrfx_gpiote_channel_get>
    1c20:	4604      	mov	r4, r0
	err = nrfx_gpiote_pin_uninit(pin);
    1c22:	4628      	mov	r0, r5
    1c24:	f001 f9b4 	bl	2f90 <nrfx_gpiote_pin_uninit>
	if (err != NRFX_SUCCESS) {
    1c28:	4b48      	ldr	r3, [pc, #288]	; (1d4c <gpio_nrfx_pin_configure+0x14c>)
    1c2a:	4298      	cmp	r0, r3
    1c2c:	d004      	beq.n	1c38 <gpio_nrfx_pin_configure+0x38>
		return -EIO;
    1c2e:	f06f 0004 	mvn.w	r0, #4
}
    1c32:	b005      	add	sp, #20
    1c34:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
	if (free_ch) {
    1c38:	4284      	cmp	r4, r0
    1c3a:	d105      	bne.n	1c48 <gpio_nrfx_pin_configure+0x48>
		err = nrfx_gpiote_channel_free(ch);
    1c3c:	f89d 0008 	ldrb.w	r0, [sp, #8]
    1c40:	f001 f936 	bl	2eb0 <nrfx_gpiote_channel_free>
	return (err != NRFX_SUCCESS) ? -EIO : 0;
    1c44:	42a0      	cmp	r0, r4
    1c46:	d1f2      	bne.n	1c2e <gpio_nrfx_pin_configure+0x2e>
	return (err != NRFX_SUCCESS) ? -EINVAL : 0;
    1c48:	2000      	movs	r0, #0
    1c4a:	e7f2      	b.n	1c32 <gpio_nrfx_pin_configure+0x32>
	nrfx_gpiote_trigger_config_t trigger_config = {
    1c4c:	f04f 0900 	mov.w	r9, #0
	err = nrfx_gpiote_channel_get(pin, &ch);
    1c50:	f10d 0103 	add.w	r1, sp, #3
    1c54:	4630      	mov	r0, r6
	nrfx_gpiote_trigger_config_t trigger_config = {
    1c56:	e9cd 9902 	strd	r9, r9, [sp, #8]
	err = nrfx_gpiote_channel_get(pin, &ch);
    1c5a:	f001 f8e5 	bl	2e28 <nrfx_gpiote_channel_get>
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    1c5e:	464b      	mov	r3, r9
	err = nrfx_gpiote_channel_get(pin, &ch);
    1c60:	4680      	mov	r8, r0
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    1c62:	aa02      	add	r2, sp, #8
    1c64:	4649      	mov	r1, r9
    1c66:	4628      	mov	r0, r5
    1c68:	f000 ffa2 	bl	2bb0 <nrfx_gpiote_input_configure>
	if (err != NRFX_SUCCESS) {
    1c6c:	4b37      	ldr	r3, [pc, #220]	; (1d4c <gpio_nrfx_pin_configure+0x14c>)
    1c6e:	4298      	cmp	r0, r3
    1c70:	d002      	beq.n	1c78 <gpio_nrfx_pin_configure+0x78>
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    1c72:	f06f 0015 	mvn.w	r0, #21
    1c76:	e7dc      	b.n	1c32 <gpio_nrfx_pin_configure+0x32>
	if (free_ch) {
    1c78:	4580      	cmp	r8, r0
    1c7a:	d103      	bne.n	1c84 <gpio_nrfx_pin_configure+0x84>
		err = nrfx_gpiote_channel_free(ch);
    1c7c:	f89d 0003 	ldrb.w	r0, [sp, #3]
    1c80:	f001 f916 	bl	2eb0 <nrfx_gpiote_channel_free>
	if (flags & GPIO_OUTPUT) {
    1c84:	05a3      	lsls	r3, r4, #22
    1c86:	d54e      	bpl.n	1d26 <gpio_nrfx_pin_configure+0x126>
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    1c88:	4b31      	ldr	r3, [pc, #196]	; (1d50 <gpio_nrfx_pin_configure+0x150>)
    1c8a:	4a32      	ldr	r2, [pc, #200]	; (1d54 <gpio_nrfx_pin_configure+0x154>)
    1c8c:	4023      	ands	r3, r4
    1c8e:	4293      	cmp	r3, r2
    1c90:	d03a      	beq.n	1d08 <gpio_nrfx_pin_configure+0x108>
    1c92:	d80c      	bhi.n	1cae <gpio_nrfx_pin_configure+0xae>
    1c94:	2b06      	cmp	r3, #6
    1c96:	d014      	beq.n	1cc2 <gpio_nrfx_pin_configure+0xc2>
    1c98:	d804      	bhi.n	1ca4 <gpio_nrfx_pin_configure+0xa4>
    1c9a:	b193      	cbz	r3, 1cc2 <gpio_nrfx_pin_configure+0xc2>
    1c9c:	2b02      	cmp	r3, #2
    1c9e:	d1e8      	bne.n	1c72 <gpio_nrfx_pin_configure+0x72>
    1ca0:	2304      	movs	r3, #4
    1ca2:	e00e      	b.n	1cc2 <gpio_nrfx_pin_configure+0xc2>
    1ca4:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
    1ca8:	d1e3      	bne.n	1c72 <gpio_nrfx_pin_configure+0x72>
		*drive = NRF_GPIO_PIN_H0S1;
    1caa:	2301      	movs	r3, #1
    1cac:	e009      	b.n	1cc2 <gpio_nrfx_pin_configure+0xc2>
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    1cae:	4a2a      	ldr	r2, [pc, #168]	; (1d58 <gpio_nrfx_pin_configure+0x158>)
    1cb0:	4293      	cmp	r3, r2
    1cb2:	d02b      	beq.n	1d0c <gpio_nrfx_pin_configure+0x10c>
    1cb4:	f5b3 0fa0 	cmp.w	r3, #5242880	; 0x500000
    1cb8:	d02a      	beq.n	1d10 <gpio_nrfx_pin_configure+0x110>
    1cba:	f5b3 0f80 	cmp.w	r3, #4194304	; 0x400000
    1cbe:	d1d8      	bne.n	1c72 <gpio_nrfx_pin_configure+0x72>
		*drive = NRF_GPIO_PIN_S0H1;
    1cc0:	2302      	movs	r3, #2
		nrfx_gpiote_output_config_t output_config = {
    1cc2:	f88d 3004 	strb.w	r3, [sp, #4]
				NRF_GPIO_PIN_INPUT_CONNECT :
    1cc6:	f484 7380 	eor.w	r3, r4, #256	; 0x100
    1cca:	f3c3 2300 	ubfx	r3, r3, #8, #1
	if (flags & GPIO_PULL_UP) {
    1cce:	06e0      	lsls	r0, r4, #27
		nrfx_gpiote_output_config_t output_config = {
    1cd0:	f88d 3005 	strb.w	r3, [sp, #5]
		return NRF_GPIO_PIN_PULLDOWN;
    1cd4:	bf54      	ite	pl
    1cd6:	f3c4 1340 	ubfxpl	r3, r4, #5, #1
		return NRF_GPIO_PIN_PULLUP;
    1cda:	2303      	movmi	r3, #3
		if (flags & GPIO_OUTPUT_INIT_HIGH) {
    1cdc:	0521      	lsls	r1, r4, #20
		nrfx_gpiote_output_config_t output_config = {
    1cde:	f88d 3006 	strb.w	r3, [sp, #6]
		if (flags & GPIO_OUTPUT_INIT_HIGH) {
    1ce2:	d517      	bpl.n	1d14 <gpio_nrfx_pin_configure+0x114>
			nrf_gpio_port_out_set(cfg->port, BIT(pin));
    1ce4:	687b      	ldr	r3, [r7, #4]
    1ce6:	2101      	movs	r1, #1
    1ce8:	fa01 f606 	lsl.w	r6, r1, r6
    p_reg->OUTSET = set_mask;
    1cec:	f8c3 6508 	str.w	r6, [r3, #1288]	; 0x508
		err = nrfx_gpiote_output_configure(abs_pin, &output_config, NULL);
    1cf0:	2200      	movs	r2, #0
    1cf2:	a901      	add	r1, sp, #4
    1cf4:	4628      	mov	r0, r5
    1cf6:	f001 f801 	bl	2cfc <nrfx_gpiote_output_configure>
		return (err != NRFX_SUCCESS) ? -EINVAL : 0;
    1cfa:	4b14      	ldr	r3, [pc, #80]	; (1d4c <gpio_nrfx_pin_configure+0x14c>)
    1cfc:	4298      	cmp	r0, r3
    1cfe:	bf14      	ite	ne
    1d00:	f06f 0015 	mvnne.w	r0, #21
    1d04:	2000      	moveq	r0, #0
    1d06:	e794      	b.n	1c32 <gpio_nrfx_pin_configure+0x32>
		*drive = NRF_GPIO_PIN_H0D1;
    1d08:	2307      	movs	r3, #7
    1d0a:	e7da      	b.n	1cc2 <gpio_nrfx_pin_configure+0xc2>
		*drive = NRF_GPIO_PIN_D0H1;
    1d0c:	2305      	movs	r3, #5
    1d0e:	e7d8      	b.n	1cc2 <gpio_nrfx_pin_configure+0xc2>
		*drive = NRF_GPIO_PIN_H0H1;
    1d10:	2303      	movs	r3, #3
    1d12:	e7d6      	b.n	1cc2 <gpio_nrfx_pin_configure+0xc2>
		} else if (flags & GPIO_OUTPUT_INIT_LOW) {
    1d14:	0562      	lsls	r2, r4, #21
			nrf_gpio_port_out_clear(cfg->port, BIT(pin));
    1d16:	bf41      	itttt	mi
    1d18:	687b      	ldrmi	r3, [r7, #4]
    1d1a:	2101      	movmi	r1, #1
    1d1c:	fa01 f606 	lslmi.w	r6, r1, r6
    p_reg->OUTCLR = clr_mask;
    1d20:	f8c3 650c 	strmi.w	r6, [r3, #1292]	; 0x50c
}
    1d24:	e7e4      	b.n	1cf0 <gpio_nrfx_pin_configure+0xf0>
	if (flags & GPIO_PULL_UP) {
    1d26:	06e3      	lsls	r3, r4, #27
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    1d28:	f04f 0300 	mov.w	r3, #0
		return NRF_GPIO_PIN_PULLUP;
    1d2c:	bf54      	ite	pl
    1d2e:	f3c4 1440 	ubfxpl	r4, r4, #5, #1
    1d32:	2403      	movmi	r4, #3
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    1d34:	461a      	mov	r2, r3
    1d36:	a901      	add	r1, sp, #4
    1d38:	4628      	mov	r0, r5
	nrfx_gpiote_input_config_t input_config = {
    1d3a:	f88d 4004 	strb.w	r4, [sp, #4]
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    1d3e:	f000 ff37 	bl	2bb0 <nrfx_gpiote_input_configure>
	return (err != NRFX_SUCCESS) ? -EINVAL : 0;
    1d42:	4b02      	ldr	r3, [pc, #8]	; (1d4c <gpio_nrfx_pin_configure+0x14c>)
    1d44:	4298      	cmp	r0, r3
    1d46:	f43f af7f 	beq.w	1c48 <gpio_nrfx_pin_configure+0x48>
    1d4a:	e792      	b.n	1c72 <gpio_nrfx_pin_configure+0x72>
    1d4c:	0bad0000 	.word	0x0bad0000
    1d50:	00f00006 	.word	0x00f00006
    1d54:	00100006 	.word	0x00100006
    1d58:	00400002 	.word	0x00400002

00001d5c <pwm_nrfx_get_cycles_per_sec>:
{
	/* TODO: Since this function might be removed, we will always return
	 * 16MHz from this function and handle the conversion with prescaler,
	 * etc, in the pin set function. See issue #6958.
	 */
	*cycles = 16ul * 1000ul * 1000ul;
    1d5c:	4802      	ldr	r0, [pc, #8]	; (1d68 <pwm_nrfx_get_cycles_per_sec+0xc>)
    1d5e:	2100      	movs	r1, #0
    1d60:	e9c2 0100 	strd	r0, r1, [r2]

	return 0;
}
    1d64:	2000      	movs	r0, #0
    1d66:	4770      	bx	lr
    1d68:	00f42400 	.word	0x00f42400

00001d6c <pwm_nrfx_init>:
	.pin_set = pwm_nrfx_pin_set,
	.get_cycles_per_sec = pwm_nrfx_get_cycles_per_sec,
};

static int pwm_nrfx_init(const struct device *dev)
{
    1d6c:	4602      	mov	r2, r0
	const struct pwm_nrfx_config *config = dev->config;
    1d6e:	6840      	ldr	r0, [r0, #4]
	struct pwm_nrfx_data *data = dev->data;

	for (size_t i = 0; i < ARRAY_SIZE(data->current); i++) {
    1d70:	6912      	ldr	r2, [r2, #16]
{
    1d72:	b538      	push	{r3, r4, r5, lr}
    1d74:	f100 0308 	add.w	r3, r0, #8
    1d78:	3204      	adds	r2, #4
    1d7a:	f100 040c 	add.w	r4, r0, #12
    1d7e:	4619      	mov	r1, r3
		bool inverted = config->initial_config.output_pins[i] & NRFX_PWM_PIN_INVERTED;
		uint16_t value = (inverted)?(PWM_NRFX_CH_VALUE_INVERTED):(PWM_NRFX_CH_VALUE_NORMAL);
    1d80:	f913 5b01 	ldrsb.w	r5, [r3], #1
    1d84:	2d00      	cmp	r5, #0
    1d86:	bfb4      	ite	lt
    1d88:	2500      	movlt	r5, #0
    1d8a:	f44f 4500 	movge.w	r5, #32768	; 0x8000
	for (size_t i = 0; i < ARRAY_SIZE(data->current); i++) {
    1d8e:	42a3      	cmp	r3, r4

		data->current[i] = value;
    1d90:	f822 5b02 	strh.w	r5, [r2], #2
	for (size_t i = 0; i < ARRAY_SIZE(data->current); i++) {
    1d94:	d1f4      	bne.n	1d80 <pwm_nrfx_init+0x14>
	};

	nrfx_err_t result = nrfx_pwm_init(&config->pwm,
    1d96:	2300      	movs	r3, #0
    1d98:	461a      	mov	r2, r3
    1d9a:	f001 f9cb 	bl	3134 <nrfx_pwm_init>
					  &config->initial_config,
					  NULL,
					  NULL);
	if (result != NRFX_SUCCESS) {
    1d9e:	4b03      	ldr	r3, [pc, #12]	; (1dac <pwm_nrfx_init+0x40>)
		LOG_ERR("Failed to initialize device: %s", dev->name);
		return -EBUSY;
    1da0:	4298      	cmp	r0, r3
	}

	return 0;
}
    1da2:	bf14      	ite	ne
    1da4:	f06f 000f 	mvnne.w	r0, #15
    1da8:	2000      	moveq	r0, #0
    1daa:	bd38      	pop	{r3, r4, r5, pc}
    1dac:	0bad0000 	.word	0x0bad0000

00001db0 <uarte_nrfx_configure>:
	return 0;
}

static int uarte_nrfx_configure(const struct device *dev,
				const struct uart_config *cfg)
{
    1db0:	b570      	push	{r4, r5, r6, lr}
		break;
	default:
		return -ENOTSUP;
	}
#else
	if (cfg->stop_bits != UART_CFG_STOP_BITS_1) {
    1db2:	794b      	ldrb	r3, [r1, #5]
    1db4:	2b01      	cmp	r3, #1
    1db6:	d120      	bne.n	1dfa <uarte_nrfx_configure+0x4a>
		return -ENOTSUP;
	}
#endif

	if (cfg->data_bits != UART_CFG_DATA_BITS_8) {
    1db8:	798b      	ldrb	r3, [r1, #6]
    1dba:	2b03      	cmp	r3, #3
    1dbc:	d11d      	bne.n	1dfa <uarte_nrfx_configure+0x4a>
		return -ENOTSUP;
	}

	switch (cfg->flow_ctrl) {
    1dbe:	79cc      	ldrb	r4, [r1, #7]
    1dc0:	b10c      	cbz	r4, 1dc6 <uarte_nrfx_configure+0x16>
    1dc2:	2c01      	cmp	r4, #1
    1dc4:	d119      	bne.n	1dfa <uarte_nrfx_configure+0x4a>
	}

#if defined(UARTE_CONFIG_PARITYTYPE_Msk)
	uarte_cfg.paritytype = NRF_UARTE_PARITYTYPE_EVEN;
#endif
	switch (cfg->parity) {
    1dc6:	790a      	ldrb	r2, [r1, #4]
    1dc8:	b112      	cbz	r2, 1dd0 <uarte_nrfx_configure+0x20>
    1dca:	2a02      	cmp	r2, #2
    1dcc:	d115      	bne.n	1dfa <uarte_nrfx_configure+0x4a>
    1dce:	220e      	movs	r2, #14
#endif
	default:
		return -ENOTSUP;
	}

	if (baudrate_set(dev, cfg->baudrate) != 0) {
    1dd0:	680b      	ldr	r3, [r1, #0]
	return config->uarte_regs;
    1dd2:	6845      	ldr	r5, [r0, #4]
	switch (baudrate) {
    1dd4:	f5b3 4f16 	cmp.w	r3, #38400	; 0x9600
	return config->uarte_regs;
    1dd8:	682d      	ldr	r5, [r5, #0]
	switch (baudrate) {
    1dda:	d062      	beq.n	1ea2 <uarte_nrfx_configure+0xf2>
    1ddc:	d82b      	bhi.n	1e36 <uarte_nrfx_configure+0x86>
    1dde:	f5b3 5f16 	cmp.w	r3, #9600	; 0x2580
    1de2:	d061      	beq.n	1ea8 <uarte_nrfx_configure+0xf8>
    1de4:	d814      	bhi.n	1e10 <uarte_nrfx_configure+0x60>
    1de6:	f5b3 6f96 	cmp.w	r3, #1200	; 0x4b0
    1dea:	d05f      	beq.n	1eac <uarte_nrfx_configure+0xfc>
    1dec:	d808      	bhi.n	1e00 <uarte_nrfx_configure+0x50>
    1dee:	f5b3 7f96 	cmp.w	r3, #300	; 0x12c
    1df2:	d05e      	beq.n	1eb2 <uarte_nrfx_configure+0x102>
    1df4:	f5b3 7f16 	cmp.w	r3, #600	; 0x258
    1df8:	d05e      	beq.n	1eb8 <uarte_nrfx_configure+0x108>
    1dfa:	f06f 0085 	mvn.w	r0, #133	; 0x85
    1dfe:	e04f      	b.n	1ea0 <uarte_nrfx_configure+0xf0>
    1e00:	f5b3 6f16 	cmp.w	r3, #2400	; 0x960
    1e04:	d05b      	beq.n	1ebe <uarte_nrfx_configure+0x10e>
    1e06:	f5b3 5f96 	cmp.w	r3, #4800	; 0x12c0
    1e0a:	d1f6      	bne.n	1dfa <uarte_nrfx_configure+0x4a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_4800;
    1e0c:	4b36      	ldr	r3, [pc, #216]	; (1ee8 <uarte_nrfx_configure+0x138>)
    1e0e:	e03c      	b.n	1e8a <uarte_nrfx_configure+0xda>
	switch (baudrate) {
    1e10:	f5b3 4fe1 	cmp.w	r3, #28800	; 0x7080
    1e14:	d056      	beq.n	1ec4 <uarte_nrfx_configure+0x114>
    1e16:	d807      	bhi.n	1e28 <uarte_nrfx_configure+0x78>
    1e18:	f5b3 5f61 	cmp.w	r3, #14400	; 0x3840
    1e1c:	d054      	beq.n	1ec8 <uarte_nrfx_configure+0x118>
    1e1e:	f5b3 4f96 	cmp.w	r3, #19200	; 0x4b00
    1e22:	d1ea      	bne.n	1dfa <uarte_nrfx_configure+0x4a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_19200;
    1e24:	4b31      	ldr	r3, [pc, #196]	; (1eec <uarte_nrfx_configure+0x13c>)
    1e26:	e030      	b.n	1e8a <uarte_nrfx_configure+0xda>
	switch (baudrate) {
    1e28:	f647 2612 	movw	r6, #31250	; 0x7a12
    1e2c:	42b3      	cmp	r3, r6
    1e2e:	d1e4      	bne.n	1dfa <uarte_nrfx_configure+0x4a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_31250;
    1e30:	f44f 0300 	mov.w	r3, #8388608	; 0x800000
    1e34:	e029      	b.n	1e8a <uarte_nrfx_configure+0xda>
	switch (baudrate) {
    1e36:	f5b3 3f61 	cmp.w	r3, #230400	; 0x38400
    1e3a:	d047      	beq.n	1ecc <uarte_nrfx_configure+0x11c>
    1e3c:	d813      	bhi.n	1e66 <uarte_nrfx_configure+0xb6>
    1e3e:	f5b3 3f96 	cmp.w	r3, #76800	; 0x12c00
    1e42:	d046      	beq.n	1ed2 <uarte_nrfx_configure+0x122>
    1e44:	d809      	bhi.n	1e5a <uarte_nrfx_configure+0xaa>
    1e46:	f64d 26c0 	movw	r6, #56000	; 0xdac0
    1e4a:	42b3      	cmp	r3, r6
    1e4c:	d043      	beq.n	1ed6 <uarte_nrfx_configure+0x126>
    1e4e:	f5b3 4f61 	cmp.w	r3, #57600	; 0xe100
    1e52:	d1d2      	bne.n	1dfa <uarte_nrfx_configure+0x4a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_57600;
    1e54:	f44f 036b 	mov.w	r3, #15400960	; 0xeb0000
    1e58:	e017      	b.n	1e8a <uarte_nrfx_configure+0xda>
	switch (baudrate) {
    1e5a:	f5b3 3fe1 	cmp.w	r3, #115200	; 0x1c200
    1e5e:	d1cc      	bne.n	1dfa <uarte_nrfx_configure+0x4a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_115200;
    1e60:	f04f 73eb 	mov.w	r3, #30801920	; 0x1d60000
    1e64:	e011      	b.n	1e8a <uarte_nrfx_configure+0xda>
	switch (baudrate) {
    1e66:	f5b3 2f61 	cmp.w	r3, #921600	; 0xe1000
    1e6a:	d037      	beq.n	1edc <uarte_nrfx_configure+0x12c>
    1e6c:	d808      	bhi.n	1e80 <uarte_nrfx_configure+0xd0>
    1e6e:	4e20      	ldr	r6, [pc, #128]	; (1ef0 <uarte_nrfx_configure+0x140>)
    1e70:	42b3      	cmp	r3, r6
    1e72:	d036      	beq.n	1ee2 <uarte_nrfx_configure+0x132>
    1e74:	f5b3 2fe1 	cmp.w	r3, #460800	; 0x70800
    1e78:	d1bf      	bne.n	1dfa <uarte_nrfx_configure+0x4a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_460800;
    1e7a:	f04f 63e8 	mov.w	r3, #121634816	; 0x7400000
    1e7e:	e004      	b.n	1e8a <uarte_nrfx_configure+0xda>
	switch (baudrate) {
    1e80:	4e1c      	ldr	r6, [pc, #112]	; (1ef4 <uarte_nrfx_configure+0x144>)
    1e82:	42b3      	cmp	r3, r6
    1e84:	d1b9      	bne.n	1dfa <uarte_nrfx_configure+0x4a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_1000000;
    1e86:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
                    | (uint32_t)p_cfg->hwfc;
}

NRF_STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate)
{
    p_reg->BAUDRATE = baudrate;
    1e8a:	f8c5 3524 	str.w	r3, [r5, #1316]	; 0x524
		return -ENOTSUP;
	}

	nrf_uarte_configure(get_uarte_instance(dev), &uarte_cfg);

	get_dev_data(dev)->uart_config = *cfg;
    1e8e:	6903      	ldr	r3, [r0, #16]
    1e90:	c903      	ldmia	r1, {r0, r1}
                    | (uint32_t)p_cfg->hwfc;
    1e92:	4322      	orrs	r2, r4
    1e94:	3304      	adds	r3, #4
    p_reg->CONFIG = (uint32_t)p_cfg->parity
    1e96:	f8c5 256c 	str.w	r2, [r5, #1388]	; 0x56c
    1e9a:	e883 0003 	stmia.w	r3, {r0, r1}

	return 0;
    1e9e:	2000      	movs	r0, #0
}
    1ea0:	bd70      	pop	{r4, r5, r6, pc}
		nrf_baudrate = NRF_UARTE_BAUDRATE_38400;
    1ea2:	f44f 031d 	mov.w	r3, #10289152	; 0x9d0000
    1ea6:	e7f0      	b.n	1e8a <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_9600;
    1ea8:	4b13      	ldr	r3, [pc, #76]	; (1ef8 <uarte_nrfx_configure+0x148>)
    1eaa:	e7ee      	b.n	1e8a <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_1200;
    1eac:	f44f 239e 	mov.w	r3, #323584	; 0x4f000
    1eb0:	e7eb      	b.n	1e8a <uarte_nrfx_configure+0xda>
		nrf_baudrate = 0x00014000;
    1eb2:	f44f 33a0 	mov.w	r3, #81920	; 0x14000
    1eb6:	e7e8      	b.n	1e8a <uarte_nrfx_configure+0xda>
	switch (baudrate) {
    1eb8:	f44f 331c 	mov.w	r3, #159744	; 0x27000
    1ebc:	e7e5      	b.n	1e8a <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_2400;
    1ebe:	f44f 231d 	mov.w	r3, #643072	; 0x9d000
    1ec2:	e7e2      	b.n	1e8a <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_28800;
    1ec4:	4b0d      	ldr	r3, [pc, #52]	; (1efc <uarte_nrfx_configure+0x14c>)
    1ec6:	e7e0      	b.n	1e8a <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_14400;
    1ec8:	4b0d      	ldr	r3, [pc, #52]	; (1f00 <uarte_nrfx_configure+0x150>)
    1eca:	e7de      	b.n	1e8a <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_230400;
    1ecc:	f04f 736c 	mov.w	r3, #61865984	; 0x3b00000
    1ed0:	e7db      	b.n	1e8a <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_76800;
    1ed2:	4b0c      	ldr	r3, [pc, #48]	; (1f04 <uarte_nrfx_configure+0x154>)
    1ed4:	e7d9      	b.n	1e8a <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_56000;
    1ed6:	f44f 0365 	mov.w	r3, #15007744	; 0xe50000
    1eda:	e7d6      	b.n	1e8a <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_921600;
    1edc:	f04f 6370 	mov.w	r3, #251658240	; 0xf000000
    1ee0:	e7d3      	b.n	1e8a <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_250000;
    1ee2:	f04f 6380 	mov.w	r3, #67108864	; 0x4000000
    1ee6:	e7d0      	b.n	1e8a <uarte_nrfx_configure+0xda>
    1ee8:	0013b000 	.word	0x0013b000
    1eec:	004ea000 	.word	0x004ea000
    1ef0:	0003d090 	.word	0x0003d090
    1ef4:	000f4240 	.word	0x000f4240
    1ef8:	00275000 	.word	0x00275000
    1efc:	0075c000 	.word	0x0075c000
    1f00:	003af000 	.word	0x003af000
    1f04:	013a9000 	.word	0x013a9000

00001f08 <uarte_nrfx_poll_out>:
 *
 * @param dev UARTE device struct
 * @param c Character to send
 */
static void uarte_nrfx_poll_out(const struct device *dev, unsigned char c)
{
    1f08:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	struct uarte_nrfx_data *data = get_dev_data(dev);
    1f0a:	6906      	ldr	r6, [r0, #16]
{
    1f0c:	4605      	mov	r5, r0
    1f0e:	460f      	mov	r7, r1
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    1f10:	f002 fd5a 	bl	49c8 <k_is_in_isr>
    1f14:	b910      	cbnz	r0, 1f1c <uarte_nrfx_poll_out+0x14>
	return !z_sys_post_kernel;
    1f16:	4b2c      	ldr	r3, [pc, #176]	; (1fc8 <uarte_nrfx_poll_out+0xc0>)
	int key;

	if (isr_mode) {
    1f18:	781b      	ldrb	r3, [r3, #0]
    1f1a:	b983      	cbnz	r3, 1f3e <uarte_nrfx_poll_out+0x36>
	__asm__ volatile(
    1f1c:	f04f 0320 	mov.w	r3, #32
    1f20:	f3ef 8411 	mrs	r4, BASEPRI
    1f24:	f383 8812 	msr	BASEPRI_MAX, r3
    1f28:	f3bf 8f6f 	isb	sy
		while (1) {
			key = irq_lock();
			if (is_tx_ready(dev)) {
    1f2c:	4628      	mov	r0, r5
    1f2e:	f002 fc55 	bl	47dc <is_tx_ready>
    1f32:	bb28      	cbnz	r0, 1f80 <uarte_nrfx_poll_out+0x78>
	__asm__ volatile(
    1f34:	f384 8811 	msr	BASEPRI, r4
    1f38:	f3bf 8f6f 	isb	sy
}
    1f3c:	e7ee      	b.n	1f1c <uarte_nrfx_poll_out+0x14>
{
    1f3e:	2464      	movs	r4, #100	; 0x64
		NRFX_WAIT_FOR(is_tx_ready(dev), 100, 1, res);
    1f40:	4628      	mov	r0, r5
    1f42:	f002 fc4b 	bl	47dc <is_tx_ready>
    1f46:	b970      	cbnz	r0, 1f66 <uarte_nrfx_poll_out+0x5e>
    1f48:	2001      	movs	r0, #1
    1f4a:	f002 fc70 	bl	482e <nrfx_busy_wait>
    1f4e:	3c01      	subs	r4, #1
    1f50:	d1f6      	bne.n	1f40 <uarte_nrfx_poll_out+0x38>
    1f52:	2100      	movs	r1, #0
    1f54:	2021      	movs	r0, #33	; 0x21
    1f56:	f001 fe8d 	bl	3c74 <z_impl_k_sleep>
	return k_sleep(Z_TIMEOUT_MS(ms));
    1f5a:	e7f0      	b.n	1f3e <uarte_nrfx_poll_out+0x36>
	__asm__ volatile(
    1f5c:	f384 8811 	msr	BASEPRI, r4
    1f60:	f3bf 8f6f 	isb	sy
}
    1f64:	e7f5      	b.n	1f52 <uarte_nrfx_poll_out+0x4a>
	__asm__ volatile(
    1f66:	f04f 0320 	mov.w	r3, #32
    1f6a:	f3ef 8411 	mrs	r4, BASEPRI
    1f6e:	f383 8812 	msr	BASEPRI_MAX, r3
    1f72:	f3bf 8f6f 	isb	sy
			if (is_tx_ready(dev)) {
    1f76:	4628      	mov	r0, r5
    1f78:	f002 fc30 	bl	47dc <is_tx_ready>
    1f7c:	2800      	cmp	r0, #0
    1f7e:	d0ed      	beq.n	1f5c <uarte_nrfx_poll_out+0x54>
		}
	} else {
		key = wait_tx_ready(dev);
	}

	data->char_out = c;
    1f80:	f806 7f10 	strb.w	r7, [r6, #16]!
	const struct uarte_nrfx_config *config = get_dev_config(dev);
    1f84:	6869      	ldr	r1, [r5, #4]
	return config->uarte_regs;
    1f86:	680b      	ldr	r3, [r1, #0]
NRF_STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,
                                               uint8_t  const * p_buffer,
                                               size_t           length)
{
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    p_reg->TXD.MAXCNT = length;
    1f88:	2201      	movs	r2, #1
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    1f8a:	f8c3 6544 	str.w	r6, [r3, #1348]	; 0x544
    p_reg->TXD.MAXCNT = length;
    1f8e:	f8c3 2548 	str.w	r2, [r3, #1352]	; 0x548
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    1f92:	2200      	movs	r2, #0
    1f94:	f8c3 2120 	str.w	r2, [r3, #288]	; 0x120
    1f98:	f8d3 0120 	ldr.w	r0, [r3, #288]	; 0x120
    1f9c:	f8c3 2158 	str.w	r2, [r3, #344]	; 0x158
    1fa0:	f8d3 2158 	ldr.w	r2, [r3, #344]	; 0x158
	if (get_dev_config(dev)->flags & UARTE_CFG_FLAG_LOW_POWER) {
    1fa4:	684a      	ldr	r2, [r1, #4]
    1fa6:	06d2      	lsls	r2, r2, #27
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
    1fa8:	bf41      	itttt	mi
    1faa:	2208      	movmi	r2, #8
    1fac:	f8c3 2500 	strmi.w	r2, [r3, #1280]	; 0x500
    p_reg->INTENSET = mask;
    1fb0:	f44f 0280 	movmi.w	r2, #4194304	; 0x400000
    1fb4:	f8c3 2304 	strmi.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    1fb8:	2201      	movs	r2, #1
    1fba:	609a      	str	r2, [r3, #8]
	__asm__ volatile(
    1fbc:	f384 8811 	msr	BASEPRI, r4
    1fc0:	f3bf 8f6f 	isb	sy
	tx_start(dev, &data->char_out, 1);

	irq_unlock(key);
}
    1fc4:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    1fc6:	bf00      	nop
    1fc8:	2000077f 	.word	0x2000077f

00001fcc <uarte_0_init>:
				.tx_buffer = uarte##idx##_tx_buffer,	       \
				.tx_buff_size = sizeof(uarte##idx##_tx_buffer),\
			};))

#ifdef CONFIG_UART_0_NRF_UARTE
UART_NRF_UARTE_DEVICE(0);
    1fcc:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    1fd0:	2101      	movs	r1, #1
    1fd2:	4605      	mov	r5, r0
    1fd4:	2200      	movs	r2, #0
    1fd6:	2002      	movs	r0, #2
    1fd8:	f7ff f810 	bl	ffc <z_arm_irq_priority_set>
    1fdc:	2002      	movs	r0, #2
    1fde:	f7fe ffef 	bl	fc0 <arch_irq_enable>
	const struct uarte_nrfx_config *config = get_dev_config(dev);
    1fe2:	686f      	ldr	r7, [r5, #4]
	struct uarte_nrfx_data *data = get_dev_data(dev);
    1fe4:	692e      	ldr	r6, [r5, #16]
	return config->uarte_regs;
    1fe6:	683c      	ldr	r4, [r7, #0]
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
    1fe8:	2300      	movs	r3, #0
    1fea:	f8c4 3500 	str.w	r3, [r4, #1280]	; 0x500
	data->dev = dev;
    1fee:	6035      	str	r5, [r6, #0]
	const struct uarte_nrfx_config *cfg = get_dev_config(dev);
    1ff0:	686b      	ldr	r3, [r5, #4]
		if (cfg->tx_pin != NRF_UARTE_PSEL_DISCONNECTED) {
    1ff2:	68d8      	ldr	r0, [r3, #12]
    1ff4:	1c41      	adds	r1, r0, #1
    1ff6:	d00c      	beq.n	2012 <uarte_0_init+0x46>
    *p_pin = pin_number & 0x1F;
    1ff8:	f000 021f 	and.w	r2, r0, #31
    p_reg->OUTSET = set_mask;
    1ffc:	f04f 4ca0 	mov.w	ip, #1342177280	; 0x50000000
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    2000:	2101      	movs	r1, #1
    2002:	4091      	lsls	r1, r2
    reg->PIN_CNF[pin_number] = cnf;
    2004:	f502 72e0 	add.w	r2, r2, #448	; 0x1c0
    p_reg->OUTSET = set_mask;
    2008:	f8cc 1508 	str.w	r1, [ip, #1288]	; 0x508
    reg->PIN_CNF[pin_number] = cnf;
    200c:	2103      	movs	r1, #3
    200e:	f84c 1022 	str.w	r1, [ip, r2, lsl #2]
		if (cfg->rx_pin != NRF_UARTE_PSEL_DISCONNECTED) {
    2012:	6919      	ldr	r1, [r3, #16]
    2014:	1c4a      	adds	r2, r1, #1
    2016:	d00e      	beq.n	2036 <uarte_0_init+0x6a>
			nrf_gpio_cfg_input(cfg->rx_pin,
    2018:	7f1a      	ldrb	r2, [r3, #28]
    201a:	2a00      	cmp	r2, #0
    *p_pin = pin_number & 0x1F;
    201c:	f001 021f 	and.w	r2, r1, #31
    reg->PIN_CNF[pin_number] = cnf;
    2020:	f502 72e0 	add.w	r2, r2, #448	; 0x1c0
    2024:	f04f 4ca0 	mov.w	ip, #1342177280	; 0x50000000
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    2028:	bf14      	ite	ne
    202a:	f04f 0e0c 	movne.w	lr, #12
    202e:	f04f 0e00 	moveq.w	lr, #0
    reg->PIN_CNF[pin_number] = cnf;
    2032:	f84c e022 	str.w	lr, [ip, r2, lsl #2]
		if (cfg->rts_pin != NRF_UARTE_PSEL_DISCONNECTED) {
    2036:	f8d3 c014 	ldr.w	ip, [r3, #20]
    203a:	f1bc 3fff 	cmp.w	ip, #4294967295
    203e:	d00f      	beq.n	2060 <uarte_0_init+0x94>
    *p_pin = pin_number & 0x1F;
    2040:	f00c 021f 	and.w	r2, ip, #31
    p_reg->OUTSET = set_mask;
    2044:	f04f 48a0 	mov.w	r8, #1342177280	; 0x50000000
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    2048:	f04f 0e01 	mov.w	lr, #1
    204c:	fa0e fe02 	lsl.w	lr, lr, r2
    reg->PIN_CNF[pin_number] = cnf;
    2050:	f502 72e0 	add.w	r2, r2, #448	; 0x1c0
    p_reg->OUTSET = set_mask;
    2054:	f8c8 e508 	str.w	lr, [r8, #1288]	; 0x508
    reg->PIN_CNF[pin_number] = cnf;
    2058:	f04f 0e03 	mov.w	lr, #3
    205c:	f848 e022 	str.w	lr, [r8, r2, lsl #2]
		if (cfg->cts_pin != NRF_UARTE_PSEL_DISCONNECTED) {
    2060:	f8d3 e018 	ldr.w	lr, [r3, #24]
    2064:	f1be 3fff 	cmp.w	lr, #4294967295
    2068:	d00e      	beq.n	2088 <uarte_0_init+0xbc>
			nrf_gpio_cfg_input(cfg->cts_pin,
    206a:	7f5a      	ldrb	r2, [r3, #29]
    206c:	2a00      	cmp	r2, #0
    *p_pin = pin_number & 0x1F;
    206e:	f00e 021f 	and.w	r2, lr, #31
    reg->PIN_CNF[pin_number] = cnf;
    2072:	f502 72e0 	add.w	r2, r2, #448	; 0x1c0
    2076:	f04f 48a0 	mov.w	r8, #1342177280	; 0x50000000
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    207a:	bf14      	ite	ne
    207c:	f04f 090c 	movne.w	r9, #12
    2080:	f04f 0900 	moveq.w	r9, #0
    reg->PIN_CNF[pin_number] = cnf;
    2084:	f848 9022 	str.w	r9, [r8, r2, lsl #2]
	nrf_uarte_txrx_pins_set(cfg->uarte_regs, cfg->tx_pin, cfg->rx_pin);
    2088:	681b      	ldr	r3, [r3, #0]
    p_reg->PSEL.TXD = pseltxd;
    208a:	f8c3 050c 	str.w	r0, [r3, #1292]	; 0x50c
    p_reg->PSEL.RXD = pselrxd;
    208e:	f8c3 1514 	str.w	r1, [r3, #1300]	; 0x514
	err = uarte_nrfx_configure(dev, &get_dev_data(dev)->uart_config);
    2092:	6929      	ldr	r1, [r5, #16]
    p_reg->PSEL.RTS = pselrts;
    2094:	f8c3 c508 	str.w	ip, [r3, #1288]	; 0x508
    2098:	4628      	mov	r0, r5
    p_reg->PSEL.CTS = pselcts;
    209a:	f8c3 e510 	str.w	lr, [r3, #1296]	; 0x510
    209e:	3104      	adds	r1, #4
    20a0:	f7ff fe86 	bl	1db0 <uarte_nrfx_configure>
	if (err) {
    20a4:	4605      	mov	r5, r0
    20a6:	2800      	cmp	r0, #0
    20a8:	d143      	bne.n	2132 <uarte_0_init+0x166>
	    cfg->flags & UARTE_CFG_FLAG_PPI_ENDTX) {
    20aa:	687b      	ldr	r3, [r7, #4]
	if (IS_ENABLED(CONFIG_UART_ENHANCED_POLL_OUT) &&
    20ac:	0799      	lsls	r1, r3, #30
    20ae:	d519      	bpl.n	20e4 <uarte_0_init+0x118>
	ret = gppi_channel_alloc(&data->ppi_ch_endtx);
    20b0:	f106 0012 	add.w	r0, r6, #18
    20b4:	f001 f838 	bl	3128 <nrfx_ppi_channel_alloc>
	if (ret != NRFX_SUCCESS) {
    20b8:	4b21      	ldr	r3, [pc, #132]	; (2140 <uarte_0_init+0x174>)
    20ba:	4298      	cmp	r0, r3
    20bc:	d13c      	bne.n	2138 <uarte_0_init+0x16c>
	nrfx_gppi_channel_endpoints_setup(data->ppi_ch_endtx,
    20be:	7cb0      	ldrb	r0, [r6, #18]
    return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
    20c0:	00c3      	lsls	r3, r0, #3
    20c2:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    20c6:	f503 33f8 	add.w	r3, r3, #126976	; 0x1f000
    return (uint32_t)p_reg + (uint32_t)task;
    20ca:	f104 020c 	add.w	r2, r4, #12
    return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
    20ce:	f504 7190 	add.w	r1, r4, #288	; 0x120
NRF_STATIC_INLINE void nrf_ppi_channel_endpoint_setup(NRF_PPI_Type *    p_reg,
                                                      nrf_ppi_channel_t channel,
                                                      uint32_t          eep,
                                                      uint32_t          tep)
{
    p_reg->CH[(uint32_t) channel].EEP = eep;
    20d2:	f8c3 1510 	str.w	r1, [r3, #1296]	; 0x510
    p_reg->CH[(uint32_t) channel].TEP = tep;
    20d6:	f8c3 2514 	str.w	r2, [r3, #1300]	; 0x514
    p_reg->CHENSET = mask;
    20da:	4a1a      	ldr	r2, [pc, #104]	; (2144 <uarte_0_init+0x178>)
	nrfx_gppi_channels_enable(BIT(data->ppi_ch_endtx));
    20dc:	2301      	movs	r3, #1
    20de:	4083      	lsls	r3, r0
    20e0:	f8c2 3504 	str.w	r3, [r2, #1284]	; 0x504
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
    20e4:	2308      	movs	r3, #8
    20e6:	f8c4 3500 	str.w	r3, [r4, #1280]	; 0x500
		if (!cfg->disable_rx) {
    20ea:	7a3b      	ldrb	r3, [r7, #8]
    20ec:	b95b      	cbnz	r3, 2106 <uarte_0_init+0x13a>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    20ee:	f8c4 3110 	str.w	r3, [r4, #272]	; 0x110
    20f2:	f8d4 3110 	ldr.w	r3, [r4, #272]	; 0x110
			nrf_uarte_rx_buffer_set(uarte, &data->rx_data, 1);
    20f6:	f106 0311 	add.w	r3, r6, #17

NRF_STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
                                               uint8_t *        p_buffer,
                                               size_t           length)
{
    p_reg->RXD.PTR    = (uint32_t)p_buffer;
    20fa:	f8c4 3534 	str.w	r3, [r4, #1332]	; 0x534
    p_reg->RXD.MAXCNT = length;
    20fe:	2301      	movs	r3, #1
    2100:	f8c4 3538 	str.w	r3, [r4, #1336]	; 0x538
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2104:	6023      	str	r3, [r4, #0]
	if (!(cfg->flags & UARTE_CFG_FLAG_PPI_ENDTX)) {
    2106:	687b      	ldr	r3, [r7, #4]
    2108:	079a      	lsls	r2, r3, #30
    p_reg->INTENSET = mask;
    210a:	bf5c      	itt	pl
    210c:	f44f 7280 	movpl.w	r2, #256	; 0x100
    2110:	f8c4 2304 	strpl.w	r2, [r4, #772]	; 0x304
	if (cfg->flags & UARTE_CFG_FLAG_LOW_POWER) {
    2114:	06db      	lsls	r3, r3, #27
    2116:	bf44      	itt	mi
    2118:	f44f 0380 	movmi.w	r3, #4194304	; 0x400000
    211c:	f8c4 3304 	strmi.w	r3, [r4, #772]	; 0x304
	nrf_uarte_tx_buffer_set(uarte, &data->char_out, 0);
    2120:	3610      	adds	r6, #16
    p_reg->TXD.MAXCNT = length;
    2122:	2300      	movs	r3, #0
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    2124:	f8c4 6544 	str.w	r6, [r4, #1348]	; 0x544
    p_reg->TXD.MAXCNT = length;
    2128:	f8c4 3548 	str.w	r3, [r4, #1352]	; 0x548
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    212c:	2301      	movs	r3, #1
    212e:	60a3      	str	r3, [r4, #8]
    2130:	60e3      	str	r3, [r4, #12]
UART_NRF_UARTE_DEVICE(0);
    2132:	4628      	mov	r0, r5
    2134:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
		return -EIO;
    2138:	f06f 0504 	mvn.w	r5, #4
UART_NRF_UARTE_DEVICE(0);
    213c:	e7f9      	b.n	2132 <uarte_0_init+0x166>
    213e:	bf00      	nop
    2140:	0bad0000 	.word	0x0bad0000
    2144:	4001f000 	.word	0x4001f000

00002148 <sys_clock_timeout_handler>:
static void sys_clock_timeout_handler(int32_t chan,
				      uint64_t expire_time,
				      void *user_data)
{
	uint32_t cc_value = absolute_time_to_cc(expire_time);
	uint64_t dticks = (expire_time - last_count) / CYC_PER_TICK;
    2148:	4919      	ldr	r1, [pc, #100]	; (21b0 <sys_clock_timeout_handler+0x68>)
{
    214a:	b570      	push	{r4, r5, r6, lr}
    214c:	4604      	mov	r4, r0
	return absolute_time & COUNTER_MAX;
    214e:	f022 467f 	bic.w	r6, r2, #4278190080	; 0xff000000
	uint64_t dticks = (expire_time - last_count) / CYC_PER_TICK;
    2152:	6808      	ldr	r0, [r1, #0]

	last_count += dticks * CYC_PER_TICK;
    2154:	e9c1 2300 	strd	r2, r3, [r1]
	return (cc_value >= ANCHOR_RANGE_START) && (cc_value < ANCHOR_RANGE_END);
    2158:	f5a6 1300 	sub.w	r3, r6, #2097152	; 0x200000
	uint64_t dticks = (expire_time - last_count) / CYC_PER_TICK;
    215c:	1a10      	subs	r0, r2, r0
	if (in_anchor_range(cc_value)) {
    215e:	f5b3 0f40 	cmp.w	r3, #12582912	; 0xc00000
    2162:	f04f 0500 	mov.w	r5, #0
    2166:	d20a      	bcs.n	217e <sys_clock_timeout_handler+0x36>
		anchor = (((uint64_t)overflow_cnt) << COUNTER_BIT_WIDTH) + cc_value;
    2168:	4b12      	ldr	r3, [pc, #72]	; (21b4 <sys_clock_timeout_handler+0x6c>)
    216a:	6819      	ldr	r1, [r3, #0]
    216c:	060a      	lsls	r2, r1, #24
    216e:	0a0b      	lsrs	r3, r1, #8
    2170:	1992      	adds	r2, r2, r6
    2172:	4911      	ldr	r1, [pc, #68]	; (21b8 <sys_clock_timeout_handler+0x70>)
    2174:	f143 0300 	adc.w	r3, r3, #0
    2178:	e9c1 2300 	strd	r2, r3, [r1]
		return true;
    217c:	2501      	movs	r5, #1
		 */
		compare_set(chan, last_count + CYC_PER_TICK,
					  sys_clock_timeout_handler, NULL);
	}

	sys_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
    217e:	f001 fedd 	bl	3f3c <sys_clock_announce>
    p_reg->CC[ch] = cc_val;
}

NRF_STATIC_INLINE  uint32_t nrf_rtc_cc_get(NRF_RTC_Type const * p_reg, uint32_t ch)
{
    return p_reg->CC[ch];
    2182:	00a3      	lsls	r3, r4, #2
    2184:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    2188:	f503 3388 	add.w	r3, r3, #69632	; 0x11000
    218c:	f8d3 2540 	ldr.w	r2, [r3, #1344]	; 0x540
			   (int32_t)dticks : (dticks > 0));

	if (cc_value == get_comparator(chan)) {
    2190:	42b2      	cmp	r2, r6
    2192:	d10b      	bne.n	21ac <sys_clock_timeout_handler+0x64>
		 * If anchor was updated we can enable same CC value to trigger
		 * interrupt after full cycle. Else set event in anchor update
		 * range. Since anchor was not updated we know that it's very
		 * far from mid point so setting is done without any protection.
		 */
		if (!anchor_updated) {
    2194:	b91d      	cbnz	r5, 219e <sys_clock_timeout_handler+0x56>
    p_reg->CC[ch] = cc_val;
    2196:	f44f 0200 	mov.w	r2, #8388608	; 0x800000
    219a:	f8c3 2540 	str.w	r2, [r3, #1344]	; 0x540
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
}

NRF_STATIC_INLINE void nrf_rtc_event_enable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->EVTENSET = mask;
    219e:	4b07      	ldr	r3, [pc, #28]	; (21bc <sys_clock_timeout_handler+0x74>)
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    21a0:	f44f 3080 	mov.w	r0, #65536	; 0x10000
    21a4:	fa00 f404 	lsl.w	r4, r0, r4
    21a8:	f8c3 4344 	str.w	r4, [r3, #836]	; 0x344
			set_comparator(chan, COUNTER_HALF_SPAN);
		}
		event_enable(chan);
	}
}
    21ac:	bd70      	pop	{r4, r5, r6, pc}
    21ae:	bf00      	nop
    21b0:	200000b0 	.word	0x200000b0
    21b4:	20000274 	.word	0x20000274
    21b8:	20000098 	.word	0x20000098
    21bc:	40011000 	.word	0x40011000

000021c0 <compare_int_lock>:
{
    21c0:	b510      	push	{r4, lr}
	atomic_val_t prev = atomic_and(&int_mask, ~BIT(chan));
    21c2:	2301      	movs	r3, #1
    21c4:	4083      	lsls	r3, r0
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    21c6:	4a11      	ldr	r2, [pc, #68]	; (220c <compare_int_lock+0x4c>)
    21c8:	f3bf 8f5b 	dmb	ish
    21cc:	43dc      	mvns	r4, r3
    21ce:	e852 1f00 	ldrex	r1, [r2]
    21d2:	ea01 0c04 	and.w	ip, r1, r4
    21d6:	e842 ce00 	strex	lr, ip, [r2]
    21da:	f1be 0f00 	cmp.w	lr, #0
    21de:	d1f6      	bne.n	21ce <compare_int_lock+0xe>
    21e0:	f3bf 8f5b 	dmb	ish
	nrf_rtc_int_disable(RTC, RTC_CHANNEL_INT_MASK(chan));
    21e4:	f44f 3280 	mov.w	r2, #65536	; 0x10000
    21e8:	fa02 f000 	lsl.w	r0, r2, r0
    p_reg->INTENCLR = mask;
    21ec:	f102 4280 	add.w	r2, r2, #1073741824	; 0x40000000
    21f0:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
    21f4:	f8c2 0308 	str.w	r0, [r2, #776]	; 0x308
  __ASM volatile ("dmb 0xF":::"memory");
    21f8:	f3bf 8f5f 	dmb	sy
  __ASM volatile ("isb 0xF":::"memory");
    21fc:	f3bf 8f6f 	isb	sy
	return prev & BIT(chan);
    2200:	420b      	tst	r3, r1
}
    2202:	bf14      	ite	ne
    2204:	2001      	movne	r0, #1
    2206:	2000      	moveq	r0, #0
    2208:	bd10      	pop	{r4, pc}
    220a:	bf00      	nop
    220c:	20000270 	.word	0x20000270

00002210 <compare_int_unlock.part.0>:
		atomic_or(&int_mask, BIT(chan));
    2210:	2301      	movs	r3, #1
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    2212:	4a12      	ldr	r2, [pc, #72]	; (225c <compare_int_unlock.part.0+0x4c>)
    2214:	f3bf 8f5b 	dmb	ish
    2218:	4083      	lsls	r3, r0
    221a:	e852 1f00 	ldrex	r1, [r2]
    221e:	4319      	orrs	r1, r3
    2220:	e842 1c00 	strex	ip, r1, [r2]
    2224:	f1bc 0f00 	cmp.w	ip, #0
    2228:	d1f7      	bne.n	221a <compare_int_unlock.part.0+0xa>
    222a:	f3bf 8f5b 	dmb	ish
    p_reg->INTENSET = mask;
    222e:	4a0c      	ldr	r2, [pc, #48]	; (2260 <compare_int_unlock.part.0+0x50>)
		nrf_rtc_int_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    2230:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    2234:	4083      	lsls	r3, r0
    2236:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
	return __atomic_load_n(target, __ATOMIC_SEQ_CST);
    223a:	4b0a      	ldr	r3, [pc, #40]	; (2264 <compare_int_unlock.part.0+0x54>)
    223c:	f3bf 8f5b 	dmb	ish
    2240:	681b      	ldr	r3, [r3, #0]
    2242:	f3bf 8f5b 	dmb	ish
		if (atomic_get(&force_isr_mask) & BIT(chan)) {
    2246:	fa23 f000 	lsr.w	r0, r3, r0
    224a:	07c3      	lsls	r3, r0, #31
    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    224c:	bf42      	ittt	mi
    224e:	4b06      	ldrmi	r3, [pc, #24]	; (2268 <compare_int_unlock.part.0+0x58>)
    2250:	f44f 3200 	movmi.w	r2, #131072	; 0x20000
    2254:	f8c3 2100 	strmi.w	r2, [r3, #256]	; 0x100
}
    2258:	4770      	bx	lr
    225a:	bf00      	nop
    225c:	20000270 	.word	0x20000270
    2260:	40011000 	.word	0x40011000
    2264:	2000026c 	.word	0x2000026c
    2268:	e000e100 	.word	0xe000e100

0000226c <z_nrf_rtc_timer_read>:
	uint64_t val = ((uint64_t)overflow_cnt) << COUNTER_BIT_WIDTH;
    226c:	4b0d      	ldr	r3, [pc, #52]	; (22a4 <z_nrf_rtc_timer_read+0x38>)
    226e:	681b      	ldr	r3, [r3, #0]
    2270:	0a19      	lsrs	r1, r3, #8
    2272:	0618      	lsls	r0, r3, #24
  __ASM volatile ("dmb 0xF":::"memory");
    2274:	f3bf 8f5f 	dmb	sy
     return p_reg->COUNTER;
    2278:	4b0b      	ldr	r3, [pc, #44]	; (22a8 <z_nrf_rtc_timer_read+0x3c>)
    227a:	f8d3 3504 	ldr.w	r3, [r3, #1284]	; 0x504
	val += cntr;
    227e:	18c0      	adds	r0, r0, r3
    2280:	f141 0100 	adc.w	r1, r1, #0
	if (cntr < OVERFLOW_RISK_RANGE_END) {
    2284:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
    2288:	d20a      	bcs.n	22a0 <z_nrf_rtc_timer_read+0x34>
		if (val < anchor) {
    228a:	4b08      	ldr	r3, [pc, #32]	; (22ac <z_nrf_rtc_timer_read+0x40>)
    228c:	e9d3 2300 	ldrd	r2, r3, [r3]
    2290:	4299      	cmp	r1, r3
    2292:	bf08      	it	eq
    2294:	4290      	cmpeq	r0, r2
    2296:	d203      	bcs.n	22a0 <z_nrf_rtc_timer_read+0x34>
			val += COUNTER_SPAN;
    2298:	f110 7080 	adds.w	r0, r0, #16777216	; 0x1000000
    229c:	f141 0100 	adc.w	r1, r1, #0
}
    22a0:	4770      	bx	lr
    22a2:	bf00      	nop
    22a4:	20000274 	.word	0x20000274
    22a8:	40011000 	.word	0x40011000
    22ac:	20000098 	.word	0x20000098

000022b0 <compare_set>:
{
    22b0:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    22b4:	b085      	sub	sp, #20
    22b6:	4616      	mov	r6, r2
    22b8:	461f      	mov	r7, r3
    22ba:	4605      	mov	r5, r0
	key = compare_int_lock(chan);
    22bc:	f7ff ff80 	bl	21c0 <compare_int_lock>
    22c0:	9001      	str	r0, [sp, #4]
	uint64_t curr_time = z_nrf_rtc_timer_read();
    22c2:	f7ff ffd3 	bl	226c <z_nrf_rtc_timer_read>
	if (curr_time < target_time) {
    22c6:	42b9      	cmp	r1, r7
    22c8:	bf08      	it	eq
    22ca:	42b0      	cmpeq	r0, r6
    22cc:	d27f      	bcs.n	23ce <compare_set+0x11e>
		if (target_time - curr_time > COUNTER_SPAN) {
    22ce:	ebb6 0800 	subs.w	r8, r6, r0
    22d2:	eb67 0901 	sbc.w	r9, r7, r1
    22d6:	2300      	movs	r3, #0
    22d8:	f04f 7280 	mov.w	r2, #16777216	; 0x1000000
    22dc:	454b      	cmp	r3, r9
    22de:	bf08      	it	eq
    22e0:	4542      	cmpeq	r2, r8
    22e2:	f0c0 8085 	bcc.w	23f0 <compare_set+0x140>
		if (target_time != cc_data[chan].target_time) {
    22e6:	4b44      	ldr	r3, [pc, #272]	; (23f8 <compare_set+0x148>)
    22e8:	eb03 1305 	add.w	r3, r3, r5, lsl #4
    22ec:	e9d3 2302 	ldrd	r2, r3, [r3, #8]
    22f0:	429f      	cmp	r7, r3
    22f2:	bf08      	it	eq
    22f4:	4296      	cmpeq	r6, r2
    22f6:	d054      	beq.n	23a2 <compare_set+0xf2>
    22f8:	ea4f 0985 	mov.w	r9, r5, lsl #2
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    22fc:	f44f 3b80 	mov.w	fp, #65536	; 0x10000
    2300:	f109 4980 	add.w	r9, r9, #1073741824	; 0x40000000
	nrf_rtc_event_clear(RTC, RTC_CHANNEL_EVENT_ADDR(chan));
    2304:	f105 0850 	add.w	r8, r5, #80	; 0x50
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    2308:	fa0b f205 	lsl.w	r2, fp, r5
    230c:	f509 3988 	add.w	r9, r9, #69632	; 0x11000
	nrf_rtc_event_clear(RTC, RTC_CHANNEL_EVENT_ADDR(chan));
    2310:	ea4f 0888 	mov.w	r8, r8, lsl #2
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    2314:	fa1f f888 	uxth.w	r8, r8
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    2318:	9202      	str	r2, [sp, #8]
     return p_reg->COUNTER;
    231a:	4a38      	ldr	r2, [pc, #224]	; (23fc <compare_set+0x14c>)
    return p_reg->CC[ch];
    231c:	f8d9 0540 	ldr.w	r0, [r9, #1344]	; 0x540
	return absolute_time & COUNTER_MAX;
    2320:	f026 437f 	bic.w	r3, r6, #4278190080	; 0xff000000
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    2324:	f108 4880 	add.w	r8, r8, #1073741824	; 0x40000000
    2328:	f508 3888 	add.w	r8, r8, #69632	; 0x11000
	uint32_t cc_val = abs_val & COUNTER_MAX;
    232c:	461c      	mov	r4, r3
    232e:	4693      	mov	fp, r2
     return p_reg->COUNTER;
    2330:	f8d2 a504 	ldr.w	sl, [r2, #1284]	; 0x504
	return (a - b) & COUNTER_MAX;
    2334:	eba0 000a 	sub.w	r0, r0, sl
    2338:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
	nrf_rtc_cc_set(RTC, chan, cyc & COUNTER_MAX);
    233c:	f02a 417f 	bic.w	r1, sl, #4278190080	; 0xff000000
		if (counter_sub(prev_cc, now) == 1) {
    2340:	2801      	cmp	r0, #1
    p_reg->CC[ch] = cc_val;
    2342:	f8c9 1540 	str.w	r1, [r9, #1344]	; 0x540
    2346:	d105      	bne.n	2354 <compare_set+0xa4>
    2348:	9303      	str	r3, [sp, #12]
	z_impl_k_busy_wait(usec_to_wait);
    234a:	2013      	movs	r0, #19
    234c:	f002 fc36 	bl	4bbc <z_impl_k_busy_wait>
    2350:	4a2a      	ldr	r2, [pc, #168]	; (23fc <compare_set+0x14c>)
    2352:	9b03      	ldr	r3, [sp, #12]
    p_reg->EVTENSET = mask;
    2354:	9902      	ldr	r1, [sp, #8]
		if (counter_sub(cc_val, now + 2) > COUNTER_HALF_SPAN) {
    2356:	f10a 0c02 	add.w	ip, sl, #2
	return (a - b) & COUNTER_MAX;
    235a:	eba4 000c 	sub.w	r0, r4, ip
    235e:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
			cc_val = now + 2;
    2362:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    2366:	bf88      	it	hi
    2368:	4664      	movhi	r4, ip
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    236a:	2000      	movs	r0, #0
    236c:	f8c8 0000 	str.w	r0, [r8]
    2370:	f8d8 0000 	ldr.w	r0, [r8]
    p_reg->EVTENSET = mask;
    2374:	f8cb 1344 	str.w	r1, [fp, #836]	; 0x344
	nrf_rtc_cc_set(RTC, chan, cyc & COUNTER_MAX);
    2378:	f024 407f 	bic.w	r0, r4, #4278190080	; 0xff000000
    p_reg->CC[ch] = cc_val;
    237c:	f8c9 0540 	str.w	r0, [r9, #1344]	; 0x540
     return p_reg->COUNTER;
    2380:	f8db 0504 	ldr.w	r0, [fp, #1284]	; 0x504
		 (counter_sub(cc_val, now2 + 2) > COUNTER_HALF_SPAN));
    2384:	4582      	cmp	sl, r0
    2386:	d006      	beq.n	2396 <compare_set+0xe6>
	return (a - b) & COUNTER_MAX;
    2388:	1a20      	subs	r0, r4, r0
    238a:	3802      	subs	r0, #2
    238c:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
	} while ((now2 != now) &&
    2390:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    2394:	d819      	bhi.n	23ca <compare_set+0x11a>
	return (a - b) & COUNTER_MAX;
    2396:	1ae4      	subs	r4, r4, r3
    2398:	f024 447f 	bic.w	r4, r4, #4278190080	; 0xff000000
			target_time += counter_sub(cc_set, cc_value);
    239c:	1932      	adds	r2, r6, r4
    239e:	f147 0300 	adc.w	r3, r7, #0
	cc_data[chan].target_time = target_time;
    23a2:	4c15      	ldr	r4, [pc, #84]	; (23f8 <compare_set+0x148>)
    23a4:	0129      	lsls	r1, r5, #4
    23a6:	eb04 1005 	add.w	r0, r4, r5, lsl #4
    23aa:	e9c0 2302 	strd	r2, r3, [r0, #8]
	cc_data[chan].callback = handler;
    23ae:	9a0e      	ldr	r2, [sp, #56]	; 0x38
	cc_data[chan].user_context = user_data;
    23b0:	9b0f      	ldr	r3, [sp, #60]	; 0x3c
	cc_data[chan].callback = handler;
    23b2:	5062      	str	r2, [r4, r1]
	cc_data[chan].user_context = user_data;
    23b4:	6043      	str	r3, [r0, #4]
	return ret;
    23b6:	2400      	movs	r4, #0
	if (key) {
    23b8:	9b01      	ldr	r3, [sp, #4]
    23ba:	b113      	cbz	r3, 23c2 <compare_set+0x112>
    23bc:	4628      	mov	r0, r5
    23be:	f7ff ff27 	bl	2210 <compare_int_unlock.part.0>
}
    23c2:	4620      	mov	r0, r4
    23c4:	b005      	add	sp, #20
    23c6:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    23ca:	4620      	mov	r0, r4
    23cc:	e7b0      	b.n	2330 <compare_set+0x80>
		atomic_or(&force_isr_mask, BIT(chan));
    23ce:	2301      	movs	r3, #1
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    23d0:	4a0b      	ldr	r2, [pc, #44]	; (2400 <compare_set+0x150>)
    23d2:	f3bf 8f5b 	dmb	ish
    23d6:	40ab      	lsls	r3, r5
    23d8:	e852 1f00 	ldrex	r1, [r2]
    23dc:	4319      	orrs	r1, r3
    23de:	e842 1000 	strex	r0, r1, [r2]
    23e2:	2800      	cmp	r0, #0
    23e4:	d1f8      	bne.n	23d8 <compare_set+0x128>
    23e6:	f3bf 8f5b 	dmb	ish
    23ea:	4632      	mov	r2, r6
    23ec:	463b      	mov	r3, r7
    23ee:	e7d8      	b.n	23a2 <compare_set+0xf2>
			return -EINVAL;
    23f0:	f06f 0415 	mvn.w	r4, #21
    23f4:	e7e0      	b.n	23b8 <compare_set+0x108>
    23f6:	bf00      	nop
    23f8:	200000a0 	.word	0x200000a0
    23fc:	40011000 	.word	0x40011000
    2400:	2000026c 	.word	0x2000026c

00002404 <sys_clock_driver_init>:
{
	return (uint32_t)z_nrf_rtc_timer_read();
}

static int sys_clock_driver_init(const struct device *dev)
{
    2404:	b573      	push	{r0, r1, r4, r5, r6, lr}
			CLOCK_CONTROL_NRF_LF_START_STABLE);

	/* TODO: replace with counter driver to access RTC */
	nrf_rtc_prescaler_set(RTC, 0);
	for (int32_t chan = 0; chan < CHAN_COUNT; chan++) {
		cc_data[chan].target_time = TARGET_TIME_INVALID;
    2406:	4b19      	ldr	r3, [pc, #100]	; (246c <sys_clock_driver_init+0x68>)
    p_reg->PRESCALER = val;
    2408:	4d19      	ldr	r5, [pc, #100]	; (2470 <sys_clock_driver_init+0x6c>)
    240a:	2400      	movs	r4, #0
    240c:	f04f 30ff 	mov.w	r0, #4294967295
    2410:	f04f 31ff 	mov.w	r1, #4294967295
    2414:	f8c5 4508 	str.w	r4, [r5, #1288]	; 0x508
    2418:	e9c3 0102 	strd	r0, r1, [r3, #8]
    p_reg->INTENSET = mask;
    241c:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    2420:	f8c5 3304 	str.w	r3, [r5, #772]	; 0x304
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    2424:	4b13      	ldr	r3, [pc, #76]	; (2474 <sys_clock_driver_init+0x70>)
    2426:	2602      	movs	r6, #2
    2428:	f44f 3200 	mov.w	r2, #131072	; 0x20000

	nrf_rtc_int_enable(RTC, NRF_RTC_INT_OVERFLOW_MASK);

	NVIC_ClearPendingIRQ(RTC_IRQn);

	IRQ_CONNECT(RTC_IRQn, DT_IRQ(DT_NODELABEL(RTC_LABEL), priority),
    242c:	2101      	movs	r1, #1
    242e:	f8c5 6304 	str.w	r6, [r5, #772]	; 0x304
    2432:	2011      	movs	r0, #17
    2434:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
    2438:	4622      	mov	r2, r4
    243a:	f7fe fddf 	bl	ffc <z_arm_irq_priority_set>
		    rtc_nrf_isr, 0, 0);
	irq_enable(RTC_IRQn);
    243e:	2011      	movs	r0, #17
    2440:	f7fe fdbe 	bl	fc0 <arch_irq_enable>
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    2444:	4a0c      	ldr	r2, [pc, #48]	; (2478 <sys_clock_driver_init+0x74>)
    2446:	2301      	movs	r3, #1
    2448:	6013      	str	r3, [r2, #0]

	nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_CLEAR);
	nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_START);

	int_mask = BIT_MASK(CHAN_COUNT);
    244a:	4a0c      	ldr	r2, [pc, #48]	; (247c <sys_clock_driver_init+0x78>)
    244c:	602b      	str	r3, [r5, #0]
    244e:	6013      	str	r3, [r2, #0]

	uint32_t initial_timeout = IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
		(COUNTER_HALF_SPAN - 1) :
		(counter() + CYC_PER_TICK);

	compare_set(0, initial_timeout, sys_clock_timeout_handler, NULL);
    2450:	4b0b      	ldr	r3, [pc, #44]	; (2480 <sys_clock_driver_init+0x7c>)
    2452:	4a0c      	ldr	r2, [pc, #48]	; (2484 <sys_clock_driver_init+0x80>)
    2454:	9300      	str	r3, [sp, #0]
    2456:	9401      	str	r4, [sp, #4]
    2458:	2300      	movs	r3, #0
    245a:	4620      	mov	r0, r4
    245c:	f7ff ff28 	bl	22b0 <compare_set>

	z_nrf_clock_control_lf_on(mode);
    2460:	4630      	mov	r0, r6
    2462:	f7ff fa6d 	bl	1940 <z_nrf_clock_control_lf_on>

	return 0;
}
    2466:	4620      	mov	r0, r4
    2468:	b002      	add	sp, #8
    246a:	bd70      	pop	{r4, r5, r6, pc}
    246c:	200000a0 	.word	0x200000a0
    2470:	40011000 	.word	0x40011000
    2474:	e000e100 	.word	0xe000e100
    2478:	40011008 	.word	0x40011008
    247c:	20000270 	.word	0x20000270
    2480:	00002149 	.word	0x00002149
    2484:	007fffff 	.word	0x007fffff

00002488 <rtc_nrf_isr>:
{
    2488:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    return p_reg->INTENSET & mask;
    248c:	4c34      	ldr	r4, [pc, #208]	; (2560 <rtc_nrf_isr+0xd8>)
    248e:	f8d4 3304 	ldr.w	r3, [r4, #772]	; 0x304
	if (nrf_rtc_int_enable_check(RTC, NRF_RTC_INT_OVERFLOW_MASK) &&
    2492:	079a      	lsls	r2, r3, #30
    2494:	d509      	bpl.n	24aa <rtc_nrf_isr+0x22>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    2496:	4b33      	ldr	r3, [pc, #204]	; (2564 <rtc_nrf_isr+0xdc>)
    2498:	681a      	ldr	r2, [r3, #0]
    249a:	b132      	cbz	r2, 24aa <rtc_nrf_isr+0x22>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    249c:	2200      	movs	r2, #0
    249e:	601a      	str	r2, [r3, #0]
		overflow_cnt++;
    24a0:	4a31      	ldr	r2, [pc, #196]	; (2568 <rtc_nrf_isr+0xe0>)
    24a2:	681b      	ldr	r3, [r3, #0]
    24a4:	6813      	ldr	r3, [r2, #0]
    24a6:	3301      	adds	r3, #1
    24a8:	6013      	str	r3, [r2, #0]
	__asm__ volatile(
    24aa:	f04f 0320 	mov.w	r3, #32
    24ae:	f3ef 8211 	mrs	r2, BASEPRI
    24b2:	f383 8812 	msr	BASEPRI_MAX, r3
    24b6:	f3bf 8f6f 	isb	sy
    return p_reg->INTENSET & mask;
    24ba:	f8d4 3304 	ldr.w	r3, [r4, #772]	; 0x304
	if (nrf_rtc_int_enable_check(RTC, RTC_CHANNEL_INT_MASK(chan))) {
    24be:	03db      	lsls	r3, r3, #15
    24c0:	d512      	bpl.n	24e8 <rtc_nrf_isr+0x60>
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    24c2:	f3bf 8f5b 	dmb	ish
    24c6:	4b29      	ldr	r3, [pc, #164]	; (256c <rtc_nrf_isr+0xe4>)
    24c8:	e853 1f00 	ldrex	r1, [r3]
    24cc:	f021 0001 	bic.w	r0, r1, #1
    24d0:	e843 0600 	strex	r6, r0, [r3]
    24d4:	2e00      	cmp	r6, #0
    24d6:	d1f7      	bne.n	24c8 <rtc_nrf_isr+0x40>
    24d8:	f3bf 8f5b 	dmb	ish
    24dc:	4b24      	ldr	r3, [pc, #144]	; (2570 <rtc_nrf_isr+0xe8>)
		result = atomic_and(&force_isr_mask, ~BIT(chan)) ||
    24de:	2900      	cmp	r1, #0
    24e0:	d136      	bne.n	2550 <rtc_nrf_isr+0xc8>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    24e2:	6819      	ldr	r1, [r3, #0]
		if (result) {
    24e4:	2900      	cmp	r1, #0
    24e6:	d133      	bne.n	2550 <rtc_nrf_isr+0xc8>
{
    24e8:	2300      	movs	r3, #0
	__asm__ volatile(
    24ea:	f382 8811 	msr	BASEPRI, r2
    24ee:	f3bf 8f6f 	isb	sy
	if (channel_processing_check_and_clear(chan)) {
    24f2:	b353      	cbz	r3, 254a <rtc_nrf_isr+0xc2>
		curr_time = z_nrf_rtc_timer_read();
    24f4:	f7ff feba 	bl	226c <z_nrf_rtc_timer_read>
    24f8:	4606      	mov	r6, r0
	__asm__ volatile(
    24fa:	f04f 0320 	mov.w	r3, #32
    24fe:	f3ef 8011 	mrs	r0, BASEPRI
    2502:	f383 8812 	msr	BASEPRI_MAX, r3
    2506:	f3bf 8f6f 	isb	sy
		expire_time = cc_data[chan].target_time;
    250a:	4b1a      	ldr	r3, [pc, #104]	; (2574 <rtc_nrf_isr+0xec>)
    250c:	e9d3 8902 	ldrd	r8, r9, [r3, #8]
		if (curr_time >= expire_time) {
    2510:	4549      	cmp	r1, r9
    2512:	bf08      	it	eq
    2514:	4546      	cmpeq	r6, r8
    2516:	f04f 0200 	mov.w	r2, #0
    251a:	d31e      	bcc.n	255a <rtc_nrf_isr+0xd2>
			cc_data[chan].target_time = TARGET_TIME_INVALID;
    251c:	f04f 36ff 	mov.w	r6, #4294967295
    2520:	f04f 37ff 	mov.w	r7, #4294967295
			user_context = cc_data[chan].user_context;
    2524:	e9d3 1500 	ldrd	r1, r5, [r3]
			cc_data[chan].target_time = TARGET_TIME_INVALID;
    2528:	e9c3 6702 	strd	r6, r7, [r3, #8]
			cc_data[chan].callback = NULL;
    252c:	601a      	str	r2, [r3, #0]
}

NRF_STATIC_INLINE void nrf_rtc_event_disable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->EVTENCLR = mask;
    252e:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    2532:	f8c4 3348 	str.w	r3, [r4, #840]	; 0x348
	__asm__ volatile(
    2536:	f380 8811 	msr	BASEPRI, r0
    253a:	f3bf 8f6f 	isb	sy
		if (handler) {
    253e:	b121      	cbz	r1, 254a <rtc_nrf_isr+0xc2>
			handler(chan, expire_time, user_context);
    2540:	9500      	str	r5, [sp, #0]
    2542:	4642      	mov	r2, r8
    2544:	464b      	mov	r3, r9
    2546:	2000      	movs	r0, #0
    2548:	4788      	blx	r1
}
    254a:	b003      	add	sp, #12
    254c:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    2550:	2100      	movs	r1, #0
    2552:	6019      	str	r1, [r3, #0]
    2554:	681b      	ldr	r3, [r3, #0]
		result = atomic_and(&force_isr_mask, ~BIT(chan)) ||
    2556:	2301      	movs	r3, #1
}
    2558:	e7c7      	b.n	24ea <rtc_nrf_isr+0x62>
		z_nrf_rtc_timer_compare_handler_t handler = NULL;
    255a:	4611      	mov	r1, r2
    255c:	e7eb      	b.n	2536 <rtc_nrf_isr+0xae>
    255e:	bf00      	nop
    2560:	40011000 	.word	0x40011000
    2564:	40011104 	.word	0x40011104
    2568:	20000274 	.word	0x20000274
    256c:	2000026c 	.word	0x2000026c
    2570:	40011140 	.word	0x40011140
    2574:	200000a0 	.word	0x200000a0

00002578 <sys_clock_set_timeout>:
	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    2578:	4b14      	ldr	r3, [pc, #80]	; (25cc <sys_clock_set_timeout+0x54>)
{
    257a:	b513      	push	{r0, r1, r4, lr}
	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    257c:	f1b0 3fff 	cmp.w	r0, #4294967295
    2580:	bf08      	it	eq
    2582:	4618      	moveq	r0, r3
	ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
    2584:	1e44      	subs	r4, r0, #1
    2586:	2c00      	cmp	r4, #0
    2588:	dd1e      	ble.n	25c8 <sys_clock_set_timeout+0x50>
    258a:	429c      	cmp	r4, r3
    258c:	bfa8      	it	ge
    258e:	461c      	movge	r4, r3
	uint32_t unannounced = z_nrf_rtc_timer_read() - last_count;
    2590:	f7ff fe6c 	bl	226c <z_nrf_rtc_timer_read>
    2594:	4b0e      	ldr	r3, [pc, #56]	; (25d0 <sys_clock_set_timeout+0x58>)
	compare_set(0, target_time, sys_clock_timeout_handler, NULL);
    2596:	490f      	ldr	r1, [pc, #60]	; (25d4 <sys_clock_set_timeout+0x5c>)
	uint32_t unannounced = z_nrf_rtc_timer_read() - last_count;
    2598:	e9d3 2300 	ldrd	r2, r3, [r3]
    259c:	1a80      	subs	r0, r0, r2
		ticks = 0;
    259e:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    25a2:	bf28      	it	cs
    25a4:	2400      	movcs	r4, #0
	cyc = ticks * CYC_PER_TICK + 1 + unannounced;
    25a6:	3001      	adds	r0, #1
    25a8:	4404      	add	r4, r0
	uint64_t target_time = cyc + last_count;
    25aa:	4808      	ldr	r0, [pc, #32]	; (25cc <sys_clock_set_timeout+0x54>)
	compare_set(0, target_time, sys_clock_timeout_handler, NULL);
    25ac:	9100      	str	r1, [sp, #0]
	uint64_t target_time = cyc + last_count;
    25ae:	4284      	cmp	r4, r0
    25b0:	bf28      	it	cs
    25b2:	4604      	movcs	r4, r0
	compare_set(0, target_time, sys_clock_timeout_handler, NULL);
    25b4:	1912      	adds	r2, r2, r4
    25b6:	f04f 0000 	mov.w	r0, #0
    25ba:	9001      	str	r0, [sp, #4]
    25bc:	f143 0300 	adc.w	r3, r3, #0
    25c0:	f7ff fe76 	bl	22b0 <compare_set>
}
    25c4:	b002      	add	sp, #8
    25c6:	bd10      	pop	{r4, pc}
	ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
    25c8:	2400      	movs	r4, #0
    25ca:	e7e1      	b.n	2590 <sys_clock_set_timeout+0x18>
    25cc:	007fffff 	.word	0x007fffff
    25d0:	200000b0 	.word	0x200000b0
    25d4:	00002149 	.word	0x00002149

000025d8 <sys_clock_elapsed>:
{
    25d8:	b508      	push	{r3, lr}
	return (z_nrf_rtc_timer_read() - last_count) / CYC_PER_TICK;
    25da:	f7ff fe47 	bl	226c <z_nrf_rtc_timer_read>
    25de:	4b02      	ldr	r3, [pc, #8]	; (25e8 <sys_clock_elapsed+0x10>)
    25e0:	681b      	ldr	r3, [r3, #0]
}
    25e2:	1ac0      	subs	r0, r0, r3
    25e4:	bd08      	pop	{r3, pc}
    25e6:	bf00      	nop
    25e8:	200000b0 	.word	0x200000b0

000025ec <nrf52_errata_108>:
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            uint32_t var1;
            uint32_t var2;

            if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF)
    25ec:	4b04      	ldr	r3, [pc, #16]	; (2600 <nrf52_errata_108+0x14>)
    25ee:	6818      	ldr	r0, [r3, #0]
    25f0:	1c42      	adds	r2, r0, #1
            {
                var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
    25f2:	bf04      	itt	eq
    25f4:	4b03      	ldreq	r3, [pc, #12]	; (2604 <nrf52_errata_108+0x18>)
    25f6:	7818      	ldrbeq	r0, [r3, #0]
                }
            }
        #endif
        return false;
    #endif
}
    25f8:	1f83      	subs	r3, r0, #6
    25fa:	4258      	negs	r0, r3
    25fc:	4158      	adcs	r0, r3
    25fe:	4770      	bx	lr
    2600:	10000130 	.word	0x10000130
    2604:	f0000fe0 	.word	0xf0000fe0

00002608 <nrf52_errata_16>:
    #ifndef NRF52_SERIES
        return false;
    #else
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
    2608:	4b07      	ldr	r3, [pc, #28]	; (2628 <nrf52_errata_16+0x20>)
    260a:	781b      	ldrb	r3, [r3, #0]
            uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
        #endif
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            if (var1 == 0x06)
    260c:	2b06      	cmp	r3, #6
    260e:	d109      	bne.n	2624 <nrf52_errata_16+0x1c>
            uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
    2610:	4b06      	ldr	r3, [pc, #24]	; (262c <nrf52_errata_16+0x24>)
    2612:	681b      	ldr	r3, [r3, #0]
    2614:	f3c3 1303 	ubfx	r3, r3, #4, #4
    2618:	3b03      	subs	r3, #3
    261a:	2b04      	cmp	r3, #4
    261c:	d802      	bhi.n	2624 <nrf52_errata_16+0x1c>
    261e:	4a04      	ldr	r2, [pc, #16]	; (2630 <nrf52_errata_16+0x28>)
    2620:	5cd0      	ldrb	r0, [r2, r3]
    2622:	4770      	bx	lr
                    default:
                        return false;
                }
            }
        #endif
        return false;
    2624:	2000      	movs	r0, #0
    #endif
}
    2626:	4770      	bx	lr
    2628:	f0000fe0 	.word	0xf0000fe0
    262c:	f0000fe8 	.word	0xf0000fe8
    2630:	00004f34 	.word	0x00004f34

00002634 <nvmc_wait>:

/* -- NVMC utility functions -- */
/* Waits until NVMC is done with the current pending action */
void nvmc_wait(void)
{
    while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
    2634:	4a02      	ldr	r2, [pc, #8]	; (2640 <nvmc_wait+0xc>)
    2636:	f8d2 3400 	ldr.w	r3, [r2, #1024]	; 0x400
    263a:	2b00      	cmp	r3, #0
    263c:	d0fb      	beq.n	2636 <nvmc_wait+0x2>
}
    263e:	4770      	bx	lr
    2640:	4001e000 	.word	0x4001e000

00002644 <SystemInit>:
{
    SystemCoreClock = __SYSTEM_CLOCK_64M;
}

void SystemInit(void)
{
    2644:	b510      	push	{r4, lr}
    #endif

    #if NRF52_ERRATA_12_ENABLE_WORKAROUND
        /* Workaround for Errata 12 "COMP: Reference ladder not correctly calibrated" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp */
        if (nrf52_errata_12()){
    2646:	f7ff ffd1 	bl	25ec <nrf52_errata_108>
    264a:	b128      	cbz	r0, 2658 <SystemInit+0x14>
            *(volatile uint32_t *)0x40013540 = (*(uint32_t *)0x10000324 & 0x00001F00) >> 8;
    264c:	4b81      	ldr	r3, [pc, #516]	; (2854 <SystemInit+0x210>)
    264e:	4a82      	ldr	r2, [pc, #520]	; (2858 <SystemInit+0x214>)
    2650:	681b      	ldr	r3, [r3, #0]
    2652:	f3c3 2304 	ubfx	r3, r3, #8, #5
    2656:	6013      	str	r3, [r2, #0]
    #endif

    #if NRF52_ERRATA_16_ENABLE_WORKAROUND
        /* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp */
        if (nrf52_errata_16()){
    2658:	f7ff ffd6 	bl	2608 <nrf52_errata_16>
    265c:	b110      	cbz	r0, 2664 <SystemInit+0x20>
            *(volatile uint32_t *)0x4007C074 = 3131961357ul;
    265e:	4b7f      	ldr	r3, [pc, #508]	; (285c <SystemInit+0x218>)
    2660:	4a7f      	ldr	r2, [pc, #508]	; (2860 <SystemInit+0x21c>)
    2662:	601a      	str	r2, [r3, #0]
    #endif

    #if NRF52_ERRATA_31_ENABLE_WORKAROUND
        /* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp */
        if (nrf52_errata_31()){
    2664:	f7ff ffc2 	bl	25ec <nrf52_errata_108>
    2668:	b128      	cbz	r0, 2676 <SystemInit+0x32>
            *(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13;
    266a:	4b7e      	ldr	r3, [pc, #504]	; (2864 <SystemInit+0x220>)
    266c:	4a7e      	ldr	r2, [pc, #504]	; (2868 <SystemInit+0x224>)
    266e:	681b      	ldr	r3, [r3, #0]
    2670:	f3c3 3342 	ubfx	r3, r3, #13, #3
    2674:	6013      	str	r3, [r2, #0]
    #endif

    #if NRF52_ERRATA_32_ENABLE_WORKAROUND
        /* Workaround for Errata 32 "DIF: Debug session automatically enables TracePort pins" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp */
        if (nrf52_errata_32()){
    2676:	f7ff ffc7 	bl	2608 <nrf52_errata_16>
    267a:	b120      	cbz	r0, 2686 <SystemInit+0x42>
            CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk;
    267c:	4a7b      	ldr	r2, [pc, #492]	; (286c <SystemInit+0x228>)
    267e:	68d3      	ldr	r3, [r2, #12]
    2680:	f023 7380 	bic.w	r3, r3, #16777216	; 0x1000000
    2684:	60d3      	str	r3, [r2, #12]
    #endif

    #if NRF52_ERRATA_36_ENABLE_WORKAROUND
        /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_36()){
    2686:	f7ff ffb1 	bl	25ec <nrf52_errata_108>
    268a:	b140      	cbz	r0, 269e <SystemInit+0x5a>
            NRF_CLOCK->EVENTS_DONE = 0;
    268c:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2690:	2200      	movs	r2, #0
    2692:	f8c3 210c 	str.w	r2, [r3, #268]	; 0x10c
            NRF_CLOCK->EVENTS_CTTO = 0;
    2696:	f8c3 2110 	str.w	r2, [r3, #272]	; 0x110
            NRF_CLOCK->CTIV = 0;
    269a:	f8c3 2538 	str.w	r2, [r3, #1336]	; 0x538
    #endif

    #if NRF52_ERRATA_37_ENABLE_WORKAROUND
        /* Workaround for Errata 37 "RADIO: Encryption engine is slow by default" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_37()){
    269e:	f7ff ffb3 	bl	2608 <nrf52_errata_16>
    26a2:	b110      	cbz	r0, 26aa <SystemInit+0x66>
            *(volatile uint32_t *)0x400005A0 = 0x3;
    26a4:	4b72      	ldr	r3, [pc, #456]	; (2870 <SystemInit+0x22c>)
    26a6:	2203      	movs	r2, #3
    26a8:	601a      	str	r2, [r3, #0]
    #endif

    #if NRF52_ERRATA_57_ENABLE_WORKAROUND
        /* Workaround for Errata 57 "NFCT: NFC Modulation amplitude" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_57()){
    26aa:	f7ff ffad 	bl	2608 <nrf52_errata_16>
    26ae:	b140      	cbz	r0, 26c2 <SystemInit+0x7e>
            *(volatile uint32_t *)0x40005610 = 0x00000005;
    26b0:	4b70      	ldr	r3, [pc, #448]	; (2874 <SystemInit+0x230>)
    26b2:	2205      	movs	r2, #5
    26b4:	601a      	str	r2, [r3, #0]
            *(volatile uint32_t *)0x40005688 = 0x00000001;
    26b6:	2201      	movs	r2, #1
    26b8:	679a      	str	r2, [r3, #120]	; 0x78
            *(volatile uint32_t *)0x40005618 = 0x00000000;
    26ba:	2200      	movs	r2, #0
    26bc:	609a      	str	r2, [r3, #8]
            *(volatile uint32_t *)0x40005614 = 0x0000003F;
    26be:	223f      	movs	r2, #63	; 0x3f
    26c0:	605a      	str	r2, [r3, #4]
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            uint32_t var1;
            uint32_t var2;

            if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF)
    26c2:	4b6d      	ldr	r3, [pc, #436]	; (2878 <SystemInit+0x234>)
    26c4:	681a      	ldr	r2, [r3, #0]
    26c6:	1c51      	adds	r1, r2, #1
            {
                var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
    26c8:	bf0b      	itete	eq
    26ca:	4b6c      	ldreq	r3, [pc, #432]	; (287c <SystemInit+0x238>)
                var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
            }
            else
            {
                var1 = *(uint32_t *)0x10000130ul;
                var2 = *(uint32_t *)0x10000134ul;
    26cc:	4b6c      	ldrne	r3, [pc, #432]	; (2880 <SystemInit+0x23c>)
                var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
    26ce:	781a      	ldrbeq	r2, [r3, #0]
                var2 = *(uint32_t *)0x10000134ul;
    26d0:	681b      	ldrne	r3, [r3, #0]
                var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
    26d2:	bf02      	ittt	eq
    26d4:	3308      	addeq	r3, #8
    26d6:	681b      	ldreq	r3, [r3, #0]
    26d8:	f3c3 1303 	ubfxeq	r3, r3, #4, #4
            uint32_t var1 = *(uint32_t *)0x10000130ul;
            uint32_t var2 = *(uint32_t *)0x10000134ul;
        #endif
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            if (var1 == 0x06)
    26dc:	2a06      	cmp	r2, #6
    26de:	d14d      	bne.n	277c <SystemInit+0x138>
            {
                switch(var2)
    26e0:	3b03      	subs	r3, #3
    26e2:	2b04      	cmp	r3, #4
    26e4:	d803      	bhi.n	26ee <SystemInit+0xaa>
    #endif

    #if NRF52_ERRATA_66_ENABLE_WORKAROUND
        /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_66()){
    26e6:	4a67      	ldr	r2, [pc, #412]	; (2884 <SystemInit+0x240>)
    26e8:	5cd3      	ldrb	r3, [r2, r3]
    26ea:	2b00      	cmp	r3, #0
    26ec:	d046      	beq.n	277c <SystemInit+0x138>
            NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
    26ee:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
    26f2:	4b65      	ldr	r3, [pc, #404]	; (2888 <SystemInit+0x244>)
    26f4:	f8d2 1404 	ldr.w	r1, [r2, #1028]	; 0x404
    26f8:	f8c3 1520 	str.w	r1, [r3, #1312]	; 0x520
            NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
    26fc:	f8d2 1408 	ldr.w	r1, [r2, #1032]	; 0x408
    2700:	f8c3 1524 	str.w	r1, [r3, #1316]	; 0x524
            NRF_TEMP->A2 = NRF_FICR->TEMP.A2;
    2704:	f8d2 140c 	ldr.w	r1, [r2, #1036]	; 0x40c
    2708:	f8c3 1528 	str.w	r1, [r3, #1320]	; 0x528
            NRF_TEMP->A3 = NRF_FICR->TEMP.A3;
    270c:	f8d2 1410 	ldr.w	r1, [r2, #1040]	; 0x410
    2710:	f8c3 152c 	str.w	r1, [r3, #1324]	; 0x52c
            NRF_TEMP->A4 = NRF_FICR->TEMP.A4;
    2714:	f8d2 1414 	ldr.w	r1, [r2, #1044]	; 0x414
    2718:	f8c3 1530 	str.w	r1, [r3, #1328]	; 0x530
            NRF_TEMP->A5 = NRF_FICR->TEMP.A5;
    271c:	f8d2 1418 	ldr.w	r1, [r2, #1048]	; 0x418
    2720:	f8c3 1534 	str.w	r1, [r3, #1332]	; 0x534
            NRF_TEMP->B0 = NRF_FICR->TEMP.B0;
    2724:	f8d2 141c 	ldr.w	r1, [r2, #1052]	; 0x41c
    2728:	f8c3 1540 	str.w	r1, [r3, #1344]	; 0x540
            NRF_TEMP->B1 = NRF_FICR->TEMP.B1;
    272c:	f8d2 1420 	ldr.w	r1, [r2, #1056]	; 0x420
    2730:	f8c3 1544 	str.w	r1, [r3, #1348]	; 0x544
            NRF_TEMP->B2 = NRF_FICR->TEMP.B2;
    2734:	f8d2 1424 	ldr.w	r1, [r2, #1060]	; 0x424
    2738:	f8c3 1548 	str.w	r1, [r3, #1352]	; 0x548
            NRF_TEMP->B3 = NRF_FICR->TEMP.B3;
    273c:	f8d2 1428 	ldr.w	r1, [r2, #1064]	; 0x428
    2740:	f8c3 154c 	str.w	r1, [r3, #1356]	; 0x54c
            NRF_TEMP->B4 = NRF_FICR->TEMP.B4;
    2744:	f8d2 142c 	ldr.w	r1, [r2, #1068]	; 0x42c
    2748:	f8c3 1550 	str.w	r1, [r3, #1360]	; 0x550
            NRF_TEMP->B5 = NRF_FICR->TEMP.B5;
    274c:	f8d2 1430 	ldr.w	r1, [r2, #1072]	; 0x430
    2750:	f8c3 1554 	str.w	r1, [r3, #1364]	; 0x554
            NRF_TEMP->T0 = NRF_FICR->TEMP.T0;
    2754:	f8d2 1434 	ldr.w	r1, [r2, #1076]	; 0x434
    2758:	f8c3 1560 	str.w	r1, [r3, #1376]	; 0x560
            NRF_TEMP->T1 = NRF_FICR->TEMP.T1;
    275c:	f8d2 1438 	ldr.w	r1, [r2, #1080]	; 0x438
    2760:	f8c3 1564 	str.w	r1, [r3, #1380]	; 0x564
            NRF_TEMP->T2 = NRF_FICR->TEMP.T2;
    2764:	f8d2 143c 	ldr.w	r1, [r2, #1084]	; 0x43c
    2768:	f8c3 1568 	str.w	r1, [r3, #1384]	; 0x568
            NRF_TEMP->T3 = NRF_FICR->TEMP.T3;
    276c:	f8d2 1440 	ldr.w	r1, [r2, #1088]	; 0x440
    2770:	f8c3 156c 	str.w	r1, [r3, #1388]	; 0x56c
            NRF_TEMP->T4 = NRF_FICR->TEMP.T4;
    2774:	f8d2 2444 	ldr.w	r2, [r2, #1092]	; 0x444
    2778:	f8c3 2570 	str.w	r2, [r3, #1392]	; 0x570
    #endif

    #if NRF52_ERRATA_108_ENABLE_WORKAROUND
        /* Workaround for Errata 108 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_108()){
    277c:	f7ff ff36 	bl	25ec <nrf52_errata_108>
    2780:	b128      	cbz	r0, 278e <SystemInit+0x14a>
            *(volatile uint32_t *)0x40000EE4ul = *(volatile uint32_t *)0x10000258ul & 0x0000004Ful;
    2782:	4b42      	ldr	r3, [pc, #264]	; (288c <SystemInit+0x248>)
    2784:	4a42      	ldr	r2, [pc, #264]	; (2890 <SystemInit+0x24c>)
    2786:	681b      	ldr	r3, [r3, #0]
    2788:	f003 034f 	and.w	r3, r3, #79	; 0x4f
    278c:	6013      	str	r3, [r2, #0]
    #endif

    #if NRF52_ERRATA_136_ENABLE_WORKAROUND
        /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_136()){
    278e:	f7ff ff2d 	bl	25ec <nrf52_errata_108>
    2792:	b148      	cbz	r0, 27a8 <SystemInit+0x164>
            if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){
    2794:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2798:	f8d3 2400 	ldr.w	r2, [r3, #1024]	; 0x400
    279c:	07d2      	lsls	r2, r2, #31
                NRF_POWER->RESETREAS =  ~POWER_RESETREAS_RESETPIN_Msk;
    279e:	bf44      	itt	mi
    27a0:	f06f 0201 	mvnmi.w	r2, #1
    27a4:	f8c3 2400 	strmi.w	r2, [r3, #1024]	; 0x400
    #ifndef NRF52_SERIES
        return false;
    #else
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    27a8:	4b33      	ldr	r3, [pc, #204]	; (2878 <SystemInit+0x234>)
            uint32_t var2 = *(uint32_t *)0x10000134ul;
        #endif
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            if (var1 == 0x06)
    27aa:	681b      	ldr	r3, [r3, #0]
    27ac:	2b06      	cmp	r3, #6
    27ae:	d120      	bne.n	27f2 <SystemInit+0x1ae>
            uint32_t var2 = *(uint32_t *)0x10000134ul;
    27b0:	4b33      	ldr	r3, [pc, #204]	; (2880 <SystemInit+0x23c>)
    27b2:	681b      	ldr	r3, [r3, #0]
    27b4:	3b03      	subs	r3, #3
    27b6:	2b04      	cmp	r3, #4
    27b8:	d802      	bhi.n	27c0 <SystemInit+0x17c>
    #endif

    #if NRF52_ERRATA_182_ENABLE_WORKAROUND
        /* Workaround for Errata 182 "RADIO: Fixes for anomalies #102, #106, and #107 do not take effect" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_182()){
    27ba:	4a36      	ldr	r2, [pc, #216]	; (2894 <SystemInit+0x250>)
    27bc:	5cd3      	ldrb	r3, [r2, r3]
    27be:	b143      	cbz	r3, 27d2 <SystemInit+0x18e>
            *(volatile uint32_t *) 0x4000173C |= (0x1 << 10);
    27c0:	4a35      	ldr	r2, [pc, #212]	; (2898 <SystemInit+0x254>)
    27c2:	6813      	ldr	r3, [r2, #0]
    27c4:	f443 6380 	orr.w	r3, r3, #1024	; 0x400
    27c8:	6013      	str	r3, [r2, #0]
         || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\
         || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\
         || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    27ca:	4b2b      	ldr	r3, [pc, #172]	; (2878 <SystemInit+0x234>)
            uint32_t var2 = *(uint32_t *)0x10000134ul;
        #endif
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            if (var1 == 0x06)
    27cc:	681b      	ldr	r3, [r3, #0]
    27ce:	2b06      	cmp	r3, #6
    27d0:	d10f      	bne.n	27f2 <SystemInit+0x1ae>
            uint32_t var2 = *(uint32_t *)0x10000134ul;
    27d2:	4b2b      	ldr	r3, [pc, #172]	; (2880 <SystemInit+0x23c>)
    27d4:	681b      	ldr	r3, [r3, #0]
    27d6:	3b03      	subs	r3, #3
    27d8:	2b04      	cmp	r3, #4
    27da:	d802      	bhi.n	27e2 <SystemInit+0x19e>
            {
                /* Prevent processor from unlocking APPROTECT soft branch after this point. */
                NRF_APPROTECT->FORCEPROTECT = APPROTECT_FORCEPROTECT_FORCEPROTECT_Force;
            }
        #else
            if (nrf52_configuration_249())
    27dc:	4a2f      	ldr	r2, [pc, #188]	; (289c <SystemInit+0x258>)
    27de:	5cd3      	ldrb	r3, [r2, r3]
    27e0:	b13b      	cbz	r3, 27f2 <SystemInit+0x1ae>
            {
                /* Load APPROTECT soft branch from UICR.
                   If UICR->APPROTECT is disabled, POWER->APPROTECT will be disabled. */
                NRF_APPROTECT->DISABLE = NRF_UICR->APPROTECT;
    27e2:	f04f 2310 	mov.w	r3, #268439552	; 0x10001000
    27e6:	f8d3 2208 	ldr.w	r2, [r3, #520]	; 0x208
    27ea:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    27ee:	f8c3 2558 	str.w	r2, [r3, #1368]	; 0x558

    /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
      defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
      reserved for PinReset and not available as normal GPIO. */
    #if defined (CONFIG_GPIO_AS_PINRESET)
        if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
    27f2:	f04f 2310 	mov.w	r3, #268439552	; 0x10001000
    27f6:	f8d3 2200 	ldr.w	r2, [r3, #512]	; 0x200
    27fa:	2a00      	cmp	r2, #0
    27fc:	db03      	blt.n	2806 <SystemInit+0x1c2>
            ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
    27fe:	f8d3 3204 	ldr.w	r3, [r3, #516]	; 0x204
        if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
    2802:	2b00      	cmp	r3, #0
    2804:	da22      	bge.n	284c <SystemInit+0x208>
    NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
    2806:	4926      	ldr	r1, [pc, #152]	; (28a0 <SystemInit+0x25c>)
    2808:	2301      	movs	r3, #1
    280a:	f8c1 3504 	str.w	r3, [r1, #1284]	; 0x504
    nvmc_wait();
    280e:	f7ff ff11 	bl	2634 <nvmc_wait>
            nvmc_config(NVMC_CONFIG_WEN_Wen);
            NRF_UICR->PSELRESET[0] = RESET_PIN;
    2812:	f04f 2010 	mov.w	r0, #268439552	; 0x10001000
    2816:	2415      	movs	r4, #21
    2818:	f8c0 4200 	str.w	r4, [r0, #512]	; 0x200
            nvmc_wait();
    281c:	f7ff ff0a 	bl	2634 <nvmc_wait>
            NRF_UICR->PSELRESET[1] = RESET_PIN;
    2820:	f8c0 4204 	str.w	r4, [r0, #516]	; 0x204
            nvmc_wait();
    2824:	f7ff ff06 	bl	2634 <nvmc_wait>
    NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
    2828:	2300      	movs	r3, #0
    282a:	f8c1 3504 	str.w	r3, [r1, #1284]	; 0x504
    nvmc_wait();
    282e:	f7ff ff01 	bl	2634 <nvmc_wait>
  __ASM volatile ("dsb 0xF":::"memory");
    2832:	f3bf 8f4f 	dsb	sy
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    2836:	491b      	ldr	r1, [pc, #108]	; (28a4 <SystemInit+0x260>)
    2838:	4b1b      	ldr	r3, [pc, #108]	; (28a8 <SystemInit+0x264>)
    283a:	68ca      	ldr	r2, [r1, #12]
    283c:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    2840:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    2842:	60cb      	str	r3, [r1, #12]
    2844:	f3bf 8f4f 	dsb	sy
    __NOP();
    2848:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    284a:	e7fd      	b.n	2848 <SystemInit+0x204>
    SystemCoreClock = __SYSTEM_CLOCK_64M;
    284c:	4b17      	ldr	r3, [pc, #92]	; (28ac <SystemInit+0x268>)
    284e:	4a18      	ldr	r2, [pc, #96]	; (28b0 <SystemInit+0x26c>)
    2850:	601a      	str	r2, [r3, #0]
            NVIC_SystemReset();
        }
    #endif

    SystemCoreClockUpdate();
}
    2852:	bd10      	pop	{r4, pc}
    2854:	10000324 	.word	0x10000324
    2858:	40013540 	.word	0x40013540
    285c:	4007c074 	.word	0x4007c074
    2860:	baadf00d 	.word	0xbaadf00d
    2864:	10000244 	.word	0x10000244
    2868:	4000053c 	.word	0x4000053c
    286c:	e000edf0 	.word	0xe000edf0
    2870:	400005a0 	.word	0x400005a0
    2874:	40005610 	.word	0x40005610
    2878:	10000130 	.word	0x10000130
    287c:	f0000fe0 	.word	0xf0000fe0
    2880:	10000134 	.word	0x10000134
    2884:	00004f25 	.word	0x00004f25
    2888:	4000c000 	.word	0x4000c000
    288c:	10000258 	.word	0x10000258
    2890:	40000ee4 	.word	0x40000ee4
    2894:	00004f2a 	.word	0x00004f2a
    2898:	4000173c 	.word	0x4000173c
    289c:	00004f2f 	.word	0x00004f2f
    28a0:	4001e000 	.word	0x4001e000
    28a4:	e000ed00 	.word	0xe000ed00
    28a8:	05fa0004 	.word	0x05fa0004
    28ac:	2000001c 	.word	0x2000001c
    28b0:	03d09000 	.word	0x03d09000

000028b4 <nrfx_flag32_alloc>:
{
    return (mask & NRFX_BIT(bitpos)) ? false : true;
}

nrfx_err_t nrfx_flag32_alloc(nrfx_atomic_t * p_mask, uint8_t *p_flag)
{
    28b4:	b570      	push	{r4, r5, r6, lr}
        idx = 31 - NRF_CLZ(prev_mask);
        if (idx < 0) {
            return NRFX_ERROR_NO_MEM;
        }

        new_mask = prev_mask & ~NRFX_BIT(idx);
    28b6:	2501      	movs	r5, #1
        prev_mask = *p_mask;
    28b8:	6803      	ldr	r3, [r0, #0]
        idx = 31 - NRF_CLZ(prev_mask);
    28ba:	fab3 f283 	clz	r2, r3
        if (idx < 0) {
    28be:	2a20      	cmp	r2, #32
        idx = 31 - NRF_CLZ(prev_mask);
    28c0:	f1c2 041f 	rsb	r4, r2, #31
        if (idx < 0) {
    28c4:	d014      	beq.n	28f0 <nrfx_flag32_alloc+0x3c>
	return __atomic_compare_exchange_n(target, &old_value, new_value,
    28c6:	f3bf 8f5b 	dmb	ish
        new_mask = prev_mask & ~NRFX_BIT(idx);
    28ca:	fa05 f204 	lsl.w	r2, r5, r4
    28ce:	ea23 0202 	bic.w	r2, r3, r2
    28d2:	e850 6f00 	ldrex	r6, [r0]
    28d6:	429e      	cmp	r6, r3
    28d8:	d104      	bne.n	28e4 <nrfx_flag32_alloc+0x30>
    28da:	e840 2c00 	strex	ip, r2, [r0]
    28de:	f1bc 0f00 	cmp.w	ip, #0
    28e2:	d1f6      	bne.n	28d2 <nrfx_flag32_alloc+0x1e>
    28e4:	f3bf 8f5b 	dmb	ish
    } while (!NRFX_ATOMIC_CAS(p_mask, prev_mask, new_mask));
    28e8:	d1e6      	bne.n	28b8 <nrfx_flag32_alloc+0x4>

    *p_flag = idx;

    return NRFX_SUCCESS;
    28ea:	4802      	ldr	r0, [pc, #8]	; (28f4 <nrfx_flag32_alloc+0x40>)
    *p_flag = idx;
    28ec:	700c      	strb	r4, [r1, #0]
}
    28ee:	bd70      	pop	{r4, r5, r6, pc}
            return NRFX_ERROR_NO_MEM;
    28f0:	4801      	ldr	r0, [pc, #4]	; (28f8 <nrfx_flag32_alloc+0x44>)
    28f2:	e7fc      	b.n	28ee <nrfx_flag32_alloc+0x3a>
    28f4:	0bad0000 	.word	0x0bad0000
    28f8:	0bad0002 	.word	0x0bad0002

000028fc <nrfx_flag32_free>:

nrfx_err_t nrfx_flag32_free(nrfx_atomic_t * p_mask, uint8_t flag)
{
    uint32_t new_mask, prev_mask;

    if ((NRFX_BIT(flag) & *p_mask))
    28fc:	6803      	ldr	r3, [r0, #0]
    28fe:	40cb      	lsrs	r3, r1
    2900:	07db      	lsls	r3, r3, #31
{
    2902:	b510      	push	{r4, lr}
    if ((NRFX_BIT(flag) & *p_mask))
    2904:	d415      	bmi.n	2932 <nrfx_flag32_free+0x36>
        return NRFX_ERROR_INVALID_PARAM;
    }

    do {
        prev_mask = *p_mask;
        new_mask = prev_mask | NRFX_BIT(flag);
    2906:	2301      	movs	r3, #1
    2908:	fa03 f101 	lsl.w	r1, r3, r1
        prev_mask = *p_mask;
    290c:	6803      	ldr	r3, [r0, #0]
    290e:	f3bf 8f5b 	dmb	ish
        new_mask = prev_mask | NRFX_BIT(flag);
    2912:	ea41 0203 	orr.w	r2, r1, r3
    2916:	e850 4f00 	ldrex	r4, [r0]
    291a:	429c      	cmp	r4, r3
    291c:	d104      	bne.n	2928 <nrfx_flag32_free+0x2c>
    291e:	e840 2c00 	strex	ip, r2, [r0]
    2922:	f1bc 0f00 	cmp.w	ip, #0
    2926:	d1f6      	bne.n	2916 <nrfx_flag32_free+0x1a>
    2928:	f3bf 8f5b 	dmb	ish
    } while (!NRFX_ATOMIC_CAS(p_mask, prev_mask, new_mask));
    292c:	d1ee      	bne.n	290c <nrfx_flag32_free+0x10>

    return NRFX_SUCCESS;
    292e:	4802      	ldr	r0, [pc, #8]	; (2938 <nrfx_flag32_free+0x3c>)
}
    2930:	bd10      	pop	{r4, pc}
        return NRFX_ERROR_INVALID_PARAM;
    2932:	4802      	ldr	r0, [pc, #8]	; (293c <nrfx_flag32_free+0x40>)
    2934:	e7fc      	b.n	2930 <nrfx_flag32_free+0x34>
    2936:	bf00      	nop
    2938:	0bad0000 	.word	0x0bad0000
    293c:	0bad0004 	.word	0x0bad0004

00002940 <nrfx_clock_init>:
nrfx_err_t nrfx_clock_init(nrfx_clock_event_handler_t event_handler)
{
    NRFX_ASSERT(event_handler);

    nrfx_err_t err_code = NRFX_SUCCESS;
    if (m_clock_cb.module_initialized)
    2940:	4b04      	ldr	r3, [pc, #16]	; (2954 <nrfx_clock_init+0x14>)
    2942:	791a      	ldrb	r2, [r3, #4]
    2944:	b922      	cbnz	r2, 2950 <nrfx_clock_init+0x10>
    {
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
        m_clock_cb.cal_state = CAL_STATE_IDLE;
#endif
        m_clock_cb.event_handler = event_handler;
        m_clock_cb.module_initialized = true;
    2946:	2201      	movs	r2, #1
        m_clock_cb.event_handler = event_handler;
    2948:	6018      	str	r0, [r3, #0]
        m_clock_cb.module_initialized = true;
    294a:	809a      	strh	r2, [r3, #4]
    nrfx_err_t err_code = NRFX_SUCCESS;
    294c:	4802      	ldr	r0, [pc, #8]	; (2958 <nrfx_clock_init+0x18>)
    294e:	4770      	bx	lr
        err_code = NRFX_ERROR_ALREADY_INITIALIZED;
    2950:	4802      	ldr	r0, [pc, #8]	; (295c <nrfx_clock_init+0x1c>)
#endif
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    2952:	4770      	bx	lr
    2954:	20000278 	.word	0x20000278
    2958:	0bad0000 	.word	0x0bad0000
    295c:	0bad000c 	.word	0x0bad000c

00002960 <nrfx_clock_start>:
    m_clock_cb.module_initialized = false;
    NRFX_LOG_INFO("Uninitialized.");
}

void nrfx_clock_start(nrf_clock_domain_t domain)
{
    2960:	b530      	push	{r4, r5, lr}
    NRFX_ASSERT(m_clock_cb.module_initialized);
    switch (domain)
    2962:	b110      	cbz	r0, 296a <nrfx_clock_start+0xa>
    2964:	2801      	cmp	r0, #1
    2966:	d033      	beq.n	29d0 <nrfx_clock_start+0x70>
#endif
        default:
            NRFX_ASSERT(0);
            break;
    }
}
    2968:	bd30      	pop	{r4, r5, pc}
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    296a:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    296e:	f8d3 2418 	ldr.w	r2, [r3, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    2972:	f8d3 1418 	ldr.w	r1, [r3, #1048]	; 0x418
    2976:	f411 3f80 	tst.w	r1, #65536	; 0x10000
    297a:	4619      	mov	r1, r3
    297c:	d024      	beq.n	29c8 <nrfx_clock_start+0x68>
                                        >> CLOCK_LFCLKSTAT_SRC_Pos);
    297e:	f002 0203 	and.w	r2, r2, #3
                if (nrf_clock_is_running(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK, &lfclksrc) &&
    2982:	2a01      	cmp	r2, #1
    2984:	d120      	bne.n	29c8 <nrfx_clock_start+0x68>
    p_reg->LFCLKSRC = (uint32_t)(source);
    2986:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    298a:	4b16      	ldr	r3, [pc, #88]	; (29e4 <nrfx_clock_start+0x84>)
    298c:	2200      	movs	r2, #0
    298e:	601a      	str	r2, [r3, #0]
    2990:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENSET = mask;
    2992:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2996:	2202      	movs	r2, #2
    2998:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    core_debug = CoreDebug->DEMCR;
    299c:	4a12      	ldr	r2, [pc, #72]	; (29e8 <nrfx_clock_start+0x88>)
    299e:	68d0      	ldr	r0, [r2, #12]
    CoreDebug->DEMCR = core_debug | CoreDebug_DEMCR_TRCENA_Msk;
    29a0:	f040 7380 	orr.w	r3, r0, #16777216	; 0x1000000
    29a4:	60d3      	str	r3, [r2, #12]
    dwt_ctrl = DWT->CTRL;
    29a6:	4b11      	ldr	r3, [pc, #68]	; (29ec <nrfx_clock_start+0x8c>)
    29a8:	681c      	ldr	r4, [r3, #0]
    DWT->CTRL = dwt_ctrl | DWT_CTRL_CYCCNTENA_Msk;
    29aa:	f044 0101 	orr.w	r1, r4, #1
    29ae:	6019      	str	r1, [r3, #0]
    cyccnt_inital = DWT->CYCCNT;
    29b0:	685d      	ldr	r5, [r3, #4]
    while ((DWT->CYCCNT - cyccnt_inital) < ANOMALY_132_DELAY_CYCLES)
    29b2:	6859      	ldr	r1, [r3, #4]
    29b4:	1b49      	subs	r1, r1, r5
    29b6:	f5b1 5f0a 	cmp.w	r1, #8832	; 0x2280
    29ba:	d3fa      	bcc.n	29b2 <nrfx_clock_start+0x52>
    DWT->CTRL = dwt_ctrl;
    29bc:	601c      	str	r4, [r3, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    29be:	4b0c      	ldr	r3, [pc, #48]	; (29f0 <nrfx_clock_start+0x90>)
    CoreDebug->DEMCR = core_debug;
    29c0:	60d0      	str	r0, [r2, #12]
    29c2:	2201      	movs	r2, #1
    29c4:	601a      	str	r2, [r3, #0]
}
    29c6:	e7cf      	b.n	2968 <nrfx_clock_start+0x8>
    p_reg->LFCLKSRC = (uint32_t)(source);
    29c8:	2300      	movs	r3, #0
    29ca:	f8c1 3518 	str.w	r3, [r1, #1304]	; 0x518
}
    29ce:	e7dc      	b.n	298a <nrfx_clock_start+0x2a>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    29d0:	4b08      	ldr	r3, [pc, #32]	; (29f4 <nrfx_clock_start+0x94>)
    29d2:	2200      	movs	r2, #0
    29d4:	601a      	str	r2, [r3, #0]
    29d6:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENSET = mask;
    29d8:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    29dc:	f8c3 0304 	str.w	r0, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    29e0:	6018      	str	r0, [r3, #0]
}
    29e2:	e7c1      	b.n	2968 <nrfx_clock_start+0x8>
    29e4:	40000104 	.word	0x40000104
    29e8:	e000edf0 	.word	0xe000edf0
    29ec:	e0001000 	.word	0xe0001000
    29f0:	40000008 	.word	0x40000008
    29f4:	40000100 	.word	0x40000100

000029f8 <nrfx_clock_stop>:

void nrfx_clock_stop(nrf_clock_domain_t domain)
{
    29f8:	b538      	push	{r3, r4, r5, lr}
    NRFX_ASSERT(m_clock_cb.module_initialized);
    switch (domain)
    29fa:	b110      	cbz	r0, 2a02 <nrfx_clock_stop+0xa>
    29fc:	2801      	cmp	r0, #1
    29fe:	d018      	beq.n	2a32 <nrfx_clock_stop+0x3a>
    if (domain == NRF_CLOCK_DOMAIN_HFCLK)
    {
            m_clock_cb.hfclk_started = false;
    }
#endif
}
    2a00:	bd38      	pop	{r3, r4, r5, pc}
    p_reg->INTENCLR = mask;
    2a02:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2a06:	2202      	movs	r2, #2
    2a08:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2a0c:	4a18      	ldr	r2, [pc, #96]	; (2a70 <nrfx_clock_stop+0x78>)
    2a0e:	6010      	str	r0, [r2, #0]
    2a10:	6812      	ldr	r2, [r2, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2a12:	4a18      	ldr	r2, [pc, #96]	; (2a74 <nrfx_clock_stop+0x7c>)
    2a14:	2101      	movs	r1, #1
    2a16:	6011      	str	r1, [r2, #0]
    2a18:	f242 7510 	movw	r5, #10000	; 0x2710
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    2a1c:	461c      	mov	r4, r3
    2a1e:	f8d4 3418 	ldr.w	r3, [r4, #1048]	; 0x418
    2a22:	03db      	lsls	r3, r3, #15
    2a24:	d5ec      	bpl.n	2a00 <nrfx_clock_stop+0x8>
        NRFX_WAIT_FOR(!nrfx_clock_is_running(domain, NULL), 10000, 1, stopped);
    2a26:	2001      	movs	r0, #1
    2a28:	f001 ff01 	bl	482e <nrfx_busy_wait>
    2a2c:	3d01      	subs	r5, #1
    2a2e:	d1f6      	bne.n	2a1e <nrfx_clock_stop+0x26>
    2a30:	e7e6      	b.n	2a00 <nrfx_clock_stop+0x8>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2a32:	4b11      	ldr	r3, [pc, #68]	; (2a78 <nrfx_clock_stop+0x80>)
    p_reg->INTENCLR = mask;
    2a34:	f04f 4480 	mov.w	r4, #1073741824	; 0x40000000
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2a38:	2200      	movs	r2, #0
    p_reg->INTENCLR = mask;
    2a3a:	f8c4 0308 	str.w	r0, [r4, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2a3e:	601a      	str	r2, [r3, #0]
    2a40:	681b      	ldr	r3, [r3, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2a42:	4b0e      	ldr	r3, [pc, #56]	; (2a7c <nrfx_clock_stop+0x84>)
    2a44:	f242 7510 	movw	r5, #10000	; 0x2710
    2a48:	6018      	str	r0, [r3, #0]
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    2a4a:	f8d4 340c 	ldr.w	r3, [r4, #1036]	; 0x40c
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    2a4e:	f8d4 240c 	ldr.w	r2, [r4, #1036]	; 0x40c
    2a52:	03d2      	lsls	r2, r2, #15
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    2a54:	f003 0301 	and.w	r3, r3, #1
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    2a58:	d505      	bpl.n	2a66 <nrfx_clock_stop+0x6e>
        NRFX_WAIT_FOR((!nrfx_clock_is_running(domain, &clk_src) ||
    2a5a:	b123      	cbz	r3, 2a66 <nrfx_clock_stop+0x6e>
    2a5c:	2001      	movs	r0, #1
    2a5e:	f001 fee6 	bl	482e <nrfx_busy_wait>
    2a62:	3d01      	subs	r5, #1
    2a64:	d1f1      	bne.n	2a4a <nrfx_clock_stop+0x52>
            m_clock_cb.hfclk_started = false;
    2a66:	4b06      	ldr	r3, [pc, #24]	; (2a80 <nrfx_clock_stop+0x88>)
    2a68:	2200      	movs	r2, #0
    2a6a:	715a      	strb	r2, [r3, #5]
    2a6c:	e7c8      	b.n	2a00 <nrfx_clock_stop+0x8>
    2a6e:	bf00      	nop
    2a70:	40000104 	.word	0x40000104
    2a74:	4000000c 	.word	0x4000000c
    2a78:	40000100 	.word	0x40000100
    2a7c:	40000004 	.word	0x40000004
    2a80:	20000278 	.word	0x20000278

00002a84 <nrfx_power_clock_irq_handler>:
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    2a84:	4b16      	ldr	r3, [pc, #88]	; (2ae0 <nrfx_power_clock_irq_handler+0x5c>)
    2a86:	681a      	ldr	r2, [r3, #0]
    }
}
#endif

void nrfx_clock_irq_handler(void)
{
    2a88:	b510      	push	{r4, lr}
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED))
    2a8a:	b16a      	cbz	r2, 2aa8 <nrfx_power_clock_irq_handler+0x24>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2a8c:	2200      	movs	r2, #0
    2a8e:	601a      	str	r2, [r3, #0]
    2a90:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENCLR = mask;
    2a92:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2a96:	2201      	movs	r2, #1
    2a98:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
        nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED);
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_HFCLKSTARTED");
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF_STARTED_MASK);

#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_201)
        if (!m_clock_cb.hfclk_started)
    2a9c:	4b11      	ldr	r3, [pc, #68]	; (2ae4 <nrfx_power_clock_irq_handler+0x60>)
    2a9e:	7958      	ldrb	r0, [r3, #5]
    2aa0:	b910      	cbnz	r0, 2aa8 <nrfx_power_clock_irq_handler+0x24>
        {
            m_clock_cb.hfclk_started = true;
    2aa2:	715a      	strb	r2, [r3, #5]
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
    2aa4:	681b      	ldr	r3, [r3, #0]
    2aa6:	4798      	blx	r3
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    2aa8:	4b0f      	ldr	r3, [pc, #60]	; (2ae8 <nrfx_power_clock_irq_handler+0x64>)
    2aaa:	681a      	ldr	r2, [r3, #0]
        }
#else
        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
#endif
    }
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED))
    2aac:	b172      	cbz	r2, 2acc <nrfx_power_clock_irq_handler+0x48>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2aae:	2200      	movs	r2, #0
    2ab0:	601a      	str	r2, [r3, #0]
    2ab2:	681b      	ldr	r3, [r3, #0]
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    2ab4:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2ab8:	f8d3 2418 	ldr.w	r2, [r3, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    2abc:	f8d3 1418 	ldr.w	r1, [r3, #1048]	; 0x418
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_LFCLKSTARTED");

#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED)
        nrf_clock_lfclk_t lfclksrc;
        (void)nrf_clock_is_running(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK, &lfclksrc);
        if (lfclksrc == NRF_CLOCK_LFCLK_RC)
    2ac0:	0792      	lsls	r2, r2, #30
    2ac2:	d104      	bne.n	2ace <nrfx_power_clock_irq_handler+0x4a>
    p_reg->LFCLKSRC = (uint32_t)(source);
    2ac4:	2201      	movs	r2, #1
    2ac6:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2aca:	609a      	str	r2, [r3, #8]
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF192M_STARTED_MASK);

        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK192M_STARTED);
    }
#endif
}
    2acc:	bd10      	pop	{r4, pc}
    p_reg->INTENCLR = mask;
    2ace:	2202      	movs	r2, #2
    2ad0:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    2ad4:	4b03      	ldr	r3, [pc, #12]	; (2ae4 <nrfx_power_clock_irq_handler+0x60>)
}
    2ad6:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    2ada:	681b      	ldr	r3, [r3, #0]
    2adc:	2001      	movs	r0, #1
    2ade:	4718      	bx	r3
    2ae0:	40000100 	.word	0x40000100
    2ae4:	20000278 	.word	0x20000278
    2ae8:	40000104 	.word	0x40000104

00002aec <call_handler>:
    nrf_gpiote_event_t event = nrfx_gpiote_in_event_get(pin);
    return nrf_gpiote_event_address_get(NRF_GPIOTE, event);
}

static void call_handler(nrfx_gpiote_pin_t pin, nrfx_gpiote_trigger_t trigger)
{
    2aec:	b570      	push	{r4, r5, r6, lr}
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    2aee:	f100 0308 	add.w	r3, r0, #8
    2af2:	4c0c      	ldr	r4, [pc, #48]	; (2b24 <call_handler+0x38>)
    2af4:	f834 3013 	ldrh.w	r3, [r4, r3, lsl #1]
    2af8:	05da      	lsls	r2, r3, #23
{
    2afa:	4605      	mov	r5, r0
    2afc:	460e      	mov	r6, r1
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    2afe:	d507      	bpl.n	2b10 <call_handler+0x24>
    2b00:	f3c3 2343 	ubfx	r3, r3, #9, #4
    nrfx_gpiote_handler_config_t const * handler = channel_handler_get(pin);

    if (handler)
    {
        handler->handler(pin, trigger, handler->p_context);
    2b04:	eb04 02c3 	add.w	r2, r4, r3, lsl #3
    2b08:	f854 3033 	ldr.w	r3, [r4, r3, lsl #3]
    2b0c:	6852      	ldr	r2, [r2, #4]
    2b0e:	4798      	blx	r3
    }
    if (m_cb.global_handler.handler)
    2b10:	68a3      	ldr	r3, [r4, #8]
    2b12:	b12b      	cbz	r3, 2b20 <call_handler+0x34>
    {
        m_cb.global_handler.handler(pin, trigger, m_cb.global_handler.p_context);
    2b14:	68e2      	ldr	r2, [r4, #12]
    2b16:	4631      	mov	r1, r6
    2b18:	4628      	mov	r0, r5
    }
}
    2b1a:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
        m_cb.global_handler.handler(pin, trigger, m_cb.global_handler.p_context);
    2b1e:	4718      	bx	r3
}
    2b20:	bd70      	pop	{r4, r5, r6, pc}
    2b22:	bf00      	nop
    2b24:	20000020 	.word	0x20000020

00002b28 <release_handler>:
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    2b28:	4b12      	ldr	r3, [pc, #72]	; (2b74 <release_handler+0x4c>)
    2b2a:	3008      	adds	r0, #8
{
    2b2c:	b410      	push	{r4}
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    2b2e:	f833 2010 	ldrh.w	r2, [r3, r0, lsl #1]
    2b32:	05d1      	lsls	r1, r2, #23
    2b34:	d51b      	bpl.n	2b6e <release_handler+0x46>
    2b36:	f3c2 2143 	ubfx	r1, r2, #9, #4
    m_cb.pin_flags[pin] &= ~PIN_HANDLER_MASK;
    2b3a:	f422 52f8 	bic.w	r2, r2, #7936	; 0x1f00
    2b3e:	f823 2010 	strh.w	r2, [r3, r0, lsl #1]
    for (uint32_t i = 0; i < MAX_PIN_NUMBER; i++)
    2b42:	f103 0410 	add.w	r4, r3, #16
    2b46:	2000      	movs	r0, #0
        if (PIN_GET_HANDLER_ID(m_cb.pin_flags[i]) == handler_id)
    2b48:	f834 2b02 	ldrh.w	r2, [r4], #2
    2b4c:	f412 7f80 	tst.w	r2, #256	; 0x100
    2b50:	d003      	beq.n	2b5a <release_handler+0x32>
    2b52:	f3c2 2243 	ubfx	r2, r2, #9, #4
    2b56:	4291      	cmp	r1, r2
    2b58:	d009      	beq.n	2b6e <release_handler+0x46>
    for (uint32_t i = 0; i < MAX_PIN_NUMBER; i++)
    2b5a:	3001      	adds	r0, #1
    2b5c:	2820      	cmp	r0, #32
    2b5e:	d1f3      	bne.n	2b48 <release_handler+0x20>
        m_cb.handlers[handler_id].handler = NULL;
    2b60:	2200      	movs	r2, #0
    2b62:	f843 2031 	str.w	r2, [r3, r1, lsl #3]
        nrfx_err_t err = nrfx_flag32_free(&m_cb.available_evt_handlers, handler_id);
    2b66:	4804      	ldr	r0, [pc, #16]	; (2b78 <release_handler+0x50>)
}
    2b68:	bc10      	pop	{r4}
        nrfx_err_t err = nrfx_flag32_free(&m_cb.available_evt_handlers, handler_id);
    2b6a:	f7ff bec7 	b.w	28fc <nrfx_flag32_free>
}
    2b6e:	bc10      	pop	{r4}
    2b70:	4770      	bx	lr
    2b72:	bf00      	nop
    2b74:	20000020 	.word	0x20000020
    2b78:	20000074 	.word	0x20000074

00002b7c <pin_handler_trigger_uninit>:
{
    2b7c:	b538      	push	{r3, r4, r5, lr}
    return m_cb.pin_flags[pin] & PIN_FLAG_TE_USED;
    2b7e:	4c0a      	ldr	r4, [pc, #40]	; (2ba8 <pin_handler_trigger_uninit+0x2c>)
    2b80:	f100 0508 	add.w	r5, r0, #8
    2b84:	f834 3015 	ldrh.w	r3, [r4, r5, lsl #1]
    if (pin_in_use_by_te(pin))
    2b88:	069a      	lsls	r2, r3, #26
    2b8a:	d506      	bpl.n	2b9a <pin_handler_trigger_uninit+0x1e>
        nrf_gpiote_te_default(NRF_GPIOTE, pin_te_get(pin));
    2b8c:	0b5b      	lsrs	r3, r3, #13
                         ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
}

NRF_STATIC_INLINE void nrf_gpiote_te_default(NRF_GPIOTE_Type * p_reg, uint32_t idx)
{
    p_reg->CONFIG[idx] = 0;
    2b8e:	4a07      	ldr	r2, [pc, #28]	; (2bac <pin_handler_trigger_uninit+0x30>)
    2b90:	f503 73a2 	add.w	r3, r3, #324	; 0x144
    2b94:	2100      	movs	r1, #0
    2b96:	f842 1023 	str.w	r1, [r2, r3, lsl #2]
    release_handler(pin);
    2b9a:	f7ff ffc5 	bl	2b28 <release_handler>
    m_cb.pin_flags[pin] = PIN_FLAG_NOT_USED;
    2b9e:	2300      	movs	r3, #0
    2ba0:	f824 3015 	strh.w	r3, [r4, r5, lsl #1]
}
    2ba4:	bd38      	pop	{r3, r4, r5, pc}
    2ba6:	bf00      	nop
    2ba8:	20000020 	.word	0x20000020
    2bac:	40006000 	.word	0x40006000

00002bb0 <nrfx_gpiote_input_configure>:
{
    2bb0:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
    2bb2:	4604      	mov	r4, r0
    if (p_input_config)
    2bb4:	b1f9      	cbz	r1, 2bf6 <nrfx_gpiote_input_configure+0x46>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    2bb6:	4f4c      	ldr	r7, [pc, #304]	; (2ce8 <nrfx_gpiote_input_configure+0x138>)
    2bb8:	f100 0c08 	add.w	ip, r0, #8
    2bbc:	f837 001c 	ldrh.w	r0, [r7, ip, lsl #1]
        if (pin_is_task_output(pin))
    2bc0:	f000 0522 	and.w	r5, r0, #34	; 0x22
    2bc4:	2d22      	cmp	r5, #34	; 0x22
    2bc6:	d102      	bne.n	2bce <nrfx_gpiote_input_configure+0x1e>
            return NRFX_ERROR_INVALID_PARAM;
    2bc8:	4848      	ldr	r0, [pc, #288]	; (2cec <nrfx_gpiote_input_configure+0x13c>)
}
    2bca:	b003      	add	sp, #12
    2bcc:	bdf0      	pop	{r4, r5, r6, r7, pc}
    *p_pin = pin_number & 0x1F;
    2bce:	f004 051f 	and.w	r5, r4, #31
    2bd2:	00ad      	lsls	r5, r5, #2
    2bd4:	f105 45a0 	add.w	r5, r5, #1342177280	; 0x50000000
           ((uint32_t)(p_pull  ? *p_pull  : 0) << GPIO_PIN_CNF_PULL_Pos)  |
    2bd8:	7809      	ldrb	r1, [r1, #0]
    uint32_t cnf = reg->PIN_CNF[pin_number];
    2bda:	f8d5 6700 	ldr.w	r6, [r5, #1792]	; 0x700
        m_cb.pin_flags[pin] &= ~PIN_FLAG_OUTPUT;
    2bde:	f020 0002 	bic.w	r0, r0, #2
    cnf &= ~to_update;
    2be2:	f026 060f 	bic.w	r6, r6, #15
        m_cb.pin_flags[pin] |= PIN_FLAG_IN_USE;
    2be6:	f040 0001 	orr.w	r0, r0, #1
    cnf |= ((uint32_t)(p_dir   ? *p_dir   : 0) << GPIO_PIN_CNF_DIR_Pos)   |
    2bea:	ea46 0181 	orr.w	r1, r6, r1, lsl #2
    2bee:	f827 001c 	strh.w	r0, [r7, ip, lsl #1]
    reg->PIN_CNF[pin_number] = cnf;
    2bf2:	f8c5 1700 	str.w	r1, [r5, #1792]	; 0x700
    if (p_trigger_config)
    2bf6:	b192      	cbz	r2, 2c1e <nrfx_gpiote_input_configure+0x6e>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    2bf8:	483b      	ldr	r0, [pc, #236]	; (2ce8 <nrfx_gpiote_input_configure+0x138>)
        nrfx_gpiote_trigger_t trigger = p_trigger_config->trigger;
    2bfa:	7816      	ldrb	r6, [r2, #0]
        bool use_evt = p_trigger_config->p_in_channel ? true : false;
    2bfc:	6852      	ldr	r2, [r2, #4]
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    2bfe:	f104 0508 	add.w	r5, r4, #8
    2c02:	f830 1015 	ldrh.w	r1, [r0, r5, lsl #1]
        if (pin_is_output(pin))
    2c06:	078f      	lsls	r7, r1, #30
    2c08:	d50c      	bpl.n	2c24 <nrfx_gpiote_input_configure+0x74>
            if (use_evt)
    2c0a:	2a00      	cmp	r2, #0
    2c0c:	d1dc      	bne.n	2bc8 <nrfx_gpiote_input_configure+0x18>
        m_cb.pin_flags[pin] &= ~PIN_FLAG_TRIG_MODE_MASK;
    2c0e:	f830 2015 	ldrh.w	r2, [r0, r5, lsl #1]
    2c12:	f022 021c 	bic.w	r2, r2, #28
        m_cb.pin_flags[pin] |= PIN_FLAG_TRIG_MODE_SET(trigger);
    2c16:	ea42 0286 	orr.w	r2, r2, r6, lsl #2
    2c1a:	f820 2015 	strh.w	r2, [r0, r5, lsl #1]
    if (p_handler_config)
    2c1e:	bbcb      	cbnz	r3, 2c94 <nrfx_gpiote_input_configure+0xe4>
    return NRFX_SUCCESS;
    2c20:	4833      	ldr	r0, [pc, #204]	; (2cf0 <nrfx_gpiote_input_configure+0x140>)
    2c22:	e7d2      	b.n	2bca <nrfx_gpiote_input_configure+0x1a>
            m_cb.pin_flags[pin] &= ~(PIN_TE_ID_MASK | PIN_FLAG_TE_USED);
    2c24:	f021 0120 	bic.w	r1, r1, #32
    2c28:	04c9      	lsls	r1, r1, #19
    2c2a:	0cc9      	lsrs	r1, r1, #19
    2c2c:	f820 1015 	strh.w	r1, [r0, r5, lsl #1]
            if (use_evt)
    2c30:	2a00      	cmp	r2, #0
    2c32:	d0ec      	beq.n	2c0e <nrfx_gpiote_input_configure+0x5e>
                if (!edge)
    2c34:	2e03      	cmp	r6, #3
    2c36:	d8c7      	bhi.n	2bc8 <nrfx_gpiote_input_configure+0x18>
                uint8_t ch = *p_trigger_config->p_in_channel;
    2c38:	7817      	ldrb	r7, [r2, #0]
                if (trigger == NRFX_GPIOTE_TRIGGER_NONE)
    2c3a:	b92e      	cbnz	r6, 2c48 <nrfx_gpiote_input_configure+0x98>
    2c3c:	4a2d      	ldr	r2, [pc, #180]	; (2cf4 <nrfx_gpiote_input_configure+0x144>)
    2c3e:	f507 71a2 	add.w	r1, r7, #324	; 0x144
    2c42:	f842 6021 	str.w	r6, [r2, r1, lsl #2]
#if defined(NRF9160_XXAA) || defined(NRF5340_XXAA)
    p_reg->CONFIG[idx] = 0;
#endif
}
    2c46:	e7e2      	b.n	2c0e <nrfx_gpiote_input_configure+0x5e>
   p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk;
    2c48:	00ba      	lsls	r2, r7, #2
    2c4a:	f102 4280 	add.w	r2, r2, #1073741824	; 0x40000000
    2c4e:	f502 42c0 	add.w	r2, r2, #24576	; 0x6000
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    2c52:	ea4f 2e04 	mov.w	lr, r4, lsl #8
   p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk;
    2c56:	f8d2 c510 	ldr.w	ip, [r2, #1296]	; 0x510
    2c5a:	f02c 0c03 	bic.w	ip, ip, #3
    2c5e:	f8c2 c510 	str.w	ip, [r2, #1296]	; 0x510
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk);
    2c62:	f8d2 c510 	ldr.w	ip, [r2, #1296]	; 0x510
    2c66:	f42c 3c47 	bic.w	ip, ip, #203776	; 0x31c00
    2c6a:	f42c 7c40 	bic.w	ip, ip, #768	; 0x300
    2c6e:	f8c2 c510 	str.w	ip, [r2, #1296]	; 0x510
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    2c72:	f8d2 c510 	ldr.w	ip, [r2, #1296]	; 0x510
    2c76:	f40e 5ef8 	and.w	lr, lr, #7936	; 0x1f00
    2c7a:	ea4c 4c06 	orr.w	ip, ip, r6, lsl #16
                    m_cb.pin_flags[pin] |= PIN_FLAG_TE_ID(ch);
    2c7e:	ea41 3147 	orr.w	r1, r1, r7, lsl #13
    2c82:	ea4c 0c0e 	orr.w	ip, ip, lr
    2c86:	f041 0120 	orr.w	r1, r1, #32
    2c8a:	f820 1015 	strh.w	r1, [r0, r5, lsl #1]
    2c8e:	f8c2 c510 	str.w	ip, [r2, #1296]	; 0x510
    2c92:	e7bc      	b.n	2c0e <nrfx_gpiote_input_configure+0x5e>
        err = pin_handler_set(pin, p_handler_config->handler, p_handler_config->p_context);
    2c94:	e9d3 6700 	ldrd	r6, r7, [r3]
    release_handler(pin);
    2c98:	4620      	mov	r0, r4
    2c9a:	f7ff ff45 	bl	2b28 <release_handler>
    if (!handler)
    2c9e:	2e00      	cmp	r6, #0
    2ca0:	d0be      	beq.n	2c20 <nrfx_gpiote_input_configure+0x70>
        if ((m_cb.handlers[i].handler == handler) && (m_cb.handlers[i].p_context == p_context))
    2ca2:	4d11      	ldr	r5, [pc, #68]	; (2ce8 <nrfx_gpiote_input_configure+0x138>)
    2ca4:	682b      	ldr	r3, [r5, #0]
    2ca6:	429e      	cmp	r6, r3
    2ca8:	d104      	bne.n	2cb4 <nrfx_gpiote_input_configure+0x104>
    2caa:	686b      	ldr	r3, [r5, #4]
    2cac:	429f      	cmp	r7, r3
    2cae:	d101      	bne.n	2cb4 <nrfx_gpiote_input_configure+0x104>
    2cb0:	2200      	movs	r2, #0
    2cb2:	e009      	b.n	2cc8 <nrfx_gpiote_input_configure+0x118>
        err = nrfx_flag32_alloc(&m_cb.available_evt_handlers, &id);
    2cb4:	4810      	ldr	r0, [pc, #64]	; (2cf8 <nrfx_gpiote_input_configure+0x148>)
    2cb6:	f10d 0107 	add.w	r1, sp, #7
    2cba:	f7ff fdfb 	bl	28b4 <nrfx_flag32_alloc>
        if (err != NRFX_SUCCESS)
    2cbe:	4b0c      	ldr	r3, [pc, #48]	; (2cf0 <nrfx_gpiote_input_configure+0x140>)
    2cc0:	4298      	cmp	r0, r3
    2cc2:	d182      	bne.n	2bca <nrfx_gpiote_input_configure+0x1a>
        handler_id = (int32_t)id;
    2cc4:	f89d 2007 	ldrb.w	r2, [sp, #7]
    m_cb.handlers[handler_id].handler = handler;
    2cc8:	f845 6032 	str.w	r6, [r5, r2, lsl #3]
    m_cb.handlers[handler_id].p_context = p_context;
    2ccc:	eb05 03c2 	add.w	r3, r5, r2, lsl #3
    m_cb.pin_flags[pin] |= PIN_FLAG_HANDLER(handler_id);
    2cd0:	3408      	adds	r4, #8
    m_cb.handlers[handler_id].p_context = p_context;
    2cd2:	605f      	str	r7, [r3, #4]
    m_cb.pin_flags[pin] |= PIN_FLAG_HANDLER(handler_id);
    2cd4:	f835 3014 	ldrh.w	r3, [r5, r4, lsl #1]
    2cd8:	ea43 2342 	orr.w	r3, r3, r2, lsl #9
    2cdc:	f443 7380 	orr.w	r3, r3, #256	; 0x100
    2ce0:	f825 3014 	strh.w	r3, [r5, r4, lsl #1]
    2ce4:	e79c      	b.n	2c20 <nrfx_gpiote_input_configure+0x70>
    2ce6:	bf00      	nop
    2ce8:	20000020 	.word	0x20000020
    2cec:	0bad0004 	.word	0x0bad0004
    2cf0:	0bad0000 	.word	0x0bad0000
    2cf4:	40006000 	.word	0x40006000
    2cf8:	20000074 	.word	0x20000074

00002cfc <nrfx_gpiote_output_configure>:
{
    2cfc:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
    if (p_config)
    2d00:	2900      	cmp	r1, #0
    2d02:	d044      	beq.n	2d8e <nrfx_gpiote_output_configure+0x92>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    2d04:	4f42      	ldr	r7, [pc, #264]	; (2e10 <nrfx_gpiote_output_configure+0x114>)
    2d06:	f100 0c08 	add.w	ip, r0, #8
    2d0a:	f837 501c 	ldrh.w	r5, [r7, ip, lsl #1]
        if (pin_is_input(pin) && pin_in_use_by_te(pin))
    2d0e:	07ab      	lsls	r3, r5, #30
    2d10:	d404      	bmi.n	2d1c <nrfx_gpiote_output_configure+0x20>
    2d12:	06ae      	lsls	r6, r5, #26
    2d14:	d502      	bpl.n	2d1c <nrfx_gpiote_output_configure+0x20>
           ((uint32_t)(p_pull  ? *p_pull  : 0) << GPIO_PIN_CNF_PULL_Pos)  |
    2d16:	483f      	ldr	r0, [pc, #252]	; (2e14 <nrfx_gpiote_output_configure+0x118>)
}
    2d18:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
        if (pin_has_trigger(pin) && (p_config->input_connect == NRF_GPIO_PIN_INPUT_DISCONNECT))
    2d1c:	f015 0f1c 	tst.w	r5, #28
    2d20:	d002      	beq.n	2d28 <nrfx_gpiote_output_configure+0x2c>
    2d22:	784b      	ldrb	r3, [r1, #1]
    2d24:	2b01      	cmp	r3, #1
    2d26:	d0f6      	beq.n	2d16 <nrfx_gpiote_output_configure+0x1a>
                         (p_input ? GPIO_PIN_CNF_INPUT_Msk : 0) |
    2d28:	f111 0e01 	adds.w	lr, r1, #1
    *p_pin = pin_number & 0x1F;
    2d2c:	f000 061f 	and.w	r6, r0, #31
                         (p_input ? GPIO_PIN_CNF_INPUT_Msk : 0) |
    2d30:	bf14      	ite	ne
    2d32:	2402      	movne	r4, #2
    2d34:	2400      	moveq	r4, #0
    2d36:	00b6      	lsls	r6, r6, #2
                         (p_pull  ? GPIO_PIN_CNF_PULL_Msk  : 0) |
    2d38:	1c8b      	adds	r3, r1, #2
    2d3a:	f106 46a0 	add.w	r6, r6, #1342177280	; 0x50000000
    2d3e:	bf14      	ite	ne
    2d40:	f04f 090c 	movne.w	r9, #12
    2d44:	f04f 0900 	moveq.w	r9, #0
    2d48:	ea44 0409 	orr.w	r4, r4, r9
    uint32_t cnf = reg->PIN_CNF[pin_number];
    2d4c:	f8d6 8700 	ldr.w	r8, [r6, #1792]	; 0x700
                         (p_pull  ? GPIO_PIN_CNF_PULL_Msk  : 0) |
    2d50:	f444 64e0 	orr.w	r4, r4, #1792	; 0x700
    2d54:	f044 0401 	orr.w	r4, r4, #1
    cnf &= ~to_update;
    2d58:	ea28 0804 	bic.w	r8, r8, r4
           ((uint32_t)(p_input ? *p_input : 0) << GPIO_PIN_CNF_INPUT_Pos) |
    2d5c:	f1be 0f00 	cmp.w	lr, #0
    2d60:	d003      	beq.n	2d6a <nrfx_gpiote_output_configure+0x6e>
    2d62:	f891 e001 	ldrb.w	lr, [r1, #1]
    2d66:	ea4f 0e4e 	mov.w	lr, lr, lsl #1
           ((uint32_t)(p_pull  ? *p_pull  : 0) << GPIO_PIN_CNF_PULL_Pos)  |
    2d6a:	b10b      	cbz	r3, 2d70 <nrfx_gpiote_output_configure+0x74>
    2d6c:	788c      	ldrb	r4, [r1, #2]
    2d6e:	00a3      	lsls	r3, r4, #2
           ((uint32_t)(p_drive ? *p_drive : 0) << GPIO_PIN_CNF_DRIVE_Pos) |
    2d70:	7809      	ldrb	r1, [r1, #0]
    2d72:	ea43 2301 	orr.w	r3, r3, r1, lsl #8
    2d76:	ea43 0308 	orr.w	r3, r3, r8
    2d7a:	ea43 030e 	orr.w	r3, r3, lr
        m_cb.pin_flags[pin] |= PIN_FLAG_IN_USE | PIN_FLAG_OUTPUT;
    2d7e:	f045 0503 	orr.w	r5, r5, #3
    cnf |= ((uint32_t)(p_dir   ? *p_dir   : 0) << GPIO_PIN_CNF_DIR_Pos)   |
    2d82:	f043 0301 	orr.w	r3, r3, #1
    2d86:	f827 501c 	strh.w	r5, [r7, ip, lsl #1]
    reg->PIN_CNF[pin_number] = cnf;
    2d8a:	f8c6 3700 	str.w	r3, [r6, #1792]	; 0x700
    if (p_task_config)
    2d8e:	b90a      	cbnz	r2, 2d94 <nrfx_gpiote_output_configure+0x98>
    return NRFX_SUCCESS;
    2d90:	4821      	ldr	r0, [pc, #132]	; (2e18 <nrfx_gpiote_output_configure+0x11c>)
    2d92:	e7c1      	b.n	2d18 <nrfx_gpiote_output_configure+0x1c>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    2d94:	4d1e      	ldr	r5, [pc, #120]	; (2e10 <nrfx_gpiote_output_configure+0x114>)
    2d96:	f100 0608 	add.w	r6, r0, #8
    2d9a:	f835 4016 	ldrh.w	r4, [r5, r6, lsl #1]
        if (pin_is_input(pin))
    2d9e:	07a3      	lsls	r3, r4, #30
    2da0:	d5b9      	bpl.n	2d16 <nrfx_gpiote_output_configure+0x1a>
        uint32_t ch = p_task_config->task_ch;
    2da2:	7817      	ldrb	r7, [r2, #0]
        m_cb.pin_flags[pin] &= ~(PIN_FLAG_TE_USED | PIN_TE_ID_MASK);
    2da4:	f024 0420 	bic.w	r4, r4, #32
    2da8:	00b9      	lsls	r1, r7, #2
    2daa:	f101 4180 	add.w	r1, r1, #1073741824	; 0x40000000
    2dae:	04e4      	lsls	r4, r4, #19
    2db0:	f501 41c0 	add.w	r1, r1, #24576	; 0x6000
    2db4:	0ce4      	lsrs	r4, r4, #19
    2db6:	f825 4016 	strh.w	r4, [r5, r6, lsl #1]
    p_reg->CONFIG[idx] = 0;
    2dba:	2300      	movs	r3, #0
    2dbc:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
        if (p_task_config->polarity != NRF_GPIOTE_POLARITY_NONE)
    2dc0:	f892 c001 	ldrb.w	ip, [r2, #1]
    2dc4:	f1bc 0f00 	cmp.w	ip, #0
    2dc8:	d0e2      	beq.n	2d90 <nrfx_gpiote_output_configure+0x94>
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk |
    2dca:	f8d1 3510 	ldr.w	r3, [r1, #1296]	; 0x510
            nrf_gpiote_task_configure(NRF_GPIOTE, ch, pin,
    2dce:	7892      	ldrb	r2, [r2, #2]
    2dd0:	f423 1398 	bic.w	r3, r3, #1245184	; 0x130000
    2dd4:	f423 53f8 	bic.w	r3, r3, #7936	; 0x1f00
    2dd8:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    2ddc:	f8d1 e510 	ldr.w	lr, [r1, #1296]	; 0x510
    2de0:	0203      	lsls	r3, r0, #8
    2de2:	f403 53f8 	and.w	r3, r3, #7936	; 0x1f00
                        ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk) |
    2de6:	ea4f 400c 	mov.w	r0, ip, lsl #16
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    2dea:	ea43 030e 	orr.w	r3, r3, lr
                        ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk) |
    2dee:	f400 3040 	and.w	r0, r0, #196608	; 0x30000
                        ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
    2df2:	0512      	lsls	r2, r2, #20
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    2df4:	4303      	orrs	r3, r0
                        ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
    2df6:	f402 1280 	and.w	r2, r2, #1048576	; 0x100000
            m_cb.pin_flags[pin] |= PIN_FLAG_TE_ID(ch);
    2dfa:	ea44 3447 	orr.w	r4, r4, r7, lsl #13
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    2dfe:	4313      	orrs	r3, r2
    2e00:	f044 0420 	orr.w	r4, r4, #32
    2e04:	f825 4016 	strh.w	r4, [r5, r6, lsl #1]
    2e08:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
    2e0c:	e7c0      	b.n	2d90 <nrfx_gpiote_output_configure+0x94>
    2e0e:	bf00      	nop
    2e10:	20000020 	.word	0x20000020
    2e14:	0bad0004 	.word	0x0bad0004
    2e18:	0bad0000 	.word	0x0bad0000

00002e1c <nrfx_gpiote_global_callback_set>:
    m_cb.global_handler.handler = handler;
    2e1c:	4b01      	ldr	r3, [pc, #4]	; (2e24 <nrfx_gpiote_global_callback_set+0x8>)
    m_cb.global_handler.p_context = p_context;
    2e1e:	e9c3 0102 	strd	r0, r1, [r3, #8]
}
    2e22:	4770      	bx	lr
    2e24:	20000020 	.word	0x20000020

00002e28 <nrfx_gpiote_channel_get>:
    return m_cb.pin_flags[pin] & PIN_FLAG_TE_USED;
    2e28:	3008      	adds	r0, #8
    2e2a:	4b05      	ldr	r3, [pc, #20]	; (2e40 <nrfx_gpiote_channel_get+0x18>)
    2e2c:	f833 3010 	ldrh.w	r3, [r3, r0, lsl #1]
    if (pin_in_use_by_te(pin))
    2e30:	069a      	lsls	r2, r3, #26
        *p_channel = PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    2e32:	bf43      	ittte	mi
    2e34:	0b5b      	lsrmi	r3, r3, #13
        return NRFX_SUCCESS;
    2e36:	4803      	ldrmi	r0, [pc, #12]	; (2e44 <nrfx_gpiote_channel_get+0x1c>)
        *p_channel = PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    2e38:	700b      	strbmi	r3, [r1, #0]
        return NRFX_ERROR_INVALID_PARAM;
    2e3a:	4803      	ldrpl	r0, [pc, #12]	; (2e48 <nrfx_gpiote_channel_get+0x20>)
}
    2e3c:	4770      	bx	lr
    2e3e:	bf00      	nop
    2e40:	20000020 	.word	0x20000020
    2e44:	0bad0000 	.word	0x0bad0000
    2e48:	0bad0004 	.word	0x0bad0004

00002e4c <nrfx_gpiote_init>:
{
    2e4c:	b538      	push	{r3, r4, r5, lr}
    if (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED)
    2e4e:	4c0e      	ldr	r4, [pc, #56]	; (2e88 <nrfx_gpiote_init+0x3c>)
    2e50:	f894 5058 	ldrb.w	r5, [r4, #88]	; 0x58
    2e54:	b9b5      	cbnz	r5, 2e84 <nrfx_gpiote_init+0x38>
    memset(m_cb.pin_flags, 0, sizeof(m_cb.pin_flags));
    2e56:	2240      	movs	r2, #64	; 0x40
    2e58:	4629      	mov	r1, r5
    2e5a:	f104 0010 	add.w	r0, r4, #16
    2e5e:	f001 fa9e 	bl	439e <memset>
    NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_GPIOTE));
    2e62:	2006      	movs	r0, #6
    2e64:	f7fe f8ac 	bl	fc0 <arch_irq_enable>
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    2e68:	4b08      	ldr	r3, [pc, #32]	; (2e8c <nrfx_gpiote_init+0x40>)
    return err_code;
    2e6a:	4809      	ldr	r0, [pc, #36]	; (2e90 <nrfx_gpiote_init+0x44>)
    2e6c:	601d      	str	r5, [r3, #0]
    2e6e:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENSET = mask;
    2e70:	4b08      	ldr	r3, [pc, #32]	; (2e94 <nrfx_gpiote_init+0x48>)
    2e72:	f04f 4200 	mov.w	r2, #2147483648	; 0x80000000
    2e76:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    m_cb.state = NRFX_DRV_STATE_INITIALIZED;
    2e7a:	2301      	movs	r3, #1
    2e7c:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
    m_cb.available_evt_handlers = NRFX_BIT_MASK(NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS);
    2e80:	6563      	str	r3, [r4, #84]	; 0x54
}
    2e82:	bd38      	pop	{r3, r4, r5, pc}
        return err_code;
    2e84:	4804      	ldr	r0, [pc, #16]	; (2e98 <nrfx_gpiote_init+0x4c>)
    2e86:	e7fc      	b.n	2e82 <nrfx_gpiote_init+0x36>
    2e88:	20000020 	.word	0x20000020
    2e8c:	4000617c 	.word	0x4000617c
    2e90:	0bad0000 	.word	0x0bad0000
    2e94:	40006000 	.word	0x40006000
    2e98:	0bad0005 	.word	0x0bad0005

00002e9c <nrfx_gpiote_is_init>:
    return (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED) ? true : false;
    2e9c:	4b03      	ldr	r3, [pc, #12]	; (2eac <nrfx_gpiote_is_init+0x10>)
    2e9e:	f893 0058 	ldrb.w	r0, [r3, #88]	; 0x58
}
    2ea2:	3800      	subs	r0, #0
    2ea4:	bf18      	it	ne
    2ea6:	2001      	movne	r0, #1
    2ea8:	4770      	bx	lr
    2eaa:	bf00      	nop
    2eac:	20000020 	.word	0x20000020

00002eb0 <nrfx_gpiote_channel_free>:
{
    2eb0:	4601      	mov	r1, r0
    return nrfx_flag32_free(&m_cb.available_channels_mask, channel);
    2eb2:	4801      	ldr	r0, [pc, #4]	; (2eb8 <nrfx_gpiote_channel_free+0x8>)
    2eb4:	f7ff bd22 	b.w	28fc <nrfx_flag32_free>
    2eb8:	20000070 	.word	0x20000070

00002ebc <nrfx_gpiote_channel_alloc>:
{
    2ebc:	4601      	mov	r1, r0
    return nrfx_flag32_alloc(&m_cb.available_channels_mask, p_channel);
    2ebe:	4801      	ldr	r0, [pc, #4]	; (2ec4 <nrfx_gpiote_channel_alloc+0x8>)
    2ec0:	f7ff bcf8 	b.w	28b4 <nrfx_flag32_alloc>
    2ec4:	20000070 	.word	0x20000070

00002ec8 <nrfx_gpiote_trigger_enable>:
    return m_cb.pin_flags[pin] & PIN_FLAG_TE_USED;
    2ec8:	f100 0208 	add.w	r2, r0, #8
    2ecc:	4b1d      	ldr	r3, [pc, #116]	; (2f44 <nrfx_gpiote_trigger_enable+0x7c>)
    2ece:	f833 3012 	ldrh.w	r3, [r3, r2, lsl #1]
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    2ed2:	069a      	lsls	r2, r3, #26
{
    2ed4:	b410      	push	{r4}
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    2ed6:	d51d      	bpl.n	2f14 <nrfx_gpiote_trigger_enable+0x4c>
    2ed8:	f013 0402 	ands.w	r4, r3, #2
    2edc:	d11a      	bne.n	2f14 <nrfx_gpiote_trigger_enable+0x4c>
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    2ede:	0b5b      	lsrs	r3, r3, #13
#endif

NRF_STATIC_INLINE nrf_gpiote_event_t nrf_gpiote_in_event_get(uint8_t index)
{
    NRFX_ASSERT(index < GPIOTE_CH_NUM);
    return (nrf_gpiote_event_t)NRFX_OFFSETOF(NRF_GPIOTE_Type, EVENTS_IN[index]);
    2ee0:	009a      	lsls	r2, r3, #2
    return ((uint32_t)p_reg + event);
    2ee2:	f102 4080 	add.w	r0, r2, #1073741824	; 0x40000000
    2ee6:	f500 40c2 	add.w	r0, r0, #24832	; 0x6100
    2eea:	f102 4280 	add.w	r2, r2, #1073741824	; 0x40000000
    2eee:	f502 42c0 	add.w	r2, r2, #24576	; 0x6000
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    2ef2:	6004      	str	r4, [r0, #0]
    2ef4:	6800      	ldr	r0, [r0, #0]
   p_reg->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event;
    2ef6:	f8d2 0510 	ldr.w	r0, [r2, #1296]	; 0x510
    2efa:	f040 0001 	orr.w	r0, r0, #1
    2efe:	f8c2 0510 	str.w	r0, [r2, #1296]	; 0x510
        if (int_enable)
    2f02:	b129      	cbz	r1, 2f10 <nrfx_gpiote_trigger_enable+0x48>
            nrf_gpiote_int_enable(NRF_GPIOTE, NRFX_BIT(ch));
    2f04:	2201      	movs	r2, #1
    2f06:	fa02 f303 	lsl.w	r3, r2, r3
    p_reg->INTENSET = mask;
    2f0a:	4a0f      	ldr	r2, [pc, #60]	; (2f48 <nrfx_gpiote_trigger_enable+0x80>)
    2f0c:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
}
    2f10:	bc10      	pop	{r4}
    2f12:	4770      	bx	lr
    nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    2f14:	f3c3 0382 	ubfx	r3, r3, #2, #3
    if (trigger == NRFX_GPIOTE_TRIGGER_LOW)
    2f18:	2b04      	cmp	r3, #4
    2f1a:	d00e      	beq.n	2f3a <nrfx_gpiote_trigger_enable+0x72>
    else if (trigger == NRFX_GPIOTE_TRIGGER_HIGH)
    2f1c:	2b05      	cmp	r3, #5
    2f1e:	d00e      	beq.n	2f3e <nrfx_gpiote_trigger_enable+0x76>
    return p_reg->IN;
    2f20:	f04f 43a0 	mov.w	r3, #1342177280	; 0x50000000
    2f24:	f8d3 1510 	ldr.w	r1, [r3, #1296]	; 0x510
    *p_pin = pin_number & 0x1F;
    2f28:	f000 031f 	and.w	r3, r0, #31
    return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL);
    2f2c:	40d9      	lsrs	r1, r3
    2f2e:	f001 0101 	and.w	r1, r1, #1
        sense = nrf_gpio_pin_read(pin) ? NRF_GPIO_PIN_SENSE_LOW : NRF_GPIO_PIN_SENSE_HIGH;
    2f32:	3102      	adds	r1, #2
}
    2f34:	bc10      	pop	{r4}
        nrf_gpio_cfg_sense_set(pin, get_initial_sense(pin));
    2f36:	f001 bc86 	b.w	4846 <nrf_gpio_cfg_sense_set>
        sense = NRF_GPIO_PIN_SENSE_LOW;
    2f3a:	2103      	movs	r1, #3
    2f3c:	e7fa      	b.n	2f34 <nrfx_gpiote_trigger_enable+0x6c>
        sense = NRF_GPIO_PIN_SENSE_HIGH;
    2f3e:	2102      	movs	r1, #2
    2f40:	e7f8      	b.n	2f34 <nrfx_gpiote_trigger_enable+0x6c>
    2f42:	bf00      	nop
    2f44:	20000020 	.word	0x20000020
    2f48:	40006000 	.word	0x40006000

00002f4c <nrfx_gpiote_trigger_disable>:
    return m_cb.pin_flags[pin] & PIN_FLAG_TE_USED;
    2f4c:	4b0e      	ldr	r3, [pc, #56]	; (2f88 <nrfx_gpiote_trigger_disable+0x3c>)
    2f4e:	f100 0208 	add.w	r2, r0, #8
    2f52:	f833 3012 	ldrh.w	r3, [r3, r2, lsl #1]
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    2f56:	0699      	lsls	r1, r3, #26
    2f58:	d513      	bpl.n	2f82 <nrfx_gpiote_trigger_disable+0x36>
    2f5a:	079a      	lsls	r2, r3, #30
    2f5c:	d411      	bmi.n	2f82 <nrfx_gpiote_trigger_disable+0x36>
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    2f5e:	0b5b      	lsrs	r3, r3, #13
        nrf_gpiote_int_disable(NRF_GPIOTE, NRFX_BIT(ch));
    2f60:	2201      	movs	r2, #1
    2f62:	409a      	lsls	r2, r3
    p_reg->INTENCLR = mask;
    2f64:	009b      	lsls	r3, r3, #2
    2f66:	4909      	ldr	r1, [pc, #36]	; (2f8c <nrfx_gpiote_trigger_disable+0x40>)
    2f68:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    2f6c:	f503 43c0 	add.w	r3, r3, #24576	; 0x6000
    2f70:	f8c1 2308 	str.w	r2, [r1, #776]	; 0x308
   p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk;
    2f74:	f8d3 2510 	ldr.w	r2, [r3, #1296]	; 0x510
    2f78:	f022 0203 	bic.w	r2, r2, #3
    2f7c:	f8c3 2510 	str.w	r2, [r3, #1296]	; 0x510
}
    2f80:	4770      	bx	lr
        nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE);
    2f82:	2100      	movs	r1, #0
    2f84:	f001 bc5f 	b.w	4846 <nrf_gpio_cfg_sense_set>
    2f88:	20000020 	.word	0x20000020
    2f8c:	40006000 	.word	0x40006000

00002f90 <nrfx_gpiote_pin_uninit>:
    return m_cb.pin_flags[pin] & PIN_FLAG_IN_USE;
    2f90:	4b0d      	ldr	r3, [pc, #52]	; (2fc8 <nrfx_gpiote_pin_uninit+0x38>)
    2f92:	f100 0208 	add.w	r2, r0, #8
{
    2f96:	b510      	push	{r4, lr}
    return m_cb.pin_flags[pin] & PIN_FLAG_IN_USE;
    2f98:	f813 3012 	ldrb.w	r3, [r3, r2, lsl #1]
    if (!pin_in_use(pin))
    2f9c:	07db      	lsls	r3, r3, #31
{
    2f9e:	4604      	mov	r4, r0
    if (!pin_in_use(pin))
    2fa0:	d50f      	bpl.n	2fc2 <nrfx_gpiote_pin_uninit+0x32>
    nrfx_gpiote_trigger_disable(pin);
    2fa2:	f7ff ffd3 	bl	2f4c <nrfx_gpiote_trigger_disable>
    pin_handler_trigger_uninit(pin);
    2fa6:	4620      	mov	r0, r4
    *p_pin = pin_number & 0x1F;
    2fa8:	f004 041f 	and.w	r4, r4, #31
    2fac:	f7ff fde6 	bl	2b7c <pin_handler_trigger_uninit>
    reg->PIN_CNF[pin_number] = cnf;
    2fb0:	f504 74e0 	add.w	r4, r4, #448	; 0x1c0
    2fb4:	f04f 43a0 	mov.w	r3, #1342177280	; 0x50000000
    2fb8:	2202      	movs	r2, #2
    2fba:	f843 2024 	str.w	r2, [r3, r4, lsl #2]
    2fbe:	4803      	ldr	r0, [pc, #12]	; (2fcc <nrfx_gpiote_pin_uninit+0x3c>)
}
    2fc0:	bd10      	pop	{r4, pc}
        return NRFX_ERROR_INVALID_PARAM;
    2fc2:	4803      	ldr	r0, [pc, #12]	; (2fd0 <nrfx_gpiote_pin_uninit+0x40>)
    2fc4:	e7fc      	b.n	2fc0 <nrfx_gpiote_pin_uninit+0x30>
    2fc6:	bf00      	nop
    2fc8:	20000020 	.word	0x20000020
    2fcc:	0bad0000 	.word	0x0bad0000
    2fd0:	0bad0004 	.word	0x0bad0004

00002fd4 <nrfx_gpiote_irq_handler>:
        call_handler(pin, gpiote_polarity_to_trigger(polarity));
    }
}

void nrfx_gpiote_irq_handler(void)
{
    2fd4:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    2fd8:	4b4e      	ldr	r3, [pc, #312]	; (3114 <nrfx_gpiote_irq_handler+0x140>)
    return p_reg->INTENSET & mask;
    2fda:	484f      	ldr	r0, [pc, #316]	; (3118 <nrfx_gpiote_irq_handler+0x144>)
    uint32_t i;
    nrf_gpiote_event_t event = NRF_GPIOTE_EVENT_IN_0;
    uint32_t mask = (uint32_t)NRF_GPIOTE_INT_IN0_MASK;

    /* collect status of all GPIOTE pin events. Processing is done once all are collected and cleared.*/
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    2fdc:	494f      	ldr	r1, [pc, #316]	; (311c <nrfx_gpiote_irq_handler+0x148>)
    uint32_t status = 0;
    2fde:	2600      	movs	r6, #0
{
    2fe0:	b085      	sub	sp, #20
    uint32_t mask = (uint32_t)NRF_GPIOTE_INT_IN0_MASK;
    2fe2:	2201      	movs	r2, #1
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    2fe4:	4634      	mov	r4, r6
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    2fe6:	681d      	ldr	r5, [r3, #0]
    {
        if (nrf_gpiote_event_check(NRF_GPIOTE, event) &&
    2fe8:	b135      	cbz	r5, 2ff8 <nrfx_gpiote_irq_handler+0x24>
    return p_reg->INTENSET & mask;
    2fea:	f8d0 5304 	ldr.w	r5, [r0, #772]	; 0x304
    2fee:	4215      	tst	r5, r2
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    2ff0:	bf1e      	ittt	ne
    2ff2:	601c      	strne	r4, [r3, #0]
    2ff4:	681d      	ldrne	r5, [r3, #0]
            nrf_gpiote_int_enable_check(NRF_GPIOTE, mask))
        {
            nrf_gpiote_event_clear(NRF_GPIOTE, event);
            status |= mask;
    2ff6:	4316      	orrne	r6, r2
        }
        mask <<= 1;
    2ff8:	3304      	adds	r3, #4
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    2ffa:	428b      	cmp	r3, r1
        mask <<= 1;
    2ffc:	ea4f 0242 	mov.w	r2, r2, lsl #1
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    3000:	d1f1      	bne.n	2fe6 <nrfx_gpiote_irq_handler+0x12>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    3002:	4f47      	ldr	r7, [pc, #284]	; (3120 <nrfx_gpiote_irq_handler+0x14c>)
    3004:	683b      	ldr	r3, [r7, #0]
         * in ascending order. */
        event = (nrf_gpiote_event_t)((uint32_t)event + sizeof(uint32_t));
    }

    /* handle PORT event */
    if (nrf_gpiote_event_check(NRF_GPIOTE, NRF_GPIOTE_EVENT_PORT))
    3006:	b1ab      	cbz	r3, 3034 <nrfx_gpiote_irq_handler+0x60>
        *p_masks = gpio_regs[i]->LATCH;
    3008:	f04f 45a0 	mov.w	r5, #1342177280	; 0x50000000
    300c:	f8d5 3520 	ldr.w	r3, [r5, #1312]	; 0x520
    3010:	9303      	str	r3, [sp, #12]
        gpio_regs[i]->LATCH = *p_masks;
    3012:	f8c5 3520 	str.w	r3, [r5, #1312]	; 0x520
__STATIC_INLINE void nrf_bitmask_bit_clear(uint32_t bit, void * p_mask)
{
    uint8_t * p_mask8 = (uint8_t *)p_mask;
    uint32_t byte_idx = BITMASK_BYTE_GET(bit);
    bit = BITMASK_RELBIT_GET(bit);
    p_mask8[byte_idx] &= ~(1 << bit);
    3016:	f10d 080c 	add.w	r8, sp, #12
    301a:	f04f 0901 	mov.w	r9, #1
            while (latch[i])
    301e:	9803      	ldr	r0, [sp, #12]
    3020:	b950      	cbnz	r0, 3038 <nrfx_gpiote_irq_handler+0x64>
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    3022:	6038      	str	r0, [r7, #0]
    3024:	683b      	ldr	r3, [r7, #0]
        *p_masks = gpio_regs[i]->LATCH;
    3026:	f8d5 3520 	ldr.w	r3, [r5, #1312]	; 0x520
    302a:	9303      	str	r3, [sp, #12]
        gpio_regs[i]->LATCH = *p_masks;
    302c:	f8c5 3520 	str.w	r3, [r5, #1312]	; 0x520
        if (latch[port_idx])
    3030:	2b00      	cmp	r3, #0
    3032:	d1f0      	bne.n	3016 <nrfx_gpiote_irq_handler+0x42>
        mask &= ~NRFX_BIT(ch);
    3034:	2401      	movs	r4, #1
    3036:	e068      	b.n	310a <nrfx_gpiote_irq_handler+0x136>
                uint32_t pin = NRF_CTZ(latch[i]);
    3038:	fa90 faa0 	rbit	sl, r0
    303c:	faba fa8a 	clz	sl, sl
                nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    3040:	4a38      	ldr	r2, [pc, #224]	; (3124 <nrfx_gpiote_irq_handler+0x150>)
    3042:	f10a 0308 	add.w	r3, sl, #8
    uint32_t byte_idx = BITMASK_BYTE_GET(bit);
    3046:	ea4f 0cda 	mov.w	ip, sl, lsr #3
    304a:	f832 1013 	ldrh.w	r1, [r2, r3, lsl #1]
    bit = BITMASK_RELBIT_GET(bit);
    304e:	f00a 0307 	and.w	r3, sl, #7
    p_mask8[byte_idx] &= ~(1 << bit);
    3052:	fa09 f203 	lsl.w	r2, r9, r3
    3056:	f818 300c 	ldrb.w	r3, [r8, ip]
    305a:	ea23 0302 	bic.w	r3, r3, r2
    305e:	f808 300c 	strb.w	r3, [r8, ip]
    3062:	ea4f 038a 	mov.w	r3, sl, lsl #2
    3066:	f103 43a0 	add.w	r3, r3, #1342177280	; 0x50000000
    306a:	f3c1 0482 	ubfx	r4, r1, #2, #3
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    306e:	f8d3 2700 	ldr.w	r2, [r3, #1792]	; 0x700
    if (is_level(trigger))
    3072:	06c8      	lsls	r0, r1, #27
                nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    3074:	46a3      	mov	fp, r4
                                   GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos);
    3076:	f3c2 4201 	ubfx	r2, r2, #16, #2
    if (is_level(trigger))
    307a:	d519      	bpl.n	30b0 <nrfx_gpiote_irq_handler+0xdc>
        call_handler(pin, trigger);
    307c:	4659      	mov	r1, fp
    307e:	4650      	mov	r0, sl
    3080:	9301      	str	r3, [sp, #4]
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    3082:	b2d4      	uxtb	r4, r2
    3084:	f7ff fd32 	bl	2aec <call_handler>
    3088:	9b01      	ldr	r3, [sp, #4]
    308a:	f8d3 3700 	ldr.w	r3, [r3, #1792]	; 0x700
        if (nrf_gpio_pin_sense_get(pin) == sense)
    308e:	f3c3 4301 	ubfx	r3, r3, #16, #2
    3092:	429c      	cmp	r4, r3
    3094:	d107      	bne.n	30a6 <nrfx_gpiote_irq_handler+0xd2>
            nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE);
    3096:	2100      	movs	r1, #0
    3098:	4650      	mov	r0, sl
    309a:	f001 fbd4 	bl	4846 <nrf_gpio_cfg_sense_set>
            nrf_gpio_cfg_sense_set(pin, sense);
    309e:	4621      	mov	r1, r4
    30a0:	4650      	mov	r0, sl
    30a2:	f001 fbd0 	bl	4846 <nrf_gpio_cfg_sense_set>
    reg->LATCH = (1 << pin_number);
    30a6:	fa09 f00a 	lsl.w	r0, r9, sl
    30aa:	f8c5 0520 	str.w	r0, [r5, #1312]	; 0x520
}
    30ae:	e7b6      	b.n	301e <nrfx_gpiote_irq_handler+0x4a>
                NRF_GPIO_PIN_SENSE_LOW : NRF_GPIO_PIN_SENSE_HIGH;
    30b0:	2a02      	cmp	r2, #2
        nrf_gpio_cfg_sense_set(pin, next_sense);
    30b2:	bf0c      	ite	eq
    30b4:	2103      	moveq	r1, #3
    30b6:	2102      	movne	r1, #2
    30b8:	4650      	mov	r0, sl
    30ba:	f001 fbc4 	bl	4846 <nrf_gpio_cfg_sense_set>
        if ((trigger == NRFX_GPIOTE_TRIGGER_TOGGLE) ||
    30be:	2c03      	cmp	r4, #3
    30c0:	d003      	beq.n	30ca <nrfx_gpiote_irq_handler+0xf6>
    30c2:	2a02      	cmp	r2, #2
    30c4:	d106      	bne.n	30d4 <nrfx_gpiote_irq_handler+0x100>
            (sense == NRF_GPIO_PIN_SENSE_HIGH && trigger == NRFX_GPIOTE_TRIGGER_LOTOHI) ||
    30c6:	2c01      	cmp	r4, #1
            (sense == NRF_GPIO_PIN_SENSE_LOW && trigger == NRFX_GPIOTE_TRIGGER_HITOLO))
    30c8:	d1ed      	bne.n	30a6 <nrfx_gpiote_irq_handler+0xd2>
            call_handler(pin, trigger);
    30ca:	4659      	mov	r1, fp
    30cc:	4650      	mov	r0, sl
    30ce:	f7ff fd0d 	bl	2aec <call_handler>
    30d2:	e7e8      	b.n	30a6 <nrfx_gpiote_irq_handler+0xd2>
            (sense == NRF_GPIO_PIN_SENSE_HIGH && trigger == NRFX_GPIOTE_TRIGGER_LOTOHI) ||
    30d4:	2a03      	cmp	r2, #3
    30d6:	d1e6      	bne.n	30a6 <nrfx_gpiote_irq_handler+0xd2>
            (sense == NRF_GPIO_PIN_SENSE_LOW && trigger == NRFX_GPIOTE_TRIGGER_HITOLO))
    30d8:	2c02      	cmp	r4, #2
    30da:	e7f5      	b.n	30c8 <nrfx_gpiote_irq_handler+0xf4>
        uint32_t ch = NRF_CTZ(mask);
    30dc:	fa96 f3a6 	rbit	r3, r6
    30e0:	fab3 f383 	clz	r3, r3
        mask &= ~NRFX_BIT(ch);
    30e4:	fa04 f203 	lsl.w	r2, r4, r3
    30e8:	009b      	lsls	r3, r3, #2
    30ea:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    30ee:	f503 43c0 	add.w	r3, r3, #24576	; 0x6000
    30f2:	ea26 0602 	bic.w	r6, r6, r2
    return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
    30f6:	f8d3 0510 	ldr.w	r0, [r3, #1296]	; 0x510
    return (nrf_gpiote_polarity_t)((p_reg->CONFIG[idx] & GPIOTE_CONFIG_POLARITY_Msk) >>
    30fa:	f8d3 1510 	ldr.w	r1, [r3, #1296]	; 0x510
        call_handler(pin, gpiote_polarity_to_trigger(polarity));
    30fe:	f3c0 2004 	ubfx	r0, r0, #8, #5
    3102:	f3c1 4101 	ubfx	r1, r1, #16, #2
    3106:	f7ff fcf1 	bl	2aec <call_handler>
    while (mask)
    310a:	2e00      	cmp	r6, #0
    310c:	d1e6      	bne.n	30dc <nrfx_gpiote_irq_handler+0x108>
        port_event_handle();
    }

    /* Process pin events. */
    gpiote_evt_handle(status);
}
    310e:	b005      	add	sp, #20
    3110:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    3114:	40006100 	.word	0x40006100
    3118:	40006000 	.word	0x40006000
    311c:	40006120 	.word	0x40006120
    3120:	4000617c 	.word	0x4000617c
    3124:	20000020 	.word	0x20000020

00003128 <nrfx_ppi_channel_alloc>:
    nrfx_flag32_init(&m_groups_allocated, NRFX_PPI_ALL_APP_GROUPS_MASK);
}


nrfx_err_t nrfx_ppi_channel_alloc(nrf_ppi_channel_t * p_channel)
{
    3128:	4601      	mov	r1, r0
    return nrfx_flag32_alloc(&m_channels_allocated, (uint8_t *)p_channel);
    312a:	4801      	ldr	r0, [pc, #4]	; (3130 <nrfx_ppi_channel_alloc+0x8>)
    312c:	f7ff bbc2 	b.w	28b4 <nrfx_flag32_alloc>
    3130:	2000007c 	.word	0x2000007c

00003134 <nrfx_pwm_init>:

nrfx_err_t nrfx_pwm_init(nrfx_pwm_t const *        p_instance,
                         nrfx_pwm_config_t const * p_config,
                         nrfx_pwm_handler_t        handler,
                         void *                    p_context)
{
    3134:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    NRFX_ASSERT(p_config);

    nrfx_err_t err_code;

    pwm_control_block_t * p_cb  = &m_cb[p_instance->drv_inst_idx];
    3138:	7905      	ldrb	r5, [r0, #4]

    if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED)
    313a:	4c45      	ldr	r4, [pc, #276]	; (3250 <nrfx_pwm_init+0x11c>)
    313c:	260c      	movs	r6, #12
    313e:	436e      	muls	r6, r5
    3140:	19a7      	adds	r7, r4, r6
{
    3142:	b085      	sub	sp, #20
    if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED)
    3144:	f897 c008 	ldrb.w	ip, [r7, #8]
    3148:	f1bc 0f00 	cmp.w	ip, #0
    314c:	d17e      	bne.n	324c <nrfx_pwm_init+0x118>
        return err_code;
    }

    p_cb->handler = handler;
    p_cb->p_context = p_context;
    p_cb->skip_gpio_cfg = p_config->skip_gpio_cfg;
    314e:	f891 e00c 	ldrb.w	lr, [r1, #12]
    p_cb->handler = handler;
    3152:	51a2      	str	r2, [r4, r6]
    p_cb->p_context = p_context;
    3154:	f891 900d 	ldrb.w	r9, [r1, #13]
    3158:	607b      	str	r3, [r7, #4]
    p_cb->skip_gpio_cfg = p_config->skip_gpio_cfg;
    315a:	f887 e00a 	strb.w	lr, [r7, #10]
    if (p_config->skip_gpio_cfg && p_config->skip_psel_cfg)
    315e:	f1be 0f00 	cmp.w	lr, #0
    3162:	d032      	beq.n	31ca <nrfx_pwm_init+0x96>
    3164:	f1b9 0f00 	cmp.w	r9, #0
    3168:	d02f      	beq.n	31ca <nrfx_pwm_init+0x96>

    configure_pins(p_instance, p_config);

    nrf_pwm_enable(p_instance->p_registers);
    316a:	6800      	ldr	r0, [r0, #0]
}
#endif // defined(DPPI_PRESENT)

NRF_STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_reg)
{
    p_reg->ENABLE = (PWM_ENABLE_ENABLE_Enabled << PWM_ENABLE_ENABLE_Pos);
    316c:	2301      	movs	r3, #1
    316e:	f8c0 3500 	str.w	r3, [r0, #1280]	; 0x500
    nrf_pwm_configure(p_instance->p_registers,
    3172:	798e      	ldrb	r6, [r1, #6]
    3174:	890b      	ldrh	r3, [r1, #8]
                                         nrf_pwm_mode_t mode,
                                         uint16_t       top_value)
{
    NRFX_ASSERT(top_value <= PWM_COUNTERTOP_COUNTERTOP_Msk);

    p_reg->PRESCALER  = base_clock;
    3176:	794f      	ldrb	r7, [r1, #5]
    3178:	f8c0 750c 	str.w	r7, [r0, #1292]	; 0x50c
    p_reg->MODE       = mode;
    317c:	f8c0 6504 	str.w	r6, [r0, #1284]	; 0x504
    p_reg->COUNTERTOP = top_value;
    3180:	f8c0 3508 	str.w	r3, [r0, #1288]	; 0x508

NRF_STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type *     p_reg,
                                           nrf_pwm_dec_load_t dec_load,
                                           nrf_pwm_dec_step_t dec_step)
{
    p_reg->DECODER = ((uint32_t)dec_load << PWM_DECODER_LOAD_Pos) |
    3184:	894b      	ldrh	r3, [r1, #10]
    3186:	f8c0 3510 	str.w	r3, [r0, #1296]	; 0x510
    p_reg->SHORTS = mask;
    318a:	2300      	movs	r3, #0
    318c:	f8c0 3200 	str.w	r3, [r0, #512]	; 0x200
    p_reg->INTEN = mask;
    3190:	f8c0 3300 	str.w	r3, [r0, #768]	; 0x300
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3194:	f8c0 311c 	str.w	r3, [r0, #284]	; 0x11c
    3198:	f8d0 111c 	ldr.w	r1, [r0, #284]	; 0x11c
    319c:	f8c0 3110 	str.w	r3, [r0, #272]	; 0x110
    31a0:	f8d0 1110 	ldr.w	r1, [r0, #272]	; 0x110
    31a4:	f8c0 3114 	str.w	r3, [r0, #276]	; 0x114
    31a8:	f8d0 1114 	ldr.w	r1, [r0, #276]	; 0x114
    31ac:	f8c0 3104 	str.w	r3, [r0, #260]	; 0x104
    31b0:	f8d0 3104 	ldr.w	r3, [r0, #260]	; 0x104
    // handler is not used.
#if defined(USE_DMA_ISSUE_WORKAROUND)
    NRFX_IRQ_PRIORITY_SET(DMA_ISSUE_EGU_IRQn, p_config->irq_priority);
    NRFX_IRQ_ENABLE(DMA_ISSUE_EGU_IRQn);
#else
    if (p_cb->handler)
    31b4:	2a00      	cmp	r2, #0
    31b6:	d144      	bne.n	3242 <nrfx_pwm_init+0x10e>
        NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(p_instance->p_registers),
            p_config->irq_priority);
        NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_instance->p_registers));
    }

    p_cb->state = NRFX_DRV_STATE_INITIALIZED;
    31b8:	230c      	movs	r3, #12
    31ba:	fb03 4405 	mla	r4, r3, r5, r4

    err_code = NRFX_SUCCESS;
    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
    31be:	4825      	ldr	r0, [pc, #148]	; (3254 <nrfx_pwm_init+0x120>)
    p_cb->state = NRFX_DRV_STATE_INITIALIZED;
    31c0:	2301      	movs	r3, #1
    31c2:	7223      	strb	r3, [r4, #8]
}
    31c4:	b005      	add	sp, #20
    31c6:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    31ca:	f101 3cff 	add.w	ip, r1, #4294967295
    31ce:	466b      	mov	r3, sp
    31d0:	f101 0b03 	add.w	fp, r1, #3
    31d4:	f04f 48a0 	mov.w	r8, #1342177280	; 0x50000000
        uint8_t output_pin = p_config->output_pins[i];
    31d8:	f81c 7f01 	ldrb.w	r7, [ip, #1]!
        if (output_pin != NRFX_PWM_PIN_NOT_USED)
    31dc:	2fff      	cmp	r7, #255	; 0xff
    31de:	d02c      	beq.n	323a <nrfx_pwm_init+0x106>
            out_pins[i]   = output_pin & ~NRFX_PWM_PIN_INVERTED;
    31e0:	f027 0680 	bic.w	r6, r7, #128	; 0x80
    31e4:	601e      	str	r6, [r3, #0]
            if (!p_config->skip_gpio_cfg)
    31e6:	f1be 0f00 	cmp.w	lr, #0
    31ea:	d111      	bne.n	3210 <nrfx_pwm_init+0xdc>
    if (value == 0)
    31ec:	f007 061f 	and.w	r6, r7, #31
    31f0:	f04f 0a01 	mov.w	sl, #1
    31f4:	fa0a fa06 	lsl.w	sl, sl, r6
    reg->PIN_CNF[pin_number] = cnf;
    31f8:	f506 76e0 	add.w	r6, r6, #448	; 0x1c0
    if (value == 0)
    31fc:	063f      	lsls	r7, r7, #24
    reg->PIN_CNF[pin_number] = cnf;
    31fe:	f04f 0703 	mov.w	r7, #3
    p_reg->OUTCLR = clr_mask;
    3202:	bf54      	ite	pl
    3204:	f8c8 a50c 	strpl.w	sl, [r8, #1292]	; 0x50c
    p_reg->OUTSET = set_mask;
    3208:	f8c8 a508 	strmi.w	sl, [r8, #1288]	; 0x508
    reg->PIN_CNF[pin_number] = cnf;
    320c:	f848 7026 	str.w	r7, [r8, r6, lsl #2]
    for (i = 0; i < NRF_PWM_CHANNEL_COUNT; ++i)
    3210:	45dc      	cmp	ip, fp
    3212:	f103 0304 	add.w	r3, r3, #4
    3216:	d1df      	bne.n	31d8 <nrfx_pwm_init+0xa4>
    if (!p_config->skip_psel_cfg)
    3218:	f1b9 0f00 	cmp.w	r9, #0
    321c:	d1a5      	bne.n	316a <nrfx_pwm_init+0x36>
    321e:	6803      	ldr	r3, [r0, #0]
        p_reg->PSEL.OUT[i] = out_pins[i];
    3220:	9e00      	ldr	r6, [sp, #0]
    3222:	f8c3 6560 	str.w	r6, [r3, #1376]	; 0x560
    3226:	9e01      	ldr	r6, [sp, #4]
    3228:	f8c3 6564 	str.w	r6, [r3, #1380]	; 0x564
    322c:	9e02      	ldr	r6, [sp, #8]
    322e:	f8c3 6568 	str.w	r6, [r3, #1384]	; 0x568
    3232:	9e03      	ldr	r6, [sp, #12]
    3234:	f8c3 656c 	str.w	r6, [r3, #1388]	; 0x56c
    for (i = 0; i < NRF_PWM_CHANNEL_COUNT; ++i)
    3238:	e797      	b.n	316a <nrfx_pwm_init+0x36>
            out_pins[i] = NRF_PWM_PIN_NOT_CONNECTED;
    323a:	f04f 36ff 	mov.w	r6, #4294967295
    323e:	601e      	str	r6, [r3, #0]
    3240:	e7e6      	b.n	3210 <nrfx_pwm_init+0xdc>
        NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_instance->p_registers));
    3242:	f340 3007 	sbfx	r0, r0, #12, #8
    3246:	f7fd febb 	bl	fc0 <arch_irq_enable>
    324a:	e7b5      	b.n	31b8 <nrfx_pwm_init+0x84>
        return err_code;
    324c:	4802      	ldr	r0, [pc, #8]	; (3258 <nrfx_pwm_init+0x124>)
    324e:	e7b9      	b.n	31c4 <nrfx_pwm_init+0x90>
    3250:	20000280 	.word	0x20000280
    3254:	0bad0000 	.word	0x0bad0000
    3258:	0bad0005 	.word	0x0bad0005

0000325c <nrfx_pwm_simple_playback>:

uint32_t nrfx_pwm_simple_playback(nrfx_pwm_t const *         p_instance,
                                  nrf_pwm_sequence_t const * p_sequence,
                                  uint16_t                   playback_count,
                                  uint32_t                   flags)
{
    325c:	b4f0      	push	{r4, r5, r6, r7}
    325e:	460d      	mov	r5, r1
    pwm_control_block_t * p_cb  = &m_cb[p_instance->drv_inst_idx];
    3260:	7901      	ldrb	r1, [r0, #4]
    NRFX_ASSERT(playback_count > 0);
    NRFX_ASSERT(nrfx_is_in_ram(p_sequence->values.p_raw));

    // To take advantage of the looping mechanism, we need to use both sequences
    // (single sequence can be played back only once).
    nrf_pwm_sequence_set(p_instance->p_registers, 0, p_sequence);
    3262:	6800      	ldr	r0, [r0, #0]
    p_reg->SEQ[seq_id].PTR = (uint32_t)p_values;
    3264:	f8d5 c000 	ldr.w	ip, [r5]
    p_reg->SEQ[seq_id].CNT = length;
    3268:	88af      	ldrh	r7, [r5, #4]
    nrf_pwm_seq_refresh_set(  p_reg, seq_id, p_seq->repeats);
    326a:	68ae      	ldr	r6, [r5, #8]
    p_reg->SEQ[seq_id].PTR = (uint32_t)p_values;
    326c:	f8c0 c520 	str.w	ip, [r0, #1312]	; 0x520
{
    3270:	461c      	mov	r4, r3
    pwm_control_block_t * p_cb  = &m_cb[p_instance->drv_inst_idx];
    3272:	4b18      	ldr	r3, [pc, #96]	; (32d4 <nrfx_pwm_simple_playback+0x78>)
    p_reg->SEQ[seq_id].CNT = length;
    3274:	f8c0 7524 	str.w	r7, [r0, #1316]	; 0x524
    3278:	eb01 0141 	add.w	r1, r1, r1, lsl #1
    327c:	eb03 0181 	add.w	r1, r3, r1, lsl #2
    nrf_pwm_seq_end_delay_set(p_reg, seq_id, p_seq->end_delay);
    3280:	68eb      	ldr	r3, [r5, #12]
    p_reg->SEQ[seq_id].REFRESH  = refresh;
    3282:	f8c0 6528 	str.w	r6, [r0, #1320]	; 0x528
    p_reg->SEQ[seq_id].ENDDELAY = end_delay;
    3286:	f8c0 352c 	str.w	r3, [r0, #1324]	; 0x52c
    p_reg->SEQ[seq_id].PTR = (uint32_t)p_values;
    328a:	f8c0 c540 	str.w	ip, [r0, #1344]	; 0x540
    p_reg->SEQ[seq_id].CNT = length;
    328e:	f8c0 7544 	str.w	r7, [r0, #1348]	; 0x544
    p_reg->SEQ[seq_id].REFRESH  = refresh;
    3292:	f8c0 6548 	str.w	r6, [r0, #1352]	; 0x548
    p_reg->SEQ[seq_id].ENDDELAY = end_delay;
    3296:	f8c0 354c 	str.w	r3, [r0, #1356]	; 0x54c
    nrf_pwm_sequence_set(p_instance->p_registers, 1, p_sequence);
    bool odd = (playback_count & 1);
    329a:	f002 0301 	and.w	r3, r2, #1
}

NRF_STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_reg,
                                        uint16_t       loop_count)
{
    p_reg->LOOP = loop_count;
    329e:	eb03 0252 	add.w	r2, r3, r2, lsr #1
    32a2:	f8c0 2514 	str.w	r2, [r0, #1300]	; 0x514
    nrf_pwm_loop_set(p_instance->p_registers,
        (playback_count / 2) + (odd ? 1 : 0));

    uint32_t shorts_mask;
    if (flags & NRFX_PWM_FLAG_STOP)
    32a6:	07e2      	lsls	r2, r4, #31
    32a8:	d411      	bmi.n	32ce <nrfx_pwm_simple_playback+0x72>
    {
        shorts_mask = NRF_PWM_SHORT_LOOPSDONE_STOP_MASK;
    }
    else if (flags & NRFX_PWM_FLAG_LOOP)
    32aa:	f014 0202 	ands.w	r2, r4, #2
    32ae:	d003      	beq.n	32b8 <nrfx_pwm_simple_playback+0x5c>
    {
        shorts_mask = odd ? NRF_PWM_SHORT_LOOPSDONE_SEQSTART1_MASK
                          : NRF_PWM_SHORT_LOOPSDONE_SEQSTART0_MASK;
    32b0:	2b00      	cmp	r3, #0
    32b2:	bf14      	ite	ne
    32b4:	2208      	movne	r2, #8
    32b6:	2204      	moveq	r2, #4
                  __func__,
                  p_sequence->length);
    NRFX_LOG_DEBUG("Sequence data:");
    NRFX_LOG_HEXDUMP_DEBUG((uint8_t *)p_sequence->values.p_raw,
                           p_sequence->length * sizeof(uint16_t));
    return start_playback(p_instance, p_cb, flags,
    32b8:	2b00      	cmp	r3, #0
    p_reg->SHORTS = mask;
    32ba:	f8c0 2200 	str.w	r2, [r0, #512]	; 0x200
    32be:	bf18      	it	ne
    32c0:	230c      	movne	r3, #12
    32c2:	b2e2      	uxtb	r2, r4
    32c4:	bf08      	it	eq
    32c6:	2308      	moveq	r3, #8
        odd ? NRF_PWM_TASK_SEQSTART1 : NRF_PWM_TASK_SEQSTART0);
}
    32c8:	bcf0      	pop	{r4, r5, r6, r7}
    return start_playback(p_instance, p_cb, flags,
    32ca:	f001 baca 	b.w	4862 <start_playback.isra.0>
        shorts_mask = NRF_PWM_SHORT_LOOPSDONE_STOP_MASK;
    32ce:	2210      	movs	r2, #16
    32d0:	e7f2      	b.n	32b8 <nrfx_pwm_simple_playback+0x5c>
    32d2:	bf00      	nop
    32d4:	20000280 	.word	0x20000280

000032d8 <nrfx_pwm_is_stopped>:

    bool ret_val = false;

    // If the event handler is used (interrupts are enabled), the state will
    // be changed in interrupt handler when the STOPPED event occurs.
    if (p_cb->state != NRFX_DRV_STATE_POWERED_ON)
    32d8:	4b08      	ldr	r3, [pc, #32]	; (32fc <nrfx_pwm_is_stopped+0x24>)
    pwm_control_block_t * p_cb  = &m_cb[p_instance->drv_inst_idx];
    32da:	7902      	ldrb	r2, [r0, #4]
    if (p_cb->state != NRFX_DRV_STATE_POWERED_ON)
    32dc:	210c      	movs	r1, #12
    32de:	fb01 3202 	mla	r2, r1, r2, r3
    {
        ret_val = true;
    }
    // If interrupts are disabled, we must check the STOPPED event here.
    if (nrf_pwm_event_check(p_instance->p_registers, NRF_PWM_EVENT_STOPPED))
    32e2:	6801      	ldr	r1, [r0, #0]
    if (p_cb->state != NRFX_DRV_STATE_POWERED_ON)
    32e4:	7a13      	ldrb	r3, [r2, #8]
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    32e6:	f8d1 1104 	ldr.w	r1, [r1, #260]	; 0x104
    32ea:	b2db      	uxtb	r3, r3
    if (nrf_pwm_event_check(p_instance->p_registers, NRF_PWM_EVENT_STOPPED))
    32ec:	b919      	cbnz	r1, 32f6 <nrfx_pwm_is_stopped+0x1e>
    if (p_cb->state != NRFX_DRV_STATE_POWERED_ON)
    32ee:	1e98      	subs	r0, r3, #2
    32f0:	bf18      	it	ne
    32f2:	2001      	movne	r0, #1
    32f4:	4770      	bx	lr
    {
        p_cb->state = NRFX_DRV_STATE_INITIALIZED;
    32f6:	2001      	movs	r0, #1
    32f8:	7210      	strb	r0, [r2, #8]
        ret_val = true;
    }

    NRFX_LOG_INFO("%s returned %d.", __func__, ret_val);
    return ret_val;
}
    32fa:	4770      	bx	lr
    32fc:	20000280 	.word	0x20000280

00003300 <_DoInit>:
                      _DoInit();                                                                     \
                    }                                                                                \
                  } while (0);                                                                       \
                }

static void _DoInit(void) {
    3300:	b510      	push	{r4, lr}
  volatile SEGGER_RTT_CB* p;   // Volatile to make sure that compiler cannot change the order of accesses to the control block
  //
  // Initialize control block
  //
  p                     = (volatile SEGGER_RTT_CB*)((char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access control block uncached so that nothing in the cache ever becomes dirty and all changes are visible in HW directly
  p->MaxNumUpBuffers    = SEGGER_RTT_MAX_NUM_UP_BUFFERS;
    3302:	4c14      	ldr	r4, [pc, #80]	; (3354 <_DoInit+0x54>)
  p->MaxNumDownBuffers  = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS;
  //
  // Initialize up buffer 0
  //
  p->aUp[0].sName         = "Terminal";
    3304:	4a14      	ldr	r2, [pc, #80]	; (3358 <_DoInit+0x58>)
  //
  // Finish initialization of the control block.
  // Copy Id string in three steps to make sure "SEGGER RTT" is not found
  // in initializer memory (usually flash) by J-Link
  //
  STRCPY((char*)&p->acID[7], "RTT");
    3306:	4915      	ldr	r1, [pc, #84]	; (335c <_DoInit+0x5c>)
  p->MaxNumUpBuffers    = SEGGER_RTT_MAX_NUM_UP_BUFFERS;
    3308:	2303      	movs	r3, #3
    330a:	6123      	str	r3, [r4, #16]
  p->MaxNumDownBuffers  = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS;
    330c:	6163      	str	r3, [r4, #20]
  p->aUp[0].pBuffer       = _acUpBuffer;
    330e:	4b14      	ldr	r3, [pc, #80]	; (3360 <_DoInit+0x60>)
  p->aUp[0].sName         = "Terminal";
    3310:	61a2      	str	r2, [r4, #24]
  p->aUp[0].pBuffer       = _acUpBuffer;
    3312:	61e3      	str	r3, [r4, #28]
  p->aUp[0].SizeOfBuffer  = BUFFER_SIZE_UP;
    3314:	f44f 6380 	mov.w	r3, #1024	; 0x400
    3318:	6223      	str	r3, [r4, #32]
  p->aUp[0].RdOff         = 0u;
    331a:	2300      	movs	r3, #0
    331c:	62a3      	str	r3, [r4, #40]	; 0x28
  p->aUp[0].WrOff         = 0u;
    331e:	6263      	str	r3, [r4, #36]	; 0x24
  p->aUp[0].Flags         = SEGGER_RTT_MODE_DEFAULT;
    3320:	62e3      	str	r3, [r4, #44]	; 0x2c
  p->aDown[0].sName         = "Terminal";
    3322:	6622      	str	r2, [r4, #96]	; 0x60
  p->aDown[0].pBuffer       = _acDownBuffer;
    3324:	4a0f      	ldr	r2, [pc, #60]	; (3364 <_DoInit+0x64>)
    3326:	6662      	str	r2, [r4, #100]	; 0x64
  STRCPY((char*)&p->acID[7], "RTT");
    3328:	1de0      	adds	r0, r4, #7
  p->aDown[0].SizeOfBuffer  = BUFFER_SIZE_DOWN;
    332a:	2210      	movs	r2, #16
    332c:	66a2      	str	r2, [r4, #104]	; 0x68
  p->aDown[0].RdOff         = 0u;
    332e:	6723      	str	r3, [r4, #112]	; 0x70
  p->aDown[0].WrOff         = 0u;
    3330:	66e3      	str	r3, [r4, #108]	; 0x6c
  p->aDown[0].Flags         = SEGGER_RTT_MODE_DEFAULT;
    3332:	6763      	str	r3, [r4, #116]	; 0x74
  STRCPY((char*)&p->acID[7], "RTT");
    3334:	f001 f80e 	bl	4354 <strcpy>
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
    3338:	f3bf 8f5f 	dmb	sy
  STRCPY((char*)&p->acID[0], "SEGGER");
    333c:	490a      	ldr	r1, [pc, #40]	; (3368 <_DoInit+0x68>)
    333e:	4620      	mov	r0, r4
    3340:	f001 f808 	bl	4354 <strcpy>
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
    3344:	f3bf 8f5f 	dmb	sy
  p->acID[6] = ' ';
    3348:	2320      	movs	r3, #32
    334a:	71a3      	strb	r3, [r4, #6]
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
    334c:	f3bf 8f5f 	dmb	sy
}
    3350:	bd10      	pop	{r4, pc}
    3352:	bf00      	nop
    3354:	2000028c 	.word	0x2000028c
    3358:	00004f39 	.word	0x00004f39
    335c:	00004f42 	.word	0x00004f42
    3360:	2000037f 	.word	0x2000037f
    3364:	2000036f 	.word	0x2000036f
    3368:	00004f46 	.word	0x00004f46

0000336c <SEGGER_RTT_WriteNoLock>:
*    (1) Data is stored according to buffer flags.
*    (2) For performance reasons this function does not call Init()
*        and may only be called after RTT has been initialized.
*        Either by calling SEGGER_RTT_Init() or calling another RTT API function first.
*/
unsigned SEGGER_RTT_WriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) {
    336c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
  SEGGER_RTT_BUFFER_UP* pRing;
  //
  // Get "to-host" ring buffer.
  //
  pData = (const char *)pBuffer;
  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
    336e:	4c18      	ldr	r4, [pc, #96]	; (33d0 <SEGGER_RTT_WriteNoLock+0x64>)
    3370:	2318      	movs	r3, #24
    3372:	fb00 3503 	mla	r5, r0, r3, r3
  //
  // How we output depends upon the mode...
  //
  switch (pRing->Flags) {
    3376:	fb03 4000 	mla	r0, r3, r0, r4
  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
    337a:	4425      	add	r5, r4
  switch (pRing->Flags) {
    337c:	6ac4      	ldr	r4, [r0, #44]	; 0x2c
    337e:	2c01      	cmp	r4, #1
unsigned SEGGER_RTT_WriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) {
    3380:	460f      	mov	r7, r1
    3382:	4616      	mov	r6, r2
  switch (pRing->Flags) {
    3384:	d00f      	beq.n	33a6 <SEGGER_RTT_WriteNoLock+0x3a>
    3386:	2c02      	cmp	r4, #2
    3388:	d01a      	beq.n	33c0 <SEGGER_RTT_WriteNoLock+0x54>
    338a:	b9f4      	cbnz	r4, 33ca <SEGGER_RTT_WriteNoLock+0x5e>
  case SEGGER_RTT_MODE_NO_BLOCK_SKIP:
    //
    // If we are in skip mode and there is no space for the whole
    // of this output, don't bother.
    //
    Avail = _GetAvailWriteSpace(pRing);
    338c:	4628      	mov	r0, r5
    338e:	f001 faa1 	bl	48d4 <_GetAvailWriteSpace>
    if (Avail < NumBytes) {
    3392:	4286      	cmp	r6, r0
    3394:	d805      	bhi.n	33a2 <SEGGER_RTT_WriteNoLock+0x36>
      Status = 0u;
    } else {
      Status = NumBytes;
      _WriteNoCheck(pRing, pData, NumBytes);
    3396:	4632      	mov	r2, r6
    3398:	4639      	mov	r1, r7
    339a:	4628      	mov	r0, r5
    339c:	f001 faa8 	bl	48f0 <_WriteNoCheck>
    33a0:	4634      	mov	r4, r6
  }
  //
  // Finish up.
  //
  return Status;
}
    33a2:	4620      	mov	r0, r4
    33a4:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    Avail = _GetAvailWriteSpace(pRing);
    33a6:	4628      	mov	r0, r5
    33a8:	f001 fa94 	bl	48d4 <_GetAvailWriteSpace>
    Status = Avail < NumBytes ? Avail : NumBytes;
    33ac:	4286      	cmp	r6, r0
    33ae:	4634      	mov	r4, r6
    33b0:	bf28      	it	cs
    33b2:	4604      	movcs	r4, r0
    _WriteNoCheck(pRing, pData, Status);
    33b4:	4622      	mov	r2, r4
    33b6:	4639      	mov	r1, r7
    33b8:	4628      	mov	r0, r5
    33ba:	f001 fa99 	bl	48f0 <_WriteNoCheck>
    break;
    33be:	e7f0      	b.n	33a2 <SEGGER_RTT_WriteNoLock+0x36>
    Status = _WriteBlocking(pRing, pData, NumBytes);
    33c0:	4628      	mov	r0, r5
}
    33c2:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
    Status = _WriteBlocking(pRing, pData, NumBytes);
    33c6:	f001 bab1 	b.w	492c <_WriteBlocking>
  switch (pRing->Flags) {
    33ca:	2400      	movs	r4, #0
  return Status;
    33cc:	e7e9      	b.n	33a2 <SEGGER_RTT_WriteNoLock+0x36>
    33ce:	bf00      	nop
    33d0:	2000028c 	.word	0x2000028c

000033d4 <init_idle_thread>:
} /* LCOV_EXCL_LINE ... because we just dumped final coverage data */

#if defined(CONFIG_MULTITHREADING)
__boot_func
static void init_idle_thread(int i)
{
    33d4:	b530      	push	{r4, r5, lr}
	snprintk(tname, 8, "idle %02d", i);
#else
	char *tname = NULL;
#endif /* CONFIG_THREAD_NAME */

	z_setup_new_thread(thread, stack,
    33d6:	2300      	movs	r3, #0
{
    33d8:	b087      	sub	sp, #28
	z_setup_new_thread(thread, stack,
    33da:	2201      	movs	r2, #1
    33dc:	e9cd 2304 	strd	r2, r3, [sp, #16]
    33e0:	220f      	movs	r2, #15
    33e2:	e9cd 3202 	strd	r3, r2, [sp, #8]
	struct k_thread *thread = &z_idle_threads[i];
    33e6:	4c0d      	ldr	r4, [pc, #52]	; (341c <init_idle_thread+0x48>)
			  CONFIG_IDLE_STACK_SIZE, idle, &_kernel.cpus[i],
    33e8:	4a0d      	ldr	r2, [pc, #52]	; (3420 <init_idle_thread+0x4c>)
	z_setup_new_thread(thread, stack,
    33ea:	9301      	str	r3, [sp, #4]
    33ec:	490d      	ldr	r1, [pc, #52]	; (3424 <init_idle_thread+0x50>)
			  CONFIG_IDLE_STACK_SIZE, idle, &_kernel.cpus[i],
    33ee:	2318      	movs	r3, #24
	struct k_thread *thread = &z_idle_threads[i];
    33f0:	eb04 14c0 	add.w	r4, r4, r0, lsl #7
			  CONFIG_IDLE_STACK_SIZE, idle, &_kernel.cpus[i],
    33f4:	fb03 2300 	mla	r3, r3, r0, r2
	z_setup_new_thread(thread, stack,
    33f8:	f44f 75b0 	mov.w	r5, #352	; 0x160
    33fc:	9300      	str	r3, [sp, #0]
    33fe:	fb05 1100 	mla	r1, r5, r0, r1
    3402:	4b09      	ldr	r3, [pc, #36]	; (3428 <init_idle_thread+0x54>)
    3404:	f44f 72a0 	mov.w	r2, #320	; 0x140
    3408:	4620      	mov	r0, r4
    340a:	f000 f8a5 	bl	3558 <z_setup_new_thread>
	SYS_PORT_TRACING_FUNC(k_thread, sched_resume, thread);
}

static inline void z_mark_thread_as_started(struct k_thread *thread)
{
	thread->base.thread_state &= ~_THREAD_PRESTART;
    340e:	7b63      	ldrb	r3, [r4, #13]
    3410:	f023 0304 	bic.w	r3, r3, #4
    3414:	7363      	strb	r3, [r4, #13]
	z_mark_thread_as_started(thread);

#ifdef CONFIG_SMP
	thread->base.is_idle = 1U;
#endif
}
    3416:	b007      	add	sp, #28
    3418:	bd30      	pop	{r4, r5, pc}
    341a:	bf00      	nop
    341c:	200000b8 	.word	0x200000b8
    3420:	20000334 	.word	0x20000334
    3424:	20000ba0 	.word	0x20000ba0
    3428:	00003679 	.word	0x00003679

0000342c <bg_thread_main>:
{
    342c:	b508      	push	{r3, lr}
	z_sys_post_kernel = true;
    342e:	4b0a      	ldr	r3, [pc, #40]	; (3458 <bg_thread_main+0x2c>)
    3430:	2201      	movs	r2, #1
	z_sys_init_run_level(_SYS_INIT_LEVEL_POST_KERNEL);
    3432:	2002      	movs	r0, #2
	z_sys_post_kernel = true;
    3434:	701a      	strb	r2, [r3, #0]
	z_sys_init_run_level(_SYS_INIT_LEVEL_POST_KERNEL);
    3436:	f000 fe13 	bl	4060 <z_sys_init_run_level>
	boot_banner();
    343a:	f000 fe05 	bl	4048 <boot_banner>
	z_sys_init_run_level(_SYS_INIT_LEVEL_APPLICATION);
    343e:	2003      	movs	r0, #3
    3440:	f000 fe0e 	bl	4060 <z_sys_init_run_level>
	z_init_static_threads();
    3444:	f000 f8ba 	bl	35bc <z_init_static_threads>
	main();
    3448:	f7fc ffc2 	bl	3d0 <main>
	z_main_thread.base.user_options &= ~K_ESSENTIAL;
    344c:	4a03      	ldr	r2, [pc, #12]	; (345c <bg_thread_main+0x30>)
    344e:	7b13      	ldrb	r3, [r2, #12]
    3450:	f023 0301 	bic.w	r3, r3, #1
    3454:	7313      	strb	r3, [r2, #12]
} /* LCOV_EXCL_LINE ... because we just dumped final coverage data */
    3456:	bd08      	pop	{r3, pc}
    3458:	2000077f 	.word	0x2000077f
    345c:	20000138 	.word	0x20000138

00003460 <z_bss_zero>:
	(void)memset(__bss_start, 0, __bss_end - __bss_start);
    3460:	4802      	ldr	r0, [pc, #8]	; (346c <z_bss_zero+0xc>)
    3462:	4a03      	ldr	r2, [pc, #12]	; (3470 <z_bss_zero+0x10>)
    3464:	2100      	movs	r1, #0
    3466:	1a12      	subs	r2, r2, r0
    3468:	f000 bf99 	b.w	439e <memset>
    346c:	20000098 	.word	0x20000098
    3470:	20000780 	.word	0x20000780

00003474 <z_cstart>:
 *
 * @return Does not return
 */
__boot_func
FUNC_NORETURN void z_cstart(void)
{
    3474:	b580      	push	{r7, lr}
 *
 * @return N/A
 */
static ALWAYS_INLINE void z_arm_interrupt_stack_setup(void)
{
	uint32_t msp =
    3476:	f8df 80d8 	ldr.w	r8, [pc, #216]	; 3550 <z_cstart+0xdc>
    347a:	b0a6      	sub	sp, #152	; 0x98
  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
    347c:	f388 8808 	msr	MSP, r8
	 * for Cortex-M3 and Cortex-M4 (ARMv7-M) MCUs. For the rest
	 * of ARM Cortex-M processors this setting is enforced by
	 * default and it is not configurable.
	 */
#if defined(CONFIG_CPU_CORTEX_M3) || defined(CONFIG_CPU_CORTEX_M4)
	SCB->CCR |= SCB_CCR_STKALIGN_Msk;
    3480:	4d2d      	ldr	r5, [pc, #180]	; (3538 <z_cstart+0xc4>)
#endif
#ifdef CONFIG_USERSPACE
	dummy_thread->mem_domain_info.mem_domain = &k_mem_domain_default;
#endif

	_current_cpu->current = dummy_thread;
    3482:	4e2e      	ldr	r6, [pc, #184]	; (353c <z_cstart+0xc8>)
    3484:	696b      	ldr	r3, [r5, #20]
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    3486:	f8df 90cc 	ldr.w	r9, [pc, #204]	; 3554 <z_cstart+0xe0>
    348a:	f443 7300 	orr.w	r3, r3, #512	; 0x200
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    348e:	2400      	movs	r4, #0
    3490:	616b      	str	r3, [r5, #20]
    3492:	23e0      	movs	r3, #224	; 0xe0
    3494:	f885 3022 	strb.w	r3, [r5, #34]	; 0x22
    3498:	77ec      	strb	r4, [r5, #31]
    349a:	762c      	strb	r4, [r5, #24]
    349c:	766c      	strb	r4, [r5, #25]
    349e:	76ac      	strb	r4, [r5, #26]
    34a0:	f885 4020 	strb.w	r4, [r5, #32]
#if defined(CONFIG_ARM_SECURE_FIRMWARE)
	NVIC_SetPriority(SecureFault_IRQn, _EXC_FAULT_PRIO);
#endif /* CONFIG_ARM_SECURE_FIRMWARE */

	/* Enable Usage, Mem, & Bus Faults */
	SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk |
    34a4:	6a6b      	ldr	r3, [r5, #36]	; 0x24
    34a6:	f443 23e0 	orr.w	r3, r3, #458752	; 0x70000
    34aa:	626b      	str	r3, [r5, #36]	; 0x24
    34ac:	f885 4023 	strb.w	r4, [r5, #35]	; 0x23

static ALWAYS_INLINE void arch_kernel_init(void)
{
	z_arm_interrupt_stack_setup();
	z_arm_exc_setup();
	z_arm_fault_init();
    34b0:	f7fd ff94 	bl	13dc <z_arm_fault_init>
	z_arm_cpu_idle_init();
    34b4:	f7fd fd66 	bl	f84 <z_arm_cpu_idle_init>
static ALWAYS_INLINE void z_arm_clear_faults(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* Reset all faults */
	SCB->CFSR = SCB_CFSR_USGFAULTSR_Msk |
    34b8:	f04f 33ff 	mov.w	r3, #4294967295
    34bc:	62ab      	str	r3, [r5, #40]	; 0x28
		    SCB_CFSR_MEMFAULTSR_Msk |
		    SCB_CFSR_BUSFAULTSR_Msk;

	/* Clear all Hard Faults - HFSR is write-one-to-clear */
	SCB->HFSR = 0xffffffff;
    34be:	62eb      	str	r3, [r5, #44]	; 0x2c
	z_arm_clear_faults();
#if defined(CONFIG_ARM_MPU)
	z_arm_mpu_init();
    34c0:	f7fe f8b6 	bl	1630 <z_arm_mpu_init>
	 * to set up access permissions for fixed memory sections, such
	 * as Application Memory or No-Cacheable SRAM area.
	 *
	 * This function is invoked once, upon system initialization.
	 */
	z_arm_configure_static_mpu_regions();
    34c4:	f7fe f826 	bl	1514 <z_arm_configure_static_mpu_regions>
	dummy_thread->base.user_options = K_ESSENTIAL;
    34c8:	f240 1301 	movw	r3, #257	; 0x101
    34cc:	f8ad 3024 	strh.w	r3, [sp, #36]	; 0x24
	_current_cpu->current = dummy_thread;
    34d0:	ab06      	add	r3, sp, #24
    34d2:	60b3      	str	r3, [r6, #8]
	dummy_thread->stack_info.size = 0U;
    34d4:	e9cd 441f 	strd	r4, r4, [sp, #124]	; 0x7c
	struct k_thread dummy_thread;

	z_dummy_thread_init(&dummy_thread);
#endif
	/* do any necessary initialization of static devices */
	z_device_state_init();
    34d8:	f001 fb74 	bl	4bc4 <z_device_state_init>

	/* perform basic hardware initialization */
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_1);
    34dc:	4620      	mov	r0, r4
    34de:	f000 fdbf 	bl	4060 <z_sys_init_run_level>
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_2);
    34e2:	2001      	movs	r0, #1
	_kernel.ready_q.cache = &z_main_thread;
    34e4:	4d16      	ldr	r5, [pc, #88]	; (3540 <z_cstart+0xcc>)
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_2);
    34e6:	f000 fdbb 	bl	4060 <z_sys_init_run_level>
	z_sched_init();
    34ea:	f000 fb29 	bl	3b40 <z_sched_init>
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    34ee:	4b15      	ldr	r3, [pc, #84]	; (3544 <z_cstart+0xd0>)
    34f0:	9305      	str	r3, [sp, #20]
    34f2:	2301      	movs	r3, #1
    34f4:	4914      	ldr	r1, [pc, #80]	; (3548 <z_cstart+0xd4>)
    34f6:	9400      	str	r4, [sp, #0]
    34f8:	e9cd 4303 	strd	r4, r3, [sp, #12]
    34fc:	f44f 6280 	mov.w	r2, #1024	; 0x400
    3500:	464b      	mov	r3, r9
    3502:	e9cd 4401 	strd	r4, r4, [sp, #4]
    3506:	4628      	mov	r0, r5
	_kernel.ready_q.cache = &z_main_thread;
    3508:	61f5      	str	r5, [r6, #28]
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    350a:	f000 f825 	bl	3558 <z_setup_new_thread>
    350e:	7b6a      	ldrb	r2, [r5, #13]
    3510:	f022 0204 	bic.w	r2, r2, #4
    3514:	736a      	strb	r2, [r5, #13]
    3516:	4607      	mov	r7, r0
	z_ready_thread(&z_main_thread);
    3518:	4628      	mov	r0, r5
    351a:	f001 fa94 	bl	4a46 <z_ready_thread>
		init_idle_thread(i);
    351e:	4620      	mov	r0, r4
    3520:	f7ff ff58 	bl	33d4 <init_idle_thread>
		_kernel.cpus[i].idle_thread = &z_idle_threads[i];
    3524:	4b09      	ldr	r3, [pc, #36]	; (354c <z_cstart+0xd8>)
    3526:	60f3      	str	r3, [r6, #12]
	arch_switch_to_main_thread(&z_main_thread, stack_ptr, bg_thread_main);
    3528:	464a      	mov	r2, r9
    352a:	4639      	mov	r1, r7
    352c:	4628      	mov	r0, r5
		_kernel.cpus[i].id = i;
    352e:	7534      	strb	r4, [r6, #20]
		_kernel.cpus[i].irq_stack =
    3530:	f8c6 8004 	str.w	r8, [r6, #4]
	arch_switch_to_main_thread(&z_main_thread, stack_ptr, bg_thread_main);
    3534:	f7fd fe24 	bl	1180 <arch_switch_to_main_thread>
	CODE_UNREACHABLE; /* LCOV_EXCL_LINE */
    3538:	e000ed00 	.word	0xe000ed00
    353c:	20000334 	.word	0x20000334
    3540:	20000138 	.word	0x20000138
    3544:	00004f4d 	.word	0x00004f4d
    3548:	20000780 	.word	0x20000780
    354c:	200000b8 	.word	0x200000b8
    3550:	20001520 	.word	0x20001520
    3554:	0000342d 	.word	0x0000342d

00003558 <z_setup_new_thread>:
char *z_setup_new_thread(struct k_thread *new_thread,
			 k_thread_stack_t *stack, size_t stack_size,
			 k_thread_entry_t entry,
			 void *p1, void *p2, void *p3,
			 int prio, uint32_t options, const char *name)
{
    3558:	e92d 41ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr}
void z_init_thread_base(struct _thread_base *thread_base, int priority,
		       uint32_t initial_state, unsigned int options)
{
	/* k_q_node is initialized upon first insertion in a list */
	thread_base->pended_on = NULL;
	thread_base->user_options = (uint8_t)options;
    355c:	9e0e      	ldr	r6, [sp, #56]	; 0x38
    355e:	7306      	strb	r6, [r0, #12]
	thread_base->thread_state = (uint8_t)initial_state;
    3560:	2604      	movs	r6, #4
    3562:	7346      	strb	r6, [r0, #13]

	thread_base->prio = priority;
    3564:	9e0d      	ldr	r6, [sp, #52]	; 0x34
    3566:	7386      	strb	r6, [r0, #14]
	SYS_DLIST_FOR_EACH_CONTAINER(&((wq)->waitq), thread_ptr, \
				     base.qnode_dlist)

static inline void z_waitq_init(_wait_q_t *w)
{
	sys_dlist_init(&w->waitq);
    3568:	f100 0558 	add.w	r5, r0, #88	; 0x58
{
    356c:	460f      	mov	r7, r1
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    356e:	1dd6      	adds	r6, r2, #7
 */

static inline void sys_dlist_init(sys_dlist_t *list)
{
	list->head = (sys_dnode_t *)list;
	list->tail = (sys_dnode_t *)list;
    3570:	e9c0 5516 	strd	r5, r5, [r0, #88]	; 0x58
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    3574:	9a0c      	ldr	r2, [sp, #48]	; 0x30
	thread_base->pended_on = NULL;
    3576:	2500      	movs	r5, #0
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    3578:	f026 0607 	bic.w	r6, r6, #7

/** @} */

static inline char *Z_KERNEL_STACK_BUFFER(k_thread_stack_t *sym)
{
	return (char *)sym + K_KERNEL_STACK_RESERVED;
    357c:	3720      	adds	r7, #32
 */

static inline void sys_dnode_init(sys_dnode_t *node)
{
	node->next = NULL;
	node->prev = NULL;
    357e:	e9c0 5506 	strd	r5, r5, [r0, #24]
	new_thread->stack_info.size = stack_buf_size;
    3582:	e9c0 7619 	strd	r7, r6, [r0, #100]	; 0x64
	thread_base->pended_on = NULL;
    3586:	6085      	str	r5, [r0, #8]

	thread_base->sched_locked = 0U;
    3588:	73c5      	strb	r5, [r0, #15]
	new_thread->stack_info.delta = delta;
    358a:	66c5      	str	r5, [r0, #108]	; 0x6c
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    358c:	f106 0820 	add.w	r8, r6, #32
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    3590:	9202      	str	r2, [sp, #8]
    3592:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
    3594:	9201      	str	r2, [sp, #4]
	stack_ptr = (char *)stack + stack_obj_size;
    3596:	4488      	add	r8, r1
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    3598:	9a0a      	ldr	r2, [sp, #40]	; 0x28
    359a:	9200      	str	r2, [sp, #0]
    359c:	4642      	mov	r2, r8
{
    359e:	4604      	mov	r4, r0
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    35a0:	f7fd fdb8 	bl	1114 <arch_new_thread>
	if (!_current) {
    35a4:	4b04      	ldr	r3, [pc, #16]	; (35b8 <z_setup_new_thread+0x60>)
	new_thread->init_data = NULL;
    35a6:	6565      	str	r5, [r4, #84]	; 0x54
	if (!_current) {
    35a8:	689b      	ldr	r3, [r3, #8]
    35aa:	b103      	cbz	r3, 35ae <z_setup_new_thread+0x56>
	new_thread->resource_pool = _current->resource_pool;
    35ac:	6f1b      	ldr	r3, [r3, #112]	; 0x70
	return stack_ptr;
    35ae:	6723      	str	r3, [r4, #112]	; 0x70
}
    35b0:	4640      	mov	r0, r8
    35b2:	b004      	add	sp, #16
    35b4:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    35b8:	20000334 	.word	0x20000334

000035bc <z_init_static_threads>:
{
    35bc:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
	_FOREACH_STATIC_THREAD(thread_data) {
    35c0:	4e2a      	ldr	r6, [pc, #168]	; (366c <z_init_static_threads+0xb0>)
    35c2:	4d2b      	ldr	r5, [pc, #172]	; (3670 <z_init_static_threads+0xb4>)
{
    35c4:	b086      	sub	sp, #24
    35c6:	46b0      	mov	r8, r6
	_FOREACH_STATIC_THREAD(thread_data) {
    35c8:	42b5      	cmp	r5, r6
    35ca:	f105 0430 	add.w	r4, r5, #48	; 0x30
    35ce:	d310      	bcc.n	35f2 <z_init_static_threads+0x36>
	k_sched_lock();
    35d0:	f000 f90c 	bl	37ec <k_sched_lock>
	_FOREACH_STATIC_THREAD(thread_data) {
    35d4:	4c26      	ldr	r4, [pc, #152]	; (3670 <z_init_static_threads+0xb4>)

extern void z_thread_timeout(struct _timeout *timeout);

static inline void z_add_thread_timeout(struct k_thread *thread, k_timeout_t ticks)
{
	z_add_timeout(&thread->base.timeout, z_thread_timeout, ticks);
    35d6:	f8df a09c 	ldr.w	sl, [pc, #156]	; 3674 <z_init_static_threads+0xb8>
		} else {
			return (t * to_hz + off) / from_hz;
    35da:	f44f 4900 	mov.w	r9, #32768	; 0x8000
    35de:	f240 36e7 	movw	r6, #999	; 0x3e7
    35e2:	2700      	movs	r7, #0
    35e4:	4544      	cmp	r4, r8
    35e6:	d321      	bcc.n	362c <z_init_static_threads+0x70>
}
    35e8:	b006      	add	sp, #24
    35ea:	e8bd 47f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
	k_sched_unlock();
    35ee:	f000 ba8b 	b.w	3b08 <k_sched_unlock>
		z_setup_new_thread(
    35f2:	f854 3c04 	ldr.w	r3, [r4, #-4]
    35f6:	9305      	str	r3, [sp, #20]
    35f8:	f854 3c10 	ldr.w	r3, [r4, #-16]
    35fc:	9304      	str	r3, [sp, #16]
    35fe:	f854 3c14 	ldr.w	r3, [r4, #-20]
    3602:	9303      	str	r3, [sp, #12]
    3604:	f854 3c18 	ldr.w	r3, [r4, #-24]
    3608:	9302      	str	r3, [sp, #8]
    360a:	f854 3c1c 	ldr.w	r3, [r4, #-28]
    360e:	9301      	str	r3, [sp, #4]
    3610:	f854 3c20 	ldr.w	r3, [r4, #-32]
    3614:	9300      	str	r3, [sp, #0]
    3616:	e954 230a 	ldrd	r2, r3, [r4, #-40]	; 0x28
    361a:	e954 010c 	ldrd	r0, r1, [r4, #-48]	; 0x30
    361e:	f7ff ff9b 	bl	3558 <z_setup_new_thread>
		thread_data->init_thread->init_data = thread_data;
    3622:	f854 3c30 	ldr.w	r3, [r4, #-48]
    3626:	655d      	str	r5, [r3, #84]	; 0x54
    3628:	4625      	mov	r5, r4
    362a:	e7cd      	b.n	35c8 <z_init_static_threads+0xc>
		if (thread_data->init_delay != K_TICKS_FOREVER) {
    362c:	6a63      	ldr	r3, [r4, #36]	; 0x24
    362e:	1c5a      	adds	r2, r3, #1
    3630:	d00d      	beq.n	364e <z_init_static_threads+0x92>
					    K_MSEC(thread_data->init_delay));
    3632:	ea23 73e3 	bic.w	r3, r3, r3, asr #31
    3636:	4630      	mov	r0, r6
    3638:	4639      	mov	r1, r7
    363a:	fbc9 0103 	smlal	r0, r1, r9, r3
	if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) {
    363e:	42b9      	cmp	r1, r7
    3640:	bf08      	it	eq
    3642:	42b0      	cmpeq	r0, r6
			schedule_new_thread(thread_data->init_thread,
    3644:	6825      	ldr	r5, [r4, #0]
	if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) {
    3646:	d104      	bne.n	3652 <z_init_static_threads+0x96>
	z_sched_start(thread);
    3648:	4628      	mov	r0, r5
    364a:	f000 f9bb 	bl	39c4 <z_sched_start>
	_FOREACH_STATIC_THREAD(thread_data) {
    364e:	3430      	adds	r4, #48	; 0x30
    3650:	e7c8      	b.n	35e4 <z_init_static_threads+0x28>
    3652:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    3656:	2300      	movs	r3, #0
    3658:	f7fc fd40 	bl	dc <__aeabi_uldivmod>
    365c:	4602      	mov	r2, r0
    365e:	460b      	mov	r3, r1
    3660:	f105 0018 	add.w	r0, r5, #24
    3664:	4651      	mov	r1, sl
    3666:	f000 fbe1 	bl	3e2c <z_add_timeout>
    366a:	e7f0      	b.n	364e <z_init_static_threads+0x92>
    366c:	20000098 	.word	0x20000098
    3670:	20000098 	.word	0x20000098
    3674:	00004a67 	.word	0x00004a67

00003678 <idle>:
#endif	/* CONFIG_PM */
	sys_clock_idle_exit();
}

void idle(void *unused1, void *unused2, void *unused3)
{
    3678:	b508      	push	{r3, lr}
		 * higher level construct.
		 */
		(void) arch_irq_lock();

#ifdef CONFIG_PM
		_kernel.idle = z_get_next_timeout_expiry();
    367a:	4c09      	ldr	r4, [pc, #36]	; (36a0 <idle+0x28>)
	__asm__ volatile(
    367c:	f04f 0220 	mov.w	r2, #32
    3680:	f3ef 8311 	mrs	r3, BASEPRI
    3684:	f382 8812 	msr	BASEPRI_MAX, r2
    3688:	f3bf 8f6f 	isb	sy
    368c:	f001 fa68 	bl	4b60 <z_get_next_timeout_expiry>
    3690:	61a0      	str	r0, [r4, #24]
		 * processing in those cases i.e. skips k_cpu_idle().
		 * The kernel's idle processing re-enables interrupts
		 * which is essential for the kernel's scheduling
		 * logic.
		 */
		if (pm_system_suspend(_kernel.idle) == false) {
    3692:	f7fd fbf7 	bl	e84 <pm_system_suspend>
    3696:	2800      	cmp	r0, #0
    3698:	d1f0      	bne.n	367c <idle+0x4>
	arch_cpu_idle();
    369a:	f7fd fc79 	bl	f90 <arch_cpu_idle>
}
    369e:	e7ed      	b.n	367c <idle+0x4>
    36a0:	20000334 	.word	0x20000334

000036a4 <z_impl_k_sem_give>:
	ARG_UNUSED(sem);
#endif
}

void z_impl_k_sem_give(struct k_sem *sem)
{
    36a4:	b538      	push	{r3, r4, r5, lr}
    36a6:	4604      	mov	r4, r0
    36a8:	f04f 0320 	mov.w	r3, #32
    36ac:	f3ef 8511 	mrs	r5, BASEPRI
    36b0:	f383 8812 	msr	BASEPRI_MAX, r3
    36b4:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&lock);
	struct k_thread *thread;

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_sem, give, sem);

	thread = z_unpend_first_thread(&sem->wait_q);
    36b8:	f001 fa24 	bl	4b04 <z_unpend_first_thread>

	if (thread != NULL) {
    36bc:	b148      	cbz	r0, 36d2 <z_impl_k_sem_give+0x2e>
}

static ALWAYS_INLINE void
arch_thread_return_value_set(struct k_thread *thread, unsigned int value)
{
	thread->arch.swap_return_value = value;
    36be:	2200      	movs	r2, #0
    36c0:	6782      	str	r2, [r0, #120]	; 0x78
		arch_thread_return_value_set(thread, 0);
		z_ready_thread(thread);
    36c2:	f001 f9c0 	bl	4a46 <z_ready_thread>
	} else {
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
		handle_poll_events(sem);
	}

	z_reschedule(&lock, key);
    36c6:	4629      	mov	r1, r5
    36c8:	4805      	ldr	r0, [pc, #20]	; (36e0 <z_impl_k_sem_give+0x3c>)

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_sem, give, sem);
}
    36ca:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
	z_reschedule(&lock, key);
    36ce:	f000 b87b 	b.w	37c8 <z_reschedule>
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
    36d2:	e9d4 3202 	ldrd	r3, r2, [r4, #8]
    36d6:	429a      	cmp	r2, r3
    36d8:	bf18      	it	ne
    36da:	3301      	addne	r3, #1
    36dc:	60a3      	str	r3, [r4, #8]
		handle_poll_events(sem);
    36de:	e7f2      	b.n	36c6 <z_impl_k_sem_give+0x22>
    36e0:	20000780 	.word	0x20000780

000036e4 <z_impl_k_sem_take>:
}
#include <syscalls/k_sem_give_mrsh.c>
#endif

int z_impl_k_sem_take(struct k_sem *sem, k_timeout_t timeout)
{
    36e4:	b537      	push	{r0, r1, r2, r4, r5, lr}
    36e6:	4614      	mov	r4, r2
    36e8:	461d      	mov	r5, r3
    36ea:	f04f 0320 	mov.w	r3, #32
    36ee:	f3ef 8111 	mrs	r1, BASEPRI
    36f2:	f383 8812 	msr	BASEPRI_MAX, r3
    36f6:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&lock);

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_sem, take, sem, timeout);

	if (likely(sem->count > 0U)) {
    36fa:	6883      	ldr	r3, [r0, #8]
    36fc:	b143      	cbz	r3, 3710 <z_impl_k_sem_take+0x2c>
		sem->count--;
    36fe:	3b01      	subs	r3, #1
    3700:	6083      	str	r3, [r0, #8]
	__asm__ volatile(
    3702:	f381 8811 	msr	BASEPRI, r1
    3706:	f3bf 8f6f 	isb	sy
		k_spin_unlock(&lock, key);
		ret = 0;
    370a:	2000      	movs	r0, #0

out:
	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_sem, take, sem, timeout, ret);

	return ret;
}
    370c:	b003      	add	sp, #12
    370e:	bd30      	pop	{r4, r5, pc}
	if (K_TIMEOUT_EQ(timeout, K_NO_WAIT)) {
    3710:	ea54 0305 	orrs.w	r3, r4, r5
    3714:	d106      	bne.n	3724 <z_impl_k_sem_take+0x40>
    3716:	f381 8811 	msr	BASEPRI, r1
    371a:	f3bf 8f6f 	isb	sy
		ret = -EBUSY;
    371e:	f06f 000f 	mvn.w	r0, #15
    3722:	e7f3      	b.n	370c <z_impl_k_sem_take+0x28>
	ret = z_pend_curr(&lock, key, &sem->wait_q, timeout);
    3724:	4602      	mov	r2, r0
    3726:	e9cd 4500 	strd	r4, r5, [sp]
    372a:	4802      	ldr	r0, [pc, #8]	; (3734 <z_impl_k_sem_take+0x50>)
    372c:	f000 f9a6 	bl	3a7c <z_pend_curr>
	return ret;
    3730:	e7ec      	b.n	370c <z_impl_k_sem_take+0x28>
    3732:	bf00      	nop
    3734:	20000780 	.word	0x20000780

00003738 <z_reset_time_slice>:
 */
static struct k_thread *pending_current;
#endif

void z_reset_time_slice(void)
{
    3738:	b510      	push	{r4, lr}
	/* Add the elapsed time since the last announced tick to the
	 * slice count, as we'll see those "expired" ticks arrive in a
	 * FUTURE z_time_slice() call.
	 */
	if (slice_time != 0) {
    373a:	4c08      	ldr	r4, [pc, #32]	; (375c <z_reset_time_slice+0x24>)
    373c:	6823      	ldr	r3, [r4, #0]
    373e:	b15b      	cbz	r3, 3758 <z_reset_time_slice+0x20>
		_current_cpu->slice_ticks = slice_time + sys_clock_elapsed();
    3740:	f7fe ff4a 	bl	25d8 <sys_clock_elapsed>
    3744:	4603      	mov	r3, r0
    3746:	6820      	ldr	r0, [r4, #0]
    3748:	4a05      	ldr	r2, [pc, #20]	; (3760 <z_reset_time_slice+0x28>)
    374a:	4403      	add	r3, r0
		z_set_timeout_expiry(slice_time, false);
	}
}
    374c:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
		_current_cpu->slice_ticks = slice_time + sys_clock_elapsed();
    3750:	6113      	str	r3, [r2, #16]
		z_set_timeout_expiry(slice_time, false);
    3752:	2100      	movs	r1, #0
    3754:	f001 ba14 	b.w	4b80 <z_set_timeout_expiry>
}
    3758:	bd10      	pop	{r4, pc}
    375a:	bf00      	nop
    375c:	20000364 	.word	0x20000364
    3760:	20000334 	.word	0x20000334

00003764 <k_sched_time_slice_set>:

void k_sched_time_slice_set(int32_t slice, int prio)
{
    3764:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    3766:	4604      	mov	r4, r0
    3768:	460d      	mov	r5, r1
	__asm__ volatile(
    376a:	f04f 0320 	mov.w	r3, #32
    376e:	f3ef 8611 	mrs	r6, BASEPRI
    3772:	f383 8812 	msr	BASEPRI_MAX, r3
    3776:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
		_current_cpu->slice_ticks = 0;
    377a:	4b10      	ldr	r3, [pc, #64]	; (37bc <k_sched_time_slice_set+0x58>)
    377c:	2200      	movs	r2, #0
			return (uint32_t)((t * to_hz + off) / from_hz);
    377e:	f44f 4700 	mov.w	r7, #32768	; 0x8000
    3782:	f240 30e7 	movw	r0, #999	; 0x3e7
    3786:	2100      	movs	r1, #0
    3788:	611a      	str	r2, [r3, #16]
    378a:	fbe7 0104 	umlal	r0, r1, r7, r4
    378e:	2300      	movs	r3, #0
    3790:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    3794:	f7fc fca2 	bl	dc <__aeabi_uldivmod>
		slice_time = k_ms_to_ticks_ceil32(slice);
		if (IS_ENABLED(CONFIG_TICKLESS_KERNEL) && slice > 0) {
    3798:	2c00      	cmp	r4, #0
    379a:	4b09      	ldr	r3, [pc, #36]	; (37c0 <k_sched_time_slice_set+0x5c>)
    379c:	dc09      	bgt.n	37b2 <k_sched_time_slice_set+0x4e>
			/* It's not possible to reliably set a 1-tick
			 * timeout if ticks aren't regular.
			 */
			slice_time = MAX(2, slice_time);
    379e:	6018      	str	r0, [r3, #0]
		}
		slice_max_prio = prio;
    37a0:	4b08      	ldr	r3, [pc, #32]	; (37c4 <k_sched_time_slice_set+0x60>)
    37a2:	601d      	str	r5, [r3, #0]
		z_reset_time_slice();
    37a4:	f7ff ffc8 	bl	3738 <z_reset_time_slice>
	__asm__ volatile(
    37a8:	f386 8811 	msr	BASEPRI, r6
    37ac:	f3bf 8f6f 	isb	sy
	}
}
    37b0:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
			slice_time = MAX(2, slice_time);
    37b2:	2802      	cmp	r0, #2
    37b4:	bfb8      	it	lt
    37b6:	2002      	movlt	r0, #2
    37b8:	e7f1      	b.n	379e <k_sched_time_slice_set+0x3a>
    37ba:	bf00      	nop
    37bc:	20000334 	.word	0x20000334
    37c0:	20000364 	.word	0x20000364
    37c4:	20000360 	.word	0x20000360

000037c8 <z_reschedule>:
{
#ifdef CONFIG_SMP
	_current_cpu->swap_ok = 0;
#endif

	return arch_irq_unlocked(key) && !arch_is_in_isr();
    37c8:	b949      	cbnz	r1, 37de <z_reschedule+0x16>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    37ca:	f3ef 8005 	mrs	r0, IPSR
#endif
}

void z_reschedule(struct k_spinlock *lock, k_spinlock_key_t key)
{
	if (resched(key.key) && need_swap()) {
    37ce:	b930      	cbnz	r0, 37de <z_reschedule+0x16>
	new_thread = _kernel.ready_q.cache;
    37d0:	4b05      	ldr	r3, [pc, #20]	; (37e8 <z_reschedule+0x20>)
	if (resched(key.key) && need_swap()) {
    37d2:	69da      	ldr	r2, [r3, #28]
    37d4:	689b      	ldr	r3, [r3, #8]
    37d6:	429a      	cmp	r2, r3
    37d8:	d001      	beq.n	37de <z_reschedule+0x16>
	ret = arch_swap(key);
    37da:	f7fd bc47 	b.w	106c <arch_swap>
    37de:	f381 8811 	msr	BASEPRI, r1
    37e2:	f3bf 8f6f 	isb	sy
		z_swap(lock, key);
	} else {
		k_spin_unlock(lock, key);
	}
}
    37e6:	4770      	bx	lr
    37e8:	20000334 	.word	0x20000334

000037ec <k_sched_lock>:
	__asm__ volatile(
    37ec:	f04f 0320 	mov.w	r3, #32
    37f0:	f3ef 8111 	mrs	r1, BASEPRI
    37f4:	f383 8812 	msr	BASEPRI_MAX, r3
    37f8:	f3bf 8f6f 	isb	sy
static inline void z_sched_lock(void)
{
	__ASSERT(!arch_is_in_isr(), "");
	__ASSERT(_current->base.sched_locked != 1U, "");

	--_current->base.sched_locked;
    37fc:	4b04      	ldr	r3, [pc, #16]	; (3810 <k_sched_lock+0x24>)
    37fe:	689a      	ldr	r2, [r3, #8]
    3800:	7bd3      	ldrb	r3, [r2, #15]
    3802:	3b01      	subs	r3, #1
    3804:	73d3      	strb	r3, [r2, #15]
	__asm__ volatile(
    3806:	f381 8811 	msr	BASEPRI, r1
    380a:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
		SYS_PORT_TRACING_FUNC(k_thread, sched_lock);

		z_sched_lock();
	}
}
    380e:	4770      	bx	lr
    3810:	20000334 	.word	0x20000334

00003814 <update_cache>:
{
    3814:	b538      	push	{r3, r4, r5, lr}
    3816:	4602      	mov	r2, r0
	return _priq_run_best(curr_cpu_runq());
    3818:	480c      	ldr	r0, [pc, #48]	; (384c <update_cache+0x38>)
    381a:	4d0d      	ldr	r5, [pc, #52]	; (3850 <update_cache+0x3c>)
    381c:	f001 f909 	bl	4a32 <z_priq_dumb_best>
	return (thread != NULL) ? thread : _current_cpu->idle_thread;
    3820:	4604      	mov	r4, r0
    3822:	b900      	cbnz	r0, 3826 <update_cache+0x12>
    3824:	68ec      	ldr	r4, [r5, #12]
	if (preempt_ok != 0) {
    3826:	68ab      	ldr	r3, [r5, #8]
    3828:	b94a      	cbnz	r2, 383e <update_cache+0x2a>
	if (z_is_thread_prevented_from_running(_current)) {
    382a:	7b5a      	ldrb	r2, [r3, #13]
    382c:	06d2      	lsls	r2, r2, #27
    382e:	d106      	bne.n	383e <update_cache+0x2a>
	if (IS_ENABLED(CONFIG_SWAP_NONATOMIC)
    3830:	69a2      	ldr	r2, [r4, #24]
    3832:	b922      	cbnz	r2, 383e <update_cache+0x2a>
	if (is_preempt(_current) || is_metairq(thread)) {
    3834:	89da      	ldrh	r2, [r3, #14]
    3836:	2a7f      	cmp	r2, #127	; 0x7f
    3838:	d901      	bls.n	383e <update_cache+0x2a>
		_kernel.ready_q.cache = _current;
    383a:	61eb      	str	r3, [r5, #28]
}
    383c:	bd38      	pop	{r3, r4, r5, pc}
		if (thread != _current) {
    383e:	429c      	cmp	r4, r3
    3840:	d001      	beq.n	3846 <update_cache+0x32>
			z_reset_time_slice();
    3842:	f7ff ff79 	bl	3738 <z_reset_time_slice>
		_kernel.ready_q.cache = thread;
    3846:	61ec      	str	r4, [r5, #28]
}
    3848:	e7f8      	b.n	383c <update_cache+0x28>
    384a:	bf00      	nop
    384c:	20000354 	.word	0x20000354
    3850:	20000334 	.word	0x20000334

00003854 <move_thread_to_end_of_prio_q>:
{
    3854:	b570      	push	{r4, r5, r6, lr}
	if (z_is_thread_queued(thread)) {
    3856:	f990 200d 	ldrsb.w	r2, [r0, #13]
	return z_is_thread_state_set(thread, _THREAD_QUEUED);
    385a:	7b43      	ldrb	r3, [r0, #13]
    385c:	2a00      	cmp	r2, #0
{
    385e:	4601      	mov	r1, r0
	if (z_is_thread_queued(thread)) {
    3860:	da04      	bge.n	386c <move_thread_to_end_of_prio_q+0x18>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    3862:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    3866:	7343      	strb	r3, [r0, #13]

void z_priq_dumb_remove(sys_dlist_t *pq, struct k_thread *thread)
{
	__ASSERT_NO_MSG(!z_is_idle_thread_object(thread));

	sys_dlist_remove(&thread->base.qnode_dlist);
    3868:	f001 f8bb 	bl	49e2 <sys_dlist_remove>
	thread->base.thread_state |= _THREAD_QUEUED;
    386c:	7b4b      	ldrb	r3, [r1, #13]
 * @return true if empty, false otherwise
 */

static inline bool sys_dlist_is_empty(sys_dlist_t *list)
{
	return list->head == list;
    386e:	4a17      	ldr	r2, [pc, #92]	; (38cc <move_thread_to_end_of_prio_q+0x78>)
    3870:	f063 037f 	orn	r3, r3, #127	; 0x7f
    3874:	4610      	mov	r0, r2
    3876:	734b      	strb	r3, [r1, #13]
    3878:	f850 3f20 	ldr.w	r3, [r0, #32]!
 */

static inline sys_dnode_t *sys_dlist_peek_next(sys_dlist_t *list,
					       sys_dnode_t *node)
{
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    387c:	6a55      	ldr	r5, [r2, #36]	; 0x24
	return sys_dlist_is_empty(list) ? NULL : list->head;
    387e:	4283      	cmp	r3, r0
    3880:	bf08      	it	eq
    3882:	2300      	moveq	r3, #0
    3884:	2b00      	cmp	r3, #0
    3886:	bf38      	it	cc
    3888:	2300      	movcc	r3, #0
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    388a:	b1cb      	cbz	r3, 38c0 <move_thread_to_end_of_prio_q+0x6c>
	int32_t b1 = thread_1->base.prio;
    388c:	f991 600e 	ldrsb.w	r6, [r1, #14]
	int32_t b2 = thread_2->base.prio;
    3890:	f993 400e 	ldrsb.w	r4, [r3, #14]
	if (b1 != b2) {
    3894:	42a6      	cmp	r6, r4
    3896:	d00f      	beq.n	38b8 <move_thread_to_end_of_prio_q+0x64>
		return b2 - b1;
    3898:	1ba4      	subs	r4, r4, r6
		if (z_sched_prio_cmp(thread, t) > 0) {
    389a:	2c00      	cmp	r4, #0
    389c:	dd0c      	ble.n	38b8 <move_thread_to_end_of_prio_q+0x64>
 * @param successor the position before which "node" will be inserted
 * @param node the element to insert
 */
static inline void sys_dlist_insert(sys_dnode_t *successor, sys_dnode_t *node)
{
	sys_dnode_t *const prev = successor->prev;
    389e:	6858      	ldr	r0, [r3, #4]

	node->prev = prev;
	node->next = successor;
    38a0:	e9c1 3000 	strd	r3, r0, [r1]
	prev->next = node;
    38a4:	6001      	str	r1, [r0, #0]
	successor->prev = node;
    38a6:	6059      	str	r1, [r3, #4]
	update_cache(thread == _current);
    38a8:	6890      	ldr	r0, [r2, #8]
    38aa:	1a43      	subs	r3, r0, r1
    38ac:	4258      	negs	r0, r3
}
    38ae:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	update_cache(thread == _current);
    38b2:	4158      	adcs	r0, r3
    38b4:	f7ff bfae 	b.w	3814 <update_cache>
	return (node == list->tail) ? NULL : node->next;
    38b8:	42ab      	cmp	r3, r5
    38ba:	d001      	beq.n	38c0 <move_thread_to_end_of_prio_q+0x6c>
    38bc:	681b      	ldr	r3, [r3, #0]
    38be:	e7e4      	b.n	388a <move_thread_to_end_of_prio_q+0x36>
	node->prev = tail;
    38c0:	e9c1 0500 	strd	r0, r5, [r1]
	tail->next = node;
    38c4:	6029      	str	r1, [r5, #0]
	list->tail = node;
    38c6:	6251      	str	r1, [r2, #36]	; 0x24
}
    38c8:	e7ee      	b.n	38a8 <move_thread_to_end_of_prio_q+0x54>
    38ca:	bf00      	nop
    38cc:	20000334 	.word	0x20000334

000038d0 <z_time_slice>:
{
    38d0:	b570      	push	{r4, r5, r6, lr}
    38d2:	4601      	mov	r1, r0
	__asm__ volatile(
    38d4:	f04f 0320 	mov.w	r3, #32
    38d8:	f3ef 8411 	mrs	r4, BASEPRI
    38dc:	f383 8812 	msr	BASEPRI_MAX, r3
    38e0:	f3bf 8f6f 	isb	sy
	if (pending_current == _current) {
    38e4:	4b16      	ldr	r3, [pc, #88]	; (3940 <z_time_slice+0x70>)
    38e6:	4a17      	ldr	r2, [pc, #92]	; (3944 <z_time_slice+0x74>)
    38e8:	6898      	ldr	r0, [r3, #8]
    38ea:	6815      	ldr	r5, [r2, #0]
    38ec:	42a8      	cmp	r0, r5
    38ee:	461d      	mov	r5, r3
    38f0:	d106      	bne.n	3900 <z_time_slice+0x30>
			z_reset_time_slice();
    38f2:	f7ff ff21 	bl	3738 <z_reset_time_slice>
	__asm__ volatile(
    38f6:	f384 8811 	msr	BASEPRI, r4
    38fa:	f3bf 8f6f 	isb	sy
}
    38fe:	bd70      	pop	{r4, r5, r6, pc}
	pending_current = NULL;
    3900:	2600      	movs	r6, #0
    3902:	6016      	str	r6, [r2, #0]
	if (slice_time && sliceable(_current)) {
    3904:	4a10      	ldr	r2, [pc, #64]	; (3948 <z_time_slice+0x78>)
    3906:	6812      	ldr	r2, [r2, #0]
    3908:	b1ba      	cbz	r2, 393a <z_time_slice+0x6a>
		&& !z_is_idle_thread_object(thread);
    390a:	89c2      	ldrh	r2, [r0, #14]
    390c:	2a7f      	cmp	r2, #127	; 0x7f
    390e:	d814      	bhi.n	393a <z_time_slice+0x6a>
		&& !z_is_thread_prevented_from_running(thread)
    3910:	7b42      	ldrb	r2, [r0, #13]
    3912:	06d2      	lsls	r2, r2, #27
    3914:	d111      	bne.n	393a <z_time_slice+0x6a>
		&& !z_is_prio_higher(thread->base.prio, slice_max_prio)
    3916:	4a0d      	ldr	r2, [pc, #52]	; (394c <z_time_slice+0x7c>)
    3918:	f990 600e 	ldrsb.w	r6, [r0, #14]
    391c:	6812      	ldr	r2, [r2, #0]
    391e:	4296      	cmp	r6, r2
    3920:	db0b      	blt.n	393a <z_time_slice+0x6a>
		&& !z_is_idle_thread_object(thread);
    3922:	4a0b      	ldr	r2, [pc, #44]	; (3950 <z_time_slice+0x80>)
    3924:	4290      	cmp	r0, r2
    3926:	d008      	beq.n	393a <z_time_slice+0x6a>
		if (ticks >= _current_cpu->slice_ticks) {
    3928:	691a      	ldr	r2, [r3, #16]
    392a:	428a      	cmp	r2, r1
    392c:	dc02      	bgt.n	3934 <z_time_slice+0x64>
			move_thread_to_end_of_prio_q(_current);
    392e:	f7ff ff91 	bl	3854 <move_thread_to_end_of_prio_q>
    3932:	e7de      	b.n	38f2 <z_time_slice+0x22>
			_current_cpu->slice_ticks -= ticks;
    3934:	1a52      	subs	r2, r2, r1
    3936:	611a      	str	r2, [r3, #16]
    3938:	e7dd      	b.n	38f6 <z_time_slice+0x26>
		_current_cpu->slice_ticks = 0;
    393a:	2300      	movs	r3, #0
    393c:	612b      	str	r3, [r5, #16]
    393e:	e7da      	b.n	38f6 <z_time_slice+0x26>
    3940:	20000334 	.word	0x20000334
    3944:	2000035c 	.word	0x2000035c
    3948:	20000364 	.word	0x20000364
    394c:	20000360 	.word	0x20000360
    3950:	200000b8 	.word	0x200000b8

00003954 <ready_thread>:
{
    3954:	b470      	push	{r4, r5, r6}
	if (!z_is_thread_queued(thread) && z_is_thread_ready(thread)) {
    3956:	f990 300d 	ldrsb.w	r3, [r0, #13]
    395a:	7b42      	ldrb	r2, [r0, #13]
    395c:	2b00      	cmp	r3, #0
    395e:	db2d      	blt.n	39bc <ready_thread+0x68>
	return !((z_is_thread_prevented_from_running(thread)) != 0U ||
    3960:	06d3      	lsls	r3, r2, #27
    3962:	d12b      	bne.n	39bc <ready_thread+0x68>
	return !sys_dnode_is_linked(&to->node);
    3964:	6983      	ldr	r3, [r0, #24]
    3966:	bb4b      	cbnz	r3, 39bc <ready_thread+0x68>
	return list->head == list;
    3968:	4915      	ldr	r1, [pc, #84]	; (39c0 <ready_thread+0x6c>)
	thread->base.thread_state |= _THREAD_QUEUED;
    396a:	f062 027f 	orn	r2, r2, #127	; 0x7f
    396e:	7342      	strb	r2, [r0, #13]
    3970:	460a      	mov	r2, r1
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    3972:	6a4d      	ldr	r5, [r1, #36]	; 0x24
	return list->head == list;
    3974:	f852 4f20 	ldr.w	r4, [r2, #32]!
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3978:	4294      	cmp	r4, r2
    397a:	bf18      	it	ne
    397c:	4623      	movne	r3, r4
    397e:	2b00      	cmp	r3, #0
    3980:	bf38      	it	cc
    3982:	2300      	movcc	r3, #0
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    3984:	b1ab      	cbz	r3, 39b2 <ready_thread+0x5e>
	int32_t b1 = thread_1->base.prio;
    3986:	f990 600e 	ldrsb.w	r6, [r0, #14]
	int32_t b2 = thread_2->base.prio;
    398a:	f993 400e 	ldrsb.w	r4, [r3, #14]
	if (b1 != b2) {
    398e:	42a6      	cmp	r6, r4
    3990:	d00b      	beq.n	39aa <ready_thread+0x56>
		return b2 - b1;
    3992:	1ba4      	subs	r4, r4, r6
		if (z_sched_prio_cmp(thread, t) > 0) {
    3994:	2c00      	cmp	r4, #0
    3996:	dd08      	ble.n	39aa <ready_thread+0x56>
	sys_dnode_t *const prev = successor->prev;
    3998:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
    399a:	e9c0 3200 	strd	r3, r2, [r0]
	prev->next = node;
    399e:	6010      	str	r0, [r2, #0]
	successor->prev = node;
    39a0:	6058      	str	r0, [r3, #4]
}
    39a2:	bc70      	pop	{r4, r5, r6}
		update_cache(0);
    39a4:	2000      	movs	r0, #0
    39a6:	f7ff bf35 	b.w	3814 <update_cache>
	return (node == list->tail) ? NULL : node->next;
    39aa:	42ab      	cmp	r3, r5
    39ac:	d001      	beq.n	39b2 <ready_thread+0x5e>
    39ae:	681b      	ldr	r3, [r3, #0]
    39b0:	e7e8      	b.n	3984 <ready_thread+0x30>
	node->prev = tail;
    39b2:	e9c0 2500 	strd	r2, r5, [r0]
	tail->next = node;
    39b6:	6028      	str	r0, [r5, #0]
	list->tail = node;
    39b8:	6248      	str	r0, [r1, #36]	; 0x24
}
    39ba:	e7f2      	b.n	39a2 <ready_thread+0x4e>
}
    39bc:	bc70      	pop	{r4, r5, r6}
    39be:	4770      	bx	lr
    39c0:	20000334 	.word	0x20000334

000039c4 <z_sched_start>:
{
    39c4:	b510      	push	{r4, lr}
	__asm__ volatile(
    39c6:	f04f 0220 	mov.w	r2, #32
    39ca:	f3ef 8411 	mrs	r4, BASEPRI
    39ce:	f382 8812 	msr	BASEPRI_MAX, r2
    39d2:	f3bf 8f6f 	isb	sy
	if (z_has_thread_started(thread)) {
    39d6:	7b42      	ldrb	r2, [r0, #13]
    39d8:	0751      	lsls	r1, r2, #29
    39da:	d404      	bmi.n	39e6 <z_sched_start+0x22>
	__asm__ volatile(
    39dc:	f384 8811 	msr	BASEPRI, r4
    39e0:	f3bf 8f6f 	isb	sy
}
    39e4:	bd10      	pop	{r4, pc}
	thread->base.thread_state &= ~_THREAD_PRESTART;
    39e6:	f022 0204 	bic.w	r2, r2, #4
    39ea:	7342      	strb	r2, [r0, #13]
	ready_thread(thread);
    39ec:	f7ff ffb2 	bl	3954 <ready_thread>
	z_reschedule(&sched_spinlock, key);
    39f0:	4621      	mov	r1, r4
    39f2:	4802      	ldr	r0, [pc, #8]	; (39fc <z_sched_start+0x38>)
}
    39f4:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	z_reschedule(&sched_spinlock, key);
    39f8:	f7ff bee6 	b.w	37c8 <z_reschedule>
    39fc:	20000780 	.word	0x20000780

00003a00 <unready_thread>:
{
    3a00:	b508      	push	{r3, lr}
	if (z_is_thread_queued(thread)) {
    3a02:	f990 200d 	ldrsb.w	r2, [r0, #13]
	return z_is_thread_state_set(thread, _THREAD_QUEUED);
    3a06:	7b43      	ldrb	r3, [r0, #13]
    3a08:	2a00      	cmp	r2, #0
{
    3a0a:	4601      	mov	r1, r0
	if (z_is_thread_queued(thread)) {
    3a0c:	da04      	bge.n	3a18 <unready_thread+0x18>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    3a0e:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    3a12:	7343      	strb	r3, [r0, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    3a14:	f000 ffe5 	bl	49e2 <sys_dlist_remove>
	update_cache(thread == _current);
    3a18:	4b04      	ldr	r3, [pc, #16]	; (3a2c <unready_thread+0x2c>)
    3a1a:	6898      	ldr	r0, [r3, #8]
    3a1c:	1a43      	subs	r3, r0, r1
    3a1e:	4258      	negs	r0, r3
    3a20:	4158      	adcs	r0, r3
}
    3a22:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	update_cache(thread == _current);
    3a26:	f7ff bef5 	b.w	3814 <update_cache>
    3a2a:	bf00      	nop
    3a2c:	20000334 	.word	0x20000334

00003a30 <pend>:
{
    3a30:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    3a34:	4606      	mov	r6, r0
    3a36:	4614      	mov	r4, r2
    3a38:	461d      	mov	r5, r3
	__asm__ volatile(
    3a3a:	f04f 0320 	mov.w	r3, #32
    3a3e:	f3ef 8711 	mrs	r7, BASEPRI
    3a42:	f383 8812 	msr	BASEPRI_MAX, r3
    3a46:	f3bf 8f6f 	isb	sy
		add_to_waitq_locked(thread, wait_q);
    3a4a:	f001 f82e 	bl	4aaa <add_to_waitq_locked>
	__asm__ volatile(
    3a4e:	f387 8811 	msr	BASEPRI, r7
    3a52:	f3bf 8f6f 	isb	sy
	if (!K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    3a56:	1c6b      	adds	r3, r5, #1
    3a58:	bf08      	it	eq
    3a5a:	f1b4 3fff 	cmpeq.w	r4, #4294967295
    3a5e:	d008      	beq.n	3a72 <pend+0x42>
	z_add_timeout(&thread->base.timeout, z_thread_timeout, ticks);
    3a60:	4622      	mov	r2, r4
    3a62:	462b      	mov	r3, r5
    3a64:	f106 0018 	add.w	r0, r6, #24
    3a68:	4903      	ldr	r1, [pc, #12]	; (3a78 <pend+0x48>)
}
    3a6a:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
    3a6e:	f000 b9dd 	b.w	3e2c <z_add_timeout>
    3a72:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    3a76:	bf00      	nop
    3a78:	00004a67 	.word	0x00004a67

00003a7c <z_pend_curr>:
{
    3a7c:	b510      	push	{r4, lr}
	pending_current = _current;
    3a7e:	4b07      	ldr	r3, [pc, #28]	; (3a9c <z_pend_curr+0x20>)
    3a80:	6898      	ldr	r0, [r3, #8]
    3a82:	4b07      	ldr	r3, [pc, #28]	; (3aa0 <z_pend_curr+0x24>)
{
    3a84:	460c      	mov	r4, r1
	pending_current = _current;
    3a86:	6018      	str	r0, [r3, #0]
{
    3a88:	4611      	mov	r1, r2
	pend(_current, wait_q, timeout);
    3a8a:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
    3a8e:	f7ff ffcf 	bl	3a30 <pend>
    3a92:	4620      	mov	r0, r4
}
    3a94:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    3a98:	f7fd bae8 	b.w	106c <arch_swap>
    3a9c:	20000334 	.word	0x20000334
    3aa0:	2000035c 	.word	0x2000035c

00003aa4 <z_impl_k_thread_suspend>:
{
    3aa4:	b570      	push	{r4, r5, r6, lr}
    3aa6:	4604      	mov	r4, r0
}

static inline int z_abort_thread_timeout(struct k_thread *thread)
{
	return z_abort_timeout(&thread->base.timeout);
    3aa8:	3018      	adds	r0, #24
    3aaa:	f001 f843 	bl	4b34 <z_abort_timeout>
	__asm__ volatile(
    3aae:	f04f 0320 	mov.w	r3, #32
    3ab2:	f3ef 8611 	mrs	r6, BASEPRI
    3ab6:	f383 8812 	msr	BASEPRI_MAX, r3
    3aba:	f3bf 8f6f 	isb	sy
		if (z_is_thread_queued(thread)) {
    3abe:	f994 200d 	ldrsb.w	r2, [r4, #13]
    3ac2:	7b63      	ldrb	r3, [r4, #13]
    3ac4:	2a00      	cmp	r2, #0
    3ac6:	da05      	bge.n	3ad4 <z_impl_k_thread_suspend+0x30>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    3ac8:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    3acc:	7363      	strb	r3, [r4, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    3ace:	4620      	mov	r0, r4
    3ad0:	f000 ff87 	bl	49e2 <sys_dlist_remove>
		update_cache(thread == _current);
    3ad4:	4d0b      	ldr	r5, [pc, #44]	; (3b04 <z_impl_k_thread_suspend+0x60>)
	thread->base.thread_state |= _THREAD_SUSPENDED;
    3ad6:	7b63      	ldrb	r3, [r4, #13]
    3ad8:	68a8      	ldr	r0, [r5, #8]
    3ada:	f043 0310 	orr.w	r3, r3, #16
    3ade:	7363      	strb	r3, [r4, #13]
    3ae0:	1b03      	subs	r3, r0, r4
    3ae2:	4258      	negs	r0, r3
    3ae4:	4158      	adcs	r0, r3
    3ae6:	f7ff fe95 	bl	3814 <update_cache>
	__asm__ volatile(
    3aea:	f386 8811 	msr	BASEPRI, r6
    3aee:	f3bf 8f6f 	isb	sy
	if (thread == _current) {
    3af2:	68ab      	ldr	r3, [r5, #8]
    3af4:	42a3      	cmp	r3, r4
    3af6:	d103      	bne.n	3b00 <z_impl_k_thread_suspend+0x5c>
}
    3af8:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		z_reschedule_unlocked();
    3afc:	f000 bf8f 	b.w	4a1e <z_reschedule_unlocked>
}
    3b00:	bd70      	pop	{r4, r5, r6, pc}
    3b02:	bf00      	nop
    3b04:	20000334 	.word	0x20000334

00003b08 <k_sched_unlock>:
{
    3b08:	b510      	push	{r4, lr}
	__asm__ volatile(
    3b0a:	f04f 0320 	mov.w	r3, #32
    3b0e:	f3ef 8411 	mrs	r4, BASEPRI
    3b12:	f383 8812 	msr	BASEPRI_MAX, r3
    3b16:	f3bf 8f6f 	isb	sy
		++_current->base.sched_locked;
    3b1a:	4b08      	ldr	r3, [pc, #32]	; (3b3c <k_sched_unlock+0x34>)
    3b1c:	689a      	ldr	r2, [r3, #8]
    3b1e:	7bd3      	ldrb	r3, [r2, #15]
    3b20:	3301      	adds	r3, #1
    3b22:	73d3      	strb	r3, [r2, #15]
		update_cache(0);
    3b24:	2000      	movs	r0, #0
    3b26:	f7ff fe75 	bl	3814 <update_cache>
	__asm__ volatile(
    3b2a:	f384 8811 	msr	BASEPRI, r4
    3b2e:	f3bf 8f6f 	isb	sy
}
    3b32:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	z_reschedule_unlocked();
    3b36:	f000 bf72 	b.w	4a1e <z_reschedule_unlocked>
    3b3a:	bf00      	nop
    3b3c:	20000334 	.word	0x20000334

00003b40 <z_sched_init>:
	list->head = (sys_dnode_t *)list;
    3b40:	4b04      	ldr	r3, [pc, #16]	; (3b54 <z_sched_init+0x14>)
#else
	init_ready_q(&_kernel.ready_q);
#endif

#ifdef CONFIG_TIMESLICING
	k_sched_time_slice_set(CONFIG_TIMESLICE_SIZE,
    3b42:	2100      	movs	r1, #0
    3b44:	f103 0220 	add.w	r2, r3, #32
	list->tail = (sys_dnode_t *)list;
    3b48:	e9c3 2208 	strd	r2, r2, [r3, #32]
    3b4c:	4608      	mov	r0, r1
    3b4e:	f7ff be09 	b.w	3764 <k_sched_time_slice_set>
    3b52:	bf00      	nop
    3b54:	20000334 	.word	0x20000334

00003b58 <z_impl_k_yield>:
#include <syscalls/k_thread_deadline_set_mrsh.c>
#endif
#endif

void z_impl_k_yield(void)
{
    3b58:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	__asm__ volatile(
    3b5a:	f04f 0320 	mov.w	r3, #32
    3b5e:	f3ef 8411 	mrs	r4, BASEPRI
    3b62:	f383 8812 	msr	BASEPRI_MAX, r3
    3b66:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&sched_spinlock);

	if (!IS_ENABLED(CONFIG_SMP) ||
	    z_is_thread_queued(_current)) {
		dequeue_thread(_current);
    3b6a:	491b      	ldr	r1, [pc, #108]	; (3bd8 <z_impl_k_yield+0x80>)
    3b6c:	6888      	ldr	r0, [r1, #8]
	thread->base.thread_state &= ~_THREAD_QUEUED;
    3b6e:	7b43      	ldrb	r3, [r0, #13]
    3b70:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    3b74:	7343      	strb	r3, [r0, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    3b76:	f000 ff34 	bl	49e2 <sys_dlist_remove>
	}
	queue_thread(_current);
    3b7a:	688a      	ldr	r2, [r1, #8]
	thread->base.thread_state |= _THREAD_QUEUED;
    3b7c:	7b53      	ldrb	r3, [r2, #13]
	return list->head == list;
    3b7e:	4608      	mov	r0, r1
    3b80:	f063 037f 	orn	r3, r3, #127	; 0x7f
    3b84:	7353      	strb	r3, [r2, #13]
    3b86:	f850 3f20 	ldr.w	r3, [r0, #32]!
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    3b8a:	6a4e      	ldr	r6, [r1, #36]	; 0x24
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3b8c:	4283      	cmp	r3, r0
    3b8e:	bf08      	it	eq
    3b90:	2300      	moveq	r3, #0
    3b92:	2b00      	cmp	r3, #0
    3b94:	bf38      	it	cc
    3b96:	2300      	movcc	r3, #0
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    3b98:	b1cb      	cbz	r3, 3bce <z_impl_k_yield+0x76>
	int32_t b1 = thread_1->base.prio;
    3b9a:	f992 700e 	ldrsb.w	r7, [r2, #14]
	int32_t b2 = thread_2->base.prio;
    3b9e:	f993 500e 	ldrsb.w	r5, [r3, #14]
	if (b1 != b2) {
    3ba2:	42af      	cmp	r7, r5
    3ba4:	d00f      	beq.n	3bc6 <z_impl_k_yield+0x6e>
		return b2 - b1;
    3ba6:	1bed      	subs	r5, r5, r7
		if (z_sched_prio_cmp(thread, t) > 0) {
    3ba8:	2d00      	cmp	r5, #0
    3baa:	dd0c      	ble.n	3bc6 <z_impl_k_yield+0x6e>
	sys_dnode_t *const prev = successor->prev;
    3bac:	6859      	ldr	r1, [r3, #4]
	node->next = successor;
    3bae:	e9c2 3100 	strd	r3, r1, [r2]
	prev->next = node;
    3bb2:	600a      	str	r2, [r1, #0]
	successor->prev = node;
    3bb4:	605a      	str	r2, [r3, #4]
	update_cache(1);
    3bb6:	2001      	movs	r0, #1
    3bb8:	f7ff fe2c 	bl	3814 <update_cache>
    3bbc:	4620      	mov	r0, r4
	z_swap(&sched_spinlock, key);
}
    3bbe:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
    3bc2:	f7fd ba53 	b.w	106c <arch_swap>
	return (node == list->tail) ? NULL : node->next;
    3bc6:	42b3      	cmp	r3, r6
    3bc8:	d001      	beq.n	3bce <z_impl_k_yield+0x76>
    3bca:	681b      	ldr	r3, [r3, #0]
    3bcc:	e7e4      	b.n	3b98 <z_impl_k_yield+0x40>
	node->prev = tail;
    3bce:	e9c2 0600 	strd	r0, r6, [r2]
	tail->next = node;
    3bd2:	6032      	str	r2, [r6, #0]
	list->tail = node;
    3bd4:	624a      	str	r2, [r1, #36]	; 0x24
}
    3bd6:	e7ee      	b.n	3bb6 <z_impl_k_yield+0x5e>
    3bd8:	20000334 	.word	0x20000334

00003bdc <z_tick_sleep>:
}
#include <syscalls/k_yield_mrsh.c>
#endif

static int32_t z_tick_sleep(k_ticks_t ticks)
{
    3bdc:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    3be0:	4604      	mov	r4, r0
    3be2:	460d      	mov	r5, r1
	 */
	LOG_DBG("thread %p for %u ticks", _current, ticks);
#endif

	/* wait of 0 ms is treated as a 'yield' */
	if (ticks == 0) {
    3be4:	ea54 0105 	orrs.w	r1, r4, r5
    3be8:	d104      	bne.n	3bf4 <z_tick_sleep+0x18>
	z_impl_k_yield();
    3bea:	f7ff ffb5 	bl	3b58 <z_impl_k_yield>
		k_yield();
		return 0;
    3bee:	2000      	movs	r0, #0
		return ticks;
	}
#endif

	return 0;
}
    3bf0:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	if (Z_TICK_ABS(ticks) <= 0) {
    3bf4:	f06f 0101 	mvn.w	r1, #1
    3bf8:	1a0a      	subs	r2, r1, r0
    3bfa:	f04f 31ff 	mov.w	r1, #4294967295
    3bfe:	eb61 0305 	sbc.w	r3, r1, r5
    3c02:	2a01      	cmp	r2, #1
    3c04:	f173 0300 	sbcs.w	r3, r3, #0
    3c08:	da2a      	bge.n	3c60 <z_tick_sleep+0x84>
		expected_wakeup_ticks = ticks + sys_clock_tick_get_32();
    3c0a:	f000 ffd3 	bl	4bb4 <sys_clock_tick_get_32>
    3c0e:	1906      	adds	r6, r0, r4
    3c10:	f04f 0320 	mov.w	r3, #32
    3c14:	f3ef 8811 	mrs	r8, BASEPRI
    3c18:	f383 8812 	msr	BASEPRI_MAX, r3
    3c1c:	f3bf 8f6f 	isb	sy
	pending_current = _current;
    3c20:	4f11      	ldr	r7, [pc, #68]	; (3c68 <z_tick_sleep+0x8c>)
    3c22:	4b12      	ldr	r3, [pc, #72]	; (3c6c <z_tick_sleep+0x90>)
    3c24:	68b8      	ldr	r0, [r7, #8]
    3c26:	6018      	str	r0, [r3, #0]
	unready_thread(_current);
    3c28:	f7ff feea 	bl	3a00 <unready_thread>
	z_add_thread_timeout(_current, timeout);
    3c2c:	68b8      	ldr	r0, [r7, #8]
	z_add_timeout(&thread->base.timeout, z_thread_timeout, ticks);
    3c2e:	4910      	ldr	r1, [pc, #64]	; (3c70 <z_tick_sleep+0x94>)
    3c30:	4622      	mov	r2, r4
    3c32:	462b      	mov	r3, r5
    3c34:	3018      	adds	r0, #24
    3c36:	f000 f8f9 	bl	3e2c <z_add_timeout>
	z_mark_thread_as_suspended(_current);
    3c3a:	68ba      	ldr	r2, [r7, #8]
    3c3c:	7b53      	ldrb	r3, [r2, #13]
    3c3e:	f043 0310 	orr.w	r3, r3, #16
    3c42:	7353      	strb	r3, [r2, #13]
    3c44:	4640      	mov	r0, r8
    3c46:	f7fd fa11 	bl	106c <arch_swap>
	ticks = (k_ticks_t)expected_wakeup_ticks - sys_clock_tick_get_32();
    3c4a:	f000 ffb3 	bl	4bb4 <sys_clock_tick_get_32>
    3c4e:	1a30      	subs	r0, r6, r0
    3c50:	eb66 0106 	sbc.w	r1, r6, r6
	if (ticks > 0) {
    3c54:	2801      	cmp	r0, #1
    3c56:	f171 0300 	sbcs.w	r3, r1, #0
		return ticks;
    3c5a:	bfb8      	it	lt
    3c5c:	2000      	movlt	r0, #0
    3c5e:	e7c7      	b.n	3bf0 <z_tick_sleep+0x14>
		expected_wakeup_ticks = Z_TICK_ABS(ticks);
    3c60:	f06f 0601 	mvn.w	r6, #1
    3c64:	1a36      	subs	r6, r6, r0
    3c66:	e7d3      	b.n	3c10 <z_tick_sleep+0x34>
    3c68:	20000334 	.word	0x20000334
    3c6c:	2000035c 	.word	0x2000035c
    3c70:	00004a67 	.word	0x00004a67

00003c74 <z_impl_k_sleep>:

int32_t z_impl_k_sleep(k_timeout_t timeout)
{
    3c74:	b508      	push	{r3, lr}
    3c76:	460b      	mov	r3, r1
	__ASSERT(!arch_is_in_isr(), "");

	SYS_PORT_TRACING_FUNC_ENTER(k_thread, sleep, timeout);

	/* in case of K_FOREVER, we suspend */
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    3c78:	3301      	adds	r3, #1
    3c7a:	bf08      	it	eq
    3c7c:	f1b0 3fff 	cmpeq.w	r0, #4294967295
    3c80:	d106      	bne.n	3c90 <z_impl_k_sleep+0x1c>
		k_thread_suspend(_current);
    3c82:	4b08      	ldr	r3, [pc, #32]	; (3ca4 <z_impl_k_sleep+0x30>)
    3c84:	6898      	ldr	r0, [r3, #8]
	z_impl_k_thread_suspend(thread);
    3c86:	f7ff ff0d 	bl	3aa4 <z_impl_k_thread_suspend>

		SYS_PORT_TRACING_FUNC_EXIT(k_thread, sleep, timeout, (int32_t) K_TICKS_FOREVER);

		return (int32_t) K_TICKS_FOREVER;
    3c8a:	f04f 30ff 	mov.w	r0, #4294967295
	int32_t ret = k_ticks_to_ms_floor64(ticks);

	SYS_PORT_TRACING_FUNC_EXIT(k_thread, sleep, timeout, ret);

	return ret;
}
    3c8e:	bd08      	pop	{r3, pc}
	ticks = z_tick_sleep(ticks);
    3c90:	f7ff ffa4 	bl	3bdc <z_tick_sleep>
			return (t * to_hz + off) / from_hz;
    3c94:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
    3c98:	fb80 2303 	smull	r2, r3, r0, r3
    3c9c:	0bd0      	lsrs	r0, r2, #15
    3c9e:	ea40 4043 	orr.w	r0, r0, r3, lsl #17
	return ret;
    3ca2:	e7f4      	b.n	3c8e <z_impl_k_sleep+0x1a>
    3ca4:	20000334 	.word	0x20000334

00003ca8 <z_impl_z_current_get>:

#ifdef CONFIG_SMP
	arch_irq_unlock(k);
#endif
	return ret;
}
    3ca8:	4b01      	ldr	r3, [pc, #4]	; (3cb0 <z_impl_z_current_get+0x8>)
    3caa:	6898      	ldr	r0, [r3, #8]
    3cac:	4770      	bx	lr
    3cae:	bf00      	nop
    3cb0:	20000334 	.word	0x20000334

00003cb4 <z_thread_abort>:
#endif
	}
}

void z_thread_abort(struct k_thread *thread)
{
    3cb4:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    3cb8:	4604      	mov	r4, r0
    3cba:	f04f 0320 	mov.w	r3, #32
    3cbe:	f3ef 8611 	mrs	r6, BASEPRI
    3cc2:	f383 8812 	msr	BASEPRI_MAX, r3
    3cc6:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&sched_spinlock);

	if ((thread->base.thread_state & _THREAD_DEAD) != 0U) {
    3cca:	7b43      	ldrb	r3, [r0, #13]
    3ccc:	071a      	lsls	r2, r3, #28
    3cce:	d505      	bpl.n	3cdc <z_thread_abort+0x28>
	__asm__ volatile(
    3cd0:	f386 8811 	msr	BASEPRI, r6
    3cd4:	f3bf 8f6f 	isb	sy
	if (thread == _current && !arch_is_in_isr()) {
		z_swap(&sched_spinlock, key);
		__ASSERT(false, "aborted _current back from dead");
	}
	k_spin_unlock(&sched_spinlock, key);
}
    3cd8:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		thread->base.thread_state &= ~_THREAD_ABORTING;
    3cdc:	f023 0220 	bic.w	r2, r3, #32
    3ce0:	f042 0108 	orr.w	r1, r2, #8
		if (z_is_thread_queued(thread)) {
    3ce4:	09d2      	lsrs	r2, r2, #7
    3ce6:	d120      	bne.n	3d2a <z_thread_abort+0x76>
		thread->base.thread_state &= ~_THREAD_ABORTING;
    3ce8:	7341      	strb	r1, [r0, #13]
		if (thread->base.pended_on != NULL) {
    3cea:	68a3      	ldr	r3, [r4, #8]
    3cec:	b113      	cbz	r3, 3cf4 <z_thread_abort+0x40>
			unpend_thread_no_timeout(thread);
    3cee:	4620      	mov	r0, r4
    3cf0:	f000 fe7f 	bl	49f2 <unpend_thread_no_timeout>
	return z_abort_timeout(&thread->base.timeout);
    3cf4:	f104 0018 	add.w	r0, r4, #24
    3cf8:	f000 ff1c 	bl	4b34 <z_abort_timeout>
}

static inline struct k_thread *z_waitq_head(_wait_q_t *w)
{
	return (struct k_thread *)sys_dlist_peek_head(&w->waitq);
    3cfc:	f104 0758 	add.w	r7, r4, #88	; 0x58
    3d00:	f04f 0800 	mov.w	r8, #0
	return list->head == list;
    3d04:	6da5      	ldr	r5, [r4, #88]	; 0x58
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3d06:	42bd      	cmp	r5, r7
    3d08:	d000      	beq.n	3d0c <z_thread_abort+0x58>
	while ((thread = z_waitq_head(wait_q)) != NULL) {
    3d0a:	b9b5      	cbnz	r5, 3d3a <z_thread_abort+0x86>
		update_cache(1);
    3d0c:	2001      	movs	r0, #1
    3d0e:	f7ff fd81 	bl	3814 <update_cache>
	if (thread == _current && !arch_is_in_isr()) {
    3d12:	4b10      	ldr	r3, [pc, #64]	; (3d54 <z_thread_abort+0xa0>)
    3d14:	689b      	ldr	r3, [r3, #8]
    3d16:	42a3      	cmp	r3, r4
    3d18:	d1da      	bne.n	3cd0 <z_thread_abort+0x1c>
    3d1a:	f3ef 8305 	mrs	r3, IPSR
    3d1e:	2b00      	cmp	r3, #0
    3d20:	d1d6      	bne.n	3cd0 <z_thread_abort+0x1c>
    3d22:	4630      	mov	r0, r6
    3d24:	f7fd f9a2 	bl	106c <arch_swap>
	return ret;
    3d28:	e7d2      	b.n	3cd0 <z_thread_abort+0x1c>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    3d2a:	f003 035f 	and.w	r3, r3, #95	; 0x5f
    3d2e:	f043 0308 	orr.w	r3, r3, #8
    3d32:	7343      	strb	r3, [r0, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    3d34:	f000 fe55 	bl	49e2 <sys_dlist_remove>
}
    3d38:	e7d7      	b.n	3cea <z_thread_abort+0x36>
		unpend_thread_no_timeout(thread);
    3d3a:	4628      	mov	r0, r5
    3d3c:	f000 fe59 	bl	49f2 <unpend_thread_no_timeout>
    3d40:	f105 0018 	add.w	r0, r5, #24
    3d44:	f000 fef6 	bl	4b34 <z_abort_timeout>
    3d48:	f8c5 8078 	str.w	r8, [r5, #120]	; 0x78
		ready_thread(thread);
    3d4c:	4628      	mov	r0, r5
    3d4e:	f7ff fe01 	bl	3954 <ready_thread>
    3d52:	e7d7      	b.n	3d04 <z_thread_abort+0x50>
    3d54:	20000334 	.word	0x20000334

00003d58 <z_data_copy>:
 * This routine copies the data section from ROM to RAM.
 *
 * @return N/A
 */
void z_data_copy(void)
{
    3d58:	b508      	push	{r3, lr}
	(void)memcpy(&__data_region_start, &__data_region_load_start,
		 __data_region_end - __data_region_start);
    3d5a:	4806      	ldr	r0, [pc, #24]	; (3d74 <z_data_copy+0x1c>)
	(void)memcpy(&__data_region_start, &__data_region_load_start,
    3d5c:	4a06      	ldr	r2, [pc, #24]	; (3d78 <z_data_copy+0x20>)
    3d5e:	4907      	ldr	r1, [pc, #28]	; (3d7c <z_data_copy+0x24>)
    3d60:	1a12      	subs	r2, r2, r0
    3d62:	f000 fb11 	bl	4388 <memcpy>
#else
	(void)memcpy(&_app_smem_start, &_app_smem_rom_start,
		 _app_smem_end - _app_smem_start);
#endif /* CONFIG_STACK_CANARIES */
#endif /* CONFIG_USERSPACE */
}
    3d66:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	(void)memcpy(&__ramfunc_start, &__ramfunc_load_start,
    3d6a:	4a05      	ldr	r2, [pc, #20]	; (3d80 <z_data_copy+0x28>)
    3d6c:	4905      	ldr	r1, [pc, #20]	; (3d84 <z_data_copy+0x2c>)
    3d6e:	4806      	ldr	r0, [pc, #24]	; (3d88 <z_data_copy+0x30>)
    3d70:	f000 bb0a 	b.w	4388 <memcpy>
    3d74:	20000000 	.word	0x20000000
    3d78:	20000098 	.word	0x20000098
    3d7c:	00004f88 	.word	0x00004f88
    3d80:	00000000 	.word	0x00000000
    3d84:	00004f88 	.word	0x00004f88
    3d88:	20000000 	.word	0x20000000

00003d8c <elapsed>:
	sys_dlist_remove(&t->node);
}

static int32_t elapsed(void)
{
	return announce_remaining == 0 ? sys_clock_elapsed() : 0U;
    3d8c:	4b03      	ldr	r3, [pc, #12]	; (3d9c <elapsed+0x10>)
    3d8e:	681b      	ldr	r3, [r3, #0]
    3d90:	b90b      	cbnz	r3, 3d96 <elapsed+0xa>
    3d92:	f7fe bc21 	b.w	25d8 <sys_clock_elapsed>
}
    3d96:	2000      	movs	r0, #0
    3d98:	4770      	bx	lr
    3d9a:	bf00      	nop
    3d9c:	20000368 	.word	0x20000368

00003da0 <remove_timeout>:
{
    3da0:	b530      	push	{r4, r5, lr}
    3da2:	6803      	ldr	r3, [r0, #0]
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    3da4:	b168      	cbz	r0, 3dc2 <remove_timeout+0x22>
    3da6:	4a0a      	ldr	r2, [pc, #40]	; (3dd0 <remove_timeout+0x30>)
	return (node == list->tail) ? NULL : node->next;
    3da8:	6852      	ldr	r2, [r2, #4]
    3daa:	4290      	cmp	r0, r2
    3dac:	d009      	beq.n	3dc2 <remove_timeout+0x22>
	if (next(t) != NULL) {
    3dae:	b143      	cbz	r3, 3dc2 <remove_timeout+0x22>
		next(t)->dticks += t->dticks;
    3db0:	e9d3 2104 	ldrd	r2, r1, [r3, #16]
    3db4:	e9d0 4504 	ldrd	r4, r5, [r0, #16]
    3db8:	1912      	adds	r2, r2, r4
    3dba:	eb45 0101 	adc.w	r1, r5, r1
    3dbe:	e9c3 2104 	strd	r2, r1, [r3, #16]
 * @return N/A
 */

static inline void sys_dlist_remove(sys_dnode_t *node)
{
	sys_dnode_t *const prev = node->prev;
    3dc2:	6842      	ldr	r2, [r0, #4]
	sys_dnode_t *const next = node->next;

	prev->next = next;
    3dc4:	6013      	str	r3, [r2, #0]
	next->prev = prev;
    3dc6:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    3dc8:	2300      	movs	r3, #0
	node->prev = NULL;
    3dca:	e9c0 3300 	strd	r3, r3, [r0]
}
    3dce:	bd30      	pop	{r4, r5, pc}
    3dd0:	20000080 	.word	0x20000080

00003dd4 <next_timeout>:

static int32_t next_timeout(void)
{
    3dd4:	b538      	push	{r3, r4, r5, lr}
	return list->head == list;
    3dd6:	4b13      	ldr	r3, [pc, #76]	; (3e24 <next_timeout+0x50>)
    3dd8:	681c      	ldr	r4, [r3, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3dda:	429c      	cmp	r4, r3
    3ddc:	bf08      	it	eq
    3dde:	2400      	moveq	r4, #0
	struct _timeout *to = first();
	int32_t ticks_elapsed = elapsed();
    3de0:	f7ff ffd4 	bl	3d8c <elapsed>
    3de4:	4605      	mov	r5, r0
	int32_t ret = to == NULL ? MAX_WAIT
    3de6:	b1bc      	cbz	r4, 3e18 <next_timeout+0x44>
		: CLAMP(to->dticks - ticks_elapsed, 0, MAX_WAIT);
    3de8:	e9d4 0104 	ldrd	r0, r1, [r4, #16]
    3dec:	1b40      	subs	r0, r0, r5
    3dee:	eb61 71e5 	sbc.w	r1, r1, r5, asr #31
	int32_t ret = to == NULL ? MAX_WAIT
    3df2:	2801      	cmp	r0, #1
    3df4:	f171 0300 	sbcs.w	r3, r1, #0
    3df8:	db11      	blt.n	3e1e <next_timeout+0x4a>
		: CLAMP(to->dticks - ticks_elapsed, 0, MAX_WAIT);
    3dfa:	f06f 4200 	mvn.w	r2, #2147483648	; 0x80000000
    3dfe:	2300      	movs	r3, #0
    3e00:	4282      	cmp	r2, r0
    3e02:	eb73 0401 	sbcs.w	r4, r3, r1
    3e06:	da00      	bge.n	3e0a <next_timeout+0x36>
    3e08:	4610      	mov	r0, r2

#ifdef CONFIG_TIMESLICING
	if (_current_cpu->slice_ticks && _current_cpu->slice_ticks < ret) {
    3e0a:	4b07      	ldr	r3, [pc, #28]	; (3e28 <next_timeout+0x54>)
    3e0c:	691b      	ldr	r3, [r3, #16]
    3e0e:	b113      	cbz	r3, 3e16 <next_timeout+0x42>
    3e10:	4298      	cmp	r0, r3
    3e12:	bfa8      	it	ge
    3e14:	4618      	movge	r0, r3
		ret = _current_cpu->slice_ticks;
	}
#endif
	return ret;
}
    3e16:	bd38      	pop	{r3, r4, r5, pc}
	int32_t ret = to == NULL ? MAX_WAIT
    3e18:	f06f 4000 	mvn.w	r0, #2147483648	; 0x80000000
    3e1c:	e7f5      	b.n	3e0a <next_timeout+0x36>
    3e1e:	2000      	movs	r0, #0
    3e20:	e7f3      	b.n	3e0a <next_timeout+0x36>
    3e22:	bf00      	nop
    3e24:	20000080 	.word	0x20000080
    3e28:	20000334 	.word	0x20000334

00003e2c <z_add_timeout>:

void z_add_timeout(struct _timeout *to, _timeout_func_t fn,
		   k_timeout_t timeout)
{
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    3e2c:	f1b3 3fff 	cmp.w	r3, #4294967295
    3e30:	bf08      	it	eq
    3e32:	f1b2 3fff 	cmpeq.w	r2, #4294967295
{
    3e36:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    3e3a:	4604      	mov	r4, r0
    3e3c:	4692      	mov	sl, r2
    3e3e:	469b      	mov	fp, r3
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    3e40:	d073      	beq.n	3f2a <z_add_timeout+0xfe>
#ifdef CONFIG_KERNEL_COHERENCE
	__ASSERT_NO_MSG(arch_mem_coherent(to));
#endif

	__ASSERT(!sys_dnode_is_linked(&to->node), "");
	to->fn = fn;
    3e42:	6081      	str	r1, [r0, #8]
	__asm__ volatile(
    3e44:	f04f 0320 	mov.w	r3, #32
    3e48:	f3ef 8511 	mrs	r5, BASEPRI
    3e4c:	f383 8812 	msr	BASEPRI_MAX, r3
    3e50:	f3bf 8f6f 	isb	sy

	LOCKED(&timeout_lock) {
		struct _timeout *t;

		if (IS_ENABLED(CONFIG_TIMEOUT_64BIT) &&
		    Z_TICK_ABS(timeout.ticks) >= 0) {
    3e54:	f06f 0301 	mvn.w	r3, #1
    3e58:	ebb3 080a 	subs.w	r8, r3, sl
    3e5c:	f04f 32ff 	mov.w	r2, #4294967295
    3e60:	eb62 090b 	sbc.w	r9, r2, fp
		if (IS_ENABLED(CONFIG_TIMEOUT_64BIT) &&
    3e64:	f1b8 0f00 	cmp.w	r8, #0
    3e68:	f179 0100 	sbcs.w	r1, r9, #0
    3e6c:	db1c      	blt.n	3ea8 <z_add_timeout+0x7c>
			k_ticks_t ticks = Z_TICK_ABS(timeout.ticks) - curr_tick;
    3e6e:	4830      	ldr	r0, [pc, #192]	; (3f30 <z_add_timeout+0x104>)
    3e70:	e9d0 1000 	ldrd	r1, r0, [r0]
    3e74:	1a5b      	subs	r3, r3, r1
    3e76:	eb62 0200 	sbc.w	r2, r2, r0

			to->dticks = MAX(1, ticks);
    3e7a:	ebb3 060a 	subs.w	r6, r3, sl
    3e7e:	eb62 070b 	sbc.w	r7, r2, fp
    3e82:	2e01      	cmp	r6, #1
    3e84:	f177 0300 	sbcs.w	r3, r7, #0
    3e88:	bfbc      	itt	lt
    3e8a:	2601      	movlt	r6, #1
    3e8c:	2700      	movlt	r7, #0
    3e8e:	e9c4 6704 	strd	r6, r7, [r4, #16]
	return list->head == list;
    3e92:	4a28      	ldr	r2, [pc, #160]	; (3f34 <z_add_timeout+0x108>)
    3e94:	e9d2 3c00 	ldrd	r3, ip, [r2]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3e98:	4293      	cmp	r3, r2
    3e9a:	d11e      	bne.n	3eda <z_add_timeout+0xae>
	node->prev = tail;
    3e9c:	e9c4 2c00 	strd	r2, ip, [r4]
	tail->next = node;
    3ea0:	f8cc 4000 	str.w	r4, [ip]
	list->tail = node;
    3ea4:	6054      	str	r4, [r2, #4]
}
    3ea6:	e02d      	b.n	3f04 <z_add_timeout+0xd8>
		} else {
			to->dticks = timeout.ticks + 1 + elapsed();
    3ea8:	f7ff ff70 	bl	3d8c <elapsed>
    3eac:	f11a 0301 	adds.w	r3, sl, #1
    3eb0:	9300      	str	r3, [sp, #0]
    3eb2:	f14b 0300 	adc.w	r3, fp, #0
    3eb6:	9301      	str	r3, [sp, #4]
    3eb8:	e9dd 2300 	ldrd	r2, r3, [sp]
    3ebc:	1812      	adds	r2, r2, r0
    3ebe:	eb43 73e0 	adc.w	r3, r3, r0, asr #31
    3ec2:	e9c4 2304 	strd	r2, r3, [r4, #16]
    3ec6:	e7e4      	b.n	3e92 <z_add_timeout+0x66>
			if (t->dticks > to->dticks) {
				t->dticks -= to->dticks;
				sys_dlist_insert(&t->node, &to->node);
				break;
			}
			to->dticks -= t->dticks;
    3ec8:	ebb6 0008 	subs.w	r0, r6, r8
    3ecc:	eb67 0109 	sbc.w	r1, r7, r9
	return (node == list->tail) ? NULL : node->next;
    3ed0:	4563      	cmp	r3, ip
    3ed2:	e9c4 0104 	strd	r0, r1, [r4, #16]
    3ed6:	d0e1      	beq.n	3e9c <z_add_timeout+0x70>
    3ed8:	681b      	ldr	r3, [r3, #0]
		for (t = first(); t != NULL; t = next(t)) {
    3eda:	2b00      	cmp	r3, #0
    3edc:	d0de      	beq.n	3e9c <z_add_timeout+0x70>
			if (t->dticks > to->dticks) {
    3ede:	e9d3 8904 	ldrd	r8, r9, [r3, #16]
    3ee2:	e9d4 6704 	ldrd	r6, r7, [r4, #16]
    3ee6:	4546      	cmp	r6, r8
    3ee8:	eb77 0109 	sbcs.w	r1, r7, r9
    3eec:	daec      	bge.n	3ec8 <z_add_timeout+0x9c>
				t->dticks -= to->dticks;
    3eee:	ebb8 0006 	subs.w	r0, r8, r6
    3ef2:	eb69 0107 	sbc.w	r1, r9, r7
    3ef6:	e9c3 0104 	strd	r0, r1, [r3, #16]
	sys_dnode_t *const prev = successor->prev;
    3efa:	6859      	ldr	r1, [r3, #4]
	node->next = successor;
    3efc:	e9c4 3100 	strd	r3, r1, [r4]
	prev->next = node;
    3f00:	600c      	str	r4, [r1, #0]
	successor->prev = node;
    3f02:	605c      	str	r4, [r3, #4]
	return list->head == list;
    3f04:	6813      	ldr	r3, [r2, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3f06:	4293      	cmp	r3, r2
    3f08:	d00b      	beq.n	3f22 <z_add_timeout+0xf6>

		if (t == NULL) {
			sys_dlist_append(&timeout_list, &to->node);
		}

		if (to == first()) {
    3f0a:	429c      	cmp	r4, r3
    3f0c:	d109      	bne.n	3f22 <z_add_timeout+0xf6>
			 * last announcement, and slice_ticks is based
			 * on that. It means that the time remaining for
			 * the next announcement can be less than
			 * slice_ticks.
			 */
			int32_t next_time = next_timeout();
    3f0e:	f7ff ff61 	bl	3dd4 <next_timeout>

			if (next_time == 0 ||
    3f12:	b118      	cbz	r0, 3f1c <z_add_timeout+0xf0>
			    _current_cpu->slice_ticks != next_time) {
    3f14:	4b08      	ldr	r3, [pc, #32]	; (3f38 <z_add_timeout+0x10c>)
			if (next_time == 0 ||
    3f16:	691b      	ldr	r3, [r3, #16]
    3f18:	4283      	cmp	r3, r0
    3f1a:	d002      	beq.n	3f22 <z_add_timeout+0xf6>
				sys_clock_set_timeout(next_time, false);
    3f1c:	2100      	movs	r1, #0
    3f1e:	f7fe fb2b 	bl	2578 <sys_clock_set_timeout>
	__asm__ volatile(
    3f22:	f385 8811 	msr	BASEPRI, r5
    3f26:	f3bf 8f6f 	isb	sy
#else
			sys_clock_set_timeout(next_timeout(), false);
#endif	/* CONFIG_TIMESLICING */
		}
	}
}
    3f2a:	b003      	add	sp, #12
    3f2c:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    3f30:	200001b8 	.word	0x200001b8
    3f34:	20000080 	.word	0x20000080
    3f38:	20000334 	.word	0x20000334

00003f3c <sys_clock_announce>:
		}
	}
}

void sys_clock_announce(int32_t ticks)
{
    3f3c:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    3f40:	4606      	mov	r6, r0
#ifdef CONFIG_TIMESLICING
	z_time_slice(ticks);
    3f42:	f7ff fcc5 	bl	38d0 <z_time_slice>
	__asm__ volatile(
    3f46:	f04f 0320 	mov.w	r3, #32
    3f4a:	f3ef 8411 	mrs	r4, BASEPRI
    3f4e:	f383 8812 	msr	BASEPRI_MAX, r3
    3f52:	f3bf 8f6f 	isb	sy
#endif

	k_spinlock_key_t key = k_spin_lock(&timeout_lock);

	announce_remaining = ticks;
    3f56:	4d2c      	ldr	r5, [pc, #176]	; (4008 <sys_clock_announce+0xcc>)
    3f58:	f8df a0b0 	ldr.w	sl, [pc, #176]	; 400c <sys_clock_announce+0xd0>
	return list->head == list;
    3f5c:	f8df b0b0 	ldr.w	fp, [pc, #176]	; 4010 <sys_clock_announce+0xd4>
    3f60:	602e      	str	r6, [r5, #0]

	while (first() != NULL && first()->dticks <= announce_remaining) {
    3f62:	4651      	mov	r1, sl
    3f64:	f8d5 c000 	ldr.w	ip, [r5]
    3f68:	f8db 0000 	ldr.w	r0, [fp]
    3f6c:	4662      	mov	r2, ip
    3f6e:	17d3      	asrs	r3, r2, #31
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3f70:	4558      	cmp	r0, fp
    3f72:	e9da 8900 	ldrd	r8, r9, [sl]
    3f76:	e9cd 2300 	strd	r2, r3, [sp]
    3f7a:	d00d      	beq.n	3f98 <sys_clock_announce+0x5c>
    3f7c:	b160      	cbz	r0, 3f98 <sys_clock_announce+0x5c>
    3f7e:	e9d0 6704 	ldrd	r6, r7, [r0, #16]
    3f82:	45b4      	cmp	ip, r6
    3f84:	41bb      	sbcs	r3, r7
    3f86:	da1e      	bge.n	3fc6 <sys_clock_announce+0x8a>
		t->fn(t);
		key = k_spin_lock(&timeout_lock);
	}

	if (first() != NULL) {
		first()->dticks -= announce_remaining;
    3f88:	9b00      	ldr	r3, [sp, #0]
    3f8a:	ebb6 0c03 	subs.w	ip, r6, r3
    3f8e:	9b01      	ldr	r3, [sp, #4]
    3f90:	eb67 0603 	sbc.w	r6, r7, r3
    3f94:	e9c0 c604 	strd	ip, r6, [r0, #16]
	}

	curr_tick += announce_remaining;
    3f98:	9b00      	ldr	r3, [sp, #0]
    3f9a:	eb13 0208 	adds.w	r2, r3, r8
    3f9e:	9b01      	ldr	r3, [sp, #4]
	announce_remaining = 0;
    3fa0:	f04f 0600 	mov.w	r6, #0
	curr_tick += announce_remaining;
    3fa4:	eb43 0309 	adc.w	r3, r3, r9
    3fa8:	e9c1 2300 	strd	r2, r3, [r1]
	announce_remaining = 0;
    3fac:	602e      	str	r6, [r5, #0]

	sys_clock_set_timeout(next_timeout(), false);
    3fae:	f7ff ff11 	bl	3dd4 <next_timeout>
    3fb2:	4631      	mov	r1, r6
    3fb4:	f7fe fae0 	bl	2578 <sys_clock_set_timeout>
	__asm__ volatile(
    3fb8:	f384 8811 	msr	BASEPRI, r4
    3fbc:	f3bf 8f6f 	isb	sy

	k_spin_unlock(&timeout_lock, key);
}
    3fc0:	b003      	add	sp, #12
    3fc2:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		curr_tick += dt;
    3fc6:	eb18 0806 	adds.w	r8, r8, r6
		t->dticks = 0;
    3fca:	f04f 0200 	mov.w	r2, #0
    3fce:	f04f 0300 	mov.w	r3, #0
		curr_tick += dt;
    3fd2:	eb49 79e6 	adc.w	r9, r9, r6, asr #31
		t->dticks = 0;
    3fd6:	e9c0 2304 	strd	r2, r3, [r0, #16]
		announce_remaining -= dt;
    3fda:	ebac 0606 	sub.w	r6, ip, r6
		curr_tick += dt;
    3fde:	e9ca 8900 	strd	r8, r9, [sl]
		announce_remaining -= dt;
    3fe2:	602e      	str	r6, [r5, #0]
		remove_timeout(t);
    3fe4:	f7ff fedc 	bl	3da0 <remove_timeout>
    3fe8:	f384 8811 	msr	BASEPRI, r4
    3fec:	f3bf 8f6f 	isb	sy
		t->fn(t);
    3ff0:	6883      	ldr	r3, [r0, #8]
    3ff2:	4798      	blx	r3
	__asm__ volatile(
    3ff4:	f04f 0320 	mov.w	r3, #32
    3ff8:	f3ef 8411 	mrs	r4, BASEPRI
    3ffc:	f383 8812 	msr	BASEPRI_MAX, r3
    4000:	f3bf 8f6f 	isb	sy

	/* Note that we need to use the underlying arch-specific lock
	 * implementation.  The "irq_lock()" API in SMP context is
	 * actually a wrapper for a global spinlock!
	 */
	k.key = arch_irq_lock();
    4004:	4901      	ldr	r1, [pc, #4]	; (400c <sys_clock_announce+0xd0>)
#endif

#ifdef CONFIG_SPIN_VALIDATE
	z_spin_lock_set_owner(l);
#endif
	return k;
    4006:	e7ad      	b.n	3f64 <sys_clock_announce+0x28>
    4008:	20000368 	.word	0x20000368
    400c:	200001b8 	.word	0x200001b8
    4010:	20000080 	.word	0x20000080

00004014 <sys_clock_tick_get>:

int64_t sys_clock_tick_get(void)
{
    4014:	b510      	push	{r4, lr}
    4016:	f04f 0320 	mov.w	r3, #32
    401a:	f3ef 8411 	mrs	r4, BASEPRI
    401e:	f383 8812 	msr	BASEPRI_MAX, r3
    4022:	f3bf 8f6f 	isb	sy
	uint64_t t = 0U;

	LOCKED(&timeout_lock) {
		t = curr_tick + sys_clock_elapsed();
    4026:	f7fe fad7 	bl	25d8 <sys_clock_elapsed>
    402a:	4b06      	ldr	r3, [pc, #24]	; (4044 <sys_clock_tick_get+0x30>)
    402c:	e9d3 2300 	ldrd	r2, r3, [r3]
    4030:	1812      	adds	r2, r2, r0
    4032:	f143 0300 	adc.w	r3, r3, #0
	__asm__ volatile(
    4036:	f384 8811 	msr	BASEPRI, r4
    403a:	f3bf 8f6f 	isb	sy
	}
	return t;
}
    403e:	4610      	mov	r0, r2
    4040:	4619      	mov	r1, r3
    4042:	bd10      	pop	{r4, pc}
    4044:	200001b8 	.word	0x200001b8

00004048 <boot_banner>:
		k_busy_wait(CONFIG_BOOT_DELAY * USEC_PER_MSEC);
	}

#if defined(CONFIG_BOOT_BANNER)
#ifdef BUILD_VERSION
	printk("*** Booting Zephyr OS build %s %s ***\n",
    4048:	4a02      	ldr	r2, [pc, #8]	; (4054 <boot_banner+0xc>)
    404a:	4903      	ldr	r1, [pc, #12]	; (4058 <boot_banner+0x10>)
    404c:	4803      	ldr	r0, [pc, #12]	; (405c <boot_banner+0x14>)
    404e:	f000 b847 	b.w	40e0 <printk>
    4052:	bf00      	nop
    4054:	00004ef5 	.word	0x00004ef5
    4058:	00004f52 	.word	0x00004f52
    405c:	00004f61 	.word	0x00004f61

00004060 <z_sys_init_run_level>:
		/* End marker */
		__init_end,
	};
	const struct init_entry *entry;

	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    4060:	4b0e      	ldr	r3, [pc, #56]	; (409c <z_sys_init_run_level+0x3c>)
{
    4062:	b570      	push	{r4, r5, r6, lr}
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    4064:	f853 4020 	ldr.w	r4, [r3, r0, lsl #2]
    4068:	3001      	adds	r0, #1
    406a:	f853 6020 	ldr.w	r6, [r3, r0, lsl #2]
    406e:	42a6      	cmp	r6, r4
    4070:	d800      	bhi.n	4074 <z_sys_init_run_level+0x14>
				dev->state->init_res = rc;
			}
			dev->state->initialized = true;
		}
	}
}
    4072:	bd70      	pop	{r4, r5, r6, pc}
		int rc = entry->init(dev);
    4074:	e9d4 3500 	ldrd	r3, r5, [r4]
    4078:	4628      	mov	r0, r5
    407a:	4798      	blx	r3
		if (dev != NULL) {
    407c:	b165      	cbz	r5, 4098 <z_sys_init_run_level+0x38>
			if (rc != 0) {
    407e:	68eb      	ldr	r3, [r5, #12]
    4080:	b130      	cbz	r0, 4090 <z_sys_init_run_level+0x30>
				if (rc < 0) {
    4082:	2800      	cmp	r0, #0
    4084:	bfb8      	it	lt
    4086:	4240      	neglt	r0, r0
				dev->state->init_res = rc;
    4088:	28ff      	cmp	r0, #255	; 0xff
    408a:	bfa8      	it	ge
    408c:	20ff      	movge	r0, #255	; 0xff
    408e:	7018      	strb	r0, [r3, #0]
			dev->state->initialized = true;
    4090:	785a      	ldrb	r2, [r3, #1]
    4092:	f042 0201 	orr.w	r2, r2, #1
    4096:	705a      	strb	r2, [r3, #1]
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    4098:	3408      	adds	r4, #8
    409a:	e7e8      	b.n	406e <z_sys_init_run_level+0xe>
    409c:	00004ed4 	.word	0x00004ed4

000040a0 <sys_notify_validate>:

int sys_notify_validate(struct sys_notify *notify)
{
	int rv = 0;

	if (notify == NULL) {
    40a0:	4603      	mov	r3, r0
    40a2:	b158      	cbz	r0, 40bc <sys_notify_validate+0x1c>
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    40a4:	6842      	ldr	r2, [r0, #4]
	return method & SYS_NOTIFY_METHOD_MASK;
    40a6:	f002 0203 	and.w	r2, r2, #3
		return -EINVAL;
	}

	/* Validate configuration based on mode */
	switch (sys_notify_get_method(notify)) {
    40aa:	2a01      	cmp	r2, #1
    40ac:	d003      	beq.n	40b6 <sys_notify_validate+0x16>
    40ae:	2a03      	cmp	r2, #3
    40b0:	d104      	bne.n	40bc <sys_notify_validate+0x1c>
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		if (notify->method.callback == NULL) {
    40b2:	6802      	ldr	r2, [r0, #0]
    40b4:	b112      	cbz	r2, 40bc <sys_notify_validate+0x1c>
		break;
	}

	/* Clear the result here instead of in all callers. */
	if (rv == 0) {
		notify->result = 0;
    40b6:	2000      	movs	r0, #0
    40b8:	6098      	str	r0, [r3, #8]
    40ba:	4770      	bx	lr
		return -EINVAL;
    40bc:	f06f 0015 	mvn.w	r0, #21
	}

	return rv;
}
    40c0:	4770      	bx	lr

000040c2 <sys_notify_finalize>:
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    40c2:	6842      	ldr	r2, [r0, #4]
	uint32_t method = sys_notify_get_method(notify);

	/* Store the result and capture secondary notification
	 * information.
	 */
	notify->result = res;
    40c4:	6081      	str	r1, [r0, #8]
	return method & SYS_NOTIFY_METHOD_MASK;
    40c6:	f002 0203 	and.w	r2, r2, #3
	switch (method) {
    40ca:	2a03      	cmp	r2, #3
    40cc:	f04f 0200 	mov.w	r2, #0
{
    40d0:	4603      	mov	r3, r0
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		rv = notify->method.callback;
    40d2:	bf0c      	ite	eq
    40d4:	6800      	ldreq	r0, [r0, #0]
	sys_notify_generic_callback rv = NULL;
    40d6:	4610      	movne	r0, r2
	/* Mark completion by clearing the flags field to the
	 * completed state, releasing any spin-waiters, then complete
	 * secondary notification.
	 */
	compiler_barrier();
	notify->flags = SYS_NOTIFY_METHOD_COMPLETED;
    40d8:	605a      	str	r2, [r3, #4]
	if (IS_ENABLED(CONFIG_POLL) && (sig != NULL)) {
		k_poll_signal_raise(sig, res);
	}

	return rv;
}
    40da:	4770      	bx	lr

000040dc <arch_printk_char_out>:
}
    40dc:	2000      	movs	r0, #0
    40de:	4770      	bx	lr

000040e0 <printk>:
 *
 * @return N/A
 */

void printk(const char *fmt, ...)
{
    40e0:	b40f      	push	{r0, r1, r2, r3}
    40e2:	b507      	push	{r0, r1, r2, lr}
    40e4:	a904      	add	r1, sp, #16
    40e6:	f851 0b04 	ldr.w	r0, [r1], #4
	va_list ap;

	va_start(ap, fmt);
    40ea:	9101      	str	r1, [sp, #4]

	if (IS_ENABLED(CONFIG_LOG_PRINTK)) {
		log_printk(fmt, ap);
	} else {
		vprintk(fmt, ap);
    40ec:	f7fc f984 	bl	3f8 <vprintk>
	}
	va_end(ap);
}
    40f0:	b003      	add	sp, #12
    40f2:	f85d eb04 	ldr.w	lr, [sp], #4
    40f6:	b004      	add	sp, #16
    40f8:	4770      	bx	lr

000040fa <process_recheck>:
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    40fa:	8b03      	ldrh	r3, [r0, #24]
	if ((state == ONOFF_STATE_OFF)
    40fc:	f013 0307 	ands.w	r3, r3, #7
    4100:	d105      	bne.n	410e <process_recheck+0x14>
	    && !sys_slist_is_empty(&mgr->clients)) {
    4102:	6803      	ldr	r3, [r0, #0]
    4104:	2b00      	cmp	r3, #0
		evt = EVT_START;
    4106:	bf0c      	ite	eq
    4108:	2000      	moveq	r0, #0
    410a:	2003      	movne	r0, #3
    410c:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ON)
    410e:	2b02      	cmp	r3, #2
    4110:	d105      	bne.n	411e <process_recheck+0x24>
		   && (mgr->refs == 0U)) {
    4112:	8b43      	ldrh	r3, [r0, #26]
    4114:	2b00      	cmp	r3, #0
		evt = EVT_STOP;
    4116:	bf14      	ite	ne
    4118:	2000      	movne	r0, #0
    411a:	2004      	moveq	r0, #4
    411c:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ERROR)
    411e:	2b01      	cmp	r3, #1
    4120:	d105      	bne.n	412e <process_recheck+0x34>
		   && !sys_slist_is_empty(&mgr->clients)) {
    4122:	6803      	ldr	r3, [r0, #0]
    4124:	2b00      	cmp	r3, #0
		evt = EVT_RESET;
    4126:	bf0c      	ite	eq
    4128:	2000      	moveq	r0, #0
    412a:	2005      	movne	r0, #5
    412c:	4770      	bx	lr
	int evt = EVT_NOP;
    412e:	2000      	movs	r0, #0
}
    4130:	4770      	bx	lr

00004132 <notify_one>:
{
    4132:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    4136:	460d      	mov	r5, r1
    4138:	4607      	mov	r7, r0
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    413a:	4619      	mov	r1, r3
    413c:	1d28      	adds	r0, r5, #4
{
    413e:	4690      	mov	r8, r2
    4140:	461e      	mov	r6, r3
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    4142:	f7ff ffbe 	bl	40c2 <sys_notify_finalize>
	if (cb) {
    4146:	4604      	mov	r4, r0
    4148:	b138      	cbz	r0, 415a <notify_one+0x28>
		cb(mgr, cli, state, res);
    414a:	4633      	mov	r3, r6
    414c:	4642      	mov	r2, r8
    414e:	4629      	mov	r1, r5
    4150:	4638      	mov	r0, r7
    4152:	46a4      	mov	ip, r4
}
    4154:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
		cb(mgr, cli, state, res);
    4158:	4760      	bx	ip
}
    415a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

0000415e <transition_complete>:
{
    415e:	b410      	push	{r4}
	__asm__ volatile(
    4160:	f04f 0420 	mov.w	r4, #32
    4164:	f3ef 8211 	mrs	r2, BASEPRI
    4168:	f384 8812 	msr	BASEPRI_MAX, r4
    416c:	f3bf 8f6f 	isb	sy
	mgr->last_res = res;
    4170:	6141      	str	r1, [r0, #20]
}
    4172:	bc10      	pop	{r4}
	process_event(mgr, EVT_COMPLETE, key);
    4174:	2101      	movs	r1, #1
    4176:	f7fc b94d 	b.w	414 <process_event>

0000417a <validate_args>:
{
    417a:	b510      	push	{r4, lr}
    417c:	460c      	mov	r4, r1
	if ((mgr == NULL) || (cli == NULL)) {
    417e:	b140      	cbz	r0, 4192 <validate_args+0x18>
    4180:	b139      	cbz	r1, 4192 <validate_args+0x18>
	int rv = sys_notify_validate(&cli->notify);
    4182:	1d08      	adds	r0, r1, #4
    4184:	f7ff ff8c 	bl	40a0 <sys_notify_validate>
	if ((rv == 0)
    4188:	b928      	cbnz	r0, 4196 <validate_args+0x1c>
	    && ((cli->notify.flags
    418a:	68a3      	ldr	r3, [r4, #8]
    418c:	f033 0303 	bics.w	r3, r3, #3
    4190:	d001      	beq.n	4196 <validate_args+0x1c>
		rv = -EINVAL;
    4192:	f06f 0015 	mvn.w	r0, #21
}
    4196:	bd10      	pop	{r4, pc}

00004198 <onoff_manager_init>:
{
    4198:	b538      	push	{r3, r4, r5, lr}
    419a:	460c      	mov	r4, r1
	if ((mgr == NULL)
    419c:	4605      	mov	r5, r0
    419e:	b158      	cbz	r0, 41b8 <onoff_manager_init+0x20>
	    || (transitions == NULL)
    41a0:	b151      	cbz	r1, 41b8 <onoff_manager_init+0x20>
	    || (transitions->start == NULL)
    41a2:	680b      	ldr	r3, [r1, #0]
    41a4:	b143      	cbz	r3, 41b8 <onoff_manager_init+0x20>
	    || (transitions->stop == NULL)) {
    41a6:	684b      	ldr	r3, [r1, #4]
    41a8:	b133      	cbz	r3, 41b8 <onoff_manager_init+0x20>
	*mgr = (struct onoff_manager)ONOFF_MANAGER_INITIALIZER(transitions);
    41aa:	221c      	movs	r2, #28
    41ac:	2100      	movs	r1, #0
    41ae:	f000 f8f6 	bl	439e <memset>
    41b2:	612c      	str	r4, [r5, #16]
	return 0;
    41b4:	2000      	movs	r0, #0
}
    41b6:	bd38      	pop	{r3, r4, r5, pc}
		return -EINVAL;
    41b8:	f06f 0015 	mvn.w	r0, #21
    41bc:	e7fb      	b.n	41b6 <onoff_manager_init+0x1e>

000041be <onoff_request>:

int onoff_request(struct onoff_manager *mgr,
		  struct onoff_client *cli)
{
    41be:	b570      	push	{r4, r5, r6, lr}
    41c0:	4604      	mov	r4, r0
    41c2:	460e      	mov	r6, r1
	bool add_client = false;        /* add client to pending list */
	bool start = false;             /* trigger a start transition */
	bool notify = false;            /* do client notification */
	int rv = validate_args(mgr, cli);
    41c4:	f7ff ffd9 	bl	417a <validate_args>

	if (rv < 0) {
    41c8:	1e05      	subs	r5, r0, #0
    41ca:	db31      	blt.n	4230 <onoff_request+0x72>
    41cc:	f04f 0320 	mov.w	r3, #32
    41d0:	f3ef 8111 	mrs	r1, BASEPRI
    41d4:	f383 8812 	msr	BASEPRI_MAX, r3
    41d8:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&mgr->lock);
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;

	/* Reject if this would overflow the reference count. */
	if (mgr->refs == SERVICE_REFS_MAX) {
    41dc:	8b63      	ldrh	r3, [r4, #26]
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    41de:	8b20      	ldrh	r0, [r4, #24]
	if (mgr->refs == SERVICE_REFS_MAX) {
    41e0:	f64f 75ff 	movw	r5, #65535	; 0xffff
    41e4:	42ab      	cmp	r3, r5
    41e6:	f000 0207 	and.w	r2, r0, #7
    41ea:	d02e      	beq.n	424a <onoff_request+0x8c>
		rv = -EAGAIN;
		goto out;
	}

	rv = state;
	if (state == ONOFF_STATE_ON) {
    41ec:	2a02      	cmp	r2, #2
    41ee:	d10e      	bne.n	420e <onoff_request+0x50>
		/* Increment reference count, notify in exit */
		notify = true;
		mgr->refs += 1U;
    41f0:	3301      	adds	r3, #1
    41f2:	8363      	strh	r3, [r4, #26]
	rv = state;
    41f4:	4615      	mov	r5, r2
		notify = true;
    41f6:	2301      	movs	r3, #1
	__asm__ volatile(
    41f8:	f381 8811 	msr	BASEPRI, r1
    41fc:	f3bf 8f6f 	isb	sy
	if (start) {
		process_event(mgr, EVT_RECHECK, key);
	} else {
		k_spin_unlock(&mgr->lock, key);

		if (notify) {
    4200:	b1b3      	cbz	r3, 4230 <onoff_request+0x72>
			notify_one(mgr, cli, state, 0);
    4202:	2300      	movs	r3, #0
    4204:	4631      	mov	r1, r6
    4206:	4620      	mov	r0, r4
    4208:	f7ff ff93 	bl	4132 <notify_one>
    420c:	e010      	b.n	4230 <onoff_request+0x72>
	} else if ((state == ONOFF_STATE_OFF)
    420e:	0783      	lsls	r3, r0, #30
    4210:	d001      	beq.n	4216 <onoff_request+0x58>
		   || (state == ONOFF_STATE_TO_ON)) {
    4212:	2a06      	cmp	r2, #6
    4214:	d10e      	bne.n	4234 <onoff_request+0x76>
	parent->next = child;
    4216:	2300      	movs	r3, #0
    4218:	6033      	str	r3, [r6, #0]
Z_GENLIST_APPEND(slist, snode)
    421a:	6863      	ldr	r3, [r4, #4]
    421c:	b993      	cbnz	r3, 4244 <onoff_request+0x86>
	list->head = node;
    421e:	e9c4 6600 	strd	r6, r6, [r4]
	if (start) {
    4222:	4615      	mov	r5, r2
    4224:	b962      	cbnz	r2, 4240 <onoff_request+0x82>
		process_event(mgr, EVT_RECHECK, key);
    4226:	460a      	mov	r2, r1
    4228:	4620      	mov	r0, r4
    422a:	2102      	movs	r1, #2
    422c:	f7fc f8f2 	bl	414 <process_event>
		}
	}

	return rv;
}
    4230:	4628      	mov	r0, r5
    4232:	bd70      	pop	{r4, r5, r6, pc}
		rv = -EIO;
    4234:	2a05      	cmp	r2, #5
    4236:	bf0c      	ite	eq
    4238:	f06f 0585 	mvneq.w	r5, #133	; 0x85
    423c:	f06f 0504 	mvnne.w	r5, #4
    4240:	2300      	movs	r3, #0
    4242:	e7d9      	b.n	41f8 <onoff_request+0x3a>
	parent->next = child;
    4244:	601e      	str	r6, [r3, #0]
	list->tail = node;
    4246:	6066      	str	r6, [r4, #4]
}
    4248:	e7eb      	b.n	4222 <onoff_request+0x64>
		rv = -EAGAIN;
    424a:	f06f 050a 	mvn.w	r5, #10
    424e:	e7f7      	b.n	4240 <onoff_request+0x82>

00004250 <z_thread_entry>:
 * This routine does not return, and is marked as such so the compiler won't
 * generate preamble code that is only used by functions that actually return.
 */
FUNC_NORETURN void z_thread_entry(k_thread_entry_t entry,
				 void *p1, void *p2, void *p3)
{
    4250:	4604      	mov	r4, r0
    4252:	b508      	push	{r3, lr}
    4254:	4608      	mov	r0, r1
    4256:	4611      	mov	r1, r2
#ifdef CONFIG_THREAD_LOCAL_STORAGE
	z_tls_current = z_current_get();
#endif
	entry(p1, p2, p3);
    4258:	461a      	mov	r2, r3
    425a:	47a0      	blx	r4
	return z_impl_z_current_get();
    425c:	f7ff fd24 	bl	3ca8 <z_impl_z_current_get>
	z_impl_k_thread_abort(thread);
    4260:	f7fd f946 	bl	14f0 <z_impl_k_thread_abort>

00004264 <encode_uint>:
{
    4264:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    4268:	4699      	mov	r9, r3
	bool upcase = isupper((int)conv->specifier);
    426a:	78d3      	ldrb	r3, [r2, #3]
{
    426c:	4614      	mov	r4, r2
	switch (specifier) {
    426e:	2b6f      	cmp	r3, #111	; 0x6f
	return (int)(((unsigned)(a)-(unsigned)'A') < 26U);
    4270:	f1a3 0241 	sub.w	r2, r3, #65	; 0x41
{
    4274:	4606      	mov	r6, r0
    4276:	460f      	mov	r7, r1
    4278:	9201      	str	r2, [sp, #4]
	switch (specifier) {
    427a:	d02d      	beq.n	42d8 <encode_uint+0x74>
    427c:	d828      	bhi.n	42d0 <encode_uint+0x6c>
		return 16;
    427e:	2b58      	cmp	r3, #88	; 0x58
    4280:	bf14      	ite	ne
    4282:	250a      	movne	r5, #10
    4284:	2510      	moveq	r5, #16
	char *bp = bps + (bpe - bps);
    4286:	f8dd 8030 	ldr.w	r8, [sp, #48]	; 0x30
		unsigned int lsv = (unsigned int)(value % radix);
    428a:	46aa      	mov	sl, r5
    428c:	f04f 0b00 	mov.w	fp, #0
    4290:	4652      	mov	r2, sl
    4292:	465b      	mov	r3, fp
    4294:	4630      	mov	r0, r6
    4296:	4639      	mov	r1, r7
    4298:	f7fb ff20 	bl	dc <__aeabi_uldivmod>
		*--bp = (lsv <= 9) ? ('0' + lsv)
    429c:	2a09      	cmp	r2, #9
    429e:	b2d3      	uxtb	r3, r2
    42a0:	d81f      	bhi.n	42e2 <encode_uint+0x7e>
    42a2:	3330      	adds	r3, #48	; 0x30
	} while ((value != 0) && (bps < bp));
    42a4:	455f      	cmp	r7, fp
		*--bp = (lsv <= 9) ? ('0' + lsv)
    42a6:	b2db      	uxtb	r3, r3
	} while ((value != 0) && (bps < bp));
    42a8:	bf08      	it	eq
    42aa:	4556      	cmpeq	r6, sl
		*--bp = (lsv <= 9) ? ('0' + lsv)
    42ac:	f808 3d01 	strb.w	r3, [r8, #-1]!
	} while ((value != 0) && (bps < bp));
    42b0:	d301      	bcc.n	42b6 <encode_uint+0x52>
    42b2:	45c8      	cmp	r8, r9
    42b4:	d812      	bhi.n	42dc <encode_uint+0x78>
	if (conv->flag_hash) {
    42b6:	7823      	ldrb	r3, [r4, #0]
    42b8:	069b      	lsls	r3, r3, #26
    42ba:	d505      	bpl.n	42c8 <encode_uint+0x64>
		if (radix == 8) {
    42bc:	2d08      	cmp	r5, #8
    42be:	d116      	bne.n	42ee <encode_uint+0x8a>
			conv->altform_0 = true;
    42c0:	78a3      	ldrb	r3, [r4, #2]
    42c2:	f043 0308 	orr.w	r3, r3, #8
			conv->altform_0c = true;
    42c6:	70a3      	strb	r3, [r4, #2]
}
    42c8:	4640      	mov	r0, r8
    42ca:	b003      	add	sp, #12
    42cc:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
	switch (specifier) {
    42d0:	f003 03f7 	and.w	r3, r3, #247	; 0xf7
		return 16;
    42d4:	2b70      	cmp	r3, #112	; 0x70
    42d6:	e7d3      	b.n	4280 <encode_uint+0x1c>
	switch (specifier) {
    42d8:	2508      	movs	r5, #8
    42da:	e7d4      	b.n	4286 <encode_uint+0x22>
		value /= radix;
    42dc:	4606      	mov	r6, r0
    42de:	460f      	mov	r7, r1
    42e0:	e7d6      	b.n	4290 <encode_uint+0x2c>
		*--bp = (lsv <= 9) ? ('0' + lsv)
    42e2:	9a01      	ldr	r2, [sp, #4]
    42e4:	2a19      	cmp	r2, #25
    42e6:	bf94      	ite	ls
    42e8:	3337      	addls	r3, #55	; 0x37
    42ea:	3357      	addhi	r3, #87	; 0x57
    42ec:	e7da      	b.n	42a4 <encode_uint+0x40>
		} else if (radix == 16) {
    42ee:	2d10      	cmp	r5, #16
    42f0:	d1ea      	bne.n	42c8 <encode_uint+0x64>
			conv->altform_0c = true;
    42f2:	78a3      	ldrb	r3, [r4, #2]
    42f4:	f043 0310 	orr.w	r3, r3, #16
    42f8:	e7e5      	b.n	42c6 <encode_uint+0x62>

000042fa <outs>:
{
    42fa:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    42fe:	4607      	mov	r7, r0
    4300:	4688      	mov	r8, r1
    4302:	4615      	mov	r5, r2
    4304:	461e      	mov	r6, r3
	while ((sp < ep) || ((ep == NULL) && *sp)) {
    4306:	4614      	mov	r4, r2
    4308:	42b4      	cmp	r4, r6
    430a:	eba4 0005 	sub.w	r0, r4, r5
    430e:	d302      	bcc.n	4316 <outs+0x1c>
    4310:	b93e      	cbnz	r6, 4322 <outs+0x28>
    4312:	7823      	ldrb	r3, [r4, #0]
    4314:	b12b      	cbz	r3, 4322 <outs+0x28>
		int rc = out((int)*sp++, ctx);
    4316:	f814 0b01 	ldrb.w	r0, [r4], #1
    431a:	4641      	mov	r1, r8
    431c:	47b8      	blx	r7
		if (rc < 0) {
    431e:	2800      	cmp	r0, #0
    4320:	daf2      	bge.n	4308 <outs+0xe>
}
    4322:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00004326 <_ConfigAbsSyms>:
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_OUTPUT_DISASSEMBLY, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_OUTPUT_PRINT_MEMORY_USAGE, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_BUILD_OUTPUT_BIN, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_COMPAT_INCLUDES, 1);

GEN_ABS_SYM_END
    4326:	4770      	bx	lr

00004328 <pm_policy_next_state>:
		}
	}

error:
	LOG_DBG("No suitable power state found for cpu: %d!", cpu);
	return (struct pm_state_info){PM_STATE_ACTIVE, 0, 0};
    4328:	2200      	movs	r2, #0
    432a:	e9c0 2200 	strd	r2, r2, [r0]
    432e:	6082      	str	r2, [r0, #8]
}
    4330:	4770      	bx	lr

00004332 <z_arm_fatal_error>:
{

	if (esf != NULL) {
		esf_dump(esf);
	}
	z_fatal_error(reason, esf);
    4332:	f000 bb2e 	b.w	4992 <z_fatal_error>

00004336 <z_do_kernel_oops>:
 *   fault handler will executed insted of the SVC.
 *
 * @param esf exception frame
 */
void z_do_kernel_oops(const z_arch_esf_t *esf)
{
    4336:	4601      	mov	r1, r0
	z_fatal_error(reason, esf);
    4338:	6800      	ldr	r0, [r0, #0]
    433a:	f000 bb2a 	b.w	4992 <z_fatal_error>

0000433e <z_irq_spurious>:
 */
void z_irq_spurious(const void *unused)
{
	ARG_UNUSED(unused);

	z_arm_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
    433e:	2100      	movs	r1, #0
    4340:	2001      	movs	r0, #1
    4342:	f7ff bff6 	b.w	4332 <z_arm_fatal_error>

00004346 <z_arm_nmi>:
 *
 * @return N/A
 */

void z_arm_nmi(void)
{
    4346:	b508      	push	{r3, lr}
	handler();
    4348:	f7fc fe70 	bl	102c <z_SysNmiOnReset>
	z_arm_int_exit();
}
    434c:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	z_arm_int_exit();
    4350:	f7fc bf4c 	b.w	11ec <z_arm_exc_exit>

00004354 <strcpy>:

char *strcpy(char *ZRESTRICT d, const char *ZRESTRICT s)
{
	char *dest = d;

	while (*s != '\0') {
    4354:	3901      	subs	r1, #1
    4356:	4603      	mov	r3, r0
    4358:	f811 2f01 	ldrb.w	r2, [r1, #1]!
    435c:	b90a      	cbnz	r2, 4362 <strcpy+0xe>
		*d = *s;
		d++;
		s++;
	}

	*d = '\0';
    435e:	701a      	strb	r2, [r3, #0]

	return dest;
}
    4360:	4770      	bx	lr
		*d = *s;
    4362:	f803 2b01 	strb.w	r2, [r3], #1
		s++;
    4366:	e7f7      	b.n	4358 <strcpy+0x4>

00004368 <strlen>:
 *
 * @return number of bytes in string <s>
 */

size_t strlen(const char *s)
{
    4368:	4603      	mov	r3, r0
	size_t n = 0;
    436a:	2000      	movs	r0, #0

	while (*s != '\0') {
    436c:	5c1a      	ldrb	r2, [r3, r0]
    436e:	b902      	cbnz	r2, 4372 <strlen+0xa>
		s++;
		n++;
	}

	return n;
}
    4370:	4770      	bx	lr
		n++;
    4372:	3001      	adds	r0, #1
    4374:	e7fa      	b.n	436c <strlen+0x4>

00004376 <strnlen>:
 *
 * @return number of bytes in fixed-size string <s>
 */

size_t strnlen(const char *s, size_t maxlen)
{
    4376:	4603      	mov	r3, r0
	size_t n = 0;
    4378:	2000      	movs	r0, #0

	while (*s != '\0' && n < maxlen) {
    437a:	5c1a      	ldrb	r2, [r3, r0]
    437c:	b10a      	cbz	r2, 4382 <strnlen+0xc>
    437e:	4288      	cmp	r0, r1
    4380:	d100      	bne.n	4384 <strnlen+0xe>
		s++;
		n++;
	}

	return n;
}
    4382:	4770      	bx	lr
		n++;
    4384:	3001      	adds	r0, #1
    4386:	e7f8      	b.n	437a <strnlen+0x4>

00004388 <memcpy>:
 *
 * @return pointer to start of destination buffer
 */

void *memcpy(void *ZRESTRICT d, const void *ZRESTRICT s, size_t n)
{
    4388:	b510      	push	{r4, lr}
    438a:	1e43      	subs	r3, r0, #1
    438c:	440a      	add	r2, r1
	}
#endif

	/* do byte-sized copying until finished */

	while (n > 0) {
    438e:	4291      	cmp	r1, r2
    4390:	d100      	bne.n	4394 <memcpy+0xc>
		*(d_byte++) = *(s_byte++);
		n--;
	}

	return d;
}
    4392:	bd10      	pop	{r4, pc}
		*(d_byte++) = *(s_byte++);
    4394:	f811 4b01 	ldrb.w	r4, [r1], #1
    4398:	f803 4f01 	strb.w	r4, [r3, #1]!
		n--;
    439c:	e7f7      	b.n	438e <memcpy+0x6>

0000439e <memset>:
void *memset(void *buf, int c, size_t n)
{
	/* do byte-sized initialization until word-aligned or finished */

	unsigned char *d_byte = (unsigned char *)buf;
	unsigned char c_byte = (unsigned char)c;
    439e:	b2c9      	uxtb	r1, r1
	/* do byte-sized initialization until finished */

	d_byte = (unsigned char *)d_word;
#endif

	while (n > 0) {
    43a0:	4402      	add	r2, r0
	unsigned char *d_byte = (unsigned char *)buf;
    43a2:	4603      	mov	r3, r0
	while (n > 0) {
    43a4:	4293      	cmp	r3, r2
    43a6:	d100      	bne.n	43aa <memset+0xc>
		*(d_byte++) = c_byte;
		n--;
	}

	return buf;
}
    43a8:	4770      	bx	lr
		*(d_byte++) = c_byte;
    43aa:	f803 1b01 	strb.w	r1, [r3], #1
		n--;
    43ae:	e7f9      	b.n	43a4 <memset+0x6>

000043b0 <_stdout_hook_default>:
}
    43b0:	f04f 30ff 	mov.w	r0, #4294967295
    43b4:	4770      	bx	lr

000043b6 <pm_power_state_set>:
#include <logging/log.h>
LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);

/* Invoke Low Power/System Off specific Tasks */
__weak void pm_power_state_set(struct pm_state_info info)
{
    43b6:	b084      	sub	sp, #16
    43b8:	ab04      	add	r3, sp, #16
    43ba:	e903 0007 	stmdb	r3, {r0, r1, r2}
	switch (info.state) {
    43be:	f89d 3004 	ldrb.w	r3, [sp, #4]
    43c2:	2b06      	cmp	r3, #6
    43c4:	d108      	bne.n	43d8 <pm_power_state_set+0x22>
    p_reg->SYSTEMOFF = POWER_SYSTEMOFF_SYSTEMOFF_Enter;
    43c6:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    43ca:	2201      	movs	r2, #1
    43cc:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
  __ASM volatile ("dsb 0xF":::"memory");
    43d0:	f3bf 8f4f 	dsb	sy
        __WFE();
    43d4:	bf20      	wfe
    while (true)
    43d6:	e7fd      	b.n	43d4 <pm_power_state_set+0x1e>
		break;
	default:
		LOG_DBG("Unsupported power state %u", info.state);
		break;
	}
}
    43d8:	b004      	add	sp, #16
    43da:	4770      	bx	lr

000043dc <pm_power_state_exit_post_ops>:

/* Handle SOC specific activity after Low Power Mode Exit */
__weak void pm_power_state_exit_post_ops(struct pm_state_info info)
{
    43dc:	b084      	sub	sp, #16
    43de:	ab04      	add	r3, sp, #16
    43e0:	e903 0007 	stmdb	r3, {r0, r1, r2}
    43e4:	2300      	movs	r3, #0
    43e6:	f383 8811 	msr	BASEPRI, r3
    43ea:	f3bf 8f6f 	isb	sy
	/*
	 * System is now in active mode. Reenable interrupts which were disabled
	 * when OS started idling code.
	 */
	irq_unlock(0);
}
    43ee:	b004      	add	sp, #16
    43f0:	4770      	bx	lr

000043f2 <get_status>:
	return GET_STATUS(get_sub_data(dev, type)->flags);
    43f2:	6902      	ldr	r2, [r0, #16]
    43f4:	b2cb      	uxtb	r3, r1
    43f6:	210c      	movs	r1, #12
    43f8:	fb03 2101 	mla	r1, r3, r1, r2
    43fc:	6c08      	ldr	r0, [r1, #64]	; 0x40
}
    43fe:	f000 0007 	and.w	r0, r0, #7
    4402:	4770      	bx	lr

00004404 <set_off_state>:
	__asm__ volatile(
    4404:	f04f 0320 	mov.w	r3, #32
    4408:	f3ef 8211 	mrs	r2, BASEPRI
    440c:	f383 8812 	msr	BASEPRI_MAX, r3
    4410:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    4414:	6803      	ldr	r3, [r0, #0]
	if ((current_ctx != 0) && (current_ctx != ctx)) {
    4416:	f013 03c0 	ands.w	r3, r3, #192	; 0xc0
    441a:	d001      	beq.n	4420 <set_off_state+0x1c>
    441c:	428b      	cmp	r3, r1
    441e:	d107      	bne.n	4430 <set_off_state+0x2c>
		*flags = CLOCK_CONTROL_STATUS_OFF;
    4420:	2301      	movs	r3, #1
    4422:	6003      	str	r3, [r0, #0]
	int err = 0;
    4424:	2000      	movs	r0, #0
	__asm__ volatile(
    4426:	f382 8811 	msr	BASEPRI, r2
    442a:	f3bf 8f6f 	isb	sy
}
    442e:	4770      	bx	lr
		err = -EPERM;
    4430:	f04f 30ff 	mov.w	r0, #4294967295
    4434:	e7f7      	b.n	4426 <set_off_state+0x22>

00004436 <set_starting_state>:
{
    4436:	b510      	push	{r4, lr}
	__asm__ volatile(
    4438:	f04f 0320 	mov.w	r3, #32
    443c:	f3ef 8211 	mrs	r2, BASEPRI
    4440:	f383 8812 	msr	BASEPRI_MAX, r3
    4444:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    4448:	6803      	ldr	r3, [r0, #0]
	if ((*flags & (STATUS_MASK)) == CLOCK_CONTROL_STATUS_OFF) {
    444a:	f003 0407 	and.w	r4, r3, #7
    444e:	2c01      	cmp	r4, #1
    4450:	d106      	bne.n	4460 <set_starting_state+0x2a>
		*flags = CLOCK_CONTROL_STATUS_STARTING | ctx;
    4452:	6001      	str	r1, [r0, #0]
	int err = 0;
    4454:	2000      	movs	r0, #0
	__asm__ volatile(
    4456:	f382 8811 	msr	BASEPRI, r2
    445a:	f3bf 8f6f 	isb	sy
}
    445e:	bd10      	pop	{r4, pc}
	uint32_t current_ctx = GET_CTX(*flags);
    4460:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
	} else if (current_ctx != ctx) {
    4464:	428b      	cmp	r3, r1
		err = -EALREADY;
    4466:	bf14      	ite	ne
    4468:	f04f 30ff 	movne.w	r0, #4294967295
    446c:	f06f 0077 	mvneq.w	r0, #119	; 0x77
    4470:	e7f1      	b.n	4456 <set_starting_state+0x20>

00004472 <set_on_state>:
	__asm__ volatile(
    4472:	f04f 0320 	mov.w	r3, #32
    4476:	f3ef 8211 	mrs	r2, BASEPRI
    447a:	f383 8812 	msr	BASEPRI_MAX, r3
    447e:	f3bf 8f6f 	isb	sy
	*flags = CLOCK_CONTROL_STATUS_ON | GET_CTX(*flags);
    4482:	6803      	ldr	r3, [r0, #0]
    4484:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
    4488:	f043 0302 	orr.w	r3, r3, #2
    448c:	6003      	str	r3, [r0, #0]
	__asm__ volatile(
    448e:	f382 8811 	msr	BASEPRI, r2
    4492:	f3bf 8f6f 	isb	sy
}
    4496:	4770      	bx	lr

00004498 <onoff_started_callback>:
	return &data->mgr[type];
    4498:	6900      	ldr	r0, [r0, #16]
{
    449a:	b410      	push	{r4}
	return &data->mgr[type];
    449c:	b2cb      	uxtb	r3, r1
	notify(mgr, 0);
    449e:	241c      	movs	r4, #28
    44a0:	fb03 0004 	mla	r0, r3, r4, r0
    44a4:	2100      	movs	r1, #0
}
    44a6:	bc10      	pop	{r4}
	notify(mgr, 0);
    44a8:	4710      	bx	r2

000044aa <lfclk_stop>:
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
    44aa:	2000      	movs	r0, #0
    44ac:	f7fe baa4 	b.w	29f8 <nrfx_clock_stop>

000044b0 <blocking_start_callback>:
{
    44b0:	4610      	mov	r0, r2
		arch_syscall_invoke1(*(uintptr_t *)&sem, K_SYSCALL_K_SEM_GIVE);
		return;
	}
#endif
	compiler_barrier();
	z_impl_k_sem_give(sem);
    44b2:	f7ff b8f7 	b.w	36a4 <z_impl_k_sem_give>

000044b6 <api_stop>:
{
    44b6:	b538      	push	{r3, r4, r5, lr}
    44b8:	b2cc      	uxtb	r4, r1
	err = set_off_state(&subdata->flags, ctx);
    44ba:	230c      	movs	r3, #12
{
    44bc:	4605      	mov	r5, r0
	err = set_off_state(&subdata->flags, ctx);
    44be:	4363      	muls	r3, r4
    44c0:	6900      	ldr	r0, [r0, #16]
    44c2:	3340      	adds	r3, #64	; 0x40
    44c4:	2180      	movs	r1, #128	; 0x80
    44c6:	4418      	add	r0, r3
    44c8:	f7ff ff9c 	bl	4404 <set_off_state>
	if (err < 0) {
    44cc:	2800      	cmp	r0, #0
    44ce:	db05      	blt.n	44dc <api_stop+0x26>
	get_sub_config(dev, type)->stop();
    44d0:	6869      	ldr	r1, [r5, #4]
    44d2:	eb01 04c4 	add.w	r4, r1, r4, lsl #3
    44d6:	6863      	ldr	r3, [r4, #4]
    44d8:	4798      	blx	r3
	return 0;
    44da:	2000      	movs	r0, #0
}
    44dc:	bd38      	pop	{r3, r4, r5, pc}

000044de <api_start>:
{
    44de:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    44e2:	b2cd      	uxtb	r5, r1
	err = set_starting_state(&subdata->flags, ctx);
    44e4:	270c      	movs	r7, #12
	struct nrf_clock_control_sub_data *subdata = get_sub_data(dev, type);
    44e6:	6904      	ldr	r4, [r0, #16]
	err = set_starting_state(&subdata->flags, ctx);
    44e8:	436f      	muls	r7, r5
{
    44ea:	4606      	mov	r6, r0
	err = set_starting_state(&subdata->flags, ctx);
    44ec:	f107 0040 	add.w	r0, r7, #64	; 0x40
    44f0:	2180      	movs	r1, #128	; 0x80
    44f2:	4420      	add	r0, r4
{
    44f4:	4690      	mov	r8, r2
    44f6:	4699      	mov	r9, r3
	err = set_starting_state(&subdata->flags, ctx);
    44f8:	f7ff ff9d 	bl	4436 <set_starting_state>
	if (err < 0) {
    44fc:	2800      	cmp	r0, #0
    44fe:	db07      	blt.n	4510 <api_start+0x32>
	subdata->cb = cb;
    4500:	443c      	add	r4, r7
	subdata->user_data = user_data;
    4502:	e9c4 890e 	strd	r8, r9, [r4, #56]	; 0x38
	 get_sub_config(dev, type)->start();
    4506:	6873      	ldr	r3, [r6, #4]
    4508:	f853 3035 	ldr.w	r3, [r3, r5, lsl #3]
    450c:	4798      	blx	r3
	return 0;
    450e:	2000      	movs	r0, #0
}
    4510:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}

00004514 <gpio_nrfx_port_get_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    4514:	6843      	ldr	r3, [r0, #4]
    4516:	685b      	ldr	r3, [r3, #4]
    return p_reg->IN;
    4518:	f8d3 3510 	ldr.w	r3, [r3, #1296]	; 0x510
	*value = nrf_gpio_port_in_read(reg);
    451c:	600b      	str	r3, [r1, #0]
}
    451e:	2000      	movs	r0, #0
    4520:	4770      	bx	lr

00004522 <gpio_nrfx_port_set_masked_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    4522:	6843      	ldr	r3, [r0, #4]
    4524:	685b      	ldr	r3, [r3, #4]
    return p_reg->OUT;
    4526:	f8d3 0504 	ldr.w	r0, [r3, #1284]	; 0x504
	nrf_gpio_port_out_write(reg, value_tmp | (mask & value));
    452a:	4042      	eors	r2, r0
    452c:	400a      	ands	r2, r1
    452e:	4042      	eors	r2, r0
    p_reg->OUT = value;
    4530:	f8c3 2504 	str.w	r2, [r3, #1284]	; 0x504
}
    4534:	2000      	movs	r0, #0
    4536:	4770      	bx	lr

00004538 <gpio_nrfx_port_set_bits_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    4538:	6843      	ldr	r3, [r0, #4]
    453a:	685b      	ldr	r3, [r3, #4]
}
    453c:	2000      	movs	r0, #0
    p_reg->OUTSET = set_mask;
    453e:	f8c3 1508 	str.w	r1, [r3, #1288]	; 0x508
    4542:	4770      	bx	lr

00004544 <gpio_nrfx_port_clear_bits_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    4544:	6843      	ldr	r3, [r0, #4]
    4546:	685b      	ldr	r3, [r3, #4]
}
    4548:	2000      	movs	r0, #0
    p_reg->OUTCLR = clr_mask;
    454a:	f8c3 150c 	str.w	r1, [r3, #1292]	; 0x50c
    454e:	4770      	bx	lr

00004550 <gpio_nrfx_port_toggle_bits>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    4550:	6843      	ldr	r3, [r0, #4]
    4552:	685a      	ldr	r2, [r3, #4]
    return p_reg->OUT;
    4554:	f8d2 3504 	ldr.w	r3, [r2, #1284]	; 0x504
	nrf_gpio_port_out_write(reg, value ^ mask);
    4558:	404b      	eors	r3, r1
    p_reg->OUT = value;
    455a:	f8c2 3504 	str.w	r3, [r2, #1284]	; 0x504
}
    455e:	2000      	movs	r0, #0
    4560:	4770      	bx	lr

00004562 <gpio_nrfx_manage_callback>:
	return gpio_manage_callback(&get_port_data(port)->callbacks,
    4562:	6903      	ldr	r3, [r0, #16]
Z_GENLIST_IS_EMPTY(slist)
    4564:	6858      	ldr	r0, [r3, #4]
{
    4566:	b530      	push	{r4, r5, lr}
	if (!sys_slist_is_empty(callbacks)) {
    4568:	b158      	cbz	r0, 4582 <gpio_nrfx_manage_callback+0x20>
 */
static inline bool sys_slist_find_and_remove(sys_slist_t *list,
					     sys_snode_t *node);

/** @} */
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    456a:	2400      	movs	r4, #0
    456c:	4281      	cmp	r1, r0
    456e:	d113      	bne.n	4598 <gpio_nrfx_manage_callback+0x36>
Z_GENLIST_REMOVE(slist, snode)
    4570:	6808      	ldr	r0, [r1, #0]
    4572:	b95c      	cbnz	r4, 458c <gpio_nrfx_manage_callback+0x2a>
    4574:	689c      	ldr	r4, [r3, #8]
	list->head = node;
    4576:	6058      	str	r0, [r3, #4]
Z_GENLIST_REMOVE(slist, snode)
    4578:	42a1      	cmp	r1, r4
    457a:	d100      	bne.n	457e <gpio_nrfx_manage_callback+0x1c>
	list->tail = node;
    457c:	6098      	str	r0, [r3, #8]
	parent->next = child;
    457e:	2000      	movs	r0, #0
    4580:	6008      	str	r0, [r1, #0]
	if (set) {
    4582:	b972      	cbnz	r2, 45a2 <gpio_nrfx_manage_callback+0x40>
	return 0;
    4584:	2000      	movs	r0, #0
}
    4586:	bd30      	pop	{r4, r5, pc}
    4588:	4628      	mov	r0, r5
    458a:	e7ef      	b.n	456c <gpio_nrfx_manage_callback+0xa>
    458c:	6020      	str	r0, [r4, #0]
Z_GENLIST_REMOVE(slist, snode)
    458e:	6898      	ldr	r0, [r3, #8]
    4590:	4281      	cmp	r1, r0
	list->tail = node;
    4592:	bf08      	it	eq
    4594:	609c      	streq	r4, [r3, #8]
}
    4596:	e7f2      	b.n	457e <gpio_nrfx_manage_callback+0x1c>
Z_GENLIST_PEEK_NEXT_NO_CHECK(slist, snode)
    4598:	6805      	ldr	r5, [r0, #0]
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    459a:	4604      	mov	r4, r0
    459c:	2d00      	cmp	r5, #0
    459e:	d1f3      	bne.n	4588 <gpio_nrfx_manage_callback+0x26>
			if (!set) {
    45a0:	b13a      	cbz	r2, 45b2 <gpio_nrfx_manage_callback+0x50>
Z_GENLIST_PREPEND(slist, snode)
    45a2:	685a      	ldr	r2, [r3, #4]
	parent->next = child;
    45a4:	600a      	str	r2, [r1, #0]
Z_GENLIST_PREPEND(slist, snode)
    45a6:	6898      	ldr	r0, [r3, #8]
	list->head = node;
    45a8:	6059      	str	r1, [r3, #4]
Z_GENLIST_PREPEND(slist, snode)
    45aa:	2800      	cmp	r0, #0
    45ac:	d1ea      	bne.n	4584 <gpio_nrfx_manage_callback+0x22>
	list->tail = node;
    45ae:	6099      	str	r1, [r3, #8]
}
    45b0:	e7e9      	b.n	4586 <gpio_nrfx_manage_callback+0x24>
				return -EINVAL;
    45b2:	f06f 0015 	mvn.w	r0, #21
	return gpio_manage_callback(&get_port_data(port)->callbacks,
    45b6:	e7e6      	b.n	4586 <gpio_nrfx_manage_callback+0x24>

000045b8 <any_other_channel_is_active>:
{
    45b8:	b530      	push	{r4, r5, lr}
    45ba:	2300      	movs	r3, #0
		data->current[channel] & PWM_NRFX_CH_PULSE_CYCLES_MASK;
    45bc:	1d0c      	adds	r4, r1, #4
		if (i != channel && pwm_channel_is_active(i, data)) {
    45be:	b2da      	uxtb	r2, r3
    45c0:	4282      	cmp	r2, r0
    45c2:	d007      	beq.n	45d4 <any_other_channel_is_active+0x1c>
	uint16_t pulse_cycle =
    45c4:	f834 2013 	ldrh.w	r2, [r4, r3, lsl #1]
    45c8:	f3c2 020e 	ubfx	r2, r2, #0, #15
	return (pulse_cycle > 0 && pulse_cycle < data->countertop);
    45cc:	b112      	cbz	r2, 45d4 <any_other_channel_is_active+0x1c>
    45ce:	898d      	ldrh	r5, [r1, #12]
    45d0:	4295      	cmp	r5, r2
    45d2:	d804      	bhi.n	45de <any_other_channel_is_active+0x26>
	for (i = 0; i < NRF_PWM_CHANNEL_COUNT; ++i) {
    45d4:	3301      	adds	r3, #1
    45d6:	2b04      	cmp	r3, #4
    45d8:	d1f1      	bne.n	45be <any_other_channel_is_active+0x6>
	return false;
    45da:	2000      	movs	r0, #0
}
    45dc:	bd30      	pop	{r4, r5, pc}
			return true;
    45de:	2001      	movs	r0, #1
    45e0:	e7fc      	b.n	45dc <any_other_channel_is_active+0x24>

000045e2 <pwm_nrfx_pin_set>:
{
    45e2:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
    45e6:	f89d 4020 	ldrb.w	r4, [sp, #32]
	const struct pwm_nrfx_config *config = dev->config;
    45ea:	6846      	ldr	r6, [r0, #4]
{
    45ec:	460f      	mov	r7, r1
    45ee:	4615      	mov	r5, r2
	struct pwm_nrfx_data *data = dev->data;
    45f0:	6901      	ldr	r1, [r0, #16]
{
    45f2:	4698      	mov	r8, r3
	if (flags) {
    45f4:	2c00      	cmp	r4, #0
    45f6:	d13b      	bne.n	4670 <pwm_nrfx_pin_set+0x8e>
	for (i = 0U; i < NRF_PWM_CHANNEL_COUNT; i++) {
    45f8:	1df2      	adds	r2, r6, #7
		if (output_pins[i] != NRFX_PWM_PIN_NOT_USED
    45fa:	f812 3f01 	ldrb.w	r3, [r2, #1]!
    45fe:	2bff      	cmp	r3, #255	; 0xff
    4600:	d003      	beq.n	460a <pwm_nrfx_pin_set+0x28>
		    && (pwm == (output_pins[i] & PWM_NRFX_CH_PIN_MASK))) {
    4602:	f023 0380 	bic.w	r3, r3, #128	; 0x80
    4606:	429f      	cmp	r7, r3
    4608:	d035      	beq.n	4676 <pwm_nrfx_pin_set+0x94>
	for (i = 0U; i < NRF_PWM_CHANNEL_COUNT; i++) {
    460a:	3401      	adds	r4, #1
    460c:	b2e4      	uxtb	r4, r4
    460e:	2c04      	cmp	r4, #4
    4610:	d1f3      	bne.n	45fa <pwm_nrfx_pin_set+0x18>
		return -EINVAL;
    4612:	f06f 0015 	mvn.w	r0, #21
    4616:	e009      	b.n	462c <pwm_nrfx_pin_set+0x4a>
	was_stopped = !pwm_channel_is_active(channel, data) &&
    4618:	2000      	movs	r0, #0
    461a:	e03c      	b.n	4696 <pwm_nrfx_pin_set+0xb4>
		countertop >>= 1;
    461c:	3301      	adds	r3, #1
	} while (prescaler <= PWM_PRESCALER_PRESCALER_Msk);
    461e:	2b08      	cmp	r3, #8
		countertop >>= 1;
    4620:	ea4f 0252 	mov.w	r2, r2, lsr #1
	} while (prescaler <= PWM_PRESCALER_PRESCALER_Msk);
    4624:	d154      	bne.n	46d0 <pwm_nrfx_pin_set+0xee>
    4626:	e7f4      	b.n	4612 <pwm_nrfx_pin_set+0x30>
		if (was_stopped) {
    4628:	b9a8      	cbnz	r0, 4656 <pwm_nrfx_pin_set+0x74>
	return 0;
    462a:	2000      	movs	r0, #0
}
    462c:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
			&& channel_inverted_state;
    4630:	4545      	cmp	r5, r8
    4632:	d87f      	bhi.n	4734 <pwm_nrfx_pin_set+0x152>
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    4634:	2301      	movs	r3, #1
    4636:	fa03 f707 	lsl.w	r7, r3, r7
    p_reg->OUTCLR = clr_mask;
    463a:	f04f 43a0 	mov.w	r3, #1342177280	; 0x50000000
    463e:	f8c3 750c 	str.w	r7, [r3, #1292]	; 0x50c
		if (!any_other_channel_is_active(channel, data)) {
    4642:	4620      	mov	r0, r4
    4644:	f7ff ffb8 	bl	45b8 <any_other_channel_is_active>
    4648:	2800      	cmp	r0, #0
    464a:	d1ee      	bne.n	462a <pwm_nrfx_pin_set+0x48>
			nrfx_pwm_stop(&config->pwm, false);
    464c:	4601      	mov	r1, r0
    464e:	4630      	mov	r0, r6
    4650:	f000 f92a 	bl	48a8 <nrfx_pwm_stop>
    4654:	e7e9      	b.n	462a <pwm_nrfx_pin_set+0x48>
			while (!nrfx_pwm_is_stopped(&config->pwm)) {
    4656:	4630      	mov	r0, r6
    4658:	f7fe fe3e 	bl	32d8 <nrfx_pwm_is_stopped>
    465c:	2800      	cmp	r0, #0
    465e:	d0fa      	beq.n	4656 <pwm_nrfx_pin_set+0x74>
			nrfx_pwm_simple_playback(&config->pwm,
    4660:	2302      	movs	r3, #2
    4662:	2201      	movs	r2, #1
    4664:	f106 0118 	add.w	r1, r6, #24
    4668:	4630      	mov	r0, r6
    466a:	f7fe fdf7 	bl	325c <nrfx_pwm_simple_playback>
    466e:	e7dc      	b.n	462a <pwm_nrfx_pin_set+0x48>
		return -ENOTSUP;
    4670:	f06f 0085 	mvn.w	r0, #133	; 0x85
    4674:	e7da      	b.n	462c <pwm_nrfx_pin_set+0x4a>
	uint16_t pulse_cycle =
    4676:	eb01 0944 	add.w	r9, r1, r4, lsl #1
		data->current[channel] & PWM_NRFX_CH_PULSE_CYCLES_MASK;
    467a:	f8b9 a004 	ldrh.w	sl, [r9, #4]
	uint16_t pulse_cycle =
    467e:	f3ca 030e 	ubfx	r3, sl, #0, #15
	return (pulse_cycle > 0 && pulse_cycle < data->countertop);
    4682:	b113      	cbz	r3, 468a <pwm_nrfx_pin_set+0xa8>
    4684:	898a      	ldrh	r2, [r1, #12]
    4686:	429a      	cmp	r2, r3
    4688:	d8c6      	bhi.n	4618 <pwm_nrfx_pin_set+0x36>
		      !any_other_channel_is_active(channel, data);
    468a:	4620      	mov	r0, r4
    468c:	f7ff ff94 	bl	45b8 <any_other_channel_is_active>
	was_stopped = !pwm_channel_is_active(channel, data) &&
    4690:	f080 0001 	eor.w	r0, r0, #1
    4694:	b2c0      	uxtb	r0, r0
	if (config->initial_config.count_mode == NRF_PWM_MODE_UP_AND_DOWN) {
    4696:	f896 c00e 	ldrb.w	ip, [r6, #14]
    469a:	f1bc 0f01 	cmp.w	ip, #1
		period_cycles /= 2;
    469e:	bf04      	itt	eq
    46a0:	086d      	lsreq	r5, r5, #1
		pulse_cycles /= 2;
    46a2:	ea4f 0858 	moveq.w	r8, r8, lsr #1
	if (period_cycles != 0 && period_cycles != data->period_cycles) {
    46a6:	b325      	cbz	r5, 46f2 <pwm_nrfx_pin_set+0x110>
    46a8:	680b      	ldr	r3, [r1, #0]
    46aa:	42ab      	cmp	r3, r5
    46ac:	d021      	beq.n	46f2 <pwm_nrfx_pin_set+0x110>
    46ae:	2300      	movs	r3, #0
				data->current[i]
    46b0:	f101 0e04 	add.w	lr, r1, #4
		if (i != channel) {
    46b4:	b2da      	uxtb	r2, r3
    46b6:	42a2      	cmp	r2, r4
    46b8:	d005      	beq.n	46c6 <pwm_nrfx_pin_set+0xe4>
			uint16_t channel_pulse_cycle =
    46ba:	f83e 2013 	ldrh.w	r2, [lr, r3, lsl #1]
			if (channel_pulse_cycle > 0) {
    46be:	f3c2 020e 	ubfx	r2, r2, #0, #15
    46c2:	2a00      	cmp	r2, #0
    46c4:	d1a5      	bne.n	4612 <pwm_nrfx_pin_set+0x30>
	for (i = 0; i < NRF_PWM_CHANNEL_COUNT; ++i) {
    46c6:	3301      	adds	r3, #1
    46c8:	2b04      	cmp	r3, #4
    46ca:	d1f3      	bne.n	46b4 <pwm_nrfx_pin_set+0xd2>
    46cc:	462a      	mov	r2, r5
    46ce:	2300      	movs	r3, #0
		if (countertop <= PWM_COUNTERTOP_COUNTERTOP_Msk) {
    46d0:	f5b2 4f00 	cmp.w	r2, #32768	; 0x8000
    46d4:	fa5f fe83 	uxtb.w	lr, r3
    46d8:	d2a0      	bcs.n	461c <pwm_nrfx_pin_set+0x3a>
			data->prescaler     = prescaler;
    46da:	f881 e00e 	strb.w	lr, [r1, #14]
			nrf_pwm_configure(config->pwm.p_registers,
    46de:	f8d6 e000 	ldr.w	lr, [r6]
			data->period_cycles = period_cycles;
    46e2:	600d      	str	r5, [r1, #0]
			data->countertop    = (uint16_t)countertop;
    46e4:	818a      	strh	r2, [r1, #12]
    p_reg->PRESCALER  = base_clock;
    46e6:	f8ce 350c 	str.w	r3, [lr, #1292]	; 0x50c
    p_reg->MODE       = mode;
    46ea:	f8ce c504 	str.w	ip, [lr, #1284]	; 0x504
    p_reg->COUNTERTOP = top_value;
    46ee:	f8ce 2508 	str.w	r2, [lr, #1288]	; 0x508
		| (pulse_cycles >> data->prescaler));
    46f2:	7b8a      	ldrb	r2, [r1, #14]
	pulse_cycles = MIN(pulse_cycles, period_cycles);
    46f4:	4545      	cmp	r5, r8
    46f6:	462b      	mov	r3, r5
    46f8:	bf28      	it	cs
    46fa:	4643      	movcs	r3, r8
		| (pulse_cycles >> data->prescaler));
    46fc:	fa23 f202 	lsr.w	r2, r3, r2
		(data->current[channel] & PWM_NRFX_CH_POLARITY_MASK)
    4700:	f40a 4a00 	and.w	sl, sl, #32768	; 0x8000
		| (pulse_cycles >> data->prescaler));
    4704:	ea42 020a 	orr.w	r2, r2, sl
    4708:	b292      	uxth	r2, r2
	data->current[channel] = (
    470a:	f8a9 2004 	strh.w	r2, [r9, #4]
	uint16_t pulse_cycle =
    470e:	f3c2 020e 	ubfx	r2, r2, #0, #15
	return (pulse_cycle > 0 && pulse_cycle < data->countertop);
    4712:	b11a      	cbz	r2, 471c <pwm_nrfx_pin_set+0x13a>
    4714:	f8b1 c00c 	ldrh.w	ip, [r1, #12]
    4718:	4594      	cmp	ip, r2
    471a:	d885      	bhi.n	4628 <pwm_nrfx_pin_set+0x46>
			config->initial_config.output_pins[channel]
    471c:	1932      	adds	r2, r6, r4
    471e:	f007 071f 	and.w	r7, r7, #31
    4722:	f992 2008 	ldrsb.w	r2, [r2, #8]
			&& !channel_inverted_state;
    4726:	2b00      	cmp	r3, #0
    4728:	d082      	beq.n	4630 <pwm_nrfx_pin_set+0x4e>
			&& channel_inverted_state;
    472a:	4545      	cmp	r5, r8
    472c:	d805      	bhi.n	473a <pwm_nrfx_pin_set+0x158>
    472e:	2a00      	cmp	r2, #0
    4730:	db80      	blt.n	4634 <pwm_nrfx_pin_set+0x52>
    4732:	e002      	b.n	473a <pwm_nrfx_pin_set+0x158>
		if (pulse_0_and_not_inverted || pulse_100_and_inverted) {
    4734:	2a00      	cmp	r2, #0
    4736:	f6bf af7d 	bge.w	4634 <pwm_nrfx_pin_set+0x52>
    p_reg->OUTSET = set_mask;
    473a:	2301      	movs	r3, #1
    473c:	fa03 f707 	lsl.w	r7, r3, r7
    4740:	f04f 43a0 	mov.w	r3, #1342177280	; 0x50000000
    4744:	f8c3 7508 	str.w	r7, [r3, #1288]	; 0x508
}
    4748:	e77b      	b.n	4642 <pwm_nrfx_pin_set+0x60>

0000474a <uarte_nrfx_isr_int>:
	return config->uarte_regs;
    474a:	6843      	ldr	r3, [r0, #4]
    474c:	681b      	ldr	r3, [r3, #0]
    return p_reg->INTENSET & mask;
    474e:	f8d3 2304 	ldr.w	r2, [r3, #772]	; 0x304
	if (nrf_uarte_int_enable_check(uarte, NRF_UARTE_INT_ENDTX_MASK) &&
    4752:	05d1      	lsls	r1, r2, #23
    4754:	d518      	bpl.n	4788 <uarte_nrfx_isr_int+0x3e>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    4756:	f8d3 2120 	ldr.w	r2, [r3, #288]	; 0x120
    475a:	b1aa      	cbz	r2, 4788 <uarte_nrfx_isr_int+0x3e>
	__asm__ volatile(
    475c:	f04f 0120 	mov.w	r1, #32
    4760:	f3ef 8211 	mrs	r2, BASEPRI
    4764:	f381 8812 	msr	BASEPRI_MAX, r1
    4768:	f3bf 8f6f 	isb	sy
    476c:	f8d3 1120 	ldr.w	r1, [r3, #288]	; 0x120
	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDTX)) {
    4770:	b131      	cbz	r1, 4780 <uarte_nrfx_isr_int+0x36>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    4772:	2100      	movs	r1, #0
    4774:	f8c3 1120 	str.w	r1, [r3, #288]	; 0x120
    4778:	f8d3 1120 	ldr.w	r1, [r3, #288]	; 0x120
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    477c:	2101      	movs	r1, #1
    477e:	60d9      	str	r1, [r3, #12]
	__asm__ volatile(
    4780:	f382 8811 	msr	BASEPRI, r2
    4784:	f3bf 8f6f 	isb	sy
	if (get_dev_config(dev)->flags & UARTE_CFG_FLAG_LOW_POWER) {
    4788:	6842      	ldr	r2, [r0, #4]
    478a:	6852      	ldr	r2, [r2, #4]
    478c:	06d2      	lsls	r2, r2, #27
    478e:	d515      	bpl.n	47bc <uarte_nrfx_isr_int+0x72>
	__asm__ volatile(
    4790:	f04f 0120 	mov.w	r1, #32
    4794:	f3ef 8211 	mrs	r2, BASEPRI
    4798:	f381 8812 	msr	BASEPRI_MAX, r1
    479c:	f3bf 8f6f 	isb	sy
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    47a0:	f8d3 1158 	ldr.w	r1, [r3, #344]	; 0x158
		if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED)) {
    47a4:	b111      	cbz	r1, 47ac <uarte_nrfx_isr_int+0x62>
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
    47a6:	2100      	movs	r1, #0
    47a8:	f8c3 1500 	str.w	r1, [r3, #1280]	; 0x500
    p_reg->INTENCLR = mask;
    47ac:	f44f 0180 	mov.w	r1, #4194304	; 0x400000
    47b0:	f8c3 1308 	str.w	r1, [r3, #776]	; 0x308
	__asm__ volatile(
    47b4:	f382 8811 	msr	BASEPRI, r2
    47b8:	f3bf 8f6f 	isb	sy
}
    47bc:	4770      	bx	lr

000047be <uarte_nrfx_config_get>:
	*cfg = get_dev_data(dev)->uart_config;
    47be:	6902      	ldr	r2, [r0, #16]
{
    47c0:	460b      	mov	r3, r1
	*cfg = get_dev_data(dev)->uart_config;
    47c2:	e9d2 0101 	ldrd	r0, r1, [r2, #4]
    47c6:	e883 0003 	stmia.w	r3, {r0, r1}
}
    47ca:	2000      	movs	r0, #0
    47cc:	4770      	bx	lr

000047ce <uarte_nrfx_err_check>:
	return config->uarte_regs;
    47ce:	6843      	ldr	r3, [r0, #4]
    47d0:	681b      	ldr	r3, [r3, #0]
    uint32_t errsrc_mask = p_reg->ERRORSRC;
    47d2:	f8d3 0480 	ldr.w	r0, [r3, #1152]	; 0x480
    p_reg->ERRORSRC = errsrc_mask;
    47d6:	f8c3 0480 	str.w	r0, [r3, #1152]	; 0x480
}
    47da:	4770      	bx	lr

000047dc <is_tx_ready>:
	const struct uarte_nrfx_config *config = get_dev_config(dev);
    47dc:	6842      	ldr	r2, [r0, #4]
	return config->uarte_regs;
    47de:	6813      	ldr	r3, [r2, #0]
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    47e0:	f8d3 0158 	ldr.w	r0, [r3, #344]	; 0x158
	return nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED) ||
    47e4:	b940      	cbnz	r0, 47f8 <is_tx_ready+0x1c>
	bool ppi_endtx = get_dev_config(dev)->flags & UARTE_CFG_FLAG_PPI_ENDTX;
    47e6:	6852      	ldr	r2, [r2, #4]
	return nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED) ||
    47e8:	0792      	lsls	r2, r2, #30
    47ea:	d406      	bmi.n	47fa <is_tx_ready+0x1e>
    47ec:	f8d3 0120 	ldr.w	r0, [r3, #288]	; 0x120
    47f0:	3800      	subs	r0, #0
    47f2:	bf18      	it	ne
    47f4:	2001      	movne	r0, #1
    47f6:	4770      	bx	lr
    47f8:	2001      	movs	r0, #1
}
    47fa:	4770      	bx	lr

000047fc <uarte_nrfx_poll_in>:
	return config->uarte_regs;
    47fc:	6843      	ldr	r3, [r0, #4]
	const struct uarte_nrfx_data *data = get_dev_data(dev);
    47fe:	6902      	ldr	r2, [r0, #16]
	return config->uarte_regs;
    4800:	681b      	ldr	r3, [r3, #0]
    4802:	f8d3 0110 	ldr.w	r0, [r3, #272]	; 0x110
	if (!nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDRX)) {
    4806:	b148      	cbz	r0, 481c <uarte_nrfx_poll_in+0x20>
	*c = data->rx_data;
    4808:	7c52      	ldrb	r2, [r2, #17]
    480a:	700a      	strb	r2, [r1, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    480c:	2000      	movs	r0, #0
    480e:	f8c3 0110 	str.w	r0, [r3, #272]	; 0x110
    4812:	f8d3 2110 	ldr.w	r2, [r3, #272]	; 0x110
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    4816:	2201      	movs	r2, #1
    4818:	601a      	str	r2, [r3, #0]
	return 0;
    481a:	4770      	bx	lr
		return -1;
    481c:	f04f 30ff 	mov.w	r0, #4294967295
}
    4820:	4770      	bx	lr

00004822 <sys_clock_idle_exit>:
{
}

void __weak sys_clock_idle_exit(void)
{
}
    4822:	4770      	bx	lr

00004824 <k_sys_fatal_error_handler>:

extern void sys_arch_reboot(int type);

void k_sys_fatal_error_handler(unsigned int reason,
			       const z_arch_esf_t *esf)
{
    4824:	b508      	push	{r3, lr}
	z_spm_ns_fatal_error_handler();
#endif

	if (IS_ENABLED(CONFIG_RESET_ON_FATAL_ERROR)) {
		LOG_ERR("Resetting system");
		sys_arch_reboot(0);
    4826:	2000      	movs	r0, #0
    4828:	f7fc ff4e 	bl	16c8 <sys_arch_reboot>

0000482c <nrfx_isr>:
#include <nrfx.h>
#include <kernel.h>

void nrfx_isr(const void *irq_handler)
{
	((nrfx_irq_handler_t)irq_handler)();
    482c:	4700      	bx	r0

0000482e <nrfx_busy_wait>:
	z_impl_k_busy_wait(usec_to_wait);
    482e:	f000 b9c5 	b.w	4bbc <z_impl_k_busy_wait>

00004832 <nrfx_clock_enable>:
{
    4832:	b508      	push	{r3, lr}
    priority = NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY;
#else
    #error "This code is not supposed to be compiled when neither POWER nor CLOCK is enabled."
#endif

    if (!NRFX_IRQ_IS_ENABLED(nrfx_get_irq_number(NRF_CLOCK)))
    4834:	2000      	movs	r0, #0
    4836:	f7fc fbd3 	bl	fe0 <arch_irq_is_enabled>
    483a:	b918      	cbnz	r0, 4844 <nrfx_clock_enable+0x12>
}
    483c:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    {
        NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_CLOCK), priority);
        NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_CLOCK));
    4840:	f7fc bbbe 	b.w	fc0 <arch_irq_enable>
    4844:	bd08      	pop	{r3, pc}

00004846 <nrf_gpio_cfg_sense_set>:
    *p_pin = pin_number & 0x1F;
    4846:	f000 001f 	and.w	r0, r0, #31
    484a:	0080      	lsls	r0, r0, #2
    484c:	f100 40a0 	add.w	r0, r0, #1342177280	; 0x50000000
    uint32_t cnf = reg->PIN_CNF[pin_number];
    4850:	f8d0 3700 	ldr.w	r3, [r0, #1792]	; 0x700
    cnf &= ~to_update;
    4854:	f423 3340 	bic.w	r3, r3, #196608	; 0x30000
    cnf |= ((uint32_t)(p_dir   ? *p_dir   : 0) << GPIO_PIN_CNF_DIR_Pos)   |
    4858:	ea43 4301 	orr.w	r3, r3, r1, lsl #16
    reg->PIN_CNF[pin_number] = cnf;
    485c:	f8c0 3700 	str.w	r3, [r0, #1792]	; 0x700
}
    4860:	4770      	bx	lr

00004862 <start_playback.isra.0>:
static uint32_t start_playback(nrfx_pwm_t const * p_instance,
    4862:	b510      	push	{r4, lr}
    p_cb->state = NRFX_DRV_STATE_POWERED_ON;
    4864:	2402      	movs	r4, #2
    4866:	720c      	strb	r4, [r1, #8]
    p_cb->flags = flags;
    4868:	724a      	strb	r2, [r1, #9]
    if (p_cb->handler)
    486a:	6809      	ldr	r1, [r1, #0]
    486c:	b171      	cbz	r1, 488c <start_playback.isra.0+0x2a>
            int_mask |= NRF_PWM_INT_SEQEND0_MASK;
    486e:	f012 0f04 	tst.w	r2, #4
    4872:	bf0c      	ite	eq
    4874:	2182      	moveq	r1, #130	; 0x82
    4876:	2192      	movne	r1, #146	; 0x92
        if (flags & NRFX_PWM_FLAG_SIGNAL_END_SEQ1)
    4878:	0714      	lsls	r4, r2, #28
            int_mask |= NRF_PWM_INT_SEQEND1_MASK;
    487a:	bf48      	it	mi
    487c:	f041 0120 	orrmi.w	r1, r1, #32
        if (flags & NRFX_PWM_FLAG_NO_EVT_FINISHED)
    4880:	06d4      	lsls	r4, r2, #27
            int_mask &= ~NRF_PWM_INT_LOOPSDONE_MASK;
    4882:	bf48      	it	mi
    4884:	f021 0180 	bicmi.w	r1, r1, #128	; 0x80
    p_reg->INTEN = mask;
    4888:	f8c0 1300 	str.w	r1, [r0, #768]	; 0x300
    if (flags & NRFX_PWM_FLAG_START_VIA_TASK)
    488c:	0612      	lsls	r2, r2, #24
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    488e:	f04f 0100 	mov.w	r1, #0
    4892:	f8c0 1104 	str.w	r1, [r0, #260]	; 0x104
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    4896:	bf58      	it	pl
    4898:	2201      	movpl	r2, #1
    489a:	f8d0 4104 	ldr.w	r4, [r0, #260]	; 0x104
    489e:	bf56      	itet	pl
    48a0:	50c2      	strpl	r2, [r0, r3]
    return ((uint32_t)p_reg + (uint32_t)task);
    48a2:	18c0      	addmi	r0, r0, r3
    return 0;
    48a4:	4608      	movpl	r0, r1
}
    48a6:	bd10      	pop	{r4, pc}

000048a8 <nrfx_pwm_stop>:
{
    48a8:	b538      	push	{r3, r4, r5, lr}
    nrf_pwm_shorts_set(p_instance->p_registers, 0);
    48aa:	6803      	ldr	r3, [r0, #0]
    p_reg->SHORTS = mask;
    48ac:	2200      	movs	r2, #0
    48ae:	f8c3 2200 	str.w	r2, [r3, #512]	; 0x200
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    48b2:	2201      	movs	r2, #1
    48b4:	605a      	str	r2, [r3, #4]
{
    48b6:	4605      	mov	r5, r0
    48b8:	460c      	mov	r4, r1
    if (nrfx_pwm_is_stopped(p_instance))
    48ba:	f7fe fd0d 	bl	32d8 <nrfx_pwm_is_stopped>
    48be:	b938      	cbnz	r0, 48d0 <nrfx_pwm_stop+0x28>
            if (nrfx_pwm_is_stopped(p_instance))
    48c0:	4628      	mov	r0, r5
    48c2:	f7fe fd09 	bl	32d8 <nrfx_pwm_is_stopped>
    48c6:	b918      	cbnz	r0, 48d0 <nrfx_pwm_stop+0x28>
        } while (wait_until_stopped);
    48c8:	2c00      	cmp	r4, #0
    48ca:	d1f9      	bne.n	48c0 <nrfx_pwm_stop+0x18>
}
    48cc:	4620      	mov	r0, r4
    48ce:	bd38      	pop	{r3, r4, r5, pc}
        ret_val = true;
    48d0:	2401      	movs	r4, #1
    48d2:	e7fb      	b.n	48cc <nrfx_pwm_stop+0x24>

000048d4 <_GetAvailWriteSpace>:
  RdOff = pRing->RdOff;
    48d4:	6903      	ldr	r3, [r0, #16]
  WrOff = pRing->WrOff;
    48d6:	68c1      	ldr	r1, [r0, #12]
  if (RdOff <= WrOff) {
    48d8:	428b      	cmp	r3, r1
    r = pRing->SizeOfBuffer - 1u - WrOff + RdOff;
    48da:	bf9d      	ittte	ls
    48dc:	6882      	ldrls	r2, [r0, #8]
    48de:	18d2      	addls	r2, r2, r3
    48e0:	f102 32ff 	addls.w	r2, r2, #4294967295
    r = RdOff - WrOff - 1u;
    48e4:	f103 33ff 	addhi.w	r3, r3, #4294967295
    r = pRing->SizeOfBuffer - 1u - WrOff + RdOff;
    48e8:	bf94      	ite	ls
    48ea:	1a50      	subls	r0, r2, r1
    r = RdOff - WrOff - 1u;
    48ec:	1a58      	subhi	r0, r3, r1
}
    48ee:	4770      	bx	lr

000048f0 <_WriteNoCheck>:
static void _WriteNoCheck(SEGGER_RTT_BUFFER_UP* pRing, const char* pData, unsigned NumBytes) {
    48f0:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
  Rem = pRing->SizeOfBuffer - WrOff;
    48f4:	e9d0 9402 	ldrd	r9, r4, [r0, #8]
static void _WriteNoCheck(SEGGER_RTT_BUFFER_UP* pRing, const char* pData, unsigned NumBytes) {
    48f8:	4605      	mov	r5, r0
  Rem = pRing->SizeOfBuffer - WrOff;
    48fa:	eba9 0804 	sub.w	r8, r9, r4
  if (Rem > NumBytes) {
    48fe:	6840      	ldr	r0, [r0, #4]
    4900:	4590      	cmp	r8, r2
    4902:	4420      	add	r0, r4
static void _WriteNoCheck(SEGGER_RTT_BUFFER_UP* pRing, const char* pData, unsigned NumBytes) {
    4904:	460f      	mov	r7, r1
    4906:	4414      	add	r4, r2
  if (Rem > NumBytes) {
    4908:	d906      	bls.n	4918 <_WriteNoCheck+0x28>
    SEGGER_RTT_MEMCPY((void*)pDst, pData + Rem, NumBytesAtOnce);
    490a:	f7ff fd3d 	bl	4388 <memcpy>
    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
    490e:	f3bf 8f5f 	dmb	sy
    pRing->WrOff = NumBytesAtOnce;
    4912:	60ec      	str	r4, [r5, #12]
}
    4914:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
    SEGGER_RTT_MEMCPY((void*)pDst, pData, NumBytesAtOnce);
    4918:	4642      	mov	r2, r8
    NumBytesAtOnce = NumBytes - Rem;
    491a:	eba4 0409 	sub.w	r4, r4, r9
    SEGGER_RTT_MEMCPY((void*)pDst, pData, NumBytesAtOnce);
    491e:	f7ff fd33 	bl	4388 <memcpy>
    SEGGER_RTT_MEMCPY((void*)pDst, pData + Rem, NumBytesAtOnce);
    4922:	6868      	ldr	r0, [r5, #4]
    4924:	4622      	mov	r2, r4
    4926:	eb07 0108 	add.w	r1, r7, r8
    492a:	e7ee      	b.n	490a <_WriteNoCheck+0x1a>

0000492c <_WriteBlocking>:
static unsigned _WriteBlocking(SEGGER_RTT_BUFFER_UP* pRing, const char* pBuffer, unsigned NumBytes) {
    492c:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
  WrOff = pRing->WrOff;
    4930:	68c5      	ldr	r5, [r0, #12]
static unsigned _WriteBlocking(SEGGER_RTT_BUFFER_UP* pRing, const char* pBuffer, unsigned NumBytes) {
    4932:	4606      	mov	r6, r0
    4934:	4689      	mov	r9, r1
    4936:	4617      	mov	r7, r2
  NumBytesWritten = 0u;
    4938:	f04f 0800 	mov.w	r8, #0
    RdOff = pRing->RdOff;                         // May be changed by host (debug probe) in the meantime
    493c:	6934      	ldr	r4, [r6, #16]
    if (RdOff > WrOff) {
    493e:	68b3      	ldr	r3, [r6, #8]
    pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF;
    4940:	6870      	ldr	r0, [r6, #4]
    if (RdOff > WrOff) {
    4942:	42a5      	cmp	r5, r4
      NumBytesToWrite = pRing->SizeOfBuffer - (WrOff - RdOff + 1u);
    4944:	bf28      	it	cs
    4946:	18e4      	addcs	r4, r4, r3
    4948:	3c01      	subs	r4, #1
    494a:	1b62      	subs	r2, r4, r5
    NumBytesToWrite = MIN(NumBytesToWrite, (pRing->SizeOfBuffer - WrOff));      // Number of bytes that can be written until buffer wrap-around
    494c:	1b5c      	subs	r4, r3, r5
    NumBytesToWrite = MIN(NumBytesToWrite, NumBytes);
    494e:	42bc      	cmp	r4, r7
    4950:	bf28      	it	cs
    4952:	463c      	movcs	r4, r7
    4954:	4294      	cmp	r4, r2
    4956:	bf28      	it	cs
    4958:	4614      	movcs	r4, r2
    SEGGER_RTT_MEMCPY((void*)pDst, pBuffer, NumBytesToWrite);
    495a:	4649      	mov	r1, r9
    495c:	4622      	mov	r2, r4
    495e:	4428      	add	r0, r5
    4960:	f7ff fd12 	bl	4388 <memcpy>
    if (WrOff == pRing->SizeOfBuffer) {
    4964:	68b3      	ldr	r3, [r6, #8]
    WrOff           += NumBytesToWrite;
    4966:	4425      	add	r5, r4
    NumBytesWritten += NumBytesToWrite;
    4968:	44a0      	add	r8, r4
    pBuffer         += NumBytesToWrite;
    496a:	44a1      	add	r9, r4
    NumBytes        -= NumBytesToWrite;
    496c:	1b3f      	subs	r7, r7, r4
      WrOff = 0u;
    496e:	42ab      	cmp	r3, r5
    4970:	bf08      	it	eq
    4972:	2500      	moveq	r5, #0
    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
    4974:	f3bf 8f5f 	dmb	sy
    pRing->WrOff = WrOff;
    4978:	60f5      	str	r5, [r6, #12]
  } while (NumBytes);
    497a:	2f00      	cmp	r7, #0
    497c:	d1de      	bne.n	493c <_WriteBlocking+0x10>
}
    497e:	4640      	mov	r0, r8
    4980:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}

00004984 <SEGGER_RTT_Init>:
*    Initializes the RTT Control Block.
*    Should be used in RAM targets, at start of the application.
*
*/
void SEGGER_RTT_Init (void) {
  _DoInit();
    4984:	f7fe bcbc 	b.w	3300 <_DoInit>

00004988 <rtt_init>:
 */

K_MUTEX_DEFINE(rtt_term_mutex);

static int rtt_init(const struct device *unused)
{
    4988:	b508      	push	{r3, lr}
	ARG_UNUSED(unused);

	SEGGER_RTT_Init();
    498a:	f7ff fffb 	bl	4984 <SEGGER_RTT_Init>

	return 0;
}
    498e:	2000      	movs	r0, #0
    4990:	bd08      	pop	{r3, pc}

00004992 <z_fatal_error>:
	return 0;
#endif
}

void z_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
{
    4992:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    4994:	4605      	mov	r5, r0
    4996:	460e      	mov	r6, r1
	__asm__ volatile(
    4998:	f04f 0320 	mov.w	r3, #32
    499c:	f3ef 8711 	mrs	r7, BASEPRI
    49a0:	f383 8812 	msr	BASEPRI_MAX, r3
    49a4:	f3bf 8f6f 	isb	sy
	return z_impl_z_current_get();
    49a8:	f7ff f97e 	bl	3ca8 <z_impl_z_current_get>
	LOG_ERR("Current thread: %p (%s)", thread,
		log_strdup(thread_name_get(thread)));

	coredump(reason, esf, thread);

	k_sys_fatal_error_handler(reason, esf);
    49ac:	4631      	mov	r1, r6
    49ae:	4604      	mov	r4, r0
    49b0:	4628      	mov	r0, r5
    49b2:	f7ff ff37 	bl	4824 <k_sys_fatal_error_handler>
	__asm__ volatile(
    49b6:	f387 8811 	msr	BASEPRI, r7
    49ba:	f3bf 8f6f 	isb	sy
	z_impl_k_thread_abort(thread);
    49be:	4620      	mov	r0, r4
	arch_irq_unlock(key);

	if (IS_ENABLED(CONFIG_MULTITHREADING)) {
		k_thread_abort(thread);
	}
}
    49c0:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
    49c4:	f7fc bd94 	b.w	14f0 <z_impl_k_thread_abort>

000049c8 <k_is_in_isr>:
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    49c8:	f3ef 8005 	mrs	r0, IPSR
}
    49cc:	3800      	subs	r0, #0
    49ce:	bf18      	it	ne
    49d0:	2001      	movne	r0, #1
    49d2:	4770      	bx	lr

000049d4 <z_pm_save_idle_exit>:
{
    49d4:	b508      	push	{r3, lr}
	pm_system_resume();
    49d6:	f7fc fa11 	bl	dfc <pm_system_resume>
}
    49da:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	sys_clock_idle_exit();
    49de:	f7ff bf20 	b.w	4822 <sys_clock_idle_exit>

000049e2 <sys_dlist_remove>:
	sys_dnode_t *const next = node->next;
    49e2:	e9d0 3200 	ldrd	r3, r2, [r0]
	prev->next = next;
    49e6:	6013      	str	r3, [r2, #0]
	next->prev = prev;
    49e8:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    49ea:	2300      	movs	r3, #0
	node->prev = NULL;
    49ec:	e9c0 3300 	strd	r3, r3, [r0]
	sys_dnode_init(node);
}
    49f0:	4770      	bx	lr

000049f2 <unpend_thread_no_timeout>:
{
    49f2:	b508      	push	{r3, lr}
	sys_dlist_remove(&thread->base.qnode_dlist);
    49f4:	f7ff fff5 	bl	49e2 <sys_dlist_remove>
	thread->base.thread_state &= ~_THREAD_PENDING;
    49f8:	7b43      	ldrb	r3, [r0, #13]
    49fa:	f023 0302 	bic.w	r3, r3, #2
    49fe:	7343      	strb	r3, [r0, #13]
	thread->base.pended_on = NULL;
    4a00:	2300      	movs	r3, #0
    4a02:	6083      	str	r3, [r0, #8]
}
    4a04:	bd08      	pop	{r3, pc}

00004a06 <z_reschedule_irqlock>:
	return arch_irq_unlocked(key) && !arch_is_in_isr();
    4a06:	4603      	mov	r3, r0
    4a08:	b920      	cbnz	r0, 4a14 <z_reschedule_irqlock+0xe>
    4a0a:	f3ef 8205 	mrs	r2, IPSR
	if (resched(key)) {
    4a0e:	b90a      	cbnz	r2, 4a14 <z_reschedule_irqlock+0xe>
	ret = arch_swap(key);
    4a10:	f7fc bb2c 	b.w	106c <arch_swap>
    4a14:	f383 8811 	msr	BASEPRI, r3
    4a18:	f3bf 8f6f 	isb	sy
}
    4a1c:	4770      	bx	lr

00004a1e <z_reschedule_unlocked>:
	__asm__ volatile(
    4a1e:	f04f 0320 	mov.w	r3, #32
    4a22:	f3ef 8011 	mrs	r0, BASEPRI
    4a26:	f383 8812 	msr	BASEPRI_MAX, r3
    4a2a:	f3bf 8f6f 	isb	sy
	(void) z_reschedule_irqlock(arch_irq_lock());
    4a2e:	f7ff bfea 	b.w	4a06 <z_reschedule_irqlock>

00004a32 <z_priq_dumb_best>:
{
    4a32:	4603      	mov	r3, r0
	return list->head == list;
    4a34:	6800      	ldr	r0, [r0, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4a36:	4283      	cmp	r3, r0
    4a38:	d003      	beq.n	4a42 <z_priq_dumb_best+0x10>
	if (n != NULL) {
    4a3a:	2800      	cmp	r0, #0
    4a3c:	bf38      	it	cc
    4a3e:	2000      	movcc	r0, #0
    4a40:	4770      	bx	lr
	struct k_thread *thread = NULL;
    4a42:	2000      	movs	r0, #0
}
    4a44:	4770      	bx	lr

00004a46 <z_ready_thread>:
{
    4a46:	b510      	push	{r4, lr}
    4a48:	f04f 0320 	mov.w	r3, #32
    4a4c:	f3ef 8411 	mrs	r4, BASEPRI
    4a50:	f383 8812 	msr	BASEPRI_MAX, r3
    4a54:	f3bf 8f6f 	isb	sy
			ready_thread(thread);
    4a58:	f7fe ff7c 	bl	3954 <ready_thread>
	__asm__ volatile(
    4a5c:	f384 8811 	msr	BASEPRI, r4
    4a60:	f3bf 8f6f 	isb	sy
}
    4a64:	bd10      	pop	{r4, pc}

00004a66 <z_thread_timeout>:
{
    4a66:	b510      	push	{r4, lr}
    4a68:	4601      	mov	r1, r0
	__asm__ volatile(
    4a6a:	f04f 0320 	mov.w	r3, #32
    4a6e:	f3ef 8411 	mrs	r4, BASEPRI
    4a72:	f383 8812 	msr	BASEPRI_MAX, r3
    4a76:	f3bf 8f6f 	isb	sy
		if (!killed) {
    4a7a:	f810 3c0b 	ldrb.w	r3, [r0, #-11]
    4a7e:	f013 0f28 	tst.w	r3, #40	; 0x28
    4a82:	d10d      	bne.n	4aa0 <z_thread_timeout+0x3a>
			if (thread->base.pended_on != NULL) {
    4a84:	f851 3c10 	ldr.w	r3, [r1, #-16]
	struct k_thread *thread = CONTAINER_OF(timeout,
    4a88:	3818      	subs	r0, #24
			if (thread->base.pended_on != NULL) {
    4a8a:	b10b      	cbz	r3, 4a90 <z_thread_timeout+0x2a>
				unpend_thread_no_timeout(thread);
    4a8c:	f7ff ffb1 	bl	49f2 <unpend_thread_no_timeout>
	thread->base.thread_state &= ~_THREAD_SUSPENDED;
    4a90:	f811 3c0b 	ldrb.w	r3, [r1, #-11]
    4a94:	f023 0314 	bic.w	r3, r3, #20
    4a98:	f801 3c0b 	strb.w	r3, [r1, #-11]
			ready_thread(thread);
    4a9c:	f7fe ff5a 	bl	3954 <ready_thread>
	__asm__ volatile(
    4aa0:	f384 8811 	msr	BASEPRI, r4
    4aa4:	f3bf 8f6f 	isb	sy
}
    4aa8:	bd10      	pop	{r4, pc}

00004aaa <add_to_waitq_locked>:
{
    4aaa:	b538      	push	{r3, r4, r5, lr}
    4aac:	4604      	mov	r4, r0
    4aae:	460d      	mov	r5, r1
	unready_thread(thread);
    4ab0:	f7fe ffa6 	bl	3a00 <unready_thread>
	thread->base.thread_state |= _THREAD_PENDING;
    4ab4:	7b63      	ldrb	r3, [r4, #13]
    4ab6:	f043 0302 	orr.w	r3, r3, #2
    4aba:	7363      	strb	r3, [r4, #13]
	if (wait_q != NULL) {
    4abc:	b1b5      	cbz	r5, 4aec <add_to_waitq_locked+0x42>
	return list->head == list;
    4abe:	682b      	ldr	r3, [r5, #0]
		thread->base.pended_on = wait_q;
    4ac0:	60a5      	str	r5, [r4, #8]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4ac2:	429d      	cmp	r5, r3
    4ac4:	bf08      	it	eq
    4ac6:	2300      	moveq	r3, #0
    4ac8:	2b00      	cmp	r3, #0
    4aca:	bf38      	it	cc
    4acc:	2300      	movcc	r3, #0
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    4ace:	b19b      	cbz	r3, 4af8 <add_to_waitq_locked+0x4e>
	int32_t b1 = thread_1->base.prio;
    4ad0:	f994 100e 	ldrsb.w	r1, [r4, #14]
	int32_t b2 = thread_2->base.prio;
    4ad4:	f993 200e 	ldrsb.w	r2, [r3, #14]
	if (b1 != b2) {
    4ad8:	4291      	cmp	r1, r2
    4ada:	d008      	beq.n	4aee <add_to_waitq_locked+0x44>
		return b2 - b1;
    4adc:	1a52      	subs	r2, r2, r1
		if (z_sched_prio_cmp(thread, t) > 0) {
    4ade:	2a00      	cmp	r2, #0
    4ae0:	dd05      	ble.n	4aee <add_to_waitq_locked+0x44>
	sys_dnode_t *const prev = successor->prev;
    4ae2:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
    4ae4:	e9c4 3200 	strd	r3, r2, [r4]
	prev->next = node;
    4ae8:	6014      	str	r4, [r2, #0]
	successor->prev = node;
    4aea:	605c      	str	r4, [r3, #4]
}
    4aec:	bd38      	pop	{r3, r4, r5, pc}
	return (node == list->tail) ? NULL : node->next;
    4aee:	686a      	ldr	r2, [r5, #4]
    4af0:	4293      	cmp	r3, r2
    4af2:	d001      	beq.n	4af8 <add_to_waitq_locked+0x4e>
    4af4:	681b      	ldr	r3, [r3, #0]
    4af6:	e7ea      	b.n	4ace <add_to_waitq_locked+0x24>
	sys_dnode_t *const tail = list->tail;
    4af8:	686b      	ldr	r3, [r5, #4]
	node->prev = tail;
    4afa:	e9c4 5300 	strd	r5, r3, [r4]
	tail->next = node;
    4afe:	601c      	str	r4, [r3, #0]
	list->tail = node;
    4b00:	606c      	str	r4, [r5, #4]
    4b02:	e7f3      	b.n	4aec <add_to_waitq_locked+0x42>

00004b04 <z_unpend_first_thread>:
{
    4b04:	b538      	push	{r3, r4, r5, lr}
	__asm__ volatile(
    4b06:	f04f 0320 	mov.w	r3, #32
    4b0a:	f3ef 8511 	mrs	r5, BASEPRI
    4b0e:	f383 8812 	msr	BASEPRI_MAX, r3
    4b12:	f3bf 8f6f 	isb	sy
		thread = _priq_wait_best(&wait_q->waitq);
    4b16:	f7ff ff8c 	bl	4a32 <z_priq_dumb_best>
		if (thread != NULL) {
    4b1a:	4604      	mov	r4, r0
    4b1c:	b120      	cbz	r0, 4b28 <z_unpend_first_thread+0x24>
			unpend_thread_no_timeout(thread);
    4b1e:	f7ff ff68 	bl	49f2 <unpend_thread_no_timeout>
    4b22:	3018      	adds	r0, #24
    4b24:	f000 f806 	bl	4b34 <z_abort_timeout>
	__asm__ volatile(
    4b28:	f385 8811 	msr	BASEPRI, r5
    4b2c:	f3bf 8f6f 	isb	sy
}
    4b30:	4620      	mov	r0, r4
    4b32:	bd38      	pop	{r3, r4, r5, pc}

00004b34 <z_abort_timeout>:
{
    4b34:	b510      	push	{r4, lr}
	__asm__ volatile(
    4b36:	f04f 0220 	mov.w	r2, #32
    4b3a:	f3ef 8411 	mrs	r4, BASEPRI
    4b3e:	f382 8812 	msr	BASEPRI_MAX, r2
    4b42:	f3bf 8f6f 	isb	sy
		if (sys_dnode_is_linked(&to->node)) {
    4b46:	6803      	ldr	r3, [r0, #0]
    4b48:	b13b      	cbz	r3, 4b5a <z_abort_timeout+0x26>
			remove_timeout(to);
    4b4a:	f7ff f929 	bl	3da0 <remove_timeout>
			ret = 0;
    4b4e:	2000      	movs	r0, #0
	__asm__ volatile(
    4b50:	f384 8811 	msr	BASEPRI, r4
    4b54:	f3bf 8f6f 	isb	sy
}
    4b58:	bd10      	pop	{r4, pc}
	int ret = -EINVAL;
    4b5a:	f06f 0015 	mvn.w	r0, #21
    4b5e:	e7f7      	b.n	4b50 <z_abort_timeout+0x1c>

00004b60 <z_get_next_timeout_expiry>:
{
    4b60:	b510      	push	{r4, lr}
	__asm__ volatile(
    4b62:	f04f 0320 	mov.w	r3, #32
    4b66:	f3ef 8411 	mrs	r4, BASEPRI
    4b6a:	f383 8812 	msr	BASEPRI_MAX, r3
    4b6e:	f3bf 8f6f 	isb	sy
		ret = next_timeout();
    4b72:	f7ff f92f 	bl	3dd4 <next_timeout>
	__asm__ volatile(
    4b76:	f384 8811 	msr	BASEPRI, r4
    4b7a:	f3bf 8f6f 	isb	sy
}
    4b7e:	bd10      	pop	{r4, pc}

00004b80 <z_set_timeout_expiry>:
{
    4b80:	b570      	push	{r4, r5, r6, lr}
    4b82:	4604      	mov	r4, r0
    4b84:	460d      	mov	r5, r1
	__asm__ volatile(
    4b86:	f04f 0320 	mov.w	r3, #32
    4b8a:	f3ef 8611 	mrs	r6, BASEPRI
    4b8e:	f383 8812 	msr	BASEPRI_MAX, r3
    4b92:	f3bf 8f6f 	isb	sy
		int next_to = next_timeout();
    4b96:	f7ff f91d 	bl	3dd4 <next_timeout>
		if (!imminent && (sooner || IS_ENABLED(CONFIG_SMP))) {
    4b9a:	2801      	cmp	r0, #1
    4b9c:	dd05      	ble.n	4baa <z_set_timeout_expiry+0x2a>
    4b9e:	42a0      	cmp	r0, r4
    4ba0:	db03      	blt.n	4baa <z_set_timeout_expiry+0x2a>
			sys_clock_set_timeout(MIN(ticks, next_to), is_idle);
    4ba2:	4629      	mov	r1, r5
    4ba4:	4620      	mov	r0, r4
    4ba6:	f7fd fce7 	bl	2578 <sys_clock_set_timeout>
	__asm__ volatile(
    4baa:	f386 8811 	msr	BASEPRI, r6
    4bae:	f3bf 8f6f 	isb	sy
}
    4bb2:	bd70      	pop	{r4, r5, r6, pc}

00004bb4 <sys_clock_tick_get_32>:

uint32_t sys_clock_tick_get_32(void)
{
    4bb4:	b508      	push	{r3, lr}
#ifdef CONFIG_TICKLESS_KERNEL
	return (uint32_t)sys_clock_tick_get();
    4bb6:	f7ff fa2d 	bl	4014 <sys_clock_tick_get>
#else
	return (uint32_t)curr_tick;
#endif
}
    4bba:	bd08      	pop	{r3, pc}

00004bbc <z_impl_k_busy_wait>:
#endif

void z_impl_k_busy_wait(uint32_t usec_to_wait)
{
	SYS_PORT_TRACING_FUNC_ENTER(k_thread, busy_wait, usec_to_wait);
	if (usec_to_wait == 0U) {
    4bbc:	b108      	cbz	r0, 4bc2 <z_impl_k_busy_wait+0x6>
		if ((current_cycles - start_cycles) >= cycles_to_wait) {
			break;
		}
	}
#else
	arch_busy_wait(usec_to_wait);
    4bbe:	f7fc bd99 	b.w	16f4 <arch_busy_wait>
#endif /* CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT */
	SYS_PORT_TRACING_FUNC_EXIT(k_thread, busy_wait, usec_to_wait);
}
    4bc2:	4770      	bx	lr

00004bc4 <z_device_state_init>:
}
    4bc4:	4770      	bx	lr

00004bc6 <_OffsetAbsSyms>:

#include <gen_offset.h>

#include "offsets_aarch32.c"

GEN_ABS_SYM_END
    4bc6:	4770      	bx	lr

00004bc8 <z_arm_platform_init>:
	 */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r0, =SystemInit
	bx r0
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	b SystemInit
    4bc8:	f7fd bd3c 	b.w	2644 <SystemInit>
