
zephyr.elf:     file format elf32-littlearm


Disassembly of section rom_start:

00000000 <_vector_start>:

void i2c_dump_msgs(const char *name, const struct i2c_msg *msgs,
		   uint8_t num_msgs, uint16_t addr)
{
	LOG_DBG("I2C msg: %s, addr=%x", name, addr);
	for (unsigned int i = 0; i < num_msgs; i++) {
   0:	20001290 	.word	0x20001290
   4:	00002b6d 	.word	0x00002b6d
   8:	000072b5 	.word	0x000072b5
int lm75_init(const struct device *dev)
{
	struct lm75_config *cfg = (struct lm75_config *)dev->config;

	if (device_is_ready(cfg->i2c_dev)) {
		return 0;
   c:	00002b25 	.word	0x00002b25
 * @return Source ID.
 */
static inline uint32_t log_const_source_id(
				const struct log_source_const_data *data)
{
	return ((uint8_t *)data - (uint8_t *)__log_const_start)/
  10:	00002b25 	.word	0x00002b25
  14:	00002b25 	.word	0x00002b25
	}

	LOG_ERR("I2C dev not ready");
  18:	00002b25 	.word	0x00002b25
	...
  2c:	000022fd 	.word	0x000022fd
	return -ENODEV;
  30:	00002b25 	.word	0x00002b25
  34:	00000000 	.word	0x00000000
  38:	000022b1 	.word	0x000022b1
  3c:	0000766f 	.word	0x0000766f

00000040 <_irq_vector_table>:
  40:	00002381 00002381 00002381 00002381     .#...#...#...#..
  50:	00002381 00002381 00002381 00002381     .#...#...#...#..
  60:	00002381 00002381 00002381 00002381     .#...#...#...#..
  70:	00002381 00002381 00002381 00002381     .#...#...#...#..
  80:	00002381 00002381 00002381 00002381     .#...#...#...#..
  90:	00002381 00002381 00002381 00002381     .#...#...#...#..
  a0:	00002381 00002381 00002381 00002381     .#...#...#...#..
  b0:	00002381 00002381 00002381 00002381     .#...#...#...#..
  c0:	00002381 00002381 00002381 00002381     .#...#...#...#..
  d0:	00002381 00002381 00002381 00002381     .#...#...#...#..
  e0:	00002381 00002381 00002381 00002381     .#...#...#...#..
  f0:	00002381 00002381 00002381 00002381     .#...#...#...#..

Disassembly of section text:

00000100 <__aeabi_uldivmod>:
     100:	b953      	cbnz	r3, 118 <__aeabi_uldivmod+0x18>
     102:	b94a      	cbnz	r2, 118 <__aeabi_uldivmod+0x18>
     104:	2900      	cmp	r1, #0
     106:	bf08      	it	eq
     108:	2800      	cmpeq	r0, #0
     10a:	bf1c      	itt	ne
     10c:	f04f 31ff 	movne.w	r1, #4294967295
     110:	f04f 30ff 	movne.w	r0, #4294967295
     114:	f000 b96c 	b.w	3f0 <__aeabi_idiv0>
     118:	f1ad 0c08 	sub.w	ip, sp, #8
     11c:	e96d ce04 	strd	ip, lr, [sp, #-16]!
     120:	f000 f806 	bl	130 <__udivmoddi4>
     124:	f8dd e004 	ldr.w	lr, [sp, #4]
     128:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
     12c:	b004      	add	sp, #16
     12e:	4770      	bx	lr

00000130 <__udivmoddi4>:
     130:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
     134:	9e08      	ldr	r6, [sp, #32]
     136:	460d      	mov	r5, r1
     138:	4604      	mov	r4, r0
     13a:	468e      	mov	lr, r1
     13c:	2b00      	cmp	r3, #0
     13e:	f040 8082 	bne.w	246 <CONFIG_FLASH_SIZE+0x46>
     142:	428a      	cmp	r2, r1
     144:	4617      	mov	r7, r2
     146:	d946      	bls.n	1d6 <CONFIG_IDLE_STACK_SIZE+0x96>
     148:	fab2 f282 	clz	r2, r2
     14c:	b14a      	cbz	r2, 162 <CONFIG_IDLE_STACK_SIZE+0x22>
     14e:	f1c2 0120 	rsb	r1, r2, #32
     152:	fa05 f302 	lsl.w	r3, r5, r2
     156:	fa20 f101 	lsr.w	r1, r0, r1
     15a:	4097      	lsls	r7, r2
     15c:	ea41 0e03 	orr.w	lr, r1, r3
     160:	4094      	lsls	r4, r2
     162:	ea4f 4817 	mov.w	r8, r7, lsr #16
     166:	0c23      	lsrs	r3, r4, #16
     168:	fbbe fcf8 	udiv	ip, lr, r8
     16c:	b2b9      	uxth	r1, r7
     16e:	fb08 ee1c 	mls	lr, r8, ip, lr
     172:	ea43 430e 	orr.w	r3, r3, lr, lsl #16
     176:	fb0c f001 	mul.w	r0, ip, r1
     17a:	4298      	cmp	r0, r3
     17c:	d90a      	bls.n	194 <CONFIG_IDLE_STACK_SIZE+0x54>
     17e:	18fb      	adds	r3, r7, r3
     180:	f10c 35ff 	add.w	r5, ip, #4294967295
     184:	f080 8116 	bcs.w	3b4 <CONFIG_LOG_PROCESS_THREAD_STACK_SIZE+0xb4>
     188:	4298      	cmp	r0, r3
     18a:	f240 8113 	bls.w	3b4 <CONFIG_LOG_PROCESS_THREAD_STACK_SIZE+0xb4>
     18e:	f1ac 0c02 	sub.w	ip, ip, #2
     192:	443b      	add	r3, r7
     194:	1a1b      	subs	r3, r3, r0
     196:	b2a4      	uxth	r4, r4
     198:	fbb3 f0f8 	udiv	r0, r3, r8
     19c:	fb08 3310 	mls	r3, r8, r0, r3
     1a0:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
     1a4:	fb00 f101 	mul.w	r1, r0, r1
     1a8:	42a1      	cmp	r1, r4
     1aa:	d909      	bls.n	1c0 <CONFIG_IDLE_STACK_SIZE+0x80>
     1ac:	193c      	adds	r4, r7, r4
     1ae:	f100 33ff 	add.w	r3, r0, #4294967295
     1b2:	f080 8101 	bcs.w	3b8 <CONFIG_LOG_PROCESS_THREAD_STACK_SIZE+0xb8>
     1b6:	42a1      	cmp	r1, r4
     1b8:	f240 80fe 	bls.w	3b8 <CONFIG_LOG_PROCESS_THREAD_STACK_SIZE+0xb8>
     1bc:	3802      	subs	r0, #2
     1be:	443c      	add	r4, r7
     1c0:	1a64      	subs	r4, r4, r1
     1c2:	ea40 400c 	orr.w	r0, r0, ip, lsl #16
     1c6:	2100      	movs	r1, #0
     1c8:	b11e      	cbz	r6, 1d2 <CONFIG_IDLE_STACK_SIZE+0x92>
     1ca:	40d4      	lsrs	r4, r2
     1cc:	2300      	movs	r3, #0
     1ce:	e9c6 4300 	strd	r4, r3, [r6]
     1d2:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
     1d6:	b902      	cbnz	r2, 1da <CONFIG_IDLE_STACK_SIZE+0x9a>
     1d8:	deff      	udf	#255	; 0xff
     1da:	fab2 f282 	clz	r2, r2
     1de:	2a00      	cmp	r2, #0
     1e0:	d14f      	bne.n	282 <CONFIG_FLASH_SIZE+0x82>
     1e2:	1bcb      	subs	r3, r1, r7
     1e4:	ea4f 4e17 	mov.w	lr, r7, lsr #16
     1e8:	fa1f f887 	uxth.w	r8, r7
     1ec:	2101      	movs	r1, #1
     1ee:	fbb3 fcfe 	udiv	ip, r3, lr
     1f2:	0c25      	lsrs	r5, r4, #16
     1f4:	fb0e 331c 	mls	r3, lr, ip, r3
     1f8:	ea45 4503 	orr.w	r5, r5, r3, lsl #16
     1fc:	fb08 f30c 	mul.w	r3, r8, ip
     200:	42ab      	cmp	r3, r5
     202:	d907      	bls.n	214 <CONFIG_FLASH_SIZE+0x14>
     204:	197d      	adds	r5, r7, r5
     206:	f10c 30ff 	add.w	r0, ip, #4294967295
     20a:	d202      	bcs.n	212 <CONFIG_FLASH_SIZE+0x12>
     20c:	42ab      	cmp	r3, r5
     20e:	f200 80e7 	bhi.w	3e0 <CONFIG_LOG_PROCESS_THREAD_STACK_SIZE+0xe0>
     212:	4684      	mov	ip, r0
     214:	1aed      	subs	r5, r5, r3
     216:	b2a3      	uxth	r3, r4
     218:	fbb5 f0fe 	udiv	r0, r5, lr
     21c:	fb0e 5510 	mls	r5, lr, r0, r5
     220:	ea43 4405 	orr.w	r4, r3, r5, lsl #16
     224:	fb08 f800 	mul.w	r8, r8, r0
     228:	45a0      	cmp	r8, r4
     22a:	d907      	bls.n	23c <CONFIG_FLASH_SIZE+0x3c>
     22c:	193c      	adds	r4, r7, r4
     22e:	f100 33ff 	add.w	r3, r0, #4294967295
     232:	d202      	bcs.n	23a <CONFIG_FLASH_SIZE+0x3a>
     234:	45a0      	cmp	r8, r4
     236:	f200 80d7 	bhi.w	3e8 <CONFIG_LOG_PROCESS_THREAD_SLEEP_MS>
     23a:	4618      	mov	r0, r3
     23c:	eba4 0408 	sub.w	r4, r4, r8
     240:	ea40 400c 	orr.w	r0, r0, ip, lsl #16
     244:	e7c0      	b.n	1c8 <CONFIG_IDLE_STACK_SIZE+0x88>
     246:	428b      	cmp	r3, r1
     248:	d908      	bls.n	25c <CONFIG_FLASH_SIZE+0x5c>
     24a:	2e00      	cmp	r6, #0
     24c:	f000 80af 	beq.w	3ae <CONFIG_LOG_PROCESS_THREAD_STACK_SIZE+0xae>
     250:	2100      	movs	r1, #0
     252:	e9c6 0500 	strd	r0, r5, [r6]
     256:	4608      	mov	r0, r1
     258:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
     25c:	fab3 f183 	clz	r1, r3
     260:	2900      	cmp	r1, #0
     262:	d14b      	bne.n	2fc <CONFIG_FLASH_SIZE+0xfc>
     264:	42ab      	cmp	r3, r5
     266:	d302      	bcc.n	26e <CONFIG_FLASH_SIZE+0x6e>
     268:	4282      	cmp	r2, r0
     26a:	f200 80b7 	bhi.w	3dc <CONFIG_LOG_PROCESS_THREAD_STACK_SIZE+0xdc>
     26e:	1a84      	subs	r4, r0, r2
     270:	eb65 0303 	sbc.w	r3, r5, r3
     274:	2001      	movs	r0, #1
     276:	469e      	mov	lr, r3
     278:	2e00      	cmp	r6, #0
     27a:	d0aa      	beq.n	1d2 <CONFIG_IDLE_STACK_SIZE+0x92>
     27c:	e9c6 4e00 	strd	r4, lr, [r6]
     280:	e7a7      	b.n	1d2 <CONFIG_IDLE_STACK_SIZE+0x92>
     282:	f1c2 0c20 	rsb	ip, r2, #32
     286:	fa01 f302 	lsl.w	r3, r1, r2
     28a:	4097      	lsls	r7, r2
     28c:	fa20 f00c 	lsr.w	r0, r0, ip
     290:	ea4f 4e17 	mov.w	lr, r7, lsr #16
     294:	fa21 fc0c 	lsr.w	ip, r1, ip
     298:	4318      	orrs	r0, r3
     29a:	fbbc f1fe 	udiv	r1, ip, lr
     29e:	0c05      	lsrs	r5, r0, #16
     2a0:	fb0e cc11 	mls	ip, lr, r1, ip
     2a4:	fa1f f887 	uxth.w	r8, r7
     2a8:	ea45 450c 	orr.w	r5, r5, ip, lsl #16
     2ac:	fb01 f308 	mul.w	r3, r1, r8
     2b0:	42ab      	cmp	r3, r5
     2b2:	fa04 f402 	lsl.w	r4, r4, r2
     2b6:	d909      	bls.n	2cc <CONFIG_FLASH_SIZE+0xcc>
     2b8:	197d      	adds	r5, r7, r5
     2ba:	f101 3cff 	add.w	ip, r1, #4294967295
     2be:	f080 808b 	bcs.w	3d8 <CONFIG_LOG_PROCESS_THREAD_STACK_SIZE+0xd8>
     2c2:	42ab      	cmp	r3, r5
     2c4:	f240 8088 	bls.w	3d8 <CONFIG_LOG_PROCESS_THREAD_STACK_SIZE+0xd8>
     2c8:	3902      	subs	r1, #2
     2ca:	443d      	add	r5, r7
     2cc:	1aeb      	subs	r3, r5, r3
     2ce:	b285      	uxth	r5, r0
     2d0:	fbb3 f0fe 	udiv	r0, r3, lr
     2d4:	fb0e 3310 	mls	r3, lr, r0, r3
     2d8:	ea45 4503 	orr.w	r5, r5, r3, lsl #16
     2dc:	fb00 f308 	mul.w	r3, r0, r8
     2e0:	42ab      	cmp	r3, r5
     2e2:	d907      	bls.n	2f4 <CONFIG_FLASH_SIZE+0xf4>
     2e4:	197d      	adds	r5, r7, r5
     2e6:	f100 3cff 	add.w	ip, r0, #4294967295
     2ea:	d271      	bcs.n	3d0 <CONFIG_LOG_PROCESS_THREAD_STACK_SIZE+0xd0>
     2ec:	42ab      	cmp	r3, r5
     2ee:	d96f      	bls.n	3d0 <CONFIG_LOG_PROCESS_THREAD_STACK_SIZE+0xd0>
     2f0:	3802      	subs	r0, #2
     2f2:	443d      	add	r5, r7
     2f4:	1aeb      	subs	r3, r5, r3
     2f6:	ea40 4101 	orr.w	r1, r0, r1, lsl #16
     2fa:	e778      	b.n	1ee <CONFIG_IDLE_STACK_SIZE+0xae>
     2fc:	f1c1 0c20 	rsb	ip, r1, #32
     300:	408b      	lsls	r3, r1
     302:	fa22 f70c 	lsr.w	r7, r2, ip
     306:	431f      	orrs	r7, r3
     308:	fa20 f40c 	lsr.w	r4, r0, ip
     30c:	fa05 f301 	lsl.w	r3, r5, r1
     310:	ea4f 4e17 	mov.w	lr, r7, lsr #16
     314:	fa25 f50c 	lsr.w	r5, r5, ip
     318:	431c      	orrs	r4, r3
     31a:	0c23      	lsrs	r3, r4, #16
     31c:	fbb5 f9fe 	udiv	r9, r5, lr
     320:	fa1f f887 	uxth.w	r8, r7
     324:	fb0e 5519 	mls	r5, lr, r9, r5
     328:	ea43 4505 	orr.w	r5, r3, r5, lsl #16
     32c:	fb09 fa08 	mul.w	sl, r9, r8
     330:	45aa      	cmp	sl, r5
     332:	fa02 f201 	lsl.w	r2, r2, r1
     336:	fa00 f301 	lsl.w	r3, r0, r1
     33a:	d908      	bls.n	34e <CONFIG_LOG_PROCESS_THREAD_STACK_SIZE+0x4e>
     33c:	197d      	adds	r5, r7, r5
     33e:	f109 30ff 	add.w	r0, r9, #4294967295
     342:	d247      	bcs.n	3d4 <CONFIG_LOG_PROCESS_THREAD_STACK_SIZE+0xd4>
     344:	45aa      	cmp	sl, r5
     346:	d945      	bls.n	3d4 <CONFIG_LOG_PROCESS_THREAD_STACK_SIZE+0xd4>
     348:	f1a9 0902 	sub.w	r9, r9, #2
     34c:	443d      	add	r5, r7
     34e:	eba5 050a 	sub.w	r5, r5, sl
     352:	b2a4      	uxth	r4, r4
     354:	fbb5 f0fe 	udiv	r0, r5, lr
     358:	fb0e 5510 	mls	r5, lr, r0, r5
     35c:	ea44 4405 	orr.w	r4, r4, r5, lsl #16
     360:	fb00 f808 	mul.w	r8, r0, r8
     364:	45a0      	cmp	r8, r4
     366:	d907      	bls.n	378 <CONFIG_LOG_PROCESS_THREAD_STACK_SIZE+0x78>
     368:	193c      	adds	r4, r7, r4
     36a:	f100 35ff 	add.w	r5, r0, #4294967295
     36e:	d22d      	bcs.n	3cc <CONFIG_LOG_PROCESS_THREAD_STACK_SIZE+0xcc>
     370:	45a0      	cmp	r8, r4
     372:	d92b      	bls.n	3cc <CONFIG_LOG_PROCESS_THREAD_STACK_SIZE+0xcc>
     374:	3802      	subs	r0, #2
     376:	443c      	add	r4, r7
     378:	ea40 4009 	orr.w	r0, r0, r9, lsl #16
     37c:	eba4 0408 	sub.w	r4, r4, r8
     380:	fba0 8902 	umull	r8, r9, r0, r2
     384:	454c      	cmp	r4, r9
     386:	46c6      	mov	lr, r8
     388:	464d      	mov	r5, r9
     38a:	d319      	bcc.n	3c0 <CONFIG_LOG_PROCESS_THREAD_STACK_SIZE+0xc0>
     38c:	d016      	beq.n	3bc <CONFIG_LOG_PROCESS_THREAD_STACK_SIZE+0xbc>
     38e:	b15e      	cbz	r6, 3a8 <CONFIG_LOG_PROCESS_THREAD_STACK_SIZE+0xa8>
     390:	ebb3 020e 	subs.w	r2, r3, lr
     394:	eb64 0405 	sbc.w	r4, r4, r5
     398:	fa04 fc0c 	lsl.w	ip, r4, ip
     39c:	40ca      	lsrs	r2, r1
     39e:	ea4c 0202 	orr.w	r2, ip, r2
     3a2:	40cc      	lsrs	r4, r1
     3a4:	e9c6 2400 	strd	r2, r4, [r6]
     3a8:	2100      	movs	r1, #0
     3aa:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
     3ae:	4631      	mov	r1, r6
     3b0:	4630      	mov	r0, r6
     3b2:	e70e      	b.n	1d2 <CONFIG_IDLE_STACK_SIZE+0x92>
     3b4:	46ac      	mov	ip, r5
     3b6:	e6ed      	b.n	194 <CONFIG_IDLE_STACK_SIZE+0x54>
     3b8:	4618      	mov	r0, r3
     3ba:	e701      	b.n	1c0 <CONFIG_IDLE_STACK_SIZE+0x80>
     3bc:	4543      	cmp	r3, r8
     3be:	d2e6      	bcs.n	38e <CONFIG_LOG_PROCESS_THREAD_STACK_SIZE+0x8e>
     3c0:	ebb8 0e02 	subs.w	lr, r8, r2
     3c4:	eb69 0507 	sbc.w	r5, r9, r7
     3c8:	3801      	subs	r0, #1
     3ca:	e7e0      	b.n	38e <CONFIG_LOG_PROCESS_THREAD_STACK_SIZE+0x8e>
     3cc:	4628      	mov	r0, r5
     3ce:	e7d3      	b.n	378 <CONFIG_LOG_PROCESS_THREAD_STACK_SIZE+0x78>
     3d0:	4660      	mov	r0, ip
     3d2:	e78f      	b.n	2f4 <CONFIG_FLASH_SIZE+0xf4>
     3d4:	4681      	mov	r9, r0
     3d6:	e7ba      	b.n	34e <CONFIG_LOG_PROCESS_THREAD_STACK_SIZE+0x4e>
     3d8:	4661      	mov	r1, ip
     3da:	e777      	b.n	2cc <CONFIG_FLASH_SIZE+0xcc>
     3dc:	4608      	mov	r0, r1
     3de:	e74b      	b.n	278 <CONFIG_FLASH_SIZE+0x78>
     3e0:	f1ac 0c02 	sub.w	ip, ip, #2
     3e4:	443d      	add	r5, r7
     3e6:	e715      	b.n	214 <CONFIG_FLASH_SIZE+0x14>
     3e8:	3802      	subs	r0, #2
     3ea:	443c      	add	r4, r7
     3ec:	e726      	b.n	23c <CONFIG_FLASH_SIZE+0x3c>
     3ee:	bf00      	nop

000003f0 <__aeabi_idiv0>:
     3f0:	4770      	bx	lr
     3f2:	bf00      	nop

000003f4 <strcmp>:
     3f4:	f810 2b01 	ldrb.w	r2, [r0], #1
     3f8:	f811 3b01 	ldrb.w	r3, [r1], #1
     3fc:	2a01      	cmp	r2, #1
     3fe:	bf28      	it	cs
     400:	429a      	cmpcs	r2, r3
     402:	d0f7      	beq.n	3f4 <strcmp>
     404:	1ad0      	subs	r0, r2, r3
     406:	4770      	bx	lr

00000408 <strlen>:
     408:	4603      	mov	r3, r0
     40a:	f813 2b01 	ldrb.w	r2, [r3], #1
     40e:	2a00      	cmp	r2, #0
     410:	d1fb      	bne.n	40a <strlen+0x2>
     412:	1a18      	subs	r0, r3, r0
     414:	3801      	subs	r0, #1
     416:	4770      	bx	lr

00000418 <main>:
#include <drivers/sensor.h>
#include <logging/log.h>
#include <stdio.h>

void main(void)
{
     418:	b510      	push	{r4, lr}
     41a:	b082      	sub	sp, #8
		/* coverity[OVERRUN] */
		return (const struct device *) arch_syscall_invoke1(*(uintptr_t *)&name, K_SYSCALL_DEVICE_GET_BINDING);
	}
#endif
	compiler_barrier();
	return z_impl_device_get_binding(name);
     41c:	4815      	ldr	r0, [pc, #84]	; (474 <main+0x5c>)
     41e:	f004 fe4b 	bl	50b8 <z_impl_device_get_binding>
	struct sensor_value temp_value;
	int read;
	int ret;
	const struct device *dev = device_get_binding(DT_LABEL(DT_INST(0, ti_lm75)));

	if (dev == NULL) {
     422:	4604      	mov	r4, r0
     424:	b1c0      	cbz	r0, 458 <main+0x40>
 */
__syscall int sensor_sample_fetch(const struct device *dev);

static inline int z_impl_sensor_sample_fetch(const struct device *dev)
{
	const struct sensor_driver_api *api =
     426:	68a3      	ldr	r3, [r4, #8]
		(const struct sensor_driver_api *)dev->api;

	return api->sample_fetch(dev, SENSOR_CHAN_ALL);
     428:	68db      	ldr	r3, [r3, #12]
     42a:	2139      	movs	r1, #57	; 0x39
     42c:	4620      	mov	r0, r4
     42e:	4798      	blx	r3

	while(1)
	{
		/*lm75*/
		read = sensor_sample_fetch(dev);
		if (read) {
     430:	b9b0      	cbnz	r0, 460 <main+0x48>

static inline int z_impl_sensor_channel_get(const struct device *dev,
					    enum sensor_channel chan,
					    struct sensor_value *val)
{
	const struct sensor_driver_api *api =
     432:	68a3      	ldr	r3, [r4, #8]
		(const struct sensor_driver_api *)dev->api;

	return api->channel_get(dev, chan, val);
     434:	691b      	ldr	r3, [r3, #16]
     436:	466a      	mov	r2, sp
     438:	210d      	movs	r1, #13
     43a:	4620      	mov	r0, r4
     43c:	4798      	blx	r3
			printk("sample fetch error\n");
			return;
		}

		ret = sensor_channel_get(dev, SENSOR_CHAN_AMBIENT_TEMP, &temp_value);
		if (ret) {
     43e:	4601      	mov	r1, r0
     440:	b998      	cbnz	r0, 46a <main+0x52>
			printk("Failed to get measurements (%d)\n", ret);
			return;
		}
		printk("temp is %d.%d oC\n", temp_value.val1, temp_value.val2);
     442:	9a01      	ldr	r2, [sp, #4]
     444:	9900      	ldr	r1, [sp, #0]
     446:	480c      	ldr	r0, [pc, #48]	; (478 <main+0x60>)
     448:	f006 fa78 	bl	693c <printk>
		/* coverity[OVERRUN] */
		return (int32_t) arch_syscall_invoke2(parm0.split.lo, parm0.split.hi, K_SYSCALL_K_SLEEP);
	}
#endif
	compiler_barrier();
	return z_impl_k_sleep(timeout);
     44c:	f44f 4000 	mov.w	r0, #32768	; 0x8000
     450:	2100      	movs	r1, #0
     452:	f005 ff57 	bl	6304 <z_impl_k_sleep>
	{
     456:	e7e6      	b.n	426 <main+0xe>
		printk("device not found.  aborting test.\n");
     458:	4808      	ldr	r0, [pc, #32]	; (47c <main+0x64>)
     45a:	f006 fa6f 	bl	693c <printk>
		return;
     45e:	e002      	b.n	466 <main+0x4e>
			printk("sample fetch error\n");
     460:	4807      	ldr	r0, [pc, #28]	; (480 <main+0x68>)
     462:	f006 fa6b 	bl	693c <printk>
		k_sleep(K_MSEC(1000));
	}
}
     466:	b002      	add	sp, #8
     468:	bd10      	pop	{r4, pc}
			printk("Failed to get measurements (%d)\n", ret);
     46a:	4806      	ldr	r0, [pc, #24]	; (484 <main+0x6c>)
     46c:	f006 fa66 	bl	693c <printk>
			return;
     470:	e7f9      	b.n	466 <main+0x4e>
     472:	bf00      	nop
     474:	00008488 	.word	0x00008488
     478:	000084ec 	.word	0x000084ec
     47c:	00008490 	.word	0x00008490
     480:	000084b4 	.word	0x000084b4
     484:	000084c8 	.word	0x000084c8

00000488 <char_out>:
struct out_context {
	int count;
};

static int char_out(int c, void *ctx_p)
{
     488:	b508      	push	{r3, lr}
	struct out_context *ctx = ctx_p;

	ctx->count++;
     48a:	680b      	ldr	r3, [r1, #0]
     48c:	3301      	adds	r3, #1
     48e:	600b      	str	r3, [r1, #0]
	return _char_out(c);
     490:	4b01      	ldr	r3, [pc, #4]	; (498 <char_out+0x10>)
     492:	681b      	ldr	r3, [r3, #0]
     494:	4798      	blx	r3
}
     496:	bd08      	pop	{r3, pc}
     498:	20000000 	.word	0x20000000

0000049c <__printk_hook_install>:
	_char_out = fn;
     49c:	4b01      	ldr	r3, [pc, #4]	; (4a4 <__printk_hook_install+0x8>)
     49e:	6018      	str	r0, [r3, #0]
}
     4a0:	4770      	bx	lr
     4a2:	bf00      	nop
     4a4:	20000000 	.word	0x20000000

000004a8 <vprintk>:
#endif
	}
}
#else
void vprintk(const char *fmt, va_list ap)
{
     4a8:	b500      	push	{lr}
     4aa:	b083      	sub	sp, #12
     4ac:	4602      	mov	r2, r0
     4ae:	460b      	mov	r3, r1
	struct out_context ctx = { 0 };
     4b0:	2100      	movs	r1, #0
     4b2:	9101      	str	r1, [sp, #4]
#ifdef CONFIG_PRINTK_SYNC
	k_spinlock_key_t key = k_spin_lock(&lock);
#endif

	cbvprintf(char_out, &ctx, fmt, ap);
     4b4:	a901      	add	r1, sp, #4
     4b6:	4803      	ldr	r0, [pc, #12]	; (4c4 <vprintk+0x1c>)
     4b8:	f000 f94e 	bl	758 <cbvprintf>

#ifdef CONFIG_PRINTK_SYNC
	k_spin_unlock(&lock, key);
#endif
}
     4bc:	b003      	add	sp, #12
     4be:	f85d fb04 	ldr.w	pc, [sp], #4
     4c2:	bf00      	nop
     4c4:	00000489 	.word	0x00000489

000004c8 <vsnprintk>:

	return ret;
}

int vsnprintk(char *str, size_t size, const char *fmt, va_list ap)
{
     4c8:	b510      	push	{r4, lr}
     4ca:	b084      	sub	sp, #16
     4cc:	4604      	mov	r4, r0
	struct str_context ctx = { str, size, 0 };
     4ce:	9001      	str	r0, [sp, #4]
     4d0:	9102      	str	r1, [sp, #8]
     4d2:	2100      	movs	r1, #0
     4d4:	9103      	str	r1, [sp, #12]

	cbvprintf(str_out, &ctx, fmt, ap);
     4d6:	a901      	add	r1, sp, #4
     4d8:	4805      	ldr	r0, [pc, #20]	; (4f0 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x8>)
     4da:	f000 f93d 	bl	758 <cbvprintf>

	if (ctx.count < ctx.max) {
     4de:	9b03      	ldr	r3, [sp, #12]
     4e0:	9a02      	ldr	r2, [sp, #8]
     4e2:	4293      	cmp	r3, r2
     4e4:	da01      	bge.n	4ea <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x2>
		str[ctx.count] = '\0';
     4e6:	2200      	movs	r2, #0
     4e8:	54e2      	strb	r2, [r4, r3]
	}

	return ctx.count;
}
     4ea:	9803      	ldr	r0, [sp, #12]
     4ec:	b004      	add	sp, #16
     4ee:	bd10      	pop	{r4, pc}
     4f0:	0000690d 	.word	0x0000690d

000004f4 <process_event>:
 * regions.
 */
static void process_event(struct onoff_manager *mgr,
			  int evt,
			  k_spinlock_key_t key)
{
     4f4:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
     4f8:	b083      	sub	sp, #12
     4fa:	4604      	mov	r4, r0
     4fc:	4608      	mov	r0, r1
     4fe:	4615      	mov	r5, r2
	sys_slist_t clients;
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     500:	8ba3      	ldrh	r3, [r4, #28]
	__ASSERT_NO_MSG(evt != EVT_NOP);

	/* If this is a nested call record the event for processing in
	 * the top invocation.
	 */
	if (processing) {
     502:	f013 0f08 	tst.w	r3, #8
     506:	d105      	bne.n	514 <process_event+0x20>
     508:	f003 0607 	and.w	r6, r3, #7
 *
 * @param list A pointer on the list to initialize
 */
static inline void sys_slist_init(sys_slist_t *list)
{
	list->head = NULL;
     50c:	2300      	movs	r3, #0
     50e:	9300      	str	r3, [sp, #0]
	list->tail = NULL;
     510:	9301      	str	r3, [sp, #4]
}
     512:	e069      	b.n	5e8 <process_event+0xf4>
		if (evt == EVT_COMPLETE) {
     514:	2901      	cmp	r1, #1
     516:	d009      	beq.n	52c <process_event+0x38>
			mgr->flags |= ONOFF_FLAG_COMPLETE;
		} else {
			__ASSERT_NO_MSG(evt == EVT_RECHECK);

			mgr->flags |= ONOFF_FLAG_RECHECK;
     518:	f043 0320 	orr.w	r3, r3, #32
     51c:	83a3      	strh	r3, [r4, #28]
	__asm__ volatile(
		"cpsie i;"
		"isb"
		: : : "memory");
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	__asm__ volatile(
     51e:	f385 8811 	msr	BASEPRI, r5
     522:	f3bf 8f6f 	isb	sy
		state = mgr->flags & ONOFF_STATE_MASK;
	} while (evt != EVT_NOP);

out:
	k_spin_unlock(&mgr->lock, key);
}
     526:	b003      	add	sp, #12
     528:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
			mgr->flags |= ONOFF_FLAG_COMPLETE;
     52c:	f043 0310 	orr.w	r3, r3, #16
     530:	83a3      	strh	r3, [r4, #28]
     532:	e7f4      	b.n	51e <process_event+0x2a>
			evt = process_recheck(mgr);
     534:	4620      	mov	r0, r4
     536:	f006 fa44 	bl	69c2 <process_recheck>
     53a:	e057      	b.n	5ec <process_event+0xf8>
			res = mgr->last_res;
     53c:	f8d4 9018 	ldr.w	r9, [r4, #24]
			process_complete(mgr, &clients, res);
     540:	464a      	mov	r2, r9
     542:	4669      	mov	r1, sp
     544:	4620      	mov	r0, r4
     546:	f006 fa55 	bl	69f4 <process_complete>
		onoff_transition_fn transit = NULL;
     54a:	2700      	movs	r7, #0
     54c:	e05a      	b.n	604 <process_event+0x110>
			transit = mgr->transitions->start;
     54e:	6923      	ldr	r3, [r4, #16]
     550:	681f      	ldr	r7, [r3, #0]
			set_state(mgr, ONOFF_STATE_TO_ON);
     552:	2106      	movs	r1, #6
     554:	4620      	mov	r0, r4
     556:	f006 fa0d 	bl	6974 <set_state>
		res = 0;
     55a:	f04f 0900 	mov.w	r9, #0
     55e:	e051      	b.n	604 <process_event+0x110>
			transit = mgr->transitions->stop;
     560:	6923      	ldr	r3, [r4, #16]
     562:	685f      	ldr	r7, [r3, #4]
			set_state(mgr, ONOFF_STATE_TO_OFF);
     564:	2104      	movs	r1, #4
     566:	4620      	mov	r0, r4
     568:	f006 fa04 	bl	6974 <set_state>
		res = 0;
     56c:	f04f 0900 	mov.w	r9, #0
     570:	e048      	b.n	604 <process_event+0x110>
			transit = mgr->transitions->reset;
     572:	6923      	ldr	r3, [r4, #16]
     574:	689f      	ldr	r7, [r3, #8]
			set_state(mgr, ONOFF_STATE_RESETTING);
     576:	2105      	movs	r1, #5
     578:	4620      	mov	r0, r4
     57a:	f006 f9fb 	bl	6974 <set_state>
		res = 0;
     57e:	f04f 0900 	mov.w	r9, #0
     582:	e03f      	b.n	604 <process_event+0x110>
				   && !sys_slist_is_empty(&mgr->monitors);
     584:	2200      	movs	r2, #0
     586:	e046      	b.n	616 <process_event+0x122>
     588:	2200      	movs	r2, #0
     58a:	e044      	b.n	616 <process_event+0x122>
			uint32_t flags = mgr->flags | ONOFF_FLAG_PROCESSING;
     58c:	f043 0308 	orr.w	r3, r3, #8
			mgr->flags = flags;
     590:	83a3      	strh	r3, [r4, #28]
     592:	f385 8811 	msr	BASEPRI, r5
     596:	f3bf 8f6f 	isb	sy
			if (do_monitors) {
     59a:	2900      	cmp	r1, #0
     59c:	d144      	bne.n	628 <process_event+0x134>
 *
 * @return A pointer on the first node of the list (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_head(sys_slist_t *list)
{
	return list->head;
     59e:	9b00      	ldr	r3, [sp, #0]
			if (!sys_slist_is_empty(&clients)) {
     5a0:	b12b      	cbz	r3, 5ae <process_event+0xba>
				notify_all(mgr, &clients, state, res);
     5a2:	464b      	mov	r3, r9
     5a4:	4642      	mov	r2, r8
     5a6:	4669      	mov	r1, sp
     5a8:	4620      	mov	r0, r4
     5aa:	f006 fa99 	bl	6ae0 <notify_all>
			if (transit != NULL) {
     5ae:	b117      	cbz	r7, 5b6 <process_event+0xc2>
				transit(mgr, transition_complete);
     5b0:	4925      	ldr	r1, [pc, #148]	; (648 <process_event+0x154>)
     5b2:	4620      	mov	r0, r4
     5b4:	47b8      	blx	r7
	__asm__ volatile(
     5b6:	f04f 0320 	mov.w	r3, #32
     5ba:	f3ef 8511 	mrs	r5, BASEPRI
     5be:	f383 8812 	msr	BASEPRI_MAX, r3
     5c2:	f3bf 8f6f 	isb	sy
			mgr->flags &= ~ONOFF_FLAG_PROCESSING;
     5c6:	8ba3      	ldrh	r3, [r4, #28]
     5c8:	f023 0308 	bic.w	r3, r3, #8
     5cc:	83a3      	strh	r3, [r4, #28]
		if ((mgr->flags & ONOFF_FLAG_COMPLETE) != 0) {
     5ce:	8ba3      	ldrh	r3, [r4, #28]
     5d0:	f013 0f10 	tst.w	r3, #16
     5d4:	d02e      	beq.n	634 <process_event+0x140>
			mgr->flags &= ~ONOFF_FLAG_COMPLETE;
     5d6:	f023 0310 	bic.w	r3, r3, #16
     5da:	83a3      	strh	r3, [r4, #28]
			evt = EVT_COMPLETE;
     5dc:	2001      	movs	r0, #1
		state = mgr->flags & ONOFF_STATE_MASK;
     5de:	8ba6      	ldrh	r6, [r4, #28]
     5e0:	f006 0607 	and.w	r6, r6, #7
	} while (evt != EVT_NOP);
     5e4:	2800      	cmp	r0, #0
     5e6:	d09a      	beq.n	51e <process_event+0x2a>
		if (evt == EVT_RECHECK) {
     5e8:	2802      	cmp	r0, #2
     5ea:	d0a3      	beq.n	534 <process_event+0x40>
		if (evt == EVT_NOP) {
     5ec:	2800      	cmp	r0, #0
     5ee:	d096      	beq.n	51e <process_event+0x2a>
		if (evt == EVT_COMPLETE) {
     5f0:	2801      	cmp	r0, #1
     5f2:	d0a3      	beq.n	53c <process_event+0x48>
		} else if (evt == EVT_START) {
     5f4:	2803      	cmp	r0, #3
     5f6:	d0aa      	beq.n	54e <process_event+0x5a>
		} else if (evt == EVT_STOP) {
     5f8:	2804      	cmp	r0, #4
     5fa:	d0b1      	beq.n	560 <process_event+0x6c>
		} else if (evt == EVT_RESET) {
     5fc:	2805      	cmp	r0, #5
     5fe:	d0b8      	beq.n	572 <process_event+0x7e>
		onoff_transition_fn transit = NULL;
     600:	2700      	movs	r7, #0
		res = 0;
     602:	46b9      	mov	r9, r7
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     604:	8ba3      	ldrh	r3, [r4, #28]
     606:	f003 0807 	and.w	r8, r3, #7
				   && !sys_slist_is_empty(&mgr->monitors);
     60a:	45b0      	cmp	r8, r6
     60c:	d0ba      	beq.n	584 <process_event+0x90>
     60e:	68a2      	ldr	r2, [r4, #8]
     610:	2a00      	cmp	r2, #0
     612:	d0b9      	beq.n	588 <process_event+0x94>
     614:	2201      	movs	r2, #1
		if (do_monitors
     616:	4611      	mov	r1, r2
     618:	2a00      	cmp	r2, #0
     61a:	d1b7      	bne.n	58c <process_event+0x98>
     61c:	9a00      	ldr	r2, [sp, #0]
		    || !sys_slist_is_empty(&clients)
     61e:	2a00      	cmp	r2, #0
     620:	d1b4      	bne.n	58c <process_event+0x98>
		    || (transit != NULL)) {
     622:	2f00      	cmp	r7, #0
     624:	d1b2      	bne.n	58c <process_event+0x98>
     626:	e7d2      	b.n	5ce <process_event+0xda>
				notify_monitors(mgr, state, res);
     628:	464a      	mov	r2, r9
     62a:	4641      	mov	r1, r8
     62c:	4620      	mov	r0, r4
     62e:	f006 f9a9 	bl	6984 <notify_monitors>
     632:	e7b4      	b.n	59e <process_event+0xaa>
		} else if ((mgr->flags & ONOFF_FLAG_RECHECK) != 0) {
     634:	f013 0f20 	tst.w	r3, #32
     638:	d004      	beq.n	644 <process_event+0x150>
			mgr->flags &= ~ONOFF_FLAG_RECHECK;
     63a:	f023 0320 	bic.w	r3, r3, #32
     63e:	83a3      	strh	r3, [r4, #28]
			evt = EVT_RECHECK;
     640:	2002      	movs	r0, #2
     642:	e7cc      	b.n	5de <process_event+0xea>
		evt = EVT_NOP;
     644:	2000      	movs	r0, #0
     646:	e7ca      	b.n	5de <process_event+0xea>
     648:	00006b0f 	.word	0x00006b0f

0000064c <extract_decimal>:
 * the referenced text.
 *
 * @return the decoded integer value.
 */
static size_t extract_decimal(const char **str)
{
     64c:	b410      	push	{r4}
     64e:	4604      	mov	r4, r0
	const char *sp = *str;
     650:	6802      	ldr	r2, [r0, #0]
	size_t val = 0;
     652:	2000      	movs	r0, #0

	while (isdigit((int)(unsigned char)*sp)) {
     654:	7813      	ldrb	r3, [r2, #0]
     656:	4907      	ldr	r1, [pc, #28]	; (674 <extract_decimal+0x28>)
     658:	5c59      	ldrb	r1, [r3, r1]
     65a:	f011 0f04 	tst.w	r1, #4
     65e:	d006      	beq.n	66e <extract_decimal+0x22>
		val = 10U * val + *sp++ - '0';
     660:	eb00 0080 	add.w	r0, r0, r0, lsl #2
     664:	3201      	adds	r2, #1
     666:	eb03 0040 	add.w	r0, r3, r0, lsl #1
     66a:	3830      	subs	r0, #48	; 0x30
     66c:	e7f2      	b.n	654 <extract_decimal+0x8>
	}
	*str = sp;
     66e:	6022      	str	r2, [r4, #0]
	return val;
}
     670:	bc10      	pop	{r4}
     672:	4770      	bx	lr
     674:	00008ea6 	.word	0x00008ea6

00000678 <encode_uint>:
 */
static char *encode_uint(uint_value_type value,
			 struct conversion *conv,
			 char *bps,
			 const char *bpe)
{
     678:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     67c:	b083      	sub	sp, #12
     67e:	4604      	mov	r4, r0
     680:	460d      	mov	r5, r1
     682:	9201      	str	r2, [sp, #4]
     684:	469a      	mov	sl, r3
     686:	f8dd 8030 	ldr.w	r8, [sp, #48]	; 0x30
	bool upcase = isupper((int)conv->specifier);
     68a:	78d3      	ldrb	r3, [r2, #3]
     68c:	4a31      	ldr	r2, [pc, #196]	; (754 <encode_uint+0xdc>)
     68e:	f813 b002 	ldrb.w	fp, [r3, r2]
     692:	f00b 0b03 	and.w	fp, fp, #3
	switch (specifier) {
     696:	2b6f      	cmp	r3, #111	; 0x6f
     698:	d00f      	beq.n	6ba <encode_uint+0x42>
     69a:	d906      	bls.n	6aa <encode_uint+0x32>
     69c:	2b70      	cmp	r3, #112	; 0x70
     69e:	d00f      	beq.n	6c0 <encode_uint+0x48>
     6a0:	2b78      	cmp	r3, #120	; 0x78
     6a2:	d110      	bne.n	6c6 <encode_uint+0x4e>
		return 16;
     6a4:	f04f 0910 	mov.w	r9, #16
     6a8:	e023      	b.n	6f2 <encode_uint+0x7a>
	switch (specifier) {
     6aa:	2b58      	cmp	r3, #88	; 0x58
     6ac:	d002      	beq.n	6b4 <encode_uint+0x3c>
     6ae:	f04f 090a 	mov.w	r9, #10
     6b2:	e01e      	b.n	6f2 <encode_uint+0x7a>
		return 16;
     6b4:	f04f 0910 	mov.w	r9, #16
     6b8:	e01b      	b.n	6f2 <encode_uint+0x7a>
		return 8;
     6ba:	f04f 0908 	mov.w	r9, #8
     6be:	e018      	b.n	6f2 <encode_uint+0x7a>
		return 16;
     6c0:	f04f 0910 	mov.w	r9, #16
     6c4:	e015      	b.n	6f2 <encode_uint+0x7a>
	switch (specifier) {
     6c6:	f04f 090a 	mov.w	r9, #10
	const unsigned int radix = conversion_radix(conv->specifier);
	char *bp = bps + (bpe - bps);
     6ca:	e012      	b.n	6f2 <encode_uint+0x7a>

	do {
		unsigned int lsv = (unsigned int)(value % radix);

		*--bp = (lsv <= 9) ? ('0' + lsv)
     6cc:	b2d2      	uxtb	r2, r2
     6ce:	3230      	adds	r2, #48	; 0x30
     6d0:	b2d2      	uxtb	r2, r2
     6d2:	f808 2d01 	strb.w	r2, [r8, #-1]!
			: upcase ? ('A' + lsv - 10) : ('a' + lsv - 10);
		value /= radix;
     6d6:	4632      	mov	r2, r6
     6d8:	463b      	mov	r3, r7
     6da:	4620      	mov	r0, r4
     6dc:	4629      	mov	r1, r5
     6de:	f7ff fd0f 	bl	100 <__aeabi_uldivmod>
	} while ((value != 0) && (bps < bp));
     6e2:	42bd      	cmp	r5, r7
     6e4:	bf08      	it	eq
     6e6:	42b4      	cmpeq	r4, r6
     6e8:	d318      	bcc.n	71c <encode_uint+0xa4>
     6ea:	45d0      	cmp	r8, sl
     6ec:	d916      	bls.n	71c <encode_uint+0xa4>
		value /= radix;
     6ee:	4604      	mov	r4, r0
     6f0:	460d      	mov	r5, r1
		unsigned int lsv = (unsigned int)(value % radix);
     6f2:	464e      	mov	r6, r9
     6f4:	2700      	movs	r7, #0
     6f6:	464a      	mov	r2, r9
     6f8:	463b      	mov	r3, r7
     6fa:	4620      	mov	r0, r4
     6fc:	4629      	mov	r1, r5
     6fe:	f7ff fcff 	bl	100 <__aeabi_uldivmod>
		*--bp = (lsv <= 9) ? ('0' + lsv)
     702:	2a09      	cmp	r2, #9
     704:	d9e2      	bls.n	6cc <encode_uint+0x54>
     706:	f1bb 0f01 	cmp.w	fp, #1
     70a:	d003      	beq.n	714 <encode_uint+0x9c>
			: upcase ? ('A' + lsv - 10) : ('a' + lsv - 10);
     70c:	b2d2      	uxtb	r2, r2
		*--bp = (lsv <= 9) ? ('0' + lsv)
     70e:	3257      	adds	r2, #87	; 0x57
     710:	b2d2      	uxtb	r2, r2
     712:	e7de      	b.n	6d2 <encode_uint+0x5a>
			: upcase ? ('A' + lsv - 10) : ('a' + lsv - 10);
     714:	b2d2      	uxtb	r2, r2
		*--bp = (lsv <= 9) ? ('0' + lsv)
     716:	3237      	adds	r2, #55	; 0x37
     718:	b2d2      	uxtb	r2, r2
     71a:	e7da      	b.n	6d2 <encode_uint+0x5a>

	/* Record required alternate forms.  This can be determined
	 * from the radix without re-checking specifier.
	 */
	if (conv->flag_hash) {
     71c:	9b01      	ldr	r3, [sp, #4]
     71e:	781b      	ldrb	r3, [r3, #0]
     720:	f013 0f20 	tst.w	r3, #32
     724:	d005      	beq.n	732 <encode_uint+0xba>
		if (radix == 8) {
     726:	f1b9 0f08 	cmp.w	r9, #8
     72a:	d006      	beq.n	73a <encode_uint+0xc2>
			conv->altform_0 = true;
		} else if (radix == 16) {
     72c:	f1b9 0f10 	cmp.w	r9, #16
     730:	d009      	beq.n	746 <encode_uint+0xce>
			;
		}
	}

	return bp;
}
     732:	4640      	mov	r0, r8
     734:	b003      	add	sp, #12
     736:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
			conv->altform_0 = true;
     73a:	9a01      	ldr	r2, [sp, #4]
     73c:	7893      	ldrb	r3, [r2, #2]
     73e:	f043 0308 	orr.w	r3, r3, #8
     742:	7093      	strb	r3, [r2, #2]
     744:	e7f5      	b.n	732 <encode_uint+0xba>
			conv->altform_0c = true;
     746:	9a01      	ldr	r2, [sp, #4]
     748:	7893      	ldrb	r3, [r2, #2]
     74a:	f043 0310 	orr.w	r3, r3, #16
     74e:	7093      	strb	r3, [r2, #2]
     750:	e7ef      	b.n	732 <encode_uint+0xba>
     752:	bf00      	nop
     754:	00008ea6 	.word	0x00008ea6

00000758 <cbvprintf>:

	return (int)count;
}

int cbvprintf(cbprintf_cb out, void *ctx, const char *fp, va_list ap)
{
     758:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     75c:	b093      	sub	sp, #76	; 0x4c
     75e:	4606      	mov	r6, r0
     760:	460d      	mov	r5, r1
     762:	4692      	mov	sl, r2
     764:	9303      	str	r3, [sp, #12]
	char buf[CONVERTED_BUFLEN];
	size_t count = 0;
     766:	2400      	movs	r4, #0
		return rc; \
	} \
	count += rc; \
} while (false)

	while (*fp != 0) {
     768:	f89a 0000 	ldrb.w	r0, [sl]
     76c:	2800      	cmp	r0, #0
     76e:	f000 84d6 	beq.w	111e <CONFIG_FPROTECT_BLOCK_SIZE+0x11e>
		if (*fp != '%') {
     772:	2825      	cmp	r0, #37	; 0x25
     774:	d008      	beq.n	788 <cbvprintf+0x30>
			OUTC(*fp++);
     776:	f10a 0a01 	add.w	sl, sl, #1
     77a:	4629      	mov	r1, r5
     77c:	47b0      	blx	r6
     77e:	2800      	cmp	r0, #0
     780:	f2c0 84ce 	blt.w	1120 <CONFIG_FPROTECT_BLOCK_SIZE+0x120>
     784:	3401      	adds	r4, #1
			continue;
     786:	e7ef      	b.n	768 <cbvprintf+0x10>
		 * mitigate LLVM code generation bug.
		 */
		struct {
			union argument_value value;
			struct conversion conv;
		} state = {
     788:	2300      	movs	r3, #0
     78a:	9306      	str	r3, [sp, #24]
     78c:	9307      	str	r3, [sp, #28]
     78e:	930b      	str	r3, [sp, #44]	; 0x2c
	*conv = (struct conversion) {
     790:	9308      	str	r3, [sp, #32]
     792:	9309      	str	r3, [sp, #36]	; 0x24
     794:	930a      	str	r3, [sp, #40]	; 0x28
	++sp;
     796:	f10a 0801 	add.w	r8, sl, #1
	if (*sp == '%') {
     79a:	f89a 3001 	ldrb.w	r3, [sl, #1]
     79e:	2b25      	cmp	r3, #37	; 0x25
     7a0:	d001      	beq.n	7a6 <cbvprintf+0x4e>
	bool loop = true;
     7a2:	2701      	movs	r7, #1
     7a4:	e02c      	b.n	800 <CONFIG_ISR_STACK_SIZE>
		conv->specifier = *sp++;
     7a6:	f10a 0802 	add.w	r8, sl, #2
     7aa:	f88d 3023 	strb.w	r3, [sp, #35]	; 0x23
		return sp;
     7ae:	e1a8      	b.n	b02 <CONFIG_ISR_STACK_SIZE+0x302>
			conv->flag_dash = true;
     7b0:	f89d 3020 	ldrb.w	r3, [sp, #32]
     7b4:	f043 0304 	orr.w	r3, r3, #4
     7b8:	f88d 3020 	strb.w	r3, [sp, #32]
		if (loop) {
     7bc:	b1ff      	cbz	r7, 7fe <cbvprintf+0xa6>
			++sp;
     7be:	f108 0801 	add.w	r8, r8, #1
     7c2:	e01c      	b.n	7fe <cbvprintf+0xa6>
			conv->flag_plus = true;
     7c4:	f89d 3020 	ldrb.w	r3, [sp, #32]
     7c8:	f043 0308 	orr.w	r3, r3, #8
     7cc:	f88d 3020 	strb.w	r3, [sp, #32]
			break;
     7d0:	e7f4      	b.n	7bc <cbvprintf+0x64>
			conv->flag_space = true;
     7d2:	f89d 3020 	ldrb.w	r3, [sp, #32]
     7d6:	f043 0310 	orr.w	r3, r3, #16
     7da:	f88d 3020 	strb.w	r3, [sp, #32]
			break;
     7de:	e7ed      	b.n	7bc <cbvprintf+0x64>
			conv->flag_hash = true;
     7e0:	f89d 3020 	ldrb.w	r3, [sp, #32]
     7e4:	f043 0320 	orr.w	r3, r3, #32
     7e8:	f88d 3020 	strb.w	r3, [sp, #32]
			break;
     7ec:	e7e6      	b.n	7bc <cbvprintf+0x64>
			conv->flag_zero = true;
     7ee:	f89d 3020 	ldrb.w	r3, [sp, #32]
     7f2:	f043 0340 	orr.w	r3, r3, #64	; 0x40
     7f6:	f88d 3020 	strb.w	r3, [sp, #32]
			break;
     7fa:	e7df      	b.n	7bc <cbvprintf+0x64>
		switch (*sp) {
     7fc:	2700      	movs	r7, #0
	} while (loop);
     7fe:	b34f      	cbz	r7, 854 <CONFIG_ISR_STACK_SIZE+0x54>
		switch (*sp) {
     800:	f898 3000 	ldrb.w	r3, [r8]
     804:	3b20      	subs	r3, #32
     806:	2b10      	cmp	r3, #16
     808:	d8f8      	bhi.n	7fc <cbvprintf+0xa4>
     80a:	a201      	add	r2, pc, #4	; (adr r2, 810 <CONFIG_ISR_STACK_SIZE+0x10>)
     80c:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
     810:	000007d3 	.word	0x000007d3
     814:	000007fd 	.word	0x000007fd
     818:	000007fd 	.word	0x000007fd
     81c:	000007e1 	.word	0x000007e1
     820:	000007fd 	.word	0x000007fd
     824:	000007fd 	.word	0x000007fd
     828:	000007fd 	.word	0x000007fd
     82c:	000007fd 	.word	0x000007fd
     830:	000007fd 	.word	0x000007fd
     834:	000007fd 	.word	0x000007fd
     838:	000007fd 	.word	0x000007fd
     83c:	000007c5 	.word	0x000007c5
     840:	000007fd 	.word	0x000007fd
     844:	000007b1 	.word	0x000007b1
     848:	000007fd 	.word	0x000007fd
     84c:	000007fd 	.word	0x000007fd
     850:	000007ef 	.word	0x000007ef
	if (conv->flag_zero && conv->flag_dash) {
     854:	f89d 3020 	ldrb.w	r3, [sp, #32]
     858:	f003 0344 	and.w	r3, r3, #68	; 0x44
     85c:	2b44      	cmp	r3, #68	; 0x44
     85e:	d06d      	beq.n	93c <CONFIG_ISR_STACK_SIZE+0x13c>
	sp = extract_width(conv, sp);
     860:	f8cd 8014 	str.w	r8, [sp, #20]
	conv->width_present = true;
     864:	f89d 3020 	ldrb.w	r3, [sp, #32]
     868:	f043 0380 	orr.w	r3, r3, #128	; 0x80
     86c:	f88d 3020 	strb.w	r3, [sp, #32]
	if (*sp == '*') {
     870:	f898 3000 	ldrb.w	r3, [r8]
     874:	2b2a      	cmp	r3, #42	; 0x2a
     876:	d068      	beq.n	94a <CONFIG_ISR_STACK_SIZE+0x14a>
	size_t width = extract_decimal(&sp);
     878:	a805      	add	r0, sp, #20
     87a:	f7ff fee7 	bl	64c <extract_decimal>
	if (sp != wp) {
     87e:	9b05      	ldr	r3, [sp, #20]
     880:	4598      	cmp	r8, r3
     882:	d012      	beq.n	8aa <CONFIG_ISR_STACK_SIZE+0xaa>
		conv->width_present = true;
     884:	f89d 3020 	ldrb.w	r3, [sp, #32]
     888:	f043 0380 	orr.w	r3, r3, #128	; 0x80
     88c:	f88d 3020 	strb.w	r3, [sp, #32]
		conv->width_value = width;
     890:	9009      	str	r0, [sp, #36]	; 0x24
		conv->unsupported |= ((conv->width_value < 0)
     892:	f3c3 0340 	ubfx	r3, r3, #1, #1
				      || (width != (size_t)conv->width_value));
     896:	2800      	cmp	r0, #0
     898:	db60      	blt.n	95c <CONFIG_ISR_STACK_SIZE+0x15c>
     89a:	2200      	movs	r2, #0
		conv->unsupported |= ((conv->width_value < 0)
     89c:	4313      	orrs	r3, r2
     89e:	f89d 2020 	ldrb.w	r2, [sp, #32]
     8a2:	f363 0241 	bfi	r2, r3, #1, #1
     8a6:	f88d 2020 	strb.w	r2, [sp, #32]
	return sp;
     8aa:	9b05      	ldr	r3, [sp, #20]
	sp = extract_prec(conv, sp);
     8ac:	9305      	str	r3, [sp, #20]
	conv->prec_present = (*sp == '.');
     8ae:	781b      	ldrb	r3, [r3, #0]
     8b0:	2b2e      	cmp	r3, #46	; 0x2e
     8b2:	bf14      	ite	ne
     8b4:	2300      	movne	r3, #0
     8b6:	2301      	moveq	r3, #1
     8b8:	f89d 2021 	ldrb.w	r2, [sp, #33]	; 0x21
     8bc:	f363 0241 	bfi	r2, r3, #1, #1
     8c0:	f88d 2021 	strb.w	r2, [sp, #33]	; 0x21
	if (!conv->prec_present) {
     8c4:	2b00      	cmp	r3, #0
     8c6:	d04b      	beq.n	960 <CONFIG_ISR_STACK_SIZE+0x160>
	++sp;
     8c8:	9b05      	ldr	r3, [sp, #20]
     8ca:	1c5a      	adds	r2, r3, #1
     8cc:	9205      	str	r2, [sp, #20]
	if (*sp == '*') {
     8ce:	785b      	ldrb	r3, [r3, #1]
     8d0:	2b2a      	cmp	r3, #42	; 0x2a
     8d2:	d048      	beq.n	966 <CONFIG_ISR_STACK_SIZE+0x166>
	size_t prec = extract_decimal(&sp);
     8d4:	a805      	add	r0, sp, #20
     8d6:	f7ff feb9 	bl	64c <extract_decimal>
	conv->prec_value = prec;
     8da:	900a      	str	r0, [sp, #40]	; 0x28
	conv->unsupported |= ((conv->prec_value < 0)
     8dc:	f89d 3020 	ldrb.w	r3, [sp, #32]
     8e0:	f3c3 0340 	ubfx	r3, r3, #1, #1
			      || (prec != (size_t)conv->prec_value));
     8e4:	2800      	cmp	r0, #0
     8e6:	db47      	blt.n	978 <CONFIG_ISR_STACK_SIZE+0x178>
     8e8:	2200      	movs	r2, #0
	conv->unsupported |= ((conv->prec_value < 0)
     8ea:	4313      	orrs	r3, r2
     8ec:	f89d 2020 	ldrb.w	r2, [sp, #32]
     8f0:	f363 0241 	bfi	r2, r3, #1, #1
     8f4:	f88d 2020 	strb.w	r2, [sp, #32]
	return sp;
     8f8:	f8dd 8014 	ldr.w	r8, [sp, #20]
	switch (*sp) {
     8fc:	f898 3000 	ldrb.w	r3, [r8]
     900:	3b4c      	subs	r3, #76	; 0x4c
     902:	2b2e      	cmp	r3, #46	; 0x2e
     904:	f200 80dc 	bhi.w	ac0 <CONFIG_ISR_STACK_SIZE+0x2c0>
     908:	e8df f003 	tbb	[pc, r3]
     90c:	dadadaca 	.word	0xdadadaca
     910:	dadadada 	.word	0xdadadada
     914:	dadadada 	.word	0xdadadada
     918:	dadadada 	.word	0xdadadada
     91c:	dadadada 	.word	0xdadadada
     920:	dadadada 	.word	0xdadadada
     924:	dadadada 	.word	0xdadadada
     928:	da6ada38 	.word	0xda6ada38
     92c:	dadada51 	.word	0xdadada51
     930:	dadadada 	.word	0xdadadada
     934:	dadadac0 	.word	0xdadadac0
     938:	dada      	.short	0xdada
     93a:	b6          	.byte	0xb6
     93b:	00          	.byte	0x00
		conv->flag_zero = false;
     93c:	f89d 3020 	ldrb.w	r3, [sp, #32]
     940:	f36f 1386 	bfc	r3, #6, #1
     944:	f88d 3020 	strb.w	r3, [sp, #32]
     948:	e78a      	b.n	860 <CONFIG_ISR_STACK_SIZE+0x60>
		conv->width_star = true;
     94a:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     94e:	f043 0301 	orr.w	r3, r3, #1
     952:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
		return ++sp;
     956:	4643      	mov	r3, r8
     958:	3301      	adds	r3, #1
     95a:	e7a7      	b.n	8ac <CONFIG_ISR_STACK_SIZE+0xac>
				      || (width != (size_t)conv->width_value));
     95c:	2201      	movs	r2, #1
     95e:	e79d      	b.n	89c <CONFIG_ISR_STACK_SIZE+0x9c>
		return sp;
     960:	f8dd 8014 	ldr.w	r8, [sp, #20]
     964:	e7ca      	b.n	8fc <CONFIG_ISR_STACK_SIZE+0xfc>
		conv->prec_star = true;
     966:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     96a:	f043 0304 	orr.w	r3, r3, #4
     96e:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
		return ++sp;
     972:	f102 0801 	add.w	r8, r2, #1
     976:	e7c1      	b.n	8fc <CONFIG_ISR_STACK_SIZE+0xfc>
			      || (prec != (size_t)conv->prec_value));
     978:	2201      	movs	r2, #1
     97a:	e7b6      	b.n	8ea <CONFIG_ISR_STACK_SIZE+0xea>
		if (*++sp == 'h') {
     97c:	f108 0201 	add.w	r2, r8, #1
     980:	f898 3001 	ldrb.w	r3, [r8, #1]
     984:	2b68      	cmp	r3, #104	; 0x68
     986:	d008      	beq.n	99a <CONFIG_ISR_STACK_SIZE+0x19a>
			conv->length_mod = LENGTH_H;
     988:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     98c:	2102      	movs	r1, #2
     98e:	f361 03c6 	bfi	r3, r1, #3, #4
     992:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
		if (*++sp == 'h') {
     996:	4690      	mov	r8, r2
     998:	e02b      	b.n	9f2 <CONFIG_ISR_STACK_SIZE+0x1f2>
			conv->length_mod = LENGTH_HH;
     99a:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     99e:	2201      	movs	r2, #1
     9a0:	f362 03c6 	bfi	r3, r2, #3, #4
     9a4:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
			++sp;
     9a8:	f108 0802 	add.w	r8, r8, #2
     9ac:	e021      	b.n	9f2 <CONFIG_ISR_STACK_SIZE+0x1f2>
		if (*++sp == 'l') {
     9ae:	f108 0201 	add.w	r2, r8, #1
     9b2:	f898 3001 	ldrb.w	r3, [r8, #1]
     9b6:	2b6c      	cmp	r3, #108	; 0x6c
     9b8:	d008      	beq.n	9cc <CONFIG_ISR_STACK_SIZE+0x1cc>
			conv->length_mod = LENGTH_L;
     9ba:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     9be:	2103      	movs	r1, #3
     9c0:	f361 03c6 	bfi	r3, r1, #3, #4
     9c4:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
		if (*++sp == 'l') {
     9c8:	4690      	mov	r8, r2
     9ca:	e012      	b.n	9f2 <CONFIG_ISR_STACK_SIZE+0x1f2>
			conv->length_mod = LENGTH_LL;
     9cc:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     9d0:	2204      	movs	r2, #4
     9d2:	f362 03c6 	bfi	r3, r2, #3, #4
     9d6:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
			++sp;
     9da:	f108 0802 	add.w	r8, r8, #2
     9de:	e008      	b.n	9f2 <CONFIG_ISR_STACK_SIZE+0x1f2>
		conv->length_mod = LENGTH_J;
     9e0:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     9e4:	2205      	movs	r2, #5
     9e6:	f362 03c6 	bfi	r3, r2, #3, #4
     9ea:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
		++sp;
     9ee:	f108 0801 	add.w	r8, r8, #1
	conv->specifier = *sp++;
     9f2:	f818 3b01 	ldrb.w	r3, [r8], #1
     9f6:	f88d 3023 	strb.w	r3, [sp, #35]	; 0x23
	switch (conv->specifier) {
     9fa:	f1a3 0241 	sub.w	r2, r3, #65	; 0x41
     9fe:	2a37      	cmp	r2, #55	; 0x37
     a00:	f200 8150 	bhi.w	ca4 <CONFIG_ISR_STACK_SIZE+0x4a4>
     a04:	e8df f012 	tbh	[pc, r2, lsl #1]
     a08:	014e0126 	.word	0x014e0126
     a0c:	014e014e 	.word	0x014e014e
     a10:	01260126 	.word	0x01260126
     a14:	014e0126 	.word	0x014e0126
     a18:	014e014e 	.word	0x014e014e
     a1c:	014e014e 	.word	0x014e014e
     a20:	014e014e 	.word	0x014e014e
     a24:	014e014e 	.word	0x014e014e
     a28:	014e014e 	.word	0x014e014e
     a2c:	014e014e 	.word	0x014e014e
     a30:	014e014e 	.word	0x014e014e
     a34:	0113014e 	.word	0x0113014e
     a38:	014e014e 	.word	0x014e014e
     a3c:	014e014e 	.word	0x014e014e
     a40:	014e014e 	.word	0x014e014e
     a44:	014e014e 	.word	0x014e014e
     a48:	014e0126 	.word	0x014e0126
     a4c:	00630113 	.word	0x00630113
     a50:	01260126 	.word	0x01260126
     a54:	014e0126 	.word	0x014e0126
     a58:	014e0063 	.word	0x014e0063
     a5c:	014e014e 	.word	0x014e014e
     a60:	012f014e 	.word	0x012f014e
     a64:	013f0113 	.word	0x013f0113
     a68:	014e014e 	.word	0x014e014e
     a6c:	014e013f 	.word	0x014e013f
     a70:	014e0113 	.word	0x014e0113
     a74:	0113014e 	.word	0x0113014e
		conv->length_mod = LENGTH_Z;
     a78:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     a7c:	2206      	movs	r2, #6
     a7e:	f362 03c6 	bfi	r3, r2, #3, #4
     a82:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
		++sp;
     a86:	f108 0801 	add.w	r8, r8, #1
		break;
     a8a:	e7b2      	b.n	9f2 <CONFIG_ISR_STACK_SIZE+0x1f2>
		conv->length_mod = LENGTH_T;
     a8c:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     a90:	2207      	movs	r2, #7
     a92:	f362 03c6 	bfi	r3, r2, #3, #4
     a96:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
		++sp;
     a9a:	f108 0801 	add.w	r8, r8, #1
		break;
     a9e:	e7a8      	b.n	9f2 <CONFIG_ISR_STACK_SIZE+0x1f2>
		conv->length_mod = LENGTH_UPPER_L;
     aa0:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     aa4:	2208      	movs	r2, #8
     aa6:	f362 03c6 	bfi	r3, r2, #3, #4
     aaa:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
		++sp;
     aae:	f108 0801 	add.w	r8, r8, #1
		conv->unsupported = true;
     ab2:	f89d 3020 	ldrb.w	r3, [sp, #32]
     ab6:	f043 0302 	orr.w	r3, r3, #2
     aba:	f88d 3020 	strb.w	r3, [sp, #32]
		break;
     abe:	e798      	b.n	9f2 <CONFIG_ISR_STACK_SIZE+0x1f2>
		conv->length_mod = LENGTH_NONE;
     ac0:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     ac4:	f36f 03c6 	bfc	r3, #3, #4
     ac8:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
		break;
     acc:	e791      	b.n	9f2 <CONFIG_ISR_STACK_SIZE+0x1f2>
		conv->specifier_cat = SPECIFIER_SINT;
     ace:	f89d 2022 	ldrb.w	r2, [sp, #34]	; 0x22
     ad2:	2101      	movs	r1, #1
     ad4:	f361 0202 	bfi	r2, r1, #0, #3
     ad8:	f88d 2022 	strb.w	r2, [sp, #34]	; 0x22
		if (conv->length_mod == LENGTH_UPPER_L) {
     adc:	f89d 2021 	ldrb.w	r2, [sp, #33]	; 0x21
     ae0:	f002 0278 	and.w	r2, r2, #120	; 0x78
     ae4:	2a40      	cmp	r2, #64	; 0x40
     ae6:	f000 80aa 	beq.w	c3e <CONFIG_ISR_STACK_SIZE+0x43e>
		if (conv->specifier == 'c') {
     aea:	2b63      	cmp	r3, #99	; 0x63
     aec:	f000 80ae 	beq.w	c4c <CONFIG_ISR_STACK_SIZE+0x44c>
	conv->unsupported |= unsupported;
     af0:	f89d 3020 	ldrb.w	r3, [sp, #32]
     af4:	f3c3 0240 	ubfx	r2, r3, #1, #1
     af8:	4317      	orrs	r7, r2
     afa:	f367 0341 	bfi	r3, r7, #1, #1
     afe:	f88d 3020 	strb.w	r3, [sp, #32]
		fp = extract_conversion(conv, sp);

		/* If dynamic width is specified, process it,
		 * otherwise set width if present.
		 */
		if (conv->width_star) {
     b02:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     b06:	f013 0f01 	tst.w	r3, #1
     b0a:	f000 80da 	beq.w	cc2 <CONFIG_ISR_STACK_SIZE+0x4c2>
			width = va_arg(ap, int);
     b0e:	9b03      	ldr	r3, [sp, #12]
     b10:	1d1a      	adds	r2, r3, #4
     b12:	9203      	str	r2, [sp, #12]
     b14:	681f      	ldr	r7, [r3, #0]

			if (width < 0) {
     b16:	2f00      	cmp	r7, #0
     b18:	f2c0 80cb 	blt.w	cb2 <CONFIG_ISR_STACK_SIZE+0x4b2>

		/* If dynamic precision is specified, process it, otherwise
		 * set precision if present.  For floating point where
		 * precision is not present use 6.
		 */
		if (conv->prec_star) {
     b1c:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     b20:	f013 0f04 	tst.w	r3, #4
     b24:	f000 80df 	beq.w	ce6 <CONFIG_ISR_STACK_SIZE+0x4e6>
			int arg = va_arg(ap, int);
     b28:	9b03      	ldr	r3, [sp, #12]
     b2a:	1d1a      	adds	r2, r3, #4
     b2c:	9203      	str	r2, [sp, #12]
     b2e:	f8d3 b000 	ldr.w	fp, [r3]

			if (arg < 0) {
     b32:	f1bb 0f00 	cmp.w	fp, #0
     b36:	f2c0 80cd 	blt.w	cd4 <CONFIG_ISR_STACK_SIZE+0x4d4>
		}

		/* Reuse width and precision memory in conv for value
		 * padding counts.
		 */
		conv->pad0_value = 0;
     b3a:	2300      	movs	r3, #0
     b3c:	9309      	str	r3, [sp, #36]	; 0x24
		conv->pad0_pre_exp = 0;
     b3e:	930a      	str	r3, [sp, #40]	; 0x28
		 * This can't be extracted to a helper function because
		 * passing a pointer to va_list doesn't work on x86_64.  See
		 * https://stackoverflow.com/a/8048892.
		 */
		enum specifier_cat_enum specifier_cat
			= (enum specifier_cat_enum)conv->specifier_cat;
     b40:	f89d 3022 	ldrb.w	r3, [sp, #34]	; 0x22
     b44:	f003 0307 	and.w	r3, r3, #7
		enum length_mod_enum length_mod
			= (enum length_mod_enum)conv->length_mod;
     b48:	f89d 1021 	ldrb.w	r1, [sp, #33]	; 0x21
     b4c:	f3c1 01c3 	ubfx	r1, r1, #3, #4
		/* Extract the value based on the argument category and length.
		 *
		 * Note that the length modifier doesn't affect the value of a
		 * pointer argument.
		 */
		if (specifier_cat == SPECIFIER_SINT) {
     b50:	2b01      	cmp	r3, #1
     b52:	f000 80d1 	beq.w	cf8 <CONFIG_ISR_STACK_SIZE+0x4f8>
			if (length_mod == LENGTH_HH) {
				value->sint = (char)value->sint;
			} else if (length_mod == LENGTH_H) {
				value->sint = (short)value->sint;
			}
		} else if (specifier_cat == SPECIFIER_UINT) {
     b56:	2b02      	cmp	r3, #2
     b58:	f000 8116 	beq.w	d88 <CONFIG_ISR_STACK_SIZE+0x588>
			if (length_mod == LENGTH_HH) {
				value->uint = (unsigned char)value->uint;
			} else if (length_mod == LENGTH_H) {
				value->uint = (unsigned short)value->uint;
			}
		} else if (specifier_cat == SPECIFIER_FP) {
     b5c:	2b04      	cmp	r3, #4
     b5e:	f000 8167 	beq.w	e30 <CONFIG_ISR_STACK_SIZE+0x630>
			if (length_mod == LENGTH_UPPER_L) {
				value->ldbl = va_arg(ap, long double);
			} else {
				value->dbl = va_arg(ap, double);
			}
		} else if (specifier_cat == SPECIFIER_PTR) {
     b62:	2b03      	cmp	r3, #3
     b64:	f000 817e 	beq.w	e64 <CONFIG_ISR_STACK_SIZE+0x664>
		/* We've now consumed all arguments related to this
		 * specification.  If the conversion is invalid, or is
		 * something we don't support, then output the original
		 * specification and move on.
		 */
		if (conv->invalid || conv->unsupported) {
     b68:	f89d 9020 	ldrb.w	r9, [sp, #32]
     b6c:	f019 0303 	ands.w	r3, r9, #3
     b70:	9302      	str	r3, [sp, #8]
     b72:	f040 817d 	bne.w	e70 <CONFIG_ISR_STACK_SIZE+0x670>
		}

		/* Do formatting, either into the buffer or
		 * referencing external data.
		 */
		switch (conv->specifier) {
     b76:	f89d 3023 	ldrb.w	r3, [sp, #35]	; 0x23
     b7a:	3b25      	subs	r3, #37	; 0x25
     b7c:	2b53      	cmp	r3, #83	; 0x53
     b7e:	f200 8233 	bhi.w	fe8 <CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD+0x48>
     b82:	e8df f013 	tbh	[pc, r3, lsl #1]
     b86:	0181      	.short	0x0181
     b88:	02310231 	.word	0x02310231
     b8c:	02310231 	.word	0x02310231
     b90:	02310231 	.word	0x02310231
     b94:	02310231 	.word	0x02310231
     b98:	02310231 	.word	0x02310231
     b9c:	02310231 	.word	0x02310231
     ba0:	02310231 	.word	0x02310231
     ba4:	02310231 	.word	0x02310231
     ba8:	02310231 	.word	0x02310231
     bac:	02310231 	.word	0x02310231
     bb0:	02310231 	.word	0x02310231
     bb4:	02310231 	.word	0x02310231
     bb8:	02310231 	.word	0x02310231
     bbc:	02310231 	.word	0x02310231
     bc0:	02310231 	.word	0x02310231
     bc4:	02310231 	.word	0x02310231
     bc8:	02310231 	.word	0x02310231
     bcc:	02310231 	.word	0x02310231
     bd0:	02310231 	.word	0x02310231
     bd4:	02310231 	.word	0x02310231
     bd8:	02310231 	.word	0x02310231
     bdc:	02310231 	.word	0x02310231
     be0:	02310231 	.word	0x02310231
     be4:	02310231 	.word	0x02310231
     be8:	02310231 	.word	0x02310231
     bec:	023101c7 	.word	0x023101c7
     bf0:	02310231 	.word	0x02310231
     bf4:	02310231 	.word	0x02310231
     bf8:	02310231 	.word	0x02310231
     bfc:	02310231 	.word	0x02310231
     c00:	01a10231 	.word	0x01a10231
     c04:	023101ab 	.word	0x023101ab
     c08:	02310231 	.word	0x02310231
     c0c:	01ab0231 	.word	0x01ab0231
     c10:	02310231 	.word	0x02310231
     c14:	02310231 	.word	0x02310231
     c18:	01c70208 	.word	0x01c70208
     c1c:	023101ea 	.word	0x023101ea
     c20:	018f0231 	.word	0x018f0231
     c24:	01c70231 	.word	0x01c70231
     c28:	02310231 	.word	0x02310231
     c2c:	01c7      	.short	0x01c7
		conv->specifier_cat = SPECIFIER_UINT;
     c2e:	f89d 2022 	ldrb.w	r2, [sp, #34]	; 0x22
     c32:	2102      	movs	r1, #2
     c34:	f361 0202 	bfi	r2, r1, #0, #3
     c38:	f88d 2022 	strb.w	r2, [sp, #34]	; 0x22
     c3c:	e74e      	b.n	adc <CONFIG_ISR_STACK_SIZE+0x2dc>
			conv->invalid = true;
     c3e:	f89d 1020 	ldrb.w	r1, [sp, #32]
     c42:	f041 0101 	orr.w	r1, r1, #1
     c46:	f88d 1020 	strb.w	r1, [sp, #32]
     c4a:	e74e      	b.n	aea <CONFIG_ISR_STACK_SIZE+0x2ea>
			unsupported = (conv->length_mod != LENGTH_NONE);
     c4c:	1e17      	subs	r7, r2, #0
     c4e:	bf18      	it	ne
     c50:	2701      	movne	r7, #1
     c52:	e74d      	b.n	af0 <CONFIG_ISR_STACK_SIZE+0x2f0>
		conv->specifier_cat = SPECIFIER_FP;
     c54:	f89d 3022 	ldrb.w	r3, [sp, #34]	; 0x22
     c58:	2204      	movs	r2, #4
     c5a:	f362 0302 	bfi	r3, r2, #0, #3
     c5e:	f88d 3022 	strb.w	r3, [sp, #34]	; 0x22
			unsupported = true;
     c62:	2701      	movs	r7, #1
			break;
     c64:	e744      	b.n	af0 <CONFIG_ISR_STACK_SIZE+0x2f0>
		conv->specifier_cat = SPECIFIER_PTR;
     c66:	f89d 3022 	ldrb.w	r3, [sp, #34]	; 0x22
     c6a:	2203      	movs	r2, #3
     c6c:	f362 0302 	bfi	r3, r2, #0, #3
     c70:	f88d 3022 	strb.w	r3, [sp, #34]	; 0x22
		if (conv->length_mod == LENGTH_UPPER_L) {
     c74:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     c78:	f003 0378 	and.w	r3, r3, #120	; 0x78
     c7c:	2b40      	cmp	r3, #64	; 0x40
     c7e:	f47f af37 	bne.w	af0 <CONFIG_ISR_STACK_SIZE+0x2f0>
			unsupported = true;
     c82:	2701      	movs	r7, #1
     c84:	e734      	b.n	af0 <CONFIG_ISR_STACK_SIZE+0x2f0>
		conv->specifier_cat = SPECIFIER_PTR;
     c86:	f89d 3022 	ldrb.w	r3, [sp, #34]	; 0x22
     c8a:	2203      	movs	r2, #3
     c8c:	f362 0302 	bfi	r3, r2, #0, #3
     c90:	f88d 3022 	strb.w	r3, [sp, #34]	; 0x22
		if (conv->length_mod != LENGTH_NONE) {
     c94:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     c98:	f013 0f78 	tst.w	r3, #120	; 0x78
     c9c:	f43f af28 	beq.w	af0 <CONFIG_ISR_STACK_SIZE+0x2f0>
			unsupported = true;
     ca0:	2701      	movs	r7, #1
     ca2:	e725      	b.n	af0 <CONFIG_ISR_STACK_SIZE+0x2f0>
		conv->invalid = true;
     ca4:	f89d 3020 	ldrb.w	r3, [sp, #32]
     ca8:	f043 0301 	orr.w	r3, r3, #1
     cac:	f88d 3020 	strb.w	r3, [sp, #32]
		break;
     cb0:	e71e      	b.n	af0 <CONFIG_ISR_STACK_SIZE+0x2f0>
				conv->flag_dash = true;
     cb2:	f89d 3020 	ldrb.w	r3, [sp, #32]
     cb6:	f043 0304 	orr.w	r3, r3, #4
     cba:	f88d 3020 	strb.w	r3, [sp, #32]
				width = -width;
     cbe:	427f      	negs	r7, r7
     cc0:	e72c      	b.n	b1c <CONFIG_ISR_STACK_SIZE+0x31c>
		} else if (conv->width_present) {
     cc2:	f99d 3020 	ldrsb.w	r3, [sp, #32]
     cc6:	2b00      	cmp	r3, #0
     cc8:	db02      	blt.n	cd0 <CONFIG_ISR_STACK_SIZE+0x4d0>
		int width = -1;
     cca:	f04f 37ff 	mov.w	r7, #4294967295
     cce:	e725      	b.n	b1c <CONFIG_ISR_STACK_SIZE+0x31c>
			width = conv->width_value;
     cd0:	9f09      	ldr	r7, [sp, #36]	; 0x24
     cd2:	e723      	b.n	b1c <CONFIG_ISR_STACK_SIZE+0x31c>
				conv->prec_present = false;
     cd4:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     cd8:	f36f 0341 	bfc	r3, #1, #1
     cdc:	f88d 3021 	strb.w	r3, [sp, #33]	; 0x21
		int precision = -1;
     ce0:	f04f 3bff 	mov.w	fp, #4294967295
     ce4:	e729      	b.n	b3a <CONFIG_ISR_STACK_SIZE+0x33a>
		} else if (conv->prec_present) {
     ce6:	f013 0f02 	tst.w	r3, #2
     cea:	d002      	beq.n	cf2 <CONFIG_ISR_STACK_SIZE+0x4f2>
			precision = conv->prec_value;
     cec:	f8dd b028 	ldr.w	fp, [sp, #40]	; 0x28
     cf0:	e723      	b.n	b3a <CONFIG_ISR_STACK_SIZE+0x33a>
		int precision = -1;
     cf2:	f04f 3bff 	mov.w	fp, #4294967295
     cf6:	e720      	b.n	b3a <CONFIG_ISR_STACK_SIZE+0x33a>
			switch (length_mod) {
     cf8:	1ecb      	subs	r3, r1, #3
     cfa:	2b04      	cmp	r3, #4
     cfc:	d804      	bhi.n	d08 <CONFIG_ISR_STACK_SIZE+0x508>
     cfe:	e8df f003 	tbb	[pc, r3]
     d02:	1d0b      	.short	0x1d0b
     d04:	3529      	.short	0x3529
     d06:	35          	.byte	0x35
     d07:	00          	.byte	0x00
				value->sint = va_arg(ap, int);
     d08:	9b03      	ldr	r3, [sp, #12]
     d0a:	1d1a      	adds	r2, r3, #4
     d0c:	9203      	str	r2, [sp, #12]
     d0e:	681a      	ldr	r2, [r3, #0]
     d10:	17d3      	asrs	r3, r2, #31
     d12:	e9cd 2306 	strd	r2, r3, [sp, #24]
				break;
     d16:	e006      	b.n	d26 <CONFIG_ISR_STACK_SIZE+0x526>
					value->sint = va_arg(ap, long);
     d18:	9b03      	ldr	r3, [sp, #12]
     d1a:	1d1a      	adds	r2, r3, #4
     d1c:	9203      	str	r2, [sp, #12]
     d1e:	681a      	ldr	r2, [r3, #0]
     d20:	17d3      	asrs	r3, r2, #31
     d22:	e9cd 2306 	strd	r2, r3, [sp, #24]
			if (length_mod == LENGTH_HH) {
     d26:	2901      	cmp	r1, #1
     d28:	d028      	beq.n	d7c <CONFIG_ISR_STACK_SIZE+0x57c>
			} else if (length_mod == LENGTH_H) {
     d2a:	2902      	cmp	r1, #2
     d2c:	f47f af1c 	bne.w	b68 <CONFIG_ISR_STACK_SIZE+0x368>
				value->sint = (short)value->sint;
     d30:	f9bd 2018 	ldrsh.w	r2, [sp, #24]
     d34:	17d3      	asrs	r3, r2, #31
     d36:	e9cd 2306 	strd	r2, r3, [sp, #24]
     d3a:	e715      	b.n	b68 <CONFIG_ISR_STACK_SIZE+0x368>
					(sint_value_type)va_arg(ap, long long);
     d3c:	9b03      	ldr	r3, [sp, #12]
     d3e:	3307      	adds	r3, #7
     d40:	f023 0307 	bic.w	r3, r3, #7
     d44:	f103 0208 	add.w	r2, r3, #8
     d48:	9203      	str	r2, [sp, #12]
     d4a:	e9d3 2300 	ldrd	r2, r3, [r3]
				value->sint =
     d4e:	e9cd 2306 	strd	r2, r3, [sp, #24]
				break;
     d52:	e7e8      	b.n	d26 <CONFIG_ISR_STACK_SIZE+0x526>
					(sint_value_type)va_arg(ap, intmax_t);
     d54:	9b03      	ldr	r3, [sp, #12]
     d56:	3307      	adds	r3, #7
     d58:	f023 0307 	bic.w	r3, r3, #7
     d5c:	f103 0208 	add.w	r2, r3, #8
     d60:	9203      	str	r2, [sp, #12]
     d62:	e9d3 2300 	ldrd	r2, r3, [r3]
				value->sint =
     d66:	e9cd 2306 	strd	r2, r3, [sp, #24]
				break;
     d6a:	e7dc      	b.n	d26 <CONFIG_ISR_STACK_SIZE+0x526>
					(sint_value_type)va_arg(ap, ptrdiff_t);
     d6c:	9b03      	ldr	r3, [sp, #12]
     d6e:	1d1a      	adds	r2, r3, #4
     d70:	9203      	str	r2, [sp, #12]
     d72:	681a      	ldr	r2, [r3, #0]
     d74:	17d3      	asrs	r3, r2, #31
				value->sint =
     d76:	e9cd 2306 	strd	r2, r3, [sp, #24]
				break;
     d7a:	e7d4      	b.n	d26 <CONFIG_ISR_STACK_SIZE+0x526>
				value->sint = (char)value->sint;
     d7c:	f89d 3018 	ldrb.w	r3, [sp, #24]
     d80:	9306      	str	r3, [sp, #24]
     d82:	2300      	movs	r3, #0
     d84:	9307      	str	r3, [sp, #28]
     d86:	e6ef      	b.n	b68 <CONFIG_ISR_STACK_SIZE+0x368>
			switch (length_mod) {
     d88:	1ecb      	subs	r3, r1, #3
     d8a:	2b04      	cmp	r3, #4
     d8c:	d804      	bhi.n	d98 <CONFIG_ISR_STACK_SIZE+0x598>
     d8e:	e8df f003 	tbb	[pc, r3]
     d92:	1f0b      	.short	0x1f0b
     d94:	4135      	.short	0x4135
     d96:	41          	.byte	0x41
     d97:	00          	.byte	0x00
				value->uint = va_arg(ap, unsigned int);
     d98:	9b03      	ldr	r3, [sp, #12]
     d9a:	1d1a      	adds	r2, r3, #4
     d9c:	9203      	str	r2, [sp, #12]
     d9e:	681b      	ldr	r3, [r3, #0]
     da0:	9306      	str	r3, [sp, #24]
     da2:	2300      	movs	r3, #0
     da4:	9307      	str	r3, [sp, #28]
				break;
     da6:	e01e      	b.n	de6 <CONFIG_ISR_STACK_SIZE+0x5e6>
				    && (conv->specifier == 'c')) {
     da8:	f89d 3023 	ldrb.w	r3, [sp, #35]	; 0x23
				if ((!WCHAR_IS_SIGNED)
     dac:	2b63      	cmp	r3, #99	; 0x63
     dae:	d007      	beq.n	dc0 <CONFIG_ISR_STACK_SIZE+0x5c0>
					value->uint = va_arg(ap, unsigned long);
     db0:	9b03      	ldr	r3, [sp, #12]
     db2:	1d1a      	adds	r2, r3, #4
     db4:	9203      	str	r2, [sp, #12]
     db6:	681b      	ldr	r3, [r3, #0]
     db8:	9306      	str	r3, [sp, #24]
     dba:	2300      	movs	r3, #0
     dbc:	9307      	str	r3, [sp, #28]
     dbe:	e012      	b.n	de6 <CONFIG_ISR_STACK_SIZE+0x5e6>
					value->uint = (wchar_t)va_arg(ap,
     dc0:	9b03      	ldr	r3, [sp, #12]
     dc2:	1d1a      	adds	r2, r3, #4
     dc4:	9203      	str	r2, [sp, #12]
     dc6:	681b      	ldr	r3, [r3, #0]
     dc8:	9306      	str	r3, [sp, #24]
     dca:	2300      	movs	r3, #0
     dcc:	9307      	str	r3, [sp, #28]
     dce:	e00a      	b.n	de6 <CONFIG_ISR_STACK_SIZE+0x5e6>
					(uint_value_type)va_arg(ap,
     dd0:	9b03      	ldr	r3, [sp, #12]
     dd2:	3307      	adds	r3, #7
     dd4:	f023 0307 	bic.w	r3, r3, #7
     dd8:	f103 0208 	add.w	r2, r3, #8
     ddc:	9203      	str	r2, [sp, #12]
     dde:	e9d3 2300 	ldrd	r2, r3, [r3]
				value->uint =
     de2:	e9cd 2306 	strd	r2, r3, [sp, #24]
			if (length_mod == LENGTH_HH) {
     de6:	2901      	cmp	r1, #1
     de8:	d01c      	beq.n	e24 <CONFIG_ISR_STACK_SIZE+0x624>
			} else if (length_mod == LENGTH_H) {
     dea:	2902      	cmp	r1, #2
     dec:	f47f aebc 	bne.w	b68 <CONFIG_ISR_STACK_SIZE+0x368>
				value->uint = (unsigned short)value->uint;
     df0:	f8bd 3018 	ldrh.w	r3, [sp, #24]
     df4:	9306      	str	r3, [sp, #24]
     df6:	2300      	movs	r3, #0
     df8:	9307      	str	r3, [sp, #28]
     dfa:	e6b5      	b.n	b68 <CONFIG_ISR_STACK_SIZE+0x368>
					(uint_value_type)va_arg(ap,
     dfc:	9b03      	ldr	r3, [sp, #12]
     dfe:	3307      	adds	r3, #7
     e00:	f023 0307 	bic.w	r3, r3, #7
     e04:	f103 0208 	add.w	r2, r3, #8
     e08:	9203      	str	r2, [sp, #12]
     e0a:	e9d3 2300 	ldrd	r2, r3, [r3]
				value->uint =
     e0e:	e9cd 2306 	strd	r2, r3, [sp, #24]
				break;
     e12:	e7e8      	b.n	de6 <CONFIG_ISR_STACK_SIZE+0x5e6>
					(uint_value_type)va_arg(ap, size_t);
     e14:	9b03      	ldr	r3, [sp, #12]
     e16:	1d1a      	adds	r2, r3, #4
     e18:	9203      	str	r2, [sp, #12]
     e1a:	681b      	ldr	r3, [r3, #0]
				value->uint =
     e1c:	9306      	str	r3, [sp, #24]
     e1e:	2300      	movs	r3, #0
     e20:	9307      	str	r3, [sp, #28]
				break;
     e22:	e7e0      	b.n	de6 <CONFIG_ISR_STACK_SIZE+0x5e6>
				value->uint = (unsigned char)value->uint;
     e24:	f89d 3018 	ldrb.w	r3, [sp, #24]
     e28:	9306      	str	r3, [sp, #24]
     e2a:	2300      	movs	r3, #0
     e2c:	9307      	str	r3, [sp, #28]
     e2e:	e69b      	b.n	b68 <CONFIG_ISR_STACK_SIZE+0x368>
			if (length_mod == LENGTH_UPPER_L) {
     e30:	2908      	cmp	r1, #8
     e32:	d00b      	beq.n	e4c <CONFIG_ISR_STACK_SIZE+0x64c>
				value->dbl = va_arg(ap, double);
     e34:	9b03      	ldr	r3, [sp, #12]
     e36:	3307      	adds	r3, #7
     e38:	f023 0307 	bic.w	r3, r3, #7
     e3c:	f103 0208 	add.w	r2, r3, #8
     e40:	9203      	str	r2, [sp, #12]
     e42:	e9d3 2300 	ldrd	r2, r3, [r3]
     e46:	e9cd 2306 	strd	r2, r3, [sp, #24]
     e4a:	e68d      	b.n	b68 <CONFIG_ISR_STACK_SIZE+0x368>
				value->ldbl = va_arg(ap, long double);
     e4c:	9b03      	ldr	r3, [sp, #12]
     e4e:	3307      	adds	r3, #7
     e50:	f023 0307 	bic.w	r3, r3, #7
     e54:	f103 0208 	add.w	r2, r3, #8
     e58:	9203      	str	r2, [sp, #12]
     e5a:	e9d3 2300 	ldrd	r2, r3, [r3]
     e5e:	e9cd 2306 	strd	r2, r3, [sp, #24]
     e62:	e681      	b.n	b68 <CONFIG_ISR_STACK_SIZE+0x368>
			value->ptr = va_arg(ap, void *);
     e64:	9b03      	ldr	r3, [sp, #12]
     e66:	1d1a      	adds	r2, r3, #4
     e68:	9203      	str	r2, [sp, #12]
     e6a:	681b      	ldr	r3, [r3, #0]
     e6c:	9306      	str	r3, [sp, #24]
     e6e:	e67b      	b.n	b68 <CONFIG_ISR_STACK_SIZE+0x368>
			OUTS(sp, fp);
     e70:	4643      	mov	r3, r8
     e72:	4652      	mov	r2, sl
     e74:	4629      	mov	r1, r5
     e76:	4630      	mov	r0, r6
     e78:	f005 feff 	bl	6c7a <outs>
     e7c:	2800      	cmp	r0, #0
     e7e:	f2c0 814f 	blt.w	1120 <CONFIG_FPROTECT_BLOCK_SIZE+0x120>
     e82:	4404      	add	r4, r0
		fp = extract_conversion(conv, sp);
     e84:	46c2      	mov	sl, r8
			continue;
     e86:	e46f      	b.n	768 <cbvprintf+0x10>
		case '%':
			OUTC('%');
     e88:	4629      	mov	r1, r5
     e8a:	2025      	movs	r0, #37	; 0x25
     e8c:	47b0      	blx	r6
     e8e:	2800      	cmp	r0, #0
     e90:	f2c0 8146 	blt.w	1120 <CONFIG_FPROTECT_BLOCK_SIZE+0x120>
     e94:	3401      	adds	r4, #1
		char sign = 0;
     e96:	f8dd 9008 	ldr.w	r9, [sp, #8]
		const char *bpe = buf + sizeof(buf);
     e9a:	f10d 0b46 	add.w	fp, sp, #70	; 0x46
		const char *bps = NULL;
     e9e:	f04f 0a00 	mov.w	sl, #0
			break;
     ea2:	e0a7      	b.n	ff4 <CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD+0x54>
		case 's': {
			bps = (const char *)value->ptr;
     ea4:	f8dd a018 	ldr.w	sl, [sp, #24]

			size_t len;

			if (precision >= 0) {
     ea8:	f1bb 0f00 	cmp.w	fp, #0
     eac:	db08      	blt.n	ec0 <CONFIG_ISR_STACK_SIZE+0x6c0>
				len = strnlen(bps, precision);
     eae:	4659      	mov	r1, fp
     eb0:	4650      	mov	r0, sl
     eb2:	f007 f90b 	bl	80cc <strnlen>
			} else {
				len = strlen(bps);
			}

			bpe = bps + len;
     eb6:	eb0a 0b00 	add.w	fp, sl, r0
		char sign = 0;
     eba:	f8dd 9008 	ldr.w	r9, [sp, #8]
			precision = -1;

			break;
     ebe:	e099      	b.n	ff4 <CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD+0x54>
				len = strlen(bps);
     ec0:	4650      	mov	r0, sl
     ec2:	f7ff faa1 	bl	408 <strlen>
     ec6:	e7f6      	b.n	eb6 <CONFIG_ISR_STACK_SIZE+0x6b6>
		}
		case 'c':
			bps = buf;
			buf[0] = CHAR_IS_SIGNED ? value->sint : value->uint;
     ec8:	9b06      	ldr	r3, [sp, #24]
     eca:	f88d 3030 	strb.w	r3, [sp, #48]	; 0x30
		char sign = 0;
     ece:	f8dd 9008 	ldr.w	r9, [sp, #8]
			bpe = buf + 1;
     ed2:	f10d 0b31 	add.w	fp, sp, #49	; 0x31
			bps = buf;
     ed6:	f10d 0a30 	add.w	sl, sp, #48	; 0x30
			break;
     eda:	e08b      	b.n	ff4 <CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD+0x54>
		case 'd':
		case 'i':
			if (conv->flag_plus) {
     edc:	f019 0f08 	tst.w	r9, #8
     ee0:	d105      	bne.n	eee <CONFIG_ISR_STACK_SIZE+0x6ee>
				sign = '+';
			} else if (conv->flag_space) {
     ee2:	f019 0910 	ands.w	r9, r9, #16
     ee6:	d004      	beq.n	ef2 <CONFIG_ISR_STACK_SIZE+0x6f2>
				sign = ' ';
     ee8:	f04f 0920 	mov.w	r9, #32
     eec:	e001      	b.n	ef2 <CONFIG_ISR_STACK_SIZE+0x6f2>
				sign = '+';
     eee:	f04f 092b 	mov.w	r9, #43	; 0x2b

			/* sint/uint overlay in the union, and so
			 * can't appear in read and write operations
			 * in the same statement.
			 */
			sint = value->sint;
     ef2:	e9dd 2306 	ldrd	r2, r3, [sp, #24]
			if (sint < 0) {
     ef6:	2a00      	cmp	r2, #0
     ef8:	f173 0100 	sbcs.w	r1, r3, #0
     efc:	db02      	blt.n	f04 <CONFIG_ISR_STACK_SIZE+0x704>
				sign = '-';
				value->uint = (uint_value_type)-sint;
			} else {
				value->uint = (uint_value_type)sint;
     efe:	e9cd 2306 	strd	r2, r3, [sp, #24]
     f02:	e009      	b.n	f18 <CONFIG_ISR_STACK_SIZE+0x718>
				value->uint = (uint_value_type)-sint;
     f04:	4252      	negs	r2, r2
     f06:	eb63 0343 	sbc.w	r3, r3, r3, lsl #1
     f0a:	e9cd 2306 	strd	r2, r3, [sp, #24]
				sign = '-';
     f0e:	f04f 092d 	mov.w	r9, #45	; 0x2d
     f12:	e001      	b.n	f18 <CONFIG_ISR_STACK_SIZE+0x718>
		switch (conv->specifier) {
     f14:	f8dd 9008 	ldr.w	r9, [sp, #8]
			__fallthrough;
		case 'o':
		case 'u':
		case 'x':
		case 'X':
			bps = encode_uint(value->uint, conv, buf, bpe);
     f18:	f10d 0346 	add.w	r3, sp, #70	; 0x46
     f1c:	9300      	str	r3, [sp, #0]
     f1e:	ab0c      	add	r3, sp, #48	; 0x30
     f20:	aa08      	add	r2, sp, #32
     f22:	e9dd 0106 	ldrd	r0, r1, [sp, #24]
     f26:	f7ff fba7 	bl	678 <encode_uint>
     f2a:	4682      	mov	sl, r0
			/* Update pad0 values based on precision and converted
			 * length.  Note that a non-empty sign is not in the
			 * converted sequence, but it does not affect the
			 * padding size.
			 */
			if (precision >= 0) {
     f2c:	f1bb 0f00 	cmp.w	fp, #0
     f30:	f2c0 8090 	blt.w	1054 <CONFIG_FPROTECT_BLOCK_SIZE+0x54>
				size_t len = bpe - bps;
     f34:	f10d 0346 	add.w	r3, sp, #70	; 0x46
     f38:	eba3 030a 	sub.w	r3, r3, sl

				/* Zero-padding flag is ignored for integer
				 * conversions with precision.
				 */
				conv->flag_zero = false;
     f3c:	f89d 2020 	ldrb.w	r2, [sp, #32]
     f40:	f36f 1286 	bfc	r2, #6, #1
     f44:	f88d 2020 	strb.w	r2, [sp, #32]

				/* Set pad0_value to satisfy precision */
				if (len < (size_t)precision) {
     f48:	459b      	cmp	fp, r3
     f4a:	f240 8086 	bls.w	105a <CONFIG_FPROTECT_BLOCK_SIZE+0x5a>
					conv->pad0_value = precision - (int)len;
     f4e:	ebab 0303 	sub.w	r3, fp, r3
     f52:	9309      	str	r3, [sp, #36]	; 0x24
		const char *bpe = buf + sizeof(buf);
     f54:	f10d 0b46 	add.w	fp, sp, #70	; 0x46
     f58:	e04c      	b.n	ff4 <CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD+0x54>
		case 'p':
			/* Implementation-defined: null is "(nil)", non-null
			 * has 0x prefix followed by significant address hex
			 * digits, no leading zeros.
			 */
			if (value->ptr != NULL) {
     f5a:	9806      	ldr	r0, [sp, #24]
     f5c:	b930      	cbnz	r0, f6c <CONFIG_ISR_STACK_SIZE+0x76c>
		char sign = 0;
     f5e:	f8dd 9008 	ldr.w	r9, [sp, #8]

				goto prec_int_pad0;
			}

			bps = "(nil)";
			bpe = bps + 5;
     f62:	f8df b1c4 	ldr.w	fp, [pc, #452]	; 1128 <CONFIG_FPROTECT_BLOCK_SIZE+0x128>
			bps = "(nil)";
     f66:	f1ab 0a05 	sub.w	sl, fp, #5
     f6a:	e043      	b.n	ff4 <CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD+0x54>
				bps = encode_uint((uintptr_t)value->ptr, conv,
     f6c:	f10d 0346 	add.w	r3, sp, #70	; 0x46
     f70:	9300      	str	r3, [sp, #0]
     f72:	ab0c      	add	r3, sp, #48	; 0x30
     f74:	aa08      	add	r2, sp, #32
     f76:	2100      	movs	r1, #0
     f78:	f7ff fb7e 	bl	678 <encode_uint>
     f7c:	4682      	mov	sl, r0
				conv->altform_0c = true;
     f7e:	f89d 3022 	ldrb.w	r3, [sp, #34]	; 0x22
     f82:	f043 0310 	orr.w	r3, r3, #16
     f86:	f88d 3022 	strb.w	r3, [sp, #34]	; 0x22
				conv->specifier = 'x';
     f8a:	2378      	movs	r3, #120	; 0x78
     f8c:	f88d 3023 	strb.w	r3, [sp, #35]	; 0x23
		char sign = 0;
     f90:	f8dd 9008 	ldr.w	r9, [sp, #8]
				goto prec_int_pad0;
     f94:	e7ca      	b.n	f2c <CONFIG_ISR_STACK_SIZE+0x72c>

			break;
		case 'n':
			if (IS_ENABLED(CONFIG_CBPRINTF_N_SPECIFIER)) {
				store_count(conv, value->ptr, count);
     f96:	9a06      	ldr	r2, [sp, #24]
	switch ((enum length_mod_enum)conv->length_mod) {
     f98:	f89d 3021 	ldrb.w	r3, [sp, #33]	; 0x21
     f9c:	f3c3 03c3 	ubfx	r3, r3, #3, #4
     fa0:	2b07      	cmp	r3, #7
     fa2:	d806      	bhi.n	fb2 <CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD+0x12>
     fa4:	e8df f003 	tbb	[pc, r3]
     fa8:	100e0c04 	.word	0x100e0c04
     fac:	1e1c1712 	.word	0x1e1c1712
		*(int *)dp = count;
     fb0:	6014      	str	r4, [r2, #0]
		char sign = 0;
     fb2:	f8dd 9008 	ldr.w	r9, [sp, #8]
		const char *bpe = buf + sizeof(buf);
     fb6:	f10d 0b46 	add.w	fp, sp, #70	; 0x46
		const char *bps = NULL;
     fba:	f04f 0a00 	mov.w	sl, #0
}
     fbe:	e019      	b.n	ff4 <CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD+0x54>
		*(signed char *)dp = (signed char)count;
     fc0:	7014      	strb	r4, [r2, #0]
		break;
     fc2:	e7f6      	b.n	fb2 <CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD+0x12>
		*(short *)dp = (short)count;
     fc4:	8014      	strh	r4, [r2, #0]
		break;
     fc6:	e7f4      	b.n	fb2 <CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD+0x12>
		*(long *)dp = (long)count;
     fc8:	6014      	str	r4, [r2, #0]
		break;
     fca:	e7f2      	b.n	fb2 <CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD+0x12>
		*(long long *)dp = (long long)count;
     fcc:	4620      	mov	r0, r4
     fce:	17e1      	asrs	r1, r4, #31
     fd0:	e9c2 0100 	strd	r0, r1, [r2]
		break;
     fd4:	e7ed      	b.n	fb2 <CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD+0x12>
		*(intmax_t *)dp = (intmax_t)count;
     fd6:	4620      	mov	r0, r4
     fd8:	17e1      	asrs	r1, r4, #31
     fda:	e9c2 0100 	strd	r0, r1, [r2]
		break;
     fde:	e7e8      	b.n	fb2 <CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD+0x12>
		*(size_t *)dp = (size_t)count;
     fe0:	6014      	str	r4, [r2, #0]
		break;
     fe2:	e7e6      	b.n	fb2 <CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD+0x12>
		*(ptrdiff_t *)dp = (ptrdiff_t)count;
     fe4:	6014      	str	r4, [r2, #0]
		break;
     fe6:	e7e4      	b.n	fb2 <CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD+0x12>
		switch (conv->specifier) {
     fe8:	f8dd 9008 	ldr.w	r9, [sp, #8]
     fec:	f10d 0b46 	add.w	fp, sp, #70	; 0x46
     ff0:	f04f 0a00 	mov.w	sl, #0
		}

		/* If we don't have a converted value to emit, move
		 * on.
		 */
		if (bps == NULL) {
     ff4:	f1ba 0f00 	cmp.w	sl, #0
     ff8:	f000 808e 	beq.w	1118 <CONFIG_FPROTECT_BLOCK_SIZE+0x118>
		 *   * any exponent content from the converted value
		 * * for non-FP:
		 *   * any pad0_prefix
		 *   * the converted value
		 */
		size_t nj_len = (bpe - bps);
     ffc:	ebab 020a 	sub.w	r2, fp, sl
		int pad_len = 0;

		if (sign != 0) {
    1000:	f1b9 0f00 	cmp.w	r9, #0
    1004:	d000      	beq.n	1008 <CONFIG_FPROTECT_BLOCK_SIZE+0x8>
			nj_len += 1U;
    1006:	3201      	adds	r2, #1
		}

		if (conv->altform_0c) {
    1008:	f89d 1022 	ldrb.w	r1, [sp, #34]	; 0x22
    100c:	f011 0f10 	tst.w	r1, #16
    1010:	d026      	beq.n	1060 <CONFIG_FPROTECT_BLOCK_SIZE+0x60>
			nj_len += 2U;
    1012:	3202      	adds	r2, #2
		} else if (conv->altform_0) {
			nj_len += 1U;
		}

		nj_len += conv->pad0_value;
    1014:	9b09      	ldr	r3, [sp, #36]	; 0x24
    1016:	4413      	add	r3, r2
		if (conv->pad_fp) {
    1018:	f011 0f40 	tst.w	r1, #64	; 0x40
    101c:	d001      	beq.n	1022 <CONFIG_FPROTECT_BLOCK_SIZE+0x22>
			nj_len += conv->pad0_pre_exp;
    101e:	9a0a      	ldr	r2, [sp, #40]	; 0x28
    1020:	4413      	add	r3, r2
		 * result in no padding.
		 *
		 * If a non-negative padding width is present and we're doing
		 * right-justification, emit the padding now.
		 */
		if (width > 0) {
    1022:	2f00      	cmp	r7, #0
    1024:	dd32      	ble.n	108c <CONFIG_FPROTECT_BLOCK_SIZE+0x8c>
			width -= (int)nj_len;
    1026:	1aff      	subs	r7, r7, r3

			if (!conv->flag_dash) {
    1028:	f89d 3020 	ldrb.w	r3, [sp, #32]
    102c:	f013 0f04 	tst.w	r3, #4
    1030:	d12c      	bne.n	108c <CONFIG_FPROTECT_BLOCK_SIZE+0x8c>
				char pad = ' ';

				/* If we're zero-padding we have to emit the
				 * sign first.
				 */
				if (conv->flag_zero) {
    1032:	f013 0f40 	tst.w	r3, #64	; 0x40
    1036:	d018      	beq.n	106a <CONFIG_FPROTECT_BLOCK_SIZE+0x6a>
					if (sign != 0) {
    1038:	f1b9 0f00 	cmp.w	r9, #0
    103c:	d018      	beq.n	1070 <CONFIG_FPROTECT_BLOCK_SIZE+0x70>
						OUTC(sign);
    103e:	4629      	mov	r1, r5
    1040:	4648      	mov	r0, r9
    1042:	47b0      	blx	r6
    1044:	2800      	cmp	r0, #0
    1046:	db6b      	blt.n	1120 <CONFIG_FPROTECT_BLOCK_SIZE+0x120>
    1048:	3401      	adds	r4, #1
						sign = 0;
    104a:	f8dd 9008 	ldr.w	r9, [sp, #8]
					}
					pad = '0';
    104e:	2330      	movs	r3, #48	; 0x30
    1050:	9302      	str	r3, [sp, #8]
    1052:	e00f      	b.n	1074 <CONFIG_FPROTECT_BLOCK_SIZE+0x74>
		const char *bpe = buf + sizeof(buf);
    1054:	f10d 0b46 	add.w	fp, sp, #70	; 0x46
    1058:	e7cc      	b.n	ff4 <CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD+0x54>
    105a:	f10d 0b46 	add.w	fp, sp, #70	; 0x46
    105e:	e7c9      	b.n	ff4 <CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD+0x54>
		} else if (conv->altform_0) {
    1060:	f011 0f08 	tst.w	r1, #8
    1064:	d0d6      	beq.n	1014 <CONFIG_FPROTECT_BLOCK_SIZE+0x14>
			nj_len += 1U;
    1066:	3201      	adds	r2, #1
    1068:	e7d4      	b.n	1014 <CONFIG_FPROTECT_BLOCK_SIZE+0x14>
				char pad = ' ';
    106a:	2320      	movs	r3, #32
    106c:	9302      	str	r3, [sp, #8]
    106e:	e001      	b.n	1074 <CONFIG_FPROTECT_BLOCK_SIZE+0x74>
					pad = '0';
    1070:	2330      	movs	r3, #48	; 0x30
    1072:	9302      	str	r3, [sp, #8]
    1074:	463b      	mov	r3, r7
				}

				while (width-- > 0) {
    1076:	1e5f      	subs	r7, r3, #1
    1078:	2b00      	cmp	r3, #0
    107a:	dd07      	ble.n	108c <CONFIG_FPROTECT_BLOCK_SIZE+0x8c>
					OUTC(pad);
    107c:	4629      	mov	r1, r5
    107e:	9802      	ldr	r0, [sp, #8]
    1080:	47b0      	blx	r6
    1082:	2800      	cmp	r0, #0
    1084:	db4c      	blt.n	1120 <CONFIG_FPROTECT_BLOCK_SIZE+0x120>
    1086:	3401      	adds	r4, #1
				while (width-- > 0) {
    1088:	463b      	mov	r3, r7
    108a:	e7f4      	b.n	1076 <CONFIG_FPROTECT_BLOCK_SIZE+0x76>
		}

		/* If we have a sign that hasn't been emitted, now's the
		 * time....
		 */
		if (sign != 0) {
    108c:	f1b9 0f00 	cmp.w	r9, #0
    1090:	d005      	beq.n	109e <CONFIG_FPROTECT_BLOCK_SIZE+0x9e>
			OUTC(sign);
    1092:	4629      	mov	r1, r5
    1094:	4648      	mov	r0, r9
    1096:	47b0      	blx	r6
    1098:	2800      	cmp	r0, #0
    109a:	db41      	blt.n	1120 <CONFIG_FPROTECT_BLOCK_SIZE+0x120>
    109c:	3401      	adds	r4, #1
				OUTC('0');
			}

			OUTS(cp, bpe);
		} else {
			if (conv->altform_0c | conv->altform_0) {
    109e:	f89d 3022 	ldrb.w	r3, [sp, #34]	; 0x22
    10a2:	f3c3 1200 	ubfx	r2, r3, #4, #1
    10a6:	f3c3 03c0 	ubfx	r3, r3, #3, #1
    10aa:	4313      	orrs	r3, r2
    10ac:	d005      	beq.n	10ba <CONFIG_FPROTECT_BLOCK_SIZE+0xba>
				OUTC('0');
    10ae:	4629      	mov	r1, r5
    10b0:	2030      	movs	r0, #48	; 0x30
    10b2:	47b0      	blx	r6
    10b4:	2800      	cmp	r0, #0
    10b6:	db33      	blt.n	1120 <CONFIG_FPROTECT_BLOCK_SIZE+0x120>
    10b8:	3401      	adds	r4, #1
			}

			if (conv->altform_0c) {
    10ba:	f89d 3022 	ldrb.w	r3, [sp, #34]	; 0x22
    10be:	f013 0f10 	tst.w	r3, #16
    10c2:	d006      	beq.n	10d2 <CONFIG_FPROTECT_BLOCK_SIZE+0xd2>
				OUTC(conv->specifier);
    10c4:	4629      	mov	r1, r5
    10c6:	f89d 0023 	ldrb.w	r0, [sp, #35]	; 0x23
    10ca:	47b0      	blx	r6
    10cc:	2800      	cmp	r0, #0
    10ce:	db27      	blt.n	1120 <CONFIG_FPROTECT_BLOCK_SIZE+0x120>
    10d0:	3401      	adds	r4, #1
			}

			pad_len = conv->pad0_value;
    10d2:	9b09      	ldr	r3, [sp, #36]	; 0x24
			while (pad_len-- > 0) {
    10d4:	f103 39ff 	add.w	r9, r3, #4294967295
    10d8:	2b00      	cmp	r3, #0
    10da:	dd07      	ble.n	10ec <CONFIG_FPROTECT_BLOCK_SIZE+0xec>
				OUTC('0');
    10dc:	4629      	mov	r1, r5
    10de:	2030      	movs	r0, #48	; 0x30
    10e0:	47b0      	blx	r6
    10e2:	2800      	cmp	r0, #0
    10e4:	db1c      	blt.n	1120 <CONFIG_FPROTECT_BLOCK_SIZE+0x120>
    10e6:	3401      	adds	r4, #1
			while (pad_len-- > 0) {
    10e8:	464b      	mov	r3, r9
    10ea:	e7f3      	b.n	10d4 <CONFIG_FPROTECT_BLOCK_SIZE+0xd4>
			}

			OUTS(bps, bpe);
    10ec:	465b      	mov	r3, fp
    10ee:	4652      	mov	r2, sl
    10f0:	4629      	mov	r1, r5
    10f2:	4630      	mov	r0, r6
    10f4:	f005 fdc1 	bl	6c7a <outs>
    10f8:	2800      	cmp	r0, #0
    10fa:	db11      	blt.n	1120 <CONFIG_FPROTECT_BLOCK_SIZE+0x120>
    10fc:	4404      	add	r4, r0
		}

		/* Finish left justification */
		while (width > 0) {
    10fe:	2f00      	cmp	r7, #0
    1100:	dd07      	ble.n	1112 <CONFIG_FPROTECT_BLOCK_SIZE+0x112>
			OUTC(' ');
    1102:	4629      	mov	r1, r5
    1104:	2020      	movs	r0, #32
    1106:	47b0      	blx	r6
    1108:	2800      	cmp	r0, #0
    110a:	db09      	blt.n	1120 <CONFIG_FPROTECT_BLOCK_SIZE+0x120>
    110c:	3401      	adds	r4, #1
			--width;
    110e:	3f01      	subs	r7, #1
    1110:	e7f5      	b.n	10fe <CONFIG_FPROTECT_BLOCK_SIZE+0xfe>
		fp = extract_conversion(conv, sp);
    1112:	46c2      	mov	sl, r8
    1114:	f7ff bb28 	b.w	768 <cbvprintf+0x10>
    1118:	46c2      	mov	sl, r8
    111a:	f7ff bb25 	b.w	768 <cbvprintf+0x10>
		}
	}

	return count;
    111e:	4620      	mov	r0, r4
#undef OUTS
#undef OUTC
}
    1120:	b013      	add	sp, #76	; 0x4c
    1122:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    1126:	bf00      	nop
    1128:	00008505 	.word	0x00008505

0000112c <is_rodata>:
#else
	#define RO_START 0
	#define RO_END 0
#endif

	return (((const char *)addr >= (const char *)RO_START) &&
    112c:	4b05      	ldr	r3, [pc, #20]	; (1144 <is_rodata+0x18>)
    112e:	4298      	cmp	r0, r3
    1130:	d304      	bcc.n	113c <is_rodata+0x10>
    1132:	4b05      	ldr	r3, [pc, #20]	; (1148 <is_rodata+0x1c>)
    1134:	4298      	cmp	r0, r3
    1136:	d303      	bcc.n	1140 <is_rodata+0x14>
    1138:	2000      	movs	r0, #0
    113a:	4770      	bx	lr
    113c:	2000      	movs	r0, #0
    113e:	4770      	bx	lr
    1140:	2001      	movs	r0, #1
		((const char *)addr < (const char *)RO_END));
}
    1142:	4770      	bx	lr
    1144:	000080f4 	.word	0x000080f4
    1148:	00008fa8 	.word	0x00008fa8

0000114c <thread_set>:
		}
	}
}

static void thread_set(k_tid_t process_tid)
{
    114c:	b508      	push	{r3, lr}
	proc_tid = process_tid;
    114e:	4b06      	ldr	r3, [pc, #24]	; (1168 <thread_set+0x1c>)
    1150:	6018      	str	r0, [r3, #0]

	if (IS_ENABLED(CONFIG_LOG_IMMEDIATE)) {
		return;
	}

	if (CONFIG_LOG_PROCESS_TRIGGER_THRESHOLD &&
    1152:	b118      	cbz	r0, 115c <thread_set+0x10>
	    process_tid &&
	    buffered_cnt >= CONFIG_LOG_PROCESS_TRIGGER_THRESHOLD) {
    1154:	4b05      	ldr	r3, [pc, #20]	; (116c <thread_set+0x20>)
    1156:	681b      	ldr	r3, [r3, #0]
	    process_tid &&
    1158:	2b09      	cmp	r3, #9
    115a:	dc00      	bgt.n	115e <thread_set+0x12>
		k_sem_give(&log_process_thread_sem);
	}
}
    115c:	bd08      	pop	{r3, pc}
		arch_syscall_invoke1(*(uintptr_t *)&sem, K_SYSCALL_K_SEM_GIVE);
		return;
	}
#endif
	compiler_barrier();
	z_impl_k_sem_give(sem);
    115e:	4804      	ldr	r0, [pc, #16]	; (1170 <thread_set+0x24>)
    1160:	f004 fb8a 	bl	5878 <z_impl_k_sem_give>
}
    1164:	e7fa      	b.n	115c <thread_set+0x10>
    1166:	bf00      	nop
    1168:	2000044c 	.word	0x2000044c
    116c:	20000418 	.word	0x20000418
    1170:	200000c4 	.word	0x200000c4

00001174 <log_process_thread_timer_expiry_fn>:
{
	return mpsc_pbuf_is_pending(&log_buffer);
}

static void log_process_thread_timer_expiry_fn(struct k_timer *timer)
{
    1174:	b508      	push	{r3, lr}
	z_impl_k_sem_give(sem);
    1176:	4802      	ldr	r0, [pc, #8]	; (1180 <log_process_thread_timer_expiry_fn+0xc>)
    1178:	f004 fb7e 	bl	5878 <z_impl_k_sem_give>
	k_sem_give(&log_process_thread_sem);
}
    117c:	bd08      	pop	{r3, pc}
    117e:	bf00      	nop
    1180:	200000c4 	.word	0x200000c4

00001184 <next_pending>:
{
    1184:	b508      	push	{r3, lr}
	return (log_list_head_peek(&list) != NULL);
    1186:	4803      	ldr	r0, [pc, #12]	; (1194 <next_pending+0x10>)
    1188:	f005 fda0 	bl	6ccc <log_list_head_peek>
}
    118c:	3800      	subs	r0, #0
    118e:	bf18      	it	ne
    1190:	2001      	movne	r0, #1
    1192:	bd08      	pop	{r3, pc}
    1194:	20000424 	.word	0x20000424

00001198 <enable_logger>:

K_KERNEL_STACK_DEFINE(logging_stack, CONFIG_LOG_PROCESS_THREAD_STACK_SIZE);
struct k_thread logging_thread;

static int enable_logger(const struct device *arg)
{
    1198:	b530      	push	{r4, r5, lr}
    119a:	b089      	sub	sp, #36	; 0x24
	ARG_UNUSED(arg);

	if (IS_ENABLED(CONFIG_LOG_PROCESS_THREAD)) {
		k_timer_init(&log_process_thread_timer,
    119c:	2200      	movs	r2, #0
    119e:	490f      	ldr	r1, [pc, #60]	; (11dc <enable_logger+0x44>)
    11a0:	480f      	ldr	r0, [pc, #60]	; (11e0 <enable_logger+0x48>)
    11a2:	f006 ff3e 	bl	8022 <k_timer_init>
	return z_impl_k_thread_create(new_thread, stack, stack_size, entry, p1, p2, p3, prio, options, delay);
    11a6:	4d0f      	ldr	r5, [pc, #60]	; (11e4 <enable_logger+0x4c>)
    11a8:	2200      	movs	r2, #0
    11aa:	2300      	movs	r3, #0
    11ac:	e9cd 2306 	strd	r2, r3, [sp, #24]
    11b0:	2400      	movs	r4, #0
    11b2:	9404      	str	r4, [sp, #16]
    11b4:	230e      	movs	r3, #14
    11b6:	9303      	str	r3, [sp, #12]
    11b8:	9402      	str	r4, [sp, #8]
    11ba:	9401      	str	r4, [sp, #4]
    11bc:	9400      	str	r4, [sp, #0]
    11be:	4b0a      	ldr	r3, [pc, #40]	; (11e8 <enable_logger+0x50>)
    11c0:	f44f 7240 	mov.w	r2, #768	; 0x300
    11c4:	4909      	ldr	r1, [pc, #36]	; (11ec <enable_logger+0x54>)
    11c6:	4628      	mov	r0, r5
    11c8:	f006 fcb6 	bl	7b38 <z_impl_k_thread_create>
	return z_impl_k_thread_name_set(thread, str);
    11cc:	4908      	ldr	r1, [pc, #32]	; (11f0 <enable_logger+0x58>)
    11ce:	4628      	mov	r0, r5
    11d0:	f004 f9a0 	bl	5514 <z_impl_k_thread_name_set>
	} else {
		log_init();
	}

	return 0;
}
    11d4:	4620      	mov	r0, r4
    11d6:	b009      	add	sp, #36	; 0x24
    11d8:	bd30      	pop	{r4, r5, pc}
    11da:	bf00      	nop
    11dc:	00001175 	.word	0x00001175
    11e0:	200000d8 	.word	0x200000d8
    11e4:	20000110 	.word	0x20000110
    11e8:	00001889 	.word	0x00001889
    11ec:	20000b90 	.word	0x20000b90
    11f0:	00008508 	.word	0x00008508

000011f4 <z_log_get_s_mask>:
{
    11f4:	b470      	push	{r4, r5, r6}
    11f6:	4603      	mov	r3, r0
	uint32_t mask = 0U;
    11f8:	2000      	movs	r0, #0
	uint32_t arg = 0U;
    11fa:	4605      	mov	r5, r0
	bool arm = false;
    11fc:	4604      	mov	r4, r0
	while ((curr = *str++) && arg < nargs) {
    11fe:	e001      	b.n	1204 <z_log_get_s_mask+0x10>
			arm = !arm;
    1200:	f084 0401 	eor.w	r4, r4, #1
	while ((curr = *str++) && arg < nargs) {
    1204:	f813 2b01 	ldrb.w	r2, [r3], #1
    1208:	b19a      	cbz	r2, 1232 <z_log_get_s_mask+0x3e>
    120a:	428d      	cmp	r5, r1
    120c:	d211      	bcs.n	1232 <z_log_get_s_mask+0x3e>
		if (curr == '%') {
    120e:	2a25      	cmp	r2, #37	; 0x25
    1210:	d0f6      	beq.n	1200 <z_log_get_s_mask+0xc>
		} else if (arm && isalpha((int)curr)) {
    1212:	2c00      	cmp	r4, #0
    1214:	d0f6      	beq.n	1204 <z_log_get_s_mask+0x10>
    1216:	4e08      	ldr	r6, [pc, #32]	; (1238 <z_log_get_s_mask+0x44>)
    1218:	5d96      	ldrb	r6, [r2, r6]
    121a:	f016 0f03 	tst.w	r6, #3
    121e:	d0f1      	beq.n	1204 <z_log_get_s_mask+0x10>
			if (curr == 's') {
    1220:	2a73      	cmp	r2, #115	; 0x73
    1222:	d002      	beq.n	122a <z_log_get_s_mask+0x36>
			arg++;
    1224:	3501      	adds	r5, #1
			arm = false;
    1226:	2400      	movs	r4, #0
    1228:	e7ec      	b.n	1204 <z_log_get_s_mask+0x10>
				mask |= BIT(arg);
    122a:	2201      	movs	r2, #1
    122c:	40aa      	lsls	r2, r5
    122e:	4310      	orrs	r0, r2
    1230:	e7f8      	b.n	1224 <z_log_get_s_mask+0x30>
}
    1232:	bc70      	pop	{r4, r5, r6}
    1234:	4770      	bx	lr
    1236:	bf00      	nop
    1238:	00008ea6 	.word	0x00008ea6

0000123c <log_core_init>:
{
    123c:	b508      	push	{r3, lr}
	panic_mode = false;
    123e:	2300      	movs	r3, #0
    1240:	4a0b      	ldr	r2, [pc, #44]	; (1270 <log_core_init+0x34>)
    1242:	7013      	strb	r3, [r2, #0]
	dropped_cnt = 0;
    1244:	4a0b      	ldr	r2, [pc, #44]	; (1274 <log_core_init+0x38>)
    1246:	6013      	str	r3, [r2, #0]
		timestamp_func = default_get_timestamp;
    1248:	4b0b      	ldr	r3, [pc, #44]	; (1278 <log_core_init+0x3c>)
    124a:	4a0c      	ldr	r2, [pc, #48]	; (127c <log_core_init+0x40>)
    124c:	601a      	str	r2, [r3, #0]
	log_output_timestamp_freq_set(freq);
    124e:	f44f 4000 	mov.w	r0, #32768	; 0x8000
    1252:	f000 fd9d 	bl	1d90 <log_output_timestamp_freq_set>
		log_msg_pool_init();
    1256:	f000 fb7d 	bl	1954 <log_msg_pool_init>
		log_list_init(&list);
    125a:	4809      	ldr	r0, [pc, #36]	; (1280 <log_core_init+0x44>)
    125c:	f005 fd28 	bl	6cb0 <log_list_init>
		k_mem_slab_init(&log_strdup_pool, log_strdup_pool_buf,
    1260:	2304      	movs	r3, #4
    1262:	2228      	movs	r2, #40	; 0x28
    1264:	4907      	ldr	r1, [pc, #28]	; (1284 <log_core_init+0x48>)
    1266:	4808      	ldr	r0, [pc, #32]	; (1288 <log_core_init+0x4c>)
    1268:	f006 fc08 	bl	7a7c <k_mem_slab_init>
}
    126c:	bd08      	pop	{r3, pc}
    126e:	bf00      	nop
    1270:	20000b83 	.word	0x20000b83
    1274:	2000041c 	.word	0x2000041c
    1278:	20000004 	.word	0x20000004
    127c:	00006ce5 	.word	0x00006ce5
    1280:	20000424 	.word	0x20000424
    1284:	20001fd0 	.word	0x20001fd0
    1288:	2000042c 	.word	0x2000042c

0000128c <log_init>:
 *
 * @return Previous value of @a target.
 */
static inline atomic_val_t atomic_add(atomic_t *target, atomic_val_t value)
{
	return __atomic_fetch_add(target, value, __ATOMIC_SEQ_CST);
    128c:	4b18      	ldr	r3, [pc, #96]	; (12f0 <log_init+0x64>)
    128e:	f3bf 8f5b 	dmb	ish
    1292:	e853 2f00 	ldrex	r2, [r3]
    1296:	1c51      	adds	r1, r2, #1
    1298:	e843 1000 	strex	r0, r1, [r3]
    129c:	2800      	cmp	r0, #0
    129e:	d1f8      	bne.n	1292 <log_init+0x6>
    12a0:	f3bf 8f5b 	dmb	ish
	if (atomic_inc(&initialized) != 0) {
    12a4:	bb1a      	cbnz	r2, 12ee <log_init+0x62>
{
    12a6:	b570      	push	{r4, r5, r6, lr}
	for (i = 0; i < log_backend_count_get(); i++) {
    12a8:	2400      	movs	r4, #0
    12aa:	e009      	b.n	12c0 <log_init+0x34>
					   backend->cb->ctx,
    12ac:	4b11      	ldr	r3, [pc, #68]	; (12f4 <log_init+0x68>)
    12ae:	eb03 1306 	add.w	r3, r3, r6, lsl #4
    12b2:	685b      	ldr	r3, [r3, #4]
			log_backend_enable(backend,
    12b4:	2204      	movs	r2, #4
    12b6:	6819      	ldr	r1, [r3, #0]
    12b8:	4628      	mov	r0, r5
    12ba:	f000 fb29 	bl	1910 <log_backend_enable>
	for (i = 0; i < log_backend_count_get(); i++) {
    12be:	3401      	adds	r4, #1
    12c0:	4b0d      	ldr	r3, [pc, #52]	; (12f8 <log_init+0x6c>)
    12c2:	4a0c      	ldr	r2, [pc, #48]	; (12f4 <log_init+0x68>)
    12c4:	1a9b      	subs	r3, r3, r2
    12c6:	ebb4 1f23 	cmp.w	r4, r3, asr #4
    12ca:	da0f      	bge.n	12ec <log_init+0x60>
		const struct log_backend *backend = log_backend_get(i);
    12cc:	4626      	mov	r6, r4
 *
 * @return    Pointer to the backend instance.
 */
static inline const struct log_backend *log_backend_get(uint32_t idx)
{
	return &__log_backends_start[idx];
    12ce:	4d09      	ldr	r5, [pc, #36]	; (12f4 <log_init+0x68>)
    12d0:	eb05 1504 	add.w	r5, r5, r4, lsl #4
		if (backend->autostart) {
    12d4:	7b2b      	ldrb	r3, [r5, #12]
    12d6:	2b00      	cmp	r3, #0
    12d8:	d0f1      	beq.n	12be <log_init+0x32>
			if (backend->api->init != NULL) {
    12da:	0123      	lsls	r3, r4, #4
    12dc:	4a05      	ldr	r2, [pc, #20]	; (12f4 <log_init+0x68>)
    12de:	58d3      	ldr	r3, [r2, r3]
    12e0:	699b      	ldr	r3, [r3, #24]
    12e2:	2b00      	cmp	r3, #0
    12e4:	d0e2      	beq.n	12ac <log_init+0x20>
				backend->api->init(backend);
    12e6:	4628      	mov	r0, r5
    12e8:	4798      	blx	r3
    12ea:	e7df      	b.n	12ac <log_init+0x20>
}
    12ec:	bd70      	pop	{r4, r5, r6, pc}
    12ee:	4770      	bx	lr
    12f0:	20000420 	.word	0x20000420
    12f4:	000083f4 	.word	0x000083f4
    12f8:	00008414 	.word	0x00008414

000012fc <get_msg>:
{
    12fc:	b510      	push	{r4, lr}
    12fe:	f04f 0320 	mov.w	r3, #32
    1302:	f3ef 8411 	mrs	r4, BASEPRI
    1306:	f383 8812 	msr	BASEPRI_MAX, r3
    130a:	f3bf 8f6f 	isb	sy
	msg.msg = log_list_head_get(&list);
    130e:	4804      	ldr	r0, [pc, #16]	; (1320 <get_msg+0x24>)
    1310:	f005 fcde 	bl	6cd0 <log_list_head_get>
	__asm__ volatile(
    1314:	f384 8811 	msr	BASEPRI, r4
    1318:	f3bf 8f6f 	isb	sy
}
    131c:	bd10      	pop	{r4, pc}
    131e:	bf00      	nop
    1320:	20000424 	.word	0x20000424

00001324 <z_log_notify_backend_enabled>:
{
    1324:	b508      	push	{r3, lr}
	if (IS_ENABLED(CONFIG_LOG_PROCESS_THREAD) && !backend_attached) {
    1326:	4b05      	ldr	r3, [pc, #20]	; (133c <z_log_notify_backend_enabled+0x18>)
    1328:	781b      	ldrb	r3, [r3, #0]
    132a:	b11b      	cbz	r3, 1334 <z_log_notify_backend_enabled+0x10>
	backend_attached = true;
    132c:	4b03      	ldr	r3, [pc, #12]	; (133c <z_log_notify_backend_enabled+0x18>)
    132e:	2201      	movs	r2, #1
    1330:	701a      	strb	r2, [r3, #0]
}
    1332:	bd08      	pop	{r3, pc}
	z_impl_k_sem_give(sem);
    1334:	4802      	ldr	r0, [pc, #8]	; (1340 <z_log_notify_backend_enabled+0x1c>)
    1336:	f004 fa9f 	bl	5878 <z_impl_k_sem_give>
}
    133a:	e7f7      	b.n	132c <z_log_notify_backend_enabled+0x8>
    133c:	20000b82 	.word	0x20000b82
    1340:	200000c4 	.word	0x200000c4

00001344 <z_log_dropped>:
    1344:	4b0c      	ldr	r3, [pc, #48]	; (1378 <z_log_dropped+0x34>)
    1346:	f3bf 8f5b 	dmb	ish
    134a:	e853 2f00 	ldrex	r2, [r3]
    134e:	3201      	adds	r2, #1
    1350:	e843 2100 	strex	r1, r2, [r3]
    1354:	2900      	cmp	r1, #0
    1356:	d1f8      	bne.n	134a <z_log_dropped+0x6>
    1358:	f3bf 8f5b 	dmb	ish
 *
 * @return Previous value of @a target.
 */
static inline atomic_val_t atomic_sub(atomic_t *target, atomic_val_t value)
{
	return __atomic_fetch_sub(target, value, __ATOMIC_SEQ_CST);
    135c:	4b07      	ldr	r3, [pc, #28]	; (137c <z_log_dropped+0x38>)
    135e:	f3bf 8f5b 	dmb	ish
    1362:	e853 2f00 	ldrex	r2, [r3]
    1366:	3a01      	subs	r2, #1
    1368:	e843 2100 	strex	r1, r2, [r3]
    136c:	2900      	cmp	r1, #0
    136e:	d1f8      	bne.n	1362 <z_log_dropped+0x1e>
    1370:	f3bf 8f5b 	dmb	ish
}
    1374:	4770      	bx	lr
    1376:	bf00      	nop
    1378:	2000041c 	.word	0x2000041c
    137c:	20000418 	.word	0x20000418

00001380 <z_log_dropped_read_and_clear>:
{
	/* This builtin, as described by Intel, is not a traditional
	 * test-and-set operation, but rather an atomic exchange operation. It
	 * writes value into *ptr, and returns the previous contents of *ptr.
	 */
	return __atomic_exchange_n(target, value, __ATOMIC_SEQ_CST);
    1380:	4b06      	ldr	r3, [pc, #24]	; (139c <z_log_dropped_read_and_clear+0x1c>)
}
    1382:	2000      	movs	r0, #0
    1384:	4602      	mov	r2, r0
    1386:	f3bf 8f5b 	dmb	ish
    138a:	e853 0f00 	ldrex	r0, [r3]
    138e:	e843 2100 	strex	r1, r2, [r3]
    1392:	2900      	cmp	r1, #0
    1394:	d1f9      	bne.n	138a <z_log_dropped_read_and_clear+0xa>
    1396:	f3bf 8f5b 	dmb	ish
    139a:	4770      	bx	lr
    139c:	2000041c 	.word	0x2000041c

000013a0 <dropped_notify>:
{
    13a0:	b538      	push	{r3, r4, r5, lr}
	uint32_t dropped = z_log_dropped_read_and_clear();
    13a2:	f7ff ffed 	bl	1380 <z_log_dropped_read_and_clear>
    13a6:	4605      	mov	r5, r0
	for (int i = 0; i < log_backend_count_get(); i++) {
    13a8:	2400      	movs	r4, #0
    13aa:	e000      	b.n	13ae <dropped_notify+0xe>
    13ac:	3401      	adds	r4, #1
    13ae:	4b0b      	ldr	r3, [pc, #44]	; (13dc <dropped_notify+0x3c>)
    13b0:	4a0b      	ldr	r2, [pc, #44]	; (13e0 <dropped_notify+0x40>)
    13b2:	1a9b      	subs	r3, r3, r2
    13b4:	ebb4 1f23 	cmp.w	r4, r3, asr #4
    13b8:	da0f      	bge.n	13da <dropped_notify+0x3a>
    13ba:	4809      	ldr	r0, [pc, #36]	; (13e0 <dropped_notify+0x40>)
    13bc:	eb00 1004 	add.w	r0, r0, r4, lsl #4
 */
static inline bool log_backend_is_active(
				const struct log_backend *const backend)
{
	__ASSERT_NO_MSG(backend != NULL);
	return backend->cb->active;
    13c0:	6843      	ldr	r3, [r0, #4]
    13c2:	795b      	ldrb	r3, [r3, #5]
		if (log_backend_is_active(backend)) {
    13c4:	2b00      	cmp	r3, #0
    13c6:	d0f1      	beq.n	13ac <dropped_notify+0xc>
	if (backend->api->dropped != NULL) {
    13c8:	0123      	lsls	r3, r4, #4
    13ca:	4a05      	ldr	r2, [pc, #20]	; (13e0 <dropped_notify+0x40>)
    13cc:	58d3      	ldr	r3, [r2, r3]
    13ce:	691b      	ldr	r3, [r3, #16]
    13d0:	2b00      	cmp	r3, #0
    13d2:	d0eb      	beq.n	13ac <dropped_notify+0xc>
		backend->api->dropped(backend, cnt);
    13d4:	4629      	mov	r1, r5
    13d6:	4798      	blx	r3
    13d8:	e7e8      	b.n	13ac <dropped_notify+0xc>
}
    13da:	bd38      	pop	{r3, r4, r5, pc}
    13dc:	00008414 	.word	0x00008414
    13e0:	000083f4 	.word	0x000083f4

000013e4 <z_log_dropped_pending>:
	return dropped_cnt > 0;
    13e4:	4b03      	ldr	r3, [pc, #12]	; (13f4 <z_log_dropped_pending+0x10>)
    13e6:	6818      	ldr	r0, [r3, #0]
}
    13e8:	2800      	cmp	r0, #0
    13ea:	bfd4      	ite	le
    13ec:	2000      	movle	r0, #0
    13ee:	2001      	movgt	r0, #1
    13f0:	4770      	bx	lr
    13f2:	bf00      	nop
    13f4:	2000041c 	.word	0x2000041c

000013f8 <z_log_strdup>:
{
    13f8:	b570      	push	{r4, r5, r6, lr}
    13fa:	b082      	sub	sp, #8
    13fc:	4604      	mov	r4, r0
	    is_rodata(str) || k_is_user_context()) {
    13fe:	f7ff fe95 	bl	112c <is_rodata>
	if (IS_ENABLED(CONFIG_LOG_IMMEDIATE) ||
    1402:	bb10      	cbnz	r0, 144a <z_log_strdup+0x52>
	err = k_mem_slab_alloc(&log_strdup_pool, (void **)&dup, K_NO_WAIT);
    1404:	2200      	movs	r2, #0
    1406:	2300      	movs	r3, #0
    1408:	a901      	add	r1, sp, #4
    140a:	4811      	ldr	r0, [pc, #68]	; (1450 <z_log_strdup+0x58>)
    140c:	f004 f82c 	bl	5468 <k_mem_slab_alloc>
	if (err != 0) {
    1410:	b108      	cbz	r0, 1416 <z_log_strdup+0x1e>
		return (char *)log_strdup_fail_msg;
    1412:	4c10      	ldr	r4, [pc, #64]	; (1454 <z_log_strdup+0x5c>)
    1414:	e019      	b.n	144a <z_log_strdup+0x52>
	(void)atomic_set(&dup->refcount, 1);
    1416:	9b01      	ldr	r3, [sp, #4]
    1418:	2201      	movs	r2, #1
    141a:	f3bf 8f5b 	dmb	ish
    141e:	e853 1f00 	ldrex	r1, [r3]
    1422:	e843 2000 	strex	r0, r2, [r3]
    1426:	2800      	cmp	r0, #0
    1428:	d1f9      	bne.n	141e <z_log_strdup+0x26>
    142a:	f3bf 8f5b 	dmb	ish
	strncpy(dup->buf, str, sizeof(dup->buf) - 2);
    142e:	9d01      	ldr	r5, [sp, #4]
    1430:	1d2e      	adds	r6, r5, #4
#if __GNUC_PREREQ__(4,8) || defined(__clang__)
__ssp_bos_icheck3_restrict(stpncpy, char *, const char *)
#endif
__ssp_bos_icheck2_restrict(strcpy, char *, const char *)
__ssp_bos_icheck2_restrict(strcat, char *, const char *)
__ssp_bos_icheck3_restrict(strncpy, char *, const char *)
    1432:	221f      	movs	r2, #31
    1434:	4621      	mov	r1, r4
    1436:	4630      	mov	r0, r6
    1438:	f006 fe35 	bl	80a6 <strncpy>
	dup->buf[sizeof(dup->buf) - 2] = '~';
    143c:	237e      	movs	r3, #126	; 0x7e
    143e:	f885 3023 	strb.w	r3, [r5, #35]	; 0x23
	dup->buf[sizeof(dup->buf) - 1] = '\0';
    1442:	2300      	movs	r3, #0
    1444:	f885 3024 	strb.w	r3, [r5, #36]	; 0x24
	return dup->buf;
    1448:	4634      	mov	r4, r6
}
    144a:	4620      	mov	r0, r4
    144c:	b002      	add	sp, #8
    144e:	bd70      	pop	{r4, r5, r6, pc}
    1450:	2000042c 	.word	0x2000042c
    1454:	00008510 	.word	0x00008510

00001458 <log_is_strdup>:
	return PART_OF_ARRAY(log_strdup_pool_buf, (uint8_t *)buf);
    1458:	b138      	cbz	r0, 146a <log_is_strdup+0x12>
    145a:	4a07      	ldr	r2, [pc, #28]	; (1478 <log_is_strdup+0x20>)
    145c:	4290      	cmp	r0, r2
    145e:	d306      	bcc.n	146e <log_is_strdup+0x16>
    1460:	32a0      	adds	r2, #160	; 0xa0
    1462:	4290      	cmp	r0, r2
    1464:	d305      	bcc.n	1472 <log_is_strdup+0x1a>
    1466:	2000      	movs	r0, #0
    1468:	4770      	bx	lr
    146a:	2000      	movs	r0, #0
    146c:	4770      	bx	lr
    146e:	2000      	movs	r0, #0
    1470:	4770      	bx	lr
    1472:	2001      	movs	r0, #1
}
    1474:	4770      	bx	lr
    1476:	bf00      	nop
    1478:	20001fd0 	.word	0x20001fd0

0000147c <detect_missed_strdup>:
 * @retval true  Standard message.
 * @retval false Hexdump message.
 */
static inline bool log_msg_is_std(struct log_msg *msg)
{
	return  (msg->hdr.params.generic.type == LOG_MSG_TYPE_STD);
    147c:	7a03      	ldrb	r3, [r0, #8]
	if (!log_msg_is_std(msg)) {
    147e:	f013 0f01 	tst.w	r3, #1
    1482:	d000      	beq.n	1486 <detect_missed_strdup+0xa>
    1484:	4770      	bx	lr
{
    1486:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
    148a:	b083      	sub	sp, #12
    148c:	4606      	mov	r6, r0
	msg_str = log_msg_str_get(msg);
    148e:	f005 fcc2 	bl	6e16 <log_msg_str_get>
    1492:	4607      	mov	r7, r0
	mask = z_log_get_s_mask(msg_str, log_msg_nargs_get(msg));
    1494:	4630      	mov	r0, r6
    1496:	f005 fca9 	bl	6dec <log_msg_nargs_get>
    149a:	4601      	mov	r1, r0
    149c:	4638      	mov	r0, r7
    149e:	f7ff fea9 	bl	11f4 <z_log_get_s_mask>
    14a2:	4605      	mov	r5, r0
	while (mask) {
    14a4:	e004      	b.n	14b0 <detect_missed_strdup+0x34>
		mask &= ~BIT(idx);
    14a6:	2301      	movs	r3, #1
    14a8:	fa03 f404 	lsl.w	r4, r3, r4
    14ac:	ea25 0504 	bic.w	r5, r5, r4
	while (mask) {
    14b0:	b36d      	cbz	r5, 150e <detect_missed_strdup+0x92>
		idx = 31 - __builtin_clz(mask);
    14b2:	fab5 f485 	clz	r4, r5
    14b6:	f1c4 041f 	rsb	r4, r4, #31
		str = (const char *)log_msg_arg_get(msg, idx);
    14ba:	4621      	mov	r1, r4
    14bc:	4630      	mov	r0, r6
    14be:	f005 fc98 	bl	6df2 <log_msg_arg_get>
    14c2:	4681      	mov	r9, r0
		if (!is_rodata(str) && !log_is_strdup(str) &&
    14c4:	f7ff fe32 	bl	112c <is_rodata>
    14c8:	2800      	cmp	r0, #0
    14ca:	d1ec      	bne.n	14a6 <detect_missed_strdup+0x2a>
    14cc:	4648      	mov	r0, r9
    14ce:	f7ff ffc3 	bl	1458 <log_is_strdup>
    14d2:	2800      	cmp	r0, #0
    14d4:	d1e7      	bne.n	14a6 <detect_missed_strdup+0x2a>
    14d6:	4b0f      	ldr	r3, [pc, #60]	; (1514 <detect_missed_strdup+0x98>)
    14d8:	4599      	cmp	r9, r3
    14da:	d0e4      	beq.n	14a6 <detect_missed_strdup+0x2a>
	return msg->hdr.ids.source_id;
    14dc:	8971      	ldrh	r1, [r6, #10]
				log_source_name_get(CONFIG_LOG_DOMAIN_ID,
    14de:	f3c1 1189 	ubfx	r1, r1, #6, #10
    14e2:	f000 fa05 	bl	18f0 <log_source_name_get>
    14e6:	4602      	mov	r2, r0
    14e8:	4b0b      	ldr	r3, [pc, #44]	; (1518 <detect_missed_strdup+0x9c>)
    14ea:	490c      	ldr	r1, [pc, #48]	; (151c <detect_missed_strdup+0xa0>)
    14ec:	1a5b      	subs	r3, r3, r1
    14ee:	08db      	lsrs	r3, r3, #3
				LOG_ERR(ERR_MSG, idx, src_name, msg_str);
    14f0:	2101      	movs	r1, #1
    14f2:	f361 0802 	bfi	r8, r1, #0, #3
    14f6:	f36f 08c5 	bfc	r8, #3, #3
    14fa:	f363 188f 	bfi	r8, r3, #6, #10
    14fe:	f8ad 8000 	strh.w	r8, [sp]
    1502:	463b      	mov	r3, r7
    1504:	4621      	mov	r1, r4
    1506:	4806      	ldr	r0, [pc, #24]	; (1520 <detect_missed_strdup+0xa4>)
    1508:	f000 f8b2 	bl	1670 <log_3>
    150c:	e7cb      	b.n	14a6 <detect_missed_strdup+0x2a>
}
    150e:	b003      	add	sp, #12
    1510:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
    1514:	00008510 	.word	0x00008510
    1518:	000083c4 	.word	0x000083c4
    151c:	0000839c 	.word	0x0000839c
    1520:	0000852c 	.word	0x0000852c

00001524 <msg_process>:
{
    1524:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    1526:	4606      	mov	r6, r0
	if (!bypass) {
    1528:	bb19      	cbnz	r1, 1572 <msg_process+0x4e>
		    !panic_mode) {
    152a:	4b14      	ldr	r3, [pc, #80]	; (157c <msg_process+0x58>)
    152c:	781b      	ldrb	r3, [r3, #0]
		if (!IS_ENABLED(CONFIG_LOG2) &&
    152e:	b10b      	cbz	r3, 1534 <msg_process+0x10>
{
    1530:	2400      	movs	r4, #0
    1532:	e003      	b.n	153c <msg_process+0x18>
			detect_missed_strdup(msg.msg);
    1534:	f7ff ffa2 	bl	147c <detect_missed_strdup>
    1538:	e7fa      	b.n	1530 <msg_process+0xc>
		for (int i = 0; i < log_backend_count_get(); i++) {
    153a:	3401      	adds	r4, #1
    153c:	4b10      	ldr	r3, [pc, #64]	; (1580 <msg_process+0x5c>)
    153e:	4a11      	ldr	r2, [pc, #68]	; (1584 <msg_process+0x60>)
    1540:	1a9b      	subs	r3, r3, r2
    1542:	ebb4 1f23 	cmp.w	r4, r3, asr #4
    1546:	da14      	bge.n	1572 <msg_process+0x4e>
	return &__log_backends_start[idx];
    1548:	4d0e      	ldr	r5, [pc, #56]	; (1584 <msg_process+0x60>)
    154a:	eb05 1504 	add.w	r5, r5, r4, lsl #4
	return backend->cb->active;
    154e:	686b      	ldr	r3, [r5, #4]
    1550:	795b      	ldrb	r3, [r3, #5]
			if (log_backend_is_active(backend) &&
    1552:	2b00      	cmp	r3, #0
    1554:	d0f1      	beq.n	153a <msg_process+0x16>
			    msg_filter_check(backend, msg)) {
    1556:	4631      	mov	r1, r6
    1558:	4628      	mov	r0, r5
    155a:	f005 fbc1 	bl	6ce0 <msg_filter_check>
			if (log_backend_is_active(backend) &&
    155e:	2800      	cmp	r0, #0
    1560:	d0eb      	beq.n	153a <msg_process+0x16>
	backend->api->put(backend, msg);
    1562:	0127      	lsls	r7, r4, #4
    1564:	4b07      	ldr	r3, [pc, #28]	; (1584 <msg_process+0x60>)
    1566:	59db      	ldr	r3, [r3, r7]
    1568:	685b      	ldr	r3, [r3, #4]
    156a:	4631      	mov	r1, r6
    156c:	4628      	mov	r0, r5
    156e:	4798      	blx	r3
}
    1570:	e7e3      	b.n	153a <msg_process+0x16>
			log_msg_put(msg.msg);
    1572:	4630      	mov	r0, r6
    1574:	f005 fc51 	bl	6e1a <log_msg_put>
}
    1578:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    157a:	bf00      	nop
    157c:	20000b83 	.word	0x20000b83
    1580:	00008414 	.word	0x00008414
    1584:	000083f4 	.word	0x000083f4

00001588 <z_impl_log_process>:
{
    1588:	b510      	push	{r4, lr}
    158a:	4604      	mov	r4, r0
	if (!backend_attached && !bypass) {
    158c:	4b10      	ldr	r3, [pc, #64]	; (15d0 <z_impl_log_process+0x48>)
    158e:	781b      	ldrb	r3, [r3, #0]
    1590:	b903      	cbnz	r3, 1594 <z_impl_log_process+0xc>
    1592:	b1c8      	cbz	r0, 15c8 <z_impl_log_process+0x40>
	msg = get_msg();
    1594:	f7ff feb2 	bl	12fc <get_msg>
	if (msg.msg) {
    1598:	4602      	mov	r2, r0
    159a:	b178      	cbz	r0, 15bc <z_impl_log_process+0x34>
	return __atomic_fetch_sub(target, value, __ATOMIC_SEQ_CST);
    159c:	4b0d      	ldr	r3, [pc, #52]	; (15d4 <z_impl_log_process+0x4c>)
    159e:	f3bf 8f5b 	dmb	ish
    15a2:	e853 1f00 	ldrex	r1, [r3]
    15a6:	3901      	subs	r1, #1
    15a8:	e843 1000 	strex	r0, r1, [r3]
    15ac:	2800      	cmp	r0, #0
    15ae:	d1f8      	bne.n	15a2 <z_impl_log_process+0x1a>
    15b0:	f3bf 8f5b 	dmb	ish
		msg_process(msg, bypass);
    15b4:	4621      	mov	r1, r4
    15b6:	4610      	mov	r0, r2
    15b8:	f7ff ffb4 	bl	1524 <msg_process>
	if (!bypass && z_log_dropped_pending()) {
    15bc:	b914      	cbnz	r4, 15c4 <z_impl_log_process+0x3c>
    15be:	f7ff ff11 	bl	13e4 <z_log_dropped_pending>
    15c2:	b910      	cbnz	r0, 15ca <z_impl_log_process+0x42>
	return next_pending();
    15c4:	f7ff fdde 	bl	1184 <next_pending>
}
    15c8:	bd10      	pop	{r4, pc}
		dropped_notify();
    15ca:	f7ff fee9 	bl	13a0 <dropped_notify>
    15ce:	e7f9      	b.n	15c4 <z_impl_log_process+0x3c>
    15d0:	20000b82 	.word	0x20000b82
    15d4:	20000418 	.word	0x20000418

000015d8 <z_log_msg_post_finalize>:
{
    15d8:	b510      	push	{r4, lr}
    15da:	b082      	sub	sp, #8
	return __atomic_fetch_add(target, value, __ATOMIC_SEQ_CST);
    15dc:	4b1f      	ldr	r3, [pc, #124]	; (165c <z_log_msg_post_finalize+0x84>)
    15de:	f3bf 8f5b 	dmb	ish
    15e2:	e853 2f00 	ldrex	r2, [r3]
    15e6:	3201      	adds	r2, #1
    15e8:	e843 2100 	strex	r1, r2, [r3]
    15ec:	2900      	cmp	r1, #0
    15ee:	d1f8      	bne.n	15e2 <z_log_msg_post_finalize+0xa>
    15f0:	f3bf 8f5b 	dmb	ish
	if (panic_mode) {
    15f4:	4b1a      	ldr	r3, [pc, #104]	; (1660 <z_log_msg_post_finalize+0x88>)
    15f6:	781b      	ldrb	r3, [r3, #0]
    15f8:	b963      	cbnz	r3, 1614 <z_log_msg_post_finalize+0x3c>
	} else if (proc_tid != NULL && buffered_cnt == 1) {
    15fa:	4b1a      	ldr	r3, [pc, #104]	; (1664 <z_log_msg_post_finalize+0x8c>)
    15fc:	681b      	ldr	r3, [r3, #0]
    15fe:	b11b      	cbz	r3, 1608 <z_log_msg_post_finalize+0x30>
    1600:	4a16      	ldr	r2, [pc, #88]	; (165c <z_log_msg_post_finalize+0x84>)
    1602:	6812      	ldr	r2, [r2, #0]
    1604:	2a01      	cmp	r2, #1
    1606:	d015      	beq.n	1634 <z_log_msg_post_finalize+0x5c>
		if ((buffered_cnt == CONFIG_LOG_PROCESS_TRIGGER_THRESHOLD) &&
    1608:	4a14      	ldr	r2, [pc, #80]	; (165c <z_log_msg_post_finalize+0x84>)
    160a:	6812      	ldr	r2, [r2, #0]
    160c:	2a0a      	cmp	r2, #10
    160e:	d01c      	beq.n	164a <z_log_msg_post_finalize+0x72>
}
    1610:	b002      	add	sp, #8
    1612:	bd10      	pop	{r4, pc}
	__asm__ volatile(
    1614:	f04f 0320 	mov.w	r3, #32
    1618:	f3ef 8411 	mrs	r4, BASEPRI
    161c:	f383 8812 	msr	BASEPRI_MAX, r3
    1620:	f3bf 8f6f 	isb	sy
		/* coverity[OVERRUN] */
		return (bool) arch_syscall_invoke1(*(uintptr_t *)&bypass, K_SYSCALL_LOG_PROCESS);
	}
#endif
	compiler_barrier();
	return z_impl_log_process(bypass);
    1624:	2000      	movs	r0, #0
    1626:	f7ff ffaf 	bl	1588 <z_impl_log_process>
	__asm__ volatile(
    162a:	f384 8811 	msr	BASEPRI, r4
    162e:	f3bf 8f6f 	isb	sy
		"cpsie i;"
		: : : "memory", "cc");
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
}
    1632:	e7ed      	b.n	1610 <z_log_msg_post_finalize+0x38>
	z_impl_k_timer_start(timer, duration, period);
    1634:	2200      	movs	r2, #0
    1636:	2300      	movs	r3, #0
    1638:	e9cd 2300 	strd	r2, r3, [sp]
    163c:	f44f 4200 	mov.w	r2, #32768	; 0x8000
    1640:	2300      	movs	r3, #0
    1642:	4809      	ldr	r0, [pc, #36]	; (1668 <z_log_msg_post_finalize+0x90>)
    1644:	f005 f8a4 	bl	6790 <z_impl_k_timer_start>
	} else if (proc_tid != NULL && buffered_cnt == 1) {
    1648:	e7e2      	b.n	1610 <z_log_msg_post_finalize+0x38>
		if ((buffered_cnt == CONFIG_LOG_PROCESS_TRIGGER_THRESHOLD) &&
    164a:	2b00      	cmp	r3, #0
    164c:	d0e0      	beq.n	1610 <z_log_msg_post_finalize+0x38>
	z_impl_k_timer_stop(timer);
    164e:	4806      	ldr	r0, [pc, #24]	; (1668 <z_log_msg_post_finalize+0x90>)
    1650:	f006 fcf3 	bl	803a <z_impl_k_timer_stop>
	z_impl_k_sem_give(sem);
    1654:	4805      	ldr	r0, [pc, #20]	; (166c <z_log_msg_post_finalize+0x94>)
    1656:	f004 f90f 	bl	5878 <z_impl_k_sem_give>
}
    165a:	e7d9      	b.n	1610 <z_log_msg_post_finalize+0x38>
    165c:	20000418 	.word	0x20000418
    1660:	20000b83 	.word	0x20000b83
    1664:	2000044c 	.word	0x2000044c
    1668:	200000d8 	.word	0x200000d8
    166c:	200000c4 	.word	0x200000c4

00001670 <log_3>:
{
    1670:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    1674:	4680      	mov	r8, r0
    1676:	460f      	mov	r7, r1
    1678:	4616      	mov	r6, r2
    167a:	461d      	mov	r5, r3
 *
 *  @return Allocated chunk of NULL.
 */
static inline struct log_msg *z_log_msg_std_alloc(void)
{
	struct  log_msg *msg = (struct  log_msg *)log_msg_chunk_alloc();
    167c:	f000 f98e 	bl	199c <log_msg_chunk_alloc>

	if (msg != NULL) {
    1680:	4604      	mov	r4, r0
    1682:	b140      	cbz	r0, 1696 <log_3+0x26>
		/* all fields reset to 0, reference counter to 1 */
		msg->hdr.ref_cnt = 1;
    1684:	2301      	movs	r3, #1
    1686:	6043      	str	r3, [r0, #4]
		msg->hdr.params.raw = 0U;
    1688:	2200      	movs	r2, #0
    168a:	8102      	strh	r2, [r0, #8]
		msg->hdr.params.std.type = LOG_MSG_TYPE_STD;
    168c:	f04f 0300 	mov.w	r3, #0
    1690:	f362 0300 	bfi	r3, r2, #0, #1
    1694:	7203      	strb	r3, [r0, #8]
					       log_arg_t arg2,
					       log_arg_t arg3)
{
	struct  log_msg *msg = z_log_msg_std_alloc();

	if (msg != NULL) {
    1696:	b14c      	cbz	r4, 16ac <log_3+0x3c>
		msg->str = str;
    1698:	f8c4 8010 	str.w	r8, [r4, #16]
		msg->hdr.params.std.nargs = 3U;
    169c:	7a63      	ldrb	r3, [r4, #9]
    169e:	2203      	movs	r2, #3
    16a0:	f362 1307 	bfi	r3, r2, #4, #4
    16a4:	7263      	strb	r3, [r4, #9]
		msg->payload.single.args[0] = arg1;
    16a6:	6167      	str	r7, [r4, #20]
		msg->payload.single.args[1] = arg2;
    16a8:	61a6      	str	r6, [r4, #24]
		msg->payload.single.args[2] = arg3;
    16aa:	61e5      	str	r5, [r4, #28]
		if (msg == NULL) {
    16ac:	b1c4      	cbz	r4, 16e0 <log_3+0x70>
	msg->hdr.ids = src_level;
    16ae:	f8bd 3018 	ldrh.w	r3, [sp, #24]
    16b2:	8163      	strh	r3, [r4, #10]
	msg->hdr.timestamp = timestamp_func();
    16b4:	4b0b      	ldr	r3, [pc, #44]	; (16e4 <log_3+0x74>)
    16b6:	681b      	ldr	r3, [r3, #0]
    16b8:	4798      	blx	r3
    16ba:	60e0      	str	r0, [r4, #12]
	__asm__ volatile(
    16bc:	f04f 0320 	mov.w	r3, #32
    16c0:	f3ef 8511 	mrs	r5, BASEPRI
    16c4:	f383 8812 	msr	BASEPRI_MAX, r3
    16c8:	f3bf 8f6f 	isb	sy
	log_list_add_tail(&list, msg);
    16cc:	4621      	mov	r1, r4
    16ce:	4806      	ldr	r0, [pc, #24]	; (16e8 <log_3+0x78>)
    16d0:	f005 faf2 	bl	6cb8 <log_list_add_tail>
	__asm__ volatile(
    16d4:	f385 8811 	msr	BASEPRI, r5
    16d8:	f3bf 8f6f 	isb	sy
	z_log_msg_post_finalize();
    16dc:	f7ff ff7c 	bl	15d8 <z_log_msg_post_finalize>
}
    16e0:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    16e4:	20000004 	.word	0x20000004
    16e8:	20000424 	.word	0x20000424

000016ec <log_1>:
{
    16ec:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    16ee:	4606      	mov	r6, r0
    16f0:	460d      	mov	r5, r1
    16f2:	4617      	mov	r7, r2
	struct  log_msg *msg = (struct  log_msg *)log_msg_chunk_alloc();
    16f4:	f000 f952 	bl	199c <log_msg_chunk_alloc>
	if (msg != NULL) {
    16f8:	4604      	mov	r4, r0
    16fa:	b140      	cbz	r0, 170e <log_1+0x22>
		msg->hdr.ref_cnt = 1;
    16fc:	2301      	movs	r3, #1
    16fe:	6043      	str	r3, [r0, #4]
		msg->hdr.params.raw = 0U;
    1700:	2100      	movs	r1, #0
    1702:	8101      	strh	r1, [r0, #8]
		msg->hdr.params.std.type = LOG_MSG_TYPE_STD;
    1704:	f04f 0300 	mov.w	r3, #0
    1708:	f361 0300 	bfi	r3, r1, #0, #1
    170c:	7203      	strb	r3, [r0, #8]
	if (msg != NULL) {
    170e:	b134      	cbz	r4, 171e <log_1+0x32>
		msg->str = str;
    1710:	6126      	str	r6, [r4, #16]
		msg->hdr.params.std.nargs = 1U;
    1712:	7a63      	ldrb	r3, [r4, #9]
    1714:	2201      	movs	r2, #1
    1716:	f362 1307 	bfi	r3, r2, #4, #4
    171a:	7263      	strb	r3, [r4, #9]
		msg->payload.single.args[0] = arg1;
    171c:	6165      	str	r5, [r4, #20]
		if (msg == NULL) {
    171e:	b1b4      	cbz	r4, 174e <log_1+0x62>
	msg->hdr.ids = src_level;
    1720:	8167      	strh	r7, [r4, #10]
	msg->hdr.timestamp = timestamp_func();
    1722:	4b0b      	ldr	r3, [pc, #44]	; (1750 <log_1+0x64>)
    1724:	681b      	ldr	r3, [r3, #0]
    1726:	4798      	blx	r3
    1728:	60e0      	str	r0, [r4, #12]
	__asm__ volatile(
    172a:	f04f 0320 	mov.w	r3, #32
    172e:	f3ef 8511 	mrs	r5, BASEPRI
    1732:	f383 8812 	msr	BASEPRI_MAX, r3
    1736:	f3bf 8f6f 	isb	sy
	log_list_add_tail(&list, msg);
    173a:	4621      	mov	r1, r4
    173c:	4805      	ldr	r0, [pc, #20]	; (1754 <log_1+0x68>)
    173e:	f005 fabb 	bl	6cb8 <log_list_add_tail>
	__asm__ volatile(
    1742:	f385 8811 	msr	BASEPRI, r5
    1746:	f3bf 8f6f 	isb	sy
	z_log_msg_post_finalize();
    174a:	f7ff ff45 	bl	15d8 <z_log_msg_post_finalize>
}
    174e:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    1750:	20000004 	.word	0x20000004
    1754:	20000424 	.word	0x20000424

00001758 <log_2>:
{
    1758:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    175c:	4607      	mov	r7, r0
    175e:	460e      	mov	r6, r1
    1760:	4615      	mov	r5, r2
    1762:	4698      	mov	r8, r3
	struct  log_msg *msg = (struct  log_msg *)log_msg_chunk_alloc();
    1764:	f000 f91a 	bl	199c <log_msg_chunk_alloc>
	if (msg != NULL) {
    1768:	4604      	mov	r4, r0
    176a:	b140      	cbz	r0, 177e <log_2+0x26>
		msg->hdr.ref_cnt = 1;
    176c:	2301      	movs	r3, #1
    176e:	6043      	str	r3, [r0, #4]
		msg->hdr.params.raw = 0U;
    1770:	2200      	movs	r2, #0
    1772:	8102      	strh	r2, [r0, #8]
		msg->hdr.params.std.type = LOG_MSG_TYPE_STD;
    1774:	f04f 0300 	mov.w	r3, #0
    1778:	f362 0300 	bfi	r3, r2, #0, #1
    177c:	7203      	strb	r3, [r0, #8]
	if (msg != NULL) {
    177e:	b13c      	cbz	r4, 1790 <log_2+0x38>
		msg->str = str;
    1780:	6127      	str	r7, [r4, #16]
		msg->hdr.params.std.nargs = 2U;
    1782:	7a63      	ldrb	r3, [r4, #9]
    1784:	2202      	movs	r2, #2
    1786:	f362 1307 	bfi	r3, r2, #4, #4
    178a:	7263      	strb	r3, [r4, #9]
		msg->payload.single.args[0] = arg1;
    178c:	6166      	str	r6, [r4, #20]
		msg->payload.single.args[1] = arg2;
    178e:	61a5      	str	r5, [r4, #24]
		if (msg == NULL) {
    1790:	b1bc      	cbz	r4, 17c2 <log_2+0x6a>
	msg->hdr.ids = src_level;
    1792:	f8a4 800a 	strh.w	r8, [r4, #10]
	msg->hdr.timestamp = timestamp_func();
    1796:	4b0c      	ldr	r3, [pc, #48]	; (17c8 <log_2+0x70>)
    1798:	681b      	ldr	r3, [r3, #0]
    179a:	4798      	blx	r3
    179c:	60e0      	str	r0, [r4, #12]
	__asm__ volatile(
    179e:	f04f 0320 	mov.w	r3, #32
    17a2:	f3ef 8511 	mrs	r5, BASEPRI
    17a6:	f383 8812 	msr	BASEPRI_MAX, r3
    17aa:	f3bf 8f6f 	isb	sy
	log_list_add_tail(&list, msg);
    17ae:	4621      	mov	r1, r4
    17b0:	4806      	ldr	r0, [pc, #24]	; (17cc <log_2+0x74>)
    17b2:	f005 fa81 	bl	6cb8 <log_list_add_tail>
	__asm__ volatile(
    17b6:	f385 8811 	msr	BASEPRI, r5
    17ba:	f3bf 8f6f 	isb	sy
	z_log_msg_post_finalize();
    17be:	f7ff ff0b 	bl	15d8 <z_log_msg_post_finalize>
}
    17c2:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    17c6:	bf00      	nop
    17c8:	20000004 	.word	0x20000004
    17cc:	20000424 	.word	0x20000424

000017d0 <log_0>:
{
    17d0:	b570      	push	{r4, r5, r6, lr}
    17d2:	4605      	mov	r5, r0
    17d4:	460e      	mov	r6, r1
	struct  log_msg *msg = (struct  log_msg *)log_msg_chunk_alloc();
    17d6:	f000 f8e1 	bl	199c <log_msg_chunk_alloc>
	if (msg != NULL) {
    17da:	4604      	mov	r4, r0
    17dc:	b140      	cbz	r0, 17f0 <log_0+0x20>
		msg->hdr.ref_cnt = 1;
    17de:	2301      	movs	r3, #1
    17e0:	6043      	str	r3, [r0, #4]
		msg->hdr.params.raw = 0U;
    17e2:	2200      	movs	r2, #0
    17e4:	8102      	strh	r2, [r0, #8]
		msg->hdr.params.std.type = LOG_MSG_TYPE_STD;
    17e6:	f04f 0300 	mov.w	r3, #0
    17ea:	f362 0300 	bfi	r3, r2, #0, #1
    17ee:	7203      	strb	r3, [r0, #8]
	if (msg != NULL) {
    17f0:	b104      	cbz	r4, 17f4 <log_0+0x24>
		msg->str = str;
    17f2:	6125      	str	r5, [r4, #16]
		if (msg == NULL) {
    17f4:	b1b4      	cbz	r4, 1824 <log_0+0x54>
	msg->hdr.ids = src_level;
    17f6:	8166      	strh	r6, [r4, #10]
	msg->hdr.timestamp = timestamp_func();
    17f8:	4b0b      	ldr	r3, [pc, #44]	; (1828 <log_0+0x58>)
    17fa:	681b      	ldr	r3, [r3, #0]
    17fc:	4798      	blx	r3
    17fe:	60e0      	str	r0, [r4, #12]
	__asm__ volatile(
    1800:	f04f 0320 	mov.w	r3, #32
    1804:	f3ef 8511 	mrs	r5, BASEPRI
    1808:	f383 8812 	msr	BASEPRI_MAX, r3
    180c:	f3bf 8f6f 	isb	sy
	log_list_add_tail(&list, msg);
    1810:	4621      	mov	r1, r4
    1812:	4806      	ldr	r0, [pc, #24]	; (182c <log_0+0x5c>)
    1814:	f005 fa50 	bl	6cb8 <log_list_add_tail>
	__asm__ volatile(
    1818:	f385 8811 	msr	BASEPRI, r5
    181c:	f3bf 8f6f 	isb	sy
	z_log_msg_post_finalize();
    1820:	f7ff feda 	bl	15d8 <z_log_msg_post_finalize>
}
    1824:	bd70      	pop	{r4, r5, r6, pc}
    1826:	bf00      	nop
    1828:	20000004 	.word	0x20000004
    182c:	20000424 	.word	0x20000424

00001830 <z_impl_log_panic>:
	if (panic_mode) {
    1830:	4b12      	ldr	r3, [pc, #72]	; (187c <z_impl_log_panic+0x4c>)
    1832:	781b      	ldrb	r3, [r3, #0]
    1834:	b103      	cbz	r3, 1838 <z_impl_log_panic+0x8>
    1836:	4770      	bx	lr
{
    1838:	b510      	push	{r4, lr}
	log_init();
    183a:	f7ff fd27 	bl	128c <log_init>
	for (int i = 0; i < log_backend_count_get(); i++) {
    183e:	2400      	movs	r4, #0
    1840:	e000      	b.n	1844 <z_impl_log_panic+0x14>
    1842:	3401      	adds	r4, #1
    1844:	4b0e      	ldr	r3, [pc, #56]	; (1880 <z_impl_log_panic+0x50>)
    1846:	4a0f      	ldr	r2, [pc, #60]	; (1884 <z_impl_log_panic+0x54>)
    1848:	1a9b      	subs	r3, r3, r2
    184a:	ebb4 1f23 	cmp.w	r4, r3, asr #4
    184e:	da0c      	bge.n	186a <z_impl_log_panic+0x3a>
	return &__log_backends_start[idx];
    1850:	480c      	ldr	r0, [pc, #48]	; (1884 <z_impl_log_panic+0x54>)
    1852:	eb00 1004 	add.w	r0, r0, r4, lsl #4
	return backend->cb->active;
    1856:	6843      	ldr	r3, [r0, #4]
    1858:	795b      	ldrb	r3, [r3, #5]
		if (log_backend_is_active(backend)) {
    185a:	2b00      	cmp	r3, #0
    185c:	d0f1      	beq.n	1842 <z_impl_log_panic+0x12>
	backend->api->panic(backend);
    185e:	0123      	lsls	r3, r4, #4
    1860:	4a08      	ldr	r2, [pc, #32]	; (1884 <z_impl_log_panic+0x54>)
    1862:	58d3      	ldr	r3, [r2, r3]
    1864:	695b      	ldr	r3, [r3, #20]
    1866:	4798      	blx	r3
}
    1868:	e7eb      	b.n	1842 <z_impl_log_panic+0x12>
    186a:	2000      	movs	r0, #0
    186c:	f7ff fe8c 	bl	1588 <z_impl_log_process>
		while (log_process(false) == true) {
    1870:	2800      	cmp	r0, #0
    1872:	d1fa      	bne.n	186a <z_impl_log_panic+0x3a>
	panic_mode = true;
    1874:	4b01      	ldr	r3, [pc, #4]	; (187c <z_impl_log_panic+0x4c>)
    1876:	2201      	movs	r2, #1
    1878:	701a      	strb	r2, [r3, #0]
}
    187a:	bd10      	pop	{r4, pc}
    187c:	20000b83 	.word	0x20000b83
    1880:	00008414 	.word	0x00008414
    1884:	000083f4 	.word	0x000083f4

00001888 <log_process_thread_func>:
{
    1888:	b508      	push	{r3, lr}
	log_init();
    188a:	f7ff fcff 	bl	128c <log_init>
	return z_impl_z_current_get();
    188e:	f004 fd65 	bl	635c <z_impl_z_current_get>
	thread_set(k_current_get());
    1892:	f7ff fc5b 	bl	114c <thread_set>
    1896:	e006      	b.n	18a6 <log_process_thread_func+0x1e>
	return z_impl_k_sem_take(sem, timeout);
    1898:	f04f 32ff 	mov.w	r2, #4294967295
    189c:	f04f 33ff 	mov.w	r3, #4294967295
    18a0:	4804      	ldr	r0, [pc, #16]	; (18b4 <log_process_thread_func+0x2c>)
    18a2:	f004 f80d 	bl	58c0 <z_impl_k_sem_take>
    18a6:	2000      	movs	r0, #0
    18a8:	f7ff fe6e 	bl	1588 <z_impl_log_process>
		if (log_process(false) == false) {
    18ac:	2800      	cmp	r0, #0
    18ae:	d1fa      	bne.n	18a6 <log_process_thread_func+0x1e>
    18b0:	e7f2      	b.n	1898 <log_process_thread_func+0x10>
    18b2:	bf00      	nop
    18b4:	200000c4 	.word	0x200000c4

000018b8 <log_free>:
{
    18b8:	b500      	push	{lr}
    18ba:	b083      	sub	sp, #12
	struct log_strdup_buf *dup = CONTAINER_OF(str, struct log_strdup_buf,
    18bc:	3804      	subs	r0, #4
    18be:	9001      	str	r0, [sp, #4]
	return __atomic_fetch_sub(target, value, __ATOMIC_SEQ_CST);
    18c0:	f3bf 8f5b 	dmb	ish
    18c4:	e850 3f00 	ldrex	r3, [r0]
    18c8:	1e5a      	subs	r2, r3, #1
    18ca:	e840 2100 	strex	r1, r2, [r0]
    18ce:	2900      	cmp	r1, #0
    18d0:	d1f8      	bne.n	18c4 <log_free+0xc>
    18d2:	f3bf 8f5b 	dmb	ish
	if (atomic_dec(&dup->refcount) == 1) {
    18d6:	2b01      	cmp	r3, #1
    18d8:	d002      	beq.n	18e0 <log_free+0x28>
}
    18da:	b003      	add	sp, #12
    18dc:	f85d fb04 	ldr.w	pc, [sp], #4
		k_mem_slab_free(&log_strdup_pool, (void **)&dup);
    18e0:	a901      	add	r1, sp, #4
    18e2:	4802      	ldr	r0, [pc, #8]	; (18ec <log_free+0x34>)
    18e4:	f006 f8d9 	bl	7a9a <k_mem_slab_free>
}
    18e8:	e7f7      	b.n	18da <log_free+0x22>
    18ea:	bf00      	nop
    18ec:	2000042c 	.word	0x2000042c

000018f0 <log_source_name_get>:
	return log_sources_count();
}

const char *log_source_name_get(uint32_t domain_id, uint32_t src_id)
{
	return src_id < log_sources_count() ? log_name_get(src_id) : NULL;
    18f0:	4b05      	ldr	r3, [pc, #20]	; (1908 <log_source_name_get+0x18>)
    18f2:	4a06      	ldr	r2, [pc, #24]	; (190c <log_source_name_get+0x1c>)
    18f4:	1a9b      	subs	r3, r3, r2
    18f6:	ebb1 0fd3 	cmp.w	r1, r3, lsr #3
    18fa:	d202      	bcs.n	1902 <log_source_name_get+0x12>
	return __log_const_start[source_id].name;
    18fc:	f852 0031 	ldr.w	r0, [r2, r1, lsl #3]
    1900:	4770      	bx	lr
    1902:	2000      	movs	r0, #0
}
    1904:	4770      	bx	lr
    1906:	bf00      	nop
    1908:	000083f4 	.word	0x000083f4
    190c:	0000839c 	.word	0x0000839c

00001910 <log_backend_enable>:
}

void log_backend_enable(struct log_backend const *const backend,
			void *ctx,
			uint32_t level)
{
    1910:	b508      	push	{r3, lr}
	/* As first slot in filtering mask is reserved, backend ID has offset.*/
	uint32_t id = LOG_FILTER_FIRST_BACKEND_SLOT_IDX;

	id += backend - log_backend_get(0);
    1912:	4b07      	ldr	r3, [pc, #28]	; (1930 <log_backend_enable+0x20>)
    1914:	1ac3      	subs	r3, r0, r3
    1916:	111b      	asrs	r3, r3, #4
    1918:	3301      	adds	r3, #1
	backend->cb->id = id;
    191a:	6842      	ldr	r2, [r0, #4]
    191c:	7113      	strb	r3, [r2, #4]
	backend->cb->ctx = ctx;
    191e:	6843      	ldr	r3, [r0, #4]
    1920:	6019      	str	r1, [r3, #0]
	backend->cb->active = true;
    1922:	6843      	ldr	r3, [r0, #4]
    1924:	2201      	movs	r2, #1
    1926:	715a      	strb	r2, [r3, #5]

	log_backend_id_set(backend, id);
	backend_filter_set(backend, level);
	log_backend_activate(backend, ctx);

	z_log_notify_backend_enabled();
    1928:	f7ff fcfc 	bl	1324 <z_log_notify_backend_enabled>
}
    192c:	bd08      	pop	{r3, pc}
    192e:	bf00      	nop
    1930:	000083f4 	.word	0x000083f4

00001934 <cont_free>:
{
	atomic_inc(&msg->hdr.ref_cnt);
}

static void cont_free(struct log_msg_cont *cont)
{
    1934:	b510      	push	{r4, lr}
    1936:	b082      	sub	sp, #8
    1938:	9001      	str	r0, [sp, #4]
	struct log_msg_cont *next;

	while (cont != NULL) {
    193a:	9b01      	ldr	r3, [sp, #4]
    193c:	b133      	cbz	r3, 194c <cont_free+0x18>
		next = cont->next;
    193e:	681c      	ldr	r4, [r3, #0]
		k_mem_slab_free(&log_msg_pool, (void **)&cont);
    1940:	a901      	add	r1, sp, #4
    1942:	4803      	ldr	r0, [pc, #12]	; (1950 <cont_free+0x1c>)
    1944:	f006 f8a9 	bl	7a9a <k_mem_slab_free>
		cont = next;
    1948:	9401      	str	r4, [sp, #4]
    194a:	e7f6      	b.n	193a <cont_free+0x6>
	}
}
    194c:	b002      	add	sp, #8
    194e:	bd10      	pop	{r4, pc}
    1950:	20000450 	.word	0x20000450

00001954 <log_msg_pool_init>:
{
    1954:	b508      	push	{r3, lr}
	k_mem_slab_init(&log_msg_pool, log_msg_pool_buf, MSG_SIZE, NUM_OF_MSGS);
    1956:	2320      	movs	r3, #32
    1958:	461a      	mov	r2, r3
    195a:	4902      	ldr	r1, [pc, #8]	; (1964 <log_msg_pool_init+0x10>)
    195c:	4802      	ldr	r0, [pc, #8]	; (1968 <log_msg_pool_init+0x14>)
    195e:	f006 f88d 	bl	7a7c <k_mem_slab_init>
}
    1962:	bd08      	pop	{r3, pc}
    1964:	20002070 	.word	0x20002070
    1968:	20000450 	.word	0x20000450

0000196c <log_msg_no_space_handle>:

	k_mem_slab_free(&log_msg_pool, (void **)&msg);
}

union log_msg_chunk *log_msg_no_space_handle(void)
{
    196c:	b510      	push	{r4, lr}
    196e:	b082      	sub	sp, #8
	union log_msg_chunk *msg = NULL;
    1970:	2300      	movs	r3, #0
    1972:	9301      	str	r3, [sp, #4]
    1974:	2001      	movs	r0, #1
    1976:	f7ff fe07 	bl	1588 <z_impl_log_process>
    197a:	4604      	mov	r4, r0
	int err;

	if (IS_ENABLED(CONFIG_LOG_MODE_OVERFLOW)) {
		do {
			more = log_process(true);
			z_log_dropped();
    197c:	f7ff fce2 	bl	1344 <z_log_dropped>
			err = k_mem_slab_alloc(&log_msg_pool,
    1980:	2200      	movs	r2, #0
    1982:	2300      	movs	r3, #0
    1984:	a901      	add	r1, sp, #4
    1986:	4804      	ldr	r0, [pc, #16]	; (1998 <log_msg_no_space_handle+0x2c>)
    1988:	f003 fd6e 	bl	5468 <k_mem_slab_alloc>
					       (void **)&msg,
					       K_NO_WAIT);
		} while ((err != 0) && more);
    198c:	b108      	cbz	r0, 1992 <log_msg_no_space_handle+0x26>
    198e:	2c00      	cmp	r4, #0
    1990:	d1f0      	bne.n	1974 <log_msg_no_space_handle+0x8>
	} else {
		z_log_dropped();
	}
	return msg;

}
    1992:	9801      	ldr	r0, [sp, #4]
    1994:	b002      	add	sp, #8
    1996:	bd10      	pop	{r4, pc}
    1998:	20000450 	.word	0x20000450

0000199c <log_msg_chunk_alloc>:
{
    199c:	b500      	push	{lr}
    199e:	b083      	sub	sp, #12
	union log_msg_chunk *msg = NULL;
    19a0:	2300      	movs	r3, #0
    19a2:	9301      	str	r3, [sp, #4]
		   block_on_alloc()
    19a4:	f005 f9a2 	bl	6cec <block_on_alloc>
	int err = k_mem_slab_alloc(&log_msg_pool, (void **)&msg,
    19a8:	b150      	cbz	r0, 19c0 <log_msg_chunk_alloc+0x24>
    19aa:	2200      	movs	r2, #0
    19ac:	2300      	movs	r3, #0
    19ae:	a901      	add	r1, sp, #4
    19b0:	4807      	ldr	r0, [pc, #28]	; (19d0 <log_msg_chunk_alloc+0x34>)
    19b2:	f003 fd59 	bl	5468 <k_mem_slab_alloc>
	if (err != 0) {
    19b6:	b930      	cbnz	r0, 19c6 <log_msg_chunk_alloc+0x2a>
}
    19b8:	9801      	ldr	r0, [sp, #4]
    19ba:	b003      	add	sp, #12
    19bc:	f85d fb04 	ldr.w	pc, [sp], #4
	int err = k_mem_slab_alloc(&log_msg_pool, (void **)&msg,
    19c0:	2200      	movs	r2, #0
    19c2:	2300      	movs	r3, #0
    19c4:	e7f3      	b.n	19ae <log_msg_chunk_alloc+0x12>
		msg = log_msg_no_space_handle();
    19c6:	f7ff ffd1 	bl	196c <log_msg_no_space_handle>
    19ca:	9001      	str	r0, [sp, #4]
    19cc:	e7f4      	b.n	19b8 <log_msg_chunk_alloc+0x1c>
    19ce:	bf00      	nop
    19d0:	20000450 	.word	0x20000450

000019d4 <msg_free>:
{
    19d4:	b5f0      	push	{r4, r5, r6, r7, lr}
    19d6:	b083      	sub	sp, #12
    19d8:	9001      	str	r0, [sp, #4]
	uint32_t nargs = log_msg_nargs_get(msg);
    19da:	4604      	mov	r4, r0
    19dc:	f005 fa06 	bl	6dec <log_msg_nargs_get>
	return  (msg->hdr.params.generic.type == LOG_MSG_TYPE_STD);
    19e0:	7a23      	ldrb	r3, [r4, #8]
	if (log_msg_is_std(msg) && nargs) {
    19e2:	f013 0f01 	tst.w	r3, #1
    19e6:	d101      	bne.n	19ec <msg_free+0x18>
    19e8:	4606      	mov	r6, r0
    19ea:	bb50      	cbnz	r0, 1a42 <msg_free+0x6e>
	if (msg->hdr.params.generic.ext == 1) {
    19ec:	9b01      	ldr	r3, [sp, #4]
    19ee:	7a1a      	ldrb	r2, [r3, #8]
    19f0:	f012 0f02 	tst.w	r2, #2
    19f4:	d128      	bne.n	1a48 <msg_free+0x74>
	k_mem_slab_free(&log_msg_pool, (void **)&msg);
    19f6:	a901      	add	r1, sp, #4
    19f8:	4815      	ldr	r0, [pc, #84]	; (1a50 <msg_free+0x7c>)
    19fa:	f006 f84e 	bl	7a9a <k_mem_slab_free>
}
    19fe:	b003      	add	sp, #12
    1a00:	bdf0      	pop	{r4, r5, r6, r7, pc}
					smask = z_log_get_s_mask(
    1a02:	9801      	ldr	r0, [sp, #4]
    1a04:	f005 fa07 	bl	6e16 <log_msg_str_get>
    1a08:	4631      	mov	r1, r6
    1a0a:	f7ff fbf3 	bl	11f4 <z_log_get_s_mask>
					if (smask == 0U) {
    1a0e:	4607      	mov	r7, r0
    1a10:	b988      	cbnz	r0, 1a36 <msg_free+0x62>
    1a12:	e7eb      	b.n	19ec <msg_free+0x18>
					log_free(buf);
    1a14:	4628      	mov	r0, r5
    1a16:	f7ff ff4f 	bl	18b8 <log_free>
		for (i = 0U; i < nargs; i++) {
    1a1a:	3401      	adds	r4, #1
    1a1c:	42b4      	cmp	r4, r6
    1a1e:	d2e5      	bcs.n	19ec <msg_free+0x18>
			void *buf = (void *)log_msg_arg_get(msg, i);
    1a20:	4621      	mov	r1, r4
    1a22:	9801      	ldr	r0, [sp, #4]
    1a24:	f005 f9e5 	bl	6df2 <log_msg_arg_get>
    1a28:	4605      	mov	r5, r0
			if (log_is_strdup(buf)) {
    1a2a:	f7ff fd15 	bl	1458 <log_is_strdup>
    1a2e:	2800      	cmp	r0, #0
    1a30:	d0f3      	beq.n	1a1a <msg_free+0x46>
				if (smask == 0U) {
    1a32:	2f00      	cmp	r7, #0
    1a34:	d0e5      	beq.n	1a02 <msg_free+0x2e>
				if (smask & BIT(i)) {
    1a36:	fa27 f304 	lsr.w	r3, r7, r4
    1a3a:	f013 0f01 	tst.w	r3, #1
    1a3e:	d0ec      	beq.n	1a1a <msg_free+0x46>
    1a40:	e7e8      	b.n	1a14 <msg_free+0x40>
		uint32_t smask = 0U;
    1a42:	2700      	movs	r7, #0
		for (i = 0U; i < nargs; i++) {
    1a44:	463c      	mov	r4, r7
    1a46:	e7e9      	b.n	1a1c <msg_free+0x48>
		cont_free(msg->payload.ext.next);
    1a48:	6958      	ldr	r0, [r3, #20]
    1a4a:	f7ff ff73 	bl	1934 <cont_free>
    1a4e:	e7d2      	b.n	19f6 <msg_free+0x22>
    1a50:	20000450 	.word	0x20000450

00001a54 <print_formatted>:
	return 0;
}

static int print_formatted(const struct log_output *output,
			   const char *fmt, ...)
{
    1a54:	b40e      	push	{r1, r2, r3}
    1a56:	b500      	push	{lr}
    1a58:	b082      	sub	sp, #8
    1a5a:	4601      	mov	r1, r0
    1a5c:	ab03      	add	r3, sp, #12
    1a5e:	f853 2b04 	ldr.w	r2, [r3], #4
	va_list args;
	int length = 0;

	va_start(args, fmt);
    1a62:	9301      	str	r3, [sp, #4]
	length = cbvprintf(out_func, (void *)output, fmt, args);
    1a64:	4803      	ldr	r0, [pc, #12]	; (1a74 <print_formatted+0x20>)
    1a66:	f7fe fe77 	bl	758 <cbvprintf>
	va_end(args);

	return length;
}
    1a6a:	b002      	add	sp, #8
    1a6c:	f85d eb04 	ldr.w	lr, [sp], #4
    1a70:	b003      	add	sp, #12
    1a72:	4770      	bx	lr
    1a74:	000071b9 	.word	0x000071b9

00001a78 <timestamp_print>:
	output->control_block->offset = 0;
}

static int timestamp_print(const struct log_output *output,
			   uint32_t flags, uint32_t timestamp)
{
    1a78:	b5f0      	push	{r4, r5, r6, r7, lr}
    1a7a:	b085      	sub	sp, #20
	bool format =
		(flags & LOG_OUTPUT_FLAG_FORMAT_TIMESTAMP) |
		(flags & LOG_OUTPUT_FLAG_FORMAT_SYSLOG);


	if (!format) {
    1a7c:	f011 0f44 	tst.w	r1, #68	; 0x44
    1a80:	d005      	beq.n	1a8e <timestamp_print+0x16>
		length = print_formatted(output, "[%08lu] ", timestamp);
	} else if (freq != 0U) {
    1a82:	4b1a      	ldr	r3, [pc, #104]	; (1aec <timestamp_print+0x74>)
    1a84:	681c      	ldr	r4, [r3, #0]
    1a86:	b934      	cbnz	r4, 1a96 <timestamp_print+0x1e>
			length = print_formatted(output,
						 "[%02u:%02u:%02u.%03u,%03u] ",
						 hours, mins, seconds, ms, us);
		}
	} else {
		length = 0;
    1a88:	2000      	movs	r0, #0
	}

	return length;
}
    1a8a:	b005      	add	sp, #20
    1a8c:	bdf0      	pop	{r4, r5, r6, r7, pc}
		length = print_formatted(output, "[%08lu] ", timestamp);
    1a8e:	4918      	ldr	r1, [pc, #96]	; (1af0 <timestamp_print+0x78>)
    1a90:	f7ff ffe0 	bl	1a54 <print_formatted>
    1a94:	e7f9      	b.n	1a8a <timestamp_print+0x12>
		timestamp /= timestamp_div;
    1a96:	4b17      	ldr	r3, [pc, #92]	; (1af4 <timestamp_print+0x7c>)
    1a98:	6819      	ldr	r1, [r3, #0]
    1a9a:	fbb2 f1f1 	udiv	r1, r2, r1
		total_seconds = timestamp / freq;
    1a9e:	fbb1 f5f4 	udiv	r5, r1, r4
		hours = seconds / 3600U;
    1aa2:	4a15      	ldr	r2, [pc, #84]	; (1af8 <timestamp_print+0x80>)
    1aa4:	fba2 3205 	umull	r3, r2, r2, r5
    1aa8:	0ad2      	lsrs	r2, r2, #11
		seconds -= hours * 3600U;
    1aaa:	f44f 6661 	mov.w	r6, #3600	; 0xe10
    1aae:	fb06 5612 	mls	r6, r6, r2, r5
		mins = seconds / 60U;
    1ab2:	4b12      	ldr	r3, [pc, #72]	; (1afc <timestamp_print+0x84>)
    1ab4:	fba3 7306 	umull	r7, r3, r3, r6
    1ab8:	095b      	lsrs	r3, r3, #5
		remainder = timestamp % freq;
    1aba:	fb04 1115 	mls	r1, r4, r5, r1
		ms = (remainder * 1000U) / freq;
    1abe:	f44f 757a 	mov.w	r5, #1000	; 0x3e8
    1ac2:	fb05 f101 	mul.w	r1, r5, r1
    1ac6:	fbb1 f7f4 	udiv	r7, r1, r4
		us = (1000 * (remainder * 1000U - (ms * freq))) / freq;
    1aca:	fb07 1114 	mls	r1, r7, r4, r1
    1ace:	fb05 f101 	mul.w	r1, r5, r1
    1ad2:	fbb1 f4f4 	udiv	r4, r1, r4
			length = print_formatted(output,
    1ad6:	9402      	str	r4, [sp, #8]
    1ad8:	9701      	str	r7, [sp, #4]
    1ada:	ebc3 1103 	rsb	r1, r3, r3, lsl #4
    1ade:	eba6 0181 	sub.w	r1, r6, r1, lsl #2
    1ae2:	9100      	str	r1, [sp, #0]
    1ae4:	4906      	ldr	r1, [pc, #24]	; (1b00 <timestamp_print+0x88>)
    1ae6:	f7ff ffb5 	bl	1a54 <print_formatted>
    1aea:	e7ce      	b.n	1a8a <timestamp_print+0x12>
    1aec:	20000470 	.word	0x20000470
    1af0:	00008570 	.word	0x00008570
    1af4:	20000474 	.word	0x20000474
    1af8:	91a2b3c5 	.word	0x91a2b3c5
    1afc:	88888889 	.word	0x88888889
    1b00:	0000857c 	.word	0x0000857c

00001b04 <color_print>:

static void color_print(const struct log_output *output,
			bool color, bool start, uint32_t level)
{
	if (color) {
    1b04:	b161      	cbz	r1, 1b20 <color_print+0x1c>
{
    1b06:	b508      	push	{r3, lr}
		const char *log_color = start && (colors[level] != NULL) ?
				colors[level] : LOG_COLOR_CODE_DEFAULT;
    1b08:	b12a      	cbz	r2, 1b16 <color_print+0x12>
		const char *log_color = start && (colors[level] != NULL) ?
    1b0a:	4a06      	ldr	r2, [pc, #24]	; (1b24 <color_print+0x20>)
    1b0c:	f852 2023 	ldr.w	r2, [r2, r3, lsl #2]
    1b10:	b912      	cbnz	r2, 1b18 <color_print+0x14>
				colors[level] : LOG_COLOR_CODE_DEFAULT;
    1b12:	4a05      	ldr	r2, [pc, #20]	; (1b28 <color_print+0x24>)
    1b14:	e000      	b.n	1b18 <color_print+0x14>
    1b16:	4a04      	ldr	r2, [pc, #16]	; (1b28 <color_print+0x24>)
		print_formatted(output, "%s", log_color);
    1b18:	4904      	ldr	r1, [pc, #16]	; (1b2c <color_print+0x28>)
    1b1a:	f7ff ff9b 	bl	1a54 <print_formatted>
	}
}
    1b1e:	bd08      	pop	{r3, pc}
    1b20:	4770      	bx	lr
    1b22:	bf00      	nop
    1b24:	000085f8 	.word	0x000085f8
    1b28:	00008598 	.word	0x00008598
    1b2c:	000085a0 	.word	0x000085a0

00001b30 <newline_print>:
	if (IS_ENABLED(CONFIG_LOG_BACKEND_NET) &&
	    flags & LOG_OUTPUT_FLAG_FORMAT_SYSLOG) {
		return;
	}

	if ((flags & LOG_OUTPUT_FLAG_CRLF_NONE) != 0U) {
    1b30:	f011 0f10 	tst.w	r1, #16
    1b34:	d10b      	bne.n	1b4e <newline_print+0x1e>
{
    1b36:	b508      	push	{r3, lr}
		return;
	}

	if ((flags & LOG_OUTPUT_FLAG_CRLF_LFONLY) != 0U) {
    1b38:	f011 0f20 	tst.w	r1, #32
    1b3c:	d003      	beq.n	1b46 <newline_print+0x16>
		print_formatted(ctx, "\n");
    1b3e:	4904      	ldr	r1, [pc, #16]	; (1b50 <newline_print+0x20>)
    1b40:	f7ff ff88 	bl	1a54 <print_formatted>
	} else {
		print_formatted(ctx, "\r\n");
	}
}
    1b44:	bd08      	pop	{r3, pc}
		print_formatted(ctx, "\r\n");
    1b46:	4903      	ldr	r1, [pc, #12]	; (1b54 <newline_print+0x24>)
    1b48:	f7ff ff84 	bl	1a54 <print_formatted>
    1b4c:	e7fa      	b.n	1b44 <newline_print+0x14>
    1b4e:	4770      	bx	lr
    1b50:	000084fc 	.word	0x000084fc
    1b54:	000085a4 	.word	0x000085a4

00001b58 <hexdump_line_print>:
}

static void hexdump_line_print(const struct log_output *output,
			       const uint8_t *data, uint32_t length,
			       int prefix_offset, uint32_t flags)
{
    1b58:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    1b5c:	4605      	mov	r5, r0
    1b5e:	460f      	mov	r7, r1
    1b60:	4616      	mov	r6, r2
    1b62:	4698      	mov	r8, r3
	newline_print(output, flags);
    1b64:	9906      	ldr	r1, [sp, #24]
    1b66:	f7ff ffe3 	bl	1b30 <newline_print>

	for (int i = 0; i < prefix_offset; i++) {
    1b6a:	2400      	movs	r4, #0
    1b6c:	4544      	cmp	r4, r8
    1b6e:	da05      	bge.n	1b7c <hexdump_line_print+0x24>
		print_formatted(output, " ");
    1b70:	4924      	ldr	r1, [pc, #144]	; (1c04 <hexdump_line_print+0xac>)
    1b72:	4628      	mov	r0, r5
    1b74:	f7ff ff6e 	bl	1a54 <print_formatted>
	for (int i = 0; i < prefix_offset; i++) {
    1b78:	3401      	adds	r4, #1
    1b7a:	e7f7      	b.n	1b6c <hexdump_line_print+0x14>
	}

	for (int i = 0; i < HEXDUMP_BYTES_IN_LINE; i++) {
    1b7c:	2400      	movs	r4, #0
    1b7e:	e009      	b.n	1b94 <hexdump_line_print+0x3c>
		if (i > 0 && !(i % 8)) {
			print_formatted(output, " ");
    1b80:	4920      	ldr	r1, [pc, #128]	; (1c04 <hexdump_line_print+0xac>)
    1b82:	4628      	mov	r0, r5
    1b84:	f7ff ff66 	bl	1a54 <print_formatted>
    1b88:	e00b      	b.n	1ba2 <hexdump_line_print+0x4a>
		}

		if (i < length) {
			print_formatted(output, "%02x ", data[i]);
		} else {
			print_formatted(output, "   ");
    1b8a:	491f      	ldr	r1, [pc, #124]	; (1c08 <hexdump_line_print+0xb0>)
    1b8c:	4628      	mov	r0, r5
    1b8e:	f7ff ff61 	bl	1a54 <print_formatted>
	for (int i = 0; i < HEXDUMP_BYTES_IN_LINE; i++) {
    1b92:	3401      	adds	r4, #1
    1b94:	2c0f      	cmp	r4, #15
    1b96:	dc0c      	bgt.n	1bb2 <hexdump_line_print+0x5a>
		if (i > 0 && !(i % 8)) {
    1b98:	2c00      	cmp	r4, #0
    1b9a:	dd02      	ble.n	1ba2 <hexdump_line_print+0x4a>
    1b9c:	f014 0f07 	tst.w	r4, #7
    1ba0:	d0ee      	beq.n	1b80 <hexdump_line_print+0x28>
		if (i < length) {
    1ba2:	42b4      	cmp	r4, r6
    1ba4:	d2f1      	bcs.n	1b8a <hexdump_line_print+0x32>
			print_formatted(output, "%02x ", data[i]);
    1ba6:	5d3a      	ldrb	r2, [r7, r4]
    1ba8:	4918      	ldr	r1, [pc, #96]	; (1c0c <hexdump_line_print+0xb4>)
    1baa:	4628      	mov	r0, r5
    1bac:	f7ff ff52 	bl	1a54 <print_formatted>
    1bb0:	e7ef      	b.n	1b92 <hexdump_line_print+0x3a>
		}
	}

	print_formatted(output, "|");
    1bb2:	4917      	ldr	r1, [pc, #92]	; (1c10 <hexdump_line_print+0xb8>)
    1bb4:	4628      	mov	r0, r5
    1bb6:	f7ff ff4d 	bl	1a54 <print_formatted>

	for (int i = 0; i < HEXDUMP_BYTES_IN_LINE; i++) {
    1bba:	2400      	movs	r4, #0
    1bbc:	e009      	b.n	1bd2 <hexdump_line_print+0x7a>
		if (i > 0 && !(i % 8)) {
			print_formatted(output, " ");
    1bbe:	4911      	ldr	r1, [pc, #68]	; (1c04 <hexdump_line_print+0xac>)
    1bc0:	4628      	mov	r0, r5
    1bc2:	f7ff ff47 	bl	1a54 <print_formatted>
    1bc6:	e00b      	b.n	1be0 <hexdump_line_print+0x88>
		}

		if (i < length) {
			char c = (char)data[i];

			print_formatted(output, "%c",
    1bc8:	4912      	ldr	r1, [pc, #72]	; (1c14 <hexdump_line_print+0xbc>)
    1bca:	4628      	mov	r0, r5
    1bcc:	f7ff ff42 	bl	1a54 <print_formatted>
	for (int i = 0; i < HEXDUMP_BYTES_IN_LINE; i++) {
    1bd0:	3401      	adds	r4, #1
    1bd2:	2c0f      	cmp	r4, #15
    1bd4:	dc13      	bgt.n	1bfe <hexdump_line_print+0xa6>
		if (i > 0 && !(i % 8)) {
    1bd6:	2c00      	cmp	r4, #0
    1bd8:	dd02      	ble.n	1be0 <hexdump_line_print+0x88>
    1bda:	f014 0f07 	tst.w	r4, #7
    1bde:	d0ee      	beq.n	1bbe <hexdump_line_print+0x66>
		if (i < length) {
    1be0:	42b4      	cmp	r4, r6
    1be2:	d207      	bcs.n	1bf4 <hexdump_line_print+0x9c>
			char c = (char)data[i];
    1be4:	5d3a      	ldrb	r2, [r7, r4]
			      isprint((int)c) ? c : '.');
    1be6:	4b0c      	ldr	r3, [pc, #48]	; (1c18 <hexdump_line_print+0xc0>)
    1be8:	5cd3      	ldrb	r3, [r2, r3]
			print_formatted(output, "%c",
    1bea:	f013 0f97 	tst.w	r3, #151	; 0x97
    1bee:	d1eb      	bne.n	1bc8 <hexdump_line_print+0x70>
    1bf0:	222e      	movs	r2, #46	; 0x2e
    1bf2:	e7e9      	b.n	1bc8 <hexdump_line_print+0x70>
		} else {
			print_formatted(output, " ");
    1bf4:	4903      	ldr	r1, [pc, #12]	; (1c04 <hexdump_line_print+0xac>)
    1bf6:	4628      	mov	r0, r5
    1bf8:	f7ff ff2c 	bl	1a54 <print_formatted>
    1bfc:	e7e8      	b.n	1bd0 <hexdump_line_print+0x78>
		}
	}
}
    1bfe:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    1c02:	bf00      	nop
    1c04:	000085cc 	.word	0x000085cc
    1c08:	000085b0 	.word	0x000085b0
    1c0c:	000085a8 	.word	0x000085a8
    1c10:	000085b4 	.word	0x000085b4
    1c14:	000085b8 	.word	0x000085b8
    1c18:	00008ea6 	.word	0x00008ea6

00001c1c <ids_print>:
{
    1c1c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    1c20:	4680      	mov	r8, r0
    1c22:	4616      	mov	r6, r2
    1c24:	461d      	mov	r5, r3
    1c26:	f9bd 7018 	ldrsh.w	r7, [sp, #24]
	if (level_on) {
    1c2a:	b959      	cbnz	r1, 1c44 <ids_print+0x28>
	int total = 0;
    1c2c:	2400      	movs	r4, #0
	if (source_id >= 0) {
    1c2e:	2f00      	cmp	r7, #0
    1c30:	db1c      	blt.n	1c6c <ids_print+0x50>
		total += print_formatted(output,
    1c32:	b186      	cbz	r6, 1c56 <ids_print+0x3a>
				((1 << level) & LOG_FUNCTION_PREFIX_MASK)) ?
    1c34:	2301      	movs	r3, #1
    1c36:	9a07      	ldr	r2, [sp, #28]
    1c38:	4093      	lsls	r3, r2
				(func_on &&
    1c3a:	f013 0f10 	tst.w	r3, #16
    1c3e:	d118      	bne.n	1c72 <ids_print+0x56>
		total += print_formatted(output,
    1c40:	4e0d      	ldr	r6, [pc, #52]	; (1c78 <ids_print+0x5c>)
    1c42:	e009      	b.n	1c58 <ids_print+0x3c>
		total += print_formatted(output, "<%s> ", severity[level]);
    1c44:	4b0d      	ldr	r3, [pc, #52]	; (1c7c <ids_print+0x60>)
    1c46:	9a07      	ldr	r2, [sp, #28]
    1c48:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
    1c4c:	490c      	ldr	r1, [pc, #48]	; (1c80 <ids_print+0x64>)
    1c4e:	f7ff ff01 	bl	1a54 <print_formatted>
    1c52:	4604      	mov	r4, r0
    1c54:	e7eb      	b.n	1c2e <ids_print+0x12>
		total += print_formatted(output,
    1c56:	4e08      	ldr	r6, [pc, #32]	; (1c78 <ids_print+0x5c>)
    1c58:	4639      	mov	r1, r7
    1c5a:	4628      	mov	r0, r5
    1c5c:	f7ff fe48 	bl	18f0 <log_source_name_get>
    1c60:	4602      	mov	r2, r0
    1c62:	4631      	mov	r1, r6
    1c64:	4640      	mov	r0, r8
    1c66:	f7ff fef5 	bl	1a54 <print_formatted>
    1c6a:	4404      	add	r4, r0
}
    1c6c:	4620      	mov	r0, r4
    1c6e:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		total += print_formatted(output,
    1c72:	4e04      	ldr	r6, [pc, #16]	; (1c84 <ids_print+0x68>)
    1c74:	e7f0      	b.n	1c58 <ids_print+0x3c>
    1c76:	bf00      	nop
    1c78:	000085bc 	.word	0x000085bc
    1c7c:	00008634 	.word	0x00008634
    1c80:	000085c8 	.word	0x000085c8
    1c84:	000085c4 	.word	0x000085c4

00001c88 <hexdump_print>:

static void hexdump_print(struct log_msg *msg,
			  const struct log_output *output,
			  int prefix_offset, uint32_t flags)
{
    1c88:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
    1c8c:	b089      	sub	sp, #36	; 0x24
    1c8e:	4607      	mov	r7, r0
    1c90:	460e      	mov	r6, r1
    1c92:	4691      	mov	r9, r2
    1c94:	4698      	mov	r8, r3
	uint32_t offset = 0U;
	uint8_t buf[HEXDUMP_BYTES_IN_LINE];
	size_t length;

	print_formatted(output, "%s", log_msg_str_get(msg));
    1c96:	f005 f8be 	bl	6e16 <log_msg_str_get>
    1c9a:	4602      	mov	r2, r0
    1c9c:	490e      	ldr	r1, [pc, #56]	; (1cd8 <hexdump_print+0x50>)
    1c9e:	4630      	mov	r0, r6
    1ca0:	f7ff fed8 	bl	1a54 <print_formatted>
	uint32_t offset = 0U;
    1ca4:	2400      	movs	r4, #0

	do {
		length = sizeof(buf);
    1ca6:	2510      	movs	r5, #16
    1ca8:	9503      	str	r5, [sp, #12]
		log_msg_hexdump_data_get(msg, buf, &length, offset);
    1caa:	4623      	mov	r3, r4
    1cac:	aa03      	add	r2, sp, #12
    1cae:	eb0d 0105 	add.w	r1, sp, r5
    1cb2:	4638      	mov	r0, r7
    1cb4:	f005 f8c4 	bl	6e40 <log_msg_hexdump_data_get>

		if (length) {
    1cb8:	9a03      	ldr	r2, [sp, #12]
    1cba:	b152      	cbz	r2, 1cd2 <hexdump_print+0x4a>
			hexdump_line_print(output, buf, length,
    1cbc:	f8cd 8000 	str.w	r8, [sp]
    1cc0:	464b      	mov	r3, r9
    1cc2:	eb0d 0105 	add.w	r1, sp, r5
    1cc6:	4630      	mov	r0, r6
    1cc8:	f7ff ff46 	bl	1b58 <hexdump_line_print>
					   prefix_offset, flags);
			offset += length;
    1ccc:	9d03      	ldr	r5, [sp, #12]
    1cce:	442c      	add	r4, r5
		length = sizeof(buf);
    1cd0:	e7e9      	b.n	1ca6 <hexdump_print+0x1e>
		} else {
			break;
		}
	} while (true);
}
    1cd2:	b009      	add	sp, #36	; 0x24
    1cd4:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
    1cd8:	000085a0 	.word	0x000085a0

00001cdc <raw_string_print>:
}


static void raw_string_print(struct log_msg *msg,
			     const struct log_output *output)
{
    1cdc:	b5f0      	push	{r4, r5, r6, r7, lr}
    1cde:	b083      	sub	sp, #12
    1ce0:	4606      	mov	r6, r0
    1ce2:	460c      	mov	r4, r1
	__ASSERT_NO_MSG(output->size);

	size_t offset = 0;
	size_t length;
	bool eol = false;
    1ce4:	2700      	movs	r7, #0
	size_t offset = 0;
    1ce6:	463d      	mov	r5, r7
    1ce8:	e00d      	b.n	1d06 <raw_string_print+0x2a>
		/* Sting is stored in a hexdump message. */
		log_msg_hexdump_data_get(msg, output->buf, &length, offset);
		output->control_block->offset = length;

		if (length != 0) {
			eol = (output->buf[length - 1] == '\n');
    1cea:	68a2      	ldr	r2, [r4, #8]
    1cec:	4413      	add	r3, r2
    1cee:	f813 7c01 	ldrb.w	r7, [r3, #-1]
    1cf2:	2f0a      	cmp	r7, #10
    1cf4:	bf14      	ite	ne
    1cf6:	2700      	movne	r7, #0
    1cf8:	2701      	moveq	r7, #1
		}

		log_output_flush(output);
    1cfa:	4620      	mov	r0, r4
    1cfc:	f005 fa4f 	bl	719e <log_output_flush>
		offset += length;
    1d00:	9b01      	ldr	r3, [sp, #4]
    1d02:	441d      	add	r5, r3
	} while (length > 0);
    1d04:	b173      	cbz	r3, 1d24 <raw_string_print+0x48>
		length = output->size;
    1d06:	68e3      	ldr	r3, [r4, #12]
    1d08:	9301      	str	r3, [sp, #4]
		log_msg_hexdump_data_get(msg, output->buf, &length, offset);
    1d0a:	462b      	mov	r3, r5
    1d0c:	aa01      	add	r2, sp, #4
    1d0e:	68a1      	ldr	r1, [r4, #8]
    1d10:	4630      	mov	r0, r6
    1d12:	f005 f895 	bl	6e40 <log_msg_hexdump_data_get>
		output->control_block->offset = length;
    1d16:	6863      	ldr	r3, [r4, #4]
    1d18:	9a01      	ldr	r2, [sp, #4]
    1d1a:	601a      	str	r2, [r3, #0]
		if (length != 0) {
    1d1c:	9b01      	ldr	r3, [sp, #4]
    1d1e:	2b00      	cmp	r3, #0
    1d20:	d0eb      	beq.n	1cfa <raw_string_print+0x1e>
    1d22:	e7e2      	b.n	1cea <raw_string_print+0xe>

	if (eol) {
    1d24:	b90f      	cbnz	r7, 1d2a <raw_string_print+0x4e>
		print_formatted(output, "\r");
	}
}
    1d26:	b003      	add	sp, #12
    1d28:	bdf0      	pop	{r4, r5, r6, r7, pc}
		print_formatted(output, "\r");
    1d2a:	4902      	ldr	r1, [pc, #8]	; (1d34 <raw_string_print+0x58>)
    1d2c:	4620      	mov	r0, r4
    1d2e:	f7ff fe91 	bl	1a54 <print_formatted>
}
    1d32:	e7f8      	b.n	1d26 <raw_string_print+0x4a>
    1d34:	000085d0 	.word	0x000085d0

00001d38 <log_output_dropped_process>:
	postfix_print(output, flags, level);
	log_output_flush(output);
}

void log_output_dropped_process(const struct log_output *output, uint32_t cnt)
{
    1d38:	b570      	push	{r4, r5, r6, lr}
    1d3a:	b082      	sub	sp, #8
    1d3c:	4604      	mov	r4, r0
	char buf[5];
	int len;
	static const char prefix[] = DROPPED_COLOR_PREFIX "--- ";
	static const char postfix[] =
			" messages dropped ---\r\n" DROPPED_COLOR_POSTFIX;
	log_output_func_t outf = output->func;
    1d3e:	6805      	ldr	r5, [r0, #0]

	cnt = MIN(cnt, 9999);
	len = snprintk(buf, sizeof(buf), "%d", cnt);
    1d40:	f242 730f 	movw	r3, #9999	; 0x270f
    1d44:	428b      	cmp	r3, r1
    1d46:	bf28      	it	cs
    1d48:	460b      	movcs	r3, r1
    1d4a:	4a0e      	ldr	r2, [pc, #56]	; (1d84 <log_output_dropped_process+0x4c>)
    1d4c:	2105      	movs	r1, #5
    1d4e:	4668      	mov	r0, sp
    1d50:	f004 fe02 	bl	6958 <snprintk>
    1d54:	4606      	mov	r6, r0

	buffer_write(outf, (uint8_t *)prefix, sizeof(prefix) - 1,
		     output->control_block->ctx);
    1d56:	6863      	ldr	r3, [r4, #4]
	buffer_write(outf, (uint8_t *)prefix, sizeof(prefix) - 1,
    1d58:	685b      	ldr	r3, [r3, #4]
    1d5a:	220b      	movs	r2, #11
    1d5c:	490a      	ldr	r1, [pc, #40]	; (1d88 <log_output_dropped_process+0x50>)
    1d5e:	4628      	mov	r0, r5
    1d60:	f005 f876 	bl	6e50 <buffer_write>
	buffer_write(outf, buf, len, output->control_block->ctx);
    1d64:	6863      	ldr	r3, [r4, #4]
    1d66:	685b      	ldr	r3, [r3, #4]
    1d68:	4632      	mov	r2, r6
    1d6a:	4669      	mov	r1, sp
    1d6c:	4628      	mov	r0, r5
    1d6e:	f005 f86f 	bl	6e50 <buffer_write>
	buffer_write(outf, (uint8_t *)postfix, sizeof(postfix) - 1,
		     output->control_block->ctx);
    1d72:	6863      	ldr	r3, [r4, #4]
	buffer_write(outf, (uint8_t *)postfix, sizeof(postfix) - 1,
    1d74:	685b      	ldr	r3, [r3, #4]
    1d76:	221b      	movs	r2, #27
    1d78:	4904      	ldr	r1, [pc, #16]	; (1d8c <log_output_dropped_process+0x54>)
    1d7a:	4628      	mov	r0, r5
    1d7c:	f005 f868 	bl	6e50 <buffer_write>
}
    1d80:	b002      	add	sp, #8
    1d82:	bd70      	pop	{r4, r5, r6, pc}
    1d84:	000085d4 	.word	0x000085d4
    1d88:	00008628 	.word	0x00008628
    1d8c:	0000860c 	.word	0x0000860c

00001d90 <log_output_timestamp_freq_set>:

void log_output_timestamp_freq_set(uint32_t frequency)
{
	timestamp_div = 1U;
    1d90:	4b07      	ldr	r3, [pc, #28]	; (1db0 <log_output_timestamp_freq_set+0x20>)
    1d92:	2201      	movs	r2, #1
    1d94:	601a      	str	r2, [r3, #0]
	/* There is no point to have frequency higher than 1MHz (ns are not
	 * printed) and too high frequency leads to overflows in calculations.
	 */
	while (frequency > 1000000) {
    1d96:	4b07      	ldr	r3, [pc, #28]	; (1db4 <log_output_timestamp_freq_set+0x24>)
    1d98:	4298      	cmp	r0, r3
    1d9a:	d905      	bls.n	1da8 <log_output_timestamp_freq_set+0x18>
		frequency /= 2U;
    1d9c:	0840      	lsrs	r0, r0, #1
		timestamp_div *= 2U;
    1d9e:	4a04      	ldr	r2, [pc, #16]	; (1db0 <log_output_timestamp_freq_set+0x20>)
    1da0:	6813      	ldr	r3, [r2, #0]
    1da2:	005b      	lsls	r3, r3, #1
    1da4:	6013      	str	r3, [r2, #0]
    1da6:	e7f6      	b.n	1d96 <log_output_timestamp_freq_set+0x6>
	}

	freq = frequency;
    1da8:	4b03      	ldr	r3, [pc, #12]	; (1db8 <log_output_timestamp_freq_set+0x28>)
    1daa:	6018      	str	r0, [r3, #0]
}
    1dac:	4770      	bx	lr
    1dae:	bf00      	nop
    1db0:	20000474 	.word	0x20000474
    1db4:	000f4240 	.word	0x000f4240
    1db8:	20000470 	.word	0x20000470

00001dbc <char_out>:
static const char LOG_HEX_SEP[10] = "##ZLOGV1##";

static const struct device *uart_dev;

static int char_out(uint8_t *data, size_t length, void *ctx)
{
    1dbc:	b570      	push	{r4, r5, r6, lr}
    1dbe:	4606      	mov	r6, r0
    1dc0:	460d      	mov	r5, r1
	ARG_UNUSED(ctx);

	for (size_t i = 0; i < length; i++) {
    1dc2:	2400      	movs	r4, #0
    1dc4:	42ac      	cmp	r4, r5
    1dc6:	d207      	bcs.n	1dd8 <char_out+0x1c>
		/* lower 8-bit */
		x = data[i] & 0x0FU;
		(void)hex2char(x, &c);
		uart_poll_out(uart_dev, c);
#else
		uart_poll_out(uart_dev, data[i]);
    1dc8:	4b04      	ldr	r3, [pc, #16]	; (1ddc <char_out+0x20>)
    1dca:	6818      	ldr	r0, [r3, #0]
    1dcc:	5d31      	ldrb	r1, [r6, r4]
				      unsigned char out_char);

static inline void z_impl_uart_poll_out(const struct device *dev,
						unsigned char out_char)
{
	const struct uart_driver_api *api =
    1dce:	6883      	ldr	r3, [r0, #8]
		(const struct uart_driver_api *)dev->api;

	api->poll_out(dev, out_char);
    1dd0:	685b      	ldr	r3, [r3, #4]
    1dd2:	4798      	blx	r3
	for (size_t i = 0; i < length; i++) {
    1dd4:	3401      	adds	r4, #1
    1dd6:	e7f5      	b.n	1dc4 <char_out+0x8>
#endif
	}

	return length;
}
    1dd8:	4628      	mov	r0, r5
    1dda:	bd70      	pop	{r4, r5, r6, pc}
    1ddc:	2000048c 	.word	0x2000048c

00001de0 <log_backend_uart_init>:
	}
}

static void log_backend_uart_init(struct log_backend const *const backend)
{
	uart_dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_console));
    1de0:	4b01      	ldr	r3, [pc, #4]	; (1de8 <log_backend_uart_init+0x8>)
    1de2:	4a02      	ldr	r2, [pc, #8]	; (1dec <log_backend_uart_init+0xc>)
    1de4:	601a      	str	r2, [r3, #0]
		 */
		for (int i = 0; i < sizeof(LOG_HEX_SEP); i++) {
			uart_poll_out(uart_dev, LOG_HEX_SEP[i]);
		}
	}
}
    1de6:	4770      	bx	lr
    1de8:	2000048c 	.word	0x2000048c
    1dec:	00008184 	.word	0x00008184

00001df0 <panic>:

static void panic(struct log_backend const *const backend)
{
    1df0:	b508      	push	{r3, lr}
 * @param output	Log output instance.
 */
static inline void
log_backend_std_panic(const struct log_output *const output)
{
	log_output_flush(output);
    1df2:	4802      	ldr	r0, [pc, #8]	; (1dfc <panic+0xc>)
    1df4:	f005 f9d3 	bl	719e <log_output_flush>
	log_backend_std_panic(&log_output_uart);
}
    1df8:	bd08      	pop	{r3, pc}
    1dfa:	bf00      	nop
    1dfc:	00008678 	.word	0x00008678

00001e00 <dropped>:

static void dropped(const struct log_backend *const backend, uint32_t cnt)
{
    1e00:	b508      	push	{r3, lr}
 * @param cnt		Number of dropped messages.
 */
static inline void
log_backend_std_dropped(const struct log_output *const output, uint32_t cnt)
{
	log_output_dropped_process(output, cnt);
    1e02:	4802      	ldr	r0, [pc, #8]	; (1e0c <dropped+0xc>)
    1e04:	f7ff ff98 	bl	1d38 <log_output_dropped_process>
	if (IS_ENABLED(CONFIG_LOG_BACKEND_UART_OUTPUT_DICTIONARY)) {
		log_dict_output_dropped_process(&log_output_uart, cnt);
	} else {
		log_backend_std_dropped(&log_output_uart, cnt);
	}
}
    1e08:	bd08      	pop	{r3, pc}
    1e0a:	bf00      	nop
    1e0c:	00008678 	.word	0x00008678

00001e10 <put>:
{
    1e10:	b510      	push	{r4, lr}
    1e12:	460c      	mov	r4, r1
	log_msg_get(msg);
    1e14:	4608      	mov	r0, r1
    1e16:	f004 ffdc 	bl	6dd2 <log_msg_get>
	log_output_msg_process(output, msg, flags);
    1e1a:	220f      	movs	r2, #15
    1e1c:	4621      	mov	r1, r4
    1e1e:	4803      	ldr	r0, [pc, #12]	; (1e2c <put+0x1c>)
    1e20:	f005 f9e6 	bl	71f0 <log_output_msg_process>
	log_msg_put(msg);
    1e24:	4620      	mov	r0, r4
    1e26:	f004 fff8 	bl	6e1a <log_msg_put>
}
    1e2a:	bd10      	pop	{r4, pc}
    1e2c:	00008678 	.word	0x00008678

00001e30 <log_backend_rtt_init>:
{
	if (CONFIG_LOG_BACKEND_RTT_BUFFER > 0) {
		log_backend_rtt_cfg();
	}

	host_present = true;
    1e30:	4b01      	ldr	r3, [pc, #4]	; (1e38 <log_backend_rtt_init+0x8>)
    1e32:	2201      	movs	r2, #1
    1e34:	701a      	strb	r2, [r3, #0]
	line_pos = line_buf;
}
    1e36:	4770      	bx	lr
    1e38:	20000b85 	.word	0x20000b85

00001e3c <on_failed_write>:
{
    1e3c:	b508      	push	{r3, lr}
	if (retry_cnt == 0) {
    1e3e:	b918      	cbnz	r0, 1e48 <on_failed_write+0xc>
		host_present = false;
    1e40:	4b08      	ldr	r3, [pc, #32]	; (1e64 <on_failed_write+0x28>)
    1e42:	2200      	movs	r2, #0
    1e44:	701a      	strb	r2, [r3, #0]
}
    1e46:	bd08      	pop	{r3, pc}
	return IS_ENABLED(CONFIG_LOG_IMMEDIATE) || panic_mode;
    1e48:	4b07      	ldr	r3, [pc, #28]	; (1e68 <on_failed_write+0x2c>)
    1e4a:	781b      	ldrb	r3, [r3, #0]
	} else if (is_sync_mode()) {
    1e4c:	b123      	cbz	r3, 1e58 <on_failed_write+0x1c>
	z_impl_k_busy_wait(usec_to_wait);
    1e4e:	f241 3088 	movw	r0, #5000	; 0x1388
    1e52:	f006 f8e0 	bl	8016 <z_impl_k_busy_wait>
}
    1e56:	e7f6      	b.n	1e46 <on_failed_write+0xa>
	return z_impl_k_sleep(timeout);
    1e58:	20a4      	movs	r0, #164	; 0xa4
    1e5a:	2100      	movs	r1, #0
    1e5c:	f004 fa52 	bl	6304 <z_impl_k_sleep>
}
    1e60:	e7f1      	b.n	1e46 <on_failed_write+0xa>
    1e62:	bf00      	nop
    1e64:	20000b85 	.word	0x20000b85
    1e68:	20000b86 	.word	0x20000b86

00001e6c <on_write>:
{
    1e6c:	b538      	push	{r3, r4, r5, lr}
    1e6e:	4604      	mov	r4, r0
	host_present = true;
    1e70:	4b0a      	ldr	r3, [pc, #40]	; (1e9c <on_write+0x30>)
    1e72:	2201      	movs	r2, #1
    1e74:	701a      	strb	r2, [r3, #0]
	return panic_mode;
    1e76:	4b0a      	ldr	r3, [pc, #40]	; (1ea0 <on_write+0x34>)
    1e78:	781b      	ldrb	r3, [r3, #0]
	if (is_panic_mode()) {
    1e7a:	b903      	cbnz	r3, 1e7e <on_write+0x12>
}
    1e7c:	bd38      	pop	{r3, r4, r5, pc}
		while (SEGGER_RTT_HasDataUp(CONFIG_LOG_BACKEND_RTT_BUFFER) &&
    1e7e:	2000      	movs	r0, #0
    1e80:	f003 f8d6 	bl	5030 <SEGGER_RTT_HasDataUp>
    1e84:	2800      	cmp	r0, #0
    1e86:	d0f9      	beq.n	1e7c <on_write+0x10>
    1e88:	4b04      	ldr	r3, [pc, #16]	; (1e9c <on_write+0x30>)
    1e8a:	781b      	ldrb	r3, [r3, #0]
    1e8c:	2b00      	cmp	r3, #0
    1e8e:	d0f5      	beq.n	1e7c <on_write+0x10>
			on_failed_write(retry_cnt--);
    1e90:	1e65      	subs	r5, r4, #1
    1e92:	4620      	mov	r0, r4
    1e94:	f7ff ffd2 	bl	1e3c <on_failed_write>
    1e98:	462c      	mov	r4, r5
    1e9a:	e7f0      	b.n	1e7e <on_write+0x12>
    1e9c:	20000b85 	.word	0x20000b85
    1ea0:	20000b86 	.word	0x20000b86

00001ea4 <data_out_block_mode>:
{
    1ea4:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    1ea8:	4606      	mov	r6, r0
    1eaa:	460d      	mov	r5, r1
	int retry_cnt = IS_ENABLED(CONFIG_LOG_BACKEND_RTT_MODE_BLOCK) ?
    1eac:	2704      	movs	r7, #4
    1eae:	e00d      	b.n	1ecc <data_out_block_mode+0x28>
			ret = SEGGER_RTT_WriteSkipNoLock(CONFIG_LOG_BACKEND_RTT_BUFFER,
    1eb0:	462a      	mov	r2, r5
    1eb2:	4631      	mov	r1, r6
    1eb4:	2000      	movs	r0, #0
    1eb6:	f003 f857 	bl	4f68 <SEGGER_RTT_WriteSkipNoLock>
    1eba:	4604      	mov	r4, r0
    1ebc:	e01c      	b.n	1ef8 <data_out_block_mode+0x54>
			on_write(retry_cnt);
    1ebe:	4638      	mov	r0, r7
    1ec0:	f7ff ffd4 	bl	1e6c <on_write>
	} while ((ret == 0) && host_present);
    1ec4:	bb1c      	cbnz	r4, 1f0e <data_out_block_mode+0x6a>
    1ec6:	4b16      	ldr	r3, [pc, #88]	; (1f20 <data_out_block_mode+0x7c>)
    1ec8:	781b      	ldrb	r3, [r3, #0]
    1eca:	b303      	cbz	r3, 1f0e <data_out_block_mode+0x6a>
	return IS_ENABLED(CONFIG_LOG_IMMEDIATE) || panic_mode;
    1ecc:	4b15      	ldr	r3, [pc, #84]	; (1f24 <data_out_block_mode+0x80>)
    1ece:	781b      	ldrb	r3, [r3, #0]
		if (!is_sync_mode()) {
    1ed0:	2b00      	cmp	r3, #0
    1ed2:	d1ed      	bne.n	1eb0 <data_out_block_mode+0xc>
	return z_impl_k_mutex_lock(mutex, timeout);
    1ed4:	f8df 8050 	ldr.w	r8, [pc, #80]	; 1f28 <data_out_block_mode+0x84>
    1ed8:	f04f 32ff 	mov.w	r2, #4294967295
    1edc:	f04f 33ff 	mov.w	r3, #4294967295
    1ee0:	4640      	mov	r0, r8
    1ee2:	f003 fbfb 	bl	56dc <z_impl_k_mutex_lock>
			ret = SEGGER_RTT_WriteSkipNoLock(CONFIG_LOG_BACKEND_RTT_BUFFER,
    1ee6:	462a      	mov	r2, r5
    1ee8:	4631      	mov	r1, r6
    1eea:	2000      	movs	r0, #0
    1eec:	f003 f83c 	bl	4f68 <SEGGER_RTT_WriteSkipNoLock>
    1ef0:	4604      	mov	r4, r0
	return z_impl_k_mutex_unlock(mutex);
    1ef2:	4640      	mov	r0, r8
    1ef4:	f003 fc7c 	bl	57f0 <z_impl_k_mutex_unlock>
		if (ret) {
    1ef8:	2c00      	cmp	r4, #0
    1efa:	d1e0      	bne.n	1ebe <data_out_block_mode+0x1a>
		} else if (host_present) {
    1efc:	4b08      	ldr	r3, [pc, #32]	; (1f20 <data_out_block_mode+0x7c>)
    1efe:	781b      	ldrb	r3, [r3, #0]
    1f00:	2b00      	cmp	r3, #0
    1f02:	d0df      	beq.n	1ec4 <data_out_block_mode+0x20>
			retry_cnt--;
    1f04:	3f01      	subs	r7, #1
			on_failed_write(retry_cnt);
    1f06:	4638      	mov	r0, r7
    1f08:	f7ff ff98 	bl	1e3c <on_failed_write>
    1f0c:	e7da      	b.n	1ec4 <data_out_block_mode+0x20>
	return ((ret == 0) && host_present) ? 0 : length;
    1f0e:	b914      	cbnz	r4, 1f16 <data_out_block_mode+0x72>
    1f10:	4b03      	ldr	r3, [pc, #12]	; (1f20 <data_out_block_mode+0x7c>)
    1f12:	781b      	ldrb	r3, [r3, #0]
    1f14:	b903      	cbnz	r3, 1f18 <data_out_block_mode+0x74>
    1f16:	462c      	mov	r4, r5
}
    1f18:	4620      	mov	r0, r4
    1f1a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    1f1e:	bf00      	nop
    1f20:	20000b85 	.word	0x20000b85
    1f24:	20000b86 	.word	0x20000b86
    1f28:	200000b0 	.word	0x200000b0

00001f2c <panic>:

static void panic(struct log_backend const *const backend)
{
    1f2c:	b508      	push	{r3, lr}
	panic_mode = true;
    1f2e:	4b03      	ldr	r3, [pc, #12]	; (1f3c <panic+0x10>)
    1f30:	2201      	movs	r2, #1
    1f32:	701a      	strb	r2, [r3, #0]
	log_output_flush(output);
    1f34:	4802      	ldr	r0, [pc, #8]	; (1f40 <panic+0x14>)
    1f36:	f005 f932 	bl	719e <log_output_flush>
	log_backend_std_panic(&log_output_rtt);
}
    1f3a:	bd08      	pop	{r3, pc}
    1f3c:	20000b86 	.word	0x20000b86
    1f40:	000086b4 	.word	0x000086b4

00001f44 <dropped>:

static void dropped(const struct log_backend *const backend, uint32_t cnt)
{
    1f44:	b508      	push	{r3, lr}
	log_output_dropped_process(output, cnt);
    1f46:	4802      	ldr	r0, [pc, #8]	; (1f50 <dropped+0xc>)
    1f48:	f7ff fef6 	bl	1d38 <log_output_dropped_process>
	ARG_UNUSED(backend);

	log_backend_std_dropped(&log_output_rtt, cnt);
}
    1f4c:	bd08      	pop	{r3, pc}
    1f4e:	bf00      	nop
    1f50:	000086b4 	.word	0x000086b4

00001f54 <put>:
{
    1f54:	b510      	push	{r4, lr}
    1f56:	460c      	mov	r4, r1
	log_msg_get(msg);
    1f58:	4608      	mov	r0, r1
    1f5a:	f004 ff3a 	bl	6dd2 <log_msg_get>
	log_output_msg_process(output, msg, flags);
    1f5e:	220f      	movs	r2, #15
    1f60:	4621      	mov	r1, r4
    1f62:	4803      	ldr	r0, [pc, #12]	; (1f70 <put+0x1c>)
    1f64:	f005 f944 	bl	71f0 <log_output_msg_process>
	log_msg_put(msg);
    1f68:	4620      	mov	r0, r4
    1f6a:	f004 ff56 	bl	6e1a <log_msg_put>
}
    1f6e:	bd10      	pop	{r4, pc}
    1f70:	000086b4 	.word	0x000086b4

00001f74 <__do_init_array_aux>:
 * @brief Execute initialization routines referenced in .init_array section
 *
 * @return N/A
 */
void __do_init_array_aux(void)
{
    1f74:	b510      	push	{r4, lr}
	for (func_ptr *func = __init_array_start;
    1f76:	4c04      	ldr	r4, [pc, #16]	; (1f88 <__do_init_array_aux+0x14>)
    1f78:	4b04      	ldr	r3, [pc, #16]	; (1f8c <__do_init_array_aux+0x18>)
    1f7a:	429c      	cmp	r4, r3
    1f7c:	d203      	bcs.n	1f86 <__do_init_array_aux+0x12>
		func < __init_array_end;
		func++) {
		(*func)();
    1f7e:	f854 3b04 	ldr.w	r3, [r4], #4
    1f82:	4798      	blx	r3
		func++) {
    1f84:	e7f8      	b.n	1f78 <__do_init_array_aux+0x4>
	}
}
    1f86:	bd10      	pop	{r4, pc}
    1f88:	0000839c 	.word	0x0000839c
    1f8c:	0000839c 	.word	0x0000839c

00001f90 <__do_global_ctors_aux>:
 */
void __do_global_ctors_aux(void)
{
	unsigned int nCtors;

	nCtors = (unsigned long)__CTOR_LIST__[0];
    1f90:	4b06      	ldr	r3, [pc, #24]	; (1fac <__do_global_ctors_aux+0x1c>)
    1f92:	681b      	ldr	r3, [r3, #0]

	while (nCtors >= 1U) {
    1f94:	b14b      	cbz	r3, 1faa <__do_global_ctors_aux+0x1a>
{
    1f96:	b510      	push	{r4, lr}
		__CTOR_LIST__[nCtors--]();
    1f98:	1e5c      	subs	r4, r3, #1
    1f9a:	4a04      	ldr	r2, [pc, #16]	; (1fac <__do_global_ctors_aux+0x1c>)
    1f9c:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
    1fa0:	4798      	blx	r3
    1fa2:	4623      	mov	r3, r4
	while (nCtors >= 1U) {
    1fa4:	2c00      	cmp	r4, #0
    1fa6:	d1f7      	bne.n	1f98 <__do_global_ctors_aux+0x8>
	}
}
    1fa8:	bd10      	pop	{r4, pc}
    1faa:	4770      	bx	lr
    1fac:	00008394 	.word	0x00008394

00001fb0 <pm_system_resume>:
	 * and it may schedule another thread.
	 *
	 * Call pm_idle_exit_notification_disable() if this
	 * notification is not required.
	 */
	if (!post_ops_done) {
    1fb0:	4b1b      	ldr	r3, [pc, #108]	; (2020 <pm_system_resume+0x70>)
    1fb2:	681b      	ldr	r3, [r3, #0]
    1fb4:	2b00      	cmp	r3, #0
    1fb6:	d132      	bne.n	201e <pm_system_resume+0x6e>
{
    1fb8:	b530      	push	{r4, r5, lr}
    1fba:	b085      	sub	sp, #20
		post_ops_done = 1;
    1fbc:	4b18      	ldr	r3, [pc, #96]	; (2020 <pm_system_resume+0x70>)
    1fbe:	2201      	movs	r2, #1
    1fc0:	601a      	str	r2, [r3, #0]
		exit_pos_ops(z_power_state);
    1fc2:	4b18      	ldr	r3, [pc, #96]	; (2024 <pm_system_resume+0x74>)
    1fc4:	e893 0007 	ldmia.w	r3, {r0, r1, r2}
    1fc8:	ab04      	add	r3, sp, #16
    1fca:	e903 0007 	stmdb	r3, {r0, r1, r2}
	if (pm_power_state_exit_post_ops != NULL) {
    1fce:	4b16      	ldr	r3, [pc, #88]	; (2028 <pm_system_resume+0x78>)
    1fd0:	b163      	cbz	r3, 1fec <pm_system_resume+0x3c>
		pm_power_state_exit_post_ops(info);
    1fd2:	f005 f9e8 	bl	73a6 <pm_power_state_exit_post_ops>
	__asm__ volatile(
    1fd6:	f04f 0320 	mov.w	r3, #32
    1fda:	f3ef 8511 	mrs	r5, BASEPRI
    1fde:	f383 8812 	msr	BASEPRI_MAX, r3
    1fe2:	f3bf 8f6f 	isb	sy
    1fe6:	4b11      	ldr	r3, [pc, #68]	; (202c <pm_system_resume+0x7c>)
    1fe8:	681c      	ldr	r4, [r3, #0]
    1fea:	e00a      	b.n	2002 <pm_system_resume+0x52>
	__asm__ volatile(
    1fec:	2300      	movs	r3, #0
    1fee:	f383 8811 	msr	BASEPRI, r3
    1ff2:	f3bf 8f6f 	isb	sy
}
    1ff6:	e7ee      	b.n	1fd6 <pm_system_resume+0x26>
	SYS_SLIST_FOR_EACH_CONTAINER(&pm_notifiers, notifier, _node) {
    1ff8:	4623      	mov	r3, r4
 *
 * @return a pointer on the next node (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_next(sys_snode_t *node);

Z_GENLIST_PEEK_NEXT(slist, snode)
    1ffa:	b10c      	cbz	r4, 2000 <pm_system_resume+0x50>
	return node->next;
    1ffc:	6823      	ldr	r3, [r4, #0]
    1ffe:	b143      	cbz	r3, 2012 <pm_system_resume+0x62>
{
    2000:	461c      	mov	r4, r3
	SYS_SLIST_FOR_EACH_CONTAINER(&pm_notifiers, notifier, _node) {
    2002:	b134      	cbz	r4, 2012 <pm_system_resume+0x62>
			callback = notifier->state_exit;
    2004:	68a3      	ldr	r3, [r4, #8]
		if (callback) {
    2006:	2b00      	cmp	r3, #0
    2008:	d0f6      	beq.n	1ff8 <pm_system_resume+0x48>
			callback(z_power_state.state);
    200a:	4a06      	ldr	r2, [pc, #24]	; (2024 <pm_system_resume+0x74>)
    200c:	7810      	ldrb	r0, [r2, #0]
    200e:	4798      	blx	r3
    2010:	e7f2      	b.n	1ff8 <pm_system_resume+0x48>
	__asm__ volatile(
    2012:	f385 8811 	msr	BASEPRI, r5
    2016:	f3bf 8f6f 	isb	sy
		pm_state_notify(false);
	}
}
    201a:	b005      	add	sp, #20
    201c:	bd30      	pop	{r4, r5, pc}
    201e:	4770      	bx	lr
    2020:	20000008 	.word	0x20000008
    2024:	200004bc 	.word	0x200004bc
    2028:	000073a7 	.word	0x000073a7
    202c:	200004b4 	.word	0x200004b4

00002030 <pm_system_suspend>:
	return PM_STATE_ACTIVE;
}
#endif

enum pm_state pm_system_suspend(int32_t ticks)
{
    2030:	b570      	push	{r4, r5, r6, lr}
    2032:	b088      	sub	sp, #32
    2034:	4606      	mov	r6, r0
	SYS_PORT_TRACING_FUNC_ENTER(pm, system_suspend, ticks);
	z_power_state = pm_policy_next_state(ticks);
    2036:	4c2a      	ldr	r4, [pc, #168]	; (20e0 <pm_system_suspend+0xb0>)
    2038:	466d      	mov	r5, sp
    203a:	4601      	mov	r1, r0
    203c:	4628      	mov	r0, r5
    203e:	f005 f91c 	bl	727a <pm_policy_next_state>
    2042:	e895 0007 	ldmia.w	r5, {r0, r1, r2}
    2046:	e884 0007 	stmia.w	r4, {r0, r1, r2}
	if (z_power_state.state == PM_STATE_ACTIVE) {
    204a:	7820      	ldrb	r0, [r4, #0]
    204c:	2800      	cmp	r0, #0
    204e:	d045      	beq.n	20dc <pm_system_suspend+0xac>
		LOG_DBG("No PM operations done.");
		SYS_PORT_TRACING_FUNC_EXIT(pm, system_suspend, ticks, z_power_state.state);
		return z_power_state.state;
	}
	post_ops_done = 0;
    2050:	4b24      	ldr	r3, [pc, #144]	; (20e4 <pm_system_suspend+0xb4>)
    2052:	2200      	movs	r2, #0
    2054:	601a      	str	r2, [r3, #0]

	if (ticks != K_TICKS_FOREVER) {
    2056:	f1b6 3fff 	cmp.w	r6, #4294967295
    205a:	d10c      	bne.n	2076 <pm_system_suspend+0x46>
	 * state. We don't want to be scheduled out yet, first we need
	 * to send a notification about leaving the idle state. So,
	 * we lock the scheduler here and unlock just after we have
	 * sent the notification in pm_system_resume().
	 */
	k_sched_lock();
    205c:	f003 fe3e 	bl	5cdc <k_sched_lock>
	__asm__ volatile(
    2060:	f04f 0320 	mov.w	r3, #32
    2064:	f3ef 8511 	mrs	r5, BASEPRI
    2068:	f383 8812 	msr	BASEPRI_MAX, r3
    206c:	f3bf 8f6f 	isb	sy
	return list->head;
    2070:	4b1d      	ldr	r3, [pc, #116]	; (20e8 <pm_system_suspend+0xb8>)
    2072:	681c      	ldr	r4, [r3, #0]
    2074:	e016      	b.n	20a4 <pm_system_suspend+0x74>
		     k_us_to_ticks_ceil32(z_power_state.exit_latency_us), true);
    2076:	68a3      	ldr	r3, [r4, #8]
		} else {
			return t * ((uint64_t)to_hz / from_hz);
		}
	} else {
		if (result32) {
			return (uint32_t)((t * to_hz + off) / from_hz);
    2078:	0c59      	lsrs	r1, r3, #17
    207a:	03d8      	lsls	r0, r3, #15
    207c:	4c1b      	ldr	r4, [pc, #108]	; (20ec <pm_system_suspend+0xbc>)
    207e:	4a1c      	ldr	r2, [pc, #112]	; (20f0 <pm_system_suspend+0xc0>)
    2080:	2300      	movs	r3, #0
    2082:	1900      	adds	r0, r0, r4
    2084:	f04f 0400 	mov.w	r4, #0
    2088:	eb44 0101 	adc.w	r1, r4, r1
    208c:	f7fe f838 	bl	100 <__aeabi_uldivmod>
		z_set_timeout_expiry(ticks -
    2090:	2101      	movs	r1, #1
    2092:	1a30      	subs	r0, r6, r0
    2094:	f005 ff90 	bl	7fb8 <z_set_timeout_expiry>
    2098:	e7e0      	b.n	205c <pm_system_suspend+0x2c>
	SYS_SLIST_FOR_EACH_CONTAINER(&pm_notifiers, notifier, _node) {
    209a:	4623      	mov	r3, r4
Z_GENLIST_PEEK_NEXT(slist, snode)
    209c:	b10c      	cbz	r4, 20a2 <pm_system_suspend+0x72>
	return node->next;
    209e:	6823      	ldr	r3, [r4, #0]
    20a0:	b143      	cbz	r3, 20b4 <pm_system_suspend+0x84>
{
    20a2:	461c      	mov	r4, r3
	SYS_SLIST_FOR_EACH_CONTAINER(&pm_notifiers, notifier, _node) {
    20a4:	b134      	cbz	r4, 20b4 <pm_system_suspend+0x84>
			callback = notifier->state_entry;
    20a6:	6863      	ldr	r3, [r4, #4]
		if (callback) {
    20a8:	2b00      	cmp	r3, #0
    20aa:	d0f6      	beq.n	209a <pm_system_suspend+0x6a>
			callback(z_power_state.state);
    20ac:	4a0c      	ldr	r2, [pc, #48]	; (20e0 <pm_system_suspend+0xb0>)
    20ae:	7810      	ldrb	r0, [r2, #0]
    20b0:	4798      	blx	r3
    20b2:	e7f2      	b.n	209a <pm_system_suspend+0x6a>
	__asm__ volatile(
    20b4:	f385 8811 	msr	BASEPRI, r5
    20b8:	f3bf 8f6f 	isb	sy
	pm_debug_start_timer();
	/* Enter power state */
	pm_state_notify(true);
	pm_state_set(z_power_state);
    20bc:	4b08      	ldr	r3, [pc, #32]	; (20e0 <pm_system_suspend+0xb0>)
    20be:	e893 0007 	ldmia.w	r3, {r0, r1, r2}
    20c2:	ab08      	add	r3, sp, #32
    20c4:	e903 0007 	stmdb	r3, {r0, r1, r2}
	if (pm_power_state_set != NULL) {
    20c8:	4b0a      	ldr	r3, [pc, #40]	; (20f4 <pm_system_suspend+0xc4>)
    20ca:	b10b      	cbz	r3, 20d0 <pm_system_suspend+0xa0>
		pm_power_state_set(info);
    20cc:	f005 f958 	bl	7380 <pm_power_state_set>
		/* Turn on peripherals and restore device states as necessary */
		pm_resume_devices();
	}
#endif
	pm_log_debug_info(z_power_state.state);
	pm_system_resume();
    20d0:	f7ff ff6e 	bl	1fb0 <pm_system_resume>
	k_sched_unlock();
    20d4:	f004 f800 	bl	60d8 <k_sched_unlock>
	SYS_PORT_TRACING_FUNC_EXIT(pm, system_suspend, ticks, z_power_state.state);
	return z_power_state.state;
    20d8:	4b01      	ldr	r3, [pc, #4]	; (20e0 <pm_system_suspend+0xb0>)
    20da:	7818      	ldrb	r0, [r3, #0]
}
    20dc:	b008      	add	sp, #32
    20de:	bd70      	pop	{r4, r5, r6, pc}
    20e0:	200004bc 	.word	0x200004bc
    20e4:	20000008 	.word	0x20000008
    20e8:	200004b4 	.word	0x200004b4
    20ec:	000f423f 	.word	0x000f423f
    20f0:	000f4240 	.word	0x000f4240
    20f4:	00007381 	.word	0x00007381

000020f8 <z_arm_cpu_idle_init>:
 * void z_arm_cpu_idle_init(void);
 */

SECTION_FUNC(TEXT, z_arm_cpu_idle_init)
#if defined(CONFIG_CPU_CORTEX_M)
	ldr	r1, =_SCB_SCR
    20f8:	4901      	ldr	r1, [pc, #4]	; (2100 <z_arm_cpu_idle_init+0x8>)
	movs.n	r2, #_SCR_INIT_BITS
    20fa:	2210      	movs	r2, #16
	str	r2, [r1]
    20fc:	600a      	str	r2, [r1, #0]
#endif
	bx	lr
    20fe:	4770      	bx	lr
	ldr	r1, =_SCB_SCR
    2100:	e000ed10 	.word	0xe000ed10

00002104 <arch_cpu_idle>:
	 * before entering low power state.
	 *
	 * Set PRIMASK before configuring BASEPRI to prevent interruption
	 * before wake-up.
	 */
	cpsid	i
    2104:	b672      	cpsid	i

	/*
	 * Set wake-up interrupt priority to the lowest and synchronise to
	 * ensure that this is visible to the WFI instruction.
	 */
	eors.n	r0, r0
    2106:	4040      	eors	r0, r0
	msr	BASEPRI, r0
    2108:	f380 8811 	msr	BASEPRI, r0
	isb
    210c:	f3bf 8f6f 	isb	sy

	/*
	 * Wait for all memory transactions to complete before entering low
	 * power state.
	 */
	dsb
    2110:	f3bf 8f4f 	dsb	sy

	/* Enter low power state */
	wfi
    2114:	bf30      	wfi

	/*
	 * Clear PRIMASK and flush instruction buffer to immediately service
	 * the wake-up interrupt.
	 */
	cpsie	i
    2116:	b662      	cpsie	i
	isb
    2118:	f3bf 8f6f 	isb	sy

	bx	lr
    211c:	4770      	bx	lr
    211e:	bf00      	nop

00002120 <arch_cpu_atomic_idle>:

	/*
	 * Lock PRIMASK while sleeping: wfe will still get interrupted by
	 * incoming interrupts but the CPU will not service them right away.
	 */
	cpsid	i
    2120:	b672      	cpsid	i
	cpsie	i
_irq_disabled:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* r1: zero, for setting BASEPRI (needs a register) */
	eors.n	r1, r1
    2122:	4049      	eors	r1, r1

	/* unlock BASEPRI so wfe gets interrupted by incoming interrupts */
	msr	BASEPRI, r1
    2124:	f381 8811 	msr	BASEPRI, r1

	wfe
    2128:	bf20      	wfe

	msr	BASEPRI, r0
    212a:	f380 8811 	msr	BASEPRI, r0
	cpsie	i
    212e:	b662      	cpsie	i
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
	bx	lr
    2130:	4770      	bx	lr
    2132:	bf00      	nop

00002134 <esf_dump>:
#include <kernel_arch_data.h>
#include <logging/log.h>
LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);

static void esf_dump(const z_arch_esf_t *esf)
{
    2134:	b570      	push	{r4, r5, r6, lr}
    2136:	b082      	sub	sp, #8
    2138:	4604      	mov	r4, r0
	return ((uint8_t *)data - (uint8_t *)__log_const_start)/
    213a:	4d1f      	ldr	r5, [pc, #124]	; (21b8 <esf_dump+0x84>)
    213c:	4b1f      	ldr	r3, [pc, #124]	; (21bc <esf_dump+0x88>)
    213e:	1aed      	subs	r5, r5, r3
    2140:	08ed      	lsrs	r5, r5, #3
	LOG_ERR("r0/a1:  0x%08x  r1/a2:  0x%08x  r2/a3:  0x%08x",
    2142:	2601      	movs	r6, #1
    2144:	f04f 0300 	mov.w	r3, #0
    2148:	f366 0302 	bfi	r3, r6, #0, #3
    214c:	f36f 03c5 	bfc	r3, #3, #3
    2150:	f365 138f 	bfi	r3, r5, #6, #10
    2154:	f8ad 3000 	strh.w	r3, [sp]
    2158:	6883      	ldr	r3, [r0, #8]
    215a:	6842      	ldr	r2, [r0, #4]
    215c:	6801      	ldr	r1, [r0, #0]
    215e:	4818      	ldr	r0, [pc, #96]	; (21c0 <esf_dump+0x8c>)
    2160:	f7ff fa86 	bl	1670 <log_3>
		esf->basic.a1, esf->basic.a2, esf->basic.a3);
	LOG_ERR("r3/a4:  0x%08x r12/ip:  0x%08x r14/lr:  0x%08x",
    2164:	f04f 0300 	mov.w	r3, #0
    2168:	f366 0302 	bfi	r3, r6, #0, #3
    216c:	f36f 03c5 	bfc	r3, #3, #3
    2170:	f365 138f 	bfi	r3, r5, #6, #10
    2174:	f8ad 3000 	strh.w	r3, [sp]
    2178:	6963      	ldr	r3, [r4, #20]
    217a:	6922      	ldr	r2, [r4, #16]
    217c:	68e1      	ldr	r1, [r4, #12]
    217e:	4811      	ldr	r0, [pc, #68]	; (21c4 <esf_dump+0x90>)
    2180:	f7ff fa76 	bl	1670 <log_3>
		esf->basic.a4, esf->basic.ip, esf->basic.lr);
	LOG_ERR(" xpsr:  0x%08x", esf->basic.xpsr);
    2184:	f04f 0200 	mov.w	r2, #0
    2188:	f366 0202 	bfi	r2, r6, #0, #3
    218c:	f36f 02c5 	bfc	r2, #3, #3
    2190:	f365 128f 	bfi	r2, r5, #6, #10
    2194:	69e1      	ldr	r1, [r4, #28]
    2196:	480c      	ldr	r0, [pc, #48]	; (21c8 <esf_dump+0x94>)
    2198:	f7ff faa8 	bl	16ec <log_1>
	}

	LOG_ERR("EXC_RETURN: 0x%0x", esf->extra_info.exc_return);

#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
	LOG_ERR("Faulting instruction address (r15/pc): 0x%08x",
    219c:	f04f 0200 	mov.w	r2, #0
    21a0:	f366 0202 	bfi	r2, r6, #0, #3
    21a4:	f36f 02c5 	bfc	r2, #3, #3
    21a8:	f365 128f 	bfi	r2, r5, #6, #10
    21ac:	69a1      	ldr	r1, [r4, #24]
    21ae:	4807      	ldr	r0, [pc, #28]	; (21cc <esf_dump+0x98>)
    21b0:	f7ff fa9c 	bl	16ec <log_1>
		esf->basic.pc);
}
    21b4:	b002      	add	sp, #8
    21b6:	bd70      	pop	{r4, r5, r6, pc}
    21b8:	000083d4 	.word	0x000083d4
    21bc:	0000839c 	.word	0x0000839c
    21c0:	000086cc 	.word	0x000086cc
    21c4:	000086fc 	.word	0x000086fc
    21c8:	0000872c 	.word	0x0000872c
    21cc:	0000873c 	.word	0x0000873c

000021d0 <arch_irq_enable>:
#define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
#define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)

void arch_irq_enable(unsigned int irq)
{
	NVIC_EnableIRQ((IRQn_Type)irq);
    21d0:	b243      	sxtb	r3, r0
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
    21d2:	2b00      	cmp	r3, #0
    21d4:	db08      	blt.n	21e8 <arch_irq_enable+0x18>
  {
    __COMPILER_BARRIER();
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    21d6:	f000 001f 	and.w	r0, r0, #31
    21da:	095b      	lsrs	r3, r3, #5
    21dc:	2201      	movs	r2, #1
    21de:	fa02 f000 	lsl.w	r0, r2, r0
    21e2:	4a02      	ldr	r2, [pc, #8]	; (21ec <arch_irq_enable+0x1c>)
    21e4:	f842 0023 	str.w	r0, [r2, r3, lsl #2]
}
    21e8:	4770      	bx	lr
    21ea:	bf00      	nop
    21ec:	e000e100 	.word	0xe000e100

000021f0 <arch_irq_is_enabled>:
	NVIC_DisableIRQ((IRQn_Type)irq);
}

int arch_irq_is_enabled(unsigned int irq)
{
	return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq));
    21f0:	0942      	lsrs	r2, r0, #5
    21f2:	4b05      	ldr	r3, [pc, #20]	; (2208 <arch_irq_is_enabled+0x18>)
    21f4:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
    21f8:	f000 001f 	and.w	r0, r0, #31
    21fc:	2301      	movs	r3, #1
    21fe:	fa03 f000 	lsl.w	r0, r3, r0
}
    2202:	4010      	ands	r0, r2
    2204:	4770      	bx	lr
    2206:	bf00      	nop
    2208:	e000e100 	.word	0xe000e100

0000220c <z_arm_irq_priority_set>:
	 * via flags
	 */
	if (IS_ENABLED(CONFIG_ZERO_LATENCY_IRQS) && (flags & IRQ_ZERO_LATENCY)) {
		prio = _EXC_ZERO_LATENCY_IRQS_PRIO;
	} else {
		prio += _IRQ_PRIO_OFFSET;
    220c:	3101      	adds	r1, #1
	 */
	__ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1),
		 "invalid priority %d for %d irq! values must be less than %lu\n",
		 prio - _IRQ_PRIO_OFFSET, irq,
		 BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
	NVIC_SetPriority((IRQn_Type)irq, prio);
    220e:	b243      	sxtb	r3, r0
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
  if ((int32_t)(IRQn) >= 0)
    2210:	2b00      	cmp	r3, #0
    2212:	db08      	blt.n	2226 <z_arm_irq_priority_set+0x1a>
  {
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    2214:	0149      	lsls	r1, r1, #5
    2216:	b2c9      	uxtb	r1, r1
    2218:	f103 4360 	add.w	r3, r3, #3758096384	; 0xe0000000
    221c:	f503 4361 	add.w	r3, r3, #57600	; 0xe100
    2220:	f883 1300 	strb.w	r1, [r3, #768]	; 0x300
    2224:	4770      	bx	lr
  }
  else
  {
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    2226:	f000 000f 	and.w	r0, r0, #15
    222a:	0149      	lsls	r1, r1, #5
    222c:	b2c9      	uxtb	r1, r1
    222e:	4b01      	ldr	r3, [pc, #4]	; (2234 <z_arm_irq_priority_set+0x28>)
    2230:	5419      	strb	r1, [r3, r0]
}
    2232:	4770      	bx	lr
    2234:	e000ed14 	.word	0xe000ed14

00002238 <z_SysNmiOnReset>:
_ASM_FILE_PROLOGUE

GTEXT(z_SysNmiOnReset)

SECTION_FUNC(TEXT, z_SysNmiOnReset)
    wfi
    2238:	bf30      	wfi
    b z_SysNmiOnReset
    223a:	f7ff bffd 	b.w	2238 <z_SysNmiOnReset>
    223e:	bf00      	nop

00002240 <z_arm_prep_c>:
 * This routine prepares for the execution of and runs C code.
 *
 * @return N/A
 */
void z_arm_prep_c(void)
{
    2240:	b508      	push	{r3, lr}
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    2242:	4b0b      	ldr	r3, [pc, #44]	; (2270 <z_arm_prep_c+0x30>)
    2244:	4a0b      	ldr	r2, [pc, #44]	; (2274 <z_arm_prep_c+0x34>)
    2246:	f022 027f 	bic.w	r2, r2, #127	; 0x7f
    224a:	609a      	str	r2, [r3, #8]
  \details Acts as a special kind of Data Memory Barrier.
           It completes when all explicit memory accesses before this instruction complete.
 */
__STATIC_FORCEINLINE void __DSB(void)
{
  __ASM volatile ("dsb 0xF":::"memory");
    224c:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    2250:	f3bf 8f6f 	isb	sy
	SCB->CPACR &= (~(CPACR_CP10_Msk | CPACR_CP11_Msk));
    2254:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
    2258:	f422 0270 	bic.w	r2, r2, #15728640	; 0xf00000
    225c:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
	relocate_vector_table();
#if defined(CONFIG_CPU_HAS_FPU)
	z_arm_floating_point_init();
#endif
	z_bss_zero();
    2260:	f003 f8a0 	bl	53a4 <z_bss_zero>
	z_data_copy();
    2264:	f004 f8ca 	bl	63fc <z_data_copy>
#if defined(CONFIG_ARMV7_R) && defined(CONFIG_INIT_STACKS)
	z_arm_init_stacks();
#endif
	z_arm_interrupt_init();
    2268:	f000 fc66 	bl	2b38 <z_arm_interrupt_init>
	z_cstart();
    226c:	f003 f8a6 	bl	53bc <z_cstart>
    2270:	e000ed00 	.word	0xe000ed00
    2274:	00000000 	.word	0x00000000

00002278 <arch_swap>:
 * as BASEPRI is not available.
 */
int arch_swap(unsigned int key)
{
	/* store off key and return value */
	_current->arch.basepri = key;
    2278:	4a0a      	ldr	r2, [pc, #40]	; (22a4 <arch_swap+0x2c>)
    227a:	6893      	ldr	r3, [r2, #8]
    227c:	f8c3 00a8 	str.w	r0, [r3, #168]	; 0xa8
	_current->arch.swap_return_value = _k_neg_eagain;
    2280:	4909      	ldr	r1, [pc, #36]	; (22a8 <arch_swap+0x30>)
    2282:	6809      	ldr	r1, [r1, #0]
    2284:	f8c3 10ac 	str.w	r1, [r3, #172]	; 0xac

#if defined(CONFIG_CPU_CORTEX_M)
	/* set pending bit to make sure we will take a PendSV exception */
	SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    2288:	4908      	ldr	r1, [pc, #32]	; (22ac <arch_swap+0x34>)
    228a:	684b      	ldr	r3, [r1, #4]
    228c:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
    2290:	604b      	str	r3, [r1, #4]
    2292:	2300      	movs	r3, #0
    2294:	f383 8811 	msr	BASEPRI, r3
    2298:	f3bf 8f6f 	isb	sy
#endif

	/* Context switch is performed here. Returning implies the
	 * thread has been context-switched-in again.
	 */
	return _current->arch.swap_return_value;
    229c:	6893      	ldr	r3, [r2, #8]
}
    229e:	f8d3 00ac 	ldr.w	r0, [r3, #172]	; 0xac
    22a2:	4770      	bx	lr
    22a4:	20000b2c 	.word	0x20000b2c
    22a8:	00008d80 	.word	0x00008d80
    22ac:	e000ed00 	.word	0xe000ed00

000022b0 <z_arm_pendsv>:
    pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_INSTRUMENT_THREAD_SWITCHING */

    /* load _kernel into r1 and current k_thread into r2 */
    ldr r1, =_kernel
    22b0:	4910      	ldr	r1, [pc, #64]	; (22f4 <z_arm_pendsv+0x44>)
    ldr r2, [r1, #_kernel_offset_to_current]
    22b2:	688a      	ldr	r2, [r1, #8]
    /* Store LSB of LR (EXC_RETURN) to the thread's 'mode' word. */
    strb lr, [r2, #_thread_offset_to_mode_exc_return]
#endif

    /* addr of callee-saved regs in thread in r0 */
    ldr r0, =_thread_offset_to_callee_saved
    22b4:	f04f 0030 	mov.w	r0, #48	; 0x30
    add r0, r2
    22b8:	4410      	add	r0, r2

    /* save callee-saved + psp in thread */
#if defined(CONFIG_CPU_CORTEX_M)
    mrs ip, PSP
    22ba:	f3ef 8c09 	mrs	ip, PSP
    mov r6, r11
    mov r7, ip
    /* store r8-12 */
    stmea r0!, {r3-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    stmia r0, {v1-v8, ip}
    22be:	e880 1ff0 	stmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}

    /* Protect the kernel state while we play with the thread lists */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    22c2:	2020      	movs	r0, #32
    msr BASEPRI_MAX, r0
    22c4:	f380 8812 	msr	BASEPRI_MAX, r0
    isb /* Make the effect of disabling interrupts be realized immediately */
    22c8:	f3bf 8f6f 	isb	sy
     * the new thread is context-switched in since all decisions
     * to pend PendSV have been taken with the current kernel
     * state and this is what we're handling currently.
     */
#if defined(CONFIG_CPU_CORTEX_M)
    ldr v4, =_SCS_ICSR
    22cc:	4f0a      	ldr	r7, [pc, #40]	; (22f8 <z_arm_pendsv+0x48>)
    ldr v3, =_SCS_ICSR_UNPENDSV
    22ce:	f04f 6600 	mov.w	r6, #134217728	; 0x8000000
#endif

    /* _kernel is still in r1 */

    /* fetch the thread to run from the ready queue cache */
    ldr r2, [r1, #_kernel_offset_to_ready_q_cache]
    22d2:	69ca      	ldr	r2, [r1, #28]

    str r2, [r1, #_kernel_offset_to_current]
    22d4:	608a      	str	r2, [r1, #8]
     * has been handled.
     */

    /* _SCS_ICSR is still in v4 and _SCS_ICSR_UNPENDSV in v3 */
#if defined(CONFIG_CPU_CORTEX_M)
    str v3, [v4, #0]
    22d6:	603e      	str	r6, [r7, #0]

    ldr r0, [r4]
    movs.n r3, #0
    str r3, [r4]
#else
    ldr r0, [r2, #_thread_offset_to_basepri]
    22d8:	f8d2 00a8 	ldr.w	r0, [r2, #168]	; 0xa8
    movs r3, #0
    22dc:	2300      	movs	r3, #0
    str r3, [r2, #_thread_offset_to_basepri]
    22de:	f8c2 30a8 	str.w	r3, [r2, #168]	; 0xa8
    /* restore r4-r7, go back 9*4 bytes to the start of the stored block */
    subs r0, #36
    ldmia r0!, {r4-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    /* restore BASEPRI for the incoming thread */
    msr BASEPRI, r0
    22e2:	f380 8811 	msr	BASEPRI, r0
    isb

#endif

    /* load callee-saved + psp from thread */
    add r0, r2, #_thread_offset_to_callee_saved
    22e6:	f102 0030 	add.w	r0, r2, #48	; 0x30
    ldmia r0, {v1-v8, ip}
    22ea:	e890 1ff0 	ldmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
    msr PSP, ip
    22ee:	f38c 8809 	msr	PSP, ip

    /*
     * Cortex-M: return from PendSV exception
     * Cortex-R: return to the caller (z_arm_{exc,int}_exit, or z_arm_svc)
     */
    bx lr
    22f2:	4770      	bx	lr
    ldr r1, =_kernel
    22f4:	20000b2c 	.word	0x20000b2c
    ldr v4, =_SCS_ICSR
    22f8:	e000ed04 	.word	0xe000ed04

000022fc <z_arm_svc>:
  bne _stack_frame_endif
_stack_frame_msp:
  mrs r0, MSP
_stack_frame_endif:
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    tst lr, #_EXC_RETURN_SPSEL_Msk /* did we come from thread mode ? */
    22fc:	f01e 0f04 	tst.w	lr, #4
    ite eq  /* if zero (equal), came from handler mode */
    2300:	bf0c      	ite	eq
        mrseq r0, MSP   /* handler mode, stack frame is on MSP */
    2302:	f3ef 8008 	mrseq	r0, MSP
        mrsne r0, PSP   /* thread mode, stack frame is on PSP */
    2306:	f3ef 8009 	mrsne	r0, PSP
#endif


    /* Figure out what SVC call number was invoked */

    ldr r1, [r0, #24]   /* grab address of PC from stack frame */
    230a:	6981      	ldr	r1, [r0, #24]
     */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    subs r1, r1, #2
    ldrb r1, [r1]
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    ldrb r1, [r1, #-2]
    230c:	f811 1c02 	ldrb.w	r1, [r1, #-2]
#endif
    bne _oops

#endif /* CONFIG_USERSPACE */

    cmp r1, #2
    2310:	2902      	cmp	r1, #2
    beq _oops
    2312:	d0ff      	beq.n	2314 <_oops>

00002314 <_oops>:
    /* exception return is done in z_arm_int_exit() */
    b z_arm_int_exit
#endif

_oops:
    push {r0, lr}
    2314:	b501      	push	{r0, lr}
    bl z_do_kernel_oops
    2316:	f004 ffc1 	bl	729c <z_do_kernel_oops>
    /* return from SVC exception is done here */
    pop {r0, pc}
    231a:	bd01      	pop	{r0, pc}

0000231c <arch_new_thread>:
 * of the ESF.
 */
void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
		     char *stack_ptr, k_thread_entry_t entry,
		     void *p1, void *p2, void *p3)
{
    231c:	b410      	push	{r4}
		thread->stack_info.size -= FP_GUARD_EXTRA_SIZE;
	}
#endif /* FP_GUARD_EXTRA_SIZE */
#endif /* CONFIG_MPU_STACK_GUARD */

	iframe = Z_STACK_PTR_TO_FRAME(struct __basic_sf, stack_ptr);
    231e:	f1a2 0420 	sub.w	r4, r2, #32
		iframe->pc = (uint32_t)arch_user_mode_enter;
	} else {
		iframe->pc = (uint32_t)z_thread_entry;
	}
#else
	iframe->pc = (uint32_t)z_thread_entry;
    2322:	490d      	ldr	r1, [pc, #52]	; (2358 <arch_new_thread+0x3c>)
#endif

#if defined(CONFIG_CPU_CORTEX_M)
	/* force ARM mode by clearing LSB of address */
	iframe->pc &= 0xfffffffe;
    2324:	f021 0101 	bic.w	r1, r1, #1
    2328:	f842 1c08 	str.w	r1, [r2, #-8]
#endif
	iframe->a1 = (uint32_t)entry;
    232c:	f842 3c20 	str.w	r3, [r2, #-32]
	iframe->a2 = (uint32_t)p1;
    2330:	9b01      	ldr	r3, [sp, #4]
    2332:	f842 3c1c 	str.w	r3, [r2, #-28]
	iframe->a3 = (uint32_t)p2;
    2336:	9b02      	ldr	r3, [sp, #8]
    2338:	f842 3c18 	str.w	r3, [r2, #-24]
	iframe->a4 = (uint32_t)p3;
    233c:	9b03      	ldr	r3, [sp, #12]
    233e:	f842 3c14 	str.w	r3, [r2, #-20]

#if defined(CONFIG_CPU_CORTEX_M)
	iframe->xpsr =
    2342:	f04f 7380 	mov.w	r3, #16777216	; 0x1000000
    2346:	f842 3c04 	str.w	r3, [r2, #-4]
#if defined(CONFIG_COMPILER_ISA_THUMB2)
	iframe->xpsr |= T_BIT;
#endif /* CONFIG_COMPILER_ISA_THUMB2 */
#endif /* CONFIG_CPU_CORTEX_M */

	thread->callee_saved.psp = (uint32_t)iframe;
    234a:	6504      	str	r4, [r0, #80]	; 0x50
	thread->arch.basepri = 0;
    234c:	2300      	movs	r3, #0
    234e:	f8c0 30a8 	str.w	r3, [r0, #168]	; 0xa8
#endif
	/*
	 * initial values in all other registers/thread entries are
	 * irrelevant.
	 */
}
    2352:	bc10      	pop	{r4}
    2354:	4770      	bx	lr
    2356:	bf00      	nop
    2358:	00006c67 	.word	0x00006c67

0000235c <arch_switch_to_main_thread>:
void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr,
				k_thread_entry_t _main)
{
	z_arm_prepare_switch_to_main();

	_current = main_thread;
    235c:	4b07      	ldr	r3, [pc, #28]	; (237c <arch_switch_to_main_thread+0x20>)
    235e:	6098      	str	r0, [r3, #8]

	/*
	 * Set PSP to the highest address of the main stack
	 * before enabling interrupts and jumping to main.
	 */
	__asm__ volatile (
    2360:	4610      	mov	r0, r2
    2362:	f381 8809 	msr	PSP, r1
    2366:	2100      	movs	r1, #0
    2368:	b663      	cpsie	if
    236a:	f381 8811 	msr	BASEPRI, r1
    236e:	f3bf 8f6f 	isb	sy
    2372:	2200      	movs	r2, #0
    2374:	2300      	movs	r3, #0
    2376:	f004 fc76 	bl	6c66 <z_thread_entry>
	:
	: "r" (_main), "r" (stack_ptr)
	: "r0" /* not to be overwritten by msr PSP, %1 */
	);

	CODE_UNREACHABLE;
    237a:	bf00      	nop
    237c:	20000b2c 	.word	0x20000b2c

00002380 <_isr_wrapper>:
 * @return N/A
 */
SECTION_FUNC(TEXT, _isr_wrapper)

#if defined(CONFIG_CPU_CORTEX_M)
	push {r0,lr}		/* r0, lr are now the first items on the stack */
    2380:	b501      	push	{r0, lr}
	 * Disable interrupts to prevent nesting while exiting idle state. This
	 * is only necessary for the Cortex-M because it is the only ARM
	 * architecture variant that automatically enables interrupts when
	 * entering an ISR.
	 */
	cpsid i  /* PRIMASK = 1 */
    2382:	b672      	cpsid	i
#endif

	/* is this a wakeup from idle ? */
	ldr r2, =_kernel
    2384:	4a0b      	ldr	r2, [pc, #44]	; (23b4 <_isr_wrapper+0x34>)
	/* requested idle duration, in ticks */
	ldr r0, [r2, #_kernel_offset_to_idle]
    2386:	6990      	ldr	r0, [r2, #24]
	cmp r0, #0
    2388:	2800      	cmp	r0, #0
	str r1, [r2, #_kernel_offset_to_idle]
	bl z_pm_save_idle_exit
_idle_state_cleared:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	ittt ne
    238a:	bf1e      	ittt	ne
	movne	r1, #0
    238c:	2100      	movne	r1, #0
		/* clear kernel idle state */
		strne	r1, [r2, #_kernel_offset_to_idle]
    238e:	6191      	strne	r1, [r2, #24]
		blne	z_pm_save_idle_exit
    2390:	f005 fbf4 	blne	7b7c <z_pm_save_idle_exit>
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
	cpsie i		/* re-enable interrupts (PRIMASK = 0) */
    2394:	b662      	cpsie	i
#endif

#endif /* CONFIG_PM */

#if defined(CONFIG_CPU_CORTEX_M)
	mrs r0, IPSR	/* get exception number */
    2396:	f3ef 8005 	mrs	r0, IPSR
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r1, =16
	subs r0, r1	/* get IRQ number */
	lsls r0, #3	/* table is 8-byte wide */
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	sub r0, r0, #16	/* get IRQ number */
    239a:	f1a0 0010 	sub.w	r0, r0, #16
	lsl r0, r0, #3	/* table is 8-byte wide */
    239e:	ea4f 00c0 	mov.w	r0, r0, lsl #3
	lsl r1, r1, #3
	cmp r0, r1
	bge spurious_continue
#endif /* !CONFIG_CPU_CORTEX_M */

	ldr r1, =_sw_isr_table
    23a2:	4905      	ldr	r1, [pc, #20]	; (23b8 <_isr_wrapper+0x38>)
	add r1, r1, r0	/* table entry: ISRs must have their MSB set to stay
    23a4:	4401      	add	r1, r0
			 * in thumb mode */

	ldm r1!,{r0,r3}	/* arg in r0, ISR in r3 */
    23a6:	c909      	ldmia	r1!, {r0, r3}
	blx r3		/* call ISR */
    23a8:	4798      	blx	r3

#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	pop {r0, r3}
	mov lr, r3
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	pop {r0, lr}
    23aa:	e8bd 4001 	ldmia.w	sp!, {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

	/* Use 'bx' instead of 'b' because 'bx' can jump further, and use
	 * 'bx' instead of 'blx' because exception return is done in
	 * z_arm_int_exit() */
	ldr r1, =z_arm_int_exit
    23ae:	4903      	ldr	r1, [pc, #12]	; (23bc <_isr_wrapper+0x3c>)
	bx r1
    23b0:	4708      	bx	r1
    23b2:	0000      	.short	0x0000
	ldr r2, =_kernel
    23b4:	20000b2c 	.word	0x20000b2c
	ldr r1, =_sw_isr_table
    23b8:	00008214 	.word	0x00008214
	ldr r1, =z_arm_int_exit
    23bc:	000023c1 	.word	0x000023c1

000023c0 <z_arm_exc_exit>:
 */

SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_exc_exit)

#ifdef CONFIG_PREEMPT_ENABLED
	ldr r3, =_kernel
    23c0:	4b04      	ldr	r3, [pc, #16]	; (23d4 <_EXIT_EXC+0x2>)

	ldr r1, [r3, #_kernel_offset_to_current]
    23c2:	6899      	ldr	r1, [r3, #8]
	ldr r0, [r3, #_kernel_offset_to_ready_q_cache]
    23c4:	69d8      	ldr	r0, [r3, #28]
	cmp r0, r1
    23c6:	4288      	cmp	r0, r1
	beq _EXIT_EXC
    23c8:	d003      	beq.n	23d2 <_EXIT_EXC>

	/* context switch required, pend the PendSV exception */
	ldr r1, =_SCS_ICSR
    23ca:	4903      	ldr	r1, [pc, #12]	; (23d8 <_EXIT_EXC+0x6>)
	ldr r2, =_SCS_ICSR_PENDSV
    23cc:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
	str r2, [r1]
    23d0:	600a      	str	r2, [r1, #0]

000023d2 <_EXIT_EXC>:
#else
	pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_STACK_SENTINEL */

	bx lr
    23d2:	4770      	bx	lr
	ldr r3, =_kernel
    23d4:	20000b2c 	.word	0x20000b2c
	ldr r1, =_SCS_ICSR
    23d8:	e000ed04 	.word	0xe000ed04

000023dc <usage_fault>:
 * See z_arm_fault_dump() for example.
 *
 * @return error code to identify the fatal error reason
 */
static uint32_t usage_fault(const z_arch_esf_t *esf)
{
    23dc:	b508      	push	{r3, lr}
    23de:	4b4e      	ldr	r3, [pc, #312]	; (2518 <usage_fault+0x13c>)
    23e0:	4a4e      	ldr	r2, [pc, #312]	; (251c <usage_fault+0x140>)
    23e2:	1a9b      	subs	r3, r3, r2
    23e4:	08db      	lsrs	r3, r3, #3
	uint32_t reason = K_ERR_CPU_EXCEPTION;

	PR_FAULT_INFO("***** USAGE FAULT *****");
    23e6:	f04f 0100 	mov.w	r1, #0
    23ea:	2201      	movs	r2, #1
    23ec:	f362 0102 	bfi	r1, r2, #0, #3
    23f0:	f36f 01c5 	bfc	r1, #3, #3
    23f4:	f363 118f 	bfi	r1, r3, #6, #10
    23f8:	4849      	ldr	r0, [pc, #292]	; (2520 <usage_fault+0x144>)
    23fa:	f7ff f9e9 	bl	17d0 <log_0>

	/* bits are sticky: they stack and must be reset */
	if ((SCB->CFSR & SCB_CFSR_DIVBYZERO_Msk) != 0) {
    23fe:	4b49      	ldr	r3, [pc, #292]	; (2524 <usage_fault+0x148>)
    2400:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    2402:	f013 7f00 	tst.w	r3, #33554432	; 0x2000000
    2406:	d121      	bne.n	244c <usage_fault+0x70>
		PR_FAULT_INFO("  Division by zero");
	}
	if ((SCB->CFSR & SCB_CFSR_UNALIGNED_Msk) != 0) {
    2408:	4b46      	ldr	r3, [pc, #280]	; (2524 <usage_fault+0x148>)
    240a:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    240c:	f013 7f80 	tst.w	r3, #16777216	; 0x1000000
    2410:	d12d      	bne.n	246e <usage_fault+0x92>
		 */
		reason = K_ERR_STACK_CHK_FAIL;
#endif /* CONFIG_BUILTIN_STACK_GUARD */
	}
#endif /* CONFIG_ARMV8_M_MAINLINE */
	if ((SCB->CFSR & SCB_CFSR_NOCP_Msk) != 0) {
    2412:	4b44      	ldr	r3, [pc, #272]	; (2524 <usage_fault+0x148>)
    2414:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    2416:	f413 2f00 	tst.w	r3, #524288	; 0x80000
    241a:	d139      	bne.n	2490 <usage_fault+0xb4>
		PR_FAULT_INFO("  No coprocessor instructions");
	}
	if ((SCB->CFSR & SCB_CFSR_INVPC_Msk) != 0) {
    241c:	4b41      	ldr	r3, [pc, #260]	; (2524 <usage_fault+0x148>)
    241e:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    2420:	f413 2f80 	tst.w	r3, #262144	; 0x40000
    2424:	d145      	bne.n	24b2 <usage_fault+0xd6>
		PR_FAULT_INFO("  Illegal load of EXC_RETURN into PC");
	}
	if ((SCB->CFSR & SCB_CFSR_INVSTATE_Msk) != 0) {
    2426:	4b3f      	ldr	r3, [pc, #252]	; (2524 <usage_fault+0x148>)
    2428:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    242a:	f413 3f00 	tst.w	r3, #131072	; 0x20000
    242e:	d151      	bne.n	24d4 <usage_fault+0xf8>
		PR_FAULT_INFO("  Illegal use of the EPSR");
	}
	if ((SCB->CFSR & SCB_CFSR_UNDEFINSTR_Msk) != 0) {
    2430:	4b3c      	ldr	r3, [pc, #240]	; (2524 <usage_fault+0x148>)
    2432:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    2434:	f413 3f80 	tst.w	r3, #65536	; 0x10000
    2438:	d15d      	bne.n	24f6 <usage_fault+0x11a>
		PR_FAULT_INFO("  Attempt to execute undefined instruction");
	}

	/* clear UFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    243a:	4a3a      	ldr	r2, [pc, #232]	; (2524 <usage_fault+0x148>)
    243c:	6a93      	ldr	r3, [r2, #40]	; 0x28
    243e:	ea6f 4303 	mvn.w	r3, r3, lsl #16
    2442:	ea6f 4313 	mvn.w	r3, r3, lsr #16
    2446:	6293      	str	r3, [r2, #40]	; 0x28

	return reason;
}
    2448:	2000      	movs	r0, #0
    244a:	bd08      	pop	{r3, pc}
    244c:	4b32      	ldr	r3, [pc, #200]	; (2518 <usage_fault+0x13c>)
    244e:	4a33      	ldr	r2, [pc, #204]	; (251c <usage_fault+0x140>)
    2450:	1a9b      	subs	r3, r3, r2
    2452:	08db      	lsrs	r3, r3, #3
		PR_FAULT_INFO("  Division by zero");
    2454:	f04f 0100 	mov.w	r1, #0
    2458:	2201      	movs	r2, #1
    245a:	f362 0102 	bfi	r1, r2, #0, #3
    245e:	f36f 01c5 	bfc	r1, #3, #3
    2462:	f363 118f 	bfi	r1, r3, #6, #10
    2466:	4830      	ldr	r0, [pc, #192]	; (2528 <usage_fault+0x14c>)
    2468:	f7ff f9b2 	bl	17d0 <log_0>
    246c:	e7cc      	b.n	2408 <usage_fault+0x2c>
    246e:	4b2a      	ldr	r3, [pc, #168]	; (2518 <usage_fault+0x13c>)
    2470:	4a2a      	ldr	r2, [pc, #168]	; (251c <usage_fault+0x140>)
    2472:	1a9b      	subs	r3, r3, r2
    2474:	08db      	lsrs	r3, r3, #3
		PR_FAULT_INFO("  Unaligned memory access");
    2476:	f04f 0100 	mov.w	r1, #0
    247a:	2201      	movs	r2, #1
    247c:	f362 0102 	bfi	r1, r2, #0, #3
    2480:	f36f 01c5 	bfc	r1, #3, #3
    2484:	f363 118f 	bfi	r1, r3, #6, #10
    2488:	4828      	ldr	r0, [pc, #160]	; (252c <usage_fault+0x150>)
    248a:	f7ff f9a1 	bl	17d0 <log_0>
    248e:	e7c0      	b.n	2412 <usage_fault+0x36>
    2490:	4b21      	ldr	r3, [pc, #132]	; (2518 <usage_fault+0x13c>)
    2492:	4a22      	ldr	r2, [pc, #136]	; (251c <usage_fault+0x140>)
    2494:	1a9b      	subs	r3, r3, r2
    2496:	08db      	lsrs	r3, r3, #3
		PR_FAULT_INFO("  No coprocessor instructions");
    2498:	f04f 0100 	mov.w	r1, #0
    249c:	2201      	movs	r2, #1
    249e:	f362 0102 	bfi	r1, r2, #0, #3
    24a2:	f36f 01c5 	bfc	r1, #3, #3
    24a6:	f363 118f 	bfi	r1, r3, #6, #10
    24aa:	4821      	ldr	r0, [pc, #132]	; (2530 <usage_fault+0x154>)
    24ac:	f7ff f990 	bl	17d0 <log_0>
    24b0:	e7b4      	b.n	241c <usage_fault+0x40>
    24b2:	4b19      	ldr	r3, [pc, #100]	; (2518 <usage_fault+0x13c>)
    24b4:	4a19      	ldr	r2, [pc, #100]	; (251c <usage_fault+0x140>)
    24b6:	1a9b      	subs	r3, r3, r2
    24b8:	08db      	lsrs	r3, r3, #3
		PR_FAULT_INFO("  Illegal load of EXC_RETURN into PC");
    24ba:	f04f 0100 	mov.w	r1, #0
    24be:	2201      	movs	r2, #1
    24c0:	f362 0102 	bfi	r1, r2, #0, #3
    24c4:	f36f 01c5 	bfc	r1, #3, #3
    24c8:	f363 118f 	bfi	r1, r3, #6, #10
    24cc:	4819      	ldr	r0, [pc, #100]	; (2534 <usage_fault+0x158>)
    24ce:	f7ff f97f 	bl	17d0 <log_0>
    24d2:	e7a8      	b.n	2426 <usage_fault+0x4a>
    24d4:	4b10      	ldr	r3, [pc, #64]	; (2518 <usage_fault+0x13c>)
    24d6:	4a11      	ldr	r2, [pc, #68]	; (251c <usage_fault+0x140>)
    24d8:	1a9b      	subs	r3, r3, r2
    24da:	08db      	lsrs	r3, r3, #3
		PR_FAULT_INFO("  Illegal use of the EPSR");
    24dc:	f04f 0100 	mov.w	r1, #0
    24e0:	2201      	movs	r2, #1
    24e2:	f362 0102 	bfi	r1, r2, #0, #3
    24e6:	f36f 01c5 	bfc	r1, #3, #3
    24ea:	f363 118f 	bfi	r1, r3, #6, #10
    24ee:	4812      	ldr	r0, [pc, #72]	; (2538 <usage_fault+0x15c>)
    24f0:	f7ff f96e 	bl	17d0 <log_0>
    24f4:	e79c      	b.n	2430 <usage_fault+0x54>
    24f6:	4b08      	ldr	r3, [pc, #32]	; (2518 <usage_fault+0x13c>)
    24f8:	4a08      	ldr	r2, [pc, #32]	; (251c <usage_fault+0x140>)
    24fa:	1a9b      	subs	r3, r3, r2
    24fc:	08db      	lsrs	r3, r3, #3
		PR_FAULT_INFO("  Attempt to execute undefined instruction");
    24fe:	f04f 0100 	mov.w	r1, #0
    2502:	2201      	movs	r2, #1
    2504:	f362 0102 	bfi	r1, r2, #0, #3
    2508:	f36f 01c5 	bfc	r1, #3, #3
    250c:	f363 118f 	bfi	r1, r3, #6, #10
    2510:	480a      	ldr	r0, [pc, #40]	; (253c <usage_fault+0x160>)
    2512:	f7ff f95d 	bl	17d0 <log_0>
    2516:	e790      	b.n	243a <usage_fault+0x5e>
    2518:	000083d4 	.word	0x000083d4
    251c:	0000839c 	.word	0x0000839c
    2520:	0000876c 	.word	0x0000876c
    2524:	e000ed00 	.word	0xe000ed00
    2528:	00008784 	.word	0x00008784
    252c:	00008798 	.word	0x00008798
    2530:	000087b4 	.word	0x000087b4
    2534:	000087d4 	.word	0x000087d4
    2538:	000087fc 	.word	0x000087fc
    253c:	00008818 	.word	0x00008818

00002540 <debug_monitor>:
 * See z_arm_fault_dump() for example.
 *
 * @return N/A
 */
static void debug_monitor(z_arch_esf_t *esf, bool *recoverable)
{
    2540:	b508      	push	{r3, lr}
	*recoverable = false;
    2542:	2200      	movs	r2, #0
    2544:	700a      	strb	r2, [r1, #0]
    2546:	4b08      	ldr	r3, [pc, #32]	; (2568 <debug_monitor+0x28>)
    2548:	4908      	ldr	r1, [pc, #32]	; (256c <debug_monitor+0x2c>)
    254a:	1a5b      	subs	r3, r3, r1
    254c:	08db      	lsrs	r3, r3, #3

	PR_FAULT_INFO(
    254e:	f04f 0100 	mov.w	r1, #0
    2552:	2001      	movs	r0, #1
    2554:	f360 0102 	bfi	r1, r0, #0, #3
    2558:	f362 01c5 	bfi	r1, r2, #3, #3
    255c:	f363 118f 	bfi	r1, r3, #6, #10
    2560:	4803      	ldr	r0, [pc, #12]	; (2570 <debug_monitor+0x30>)
    2562:	f7ff f935 	bl	17d0 <log_0>

		*recoverable = memory_fault_recoverable(esf, false);
	}

#endif
}
    2566:	bd08      	pop	{r3, pc}
    2568:	000083d4 	.word	0x000083d4
    256c:	0000839c 	.word	0x0000839c
    2570:	00008844 	.word	0x00008844

00002574 <mem_manage_fault>:
{
    2574:	b570      	push	{r4, r5, r6, lr}
    2576:	4605      	mov	r5, r0
    2578:	460e      	mov	r6, r1
    257a:	4614      	mov	r4, r2
    257c:	4b56      	ldr	r3, [pc, #344]	; (26d8 <mem_manage_fault+0x164>)
    257e:	4a57      	ldr	r2, [pc, #348]	; (26dc <mem_manage_fault+0x168>)
    2580:	1a9b      	subs	r3, r3, r2
    2582:	08db      	lsrs	r3, r3, #3
	PR_FAULT_INFO("***** MPU FAULT *****");
    2584:	f04f 0100 	mov.w	r1, #0
    2588:	2201      	movs	r2, #1
    258a:	f362 0102 	bfi	r1, r2, #0, #3
    258e:	f36f 01c5 	bfc	r1, #3, #3
    2592:	f363 118f 	bfi	r1, r3, #6, #10
    2596:	4852      	ldr	r0, [pc, #328]	; (26e0 <mem_manage_fault+0x16c>)
    2598:	f7ff f91a 	bl	17d0 <log_0>
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
    259c:	4b51      	ldr	r3, [pc, #324]	; (26e4 <mem_manage_fault+0x170>)
    259e:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    25a0:	f013 0f10 	tst.w	r3, #16
    25a4:	d126      	bne.n	25f4 <mem_manage_fault+0x80>
	if ((SCB->CFSR & SCB_CFSR_MUNSTKERR_Msk) != 0) {
    25a6:	4b4f      	ldr	r3, [pc, #316]	; (26e4 <mem_manage_fault+0x170>)
    25a8:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    25aa:	f013 0f08 	tst.w	r3, #8
    25ae:	d132      	bne.n	2616 <mem_manage_fault+0xa2>
	if ((SCB->CFSR & SCB_CFSR_DACCVIOL_Msk) != 0) {
    25b0:	4b4c      	ldr	r3, [pc, #304]	; (26e4 <mem_manage_fault+0x170>)
    25b2:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    25b4:	f013 0f02 	tst.w	r3, #2
    25b8:	d13e      	bne.n	2638 <mem_manage_fault+0xc4>
	if ((SCB->CFSR & SCB_CFSR_IACCVIOL_Msk) != 0) {
    25ba:	4b4a      	ldr	r3, [pc, #296]	; (26e4 <mem_manage_fault+0x170>)
    25bc:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    25be:	f013 0f01 	tst.w	r3, #1
    25c2:	d167      	bne.n	2694 <mem_manage_fault+0x120>
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    25c4:	4b47      	ldr	r3, [pc, #284]	; (26e4 <mem_manage_fault+0x170>)
    25c6:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    25c8:	f013 0f20 	tst.w	r3, #32
    25cc:	d173      	bne.n	26b6 <mem_manage_fault+0x142>
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) ||
    25ce:	4b45      	ldr	r3, [pc, #276]	; (26e4 <mem_manage_fault+0x170>)
    25d0:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    25d2:	f013 0f10 	tst.w	r3, #16
    25d6:	d101      	bne.n	25dc <mem_manage_fault+0x68>
		(SCB->CFSR & SCB_CFSR_DACCVIOL_Msk)) {
    25d8:	4b42      	ldr	r3, [pc, #264]	; (26e4 <mem_manage_fault+0x170>)
    25da:	6a9b      	ldr	r3, [r3, #40]	; 0x28
	SCB->CFSR |= SCB_CFSR_MEMFAULTSR_Msk;
    25dc:	4a41      	ldr	r2, [pc, #260]	; (26e4 <mem_manage_fault+0x170>)
    25de:	6a93      	ldr	r3, [r2, #40]	; 0x28
    25e0:	f043 03ff 	orr.w	r3, r3, #255	; 0xff
    25e4:	6293      	str	r3, [r2, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf, true);
    25e6:	2101      	movs	r1, #1
    25e8:	4628      	mov	r0, r5
    25ea:	f004 fe69 	bl	72c0 <memory_fault_recoverable>
    25ee:	7020      	strb	r0, [r4, #0]
}
    25f0:	2000      	movs	r0, #0
    25f2:	bd70      	pop	{r4, r5, r6, pc}
    25f4:	4b38      	ldr	r3, [pc, #224]	; (26d8 <mem_manage_fault+0x164>)
    25f6:	4a39      	ldr	r2, [pc, #228]	; (26dc <mem_manage_fault+0x168>)
    25f8:	1a9b      	subs	r3, r3, r2
    25fa:	08db      	lsrs	r3, r3, #3
		PR_FAULT_INFO("  Stacking error (context area might be"
    25fc:	f04f 0100 	mov.w	r1, #0
    2600:	2201      	movs	r2, #1
    2602:	f362 0102 	bfi	r1, r2, #0, #3
    2606:	f36f 01c5 	bfc	r1, #3, #3
    260a:	f363 118f 	bfi	r1, r3, #6, #10
    260e:	4836      	ldr	r0, [pc, #216]	; (26e8 <mem_manage_fault+0x174>)
    2610:	f7ff f8de 	bl	17d0 <log_0>
    2614:	e7c7      	b.n	25a6 <mem_manage_fault+0x32>
    2616:	4b30      	ldr	r3, [pc, #192]	; (26d8 <mem_manage_fault+0x164>)
    2618:	4a30      	ldr	r2, [pc, #192]	; (26dc <mem_manage_fault+0x168>)
    261a:	1a9b      	subs	r3, r3, r2
    261c:	08db      	lsrs	r3, r3, #3
		PR_FAULT_INFO("  Unstacking error");
    261e:	f04f 0100 	mov.w	r1, #0
    2622:	2201      	movs	r2, #1
    2624:	f362 0102 	bfi	r1, r2, #0, #3
    2628:	f36f 01c5 	bfc	r1, #3, #3
    262c:	f363 118f 	bfi	r1, r3, #6, #10
    2630:	482e      	ldr	r0, [pc, #184]	; (26ec <mem_manage_fault+0x178>)
    2632:	f7ff f8cd 	bl	17d0 <log_0>
    2636:	e7bb      	b.n	25b0 <mem_manage_fault+0x3c>
    2638:	4b27      	ldr	r3, [pc, #156]	; (26d8 <mem_manage_fault+0x164>)
    263a:	4a28      	ldr	r2, [pc, #160]	; (26dc <mem_manage_fault+0x168>)
    263c:	1a9b      	subs	r3, r3, r2
    263e:	08db      	lsrs	r3, r3, #3
		PR_FAULT_INFO("  Data Access Violation");
    2640:	f04f 0100 	mov.w	r1, #0
    2644:	2201      	movs	r2, #1
    2646:	f362 0102 	bfi	r1, r2, #0, #3
    264a:	f36f 01c5 	bfc	r1, #3, #3
    264e:	f363 118f 	bfi	r1, r3, #6, #10
    2652:	4827      	ldr	r0, [pc, #156]	; (26f0 <mem_manage_fault+0x17c>)
    2654:	f7ff f8bc 	bl	17d0 <log_0>
		uint32_t temp = SCB->MMFAR;
    2658:	4b22      	ldr	r3, [pc, #136]	; (26e4 <mem_manage_fault+0x170>)
    265a:	6b59      	ldr	r1, [r3, #52]	; 0x34
		if ((SCB->CFSR & SCB_CFSR_MMARVALID_Msk) != 0) {
    265c:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    265e:	f013 0f80 	tst.w	r3, #128	; 0x80
    2662:	d0aa      	beq.n	25ba <mem_manage_fault+0x46>
    2664:	4b1c      	ldr	r3, [pc, #112]	; (26d8 <mem_manage_fault+0x164>)
    2666:	4a1d      	ldr	r2, [pc, #116]	; (26dc <mem_manage_fault+0x168>)
    2668:	1a9b      	subs	r3, r3, r2
    266a:	08db      	lsrs	r3, r3, #3
			PR_EXC("  MMFAR Address: 0x%x", mmfar);
    266c:	f04f 0200 	mov.w	r2, #0
    2670:	2001      	movs	r0, #1
    2672:	f360 0202 	bfi	r2, r0, #0, #3
    2676:	f36f 02c5 	bfc	r2, #3, #3
    267a:	f363 128f 	bfi	r2, r3, #6, #10
    267e:	481d      	ldr	r0, [pc, #116]	; (26f4 <mem_manage_fault+0x180>)
    2680:	f7ff f834 	bl	16ec <log_1>
			if (from_hard_fault != 0) {
    2684:	2e00      	cmp	r6, #0
    2686:	d098      	beq.n	25ba <mem_manage_fault+0x46>
				SCB->CFSR &= ~SCB_CFSR_MMARVALID_Msk;
    2688:	4a16      	ldr	r2, [pc, #88]	; (26e4 <mem_manage_fault+0x170>)
    268a:	6a93      	ldr	r3, [r2, #40]	; 0x28
    268c:	f023 0380 	bic.w	r3, r3, #128	; 0x80
    2690:	6293      	str	r3, [r2, #40]	; 0x28
    2692:	e792      	b.n	25ba <mem_manage_fault+0x46>
    2694:	4b10      	ldr	r3, [pc, #64]	; (26d8 <mem_manage_fault+0x164>)
    2696:	4a11      	ldr	r2, [pc, #68]	; (26dc <mem_manage_fault+0x168>)
    2698:	1a9b      	subs	r3, r3, r2
    269a:	08db      	lsrs	r3, r3, #3
		PR_FAULT_INFO("  Instruction Access Violation");
    269c:	f04f 0100 	mov.w	r1, #0
    26a0:	2201      	movs	r2, #1
    26a2:	f362 0102 	bfi	r1, r2, #0, #3
    26a6:	f36f 01c5 	bfc	r1, #3, #3
    26aa:	f363 118f 	bfi	r1, r3, #6, #10
    26ae:	4812      	ldr	r0, [pc, #72]	; (26f8 <mem_manage_fault+0x184>)
    26b0:	f7ff f88e 	bl	17d0 <log_0>
    26b4:	e786      	b.n	25c4 <mem_manage_fault+0x50>
    26b6:	4b08      	ldr	r3, [pc, #32]	; (26d8 <mem_manage_fault+0x164>)
    26b8:	4a08      	ldr	r2, [pc, #32]	; (26dc <mem_manage_fault+0x168>)
    26ba:	1a9b      	subs	r3, r3, r2
    26bc:	08db      	lsrs	r3, r3, #3
		PR_FAULT_INFO(
    26be:	f04f 0100 	mov.w	r1, #0
    26c2:	2201      	movs	r2, #1
    26c4:	f362 0102 	bfi	r1, r2, #0, #3
    26c8:	f36f 01c5 	bfc	r1, #3, #3
    26cc:	f363 118f 	bfi	r1, r3, #6, #10
    26d0:	480a      	ldr	r0, [pc, #40]	; (26fc <mem_manage_fault+0x188>)
    26d2:	f7ff f87d 	bl	17d0 <log_0>
    26d6:	e77a      	b.n	25ce <mem_manage_fault+0x5a>
    26d8:	000083d4 	.word	0x000083d4
    26dc:	0000839c 	.word	0x0000839c
    26e0:	00008868 	.word	0x00008868
    26e4:	e000ed00 	.word	0xe000ed00
    26e8:	00008880 	.word	0x00008880
    26ec:	000088b4 	.word	0x000088b4
    26f0:	000088c8 	.word	0x000088c8
    26f4:	000088e0 	.word	0x000088e0
    26f8:	000088f8 	.word	0x000088f8
    26fc:	00008918 	.word	0x00008918

00002700 <bus_fault>:
{
    2700:	b570      	push	{r4, r5, r6, lr}
    2702:	4605      	mov	r5, r0
    2704:	460e      	mov	r6, r1
    2706:	4614      	mov	r4, r2
    2708:	4b5e      	ldr	r3, [pc, #376]	; (2884 <bus_fault+0x184>)
    270a:	4a5f      	ldr	r2, [pc, #380]	; (2888 <bus_fault+0x188>)
    270c:	1a9b      	subs	r3, r3, r2
    270e:	08db      	lsrs	r3, r3, #3
	PR_FAULT_INFO("***** BUS FAULT *****");
    2710:	f04f 0100 	mov.w	r1, #0
    2714:	2201      	movs	r2, #1
    2716:	f362 0102 	bfi	r1, r2, #0, #3
    271a:	f36f 01c5 	bfc	r1, #3, #3
    271e:	f363 118f 	bfi	r1, r3, #6, #10
    2722:	485a      	ldr	r0, [pc, #360]	; (288c <bus_fault+0x18c>)
    2724:	f7ff f854 	bl	17d0 <log_0>
	if (SCB->CFSR & SCB_CFSR_STKERR_Msk) {
    2728:	4b59      	ldr	r3, [pc, #356]	; (2890 <bus_fault+0x190>)
    272a:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    272c:	f413 5f80 	tst.w	r3, #4096	; 0x1000
    2730:	d124      	bne.n	277c <bus_fault+0x7c>
	if (SCB->CFSR & SCB_CFSR_UNSTKERR_Msk) {
    2732:	4b57      	ldr	r3, [pc, #348]	; (2890 <bus_fault+0x190>)
    2734:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    2736:	f413 6f00 	tst.w	r3, #2048	; 0x800
    273a:	d130      	bne.n	279e <bus_fault+0x9e>
	if (SCB->CFSR & SCB_CFSR_PRECISERR_Msk) {
    273c:	4b54      	ldr	r3, [pc, #336]	; (2890 <bus_fault+0x190>)
    273e:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    2740:	f413 7f00 	tst.w	r3, #512	; 0x200
    2744:	d13c      	bne.n	27c0 <bus_fault+0xc0>
	if (SCB->CFSR & SCB_CFSR_IMPRECISERR_Msk) {
    2746:	4b52      	ldr	r3, [pc, #328]	; (2890 <bus_fault+0x190>)
    2748:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    274a:	f413 6f80 	tst.w	r3, #1024	; 0x400
    274e:	d165      	bne.n	281c <bus_fault+0x11c>
	if ((SCB->CFSR & SCB_CFSR_IBUSERR_Msk) != 0) {
    2750:	4b4f      	ldr	r3, [pc, #316]	; (2890 <bus_fault+0x190>)
    2752:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    2754:	f413 7f80 	tst.w	r3, #256	; 0x100
    2758:	d171      	bne.n	283e <bus_fault+0x13e>
	} else if (SCB->CFSR & SCB_CFSR_LSPERR_Msk) {
    275a:	4b4d      	ldr	r3, [pc, #308]	; (2890 <bus_fault+0x190>)
    275c:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    275e:	f413 5f00 	tst.w	r3, #8192	; 0x2000
    2762:	d17d      	bne.n	2860 <bus_fault+0x160>
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
    2764:	4a4a      	ldr	r2, [pc, #296]	; (2890 <bus_fault+0x190>)
    2766:	6a93      	ldr	r3, [r2, #40]	; 0x28
    2768:	f443 437f 	orr.w	r3, r3, #65280	; 0xff00
    276c:	6293      	str	r3, [r2, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf, true);
    276e:	2101      	movs	r1, #1
    2770:	4628      	mov	r0, r5
    2772:	f004 fda5 	bl	72c0 <memory_fault_recoverable>
    2776:	7020      	strb	r0, [r4, #0]
}
    2778:	2000      	movs	r0, #0
    277a:	bd70      	pop	{r4, r5, r6, pc}
    277c:	4b41      	ldr	r3, [pc, #260]	; (2884 <bus_fault+0x184>)
    277e:	4a42      	ldr	r2, [pc, #264]	; (2888 <bus_fault+0x188>)
    2780:	1a9b      	subs	r3, r3, r2
    2782:	08db      	lsrs	r3, r3, #3
		PR_FAULT_INFO("  Stacking error");
    2784:	f04f 0100 	mov.w	r1, #0
    2788:	2201      	movs	r2, #1
    278a:	f362 0102 	bfi	r1, r2, #0, #3
    278e:	f36f 01c5 	bfc	r1, #3, #3
    2792:	f363 118f 	bfi	r1, r3, #6, #10
    2796:	483f      	ldr	r0, [pc, #252]	; (2894 <bus_fault+0x194>)
    2798:	f7ff f81a 	bl	17d0 <log_0>
    279c:	e7c9      	b.n	2732 <bus_fault+0x32>
    279e:	4b39      	ldr	r3, [pc, #228]	; (2884 <bus_fault+0x184>)
    27a0:	4a39      	ldr	r2, [pc, #228]	; (2888 <bus_fault+0x188>)
    27a2:	1a9b      	subs	r3, r3, r2
    27a4:	08db      	lsrs	r3, r3, #3
		PR_FAULT_INFO("  Unstacking error");
    27a6:	f04f 0100 	mov.w	r1, #0
    27aa:	2201      	movs	r2, #1
    27ac:	f362 0102 	bfi	r1, r2, #0, #3
    27b0:	f36f 01c5 	bfc	r1, #3, #3
    27b4:	f363 118f 	bfi	r1, r3, #6, #10
    27b8:	4837      	ldr	r0, [pc, #220]	; (2898 <bus_fault+0x198>)
    27ba:	f7ff f809 	bl	17d0 <log_0>
    27be:	e7bd      	b.n	273c <bus_fault+0x3c>
    27c0:	4b30      	ldr	r3, [pc, #192]	; (2884 <bus_fault+0x184>)
    27c2:	4a31      	ldr	r2, [pc, #196]	; (2888 <bus_fault+0x188>)
    27c4:	1a9b      	subs	r3, r3, r2
    27c6:	08db      	lsrs	r3, r3, #3
		PR_FAULT_INFO("  Precise data bus error");
    27c8:	f04f 0100 	mov.w	r1, #0
    27cc:	2201      	movs	r2, #1
    27ce:	f362 0102 	bfi	r1, r2, #0, #3
    27d2:	f36f 01c5 	bfc	r1, #3, #3
    27d6:	f363 118f 	bfi	r1, r3, #6, #10
    27da:	4830      	ldr	r0, [pc, #192]	; (289c <bus_fault+0x19c>)
    27dc:	f7fe fff8 	bl	17d0 <log_0>
		STORE_xFAR(bfar, SCB->BFAR);
    27e0:	4b2b      	ldr	r3, [pc, #172]	; (2890 <bus_fault+0x190>)
    27e2:	6b99      	ldr	r1, [r3, #56]	; 0x38
		if ((SCB->CFSR & SCB_CFSR_BFARVALID_Msk) != 0) {
    27e4:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    27e6:	f413 4f00 	tst.w	r3, #32768	; 0x8000
    27ea:	d0ac      	beq.n	2746 <bus_fault+0x46>
    27ec:	4b25      	ldr	r3, [pc, #148]	; (2884 <bus_fault+0x184>)
    27ee:	4a26      	ldr	r2, [pc, #152]	; (2888 <bus_fault+0x188>)
    27f0:	1a9b      	subs	r3, r3, r2
    27f2:	08db      	lsrs	r3, r3, #3
			PR_EXC("  BFAR Address: 0x%x", bfar);
    27f4:	f04f 0200 	mov.w	r2, #0
    27f8:	2001      	movs	r0, #1
    27fa:	f360 0202 	bfi	r2, r0, #0, #3
    27fe:	f36f 02c5 	bfc	r2, #3, #3
    2802:	f363 128f 	bfi	r2, r3, #6, #10
    2806:	4826      	ldr	r0, [pc, #152]	; (28a0 <bus_fault+0x1a0>)
    2808:	f7fe ff70 	bl	16ec <log_1>
			if (from_hard_fault != 0) {
    280c:	2e00      	cmp	r6, #0
    280e:	d09a      	beq.n	2746 <bus_fault+0x46>
				SCB->CFSR &= ~SCB_CFSR_BFARVALID_Msk;
    2810:	4a1f      	ldr	r2, [pc, #124]	; (2890 <bus_fault+0x190>)
    2812:	6a93      	ldr	r3, [r2, #40]	; 0x28
    2814:	f423 4300 	bic.w	r3, r3, #32768	; 0x8000
    2818:	6293      	str	r3, [r2, #40]	; 0x28
    281a:	e794      	b.n	2746 <bus_fault+0x46>
    281c:	4b19      	ldr	r3, [pc, #100]	; (2884 <bus_fault+0x184>)
    281e:	4a1a      	ldr	r2, [pc, #104]	; (2888 <bus_fault+0x188>)
    2820:	1a9b      	subs	r3, r3, r2
    2822:	08db      	lsrs	r3, r3, #3
		PR_FAULT_INFO("  Imprecise data bus error");
    2824:	f04f 0100 	mov.w	r1, #0
    2828:	2201      	movs	r2, #1
    282a:	f362 0102 	bfi	r1, r2, #0, #3
    282e:	f36f 01c5 	bfc	r1, #3, #3
    2832:	f363 118f 	bfi	r1, r3, #6, #10
    2836:	481b      	ldr	r0, [pc, #108]	; (28a4 <bus_fault+0x1a4>)
    2838:	f7fe ffca 	bl	17d0 <log_0>
    283c:	e788      	b.n	2750 <bus_fault+0x50>
    283e:	4b11      	ldr	r3, [pc, #68]	; (2884 <bus_fault+0x184>)
    2840:	4a11      	ldr	r2, [pc, #68]	; (2888 <bus_fault+0x188>)
    2842:	1a9b      	subs	r3, r3, r2
    2844:	08db      	lsrs	r3, r3, #3
		PR_FAULT_INFO("  Instruction bus error");
    2846:	f04f 0100 	mov.w	r1, #0
    284a:	2201      	movs	r2, #1
    284c:	f362 0102 	bfi	r1, r2, #0, #3
    2850:	f36f 01c5 	bfc	r1, #3, #3
    2854:	f363 118f 	bfi	r1, r3, #6, #10
    2858:	4813      	ldr	r0, [pc, #76]	; (28a8 <bus_fault+0x1a8>)
    285a:	f7fe ffb9 	bl	17d0 <log_0>
    285e:	e781      	b.n	2764 <bus_fault+0x64>
    2860:	4b08      	ldr	r3, [pc, #32]	; (2884 <bus_fault+0x184>)
    2862:	4a09      	ldr	r2, [pc, #36]	; (2888 <bus_fault+0x188>)
    2864:	1a9b      	subs	r3, r3, r2
    2866:	08db      	lsrs	r3, r3, #3
		PR_FAULT_INFO("  Floating-point lazy state preservation error");
    2868:	f04f 0100 	mov.w	r1, #0
    286c:	2201      	movs	r2, #1
    286e:	f362 0102 	bfi	r1, r2, #0, #3
    2872:	f36f 01c5 	bfc	r1, #3, #3
    2876:	f363 118f 	bfi	r1, r3, #6, #10
    287a:	480c      	ldr	r0, [pc, #48]	; (28ac <bus_fault+0x1ac>)
    287c:	f7fe ffa8 	bl	17d0 <log_0>
    2880:	e770      	b.n	2764 <bus_fault+0x64>
    2882:	bf00      	nop
    2884:	000083d4 	.word	0x000083d4
    2888:	0000839c 	.word	0x0000839c
    288c:	00008948 	.word	0x00008948
    2890:	e000ed00 	.word	0xe000ed00
    2894:	00008960 	.word	0x00008960
    2898:	000088b4 	.word	0x000088b4
    289c:	00008974 	.word	0x00008974
    28a0:	00008990 	.word	0x00008990
    28a4:	000089a8 	.word	0x000089a8
    28a8:	000089c4 	.word	0x000089c4
    28ac:	00008918 	.word	0x00008918

000028b0 <hard_fault>:
 * See z_arm_fault_dump() for example.
 *
 * @return error code to identify the fatal error reason
 */
static uint32_t hard_fault(z_arch_esf_t *esf, bool *recoverable)
{
    28b0:	b570      	push	{r4, r5, r6, lr}
    28b2:	4605      	mov	r5, r0
    28b4:	460c      	mov	r4, r1
    28b6:	4b47      	ldr	r3, [pc, #284]	; (29d4 <hard_fault+0x124>)
    28b8:	4a47      	ldr	r2, [pc, #284]	; (29d8 <hard_fault+0x128>)
    28ba:	1a9b      	subs	r3, r3, r2
    28bc:	08db      	lsrs	r3, r3, #3
	uint32_t reason = K_ERR_CPU_EXCEPTION;

	PR_FAULT_INFO("***** HARD FAULT *****");
    28be:	f04f 0100 	mov.w	r1, #0
    28c2:	2201      	movs	r2, #1
    28c4:	f362 0102 	bfi	r1, r2, #0, #3
    28c8:	f36f 01c5 	bfc	r1, #3, #3
    28cc:	f363 118f 	bfi	r1, r3, #6, #10
    28d0:	4842      	ldr	r0, [pc, #264]	; (29dc <hard_fault+0x12c>)
    28d2:	f7fe ff7d 	bl	17d0 <log_0>
		reason = esf->basic.r0;
	}

	*recoverable = memory_fault_recoverable(esf, true);
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	*recoverable = false;
    28d6:	2300      	movs	r3, #0
    28d8:	7023      	strb	r3, [r4, #0]

	if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk) != 0) {
    28da:	4b41      	ldr	r3, [pc, #260]	; (29e0 <hard_fault+0x130>)
    28dc:	6ade      	ldr	r6, [r3, #44]	; 0x2c
    28de:	f016 0602 	ands.w	r6, r6, #2
    28e2:	d109      	bne.n	28f8 <hard_fault+0x48>
		PR_EXC("  Bus fault on vector table read");
	} else if ((SCB->HFSR & SCB_HFSR_DEBUGEVT_Msk) != 0) {
    28e4:	4b3e      	ldr	r3, [pc, #248]	; (29e0 <hard_fault+0x130>)
    28e6:	6adb      	ldr	r3, [r3, #44]	; 0x2c
    28e8:	2b00      	cmp	r3, #0
    28ea:	db17      	blt.n	291c <hard_fault+0x6c>
		PR_EXC("  Debug event");
	} else if ((SCB->HFSR & SCB_HFSR_FORCED_Msk) != 0) {
    28ec:	4b3c      	ldr	r3, [pc, #240]	; (29e0 <hard_fault+0x130>)
    28ee:	6ad8      	ldr	r0, [r3, #44]	; 0x2c
    28f0:	f010 4080 	ands.w	r0, r0, #1073741824	; 0x40000000
    28f4:	d124      	bne.n	2940 <hard_fault+0x90>
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

	return reason;
}
    28f6:	bd70      	pop	{r4, r5, r6, pc}
    28f8:	4b36      	ldr	r3, [pc, #216]	; (29d4 <hard_fault+0x124>)
    28fa:	4a37      	ldr	r2, [pc, #220]	; (29d8 <hard_fault+0x128>)
    28fc:	1a9b      	subs	r3, r3, r2
    28fe:	08db      	lsrs	r3, r3, #3
		PR_EXC("  Bus fault on vector table read");
    2900:	f04f 0100 	mov.w	r1, #0
    2904:	2201      	movs	r2, #1
    2906:	f362 0102 	bfi	r1, r2, #0, #3
    290a:	f36f 01c5 	bfc	r1, #3, #3
    290e:	f363 118f 	bfi	r1, r3, #6, #10
    2912:	4834      	ldr	r0, [pc, #208]	; (29e4 <hard_fault+0x134>)
    2914:	f7fe ff5c 	bl	17d0 <log_0>
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    2918:	2000      	movs	r0, #0
    291a:	e7ec      	b.n	28f6 <hard_fault+0x46>
    291c:	4b2d      	ldr	r3, [pc, #180]	; (29d4 <hard_fault+0x124>)
    291e:	4a2e      	ldr	r2, [pc, #184]	; (29d8 <hard_fault+0x128>)
    2920:	1a9b      	subs	r3, r3, r2
    2922:	08db      	lsrs	r3, r3, #3
		PR_EXC("  Debug event");
    2924:	f04f 0100 	mov.w	r1, #0
    2928:	2201      	movs	r2, #1
    292a:	f362 0102 	bfi	r1, r2, #0, #3
    292e:	f36f 01c5 	bfc	r1, #3, #3
    2932:	f363 118f 	bfi	r1, r3, #6, #10
    2936:	482c      	ldr	r0, [pc, #176]	; (29e8 <hard_fault+0x138>)
    2938:	f7fe ff4a 	bl	17d0 <log_0>
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    293c:	4630      	mov	r0, r6
    293e:	e7da      	b.n	28f6 <hard_fault+0x46>
    2940:	4b24      	ldr	r3, [pc, #144]	; (29d4 <hard_fault+0x124>)
    2942:	4a25      	ldr	r2, [pc, #148]	; (29d8 <hard_fault+0x128>)
    2944:	1a9b      	subs	r3, r3, r2
    2946:	08db      	lsrs	r3, r3, #3
		PR_EXC("  Fault escalation (see below)");
    2948:	f04f 0100 	mov.w	r1, #0
    294c:	2201      	movs	r2, #1
    294e:	f362 0102 	bfi	r1, r2, #0, #3
    2952:	f36f 01c5 	bfc	r1, #3, #3
    2956:	f363 118f 	bfi	r1, r3, #6, #10
    295a:	4824      	ldr	r0, [pc, #144]	; (29ec <hard_fault+0x13c>)
    295c:	f7fe ff38 	bl	17d0 <log_0>
	uint16_t *ret_addr = (uint16_t *)esf->basic.pc;
    2960:	69ab      	ldr	r3, [r5, #24]
	uint16_t fault_insn = *(ret_addr - 1);
    2962:	f833 2c02 	ldrh.w	r2, [r3, #-2]
	if (((fault_insn & 0xff00) == _SVC_OPCODE) &&
    2966:	f64d 7302 	movw	r3, #57090	; 0xdf02
    296a:	429a      	cmp	r2, r3
    296c:	d00e      	beq.n	298c <hard_fault+0xdc>
		} else if (SCB_MMFSR != 0) {
    296e:	f103 4360 	add.w	r3, r3, #3758096384	; 0xe0000000
    2972:	f603 6326 	addw	r3, r3, #3622	; 0xe26
    2976:	781b      	ldrb	r3, [r3, #0]
    2978:	b9db      	cbnz	r3, 29b2 <hard_fault+0x102>
		} else if (SCB_BFSR != 0) {
    297a:	4b1d      	ldr	r3, [pc, #116]	; (29f0 <hard_fault+0x140>)
    297c:	781b      	ldrb	r3, [r3, #0]
    297e:	b9f3      	cbnz	r3, 29be <hard_fault+0x10e>
		} else if (SCB_UFSR != 0) {
    2980:	4b1c      	ldr	r3, [pc, #112]	; (29f4 <hard_fault+0x144>)
    2982:	881b      	ldrh	r3, [r3, #0]
    2984:	b29b      	uxth	r3, r3
    2986:	bb03      	cbnz	r3, 29ca <hard_fault+0x11a>
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    2988:	4630      	mov	r0, r6
	return reason;
    298a:	e7b4      	b.n	28f6 <hard_fault+0x46>
    298c:	4b11      	ldr	r3, [pc, #68]	; (29d4 <hard_fault+0x124>)
    298e:	4a12      	ldr	r2, [pc, #72]	; (29d8 <hard_fault+0x128>)
    2990:	1a9b      	subs	r3, r3, r2
    2992:	08db      	lsrs	r3, r3, #3
			PR_EXC("ARCH_EXCEPT with reason %x\n", esf->basic.r0);
    2994:	f04f 0200 	mov.w	r2, #0
    2998:	2101      	movs	r1, #1
    299a:	f361 0202 	bfi	r2, r1, #0, #3
    299e:	f36f 02c5 	bfc	r2, #3, #3
    29a2:	f363 128f 	bfi	r2, r3, #6, #10
    29a6:	6829      	ldr	r1, [r5, #0]
    29a8:	4813      	ldr	r0, [pc, #76]	; (29f8 <hard_fault+0x148>)
    29aa:	f7fe fe9f 	bl	16ec <log_1>
			reason = esf->basic.r0;
    29ae:	6828      	ldr	r0, [r5, #0]
    29b0:	e7a1      	b.n	28f6 <hard_fault+0x46>
			reason = mem_manage_fault(esf, 1, recoverable);
    29b2:	4622      	mov	r2, r4
    29b4:	2101      	movs	r1, #1
    29b6:	4628      	mov	r0, r5
    29b8:	f7ff fddc 	bl	2574 <mem_manage_fault>
    29bc:	e79b      	b.n	28f6 <hard_fault+0x46>
			reason = bus_fault(esf, 1, recoverable);
    29be:	4622      	mov	r2, r4
    29c0:	2101      	movs	r1, #1
    29c2:	4628      	mov	r0, r5
    29c4:	f7ff fe9c 	bl	2700 <bus_fault>
    29c8:	e795      	b.n	28f6 <hard_fault+0x46>
			reason = usage_fault(esf);
    29ca:	4628      	mov	r0, r5
    29cc:	f7ff fd06 	bl	23dc <usage_fault>
    29d0:	e791      	b.n	28f6 <hard_fault+0x46>
    29d2:	bf00      	nop
    29d4:	000083d4 	.word	0x000083d4
    29d8:	0000839c 	.word	0x0000839c
    29dc:	000089dc 	.word	0x000089dc
    29e0:	e000ed00 	.word	0xe000ed00
    29e4:	000089f4 	.word	0x000089f4
    29e8:	00008a18 	.word	0x00008a18
    29ec:	00008a28 	.word	0x00008a28
    29f0:	e000ed29 	.word	0xe000ed29
    29f4:	e000ed2a 	.word	0xe000ed2a
    29f8:	00008a48 	.word	0x00008a48

000029fc <reserved_exception>:
 * See z_arm_fault_dump() for example.
 *
 * @return N/A
 */
static void reserved_exception(const z_arch_esf_t *esf, int fault)
{
    29fc:	b508      	push	{r3, lr}
    29fe:	460a      	mov	r2, r1
    2a00:	480b      	ldr	r0, [pc, #44]	; (2a30 <reserved_exception+0x34>)
    2a02:	4b0c      	ldr	r3, [pc, #48]	; (2a34 <reserved_exception+0x38>)
    2a04:	1ac0      	subs	r0, r0, r3
    2a06:	08c0      	lsrs	r0, r0, #3
	ARG_UNUSED(esf);

	PR_FAULT_INFO("***** %s %d) *****",
    2a08:	f04f 0300 	mov.w	r3, #0
    2a0c:	2101      	movs	r1, #1
    2a0e:	f361 0302 	bfi	r3, r1, #0, #3
    2a12:	f36f 03c5 	bfc	r3, #3, #3
    2a16:	f360 138f 	bfi	r3, r0, #6, #10
    2a1a:	2a0f      	cmp	r2, #15
    2a1c:	dc05      	bgt.n	2a2a <reserved_exception+0x2e>
    2a1e:	4906      	ldr	r1, [pc, #24]	; (2a38 <reserved_exception+0x3c>)
    2a20:	3a10      	subs	r2, #16
    2a22:	4806      	ldr	r0, [pc, #24]	; (2a3c <reserved_exception+0x40>)
    2a24:	f7fe fe98 	bl	1758 <log_2>
	       fault < 16 ? "Reserved Exception (" : "Spurious interrupt (IRQ ",
	       fault - 16);
}
    2a28:	bd08      	pop	{r3, pc}
	PR_FAULT_INFO("***** %s %d) *****",
    2a2a:	4905      	ldr	r1, [pc, #20]	; (2a40 <reserved_exception+0x44>)
    2a2c:	e7f8      	b.n	2a20 <reserved_exception+0x24>
    2a2e:	bf00      	nop
    2a30:	000083d4 	.word	0x000083d4
    2a34:	0000839c 	.word	0x0000839c
    2a38:	00008a64 	.word	0x00008a64
    2a3c:	00008a98 	.word	0x00008a98
    2a40:	00008a7c 	.word	0x00008a7c

00002a44 <z_arm_fault>:
 * @param callee_regs Callee-saved registers (R4-R11, PSP)
 *
 */
void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return,
	_callee_saved_t *callee_regs)
{
    2a44:	b5f0      	push	{r4, r5, r6, r7, lr}
    2a46:	b08b      	sub	sp, #44	; 0x2c
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    2a48:	4b2e      	ldr	r3, [pc, #184]	; (2b04 <z_arm_fault+0xc0>)
    2a4a:	685d      	ldr	r5, [r3, #4]
    2a4c:	f3c5 0508 	ubfx	r5, r5, #0, #9
    2a50:	2300      	movs	r3, #0
    2a52:	f383 8811 	msr	BASEPRI, r3
    2a56:	f3bf 8f6f 	isb	sy
	if ((exc_return & EXC_RETURN_INDICATOR_PREFIX) !=
    2a5a:	f002 437f 	and.w	r3, r2, #4278190080	; 0xff000000
    2a5e:	f1b3 4f7f 	cmp.w	r3, #4278190080	; 0xff000000
    2a62:	d12a      	bne.n	2aba <z_arm_fault+0x76>
	if ((exc_return & EXC_RETURN_MODE_THREAD) &&
    2a64:	f002 030c 	and.w	r3, r2, #12
    2a68:	2b08      	cmp	r3, #8
    2a6a:	d010      	beq.n	2a8e <z_arm_fault+0x4a>
		if (exc_return & EXC_RETURN_MODE_THREAD) {
    2a6c:	f012 0f08 	tst.w	r2, #8
    2a70:	d020      	beq.n	2ab4 <z_arm_fault+0x70>
			ptr_esf =  (z_arch_esf_t *)psp;
    2a72:	460c      	mov	r4, r1
	*nested_exc = false;
    2a74:	2700      	movs	r7, #0

#ifdef CONFIG_DEBUG_COREDUMP
	z_arm_coredump_fault_sp = POINTER_TO_UINT(esf);
#endif

	reason = fault_handle(esf, fault, &recoverable);
    2a76:	f10d 0227 	add.w	r2, sp, #39	; 0x27
    2a7a:	4629      	mov	r1, r5
    2a7c:	4620      	mov	r0, r4
    2a7e:	f004 fc21 	bl	72c4 <fault_handle>
    2a82:	4606      	mov	r6, r0
	if (recoverable) {
    2a84:	f89d 3027 	ldrb.w	r3, [sp, #39]	; 0x27
    2a88:	b1d3      	cbz	r3, 2ac0 <z_arm_fault+0x7c>
	} else {
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
	}

	z_arm_fatal_error(reason, &esf_copy);
}
    2a8a:	b00b      	add	sp, #44	; 0x2c
    2a8c:	bdf0      	pop	{r4, r5, r6, r7, pc}
    2a8e:	4b1e      	ldr	r3, [pc, #120]	; (2b08 <z_arm_fault+0xc4>)
    2a90:	4a1e      	ldr	r2, [pc, #120]	; (2b0c <z_arm_fault+0xc8>)
    2a92:	1a9b      	subs	r3, r3, r2
    2a94:	08db      	lsrs	r3, r3, #3
		PR_EXC("SPSEL in thread mode does not indicate PSP");
    2a96:	f04f 0100 	mov.w	r1, #0
    2a9a:	2201      	movs	r2, #1
    2a9c:	f362 0102 	bfi	r1, r2, #0, #3
    2aa0:	f36f 01c5 	bfc	r1, #3, #3
    2aa4:	f363 118f 	bfi	r1, r3, #6, #10
    2aa8:	4819      	ldr	r0, [pc, #100]	; (2b10 <z_arm_fault+0xcc>)
    2aaa:	f7fe fe91 	bl	17d0 <log_0>
	*nested_exc = false;
    2aae:	2700      	movs	r7, #0
		return NULL;
    2ab0:	463c      	mov	r4, r7
    2ab2:	e7e0      	b.n	2a76 <z_arm_fault+0x32>
			ptr_esf = (z_arch_esf_t *)msp;
    2ab4:	4604      	mov	r4, r0
			*nested_exc = true;
    2ab6:	2701      	movs	r7, #1
    2ab8:	e7dd      	b.n	2a76 <z_arm_fault+0x32>
	*nested_exc = false;
    2aba:	2700      	movs	r7, #0
		return NULL;
    2abc:	463c      	mov	r4, r7
    2abe:	e7da      	b.n	2a76 <z_arm_fault+0x32>
	memcpy(&esf_copy, esf, sizeof(z_arch_esf_t));
    2ac0:	ad01      	add	r5, sp, #4
    2ac2:	6820      	ldr	r0, [r4, #0]
    2ac4:	6861      	ldr	r1, [r4, #4]
    2ac6:	68a2      	ldr	r2, [r4, #8]
    2ac8:	68e3      	ldr	r3, [r4, #12]
    2aca:	c50f      	stmia	r5!, {r0, r1, r2, r3}
    2acc:	6920      	ldr	r0, [r4, #16]
    2ace:	6961      	ldr	r1, [r4, #20]
    2ad0:	69a2      	ldr	r2, [r4, #24]
    2ad2:	69e3      	ldr	r3, [r4, #28]
    2ad4:	c50f      	stmia	r5!, {r0, r1, r2, r3}
	if (nested_exc) {
    2ad6:	b14f      	cbz	r7, 2aec <z_arm_fault+0xa8>
		if ((esf_copy.basic.xpsr & IPSR_ISR_Msk) == 0) {
    2ad8:	9b08      	ldr	r3, [sp, #32]
    2ada:	f3c3 0208 	ubfx	r2, r3, #0, #9
    2ade:	b95a      	cbnz	r2, 2af8 <z_arm_fault+0xb4>
			esf_copy.basic.xpsr |= IPSR_ISR_Msk;
    2ae0:	ea6f 2353 	mvn.w	r3, r3, lsr #9
    2ae4:	ea6f 2343 	mvn.w	r3, r3, lsl #9
    2ae8:	9308      	str	r3, [sp, #32]
    2aea:	e005      	b.n	2af8 <z_arm_fault+0xb4>
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    2aec:	9b08      	ldr	r3, [sp, #32]
    2aee:	f423 73ff 	bic.w	r3, r3, #510	; 0x1fe
    2af2:	f023 0301 	bic.w	r3, r3, #1
    2af6:	9308      	str	r3, [sp, #32]
	z_arm_fatal_error(reason, &esf_copy);
    2af8:	a901      	add	r1, sp, #4
    2afa:	4630      	mov	r0, r6
    2afc:	f004 fbc2 	bl	7284 <z_arm_fatal_error>
    2b00:	e7c3      	b.n	2a8a <z_arm_fault+0x46>
    2b02:	bf00      	nop
    2b04:	e000ed00 	.word	0xe000ed00
    2b08:	000083d4 	.word	0x000083d4
    2b0c:	0000839c 	.word	0x0000839c
    2b10:	00008aac 	.word	0x00008aac

00002b14 <z_arm_fault_init>:
 */
void z_arm_fault_init(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
    2b14:	4a02      	ldr	r2, [pc, #8]	; (2b20 <z_arm_fault_init+0xc>)
    2b16:	6953      	ldr	r3, [r2, #20]
    2b18:	f043 0310 	orr.w	r3, r3, #16
    2b1c:	6153      	str	r3, [r2, #20]
	 * Stack to attempt to descend into secure region, in which case a
	 * Secure Hard Fault will occur and we can track the fault from there.
	 */
	SCB->CCR |= SCB_CCR_STKOFHFNMIGN_Msk;
#endif /* CONFIG_BUILTIN_STACK_GUARD */
}
    2b1e:	4770      	bx	lr
    2b20:	e000ed00 	.word	0xe000ed00

00002b24 <z_arm_bus_fault>:
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_exc_spurious)

	mrs r0, MSP
    2b24:	f3ef 8008 	mrs	r0, MSP
	mrs r1, PSP
    2b28:	f3ef 8109 	mrs	r1, PSP
	push {r0, lr}
    2b2c:	b501      	push	{r0, lr}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	push {r4-r11}
#endif
	mov  r3, sp /* pointer to _callee_saved_t */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
	mov r2, lr /* EXC_RETURN */
    2b2e:	4672      	mov	r2, lr
	bl z_arm_fault
    2b30:	f7ff ff88 	bl	2a44 <z_arm_fault>
	 * in this routine. Therefore, we can just reset
	 * the MSP to its value prior to entering the function
	 */
	add sp, #40
#endif
	pop {r0, pc}
    2b34:	bd01      	pop	{r0, pc}
    2b36:	bf00      	nop

00002b38 <z_arm_interrupt_init>:
 * @return N/A
 */

void z_arm_interrupt_init(void)
{
	int irq = 0;
    2b38:	2200      	movs	r2, #0

	for (; irq < CONFIG_NUM_IRQS; irq++) {
    2b3a:	e006      	b.n	2b4a <z_arm_interrupt_init+0x12>
    2b3c:	f002 010f 	and.w	r1, r2, #15
    2b40:	4b09      	ldr	r3, [pc, #36]	; (2b68 <z_arm_interrupt_init+0x30>)
    2b42:	440b      	add	r3, r1
    2b44:	2120      	movs	r1, #32
    2b46:	7619      	strb	r1, [r3, #24]
    2b48:	3201      	adds	r2, #1
    2b4a:	2a2f      	cmp	r2, #47	; 0x2f
    2b4c:	dc0a      	bgt.n	2b64 <z_arm_interrupt_init+0x2c>
		NVIC_SetPriority((IRQn_Type)irq, _IRQ_PRIO_OFFSET);
    2b4e:	b253      	sxtb	r3, r2
  if ((int32_t)(IRQn) >= 0)
    2b50:	2b00      	cmp	r3, #0
    2b52:	dbf3      	blt.n	2b3c <z_arm_interrupt_init+0x4>
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    2b54:	f103 4360 	add.w	r3, r3, #3758096384	; 0xe0000000
    2b58:	f503 4361 	add.w	r3, r3, #57600	; 0xe100
    2b5c:	2120      	movs	r1, #32
    2b5e:	f883 1300 	strb.w	r1, [r3, #768]	; 0x300
    2b62:	e7f1      	b.n	2b48 <z_arm_interrupt_init+0x10>
	}
}
    2b64:	4770      	bx	lr
    2b66:	bf00      	nop
    2b68:	e000ecfc 	.word	0xe000ecfc

00002b6c <__start>:
 */
SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
    /* Reset CONTROL register */
    movs.n r0, #0
    2b6c:	2000      	movs	r0, #0
    msr CONTROL, r0
    2b6e:	f380 8814 	msr	CONTROL, r0
    isb
    2b72:	f3bf 8f6f 	isb	sy
#endif /* CONFIG_CPU_CORTEX_M_HAS_SPLIM */

#endif /* CONFIG_INIT_ARCH_HW_AT_BOOT */

#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
    bl z_arm_platform_init
    2b76:	f005 fab7 	bl	80e8 <z_arm_platform_init>
#endif

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
#if defined(CONFIG_CPU_HAS_ARM_MPU)
    /* Disable MPU */
    movs.n r0, #0
    2b7a:	2000      	movs	r0, #0
    ldr r1, =_SCS_MPU_CTRL
    2b7c:	490d      	ldr	r1, [pc, #52]	; (2bb4 <__start+0x48>)
    str r0, [r1]
    2b7e:	6008      	str	r0, [r1, #0]
    dsb
    2b80:	f3bf 8f4f 	dsb	sy
#endif /* CONFIG_CPU_HAS_ARM_MPU */
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    2b84:	480c      	ldr	r0, [pc, #48]	; (2bb8 <__start+0x4c>)
    msr msp, r0
    2b86:	f380 8808 	msr	MSP, r0

    /* Initialize core architecture registers and system blocks */
    bl z_arm_init_arch_hw_at_boot
    2b8a:	f000 f829 	bl	2be0 <z_arm_init_arch_hw_at_boot>

    /* lock interrupts: will get unlocked when switch to main task */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    2b8e:	2020      	movs	r0, #32
    msr BASEPRI, r0
    2b90:	f380 8811 	msr	BASEPRI, r0

    /*
     * Set PSP and use it to boot without using MSP, so that it
     * gets set to z_interrupt_stacks during initialization.
     */
    ldr r0, =z_interrupt_stacks
    2b94:	4809      	ldr	r0, [pc, #36]	; (2bbc <__start+0x50>)
    ldr r1, =CONFIG_ISR_STACK_SIZE + MPU_GUARD_ALIGN_AND_SIZE
    2b96:	f44f 6100 	mov.w	r1, #2048	; 0x800
    adds r0, r0, r1
    2b9a:	1840      	adds	r0, r0, r1
    msr PSP, r0
    2b9c:	f380 8809 	msr	PSP, r0
    mrs r0, CONTROL
    2ba0:	f3ef 8014 	mrs	r0, CONTROL
    movs r1, #2
    2ba4:	2102      	movs	r1, #2
    orrs r0, r1 /* CONTROL_SPSEL_Msk */
    2ba6:	4308      	orrs	r0, r1
    msr CONTROL, r0
    2ba8:	f380 8814 	msr	CONTROL, r0
    /*
     * When changing the stack pointer, software must use an ISB instruction
     * immediately after the MSR instruction. This ensures that instructions
     * after the ISB instruction execute using the new stack pointer.
     */
    isb
    2bac:	f3bf 8f6f 	isb	sy
    /*
     * 'bl' jumps the furthest of the branch instructions that are
     * supported on all platforms. So it is used when jumping to z_arm_prep_c
     * (even though we do not intend to return).
     */
    bl z_arm_prep_c
    2bb0:	f7ff fb46 	bl	2240 <z_arm_prep_c>
    ldr r1, =_SCS_MPU_CTRL
    2bb4:	e000ed94 	.word	0xe000ed94
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    2bb8:	20001290 	.word	0x20001290
    ldr r0, =z_interrupt_stacks
    2bbc:	200013d0 	.word	0x200013d0

00002bc0 <z_arm_clear_arm_mpu_config>:
void z_arm_clear_arm_mpu_config(void)
{
	int i;

	int num_regions =
		((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos);
    2bc0:	4b06      	ldr	r3, [pc, #24]	; (2bdc <z_arm_clear_arm_mpu_config+0x1c>)
    2bc2:	6818      	ldr	r0, [r3, #0]
	int num_regions =
    2bc4:	f3c0 2007 	ubfx	r0, r0, #8, #8

	for (i = 0; i < num_regions; i++) {
    2bc8:	2300      	movs	r3, #0
    2bca:	4283      	cmp	r3, r0
    2bcc:	da05      	bge.n	2bda <z_arm_clear_arm_mpu_config+0x1a>
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
  MPU->RNR = rnr;
    2bce:	4a03      	ldr	r2, [pc, #12]	; (2bdc <z_arm_clear_arm_mpu_config+0x1c>)
    2bd0:	6093      	str	r3, [r2, #8]
  MPU->RASR = 0U;
    2bd2:	2100      	movs	r1, #0
    2bd4:	6111      	str	r1, [r2, #16]
    2bd6:	3301      	adds	r3, #1
    2bd8:	e7f7      	b.n	2bca <z_arm_clear_arm_mpu_config+0xa>
		ARM_MPU_ClrRegion(i);
	}
}
    2bda:	4770      	bx	lr
    2bdc:	e000ed90 	.word	0xe000ed90

00002be0 <z_arm_init_arch_hw_at_boot>:
 * components and core registers.
 *
 * @return N/A
 */
void z_arm_init_arch_hw_at_boot(void)
{
    2be0:	b510      	push	{r4, lr}
  \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
           Can only be executed in Privileged modes.
 */
__STATIC_FORCEINLINE void __disable_irq(void)
{
  __ASM volatile ("cpsid i" : : : "memory");
    2be2:	b672      	cpsid	i
  \details Assigns the given value to the Fault Mask register.
  \param [in]    faultMask  Fault Mask value to set
 */
__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
{
  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
    2be4:	2400      	movs	r4, #0
    2be6:	f384 8813 	msr	FAULTMASK, r4

	/* Initialize System Control Block components */

#if defined(CONFIG_CPU_HAS_ARM_MPU) || defined(CONFIG_CPU_HAS_NXP_MPU)
	/* Clear MPU region configuration */
	z_arm_clear_arm_mpu_config();
    2bea:	f7ff ffe9 	bl	2bc0 <z_arm_clear_arm_mpu_config>
#endif /* CONFIG_CPU_HAS_ARM_MPU */

	/* Disable NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
    2bee:	4623      	mov	r3, r4
    2bf0:	e008      	b.n	2c04 <z_arm_init_arch_hw_at_boot+0x24>
		NVIC->ICER[i] = 0xFFFFFFFF;
    2bf2:	f103 0120 	add.w	r1, r3, #32
    2bf6:	4a0e      	ldr	r2, [pc, #56]	; (2c30 <z_arm_init_arch_hw_at_boot+0x50>)
    2bf8:	f04f 30ff 	mov.w	r0, #4294967295
    2bfc:	f842 0021 	str.w	r0, [r2, r1, lsl #2]
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
    2c00:	3301      	adds	r3, #1
    2c02:	b2db      	uxtb	r3, r3
    2c04:	2b07      	cmp	r3, #7
    2c06:	d9f4      	bls.n	2bf2 <z_arm_init_arch_hw_at_boot+0x12>
	}
	/* Clear pending NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) {
    2c08:	2300      	movs	r3, #0
    2c0a:	e008      	b.n	2c1e <z_arm_init_arch_hw_at_boot+0x3e>
		NVIC->ICPR[i] = 0xFFFFFFFF;
    2c0c:	f103 0160 	add.w	r1, r3, #96	; 0x60
    2c10:	4a07      	ldr	r2, [pc, #28]	; (2c30 <z_arm_init_arch_hw_at_boot+0x50>)
    2c12:	f04f 30ff 	mov.w	r0, #4294967295
    2c16:	f842 0021 	str.w	r0, [r2, r1, lsl #2]
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) {
    2c1a:	3301      	adds	r3, #1
    2c1c:	b2db      	uxtb	r3, r3
    2c1e:	2b07      	cmp	r3, #7
    2c20:	d9f4      	bls.n	2c0c <z_arm_init_arch_hw_at_boot+0x2c>
  __ASM volatile ("cpsie i" : : : "memory");
    2c22:	b662      	cpsie	i
  __ASM volatile ("dsb 0xF":::"memory");
    2c24:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    2c28:	f3bf 8f6f 	isb	sy
	/* Restore Interrupts */
	__enable_irq();

	__DSB();
	__ISB();
}
    2c2c:	bd10      	pop	{r4, pc}
    2c2e:	bf00      	nop
    2c30:	e000e100 	.word	0xe000e100

00002c34 <z_impl_k_thread_abort>:
#include <kswap.h>
#include <wait_q.h>
#include <sys/__assert.h>

void z_impl_k_thread_abort(k_tid_t thread)
{
    2c34:	b508      	push	{r3, lr}
	if (_current == thread) {
    2c36:	4b08      	ldr	r3, [pc, #32]	; (2c58 <z_impl_k_thread_abort+0x24>)
    2c38:	689b      	ldr	r3, [r3, #8]
    2c3a:	4283      	cmp	r3, r0
    2c3c:	d002      	beq.n	2c44 <z_impl_k_thread_abort+0x10>
			 */
			SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
		}
	}

	z_thread_abort(thread);
    2c3e:	f003 fba3 	bl	6388 <z_thread_abort>
}
    2c42:	bd08      	pop	{r3, pc}
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    2c44:	f3ef 8305 	mrs	r3, IPSR
		if (arch_is_in_isr()) {
    2c48:	2b00      	cmp	r3, #0
    2c4a:	d0f8      	beq.n	2c3e <z_impl_k_thread_abort+0xa>
			SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    2c4c:	4a03      	ldr	r2, [pc, #12]	; (2c5c <z_impl_k_thread_abort+0x28>)
    2c4e:	6853      	ldr	r3, [r2, #4]
    2c50:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
    2c54:	6053      	str	r3, [r2, #4]
    2c56:	e7f2      	b.n	2c3e <z_impl_k_thread_abort+0xa>
    2c58:	20000b2c 	.word	0x20000b2c
    2c5c:	e000ed00 	.word	0xe000ed00

00002c60 <z_arm_configure_static_mpu_regions>:
 *
 * For some MPU architectures, such as the unmodified ARMv8-M MPU,
 * the function must execute with MPU enabled.
 */
void z_arm_configure_static_mpu_regions(void)
{
    2c60:	b508      	push	{r3, lr}
	/* Configure the static MPU regions within firmware SRAM boundaries.
	 * Start address of the image is given by _image_ram_start. The end
	 * of the firmware SRAM area is marked by __kernel_ram_end, taking
	 * into account the unused SRAM area, as well.
	 */
	arm_core_mpu_configure_static_mpu_regions(static_regions,
    2c62:	4b03      	ldr	r3, [pc, #12]	; (2c70 <z_arm_configure_static_mpu_regions+0x10>)
    2c64:	4a03      	ldr	r2, [pc, #12]	; (2c74 <z_arm_configure_static_mpu_regions+0x14>)
    2c66:	2101      	movs	r1, #1
    2c68:	4803      	ldr	r0, [pc, #12]	; (2c78 <z_arm_configure_static_mpu_regions+0x18>)
    2c6a:	f004 fb80 	bl	736e <arm_core_mpu_configure_static_mpu_regions>
	};

	arm_core_mpu_mark_areas_for_dynamic_regions(dyn_region_areas,
		ARRAY_SIZE(dyn_region_areas));
#endif /* CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS */
}
    2c6e:	bd08      	pop	{r3, pc}
    2c70:	20020000 	.word	0x20020000
    2c74:	20000000 	.word	0x20000000
    2c78:	00008adc 	.word	0x00008adc

00002c7c <region_init>:
#endif /* CPU_CORTEX_M0PLUS | CPU_CORTEX_M3 | CPU_CORTEX_M4 */
}

static inline void set_region_number(uint32_t index)
{
	MPU->RNR = index;
    2c7c:	4a06      	ldr	r2, [pc, #24]	; (2c98 <region_init+0x1c>)
    2c7e:	6090      	str	r0, [r2, #8]

	set_region_base_address(region_conf->base & MPU_RBAR_ADDR_Msk);
	set_region_attributes(region_conf->attr.rasr);
	set_region_size(region_conf->size | MPU_RASR_ENABLE_Msk);
#else
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    2c80:	680b      	ldr	r3, [r1, #0]
    2c82:	f023 031f 	bic.w	r3, r3, #31
				| MPU_RBAR_VALID_Msk | index;
    2c86:	4303      	orrs	r3, r0
    2c88:	f043 0310 	orr.w	r3, r3, #16
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    2c8c:	60d3      	str	r3, [r2, #12]
	MPU->RASR = region_conf->attr.rasr | MPU_RASR_ENABLE_Msk;
    2c8e:	688b      	ldr	r3, [r1, #8]
    2c90:	f043 0301 	orr.w	r3, r3, #1
    2c94:	6113      	str	r3, [r2, #16]
	LOG_DBG("[%d] 0x%08x 0x%08x",
		index, region_conf->base, region_conf->attr.rasr);
#endif
}
    2c96:	4770      	bx	lr
    2c98:	e000ed90 	.word	0xe000ed90

00002c9c <region_allocate_and_init>:
#error "Unsupported ARM CPU"
#endif

static int region_allocate_and_init(const uint8_t index,
	const struct arm_mpu_region *region_conf)
{
    2c9c:	b510      	push	{r4, lr}
    2c9e:	4604      	mov	r4, r0
	/* Attempt to allocate new region index. */
	if (index > (get_num_regions() - 1U)) {
    2ca0:	2807      	cmp	r0, #7
    2ca2:	d803      	bhi.n	2cac <region_allocate_and_init+0x10>
	}

	LOG_DBG("Program MPU region at index 0x%x", index);

	/* Program region */
	region_init(index, region_conf);
    2ca4:	f7ff ffea 	bl	2c7c <region_init>

	return index;
    2ca8:	4620      	mov	r0, r4
}
    2caa:	bd10      	pop	{r4, pc}
    2cac:	4b09      	ldr	r3, [pc, #36]	; (2cd4 <region_allocate_and_init+0x38>)
    2cae:	4a0a      	ldr	r2, [pc, #40]	; (2cd8 <region_allocate_and_init+0x3c>)
    2cb0:	1a9b      	subs	r3, r3, r2
    2cb2:	08db      	lsrs	r3, r3, #3
		LOG_ERR("Failed to allocate new MPU region %u\n", index);
    2cb4:	f04f 0200 	mov.w	r2, #0
    2cb8:	2101      	movs	r1, #1
    2cba:	f361 0202 	bfi	r2, r1, #0, #3
    2cbe:	f36f 02c5 	bfc	r2, #3, #3
    2cc2:	f363 128f 	bfi	r2, r3, #6, #10
    2cc6:	4601      	mov	r1, r0
    2cc8:	4804      	ldr	r0, [pc, #16]	; (2cdc <region_allocate_and_init+0x40>)
    2cca:	f7fe fd0f 	bl	16ec <log_1>
		return -EINVAL;
    2cce:	f06f 0015 	mvn.w	r0, #21
    2cd2:	e7ea      	b.n	2caa <region_allocate_and_init+0xe>
    2cd4:	000083cc 	.word	0x000083cc
    2cd8:	0000839c 	.word	0x0000839c
    2cdc:	00008ae8 	.word	0x00008ae8

00002ce0 <mpu_configure_regions>:
 * sanity check of the memory regions to be programmed.
 */
static int mpu_configure_regions(const struct z_arm_mpu_partition
	regions[], uint8_t regions_num, uint8_t start_reg_index,
	bool do_sanity_check)
{
    2ce0:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
    2ce4:	4680      	mov	r8, r0
    2ce6:	460f      	mov	r7, r1
    2ce8:	469a      	mov	sl, r3
	int i;
	int reg_index = start_reg_index;
    2cea:	4616      	mov	r6, r2

	for (i = 0; i < regions_num; i++) {
    2cec:	2400      	movs	r4, #0
    2cee:	e009      	b.n	2d04 <mpu_configure_regions+0x24>
				(!mpu_partition_is_valid(&regions[i]))) {
			LOG_ERR("Partition %u: sanity check failed.", i);
			return -EINVAL;
		}

		reg_index = mpu_configure_region(reg_index, &regions[i]);
    2cf0:	4629      	mov	r1, r5
    2cf2:	b2f0      	uxtb	r0, r6
    2cf4:	f004 fb1c 	bl	7330 <mpu_configure_region>
    2cf8:	4606      	mov	r6, r0

		if (reg_index == -EINVAL) {
    2cfa:	f110 0f16 	cmn.w	r0, #22
    2cfe:	d025      	beq.n	2d4c <mpu_configure_regions+0x6c>
			return reg_index;
		}

		/* Increment number of programmed MPU indices. */
		reg_index++;
    2d00:	3601      	adds	r6, #1
	for (i = 0; i < regions_num; i++) {
    2d02:	3401      	adds	r4, #1
    2d04:	42bc      	cmp	r4, r7
    2d06:	da21      	bge.n	2d4c <mpu_configure_regions+0x6c>
		if (regions[i].size == 0U) {
    2d08:	eb04 0544 	add.w	r5, r4, r4, lsl #1
    2d0c:	eb08 0585 	add.w	r5, r8, r5, lsl #2
    2d10:	686a      	ldr	r2, [r5, #4]
    2d12:	2a00      	cmp	r2, #0
    2d14:	d0f5      	beq.n	2d02 <mpu_configure_regions+0x22>
		if (do_sanity_check &&
    2d16:	f1ba 0f00 	cmp.w	sl, #0
    2d1a:	d0e9      	beq.n	2cf0 <mpu_configure_regions+0x10>
				(!mpu_partition_is_valid(&regions[i]))) {
    2d1c:	4628      	mov	r0, r5
    2d1e:	f004 faf6 	bl	730e <mpu_partition_is_valid>
		if (do_sanity_check &&
    2d22:	2800      	cmp	r0, #0
    2d24:	d1e4      	bne.n	2cf0 <mpu_configure_regions+0x10>
    2d26:	4b0b      	ldr	r3, [pc, #44]	; (2d54 <mpu_configure_regions+0x74>)
    2d28:	4a0b      	ldr	r2, [pc, #44]	; (2d58 <mpu_configure_regions+0x78>)
    2d2a:	1a9b      	subs	r3, r3, r2
    2d2c:	08db      	lsrs	r3, r3, #3
			LOG_ERR("Partition %u: sanity check failed.", i);
    2d2e:	f04f 0200 	mov.w	r2, #0
    2d32:	2101      	movs	r1, #1
    2d34:	f361 0202 	bfi	r2, r1, #0, #3
    2d38:	f36f 02c5 	bfc	r2, #3, #3
    2d3c:	f363 128f 	bfi	r2, r3, #6, #10
    2d40:	4621      	mov	r1, r4
    2d42:	4806      	ldr	r0, [pc, #24]	; (2d5c <mpu_configure_regions+0x7c>)
    2d44:	f7fe fcd2 	bl	16ec <log_1>
			return -EINVAL;
    2d48:	f06f 0615 	mvn.w	r6, #21
	}

	return reg_index;
}
    2d4c:	4630      	mov	r0, r6
    2d4e:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
    2d52:	bf00      	nop
    2d54:	000083cc 	.word	0x000083cc
    2d58:	0000839c 	.word	0x0000839c
    2d5c:	00008b10 	.word	0x00008b10

00002d60 <mpu_configure_static_mpu_regions>:
 */
static int mpu_configure_static_mpu_regions(const struct z_arm_mpu_partition
	static_regions[], const uint8_t regions_num,
	const uint32_t background_area_base,
	const uint32_t background_area_end)
{
    2d60:	b510      	push	{r4, lr}
	int mpu_reg_index = static_regions_num;
    2d62:	4c03      	ldr	r4, [pc, #12]	; (2d70 <mpu_configure_static_mpu_regions+0x10>)
	 * programmed on top of SRAM region configuration.
	 */
	ARG_UNUSED(background_area_base);
	ARG_UNUSED(background_area_end);

	mpu_reg_index = mpu_configure_regions(static_regions,
    2d64:	2301      	movs	r3, #1
    2d66:	7822      	ldrb	r2, [r4, #0]
    2d68:	f7ff ffba 	bl	2ce0 <mpu_configure_regions>
		regions_num, mpu_reg_index, true);

	static_regions_num = mpu_reg_index;
    2d6c:	7020      	strb	r0, [r4, #0]

	return mpu_reg_index;
}
    2d6e:	bd10      	pop	{r4, pc}
    2d70:	20000b87 	.word	0x20000b87

00002d74 <arm_core_mpu_enable>:
void arm_core_mpu_enable(void)
{
	/* Enable MPU and use the default memory map as a
	 * background region for privileged software access.
	 */
	MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
    2d74:	4b03      	ldr	r3, [pc, #12]	; (2d84 <arm_core_mpu_enable+0x10>)
    2d76:	2205      	movs	r2, #5
    2d78:	605a      	str	r2, [r3, #4]
  __ASM volatile ("dsb 0xF":::"memory");
    2d7a:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    2d7e:	f3bf 8f6f 	isb	sy

	/* Make sure that all the registers are set before proceeding */
	__DSB();
	__ISB();
}
    2d82:	4770      	bx	lr
    2d84:	e000ed90 	.word	0xe000ed90

00002d88 <arm_core_mpu_disable>:
  __ASM volatile ("dmb 0xF":::"memory");
    2d88:	f3bf 8f5f 	dmb	sy
{
	/* Force any outstanding transfers to complete before disabling MPU */
	__DMB();

	/* Disable MPU */
	MPU->CTRL = 0;
    2d8c:	4b01      	ldr	r3, [pc, #4]	; (2d94 <arm_core_mpu_disable+0xc>)
    2d8e:	2200      	movs	r2, #0
    2d90:	605a      	str	r2, [r3, #4]
}
    2d92:	4770      	bx	lr
    2d94:	e000ed90 	.word	0xe000ed90

00002d98 <z_arm_mpu_init>:
 *
 * This function provides the default configuration mechanism for the Memory
 * Protection Unit (MPU).
 */
int z_arm_mpu_init(void)
{
    2d98:	b538      	push	{r3, r4, r5, lr}
	uint32_t r_index;

	if (mpu_config.num_regions > get_num_regions()) {
    2d9a:	4b0e      	ldr	r3, [pc, #56]	; (2dd4 <z_arm_mpu_init+0x3c>)
    2d9c:	681d      	ldr	r5, [r3, #0]
    2d9e:	2d08      	cmp	r5, #8
    2da0:	d815      	bhi.n	2dce <z_arm_mpu_init+0x36>
		return -1;
	}

	LOG_DBG("total region count: %d", get_num_regions());

	arm_core_mpu_disable();
    2da2:	f7ff fff1 	bl	2d88 <arm_core_mpu_disable>

	/* Architecture-specific configuration */
	mpu_init();

	/* Program fixed regions configured at SOC definition. */
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    2da6:	2400      	movs	r4, #0
    2da8:	42a5      	cmp	r5, r4
    2daa:	d90a      	bls.n	2dc2 <z_arm_mpu_init+0x2a>
		region_init(r_index, &mpu_config.mpu_regions[r_index]);
    2dac:	4b09      	ldr	r3, [pc, #36]	; (2dd4 <z_arm_mpu_init+0x3c>)
    2dae:	6859      	ldr	r1, [r3, #4]
    2db0:	eb04 0244 	add.w	r2, r4, r4, lsl #1
    2db4:	0093      	lsls	r3, r2, #2
    2db6:	4419      	add	r1, r3
    2db8:	4620      	mov	r0, r4
    2dba:	f7ff ff5f 	bl	2c7c <region_init>
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    2dbe:	3401      	adds	r4, #1
    2dc0:	e7f2      	b.n	2da8 <z_arm_mpu_init+0x10>
	}

	/* Update the number of programmed MPU regions. */
	static_regions_num = mpu_config.num_regions;
    2dc2:	4b05      	ldr	r3, [pc, #20]	; (2dd8 <z_arm_mpu_init+0x40>)
    2dc4:	701d      	strb	r5, [r3, #0]


	arm_core_mpu_enable();
    2dc6:	f7ff ffd5 	bl	2d74 <arm_core_mpu_enable>
		(MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos ==
		NUM_MPU_REGIONS,
		"Invalid number of MPU regions\n");
#endif /* CORTEX_M0PLUS || CPU_CORTEX_M3 || CPU_CORTEX_M4 */

	return 0;
    2dca:	2000      	movs	r0, #0
}
    2dcc:	bd38      	pop	{r3, r4, r5, pc}
		return -1;
    2dce:	f04f 30ff 	mov.w	r0, #4294967295
    2dd2:	e7fb      	b.n	2dcc <z_arm_mpu_init+0x34>
    2dd4:	00008b44 	.word	0x00008b44
    2dd8:	20000b87 	.word	0x20000b87

00002ddc <__stdout_hook_install>:

static int (*_stdout_hook)(int) = _stdout_hook_default;

void __stdout_hook_install(int (*hook)(int))
{
	_stdout_hook = hook;
    2ddc:	4b01      	ldr	r3, [pc, #4]	; (2de4 <__stdout_hook_install+0x8>)
    2dde:	6018      	str	r0, [r3, #0]
}
    2de0:	4770      	bx	lr
    2de2:	bf00      	nop
    2de4:	2000000c 	.word	0x2000000c

00002de8 <nordicsemi_nrf52_init>:
	__asm__ volatile(
    2de8:	f04f 0320 	mov.w	r3, #32
    2dec:	f3ef 8211 	mrs	r2, BASEPRI
    2df0:	f383 8812 	msr	BASEPRI_MAX, r3
    2df4:	f3bf 8f6f 	isb	sy

	key = irq_lock();

#ifdef CONFIG_NRF_ENABLE_ICACHE
	/* Enable the instruction cache */
	NRF_NVMC->ICACHECNF = NVMC_ICACHECNF_CACHEEN_Msk;
    2df8:	2301      	movs	r3, #1
    2dfa:	4906      	ldr	r1, [pc, #24]	; (2e14 <nordicsemi_nrf52_init+0x2c>)
    2dfc:	f8c1 3540 	str.w	r3, [r1, #1344]	; 0x540
#endif

#if NRF_POWER_HAS_DCDCEN
NRF_STATIC_INLINE void nrf_power_dcdcen_set(NRF_POWER_Type * p_reg, bool enable)
{
    p_reg->DCDCEN = (enable ? POWER_DCDCEN_DCDCEN_Enabled : POWER_DCDCEN_DCDCEN_Disabled) <<
    2e00:	f04f 4180 	mov.w	r1, #1073741824	; 0x40000000
    2e04:	f8c1 3578 	str.w	r3, [r1, #1400]	; 0x578
	__asm__ volatile(
    2e08:	f382 8811 	msr	BASEPRI, r2
    2e0c:	f3bf 8f6f 	isb	sy
	NMI_INIT();

	irq_unlock(key);

	return 0;
}
    2e10:	2000      	movs	r0, #0
    2e12:	4770      	bx	lr
    2e14:	4001e000 	.word	0x4001e000

00002e18 <sys_arch_reboot>:
    *p_gpregret = val;
    2e18:	b2c0      	uxtb	r0, r0
    2e1a:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2e1e:	f8c3 051c 	str.w	r0, [r3, #1308]	; 0x51c
  __ASM volatile ("dsb 0xF":::"memory");
    2e22:	f3bf 8f4f 	dsb	sy
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
  __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                       buffered write are completed before reset */
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    2e26:	4905      	ldr	r1, [pc, #20]	; (2e3c <sys_arch_reboot+0x24>)
    2e28:	68ca      	ldr	r2, [r1, #12]
    2e2a:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    2e2e:	4b04      	ldr	r3, [pc, #16]	; (2e40 <sys_arch_reboot+0x28>)
    2e30:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    2e32:	60cb      	str	r3, [r1, #12]
    2e34:	f3bf 8f4f 	dsb	sy
                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
  __DSB();                                                          /* Ensure completion of memory access */

  for(;;)                                                           /* wait until reset */
  {
    __NOP();
    2e38:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    2e3a:	e7fd      	b.n	2e38 <sys_arch_reboot+0x20>
    2e3c:	e000ed00 	.word	0xe000ed00
    2e40:	05fa0004 	.word	0x05fa0004

00002e44 <arch_busy_wait>:

#else // NRFX_CHECK(NRFX_DELAY_DWT_BASED)

NRF_STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us)
{
    if (time_us == 0)
    2e44:	b130      	cbz	r0, 2e54 <arch_busy_wait+0x10>

void arch_busy_wait(uint32_t time_us)
{
    2e46:	b508      	push	{r3, lr}
    typedef void (* delay_func_t)(uint32_t);
    const delay_func_t delay_cycles =
        // Set LSB to 1 to execute the code in the Thumb mode.
        (delay_func_t)((((uint32_t)delay_machine_code) | 1));
    uint32_t cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ;
    delay_cycles(cycles);
    2e48:	0180      	lsls	r0, r0, #6
    2e4a:	4b03      	ldr	r3, [pc, #12]	; (2e58 <arch_busy_wait+0x14>)
    2e4c:	f043 0301 	orr.w	r3, r3, #1
    2e50:	4798      	blx	r3
	nrfx_coredep_delay_us(time_us);
}
    2e52:	bd08      	pop	{r3, pc}
    2e54:	4770      	bx	lr
    2e56:	bf00      	nop
    2e58:	00008480 	.word	0x00008480

00002e5c <get_hf_flags>:
static uint32_t *get_hf_flags(void)
{
	struct nrf_clock_control_data *data = CLOCK_DEVICE->data;

	return &data->subsys[CLOCK_CONTROL_NRF_TYPE_HFCLK].flags;
}
    2e5c:	4800      	ldr	r0, [pc, #0]	; (2e60 <get_hf_flags+0x4>)
    2e5e:	4770      	bx	lr
    2e60:	20000520 	.word	0x20000520

00002e64 <get_subsys>:
}

static clock_control_subsys_t get_subsys(struct onoff_manager *mgr)
{
	struct nrf_clock_control_data *data = CLOCK_DEVICE->data;
	size_t offset = (size_t)(mgr - data->mgr);
    2e64:	4b01      	ldr	r3, [pc, #4]	; (2e6c <get_subsys+0x8>)
    2e66:	1ac0      	subs	r0, r0, r3

	return (clock_control_subsys_t)offset;
}
    2e68:	1140      	asrs	r0, r0, #5
    2e6a:	4770      	bx	lr
    2e6c:	200004d8 	.word	0x200004d8

00002e70 <onoff_stop>:

static void onoff_stop(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    2e70:	b538      	push	{r3, r4, r5, lr}
    2e72:	4605      	mov	r5, r0
    2e74:	460c      	mov	r4, r1
	int res;

	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
    2e76:	f7ff fff5 	bl	2e64 <get_subsys>
    2e7a:	4601      	mov	r1, r0
    2e7c:	2240      	movs	r2, #64	; 0x40
    2e7e:	4803      	ldr	r0, [pc, #12]	; (2e8c <onoff_stop+0x1c>)
    2e80:	f004 fb13 	bl	74aa <stop>
    2e84:	4601      	mov	r1, r0
	notify(mgr, res);
    2e86:	4628      	mov	r0, r5
    2e88:	47a0      	blx	r4
}
    2e8a:	bd38      	pop	{r3, r4, r5, pc}
    2e8c:	0000816c 	.word	0x0000816c

00002e90 <onoff_start>:
	notify(mgr, 0);
}

static void onoff_start(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    2e90:	b530      	push	{r4, r5, lr}
    2e92:	b083      	sub	sp, #12
    2e94:	4605      	mov	r5, r0
    2e96:	460c      	mov	r4, r1
	int err;

	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    2e98:	f7ff ffe4 	bl	2e64 <get_subsys>
    2e9c:	4601      	mov	r1, r0
    2e9e:	2340      	movs	r3, #64	; 0x40
    2ea0:	9300      	str	r3, [sp, #0]
    2ea2:	4623      	mov	r3, r4
    2ea4:	4a05      	ldr	r2, [pc, #20]	; (2ebc <onoff_start+0x2c>)
    2ea6:	4806      	ldr	r0, [pc, #24]	; (2ec0 <onoff_start+0x30>)
    2ea8:	f004 fb19 	bl	74de <async_start>
			  onoff_started_callback, notify, CTX_ONOFF);
	if (err < 0) {
    2eac:	1e01      	subs	r1, r0, #0
    2eae:	db01      	blt.n	2eb4 <onoff_start+0x24>
		notify(mgr, err);
	}
}
    2eb0:	b003      	add	sp, #12
    2eb2:	bd30      	pop	{r4, r5, pc}
		notify(mgr, err);
    2eb4:	4628      	mov	r0, r5
    2eb6:	47a0      	blx	r4
}
    2eb8:	e7fa      	b.n	2eb0 <onoff_start+0x20>
    2eba:	bf00      	nop
    2ebc:	00007527 	.word	0x00007527
    2ec0:	0000816c 	.word	0x0000816c

00002ec4 <generic_hfclk_start>:
{
    2ec4:	b510      	push	{r4, lr}
	__asm__ volatile(
    2ec6:	f04f 0320 	mov.w	r3, #32
    2eca:	f3ef 8411 	mrs	r4, BASEPRI
    2ece:	f383 8812 	msr	BASEPRI_MAX, r3
    2ed2:	f3bf 8f6f 	isb	sy
	hfclk_users |= HF_USER_GENERIC;
    2ed6:	4a13      	ldr	r2, [pc, #76]	; (2f24 <generic_hfclk_start+0x60>)
    2ed8:	6813      	ldr	r3, [r2, #0]
    2eda:	f043 0302 	orr.w	r3, r3, #2
    2ede:	6013      	str	r3, [r2, #0]
	if (hfclk_users & HF_USER_BT) {
    2ee0:	f013 0f01 	tst.w	r3, #1
    2ee4:	d108      	bne.n	2ef8 <generic_hfclk_start+0x34>
	bool already_started = false;
    2ee6:	2300      	movs	r3, #0
	__asm__ volatile(
    2ee8:	f384 8811 	msr	BASEPRI, r4
    2eec:	f3bf 8f6f 	isb	sy
	if (already_started) {
    2ef0:	b99b      	cbnz	r3, 2f1a <generic_hfclk_start+0x56>
	hfclk_start();
    2ef2:	f004 fb20 	bl	7536 <hfclk_start>
}
    2ef6:	bd10      	pop	{r4, pc}
            break;
        case NRF_CLOCK_DOMAIN_HFCLK:
            if (p_clk_src != NULL)
            {
                (*(nrf_clock_hfclk_t *)p_clk_src) =
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    2ef8:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2efc:	f8d3 240c 	ldr.w	r2, [r3, #1036]	; 0x40c
                                        >> CLOCK_HFCLKSTAT_SRC_Pos);
            }
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    2f00:	f8d3 340c 	ldr.w	r3, [r3, #1036]	; 0x40c
		if (type == NRF_CLOCK_HFCLK_HIGH_ACCURACY) {
    2f04:	f012 0f01 	tst.w	r2, #1
    2f08:	d101      	bne.n	2f0e <generic_hfclk_start+0x4a>
	bool already_started = false;
    2f0a:	2300      	movs	r3, #0
    2f0c:	e7ec      	b.n	2ee8 <generic_hfclk_start+0x24>
			set_on_state(get_hf_flags());
    2f0e:	f7ff ffa5 	bl	2e5c <get_hf_flags>
    2f12:	f004 faa5 	bl	7460 <set_on_state>
			already_started = true;
    2f16:	2301      	movs	r3, #1
    2f18:	e7e6      	b.n	2ee8 <generic_hfclk_start+0x24>
		clkstarted_handle(CLOCK_DEVICE,
    2f1a:	2100      	movs	r1, #0
    2f1c:	4802      	ldr	r0, [pc, #8]	; (2f28 <generic_hfclk_start+0x64>)
    2f1e:	f004 fab2 	bl	7486 <clkstarted_handle>
		return;
    2f22:	e7e8      	b.n	2ef6 <generic_hfclk_start+0x32>
    2f24:	20000530 	.word	0x20000530
    2f28:	0000816c 	.word	0x0000816c

00002f2c <generic_hfclk_stop>:
{
    2f2c:	b508      	push	{r3, lr}
 *
 * @return Previous value of @a target.
 */
static inline atomic_val_t atomic_and(atomic_t *target, atomic_val_t value)
{
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    2f2e:	4b0a      	ldr	r3, [pc, #40]	; (2f58 <generic_hfclk_stop+0x2c>)
    2f30:	f3bf 8f5b 	dmb	ish
    2f34:	e853 2f00 	ldrex	r2, [r3]
    2f38:	f022 0102 	bic.w	r1, r2, #2
    2f3c:	e843 1000 	strex	r0, r1, [r3]
    2f40:	2800      	cmp	r0, #0
    2f42:	d1f7      	bne.n	2f34 <generic_hfclk_stop+0x8>
    2f44:	f3bf 8f5b 	dmb	ish
	if (atomic_and(&hfclk_users, ~HF_USER_GENERIC) & HF_USER_BT) {
    2f48:	f012 0f01 	tst.w	r2, #1
    2f4c:	d000      	beq.n	2f50 <generic_hfclk_stop+0x24>
}
    2f4e:	bd08      	pop	{r3, pc}
	hfclk_stop();
    2f50:	f004 fafb 	bl	754a <hfclk_stop>
    2f54:	e7fb      	b.n	2f4e <generic_hfclk_stop+0x22>
    2f56:	bf00      	nop
    2f58:	20000530 	.word	0x20000530

00002f5c <api_blocking_start>:
{
    2f5c:	b500      	push	{lr}
    2f5e:	b085      	sub	sp, #20
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    2f60:	f8cd d000 	str.w	sp, [sp]
    2f64:	f8cd d004 	str.w	sp, [sp, #4]
    2f68:	2300      	movs	r3, #0
    2f6a:	9302      	str	r3, [sp, #8]
    2f6c:	2301      	movs	r3, #1
    2f6e:	9303      	str	r3, [sp, #12]
	err = api_start(dev, subsys, blocking_start_callback, &sem);
    2f70:	466b      	mov	r3, sp
    2f72:	4a07      	ldr	r2, [pc, #28]	; (2f90 <api_blocking_start+0x34>)
    2f74:	f004 facf 	bl	7516 <api_start>
	if (err < 0) {
    2f78:	2800      	cmp	r0, #0
    2f7a:	db05      	blt.n	2f88 <api_blocking_start+0x2c>
	return z_impl_k_sem_take(sem, timeout);
    2f7c:	f44f 4280 	mov.w	r2, #16384	; 0x4000
    2f80:	2300      	movs	r3, #0
    2f82:	4668      	mov	r0, sp
    2f84:	f002 fc9c 	bl	58c0 <z_impl_k_sem_take>
}
    2f88:	b005      	add	sp, #20
    2f8a:	f85d fb04 	ldr.w	pc, [sp], #4
    2f8e:	bf00      	nop
    2f90:	00007555 	.word	0x00007555

00002f94 <clk_init>:
#endif /* NRF_CLOCK_HAS_HFCLKAUDIO */
#endif
}

static int clk_init(const struct device *dev)
{
    2f94:	b570      	push	{r4, r5, r6, lr}
    2f96:	4605      	mov	r5, r0
	static const struct onoff_transitions transitions = {
		.start = onoff_start,
		.stop = onoff_stop
	};

	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    2f98:	2200      	movs	r2, #0
    2f9a:	2101      	movs	r1, #1
    2f9c:	4610      	mov	r0, r2
    2f9e:	f7ff f935 	bl	220c <z_arm_irq_priority_set>
		    nrfx_isr, nrfx_power_clock_irq_handler, 0);
	irq_enable(DT_INST_IRQN(0));
    2fa2:	2000      	movs	r0, #0
    2fa4:	f7ff f914 	bl	21d0 <arch_irq_enable>

	nrfx_err = nrfx_clock_init(clock_event_handler);
    2fa8:	4813      	ldr	r0, [pc, #76]	; (2ff8 <clk_init+0x64>)
    2faa:	f001 fbaf 	bl	470c <nrfx_clock_init>
	if (nrfx_err != NRFX_SUCCESS) {
    2fae:	4b13      	ldr	r3, [pc, #76]	; (2ffc <clk_init+0x68>)
    2fb0:	4298      	cmp	r0, r3
    2fb2:	d11d      	bne.n	2ff0 <clk_init+0x5c>

	if (IS_ENABLED(CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC_CALIBRATION) &&
	    !IS_ENABLED(CONFIG_CLOCK_CONTROL_NRF_FORCE_ALT)) {
		struct nrf_clock_control_data *data = dev->data;

		z_nrf_clock_calibration_init(data->mgr);
    2fb4:	6928      	ldr	r0, [r5, #16]
    2fb6:	f000 f993 	bl	32e0 <z_nrf_clock_calibration_init>
	}

	nrfx_clock_enable();
    2fba:	f004 fbda 	bl	7772 <nrfx_clock_enable>

	for (enum clock_control_nrf_type i = 0;
    2fbe:	2400      	movs	r4, #0
    2fc0:	e003      	b.n	2fca <clk_init+0x36>
					 &transitions);
		if (err < 0) {
			return err;
		}

		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    2fc2:	2301      	movs	r3, #1
    2fc4:	60b3      	str	r3, [r6, #8]
		i < CLOCK_CONTROL_NRF_TYPE_COUNT; i++) {
    2fc6:	441c      	add	r4, r3
    2fc8:	b2e4      	uxtb	r4, r4
	for (enum clock_control_nrf_type i = 0;
    2fca:	2c01      	cmp	r4, #1
    2fcc:	d80e      	bhi.n	2fec <clk_init+0x58>
						get_sub_data(dev, i);
    2fce:	4621      	mov	r1, r4
    2fd0:	4628      	mov	r0, r5
    2fd2:	f004 f9f3 	bl	73bc <get_sub_data>
    2fd6:	4606      	mov	r6, r0
		err = onoff_manager_init(get_onoff_manager(dev, i),
    2fd8:	4621      	mov	r1, r4
    2fda:	4628      	mov	r0, r5
    2fdc:	f004 f9fb 	bl	73d6 <get_onoff_manager>
    2fe0:	4907      	ldr	r1, [pc, #28]	; (3000 <clk_init+0x6c>)
    2fe2:	f003 fda2 	bl	6b2a <onoff_manager_init>
		if (err < 0) {
    2fe6:	2800      	cmp	r0, #0
    2fe8:	daeb      	bge.n	2fc2 <clk_init+0x2e>
    2fea:	e000      	b.n	2fee <clk_init+0x5a>
	}

	return 0;
    2fec:	2000      	movs	r0, #0
}
    2fee:	bd70      	pop	{r4, r5, r6, pc}
		return -EIO;
    2ff0:	f06f 0004 	mvn.w	r0, #4
    2ff4:	e7fb      	b.n	2fee <clk_init+0x5a>
    2ff6:	bf00      	nop
    2ff8:	00003005 	.word	0x00003005
    2ffc:	0bad0000 	.word	0x0bad0000
    3000:	00008bbc 	.word	0x00008bbc

00003004 <clock_event_handler>:
{
    3004:	b508      	push	{r3, lr}
	switch (event) {
    3006:	2801      	cmp	r0, #1
    3008:	d010      	beq.n	302c <clock_event_handler+0x28>
    300a:	2803      	cmp	r0, #3
    300c:	d015      	beq.n	303a <clock_event_handler+0x36>
    300e:	b100      	cbz	r0, 3012 <clock_event_handler+0xe>
}
    3010:	bd08      	pop	{r3, pc}
				get_sub_data(dev, CLOCK_CONTROL_NRF_TYPE_HFCLK);
    3012:	2100      	movs	r1, #0
    3014:	480a      	ldr	r0, [pc, #40]	; (3040 <clock_event_handler+0x3c>)
    3016:	f004 f9d1 	bl	73bc <get_sub_data>
		if (GET_STATUS(data->flags) == CLOCK_CONTROL_STATUS_STARTING) {
    301a:	6883      	ldr	r3, [r0, #8]
    301c:	f013 0f07 	tst.w	r3, #7
    3020:	d1f6      	bne.n	3010 <clock_event_handler+0xc>
			clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_HFCLK);
    3022:	2100      	movs	r1, #0
    3024:	4806      	ldr	r0, [pc, #24]	; (3040 <clock_event_handler+0x3c>)
    3026:	f004 fa2e 	bl	7486 <clkstarted_handle>
    302a:	e7f1      	b.n	3010 <clock_event_handler+0xc>
			z_nrf_clock_calibration_lfclk_started();
    302c:	f004 faaf 	bl	758e <z_nrf_clock_calibration_lfclk_started>
		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_LFCLK);
    3030:	2101      	movs	r1, #1
    3032:	4803      	ldr	r0, [pc, #12]	; (3040 <clock_event_handler+0x3c>)
    3034:	f004 fa27 	bl	7486 <clkstarted_handle>
		break;
    3038:	e7ea      	b.n	3010 <clock_event_handler+0xc>
			z_nrf_clock_calibration_done_handler();
    303a:	f000 f967 	bl	330c <z_nrf_clock_calibration_done_handler>
}
    303e:	e7e7      	b.n	3010 <clock_event_handler+0xc>
    3040:	0000816c 	.word	0x0000816c

00003044 <lfclk_spinwait>:
{
    3044:	b570      	push	{r4, r5, r6, lr}
    3046:	4605      	mov	r5, r0
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    3048:	f004 fd5f 	bl	7b0a <k_is_in_isr>
    304c:	b920      	cbnz	r0, 3058 <lfclk_spinwait+0x14>
 */
static inline bool k_is_pre_kernel(void)
{
	extern bool z_sys_post_kernel; /* in init.c */

	return !z_sys_post_kernel;
    304e:	4b21      	ldr	r3, [pc, #132]	; (30d4 <lfclk_spinwait+0x90>)
    3050:	781b      	ldrb	r3, [r3, #0]
    3052:	b19b      	cbz	r3, 307c <lfclk_spinwait+0x38>
    3054:	2300      	movs	r3, #0
    3056:	e000      	b.n	305a <lfclk_spinwait+0x16>
    3058:	2301      	movs	r3, #1
	int key = isr_mode ? irq_lock() : 0;
    305a:	461c      	mov	r4, r3
    305c:	b183      	cbz	r3, 3080 <lfclk_spinwait+0x3c>
	__asm__ volatile(
    305e:	f04f 0320 	mov.w	r3, #32
    3062:	f3ef 8611 	mrs	r6, BASEPRI
    3066:	f383 8812 	msr	BASEPRI_MAX, r3
    306a:	f3bf 8f6f 	isb	sy
	if (!isr_mode) {
    306e:	b96c      	cbnz	r4, 308c <lfclk_spinwait+0x48>
    p_reg->INTENCLR = mask;
    3070:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    3074:	2202      	movs	r2, #2
    3076:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
}
    307a:	e007      	b.n	308c <lfclk_spinwait+0x48>
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    307c:	2301      	movs	r3, #1
    307e:	e7ec      	b.n	305a <lfclk_spinwait+0x16>
	int key = isr_mode ? irq_lock() : 0;
    3080:	2600      	movs	r6, #0
    3082:	e7f4      	b.n	306e <lfclk_spinwait+0x2a>
			if (isr_mode || !IS_ENABLED(CONFIG_MULTITHREADING)) {
    3084:	b1cc      	cbz	r4, 30ba <lfclk_spinwait+0x76>
 *
 * @return N/A
 */
static inline void k_cpu_atomic_idle(unsigned int key)
{
	arch_cpu_atomic_idle(key);
    3086:	4630      	mov	r0, r6
    3088:	f7ff f84a 	bl	2120 <arch_cpu_atomic_idle>
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    308c:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    3090:	f8d2 3418 	ldr.w	r3, [r2, #1048]	; 0x418
                                        >> CLOCK_LFCLKSTAT_SRC_Pos);
    3094:	f003 0303 	and.w	r3, r3, #3
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    3098:	f8d2 2418 	ldr.w	r2, [r2, #1048]	; 0x418
    309c:	f412 3f80 	tst.w	r2, #65536	; 0x10000
    30a0:	d110      	bne.n	30c4 <lfclk_spinwait+0x80>
#endif
        default:
            NRFX_ASSERT(0);
            return false;
    }
    return false;
    30a2:	2200      	movs	r2, #0
	while (!(nrfx_clock_is_running(d, (void *)&type)
    30a4:	2a00      	cmp	r2, #0
    30a6:	d0ed      	beq.n	3084 <lfclk_spinwait+0x40>
    30a8:	b10b      	cbz	r3, 30ae <lfclk_spinwait+0x6a>
		     || (mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE)))) {
    30aa:	2d01      	cmp	r5, #1
    30ac:	d1ea      	bne.n	3084 <lfclk_spinwait+0x40>
	if (isr_mode) {
    30ae:	b15c      	cbz	r4, 30c8 <lfclk_spinwait+0x84>
	__asm__ volatile(
    30b0:	f386 8811 	msr	BASEPRI, r6
    30b4:	f3bf 8f6f 	isb	sy
}
    30b8:	bd70      	pop	{r4, r5, r6, pc}
	return z_impl_k_sleep(timeout);
    30ba:	2021      	movs	r0, #33	; 0x21
    30bc:	2100      	movs	r1, #0
    30be:	f003 f921 	bl	6304 <z_impl_k_sleep>
	return k_sleep(Z_TIMEOUT_MS(ms));
    30c2:	e7e3      	b.n	308c <lfclk_spinwait+0x48>
                return true;
    30c4:	2201      	movs	r2, #1
    30c6:	e7ed      	b.n	30a4 <lfclk_spinwait+0x60>
    p_reg->INTENSET = mask;
    30c8:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    30cc:	2202      	movs	r2, #2
    30ce:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
}
    30d2:	e7f1      	b.n	30b8 <lfclk_spinwait+0x74>
    30d4:	20000b8a 	.word	0x20000b8a

000030d8 <z_nrf_clock_control_get_onoff>:
{
    30d8:	b508      	push	{r3, lr}
	return get_onoff_manager(CLOCK_DEVICE,
    30da:	b2c1      	uxtb	r1, r0
    30dc:	4801      	ldr	r0, [pc, #4]	; (30e4 <z_nrf_clock_control_get_onoff+0xc>)
    30de:	f004 f97a 	bl	73d6 <get_onoff_manager>
}
    30e2:	bd08      	pop	{r3, pc}
    30e4:	0000816c 	.word	0x0000816c

000030e8 <z_nrf_clock_control_lf_on>:
{
    30e8:	b510      	push	{r4, lr}
    30ea:	4604      	mov	r4, r0
	return __atomic_exchange_n(target, value, __ATOMIC_SEQ_CST);
    30ec:	4b10      	ldr	r3, [pc, #64]	; (3130 <z_nrf_clock_control_lf_on+0x48>)
    30ee:	2101      	movs	r1, #1
    30f0:	f3bf 8f5b 	dmb	ish
    30f4:	e853 2f00 	ldrex	r2, [r3]
    30f8:	e843 1000 	strex	r0, r1, [r3]
    30fc:	2800      	cmp	r0, #0
    30fe:	d1f9      	bne.n	30f4 <z_nrf_clock_control_lf_on+0xc>
    3100:	f3bf 8f5b 	dmb	ish
	if (atomic_set(&on, 1) == 0) {
    3104:	b11a      	cbz	r2, 310e <z_nrf_clock_control_lf_on+0x26>
	switch (start_mode) {
    3106:	1e63      	subs	r3, r4, #1
    3108:	2b01      	cmp	r3, #1
    310a:	d90c      	bls.n	3126 <z_nrf_clock_control_lf_on+0x3e>
}
    310c:	bd10      	pop	{r4, pc}
				get_onoff_manager(CLOCK_DEVICE,
    310e:	4809      	ldr	r0, [pc, #36]	; (3134 <z_nrf_clock_control_lf_on+0x4c>)
    3110:	f004 f961 	bl	73d6 <get_onoff_manager>
 */
static inline void sys_notify_init_spinwait(struct sys_notify *notify)
{
	__ASSERT_NO_MSG(notify != NULL);

	*notify = (struct sys_notify){
    3114:	4908      	ldr	r1, [pc, #32]	; (3138 <z_nrf_clock_control_lf_on+0x50>)
    3116:	2300      	movs	r3, #0
    3118:	604b      	str	r3, [r1, #4]
    311a:	60cb      	str	r3, [r1, #12]
    311c:	2301      	movs	r3, #1
    311e:	608b      	str	r3, [r1, #8]
		err = onoff_request(mgr, &cli);
    3120:	f003 fd1f 	bl	6b62 <onoff_request>
    3124:	e7ef      	b.n	3106 <z_nrf_clock_control_lf_on+0x1e>
		lfclk_spinwait(start_mode);
    3126:	4620      	mov	r0, r4
    3128:	f7ff ff8c 	bl	3044 <lfclk_spinwait>
		break;
    312c:	e7ee      	b.n	310c <z_nrf_clock_control_lf_on+0x24>
    312e:	bf00      	nop
    3130:	20000534 	.word	0x20000534
    3134:	0000816c 	.word	0x0000816c
    3138:	200004c8 	.word	0x200004c8

0000313c <get_temperature>:
	return (int16_t)(4 * val->val1 + val->val2 / 250000);
}

/* Function reads from temperature sensor and converts to 0.25'C units. */
static int get_temperature(int16_t *tvp)
{
    313c:	b510      	push	{r4, lr}
    313e:	b082      	sub	sp, #8
    3140:	4604      	mov	r4, r0
	struct sensor_value sensor_val;
	int rc = sensor_sample_fetch(temp_sensor);
    3142:	4b0e      	ldr	r3, [pc, #56]	; (317c <get_temperature+0x40>)
    3144:	6818      	ldr	r0, [r3, #0]
	const struct sensor_driver_api *api =
    3146:	6883      	ldr	r3, [r0, #8]
	return api->sample_fetch(dev, SENSOR_CHAN_ALL);
    3148:	68db      	ldr	r3, [r3, #12]
    314a:	2139      	movs	r1, #57	; 0x39
    314c:	4798      	blx	r3

	if (rc == 0) {
    314e:	b930      	cbnz	r0, 315e <get_temperature+0x22>
		rc = sensor_channel_get(temp_sensor, SENSOR_CHAN_DIE_TEMP,
    3150:	4b0a      	ldr	r3, [pc, #40]	; (317c <get_temperature+0x40>)
    3152:	6818      	ldr	r0, [r3, #0]
	const struct sensor_driver_api *api =
    3154:	6883      	ldr	r3, [r0, #8]
	return api->channel_get(dev, chan, val);
    3156:	691b      	ldr	r3, [r3, #16]
    3158:	466a      	mov	r2, sp
    315a:	210c      	movs	r1, #12
    315c:	4798      	blx	r3
					&sensor_val);
	}
	if (rc == 0) {
    315e:	b950      	cbnz	r0, 3176 <get_temperature+0x3a>
	return (int16_t)(4 * val->val1 + val->val2 / 250000);
    3160:	9b01      	ldr	r3, [sp, #4]
    3162:	4a07      	ldr	r2, [pc, #28]	; (3180 <get_temperature+0x44>)
    3164:	fb82 1203 	smull	r1, r2, r2, r3
    3168:	17db      	asrs	r3, r3, #31
    316a:	ebc3 4322 	rsb	r3, r3, r2, asr #16
    316e:	9a00      	ldr	r2, [sp, #0]
    3170:	eb03 0382 	add.w	r3, r3, r2, lsl #2
		*tvp = sensor_value_to_temp_unit(&sensor_val);
    3174:	8023      	strh	r3, [r4, #0]
	}
	return rc;
}
    3176:	b002      	add	sp, #8
    3178:	bd10      	pop	{r4, pc}
    317a:	bf00      	nop
    317c:	20000550 	.word	0x20000550
    3180:	431bde83 	.word	0x431bde83

00003184 <hf_release>:
{
    3184:	b508      	push	{r3, lr}
	clk_release(&mgrs[CLOCK_CONTROL_NRF_TYPE_HFCLK]);
    3186:	4b02      	ldr	r3, [pc, #8]	; (3190 <hf_release+0xc>)
    3188:	6818      	ldr	r0, [r3, #0]
    318a:	f004 f9ef 	bl	756c <clk_release>
}
    318e:	bd08      	pop	{r3, pc}
    3190:	2000054c 	.word	0x2000054c

00003194 <start_cycle>:
{
    3194:	b500      	push	{lr}
    3196:	b083      	sub	sp, #12
	z_impl_k_timer_start(timer, duration, period);
    3198:	2200      	movs	r2, #0
    319a:	2300      	movs	r3, #0
    319c:	e9cd 2300 	strd	r2, r3, [sp]
    31a0:	f44f 3200 	mov.w	r2, #131072	; 0x20000
    31a4:	2300      	movs	r3, #0
    31a6:	4805      	ldr	r0, [pc, #20]	; (31bc <start_cycle+0x28>)
    31a8:	f003 faf2 	bl	6790 <z_impl_k_timer_start>
	hf_release();
    31ac:	f7ff ffea 	bl	3184 <hf_release>
	cal_process_in_progress = 0;
    31b0:	4b03      	ldr	r3, [pc, #12]	; (31c0 <start_cycle+0x2c>)
    31b2:	2200      	movs	r2, #0
    31b4:	601a      	str	r2, [r3, #0]
}
    31b6:	b003      	add	sp, #12
    31b8:	f85d fb04 	ldr.w	pc, [sp], #4
    31bc:	20000078 	.word	0x20000078
    31c0:	20000538 	.word	0x20000538

000031c4 <start_hw_cal>:
{
    31c4:	b508      	push	{r3, lr}
		*(volatile uint32_t *)0x40000C34 = 0x00000002;
    31c6:	4b04      	ldr	r3, [pc, #16]	; (31d8 <start_hw_cal+0x14>)
    31c8:	2202      	movs	r2, #2
    31ca:	601a      	str	r2, [r3, #0]
	nrfx_clock_calibration_start();
    31cc:	f001 fb58 	bl	4880 <nrfx_clock_calibration_start>
	calib_skip_cnt = CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_MAX_SKIP;
    31d0:	4b02      	ldr	r3, [pc, #8]	; (31dc <start_hw_cal+0x18>)
    31d2:	2201      	movs	r2, #1
    31d4:	701a      	strb	r2, [r3, #0]
}
    31d6:	bd08      	pop	{r3, pc}
    31d8:	40000c34 	.word	0x40000c34
    31dc:	20000b88 	.word	0x20000b88

000031e0 <cal_hf_callback>:
{
    31e0:	b508      	push	{r3, lr}
	if ((temp_sensor == NULL) || !IS_ENABLED(CONFIG_MULTITHREADING)) {
    31e2:	4b05      	ldr	r3, [pc, #20]	; (31f8 <cal_hf_callback+0x18>)
    31e4:	681b      	ldr	r3, [r3, #0]
    31e6:	b11b      	cbz	r3, 31f0 <cal_hf_callback+0x10>
		k_work_submit(&temp_measure_work);
    31e8:	4804      	ldr	r0, [pc, #16]	; (31fc <cal_hf_callback+0x1c>)
    31ea:	f002 fcb3 	bl	5b54 <k_work_submit>
}
    31ee:	bd08      	pop	{r3, pc}
		start_hw_cal();
    31f0:	f7ff ffe8 	bl	31c4 <start_hw_cal>
    31f4:	e7fb      	b.n	31ee <cal_hf_callback+0xe>
    31f6:	bf00      	nop
    31f8:	20000550 	.word	0x20000550
    31fc:	20000010 	.word	0x20000010

00003200 <measure_temperature>:
/* Function determines if calibration should be performed based on temperature
 * measurement. Function is called from system work queue context. It is
 * reading temperature from TEMP sensor and compares with last measurement.
 */
static void measure_temperature(struct k_work *work)
{
    3200:	b500      	push	{lr}
    3202:	b083      	sub	sp, #12
	int16_t temperature = 0;
    3204:	2300      	movs	r3, #0
    3206:	f8ad 3006 	strh.w	r3, [sp, #6]
	int16_t diff = 0;
	bool started = false;
	int rc;

	rc = get_temperature(&temperature);
    320a:	f10d 0006 	add.w	r0, sp, #6
    320e:	f7ff ff95 	bl	313c <get_temperature>

	if (rc != 0) {
    3212:	b180      	cbz	r0, 3236 <measure_temperature+0x36>
		/* Temperature read failed, force calibration. */
		calib_skip_cnt = 0;
    3214:	2000      	movs	r0, #0
    3216:	4b12      	ldr	r3, [pc, #72]	; (3260 <measure_temperature+0x60>)
    3218:	7018      	strb	r0, [r3, #0]
	} else {
		diff = abs(temperature - prev_temperature);
	}

	if ((calib_skip_cnt == 0) ||
    321a:	4b11      	ldr	r3, [pc, #68]	; (3260 <measure_temperature+0x60>)
    321c:	781b      	ldrb	r3, [r3, #0]
    321e:	b10b      	cbz	r3, 3224 <measure_temperature+0x24>
    3220:	2801      	cmp	r0, #1
    3222:	dd12      	ble.n	324a <measure_temperature+0x4a>
		(diff >= CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_TEMP_DIFF)) {
		prev_temperature = temperature;
    3224:	4b0f      	ldr	r3, [pc, #60]	; (3264 <measure_temperature+0x64>)
    3226:	f8bd 2006 	ldrh.w	r2, [sp, #6]
    322a:	801a      	strh	r2, [r3, #0]
		started = true;
		start_hw_cal();
    322c:	f7ff ffca 	bl	31c4 <start_hw_cal>
		start_cycle();
	}

	LOG_DBG("Calibration %s. Temperature diff: %d (in 0.25'C units).",
			started ? "started" : "skipped", diff);
}
    3230:	b003      	add	sp, #12
    3232:	f85d fb04 	ldr.w	pc, [sp], #4
		diff = abs(temperature - prev_temperature);
    3236:	f9bd 0006 	ldrsh.w	r0, [sp, #6]
    323a:	4b0a      	ldr	r3, [pc, #40]	; (3264 <measure_temperature+0x64>)
    323c:	f9b3 3000 	ldrsh.w	r3, [r3]
    3240:	1ac0      	subs	r0, r0, r3
    3242:	f004 ff16 	bl	8072 <abs>
    3246:	b200      	sxth	r0, r0
    3248:	e7e7      	b.n	321a <measure_temperature+0x1a>
		calib_skip_cnt--;
    324a:	3b01      	subs	r3, #1
    324c:	4a04      	ldr	r2, [pc, #16]	; (3260 <measure_temperature+0x60>)
    324e:	7013      	strb	r3, [r2, #0]
		total_skips_cnt++;
    3250:	4a05      	ldr	r2, [pc, #20]	; (3268 <measure_temperature+0x68>)
    3252:	6813      	ldr	r3, [r2, #0]
    3254:	3301      	adds	r3, #1
    3256:	6013      	str	r3, [r2, #0]
		start_cycle();
    3258:	f7ff ff9c 	bl	3194 <start_cycle>
}
    325c:	e7e8      	b.n	3230 <measure_temperature+0x30>
    325e:	bf00      	nop
    3260:	20000b88 	.word	0x20000b88
    3264:	20000b80 	.word	0x20000b80
    3268:	20000558 	.word	0x20000558

0000326c <hf_request>:
{
    326c:	b508      	push	{r3, lr}
	clk_request(&mgrs[CLOCK_CONTROL_NRF_TYPE_HFCLK], &cli, cal_hf_callback);
    326e:	4a03      	ldr	r2, [pc, #12]	; (327c <hf_request+0x10>)
    3270:	4903      	ldr	r1, [pc, #12]	; (3280 <hf_request+0x14>)
    3272:	4b04      	ldr	r3, [pc, #16]	; (3284 <hf_request+0x18>)
    3274:	6818      	ldr	r0, [r3, #0]
    3276:	f004 f97d 	bl	7574 <clk_request>
}
    327a:	bd08      	pop	{r3, pc}
    327c:	000031e1 	.word	0x000031e1
    3280:	2000053c 	.word	0x2000053c
    3284:	2000054c 	.word	0x2000054c

00003288 <start_cal_process>:
{
    3288:	b508      	push	{r3, lr}
	return __atomic_compare_exchange_n(target, &old_value, new_value,
    328a:	4b09      	ldr	r3, [pc, #36]	; (32b0 <start_cal_process+0x28>)
    328c:	2201      	movs	r2, #1
    328e:	f3bf 8f5b 	dmb	ish
    3292:	e853 1f00 	ldrex	r1, [r3]
    3296:	2900      	cmp	r1, #0
    3298:	d103      	bne.n	32a2 <start_cal_process+0x1a>
    329a:	e843 2000 	strex	r0, r2, [r3]
    329e:	2800      	cmp	r0, #0
    32a0:	d1f7      	bne.n	3292 <start_cal_process+0xa>
    32a2:	f3bf 8f5b 	dmb	ish
	if (atomic_cas(&cal_process_in_progress, 0, 1) == false) {
    32a6:	d101      	bne.n	32ac <start_cal_process+0x24>
		hf_request();
    32a8:	f7ff ffe0 	bl	326c <hf_request>
}
    32ac:	bd08      	pop	{r3, pc}
    32ae:	bf00      	nop
    32b0:	20000538 	.word	0x20000538

000032b4 <start_unconditional_cal_process>:

SYS_INIT(temp_sensor_init, APPLICATION, 0);
#endif /* CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_MAX_SKIP */

static void start_unconditional_cal_process(void)
{
    32b4:	b508      	push	{r3, lr}
	calib_skip_cnt = 0;
    32b6:	4b03      	ldr	r3, [pc, #12]	; (32c4 <start_unconditional_cal_process+0x10>)
    32b8:	2200      	movs	r2, #0
    32ba:	701a      	strb	r2, [r3, #0]
	start_cal_process();
    32bc:	f7ff ffe4 	bl	3288 <start_cal_process>
}
    32c0:	bd08      	pop	{r3, pc}
    32c2:	bf00      	nop
    32c4:	20000b88 	.word	0x20000b88

000032c8 <temp_sensor_init>:
{
    32c8:	b508      	push	{r3, lr}
    32ca:	4803      	ldr	r0, [pc, #12]	; (32d8 <temp_sensor_init+0x10>)
    32cc:	f001 fef4 	bl	50b8 <z_impl_device_get_binding>
	temp_sensor = temp_device();
    32d0:	4b02      	ldr	r3, [pc, #8]	; (32dc <temp_sensor_init+0x14>)
    32d2:	6018      	str	r0, [r3, #0]
}
    32d4:	2000      	movs	r0, #0
    32d6:	bd08      	pop	{r3, pc}
    32d8:	00008bc8 	.word	0x00008bc8
    32dc:	20000550 	.word	0x20000550

000032e0 <z_nrf_clock_calibration_init>:
	mgrs = onoff_mgrs;
    32e0:	4b03      	ldr	r3, [pc, #12]	; (32f0 <z_nrf_clock_calibration_init+0x10>)
    32e2:	6018      	str	r0, [r3, #0]
	total_cnt = 0;
    32e4:	2300      	movs	r3, #0
    32e6:	4a03      	ldr	r2, [pc, #12]	; (32f4 <z_nrf_clock_calibration_init+0x14>)
    32e8:	6013      	str	r3, [r2, #0]
	total_skips_cnt = 0;
    32ea:	4a03      	ldr	r2, [pc, #12]	; (32f8 <z_nrf_clock_calibration_init+0x18>)
    32ec:	6013      	str	r3, [r2, #0]
}
    32ee:	4770      	bx	lr
    32f0:	2000054c 	.word	0x2000054c
    32f4:	20000554 	.word	0x20000554
    32f8:	20000558 	.word	0x20000558

000032fc <z_nrf_clock_calibration_lfclk_stopped>:
{
	start_unconditional_cal_process();
}

void z_nrf_clock_calibration_lfclk_stopped(void)
{
    32fc:	b508      	push	{r3, lr}
	z_impl_k_timer_stop(timer);
    32fe:	4802      	ldr	r0, [pc, #8]	; (3308 <z_nrf_clock_calibration_lfclk_stopped+0xc>)
    3300:	f004 fe9b 	bl	803a <z_impl_k_timer_stop>
	k_timer_stop(&backoff_timer);
	LOG_DBG("Calibration stopped");
}
    3304:	bd08      	pop	{r3, pc}
    3306:	bf00      	nop
    3308:	20000078 	.word	0x20000078

0000330c <z_nrf_clock_calibration_done_handler>:

void z_nrf_clock_calibration_done_handler(void)
{
    330c:	b508      	push	{r3, lr}
	total_cnt++;
    330e:	4a03      	ldr	r2, [pc, #12]	; (331c <z_nrf_clock_calibration_done_handler+0x10>)
    3310:	6813      	ldr	r3, [r2, #0]
    3312:	3301      	adds	r3, #1
    3314:	6013      	str	r3, [r2, #0]
	LOG_DBG("Calibration done.");

	start_cycle();
    3316:	f7ff ff3d 	bl	3194 <start_cycle>
}
    331a:	bd08      	pop	{r3, pc}
    331c:	20000554 	.word	0x20000554

00003320 <console_out>:
 *
 * @return The character passed as input.
 */

static int console_out(int c)
{
    3320:	b510      	push	{r4, lr}
    3322:	4604      	mov	r4, r0
		return c;
	}

#endif  /* CONFIG_UART_CONSOLE_DEBUG_SERVER_HOOKS */

	if ('\n' == c) {
    3324:	280a      	cmp	r0, #10
    3326:	d007      	beq.n	3338 <console_out+0x18>
		uart_poll_out(uart_console_dev, '\r');
	}
	uart_poll_out(uart_console_dev, c);
    3328:	4b07      	ldr	r3, [pc, #28]	; (3348 <console_out+0x28>)
    332a:	6818      	ldr	r0, [r3, #0]
    332c:	b2e1      	uxtb	r1, r4
	const struct uart_driver_api *api =
    332e:	6883      	ldr	r3, [r0, #8]
	api->poll_out(dev, out_char);
    3330:	685b      	ldr	r3, [r3, #4]
    3332:	4798      	blx	r3

	return c;
}
    3334:	4620      	mov	r0, r4
    3336:	bd10      	pop	{r4, pc}
		uart_poll_out(uart_console_dev, '\r');
    3338:	4b03      	ldr	r3, [pc, #12]	; (3348 <console_out+0x28>)
    333a:	6818      	ldr	r0, [r3, #0]
	const struct uart_driver_api *api =
    333c:	6883      	ldr	r3, [r0, #8]
	api->poll_out(dev, out_char);
    333e:	685b      	ldr	r3, [r3, #4]
    3340:	210d      	movs	r1, #13
    3342:	4798      	blx	r3
		return;
	}
#endif
	compiler_barrier();
	z_impl_uart_poll_out(dev, out_char);
}
    3344:	e7f0      	b.n	3328 <console_out+0x8>
    3346:	bf00      	nop
    3348:	2000055c 	.word	0x2000055c

0000334c <uart_console_hook_install>:
 *
 * @return N/A
 */

static void uart_console_hook_install(void)
{
    334c:	b510      	push	{r4, lr}
	__stdout_hook_install(console_out);
    334e:	4c04      	ldr	r4, [pc, #16]	; (3360 <uart_console_hook_install+0x14>)
    3350:	4620      	mov	r0, r4
    3352:	f7ff fd43 	bl	2ddc <__stdout_hook_install>
	__printk_hook_install(console_out);
    3356:	4620      	mov	r0, r4
    3358:	f7fd f8a0 	bl	49c <__printk_hook_install>
}
    335c:	bd10      	pop	{r4, pc}
    335e:	bf00      	nop
    3360:	00003321 	.word	0x00003321

00003364 <uart_console_init>:
 * @brief Initialize one UART as the console/debug port
 *
 * @return 0 if successful, otherwise failed.
 */
static int uart_console_init(const struct device *arg)
{
    3364:	b508      	push	{r3, lr}

	ARG_UNUSED(arg);

	/* Claim console device */
	uart_console_dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_console));
    3366:	4806      	ldr	r0, [pc, #24]	; (3380 <uart_console_init+0x1c>)
    3368:	4b06      	ldr	r3, [pc, #24]	; (3384 <uart_console_init+0x20>)
    336a:	6018      	str	r0, [r3, #0]
 *
 * @return a non-positive integer as documented in device_usable_check().
 */
static inline int z_device_usable_check(const struct device *dev)
{
	return z_device_ready(dev) ? 0 : -ENODEV;
    336c:	f004 fb62 	bl	7a34 <z_device_ready>
    3370:	b118      	cbz	r0, 337a <uart_console_init+0x16>
	if (!device_is_ready(uart_console_dev)) {
		return -ENODEV;
	}

	uart_console_hook_install();
    3372:	f7ff ffeb 	bl	334c <uart_console_hook_install>

	return 0;
    3376:	2000      	movs	r0, #0
}
    3378:	bd08      	pop	{r3, pc}
		return -ENODEV;
    337a:	f06f 0012 	mvn.w	r0, #18
    337e:	e7fb      	b.n	3378 <uart_console_init+0x14>
    3380:	00008184 	.word	0x00008184
    3384:	2000055c 	.word	0x2000055c

00003388 <gpio_nrfx_config>:
	return res;
}

static int gpio_nrfx_config(const struct device *port,
			    gpio_pin_t pin, gpio_flags_t flags)
{
    3388:	b4f0      	push	{r4, r5, r6, r7}
	return port->config;
    338a:	6843      	ldr	r3, [r0, #4]
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    338c:	685f      	ldr	r7, [r3, #4]
	nrf_gpio_pin_pull_t pull;
	nrf_gpio_pin_drive_t drive;
	nrf_gpio_pin_dir_t dir;
	nrf_gpio_pin_input_t input;

	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    338e:	4b37      	ldr	r3, [pc, #220]	; (346c <gpio_nrfx_config+0xe4>)
    3390:	4013      	ands	r3, r2
    3392:	4c37      	ldr	r4, [pc, #220]	; (3470 <gpio_nrfx_config+0xe8>)
    3394:	42a3      	cmp	r3, r4
    3396:	d027      	beq.n	33e8 <gpio_nrfx_config+0x60>
    3398:	d812      	bhi.n	33c0 <gpio_nrfx_config+0x38>
    339a:	2b06      	cmp	r3, #6
    339c:	d026      	beq.n	33ec <gpio_nrfx_config+0x64>
    339e:	d904      	bls.n	33aa <gpio_nrfx_config+0x22>
    33a0:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
    33a4:	d109      	bne.n	33ba <gpio_nrfx_config+0x32>
	case GPIO_DS_DFLT_LOW | GPIO_OPEN_DRAIN:
		drive = NRF_GPIO_PIN_S0D1;
		break;

	case GPIO_DS_ALT_LOW | GPIO_DS_DFLT_HIGH:
		drive = NRF_GPIO_PIN_H0S1;
    33a6:	2401      	movs	r4, #1
    33a8:	e016      	b.n	33d8 <gpio_nrfx_config+0x50>
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    33aa:	b30b      	cbz	r3, 33f0 <gpio_nrfx_config+0x68>
    33ac:	2b02      	cmp	r3, #2
    33ae:	d101      	bne.n	33b4 <gpio_nrfx_config+0x2c>
	case GPIO_DS_ALT_LOW | GPIO_OPEN_DRAIN:
		drive = NRF_GPIO_PIN_H0D1;
		break;

	case GPIO_DS_DFLT_HIGH | GPIO_OPEN_SOURCE:
		drive = NRF_GPIO_PIN_D0S1;
    33b0:	2404      	movs	r4, #4
    33b2:	e011      	b.n	33d8 <gpio_nrfx_config+0x50>
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    33b4:	f06f 0015 	mvn.w	r0, #21
    33b8:	e046      	b.n	3448 <gpio_nrfx_config+0xc0>
    33ba:	f06f 0015 	mvn.w	r0, #21
    33be:	e043      	b.n	3448 <gpio_nrfx_config+0xc0>
    33c0:	4c2c      	ldr	r4, [pc, #176]	; (3474 <gpio_nrfx_config+0xec>)
    33c2:	42a3      	cmp	r3, r4
    33c4:	d016      	beq.n	33f4 <gpio_nrfx_config+0x6c>
    33c6:	f5b3 0fa0 	cmp.w	r3, #5242880	; 0x500000
    33ca:	d101      	bne.n	33d0 <gpio_nrfx_config+0x48>
		drive = NRF_GPIO_PIN_H0H1;
    33cc:	2403      	movs	r4, #3
    33ce:	e003      	b.n	33d8 <gpio_nrfx_config+0x50>
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    33d0:	f5b3 0f80 	cmp.w	r3, #4194304	; 0x400000
    33d4:	d146      	bne.n	3464 <gpio_nrfx_config+0xdc>
		drive = NRF_GPIO_PIN_S0H1;
    33d6:	2402      	movs	r4, #2

	default:
		return -EINVAL;
	}

	if ((flags & GPIO_PULL_UP) != 0) {
    33d8:	f012 0f10 	tst.w	r2, #16
    33dc:	d10c      	bne.n	33f8 <gpio_nrfx_config+0x70>
		pull = NRF_GPIO_PIN_PULLUP;
	} else if ((flags & GPIO_PULL_DOWN) != 0) {
    33de:	f012 0f20 	tst.w	r2, #32
    33e2:	d033      	beq.n	344c <gpio_nrfx_config+0xc4>
		pull = NRF_GPIO_PIN_PULLDOWN;
    33e4:	2501      	movs	r5, #1
    33e6:	e008      	b.n	33fa <gpio_nrfx_config+0x72>
		drive = NRF_GPIO_PIN_H0D1;
    33e8:	2407      	movs	r4, #7
    33ea:	e7f5      	b.n	33d8 <gpio_nrfx_config+0x50>
		drive = NRF_GPIO_PIN_S0D1;
    33ec:	2406      	movs	r4, #6
    33ee:	e7f3      	b.n	33d8 <gpio_nrfx_config+0x50>
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    33f0:	2400      	movs	r4, #0
    33f2:	e7f1      	b.n	33d8 <gpio_nrfx_config+0x50>
		drive = NRF_GPIO_PIN_D0H1;
    33f4:	2405      	movs	r4, #5
    33f6:	e7ef      	b.n	33d8 <gpio_nrfx_config+0x50>
		pull = NRF_GPIO_PIN_PULLUP;
    33f8:	2503      	movs	r5, #3
	} else {
		pull = NRF_GPIO_PIN_NOPULL;
	}

	dir = ((flags & GPIO_OUTPUT) != 0)
    33fa:	f3c2 2340 	ubfx	r3, r2, #9, #1
	      ? NRF_GPIO_PIN_DIR_OUTPUT
	      : NRF_GPIO_PIN_DIR_INPUT;

	input = ((flags & GPIO_INPUT) != 0)
		? NRF_GPIO_PIN_INPUT_CONNECT
		: NRF_GPIO_PIN_INPUT_DISCONNECT;
    33fe:	f412 7f80 	tst.w	r2, #256	; 0x100
    3402:	bf0c      	ite	eq
    3404:	2601      	moveq	r6, #1
    3406:	2600      	movne	r6, #0

	if ((flags & GPIO_OUTPUT) != 0) {
    3408:	f412 7f00 	tst.w	r2, #512	; 0x200
    340c:	d006      	beq.n	341c <gpio_nrfx_config+0x94>
		if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
    340e:	f412 6f00 	tst.w	r2, #2048	; 0x800
    3412:	d01d      	beq.n	3450 <gpio_nrfx_config+0xc8>
			nrf_gpio_port_out_set(reg, BIT(pin));
    3414:	2201      	movs	r2, #1
    3416:	408a      	lsls	r2, r1
}


NRF_STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask)
{
    p_reg->OUTSET = set_mask;
    3418:	f8c7 2508 	str.w	r2, [r7, #1288]	; 0x508
	return port->config;
    341c:	6842      	ldr	r2, [r0, #4]
		} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
			nrf_gpio_port_out_clear(reg, BIT(pin));
		}
	}

	nrf_gpio_cfg(NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin),
    341e:	7a12      	ldrb	r2, [r2, #8]
    3420:	f001 011f 	and.w	r1, r1, #31
    3424:	ea41 1242 	orr.w	r2, r1, r2, lsl #5
NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin)
{
    uint32_t pin_number = *p_pin;
    *p_pin = pin_number & 0x1F;

    return pin_number >> 5;
    3428:	0952      	lsrs	r2, r2, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    342a:	2a01      	cmp	r2, #1
    342c:	d018      	beq.n	3460 <gpio_nrfx_config+0xd8>
        case 0: return NRF_P0;
    342e:	f04f 42a0 	mov.w	r2, #1342177280	; 0x50000000
    cnf |= ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)     |
    3432:	ea43 0346 	orr.w	r3, r3, r6, lsl #1
           ((uint32_t)input << GPIO_PIN_CNF_INPUT_Pos) |
    3436:	ea43 0385 	orr.w	r3, r3, r5, lsl #2
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    343a:	ea43 2304 	orr.w	r3, r3, r4, lsl #8
    reg->PIN_CNF[pin_number] = cnf;
    343e:	f501 71e0 	add.w	r1, r1, #448	; 0x1c0
    3442:	f842 3021 	str.w	r3, [r2, r1, lsl #2]
		     dir, input, pull, drive, NRF_GPIO_PIN_NOSENSE);

	return 0;
    3446:	2000      	movs	r0, #0
}
    3448:	bcf0      	pop	{r4, r5, r6, r7}
    344a:	4770      	bx	lr
		pull = NRF_GPIO_PIN_NOPULL;
    344c:	2500      	movs	r5, #0
    344e:	e7d4      	b.n	33fa <gpio_nrfx_config+0x72>
		} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
    3450:	f412 6f80 	tst.w	r2, #1024	; 0x400
    3454:	d0e2      	beq.n	341c <gpio_nrfx_config+0x94>
			nrf_gpio_port_out_clear(reg, BIT(pin));
    3456:	2201      	movs	r2, #1
    3458:	408a      	lsls	r2, r1
    p_reg->OUTCLR = clr_mask;
    345a:	f8c7 250c 	str.w	r2, [r7, #1292]	; 0x50c
}
    345e:	e7dd      	b.n	341c <gpio_nrfx_config+0x94>
        case 1: return NRF_P1;
    3460:	4a05      	ldr	r2, [pc, #20]	; (3478 <gpio_nrfx_config+0xf0>)
    3462:	e7e6      	b.n	3432 <gpio_nrfx_config+0xaa>
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    3464:	f06f 0015 	mvn.w	r0, #21
    3468:	e7ee      	b.n	3448 <gpio_nrfx_config+0xc0>
    346a:	bf00      	nop
    346c:	00f00006 	.word	0x00f00006
    3470:	00100006 	.word	0x00100006
    3474:	00400002 	.word	0x00400002
    3478:	50000300 	.word	0x50000300

0000347c <cfg_level_pins>:
	 */
	return out;
}

static void cfg_level_pins(const struct device *port)
{
    347c:	b4f0      	push	{r4, r5, r6, r7}
	return port->data;
    347e:	6905      	ldr	r5, [r0, #16]
	return port->config;
    3480:	6846      	ldr	r6, [r0, #4]
	uint32_t out = data->pin_int_en;
    3482:	68e9      	ldr	r1, [r5, #12]
	out &= ~data->trig_edge & ~data->double_edge;
    3484:	696a      	ldr	r2, [r5, #20]
    3486:	69ab      	ldr	r3, [r5, #24]
    3488:	4313      	orrs	r3, r2
    348a:	ea21 0103 	bic.w	r1, r1, r3
	const struct gpio_nrfx_data *data = get_port_data(port);
	const struct gpio_nrfx_cfg *cfg = get_port_cfg(port);
	uint32_t pin = 0U;
	uint32_t bit = 1U << pin;
    348e:	2301      	movs	r3, #1
	uint32_t pin = 0U;
    3490:	2000      	movs	r0, #0
	uint32_t level_pins = get_level_pins(port);

	/* Configure sense detection on all pins that use it. */
	while (level_pins) {
    3492:	e011      	b.n	34b8 <cfg_level_pins+0x3c>
		return NRF_GPIO_PIN_SENSE_HIGH;
    3494:	f04f 0c02 	mov.w	ip, #2
    3498:	e01d      	b.n	34d6 <cfg_level_pins+0x5a>
    349a:	4f14      	ldr	r7, [pc, #80]	; (34ec <cfg_level_pins+0x70>)
    uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_SENSE_Msk;
    349c:	f504 74e0 	add.w	r4, r4, #448	; 0x1c0
    34a0:	f857 2024 	ldr.w	r2, [r7, r4, lsl #2]
    34a4:	f422 3240 	bic.w	r2, r2, #196608	; 0x30000
    reg->PIN_CNF[pin_number] = cnf | (sense_config << GPIO_PIN_CNF_SENSE_Pos);
    34a8:	ea42 420c 	orr.w	r2, r2, ip, lsl #16
    34ac:	f847 2024 	str.w	r2, [r7, r4, lsl #2]
		if (level_pins & bit) {
			uint32_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
			uint32_t sense = sense_for_pin(data, pin);

			nrf_gpio_cfg_sense_set(abs_pin, sense);
			level_pins &= ~bit;
    34b0:	ea21 0103 	bic.w	r1, r1, r3
		}
		++pin;
    34b4:	3001      	adds	r0, #1
		bit <<= 1;
    34b6:	005b      	lsls	r3, r3, #1
	while (level_pins) {
    34b8:	b1a9      	cbz	r1, 34e6 <cfg_level_pins+0x6a>
		if (level_pins & bit) {
    34ba:	420b      	tst	r3, r1
    34bc:	d0fa      	beq.n	34b4 <cfg_level_pins+0x38>
			uint32_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    34be:	7a34      	ldrb	r4, [r6, #8]
    34c0:	f000 021f 	and.w	r2, r0, #31
    34c4:	ea42 1244 	orr.w	r2, r2, r4, lsl #5
	if ((BIT(pin) & data->int_active_level) != 0U) {
    34c8:	692c      	ldr	r4, [r5, #16]
    34ca:	40c4      	lsrs	r4, r0
    34cc:	f014 0f01 	tst.w	r4, #1
    34d0:	d1e0      	bne.n	3494 <cfg_level_pins+0x18>
	return NRF_GPIO_PIN_SENSE_LOW;
    34d2:	f04f 0c03 	mov.w	ip, #3
    *p_pin = pin_number & 0x1F;
    34d6:	f002 041f 	and.w	r4, r2, #31
    return pin_number >> 5;
    34da:	0952      	lsrs	r2, r2, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    34dc:	2a01      	cmp	r2, #1
    34de:	d0dc      	beq.n	349a <cfg_level_pins+0x1e>
        case 0: return NRF_P0;
    34e0:	f04f 47a0 	mov.w	r7, #1342177280	; 0x50000000
    34e4:	e7da      	b.n	349c <cfg_level_pins+0x20>
	}
}
    34e6:	bcf0      	pop	{r4, r5, r6, r7}
    34e8:	4770      	bx	lr
    34ea:	bf00      	nop
    34ec:	50000300 	.word	0x50000300

000034f0 <check_level_trigger_pins>:
 *
 * @return Bitmask where 1 marks pin as trigger source.
 */
static uint32_t check_level_trigger_pins(const struct device *port,
					 uint32_t *sense_levels)
{
    34f0:	b5f0      	push	{r4, r5, r6, r7, lr}
    34f2:	468c      	mov	ip, r1
	return port->data;
    34f4:	6903      	ldr	r3, [r0, #16]
	return port->config;
    34f6:	6841      	ldr	r1, [r0, #4]
	uint32_t out = data->pin_int_en;
    34f8:	68df      	ldr	r7, [r3, #12]
	out &= ~data->trig_edge & ~data->double_edge;
    34fa:	695a      	ldr	r2, [r3, #20]
    34fc:	6998      	ldr	r0, [r3, #24]
    34fe:	4302      	orrs	r2, r0
    3500:	ea27 0702 	bic.w	r7, r7, r2
	struct gpio_nrfx_data *data = get_port_data(port);
	const struct gpio_nrfx_cfg *cfg = get_port_cfg(port);
	uint32_t level_pins = get_level_pins(port);
	uint32_t port_in = nrf_gpio_port_in_read(cfg->port);
    3504:	684a      	ldr	r2, [r1, #4]
    return p_reg->IN;
    3506:	f8d2 2510 	ldr.w	r2, [r2, #1296]	; 0x510

	/* Extract which pins have logic level same as interrupt trigger level.
	 */
	uint32_t pin_states = ~(port_in ^ data->int_active_level);
    350a:	6918      	ldr	r0, [r3, #16]
    350c:	4050      	eors	r0, r2

	/* Discard pins that aren't configured for level. */
	uint32_t out = pin_states & level_pins;
    350e:	ea27 0000 	bic.w	r0, r7, r0
	uint32_t pin = 0U;
	uint32_t bit = 1U << pin;

	uint32_t port_latch = 0;

	uint32_t check_pins = level_pins;
    3512:	463c      	mov	r4, r7
	uint32_t bit = 1U << pin;
    3514:	2301      	movs	r3, #1
	uint32_t pin = 0U;
    3516:	2500      	movs	r5, #0
#if IS_ENABLED(CONFIG_GPIO_NRF_INT_EDGE_USING_SENSE)
	/* Read LATCH, which will tell us which pin has changed its state. */
	port_latch = cfg->port->LATCH;
#endif

	while (check_pins) {
    3518:	e015      	b.n	3546 <check_level_trigger_pins+0x56>
        case 1: return NRF_P1;
    351a:	f8df e074 	ldr.w	lr, [pc, #116]	; 3590 <check_level_trigger_pins+0xa0>
    351e:	e025      	b.n	356c <check_level_trigger_pins+0x7c>
    *p_pin = pin_number & 0x1F;
    3520:	f002 061f 	and.w	r6, r2, #31
    return pin_number >> 5;
    3524:	0952      	lsrs	r2, r2, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    3526:	2a01      	cmp	r2, #1
    3528:	d02e      	beq.n	3588 <check_level_trigger_pins+0x98>
        case 0: return NRF_P0;
    352a:	f04f 4ea0 	mov.w	lr, #1342177280	; 0x50000000
    uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_SENSE_Msk;
    352e:	f506 72e0 	add.w	r2, r6, #448	; 0x1c0
    3532:	f85e 6022 	ldr.w	r6, [lr, r2, lsl #2]
    3536:	f426 3640 	bic.w	r6, r6, #196608	; 0x30000
    reg->PIN_CNF[pin_number] = cnf | (sense_config << GPIO_PIN_CNF_SENSE_Pos);
    353a:	f84e 6022 	str.w	r6, [lr, r2, lsl #2]
					*sense_levels |= bit;
				}
			}

			nrf_gpio_cfg_sense_set(abs_pin, NRF_GPIO_PIN_NOSENSE);
			check_pins &= ~bit;
    353e:	ea24 0403 	bic.w	r4, r4, r3
		}
		++pin;
    3542:	3501      	adds	r5, #1
		bit <<= 1;
    3544:	005b      	lsls	r3, r3, #1
	while (check_pins) {
    3546:	b314      	cbz	r4, 358e <check_level_trigger_pins+0x9e>
		if (check_pins & bit) {
    3548:	4223      	tst	r3, r4
    354a:	d0fa      	beq.n	3542 <check_level_trigger_pins+0x52>
			uint32_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    354c:	7a0e      	ldrb	r6, [r1, #8]
    354e:	f005 021f 	and.w	r2, r5, #31
    3552:	ea42 1246 	orr.w	r2, r2, r6, lsl #5
			if (!(level_pins & bit)) {
    3556:	423b      	tst	r3, r7
    3558:	d1e2      	bne.n	3520 <check_level_trigger_pins+0x30>
    *p_pin = pin_number & 0x1F;
    355a:	f002 061f 	and.w	r6, r2, #31
    return pin_number >> 5;
    355e:	ea4f 1e52 	mov.w	lr, r2, lsr #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    3562:	f1be 0f01 	cmp.w	lr, #1
    3566:	d0d8      	beq.n	351a <check_level_trigger_pins+0x2a>
        case 0: return NRF_P0;
    3568:	f04f 4ea0 	mov.w	lr, #1342177280	; 0x50000000
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    356c:	f506 76e0 	add.w	r6, r6, #448	; 0x1c0
    3570:	f85e 6026 	ldr.w	r6, [lr, r6, lsl #2]
                                   GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos);
    3574:	f3c6 4601 	ubfx	r6, r6, #16, #2
				if (high) {
    3578:	2e02      	cmp	r6, #2
    357a:	d1d1      	bne.n	3520 <check_level_trigger_pins+0x30>
					*sense_levels |= bit;
    357c:	f8dc 6000 	ldr.w	r6, [ip]
    3580:	431e      	orrs	r6, r3
    3582:	f8cc 6000 	str.w	r6, [ip]
    3586:	e7cb      	b.n	3520 <check_level_trigger_pins+0x30>
        case 1: return NRF_P1;
    3588:	f8df e004 	ldr.w	lr, [pc, #4]	; 3590 <check_level_trigger_pins+0xa0>
    358c:	e7cf      	b.n	352e <check_level_trigger_pins+0x3e>
	 */
	cfg->port->LATCH = port_latch;
#endif

	return out;
}
    358e:	bdf0      	pop	{r4, r5, r6, r7, pc}
    3590:	50000300 	.word	0x50000300

00003594 <gpiote_pin_cleanup>:
{
    3594:	b510      	push	{r4, lr}
    p_reg->INTENCLR = mask;
}

NRF_STATIC_INLINE uint32_t nrf_gpiote_int_enable_check(NRF_GPIOTE_Type const * p_reg, uint32_t mask)
{
    return p_reg->INTENSET & mask;
    3596:	4b14      	ldr	r3, [pc, #80]	; (35e8 <gpiote_pin_cleanup+0x54>)
    3598:	f8d3 4304 	ldr.w	r4, [r3, #772]	; 0x304
    359c:	b2e4      	uxtb	r4, r4
	for (size_t i = 0; i < GPIOTE_CH_NUM; i++) {
    359e:	2300      	movs	r3, #0
    35a0:	e000      	b.n	35a4 <gpiote_pin_cleanup+0x10>
    35a2:	3301      	adds	r3, #1
    35a4:	2b07      	cmp	r3, #7
    35a6:	d81d      	bhi.n	35e4 <gpiote_pin_cleanup+0x50>
                        ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk);
}

NRF_STATIC_INLINE uint32_t nrf_gpiote_event_pin_get(NRF_GPIOTE_Type const * p_reg, uint32_t idx)
{
    return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
    35a8:	f503 72a2 	add.w	r2, r3, #324	; 0x144
    35ac:	490e      	ldr	r1, [pc, #56]	; (35e8 <gpiote_pin_cleanup+0x54>)
    35ae:	f851 2022 	ldr.w	r2, [r1, r2, lsl #2]
    35b2:	f3c2 2205 	ubfx	r2, r2, #8, #6
		if ((nrf_gpiote_event_pin_get(NRF_GPIOTE, i) == abs_pin)
    35b6:	4290      	cmp	r0, r2
    35b8:	d1f3      	bne.n	35a2 <gpiote_pin_cleanup+0xe>
		    && (intenset & BIT(i))) {
    35ba:	fa24 f203 	lsr.w	r2, r4, r3
    35be:	f012 0f01 	tst.w	r2, #1
    35c2:	d0ee      	beq.n	35a2 <gpiote_pin_cleanup+0xe>
   p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Event;
    35c4:	460a      	mov	r2, r1
    35c6:	f503 70a2 	add.w	r0, r3, #324	; 0x144
    35ca:	f851 1020 	ldr.w	r1, [r1, r0, lsl #2]
    35ce:	f021 0101 	bic.w	r1, r1, #1
    35d2:	f842 1020 	str.w	r1, [r2, r0, lsl #2]
			nrf_gpiote_int_disable(NRF_GPIOTE, BIT(i));
    35d6:	2101      	movs	r1, #1
    35d8:	4099      	lsls	r1, r3
    p_reg->INTENCLR = mask;
    35da:	f8c2 1308 	str.w	r1, [r2, #776]	; 0x308
			nrfx_gpiote_channel_free(i);
    35de:	b2d8      	uxtb	r0, r3
    35e0:	f001 f9fc 	bl	49dc <nrfx_gpiote_channel_free>
}
    35e4:	bd10      	pop	{r4, pc}
    35e6:	bf00      	nop
    35e8:	40006000 	.word	0x40006000

000035ec <gpiote_channel_alloc>:
{
    35ec:	b570      	push	{r4, r5, r6, lr}
    35ee:	b082      	sub	sp, #8
    35f0:	4604      	mov	r4, r0
    35f2:	460d      	mov	r5, r1
	if (nrfx_gpiote_channel_alloc(&channel) != NRFX_SUCCESS) {
    35f4:	f10d 0007 	add.w	r0, sp, #7
    35f8:	f001 fa0c 	bl	4a14 <nrfx_gpiote_channel_alloc>
    35fc:	4b1c      	ldr	r3, [pc, #112]	; (3670 <gpiote_channel_alloc+0x84>)
    35fe:	4298      	cmp	r0, r3
    3600:	d132      	bne.n	3668 <gpiote_channel_alloc+0x7c>
	nrf_gpiote_event_t evt = offsetof(NRF_GPIOTE_Type, EVENTS_IN[channel]);
    3602:	f89d 3007 	ldrb.w	r3, [sp, #7]
    3606:	f103 0240 	add.w	r2, r3, #64	; 0x40
    360a:	0092      	lsls	r2, r2, #2
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk);
    360c:	4e19      	ldr	r6, [pc, #100]	; (3674 <gpiote_channel_alloc+0x88>)
    360e:	f503 73a2 	add.w	r3, r3, #324	; 0x144
    3612:	f856 1023 	ldr.w	r1, [r6, r3, lsl #2]
    3616:	f421 314f 	bic.w	r1, r1, #211968	; 0x33c00
    361a:	f421 7140 	bic.w	r1, r1, #768	; 0x300
    361e:	f846 1023 	str.w	r1, [r6, r3, lsl #2]
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    3622:	f856 1023 	ldr.w	r1, [r6, r3, lsl #2]
    3626:	0224      	lsls	r4, r4, #8
    3628:	f404 547c 	and.w	r4, r4, #16128	; 0x3f00
                        ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk);
    362c:	042d      	lsls	r5, r5, #16
    362e:	f405 3540 	and.w	r5, r5, #196608	; 0x30000
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    3632:	432c      	orrs	r4, r5
    3634:	430c      	orrs	r4, r1
    3636:	f846 4023 	str.w	r4, [r6, r3, lsl #2]
    return ((uint32_t)p_reg + event);
    363a:	f102 4380 	add.w	r3, r2, #1073741824	; 0x40000000
    363e:	f503 43c0 	add.w	r3, r3, #24576	; 0x6000
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    3642:	2000      	movs	r0, #0
    3644:	6018      	str	r0, [r3, #0]
#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE void nrf_event_readback(void * p_event_reg)
{
#if NRFX_CHECK(NRFX_EVENT_READBACK_ENABLED) && !defined(NRF51)
    (void)*((volatile uint32_t *)(p_event_reg));
    3646:	681b      	ldr	r3, [r3, #0]
	nrf_gpiote_event_enable(NRF_GPIOTE, channel);
    3648:	f89d 1007 	ldrb.w	r1, [sp, #7]
   p_reg->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event;
    364c:	f501 73a2 	add.w	r3, r1, #324	; 0x144
    3650:	f856 2023 	ldr.w	r2, [r6, r3, lsl #2]
    3654:	f042 0201 	orr.w	r2, r2, #1
    3658:	f846 2023 	str.w	r2, [r6, r3, lsl #2]
	nrf_gpiote_int_enable(NRF_GPIOTE, BIT(channel));
    365c:	2301      	movs	r3, #1
    365e:	408b      	lsls	r3, r1
    p_reg->INTENSET = mask;
    3660:	f8c6 3304 	str.w	r3, [r6, #772]	; 0x304
}
    3664:	b002      	add	sp, #8
    3666:	bd70      	pop	{r4, r5, r6, pc}
		return -ENODEV;
    3668:	f06f 0012 	mvn.w	r0, #18
    366c:	e7fa      	b.n	3664 <gpiote_channel_alloc+0x78>
    366e:	bf00      	nop
    3670:	0bad0000 	.word	0x0bad0000
    3674:	40006000 	.word	0x40006000

00003678 <gpiote_pin_int_cfg>:
{
    3678:	b570      	push	{r4, r5, r6, lr}
    367a:	460d      	mov	r5, r1
	return port->data;
    367c:	6906      	ldr	r6, [r0, #16]
	return port->config;
    367e:	6843      	ldr	r3, [r0, #4]
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    3680:	7a1b      	ldrb	r3, [r3, #8]
    3682:	f001 041f 	and.w	r4, r1, #31
    3686:	ea44 1443 	orr.w	r4, r4, r3, lsl #5
	gpiote_pin_cleanup(abs_pin);
    368a:	4620      	mov	r0, r4
    368c:	f7ff ff82 	bl	3594 <gpiote_pin_cleanup>
    *p_pin = pin_number & 0x1F;
    3690:	f004 001f 	and.w	r0, r4, #31
    return pin_number >> 5;
    3694:	0963      	lsrs	r3, r4, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    3696:	2b01      	cmp	r3, #1
    3698:	d020      	beq.n	36dc <gpiote_pin_int_cfg+0x64>
        case 0: return NRF_P0;
    369a:	f04f 42a0 	mov.w	r2, #1342177280	; 0x50000000
    uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_SENSE_Msk;
    369e:	f500 71e0 	add.w	r1, r0, #448	; 0x1c0
    36a2:	f852 3021 	ldr.w	r3, [r2, r1, lsl #2]
    36a6:	f423 3340 	bic.w	r3, r3, #196608	; 0x30000
    reg->PIN_CNF[pin_number] = cnf | (sense_config << GPIO_PIN_CNF_SENSE_Pos);
    36aa:	f842 3021 	str.w	r3, [r2, r1, lsl #2]
	if (data->pin_int_en & BIT(pin)) {
    36ae:	68f3      	ldr	r3, [r6, #12]
    36b0:	40eb      	lsrs	r3, r5
    36b2:	f013 0f01 	tst.w	r3, #1
    36b6:	d02f      	beq.n	3718 <gpiote_pin_int_cfg+0xa0>
		if (data->trig_edge & BIT(pin)) {
    36b8:	6973      	ldr	r3, [r6, #20]
    36ba:	40eb      	lsrs	r3, r5
    36bc:	f013 0f01 	tst.w	r3, #1
    36c0:	d015      	beq.n	36ee <gpiote_pin_int_cfg+0x76>
				if (data->double_edge & BIT(pin)) {
    36c2:	69b3      	ldr	r3, [r6, #24]
    36c4:	40eb      	lsrs	r3, r5
    36c6:	f013 0f01 	tst.w	r3, #1
    36ca:	d109      	bne.n	36e0 <gpiote_pin_int_cfg+0x68>
				} else if ((data->int_active_level & BIT(pin)) != 0U) {
    36cc:	6931      	ldr	r1, [r6, #16]
    36ce:	fa21 f505 	lsr.w	r5, r1, r5
    36d2:	f015 0f01 	tst.w	r5, #1
    36d6:	d008      	beq.n	36ea <gpiote_pin_int_cfg+0x72>
					pol = NRF_GPIOTE_POLARITY_LOTOHI;
    36d8:	2101      	movs	r1, #1
    36da:	e002      	b.n	36e2 <gpiote_pin_int_cfg+0x6a>
        case 1: return NRF_P1;
    36dc:	4a0f      	ldr	r2, [pc, #60]	; (371c <gpiote_pin_int_cfg+0xa4>)
    36de:	e7de      	b.n	369e <gpiote_pin_int_cfg+0x26>
					pol = NRF_GPIOTE_POLARITY_TOGGLE;
    36e0:	2103      	movs	r1, #3
				res = gpiote_channel_alloc(abs_pin, pol);
    36e2:	4620      	mov	r0, r4
    36e4:	f7ff ff82 	bl	35ec <gpiote_channel_alloc>
    36e8:	e017      	b.n	371a <gpiote_pin_int_cfg+0xa2>
					pol = NRF_GPIOTE_POLARITY_HITOLO;
    36ea:	2102      	movs	r1, #2
    36ec:	e7f9      	b.n	36e2 <gpiote_pin_int_cfg+0x6a>
	if ((BIT(pin) & data->int_active_level) != 0U) {
    36ee:	6931      	ldr	r1, [r6, #16]
    36f0:	fa21 f505 	lsr.w	r5, r1, r5
    36f4:	f015 0f01 	tst.w	r5, #1
    36f8:	d10c      	bne.n	3714 <gpiote_pin_int_cfg+0x9c>
	return NRF_GPIO_PIN_SENSE_LOW;
    36fa:	2103      	movs	r1, #3
    uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_SENSE_Msk;
    36fc:	f500 70e0 	add.w	r0, r0, #448	; 0x1c0
    3700:	f852 3020 	ldr.w	r3, [r2, r0, lsl #2]
    3704:	f423 3340 	bic.w	r3, r3, #196608	; 0x30000
    reg->PIN_CNF[pin_number] = cnf | (sense_config << GPIO_PIN_CNF_SENSE_Pos);
    3708:	ea43 4301 	orr.w	r3, r3, r1, lsl #16
    370c:	f842 3020 	str.w	r3, [r2, r0, lsl #2]
	int res = 0;
    3710:	2000      	movs	r0, #0
}
    3712:	e002      	b.n	371a <gpiote_pin_int_cfg+0xa2>
		return NRF_GPIO_PIN_SENSE_HIGH;
    3714:	2102      	movs	r1, #2
    3716:	e7f1      	b.n	36fc <gpiote_pin_int_cfg+0x84>
	int res = 0;
    3718:	2000      	movs	r0, #0
}
    371a:	bd70      	pop	{r4, r5, r6, pc}
    371c:	50000300 	.word	0x50000300

00003720 <gpio_nrfx_pin_interrupt_configure>:
{
    3720:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	return port->data;
    3722:	6904      	ldr	r4, [r0, #16]
	return port->config;
    3724:	6845      	ldr	r5, [r0, #4]
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
    3726:	7a2e      	ldrb	r6, [r5, #8]
    3728:	f001 051f 	and.w	r5, r1, #31
    372c:	ea45 1546 	orr.w	r5, r5, r6, lsl #5
	if (!IS_ENABLED(CONFIG_GPIO_NRF_INT_EDGE_USING_SENSE) &&
    3730:	f5b2 3fa0 	cmp.w	r2, #81920	; 0x14000
    3734:	d025      	beq.n	3782 <gpio_nrfx_pin_interrupt_configure+0x62>
	WRITE_BIT(data->pin_int_en, pin, mode != GPIO_INT_MODE_DISABLED);
    3736:	f5b2 5f00 	cmp.w	r2, #8192	; 0x2000
    373a:	d035      	beq.n	37a8 <gpio_nrfx_pin_interrupt_configure+0x88>
    373c:	68e5      	ldr	r5, [r4, #12]
    373e:	2601      	movs	r6, #1
    3740:	408e      	lsls	r6, r1
    3742:	4335      	orrs	r5, r6
    3744:	60e5      	str	r5, [r4, #12]
	WRITE_BIT(data->trig_edge, pin, mode == GPIO_INT_MODE_EDGE);
    3746:	f5b2 3fa0 	cmp.w	r2, #81920	; 0x14000
    374a:	d033      	beq.n	37b4 <gpio_nrfx_pin_interrupt_configure+0x94>
    374c:	6962      	ldr	r2, [r4, #20]
    374e:	2501      	movs	r5, #1
    3750:	408d      	lsls	r5, r1
    3752:	ea22 0205 	bic.w	r2, r2, r5
    3756:	6162      	str	r2, [r4, #20]
	WRITE_BIT(data->double_edge, pin, trig == GPIO_INT_TRIG_BOTH);
    3758:	f5b3 2fc0 	cmp.w	r3, #393216	; 0x60000
    375c:	d02f      	beq.n	37be <gpio_nrfx_pin_interrupt_configure+0x9e>
    375e:	69a2      	ldr	r2, [r4, #24]
    3760:	2501      	movs	r5, #1
    3762:	408d      	lsls	r5, r1
    3764:	ea22 0205 	bic.w	r2, r2, r5
    3768:	61a2      	str	r2, [r4, #24]
	WRITE_BIT(data->int_active_level, pin, trig == GPIO_INT_TRIG_HIGH);
    376a:	f5b3 2f80 	cmp.w	r3, #262144	; 0x40000
    376e:	d02b      	beq.n	37c8 <gpio_nrfx_pin_interrupt_configure+0xa8>
    3770:	6923      	ldr	r3, [r4, #16]
    3772:	2201      	movs	r2, #1
    3774:	408a      	lsls	r2, r1
    3776:	ea23 0302 	bic.w	r3, r3, r2
    377a:	6123      	str	r3, [r4, #16]
	return gpiote_pin_int_cfg(port, pin);
    377c:	f7ff ff7c 	bl	3678 <gpiote_pin_int_cfg>
}
    3780:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    *p_pin = pin_number & 0x1F;
    3782:	f005 061f 	and.w	r6, r5, #31
    return pin_number >> 5;
    3786:	096d      	lsrs	r5, r5, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    3788:	2d01      	cmp	r5, #1
    378a:	d00b      	beq.n	37a4 <gpio_nrfx_pin_interrupt_configure+0x84>
        case 0: return NRF_P0;
    378c:	f04f 47a0 	mov.w	r7, #1342177280	; 0x50000000
    return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
    3790:	f506 75e0 	add.w	r5, r6, #448	; 0x1c0
    3794:	f857 5025 	ldr.w	r5, [r7, r5, lsl #2]
	    (mode == GPIO_INT_MODE_EDGE) &&
    3798:	f015 0f01 	tst.w	r5, #1
    379c:	d0cb      	beq.n	3736 <gpio_nrfx_pin_interrupt_configure+0x16>
		return -ENOTSUP;
    379e:	f06f 0085 	mvn.w	r0, #133	; 0x85
    37a2:	e7ed      	b.n	3780 <gpio_nrfx_pin_interrupt_configure+0x60>
        case 1: return NRF_P1;
    37a4:	4f0b      	ldr	r7, [pc, #44]	; (37d4 <gpio_nrfx_pin_interrupt_configure+0xb4>)
    37a6:	e7f3      	b.n	3790 <gpio_nrfx_pin_interrupt_configure+0x70>
	WRITE_BIT(data->pin_int_en, pin, mode != GPIO_INT_MODE_DISABLED);
    37a8:	68e5      	ldr	r5, [r4, #12]
    37aa:	2601      	movs	r6, #1
    37ac:	408e      	lsls	r6, r1
    37ae:	ea25 0506 	bic.w	r5, r5, r6
    37b2:	e7c7      	b.n	3744 <gpio_nrfx_pin_interrupt_configure+0x24>
	WRITE_BIT(data->trig_edge, pin, mode == GPIO_INT_MODE_EDGE);
    37b4:	6962      	ldr	r2, [r4, #20]
    37b6:	2501      	movs	r5, #1
    37b8:	408d      	lsls	r5, r1
    37ba:	432a      	orrs	r2, r5
    37bc:	e7cb      	b.n	3756 <gpio_nrfx_pin_interrupt_configure+0x36>
	WRITE_BIT(data->double_edge, pin, trig == GPIO_INT_TRIG_BOTH);
    37be:	69a2      	ldr	r2, [r4, #24]
    37c0:	2501      	movs	r5, #1
    37c2:	408d      	lsls	r5, r1
    37c4:	432a      	orrs	r2, r5
    37c6:	e7cf      	b.n	3768 <gpio_nrfx_pin_interrupt_configure+0x48>
	WRITE_BIT(data->int_active_level, pin, trig == GPIO_INT_TRIG_HIGH);
    37c8:	6923      	ldr	r3, [r4, #16]
    37ca:	2201      	movs	r2, #1
    37cc:	408a      	lsls	r2, r1
    37ce:	4313      	orrs	r3, r2
    37d0:	e7d3      	b.n	377a <gpio_nrfx_pin_interrupt_configure+0x5a>
    37d2:	bf00      	nop
    37d4:	50000300 	.word	0x50000300

000037d8 <gpio_nrfx_init>:
}

#define GPIOTE_NODE DT_INST(0, nordic_nrf_gpiote)

static int gpio_nrfx_init(const struct device *port)
{
    37d8:	b508      	push	{r3, lr}
	static bool gpio_initialized;

	if (!gpio_initialized) {
    37da:	4b0b      	ldr	r3, [pc, #44]	; (3808 <gpio_nrfx_init+0x30>)
    37dc:	781b      	ldrb	r3, [r3, #0]
    37de:	b10b      	cbz	r3, 37e4 <gpio_nrfx_init+0xc>
		irq_enable(DT_IRQN(GPIOTE_NODE));
		nrf_gpiote_int_enable(NRF_GPIOTE, NRF_GPIOTE_INT_PORT_MASK);
	}

	return 0;
}
    37e0:	2000      	movs	r0, #0
    37e2:	bd08      	pop	{r3, pc}
		gpio_initialized = true;
    37e4:	4b08      	ldr	r3, [pc, #32]	; (3808 <gpio_nrfx_init+0x30>)
    37e6:	2201      	movs	r2, #1
    37e8:	701a      	strb	r2, [r3, #0]
		IRQ_CONNECT(DT_IRQN(GPIOTE_NODE), DT_IRQ(GPIOTE_NODE, priority),
    37ea:	2200      	movs	r2, #0
    37ec:	2105      	movs	r1, #5
    37ee:	2006      	movs	r0, #6
    37f0:	f7fe fd0c 	bl	220c <z_arm_irq_priority_set>
		irq_enable(DT_IRQN(GPIOTE_NODE));
    37f4:	2006      	movs	r0, #6
    37f6:	f7fe fceb 	bl	21d0 <arch_irq_enable>
    37fa:	4b04      	ldr	r3, [pc, #16]	; (380c <gpio_nrfx_init+0x34>)
    37fc:	f04f 4200 	mov.w	r2, #2147483648	; 0x80000000
    3800:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
}
    3804:	e7ec      	b.n	37e0 <gpio_nrfx_init+0x8>
    3806:	bf00      	nop
    3808:	20000b89 	.word	0x20000b89
    380c:	40006000 	.word	0x40006000

00003810 <gpiote_event_handler>:
{
    3810:	b570      	push	{r4, r5, r6, lr}
    3812:	b084      	sub	sp, #16
	uint32_t fired_triggers[GPIO_COUNT] = {0};
    3814:	2300      	movs	r3, #0
    3816:	9302      	str	r3, [sp, #8]
    3818:	9303      	str	r3, [sp, #12]
	uint32_t sense_levels[GPIO_COUNT] = {0};
    381a:	9300      	str	r3, [sp, #0]
    381c:	9301      	str	r3, [sp, #4]
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    381e:	4b46      	ldr	r3, [pc, #280]	; (3938 <gpiote_event_handler+0x128>)
    3820:	681c      	ldr	r4, [r3, #0]
	if (port_event) {
    3822:	b90c      	cbnz	r4, 3828 <gpiote_event_handler+0x18>
{
    3824:	2100      	movs	r1, #0
    3826:	e011      	b.n	384c <gpiote_event_handler+0x3c>
			check_level_trigger_pins(DEVICE_DT_GET(GPIO(0)),
    3828:	4d44      	ldr	r5, [pc, #272]	; (393c <gpiote_event_handler+0x12c>)
    382a:	4669      	mov	r1, sp
    382c:	4628      	mov	r0, r5
    382e:	f7ff fe5f 	bl	34f0 <check_level_trigger_pins>
		fired_triggers[0] =
    3832:	9002      	str	r0, [sp, #8]
			check_level_trigger_pins(DEVICE_DT_GET(GPIO(1)),
    3834:	a901      	add	r1, sp, #4
    3836:	f105 0018 	add.w	r0, r5, #24
    383a:	f7ff fe59 	bl	34f0 <check_level_trigger_pins>
		fired_triggers[1] =
    383e:	9003      	str	r0, [sp, #12]
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    3840:	4b3d      	ldr	r3, [pc, #244]	; (3938 <gpiote_event_handler+0x128>)
    3842:	2200      	movs	r2, #0
    3844:	601a      	str	r2, [r3, #0]
    3846:	681b      	ldr	r3, [r3, #0]
}
    3848:	e7ec      	b.n	3824 <gpiote_event_handler+0x14>
	for (size_t i = 0; i < GPIOTE_CH_NUM; i++) {
    384a:	3101      	adds	r1, #1
    384c:	2907      	cmp	r1, #7
    384e:	d82d      	bhi.n	38ac <gpiote_event_handler+0x9c>
		nrf_gpiote_event_t evt =
    3850:	f101 0340 	add.w	r3, r1, #64	; 0x40
    3854:	009b      	lsls	r3, r3, #2
    3856:	b29a      	uxth	r2, r3
		if (nrf_gpiote_int_enable_check(NRF_GPIOTE, BIT(i)) &&
    3858:	2301      	movs	r3, #1
    385a:	408b      	lsls	r3, r1
    return p_reg->INTENSET & mask;
    385c:	4838      	ldr	r0, [pc, #224]	; (3940 <gpiote_event_handler+0x130>)
    385e:	f8d0 0304 	ldr.w	r0, [r0, #772]	; 0x304
    3862:	4203      	tst	r3, r0
    3864:	d0f1      	beq.n	384a <gpiote_event_handler+0x3a>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    3866:	f102 4380 	add.w	r3, r2, #1073741824	; 0x40000000
    386a:	f503 43c0 	add.w	r3, r3, #24576	; 0x6000
    386e:	681b      	ldr	r3, [r3, #0]
    3870:	2b00      	cmp	r3, #0
    3872:	d0ea      	beq.n	384a <gpiote_event_handler+0x3a>
    return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
    3874:	f501 73a2 	add.w	r3, r1, #324	; 0x144
    3878:	4831      	ldr	r0, [pc, #196]	; (3940 <gpiote_event_handler+0x130>)
    387a:	f850 0023 	ldr.w	r0, [r0, r3, lsl #2]
			fired_triggers[abs_pin / 32U] |= BIT(abs_pin % 32);
    387e:	f3c0 3340 	ubfx	r3, r0, #13, #1
    3882:	f3c0 2004 	ubfx	r0, r0, #8, #5
    3886:	2501      	movs	r5, #1
    3888:	fa05 f000 	lsl.w	r0, r5, r0
    388c:	ad04      	add	r5, sp, #16
    388e:	eb05 0383 	add.w	r3, r5, r3, lsl #2
    3892:	f853 5c08 	ldr.w	r5, [r3, #-8]
    3896:	4305      	orrs	r5, r0
    3898:	f843 5c08 	str.w	r5, [r3, #-8]
    return ((uint32_t)p_reg + event);
    389c:	f102 4380 	add.w	r3, r2, #1073741824	; 0x40000000
    38a0:	f503 43c0 	add.w	r3, r3, #24576	; 0x6000
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    38a4:	2200      	movs	r2, #0
    38a6:	601a      	str	r2, [r3, #0]
    38a8:	681b      	ldr	r3, [r3, #0]
}
    38aa:	e7ce      	b.n	384a <gpiote_event_handler+0x3a>
	if (fired_triggers[0]) {
    38ac:	9e02      	ldr	r6, [sp, #8]
    38ae:	b92e      	cbnz	r6, 38bc <gpiote_event_handler+0xac>
	if (fired_triggers[1]) {
    38b0:	9e03      	ldr	r6, [sp, #12]
    38b2:	b9ee      	cbnz	r6, 38f0 <gpiote_event_handler+0xe0>
	if (port_event) {
    38b4:	2c00      	cmp	r4, #0
    38b6:	d135      	bne.n	3924 <gpiote_event_handler+0x114>
}
    38b8:	b004      	add	sp, #16
    38ba:	bd70      	pop	{r4, r5, r6, pc}
	return list->head;
    38bc:	4b21      	ldr	r3, [pc, #132]	; (3944 <gpiote_event_handler+0x134>)
    38be:	6859      	ldr	r1, [r3, #4]
					const struct device *port,
					uint32_t pins)
{
	struct gpio_callback *cb, *tmp;

	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    38c0:	b119      	cbz	r1, 38ca <gpiote_event_handler+0xba>
    38c2:	460d      	mov	r5, r1
Z_GENLIST_PEEK_NEXT(slist, snode)
    38c4:	b149      	cbz	r1, 38da <gpiote_event_handler+0xca>
	return node->next;
    38c6:	680d      	ldr	r5, [r1, #0]
    38c8:	e007      	b.n	38da <gpiote_event_handler+0xca>
    38ca:	460d      	mov	r5, r1
    38cc:	e005      	b.n	38da <gpiote_event_handler+0xca>
    38ce:	b16d      	cbz	r5, 38ec <gpiote_event_handler+0xdc>
    38d0:	462b      	mov	r3, r5
Z_GENLIST_PEEK_NEXT(slist, snode)
    38d2:	b105      	cbz	r5, 38d6 <gpiote_event_handler+0xc6>
	return node->next;
    38d4:	682b      	ldr	r3, [r5, #0]
    38d6:	4629      	mov	r1, r5
    38d8:	461d      	mov	r5, r3
    38da:	2900      	cmp	r1, #0
    38dc:	d0e8      	beq.n	38b0 <gpiote_event_handler+0xa0>
		if (cb->pin_mask & pins) {
    38de:	688a      	ldr	r2, [r1, #8]
    38e0:	4032      	ands	r2, r6
    38e2:	d0f4      	beq.n	38ce <gpiote_event_handler+0xbe>
			__ASSERT(cb->handler, "No callback handler!");
			cb->handler(port, cb, cb->pin_mask & pins);
    38e4:	684b      	ldr	r3, [r1, #4]
    38e6:	4815      	ldr	r0, [pc, #84]	; (393c <gpiote_event_handler+0x12c>)
    38e8:	4798      	blx	r3
    38ea:	e7f0      	b.n	38ce <gpiote_event_handler+0xbe>
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    38ec:	462b      	mov	r3, r5
    38ee:	e7f2      	b.n	38d6 <gpiote_event_handler+0xc6>
	return list->head;
    38f0:	4b15      	ldr	r3, [pc, #84]	; (3948 <gpiote_event_handler+0x138>)
    38f2:	6859      	ldr	r1, [r3, #4]
    38f4:	b119      	cbz	r1, 38fe <gpiote_event_handler+0xee>
    38f6:	460d      	mov	r5, r1
Z_GENLIST_PEEK_NEXT(slist, snode)
    38f8:	b149      	cbz	r1, 390e <gpiote_event_handler+0xfe>
	return node->next;
    38fa:	680d      	ldr	r5, [r1, #0]
    38fc:	e007      	b.n	390e <gpiote_event_handler+0xfe>
    38fe:	460d      	mov	r5, r1
    3900:	e005      	b.n	390e <gpiote_event_handler+0xfe>
    3902:	b16d      	cbz	r5, 3920 <gpiote_event_handler+0x110>
    3904:	462b      	mov	r3, r5
Z_GENLIST_PEEK_NEXT(slist, snode)
    3906:	b105      	cbz	r5, 390a <gpiote_event_handler+0xfa>
	return node->next;
    3908:	682b      	ldr	r3, [r5, #0]
    390a:	4629      	mov	r1, r5
    390c:	461d      	mov	r5, r3
    390e:	2900      	cmp	r1, #0
    3910:	d0d0      	beq.n	38b4 <gpiote_event_handler+0xa4>
		if (cb->pin_mask & pins) {
    3912:	688a      	ldr	r2, [r1, #8]
    3914:	4032      	ands	r2, r6
    3916:	d0f4      	beq.n	3902 <gpiote_event_handler+0xf2>
			cb->handler(port, cb, cb->pin_mask & pins);
    3918:	684b      	ldr	r3, [r1, #4]
    391a:	480c      	ldr	r0, [pc, #48]	; (394c <gpiote_event_handler+0x13c>)
    391c:	4798      	blx	r3
    391e:	e7f0      	b.n	3902 <gpiote_event_handler+0xf2>
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    3920:	462b      	mov	r3, r5
    3922:	e7f2      	b.n	390a <gpiote_event_handler+0xfa>
		cfg_level_pins(DEVICE_DT_GET(GPIO(0)));
    3924:	4c05      	ldr	r4, [pc, #20]	; (393c <gpiote_event_handler+0x12c>)
    3926:	4620      	mov	r0, r4
    3928:	f7ff fda8 	bl	347c <cfg_level_pins>
		cfg_level_pins(DEVICE_DT_GET(GPIO(1)));
    392c:	f104 0018 	add.w	r0, r4, #24
    3930:	f7ff fda4 	bl	347c <cfg_level_pins>
}
    3934:	e7c0      	b.n	38b8 <gpiote_event_handler+0xa8>
    3936:	bf00      	nop
    3938:	4000617c 	.word	0x4000617c
    393c:	000081b4 	.word	0x000081b4
    3940:	40006000 	.word	0x40006000
    3944:	20000560 	.word	0x20000560
    3948:	2000057c 	.word	0x2000057c
    394c:	000081cc 	.word	0x000081cc

00003950 <i2c_nrfx_twi_transfer>:
}

static int i2c_nrfx_twi_transfer(const struct device *dev,
				 struct i2c_msg *msgs,
				 uint8_t num_msgs, uint16_t addr)
{
    3950:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
    3954:	b086      	sub	sp, #24
    3956:	4607      	mov	r7, r0
    3958:	4688      	mov	r8, r1
    395a:	4691      	mov	r9, r2
    395c:	469a      	mov	sl, r3
	return dev->data;
    395e:	6900      	ldr	r0, [r0, #16]
	return z_impl_k_sem_take(sem, timeout);
    3960:	f04f 32ff 	mov.w	r2, #4294967295
    3964:	f04f 33ff 	mov.w	r3, #4294967295
    3968:	f001 ffaa 	bl	58c0 <z_impl_k_sem_take>
    396c:	6938      	ldr	r0, [r7, #16]
	int ret = 0;

	k_sem_take(&(get_dev_data(dev)->transfer_sync), K_FOREVER);

	/* Dummy take on completion_sync sem to be sure that it is empty */
	k_sem_take(&(get_dev_data(dev)->completion_sync), K_NO_WAIT);
    396e:	3010      	adds	r0, #16
    3970:	2200      	movs	r2, #0
    3972:	2300      	movs	r3, #0
    3974:	f001 ffa4 	bl	58c0 <z_impl_k_sem_take>

	nrfx_twi_enable(&get_dev_config(dev)->twi);
    3978:	6878      	ldr	r0, [r7, #4]
    397a:	f001 fa1d 	bl	4db8 <nrfx_twi_enable>

	for (size_t i = 0; i < num_msgs; i++) {
    397e:	2400      	movs	r4, #0
	int ret = 0;
    3980:	4625      	mov	r5, r4
	for (size_t i = 0; i < num_msgs; i++) {
    3982:	e01b      	b.n	39bc <i2c_nrfx_twi_transfer+0x6c>
			/* - otherwise, just finish the transfer without
			 *   generating the STOP condition, unless the current
			 *   message is an RX request, for which such feature
			 *   is not supported
			 */
			} else if (msgs[i].flags & I2C_MSG_READ) {
    3984:	f013 0f01 	tst.w	r3, #1
    3988:	f040 808b 	bne.w	3aa2 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0xa>
				ret = -ENOTSUP;
				break;
			} else {
				xfer_flags |= NRFX_TWI_FLAG_TX_NO_STOP;
    398c:	2220      	movs	r2, #32
			}
		}

		res = nrfx_twi_xfer(&get_dev_config(dev)->twi,
    398e:	a901      	add	r1, sp, #4
    3990:	6878      	ldr	r0, [r7, #4]
    3992:	f001 fa41 	bl	4e18 <nrfx_twi_xfer>
				    &cur_xfer,
				    xfer_flags);
		if (res != NRFX_SUCCESS) {
    3996:	4b44      	ldr	r3, [pc, #272]	; (3aa8 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x10>)
    3998:	4298      	cmp	r0, r3
    399a:	d13d      	bne.n	3a18 <i2c_nrfx_twi_transfer+0xc8>
	return dev->data;
    399c:	6938      	ldr	r0, [r7, #16]
				ret = -EIO;
				break;
			}
		}

		ret = k_sem_take(&(get_dev_data(dev)->completion_sync),
    399e:	3010      	adds	r0, #16
    39a0:	f44f 4280 	mov.w	r2, #16384	; 0x4000
    39a4:	2300      	movs	r3, #0
    39a6:	f001 ff8b 	bl	58c0 <z_impl_k_sem_take>
				 I2C_TRANSFER_TIMEOUT_MSEC);
		if (ret != 0) {
    39aa:	4605      	mov	r5, r0
    39ac:	2800      	cmp	r0, #0
    39ae:	d13c      	bne.n	3a2a <i2c_nrfx_twi_transfer+0xda>
	return dev->data;
    39b0:	693b      	ldr	r3, [r7, #16]
					     get_dev_config(dev)->config.sda);
			ret = -EIO;
			break;
		}

		res = get_dev_data(dev)->res;
    39b2:	6a19      	ldr	r1, [r3, #32]
		if (res != NRFX_SUCCESS) {
    39b4:	4b3c      	ldr	r3, [pc, #240]	; (3aa8 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x10>)
    39b6:	4299      	cmp	r1, r3
    39b8:	d153      	bne.n	3a62 <i2c_nrfx_twi_transfer+0x112>
	for (size_t i = 0; i < num_msgs; i++) {
    39ba:	3401      	adds	r4, #1
    39bc:	454c      	cmp	r4, r9
    39be:	d266      	bcs.n	3a8e <i2c_nrfx_twi_transfer+0x13e>
		if (I2C_MSG_ADDR_10_BITS & msgs[i].flags) {
    39c0:	eb04 0244 	add.w	r2, r4, r4, lsl #1
    39c4:	eb08 0582 	add.w	r5, r8, r2, lsl #2
    39c8:	7a2b      	ldrb	r3, [r5, #8]
    39ca:	f013 0f08 	tst.w	r3, #8
    39ce:	d15c      	bne.n	3a8a <i2c_nrfx_twi_transfer+0x13a>
		nrfx_twi_xfer_desc_t cur_xfer = {
    39d0:	2600      	movs	r6, #0
    39d2:	9601      	str	r6, [sp, #4]
    39d4:	9603      	str	r6, [sp, #12]
    39d6:	9605      	str	r6, [sp, #20]
			.type		= (msgs[i].flags & I2C_MSG_READ) ?
    39d8:	7a2b      	ldrb	r3, [r5, #8]
					  NRFX_TWI_XFER_RX : NRFX_TWI_XFER_TX
    39da:	f003 0101 	and.w	r1, r3, #1
		nrfx_twi_xfer_desc_t cur_xfer = {
    39de:	f88d 1004 	strb.w	r1, [sp, #4]
    39e2:	f88d a005 	strb.w	sl, [sp, #5]
			.primary_length = msgs[i].len,
    39e6:	6869      	ldr	r1, [r5, #4]
		nrfx_twi_xfer_desc_t cur_xfer = {
    39e8:	9102      	str	r1, [sp, #8]
			.p_primary_buf  = msgs[i].buf,
    39ea:	f858 2022 	ldr.w	r2, [r8, r2, lsl #2]
		nrfx_twi_xfer_desc_t cur_xfer = {
    39ee:	9204      	str	r2, [sp, #16]
		if (!(msgs[i].flags & I2C_MSG_STOP)) {
    39f0:	f013 0f02 	tst.w	r3, #2
    39f4:	d10e      	bne.n	3a14 <i2c_nrfx_twi_transfer+0xc4>
			if ((i < (num_msgs - 1)) &&
    39f6:	f109 32ff 	add.w	r2, r9, #4294967295
    39fa:	42a2      	cmp	r2, r4
    39fc:	d9c2      	bls.n	3984 <i2c_nrfx_twi_transfer+0x34>
			    !(msgs[i + 1].flags & I2C_MSG_RESTART)) {
    39fe:	1c62      	adds	r2, r4, #1
    3a00:	eb02 0242 	add.w	r2, r2, r2, lsl #1
    3a04:	eb08 0282 	add.w	r2, r8, r2, lsl #2
    3a08:	7a12      	ldrb	r2, [r2, #8]
			if ((i < (num_msgs - 1)) &&
    3a0a:	f012 0f04 	tst.w	r2, #4
    3a0e:	d1b9      	bne.n	3984 <i2c_nrfx_twi_transfer+0x34>
				xfer_flags |= NRFX_TWI_FLAG_SUSPEND;
    3a10:	2240      	movs	r2, #64	; 0x40
    3a12:	e7bc      	b.n	398e <i2c_nrfx_twi_transfer+0x3e>
		uint32_t xfer_flags = 0;
    3a14:	2200      	movs	r2, #0
    3a16:	e7ba      	b.n	398e <i2c_nrfx_twi_transfer+0x3e>
			if (res == NRFX_ERROR_BUSY) {
    3a18:	330b      	adds	r3, #11
    3a1a:	4298      	cmp	r0, r3
    3a1c:	d002      	beq.n	3a24 <i2c_nrfx_twi_transfer+0xd4>
				ret = -EIO;
    3a1e:	f06f 0504 	mvn.w	r5, #4
    3a22:	e034      	b.n	3a8e <i2c_nrfx_twi_transfer+0x13e>
				ret = -EBUSY;
    3a24:	f06f 050f 	mvn.w	r5, #15
    3a28:	e031      	b.n	3a8e <i2c_nrfx_twi_transfer+0x13e>
    3a2a:	4b20      	ldr	r3, [pc, #128]	; (3aac <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x14>)
    3a2c:	4a20      	ldr	r2, [pc, #128]	; (3ab0 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x18>)
    3a2e:	1a9b      	subs	r3, r3, r2
    3a30:	08db      	lsrs	r3, r3, #3
			LOG_ERR("Error on I2C line occurred for message %d", i);
    3a32:	f04f 0200 	mov.w	r2, #0
    3a36:	2101      	movs	r1, #1
    3a38:	f361 0202 	bfi	r2, r1, #0, #3
    3a3c:	f36f 02c5 	bfc	r2, #3, #3
    3a40:	f363 128f 	bfi	r2, r3, #6, #10
    3a44:	4621      	mov	r1, r4
    3a46:	481b      	ldr	r0, [pc, #108]	; (3ab4 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x1c>)
    3a48:	f7fd fe50 	bl	16ec <log_1>
			nrfx_twi_disable(&get_dev_config(dev)->twi);
    3a4c:	6878      	ldr	r0, [r7, #4]
    3a4e:	f001 f9c3 	bl	4dd8 <nrfx_twi_disable>
	return dev->config;
    3a52:	687b      	ldr	r3, [r7, #4]
NRFX_STATIC_INLINE nrfx_err_t nrfx_twi_bus_recover(uint32_t scl_pin, uint32_t sda_pin);

#ifndef NRFX_DECLARE_ONLY
NRFX_STATIC_INLINE nrfx_err_t nrfx_twi_bus_recover(uint32_t scl_pin, uint32_t sda_pin)
{
    return nrfx_twi_twim_bus_recover(scl_pin, sda_pin);
    3a54:	68d9      	ldr	r1, [r3, #12]
    3a56:	6898      	ldr	r0, [r3, #8]
    3a58:	f001 f9f8 	bl	4e4c <nrfx_twi_twim_bus_recover>
			ret = -EIO;
    3a5c:	f06f 0504 	mvn.w	r5, #4
			break;
    3a60:	e015      	b.n	3a8e <i2c_nrfx_twi_transfer+0x13e>
    3a62:	4a12      	ldr	r2, [pc, #72]	; (3aac <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x14>)
    3a64:	4b12      	ldr	r3, [pc, #72]	; (3ab0 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x18>)
    3a66:	1ad2      	subs	r2, r2, r3
    3a68:	08d2      	lsrs	r2, r2, #3
			LOG_ERR("Error 0x%08X occurred for message %d", res, i);
    3a6a:	f04f 0300 	mov.w	r3, #0
    3a6e:	2001      	movs	r0, #1
    3a70:	f360 0302 	bfi	r3, r0, #0, #3
    3a74:	f36f 03c5 	bfc	r3, #3, #3
    3a78:	f362 138f 	bfi	r3, r2, #6, #10
    3a7c:	4622      	mov	r2, r4
    3a7e:	480e      	ldr	r0, [pc, #56]	; (3ab8 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x20>)
    3a80:	f7fd fe6a 	bl	1758 <log_2>
			ret = -EIO;
    3a84:	f06f 0504 	mvn.w	r5, #4
			break;
    3a88:	e001      	b.n	3a8e <i2c_nrfx_twi_transfer+0x13e>
			ret = -ENOTSUP;
    3a8a:	f06f 0585 	mvn.w	r5, #133	; 0x85
		}
	}

	nrfx_twi_disable(&get_dev_config(dev)->twi);
    3a8e:	6878      	ldr	r0, [r7, #4]
    3a90:	f001 f9a2 	bl	4dd8 <nrfx_twi_disable>
	return dev->data;
    3a94:	6938      	ldr	r0, [r7, #16]
	z_impl_k_sem_give(sem);
    3a96:	f001 feef 	bl	5878 <z_impl_k_sem_give>
	k_sem_give(&(get_dev_data(dev)->transfer_sync));

	return ret;
}
    3a9a:	4628      	mov	r0, r5
    3a9c:	b006      	add	sp, #24
    3a9e:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
				ret = -ENOTSUP;
    3aa2:	f06f 0585 	mvn.w	r5, #133	; 0x85
    3aa6:	e7f2      	b.n	3a8e <i2c_nrfx_twi_transfer+0x13e>
    3aa8:	0bad0000 	.word	0x0bad0000
    3aac:	000083bc 	.word	0x000083bc
    3ab0:	0000839c 	.word	0x0000839c
    3ab4:	00008c20 	.word	0x00008c20
    3ab8:	00008c4c 	.word	0x00008c4c

00003abc <event_handler>:

static void event_handler(nrfx_twi_evt_t const *p_event, void *p_context)
{
    3abc:	b508      	push	{r3, lr}
	struct i2c_nrfx_twi_data *dev_data = p_context;

	switch (p_event->type) {
    3abe:	7803      	ldrb	r3, [r0, #0]
    3ac0:	2b01      	cmp	r3, #1
    3ac2:	d00c      	beq.n	3ade <event_handler+0x22>
    3ac4:	2b02      	cmp	r3, #2
    3ac6:	d00d      	beq.n	3ae4 <event_handler+0x28>
    3ac8:	b113      	cbz	r3, 3ad0 <event_handler+0x14>
		break;
	case NRFX_TWI_EVT_DATA_NACK:
		dev_data->res = NRFX_ERROR_DRV_TWI_ERR_DNACK;
		break;
	default:
		dev_data->res = NRFX_ERROR_INTERNAL;
    3aca:	4b08      	ldr	r3, [pc, #32]	; (3aec <event_handler+0x30>)
    3acc:	620b      	str	r3, [r1, #32]
		break;
    3ace:	e001      	b.n	3ad4 <event_handler+0x18>
		dev_data->res = NRFX_SUCCESS;
    3ad0:	4b07      	ldr	r3, [pc, #28]	; (3af0 <event_handler+0x34>)
    3ad2:	620b      	str	r3, [r1, #32]
	}

	k_sem_give(&dev_data->completion_sync);
    3ad4:	f101 0010 	add.w	r0, r1, #16
    3ad8:	f001 fece 	bl	5878 <z_impl_k_sem_give>
}
    3adc:	bd08      	pop	{r3, pc}
		dev_data->res = NRFX_ERROR_DRV_TWI_ERR_ANACK;
    3ade:	4b05      	ldr	r3, [pc, #20]	; (3af4 <event_handler+0x38>)
    3ae0:	620b      	str	r3, [r1, #32]
		break;
    3ae2:	e7f7      	b.n	3ad4 <event_handler+0x18>
		dev_data->res = NRFX_ERROR_DRV_TWI_ERR_DNACK;
    3ae4:	4b04      	ldr	r3, [pc, #16]	; (3af8 <event_handler+0x3c>)
    3ae6:	620b      	str	r3, [r1, #32]
		break;
    3ae8:	e7f4      	b.n	3ad4 <event_handler+0x18>
    3aea:	bf00      	nop
    3aec:	0bad0001 	.word	0x0bad0001
    3af0:	0bad0000 	.word	0x0bad0000
    3af4:	0bae0001 	.word	0x0bae0001
    3af8:	0bae0002 	.word	0x0bae0002

00003afc <i2c_nrfx_twi_configure>:
	return dev->config;
    3afc:	6842      	ldr	r2, [r0, #4]
static int i2c_nrfx_twi_configure(const struct device *dev,
				  uint32_t dev_config)
{
	nrfx_twi_t const *inst = &(get_dev_config(dev)->twi);

	if (I2C_ADDR_10_BITS & dev_config) {
    3afe:	f011 0f01 	tst.w	r1, #1
    3b02:	d128      	bne.n	3b56 <i2c_nrfx_twi_configure+0x5a>
{
    3b04:	b508      	push	{r3, lr}
		return -EINVAL;
	}

	switch (I2C_SPEED_GET(dev_config)) {
    3b06:	f3c1 0342 	ubfx	r3, r1, #1, #3
    3b0a:	2b01      	cmp	r3, #1
    3b0c:	d014      	beq.n	3b38 <i2c_nrfx_twi_configure+0x3c>
    3b0e:	2b02      	cmp	r3, #2
    3b10:	d01b      	beq.n	3b4a <i2c_nrfx_twi_configure+0x4e>
    3b12:	4b12      	ldr	r3, [pc, #72]	; (3b5c <i2c_nrfx_twi_configure+0x60>)
    3b14:	4a12      	ldr	r2, [pc, #72]	; (3b60 <i2c_nrfx_twi_configure+0x64>)
    3b16:	1a9b      	subs	r3, r3, r2
    3b18:	08db      	lsrs	r3, r3, #3
		break;
	case I2C_SPEED_FAST:
		nrf_twi_frequency_set(inst->p_twi, NRF_TWI_FREQ_400K);
		break;
	default:
		LOG_ERR("unsupported speed");
    3b1a:	f04f 0100 	mov.w	r1, #0
    3b1e:	2201      	movs	r2, #1
    3b20:	f362 0102 	bfi	r1, r2, #0, #3
    3b24:	f36f 01c5 	bfc	r1, #3, #3
    3b28:	f363 118f 	bfi	r1, r3, #6, #10
    3b2c:	480d      	ldr	r0, [pc, #52]	; (3b64 <i2c_nrfx_twi_configure+0x68>)
    3b2e:	f7fd fe4f 	bl	17d0 <log_0>
		return -EINVAL;
    3b32:	f06f 0015 	mvn.w	r0, #21
    3b36:	e007      	b.n	3b48 <i2c_nrfx_twi_configure+0x4c>
		nrf_twi_frequency_set(inst->p_twi, NRF_TWI_FREQ_100K);
    3b38:	6813      	ldr	r3, [r2, #0]
}

NRF_STATIC_INLINE void nrf_twi_frequency_set(NRF_TWI_Type *      p_reg,
                                             nrf_twi_frequency_t frequency)
{
    p_reg->FREQUENCY = frequency;
    3b3a:	f04f 72cc 	mov.w	r2, #26738688	; 0x1980000
    3b3e:	f8c3 2524 	str.w	r2, [r3, #1316]	; 0x524
	return dev->data;
    3b42:	6903      	ldr	r3, [r0, #16]
	}
	get_dev_data(dev)->dev_config = dev_config;
    3b44:	6259      	str	r1, [r3, #36]	; 0x24

	return 0;
    3b46:	2000      	movs	r0, #0
}
    3b48:	bd08      	pop	{r3, pc}
		nrf_twi_frequency_set(inst->p_twi, NRF_TWI_FREQ_400K);
    3b4a:	6813      	ldr	r3, [r2, #0]
    3b4c:	f04f 62cd 	mov.w	r2, #107479040	; 0x6680000
    3b50:	f8c3 2524 	str.w	r2, [r3, #1316]	; 0x524
}
    3b54:	e7f5      	b.n	3b42 <i2c_nrfx_twi_configure+0x46>
		return -EINVAL;
    3b56:	f06f 0015 	mvn.w	r0, #21
}
    3b5a:	4770      	bx	lr
    3b5c:	000083bc 	.word	0x000083bc
    3b60:	0000839c 	.word	0x0000839c
    3b64:	00008c74 	.word	0x00008c74

00003b68 <init_twi>:
	.configure = i2c_nrfx_twi_configure,
	.transfer  = i2c_nrfx_twi_transfer,
};

static int init_twi(const struct device *dev)
{
    3b68:	b510      	push	{r4, lr}
    3b6a:	4604      	mov	r4, r0
	return dev->config;
    3b6c:	6840      	ldr	r0, [r0, #4]
	struct i2c_nrfx_twi_data *dev_data = get_dev_data(dev);
	nrfx_err_t result = nrfx_twi_init(&get_dev_config(dev)->twi,
    3b6e:	6923      	ldr	r3, [r4, #16]
    3b70:	4a0e      	ldr	r2, [pc, #56]	; (3bac <init_twi+0x44>)
    3b72:	f100 0108 	add.w	r1, r0, #8
    3b76:	f001 f8bd 	bl	4cf4 <nrfx_twi_init>
					  &get_dev_config(dev)->config,
					  event_handler, dev_data);
	if (result != NRFX_SUCCESS) {
    3b7a:	4b0d      	ldr	r3, [pc, #52]	; (3bb0 <init_twi+0x48>)
    3b7c:	4298      	cmp	r0, r3
    3b7e:	d101      	bne.n	3b84 <init_twi+0x1c>
		LOG_ERR("Failed to initialize device: %s",
			    dev->name);
		return -EBUSY;
	}

	return 0;
    3b80:	2000      	movs	r0, #0
}
    3b82:	bd10      	pop	{r4, pc}
    3b84:	4b0b      	ldr	r3, [pc, #44]	; (3bb4 <init_twi+0x4c>)
    3b86:	4a0c      	ldr	r2, [pc, #48]	; (3bb8 <init_twi+0x50>)
    3b88:	1a9b      	subs	r3, r3, r2
    3b8a:	08db      	lsrs	r3, r3, #3
		LOG_ERR("Failed to initialize device: %s",
    3b8c:	f04f 0200 	mov.w	r2, #0
    3b90:	2101      	movs	r1, #1
    3b92:	f361 0202 	bfi	r2, r1, #0, #3
    3b96:	f36f 02c5 	bfc	r2, #3, #3
    3b9a:	f363 128f 	bfi	r2, r3, #6, #10
    3b9e:	6821      	ldr	r1, [r4, #0]
    3ba0:	4806      	ldr	r0, [pc, #24]	; (3bbc <init_twi+0x54>)
    3ba2:	f7fd fda3 	bl	16ec <log_1>
		return -EBUSY;
    3ba6:	f06f 000f 	mvn.w	r0, #15
    3baa:	e7ea      	b.n	3b82 <init_twi+0x1a>
    3bac:	00003abd 	.word	0x00003abd
    3bb0:	0bad0000 	.word	0x0bad0000
    3bb4:	000083bc 	.word	0x000083bc
    3bb8:	0000839c 	.word	0x0000839c
    3bbc:	00008c88 	.word	0x00008c88

00003bc0 <hfclk_on_callback>:
    return (uint32_t)((uint8_t *)p_reg + (uint32_t)task);
}

NRF_STATIC_INLINE void nrf_temp_task_trigger(NRF_TEMP_Type * p_reg, nrf_temp_task_t task)
{
    *(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task) = 1;
    3bc0:	4b01      	ldr	r3, [pc, #4]	; (3bc8 <hfclk_on_callback+0x8>)
    3bc2:	2201      	movs	r2, #1
    3bc4:	601a      	str	r2, [r3, #0]
			      struct onoff_client *cli,
			      uint32_t state,
			      int res)
{
	nrf_temp_task_trigger(NRF_TEMP, NRF_TEMP_TASK_START);
}
    3bc6:	4770      	bx	lr
    3bc8:	4000c000 	.word	0x4000c000

00003bcc <temp_nrf5_channel_get>:

static int temp_nrf5_channel_get(const struct device *dev,
				 enum sensor_channel chan,
				 struct sensor_value *val)
{
	struct temp_nrf5_data *data = dev->data;
    3bcc:	6903      	ldr	r3, [r0, #16]
	int32_t uval;


	if (chan != SENSOR_CHAN_DIE_TEMP) {
    3bce:	290c      	cmp	r1, #12
    3bd0:	d110      	bne.n	3bf4 <temp_nrf5_channel_get+0x28>
		return -ENOTSUP;
	}

	uval = data->sample * TEMP_NRF5_TEMP_SCALE;
    3bd2:	6a59      	ldr	r1, [r3, #36]	; 0x24
    3bd4:	4b09      	ldr	r3, [pc, #36]	; (3bfc <temp_nrf5_channel_get+0x30>)
    3bd6:	fb03 f101 	mul.w	r1, r3, r1
	val->val1 = uval / 1000000;
    3bda:	4809      	ldr	r0, [pc, #36]	; (3c00 <temp_nrf5_channel_get+0x34>)
    3bdc:	fb80 3001 	smull	r3, r0, r0, r1
    3be0:	17cb      	asrs	r3, r1, #31
    3be2:	ebc3 43a0 	rsb	r3, r3, r0, asr #18
    3be6:	6013      	str	r3, [r2, #0]
	val->val2 = uval % 1000000;
    3be8:	4806      	ldr	r0, [pc, #24]	; (3c04 <temp_nrf5_channel_get+0x38>)
    3bea:	fb00 1313 	mls	r3, r0, r3, r1
    3bee:	6053      	str	r3, [r2, #4]

	LOG_DBG("Temperature:%d,%d", val->val1, val->val2);

	return 0;
    3bf0:	2000      	movs	r0, #0
    3bf2:	4770      	bx	lr
		return -ENOTSUP;
    3bf4:	f06f 0085 	mvn.w	r0, #133	; 0x85
}
    3bf8:	4770      	bx	lr
    3bfa:	bf00      	nop
    3bfc:	0003d090 	.word	0x0003d090
    3c00:	431bde83 	.word	0x431bde83
    3c04:	000f4240 	.word	0x000f4240

00003c08 <temp_nrf5_sample_fetch>:
{
    3c08:	e92d 4370 	stmdb	sp!, {r4, r5, r6, r8, r9, lr}
    3c0c:	b084      	sub	sp, #16
	struct temp_nrf5_data *data = dev->data;
    3c0e:	6904      	ldr	r4, [r0, #16]
	if (data->clk_mgr == NULL) {
    3c10:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    3c12:	b373      	cbz	r3, 3c72 <temp_nrf5_sample_fetch+0x6a>
	if (chan != SENSOR_CHAN_ALL && chan != SENSOR_CHAN_DIE_TEMP) {
    3c14:	2939      	cmp	r1, #57	; 0x39
    3c16:	d001      	beq.n	3c1c <temp_nrf5_sample_fetch+0x14>
    3c18:	290c      	cmp	r1, #12
    3c1a:	d12d      	bne.n	3c78 <temp_nrf5_sample_fetch+0x70>
	k_mutex_lock(&data->mutex, K_FOREVER);
    3c1c:	f104 0610 	add.w	r6, r4, #16
    3c20:	f04f 38ff 	mov.w	r8, #4294967295
    3c24:	f04f 39ff 	mov.w	r9, #4294967295
	return z_impl_k_mutex_lock(mutex, timeout);
    3c28:	4642      	mov	r2, r8
    3c2a:	464b      	mov	r3, r9
    3c2c:	4630      	mov	r0, r6
    3c2e:	f001 fd55 	bl	56dc <z_impl_k_mutex_lock>
					      sys_notify_generic_callback handler)
{
	__ASSERT_NO_MSG(notify != NULL);
	__ASSERT_NO_MSG(handler != NULL);

	*notify = (struct sys_notify){
    3c32:	2500      	movs	r5, #0
    3c34:	9503      	str	r5, [sp, #12]
    3c36:	4b12      	ldr	r3, [pc, #72]	; (3c80 <temp_nrf5_sample_fetch+0x78>)
    3c38:	9301      	str	r3, [sp, #4]
    3c3a:	2303      	movs	r3, #3
    3c3c:	9302      	str	r3, [sp, #8]
	r = onoff_request(data->clk_mgr, &cli);
    3c3e:	4669      	mov	r1, sp
    3c40:	6aa0      	ldr	r0, [r4, #40]	; 0x28
    3c42:	f002 ff8e 	bl	6b62 <onoff_request>
	return z_impl_k_sem_take(sem, timeout);
    3c46:	4642      	mov	r2, r8
    3c48:	464b      	mov	r3, r9
    3c4a:	4620      	mov	r0, r4
    3c4c:	f001 fe38 	bl	58c0 <z_impl_k_sem_take>
	r = onoff_release(data->clk_mgr);
    3c50:	6aa0      	ldr	r0, [r4, #40]	; 0x28
    3c52:	f002 ffe2 	bl	6c1a <onoff_release>
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
}

NRF_STATIC_INLINE int32_t nrf_temp_result_get(NRF_TEMP_Type const * p_reg)
{
    int32_t raw_measurement = p_reg->TEMP;
    3c56:	4b0b      	ldr	r3, [pc, #44]	; (3c84 <temp_nrf5_sample_fetch+0x7c>)
    3c58:	f8d3 3508 	ldr.w	r3, [r3, #1288]	; 0x508
	data->sample = nrf_temp_result_get(NRF_TEMP);
    3c5c:	6263      	str	r3, [r4, #36]	; 0x24
    *(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task) = 1;
    3c5e:	4b0a      	ldr	r3, [pc, #40]	; (3c88 <temp_nrf5_sample_fetch+0x80>)
    3c60:	2201      	movs	r2, #1
    3c62:	601a      	str	r2, [r3, #0]
	return z_impl_k_mutex_unlock(mutex);
    3c64:	4630      	mov	r0, r6
    3c66:	f001 fdc3 	bl	57f0 <z_impl_k_mutex_unlock>
	return 0;
    3c6a:	4628      	mov	r0, r5
}
    3c6c:	b004      	add	sp, #16
    3c6e:	e8bd 8370 	ldmia.w	sp!, {r4, r5, r6, r8, r9, pc}
		return -EAGAIN;
    3c72:	f06f 000a 	mvn.w	r0, #10
    3c76:	e7f9      	b.n	3c6c <temp_nrf5_sample_fetch+0x64>
		return -ENOTSUP;
    3c78:	f06f 0085 	mvn.w	r0, #133	; 0x85
    3c7c:	e7f6      	b.n	3c6c <temp_nrf5_sample_fetch+0x64>
    3c7e:	bf00      	nop
    3c80:	00003bc1 	.word	0x00003bc1
    3c84:	4000c000 	.word	0x4000c000
    3c88:	4000c004 	.word	0x4000c004

00003c8c <temp_nrf5_init>:
	.sample_fetch = temp_nrf5_sample_fetch,
	.channel_get = temp_nrf5_channel_get,
};

static int temp_nrf5_init(const struct device *dev)
{
    3c8c:	b510      	push	{r4, lr}
	struct temp_nrf5_data *data = dev->data;
    3c8e:	6904      	ldr	r4, [r0, #16]

	LOG_DBG("");

	/* A null clk_mgr indicates sensor has not been initialized */
	data->clk_mgr =
		z_nrf_clock_control_get_onoff(CLOCK_CONTROL_NRF_SUBSYS_HF);
    3c90:	2000      	movs	r0, #0
    3c92:	f7ff fa21 	bl	30d8 <z_nrf_clock_control_get_onoff>
	data->clk_mgr =
    3c96:	62a0      	str	r0, [r4, #40]	; 0x28
	return z_impl_k_sem_init(sem, initial_count, limit);
    3c98:	f04f 32ff 	mov.w	r2, #4294967295
    3c9c:	2100      	movs	r1, #0
    3c9e:	4620      	mov	r0, r4
    3ca0:	f003 ff9b 	bl	7bda <z_impl_k_sem_init>
	__ASSERT_NO_MSG(data->clk_mgr);

	k_sem_init(&data->device_sync_sem, 0, K_SEM_MAX_LIMIT);
	k_mutex_init(&data->mutex);
    3ca4:	f104 0010 	add.w	r0, r4, #16
	return z_impl_k_mutex_init(mutex);
    3ca8:	f003 ff90 	bl	7bcc <z_impl_k_mutex_init>

	IRQ_CONNECT(
    3cac:	2200      	movs	r2, #0
    3cae:	2101      	movs	r1, #1
    3cb0:	200c      	movs	r0, #12
    3cb2:	f7fe faab 	bl	220c <z_arm_irq_priority_set>
		DT_INST_IRQN(0),
		DT_INST_IRQ(0, priority),
		temp_nrf5_isr,
		DEVICE_DT_INST_GET(0),
		0);
	irq_enable(DT_INST_IRQN(0));
    3cb6:	200c      	movs	r0, #12
    3cb8:	f7fe fa8a 	bl	21d0 <arch_irq_enable>
    p_reg->INTENSET = mask;
    3cbc:	4b02      	ldr	r3, [pc, #8]	; (3cc8 <temp_nrf5_init+0x3c>)
    3cbe:	2201      	movs	r2, #1
    3cc0:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304

	nrf_temp_int_enable(NRF_TEMP, NRF_TEMP_INT_DATARDY_MASK);

	return 0;
}
    3cc4:	2000      	movs	r0, #0
    3cc6:	bd10      	pop	{r4, pc}
    3cc8:	4000c000 	.word	0x4000c000

00003ccc <temp_nrf5_isr>:
{
    3ccc:	b508      	push	{r3, lr}
	struct temp_nrf5_data *data = dev->data;
    3cce:	6900      	ldr	r0, [r0, #16]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    3cd0:	4b03      	ldr	r3, [pc, #12]	; (3ce0 <temp_nrf5_isr+0x14>)
    3cd2:	2200      	movs	r2, #0
    3cd4:	601a      	str	r2, [r3, #0]
    3cd6:	681b      	ldr	r3, [r3, #0]
	z_impl_k_sem_give(sem);
    3cd8:	f001 fdce 	bl	5878 <z_impl_k_sem_give>
}
    3cdc:	bd08      	pop	{r3, pc}
    3cde:	bf00      	nop
    3ce0:	4000c100 	.word	0x4000c100

00003ce4 <event_txdrdy_check>:
    nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}

NRF_STATIC_INLINE bool nrf_uart_event_check(NRF_UART_Type const * p_reg, nrf_uart_event_t event)
{
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    3ce4:	4b02      	ldr	r3, [pc, #8]	; (3cf0 <event_txdrdy_check+0xc>)
    3ce6:	6818      	ldr	r0, [r3, #0]
	return (nrf_uart_event_check(uart0_addr, NRF_UART_EVENT_TXDRDY)
#ifdef CONFIG_UART_0_INTERRUPT_DRIVEN
		|| uart_sw_event_txdrdy
#endif
	       );
}
    3ce8:	3800      	subs	r0, #0
    3cea:	bf18      	it	ne
    3cec:	2001      	movne	r0, #1
    3cee:	4770      	bx	lr
    3cf0:	4000211c 	.word	0x4000211c

00003cf4 <event_txdrdy_clear>:
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3cf4:	4b02      	ldr	r3, [pc, #8]	; (3d00 <event_txdrdy_clear+0xc>)
    3cf6:	2200      	movs	r2, #0
    3cf8:	601a      	str	r2, [r3, #0]
    3cfa:	681b      	ldr	r3, [r3, #0]
{
	nrf_uart_event_clear(uart0_addr, NRF_UART_EVENT_TXDRDY);
#ifdef CONFIG_UART_0_INTERRUPT_DRIVEN
	uart_sw_event_txdrdy = 0U;
#endif
}
    3cfc:	4770      	bx	lr
    3cfe:	bf00      	nop
    3d00:	4000211c 	.word	0x4000211c

00003d04 <baudrate_set>:

static int baudrate_set(const struct device *dev, uint32_t baudrate)
{
	nrf_uart_baudrate_t nrf_baudrate; /* calculated baudrate divisor */

	switch (baudrate) {
    3d04:	f5b1 4f16 	cmp.w	r1, #38400	; 0x9600
    3d08:	d06d      	beq.n	3de6 <baudrate_set+0xe2>
    3d0a:	d83b      	bhi.n	3d84 <baudrate_set+0x80>
    3d0c:	f5b1 5f16 	cmp.w	r1, #9600	; 0x2580
    3d10:	d06b      	beq.n	3dea <baudrate_set+0xe6>
    3d12:	d90a      	bls.n	3d2a <baudrate_set+0x26>
    3d14:	f5b1 4fe1 	cmp.w	r1, #28800	; 0x7080
    3d18:	d072      	beq.n	3e00 <baudrate_set+0xfc>
    3d1a:	d925      	bls.n	3d68 <baudrate_set+0x64>
    3d1c:	f647 2312 	movw	r3, #31250	; 0x7a12
    3d20:	4299      	cmp	r1, r3
    3d22:	d12c      	bne.n	3d7e <baudrate_set+0x7a>
		break;
	case 28800:
		nrf_baudrate = NRF_UART_BAUDRATE_28800;
		break;
	case 31250:
		nrf_baudrate = NRF_UART_BAUDRATE_31250;
    3d24:	f44f 0300 	mov.w	r3, #8388608	; 0x800000
    3d28:	e013      	b.n	3d52 <baudrate_set+0x4e>
	switch (baudrate) {
    3d2a:	f5b1 6f96 	cmp.w	r1, #1200	; 0x4b0
    3d2e:	d05e      	beq.n	3dee <baudrate_set+0xea>
    3d30:	d907      	bls.n	3d42 <baudrate_set+0x3e>
    3d32:	f5b1 6f16 	cmp.w	r1, #2400	; 0x960
    3d36:	d060      	beq.n	3dfa <baudrate_set+0xf6>
    3d38:	f5b1 5f96 	cmp.w	r1, #4800	; 0x12c0
    3d3c:	d111      	bne.n	3d62 <baudrate_set+0x5e>
		nrf_baudrate = NRF_UART_BAUDRATE_4800;
    3d3e:	4b3a      	ldr	r3, [pc, #232]	; (3e28 <baudrate_set+0x124>)
    3d40:	e007      	b.n	3d52 <baudrate_set+0x4e>
	switch (baudrate) {
    3d42:	f5b1 7f96 	cmp.w	r1, #300	; 0x12c
    3d46:	d055      	beq.n	3df4 <baudrate_set+0xf0>
    3d48:	f5b1 7f16 	cmp.w	r1, #600	; 0x258
    3d4c:	d106      	bne.n	3d5c <baudrate_set+0x58>
		nrf_baudrate = 0x00027000;
    3d4e:	f44f 331c 	mov.w	r3, #159744	; 0x27000
                    | (uint32_t)p_cfg->hwfc;
}

NRF_STATIC_INLINE void nrf_uart_baudrate_set(NRF_UART_Type * p_reg, nrf_uart_baudrate_t baudrate)
{
    p_reg->BAUDRATE = baudrate;
    3d52:	4a36      	ldr	r2, [pc, #216]	; (3e2c <baudrate_set+0x128>)
    3d54:	f8c2 3524 	str.w	r3, [r2, #1316]	; 0x524
		return -EINVAL;
	}

	nrf_uart_baudrate_set(uart0_addr, nrf_baudrate);

	return 0;
    3d58:	2000      	movs	r0, #0
    3d5a:	4770      	bx	lr
	switch (baudrate) {
    3d5c:	f06f 0015 	mvn.w	r0, #21
    3d60:	4770      	bx	lr
    3d62:	f06f 0015 	mvn.w	r0, #21
    3d66:	4770      	bx	lr
    3d68:	f5b1 5f61 	cmp.w	r1, #14400	; 0x3840
    3d6c:	d04a      	beq.n	3e04 <baudrate_set+0x100>
    3d6e:	f5b1 4f96 	cmp.w	r1, #19200	; 0x4b00
    3d72:	d101      	bne.n	3d78 <baudrate_set+0x74>
		nrf_baudrate = NRF_UART_BAUDRATE_19200;
    3d74:	4b2e      	ldr	r3, [pc, #184]	; (3e30 <baudrate_set+0x12c>)
    3d76:	e7ec      	b.n	3d52 <baudrate_set+0x4e>
	switch (baudrate) {
    3d78:	f06f 0015 	mvn.w	r0, #21
    3d7c:	4770      	bx	lr
    3d7e:	f06f 0015 	mvn.w	r0, #21
    3d82:	4770      	bx	lr
    3d84:	f5b1 3f61 	cmp.w	r1, #230400	; 0x38400
    3d88:	d03f      	beq.n	3e0a <baudrate_set+0x106>
    3d8a:	d909      	bls.n	3da0 <baudrate_set+0x9c>
    3d8c:	f5b1 2f61 	cmp.w	r1, #921600	; 0xe1000
    3d90:	d042      	beq.n	3e18 <baudrate_set+0x114>
    3d92:	d91d      	bls.n	3dd0 <baudrate_set+0xcc>
    3d94:	4b27      	ldr	r3, [pc, #156]	; (3e34 <baudrate_set+0x130>)
    3d96:	4299      	cmp	r1, r3
    3d98:	d143      	bne.n	3e22 <baudrate_set+0x11e>
		nrf_baudrate = NRF_UART_BAUDRATE_1000000;
    3d9a:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    3d9e:	e7d8      	b.n	3d52 <baudrate_set+0x4e>
	switch (baudrate) {
    3da0:	f5b1 3f96 	cmp.w	r1, #76800	; 0x12c00
    3da4:	d033      	beq.n	3e0e <baudrate_set+0x10a>
    3da6:	d904      	bls.n	3db2 <baudrate_set+0xae>
    3da8:	f5b1 3fe1 	cmp.w	r1, #115200	; 0x1c200
    3dac:	d10d      	bne.n	3dca <baudrate_set+0xc6>
		nrf_baudrate = NRF_UART_BAUDRATE_115200;
    3dae:	4b22      	ldr	r3, [pc, #136]	; (3e38 <baudrate_set+0x134>)
    3db0:	e7cf      	b.n	3d52 <baudrate_set+0x4e>
	switch (baudrate) {
    3db2:	f64d 23c0 	movw	r3, #56000	; 0xdac0
    3db6:	4299      	cmp	r1, r3
    3db8:	d02b      	beq.n	3e12 <baudrate_set+0x10e>
    3dba:	f5b1 4f61 	cmp.w	r1, #57600	; 0xe100
    3dbe:	d101      	bne.n	3dc4 <baudrate_set+0xc0>
		nrf_baudrate = NRF_UART_BAUDRATE_57600;
    3dc0:	4b1e      	ldr	r3, [pc, #120]	; (3e3c <baudrate_set+0x138>)
    3dc2:	e7c6      	b.n	3d52 <baudrate_set+0x4e>
	switch (baudrate) {
    3dc4:	f06f 0015 	mvn.w	r0, #21
    3dc8:	4770      	bx	lr
    3dca:	f06f 0015 	mvn.w	r0, #21
    3dce:	4770      	bx	lr
    3dd0:	4b1b      	ldr	r3, [pc, #108]	; (3e40 <baudrate_set+0x13c>)
    3dd2:	4299      	cmp	r1, r3
    3dd4:	d022      	beq.n	3e1c <baudrate_set+0x118>
    3dd6:	f5b1 2fe1 	cmp.w	r1, #460800	; 0x70800
    3dda:	d101      	bne.n	3de0 <baudrate_set+0xdc>
		nrf_baudrate = NRF_UART_BAUDRATE_460800;
    3ddc:	4b19      	ldr	r3, [pc, #100]	; (3e44 <baudrate_set+0x140>)
    3dde:	e7b8      	b.n	3d52 <baudrate_set+0x4e>
	switch (baudrate) {
    3de0:	f06f 0015 	mvn.w	r0, #21
    3de4:	4770      	bx	lr
		nrf_baudrate = NRF_UART_BAUDRATE_38400;
    3de6:	4b18      	ldr	r3, [pc, #96]	; (3e48 <baudrate_set+0x144>)
    3de8:	e7b3      	b.n	3d52 <baudrate_set+0x4e>
		nrf_baudrate = NRF_UART_BAUDRATE_9600;
    3dea:	4b18      	ldr	r3, [pc, #96]	; (3e4c <baudrate_set+0x148>)
    3dec:	e7b1      	b.n	3d52 <baudrate_set+0x4e>
		nrf_baudrate = NRF_UART_BAUDRATE_1200;
    3dee:	f44f 239e 	mov.w	r3, #323584	; 0x4f000
    3df2:	e7ae      	b.n	3d52 <baudrate_set+0x4e>
	switch (baudrate) {
    3df4:	f44f 33a0 	mov.w	r3, #81920	; 0x14000
    3df8:	e7ab      	b.n	3d52 <baudrate_set+0x4e>
		nrf_baudrate = NRF_UART_BAUDRATE_2400;
    3dfa:	f44f 231d 	mov.w	r3, #643072	; 0x9d000
    3dfe:	e7a8      	b.n	3d52 <baudrate_set+0x4e>
		nrf_baudrate = NRF_UART_BAUDRATE_28800;
    3e00:	4b13      	ldr	r3, [pc, #76]	; (3e50 <baudrate_set+0x14c>)
    3e02:	e7a6      	b.n	3d52 <baudrate_set+0x4e>
		nrf_baudrate = NRF_UART_BAUDRATE_14400;
    3e04:	f44f 136c 	mov.w	r3, #3866624	; 0x3b0000
    3e08:	e7a3      	b.n	3d52 <baudrate_set+0x4e>
		nrf_baudrate = NRF_UART_BAUDRATE_230400;
    3e0a:	4b12      	ldr	r3, [pc, #72]	; (3e54 <baudrate_set+0x150>)
    3e0c:	e7a1      	b.n	3d52 <baudrate_set+0x4e>
		nrf_baudrate = NRF_UART_BAUDRATE_76800;
    3e0e:	4b12      	ldr	r3, [pc, #72]	; (3e58 <baudrate_set+0x154>)
    3e10:	e79f      	b.n	3d52 <baudrate_set+0x4e>
		nrf_baudrate = NRF_UART_BAUDRATE_56000;
    3e12:	f44f 0365 	mov.w	r3, #15007744	; 0xe50000
    3e16:	e79c      	b.n	3d52 <baudrate_set+0x4e>
		nrf_baudrate = NRF_UART_BAUDRATE_921600;
    3e18:	4b10      	ldr	r3, [pc, #64]	; (3e5c <baudrate_set+0x158>)
    3e1a:	e79a      	b.n	3d52 <baudrate_set+0x4e>
		nrf_baudrate = NRF_UART_BAUDRATE_250000;
    3e1c:	f04f 6380 	mov.w	r3, #67108864	; 0x4000000
    3e20:	e797      	b.n	3d52 <baudrate_set+0x4e>
	switch (baudrate) {
    3e22:	f06f 0015 	mvn.w	r0, #21
}
    3e26:	4770      	bx	lr
    3e28:	0013b000 	.word	0x0013b000
    3e2c:	40002000 	.word	0x40002000
    3e30:	004ea000 	.word	0x004ea000
    3e34:	000f4240 	.word	0x000f4240
    3e38:	01d7e000 	.word	0x01d7e000
    3e3c:	00ebf000 	.word	0x00ebf000
    3e40:	0003d090 	.word	0x0003d090
    3e44:	075f7000 	.word	0x075f7000
    3e48:	009d5000 	.word	0x009d5000
    3e4c:	00275000 	.word	0x00275000
    3e50:	0075f000 	.word	0x0075f000
    3e54:	03afb000 	.word	0x03afb000
    3e58:	013a9000 	.word	0x013a9000
    3e5c:	0ebed000 	.word	0x0ebed000

00003e60 <uart_nrfx_poll_in>:
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    3e60:	4b07      	ldr	r3, [pc, #28]	; (3e80 <uart_nrfx_poll_in+0x20>)
    3e62:	681b      	ldr	r3, [r3, #0]
 * @return 0 if a character arrived, -1 if the input buffer if empty.
 */

static int uart_nrfx_poll_in(const struct device *dev, unsigned char *c)
{
	if (!nrf_uart_event_check(uart0_addr, NRF_UART_EVENT_RXDRDY)) {
    3e64:	b143      	cbz	r3, 3e78 <uart_nrfx_poll_in+0x18>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3e66:	4b06      	ldr	r3, [pc, #24]	; (3e80 <uart_nrfx_poll_in+0x20>)
    3e68:	2000      	movs	r0, #0
    3e6a:	6018      	str	r0, [r3, #0]
    3e6c:	681b      	ldr	r3, [r3, #0]
    return p_reg->RXD;
    3e6e:	4b05      	ldr	r3, [pc, #20]	; (3e84 <uart_nrfx_poll_in+0x24>)
    3e70:	f8d3 3518 	ldr.w	r3, [r3, #1304]	; 0x518

	/* Clear the interrupt */
	nrf_uart_event_clear(uart0_addr, NRF_UART_EVENT_RXDRDY);

	/* got a character */
	*c = nrf_uart_rxd_get(uart0_addr);
    3e74:	700b      	strb	r3, [r1, #0]

	return 0;
    3e76:	4770      	bx	lr
		return -1;
    3e78:	f04f 30ff 	mov.w	r0, #4294967295
}
    3e7c:	4770      	bx	lr
    3e7e:	bf00      	nop
    3e80:	40002108 	.word	0x40002108
    3e84:	40002000 	.word	0x40002000

00003e88 <uart_nrfx_err_check>:
    uint32_t errsrc_mask = p_reg->ERRORSRC;
    3e88:	4b02      	ldr	r3, [pc, #8]	; (3e94 <uart_nrfx_err_check+0xc>)
    3e8a:	f8d3 0480 	ldr.w	r0, [r3, #1152]	; 0x480
    p_reg->ERRORSRC = errsrc_mask;
    3e8e:	f8c3 0480 	str.w	r0, [r3, #1152]	; 0x480
/** Console I/O function */
static int uart_nrfx_err_check(const struct device *dev)
{
	/* register bitfields maps to the defines in uart.h */
	return nrf_uart_errorsrc_get_and_clear(uart0_addr);
}
    3e92:	4770      	bx	lr
    3e94:	40002000 	.word	0x40002000

00003e98 <uart_nrfx_configure>:

static int uart_nrfx_configure(const struct device *dev,
			       const struct uart_config *cfg)
{
    3e98:	b530      	push	{r4, r5, lr}
    3e9a:	b083      	sub	sp, #12
    3e9c:	4605      	mov	r5, r0
    3e9e:	460c      	mov	r4, r1
	nrf_uart_config_t uart_cfg;

#if defined(UART_CONFIG_STOP_Msk)
	switch (cfg->stop_bits) {
    3ea0:	794b      	ldrb	r3, [r1, #5]
    3ea2:	2b01      	cmp	r3, #1
    3ea4:	d006      	beq.n	3eb4 <uart_nrfx_configure+0x1c>
    3ea6:	2b03      	cmp	r3, #3
    3ea8:	d011      	beq.n	3ece <uart_nrfx_configure+0x36>
    3eaa:	f06f 0285 	mvn.w	r2, #133	; 0x85
	nrf_uart_configure(uart0_addr, &uart_cfg);

	get_dev_data(dev)->uart_config = *cfg;

	return 0;
}
    3eae:	4610      	mov	r0, r2
    3eb0:	b003      	add	sp, #12
    3eb2:	bd30      	pop	{r4, r5, pc}
		uart_cfg.stop = NRF_UART_STOP_ONE;
    3eb4:	2300      	movs	r3, #0
    3eb6:	f88d 3002 	strb.w	r3, [sp, #2]
	if (cfg->data_bits != UART_CFG_DATA_BITS_8) {
    3eba:	79a3      	ldrb	r3, [r4, #6]
    3ebc:	2b03      	cmp	r3, #3
    3ebe:	d145      	bne.n	3f4c <uart_nrfx_configure+0xb4>
	switch (cfg->flow_ctrl) {
    3ec0:	79e3      	ldrb	r3, [r4, #7]
    3ec2:	b143      	cbz	r3, 3ed6 <uart_nrfx_configure+0x3e>
    3ec4:	2b01      	cmp	r3, #1
    3ec6:	d015      	beq.n	3ef4 <uart_nrfx_configure+0x5c>
    3ec8:	f06f 0285 	mvn.w	r2, #133	; 0x85
    3ecc:	e7ef      	b.n	3eae <uart_nrfx_configure+0x16>
		uart_cfg.stop = NRF_UART_STOP_TWO;
    3ece:	2310      	movs	r3, #16
    3ed0:	f88d 3002 	strb.w	r3, [sp, #2]
		break;
    3ed4:	e7f1      	b.n	3eba <uart_nrfx_configure+0x22>
		uart_cfg.hwfc = NRF_UART_HWFC_DISABLED;
    3ed6:	2300      	movs	r3, #0
    3ed8:	f88d 3000 	strb.w	r3, [sp]
	uart_cfg.paritytype = NRF_UART_PARITYTYPE_EVEN;
    3edc:	2300      	movs	r3, #0
    3ede:	f8ad 3004 	strh.w	r3, [sp, #4]
	switch (cfg->parity) {
    3ee2:	7923      	ldrb	r3, [r4, #4]
    3ee4:	2b01      	cmp	r3, #1
    3ee6:	d029      	beq.n	3f3c <uart_nrfx_configure+0xa4>
    3ee8:	2b02      	cmp	r3, #2
    3eea:	d023      	beq.n	3f34 <uart_nrfx_configure+0x9c>
    3eec:	b133      	cbz	r3, 3efc <uart_nrfx_configure+0x64>
    3eee:	f06f 0285 	mvn.w	r2, #133	; 0x85
    3ef2:	e7dc      	b.n	3eae <uart_nrfx_configure+0x16>
			uart_cfg.hwfc = NRF_UART_HWFC_ENABLED;
    3ef4:	2301      	movs	r3, #1
    3ef6:	f88d 3000 	strb.w	r3, [sp]
		break;
    3efa:	e7ef      	b.n	3edc <uart_nrfx_configure+0x44>
		uart_cfg.parity = NRF_UART_PARITY_EXCLUDED;
    3efc:	f88d 3001 	strb.w	r3, [sp, #1]
	if (baudrate_set(dev, cfg->baudrate) != 0) {
    3f00:	6821      	ldr	r1, [r4, #0]
    3f02:	4628      	mov	r0, r5
    3f04:	f7ff fefe 	bl	3d04 <baudrate_set>
    3f08:	4602      	mov	r2, r0
    3f0a:	bb10      	cbnz	r0, 3f52 <uart_nrfx_configure+0xba>
    p_reg->CONFIG = (uint32_t)p_cfg->parity
    3f0c:	f89d 3001 	ldrb.w	r3, [sp, #1]
                    | (uint32_t)p_cfg->stop
    3f10:	f89d 1002 	ldrb.w	r1, [sp, #2]
    3f14:	430b      	orrs	r3, r1
                    | (uint32_t)p_cfg->paritytype
    3f16:	f8bd 1004 	ldrh.w	r1, [sp, #4]
    3f1a:	430b      	orrs	r3, r1
                    | (uint32_t)p_cfg->hwfc;
    3f1c:	f89d 1000 	ldrb.w	r1, [sp]
    3f20:	430b      	orrs	r3, r1
    p_reg->CONFIG = (uint32_t)p_cfg->parity
    3f22:	490d      	ldr	r1, [pc, #52]	; (3f58 <uart_nrfx_configure+0xc0>)
    3f24:	f8c1 356c 	str.w	r3, [r1, #1388]	; 0x56c
	return dev->data;
    3f28:	692b      	ldr	r3, [r5, #16]
	get_dev_data(dev)->uart_config = *cfg;
    3f2a:	e894 0003 	ldmia.w	r4, {r0, r1}
    3f2e:	e883 0003 	stmia.w	r3, {r0, r1}
	return 0;
    3f32:	e7bc      	b.n	3eae <uart_nrfx_configure+0x16>
		uart_cfg.parity = NRF_UART_PARITY_INCLUDED;
    3f34:	230e      	movs	r3, #14
    3f36:	f88d 3001 	strb.w	r3, [sp, #1]
		break;
    3f3a:	e7e1      	b.n	3f00 <uart_nrfx_configure+0x68>
		uart_cfg.parity = NRF_UART_PARITY_INCLUDED;
    3f3c:	230e      	movs	r3, #14
    3f3e:	f88d 3001 	strb.w	r3, [sp, #1]
		uart_cfg.paritytype = NRF_UART_PARITYTYPE_ODD;
    3f42:	f44f 7380 	mov.w	r3, #256	; 0x100
    3f46:	f8ad 3004 	strh.w	r3, [sp, #4]
		break;
    3f4a:	e7d9      	b.n	3f00 <uart_nrfx_configure+0x68>
		return -ENOTSUP;
    3f4c:	f06f 0285 	mvn.w	r2, #133	; 0x85
    3f50:	e7ad      	b.n	3eae <uart_nrfx_configure+0x16>
		return -ENOTSUP;
    3f52:	f06f 0285 	mvn.w	r2, #133	; 0x85
    3f56:	e7aa      	b.n	3eae <uart_nrfx_configure+0x16>
    3f58:	40002000 	.word	0x40002000

00003f5c <uart_nrfx_init>:
 * @param dev UART device struct
 *
 * @return 0 on success
 */
static int uart_nrfx_init(const struct device *dev)
{
    3f5c:	b538      	push	{r3, r4, r5, lr}
    p_reg->ENABLE = UART_ENABLE_ENABLE_Disabled;
    3f5e:	4a18      	ldr	r2, [pc, #96]	; (3fc0 <uart_nrfx_init+0x64>)
    3f60:	2100      	movs	r1, #0
    3f62:	f8c2 1500 	str.w	r1, [r2, #1280]	; 0x500
    p_reg->OUTSET = set_mask;
    3f66:	f04f 43a0 	mov.w	r3, #1342177280	; 0x50000000
    3f6a:	2440      	movs	r4, #64	; 0x40
    3f6c:	f8c3 4508 	str.w	r4, [r3, #1288]	; 0x508
    reg->PIN_CNF[pin_number] = cnf;
    3f70:	2403      	movs	r4, #3
    3f72:	f8c3 4718 	str.w	r4, [r3, #1816]	; 0x718
    3f76:	f8c3 1720 	str.w	r1, [r3, #1824]	; 0x720
    p_reg->PSEL.RXD = pselrxd;
    3f7a:	2508      	movs	r5, #8
    3f7c:	f8c2 5514 	str.w	r5, [r2, #1300]	; 0x514
    p_reg->PSEL.TXD = pseltxd;
    3f80:	2506      	movs	r5, #6
    3f82:	f8c2 550c 	str.w	r5, [r2, #1292]	; 0x50c
    p_reg->OUTSET = set_mask;
    3f86:	2520      	movs	r5, #32
    3f88:	f8c3 5508 	str.w	r5, [r3, #1288]	; 0x508
    reg->PIN_CNF[pin_number] = cnf;
    3f8c:	f8c3 4714 	str.w	r4, [r3, #1812]	; 0x714
    3f90:	f8c3 171c 	str.w	r1, [r3, #1820]	; 0x71c
    p_reg->PSEL.RTS = pselrts;
    3f94:	2305      	movs	r3, #5
    3f96:	f8c2 3508 	str.w	r3, [r2, #1288]	; 0x508
    p_reg->PSEL.CTS = pselcts;
    3f9a:	2307      	movs	r3, #7
    3f9c:	f8c2 3510 	str.w	r3, [r2, #1296]	; 0x510
	}

	nrf_uart_hwfc_pins_set(uart0_addr, RTS_PIN, CTS_PIN);

	/* Set initial configuration */
	err = uart_nrfx_configure(dev, &get_dev_data(dev)->uart_config);
    3fa0:	6901      	ldr	r1, [r0, #16]
    3fa2:	f7ff ff79 	bl	3e98 <uart_nrfx_configure>
	if (err) {
    3fa6:	b948      	cbnz	r0, 3fbc <uart_nrfx_init+0x60>
    p_reg->ENABLE = UART_ENABLE_ENABLE_Enabled;
    3fa8:	4b05      	ldr	r3, [pc, #20]	; (3fc0 <uart_nrfx_init+0x64>)
    3faa:	2204      	movs	r2, #4
    3fac:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3fb0:	4a04      	ldr	r2, [pc, #16]	; (3fc4 <uart_nrfx_init+0x68>)
    3fb2:	2100      	movs	r1, #0
    3fb4:	6011      	str	r1, [r2, #0]
    3fb6:	6812      	ldr	r2, [r2, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    3fb8:	2201      	movs	r2, #1
    3fba:	601a      	str	r2, [r3, #0]
#if HW_FLOW_CONTROL_AVAILABLE
	k_timer_init(&uart0_cb.tx_timeout_timer, tx_timeout, NULL);
#endif
#endif
	return 0;
}
    3fbc:	bd38      	pop	{r3, r4, r5, pc}
    3fbe:	bf00      	nop
    3fc0:	40002000 	.word	0x40002000
    3fc4:	40002108 	.word	0x40002108

00003fc8 <uart_nrfx_poll_out>:
{
    3fc8:	b538      	push	{r3, r4, r5, lr}
    3fca:	460c      	mov	r4, r1
	if (!k_is_in_isr()) {
    3fcc:	f003 fd9d 	bl	7b0a <k_is_in_isr>
    3fd0:	b9c0      	cbnz	r0, 4004 <CONFIG_HEAP_MEM_POOL_SIZE+0x28>
		uint8_t safety_cnt = 100;
    3fd2:	2564      	movs	r5, #100	; 0x64
    3fd4:	4b19      	ldr	r3, [pc, #100]	; (403c <CONFIG_HEAP_MEM_POOL_SIZE+0x60>)
    3fd6:	2201      	movs	r2, #1
    3fd8:	f3bf 8f5b 	dmb	ish
    3fdc:	e853 1f00 	ldrex	r1, [r3]
    3fe0:	2900      	cmp	r1, #0
    3fe2:	d103      	bne.n	3fec <CONFIG_HEAP_MEM_POOL_SIZE+0x10>
    3fe4:	e843 2000 	strex	r0, r2, [r3]
    3fe8:	2800      	cmp	r0, #0
    3fea:	d1f7      	bne.n	3fdc <CONFIG_HEAP_MEM_POOL_SIZE>
    3fec:	f3bf 8f5b 	dmb	ish
		while (atomic_cas((atomic_t *) lock,
    3ff0:	d00b      	beq.n	400a <CONFIG_HEAP_MEM_POOL_SIZE+0x2e>
	return z_impl_k_sleep(timeout);
    3ff2:	2021      	movs	r0, #33	; 0x21
    3ff4:	2100      	movs	r1, #0
    3ff6:	f002 f985 	bl	6304 <z_impl_k_sleep>
			if (--safety_cnt == 0) {
    3ffa:	3d01      	subs	r5, #1
    3ffc:	f015 05ff 	ands.w	r5, r5, #255	; 0xff
    4000:	d1e8      	bne.n	3fd4 <uart_nrfx_poll_out+0xc>
    4002:	e002      	b.n	400a <CONFIG_HEAP_MEM_POOL_SIZE+0x2e>
		*lock = 1;
    4004:	4b0d      	ldr	r3, [pc, #52]	; (403c <CONFIG_HEAP_MEM_POOL_SIZE+0x60>)
    4006:	2201      	movs	r2, #1
    4008:	601a      	str	r2, [r3, #0]
	event_txdrdy_clear();
    400a:	f7ff fe73 	bl	3cf4 <event_txdrdy_clear>
    400e:	4b0c      	ldr	r3, [pc, #48]	; (4040 <CONFIG_HEAP_MEM_POOL_SIZE+0x64>)
    4010:	2201      	movs	r2, #1
    4012:	601a      	str	r2, [r3, #0]
    p_reg->TXD = txd;
    4014:	3b08      	subs	r3, #8
    4016:	f8c3 451c 	str.w	r4, [r3, #1308]	; 0x51c
	NRFX_WAIT_FOR(event_txdrdy_check(), 1000, 1, res);
    401a:	f44f 747a 	mov.w	r4, #1000	; 0x3e8
    401e:	f7ff fe61 	bl	3ce4 <event_txdrdy_check>
    4022:	b920      	cbnz	r0, 402e <CONFIG_HEAP_MEM_POOL_SIZE+0x52>
    4024:	2001      	movs	r0, #1
    4026:	f003 fba0 	bl	776a <nrfx_busy_wait>
    402a:	3c01      	subs	r4, #1
    402c:	d1f7      	bne.n	401e <CONFIG_HEAP_MEM_POOL_SIZE+0x42>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    402e:	4b05      	ldr	r3, [pc, #20]	; (4044 <CONFIG_HEAP_MEM_POOL_SIZE+0x68>)
    4030:	2201      	movs	r2, #1
    4032:	601a      	str	r2, [r3, #0]
	*lock = 0;
    4034:	4b01      	ldr	r3, [pc, #4]	; (403c <CONFIG_HEAP_MEM_POOL_SIZE+0x60>)
    4036:	2200      	movs	r2, #0
    4038:	601a      	str	r2, [r3, #0]
}
    403a:	bd38      	pop	{r3, r4, r5, pc}
    403c:	200005c4 	.word	0x200005c4
    4040:	40002008 	.word	0x40002008
    4044:	4000200c 	.word	0x4000200c

00004048 <set_comparator>:
	return (a - b) & COUNTER_MAX;
}

static void set_comparator(int32_t chan, uint32_t cyc)
{
	nrf_rtc_cc_set(RTC, chan, cyc & COUNTER_MAX);
    4048:	f021 417f 	bic.w	r1, r1, #4278190080	; 0xff000000

#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE  void nrf_rtc_cc_set(NRF_RTC_Type * p_reg, uint32_t ch, uint32_t cc_val)
{
    p_reg->CC[ch] = cc_val;
    404c:	f500 70a8 	add.w	r0, r0, #336	; 0x150
    4050:	4b01      	ldr	r3, [pc, #4]	; (4058 <set_comparator+0x10>)
    4052:	f843 1020 	str.w	r1, [r3, r0, lsl #2]
}
    4056:	4770      	bx	lr
    4058:	40011000 	.word	0x40011000

0000405c <get_comparator>:
}

NRF_STATIC_INLINE  uint32_t nrf_rtc_cc_get(NRF_RTC_Type const * p_reg, uint32_t ch)
{
    return p_reg->CC[ch];
    405c:	f500 70a8 	add.w	r0, r0, #336	; 0x150
    4060:	4b01      	ldr	r3, [pc, #4]	; (4068 <get_comparator+0xc>)
    4062:	f853 0020 	ldr.w	r0, [r3, r0, lsl #2]

static uint32_t get_comparator(int32_t chan)
{
	return nrf_rtc_cc_get(RTC, chan);
}
    4066:	4770      	bx	lr
    4068:	40011000 	.word	0x40011000

0000406c <event_enable>:
	nrf_rtc_event_clear(RTC, RTC_CHANNEL_EVENT_ADDR(chan));
}

static void event_enable(int32_t chan)
{
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    406c:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    4070:	4083      	lsls	r3, r0
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
}

NRF_STATIC_INLINE void nrf_rtc_event_enable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->EVTENSET = mask;
    4072:	4a02      	ldr	r2, [pc, #8]	; (407c <event_enable+0x10>)
    4074:	f8c2 3344 	str.w	r3, [r2, #836]	; 0x344
}
    4078:	4770      	bx	lr
    407a:	bf00      	nop
    407c:	40011000 	.word	0x40011000

00004080 <event_disable>:

static void event_disable(int32_t chan)
{
	nrf_rtc_event_disable(RTC, RTC_CHANNEL_INT_MASK(chan));
    4080:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    4084:	4083      	lsls	r3, r0
}

NRF_STATIC_INLINE void nrf_rtc_event_disable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->EVTENCLR = mask;
    4086:	4a02      	ldr	r2, [pc, #8]	; (4090 <event_disable+0x10>)
    4088:	f8c2 3348 	str.w	r3, [r2, #840]	; 0x348
}
    408c:	4770      	bx	lr
    408e:	bf00      	nop
    4090:	40011000 	.word	0x40011000

00004094 <counter>:
     return p_reg->COUNTER;
    4094:	4b01      	ldr	r3, [pc, #4]	; (409c <counter+0x8>)
    4096:	f8d3 0504 	ldr.w	r0, [r3, #1284]	; 0x504

static uint32_t counter(void)
{
	return nrf_rtc_counter_get(RTC);
}
    409a:	4770      	bx	lr
    409c:	40011000 	.word	0x40011000

000040a0 <compare_int_lock>:
	__ASSERT_NO_MSG(chan < CHAN_COUNT);
	return nrf_rtc_event_address_get(RTC, nrf_rtc_compare_event_get(chan));
}

static bool compare_int_lock(int32_t chan)
{
    40a0:	b510      	push	{r4, lr}
	atomic_val_t prev = atomic_and(&int_mask, ~BIT(chan));
    40a2:	2301      	movs	r3, #1
    40a4:	4083      	lsls	r3, r0
    40a6:	43dc      	mvns	r4, r3
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    40a8:	4a10      	ldr	r2, [pc, #64]	; (40ec <compare_int_lock+0x4c>)
    40aa:	f3bf 8f5b 	dmb	ish
    40ae:	e852 1f00 	ldrex	r1, [r2]
    40b2:	ea01 0c04 	and.w	ip, r1, r4
    40b6:	e842 ce00 	strex	lr, ip, [r2]
    40ba:	f1be 0f00 	cmp.w	lr, #0
    40be:	d1f6      	bne.n	40ae <compare_int_lock+0xe>
    40c0:	f3bf 8f5b 	dmb	ish

	nrf_rtc_int_disable(RTC, RTC_CHANNEL_INT_MASK(chan));
    40c4:	f44f 3280 	mov.w	r2, #65536	; 0x10000
    40c8:	fa02 f000 	lsl.w	r0, r2, r0
    p_reg->INTENCLR = mask;
    40cc:	f102 4280 	add.w	r2, r2, #1073741824	; 0x40000000
    40d0:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
    40d4:	f8c2 0308 	str.w	r0, [r2, #776]	; 0x308
  __ASM volatile ("dmb 0xF":::"memory");
    40d8:	f3bf 8f5f 	dmb	sy
  __ASM volatile ("isb 0xF":::"memory");
    40dc:	f3bf 8f6f 	isb	sy

	__DMB();
	__ISB();

	return prev & BIT(chan);
    40e0:	420b      	tst	r3, r1
}
    40e2:	bf14      	ite	ne
    40e4:	2001      	movne	r0, #1
    40e6:	2000      	moveq	r0, #0
    40e8:	bd10      	pop	{r4, pc}
    40ea:	bf00      	nop
    40ec:	200005cc 	.word	0x200005cc

000040f0 <channel_processing_check_and_clear>:
		event_enable(chan);
	}
}

static bool channel_processing_check_and_clear(int32_t chan)
{
    40f0:	b570      	push	{r4, r5, r6, lr}
    40f2:	4604      	mov	r4, r0
	bool result = false;

	uint32_t mcu_critical_state = full_int_lock();
    40f4:	f003 fad0 	bl	7698 <full_int_lock>
    40f8:	4605      	mov	r5, r0

	if (nrf_rtc_int_enable_check(RTC, RTC_CHANNEL_INT_MASK(chan))) {
    40fa:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    40fe:	40a3      	lsls	r3, r4
    return p_reg->INTENSET & mask;
    4100:	4a17      	ldr	r2, [pc, #92]	; (4160 <channel_processing_check_and_clear+0x70>)
    4102:	f8d2 2304 	ldr.w	r2, [r2, #772]	; 0x304
    4106:	4213      	tst	r3, r2
    4108:	d105      	bne.n	4116 <channel_processing_check_and_clear+0x26>
	bool result = false;
    410a:	2600      	movs	r6, #0
		if (result) {
			event_clear(chan);
		}
	}

	full_int_unlock(mcu_critical_state);
    410c:	4628      	mov	r0, r5
    410e:	f003 facc 	bl	76aa <full_int_unlock>

	return result;
}
    4112:	4630      	mov	r0, r6
    4114:	bd70      	pop	{r4, r5, r6, pc}
		result = atomic_and(&force_isr_mask, ~BIT(chan)) ||
    4116:	2301      	movs	r3, #1
    4118:	40a3      	lsls	r3, r4
    411a:	43db      	mvns	r3, r3
    411c:	4a11      	ldr	r2, [pc, #68]	; (4164 <channel_processing_check_and_clear+0x74>)
    411e:	f3bf 8f5b 	dmb	ish
    4122:	e852 1f00 	ldrex	r1, [r2]
    4126:	ea01 0003 	and.w	r0, r1, r3
    412a:	e842 0600 	strex	r6, r0, [r2]
    412e:	2e00      	cmp	r6, #0
    4130:	d1f7      	bne.n	4122 <channel_processing_check_and_clear+0x32>
    4132:	f3bf 8f5b 	dmb	ish
    4136:	b959      	cbnz	r1, 4150 <channel_processing_check_and_clear+0x60>
			 nrf_rtc_event_check(RTC, RTC_CHANNEL_EVENT_ADDR(chan));
    4138:	f104 0350 	add.w	r3, r4, #80	; 0x50
    413c:	009b      	lsls	r3, r3, #2
    413e:	b29b      	uxth	r3, r3
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    4140:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    4144:	f503 3388 	add.w	r3, r3, #69632	; 0x11000
    4148:	681b      	ldr	r3, [r3, #0]
		result = atomic_and(&force_isr_mask, ~BIT(chan)) ||
    414a:	b113      	cbz	r3, 4152 <channel_processing_check_and_clear+0x62>
    414c:	2301      	movs	r3, #1
    414e:	e000      	b.n	4152 <channel_processing_check_and_clear+0x62>
    4150:	2301      	movs	r3, #1
		if (result) {
    4152:	461e      	mov	r6, r3
    4154:	2b00      	cmp	r3, #0
    4156:	d0d9      	beq.n	410c <channel_processing_check_and_clear+0x1c>
			event_clear(chan);
    4158:	4620      	mov	r0, r4
    415a:	f003 fa8e 	bl	767a <event_clear>
    415e:	e7d5      	b.n	410c <channel_processing_check_and_clear+0x1c>
    4160:	40011000 	.word	0x40011000
    4164:	200005c8 	.word	0x200005c8

00004168 <compare_int_unlock>:
	if (key) {
    4168:	b901      	cbnz	r1, 416c <compare_int_unlock+0x4>
}
    416a:	4770      	bx	lr
		atomic_or(&int_mask, BIT(chan));
    416c:	2301      	movs	r3, #1
    416e:	4083      	lsls	r3, r0
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    4170:	4a11      	ldr	r2, [pc, #68]	; (41b8 <compare_int_unlock+0x50>)
    4172:	f3bf 8f5b 	dmb	ish
    4176:	e852 1f00 	ldrex	r1, [r2]
    417a:	4319      	orrs	r1, r3
    417c:	e842 1c00 	strex	ip, r1, [r2]
    4180:	f1bc 0f00 	cmp.w	ip, #0
    4184:	d1f7      	bne.n	4176 <compare_int_unlock+0xe>
    4186:	f3bf 8f5b 	dmb	ish
		nrf_rtc_int_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    418a:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    418e:	4083      	lsls	r3, r0
    p_reg->INTENSET = mask;
    4190:	4a0a      	ldr	r2, [pc, #40]	; (41bc <compare_int_unlock+0x54>)
    4192:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
	return __atomic_load_n(target, __ATOMIC_SEQ_CST);
    4196:	f3bf 8f5b 	dmb	ish
    419a:	4b09      	ldr	r3, [pc, #36]	; (41c0 <compare_int_unlock+0x58>)
    419c:	681b      	ldr	r3, [r3, #0]
    419e:	f3bf 8f5b 	dmb	ish
		if (atomic_get(&force_isr_mask) & BIT(chan)) {
    41a2:	fa23 f000 	lsr.w	r0, r3, r0
    41a6:	f010 0f01 	tst.w	r0, #1
    41aa:	d0de      	beq.n	416a <compare_int_unlock+0x2>
    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    41ac:	4b05      	ldr	r3, [pc, #20]	; (41c4 <compare_int_unlock+0x5c>)
    41ae:	f44f 3200 	mov.w	r2, #131072	; 0x20000
    41b2:	f8c3 2100 	str.w	r2, [r3, #256]	; 0x100
}
    41b6:	e7d8      	b.n	416a <compare_int_unlock+0x2>
    41b8:	200005cc 	.word	0x200005cc
    41bc:	40011000 	.word	0x40011000
    41c0:	200005c8 	.word	0x200005c8
    41c4:	e000e100 	.word	0xe000e100

000041c8 <sys_clock_timeout_handler>:
{
    41c8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    41ca:	4607      	mov	r7, r0
    41cc:	4614      	mov	r4, r2
    41ce:	461e      	mov	r6, r3
	uint32_t cc_value = absolute_time_to_cc(expire_time);
    41d0:	4610      	mov	r0, r2
    41d2:	4619      	mov	r1, r3
    41d4:	f003 fa5d 	bl	7692 <absolute_time_to_cc>
    41d8:	4605      	mov	r5, r0
	uint64_t dticks = (expire_time - last_count) / CYC_PER_TICK;
    41da:	4b15      	ldr	r3, [pc, #84]	; (4230 <sys_clock_timeout_handler+0x68>)
    41dc:	681a      	ldr	r2, [r3, #0]
    41de:	1aa0      	subs	r0, r4, r2
	last_count += dticks * CYC_PER_TICK;
    41e0:	601c      	str	r4, [r3, #0]
    41e2:	605e      	str	r6, [r3, #4]
	return (cc_value >= ANCHOR_RANGE_START) && (cc_value < ANCHOR_RANGE_END);
    41e4:	f5a5 1300 	sub.w	r3, r5, #2097152	; 0x200000
	if (in_anchor_range(cc_value)) {
    41e8:	f5b3 0f40 	cmp.w	r3, #12582912	; 0xc00000
    41ec:	d308      	bcc.n	4200 <sys_clock_timeout_handler+0x38>
	return false;
    41ee:	2400      	movs	r4, #0
	sys_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
    41f0:	f002 fa10 	bl	6614 <sys_clock_announce>
	if (cc_value == get_comparator(chan)) {
    41f4:	4638      	mov	r0, r7
    41f6:	f7ff ff31 	bl	405c <get_comparator>
    41fa:	42a8      	cmp	r0, r5
    41fc:	d00c      	beq.n	4218 <sys_clock_timeout_handler+0x50>
}
    41fe:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
		anchor = (((uint64_t)overflow_cnt) << COUNTER_BIT_WIDTH) + cc_value;
    4200:	4b0c      	ldr	r3, [pc, #48]	; (4234 <sys_clock_timeout_handler+0x6c>)
    4202:	6819      	ldr	r1, [r3, #0]
    4204:	0a0b      	lsrs	r3, r1, #8
    4206:	060a      	lsls	r2, r1, #24
    4208:	1952      	adds	r2, r2, r5
    420a:	f143 0300 	adc.w	r3, r3, #0
    420e:	490a      	ldr	r1, [pc, #40]	; (4238 <sys_clock_timeout_handler+0x70>)
    4210:	e9c1 2300 	strd	r2, r3, [r1]
		return true;
    4214:	2401      	movs	r4, #1
    4216:	e7eb      	b.n	41f0 <sys_clock_timeout_handler+0x28>
		if (!anchor_updated) {
    4218:	b11c      	cbz	r4, 4222 <sys_clock_timeout_handler+0x5a>
		event_enable(chan);
    421a:	4638      	mov	r0, r7
    421c:	f7ff ff26 	bl	406c <event_enable>
}
    4220:	e7ed      	b.n	41fe <sys_clock_timeout_handler+0x36>
			set_comparator(chan, COUNTER_HALF_SPAN);
    4222:	f44f 0100 	mov.w	r1, #8388608	; 0x800000
    4226:	4638      	mov	r0, r7
    4228:	f7ff ff0e 	bl	4048 <set_comparator>
    422c:	e7f5      	b.n	421a <sys_clock_timeout_handler+0x52>
    422e:	bf00      	nop
    4230:	200001d8 	.word	0x200001d8
    4234:	200005d0 	.word	0x200005d0
    4238:	200001c0 	.word	0x200001c0

0000423c <z_nrf_rtc_timer_read>:
{
    423c:	b538      	push	{r3, r4, r5, lr}
	uint64_t val = ((uint64_t)overflow_cnt) << COUNTER_BIT_WIDTH;
    423e:	4b0d      	ldr	r3, [pc, #52]	; (4274 <z_nrf_rtc_timer_read+0x38>)
    4240:	681b      	ldr	r3, [r3, #0]
    4242:	0a1d      	lsrs	r5, r3, #8
    4244:	061c      	lsls	r4, r3, #24
  __ASM volatile ("dmb 0xF":::"memory");
    4246:	f3bf 8f5f 	dmb	sy
	uint32_t cntr = counter();
    424a:	f7ff ff23 	bl	4094 <counter>
    424e:	4603      	mov	r3, r0
	val += cntr;
    4250:	1820      	adds	r0, r4, r0
    4252:	f145 0100 	adc.w	r1, r5, #0
	if (cntr < OVERFLOW_RISK_RANGE_END) {
    4256:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
    425a:	d20a      	bcs.n	4272 <z_nrf_rtc_timer_read+0x36>
		if (val < anchor) {
    425c:	4b06      	ldr	r3, [pc, #24]	; (4278 <z_nrf_rtc_timer_read+0x3c>)
    425e:	e9d3 2300 	ldrd	r2, r3, [r3]
    4262:	4299      	cmp	r1, r3
    4264:	bf08      	it	eq
    4266:	4290      	cmpeq	r0, r2
    4268:	d203      	bcs.n	4272 <z_nrf_rtc_timer_read+0x36>
			val += COUNTER_SPAN;
    426a:	f110 7080 	adds.w	r0, r0, #16777216	; 0x1000000
    426e:	f141 0100 	adc.w	r1, r1, #0
}
    4272:	bd38      	pop	{r3, r4, r5, pc}
    4274:	200005d0 	.word	0x200005d0
    4278:	200001c0 	.word	0x200001c0

0000427c <compare_set_nolocks>:
{
    427c:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    4280:	4606      	mov	r6, r0
    4282:	4614      	mov	r4, r2
    4284:	461d      	mov	r5, r3
	uint32_t cc_value = absolute_time_to_cc(target_time);
    4286:	4610      	mov	r0, r2
    4288:	4619      	mov	r1, r3
    428a:	f003 fa02 	bl	7692 <absolute_time_to_cc>
    428e:	4607      	mov	r7, r0
	uint64_t curr_time = z_nrf_rtc_timer_read();
    4290:	f7ff ffd4 	bl	423c <z_nrf_rtc_timer_read>
	if (curr_time < target_time) {
    4294:	42a9      	cmp	r1, r5
    4296:	bf08      	it	eq
    4298:	42a0      	cmpeq	r0, r4
    429a:	d21e      	bcs.n	42da <compare_set_nolocks+0x5e>
		if (target_time - curr_time > COUNTER_SPAN) {
    429c:	ebb4 0800 	subs.w	r8, r4, r0
    42a0:	eb65 0901 	sbc.w	r9, r5, r1
    42a4:	f04f 7280 	mov.w	r2, #16777216	; 0x1000000
    42a8:	2300      	movs	r3, #0
    42aa:	454b      	cmp	r3, r9
    42ac:	bf08      	it	eq
    42ae:	4542      	cmpeq	r2, r8
    42b0:	d32e      	bcc.n	4310 <compare_set_nolocks+0x94>
		if (target_time != cc_data[chan].target_time) {
    42b2:	4b19      	ldr	r3, [pc, #100]	; (4318 <compare_set_nolocks+0x9c>)
    42b4:	eb03 1306 	add.w	r3, r3, r6, lsl #4
    42b8:	e9d3 2302 	ldrd	r2, r3, [r3, #8]
    42bc:	42ab      	cmp	r3, r5
    42be:	bf08      	it	eq
    42c0:	42a2      	cmpeq	r2, r4
    42c2:	d018      	beq.n	42f6 <compare_set_nolocks+0x7a>
			uint32_t cc_set = set_absolute_alarm(chan, cc_value);
    42c4:	4639      	mov	r1, r7
    42c6:	4630      	mov	r0, r6
    42c8:	f003 f9f4 	bl	76b4 <set_absolute_alarm>
			target_time += counter_sub(cc_set, cc_value);
    42cc:	4639      	mov	r1, r7
    42ce:	f003 f9d0 	bl	7672 <counter_sub>
    42d2:	1824      	adds	r4, r4, r0
    42d4:	f145 0500 	adc.w	r5, r5, #0
    42d8:	e00d      	b.n	42f6 <compare_set_nolocks+0x7a>
		atomic_or(&force_isr_mask, BIT(chan));
    42da:	2301      	movs	r3, #1
    42dc:	40b3      	lsls	r3, r6
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    42de:	4a0f      	ldr	r2, [pc, #60]	; (431c <compare_set_nolocks+0xa0>)
    42e0:	f3bf 8f5b 	dmb	ish
    42e4:	e852 1f00 	ldrex	r1, [r2]
    42e8:	4319      	orrs	r1, r3
    42ea:	e842 1000 	strex	r0, r1, [r2]
    42ee:	2800      	cmp	r0, #0
    42f0:	d1f8      	bne.n	42e4 <compare_set_nolocks+0x68>
    42f2:	f3bf 8f5b 	dmb	ish
	cc_data[chan].target_time = target_time;
    42f6:	4b08      	ldr	r3, [pc, #32]	; (4318 <compare_set_nolocks+0x9c>)
    42f8:	0132      	lsls	r2, r6, #4
    42fa:	eb03 1606 	add.w	r6, r3, r6, lsl #4
    42fe:	e9c6 4502 	strd	r4, r5, [r6, #8]
	cc_data[chan].callback = handler;
    4302:	9908      	ldr	r1, [sp, #32]
    4304:	5099      	str	r1, [r3, r2]
	cc_data[chan].user_context = user_data;
    4306:	9b09      	ldr	r3, [sp, #36]	; 0x24
    4308:	6073      	str	r3, [r6, #4]
	return ret;
    430a:	2000      	movs	r0, #0
}
    430c:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
			return -EINVAL;
    4310:	f06f 0015 	mvn.w	r0, #21
    4314:	e7fa      	b.n	430c <compare_set_nolocks+0x90>
    4316:	bf00      	nop
    4318:	200001c8 	.word	0x200001c8
    431c:	200005c8 	.word	0x200005c8

00004320 <process_channel>:

static void process_channel(int32_t chan)
{
    4320:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
    4324:	b082      	sub	sp, #8
    4326:	4604      	mov	r4, r0
	if (channel_processing_check_and_clear(chan)) {
    4328:	f7ff fee2 	bl	40f0 <channel_processing_check_and_clear>
    432c:	b910      	cbnz	r0, 4334 <process_channel+0x14>

		if (handler) {
			handler(chan, expire_time, user_context);
		}
	}
}
    432e:	b002      	add	sp, #8
    4330:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
		curr_time = z_nrf_rtc_timer_read();
    4334:	f7ff ff82 	bl	423c <z_nrf_rtc_timer_read>
    4338:	4606      	mov	r6, r0
    433a:	460f      	mov	r7, r1
		mcu_critical_state = full_int_lock();
    433c:	f003 f9ac 	bl	7698 <full_int_lock>
    4340:	4682      	mov	sl, r0
		expire_time = cc_data[chan].target_time;
    4342:	4b13      	ldr	r3, [pc, #76]	; (4390 <process_channel+0x70>)
    4344:	eb03 1304 	add.w	r3, r3, r4, lsl #4
    4348:	e9d3 8902 	ldrd	r8, r9, [r3, #8]
		if (curr_time >= expire_time) {
    434c:	454f      	cmp	r7, r9
    434e:	bf08      	it	eq
    4350:	4546      	cmpeq	r6, r8
    4352:	d20b      	bcs.n	436c <process_channel+0x4c>
		z_nrf_rtc_timer_compare_handler_t handler = NULL;
    4354:	2600      	movs	r6, #0
		full_int_unlock(mcu_critical_state);
    4356:	4650      	mov	r0, sl
    4358:	f003 f9a7 	bl	76aa <full_int_unlock>
		if (handler) {
    435c:	2e00      	cmp	r6, #0
    435e:	d0e6      	beq.n	432e <process_channel+0xe>
			handler(chan, expire_time, user_context);
    4360:	9500      	str	r5, [sp, #0]
    4362:	4642      	mov	r2, r8
    4364:	464b      	mov	r3, r9
    4366:	4620      	mov	r0, r4
    4368:	47b0      	blx	r6
}
    436a:	e7e0      	b.n	432e <process_channel+0xe>
			handler = cc_data[chan].callback;
    436c:	4a08      	ldr	r2, [pc, #32]	; (4390 <process_channel+0x70>)
    436e:	0123      	lsls	r3, r4, #4
    4370:	eb02 1104 	add.w	r1, r2, r4, lsl #4
    4374:	58d6      	ldr	r6, [r2, r3]
			user_context = cc_data[chan].user_context;
    4376:	684d      	ldr	r5, [r1, #4]
			cc_data[chan].callback = NULL;
    4378:	2000      	movs	r0, #0
    437a:	50d0      	str	r0, [r2, r3]
			cc_data[chan].target_time = TARGET_TIME_INVALID;
    437c:	f04f 32ff 	mov.w	r2, #4294967295
    4380:	f04f 33ff 	mov.w	r3, #4294967295
    4384:	e9c1 2302 	strd	r2, r3, [r1, #8]
			event_disable(chan);
    4388:	4620      	mov	r0, r4
    438a:	f7ff fe79 	bl	4080 <event_disable>
    438e:	e7e2      	b.n	4356 <process_channel+0x36>
    4390:	200001c8 	.word	0x200001c8

00004394 <rtc_nrf_isr>:
 * probably better abstract that at some point (e.g. query and reset
 * it by pointer at runtime, maybe?) so we don't have this leaky
 * symbol.
 */
void rtc_nrf_isr(const void *arg)
{
    4394:	b510      	push	{r4, lr}
    return p_reg->INTENSET & mask;
    4396:	4b0d      	ldr	r3, [pc, #52]	; (43cc <rtc_nrf_isr+0x38>)
    4398:	f8d3 3304 	ldr.w	r3, [r3, #772]	; 0x304
	ARG_UNUSED(arg);

	if (nrf_rtc_int_enable_check(RTC, NRF_RTC_INT_OVERFLOW_MASK) &&
    439c:	f013 0f02 	tst.w	r3, #2
    43a0:	d00a      	beq.n	43b8 <rtc_nrf_isr+0x24>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    43a2:	4b0b      	ldr	r3, [pc, #44]	; (43d0 <rtc_nrf_isr+0x3c>)
    43a4:	681b      	ldr	r3, [r3, #0]
    43a6:	b13b      	cbz	r3, 43b8 <rtc_nrf_isr+0x24>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    43a8:	4b09      	ldr	r3, [pc, #36]	; (43d0 <rtc_nrf_isr+0x3c>)
    43aa:	2200      	movs	r2, #0
    43ac:	601a      	str	r2, [r3, #0]
    43ae:	681b      	ldr	r3, [r3, #0]
	    nrf_rtc_event_check(RTC, NRF_RTC_EVENT_OVERFLOW)) {
		nrf_rtc_event_clear(RTC, NRF_RTC_EVENT_OVERFLOW);
		overflow_cnt++;
    43b0:	4a08      	ldr	r2, [pc, #32]	; (43d4 <rtc_nrf_isr+0x40>)
    43b2:	6813      	ldr	r3, [r2, #0]
    43b4:	3301      	adds	r3, #1
    43b6:	6013      	str	r3, [r2, #0]
{
    43b8:	2400      	movs	r4, #0
	}

	for (int32_t chan = 0; chan < CHAN_COUNT; chan++) {
    43ba:	2c00      	cmp	r4, #0
    43bc:	dd00      	ble.n	43c0 <rtc_nrf_isr+0x2c>
		process_channel(chan);
	}
}
    43be:	bd10      	pop	{r4, pc}
		process_channel(chan);
    43c0:	4620      	mov	r0, r4
    43c2:	f7ff ffad 	bl	4320 <process_channel>
	for (int32_t chan = 0; chan < CHAN_COUNT; chan++) {
    43c6:	3401      	adds	r4, #1
    43c8:	e7f7      	b.n	43ba <rtc_nrf_isr+0x26>
    43ca:	bf00      	nop
    43cc:	40011000 	.word	0x40011000
    43d0:	40011104 	.word	0x40011104
    43d4:	200005d0 	.word	0x200005d0

000043d8 <sys_clock_driver_init>:

	atomic_or(&alloc_mask, BIT(chan));
}

int sys_clock_driver_init(const struct device *dev)
{
    43d8:	b530      	push	{r4, r5, lr}
    43da:	b083      	sub	sp, #12
    p_reg->PRESCALER = val;
    43dc:	2300      	movs	r3, #0
    43de:	4a1f      	ldr	r2, [pc, #124]	; (445c <sys_clock_driver_init+0x84>)
    43e0:	f8c2 3508 	str.w	r3, [r2, #1288]	; 0x508
			CLOCK_CONTROL_NRF_LF_START_AVAILABLE :
			CLOCK_CONTROL_NRF_LF_START_STABLE);

	/* TODO: replace with counter driver to access RTC */
	nrf_rtc_prescaler_set(RTC, 0);
	for (int32_t chan = 0; chan < CHAN_COUNT; chan++) {
    43e4:	2b00      	cmp	r3, #0
    43e6:	dd27      	ble.n	4438 <sys_clock_driver_init+0x60>
    p_reg->INTENSET = mask;
    43e8:	4c1c      	ldr	r4, [pc, #112]	; (445c <sys_clock_driver_init+0x84>)
    43ea:	2502      	movs	r5, #2
    43ec:	f8c4 5304 	str.w	r5, [r4, #772]	; 0x304
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    43f0:	4b1b      	ldr	r3, [pc, #108]	; (4460 <sys_clock_driver_init+0x88>)
    43f2:	f44f 3200 	mov.w	r2, #131072	; 0x20000
    43f6:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180

	nrf_rtc_int_enable(RTC, NRF_RTC_INT_OVERFLOW_MASK);

	NVIC_ClearPendingIRQ(RTC_IRQn);

	IRQ_CONNECT(RTC_IRQn, DT_IRQ(DT_NODELABEL(RTC_LABEL), priority),
    43fa:	2200      	movs	r2, #0
    43fc:	2101      	movs	r1, #1
    43fe:	2011      	movs	r0, #17
    4400:	f7fd ff04 	bl	220c <z_arm_irq_priority_set>
		    rtc_nrf_isr, 0, 0);
	irq_enable(RTC_IRQn);
    4404:	2011      	movs	r0, #17
    4406:	f7fd fee3 	bl	21d0 <arch_irq_enable>
    440a:	f8c4 5304 	str.w	r5, [r4, #772]	; 0x304
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    440e:	2301      	movs	r3, #1
    4410:	4a14      	ldr	r2, [pc, #80]	; (4464 <sys_clock_driver_init+0x8c>)
    4412:	6013      	str	r3, [r2, #0]
    4414:	6023      	str	r3, [r4, #0]

	nrf_rtc_int_enable(RTC, NRF_RTC_INT_OVERFLOW_MASK);
	nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_CLEAR);
	nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_START);

	int_mask = BIT_MASK(CHAN_COUNT);
    4416:	4a14      	ldr	r2, [pc, #80]	; (4468 <sys_clock_driver_init+0x90>)
    4418:	6013      	str	r3, [r2, #0]

	uint32_t initial_timeout = IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
				(COUNTER_HALF_SPAN - 1) :
				(counter() + CYC_PER_TICK);

	compare_set(0, initial_timeout, sys_clock_timeout_handler, NULL);
    441a:	2400      	movs	r4, #0
    441c:	9401      	str	r4, [sp, #4]
    441e:	4b13      	ldr	r3, [pc, #76]	; (446c <sys_clock_driver_init+0x94>)
    4420:	9300      	str	r3, [sp, #0]
    4422:	4a13      	ldr	r2, [pc, #76]	; (4470 <sys_clock_driver_init+0x98>)
    4424:	2300      	movs	r3, #0
    4426:	4620      	mov	r0, r4
    4428:	f003 f97f 	bl	772a <compare_set>

	z_nrf_clock_control_lf_on(mode);
    442c:	4628      	mov	r0, r5
    442e:	f7fe fe5b 	bl	30e8 <z_nrf_clock_control_lf_on>

	return 0;
}
    4432:	4620      	mov	r0, r4
    4434:	b003      	add	sp, #12
    4436:	bd30      	pop	{r4, r5, pc}
		cc_data[chan].target_time = TARGET_TIME_INVALID;
    4438:	4a0e      	ldr	r2, [pc, #56]	; (4474 <sys_clock_driver_init+0x9c>)
    443a:	eb02 1203 	add.w	r2, r2, r3, lsl #4
    443e:	f04f 30ff 	mov.w	r0, #4294967295
    4442:	f04f 31ff 	mov.w	r1, #4294967295
    4446:	e9c2 0102 	strd	r0, r1, [r2, #8]
		nrf_rtc_int_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    444a:	f44f 3280 	mov.w	r2, #65536	; 0x10000
    444e:	409a      	lsls	r2, r3
    p_reg->INTENSET = mask;
    4450:	4902      	ldr	r1, [pc, #8]	; (445c <sys_clock_driver_init+0x84>)
    4452:	f8c1 2304 	str.w	r2, [r1, #772]	; 0x304
	for (int32_t chan = 0; chan < CHAN_COUNT; chan++) {
    4456:	3301      	adds	r3, #1
    4458:	e7c4      	b.n	43e4 <sys_clock_driver_init+0xc>
    445a:	bf00      	nop
    445c:	40011000 	.word	0x40011000
    4460:	e000e100 	.word	0xe000e100
    4464:	40011008 	.word	0x40011008
    4468:	200005cc 	.word	0x200005cc
    446c:	000041c9 	.word	0x000041c9
    4470:	007fffff 	.word	0x007fffff
    4474:	200001c8 	.word	0x200001c8

00004478 <sys_clock_set_timeout>:

void sys_clock_set_timeout(int32_t ticks, bool idle)
{
    4478:	b510      	push	{r4, lr}
    447a:	b082      	sub	sp, #8

	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
		return;
	}

	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    447c:	f1b0 3fff 	cmp.w	r0, #4294967295
    4480:	d007      	beq.n	4492 <sys_clock_set_timeout+0x1a>
	ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
    4482:	1e44      	subs	r4, r0, #1
    4484:	2c00      	cmp	r4, #0
    4486:	dd07      	ble.n	4498 <sys_clock_set_timeout+0x20>
    4488:	4b11      	ldr	r3, [pc, #68]	; (44d0 <sys_clock_set_timeout+0x58>)
    448a:	429c      	cmp	r4, r3
    448c:	dd05      	ble.n	449a <sys_clock_set_timeout+0x22>
    448e:	4c11      	ldr	r4, [pc, #68]	; (44d4 <sys_clock_set_timeout+0x5c>)
    4490:	e003      	b.n	449a <sys_clock_set_timeout+0x22>
	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    4492:	f500 0000 	add.w	r0, r0, #8388608	; 0x800000
    4496:	e7f4      	b.n	4482 <sys_clock_set_timeout+0xa>
	ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
    4498:	2400      	movs	r4, #0

	uint32_t unannounced = z_nrf_rtc_timer_read() - last_count;
    449a:	f7ff fecf 	bl	423c <z_nrf_rtc_timer_read>
    449e:	4b0e      	ldr	r3, [pc, #56]	; (44d8 <sys_clock_set_timeout+0x60>)
    44a0:	e9d3 2300 	ldrd	r2, r3, [r3]
    44a4:	1a80      	subs	r0, r0, r2
	/* If we haven't announced for more than half the 24-bit wrap
	 * duration, then force an announce to avoid loss of a wrap
	 * event.  This can happen if new timeouts keep being set
	 * before the existing one triggers the interrupt.
	 */
	if (unannounced >= COUNTER_HALF_SPAN) {
    44a6:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    44aa:	d300      	bcc.n	44ae <sys_clock_set_timeout+0x36>
		ticks = 0;
    44ac:	2400      	movs	r4, #0
	}

	/* Get the cycles from last_count to the tick boundary after
	 * the requested ticks have passed starting now.
	 */
	cyc = ticks * CYC_PER_TICK + 1 + unannounced;
    44ae:	4404      	add	r4, r0
    44b0:	3401      	adds	r4, #1
	cyc = (cyc / CYC_PER_TICK) * CYC_PER_TICK;

	/* Due to elapsed time the calculation above might produce a
	 * duration that laps the counter.  Don't let it.
	 */
	if (cyc > MAX_CYCLES) {
    44b2:	f5b4 0f00 	cmp.w	r4, #8388608	; 0x800000
    44b6:	d300      	bcc.n	44ba <sys_clock_set_timeout+0x42>
		cyc = MAX_CYCLES;
    44b8:	4c06      	ldr	r4, [pc, #24]	; (44d4 <sys_clock_set_timeout+0x5c>)
	}

	uint64_t target_time = cyc + last_count;

	compare_set(0, target_time, sys_clock_timeout_handler, NULL);
    44ba:	2000      	movs	r0, #0
    44bc:	9001      	str	r0, [sp, #4]
    44be:	4907      	ldr	r1, [pc, #28]	; (44dc <sys_clock_set_timeout+0x64>)
    44c0:	9100      	str	r1, [sp, #0]
    44c2:	1912      	adds	r2, r2, r4
    44c4:	f143 0300 	adc.w	r3, r3, #0
    44c8:	f003 f92f 	bl	772a <compare_set>
}
    44cc:	b002      	add	sp, #8
    44ce:	bd10      	pop	{r4, pc}
    44d0:	007ffffe 	.word	0x007ffffe
    44d4:	007fffff 	.word	0x007fffff
    44d8:	200001d8 	.word	0x200001d8
    44dc:	000041c9 	.word	0x000041c9

000044e0 <sys_clock_elapsed>:

uint32_t sys_clock_elapsed(void)
{
    44e0:	b508      	push	{r3, lr}
	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
		return 0;
	}

	return (z_nrf_rtc_timer_read() - last_count) / CYC_PER_TICK;
    44e2:	f7ff feab 	bl	423c <z_nrf_rtc_timer_read>
    44e6:	4b02      	ldr	r3, [pc, #8]	; (44f0 <sys_clock_elapsed+0x10>)
    44e8:	681b      	ldr	r3, [r3, #0]
}
    44ea:	1ac0      	subs	r0, r0, r3
    44ec:	bd08      	pop	{r3, pc}
    44ee:	bf00      	nop
    44f0:	200001d8 	.word	0x200001d8

000044f4 <k_sys_fatal_error_handler>:

extern void sys_arch_reboot(int type);

void k_sys_fatal_error_handler(unsigned int reason,
			       const z_arch_esf_t *esf)
{
    44f4:	b508      	push	{r3, lr}
	z_impl_log_panic();
    44f6:	f7fd f99b 	bl	1830 <z_impl_log_panic>
    44fa:	4b09      	ldr	r3, [pc, #36]	; (4520 <k_sys_fatal_error_handler+0x2c>)
    44fc:	4a09      	ldr	r2, [pc, #36]	; (4524 <k_sys_fatal_error_handler+0x30>)
    44fe:	1a9b      	subs	r3, r3, r2
    4500:	08db      	lsrs	r3, r3, #3
	defined(CONFIG_SPM_SERVICE_NS_HANDLER_FROM_SPM_FAULT)
	z_spm_ns_fatal_error_handler();
#endif

	if (IS_ENABLED(CONFIG_RESET_ON_FATAL_ERROR)) {
		LOG_ERR("Resetting system");
    4502:	f04f 0100 	mov.w	r1, #0
    4506:	2201      	movs	r2, #1
    4508:	f362 0102 	bfi	r1, r2, #0, #3
    450c:	f36f 01c5 	bfc	r1, #3, #3
    4510:	f363 118f 	bfi	r1, r3, #6, #10
    4514:	4804      	ldr	r0, [pc, #16]	; (4528 <k_sys_fatal_error_handler+0x34>)
    4516:	f7fd f95b 	bl	17d0 <log_0>
		sys_arch_reboot(0);
    451a:	2000      	movs	r0, #0
    451c:	f7fe fc7c 	bl	2e18 <sys_arch_reboot>
		for (;;) {
			/* Spin endlessly */
		}
	}

	CODE_UNREACHABLE;
    4520:	000083ac 	.word	0x000083ac
    4524:	0000839c 	.word	0x0000839c
    4528:	00008d34 	.word	0x00008d34

0000452c <nrf52_errata_36>:
         || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\
         || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\
         || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\
         || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\
         || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    452c:	4b03      	ldr	r3, [pc, #12]	; (453c <nrf52_errata_36+0x10>)
    452e:	681b      	ldr	r3, [r3, #0]
                        return true;
                }
            }
        #endif
        #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)
            if (var1 == 0x0D)
    4530:	2b0d      	cmp	r3, #13
    4532:	d001      	beq.n	4538 <nrf52_errata_36+0xc>
                    default:
                        return true;
                }
            }
        #endif
        return false;
    4534:	2000      	movs	r0, #0
    4536:	4770      	bx	lr
                        return true;
    4538:	2001      	movs	r0, #1
    #endif
}
    453a:	4770      	bx	lr
    453c:	10000130 	.word	0x10000130

00004540 <nrf52_errata_66>:
         || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\
         || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\
         || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\
         || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\
         || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    4540:	4b03      	ldr	r3, [pc, #12]	; (4550 <nrf52_errata_66+0x10>)
    4542:	681b      	ldr	r3, [r3, #0]
                        return true;
                }
            }
        #endif
        #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)
            if (var1 == 0x0D)
    4544:	2b0d      	cmp	r3, #13
    4546:	d001      	beq.n	454c <nrf52_errata_66+0xc>
                    default:
                        return true;
                }
            }
        #endif
        return false;
    4548:	2000      	movs	r0, #0
    454a:	4770      	bx	lr
                        return true;
    454c:	2001      	movs	r0, #1
    #endif
}
    454e:	4770      	bx	lr
    4550:	10000130 	.word	0x10000130

00004554 <nrf52_errata_136>:
         || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\
         || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\
         || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\
         || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\
         || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    4554:	4b03      	ldr	r3, [pc, #12]	; (4564 <nrf52_errata_136+0x10>)
    4556:	681b      	ldr	r3, [r3, #0]
                        return true;
                }
            }
        #endif
        #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)
            if (var1 == 0x0D)
    4558:	2b0d      	cmp	r3, #13
    455a:	d001      	beq.n	4560 <nrf52_errata_136+0xc>
                    default:
                        return true;
                }
            }
        #endif
        return false;
    455c:	2000      	movs	r0, #0
    455e:	4770      	bx	lr
                        return true;
    4560:	2001      	movs	r0, #1
    #endif
}
    4562:	4770      	bx	lr
    4564:	10000130 	.word	0x10000130

00004568 <nrf52_errata_249>:
        #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\
         || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\
         || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    4568:	4b06      	ldr	r3, [pc, #24]	; (4584 <nrf52_errata_249+0x1c>)
    456a:	681b      	ldr	r3, [r3, #0]
            uint32_t var2 = *(uint32_t *)0x10000134ul;
    456c:	4a06      	ldr	r2, [pc, #24]	; (4588 <nrf52_errata_249+0x20>)
    456e:	6812      	ldr	r2, [r2, #0]
                        return true;
                }
            }
        #endif
        #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)
            if (var1 == 0x0D)
    4570:	2b0d      	cmp	r3, #13
    4572:	d001      	beq.n	4578 <nrf52_errata_249+0x10>
                    default:
                        return true;
                }
            }
        #endif
        return false;
    4574:	2000      	movs	r0, #0
    4576:	4770      	bx	lr
                switch(var2)
    4578:	2a01      	cmp	r2, #1
    457a:	d801      	bhi.n	4580 <nrf52_errata_249+0x18>
    457c:	2000      	movs	r0, #0
    457e:	4770      	bx	lr
                        return true;
    4580:	2001      	movs	r0, #1
    #endif
}
    4582:	4770      	bx	lr
    4584:	10000130 	.word	0x10000130
    4588:	10000134 	.word	0x10000134

0000458c <nvmc_wait>:

/* -- NVMC utility functions -- */
/* Waits until NVMC is done with the current pending action */
void nvmc_wait(void)
{
    while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
    458c:	4b02      	ldr	r3, [pc, #8]	; (4598 <nvmc_wait+0xc>)
    458e:	f8d3 3400 	ldr.w	r3, [r3, #1024]	; 0x400
    4592:	2b00      	cmp	r3, #0
    4594:	d0fa      	beq.n	458c <nvmc_wait>
}
    4596:	4770      	bx	lr
    4598:	4001e000 	.word	0x4001e000

0000459c <nvmc_config>:

/*  Configure the NVMC to "mode".
    Mode must be an enumerator of field NVMC_CONFIG_WEN */
void nvmc_config(uint32_t mode)
{
    459c:	b508      	push	{r3, lr}
    NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
    459e:	4b03      	ldr	r3, [pc, #12]	; (45ac <nvmc_config+0x10>)
    45a0:	f8c3 0504 	str.w	r0, [r3, #1284]	; 0x504
    nvmc_wait();
    45a4:	f7ff fff2 	bl	458c <nvmc_wait>
}
    45a8:	bd08      	pop	{r3, pc}
    45aa:	bf00      	nop
    45ac:	4001e000 	.word	0x4001e000

000045b0 <SystemCoreClockUpdate>:

void SystemCoreClockUpdate(void)
{
    SystemCoreClock = __SYSTEM_CLOCK_64M;
    45b0:	4b01      	ldr	r3, [pc, #4]	; (45b8 <SystemCoreClockUpdate+0x8>)
    45b2:	4a02      	ldr	r2, [pc, #8]	; (45bc <SystemCoreClockUpdate+0xc>)
    45b4:	601a      	str	r2, [r3, #0]
}
    45b6:	4770      	bx	lr
    45b8:	20000050 	.word	0x20000050
    45bc:	03d09000 	.word	0x03d09000

000045c0 <SystemInit>:

void SystemInit(void)
{
    45c0:	b538      	push	{r3, r4, r5, lr}
    #endif

    #if NRF52_ERRATA_36_ENABLE_WORKAROUND
        /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_36()){
    45c2:	f7ff ffb3 	bl	452c <nrf52_errata_36>
    45c6:	b140      	cbz	r0, 45da <SystemInit+0x1a>
            NRF_CLOCK->EVENTS_DONE = 0;
    45c8:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    45cc:	2200      	movs	r2, #0
    45ce:	f8c3 210c 	str.w	r2, [r3, #268]	; 0x10c
            NRF_CLOCK->EVENTS_CTTO = 0;
    45d2:	f8c3 2110 	str.w	r2, [r3, #272]	; 0x110
            NRF_CLOCK->CTIV = 0;
    45d6:	f8c3 2538 	str.w	r2, [r3, #1336]	; 0x538
    #endif

    #if NRF52_ERRATA_66_ENABLE_WORKAROUND
        /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_66()){
    45da:	f7ff ffb1 	bl	4540 <nrf52_errata_66>
    45de:	2800      	cmp	r0, #0
    45e0:	d046      	beq.n	4670 <SystemInit+0xb0>
            NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
    45e2:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
    45e6:	f8d2 1404 	ldr.w	r1, [r2, #1028]	; 0x404
    45ea:	4b45      	ldr	r3, [pc, #276]	; (4700 <SystemInit+0x140>)
    45ec:	f8c3 1520 	str.w	r1, [r3, #1312]	; 0x520
            NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
    45f0:	f8d2 1408 	ldr.w	r1, [r2, #1032]	; 0x408
    45f4:	f8c3 1524 	str.w	r1, [r3, #1316]	; 0x524
            NRF_TEMP->A2 = NRF_FICR->TEMP.A2;
    45f8:	f8d2 140c 	ldr.w	r1, [r2, #1036]	; 0x40c
    45fc:	f8c3 1528 	str.w	r1, [r3, #1320]	; 0x528
            NRF_TEMP->A3 = NRF_FICR->TEMP.A3;
    4600:	f8d2 1410 	ldr.w	r1, [r2, #1040]	; 0x410
    4604:	f8c3 152c 	str.w	r1, [r3, #1324]	; 0x52c
            NRF_TEMP->A4 = NRF_FICR->TEMP.A4;
    4608:	f8d2 1414 	ldr.w	r1, [r2, #1044]	; 0x414
    460c:	f8c3 1530 	str.w	r1, [r3, #1328]	; 0x530
            NRF_TEMP->A5 = NRF_FICR->TEMP.A5;
    4610:	f8d2 1418 	ldr.w	r1, [r2, #1048]	; 0x418
    4614:	f8c3 1534 	str.w	r1, [r3, #1332]	; 0x534
            NRF_TEMP->B0 = NRF_FICR->TEMP.B0;
    4618:	f8d2 141c 	ldr.w	r1, [r2, #1052]	; 0x41c
    461c:	f8c3 1540 	str.w	r1, [r3, #1344]	; 0x540
            NRF_TEMP->B1 = NRF_FICR->TEMP.B1;
    4620:	f8d2 1420 	ldr.w	r1, [r2, #1056]	; 0x420
    4624:	f8c3 1544 	str.w	r1, [r3, #1348]	; 0x544
            NRF_TEMP->B2 = NRF_FICR->TEMP.B2;
    4628:	f8d2 1424 	ldr.w	r1, [r2, #1060]	; 0x424
    462c:	f8c3 1548 	str.w	r1, [r3, #1352]	; 0x548
            NRF_TEMP->B3 = NRF_FICR->TEMP.B3;
    4630:	f8d2 1428 	ldr.w	r1, [r2, #1064]	; 0x428
    4634:	f8c3 154c 	str.w	r1, [r3, #1356]	; 0x54c
            NRF_TEMP->B4 = NRF_FICR->TEMP.B4;
    4638:	f8d2 142c 	ldr.w	r1, [r2, #1068]	; 0x42c
    463c:	f8c3 1550 	str.w	r1, [r3, #1360]	; 0x550
            NRF_TEMP->B5 = NRF_FICR->TEMP.B5;
    4640:	f8d2 1430 	ldr.w	r1, [r2, #1072]	; 0x430
    4644:	f8c3 1554 	str.w	r1, [r3, #1364]	; 0x554
            NRF_TEMP->T0 = NRF_FICR->TEMP.T0;
    4648:	f8d2 1434 	ldr.w	r1, [r2, #1076]	; 0x434
    464c:	f8c3 1560 	str.w	r1, [r3, #1376]	; 0x560
            NRF_TEMP->T1 = NRF_FICR->TEMP.T1;
    4650:	f8d2 1438 	ldr.w	r1, [r2, #1080]	; 0x438
    4654:	f8c3 1564 	str.w	r1, [r3, #1380]	; 0x564
            NRF_TEMP->T2 = NRF_FICR->TEMP.T2;
    4658:	f8d2 143c 	ldr.w	r1, [r2, #1084]	; 0x43c
    465c:	f8c3 1568 	str.w	r1, [r3, #1384]	; 0x568
            NRF_TEMP->T3 = NRF_FICR->TEMP.T3;
    4660:	f8d2 1440 	ldr.w	r1, [r2, #1088]	; 0x440
    4664:	f8c3 156c 	str.w	r1, [r3, #1388]	; 0x56c
            NRF_TEMP->T4 = NRF_FICR->TEMP.T4;
    4668:	f8d2 2444 	ldr.w	r2, [r2, #1092]	; 0x444
    466c:	f8c3 2570 	str.w	r2, [r3, #1392]	; 0x570
    #endif

    #if NRF52_ERRATA_136_ENABLE_WORKAROUND
        /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_136()){
    4670:	f7ff ff70 	bl	4554 <nrf52_errata_136>
    4674:	b160      	cbz	r0, 4690 <SystemInit+0xd0>
            if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){
    4676:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    467a:	f8d3 3400 	ldr.w	r3, [r3, #1024]	; 0x400
    467e:	f013 0f01 	tst.w	r3, #1
    4682:	d005      	beq.n	4690 <SystemInit+0xd0>
                NRF_POWER->RESETREAS =  ~POWER_RESETREAS_RESETPIN_Msk;
    4684:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    4688:	f06f 0201 	mvn.w	r2, #1
    468c:	f8c3 2400 	str.w	r2, [r3, #1024]	; 0x400
            {
                /* Prevent processor from unlocking APPROTECT soft branch after this point. */
                NRF_APPROTECT->FORCEPROTECT = APPROTECT_FORCEPROTECT_FORCEPROTECT_Force;
            }
        #else
            if (nrf52_errata_249())
    4690:	f7ff ff6a 	bl	4568 <nrf52_errata_249>
    4694:	b138      	cbz	r0, 46a6 <SystemInit+0xe6>
            {
                /* Load APPROTECT soft branch from UICR.
                   If UICR->APPROTECT is disabled, POWER->APPROTECT will be disabled. */
                NRF_APPROTECT->DISABLE = NRF_UICR->APPROTECT;
    4696:	f04f 2310 	mov.w	r3, #268439552	; 0x10001000
    469a:	f8d3 2208 	ldr.w	r2, [r3, #520]	; 0x208
    469e:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    46a2:	f8c3 2558 	str.w	r2, [r3, #1368]	; 0x558

    /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
      defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
      reserved for PinReset and not available as normal GPIO. */
    #if defined (CONFIG_GPIO_AS_PINRESET)
        if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
    46a6:	f04f 2310 	mov.w	r3, #268439552	; 0x10001000
    46aa:	f8d3 3200 	ldr.w	r3, [r3, #512]	; 0x200
    46ae:	2b00      	cmp	r3, #0
    46b0:	db08      	blt.n	46c4 <SystemInit+0x104>
            ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
    46b2:	f04f 2310 	mov.w	r3, #268439552	; 0x10001000
    46b6:	f8d3 3204 	ldr.w	r3, [r3, #516]	; 0x204
        if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
    46ba:	2b00      	cmp	r3, #0
    46bc:	db02      	blt.n	46c4 <SystemInit+0x104>
            nvmc_config(NVMC_CONFIG_WEN_Ren);
            NVIC_SystemReset();
        }
    #endif

    SystemCoreClockUpdate();
    46be:	f7ff ff77 	bl	45b0 <SystemCoreClockUpdate>
}
    46c2:	bd38      	pop	{r3, r4, r5, pc}
            nvmc_config(NVMC_CONFIG_WEN_Wen);
    46c4:	2001      	movs	r0, #1
    46c6:	f7ff ff69 	bl	459c <nvmc_config>
            NRF_UICR->PSELRESET[0] = RESET_PIN;
    46ca:	f04f 2410 	mov.w	r4, #268439552	; 0x10001000
    46ce:	2512      	movs	r5, #18
    46d0:	f8c4 5200 	str.w	r5, [r4, #512]	; 0x200
            nvmc_wait();
    46d4:	f7ff ff5a 	bl	458c <nvmc_wait>
            NRF_UICR->PSELRESET[1] = RESET_PIN;
    46d8:	f8c4 5204 	str.w	r5, [r4, #516]	; 0x204
            nvmc_wait();
    46dc:	f7ff ff56 	bl	458c <nvmc_wait>
            nvmc_config(NVMC_CONFIG_WEN_Ren);
    46e0:	2000      	movs	r0, #0
    46e2:	f7ff ff5b 	bl	459c <nvmc_config>
  __ASM volatile ("dsb 0xF":::"memory");
    46e6:	f3bf 8f4f 	dsb	sy
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    46ea:	4906      	ldr	r1, [pc, #24]	; (4704 <SystemInit+0x144>)
    46ec:	68ca      	ldr	r2, [r1, #12]
    46ee:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    46f2:	4b05      	ldr	r3, [pc, #20]	; (4708 <SystemInit+0x148>)
    46f4:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    46f6:	60cb      	str	r3, [r1, #12]
    46f8:	f3bf 8f4f 	dsb	sy
    __NOP();
    46fc:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    46fe:	e7fd      	b.n	46fc <SystemInit+0x13c>
    4700:	4000c000 	.word	0x4000c000
    4704:	e000ed00 	.word	0xe000ed00
    4708:	05fa0004 	.word	0x05fa0004

0000470c <nrfx_clock_init>:
nrfx_err_t nrfx_clock_init(nrfx_clock_event_handler_t event_handler)
{
    NRFX_ASSERT(event_handler);

    nrfx_err_t err_code = NRFX_SUCCESS;
    if (m_clock_cb.module_initialized)
    470c:	4b06      	ldr	r3, [pc, #24]	; (4728 <nrfx_clock_init+0x1c>)
    470e:	791b      	ldrb	r3, [r3, #4]
    4710:	b93b      	cbnz	r3, 4722 <nrfx_clock_init+0x16>
        err_code = NRFX_ERROR_ALREADY_INITIALIZED;
    }
    else
    {
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
        m_clock_cb.cal_state = CAL_STATE_IDLE;
    4712:	4b05      	ldr	r3, [pc, #20]	; (4728 <nrfx_clock_init+0x1c>)
    4714:	2200      	movs	r2, #0
    4716:	715a      	strb	r2, [r3, #5]
#endif
        m_clock_cb.event_handler = event_handler;
    4718:	6018      	str	r0, [r3, #0]
        m_clock_cb.module_initialized = true;
    471a:	2201      	movs	r2, #1
    471c:	711a      	strb	r2, [r3, #4]
    nrfx_err_t err_code = NRFX_SUCCESS;
    471e:	4803      	ldr	r0, [pc, #12]	; (472c <nrfx_clock_init+0x20>)
    4720:	4770      	bx	lr
        err_code = NRFX_ERROR_ALREADY_INITIALIZED;
    4722:	4803      	ldr	r0, [pc, #12]	; (4730 <nrfx_clock_init+0x24>)
#endif
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    4724:	4770      	bx	lr
    4726:	bf00      	nop
    4728:	200005d4 	.word	0x200005d4
    472c:	0bad0000 	.word	0x0bad0000
    4730:	0bad000c 	.word	0x0bad000c

00004734 <nrfx_clock_start>:
}

void nrfx_clock_start(nrf_clock_domain_t domain)
{
    NRFX_ASSERT(m_clock_cb.module_initialized);
    switch (domain)
    4734:	b110      	cbz	r0, 473c <nrfx_clock_start+0x8>
    4736:	2801      	cmp	r0, #1
    4738:	d00d      	beq.n	4756 <nrfx_clock_start+0x22>
    473a:	4770      	bx	lr
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    473c:	4b0b      	ldr	r3, [pc, #44]	; (476c <nrfx_clock_start+0x38>)
    473e:	2200      	movs	r2, #0
    4740:	601a      	str	r2, [r3, #0]
    4742:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENSET = mask;
    4744:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    4748:	2202      	movs	r2, #2
    474a:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    474e:	3308      	adds	r3, #8
    4750:	2201      	movs	r2, #1
    4752:	601a      	str	r2, [r3, #0]
}
    4754:	4770      	bx	lr
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    4756:	4b06      	ldr	r3, [pc, #24]	; (4770 <nrfx_clock_start+0x3c>)
    4758:	2200      	movs	r2, #0
    475a:	601a      	str	r2, [r3, #0]
    475c:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENSET = mask;
    475e:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    4762:	2201      	movs	r2, #1
    4764:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    4768:	601a      	str	r2, [r3, #0]
#endif
        default:
            NRFX_ASSERT(0);
            break;
    }
}
    476a:	4770      	bx	lr
    476c:	40000104 	.word	0x40000104
    4770:	40000100 	.word	0x40000100

00004774 <nrfx_clock_stop>:

void nrfx_clock_stop(nrf_clock_domain_t domain)
{
    4774:	b530      	push	{r4, r5, lr}
    4776:	b083      	sub	sp, #12
    NRFX_ASSERT(m_clock_cb.module_initialized);
    switch (domain)
    4778:	4604      	mov	r4, r0
    477a:	b118      	cbz	r0, 4784 <nrfx_clock_stop+0x10>
    477c:	2801      	cmp	r0, #1
    477e:	d013      	beq.n	47a8 <nrfx_clock_stop+0x34>
    if (domain == NRF_CLOCK_DOMAIN_HFCLK)
    {
            m_clock_cb.hfclk_started = false;
    }
#endif
}
    4780:	b003      	add	sp, #12
    4782:	bd30      	pop	{r4, r5, pc}
    p_reg->INTENCLR = mask;
    4784:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    4788:	2202      	movs	r2, #2
    478a:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    478e:	f503 7382 	add.w	r3, r3, #260	; 0x104
    4792:	2200      	movs	r2, #0
    4794:	601a      	str	r2, [r3, #0]
    4796:	681b      	ldr	r3, [r3, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    4798:	4b37      	ldr	r3, [pc, #220]	; (4878 <nrfx_clock_stop+0x104>)
    479a:	2201      	movs	r2, #1
    479c:	601a      	str	r2, [r3, #0]
    if (domain == NRF_CLOCK_DOMAIN_HFCLK)
    479e:	2c01      	cmp	r4, #1
    47a0:	d00f      	beq.n	47c2 <nrfx_clock_stop+0x4e>
        NRFX_WAIT_FOR(!nrfx_clock_is_running(domain, NULL), 10000, 1, stopped);
    47a2:	f242 7510 	movw	r5, #10000	; 0x2710
    47a6:	e053      	b.n	4850 <nrfx_clock_stop+0xdc>
    p_reg->INTENCLR = mask;
    47a8:	2301      	movs	r3, #1
    47aa:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    47ae:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    47b2:	f502 7280 	add.w	r2, r2, #256	; 0x100
    47b6:	2100      	movs	r1, #0
    47b8:	6011      	str	r1, [r2, #0]
    47ba:	6812      	ldr	r2, [r2, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    47bc:	4a2f      	ldr	r2, [pc, #188]	; (487c <nrfx_clock_stop+0x108>)
    47be:	6013      	str	r3, [r2, #0]
}
    47c0:	e7ed      	b.n	479e <nrfx_clock_stop+0x2a>
        nrf_clock_hfclk_t clk_src = NRF_CLOCK_HFCLK_HIGH_ACCURACY;
    47c2:	2301      	movs	r3, #1
    47c4:	f88d 3007 	strb.w	r3, [sp, #7]
        NRFX_WAIT_FOR((!nrfx_clock_is_running(domain, &clk_src) ||
    47c8:	f242 7510 	movw	r5, #10000	; 0x2710
    47cc:	e018      	b.n	4800 <nrfx_clock_stop+0x8c>
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    47ce:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    47d2:	f8d2 3418 	ldr.w	r3, [r2, #1048]	; 0x418
                                        >> CLOCK_LFCLKSTAT_SRC_Pos);
    47d6:	f003 0303 	and.w	r3, r3, #3
                (*(nrf_clock_lfclk_t *)p_clk_src) =
    47da:	f8cd 3007 	str.w	r3, [sp, #7]
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    47de:	f8d2 3418 	ldr.w	r3, [r2, #1048]	; 0x418
    47e2:	f413 3f80 	tst.w	r3, #65536	; 0x10000
    47e6:	d120      	bne.n	482a <nrfx_clock_stop+0xb6>
    return false;
    47e8:	2300      	movs	r3, #0
    47ea:	2b00      	cmp	r3, #0
    47ec:	d0c8      	beq.n	4780 <nrfx_clock_stop+0xc>
    47ee:	f89d 3007 	ldrb.w	r3, [sp, #7]
    47f2:	2b01      	cmp	r3, #1
    47f4:	d1c4      	bne.n	4780 <nrfx_clock_stop+0xc>
    47f6:	2001      	movs	r0, #1
    47f8:	f002 ffb7 	bl	776a <nrfx_busy_wait>
    47fc:	3d01      	subs	r5, #1
    47fe:	d0bf      	beq.n	4780 <nrfx_clock_stop+0xc>
    switch (domain)
    4800:	2c00      	cmp	r4, #0
    4802:	d0e4      	beq.n	47ce <nrfx_clock_stop+0x5a>
    4804:	2c01      	cmp	r4, #1
    4806:	d001      	beq.n	480c <nrfx_clock_stop+0x98>
    4808:	2300      	movs	r3, #0
    480a:	e7ee      	b.n	47ea <nrfx_clock_stop+0x76>
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    480c:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    4810:	f8d2 340c 	ldr.w	r3, [r2, #1036]	; 0x40c
    4814:	f003 0301 	and.w	r3, r3, #1
                (*(nrf_clock_hfclk_t *)p_clk_src) =
    4818:	f88d 3007 	strb.w	r3, [sp, #7]
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    481c:	f8d2 340c 	ldr.w	r3, [r2, #1036]	; 0x40c
    4820:	f413 3f80 	tst.w	r3, #65536	; 0x10000
    4824:	d103      	bne.n	482e <nrfx_clock_stop+0xba>
    return false;
    4826:	2300      	movs	r3, #0
    4828:	e7df      	b.n	47ea <nrfx_clock_stop+0x76>
                return true;
    482a:	2301      	movs	r3, #1
    482c:	e7dd      	b.n	47ea <nrfx_clock_stop+0x76>
                return true;
    482e:	2301      	movs	r3, #1
    4830:	e7db      	b.n	47ea <nrfx_clock_stop+0x76>
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    4832:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    4836:	f8d3 3418 	ldr.w	r3, [r3, #1048]	; 0x418
    483a:	f413 3f80 	tst.w	r3, #65536	; 0x10000
    483e:	d116      	bne.n	486e <nrfx_clock_stop+0xfa>
    return false;
    4840:	2300      	movs	r3, #0
        NRFX_WAIT_FOR(!nrfx_clock_is_running(domain, NULL), 10000, 1, stopped);
    4842:	2b00      	cmp	r3, #0
    4844:	d09c      	beq.n	4780 <nrfx_clock_stop+0xc>
    4846:	2001      	movs	r0, #1
    4848:	f002 ff8f 	bl	776a <nrfx_busy_wait>
    484c:	3d01      	subs	r5, #1
    484e:	d097      	beq.n	4780 <nrfx_clock_stop+0xc>
    switch (domain)
    4850:	2c00      	cmp	r4, #0
    4852:	d0ee      	beq.n	4832 <nrfx_clock_stop+0xbe>
    4854:	2c01      	cmp	r4, #1
    4856:	d001      	beq.n	485c <nrfx_clock_stop+0xe8>
    4858:	2300      	movs	r3, #0
    485a:	e7f2      	b.n	4842 <nrfx_clock_stop+0xce>
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    485c:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    4860:	f8d3 340c 	ldr.w	r3, [r3, #1036]	; 0x40c
    4864:	f413 3f80 	tst.w	r3, #65536	; 0x10000
    4868:	d103      	bne.n	4872 <nrfx_clock_stop+0xfe>
    return false;
    486a:	2300      	movs	r3, #0
    486c:	e7e9      	b.n	4842 <nrfx_clock_stop+0xce>
                return true;
    486e:	2301      	movs	r3, #1
    4870:	e7e7      	b.n	4842 <nrfx_clock_stop+0xce>
                return true;
    4872:	2301      	movs	r3, #1
    4874:	e7e5      	b.n	4842 <nrfx_clock_stop+0xce>
    4876:	bf00      	nop
    4878:	4000000c 	.word	0x4000000c
    487c:	40000004 	.word	0x40000004

00004880 <nrfx_clock_calibration_start>:
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    4880:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    4884:	f8d2 340c 	ldr.w	r3, [r2, #1036]	; 0x40c
    4888:	f003 0301 	and.w	r3, r3, #1
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    488c:	f8d2 240c 	ldr.w	r2, [r2, #1036]	; 0x40c
    4890:	f412 3f80 	tst.w	r2, #65536	; 0x10000
    4894:	d104      	bne.n	48a0 <nrfx_clock_calibration_start+0x20>
    return false;
    4896:	2200      	movs	r2, #0
{
    nrfx_err_t err_code = NRFX_SUCCESS;

#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
    nrf_clock_hfclk_t clk_src;
    if (!nrfx_clock_is_running(NRF_CLOCK_DOMAIN_HFCLK, &clk_src))
    4898:	b302      	cbz	r2, 48dc <nrfx_clock_calibration_start+0x5c>
    {
        return NRFX_ERROR_INVALID_STATE;
    }

    if (clk_src != NRF_CLOCK_HFCLK_HIGH_ACCURACY)
    489a:	b91b      	cbnz	r3, 48a4 <nrfx_clock_calibration_start+0x24>
    {
        return NRFX_ERROR_INVALID_STATE;
    489c:	4812      	ldr	r0, [pc, #72]	; (48e8 <nrfx_clock_calibration_start+0x68>)
    489e:	4770      	bx	lr
                return true;
    48a0:	2201      	movs	r2, #1
    48a2:	e7f9      	b.n	4898 <nrfx_clock_calibration_start+0x18>
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    48a4:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    48a8:	f8d3 3418 	ldr.w	r3, [r3, #1048]	; 0x418
    48ac:	f413 3f80 	tst.w	r3, #65536	; 0x10000
    48b0:	d100      	bne.n	48b4 <nrfx_clock_calibration_start+0x34>
    return false;
    48b2:	2200      	movs	r2, #0
    }

    if (!nrfx_clock_is_running(NRF_CLOCK_DOMAIN_LFCLK, NULL))
    48b4:	b1a2      	cbz	r2, 48e0 <nrfx_clock_calibration_start+0x60>
    {
        return NRFX_ERROR_INVALID_STATE;
    }

    if (m_clock_cb.cal_state == CAL_STATE_IDLE)
    48b6:	4b0d      	ldr	r3, [pc, #52]	; (48ec <nrfx_clock_calibration_start+0x6c>)
    48b8:	795b      	ldrb	r3, [r3, #5]
    48ba:	b99b      	cbnz	r3, 48e4 <nrfx_clock_calibration_start+0x64>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    48bc:	4b0c      	ldr	r3, [pc, #48]	; (48f0 <nrfx_clock_calibration_start+0x70>)
    48be:	2200      	movs	r2, #0
    48c0:	601a      	str	r2, [r3, #0]
    48c2:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENSET = mask;
    48c4:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    48c8:	2208      	movs	r2, #8
    48ca:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    {
        nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_DONE);
        nrf_clock_int_enable(NRF_CLOCK, NRF_CLOCK_INT_DONE_MASK);
        m_clock_cb.cal_state = CAL_STATE_CAL;
    48ce:	2301      	movs	r3, #1
    48d0:	4a06      	ldr	r2, [pc, #24]	; (48ec <nrfx_clock_calibration_start+0x6c>)
    48d2:	7153      	strb	r3, [r2, #5]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    48d4:	4a07      	ldr	r2, [pc, #28]	; (48f4 <nrfx_clock_calibration_start+0x74>)
    48d6:	6013      	str	r3, [r2, #0]
    nrfx_err_t err_code = NRFX_SUCCESS;
    48d8:	4807      	ldr	r0, [pc, #28]	; (48f8 <nrfx_clock_calibration_start+0x78>)
}
    48da:	4770      	bx	lr
        return NRFX_ERROR_INVALID_STATE;
    48dc:	4802      	ldr	r0, [pc, #8]	; (48e8 <nrfx_clock_calibration_start+0x68>)
    48de:	4770      	bx	lr
        return NRFX_ERROR_INVALID_STATE;
    48e0:	4801      	ldr	r0, [pc, #4]	; (48e8 <nrfx_clock_calibration_start+0x68>)
    48e2:	4770      	bx	lr
#endif
        nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_CAL);
    }
    else
    {
        err_code = NRFX_ERROR_BUSY;
    48e4:	4805      	ldr	r0, [pc, #20]	; (48fc <nrfx_clock_calibration_start+0x7c>)

    NRFX_LOG_WARNING("Function: %s, error code: %s.",
                     __func__,
                     NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    48e6:	4770      	bx	lr
    48e8:	0bad0005 	.word	0x0bad0005
    48ec:	200005d4 	.word	0x200005d4
    48f0:	4000010c 	.word	0x4000010c
    48f4:	40000010 	.word	0x40000010
    48f8:	0bad0000 	.word	0x0bad0000
    48fc:	0bad000b 	.word	0x0bad000b

00004900 <nrfx_power_clock_irq_handler>:
    }
}
#endif

void nrfx_clock_irq_handler(void)
{
    4900:	b508      	push	{r3, lr}
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    4902:	4b20      	ldr	r3, [pc, #128]	; (4984 <nrfx_power_clock_irq_handler+0x84>)
    4904:	681b      	ldr	r3, [r3, #0]
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED))
    4906:	b15b      	cbz	r3, 4920 <nrfx_power_clock_irq_handler+0x20>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    4908:	4b1e      	ldr	r3, [pc, #120]	; (4984 <nrfx_power_clock_irq_handler+0x84>)
    490a:	2000      	movs	r0, #0
    490c:	6018      	str	r0, [r3, #0]
    490e:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENCLR = mask;
    4910:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    4914:	2201      	movs	r2, #1
    4916:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
        {
            m_clock_cb.hfclk_started = true;
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
        }
#else
        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
    491a:	4b1b      	ldr	r3, [pc, #108]	; (4988 <nrfx_power_clock_irq_handler+0x88>)
    491c:	681b      	ldr	r3, [r3, #0]
    491e:	4798      	blx	r3
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    4920:	4b1a      	ldr	r3, [pc, #104]	; (498c <nrfx_power_clock_irq_handler+0x8c>)
    4922:	681b      	ldr	r3, [r3, #0]
#endif
    }
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED))
    4924:	b163      	cbz	r3, 4940 <nrfx_power_clock_irq_handler+0x40>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    4926:	4b19      	ldr	r3, [pc, #100]	; (498c <nrfx_power_clock_irq_handler+0x8c>)
    4928:	2200      	movs	r2, #0
    492a:	601a      	str	r2, [r3, #0]
    492c:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENCLR = mask;
    492e:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    4932:	2202      	movs	r2, #2
    4934:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
        else
#endif
        {
            // After the LF clock external source start invoke user callback.
            nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_LF_STARTED_MASK);
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    4938:	4b13      	ldr	r3, [pc, #76]	; (4988 <nrfx_power_clock_irq_handler+0x88>)
    493a:	681b      	ldr	r3, [r3, #0]
    493c:	2001      	movs	r0, #1
    493e:	4798      	blx	r3
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    4940:	4b13      	ldr	r3, [pc, #76]	; (4990 <nrfx_power_clock_irq_handler+0x90>)
    4942:	681b      	ldr	r3, [r3, #0]
        }
    }

#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
#if NRF_CLOCK_HAS_CALIBRATION_TIMER
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_CTTO))
    4944:	b163      	cbz	r3, 4960 <nrfx_power_clock_irq_handler+0x60>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    4946:	4b12      	ldr	r3, [pc, #72]	; (4990 <nrfx_power_clock_irq_handler+0x90>)
    4948:	2200      	movs	r2, #0
    494a:	601a      	str	r2, [r3, #0]
    494c:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENCLR = mask;
    494e:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    4952:	2210      	movs	r2, #16
    4954:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    {
        nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_CTTO);
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_CTTO");
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_CTTO_MASK);

        m_clock_cb.event_handler(NRFX_CLOCK_EVT_CTTO);
    4958:	4b0b      	ldr	r3, [pc, #44]	; (4988 <nrfx_power_clock_irq_handler+0x88>)
    495a:	681b      	ldr	r3, [r3, #0]
    495c:	2002      	movs	r0, #2
    495e:	4798      	blx	r3
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    4960:	4b0c      	ldr	r3, [pc, #48]	; (4994 <nrfx_power_clock_irq_handler+0x94>)
    4962:	681b      	ldr	r3, [r3, #0]
    }
#endif // NRF_CLOCK_HAS_CALIBRATION_TIMER

    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_DONE))
    4964:	b16b      	cbz	r3, 4982 <nrfx_power_clock_irq_handler+0x82>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    4966:	4b0b      	ldr	r3, [pc, #44]	; (4994 <nrfx_power_clock_irq_handler+0x94>)
    4968:	2200      	movs	r2, #0
    496a:	601a      	str	r2, [r3, #0]
    496c:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENCLR = mask;
    496e:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    4972:	2108      	movs	r1, #8
    4974:	f8c3 1308 	str.w	r1, [r3, #776]	; 0x308
        *(volatile uint32_t *)0x40000C34 = 0x00000000;
#endif
        nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_DONE);
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_DONE");
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_DONE_MASK);
        m_clock_cb.cal_state = CAL_STATE_IDLE;
    4978:	4b03      	ldr	r3, [pc, #12]	; (4988 <nrfx_power_clock_irq_handler+0x88>)
    497a:	715a      	strb	r2, [r3, #5]
        m_clock_cb.event_handler(NRFX_CLOCK_EVT_CAL_DONE);
    497c:	681b      	ldr	r3, [r3, #0]
    497e:	2003      	movs	r0, #3
    4980:	4798      	blx	r3
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF192M_STARTED_MASK);

        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK192M_STARTED);
    }
#endif
}
    4982:	bd08      	pop	{r3, pc}
    4984:	40000100 	.word	0x40000100
    4988:	200005d4 	.word	0x200005d4
    498c:	40000104 	.word	0x40000104
    4990:	40000110 	.word	0x40000110
    4994:	4000010c 	.word	0x4000010c

00004998 <is_allocated_channel>:
    NRFX_LOG_INFO("Uninitialized.");
}

static bool is_allocated_channel(uint8_t index)
{
    return m_cb.allocated_channels_mask & (1UL << index);
    4998:	4b04      	ldr	r3, [pc, #16]	; (49ac <is_allocated_channel+0x14>)
    499a:	6d9a      	ldr	r2, [r3, #88]	; 0x58
    499c:	2301      	movs	r3, #1
    499e:	4083      	lsls	r3, r0
    49a0:	421a      	tst	r2, r3
}
    49a2:	bf14      	ite	ne
    49a4:	2001      	movne	r0, #1
    49a6:	2000      	moveq	r0, #0
    49a8:	4770      	bx	lr
    49aa:	bf00      	nop
    49ac:	200005dc 	.word	0x200005dc

000049b0 <channel_allocated_set>:
    return NRFX_GPIOTE_APP_CHANNELS_MASK & (1UL << index);
}

static void channel_allocated_set(uint8_t index)
{
    m_cb.allocated_channels_mask |= (1UL << index);
    49b0:	2301      	movs	r3, #1
    49b2:	fa03 f000 	lsl.w	r0, r3, r0
    49b6:	4a02      	ldr	r2, [pc, #8]	; (49c0 <channel_allocated_set+0x10>)
    49b8:	6d93      	ldr	r3, [r2, #88]	; 0x58
    49ba:	4303      	orrs	r3, r0
    49bc:	6593      	str	r3, [r2, #88]	; 0x58
}
    49be:	4770      	bx	lr
    49c0:	200005dc 	.word	0x200005dc

000049c4 <channel_allocated_clr>:

static void channel_allocated_clr(uint8_t index)
{
    m_cb.allocated_channels_mask &= ~(1UL << index);
    49c4:	2301      	movs	r3, #1
    49c6:	fa03 f000 	lsl.w	r0, r3, r0
    49ca:	4a03      	ldr	r2, [pc, #12]	; (49d8 <channel_allocated_clr+0x14>)
    49cc:	6d93      	ldr	r3, [r2, #88]	; 0x58
    49ce:	ea23 0300 	bic.w	r3, r3, r0
    49d2:	6593      	str	r3, [r2, #88]	; 0x58
}
    49d4:	4770      	bx	lr
    49d6:	bf00      	nop
    49d8:	200005dc 	.word	0x200005dc

000049dc <nrfx_gpiote_channel_free>:

nrfx_err_t nrfx_gpiote_channel_free(uint8_t channel)
{
    49dc:	b538      	push	{r3, r4, r5, lr}
    49de:	4604      	mov	r4, r0
    nrfx_err_t err_code = NRFX_SUCCESS;

    if (!is_app_channel(channel))
    49e0:	f002 fed5 	bl	778e <is_app_channel>
    49e4:	b908      	cbnz	r0, 49ea <nrfx_gpiote_channel_free+0xe>
    {
        err_code = NRFX_ERROR_INVALID_PARAM;
    49e6:	4809      	ldr	r0, [pc, #36]	; (4a0c <nrfx_gpiote_channel_free+0x30>)
        NRFX_CRITICAL_SECTION_EXIT();
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    49e8:	bd38      	pop	{r3, r4, r5, pc}
	__asm__ volatile(
    49ea:	f04f 0320 	mov.w	r3, #32
    49ee:	f3ef 8511 	mrs	r5, BASEPRI
    49f2:	f383 8812 	msr	BASEPRI_MAX, r3
    49f6:	f3bf 8f6f 	isb	sy
        channel_allocated_clr(channel);
    49fa:	4620      	mov	r0, r4
    49fc:	f7ff ffe2 	bl	49c4 <channel_allocated_clr>
	__asm__ volatile(
    4a00:	f385 8811 	msr	BASEPRI, r5
    4a04:	f3bf 8f6f 	isb	sy
    nrfx_err_t err_code = NRFX_SUCCESS;
    4a08:	4801      	ldr	r0, [pc, #4]	; (4a10 <nrfx_gpiote_channel_free+0x34>)
}
    4a0a:	e7ed      	b.n	49e8 <nrfx_gpiote_channel_free+0xc>
    4a0c:	0bad0004 	.word	0x0bad0004
    4a10:	0bad0000 	.word	0x0bad0000

00004a14 <nrfx_gpiote_channel_alloc>:

nrfx_err_t nrfx_gpiote_channel_alloc(uint8_t * p_channel)
{
    4a14:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    4a18:	4680      	mov	r8, r0
    nrfx_err_t err_code = NRFX_ERROR_NO_MEM;
    uint32_t mask = NRFX_GPIOTE_APP_CHANNELS_MASK;

    for (uint8_t ch_idx = 0; mask != 0; ch_idx++)
    4a1a:	2400      	movs	r4, #0
    uint32_t mask = NRFX_GPIOTE_APP_CHANNELS_MASK;
    4a1c:	25ff      	movs	r5, #255	; 0xff
    nrfx_err_t err_code = NRFX_ERROR_NO_MEM;
    4a1e:	4f17      	ldr	r7, [pc, #92]	; (4a7c <nrfx_gpiote_channel_alloc+0x68>)
    for (uint8_t ch_idx = 0; mask != 0; ch_idx++)
    4a20:	e013      	b.n	4a4a <nrfx_gpiote_channel_alloc+0x36>
    {
        NRFX_CRITICAL_SECTION_ENTER();
        if ((mask & (1UL << ch_idx)) && (!is_allocated_channel(ch_idx)))
        {
            channel_allocated_set(ch_idx);
    4a22:	4620      	mov	r0, r4
    4a24:	f7ff ffc4 	bl	49b0 <channel_allocated_set>
            *p_channel = ch_idx;
    4a28:	f888 4000 	strb.w	r4, [r8]
            err_code = NRFX_SUCCESS;
    4a2c:	4f14      	ldr	r7, [pc, #80]	; (4a80 <nrfx_gpiote_channel_alloc+0x6c>)
	__asm__ volatile(
    4a2e:	f386 8811 	msr	BASEPRI, r6
    4a32:	f3bf 8f6f 	isb	sy
        }
        NRFX_CRITICAL_SECTION_EXIT();

        if (err_code == NRFX_SUCCESS)
    4a36:	4b12      	ldr	r3, [pc, #72]	; (4a80 <nrfx_gpiote_channel_alloc+0x6c>)
    4a38:	429f      	cmp	r7, r3
    4a3a:	d01b      	beq.n	4a74 <nrfx_gpiote_channel_alloc+0x60>
        {
            NRFX_LOG_INFO("Allocated channel: %d.", ch_idx);
            break;
        }

        mask &= ~(1UL << ch_idx);
    4a3c:	2301      	movs	r3, #1
    4a3e:	fa03 f309 	lsl.w	r3, r3, r9
    4a42:	ea25 0503 	bic.w	r5, r5, r3
    for (uint8_t ch_idx = 0; mask != 0; ch_idx++)
    4a46:	3401      	adds	r4, #1
    4a48:	b2e4      	uxtb	r4, r4
    4a4a:	b19d      	cbz	r5, 4a74 <nrfx_gpiote_channel_alloc+0x60>
	__asm__ volatile(
    4a4c:	f04f 0320 	mov.w	r3, #32
    4a50:	f3ef 8611 	mrs	r6, BASEPRI
    4a54:	f383 8812 	msr	BASEPRI_MAX, r3
    4a58:	f3bf 8f6f 	isb	sy
        if ((mask & (1UL << ch_idx)) && (!is_allocated_channel(ch_idx)))
    4a5c:	46a1      	mov	r9, r4
    4a5e:	fa25 f304 	lsr.w	r3, r5, r4
    4a62:	f013 0f01 	tst.w	r3, #1
    4a66:	d0e2      	beq.n	4a2e <nrfx_gpiote_channel_alloc+0x1a>
    4a68:	4620      	mov	r0, r4
    4a6a:	f7ff ff95 	bl	4998 <is_allocated_channel>
    4a6e:	2800      	cmp	r0, #0
    4a70:	d1dd      	bne.n	4a2e <nrfx_gpiote_channel_alloc+0x1a>
    4a72:	e7d6      	b.n	4a22 <nrfx_gpiote_channel_alloc+0xe>
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    4a74:	4638      	mov	r0, r7
    4a76:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
    4a7a:	bf00      	nop
    4a7c:	0bad0002 	.word	0x0bad0002
    4a80:	0bad0000 	.word	0x0bad0000

00004a84 <twi_process_error>:
} twi_control_block_t;

static twi_control_block_t m_cb[NRFX_TWI_ENABLED_COUNT];

static nrfx_err_t twi_process_error(uint32_t errorsrc)
{
    4a84:	4603      	mov	r3, r0
    nrfx_err_t ret = NRFX_ERROR_INTERNAL;

    if (errorsrc & NRF_TWI_ERROR_OVERRUN)
    4a86:	f010 0f01 	tst.w	r0, #1
    4a8a:	d108      	bne.n	4a9e <twi_process_error+0x1a>
    nrfx_err_t ret = NRFX_ERROR_INTERNAL;
    4a8c:	4806      	ldr	r0, [pc, #24]	; (4aa8 <twi_process_error+0x24>)
    {
        ret = NRFX_ERROR_DRV_TWI_ERR_OVERRUN;
    }

    if (errorsrc & NRF_TWI_ERROR_ADDRESS_NACK)
    4a8e:	f013 0f02 	tst.w	r3, #2
    4a92:	d000      	beq.n	4a96 <twi_process_error+0x12>
    {
        ret = NRFX_ERROR_DRV_TWI_ERR_ANACK;
    4a94:	4805      	ldr	r0, [pc, #20]	; (4aac <twi_process_error+0x28>)
    }

    if (errorsrc & NRF_TWI_ERROR_DATA_NACK)
    4a96:	f013 0f04 	tst.w	r3, #4
    4a9a:	d102      	bne.n	4aa2 <twi_process_error+0x1e>
    {
        ret = NRFX_ERROR_DRV_TWI_ERR_DNACK;
    }

    return ret;
}
    4a9c:	4770      	bx	lr
        ret = NRFX_ERROR_DRV_TWI_ERR_OVERRUN;
    4a9e:	4804      	ldr	r0, [pc, #16]	; (4ab0 <twi_process_error+0x2c>)
    4aa0:	e7f5      	b.n	4a8e <twi_process_error+0xa>
        ret = NRFX_ERROR_DRV_TWI_ERR_DNACK;
    4aa2:	4804      	ldr	r0, [pc, #16]	; (4ab4 <twi_process_error+0x30>)
    return ret;
    4aa4:	e7fa      	b.n	4a9c <twi_process_error+0x18>
    4aa6:	bf00      	nop
    4aa8:	0bad0001 	.word	0x0bad0001
    4aac:	0bae0001 	.word	0x0bae0001
    4ab0:	0bae0000 	.word	0x0bae0000
    4ab4:	0bae0002 	.word	0x0bae0002

00004ab8 <twi_tx_start_transfer>:
    return true;
}

static nrfx_err_t twi_tx_start_transfer(NRF_TWI_Type        * p_twi,
                                        twi_control_block_t * p_cb)
{
    4ab8:	b530      	push	{r4, r5, lr}
    4aba:	b083      	sub	sp, #12
    4abc:	4604      	mov	r4, r0
    4abe:	460d      	mov	r5, r1
    nrfx_err_t ret_code = NRFX_SUCCESS;
    volatile int32_t hw_timeout;

    hw_timeout = HW_TIMEOUT;
    4ac0:	4b29      	ldr	r3, [pc, #164]	; (4b68 <twi_tx_start_transfer+0xb0>)
    4ac2:	9301      	str	r3, [sp, #4]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    4ac4:	2300      	movs	r3, #0
    4ac6:	f8c0 3104 	str.w	r3, [r0, #260]	; 0x104
    4aca:	f8d0 2104 	ldr.w	r2, [r0, #260]	; 0x104
    4ace:	f8c0 3124 	str.w	r3, [r0, #292]	; 0x124
    4ad2:	f8d0 2124 	ldr.w	r2, [r0, #292]	; 0x124
    4ad6:	f8c0 311c 	str.w	r3, [r0, #284]	; 0x11c
    4ada:	f8d0 211c 	ldr.w	r2, [r0, #284]	; 0x11c
    4ade:	f8c0 3108 	str.w	r3, [r0, #264]	; 0x108
    4ae2:	f8d0 2108 	ldr.w	r2, [r0, #264]	; 0x108
}

NRF_STATIC_INLINE void nrf_twi_shorts_set(NRF_TWI_Type * p_reg,
                                          uint32_t       mask)
{
    p_reg->SHORTS = mask;
    4ae6:	f8c0 3200 	str.w	r3, [r0, #512]	; 0x200
    nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_ERROR);
    nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_TXDSENT);
    nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_RXDREADY);
    nrf_twi_shorts_set(p_twi, 0);

    p_cb->bytes_transferred = 0;
    4aea:	634b      	str	r3, [r1, #52]	; 0x34
    p_cb->error             = false;
    4aec:	f881 302f 	strb.w	r3, [r1, #47]	; 0x2f
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    4af0:	2301      	movs	r3, #1
    4af2:	6203      	str	r3, [r0, #32]

    // In case TWI is suspended resume its operation.
    nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_RESUME);

    if (p_cb->prev_suspend != TWI_SUSPEND_TX)
    4af4:	f891 302d 	ldrb.w	r3, [r1, #45]	; 0x2d
    4af8:	2b01      	cmp	r3, #1
    4afa:	d001      	beq.n	4b00 <twi_tx_start_transfer+0x48>
    4afc:	2301      	movs	r3, #1
    4afe:	6083      	str	r3, [r0, #8]
    {
        nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_STARTTX);
    }

    (void)twi_send_byte(p_twi, p_cb);
    4b00:	4629      	mov	r1, r5
    4b02:	4620      	mov	r0, r4
    4b04:	f002 fe59 	bl	77ba <twi_send_byte>

    if (p_cb->handler)
    4b08:	682b      	ldr	r3, [r5, #0]
    4b0a:	b143      	cbz	r3, 4b1e <twi_tx_start_transfer+0x66>
    {
        p_cb->int_mask = NRF_TWI_INT_STOPPED_MASK   |
    4b0c:	f240 2386 	movw	r3, #646	; 0x286
    4b10:	60ab      	str	r3, [r5, #8]
                         NRF_TWI_INT_ERROR_MASK     |
                         NRF_TWI_INT_TXDSENT_MASK   |
                         NRF_TWI_INT_RXDREADY_MASK;

        nrf_twi_int_enable(p_twi, p_cb->int_mask);
    4b12:	68ab      	ldr	r3, [r5, #8]
    p_reg->INTENSET = mask;
    4b14:	f8c4 3304 	str.w	r3, [r4, #772]	; 0x304
    nrfx_err_t ret_code = NRFX_SUCCESS;
    4b18:	4814      	ldr	r0, [pc, #80]	; (4b6c <twi_tx_start_transfer+0xb4>)
            ret_code = NRFX_ERROR_INTERNAL;
        }

    }
    return ret_code;
}
    4b1a:	b003      	add	sp, #12
    4b1c:	bd30      	pop	{r4, r5, pc}
        while ((hw_timeout > 0) &&
    4b1e:	9b01      	ldr	r3, [sp, #4]
    4b20:	2b00      	cmp	r3, #0
    4b22:	dd08      	ble.n	4b36 <twi_tx_start_transfer+0x7e>
               twi_transfer(p_twi, p_cb))
    4b24:	4629      	mov	r1, r5
    4b26:	4620      	mov	r0, r4
    4b28:	f002 fe97 	bl	785a <twi_transfer>
        while ((hw_timeout > 0) &&
    4b2c:	b118      	cbz	r0, 4b36 <twi_tx_start_transfer+0x7e>
            hw_timeout--;
    4b2e:	9b01      	ldr	r3, [sp, #4]
    4b30:	3b01      	subs	r3, #1
    4b32:	9301      	str	r3, [sp, #4]
    4b34:	e7f3      	b.n	4b1e <twi_tx_start_transfer+0x66>
        if (p_cb->error)
    4b36:	f895 302f 	ldrb.w	r3, [r5, #47]	; 0x2f
    4b3a:	b13b      	cbz	r3, 4b4c <twi_tx_start_transfer+0x94>
    uint32_t error_source = p_reg->ERRORSRC;
    4b3c:	f8d4 04c4 	ldr.w	r0, [r4, #1220]	; 0x4c4
    p_reg->ERRORSRC = error_source;
    4b40:	f8c4 04c4 	str.w	r0, [r4, #1220]	; 0x4c4
            if (errorsrc)
    4b44:	b170      	cbz	r0, 4b64 <twi_tx_start_transfer+0xac>
                ret_code = twi_process_error(errorsrc);
    4b46:	f7ff ff9d 	bl	4a84 <twi_process_error>
    4b4a:	e000      	b.n	4b4e <twi_tx_start_transfer+0x96>
    nrfx_err_t ret_code = NRFX_SUCCESS;
    4b4c:	4807      	ldr	r0, [pc, #28]	; (4b6c <twi_tx_start_transfer+0xb4>)
        if (hw_timeout <= 0)
    4b4e:	9b01      	ldr	r3, [sp, #4]
    4b50:	2b00      	cmp	r3, #0
    4b52:	dce2      	bgt.n	4b1a <twi_tx_start_transfer+0x62>
    p_reg->ENABLE = (TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos);
    4b54:	2300      	movs	r3, #0
    4b56:	f8c4 3500 	str.w	r3, [r4, #1280]	; 0x500
    p_reg->ENABLE = (TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos);
    4b5a:	2305      	movs	r3, #5
    4b5c:	f8c4 3500 	str.w	r3, [r4, #1280]	; 0x500
            ret_code = NRFX_ERROR_INTERNAL;
    4b60:	4803      	ldr	r0, [pc, #12]	; (4b70 <twi_tx_start_transfer+0xb8>)
    return ret_code;
    4b62:	e7da      	b.n	4b1a <twi_tx_start_transfer+0x62>
                ret_code = NRFX_ERROR_INTERNAL;
    4b64:	4802      	ldr	r0, [pc, #8]	; (4b70 <twi_tx_start_transfer+0xb8>)
    4b66:	e7f2      	b.n	4b4e <twi_tx_start_transfer+0x96>
    4b68:	000186a0 	.word	0x000186a0
    4b6c:	0bad0000 	.word	0x0bad0000
    4b70:	0bad0001 	.word	0x0bad0001

00004b74 <twi_rx_start_transfer>:

static nrfx_err_t twi_rx_start_transfer(NRF_TWI_Type        * p_twi,
                                        twi_control_block_t * p_cb)
{
    4b74:	b530      	push	{r4, r5, lr}
    4b76:	b083      	sub	sp, #12
    4b78:	4604      	mov	r4, r0
    4b7a:	460d      	mov	r5, r1
    nrfx_err_t ret_code = NRFX_SUCCESS;
    volatile int32_t hw_timeout;

    hw_timeout = HW_TIMEOUT;
    4b7c:	4b2d      	ldr	r3, [pc, #180]	; (4c34 <twi_rx_start_transfer+0xc0>)
    4b7e:	9301      	str	r3, [sp, #4]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    4b80:	2300      	movs	r3, #0
    4b82:	f8c0 3104 	str.w	r3, [r0, #260]	; 0x104
    4b86:	f8d0 2104 	ldr.w	r2, [r0, #260]	; 0x104
    4b8a:	f8c0 3124 	str.w	r3, [r0, #292]	; 0x124
    4b8e:	f8d0 2124 	ldr.w	r2, [r0, #292]	; 0x124
    4b92:	f8c0 311c 	str.w	r3, [r0, #284]	; 0x11c
    4b96:	f8d0 211c 	ldr.w	r2, [r0, #284]	; 0x11c
    4b9a:	f8c0 3108 	str.w	r3, [r0, #264]	; 0x108
    4b9e:	f8d0 2108 	ldr.w	r2, [r0, #264]	; 0x108
    nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_STOPPED);
    nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_ERROR);
    nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_TXDSENT);
    nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_RXDREADY);

    p_cb->bytes_transferred = 0;
    4ba2:	634b      	str	r3, [r1, #52]	; 0x34
    p_cb->error             = false;
    4ba4:	f881 302f 	strb.w	r3, [r1, #47]	; 0x2f

    if ((p_cb->curr_length == 1) && (!TWI_FLAG_SUSPEND(p_cb->flags)))
    4ba8:	6a8b      	ldr	r3, [r1, #40]	; 0x28
    4baa:	2b01      	cmp	r3, #1
    4bac:	d015      	beq.n	4bda <twi_rx_start_transfer+0x66>
    p_reg->SHORTS = mask;
    4bae:	2301      	movs	r3, #1
    4bb0:	f8c4 3200 	str.w	r3, [r4, #512]	; 0x200
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    4bb4:	2301      	movs	r3, #1
    4bb6:	6223      	str	r3, [r4, #32]
        nrf_twi_shorts_set(p_twi, NRF_TWI_SHORT_BB_SUSPEND_MASK);
    }
    // In case TWI is suspended resume its operation.
    nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_RESUME);

    if (p_cb->prev_suspend != TWI_SUSPEND_RX)
    4bb8:	f895 302d 	ldrb.w	r3, [r5, #45]	; 0x2d
    4bbc:	2b02      	cmp	r3, #2
    4bbe:	d001      	beq.n	4bc4 <twi_rx_start_transfer+0x50>
    4bc0:	2301      	movs	r3, #1
    4bc2:	6023      	str	r3, [r4, #0]
    {
        nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_STARTRX);
    }

    if (p_cb->handler)
    4bc4:	682b      	ldr	r3, [r5, #0]
    4bc6:	b183      	cbz	r3, 4bea <twi_rx_start_transfer+0x76>
    {
        p_cb->int_mask = NRF_TWI_INT_STOPPED_MASK   |
    4bc8:	f240 2386 	movw	r3, #646	; 0x286
    4bcc:	60ab      	str	r3, [r5, #8]
                        NRF_TWI_INT_ERROR_MASK     |
                        NRF_TWI_INT_TXDSENT_MASK   |
                        NRF_TWI_INT_RXDREADY_MASK;
        nrf_twi_int_enable(p_twi, p_cb->int_mask);
    4bce:	68ab      	ldr	r3, [r5, #8]
    p_reg->INTENSET = mask;
    4bd0:	f8c4 3304 	str.w	r3, [r4, #772]	; 0x304
    nrfx_err_t ret_code = NRFX_SUCCESS;
    4bd4:	4818      	ldr	r0, [pc, #96]	; (4c38 <twi_rx_start_transfer+0xc4>)
            nrf_twi_enable(p_twi);
            ret_code = NRFX_ERROR_INTERNAL;
        }
    }
    return ret_code;
}
    4bd6:	b003      	add	sp, #12
    4bd8:	bd30      	pop	{r4, r5, pc}
    if ((p_cb->curr_length == 1) && (!TWI_FLAG_SUSPEND(p_cb->flags)))
    4bda:	6a0b      	ldr	r3, [r1, #32]
    4bdc:	f013 0f40 	tst.w	r3, #64	; 0x40
    4be0:	d1e5      	bne.n	4bae <twi_rx_start_transfer+0x3a>
    p_reg->SHORTS = mask;
    4be2:	2302      	movs	r3, #2
    4be4:	f8c0 3200 	str.w	r3, [r0, #512]	; 0x200
}
    4be8:	e7e4      	b.n	4bb4 <twi_rx_start_transfer+0x40>
        while ((hw_timeout > 0) &&
    4bea:	9b01      	ldr	r3, [sp, #4]
    4bec:	2b00      	cmp	r3, #0
    4bee:	dd08      	ble.n	4c02 <twi_rx_start_transfer+0x8e>
               twi_transfer(p_twi, p_cb))
    4bf0:	4629      	mov	r1, r5
    4bf2:	4620      	mov	r0, r4
    4bf4:	f002 fe31 	bl	785a <twi_transfer>
        while ((hw_timeout > 0) &&
    4bf8:	b118      	cbz	r0, 4c02 <twi_rx_start_transfer+0x8e>
               hw_timeout--;
    4bfa:	9b01      	ldr	r3, [sp, #4]
    4bfc:	3b01      	subs	r3, #1
    4bfe:	9301      	str	r3, [sp, #4]
    4c00:	e7f3      	b.n	4bea <twi_rx_start_transfer+0x76>
        if (p_cb->error)
    4c02:	f895 302f 	ldrb.w	r3, [r5, #47]	; 0x2f
    4c06:	b13b      	cbz	r3, 4c18 <twi_rx_start_transfer+0xa4>
    uint32_t error_source = p_reg->ERRORSRC;
    4c08:	f8d4 04c4 	ldr.w	r0, [r4, #1220]	; 0x4c4
    p_reg->ERRORSRC = error_source;
    4c0c:	f8c4 04c4 	str.w	r0, [r4, #1220]	; 0x4c4
            if (errorsrc)
    4c10:	b170      	cbz	r0, 4c30 <twi_rx_start_transfer+0xbc>
                ret_code = twi_process_error(errorsrc);
    4c12:	f7ff ff37 	bl	4a84 <twi_process_error>
    4c16:	e000      	b.n	4c1a <twi_rx_start_transfer+0xa6>
    nrfx_err_t ret_code = NRFX_SUCCESS;
    4c18:	4807      	ldr	r0, [pc, #28]	; (4c38 <twi_rx_start_transfer+0xc4>)
        if (hw_timeout <= 0)
    4c1a:	9b01      	ldr	r3, [sp, #4]
    4c1c:	2b00      	cmp	r3, #0
    4c1e:	dcda      	bgt.n	4bd6 <twi_rx_start_transfer+0x62>
    p_reg->ENABLE = (TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos);
    4c20:	2300      	movs	r3, #0
    4c22:	f8c4 3500 	str.w	r3, [r4, #1280]	; 0x500
    p_reg->ENABLE = (TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos);
    4c26:	2305      	movs	r3, #5
    4c28:	f8c4 3500 	str.w	r3, [r4, #1280]	; 0x500
            ret_code = NRFX_ERROR_INTERNAL;
    4c2c:	4803      	ldr	r0, [pc, #12]	; (4c3c <twi_rx_start_transfer+0xc8>)
    return ret_code;
    4c2e:	e7d2      	b.n	4bd6 <twi_rx_start_transfer+0x62>
                ret_code = NRFX_ERROR_INTERNAL;
    4c30:	4802      	ldr	r0, [pc, #8]	; (4c3c <twi_rx_start_transfer+0xc8>)
    4c32:	e7f2      	b.n	4c1a <twi_rx_start_transfer+0xa6>
    4c34:	000186a0 	.word	0x000186a0
    4c38:	0bad0000 	.word	0x0bad0000
    4c3c:	0bad0001 	.word	0x0bad0001

00004c40 <twi_xfer>:

static nrfx_err_t twi_xfer(NRF_TWI_Type               * p_twi,
                           twi_control_block_t        * p_cb,
                           nrfx_twi_xfer_desc_t const * p_xfer_desc,
                           uint32_t                     flags)
{
    4c40:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    4c42:	4686      	mov	lr, r0
    4c44:	460c      	mov	r4, r1
    4c46:	4615      	mov	r5, r2
    4c48:	469c      	mov	ip, r3

    nrfx_err_t err_code = NRFX_SUCCESS;

    if ((p_cb->prev_suspend == TWI_SUSPEND_TX) && (p_xfer_desc->type == NRFX_TWI_XFER_RX))
    4c4a:	f891 302d 	ldrb.w	r3, [r1, #45]	; 0x2d
    4c4e:	2b01      	cmp	r3, #1
    4c50:	d027      	beq.n	4ca2 <twi_xfer+0x62>
    {
        /* RX is invalid after TX suspend */
        return NRFX_ERROR_INVALID_STATE;
    }
    else if ((p_cb->prev_suspend == TWI_SUSPEND_RX) && (p_xfer_desc->type != NRFX_TWI_XFER_RX))
    4c52:	2b02      	cmp	r3, #2
    4c54:	d02a      	beq.n	4cac <twi_xfer+0x6c>
    p_reg->INTENCLR = mask;
    4c56:	4b24      	ldr	r3, [pc, #144]	; (4ce8 <twi_xfer+0xa8>)
    4c58:	f8ce 3308 	str.w	r3, [lr, #776]	; 0x308
    }

    /* Block TWI interrupts to ensure that function is not interrupted by TWI interrupt. */
    nrf_twi_int_disable(p_twi, NRF_TWI_ALL_INTS_MASK);

    if (p_cb->busy)
    4c5c:	f894 3030 	ldrb.w	r3, [r4, #48]	; 0x30
    4c60:	bb4b      	cbnz	r3, 4cb6 <twi_xfer+0x76>
                         NRFX_LOG_ERROR_STRING_GET(err_code));
        return err_code;
    }
    else
    {
        p_cb->busy = (TWI_FLAG_NO_HANDLER_IN_USE(flags)) ? false : true;
    4c62:	f01c 0f04 	tst.w	ip, #4
    4c66:	bf0c      	ite	eq
    4c68:	2301      	moveq	r3, #1
    4c6a:	2300      	movne	r3, #0
    4c6c:	f884 3030 	strb.w	r3, [r4, #48]	; 0x30
    }

    p_cb->flags       = flags;
    4c70:	f8c4 c020 	str.w	ip, [r4, #32]
    p_cb->xfer_desc   = *p_xfer_desc;
    4c74:	f104 060c 	add.w	r6, r4, #12
    4c78:	462f      	mov	r7, r5
    4c7a:	cf0f      	ldmia	r7!, {r0, r1, r2, r3}
    4c7c:	c60f      	stmia	r6!, {r0, r1, r2, r3}
    4c7e:	683b      	ldr	r3, [r7, #0]
    4c80:	6033      	str	r3, [r6, #0]
    p_cb->curr_length = p_xfer_desc->primary_length;
    4c82:	686b      	ldr	r3, [r5, #4]
    4c84:	62a3      	str	r3, [r4, #40]	; 0x28
    p_cb->p_curr_buf  = p_xfer_desc->p_primary_buf;
    4c86:	68eb      	ldr	r3, [r5, #12]
    4c88:	6263      	str	r3, [r4, #36]	; 0x24
    nrf_twi_address_set(p_twi, p_xfer_desc->address);
    4c8a:	786b      	ldrb	r3, [r5, #1]
    p_reg->ADDRESS = address;
    4c8c:	f8ce 3588 	str.w	r3, [lr, #1416]	; 0x588

    if (p_xfer_desc->type != NRFX_TWI_XFER_RX)
    4c90:	782b      	ldrb	r3, [r5, #0]
    4c92:	2b01      	cmp	r3, #1
    4c94:	d020      	beq.n	4cd8 <twi_xfer+0x98>
    {
        p_cb->curr_tx_no_stop = ((p_xfer_desc->type == NRFX_TWI_XFER_TX) &&
                                 !(flags & NRFX_TWI_FLAG_TX_NO_STOP)) ? false : true;
    4c96:	b99b      	cbnz	r3, 4cc0 <twi_xfer+0x80>
    4c98:	f01c 0f20 	tst.w	ip, #32
    4c9c:	d01a      	beq.n	4cd4 <twi_xfer+0x94>
    4c9e:	2301      	movs	r3, #1
    4ca0:	e00f      	b.n	4cc2 <twi_xfer+0x82>
    if ((p_cb->prev_suspend == TWI_SUSPEND_TX) && (p_xfer_desc->type == NRFX_TWI_XFER_RX))
    4ca2:	7812      	ldrb	r2, [r2, #0]
    4ca4:	2a01      	cmp	r2, #1
    4ca6:	d1d4      	bne.n	4c52 <twi_xfer+0x12>
        return NRFX_ERROR_INVALID_STATE;
    4ca8:	4810      	ldr	r0, [pc, #64]	; (4cec <twi_xfer+0xac>)
    4caa:	e012      	b.n	4cd2 <twi_xfer+0x92>
    else if ((p_cb->prev_suspend == TWI_SUSPEND_RX) && (p_xfer_desc->type != NRFX_TWI_XFER_RX))
    4cac:	782b      	ldrb	r3, [r5, #0]
    4cae:	2b01      	cmp	r3, #1
    4cb0:	d0d1      	beq.n	4c56 <twi_xfer+0x16>
        return NRFX_ERROR_INVALID_STATE;
    4cb2:	480e      	ldr	r0, [pc, #56]	; (4cec <twi_xfer+0xac>)
    4cb4:	e00d      	b.n	4cd2 <twi_xfer+0x92>
        nrf_twi_int_enable(p_twi, p_cb->int_mask);
    4cb6:	68a3      	ldr	r3, [r4, #8]
    p_reg->INTENSET = mask;
    4cb8:	f8ce 3304 	str.w	r3, [lr, #772]	; 0x304
        return err_code;
    4cbc:	480c      	ldr	r0, [pc, #48]	; (4cf0 <twi_xfer+0xb0>)
    4cbe:	e008      	b.n	4cd2 <twi_xfer+0x92>
                                 !(flags & NRFX_TWI_FLAG_TX_NO_STOP)) ? false : true;
    4cc0:	2301      	movs	r3, #1
        p_cb->curr_tx_no_stop = ((p_xfer_desc->type == NRFX_TWI_XFER_TX) &&
    4cc2:	f884 302c 	strb.w	r3, [r4, #44]	; 0x2c

        err_code = twi_tx_start_transfer(p_twi, p_cb);
    4cc6:	4621      	mov	r1, r4
    4cc8:	4670      	mov	r0, lr
    4cca:	f7ff fef5 	bl	4ab8 <twi_tx_start_transfer>
    }
    else
    {
        err_code = twi_rx_start_transfer(p_twi, p_cb);
    }
    if (p_cb->handler == NULL)
    4cce:	6823      	ldr	r3, [r4, #0]
    4cd0:	b13b      	cbz	r3, 4ce2 <twi_xfer+0xa2>
    {
        p_cb->busy = false;
    }
    return err_code;
}
    4cd2:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
                                 !(flags & NRFX_TWI_FLAG_TX_NO_STOP)) ? false : true;
    4cd4:	2300      	movs	r3, #0
    4cd6:	e7f4      	b.n	4cc2 <twi_xfer+0x82>
        err_code = twi_rx_start_transfer(p_twi, p_cb);
    4cd8:	4621      	mov	r1, r4
    4cda:	4670      	mov	r0, lr
    4cdc:	f7ff ff4a 	bl	4b74 <twi_rx_start_transfer>
    4ce0:	e7f5      	b.n	4cce <twi_xfer+0x8e>
        p_cb->busy = false;
    4ce2:	f884 3030 	strb.w	r3, [r4, #48]	; 0x30
    4ce6:	e7f4      	b.n	4cd2 <twi_xfer+0x92>
    4ce8:	00044286 	.word	0x00044286
    4cec:	0bad0005 	.word	0x0bad0005
    4cf0:	0bad000b 	.word	0x0bad000b

00004cf4 <nrfx_twi_init>:
{
    4cf4:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    twi_control_block_t * p_cb  = &m_cb[p_instance->drv_inst_idx];
    4cf6:	7904      	ldrb	r4, [r0, #4]
    if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED)
    4cf8:	ebc4 1604 	rsb	r6, r4, r4, lsl #4
    4cfc:	4d2a      	ldr	r5, [pc, #168]	; (4da8 <nrfx_twi_init+0xb4>)
    4cfe:	eb05 0586 	add.w	r5, r5, r6, lsl #2
    4d02:	f895 502e 	ldrb.w	r5, [r5, #46]	; 0x2e
    4d06:	2d00      	cmp	r5, #0
    4d08:	d14c      	bne.n	4da4 <nrfx_twi_init+0xb0>
    p_cb->handler         = event_handler;
    4d0a:	4e27      	ldr	r6, [pc, #156]	; (4da8 <nrfx_twi_init+0xb4>)
    4d0c:	ebc4 1704 	rsb	r7, r4, r4, lsl #4
    4d10:	eb06 0587 	add.w	r5, r6, r7, lsl #2
    4d14:	f846 2027 	str.w	r2, [r6, r7, lsl #2]
    p_cb->p_context       = p_context;
    4d18:	606b      	str	r3, [r5, #4]
    p_cb->int_mask        = 0;
    4d1a:	2300      	movs	r3, #0
    4d1c:	60ab      	str	r3, [r5, #8]
    p_cb->prev_suspend    = TWI_NO_SUSPEND;
    4d1e:	f885 302d 	strb.w	r3, [r5, #45]	; 0x2d
    p_cb->repeated        = false;
    4d22:	f885 3031 	strb.w	r3, [r5, #49]	; 0x31
    p_cb->busy            = false;
    4d26:	f885 3030 	strb.w	r3, [r5, #48]	; 0x30
    p_cb->hold_bus_uninit = p_config->hold_bus_uninit;
    4d2a:	7b4b      	ldrb	r3, [r1, #13]
    4d2c:	f885 3038 	strb.w	r3, [r5, #56]	; 0x38
    TWI_PIN_INIT(p_config->scl);
    4d30:	680b      	ldr	r3, [r1, #0]
    *p_pin = pin_number & 0x1F;
    4d32:	f003 051f 	and.w	r5, r3, #31
    return pin_number >> 5;
    4d36:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    4d38:	2b01      	cmp	r3, #1
    4d3a:	d02f      	beq.n	4d9c <nrfx_twi_init+0xa8>
        case 0: return NRF_P0;
    4d3c:	f04f 46a0 	mov.w	r6, #1342177280	; 0x50000000
    reg->PIN_CNF[pin_number] = cnf;
    4d40:	f505 73e0 	add.w	r3, r5, #448	; 0x1c0
    4d44:	f240 650c 	movw	r5, #1548	; 0x60c
    4d48:	f846 5023 	str.w	r5, [r6, r3, lsl #2]
    TWI_PIN_INIT(p_config->sda);
    4d4c:	684b      	ldr	r3, [r1, #4]
    *p_pin = pin_number & 0x1F;
    4d4e:	f003 051f 	and.w	r5, r3, #31
    return pin_number >> 5;
    4d52:	095b      	lsrs	r3, r3, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    4d54:	2b01      	cmp	r3, #1
    4d56:	d023      	beq.n	4da0 <nrfx_twi_init+0xac>
        case 0: return NRF_P0;
    4d58:	f04f 46a0 	mov.w	r6, #1342177280	; 0x50000000
    reg->PIN_CNF[pin_number] = cnf;
    4d5c:	f505 73e0 	add.w	r3, r5, #448	; 0x1c0
    4d60:	f240 650c 	movw	r5, #1548	; 0x60c
    4d64:	f846 5023 	str.w	r5, [r6, r3, lsl #2]
    NRF_TWI_Type * p_twi = p_instance->p_twi;
    4d68:	6803      	ldr	r3, [r0, #0]
    nrf_twi_pins_set(p_twi, p_config->scl, p_config->sda);
    4d6a:	680e      	ldr	r6, [r1, #0]
    4d6c:	684d      	ldr	r5, [r1, #4]
    p_reg->PSEL.SCL = scl_pin;
    4d6e:	f8c3 6508 	str.w	r6, [r3, #1288]	; 0x508
    p_reg->PSEL.SDA = sda_pin;
    4d72:	f8c3 550c 	str.w	r5, [r3, #1292]	; 0x50c
        (nrf_twi_frequency_t)p_config->frequency);
    4d76:	6889      	ldr	r1, [r1, #8]
    p_reg->FREQUENCY = frequency;
    4d78:	f8c3 1524 	str.w	r1, [r3, #1316]	; 0x524
    if (p_cb->handler)
    4d7c:	b122      	cbz	r2, 4d88 <nrfx_twi_init+0x94>
        NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_instance->p_twi));
    4d7e:	6800      	ldr	r0, [r0, #0]
    4d80:	f340 3007 	sbfx	r0, r0, #12, #8
    4d84:	f7fd fa24 	bl	21d0 <arch_irq_enable>
    p_cb->state = NRFX_DRV_STATE_INITIALIZED;
    4d88:	ebc4 1404 	rsb	r4, r4, r4, lsl #4
    4d8c:	4b06      	ldr	r3, [pc, #24]	; (4da8 <nrfx_twi_init+0xb4>)
    4d8e:	eb03 0484 	add.w	r4, r3, r4, lsl #2
    4d92:	2301      	movs	r3, #1
    4d94:	f884 302e 	strb.w	r3, [r4, #46]	; 0x2e
    return err_code;
    4d98:	4804      	ldr	r0, [pc, #16]	; (4dac <nrfx_twi_init+0xb8>)
}
    4d9a:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
        case 1: return NRF_P1;
    4d9c:	4e04      	ldr	r6, [pc, #16]	; (4db0 <nrfx_twi_init+0xbc>)
    4d9e:	e7cf      	b.n	4d40 <nrfx_twi_init+0x4c>
    4da0:	4e03      	ldr	r6, [pc, #12]	; (4db0 <nrfx_twi_init+0xbc>)
    4da2:	e7db      	b.n	4d5c <nrfx_twi_init+0x68>
        return err_code;
    4da4:	4803      	ldr	r0, [pc, #12]	; (4db4 <nrfx_twi_init+0xc0>)
    4da6:	e7f8      	b.n	4d9a <nrfx_twi_init+0xa6>
    4da8:	20000638 	.word	0x20000638
    4dac:	0bad0000 	.word	0x0bad0000
    4db0:	50000300 	.word	0x50000300
    4db4:	0bad0005 	.word	0x0bad0005

00004db8 <nrfx_twi_enable>:
    twi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
    4db8:	7903      	ldrb	r3, [r0, #4]
    NRF_TWI_Type * p_twi = p_instance->p_twi;
    4dba:	6802      	ldr	r2, [r0, #0]
    p_reg->ENABLE = (TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos);
    4dbc:	2105      	movs	r1, #5
    4dbe:	f8c2 1500 	str.w	r1, [r2, #1280]	; 0x500
    p_cb->state = NRFX_DRV_STATE_POWERED_ON;
    4dc2:	ebc3 1303 	rsb	r3, r3, r3, lsl #4
    4dc6:	4a03      	ldr	r2, [pc, #12]	; (4dd4 <nrfx_twi_enable+0x1c>)
    4dc8:	eb02 0383 	add.w	r3, r2, r3, lsl #2
    4dcc:	2202      	movs	r2, #2
    4dce:	f883 202e 	strb.w	r2, [r3, #46]	; 0x2e
}
    4dd2:	4770      	bx	lr
    4dd4:	20000638 	.word	0x20000638

00004dd8 <nrfx_twi_disable>:
{
    4dd8:	b410      	push	{r4}
    twi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
    4dda:	7903      	ldrb	r3, [r0, #4]
    NRF_TWI_Type * p_twi = p_instance->p_twi;
    4ddc:	6802      	ldr	r2, [r0, #0]
    p_reg->INTENCLR = mask;
    4dde:	490c      	ldr	r1, [pc, #48]	; (4e10 <nrfx_twi_disable+0x38>)
    4de0:	f8c2 1308 	str.w	r1, [r2, #776]	; 0x308
    p_reg->SHORTS &= ~(mask);
    4de4:	f8d2 1200 	ldr.w	r1, [r2, #512]	; 0x200
    4de8:	f021 0103 	bic.w	r1, r1, #3
    4dec:	f8c2 1200 	str.w	r1, [r2, #512]	; 0x200
    p_reg->ENABLE = (TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos);
    4df0:	2000      	movs	r0, #0
    4df2:	f8c2 0500 	str.w	r0, [r2, #1280]	; 0x500
    p_cb->state = NRFX_DRV_STATE_INITIALIZED;
    4df6:	4a07      	ldr	r2, [pc, #28]	; (4e14 <nrfx_twi_disable+0x3c>)
    4df8:	ebc3 1103 	rsb	r1, r3, r3, lsl #4
    4dfc:	eb02 0181 	add.w	r1, r2, r1, lsl #2
    4e00:	2401      	movs	r4, #1
    4e02:	f881 402e 	strb.w	r4, [r1, #46]	; 0x2e
    p_cb->busy = false;
    4e06:	f881 0030 	strb.w	r0, [r1, #48]	; 0x30
}
    4e0a:	bc10      	pop	{r4}
    4e0c:	4770      	bx	lr
    4e0e:	bf00      	nop
    4e10:	00044286 	.word	0x00044286
    4e14:	20000638 	.word	0x20000638

00004e18 <nrfx_twi_xfer>:
}

nrfx_err_t nrfx_twi_xfer(nrfx_twi_t const *           p_instance,
                         nrfx_twi_xfer_desc_t const * p_xfer_desc,
                         uint32_t                     flags)
{
    4e18:	b510      	push	{r4, lr}
    4e1a:	4613      	mov	r3, r2

    nrfx_err_t err_code = NRFX_SUCCESS;
    twi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
    4e1c:	7904      	ldrb	r4, [r0, #4]
    4e1e:	ebc4 1404 	rsb	r4, r4, r4, lsl #4
                           p_xfer_desc->primary_length * sizeof(p_xfer_desc->p_primary_buf[0]));
    NRFX_LOG_DEBUG("Secondary buffer data:");
    NRFX_LOG_HEXDUMP_DEBUG(p_xfer_desc->p_secondary_buf,
                           p_xfer_desc->secondary_length * sizeof(p_xfer_desc->p_secondary_buf[0]));

    err_code = twi_xfer((NRF_TWI_Type  *)p_instance->p_twi, p_cb, p_xfer_desc, flags);
    4e22:	460a      	mov	r2, r1
    4e24:	4903      	ldr	r1, [pc, #12]	; (4e34 <nrfx_twi_xfer+0x1c>)
    4e26:	eb01 0184 	add.w	r1, r1, r4, lsl #2
    4e2a:	6800      	ldr	r0, [r0, #0]
    4e2c:	f7ff ff08 	bl	4c40 <twi_xfer>
    NRFX_LOG_WARNING("Function: %s, error code: %s.",
                     __func__,
                     NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    4e30:	bd10      	pop	{r4, pc}
    4e32:	bf00      	nop
    4e34:	20000638 	.word	0x20000638

00004e38 <nrfx_twi_0_irq_handler>:

}

#if NRFX_CHECK(NRFX_TWI0_ENABLED)
void nrfx_twi_0_irq_handler(void)
{
    4e38:	b508      	push	{r3, lr}
    twi_irq_handler(NRF_TWI0, &m_cb[NRFX_TWI0_INST_IDX]);
    4e3a:	4902      	ldr	r1, [pc, #8]	; (4e44 <nrfx_twi_0_irq_handler+0xc>)
    4e3c:	4802      	ldr	r0, [pc, #8]	; (4e48 <nrfx_twi_0_irq_handler+0x10>)
    4e3e:	f002 fd88 	bl	7952 <twi_irq_handler>
}
    4e42:	bd08      	pop	{r3, pc}
    4e44:	20000638 	.word	0x20000638
    4e48:	40003000 	.word	0x40003000

00004e4c <nrfx_twi_twim_bus_recover>:
                                                  NRF_GPIO_PIN_PULLUP,        \
                                                  NRF_GPIO_PIN_S0D1,          \
                                                  NRF_GPIO_PIN_NOSENSE)

nrfx_err_t nrfx_twi_twim_bus_recover(uint32_t scl_pin, uint32_t sda_pin)
{
    4e4c:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    *p_pin = pin_number & 0x1F;
    4e50:	f000 031f 	and.w	r3, r0, #31
    return pin_number >> 5;
    4e54:	0940      	lsrs	r0, r0, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    4e56:	2801      	cmp	r0, #1
    4e58:	d036      	beq.n	4ec8 <nrfx_twi_twim_bus_recover+0x7c>
        case 0: return NRF_P0;
    4e5a:	f04f 46a0 	mov.w	r6, #1342177280	; 0x50000000
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    4e5e:	2501      	movs	r5, #1
    4e60:	409d      	lsls	r5, r3
    p_reg->OUTSET = set_mask;
    4e62:	f8c6 5508 	str.w	r5, [r6, #1288]	; 0x508
    *p_pin = pin_number & 0x1F;
    4e66:	f001 081f 	and.w	r8, r1, #31
    return pin_number >> 5;
    4e6a:	0949      	lsrs	r1, r1, #5
    switch (nrf_gpio_pin_port_number_extract(p_pin))
    4e6c:	2901      	cmp	r1, #1
    4e6e:	d02d      	beq.n	4ecc <nrfx_twi_twim_bus_recover+0x80>
        case 0: return NRF_P0;
    4e70:	f04f 47a0 	mov.w	r7, #1342177280	; 0x50000000
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    4e74:	f04f 0901 	mov.w	r9, #1
    4e78:	fa09 f908 	lsl.w	r9, r9, r8
    p_reg->OUTSET = set_mask;
    4e7c:	f8c7 9508 	str.w	r9, [r7, #1288]	; 0x508
    reg->PIN_CNF[pin_number] = cnf;
    4e80:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    4e84:	f240 620d 	movw	r2, #1549	; 0x60d
    4e88:	f846 2023 	str.w	r2, [r6, r3, lsl #2]
    4e8c:	f508 73e0 	add.w	r3, r8, #448	; 0x1c0
    4e90:	f847 2023 	str.w	r2, [r7, r3, lsl #2]
    nrf_gpio_pin_set(scl_pin);
    nrf_gpio_pin_set(sda_pin);

    TWI_TWIM_PIN_CONFIGURE(scl_pin);
    TWI_TWIM_PIN_CONFIGURE(sda_pin);
    NRFX_DELAY_US(4);
    4e94:	2004      	movs	r0, #4
    4e96:	f002 fc68 	bl	776a <nrfx_busy_wait>

    for (uint8_t i = 0; i < 9; i++)
    4e9a:	2400      	movs	r4, #0
    4e9c:	2c08      	cmp	r4, #8
    4e9e:	d817      	bhi.n	4ed0 <nrfx_twi_twim_bus_recover+0x84>
    return p_reg->IN;
    4ea0:	f8d7 3510 	ldr.w	r3, [r7, #1296]	; 0x510
    return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL);
    4ea4:	fa23 f308 	lsr.w	r3, r3, r8
    {
        if (nrf_gpio_pin_read(sda_pin))
    4ea8:	f013 0f01 	tst.w	r3, #1
    4eac:	d110      	bne.n	4ed0 <nrfx_twi_twim_bus_recover+0x84>
    p_reg->OUTCLR = clr_mask;
    4eae:	f8c6 550c 	str.w	r5, [r6, #1292]	; 0x50c
        }
        else
        {
            // Pulse CLOCK signal
            nrf_gpio_pin_clear(scl_pin);
            NRFX_DELAY_US(4);
    4eb2:	2004      	movs	r0, #4
    4eb4:	f002 fc59 	bl	776a <nrfx_busy_wait>
    p_reg->OUTSET = set_mask;
    4eb8:	f8c6 5508 	str.w	r5, [r6, #1288]	; 0x508
            nrf_gpio_pin_set(scl_pin);
            NRFX_DELAY_US(4);
    4ebc:	2004      	movs	r0, #4
    4ebe:	f002 fc54 	bl	776a <nrfx_busy_wait>
    for (uint8_t i = 0; i < 9; i++)
    4ec2:	3401      	adds	r4, #1
    4ec4:	b2e4      	uxtb	r4, r4
    4ec6:	e7e9      	b.n	4e9c <nrfx_twi_twim_bus_recover+0x50>
        case 1: return NRF_P1;
    4ec8:	4e0c      	ldr	r6, [pc, #48]	; (4efc <nrfx_twi_twim_bus_recover+0xb0>)
    4eca:	e7c8      	b.n	4e5e <nrfx_twi_twim_bus_recover+0x12>
    4ecc:	4f0b      	ldr	r7, [pc, #44]	; (4efc <nrfx_twi_twim_bus_recover+0xb0>)
    4ece:	e7d1      	b.n	4e74 <nrfx_twi_twim_bus_recover+0x28>
    p_reg->OUTCLR = clr_mask;
    4ed0:	f8c7 950c 	str.w	r9, [r7, #1292]	; 0x50c
        }
    }

    // Generate a STOP condition on the bus
    nrf_gpio_pin_clear(sda_pin);
    NRFX_DELAY_US(4);
    4ed4:	2004      	movs	r0, #4
    4ed6:	f002 fc48 	bl	776a <nrfx_busy_wait>
    p_reg->OUTSET = set_mask;
    4eda:	f8c7 9508 	str.w	r9, [r7, #1288]	; 0x508
    nrf_gpio_pin_set(sda_pin);
    NRFX_DELAY_US(4);
    4ede:	2004      	movs	r0, #4
    4ee0:	f002 fc43 	bl	776a <nrfx_busy_wait>
    return p_reg->IN;
    4ee4:	f8d7 3510 	ldr.w	r3, [r7, #1296]	; 0x510
    return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL);
    4ee8:	fa23 f808 	lsr.w	r8, r3, r8

    if (nrf_gpio_pin_read(sda_pin))
    4eec:	f018 0f01 	tst.w	r8, #1
    4ef0:	d002      	beq.n	4ef8 <nrfx_twi_twim_bus_recover+0xac>
    {
        return NRFX_SUCCESS;
    4ef2:	4803      	ldr	r0, [pc, #12]	; (4f00 <nrfx_twi_twim_bus_recover+0xb4>)
    }
    else
    {
        return NRFX_ERROR_INTERNAL;
    }
}
    4ef4:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
        return NRFX_ERROR_INTERNAL;
    4ef8:	4802      	ldr	r0, [pc, #8]	; (4f04 <nrfx_twi_twim_bus_recover+0xb8>)
    4efa:	e7fb      	b.n	4ef4 <nrfx_twi_twim_bus_recover+0xa8>
    4efc:	50000300 	.word	0x50000300
    4f00:	0bad0000 	.word	0x0bad0000
    4f04:	0bad0001 	.word	0x0bad0001

00004f08 <_DoInit>:
  volatile SEGGER_RTT_CB* p;   // Volatile to make sure that compiler cannot change the order of accesses to the control block
  //
  // Initialize control block
  //
  p                     = (volatile SEGGER_RTT_CB*)((char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access control block uncached so that nothing in the cache ever becomes dirty and all changes are visible in HW directly
  p->MaxNumUpBuffers    = SEGGER_RTT_MAX_NUM_UP_BUFFERS;
    4f08:	4b11      	ldr	r3, [pc, #68]	; (4f50 <_DoInit+0x48>)
    4f0a:	2203      	movs	r2, #3
    4f0c:	611a      	str	r2, [r3, #16]
  p->MaxNumDownBuffers  = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS;
    4f0e:	615a      	str	r2, [r3, #20]
  //
  // Initialize up buffer 0
  //
  p->aUp[0].sName         = "Terminal";
    4f10:	4910      	ldr	r1, [pc, #64]	; (4f54 <_DoInit+0x4c>)
    4f12:	6199      	str	r1, [r3, #24]
  p->aUp[0].pBuffer       = _acUpBuffer;
    4f14:	4a10      	ldr	r2, [pc, #64]	; (4f58 <_DoInit+0x50>)
    4f16:	61da      	str	r2, [r3, #28]
  p->aUp[0].SizeOfBuffer  = BUFFER_SIZE_UP;
    4f18:	f44f 6280 	mov.w	r2, #1024	; 0x400
    4f1c:	621a      	str	r2, [r3, #32]
  p->aUp[0].RdOff         = 0u;
    4f1e:	2200      	movs	r2, #0
    4f20:	629a      	str	r2, [r3, #40]	; 0x28
  p->aUp[0].WrOff         = 0u;
    4f22:	625a      	str	r2, [r3, #36]	; 0x24
  p->aUp[0].Flags         = SEGGER_RTT_MODE_DEFAULT;
    4f24:	62da      	str	r2, [r3, #44]	; 0x2c
  //
  // Initialize down buffer 0
  //
  p->aDown[0].sName         = "Terminal";
    4f26:	6619      	str	r1, [r3, #96]	; 0x60
  p->aDown[0].pBuffer       = _acDownBuffer;
    4f28:	490c      	ldr	r1, [pc, #48]	; (4f5c <_DoInit+0x54>)
    4f2a:	6659      	str	r1, [r3, #100]	; 0x64
  p->aDown[0].SizeOfBuffer  = BUFFER_SIZE_DOWN;
    4f2c:	2110      	movs	r1, #16
    4f2e:	6699      	str	r1, [r3, #104]	; 0x68
  p->aDown[0].RdOff         = 0u;
    4f30:	671a      	str	r2, [r3, #112]	; 0x70
  p->aDown[0].WrOff         = 0u;
    4f32:	66da      	str	r2, [r3, #108]	; 0x6c
  p->aDown[0].Flags         = SEGGER_RTT_MODE_DEFAULT;
    4f34:	675a      	str	r2, [r3, #116]	; 0x74
  //
  // Finish initialization of the control block.
  // Copy Id string in three steps to make sure "SEGGER RTT" is not found
  // in initializer memory (usually flash) by J-Link
  //
  STRCPY((char*)&p->acID[7], "RTT");
    4f36:	4a0a      	ldr	r2, [pc, #40]	; (4f60 <_DoInit+0x58>)
    4f38:	6810      	ldr	r0, [r2, #0]
    4f3a:	f8c3 0007 	str.w	r0, [r3, #7]
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
  STRCPY((char*)&p->acID[0], "SEGGER");
    4f3e:	4a09      	ldr	r2, [pc, #36]	; (4f64 <_DoInit+0x5c>)
    4f40:	e892 0003 	ldmia.w	r2, {r0, r1}
    4f44:	6018      	str	r0, [r3, #0]
    4f46:	8099      	strh	r1, [r3, #4]
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
  p->acID[6] = ' ';
    4f48:	2220      	movs	r2, #32
    4f4a:	719a      	strb	r2, [r3, #6]
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
}
    4f4c:	4770      	bx	lr
    4f4e:	bf00      	nop
    4f50:	20000674 	.word	0x20000674
    4f54:	00008d54 	.word	0x00008d54
    4f58:	2000072c 	.word	0x2000072c
    4f5c:	2000071c 	.word	0x2000071c
    4f60:	00008d60 	.word	0x00008d60
    4f64:	00008d64 	.word	0x00008d64

00004f68 <SEGGER_RTT_WriteSkipNoLock>:
*    (2) For performance reasons this function does not call Init()
*        and may only be called after RTT has been initialized.
*        Either by calling SEGGER_RTT_Init() or calling another RTT API function first.
*/
#if (RTT_USE_ASM == 0)
unsigned SEGGER_RTT_WriteSkipNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) {
    4f68:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    4f6c:	4604      	mov	r4, r0
    4f6e:	460e      	mov	r6, r1
    4f70:	4615      	mov	r5, r2
  //
  // 1) is the most common case for large buffers and assuming that J-Link reads the data fast enough
  //
  pData = (const char *)pBuffer;
  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
  RdOff = pRing->RdOff;
    4f72:	eb00 0340 	add.w	r3, r0, r0, lsl #1
    4f76:	4a2d      	ldr	r2, [pc, #180]	; (502c <SEGGER_RTT_WriteSkipNoLock+0xc4>)
    4f78:	eb02 02c3 	add.w	r2, r2, r3, lsl #3
    4f7c:	6a93      	ldr	r3, [r2, #40]	; 0x28
  WrOff = pRing->WrOff;
    4f7e:	6a57      	ldr	r7, [r2, #36]	; 0x24
  if (RdOff <= WrOff) {                                 // Case 1), 2) or 3)
    4f80:	42bb      	cmp	r3, r7
    4f82:	d84b      	bhi.n	501c <SEGGER_RTT_WriteSkipNoLock+0xb4>
    Avail = pRing->SizeOfBuffer - WrOff - 1u;           // Space until wrap-around (assume 1 byte not usable for case that RdOff == 0)
    4f84:	eb00 0240 	add.w	r2, r0, r0, lsl #1
    4f88:	4928      	ldr	r1, [pc, #160]	; (502c <SEGGER_RTT_WriteSkipNoLock+0xc4>)
    4f8a:	eb01 02c2 	add.w	r2, r1, r2, lsl #3
    4f8e:	f8d2 8020 	ldr.w	r8, [r2, #32]
    4f92:	eba8 0907 	sub.w	r9, r8, r7
    4f96:	f109 32ff 	add.w	r2, r9, #4294967295
    if (Avail >= NumBytes) {                            // Case 1)?
    4f9a:	4295      	cmp	r5, r2
    4f9c:	d904      	bls.n	4fa8 <SEGGER_RTT_WriteSkipNoLock+0x40>
      memcpy((void*)pDst, pData, NumBytes);
      RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
      pRing->WrOff = WrOff + NumBytes;
      return 1;
    }
    Avail += RdOff;                                     // Space incl. wrap-around
    4f9e:	4413      	add	r3, r2
    if (Avail >= NumBytes) {                            // Case 2? => If not, we have case 3) (does not fit)
    4fa0:	429d      	cmp	r5, r3
    4fa2:	d917      	bls.n	4fd4 <SEGGER_RTT_WriteSkipNoLock+0x6c>
    Avail = RdOff - WrOff - 1u;
    if (Avail >= NumBytes) {                           // Case 4)? => If not, we have case 5) (does not fit)
      goto CopyStraight;
    }
  }
  return 0;     // No space in buffer
    4fa4:	2000      	movs	r0, #0
    4fa6:	e03e      	b.n	5026 <SEGGER_RTT_WriteSkipNoLock+0xbe>
      pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF;
    4fa8:	f8df 8080 	ldr.w	r8, [pc, #128]	; 502c <SEGGER_RTT_WriteSkipNoLock+0xc4>
    4fac:	1c63      	adds	r3, r4, #1
    4fae:	eb03 0343 	add.w	r3, r3, r3, lsl #1
    4fb2:	eb08 03c3 	add.w	r3, r8, r3, lsl #3
    4fb6:	6858      	ldr	r0, [r3, #4]
__ssp_bos_icheck3_restrict(memcpy, void *, const void *)
    4fb8:	462a      	mov	r2, r5
    4fba:	4631      	mov	r1, r6
    4fbc:	4438      	add	r0, r7
    4fbe:	f003 f85c 	bl	807a <memcpy>
      pRing->WrOff = WrOff + NumBytes;
    4fc2:	443d      	add	r5, r7
    4fc4:	eb04 0444 	add.w	r4, r4, r4, lsl #1
    4fc8:	eb08 08c4 	add.w	r8, r8, r4, lsl #3
    4fcc:	f8c8 5024 	str.w	r5, [r8, #36]	; 0x24
      return 1;
    4fd0:	2001      	movs	r0, #1
    4fd2:	e028      	b.n	5026 <SEGGER_RTT_WriteSkipNoLock+0xbe>
      pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF;
    4fd4:	1c43      	adds	r3, r0, #1
    4fd6:	eb03 0343 	add.w	r3, r3, r3, lsl #1
    4fda:	4a14      	ldr	r2, [pc, #80]	; (502c <SEGGER_RTT_WriteSkipNoLock+0xc4>)
    4fdc:	eb02 03c3 	add.w	r3, r2, r3, lsl #3
    4fe0:	6858      	ldr	r0, [r3, #4]
    4fe2:	464a      	mov	r2, r9
    4fe4:	4631      	mov	r1, r6
    4fe6:	4438      	add	r0, r7
    4fe8:	f003 f847 	bl	807a <memcpy>
      NumBytes -= Rem;
    4fec:	eba7 0708 	sub.w	r7, r7, r8
      if (NumBytes) {
    4ff0:	197f      	adds	r7, r7, r5
    4ff2:	d00b      	beq.n	500c <SEGGER_RTT_WriteSkipNoLock+0xa4>
        pDst = pRing->pBuffer + SEGGER_RTT_UNCACHED_OFF;
    4ff4:	1c63      	adds	r3, r4, #1
    4ff6:	eb03 0343 	add.w	r3, r3, r3, lsl #1
    4ffa:	4a0c      	ldr	r2, [pc, #48]	; (502c <SEGGER_RTT_WriteSkipNoLock+0xc4>)
    4ffc:	eb02 03c3 	add.w	r3, r2, r3, lsl #3
    5000:	463a      	mov	r2, r7
    5002:	eb06 0109 	add.w	r1, r6, r9
    5006:	6858      	ldr	r0, [r3, #4]
    5008:	f003 f837 	bl	807a <memcpy>
      pRing->WrOff = NumBytes;
    500c:	eb04 0444 	add.w	r4, r4, r4, lsl #1
    5010:	4b06      	ldr	r3, [pc, #24]	; (502c <SEGGER_RTT_WriteSkipNoLock+0xc4>)
    5012:	eb03 04c4 	add.w	r4, r3, r4, lsl #3
    5016:	6267      	str	r7, [r4, #36]	; 0x24
      return 1;
    5018:	2001      	movs	r0, #1
    501a:	e004      	b.n	5026 <SEGGER_RTT_WriteSkipNoLock+0xbe>
    Avail = RdOff - WrOff - 1u;
    501c:	1bdb      	subs	r3, r3, r7
    501e:	3b01      	subs	r3, #1
    if (Avail >= NumBytes) {                           // Case 4)? => If not, we have case 5) (does not fit)
    5020:	42ab      	cmp	r3, r5
    5022:	d2c1      	bcs.n	4fa8 <SEGGER_RTT_WriteSkipNoLock+0x40>
  return 0;     // No space in buffer
    5024:	2000      	movs	r0, #0
}
    5026:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
    502a:	bf00      	nop
    502c:	20000674 	.word	0x20000674

00005030 <SEGGER_RTT_HasDataUp>:
unsigned SEGGER_RTT_HasDataUp(unsigned BufferIndex) {
  SEGGER_RTT_BUFFER_UP* pRing;
  unsigned                v;

  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
  v = pRing->RdOff;
    5030:	4b06      	ldr	r3, [pc, #24]	; (504c <SEGGER_RTT_HasDataUp+0x1c>)
    5032:	eb00 0240 	add.w	r2, r0, r0, lsl #1
    5036:	eb03 02c2 	add.w	r2, r3, r2, lsl #3
    503a:	6a92      	ldr	r2, [r2, #40]	; 0x28
  return pRing->WrOff - v;
    503c:	eb00 0040 	add.w	r0, r0, r0, lsl #1
    5040:	eb03 00c0 	add.w	r0, r3, r0, lsl #3
    5044:	6a40      	ldr	r0, [r0, #36]	; 0x24
}
    5046:	1a80      	subs	r0, r0, r2
    5048:	4770      	bx	lr
    504a:	bf00      	nop
    504c:	20000674 	.word	0x20000674

00005050 <z_device_state_init>:
 * The state object is always zero-initialized, but this may not be
 * sufficient.
 */
void z_device_state_init(void)
{
	const struct device *dev = __device_start;
    5050:	4b03      	ldr	r3, [pc, #12]	; (5060 <z_device_state_init+0x10>)

	while (dev < __device_end) {
    5052:	4a04      	ldr	r2, [pc, #16]	; (5064 <z_device_state_init+0x14>)
    5054:	4293      	cmp	r3, r2
    5056:	d201      	bcs.n	505c <z_device_state_init+0xc>
		z_object_init(dev);
		++dev;
    5058:	3318      	adds	r3, #24
    505a:	e7fa      	b.n	5052 <z_device_state_init+0x2>
	}
}
    505c:	4770      	bx	lr
    505e:	bf00      	nop
    5060:	0000816c 	.word	0x0000816c
    5064:	00008214 	.word	0x00008214

00005068 <z_sys_init_run_level>:
 * off and the next one begins.
 *
 * @param level init level to run.
 */
void z_sys_init_run_level(int32_t level)
{
    5068:	b570      	push	{r4, r5, r6, lr}
    506a:	4606      	mov	r6, r0
		/* End marker */
		__init_end,
	};
	const struct init_entry *entry;

	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    506c:	4b11      	ldr	r3, [pc, #68]	; (50b4 <z_sys_init_run_level+0x4c>)
    506e:	f853 4020 	ldr.w	r4, [r3, r0, lsl #2]
    5072:	e009      	b.n	5088 <z_sys_init_run_level+0x20>
			/* Mark device initialized.  If initialization
			 * failed, record the error condition.
			 */
			if (rc != 0) {
				if (rc < 0) {
					rc = -rc;
    5074:	4240      	negs	r0, r0
    5076:	e017      	b.n	50a8 <z_sys_init_run_level+0x40>
				}
				if (rc > UINT8_MAX) {
					rc = UINT8_MAX;
				}
				dev->state->init_res = rc;
    5078:	68eb      	ldr	r3, [r5, #12]
    507a:	7018      	strb	r0, [r3, #0]
			}
			dev->state->initialized = true;
    507c:	68ea      	ldr	r2, [r5, #12]
    507e:	7853      	ldrb	r3, [r2, #1]
    5080:	f043 0301 	orr.w	r3, r3, #1
    5084:	7053      	strb	r3, [r2, #1]
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    5086:	3408      	adds	r4, #8
    5088:	1c73      	adds	r3, r6, #1
    508a:	4a0a      	ldr	r2, [pc, #40]	; (50b4 <z_sys_init_run_level+0x4c>)
    508c:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
    5090:	42a3      	cmp	r3, r4
    5092:	d90d      	bls.n	50b0 <z_sys_init_run_level+0x48>
		const struct device *dev = entry->dev;
    5094:	6865      	ldr	r5, [r4, #4]
		int rc = entry->init(dev);
    5096:	6823      	ldr	r3, [r4, #0]
    5098:	4628      	mov	r0, r5
    509a:	4798      	blx	r3
		if (dev != NULL) {
    509c:	2d00      	cmp	r5, #0
    509e:	d0f2      	beq.n	5086 <z_sys_init_run_level+0x1e>
			if (rc != 0) {
    50a0:	2800      	cmp	r0, #0
    50a2:	d0eb      	beq.n	507c <z_sys_init_run_level+0x14>
				if (rc < 0) {
    50a4:	2800      	cmp	r0, #0
    50a6:	dbe5      	blt.n	5074 <z_sys_init_run_level+0xc>
				if (rc > UINT8_MAX) {
    50a8:	28ff      	cmp	r0, #255	; 0xff
    50aa:	dde5      	ble.n	5078 <z_sys_init_run_level+0x10>
					rc = UINT8_MAX;
    50ac:	20ff      	movs	r0, #255	; 0xff
    50ae:	e7e3      	b.n	5078 <z_sys_init_run_level+0x10>
		}
	}
}
    50b0:	bd70      	pop	{r4, r5, r6, pc}
    50b2:	bf00      	nop
    50b4:	00008d6c 	.word	0x00008d6c

000050b8 <z_impl_device_get_binding>:

const struct device *z_impl_device_get_binding(const char *name)
{
    50b8:	b538      	push	{r3, r4, r5, lr}
	const struct device *dev;

	/* A null string identifies no device.  So does an empty
	 * string.
	 */
	if ((name == NULL) || (name[0] == '\0')) {
    50ba:	4605      	mov	r5, r0
    50bc:	b328      	cbz	r0, 510a <z_impl_device_get_binding+0x52>
    50be:	7803      	ldrb	r3, [r0, #0]
    50c0:	b32b      	cbz	r3, 510e <z_impl_device_get_binding+0x56>
	/* Split the search into two loops: in the common scenario, where
	 * device names are stored in ROM (and are referenced by the user
	 * with CONFIG_* macros), only cheap pointer comparisons will be
	 * performed. Reserve string comparisons for a fallback.
	 */
	for (dev = __device_start; dev != __device_end; dev++) {
    50c2:	4c14      	ldr	r4, [pc, #80]	; (5114 <z_impl_device_get_binding+0x5c>)
    50c4:	e000      	b.n	50c8 <z_impl_device_get_binding+0x10>
    50c6:	3418      	adds	r4, #24
    50c8:	4b13      	ldr	r3, [pc, #76]	; (5118 <z_impl_device_get_binding+0x60>)
    50ca:	429c      	cmp	r4, r3
    50cc:	d008      	beq.n	50e0 <z_impl_device_get_binding+0x28>
		if (z_device_ready(dev) && (dev->name == name)) {
    50ce:	4620      	mov	r0, r4
    50d0:	f002 fcb0 	bl	7a34 <z_device_ready>
    50d4:	2800      	cmp	r0, #0
    50d6:	d0f6      	beq.n	50c6 <z_impl_device_get_binding+0xe>
    50d8:	6823      	ldr	r3, [r4, #0]
    50da:	42ab      	cmp	r3, r5
    50dc:	d1f3      	bne.n	50c6 <z_impl_device_get_binding+0xe>
    50de:	e012      	b.n	5106 <z_impl_device_get_binding+0x4e>
			return dev;
		}
	}

	for (dev = __device_start; dev != __device_end; dev++) {
    50e0:	4c0c      	ldr	r4, [pc, #48]	; (5114 <z_impl_device_get_binding+0x5c>)
    50e2:	e000      	b.n	50e6 <z_impl_device_get_binding+0x2e>
    50e4:	3418      	adds	r4, #24
    50e6:	4b0c      	ldr	r3, [pc, #48]	; (5118 <z_impl_device_get_binding+0x60>)
    50e8:	429c      	cmp	r4, r3
    50ea:	d00b      	beq.n	5104 <z_impl_device_get_binding+0x4c>
		if (z_device_ready(dev) && (strcmp(name, dev->name) == 0)) {
    50ec:	4620      	mov	r0, r4
    50ee:	f002 fca1 	bl	7a34 <z_device_ready>
    50f2:	2800      	cmp	r0, #0
    50f4:	d0f6      	beq.n	50e4 <z_impl_device_get_binding+0x2c>
    50f6:	6821      	ldr	r1, [r4, #0]
    50f8:	4628      	mov	r0, r5
    50fa:	f7fb f97b 	bl	3f4 <strcmp>
    50fe:	2800      	cmp	r0, #0
    5100:	d1f0      	bne.n	50e4 <z_impl_device_get_binding+0x2c>
    5102:	e000      	b.n	5106 <z_impl_device_get_binding+0x4e>
			return dev;
		}
	}

	return NULL;
    5104:	2400      	movs	r4, #0
}
    5106:	4620      	mov	r0, r4
    5108:	bd38      	pop	{r3, r4, r5, pc}
		return NULL;
    510a:	4604      	mov	r4, r0
    510c:	e7fb      	b.n	5106 <z_impl_device_get_binding+0x4e>
    510e:	2400      	movs	r4, #0
    5110:	e7f9      	b.n	5106 <z_impl_device_get_binding+0x4e>
    5112:	bf00      	nop
    5114:	0000816c 	.word	0x0000816c
    5118:	00008214 	.word	0x00008214

0000511c <reason_to_str>:
	return thread_name;
}

static const char *reason_to_str(unsigned int reason)
{
	switch (reason) {
    511c:	2804      	cmp	r0, #4
    511e:	d80c      	bhi.n	513a <reason_to_str+0x1e>
    5120:	e8df f000 	tbb	[pc, r0]
    5124:	07050d03 	.word	0x07050d03
    5128:	09          	.byte	0x09
    5129:	00          	.byte	0x00
	case K_ERR_STACK_CHK_FAIL:
		return "Stack overflow";
	case K_ERR_KERNEL_OOPS:
		return "Kernel oops";
	case K_ERR_KERNEL_PANIC:
		return "Kernel panic";
    512a:	4806      	ldr	r0, [pc, #24]	; (5144 <reason_to_str+0x28>)
    512c:	4770      	bx	lr
		return "Stack overflow";
    512e:	4806      	ldr	r0, [pc, #24]	; (5148 <reason_to_str+0x2c>)
    5130:	4770      	bx	lr
		return "Kernel oops";
    5132:	4806      	ldr	r0, [pc, #24]	; (514c <reason_to_str+0x30>)
    5134:	4770      	bx	lr
		return "Kernel panic";
    5136:	4806      	ldr	r0, [pc, #24]	; (5150 <reason_to_str+0x34>)
    5138:	4770      	bx	lr
	default:
		return "Unknown error";
    513a:	4806      	ldr	r0, [pc, #24]	; (5154 <reason_to_str+0x38>)
    513c:	4770      	bx	lr
		return "Unhandled interrupt";
    513e:	4806      	ldr	r0, [pc, #24]	; (5158 <reason_to_str+0x3c>)
	}
}
    5140:	4770      	bx	lr
    5142:	bf00      	nop
    5144:	00008dd4 	.word	0x00008dd4
    5148:	00008da8 	.word	0x00008da8
    514c:	00008db8 	.word	0x00008db8
    5150:	00008dc4 	.word	0x00008dc4
    5154:	00008d84 	.word	0x00008d84
    5158:	00008d94 	.word	0x00008d94

0000515c <thread_name_get>:
	const char *thread_name = (thread != NULL) ? k_thread_name_get(thread) : NULL;
    515c:	b130      	cbz	r0, 516c <thread_name_get+0x10>
{
    515e:	b508      	push	{r3, lr}
	const char *thread_name = (thread != NULL) ? k_thread_name_get(thread) : NULL;
    5160:	f002 fcd9 	bl	7b16 <k_thread_name_get>
	if ((thread_name == NULL) || (thread_name[0] == '\0')) {
    5164:	b120      	cbz	r0, 5170 <thread_name_get+0x14>
    5166:	7803      	ldrb	r3, [r0, #0]
    5168:	b123      	cbz	r3, 5174 <thread_name_get+0x18>
}
    516a:	bd08      	pop	{r3, pc}
		thread_name = "unknown";
    516c:	4802      	ldr	r0, [pc, #8]	; (5178 <thread_name_get+0x1c>)
}
    516e:	4770      	bx	lr
		thread_name = "unknown";
    5170:	4801      	ldr	r0, [pc, #4]	; (5178 <thread_name_get+0x1c>)
    5172:	e7fa      	b.n	516a <thread_name_get+0xe>
    5174:	4800      	ldr	r0, [pc, #0]	; (5178 <thread_name_get+0x1c>)
	return thread_name;
    5176:	e7f8      	b.n	516a <thread_name_get+0xe>
    5178:	00008de4 	.word	0x00008de4

0000517c <z_fatal_error>:
	return 0;
#endif
}

void z_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
{
    517c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    5180:	b082      	sub	sp, #8
    5182:	4605      	mov	r5, r0
    5184:	460e      	mov	r6, r1
    5186:	f04f 0320 	mov.w	r3, #32
    518a:	f3ef 8711 	mrs	r7, BASEPRI
    518e:	f383 8812 	msr	BASEPRI_MAX, r3
    5192:	f3bf 8f6f 	isb	sy
	return z_impl_z_current_get();
    5196:	f001 f8e1 	bl	635c <z_impl_z_current_get>
    519a:	4604      	mov	r4, r0
    519c:	4b29      	ldr	r3, [pc, #164]	; (5244 <z_fatal_error+0xc8>)
    519e:	4a2a      	ldr	r2, [pc, #168]	; (5248 <z_fatal_error+0xcc>)
    51a0:	1a9b      	subs	r3, r3, r2
    51a2:	08db      	lsrs	r3, r3, #3
			k_current_get() : NULL;

	/* twister looks for the "ZEPHYR FATAL ERROR" string, don't
	 * change it without also updating twister
	 */
	LOG_ERR(">>> ZEPHYR FATAL ERROR %d: %s on CPU %d", reason,
    51a4:	f04f 0800 	mov.w	r8, #0
    51a8:	2201      	movs	r2, #1
    51aa:	f362 0802 	bfi	r8, r2, #0, #3
    51ae:	f36f 08c5 	bfc	r8, #3, #3
    51b2:	f363 188f 	bfi	r8, r3, #6, #10
    51b6:	4628      	mov	r0, r5
    51b8:	f7ff ffb0 	bl	511c <reason_to_str>
    51bc:	4602      	mov	r2, r0
    51be:	f8ad 8000 	strh.w	r8, [sp]
    51c2:	2300      	movs	r3, #0
    51c4:	4629      	mov	r1, r5
    51c6:	4821      	ldr	r0, [pc, #132]	; (524c <z_fatal_error+0xd0>)
    51c8:	f7fc fa52 	bl	1670 <log_3>
	 * an IRQ or exception was being handled, or thread context.
	 *
	 * See #17656
	 */
#if defined(CONFIG_ARCH_HAS_NESTED_EXCEPTION_DETECTION)
	if ((esf != NULL) && arch_is_in_nested_exception(esf)) {
    51cc:	b11e      	cbz	r6, 51d6 <z_fatal_error+0x5a>
 * @return true if execution state was in handler mode, before
 *              the current exception occurred, otherwise false.
 */
static ALWAYS_INLINE bool arch_is_in_nested_exception(const z_arch_esf_t *esf)
{
	return (esf->basic.xpsr & IPSR_ISR_Msk) ? (true) : (false);
    51ce:	69f3      	ldr	r3, [r6, #28]
    51d0:	f3c3 0308 	ubfx	r3, r3, #0, #9
    51d4:	bb2b      	cbnz	r3, 5222 <z_fatal_error+0xa6>
    51d6:	4b1b      	ldr	r3, [pc, #108]	; (5244 <z_fatal_error+0xc8>)
    51d8:	4a1b      	ldr	r2, [pc, #108]	; (5248 <z_fatal_error+0xcc>)
    51da:	1a9b      	subs	r3, r3, r2
    51dc:	08db      	lsrs	r3, r3, #3
		LOG_ERR("Fault during interrupt handling\n");
	}
#endif

	LOG_ERR("Current thread: %p (%s)", thread,
    51de:	f04f 0800 	mov.w	r8, #0
    51e2:	2201      	movs	r2, #1
    51e4:	f362 0802 	bfi	r8, r2, #0, #3
    51e8:	f36f 08c5 	bfc	r8, #3, #3
    51ec:	f363 188f 	bfi	r8, r3, #6, #10
    51f0:	4620      	mov	r0, r4
    51f2:	f7ff ffb3 	bl	515c <thread_name_get>
{
	if (IS_ENABLED(CONFIG_LOG_MINIMAL) || IS_ENABLED(CONFIG_LOG2)) {
		return (char *)str;
	}

	return z_log_strdup(str);
    51f6:	f7fc f8ff 	bl	13f8 <z_log_strdup>
    51fa:	4602      	mov	r2, r0
    51fc:	4643      	mov	r3, r8
    51fe:	4621      	mov	r1, r4
    5200:	4813      	ldr	r0, [pc, #76]	; (5250 <z_fatal_error+0xd4>)
    5202:	f7fc faa9 	bl	1758 <log_2>
		log_strdup(thread_name_get(thread)));

	coredump(reason, esf, thread);

	k_sys_fatal_error_handler(reason, esf);
    5206:	4631      	mov	r1, r6
    5208:	4628      	mov	r0, r5
    520a:	f7ff f973 	bl	44f4 <k_sys_fatal_error_handler>
	__asm__ volatile(
    520e:	f387 8811 	msr	BASEPRI, r7
    5212:	f3bf 8f6f 	isb	sy
	z_impl_k_thread_abort(thread);
    5216:	4620      	mov	r0, r4
    5218:	f7fd fd0c 	bl	2c34 <z_impl_k_thread_abort>
	arch_irq_unlock(key);

	if (IS_ENABLED(CONFIG_MULTITHREADING)) {
		k_thread_abort(thread);
	}
}
    521c:	b002      	add	sp, #8
    521e:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    5222:	4b08      	ldr	r3, [pc, #32]	; (5244 <z_fatal_error+0xc8>)
    5224:	4a08      	ldr	r2, [pc, #32]	; (5248 <z_fatal_error+0xcc>)
    5226:	1a9b      	subs	r3, r3, r2
    5228:	08db      	lsrs	r3, r3, #3
		LOG_ERR("Fault during interrupt handling\n");
    522a:	f04f 0100 	mov.w	r1, #0
    522e:	2201      	movs	r2, #1
    5230:	f362 0102 	bfi	r1, r2, #0, #3
    5234:	f36f 01c5 	bfc	r1, #3, #3
    5238:	f363 118f 	bfi	r1, r3, #6, #10
    523c:	4805      	ldr	r0, [pc, #20]	; (5254 <z_fatal_error+0xd8>)
    523e:	f7fc fac7 	bl	17d0 <log_0>
    5242:	e7c8      	b.n	51d6 <z_fatal_error+0x5a>
    5244:	000083d4 	.word	0x000083d4
    5248:	0000839c 	.word	0x0000839c
    524c:	00008dec 	.word	0x00008dec
    5250:	00008e38 	.word	0x00008e38
    5254:	00008e14 	.word	0x00008e14

00005258 <init_idle_thread>:
} /* LCOV_EXCL_LINE ... because we just dumped final coverage data */

#if defined(CONFIG_MULTITHREADING)
__boot_func
static void init_idle_thread(int i)
{
    5258:	b5f0      	push	{r4, r5, r6, r7, lr}
    525a:	b089      	sub	sp, #36	; 0x24
    525c:	4604      	mov	r4, r0
	struct k_thread *thread = &z_idle_threads[i];
    525e:	4b15      	ldr	r3, [pc, #84]	; (52b4 <init_idle_thread+0x5c>)
    5260:	25b0      	movs	r5, #176	; 0xb0
    5262:	fb05 3500 	mla	r5, r5, r0, r3
	k_thread_stack_t *stack = z_idle_stacks[i];
    5266:	eb00 0380 	add.w	r3, r0, r0, lsl #2
    526a:	4e13      	ldr	r6, [pc, #76]	; (52b8 <init_idle_thread+0x60>)
    526c:	eb06 1683 	add.w	r6, r6, r3, lsl #6

#ifdef CONFIG_THREAD_NAME
	char tname[8];

	snprintk(tname, 8, "idle %02d", i);
    5270:	af06      	add	r7, sp, #24
    5272:	4603      	mov	r3, r0
    5274:	4a11      	ldr	r2, [pc, #68]	; (52bc <init_idle_thread+0x64>)
    5276:	2108      	movs	r1, #8
    5278:	4638      	mov	r0, r7
    527a:	f001 fb6d 	bl	6958 <snprintk>
#else
	char *tname = NULL;
#endif /* CONFIG_THREAD_NAME */

	z_setup_new_thread(thread, stack,
			  CONFIG_IDLE_STACK_SIZE, idle, &_kernel.cpus[i],
    527e:	eb04 0444 	add.w	r4, r4, r4, lsl #1
    5282:	480f      	ldr	r0, [pc, #60]	; (52c0 <init_idle_thread+0x68>)
    5284:	eb00 04c4 	add.w	r4, r0, r4, lsl #3
	z_setup_new_thread(thread, stack,
    5288:	9705      	str	r7, [sp, #20]
    528a:	2301      	movs	r3, #1
    528c:	9304      	str	r3, [sp, #16]
    528e:	230f      	movs	r3, #15
    5290:	9303      	str	r3, [sp, #12]
    5292:	2300      	movs	r3, #0
    5294:	9302      	str	r3, [sp, #8]
    5296:	9301      	str	r3, [sp, #4]
    5298:	9400      	str	r4, [sp, #0]
    529a:	4b0a      	ldr	r3, [pc, #40]	; (52c4 <init_idle_thread+0x6c>)
    529c:	f44f 72a0 	mov.w	r2, #320	; 0x140
    52a0:	4631      	mov	r1, r6
    52a2:	4628      	mov	r0, r5
    52a4:	f000 f95a 	bl	555c <z_setup_new_thread>
	SYS_PORT_TRACING_FUNC(k_thread, sched_resume, thread);
}

static inline void z_mark_thread_as_started(struct k_thread *thread)
{
	thread->base.thread_state &= ~_THREAD_PRESTART;
    52a8:	7b6b      	ldrb	r3, [r5, #13]
    52aa:	f023 0304 	bic.w	r3, r3, #4
    52ae:	736b      	strb	r3, [r5, #13]
	z_mark_thread_as_started(thread);

#ifdef CONFIG_SMP
	thread->base.is_idle = 1U;
#endif
}
    52b0:	b009      	add	sp, #36	; 0x24
    52b2:	bdf0      	pop	{r4, r5, r6, r7, pc}
    52b4:	200001e0 	.word	0x200001e0
    52b8:	20001290 	.word	0x20001290
    52bc:	00008e50 	.word	0x00008e50
    52c0:	20000b2c 	.word	0x20000b2c
    52c4:	00007b89 	.word	0x00007b89

000052c8 <prepare_multithreading>:
 *
 * @return initial stack pointer for the main thread
 */
__boot_func
static char *prepare_multithreading(void)
{
    52c8:	b570      	push	{r4, r5, r6, lr}
    52ca:	b086      	sub	sp, #24
	char *stack_ptr;

	/* _kernel.ready_q is all zeroes */
	z_sched_init();
    52cc:	f000 ff78 	bl	61c0 <z_sched_init>
	 * - the main thread will be the one to run first
	 * - no other thread is initialized yet and thus their priority fields
	 *   contain garbage, which would prevent the cache loading algorithm
	 *   to work as intended
	 */
	_kernel.ready_q.cache = &z_main_thread;
    52d0:	4d1a      	ldr	r5, [pc, #104]	; (533c <prepare_multithreading+0x74>)
    52d2:	4b1b      	ldr	r3, [pc, #108]	; (5340 <prepare_multithreading+0x78>)
    52d4:	61dd      	str	r5, [r3, #28]
#endif
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    52d6:	4b1b      	ldr	r3, [pc, #108]	; (5344 <prepare_multithreading+0x7c>)
    52d8:	9305      	str	r3, [sp, #20]
    52da:	2301      	movs	r3, #1
    52dc:	9304      	str	r3, [sp, #16]
    52de:	2400      	movs	r4, #0
    52e0:	9403      	str	r4, [sp, #12]
    52e2:	9402      	str	r4, [sp, #8]
    52e4:	9401      	str	r4, [sp, #4]
    52e6:	9400      	str	r4, [sp, #0]
    52e8:	4b17      	ldr	r3, [pc, #92]	; (5348 <prepare_multithreading+0x80>)
    52ea:	f44f 6280 	mov.w	r2, #1024	; 0x400
    52ee:	4917      	ldr	r1, [pc, #92]	; (534c <prepare_multithreading+0x84>)
    52f0:	4628      	mov	r0, r5
    52f2:	f000 f933 	bl	555c <z_setup_new_thread>
    52f6:	4606      	mov	r6, r0
    52f8:	7b6b      	ldrb	r3, [r5, #13]
    52fa:	f023 0304 	bic.w	r3, r3, #4
    52fe:	736b      	strb	r3, [r5, #13]
				       CONFIG_MAIN_STACK_SIZE, bg_thread_main,
				       NULL, NULL, NULL,
				       CONFIG_MAIN_THREAD_PRIORITY,
				       K_ESSENTIAL, "main");
	z_mark_thread_as_started(&z_main_thread);
	z_ready_thread(&z_main_thread);
    5300:	4628      	mov	r0, r5
    5302:	f002 fcea 	bl	7cda <z_ready_thread>

	for (int i = 0; i < CONFIG_MP_NUM_CPUS; i++) {
    5306:	2c00      	cmp	r4, #0
    5308:	dd02      	ble.n	5310 <prepare_multithreading+0x48>
			(Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[i]) +
			 K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[i]));
	}

	return stack_ptr;
}
    530a:	4630      	mov	r0, r6
    530c:	b006      	add	sp, #24
    530e:	bd70      	pop	{r4, r5, r6, pc}
		init_idle_thread(i);
    5310:	4620      	mov	r0, r4
    5312:	f7ff ffa1 	bl	5258 <init_idle_thread>
		_kernel.cpus[i].idle_thread = &z_idle_threads[i];
    5316:	4b0e      	ldr	r3, [pc, #56]	; (5350 <prepare_multithreading+0x88>)
    5318:	22b0      	movs	r2, #176	; 0xb0
    531a:	fb02 3204 	mla	r2, r2, r4, r3
    531e:	eb04 0144 	add.w	r1, r4, r4, lsl #1
    5322:	4b07      	ldr	r3, [pc, #28]	; (5340 <prepare_multithreading+0x78>)
    5324:	eb03 03c1 	add.w	r3, r3, r1, lsl #3
    5328:	60da      	str	r2, [r3, #12]
		_kernel.cpus[i].id = i;
    532a:	751c      	strb	r4, [r3, #20]
			(Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[i]) +
    532c:	4a09      	ldr	r2, [pc, #36]	; (5354 <prepare_multithreading+0x8c>)
    532e:	eb02 22c4 	add.w	r2, r2, r4, lsl #11
    5332:	f502 6200 	add.w	r2, r2, #2048	; 0x800
		_kernel.cpus[i].irq_stack =
    5336:	605a      	str	r2, [r3, #4]
	for (int i = 0; i < CONFIG_MP_NUM_CPUS; i++) {
    5338:	3401      	adds	r4, #1
    533a:	e7e4      	b.n	5306 <prepare_multithreading+0x3e>
    533c:	20000290 	.word	0x20000290
    5340:	20000b2c 	.word	0x20000b2c
    5344:	00008e5c 	.word	0x00008e5c
    5348:	00005359 	.word	0x00005359
    534c:	20000e90 	.word	0x20000e90
    5350:	200001e0 	.word	0x200001e0
    5354:	200013d0 	.word	0x200013d0

00005358 <bg_thread_main>:
{
    5358:	b508      	push	{r3, lr}
	z_sys_post_kernel = true;
    535a:	4b0b      	ldr	r3, [pc, #44]	; (5388 <bg_thread_main+0x30>)
    535c:	2201      	movs	r2, #1
    535e:	701a      	strb	r2, [r3, #0]
	z_sys_init_run_level(_SYS_INIT_LEVEL_POST_KERNEL);
    5360:	2002      	movs	r0, #2
    5362:	f7ff fe81 	bl	5068 <z_sys_init_run_level>
	boot_banner();
    5366:	f001 fa83 	bl	6870 <boot_banner>
	z_cpp_init_static();
    536a:	f001 ff80 	bl	726e <z_cpp_init_static>
	z_sys_init_run_level(_SYS_INIT_LEVEL_APPLICATION);
    536e:	2003      	movs	r0, #3
    5370:	f7ff fe7a 	bl	5068 <z_sys_init_run_level>
	z_init_static_threads();
    5374:	f000 f956 	bl	5624 <z_init_static_threads>
	main();
    5378:	f7fb f84e 	bl	418 <main>
	z_main_thread.base.user_options &= ~K_ESSENTIAL;
    537c:	4a03      	ldr	r2, [pc, #12]	; (538c <bg_thread_main+0x34>)
    537e:	7b13      	ldrb	r3, [r2, #12]
    5380:	f023 0301 	bic.w	r3, r3, #1
    5384:	7313      	strb	r3, [r2, #12]
} /* LCOV_EXCL_LINE ... because we just dumped final coverage data */
    5386:	bd08      	pop	{r3, pc}
    5388:	20000b8a 	.word	0x20000b8a
    538c:	20000290 	.word	0x20000290

00005390 <switch_to_main_thread>:

__boot_func
static FUNC_NORETURN void switch_to_main_thread(char *stack_ptr)
{
    5390:	b508      	push	{r3, lr}
    5392:	4601      	mov	r1, r0
#ifdef CONFIG_ARCH_HAS_CUSTOM_SWAP_TO_MAIN
	arch_switch_to_main_thread(&z_main_thread, stack_ptr, bg_thread_main);
    5394:	4a01      	ldr	r2, [pc, #4]	; (539c <switch_to_main_thread+0xc>)
    5396:	4802      	ldr	r0, [pc, #8]	; (53a0 <switch_to_main_thread+0x10>)
    5398:	f7fc ffe0 	bl	235c <arch_switch_to_main_thread>
	 * current fake thread is not on a wait queue or ready queue, so it
	 * will never be rescheduled in.
	 */
	z_swap_unlocked();
#endif
	CODE_UNREACHABLE; /* LCOV_EXCL_LINE */
    539c:	00005359 	.word	0x00005359
    53a0:	20000290 	.word	0x20000290

000053a4 <z_bss_zero>:
{
    53a4:	b508      	push	{r3, lr}
	(void)memset(__bss_start, 0, __bss_end - __bss_start);
    53a6:	4803      	ldr	r0, [pc, #12]	; (53b4 <z_bss_zero+0x10>)
__ssp_bos_icheck3(memset, void *, int)
    53a8:	4a03      	ldr	r2, [pc, #12]	; (53b8 <z_bss_zero+0x14>)
    53aa:	1a12      	subs	r2, r2, r0
    53ac:	2100      	movs	r1, #0
    53ae:	f002 fe72 	bl	8096 <memset>
}
    53b2:	bd08      	pop	{r3, pc}
    53b4:	200000d8 	.word	0x200000d8
    53b8:	20000b8c 	.word	0x20000b8c

000053bc <z_cstart>:
 *
 * @return Does not return
 */
__boot_func
FUNC_NORETURN void z_cstart(void)
{
    53bc:	b500      	push	{lr}
    53be:	b0ad      	sub	sp, #180	; 0xb4
	/* gcov hook needed to get the coverage report.*/
	gcov_static_init();

	LOG_CORE_INIT();
    53c0:	f7fb ff3c 	bl	123c <log_core_init>
 *
 * @return N/A
 */
static ALWAYS_INLINE void z_arm_interrupt_stack_setup(void)
{
	uint32_t msp =
    53c4:	4b1c      	ldr	r3, [pc, #112]	; (5438 <z_cstart+0x7c>)
  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
    53c6:	f383 8808 	msr	MSP, r3
	 * for Cortex-M3 and Cortex-M4 (ARMv7-M) MCUs. For the rest
	 * of ARM Cortex-M processors this setting is enforced by
	 * default and it is not configurable.
	 */
#if defined(CONFIG_CPU_CORTEX_M3) || defined(CONFIG_CPU_CORTEX_M4)
	SCB->CCR |= SCB_CCR_STKALIGN_Msk;
    53ca:	4c1c      	ldr	r4, [pc, #112]	; (543c <z_cstart+0x80>)
    53cc:	6963      	ldr	r3, [r4, #20]
    53ce:	f443 7300 	orr.w	r3, r3, #512	; 0x200
    53d2:	6163      	str	r3, [r4, #20]
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    53d4:	23e0      	movs	r3, #224	; 0xe0
    53d6:	f884 3022 	strb.w	r3, [r4, #34]	; 0x22
    53da:	2500      	movs	r5, #0
    53dc:	77e5      	strb	r5, [r4, #31]
    53de:	7625      	strb	r5, [r4, #24]
    53e0:	7665      	strb	r5, [r4, #25]
    53e2:	76a5      	strb	r5, [r4, #26]
    53e4:	f884 5020 	strb.w	r5, [r4, #32]
#if defined(CONFIG_ARM_SECURE_FIRMWARE)
	NVIC_SetPriority(SecureFault_IRQn, _EXC_FAULT_PRIO);
#endif /* CONFIG_ARM_SECURE_FIRMWARE */

	/* Enable Usage, Mem, & Bus Faults */
	SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk |
    53e8:	6a63      	ldr	r3, [r4, #36]	; 0x24
    53ea:	f443 23e0 	orr.w	r3, r3, #458752	; 0x70000
    53ee:	6263      	str	r3, [r4, #36]	; 0x24
    53f0:	f884 5023 	strb.w	r5, [r4, #35]	; 0x23

static ALWAYS_INLINE void arch_kernel_init(void)
{
	z_arm_interrupt_stack_setup();
	z_arm_exc_setup();
	z_arm_fault_init();
    53f4:	f7fd fb8e 	bl	2b14 <z_arm_fault_init>
	z_arm_cpu_idle_init();
    53f8:	f7fc fe7e 	bl	20f8 <z_arm_cpu_idle_init>
static ALWAYS_INLINE void z_arm_clear_faults(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* Reset all faults */
	SCB->CFSR = SCB_CFSR_USGFAULTSR_Msk |
    53fc:	f04f 33ff 	mov.w	r3, #4294967295
    5400:	62a3      	str	r3, [r4, #40]	; 0x28
		    SCB_CFSR_MEMFAULTSR_Msk |
		    SCB_CFSR_BUSFAULTSR_Msk;

	/* Clear all Hard Faults - HFSR is write-one-to-clear */
	SCB->HFSR = 0xffffffff;
    5402:	62e3      	str	r3, [r4, #44]	; 0x2c
	z_arm_clear_faults();
#if defined(CONFIG_ARM_MPU)
	z_arm_mpu_init();
    5404:	f7fd fcc8 	bl	2d98 <z_arm_mpu_init>
	 * to set up access permissions for fixed memory sections, such
	 * as Application Memory or No-Cacheable SRAM area.
	 *
	 * This function is invoked once, upon system initialization.
	 */
	z_arm_configure_static_mpu_regions();
    5408:	f7fd fc2a 	bl	2c60 <z_arm_configure_static_mpu_regions>
 *
 * The memory of the dummy thread can be completely uninitialized.
 */
static inline void z_dummy_thread_init(struct k_thread *dummy_thread)
{
	dummy_thread->base.thread_state = _THREAD_DUMMY;
    540c:	2401      	movs	r4, #1
    540e:	f88d 400d 	strb.w	r4, [sp, #13]
#ifdef CONFIG_SCHED_CPU_MASK
	dummy_thread->base.cpu_mask = -1;
#endif
	dummy_thread->base.user_options = K_ESSENTIAL;
    5412:	f88d 400c 	strb.w	r4, [sp, #12]
#ifdef CONFIG_THREAD_STACK_INFO
	dummy_thread->stack_info.start = 0U;
    5416:	9526      	str	r5, [sp, #152]	; 0x98
	dummy_thread->stack_info.size = 0U;
    5418:	9527      	str	r5, [sp, #156]	; 0x9c
#endif
#ifdef CONFIG_USERSPACE
	dummy_thread->mem_domain_info.mem_domain = &k_mem_domain_default;
#endif

	_current_cpu->current = dummy_thread;
    541a:	4b09      	ldr	r3, [pc, #36]	; (5440 <z_cstart+0x84>)
    541c:	f8c3 d008 	str.w	sp, [r3, #8]
	struct k_thread dummy_thread;

	z_dummy_thread_init(&dummy_thread);
#endif
	/* do any necessary initialization of static devices */
	z_device_state_init();
    5420:	f7ff fe16 	bl	5050 <z_device_state_init>

	/* perform basic hardware initialization */
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_1);
    5424:	4628      	mov	r0, r5
    5426:	f7ff fe1f 	bl	5068 <z_sys_init_run_level>
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_2);
    542a:	4620      	mov	r0, r4
    542c:	f7ff fe1c 	bl	5068 <z_sys_init_run_level>
	timing_init();
	timing_start();
#endif

#ifdef CONFIG_MULTITHREADING
	switch_to_main_thread(prepare_multithreading());
    5430:	f7ff ff4a 	bl	52c8 <prepare_multithreading>
    5434:	f7ff ffac 	bl	5390 <switch_to_main_thread>
    5438:	20001bd0 	.word	0x20001bd0
    543c:	e000ed00 	.word	0xe000ed00
    5440:	20000b2c 	.word	0x20000b2c

00005444 <init_mem_slab_module>:
 * Perform any initialization that wasn't done at build time.
 *
 * @return N/A
 */
static int init_mem_slab_module(const struct device *dev)
{
    5444:	b510      	push	{r4, lr}
	int rc = 0;
	ARG_UNUSED(dev);

	STRUCT_SECTION_FOREACH(k_mem_slab, slab) {
    5446:	4c06      	ldr	r4, [pc, #24]	; (5460 <init_mem_slab_module+0x1c>)
	int rc = 0;
    5448:	2000      	movs	r0, #0
	STRUCT_SECTION_FOREACH(k_mem_slab, slab) {
    544a:	4b06      	ldr	r3, [pc, #24]	; (5464 <init_mem_slab_module+0x20>)
    544c:	429c      	cmp	r4, r3
    544e:	d206      	bcs.n	545e <init_mem_slab_module+0x1a>
		rc = create_free_list(slab);
    5450:	4620      	mov	r0, r4
    5452:	f002 fafc 	bl	7a4e <create_free_list>
		if (rc < 0) {
    5456:	2800      	cmp	r0, #0
    5458:	db01      	blt.n	545e <init_mem_slab_module+0x1a>
	STRUCT_SECTION_FOREACH(k_mem_slab, slab) {
    545a:	3420      	adds	r4, #32
    545c:	e7f5      	b.n	544a <init_mem_slab_module+0x6>
		z_object_init(slab);
	}

out:
	return rc;
}
    545e:	bd10      	pop	{r4, pc}
    5460:	200000b0 	.word	0x200000b0
    5464:	200000b0 	.word	0x200000b0

00005468 <k_mem_slab_alloc>:

	return rc;
}

int k_mem_slab_alloc(struct k_mem_slab *slab, void **mem, k_timeout_t timeout)
{
    5468:	b5f0      	push	{r4, r5, r6, r7, lr}
    546a:	b083      	sub	sp, #12
    546c:	460c      	mov	r4, r1
    546e:	461f      	mov	r7, r3
	__asm__ volatile(
    5470:	f04f 0320 	mov.w	r3, #32
    5474:	f3ef 8111 	mrs	r1, BASEPRI
    5478:	f383 8812 	msr	BASEPRI_MAX, r3
    547c:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&slab->lock);
	int result;

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_mem_slab, alloc, slab, timeout);

	if (slab->free_list != NULL) {
    5480:	6983      	ldr	r3, [r0, #24]
    5482:	b16b      	cbz	r3, 54a0 <k_mem_slab_alloc+0x38>
		/* take a free block */
		*mem = slab->free_list;
    5484:	6023      	str	r3, [r4, #0]
		slab->free_list = *(char **)(slab->free_list);
    5486:	6983      	ldr	r3, [r0, #24]
    5488:	681b      	ldr	r3, [r3, #0]
    548a:	6183      	str	r3, [r0, #24]
		slab->num_used++;
    548c:	69c3      	ldr	r3, [r0, #28]
    548e:	3301      	adds	r3, #1
    5490:	61c3      	str	r3, [r0, #28]

#ifdef CONFIG_MEM_SLAB_TRACE_MAX_UTILIZATION
		slab->max_used = MAX(slab->num_used, slab->max_used);
#endif

		result = 0;
    5492:	2000      	movs	r0, #0
	__asm__ volatile(
    5494:	f381 8811 	msr	BASEPRI, r1
    5498:	f3bf 8f6f 	isb	sy
	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mem_slab, alloc, slab, timeout, result);

	k_spin_unlock(&slab->lock, key);

	return result;
}
    549c:	b003      	add	sp, #12
    549e:	bdf0      	pop	{r4, r5, r6, r7, pc}
    54a0:	4616      	mov	r6, r2
    54a2:	f100 0508 	add.w	r5, r0, #8
	} else if (K_TIMEOUT_EQ(timeout, K_NO_WAIT) ||
    54a6:	ea56 0307 	orrs.w	r3, r6, r7
    54aa:	d104      	bne.n	54b6 <k_mem_slab_alloc+0x4e>
		*mem = NULL;
    54ac:	2300      	movs	r3, #0
    54ae:	6023      	str	r3, [r4, #0]
		result = -ENOMEM;
    54b0:	f06f 000b 	mvn.w	r0, #11
    54b4:	e7ee      	b.n	5494 <k_mem_slab_alloc+0x2c>
		result = z_pend_curr(&slab->lock, key, &slab->wait_q, timeout);
    54b6:	e9cd 6700 	strd	r6, r7, [sp]
    54ba:	4602      	mov	r2, r0
    54bc:	4628      	mov	r0, r5
    54be:	f000 fd55 	bl	5f6c <z_pend_curr>
		if (result == 0) {
    54c2:	2800      	cmp	r0, #0
    54c4:	d1ea      	bne.n	549c <k_mem_slab_alloc+0x34>
			*mem = _current->base.swap_data;
    54c6:	4b02      	ldr	r3, [pc, #8]	; (54d0 <k_mem_slab_alloc+0x68>)
    54c8:	689b      	ldr	r3, [r3, #8]
    54ca:	695b      	ldr	r3, [r3, #20]
    54cc:	6023      	str	r3, [r4, #0]
		return result;
    54ce:	e7e5      	b.n	549c <k_mem_slab_alloc+0x34>
    54d0:	20000b2c 	.word	0x20000b2c

000054d4 <z_thread_monitor_exit>:
	__asm__ volatile(
    54d4:	f04f 0320 	mov.w	r3, #32
    54d8:	f3ef 8111 	mrs	r1, BASEPRI
    54dc:	f383 8812 	msr	BASEPRI_MAX, r3
    54e0:	f3bf 8f6f 	isb	sy
 */
void z_thread_monitor_exit(struct k_thread *thread)
{
	k_spinlock_key_t key = k_spin_lock(&z_thread_monitor_lock);

	if (thread == _kernel.threads) {
    54e4:	4b0a      	ldr	r3, [pc, #40]	; (5510 <z_thread_monitor_exit+0x3c>)
    54e6:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    54e8:	4283      	cmp	r3, r0
    54ea:	d104      	bne.n	54f6 <z_thread_monitor_exit+0x22>
		_kernel.threads = _kernel.threads->next_thread;
    54ec:	6f1a      	ldr	r2, [r3, #112]	; 0x70
    54ee:	4b08      	ldr	r3, [pc, #32]	; (5510 <z_thread_monitor_exit+0x3c>)
    54f0:	629a      	str	r2, [r3, #40]	; 0x28
    54f2:	e007      	b.n	5504 <z_thread_monitor_exit+0x30>
		struct k_thread *prev_thread;

		prev_thread = _kernel.threads;
		while ((prev_thread != NULL) &&
			(thread != prev_thread->next_thread)) {
			prev_thread = prev_thread->next_thread;
    54f4:	4613      	mov	r3, r2
		while ((prev_thread != NULL) &&
    54f6:	b113      	cbz	r3, 54fe <z_thread_monitor_exit+0x2a>
			(thread != prev_thread->next_thread)) {
    54f8:	6f1a      	ldr	r2, [r3, #112]	; 0x70
		while ((prev_thread != NULL) &&
    54fa:	4282      	cmp	r2, r0
    54fc:	d1fa      	bne.n	54f4 <z_thread_monitor_exit+0x20>
		}
		if (prev_thread != NULL) {
    54fe:	b10b      	cbz	r3, 5504 <z_thread_monitor_exit+0x30>
			prev_thread->next_thread = thread->next_thread;
    5500:	6f02      	ldr	r2, [r0, #112]	; 0x70
    5502:	671a      	str	r2, [r3, #112]	; 0x70
	__asm__ volatile(
    5504:	f381 8811 	msr	BASEPRI, r1
    5508:	f3bf 8f6f 	isb	sy
		}
	}

	k_spin_unlock(&z_thread_monitor_lock, key);
}
    550c:	4770      	bx	lr
    550e:	bf00      	nop
    5510:	20000b2c 	.word	0x20000b2c

00005514 <z_impl_k_thread_name_set>:
#endif

int z_impl_k_thread_name_set(struct k_thread *thread, const char *value)
{
    5514:	b510      	push	{r4, lr}
#ifdef CONFIG_THREAD_NAME
	if (thread == NULL) {
    5516:	4604      	mov	r4, r0
    5518:	b140      	cbz	r0, 552c <z_impl_k_thread_name_set+0x18>
__ssp_bos_icheck3_restrict(strncpy, char *, const char *)
    551a:	2220      	movs	r2, #32
    551c:	f104 0074 	add.w	r0, r4, #116	; 0x74
    5520:	f002 fdc1 	bl	80a6 <strncpy>
		thread = _current;
	}

	strncpy(thread->name, value, CONFIG_THREAD_MAX_NAME_LEN);
	thread->name[CONFIG_THREAD_MAX_NAME_LEN - 1] = '\0';
    5524:	2000      	movs	r0, #0
    5526:	f884 0093 	strb.w	r0, [r4, #147]	; 0x93

	SYS_PORT_TRACING_OBJ_FUNC(k_thread, name_set, thread, -ENOSYS);

	return -ENOSYS;
#endif /* CONFIG_THREAD_NAME */
}
    552a:	bd10      	pop	{r4, pc}
		thread = _current;
    552c:	4b01      	ldr	r3, [pc, #4]	; (5534 <z_impl_k_thread_name_set+0x20>)
    552e:	689c      	ldr	r4, [r3, #8]
    5530:	e7f3      	b.n	551a <z_impl_k_thread_name_set+0x6>
    5532:	bf00      	nop
    5534:	20000b2c 	.word	0x20000b2c

00005538 <schedule_new_thread>:
#endif
#endif

#ifdef CONFIG_MULTITHREADING
static void schedule_new_thread(struct k_thread *thread, k_timeout_t delay)
{
    5538:	b538      	push	{r3, r4, r5, lr}
    553a:	4614      	mov	r4, r2
    553c:	461d      	mov	r5, r3
#ifdef CONFIG_SYS_CLOCK_EXISTS
	if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) {
    553e:	ea54 0305 	orrs.w	r3, r4, r5
    5542:	d102      	bne.n	554a <schedule_new_thread+0x12>
	z_impl_k_thread_start(thread);
    5544:	f002 fae9 	bl	7b1a <z_impl_k_thread_start>
	}
#else
	ARG_UNUSED(delay);
	k_thread_start(thread);
#endif
}
    5548:	bd38      	pop	{r3, r4, r5, pc}

extern void z_thread_timeout(struct _timeout *timeout);

static inline void z_add_thread_timeout(struct k_thread *thread, k_timeout_t ticks)
{
	z_add_timeout(&thread->base.timeout, z_thread_timeout, ticks);
    554a:	462b      	mov	r3, r5
    554c:	4902      	ldr	r1, [pc, #8]	; (5558 <schedule_new_thread+0x20>)
    554e:	3018      	adds	r0, #24
    5550:	f000 ffb6 	bl	64c0 <z_add_timeout>
    5554:	e7f8      	b.n	5548 <schedule_new_thread+0x10>
    5556:	bf00      	nop
    5558:	00007d13 	.word	0x00007d13

0000555c <z_setup_new_thread>:
char *z_setup_new_thread(struct k_thread *new_thread,
			 k_thread_stack_t *stack, size_t stack_size,
			 k_thread_entry_t entry,
			 void *p1, void *p2, void *p3,
			 int prio, uint32_t options, const char *name)
{
    555c:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    5560:	b085      	sub	sp, #20
    5562:	4604      	mov	r4, r0
    5564:	460f      	mov	r7, r1
    5566:	4615      	mov	r5, r2
    5568:	461e      	mov	r6, r3
    556a:	f8dd a038 	ldr.w	sl, [sp, #56]	; 0x38
    556e:	f8dd 903c 	ldr.w	r9, [sp, #60]	; 0x3c
    5572:	f8dd 8040 	ldr.w	r8, [sp, #64]	; 0x40
    5576:	f8dd b04c 	ldr.w	fp, [sp, #76]	; 0x4c
	SYS_DLIST_FOR_EACH_CONTAINER(&((wq)->waitq), thread_ptr, \
				     base.qnode_dlist)

static inline void z_waitq_init(_wait_q_t *w)
{
	sys_dlist_init(&w->waitq);
    557a:	f100 0358 	add.w	r3, r0, #88	; 0x58
 * @return N/A
 */

static inline void sys_dlist_init(sys_dlist_t *list)
{
	list->head = (sys_dnode_t *)list;
    557e:	6583      	str	r3, [r0, #88]	; 0x58
	list->tail = (sys_dnode_t *)list;
    5580:	65c3      	str	r3, [r0, #92]	; 0x5c
	k_object_access_grant(new_thread, new_thread);
#endif
	z_waitq_init(&new_thread->join_queue);

	/* Initialize various struct k_thread members */
	z_init_thread_base(&new_thread->base, prio, _THREAD_PRESTART, options);
    5582:	9b12      	ldr	r3, [sp, #72]	; 0x48
    5584:	2204      	movs	r2, #4
    5586:	9911      	ldr	r1, [sp, #68]	; 0x44
    5588:	f002 facb 	bl	7b22 <z_init_thread_base>
	stack_ptr = setup_thread_stack(new_thread, stack, stack_size);
    558c:	462a      	mov	r2, r5
    558e:	4639      	mov	r1, r7
    5590:	4620      	mov	r0, r4
    5592:	f002 faae 	bl	7af2 <setup_thread_stack>
    5596:	4605      	mov	r5, r0
	 */
	__ASSERT_NO_MSG(arch_mem_coherent(new_thread));
	__ASSERT_NO_MSG(!arch_mem_coherent(stack));
#endif

	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    5598:	f8cd 8008 	str.w	r8, [sp, #8]
    559c:	f8cd 9004 	str.w	r9, [sp, #4]
    55a0:	f8cd a000 	str.w	sl, [sp]
    55a4:	4633      	mov	r3, r6
    55a6:	4602      	mov	r2, r0
    55a8:	4639      	mov	r1, r7
    55aa:	4620      	mov	r0, r4
    55ac:	f7fc feb6 	bl	231c <arch_new_thread>

	/* static threads overwrite it afterwards with real value */
	new_thread->init_data = NULL;
    55b0:	2300      	movs	r3, #0
    55b2:	6563      	str	r3, [r4, #84]	; 0x54
#ifdef CONFIG_THREAD_CUSTOM_DATA
	/* Initialize custom data field (value is opaque to kernel) */
	new_thread->custom_data = NULL;
#endif
#ifdef CONFIG_THREAD_MONITOR
	new_thread->entry.pEntry = entry;
    55b4:	6626      	str	r6, [r4, #96]	; 0x60
	new_thread->entry.parameter1 = p1;
    55b6:	f8c4 a064 	str.w	sl, [r4, #100]	; 0x64
	new_thread->entry.parameter2 = p2;
    55ba:	f8c4 9068 	str.w	r9, [r4, #104]	; 0x68
	new_thread->entry.parameter3 = p3;
    55be:	f8c4 806c 	str.w	r8, [r4, #108]	; 0x6c
	__asm__ volatile(
    55c2:	f04f 0320 	mov.w	r3, #32
    55c6:	f3ef 8211 	mrs	r2, BASEPRI
    55ca:	f383 8812 	msr	BASEPRI_MAX, r3
    55ce:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&z_thread_monitor_lock);

	new_thread->next_thread = _kernel.threads;
    55d2:	4b13      	ldr	r3, [pc, #76]	; (5620 <z_setup_new_thread+0xc4>)
    55d4:	6a99      	ldr	r1, [r3, #40]	; 0x28
    55d6:	6721      	str	r1, [r4, #112]	; 0x70
	_kernel.threads = new_thread;
    55d8:	629c      	str	r4, [r3, #40]	; 0x28
	__asm__ volatile(
    55da:	f382 8811 	msr	BASEPRI, r2
    55de:	f3bf 8f6f 	isb	sy
	k_spin_unlock(&z_thread_monitor_lock, key);
#endif
#ifdef CONFIG_THREAD_NAME
	if (name != NULL) {
    55e2:	f1bb 0f00 	cmp.w	fp, #0
    55e6:	d013      	beq.n	5610 <z_setup_new_thread+0xb4>
    55e8:	221f      	movs	r2, #31
    55ea:	4659      	mov	r1, fp
    55ec:	f104 0074 	add.w	r0, r4, #116	; 0x74
    55f0:	f002 fd59 	bl	80a6 <strncpy>
		strncpy(new_thread->name, name,
			CONFIG_THREAD_MAX_NAME_LEN - 1);
		/* Ensure NULL termination, truncate if longer */
		new_thread->name[CONFIG_THREAD_MAX_NAME_LEN - 1] = '\0';
    55f4:	2300      	movs	r3, #0
    55f6:	f884 3093 	strb.w	r3, [r4, #147]	; 0x93
#ifdef CONFIG_SCHED_CPU_MASK
	new_thread->base.cpu_mask = -1;
#endif
#ifdef CONFIG_ARCH_HAS_CUSTOM_SWAP_TO_MAIN
	/* _current may be null if the dummy thread is not used */
	if (!_current) {
    55fa:	4b09      	ldr	r3, [pc, #36]	; (5620 <z_setup_new_thread+0xc4>)
    55fc:	689b      	ldr	r3, [r3, #8]
    55fe:	b15b      	cbz	r3, 5618 <z_setup_new_thread+0xbc>
	}
#endif
#ifdef CONFIG_SCHED_DEADLINE
	new_thread->base.prio_deadline = 0;
#endif
	new_thread->resource_pool = _current->resource_pool;
    5600:	f8d3 30a4 	ldr.w	r3, [r3, #164]	; 0xa4
    5604:	f8c4 30a4 	str.w	r3, [r4, #164]	; 0xa4
#ifdef CONFIG_THREAD_RUNTIME_STATS
	memset(&new_thread->rt_stats, 0, sizeof(new_thread->rt_stats));
#endif

	return stack_ptr;
}
    5608:	4628      	mov	r0, r5
    560a:	b005      	add	sp, #20
    560c:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		new_thread->name[0] = '\0';
    5610:	2300      	movs	r3, #0
    5612:	f884 3074 	strb.w	r3, [r4, #116]	; 0x74
    5616:	e7f0      	b.n	55fa <z_setup_new_thread+0x9e>
		new_thread->resource_pool = NULL;
    5618:	f8c4 30a4 	str.w	r3, [r4, #164]	; 0xa4
		return stack_ptr;
    561c:	e7f4      	b.n	5608 <z_setup_new_thread+0xac>
    561e:	bf00      	nop
    5620:	20000b2c 	.word	0x20000b2c

00005624 <z_init_static_threads>:
	}
}
#endif /* CONFIG_USERSPACE */

void z_init_static_threads(void)
{
    5624:	e92d 4370 	stmdb	sp!, {r4, r5, r6, r8, r9, lr}
    5628:	b086      	sub	sp, #24
	_FOREACH_STATIC_THREAD(thread_data) {
    562a:	4c23      	ldr	r4, [pc, #140]	; (56b8 <z_init_static_threads+0x94>)
    562c:	4b23      	ldr	r3, [pc, #140]	; (56bc <z_init_static_threads+0x98>)
    562e:	429c      	cmp	r4, r3
    5630:	d215      	bcs.n	565e <z_init_static_threads+0x3a>
		z_setup_new_thread(
    5632:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
    5634:	9305      	str	r3, [sp, #20]
    5636:	6a23      	ldr	r3, [r4, #32]
    5638:	9304      	str	r3, [sp, #16]
    563a:	69e3      	ldr	r3, [r4, #28]
    563c:	9303      	str	r3, [sp, #12]
    563e:	69a3      	ldr	r3, [r4, #24]
    5640:	9302      	str	r3, [sp, #8]
    5642:	6963      	ldr	r3, [r4, #20]
    5644:	9301      	str	r3, [sp, #4]
    5646:	6923      	ldr	r3, [r4, #16]
    5648:	9300      	str	r3, [sp, #0]
    564a:	68e3      	ldr	r3, [r4, #12]
    564c:	68a2      	ldr	r2, [r4, #8]
    564e:	6861      	ldr	r1, [r4, #4]
    5650:	6820      	ldr	r0, [r4, #0]
    5652:	f7ff ff83 	bl	555c <z_setup_new_thread>
			thread_data->init_p3,
			thread_data->init_prio,
			thread_data->init_options,
			thread_data->init_name);

		thread_data->init_thread->init_data = thread_data;
    5656:	6823      	ldr	r3, [r4, #0]
    5658:	655c      	str	r4, [r3, #84]	; 0x54
	_FOREACH_STATIC_THREAD(thread_data) {
    565a:	3430      	adds	r4, #48	; 0x30
    565c:	e7e6      	b.n	562c <z_init_static_threads+0x8>
	 * until they are all started.
	 *
	 * Note that static threads defined using the legacy API have a
	 * delay of K_FOREVER.
	 */
	k_sched_lock();
    565e:	f000 fb3d 	bl	5cdc <k_sched_lock>
	_FOREACH_STATIC_THREAD(thread_data) {
    5662:	4c15      	ldr	r4, [pc, #84]	; (56b8 <z_init_static_threads+0x94>)
    5664:	e01b      	b.n	569e <z_init_static_threads+0x7a>
		if (thread_data->init_delay != K_TICKS_FOREVER) {
			schedule_new_thread(thread_data->init_thread,
    5666:	6826      	ldr	r6, [r4, #0]
					    K_MSEC(thread_data->init_delay));
    5668:	ea23 73e3 	bic.w	r3, r3, r3, asr #31
    566c:	ea4f 79e3 	mov.w	r9, r3, asr #31
		} else {
			return (t * to_hz + off) / from_hz;
    5670:	ea4f 31c9 	mov.w	r1, r9, lsl #15
    5674:	ea41 4153 	orr.w	r1, r1, r3, lsr #17
    5678:	03d8      	lsls	r0, r3, #15
    567a:	f240 35e7 	movw	r5, #999	; 0x3e7
    567e:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    5682:	2300      	movs	r3, #0
    5684:	1940      	adds	r0, r0, r5
    5686:	f04f 0500 	mov.w	r5, #0
    568a:	eb45 0101 	adc.w	r1, r5, r1
    568e:	f7fa fd37 	bl	100 <__aeabi_uldivmod>
    5692:	4602      	mov	r2, r0
    5694:	460b      	mov	r3, r1
			schedule_new_thread(thread_data->init_thread,
    5696:	4630      	mov	r0, r6
    5698:	f7ff ff4e 	bl	5538 <schedule_new_thread>
	_FOREACH_STATIC_THREAD(thread_data) {
    569c:	3430      	adds	r4, #48	; 0x30
    569e:	4b07      	ldr	r3, [pc, #28]	; (56bc <z_init_static_threads+0x98>)
    56a0:	429c      	cmp	r4, r3
    56a2:	d204      	bcs.n	56ae <z_init_static_threads+0x8a>
		if (thread_data->init_delay != K_TICKS_FOREVER) {
    56a4:	6a63      	ldr	r3, [r4, #36]	; 0x24
    56a6:	f1b3 3fff 	cmp.w	r3, #4294967295
    56aa:	d0f7      	beq.n	569c <z_init_static_threads+0x78>
    56ac:	e7db      	b.n	5666 <z_init_static_threads+0x42>
		}
	}
	k_sched_unlock();
    56ae:	f000 fd13 	bl	60d8 <k_sched_unlock>
}
    56b2:	b006      	add	sp, #24
    56b4:	e8bd 8370 	ldmia.w	sp!, {r4, r5, r6, r8, r9, pc}
    56b8:	20000078 	.word	0x20000078
    56bc:	20000078 	.word	0x20000078

000056c0 <pm_save_idle>:
 *
 * Sets the kernel data structure idle field to either a positive value or
 * K_FOREVER.
 */
static void pm_save_idle(void)
{
    56c0:	b508      	push	{r3, lr}
#ifdef CONFIG_PM
	int32_t ticks = z_get_next_timeout_expiry();
    56c2:	f002 fc63 	bl	7f8c <z_get_next_timeout_expiry>
	_kernel.idle = ticks;
    56c6:	4b04      	ldr	r3, [pc, #16]	; (56d8 <pm_save_idle+0x18>)
    56c8:	6198      	str	r0, [r3, #24]
	 * before exiting. This is because the kernel does not do its own idle
	 * processing in those cases i.e. skips k_cpu_idle(). The kernel's
	 * idle processing re-enables interrupts which is essential for
	 * the kernel's scheduling logic.
	 */
	if (pm_system_suspend(ticks) == PM_STATE_ACTIVE) {
    56ca:	f7fc fcb1 	bl	2030 <pm_system_suspend>
    56ce:	b100      	cbz	r0, 56d2 <pm_save_idle+0x12>
		k_cpu_idle();
	}
#endif
}
    56d0:	bd08      	pop	{r3, pc}
	arch_cpu_idle();
    56d2:	f7fc fd17 	bl	2104 <arch_cpu_idle>
    56d6:	e7fb      	b.n	56d0 <pm_save_idle+0x10>
    56d8:	20000b2c 	.word	0x20000b2c

000056dc <z_impl_k_mutex_lock>:
	}
	return false;
}

int z_impl_k_mutex_lock(struct k_mutex *mutex, k_timeout_t timeout)
{
    56dc:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
    56e0:	b083      	sub	sp, #12
    56e2:	4604      	mov	r4, r0
    56e4:	461d      	mov	r5, r3
	__asm__ volatile(
    56e6:	f04f 0320 	mov.w	r3, #32
    56ea:	f3ef 8711 	mrs	r7, BASEPRI
    56ee:	f383 8812 	msr	BASEPRI_MAX, r3
    56f2:	f3bf 8f6f 	isb	sy

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_mutex, lock, mutex, timeout);

	key = k_spin_lock(&lock);

	if (likely((mutex->lock_count == 0U) || (mutex->owner == _current))) {
    56f6:	68c1      	ldr	r1, [r0, #12]
    56f8:	b999      	cbnz	r1, 5722 <z_impl_k_mutex_lock+0x46>

		mutex->owner_orig_prio = (mutex->lock_count == 0U) ?
					_current->base.prio :
    56fa:	2900      	cmp	r1, #0
    56fc:	d14f      	bne.n	579e <z_impl_k_mutex_lock+0xc2>
    56fe:	4b3a      	ldr	r3, [pc, #232]	; (57e8 <z_impl_k_mutex_lock+0x10c>)
    5700:	689b      	ldr	r3, [r3, #8]
    5702:	f993 300e 	ldrsb.w	r3, [r3, #14]
		mutex->owner_orig_prio = (mutex->lock_count == 0U) ?
    5706:	6123      	str	r3, [r4, #16]
					mutex->owner_orig_prio;

		mutex->lock_count++;
    5708:	3101      	adds	r1, #1
    570a:	60e1      	str	r1, [r4, #12]
		mutex->owner = _current;
    570c:	4b36      	ldr	r3, [pc, #216]	; (57e8 <z_impl_k_mutex_lock+0x10c>)
    570e:	689b      	ldr	r3, [r3, #8]
    5710:	60a3      	str	r3, [r4, #8]
	__asm__ volatile(
    5712:	f387 8811 	msr	BASEPRI, r7
    5716:	f3bf 8f6f 	isb	sy

		k_spin_unlock(&lock, key);

		SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mutex, lock, mutex, timeout, 0);

		return 0;
    571a:	2000      	movs	r0, #0
	}

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mutex, lock, mutex, timeout, -EAGAIN);

	return -EAGAIN;
}
    571c:	b003      	add	sp, #12
    571e:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
    5722:	4616      	mov	r6, r2
	if (likely((mutex->lock_count == 0U) || (mutex->owner == _current))) {
    5724:	6882      	ldr	r2, [r0, #8]
    5726:	4b30      	ldr	r3, [pc, #192]	; (57e8 <z_impl_k_mutex_lock+0x10c>)
    5728:	689b      	ldr	r3, [r3, #8]
    572a:	429a      	cmp	r2, r3
    572c:	d0e5      	beq.n	56fa <z_impl_k_mutex_lock+0x1e>
	if (unlikely(K_TIMEOUT_EQ(timeout, K_NO_WAIT))) {
    572e:	ea55 0106 	orrs.w	r1, r5, r6
    5732:	bf0c      	ite	eq
    5734:	f04f 0801 	moveq.w	r8, #1
    5738:	f04f 0800 	movne.w	r8, #0
    573c:	d031      	beq.n	57a2 <z_impl_k_mutex_lock+0xc6>
					    mutex->owner->base.prio);
    573e:	f992 900e 	ldrsb.w	r9, [r2, #14]
	new_prio = new_prio_for_inheritance(_current->base.prio,
    5742:	4649      	mov	r1, r9
    5744:	f993 000e 	ldrsb.w	r0, [r3, #14]
    5748:	f002 fa2a 	bl	7ba0 <new_prio_for_inheritance>
	if (z_is_prio_higher(new_prio, mutex->owner->base.prio)) {
    574c:	4581      	cmp	r9, r0
    574e:	dc2f      	bgt.n	57b0 <z_impl_k_mutex_lock+0xd4>
	bool resched = false;
    5750:	f04f 0900 	mov.w	r9, #0
	int got_mutex = z_pend_curr(&lock, key, &mutex->wait_q, timeout);
    5754:	9600      	str	r6, [sp, #0]
    5756:	9501      	str	r5, [sp, #4]
    5758:	4622      	mov	r2, r4
    575a:	4639      	mov	r1, r7
    575c:	4823      	ldr	r0, [pc, #140]	; (57ec <z_impl_k_mutex_lock+0x110>)
    575e:	f000 fc05 	bl	5f6c <z_pend_curr>
	if (got_mutex == 0) {
    5762:	2800      	cmp	r0, #0
    5764:	d0da      	beq.n	571c <z_impl_k_mutex_lock+0x40>
	__asm__ volatile(
    5766:	f04f 0320 	mov.w	r3, #32
    576a:	f3ef 8511 	mrs	r5, BASEPRI
    576e:	f383 8812 	msr	BASEPRI_MAX, r3
    5772:	f3bf 8f6f 	isb	sy
 * @return true if empty, false otherwise
 */

static inline bool sys_dlist_is_empty(sys_dlist_t *list)
{
	return list->head == list;
    5776:	6823      	ldr	r3, [r4, #0]
 * @return a pointer to the head element, NULL if list is empty
 */

static inline sys_dnode_t *sys_dlist_peek_head(sys_dlist_t *list)
{
	return sys_dlist_is_empty(list) ? NULL : list->head;
    5778:	42a3      	cmp	r3, r4
    577a:	d01f      	beq.n	57bc <z_impl_k_mutex_lock+0xe0>
		new_prio_for_inheritance(waiter->base.prio, mutex->owner_orig_prio) :
    577c:	b1f3      	cbz	r3, 57bc <z_impl_k_mutex_lock+0xe0>
    577e:	6921      	ldr	r1, [r4, #16]
    5780:	f993 000e 	ldrsb.w	r0, [r3, #14]
    5784:	f002 fa0c 	bl	7ba0 <new_prio_for_inheritance>
    5788:	4601      	mov	r1, r0
	resched = adjust_owner_prio(mutex, new_prio) || resched;
    578a:	4620      	mov	r0, r4
    578c:	f002 fa13 	bl	7bb6 <adjust_owner_prio>
    5790:	b9b0      	cbnz	r0, 57c0 <z_impl_k_mutex_lock+0xe4>
    5792:	f1b9 0f00 	cmp.w	r9, #0
    5796:	d015      	beq.n	57c4 <z_impl_k_mutex_lock+0xe8>
    5798:	f04f 0801 	mov.w	r8, #1
    579c:	e012      	b.n	57c4 <z_impl_k_mutex_lock+0xe8>
					_current->base.prio :
    579e:	6923      	ldr	r3, [r4, #16]
    57a0:	e7b1      	b.n	5706 <z_impl_k_mutex_lock+0x2a>
	__asm__ volatile(
    57a2:	f387 8811 	msr	BASEPRI, r7
    57a6:	f3bf 8f6f 	isb	sy
		return -EBUSY;
    57aa:	f06f 000f 	mvn.w	r0, #15
    57ae:	e7b5      	b.n	571c <z_impl_k_mutex_lock+0x40>
		resched = adjust_owner_prio(mutex, new_prio);
    57b0:	4601      	mov	r1, r0
    57b2:	4620      	mov	r0, r4
    57b4:	f002 f9ff 	bl	7bb6 <adjust_owner_prio>
    57b8:	4681      	mov	r9, r0
    57ba:	e7cb      	b.n	5754 <z_impl_k_mutex_lock+0x78>
		new_prio_for_inheritance(waiter->base.prio, mutex->owner_orig_prio) :
    57bc:	6921      	ldr	r1, [r4, #16]
    57be:	e7e4      	b.n	578a <z_impl_k_mutex_lock+0xae>
	resched = adjust_owner_prio(mutex, new_prio) || resched;
    57c0:	f04f 0801 	mov.w	r8, #1
	if (resched) {
    57c4:	f1b8 0f00 	cmp.w	r8, #0
    57c8:	d106      	bne.n	57d8 <z_impl_k_mutex_lock+0xfc>
    57ca:	f385 8811 	msr	BASEPRI, r5
    57ce:	f3bf 8f6f 	isb	sy
	return -EAGAIN;
    57d2:	f06f 000a 	mvn.w	r0, #10
    57d6:	e7a1      	b.n	571c <z_impl_k_mutex_lock+0x40>
		z_reschedule(&lock, key);
    57d8:	4629      	mov	r1, r5
    57da:	4804      	ldr	r0, [pc, #16]	; (57ec <z_impl_k_mutex_lock+0x110>)
    57dc:	f000 fa62 	bl	5ca4 <z_reschedule>
	return -EAGAIN;
    57e0:	f06f 000a 	mvn.w	r0, #10
    57e4:	e79a      	b.n	571c <z_impl_k_mutex_lock+0x40>
    57e6:	bf00      	nop
    57e8:	20000b2c 	.word	0x20000b2c
    57ec:	20000b58 	.word	0x20000b58

000057f0 <z_impl_k_mutex_unlock>:

	__ASSERT(!arch_is_in_isr(), "mutexes cannot be used inside ISRs");

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_mutex, unlock, mutex);

	CHECKIF(mutex->owner == NULL) {
    57f0:	6882      	ldr	r2, [r0, #8]
    57f2:	2a00      	cmp	r2, #0
    57f4:	d035      	beq.n	5862 <z_impl_k_mutex_unlock+0x72>
{
    57f6:	b538      	push	{r3, r4, r5, lr}
    57f8:	4604      	mov	r4, r0
		return -EINVAL;
	}
	/*
	 * The current thread does not own the mutex.
	 */
	CHECKIF(mutex->owner != _current) {
    57fa:	4b1d      	ldr	r3, [pc, #116]	; (5870 <z_impl_k_mutex_unlock+0x80>)
    57fc:	689b      	ldr	r3, [r3, #8]
    57fe:	429a      	cmp	r2, r3
    5800:	d132      	bne.n	5868 <z_impl_k_mutex_unlock+0x78>
static inline void z_sched_lock(void)
{
	__ASSERT(!arch_is_in_isr(), "");
	__ASSERT(_current->base.sched_locked != 1U, "");

	--_current->base.sched_locked;
    5802:	7bda      	ldrb	r2, [r3, #15]
    5804:	3a01      	subs	r2, #1
    5806:	73da      	strb	r2, [r3, #15]

	/*
	 * If we are the owner and count is greater than 1, then decrement
	 * the count and return and keep current thread as the owner.
	 */
	if (mutex->lock_count > 1U) {
    5808:	68c3      	ldr	r3, [r0, #12]
    580a:	2b01      	cmp	r3, #1
    580c:	d905      	bls.n	581a <z_impl_k_mutex_unlock+0x2a>
		mutex->lock_count--;
    580e:	3b01      	subs	r3, #1
    5810:	60c3      	str	r3, [r0, #12]


k_mutex_unlock_return:
	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mutex, unlock, mutex, 0);

	k_sched_unlock();
    5812:	f000 fc61 	bl	60d8 <k_sched_unlock>

	return 0;
    5816:	2000      	movs	r0, #0
}
    5818:	bd38      	pop	{r3, r4, r5, pc}
	__asm__ volatile(
    581a:	f04f 0320 	mov.w	r3, #32
    581e:	f3ef 8511 	mrs	r5, BASEPRI
    5822:	f383 8812 	msr	BASEPRI_MAX, r3
    5826:	f3bf 8f6f 	isb	sy
	adjust_owner_prio(mutex, mutex->owner_orig_prio);
    582a:	6901      	ldr	r1, [r0, #16]
    582c:	f002 f9c3 	bl	7bb6 <adjust_owner_prio>
	new_owner = z_unpend_first_thread(&mutex->wait_q);
    5830:	4620      	mov	r0, r4
    5832:	f002 fb14 	bl	7e5e <z_unpend_first_thread>
	mutex->owner = new_owner;
    5836:	60a0      	str	r0, [r4, #8]
	if (new_owner != NULL) {
    5838:	b160      	cbz	r0, 5854 <z_impl_k_mutex_unlock+0x64>
		mutex->owner_orig_prio = new_owner->base.prio;
    583a:	f990 300e 	ldrsb.w	r3, [r0, #14]
    583e:	6123      	str	r3, [r4, #16]
}

static ALWAYS_INLINE void
arch_thread_return_value_set(struct k_thread *thread, unsigned int value)
{
	thread->arch.swap_return_value = value;
    5840:	2300      	movs	r3, #0
    5842:	f8c0 30ac 	str.w	r3, [r0, #172]	; 0xac
		z_ready_thread(new_owner);
    5846:	f002 fa48 	bl	7cda <z_ready_thread>
		z_reschedule(&lock, key);
    584a:	4629      	mov	r1, r5
    584c:	4809      	ldr	r0, [pc, #36]	; (5874 <z_impl_k_mutex_unlock+0x84>)
    584e:	f000 fa29 	bl	5ca4 <z_reschedule>
    5852:	e7de      	b.n	5812 <z_impl_k_mutex_unlock+0x22>
		mutex->lock_count = 0U;
    5854:	2300      	movs	r3, #0
    5856:	60e3      	str	r3, [r4, #12]
	__asm__ volatile(
    5858:	f385 8811 	msr	BASEPRI, r5
    585c:	f3bf 8f6f 	isb	sy
    5860:	e7d7      	b.n	5812 <z_impl_k_mutex_unlock+0x22>
		return -EINVAL;
    5862:	f06f 0015 	mvn.w	r0, #21
}
    5866:	4770      	bx	lr
		return -EPERM;
    5868:	f04f 30ff 	mov.w	r0, #4294967295
    586c:	e7d4      	b.n	5818 <z_impl_k_mutex_unlock+0x28>
    586e:	bf00      	nop
    5870:	20000b2c 	.word	0x20000b2c
    5874:	20000b58 	.word	0x20000b58

00005878 <z_impl_k_sem_give>:
	ARG_UNUSED(sem);
#endif
}

void z_impl_k_sem_give(struct k_sem *sem)
{
    5878:	b538      	push	{r3, r4, r5, lr}
    587a:	4604      	mov	r4, r0
	__asm__ volatile(
    587c:	f04f 0320 	mov.w	r3, #32
    5880:	f3ef 8511 	mrs	r5, BASEPRI
    5884:	f383 8812 	msr	BASEPRI_MAX, r3
    5888:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&lock);
	struct k_thread *thread;

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_sem, give, sem);

	thread = z_unpend_first_thread(&sem->wait_q);
    588c:	f002 fae7 	bl	7e5e <z_unpend_first_thread>

	if (thread != NULL) {
    5890:	b148      	cbz	r0, 58a6 <z_impl_k_sem_give+0x2e>
    5892:	2200      	movs	r2, #0
    5894:	f8c0 20ac 	str.w	r2, [r0, #172]	; 0xac
		arch_thread_return_value_set(thread, 0);
		z_ready_thread(thread);
    5898:	f002 fa1f 	bl	7cda <z_ready_thread>
	} else {
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
		handle_poll_events(sem);
	}

	z_reschedule(&lock, key);
    589c:	4629      	mov	r1, r5
    589e:	4807      	ldr	r0, [pc, #28]	; (58bc <z_impl_k_sem_give+0x44>)
    58a0:	f000 fa00 	bl	5ca4 <z_reschedule>

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_sem, give, sem);
}
    58a4:	bd38      	pop	{r3, r4, r5, pc}
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
    58a6:	68a3      	ldr	r3, [r4, #8]
    58a8:	68e2      	ldr	r2, [r4, #12]
    58aa:	4293      	cmp	r3, r2
    58ac:	d003      	beq.n	58b6 <z_impl_k_sem_give+0x3e>
    58ae:	2201      	movs	r2, #1
    58b0:	4413      	add	r3, r2
    58b2:	60a3      	str	r3, [r4, #8]
}
    58b4:	e7f2      	b.n	589c <z_impl_k_sem_give+0x24>
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
    58b6:	2200      	movs	r2, #0
    58b8:	e7fa      	b.n	58b0 <z_impl_k_sem_give+0x38>
    58ba:	bf00      	nop
    58bc:	20000b5c 	.word	0x20000b5c

000058c0 <z_impl_k_sem_take>:
}
#include <syscalls/k_sem_give_mrsh.c>
#endif

int z_impl_k_sem_take(struct k_sem *sem, k_timeout_t timeout)
{
    58c0:	b530      	push	{r4, r5, lr}
    58c2:	b083      	sub	sp, #12
    58c4:	461d      	mov	r5, r3
    58c6:	f04f 0320 	mov.w	r3, #32
    58ca:	f3ef 8111 	mrs	r1, BASEPRI
    58ce:	f383 8812 	msr	BASEPRI_MAX, r3
    58d2:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&lock);

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_sem, take, sem, timeout);

	if (likely(sem->count > 0U)) {
    58d6:	6883      	ldr	r3, [r0, #8]
    58d8:	b143      	cbz	r3, 58ec <z_impl_k_sem_take+0x2c>
		sem->count--;
    58da:	3b01      	subs	r3, #1
    58dc:	6083      	str	r3, [r0, #8]
	__asm__ volatile(
    58de:	f381 8811 	msr	BASEPRI, r1
    58e2:	f3bf 8f6f 	isb	sy
		k_spin_unlock(&lock, key);
		ret = 0;
    58e6:	2000      	movs	r0, #0

out:
	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_sem, take, sem, timeout, ret);

	return ret;
}
    58e8:	b003      	add	sp, #12
    58ea:	bd30      	pop	{r4, r5, pc}
    58ec:	4614      	mov	r4, r2
	if (K_TIMEOUT_EQ(timeout, K_NO_WAIT)) {
    58ee:	ea54 0305 	orrs.w	r3, r4, r5
    58f2:	d006      	beq.n	5902 <z_impl_k_sem_take+0x42>
	ret = z_pend_curr(&lock, key, &sem->wait_q, timeout);
    58f4:	e9cd 4500 	strd	r4, r5, [sp]
    58f8:	4602      	mov	r2, r0
    58fa:	4805      	ldr	r0, [pc, #20]	; (5910 <z_impl_k_sem_take+0x50>)
    58fc:	f000 fb36 	bl	5f6c <z_pend_curr>
	return ret;
    5900:	e7f2      	b.n	58e8 <z_impl_k_sem_take+0x28>
    5902:	f381 8811 	msr	BASEPRI, r1
    5906:	f3bf 8f6f 	isb	sy
		ret = -EBUSY;
    590a:	f06f 000f 	mvn.w	r0, #15
    590e:	e7eb      	b.n	58e8 <z_impl_k_sem_take+0x28>
    5910:	20000b5c 	.word	0x20000b5c

00005914 <submit_to_queue_locked>:
 * @retval -EINVAL if no queue is provided
 * @retval -ENODEV if the queue is not started
 */
static int submit_to_queue_locked(struct k_work *work,
				  struct k_work_q **queuep)
{
    5914:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    5916:	460d      	mov	r5, r1
	return (*flagp & BIT(bit)) != 0U;
    5918:	68c3      	ldr	r3, [r0, #12]
	int ret = 0;

	if (flag_test(&work->flags, K_WORK_CANCELING_BIT)) {
    591a:	f013 0f02 	tst.w	r3, #2
    591e:	d15b      	bne.n	59d8 <submit_to_queue_locked+0xc4>
    5920:	4604      	mov	r4, r0
		/* Disallowed */
		ret = -EBUSY;
	} else if (!flag_test(&work->flags, K_WORK_QUEUED_BIT)) {
    5922:	f013 0f04 	tst.w	r3, #4
    5926:	d15c      	bne.n	59e2 <submit_to_queue_locked+0xce>
		/* Not currently queued */
		ret = 1;

		/* If no queue specified resubmit to last queue.
		 */
		if (*queuep == NULL) {
    5928:	680b      	ldr	r3, [r1, #0]
    592a:	2b00      	cmp	r3, #0
    592c:	d037      	beq.n	599e <submit_to_queue_locked+0x8a>
	return (*flagp & BIT(bit)) != 0U;
    592e:	68e3      	ldr	r3, [r4, #12]

		/* If the work is currently running we have to use the
		 * queue it's running on to prevent handler
		 * re-entrancy.
		 */
		if (flag_test(&work->flags, K_WORK_RUNNING_BIT)) {
    5930:	f013 0f01 	tst.w	r3, #1
    5934:	d036      	beq.n	59a4 <submit_to_queue_locked+0x90>
			__ASSERT_NO_MSG(work->queue != NULL);
			*queuep = work->queue;
    5936:	68a3      	ldr	r3, [r4, #8]
    5938:	602b      	str	r3, [r5, #0]
			ret = 2;
    593a:	2702      	movs	r7, #2
		}

		int rc = queue_submit_locked(*queuep, work);
    593c:	682e      	ldr	r6, [r5, #0]
	if (queue == NULL) {
    593e:	2e00      	cmp	r6, #0
    5940:	d03e      	beq.n	59c0 <submit_to_queue_locked+0xac>
	bool chained = (_current == &queue->thread) && !k_is_in_isr();
    5942:	4b29      	ldr	r3, [pc, #164]	; (59e8 <submit_to_queue_locked+0xd4>)
    5944:	689b      	ldr	r3, [r3, #8]
    5946:	42b3      	cmp	r3, r6
    5948:	d02e      	beq.n	59a8 <submit_to_queue_locked+0x94>
    594a:	2300      	movs	r3, #0
    594c:	461a      	mov	r2, r3
	return (*flagp & BIT(bit)) != 0U;
    594e:	f8d6 30c8 	ldr.w	r3, [r6, #200]	; 0xc8
    5952:	f3c3 0180 	ubfx	r1, r3, #2, #1
    5956:	f3c3 00c0 	ubfx	r0, r3, #3, #1
	if (!flag_test(&queue->flags, K_WORK_QUEUE_STARTED_BIT)) {
    595a:	f013 0f01 	tst.w	r3, #1
    595e:	d032      	beq.n	59c6 <submit_to_queue_locked+0xb2>
	} else if (draining && !chained) {
    5960:	b101      	cbz	r1, 5964 <submit_to_queue_locked+0x50>
    5962:	b39a      	cbz	r2, 59cc <submit_to_queue_locked+0xb8>
	} else if (plugged && !draining) {
    5964:	b100      	cbz	r0, 5968 <submit_to_queue_locked+0x54>
    5966:	b3a1      	cbz	r1, 59d2 <submit_to_queue_locked+0xbe>
	parent->next = child;
    5968:	2300      	movs	r3, #0
    596a:	6023      	str	r3, [r4, #0]
	return list->tail;
    596c:	f8d6 30b4 	ldr.w	r3, [r6, #180]	; 0xb4
 * @param node A pointer on the node to append
 */
static inline void sys_slist_append(sys_slist_t *list,
				    sys_snode_t *node);

Z_GENLIST_APPEND(slist, snode)
    5970:	b30b      	cbz	r3, 59b6 <submit_to_queue_locked+0xa2>
	parent->next = child;
    5972:	601c      	str	r4, [r3, #0]
	list->tail = node;
    5974:	f8c6 40b4 	str.w	r4, [r6, #180]	; 0xb4
		rv = z_sched_wake(&queue->notifyq, 0, NULL);
    5978:	2200      	movs	r2, #0
    597a:	4611      	mov	r1, r2
    597c:	f106 00b8 	add.w	r0, r6, #184	; 0xb8
    5980:	f002 fa98 	bl	7eb4 <z_sched_wake>
		ret = 1;
    5984:	2001      	movs	r0, #1

		if (rc < 0) {
    5986:	2800      	cmp	r0, #0
    5988:	db06      	blt.n	5998 <submit_to_queue_locked+0x84>
	*flagp |= BIT(bit);
    598a:	68e3      	ldr	r3, [r4, #12]
    598c:	f043 0304 	orr.w	r3, r3, #4
    5990:	60e3      	str	r3, [r4, #12]
			ret = rc;
		} else {
			flag_set(&work->flags, K_WORK_QUEUED_BIT);
			work->queue = *queuep;
    5992:	682b      	ldr	r3, [r5, #0]
    5994:	60a3      	str	r3, [r4, #8]
    5996:	4638      	mov	r0, r7
		}
	} else {
		/* Already queued, do nothing. */
	}

	if (ret <= 0) {
    5998:	2800      	cmp	r0, #0
    599a:	dc21      	bgt.n	59e0 <submit_to_queue_locked+0xcc>
    599c:	e01e      	b.n	59dc <submit_to_queue_locked+0xc8>
			*queuep = work->queue;
    599e:	6883      	ldr	r3, [r0, #8]
    59a0:	600b      	str	r3, [r1, #0]
    59a2:	e7c4      	b.n	592e <submit_to_queue_locked+0x1a>
		ret = 1;
    59a4:	2701      	movs	r7, #1
    59a6:	e7c9      	b.n	593c <submit_to_queue_locked+0x28>
	bool chained = (_current == &queue->thread) && !k_is_in_isr();
    59a8:	f002 f8af 	bl	7b0a <k_is_in_isr>
    59ac:	b908      	cbnz	r0, 59b2 <submit_to_queue_locked+0x9e>
    59ae:	2301      	movs	r3, #1
    59b0:	e7cc      	b.n	594c <submit_to_queue_locked+0x38>
    59b2:	2300      	movs	r3, #0
    59b4:	e7ca      	b.n	594c <submit_to_queue_locked+0x38>
    59b6:	f8c6 40b4 	str.w	r4, [r6, #180]	; 0xb4
	list->head = node;
    59ba:	f8c6 40b0 	str.w	r4, [r6, #176]	; 0xb0
}
    59be:	e7db      	b.n	5978 <submit_to_queue_locked+0x64>
		return -EINVAL;
    59c0:	f06f 0015 	mvn.w	r0, #21
    59c4:	e7df      	b.n	5986 <submit_to_queue_locked+0x72>
		ret = -ENODEV;
    59c6:	f06f 0012 	mvn.w	r0, #18
    59ca:	e7dc      	b.n	5986 <submit_to_queue_locked+0x72>
		ret = -EBUSY;
    59cc:	f06f 000f 	mvn.w	r0, #15
    59d0:	e7d9      	b.n	5986 <submit_to_queue_locked+0x72>
		ret = -EBUSY;
    59d2:	f06f 000f 	mvn.w	r0, #15
    59d6:	e7d6      	b.n	5986 <submit_to_queue_locked+0x72>
		ret = -EBUSY;
    59d8:	f06f 000f 	mvn.w	r0, #15
		*queuep = NULL;
    59dc:	2300      	movs	r3, #0
    59de:	602b      	str	r3, [r5, #0]
	}

	return ret;
}
    59e0:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	int ret = 0;
    59e2:	2000      	movs	r0, #0
    59e4:	e7fa      	b.n	59dc <submit_to_queue_locked+0xc8>
    59e6:	bf00      	nop
    59e8:	20000b2c 	.word	0x20000b2c

000059ec <finalize_cancel_locked>:
{
    59ec:	b570      	push	{r4, r5, r6, lr}
    59ee:	4605      	mov	r5, r0
	*flagp &= ~BIT(bit);
    59f0:	68c3      	ldr	r3, [r0, #12]
    59f2:	f023 0302 	bic.w	r3, r3, #2
    59f6:	60c3      	str	r3, [r0, #12]
	return list->head;
    59f8:	4b19      	ldr	r3, [pc, #100]	; (5a60 <finalize_cancel_locked+0x74>)
    59fa:	6818      	ldr	r0, [r3, #0]
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&pending_cancels, wc, tmp, node) {
    59fc:	b1e8      	cbz	r0, 5a3a <finalize_cancel_locked+0x4e>
    59fe:	4604      	mov	r4, r0
Z_GENLIST_PEEK_NEXT(slist, snode)
    5a00:	b100      	cbz	r0, 5a04 <finalize_cancel_locked+0x18>
	return node->next;
    5a02:	6804      	ldr	r4, [r0, #0]
    5a04:	2600      	movs	r6, #0
    5a06:	e01d      	b.n	5a44 <finalize_cancel_locked+0x58>
 */
static inline void sys_slist_remove(sys_slist_t *list,
				    sys_snode_t *prev_node,
				    sys_snode_t *node);

Z_GENLIST_REMOVE(slist, snode)
    5a08:	b15e      	cbz	r6, 5a22 <finalize_cancel_locked+0x36>
	return node->next;
    5a0a:	6803      	ldr	r3, [r0, #0]
	parent->next = child;
    5a0c:	6033      	str	r3, [r6, #0]
	return list->tail;
    5a0e:	4b14      	ldr	r3, [pc, #80]	; (5a60 <finalize_cancel_locked+0x74>)
    5a10:	685b      	ldr	r3, [r3, #4]
Z_GENLIST_REMOVE(slist, snode)
    5a12:	4298      	cmp	r0, r3
    5a14:	d00e      	beq.n	5a34 <finalize_cancel_locked+0x48>
	parent->next = child;
    5a16:	2300      	movs	r3, #0
    5a18:	f840 3b08 	str.w	r3, [r0], #8
	z_impl_k_sem_give(sem);
    5a1c:	f7ff ff2c 	bl	5878 <z_impl_k_sem_give>
}
    5a20:	e015      	b.n	5a4e <finalize_cancel_locked+0x62>
	return node->next;
    5a22:	6802      	ldr	r2, [r0, #0]
	list->head = node;
    5a24:	4b0e      	ldr	r3, [pc, #56]	; (5a60 <finalize_cancel_locked+0x74>)
    5a26:	601a      	str	r2, [r3, #0]
	return list->tail;
    5a28:	685b      	ldr	r3, [r3, #4]
Z_GENLIST_REMOVE(slist, snode)
    5a2a:	4298      	cmp	r0, r3
    5a2c:	d1f3      	bne.n	5a16 <finalize_cancel_locked+0x2a>
	list->tail = node;
    5a2e:	4b0c      	ldr	r3, [pc, #48]	; (5a60 <finalize_cancel_locked+0x74>)
    5a30:	605a      	str	r2, [r3, #4]
}
    5a32:	e7f0      	b.n	5a16 <finalize_cancel_locked+0x2a>
	list->tail = node;
    5a34:	4b0a      	ldr	r3, [pc, #40]	; (5a60 <finalize_cancel_locked+0x74>)
    5a36:	605e      	str	r6, [r3, #4]
}
    5a38:	e7ed      	b.n	5a16 <finalize_cancel_locked+0x2a>
    5a3a:	4604      	mov	r4, r0
    5a3c:	e7e2      	b.n	5a04 <finalize_cancel_locked+0x18>
    5a3e:	4623      	mov	r3, r4
    5a40:	4620      	mov	r0, r4
    5a42:	461c      	mov	r4, r3
    5a44:	b150      	cbz	r0, 5a5c <finalize_cancel_locked+0x70>
		if (wc->work == work) {
    5a46:	6843      	ldr	r3, [r0, #4]
    5a48:	42ab      	cmp	r3, r5
    5a4a:	d0dd      	beq.n	5a08 <finalize_cancel_locked+0x1c>
			prev = &wc->node;
    5a4c:	4606      	mov	r6, r0
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&pending_cancels, wc, tmp, node) {
    5a4e:	2c00      	cmp	r4, #0
    5a50:	d0f5      	beq.n	5a3e <finalize_cancel_locked+0x52>
    5a52:	4623      	mov	r3, r4
Z_GENLIST_PEEK_NEXT(slist, snode)
    5a54:	2c00      	cmp	r4, #0
    5a56:	d0f3      	beq.n	5a40 <finalize_cancel_locked+0x54>
	return node->next;
    5a58:	6823      	ldr	r3, [r4, #0]
    5a5a:	e7f1      	b.n	5a40 <finalize_cancel_locked+0x54>
}
    5a5c:	bd70      	pop	{r4, r5, r6, pc}
    5a5e:	bf00      	nop
    5a60:	20000b64 	.word	0x20000b64

00005a64 <work_queue_main>:
/* Loop executed by a work queue thread.
 *
 * @param workq_ptr pointer to the work queue structure
 */
static void work_queue_main(void *workq_ptr, void *p2, void *p3)
{
    5a64:	b5f0      	push	{r4, r5, r6, r7, lr}
    5a66:	b085      	sub	sp, #20
    5a68:	4605      	mov	r5, r0
	struct k_work_q *queue = (struct k_work_q *)workq_ptr;
    5a6a:	e016      	b.n	5a9a <work_queue_main+0x36>
	return (*flagp & BIT(bit)) != 0U;
    5a6c:	f8d5 30c8 	ldr.w	r3, [r5, #200]	; 0xc8
	*flagp &= ~BIT(bit);
    5a70:	f023 0204 	bic.w	r2, r3, #4
    5a74:	f8c5 20c8 	str.w	r2, [r5, #200]	; 0xc8
			 * which should never happen, even line 'if (work != NULL)'
			 * ensures that.
			 * This means that if node is not NULL, then work will not be NULL.
			 */
			handler = work->handler;
		} else if (flag_test_and_clear(&queue->flags,
    5a78:	f013 0f04 	tst.w	r3, #4
    5a7c:	d158      	bne.n	5b30 <work_queue_main+0xcc>
			 * the lock, and we didn't find work nor got asked to
			 * stop.  Just go to sleep: when something happens the
			 * work thread will be woken and we can check again.
			 */

			(void)z_sched_wait(&lock, key, &queue->notifyq,
    5a7e:	2300      	movs	r3, #0
    5a80:	9302      	str	r3, [sp, #8]
    5a82:	f04f 32ff 	mov.w	r2, #4294967295
    5a86:	f04f 33ff 	mov.w	r3, #4294967295
    5a8a:	e9cd 2300 	strd	r2, r3, [sp]
    5a8e:	f105 02b8 	add.w	r2, r5, #184	; 0xb8
    5a92:	4631      	mov	r1, r6
    5a94:	482e      	ldr	r0, [pc, #184]	; (5b50 <work_queue_main+0xec>)
    5a96:	f000 fc9f 	bl	63d8 <z_sched_wait>
	__asm__ volatile(
    5a9a:	f04f 0320 	mov.w	r3, #32
    5a9e:	f3ef 8611 	mrs	r6, BASEPRI
    5aa2:	f383 8812 	msr	BASEPRI_MAX, r3
    5aa6:	f3bf 8f6f 	isb	sy
	return list->head;
    5aaa:	f8d5 40b0 	ldr.w	r4, [r5, #176]	; 0xb0
Z_GENLIST_GET(slist, snode)
    5aae:	2c00      	cmp	r4, #0
    5ab0:	d0dc      	beq.n	5a6c <work_queue_main+0x8>
	return node->next;
    5ab2:	6823      	ldr	r3, [r4, #0]
	list->head = node;
    5ab4:	f8c5 30b0 	str.w	r3, [r5, #176]	; 0xb0
	return list->tail;
    5ab8:	f8d5 20b4 	ldr.w	r2, [r5, #180]	; 0xb4
Z_GENLIST_GET_NOT_EMPTY(slist, snode)
    5abc:	4294      	cmp	r4, r2
    5abe:	d034      	beq.n	5b2a <work_queue_main+0xc6>
	*flagp |= BIT(bit);
    5ac0:	f8d5 30c8 	ldr.w	r3, [r5, #200]	; 0xc8
    5ac4:	f043 0302 	orr.w	r3, r3, #2
    5ac8:	f8c5 30c8 	str.w	r3, [r5, #200]	; 0xc8
    5acc:	68e3      	ldr	r3, [r4, #12]
    5ace:	f043 0301 	orr.w	r3, r3, #1
	*flagp &= ~BIT(bit);
    5ad2:	f023 0304 	bic.w	r3, r3, #4
    5ad6:	60e3      	str	r3, [r4, #12]
			handler = work->handler;
    5ad8:	6863      	ldr	r3, [r4, #4]
		if (work == NULL) {
    5ada:	2c00      	cmp	r4, #0
    5adc:	d0cf      	beq.n	5a7e <work_queue_main+0x1a>
	__asm__ volatile(
    5ade:	f386 8811 	msr	BASEPRI, r6
    5ae2:	f3bf 8f6f 	isb	sy

		if (work != NULL) {
			bool yield;

			__ASSERT_NO_MSG(handler != NULL);
			handler(work);
    5ae6:	4620      	mov	r0, r4
    5ae8:	4798      	blx	r3
	__asm__ volatile(
    5aea:	f04f 0320 	mov.w	r3, #32
    5aee:	f3ef 8611 	mrs	r6, BASEPRI
    5af2:	f383 8812 	msr	BASEPRI_MAX, r3
    5af6:	f3bf 8f6f 	isb	sy
	*flagp &= ~BIT(bit);
    5afa:	68e3      	ldr	r3, [r4, #12]
    5afc:	f023 0301 	bic.w	r3, r3, #1
    5b00:	60e3      	str	r3, [r4, #12]
			 * starving other threads.
			 */
			key = k_spin_lock(&lock);

			flag_clear(&work->flags, K_WORK_RUNNING_BIT);
			if (flag_test(&work->flags, K_WORK_CANCELING_BIT)) {
    5b02:	f013 0f02 	tst.w	r3, #2
    5b06:	d11e      	bne.n	5b46 <work_queue_main+0xe2>
	*flagp &= ~BIT(bit);
    5b08:	f8d5 30c8 	ldr.w	r3, [r5, #200]	; 0xc8
    5b0c:	f023 0302 	bic.w	r3, r3, #2
    5b10:	f8c5 30c8 	str.w	r3, [r5, #200]	; 0xc8
	return (*flagp & BIT(bit)) != 0U;
    5b14:	f3c3 2300 	ubfx	r3, r3, #8, #1
	__asm__ volatile(
    5b18:	f386 8811 	msr	BASEPRI, r6
    5b1c:	f3bf 8f6f 	isb	sy
			k_spin_unlock(&lock, key);

			/* Optionally yield to prevent the work queue from
			 * starving other threads.
			 */
			if (yield) {
    5b20:	2b00      	cmp	r3, #0
    5b22:	d1ba      	bne.n	5a9a <work_queue_main+0x36>
	z_impl_k_yield();
    5b24:	f000 fb5a 	bl	61dc <z_impl_k_yield>
}
    5b28:	e7b7      	b.n	5a9a <work_queue_main+0x36>
	list->tail = node;
    5b2a:	f8c5 30b4 	str.w	r3, [r5, #180]	; 0xb4
}
    5b2e:	e7c7      	b.n	5ac0 <work_queue_main+0x5c>
			(void)z_sched_wake_all(&queue->drainq, 1, NULL);
    5b30:	f105 07c0 	add.w	r7, r5, #192	; 0xc0
static inline bool z_sched_wake_all(_wait_q_t *wait_q, int swap_retval,
				    void *swap_data)
{
	bool woken = false;

	while (z_sched_wake(wait_q, swap_retval, swap_data)) {
    5b34:	2200      	movs	r2, #0
    5b36:	2101      	movs	r1, #1
    5b38:	4638      	mov	r0, r7
    5b3a:	f002 f9bb 	bl	7eb4 <z_sched_wake>
    5b3e:	2800      	cmp	r0, #0
    5b40:	d1f8      	bne.n	5b34 <work_queue_main+0xd0>
		k_work_handler_t handler = NULL;
    5b42:	2300      	movs	r3, #0
    5b44:	e7c9      	b.n	5ada <work_queue_main+0x76>
				finalize_cancel_locked(work);
    5b46:	4620      	mov	r0, r4
    5b48:	f7ff ff50 	bl	59ec <finalize_cancel_locked>
    5b4c:	e7dc      	b.n	5b08 <work_queue_main+0xa4>
    5b4e:	bf00      	nop
    5b50:	20000b60 	.word	0x20000b60

00005b54 <k_work_submit>:
{
    5b54:	b508      	push	{r3, lr}
    5b56:	4601      	mov	r1, r0
	int ret = k_work_submit_to_queue(&k_sys_work_q, work);
    5b58:	4801      	ldr	r0, [pc, #4]	; (5b60 <k_work_submit+0xc>)
    5b5a:	f002 f84d 	bl	7bf8 <k_work_submit_to_queue>
}
    5b5e:	bd08      	pop	{r3, pc}
    5b60:	20000348 	.word	0x20000348

00005b64 <k_work_queue_start>:
void k_work_queue_start(struct k_work_q *queue,
			k_thread_stack_t *stack,
			size_t stack_size,
			int prio,
			const struct k_work_queue_config *cfg)
{
    5b64:	b5f0      	push	{r4, r5, r6, r7, lr}
    5b66:	b089      	sub	sp, #36	; 0x24
    5b68:	4604      	mov	r4, r0
    5b6a:	9d0e      	ldr	r5, [sp, #56]	; 0x38
	list->head = NULL;
    5b6c:	2000      	movs	r0, #0
    5b6e:	f8c4 00b0 	str.w	r0, [r4, #176]	; 0xb0
	list->tail = NULL;
    5b72:	f8c4 00b4 	str.w	r0, [r4, #180]	; 0xb4
    5b76:	f104 00b8 	add.w	r0, r4, #184	; 0xb8
	list->head = (sys_dnode_t *)list;
    5b7a:	f8c4 00b8 	str.w	r0, [r4, #184]	; 0xb8
	list->tail = (sys_dnode_t *)list;
    5b7e:	f8c4 00bc 	str.w	r0, [r4, #188]	; 0xbc
    5b82:	f104 00c0 	add.w	r0, r4, #192	; 0xc0
	list->head = (sys_dnode_t *)list;
    5b86:	f8c4 00c0 	str.w	r0, [r4, #192]	; 0xc0
	list->tail = (sys_dnode_t *)list;
    5b8a:	f8c4 00c4 	str.w	r0, [r4, #196]	; 0xc4

	sys_slist_init(&queue->pending);
	z_waitq_init(&queue->notifyq);
	z_waitq_init(&queue->drainq);

	if ((cfg != NULL) && cfg->no_yield) {
    5b8e:	b1fd      	cbz	r5, 5bd0 <k_work_queue_start+0x6c>
    5b90:	7928      	ldrb	r0, [r5, #4]
    5b92:	b9f8      	cbnz	r0, 5bd4 <k_work_queue_start+0x70>
	uint32_t flags = K_WORK_QUEUE_STARTED;
    5b94:	2001      	movs	r0, #1
	*flagp = flags;
    5b96:	f8c4 00c8 	str.w	r0, [r4, #200]	; 0xc8
	return z_impl_k_thread_create(new_thread, stack, stack_size, entry, p1, p2, p3, prio, options, delay);
    5b9a:	f04f 36ff 	mov.w	r6, #4294967295
    5b9e:	f04f 37ff 	mov.w	r7, #4294967295
    5ba2:	e9cd 6706 	strd	r6, r7, [sp, #24]
    5ba6:	2000      	movs	r0, #0
    5ba8:	9004      	str	r0, [sp, #16]
    5baa:	9303      	str	r3, [sp, #12]
    5bac:	9002      	str	r0, [sp, #8]
    5bae:	9001      	str	r0, [sp, #4]
    5bb0:	9400      	str	r4, [sp, #0]
    5bb2:	4b0a      	ldr	r3, [pc, #40]	; (5bdc <k_work_queue_start+0x78>)
    5bb4:	4620      	mov	r0, r4
    5bb6:	f001 ffbf 	bl	7b38 <z_impl_k_thread_create>

	(void)k_thread_create(&queue->thread, stack, stack_size,
			      work_queue_main, queue, NULL, NULL,
			      prio, 0, K_FOREVER);

	if ((cfg != NULL) && (cfg->name != NULL)) {
    5bba:	b125      	cbz	r5, 5bc6 <k_work_queue_start+0x62>
    5bbc:	6829      	ldr	r1, [r5, #0]
    5bbe:	b111      	cbz	r1, 5bc6 <k_work_queue_start+0x62>
	return z_impl_k_thread_name_set(thread, str);
    5bc0:	4620      	mov	r0, r4
    5bc2:	f7ff fca7 	bl	5514 <z_impl_k_thread_name_set>
	z_impl_k_thread_start(thread);
    5bc6:	4620      	mov	r0, r4
    5bc8:	f001 ffa7 	bl	7b1a <z_impl_k_thread_start>
	}

	k_thread_start(&queue->thread);

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_work_queue, start, queue);
}
    5bcc:	b009      	add	sp, #36	; 0x24
    5bce:	bdf0      	pop	{r4, r5, r6, r7, pc}
	uint32_t flags = K_WORK_QUEUE_STARTED;
    5bd0:	2001      	movs	r0, #1
    5bd2:	e7e0      	b.n	5b96 <k_work_queue_start+0x32>
		flags |= K_WORK_QUEUE_NO_YIELD;
    5bd4:	f240 1001 	movw	r0, #257	; 0x101
    5bd8:	e7dd      	b.n	5b96 <k_work_queue_start+0x32>
    5bda:	bf00      	nop
    5bdc:	00005a65 	.word	0x00005a65

00005be0 <add_thread_timeout>:
		z_priq_wait_add(&wait_q->waitq, thread);
	}
}

static void add_thread_timeout(struct k_thread *thread, k_timeout_t timeout)
{
    5be0:	b538      	push	{r3, r4, r5, lr}
	if (!K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    5be2:	f1b3 3fff 	cmp.w	r3, #4294967295
    5be6:	bf08      	it	eq
    5be8:	f1b2 3fff 	cmpeq.w	r2, #4294967295
    5bec:	d100      	bne.n	5bf0 <add_thread_timeout+0x10>
		z_add_thread_timeout(thread, timeout);
	}
}
    5bee:	bd38      	pop	{r3, r4, r5, pc}
    5bf0:	4902      	ldr	r1, [pc, #8]	; (5bfc <add_thread_timeout+0x1c>)
    5bf2:	3018      	adds	r0, #24
    5bf4:	f000 fc64 	bl	64c0 <z_add_timeout>
    5bf8:	e7f9      	b.n	5bee <add_thread_timeout+0xe>
    5bfa:	bf00      	nop
    5bfc:	00007d13 	.word	0x00007d13

00005c00 <z_reset_time_slice>:
{
    5c00:	b508      	push	{r3, lr}
	if (slice_time != 0) {
    5c02:	4b08      	ldr	r3, [pc, #32]	; (5c24 <z_reset_time_slice+0x24>)
    5c04:	681b      	ldr	r3, [r3, #0]
    5c06:	b903      	cbnz	r3, 5c0a <z_reset_time_slice+0xa>
}
    5c08:	bd08      	pop	{r3, pc}
		_current_cpu->slice_ticks = slice_time + sys_clock_elapsed();
    5c0a:	f7fe fc69 	bl	44e0 <sys_clock_elapsed>
    5c0e:	4603      	mov	r3, r0
    5c10:	4a04      	ldr	r2, [pc, #16]	; (5c24 <z_reset_time_slice+0x24>)
    5c12:	6810      	ldr	r0, [r2, #0]
    5c14:	4403      	add	r3, r0
    5c16:	4a04      	ldr	r2, [pc, #16]	; (5c28 <z_reset_time_slice+0x28>)
    5c18:	6113      	str	r3, [r2, #16]
		z_set_timeout_expiry(slice_time, false);
    5c1a:	2100      	movs	r1, #0
    5c1c:	f002 f9cc 	bl	7fb8 <z_set_timeout_expiry>
}
    5c20:	e7f2      	b.n	5c08 <z_reset_time_slice+0x8>
    5c22:	bf00      	nop
    5c24:	20000b78 	.word	0x20000b78
    5c28:	20000b2c 	.word	0x20000b2c

00005c2c <k_sched_time_slice_set>:
{
    5c2c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    5c30:	4606      	mov	r6, r0
    5c32:	4688      	mov	r8, r1
	LOCKED(&sched_spinlock) {
    5c34:	2300      	movs	r3, #0
	__asm__ volatile(
    5c36:	f04f 0220 	mov.w	r2, #32
    5c3a:	f3ef 8711 	mrs	r7, BASEPRI
    5c3e:	f382 8812 	msr	BASEPRI_MAX, r2
    5c42:	f3bf 8f6f 	isb	sy
#endif

#ifdef CONFIG_SPIN_VALIDATE
	z_spin_lock_set_owner(l);
#endif
	return k;
    5c46:	e009      	b.n	5c5c <k_sched_time_slice_set+0x30>
		slice_max_prio = prio;
    5c48:	4b13      	ldr	r3, [pc, #76]	; (5c98 <k_sched_time_slice_set+0x6c>)
    5c4a:	f8c3 8000 	str.w	r8, [r3]
		z_reset_time_slice();
    5c4e:	f7ff ffd7 	bl	5c00 <z_reset_time_slice>
	__asm__ volatile(
    5c52:	f387 8811 	msr	BASEPRI, r7
    5c56:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
    5c5a:	2301      	movs	r3, #1
    5c5c:	b9cb      	cbnz	r3, 5c92 <k_sched_time_slice_set+0x66>
		_current_cpu->slice_ticks = 0;
    5c5e:	2300      	movs	r3, #0
    5c60:	4a0e      	ldr	r2, [pc, #56]	; (5c9c <k_sched_time_slice_set+0x70>)
    5c62:	6113      	str	r3, [r2, #16]
			return (uint32_t)((t * to_hz + off) / from_hz);
    5c64:	0c75      	lsrs	r5, r6, #17
    5c66:	03f4      	lsls	r4, r6, #15
    5c68:	f240 30e7 	movw	r0, #999	; 0x3e7
    5c6c:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    5c70:	2300      	movs	r3, #0
    5c72:	1820      	adds	r0, r4, r0
    5c74:	f04f 0100 	mov.w	r1, #0
    5c78:	eb45 0101 	adc.w	r1, r5, r1
    5c7c:	f7fa fa40 	bl	100 <__aeabi_uldivmod>
		slice_time = k_ms_to_ticks_ceil32(slice);
    5c80:	4b07      	ldr	r3, [pc, #28]	; (5ca0 <k_sched_time_slice_set+0x74>)
    5c82:	6018      	str	r0, [r3, #0]
		if (IS_ENABLED(CONFIG_TICKLESS_KERNEL) && slice > 0) {
    5c84:	2e00      	cmp	r6, #0
    5c86:	dddf      	ble.n	5c48 <k_sched_time_slice_set+0x1c>
			slice_time = MAX(2, slice_time);
    5c88:	2802      	cmp	r0, #2
    5c8a:	bfb8      	it	lt
    5c8c:	2002      	movlt	r0, #2
    5c8e:	6018      	str	r0, [r3, #0]
    5c90:	e7da      	b.n	5c48 <k_sched_time_slice_set+0x1c>
}
    5c92:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    5c96:	bf00      	nop
    5c98:	20000b74 	.word	0x20000b74
    5c9c:	20000b2c 	.word	0x20000b2c
    5ca0:	20000b78 	.word	0x20000b78

00005ca4 <z_reschedule>:
	return new_thread != _current;
#endif
}

void z_reschedule(struct k_spinlock *lock, k_spinlock_key_t key)
{
    5ca4:	b508      	push	{r3, lr}
	if (resched(key.key) && need_swap()) {
    5ca6:	4608      	mov	r0, r1
	return arch_irq_unlocked(key) && !arch_is_in_isr();
    5ca8:	b921      	cbnz	r1, 5cb4 <z_reschedule+0x10>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    5caa:	f3ef 8305 	mrs	r3, IPSR
    5cae:	b913      	cbnz	r3, 5cb6 <z_reschedule+0x12>
    5cb0:	2101      	movs	r1, #1
    5cb2:	e000      	b.n	5cb6 <z_reschedule+0x12>
    5cb4:	2100      	movs	r1, #0
	if (resched(key.key) && need_swap()) {
    5cb6:	f011 0f01 	tst.w	r1, #1
    5cba:	d007      	beq.n	5ccc <z_reschedule+0x28>
	new_thread = _kernel.ready_q.cache;
    5cbc:	4b06      	ldr	r3, [pc, #24]	; (5cd8 <z_reschedule+0x34>)
    5cbe:	69da      	ldr	r2, [r3, #28]
	return new_thread != _current;
    5cc0:	689b      	ldr	r3, [r3, #8]
	if (resched(key.key) && need_swap()) {
    5cc2:	429a      	cmp	r2, r3
    5cc4:	d002      	beq.n	5ccc <z_reschedule+0x28>
	ret = arch_swap(key);
    5cc6:	f7fc fad7 	bl	2278 <arch_swap>
		z_swap(lock, key);
    5cca:	e003      	b.n	5cd4 <z_reschedule+0x30>
    5ccc:	f380 8811 	msr	BASEPRI, r0
    5cd0:	f3bf 8f6f 	isb	sy
	} else {
		k_spin_unlock(lock, key);
	}
}
    5cd4:	bd08      	pop	{r3, pc}
    5cd6:	bf00      	nop
    5cd8:	20000b2c 	.word	0x20000b2c

00005cdc <k_sched_lock>:
	}
}

void k_sched_lock(void)
{
	LOCKED(&sched_spinlock) {
    5cdc:	2300      	movs	r3, #0
	__asm__ volatile(
    5cde:	f04f 0220 	mov.w	r2, #32
    5ce2:	f3ef 8111 	mrs	r1, BASEPRI
    5ce6:	f382 8812 	msr	BASEPRI_MAX, r2
    5cea:	f3bf 8f6f 	isb	sy
    5cee:	b953      	cbnz	r3, 5d06 <k_sched_lock+0x2a>
	--_current->base.sched_locked;
    5cf0:	4b05      	ldr	r3, [pc, #20]	; (5d08 <k_sched_lock+0x2c>)
    5cf2:	689a      	ldr	r2, [r3, #8]
    5cf4:	7bd3      	ldrb	r3, [r2, #15]
    5cf6:	3b01      	subs	r3, #1
    5cf8:	73d3      	strb	r3, [r2, #15]
	__asm__ volatile(
    5cfa:	f381 8811 	msr	BASEPRI, r1
    5cfe:	f3bf 8f6f 	isb	sy
    5d02:	2301      	movs	r3, #1
    5d04:	e7f3      	b.n	5cee <k_sched_lock+0x12>
		SYS_PORT_TRACING_FUNC(k_thread, sched_lock);

		z_sched_lock();
	}
}
    5d06:	4770      	bx	lr
    5d08:	20000b2c 	.word	0x20000b2c

00005d0c <update_cache>:
{
    5d0c:	b538      	push	{r3, r4, r5, lr}
    5d0e:	4604      	mov	r4, r0
	thread = _priq_run_best(&_kernel.ready_q.runq);
    5d10:	480f      	ldr	r0, [pc, #60]	; (5d50 <update_cache+0x44>)
    5d12:	f001 ffdb 	bl	7ccc <z_priq_dumb_best>
	return (thread != NULL) ? thread : _current_cpu->idle_thread;
    5d16:	4605      	mov	r5, r0
    5d18:	b170      	cbz	r0, 5d38 <update_cache+0x2c>
	if (preempt_ok != 0) {
    5d1a:	b984      	cbnz	r4, 5d3e <update_cache+0x32>
	if (z_is_thread_prevented_from_running(_current)) {
    5d1c:	4b0d      	ldr	r3, [pc, #52]	; (5d54 <update_cache+0x48>)
    5d1e:	689b      	ldr	r3, [r3, #8]
	uint8_t state = thread->base.thread_state;
    5d20:	7b5a      	ldrb	r2, [r3, #13]
    5d22:	f012 0f1f 	tst.w	r2, #31
    5d26:	d10a      	bne.n	5d3e <update_cache+0x32>
	return node->next != NULL;
    5d28:	69aa      	ldr	r2, [r5, #24]
	if (IS_ENABLED(CONFIG_SWAP_NONATOMIC)
    5d2a:	b942      	cbnz	r2, 5d3e <update_cache+0x32>
	return thread->base.preempt <= _PREEMPT_THRESHOLD;
    5d2c:	89da      	ldrh	r2, [r3, #14]
	if (is_preempt(_current) || is_metairq(thread)) {
    5d2e:	2a7f      	cmp	r2, #127	; 0x7f
    5d30:	d905      	bls.n	5d3e <update_cache+0x32>
		_kernel.ready_q.cache = _current;
    5d32:	4a08      	ldr	r2, [pc, #32]	; (5d54 <update_cache+0x48>)
    5d34:	61d3      	str	r3, [r2, #28]
    5d36:	e00a      	b.n	5d4e <update_cache+0x42>
	return (thread != NULL) ? thread : _current_cpu->idle_thread;
    5d38:	4b06      	ldr	r3, [pc, #24]	; (5d54 <update_cache+0x48>)
    5d3a:	68dd      	ldr	r5, [r3, #12]
    5d3c:	e7ed      	b.n	5d1a <update_cache+0xe>
		if (thread != _current) {
    5d3e:	4b05      	ldr	r3, [pc, #20]	; (5d54 <update_cache+0x48>)
    5d40:	689b      	ldr	r3, [r3, #8]
    5d42:	42ab      	cmp	r3, r5
    5d44:	d001      	beq.n	5d4a <update_cache+0x3e>
			z_reset_time_slice();
    5d46:	f7ff ff5b 	bl	5c00 <z_reset_time_slice>
		_kernel.ready_q.cache = thread;
    5d4a:	4b02      	ldr	r3, [pc, #8]	; (5d54 <update_cache+0x48>)
    5d4c:	61dd      	str	r5, [r3, #28]
}
    5d4e:	bd38      	pop	{r3, r4, r5, pc}
    5d50:	20000b4c 	.word	0x20000b4c
    5d54:	20000b2c 	.word	0x20000b2c

00005d58 <move_thread_to_end_of_prio_q>:
{
    5d58:	b538      	push	{r3, r4, r5, lr}
    5d5a:	4605      	mov	r5, r0
	return (thread->base.thread_state & state) != 0U;
    5d5c:	7b42      	ldrb	r2, [r0, #13]
	if (z_is_thread_queued(thread)) {
    5d5e:	f990 300d 	ldrsb.w	r3, [r0, #13]
    5d62:	2b00      	cmp	r3, #0
    5d64:	db28      	blt.n	5db8 <move_thread_to_end_of_prio_q+0x60>
	thread->base.thread_state |= _THREAD_QUEUED;
    5d66:	7b6b      	ldrb	r3, [r5, #13]
    5d68:	f063 037f 	orn	r3, r3, #127	; 0x7f
    5d6c:	736b      	strb	r3, [r5, #13]
	return list->head == list;
    5d6e:	4b1a      	ldr	r3, [pc, #104]	; (5dd8 <move_thread_to_end_of_prio_q+0x80>)
    5d70:	f853 4f20 	ldr.w	r4, [r3, #32]!
	return sys_dlist_is_empty(list) ? NULL : list->head;
    5d74:	429c      	cmp	r4, r3
    5d76:	d02d      	beq.n	5dd4 <move_thread_to_end_of_prio_q+0x7c>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    5d78:	b16c      	cbz	r4, 5d96 <move_thread_to_end_of_prio_q+0x3e>
		if (z_sched_prio_cmp(thread, t) > 0) {
    5d7a:	4621      	mov	r1, r4
    5d7c:	4628      	mov	r0, r5
    5d7e:	f001 ff5f 	bl	7c40 <z_sched_prio_cmp>
    5d82:	2800      	cmp	r0, #0
    5d84:	dc20      	bgt.n	5dc8 <move_thread_to_end_of_prio_q+0x70>
 */

static inline sys_dnode_t *sys_dlist_peek_next(sys_dlist_t *list,
					       sys_dnode_t *node)
{
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    5d86:	b134      	cbz	r4, 5d96 <move_thread_to_end_of_prio_q+0x3e>
	return (node == list->tail) ? NULL : node->next;
    5d88:	4b13      	ldr	r3, [pc, #76]	; (5dd8 <move_thread_to_end_of_prio_q+0x80>)
    5d8a:	6a5b      	ldr	r3, [r3, #36]	; 0x24
    5d8c:	429c      	cmp	r4, r3
    5d8e:	d002      	beq.n	5d96 <move_thread_to_end_of_prio_q+0x3e>
    5d90:	6824      	ldr	r4, [r4, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    5d92:	2c00      	cmp	r4, #0
    5d94:	d1f0      	bne.n	5d78 <move_thread_to_end_of_prio_q+0x20>
 * @return N/A
 */

static inline void sys_dlist_append(sys_dlist_t *list, sys_dnode_t *node)
{
	sys_dnode_t *const tail = list->tail;
    5d96:	4b10      	ldr	r3, [pc, #64]	; (5dd8 <move_thread_to_end_of_prio_q+0x80>)
    5d98:	6a5a      	ldr	r2, [r3, #36]	; 0x24

	node->next = list;
    5d9a:	f103 0120 	add.w	r1, r3, #32
    5d9e:	6029      	str	r1, [r5, #0]
	node->prev = tail;
    5da0:	606a      	str	r2, [r5, #4]

	tail->next = node;
    5da2:	6015      	str	r5, [r2, #0]
	list->tail = node;
    5da4:	625d      	str	r5, [r3, #36]	; 0x24
	update_cache(thread == _current);
    5da6:	4b0c      	ldr	r3, [pc, #48]	; (5dd8 <move_thread_to_end_of_prio_q+0x80>)
    5da8:	6898      	ldr	r0, [r3, #8]
    5daa:	42a8      	cmp	r0, r5
    5dac:	bf14      	ite	ne
    5dae:	2000      	movne	r0, #0
    5db0:	2001      	moveq	r0, #1
    5db2:	f7ff ffab 	bl	5d0c <update_cache>
}
    5db6:	bd38      	pop	{r3, r4, r5, pc}
	thread->base.thread_state &= ~_THREAD_QUEUED;
    5db8:	f002 027f 	and.w	r2, r2, #127	; 0x7f
    5dbc:	7342      	strb	r2, [r0, #13]
		_priq_run_remove(pq, thread);
    5dbe:	4601      	mov	r1, r0
    5dc0:	4806      	ldr	r0, [pc, #24]	; (5ddc <move_thread_to_end_of_prio_q+0x84>)
    5dc2:	f001 ff7b 	bl	7cbc <z_priq_dumb_remove>
}
    5dc6:	e7ce      	b.n	5d66 <move_thread_to_end_of_prio_q+0xe>
 * @param successor the position before which "node" will be inserted
 * @param node the element to insert
 */
static inline void sys_dlist_insert(sys_dnode_t *successor, sys_dnode_t *node)
{
	sys_dnode_t *const prev = successor->prev;
    5dc8:	6863      	ldr	r3, [r4, #4]

	node->prev = prev;
    5dca:	606b      	str	r3, [r5, #4]
	node->next = successor;
    5dcc:	602c      	str	r4, [r5, #0]
	prev->next = node;
    5dce:	601d      	str	r5, [r3, #0]
	successor->prev = node;
    5dd0:	6065      	str	r5, [r4, #4]
}
    5dd2:	e7e8      	b.n	5da6 <move_thread_to_end_of_prio_q+0x4e>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    5dd4:	2400      	movs	r4, #0
    5dd6:	e7cf      	b.n	5d78 <move_thread_to_end_of_prio_q+0x20>
    5dd8:	20000b2c 	.word	0x20000b2c
    5ddc:	20000b4c 	.word	0x20000b4c

00005de0 <z_time_slice>:
{
    5de0:	b510      	push	{r4, lr}
	__asm__ volatile(
    5de2:	f04f 0320 	mov.w	r3, #32
    5de6:	f3ef 8411 	mrs	r4, BASEPRI
    5dea:	f383 8812 	msr	BASEPRI_MAX, r3
    5dee:	f3bf 8f6f 	isb	sy
	if (pending_current == _current) {
    5df2:	4b1c      	ldr	r3, [pc, #112]	; (5e64 <z_time_slice+0x84>)
    5df4:	689b      	ldr	r3, [r3, #8]
    5df6:	4a1c      	ldr	r2, [pc, #112]	; (5e68 <z_time_slice+0x88>)
    5df8:	6812      	ldr	r2, [r2, #0]
    5dfa:	4293      	cmp	r3, r2
    5dfc:	d01d      	beq.n	5e3a <z_time_slice+0x5a>
	pending_current = NULL;
    5dfe:	4a1a      	ldr	r2, [pc, #104]	; (5e68 <z_time_slice+0x88>)
    5e00:	2100      	movs	r1, #0
    5e02:	6011      	str	r1, [r2, #0]
	if (slice_time && sliceable(_current)) {
    5e04:	4a19      	ldr	r2, [pc, #100]	; (5e6c <z_time_slice+0x8c>)
    5e06:	6812      	ldr	r2, [r2, #0]
    5e08:	b322      	cbz	r2, 5e54 <z_time_slice+0x74>
	return thread->base.preempt <= _PREEMPT_THRESHOLD;
    5e0a:	89da      	ldrh	r2, [r3, #14]
		&& !z_is_idle_thread_object(thread);
    5e0c:	2a7f      	cmp	r2, #127	; 0x7f
    5e0e:	d821      	bhi.n	5e54 <z_time_slice+0x74>
	uint8_t state = thread->base.thread_state;
    5e10:	7b5a      	ldrb	r2, [r3, #13]
		&& !z_is_thread_prevented_from_running(thread)
    5e12:	f012 0f1f 	tst.w	r2, #31
    5e16:	d11d      	bne.n	5e54 <z_time_slice+0x74>
		&& !z_is_prio_higher(thread->base.prio, slice_max_prio)
    5e18:	f993 100e 	ldrsb.w	r1, [r3, #14]
    5e1c:	4a14      	ldr	r2, [pc, #80]	; (5e70 <z_time_slice+0x90>)
    5e1e:	6812      	ldr	r2, [r2, #0]
    5e20:	4291      	cmp	r1, r2
    5e22:	db17      	blt.n	5e54 <z_time_slice+0x74>
		&& !z_is_idle_thread_object(thread);
    5e24:	4a13      	ldr	r2, [pc, #76]	; (5e74 <z_time_slice+0x94>)
    5e26:	4293      	cmp	r3, r2
    5e28:	d014      	beq.n	5e54 <z_time_slice+0x74>
		if (ticks >= _current_cpu->slice_ticks) {
    5e2a:	4a0e      	ldr	r2, [pc, #56]	; (5e64 <z_time_slice+0x84>)
    5e2c:	6912      	ldr	r2, [r2, #16]
    5e2e:	4282      	cmp	r2, r0
    5e30:	dd0a      	ble.n	5e48 <z_time_slice+0x68>
			_current_cpu->slice_ticks -= ticks;
    5e32:	1a10      	subs	r0, r2, r0
    5e34:	4b0b      	ldr	r3, [pc, #44]	; (5e64 <z_time_slice+0x84>)
    5e36:	6118      	str	r0, [r3, #16]
    5e38:	e00f      	b.n	5e5a <z_time_slice+0x7a>
		z_reset_time_slice();
    5e3a:	f7ff fee1 	bl	5c00 <z_reset_time_slice>
	__asm__ volatile(
    5e3e:	f384 8811 	msr	BASEPRI, r4
    5e42:	f3bf 8f6f 	isb	sy
		return;
    5e46:	e00c      	b.n	5e62 <z_time_slice+0x82>
			move_thread_to_end_of_prio_q(_current);
    5e48:	4618      	mov	r0, r3
    5e4a:	f7ff ff85 	bl	5d58 <move_thread_to_end_of_prio_q>
			z_reset_time_slice();
    5e4e:	f7ff fed7 	bl	5c00 <z_reset_time_slice>
    5e52:	e002      	b.n	5e5a <z_time_slice+0x7a>
		_current_cpu->slice_ticks = 0;
    5e54:	4b03      	ldr	r3, [pc, #12]	; (5e64 <z_time_slice+0x84>)
    5e56:	2200      	movs	r2, #0
    5e58:	611a      	str	r2, [r3, #16]
    5e5a:	f384 8811 	msr	BASEPRI, r4
    5e5e:	f3bf 8f6f 	isb	sy
}
    5e62:	bd10      	pop	{r4, pc}
    5e64:	20000b2c 	.word	0x20000b2c
    5e68:	20000b6c 	.word	0x20000b6c
    5e6c:	20000b78 	.word	0x20000b78
    5e70:	20000b74 	.word	0x20000b74
    5e74:	200001e0 	.word	0x200001e0

00005e78 <ready_thread>:
{
    5e78:	b538      	push	{r3, r4, r5, lr}
	return (thread->base.thread_state & state) != 0U;
    5e7a:	7b43      	ldrb	r3, [r0, #13]
	if (!z_is_thread_queued(thread) && z_is_thread_ready(thread)) {
    5e7c:	f990 200d 	ldrsb.w	r2, [r0, #13]
    5e80:	2a00      	cmp	r2, #0
    5e82:	db2d      	blt.n	5ee0 <ready_thread+0x68>
    5e84:	4604      	mov	r4, r0
	return !((z_is_thread_prevented_from_running(thread)) != 0U ||
    5e86:	f013 0f1f 	tst.w	r3, #31
    5e8a:	d105      	bne.n	5e98 <ready_thread+0x20>
	return node->next != NULL;
    5e8c:	6982      	ldr	r2, [r0, #24]
    5e8e:	b10a      	cbz	r2, 5e94 <ready_thread+0x1c>
    5e90:	2200      	movs	r2, #0
    5e92:	e002      	b.n	5e9a <ready_thread+0x22>
    5e94:	2201      	movs	r2, #1
    5e96:	e000      	b.n	5e9a <ready_thread+0x22>
    5e98:	2200      	movs	r2, #0
    5e9a:	b30a      	cbz	r2, 5ee0 <ready_thread+0x68>
	thread->base.thread_state |= _THREAD_QUEUED;
    5e9c:	f063 037f 	orn	r3, r3, #127	; 0x7f
    5ea0:	7363      	strb	r3, [r4, #13]
	return list->head == list;
    5ea2:	4b14      	ldr	r3, [pc, #80]	; (5ef4 <ready_thread+0x7c>)
    5ea4:	f853 5f20 	ldr.w	r5, [r3, #32]!
	return sys_dlist_is_empty(list) ? NULL : list->head;
    5ea8:	429d      	cmp	r5, r3
    5eaa:	d020      	beq.n	5eee <ready_thread+0x76>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    5eac:	b16d      	cbz	r5, 5eca <ready_thread+0x52>
		if (z_sched_prio_cmp(thread, t) > 0) {
    5eae:	4629      	mov	r1, r5
    5eb0:	4620      	mov	r0, r4
    5eb2:	f001 fec5 	bl	7c40 <z_sched_prio_cmp>
    5eb6:	2800      	cmp	r0, #0
    5eb8:	dc13      	bgt.n	5ee2 <ready_thread+0x6a>
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    5eba:	b135      	cbz	r5, 5eca <ready_thread+0x52>
	return (node == list->tail) ? NULL : node->next;
    5ebc:	4b0d      	ldr	r3, [pc, #52]	; (5ef4 <ready_thread+0x7c>)
    5ebe:	6a5b      	ldr	r3, [r3, #36]	; 0x24
    5ec0:	429d      	cmp	r5, r3
    5ec2:	d002      	beq.n	5eca <ready_thread+0x52>
    5ec4:	682d      	ldr	r5, [r5, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    5ec6:	2d00      	cmp	r5, #0
    5ec8:	d1f0      	bne.n	5eac <ready_thread+0x34>
	sys_dnode_t *const tail = list->tail;
    5eca:	4b0a      	ldr	r3, [pc, #40]	; (5ef4 <ready_thread+0x7c>)
    5ecc:	6a5a      	ldr	r2, [r3, #36]	; 0x24
	node->next = list;
    5ece:	f103 0120 	add.w	r1, r3, #32
    5ed2:	6021      	str	r1, [r4, #0]
	node->prev = tail;
    5ed4:	6062      	str	r2, [r4, #4]
	tail->next = node;
    5ed6:	6014      	str	r4, [r2, #0]
	list->tail = node;
    5ed8:	625c      	str	r4, [r3, #36]	; 0x24
		update_cache(0);
    5eda:	2000      	movs	r0, #0
    5edc:	f7ff ff16 	bl	5d0c <update_cache>
}
    5ee0:	bd38      	pop	{r3, r4, r5, pc}
	sys_dnode_t *const prev = successor->prev;
    5ee2:	686b      	ldr	r3, [r5, #4]
	node->prev = prev;
    5ee4:	6063      	str	r3, [r4, #4]
	node->next = successor;
    5ee6:	6025      	str	r5, [r4, #0]
	prev->next = node;
    5ee8:	601c      	str	r4, [r3, #0]
	successor->prev = node;
    5eea:	606c      	str	r4, [r5, #4]
}
    5eec:	e7f5      	b.n	5eda <ready_thread+0x62>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    5eee:	2500      	movs	r5, #0
    5ef0:	e7dc      	b.n	5eac <ready_thread+0x34>
    5ef2:	bf00      	nop
    5ef4:	20000b2c 	.word	0x20000b2c

00005ef8 <z_sched_start>:
{
    5ef8:	b510      	push	{r4, lr}
	__asm__ volatile(
    5efa:	f04f 0320 	mov.w	r3, #32
    5efe:	f3ef 8411 	mrs	r4, BASEPRI
    5f02:	f383 8812 	msr	BASEPRI_MAX, r3
    5f06:	f3bf 8f6f 	isb	sy
	return (thread->base.thread_state & _THREAD_PRESTART) == 0U;
    5f0a:	7b43      	ldrb	r3, [r0, #13]
	if (z_has_thread_started(thread)) {
    5f0c:	f013 0f04 	tst.w	r3, #4
    5f10:	d104      	bne.n	5f1c <z_sched_start+0x24>
	__asm__ volatile(
    5f12:	f384 8811 	msr	BASEPRI, r4
    5f16:	f3bf 8f6f 	isb	sy
}
    5f1a:	bd10      	pop	{r4, pc}
	thread->base.thread_state &= ~_THREAD_PRESTART;
    5f1c:	f023 0304 	bic.w	r3, r3, #4
    5f20:	7343      	strb	r3, [r0, #13]
	ready_thread(thread);
    5f22:	f7ff ffa9 	bl	5e78 <ready_thread>
	z_reschedule(&sched_spinlock, key);
    5f26:	4621      	mov	r1, r4
    5f28:	4801      	ldr	r0, [pc, #4]	; (5f30 <z_sched_start+0x38>)
    5f2a:	f7ff febb 	bl	5ca4 <z_reschedule>
    5f2e:	e7f4      	b.n	5f1a <z_sched_start+0x22>
    5f30:	20000b70 	.word	0x20000b70

00005f34 <unready_thread>:
{
    5f34:	b510      	push	{r4, lr}
    5f36:	4604      	mov	r4, r0
	return (thread->base.thread_state & state) != 0U;
    5f38:	7b42      	ldrb	r2, [r0, #13]
	if (z_is_thread_queued(thread)) {
    5f3a:	f990 300d 	ldrsb.w	r3, [r0, #13]
    5f3e:	2b00      	cmp	r3, #0
    5f40:	db08      	blt.n	5f54 <unready_thread+0x20>
	update_cache(thread == _current);
    5f42:	4b08      	ldr	r3, [pc, #32]	; (5f64 <unready_thread+0x30>)
    5f44:	6898      	ldr	r0, [r3, #8]
    5f46:	42a0      	cmp	r0, r4
    5f48:	bf14      	ite	ne
    5f4a:	2000      	movne	r0, #0
    5f4c:	2001      	moveq	r0, #1
    5f4e:	f7ff fedd 	bl	5d0c <update_cache>
}
    5f52:	bd10      	pop	{r4, pc}
	thread->base.thread_state &= ~_THREAD_QUEUED;
    5f54:	f002 027f 	and.w	r2, r2, #127	; 0x7f
    5f58:	7342      	strb	r2, [r0, #13]
		_priq_run_remove(pq, thread);
    5f5a:	4601      	mov	r1, r0
    5f5c:	4802      	ldr	r0, [pc, #8]	; (5f68 <unready_thread+0x34>)
    5f5e:	f001 fead 	bl	7cbc <z_priq_dumb_remove>
}
    5f62:	e7ee      	b.n	5f42 <unready_thread+0xe>
    5f64:	20000b2c 	.word	0x20000b2c
    5f68:	20000b4c 	.word	0x20000b4c

00005f6c <z_pend_curr>:
{
    5f6c:	b510      	push	{r4, lr}
    5f6e:	460c      	mov	r4, r1
    5f70:	4611      	mov	r1, r2
	pending_current = _current;
    5f72:	4b06      	ldr	r3, [pc, #24]	; (5f8c <z_pend_curr+0x20>)
    5f74:	6898      	ldr	r0, [r3, #8]
    5f76:	4b06      	ldr	r3, [pc, #24]	; (5f90 <z_pend_curr+0x24>)
    5f78:	6018      	str	r0, [r3, #0]
	pend(_current, wait_q, timeout);
    5f7a:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
    5f7e:	f001 ff26 	bl	7dce <pend>
    5f82:	4620      	mov	r0, r4
    5f84:	f7fc f978 	bl	2278 <arch_swap>
}
    5f88:	bd10      	pop	{r4, pc}
    5f8a:	bf00      	nop
    5f8c:	20000b2c 	.word	0x20000b2c
    5f90:	20000b6c 	.word	0x20000b6c

00005f94 <z_set_prio>:
{
    5f94:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    5f98:	4604      	mov	r4, r0
    5f9a:	460f      	mov	r7, r1
	LOCKED(&sched_spinlock) {
    5f9c:	2300      	movs	r3, #0
	__asm__ volatile(
    5f9e:	f04f 0220 	mov.w	r2, #32
    5fa2:	f3ef 8611 	mrs	r6, BASEPRI
    5fa6:	f382 8812 	msr	BASEPRI_MAX, r2
    5faa:	f3bf 8f6f 	isb	sy
	bool need_sched = 0;
    5fae:	4698      	mov	r8, r3
    5fb0:	e008      	b.n	5fc4 <z_set_prio+0x30>
		if (need_sched) {
    5fb2:	f012 0801 	ands.w	r8, r2, #1
    5fb6:	d111      	bne.n	5fdc <z_set_prio+0x48>
			thread->base.prio = prio;
    5fb8:	73a7      	strb	r7, [r4, #14]
	__asm__ volatile(
    5fba:	f386 8811 	msr	BASEPRI, r6
    5fbe:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
    5fc2:	2301      	movs	r3, #1
    5fc4:	461a      	mov	r2, r3
    5fc6:	2b00      	cmp	r3, #0
    5fc8:	d13d      	bne.n	6046 <z_set_prio+0xb2>
	uint8_t state = thread->base.thread_state;
    5fca:	7b63      	ldrb	r3, [r4, #13]
	return !((z_is_thread_prevented_from_running(thread)) != 0U ||
    5fcc:	f013 0f1f 	tst.w	r3, #31
    5fd0:	d1ef      	bne.n	5fb2 <z_set_prio+0x1e>
	return node->next != NULL;
    5fd2:	69a1      	ldr	r1, [r4, #24]
    5fd4:	2900      	cmp	r1, #0
    5fd6:	d1ec      	bne.n	5fb2 <z_set_prio+0x1e>
    5fd8:	2201      	movs	r2, #1
    5fda:	e7ea      	b.n	5fb2 <z_set_prio+0x1e>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    5fdc:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    5fe0:	7363      	strb	r3, [r4, #13]
		_priq_run_remove(pq, thread);
    5fe2:	f8df 906c 	ldr.w	r9, [pc, #108]	; 6050 <z_set_prio+0xbc>
    5fe6:	4621      	mov	r1, r4
    5fe8:	4648      	mov	r0, r9
    5fea:	f001 fe67 	bl	7cbc <z_priq_dumb_remove>
				thread->base.prio = prio;
    5fee:	73a7      	strb	r7, [r4, #14]
	thread->base.thread_state |= _THREAD_QUEUED;
    5ff0:	7b63      	ldrb	r3, [r4, #13]
    5ff2:	f063 037f 	orn	r3, r3, #127	; 0x7f
    5ff6:	7363      	strb	r3, [r4, #13]
	return list->head == list;
    5ff8:	f8d9 5000 	ldr.w	r5, [r9]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    5ffc:	454d      	cmp	r5, r9
    5ffe:	d020      	beq.n	6042 <z_set_prio+0xae>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    6000:	b16d      	cbz	r5, 601e <z_set_prio+0x8a>
		if (z_sched_prio_cmp(thread, t) > 0) {
    6002:	4629      	mov	r1, r5
    6004:	4620      	mov	r0, r4
    6006:	f001 fe1b 	bl	7c40 <z_sched_prio_cmp>
    600a:	2800      	cmp	r0, #0
    600c:	dc13      	bgt.n	6036 <z_set_prio+0xa2>
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    600e:	b135      	cbz	r5, 601e <z_set_prio+0x8a>
	return (node == list->tail) ? NULL : node->next;
    6010:	4b0e      	ldr	r3, [pc, #56]	; (604c <z_set_prio+0xb8>)
    6012:	6a5b      	ldr	r3, [r3, #36]	; 0x24
    6014:	429d      	cmp	r5, r3
    6016:	d002      	beq.n	601e <z_set_prio+0x8a>
    6018:	682d      	ldr	r5, [r5, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    601a:	2d00      	cmp	r5, #0
    601c:	d1f0      	bne.n	6000 <z_set_prio+0x6c>
	sys_dnode_t *const tail = list->tail;
    601e:	4b0b      	ldr	r3, [pc, #44]	; (604c <z_set_prio+0xb8>)
    6020:	6a5a      	ldr	r2, [r3, #36]	; 0x24
	node->next = list;
    6022:	f103 0120 	add.w	r1, r3, #32
    6026:	6021      	str	r1, [r4, #0]
	node->prev = tail;
    6028:	6062      	str	r2, [r4, #4]
	tail->next = node;
    602a:	6014      	str	r4, [r2, #0]
	list->tail = node;
    602c:	625c      	str	r4, [r3, #36]	; 0x24
			update_cache(1);
    602e:	2001      	movs	r0, #1
    6030:	f7ff fe6c 	bl	5d0c <update_cache>
    6034:	e7c1      	b.n	5fba <z_set_prio+0x26>
	sys_dnode_t *const prev = successor->prev;
    6036:	686b      	ldr	r3, [r5, #4]
	node->prev = prev;
    6038:	6063      	str	r3, [r4, #4]
	node->next = successor;
    603a:	6025      	str	r5, [r4, #0]
	prev->next = node;
    603c:	601c      	str	r4, [r3, #0]
	successor->prev = node;
    603e:	606c      	str	r4, [r5, #4]
}
    6040:	e7f5      	b.n	602e <z_set_prio+0x9a>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    6042:	2500      	movs	r5, #0
    6044:	e7dc      	b.n	6000 <z_set_prio+0x6c>
}
    6046:	4640      	mov	r0, r8
    6048:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
    604c:	20000b2c 	.word	0x20000b2c
    6050:	20000b4c 	.word	0x20000b4c

00006054 <z_impl_k_thread_suspend>:
{
    6054:	b538      	push	{r3, r4, r5, lr}
    6056:	4604      	mov	r4, r0
}

static inline int z_abort_thread_timeout(struct k_thread *thread)
{
	return z_abort_timeout(&thread->base.timeout);
    6058:	3018      	adds	r0, #24
    605a:	f001 ff79 	bl	7f50 <z_abort_timeout>
	LOCKED(&sched_spinlock) {
    605e:	2300      	movs	r3, #0
	__asm__ volatile(
    6060:	f04f 0220 	mov.w	r2, #32
    6064:	f3ef 8511 	mrs	r5, BASEPRI
    6068:	f382 8812 	msr	BASEPRI_MAX, r2
    606c:	f3bf 8f6f 	isb	sy
    6070:	e010      	b.n	6094 <z_impl_k_thread_suspend+0x40>
	thread->base.thread_state |= _THREAD_SUSPENDED;
    6072:	7b63      	ldrb	r3, [r4, #13]
    6074:	f043 0310 	orr.w	r3, r3, #16
    6078:	7363      	strb	r3, [r4, #13]
		update_cache(thread == _current);
    607a:	4b15      	ldr	r3, [pc, #84]	; (60d0 <z_impl_k_thread_suspend+0x7c>)
    607c:	6898      	ldr	r0, [r3, #8]
    607e:	42a0      	cmp	r0, r4
    6080:	bf14      	ite	ne
    6082:	2000      	movne	r0, #0
    6084:	2001      	moveq	r0, #1
    6086:	f7ff fe41 	bl	5d0c <update_cache>
	__asm__ volatile(
    608a:	f385 8811 	msr	BASEPRI, r5
    608e:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
    6092:	2301      	movs	r3, #1
    6094:	b963      	cbnz	r3, 60b0 <z_impl_k_thread_suspend+0x5c>
	return (thread->base.thread_state & state) != 0U;
    6096:	7b62      	ldrb	r2, [r4, #13]
		if (z_is_thread_queued(thread)) {
    6098:	f994 300d 	ldrsb.w	r3, [r4, #13]
    609c:	2b00      	cmp	r3, #0
    609e:	dae8      	bge.n	6072 <z_impl_k_thread_suspend+0x1e>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    60a0:	f002 027f 	and.w	r2, r2, #127	; 0x7f
    60a4:	7362      	strb	r2, [r4, #13]
		_priq_run_remove(pq, thread);
    60a6:	4621      	mov	r1, r4
    60a8:	480a      	ldr	r0, [pc, #40]	; (60d4 <z_impl_k_thread_suspend+0x80>)
    60aa:	f001 fe07 	bl	7cbc <z_priq_dumb_remove>
}
    60ae:	e7e0      	b.n	6072 <z_impl_k_thread_suspend+0x1e>
	if (thread == _current) {
    60b0:	4b07      	ldr	r3, [pc, #28]	; (60d0 <z_impl_k_thread_suspend+0x7c>)
    60b2:	689b      	ldr	r3, [r3, #8]
    60b4:	42a3      	cmp	r3, r4
    60b6:	d000      	beq.n	60ba <z_impl_k_thread_suspend+0x66>
}
    60b8:	bd38      	pop	{r3, r4, r5, pc}
	__asm__ volatile(
    60ba:	f04f 0320 	mov.w	r3, #32
    60be:	f3ef 8011 	mrs	r0, BASEPRI
    60c2:	f383 8812 	msr	BASEPRI_MAX, r3
    60c6:	f3bf 8f6f 	isb	sy
	(void) z_reschedule_irqlock(arch_irq_lock());
    60ca:	f001 fde2 	bl	7c92 <z_reschedule_irqlock>
    60ce:	e7f3      	b.n	60b8 <z_impl_k_thread_suspend+0x64>
    60d0:	20000b2c 	.word	0x20000b2c
    60d4:	20000b4c 	.word	0x20000b4c

000060d8 <k_sched_unlock>:

void k_sched_unlock(void)
{
    60d8:	b510      	push	{r4, lr}
	LOCKED(&sched_spinlock) {
    60da:	2300      	movs	r3, #0
    60dc:	f04f 0220 	mov.w	r2, #32
    60e0:	f3ef 8411 	mrs	r4, BASEPRI
    60e4:	f382 8812 	msr	BASEPRI_MAX, r2
    60e8:	f3bf 8f6f 	isb	sy
    60ec:	b96b      	cbnz	r3, 610a <k_sched_unlock+0x32>
		__ASSERT(_current->base.sched_locked != 0U, "");
		__ASSERT(!arch_is_in_isr(), "");

		++_current->base.sched_locked;
    60ee:	4b0c      	ldr	r3, [pc, #48]	; (6120 <k_sched_unlock+0x48>)
    60f0:	689a      	ldr	r2, [r3, #8]
    60f2:	7bd3      	ldrb	r3, [r2, #15]
    60f4:	3301      	adds	r3, #1
    60f6:	73d3      	strb	r3, [r2, #15]
		update_cache(0);
    60f8:	2000      	movs	r0, #0
    60fa:	f7ff fe07 	bl	5d0c <update_cache>
	__asm__ volatile(
    60fe:	f384 8811 	msr	BASEPRI, r4
    6102:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
    6106:	2301      	movs	r3, #1
    6108:	e7f0      	b.n	60ec <k_sched_unlock+0x14>
	__asm__ volatile(
    610a:	f04f 0320 	mov.w	r3, #32
    610e:	f3ef 8011 	mrs	r0, BASEPRI
    6112:	f383 8812 	msr	BASEPRI_MAX, r3
    6116:	f3bf 8f6f 	isb	sy
    611a:	f001 fdba 	bl	7c92 <z_reschedule_irqlock>
		_current, _current->base.sched_locked);

	SYS_PORT_TRACING_FUNC(k_thread, sched_unlock);

	z_reschedule_unlocked();
}
    611e:	bd10      	pop	{r4, pc}
    6120:	20000b2c 	.word	0x20000b2c

00006124 <end_thread>:
#ifdef CONFIG_CMSIS_RTOS_V1
extern void z_thread_cmsis_status_mask_clear(struct k_thread *thread);
#endif

static void end_thread(struct k_thread *thread)
{
    6124:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	/* We hold the lock, and the thread is known not to be running
	 * anywhere.
	 */
	if ((thread->base.thread_state & _THREAD_DEAD) == 0U) {
    6126:	7b43      	ldrb	r3, [r0, #13]
    6128:	f013 0f08 	tst.w	r3, #8
    612c:	d145      	bne.n	61ba <end_thread+0x96>
    612e:	4605      	mov	r5, r0
		thread->base.thread_state |= _THREAD_DEAD;
    6130:	f043 0308 	orr.w	r3, r3, #8
		thread->base.thread_state &= ~_THREAD_ABORTING;
    6134:	f003 03df 	and.w	r3, r3, #223	; 0xdf
    6138:	7343      	strb	r3, [r0, #13]
		if (z_is_thread_queued(thread)) {
    613a:	f013 0f80 	tst.w	r3, #128	; 0x80
    613e:	d114      	bne.n	616a <end_thread+0x46>
			dequeue_thread(&_kernel.ready_q.runq, thread);
		}
		if (thread->base.pended_on != NULL) {
    6140:	68ab      	ldr	r3, [r5, #8]
    6142:	b15b      	cbz	r3, 615c <end_thread+0x38>
	_priq_wait_remove(&pended_on_thread(thread)->waitq, thread);
    6144:	4628      	mov	r0, r5
    6146:	f001 fd79 	bl	7c3c <pended_on_thread>
    614a:	4629      	mov	r1, r5
    614c:	f001 fdb6 	bl	7cbc <z_priq_dumb_remove>
	thread->base.thread_state &= ~_THREAD_PENDING;
    6150:	7b6b      	ldrb	r3, [r5, #13]
    6152:	f023 0302 	bic.w	r3, r3, #2
    6156:	736b      	strb	r3, [r5, #13]
	thread->base.pended_on = NULL;
    6158:	2300      	movs	r3, #0
    615a:	60ab      	str	r3, [r5, #8]
    615c:	f105 0018 	add.w	r0, r5, #24
    6160:	f001 fef6 	bl	7f50 <z_abort_timeout>
			unpend_thread_no_timeout(thread);
		}
		(void)z_abort_thread_timeout(thread);
		unpend_all(&thread->join_queue);
    6164:	f105 0758 	add.w	r7, r5, #88	; 0x58
	while ((thread = z_waitq_head(wait_q)) != NULL) {
    6168:	e01c      	b.n	61a4 <end_thread+0x80>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    616a:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    616e:	7343      	strb	r3, [r0, #13]
		_priq_run_remove(pq, thread);
    6170:	4601      	mov	r1, r0
    6172:	4812      	ldr	r0, [pc, #72]	; (61bc <end_thread+0x98>)
    6174:	f001 fda2 	bl	7cbc <z_priq_dumb_remove>
}
    6178:	e7e2      	b.n	6140 <end_thread+0x1c>
	_priq_wait_remove(&pended_on_thread(thread)->waitq, thread);
    617a:	4620      	mov	r0, r4
    617c:	f001 fd5e 	bl	7c3c <pended_on_thread>
    6180:	4621      	mov	r1, r4
    6182:	f001 fd9b 	bl	7cbc <z_priq_dumb_remove>
    6186:	7b63      	ldrb	r3, [r4, #13]
    6188:	f023 0302 	bic.w	r3, r3, #2
    618c:	7363      	strb	r3, [r4, #13]
	thread->base.pended_on = NULL;
    618e:	2600      	movs	r6, #0
    6190:	60a6      	str	r6, [r4, #8]
    6192:	f104 0018 	add.w	r0, r4, #24
    6196:	f001 fedb 	bl	7f50 <z_abort_timeout>
    619a:	f8c4 60ac 	str.w	r6, [r4, #172]	; 0xac
		ready_thread(thread);
    619e:	4620      	mov	r0, r4
    61a0:	f7ff fe6a 	bl	5e78 <ready_thread>
	return list->head == list;
    61a4:	683c      	ldr	r4, [r7, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    61a6:	42bc      	cmp	r4, r7
    61a8:	d001      	beq.n	61ae <end_thread+0x8a>
	while ((thread = z_waitq_head(wait_q)) != NULL) {
    61aa:	2c00      	cmp	r4, #0
    61ac:	d1e5      	bne.n	617a <end_thread+0x56>
		update_cache(1);
    61ae:	2001      	movs	r0, #1
    61b0:	f7ff fdac 	bl	5d0c <update_cache>

		SYS_PORT_TRACING_FUNC(k_thread, sched_abort, thread);

		z_thread_monitor_exit(thread);
    61b4:	4628      	mov	r0, r5
    61b6:	f7ff f98d 	bl	54d4 <z_thread_monitor_exit>
		z_thread_perms_all_clear(thread);
		z_object_uninit(thread->stack_obj);
		z_object_uninit(thread);
#endif
	}
}
    61ba:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    61bc:	20000b4c 	.word	0x20000b4c

000061c0 <z_sched_init>:
{
    61c0:	b508      	push	{r3, lr}
	list->head = (sys_dnode_t *)list;
    61c2:	4b05      	ldr	r3, [pc, #20]	; (61d8 <z_sched_init+0x18>)
    61c4:	f103 0220 	add.w	r2, r3, #32
    61c8:	621a      	str	r2, [r3, #32]
	list->tail = (sys_dnode_t *)list;
    61ca:	625a      	str	r2, [r3, #36]	; 0x24
	k_sched_time_slice_set(CONFIG_TIMESLICE_SIZE,
    61cc:	2100      	movs	r1, #0
    61ce:	4608      	mov	r0, r1
    61d0:	f7ff fd2c 	bl	5c2c <k_sched_time_slice_set>
}
    61d4:	bd08      	pop	{r3, pc}
    61d6:	bf00      	nop
    61d8:	20000b2c 	.word	0x20000b2c

000061dc <z_impl_k_yield>:
{
    61dc:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    61de:	f04f 0320 	mov.w	r3, #32
    61e2:	f3ef 8611 	mrs	r6, BASEPRI
    61e6:	f383 8812 	msr	BASEPRI_MAX, r3
    61ea:	f3bf 8f6f 	isb	sy
		dequeue_thread(&_kernel.ready_q.runq,
    61ee:	4c1c      	ldr	r4, [pc, #112]	; (6260 <z_impl_k_yield+0x84>)
    61f0:	68a1      	ldr	r1, [r4, #8]
	thread->base.thread_state &= ~_THREAD_QUEUED;
    61f2:	7b4b      	ldrb	r3, [r1, #13]
    61f4:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    61f8:	734b      	strb	r3, [r1, #13]
		_priq_run_remove(pq, thread);
    61fa:	f104 0720 	add.w	r7, r4, #32
    61fe:	4638      	mov	r0, r7
    6200:	f001 fd5c 	bl	7cbc <z_priq_dumb_remove>
	queue_thread(&_kernel.ready_q.runq, _current);
    6204:	68a5      	ldr	r5, [r4, #8]
	thread->base.thread_state |= _THREAD_QUEUED;
    6206:	7b6b      	ldrb	r3, [r5, #13]
    6208:	f063 037f 	orn	r3, r3, #127	; 0x7f
    620c:	736b      	strb	r3, [r5, #13]
	return list->head == list;
    620e:	6a24      	ldr	r4, [r4, #32]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    6210:	42bc      	cmp	r4, r7
    6212:	d023      	beq.n	625c <z_impl_k_yield+0x80>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    6214:	b16c      	cbz	r4, 6232 <z_impl_k_yield+0x56>
		if (z_sched_prio_cmp(thread, t) > 0) {
    6216:	4621      	mov	r1, r4
    6218:	4628      	mov	r0, r5
    621a:	f001 fd11 	bl	7c40 <z_sched_prio_cmp>
    621e:	2800      	cmp	r0, #0
    6220:	dc16      	bgt.n	6250 <z_impl_k_yield+0x74>
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    6222:	b134      	cbz	r4, 6232 <z_impl_k_yield+0x56>
	return (node == list->tail) ? NULL : node->next;
    6224:	4b0e      	ldr	r3, [pc, #56]	; (6260 <z_impl_k_yield+0x84>)
    6226:	6a5b      	ldr	r3, [r3, #36]	; 0x24
    6228:	429c      	cmp	r4, r3
    622a:	d002      	beq.n	6232 <z_impl_k_yield+0x56>
    622c:	6824      	ldr	r4, [r4, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    622e:	2c00      	cmp	r4, #0
    6230:	d1f0      	bne.n	6214 <z_impl_k_yield+0x38>
	sys_dnode_t *const tail = list->tail;
    6232:	4b0b      	ldr	r3, [pc, #44]	; (6260 <z_impl_k_yield+0x84>)
    6234:	6a5a      	ldr	r2, [r3, #36]	; 0x24
	node->next = list;
    6236:	f103 0120 	add.w	r1, r3, #32
    623a:	6029      	str	r1, [r5, #0]
	node->prev = tail;
    623c:	606a      	str	r2, [r5, #4]
	tail->next = node;
    623e:	6015      	str	r5, [r2, #0]
	list->tail = node;
    6240:	625d      	str	r5, [r3, #36]	; 0x24
	update_cache(1);
    6242:	2001      	movs	r0, #1
    6244:	f7ff fd62 	bl	5d0c <update_cache>
    6248:	4630      	mov	r0, r6
    624a:	f7fc f815 	bl	2278 <arch_swap>
}
    624e:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	sys_dnode_t *const prev = successor->prev;
    6250:	6863      	ldr	r3, [r4, #4]
	node->prev = prev;
    6252:	606b      	str	r3, [r5, #4]
	node->next = successor;
    6254:	602c      	str	r4, [r5, #0]
	prev->next = node;
    6256:	601d      	str	r5, [r3, #0]
	successor->prev = node;
    6258:	6065      	str	r5, [r4, #4]
}
    625a:	e7f2      	b.n	6242 <z_impl_k_yield+0x66>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    625c:	2400      	movs	r4, #0
    625e:	e7d9      	b.n	6214 <z_impl_k_yield+0x38>
    6260:	20000b2c 	.word	0x20000b2c

00006264 <z_tick_sleep>:
{
    6264:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    6268:	4604      	mov	r4, r0
    626a:	460d      	mov	r5, r1
	if (ticks == 0) {
    626c:	ea54 0105 	orrs.w	r1, r4, r5
    6270:	d037      	beq.n	62e2 <z_tick_sleep+0x7e>
	if (Z_TICK_ABS(ticks) <= 0) {
    6272:	f06f 0101 	mvn.w	r1, #1
    6276:	1a0a      	subs	r2, r1, r0
    6278:	f04f 31ff 	mov.w	r1, #4294967295
    627c:	eb61 0305 	sbc.w	r3, r1, r5
    6280:	2a01      	cmp	r2, #1
    6282:	f173 0300 	sbcs.w	r3, r3, #0
    6286:	db30      	blt.n	62ea <z_tick_sleep+0x86>
		expected_wakeup_ticks = Z_TICK_ABS(ticks);
    6288:	f06f 0601 	mvn.w	r6, #1
    628c:	1a36      	subs	r6, r6, r0
    628e:	f04f 0320 	mov.w	r3, #32
    6292:	f3ef 8811 	mrs	r8, BASEPRI
    6296:	f383 8812 	msr	BASEPRI_MAX, r3
    629a:	f3bf 8f6f 	isb	sy
	pending_current = _current;
    629e:	4f16      	ldr	r7, [pc, #88]	; (62f8 <z_tick_sleep+0x94>)
    62a0:	68b8      	ldr	r0, [r7, #8]
    62a2:	4b16      	ldr	r3, [pc, #88]	; (62fc <z_tick_sleep+0x98>)
    62a4:	6018      	str	r0, [r3, #0]
	unready_thread(_current);
    62a6:	f7ff fe45 	bl	5f34 <unready_thread>
	z_add_thread_timeout(_current, timeout);
    62aa:	68b8      	ldr	r0, [r7, #8]
	z_add_timeout(&thread->base.timeout, z_thread_timeout, ticks);
    62ac:	4622      	mov	r2, r4
    62ae:	462b      	mov	r3, r5
    62b0:	4913      	ldr	r1, [pc, #76]	; (6300 <z_tick_sleep+0x9c>)
    62b2:	3018      	adds	r0, #24
    62b4:	f000 f904 	bl	64c0 <z_add_timeout>
	z_mark_thread_as_suspended(_current);
    62b8:	68ba      	ldr	r2, [r7, #8]
	thread->base.thread_state |= _THREAD_SUSPENDED;
    62ba:	7b53      	ldrb	r3, [r2, #13]
    62bc:	f043 0310 	orr.w	r3, r3, #16
    62c0:	7353      	strb	r3, [r2, #13]
    62c2:	4640      	mov	r0, r8
    62c4:	f7fb ffd8 	bl	2278 <arch_swap>
	ticks = (k_ticks_t)expected_wakeup_ticks - sys_clock_tick_get_32();
    62c8:	2500      	movs	r5, #0
    62ca:	f001 fea0 	bl	800e <sys_clock_tick_get_32>
    62ce:	1a34      	subs	r4, r6, r0
    62d0:	f165 0500 	sbc.w	r5, r5, #0
	if (ticks > 0) {
    62d4:	2c01      	cmp	r4, #1
    62d6:	f175 0300 	sbcs.w	r3, r5, #0
    62da:	da0a      	bge.n	62f2 <z_tick_sleep+0x8e>
	return 0;
    62dc:	2000      	movs	r0, #0
}
    62de:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	z_impl_k_yield();
    62e2:	f7ff ff7b 	bl	61dc <z_impl_k_yield>
		return 0;
    62e6:	2000      	movs	r0, #0
    62e8:	e7f9      	b.n	62de <z_tick_sleep+0x7a>
		expected_wakeup_ticks = ticks + sys_clock_tick_get_32();
    62ea:	f001 fe90 	bl	800e <sys_clock_tick_get_32>
    62ee:	1906      	adds	r6, r0, r4
    62f0:	e7cd      	b.n	628e <z_tick_sleep+0x2a>
		return ticks;
    62f2:	4620      	mov	r0, r4
    62f4:	e7f3      	b.n	62de <z_tick_sleep+0x7a>
    62f6:	bf00      	nop
    62f8:	20000b2c 	.word	0x20000b2c
    62fc:	20000b6c 	.word	0x20000b6c
    6300:	00007d13 	.word	0x00007d13

00006304 <z_impl_k_sleep>:
{
    6304:	b538      	push	{r3, r4, r5, lr}
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    6306:	f1b1 3fff 	cmp.w	r1, #4294967295
    630a:	bf08      	it	eq
    630c:	f1b0 3fff 	cmpeq.w	r0, #4294967295
    6310:	d01a      	beq.n	6348 <z_impl_k_sleep+0x44>
	ticks = z_tick_sleep(ticks);
    6312:	f7ff ffa7 	bl	6264 <z_tick_sleep>
	int32_t ret = k_ticks_to_ms_floor64(ticks);
    6316:	4604      	mov	r4, r0
    6318:	17c5      	asrs	r5, r0, #31
			return (t * to_hz + off) / from_hz;
    631a:	0169      	lsls	r1, r5, #5
    631c:	0143      	lsls	r3, r0, #5
    631e:	ea41 62d0 	orr.w	r2, r1, r0, lsr #27
    6322:	1a18      	subs	r0, r3, r0
    6324:	eb62 0305 	sbc.w	r3, r2, r5
    6328:	009a      	lsls	r2, r3, #2
    632a:	ea42 7290 	orr.w	r2, r2, r0, lsr #30
    632e:	0081      	lsls	r1, r0, #2
    6330:	4613      	mov	r3, r2
    6332:	1908      	adds	r0, r1, r4
    6334:	eb45 0303 	adc.w	r3, r5, r3
    6338:	00da      	lsls	r2, r3, #3
    633a:	ea42 7250 	orr.w	r2, r2, r0, lsr #29
    633e:	00c1      	lsls	r1, r0, #3
    6340:	0bc8      	lsrs	r0, r1, #15
    6342:	ea40 4042 	orr.w	r0, r0, r2, lsl #17
}
    6346:	bd38      	pop	{r3, r4, r5, pc}
		k_thread_suspend(_current);
    6348:	4b03      	ldr	r3, [pc, #12]	; (6358 <z_impl_k_sleep+0x54>)
    634a:	6898      	ldr	r0, [r3, #8]
	z_impl_k_thread_suspend(thread);
    634c:	f7ff fe82 	bl	6054 <z_impl_k_thread_suspend>
		return (int32_t) K_TICKS_FOREVER;
    6350:	f04f 30ff 	mov.w	r0, #4294967295
    6354:	e7f7      	b.n	6346 <z_impl_k_sleep+0x42>
    6356:	bf00      	nop
    6358:	20000b2c 	.word	0x20000b2c

0000635c <z_impl_z_current_get>:
}
    635c:	4b01      	ldr	r3, [pc, #4]	; (6364 <z_impl_z_current_get+0x8>)
    635e:	6898      	ldr	r0, [r3, #8]
    6360:	4770      	bx	lr
    6362:	bf00      	nop
    6364:	20000b2c 	.word	0x20000b2c

00006368 <z_impl_k_is_preempt_thread>:
    6368:	f3ef 8305 	mrs	r3, IPSR
	return !arch_is_in_isr() && is_preempt(_current);
    636c:	b933      	cbnz	r3, 637c <z_impl_k_is_preempt_thread+0x14>
    636e:	4b05      	ldr	r3, [pc, #20]	; (6384 <z_impl_k_is_preempt_thread+0x1c>)
    6370:	689b      	ldr	r3, [r3, #8]
	return thread->base.preempt <= _PREEMPT_THRESHOLD;
    6372:	89db      	ldrh	r3, [r3, #14]
	return !arch_is_in_isr() && is_preempt(_current);
    6374:	2b7f      	cmp	r3, #127	; 0x7f
    6376:	d803      	bhi.n	6380 <z_impl_k_is_preempt_thread+0x18>
    6378:	2001      	movs	r0, #1
    637a:	4770      	bx	lr
    637c:	2000      	movs	r0, #0
    637e:	4770      	bx	lr
    6380:	2000      	movs	r0, #0
}
    6382:	4770      	bx	lr
    6384:	20000b2c 	.word	0x20000b2c

00006388 <z_thread_abort>:

void z_thread_abort(struct k_thread *thread)
{
    6388:	b538      	push	{r3, r4, r5, lr}
    638a:	f04f 0320 	mov.w	r3, #32
    638e:	f3ef 8511 	mrs	r5, BASEPRI
    6392:	f383 8812 	msr	BASEPRI_MAX, r3
    6396:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&sched_spinlock);

	if ((thread->base.thread_state & _THREAD_DEAD) != 0U) {
    639a:	7b43      	ldrb	r3, [r0, #13]
    639c:	f013 0f08 	tst.w	r3, #8
    63a0:	d004      	beq.n	63ac <z_thread_abort+0x24>
	__asm__ volatile(
    63a2:	f385 8811 	msr	BASEPRI, r5
    63a6:	f3bf 8f6f 	isb	sy
	if (thread == _current && !arch_is_in_isr()) {
		z_swap(&sched_spinlock, key);
		__ASSERT(false, "aborted _current back from dead");
	}
	k_spin_unlock(&sched_spinlock, key);
}
    63aa:	bd38      	pop	{r3, r4, r5, pc}
    63ac:	4604      	mov	r4, r0
	end_thread(thread);
    63ae:	f7ff feb9 	bl	6124 <end_thread>
	if (thread == _current && !arch_is_in_isr()) {
    63b2:	4b08      	ldr	r3, [pc, #32]	; (63d4 <z_thread_abort+0x4c>)
    63b4:	689b      	ldr	r3, [r3, #8]
    63b6:	42a3      	cmp	r3, r4
    63b8:	d004      	beq.n	63c4 <z_thread_abort+0x3c>
    63ba:	f385 8811 	msr	BASEPRI, r5
    63be:	f3bf 8f6f 	isb	sy
    63c2:	e7f2      	b.n	63aa <z_thread_abort+0x22>
    63c4:	f3ef 8305 	mrs	r3, IPSR
    63c8:	2b00      	cmp	r3, #0
    63ca:	d1f6      	bne.n	63ba <z_thread_abort+0x32>
    63cc:	4628      	mov	r0, r5
    63ce:	f7fb ff53 	bl	2278 <arch_swap>
	return ret;
    63d2:	e7f2      	b.n	63ba <z_thread_abort+0x32>
    63d4:	20000b2c 	.word	0x20000b2c

000063d8 <z_sched_wait>:
	return ret;
}

int z_sched_wait(struct k_spinlock *lock, k_spinlock_key_t key,
		 _wait_q_t *wait_q, k_timeout_t timeout, void **data)
{
    63d8:	b5d0      	push	{r4, r6, r7, lr}
    63da:	b082      	sub	sp, #8
    63dc:	9c08      	ldr	r4, [sp, #32]
	int ret = z_pend_curr(lock, key, wait_q, timeout);
    63de:	e9dd 6706 	ldrd	r6, r7, [sp, #24]
    63e2:	e9cd 6700 	strd	r6, r7, [sp]
    63e6:	f7ff fdc1 	bl	5f6c <z_pend_curr>

	if (data != NULL) {
    63ea:	b11c      	cbz	r4, 63f4 <z_sched_wait+0x1c>
		*data = _current->base.swap_data;
    63ec:	4b02      	ldr	r3, [pc, #8]	; (63f8 <z_sched_wait+0x20>)
    63ee:	689b      	ldr	r3, [r3, #8]
    63f0:	695b      	ldr	r3, [r3, #20]
    63f2:	6023      	str	r3, [r4, #0]
	}
	return ret;
}
    63f4:	b002      	add	sp, #8
    63f6:	bdd0      	pop	{r4, r6, r7, pc}
    63f8:	20000b2c 	.word	0x20000b2c

000063fc <z_data_copy>:
 * This routine copies the data section from ROM to RAM.
 *
 * @return N/A
 */
void z_data_copy(void)
{
    63fc:	b508      	push	{r3, lr}
	(void)memcpy(&__data_region_start, &__data_region_load_start,
    63fe:	4806      	ldr	r0, [pc, #24]	; (6418 <z_data_copy+0x1c>)
__ssp_bos_icheck3_restrict(memcpy, void *, const void *)
    6400:	4a06      	ldr	r2, [pc, #24]	; (641c <z_data_copy+0x20>)
    6402:	1a12      	subs	r2, r2, r0
    6404:	4906      	ldr	r1, [pc, #24]	; (6420 <z_data_copy+0x24>)
    6406:	f001 fe38 	bl	807a <memcpy>
    640a:	4a06      	ldr	r2, [pc, #24]	; (6424 <z_data_copy+0x28>)
    640c:	4906      	ldr	r1, [pc, #24]	; (6428 <z_data_copy+0x2c>)
    640e:	4807      	ldr	r0, [pc, #28]	; (642c <z_data_copy+0x30>)
    6410:	f001 fe33 	bl	807a <memcpy>
#else
	(void)memcpy(&_app_smem_start, &_app_smem_rom_start,
		 _app_smem_end - _app_smem_start);
#endif /* CONFIG_STACK_CANARIES */
#endif /* CONFIG_USERSPACE */
}
    6414:	bd08      	pop	{r3, pc}
    6416:	bf00      	nop
    6418:	20000000 	.word	0x20000000
    641c:	200000d4 	.word	0x200000d4
    6420:	00008fa8 	.word	0x00008fa8
    6424:	00000000 	.word	0x00000000
    6428:	00008fa8 	.word	0x00008fa8
    642c:	20000000 	.word	0x20000000

00006430 <first>:
	return list->head == list;
    6430:	4b03      	ldr	r3, [pc, #12]	; (6440 <first+0x10>)
    6432:	6818      	ldr	r0, [r3, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    6434:	4298      	cmp	r0, r3
    6436:	d000      	beq.n	643a <first+0xa>
static struct _timeout *first(void)
{
	sys_dnode_t *t = sys_dlist_peek_head(&timeout_list);

	return t == NULL ? NULL : CONTAINER_OF(t, struct _timeout, node);
}
    6438:	4770      	bx	lr
    643a:	2000      	movs	r0, #0
	return t == NULL ? NULL : CONTAINER_OF(t, struct _timeout, node);
    643c:	e7fc      	b.n	6438 <first+0x8>
    643e:	bf00      	nop
    6440:	20000054 	.word	0x20000054

00006444 <next>:
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    6444:	b130      	cbz	r0, 6454 <next+0x10>
	return (node == list->tail) ? NULL : node->next;
    6446:	4a04      	ldr	r2, [pc, #16]	; (6458 <next+0x14>)
    6448:	6852      	ldr	r2, [r2, #4]
    644a:	4290      	cmp	r0, r2
    644c:	d001      	beq.n	6452 <next+0xe>
    644e:	6800      	ldr	r0, [r0, #0]
    6450:	4770      	bx	lr
    6452:	2000      	movs	r0, #0
static struct _timeout *next(struct _timeout *t)
{
	sys_dnode_t *n = sys_dlist_peek_next(&timeout_list, &t->node);

	return n == NULL ? NULL : CONTAINER_OF(n, struct _timeout, node);
}
    6454:	4770      	bx	lr
    6456:	bf00      	nop
    6458:	20000054 	.word	0x20000054

0000645c <elapsed>:

	sys_dlist_remove(&t->node);
}

static int32_t elapsed(void)
{
    645c:	b508      	push	{r3, lr}
	return announce_remaining == 0 ? sys_clock_elapsed() : 0U;
    645e:	4b04      	ldr	r3, [pc, #16]	; (6470 <elapsed+0x14>)
    6460:	681b      	ldr	r3, [r3, #0]
    6462:	b10b      	cbz	r3, 6468 <elapsed+0xc>
    6464:	2000      	movs	r0, #0
}
    6466:	bd08      	pop	{r3, pc}
	return announce_remaining == 0 ? sys_clock_elapsed() : 0U;
    6468:	f7fe f83a 	bl	44e0 <sys_clock_elapsed>
    646c:	e7fb      	b.n	6466 <elapsed+0xa>
    646e:	bf00      	nop
    6470:	20000b7c 	.word	0x20000b7c

00006474 <next_timeout>:

static int32_t next_timeout(void)
{
    6474:	b510      	push	{r4, lr}
	struct _timeout *to = first();
    6476:	f7ff ffdb 	bl	6430 <first>
    647a:	4604      	mov	r4, r0
	int32_t ticks_elapsed = elapsed();
    647c:	f7ff ffee 	bl	645c <elapsed>
	int32_t ret = to == NULL ? MAX_WAIT
    6480:	b18c      	cbz	r4, 64a6 <next_timeout+0x32>
		: CLAMP(to->dticks - ticks_elapsed, 0, MAX_WAIT);
    6482:	e9d4 2304 	ldrd	r2, r3, [r4, #16]
    6486:	1a12      	subs	r2, r2, r0
    6488:	eb63 73e0 	sbc.w	r3, r3, r0, asr #31
	int32_t ret = to == NULL ? MAX_WAIT
    648c:	2a01      	cmp	r2, #1
    648e:	f173 0100 	sbcs.w	r1, r3, #0
    6492:	db11      	blt.n	64b8 <next_timeout+0x44>
		: CLAMP(to->dticks - ticks_elapsed, 0, MAX_WAIT);
    6494:	4610      	mov	r0, r2
    6496:	f1b2 4f00 	cmp.w	r2, #2147483648	; 0x80000000
    649a:	f173 0300 	sbcs.w	r3, r3, #0
    649e:	db04      	blt.n	64aa <next_timeout+0x36>
    64a0:	f06f 4000 	mvn.w	r0, #2147483648	; 0x80000000
    64a4:	e001      	b.n	64aa <next_timeout+0x36>
	int32_t ret = to == NULL ? MAX_WAIT
    64a6:	f06f 4000 	mvn.w	r0, #2147483648	; 0x80000000

#ifdef CONFIG_TIMESLICING
	if (_current_cpu->slice_ticks && _current_cpu->slice_ticks < ret) {
    64aa:	4b04      	ldr	r3, [pc, #16]	; (64bc <next_timeout+0x48>)
    64ac:	691b      	ldr	r3, [r3, #16]
    64ae:	b113      	cbz	r3, 64b6 <next_timeout+0x42>
    64b0:	4283      	cmp	r3, r0
    64b2:	da00      	bge.n	64b6 <next_timeout+0x42>
		ret = _current_cpu->slice_ticks;
    64b4:	4618      	mov	r0, r3
	}
#endif
	return ret;
}
    64b6:	bd10      	pop	{r4, pc}
	int32_t ret = to == NULL ? MAX_WAIT
    64b8:	2000      	movs	r0, #0
    64ba:	e7f6      	b.n	64aa <next_timeout+0x36>
    64bc:	20000b2c 	.word	0x20000b2c

000064c0 <z_add_timeout>:

void z_add_timeout(struct _timeout *to, _timeout_func_t fn,
		   k_timeout_t timeout)
{
    64c0:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    64c4:	b083      	sub	sp, #12
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    64c6:	f1b3 3fff 	cmp.w	r3, #4294967295
    64ca:	bf08      	it	eq
    64cc:	f1b2 3fff 	cmpeq.w	r2, #4294967295
    64d0:	f000 8096 	beq.w	6600 <z_add_timeout+0x140>
    64d4:	4682      	mov	sl, r0
    64d6:	4614      	mov	r4, r2
    64d8:	461d      	mov	r5, r3
#ifdef CONFIG_KERNEL_COHERENCE
	__ASSERT_NO_MSG(arch_mem_coherent(to));
#endif

	__ASSERT(!sys_dnode_is_linked(&to->node), "");
	to->fn = fn;
    64da:	6081      	str	r1, [r0, #8]

	LOCKED(&timeout_lock) {
    64dc:	2300      	movs	r3, #0
	__asm__ volatile(
    64de:	f04f 0220 	mov.w	r2, #32
    64e2:	f3ef 8b11 	mrs	fp, BASEPRI
    64e6:	f382 8812 	msr	BASEPRI_MAX, r2
    64ea:	f3bf 8f6f 	isb	sy
    64ee:	e02e      	b.n	654e <z_add_timeout+0x8e>

		if (IS_ENABLED(CONFIG_TIMEOUT_64BIT) &&
		    Z_TICK_ABS(timeout.ticks) >= 0) {
			k_ticks_t ticks = Z_TICK_ABS(timeout.ticks) - curr_tick;

			to->dticks = MAX(1, ticks);
    64f0:	2201      	movs	r2, #1
    64f2:	2300      	movs	r3, #0
    64f4:	e04b      	b.n	658e <z_add_timeout+0xce>
		} else {
			to->dticks = timeout.ticks + 1 + elapsed();
    64f6:	f7ff ffb1 	bl	645c <elapsed>
    64fa:	1822      	adds	r2, r4, r0
    64fc:	eb45 73e0 	adc.w	r3, r5, r0, asr #31
    6500:	3201      	adds	r2, #1
    6502:	f143 0300 	adc.w	r3, r3, #0
    6506:	f8ca 2010 	str.w	r2, [sl, #16]
    650a:	f8ca 3014 	str.w	r3, [sl, #20]
    650e:	e042      	b.n	6596 <z_add_timeout+0xd6>
		}

		for (t = first(); t != NULL; t = next(t)) {
			if (t->dticks > to->dticks) {
				t->dticks -= to->dticks;
    6510:	9b00      	ldr	r3, [sp, #0]
    6512:	1ac2      	subs	r2, r0, r3
    6514:	9b01      	ldr	r3, [sp, #4]
    6516:	eb61 0303 	sbc.w	r3, r1, r3
    651a:	f8cc 2010 	str.w	r2, [ip, #16]
    651e:	f8cc 3014 	str.w	r3, [ip, #20]
	sys_dnode_t *const prev = successor->prev;
    6522:	f8dc 3004 	ldr.w	r3, [ip, #4]
	node->prev = prev;
    6526:	f8ca 3004 	str.w	r3, [sl, #4]
	node->next = successor;
    652a:	f8ca c000 	str.w	ip, [sl]
	prev->next = node;
    652e:	f8c3 a000 	str.w	sl, [r3]
	successor->prev = node;
    6532:	f8cc a004 	str.w	sl, [ip, #4]
				break;
			}
			to->dticks -= t->dticks;
		}

		if (t == NULL) {
    6536:	f1bc 0f00 	cmp.w	ip, #0
    653a:	d049      	beq.n	65d0 <z_add_timeout+0x110>
			sys_dlist_append(&timeout_list, &to->node);
		}

		if (to == first()) {
    653c:	f7ff ff78 	bl	6430 <first>
    6540:	4582      	cmp	sl, r0
    6542:	d050      	beq.n	65e6 <z_add_timeout+0x126>
	__asm__ volatile(
    6544:	f38b 8811 	msr	BASEPRI, fp
    6548:	f3bf 8f6f 	isb	sy
	LOCKED(&timeout_lock) {
    654c:	2301      	movs	r3, #1
    654e:	2b00      	cmp	r3, #0
    6550:	d156      	bne.n	6600 <z_add_timeout+0x140>
		    Z_TICK_ABS(timeout.ticks) >= 0) {
    6552:	f06f 0301 	mvn.w	r3, #1
    6556:	ebb3 0804 	subs.w	r8, r3, r4
    655a:	f04f 30ff 	mov.w	r0, #4294967295
    655e:	eb60 0905 	sbc.w	r9, r0, r5
		if (IS_ENABLED(CONFIG_TIMEOUT_64BIT) &&
    6562:	f1b8 0f00 	cmp.w	r8, #0
    6566:	f179 0300 	sbcs.w	r3, r9, #0
    656a:	dbc4      	blt.n	64f6 <z_add_timeout+0x36>
			k_ticks_t ticks = Z_TICK_ABS(timeout.ticks) - curr_tick;
    656c:	4a26      	ldr	r2, [pc, #152]	; (6608 <z_add_timeout+0x148>)
    656e:	6813      	ldr	r3, [r2, #0]
    6570:	6852      	ldr	r2, [r2, #4]
    6572:	18e3      	adds	r3, r4, r3
    6574:	eb45 0202 	adc.w	r2, r5, r2
    6578:	f06f 0101 	mvn.w	r1, #1
    657c:	1ace      	subs	r6, r1, r3
    657e:	eb60 0702 	sbc.w	r7, r0, r2
			to->dticks = MAX(1, ticks);
    6582:	4632      	mov	r2, r6
    6584:	463b      	mov	r3, r7
    6586:	2e01      	cmp	r6, #1
    6588:	f177 0100 	sbcs.w	r1, r7, #0
    658c:	dbb0      	blt.n	64f0 <z_add_timeout+0x30>
    658e:	f8ca 2010 	str.w	r2, [sl, #16]
    6592:	f8ca 3014 	str.w	r3, [sl, #20]
		for (t = first(); t != NULL; t = next(t)) {
    6596:	f7ff ff4b 	bl	6430 <first>
    659a:	4684      	mov	ip, r0
    659c:	f1bc 0f00 	cmp.w	ip, #0
    65a0:	d0c9      	beq.n	6536 <z_add_timeout+0x76>
			if (t->dticks > to->dticks) {
    65a2:	e9dc 0104 	ldrd	r0, r1, [ip, #16]
    65a6:	e9da 2304 	ldrd	r2, r3, [sl, #16]
    65aa:	e9cd 2300 	strd	r2, r3, [sp]
    65ae:	4282      	cmp	r2, r0
    65b0:	418b      	sbcs	r3, r1
    65b2:	dbad      	blt.n	6510 <z_add_timeout+0x50>
			to->dticks -= t->dticks;
    65b4:	9b00      	ldr	r3, [sp, #0]
    65b6:	1a1a      	subs	r2, r3, r0
    65b8:	9b01      	ldr	r3, [sp, #4]
    65ba:	eb63 0301 	sbc.w	r3, r3, r1
    65be:	f8ca 2010 	str.w	r2, [sl, #16]
    65c2:	f8ca 3014 	str.w	r3, [sl, #20]
		for (t = first(); t != NULL; t = next(t)) {
    65c6:	4660      	mov	r0, ip
    65c8:	f7ff ff3c 	bl	6444 <next>
    65cc:	4684      	mov	ip, r0
    65ce:	e7e5      	b.n	659c <z_add_timeout+0xdc>
	sys_dnode_t *const tail = list->tail;
    65d0:	4b0e      	ldr	r3, [pc, #56]	; (660c <z_add_timeout+0x14c>)
    65d2:	685a      	ldr	r2, [r3, #4]
	node->next = list;
    65d4:	f8ca 3000 	str.w	r3, [sl]
	node->prev = tail;
    65d8:	f8ca 2004 	str.w	r2, [sl, #4]
	tail->next = node;
    65dc:	f8c2 a000 	str.w	sl, [r2]
	list->tail = node;
    65e0:	f8c3 a004 	str.w	sl, [r3, #4]
}
    65e4:	e7aa      	b.n	653c <z_add_timeout+0x7c>
			 * last announcement, and slice_ticks is based
			 * on that. It means that the time remaining for
			 * the next announcement can be less than
			 * slice_ticks.
			 */
			int32_t next_time = next_timeout();
    65e6:	f7ff ff45 	bl	6474 <next_timeout>

			if (next_time == 0 ||
    65ea:	4603      	mov	r3, r0
    65ec:	b118      	cbz	r0, 65f6 <z_add_timeout+0x136>
			    _current_cpu->slice_ticks != next_time) {
    65ee:	4a08      	ldr	r2, [pc, #32]	; (6610 <z_add_timeout+0x150>)
    65f0:	6912      	ldr	r2, [r2, #16]
			if (next_time == 0 ||
    65f2:	4282      	cmp	r2, r0
    65f4:	d0a6      	beq.n	6544 <z_add_timeout+0x84>
				sys_clock_set_timeout(next_time, false);
    65f6:	2100      	movs	r1, #0
    65f8:	4618      	mov	r0, r3
    65fa:	f7fd ff3d 	bl	4478 <sys_clock_set_timeout>
    65fe:	e7a1      	b.n	6544 <z_add_timeout+0x84>
#else
			sys_clock_set_timeout(next_timeout(), false);
#endif	/* CONFIG_TIMESLICING */
		}
	}
}
    6600:	b003      	add	sp, #12
    6602:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    6606:	bf00      	nop
    6608:	20000340 	.word	0x20000340
    660c:	20000054 	.word	0x20000054
    6610:	20000b2c 	.word	0x20000b2c

00006614 <sys_clock_announce>:
		}
	}
}

void sys_clock_announce(int32_t ticks)
{
    6614:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    6616:	4604      	mov	r4, r0
#ifdef CONFIG_TIMESLICING
	z_time_slice(ticks);
    6618:	f7ff fbe2 	bl	5de0 <z_time_slice>
	__asm__ volatile(
    661c:	f04f 0320 	mov.w	r3, #32
    6620:	f3ef 8511 	mrs	r5, BASEPRI
    6624:	f383 8812 	msr	BASEPRI_MAX, r3
    6628:	f3bf 8f6f 	isb	sy
#endif

	k_spinlock_key_t key = k_spin_lock(&timeout_lock);

	announce_remaining = ticks;
    662c:	4b28      	ldr	r3, [pc, #160]	; (66d0 <sys_clock_announce+0xbc>)
    662e:	601c      	str	r4, [r3, #0]

	while (first() != NULL && first()->dticks <= announce_remaining) {
    6630:	f7ff fefe 	bl	6430 <first>
    6634:	4604      	mov	r4, r0
    6636:	b350      	cbz	r0, 668e <sys_clock_announce+0x7a>
    6638:	e9d0 6704 	ldrd	r6, r7, [r0, #16]
    663c:	4b24      	ldr	r3, [pc, #144]	; (66d0 <sys_clock_announce+0xbc>)
    663e:	681b      	ldr	r3, [r3, #0]
    6640:	17d9      	asrs	r1, r3, #31
    6642:	42b3      	cmp	r3, r6
    6644:	eb71 0207 	sbcs.w	r2, r1, r7
    6648:	db21      	blt.n	668e <sys_clock_announce+0x7a>
		struct _timeout *t = first();
		int dt = t->dticks;

		curr_tick += dt;
    664a:	4a22      	ldr	r2, [pc, #136]	; (66d4 <sys_clock_announce+0xc0>)
    664c:	e9d2 0100 	ldrd	r0, r1, [r2]
    6650:	1980      	adds	r0, r0, r6
    6652:	eb41 71e6 	adc.w	r1, r1, r6, asr #31
    6656:	e9c2 0100 	strd	r0, r1, [r2]
		announce_remaining -= dt;
    665a:	1b9b      	subs	r3, r3, r6
    665c:	4a1c      	ldr	r2, [pc, #112]	; (66d0 <sys_clock_announce+0xbc>)
    665e:	6013      	str	r3, [r2, #0]
		t->dticks = 0;
    6660:	2200      	movs	r2, #0
    6662:	2300      	movs	r3, #0
    6664:	e9c4 2304 	strd	r2, r3, [r4, #16]
		remove_timeout(t);
    6668:	4620      	mov	r0, r4
    666a:	f001 fc5a 	bl	7f22 <remove_timeout>
	__asm__ volatile(
    666e:	f385 8811 	msr	BASEPRI, r5
    6672:	f3bf 8f6f 	isb	sy

		k_spin_unlock(&timeout_lock, key);
		t->fn(t);
    6676:	68a3      	ldr	r3, [r4, #8]
    6678:	4620      	mov	r0, r4
    667a:	4798      	blx	r3
	__asm__ volatile(
    667c:	f04f 0320 	mov.w	r3, #32
    6680:	f3ef 8511 	mrs	r5, BASEPRI
    6684:	f383 8812 	msr	BASEPRI_MAX, r3
    6688:	f3bf 8f6f 	isb	sy
    668c:	e7d0      	b.n	6630 <sys_clock_announce+0x1c>
		key = k_spin_lock(&timeout_lock);
	}

	if (first() != NULL) {
    668e:	b144      	cbz	r4, 66a2 <sys_clock_announce+0x8e>
		first()->dticks -= announce_remaining;
    6690:	4b0f      	ldr	r3, [pc, #60]	; (66d0 <sys_clock_announce+0xbc>)
    6692:	6819      	ldr	r1, [r3, #0]
    6694:	e9d4 2304 	ldrd	r2, r3, [r4, #16]
    6698:	1a52      	subs	r2, r2, r1
    669a:	eb63 73e1 	sbc.w	r3, r3, r1, asr #31
    669e:	e9c4 2304 	strd	r2, r3, [r4, #16]
	}

	curr_tick += announce_remaining;
    66a2:	480c      	ldr	r0, [pc, #48]	; (66d4 <sys_clock_announce+0xc0>)
    66a4:	490a      	ldr	r1, [pc, #40]	; (66d0 <sys_clock_announce+0xbc>)
    66a6:	680c      	ldr	r4, [r1, #0]
    66a8:	e9d0 2300 	ldrd	r2, r3, [r0]
    66ac:	1912      	adds	r2, r2, r4
    66ae:	eb43 73e4 	adc.w	r3, r3, r4, asr #31
    66b2:	e9c0 2300 	strd	r2, r3, [r0]
	announce_remaining = 0;
    66b6:	2400      	movs	r4, #0
    66b8:	600c      	str	r4, [r1, #0]

	sys_clock_set_timeout(next_timeout(), false);
    66ba:	f7ff fedb 	bl	6474 <next_timeout>
    66be:	4621      	mov	r1, r4
    66c0:	f7fd feda 	bl	4478 <sys_clock_set_timeout>
	__asm__ volatile(
    66c4:	f385 8811 	msr	BASEPRI, r5
    66c8:	f3bf 8f6f 	isb	sy

	k_spin_unlock(&timeout_lock, key);
}
    66cc:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    66ce:	bf00      	nop
    66d0:	20000b7c 	.word	0x20000b7c
    66d4:	20000340 	.word	0x20000340

000066d8 <sys_clock_tick_get>:

int64_t sys_clock_tick_get(void)
{
    66d8:	b510      	push	{r4, lr}
	uint64_t t = 0U;

	LOCKED(&timeout_lock) {
    66da:	2100      	movs	r1, #0
	__asm__ volatile(
    66dc:	f04f 0320 	mov.w	r3, #32
    66e0:	f3ef 8411 	mrs	r4, BASEPRI
    66e4:	f383 8812 	msr	BASEPRI_MAX, r3
    66e8:	f3bf 8f6f 	isb	sy
	uint64_t t = 0U;
    66ec:	2200      	movs	r2, #0
    66ee:	2300      	movs	r3, #0
	LOCKED(&timeout_lock) {
    66f0:	b969      	cbnz	r1, 670e <sys_clock_tick_get+0x36>
		t = curr_tick + sys_clock_elapsed();
    66f2:	f7fd fef5 	bl	44e0 <sys_clock_elapsed>
    66f6:	4b07      	ldr	r3, [pc, #28]	; (6714 <sys_clock_tick_get+0x3c>)
    66f8:	e9d3 2300 	ldrd	r2, r3, [r3]
    66fc:	1812      	adds	r2, r2, r0
    66fe:	f143 0300 	adc.w	r3, r3, #0
	__asm__ volatile(
    6702:	f384 8811 	msr	BASEPRI, r4
    6706:	f3bf 8f6f 	isb	sy
	LOCKED(&timeout_lock) {
    670a:	2101      	movs	r1, #1
    670c:	e7f0      	b.n	66f0 <sys_clock_tick_get+0x18>
	}
	return t;
}
    670e:	4610      	mov	r0, r2
    6710:	4619      	mov	r1, r3
    6712:	bd10      	pop	{r4, pc}
    6714:	20000340 	.word	0x20000340

00006718 <z_timer_expiration_handler>:
 * @param t  Timeout used by the timer.
 *
 * @return N/A
 */
void z_timer_expiration_handler(struct _timeout *t)
{
    6718:	b538      	push	{r3, r4, r5, lr}
    671a:	4604      	mov	r4, r0
	__asm__ volatile(
    671c:	f04f 0320 	mov.w	r3, #32
    6720:	f3ef 8511 	mrs	r5, BASEPRI
    6724:	f383 8812 	msr	BASEPRI_MAX, r3
    6728:	f3bf 8f6f 	isb	sy

	/*
	 * if the timer is periodic, start it again; don't add _TICK_ALIGN
	 * since we're already aligned to a tick boundary
	 */
	if (!K_TIMEOUT_EQ(timer->period, K_NO_WAIT) &&
    672c:	e9d0 230a 	ldrd	r2, r3, [r0, #40]	; 0x28
    6730:	ea52 0103 	orrs.w	r1, r2, r3
    6734:	d005      	beq.n	6742 <z_timer_expiration_handler+0x2a>
    6736:	f1b3 3fff 	cmp.w	r3, #4294967295
    673a:	bf08      	it	eq
    673c:	f1b2 3fff 	cmpeq.w	r2, #4294967295
    6740:	d11a      	bne.n	6778 <z_timer_expiration_handler+0x60>
		z_add_timeout(&timer->timeout, z_timer_expiration_handler,
			     timer->period);
	}

	/* update timer's status */
	timer->status += 1U;
    6742:	6b23      	ldr	r3, [r4, #48]	; 0x30
    6744:	3301      	adds	r3, #1
    6746:	6323      	str	r3, [r4, #48]	; 0x30

	/* invoke timer expiry function */
	if (timer->expiry_fn != NULL) {
    6748:	6a23      	ldr	r3, [r4, #32]
    674a:	b10b      	cbz	r3, 6750 <z_timer_expiration_handler+0x38>
		timer->expiry_fn(timer);
    674c:	4620      	mov	r0, r4
    674e:	4798      	blx	r3
}

static inline struct k_thread *z_waitq_head(_wait_q_t *w)
{
	return (struct k_thread *)sys_dlist_peek_head(&w->waitq);
    6750:	f104 0318 	add.w	r3, r4, #24
	return list->head == list;
    6754:	69a4      	ldr	r4, [r4, #24]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    6756:	42a3      	cmp	r3, r4
    6758:	d012      	beq.n	6780 <z_timer_expiration_handler+0x68>
		return;
	}

	thread = z_waitq_head(&timer->wait_q);

	if (thread == NULL) {
    675a:	b18c      	cbz	r4, 6780 <z_timer_expiration_handler+0x68>
		k_spin_unlock(&lock, key);
		return;
	}

	z_unpend_thread_no_timeout(thread);
    675c:	4620      	mov	r0, r4
    675e:	f001 fa79 	bl	7c54 <z_unpend_thread_no_timeout>
    6762:	2300      	movs	r3, #0
    6764:	f8c4 30ac 	str.w	r3, [r4, #172]	; 0xac
	__asm__ volatile(
    6768:	f385 8811 	msr	BASEPRI, r5
    676c:	f3bf 8f6f 	isb	sy

	arch_thread_return_value_set(thread, 0);

	k_spin_unlock(&lock, key);

	z_ready_thread(thread);
    6770:	4620      	mov	r0, r4
    6772:	f001 fab2 	bl	7cda <z_ready_thread>
}
    6776:	bd38      	pop	{r3, r4, r5, pc}
		z_add_timeout(&timer->timeout, z_timer_expiration_handler,
    6778:	4904      	ldr	r1, [pc, #16]	; (678c <z_timer_expiration_handler+0x74>)
    677a:	f7ff fea1 	bl	64c0 <z_add_timeout>
    677e:	e7e0      	b.n	6742 <z_timer_expiration_handler+0x2a>
    6780:	f385 8811 	msr	BASEPRI, r5
    6784:	f3bf 8f6f 	isb	sy
		return;
    6788:	e7f5      	b.n	6776 <z_timer_expiration_handler+0x5e>
    678a:	bf00      	nop
    678c:	00006719 	.word	0x00006719

00006790 <z_impl_k_timer_start>:
}


void z_impl_k_timer_start(struct k_timer *timer, k_timeout_t duration,
			  k_timeout_t period)
{
    6790:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    6794:	b087      	sub	sp, #28
    6796:	4614      	mov	r4, r2
    6798:	461d      	mov	r5, r3
    679a:	e9dd 8910 	ldrd	r8, r9, [sp, #64]	; 0x40
	SYS_PORT_TRACING_OBJ_FUNC(k_timer, start, timer);

	if (K_TIMEOUT_EQ(duration, K_FOREVER)) {
    679e:	f1b3 3fff 	cmp.w	r3, #4294967295
    67a2:	bf08      	it	eq
    67a4:	f1b2 3fff 	cmpeq.w	r2, #4294967295
    67a8:	d035      	beq.n	6816 <z_impl_k_timer_start+0x86>
    67aa:	4606      	mov	r6, r0
    67ac:	4613      	mov	r3, r2
    67ae:	462a      	mov	r2, r5
	 * for backwards compatibility.  This is unfortunate
	 * (i.e. k_timer_start() doesn't treat its initial sleep
	 * argument the same way k_sleep() does), but historical.  The
	 * timer_api test relies on this behavior.
	 */
	if (!K_TIMEOUT_EQ(period, K_FOREVER) && period.ticks != 0 &&
    67b0:	f1b9 3fff 	cmp.w	r9, #4294967295
    67b4:	bf08      	it	eq
    67b6:	f1b8 3fff 	cmpeq.w	r8, #4294967295
    67ba:	d012      	beq.n	67e2 <z_impl_k_timer_start+0x52>
    67bc:	ea58 0109 	orrs.w	r1, r8, r9
    67c0:	d00f      	beq.n	67e2 <z_impl_k_timer_start+0x52>
	    Z_TICK_ABS(period.ticks) < 0) {
    67c2:	f06f 0701 	mvn.w	r7, #1
    67c6:	ebb7 0708 	subs.w	r7, r7, r8
    67ca:	9702      	str	r7, [sp, #8]
    67cc:	f04f 31ff 	mov.w	r1, #4294967295
    67d0:	eb61 0709 	sbc.w	r7, r1, r9
    67d4:	9703      	str	r7, [sp, #12]
	if (!K_TIMEOUT_EQ(period, K_FOREVER) && period.ticks != 0 &&
    67d6:	e9dd 0102 	ldrd	r0, r1, [sp, #8]
    67da:	2800      	cmp	r0, #0
    67dc:	f171 0100 	sbcs.w	r1, r1, #0
    67e0:	db1c      	blt.n	681c <z_impl_k_timer_start+0x8c>
		period.ticks = MAX(period.ticks - 1, 1);
	}
	if (Z_TICK_ABS(duration.ticks) < 0) {
    67e2:	f06f 0101 	mvn.w	r1, #1
    67e6:	ebb1 0a03 	subs.w	sl, r1, r3
    67ea:	f04f 31ff 	mov.w	r1, #4294967295
    67ee:	eb61 0b02 	sbc.w	fp, r1, r2
    67f2:	f1ba 0f00 	cmp.w	sl, #0
    67f6:	f17b 0100 	sbcs.w	r1, fp, #0
    67fa:	db23      	blt.n	6844 <z_impl_k_timer_start+0xb4>
		duration.ticks = MAX(duration.ticks - 1, 0);
	}

	(void)z_abort_timeout(&timer->timeout);
    67fc:	4630      	mov	r0, r6
    67fe:	f001 fba7 	bl	7f50 <z_abort_timeout>
	timer->period = period;
    6802:	e9c6 890a 	strd	r8, r9, [r6, #40]	; 0x28
	timer->status = 0U;
    6806:	2300      	movs	r3, #0
    6808:	6333      	str	r3, [r6, #48]	; 0x30

	z_add_timeout(&timer->timeout, z_timer_expiration_handler,
    680a:	4622      	mov	r2, r4
    680c:	462b      	mov	r3, r5
    680e:	4917      	ldr	r1, [pc, #92]	; (686c <z_impl_k_timer_start+0xdc>)
    6810:	4630      	mov	r0, r6
    6812:	f7ff fe55 	bl	64c0 <z_add_timeout>
		     duration);
}
    6816:	b007      	add	sp, #28
    6818:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		period.ticks = MAX(period.ticks - 1, 1);
    681c:	f118 31ff 	adds.w	r1, r8, #4294967295
    6820:	9104      	str	r1, [sp, #16]
    6822:	f149 31ff 	adc.w	r1, r9, #4294967295
    6826:	9105      	str	r1, [sp, #20]
    6828:	e9dd 7804 	ldrd	r7, r8, [sp, #16]
    682c:	4638      	mov	r0, r7
    682e:	4641      	mov	r1, r8
    6830:	2f01      	cmp	r7, #1
    6832:	f178 0700 	sbcs.w	r7, r8, #0
    6836:	db02      	blt.n	683e <z_impl_k_timer_start+0xae>
    6838:	4680      	mov	r8, r0
    683a:	4689      	mov	r9, r1
    683c:	e7d1      	b.n	67e2 <z_impl_k_timer_start+0x52>
    683e:	2001      	movs	r0, #1
    6840:	2100      	movs	r1, #0
    6842:	e7f9      	b.n	6838 <z_impl_k_timer_start+0xa8>
		duration.ticks = MAX(duration.ticks - 1, 0);
    6844:	f113 33ff 	adds.w	r3, r3, #4294967295
    6848:	9300      	str	r3, [sp, #0]
    684a:	f142 33ff 	adc.w	r3, r2, #4294967295
    684e:	9301      	str	r3, [sp, #4]
    6850:	e9dd 0100 	ldrd	r0, r1, [sp]
    6854:	4602      	mov	r2, r0
    6856:	460b      	mov	r3, r1
    6858:	2800      	cmp	r0, #0
    685a:	f171 0100 	sbcs.w	r1, r1, #0
    685e:	db02      	blt.n	6866 <z_impl_k_timer_start+0xd6>
    6860:	4614      	mov	r4, r2
    6862:	461d      	mov	r5, r3
    6864:	e7ca      	b.n	67fc <z_impl_k_timer_start+0x6c>
    6866:	2200      	movs	r2, #0
    6868:	4613      	mov	r3, r2
    686a:	e7f9      	b.n	6860 <z_impl_k_timer_start+0xd0>
    686c:	00006719 	.word	0x00006719

00006870 <boot_banner>:
#define BOOT_DELAY_BANNER ""
#endif

#if defined(CONFIG_BOOT_DELAY) || CONFIG_BOOT_DELAY > 0
void boot_banner(void)
{
    6870:	b508      	push	{r3, lr}
		k_busy_wait(CONFIG_BOOT_DELAY * USEC_PER_MSEC);
	}

#if defined(CONFIG_BOOT_BANNER)
#ifdef BUILD_VERSION
	printk("*** Booting Zephyr OS build %s %s ***\n",
    6872:	4a03      	ldr	r2, [pc, #12]	; (6880 <boot_banner+0x10>)
    6874:	4903      	ldr	r1, [pc, #12]	; (6884 <boot_banner+0x14>)
    6876:	4804      	ldr	r0, [pc, #16]	; (6888 <boot_banner+0x18>)
    6878:	f000 f860 	bl	693c <printk>
#else
	printk("*** Booting Zephyr OS version %s %s ***\n",
	       KERNEL_VERSION_STRING, BOOT_DELAY_BANNER);
#endif
#endif
}
    687c:	bd08      	pop	{r3, pc}
    687e:	bf00      	nop
    6880:	000084e8 	.word	0x000084e8
    6884:	00008e68 	.word	0x00008e68
    6888:	00008e74 	.word	0x00008e74

0000688c <k_sys_work_q_init>:
			     CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE);

struct k_work_q k_sys_work_q;

static int k_sys_work_q_init(const struct device *dev)
{
    688c:	b510      	push	{r4, lr}
    688e:	b084      	sub	sp, #16
	ARG_UNUSED(dev);
	struct k_work_queue_config cfg = {
    6890:	4b08      	ldr	r3, [pc, #32]	; (68b4 <k_sys_work_q_init+0x28>)
    6892:	9302      	str	r3, [sp, #8]
    6894:	2400      	movs	r4, #0
    6896:	f88d 400c 	strb.w	r4, [sp, #12]
		.name = "sysworkq",
		.no_yield = IS_ENABLED(CONFIG_SYSTEM_WORKQUEUE_NO_YIELD),
	};

	k_work_queue_start(&k_sys_work_q,
    689a:	ab02      	add	r3, sp, #8
    689c:	9300      	str	r3, [sp, #0]
    689e:	f04f 33ff 	mov.w	r3, #4294967295
    68a2:	f44f 6280 	mov.w	r2, #1024	; 0x400
    68a6:	4904      	ldr	r1, [pc, #16]	; (68b8 <k_sys_work_q_init+0x2c>)
    68a8:	4804      	ldr	r0, [pc, #16]	; (68bc <k_sys_work_q_init+0x30>)
    68aa:	f7ff f95b 	bl	5b64 <k_work_queue_start>
			    sys_work_q_stack,
			    K_KERNEL_STACK_SIZEOF(sys_work_q_stack),
			    CONFIG_SYSTEM_WORKQUEUE_PRIORITY, &cfg);
	return 0;
}
    68ae:	4620      	mov	r0, r4
    68b0:	b004      	add	sp, #16
    68b2:	bd10      	pop	{r4, pc}
    68b4:	00008e9c 	.word	0x00008e9c
    68b8:	20001bd0 	.word	0x20001bd0
    68bc:	20000348 	.word	0x20000348

000068c0 <sys_notify_validate>:

int sys_notify_validate(struct sys_notify *notify)
{
	int rv = 0;

	if (notify == NULL) {
    68c0:	4602      	mov	r2, r0
    68c2:	b158      	cbz	r0, 68dc <sys_notify_validate+0x1c>
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    68c4:	6843      	ldr	r3, [r0, #4]
	return method & SYS_NOTIFY_METHOD_MASK;
    68c6:	f003 0303 	and.w	r3, r3, #3
		return -EINVAL;
	}

	/* Validate configuration based on mode */
	switch (sys_notify_get_method(notify)) {
    68ca:	2b01      	cmp	r3, #1
    68cc:	d003      	beq.n	68d6 <sys_notify_validate+0x16>
    68ce:	2b03      	cmp	r3, #3
    68d0:	d107      	bne.n	68e2 <sys_notify_validate+0x22>
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		if (notify->method.callback == NULL) {
    68d2:	6803      	ldr	r3, [r0, #0]
    68d4:	b143      	cbz	r3, 68e8 <sys_notify_validate+0x28>
		break;
	}

	/* Clear the result here instead of in all callers. */
	if (rv == 0) {
		notify->result = 0;
    68d6:	2000      	movs	r0, #0
    68d8:	6090      	str	r0, [r2, #8]
    68da:	4770      	bx	lr
		return -EINVAL;
    68dc:	f06f 0015 	mvn.w	r0, #21
    68e0:	4770      	bx	lr
	switch (sys_notify_get_method(notify)) {
    68e2:	f06f 0015 	mvn.w	r0, #21
    68e6:	4770      	bx	lr
			rv = -EINVAL;
    68e8:	f06f 0015 	mvn.w	r0, #21
	}

	return rv;
}
    68ec:	4770      	bx	lr

000068ee <sys_notify_finalize>:

sys_notify_generic_callback sys_notify_finalize(struct sys_notify *notify,
						    int res)
{
    68ee:	4603      	mov	r3, r0
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    68f0:	6842      	ldr	r2, [r0, #4]
	return method & SYS_NOTIFY_METHOD_MASK;
    68f2:	f002 0203 	and.w	r2, r2, #3
	uint32_t method = sys_notify_get_method(notify);

	/* Store the result and capture secondary notification
	 * information.
	 */
	notify->result = res;
    68f6:	6081      	str	r1, [r0, #8]
	switch (method) {
    68f8:	2a03      	cmp	r2, #3
    68fa:	d103      	bne.n	6904 <sys_notify_finalize+0x16>
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		rv = notify->method.callback;
    68fc:	6800      	ldr	r0, [r0, #0]
	/* Mark completion by clearing the flags field to the
	 * completed state, releasing any spin-waiters, then complete
	 * secondary notification.
	 */
	compiler_barrier();
	notify->flags = SYS_NOTIFY_METHOD_COMPLETED;
    68fe:	2200      	movs	r2, #0
    6900:	605a      	str	r2, [r3, #4]
	if (IS_ENABLED(CONFIG_POLL) && (sig != NULL)) {
		k_poll_signal_raise(sig, res);
	}

	return rv;
}
    6902:	4770      	bx	lr
	sys_notify_generic_callback rv = NULL;
    6904:	2000      	movs	r0, #0
    6906:	e7fa      	b.n	68fe <sys_notify_finalize+0x10>

00006908 <arch_printk_char_out>:
}
    6908:	2000      	movs	r0, #0
    690a:	4770      	bx	lr

0000690c <str_out>:
{
    690c:	b410      	push	{r4}
	if (ctx->str == NULL || ctx->count >= ctx->max) {
    690e:	680c      	ldr	r4, [r1, #0]
    6910:	b154      	cbz	r4, 6928 <str_out+0x1c>
    6912:	688a      	ldr	r2, [r1, #8]
    6914:	684b      	ldr	r3, [r1, #4]
    6916:	429a      	cmp	r2, r3
    6918:	da06      	bge.n	6928 <str_out+0x1c>
	if (ctx->count == ctx->max - 1) {
    691a:	3b01      	subs	r3, #1
    691c:	429a      	cmp	r2, r3
    691e:	d008      	beq.n	6932 <str_out+0x26>
		ctx->str[ctx->count++] = c;
    6920:	1c53      	adds	r3, r2, #1
    6922:	608b      	str	r3, [r1, #8]
    6924:	54a0      	strb	r0, [r4, r2]
    6926:	e002      	b.n	692e <str_out+0x22>
		ctx->count++;
    6928:	688b      	ldr	r3, [r1, #8]
    692a:	3301      	adds	r3, #1
    692c:	608b      	str	r3, [r1, #8]
}
    692e:	bc10      	pop	{r4}
    6930:	4770      	bx	lr
		ctx->str[ctx->count++] = '\0';
    6932:	1c53      	adds	r3, r2, #1
    6934:	608b      	str	r3, [r1, #8]
    6936:	2300      	movs	r3, #0
    6938:	54a3      	strb	r3, [r4, r2]
    693a:	e7f8      	b.n	692e <str_out+0x22>

0000693c <printk>:
{
    693c:	b40f      	push	{r0, r1, r2, r3}
    693e:	b500      	push	{lr}
    6940:	b083      	sub	sp, #12
    6942:	a904      	add	r1, sp, #16
    6944:	f851 0b04 	ldr.w	r0, [r1], #4
	va_start(ap, fmt);
    6948:	9101      	str	r1, [sp, #4]
		vprintk(fmt, ap);
    694a:	f7f9 fdad 	bl	4a8 <vprintk>
}
    694e:	b003      	add	sp, #12
    6950:	f85d eb04 	ldr.w	lr, [sp], #4
    6954:	b004      	add	sp, #16
    6956:	4770      	bx	lr

00006958 <snprintk>:
{
    6958:	b40c      	push	{r2, r3}
    695a:	b500      	push	{lr}
    695c:	b083      	sub	sp, #12
    695e:	ab04      	add	r3, sp, #16
    6960:	f853 2b04 	ldr.w	r2, [r3], #4
	va_start(ap, fmt);
    6964:	9301      	str	r3, [sp, #4]
	ret = vsnprintk(str, size, fmt, ap);
    6966:	f7f9 fdaf 	bl	4c8 <vsnprintk>
}
    696a:	b003      	add	sp, #12
    696c:	f85d eb04 	ldr.w	lr, [sp], #4
    6970:	b002      	add	sp, #8
    6972:	4770      	bx	lr

00006974 <set_state>:
	mgr->flags = (state & ONOFF_STATE_MASK)
    6974:	f001 0307 	and.w	r3, r1, #7
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    6978:	8b81      	ldrh	r1, [r0, #28]
    697a:	f021 0107 	bic.w	r1, r1, #7
    697e:	4319      	orrs	r1, r3
	mgr->flags = (state & ONOFF_STATE_MASK)
    6980:	8381      	strh	r1, [r0, #28]
}
    6982:	4770      	bx	lr

00006984 <notify_monitors>:
{
    6984:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    6988:	4606      	mov	r6, r0
    698a:	460f      	mov	r7, r1
    698c:	4690      	mov	r8, r2
	return list->head;
    698e:	6881      	ldr	r1, [r0, #8]
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
    6990:	b119      	cbz	r1, 699a <notify_monitors+0x16>
    6992:	460c      	mov	r4, r1
Z_GENLIST_PEEK_NEXT(slist, snode)
    6994:	b131      	cbz	r1, 69a4 <notify_monitors+0x20>
	return node->next;
    6996:	680c      	ldr	r4, [r1, #0]
    6998:	e004      	b.n	69a4 <notify_monitors+0x20>
    699a:	460c      	mov	r4, r1
    699c:	e002      	b.n	69a4 <notify_monitors+0x20>
    699e:	4623      	mov	r3, r4
    69a0:	4621      	mov	r1, r4
    69a2:	461c      	mov	r4, r3
    69a4:	b159      	cbz	r1, 69be <notify_monitors+0x3a>
		mon->callback(mgr, mon, state, res);
    69a6:	684d      	ldr	r5, [r1, #4]
    69a8:	4643      	mov	r3, r8
    69aa:	463a      	mov	r2, r7
    69ac:	4630      	mov	r0, r6
    69ae:	47a8      	blx	r5
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
    69b0:	2c00      	cmp	r4, #0
    69b2:	d0f4      	beq.n	699e <notify_monitors+0x1a>
    69b4:	4623      	mov	r3, r4
Z_GENLIST_PEEK_NEXT(slist, snode)
    69b6:	2c00      	cmp	r4, #0
    69b8:	d0f2      	beq.n	69a0 <notify_monitors+0x1c>
	return node->next;
    69ba:	6823      	ldr	r3, [r4, #0]
    69bc:	e7f0      	b.n	69a0 <notify_monitors+0x1c>
}
    69be:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

000069c2 <process_recheck>:
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    69c2:	8b83      	ldrh	r3, [r0, #28]
	if ((state == ONOFF_STATE_OFF)
    69c4:	f013 0307 	ands.w	r3, r3, #7
    69c8:	d103      	bne.n	69d2 <process_recheck+0x10>
	return list->head;
    69ca:	6802      	ldr	r2, [r0, #0]
	    && !sys_slist_is_empty(&mgr->clients)) {
    69cc:	b10a      	cbz	r2, 69d2 <process_recheck+0x10>
		evt = EVT_START;
    69ce:	2003      	movs	r0, #3
    69d0:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ON)
    69d2:	2b02      	cmp	r3, #2
    69d4:	d003      	beq.n	69de <process_recheck+0x1c>
	} else if ((state == ONOFF_STATE_ERROR)
    69d6:	2b01      	cmp	r3, #1
    69d8:	d006      	beq.n	69e8 <process_recheck+0x26>
	int evt = EVT_NOP;
    69da:	2000      	movs	r0, #0
    69dc:	4770      	bx	lr
		   && (mgr->refs == 0U)) {
    69de:	8bc2      	ldrh	r2, [r0, #30]
    69e0:	2a00      	cmp	r2, #0
    69e2:	d1f8      	bne.n	69d6 <process_recheck+0x14>
		evt = EVT_STOP;
    69e4:	2004      	movs	r0, #4
    69e6:	4770      	bx	lr
    69e8:	6803      	ldr	r3, [r0, #0]
		   && !sys_slist_is_empty(&mgr->clients)) {
    69ea:	b10b      	cbz	r3, 69f0 <process_recheck+0x2e>
		evt = EVT_RESET;
    69ec:	2005      	movs	r0, #5
}
    69ee:	4770      	bx	lr
	int evt = EVT_NOP;
    69f0:	2000      	movs	r0, #0
    69f2:	4770      	bx	lr

000069f4 <process_complete>:
{
    69f4:	b538      	push	{r3, r4, r5, lr}
    69f6:	4604      	mov	r4, r0
    69f8:	460d      	mov	r5, r1
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    69fa:	8b83      	ldrh	r3, [r0, #28]
	if (res < 0) {
    69fc:	2a00      	cmp	r2, #0
    69fe:	db07      	blt.n	6a10 <process_complete+0x1c>
    6a00:	f003 0307 	and.w	r3, r3, #7
		   || (state == ONOFF_STATE_RESETTING)) {
    6a04:	1f5a      	subs	r2, r3, #5
	} else if ((state == ONOFF_STATE_TO_ON)
    6a06:	2a01      	cmp	r2, #1
    6a08:	d90e      	bls.n	6a28 <process_complete+0x34>
	} else if (state == ONOFF_STATE_TO_OFF) {
    6a0a:	2b04      	cmp	r3, #4
    6a0c:	d032      	beq.n	6a74 <process_complete+0x80>
}
    6a0e:	bd38      	pop	{r3, r4, r5, pc}
		*clients = mgr->clients;
    6a10:	e9d0 0100 	ldrd	r0, r1, [r0]
    6a14:	e885 0003 	stmia.w	r5, {r0, r1}
	list->head = NULL;
    6a18:	2300      	movs	r3, #0
    6a1a:	6023      	str	r3, [r4, #0]
	list->tail = NULL;
    6a1c:	6063      	str	r3, [r4, #4]
		set_state(mgr, ONOFF_STATE_ERROR);
    6a1e:	2101      	movs	r1, #1
    6a20:	4620      	mov	r0, r4
    6a22:	f7ff ffa7 	bl	6974 <set_state>
    6a26:	e7f2      	b.n	6a0e <process_complete+0x1a>
		*clients = mgr->clients;
    6a28:	e9d0 0100 	ldrd	r0, r1, [r0]
    6a2c:	e885 0003 	stmia.w	r5, {r0, r1}
	list->head = NULL;
    6a30:	2200      	movs	r2, #0
    6a32:	6022      	str	r2, [r4, #0]
	list->tail = NULL;
    6a34:	6062      	str	r2, [r4, #4]
		if (state == ONOFF_STATE_TO_ON) {
    6a36:	2b06      	cmp	r3, #6
    6a38:	d117      	bne.n	6a6a <process_complete+0x76>
	return list->head;
    6a3a:	682b      	ldr	r3, [r5, #0]
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
    6a3c:	b13b      	cbz	r3, 6a4e <process_complete+0x5a>
				mgr->refs += 1U;
    6a3e:	8be2      	ldrh	r2, [r4, #30]
    6a40:	3201      	adds	r2, #1
    6a42:	83e2      	strh	r2, [r4, #30]
Z_GENLIST_PEEK_NEXT(slist, snode)
    6a44:	2b00      	cmp	r3, #0
    6a46:	d0f9      	beq.n	6a3c <process_complete+0x48>
	return node->next;
    6a48:	681b      	ldr	r3, [r3, #0]
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
    6a4a:	2b00      	cmp	r3, #0
    6a4c:	d1f6      	bne.n	6a3c <process_complete+0x48>
			set_state(mgr, ONOFF_STATE_ON);
    6a4e:	2102      	movs	r1, #2
    6a50:	4620      	mov	r0, r4
    6a52:	f7ff ff8f 	bl	6974 <set_state>
		if (process_recheck(mgr) != EVT_NOP) {
    6a56:	4620      	mov	r0, r4
    6a58:	f7ff ffb3 	bl	69c2 <process_recheck>
    6a5c:	2800      	cmp	r0, #0
    6a5e:	d0d6      	beq.n	6a0e <process_complete+0x1a>
			mgr->flags |= ONOFF_FLAG_RECHECK;
    6a60:	8ba3      	ldrh	r3, [r4, #28]
    6a62:	f043 0320 	orr.w	r3, r3, #32
    6a66:	83a3      	strh	r3, [r4, #28]
    6a68:	e7d1      	b.n	6a0e <process_complete+0x1a>
			set_state(mgr, ONOFF_STATE_OFF);
    6a6a:	2100      	movs	r1, #0
    6a6c:	4620      	mov	r0, r4
    6a6e:	f7ff ff81 	bl	6974 <set_state>
    6a72:	e7f0      	b.n	6a56 <process_complete+0x62>
		set_state(mgr, ONOFF_STATE_OFF);
    6a74:	2100      	movs	r1, #0
    6a76:	f7ff ff7d 	bl	6974 <set_state>
		if (process_recheck(mgr) != EVT_NOP) {
    6a7a:	4620      	mov	r0, r4
    6a7c:	f7ff ffa1 	bl	69c2 <process_recheck>
    6a80:	2800      	cmp	r0, #0
    6a82:	d0c4      	beq.n	6a0e <process_complete+0x1a>
			mgr->flags |= ONOFF_FLAG_RECHECK;
    6a84:	8ba3      	ldrh	r3, [r4, #28]
    6a86:	f043 0320 	orr.w	r3, r3, #32
    6a8a:	83a3      	strh	r3, [r4, #28]
}
    6a8c:	e7bf      	b.n	6a0e <process_complete+0x1a>

00006a8e <validate_args>:
	if ((mgr == NULL) || (cli == NULL)) {
    6a8e:	b158      	cbz	r0, 6aa8 <validate_args+0x1a>
{
    6a90:	b510      	push	{r4, lr}
    6a92:	460c      	mov	r4, r1
	if ((mgr == NULL) || (cli == NULL)) {
    6a94:	b159      	cbz	r1, 6aae <validate_args+0x20>
	int rv = sys_notify_validate(&cli->notify);
    6a96:	1d08      	adds	r0, r1, #4
    6a98:	f7ff ff12 	bl	68c0 <sys_notify_validate>
	if ((rv == 0)
    6a9c:	b918      	cbnz	r0, 6aa6 <validate_args+0x18>
	    && ((cli->notify.flags
    6a9e:	68a3      	ldr	r3, [r4, #8]
    6aa0:	f033 0303 	bics.w	r3, r3, #3
    6aa4:	d106      	bne.n	6ab4 <validate_args+0x26>
}
    6aa6:	bd10      	pop	{r4, pc}
		return -EINVAL;
    6aa8:	f06f 0015 	mvn.w	r0, #21
}
    6aac:	4770      	bx	lr
		return -EINVAL;
    6aae:	f06f 0015 	mvn.w	r0, #21
    6ab2:	e7f8      	b.n	6aa6 <validate_args+0x18>
		rv = -EINVAL;
    6ab4:	f06f 0015 	mvn.w	r0, #21
    6ab8:	e7f5      	b.n	6aa6 <validate_args+0x18>

00006aba <notify_one>:
{
    6aba:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    6abe:	4607      	mov	r7, r0
    6ac0:	460c      	mov	r4, r1
    6ac2:	4616      	mov	r6, r2
    6ac4:	461d      	mov	r5, r3
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    6ac6:	4619      	mov	r1, r3
    6ac8:	1d20      	adds	r0, r4, #4
    6aca:	f7ff ff10 	bl	68ee <sys_notify_finalize>
	if (cb) {
    6ace:	b128      	cbz	r0, 6adc <notify_one+0x22>
    6ad0:	4680      	mov	r8, r0
		cb(mgr, cli, state, res);
    6ad2:	462b      	mov	r3, r5
    6ad4:	4632      	mov	r2, r6
    6ad6:	4621      	mov	r1, r4
    6ad8:	4638      	mov	r0, r7
    6ada:	47c0      	blx	r8
}
    6adc:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00006ae0 <notify_all>:
{
    6ae0:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    6ae4:	4681      	mov	r9, r0
    6ae6:	460c      	mov	r4, r1
    6ae8:	4690      	mov	r8, r2
    6aea:	461f      	mov	r7, r3
	while (!sys_slist_is_empty(list)) {
    6aec:	e005      	b.n	6afa <notify_all+0x1a>
	list->tail = node;
    6aee:	6065      	str	r5, [r4, #4]
		notify_one(mgr, cli, state, res);
    6af0:	463b      	mov	r3, r7
    6af2:	4642      	mov	r2, r8
    6af4:	4648      	mov	r0, r9
    6af6:	f7ff ffe0 	bl	6aba <notify_one>
	return list->head;
    6afa:	6821      	ldr	r1, [r4, #0]
	while (!sys_slist_is_empty(list)) {
    6afc:	b129      	cbz	r1, 6b0a <notify_all+0x2a>
	return node->next;
    6afe:	680d      	ldr	r5, [r1, #0]
	list->head = node;
    6b00:	6025      	str	r5, [r4, #0]
	return list->tail;
    6b02:	6866      	ldr	r6, [r4, #4]
Z_GENLIST_GET_NOT_EMPTY(slist, snode)
    6b04:	428e      	cmp	r6, r1
    6b06:	d1f3      	bne.n	6af0 <notify_all+0x10>
    6b08:	e7f1      	b.n	6aee <notify_all+0xe>
}
    6b0a:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}

00006b0e <transition_complete>:
{
    6b0e:	b510      	push	{r4, lr}
	__asm__ volatile(
    6b10:	f04f 0420 	mov.w	r4, #32
    6b14:	f3ef 8211 	mrs	r2, BASEPRI
    6b18:	f384 8812 	msr	BASEPRI_MAX, r4
    6b1c:	f3bf 8f6f 	isb	sy
	mgr->last_res = res;
    6b20:	6181      	str	r1, [r0, #24]
	process_event(mgr, EVT_COMPLETE, key);
    6b22:	2101      	movs	r1, #1
    6b24:	f7f9 fce6 	bl	4f4 <process_event>
}
    6b28:	bd10      	pop	{r4, pc}

00006b2a <onoff_manager_init>:
	if ((mgr == NULL)
    6b2a:	b170      	cbz	r0, 6b4a <onoff_manager_init+0x20>
{
    6b2c:	b538      	push	{r3, r4, r5, lr}
    6b2e:	460c      	mov	r4, r1
    6b30:	4605      	mov	r5, r0
	    || (transitions == NULL)
    6b32:	b169      	cbz	r1, 6b50 <onoff_manager_init+0x26>
	    || (transitions->start == NULL)
    6b34:	680b      	ldr	r3, [r1, #0]
    6b36:	b173      	cbz	r3, 6b56 <onoff_manager_init+0x2c>
	    || (transitions->stop == NULL)) {
    6b38:	684b      	ldr	r3, [r1, #4]
    6b3a:	b17b      	cbz	r3, 6b5c <onoff_manager_init+0x32>
	*mgr = (struct onoff_manager)ONOFF_MANAGER_INITIALIZER(transitions);
    6b3c:	2220      	movs	r2, #32
    6b3e:	2100      	movs	r1, #0
    6b40:	f001 faa9 	bl	8096 <memset>
    6b44:	612c      	str	r4, [r5, #16]
	return 0;
    6b46:	2000      	movs	r0, #0
}
    6b48:	bd38      	pop	{r3, r4, r5, pc}
		return -EINVAL;
    6b4a:	f06f 0015 	mvn.w	r0, #21
}
    6b4e:	4770      	bx	lr
		return -EINVAL;
    6b50:	f06f 0015 	mvn.w	r0, #21
    6b54:	e7f8      	b.n	6b48 <onoff_manager_init+0x1e>
    6b56:	f06f 0015 	mvn.w	r0, #21
    6b5a:	e7f5      	b.n	6b48 <onoff_manager_init+0x1e>
    6b5c:	f06f 0015 	mvn.w	r0, #21
    6b60:	e7f2      	b.n	6b48 <onoff_manager_init+0x1e>

00006b62 <onoff_request>:

int onoff_request(struct onoff_manager *mgr,
		  struct onoff_client *cli)
{
    6b62:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    6b64:	4604      	mov	r4, r0
    6b66:	460f      	mov	r7, r1
	bool add_client = false;        /* add client to pending list */
	bool start = false;             /* trigger a start transition */
	bool notify = false;            /* do client notification */
	int rv = validate_args(mgr, cli);
    6b68:	f7ff ff91 	bl	6a8e <validate_args>

	if (rv < 0) {
    6b6c:	1e06      	subs	r6, r0, #0
    6b6e:	db37      	blt.n	6be0 <onoff_request+0x7e>
    6b70:	f04f 0320 	mov.w	r3, #32
    6b74:	f3ef 8211 	mrs	r2, BASEPRI
    6b78:	f383 8812 	msr	BASEPRI_MAX, r3
    6b7c:	f3bf 8f6f 	isb	sy
		return rv;
	}

	k_spinlock_key_t key = k_spin_lock(&mgr->lock);
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    6b80:	8ba5      	ldrh	r5, [r4, #28]
    6b82:	f005 0507 	and.w	r5, r5, #7

	/* Reject if this would overflow the reference count. */
	if (mgr->refs == SERVICE_REFS_MAX) {
    6b86:	8be3      	ldrh	r3, [r4, #30]
    6b88:	f64f 71ff 	movw	r1, #65535	; 0xffff
    6b8c:	428b      	cmp	r3, r1
    6b8e:	d02f      	beq.n	6bf0 <onoff_request+0x8e>
		rv = -EAGAIN;
		goto out;
	}

	rv = state;
    6b90:	462e      	mov	r6, r5
	if (state == ONOFF_STATE_ON) {
    6b92:	2d02      	cmp	r5, #2
    6b94:	d00c      	beq.n	6bb0 <onoff_request+0x4e>
		/* Increment reference count, notify in exit */
		notify = true;
		mgr->refs += 1U;
	} else if ((state == ONOFF_STATE_OFF)
    6b96:	b18d      	cbz	r5, 6bbc <onoff_request+0x5a>
		   || (state == ONOFF_STATE_TO_OFF)
    6b98:	2d04      	cmp	r5, #4
    6b9a:	d00f      	beq.n	6bbc <onoff_request+0x5a>
		   || (state == ONOFF_STATE_TO_ON)) {
    6b9c:	2d06      	cmp	r5, #6
    6b9e:	d00d      	beq.n	6bbc <onoff_request+0x5a>
		/* Start if OFF, queue client */
		start = (state == ONOFF_STATE_OFF);
		add_client = true;
	} else if (state == ONOFF_STATE_RESETTING) {
    6ba0:	2d05      	cmp	r5, #5
    6ba2:	d01f      	beq.n	6be4 <onoff_request+0x82>
		rv = -ENOTSUP;
	} else {
		__ASSERT_NO_MSG(state == ONOFF_STATE_ERROR);
		rv = -EIO;
    6ba4:	f06f 0604 	mvn.w	r6, #4
	bool notify = false;            /* do client notification */
    6ba8:	2100      	movs	r1, #0
	bool start = false;             /* trigger a start transition */
    6baa:	460b      	mov	r3, r1
	bool add_client = false;        /* add client to pending list */
    6bac:	4608      	mov	r0, r1
    6bae:	e00a      	b.n	6bc6 <onoff_request+0x64>
		mgr->refs += 1U;
    6bb0:	3301      	adds	r3, #1
    6bb2:	83e3      	strh	r3, [r4, #30]
		notify = true;
    6bb4:	2101      	movs	r1, #1
	bool start = false;             /* trigger a start transition */
    6bb6:	2300      	movs	r3, #0
	bool add_client = false;        /* add client to pending list */
    6bb8:	4618      	mov	r0, r3
    6bba:	e004      	b.n	6bc6 <onoff_request+0x64>
		start = (state == ONOFF_STATE_OFF);
    6bbc:	fab5 f385 	clz	r3, r5
    6bc0:	095b      	lsrs	r3, r3, #5
	bool notify = false;            /* do client notification */
    6bc2:	2100      	movs	r1, #0
		add_client = true;
    6bc4:	2001      	movs	r0, #1
	}

out:
	if (add_client) {
    6bc6:	b128      	cbz	r0, 6bd4 <onoff_request+0x72>
	parent->next = child;
    6bc8:	2000      	movs	r0, #0
    6bca:	6038      	str	r0, [r7, #0]
	return list->tail;
    6bcc:	6860      	ldr	r0, [r4, #4]
Z_GENLIST_APPEND(slist, snode)
    6bce:	b1a8      	cbz	r0, 6bfc <onoff_request+0x9a>
	parent->next = child;
    6bd0:	6007      	str	r7, [r0, #0]
	list->tail = node;
    6bd2:	6067      	str	r7, [r4, #4]
		sys_slist_append(&mgr->clients, &cli->node);
	}

	if (start) {
    6bd4:	b9ab      	cbnz	r3, 6c02 <onoff_request+0xa0>
	__asm__ volatile(
    6bd6:	f382 8811 	msr	BASEPRI, r2
    6bda:	f3bf 8f6f 	isb	sy
		process_event(mgr, EVT_RECHECK, key);
	} else {
		k_spin_unlock(&mgr->lock, key);

		if (notify) {
    6bde:	b9a9      	cbnz	r1, 6c0c <onoff_request+0xaa>
			notify_one(mgr, cli, state, 0);
		}
	}

	return rv;
}
    6be0:	4630      	mov	r0, r6
    6be2:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
		rv = -ENOTSUP;
    6be4:	f06f 0685 	mvn.w	r6, #133	; 0x85
	bool notify = false;            /* do client notification */
    6be8:	2100      	movs	r1, #0
	bool start = false;             /* trigger a start transition */
    6bea:	460b      	mov	r3, r1
	bool add_client = false;        /* add client to pending list */
    6bec:	4608      	mov	r0, r1
    6bee:	e7ea      	b.n	6bc6 <onoff_request+0x64>
		rv = -EAGAIN;
    6bf0:	f06f 060a 	mvn.w	r6, #10
	bool notify = false;            /* do client notification */
    6bf4:	2100      	movs	r1, #0
	bool start = false;             /* trigger a start transition */
    6bf6:	460b      	mov	r3, r1
	bool add_client = false;        /* add client to pending list */
    6bf8:	4608      	mov	r0, r1
    6bfa:	e7e4      	b.n	6bc6 <onoff_request+0x64>
    6bfc:	6067      	str	r7, [r4, #4]
	list->head = node;
    6bfe:	6027      	str	r7, [r4, #0]
}
    6c00:	e7e8      	b.n	6bd4 <onoff_request+0x72>
		process_event(mgr, EVT_RECHECK, key);
    6c02:	2102      	movs	r1, #2
    6c04:	4620      	mov	r0, r4
    6c06:	f7f9 fc75 	bl	4f4 <process_event>
    6c0a:	e7e9      	b.n	6be0 <onoff_request+0x7e>
			notify_one(mgr, cli, state, 0);
    6c0c:	2300      	movs	r3, #0
    6c0e:	462a      	mov	r2, r5
    6c10:	4639      	mov	r1, r7
    6c12:	4620      	mov	r0, r4
    6c14:	f7ff ff51 	bl	6aba <notify_one>
    6c18:	e7e2      	b.n	6be0 <onoff_request+0x7e>

00006c1a <onoff_release>:

int onoff_release(struct onoff_manager *mgr)
{
    6c1a:	b510      	push	{r4, lr}
	__asm__ volatile(
    6c1c:	f04f 0320 	mov.w	r3, #32
    6c20:	f3ef 8211 	mrs	r2, BASEPRI
    6c24:	f383 8812 	msr	BASEPRI_MAX, r3
    6c28:	f3bf 8f6f 	isb	sy
	bool stop = false;      /* trigger a stop transition */

	k_spinlock_key_t key = k_spin_lock(&mgr->lock);
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    6c2c:	8b83      	ldrh	r3, [r0, #28]
    6c2e:	f003 0307 	and.w	r3, r3, #7
	int rv = state;

	if (state != ONOFF_STATE_ON) {
    6c32:	2b02      	cmp	r3, #2
    6c34:	d007      	beq.n	6c46 <onoff_release+0x2c>
		if (state == ONOFF_STATE_ERROR) {
    6c36:	2b01      	cmp	r3, #1
    6c38:	d002      	beq.n	6c40 <onoff_release+0x26>
			rv = -EIO;
		} else {
			rv = -ENOTSUP;
    6c3a:	f06f 0485 	mvn.w	r4, #133	; 0x85
	__ASSERT_NO_MSG(mgr->refs > 0);
	mgr->refs -= 1U;
	stop = (mgr->refs == 0);

out:
	if (stop) {
    6c3e:	e008      	b.n	6c52 <onoff_release+0x38>
			rv = -EIO;
    6c40:	f06f 0404 	mvn.w	r4, #4
    6c44:	e005      	b.n	6c52 <onoff_release+0x38>
    6c46:	461c      	mov	r4, r3
	mgr->refs -= 1U;
    6c48:	8bc3      	ldrh	r3, [r0, #30]
    6c4a:	3b01      	subs	r3, #1
    6c4c:	b29b      	uxth	r3, r3
    6c4e:	83c3      	strh	r3, [r0, #30]
	if (stop) {
    6c50:	b12b      	cbz	r3, 6c5e <onoff_release+0x44>
	__asm__ volatile(
    6c52:	f382 8811 	msr	BASEPRI, r2
    6c56:	f3bf 8f6f 	isb	sy
	} else {
		k_spin_unlock(&mgr->lock, key);
	}

	return rv;
}
    6c5a:	4620      	mov	r0, r4
    6c5c:	bd10      	pop	{r4, pc}
		process_event(mgr, EVT_RECHECK, key);
    6c5e:	2102      	movs	r1, #2
    6c60:	f7f9 fc48 	bl	4f4 <process_event>
    6c64:	e7f9      	b.n	6c5a <onoff_release+0x40>

00006c66 <z_thread_entry>:
 * This routine does not return, and is marked as such so the compiler won't
 * generate preamble code that is only used by functions that actually return.
 */
FUNC_NORETURN void z_thread_entry(k_thread_entry_t entry,
				 void *p1, void *p2, void *p3)
{
    6c66:	b508      	push	{r3, lr}
    6c68:	4604      	mov	r4, r0
    6c6a:	4608      	mov	r0, r1
    6c6c:	4611      	mov	r1, r2
#ifdef CONFIG_THREAD_LOCAL_STORAGE
	z_tls_current = z_current_get();
#endif
	entry(p1, p2, p3);
    6c6e:	461a      	mov	r2, r3
    6c70:	47a0      	blx	r4
	return z_impl_z_current_get();
    6c72:	f7ff fb73 	bl	635c <z_impl_z_current_get>
	z_impl_k_thread_abort(thread);
    6c76:	f7fb ffdd 	bl	2c34 <z_impl_k_thread_abort>

00006c7a <outs>:
{
    6c7a:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    6c7e:	4607      	mov	r7, r0
    6c80:	460e      	mov	r6, r1
    6c82:	4614      	mov	r4, r2
    6c84:	4698      	mov	r8, r3
	size_t count = 0;
    6c86:	2500      	movs	r5, #0
	while ((sp < ep) || ((ep == NULL) && *sp)) {
    6c88:	e006      	b.n	6c98 <outs+0x1e>
		int rc = out((int)*sp++, ctx);
    6c8a:	4631      	mov	r1, r6
    6c8c:	f814 0b01 	ldrb.w	r0, [r4], #1
    6c90:	47b8      	blx	r7
		if (rc < 0) {
    6c92:	2800      	cmp	r0, #0
    6c94:	db09      	blt.n	6caa <outs+0x30>
		++count;
    6c96:	3501      	adds	r5, #1
	while ((sp < ep) || ((ep == NULL) && *sp)) {
    6c98:	4544      	cmp	r4, r8
    6c9a:	d3f6      	bcc.n	6c8a <outs+0x10>
    6c9c:	f1b8 0f00 	cmp.w	r8, #0
    6ca0:	d102      	bne.n	6ca8 <outs+0x2e>
    6ca2:	7823      	ldrb	r3, [r4, #0]
    6ca4:	2b00      	cmp	r3, #0
    6ca6:	d1f0      	bne.n	6c8a <outs+0x10>
	return (int)count;
    6ca8:	4628      	mov	r0, r5
}
    6caa:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00006cae <_ConfigAbsSyms>:
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_OUTPUT_DISASSEMBLY, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_OUTPUT_PRINT_MEMORY_USAGE, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_BUILD_OUTPUT_BIN, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_COMPAT_INCLUDES, 1);

GEN_ABS_SYM_END
    6cae:	4770      	bx	lr

00006cb0 <log_list_init>:

#include "log_list.h"

void log_list_init(struct log_list_t *list)
{
	list->tail = NULL;
    6cb0:	2300      	movs	r3, #0
    6cb2:	6043      	str	r3, [r0, #4]
	list->head = NULL;
    6cb4:	6003      	str	r3, [r0, #0]
}
    6cb6:	4770      	bx	lr

00006cb8 <log_list_add_tail>:

void log_list_add_tail(struct log_list_t *list, struct log_msg *msg)
{
	if (list->head == NULL) {
    6cb8:	6803      	ldr	r3, [r0, #0]
    6cba:	b12b      	cbz	r3, 6cc8 <log_list_add_tail+0x10>
		list->head = msg;
	} else {
		list->tail->next = msg;
    6cbc:	6843      	ldr	r3, [r0, #4]
    6cbe:	6019      	str	r1, [r3, #0]
	}

	list->tail = msg;
    6cc0:	6041      	str	r1, [r0, #4]
	msg->next = NULL;
    6cc2:	2300      	movs	r3, #0
    6cc4:	600b      	str	r3, [r1, #0]
}
    6cc6:	4770      	bx	lr
		list->head = msg;
    6cc8:	6001      	str	r1, [r0, #0]
    6cca:	e7f9      	b.n	6cc0 <log_list_add_tail+0x8>

00006ccc <log_list_head_peek>:

struct log_msg *log_list_head_peek(struct log_list_t *list)
{
	return list->head;
}
    6ccc:	6800      	ldr	r0, [r0, #0]
    6cce:	4770      	bx	lr

00006cd0 <log_list_head_get>:

struct log_msg *log_list_head_get(struct log_list_t *list)
{
    6cd0:	4603      	mov	r3, r0
	struct log_msg *msg = list->head;
    6cd2:	6800      	ldr	r0, [r0, #0]

	if (list->head != NULL) {
    6cd4:	b108      	cbz	r0, 6cda <log_list_head_get+0xa>
		list->head = list->head->next;
    6cd6:	6802      	ldr	r2, [r0, #0]
    6cd8:	601a      	str	r2, [r3, #0]
	}

	return msg;
}
    6cda:	4770      	bx	lr

00006cdc <dummy_timestamp>:
}
    6cdc:	2000      	movs	r0, #0
    6cde:	4770      	bx	lr

00006ce0 <msg_filter_check>:
}
    6ce0:	2001      	movs	r0, #1
    6ce2:	4770      	bx	lr

00006ce4 <default_get_timestamp>:
{
    6ce4:	b508      	push	{r3, lr}
#ifndef _ASMLANGUAGE
extern uint32_t sys_clock_cycle_get_32(void);

static inline uint32_t arch_k_cycle_get_32(void)
{
	return sys_clock_cycle_get_32();
    6ce6:	f000 fd39 	bl	775c <sys_clock_cycle_get_32>
}
    6cea:	bd08      	pop	{r3, pc}

00006cec <block_on_alloc>:
}
    6cec:	2000      	movs	r0, #0
    6cee:	4770      	bx	lr

00006cf0 <cont_arg_get>:

static log_arg_t cont_arg_get(struct log_msg *msg, uint32_t arg_idx)
{
	struct log_msg_cont *cont;

	if (arg_idx < LOG_MSG_NARGS_HEAD_CHUNK) {
    6cf0:	2901      	cmp	r1, #1
    6cf2:	d906      	bls.n	6d02 <cont_arg_get+0x12>
		return msg->payload.ext.data.args[arg_idx];
	}


	cont = msg->payload.ext.next;
    6cf4:	6943      	ldr	r3, [r0, #20]
	arg_idx -= LOG_MSG_NARGS_HEAD_CHUNK;
    6cf6:	3902      	subs	r1, #2

	while (arg_idx >= ARGS_CONT_MSG) {
    6cf8:	2906      	cmp	r1, #6
    6cfa:	d907      	bls.n	6d0c <cont_arg_get+0x1c>
		arg_idx -= ARGS_CONT_MSG;
    6cfc:	3907      	subs	r1, #7
		cont = cont->next;
    6cfe:	681b      	ldr	r3, [r3, #0]
    6d00:	e7fa      	b.n	6cf8 <cont_arg_get+0x8>
		return msg->payload.ext.data.args[arg_idx];
    6d02:	3104      	adds	r1, #4
    6d04:	eb00 0181 	add.w	r1, r0, r1, lsl #2
    6d08:	6888      	ldr	r0, [r1, #8]
    6d0a:	4770      	bx	lr
	}

	return cont->payload.args[arg_idx];
    6d0c:	eb03 0181 	add.w	r1, r3, r1, lsl #2
    6d10:	6848      	ldr	r0, [r1, #4]
}
    6d12:	4770      	bx	lr

00006d14 <log_msg_hexdump_data_op>:
static void log_msg_hexdump_data_op(struct log_msg *msg,
				    uint8_t *data,
				    size_t *length,
				    size_t offset,
				    bool put_op)
{
    6d14:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    6d18:	461c      	mov	r4, r3
    6d1a:	f89d 9020 	ldrb.w	r9, [sp, #32]
	uint32_t available_len = msg->hdr.params.hexdump.length;
    6d1e:	8903      	ldrh	r3, [r0, #8]
    6d20:	f3c3 038d 	ubfx	r3, r3, #2, #14
	uint8_t *head_data;
	uint32_t chunk_len;
	uint32_t req_len;
	uint32_t cpy_len;

	if (offset >= available_len) {
    6d24:	42a3      	cmp	r3, r4
    6d26:	d91f      	bls.n	6d68 <log_msg_hexdump_data_op+0x54>
    6d28:	4688      	mov	r8, r1
		*length = 0;
		return;
	}

	if ((offset + *length) > available_len) {
    6d2a:	6811      	ldr	r1, [r2, #0]
    6d2c:	4421      	add	r1, r4
    6d2e:	4299      	cmp	r1, r3
    6d30:	d901      	bls.n	6d36 <log_msg_hexdump_data_op+0x22>
		*length = available_len - offset;
    6d32:	1b19      	subs	r1, r3, r4
    6d34:	6011      	str	r1, [r2, #0]
	}

	req_len = *length;
    6d36:	6817      	ldr	r7, [r2, #0]

	if (available_len > LOG_MSG_HEXDUMP_BYTES_SINGLE_CHUNK) {
    6d38:	2b0c      	cmp	r3, #12
    6d3a:	d919      	bls.n	6d70 <log_msg_hexdump_data_op+0x5c>
		chunk_len = LOG_MSG_HEXDUMP_BYTES_HEAD_CHUNK;
		head_data = msg->payload.ext.data.bytes;
    6d3c:	f100 0c18 	add.w	ip, r0, #24
		cont = msg->payload.ext.next;
    6d40:	6946      	ldr	r6, [r0, #20]
		chunk_len = LOG_MSG_HEXDUMP_BYTES_HEAD_CHUNK;
    6d42:	2308      	movs	r3, #8
		head_data = msg->payload.single.bytes;
		chunk_len = available_len;

	}

	if (offset < chunk_len) {
    6d44:	42a3      	cmp	r3, r4
    6d46:	d91e      	bls.n	6d86 <log_msg_hexdump_data_op+0x72>
		cpy_len = req_len > chunk_len ? chunk_len : req_len;
    6d48:	42bb      	cmp	r3, r7
    6d4a:	bf28      	it	cs
    6d4c:	463b      	movcs	r3, r7
    6d4e:	461d      	mov	r5, r3

		if (put_op) {
    6d50:	f1b9 0f00 	cmp.w	r9, #0
    6d54:	d010      	beq.n	6d78 <log_msg_hexdump_data_op+0x64>
    6d56:	461a      	mov	r2, r3
    6d58:	4641      	mov	r1, r8
    6d5a:	eb0c 0004 	add.w	r0, ip, r4
    6d5e:	f001 f98c 	bl	807a <memcpy>
			(void)memcpy(&head_data[offset], data, cpy_len);
		} else {
			(void)memcpy(data, &head_data[offset], cpy_len);
		}

		req_len -= cpy_len;
    6d62:	1b7f      	subs	r7, r7, r5
		data += cpy_len;
    6d64:	44a8      	add	r8, r5
    6d66:	e021      	b.n	6dac <log_msg_hexdump_data_op+0x98>
		*length = 0;
    6d68:	2300      	movs	r3, #0
    6d6a:	6013      	str	r3, [r2, #0]
		offset = 0;
		cont = cont->next;
		req_len -= cpy_len;
		data += cpy_len;
	}
}
    6d6c:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
		head_data = msg->payload.single.bytes;
    6d70:	f100 0c14 	add.w	ip, r0, #20
	struct log_msg_cont *cont = NULL;
    6d74:	2600      	movs	r6, #0
    6d76:	e7e5      	b.n	6d44 <log_msg_hexdump_data_op+0x30>
    6d78:	461a      	mov	r2, r3
    6d7a:	eb0c 0104 	add.w	r1, ip, r4
    6d7e:	4640      	mov	r0, r8
    6d80:	f001 f97b 	bl	807a <memcpy>
    6d84:	e7ed      	b.n	6d62 <log_msg_hexdump_data_op+0x4e>
		offset -= chunk_len;
    6d86:	1ae4      	subs	r4, r4, r3
		if (cont == NULL) {
    6d88:	b91e      	cbnz	r6, 6d92 <log_msg_hexdump_data_op+0x7e>
			cont = msg->payload.ext.next;
    6d8a:	6946      	ldr	r6, [r0, #20]
    6d8c:	e001      	b.n	6d92 <log_msg_hexdump_data_op+0x7e>
			cont = cont->next;
    6d8e:	6836      	ldr	r6, [r6, #0]
			offset -= chunk_len;
    6d90:	3c1c      	subs	r4, #28
		while (offset >= chunk_len) {
    6d92:	2c1b      	cmp	r4, #27
    6d94:	d8fb      	bhi.n	6d8e <log_msg_hexdump_data_op+0x7a>
    6d96:	e009      	b.n	6dac <log_msg_hexdump_data_op+0x98>
			(void)memcpy(data, &cont->payload.bytes[offset],
    6d98:	1931      	adds	r1, r6, r4
    6d9a:	462a      	mov	r2, r5
    6d9c:	3104      	adds	r1, #4
    6d9e:	4640      	mov	r0, r8
    6da0:	f001 f96b 	bl	807a <memcpy>
		cont = cont->next;
    6da4:	6836      	ldr	r6, [r6, #0]
		req_len -= cpy_len;
    6da6:	1b7f      	subs	r7, r7, r5
		data += cpy_len;
    6da8:	44a8      	add	r8, r5
		offset = 0;
    6daa:	2400      	movs	r4, #0
	while ((req_len > 0) && (cont != NULL)) {
    6dac:	2f00      	cmp	r7, #0
    6dae:	d0dd      	beq.n	6d6c <log_msg_hexdump_data_op+0x58>
    6db0:	2e00      	cmp	r6, #0
    6db2:	d0db      	beq.n	6d6c <log_msg_hexdump_data_op+0x58>
		chunk_len = HEXDUMP_BYTES_CONT_MSG - offset;
    6db4:	f1c4 051c 	rsb	r5, r4, #28
		cpy_len = req_len > chunk_len ? chunk_len : req_len;
    6db8:	42bd      	cmp	r5, r7
    6dba:	bf28      	it	cs
    6dbc:	463d      	movcs	r5, r7
		if (put_op) {
    6dbe:	f1b9 0f00 	cmp.w	r9, #0
    6dc2:	d0e9      	beq.n	6d98 <log_msg_hexdump_data_op+0x84>
			(void)memcpy(&cont->payload.bytes[offset],
    6dc4:	1930      	adds	r0, r6, r4
    6dc6:	462a      	mov	r2, r5
    6dc8:	4641      	mov	r1, r8
    6dca:	3004      	adds	r0, #4
    6dcc:	f001 f955 	bl	807a <memcpy>
    6dd0:	e7e8      	b.n	6da4 <log_msg_hexdump_data_op+0x90>

00006dd2 <log_msg_get>:
	atomic_inc(&msg->hdr.ref_cnt);
    6dd2:	3004      	adds	r0, #4
	return __atomic_fetch_add(target, value, __ATOMIC_SEQ_CST);
    6dd4:	f3bf 8f5b 	dmb	ish
    6dd8:	e850 3f00 	ldrex	r3, [r0]
    6ddc:	3301      	adds	r3, #1
    6dde:	e840 3200 	strex	r2, r3, [r0]
    6de2:	2a00      	cmp	r2, #0
    6de4:	d1f8      	bne.n	6dd8 <log_msg_get+0x6>
    6de6:	f3bf 8f5b 	dmb	ish
}
    6dea:	4770      	bx	lr

00006dec <log_msg_nargs_get>:
	return msg->hdr.params.std.nargs;
    6dec:	7a40      	ldrb	r0, [r0, #9]
}
    6dee:	0900      	lsrs	r0, r0, #4
    6df0:	4770      	bx	lr

00006df2 <log_msg_arg_get>:
{
    6df2:	b508      	push	{r3, lr}
	if (arg_idx >= msg->hdr.params.std.nargs) {
    6df4:	7a43      	ldrb	r3, [r0, #9]
    6df6:	ebb1 1f13 	cmp.w	r1, r3, lsr #4
    6dfa:	d20a      	bcs.n	6e12 <log_msg_arg_get+0x20>
    6dfc:	091a      	lsrs	r2, r3, #4
	if (msg->hdr.params.std.nargs <= LOG_MSG_NARGS_SINGLE_CHUNK) {
    6dfe:	2a03      	cmp	r2, #3
    6e00:	d804      	bhi.n	6e0c <log_msg_arg_get+0x1a>
		arg = msg->payload.single.args[arg_idx];
    6e02:	3104      	adds	r1, #4
    6e04:	eb00 0081 	add.w	r0, r0, r1, lsl #2
    6e08:	6840      	ldr	r0, [r0, #4]
    6e0a:	e003      	b.n	6e14 <log_msg_arg_get+0x22>
		arg = cont_arg_get(msg, arg_idx);
    6e0c:	f7ff ff70 	bl	6cf0 <cont_arg_get>
    6e10:	e000      	b.n	6e14 <log_msg_arg_get+0x22>
		return 0;
    6e12:	2000      	movs	r0, #0
}
    6e14:	bd08      	pop	{r3, pc}

00006e16 <log_msg_str_get>:
}
    6e16:	6900      	ldr	r0, [r0, #16]
    6e18:	4770      	bx	lr

00006e1a <log_msg_put>:
{
    6e1a:	b508      	push	{r3, lr}
	atomic_dec(&msg->hdr.ref_cnt);
    6e1c:	1d03      	adds	r3, r0, #4
	return __atomic_fetch_sub(target, value, __ATOMIC_SEQ_CST);
    6e1e:	f3bf 8f5b 	dmb	ish
    6e22:	e853 2f00 	ldrex	r2, [r3]
    6e26:	3a01      	subs	r2, #1
    6e28:	e843 2100 	strex	r1, r2, [r3]
    6e2c:	2900      	cmp	r1, #0
    6e2e:	d1f8      	bne.n	6e22 <log_msg_put+0x8>
    6e30:	f3bf 8f5b 	dmb	ish
	if (msg->hdr.ref_cnt == 0) {
    6e34:	6843      	ldr	r3, [r0, #4]
    6e36:	b103      	cbz	r3, 6e3a <log_msg_put+0x20>
}
    6e38:	bd08      	pop	{r3, pc}
		msg_free(msg);
    6e3a:	f7fa fdcb 	bl	19d4 <msg_free>
}
    6e3e:	e7fb      	b.n	6e38 <log_msg_put+0x1e>

00006e40 <log_msg_hexdump_data_get>:

void log_msg_hexdump_data_get(struct log_msg *msg,
			      uint8_t *data,
			      size_t *length,
			      size_t offset)
{
    6e40:	b510      	push	{r4, lr}
    6e42:	b082      	sub	sp, #8
	log_msg_hexdump_data_op(msg, data, length, offset, false);
    6e44:	2400      	movs	r4, #0
    6e46:	9400      	str	r4, [sp, #0]
    6e48:	f7ff ff64 	bl	6d14 <log_msg_hexdump_data_op>
}
    6e4c:	b002      	add	sp, #8
    6e4e:	bd10      	pop	{r4, pc}

00006e50 <buffer_write>:
{
    6e50:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    6e52:	4607      	mov	r7, r0
    6e54:	460d      	mov	r5, r1
    6e56:	4614      	mov	r4, r2
    6e58:	461e      	mov	r6, r3
		processed = outf(buf, len, ctx);
    6e5a:	4632      	mov	r2, r6
    6e5c:	4621      	mov	r1, r4
    6e5e:	4628      	mov	r0, r5
    6e60:	47b8      	blx	r7
		buf += processed;
    6e62:	4405      	add	r5, r0
	} while (len != 0);
    6e64:	1a24      	subs	r4, r4, r0
    6e66:	d1f8      	bne.n	6e5a <buffer_write+0xa>
}
    6e68:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}

00006e6a <color_prefix>:
{
    6e6a:	b508      	push	{r3, lr}
    6e6c:	4613      	mov	r3, r2
	color_print(output, color, true, level);
    6e6e:	2201      	movs	r2, #1
    6e70:	f7fa fe48 	bl	1b04 <color_print>
}
    6e74:	bd08      	pop	{r3, pc}

00006e76 <color_postfix>:
{
    6e76:	b508      	push	{r3, lr}
    6e78:	4613      	mov	r3, r2
	color_print(output, color, false, level);
    6e7a:	2200      	movs	r2, #0
    6e7c:	f7fa fe42 	bl	1b04 <color_print>
}
    6e80:	bd08      	pop	{r3, pc}

00006e82 <postfix_print>:
{
    6e82:	b538      	push	{r3, r4, r5, lr}
    6e84:	4605      	mov	r5, r0
    6e86:	460c      	mov	r4, r1
	color_postfix(output, (flags & LOG_OUTPUT_FLAG_COLORS),
    6e88:	f001 0101 	and.w	r1, r1, #1
    6e8c:	f7ff fff3 	bl	6e76 <color_postfix>
	newline_print(output, flags);
    6e90:	4621      	mov	r1, r4
    6e92:	4628      	mov	r0, r5
    6e94:	f7fa fe4c 	bl	1b30 <newline_print>
}
    6e98:	bd38      	pop	{r3, r4, r5, pc}

00006e9a <prefix_print>:
{
    6e9a:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
    6e9e:	b083      	sub	sp, #12
    6ea0:	4604      	mov	r4, r0
    6ea2:	4615      	mov	r5, r2
    6ea4:	f89d 6028 	ldrb.w	r6, [sp, #40]	; 0x28
	bool colors_on = flags & LOG_OUTPUT_FLAG_COLORS;
    6ea8:	f001 0901 	and.w	r9, r1, #1
	bool level_on = flags & LOG_OUTPUT_FLAG_LEVEL;
    6eac:	f3c1 08c0 	ubfx	r8, r1, #3, #1
	if (stamp) {
    6eb0:	f011 0702 	ands.w	r7, r1, #2
    6eb4:	d113      	bne.n	6ede <prefix_print+0x44>
		color_prefix(output, colors_on, level);
    6eb6:	4632      	mov	r2, r6
    6eb8:	4649      	mov	r1, r9
    6eba:	4620      	mov	r0, r4
    6ebc:	f7ff ffd5 	bl	6e6a <color_prefix>
	length += ids_print(output, level_on, func_on,
    6ec0:	9601      	str	r6, [sp, #4]
    6ec2:	f9bd 3030 	ldrsh.w	r3, [sp, #48]	; 0x30
    6ec6:	9300      	str	r3, [sp, #0]
    6ec8:	f89d 302c 	ldrb.w	r3, [sp, #44]	; 0x2c
    6ecc:	462a      	mov	r2, r5
    6ece:	4641      	mov	r1, r8
    6ed0:	4620      	mov	r0, r4
    6ed2:	f7fa fea3 	bl	1c1c <ids_print>
}
    6ed6:	4438      	add	r0, r7
    6ed8:	b003      	add	sp, #12
    6eda:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
		length += timestamp_print(output, flags, timestamp);
    6ede:	461a      	mov	r2, r3
    6ee0:	f7fa fdca 	bl	1a78 <timestamp_print>
    6ee4:	4607      	mov	r7, r0
    6ee6:	e7e6      	b.n	6eb6 <prefix_print+0x1c>

00006ee8 <std_print>:
{
    6ee8:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
    6eec:	b08e      	sub	sp, #56	; 0x38
    6eee:	af0e      	add	r7, sp, #56	; 0x38
    6ef0:	4606      	mov	r6, r0
    6ef2:	4689      	mov	r9, r1
	const char *str = log_msg_str_get(msg);
    6ef4:	f7ff ff8f 	bl	6e16 <log_msg_str_get>
    6ef8:	4682      	mov	sl, r0
	uint32_t nargs = log_msg_nargs_get(msg);
    6efa:	4630      	mov	r0, r6
    6efc:	f7ff ff76 	bl	6dec <log_msg_nargs_get>
    6f00:	4680      	mov	r8, r0
	log_arg_t *args = alloca(sizeof(log_arg_t)*nargs);
    6f02:	0083      	lsls	r3, r0, #2
    6f04:	3307      	adds	r3, #7
    6f06:	f023 0307 	bic.w	r3, r3, #7
    6f0a:	ebad 0d03 	sub.w	sp, sp, r3
    6f0e:	ad0e      	add	r5, sp, #56	; 0x38
	for (i = 0; i < nargs; i++) {
    6f10:	2400      	movs	r4, #0
    6f12:	4544      	cmp	r4, r8
    6f14:	d207      	bcs.n	6f26 <std_print+0x3e>
		args[i] = log_msg_arg_get(msg, i);
    6f16:	4621      	mov	r1, r4
    6f18:	4630      	mov	r0, r6
    6f1a:	f7ff ff6a 	bl	6df2 <log_msg_arg_get>
    6f1e:	f845 0024 	str.w	r0, [r5, r4, lsl #2]
	for (i = 0; i < nargs; i++) {
    6f22:	3401      	adds	r4, #1
    6f24:	e7f5      	b.n	6f12 <std_print+0x2a>
	switch (log_msg_nargs_get(msg)) {
    6f26:	4630      	mov	r0, r6
    6f28:	f7ff ff60 	bl	6dec <log_msg_nargs_get>
    6f2c:	280f      	cmp	r0, #15
    6f2e:	d815      	bhi.n	6f5c <std_print+0x74>
    6f30:	e8df f010 	tbh	[pc, r0, lsl #1]
    6f34:	00170010 	.word	0x00170010
    6f38:	0024001d 	.word	0x0024001d
    6f3c:	0038002d 	.word	0x0038002d
    6f40:	00540045 	.word	0x00540045
    6f44:	00780065 	.word	0x00780065
    6f48:	00a4008d 	.word	0x00a4008d
    6f4c:	00d800bd 	.word	0x00d800bd
    6f50:	011400f5 	.word	0x011400f5
		print_formatted(output, str);
    6f54:	4651      	mov	r1, sl
    6f56:	4648      	mov	r0, r9
    6f58:	f7fa fd7c 	bl	1a54 <print_formatted>
}
    6f5c:	46bd      	mov	sp, r7
    6f5e:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
		print_formatted(output, str, args[0]);
    6f62:	682a      	ldr	r2, [r5, #0]
    6f64:	4651      	mov	r1, sl
    6f66:	4648      	mov	r0, r9
    6f68:	f7fa fd74 	bl	1a54 <print_formatted>
		break;
    6f6c:	e7f6      	b.n	6f5c <std_print+0x74>
		print_formatted(output, str, args[0], args[1]);
    6f6e:	686b      	ldr	r3, [r5, #4]
    6f70:	682a      	ldr	r2, [r5, #0]
    6f72:	4651      	mov	r1, sl
    6f74:	4648      	mov	r0, r9
    6f76:	f7fa fd6d 	bl	1a54 <print_formatted>
		break;
    6f7a:	e7ef      	b.n	6f5c <std_print+0x74>
		print_formatted(output, str, args[0], args[1], args[2]);
    6f7c:	686b      	ldr	r3, [r5, #4]
    6f7e:	682a      	ldr	r2, [r5, #0]
    6f80:	68a9      	ldr	r1, [r5, #8]
    6f82:	9100      	str	r1, [sp, #0]
    6f84:	4651      	mov	r1, sl
    6f86:	4648      	mov	r0, r9
    6f88:	f7fa fd64 	bl	1a54 <print_formatted>
		break;
    6f8c:	e7e6      	b.n	6f5c <std_print+0x74>
		print_formatted(output, str, args[0], args[1], args[2],
    6f8e:	686b      	ldr	r3, [r5, #4]
    6f90:	682a      	ldr	r2, [r5, #0]
    6f92:	68e9      	ldr	r1, [r5, #12]
    6f94:	9101      	str	r1, [sp, #4]
    6f96:	68a9      	ldr	r1, [r5, #8]
    6f98:	9100      	str	r1, [sp, #0]
    6f9a:	4651      	mov	r1, sl
    6f9c:	4648      	mov	r0, r9
    6f9e:	f7fa fd59 	bl	1a54 <print_formatted>
		break;
    6fa2:	e7db      	b.n	6f5c <std_print+0x74>
		print_formatted(output, str, args[0], args[1], args[2],
    6fa4:	686b      	ldr	r3, [r5, #4]
    6fa6:	682a      	ldr	r2, [r5, #0]
    6fa8:	6929      	ldr	r1, [r5, #16]
    6faa:	9102      	str	r1, [sp, #8]
    6fac:	68e9      	ldr	r1, [r5, #12]
    6fae:	9101      	str	r1, [sp, #4]
    6fb0:	68a9      	ldr	r1, [r5, #8]
    6fb2:	9100      	str	r1, [sp, #0]
    6fb4:	4651      	mov	r1, sl
    6fb6:	4648      	mov	r0, r9
    6fb8:	f7fa fd4c 	bl	1a54 <print_formatted>
		break;
    6fbc:	e7ce      	b.n	6f5c <std_print+0x74>
		print_formatted(output, str, args[0], args[1], args[2],
    6fbe:	686b      	ldr	r3, [r5, #4]
    6fc0:	682a      	ldr	r2, [r5, #0]
    6fc2:	6969      	ldr	r1, [r5, #20]
    6fc4:	9103      	str	r1, [sp, #12]
    6fc6:	6929      	ldr	r1, [r5, #16]
    6fc8:	9102      	str	r1, [sp, #8]
    6fca:	68e9      	ldr	r1, [r5, #12]
    6fcc:	9101      	str	r1, [sp, #4]
    6fce:	68a9      	ldr	r1, [r5, #8]
    6fd0:	9100      	str	r1, [sp, #0]
    6fd2:	4651      	mov	r1, sl
    6fd4:	4648      	mov	r0, r9
    6fd6:	f7fa fd3d 	bl	1a54 <print_formatted>
		break;
    6fda:	e7bf      	b.n	6f5c <std_print+0x74>
		print_formatted(output, str, args[0], args[1], args[2],
    6fdc:	686b      	ldr	r3, [r5, #4]
    6fde:	682a      	ldr	r2, [r5, #0]
    6fe0:	69a9      	ldr	r1, [r5, #24]
    6fe2:	9104      	str	r1, [sp, #16]
    6fe4:	6969      	ldr	r1, [r5, #20]
    6fe6:	9103      	str	r1, [sp, #12]
    6fe8:	6929      	ldr	r1, [r5, #16]
    6fea:	9102      	str	r1, [sp, #8]
    6fec:	68e9      	ldr	r1, [r5, #12]
    6fee:	9101      	str	r1, [sp, #4]
    6ff0:	68a9      	ldr	r1, [r5, #8]
    6ff2:	9100      	str	r1, [sp, #0]
    6ff4:	4651      	mov	r1, sl
    6ff6:	4648      	mov	r0, r9
    6ff8:	f7fa fd2c 	bl	1a54 <print_formatted>
		break;
    6ffc:	e7ae      	b.n	6f5c <std_print+0x74>
		print_formatted(output, str, args[0], args[1], args[2],
    6ffe:	686b      	ldr	r3, [r5, #4]
    7000:	682a      	ldr	r2, [r5, #0]
    7002:	69e9      	ldr	r1, [r5, #28]
    7004:	9105      	str	r1, [sp, #20]
    7006:	69a9      	ldr	r1, [r5, #24]
    7008:	9104      	str	r1, [sp, #16]
    700a:	6969      	ldr	r1, [r5, #20]
    700c:	9103      	str	r1, [sp, #12]
    700e:	6929      	ldr	r1, [r5, #16]
    7010:	9102      	str	r1, [sp, #8]
    7012:	68e9      	ldr	r1, [r5, #12]
    7014:	9101      	str	r1, [sp, #4]
    7016:	68a9      	ldr	r1, [r5, #8]
    7018:	9100      	str	r1, [sp, #0]
    701a:	4651      	mov	r1, sl
    701c:	4648      	mov	r0, r9
    701e:	f7fa fd19 	bl	1a54 <print_formatted>
		break;
    7022:	e79b      	b.n	6f5c <std_print+0x74>
		print_formatted(output, str, args[0], args[1], args[2],
    7024:	686b      	ldr	r3, [r5, #4]
    7026:	682a      	ldr	r2, [r5, #0]
    7028:	6a29      	ldr	r1, [r5, #32]
    702a:	9106      	str	r1, [sp, #24]
    702c:	69e9      	ldr	r1, [r5, #28]
    702e:	9105      	str	r1, [sp, #20]
    7030:	69a9      	ldr	r1, [r5, #24]
    7032:	9104      	str	r1, [sp, #16]
    7034:	6969      	ldr	r1, [r5, #20]
    7036:	9103      	str	r1, [sp, #12]
    7038:	6929      	ldr	r1, [r5, #16]
    703a:	9102      	str	r1, [sp, #8]
    703c:	68e9      	ldr	r1, [r5, #12]
    703e:	9101      	str	r1, [sp, #4]
    7040:	68a9      	ldr	r1, [r5, #8]
    7042:	9100      	str	r1, [sp, #0]
    7044:	4651      	mov	r1, sl
    7046:	4648      	mov	r0, r9
    7048:	f7fa fd04 	bl	1a54 <print_formatted>
		break;
    704c:	e786      	b.n	6f5c <std_print+0x74>
		print_formatted(output, str, args[0], args[1], args[2],
    704e:	686b      	ldr	r3, [r5, #4]
    7050:	682a      	ldr	r2, [r5, #0]
    7052:	6a69      	ldr	r1, [r5, #36]	; 0x24
    7054:	9107      	str	r1, [sp, #28]
    7056:	6a29      	ldr	r1, [r5, #32]
    7058:	9106      	str	r1, [sp, #24]
    705a:	69e9      	ldr	r1, [r5, #28]
    705c:	9105      	str	r1, [sp, #20]
    705e:	69a9      	ldr	r1, [r5, #24]
    7060:	9104      	str	r1, [sp, #16]
    7062:	6969      	ldr	r1, [r5, #20]
    7064:	9103      	str	r1, [sp, #12]
    7066:	6929      	ldr	r1, [r5, #16]
    7068:	9102      	str	r1, [sp, #8]
    706a:	68e9      	ldr	r1, [r5, #12]
    706c:	9101      	str	r1, [sp, #4]
    706e:	68a9      	ldr	r1, [r5, #8]
    7070:	9100      	str	r1, [sp, #0]
    7072:	4651      	mov	r1, sl
    7074:	4648      	mov	r0, r9
    7076:	f7fa fced 	bl	1a54 <print_formatted>
		break;
    707a:	e76f      	b.n	6f5c <std_print+0x74>
		print_formatted(output, str, args[0], args[1], args[2],
    707c:	686b      	ldr	r3, [r5, #4]
    707e:	682a      	ldr	r2, [r5, #0]
    7080:	6aa9      	ldr	r1, [r5, #40]	; 0x28
    7082:	9108      	str	r1, [sp, #32]
    7084:	6a69      	ldr	r1, [r5, #36]	; 0x24
    7086:	9107      	str	r1, [sp, #28]
    7088:	6a29      	ldr	r1, [r5, #32]
    708a:	9106      	str	r1, [sp, #24]
    708c:	69e9      	ldr	r1, [r5, #28]
    708e:	9105      	str	r1, [sp, #20]
    7090:	69a9      	ldr	r1, [r5, #24]
    7092:	9104      	str	r1, [sp, #16]
    7094:	6969      	ldr	r1, [r5, #20]
    7096:	9103      	str	r1, [sp, #12]
    7098:	6929      	ldr	r1, [r5, #16]
    709a:	9102      	str	r1, [sp, #8]
    709c:	68e9      	ldr	r1, [r5, #12]
    709e:	9101      	str	r1, [sp, #4]
    70a0:	68a9      	ldr	r1, [r5, #8]
    70a2:	9100      	str	r1, [sp, #0]
    70a4:	4651      	mov	r1, sl
    70a6:	4648      	mov	r0, r9
    70a8:	f7fa fcd4 	bl	1a54 <print_formatted>
		break;
    70ac:	e756      	b.n	6f5c <std_print+0x74>
		print_formatted(output, str, args[0], args[1], args[2],
    70ae:	686b      	ldr	r3, [r5, #4]
    70b0:	682a      	ldr	r2, [r5, #0]
    70b2:	6ae9      	ldr	r1, [r5, #44]	; 0x2c
    70b4:	9109      	str	r1, [sp, #36]	; 0x24
    70b6:	6aa9      	ldr	r1, [r5, #40]	; 0x28
    70b8:	9108      	str	r1, [sp, #32]
    70ba:	6a69      	ldr	r1, [r5, #36]	; 0x24
    70bc:	9107      	str	r1, [sp, #28]
    70be:	6a29      	ldr	r1, [r5, #32]
    70c0:	9106      	str	r1, [sp, #24]
    70c2:	69e9      	ldr	r1, [r5, #28]
    70c4:	9105      	str	r1, [sp, #20]
    70c6:	69a9      	ldr	r1, [r5, #24]
    70c8:	9104      	str	r1, [sp, #16]
    70ca:	6969      	ldr	r1, [r5, #20]
    70cc:	9103      	str	r1, [sp, #12]
    70ce:	6929      	ldr	r1, [r5, #16]
    70d0:	9102      	str	r1, [sp, #8]
    70d2:	68e9      	ldr	r1, [r5, #12]
    70d4:	9101      	str	r1, [sp, #4]
    70d6:	68a9      	ldr	r1, [r5, #8]
    70d8:	9100      	str	r1, [sp, #0]
    70da:	4651      	mov	r1, sl
    70dc:	4648      	mov	r0, r9
    70de:	f7fa fcb9 	bl	1a54 <print_formatted>
		break;
    70e2:	e73b      	b.n	6f5c <std_print+0x74>
		print_formatted(output, str, args[0], args[1], args[2],
    70e4:	686b      	ldr	r3, [r5, #4]
    70e6:	682a      	ldr	r2, [r5, #0]
    70e8:	6b29      	ldr	r1, [r5, #48]	; 0x30
    70ea:	910a      	str	r1, [sp, #40]	; 0x28
    70ec:	6ae9      	ldr	r1, [r5, #44]	; 0x2c
    70ee:	9109      	str	r1, [sp, #36]	; 0x24
    70f0:	6aa9      	ldr	r1, [r5, #40]	; 0x28
    70f2:	9108      	str	r1, [sp, #32]
    70f4:	6a69      	ldr	r1, [r5, #36]	; 0x24
    70f6:	9107      	str	r1, [sp, #28]
    70f8:	6a29      	ldr	r1, [r5, #32]
    70fa:	9106      	str	r1, [sp, #24]
    70fc:	69e9      	ldr	r1, [r5, #28]
    70fe:	9105      	str	r1, [sp, #20]
    7100:	69a9      	ldr	r1, [r5, #24]
    7102:	9104      	str	r1, [sp, #16]
    7104:	6969      	ldr	r1, [r5, #20]
    7106:	9103      	str	r1, [sp, #12]
    7108:	6929      	ldr	r1, [r5, #16]
    710a:	9102      	str	r1, [sp, #8]
    710c:	68e9      	ldr	r1, [r5, #12]
    710e:	9101      	str	r1, [sp, #4]
    7110:	68a9      	ldr	r1, [r5, #8]
    7112:	9100      	str	r1, [sp, #0]
    7114:	4651      	mov	r1, sl
    7116:	4648      	mov	r0, r9
    7118:	f7fa fc9c 	bl	1a54 <print_formatted>
		break;
    711c:	e71e      	b.n	6f5c <std_print+0x74>
		print_formatted(output, str, args[0], args[1], args[2],
    711e:	686b      	ldr	r3, [r5, #4]
    7120:	682a      	ldr	r2, [r5, #0]
    7122:	6b69      	ldr	r1, [r5, #52]	; 0x34
    7124:	910b      	str	r1, [sp, #44]	; 0x2c
    7126:	6b29      	ldr	r1, [r5, #48]	; 0x30
    7128:	910a      	str	r1, [sp, #40]	; 0x28
    712a:	6ae9      	ldr	r1, [r5, #44]	; 0x2c
    712c:	9109      	str	r1, [sp, #36]	; 0x24
    712e:	6aa9      	ldr	r1, [r5, #40]	; 0x28
    7130:	9108      	str	r1, [sp, #32]
    7132:	6a69      	ldr	r1, [r5, #36]	; 0x24
    7134:	9107      	str	r1, [sp, #28]
    7136:	6a29      	ldr	r1, [r5, #32]
    7138:	9106      	str	r1, [sp, #24]
    713a:	69e9      	ldr	r1, [r5, #28]
    713c:	9105      	str	r1, [sp, #20]
    713e:	69a9      	ldr	r1, [r5, #24]
    7140:	9104      	str	r1, [sp, #16]
    7142:	6969      	ldr	r1, [r5, #20]
    7144:	9103      	str	r1, [sp, #12]
    7146:	6929      	ldr	r1, [r5, #16]
    7148:	9102      	str	r1, [sp, #8]
    714a:	68e9      	ldr	r1, [r5, #12]
    714c:	9101      	str	r1, [sp, #4]
    714e:	68a9      	ldr	r1, [r5, #8]
    7150:	9100      	str	r1, [sp, #0]
    7152:	4651      	mov	r1, sl
    7154:	4648      	mov	r0, r9
    7156:	f7fa fc7d 	bl	1a54 <print_formatted>
		break;
    715a:	e6ff      	b.n	6f5c <std_print+0x74>
		print_formatted(output, str, args[0], args[1], args[2],
    715c:	686b      	ldr	r3, [r5, #4]
    715e:	682a      	ldr	r2, [r5, #0]
    7160:	6ba9      	ldr	r1, [r5, #56]	; 0x38
    7162:	910c      	str	r1, [sp, #48]	; 0x30
    7164:	6b69      	ldr	r1, [r5, #52]	; 0x34
    7166:	910b      	str	r1, [sp, #44]	; 0x2c
    7168:	6b29      	ldr	r1, [r5, #48]	; 0x30
    716a:	910a      	str	r1, [sp, #40]	; 0x28
    716c:	6ae9      	ldr	r1, [r5, #44]	; 0x2c
    716e:	9109      	str	r1, [sp, #36]	; 0x24
    7170:	6aa9      	ldr	r1, [r5, #40]	; 0x28
    7172:	9108      	str	r1, [sp, #32]
    7174:	6a69      	ldr	r1, [r5, #36]	; 0x24
    7176:	9107      	str	r1, [sp, #28]
    7178:	6a29      	ldr	r1, [r5, #32]
    717a:	9106      	str	r1, [sp, #24]
    717c:	69e9      	ldr	r1, [r5, #28]
    717e:	9105      	str	r1, [sp, #20]
    7180:	69a9      	ldr	r1, [r5, #24]
    7182:	9104      	str	r1, [sp, #16]
    7184:	6969      	ldr	r1, [r5, #20]
    7186:	9103      	str	r1, [sp, #12]
    7188:	6929      	ldr	r1, [r5, #16]
    718a:	9102      	str	r1, [sp, #8]
    718c:	68e9      	ldr	r1, [r5, #12]
    718e:	9101      	str	r1, [sp, #4]
    7190:	68a9      	ldr	r1, [r5, #8]
    7192:	9100      	str	r1, [sp, #0]
    7194:	4651      	mov	r1, sl
    7196:	4648      	mov	r0, r9
    7198:	f7fa fc5c 	bl	1a54 <print_formatted>
}
    719c:	e6de      	b.n	6f5c <std_print+0x74>

0000719e <log_output_flush>:
{
    719e:	b510      	push	{r4, lr}
    71a0:	4604      	mov	r4, r0
		     output->control_block->offset,
    71a2:	6842      	ldr	r2, [r0, #4]
	buffer_write(output->func, output->buf,
    71a4:	6853      	ldr	r3, [r2, #4]
    71a6:	6812      	ldr	r2, [r2, #0]
    71a8:	6881      	ldr	r1, [r0, #8]
    71aa:	6800      	ldr	r0, [r0, #0]
    71ac:	f7ff fe50 	bl	6e50 <buffer_write>
	output->control_block->offset = 0;
    71b0:	6863      	ldr	r3, [r4, #4]
    71b2:	2200      	movs	r2, #0
    71b4:	601a      	str	r2, [r3, #0]
}
    71b6:	bd10      	pop	{r4, pc}

000071b8 <out_func>:
{
    71b8:	b538      	push	{r3, r4, r5, lr}
    71ba:	4605      	mov	r5, r0
    71bc:	460c      	mov	r4, r1
	if (out_ctx->control_block->offset == out_ctx->size) {
    71be:	684b      	ldr	r3, [r1, #4]
    71c0:	681a      	ldr	r2, [r3, #0]
    71c2:	68cb      	ldr	r3, [r1, #12]
    71c4:	429a      	cmp	r2, r3
    71c6:	d00f      	beq.n	71e8 <out_func+0x30>
	idx = atomic_inc(&out_ctx->control_block->offset);
    71c8:	6863      	ldr	r3, [r4, #4]
	return __atomic_fetch_add(target, value, __ATOMIC_SEQ_CST);
    71ca:	f3bf 8f5b 	dmb	ish
    71ce:	e853 2f00 	ldrex	r2, [r3]
    71d2:	1c51      	adds	r1, r2, #1
    71d4:	e843 1000 	strex	r0, r1, [r3]
    71d8:	2800      	cmp	r0, #0
    71da:	d1f8      	bne.n	71ce <out_func+0x16>
    71dc:	f3bf 8f5b 	dmb	ish
	out_ctx->buf[idx] = (uint8_t)c;
    71e0:	68a3      	ldr	r3, [r4, #8]
    71e2:	549d      	strb	r5, [r3, r2]
}
    71e4:	2000      	movs	r0, #0
    71e6:	bd38      	pop	{r3, r4, r5, pc}
		log_output_flush(out_ctx);
    71e8:	4608      	mov	r0, r1
    71ea:	f7ff ffd8 	bl	719e <log_output_flush>
    71ee:	e7eb      	b.n	71c8 <out_func+0x10>

000071f0 <log_output_msg_process>:
{
    71f0:	b5f0      	push	{r4, r5, r6, r7, lr}
    71f2:	b085      	sub	sp, #20
    71f4:	4606      	mov	r6, r0
    71f6:	460c      	mov	r4, r1
    71f8:	4617      	mov	r7, r2
    71fa:	7a0b      	ldrb	r3, [r1, #8]
    71fc:	f083 0301 	eor.w	r3, r3, #1
    7200:	f003 0201 	and.w	r2, r3, #1
	return msg->hdr.timestamp;
    7204:	68cb      	ldr	r3, [r1, #12]
	return msg->hdr.ids.level;
    7206:	7a89      	ldrb	r1, [r1, #10]
	return msg->hdr.ids.domain_id;
    7208:	f3c1 0cc2 	ubfx	ip, r1, #3, #3
	return msg->hdr.ids.source_id;
    720c:	8960      	ldrh	r0, [r4, #10]
	int16_t source_id = (int16_t)log_msg_source_id_get(msg);
    720e:	f3c0 1089 	ubfx	r0, r0, #6, #10
			0 : prefix_print(output, flags, std_msg, timestamp,
    7212:	f011 0507 	ands.w	r5, r1, #7
    7216:	d10f      	bne.n	7238 <log_output_msg_process+0x48>
    7218:	2200      	movs	r2, #0
	return  (msg->hdr.params.generic.type == LOG_MSG_TYPE_STD);
    721a:	7a23      	ldrb	r3, [r4, #8]
	if (log_msg_is_std(msg)) {
    721c:	f013 0f01 	tst.w	r3, #1
    7220:	d014      	beq.n	724c <log_output_msg_process+0x5c>
	} else if (raw_string) {
    7222:	b9c5      	cbnz	r5, 7256 <log_output_msg_process+0x66>
		raw_string_print(msg, output);
    7224:	4631      	mov	r1, r6
    7226:	4620      	mov	r0, r4
    7228:	f7fa fd58 	bl	1cdc <raw_string_print>
	if (!raw_string) {
    722c:	b9cd      	cbnz	r5, 7262 <log_output_msg_process+0x72>
	log_output_flush(output);
    722e:	4630      	mov	r0, r6
    7230:	f7ff ffb5 	bl	719e <log_output_flush>
}
    7234:	b005      	add	sp, #20
    7236:	bdf0      	pop	{r4, r5, r6, r7, pc}
			0 : prefix_print(output, flags, std_msg, timestamp,
    7238:	9002      	str	r0, [sp, #8]
    723a:	f8cd c004 	str.w	ip, [sp, #4]
    723e:	9500      	str	r5, [sp, #0]
    7240:	4639      	mov	r1, r7
    7242:	4630      	mov	r0, r6
    7244:	f7ff fe29 	bl	6e9a <prefix_print>
    7248:	4602      	mov	r2, r0
    724a:	e7e6      	b.n	721a <log_output_msg_process+0x2a>
		std_print(msg, output);
    724c:	4631      	mov	r1, r6
    724e:	4620      	mov	r0, r4
    7250:	f7ff fe4a 	bl	6ee8 <std_print>
    7254:	e7ea      	b.n	722c <log_output_msg_process+0x3c>
		hexdump_print(msg, output, prefix_offset, flags);
    7256:	463b      	mov	r3, r7
    7258:	4631      	mov	r1, r6
    725a:	4620      	mov	r0, r4
    725c:	f7fa fd14 	bl	1c88 <hexdump_print>
    7260:	e7e4      	b.n	722c <log_output_msg_process+0x3c>
		postfix_print(output, flags, level);
    7262:	462a      	mov	r2, r5
    7264:	4639      	mov	r1, r7
    7266:	4630      	mov	r0, r6
    7268:	f7ff fe0b 	bl	6e82 <postfix_print>
    726c:	e7df      	b.n	722e <log_output_msg_process+0x3e>

0000726e <z_cpp_init_static>:

void __do_global_ctors_aux(void);
void __do_init_array_aux(void);

void z_cpp_init_static(void)
{
    726e:	b508      	push	{r3, lr}
	__do_global_ctors_aux();
    7270:	f7fa fe8e 	bl	1f90 <__do_global_ctors_aux>
	__do_init_array_aux();
    7274:	f7fa fe7e 	bl	1f74 <__do_init_array_aux>
}
    7278:	bd08      	pop	{r3, pc}

0000727a <pm_policy_next_state>:
			return pm_min_residency[i];
		}
	}

	LOG_DBG("No suitable power state found!");
	return (struct pm_state_info){PM_STATE_ACTIVE, 0, 0};
    727a:	2200      	movs	r2, #0
    727c:	6002      	str	r2, [r0, #0]
    727e:	6042      	str	r2, [r0, #4]
    7280:	6082      	str	r2, [r0, #8]
}
    7282:	4770      	bx	lr

00007284 <z_arm_fatal_error>:

void z_arm_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
{
    7284:	b538      	push	{r3, r4, r5, lr}
    7286:	4604      	mov	r4, r0

	if (esf != NULL) {
    7288:	460d      	mov	r5, r1
    728a:	b111      	cbz	r1, 7292 <z_arm_fatal_error+0xe>
		esf_dump(esf);
    728c:	4608      	mov	r0, r1
    728e:	f7fa ff51 	bl	2134 <esf_dump>
	}
	z_fatal_error(reason, esf);
    7292:	4629      	mov	r1, r5
    7294:	4620      	mov	r0, r4
    7296:	f7fd ff71 	bl	517c <z_fatal_error>
}
    729a:	bd38      	pop	{r3, r4, r5, pc}

0000729c <z_do_kernel_oops>:
 *   fault handler will executed insted of the SVC.
 *
 * @param esf exception frame
 */
void z_do_kernel_oops(const z_arch_esf_t *esf)
{
    729c:	b508      	push	{r3, lr}
    729e:	4601      	mov	r1, r0
	}

#endif /* CONFIG_USERSPACE */

#if !defined(CONFIG_EXTRA_EXCEPTION_INFO)
	z_arm_fatal_error(reason, esf);
    72a0:	6800      	ldr	r0, [r0, #0]
    72a2:	f7ff ffef 	bl	7284 <z_arm_fatal_error>

	memcpy(&esf_copy, esf, offsetof(z_arch_esf_t, extra_info));
	esf_copy.extra_info = (struct __extra_esf_info) { 0 };
	z_arm_fatal_error(reason, &esf_copy);
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
}
    72a6:	bd08      	pop	{r3, pc}

000072a8 <z_irq_spurious>:
 * called.
 *
 * @return N/A
 */
void z_irq_spurious(const void *unused)
{
    72a8:	b508      	push	{r3, lr}
	ARG_UNUSED(unused);

	z_arm_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
    72aa:	2100      	movs	r1, #0
    72ac:	2001      	movs	r0, #1
    72ae:	f7ff ffe9 	bl	7284 <z_arm_fatal_error>
}
    72b2:	bd08      	pop	{r3, pc}

000072b4 <z_arm_nmi>:
 *
 * @return N/A
 */

void z_arm_nmi(void)
{
    72b4:	b508      	push	{r3, lr}
	handler();
    72b6:	f7fa ffbf 	bl	2238 <z_SysNmiOnReset>
	z_arm_int_exit();
    72ba:	f7fb f881 	bl	23c0 <z_arm_exc_exit>
}
    72be:	bd08      	pop	{r3, pc}

000072c0 <memory_fault_recoverable>:
}
    72c0:	2000      	movs	r0, #0
    72c2:	4770      	bx	lr

000072c4 <fault_handle>:
{
    72c4:	b508      	push	{r3, lr}
	*recoverable = false;
    72c6:	2300      	movs	r3, #0
    72c8:	7013      	strb	r3, [r2, #0]
	switch (fault) {
    72ca:	1ecb      	subs	r3, r1, #3
    72cc:	2b09      	cmp	r3, #9
    72ce:	d81a      	bhi.n	7306 <fault_handle+0x42>
    72d0:	e8df f003 	tbb	[pc, r3]
    72d4:	110d0905 	.word	0x110d0905
    72d8:	19191919 	.word	0x19191919
    72dc:	1419      	.short	0x1419
		reason = hard_fault(esf, recoverable);
    72de:	4611      	mov	r1, r2
    72e0:	f7fb fae6 	bl	28b0 <hard_fault>
}
    72e4:	bd08      	pop	{r3, pc}
		reason = mem_manage_fault(esf, 0, recoverable);
    72e6:	2100      	movs	r1, #0
    72e8:	f7fb f944 	bl	2574 <mem_manage_fault>
		break;
    72ec:	e7fa      	b.n	72e4 <fault_handle+0x20>
		reason = bus_fault(esf, 0, recoverable);
    72ee:	2100      	movs	r1, #0
    72f0:	f7fb fa06 	bl	2700 <bus_fault>
		break;
    72f4:	e7f6      	b.n	72e4 <fault_handle+0x20>
		reason = usage_fault(esf);
    72f6:	f7fb f871 	bl	23dc <usage_fault>
		break;
    72fa:	e7f3      	b.n	72e4 <fault_handle+0x20>
		debug_monitor(esf, recoverable);
    72fc:	4611      	mov	r1, r2
    72fe:	f7fb f91f 	bl	2540 <debug_monitor>
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    7302:	2000      	movs	r0, #0
		break;
    7304:	e7ee      	b.n	72e4 <fault_handle+0x20>
		reserved_exception(esf, fault);
    7306:	f7fb fb79 	bl	29fc <reserved_exception>
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    730a:	2000      	movs	r0, #0
	return reason;
    730c:	e7ea      	b.n	72e4 <fault_handle+0x20>

0000730e <mpu_partition_is_valid>:
		((part->size & (part->size - 1U)) == 0U)
    730e:	6843      	ldr	r3, [r0, #4]
    7310:	1e5a      	subs	r2, r3, #1
		&&
    7312:	4213      	tst	r3, r2
    7314:	d106      	bne.n	7324 <mpu_partition_is_valid+0x16>
		&&
    7316:	2b1f      	cmp	r3, #31
    7318:	d906      	bls.n	7328 <mpu_partition_is_valid+0x1a>
		((part->start & (part->size - 1U)) == 0U);
    731a:	6803      	ldr	r3, [r0, #0]
		&&
    731c:	421a      	tst	r2, r3
    731e:	d005      	beq.n	732c <mpu_partition_is_valid+0x1e>
    7320:	2000      	movs	r0, #0
    7322:	4770      	bx	lr
    7324:	2000      	movs	r0, #0
    7326:	4770      	bx	lr
    7328:	2000      	movs	r0, #0
    732a:	4770      	bx	lr
    732c:	2001      	movs	r0, #1
}
    732e:	4770      	bx	lr

00007330 <mpu_configure_region>:
{
    7330:	b500      	push	{lr}
    7332:	b085      	sub	sp, #20
	region_conf.base = new_region->start;
    7334:	680b      	ldr	r3, [r1, #0]
    7336:	9301      	str	r3, [sp, #4]
	get_region_attr_from_mpu_partition_info(&region_conf.attr,
    7338:	684b      	ldr	r3, [r1, #4]
	p_attr->rasr = attr->rasr_attr | size_to_mpu_rasr_size(size);
    733a:	688a      	ldr	r2, [r1, #8]
	if (size <= 32U) {
    733c:	2b20      	cmp	r3, #32
    733e:	d912      	bls.n	7366 <mpu_configure_region+0x36>
	if (size > (1UL << 31)) {
    7340:	f1b3 4f00 	cmp.w	r3, #2147483648	; 0x80000000
    7344:	d811      	bhi.n	736a <mpu_configure_region+0x3a>
	return ((32 - __builtin_clz(size - 1U) - 2 + 1) << MPU_RASR_SIZE_Pos) &
    7346:	3b01      	subs	r3, #1
    7348:	fab3 f383 	clz	r3, r3
    734c:	f1c3 031f 	rsb	r3, r3, #31
    7350:	005b      	lsls	r3, r3, #1
    7352:	f003 033e 	and.w	r3, r3, #62	; 0x3e
	p_attr->rasr = attr->rasr_attr | size_to_mpu_rasr_size(size);
    7356:	4313      	orrs	r3, r2
    7358:	9303      	str	r3, [sp, #12]
	return region_allocate_and_init(index,
    735a:	a901      	add	r1, sp, #4
    735c:	f7fb fc9e 	bl	2c9c <region_allocate_and_init>
}
    7360:	b005      	add	sp, #20
    7362:	f85d fb04 	ldr.w	pc, [sp], #4
		return REGION_32B;
    7366:	2308      	movs	r3, #8
    7368:	e7f5      	b.n	7356 <mpu_configure_region+0x26>
		return REGION_4G;
    736a:	233e      	movs	r3, #62	; 0x3e
    736c:	e7f3      	b.n	7356 <mpu_configure_region+0x26>

0000736e <arm_core_mpu_configure_static_mpu_regions>:
{
    736e:	b508      	push	{r3, lr}
	if (mpu_configure_static_mpu_regions(static_regions, regions_num,
    7370:	f7fb fcf6 	bl	2d60 <mpu_configure_static_mpu_regions>
}
    7374:	bd08      	pop	{r3, pc}

00007376 <malloc_prepare>:
}
    7376:	2000      	movs	r0, #0
    7378:	4770      	bx	lr

0000737a <_stdout_hook_default>:
}
    737a:	f04f 30ff 	mov.w	r0, #4294967295
    737e:	4770      	bx	lr

00007380 <pm_power_state_set>:
#include <logging/log.h>
LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);

/* Invoke Low Power/System Off specific Tasks */
__weak void pm_power_state_set(struct pm_state_info info)
{
    7380:	b084      	sub	sp, #16
    7382:	ab04      	add	r3, sp, #16
    7384:	e903 0007 	stmdb	r3, {r0, r1, r2}
	switch (info.state) {
    7388:	f89d 3004 	ldrb.w	r3, [sp, #4]
    738c:	2b06      	cmp	r3, #6
    738e:	d001      	beq.n	7394 <pm_power_state_set+0x14>
		break;
	default:
		LOG_DBG("Unsupported power state %u", info.state);
		break;
	}
}
    7390:	b004      	add	sp, #16
    7392:	4770      	bx	lr
    p_reg->SYSTEMOFF = POWER_SYSTEMOFF_SYSTEMOFF_Enter;
    7394:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    7398:	2201      	movs	r2, #1
    739a:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
  __ASM volatile ("dsb 0xF":::"memory");
    739e:	f3bf 8f4f 	dsb	sy
        __WFE();
    73a2:	bf20      	wfe
    while (true)
    73a4:	e7fd      	b.n	73a2 <pm_power_state_set+0x22>

000073a6 <pm_power_state_exit_post_ops>:

/* Handle SOC specific activity after Low Power Mode Exit */
__weak void pm_power_state_exit_post_ops(struct pm_state_info info)
{
    73a6:	b084      	sub	sp, #16
    73a8:	ab04      	add	r3, sp, #16
    73aa:	e903 0007 	stmdb	r3, {r0, r1, r2}
    73ae:	2300      	movs	r3, #0
    73b0:	f383 8811 	msr	BASEPRI, r3
    73b4:	f3bf 8f6f 	isb	sy
	/*
	 * System is now in active mode. Reenable interrupts which were disabled
	 * when OS started idling code.
	 */
	irq_unlock(0);
}
    73b8:	b004      	add	sp, #16
    73ba:	4770      	bx	lr

000073bc <get_sub_data>:
	struct nrf_clock_control_data *data = dev->data;
    73bc:	6900      	ldr	r0, [r0, #16]
	return &data->subsys[type];
    73be:	eb01 0141 	add.w	r1, r1, r1, lsl #1
    73c2:	0089      	lsls	r1, r1, #2
    73c4:	3140      	adds	r1, #64	; 0x40
}
    73c6:	4408      	add	r0, r1
    73c8:	4770      	bx	lr

000073ca <get_sub_config>:
	const struct nrf_clock_control_config *config =
    73ca:	6840      	ldr	r0, [r0, #4]
	return &config->subsys[type];
    73cc:	eb01 0141 	add.w	r1, r1, r1, lsl #1
}
    73d0:	eb00 0081 	add.w	r0, r0, r1, lsl #2
    73d4:	4770      	bx	lr

000073d6 <get_onoff_manager>:
	struct nrf_clock_control_data *data = dev->data;
    73d6:	6900      	ldr	r0, [r0, #16]
}
    73d8:	eb00 1041 	add.w	r0, r0, r1, lsl #5
    73dc:	4770      	bx	lr

000073de <get_status>:
{
    73de:	b508      	push	{r3, lr}
	return GET_STATUS(get_sub_data(dev, type)->flags);
    73e0:	b2c9      	uxtb	r1, r1
    73e2:	f7ff ffeb 	bl	73bc <get_sub_data>
    73e6:	6880      	ldr	r0, [r0, #8]
}
    73e8:	f000 0007 	and.w	r0, r0, #7
    73ec:	bd08      	pop	{r3, pc}

000073ee <set_off_state>:
	__asm__ volatile(
    73ee:	f04f 0320 	mov.w	r3, #32
    73f2:	f3ef 8211 	mrs	r2, BASEPRI
    73f6:	f383 8812 	msr	BASEPRI_MAX, r3
    73fa:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    73fe:	6803      	ldr	r3, [r0, #0]
	if ((current_ctx != 0) && (current_ctx != ctx)) {
    7400:	f013 03c0 	ands.w	r3, r3, #192	; 0xc0
    7404:	d001      	beq.n	740a <set_off_state+0x1c>
    7406:	428b      	cmp	r3, r1
    7408:	d107      	bne.n	741a <set_off_state+0x2c>
		*flags = CLOCK_CONTROL_STATUS_OFF;
    740a:	2301      	movs	r3, #1
    740c:	6003      	str	r3, [r0, #0]
	int err = 0;
    740e:	2000      	movs	r0, #0
	__asm__ volatile(
    7410:	f382 8811 	msr	BASEPRI, r2
    7414:	f3bf 8f6f 	isb	sy
}
    7418:	4770      	bx	lr
		err = -EPERM;
    741a:	f04f 30ff 	mov.w	r0, #4294967295
    741e:	e7f7      	b.n	7410 <set_off_state+0x22>

00007420 <set_starting_state>:
{
    7420:	b410      	push	{r4}
	__asm__ volatile(
    7422:	f04f 0320 	mov.w	r3, #32
    7426:	f3ef 8211 	mrs	r2, BASEPRI
    742a:	f383 8812 	msr	BASEPRI_MAX, r3
    742e:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    7432:	6803      	ldr	r3, [r0, #0]
    7434:	f003 04c0 	and.w	r4, r3, #192	; 0xc0
	if ((*flags & (STATUS_MASK)) == CLOCK_CONTROL_STATUS_OFF) {
    7438:	f003 0307 	and.w	r3, r3, #7
    743c:	2b01      	cmp	r3, #1
    743e:	d009      	beq.n	7454 <set_starting_state+0x34>
	} else if (current_ctx != ctx) {
    7440:	428c      	cmp	r4, r1
    7442:	d00a      	beq.n	745a <set_starting_state+0x3a>
		err = -EPERM;
    7444:	f04f 30ff 	mov.w	r0, #4294967295
	__asm__ volatile(
    7448:	f382 8811 	msr	BASEPRI, r2
    744c:	f3bf 8f6f 	isb	sy
}
    7450:	bc10      	pop	{r4}
    7452:	4770      	bx	lr
		*flags = CLOCK_CONTROL_STATUS_STARTING | ctx;
    7454:	6001      	str	r1, [r0, #0]
	int err = 0;
    7456:	2000      	movs	r0, #0
    7458:	e7f6      	b.n	7448 <set_starting_state+0x28>
		err = -EALREADY;
    745a:	f06f 0077 	mvn.w	r0, #119	; 0x77
    745e:	e7f3      	b.n	7448 <set_starting_state+0x28>

00007460 <set_on_state>:
	__asm__ volatile(
    7460:	f04f 0320 	mov.w	r3, #32
    7464:	f3ef 8211 	mrs	r2, BASEPRI
    7468:	f383 8812 	msr	BASEPRI_MAX, r3
    746c:	f3bf 8f6f 	isb	sy
	*flags = CLOCK_CONTROL_STATUS_ON | GET_CTX(*flags);
    7470:	6803      	ldr	r3, [r0, #0]
    7472:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
    7476:	f043 0302 	orr.w	r3, r3, #2
    747a:	6003      	str	r3, [r0, #0]
	__asm__ volatile(
    747c:	f382 8811 	msr	BASEPRI, r2
    7480:	f3bf 8f6f 	isb	sy
}
    7484:	4770      	bx	lr

00007486 <clkstarted_handle>:
{
    7486:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    7488:	4606      	mov	r6, r0
    748a:	460c      	mov	r4, r1
	struct nrf_clock_control_sub_data *sub_data = get_sub_data(dev, type);
    748c:	f7ff ff96 	bl	73bc <get_sub_data>
	clock_control_cb_t callback = sub_data->cb;
    7490:	6805      	ldr	r5, [r0, #0]
	void *user_data = sub_data->user_data;
    7492:	6847      	ldr	r7, [r0, #4]
	sub_data->cb = NULL;
    7494:	2300      	movs	r3, #0
    7496:	f840 3b08 	str.w	r3, [r0], #8
	set_on_state(&sub_data->flags);
    749a:	f7ff ffe1 	bl	7460 <set_on_state>
	if (callback) {
    749e:	b11d      	cbz	r5, 74a8 <clkstarted_handle+0x22>
		callback(dev, (clock_control_subsys_t)type, user_data);
    74a0:	463a      	mov	r2, r7
    74a2:	4621      	mov	r1, r4
    74a4:	4630      	mov	r0, r6
    74a6:	47a8      	blx	r5
}
    74a8:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}

000074aa <stop>:
{
    74aa:	b570      	push	{r4, r5, r6, lr}
    74ac:	4606      	mov	r6, r0
    74ae:	4615      	mov	r5, r2
	enum clock_control_nrf_type type = (enum clock_control_nrf_type)subsys;
    74b0:	b2cc      	uxtb	r4, r1
	struct nrf_clock_control_sub_data *subdata = get_sub_data(dev, type);
    74b2:	4621      	mov	r1, r4
    74b4:	f7ff ff82 	bl	73bc <get_sub_data>
	err = set_off_state(&subdata->flags, ctx);
    74b8:	4629      	mov	r1, r5
    74ba:	3008      	adds	r0, #8
    74bc:	f7ff ff97 	bl	73ee <set_off_state>
	if (err < 0) {
    74c0:	2800      	cmp	r0, #0
    74c2:	db06      	blt.n	74d2 <stop+0x28>
	get_sub_config(dev, type)->stop();
    74c4:	4621      	mov	r1, r4
    74c6:	4630      	mov	r0, r6
    74c8:	f7ff ff7f 	bl	73ca <get_sub_config>
    74cc:	6843      	ldr	r3, [r0, #4]
    74ce:	4798      	blx	r3
	return 0;
    74d0:	2000      	movs	r0, #0
}
    74d2:	bd70      	pop	{r4, r5, r6, pc}

000074d4 <api_stop>:
{
    74d4:	b508      	push	{r3, lr}
	return stop(dev, subsys, CTX_API);
    74d6:	2280      	movs	r2, #128	; 0x80
    74d8:	f7ff ffe7 	bl	74aa <stop>
}
    74dc:	bd08      	pop	{r3, pc}

000074de <async_start>:
{
    74de:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    74e2:	4606      	mov	r6, r0
    74e4:	4690      	mov	r8, r2
    74e6:	461f      	mov	r7, r3
	enum clock_control_nrf_type type = (enum clock_control_nrf_type)subsys;
    74e8:	b2cd      	uxtb	r5, r1
	struct nrf_clock_control_sub_data *subdata = get_sub_data(dev, type);
    74ea:	4629      	mov	r1, r5
    74ec:	f7ff ff66 	bl	73bc <get_sub_data>
    74f0:	4604      	mov	r4, r0
	err = set_starting_state(&subdata->flags, ctx);
    74f2:	9906      	ldr	r1, [sp, #24]
    74f4:	3008      	adds	r0, #8
    74f6:	f7ff ff93 	bl	7420 <set_starting_state>
	if (err < 0) {
    74fa:	2800      	cmp	r0, #0
    74fc:	db09      	blt.n	7512 <async_start+0x34>
	subdata->cb = cb;
    74fe:	f8c4 8000 	str.w	r8, [r4]
	subdata->user_data = user_data;
    7502:	6067      	str	r7, [r4, #4]
	 get_sub_config(dev, type)->start();
    7504:	4629      	mov	r1, r5
    7506:	4630      	mov	r0, r6
    7508:	f7ff ff5f 	bl	73ca <get_sub_config>
    750c:	6803      	ldr	r3, [r0, #0]
    750e:	4798      	blx	r3
	return 0;
    7510:	2000      	movs	r0, #0
}
    7512:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00007516 <api_start>:
{
    7516:	b510      	push	{r4, lr}
    7518:	b082      	sub	sp, #8
	return async_start(dev, subsys, cb, user_data, CTX_API);
    751a:	2480      	movs	r4, #128	; 0x80
    751c:	9400      	str	r4, [sp, #0]
    751e:	f7ff ffde 	bl	74de <async_start>
}
    7522:	b002      	add	sp, #8
    7524:	bd10      	pop	{r4, pc}

00007526 <onoff_started_callback>:
{
    7526:	b510      	push	{r4, lr}
    7528:	4614      	mov	r4, r2
	struct onoff_manager *mgr = get_onoff_manager(dev, type);
    752a:	b2c9      	uxtb	r1, r1
    752c:	f7ff ff53 	bl	73d6 <get_onoff_manager>
	notify(mgr, 0);
    7530:	2100      	movs	r1, #0
    7532:	47a0      	blx	r4
}
    7534:	bd10      	pop	{r4, pc}

00007536 <hfclk_start>:
{
    7536:	b508      	push	{r3, lr}
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_start(void)
{
    nrfx_clock_start(NRF_CLOCK_DOMAIN_HFCLK);
    7538:	2001      	movs	r0, #1
    753a:	f7fd f8fb 	bl	4734 <nrfx_clock_start>
}
    753e:	bd08      	pop	{r3, pc}

00007540 <lfclk_start>:
{
    7540:	b508      	push	{r3, lr}
    nrfx_clock_start(NRF_CLOCK_DOMAIN_LFCLK);
    7542:	2000      	movs	r0, #0
    7544:	f7fd f8f6 	bl	4734 <nrfx_clock_start>
}
    7548:	bd08      	pop	{r3, pc}

0000754a <hfclk_stop>:
{
    754a:	b508      	push	{r3, lr}
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_stop(void)
{
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLK);
    754c:	2001      	movs	r0, #1
    754e:	f7fd f911 	bl	4774 <nrfx_clock_stop>
}
    7552:	bd08      	pop	{r3, pc}

00007554 <blocking_start_callback>:
{
    7554:	b508      	push	{r3, lr}
    7556:	4610      	mov	r0, r2
	z_impl_k_sem_give(sem);
    7558:	f7fe f98e 	bl	5878 <z_impl_k_sem_give>
}
    755c:	bd08      	pop	{r3, pc}

0000755e <lfclk_stop>:
{
    755e:	b508      	push	{r3, lr}
		z_nrf_clock_calibration_lfclk_stopped();
    7560:	f7fb fecc 	bl	32fc <z_nrf_clock_calibration_lfclk_stopped>
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
    7564:	2000      	movs	r0, #0
    7566:	f7fd f905 	bl	4774 <nrfx_clock_stop>
}
    756a:	bd08      	pop	{r3, pc}

0000756c <clk_release>:
{
    756c:	b508      	push	{r3, lr}
	err = onoff_release(mgr);
    756e:	f7ff fb54 	bl	6c1a <onoff_release>
}
    7572:	bd08      	pop	{r3, pc}

00007574 <clk_request>:
{
    7574:	b538      	push	{r3, r4, r5, lr}
	*notify = (struct sys_notify){
    7576:	2500      	movs	r5, #0
    7578:	60cd      	str	r5, [r1, #12]
    757a:	604a      	str	r2, [r1, #4]
    757c:	2203      	movs	r2, #3
    757e:	608a      	str	r2, [r1, #8]
	err = onoff_request(mgr, cli);
    7580:	f7ff faef 	bl	6b62 <onoff_request>
}
    7584:	bd38      	pop	{r3, r4, r5, pc}

00007586 <timeout_handler>:
{
    7586:	b508      	push	{r3, lr}
	start_cal_process();
    7588:	f7fb fe7e 	bl	3288 <start_cal_process>
}
    758c:	bd08      	pop	{r3, pc}

0000758e <z_nrf_clock_calibration_lfclk_started>:
{
    758e:	b508      	push	{r3, lr}
	start_unconditional_cal_process();
    7590:	f7fb fe90 	bl	32b4 <start_unconditional_cal_process>
}
    7594:	bd08      	pop	{r3, pc}

00007596 <gpio_nrfx_port_get_raw>:
	return port->config;
    7596:	6843      	ldr	r3, [r0, #4]
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    7598:	685b      	ldr	r3, [r3, #4]
    return p_reg->IN;
    759a:	f8d3 3510 	ldr.w	r3, [r3, #1296]	; 0x510
	*value = nrf_gpio_port_in_read(reg);
    759e:	600b      	str	r3, [r1, #0]
}
    75a0:	2000      	movs	r0, #0
    75a2:	4770      	bx	lr

000075a4 <gpio_nrfx_port_set_masked_raw>:
	return port->config;
    75a4:	6843      	ldr	r3, [r0, #4]
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    75a6:	685b      	ldr	r3, [r3, #4]
    return p_reg->OUT;
    75a8:	f8d3 0504 	ldr.w	r0, [r3, #1284]	; 0x504
	nrf_gpio_port_out_write(reg, value_tmp | (mask & value));
    75ac:	4042      	eors	r2, r0
    75ae:	400a      	ands	r2, r1
    75b0:	4042      	eors	r2, r0
    p_reg->OUT = value;
    75b2:	f8c3 2504 	str.w	r2, [r3, #1284]	; 0x504
}
    75b6:	2000      	movs	r0, #0
    75b8:	4770      	bx	lr

000075ba <gpio_nrfx_port_set_bits_raw>:
	return port->config;
    75ba:	6843      	ldr	r3, [r0, #4]
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    75bc:	685b      	ldr	r3, [r3, #4]
    p_reg->OUTSET = set_mask;
    75be:	f8c3 1508 	str.w	r1, [r3, #1288]	; 0x508
}
    75c2:	2000      	movs	r0, #0
    75c4:	4770      	bx	lr

000075c6 <gpio_nrfx_port_clear_bits_raw>:
	return port->config;
    75c6:	6843      	ldr	r3, [r0, #4]
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    75c8:	685b      	ldr	r3, [r3, #4]
    p_reg->OUTCLR = clr_mask;
    75ca:	f8c3 150c 	str.w	r1, [r3, #1292]	; 0x50c
}
    75ce:	2000      	movs	r0, #0
    75d0:	4770      	bx	lr

000075d2 <gpio_nrfx_port_toggle_bits>:
	return port->config;
    75d2:	6843      	ldr	r3, [r0, #4]
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    75d4:	685a      	ldr	r2, [r3, #4]
    return p_reg->OUT;
    75d6:	f8d2 3504 	ldr.w	r3, [r2, #1284]	; 0x504
	nrf_gpio_port_out_write(reg, value ^ mask);
    75da:	404b      	eors	r3, r1
    p_reg->OUT = value;
    75dc:	f8c2 3504 	str.w	r3, [r2, #1284]	; 0x504
}
    75e0:	2000      	movs	r0, #0
    75e2:	4770      	bx	lr

000075e4 <gpio_nrfx_manage_callback>:
{
    75e4:	b470      	push	{r4, r5, r6}
	return port->data;
    75e6:	6900      	ldr	r0, [r0, #16]
	return gpio_manage_callback(&get_port_data(port)->callbacks,
    75e8:	1d05      	adds	r5, r0, #4
	return list->head;
    75ea:	6843      	ldr	r3, [r0, #4]
	if (!sys_slist_is_empty(callbacks)) {
    75ec:	b1db      	cbz	r3, 7626 <gpio_nrfx_manage_callback+0x42>
		if (!sys_slist_find_and_remove(callbacks, &callback->node)) {
    75ee:	460e      	mov	r6, r1
 */
static inline bool sys_slist_find_and_remove(sys_slist_t *list,
					     sys_snode_t *node);

/** @} */
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    75f0:	2400      	movs	r4, #0
    75f2:	e00a      	b.n	760a <gpio_nrfx_manage_callback+0x26>
	return node->next;
    75f4:	680b      	ldr	r3, [r1, #0]
	list->head = node;
    75f6:	6043      	str	r3, [r0, #4]
	return list->tail;
    75f8:	686c      	ldr	r4, [r5, #4]
Z_GENLIST_REMOVE(slist, snode)
    75fa:	42a1      	cmp	r1, r4
    75fc:	d10f      	bne.n	761e <gpio_nrfx_manage_callback+0x3a>
	list->tail = node;
    75fe:	606b      	str	r3, [r5, #4]
}
    7600:	e00d      	b.n	761e <gpio_nrfx_manage_callback+0x3a>
	list->tail = node;
    7602:	606c      	str	r4, [r5, #4]
}
    7604:	e00b      	b.n	761e <gpio_nrfx_manage_callback+0x3a>
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    7606:	461c      	mov	r4, r3
    7608:	681b      	ldr	r3, [r3, #0]
    760a:	b15b      	cbz	r3, 7624 <gpio_nrfx_manage_callback+0x40>
    760c:	429e      	cmp	r6, r3
    760e:	d1fa      	bne.n	7606 <gpio_nrfx_manage_callback+0x22>
Z_GENLIST_REMOVE(slist, snode)
    7610:	2c00      	cmp	r4, #0
    7612:	d0ef      	beq.n	75f4 <gpio_nrfx_manage_callback+0x10>
	return node->next;
    7614:	680b      	ldr	r3, [r1, #0]
	parent->next = child;
    7616:	6023      	str	r3, [r4, #0]
	return list->tail;
    7618:	686b      	ldr	r3, [r5, #4]
Z_GENLIST_REMOVE(slist, snode)
    761a:	4299      	cmp	r1, r3
    761c:	d0f1      	beq.n	7602 <gpio_nrfx_manage_callback+0x1e>
	parent->next = child;
    761e:	2300      	movs	r3, #0
    7620:	600b      	str	r3, [r1, #0]
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    7622:	e000      	b.n	7626 <gpio_nrfx_manage_callback+0x42>
			if (!set) {
    7624:	b152      	cbz	r2, 763c <gpio_nrfx_manage_callback+0x58>
	if (set) {
    7626:	b162      	cbz	r2, 7642 <gpio_nrfx_manage_callback+0x5e>
	return list->head;
    7628:	6843      	ldr	r3, [r0, #4]
	parent->next = child;
    762a:	600b      	str	r3, [r1, #0]
	list->head = node;
    762c:	6041      	str	r1, [r0, #4]
	return list->tail;
    762e:	686b      	ldr	r3, [r5, #4]
Z_GENLIST_PREPEND(slist, snode)
    7630:	b10b      	cbz	r3, 7636 <gpio_nrfx_manage_callback+0x52>
	return 0;
    7632:	2000      	movs	r0, #0
    7634:	e006      	b.n	7644 <gpio_nrfx_manage_callback+0x60>
	list->tail = node;
    7636:	6069      	str	r1, [r5, #4]
    7638:	2000      	movs	r0, #0
}
    763a:	e003      	b.n	7644 <gpio_nrfx_manage_callback+0x60>
				return -EINVAL;
    763c:	f06f 0015 	mvn.w	r0, #21
    7640:	e000      	b.n	7644 <gpio_nrfx_manage_callback+0x60>
	return 0;
    7642:	2000      	movs	r0, #0
}
    7644:	bc70      	pop	{r4, r5, r6}
    7646:	4770      	bx	lr

00007648 <twi_0_init>:
		      POST_KERNEL,					       \
		      CONFIG_I2C_INIT_PRIORITY,				       \
		      &i2c_nrfx_twi_driver_api)

#ifdef CONFIG_I2C_0_NRF_TWI
I2C_NRFX_TWI_DEVICE(0);
    7648:	b510      	push	{r4, lr}
    764a:	4604      	mov	r4, r0
    764c:	2200      	movs	r2, #0
    764e:	2101      	movs	r1, #1
    7650:	2003      	movs	r0, #3
    7652:	f7fa fddb 	bl	220c <z_arm_irq_priority_set>
    7656:	4620      	mov	r0, r4
    7658:	f7fc fa86 	bl	3b68 <init_twi>
    765c:	bd10      	pop	{r4, pc}

0000765e <uart_nrfx_config_get>:
{
    765e:	460b      	mov	r3, r1
	return dev->data;
    7660:	6902      	ldr	r2, [r0, #16]
	*cfg = get_dev_data(dev)->uart_config;
    7662:	e892 0003 	ldmia.w	r2, {r0, r1}
    7666:	e883 0003 	stmia.w	r3, {r0, r1}
}
    766a:	2000      	movs	r0, #0
    766c:	4770      	bx	lr

0000766e <sys_clock_isr>:
/* Weak-linked noop defaults for optional driver interfaces*/

void __weak sys_clock_isr(void *arg)
{
	__ASSERT_NO_MSG(false);
}
    766e:	4770      	bx	lr

00007670 <sys_clock_idle_exit>:
{
}

void __weak sys_clock_idle_exit(void)
{
}
    7670:	4770      	bx	lr

00007672 <counter_sub>:
	return (a - b) & COUNTER_MAX;
    7672:	1a40      	subs	r0, r0, r1
}
    7674:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
    7678:	4770      	bx	lr

0000767a <event_clear>:
	nrf_rtc_event_clear(RTC, RTC_CHANNEL_EVENT_ADDR(chan));
    767a:	f100 0350 	add.w	r3, r0, #80	; 0x50
    767e:	009b      	lsls	r3, r3, #2
    7680:	b29b      	uxth	r3, r3
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    7682:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    7686:	f503 3388 	add.w	r3, r3, #69632	; 0x11000
    768a:	2200      	movs	r2, #0
    768c:	601a      	str	r2, [r3, #0]
    768e:	681b      	ldr	r3, [r3, #0]
}
    7690:	4770      	bx	lr

00007692 <absolute_time_to_cc>:
}
    7692:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
    7696:	4770      	bx	lr

00007698 <full_int_lock>:
	__asm__ volatile(
    7698:	f04f 0320 	mov.w	r3, #32
    769c:	f3ef 8011 	mrs	r0, BASEPRI
    76a0:	f383 8812 	msr	BASEPRI_MAX, r3
    76a4:	f3bf 8f6f 	isb	sy
}
    76a8:	4770      	bx	lr

000076aa <full_int_unlock>:
	__asm__ volatile(
    76aa:	f380 8811 	msr	BASEPRI, r0
    76ae:	f3bf 8f6f 	isb	sy
}
    76b2:	4770      	bx	lr

000076b4 <set_absolute_alarm>:
{
    76b4:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    76b6:	4606      	mov	r6, r0
	uint32_t cc_val = abs_val & COUNTER_MAX;
    76b8:	f021 457f 	bic.w	r5, r1, #4278190080	; 0xff000000
	uint32_t prev_cc = get_comparator(chan);
    76bc:	f7fc fcce 	bl	405c <get_comparator>
    76c0:	4607      	mov	r7, r0
    76c2:	e019      	b.n	76f8 <set_absolute_alarm+0x44>
	z_impl_k_busy_wait(usec_to_wait);
    76c4:	2013      	movs	r0, #19
    76c6:	f000 fca6 	bl	8016 <z_impl_k_busy_wait>
}
    76ca:	e022      	b.n	7712 <set_absolute_alarm+0x5e>
		event_clear(chan);
    76cc:	4630      	mov	r0, r6
    76ce:	f7ff ffd4 	bl	767a <event_clear>
		event_enable(chan);
    76d2:	4630      	mov	r0, r6
    76d4:	f7fc fcca 	bl	406c <event_enable>
		set_comparator(chan, cc_val);
    76d8:	4629      	mov	r1, r5
    76da:	4630      	mov	r0, r6
    76dc:	f7fc fcb4 	bl	4048 <set_comparator>
		now2 = counter();
    76e0:	f7fc fcd8 	bl	4094 <counter>
		 (counter_sub(cc_val, now2 + 2) > COUNTER_HALF_SPAN));
    76e4:	4284      	cmp	r4, r0
    76e6:	d01e      	beq.n	7726 <set_absolute_alarm+0x72>
    76e8:	1c81      	adds	r1, r0, #2
    76ea:	4628      	mov	r0, r5
    76ec:	f7ff ffc1 	bl	7672 <counter_sub>
	} while ((now2 != now) &&
    76f0:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    76f4:	d917      	bls.n	7726 <set_absolute_alarm+0x72>
		prev_cc = cc_val;
    76f6:	462f      	mov	r7, r5
		now = counter();
    76f8:	f7fc fccc 	bl	4094 <counter>
    76fc:	4604      	mov	r4, r0
		set_comparator(chan, now);
    76fe:	4601      	mov	r1, r0
    7700:	4630      	mov	r0, r6
    7702:	f7fc fca1 	bl	4048 <set_comparator>
		if (counter_sub(prev_cc, now) == 1) {
    7706:	4621      	mov	r1, r4
    7708:	4638      	mov	r0, r7
    770a:	f7ff ffb2 	bl	7672 <counter_sub>
    770e:	2801      	cmp	r0, #1
    7710:	d0d8      	beq.n	76c4 <set_absolute_alarm+0x10>
		if (counter_sub(cc_val, now + 2) > COUNTER_HALF_SPAN) {
    7712:	1ca7      	adds	r7, r4, #2
    7714:	4639      	mov	r1, r7
    7716:	4628      	mov	r0, r5
    7718:	f7ff ffab 	bl	7672 <counter_sub>
    771c:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    7720:	d9d4      	bls.n	76cc <set_absolute_alarm+0x18>
			cc_val = now + 2;
    7722:	463d      	mov	r5, r7
    7724:	e7d2      	b.n	76cc <set_absolute_alarm+0x18>
}
    7726:	4628      	mov	r0, r5
    7728:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}

0000772a <compare_set>:
{
    772a:	b5f0      	push	{r4, r5, r6, r7, lr}
    772c:	b083      	sub	sp, #12
    772e:	4604      	mov	r4, r0
    7730:	4617      	mov	r7, r2
    7732:	461d      	mov	r5, r3
	key = compare_int_lock(chan);
    7734:	f7fc fcb4 	bl	40a0 <compare_int_lock>
    7738:	4606      	mov	r6, r0
	int ret = compare_set_nolocks(chan, target_time, handler, user_data);
    773a:	9b09      	ldr	r3, [sp, #36]	; 0x24
    773c:	9301      	str	r3, [sp, #4]
    773e:	9b08      	ldr	r3, [sp, #32]
    7740:	9300      	str	r3, [sp, #0]
    7742:	463a      	mov	r2, r7
    7744:	462b      	mov	r3, r5
    7746:	4620      	mov	r0, r4
    7748:	f7fc fd98 	bl	427c <compare_set_nolocks>
    774c:	4605      	mov	r5, r0
	compare_int_unlock(chan, key);
    774e:	4631      	mov	r1, r6
    7750:	4620      	mov	r0, r4
    7752:	f7fc fd09 	bl	4168 <compare_int_unlock>
}
    7756:	4628      	mov	r0, r5
    7758:	b003      	add	sp, #12
    775a:	bdf0      	pop	{r4, r5, r6, r7, pc}

0000775c <sys_clock_cycle_get_32>:

uint32_t sys_clock_cycle_get_32(void)
{
    775c:	b508      	push	{r3, lr}
	return (uint32_t)z_nrf_rtc_timer_read();
    775e:	f7fc fd6d 	bl	423c <z_nrf_rtc_timer_read>
}
    7762:	bd08      	pop	{r3, pc}

00007764 <nrfx_isr>:

#include <nrfx.h>
#include <kernel.h>

void nrfx_isr(const void *irq_handler)
{
    7764:	b508      	push	{r3, lr}
	((nrfx_irq_handler_t)irq_handler)();
    7766:	4780      	blx	r0
}
    7768:	bd08      	pop	{r3, pc}

0000776a <nrfx_busy_wait>:

void nrfx_busy_wait(uint32_t usec_to_wait)
{
    776a:	b508      	push	{r3, lr}
	z_impl_k_busy_wait(usec_to_wait);
    776c:	f000 fc53 	bl	8016 <z_impl_k_busy_wait>
	k_busy_wait(usec_to_wait);
}
    7770:	bd08      	pop	{r3, pc}

00007772 <nrfx_clock_enable>:
{
    7772:	b508      	push	{r3, lr}
    priority = NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY;
#else
    #error "This code is not supposed to be compiled when neither POWER nor CLOCK is enabled."
#endif

    if (!NRFX_IRQ_IS_ENABLED(nrfx_get_irq_number(NRF_CLOCK)))
    7774:	2000      	movs	r0, #0
    7776:	f7fa fd3b 	bl	21f0 <arch_irq_is_enabled>
    777a:	b128      	cbz	r0, 7788 <nrfx_clock_enable+0x16>
}

NRF_STATIC_INLINE void nrf_clock_lf_src_set(NRF_CLOCK_Type * p_reg, nrf_clock_lfclk_t source)
{
    p_reg->LFCLKSRC = (uint32_t)(source);
    777c:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    7780:	2200      	movs	r2, #0
    7782:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
}
    7786:	bd08      	pop	{r3, pc}
    {
        NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_CLOCK), priority);
        NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_CLOCK));
    7788:	f7fa fd22 	bl	21d0 <arch_irq_enable>
    778c:	e7f6      	b.n	777c <nrfx_clock_enable+0xa>

0000778e <is_app_channel>:
    return NRFX_GPIOTE_APP_CHANNELS_MASK & (1UL << index);
    778e:	2301      	movs	r3, #1
    7790:	4083      	lsls	r3, r0
    7792:	f013 0fff 	tst.w	r3, #255	; 0xff
}
    7796:	bf14      	ite	ne
    7798:	2001      	movne	r0, #1
    779a:	2000      	moveq	r0, #0
    779c:	4770      	bx	lr

0000779e <xfer_completeness_check>:
    if (p_cb->bytes_transferred != p_cb->curr_length)
    779e:	6b4a      	ldr	r2, [r1, #52]	; 0x34
    77a0:	6a8b      	ldr	r3, [r1, #40]	; 0x28
    77a2:	429a      	cmp	r2, r3
    77a4:	d007      	beq.n	77b6 <xfer_completeness_check+0x18>
    77a6:	2300      	movs	r3, #0
    77a8:	f8c0 3500 	str.w	r3, [r0, #1280]	; 0x500
    p_reg->ENABLE = (TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos);
    77ac:	2205      	movs	r2, #5
    77ae:	f8c0 2500 	str.w	r2, [r0, #1280]	; 0x500
        return false;
    77b2:	4618      	mov	r0, r3
    77b4:	4770      	bx	lr
        return true;
    77b6:	2001      	movs	r0, #1
}
    77b8:	4770      	bx	lr

000077ba <twi_send_byte>:
{
    77ba:	4603      	mov	r3, r0
    if (p_cb->bytes_transferred < p_cb->curr_length)
    77bc:	6b4a      	ldr	r2, [r1, #52]	; 0x34
    77be:	6a88      	ldr	r0, [r1, #40]	; 0x28
    77c0:	4282      	cmp	r2, r0
    77c2:	d205      	bcs.n	77d0 <twi_send_byte+0x16>
        nrf_twi_txd_set(p_twi, p_cb->p_curr_buf[p_cb->bytes_transferred]);
    77c4:	6a49      	ldr	r1, [r1, #36]	; 0x24
    77c6:	5c8a      	ldrb	r2, [r1, r2]
    p_reg->TXD = data;
    77c8:	f8c3 251c 	str.w	r2, [r3, #1308]	; 0x51c
    return true;
    77cc:	2001      	movs	r0, #1
}
    77ce:	4770      	bx	lr
        if (p_cb->curr_tx_no_stop)
    77d0:	f891 002c 	ldrb.w	r0, [r1, #44]	; 0x2c
    77d4:	b930      	cbnz	r0, 77e4 <twi_send_byte+0x2a>
        else if(TWI_FLAG_SUSPEND(p_cb->flags))
    77d6:	6a0a      	ldr	r2, [r1, #32]
    77d8:	f012 0f40 	tst.w	r2, #64	; 0x40
    77dc:	d106      	bne.n	77ec <twi_send_byte+0x32>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    77de:	2001      	movs	r0, #1
    77e0:	6158      	str	r0, [r3, #20]
}
    77e2:	4770      	bx	lr
    77e4:	2201      	movs	r2, #1
    77e6:	61da      	str	r2, [r3, #28]
            return false;
    77e8:	2000      	movs	r0, #0
    77ea:	4770      	bx	lr
    77ec:	2201      	movs	r2, #1
    77ee:	61da      	str	r2, [r3, #28]
            p_cb->prev_suspend = TWI_SUSPEND_TX;
    77f0:	f881 202d 	strb.w	r2, [r1, #45]	; 0x2d
            return false;
    77f4:	4770      	bx	lr

000077f6 <twi_receive_byte>:
    if (p_cb->bytes_transferred < p_cb->curr_length)
    77f6:	6b4b      	ldr	r3, [r1, #52]	; 0x34
    77f8:	6a8a      	ldr	r2, [r1, #40]	; 0x28
    77fa:	4293      	cmp	r3, r2
    77fc:	d22b      	bcs.n	7856 <twi_receive_byte+0x60>
{
    77fe:	b410      	push	{r4}
    7800:	4604      	mov	r4, r0
        p_cb->p_curr_buf[p_cb->bytes_transferred] = nrf_twi_rxd_get(p_twi);
    7802:	6a4a      	ldr	r2, [r1, #36]	; 0x24
    return (uint8_t)p_reg->RXD;
    7804:	f8d0 0518 	ldr.w	r0, [r0, #1304]	; 0x518
    7808:	54d0      	strb	r0, [r2, r3]
        ++(p_cb->bytes_transferred);
    780a:	6b4b      	ldr	r3, [r1, #52]	; 0x34
    780c:	3301      	adds	r3, #1
    780e:	634b      	str	r3, [r1, #52]	; 0x34
        if ((p_cb->bytes_transferred == p_cb->curr_length - 1) && (!TWI_FLAG_SUSPEND(p_cb->flags)))
    7810:	6a8a      	ldr	r2, [r1, #40]	; 0x28
    7812:	1e50      	subs	r0, r2, #1
    7814:	4283      	cmp	r3, r0
    7816:	d007      	beq.n	7828 <twi_receive_byte+0x32>
        else if (p_cb->bytes_transferred == p_cb->curr_length && (!TWI_FLAG_SUSPEND(p_cb->flags)))
    7818:	4293      	cmp	r3, r2
    781a:	d00d      	beq.n	7838 <twi_receive_byte+0x42>
        else if (p_cb->bytes_transferred == p_cb->curr_length && TWI_FLAG_SUSPEND(p_cb->flags))
    781c:	4293      	cmp	r3, r2
    781e:	d011      	beq.n	7844 <twi_receive_byte+0x4e>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    7820:	2001      	movs	r0, #1
    7822:	6220      	str	r0, [r4, #32]
}
    7824:	bc10      	pop	{r4}
    7826:	4770      	bx	lr
        if ((p_cb->bytes_transferred == p_cb->curr_length - 1) && (!TWI_FLAG_SUSPEND(p_cb->flags)))
    7828:	6a08      	ldr	r0, [r1, #32]
    782a:	f010 0f40 	tst.w	r0, #64	; 0x40
    782e:	d1f3      	bne.n	7818 <twi_receive_byte+0x22>
    p_reg->SHORTS = mask;
    7830:	2302      	movs	r3, #2
    7832:	f8c4 3200 	str.w	r3, [r4, #512]	; 0x200
}
    7836:	e7f3      	b.n	7820 <twi_receive_byte+0x2a>
        else if (p_cb->bytes_transferred == p_cb->curr_length && (!TWI_FLAG_SUSPEND(p_cb->flags)))
    7838:	6a08      	ldr	r0, [r1, #32]
    783a:	f010 0f40 	tst.w	r0, #64	; 0x40
    783e:	d1ed      	bne.n	781c <twi_receive_byte+0x26>
            return true;
    7840:	2001      	movs	r0, #1
    7842:	e7ef      	b.n	7824 <twi_receive_byte+0x2e>
        else if (p_cb->bytes_transferred == p_cb->curr_length && TWI_FLAG_SUSPEND(p_cb->flags))
    7844:	6a0b      	ldr	r3, [r1, #32]
    7846:	f013 0f40 	tst.w	r3, #64	; 0x40
    784a:	d0e9      	beq.n	7820 <twi_receive_byte+0x2a>
            p_cb->prev_suspend = TWI_SUSPEND_RX;
    784c:	2302      	movs	r3, #2
    784e:	f881 302d 	strb.w	r3, [r1, #45]	; 0x2d
            return false;
    7852:	2000      	movs	r0, #0
    7854:	e7e6      	b.n	7824 <twi_receive_byte+0x2e>
    return true;
    7856:	2001      	movs	r0, #1
}
    7858:	4770      	bx	lr

0000785a <twi_transfer>:
{
    785a:	b570      	push	{r4, r5, r6, lr}
    785c:	4604      	mov	r4, r0
    785e:	460d      	mov	r5, r1
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    7860:	f8d0 3104 	ldr.w	r3, [r0, #260]	; 0x104
    if (nrf_twi_event_check(p_twi, NRF_TWI_EVENT_STOPPED))
    7864:	b1cb      	cbz	r3, 789a <twi_transfer+0x40>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    7866:	2300      	movs	r3, #0
    7868:	f8c0 3104 	str.w	r3, [r0, #260]	; 0x104
    786c:	f8d0 3104 	ldr.w	r3, [r0, #260]	; 0x104
        stopped = true;
    7870:	2601      	movs	r6, #1
    if (p_cb->error)
    7872:	f895 302f 	ldrb.w	r3, [r5, #47]	; 0x2f
    7876:	b193      	cbz	r3, 789e <twi_transfer+0x44>
    7878:	2300      	movs	r3, #0
    787a:	f8c4 3124 	str.w	r3, [r4, #292]	; 0x124
    787e:	f8d4 2124 	ldr.w	r2, [r4, #292]	; 0x124
    7882:	f8c4 311c 	str.w	r3, [r4, #284]	; 0x11c
    7886:	f8d4 211c 	ldr.w	r2, [r4, #284]	; 0x11c
    788a:	f8c4 3108 	str.w	r3, [r4, #264]	; 0x108
    788e:	f8d4 3108 	ldr.w	r3, [r4, #264]	; 0x108
    if (stopped)
    7892:	2e00      	cmp	r6, #0
    7894:	d14c      	bne.n	7930 <twi_transfer+0xd6>
    return true;
    7896:	2001      	movs	r0, #1
}
    7898:	bd70      	pop	{r4, r5, r6, pc}
    bool stopped = false;
    789a:	2600      	movs	r6, #0
    789c:	e7e9      	b.n	7872 <twi_transfer+0x18>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    789e:	f8d4 3124 	ldr.w	r3, [r4, #292]	; 0x124
    else if (nrf_twi_event_check(p_twi, NRF_TWI_EVENT_ERROR))
    78a2:	b14b      	cbz	r3, 78b8 <twi_transfer+0x5e>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    78a4:	2300      	movs	r3, #0
    78a6:	f8c4 3124 	str.w	r3, [r4, #292]	; 0x124
    78aa:	f8d4 3124 	ldr.w	r3, [r4, #292]	; 0x124
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    78ae:	2301      	movs	r3, #1
    78b0:	6163      	str	r3, [r4, #20]
        p_cb->error = true;
    78b2:	f885 302f 	strb.w	r3, [r5, #47]	; 0x2f
    78b6:	e7ec      	b.n	7892 <twi_transfer+0x38>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    78b8:	f8d4 311c 	ldr.w	r3, [r4, #284]	; 0x11c
        if (nrf_twi_event_check(p_twi, NRF_TWI_EVENT_TXDSENT))
    78bc:	b1db      	cbz	r3, 78f6 <twi_transfer+0x9c>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    78be:	2300      	movs	r3, #0
    78c0:	f8c4 311c 	str.w	r3, [r4, #284]	; 0x11c
    78c4:	f8d4 311c 	ldr.w	r3, [r4, #284]	; 0x11c
            ++(p_cb->bytes_transferred);
    78c8:	6b6b      	ldr	r3, [r5, #52]	; 0x34
    78ca:	3301      	adds	r3, #1
    78cc:	636b      	str	r3, [r5, #52]	; 0x34
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    78ce:	f8d4 3124 	ldr.w	r3, [r4, #292]	; 0x124
            if (nrf_twi_event_check(p_twi, NRF_TWI_EVENT_ERROR))
    78d2:	b14b      	cbz	r3, 78e8 <twi_transfer+0x8e>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    78d4:	2300      	movs	r3, #0
    78d6:	f8c4 3124 	str.w	r3, [r4, #292]	; 0x124
    78da:	f8d4 3124 	ldr.w	r3, [r4, #292]	; 0x124
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    78de:	2301      	movs	r3, #1
    78e0:	6163      	str	r3, [r4, #20]
                p_cb->error = true;
    78e2:	f885 302f 	strb.w	r3, [r5, #47]	; 0x2f
    78e6:	e7d4      	b.n	7892 <twi_transfer+0x38>
                if (!twi_send_byte(p_twi, p_cb))
    78e8:	4629      	mov	r1, r5
    78ea:	4620      	mov	r0, r4
    78ec:	f7ff ff65 	bl	77ba <twi_send_byte>
    78f0:	2800      	cmp	r0, #0
    78f2:	d1ce      	bne.n	7892 <twi_transfer+0x38>
    78f4:	e7d0      	b.n	7898 <twi_transfer+0x3e>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    78f6:	f8d4 3108 	ldr.w	r3, [r4, #264]	; 0x108
        else if (nrf_twi_event_check(p_twi, NRF_TWI_EVENT_RXDREADY))
    78fa:	2b00      	cmp	r3, #0
    78fc:	d0c9      	beq.n	7892 <twi_transfer+0x38>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    78fe:	2300      	movs	r3, #0
    7900:	f8c4 3108 	str.w	r3, [r4, #264]	; 0x108
    7904:	f8d4 3108 	ldr.w	r3, [r4, #264]	; 0x108
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    7908:	f8d4 3124 	ldr.w	r3, [r4, #292]	; 0x124
            if (nrf_twi_event_check(p_twi, NRF_TWI_EVENT_ERROR))
    790c:	b14b      	cbz	r3, 7922 <twi_transfer+0xc8>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    790e:	2300      	movs	r3, #0
    7910:	f8c4 3124 	str.w	r3, [r4, #292]	; 0x124
    7914:	f8d4 3124 	ldr.w	r3, [r4, #292]	; 0x124
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    7918:	2301      	movs	r3, #1
    791a:	6163      	str	r3, [r4, #20]
                p_cb->error = true;
    791c:	f885 302f 	strb.w	r3, [r5, #47]	; 0x2f
    7920:	e7b7      	b.n	7892 <twi_transfer+0x38>
                if (!twi_receive_byte(p_twi, p_cb))
    7922:	4629      	mov	r1, r5
    7924:	4620      	mov	r0, r4
    7926:	f7ff ff66 	bl	77f6 <twi_receive_byte>
    792a:	2800      	cmp	r0, #0
    792c:	d1b1      	bne.n	7892 <twi_transfer+0x38>
    792e:	e7b3      	b.n	7898 <twi_transfer+0x3e>
        p_cb->prev_suspend = TWI_NO_SUSPEND;
    7930:	2300      	movs	r3, #0
    7932:	f885 302d 	strb.w	r3, [r5, #45]	; 0x2d
        if (!p_cb->error)
    7936:	f895 302f 	ldrb.w	r3, [r5, #47]	; 0x2f
    793a:	b10b      	cbz	r3, 7940 <twi_transfer+0xe6>
        return false;
    793c:	2000      	movs	r0, #0
    793e:	e7ab      	b.n	7898 <twi_transfer+0x3e>
            p_cb->error = !xfer_completeness_check(p_twi, p_cb);
    7940:	4629      	mov	r1, r5
    7942:	4620      	mov	r0, r4
    7944:	f7ff ff2b 	bl	779e <xfer_completeness_check>
    7948:	f080 0001 	eor.w	r0, r0, #1
    794c:	f885 002f 	strb.w	r0, [r5, #47]	; 0x2f
    7950:	e7f4      	b.n	793c <twi_transfer+0xe2>

00007952 <twi_irq_handler>:
{
    7952:	b5f0      	push	{r4, r5, r6, r7, lr}
    7954:	b087      	sub	sp, #28
    7956:	4607      	mov	r7, r0
    7958:	460c      	mov	r4, r1
    if (twi_transfer(p_twi, p_cb))
    795a:	f7ff ff7e 	bl	785a <twi_transfer>
    795e:	2800      	cmp	r0, #0
    7960:	d15d      	bne.n	7a1e <twi_irq_handler+0xcc>
    if (!p_cb->error &&
    7962:	f894 c02f 	ldrb.w	ip, [r4, #47]	; 0x2f
    7966:	f1bc 0f00 	cmp.w	ip, #0
    796a:	d104      	bne.n	7976 <twi_irq_handler+0x24>
        ((p_cb->xfer_desc.type == NRFX_TWI_XFER_TXRX) ||
    796c:	7b22      	ldrb	r2, [r4, #12]
    796e:	1e93      	subs	r3, r2, #2
    7970:	b2db      	uxtb	r3, r3
    if (!p_cb->error &&
    7972:	2b01      	cmp	r3, #1
    7974:	d914      	bls.n	79a0 <twi_irq_handler+0x4e>
        event.xfer_desc = p_cb->xfer_desc;
    7976:	ad01      	add	r5, sp, #4
    7978:	f104 060c 	add.w	r6, r4, #12
    797c:	ce0f      	ldmia	r6!, {r0, r1, r2, r3}
    797e:	c50f      	stmia	r5!, {r0, r1, r2, r3}
    7980:	6833      	ldr	r3, [r6, #0]
    7982:	602b      	str	r3, [r5, #0]
        if (p_cb->error)
    7984:	f1bc 0f00 	cmp.w	ip, #0
    7988:	d038      	beq.n	79fc <twi_irq_handler+0xaa>
    uint32_t error_source = p_reg->ERRORSRC;
    798a:	f8d7 34c4 	ldr.w	r3, [r7, #1220]	; 0x4c4
    p_reg->ERRORSRC = error_source;
    798e:	f8c7 34c4 	str.w	r3, [r7, #1220]	; 0x4c4
            if (errorsrc & NRF_TWI_ERROR_ADDRESS_NACK)
    7992:	f013 0f02 	tst.w	r3, #2
    7996:	d01f      	beq.n	79d8 <twi_irq_handler+0x86>
                event.type = NRFX_TWI_EVT_ADDRESS_NACK;
    7998:	2301      	movs	r3, #1
    799a:	f88d 3000 	strb.w	r3, [sp]
                NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRFX_TWI_EVT_ADDRESS_NACK));
    799e:	e030      	b.n	7a02 <twi_irq_handler+0xb0>
        p_cb->p_curr_buf == p_cb->xfer_desc.p_primary_buf)
    79a0:	6a61      	ldr	r1, [r4, #36]	; 0x24
    79a2:	69a3      	ldr	r3, [r4, #24]
         (p_cb->xfer_desc.type == NRFX_TWI_XFER_TXTX)) &&
    79a4:	4299      	cmp	r1, r3
    79a6:	d1e6      	bne.n	7976 <twi_irq_handler+0x24>
        p_cb->p_curr_buf      = p_cb->xfer_desc.p_secondary_buf;
    79a8:	69e3      	ldr	r3, [r4, #28]
    79aa:	6263      	str	r3, [r4, #36]	; 0x24
        p_cb->curr_length     = p_cb->xfer_desc.secondary_length;
    79ac:	6963      	ldr	r3, [r4, #20]
    79ae:	62a3      	str	r3, [r4, #40]	; 0x28
        p_cb->curr_tx_no_stop = (p_cb->flags & NRFX_TWI_FLAG_TX_NO_STOP);
    79b0:	6a23      	ldr	r3, [r4, #32]
    79b2:	f3c3 1340 	ubfx	r3, r3, #5, #1
    79b6:	f884 302c 	strb.w	r3, [r4, #44]	; 0x2c
        p_cb->prev_suspend    = TWI_NO_SUSPEND;
    79ba:	2300      	movs	r3, #0
    79bc:	f884 302d 	strb.w	r3, [r4, #45]	; 0x2d
        if (p_cb->xfer_desc.type == NRFX_TWI_XFER_TXTX)
    79c0:	2a03      	cmp	r2, #3
    79c2:	d004      	beq.n	79ce <twi_irq_handler+0x7c>
            (void)twi_rx_start_transfer(p_twi, p_cb);
    79c4:	4621      	mov	r1, r4
    79c6:	4638      	mov	r0, r7
    79c8:	f7fd f8d4 	bl	4b74 <twi_rx_start_transfer>
    79cc:	e027      	b.n	7a1e <twi_irq_handler+0xcc>
            (void)twi_tx_start_transfer(p_twi, p_cb);
    79ce:	4621      	mov	r1, r4
    79d0:	4638      	mov	r0, r7
    79d2:	f7fd f871 	bl	4ab8 <twi_tx_start_transfer>
    79d6:	e022      	b.n	7a1e <twi_irq_handler+0xcc>
            else if (errorsrc & NRF_TWI_ERROR_DATA_NACK)
    79d8:	f013 0f04 	tst.w	r3, #4
    79dc:	d003      	beq.n	79e6 <twi_irq_handler+0x94>
                event.type = NRFX_TWI_EVT_DATA_NACK;
    79de:	2302      	movs	r3, #2
    79e0:	f88d 3000 	strb.w	r3, [sp]
                NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRFX_TWI_EVT_DATA_NACK));
    79e4:	e00d      	b.n	7a02 <twi_irq_handler+0xb0>
            else if (errorsrc & NRF_TWI_ERROR_OVERRUN)
    79e6:	f013 0f01 	tst.w	r3, #1
    79ea:	d003      	beq.n	79f4 <twi_irq_handler+0xa2>
                event.type = NRFX_TWI_EVT_OVERRUN;
    79ec:	2303      	movs	r3, #3
    79ee:	f88d 3000 	strb.w	r3, [sp]
                NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRFX_TWI_EVT_OVERRUN));
    79f2:	e006      	b.n	7a02 <twi_irq_handler+0xb0>
                event.type = NRFX_TWI_EVT_BUS_ERROR;
    79f4:	2304      	movs	r3, #4
    79f6:	f88d 3000 	strb.w	r3, [sp]
                NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRFX_TWI_EVT_BUS_ERROR));
    79fa:	e002      	b.n	7a02 <twi_irq_handler+0xb0>
            event.type = NRFX_TWI_EVT_DONE;
    79fc:	2300      	movs	r3, #0
    79fe:	f88d 3000 	strb.w	r3, [sp]
        p_cb->busy = false;
    7a02:	2300      	movs	r3, #0
    7a04:	f884 3030 	strb.w	r3, [r4, #48]	; 0x30
        if (!(TWI_FLAG_NO_HANDLER_IN_USE(p_cb->flags)) || p_cb->error)
    7a08:	6a23      	ldr	r3, [r4, #32]
    7a0a:	f013 0f04 	tst.w	r3, #4
    7a0e:	d002      	beq.n	7a16 <twi_irq_handler+0xc4>
    7a10:	f894 302f 	ldrb.w	r3, [r4, #47]	; 0x2f
    7a14:	b11b      	cbz	r3, 7a1e <twi_irq_handler+0xcc>
            p_cb->handler(&event, p_cb->p_context);
    7a16:	6823      	ldr	r3, [r4, #0]
    7a18:	6861      	ldr	r1, [r4, #4]
    7a1a:	4668      	mov	r0, sp
    7a1c:	4798      	blx	r3
}
    7a1e:	b007      	add	sp, #28
    7a20:	bdf0      	pop	{r4, r5, r6, r7, pc}

00007a22 <SEGGER_RTT_Init>:
*  Function description
*    Initializes the RTT Control Block.
*    Should be used in RAM targets, at start of the application.
*
*/
void SEGGER_RTT_Init (void) {
    7a22:	b508      	push	{r3, lr}
  _DoInit();
    7a24:	f7fd fa70 	bl	4f08 <_DoInit>
}
    7a28:	bd08      	pop	{r3, pc}

00007a2a <rtt_init>:
 */

K_MUTEX_DEFINE(rtt_term_mutex);

static int rtt_init(const struct device *unused)
{
    7a2a:	b508      	push	{r3, lr}
	ARG_UNUSED(unused);

	SEGGER_RTT_Init();
    7a2c:	f7ff fff9 	bl	7a22 <SEGGER_RTT_Init>

	return 0;
}
    7a30:	2000      	movs	r0, #0
    7a32:	bd08      	pop	{r3, pc}

00007a34 <z_device_ready>:
{
	/*
	 * if an invalid device pointer is passed as argument, this call
	 * reports the `device` as not ready for usage.
	 */
	if (dev == NULL) {
    7a34:	b148      	cbz	r0, 7a4a <z_device_ready+0x16>
		return false;
	}

	return dev->state->initialized && (dev->state->init_res == 0U);
    7a36:	68c3      	ldr	r3, [r0, #12]
    7a38:	8818      	ldrh	r0, [r3, #0]
    7a3a:	f3c0 0008 	ubfx	r0, r0, #0, #9
    7a3e:	f5b0 7f80 	cmp.w	r0, #256	; 0x100
    7a42:	bf14      	ite	ne
    7a44:	2000      	movne	r0, #0
    7a46:	2001      	moveq	r0, #1
    7a48:	4770      	bx	lr
		return false;
    7a4a:	2000      	movs	r0, #0
}
    7a4c:	4770      	bx	lr

00007a4e <create_free_list>:
	CHECKIF(((slab->block_size | (uintptr_t)slab->buffer) &
    7a4e:	6902      	ldr	r2, [r0, #16]
    7a50:	6943      	ldr	r3, [r0, #20]
    7a52:	431a      	orrs	r2, r3
    7a54:	f012 0203 	ands.w	r2, r2, #3
    7a58:	d10d      	bne.n	7a76 <create_free_list+0x28>
	slab->free_list = NULL;
    7a5a:	2100      	movs	r1, #0
    7a5c:	6181      	str	r1, [r0, #24]
	for (j = 0U; j < slab->num_blocks; j++) {
    7a5e:	e005      	b.n	7a6c <create_free_list+0x1e>
		*(char **)p = slab->free_list;
    7a60:	6981      	ldr	r1, [r0, #24]
    7a62:	6019      	str	r1, [r3, #0]
		slab->free_list = p;
    7a64:	6183      	str	r3, [r0, #24]
		p += slab->block_size;
    7a66:	6901      	ldr	r1, [r0, #16]
    7a68:	440b      	add	r3, r1
	for (j = 0U; j < slab->num_blocks; j++) {
    7a6a:	3201      	adds	r2, #1
    7a6c:	68c1      	ldr	r1, [r0, #12]
    7a6e:	4291      	cmp	r1, r2
    7a70:	d8f6      	bhi.n	7a60 <create_free_list+0x12>
	return 0;
    7a72:	2000      	movs	r0, #0
    7a74:	4770      	bx	lr
		return -EINVAL;
    7a76:	f06f 0015 	mvn.w	r0, #21
}
    7a7a:	4770      	bx	lr

00007a7c <k_mem_slab_init>:
{
    7a7c:	b510      	push	{r4, lr}
    7a7e:	4604      	mov	r4, r0
	slab->num_blocks = num_blocks;
    7a80:	60c3      	str	r3, [r0, #12]
	slab->block_size = block_size;
    7a82:	6102      	str	r2, [r0, #16]
	slab->buffer = buffer;
    7a84:	6141      	str	r1, [r0, #20]
	slab->num_used = 0U;
    7a86:	2300      	movs	r3, #0
    7a88:	61c3      	str	r3, [r0, #28]
	slab->lock = (struct k_spinlock) {};
    7a8a:	7203      	strb	r3, [r0, #8]
	rc = create_free_list(slab);
    7a8c:	f7ff ffdf 	bl	7a4e <create_free_list>
	if (rc < 0) {
    7a90:	2800      	cmp	r0, #0
    7a92:	db01      	blt.n	7a98 <k_mem_slab_init+0x1c>
	list->head = (sys_dnode_t *)list;
    7a94:	6024      	str	r4, [r4, #0]
	list->tail = (sys_dnode_t *)list;
    7a96:	6064      	str	r4, [r4, #4]
}
    7a98:	bd10      	pop	{r4, pc}

00007a9a <k_mem_slab_free>:

void k_mem_slab_free(struct k_mem_slab *slab, void **mem)
{
    7a9a:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    7a9c:	4604      	mov	r4, r0
    7a9e:	460d      	mov	r5, r1
	__asm__ volatile(
    7aa0:	f04f 0320 	mov.w	r3, #32
    7aa4:	f3ef 8611 	mrs	r6, BASEPRI
    7aa8:	f383 8812 	msr	BASEPRI_MAX, r3
    7aac:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&slab->lock);

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_mem_slab, free, slab);
	if (slab->free_list == NULL && IS_ENABLED(CONFIG_MULTITHREADING)) {
    7ab0:	6983      	ldr	r3, [r0, #24]
    7ab2:	b163      	cbz	r3, 7ace <k_mem_slab_free+0x34>
			z_ready_thread(pending_thread);
			z_reschedule(&slab->lock, key);
			return;
		}
	}
	**(char ***) mem = slab->free_list;
    7ab4:	682b      	ldr	r3, [r5, #0]
    7ab6:	69a2      	ldr	r2, [r4, #24]
    7ab8:	601a      	str	r2, [r3, #0]
	slab->free_list = *(char **) mem;
    7aba:	682b      	ldr	r3, [r5, #0]
    7abc:	61a3      	str	r3, [r4, #24]
	slab->num_used--;
    7abe:	69e3      	ldr	r3, [r4, #28]
    7ac0:	3b01      	subs	r3, #1
    7ac2:	61e3      	str	r3, [r4, #28]
	__asm__ volatile(
    7ac4:	f386 8811 	msr	BASEPRI, r6
    7ac8:	f3bf 8f6f 	isb	sy

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mem_slab, free, slab);

	k_spin_unlock(&slab->lock, key);
}
    7acc:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    7ace:	f100 0708 	add.w	r7, r0, #8
		struct k_thread *pending_thread = z_unpend_first_thread(&slab->wait_q);
    7ad2:	f000 f9c4 	bl	7e5e <z_unpend_first_thread>
		if (pending_thread != NULL) {
    7ad6:	2800      	cmp	r0, #0
    7ad8:	d0ec      	beq.n	7ab4 <k_mem_slab_free+0x1a>
			z_thread_return_value_set_with_data(pending_thread, 0, *mem);
    7ada:	682a      	ldr	r2, [r5, #0]
    7adc:	2100      	movs	r1, #0
    7ade:	f8c0 10ac 	str.w	r1, [r0, #172]	; 0xac
z_thread_return_value_set_with_data(struct k_thread *thread,
				   unsigned int value,
				   void *data)
{
	arch_thread_return_value_set(thread, value);
	thread->base.swap_data = data;
    7ae2:	6142      	str	r2, [r0, #20]
			z_ready_thread(pending_thread);
    7ae4:	f000 f8f9 	bl	7cda <z_ready_thread>
			z_reschedule(&slab->lock, key);
    7ae8:	4631      	mov	r1, r6
    7aea:	4638      	mov	r0, r7
    7aec:	f7fe f8da 	bl	5ca4 <z_reschedule>
			return;
    7af0:	e7ec      	b.n	7acc <k_mem_slab_free+0x32>

00007af2 <setup_thread_stack>:
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    7af2:	3207      	adds	r2, #7
    7af4:	f022 0207 	bic.w	r2, r2, #7
	new_thread->stack_info.start = (uintptr_t)stack_buf_start;
    7af8:	f8c0 1098 	str.w	r1, [r0, #152]	; 0x98
	new_thread->stack_info.size = stack_buf_size;
    7afc:	f8c0 209c 	str.w	r2, [r0, #156]	; 0x9c
	new_thread->stack_info.delta = delta;
    7b00:	2300      	movs	r3, #0
    7b02:	f8c0 30a0 	str.w	r3, [r0, #160]	; 0xa0
}
    7b06:	1888      	adds	r0, r1, r2
    7b08:	4770      	bx	lr

00007b0a <k_is_in_isr>:
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    7b0a:	f3ef 8005 	mrs	r0, IPSR
}
    7b0e:	3800      	subs	r0, #0
    7b10:	bf18      	it	ne
    7b12:	2001      	movne	r0, #1
    7b14:	4770      	bx	lr

00007b16 <k_thread_name_get>:
}
    7b16:	3074      	adds	r0, #116	; 0x74
    7b18:	4770      	bx	lr

00007b1a <z_impl_k_thread_start>:
{
    7b1a:	b508      	push	{r3, lr}
	z_sched_start(thread);
    7b1c:	f7fe f9ec 	bl	5ef8 <z_sched_start>
}
    7b20:	bd08      	pop	{r3, pc}

00007b22 <z_init_thread_base>:
#endif

void z_init_thread_base(struct _thread_base *thread_base, int priority,
		       uint32_t initial_state, unsigned int options)
{
    7b22:	b410      	push	{r4}
	/* k_q_node is initialized upon first insertion in a list */
	thread_base->pended_on = NULL;
    7b24:	2400      	movs	r4, #0
    7b26:	6084      	str	r4, [r0, #8]
	thread_base->user_options = (uint8_t)options;
    7b28:	7303      	strb	r3, [r0, #12]
	thread_base->thread_state = (uint8_t)initial_state;
    7b2a:	7342      	strb	r2, [r0, #13]

	thread_base->prio = priority;
    7b2c:	7381      	strb	r1, [r0, #14]

	thread_base->sched_locked = 0U;
    7b2e:	73c4      	strb	r4, [r0, #15]
	node->next = NULL;
    7b30:	6184      	str	r4, [r0, #24]
	node->prev = NULL;
    7b32:	61c4      	str	r4, [r0, #28]
#endif

	/* swap_data does not need to be initialized */

	z_init_thread_timeout(thread_base);
}
    7b34:	bc10      	pop	{r4}
    7b36:	4770      	bx	lr

00007b38 <z_impl_k_thread_create>:
{
    7b38:	b5f0      	push	{r4, r5, r6, r7, lr}
    7b3a:	b087      	sub	sp, #28
    7b3c:	4604      	mov	r4, r0
    7b3e:	e9dd 6712 	ldrd	r6, r7, [sp, #72]	; 0x48
	z_setup_new_thread(new_thread, stack, stack_size, entry, p1, p2, p3,
    7b42:	2500      	movs	r5, #0
    7b44:	9505      	str	r5, [sp, #20]
    7b46:	9d10      	ldr	r5, [sp, #64]	; 0x40
    7b48:	9504      	str	r5, [sp, #16]
    7b4a:	9d0f      	ldr	r5, [sp, #60]	; 0x3c
    7b4c:	9503      	str	r5, [sp, #12]
    7b4e:	9d0e      	ldr	r5, [sp, #56]	; 0x38
    7b50:	9502      	str	r5, [sp, #8]
    7b52:	9d0d      	ldr	r5, [sp, #52]	; 0x34
    7b54:	9501      	str	r5, [sp, #4]
    7b56:	9d0c      	ldr	r5, [sp, #48]	; 0x30
    7b58:	9500      	str	r5, [sp, #0]
    7b5a:	f7fd fcff 	bl	555c <z_setup_new_thread>
	if (!K_TIMEOUT_EQ(delay, K_FOREVER)) {
    7b5e:	f1b7 3fff 	cmp.w	r7, #4294967295
    7b62:	bf08      	it	eq
    7b64:	f1b6 3fff 	cmpeq.w	r6, #4294967295
    7b68:	d102      	bne.n	7b70 <z_impl_k_thread_create+0x38>
}
    7b6a:	4620      	mov	r0, r4
    7b6c:	b007      	add	sp, #28
    7b6e:	bdf0      	pop	{r4, r5, r6, r7, pc}
		schedule_new_thread(new_thread, delay);
    7b70:	4632      	mov	r2, r6
    7b72:	463b      	mov	r3, r7
    7b74:	4620      	mov	r0, r4
    7b76:	f7fd fcdf 	bl	5538 <schedule_new_thread>
    7b7a:	e7f6      	b.n	7b6a <z_impl_k_thread_create+0x32>

00007b7c <z_pm_save_idle_exit>:

void z_pm_save_idle_exit(int32_t ticks)
{
    7b7c:	b508      	push	{r3, lr}
	/* Some CPU low power states require notification at the ISR
	 * to allow any operations that needs to be done before kernel
	 * switches task or processes nested interrupts.
	 * This can be simply ignored if not required.
	 */
	pm_system_resume();
    7b7e:	f7fa fa17 	bl	1fb0 <pm_system_resume>
#endif	/* CONFIG_PM */
	sys_clock_idle_exit();
    7b82:	f7ff fd75 	bl	7670 <sys_clock_idle_exit>
}
    7b86:	bd08      	pop	{r3, pc}

00007b88 <idle>:

void idle(void *unused1, void *unused2, void *unused3)
{
    7b88:	b508      	push	{r3, lr}
	__asm__ volatile(
    7b8a:	f04f 0220 	mov.w	r2, #32
    7b8e:	f3ef 8311 	mrs	r3, BASEPRI
    7b92:	f382 8812 	msr	BASEPRI_MAX, r2
    7b96:	f3bf 8f6f 	isb	sy
		 * higher level construct.
		 */
		(void) arch_irq_lock();

		if (IS_ENABLED(CONFIG_PM)) {
			pm_save_idle();
    7b9a:	f7fd fd91 	bl	56c0 <pm_save_idle>
    7b9e:	e7f4      	b.n	7b8a <idle+0x2>

00007ba0 <new_prio_for_inheritance>:
	int new_prio = z_is_prio_higher(target, limit) ? target : limit;
    7ba0:	4288      	cmp	r0, r1
    7ba2:	da00      	bge.n	7ba6 <new_prio_for_inheritance+0x6>
    7ba4:	4601      	mov	r1, r0
	return z_is_under_prio_ceiling(prio) ? prio : CONFIG_PRIORITY_CEILING;
    7ba6:	f111 0f7f 	cmn.w	r1, #127	; 0x7f
    7baa:	db01      	blt.n	7bb0 <new_prio_for_inheritance+0x10>
    7bac:	4608      	mov	r0, r1
    7bae:	4770      	bx	lr
    7bb0:	f06f 007e 	mvn.w	r0, #126	; 0x7e
}
    7bb4:	4770      	bx	lr

00007bb6 <adjust_owner_prio>:
{
    7bb6:	b508      	push	{r3, lr}
	if (mutex->owner->base.prio != new_prio) {
    7bb8:	6880      	ldr	r0, [r0, #8]
    7bba:	f990 300e 	ldrsb.w	r3, [r0, #14]
    7bbe:	428b      	cmp	r3, r1
    7bc0:	d101      	bne.n	7bc6 <adjust_owner_prio+0x10>
	return false;
    7bc2:	2000      	movs	r0, #0
}
    7bc4:	bd08      	pop	{r3, pc}
		return z_set_prio(mutex->owner, new_prio);
    7bc6:	f7fe f9e5 	bl	5f94 <z_set_prio>
    7bca:	e7fb      	b.n	7bc4 <adjust_owner_prio+0xe>

00007bcc <z_impl_k_mutex_init>:
{
    7bcc:	4603      	mov	r3, r0
	mutex->owner = NULL;
    7bce:	2000      	movs	r0, #0
    7bd0:	6098      	str	r0, [r3, #8]
	mutex->lock_count = 0U;
    7bd2:	60d8      	str	r0, [r3, #12]
	list->head = (sys_dnode_t *)list;
    7bd4:	601b      	str	r3, [r3, #0]
	list->tail = (sys_dnode_t *)list;
    7bd6:	605b      	str	r3, [r3, #4]
}
    7bd8:	4770      	bx	lr

00007bda <z_impl_k_sem_init>:
	CHECKIF(limit == 0U || limit > K_SEM_MAX_LIMIT || initial_count > limit) {
    7bda:	b13a      	cbz	r2, 7bec <z_impl_k_sem_init+0x12>
    7bdc:	428a      	cmp	r2, r1
    7bde:	d308      	bcc.n	7bf2 <z_impl_k_sem_init+0x18>
	sem->count = initial_count;
    7be0:	6081      	str	r1, [r0, #8]
	sem->limit = limit;
    7be2:	60c2      	str	r2, [r0, #12]
	list->head = (sys_dnode_t *)list;
    7be4:	6000      	str	r0, [r0, #0]
	list->tail = (sys_dnode_t *)list;
    7be6:	6040      	str	r0, [r0, #4]
	return 0;
    7be8:	2000      	movs	r0, #0
    7bea:	4770      	bx	lr
		return -EINVAL;
    7bec:	f06f 0015 	mvn.w	r0, #21
    7bf0:	4770      	bx	lr
    7bf2:	f06f 0015 	mvn.w	r0, #21
}
    7bf6:	4770      	bx	lr

00007bf8 <k_work_submit_to_queue>:
{
    7bf8:	b530      	push	{r4, r5, lr}
    7bfa:	b083      	sub	sp, #12
    7bfc:	9001      	str	r0, [sp, #4]
    7bfe:	4608      	mov	r0, r1
    7c00:	f04f 0320 	mov.w	r3, #32
    7c04:	f3ef 8511 	mrs	r5, BASEPRI
    7c08:	f383 8812 	msr	BASEPRI_MAX, r3
    7c0c:	f3bf 8f6f 	isb	sy
	int ret = submit_to_queue_locked(work, &queue);
    7c10:	a901      	add	r1, sp, #4
    7c12:	f7fd fe7f 	bl	5914 <submit_to_queue_locked>
    7c16:	4604      	mov	r4, r0
	__asm__ volatile(
    7c18:	f385 8811 	msr	BASEPRI, r5
    7c1c:	f3bf 8f6f 	isb	sy
	if ((ret > 0) && (k_is_preempt_thread() != 0)) {
    7c20:	2800      	cmp	r0, #0
    7c22:	dc02      	bgt.n	7c2a <k_work_submit_to_queue+0x32>
}
    7c24:	4620      	mov	r0, r4
    7c26:	b003      	add	sp, #12
    7c28:	bd30      	pop	{r4, r5, pc}
	return z_impl_k_is_preempt_thread();
    7c2a:	f7fe fb9d 	bl	6368 <z_impl_k_is_preempt_thread>
	if ((ret > 0) && (k_is_preempt_thread() != 0)) {
    7c2e:	2800      	cmp	r0, #0
    7c30:	d0f8      	beq.n	7c24 <k_work_submit_to_queue+0x2c>
	z_impl_k_yield();
    7c32:	f7fe fad3 	bl	61dc <z_impl_k_yield>
	return ret;
    7c36:	e7f5      	b.n	7c24 <k_work_submit_to_queue+0x2c>

00007c38 <thread_active_elsewhere>:
}
    7c38:	2000      	movs	r0, #0
    7c3a:	4770      	bx	lr

00007c3c <pended_on_thread>:
}
    7c3c:	6880      	ldr	r0, [r0, #8]
    7c3e:	4770      	bx	lr

00007c40 <z_sched_prio_cmp>:
	int32_t b1 = thread_1->base.prio;
    7c40:	f990 300e 	ldrsb.w	r3, [r0, #14]
	int32_t b2 = thread_2->base.prio;
    7c44:	f991 000e 	ldrsb.w	r0, [r1, #14]
	if (b1 != b2) {
    7c48:	4283      	cmp	r3, r0
    7c4a:	d001      	beq.n	7c50 <z_sched_prio_cmp+0x10>
		return b2 - b1;
    7c4c:	1ac0      	subs	r0, r0, r3
    7c4e:	4770      	bx	lr
	return 0;
    7c50:	2000      	movs	r0, #0
}
    7c52:	4770      	bx	lr

00007c54 <z_unpend_thread_no_timeout>:
{
    7c54:	b538      	push	{r3, r4, r5, lr}
    7c56:	4604      	mov	r4, r0
	LOCKED(&sched_spinlock) {
    7c58:	2300      	movs	r3, #0
	__asm__ volatile(
    7c5a:	f04f 0220 	mov.w	r2, #32
    7c5e:	f3ef 8511 	mrs	r5, BASEPRI
    7c62:	f382 8812 	msr	BASEPRI_MAX, r2
    7c66:	f3bf 8f6f 	isb	sy
    7c6a:	b98b      	cbnz	r3, 7c90 <z_unpend_thread_no_timeout+0x3c>
	_priq_wait_remove(&pended_on_thread(thread)->waitq, thread);
    7c6c:	4620      	mov	r0, r4
    7c6e:	f7ff ffe5 	bl	7c3c <pended_on_thread>
    7c72:	4621      	mov	r1, r4
    7c74:	f000 f822 	bl	7cbc <z_priq_dumb_remove>
	thread->base.thread_state &= ~_THREAD_PENDING;
    7c78:	7b63      	ldrb	r3, [r4, #13]
    7c7a:	f023 0302 	bic.w	r3, r3, #2
    7c7e:	7363      	strb	r3, [r4, #13]
	thread->base.pended_on = NULL;
    7c80:	2300      	movs	r3, #0
    7c82:	60a3      	str	r3, [r4, #8]
	__asm__ volatile(
    7c84:	f385 8811 	msr	BASEPRI, r5
    7c88:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
    7c8c:	2301      	movs	r3, #1
    7c8e:	e7ec      	b.n	7c6a <z_unpend_thread_no_timeout+0x16>
}
    7c90:	bd38      	pop	{r3, r4, r5, pc}

00007c92 <z_reschedule_irqlock>:
{
    7c92:	b508      	push	{r3, lr}
	return arch_irq_unlocked(key) && !arch_is_in_isr();
    7c94:	4603      	mov	r3, r0
    7c96:	b920      	cbnz	r0, 7ca2 <z_reschedule_irqlock+0x10>
    7c98:	f3ef 8205 	mrs	r2, IPSR
    7c9c:	b942      	cbnz	r2, 7cb0 <z_reschedule_irqlock+0x1e>
    7c9e:	2201      	movs	r2, #1
    7ca0:	e000      	b.n	7ca4 <z_reschedule_irqlock+0x12>
    7ca2:	2200      	movs	r2, #0
	if (resched(key)) {
    7ca4:	b932      	cbnz	r2, 7cb4 <z_reschedule_irqlock+0x22>
    7ca6:	f383 8811 	msr	BASEPRI, r3
    7caa:	f3bf 8f6f 	isb	sy
}
    7cae:	bd08      	pop	{r3, pc}
	return arch_irq_unlocked(key) && !arch_is_in_isr();
    7cb0:	2200      	movs	r2, #0
    7cb2:	e7f7      	b.n	7ca4 <z_reschedule_irqlock+0x12>
	ret = arch_swap(key);
    7cb4:	4618      	mov	r0, r3
    7cb6:	f7fa fadf 	bl	2278 <arch_swap>
	return ret;
    7cba:	e7f8      	b.n	7cae <z_reschedule_irqlock+0x1c>

00007cbc <z_priq_dumb_remove>:
 * @return N/A
 */

static inline void sys_dlist_remove(sys_dnode_t *node)
{
	sys_dnode_t *const prev = node->prev;
    7cbc:	684a      	ldr	r2, [r1, #4]
	sys_dnode_t *const next = node->next;
    7cbe:	680b      	ldr	r3, [r1, #0]

	prev->next = next;
    7cc0:	6013      	str	r3, [r2, #0]
	next->prev = prev;
    7cc2:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    7cc4:	2300      	movs	r3, #0
    7cc6:	600b      	str	r3, [r1, #0]
	node->prev = NULL;
    7cc8:	604b      	str	r3, [r1, #4]
}
    7cca:	4770      	bx	lr

00007ccc <z_priq_dumb_best>:
{
    7ccc:	4603      	mov	r3, r0
	return list->head == list;
    7cce:	6800      	ldr	r0, [r0, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    7cd0:	4283      	cmp	r3, r0
    7cd2:	d000      	beq.n	7cd6 <z_priq_dumb_best+0xa>
}
    7cd4:	4770      	bx	lr
	struct k_thread *thread = NULL;
    7cd6:	2000      	movs	r0, #0
	return thread;
    7cd8:	e7fc      	b.n	7cd4 <z_priq_dumb_best+0x8>

00007cda <z_ready_thread>:
{
    7cda:	b538      	push	{r3, r4, r5, lr}
    7cdc:	4604      	mov	r4, r0
	LOCKED(&sched_spinlock) {
    7cde:	2300      	movs	r3, #0
	__asm__ volatile(
    7ce0:	f04f 0220 	mov.w	r2, #32
    7ce4:	f3ef 8511 	mrs	r5, BASEPRI
    7ce8:	f382 8812 	msr	BASEPRI_MAX, r2
    7cec:	f3bf 8f6f 	isb	sy
    7cf0:	e007      	b.n	7d02 <z_ready_thread+0x28>
			ready_thread(thread);
    7cf2:	4620      	mov	r0, r4
    7cf4:	f7fe f8c0 	bl	5e78 <ready_thread>
	__asm__ volatile(
    7cf8:	f385 8811 	msr	BASEPRI, r5
    7cfc:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
    7d00:	2301      	movs	r3, #1
    7d02:	b92b      	cbnz	r3, 7d10 <z_ready_thread+0x36>
		if (!thread_active_elsewhere(thread)) {
    7d04:	4620      	mov	r0, r4
    7d06:	f7ff ff97 	bl	7c38 <thread_active_elsewhere>
    7d0a:	2800      	cmp	r0, #0
    7d0c:	d1f4      	bne.n	7cf8 <z_ready_thread+0x1e>
    7d0e:	e7f0      	b.n	7cf2 <z_ready_thread+0x18>
}
    7d10:	bd38      	pop	{r3, r4, r5, pc}

00007d12 <z_thread_timeout>:
{
    7d12:	b570      	push	{r4, r5, r6, lr}
    7d14:	4604      	mov	r4, r0
	struct k_thread *thread = CONTAINER_OF(timeout,
    7d16:	f1a0 0518 	sub.w	r5, r0, #24
	LOCKED(&sched_spinlock) {
    7d1a:	2300      	movs	r3, #0
	__asm__ volatile(
    7d1c:	f04f 0220 	mov.w	r2, #32
    7d20:	f3ef 8611 	mrs	r6, BASEPRI
    7d24:	f382 8812 	msr	BASEPRI_MAX, r2
    7d28:	f3bf 8f6f 	isb	sy
    7d2c:	e019      	b.n	7d62 <z_thread_timeout+0x50>
	_priq_wait_remove(&pended_on_thread(thread)->waitq, thread);
    7d2e:	4628      	mov	r0, r5
    7d30:	f7ff ff84 	bl	7c3c <pended_on_thread>
    7d34:	4629      	mov	r1, r5
    7d36:	f7ff ffc1 	bl	7cbc <z_priq_dumb_remove>
    7d3a:	7b6b      	ldrb	r3, [r5, #13]
    7d3c:	f023 0302 	bic.w	r3, r3, #2
    7d40:	736b      	strb	r3, [r5, #13]
	thread->base.pended_on = NULL;
    7d42:	2300      	movs	r3, #0
    7d44:	60ab      	str	r3, [r5, #8]
	thread->base.thread_state &= ~_THREAD_PRESTART;
    7d46:	f814 3c0b 	ldrb.w	r3, [r4, #-11]
	thread->base.thread_state &= ~_THREAD_SUSPENDED;
    7d4a:	f003 03eb 	and.w	r3, r3, #235	; 0xeb
    7d4e:	f804 3c0b 	strb.w	r3, [r4, #-11]
			ready_thread(thread);
    7d52:	4628      	mov	r0, r5
    7d54:	f7fe f890 	bl	5e78 <ready_thread>
	__asm__ volatile(
    7d58:	f386 8811 	msr	BASEPRI, r6
    7d5c:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
    7d60:	2301      	movs	r3, #1
    7d62:	b94b      	cbnz	r3, 7d78 <z_thread_timeout+0x66>
		bool killed = ((thread->base.thread_state & _THREAD_DEAD) ||
    7d64:	f814 3c0b 	ldrb.w	r3, [r4, #-11]
		if (!killed) {
    7d68:	f013 0f28 	tst.w	r3, #40	; 0x28
    7d6c:	d1f4      	bne.n	7d58 <z_thread_timeout+0x46>
			if (thread->base.pended_on != NULL) {
    7d6e:	f854 3c10 	ldr.w	r3, [r4, #-16]
    7d72:	2b00      	cmp	r3, #0
    7d74:	d1db      	bne.n	7d2e <z_thread_timeout+0x1c>
    7d76:	e7e6      	b.n	7d46 <z_thread_timeout+0x34>
}
    7d78:	bd70      	pop	{r4, r5, r6, pc}

00007d7a <add_to_waitq_locked>:
{
    7d7a:	b570      	push	{r4, r5, r6, lr}
    7d7c:	4605      	mov	r5, r0
    7d7e:	460e      	mov	r6, r1
	unready_thread(thread);
    7d80:	f7fe f8d8 	bl	5f34 <unready_thread>
	thread->base.thread_state |= _THREAD_PENDING;
    7d84:	7b6b      	ldrb	r3, [r5, #13]
    7d86:	f043 0302 	orr.w	r3, r3, #2
    7d8a:	736b      	strb	r3, [r5, #13]
	if (wait_q != NULL) {
    7d8c:	b1b6      	cbz	r6, 7dbc <add_to_waitq_locked+0x42>
		thread->base.pended_on = wait_q;
    7d8e:	60ae      	str	r6, [r5, #8]
	return list->head == list;
    7d90:	6834      	ldr	r4, [r6, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    7d92:	42a6      	cmp	r6, r4
    7d94:	d019      	beq.n	7dca <add_to_waitq_locked+0x50>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    7d96:	b164      	cbz	r4, 7db2 <add_to_waitq_locked+0x38>
		if (z_sched_prio_cmp(thread, t) > 0) {
    7d98:	4621      	mov	r1, r4
    7d9a:	4628      	mov	r0, r5
    7d9c:	f7ff ff50 	bl	7c40 <z_sched_prio_cmp>
    7da0:	2800      	cmp	r0, #0
    7da2:	dc0c      	bgt.n	7dbe <add_to_waitq_locked+0x44>
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    7da4:	b12c      	cbz	r4, 7db2 <add_to_waitq_locked+0x38>
	return (node == list->tail) ? NULL : node->next;
    7da6:	6873      	ldr	r3, [r6, #4]
    7da8:	429c      	cmp	r4, r3
    7daa:	d002      	beq.n	7db2 <add_to_waitq_locked+0x38>
    7dac:	6824      	ldr	r4, [r4, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    7dae:	2c00      	cmp	r4, #0
    7db0:	d1f1      	bne.n	7d96 <add_to_waitq_locked+0x1c>
	sys_dnode_t *const tail = list->tail;
    7db2:	6873      	ldr	r3, [r6, #4]
	node->next = list;
    7db4:	602e      	str	r6, [r5, #0]
	node->prev = tail;
    7db6:	606b      	str	r3, [r5, #4]
	tail->next = node;
    7db8:	601d      	str	r5, [r3, #0]
	list->tail = node;
    7dba:	6075      	str	r5, [r6, #4]
}
    7dbc:	bd70      	pop	{r4, r5, r6, pc}
	sys_dnode_t *const prev = successor->prev;
    7dbe:	6863      	ldr	r3, [r4, #4]
	node->prev = prev;
    7dc0:	606b      	str	r3, [r5, #4]
	node->next = successor;
    7dc2:	602c      	str	r4, [r5, #0]
	prev->next = node;
    7dc4:	601d      	str	r5, [r3, #0]
	successor->prev = node;
    7dc6:	6065      	str	r5, [r4, #4]
}
    7dc8:	e7f8      	b.n	7dbc <add_to_waitq_locked+0x42>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    7dca:	2400      	movs	r4, #0
    7dcc:	e7e3      	b.n	7d96 <add_to_waitq_locked+0x1c>

00007dce <pend>:
{
    7dce:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    7dd2:	4605      	mov	r5, r0
    7dd4:	460f      	mov	r7, r1
    7dd6:	4691      	mov	r9, r2
    7dd8:	4698      	mov	r8, r3
	LOCKED(&sched_spinlock) {
    7dda:	2400      	movs	r4, #0
	__asm__ volatile(
    7ddc:	f04f 0320 	mov.w	r3, #32
    7de0:	f3ef 8611 	mrs	r6, BASEPRI
    7de4:	f383 8812 	msr	BASEPRI_MAX, r3
    7de8:	f3bf 8f6f 	isb	sy
    7dec:	b94c      	cbnz	r4, 7e02 <pend+0x34>
		add_to_waitq_locked(thread, wait_q);
    7dee:	4639      	mov	r1, r7
    7df0:	4628      	mov	r0, r5
    7df2:	f7ff ffc2 	bl	7d7a <add_to_waitq_locked>
	__asm__ volatile(
    7df6:	f386 8811 	msr	BASEPRI, r6
    7dfa:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
    7dfe:	2401      	movs	r4, #1
    7e00:	e7f4      	b.n	7dec <pend+0x1e>
	add_thread_timeout(thread, timeout);
    7e02:	464a      	mov	r2, r9
    7e04:	4643      	mov	r3, r8
    7e06:	4628      	mov	r0, r5
    7e08:	f7fd feea 	bl	5be0 <add_thread_timeout>
}
    7e0c:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}

00007e10 <z_unpend1_no_timeout>:
{
    7e10:	b570      	push	{r4, r5, r6, lr}
    7e12:	4606      	mov	r6, r0
	LOCKED(&sched_spinlock) {
    7e14:	2300      	movs	r3, #0
	__asm__ volatile(
    7e16:	f04f 0220 	mov.w	r2, #32
    7e1a:	f3ef 8511 	mrs	r5, BASEPRI
    7e1e:	f382 8812 	msr	BASEPRI_MAX, r2
    7e22:	f3bf 8f6f 	isb	sy
	struct k_thread *thread = NULL;
    7e26:	461c      	mov	r4, r3
    7e28:	e00f      	b.n	7e4a <z_unpend1_no_timeout+0x3a>
	_priq_wait_remove(&pended_on_thread(thread)->waitq, thread);
    7e2a:	f7ff ff07 	bl	7c3c <pended_on_thread>
    7e2e:	4621      	mov	r1, r4
    7e30:	f7ff ff44 	bl	7cbc <z_priq_dumb_remove>
	thread->base.thread_state &= ~_THREAD_PENDING;
    7e34:	7b63      	ldrb	r3, [r4, #13]
    7e36:	f023 0302 	bic.w	r3, r3, #2
    7e3a:	7363      	strb	r3, [r4, #13]
	thread->base.pended_on = NULL;
    7e3c:	2300      	movs	r3, #0
    7e3e:	60a3      	str	r3, [r4, #8]
	__asm__ volatile(
    7e40:	f385 8811 	msr	BASEPRI, r5
    7e44:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
    7e48:	2301      	movs	r3, #1
    7e4a:	b933      	cbnz	r3, 7e5a <z_unpend1_no_timeout+0x4a>
		thread = _priq_wait_best(&wait_q->waitq);
    7e4c:	4630      	mov	r0, r6
    7e4e:	f7ff ff3d 	bl	7ccc <z_priq_dumb_best>
		if (thread != NULL) {
    7e52:	4604      	mov	r4, r0
    7e54:	2800      	cmp	r0, #0
    7e56:	d1e8      	bne.n	7e2a <z_unpend1_no_timeout+0x1a>
    7e58:	e7f2      	b.n	7e40 <z_unpend1_no_timeout+0x30>
}
    7e5a:	4620      	mov	r0, r4
    7e5c:	bd70      	pop	{r4, r5, r6, pc}

00007e5e <z_unpend_first_thread>:
{
    7e5e:	b570      	push	{r4, r5, r6, lr}
    7e60:	4606      	mov	r6, r0
	LOCKED(&sched_spinlock) {
    7e62:	2300      	movs	r3, #0
	__asm__ volatile(
    7e64:	f04f 0220 	mov.w	r2, #32
    7e68:	f3ef 8511 	mrs	r5, BASEPRI
    7e6c:	f382 8812 	msr	BASEPRI_MAX, r2
    7e70:	f3bf 8f6f 	isb	sy
	struct k_thread *thread = NULL;
    7e74:	461c      	mov	r4, r3
    7e76:	e013      	b.n	7ea0 <z_unpend_first_thread+0x42>
	_priq_wait_remove(&pended_on_thread(thread)->waitq, thread);
    7e78:	f7ff fee0 	bl	7c3c <pended_on_thread>
    7e7c:	4621      	mov	r1, r4
    7e7e:	f7ff ff1d 	bl	7cbc <z_priq_dumb_remove>
    7e82:	7b63      	ldrb	r3, [r4, #13]
    7e84:	f023 0302 	bic.w	r3, r3, #2
    7e88:	7363      	strb	r3, [r4, #13]
	thread->base.pended_on = NULL;
    7e8a:	2300      	movs	r3, #0
    7e8c:	60a3      	str	r3, [r4, #8]
	return z_abort_timeout(&thread->base.timeout);
    7e8e:	f104 0018 	add.w	r0, r4, #24
    7e92:	f000 f85d 	bl	7f50 <z_abort_timeout>
	__asm__ volatile(
    7e96:	f385 8811 	msr	BASEPRI, r5
    7e9a:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
    7e9e:	2301      	movs	r3, #1
    7ea0:	b933      	cbnz	r3, 7eb0 <z_unpend_first_thread+0x52>
		thread = _priq_wait_best(&wait_q->waitq);
    7ea2:	4630      	mov	r0, r6
    7ea4:	f7ff ff12 	bl	7ccc <z_priq_dumb_best>
		if (thread != NULL) {
    7ea8:	4604      	mov	r4, r0
    7eaa:	2800      	cmp	r0, #0
    7eac:	d1e4      	bne.n	7e78 <z_unpend_first_thread+0x1a>
    7eae:	e7f2      	b.n	7e96 <z_unpend_first_thread+0x38>
}
    7eb0:	4620      	mov	r0, r4
    7eb2:	bd70      	pop	{r4, r5, r6, pc}

00007eb4 <z_sched_wake>:
{
    7eb4:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    7eb8:	4606      	mov	r6, r0
    7eba:	4688      	mov	r8, r1
    7ebc:	4617      	mov	r7, r2
	LOCKED(&sched_spinlock) {
    7ebe:	2300      	movs	r3, #0
	__asm__ volatile(
    7ec0:	f04f 0220 	mov.w	r2, #32
    7ec4:	f3ef 8511 	mrs	r5, BASEPRI
    7ec8:	f382 8812 	msr	BASEPRI_MAX, r2
    7ecc:	f3bf 8f6f 	isb	sy
	bool ret = false;
    7ed0:	4699      	mov	r9, r3
    7ed2:	e01b      	b.n	7f0c <z_sched_wake+0x58>
    7ed4:	f8c0 80ac 	str.w	r8, [r0, #172]	; 0xac
    7ed8:	6147      	str	r7, [r0, #20]
	_priq_wait_remove(&pended_on_thread(thread)->waitq, thread);
    7eda:	f7ff feaf 	bl	7c3c <pended_on_thread>
    7ede:	4621      	mov	r1, r4
    7ee0:	f7ff feec 	bl	7cbc <z_priq_dumb_remove>
    7ee4:	7b63      	ldrb	r3, [r4, #13]
    7ee6:	f023 0302 	bic.w	r3, r3, #2
    7eea:	7363      	strb	r3, [r4, #13]
	thread->base.pended_on = NULL;
    7eec:	2300      	movs	r3, #0
    7eee:	60a3      	str	r3, [r4, #8]
    7ef0:	f104 0018 	add.w	r0, r4, #24
    7ef4:	f000 f82c 	bl	7f50 <z_abort_timeout>
			ready_thread(thread);
    7ef8:	4620      	mov	r0, r4
    7efa:	f7fd ffbd 	bl	5e78 <ready_thread>
			ret = true;
    7efe:	f04f 0901 	mov.w	r9, #1
	__asm__ volatile(
    7f02:	f385 8811 	msr	BASEPRI, r5
    7f06:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
    7f0a:	2301      	movs	r3, #1
    7f0c:	b933      	cbnz	r3, 7f1c <z_sched_wake+0x68>
		thread = _priq_wait_best(&wait_q->waitq);
    7f0e:	4630      	mov	r0, r6
    7f10:	f7ff fedc 	bl	7ccc <z_priq_dumb_best>
		if (thread != NULL) {
    7f14:	4604      	mov	r4, r0
    7f16:	2800      	cmp	r0, #0
    7f18:	d1dc      	bne.n	7ed4 <z_sched_wake+0x20>
    7f1a:	e7f2      	b.n	7f02 <z_sched_wake+0x4e>
}
    7f1c:	4648      	mov	r0, r9
    7f1e:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}

00007f22 <remove_timeout>:
{
    7f22:	b538      	push	{r3, r4, r5, lr}
    7f24:	4604      	mov	r4, r0
	if (next(t) != NULL) {
    7f26:	f7fe fa8d 	bl	6444 <next>
    7f2a:	b148      	cbz	r0, 7f40 <remove_timeout+0x1e>
    7f2c:	4602      	mov	r2, r0
		next(t)->dticks += t->dticks;
    7f2e:	6920      	ldr	r0, [r4, #16]
    7f30:	6965      	ldr	r5, [r4, #20]
    7f32:	6913      	ldr	r3, [r2, #16]
    7f34:	6951      	ldr	r1, [r2, #20]
    7f36:	181b      	adds	r3, r3, r0
    7f38:	eb45 0101 	adc.w	r1, r5, r1
    7f3c:	6113      	str	r3, [r2, #16]
    7f3e:	6151      	str	r1, [r2, #20]
	sys_dnode_t *const prev = node->prev;
    7f40:	6862      	ldr	r2, [r4, #4]
	sys_dnode_t *const next = node->next;
    7f42:	6823      	ldr	r3, [r4, #0]
	prev->next = next;
    7f44:	6013      	str	r3, [r2, #0]
	next->prev = prev;
    7f46:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    7f48:	2300      	movs	r3, #0
    7f4a:	6023      	str	r3, [r4, #0]
	node->prev = NULL;
    7f4c:	6063      	str	r3, [r4, #4]
}
    7f4e:	bd38      	pop	{r3, r4, r5, pc}

00007f50 <z_abort_timeout>:
{
    7f50:	b570      	push	{r4, r5, r6, lr}
    7f52:	4604      	mov	r4, r0
	LOCKED(&timeout_lock) {
    7f54:	2300      	movs	r3, #0
	__asm__ volatile(
    7f56:	f04f 0220 	mov.w	r2, #32
    7f5a:	f3ef 8611 	mrs	r6, BASEPRI
    7f5e:	f382 8812 	msr	BASEPRI_MAX, r2
    7f62:	f3bf 8f6f 	isb	sy
	int ret = -EINVAL;
    7f66:	f06f 0015 	mvn.w	r0, #21
    7f6a:	e008      	b.n	7f7e <z_abort_timeout+0x2e>
			remove_timeout(to);
    7f6c:	4620      	mov	r0, r4
    7f6e:	f7ff ffd8 	bl	7f22 <remove_timeout>
			ret = 0;
    7f72:	4628      	mov	r0, r5
	__asm__ volatile(
    7f74:	f386 8811 	msr	BASEPRI, r6
    7f78:	f3bf 8f6f 	isb	sy
	LOCKED(&timeout_lock) {
    7f7c:	2301      	movs	r3, #1
    7f7e:	461d      	mov	r5, r3
    7f80:	b91b      	cbnz	r3, 7f8a <z_abort_timeout+0x3a>
	return node->next != NULL;
    7f82:	6823      	ldr	r3, [r4, #0]
		if (sys_dnode_is_linked(&to->node)) {
    7f84:	2b00      	cmp	r3, #0
    7f86:	d1f1      	bne.n	7f6c <z_abort_timeout+0x1c>
    7f88:	e7f4      	b.n	7f74 <z_abort_timeout+0x24>
}
    7f8a:	bd70      	pop	{r4, r5, r6, pc}

00007f8c <z_get_next_timeout_expiry>:
{
    7f8c:	b510      	push	{r4, lr}
	LOCKED(&timeout_lock) {
    7f8e:	2300      	movs	r3, #0
	__asm__ volatile(
    7f90:	f04f 0220 	mov.w	r2, #32
    7f94:	f3ef 8411 	mrs	r4, BASEPRI
    7f98:	f382 8812 	msr	BASEPRI_MAX, r2
    7f9c:	f3bf 8f6f 	isb	sy
	int32_t ret = (int32_t) K_TICKS_FOREVER;
    7fa0:	f04f 30ff 	mov.w	r0, #4294967295
	LOCKED(&timeout_lock) {
    7fa4:	b93b      	cbnz	r3, 7fb6 <z_get_next_timeout_expiry+0x2a>
		ret = next_timeout();
    7fa6:	f7fe fa65 	bl	6474 <next_timeout>
	__asm__ volatile(
    7faa:	f384 8811 	msr	BASEPRI, r4
    7fae:	f3bf 8f6f 	isb	sy
	LOCKED(&timeout_lock) {
    7fb2:	2301      	movs	r3, #1
    7fb4:	e7f6      	b.n	7fa4 <z_get_next_timeout_expiry+0x18>
}
    7fb6:	bd10      	pop	{r4, pc}

00007fb8 <z_set_timeout_expiry>:
{
    7fb8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    7fba:	4606      	mov	r6, r0
    7fbc:	460f      	mov	r7, r1
	LOCKED(&timeout_lock) {
    7fbe:	2300      	movs	r3, #0
	__asm__ volatile(
    7fc0:	f04f 0220 	mov.w	r2, #32
    7fc4:	f3ef 8511 	mrs	r5, BASEPRI
    7fc8:	f382 8812 	msr	BASEPRI_MAX, r2
    7fcc:	f3bf 8f6f 	isb	sy
    7fd0:	e00a      	b.n	7fe8 <z_set_timeout_expiry+0x30>
			      || (ticks <= next_to);
    7fd2:	2401      	movs	r4, #1
		bool sooner = (next_to == K_TICKS_FOREVER)
    7fd4:	f004 0401 	and.w	r4, r4, #1
		if (!imminent && (sooner || IS_ENABLED(CONFIG_SMP))) {
    7fd8:	2801      	cmp	r0, #1
    7fda:	dd00      	ble.n	7fde <z_set_timeout_expiry+0x26>
    7fdc:	b97c      	cbnz	r4, 7ffe <z_set_timeout_expiry+0x46>
	__asm__ volatile(
    7fde:	f385 8811 	msr	BASEPRI, r5
    7fe2:	f3bf 8f6f 	isb	sy
	LOCKED(&timeout_lock) {
    7fe6:	2301      	movs	r3, #1
    7fe8:	461c      	mov	r4, r3
    7fea:	b97b      	cbnz	r3, 800c <CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC+0xc>
		int next_to = next_timeout();
    7fec:	f7fe fa42 	bl	6474 <next_timeout>
			      || (ticks <= next_to);
    7ff0:	f1b0 3fff 	cmp.w	r0, #4294967295
    7ff4:	d0ed      	beq.n	7fd2 <z_set_timeout_expiry+0x1a>
    7ff6:	42b0      	cmp	r0, r6
    7ff8:	dbec      	blt.n	7fd4 <z_set_timeout_expiry+0x1c>
    7ffa:	2401      	movs	r4, #1
    7ffc:	e7ea      	b.n	7fd4 <z_set_timeout_expiry+0x1c>
			sys_clock_set_timeout(MIN(ticks, next_to), is_idle);
    7ffe:	4639      	mov	r1, r7
    8000:	42b0      	cmp	r0, r6
    8002:	bfa8      	it	ge
    8004:	4630      	movge	r0, r6
    8006:	f7fc fa37 	bl	4478 <sys_clock_set_timeout>
    800a:	e7e8      	b.n	7fde <z_set_timeout_expiry+0x26>
}
    800c:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}

0000800e <sys_clock_tick_get_32>:

uint32_t sys_clock_tick_get_32(void)
{
    800e:	b508      	push	{r3, lr}
#ifdef CONFIG_TICKLESS_KERNEL
	return (uint32_t)sys_clock_tick_get();
    8010:	f7fe fb62 	bl	66d8 <sys_clock_tick_get>
#else
	return (uint32_t)curr_tick;
#endif
}
    8014:	bd08      	pop	{r3, pc}

00008016 <z_impl_k_busy_wait>:
#endif

void z_impl_k_busy_wait(uint32_t usec_to_wait)
{
	SYS_PORT_TRACING_FUNC_ENTER(k_thread, busy_wait, usec_to_wait);
	if (usec_to_wait == 0U) {
    8016:	b900      	cbnz	r0, 801a <z_impl_k_busy_wait+0x4>
    8018:	4770      	bx	lr
{
    801a:	b508      	push	{r3, lr}
		if ((current_cycles - start_cycles) >= cycles_to_wait) {
			break;
		}
	}
#else
	arch_busy_wait(usec_to_wait);
    801c:	f7fa ff12 	bl	2e44 <arch_busy_wait>
#endif /* CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT */
	SYS_PORT_TRACING_FUNC_EXIT(k_thread, busy_wait, usec_to_wait);
}
    8020:	bd08      	pop	{r3, pc}

00008022 <k_timer_init>:
	timer->expiry_fn = expiry_fn;
    8022:	6201      	str	r1, [r0, #32]
	timer->stop_fn = stop_fn;
    8024:	6242      	str	r2, [r0, #36]	; 0x24
	timer->status = 0U;
    8026:	2300      	movs	r3, #0
    8028:	6303      	str	r3, [r0, #48]	; 0x30
	sys_dlist_init(&w->waitq);
    802a:	f100 0218 	add.w	r2, r0, #24
	list->head = (sys_dnode_t *)list;
    802e:	6182      	str	r2, [r0, #24]
	list->tail = (sys_dnode_t *)list;
    8030:	61c2      	str	r2, [r0, #28]
	node->next = NULL;
    8032:	6003      	str	r3, [r0, #0]
	node->prev = NULL;
    8034:	6043      	str	r3, [r0, #4]
	timer->user_data = NULL;
    8036:	6343      	str	r3, [r0, #52]	; 0x34
}
    8038:	4770      	bx	lr

0000803a <z_impl_k_timer_stop>:
}
#include <syscalls/k_timer_start_mrsh.c>
#endif

void z_impl_k_timer_stop(struct k_timer *timer)
{
    803a:	b510      	push	{r4, lr}
    803c:	4604      	mov	r4, r0
	SYS_PORT_TRACING_OBJ_FUNC(k_timer, stop, timer);

	int inactive = z_abort_timeout(&timer->timeout) != 0;
    803e:	f7ff ff87 	bl	7f50 <z_abort_timeout>

	if (inactive) {
    8042:	b9a0      	cbnz	r0, 806e <z_impl_k_timer_stop+0x34>
		return;
	}

	if (timer->stop_fn != NULL) {
    8044:	6a63      	ldr	r3, [r4, #36]	; 0x24
    8046:	b10b      	cbz	r3, 804c <z_impl_k_timer_stop+0x12>
		timer->stop_fn(timer);
    8048:	4620      	mov	r0, r4
    804a:	4798      	blx	r3
	}

	if (IS_ENABLED(CONFIG_MULTITHREADING)) {
		struct k_thread *pending_thread = z_unpend1_no_timeout(&timer->wait_q);
    804c:	f104 0018 	add.w	r0, r4, #24
    8050:	f7ff fede 	bl	7e10 <z_unpend1_no_timeout>

		if (pending_thread != NULL) {
    8054:	b158      	cbz	r0, 806e <z_impl_k_timer_stop+0x34>
			z_ready_thread(pending_thread);
    8056:	f7ff fe40 	bl	7cda <z_ready_thread>
	__asm__ volatile(
    805a:	f04f 0320 	mov.w	r3, #32
    805e:	f3ef 8011 	mrs	r0, BASEPRI
    8062:	f383 8812 	msr	BASEPRI_MAX, r3
    8066:	f3bf 8f6f 	isb	sy
	(void) z_reschedule_irqlock(arch_irq_lock());
    806a:	f7ff fe12 	bl	7c92 <z_reschedule_irqlock>
			z_reschedule_unlocked();
		}
	}
}
    806e:	bd10      	pop	{r4, pc}

00008070 <_OffsetAbsSyms>:

#include <gen_offset.h>

#include "offsets_aarch32.c"

GEN_ABS_SYM_END
    8070:	4770      	bx	lr

00008072 <abs>:
    8072:	2800      	cmp	r0, #0
    8074:	bfb8      	it	lt
    8076:	4240      	neglt	r0, r0
    8078:	4770      	bx	lr

0000807a <memcpy>:
    807a:	440a      	add	r2, r1
    807c:	4291      	cmp	r1, r2
    807e:	f100 33ff 	add.w	r3, r0, #4294967295
    8082:	d100      	bne.n	8086 <memcpy+0xc>
    8084:	4770      	bx	lr
    8086:	b510      	push	{r4, lr}
    8088:	f811 4b01 	ldrb.w	r4, [r1], #1
    808c:	f803 4f01 	strb.w	r4, [r3, #1]!
    8090:	4291      	cmp	r1, r2
    8092:	d1f9      	bne.n	8088 <memcpy+0xe>
    8094:	bd10      	pop	{r4, pc}

00008096 <memset>:
    8096:	4402      	add	r2, r0
    8098:	4603      	mov	r3, r0
    809a:	4293      	cmp	r3, r2
    809c:	d100      	bne.n	80a0 <memset+0xa>
    809e:	4770      	bx	lr
    80a0:	f803 1b01 	strb.w	r1, [r3], #1
    80a4:	e7f9      	b.n	809a <memset+0x4>

000080a6 <strncpy>:
    80a6:	b510      	push	{r4, lr}
    80a8:	3901      	subs	r1, #1
    80aa:	4603      	mov	r3, r0
    80ac:	b132      	cbz	r2, 80bc <strncpy+0x16>
    80ae:	f811 4f01 	ldrb.w	r4, [r1, #1]!
    80b2:	f803 4b01 	strb.w	r4, [r3], #1
    80b6:	3a01      	subs	r2, #1
    80b8:	2c00      	cmp	r4, #0
    80ba:	d1f7      	bne.n	80ac <strncpy+0x6>
    80bc:	441a      	add	r2, r3
    80be:	2100      	movs	r1, #0
    80c0:	4293      	cmp	r3, r2
    80c2:	d100      	bne.n	80c6 <strncpy+0x20>
    80c4:	bd10      	pop	{r4, pc}
    80c6:	f803 1b01 	strb.w	r1, [r3], #1
    80ca:	e7f9      	b.n	80c0 <strncpy+0x1a>

000080cc <strnlen>:
    80cc:	b510      	push	{r4, lr}
    80ce:	4602      	mov	r2, r0
    80d0:	4401      	add	r1, r0
    80d2:	428a      	cmp	r2, r1
    80d4:	4613      	mov	r3, r2
    80d6:	d101      	bne.n	80dc <strnlen+0x10>
    80d8:	1a18      	subs	r0, r3, r0
    80da:	bd10      	pop	{r4, pc}
    80dc:	781c      	ldrb	r4, [r3, #0]
    80de:	3201      	adds	r2, #1
    80e0:	2c00      	cmp	r4, #0
    80e2:	d1f6      	bne.n	80d2 <strnlen+0x6>
    80e4:	e7f8      	b.n	80d8 <strnlen+0xc>
	...

000080e8 <z_arm_platform_init>:
	 */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r0, =SystemInit
	bx r0
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	b SystemInit
    80e8:	f7fc ba6a 	b.w	45c0 <SystemInit>
