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fixed_armv5e.h
1 /* Copyright (C) 2007-2009 Xiph.Org Foundation
2  Copyright (C) 2003-2008 Jean-Marc Valin
3  Copyright (C) 2007-2008 CSIRO
4  Copyright (C) 2013 Parrot */
5 /*
6  Redistribution and use in source and binary forms, with or without
7  modification, are permitted provided that the following conditions
8  are met:
9 
10  - Redistributions of source code must retain the above copyright
11  notice, this list of conditions and the following disclaimer.
12 
13  - Redistributions in binary form must reproduce the above copyright
14  notice, this list of conditions and the following disclaimer in the
15  documentation and/or other materials provided with the distribution.
16 
17  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18  ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
21  OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
22  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
23  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
24  PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
25  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
26  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
27  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29 
30 #ifndef FIXED_ARMv5E_H
31 #define FIXED_ARMv5E_H
32 
33 #include "fixed_armv4.h"
34 
36 #undef MULT16_32_Q16
37 static OPUS_INLINE opus_val32 MULT16_32_Q16_armv5e(opus_val16 a, opus_val32 b)
38 {
39  int res;
40 
41 #if defined( __CC_ARM )
42  __asm{ SMULWB res, b, a }
43 #elif defined( __ICCARM__ )
44  __asm(
45  "smulwb %0, %1, %2\n\t"
46  : "=r"(res)
47  : "r"(b),"r"(a)
48  );
49 #else
50  __asm__(
51  "#MULT16_32_Q16\n\t"
52  "smulwb %0, %1, %2\n\t"
53  : "=r"(res)
54  : "r"(b),"r"(a)
55  );
56 #endif
57 
58  return res;
59 }
60 #define MULT16_32_Q16(a, b) (MULT16_32_Q16_armv5e(a, b))
61 
62 
64 #undef MULT16_32_Q15
65 static OPUS_INLINE opus_val32 MULT16_32_Q15_armv5e(opus_val16 a, opus_val32 b)
66 {
67  int res;
68 
69 #if defined( __CC_ARM )
70  __asm{ SMULWB res, b, a }
71 #elif defined( __ICCARM__ )
72  __asm(
73  "smulwb %0, %1, %2\n\t"
74  : "=r"(res)
75  : "r"(b), "r"(a)
76  );
77 #else
78  __asm__(
79  "#MULT16_32_Q15\n\t"
80  "smulwb %0, %1, %2\n\t"
81  : "=r"(res)
82  : "r"(b), "r"(a)
83  );
84 #endif
85 
86  return SHL32(res,1);
87 }
88 #define MULT16_32_Q15(a, b) (MULT16_32_Q15_armv5e(a, b))
89 
90 
94 #undef MAC16_32_Q15
95 static OPUS_INLINE opus_val32 MAC16_32_Q15_armv5e(opus_val32 c, opus_val16 a,
96  opus_val32 b)
97 {
98  int res;
99 
100 #if defined( __CC_ARM )
101  __asm{ SMLAWB res, (SHL32(b,1)), a, c }
102 #elif defined( __ICCARM__ )
103  __asm(
104  "smlawb %0, %1, %2, %3;\n"
105  : "=r"(res)
106  : "r"(SHL32(b,1)), "r"(a), "r"(c)
107  );
108 #else
109  __asm__(
110  "#MAC16_32_Q15\n\t"
111  "smlawb %0, %1, %2, %3;\n"
112  : "=r"(res)
113  : "r"(SHL32(b,1)), "r"(a), "r"(c)
114  );
115 #endif
116 
117  return res;
118 }
119 #define MAC16_32_Q15(c, a, b) (MAC16_32_Q15_armv5e(c, a, b))
120 
123 #undef MAC16_32_Q16
124 static OPUS_INLINE opus_val32 MAC16_32_Q16_armv5e(opus_val32 c, opus_val16 a,
125  opus_val32 b)
126 {
127  int res;
128 
129 #if defined( __CC_ARM )
130  __asm{ SMLAWB res, b, a, c }
131 #elif defined( __ICCARM__ )
132  __asm(
133  "smlawb %0, %1, %2, %3;\n"
134  : "=r"(res)
135  : "r"(b), "r"(a), "r"(c)
136  );
137 #else
138  __asm__(
139  "#MAC16_32_Q16\n\t"
140  "smlawb %0, %1, %2, %3;\n"
141  : "=r"(res)
142  : "r"(b), "r"(a), "r"(c)
143  );
144 #endif
145 
146  return res;
147 }
148 #define MAC16_32_Q16(c, a, b) (MAC16_32_Q16_armv5e(c, a, b))
149 
151 #undef MAC16_16
152 static OPUS_INLINE opus_val32 MAC16_16_armv5e(opus_val32 c, opus_val16 a,
153  opus_val16 b)
154 {
155  int res;
156 
157 #if defined( __CC_ARM )
158  __asm{ SMLABB res, a, b, c }
159 #elif defined( __ICCARM__ )
160  __asm(
161  "smlabb %0, %1, %2, %3;\n"
162  : "=r"(res)
163  : "r"(a), "r"(b), "r"(c)
164  );
165 #else
166  __asm__(
167  "#MAC16_16\n\t"
168  "smlabb %0, %1, %2, %3;\n"
169  : "=r"(res)
170  : "r"(a), "r"(b), "r"(c)
171  );
172 #endif
173 
174  return res;
175 }
176 #define MAC16_16(c, a, b) (MAC16_16_armv5e(c, a, b))
177 
179 #undef MULT16_16
180 static OPUS_INLINE opus_val32 MULT16_16_armv5e(opus_val16 a, opus_val16 b)
181 {
182  int res;
183 #if defined( __CC_ARM )
184  __asm{ SMULBB res, a, b }
185 #elif defined( __ICCARM__ )
186  __asm(
187  "smulbb %0, %1, %2;\n"
188  : "=r"(res)
189  : "r"(a), "r"(b)
190  );
191 #else
192  __asm__(
193  "#MULT16_16\n\t"
194  "smulbb %0, %1, %2;\n"
195  : "=r"(res)
196  : "r"(a), "r"(b)
197  );
198 #endif
199 
200  return res;
201 }
202 #define MULT16_16(a, b) (MULT16_16_armv5e(a, b))
203 
204 #ifdef OPUS_ARM_INLINE_MEDIA
205 
206 #undef SIG2WORD16
207 static OPUS_INLINE opus_val16 SIG2WORD16_armv6(opus_val32 x)
208 {
209  celt_sig res;
210 
211 #if defined( __CC_ARM )
212  __asm{ SSAT res, 16, (x+2048), ASR 12 }
213 #elif defined( __ICCARM__ )
214  __asm(
215  "ssat %0, #16, %1, ASR #12\n\t"
216  : "=r"(res)
217  : "r"(x+2048)
218  );
219 #else
220  __asm__(
221  "#SIG2WORD16\n\t"
222  "ssat %0, #16, %1, ASR #12\n\t"
223  : "=r"(res)
224  : "r"(x+2048)
225  );
226 #endif
227 
228  return EXTRACT16(res);
229 }
230 #define SIG2WORD16(x) (SIG2WORD16_armv6(x))
231 
232 #endif /* OPUS_ARM_INLINE_MEDIA */
233 
234 #endif