29 #ifndef SILK_MACROS_ARMv5E_H
30 #define SILK_MACROS_ARMv5E_H
35 #define SAFE_SHL(a,b) ((opus_int32)((opus_uint32)(a) << (b)))
39 static OPUS_INLINE opus_int32 silk_SMULWB_armv5e(opus_int32 a, opus_int16 b)
43 #if defined( __CC_ARM )
44 __asm{ SMULWB res, a, b }
45 #elif defined( __ICCARM__ )
47 "smulwb %0, %1, %2\n\t"
54 "smulwb %0, %1, %2\n\t"
62 #define silk_SMULWB(a, b) (silk_SMULWB_armv5e(a, b))
66 static OPUS_INLINE opus_int32 silk_SMLAWB_armv5e(opus_int32 a, opus_int32 b,
71 #if defined( __CC_ARM )
72 __asm{ SMLAWB res, b, c, a }
73 #elif defined( __ICCARM__ )
75 "smlawb %0, %1, %2, %3\n\t"
77 :
"r"(b),
"r"(c),
"r"(a)
82 "smlawb %0, %1, %2, %3\n\t"
84 :
"r"(b),
"r"(c),
"r"(a)
90 #define silk_SMLAWB(a, b, c) (silk_SMLAWB_armv5e(a, b, c))
94 static OPUS_INLINE opus_int32 silk_SMULWT_armv5e(opus_int32 a, opus_int32 b)
98 #if defined( __CC_ARM )
99 __asm{ SMULWT res, a, b }
100 #elif defined( __ICCARM__ )
102 "smulwt %0, %1, %2\n\t"
109 "smulwt %0, %1, %2\n\t"
117 #define silk_SMULWT(a, b) (silk_SMULWT_armv5e(a, b))
121 static OPUS_INLINE opus_int32 silk_SMLAWT_armv5e(opus_int32 a, opus_int32 b,
126 #if defined( __CC_ARM )
127 __asm{ SMLAWT res, b, c, a }
128 #elif defined( __ICCARM__ )
130 "smlawt %0, %1, %2, %3\n\t"
132 :
"r"(b),
"r"(c),
"r"(a)
137 "smlawt %0, %1, %2, %3\n\t"
139 :
"r"(b),
"r"(c),
"r"(a)
145 #define silk_SMLAWT(a, b, c) (silk_SMLAWT_armv5e(a, b, c))
149 static OPUS_INLINE opus_int32 silk_SMULBB_armv5e(opus_int32 a, opus_int32 b)
153 #if defined( __CC_ARM )
154 __asm{ SMULBB res, a, b }
155 #elif defined( __ICCARM__ )
157 "smulbb %0, %1, %2\n\t"
164 "smulbb %0, %1, %2\n\t"
172 #define silk_SMULBB(a, b) (silk_SMULBB_armv5e(a, b))
176 static OPUS_INLINE opus_int32 silk_SMLABB_armv5e(opus_int32 a, opus_int32 b,
181 #if defined( __CC_ARM )
182 __asm{ SMLABB res, b, c, a }
183 #elif defined( __ICCARM__ )
185 "smlabb %0, %1, %2, %3\n\t"
187 :
"r"(b),
"r"(c),
"r"(a)
192 "smlabb %0, %1, %2, %3\n\t"
194 :
"%r"(b),
"r"(c),
"r"(a)
200 #define silk_SMLABB(a, b, c) (silk_SMLABB_armv5e(a, b, c))
204 static OPUS_INLINE opus_int32 silk_SMULBT_armv5e(opus_int32 a, opus_int32 b)
207 #if defined( __CC_ARM )
208 __asm{ SMULBT res, a, b }
209 #elif defined( __ICCARM__ )
211 "smulbt %0, %1, %2\n\t"
218 "smulbt %0, %1, %2\n\t"
225 #define silk_SMULBT(a, b) (silk_SMULBT_armv5e(a, b))
229 static OPUS_INLINE opus_int32 silk_SMLABT_armv5e(opus_int32 a, opus_int32 b,
233 #if defined( __CC_ARM )
234 __asm{ SMLABT res, b, c, a }
235 #elif defined( __ICCARM__ )
237 "smlabt %0, %1, %2, %3\n\t"
239 :
"r"(b),
"r"(c),
"r"(a)
244 "smlabt %0, %1, %2, %3\n\t"
246 :
"r"(b),
"r"(c),
"r"(a)
252 #define silk_SMLABT(a, b, c) (silk_SMLABT_armv5e(a, b, c))
255 #undef silk_ADD_SAT32
256 static OPUS_INLINE opus_int32 silk_ADD_SAT32_armv5e(opus_int32 a, opus_int32 b)
260 #if defined( __CC_ARM )
261 __asm{ QADD res, a, b }
262 #elif defined( __ICCARM__ )
264 "qadd %0, %1, %2\n\t"
270 "#silk_ADD_SAT32\n\t"
271 "qadd %0, %1, %2\n\t"
279 #define silk_ADD_SAT32(a, b) (silk_ADD_SAT32_armv5e(a, b))
281 #undef silk_SUB_SAT32
282 static OPUS_INLINE opus_int32 silk_SUB_SAT32_armv5e(opus_int32 a, opus_int32 b)
286 #if defined( __CC_ARM )
287 __asm{ QSUB res, a, b }
288 #elif defined( __ICCARM__ )
290 "qsub %0, %1, %2\n\t"
296 "#silk_SUB_SAT32\n\t"
297 "qsub %0, %1, %2\n\t"
305 #define silk_SUB_SAT32(a, b) (silk_SUB_SAT32_armv5e(a, b))
308 static OPUS_INLINE opus_int32 silk_CLZ16_armv5(opus_int16 in16)
312 #if defined( __CC_ARM )
313 __asm{ CLZ res, (SAFE_SHL(in16,16)|0x8000) }
314 #elif defined( __ICCARM__ )
318 :
"r"(SAFE_SHL(in16,16)|0x8000)
325 :
"r"(SAFE_SHL(in16,16)|0x8000)
331 #define silk_CLZ16(in16) (silk_CLZ16_armv5(in16))
334 static OPUS_INLINE opus_int32 silk_CLZ32_armv5(opus_int32 in32)
337 #if defined( __CC_ARM )
338 __asm{ CLZ res, in32 }
339 #elif defined( __ICCARM__ )
356 #define silk_CLZ32(in32) (silk_CLZ32_armv5(in32))