32 static OPUS_INLINE opus_val32 MULT16_32_Q16_armv4(opus_val16 a, opus_val32 b)
37 #if defined( __CC_ARM )
38 __asm{ SMULL rd_lo, rd_hi, b, (SHL32(a,16)) }
39 #elif defined( __ICCARM__ )
41 "smull %0, %1, %2, %3\n\t"
42 :
"=&r"(rd_lo),
"=&r"(rd_hi)
43 :
"r"(b),
"r"(SHL32(a,16))
49 "smull %0, %1, %2, %3\n\t"
50 :
"=&r"(rd_lo),
"=&r"(rd_hi)
51 :
"%r"(b),
"r"(SHL32(a,16))
57 #define MULT16_32_Q16(a, b) (MULT16_32_Q16_armv4(a, b))
62 static OPUS_INLINE opus_val32 MULT16_32_Q15_armv4(opus_val16 a, opus_val32 b)
67 #if defined( __CC_ARM )
68 __asm{ SMULL rd_lo, rd_hi, b, (SHL32(a,16)) }
69 #elif defined( __ICCARM__ )
71 "smull %0, %1, %2, %3\n\t"
72 :
"=&r"(rd_lo),
"=&r"(rd_hi)
73 :
"r"(b),
"r"(SHL32(a,16))
79 "smull %0, %1, %2, %3\n\t"
80 :
"=&r"(rd_lo),
"=&r"(rd_hi)
81 :
"%r"(b),
"r"(SHL32(a,16))
86 return SHL32(rd_hi,1);
88 #define MULT16_32_Q15(a, b) (MULT16_32_Q15_armv4(a, b))
95 #define MAC16_32_Q15(c, a, b) ADD32(c, MULT16_32_Q15(a, b))
100 #define MAC16_32_Q16(c, a, b) ADD32(c, MULT16_32_Q16(a, b))
104 #define MULT32_32_Q31(a,b) (opus_val32)((((opus_int64)(a)) * ((opus_int64)(b)))>>31)