28 #ifndef SILK_MACROS_ARMv4_H
29 #define SILK_MACROS_ARMv4_H
34 #define SAFE_SHL(a,b) ((opus_int32)((opus_uint32)(a) << (b)))
38 static OPUS_INLINE opus_int32 silk_SMULWB_armv4(opus_int32 a, opus_int16 b)
43 #if defined( __CC_ARM )
44 __asm{ SMULL rd_lo, rd_hi, a, (SAFE_SHL(b,16)) }
45 #elif defined( __ICCARM__ )
47 "smull %0, %1, %2, %3\n\t"
48 :
"=&r"(rd_lo),
"=&r"(rd_hi)
49 :
"r"(a),
"r"(SAFE_SHL(b,16))
55 "smull %0, %1, %2, %3\n\t"
56 :
"=&r"(rd_lo),
"=&r"(rd_hi)
57 :
"%r"(a),
"r"(SAFE_SHL(b,16))
63 #define silk_SMULWB(a, b) (silk_SMULWB_armv4(a, b))
67 #define silk_SMLAWB(a, b, c) ((a) + silk_SMULWB(b, c))
71 static OPUS_INLINE opus_int32 silk_SMULWT_armv4(opus_int32 a, opus_int32 b)
76 #if defined( __CC_ARM )
77 __asm{ SMULL rd_lo, rd_hi, a, (b&~0xFFFF) }
78 #elif defined( __ICCARM__ )
80 "smull %0, %1, %2, %3\n\t"
81 :
"=&r"(rd_lo),
"=&r"(rd_hi)
82 :
"r"(a),
"r"(b&~0xFFFF)
88 "smull %0, %1, %2, %3\n\t"
89 :
"=&r"(rd_lo),
"=&r"(rd_hi)
90 :
"%r"(a),
"r"(b&~0xFFFF)
96 #define silk_SMULWT(a, b) (silk_SMULWT_armv4(a, b))
100 #define silk_SMLAWT(a, b, c) ((a) + silk_SMULWT(b, c))
104 static OPUS_INLINE opus_int32 silk_SMULWW_armv4(opus_int32 a, opus_int32 b)
109 #if defined( __CC_ARM )
110 __asm{ SMULL rd_lo, rd_hi, a, b }
111 #elif defined( __ICCARM__ )
113 "smull %0, %1, %2, %3\n\t"
114 :
"=&r"(rd_lo),
"=&r"(rd_hi)
120 "smull %0, %1, %2, %3\n\t"
121 :
"=&r"(rd_lo),
"=&r"(rd_hi)
125 return SAFE_SHL(rd_hi,16)+(rd_lo>>16);
127 #define silk_SMULWW(a, b) (silk_SMULWW_armv4(a, b))
130 static OPUS_INLINE opus_int32 silk_SMLAWW_armv4(opus_int32 a, opus_int32 b,
136 #if defined( __CC_ARM )
137 __asm{ SMULL rd_lo, rd_hi, b, c }
138 #elif defined( __ICCARM__ )
140 "smull %0, %1, %2, %3\n\t"
141 :
"=&r"(rd_lo),
"=&r"(rd_hi)
147 "smull %0, %1, %2, %3\n\t"
148 :
"=&r"(rd_lo),
"=&r"(rd_hi)
153 return a+SAFE_SHL(rd_hi,16)+(rd_lo>>16);
155 #define silk_SMLAWW(a, b, c) (silk_SMLAWW_armv4(a, b, c))