/ {
	chosen {
		nordic,pm-ext-flash = &mx25r64;
	};
};

/ {
	soc {
		/* Add a flash controller which has the compatible
		 * 'zephyr,sim-flash'. This will ensure that the flash
		 * simulator can use it. None of the other properties in this
		 * node is used for anything.
		 */
		nordic_ram_flash_controller: nordic_ram-flash-controller@0 {
			compatible = "zephyr,sim-flash";
			reg = <0x00000000 DT_SIZE_K(40)>;
			#address-cells = <1>;
			#size-cells = <1>;
			erase-value = <0xff>;
			label = "nordic_ram_flash_flash_controller";

			/* This node label must match that used in the flash
			 * simulator.
			 */
			flash_sim0: flash_sim@0 {
				status = "okay";
				compatible = "soc-nv-flash";
				label = "simulated_flash";
				erase-block-size = <4096>;
				write-block-size = <4>;
				reg = <0x00000000 DT_SIZE_K(256)>;

				partitions {
					compatible = "fixed-partitions";
					#address-cells = <1>;
					#size-cells = <1>;

					/* This partition must be defined for
					 * MCUboot to find the partition ID
					 * of the primary slot for image 1,
					 * which is stored in this partition.
					 */
					slot2_partition: partition@0 {
						label = "image-2";
						reg = <0x00000000 0x00000A000>;
					};
				};
			};
		};
	};
};

&qspi {
	status = "disabled";
};

&spi4 {
	cs-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>, <&gpio0 17 GPIO_ACTIVE_LOW>, < &gpio1 10 GPIO_ACTIVE_LOW >;
	status = "okay";
	sdhc0: sdhc@0 {
		status = "okay";
	};
	cs47l63: cs47l63@1 {
		status = "okay";
	};
	mx25r64: mx25r6435f@2 {

		compatible = "jedec,spi-nor";
		reg = <2>;
		spi-max-frequency = <8000000>;

		label = "MX25R64";
		jedec-id = [c2 28 17];
		sfdp-bfp = [
			e5 20 f1 ff  ff ff ff 03  44 eb 08 6b  08 3b 04 bb
			ee ff ff ff  ff ff 00 ff  ff ff 00 ff  0c 20 0f 52
			10 d8 00 ff  23 72 f5 00  82 ed 04 cc  44 83 68 44
			30 b0 30 b0  f7 c4 d5 5c  00 be 29 ff  f0 d0 ff ff
		];
		size = <67108864>;
		has-dpd;
		t-enter-dpd = <10000>;
		t-exit-dpd = <5000>;
		dpd-wakeup-sequence = <30000 20 45000>;
	};
};

&gpio_fwd {
	uart {
		gpios = < &gpio1 0x9 0x0 >, < &gpio1 0x8 0x0 >, < &gpio1 0xb 0x0 >;
	};
};
