# 1 "C:/nrfconnectsdk/v2.1.2/zephyr/misc/empty_file.c"
# 1 "<built-in>"
# 1 "<command-line>"
# 1 "C:/nrfconnectsdk/v2.1.2/nrf/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp.dts" 1






/dts-v1/;
# 1 "C:/nrfconnectsdk/v2.1.2/zephyr/dts/arm/nordic/nrf5340_cpuapp_qkaa.dtsi" 1 3 4






# 1 "C:/nrfconnectsdk/v2.1.2/zephyr/dts/common/mem.h" 1 3 4
# 8 "C:/nrfconnectsdk/v2.1.2/zephyr/dts/arm/nordic/nrf5340_cpuapp_qkaa.dtsi" 2 3 4
# 1 "C:/nrfconnectsdk/v2.1.2/zephyr/dts/arm/nordic/nrf5340_cpuapp.dtsi" 1 3 4






# 1 "C:/nrfconnectsdk/v2.1.2/zephyr/dts/arm/armv8-m.dtsi" 1 3 4


# 1 "C:/nrfconnectsdk/v2.1.2/zephyr/dts/common/skeleton.dtsi" 1 3 4
# 9 "C:/nrfconnectsdk/v2.1.2/zephyr/dts/common/skeleton.dtsi" 3 4
/ {
 #address-cells = <1>;
 #size-cells = <1>;
 chosen { };
 aliases { };
};
# 4 "C:/nrfconnectsdk/v2.1.2/zephyr/dts/arm/armv8-m.dtsi" 2 3 4

/ {
 soc {
  #address-cells = <1>;
  #size-cells = <1>;
  compatible = "simple-bus";
  interrupt-parent = <&nvic>;
  ranges;

  nvic: interrupt-controller@e000e100 {
   #address-cells = <1>;
   compatible = "arm,v8m-nvic";
   reg = <0xe000e100 0xc00>;
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  systick: timer@e000e010 {
   compatible = "arm,armv8m-systick";
   reg = <0xe000e010 0x10>;
  };
 };
};
# 8 "C:/nrfconnectsdk/v2.1.2/zephyr/dts/arm/nordic/nrf5340_cpuapp.dtsi" 2 3 4
# 1 "C:/nrfconnectsdk/v2.1.2/zephyr/dts/arm/nordic/nrf_common.dtsi" 1 3 4






# 1 "C:/nrfconnectsdk/v2.1.2/zephyr/include/zephyr/dt-bindings/adc/adc.h" 1 3 4
# 8 "C:/nrfconnectsdk/v2.1.2/zephyr/dts/arm/nordic/nrf_common.dtsi" 2 3 4
# 1 "C:/nrfconnectsdk/v2.1.2/zephyr/include/zephyr/dt-bindings/adc/nrf-adc.h" 1 3 4
# 10 "C:/nrfconnectsdk/v2.1.2/zephyr/include/zephyr/dt-bindings/adc/nrf-adc.h" 3 4
# 1 "C:/nrfconnectsdk/v2.1.2/zephyr/include/zephyr/dt-bindings/dt-util.h" 1 3 4
# 19 "C:/nrfconnectsdk/v2.1.2/zephyr/include/zephyr/dt-bindings/dt-util.h" 3 4
# 1 "C:/nrfconnectsdk/v2.1.2/zephyr/include/zephyr/sys/util_macro.h" 1 3 4
# 34 "C:/nrfconnectsdk/v2.1.2/zephyr/include/zephyr/sys/util_macro.h" 3 4
# 1 "C:/nrfconnectsdk/v2.1.2/zephyr/include/zephyr/sys/util_internal.h" 1 3 4
# 18 "C:/nrfconnectsdk/v2.1.2/zephyr/include/zephyr/sys/util_internal.h" 3 4
# 1 "C:/nrfconnectsdk/v2.1.2/zephyr/include/zephyr/sys/util_loops.h" 1 3 4
# 19 "C:/nrfconnectsdk/v2.1.2/zephyr/include/zephyr/sys/util_internal.h" 2 3 4
# 35 "C:/nrfconnectsdk/v2.1.2/zephyr/include/zephyr/sys/util_macro.h" 2 3 4
# 20 "C:/nrfconnectsdk/v2.1.2/zephyr/include/zephyr/dt-bindings/dt-util.h" 2 3 4
# 11 "C:/nrfconnectsdk/v2.1.2/zephyr/include/zephyr/dt-bindings/adc/nrf-adc.h" 2 3 4
# 9 "C:/nrfconnectsdk/v2.1.2/zephyr/dts/arm/nordic/nrf_common.dtsi" 2 3 4
# 1 "C:/nrfconnectsdk/v2.1.2/zephyr/include/zephyr/dt-bindings/gpio/gpio.h" 1 3 4
# 10 "C:/nrfconnectsdk/v2.1.2/zephyr/dts/arm/nordic/nrf_common.dtsi" 2 3 4
# 1 "C:/nrfconnectsdk/v2.1.2/zephyr/include/zephyr/dt-bindings/i2c/i2c.h" 1 3 4
# 11 "C:/nrfconnectsdk/v2.1.2/zephyr/dts/arm/nordic/nrf_common.dtsi" 2 3 4
# 1 "C:/nrfconnectsdk/v2.1.2/zephyr/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h" 1 3 4
# 12 "C:/nrfconnectsdk/v2.1.2/zephyr/dts/arm/nordic/nrf_common.dtsi" 2 3 4
# 1 "C:/nrfconnectsdk/v2.1.2/zephyr/include/zephyr/dt-bindings/pwm/pwm.h" 1 3 4
# 13 "C:/nrfconnectsdk/v2.1.2/zephyr/dts/arm/nordic/nrf_common.dtsi" 2 3 4

# 1 "C:/nrfconnectsdk/v2.1.2/zephyr/dts/common/freq.h" 1 3 4
# 15 "C:/nrfconnectsdk/v2.1.2/zephyr/dts/arm/nordic/nrf_common.dtsi" 2 3 4
# 1 "C:/nrfconnectsdk/v2.1.2/zephyr/dts/arm/nordic/override.dtsi" 1 3 4
# 16 "C:/nrfconnectsdk/v2.1.2/zephyr/dts/arm/nordic/nrf_common.dtsi" 2 3 4
# 24 "C:/nrfconnectsdk/v2.1.2/zephyr/dts/arm/nordic/nrf_common.dtsi" 3 4
/ {
 pinctrl: pin-controller {




  compatible = "nordic,nrf-pinctrl";
 };

 rng_hci: entropy_bt_hci {
  compatible = "zephyr,bt-hci-entropy";
  status = "okay";
 };
};

&systick {




 status = "disabled";
};
# 9 "C:/nrfconnectsdk/v2.1.2/zephyr/dts/arm/nordic/nrf5340_cpuapp.dtsi" 2 3 4

/ {
 cpus {
  #address-cells = <1>;
  #size-cells = <0>;

  cpu0: cpu@0 {
   device_type = "cpu";
   compatible = "arm,cortex-m33f";
   reg = <0>;
   #address-cells = <1>;
   #size-cells = <1>;

   itm: itm@e0000000 {
    compatible = "arm,armv8m-itm";
    reg = <0xe0000000 0x1000>;
    swo-ref-frequency = <64000000>;
   };

   mpu: mpu@e000ed90 {
    compatible = "arm,armv8m-mpu";
    reg = <0xe000ed90 0x40>;
   };
  };
 };

 chosen {
  zephyr,entropy = &cryptocell;
  zephyr,flash-controller = &flash_controller;
 };

 soc {
  ficr: ficr@ff0000 {
   compatible = "nordic,nrf-ficr";
   reg = <0xff0000 0x1000>;
   status = "okay";
  };

  uicr: uicr@ff8000 {
   compatible = "nordic,nrf-uicr";
   reg = <0xff8000 0x1000>;
   status = "okay";
  };

  sram0: memory@20000000 {
   compatible = "mmio-sram";
  };

  peripheral@50000000 {
   #address-cells = <1>;
   #size-cells = <1>;
   ranges = <0x0 0x50000000 0x10000000>;




# 1 "C:/nrfconnectsdk/v2.1.2/zephyr/dts/arm/nordic/nrf5340_cpuapp_peripherals.dtsi" 1 3 4






dcnf: dcnf@0 {
 compatible = "nordic,nrf-dcnf";
 reg = <0x0 0x1000>;
 status = "okay";
};

oscillators: oscillator@4000 {
 compatible = "nordic,nrf-oscillators";
 reg = <0x4000 0x1000>;
 status = "okay";
};

regulators: regulator@4000 {
 compatible = "nordic,nrf-regulators";
 reg = <0x4000 0x1000>;
 status = "okay";
};

clock: clock@5000 {
 compatible = "nordic,nrf-clock";
 reg = <0x5000 0x1000>;
 interrupts = <5 1>;
 status = "okay";
};

power: power@5000 {
 compatible = "nordic,nrf-power";
 reg = <0x5000 0x1000>;
 interrupts = <5 1>;
 status = "okay";
};

reset: reset-controller@5000 {
 compatible = "nordic,nrf-reset";
 reg = <0x5000 0x1000>;
 status = "okay";
};

ctrlap: ctrlap@6000 {
 compatible = "nordic,nrf-ctrlapperi";
 reg = <0x6000 0x1000>;
 status = "okay";
};

i2c0: i2c@8000 {





 compatible = "nordic,nrf-twim";
 #address-cells = <1>;
 #size-cells = <0>;
 reg = <0x8000 0x1000>;
 clock-frequency = <100000>;
 interrupts = <8 1>;
 status = "disabled";
};

spi0: spi@8000 {






 compatible = "nordic,nrf-spim";
 #address-cells = <1>;
 #size-cells = <0>;
 reg = <0x8000 0x1000>;
 interrupts = <8 1>;
 max-frequency = <((8) * 1000 * 1000)>;
 status = "disabled";
};

uart0: uart@8000 {
 compatible = "nordic,nrf-uarte";
 reg = <0x8000 0x1000>;
 interrupts = <8 1>;
 status = "disabled";
};

i2c1: i2c@9000 {






 compatible = "nordic,nrf-twim";
 #address-cells = <1>;
 #size-cells = <0>;
 reg = <0x9000 0x1000>;
 clock-frequency = <100000>;
 interrupts = <9 1>;
 status = "disabled";
};

spi1: spi@9000 {






 compatible = "nordic,nrf-spim";
 #address-cells = <1>;
 #size-cells = <0>;
 reg = <0x9000 0x1000>;
 interrupts = <9 1>;
 max-frequency = <((8) * 1000 * 1000)>;
 status = "disabled";
};

uart1: uart@9000 {
 compatible = "nordic,nrf-uarte";
 reg = <0x9000 0x1000>;
 interrupts = <9 1>;
 status = "disabled";
};

spi4: spi@a000 {
 compatible = "nordic,nrf-spim";
 #address-cells = <1>;
 #size-cells = <0>;
 reg = <0xa000 0x1000>;
 interrupts = <10 1>;
 max-frequency = <((32) * 1000 * 1000)>;
 rx-delay-supported;
 rx-delay = <2>;
 status = "disabled";
};

i2c2: i2c@b000 {






 compatible = "nordic,nrf-twim";
 #address-cells = <1>;
 #size-cells = <0>;
 reg = <0xb000 0x1000>;
 clock-frequency = <100000>;
 interrupts = <11 1>;
 status = "disabled";
};

spi2: spi@b000 {






 compatible = "nordic,nrf-spim";
 #address-cells = <1>;
 #size-cells = <0>;
 reg = <0xb000 0x1000>;
 interrupts = <11 1>;
 max-frequency = <((8) * 1000 * 1000)>;
 status = "disabled";
};

uart2: uart@b000 {
 compatible = "nordic,nrf-uarte";
 reg = <0xb000 0x1000>;
 interrupts = <11 1>;
 status = "disabled";
};

i2c3: i2c@c000 {






 compatible = "nordic,nrf-twim";
 #address-cells = <1>;
 #size-cells = <0>;
 reg = <0xc000 0x1000>;
 clock-frequency = <100000>;
 interrupts = <12 1>;
 status = "disabled";
};

spi3: spi@c000 {






 compatible = "nordic,nrf-spim";
 #address-cells = <1>;
 #size-cells = <0>;
 reg = <0xc000 0x1000>;
 interrupts = <12 1>;
 max-frequency = <((8) * 1000 * 1000)>;
 status = "disabled";
};

uart3: uart@c000 {
 compatible = "nordic,nrf-uarte";
 reg = <0xc000 0x1000>;
 interrupts = <12 1>;
 status = "disabled";
};

adc: adc@e000 {
 compatible = "nordic,nrf-saadc";
 reg = <0xe000 0x1000>;
 interrupts = <14 1>;
 status = "disabled";
 #io-channel-cells = <1>;
};

timer0: timer@f000 {
 compatible = "nordic,nrf-timer";
 status = "disabled";
 reg = <0xf000 0x1000>;
 cc-num = <6>;
 interrupts = <15 1>;
 prescaler = <0>;
};

timer1: timer@10000 {
 compatible = "nordic,nrf-timer";
 status = "disabled";
 reg = <0x10000 0x1000>;
 cc-num = <6>;
 interrupts = <16 1>;
 prescaler = <0>;
};

timer2: timer@11000 {
 compatible = "nordic,nrf-timer";
 status = "disabled";
 reg = <0x11000 0x1000>;
 cc-num = <6>;
 interrupts = <17 1>;
 prescaler = <0>;
};

rtc0: rtc@14000 {
 compatible = "nordic,nrf-rtc";
 reg = <0x14000 0x1000>;
 cc-num = <4>;
 interrupts = <20 1>;
 status = "okay";
 clock-frequency = <32768>;
 prescaler = <1>;
};

rtc1: rtc@15000 {
 compatible = "nordic,nrf-rtc";
 reg = <0x15000 0x1000>;
 cc-num = <4>;
 interrupts = <21 1>;
 status = "okay";
 clock-frequency = <32768>;
 prescaler = <1>;
};

dppic: dppic@17000 {
 compatible = "nordic,nrf-dppic";
 reg = <0x17000 0x1000>;
 status = "okay";
};

wdt: wdt0: watchdog@18000 {
 compatible = "nordic,nrf-wdt";
 reg = <0x18000 0x1000>;
 interrupts = <24 1>;
 status = "okay";
};

wdt1: watchdog@19000 {
 compatible = "nordic,nrf-wdt";
 reg = <0x19000 0x1000>;
 interrupts = <25 1>;
 status = "disabled";
};

comp: comparator@1a000 {






 compatible = "nordic,nrf-comp";
 reg = <0x1a000 0x1000>;
 interrupts = <26 1>;
 status = "disabled";
 #io-channel-cells = <1>;
};

egu0: egu@1b000 {
 compatible = "nordic,nrf-egu";
 reg = <0x1b000 0x1000>;
 interrupts = <27 1>;
 status = "okay";
};

egu1: egu@1c000 {
 compatible = "nordic,nrf-egu";
 reg = <0x1c000 0x1000>;
 interrupts = <28 1>;
 status = "okay";
};

egu2: egu@1d000 {
 compatible = "nordic,nrf-egu";
 reg = <0x1d000 0x1000>;
 interrupts = <29 1>;
 status = "okay";
};

egu3: egu@1e000 {
 compatible = "nordic,nrf-egu";
 reg = <0x1e000 0x1000>;
 interrupts = <30 1>;
 status = "okay";
};

egu4: egu@1f000 {
 compatible = "nordic,nrf-egu";
 reg = <0x1f000 0x1000>;
 interrupts = <31 1>;
 status = "okay";
};

egu5: egu@20000 {
 compatible = "nordic,nrf-egu";
 reg = <0x20000 0x1000>;
 interrupts = <32 1>;
 status = "okay";
};

pwm0: pwm@21000 {
 compatible = "nordic,nrf-pwm";
 reg = <0x21000 0x1000>;
 interrupts = <33 1>;
 status = "disabled";
 #pwm-cells = <3>;
};

pwm1: pwm@22000 {
 compatible = "nordic,nrf-pwm";
 reg = <0x22000 0x1000>;
 interrupts = <34 1>;
 status = "disabled";
 #pwm-cells = <3>;
};

pwm2: pwm@23000 {
 compatible = "nordic,nrf-pwm";
 reg = <0x23000 0x1000>;
 interrupts = <35 1>;
 status = "disabled";
 #pwm-cells = <3>;
};

pwm3: pwm@24000 {
 compatible = "nordic,nrf-pwm";
 reg = <0x24000 0x1000>;
 interrupts = <36 1>;
 status = "disabled";
 #pwm-cells = <3>;
};

pdm0: pdm@26000 {
 compatible = "nordic,nrf-pdm";
 reg = <0x26000 0x1000>;
 interrupts = <38 1>;
 status = "disabled";
};

i2s0: i2s@28000 {
 compatible = "nordic,nrf-i2s";
 #address-cells = <1>;
 #size-cells = <0>;
 reg = <0x28000 0x1000>;
 interrupts = <40 1>;
 status = "disabled";
};

mbox: ipc: mbox@2a000 {
 compatible = "nordic,mbox-nrf-ipc", "nordic,nrf-ipc";
 reg = <0x2a000 0x1000>;
 tx-mask = <0x0000ffff>;
 rx-mask = <0x0000ffff>;
 interrupts = <42 1>;
 #mbox-cells = <1>;
 status = "okay";
};

qspi: qspi@2b000 {
 compatible = "nordic,nrf-qspi";
 #address-cells = <1>;
 #size-cells = <0>;
 reg = <0x2b000 0x1000>, <0x10000000 0x10000000>;
 reg-names = "qspi", "qspi_mm";
 interrupts = <43 1>;
 status = "disabled";
};

nfct: nfct@2d000 {
 compatible = "nordic,nrf-nfct";
 reg = <0x2d000 0x1000>;
 interrupts = <45 1>;
 status = "disabled";
};

mutex: mutex@30000 {
 compatible = "nordic,nrf-mutex";
 reg = <0x30000 0x1000>;
 status = "okay";
};

qdec0: qdec@33000 {
 compatible = "nordic,nrf-qdec";
 reg = <0x33000 0x1000>;
 interrupts = <51 1>;
 status = "disabled";
};

qdec1: qdec@34000 {
 compatible = "nordic,nrf-qdec";
 reg = <0x34000 0x1000>;
 interrupts = <52 1>;
 status = "disabled";
};

usbd: usbd@36000 {
 compatible = "nordic,nrf-usbd";
 reg = <0x36000 0x1000>;
 interrupts = <54 1>;
 num-bidir-endpoints = <1>;
 num-in-endpoints = <7>;
 num-out-endpoints = <7>;
 num-isoin-endpoints = <1>;
 num-isoout-endpoints = <1>;
 status = "disabled";
};

usbreg: regulator@37000 {
 compatible = "nordic,nrf-usbreg";
 reg = <0x37000 0x1000>;
 interrupts = <55 1>;
 status = "okay";
};

flash_controller: flash-controller@39000 {
 compatible = "nordic,nrf53-flash-controller";
 reg = <0x39000 0x1000>;
 partial-erase;

 #address-cells = <1>;
 #size-cells = <1>;


 flash0: flash@0 {
  compatible = "soc-nv-flash";
  erase-block-size = <4096>;
  write-block-size = <4>;
 };
};

kmu: kmu@39000 {
 compatible = "nordic,nrf-kmu";
 reg = <0x39000 0x1000>;
 interrupts = <57 1>;
 status = "okay";
};

vmc: vmc@81000 {
 compatible = "nordic,nrf-vmc";
 reg = <0x81000 0x1000>;
 status = "okay";
};

gpio0: gpio@842500 {
 compatible = "nordic,nrf-gpio";
 gpio-controller;
 reg = <0x842500 0x300>;
 #gpio-cells = <2>;
 status = "disabled";
 port = <0>;
};

gpio1: gpio@842800 {
 compatible = "nordic,nrf-gpio";
 gpio-controller;
 reg = <0x842800 0x300>;
 #gpio-cells = <2>;
 ngpios = <16>;
 status = "disabled";
 port = <1>;
};
# 66 "C:/nrfconnectsdk/v2.1.2/zephyr/dts/arm/nordic/nrf5340_cpuapp.dtsi" 2 3 4
  };



  spu: spu@50003000 {
   compatible = "nordic,nrf-spu";
   reg = <0x50003000 0x1000>;
   interrupts = <3 1>;
   status = "okay";
  };






  gpiote: gpiote0: gpiote@5000d000 {
   compatible = "nordic,nrf-gpiote";
   reg = <0x5000d000 0x1000>;
   interrupts = <13 5>;
   status = "disabled";
  };

  cryptocell: crypto@50844000 {
   compatible = "nordic,nrf-cc312";
   reg = <0x50844000 0x1000>;
   status = "okay";
   #address-cells = <1>;
   #size-cells = <1>;
   cryptocell312: crypto@50845000 {
    compatible = "arm,cryptocell-312";
    reg = <0x50845000 0x1000>;
    interrupts = <68 1>;
   };
  };
 };


 ipc {
# 1 "C:/nrfconnectsdk/v2.1.2/zephyr/dts/arm/nordic/nrf5340_cpuapp_ipc.dtsi" 1 3 4






ipc0: ipc0 {
 compatible = "zephyr,ipc-openamp-static-vrings";
 memory-region = <&sram0_shared>;
 mboxes = <&mbox 0>, <&mbox 1>;
 mbox-names = "tx", "rx";
 role = "host";
 status = "okay";
};
# 106 "C:/nrfconnectsdk/v2.1.2/zephyr/dts/arm/nordic/nrf5340_cpuapp.dtsi" 2 3 4
 };
};

&nvic {
 arm,num-irq-priority-bits = <3>;
};






# 1 "C:/nrfconnectsdk/v2.1.2/zephyr/dts/arm/nordic/nrf5340_cpuapp_peripherals_ns.dtsi" 1 3 4
# 11 "C:/nrfconnectsdk/v2.1.2/zephyr/dts/arm/nordic/nrf5340_cpuapp_peripherals_ns.dtsi" 3 4
/ {
 soc {
  gpiote1: gpiote@4002f000 {
   compatible = "nordic,nrf-gpiote";
   reg = <0x4002f000 0x1000>;
   interrupts = <47 5>;
   status = "disabled";
  };
 };
};
# 119 "C:/nrfconnectsdk/v2.1.2/zephyr/dts/arm/nordic/nrf5340_cpuapp.dtsi" 2 3 4
# 9 "C:/nrfconnectsdk/v2.1.2/zephyr/dts/arm/nordic/nrf5340_cpuapp_qkaa.dtsi" 2 3 4

&flash0 {
 reg = <0x00000000 ((1024) * 1024)>;
};

&sram0 {
 reg = <0x20000000 ((512) * 1024)>;
};

&mpu {
 arm,num-mpu-regions = <8>;
};

/ {
 soc {
  compatible = "nordic,nRF5340-CPUAPP-QKAA", "nordic,nRF5340-CPUAPP", "nordic,nRF53", "simple-bus";
 };
};
# 9 "C:/nrfconnectsdk/v2.1.2/nrf/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp.dts" 2
# 1 "C:/nrfconnectsdk/v2.1.2/nrf/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_common.dts" 1





# 1 "C:/nrfconnectsdk/v2.1.2/nrf/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_common-pinctrl.dtsi" 1






&pinctrl {
 i2s0_default: i2s0_default {
  group1 {
   psels = <((((((0) * 32U) + (12)) & 0x3FU) << 0U) | ((19U & 0xFFFFU) << 16U))>;
   nordic,drive-mode = <3U>;
  };
  group2 {
   psels = <((((((0) * 32U) + (14)) & 0x3FU) << 0U) | ((13U & 0xFFFFU) << 16U))>,
    <((((((0) * 32U) + (16)) & 0x3FU) << 0U) | ((15U & 0xFFFFU) << 16U))>,
    <((((((0) * 32U) + (13)) & 0x3FU) << 0U) | ((18U & 0xFFFFU) << 16U))>,
    <((((((0) * 32U) + (15)) & 0x3FU) << 0U) | ((17U & 0xFFFFU) << 16U))>;
  };
 };

 i2s0_sleep: i2s0_sleep {
  group1 {
   psels = <((((((0) * 32U) + (12)) & 0x3FU) << 0U) | ((19U & 0xFFFFU) << 16U))>,
    <((((((0) * 32U) + (14)) & 0x3FU) << 0U) | ((13U & 0xFFFFU) << 16U))>,
    <((((((0) * 32U) + (16)) & 0x3FU) << 0U) | ((15U & 0xFFFFU) << 16U))>,
    <((((((0) * 32U) + (13)) & 0x3FU) << 0U) | ((18U & 0xFFFFU) << 16U))>,
    <((((((0) * 32U) + (15)) & 0x3FU) << 0U) | ((17U & 0xFFFFU) << 16U))>;
   low-power-enable;
  };
 };

 uart0_default: uart0_default {
  group1 {
   psels = <((((((1) * 32U) + (5)) & 0x3FU) << 0U) | ((0U & 0xFFFFU) << 16U))>,
    <((((((1) * 32U) + (7)) & 0x3FU) << 0U) | ((2U & 0xFFFFU) << 16U))>;
  };
  group2 {
   psels = <((((((1) * 32U) + (4)) & 0x3FU) << 0U) | ((1U & 0xFFFFU) << 16U))>,
    <((((((1) * 32U) + (6)) & 0x3FU) << 0U) | ((3U & 0xFFFFU) << 16U))>;
   bias-pull-up;
  };
 };

 uart0_sleep: uart0_sleep {
  group1 {
   psels = <((((((1) * 32U) + (5)) & 0x3FU) << 0U) | ((0U & 0xFFFFU) << 16U))>,
    <((((((1) * 32U) + (4)) & 0x3FU) << 0U) | ((1U & 0xFFFFU) << 16U))>,
    <((((((1) * 32U) + (7)) & 0x3FU) << 0U) | ((2U & 0xFFFFU) << 16U))>,
    <((((((1) * 32U) + (6)) & 0x3FU) << 0U) | ((3U & 0xFFFFU) << 16U))>;
   low-power-enable;
  };
 };

 i2c1_default: i2c1_default {
  group1 {
   psels = <((((((1) * 32U) + (2)) & 0x3FU) << 0U) | ((12U & 0xFFFFU) << 16U))>,
    <((((((1) * 32U) + (3)) & 0x3FU) << 0U) | ((11U & 0xFFFFU) << 16U))>;
  };
 };

 i2c1_sleep: i2c1_sleep {
  group1 {
   psels = <((((((1) * 32U) + (2)) & 0x3FU) << 0U) | ((12U & 0xFFFFU) << 16U))>,
    <((((((1) * 32U) + (3)) & 0x3FU) << 0U) | ((11U & 0xFFFFU) << 16U))>;
   low-power-enable;
  };
 };

 spi4_default: spi4_default {
  group1 {
   psels = <((((((0) * 32U) + (8)) & 0x3FU) << 0U) | ((4U & 0xFFFFU) << 16U))>,
    <((((((0) * 32U) + (9)) & 0x3FU) << 0U) | ((5U & 0xFFFFU) << 16U))>;


   nordic,drive-mode = <3U>;
  };
  group2 {
   psels = <((((((0) * 32U) + (10)) & 0x3FU) << 0U) | ((6U & 0xFFFFU) << 16U))>;
  };
 };

 spi4_sleep: spi4_sleep {
  group1 {
   psels = <((((((0) * 32U) + (8)) & 0x3FU) << 0U) | ((4U & 0xFFFFU) << 16U))>,
    <((((((0) * 32U) + (10)) & 0x3FU) << 0U) | ((6U & 0xFFFFU) << 16U))>,
    <((((((0) * 32U) + (9)) & 0x3FU) << 0U) | ((5U & 0xFFFFU) << 16U))>;
   low-power-enable;
  };
 };
};
# 7 "C:/nrfconnectsdk/v2.1.2/nrf/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_common.dts" 2

/ {
 chosen {
  zephyr,console = &uart0;
  zephyr,shell-uart = &uart0;
  zephyr,uart-mcumgr = &uart0;
  zephyr,bt-mon-uart = &uart0;
  zephyr,bt-c2h-uart = &uart0;
  zephyr,bt-hci-rpmsg-ipc = &ipc0;
 };

 gpio_fwd: nrf-gpio-forwarder {
  compatible = "nordic,nrf-gpio-forwarder";
  status = "okay";
  uart {
   gpios = <&gpio1 9 0>, <&gpio1 8 0>, <&gpio1 11 0>, <&gpio1 10 0>;
  };
 };
};

&adc {
 status = "okay";
};

&gpiote {
 status = "okay";
};

&gpio0 {
 status = "okay";
};

&gpio1 {
 status = "okay";
};

&i2s0 {
 compatible = "nordic,nrf-i2s";
 status = "okay";
 pinctrl-0 = <&i2s0_default>;
 pinctrl-names = "default";
};

&uart0 {
 status = "okay";
 current-speed = <115200>;
 pinctrl-0 = <&uart0_default>;
 pinctrl-1 = <&uart0_sleep>;
 pinctrl-names = "default", "sleep";
};

&i2c1 {
 compatible = "nordic,nrf-twim";
 status = "okay";
 pinctrl-0 = <&i2c1_default>;
 pinctrl-1 = <&i2c1_sleep>;
 pinctrl-names = "default", "sleep";
};

&spi4 {
 compatible = "nordic,nrf-spim";
 status = "okay";
 cs-gpios = <&gpio0 11 (1 << 0)>, <&gpio0 17 (1 << 0)>;
 pinctrl-0 = <&spi4_default>;
 pinctrl-1 = <&spi4_sleep>;
 pinctrl-names = "default", "sleep";
 sdhc0: sdhc@0 {
  compatible = "zephyr,sdhc-spi-slot";
  reg = <0>;
  status = "okay";
  label = "SDHC0";
  mmc {
   compatible = "zephyr,sdmmc-disk";
   status = "okay";
  };

  spi-max-frequency = <8000000>;
 };
 cs47l63: cs47l63@1 {
  reg = <1>;
  label = "CS47L63";
 };
};

&pwm0 {
 status = "okay";
};

&timer0 {
 status = "okay";
};

&timer1 {
 status = "okay";
};

&timer2 {
 status = "okay";
};

&flash0 {
 partitions {
  compatible = "fixed-partitions";
  #address-cells = <1>;
  #size-cells = <1>;

  boot_partition: partition@0 {
   label = "mcuboot";
   reg = <0x00000000 0x00010000>;
  };
  slot0_partition: partition@10000 {
   label = "image-0";
  };
  slot0_ns_partition: partition@50000 {
   label = "image-0-nonsecure";
  };
  slot1_partition: partition@80000 {
   label = "image-1";
  };
  slot1_ns_partition: partition@c0000 {
   label = "image-1-nonsecure";
  };
  scratch_partition: partition@f0000 {
   label = "image-scratch";
   reg = <0x000f0000 0xa000>;
  };
  storage_partition: partition@fa000 {
   label = "storage";
   reg = <0x000fa000 0x00006000>;
  };
 };
};

/ {
 reserved-memory {
  #address-cells = <1>;
  #size-cells = <1>;
  ranges;

  sram0_image: image@20000000 {

  };

  sram0_s: image_s@20000000 {

  };

  sram0_ns: image_ns@20040000 {

  };
 };
};


# 1 "C:/nrfconnectsdk/v2.1.2/nrf/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_partition_conf.dts" 1
# 24 "C:/nrfconnectsdk/v2.1.2/nrf/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_partition_conf.dts"
&slot0_partition {
 reg = <0x00010000 0x40000>;
};

&slot0_ns_partition {
 reg = <0x00050000 0x30000>;
};

&slot1_partition {
 reg = <0x00080000 0x40000>;
};

&slot1_ns_partition {
 reg = <0x000c0000 0x30000>;
};
# 47 "C:/nrfconnectsdk/v2.1.2/nrf/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_partition_conf.dts"
&sram0_image {
 reg = <0x20000000 ((448) * 1024)>;
};

&sram0_s {
 reg = <0x20000000 0x40000>;
};

&sram0_ns {
 reg = <0x20040000 0x30000>;
};


# 1 "C:/nrfconnectsdk/v2.1.2/nrf/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_shared_sram_planning_conf.dts" 1
# 14 "C:/nrfconnectsdk/v2.1.2/nrf/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_shared_sram_planning_conf.dts"
/ {
 chosen {

  zephyr,ipc_shm = &sram0_shared;
 };

 reserved-memory {
  #address-cells = <1>;
  #size-cells = <1>;
  ranges;

  sram0_shared: memory@20070000 {

   reg = <0x20070000 0x10000>;
  };
 };
};
# 61 "C:/nrfconnectsdk/v2.1.2/nrf/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_partition_conf.dts" 2
# 162 "C:/nrfconnectsdk/v2.1.2/nrf/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_common.dts" 2
# 1 "C:/nrfconnectsdk/v2.1.2/nrf/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_shared.dts" 1
/ {
leds: leds {
  compatible = "gpio-leds";
  rgb1_red: led_0 {
   gpios = <&gpio0 7 (0 << 0)>;
   label = "0 LED_RGB_RED CORE_APP";
  };
  rgb1_green: led_1 {
   gpios = <&gpio0 25 (0 << 0)>;
   label = "0 LED_RGB_GREEN CORE_APP";
  };
  rgb1_blue: led_2 {
   gpios = <&gpio0 26 (0 << 0)>;
   label = "0 LED_RGB_BLUE CORE_APP";
  };
  rgb2_red: led_3 {
   gpios = <&gpio0 28 (0 << 0)>;
   label = "1 LED_RGB_RED CORE_NET";
  };
  rgb2_green: led_4 {
   gpios = <&gpio0 29 (0 << 0)>;
   label = "1 LED_RGB_GREEN CORE_NET";
  };
  rgb2_blue: led_5 {
   gpios = <&gpio0 30 (0 << 0)>;
   label = "1 LED_RGB_BLUE CORE_NET";
  };
  led1_blue: led_6 {
   gpios = <&gpio0 31 (0 << 0)>;
   label = "2 LED_MONO_BLUE CORE_APP";
  };
  led2_green: led_7 {
   gpios = <&gpio1 0 (0 << 0)>;
   label = "3 LED_MONO_GREEN CORE_APP";
  };
  led3_green: led_8 {
   gpios = <&gpio1 1 (0 << 0)>;
   label = "4 LED_MONO_GREEN CORE_APP";
  };

 };

 buttons {
  compatible = "gpio-keys";
  button_1_vol_dn: button_1_vol_dn {
   gpios = <&gpio0 2 ((1 << 4) | (1 << 0))>;
   label = "Push button 1";
  };
  button_2_vol_up: button_2_vol_up {
   gpios = <&gpio0 3 ((1 << 4) | (1 << 0))>;
   label = "Push button 2";
  };
  button3: button_3 {
   gpios = <&gpio0 4 ((1 << 4) | (1 << 0))>;
   label = "Push button 3";
  };
  button4: button_4 {
   gpios = <&gpio0 6 ((1 << 4) | (1 << 0))>;
   label = "Push button 4";
  };
  button5: button_5 {
   gpios = <&gpio0 5 ((1 << 4) | (1 << 0))>;
   label = "Push button 5";
  };
 };

 nrf5340_audio_dk {
  compatible = "gpio-keys";
  hw_codec_gpio_in: hw_codec_gpio_in {
   gpios = <&gpio0 20 (1 << 0)>;
   label = "GPIO from HW codec";
  };

  hw_codec_irq_in: hw_codec_irq_in {
   gpios = <&gpio0 19 (1 << 0)>;
   label = "Interrupt from HW codec";
  };

  hw_codec_reset_out: hw_codec_reset_out {
   gpios = <&gpio0 18 (1 << 0)>;
   label = "Reset HW codec";
  };

  hw_codec_sel_out: hw_codec_sel_out {
   gpios = <&gpio0 21 (1 << 0)>;
   label = "HW codec selector. Low selects OB HW codec, high 				 selects external HW codec";

  };

  spi_sel_in: spi_sel_in {
   gpios = <&gpio0 22 (1 << 0)>;
   label = "SPI select in. High = nRF SPI to HW codec. 				 Low = FTDI to HW codec";

  };

  pmic_iset_out: pmic_iset_out {
   gpios = <&gpio0 23 (0 << 0)>;
   label = "PMIC ISET";
  };

  board_id_en_out: board_id_en_out {
   gpios = <&gpio0 24 (0 << 0)>;
   label = "Board revision readback enable";
  };

  board_id_in: board_id_in {
   gpios = <&gpio0 27 (0 << 0)>;
   label = "Board revision analog readback";
  };

  curr_mon_alert_in: curr_mon_alert_in {
   gpios = <&gpio1 15 (1 << 0)>;
   label = "Curr mon alert in from INA231";
  };
 };

 aliases {
  led0 = &rgb1_red;
  led1 = &rgb1_green;
  led2 = &rgb1_blue;
  led3 = &rgb2_red;
  led4 = &rgb2_green;
  led5 = &rgb2_blue;
  led6 = &led1_blue;
  led7 = &led2_green;
  led8 = &led3_green;
  sw0 = &button_1_vol_dn;
  sw1 = &button_2_vol_up;
  sw2 = &button3;
  sw3 = &button4;
  sw4 = &button5;
  mcuboot-led0 = &led1_blue;
  mcuboot-button0 = &button3;
 };
};
# 163 "C:/nrfconnectsdk/v2.1.2/nrf/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_common.dts" 2
# 10 "C:/nrfconnectsdk/v2.1.2/nrf/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp.dts" 2

/ {
 model = "Nordic nRF5340 Audio DK NRF5340 Application";
 compatible = "nordic,nrf5340-audio-dk-nrf5340-cpuapp";

 chosen {
  zephyr,sram = &sram0_image;
  zephyr,flash = &flash0;
  zephyr,code-partition = &slot0_partition;
  zephyr,sram-secure-partition = &sram0_s;
  zephyr,sram-non-secure-partition = &sram0_ns;
 };
};

zephyr_udc0: &usbd {
 compatible = "nordic,nrf-usbd";
 status = "okay";

 hs_0: hs_0 {
  compatible = "usb-audio-hs";
  mic-feature-mute;
  mic-channel-l;
  mic-channel-r;

  hp-feature-mute;
  hp-channel-l;
  hp-channel-r;
 };
};
# 1 "<command-line>" 2
# 1 "C:/nrfconnectsdk/v2.1.2/zephyr/misc/empty_file.c"
