/*
 * Generated by gen_defines.py
 *
 * DTS input file:
 *   nrf5340dk_nrf5340_cpunet.dts.pre.tmp
 *
 * Directories with bindings:
 *   D:/ncs/v1.4.99-dev1/nrf/dts/bindings, $ZEPHYR_BASE\dts\bindings
 *
 * Node dependency ordering (ordinal and path):
 *   0   /
 *   1   /aliases
 *   2   /chosen
 *   3   /buttons
 *   4   /soc
 *   5   /soc/gpio@418c0500
 *   6   /buttons/button_0
 *   7   /buttons/button_1
 *   8   /buttons/button_2
 *   9   /buttons/button_3
 *   10  /cpus
 *   11  /cpus/cpu@1
 *   12  /cpus/cpu@1/mpu@e000ed90
 *   13  /flash-controller@41080000
 *   14  /flash-controller@41080000/flash@1000000
 *   15  /flash-controller@41080000/flash@1000000/partitions
 *   16  /flash-controller@41080000/flash@1000000/partitions/partition@0
 *   17  /flash-controller@41080000/flash@1000000/partitions/partition@c000
 *   18  /flash-controller@41080000/flash@1000000/partitions/partition@1e000
 *   19  /flash-controller@41080000/flash@1000000/partitions/partition@30000
 *   20  /flash-controller@41080000/flash@1000000/partitions/partition@3a000
 *   21  /leds
 *   22  /leds/led_0
 *   23  /leds/led_1
 *   24  /leds/led_2
 *   25  /leds/led_3
 *   26  /reserved-memory
 *   27  /reserved-memory/memory@20070000
 *   28  /soc/interrupt-controller@e000e100
 *   29  /soc/clock@41005000
 *   30  /soc/dppic@4100f000
 *   31  /soc/egu@41014000
 *   32  /soc/ficr@1ff0000
 *   33  /soc/gpio@418c0800
 *   34  /soc/gpiote@4100a000
 *   35  /soc/i2c@41013000
 *   36  /soc/ipc@41012000
 *   37  /soc/memory@20000000
 *   38  /soc/memory@21000000
 *   39  /soc/power@41005000
 *   40  /soc/random@41009000
 *   41  /soc/rtc@41011000
 *   42  /soc/rtc@41016000
 *   43  /soc/spi@41013000
 *   44  /soc/temp@41010000
 *   45  /soc/timer@4100c000
 *   46  /soc/timer@41018000
 *   47  /soc/timer@41019000
 *   48  /soc/timer@e000e010
 *   49  /soc/uart@41013000
 *   50  /soc/uicr@1ff8000
 *   51  /soc/vmc@41081000
 *   52  /soc/watchdog@4100b000
 *
 * Definitions derived from these nodes in dependency order are next,
 * followed by /chosen nodes.
 */

/*
 * Devicetree node: /
 *
 * Node identifier: DT_N
 */
#define DT_N_FOREACH_CHILD(fn) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_cpus) fn(DT_N_S_flash_controller_41080000) fn(DT_N_S_leds) fn(DT_N_S_buttons) fn(DT_N_S_reserved_memory)

/* Node's dependency ordinal: */
#define DT_N_ORD 0

/* Ordinals for what this node depends on directly: */
#define DT_N_REQUIRES_ORDS /* nothing */

/* Ordinals for what depends directly on this node: */
#define DT_N_SUPPORTS_ORDS \
	1, /* /aliases */ \
	2, /* /chosen */ \
	3, /* /buttons */ \
	4, /* /soc */ \
	10, /* /cpus */ \
	13, /* /flash-controller@41080000 */ \
	21, /* /leds */ \
	26, /* /reserved-memory */

/* Existence and alternate IDs: */
#define DT_N_EXISTS 1
#define DT_N_INST_0_nordic_nrf5340_dk_nrf5340_cpunet DT_N

/* Special property macros: */
#define DT_N_REG_NUM 0
#define DT_N_IRQ_NUM 0
#define DT_N_COMPAT_MATCHES_nordic_nrf5340_dk_nrf5340_cpunet 1
#define DT_N_STATUS_okay 1

/* Generic property macros: */
#define DT_N_P_compatible {"nordic,nrf5340-dk-nrf5340-cpunet"}
#define DT_N_P_compatible_IDX_0 "nordic,nrf5340-dk-nrf5340-cpunet"
#define DT_N_P_compatible_IDX_0_EXISTS 1
#define DT_N_P_compatible_LEN 1
#define DT_N_P_compatible_EXISTS 1

/*
 * Devicetree node: /aliases
 *
 * Node identifier: DT_N_S_aliases
 */

/* Node parent (/) identifier: */
#define DT_N_S_aliases_PARENT DT_N
#define DT_N_S_aliases_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_aliases_ORD 1

/* Ordinals for what this node depends on directly: */
#define DT_N_S_aliases_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_aliases_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_aliases_EXISTS 1

/* Special property macros: */
#define DT_N_S_aliases_REG_NUM 0
#define DT_N_S_aliases_IRQ_NUM 0
#define DT_N_S_aliases_STATUS_okay 1

/* (No generic property macros) */

/*
 * Devicetree node: /chosen
 *
 * Node identifier: DT_N_S_chosen
 */

/* Node parent (/) identifier: */
#define DT_N_S_chosen_PARENT DT_N
#define DT_N_S_chosen_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_chosen_ORD 2

/* Ordinals for what this node depends on directly: */
#define DT_N_S_chosen_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_chosen_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_chosen_EXISTS 1

/* Special property macros: */
#define DT_N_S_chosen_REG_NUM 0
#define DT_N_S_chosen_IRQ_NUM 0
#define DT_N_S_chosen_STATUS_okay 1

/* (No generic property macros) */

/*
 * Devicetree node: /buttons
 *
 * Node identifier: DT_N_S_buttons
 *
 * Binding (compatible = gpio-keys):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-keys.yaml
 *
 * Description:
 *   GPIO KEYS parent node
 */

/* Node parent (/) identifier: */
#define DT_N_S_buttons_PARENT DT_N
#define DT_N_S_buttons_FOREACH_CHILD(fn) fn(DT_N_S_buttons_S_button_0) fn(DT_N_S_buttons_S_button_1) fn(DT_N_S_buttons_S_button_2) fn(DT_N_S_buttons_S_button_3)

/* Node's dependency ordinal: */
#define DT_N_S_buttons_ORD 3

/* Ordinals for what this node depends on directly: */
#define DT_N_S_buttons_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_buttons_SUPPORTS_ORDS \
	6, /* /buttons/button_0 */ \
	7, /* /buttons/button_1 */ \
	8, /* /buttons/button_2 */ \
	9, /* /buttons/button_3 */

/* Existence and alternate IDs: */
#define DT_N_S_buttons_EXISTS 1
#define DT_N_INST_0_gpio_keys DT_N_S_buttons

/* Special property macros: */
#define DT_N_S_buttons_REG_NUM 0
#define DT_N_S_buttons_IRQ_NUM 0
#define DT_N_S_buttons_COMPAT_MATCHES_gpio_keys 1
#define DT_N_S_buttons_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_buttons_P_compatible {"gpio-keys"}
#define DT_N_S_buttons_P_compatible_IDX_0 "gpio-keys"
#define DT_N_S_buttons_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_buttons_P_compatible_LEN 1
#define DT_N_S_buttons_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc
 *
 * Node identifier: DT_N_S_soc
 */

/* Node parent (/) identifier: */
#define DT_N_S_soc_PARENT DT_N
#define DT_N_S_soc_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_memory_21000000) fn(DT_N_S_soc_S_clock_41005000) fn(DT_N_S_soc_S_dppic_4100f000) fn(DT_N_S_soc_S_egu_41014000) fn(DT_N_S_soc_S_ficr_1ff0000) fn(DT_N_S_soc_S_gpio_418c0500) fn(DT_N_S_soc_S_gpio_418c0800) fn(DT_N_S_soc_S_gpiote_4100a000) fn(DT_N_S_soc_S_i2c_41013000) fn(DT_N_S_soc_S_ipc_41012000) fn(DT_N_S_soc_S_power_41005000) fn(DT_N_S_soc_S_random_41009000) fn(DT_N_S_soc_S_rtc_41011000) fn(DT_N_S_soc_S_rtc_41016000) fn(DT_N_S_soc_S_spi_41013000) fn(DT_N_S_soc_S_temp_41010000) fn(DT_N_S_soc_S_timer_4100c000) fn(DT_N_S_soc_S_timer_41018000) fn(DT_N_S_soc_S_timer_41019000) fn(DT_N_S_soc_S_uart_41013000) fn(DT_N_S_soc_S_uicr_1ff8000) fn(DT_N_S_soc_S_vmc_41081000) fn(DT_N_S_soc_S_watchdog_4100b000)

/* Node's dependency ordinal: */
#define DT_N_S_soc_ORD 4

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_SUPPORTS_ORDS \
	5, /* /soc/gpio@418c0500 */ \
	28, /* /soc/interrupt-controller@e000e100 */ \
	29, /* /soc/clock@41005000 */ \
	30, /* /soc/dppic@4100f000 */ \
	31, /* /soc/egu@41014000 */ \
	32, /* /soc/ficr@1ff0000 */ \
	33, /* /soc/gpio@418c0800 */ \
	34, /* /soc/gpiote@4100a000 */ \
	35, /* /soc/i2c@41013000 */ \
	36, /* /soc/ipc@41012000 */ \
	37, /* /soc/memory@20000000 */ \
	38, /* /soc/memory@21000000 */ \
	39, /* /soc/power@41005000 */ \
	40, /* /soc/random@41009000 */ \
	41, /* /soc/rtc@41011000 */ \
	42, /* /soc/rtc@41016000 */ \
	43, /* /soc/spi@41013000 */ \
	44, /* /soc/temp@41010000 */ \
	45, /* /soc/timer@4100c000 */ \
	46, /* /soc/timer@41018000 */ \
	47, /* /soc/timer@41019000 */ \
	48, /* /soc/timer@e000e010 */ \
	49, /* /soc/uart@41013000 */ \
	50, /* /soc/uicr@1ff8000 */ \
	51, /* /soc/vmc@41081000 */ \
	52, /* /soc/watchdog@4100b000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_EXISTS 1
#define DT_N_INST_0_nordic_nrf5340_cpunet_qkaa DT_N_S_soc
#define DT_N_INST_0_nordic_nrf5340_cpunet      DT_N_S_soc
#define DT_N_INST_0_nordic_nrf53               DT_N_S_soc
#define DT_N_INST_0_simple_bus                 DT_N_S_soc

/* Special property macros: */
#define DT_N_S_soc_REG_NUM 0
#define DT_N_S_soc_IRQ_NUM 0
#define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf5340_cpunet_qkaa 1
#define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf5340_cpunet 1
#define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf53 1
#define DT_N_S_soc_COMPAT_MATCHES_simple_bus 1
#define DT_N_S_soc_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_P_compatible {"nordic,nRF5340-CPUNET-QKAA", "nordic,nRF5340-CPUNET", "nordic,nRF53", "simple-bus"}
#define DT_N_S_soc_P_compatible_IDX_0 "nordic,nRF5340-CPUNET-QKAA"
#define DT_N_S_soc_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_P_compatible_IDX_1 "nordic,nRF5340-CPUNET"
#define DT_N_S_soc_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_P_compatible_IDX_2 "nordic,nRF53"
#define DT_N_S_soc_P_compatible_IDX_2_EXISTS 1
#define DT_N_S_soc_P_compatible_IDX_3 "simple-bus"
#define DT_N_S_soc_P_compatible_IDX_3_EXISTS 1
#define DT_N_S_soc_P_compatible_LEN 4
#define DT_N_S_soc_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/gpio@418c0500
 *
 * Node identifier: DT_N_S_soc_S_gpio_418c0500
 *
 * Binding (compatible = nordic,nrf-gpio):
 *   $ZEPHYR_BASE\dts\bindings\gpio\nordic,nrf-gpio.yaml
 *
 * Description:
 *   NRF5 GPIO node
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_gpio_418c0500_PARENT DT_N_S_soc
#define DT_N_S_soc_S_gpio_418c0500_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_gpio_418c0500_ORD 5

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_gpio_418c0500_REQUIRES_ORDS \
	4, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_gpio_418c0500_SUPPORTS_ORDS \
	6, /* /buttons/button_0 */ \
	7, /* /buttons/button_1 */ \
	8, /* /buttons/button_2 */ \
	9, /* /buttons/button_3 */ \
	22, /* /leds/led_0 */ \
	23, /* /leds/led_1 */ \
	24, /* /leds/led_2 */ \
	25, /* /leds/led_3 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_gpio_418c0500_EXISTS 1
#define DT_N_INST_0_nordic_nrf_gpio DT_N_S_soc_S_gpio_418c0500
#define DT_N_NODELABEL_gpio0        DT_N_S_soc_S_gpio_418c0500

/* Special property macros: */
#define DT_N_S_soc_S_gpio_418c0500_REG_NUM 1
#define DT_N_S_soc_S_gpio_418c0500_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_418c0500_REG_IDX_0_VAL_ADDRESS 1099695360 /* 0x418c0500 */
#define DT_N_S_soc_S_gpio_418c0500_REG_IDX_0_VAL_SIZE 768 /* 0x300 */
#define DT_N_S_soc_S_gpio_418c0500_IRQ_NUM 0
#define DT_N_S_soc_S_gpio_418c0500_COMPAT_MATCHES_nordic_nrf_gpio 1
#define DT_N_S_soc_S_gpio_418c0500_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_gpio_418c0500_P_reg {1099695360 /* 0x418c0500 */, 768 /* 0x300 */}
#define DT_N_S_soc_S_gpio_418c0500_P_reg_IDX_0 1099695360
#define DT_N_S_soc_S_gpio_418c0500_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_418c0500_P_reg_IDX_1 768
#define DT_N_S_soc_S_gpio_418c0500_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_gpio_418c0500_P_reg_EXISTS 1
#define DT_N_S_soc_S_gpio_418c0500_P_label "GPIO_0"
#define DT_N_S_soc_S_gpio_418c0500_P_label_EXISTS 1
#define DT_N_S_soc_S_gpio_418c0500_P_gpio_controller 1
#define DT_N_S_soc_S_gpio_418c0500_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_gpio_418c0500_P_ngpios 32
#define DT_N_S_soc_S_gpio_418c0500_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_gpio_418c0500_P_status "okay"
#define DT_N_S_soc_S_gpio_418c0500_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_gpio_418c0500_P_status_EXISTS 1
#define DT_N_S_soc_S_gpio_418c0500_P_compatible {"nordic,nrf-gpio"}
#define DT_N_S_soc_S_gpio_418c0500_P_compatible_IDX_0 "nordic,nrf-gpio"
#define DT_N_S_soc_S_gpio_418c0500_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_418c0500_P_compatible_LEN 1
#define DT_N_S_soc_S_gpio_418c0500_P_compatible_EXISTS 1

/*
 * Devicetree node: /buttons/button_0
 *
 * Node identifier: DT_N_S_buttons_S_button_0
 *
 * Binding (compatible = gpio-keys):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-keys.yaml
 *
 * Description:
 *   GPIO KEYS child node
 */

/* Node parent (/buttons) identifier: */
#define DT_N_S_buttons_S_button_0_PARENT DT_N_S_buttons
#define DT_N_S_buttons_S_button_0_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_buttons_S_button_0_ORD 6

/* Ordinals for what this node depends on directly: */
#define DT_N_S_buttons_S_button_0_REQUIRES_ORDS \
	3, /* /buttons */ \
	5, /* /soc/gpio@418c0500 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_buttons_S_button_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_buttons_S_button_0_EXISTS 1
#define DT_N_ALIAS_sw0         DT_N_S_buttons_S_button_0
#define DT_N_NODELABEL_button0 DT_N_S_buttons_S_button_0

/* Special property macros: */
#define DT_N_S_buttons_S_button_0_REG_NUM 0
#define DT_N_S_buttons_S_button_0_IRQ_NUM 0
#define DT_N_S_buttons_S_button_0_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_PH DT_N_S_soc_S_gpio_418c0500
#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_pin 23
#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_flags 17
#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_buttons_S_button_0_P_gpios_LEN 1
#define DT_N_S_buttons_S_button_0_P_gpios_EXISTS 1
#define DT_N_S_buttons_S_button_0_P_label "Push button 1"
#define DT_N_S_buttons_S_button_0_P_label_EXISTS 1

/*
 * Devicetree node: /buttons/button_1
 *
 * Node identifier: DT_N_S_buttons_S_button_1
 *
 * Binding (compatible = gpio-keys):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-keys.yaml
 *
 * Description:
 *   GPIO KEYS child node
 */

/* Node parent (/buttons) identifier: */
#define DT_N_S_buttons_S_button_1_PARENT DT_N_S_buttons
#define DT_N_S_buttons_S_button_1_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_buttons_S_button_1_ORD 7

/* Ordinals for what this node depends on directly: */
#define DT_N_S_buttons_S_button_1_REQUIRES_ORDS \
	3, /* /buttons */ \
	5, /* /soc/gpio@418c0500 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_buttons_S_button_1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_buttons_S_button_1_EXISTS 1
#define DT_N_ALIAS_sw1         DT_N_S_buttons_S_button_1
#define DT_N_NODELABEL_button1 DT_N_S_buttons_S_button_1

/* Special property macros: */
#define DT_N_S_buttons_S_button_1_REG_NUM 0
#define DT_N_S_buttons_S_button_1_IRQ_NUM 0
#define DT_N_S_buttons_S_button_1_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_PH DT_N_S_soc_S_gpio_418c0500
#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_pin 24
#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_flags 17
#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_buttons_S_button_1_P_gpios_LEN 1
#define DT_N_S_buttons_S_button_1_P_gpios_EXISTS 1
#define DT_N_S_buttons_S_button_1_P_label "Push button 2"
#define DT_N_S_buttons_S_button_1_P_label_EXISTS 1

/*
 * Devicetree node: /buttons/button_2
 *
 * Node identifier: DT_N_S_buttons_S_button_2
 *
 * Binding (compatible = gpio-keys):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-keys.yaml
 *
 * Description:
 *   GPIO KEYS child node
 */

/* Node parent (/buttons) identifier: */
#define DT_N_S_buttons_S_button_2_PARENT DT_N_S_buttons
#define DT_N_S_buttons_S_button_2_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_buttons_S_button_2_ORD 8

/* Ordinals for what this node depends on directly: */
#define DT_N_S_buttons_S_button_2_REQUIRES_ORDS \
	3, /* /buttons */ \
	5, /* /soc/gpio@418c0500 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_buttons_S_button_2_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_buttons_S_button_2_EXISTS 1
#define DT_N_ALIAS_sw2         DT_N_S_buttons_S_button_2
#define DT_N_NODELABEL_button2 DT_N_S_buttons_S_button_2

/* Special property macros: */
#define DT_N_S_buttons_S_button_2_REG_NUM 0
#define DT_N_S_buttons_S_button_2_IRQ_NUM 0
#define DT_N_S_buttons_S_button_2_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_PH DT_N_S_soc_S_gpio_418c0500
#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_pin 8
#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_flags 17
#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_buttons_S_button_2_P_gpios_LEN 1
#define DT_N_S_buttons_S_button_2_P_gpios_EXISTS 1
#define DT_N_S_buttons_S_button_2_P_label "Push button 3"
#define DT_N_S_buttons_S_button_2_P_label_EXISTS 1

/*
 * Devicetree node: /buttons/button_3
 *
 * Node identifier: DT_N_S_buttons_S_button_3
 *
 * Binding (compatible = gpio-keys):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-keys.yaml
 *
 * Description:
 *   GPIO KEYS child node
 */

/* Node parent (/buttons) identifier: */
#define DT_N_S_buttons_S_button_3_PARENT DT_N_S_buttons
#define DT_N_S_buttons_S_button_3_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_buttons_S_button_3_ORD 9

/* Ordinals for what this node depends on directly: */
#define DT_N_S_buttons_S_button_3_REQUIRES_ORDS \
	3, /* /buttons */ \
	5, /* /soc/gpio@418c0500 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_buttons_S_button_3_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_buttons_S_button_3_EXISTS 1
#define DT_N_ALIAS_sw3         DT_N_S_buttons_S_button_3
#define DT_N_NODELABEL_button3 DT_N_S_buttons_S_button_3

/* Special property macros: */
#define DT_N_S_buttons_S_button_3_REG_NUM 0
#define DT_N_S_buttons_S_button_3_IRQ_NUM 0
#define DT_N_S_buttons_S_button_3_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_PH DT_N_S_soc_S_gpio_418c0500
#define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_VAL_pin 9
#define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_VAL_flags 17
#define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_buttons_S_button_3_P_gpios_LEN 1
#define DT_N_S_buttons_S_button_3_P_gpios_EXISTS 1
#define DT_N_S_buttons_S_button_3_P_label "Push button 4"
#define DT_N_S_buttons_S_button_3_P_label_EXISTS 1

/*
 * Devicetree node: /cpus
 *
 * Node identifier: DT_N_S_cpus
 */

/* Node parent (/) identifier: */
#define DT_N_S_cpus_PARENT DT_N
#define DT_N_S_cpus_FOREACH_CHILD(fn) fn(DT_N_S_cpus_S_cpu_1)

/* Node's dependency ordinal: */
#define DT_N_S_cpus_ORD 10

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_SUPPORTS_ORDS \
	11, /* /cpus/cpu@1 */

/* Existence and alternate IDs: */
#define DT_N_S_cpus_EXISTS 1

/* Special property macros: */
#define DT_N_S_cpus_REG_NUM 0
#define DT_N_S_cpus_IRQ_NUM 0
#define DT_N_S_cpus_STATUS_okay 1

/* (No generic property macros) */

/*
 * Devicetree node: /cpus/cpu@1
 *
 * Node identifier: DT_N_S_cpus_S_cpu_1
 *
 * Binding (compatible = arm,cortex-m33):
 *   $ZEPHYR_BASE\dts\bindings\cpu\arm,cortex-m33.yaml
 *
 * Description:
 *   ARM Cortex-M33 CPU
 */

/* Node parent (/cpus) identifier: */
#define DT_N_S_cpus_S_cpu_1_PARENT DT_N_S_cpus
#define DT_N_S_cpus_S_cpu_1_FOREACH_CHILD(fn) fn(DT_N_S_cpus_S_cpu_1_S_mpu_e000ed90)

/* Node's dependency ordinal: */
#define DT_N_S_cpus_S_cpu_1_ORD 11

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_S_cpu_1_REQUIRES_ORDS \
	10, /* /cpus */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_S_cpu_1_SUPPORTS_ORDS \
	12, /* /cpus/cpu@1/mpu@e000ed90 */

/* Existence and alternate IDs: */
#define DT_N_S_cpus_S_cpu_1_EXISTS 1
#define DT_N_INST_0_arm_cortex_m33 DT_N_S_cpus_S_cpu_1

/* Special property macros: */
#define DT_N_S_cpus_S_cpu_1_REG_NUM 1
#define DT_N_S_cpus_S_cpu_1_REG_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_1_REG_IDX_0_VAL_ADDRESS 1 /* 0x1 */
#define DT_N_S_cpus_S_cpu_1_IRQ_NUM 0
#define DT_N_S_cpus_S_cpu_1_COMPAT_MATCHES_arm_cortex_m33 1
#define DT_N_S_cpus_S_cpu_1_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_cpus_S_cpu_1_P_compatible {"arm,cortex-m33"}
#define DT_N_S_cpus_S_cpu_1_P_compatible_IDX_0 "arm,cortex-m33"
#define DT_N_S_cpus_S_cpu_1_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_1_P_compatible_LEN 1
#define DT_N_S_cpus_S_cpu_1_P_compatible_EXISTS 1
#define DT_N_S_cpus_S_cpu_1_P_reg {1 /* 0x1 */}
#define DT_N_S_cpus_S_cpu_1_P_reg_IDX_0 1
#define DT_N_S_cpus_S_cpu_1_P_reg_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_1_P_reg_EXISTS 1

/*
 * Devicetree node: /cpus/cpu@1/mpu@e000ed90
 *
 * Node identifier: DT_N_S_cpus_S_cpu_1_S_mpu_e000ed90
 *
 * Binding (compatible = arm,armv8m-mpu):
 *   $ZEPHYR_BASE\dts\bindings\mmu_mpu\arm,armv8m-mpu.yaml
 *
 * Description:
 *   ARMv8-M MPU (Memory Protection Unit)
 */

/* Node parent (/cpus/cpu@1) identifier: */
#define DT_N_S_cpus_S_cpu_1_S_mpu_e000ed90_PARENT DT_N_S_cpus_S_cpu_1
#define DT_N_S_cpus_S_cpu_1_S_mpu_e000ed90_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_cpus_S_cpu_1_S_mpu_e000ed90_ORD 12

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_S_cpu_1_S_mpu_e000ed90_REQUIRES_ORDS \
	11, /* /cpus/cpu@1 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_S_cpu_1_S_mpu_e000ed90_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_cpus_S_cpu_1_S_mpu_e000ed90_EXISTS 1
#define DT_N_INST_0_arm_armv8m_mpu DT_N_S_cpus_S_cpu_1_S_mpu_e000ed90
#define DT_N_NODELABEL_mpu         DT_N_S_cpus_S_cpu_1_S_mpu_e000ed90

/* Special property macros: */
#define DT_N_S_cpus_S_cpu_1_S_mpu_e000ed90_REG_NUM 1
#define DT_N_S_cpus_S_cpu_1_S_mpu_e000ed90_REG_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_1_S_mpu_e000ed90_REG_IDX_0_VAL_ADDRESS 3758157200 /* 0xe000ed90 */
#define DT_N_S_cpus_S_cpu_1_S_mpu_e000ed90_REG_IDX_0_VAL_SIZE 64 /* 0x40 */
#define DT_N_S_cpus_S_cpu_1_S_mpu_e000ed90_IRQ_NUM 0
#define DT_N_S_cpus_S_cpu_1_S_mpu_e000ed90_COMPAT_MATCHES_arm_armv8m_mpu 1
#define DT_N_S_cpus_S_cpu_1_S_mpu_e000ed90_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_cpus_S_cpu_1_S_mpu_e000ed90_P_reg {3758157200 /* 0xe000ed90 */, 64 /* 0x40 */}
#define DT_N_S_cpus_S_cpu_1_S_mpu_e000ed90_P_reg_IDX_0 3758157200
#define DT_N_S_cpus_S_cpu_1_S_mpu_e000ed90_P_reg_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_1_S_mpu_e000ed90_P_reg_IDX_1 64
#define DT_N_S_cpus_S_cpu_1_S_mpu_e000ed90_P_reg_IDX_1_EXISTS 1
#define DT_N_S_cpus_S_cpu_1_S_mpu_e000ed90_P_reg_EXISTS 1
#define DT_N_S_cpus_S_cpu_1_S_mpu_e000ed90_P_arm_num_mpu_regions 8
#define DT_N_S_cpus_S_cpu_1_S_mpu_e000ed90_P_arm_num_mpu_regions_EXISTS 1
#define DT_N_S_cpus_S_cpu_1_S_mpu_e000ed90_P_compatible {"arm,armv8m-mpu"}
#define DT_N_S_cpus_S_cpu_1_S_mpu_e000ed90_P_compatible_IDX_0 "arm,armv8m-mpu"
#define DT_N_S_cpus_S_cpu_1_S_mpu_e000ed90_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_1_S_mpu_e000ed90_P_compatible_LEN 1
#define DT_N_S_cpus_S_cpu_1_S_mpu_e000ed90_P_compatible_EXISTS 1

/*
 * Devicetree node: /flash-controller@41080000
 *
 * Node identifier: DT_N_S_flash_controller_41080000
 *
 * Binding (compatible = nordic,nrf53-flash-controller):
 *   $ZEPHYR_BASE\dts\bindings\flash_controller\nordic,nrf53-flash-controller.yaml
 *
 * Description:
 *   Nordic NVMC (Non-Volatile Memory Controller)
 */

/* Node parent (/) identifier: */
#define DT_N_S_flash_controller_41080000_PARENT DT_N
#define DT_N_S_flash_controller_41080000_FOREACH_CHILD(fn) fn(DT_N_S_flash_controller_41080000_S_flash_1000000)

/* Node's dependency ordinal: */
#define DT_N_S_flash_controller_41080000_ORD 13

/* Ordinals for what this node depends on directly: */
#define DT_N_S_flash_controller_41080000_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_flash_controller_41080000_SUPPORTS_ORDS \
	14, /* /flash-controller@41080000/flash@1000000 */

/* Existence and alternate IDs: */
#define DT_N_S_flash_controller_41080000_EXISTS 1
#define DT_N_INST_0_nordic_nrf53_flash_controller DT_N_S_flash_controller_41080000
#define DT_N_NODELABEL_flash_controller           DT_N_S_flash_controller_41080000

/* Special property macros: */
#define DT_N_S_flash_controller_41080000_REG_NUM 1
#define DT_N_S_flash_controller_41080000_REG_IDX_0_EXISTS 1
#define DT_N_S_flash_controller_41080000_REG_IDX_0_VAL_ADDRESS 1091043328 /* 0x41080000 */
#define DT_N_S_flash_controller_41080000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_flash_controller_41080000_IRQ_NUM 0
#define DT_N_S_flash_controller_41080000_COMPAT_MATCHES_nordic_nrf53_flash_controller 1
#define DT_N_S_flash_controller_41080000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_flash_controller_41080000_P_label "NRF_FLASH_DRV_NAME"
#define DT_N_S_flash_controller_41080000_P_label_EXISTS 1
#define DT_N_S_flash_controller_41080000_P_reg {1091043328 /* 0x41080000 */, 4096 /* 0x1000 */}
#define DT_N_S_flash_controller_41080000_P_reg_IDX_0 1091043328
#define DT_N_S_flash_controller_41080000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_flash_controller_41080000_P_reg_IDX_1 4096
#define DT_N_S_flash_controller_41080000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_flash_controller_41080000_P_reg_EXISTS 1
#define DT_N_S_flash_controller_41080000_P_compatible {"nordic,nrf53-flash-controller"}
#define DT_N_S_flash_controller_41080000_P_compatible_IDX_0 "nordic,nrf53-flash-controller"
#define DT_N_S_flash_controller_41080000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_flash_controller_41080000_P_compatible_LEN 1
#define DT_N_S_flash_controller_41080000_P_compatible_EXISTS 1

/*
 * Devicetree node: /flash-controller@41080000/flash@1000000
 *
 * Node identifier: DT_N_S_flash_controller_41080000_S_flash_1000000
 *
 * Binding (compatible = soc-nv-flash):
 *   $ZEPHYR_BASE\dts\bindings\mtd\soc-nv-flash.yaml
 *
 * Description:
 *   Flash node
 */

/* Node parent (/flash-controller@41080000) identifier: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_PARENT DT_N_S_flash_controller_41080000
#define DT_N_S_flash_controller_41080000_S_flash_1000000_FOREACH_CHILD(fn) fn(DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions)

/* Node's dependency ordinal: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_ORD 14

/* Ordinals for what this node depends on directly: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_REQUIRES_ORDS \
	13, /* /flash-controller@41080000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_SUPPORTS_ORDS \
	15, /* /flash-controller@41080000/flash@1000000/partitions */

/* Existence and alternate IDs: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_EXISTS 1
#define DT_N_INST_0_soc_nv_flash DT_N_S_flash_controller_41080000_S_flash_1000000
#define DT_N_NODELABEL_flash1    DT_N_S_flash_controller_41080000_S_flash_1000000

/* Special property macros: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_REG_NUM 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_REG_IDX_0_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_REG_IDX_0_VAL_ADDRESS 16777216 /* 0x1000000 */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_REG_IDX_0_VAL_SIZE 262144 /* 0x40000 */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_IRQ_NUM 0
#define DT_N_S_flash_controller_41080000_S_flash_1000000_COMPAT_MATCHES_soc_nv_flash 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_P_label "NRF_FLASH"
#define DT_N_S_flash_controller_41080000_S_flash_1000000_P_label_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_P_erase_block_size 2048
#define DT_N_S_flash_controller_41080000_S_flash_1000000_P_erase_block_size_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_P_write_block_size 4
#define DT_N_S_flash_controller_41080000_S_flash_1000000_P_write_block_size_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_P_compatible {"soc-nv-flash"}
#define DT_N_S_flash_controller_41080000_S_flash_1000000_P_compatible_IDX_0 "soc-nv-flash"
#define DT_N_S_flash_controller_41080000_S_flash_1000000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_P_compatible_LEN 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_P_compatible_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_P_reg {16777216 /* 0x1000000 */, 262144 /* 0x40000 */}
#define DT_N_S_flash_controller_41080000_S_flash_1000000_P_reg_IDX_0 16777216
#define DT_N_S_flash_controller_41080000_S_flash_1000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_P_reg_IDX_1 262144
#define DT_N_S_flash_controller_41080000_S_flash_1000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_P_reg_EXISTS 1

/*
 * Devicetree node: /flash-controller@41080000/flash@1000000/partitions
 *
 * Node identifier: DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions
 *
 * Binding (compatible = fixed-partitions):
 *   $ZEPHYR_BASE\dts\bindings\mtd\partition.yaml
 *
 * Description:
 *   Flash partitions parent node
 */

/* Node parent (/flash-controller@41080000/flash@1000000) identifier: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_PARENT DT_N_S_flash_controller_41080000_S_flash_1000000
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_FOREACH_CHILD(fn) fn(DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_0) fn(DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_c000) fn(DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_1e000) fn(DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_30000) fn(DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_3a000)

/* Node's dependency ordinal: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_ORD 15

/* Ordinals for what this node depends on directly: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_REQUIRES_ORDS \
	14, /* /flash-controller@41080000/flash@1000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_SUPPORTS_ORDS \
	16, /* /flash-controller@41080000/flash@1000000/partitions/partition@0 */ \
	17, /* /flash-controller@41080000/flash@1000000/partitions/partition@c000 */ \
	18, /* /flash-controller@41080000/flash@1000000/partitions/partition@1e000 */ \
	19, /* /flash-controller@41080000/flash@1000000/partitions/partition@30000 */ \
	20, /* /flash-controller@41080000/flash@1000000/partitions/partition@3a000 */

/* Existence and alternate IDs: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_EXISTS 1
#define DT_N_INST_0_fixed_partitions DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions

/* Special property macros: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_REG_NUM 0
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_IRQ_NUM 0
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_COMPAT_MATCHES_fixed_partitions 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_STATUS_okay 1

/* (No generic property macros) */

/*
 * Devicetree node: /flash-controller@41080000/flash@1000000/partitions/partition@0
 *
 * Node identifier: DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_0
 *
 * Binding (compatible = fixed-partitions):
 *   $ZEPHYR_BASE\dts\bindings\mtd\partition.yaml
 *
 * Description:
 *   Flash partition child node
 */

/* Node parent (/flash-controller@41080000/flash@1000000/partitions) identifier: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_0_PARENT DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_0_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_0_ORD 16

/* Ordinals for what this node depends on directly: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_0_REQUIRES_ORDS \
	15, /* /flash-controller@41080000/flash@1000000/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_0_EXISTS 1
#define DT_N_NODELABEL_boot_partition DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_0

/* Special property macros: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_0_REG_NUM 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_0_REG_IDX_0_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_0_REG_IDX_0_VAL_SIZE 49152 /* 0xc000 */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_0_IRQ_NUM 0
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_0_STATUS_okay 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_0_PARTITION_ID 0

/* Generic property macros: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_0_P_label "mcuboot"
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_0_P_label_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_0_P_read_only 0
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_0_P_read_only_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_0_P_reg {0 /* 0x0 */, 49152 /* 0xc000 */}
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_0_P_reg_IDX_0 0
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_0_P_reg_IDX_1 49152
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_0_P_reg_IDX_1_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_0_P_reg_EXISTS 1

/*
 * Devicetree node: /flash-controller@41080000/flash@1000000/partitions/partition@c000
 *
 * Node identifier: DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_c000
 *
 * Binding (compatible = fixed-partitions):
 *   $ZEPHYR_BASE\dts\bindings\mtd\partition.yaml
 *
 * Description:
 *   Flash partition child node
 */

/* Node parent (/flash-controller@41080000/flash@1000000/partitions) identifier: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_c000_PARENT DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_c000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_c000_ORD 17

/* Ordinals for what this node depends on directly: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_c000_REQUIRES_ORDS \
	15, /* /flash-controller@41080000/flash@1000000/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_c000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_c000_EXISTS 1
#define DT_N_NODELABEL_slot0_partition DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_c000

/* Special property macros: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_c000_REG_NUM 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_c000_REG_IDX_0_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_c000_REG_IDX_0_VAL_ADDRESS 49152 /* 0xc000 */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_c000_REG_IDX_0_VAL_SIZE 73728 /* 0x12000 */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_c000_IRQ_NUM 0
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_c000_STATUS_okay 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_c000_PARTITION_ID 1

/* Generic property macros: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_c000_P_label "image-0"
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_c000_P_label_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_c000_P_read_only 0
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_c000_P_read_only_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_c000_P_reg {49152 /* 0xc000 */, 73728 /* 0x12000 */}
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_c000_P_reg_IDX_0 49152
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_c000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_c000_P_reg_IDX_1 73728
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_c000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_c000_P_reg_EXISTS 1

/*
 * Devicetree node: /flash-controller@41080000/flash@1000000/partitions/partition@1e000
 *
 * Node identifier: DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_1e000
 *
 * Binding (compatible = fixed-partitions):
 *   $ZEPHYR_BASE\dts\bindings\mtd\partition.yaml
 *
 * Description:
 *   Flash partition child node
 */

/* Node parent (/flash-controller@41080000/flash@1000000/partitions) identifier: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_1e000_PARENT DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_1e000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_1e000_ORD 18

/* Ordinals for what this node depends on directly: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_1e000_REQUIRES_ORDS \
	15, /* /flash-controller@41080000/flash@1000000/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_1e000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_1e000_EXISTS 1
#define DT_N_NODELABEL_slot1_partition DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_1e000

/* Special property macros: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_1e000_REG_NUM 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_1e000_REG_IDX_0_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_1e000_REG_IDX_0_VAL_ADDRESS 122880 /* 0x1e000 */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_1e000_REG_IDX_0_VAL_SIZE 73728 /* 0x12000 */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_1e000_IRQ_NUM 0
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_1e000_STATUS_okay 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_1e000_PARTITION_ID 2

/* Generic property macros: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_1e000_P_label "image-1"
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_1e000_P_label_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_1e000_P_read_only 0
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_1e000_P_read_only_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_1e000_P_reg {122880 /* 0x1e000 */, 73728 /* 0x12000 */}
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_1e000_P_reg_IDX_0 122880
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_1e000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_1e000_P_reg_IDX_1 73728
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_1e000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_1e000_P_reg_EXISTS 1

/*
 * Devicetree node: /flash-controller@41080000/flash@1000000/partitions/partition@30000
 *
 * Node identifier: DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_30000
 *
 * Binding (compatible = fixed-partitions):
 *   $ZEPHYR_BASE\dts\bindings\mtd\partition.yaml
 *
 * Description:
 *   Flash partition child node
 */

/* Node parent (/flash-controller@41080000/flash@1000000/partitions) identifier: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_30000_PARENT DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_30000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_30000_ORD 19

/* Ordinals for what this node depends on directly: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_30000_REQUIRES_ORDS \
	15, /* /flash-controller@41080000/flash@1000000/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_30000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_30000_EXISTS 1
#define DT_N_NODELABEL_scratch_partition DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_30000

/* Special property macros: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_30000_REG_NUM 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_30000_REG_IDX_0_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_30000_REG_IDX_0_VAL_ADDRESS 196608 /* 0x30000 */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_30000_REG_IDX_0_VAL_SIZE 40960 /* 0xa000 */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_30000_IRQ_NUM 0
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_30000_STATUS_okay 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_30000_PARTITION_ID 3

/* Generic property macros: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_30000_P_label "image-scratch"
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_30000_P_label_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_30000_P_read_only 0
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_30000_P_read_only_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_30000_P_reg {196608 /* 0x30000 */, 40960 /* 0xa000 */}
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_30000_P_reg_IDX_0 196608
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_30000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_30000_P_reg_IDX_1 40960
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_30000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_30000_P_reg_EXISTS 1

/*
 * Devicetree node: /flash-controller@41080000/flash@1000000/partitions/partition@3a000
 *
 * Node identifier: DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_3a000
 *
 * Binding (compatible = fixed-partitions):
 *   $ZEPHYR_BASE\dts\bindings\mtd\partition.yaml
 *
 * Description:
 *   Flash partition child node
 */

/* Node parent (/flash-controller@41080000/flash@1000000/partitions) identifier: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_3a000_PARENT DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_3a000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_3a000_ORD 20

/* Ordinals for what this node depends on directly: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_3a000_REQUIRES_ORDS \
	15, /* /flash-controller@41080000/flash@1000000/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_3a000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_3a000_EXISTS 1
#define DT_N_NODELABEL_storage_partition DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_3a000

/* Special property macros: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_3a000_REG_NUM 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_3a000_REG_IDX_0_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_3a000_REG_IDX_0_VAL_ADDRESS 237568 /* 0x3a000 */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_3a000_REG_IDX_0_VAL_SIZE 24576 /* 0x6000 */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_3a000_IRQ_NUM 0
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_3a000_STATUS_okay 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_3a000_PARTITION_ID 4

/* Generic property macros: */
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_3a000_P_label "storage"
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_3a000_P_label_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_3a000_P_read_only 0
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_3a000_P_read_only_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_3a000_P_reg {237568 /* 0x3a000 */, 24576 /* 0x6000 */}
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_3a000_P_reg_IDX_0 237568
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_3a000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_3a000_P_reg_IDX_1 24576
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_3a000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_3a000_P_reg_EXISTS 1

/*
 * Devicetree node: /leds
 *
 * Node identifier: DT_N_S_leds
 *
 * Binding (compatible = gpio-leds):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-leds.yaml
 *
 * Description:
 *   GPIO LEDs parent node
 */

/* Node parent (/) identifier: */
#define DT_N_S_leds_PARENT DT_N
#define DT_N_S_leds_FOREACH_CHILD(fn) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_leds_S_led_3)

/* Node's dependency ordinal: */
#define DT_N_S_leds_ORD 21

/* Ordinals for what this node depends on directly: */
#define DT_N_S_leds_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_leds_SUPPORTS_ORDS \
	22, /* /leds/led_0 */ \
	23, /* /leds/led_1 */ \
	24, /* /leds/led_2 */ \
	25, /* /leds/led_3 */

/* Existence and alternate IDs: */
#define DT_N_S_leds_EXISTS 1
#define DT_N_INST_0_gpio_leds DT_N_S_leds

/* Special property macros: */
#define DT_N_S_leds_REG_NUM 0
#define DT_N_S_leds_IRQ_NUM 0
#define DT_N_S_leds_COMPAT_MATCHES_gpio_leds 1
#define DT_N_S_leds_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_leds_P_compatible {"gpio-leds"}
#define DT_N_S_leds_P_compatible_IDX_0 "gpio-leds"
#define DT_N_S_leds_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_leds_P_compatible_LEN 1
#define DT_N_S_leds_P_compatible_EXISTS 1

/*
 * Devicetree node: /leds/led_0
 *
 * Node identifier: DT_N_S_leds_S_led_0
 *
 * Binding (compatible = gpio-leds):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-leds.yaml
 *
 * Description:
 *   GPIO LED child node
 */

/* Node parent (/leds) identifier: */
#define DT_N_S_leds_S_led_0_PARENT DT_N_S_leds
#define DT_N_S_leds_S_led_0_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_leds_S_led_0_ORD 22

/* Ordinals for what this node depends on directly: */
#define DT_N_S_leds_S_led_0_REQUIRES_ORDS \
	5, /* /soc/gpio@418c0500 */ \
	21, /* /leds */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_leds_S_led_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_leds_S_led_0_EXISTS 1
#define DT_N_ALIAS_led0     DT_N_S_leds_S_led_0
#define DT_N_NODELABEL_led0 DT_N_S_leds_S_led_0

/* Special property macros: */
#define DT_N_S_leds_S_led_0_REG_NUM 0
#define DT_N_S_leds_S_led_0_IRQ_NUM 0
#define DT_N_S_leds_S_led_0_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_PH DT_N_S_soc_S_gpio_418c0500
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_pin 28
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_flags 1
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_leds_S_led_0_P_gpios_LEN 1
#define DT_N_S_leds_S_led_0_P_gpios_EXISTS 1
#define DT_N_S_leds_S_led_0_P_label "Green LED 0"
#define DT_N_S_leds_S_led_0_P_label_EXISTS 1

/*
 * Devicetree node: /leds/led_1
 *
 * Node identifier: DT_N_S_leds_S_led_1
 *
 * Binding (compatible = gpio-leds):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-leds.yaml
 *
 * Description:
 *   GPIO LED child node
 */

/* Node parent (/leds) identifier: */
#define DT_N_S_leds_S_led_1_PARENT DT_N_S_leds
#define DT_N_S_leds_S_led_1_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_leds_S_led_1_ORD 23

/* Ordinals for what this node depends on directly: */
#define DT_N_S_leds_S_led_1_REQUIRES_ORDS \
	5, /* /soc/gpio@418c0500 */ \
	21, /* /leds */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_leds_S_led_1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_leds_S_led_1_EXISTS 1
#define DT_N_ALIAS_led1     DT_N_S_leds_S_led_1
#define DT_N_NODELABEL_led1 DT_N_S_leds_S_led_1

/* Special property macros: */
#define DT_N_S_leds_S_led_1_REG_NUM 0
#define DT_N_S_leds_S_led_1_IRQ_NUM 0
#define DT_N_S_leds_S_led_1_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_PH DT_N_S_soc_S_gpio_418c0500
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_pin 29
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_flags 1
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_leds_S_led_1_P_gpios_LEN 1
#define DT_N_S_leds_S_led_1_P_gpios_EXISTS 1
#define DT_N_S_leds_S_led_1_P_label "Green LED 1"
#define DT_N_S_leds_S_led_1_P_label_EXISTS 1

/*
 * Devicetree node: /leds/led_2
 *
 * Node identifier: DT_N_S_leds_S_led_2
 *
 * Binding (compatible = gpio-leds):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-leds.yaml
 *
 * Description:
 *   GPIO LED child node
 */

/* Node parent (/leds) identifier: */
#define DT_N_S_leds_S_led_2_PARENT DT_N_S_leds
#define DT_N_S_leds_S_led_2_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_leds_S_led_2_ORD 24

/* Ordinals for what this node depends on directly: */
#define DT_N_S_leds_S_led_2_REQUIRES_ORDS \
	5, /* /soc/gpio@418c0500 */ \
	21, /* /leds */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_leds_S_led_2_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_leds_S_led_2_EXISTS 1
#define DT_N_ALIAS_led2     DT_N_S_leds_S_led_2
#define DT_N_NODELABEL_led2 DT_N_S_leds_S_led_2

/* Special property macros: */
#define DT_N_S_leds_S_led_2_REG_NUM 0
#define DT_N_S_leds_S_led_2_IRQ_NUM 0
#define DT_N_S_leds_S_led_2_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_PH DT_N_S_soc_S_gpio_418c0500
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_pin 30
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_flags 1
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_leds_S_led_2_P_gpios_LEN 1
#define DT_N_S_leds_S_led_2_P_gpios_EXISTS 1
#define DT_N_S_leds_S_led_2_P_label "Green LED 2"
#define DT_N_S_leds_S_led_2_P_label_EXISTS 1

/*
 * Devicetree node: /leds/led_3
 *
 * Node identifier: DT_N_S_leds_S_led_3
 *
 * Binding (compatible = gpio-leds):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-leds.yaml
 *
 * Description:
 *   GPIO LED child node
 */

/* Node parent (/leds) identifier: */
#define DT_N_S_leds_S_led_3_PARENT DT_N_S_leds
#define DT_N_S_leds_S_led_3_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_leds_S_led_3_ORD 25

/* Ordinals for what this node depends on directly: */
#define DT_N_S_leds_S_led_3_REQUIRES_ORDS \
	5, /* /soc/gpio@418c0500 */ \
	21, /* /leds */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_leds_S_led_3_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_leds_S_led_3_EXISTS 1
#define DT_N_ALIAS_led3     DT_N_S_leds_S_led_3
#define DT_N_NODELABEL_led3 DT_N_S_leds_S_led_3

/* Special property macros: */
#define DT_N_S_leds_S_led_3_REG_NUM 0
#define DT_N_S_leds_S_led_3_IRQ_NUM 0
#define DT_N_S_leds_S_led_3_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_PH DT_N_S_soc_S_gpio_418c0500
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_pin 31
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_flags 1
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_leds_S_led_3_P_gpios_LEN 1
#define DT_N_S_leds_S_led_3_P_gpios_EXISTS 1
#define DT_N_S_leds_S_led_3_P_label "Green LED 3"
#define DT_N_S_leds_S_led_3_P_label_EXISTS 1

/*
 * Devicetree node: /reserved-memory
 *
 * Node identifier: DT_N_S_reserved_memory
 */

/* Node parent (/) identifier: */
#define DT_N_S_reserved_memory_PARENT DT_N
#define DT_N_S_reserved_memory_FOREACH_CHILD(fn) fn(DT_N_S_reserved_memory_S_memory_20070000)

/* Node's dependency ordinal: */
#define DT_N_S_reserved_memory_ORD 26

/* Ordinals for what this node depends on directly: */
#define DT_N_S_reserved_memory_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_reserved_memory_SUPPORTS_ORDS \
	27, /* /reserved-memory/memory@20070000 */

/* Existence and alternate IDs: */
#define DT_N_S_reserved_memory_EXISTS 1

/* Special property macros: */
#define DT_N_S_reserved_memory_REG_NUM 0
#define DT_N_S_reserved_memory_IRQ_NUM 0
#define DT_N_S_reserved_memory_STATUS_okay 1

/* (No generic property macros) */

/*
 * Devicetree node: /reserved-memory/memory@20070000
 *
 * Node identifier: DT_N_S_reserved_memory_S_memory_20070000
 */

/* Node parent (/reserved-memory) identifier: */
#define DT_N_S_reserved_memory_S_memory_20070000_PARENT DT_N_S_reserved_memory
#define DT_N_S_reserved_memory_S_memory_20070000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_reserved_memory_S_memory_20070000_ORD 27

/* Ordinals for what this node depends on directly: */
#define DT_N_S_reserved_memory_S_memory_20070000_REQUIRES_ORDS \
	26, /* /reserved-memory */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_reserved_memory_S_memory_20070000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_reserved_memory_S_memory_20070000_EXISTS 1
#define DT_N_NODELABEL_sram0_shared DT_N_S_reserved_memory_S_memory_20070000

/* Special property macros: */
#define DT_N_S_reserved_memory_S_memory_20070000_REG_NUM 1
#define DT_N_S_reserved_memory_S_memory_20070000_REG_IDX_0_EXISTS 1
#define DT_N_S_reserved_memory_S_memory_20070000_REG_IDX_0_VAL_ADDRESS 537329664 /* 0x20070000 */
#define DT_N_S_reserved_memory_S_memory_20070000_REG_IDX_0_VAL_SIZE 65536 /* 0x10000 */
#define DT_N_S_reserved_memory_S_memory_20070000_IRQ_NUM 0
#define DT_N_S_reserved_memory_S_memory_20070000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_reserved_memory_S_memory_20070000_P_reg {537329664 /* 0x20070000 */, 65536 /* 0x10000 */}
#define DT_N_S_reserved_memory_S_memory_20070000_P_reg_IDX_0 537329664
#define DT_N_S_reserved_memory_S_memory_20070000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_reserved_memory_S_memory_20070000_P_reg_IDX_1 65536
#define DT_N_S_reserved_memory_S_memory_20070000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_reserved_memory_S_memory_20070000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/interrupt-controller@e000e100
 *
 * Node identifier: DT_N_S_soc_S_interrupt_controller_e000e100
 *
 * Binding (compatible = arm,v8m-nvic):
 *   $ZEPHYR_BASE\dts\bindings\interrupt-controller\arm,v8m-nvic.yaml
 *
 * Description:
 *   ARMv8-M NVIC (Nested Vectored Interrupt Controller)
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_PARENT DT_N_S_soc
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_ORD 28

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_REQUIRES_ORDS \
	4, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_SUPPORTS_ORDS \
	29, /* /soc/clock@41005000 */ \
	31, /* /soc/egu@41014000 */ \
	34, /* /soc/gpiote@4100a000 */ \
	35, /* /soc/i2c@41013000 */ \
	36, /* /soc/ipc@41012000 */ \
	39, /* /soc/power@41005000 */ \
	40, /* /soc/random@41009000 */ \
	41, /* /soc/rtc@41011000 */ \
	42, /* /soc/rtc@41016000 */ \
	43, /* /soc/spi@41013000 */ \
	44, /* /soc/temp@41010000 */ \
	45, /* /soc/timer@4100c000 */ \
	46, /* /soc/timer@41018000 */ \
	47, /* /soc/timer@41019000 */ \
	49, /* /soc/uart@41013000 */ \
	52, /* /soc/watchdog@4100b000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_EXISTS 1
#define DT_N_INST_0_arm_v8m_nvic DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_NODELABEL_nvic      DT_N_S_soc_S_interrupt_controller_e000e100

/* Special property macros: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_NUM 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_VAL_ADDRESS 3758153984 /* 0xe000e100 */
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_VAL_SIZE 3072 /* 0xc00 */
#define DT_N_S_soc_S_interrupt_controller_e000e100_IRQ_NUM 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_MATCHES_arm_v8m_nvic 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg {3758153984 /* 0xe000e100 */, 3072 /* 0xc00 */}
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_0 3758153984
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_1 3072
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits 3
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_interrupt_controller 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_interrupt_controller_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible {"arm,v8m-nvic"}
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0 "arm,v8m-nvic"
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_LEN 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/clock@41005000
 *
 * Node identifier: DT_N_S_soc_S_clock_41005000
 *
 * Binding (compatible = nordic,nrf-clock):
 *   $ZEPHYR_BASE\dts\bindings\clock\nordic,nrf-clock.yaml
 *
 * Description:
 *   Nordic nRF clock control node
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_clock_41005000_PARENT DT_N_S_soc
#define DT_N_S_soc_S_clock_41005000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_clock_41005000_ORD 29

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_clock_41005000_REQUIRES_ORDS \
	4, /* /soc */ \
	28, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_clock_41005000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_clock_41005000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_clock DT_N_S_soc_S_clock_41005000
#define DT_N_NODELABEL_clock         DT_N_S_soc_S_clock_41005000

/* Special property macros: */
#define DT_N_S_soc_S_clock_41005000_REG_NUM 1
#define DT_N_S_soc_S_clock_41005000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_clock_41005000_REG_IDX_0_VAL_ADDRESS 1090539520 /* 0x41005000 */
#define DT_N_S_soc_S_clock_41005000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_clock_41005000_IRQ_NUM 1
#define DT_N_S_soc_S_clock_41005000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_clock_41005000_IRQ_IDX_0_VAL_irq 5
#define DT_N_S_soc_S_clock_41005000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_clock_41005000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_clock_41005000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_clock_41005000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_clock_41005000_COMPAT_MATCHES_nordic_nrf_clock 1
#define DT_N_S_soc_S_clock_41005000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_clock_41005000_P_label "CLOCK"
#define DT_N_S_soc_S_clock_41005000_P_label_EXISTS 1
#define DT_N_S_soc_S_clock_41005000_P_reg {1090539520 /* 0x41005000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_clock_41005000_P_reg_IDX_0 1090539520
#define DT_N_S_soc_S_clock_41005000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_clock_41005000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_clock_41005000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_clock_41005000_P_reg_EXISTS 1
#define DT_N_S_soc_S_clock_41005000_P_interrupts {5 /* 0x5 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_clock_41005000_P_interrupts_IDX_0 5
#define DT_N_S_soc_S_clock_41005000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_clock_41005000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_clock_41005000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_clock_41005000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_clock_41005000_P_status "okay"
#define DT_N_S_soc_S_clock_41005000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_clock_41005000_P_status_EXISTS 1
#define DT_N_S_soc_S_clock_41005000_P_compatible {"nordic,nrf-clock"}
#define DT_N_S_soc_S_clock_41005000_P_compatible_IDX_0 "nordic,nrf-clock"
#define DT_N_S_soc_S_clock_41005000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_clock_41005000_P_compatible_LEN 1
#define DT_N_S_soc_S_clock_41005000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/dppic@4100f000
 *
 * Node identifier: DT_N_S_soc_S_dppic_4100f000
 *
 * Binding (compatible = nordic,nrf-dppic):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-dppic.yaml
 *
 * Description:
 *   Nordic DPPIC (Distributed Programmable Peripheral Interconnect Controller)
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_dppic_4100f000_PARENT DT_N_S_soc
#define DT_N_S_soc_S_dppic_4100f000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_dppic_4100f000_ORD 30

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_dppic_4100f000_REQUIRES_ORDS \
	4, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_dppic_4100f000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_dppic_4100f000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_dppic DT_N_S_soc_S_dppic_4100f000
#define DT_N_NODELABEL_dppic         DT_N_S_soc_S_dppic_4100f000

/* Special property macros: */
#define DT_N_S_soc_S_dppic_4100f000_REG_NUM 1
#define DT_N_S_soc_S_dppic_4100f000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dppic_4100f000_REG_IDX_0_VAL_ADDRESS 1090580480 /* 0x4100f000 */
#define DT_N_S_soc_S_dppic_4100f000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_dppic_4100f000_IRQ_NUM 0
#define DT_N_S_soc_S_dppic_4100f000_COMPAT_MATCHES_nordic_nrf_dppic 1
#define DT_N_S_soc_S_dppic_4100f000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_dppic_4100f000_P_reg {1090580480 /* 0x4100f000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_dppic_4100f000_P_reg_IDX_0 1090580480
#define DT_N_S_soc_S_dppic_4100f000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dppic_4100f000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_dppic_4100f000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_dppic_4100f000_P_reg_EXISTS 1
#define DT_N_S_soc_S_dppic_4100f000_P_status "okay"
#define DT_N_S_soc_S_dppic_4100f000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_dppic_4100f000_P_status_EXISTS 1
#define DT_N_S_soc_S_dppic_4100f000_P_compatible {"nordic,nrf-dppic"}
#define DT_N_S_soc_S_dppic_4100f000_P_compatible_IDX_0 "nordic,nrf-dppic"
#define DT_N_S_soc_S_dppic_4100f000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dppic_4100f000_P_compatible_LEN 1
#define DT_N_S_soc_S_dppic_4100f000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_dppic_4100f000_P_label "DPPIC"
#define DT_N_S_soc_S_dppic_4100f000_P_label_EXISTS 1

/*
 * Devicetree node: /soc/egu@41014000
 *
 * Node identifier: DT_N_S_soc_S_egu_41014000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-egu.yaml
 *
 * Description:
 *   Nordic EGU (Event Generator Unit)
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_egu_41014000_PARENT DT_N_S_soc
#define DT_N_S_soc_S_egu_41014000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_egu_41014000_ORD 31

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_egu_41014000_REQUIRES_ORDS \
	4, /* /soc */ \
	28, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_egu_41014000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_egu_41014000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_egu DT_N_S_soc_S_egu_41014000
#define DT_N_NODELABEL_egu0        DT_N_S_soc_S_egu_41014000

/* Special property macros: */
#define DT_N_S_soc_S_egu_41014000_REG_NUM 1
#define DT_N_S_soc_S_egu_41014000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_41014000_REG_IDX_0_VAL_ADDRESS 1090600960 /* 0x41014000 */
#define DT_N_S_soc_S_egu_41014000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_egu_41014000_IRQ_NUM 1
#define DT_N_S_soc_S_egu_41014000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_41014000_IRQ_IDX_0_VAL_irq 20
#define DT_N_S_soc_S_egu_41014000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_egu_41014000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_41014000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_egu_41014000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_egu_41014000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_egu_41014000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_egu_41014000_P_reg {1090600960 /* 0x41014000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_egu_41014000_P_reg_IDX_0 1090600960
#define DT_N_S_soc_S_egu_41014000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_41014000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_egu_41014000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_egu_41014000_P_reg_EXISTS 1
#define DT_N_S_soc_S_egu_41014000_P_interrupts {20 /* 0x14 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_egu_41014000_P_interrupts_IDX_0 20
#define DT_N_S_soc_S_egu_41014000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_41014000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_egu_41014000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_egu_41014000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_egu_41014000_P_status "okay"
#define DT_N_S_soc_S_egu_41014000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_egu_41014000_P_status_EXISTS 1
#define DT_N_S_soc_S_egu_41014000_P_compatible {"nordic,nrf-egu"}
#define DT_N_S_soc_S_egu_41014000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_egu_41014000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_41014000_P_compatible_LEN 1
#define DT_N_S_soc_S_egu_41014000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_egu_41014000_P_label "EGU_0"
#define DT_N_S_soc_S_egu_41014000_P_label_EXISTS 1

/*
 * Devicetree node: /soc/ficr@1ff0000
 *
 * Node identifier: DT_N_S_soc_S_ficr_1ff0000
 *
 * Binding (compatible = nordic,nrf-ficr):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-ficr.yaml
 *
 * Description:
 *   Nordic FICR (Factory Information Configuration Registers)
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_ficr_1ff0000_PARENT DT_N_S_soc
#define DT_N_S_soc_S_ficr_1ff0000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_ficr_1ff0000_ORD 32

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_ficr_1ff0000_REQUIRES_ORDS \
	4, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_ficr_1ff0000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_ficr_1ff0000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_ficr DT_N_S_soc_S_ficr_1ff0000
#define DT_N_NODELABEL_ficr         DT_N_S_soc_S_ficr_1ff0000

/* Special property macros: */
#define DT_N_S_soc_S_ficr_1ff0000_REG_NUM 1
#define DT_N_S_soc_S_ficr_1ff0000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ficr_1ff0000_REG_IDX_0_VAL_ADDRESS 33488896 /* 0x1ff0000 */
#define DT_N_S_soc_S_ficr_1ff0000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_ficr_1ff0000_IRQ_NUM 0
#define DT_N_S_soc_S_ficr_1ff0000_COMPAT_MATCHES_nordic_nrf_ficr 1
#define DT_N_S_soc_S_ficr_1ff0000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_ficr_1ff0000_P_reg {33488896 /* 0x1ff0000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_ficr_1ff0000_P_reg_IDX_0 33488896
#define DT_N_S_soc_S_ficr_1ff0000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ficr_1ff0000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_ficr_1ff0000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_ficr_1ff0000_P_reg_EXISTS 1
#define DT_N_S_soc_S_ficr_1ff0000_P_status "okay"
#define DT_N_S_soc_S_ficr_1ff0000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_ficr_1ff0000_P_status_EXISTS 1
#define DT_N_S_soc_S_ficr_1ff0000_P_compatible {"nordic,nrf-ficr"}
#define DT_N_S_soc_S_ficr_1ff0000_P_compatible_IDX_0 "nordic,nrf-ficr"
#define DT_N_S_soc_S_ficr_1ff0000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ficr_1ff0000_P_compatible_LEN 1
#define DT_N_S_soc_S_ficr_1ff0000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/gpio@418c0800
 *
 * Node identifier: DT_N_S_soc_S_gpio_418c0800
 *
 * Binding (compatible = nordic,nrf-gpio):
 *   $ZEPHYR_BASE\dts\bindings\gpio\nordic,nrf-gpio.yaml
 *
 * Description:
 *   NRF5 GPIO node
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_gpio_418c0800_PARENT DT_N_S_soc
#define DT_N_S_soc_S_gpio_418c0800_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_gpio_418c0800_ORD 33

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_gpio_418c0800_REQUIRES_ORDS \
	4, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_gpio_418c0800_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_gpio_418c0800_EXISTS 1
#define DT_N_INST_1_nordic_nrf_gpio DT_N_S_soc_S_gpio_418c0800
#define DT_N_NODELABEL_gpio1        DT_N_S_soc_S_gpio_418c0800

/* Special property macros: */
#define DT_N_S_soc_S_gpio_418c0800_REG_NUM 1
#define DT_N_S_soc_S_gpio_418c0800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_418c0800_REG_IDX_0_VAL_ADDRESS 1099696128 /* 0x418c0800 */
#define DT_N_S_soc_S_gpio_418c0800_REG_IDX_0_VAL_SIZE 768 /* 0x300 */
#define DT_N_S_soc_S_gpio_418c0800_IRQ_NUM 0
#define DT_N_S_soc_S_gpio_418c0800_COMPAT_MATCHES_nordic_nrf_gpio 1
#define DT_N_S_soc_S_gpio_418c0800_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_gpio_418c0800_P_reg {1099696128 /* 0x418c0800 */, 768 /* 0x300 */}
#define DT_N_S_soc_S_gpio_418c0800_P_reg_IDX_0 1099696128
#define DT_N_S_soc_S_gpio_418c0800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_418c0800_P_reg_IDX_1 768
#define DT_N_S_soc_S_gpio_418c0800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_gpio_418c0800_P_reg_EXISTS 1
#define DT_N_S_soc_S_gpio_418c0800_P_label "GPIO_1"
#define DT_N_S_soc_S_gpio_418c0800_P_label_EXISTS 1
#define DT_N_S_soc_S_gpio_418c0800_P_gpio_controller 1
#define DT_N_S_soc_S_gpio_418c0800_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_gpio_418c0800_P_ngpios 16
#define DT_N_S_soc_S_gpio_418c0800_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_gpio_418c0800_P_status "okay"
#define DT_N_S_soc_S_gpio_418c0800_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_gpio_418c0800_P_status_EXISTS 1
#define DT_N_S_soc_S_gpio_418c0800_P_compatible {"nordic,nrf-gpio"}
#define DT_N_S_soc_S_gpio_418c0800_P_compatible_IDX_0 "nordic,nrf-gpio"
#define DT_N_S_soc_S_gpio_418c0800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_418c0800_P_compatible_LEN 1
#define DT_N_S_soc_S_gpio_418c0800_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/gpiote@4100a000
 *
 * Node identifier: DT_N_S_soc_S_gpiote_4100a000
 *
 * Binding (compatible = nordic,nrf-gpiote):
 *   $ZEPHYR_BASE\dts\bindings\gpio\nordic,nrf-gpiote.yaml
 *
 * Description:
 *   NRF5 GPIOTE node
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_gpiote_4100a000_PARENT DT_N_S_soc
#define DT_N_S_soc_S_gpiote_4100a000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_gpiote_4100a000_ORD 34

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_gpiote_4100a000_REQUIRES_ORDS \
	4, /* /soc */ \
	28, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_gpiote_4100a000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_gpiote_4100a000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_gpiote DT_N_S_soc_S_gpiote_4100a000
#define DT_N_NODELABEL_gpiote         DT_N_S_soc_S_gpiote_4100a000

/* Special property macros: */
#define DT_N_S_soc_S_gpiote_4100a000_REG_NUM 1
#define DT_N_S_soc_S_gpiote_4100a000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_4100a000_REG_IDX_0_VAL_ADDRESS 1090560000 /* 0x4100a000 */
#define DT_N_S_soc_S_gpiote_4100a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_gpiote_4100a000_IRQ_NUM 1
#define DT_N_S_soc_S_gpiote_4100a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_4100a000_IRQ_IDX_0_VAL_irq 10
#define DT_N_S_soc_S_gpiote_4100a000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_gpiote_4100a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_4100a000_IRQ_IDX_0_VAL_priority 5
#define DT_N_S_soc_S_gpiote_4100a000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_gpiote_4100a000_COMPAT_MATCHES_nordic_nrf_gpiote 1
#define DT_N_S_soc_S_gpiote_4100a000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_gpiote_4100a000_P_reg {1090560000 /* 0x4100a000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_gpiote_4100a000_P_reg_IDX_0 1090560000
#define DT_N_S_soc_S_gpiote_4100a000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_4100a000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_gpiote_4100a000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_gpiote_4100a000_P_reg_EXISTS 1
#define DT_N_S_soc_S_gpiote_4100a000_P_interrupts {10 /* 0xa */, 5 /* 0x5 */}
#define DT_N_S_soc_S_gpiote_4100a000_P_interrupts_IDX_0 10
#define DT_N_S_soc_S_gpiote_4100a000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_4100a000_P_interrupts_IDX_1 5
#define DT_N_S_soc_S_gpiote_4100a000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_gpiote_4100a000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_gpiote_4100a000_P_label "GPIOTE_0"
#define DT_N_S_soc_S_gpiote_4100a000_P_label_EXISTS 1
#define DT_N_S_soc_S_gpiote_4100a000_P_status "okay"
#define DT_N_S_soc_S_gpiote_4100a000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_gpiote_4100a000_P_status_EXISTS 1
#define DT_N_S_soc_S_gpiote_4100a000_P_compatible {"nordic,nrf-gpiote"}
#define DT_N_S_soc_S_gpiote_4100a000_P_compatible_IDX_0 "nordic,nrf-gpiote"
#define DT_N_S_soc_S_gpiote_4100a000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_4100a000_P_compatible_LEN 1
#define DT_N_S_soc_S_gpiote_4100a000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/i2c@41013000
 *
 * Node identifier: DT_N_S_soc_S_i2c_41013000
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_i2c_41013000_PARENT DT_N_S_soc
#define DT_N_S_soc_S_i2c_41013000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_i2c_41013000_ORD 35

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_i2c_41013000_REQUIRES_ORDS \
	4, /* /soc */ \
	28, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_i2c_41013000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_i2c_41013000_EXISTS 1
#define DT_N_NODELABEL_i2c0 DT_N_S_soc_S_i2c_41013000

/* Special property macros: */
#define DT_N_S_soc_S_i2c_41013000_REG_NUM 1
#define DT_N_S_soc_S_i2c_41013000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_41013000_REG_IDX_0_VAL_ADDRESS 1090596864 /* 0x41013000 */
#define DT_N_S_soc_S_i2c_41013000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_i2c_41013000_IRQ_NUM 1
#define DT_N_S_soc_S_i2c_41013000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_41013000_IRQ_IDX_0_VAL_irq 19
#define DT_N_S_soc_S_i2c_41013000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2c_41013000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_41013000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_i2c_41013000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2c_41013000_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_i2c_41013000_P_reg {1090596864 /* 0x41013000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_i2c_41013000_P_reg_IDX_0 1090596864
#define DT_N_S_soc_S_i2c_41013000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_41013000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_i2c_41013000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_41013000_P_reg_EXISTS 1
#define DT_N_S_soc_S_i2c_41013000_P_interrupts {19 /* 0x13 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_i2c_41013000_P_interrupts_IDX_0 19
#define DT_N_S_soc_S_i2c_41013000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_41013000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_i2c_41013000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_41013000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_i2c_41013000_P_status "disabled"
#define DT_N_S_soc_S_i2c_41013000_P_status_EXISTS 1
#define DT_N_S_soc_S_i2c_41013000_P_label "I2C_0"
#define DT_N_S_soc_S_i2c_41013000_P_label_EXISTS 1

/*
 * Devicetree node: /soc/ipc@41012000
 *
 * Node identifier: DT_N_S_soc_S_ipc_41012000
 *
 * Binding (compatible = nordic,nrf-ipc):
 *   $ZEPHYR_BASE\dts\bindings\ipm\nordic,nrf-ipc.yaml
 *
 * Description:
 *   Nordic nRF family IPC (Interprocessor Communication)
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_ipc_41012000_PARENT DT_N_S_soc
#define DT_N_S_soc_S_ipc_41012000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_ipc_41012000_ORD 36

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_ipc_41012000_REQUIRES_ORDS \
	4, /* /soc */ \
	28, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_ipc_41012000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_ipc_41012000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_ipc DT_N_S_soc_S_ipc_41012000
#define DT_N_NODELABEL_ipc         DT_N_S_soc_S_ipc_41012000

/* Special property macros: */
#define DT_N_S_soc_S_ipc_41012000_REG_NUM 1
#define DT_N_S_soc_S_ipc_41012000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ipc_41012000_REG_IDX_0_VAL_ADDRESS 1090592768 /* 0x41012000 */
#define DT_N_S_soc_S_ipc_41012000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_ipc_41012000_IRQ_NUM 1
#define DT_N_S_soc_S_ipc_41012000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ipc_41012000_IRQ_IDX_0_VAL_irq 18
#define DT_N_S_soc_S_ipc_41012000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_ipc_41012000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ipc_41012000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_ipc_41012000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_ipc_41012000_COMPAT_MATCHES_nordic_nrf_ipc 1
#define DT_N_S_soc_S_ipc_41012000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_ipc_41012000_P_reg {1090592768 /* 0x41012000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_ipc_41012000_P_reg_IDX_0 1090592768
#define DT_N_S_soc_S_ipc_41012000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ipc_41012000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_ipc_41012000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_ipc_41012000_P_reg_EXISTS 1
#define DT_N_S_soc_S_ipc_41012000_P_interrupts {18 /* 0x12 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_ipc_41012000_P_interrupts_IDX_0 18
#define DT_N_S_soc_S_ipc_41012000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ipc_41012000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_ipc_41012000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_ipc_41012000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_ipc_41012000_P_status "okay"
#define DT_N_S_soc_S_ipc_41012000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_ipc_41012000_P_status_EXISTS 1
#define DT_N_S_soc_S_ipc_41012000_P_compatible {"nordic,nrf-ipc"}
#define DT_N_S_soc_S_ipc_41012000_P_compatible_IDX_0 "nordic,nrf-ipc"
#define DT_N_S_soc_S_ipc_41012000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ipc_41012000_P_compatible_LEN 1
#define DT_N_S_soc_S_ipc_41012000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_ipc_41012000_P_label "IPC"
#define DT_N_S_soc_S_ipc_41012000_P_label_EXISTS 1

/*
 * Devicetree node: /soc/memory@20000000
 *
 * Node identifier: DT_N_S_soc_S_memory_20000000
 *
 * Binding (compatible = mmio-sram):
 *   $ZEPHYR_BASE\dts\bindings\sram\mmio-sram.yaml
 *
 * Description:
 *   Generic on-chip SRAM description
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_memory_20000000_PARENT DT_N_S_soc
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_memory_20000000_ORD 37

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_memory_20000000_REQUIRES_ORDS \
	4, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_memory_20000000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_memory_20000000_EXISTS 1
#define DT_N_INST_0_mmio_sram DT_N_S_soc_S_memory_20000000
#define DT_N_NODELABEL_sram0  DT_N_S_soc_S_memory_20000000

/* Special property macros: */
#define DT_N_S_soc_S_memory_20000000_REG_NUM 1
#define DT_N_S_soc_S_memory_20000000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_REG_IDX_0_VAL_ADDRESS 536870912 /* 0x20000000 */
#define DT_N_S_soc_S_memory_20000000_REG_IDX_0_VAL_SIZE 524288 /* 0x80000 */
#define DT_N_S_soc_S_memory_20000000_IRQ_NUM 0
#define DT_N_S_soc_S_memory_20000000_COMPAT_MATCHES_mmio_sram 1
#define DT_N_S_soc_S_memory_20000000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_memory_20000000_P_reg {536870912 /* 0x20000000 */, 524288 /* 0x80000 */}
#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_0 536870912
#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_1 524288
#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_reg_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_compatible {"mmio-sram"}
#define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0 "mmio-sram"
#define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_compatible_LEN 1
#define DT_N_S_soc_S_memory_20000000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/memory@21000000
 *
 * Node identifier: DT_N_S_soc_S_memory_21000000
 *
 * Binding (compatible = mmio-sram):
 *   $ZEPHYR_BASE\dts\bindings\sram\mmio-sram.yaml
 *
 * Description:
 *   Generic on-chip SRAM description
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_memory_21000000_PARENT DT_N_S_soc
#define DT_N_S_soc_S_memory_21000000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_memory_21000000_ORD 38

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_memory_21000000_REQUIRES_ORDS \
	4, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_memory_21000000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_memory_21000000_EXISTS 1
#define DT_N_INST_1_mmio_sram DT_N_S_soc_S_memory_21000000
#define DT_N_NODELABEL_sram1  DT_N_S_soc_S_memory_21000000

/* Special property macros: */
#define DT_N_S_soc_S_memory_21000000_REG_NUM 1
#define DT_N_S_soc_S_memory_21000000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_21000000_REG_IDX_0_VAL_ADDRESS 553648128 /* 0x21000000 */
#define DT_N_S_soc_S_memory_21000000_REG_IDX_0_VAL_SIZE 65536 /* 0x10000 */
#define DT_N_S_soc_S_memory_21000000_IRQ_NUM 0
#define DT_N_S_soc_S_memory_21000000_COMPAT_MATCHES_mmio_sram 1
#define DT_N_S_soc_S_memory_21000000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_memory_21000000_P_reg {553648128 /* 0x21000000 */, 65536 /* 0x10000 */}
#define DT_N_S_soc_S_memory_21000000_P_reg_IDX_0 553648128
#define DT_N_S_soc_S_memory_21000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_21000000_P_reg_IDX_1 65536
#define DT_N_S_soc_S_memory_21000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_memory_21000000_P_reg_EXISTS 1
#define DT_N_S_soc_S_memory_21000000_P_compatible {"mmio-sram"}
#define DT_N_S_soc_S_memory_21000000_P_compatible_IDX_0 "mmio-sram"
#define DT_N_S_soc_S_memory_21000000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_21000000_P_compatible_LEN 1
#define DT_N_S_soc_S_memory_21000000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/power@41005000
 *
 * Node identifier: DT_N_S_soc_S_power_41005000
 *
 * Binding (compatible = nordic,nrf-power):
 *   $ZEPHYR_BASE\dts\bindings\power\nordic,nrf-power.yaml
 *
 * Description:
 *   Nordic nRF power control node
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_power_41005000_PARENT DT_N_S_soc
#define DT_N_S_soc_S_power_41005000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_power_41005000_ORD 39

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_power_41005000_REQUIRES_ORDS \
	4, /* /soc */ \
	28, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_power_41005000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_power_41005000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_power DT_N_S_soc_S_power_41005000
#define DT_N_NODELABEL_power         DT_N_S_soc_S_power_41005000

/* Special property macros: */
#define DT_N_S_soc_S_power_41005000_REG_NUM 1
#define DT_N_S_soc_S_power_41005000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_power_41005000_REG_IDX_0_VAL_ADDRESS 1090539520 /* 0x41005000 */
#define DT_N_S_soc_S_power_41005000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_power_41005000_IRQ_NUM 1
#define DT_N_S_soc_S_power_41005000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_power_41005000_IRQ_IDX_0_VAL_irq 5
#define DT_N_S_soc_S_power_41005000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_power_41005000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_power_41005000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_power_41005000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_power_41005000_COMPAT_MATCHES_nordic_nrf_power 1
#define DT_N_S_soc_S_power_41005000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_power_41005000_P_reg {1090539520 /* 0x41005000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_power_41005000_P_reg_IDX_0 1090539520
#define DT_N_S_soc_S_power_41005000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_power_41005000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_power_41005000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_power_41005000_P_reg_EXISTS 1
#define DT_N_S_soc_S_power_41005000_P_interrupts {5 /* 0x5 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_power_41005000_P_interrupts_IDX_0 5
#define DT_N_S_soc_S_power_41005000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_power_41005000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_power_41005000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_power_41005000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_power_41005000_P_status "okay"
#define DT_N_S_soc_S_power_41005000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_power_41005000_P_status_EXISTS 1
#define DT_N_S_soc_S_power_41005000_P_compatible {"nordic,nrf-power"}
#define DT_N_S_soc_S_power_41005000_P_compatible_IDX_0 "nordic,nrf-power"
#define DT_N_S_soc_S_power_41005000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_power_41005000_P_compatible_LEN 1
#define DT_N_S_soc_S_power_41005000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/random@41009000
 *
 * Node identifier: DT_N_S_soc_S_random_41009000
 *
 * Binding (compatible = nordic,nrf-rng):
 *   $ZEPHYR_BASE\dts\bindings\rng\nordic,nrf-rng.yaml
 *
 * Description:
 *   Nordic nRF family RNG (Random Number Generator)
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_random_41009000_PARENT DT_N_S_soc
#define DT_N_S_soc_S_random_41009000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_random_41009000_ORD 40

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_random_41009000_REQUIRES_ORDS \
	4, /* /soc */ \
	28, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_random_41009000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_random_41009000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_rng DT_N_S_soc_S_random_41009000
#define DT_N_NODELABEL_rng         DT_N_S_soc_S_random_41009000

/* Special property macros: */
#define DT_N_S_soc_S_random_41009000_REG_NUM 1
#define DT_N_S_soc_S_random_41009000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_random_41009000_REG_IDX_0_VAL_ADDRESS 1090555904 /* 0x41009000 */
#define DT_N_S_soc_S_random_41009000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_random_41009000_IRQ_NUM 1
#define DT_N_S_soc_S_random_41009000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_random_41009000_IRQ_IDX_0_VAL_irq 9
#define DT_N_S_soc_S_random_41009000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_random_41009000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_random_41009000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_random_41009000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_random_41009000_COMPAT_MATCHES_nordic_nrf_rng 1
#define DT_N_S_soc_S_random_41009000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_random_41009000_P_reg {1090555904 /* 0x41009000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_random_41009000_P_reg_IDX_0 1090555904
#define DT_N_S_soc_S_random_41009000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_random_41009000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_random_41009000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_random_41009000_P_reg_EXISTS 1
#define DT_N_S_soc_S_random_41009000_P_interrupts {9 /* 0x9 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_random_41009000_P_interrupts_IDX_0 9
#define DT_N_S_soc_S_random_41009000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_random_41009000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_random_41009000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_random_41009000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_random_41009000_P_status "okay"
#define DT_N_S_soc_S_random_41009000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_random_41009000_P_status_EXISTS 1
#define DT_N_S_soc_S_random_41009000_P_compatible {"nordic,nrf-rng"}
#define DT_N_S_soc_S_random_41009000_P_compatible_IDX_0 "nordic,nrf-rng"
#define DT_N_S_soc_S_random_41009000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_random_41009000_P_compatible_LEN 1
#define DT_N_S_soc_S_random_41009000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_random_41009000_P_label "RNG"
#define DT_N_S_soc_S_random_41009000_P_label_EXISTS 1

/*
 * Devicetree node: /soc/rtc@41011000
 *
 * Node identifier: DT_N_S_soc_S_rtc_41011000
 *
 * Binding (compatible = nordic,nrf-rtc):
 *   $ZEPHYR_BASE\dts\bindings\rtc\nordic,nrf-rtc.yaml
 *
 * Description:
 *   Nordic nRF RTC (Real-Time Counter)
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_rtc_41011000_PARENT DT_N_S_soc
#define DT_N_S_soc_S_rtc_41011000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_rtc_41011000_ORD 41

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_rtc_41011000_REQUIRES_ORDS \
	4, /* /soc */ \
	28, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_rtc_41011000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_rtc_41011000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_rtc DT_N_S_soc_S_rtc_41011000
#define DT_N_NODELABEL_rtc0        DT_N_S_soc_S_rtc_41011000

/* Special property macros: */
#define DT_N_S_soc_S_rtc_41011000_REG_NUM 1
#define DT_N_S_soc_S_rtc_41011000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_41011000_REG_IDX_0_VAL_ADDRESS 1090588672 /* 0x41011000 */
#define DT_N_S_soc_S_rtc_41011000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_rtc_41011000_IRQ_NUM 1
#define DT_N_S_soc_S_rtc_41011000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_41011000_IRQ_IDX_0_VAL_irq 17
#define DT_N_S_soc_S_rtc_41011000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_rtc_41011000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_41011000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_rtc_41011000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_rtc_41011000_COMPAT_MATCHES_nordic_nrf_rtc 1
#define DT_N_S_soc_S_rtc_41011000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_rtc_41011000_P_reg {1090588672 /* 0x41011000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_rtc_41011000_P_reg_IDX_0 1090588672
#define DT_N_S_soc_S_rtc_41011000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_41011000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_rtc_41011000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_rtc_41011000_P_reg_EXISTS 1
#define DT_N_S_soc_S_rtc_41011000_P_cc_num 4
#define DT_N_S_soc_S_rtc_41011000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_rtc_41011000_P_ppi_wrap 0
#define DT_N_S_soc_S_rtc_41011000_P_ppi_wrap_EXISTS 1
#define DT_N_S_soc_S_rtc_41011000_P_fixed_top 0
#define DT_N_S_soc_S_rtc_41011000_P_fixed_top_EXISTS 1
#define DT_N_S_soc_S_rtc_41011000_P_label "RTC_0"
#define DT_N_S_soc_S_rtc_41011000_P_label_EXISTS 1
#define DT_N_S_soc_S_rtc_41011000_P_interrupts {17 /* 0x11 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_rtc_41011000_P_interrupts_IDX_0 17
#define DT_N_S_soc_S_rtc_41011000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_41011000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_rtc_41011000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_rtc_41011000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_rtc_41011000_P_status "okay"
#define DT_N_S_soc_S_rtc_41011000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_rtc_41011000_P_status_EXISTS 1
#define DT_N_S_soc_S_rtc_41011000_P_compatible {"nordic,nrf-rtc"}
#define DT_N_S_soc_S_rtc_41011000_P_compatible_IDX_0 "nordic,nrf-rtc"
#define DT_N_S_soc_S_rtc_41011000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_41011000_P_compatible_LEN 1
#define DT_N_S_soc_S_rtc_41011000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/rtc@41016000
 *
 * Node identifier: DT_N_S_soc_S_rtc_41016000
 *
 * Binding (compatible = nordic,nrf-rtc):
 *   $ZEPHYR_BASE\dts\bindings\rtc\nordic,nrf-rtc.yaml
 *
 * Description:
 *   Nordic nRF RTC (Real-Time Counter)
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_rtc_41016000_PARENT DT_N_S_soc
#define DT_N_S_soc_S_rtc_41016000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_rtc_41016000_ORD 42

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_rtc_41016000_REQUIRES_ORDS \
	4, /* /soc */ \
	28, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_rtc_41016000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_rtc_41016000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_rtc DT_N_S_soc_S_rtc_41016000
#define DT_N_NODELABEL_rtc1        DT_N_S_soc_S_rtc_41016000

/* Special property macros: */
#define DT_N_S_soc_S_rtc_41016000_REG_NUM 1
#define DT_N_S_soc_S_rtc_41016000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_41016000_REG_IDX_0_VAL_ADDRESS 1090609152 /* 0x41016000 */
#define DT_N_S_soc_S_rtc_41016000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_rtc_41016000_IRQ_NUM 1
#define DT_N_S_soc_S_rtc_41016000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_41016000_IRQ_IDX_0_VAL_irq 22
#define DT_N_S_soc_S_rtc_41016000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_rtc_41016000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_41016000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_rtc_41016000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_rtc_41016000_COMPAT_MATCHES_nordic_nrf_rtc 1
#define DT_N_S_soc_S_rtc_41016000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_rtc_41016000_P_reg {1090609152 /* 0x41016000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_rtc_41016000_P_reg_IDX_0 1090609152
#define DT_N_S_soc_S_rtc_41016000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_41016000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_rtc_41016000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_rtc_41016000_P_reg_EXISTS 1
#define DT_N_S_soc_S_rtc_41016000_P_cc_num 4
#define DT_N_S_soc_S_rtc_41016000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_rtc_41016000_P_ppi_wrap 0
#define DT_N_S_soc_S_rtc_41016000_P_ppi_wrap_EXISTS 1
#define DT_N_S_soc_S_rtc_41016000_P_fixed_top 0
#define DT_N_S_soc_S_rtc_41016000_P_fixed_top_EXISTS 1
#define DT_N_S_soc_S_rtc_41016000_P_label "RTC_1"
#define DT_N_S_soc_S_rtc_41016000_P_label_EXISTS 1
#define DT_N_S_soc_S_rtc_41016000_P_interrupts {22 /* 0x16 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_rtc_41016000_P_interrupts_IDX_0 22
#define DT_N_S_soc_S_rtc_41016000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_41016000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_rtc_41016000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_rtc_41016000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_rtc_41016000_P_status "okay"
#define DT_N_S_soc_S_rtc_41016000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_rtc_41016000_P_status_EXISTS 1
#define DT_N_S_soc_S_rtc_41016000_P_compatible {"nordic,nrf-rtc"}
#define DT_N_S_soc_S_rtc_41016000_P_compatible_IDX_0 "nordic,nrf-rtc"
#define DT_N_S_soc_S_rtc_41016000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_41016000_P_compatible_LEN 1
#define DT_N_S_soc_S_rtc_41016000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/spi@41013000
 *
 * Node identifier: DT_N_S_soc_S_spi_41013000
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_spi_41013000_PARENT DT_N_S_soc
#define DT_N_S_soc_S_spi_41013000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_spi_41013000_ORD 43

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_spi_41013000_REQUIRES_ORDS \
	4, /* /soc */ \
	28, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_spi_41013000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_spi_41013000_EXISTS 1
#define DT_N_NODELABEL_spi0 DT_N_S_soc_S_spi_41013000

/* Special property macros: */
#define DT_N_S_soc_S_spi_41013000_REG_NUM 1
#define DT_N_S_soc_S_spi_41013000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_41013000_REG_IDX_0_VAL_ADDRESS 1090596864 /* 0x41013000 */
#define DT_N_S_soc_S_spi_41013000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_spi_41013000_IRQ_NUM 1
#define DT_N_S_soc_S_spi_41013000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_41013000_IRQ_IDX_0_VAL_irq 19
#define DT_N_S_soc_S_spi_41013000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_spi_41013000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_41013000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_spi_41013000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_spi_41013000_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_spi_41013000_P_reg {1090596864 /* 0x41013000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_spi_41013000_P_reg_IDX_0 1090596864
#define DT_N_S_soc_S_spi_41013000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_41013000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_spi_41013000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_41013000_P_reg_EXISTS 1
#define DT_N_S_soc_S_spi_41013000_P_interrupts {19 /* 0x13 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_spi_41013000_P_interrupts_IDX_0 19
#define DT_N_S_soc_S_spi_41013000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_41013000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_spi_41013000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_41013000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_spi_41013000_P_status "disabled"
#define DT_N_S_soc_S_spi_41013000_P_status_EXISTS 1
#define DT_N_S_soc_S_spi_41013000_P_label "SPI_0"
#define DT_N_S_soc_S_spi_41013000_P_label_EXISTS 1

/*
 * Devicetree node: /soc/temp@41010000
 *
 * Node identifier: DT_N_S_soc_S_temp_41010000
 *
 * Binding (compatible = nordic,nrf-temp):
 *   $ZEPHYR_BASE\dts\bindings\sensor\nordic,nrf-temp.yaml
 *
 * Description:
 *   Nordic nRF family TEMP node
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_temp_41010000_PARENT DT_N_S_soc
#define DT_N_S_soc_S_temp_41010000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_temp_41010000_ORD 44

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_temp_41010000_REQUIRES_ORDS \
	4, /* /soc */ \
	28, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_temp_41010000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_temp_41010000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_temp DT_N_S_soc_S_temp_41010000
#define DT_N_NODELABEL_temp         DT_N_S_soc_S_temp_41010000

/* Special property macros: */
#define DT_N_S_soc_S_temp_41010000_REG_NUM 1
#define DT_N_S_soc_S_temp_41010000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_temp_41010000_REG_IDX_0_VAL_ADDRESS 1090584576 /* 0x41010000 */
#define DT_N_S_soc_S_temp_41010000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_temp_41010000_IRQ_NUM 1
#define DT_N_S_soc_S_temp_41010000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_temp_41010000_IRQ_IDX_0_VAL_irq 16
#define DT_N_S_soc_S_temp_41010000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_temp_41010000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_temp_41010000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_temp_41010000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_temp_41010000_COMPAT_MATCHES_nordic_nrf_temp 1
#define DT_N_S_soc_S_temp_41010000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_temp_41010000_P_reg {1090584576 /* 0x41010000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_temp_41010000_P_reg_IDX_0 1090584576
#define DT_N_S_soc_S_temp_41010000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_temp_41010000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_temp_41010000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_temp_41010000_P_reg_EXISTS 1
#define DT_N_S_soc_S_temp_41010000_P_interrupts {16 /* 0x10 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_temp_41010000_P_interrupts_IDX_0 16
#define DT_N_S_soc_S_temp_41010000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_temp_41010000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_temp_41010000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_temp_41010000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_temp_41010000_P_label "TEMP_0"
#define DT_N_S_soc_S_temp_41010000_P_label_EXISTS 1
#define DT_N_S_soc_S_temp_41010000_P_status "okay"
#define DT_N_S_soc_S_temp_41010000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_temp_41010000_P_status_EXISTS 1
#define DT_N_S_soc_S_temp_41010000_P_compatible {"nordic,nrf-temp"}
#define DT_N_S_soc_S_temp_41010000_P_compatible_IDX_0 "nordic,nrf-temp"
#define DT_N_S_soc_S_temp_41010000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_temp_41010000_P_compatible_LEN 1
#define DT_N_S_soc_S_temp_41010000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/timer@4100c000
 *
 * Node identifier: DT_N_S_soc_S_timer_4100c000
 *
 * Binding (compatible = nordic,nrf-timer):
 *   $ZEPHYR_BASE\dts\bindings\timer\nordic,nrf-timer.yaml
 *
 * Description:
 *   Nordic nRF timer node
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timer_4100c000_PARENT DT_N_S_soc
#define DT_N_S_soc_S_timer_4100c000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timer_4100c000_ORD 45

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timer_4100c000_REQUIRES_ORDS \
	4, /* /soc */ \
	28, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timer_4100c000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timer_4100c000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_timer DT_N_S_soc_S_timer_4100c000
#define DT_N_NODELABEL_timer0        DT_N_S_soc_S_timer_4100c000

/* Special property macros: */
#define DT_N_S_soc_S_timer_4100c000_REG_NUM 1
#define DT_N_S_soc_S_timer_4100c000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4100c000_REG_IDX_0_VAL_ADDRESS 1090568192 /* 0x4100c000 */
#define DT_N_S_soc_S_timer_4100c000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_timer_4100c000_IRQ_NUM 1
#define DT_N_S_soc_S_timer_4100c000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4100c000_IRQ_IDX_0_VAL_irq 12
#define DT_N_S_soc_S_timer_4100c000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timer_4100c000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4100c000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_timer_4100c000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timer_4100c000_COMPAT_MATCHES_nordic_nrf_timer 1
#define DT_N_S_soc_S_timer_4100c000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_timer_4100c000_P_reg {1090568192 /* 0x4100c000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_timer_4100c000_P_reg_IDX_0 1090568192
#define DT_N_S_soc_S_timer_4100c000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4100c000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_timer_4100c000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timer_4100c000_P_reg_EXISTS 1
#define DT_N_S_soc_S_timer_4100c000_P_cc_num 8
#define DT_N_S_soc_S_timer_4100c000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_timer_4100c000_P_interrupts {12 /* 0xc */, 1 /* 0x1 */}
#define DT_N_S_soc_S_timer_4100c000_P_interrupts_IDX_0 12
#define DT_N_S_soc_S_timer_4100c000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4100c000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_timer_4100c000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timer_4100c000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timer_4100c000_P_label "TIMER0"
#define DT_N_S_soc_S_timer_4100c000_P_label_EXISTS 1
#define DT_N_S_soc_S_timer_4100c000_P_prescaler 0
#define DT_N_S_soc_S_timer_4100c000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_timer_4100c000_P_status "okay"
#define DT_N_S_soc_S_timer_4100c000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_timer_4100c000_P_status_EXISTS 1
#define DT_N_S_soc_S_timer_4100c000_P_compatible {"nordic,nrf-timer"}
#define DT_N_S_soc_S_timer_4100c000_P_compatible_IDX_0 "nordic,nrf-timer"
#define DT_N_S_soc_S_timer_4100c000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4100c000_P_compatible_LEN 1
#define DT_N_S_soc_S_timer_4100c000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/timer@41018000
 *
 * Node identifier: DT_N_S_soc_S_timer_41018000
 *
 * Binding (compatible = nordic,nrf-timer):
 *   $ZEPHYR_BASE\dts\bindings\timer\nordic,nrf-timer.yaml
 *
 * Description:
 *   Nordic nRF timer node
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timer_41018000_PARENT DT_N_S_soc
#define DT_N_S_soc_S_timer_41018000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timer_41018000_ORD 46

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timer_41018000_REQUIRES_ORDS \
	4, /* /soc */ \
	28, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timer_41018000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timer_41018000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_timer DT_N_S_soc_S_timer_41018000
#define DT_N_NODELABEL_timer1        DT_N_S_soc_S_timer_41018000

/* Special property macros: */
#define DT_N_S_soc_S_timer_41018000_REG_NUM 1
#define DT_N_S_soc_S_timer_41018000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_41018000_REG_IDX_0_VAL_ADDRESS 1090617344 /* 0x41018000 */
#define DT_N_S_soc_S_timer_41018000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_timer_41018000_IRQ_NUM 1
#define DT_N_S_soc_S_timer_41018000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_41018000_IRQ_IDX_0_VAL_irq 24
#define DT_N_S_soc_S_timer_41018000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timer_41018000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_41018000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_timer_41018000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timer_41018000_COMPAT_MATCHES_nordic_nrf_timer 1
#define DT_N_S_soc_S_timer_41018000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_timer_41018000_P_reg {1090617344 /* 0x41018000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_timer_41018000_P_reg_IDX_0 1090617344
#define DT_N_S_soc_S_timer_41018000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_41018000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_timer_41018000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timer_41018000_P_reg_EXISTS 1
#define DT_N_S_soc_S_timer_41018000_P_cc_num 8
#define DT_N_S_soc_S_timer_41018000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_timer_41018000_P_interrupts {24 /* 0x18 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_timer_41018000_P_interrupts_IDX_0 24
#define DT_N_S_soc_S_timer_41018000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_41018000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_timer_41018000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timer_41018000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timer_41018000_P_label "TIMER1"
#define DT_N_S_soc_S_timer_41018000_P_label_EXISTS 1
#define DT_N_S_soc_S_timer_41018000_P_prescaler 0
#define DT_N_S_soc_S_timer_41018000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_timer_41018000_P_status "okay"
#define DT_N_S_soc_S_timer_41018000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_timer_41018000_P_status_EXISTS 1
#define DT_N_S_soc_S_timer_41018000_P_compatible {"nordic,nrf-timer"}
#define DT_N_S_soc_S_timer_41018000_P_compatible_IDX_0 "nordic,nrf-timer"
#define DT_N_S_soc_S_timer_41018000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_41018000_P_compatible_LEN 1
#define DT_N_S_soc_S_timer_41018000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/timer@41019000
 *
 * Node identifier: DT_N_S_soc_S_timer_41019000
 *
 * Binding (compatible = nordic,nrf-timer):
 *   $ZEPHYR_BASE\dts\bindings\timer\nordic,nrf-timer.yaml
 *
 * Description:
 *   Nordic nRF timer node
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timer_41019000_PARENT DT_N_S_soc
#define DT_N_S_soc_S_timer_41019000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timer_41019000_ORD 47

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timer_41019000_REQUIRES_ORDS \
	4, /* /soc */ \
	28, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timer_41019000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timer_41019000_EXISTS 1
#define DT_N_INST_2_nordic_nrf_timer DT_N_S_soc_S_timer_41019000
#define DT_N_NODELABEL_timer2        DT_N_S_soc_S_timer_41019000

/* Special property macros: */
#define DT_N_S_soc_S_timer_41019000_REG_NUM 1
#define DT_N_S_soc_S_timer_41019000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_41019000_REG_IDX_0_VAL_ADDRESS 1090621440 /* 0x41019000 */
#define DT_N_S_soc_S_timer_41019000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_timer_41019000_IRQ_NUM 1
#define DT_N_S_soc_S_timer_41019000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_41019000_IRQ_IDX_0_VAL_irq 25
#define DT_N_S_soc_S_timer_41019000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timer_41019000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_41019000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_timer_41019000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timer_41019000_COMPAT_MATCHES_nordic_nrf_timer 1
#define DT_N_S_soc_S_timer_41019000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_timer_41019000_P_reg {1090621440 /* 0x41019000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_timer_41019000_P_reg_IDX_0 1090621440
#define DT_N_S_soc_S_timer_41019000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_41019000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_timer_41019000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timer_41019000_P_reg_EXISTS 1
#define DT_N_S_soc_S_timer_41019000_P_cc_num 8
#define DT_N_S_soc_S_timer_41019000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_timer_41019000_P_interrupts {25 /* 0x19 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_timer_41019000_P_interrupts_IDX_0 25
#define DT_N_S_soc_S_timer_41019000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_41019000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_timer_41019000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timer_41019000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timer_41019000_P_label "TIMER2"
#define DT_N_S_soc_S_timer_41019000_P_label_EXISTS 1
#define DT_N_S_soc_S_timer_41019000_P_prescaler 0
#define DT_N_S_soc_S_timer_41019000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_timer_41019000_P_status "okay"
#define DT_N_S_soc_S_timer_41019000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_timer_41019000_P_status_EXISTS 1
#define DT_N_S_soc_S_timer_41019000_P_compatible {"nordic,nrf-timer"}
#define DT_N_S_soc_S_timer_41019000_P_compatible_IDX_0 "nordic,nrf-timer"
#define DT_N_S_soc_S_timer_41019000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_41019000_P_compatible_LEN 1
#define DT_N_S_soc_S_timer_41019000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/timer@e000e010
 *
 * Node identifier: DT_N_S_soc_S_timer_e000e010
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timer_e000e010_PARENT DT_N_S_soc
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timer_e000e010_ORD 48

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timer_e000e010_REQUIRES_ORDS \
	4, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timer_e000e010_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timer_e000e010_EXISTS 1
#define DT_N_INST_0_arm_armv8m_systick DT_N_S_soc_S_timer_e000e010
#define DT_N_NODELABEL_systick         DT_N_S_soc_S_timer_e000e010

/* Special property macros: */
#define DT_N_S_soc_S_timer_e000e010_REG_NUM 1
#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_VAL_ADDRESS 3758153744 /* 0xe000e010 */
#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_VAL_SIZE 16 /* 0x10 */
#define DT_N_S_soc_S_timer_e000e010_IRQ_NUM 0
#define DT_N_S_soc_S_timer_e000e010_COMPAT_MATCHES_arm_armv8m_systick 1
#define DT_N_S_soc_S_timer_e000e010_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_timer_e000e010_P_compatible {"arm,armv8m-systick"}
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0 "arm,armv8m-systick"
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_compatible_LEN 1
#define DT_N_S_soc_S_timer_e000e010_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_reg {3758153744 /* 0xe000e010 */, 16 /* 0x10 */}
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_0 3758153744
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_1 16
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_reg_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_status "disabled"
#define DT_N_S_soc_S_timer_e000e010_P_status_EXISTS 1

/*
 * Devicetree node: /soc/uart@41013000
 *
 * Node identifier: DT_N_S_soc_S_uart_41013000
 *
 * Binding (compatible = nordic,nrf-uarte):
 *   $ZEPHYR_BASE\dts\bindings\serial\nordic,nrf-uarte.yaml
 *
 * Description:
 *   Nordic UARTE
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_uart_41013000_PARENT DT_N_S_soc
#define DT_N_S_soc_S_uart_41013000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_uart_41013000_ORD 49

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_uart_41013000_REQUIRES_ORDS \
	4, /* /soc */ \
	28, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_uart_41013000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_uart_41013000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_uarte DT_N_S_soc_S_uart_41013000
#define DT_N_NODELABEL_uart0         DT_N_S_soc_S_uart_41013000

/* Special property macros: */
#define DT_N_S_soc_S_uart_41013000_REG_NUM 1
#define DT_N_S_soc_S_uart_41013000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_41013000_REG_IDX_0_VAL_ADDRESS 1090596864 /* 0x41013000 */
#define DT_N_S_soc_S_uart_41013000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_uart_41013000_IRQ_NUM 1
#define DT_N_S_soc_S_uart_41013000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_41013000_IRQ_IDX_0_VAL_irq 19
#define DT_N_S_soc_S_uart_41013000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_uart_41013000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_41013000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_uart_41013000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_uart_41013000_COMPAT_MATCHES_nordic_nrf_uarte 1
#define DT_N_S_soc_S_uart_41013000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_uart_41013000_P_reg {1090596864 /* 0x41013000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_uart_41013000_P_reg_IDX_0 1090596864
#define DT_N_S_soc_S_uart_41013000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_41013000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_uart_41013000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_uart_41013000_P_reg_EXISTS 1
#define DT_N_S_soc_S_uart_41013000_P_interrupts {19 /* 0x13 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_uart_41013000_P_interrupts_IDX_0 19
#define DT_N_S_soc_S_uart_41013000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_41013000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_uart_41013000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_uart_41013000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_uart_41013000_P_tx_pin 33
#define DT_N_S_soc_S_uart_41013000_P_tx_pin_EXISTS 1
#define DT_N_S_soc_S_uart_41013000_P_rx_pin 32
#define DT_N_S_soc_S_uart_41013000_P_rx_pin_EXISTS 1
#define DT_N_S_soc_S_uart_41013000_P_rts_pin 11
#define DT_N_S_soc_S_uart_41013000_P_rts_pin_EXISTS 1
#define DT_N_S_soc_S_uart_41013000_P_cts_pin 10
#define DT_N_S_soc_S_uart_41013000_P_cts_pin_EXISTS 1
#define DT_N_S_soc_S_uart_41013000_P_current_speed 115200
#define DT_N_S_soc_S_uart_41013000_P_current_speed_EXISTS 1
#define DT_N_S_soc_S_uart_41013000_P_label "UART_0"
#define DT_N_S_soc_S_uart_41013000_P_label_EXISTS 1
#define DT_N_S_soc_S_uart_41013000_P_hw_flow_control 0
#define DT_N_S_soc_S_uart_41013000_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_uart_41013000_P_status "okay"
#define DT_N_S_soc_S_uart_41013000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_uart_41013000_P_status_EXISTS 1
#define DT_N_S_soc_S_uart_41013000_P_compatible {"nordic,nrf-uarte"}
#define DT_N_S_soc_S_uart_41013000_P_compatible_IDX_0 "nordic,nrf-uarte"
#define DT_N_S_soc_S_uart_41013000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_41013000_P_compatible_LEN 1
#define DT_N_S_soc_S_uart_41013000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/uicr@1ff8000
 *
 * Node identifier: DT_N_S_soc_S_uicr_1ff8000
 *
 * Binding (compatible = nordic,nrf-uicr):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-uicr.yaml
 *
 * Description:
 *   Nordic UICR (User Information Configuration Registers)
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_uicr_1ff8000_PARENT DT_N_S_soc
#define DT_N_S_soc_S_uicr_1ff8000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_uicr_1ff8000_ORD 50

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_uicr_1ff8000_REQUIRES_ORDS \
	4, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_uicr_1ff8000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_uicr_1ff8000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_uicr DT_N_S_soc_S_uicr_1ff8000
#define DT_N_NODELABEL_uicr         DT_N_S_soc_S_uicr_1ff8000

/* Special property macros: */
#define DT_N_S_soc_S_uicr_1ff8000_REG_NUM 1
#define DT_N_S_soc_S_uicr_1ff8000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uicr_1ff8000_REG_IDX_0_VAL_ADDRESS 33521664 /* 0x1ff8000 */
#define DT_N_S_soc_S_uicr_1ff8000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_uicr_1ff8000_IRQ_NUM 0
#define DT_N_S_soc_S_uicr_1ff8000_COMPAT_MATCHES_nordic_nrf_uicr 1
#define DT_N_S_soc_S_uicr_1ff8000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_uicr_1ff8000_P_reg {33521664 /* 0x1ff8000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_uicr_1ff8000_P_reg_IDX_0 33521664
#define DT_N_S_soc_S_uicr_1ff8000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uicr_1ff8000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_uicr_1ff8000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_uicr_1ff8000_P_reg_EXISTS 1
#define DT_N_S_soc_S_uicr_1ff8000_P_status "okay"
#define DT_N_S_soc_S_uicr_1ff8000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_uicr_1ff8000_P_status_EXISTS 1
#define DT_N_S_soc_S_uicr_1ff8000_P_compatible {"nordic,nrf-uicr"}
#define DT_N_S_soc_S_uicr_1ff8000_P_compatible_IDX_0 "nordic,nrf-uicr"
#define DT_N_S_soc_S_uicr_1ff8000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uicr_1ff8000_P_compatible_LEN 1
#define DT_N_S_soc_S_uicr_1ff8000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/vmc@41081000
 *
 * Node identifier: DT_N_S_soc_S_vmc_41081000
 *
 * Binding (compatible = nordic,nrf-vmc):
 *   $ZEPHYR_BASE\dts\bindings\power\nordic,nrf-vmc.yaml
 *
 * Description:
 *   Nordic VMC (Volatile Memory Controller)
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_vmc_41081000_PARENT DT_N_S_soc
#define DT_N_S_soc_S_vmc_41081000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_vmc_41081000_ORD 51

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_vmc_41081000_REQUIRES_ORDS \
	4, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_vmc_41081000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_vmc_41081000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_vmc DT_N_S_soc_S_vmc_41081000
#define DT_N_NODELABEL_vmc         DT_N_S_soc_S_vmc_41081000

/* Special property macros: */
#define DT_N_S_soc_S_vmc_41081000_REG_NUM 1
#define DT_N_S_soc_S_vmc_41081000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_vmc_41081000_REG_IDX_0_VAL_ADDRESS 1091047424 /* 0x41081000 */
#define DT_N_S_soc_S_vmc_41081000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_vmc_41081000_IRQ_NUM 0
#define DT_N_S_soc_S_vmc_41081000_COMPAT_MATCHES_nordic_nrf_vmc 1
#define DT_N_S_soc_S_vmc_41081000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_vmc_41081000_P_reg {1091047424 /* 0x41081000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_vmc_41081000_P_reg_IDX_0 1091047424
#define DT_N_S_soc_S_vmc_41081000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_vmc_41081000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_vmc_41081000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_vmc_41081000_P_reg_EXISTS 1
#define DT_N_S_soc_S_vmc_41081000_P_status "okay"
#define DT_N_S_soc_S_vmc_41081000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_vmc_41081000_P_status_EXISTS 1
#define DT_N_S_soc_S_vmc_41081000_P_compatible {"nordic,nrf-vmc"}
#define DT_N_S_soc_S_vmc_41081000_P_compatible_IDX_0 "nordic,nrf-vmc"
#define DT_N_S_soc_S_vmc_41081000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_vmc_41081000_P_compatible_LEN 1
#define DT_N_S_soc_S_vmc_41081000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/watchdog@4100b000
 *
 * Node identifier: DT_N_S_soc_S_watchdog_4100b000
 *
 * Binding (compatible = nordic,nrf-watchdog):
 *   $ZEPHYR_BASE\dts\bindings\watchdog\nordic,nrf-watchdog.yaml
 *
 * Description:
 *   Nordic Semiconductor nRF watchdog
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_watchdog_4100b000_PARENT DT_N_S_soc
#define DT_N_S_soc_S_watchdog_4100b000_FOREACH_CHILD(fn) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_watchdog_4100b000_ORD 52

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_watchdog_4100b000_REQUIRES_ORDS \
	4, /* /soc */ \
	28, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_watchdog_4100b000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_watchdog_4100b000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_watchdog DT_N_S_soc_S_watchdog_4100b000
#define DT_N_NODELABEL_wdt              DT_N_S_soc_S_watchdog_4100b000
#define DT_N_NODELABEL_wdt0             DT_N_S_soc_S_watchdog_4100b000

/* Special property macros: */
#define DT_N_S_soc_S_watchdog_4100b000_REG_NUM 1
#define DT_N_S_soc_S_watchdog_4100b000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_4100b000_REG_IDX_0_VAL_ADDRESS 1090564096 /* 0x4100b000 */
#define DT_N_S_soc_S_watchdog_4100b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_watchdog_4100b000_IRQ_NUM 1
#define DT_N_S_soc_S_watchdog_4100b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_4100b000_IRQ_IDX_0_VAL_irq 11
#define DT_N_S_soc_S_watchdog_4100b000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_watchdog_4100b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_4100b000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_watchdog_4100b000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_watchdog_4100b000_COMPAT_MATCHES_nordic_nrf_watchdog 1
#define DT_N_S_soc_S_watchdog_4100b000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_watchdog_4100b000_P_reg {1090564096 /* 0x4100b000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_watchdog_4100b000_P_reg_IDX_0 1090564096
#define DT_N_S_soc_S_watchdog_4100b000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_4100b000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_watchdog_4100b000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_watchdog_4100b000_P_reg_EXISTS 1
#define DT_N_S_soc_S_watchdog_4100b000_P_label "WDT"
#define DT_N_S_soc_S_watchdog_4100b000_P_label_EXISTS 1
#define DT_N_S_soc_S_watchdog_4100b000_P_interrupts {11 /* 0xb */, 1 /* 0x1 */}
#define DT_N_S_soc_S_watchdog_4100b000_P_interrupts_IDX_0 11
#define DT_N_S_soc_S_watchdog_4100b000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_4100b000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_watchdog_4100b000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_watchdog_4100b000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_watchdog_4100b000_P_status "okay"
#define DT_N_S_soc_S_watchdog_4100b000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_watchdog_4100b000_P_status_EXISTS 1
#define DT_N_S_soc_S_watchdog_4100b000_P_compatible {"nordic,nrf-watchdog"}
#define DT_N_S_soc_S_watchdog_4100b000_P_compatible_IDX_0 "nordic,nrf-watchdog"
#define DT_N_S_soc_S_watchdog_4100b000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_4100b000_P_compatible_LEN 1
#define DT_N_S_soc_S_watchdog_4100b000_P_compatible_EXISTS 1

/*
 * Chosen nodes
 */
#define DT_CHOSEN_zephyr_entropy                 DT_N_S_soc_S_random_41009000
#define DT_CHOSEN_zephyr_entropy_EXISTS          1
#define DT_CHOSEN_zephyr_flash_controller        DT_N_S_flash_controller_41080000
#define DT_CHOSEN_zephyr_flash_controller_EXISTS 1
#define DT_CHOSEN_zephyr_console                 DT_N_S_soc_S_uart_41013000
#define DT_CHOSEN_zephyr_console_EXISTS          1
#define DT_CHOSEN_zephyr_shell_uart              DT_N_S_soc_S_uart_41013000
#define DT_CHOSEN_zephyr_shell_uart_EXISTS       1
#define DT_CHOSEN_zephyr_uart_mcumgr             DT_N_S_soc_S_uart_41013000
#define DT_CHOSEN_zephyr_uart_mcumgr_EXISTS      1
#define DT_CHOSEN_zephyr_bt_mon_uart             DT_N_S_soc_S_uart_41013000
#define DT_CHOSEN_zephyr_bt_mon_uart_EXISTS      1
#define DT_CHOSEN_zephyr_bt_c2h_uart             DT_N_S_soc_S_uart_41013000
#define DT_CHOSEN_zephyr_bt_c2h_uart_EXISTS      1
#define DT_CHOSEN_zephyr_sram                    DT_N_S_soc_S_memory_21000000
#define DT_CHOSEN_zephyr_sram_EXISTS             1
#define DT_CHOSEN_zephyr_flash                   DT_N_S_flash_controller_41080000_S_flash_1000000
#define DT_CHOSEN_zephyr_flash_EXISTS            1
#define DT_CHOSEN_zephyr_code_partition          DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_c000
#define DT_CHOSEN_zephyr_code_partition_EXISTS   1
#define DT_CHOSEN_zephyr_ipc_shm                 DT_N_S_reserved_memory_S_memory_20070000
#define DT_CHOSEN_zephyr_ipc_shm_EXISTS          1
#define DT_COMPAT_fixed_partitions_LABEL_mcuboot DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_0
#define DT_COMPAT_fixed_partitions_LABEL_mcuboot_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_image_0 DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_c000
#define DT_COMPAT_fixed_partitions_LABEL_image_0_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_image_1 DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_1e000
#define DT_COMPAT_fixed_partitions_LABEL_image_1_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_image_scratch DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_30000
#define DT_COMPAT_fixed_partitions_LABEL_image_scratch_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_storage DT_N_S_flash_controller_41080000_S_flash_1000000_S_partitions_S_partition_3a000
#define DT_COMPAT_fixed_partitions_LABEL_storage_EXISTS 1

/*
 * Macros for compatibles with status "okay" nodes
 */
#define DT_COMPAT_HAS_OKAY_nordic_nrf5340_dk_nrf5340_cpunet 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf5340_cpunet_qkaa 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf5340_cpunet 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf53 1
#define DT_COMPAT_HAS_OKAY_simple_bus 1
#define DT_COMPAT_HAS_OKAY_arm_v8m_nvic 1
#define DT_COMPAT_HAS_OKAY_mmio_sram 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_clock 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_dppic 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_egu 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_ficr 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_gpio 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_gpiote 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_ipc 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_power 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_rng 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_rtc 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_temp 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_timer 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_uarte 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_uicr 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_vmc 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_watchdog 1
#define DT_COMPAT_HAS_OKAY_arm_cortex_m33 1
#define DT_COMPAT_HAS_OKAY_arm_armv8m_mpu 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf53_flash_controller 1
#define DT_COMPAT_HAS_OKAY_soc_nv_flash 1
#define DT_COMPAT_HAS_OKAY_fixed_partitions 1
#define DT_COMPAT_HAS_OKAY_gpio_leds 1
#define DT_COMPAT_HAS_OKAY_gpio_keys 1

/*
 * Macros for status "okay" instances of each compatible
 */
#define DT_N_INST_nordic_nrf5340_dk_nrf5340_cpunet_NUM_OKAY 1
#define DT_N_INST_nordic_nrf5340_cpunet_qkaa_NUM_OKAY 1
#define DT_N_INST_nordic_nrf5340_cpunet_NUM_OKAY 1
#define DT_N_INST_nordic_nrf53_NUM_OKAY 1
#define DT_N_INST_simple_bus_NUM_OKAY 1
#define DT_N_INST_arm_v8m_nvic_NUM_OKAY 1
#define DT_N_INST_mmio_sram_NUM_OKAY 2
#define DT_N_INST_nordic_nrf_clock_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_dppic_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_egu_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_ficr_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_gpio_NUM_OKAY 2
#define DT_N_INST_nordic_nrf_gpiote_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_ipc_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_power_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_rng_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_rtc_NUM_OKAY 2
#define DT_N_INST_nordic_nrf_temp_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_timer_NUM_OKAY 3
#define DT_N_INST_nordic_nrf_uarte_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_uicr_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_vmc_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_watchdog_NUM_OKAY 1
#define DT_N_INST_arm_cortex_m33_NUM_OKAY 1
#define DT_N_INST_arm_armv8m_mpu_NUM_OKAY 1
#define DT_N_INST_nordic_nrf53_flash_controller_NUM_OKAY 1
#define DT_N_INST_soc_nv_flash_NUM_OKAY 1
#define DT_N_INST_fixed_partitions_NUM_OKAY 1
#define DT_N_INST_gpio_leds_NUM_OKAY 1
#define DT_N_INST_gpio_keys_NUM_OKAY 1
#define DT_FOREACH_OKAY_INST_nordic_nrf5340_dk_nrf5340_cpunet(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf5340_cpunet_qkaa(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf5340_cpunet(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf53(fn) fn(0)
#define DT_FOREACH_OKAY_INST_simple_bus(fn) fn(0)
#define DT_FOREACH_OKAY_INST_arm_v8m_nvic(fn) fn(0)
#define DT_FOREACH_OKAY_INST_mmio_sram(fn) fn(0) fn(1)
#define DT_FOREACH_OKAY_INST_nordic_nrf_clock(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_dppic(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_egu(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_ficr(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_gpio(fn) fn(0) fn(1)
#define DT_FOREACH_OKAY_INST_nordic_nrf_gpiote(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_ipc(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_power(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_rng(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_rtc(fn) fn(0) fn(1)
#define DT_FOREACH_OKAY_INST_nordic_nrf_temp(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_timer(fn) fn(0) fn(1) fn(2)
#define DT_FOREACH_OKAY_INST_nordic_nrf_uarte(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_uicr(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_vmc(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_watchdog(fn) fn(0)
#define DT_FOREACH_OKAY_INST_arm_cortex_m33(fn) fn(0)
#define DT_FOREACH_OKAY_INST_arm_armv8m_mpu(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf53_flash_controller(fn) fn(0)
#define DT_FOREACH_OKAY_INST_soc_nv_flash(fn) fn(0)
#define DT_FOREACH_OKAY_INST_fixed_partitions(fn) fn(0)
#define DT_FOREACH_OKAY_INST_gpio_leds(fn) fn(0)
#define DT_FOREACH_OKAY_INST_gpio_keys(fn) fn(0)

/*
 * Bus information for status "okay" nodes of each compatible
 */
