
zephyr.elf:     file format elf32-littlearm


Disassembly of section rom_start:

00000000 <_vector_table>:
	return cb(str, strl, ctx);
}

int cbvprintf_package(void *packaged, size_t len, uint32_t flags,
		      const char *fmt, va_list ap)
{
   0:	40 45 00 20 d9 20 00 00 85 66 00 00 ad 20 00 00     @E. . ...f... ..
	bool rws_pos_en = !!(flags & CBPRINTF_PACKAGE_ADD_RW_STR_POS);
	/* Get number of first read only strings present in the string.
	 * There is always at least 1 (fmt) but flags can indicate more, e.g
	 * fixed prefix appended to all strings.
	 */
	int fros_cnt = 1 + Z_CBPRINTF_PACKAGE_FIRST_RO_STR_CNT_GET(flags);
  10:	ad 20 00 00 ad 20 00 00 ad 20 00 00 00 00 00 00     . ... ... ......
	...

	/*
	 * Otherwise we must ensure we can store at least
	 * the pointer to the format string itself.
	 */
	if (buf0 != NULL && BUF_OFFSET + sizeof(char *) > len) {
  2c:	0d 1c 00 00 ad 20 00 00 00 00 00 00 ad 20 00 00     ..... ....... ..
		buf += len % CBPRINTF_PACKAGE_ALIGNMENT;
  3c:	ad 20 00 00                                         . ..

00000040 <_irq_vector_table>:
		len = CBPRINTF_PACKAGE_ALIGNMENT - (len % CBPRINTF_PACKAGE_ALIGNMENT);
  40:	8d 1c 00 00 8d 1c 00 00 8d 1c 00 00 8d 1c 00 00     ................
	int arg_idx	      = -1; /* Argument index. Preincremented thus starting from -1.*/
  50:	8d 1c 00 00 8d 1c 00 00 8d 1c 00 00 8d 1c 00 00     ................

		/* copy va_list data over to our buffer */
		if (is_str_arg) {
			s = va_arg(ap, char *);
process_string:
			if (buf0 != NULL) {
  60:	8d 1c 00 00 8d 1c 00 00 8d 1c 00 00 8d 1c 00 00     ................
#else
	#define RO_START 0
	#define RO_END 0
#endif

	return (((const char *)addr >= (const char *)RO_START) &&
  70:	8d 1c 00 00 8d 1c 00 00 8d 1c 00 00 8d 1c 00 00     ................
			bool do_ro = !!(flags & CBPRINTF_PACKAGE_ADD_RO_STR_POS);

			if (is_ro && !do_ro) {
				/* nothing to do */
			} else {
				uint32_t s_ptr_idx = BUF_OFFSET / sizeof(int);
  80:	8d 1c 00 00 8d 1c 00 00 8d 1c 00 00 8d 1c 00 00     ................
				if (do_ro && s_ptr_idx > STR_POS_MASK) {
					__ASSERT(false, "String with too many arguments");
					return -EINVAL;
				}

				if (s_idx >= ARRAY_SIZE(str_ptr_pos)) {
  90:	8d 1c 00 00 8d 1c 00 00 8d 1c 00 00 8d 1c 00 00     ................
				if (buf0 != NULL) {
					/*
					 * Remember string pointer location.
					 * We will append non-ro strings later.
					 */
					str_ptr_pos[s_idx] = s_ptr_idx;
  a0:	8d 1c 00 00 8d 1c 00 00 8d 1c 00 00 8d 1c 00 00     ................
					if (is_ro) {
						/* flag read-only string. */
						str_ptr_pos[s_idx] |= STR_POS_RO_FLAG;
						s_ro_cnt++;
					} else {
						s_rw_cnt++;
  b0:	8d 1c 00 00 8d 1c 00 00 8d 1c 00 00 8d 1c 00 00     ................
			switch (*fmt) {
  c0:	8d 1c 00 00 8d 1c 00 00 8d 1c 00 00 8d 1c 00 00     ................
  d0:	8d 1c 00 00 8d 1c 00 00 8d 1c 00 00 8d 1c 00 00     ................
  e0:	8d 1c 00 00 8d 1c 00 00 8d 1c 00 00 8d 1c 00 00     ................
  f0:	8d 1c 00 00 8d 1c 00 00 8d 1c 00 00 8d 1c 00 00     ................

Disassembly of section text:

00000100 <__aeabi_uldivmod>:
     100:	b953      	cbnz	r3, 118 <__aeabi_uldivmod+0x18>
     102:	b94a      	cbnz	r2, 118 <__aeabi_uldivmod+0x18>
     104:	2900      	cmp	r1, #0
     106:	bf08      	it	eq
     108:	2800      	cmpeq	r0, #0
     10a:	bf1c      	itt	ne
     10c:	f04f 31ff 	movne.w	r1, #4294967295
     110:	f04f 30ff 	movne.w	r0, #4294967295
     114:	f000 b80c 	b.w	130 <__aeabi_idiv0>
     118:	f1ad 0c08 	sub.w	ip, sp, #8
     11c:	e96d ce04 	strd	ip, lr, [sp, #-16]!
				align = VA_STACK_ALIGN(void *);
     120:	f000 f808 	bl	134 <__udivmoddi4>
			switch (*fmt) {
     124:	f8dd e004 	ldr.w	lr, [sp, #4]
     128:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
     12c:	b004      	add	sp, #16
     12e:	4770      	bx	lr

00000130 <__aeabi_idiv0>:
     130:	4770      	bx	lr
     132:	bf00      	nop

00000134 <__udivmoddi4>:
     134:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
     138:	4686      	mov	lr, r0
     13a:	468c      	mov	ip, r1
     13c:	4608      	mov	r0, r1
     13e:	9e08      	ldr	r6, [sp, #32]
     140:	4615      	mov	r5, r2
     142:	4674      	mov	r4, lr
		buf = (void *) ROUND_UP(buf, align);
     144:	4619      	mov	r1, r3
     146:	2b00      	cmp	r3, #0
     148:	f040 80c2 	bne.w	2d0 <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0xd0>
     14c:	4285      	cmp	r5, r0
     14e:	fab2 f282 	clz	r2, r2
		if (buf0 != NULL && BUF_OFFSET + size > len) {
     152:	d945      	bls.n	1e0 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x73>
     154:	b14a      	cbz	r2, 16a <CONFIG_IDLE_STACK_SIZE+0x2a>
     156:	f1c2 0320 	rsb	r3, r2, #32
     15a:	fa00 fc02 	lsl.w	ip, r0, r2
     15e:	fa2e f303 	lsr.w	r3, lr, r3
		if (is_str_arg) {
     162:	4095      	lsls	r5, r2
				s_idx++;
			}
			buf += sizeof(char *);

			is_str_arg = false;
		} else if (size == sizeof(int)) {
     164:	ea43 0c0c 	orr.w	ip, r3, ip
			int v = va_arg(ap, int);
     168:	4094      	lsls	r4, r2
     16a:	ea4f 4e15 	mov.w	lr, r5, lsr #16

			if (buf0 != NULL) {
				*(int *)buf = v;
			}
			buf += sizeof(int);
     16e:	b2a8      	uxth	r0, r5
     170:	fbbc f8fe 	udiv	r8, ip, lr
				arg_idx--;
     174:	0c23      	lsrs	r3, r4, #16
     176:	fb0e cc18 	mls	ip, lr, r8, ip
				parsing = false;
     17a:	fb08 f900 	mul.w	r9, r8, r0
				continue;
     17e:	ea43 430c 	orr.w	r3, r3, ip, lsl #16
				if (fmt[-1] == 'l') {
     182:	4599      	cmp	r9, r3
     184:	d928      	bls.n	1d8 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x6b>
     186:	18eb      	adds	r3, r5, r3
					if (fmt[-2] == 'l') {
     188:	f108 37ff 	add.w	r7, r8, #4294967295
     18c:	d204      	bcs.n	198 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x2b>
     18e:	4599      	cmp	r9, r3
				parsing = false;
     190:	d902      	bls.n	198 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x2b>
					if (fmt[-2] == 'l') {
     192:	f1a8 0702 	sub.w	r7, r8, #2
						align = VA_STACK_ALIGN(long long);
     196:	442b      	add	r3, r5
				size = sizeof(void *);
     198:	eba3 0309 	sub.w	r3, r3, r9
					v.ld = va_arg(ap, long double);
     19c:	b2a4      	uxth	r4, r4
     19e:	fbb3 fcfe 	udiv	ip, r3, lr
     1a2:	fb0e 331c 	mls	r3, lr, ip, r3
     1a6:	fb0c f000 	mul.w	r0, ip, r0
				buf = (void *) ROUND_UP(buf, align);
     1aa:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
				if (buf0 != NULL) {
     1ae:	42a0      	cmp	r0, r4
					if (BUF_OFFSET + size > len) {
     1b0:	d914      	bls.n	1dc <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x6f>
     1b2:	192c      	adds	r4, r5, r4
     1b4:	f10c 33ff 	add.w	r3, ip, #4294967295
     1b8:	d204      	bcs.n	1c4 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x57>
						*(long double *)buf = v.ld;
     1ba:	42a0      	cmp	r0, r4
     1bc:	d902      	bls.n	1c4 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x57>
				buf += size;
     1be:	f1ac 0302 	sub.w	r3, ip, #2
				parsing = false;
     1c2:	442c      	add	r4, r5
			switch (*fmt) {
     1c4:	1a24      	subs	r4, r4, r0
     1c6:	ea43 4007 	orr.w	r0, r3, r7, lsl #16
			if (*++fmt == '\0') {
     1ca:	b11e      	cbz	r6, 1d4 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x67>
     1cc:	40d4      	lsrs	r4, r2
     1ce:	2300      	movs	r3, #0
     1d0:	6034      	str	r4, [r6, #0]
			if (!parsing) {
     1d2:	6073      	str	r3, [r6, #4]
     1d4:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
     1d8:	4647      	mov	r7, r8
				if (*fmt == '%') {
     1da:	e7dd      	b.n	198 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x2b>
     1dc:	4663      	mov	r3, ip
					arg_idx++;
     1de:	e7f1      	b.n	1c4 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x57>
     1e0:	bb92      	cbnz	r2, 248 <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0x48>
     1e2:	1b43      	subs	r3, r0, r5
					parsing = true;
     1e4:	2101      	movs	r1, #1
     1e6:	ea4f 4e15 	mov.w	lr, r5, lsr #16
				align = VA_STACK_ALIGN(size_t);
     1ea:	b2af      	uxth	r7, r5
     1ec:	fbb3 fcfe 	udiv	ip, r3, lr
			switch (*fmt) {
     1f0:	0c20      	lsrs	r0, r4, #16
     1f2:	fb0e 331c 	mls	r3, lr, ip, r3
				parsing = false;
     1f6:	fb0c f807 	mul.w	r8, ip, r7

			if (buf0 != NULL) {
				*(long *)buf = v;
			}
			buf += sizeof(long);
		} else if (size == sizeof(long long)) {
     1fa:	ea40 4303 	orr.w	r3, r0, r3, lsl #16
					return -EINVAL;
     1fe:	4598      	cmp	r8, r3
     200:	d962      	bls.n	2c8 <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0xc8>
			long long v = va_arg(ap, long long);
     202:	18eb      	adds	r3, r5, r3
     204:	f10c 30ff 	add.w	r0, ip, #4294967295
     208:	d204      	bcs.n	214 <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0x14>
     20a:	4598      	cmp	r8, r3
     20c:	d902      	bls.n	214 <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0x14>

			if (buf0 != NULL) {
				if (Z_CBPRINTF_VA_STACK_LL_DBL_MEMCPY) {
					memcpy(buf, &v, sizeof(long long));
				} else {
					*(long long *)buf = v;
     20e:	f1ac 0002 	sub.w	r0, ip, #2
				}
			}
			buf += sizeof(long long);
     212:	442b      	add	r3, r5
     214:	eba3 0308 	sub.w	r3, r3, r8
		if (is_str_arg) {
     218:	b2a4      	uxth	r4, r4
		} else if (size == sizeof(int)) {
     21a:	fbb3 fcfe 	udiv	ip, r3, lr
			int v = va_arg(ap, int);
     21e:	fb0e 331c 	mls	r3, lr, ip, r3
			if (buf0 != NULL) {
     222:	fb0c f707 	mul.w	r7, ip, r7
		} else if (size == sizeof(long long)) {
     226:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
			long long v = va_arg(ap, long long);
     22a:	42a7      	cmp	r7, r4
     22c:	d94e      	bls.n	2cc <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0xcc>
     22e:	192c      	adds	r4, r5, r4
     230:	f10c 33ff 	add.w	r3, ip, #4294967295
			if (buf0 != NULL) {
     234:	d204      	bcs.n	240 <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0x40>
			bool is_ro = (fros_cnt-- > 0) ? true : ptr_in_rodata(s);
     236:	42a7      	cmp	r7, r4
     238:	d902      	bls.n	240 <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0x40>
     23a:	f1ac 0302 	sub.w	r3, ip, #2
			s = va_arg(ap, char *);
     23e:	442c      	add	r4, r5
     240:	1be4      	subs	r4, r4, r7
     242:	ea43 4000 	orr.w	r0, r3, r0, lsl #16
			if (is_ro && !do_ro) {
     246:	e7c0      	b.n	1ca <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x5d>
     248:	f1c2 0320 	rsb	r3, r2, #32
				uint32_t s_ptr_idx = BUF_OFFSET / sizeof(int);
     24c:	fa20 f103 	lsr.w	r1, r0, r3
     250:	4095      	lsls	r5, r2
			bool is_ro = (fros_cnt-- > 0) ? true : ptr_in_rodata(s);
     252:	4090      	lsls	r0, r2
     254:	fa2e f303 	lsr.w	r3, lr, r3
				if (do_ro && s_ptr_idx > STR_POS_MASK) {
     258:	4303      	orrs	r3, r0
     25a:	ea4f 4e15 	mov.w	lr, r5, lsr #16
				if (s_idx >= ARRAY_SIZE(str_ptr_pos)) {
     25e:	b2af      	uxth	r7, r5
				if (buf0 != NULL) {
     260:	fbb1 fcfe 	udiv	ip, r1, lr
					str_ptr_pos[s_idx] = s_ptr_idx;
     264:	fb0e 101c 	mls	r0, lr, ip, r1
     268:	0c19      	lsrs	r1, r3, #16
     26a:	fb0c f807 	mul.w	r8, ip, r7
     26e:	ea41 4100 	orr.w	r1, r1, r0, lsl #16
					str_ptr_arg[s_idx] = arg_idx;
     272:	4588      	cmp	r8, r1
     274:	fa04 f402 	lsl.w	r4, r4, r2
					if (is_ro) {
     278:	d922      	bls.n	2c0 <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0xc0>
     27a:	1869      	adds	r1, r5, r1
     27c:	f10c 30ff 	add.w	r0, ip, #4294967295
						str_ptr_pos[s_idx] |= STR_POS_RO_FLAG;
     280:	d204      	bcs.n	28c <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0x8c>
     282:	4588      	cmp	r8, r1
     284:	d902      	bls.n	28c <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0x8c>
						s_ro_cnt++;
     286:	f1ac 0002 	sub.w	r0, ip, #2
				s_idx++;
     28a:	4429      	add	r1, r5
					if (BUF_OFFSET + size > len) {
     28c:	eba1 0108 	sub.w	r1, r1, r8
			buf += sizeof(char *);
     290:	b29b      	uxth	r3, r3
					if (BUF_OFFSET + size > len) {
     292:	fbb1 fcfe 	udiv	ip, r1, lr
			switch (*fmt) {
     296:	fb0e 111c 	mls	r1, lr, ip, r1
			bool is_ro = (fros_cnt-- > 0) ? true : ptr_in_rodata(s);
     29a:	fb0c f707 	mul.w	r7, ip, r7
     29e:	ea43 4301 	orr.w	r3, r3, r1, lsl #16
				} else if (is_ro) {
     2a2:	429f      	cmp	r7, r3
     2a4:	d90e      	bls.n	2c4 <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0xc4>
					len += 1;
     2a6:	18eb      	adds	r3, r5, r3
     2a8:	f10c 31ff 	add.w	r1, ip, #4294967295
					len += 2;
     2ac:	d204      	bcs.n	2b8 <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0xb8>
				} else if (rws_pos_en) {
     2ae:	429f      	cmp	r7, r3
     2b0:	d902      	bls.n	2b8 <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0xb8>
					len += strlen(s) + 1 + 1;
     2b2:	f1ac 0102 	sub.w	r1, ip, #2
     2b6:	442b      	add	r3, r5
     2b8:	1bdb      	subs	r3, r3, r7
     2ba:	ea41 4100 	orr.w	r1, r1, r0, lsl #16
     2be:	e792      	b.n	1e6 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x79>
     2c0:	4660      	mov	r0, ip
     2c2:	e7e3      	b.n	28c <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0x8c>
	 * We remember the size of the argument list as a multiple of
	 * sizeof(int) and limit it to a 8-bit field. That means 1020 bytes
	 * worth of va_list, or about 127 arguments on a 64-bit system
	 * (twice that on 32-bit systems). That ought to be good enough.
	 */
	if (BUF_OFFSET / sizeof(int) > 255) {
     2c4:	4661      	mov	r1, ip
     2c6:	e7f7      	b.n	2b8 <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0xb8>
     2c8:	4660      	mov	r0, ip
     2ca:	e7a3      	b.n	214 <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0x14>

	/*
	 * If all we wanted was to count required buffer size
	 * then we have it now.
	 */
	if (buf0 == NULL) {
     2cc:	4663      	mov	r3, ip
		return BUF_OFFSET + len - CBPRINTF_PACKAGE_ALIGNMENT;
     2ce:	e7b7      	b.n	240 <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0x40>
     2d0:	4283      	cmp	r3, r0
     2d2:	d906      	bls.n	2e2 <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0xe2>
     2d4:	b916      	cbnz	r6, 2dc <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0xdc>
     2d6:	2100      	movs	r1, #0
     2d8:	4608      	mov	r0, r1
     2da:	e77b      	b.n	1d4 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x67>
     2dc:	e9c6 e000 	strd	lr, r0, [r6]
	*(char **)buf0 = NULL;

	/* Record end of argument list. */
	pkg_hdr->desc.len = BUF_OFFSET / sizeof(int);

	if (rws_pos_en) {
     2e0:	e7f9      	b.n	2d6 <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0xd6>
	*(char **)buf0 = NULL;
     2e2:	fab3 f783 	clz	r7, r3
	pkg_hdr->desc.len = BUF_OFFSET / sizeof(int);
     2e6:	b98f      	cbnz	r7, 30c <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0xc>
		/* Strings are appended, update location counter. */
		pkg_hdr->desc.str_cnt = 0;
		pkg_hdr->desc.rw_str_cnt = s_rw_cnt;
     2e8:	4283      	cmp	r3, r0
     2ea:	d301      	bcc.n	2f0 <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0xf0>
	if (rws_pos_en) {
     2ec:	4572      	cmp	r2, lr
		pkg_hdr->desc.rw_str_cnt = s_rw_cnt;
     2ee:	d808      	bhi.n	302 <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x2>
		/* Strings are appended, update append counter. */
		pkg_hdr->desc.str_cnt = s_rw_cnt;
		pkg_hdr->desc.rw_str_cnt = 0;
	}

	pkg_hdr->desc.ro_str_cnt = s_ro_cnt;
     2f0:	ebbe 0402 	subs.w	r4, lr, r2
#ifdef CONFIG_CBPRINTF_PACKAGE_HEADER_STORE_CREATION_FLAGS
	pkg_hdr->desc.pkg_flags = flags;
#endif

	/* Store strings pointer locations of read only strings. */
	if (s_ro_cnt) {
     2f4:	eb60 0303 	sbc.w	r3, r0, r3
     2f8:	2001      	movs	r0, #1
     2fa:	469c      	mov	ip, r3
		for (i = 0; i < s_idx; i++) {
     2fc:	b91e      	cbnz	r6, 306 <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x6>
			}

			uint8_t pos = str_ptr_pos[i] & STR_POS_MASK;

			/* make sure it fits */
			if (BUF_OFFSET + 1 > len) {
     2fe:	2100      	movs	r1, #0
     300:	e768      	b.n	1d4 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x67>
		for (i = 0; i < s_idx; i++) {
     302:	4638      	mov	r0, r7
     304:	e7fa      	b.n	2fc <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0xfc>
			/* find the string length including terminating '\0' */
			size = strlen(s) + 1;
		}

		/* make sure it fits */
		if (BUF_OFFSET + 1 + size > len) {
     306:	e9c6 4c00 	strd	r4, ip, [r6]
     30a:	e7f8      	b.n	2fe <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0xfe>
     30c:	f1c7 0c20 	rsb	ip, r7, #32
			*buf++ = str_ptr_arg[i];
     310:	40bb      	lsls	r3, r7
		if (BUF_OFFSET + 1 + size > len) {
     312:	fa22 f40c 	lsr.w	r4, r2, ip
			*buf++ = str_ptr_arg[i];
     316:	431c      	orrs	r4, r3
	for (i = 0; i < s_idx; i++) {
     318:	fa2e f10c 	lsr.w	r1, lr, ip
	/*
	 * TODO: remove pointers for appended strings since they're useless.
	 * TODO: explore leveraging same mechanism to remove alignment padding
	 */

	return BUF_OFFSET;
     31c:	fa20 f30c 	lsr.w	r3, r0, ip
		pkg_hdr->desc.str_cnt = s_rw_cnt;
     320:	40b8      	lsls	r0, r7
		pkg_hdr->desc.rw_str_cnt = 0;
     322:	4301      	orrs	r1, r0
			if (!(str_ptr_pos[i] & STR_POS_RO_FLAG)) {
     324:	ea4f 4914 	mov.w	r9, r4, lsr #16
     328:	fa0e f507 	lsl.w	r5, lr, r7
			if (BUF_OFFSET + 1 > len) {
     32c:	fbb3 f8f9 	udiv	r8, r3, r9
     330:	fa1f fe84 	uxth.w	lr, r4
			uint8_t pos = str_ptr_pos[i] & STR_POS_MASK;
     334:	fb09 3018 	mls	r0, r9, r8, r3
			if (BUF_OFFSET + 1 > len) {
     338:	0c0b      	lsrs	r3, r1, #16
			*buf++ = pos;
     33a:	fb08 fa0e 	mul.w	sl, r8, lr
		for (i = 0; i < s_idx; i++) {
     33e:	ea43 4300 	orr.w	r3, r3, r0, lsl #16
		if (s_ro_cnt && str_ptr_pos[i] & STR_POS_RO_FLAG) {
     342:	459a      	cmp	sl, r3
     344:	fa02 f207 	lsl.w	r2, r2, r7
     348:	d940      	bls.n	3cc <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0xcc>
     34a:	18e3      	adds	r3, r4, r3
     34c:	f108 30ff 	add.w	r0, r8, #4294967295
		if (rws_pos_en) {
     350:	d204      	bcs.n	35c <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x5c>
     352:	459a      	cmp	sl, r3
			*buf++ = str_ptr_arg[i];
     354:	d902      	bls.n	35c <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x5c>
     356:	f1a8 0002 	sub.w	r0, r8, #2
     35a:	4423      	add	r3, r4
			size = 0;
     35c:	eba3 030a 	sub.w	r3, r3, sl
		if (BUF_OFFSET + 1 + size > len) {
     360:	b289      	uxth	r1, r1
     362:	fbb3 f8f9 	udiv	r8, r3, r9
     366:	fb09 3318 	mls	r3, r9, r8, r3
		*buf++ = str_ptr_pos[i];
     36a:	fb08 fe0e 	mul.w	lr, r8, lr
     36e:	ea41 4103 	orr.w	r1, r1, r3, lsl #16
		memcpy(buf, s, size);
     372:	458e      	cmp	lr, r1
     374:	d92c      	bls.n	3d0 <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0xd0>
     376:	1861      	adds	r1, r4, r1
     378:	f108 33ff 	add.w	r3, r8, #4294967295
		buf += size;
     37c:	d204      	bcs.n	388 <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x88>
     37e:	458e      	cmp	lr, r1
	for (i = 0; i < s_idx; i++) {
     380:	d902      	bls.n	388 <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x88>
     382:	f1a8 0302 	sub.w	r3, r8, #2
     386:	4421      	add	r1, r4
     388:	ea43 4000 	orr.w	r0, r3, r0, lsl #16
			s = *(char **)(buf0 + str_ptr_pos[i] * sizeof(int));
     38c:	fba0 9802 	umull	r9, r8, r0, r2
     390:	eba1 010e 	sub.w	r1, r1, lr
			*(char **)(buf0 + str_ptr_pos[i] * sizeof(int)) = NULL;
     394:	4541      	cmp	r1, r8
     396:	46ce      	mov	lr, r9
     398:	4643      	mov	r3, r8
			size = strlen(s) + 1;
     39a:	d302      	bcc.n	3a2 <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0xa2>
     39c:	d106      	bne.n	3ac <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0xac>
     39e:	454d      	cmp	r5, r9
     3a0:	d204      	bcs.n	3ac <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0xac>
     3a2:	ebb9 0e02 	subs.w	lr, r9, r2
		return -EFAULT;
     3a6:	eb68 0304 	sbc.w	r3, r8, r4
     3aa:	3801      	subs	r0, #1
     3ac:	2e00      	cmp	r6, #0
     3ae:	d0a6      	beq.n	2fe <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0xfe>
     3b0:	ebb5 020e 	subs.w	r2, r5, lr
     3b4:	eb61 0103 	sbc.w	r1, r1, r3
     3b8:	fa01 fc0c 	lsl.w	ip, r1, ip
     3bc:	fa22 f307 	lsr.w	r3, r2, r7
     3c0:	ea4c 0303 	orr.w	r3, ip, r3
     3c4:	40f9      	lsrs	r1, r7
     3c6:	e9c6 3100 	strd	r3, r1, [r6]
     3ca:	e798      	b.n	2fe <CONFIG_PM_PARTITION_SIZE_MCUBOOT_PAD+0xfe>
     3cc:	4640      	mov	r0, r8
     3ce:	e7c5      	b.n	35c <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x5c>
     3d0:	4643      	mov	r3, r8
     3d2:	e7d9      	b.n	388 <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x88>

000003d4 <main>:
    return (bool)pin_active;
}
#endif

void main(void)
{
     3d4:	b57f      	push	{r0, r1, r2, r3, r4, r5, r6, lr}
}

NRF_STATIC_INLINE void nrf_wdt_reload_request_set(NRF_WDT_Type *        p_reg,
                                                  nrf_wdt_rr_register_t rr_register)
{
    p_reg->RR[rr_register] = NRF_WDT_RR_VALUE;
     3d6:	4b2b      	ldr	r3, [pc, #172]	; (484 <FIH_LABEL_FIH_CALL_END_224+0x78>)
     3d8:	4a2b      	ldr	r2, [pc, #172]	; (488 <FIH_LABEL_FIH_CALL_END_224+0x7c>)
     3da:	f8c3 2600 	str.w	r2, [r3, #1536]	; 0x600
    fih_int fih_rc = FIH_FAILURE;

    MCUBOOT_WATCHDOG_FEED();

#if !defined(MCUBOOT_DIRECT_XIP)
    BOOT_LOG_INF("Starting bootloader");
     3de:	482b      	ldr	r0, [pc, #172]	; (48c <FIH_LABEL_FIH_CALL_END_224+0x80>)
     3e0:	f8c3 2604 	str.w	r2, [r3, #1540]	; 0x604
     3e4:	2149      	movs	r1, #73	; 0x49
     3e6:	f8c3 2608 	str.w	r2, [r3, #1544]	; 0x608
     3ea:	f8c3 260c 	str.w	r2, [r3, #1548]	; 0x60c
     3ee:	f8c3 2610 	str.w	r2, [r3, #1552]	; 0x610
     3f2:	f8c3 2614 	str.w	r2, [r3, #1556]	; 0x614
     3f6:	f8c3 2618 	str.w	r2, [r3, #1560]	; 0x618
     3fa:	f8c3 261c 	str.w	r2, [r3, #1564]	; 0x61c
     3fe:	f006 f8b6 	bl	656e <z_log_minimal_printk>
#ifdef CONFIG_MCUBOOT_INDICATION_LED
    /* LED init */
    led_init();
#endif

    os_heap_init();
     402:	f005 fc5e 	bl	5cc2 <os_heap_init>

00000406 <FIH_LABEL_FIH_CALL_START_212>:
    rc = boot_console_init();
    int timeout_in_ms = CONFIG_BOOT_SERIAL_WAIT_FOR_DFU_TIMEOUT;
    uint32_t start = k_uptime_get_32();
#endif

    FIH_CALL(boot_go, fih_rc, &rsp);
     406:	a801      	add	r0, sp, #4
     408:	f000 fc78 	bl	cfc <boot_go>

0000040c <FIH_LABEL_FIH_CALL_END_224>:
        timeout_in_ms = 1;
    }
    boot_serial_check_start(&boot_funcs,timeout_in_ms);
#endif

    if (fih_not_eq(fih_rc, FIH_SUCCESS)) {
     40c:	4b20      	ldr	r3, [pc, #128]	; (490 <FIH_LABEL_FIH_CALL_END_224+0x84>)
     40e:	681b      	ldr	r3, [r3, #0]
     410:	4283      	cmp	r3, r0
     412:	d004      	beq.n	41e <FIH_LABEL_FIH_CALL_END_224+0x12>
        BOOT_LOG_ERR("Unable to find bootable image");
     414:	481f      	ldr	r0, [pc, #124]	; (494 <FIH_LABEL_FIH_CALL_END_224+0x88>)
     416:	2145      	movs	r1, #69	; 0x45
     418:	f006 f8a9 	bl	656e <z_log_minimal_printk>

        mcuboot_status_change(MCUBOOT_STATUS_NO_BOOTABLE_IMAGE_FOUND);

        FIH_PANIC;
     41c:	e7fe      	b.n	41c <FIH_LABEL_FIH_CALL_END_224+0x10>
    }

    BOOT_LOG_INF("Bootloader chainload address offset: 0x%x",
     41e:	9a03      	ldr	r2, [sp, #12]
     420:	481d      	ldr	r0, [pc, #116]	; (498 <FIH_LABEL_FIH_CALL_END_224+0x8c>)
     422:	2149      	movs	r1, #73	; 0x49
     424:	f006 f8a3 	bl	656e <z_log_minimal_printk>
                 rsp.br_image_off);

#if defined(MCUBOOT_DIRECT_XIP)
    BOOT_LOG_INF("Jumping to the image slot");
#else
    BOOT_LOG_INF("Jumping to the first image slot");
     428:	481c      	ldr	r0, [pc, #112]	; (49c <FIH_LABEL_FIH_CALL_END_224+0x90>)
     42a:	2149      	movs	r1, #73	; 0x49
     42c:	f006 f89f 	bl	656e <z_log_minimal_printk>
/* There is only one instance of MCUBoot */
#define PROTECT_SIZE (PM_MCUBOOT_PRIMARY_ADDRESS - PM_MCUBOOT_ADDRESS)
#define PROTECT_ADDR PM_MCUBOOT_ADDRESS
#endif

    rc = fprotect_area(PROTECT_ADDR, PROTECT_SIZE);
     430:	f44f 4140 	mov.w	r1, #49152	; 0xc000
     434:	2000      	movs	r0, #0
     436:	f006 fb9c 	bl	6b72 <fprotect_area>

    if (rc != 0) {
     43a:	b120      	cbz	r0, 446 <FIH_LABEL_FIH_CALL_END_224+0x3a>
        BOOT_LOG_ERR("Protect mcuboot flash failed, cancel startup.");
     43c:	4818      	ldr	r0, [pc, #96]	; (4a0 <FIH_LABEL_FIH_CALL_END_224+0x94>)
     43e:	2145      	movs	r1, #69	; 0x45
     440:	f006 f895 	bl	656e <z_log_minimal_printk>
        while (1)
     444:	e7fe      	b.n	444 <FIH_LABEL_FIH_CALL_END_224+0x38>
    rc = flash_device_base(rsp->br_flash_dev_id, &flash_base);
     446:	4669      	mov	r1, sp
     448:	f89d 0008 	ldrb.w	r0, [sp, #8]
     44c:	f000 f82c 	bl	4a8 <flash_device_base>
    vt = (struct arm_vector_table *)(flash_base +
     450:	9b00      	ldr	r3, [sp, #0]
     452:	9c03      	ldr	r4, [sp, #12]
     454:	441c      	add	r4, r3
                                     rsp->br_hdr->ih_hdr_size);
     456:	9b01      	ldr	r3, [sp, #4]
     458:	891d      	ldrh	r5, [r3, #8]
    nrf_cleanup_peripheral();
     45a:	f000 ff39 	bl	12d0 <nrf_cleanup_peripheral>
                                     rsp->br_image_off +
     45e:	1966      	adds	r6, r4, r5
		:
		: "memory");
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	unsigned int tmp;

	__asm__ volatile(
     460:	f04f 0220 	mov.w	r2, #32
     464:	f3ef 8311 	mrs	r3, BASEPRI
     468:	f382 8812 	msr	BASEPRI_MAX, r2
     46c:	f3bf 8f6f 	isb	sy
  \details Assigns the given value to the Main Stack Pointer (MSP).
  \param [in]    topOfMainStack  Main Stack Pointer value to set
 */
__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
{
  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
     470:	5963      	ldr	r3, [r4, r5]
     472:	f383 8808 	msr	MSP, r3
    ((void (*)(void))vt->reset)();
     476:	6873      	ldr	r3, [r6, #4]
     478:	4798      	blx	r3

    do_boot(&rsp);

    mcuboot_status_change(MCUBOOT_STATUS_BOOT_FAILED);

    BOOT_LOG_ERR("Never should get here");
     47a:	480a      	ldr	r0, [pc, #40]	; (4a4 <FIH_LABEL_FIH_CALL_END_224+0x98>)
     47c:	2145      	movs	r1, #69	; 0x45
     47e:	f006 f876 	bl	656e <z_log_minimal_printk>
    while (1)
     482:	e7fe      	b.n	482 <FIH_LABEL_FIH_CALL_END_224+0x76>
     484:	40010000 	.word	0x40010000
     488:	6e524635 	.word	0x6e524635
     48c:	00007570 	.word	0x00007570
     490:	200001f0 	.word	0x200001f0
     494:	00007589 	.word	0x00007589
     498:	000075ac 	.word	0x000075ac
     49c:	000075db 	.word	0x000075db
     4a0:	00007600 	.word	0x00007600
     4a4:	00007633 	.word	0x00007633

000004a8 <flash_device_base>:
#endif

static const struct device *flash_dev = DEVICE_DT_GET(FLASH_DEVICE_NODE);

int flash_device_base(uint8_t fd_id, uintptr_t *ret)
{
     4a8:	b508      	push	{r3, lr}
    if (fd_id != FLASH_DEVICE_ID) {
     4aa:	4602      	mov	r2, r0
     4ac:	b138      	cbz	r0, 4be <flash_device_base+0x16>
        BOOT_LOG_ERR("invalid flash ID %d; expected %d",
     4ae:	4805      	ldr	r0, [pc, #20]	; (4c4 <flash_device_base+0x1c>)
     4b0:	2300      	movs	r3, #0
     4b2:	2145      	movs	r1, #69	; 0x45
     4b4:	f006 f85b 	bl	656e <z_log_minimal_printk>
                     fd_id, FLASH_DEVICE_ID);
        return -EINVAL;
     4b8:	f06f 0015 	mvn.w	r0, #21
    }
    *ret = FLASH_DEVICE_BASE;
    return 0;
}
     4bc:	bd08      	pop	{r3, pc}
    *ret = FLASH_DEVICE_BASE;
     4be:	6008      	str	r0, [r1, #0]
    return 0;
     4c0:	e7fc      	b.n	4bc <flash_device_base+0x14>
     4c2:	bf00      	nop
     4c4:	00007656 	.word	0x00007656

000004c8 <flash_area_sector_from_off>:
    return -EINVAL;
}
#endif

int flash_area_sector_from_off(off_t off, struct flash_sector *sector)
{
     4c8:	b51f      	push	{r0, r1, r2, r3, r4, lr}
     4ca:	460c      	mov	r4, r1
		union { uintptr_t x; struct flash_pages_info * val; } parm2 = { .val = info };
		return (int) arch_syscall_invoke3(parm0.x, parm1.x, parm2.x, K_SYSCALL_FLASH_GET_PAGE_INFO_BY_OFFS);
	}
#endif
	compiler_barrier();
	return z_impl_flash_get_page_info_by_offs(dev, offset, info);
     4cc:	4601      	mov	r1, r0
     4ce:	aa01      	add	r2, sp, #4
     4d0:	4804      	ldr	r0, [pc, #16]	; (4e4 <flash_area_sector_from_off+0x1c>)
     4d2:	f006 fa3f 	bl	6954 <z_impl_flash_get_page_info_by_offs>
    int rc;
    struct flash_pages_info page;

    rc = flash_get_page_info_by_offs(flash_dev, off, &page);
    if (rc) {
     4d6:	b918      	cbnz	r0, 4e0 <flash_area_sector_from_off+0x18>
        return rc;
    }

    sector->fs_off = page.start_offset;
     4d8:	9b01      	ldr	r3, [sp, #4]
     4da:	6023      	str	r3, [r4, #0]
    sector->fs_size = page.size;
     4dc:	9b02      	ldr	r3, [sp, #8]
     4de:	6063      	str	r3, [r4, #4]

    return rc;
}
     4e0:	b004      	add	sp, #16
     4e2:	bd10      	pop	{r4, pc}
     4e4:	00006fc8 	.word	0x00006fc8

000004e8 <bootutil_img_validate>:
fih_int
bootutil_img_validate(struct enc_key_data *enc_state, int image_index,
                      struct image_header *hdr, const struct flash_area *fap,
                      uint8_t *tmp_buf, uint32_t tmp_buf_sz, uint8_t *seed,
                      int seed_len, uint8_t *out_hash)
{
     4e8:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     4ec:	461e      	mov	r6, r3
     4ee:	b0db      	sub	sp, #364	; 0x16c
    uint32_t off;
    uint16_t len;
    uint16_t type;
    int sha256_valid = 0;
#ifdef EXPECTED_SIG_TLV
    fih_int valid_signature = FIH_FAILURE;
     4f0:	4b82      	ldr	r3, [pc, #520]	; (6fc <FIH_LABEL_FIH_CALL_END_1006+0x20>)
{
     4f2:	f8dd b1a0 	ldr.w	fp, [sp, #416]	; 0x1a0
    fih_int valid_signature = FIH_FAILURE;
     4f6:	f8d3 8000 	ldr.w	r8, [r3]
{
     4fa:	e9dd 5766 	ldrd	r5, r7, [sp, #408]	; 0x198
     4fe:	4614      	mov	r4, r2
}

/* Enable and disable cc310 to reduce power consumption */
static inline void cc310_sha256_init(nrf_cc310_bl_hash_context_sha256_t * ctx)
{
    cc310_init();
     500:	f000 feb0 	bl	1264 <cc310_init>
    NRF_CRYPTOCELL->ENABLE=1;
     504:	4b7e      	ldr	r3, [pc, #504]	; (700 <FIH_LABEL_FIH_CALL_END_1006+0x24>)
     506:	2201      	movs	r2, #1
     508:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
    nrf_cc310_enable();
    nrf_cc310_bl_hash_sha256_init(ctx);
     50c:	a83a      	add	r0, sp, #232	; 0xe8
     50e:	f004 fb0d 	bl	4b2c <nrf_cc310_bl_hash_sha256_init>
    if (seed && (seed_len > 0)) {
     512:	b135      	cbz	r5, 522 <bootutil_img_validate+0x3a>
     514:	2f00      	cmp	r7, #0
     516:	dd04      	ble.n	522 <bootutil_img_validate+0x3a>

static inline int bootutil_sha256_update(bootutil_sha256_context *ctx,
                                          const void *data,
                                          uint32_t data_len)
{
    cc310_sha256_update(ctx, data, data_len);
     518:	463a      	mov	r2, r7
     51a:	4629      	mov	r1, r5
     51c:	a83a      	add	r0, sp, #232	; 0xe8
     51e:	f005 ff21 	bl	6364 <cc310_sha256_update>
    size += hdr->ih_protect_tlv_size;
     522:	8963      	ldrh	r3, [r4, #10]
    size = hdr_size = hdr->ih_hdr_size;
     524:	8927      	ldrh	r7, [r4, #8]
     526:	441f      	add	r7, r3
    size += hdr->ih_protect_tlv_size;
     528:	68e3      	ldr	r3, [r4, #12]
    for (off = 0; off < size; off += blk_sz) {
     52a:	f04f 0900 	mov.w	r9, #0
    size += hdr->ih_protect_tlv_size;
     52e:	441f      	add	r7, r3
    for (off = 0; off < size; off += blk_sz) {
     530:	454f      	cmp	r7, r9
     532:	d825      	bhi.n	580 <bootutil_img_validate+0x98>
}

static inline void cc310_sha256_finalize(bootutil_sha256_context *ctx,
                                          uint8_t *output)
{
    nrf_cc310_bl_hash_sha256_finalize(ctx,
     534:	a90d      	add	r1, sp, #52	; 0x34
     536:	a83a      	add	r0, sp, #232	; 0xe8
     538:	f004 fb6a 	bl	4c10 <nrf_cc310_bl_hash_sha256_finalize>
    NRF_CRYPTOCELL->ENABLE=0;
     53c:	4b70      	ldr	r3, [pc, #448]	; (700 <FIH_LABEL_FIH_CALL_END_1006+0x24>)
     53e:	2200      	movs	r2, #0
     540:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
     544:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
            tmp_buf_sz, hash, seed, seed_len);
    if (rc) {
        goto out;
    }

    if (out_hash) {
     548:	f1bb 0f00 	cmp.w	fp, #0
     54c:	d004      	beq.n	558 <bootutil_img_validate+0x70>
        memcpy(out_hash, hash, 32);
     54e:	2220      	movs	r2, #32
     550:	a90d      	add	r1, sp, #52	; 0x34
     552:	4658      	mov	r0, fp
     554:	f006 f8be 	bl	66d4 <memcpy>
    }

    rc = bootutil_tlv_iter_begin(&it, hdr, fap, IMAGE_TLV_ANY, false);
     558:	2300      	movs	r3, #0
     55a:	9300      	str	r3, [sp, #0]
     55c:	4632      	mov	r2, r6
     55e:	f64f 73ff 	movw	r3, #65535	; 0xffff
     562:	4621      	mov	r1, r4
     564:	a807      	add	r0, sp, #28
     566:	f005 fbad 	bl	5cc4 <bootutil_tlv_iter_begin>
    if (rc) {
     56a:	4605      	mov	r5, r0
     56c:	b9d0      	cbnz	r0, 5a4 <bootutil_img_validate+0xbc>
        goto out;
    }

    if (it.tlv_end > bootutil_max_image_size(fap)) {
     56e:	4630      	mov	r0, r6
     570:	9c0c      	ldr	r4, [sp, #48]	; 0x30
     572:	f000 f983 	bl	87c <bootutil_max_image_size>
     576:	4284      	cmp	r4, r0
     578:	d91f      	bls.n	5ba <bootutil_img_validate+0xd2>
        rc = -1;
     57a:	f04f 35ff 	mov.w	r5, #4294967295
     57e:	e011      	b.n	5a4 <bootutil_img_validate+0xbc>
        if (blk_sz > tmp_buf_sz) {
     580:	9b65      	ldr	r3, [sp, #404]	; 0x194
        rc = flash_area_read(fap, off, tmp_buf, blk_sz);
     582:	9a64      	ldr	r2, [sp, #400]	; 0x190
        blk_sz = size - off;
     584:	eba7 0a09 	sub.w	sl, r7, r9
     588:	459a      	cmp	sl, r3
     58a:	bf28      	it	cs
     58c:	469a      	movcs	sl, r3
        rc = flash_area_read(fap, off, tmp_buf, blk_sz);
     58e:	4653      	mov	r3, sl
     590:	4649      	mov	r1, r9
     592:	4630      	mov	r0, r6
     594:	f005 fff9 	bl	658a <flash_area_read>
        if (rc) {
     598:	4605      	mov	r5, r0
     59a:	b138      	cbz	r0, 5ac <bootutil_img_validate+0xc4>
     59c:	4b58      	ldr	r3, [pc, #352]	; (700 <FIH_LABEL_FIH_CALL_END_1006+0x24>)
     59e:	2200      	movs	r2, #0
     5a0:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
    if (rc) {
        fih_rc = fih_int_encode(rc);
    }

    FIH_RET(fih_rc);
}
     5a4:	4628      	mov	r0, r5
     5a6:	b05b      	add	sp, #364	; 0x16c
     5a8:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
     5ac:	9964      	ldr	r1, [sp, #400]	; 0x190
     5ae:	4652      	mov	r2, sl
     5b0:	a83a      	add	r0, sp, #232	; 0xe8
     5b2:	f005 fed7 	bl	6364 <cc310_sha256_update>
    for (off = 0; off < size; off += blk_sz) {
     5b6:	44d1      	add	r9, sl
     5b8:	e7ba      	b.n	530 <bootutil_img_validate+0x48>
            if (key_id < 0 || key_id >= bootutil_key_cnt) {
     5ba:	f8df b150 	ldr.w	fp, [pc, #336]	; 70c <FIH_LABEL_FIH_CALL_END_1006+0x30>
     5be:	f8df 9140 	ldr.w	r9, [pc, #320]	; 700 <FIH_LABEL_FIH_CALL_END_1006+0x24>
    int key_id = -1;
     5c2:	f04f 37ff 	mov.w	r7, #4294967295
        rc = bootutil_tlv_iter_next(&it, &off, &len, &type);
     5c6:	f10d 0316 	add.w	r3, sp, #22
     5ca:	aa05      	add	r2, sp, #20
     5cc:	a906      	add	r1, sp, #24
     5ce:	a807      	add	r0, sp, #28
     5d0:	f005 fbc6 	bl	5d60 <bootutil_tlv_iter_next>
        if (rc < 0) {
     5d4:	1e04      	subs	r4, r0, #0
     5d6:	f2c0 808f 	blt.w	6f8 <FIH_LABEL_FIH_CALL_END_1006+0x1c>
        } else if (rc > 0) {
     5da:	f040 8082 	bne.w	6e2 <FIH_LABEL_FIH_CALL_END_1006+0x6>
        if (type == IMAGE_TLV_SHA256) {
     5de:	f8bd a016 	ldrh.w	sl, [sp, #22]
     5e2:	f1ba 0f10 	cmp.w	sl, #16
     5e6:	d118      	bne.n	61a <FIH_LABEL_FIH_CALL_END_689+0xc>
            if (len != sizeof(hash)) {
     5e8:	f8bd 5014 	ldrh.w	r5, [sp, #20]
     5ec:	2d20      	cmp	r5, #32
     5ee:	d1c4      	bne.n	57a <bootutil_img_validate+0x92>
            rc = LOAD_IMAGE_DATA(hdr, fap, off, buf, sizeof(hash));
     5f0:	9906      	ldr	r1, [sp, #24]
     5f2:	462b      	mov	r3, r5
     5f4:	aa3a      	add	r2, sp, #232	; 0xe8
     5f6:	4630      	mov	r0, r6
     5f8:	f005 ffc7 	bl	658a <flash_area_read>
            if (rc) {
     5fc:	4604      	mov	r4, r0
     5fe:	2800      	cmp	r0, #0
     600:	d17a      	bne.n	6f8 <FIH_LABEL_FIH_CALL_END_1006+0x1c>

00000602 <FIH_LABEL_FIH_CALL_START_672>:
            FIH_CALL(boot_fih_memequal, fih_rc, hash, buf, sizeof(hash));
     602:	462a      	mov	r2, r5
     604:	a93a      	add	r1, sp, #232	; 0xe8
     606:	a80d      	add	r0, sp, #52	; 0x34
     608:	f005 fc22 	bl	5e50 <boot_fih_memequal>
     60c:	4605      	mov	r5, r0

0000060e <FIH_LABEL_FIH_CALL_END_689>:
            if (fih_not_eq(fih_rc, FIH_SUCCESS)) {
     60e:	4b3d      	ldr	r3, [pc, #244]	; (704 <FIH_LABEL_FIH_CALL_END_1006+0x28>)
     610:	681b      	ldr	r3, [r3, #0]
     612:	4283      	cmp	r3, r0
     614:	d1c6      	bne.n	5a4 <bootutil_img_validate+0xbc>
            sha256_valid = 1;
     616:	2501      	movs	r5, #1
     618:	e7d5      	b.n	5c6 <bootutil_img_validate+0xde>
        } else if (type == IMAGE_TLV_KEYHASH) {
     61a:	f1ba 0f01 	cmp.w	sl, #1
     61e:	d13e      	bne.n	69e <FIH_LABEL_FIH_CALL_END_689+0x90>
            if (len > 32) {
     620:	f8bd 3014 	ldrh.w	r3, [sp, #20]
     624:	2b20      	cmp	r3, #32
     626:	d8a8      	bhi.n	57a <bootutil_img_validate+0x92>
            rc = LOAD_IMAGE_DATA(hdr, fap, off, buf, len);
     628:	9906      	ldr	r1, [sp, #24]
     62a:	aa3a      	add	r2, sp, #232	; 0xe8
     62c:	4630      	mov	r0, r6
     62e:	f005 ffac 	bl	658a <flash_area_read>
            if (rc) {
     632:	4604      	mov	r4, r0
     634:	2800      	cmp	r0, #0
     636:	d15f      	bne.n	6f8 <FIH_LABEL_FIH_CALL_END_1006+0x1c>
            key_id = bootutil_find_key(buf, len);
     638:	f89d 3014 	ldrb.w	r3, [sp, #20]
     63c:	9302      	str	r3, [sp, #8]
    if (keyhash_len > 32) {
     63e:	2b20      	cmp	r3, #32
     640:	d809      	bhi.n	656 <FIH_LABEL_FIH_CALL_END_689+0x48>
    for (i = 0; i < bootutil_key_cnt; i++) {
     642:	f8db 3000 	ldr.w	r3, [fp]
     646:	4f30      	ldr	r7, [pc, #192]	; (708 <FIH_LABEL_FIH_CALL_END_1006+0x2c>)
     648:	9303      	str	r3, [sp, #12]
     64a:	9b03      	ldr	r3, [sp, #12]
     64c:	429c      	cmp	r4, r3
     64e:	db05      	blt.n	65c <FIH_LABEL_FIH_CALL_END_689+0x4e>
     650:	2300      	movs	r3, #0
     652:	f8c9 3500 	str.w	r3, [r9, #1280]	; 0x500
        return -1;
     656:	f04f 34ff 	mov.w	r4, #4294967295
     65a:	e01c      	b.n	696 <FIH_LABEL_FIH_CALL_END_689+0x88>
    cc310_init();
     65c:	f000 fe02 	bl	1264 <cc310_init>
    NRF_CRYPTOCELL->ENABLE=1;
     660:	f8c9 a500 	str.w	sl, [r9, #1280]	; 0x500
    nrf_cc310_bl_hash_sha256_init(ctx);
     664:	a81d      	add	r0, sp, #116	; 0x74
     666:	f004 fa61 	bl	4b2c <nrf_cc310_bl_hash_sha256_init>
        bootutil_sha256_update(&sha256_ctx, key->key, *key->len);
     66a:	687a      	ldr	r2, [r7, #4]
     66c:	f857 1b08 	ldr.w	r1, [r7], #8
     670:	6812      	ldr	r2, [r2, #0]
     672:	a81d      	add	r0, sp, #116	; 0x74
     674:	f005 fe76 	bl	6364 <cc310_sha256_update>
    nrf_cc310_bl_hash_sha256_finalize(ctx,
     678:	a915      	add	r1, sp, #84	; 0x54
     67a:	a81d      	add	r0, sp, #116	; 0x74
     67c:	f004 fac8 	bl	4c10 <nrf_cc310_bl_hash_sha256_finalize>
    NRF_CRYPTOCELL->ENABLE=0;
     680:	2200      	movs	r2, #0
     682:	f8c9 2500 	str.w	r2, [r9, #1280]	; 0x500
        if (!memcmp(hash, keyhash, keyhash_len)) {
     686:	9a02      	ldr	r2, [sp, #8]
     688:	a93a      	add	r1, sp, #232	; 0xe8
     68a:	a815      	add	r0, sp, #84	; 0x54
     68c:	f006 f812 	bl	66b4 <memcmp>
     690:	b918      	cbnz	r0, 69a <FIH_LABEL_FIH_CALL_END_689+0x8c>
     692:	f8c9 0500 	str.w	r0, [r9, #1280]	; 0x500
            key_id = bootutil_find_key(buf, len);
     696:	4627      	mov	r7, r4
     698:	e795      	b.n	5c6 <bootutil_img_validate+0xde>
    for (i = 0; i < bootutil_key_cnt; i++) {
     69a:	3401      	adds	r4, #1
     69c:	e7d5      	b.n	64a <FIH_LABEL_FIH_CALL_END_689+0x3c>
        } else if (type == EXPECTED_SIG_TLV) {
     69e:	f1ba 0f22 	cmp.w	sl, #34	; 0x22
     6a2:	d190      	bne.n	5c6 <bootutil_img_validate+0xde>
            if (key_id < 0 || key_id >= bootutil_key_cnt) {
     6a4:	1c7b      	adds	r3, r7, #1
     6a6:	d08e      	beq.n	5c6 <bootutil_img_validate+0xde>
     6a8:	f8db 3000 	ldr.w	r3, [fp]
     6ac:	42bb      	cmp	r3, r7
     6ae:	dd15      	ble.n	6dc <FIH_LABEL_FIH_CALL_END_1006>
            if (!EXPECTED_SIG_LEN(len) || len > sizeof(buf)) {
     6b0:	f8bd 3014 	ldrh.w	r3, [sp, #20]
     6b4:	2b80      	cmp	r3, #128	; 0x80
     6b6:	f63f af60 	bhi.w	57a <bootutil_img_validate+0x92>
            rc = LOAD_IMAGE_DATA(hdr, fap, off, buf, len);
     6ba:	9906      	ldr	r1, [sp, #24]
     6bc:	aa3a      	add	r2, sp, #232	; 0xe8
     6be:	4630      	mov	r0, r6
     6c0:	f005 ff63 	bl	658a <flash_area_read>
            if (rc) {
     6c4:	4604      	mov	r4, r0
     6c6:	b9b8      	cbnz	r0, 6f8 <FIH_LABEL_FIH_CALL_END_1006+0x1c>

000006c8 <FIH_LABEL_FIH_CALL_START_985>:
            FIH_CALL(bootutil_verify_sig, valid_signature, hash, sizeof(hash),
     6c8:	b2ff      	uxtb	r7, r7
     6ca:	f8bd 3014 	ldrh.w	r3, [sp, #20]
     6ce:	9700      	str	r7, [sp, #0]
     6d0:	aa3a      	add	r2, sp, #232	; 0xe8
     6d2:	2120      	movs	r1, #32
     6d4:	a80d      	add	r0, sp, #52	; 0x34
     6d6:	f000 f81b 	bl	710 <bootutil_verify_sig>
     6da:	4680      	mov	r8, r0

000006dc <FIH_LABEL_FIH_CALL_END_1006>:
            key_id = -1;
     6dc:	f04f 37ff 	mov.w	r7, #4294967295
     6e0:	e771      	b.n	5c6 <bootutil_img_validate+0xde>
    if (rc) {
     6e2:	b145      	cbz	r5, 6f6 <FIH_LABEL_FIH_CALL_END_1006+0x1a>
    fih_rc = fih_int_encode_zero_equality(fih_not_eq(valid_signature,
     6e4:	4b07      	ldr	r3, [pc, #28]	; (704 <FIH_LABEL_FIH_CALL_END_1006+0x28>)
 * value that is not FIH_SUCCESS
 */
__attribute__((always_inline)) inline
fih_int fih_int_encode_zero_equality(int x)
{
    if (x) {
     6e6:	681b      	ldr	r3, [r3, #0]
     6e8:	4543      	cmp	r3, r8
        return FIH_FAILURE;
     6ea:	bf1c      	itt	ne
     6ec:	4b03      	ldrne	r3, [pc, #12]	; (6fc <FIH_LABEL_FIH_CALL_END_1006+0x20>)
     6ee:	f8d3 8000 	ldrne.w	r8, [r3]
        return -1;
     6f2:	4645      	mov	r5, r8
     6f4:	e756      	b.n	5a4 <bootutil_img_validate+0xbc>
    rc = !sha256_valid;
     6f6:	2401      	movs	r4, #1
        return -1;
     6f8:	4625      	mov	r5, r4
     6fa:	e753      	b.n	5a4 <bootutil_img_validate+0xbc>
     6fc:	20000000 	.word	0x20000000
     700:	5002a000 	.word	0x5002a000
     704:	200001f0 	.word	0x200001f0
     708:	000071ec 	.word	0x000071ec
     70c:	000071e8 	.word	0x000071e8

00000710 <bootutil_verify_sig>:
#endif /* not MCUBOOT_ECDSA_NEED_ASN1_SIG */

int
bootutil_verify_sig(uint8_t *hash, uint32_t hlen, uint8_t *sig, size_t slen,
  uint8_t key_id)
{
     710:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
     714:	b096      	sub	sp, #88	; 0x58
     716:	4617      	mov	r7, r2
     718:	461d      	mov	r5, r3
     71a:	f89d 2070 	ldrb.w	r2, [sp, #112]	; 0x70

#ifndef MCUBOOT_ECDSA_NEED_ASN1_SIG
    uint8_t signature[2 * NUM_ECC_BYTES];
#endif

    pubkey = (uint8_t *)bootutil_keys[key_id].key;
     71e:	4b35      	ldr	r3, [pc, #212]	; (7f4 <bootutil_verify_sig+0xe4>)
{
     720:	460e      	mov	r6, r1
    pubkey = (uint8_t *)bootutil_keys[key_id].key;
     722:	f853 1032 	ldr.w	r1, [r3, r2, lsl #3]
     726:	9101      	str	r1, [sp, #4]
    end = pubkey + *bootutil_keys[key_id].len;
     728:	eb03 03c2 	add.w	r3, r3, r2, lsl #3
{
     72c:	4680      	mov	r8, r0
    end = pubkey + *bootutil_keys[key_id].len;
     72e:	685b      	ldr	r3, [r3, #4]
     730:	6818      	ldr	r0, [r3, #0]
    if (mbedtls_asn1_get_tag(cp, end, &len,
     732:	aa02      	add	r2, sp, #8
     734:	4401      	add	r1, r0
     736:	2330      	movs	r3, #48	; 0x30
     738:	a801      	add	r0, sp, #4
     73a:	f005 fda1 	bl	6280 <mbedtls_asn1_get_tag>
     73e:	b120      	cbz	r0, 74a <bootutil_verify_sig+0x3a>
    rc = bootutil_parse_eckey(&ctx, &pubkey, end);
#else
    rc = bootutil_import_key(&pubkey, end);
#endif
    if (rc) {
        return -1;
     740:	f04f 30ff 	mov.w	r0, #4294967295
#endif /* CY_MBEDTLS_HW_ACCELERATION */

    bootutil_ecdsa_p256_drop(&ctx);

    return rc;
}
     744:	b016      	add	sp, #88	; 0x58
     746:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    end = *cp + len;
     74a:	e9dd 4301 	ldrd	r4, r3, [sp, #4]
     74e:	441c      	add	r4, r3
    if (mbedtls_asn1_get_alg(cp, end, &alg, &param)) {
     750:	aa03      	add	r2, sp, #12
     752:	ab06      	add	r3, sp, #24
     754:	4621      	mov	r1, r4
     756:	a801      	add	r0, sp, #4
     758:	f005 fdba 	bl	62d0 <mbedtls_asn1_get_alg>
     75c:	2800      	cmp	r0, #0
     75e:	d1ef      	bne.n	740 <bootutil_verify_sig+0x30>
    if (alg.MBEDTLS_CONTEXT_MEMBER(len) != sizeof(ec_pubkey_oid) - 1 ||
     760:	9a04      	ldr	r2, [sp, #16]
     762:	2a07      	cmp	r2, #7
     764:	d1ec      	bne.n	740 <bootutil_verify_sig+0x30>
        memcmp(alg.MBEDTLS_CONTEXT_MEMBER(p), ec_pubkey_oid, sizeof(ec_pubkey_oid) - 1)) {
     766:	4924      	ldr	r1, [pc, #144]	; (7f8 <bootutil_verify_sig+0xe8>)
     768:	9805      	ldr	r0, [sp, #20]
     76a:	f005 ffa3 	bl	66b4 <memcmp>
    if (alg.MBEDTLS_CONTEXT_MEMBER(len) != sizeof(ec_pubkey_oid) - 1 ||
     76e:	2800      	cmp	r0, #0
     770:	d1e6      	bne.n	740 <bootutil_verify_sig+0x30>
    if (param.MBEDTLS_CONTEXT_MEMBER(len) != sizeof(ec_secp256r1_oid) - 1 ||
     772:	9a07      	ldr	r2, [sp, #28]
     774:	2a08      	cmp	r2, #8
     776:	d1e3      	bne.n	740 <bootutil_verify_sig+0x30>
        memcmp(param.MBEDTLS_CONTEXT_MEMBER(p), ec_secp256r1_oid, sizeof(ec_secp256r1_oid) - 1)) {
     778:	4920      	ldr	r1, [pc, #128]	; (7fc <bootutil_verify_sig+0xec>)
     77a:	9808      	ldr	r0, [sp, #32]
     77c:	f005 ff9a 	bl	66b4 <memcmp>
    if (param.MBEDTLS_CONTEXT_MEMBER(len) != sizeof(ec_secp256r1_oid) - 1 ||
     780:	2800      	cmp	r0, #0
     782:	d1dd      	bne.n	740 <bootutil_verify_sig+0x30>
    if (mbedtls_asn1_get_bitstring_null(cp, end, &len)) {
     784:	aa02      	add	r2, sp, #8
     786:	4621      	mov	r1, r4
     788:	a801      	add	r0, sp, #4
     78a:	f005 fd8d 	bl	62a8 <mbedtls_asn1_get_bitstring_null>
     78e:	2800      	cmp	r0, #0
     790:	d1d6      	bne.n	740 <bootutil_verify_sig+0x30>
    if (*cp + len != end) {
     792:	e9dd 3201 	ldrd	r3, r2, [sp, #4]
     796:	4413      	add	r3, r2
     798:	429c      	cmp	r4, r3
     79a:	d1d1      	bne.n	740 <bootutil_verify_sig+0x30>
    if (len != 2 * NUM_ECC_BYTES + 1) {
     79c:	2a41      	cmp	r2, #65	; 0x41
     79e:	d1cf      	bne.n	740 <bootutil_verify_sig+0x30>
    rc = bootutil_decode_sig(signature, sig, sig + slen);
     7a0:	443d      	add	r5, r7
    rc = mbedtls_asn1_get_tag(&cp, end, &len,
     7a2:	2330      	movs	r3, #48	; 0x30
     7a4:	aa03      	add	r2, sp, #12
     7a6:	4629      	mov	r1, r5
     7a8:	a802      	add	r0, sp, #8
     7aa:	9702      	str	r7, [sp, #8]
     7ac:	f005 fd68 	bl	6280 <mbedtls_asn1_get_tag>
    if (rc) {
     7b0:	2800      	cmp	r0, #0
     7b2:	d1c5      	bne.n	740 <bootutil_verify_sig+0x30>
    if (cp + len > end) {
     7b4:	e9dd 3202 	ldrd	r3, r2, [sp, #8]
     7b8:	4413      	add	r3, r2
     7ba:	429d      	cmp	r5, r3
     7bc:	d3c0      	bcc.n	740 <bootutil_verify_sig+0x30>
    rc = bootutil_read_bigint(signature, &cp, end);
     7be:	462a      	mov	r2, r5
     7c0:	a902      	add	r1, sp, #8
     7c2:	a806      	add	r0, sp, #24
     7c4:	f005 fb18 	bl	5df8 <bootutil_read_bigint>
    if (rc) {
     7c8:	2800      	cmp	r0, #0
     7ca:	d1b9      	bne.n	740 <bootutil_verify_sig+0x30>
    rc = bootutil_read_bigint(signature + NUM_ECC_BYTES, &cp, end);
     7cc:	462a      	mov	r2, r5
     7ce:	a902      	add	r1, sp, #8
     7d0:	a80e      	add	r0, sp, #56	; 0x38
     7d2:	f005 fb11 	bl	5df8 <bootutil_read_bigint>
    if (rc) {
     7d6:	2800      	cmp	r0, #0
     7d8:	d1b2      	bne.n	740 <bootutil_verify_sig+0x30>
    if (hlen != NUM_ECC_BYTES) {
     7da:	2e20      	cmp	r6, #32
     7dc:	d1b0      	bne.n	740 <bootutil_verify_sig+0x30>
    rc = bootutil_ecdsa_p256_verify(&ctx, pubkey, end - pubkey, hash, signature,
     7de:	9901      	ldr	r1, [sp, #4]
    (void)ctx;
    (void)pk_len;
    (void)sig_len;

    /* Only support uncompressed keys. */
    if (pk[0] != 0x04) {
     7e0:	780b      	ldrb	r3, [r1, #0]
     7e2:	2b04      	cmp	r3, #4
     7e4:	d1ac      	bne.n	740 <bootutil_verify_sig+0x30>
        return -1;
    }
    pk++;

    return cc310_ecdsa_verify_secp256r1(hash, pk, sig, BOOTUTIL_CRYPTO_ECDSA_P256_HASH_SIZE);
     7e6:	4633      	mov	r3, r6
     7e8:	aa06      	add	r2, sp, #24
     7ea:	3101      	adds	r1, #1
     7ec:	4640      	mov	r0, r8
     7ee:	f000 fd51 	bl	1294 <cc310_ecdsa_verify_secp256r1>
     7f2:	e7a7      	b.n	744 <bootutil_verify_sig+0x34>
     7f4:	000071ec 	.word	0x000071ec
     7f8:	00007685 	.word	0x00007685
     7fc:	0000767c 	.word	0x0000767c

00000800 <boot_read_swap_size>:
    return -1;
}

int
boot_read_swap_size(int image_index, uint32_t *swap_size)
{
     800:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
     804:	b086      	sub	sp, #24
    uint8_t areas[2] = {
     806:	2302      	movs	r3, #2
    if (memcmp(magic, BOOT_IMG_MAGIC, BOOT_MAGIC_SZ) == 0) {
     808:	f8df 806c 	ldr.w	r8, [pc, #108]	; 878 <__z_interrupt_stack_SIZEOF+0x38>
    uint8_t areas[2] = {
     80c:	f8ad 3000 	strh.w	r3, [sp]
{
     810:	460d      	mov	r5, r1
     812:	466f      	mov	r7, sp
    for (i = 0; i < sizeof(areas) / sizeof(areas[0]); i++) {
     814:	2600      	movs	r6, #0
        rc = flash_area_open(areas[i], fap);
     816:	f817 0b01 	ldrb.w	r0, [r7], #1
     81a:	a901      	add	r1, sp, #4
     81c:	f001 f8e6 	bl	19ec <flash_area_open>
        if (rc != 0) {
     820:	4604      	mov	r4, r0
     822:	b9a0      	cbnz	r0, 84e <__z_interrupt_stack_SIZEOF+0xe>
        off = boot_magic_off(*fap);
     824:	9801      	ldr	r0, [sp, #4]
    return flash_area_get_size(fap) - BOOT_MAGIC_SZ;
     826:	6881      	ldr	r1, [r0, #8]
        rc = flash_area_read(*fap, off, magic, BOOT_MAGIC_SZ);
     828:	2310      	movs	r3, #16
     82a:	aa02      	add	r2, sp, #8
     82c:	3910      	subs	r1, #16
     82e:	f005 feac 	bl	658a <flash_area_read>
     832:	4604      	mov	r4, r0
        flash_area_close(*fap);
     834:	9801      	ldr	r0, [sp, #4]
     836:	f005 fea7 	bl	6588 <flash_area_close>
        if (rc != 0) {
     83a:	b944      	cbnz	r4, 84e <__z_interrupt_stack_SIZEOF+0xe>
    if (memcmp(magic, BOOT_IMG_MAGIC, BOOT_MAGIC_SZ) == 0) {
     83c:	2210      	movs	r2, #16
     83e:	4641      	mov	r1, r8
     840:	a802      	add	r0, sp, #8
     842:	f005 ff37 	bl	66b4 <memcmp>
     846:	b140      	cbz	r0, 85a <__z_interrupt_stack_SIZEOF+0x1a>
    for (i = 0; i < sizeof(areas) / sizeof(areas[0]); i++) {
     848:	b12e      	cbz	r6, 856 <__z_interrupt_stack_SIZEOF+0x16>
    return -1;
     84a:	f04f 34ff 	mov.w	r4, #4294967295
        rc = flash_area_read(fap, off, swap_size, sizeof *swap_size);
        flash_area_close(fap);
    }

    return rc;
}
     84e:	4620      	mov	r0, r4
     850:	b006      	add	sp, #24
     852:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    for (i = 0; i < sizeof(areas) / sizeof(areas[0]); i++) {
     856:	2601      	movs	r6, #1
     858:	e7dd      	b.n	816 <boot_read_swap_size+0x16>
    return boot_swap_info_off(fap) - BOOT_MAX_ALIGN;
     85a:	9801      	ldr	r0, [sp, #4]
     85c:	f006 f997 	bl	6b8e <boot_swap_info_off>
        rc = flash_area_read(fap, off, swap_size, sizeof *swap_size);
     860:	2304      	movs	r3, #4
     862:	f1a0 0108 	sub.w	r1, r0, #8
     866:	462a      	mov	r2, r5
     868:	9801      	ldr	r0, [sp, #4]
     86a:	f005 fe8e 	bl	658a <flash_area_read>
     86e:	4604      	mov	r4, r0
        flash_area_close(fap);
     870:	9801      	ldr	r0, [sp, #4]
     872:	f005 fe89 	bl	6588 <flash_area_close>
     876:	e7ea      	b.n	84e <__z_interrupt_stack_SIZEOF+0xe>
     878:	00007560 	.word	0x00007560

0000087c <bootutil_max_image_size>:
    return 0;
}
#endif

uint32_t bootutil_max_image_size(const struct flash_area *fap)
{
     87c:	b507      	push	{r0, r1, r2, lr}
#if defined(MCUBOOT_SWAP_USING_SCRATCH)
    return boot_status_off(fap);
#elif defined(MCUBOOT_SWAP_USING_MOVE)
    struct flash_sector sector;
    /* get the last sector offset */
    int rc = flash_area_sector_from_off(boot_status_off(fap), &sector);
     87e:	f005 fafb 	bl	5e78 <boot_status_off>
     882:	4669      	mov	r1, sp
     884:	f7ff fe20 	bl	4c8 <flash_area_sector_from_off>
    if (rc) {
     888:	b138      	cbz	r0, 89a <bootutil_max_image_size+0x1e>
        BOOT_LOG_ERR("Unable to determine flash sector of the image trailer");
     88a:	4805      	ldr	r0, [pc, #20]	; (8a0 <bootutil_max_image_size+0x24>)
     88c:	2145      	movs	r1, #69	; 0x45
     88e:	f005 fe6e 	bl	656e <z_log_minimal_printk>
        return 0; /* Returning of zero here should cause any check which uses
     892:	2000      	movs	r0, #0
#elif defined(MCUBOOT_DIRECT_XIP)
    return boot_swap_info_off(fap);
#elif defined(MCUBOOT_RAM_LOAD)
    return boot_swap_info_off(fap);
#endif
}
     894:	b003      	add	sp, #12
     896:	f85d fb04 	ldr.w	pc, [sp], #4
 */
uint8_t flash_area_erased_val(const struct flash_area *fap);

static inline uint32_t flash_sector_get_off(const struct flash_sector *fs)
{
	return fs->fs_off;
     89a:	9800      	ldr	r0, [sp, #0]
    return flash_sector_get_off(&sector);
     89c:	e7fa      	b.n	894 <bootutil_max_image_size+0x18>
     89e:	bf00      	nop
     8a0:	0000768d 	.word	0x0000768d

000008a4 <boot_validate_slot.isra.0>:
 *         FIH_SUCCESS                      if image was successfully validated
 *         1 (or its fih_int encoded form)  if no bootloable image was found
 *         FIH_FAILURE                      on any errors
 */
static fih_int
boot_validate_slot(struct boot_loader_state *state, int slot,
     8a4:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
                   struct boot_status *bs)
{
    const struct flash_area *fap;
    struct image_header *hdr;
    int area_id;
    fih_int fih_rc = FIH_FAILURE;
     8a8:	4b35      	ldr	r3, [pc, #212]	; (980 <FIH_LABEL_FIH_CALL_END_437+0x76>)
boot_validate_slot(struct boot_loader_state *state, int slot,
     8aa:	b088      	sub	sp, #32
     8ac:	4606      	mov	r6, r0
    int rc;

    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
     8ae:	2000      	movs	r0, #0
boot_validate_slot(struct boot_loader_state *state, int slot,
     8b0:	460c      	mov	r4, r1
    fih_int fih_rc = FIH_FAILURE;
     8b2:	681d      	ldr	r5, [r3, #0]
    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
     8b4:	f005 f9fa 	bl	5cac <flash_area_id_from_multi_image_slot>
    rc = flash_area_open(area_id, &fap);
     8b8:	a906      	add	r1, sp, #24
     8ba:	b2c0      	uxtb	r0, r0
     8bc:	f001 f896 	bl	19ec <flash_area_open>
    if (rc != 0) {
     8c0:	2800      	cmp	r0, #0
     8c2:	d157      	bne.n	974 <FIH_LABEL_FIH_CALL_END_437+0x6a>
    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
     8c4:	4621      	mov	r1, r4
     8c6:	f005 f9f1 	bl	5cac <flash_area_id_from_multi_image_slot>
     ((swap_type) == BOOT_SWAP_TYPE_PERM))

static inline struct image_header*
boot_img_hdr(struct boot_loader_state *state, size_t slot)
{
    return &BOOT_IMG(state, slot).hdr;
     8ca:	252c      	movs	r5, #44	; 0x2c
    rc = flash_area_open(area_id, &fap);
     8cc:	a907      	add	r1, sp, #28
     8ce:	b2c0      	uxtb	r0, r0
     8d0:	fb05 6504 	mla	r5, r5, r4, r6
     8d4:	f001 f88a 	bl	19ec <flash_area_open>
    if (rc != 0) {
     8d8:	2800      	cmp	r0, #0
     8da:	d033      	beq.n	944 <FIH_LABEL_FIH_CALL_END_437+0x3a>
        FIH_RET(fih_rc);
    }

    hdr = boot_img_hdr(state, slot);
    if (boot_check_header_erased(state, slot) == 0 ||
        (hdr->ih_flags & IMAGE_F_NON_BOOTABLE)) {
     8dc:	272c      	movs	r7, #44	; 0x2c
     8de:	4367      	muls	r7, r4
     8e0:	eb06 0807 	add.w	r8, r6, r7
#endif
    BOOT_HOOK_CALL_FIH(boot_image_check_hook, fih_int_encode(BOOT_HOOK_REGULAR),
                       fih_rc, BOOT_CURR_IMG(state), slot);
    if (fih_eq(fih_rc, fih_int_encode(BOOT_HOOK_REGULAR)))
    {
        FIH_CALL(boot_image_check, fih_rc, state, hdr, fap, bs);
     8e4:	9b06      	ldr	r3, [sp, #24]
        (hdr->ih_flags & IMAGE_F_NON_BOOTABLE)) {
     8e6:	f8d8 1010 	ldr.w	r1, [r8, #16]
    if (boot_check_header_erased(state, slot) == 0 ||
     8ea:	f011 0110 	ands.w	r1, r1, #16
     8ee:	d138      	bne.n	962 <FIH_LABEL_FIH_CALL_END_437+0x58>

000008f0 <FIH_LABEL_FIH_CALL_START_388>:
    FIH_CALL(bootutil_img_validate, fih_rc, BOOT_CURR_ENC(state), image_index,
     8f0:	f44f 7280 	mov.w	r2, #256	; 0x100
     8f4:	9201      	str	r2, [sp, #4]
     8f6:	4a23      	ldr	r2, [pc, #140]	; (984 <FIH_LABEL_FIH_CALL_END_437+0x7a>)
     8f8:	9200      	str	r2, [sp, #0]
     8fa:	e9cd 1103 	strd	r1, r1, [sp, #12]
     8fe:	462a      	mov	r2, r5
     900:	9102      	str	r1, [sp, #8]
     902:	4608      	mov	r0, r1
     904:	f7ff fdf0 	bl	4e8 <bootutil_img_validate>
     908:	4605      	mov	r5, r0

0000090a <FIH_LABEL_FIH_CALL_END_437>:
    if (hdr->ih_magic != IMAGE_MAGIC) {
     90a:	4b1f      	ldr	r3, [pc, #124]	; (988 <FIH_LABEL_FIH_CALL_END_437+0x7e>)
     90c:	59f2      	ldr	r2, [r6, r7]
    }
    if (!boot_is_header_valid(hdr, fap) || fih_not_eq(fih_rc, FIH_SUCCESS)) {
     90e:	9806      	ldr	r0, [sp, #24]
    if (hdr->ih_magic != IMAGE_MAGIC) {
     910:	429a      	cmp	r2, r3
     912:	d10c      	bne.n	92e <FIH_LABEL_FIH_CALL_END_437+0x24>
    if (!boot_u32_safe_add(&size, hdr->ih_img_size, hdr->ih_hdr_size)) {
     914:	f8d8 200c 	ldr.w	r2, [r8, #12]
     918:	f8b8 3008 	ldrh.w	r3, [r8, #8]
    if (a > UINT32_MAX - b) {
     91c:	189b      	adds	r3, r3, r2
     91e:	d206      	bcs.n	92e <FIH_LABEL_FIH_CALL_END_437+0x24>
    if (size >= flash_area_get_size(fap)) {
     920:	6882      	ldr	r2, [r0, #8]
     922:	4293      	cmp	r3, r2
     924:	d203      	bcs.n	92e <FIH_LABEL_FIH_CALL_END_437+0x24>
    if (!boot_is_header_valid(hdr, fap) || fih_not_eq(fih_rc, FIH_SUCCESS)) {
     926:	4b19      	ldr	r3, [pc, #100]	; (98c <FIH_LABEL_FIH_CALL_END_437+0x82>)
     928:	681b      	ldr	r3, [r3, #0]
     92a:	42ab      	cmp	r3, r5
     92c:	d01f      	beq.n	96e <FIH_LABEL_FIH_CALL_END_437+0x64>
        if ((slot != BOOT_PRIMARY_SLOT) || ARE_SLOTS_EQUIVALENT()) {
     92e:	b32c      	cbz	r4, 97c <FIH_LABEL_FIH_CALL_END_437+0x72>
            flash_area_erase(fap, 0, flash_area_get_size(fap));
     930:	6882      	ldr	r2, [r0, #8]
     932:	2100      	movs	r1, #0
     934:	f005 fe53 	bl	65de <flash_area_erase>
            /* Image is invalid, erase it to prevent further unnecessary
             * attempts to validate and boot it.
             */
        }
#if !defined(__BOOTSIM__)
        BOOT_LOG_ERR("Image in the %s slot is not valid!",
     938:	4a15      	ldr	r2, [pc, #84]	; (990 <FIH_LABEL_FIH_CALL_END_437+0x86>)
     93a:	4816      	ldr	r0, [pc, #88]	; (994 <FIH_LABEL_FIH_CALL_END_437+0x8a>)
     93c:	2145      	movs	r1, #69	; 0x45
     93e:	f005 fe16 	bl	656e <z_log_minimal_printk>
                     (slot == BOOT_PRIMARY_SLOT) ? "primary" : "secondary");
#endif
        fih_rc = fih_int_encode(1);
        goto out;
     942:	e013      	b.n	96c <FIH_LABEL_FIH_CALL_END_437+0x62>
    erased_val = flash_area_erased_val(fap);
     944:	9807      	ldr	r0, [sp, #28]
     946:	f005 fe67 	bl	6618 <flash_area_erased_val>
     94a:	4607      	mov	r7, r0
    flash_area_close(fap);
     94c:	9807      	ldr	r0, [sp, #28]
     94e:	f005 fe1b 	bl	6588 <flash_area_close>
    for (i = 0; i < len; i++) {
     952:	1e6b      	subs	r3, r5, #1
     954:	1cea      	adds	r2, r5, #3
        if (val != p[i]) {
     956:	f813 1f01 	ldrb.w	r1, [r3, #1]!
     95a:	42b9      	cmp	r1, r7
     95c:	d1be      	bne.n	8dc <boot_validate_slot.isra.0+0x38>
    for (i = 0; i < len; i++) {
     95e:	4293      	cmp	r3, r2
     960:	d1f9      	bne.n	956 <FIH_LABEL_FIH_CALL_END_437+0x4c>
        if (slot != BOOT_PRIMARY_SLOT) {
     962:	b11c      	cbz	r4, 96c <FIH_LABEL_FIH_CALL_END_437+0x62>
            swap_erase_trailer_sectors(state, fap);
     964:	9906      	ldr	r1, [sp, #24]
     966:	4630      	mov	r0, r6
     968:	f005 fb6a 	bl	6040 <swap_erase_trailer_sectors>
        fih_rc = fih_int_encode(1);
     96c:	2501      	movs	r5, #1
        }
    }
#endif

out:
    flash_area_close(fap);
     96e:	9806      	ldr	r0, [sp, #24]
     970:	f005 fe0a 	bl	6588 <flash_area_close>

    FIH_RET(fih_rc);
}
     974:	4628      	mov	r0, r5
     976:	b008      	add	sp, #32
     978:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
        BOOT_LOG_ERR("Image in the %s slot is not valid!",
     97c:	4a06      	ldr	r2, [pc, #24]	; (998 <FIH_LABEL_FIH_CALL_END_437+0x8e>)
     97e:	e7dc      	b.n	93a <FIH_LABEL_FIH_CALL_END_437+0x30>
     980:	20000000 	.word	0x20000000
     984:	20000fbc 	.word	0x20000fbc
     988:	96f3b83d 	.word	0x96f3b83d
     98c:	200001f0 	.word	0x200001f0
     990:	000076d0 	.word	0x000076d0
     994:	000076da 	.word	0x000076da
     998:	000076c8 	.word	0x000076c8

0000099c <boot_swap_image>:
 *
 * @return                      0 on success; nonzero on failure.
 */
static int
boot_swap_image(struct boot_loader_state *state, struct boot_status *bs)
{
     99c:	b573      	push	{r0, r1, r4, r5, r6, lr}
     99e:	460d      	mov	r5, r1
     9a0:	4604      	mov	r4, r0
    uint8_t image_index;
    int rc;

    /* FIXME: just do this if asked by user? */

    size = copy_size = 0;
     9a2:	2100      	movs	r1, #0
    image_index = BOOT_CURR_IMG(state);

    if (boot_status_is_reset(bs)) {
     9a4:	4628      	mov	r0, r5
    size = copy_size = 0;
     9a6:	e9cd 1100 	strd	r1, r1, [sp]
    if (boot_status_is_reset(bs)) {
     9aa:	f005 fb08 	bl	5fbe <boot_status_is_reset>
     9ae:	b330      	cbz	r0, 9fe <boot_swap_image+0x62>
        /*
         * No swap ever happened, so need to find the largest image which
         * will be used to determine the amount of sectors to swap.
         */
        hdr = boot_img_hdr(state, BOOT_PRIMARY_SLOT);
        if (hdr->ih_magic == IMAGE_MAGIC) {
     9b0:	4e16      	ldr	r6, [pc, #88]	; (a0c <boot_swap_image+0x70>)
     9b2:	6823      	ldr	r3, [r4, #0]
     9b4:	42b3      	cmp	r3, r6
     9b6:	d103      	bne.n	9c0 <boot_swap_image+0x24>
            rc = boot_read_image_size(state, BOOT_PRIMARY_SLOT, &copy_size);
     9b8:	aa01      	add	r2, sp, #4
     9ba:	4620      	mov	r0, r4
     9bc:	f005 fa94 	bl	5ee8 <boot_read_image_size.constprop.0.isra.0>
            memset(bs->enckey[0], 0xff, BOOT_ENC_KEY_ALIGN_SIZE);
        }
#endif

        hdr = boot_img_hdr(state, BOOT_SECONDARY_SLOT);
        if (hdr->ih_magic == IMAGE_MAGIC) {
     9c0:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
     9c2:	42b3      	cmp	r3, r6
     9c4:	d104      	bne.n	9d0 <boot_swap_image+0x34>
            rc = boot_read_image_size(state, BOOT_SECONDARY_SLOT, &size);
     9c6:	466a      	mov	r2, sp
     9c8:	2101      	movs	r1, #1
     9ca:	4620      	mov	r0, r4
     9cc:	f005 fa8c 	bl	5ee8 <boot_read_image_size.constprop.0.isra.0>
        } else {
            memset(bs->enckey[1], 0xff, BOOT_ENC_KEY_ALIGN_SIZE);
        }
#endif

        if (size > copy_size) {
     9d0:	e9dd 3200 	ldrd	r3, r2, [sp]
     9d4:	4293      	cmp	r3, r2
            copy_size = size;
     9d6:	bf88      	it	hi
     9d8:	9301      	strhi	r3, [sp, #4]
        }

        bs->swap_size = copy_size;
     9da:	9b01      	ldr	r3, [sp, #4]
     9dc:	60ab      	str	r3, [r5, #8]
            }
        }
#endif
    }

    swap_run(state, bs, copy_size);
     9de:	9a01      	ldr	r2, [sp, #4]
     9e0:	4629      	mov	r1, r5
     9e2:	4620      	mov	r0, r4
     9e4:	f000 fb34 	bl	1050 <swap_run>

#ifdef MCUBOOT_VALIDATE_PRIMARY_SLOT
    extern int boot_status_fails;
    if (boot_status_fails > 0) {
     9e8:	4b09      	ldr	r3, [pc, #36]	; (a10 <boot_swap_image+0x74>)
     9ea:	681a      	ldr	r2, [r3, #0]
     9ec:	2a00      	cmp	r2, #0
     9ee:	dd03      	ble.n	9f8 <boot_swap_image+0x5c>
        BOOT_LOG_WRN("%d status write fails performing the swap",
     9f0:	4808      	ldr	r0, [pc, #32]	; (a14 <boot_swap_image+0x78>)
     9f2:	2157      	movs	r1, #87	; 0x57
     9f4:	f005 fdbb 	bl	656e <z_log_minimal_printk>
#endif
    rc = BOOT_HOOK_CALL(boot_copy_region_post_hook, 0, BOOT_CURR_IMG(state),
                        BOOT_IMG_AREA(state, BOOT_PRIMARY_SLOT), size);

    return 0;
}
     9f8:	2000      	movs	r0, #0
     9fa:	b002      	add	sp, #8
     9fc:	bd70      	pop	{r4, r5, r6, pc}
        rc = boot_read_swap_size(image_index, &bs->swap_size);
     9fe:	f105 0108 	add.w	r1, r5, #8
     a02:	f7ff fefd 	bl	800 <boot_read_swap_size>
        copy_size = bs->swap_size;
     a06:	68ab      	ldr	r3, [r5, #8]
     a08:	9301      	str	r3, [sp, #4]
     a0a:	e7e8      	b.n	9de <boot_swap_image+0x42>
     a0c:	96f3b83d 	.word	0x96f3b83d
     a10:	20000e54 	.word	0x20000e54
     a14:	00007702 	.word	0x00007702

00000a18 <boot_copy_region>:
{
     a18:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
        rc = flash_area_read(fap_src, off_src + bytes_copied, buf, chunk_sz);
     a1c:	f8df b078 	ldr.w	fp, [pc, #120]	; a98 <boot_copy_region+0x80>
     a20:	4c1b      	ldr	r4, [pc, #108]	; (a90 <boot_copy_region+0x78>)
     a22:	4d1c      	ldr	r5, [pc, #112]	; (a94 <boot_copy_region+0x7c>)
{
     a24:	4688      	mov	r8, r1
     a26:	4691      	mov	r9, r2
     a28:	469a      	mov	sl, r3
    bytes_copied = 0;
     a2a:	2600      	movs	r6, #0
    while (bytes_copied < sz) {
     a2c:	9b0b      	ldr	r3, [sp, #44]	; 0x2c
     a2e:	429e      	cmp	r6, r3
     a30:	d301      	bcc.n	a36 <boot_copy_region+0x1e>
    return 0;
     a32:	2000      	movs	r0, #0
     a34:	e00f      	b.n	a56 <boot_copy_region+0x3e>
        if (sz - bytes_copied > sizeof buf) {
     a36:	9b0b      	ldr	r3, [sp, #44]	; 0x2c
        rc = flash_area_read(fap_src, off_src + bytes_copied, buf, chunk_sz);
     a38:	4a17      	ldr	r2, [pc, #92]	; (a98 <boot_copy_region+0x80>)
        if (sz - bytes_copied > sizeof buf) {
     a3a:	1b9f      	subs	r7, r3, r6
     a3c:	f5b7 6f80 	cmp.w	r7, #1024	; 0x400
     a40:	bf28      	it	cs
     a42:	f44f 6780 	movcs.w	r7, #1024	; 0x400
        rc = flash_area_read(fap_src, off_src + bytes_copied, buf, chunk_sz);
     a46:	463b      	mov	r3, r7
     a48:	eb06 010a 	add.w	r1, r6, sl
     a4c:	4640      	mov	r0, r8
     a4e:	f005 fd9c 	bl	658a <flash_area_read>
        if (rc != 0) {
     a52:	b110      	cbz	r0, a5a <boot_copy_region+0x42>
            return BOOT_EFLASH;
     a54:	2001      	movs	r0, #1
}
     a56:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
        rc = flash_area_write(fap_dst, off_dst + bytes_copied, buf, chunk_sz);
     a5a:	990a      	ldr	r1, [sp, #40]	; 0x28
     a5c:	463b      	mov	r3, r7
     a5e:	465a      	mov	r2, fp
     a60:	1871      	adds	r1, r6, r1
     a62:	4648      	mov	r0, r9
     a64:	f005 fda6 	bl	65b4 <flash_area_write>
        if (rc != 0) {
     a68:	2800      	cmp	r0, #0
     a6a:	d1f3      	bne.n	a54 <boot_copy_region+0x3c>
     a6c:	f8c4 5600 	str.w	r5, [r4, #1536]	; 0x600
        bytes_copied += chunk_sz;
     a70:	443e      	add	r6, r7
     a72:	f8c4 5604 	str.w	r5, [r4, #1540]	; 0x604
     a76:	f8c4 5608 	str.w	r5, [r4, #1544]	; 0x608
     a7a:	f8c4 560c 	str.w	r5, [r4, #1548]	; 0x60c
     a7e:	f8c4 5610 	str.w	r5, [r4, #1552]	; 0x610
     a82:	f8c4 5614 	str.w	r5, [r4, #1556]	; 0x614
     a86:	f8c4 5618 	str.w	r5, [r4, #1560]	; 0x618
     a8a:	f8c4 561c 	str.w	r5, [r4, #1564]	; 0x61c
        MCUBOOT_WATCHDOG_FEED();
     a8e:	e7cd      	b.n	a2c <boot_copy_region+0x14>
     a90:	40010000 	.word	0x40010000
     a94:	6e524635 	.word	0x6e524635
     a98:	200009f4 	.word	0x200009f4

00000a9c <context_boot_go>:
#endif
}

fih_int
context_boot_go(struct boot_loader_state *state, struct boot_rsp *rsp)
{
     a9c:	e92d 41ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr}
        boot_enc_zeroize(BOOT_CURR_ENC(state));
#endif

        image_index = BOOT_CURR_IMG(state);

        BOOT_IMG(state, BOOT_PRIMARY_SLOT).sectors =
     aa0:	4b8f      	ldr	r3, [pc, #572]	; (ce0 <FIH_LABEL_FIH_CALL_END_2278+0x42>)
     aa2:	6243      	str	r3, [r0, #36]	; 0x24
{
     aa4:	460e      	mov	r6, r1
            primary_slot_sectors[image_index];
        BOOT_IMG(state, BOOT_SECONDARY_SLOT).sectors =
     aa6:	4b8f      	ldr	r3, [pc, #572]	; (ce4 <FIH_LABEL_FIH_CALL_END_2278+0x46>)
     aa8:	6503      	str	r3, [r0, #80]	; 0x50

        /* Open primary and secondary image areas for the duration
         * of this call.
         */
        for (slot = 0; slot < BOOT_NUM_SLOTS; slot++) {
            fa_id = flash_area_id_from_multi_image_slot(image_index, slot);
     aaa:	2100      	movs	r1, #0
{
     aac:	4604      	mov	r4, r0
            fa_id = flash_area_id_from_multi_image_slot(image_index, slot);
     aae:	4608      	mov	r0, r1
     ab0:	f005 f8fc 	bl	5cac <flash_area_id_from_multi_image_slot>
            rc = flash_area_open(fa_id, &BOOT_IMG_AREA(state, slot));
     ab4:	f104 0120 	add.w	r1, r4, #32
     ab8:	b2c0      	uxtb	r0, r0
     aba:	f000 ff97 	bl	19ec <flash_area_open>
            fa_id = flash_area_id_from_multi_image_slot(image_index, slot);
     abe:	2101      	movs	r1, #1
     ac0:	2000      	movs	r0, #0
     ac2:	f005 f8f3 	bl	5cac <flash_area_id_from_multi_image_slot>
            rc = flash_area_open(fa_id, &BOOT_IMG_AREA(state, slot));
     ac6:	f104 014c 	add.w	r1, r4, #76	; 0x4c
     aca:	b2c0      	uxtb	r0, r0
     acc:	f000 ff8e 	bl	19ec <flash_area_open>
     ad0:	4605      	mov	r5, r0
    rc = boot_read_sectors(state);
     ad2:	4620      	mov	r0, r4
     ad4:	f005 fa49 	bl	5f6a <boot_read_sectors>
    if (rc != 0) {
     ad8:	4607      	mov	r7, r0
     ada:	b968      	cbnz	r0, af8 <context_boot_go+0x5c>
    rc = boot_read_image_headers(state, false, NULL);
     adc:	2200      	movs	r2, #0
     ade:	4611      	mov	r1, r2
     ae0:	4620      	mov	r0, r4
     ae2:	f005 f9eb 	bl	5ebc <boot_read_image_headers>
    if (rc != 0) {
     ae6:	4607      	mov	r7, r0
     ae8:	b300      	cbz	r0, b2c <context_boot_go+0x90>
        BOOT_LOG_WRN("Failed reading image headers; Image=%u",
     aea:	487f      	ldr	r0, [pc, #508]	; (ce8 <FIH_LABEL_FIH_CALL_END_2278+0x4a>)
     aec:	2200      	movs	r2, #0
     aee:	2157      	movs	r1, #87	; 0x57
            BOOT_LOG_WRN("Failed reading boot status; Image=%u",
     af0:	f005 fd3d 	bl	656e <z_log_minimal_printk>
        BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_NONE;
     af4:	2301      	movs	r3, #1
     af6:	e08f      	b.n	c18 <FIH_LABEL_FIH_CALL_END_2027+0xe>
        BOOT_LOG_WRN("Failed reading sectors; BOOT_MAX_IMG_SECTORS=%d"
     af8:	487c      	ldr	r0, [pc, #496]	; (cec <FIH_LABEL_FIH_CALL_END_2278+0x4e>)
     afa:	2280      	movs	r2, #128	; 0x80
     afc:	2157      	movs	r1, #87	; 0x57
     afe:	f005 fd36 	bl	656e <z_log_minimal_printk>
        BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_NONE;
     b02:	2301      	movs	r3, #1
        if (rc == BOOT_EFLASH)
     b04:	429f      	cmp	r7, r3
        BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_NONE;
     b06:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
        if (rc == BOOT_EFLASH)
     b0a:	d1e7      	bne.n	adc <context_boot_go+0x40>
#endif

        /* Determine swap type and complete swap if it has been aborted. */
        boot_prepare_image_for_update(state, &bs);

        if (BOOT_IS_UPGRADE(BOOT_SWAP_TYPE(state))) {
     b0c:	f894 3058 	ldrb.w	r3, [r4, #88]	; 0x58
        /* Indicate that swap is not aborted */
        boot_status_reset(&bs);
#endif /* (BOOT_IMAGE_NUMBER > 1) */

        /* Set the previously determined swap type */
        bs.swap_type = BOOT_SWAP_TYPE(state);
     b10:	f88d 3007 	strb.w	r3, [sp, #7]

        switch (BOOT_SWAP_TYPE(state)) {
     b14:	2b04      	cmp	r3, #4
     b16:	f200 8082 	bhi.w	c1e <FIH_LABEL_FIH_CALL_END_2027+0x14>
     b1a:	2b01      	cmp	r3, #1
     b1c:	f200 8085 	bhi.w	c2a <FIH_LABEL_FIH_CALL_END_2027+0x20>
     b20:	f000 809c 	beq.w	c5c <FIH_LABEL_FIH_CALL_END_2027+0x52>
            }
#endif /* !MCUBOOT_OVERWRITE_ONLY */
            break;

        default:
            BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_PANIC;
     b24:	23ff      	movs	r3, #255	; 0xff
     b26:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
     b2a:	e097      	b.n	c5c <FIH_LABEL_FIH_CALL_END_2027+0x52>
    if (boot_slots_compatible(state)) {
     b2c:	4620      	mov	r0, r4
     b2e:	f000 f9a7 	bl	e80 <boot_slots_compatible>
     b32:	2800      	cmp	r0, #0
     b34:	d0de      	beq.n	af4 <context_boot_go+0x58>
        boot_status_reset(bs);
     b36:	4668      	mov	r0, sp
     b38:	f005 fa38 	bl	5fac <boot_status_reset>
        rc = swap_read_status(state, bs);
     b3c:	4669      	mov	r1, sp
     b3e:	4620      	mov	r0, r4
     b40:	f005 fad3 	bl	60ea <swap_read_status>
        if (rc != 0) {
     b44:	b118      	cbz	r0, b4e <context_boot_go+0xb2>
            BOOT_LOG_WRN("Failed reading boot status; Image=%u",
     b46:	486a      	ldr	r0, [pc, #424]	; (cf0 <FIH_LABEL_FIH_CALL_END_2278+0x52>)
     b48:	463a      	mov	r2, r7
     b4a:	2157      	movs	r1, #87	; 0x57
     b4c:	e7d0      	b.n	af0 <context_boot_go+0x54>
        rc = boot_read_image_headers(state, !boot_status_is_reset(bs), bs);
     b4e:	4668      	mov	r0, sp
     b50:	f005 fa35 	bl	5fbe <boot_status_is_reset>
     b54:	f080 0101 	eor.w	r1, r0, #1
     b58:	466a      	mov	r2, sp
     b5a:	b2c9      	uxtb	r1, r1
     b5c:	4620      	mov	r0, r4
     b5e:	f005 f9ad 	bl	5ebc <boot_read_image_headers>
        if (rc != 0) {
     b62:	4602      	mov	r2, r0
     b64:	2800      	cmp	r0, #0
     b66:	d1c0      	bne.n	aea <context_boot_go+0x4e>
        if (!boot_status_is_reset(bs)) {
     b68:	4668      	mov	r0, sp
     b6a:	f005 fa28 	bl	5fbe <boot_status_is_reset>
     b6e:	4607      	mov	r7, r0
     b70:	bb60      	cbnz	r0, bcc <context_boot_go+0x130>
    rc = boot_swap_image(state, bs);
     b72:	4669      	mov	r1, sp
     b74:	4620      	mov	r0, r4
     b76:	f7ff ff11 	bl	99c <boot_swap_image>
    BOOT_SWAP_TYPE(state) = bs->swap_type;
     b7a:	f89d 3007 	ldrb.w	r3, [sp, #7]
     b7e:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
    if (bs->swap_type == BOOT_SWAP_TYPE_REVERT ||
     b82:	3b03      	subs	r3, #3
     b84:	2b01      	cmp	r3, #1
     b86:	d806      	bhi.n	b96 <context_boot_go+0xfa>
        rc = swap_set_image_ok(BOOT_CURR_IMG(state));
     b88:	4638      	mov	r0, r7
     b8a:	f005 fafc 	bl	6186 <swap_set_image_ok>
        if (rc != 0) {
     b8e:	b110      	cbz	r0, b96 <context_boot_go+0xfa>
            BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_PANIC;
     b90:	23ff      	movs	r3, #255	; 0xff
     b92:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
    if (BOOT_IS_UPGRADE(bs->swap_type)) {
     b96:	f89d 3007 	ldrb.w	r3, [sp, #7]
     b9a:	3b02      	subs	r3, #2
     b9c:	2b02      	cmp	r3, #2
     b9e:	d80b      	bhi.n	bb8 <context_boot_go+0x11c>
        rc = swap_set_copy_done(BOOT_CURR_IMG(state));
     ba0:	2000      	movs	r0, #0
     ba2:	f005 fade 	bl	6162 <swap_set_copy_done>
        if (rc != 0) {
     ba6:	b138      	cbz	r0, bb8 <context_boot_go+0x11c>
            BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_PANIC;
     ba8:	23ff      	movs	r3, #255	; 0xff
     baa:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
        BOOT_LOG_ERR("panic!");
     bae:	4851      	ldr	r0, [pc, #324]	; (cf4 <FIH_LABEL_FIH_CALL_END_2278+0x56>)
     bb0:	2145      	movs	r1, #69	; 0x45
     bb2:	f005 fcdc 	bl	656e <z_log_minimal_printk>
        while (1) {}
     bb6:	e7fe      	b.n	bb6 <context_boot_go+0x11a>
    if (BOOT_SWAP_TYPE(state) == BOOT_SWAP_TYPE_PANIC) {
     bb8:	f894 3058 	ldrb.w	r3, [r4, #88]	; 0x58
     bbc:	2bff      	cmp	r3, #255	; 0xff
     bbe:	d0f6      	beq.n	bae <context_boot_go+0x112>
            rc = boot_read_image_headers(state, false, bs);
     bc0:	466a      	mov	r2, sp
     bc2:	2100      	movs	r1, #0
     bc4:	4620      	mov	r0, r4
     bc6:	f005 f979 	bl	5ebc <boot_read_image_headers>
            BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_NONE;
     bca:	e793      	b.n	af4 <context_boot_go+0x58>
            if (bs->swap_type == BOOT_SWAP_TYPE_NONE) {
     bcc:	f89d 8007 	ldrb.w	r8, [sp, #7]
     bd0:	f1b8 0f01 	cmp.w	r8, #1
     bd4:	d115      	bne.n	c02 <FIH_LABEL_FIH_CALL_START_2012>
    swap_type = boot_swap_type_multi(BOOT_CURR_IMG(state));
     bd6:	4610      	mov	r0, r2
     bd8:	f002 fcd8 	bl	358c <boot_swap_type_multi>
    if (BOOT_IS_UPGRADE(swap_type)) {
     bdc:	1e83      	subs	r3, r0, #2
     bde:	2b02      	cmp	r3, #2
    swap_type = boot_swap_type_multi(BOOT_CURR_IMG(state));
     be0:	4607      	mov	r7, r0
    if (BOOT_IS_UPGRADE(swap_type)) {
     be2:	d80b      	bhi.n	bfc <FIH_LABEL_FIH_CALL_END_1976+0x10>

00000be4 <FIH_LABEL_FIH_CALL_START_1961>:
        FIH_CALL(boot_validate_slot, fih_rc, state, BOOT_SECONDARY_SLOT, bs);
     be4:	4641      	mov	r1, r8
     be6:	4620      	mov	r0, r4
     be8:	f7ff fe5c 	bl	8a4 <boot_validate_slot.isra.0>

00000bec <FIH_LABEL_FIH_CALL_END_1976>:
        if (fih_not_eq(fih_rc, FIH_SUCCESS)) {
     bec:	4b42      	ldr	r3, [pc, #264]	; (cf8 <FIH_LABEL_FIH_CALL_END_2278+0x5a>)
     bee:	681b      	ldr	r3, [r3, #0]
     bf0:	4298      	cmp	r0, r3
     bf2:	d003      	beq.n	bfc <FIH_LABEL_FIH_CALL_END_1976+0x10>
                swap_type = BOOT_SWAP_TYPE_NONE;
     bf4:	2801      	cmp	r0, #1
     bf6:	bf14      	ite	ne
     bf8:	2705      	movne	r7, #5
     bfa:	2701      	moveq	r7, #1
                BOOT_SWAP_TYPE(state) = boot_validated_swap_type(state, bs);
     bfc:	f884 7058 	strb.w	r7, [r4, #88]	; 0x58
     c00:	e784      	b.n	b0c <context_boot_go+0x70>

00000c02 <FIH_LABEL_FIH_CALL_START_2012>:
                FIH_CALL(boot_validate_slot, fih_rc,
     c02:	2101      	movs	r1, #1
     c04:	4620      	mov	r0, r4
     c06:	f7ff fe4d 	bl	8a4 <boot_validate_slot.isra.0>

00000c0a <FIH_LABEL_FIH_CALL_END_2027>:
                if (fih_not_eq(fih_rc, FIH_SUCCESS)) {
     c0a:	4b3b      	ldr	r3, [pc, #236]	; (cf8 <FIH_LABEL_FIH_CALL_END_2278+0x5a>)
     c0c:	681b      	ldr	r3, [r3, #0]
     c0e:	4298      	cmp	r0, r3
                    BOOT_SWAP_TYPE(state) = bs->swap_type;
     c10:	bf0c      	ite	eq
     c12:	f89d 3007 	ldrbeq.w	r3, [sp, #7]
                    BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_FAIL;
     c16:	2305      	movne	r3, #5
        BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_NONE;
     c18:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
     c1c:	e776      	b.n	b0c <context_boot_go+0x70>
        switch (BOOT_SWAP_TYPE(state)) {
     c1e:	2b05      	cmp	r3, #5
     c20:	d180      	bne.n	b24 <context_boot_go+0x88>
            rc = swap_set_image_ok(BOOT_CURR_IMG(state));
     c22:	2000      	movs	r0, #0
     c24:	f005 faaf 	bl	6186 <swap_set_image_ok>
     c28:	e013      	b.n	c52 <FIH_LABEL_FIH_CALL_END_2027+0x48>
        rc = boot_swap_image(state, bs);
     c2a:	4669      	mov	r1, sp
     c2c:	4620      	mov	r0, r4
     c2e:	f7ff feb5 	bl	99c <boot_swap_image>
    swap_type = BOOT_SWAP_TYPE(state);
     c32:	f894 3058 	ldrb.w	r3, [r4, #88]	; 0x58
    if (swap_type == BOOT_SWAP_TYPE_REVERT ||
     c36:	1eda      	subs	r2, r3, #3
     c38:	2a01      	cmp	r2, #1
        rc = boot_swap_image(state, bs);
     c3a:	4605      	mov	r5, r0
    if (swap_type == BOOT_SWAP_TYPE_REVERT ||
     c3c:	d80c      	bhi.n	c58 <FIH_LABEL_FIH_CALL_END_2027+0x4e>
        rc = swap_set_image_ok(BOOT_CURR_IMG(state));
     c3e:	2000      	movs	r0, #0
     c40:	f005 faa1 	bl	6186 <swap_set_image_ok>
        if (rc != 0) {
     c44:	4605      	mov	r5, r0
     c46:	2800      	cmp	r0, #0
     c48:	f47f af6c 	bne.w	b24 <context_boot_go+0x88>
        rc = swap_set_copy_done(BOOT_CURR_IMG(state));
     c4c:	2000      	movs	r0, #0
     c4e:	f005 fa88 	bl	6162 <swap_set_copy_done>
            if (rc != 0) {
     c52:	4605      	mov	r5, r0
     c54:	b110      	cbz	r0, c5c <FIH_LABEL_FIH_CALL_END_2027+0x52>
     c56:	e765      	b.n	b24 <context_boot_go+0x88>
    if (BOOT_IS_UPGRADE(swap_type)) {
     c58:	2b02      	cmp	r3, #2
     c5a:	d0f7      	beq.n	c4c <FIH_LABEL_FIH_CALL_END_2027+0x42>
        }

        if (BOOT_SWAP_TYPE(state) == BOOT_SWAP_TYPE_PANIC) {
     c5c:	f894 3058 	ldrb.w	r3, [r4, #88]	; 0x58
     c60:	2bff      	cmp	r3, #255	; 0xff
     c62:	d104      	bne.n	c6e <FIH_LABEL_FIH_CALL_END_2027+0x64>
            BOOT_LOG_ERR("panic!");
     c64:	4823      	ldr	r0, [pc, #140]	; (cf4 <FIH_LABEL_FIH_CALL_END_2278+0x56>)
     c66:	2145      	movs	r1, #69	; 0x45
     c68:	f005 fc81 	bl	656e <z_log_minimal_printk>
            assert(0);

            /* Loop forever... */
            FIH_PANIC;
     c6c:	e7fe      	b.n	c6c <FIH_LABEL_FIH_CALL_END_2027+0x62>
#if BOOT_IMAGE_NUMBER > 1
        if (state->img_mask[BOOT_CURR_IMG(state)]) {
            continue;
        }
#endif
        if (BOOT_SWAP_TYPE(state) != BOOT_SWAP_TYPE_NONE) {
     c6e:	2b01      	cmp	r3, #1
     c70:	d010      	beq.n	c94 <FIH_LABEL_FIH_CALL_START_2263>
            /* Attempt to read an image header from each slot. Ensure that image
             * headers in slots are aligned with headers in boot_data.
             */
            rc = boot_read_image_headers(state, false, &bs);
     c72:	466a      	mov	r2, sp
     c74:	2100      	movs	r1, #0
     c76:	4620      	mov	r0, r4
     c78:	f005 f920 	bl	5ebc <boot_read_image_headers>
            if (rc != 0) {
     c7c:	4605      	mov	r5, r0
     c7e:	b148      	cbz	r0, c94 <FIH_LABEL_FIH_CALL_START_2263>
            flash_area_close(BOOT_IMG_AREA(state, BOOT_NUM_SLOTS - 1 - slot));
     c80:	6ce0      	ldr	r0, [r4, #76]	; 0x4c
     c82:	f005 fc81 	bl	6588 <flash_area_close>
     c86:	6a20      	ldr	r0, [r4, #32]
     c88:	f005 fc7e 	bl	6588 <flash_area_close>
    if (rc) {
        fih_rc = fih_int_encode(rc);
    }

    FIH_RET(fih_rc);
}
     c8c:	4628      	mov	r0, r5
     c8e:	b004      	add	sp, #16
     c90:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00000c94 <FIH_LABEL_FIH_CALL_START_2263>:
            FIH_CALL(boot_validate_slot, fih_rc, state, BOOT_PRIMARY_SLOT, NULL);
     c94:	2100      	movs	r1, #0
     c96:	4620      	mov	r0, r4
     c98:	f7ff fe04 	bl	8a4 <boot_validate_slot.isra.0>
     c9c:	4607      	mov	r7, r0

00000c9e <FIH_LABEL_FIH_CALL_END_2278>:
            if (fih_not_eq(fih_rc, FIH_SUCCESS)) {
     c9e:	f8df 8058 	ldr.w	r8, [pc, #88]	; cf8 <FIH_LABEL_FIH_CALL_END_2278+0x5a>
     ca2:	f8d8 3000 	ldr.w	r3, [r8]
     ca6:	4298      	cmp	r0, r3
     ca8:	d10f      	bne.n	cca <FIH_LABEL_FIH_CALL_END_2278+0x2c>
    memset(&bs, 0, sizeof(struct boot_status));
     caa:	2210      	movs	r2, #16
     cac:	2100      	movs	r1, #0
     cae:	4668      	mov	r0, sp
     cb0:	f005 fd1b 	bl	66ea <memset>
    rsp->br_flash_dev_id = flash_area_get_device_id(BOOT_IMG_AREA(state, active_slot));
     cb4:	6a20      	ldr	r0, [r4, #32]
     cb6:	f005 f802 	bl	5cbe <flash_area_get_device_id>
     cba:	7130      	strb	r0, [r6, #4]
	return (uint32_t)fa->fa_off;
     cbc:	6a23      	ldr	r3, [r4, #32]
    rsp->br_image_off = boot_img_slot_off(state, active_slot);
     cbe:	685b      	ldr	r3, [r3, #4]
    rsp->br_hdr = boot_img_hdr(state, active_slot);
     cc0:	6034      	str	r4, [r6, #0]
    fih_rc = FIH_SUCCESS;
     cc2:	f8d8 5000 	ldr.w	r5, [r8]
    rsp->br_image_off = boot_img_slot_off(state, active_slot);
     cc6:	60b3      	str	r3, [r6, #8]
    fih_rc = FIH_SUCCESS;
     cc8:	e7da      	b.n	c80 <FIH_LABEL_FIH_CALL_END_2027+0x76>
            flash_area_close(BOOT_IMG_AREA(state, BOOT_NUM_SLOTS - 1 - slot));
     cca:	6ce0      	ldr	r0, [r4, #76]	; 0x4c
     ccc:	f005 fc5c 	bl	6588 <flash_area_close>
     cd0:	6a20      	ldr	r0, [r4, #32]
     cd2:	f005 fc59 	bl	6588 <flash_area_close>
    if (rc) {
     cd6:	2d00      	cmp	r5, #0
     cd8:	bf08      	it	eq
     cda:	463d      	moveq	r5, r7
     cdc:	e7d6      	b.n	c8c <FIH_LABEL_FIH_CALL_END_2027+0x82>
     cde:	bf00      	nop
     ce0:	200005f4 	.word	0x200005f4
     ce4:	200001f4 	.word	0x200001f4
     ce8:	00007773 	.word	0x00007773
     cec:	00007731 	.word	0x00007731
     cf0:	0000779f 	.word	0x0000779f
     cf4:	000077c9 	.word	0x000077c9
     cf8:	200001f0 	.word	0x200001f0

00000cfc <boot_go>:
 *
 * @return                      FIH_SUCCESS on success; nonzero on failure.
 */
fih_int
boot_go(struct boot_rsp *rsp)
{
     cfc:	b538      	push	{r3, r4, r5, lr}
void boot_state_clear(struct boot_loader_state *state)
{
    if (state != NULL) {
        memset(state, 0, sizeof(struct boot_loader_state));
    } else {
        memset(&boot_data, 0, sizeof(struct boot_loader_state));
     cfe:	4d06      	ldr	r5, [pc, #24]	; (d18 <FIH_LABEL_FIH_CALL_END_2900+0x4>)
{
     d00:	4604      	mov	r4, r0
        memset(&boot_data, 0, sizeof(struct boot_loader_state));
     d02:	2260      	movs	r2, #96	; 0x60
     d04:	2100      	movs	r1, #0
     d06:	4628      	mov	r0, r5
     d08:	f005 fcef 	bl	66ea <memset>

00000d0c <FIH_LABEL_FIH_CALL_START_2886>:
    FIH_CALL(context_boot_go, fih_rc, &boot_data, rsp);
     d0c:	4621      	mov	r1, r4
     d0e:	4628      	mov	r0, r5
     d10:	f7ff fec4 	bl	a9c <context_boot_go>

00000d14 <FIH_LABEL_FIH_CALL_END_2900>:
}
     d14:	bd38      	pop	{r3, r4, r5, pc}
     d16:	bf00      	nop
     d18:	20000df4 	.word	0x20000df4

00000d1c <boot_read_image_header>:
static uint32_t g_last_idx = UINT32_MAX;

int
boot_read_image_header(struct boot_loader_state *state, int slot,
                       struct image_header *out_hdr, struct boot_status *bs)
{
     d1c:	b573      	push	{r0, r1, r4, r5, r6, lr}
     d1e:	4616      	mov	r6, r2
#if (BOOT_IMAGE_NUMBER == 1)
    (void)state;
#endif

    off = 0;
    if (bs) {
     d20:	461d      	mov	r5, r3
     d22:	b143      	cbz	r3, d36 <boot_read_image_header+0x1a>
        sz = boot_img_sector_size(state, BOOT_PRIMARY_SLOT, 0);
        if (bs->op == BOOT_STATUS_OP_MOVE) {
     d24:	795b      	ldrb	r3, [r3, #5]
     d26:	2b01      	cmp	r3, #1
     d28:	d107      	bne.n	d3a <boot_read_image_header+0x1e>
            if (slot == 0 && bs->idx > g_last_idx) {
     d2a:	b921      	cbnz	r1, d36 <boot_read_image_header+0x1a>
     d2c:	4b20      	ldr	r3, [pc, #128]	; (db0 <boot_read_image_header+0x94>)
     d2e:	682a      	ldr	r2, [r5, #0]
     d30:	681b      	ldr	r3, [r3, #0]
     d32:	429a      	cmp	r2, r3
     d34:	d817      	bhi.n	d66 <boot_read_image_header+0x4a>
    off = 0;
     d36:	2400      	movs	r4, #0
     d38:	e018      	b.n	d6c <boot_read_image_header+0x50>
                /* second sector */
                off = sz;
            }
        } else if (bs->op == BOOT_STATUS_OP_SWAP) {
     d3a:	2b02      	cmp	r3, #2
     d3c:	d1fb      	bne.n	d36 <boot_read_image_header+0x1a>
            if (bs->idx > 1 && bs->idx <= g_last_idx) {
     d3e:	682b      	ldr	r3, [r5, #0]
     d40:	2b01      	cmp	r3, #1
     d42:	d907      	bls.n	d54 <boot_read_image_header+0x38>
     d44:	4a1a      	ldr	r2, [pc, #104]	; (db0 <boot_read_image_header+0x94>)
     d46:	6812      	ldr	r2, [r2, #0]
     d48:	4293      	cmp	r3, r2
     d4a:	d8f4      	bhi.n	d36 <boot_read_image_header+0x1a>
                if (slot == 0) {
     d4c:	fab1 f181 	clz	r1, r1
     d50:	0949      	lsrs	r1, r1, #5
     d52:	e7f0      	b.n	d36 <boot_read_image_header+0x1a>
                    slot = 1;
                } else {
                    slot = 0;
                }
            } else if (bs->idx == 1) {
     d54:	d1ef      	bne.n	d36 <boot_read_image_header+0x1a>
                if (slot == 0) {
     d56:	b131      	cbz	r1, d66 <boot_read_image_header+0x4a>
                    off = sz;
                }
                if (slot == 1 && bs->state == 2) {
     d58:	2901      	cmp	r1, #1
     d5a:	d1ec      	bne.n	d36 <boot_read_image_header+0x1a>
     d5c:	7929      	ldrb	r1, [r5, #4]
     d5e:	3902      	subs	r1, #2
     d60:	bf18      	it	ne
     d62:	2101      	movne	r1, #1
     d64:	e7e7      	b.n	d36 <boot_read_image_header+0x1a>
}

static inline uint32_t flash_sector_get_size(const struct flash_sector *fs)
{
	return fs->fs_size;
     d66:	6a43      	ldr	r3, [r0, #36]	; 0x24
     d68:	685c      	ldr	r4, [r3, #4]
     d6a:	2100      	movs	r1, #0
                }
            }
        }
    }

    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
     d6c:	2000      	movs	r0, #0
     d6e:	f004 ff9d 	bl	5cac <flash_area_id_from_multi_image_slot>
    rc = flash_area_open(area_id, &fap);
     d72:	a901      	add	r1, sp, #4
     d74:	b2c0      	uxtb	r0, r0
     d76:	f000 fe39 	bl	19ec <flash_area_open>
    if (rc != 0) {
     d7a:	b130      	cbz	r0, d8a <boot_read_image_header+0x6e>
        rc = BOOT_EFLASH;
     d7c:	2401      	movs	r4, #1
    }

    rc = 0;

done:
    flash_area_close(fap);
     d7e:	9801      	ldr	r0, [sp, #4]
     d80:	f005 fc02 	bl	6588 <flash_area_close>
    return rc;
}
     d84:	4620      	mov	r0, r4
     d86:	b002      	add	sp, #8
     d88:	bd70      	pop	{r4, r5, r6, pc}
    rc = flash_area_read(fap, off, out_hdr, sizeof *out_hdr);
     d8a:	4621      	mov	r1, r4
     d8c:	9801      	ldr	r0, [sp, #4]
     d8e:	2320      	movs	r3, #32
     d90:	4632      	mov	r2, r6
     d92:	f005 fbfa 	bl	658a <flash_area_read>
    if (rc != 0) {
     d96:	4604      	mov	r4, r0
     d98:	2800      	cmp	r0, #0
     d9a:	d1ef      	bne.n	d7c <boot_read_image_header+0x60>
    if (bs != NULL && out_hdr->ih_magic != IMAGE_MAGIC) {
     d9c:	2d00      	cmp	r5, #0
     d9e:	d0ee      	beq.n	d7e <boot_read_image_header+0x62>
     da0:	6834      	ldr	r4, [r6, #0]
     da2:	4b04      	ldr	r3, [pc, #16]	; (db4 <boot_read_image_header+0x98>)
     da4:	1ae4      	subs	r4, r4, r3
     da6:	bf18      	it	ne
     da8:	f04f 34ff 	movne.w	r4, #4294967295
     dac:	e7e7      	b.n	d7e <boot_read_image_header+0x62>
     dae:	bf00      	nop
     db0:	20000004 	.word	0x20000004
     db4:	96f3b83d 	.word	0x96f3b83d

00000db8 <swap_read_status_bytes>:

int
swap_read_status_bytes(const struct flash_area *fap,
        struct boot_loader_state *state, struct boot_status *bs)
{
     db8:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     dbc:	4607      	mov	r7, r0
     dbe:	b085      	sub	sp, #20
     dc0:	460c      	mov	r4, r1
    int rc;
    int last_rc;
    int erased_sections;
    int i;

    max_entries = boot_status_entries(BOOT_CURR_IMG(state), fap);
     dc2:	4601      	mov	r1, r0
     dc4:	2000      	movs	r0, #0
{
     dc6:	4616      	mov	r6, r2
    max_entries = boot_status_entries(BOOT_CURR_IMG(state), fap);
     dc8:	f005 f849 	bl	5e5e <boot_status_entries>
    if (max_entries < 0) {
     dcc:	1e05      	subs	r5, r0, #0
     dce:	db50      	blt.n	e72 <swap_read_status_bytes+0xba>
    erased_sections = 0;
    found_idx = -1;
    /* skip erased sectors at the end */
    last_rc = 1;
    write_sz = BOOT_WRITE_SZ(state);
    off = boot_status_off(fap);
     dd0:	4638      	mov	r0, r7
    write_sz = BOOT_WRITE_SZ(state);
     dd2:	6de4      	ldr	r4, [r4, #92]	; 0x5c
    off = boot_status_off(fap);
     dd4:	f005 f850 	bl	5e78 <boot_status_off>
    for (i = max_entries; i > 0; i--) {
     dd8:	fa5f f984 	uxtb.w	r9, r4
     ddc:	1e6b      	subs	r3, r5, #1
     dde:	fb09 0803 	mla	r8, r9, r3, r0
    erased_sections = 0;
     de2:	f04f 0a00 	mov.w	sl, #0
    last_rc = 1;
     de6:	f04f 0b01 	mov.w	fp, #1
    found_idx = -1;
     dea:	f04f 34ff 	mov.w	r4, #4294967295
    for (i = max_entries; i > 0; i--) {
     dee:	b99d      	cbnz	r5, e18 <swap_read_status_bytes+0x60>
            }
        }
        last_rc = rc;
    }

    if (erased_sections > 1) {
     df0:	f1ba 0f01 	cmp.w	sl, #1
     df4:	dd03      	ble.n	dfe <swap_read_status_bytes+0x46>
        /* This means there was an error writing status on the last
         * swap. Tell user and move on to validation!
         */
#if !defined(__BOOTSIM__)
        BOOT_LOG_ERR("Detected inconsistent status!");
     df6:	4821      	ldr	r0, [pc, #132]	; (e7c <swap_read_status_bytes+0xc4>)
     df8:	2145      	movs	r1, #69	; 0x45
     dfa:	f005 fbb8 	bl	656e <z_log_minimal_printk>
        assert(0);
#endif
    }

    move_entries = BOOT_MAX_IMG_SECTORS * BOOT_STATUS_MOVE_STATE_COUNT;
    if (found_idx == -1) {
     dfe:	1c63      	adds	r3, r4, #1
     e00:	d006      	beq.n	e10 <swap_read_status_bytes+0x58>
        /* no swap status found; nothing to do */
    } else if (found_idx < move_entries) {
     e02:	2c7f      	cmp	r4, #127	; 0x7f
     e04:	dc2a      	bgt.n	e5c <swap_read_status_bytes+0xa4>
        bs->op = BOOT_STATUS_OP_MOVE;
        bs->idx = (found_idx  / BOOT_STATUS_MOVE_STATE_COUNT) + BOOT_STATUS_IDX_0;
     e06:	3401      	adds	r4, #1
        bs->state = (found_idx % BOOT_STATUS_MOVE_STATE_COUNT) + BOOT_STATUS_STATE_0;;
     e08:	f240 1301 	movw	r3, #257	; 0x101
        bs->idx = (found_idx  / BOOT_STATUS_MOVE_STATE_COUNT) + BOOT_STATUS_IDX_0;
     e0c:	6034      	str	r4, [r6, #0]
        bs->state = (found_idx % BOOT_STATUS_MOVE_STATE_COUNT) + BOOT_STATUS_STATE_0;;
     e0e:	80b3      	strh	r3, [r6, #4]
        bs->idx = ((found_idx - move_entries) / BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_IDX_0;
        bs->state = ((found_idx - move_entries) % BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_STATE_0;
    }

    return 0;
}
     e10:	4628      	mov	r0, r5
     e12:	b005      	add	sp, #20
     e14:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
        rc = flash_area_read(fap, off + (i - 1) * write_sz, &status, 1);
     e18:	1e6b      	subs	r3, r5, #1
     e1a:	9300      	str	r3, [sp, #0]
     e1c:	f10d 020f 	add.w	r2, sp, #15
     e20:	2301      	movs	r3, #1
     e22:	4641      	mov	r1, r8
     e24:	4638      	mov	r0, r7
     e26:	f005 fbb0 	bl	658a <flash_area_read>
        if (rc < 0) {
     e2a:	1e03      	subs	r3, r0, #0
     e2c:	9301      	str	r3, [sp, #4]
     e2e:	db22      	blt.n	e76 <swap_read_status_bytes+0xbe>
        if (bootutil_buffer_is_erased(fap, &status, 1)) {
     e30:	2201      	movs	r2, #1
     e32:	f10d 010f 	add.w	r1, sp, #15
     e36:	4638      	mov	r0, r7
     e38:	f005 febd 	bl	6bb6 <bootutil_buffer_is_erased>
     e3c:	9b01      	ldr	r3, [sp, #4]
     e3e:	b140      	cbz	r0, e52 <swap_read_status_bytes+0x9a>
            if (rc != last_rc) {
     e40:	455b      	cmp	r3, fp
     e42:	d001      	beq.n	e48 <swap_read_status_bytes+0x90>
                erased_sections++;
     e44:	f10a 0a01 	add.w	sl, sl, #1
            if (found_idx == -1) {
     e48:	9d00      	ldr	r5, [sp, #0]
     e4a:	eba8 0809 	sub.w	r8, r8, r9
     e4e:	469b      	mov	fp, r3
     e50:	e7cd      	b.n	dee <swap_read_status_bytes+0x36>
     e52:	f1b4 3fff 	cmp.w	r4, #4294967295
     e56:	bf08      	it	eq
     e58:	462c      	moveq	r4, r5
     e5a:	e7f5      	b.n	e48 <swap_read_status_bytes+0x90>
        bs->op = BOOT_STATUS_OP_SWAP;
     e5c:	2302      	movs	r3, #2
        bs->idx = ((found_idx - move_entries) / BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_IDX_0;
     e5e:	3c80      	subs	r4, #128	; 0x80
        bs->op = BOOT_STATUS_OP_SWAP;
     e60:	7173      	strb	r3, [r6, #5]
        bs->idx = ((found_idx - move_entries) / BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_IDX_0;
     e62:	1063      	asrs	r3, r4, #1
        bs->state = ((found_idx - move_entries) % BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_STATE_0;
     e64:	f004 0401 	and.w	r4, r4, #1
        bs->idx = ((found_idx - move_entries) / BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_IDX_0;
     e68:	3301      	adds	r3, #1
        bs->state = ((found_idx - move_entries) % BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_STATE_0;
     e6a:	3401      	adds	r4, #1
        bs->idx = ((found_idx - move_entries) / BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_IDX_0;
     e6c:	6033      	str	r3, [r6, #0]
        bs->state = ((found_idx - move_entries) % BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_STATE_0;
     e6e:	7134      	strb	r4, [r6, #4]
     e70:	e7ce      	b.n	e10 <swap_read_status_bytes+0x58>
        return BOOT_EBADARGS;
     e72:	2507      	movs	r5, #7
     e74:	e7cc      	b.n	e10 <swap_read_status_bytes+0x58>
            return BOOT_EFLASH;
     e76:	2501      	movs	r5, #1
     e78:	e7ca      	b.n	e10 <swap_read_status_bytes+0x58>
     e7a:	bf00      	nop
     e7c:	000077d5 	.word	0x000077d5

00000e80 <boot_slots_compatible>:
    return off;
}

int
boot_slots_compatible(struct boot_loader_state *state)
{
     e80:	b538      	push	{r3, r4, r5, lr}
}

static inline size_t
boot_img_num_sectors(const struct boot_loader_state *state, size_t slot)
{
    return BOOT_IMG(state, slot).num_sectors;
     e82:	6a81      	ldr	r1, [r0, #40]	; 0x28
     e84:	6d42      	ldr	r2, [r0, #84]	; 0x54
    size_t sector_sz_sec = 0;
    size_t i;

    num_sectors_pri = boot_img_num_sectors(state, BOOT_PRIMARY_SLOT);
    num_sectors_sec = boot_img_num_sectors(state, BOOT_SECONDARY_SLOT);
    if ((num_sectors_pri != num_sectors_sec) &&
     e86:	4291      	cmp	r1, r2
     e88:	d008      	beq.n	e9c <boot_slots_compatible+0x1c>
            (num_sectors_pri != (num_sectors_sec + 1))) {
     e8a:	1c53      	adds	r3, r2, #1
    if ((num_sectors_pri != num_sectors_sec) &&
     e8c:	428b      	cmp	r3, r1
     e8e:	d005      	beq.n	e9c <boot_slots_compatible+0x1c>
        BOOT_LOG_WRN("Cannot upgrade: not a compatible amount of sectors");
     e90:	4813      	ldr	r0, [pc, #76]	; (ee0 <boot_slots_compatible+0x60>)
     e92:	2157      	movs	r1, #87	; 0x57
        return 0;
    }

    if (num_sectors_pri > BOOT_MAX_IMG_SECTORS) {
        BOOT_LOG_WRN("Cannot upgrade: more sectors than allowed");
     e94:	f005 fb6b 	bl	656e <z_log_minimal_printk>
        return 0;
     e98:	2000      	movs	r0, #0
        }
    }

    return 1;
#endif /* PM_S1_ADDRESS */
}
     e9a:	bd38      	pop	{r3, r4, r5, pc}
    if (num_sectors_pri > BOOT_MAX_IMG_SECTORS) {
     e9c:	2980      	cmp	r1, #128	; 0x80
     e9e:	d91c      	bls.n	eda <boot_slots_compatible+0x5a>
        BOOT_LOG_WRN("Cannot upgrade: more sectors than allowed");
     ea0:	4810      	ldr	r0, [pc, #64]	; (ee4 <boot_slots_compatible+0x64>)
     ea2:	2157      	movs	r1, #87	; 0x57
     ea4:	e7f6      	b.n	e94 <boot_slots_compatible+0x14>
     ea6:	6a44      	ldr	r4, [r0, #36]	; 0x24
     ea8:	6d05      	ldr	r5, [r0, #80]	; 0x50
     eaa:	eb04 04c3 	add.w	r4, r4, r3, lsl #3
     eae:	eb05 05c3 	add.w	r5, r5, r3, lsl #3
     eb2:	6864      	ldr	r4, [r4, #4]
        if (sector_sz_pri != sector_sz_sec) {
     eb4:	686d      	ldr	r5, [r5, #4]
     eb6:	42ac      	cmp	r4, r5
     eb8:	d002      	beq.n	ec0 <boot_slots_compatible+0x40>
            BOOT_LOG_WRN("Cannot upgrade: not same sector layout");
     eba:	480b      	ldr	r0, [pc, #44]	; (ee8 <boot_slots_compatible+0x68>)
     ebc:	2157      	movs	r1, #87	; 0x57
     ebe:	e7e9      	b.n	e94 <boot_slots_compatible+0x14>
    for (i = 0; i < num_sectors_sec; i++) {
     ec0:	3301      	adds	r3, #1
     ec2:	429a      	cmp	r2, r3
     ec4:	d1ef      	bne.n	ea6 <boot_slots_compatible+0x26>
    if (num_sectors_pri > num_sectors_sec) {
     ec6:	4291      	cmp	r1, r2
     ec8:	d905      	bls.n	ed6 <boot_slots_compatible+0x56>
     eca:	6a43      	ldr	r3, [r0, #36]	; 0x24
     ecc:	eb03 03c2 	add.w	r3, r3, r2, lsl #3
        if (sector_sz_pri != boot_img_sector_size(state, BOOT_PRIMARY_SLOT, i)) {
     ed0:	685b      	ldr	r3, [r3, #4]
     ed2:	42a3      	cmp	r3, r4
     ed4:	d1f1      	bne.n	eba <boot_slots_compatible+0x3a>
    return 1;
     ed6:	2001      	movs	r0, #1
     ed8:	e7df      	b.n	e9a <boot_slots_compatible+0x1a>
    for (i = 0; i < num_sectors_sec; i++) {
     eda:	2300      	movs	r3, #0
    size_t sector_sz_pri = 0;
     edc:	461c      	mov	r4, r3
     ede:	e7f0      	b.n	ec2 <boot_slots_compatible+0x42>
     ee0:	000077f8 	.word	0x000077f8
     ee4:	00007830 	.word	0x00007830
     ee8:	0000785f 	.word	0x0000785f

00000eec <swap_status_source>:
                 (state)->copy_done,                                \
                 (state)->image_ok)

int
swap_status_source(struct boot_loader_state *state)
{
     eec:	b500      	push	{lr}
     eee:	b089      	sub	sp, #36	; 0x24
    (void)state;
#endif

    image_index = BOOT_CURR_IMG(state);

    rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_PRIMARY(image_index),
     ef0:	a904      	add	r1, sp, #16
     ef2:	2002      	movs	r0, #2
     ef4:	f005 fed1 	bl	6c9a <boot_read_swap_state_by_id>
            &state_primary_slot);
    assert(rc == 0);

    BOOT_LOG_SWAP_STATE("Primary image", &state_primary_slot);
     ef8:	f89d 2010 	ldrb.w	r2, [sp, #16]
     efc:	2a01      	cmp	r2, #1
     efe:	d041      	beq.n	f84 <swap_status_source+0x98>
     f00:	4b25      	ldr	r3, [pc, #148]	; (f98 <swap_status_source+0xac>)
     f02:	4926      	ldr	r1, [pc, #152]	; (f9c <swap_status_source+0xb0>)
     f04:	2a03      	cmp	r2, #3
     f06:	bf08      	it	eq
     f08:	460b      	moveq	r3, r1
     f0a:	f89d 2013 	ldrb.w	r2, [sp, #19]
     f0e:	9202      	str	r2, [sp, #8]
     f10:	f89d 2012 	ldrb.w	r2, [sp, #18]
     f14:	9201      	str	r2, [sp, #4]
     f16:	f89d 2011 	ldrb.w	r2, [sp, #17]
     f1a:	4821      	ldr	r0, [pc, #132]	; (fa0 <swap_status_source+0xb4>)
     f1c:	9200      	str	r2, [sp, #0]
     f1e:	2149      	movs	r1, #73	; 0x49
     f20:	4a20      	ldr	r2, [pc, #128]	; (fa4 <swap_status_source+0xb8>)
     f22:	f005 fb24 	bl	656e <z_log_minimal_printk>

    rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_SECONDARY(image_index),
     f26:	a906      	add	r1, sp, #24
     f28:	2005      	movs	r0, #5
     f2a:	f005 feb6 	bl	6c9a <boot_read_swap_state_by_id>
            &state_secondary_slot);
    assert(rc == 0);

    BOOT_LOG_SWAP_STATE("Secondary image", &state_secondary_slot);
     f2e:	f89d 2018 	ldrb.w	r2, [sp, #24]
     f32:	2a01      	cmp	r2, #1
     f34:	d028      	beq.n	f88 <swap_status_source+0x9c>
     f36:	4b18      	ldr	r3, [pc, #96]	; (f98 <swap_status_source+0xac>)
     f38:	4918      	ldr	r1, [pc, #96]	; (f9c <swap_status_source+0xb0>)
     f3a:	2a03      	cmp	r2, #3
     f3c:	bf08      	it	eq
     f3e:	460b      	moveq	r3, r1
     f40:	f89d 201b 	ldrb.w	r2, [sp, #27]
     f44:	9202      	str	r2, [sp, #8]
     f46:	f89d 201a 	ldrb.w	r2, [sp, #26]
     f4a:	9201      	str	r2, [sp, #4]
     f4c:	f89d 2019 	ldrb.w	r2, [sp, #25]
     f50:	9200      	str	r2, [sp, #0]
     f52:	4813      	ldr	r0, [pc, #76]	; (fa0 <swap_status_source+0xb4>)
     f54:	4a14      	ldr	r2, [pc, #80]	; (fa8 <swap_status_source+0xbc>)
     f56:	2149      	movs	r1, #73	; 0x49
     f58:	f005 fb09 	bl	656e <z_log_minimal_printk>

    if (state_primary_slot.magic == BOOT_MAGIC_GOOD &&
     f5c:	f89d 3010 	ldrb.w	r3, [sp, #16]
     f60:	2b01      	cmp	r3, #1
     f62:	d113      	bne.n	f8c <swap_status_source+0xa0>
     f64:	f89d 3012 	ldrb.w	r3, [sp, #18]
     f68:	2b03      	cmp	r3, #3
     f6a:	d10f      	bne.n	f8c <swap_status_source+0xa0>
            state_primary_slot.copy_done == BOOT_FLAG_UNSET &&
     f6c:	f89d 3018 	ldrb.w	r3, [sp, #24]
     f70:	2b01      	cmp	r3, #1
     f72:	d00b      	beq.n	f8c <swap_status_source+0xa0>
            state_secondary_slot.magic != BOOT_MAGIC_GOOD) {

        source = BOOT_STATUS_SOURCE_PRIMARY_SLOT;

        BOOT_LOG_INF("Boot source: primary slot");
     f74:	480d      	ldr	r0, [pc, #52]	; (fac <swap_status_source+0xc0>)
     f76:	2149      	movs	r1, #73	; 0x49
     f78:	f005 faf9 	bl	656e <z_log_minimal_printk>
        return source;
     f7c:	2002      	movs	r0, #2
    }

    BOOT_LOG_INF("Boot source: none");
    return BOOT_STATUS_SOURCE_NONE;
}
     f7e:	b009      	add	sp, #36	; 0x24
     f80:	f85d fb04 	ldr.w	pc, [sp], #4
    BOOT_LOG_SWAP_STATE("Primary image", &state_primary_slot);
     f84:	4b0a      	ldr	r3, [pc, #40]	; (fb0 <swap_status_source+0xc4>)
     f86:	e7c0      	b.n	f0a <swap_status_source+0x1e>
    BOOT_LOG_SWAP_STATE("Secondary image", &state_secondary_slot);
     f88:	4b09      	ldr	r3, [pc, #36]	; (fb0 <swap_status_source+0xc4>)
     f8a:	e7d9      	b.n	f40 <swap_status_source+0x54>
    BOOT_LOG_INF("Boot source: none");
     f8c:	4809      	ldr	r0, [pc, #36]	; (fb4 <swap_status_source+0xc8>)
     f8e:	2149      	movs	r1, #73	; 0x49
     f90:	f005 faed 	bl	656e <z_log_minimal_printk>
    return BOOT_STATUS_SOURCE_NONE;
     f94:	2000      	movs	r0, #0
     f96:	e7f2      	b.n	f7e <swap_status_source+0x92>
     f98:	0000788b 	.word	0x0000788b
     f9c:	00007894 	.word	0x00007894
     fa0:	000078a8 	.word	0x000078a8
     fa4:	0000789a 	.word	0x0000789a
     fa8:	000078e9 	.word	0x000078e9
     fac:	000078f9 	.word	0x000078f9
     fb0:	0000788f 	.word	0x0000788f
     fb4:	00007918 	.word	0x00007918

00000fb8 <fixup_revert>:
 * upgrade (by initializing the secondary slot).
 */
void
fixup_revert(const struct boot_loader_state *state, struct boot_status *bs,
        const struct flash_area *fap_sec)
{
     fb8:	b570      	push	{r4, r5, r6, lr}
#if (BOOT_IMAGE_NUMBER == 1)
    (void)state;
#endif

    /* No fixup required */
    if (bs->swap_type != BOOT_SWAP_TYPE_REVERT ||
     fba:	684b      	ldr	r3, [r1, #4]
{
     fbc:	4614      	mov	r4, r2
    if (bs->swap_type != BOOT_SWAP_TYPE_REVERT ||
     fbe:	4a1e      	ldr	r2, [pc, #120]	; (1038 <CONFIG_FPROTECT_BLOCK_SIZE+0x38>)
     fc0:	f003 23ff 	and.w	r3, r3, #4278255360	; 0xff00ff00
     fc4:	4293      	cmp	r3, r2
{
     fc6:	b086      	sub	sp, #24
     fc8:	4606      	mov	r6, r0
     fca:	460d      	mov	r5, r1
    if (bs->swap_type != BOOT_SWAP_TYPE_REVERT ||
     fcc:	d12f      	bne.n	102e <CONFIG_FPROTECT_BLOCK_SIZE+0x2e>
        bs->op != BOOT_STATUS_OP_MOVE ||
     fce:	680b      	ldr	r3, [r1, #0]
     fd0:	2b01      	cmp	r3, #1
     fd2:	d12c      	bne.n	102e <CONFIG_FPROTECT_BLOCK_SIZE+0x2e>
        bs->idx != BOOT_STATUS_IDX_0) {
        return;
    }

    rc = boot_read_swap_state(fap_sec, &swap_state);
     fd4:	a904      	add	r1, sp, #16
     fd6:	4620      	mov	r0, r4
     fd8:	f002 fa82 	bl	34e0 <boot_read_swap_state>
    assert(rc == 0);

    BOOT_LOG_SWAP_STATE("Secondary image", &swap_state);
     fdc:	f89d 2010 	ldrb.w	r2, [sp, #16]
     fe0:	2a01      	cmp	r2, #1
     fe2:	d026      	beq.n	1032 <CONFIG_FPROTECT_BLOCK_SIZE+0x32>
     fe4:	4b15      	ldr	r3, [pc, #84]	; (103c <CONFIG_FPROTECT_BLOCK_SIZE+0x3c>)
     fe6:	4916      	ldr	r1, [pc, #88]	; (1040 <CONFIG_FPROTECT_BLOCK_SIZE+0x40>)
     fe8:	2a03      	cmp	r2, #3
     fea:	bf08      	it	eq
     fec:	460b      	moveq	r3, r1
     fee:	f89d 2013 	ldrb.w	r2, [sp, #19]
     ff2:	9202      	str	r2, [sp, #8]
     ff4:	f89d 2012 	ldrb.w	r2, [sp, #18]
     ff8:	9201      	str	r2, [sp, #4]
     ffa:	f89d 2011 	ldrb.w	r2, [sp, #17]
     ffe:	9200      	str	r2, [sp, #0]
    1000:	4810      	ldr	r0, [pc, #64]	; (1044 <CONFIG_FPROTECT_BLOCK_SIZE+0x44>)
    1002:	4a11      	ldr	r2, [pc, #68]	; (1048 <CONFIG_FPROTECT_BLOCK_SIZE+0x48>)
    1004:	2149      	movs	r1, #73	; 0x49
    1006:	f005 fab2 	bl	656e <z_log_minimal_printk>

    if (swap_state.magic == BOOT_MAGIC_UNSET) {
    100a:	f89d 3010 	ldrb.w	r3, [sp, #16]
    100e:	2b03      	cmp	r3, #3
    1010:	d10d      	bne.n	102e <CONFIG_FPROTECT_BLOCK_SIZE+0x2e>
        rc = swap_erase_trailer_sectors(state, fap_sec);
    1012:	4621      	mov	r1, r4
    1014:	4630      	mov	r0, r6
    1016:	f005 f813 	bl	6040 <swap_erase_trailer_sectors>
        assert(rc == 0);

        rc = boot_write_image_ok(fap_sec);
    101a:	4620      	mov	r0, r4
    101c:	f005 fe30 	bl	6c80 <boot_write_image_ok>
        assert(rc == 0);

        rc = boot_write_swap_size(fap_sec, bs->swap_size);
    1020:	68a9      	ldr	r1, [r5, #8]
    1022:	4620      	mov	r0, r4
    1024:	f004 ff3b 	bl	5e9e <boot_write_swap_size>
        assert(rc == 0);

        rc = boot_write_magic(fap_sec);
    1028:	4620      	mov	r0, r4
    102a:	f002 fa39 	bl	34a0 <boot_write_magic>
        assert(rc == 0);
    }
}
    102e:	b006      	add	sp, #24
    1030:	bd70      	pop	{r4, r5, r6, pc}
    BOOT_LOG_SWAP_STATE("Secondary image", &swap_state);
    1032:	4b06      	ldr	r3, [pc, #24]	; (104c <CONFIG_FPROTECT_BLOCK_SIZE+0x4c>)
    1034:	e7db      	b.n	fee <fixup_revert+0x36>
    1036:	bf00      	nop
    1038:	04000100 	.word	0x04000100
    103c:	0000788b 	.word	0x0000788b
    1040:	00007894 	.word	0x00007894
    1044:	000078a8 	.word	0x000078a8
    1048:	000078e9 	.word	0x000078e9
    104c:	0000788f 	.word	0x0000788f

00001050 <swap_run>:

void
swap_run(struct boot_loader_state *state, struct boot_status *bs,
         uint32_t copy_size)
{
    1050:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    1054:	4605      	mov	r5, r0
    1056:	b089      	sub	sp, #36	; 0x24
    uint8_t image_index;
    const struct flash_area *fap_pri;
    const struct flash_area *fap_sec;
    int rc;

    BOOT_LOG_INF("Starting swap using move algorithm.");
    1058:	487d      	ldr	r0, [pc, #500]	; (1250 <swap_run+0x200>)
{
    105a:	460c      	mov	r4, r1
    BOOT_LOG_INF("Starting swap using move algorithm.");
    105c:	2149      	movs	r1, #73	; 0x49
{
    105e:	4617      	mov	r7, r2
    BOOT_LOG_INF("Starting swap using move algorithm.");
    1060:	f005 fa85 	bl	656e <z_log_minimal_printk>
    1064:	6a6b      	ldr	r3, [r5, #36]	; 0x24
    1066:	2201      	movs	r2, #1
    1068:	685e      	ldr	r6, [r3, #4]

    sz = 0;
    106a:	2300      	movs	r3, #0
    g_last_idx = 0;

    sector_sz = boot_img_sector_size(state, BOOT_PRIMARY_SLOT, 0);
    while (1) {
        sz += sector_sz;
    106c:	4433      	add	r3, r6
        /* Skip to next sector because all sectors will be moved up. */
        g_last_idx++;
        if (sz >= copy_size) {
    106e:	42bb      	cmp	r3, r7
    1070:	4611      	mov	r1, r2
    1072:	f102 0201 	add.w	r2, r2, #1
    1076:	d3f9      	bcc.n	106c <swap_run+0x1c>
    1078:	4f76      	ldr	r7, [pc, #472]	; (1254 <swap_run+0x204>)
    }

    /*
     * When starting a new swap upgrade, check that there is enough space.
     */
    if (boot_status_is_reset(bs)) {
    107a:	4620      	mov	r0, r4
    107c:	6039      	str	r1, [r7, #0]
    107e:	f004 ff9e 	bl	5fbe <boot_status_is_reset>
    1082:	b308      	cbz	r0, 10c8 <swap_run+0x78>
        sz = 0;
        trailer_sz = boot_trailer_sz(BOOT_WRITE_SZ(state));
    1084:	6de8      	ldr	r0, [r5, #92]	; 0x5c
    1086:	f004 fee5 	bl	5e54 <boot_trailer_sz>
        first_trailer_idx = boot_img_num_sectors(state, BOOT_PRIMARY_SLOT) - 1;
    108a:	6aab      	ldr	r3, [r5, #40]	; 0x28
    108c:	f103 38ff 	add.w	r8, r3, #4294967295
        sz = 0;
    1090:	2300      	movs	r3, #0

        while (1) {
            sz += sector_sz;
    1092:	4433      	add	r3, r6
            if  (sz >= trailer_sz) {
    1094:	4283      	cmp	r3, r0
    1096:	d202      	bcs.n	109e <swap_run+0x4e>
                break;
            }
            first_trailer_idx--;
    1098:	f108 38ff 	add.w	r8, r8, #4294967295
            sz += sector_sz;
    109c:	e7f9      	b.n	1092 <swap_run+0x42>
        }

        if (g_last_idx >= first_trailer_idx) {
    109e:	683b      	ldr	r3, [r7, #0]
    10a0:	4543      	cmp	r3, r8
    10a2:	d311      	bcc.n	10c8 <swap_run+0x78>
            BOOT_LOG_WRN("Not enough free space to run swap upgrade");
    10a4:	486c      	ldr	r0, [pc, #432]	; (1258 <swap_run+0x208>)
    10a6:	2157      	movs	r1, #87	; 0x57
    10a8:	f005 fa61 	bl	656e <z_log_minimal_printk>
            BOOT_LOG_WRN("required %d bytes but only %d are available",
    10ac:	683a      	ldr	r2, [r7, #0]
    10ae:	486b      	ldr	r0, [pc, #428]	; (125c <swap_run+0x20c>)
    10b0:	fb08 f306 	mul.w	r3, r8, r6
    10b4:	fb02 6206 	mla	r2, r2, r6, r6
    10b8:	2157      	movs	r1, #87	; 0x57
    10ba:	f005 fa58 	bl	656e <z_log_minimal_printk>
                         (g_last_idx + 1) * sector_sz ,
                         first_trailer_idx * sector_sz);
            bs->swap_type = BOOT_SWAP_TYPE_NONE;
    10be:	2301      	movs	r3, #1
    10c0:	71e3      	strb	r3, [r4, #7]
        idx++;
    }

    flash_area_close(fap_pri);
    flash_area_close(fap_sec);
}
    10c2:	b009      	add	sp, #36	; 0x24
    10c4:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    rc = flash_area_open(FLASH_AREA_IMAGE_PRIMARY(image_index), &fap_pri);
    10c8:	a906      	add	r1, sp, #24
    10ca:	2002      	movs	r0, #2
    10cc:	f000 fc8e 	bl	19ec <flash_area_open>
    rc = flash_area_open(FLASH_AREA_IMAGE_SECONDARY(image_index), &fap_sec);
    10d0:	a907      	add	r1, sp, #28
    10d2:	2005      	movs	r0, #5
    10d4:	f000 fc8a 	bl	19ec <flash_area_open>
    fixup_revert(state, bs, fap_sec);
    10d8:	9a07      	ldr	r2, [sp, #28]
    10da:	4621      	mov	r1, r4
    10dc:	4628      	mov	r0, r5
    10de:	f7ff ff6b 	bl	fb8 <fixup_revert>
    if (bs->op == BOOT_STATUS_OP_MOVE) {
    10e2:	7963      	ldrb	r3, [r4, #5]
    10e4:	2b01      	cmp	r3, #1
    10e6:	d10b      	bne.n	1100 <swap_run+0xb0>
        idx = g_last_idx;
    10e8:	f8d7 8000 	ldr.w	r8, [r7]
    BOOT_STATUS_ASSERT(rc == 0);
    10ec:	f8df b170 	ldr.w	fp, [pc, #368]	; 1260 <swap_run+0x210>
            if (idx <= (g_last_idx - bs->idx + 1)) {
    10f0:	683b      	ldr	r3, [r7, #0]
                boot_move_sector_up(idx, sector_sz, state, bs, fap_pri, fap_sec);
    10f2:	f8dd 9018 	ldr.w	r9, [sp, #24]
        while (idx > 0) {
    10f6:	f1b8 0f00 	cmp.w	r8, #0
    10fa:	d111      	bne.n	1120 <swap_run+0xd0>
        bs->idx = BOOT_STATUS_IDX_0;
    10fc:	2301      	movs	r3, #1
    10fe:	6023      	str	r3, [r4, #0]
    bs->op = BOOT_STATUS_OP_SWAP;
    1100:	2302      	movs	r3, #2
    1102:	7163      	strb	r3, [r4, #5]
    idx = 1;
    1104:	f04f 0801 	mov.w	r8, #1
    while (idx <= g_last_idx) {
    1108:	683b      	ldr	r3, [r7, #0]
            boot_swap_sectors(idx, sector_sz, state, bs, fap_pri, fap_sec);
    110a:	f8dd a018 	ldr.w	sl, [sp, #24]
    while (idx <= g_last_idx) {
    110e:	4598      	cmp	r8, r3
    1110:	d949      	bls.n	11a6 <swap_run+0x156>
    flash_area_close(fap_pri);
    1112:	4650      	mov	r0, sl
    1114:	f005 fa38 	bl	6588 <flash_area_close>
    flash_area_close(fap_sec);
    1118:	9807      	ldr	r0, [sp, #28]
    111a:	f005 fa35 	bl	6588 <flash_area_close>
    111e:	e7d0      	b.n	10c2 <swap_run+0x72>
            if (idx <= (g_last_idx - bs->idx + 1)) {
    1120:	6822      	ldr	r2, [r4, #0]
    1122:	3301      	adds	r3, #1
    1124:	1a9b      	subs	r3, r3, r2
    1126:	4598      	cmp	r8, r3
    1128:	d83a      	bhi.n	11a0 <swap_run+0x150>

static inline uint32_t
boot_img_sector_off(const struct boot_loader_state *state, size_t slot,
                    size_t sector)
{
    return flash_sector_get_off(&BOOT_IMG(state, slot).sectors[sector]) -
    112a:	6a6b      	ldr	r3, [r5, #36]	; 0x24
	return fs->fs_off;
    112c:	6819      	ldr	r1, [r3, #0]
    112e:	f853 0038 	ldr.w	r0, [r3, r8, lsl #3]
    1132:	eb03 03c8 	add.w	r3, r3, r8, lsl #3
    if (bs->idx == BOOT_STATUS_IDX_0) {
    1136:	2a01      	cmp	r2, #1
    1138:	f853 3c08 	ldr.w	r3, [r3, #-8]
    113c:	eba3 0301 	sub.w	r3, r3, r1
    1140:	eba0 0a01 	sub.w	sl, r0, r1
    1144:	9304      	str	r3, [sp, #16]
    1146:	d111      	bne.n	116c <swap_run+0x11c>
                boot_move_sector_up(idx, sector_sz, state, bs, fap_pri, fap_sec);
    1148:	9b07      	ldr	r3, [sp, #28]
    114a:	9303      	str	r3, [sp, #12]
        if (bs->source != BOOT_STATUS_SOURCE_PRIMARY_SLOT) {
    114c:	68e3      	ldr	r3, [r4, #12]
    114e:	2b02      	cmp	r3, #2
    1150:	d008      	beq.n	1164 <swap_run+0x114>
            rc = swap_erase_trailer_sectors(state, fap_pri);
    1152:	4649      	mov	r1, r9
    1154:	4628      	mov	r0, r5
    1156:	f004 ff73 	bl	6040 <swap_erase_trailer_sectors>
            rc = swap_status_init(state, fap_pri, bs);
    115a:	4622      	mov	r2, r4
    115c:	4649      	mov	r1, r9
    115e:	4628      	mov	r0, r5
    1160:	f004 ffa4 	bl	60ac <swap_status_init>
        rc = swap_erase_trailer_sectors(state, fap_sec);
    1164:	9903      	ldr	r1, [sp, #12]
    1166:	4628      	mov	r0, r5
    1168:	f004 ff6a 	bl	6040 <swap_erase_trailer_sectors>
    rc = boot_erase_region(fap_pri, new_off, sz);
    116c:	4632      	mov	r2, r6
    116e:	4651      	mov	r1, sl
    1170:	4648      	mov	r0, r9
    1172:	f004 ff63 	bl	603c <boot_erase_region>
    rc = boot_copy_region(state, fap_pri, fap_pri, old_off, new_off, sz);
    1176:	9b04      	ldr	r3, [sp, #16]
    1178:	464a      	mov	r2, r9
    117a:	4649      	mov	r1, r9
    117c:	e9cd a600 	strd	sl, r6, [sp]
    1180:	4628      	mov	r0, r5
    1182:	f7ff fc49 	bl	a18 <boot_copy_region>
    rc = boot_write_status(state, bs);
    1186:	4621      	mov	r1, r4
    1188:	4628      	mov	r0, r5
    118a:	f004 ff25 	bl	5fd8 <boot_write_status>
    bs->idx++;
    118e:	6823      	ldr	r3, [r4, #0]
    1190:	3301      	adds	r3, #1
    1192:	6023      	str	r3, [r4, #0]
    BOOT_STATUS_ASSERT(rc == 0);
    1194:	b120      	cbz	r0, 11a0 <swap_run+0x150>
    1196:	f8db 3000 	ldr.w	r3, [fp]
    119a:	3301      	adds	r3, #1
    119c:	f8cb 3000 	str.w	r3, [fp]
            idx--;
    11a0:	f108 38ff 	add.w	r8, r8, #4294967295
    11a4:	e7a4      	b.n	10f0 <swap_run+0xa0>
        if (idx >= bs->idx) {
    11a6:	6823      	ldr	r3, [r4, #0]
    11a8:	4598      	cmp	r8, r3
    11aa:	d34e      	bcc.n	124a <swap_run+0x1fa>
    11ac:	6a6a      	ldr	r2, [r5, #36]	; 0x24
            boot_swap_sectors(idx, sector_sz, state, bs, fap_pri, fap_sec);
    11ae:	f8dd b01c 	ldr.w	fp, [sp, #28]
    11b2:	f852 1038 	ldr.w	r1, [r2, r8, lsl #3]
    11b6:	9104      	str	r1, [sp, #16]
    11b8:	ea4f 03c8 	mov.w	r3, r8, lsl #3
    11bc:	3b08      	subs	r3, #8
    11be:	6811      	ldr	r1, [r2, #0]
    11c0:	9103      	str	r1, [sp, #12]
    11c2:	58d1      	ldr	r1, [r2, r3]
    11c4:	6d2a      	ldr	r2, [r5, #80]	; 0x50
    11c6:	58d0      	ldr	r0, [r2, r3]
    11c8:	6813      	ldr	r3, [r2, #0]
    11ca:	eba0 0903 	sub.w	r9, r0, r3
    if (bs->state == BOOT_STATUS_STATE_0) {
    11ce:	7923      	ldrb	r3, [r4, #4]
    11d0:	2b01      	cmp	r3, #1
    11d2:	d138      	bne.n	1246 <swap_run+0x1f6>
    11d4:	9b03      	ldr	r3, [sp, #12]
        rc = boot_erase_region(fap_pri, pri_off, sz);
    11d6:	4632      	mov	r2, r6
    11d8:	1ac9      	subs	r1, r1, r3
    11da:	4650      	mov	r0, sl
    11dc:	9105      	str	r1, [sp, #20]
    11de:	f004 ff2d 	bl	603c <boot_erase_region>
        rc = boot_copy_region(state, fap_sec, fap_pri, sec_off, pri_off, sz);
    11e2:	9905      	ldr	r1, [sp, #20]
    11e4:	9100      	str	r1, [sp, #0]
    11e6:	464b      	mov	r3, r9
    11e8:	4652      	mov	r2, sl
    11ea:	4659      	mov	r1, fp
    11ec:	9601      	str	r6, [sp, #4]
    11ee:	4628      	mov	r0, r5
    11f0:	f7ff fc12 	bl	a18 <boot_copy_region>
        rc = boot_write_status(state, bs);
    11f4:	4621      	mov	r1, r4
    11f6:	4628      	mov	r0, r5
    11f8:	f004 feee 	bl	5fd8 <boot_write_status>
        bs->state = BOOT_STATUS_STATE_1;
    11fc:	2302      	movs	r3, #2
    11fe:	7123      	strb	r3, [r4, #4]
        BOOT_STATUS_ASSERT(rc == 0);
    1200:	b118      	cbz	r0, 120a <swap_run+0x1ba>
    1202:	4a17      	ldr	r2, [pc, #92]	; (1260 <swap_run+0x210>)
    1204:	6813      	ldr	r3, [r2, #0]
    1206:	3301      	adds	r3, #1
    1208:	6013      	str	r3, [r2, #0]
        rc = boot_erase_region(fap_sec, sec_off, sz);
    120a:	4632      	mov	r2, r6
    120c:	4649      	mov	r1, r9
    120e:	4658      	mov	r0, fp
    1210:	f004 ff14 	bl	603c <boot_erase_region>
        rc = boot_copy_region(state, fap_pri, fap_sec, pri_up_off, sec_off, sz);
    1214:	e9dd 2303 	ldrd	r2, r3, [sp, #12]
    1218:	4651      	mov	r1, sl
    121a:	1a9b      	subs	r3, r3, r2
    121c:	e9cd 9600 	strd	r9, r6, [sp]
    1220:	465a      	mov	r2, fp
    1222:	4628      	mov	r0, r5
    1224:	f7ff fbf8 	bl	a18 <boot_copy_region>
        rc = boot_write_status(state, bs);
    1228:	4621      	mov	r1, r4
    122a:	4628      	mov	r0, r5
    122c:	f004 fed4 	bl	5fd8 <boot_write_status>
        bs->idx++;
    1230:	6823      	ldr	r3, [r4, #0]
    1232:	3301      	adds	r3, #1
    1234:	6023      	str	r3, [r4, #0]
        bs->state = BOOT_STATUS_STATE_0;
    1236:	2301      	movs	r3, #1
    1238:	7123      	strb	r3, [r4, #4]
        BOOT_STATUS_ASSERT(rc == 0);
    123a:	b130      	cbz	r0, 124a <swap_run+0x1fa>
    123c:	4a08      	ldr	r2, [pc, #32]	; (1260 <swap_run+0x210>)
    123e:	6813      	ldr	r3, [r2, #0]
    1240:	3301      	adds	r3, #1
    1242:	6013      	str	r3, [r2, #0]
    1244:	e001      	b.n	124a <swap_run+0x1fa>
    if (bs->state == BOOT_STATUS_STATE_1) {
    1246:	2b02      	cmp	r3, #2
    1248:	d0df      	beq.n	120a <swap_run+0x1ba>
        idx++;
    124a:	f108 0801 	add.w	r8, r8, #1
    124e:	e75b      	b.n	1108 <swap_run+0xb8>
    1250:	0000792f 	.word	0x0000792f
    1254:	20000004 	.word	0x20000004
    1258:	00007958 	.word	0x00007958
    125c:	00007987 	.word	0x00007987
    1260:	20000e54 	.word	0x20000e54

00001264 <cc310_init>:
 */

#include "cc310_glue.h"

int cc310_init(void)
{
    1264:	b570      	push	{r4, r5, r6, lr}
    /* Only initialize once */
    static bool initialized;

    if (!initialized) {
    1266:	4d09      	ldr	r5, [pc, #36]	; (128c <cc310_init+0x28>)
    1268:	782b      	ldrb	r3, [r5, #0]
    126a:	b10b      	cbz	r3, 1270 <cc310_init+0xc>
        }
        initialized = true;
        nrf_cc310_disable();
    }

    return 0;
    126c:	2000      	movs	r0, #0
}
    126e:	bd70      	pop	{r4, r5, r6, pc}
    NRF_CRYPTOCELL->ENABLE=1;
    1270:	4c07      	ldr	r4, [pc, #28]	; (1290 <cc310_init+0x2c>)
    1272:	2601      	movs	r6, #1
    1274:	f8c4 6500 	str.w	r6, [r4, #1280]	; 0x500
        if (nrf_cc310_bl_init() != 0) {
    1278:	f003 fcfa 	bl	4c70 <nrf_cc310_bl_init>
    127c:	b918      	cbnz	r0, 1286 <cc310_init+0x22>
        initialized = true;
    127e:	702e      	strb	r6, [r5, #0]
    NRF_CRYPTOCELL->ENABLE=0;
    1280:	f8c4 0500 	str.w	r0, [r4, #1280]	; 0x500
}
    1284:	e7f2      	b.n	126c <cc310_init+0x8>
            return -1;
    1286:	f04f 30ff 	mov.w	r0, #4294967295
    128a:	e7f0      	b.n	126e <cc310_init+0xa>
    128c:	200010bc 	.word	0x200010bc
    1290:	5002a000 	.word	0x5002a000

00001294 <cc310_ecdsa_verify_secp256r1>:

int cc310_ecdsa_verify_secp256r1(uint8_t *hash,
                                 uint8_t *public_key,
                                 uint8_t *signature,
                                 size_t hash_len)
{
    1294:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    NRF_CRYPTOCELL->ENABLE=1;
    1298:	f8df 8030 	ldr.w	r8, [pc, #48]	; 12cc <cc310_ecdsa_verify_secp256r1+0x38>
    129c:	b0ac      	sub	sp, #176	; 0xb0
    129e:	461f      	mov	r7, r3
    12a0:	4606      	mov	r6, r0
    12a2:	460c      	mov	r4, r1
    12a4:	4615      	mov	r5, r2
        int rc;
        nrf_cc310_bl_ecdsa_verify_context_secp256r1_t ctx;
        cc310_init();
    12a6:	f7ff ffdd 	bl	1264 <cc310_init>
    12aa:	2301      	movs	r3, #1
    12ac:	f8c8 3500 	str.w	r3, [r8, #1280]	; 0x500
        nrf_cc310_enable();
        rc = nrf_cc310_bl_ecdsa_verify_secp256r1(&ctx,
    12b0:	462a      	mov	r2, r5
    12b2:	4633      	mov	r3, r6
    12b4:	9700      	str	r7, [sp, #0]
    12b6:	4621      	mov	r1, r4
    12b8:	a803      	add	r0, sp, #12
    12ba:	f005 fde9 	bl	6e90 <nrf_cc310_bl_ecdsa_verify_secp256r1>
    NRF_CRYPTOCELL->ENABLE=0;
    12be:	2300      	movs	r3, #0
    12c0:	f8c8 3500 	str.w	r3, [r8, #1280]	; 0x500
                                                 (nrf_cc310_bl_ecc_signature_secp256r1_t  *) signature,
                                                 hash,
                                                 hash_len);
        nrf_cc310_disable();
        return rc;
}
    12c4:	b02c      	add	sp, #176	; 0xb0
    12c6:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    12ca:	bf00      	nop
    12cc:	5002a000 	.word	0x5002a000

000012d0 <nrf_cleanup_peripheral>:
    return (uint32_t)p_reg + task;
}

NRF_STATIC_INLINE void nrf_rtc_task_trigger(NRF_RTC_Type * p_reg, nrf_rtc_task_t task)
{
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    12d0:	4a16      	ldr	r2, [pc, #88]	; (132c <nrf_cleanup_peripheral+0x5c>)
    p_reg->EVTENSET = mask;
}

NRF_STATIC_INLINE void nrf_rtc_event_disable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->EVTENCLR = mask;
    12d2:	f04f 33ff 	mov.w	r3, #4294967295
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    12d6:	2101      	movs	r1, #1
    12d8:	6051      	str	r1, [r2, #4]
    p_reg->EVTENCLR = mask;
    12da:	f8c2 3348 	str.w	r3, [r2, #840]	; 0x348
    p_reg->INTENCLR = mask;
    12de:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    12e2:	f502 42c0 	add.w	r2, r2, #24576	; 0x6000
    12e6:	6051      	str	r1, [r2, #4]
    p_reg->EVTENCLR = mask;
    12e8:	f8c2 3348 	str.w	r3, [r2, #840]	; 0x348
    p_reg->INTENCLR = mask;
    12ec:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    12f0:	f502 3298 	add.w	r2, r2, #77824	; 0x13000
    12f4:	6051      	str	r1, [r2, #4]
    p_reg->EVTENCLR = mask;
    12f6:	f8c2 3348 	str.w	r3, [r2, #840]	; 0x348
    p_reg->INTENCLR = mask;
    12fa:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
}

NRF_STATIC_INLINE void nrf_uarte_disable(NRF_UARTE_Type * p_reg)
{
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
    12fe:	f5a2 3208 	sub.w	r2, r2, #139264	; 0x22000
    1302:	2100      	movs	r1, #0
    1304:	f8c2 1500 	str.w	r1, [r2, #1280]	; 0x500
    p_reg->INTENCLR = mask;
    1308:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
    130c:	f502 3218 	add.w	r2, r2, #155648	; 0x26000
    1310:	f8c2 1500 	str.w	r1, [r2, #1280]	; 0x500
    p_reg->INTENCLR = mask;
    1314:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
    }
}

NRF_STATIC_INLINE void nrf_ppi_channels_disable_all(NRF_PPI_Type * p_reg)
{
    p_reg->CHENCLR = ((uint32_t)0xFFFFFFFFuL);
    1318:	f5a2 4210 	sub.w	r2, r2, #36864	; 0x9000
    131c:	f8c2 3508 	str.w	r3, [r2, #1288]	; 0x508
    p_reg->INTENSET = mask;
}

NRF_STATIC_INLINE void nrf_clock_int_disable(NRF_CLOCK_Type * p_reg, uint32_t mask)
{
    p_reg->INTENCLR = mask;
    1320:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    1324:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
#endif
#if defined(NRF_DPPIC)
    nrf_dppi_channels_disable_all(NRF_DPPIC);
#endif
    nrf_cleanup_clock();
}
    1328:	4770      	bx	lr
    132a:	bf00      	nop
    132c:	4000b000 	.word	0x4000b000

00001330 <char_out>:
}

static int char_out(int c, void *ctx_p)
{
	(void) ctx_p;
	return _char_out(c);
    1330:	4b01      	ldr	r3, [pc, #4]	; (1338 <char_out+0x8>)
    1332:	681b      	ldr	r3, [r3, #0]
    1334:	4718      	bx	r3
    1336:	bf00      	nop
    1338:	20000008 	.word	0x20000008

0000133c <__printk_hook_install>:
	_char_out = fn;
    133c:	4b01      	ldr	r3, [pc, #4]	; (1344 <__printk_hook_install+0x8>)
    133e:	6018      	str	r0, [r3, #0]
}
    1340:	4770      	bx	lr
    1342:	bf00      	nop
    1344:	20000008 	.word	0x20000008

00001348 <vprintk>:
}

void vprintk(const char *fmt, va_list ap)
{
    1348:	b507      	push	{r0, r1, r2, lr}
    134a:	460b      	mov	r3, r1
int cbvprintf(cbprintf_cb out, void *ctx, const char *format, va_list ap);
#else
static inline
int cbvprintf(cbprintf_cb out, void *ctx, const char *format, va_list ap)
{
	return z_cbvprintf_impl(out, ctx, format, ap, 0);
    134c:	2100      	movs	r1, #0
    134e:	4602      	mov	r2, r0
    1350:	9100      	str	r1, [sp, #0]
    1352:	4803      	ldr	r0, [pc, #12]	; (1360 <vprintk+0x18>)
    1354:	f000 f914 	bl	1580 <z_cbvprintf_impl>

#ifdef CONFIG_PRINTK_SYNC
		k_spin_unlock(&lock, key);
#endif
	}
}
    1358:	b003      	add	sp, #12
    135a:	f85d fb04 	ldr.w	pc, [sp], #4
    135e:	bf00      	nop
    1360:	00001331 	.word	0x00001331

00001364 <process_event>:
 * regions.
 */
static void process_event(struct onoff_manager *mgr,
			  int evt,
			  k_spinlock_key_t key)
{
    1364:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
	sys_slist_t clients;
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    1368:	8b05      	ldrh	r5, [r0, #24]
{
    136a:	4604      	mov	r4, r0
	__ASSERT_NO_MSG(evt != EVT_NOP);

	/* If this is a nested call record the event for processing in
	 * the top invocation.
	 */
	if (processing) {
    136c:	0728      	lsls	r0, r5, #28
{
    136e:	4690      	mov	r8, r2
	if (processing) {
    1370:	d411      	bmi.n	1396 <process_event+0x32>

	sys_slist_init(&clients);
	do {
		onoff_transition_fn transit = NULL;

		if (evt == EVT_RECHECK) {
    1372:	2902      	cmp	r1, #2
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    1374:	f005 0507 	and.w	r5, r5, #7
		if (evt == EVT_RECHECK) {
    1378:	f040 80cd 	bne.w	1516 <process_event+0x1b2>
			evt = process_recheck(mgr);
    137c:	4620      	mov	r0, r4
    137e:	f005 f81b 	bl	63b8 <process_recheck>
		}

		if (evt == EVT_NOP) {
    1382:	b178      	cbz	r0, 13a4 <process_event+0x40>
			break;
		}

		res = 0;
		if (evt == EVT_COMPLETE) {
    1384:	3801      	subs	r0, #1
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    1386:	8b21      	ldrh	r1, [r4, #24]
    1388:	2804      	cmp	r0, #4
    138a:	d811      	bhi.n	13b0 <process_event+0x4c>
    138c:	e8df f000 	tbb	[pc, r0]
    1390:	856d10c3 	.word	0x856d10c3
    1394:	95          	.byte	0x95
    1395:	00          	.byte	0x00
		if (evt == EVT_COMPLETE) {
    1396:	2901      	cmp	r1, #1
			mgr->flags |= ONOFF_FLAG_COMPLETE;
    1398:	bf0c      	ite	eq
    139a:	f045 0510 	orreq.w	r5, r5, #16
			mgr->flags |= ONOFF_FLAG_RECHECK;
    139e:	f045 0520 	orrne.w	r5, r5, #32
    13a2:	8325      	strh	r5, [r4, #24]
	__asm__ volatile(
		"cpsie i;"
		"isb"
		: : : "memory");
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	__asm__ volatile(
    13a4:	f388 8811 	msr	BASEPRI, r8
    13a8:	f3bf 8f6f 	isb	sy
		state = mgr->flags & ONOFF_STATE_MASK;
	} while (evt != EVT_NOP);

out:
	k_spin_unlock(&mgr->lock, key);
}
    13ac:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
    13b0:	f001 0a07 	and.w	sl, r1, #7
				   && !sys_slist_is_empty(&mgr->monitors);
    13b4:	45aa      	cmp	sl, r5
    13b6:	f000 80a6 	beq.w	1506 <process_event+0x1a2>
	 * a memory barrier when used like this, and we don't have a
	 * Zephyr framework for that.
	 */
	atomic_clear(&l->locked);
#endif
	arch_irq_unlock(key.key);
    13ba:	2700      	movs	r7, #0
    13bc:	46b9      	mov	r9, r7
    13be:	463e      	mov	r6, r7
    13c0:	68a3      	ldr	r3, [r4, #8]
    13c2:	2b00      	cmp	r3, #0
    13c4:	f000 80bd 	beq.w	1542 <process_event+0x1de>
			uint32_t flags = mgr->flags | ONOFF_FLAG_PROCESSING;
    13c8:	f041 0108 	orr.w	r1, r1, #8
			mgr->flags = flags;
    13cc:	8321      	strh	r1, [r4, #24]
    13ce:	f388 8811 	msr	BASEPRI, r8
    13d2:	f3bf 8f6f 	isb	sy
 *
 * @return A pointer on the first node of the list (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_head(sys_slist_t *list)
{
	return list->head;
    13d6:	68a1      	ldr	r1, [r4, #8]
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
    13d8:	2900      	cmp	r1, #0
    13da:	f000 80bb 	beq.w	1554 <process_event+0x1f0>
	return node->next;
    13de:	680d      	ldr	r5, [r1, #0]
    13e0:	2900      	cmp	r1, #0
    13e2:	f000 80b7 	beq.w	1554 <process_event+0x1f0>
		mon->callback(mgr, mon, state, res);
    13e6:	f8d1 8004 	ldr.w	r8, [r1, #4]
    13ea:	4633      	mov	r3, r6
    13ec:	4652      	mov	r2, sl
    13ee:	4620      	mov	r0, r4
    13f0:	47c0      	blx	r8
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
    13f2:	2d00      	cmp	r5, #0
    13f4:	d076      	beq.n	14e4 <process_event+0x180>
    13f6:	682b      	ldr	r3, [r5, #0]
    13f8:	4629      	mov	r1, r5
    13fa:	461d      	mov	r5, r3
    13fc:	e7f0      	b.n	13e0 <process_event+0x7c>
    13fe:	f001 0307 	and.w	r3, r1, #7
		   || (state == ONOFF_STATE_RESETTING)) {
    1402:	1f5a      	subs	r2, r3, #5
	} else if ((state == ONOFF_STATE_TO_ON)
    1404:	2a01      	cmp	r2, #1
    1406:	d81b      	bhi.n	1440 <process_event+0xdc>
	list->head = NULL;
    1408:	2200      	movs	r2, #0
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    140a:	f021 0107 	bic.w	r1, r1, #7
		if (state == ONOFF_STATE_TO_ON) {
    140e:	2b06      	cmp	r3, #6
		*clients = mgr->clients;
    1410:	6827      	ldr	r7, [r4, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    1412:	b289      	uxth	r1, r1
	list->tail = NULL;
    1414:	e9c4 2200 	strd	r2, r2, [r4]
		if (state == ONOFF_STATE_TO_ON) {
    1418:	d109      	bne.n	142e <process_event+0xca>
    141a:	463b      	mov	r3, r7
    141c:	e003      	b.n	1426 <process_event+0xc2>
				mgr->refs += 1U;
    141e:	8b62      	ldrh	r2, [r4, #26]
    1420:	3201      	adds	r2, #1
    1422:	8362      	strh	r2, [r4, #26]
	return node->next;
    1424:	681b      	ldr	r3, [r3, #0]
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
    1426:	2b00      	cmp	r3, #0
    1428:	d1f9      	bne.n	141e <process_event+0xba>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    142a:	f041 0102 	orr.w	r1, r1, #2
	mgr->flags = (state & ONOFF_STATE_MASK)
    142e:	8321      	strh	r1, [r4, #24]
		if (process_recheck(mgr) != EVT_NOP) {
    1430:	4620      	mov	r0, r4
    1432:	f004 ffc1 	bl	63b8 <process_recheck>
    1436:	2800      	cmp	r0, #0
    1438:	d07b      	beq.n	1532 <process_event+0x1ce>
			mgr->flags |= ONOFF_FLAG_RECHECK;
    143a:	f041 0120 	orr.w	r1, r1, #32
    143e:	e077      	b.n	1530 <process_event+0x1cc>
	} else if (state == ONOFF_STATE_TO_OFF) {
    1440:	2b04      	cmp	r3, #4
    1442:	d10a      	bne.n	145a <process_event+0xf6>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    1444:	f021 0107 	bic.w	r1, r1, #7
    1448:	b289      	uxth	r1, r1
	mgr->flags = (state & ONOFF_STATE_MASK)
    144a:	8321      	strh	r1, [r4, #24]
		if (process_recheck(mgr) != EVT_NOP) {
    144c:	4620      	mov	r0, r4
    144e:	f004 ffb3 	bl	63b8 <process_recheck>
    1452:	b110      	cbz	r0, 145a <process_event+0xf6>
			mgr->flags |= ONOFF_FLAG_RECHECK;
    1454:	f041 0120 	orr.w	r1, r1, #32
    1458:	8321      	strh	r1, [r4, #24]
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
    145a:	8b21      	ldrh	r1, [r4, #24]
    145c:	f001 0a07 	and.w	sl, r1, #7
				   && !sys_slist_is_empty(&mgr->monitors);
    1460:	45aa      	cmp	sl, r5
    1462:	d050      	beq.n	1506 <process_event+0x1a2>
    1464:	2700      	movs	r7, #0
		onoff_transition_fn transit = NULL;
    1466:	46b9      	mov	r9, r7
    1468:	e7aa      	b.n	13c0 <process_event+0x5c>
			transit = mgr->transitions->start;
    146a:	6923      	ldr	r3, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    146c:	f021 0107 	bic.w	r1, r1, #7
    1470:	f041 0106 	orr.w	r1, r1, #6
				   && !sys_slist_is_empty(&mgr->monitors);
    1474:	2d06      	cmp	r5, #6
			transit = mgr->transitions->start;
    1476:	f8d3 9000 	ldr.w	r9, [r3]
	mgr->flags = (state & ONOFF_STATE_MASK)
    147a:	8321      	strh	r1, [r4, #24]
				   && !sys_slist_is_empty(&mgr->monitors);
    147c:	d12d      	bne.n	14da <process_event+0x176>
		    || (transit != NULL)) {
    147e:	f1b9 0f00 	cmp.w	r9, #0
    1482:	d040      	beq.n	1506 <process_event+0x1a2>
			uint32_t flags = mgr->flags | ONOFF_FLAG_PROCESSING;
    1484:	f041 0108 	orr.w	r1, r1, #8
			mgr->flags = flags;
    1488:	8321      	strh	r1, [r4, #24]
    148a:	f388 8811 	msr	BASEPRI, r8
    148e:	f3bf 8f6f 	isb	sy
				transit(mgr, transition_complete);
    1492:	493a      	ldr	r1, [pc, #232]	; (157c <process_event+0x218>)
    1494:	4620      	mov	r0, r4
    1496:	47c8      	blx	r9
    1498:	e029      	b.n	14ee <process_event+0x18a>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    149a:	f021 0107 	bic.w	r1, r1, #7
			transit = mgr->transitions->stop;
    149e:	6923      	ldr	r3, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    14a0:	f041 0104 	orr.w	r1, r1, #4
    14a4:	b289      	uxth	r1, r1
				   && !sys_slist_is_empty(&mgr->monitors);
    14a6:	2d04      	cmp	r5, #4
			transit = mgr->transitions->stop;
    14a8:	f8d3 9004 	ldr.w	r9, [r3, #4]
	mgr->flags = (state & ONOFF_STATE_MASK)
    14ac:	8321      	strh	r1, [r4, #24]
				   && !sys_slist_is_empty(&mgr->monitors);
    14ae:	d0e6      	beq.n	147e <process_event+0x11a>
    14b0:	2700      	movs	r7, #0
		res = 0;
    14b2:	463e      	mov	r6, r7
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
    14b4:	f04f 0a04 	mov.w	sl, #4
    14b8:	e782      	b.n	13c0 <process_event+0x5c>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    14ba:	f021 0107 	bic.w	r1, r1, #7
			transit = mgr->transitions->reset;
    14be:	6923      	ldr	r3, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    14c0:	f041 0105 	orr.w	r1, r1, #5
    14c4:	b289      	uxth	r1, r1
				   && !sys_slist_is_empty(&mgr->monitors);
    14c6:	2d05      	cmp	r5, #5
			transit = mgr->transitions->reset;
    14c8:	f8d3 9008 	ldr.w	r9, [r3, #8]
	mgr->flags = (state & ONOFF_STATE_MASK)
    14cc:	8321      	strh	r1, [r4, #24]
				   && !sys_slist_is_empty(&mgr->monitors);
    14ce:	d0d6      	beq.n	147e <process_event+0x11a>
    14d0:	2700      	movs	r7, #0
		res = 0;
    14d2:	463e      	mov	r6, r7
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
    14d4:	f04f 0a05 	mov.w	sl, #5
    14d8:	e772      	b.n	13c0 <process_event+0x5c>
				   && !sys_slist_is_empty(&mgr->monitors);
    14da:	2700      	movs	r7, #0
		res = 0;
    14dc:	463e      	mov	r6, r7
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
    14de:	f04f 0a06 	mov.w	sl, #6
    14e2:	e76d      	b.n	13c0 <process_event+0x5c>
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
    14e4:	462b      	mov	r3, r5
    14e6:	e787      	b.n	13f8 <process_event+0x94>
			if (transit != NULL) {
    14e8:	f1b9 0f00 	cmp.w	r9, #0
    14ec:	d1d1      	bne.n	1492 <process_event+0x12e>
	__asm__ volatile(
    14ee:	f04f 0320 	mov.w	r3, #32
    14f2:	f3ef 8811 	mrs	r8, BASEPRI
    14f6:	f383 8812 	msr	BASEPRI_MAX, r3
    14fa:	f3bf 8f6f 	isb	sy
			mgr->flags &= ~ONOFF_FLAG_PROCESSING;
    14fe:	8b23      	ldrh	r3, [r4, #24]
    1500:	f023 0308 	bic.w	r3, r3, #8
    1504:	8323      	strh	r3, [r4, #24]
		if ((mgr->flags & ONOFF_FLAG_COMPLETE) != 0) {
    1506:	8b25      	ldrh	r5, [r4, #24]
    1508:	06ea      	lsls	r2, r5, #27
    150a:	d52e      	bpl.n	156a <process_event+0x206>
			mgr->flags &= ~ONOFF_FLAG_COMPLETE;
    150c:	f025 0310 	bic.w	r3, r5, #16
    1510:	8323      	strh	r3, [r4, #24]
		state = mgr->flags & ONOFF_STATE_MASK;
    1512:	f005 0507 	and.w	r5, r5, #7
			res = mgr->last_res;
    1516:	6966      	ldr	r6, [r4, #20]
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    1518:	8b21      	ldrh	r1, [r4, #24]
	if (res < 0) {
    151a:	2e00      	cmp	r6, #0
    151c:	f6bf af6f 	bge.w	13fe <process_event+0x9a>
	list->head = NULL;
    1520:	2300      	movs	r3, #0
		*clients = mgr->clients;
    1522:	6827      	ldr	r7, [r4, #0]
	list->tail = NULL;
    1524:	e9c4 3300 	strd	r3, r3, [r4]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    1528:	f021 0107 	bic.w	r1, r1, #7
    152c:	f041 0101 	orr.w	r1, r1, #1
			mgr->flags |= ONOFF_FLAG_RECHECK;
    1530:	8321      	strh	r1, [r4, #24]
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
    1532:	8b21      	ldrh	r1, [r4, #24]
    1534:	f001 0a07 	and.w	sl, r1, #7
				   && !sys_slist_is_empty(&mgr->monitors);
    1538:	45aa      	cmp	sl, r5
    153a:	f04f 0900 	mov.w	r9, #0
    153e:	f47f af3f 	bne.w	13c0 <process_event+0x5c>
		    || !sys_slist_is_empty(&clients)
    1542:	2f00      	cmp	r7, #0
    1544:	d09b      	beq.n	147e <process_event+0x11a>
			uint32_t flags = mgr->flags | ONOFF_FLAG_PROCESSING;
    1546:	f041 0108 	orr.w	r1, r1, #8
			mgr->flags = flags;
    154a:	8321      	strh	r1, [r4, #24]
	__asm__ volatile(
    154c:	f388 8811 	msr	BASEPRI, r8
    1550:	f3bf 8f6f 	isb	sy
			if (!sys_slist_is_empty(&clients)) {
    1554:	2f00      	cmp	r7, #0
    1556:	d0c7      	beq.n	14e8 <process_event+0x184>
	return node->next;
    1558:	683d      	ldr	r5, [r7, #0]
		notify_one(mgr, cli, state, res);
    155a:	4639      	mov	r1, r7
    155c:	4633      	mov	r3, r6
    155e:	4652      	mov	r2, sl
    1560:	4620      	mov	r0, r4
    1562:	f004 ff55 	bl	6410 <notify_one>
	list->head = node;
    1566:	462f      	mov	r7, r5
	while (!sys_slist_is_empty(list)) {
    1568:	e7f4      	b.n	1554 <process_event+0x1f0>
		} else if ((mgr->flags & ONOFF_FLAG_RECHECK) != 0) {
    156a:	06ab      	lsls	r3, r5, #26
    156c:	f57f af1a 	bpl.w	13a4 <process_event+0x40>
			mgr->flags &= ~ONOFF_FLAG_RECHECK;
    1570:	f025 0320 	bic.w	r3, r5, #32
			mgr->flags &= ~ONOFF_FLAG_COMPLETE;
    1574:	8323      	strh	r3, [r4, #24]
		state = mgr->flags & ONOFF_STATE_MASK;
    1576:	f005 0507 	and.w	r5, r5, #7
		if (evt == EVT_RECHECK) {
    157a:	e6ff      	b.n	137c <process_event+0x18>
    157c:	0000643d 	.word	0x0000643d

00001580 <z_cbvprintf_impl>:
 *
 * @return printed byte count if CONFIG_CBPRINTF_LIBC_SUBSTS is set
 */
int z_cbvprintf_impl(cbprintf_cb out, void *ctx, const char *fmt,
		     va_list ap, uint32_t flags)
{
    1580:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    1584:	b08d      	sub	sp, #52	; 0x34
    1586:	461d      	mov	r5, r3

	const bool tagged_ap = (flags & Z_CBVPRINTF_PROCESS_FLAG_TAGGED_ARGS)
			       == Z_CBVPRINTF_PROCESS_FLAG_TAGGED_ARGS;

	/* we pre-increment in the loop  afterwards */
	fmt--;
    1588:	1e53      	subs	r3, r2, #1
{
    158a:	4682      	mov	sl, r0
    158c:	9101      	str	r1, [sp, #4]
	fmt--;
    158e:	9303      	str	r3, [sp, #12]
	size_t count = 0;
    1590:	f04f 0900 	mov.w	r9, #0

start:
	while (*++fmt != '%') {
    1594:	9b03      	ldr	r3, [sp, #12]
    1596:	7858      	ldrb	r0, [r3, #1]
    1598:	2825      	cmp	r0, #37	; 0x25
    159a:	f103 0401 	add.w	r4, r3, #1
    159e:	d119      	bne.n	15d4 <z_cbvprintf_impl+0x54>
	prefix = "";
	padding_mode = 0;
	length_mod = 0;
	special = 0;

	for (fmt++ ; ; fmt++) {
    15a0:	461e      	mov	r6, r3
	special = 0;
    15a2:	2000      	movs	r0, #0
	precision = -1;
    15a4:	f04f 38ff 	mov.w	r8, #4294967295
	for (fmt++ ; ; fmt++) {
    15a8:	3602      	adds	r6, #2
	length_mod = 0;
    15aa:	4603      	mov	r3, r0
	padding_mode = 0;
    15ac:	9002      	str	r0, [sp, #8]
	min_width = -1;
    15ae:	4644      	mov	r4, r8
		switch (*fmt) {
    15b0:	7831      	ldrb	r1, [r6, #0]
    15b2:	9603      	str	r6, [sp, #12]
    15b4:	2939      	cmp	r1, #57	; 0x39
    15b6:	d854      	bhi.n	1662 <z_cbvprintf_impl+0xe2>
    15b8:	291f      	cmp	r1, #31
    15ba:	d814      	bhi.n	15e6 <z_cbvprintf_impl+0x66>
    15bc:	2900      	cmp	r1, #0
    15be:	f000 81ed 	beq.w	199c <z_cbvprintf_impl+0x41c>
			precision = 0;
			break;
		}

		default:
			OUTC('%');
    15c2:	9901      	ldr	r1, [sp, #4]
    15c4:	2025      	movs	r0, #37	; 0x25
    15c6:	47d0      	blx	sl
			OUTC(*fmt);
    15c8:	9901      	ldr	r1, [sp, #4]
    15ca:	7830      	ldrb	r0, [r6, #0]
    15cc:	47d0      	blx	sl
    15ce:	f109 0902 	add.w	r9, r9, #2
			goto start;
    15d2:	e7df      	b.n	1594 <z_cbvprintf_impl+0x14>
		if (*fmt == '\0') {
    15d4:	2800      	cmp	r0, #0
    15d6:	f000 81e1 	beq.w	199c <z_cbvprintf_impl+0x41c>
		OUTC(*fmt);
    15da:	9901      	ldr	r1, [sp, #4]
    15dc:	47d0      	blx	sl
    15de:	f109 0901 	add.w	r9, r9, #1
	while (*++fmt != '%') {
    15e2:	9403      	str	r4, [sp, #12]
    15e4:	e7d6      	b.n	1594 <z_cbvprintf_impl+0x14>
		switch (*fmt) {
    15e6:	f1a1 0220 	sub.w	r2, r1, #32
    15ea:	2a19      	cmp	r2, #25
    15ec:	d8e9      	bhi.n	15c2 <z_cbvprintf_impl+0x42>
    15ee:	a701      	add	r7, pc, #4	; (adr r7, 15f4 <z_cbvprintf_impl+0x74>)
    15f0:	f857 f022 	ldr.w	pc, [r7, r2, lsl #2]
    15f4:	0000165d 	.word	0x0000165d
    15f8:	000015c3 	.word	0x000015c3
    15fc:	000015c3 	.word	0x000015c3
    1600:	0000165d 	.word	0x0000165d
    1604:	000015c3 	.word	0x000015c3
    1608:	000016dd 	.word	0x000016dd
    160c:	000015c3 	.word	0x000015c3
    1610:	000015c3 	.word	0x000015c3
    1614:	000015c3 	.word	0x000015c3
    1618:	000015c3 	.word	0x000015c3
    161c:	00001729 	.word	0x00001729
    1620:	0000165d 	.word	0x0000165d
    1624:	000015c3 	.word	0x000015c3
    1628:	0000173d 	.word	0x0000173d
    162c:	000016e9 	.word	0x000016e9
    1630:	000015c3 	.word	0x000015c3
    1634:	000016f7 	.word	0x000016f7
    1638:	00001717 	.word	0x00001717
    163c:	00001717 	.word	0x00001717
    1640:	00001717 	.word	0x00001717
    1644:	00001717 	.word	0x00001717
    1648:	00001717 	.word	0x00001717
    164c:	00001717 	.word	0x00001717
    1650:	00001717 	.word	0x00001717
    1654:	00001717 	.word	0x00001717
    1658:	00001717 	.word	0x00001717
    165c:	4608      	mov	r0, r1
    165e:	3601      	adds	r6, #1
    1660:	e7a6      	b.n	15b0 <z_cbvprintf_impl+0x30>
    1662:	2958      	cmp	r1, #88	; 0x58
    1664:	f000 80eb 	beq.w	183e <z_cbvprintf_impl+0x2be>
    1668:	f1a1 0263 	sub.w	r2, r1, #99	; 0x63
    166c:	b2d7      	uxtb	r7, r2
    166e:	2f17      	cmp	r7, #23
    1670:	d8a7      	bhi.n	15c2 <z_cbvprintf_impl+0x42>
    1672:	2a17      	cmp	r2, #23
    1674:	d8a5      	bhi.n	15c2 <z_cbvprintf_impl+0x42>
    1676:	a701      	add	r7, pc, #4	; (adr r7, 167c <z_cbvprintf_impl+0xfc>)
    1678:	f857 f022 	ldr.w	pc, [r7, r2, lsl #2]
    167c:	000018e5 	.word	0x000018e5
    1680:	00001763 	.word	0x00001763
    1684:	000015c3 	.word	0x000015c3
    1688:	000015c3 	.word	0x000015c3
    168c:	000015c3 	.word	0x000015c3
    1690:	00001743 	.word	0x00001743
    1694:	00001763 	.word	0x00001763
    1698:	000015c3 	.word	0x000015c3
    169c:	000015c3 	.word	0x000015c3
    16a0:	00001743 	.word	0x00001743
    16a4:	000015c3 	.word	0x000015c3
    16a8:	000015c3 	.word	0x000015c3
    16ac:	000015c3 	.word	0x000015c3
    16b0:	00001819 	.word	0x00001819
    16b4:	000015c3 	.word	0x000015c3
    16b8:	000015c3 	.word	0x000015c3
    16bc:	000018b9 	.word	0x000018b9
    16c0:	000015c3 	.word	0x000015c3
    16c4:	00001763 	.word	0x00001763
    16c8:	000015c3 	.word	0x000015c3
    16cc:	000015c3 	.word	0x000015c3
    16d0:	00001819 	.word	0x00001819
    16d4:	000015c3 	.word	0x000015c3
    16d8:	00001743 	.word	0x00001743
			OUTC('%');
    16dc:	9901      	ldr	r1, [sp, #4]
    16de:	2025      	movs	r0, #37	; 0x25
    16e0:	47d0      	blx	sl
    16e2:	f109 0901 	add.w	r9, r9, #1
			goto start;
    16e6:	e755      	b.n	1594 <z_cbvprintf_impl+0x14>
			padding_mode &= (char)~PAD_ZERO;
    16e8:	9a02      	ldr	r2, [sp, #8]
    16ea:	f002 02fe 	and.w	r2, r2, #254	; 0xfe
    16ee:	9202      	str	r2, [sp, #8]
			precision = 0;
    16f0:	f04f 0800 	mov.w	r8, #0
			continue;
    16f4:	e7b3      	b.n	165e <z_cbvprintf_impl+0xde>
			if (min_width < 0 && precision < 0 && !padding_mode) {
    16f6:	2c00      	cmp	r4, #0
    16f8:	da0d      	bge.n	1716 <z_cbvprintf_impl+0x196>
    16fa:	f1b8 0f00 	cmp.w	r8, #0
    16fe:	da0d      	bge.n	171c <z_cbvprintf_impl+0x19c>
    1700:	9a02      	ldr	r2, [sp, #8]
    1702:	2a00      	cmp	r2, #0
    1704:	f000 8142 	beq.w	198c <z_cbvprintf_impl+0x40c>
				if (min_width < 0) {
    1708:	ea24 74e4 	bic.w	r4, r4, r4, asr #31
				min_width = 10 * min_width + *fmt - '0';
    170c:	220a      	movs	r2, #10
    170e:	fb02 1404 	mla	r4, r2, r4, r1
    1712:	3c30      	subs	r4, #48	; 0x30
    1714:	e7a3      	b.n	165e <z_cbvprintf_impl+0xde>
			if (precision >= 0) {
    1716:	f1b8 0f00 	cmp.w	r8, #0
    171a:	dbf5      	blt.n	1708 <z_cbvprintf_impl+0x188>
				precision = 10 * precision + *fmt - '0';
    171c:	220a      	movs	r2, #10
    171e:	fb02 1208 	mla	r2, r2, r8, r1
    1722:	f1a2 0830 	sub.w	r8, r2, #48	; 0x30
    1726:	e79a      	b.n	165e <z_cbvprintf_impl+0xde>
			if (precision >= 0) {
    1728:	f1b8 0f00 	cmp.w	r8, #0
				precision = va_arg(ap, int);
    172c:	f855 2b04 	ldr.w	r2, [r5], #4
			if (precision >= 0) {
    1730:	f280 812e 	bge.w	1990 <z_cbvprintf_impl+0x410>
				if (min_width < 0) {
    1734:	2a00      	cmp	r2, #0
    1736:	f280 812d 	bge.w	1994 <z_cbvprintf_impl+0x414>
					min_width = -min_width;
    173a:	4254      	negs	r4, r2
		switch (*fmt) {
    173c:	2202      	movs	r2, #2
				padding_mode = PAD_ZERO;
    173e:	9202      	str	r2, [sp, #8]
    1740:	e78d      	b.n	165e <z_cbvprintf_impl+0xde>
			if (*fmt == 'h' && length_mod == 'h') {
    1742:	2968      	cmp	r1, #104	; 0x68
    1744:	d103      	bne.n	174e <z_cbvprintf_impl+0x1ce>
    1746:	2b68      	cmp	r3, #104	; 0x68
    1748:	d106      	bne.n	1758 <z_cbvprintf_impl+0x1d8>
				length_mod = 'H';
    174a:	2348      	movs	r3, #72	; 0x48
    174c:	e787      	b.n	165e <z_cbvprintf_impl+0xde>
			} else if (*fmt == 'l' && length_mod == 'l') {
    174e:	296c      	cmp	r1, #108	; 0x6c
    1750:	d102      	bne.n	1758 <z_cbvprintf_impl+0x1d8>
    1752:	2b6c      	cmp	r3, #108	; 0x6c
    1754:	f000 8120 	beq.w	1998 <z_cbvprintf_impl+0x418>
			} else if (length_mod == '\0') {
    1758:	2b00      	cmp	r3, #0
    175a:	f47f af32 	bne.w	15c2 <z_cbvprintf_impl+0x42>
		switch (*fmt) {
    175e:	460b      	mov	r3, r1
    1760:	e77d      	b.n	165e <z_cbvprintf_impl+0xde>
			if (length_mod == 'z') {
    1762:	2b7a      	cmp	r3, #122	; 0x7a
    1764:	d106      	bne.n	1774 <z_cbvprintf_impl+0x1f4>
			} else if (*fmt == 'u') {
    1766:	2975      	cmp	r1, #117	; 0x75
				precision = va_arg(ap, int);
    1768:	f855 6b04 	ldr.w	r6, [r5], #4
			} else if (*fmt == 'u') {
    176c:	d114      	bne.n	1798 <z_cbvprintf_impl+0x218>
				d = va_arg(ap, unsigned int);
    176e:	f04f 0b00 	mov.w	fp, #0
			if (*fmt != 'u' && (int_value_type)d < 0) {
    1772:	e00c      	b.n	178e <z_cbvprintf_impl+0x20e>
			} else if (length_mod == 'l') {
    1774:	2b6c      	cmp	r3, #108	; 0x6c
    1776:	d0f6      	beq.n	1766 <z_cbvprintf_impl+0x1e6>
			} else if (length_mod == 'L') {
    1778:	2b4c      	cmp	r3, #76	; 0x4c
    177a:	d1f4      	bne.n	1766 <z_cbvprintf_impl+0x1e6>
					unsigned long long llu =
    177c:	3507      	adds	r5, #7
    177e:	f025 0307 	bic.w	r3, r5, #7
				if (*fmt == 'u') {
    1782:	2975      	cmp	r1, #117	; 0x75
					unsigned long long llu =
    1784:	e9d3 6b00 	ldrd	r6, fp, [r3]
    1788:	f103 0508 	add.w	r5, r3, #8
				if (*fmt == 'u') {
    178c:	d106      	bne.n	179c <z_cbvprintf_impl+0x21c>
			} else if (special == ' ') {
    178e:	2820      	cmp	r0, #32
    1790:	d13b      	bne.n	180a <z_cbvprintf_impl+0x28a>
				prefix = " ";
    1792:	4f84      	ldr	r7, [pc, #528]	; (19a4 <z_cbvprintf_impl+0x424>)
				min_width--;
    1794:	3c01      	subs	r4, #1
    1796:	e009      	b.n	17ac <z_cbvprintf_impl+0x22c>
				d = va_arg(ap, int);
    1798:	ea4f 7be6 	mov.w	fp, r6, asr #31
			if (*fmt != 'u' && (int_value_type)d < 0) {
    179c:	f1bb 0f00 	cmp.w	fp, #0
    17a0:	daf5      	bge.n	178e <z_cbvprintf_impl+0x20e>
				d = -d;
    17a2:	4276      	negs	r6, r6
				prefix = "-";
    17a4:	4f80      	ldr	r7, [pc, #512]	; (19a8 <z_cbvprintf_impl+0x428>)
				d = -d;
    17a6:	eb6b 0b4b 	sbc.w	fp, fp, fp, lsl #1
				min_width--;
    17aa:	3c01      	subs	r4, #1
	int i = 0;
    17ac:	f10d 032d 	add.w	r3, sp, #45	; 0x2d
    17b0:	9305      	str	r3, [sp, #20]
    17b2:	2300      	movs	r3, #0
    17b4:	9304      	str	r3, [sp, #16]
		unsigned int c = num % base;
    17b6:	4630      	mov	r0, r6
    17b8:	4659      	mov	r1, fp
    17ba:	220a      	movs	r2, #10
    17bc:	2300      	movs	r3, #0
    17be:	f7fe fc9f 	bl	100 <__aeabi_uldivmod>
    17c2:	9b04      	ldr	r3, [sp, #16]
    17c4:	468e      	mov	lr, r1
		buftop[--i] = c + '0';
    17c6:	1e59      	subs	r1, r3, #1
    17c8:	9104      	str	r1, [sp, #16]
    17ca:	9905      	ldr	r1, [sp, #20]
    17cc:	3230      	adds	r2, #48	; 0x30
    17ce:	46b4      	mov	ip, r6
    17d0:	f801 2d01 	strb.w	r2, [r1, #-1]!
	} while (num);
    17d4:	f1bc 0f0a 	cmp.w	ip, #10
    17d8:	465a      	mov	r2, fp
    17da:	f172 0200 	sbcs.w	r2, r2, #0
		buftop[--i] = c + '0';
    17de:	9105      	str	r1, [sp, #20]
		num /= base;
    17e0:	4606      	mov	r6, r0
    17e2:	46f3      	mov	fp, lr
	} while (num);
    17e4:	d2e7      	bcs.n	17b6 <z_cbvprintf_impl+0x236>
	return -i;
    17e6:	f1c3 0b01 	rsb	fp, r3, #1
			data = buf + sizeof(buf) - data_len;
    17ea:	3330      	adds	r3, #48	; 0x30
			data = buf + sizeof(buf) - data_len;
    17ec:	eb0d 0603 	add.w	r6, sp, r3
		}

		if (precision < 0 && (padding_mode & PAD_ZERO)) {
    17f0:	f1b8 0f00 	cmp.w	r8, #0
			data = buf + sizeof(buf) - data_len;
    17f4:	f1a6 0604 	sub.w	r6, r6, #4
		if (precision < 0 && (padding_mode & PAD_ZERO)) {
    17f8:	da6d      	bge.n	18d6 <z_cbvprintf_impl+0x356>
    17fa:	9b02      	ldr	r3, [sp, #8]
    17fc:	07d9      	lsls	r1, r3, #31
    17fe:	d47c      	bmi.n	18fa <z_cbvprintf_impl+0x37a>
			precision = min_width;
		}
		min_width -= data_len;
		precision -= data_len;
    1800:	eba8 030b 	sub.w	r3, r8, fp
		min_width -= data_len;
    1804:	eba4 040b 	sub.w	r4, r4, fp
    1808:	e013      	b.n	1832 <z_cbvprintf_impl+0x2b2>
			} else if (special == '+') {
    180a:	282b      	cmp	r0, #43	; 0x2b
				prefix = "+";
    180c:	bf0a      	itet	eq
    180e:	4f67      	ldreq	r7, [pc, #412]	; (19ac <z_cbvprintf_impl+0x42c>)
	prefix = "";
    1810:	4f67      	ldrne	r7, [pc, #412]	; (19b0 <z_cbvprintf_impl+0x430>)
				min_width--;
    1812:	f104 34ff 	addeq.w	r4, r4, #4294967295
    1816:	e7c9      	b.n	17ac <z_cbvprintf_impl+0x22c>
			if (*fmt == 'p') {
    1818:	2970      	cmp	r1, #112	; 0x70
    181a:	d10f      	bne.n	183c <z_cbvprintf_impl+0x2bc>
				x = (uintptr_t)va_arg(ap, void *);
    181c:	f855 2b04 	ldr.w	r2, [r5], #4
    1820:	2300      	movs	r3, #0
				if (x == (uint_value_type)0) {
    1822:	b9fa      	cbnz	r2, 1864 <z_cbvprintf_impl+0x2e4>
					data = "(nil)";
    1824:	4e63      	ldr	r6, [pc, #396]	; (19b4 <z_cbvprintf_impl+0x434>)
		min_width -= data_len;
    1826:	3c05      	subs	r4, #5
		precision -= data_len;
    1828:	f06f 0304 	mvn.w	r3, #4
					data_len = 5;
    182c:	f04f 0b05 	mov.w	fp, #5
	prefix = "";
    1830:	4f5f      	ldr	r7, [pc, #380]	; (19b0 <z_cbvprintf_impl+0x430>)
		if (precision > 0) {
			min_width -= precision;
		}

		if (!(padding_mode & PAD_TAIL)) {
    1832:	9a02      	ldr	r2, [sp, #8]
    1834:	0792      	lsls	r2, r2, #30
    1836:	d46f      	bmi.n	1918 <z_cbvprintf_impl+0x398>
    1838:	46a0      	mov	r8, r4
    183a:	e065      	b.n	1908 <z_cbvprintf_impl+0x388>
		switch (*fmt) {
    183c:	2178      	movs	r1, #120	; 0x78
			} else if (length_mod == 'l') {
    183e:	2b6c      	cmp	r3, #108	; 0x6c
    1840:	d103      	bne.n	184a <z_cbvprintf_impl+0x2ca>
				x = va_arg(ap, unsigned int);
    1842:	f855 2b04 	ldr.w	r2, [r5], #4
    1846:	2300      	movs	r3, #0
    1848:	e008      	b.n	185c <z_cbvprintf_impl+0x2dc>
			} else if (length_mod == 'L') {
    184a:	2b4c      	cmp	r3, #76	; 0x4c
    184c:	d1f9      	bne.n	1842 <z_cbvprintf_impl+0x2c2>
				unsigned long long llx =
    184e:	3507      	adds	r5, #7
    1850:	f025 0307 	bic.w	r3, r5, #7
    1854:	461d      	mov	r5, r3
    1856:	685b      	ldr	r3, [r3, #4]
    1858:	f855 2b08 	ldr.w	r2, [r5], #8
			if (special == '#') {
    185c:	2823      	cmp	r0, #35	; 0x23
    185e:	d125      	bne.n	18ac <z_cbvprintf_impl+0x32c>
				prefix = (*fmt & 0x20) ? "0x" : "0X";
    1860:	0688      	lsls	r0, r1, #26
    1862:	d521      	bpl.n	18a8 <z_cbvprintf_impl+0x328>
    1864:	4f54      	ldr	r7, [pc, #336]	; (19b8 <z_cbvprintf_impl+0x438>)
				min_width -= 2;
    1866:	3c02      	subs	r4, #2
			data_len = convert_value(x, 16, ALPHA(*fmt),
    1868:	f001 0160 	and.w	r1, r1, #96	; 0x60
    186c:	f1a1 0b39 	sub.w	fp, r1, #57	; 0x39
	int i = 0;
    1870:	f10d 0e2d 	add.w	lr, sp, #45	; 0x2d
    1874:	2600      	movs	r6, #0
		unsigned int c = num % base;
    1876:	f002 010f 	and.w	r1, r2, #15
		if (c >= 10) {
    187a:	2909      	cmp	r1, #9
			c += alpha;
    187c:	bf88      	it	hi
    187e:	4459      	addhi	r1, fp
		buftop[--i] = c + '0';
    1880:	3130      	adds	r1, #48	; 0x30
    1882:	f80e 1d01 	strb.w	r1, [lr, #-1]!
	} while (num);
    1886:	2a10      	cmp	r2, #16
		num /= base;
    1888:	ea4f 1112 	mov.w	r1, r2, lsr #4
    188c:	ea41 7103 	orr.w	r1, r1, r3, lsl #28
    1890:	ea4f 1013 	mov.w	r0, r3, lsr #4
	} while (num);
    1894:	f173 0300 	sbcs.w	r3, r3, #0
		buftop[--i] = c + '0';
    1898:	f106 3cff 	add.w	ip, r6, #4294967295
	} while (num);
    189c:	d208      	bcs.n	18b0 <z_cbvprintf_impl+0x330>
	return -i;
    189e:	f1c6 0b01 	rsb	fp, r6, #1
			data = buf + sizeof(buf) - data_len;
    18a2:	f106 0330 	add.w	r3, r6, #48	; 0x30
    18a6:	e7a1      	b.n	17ec <z_cbvprintf_impl+0x26c>
				prefix = (*fmt & 0x20) ? "0x" : "0X";
    18a8:	4f44      	ldr	r7, [pc, #272]	; (19bc <z_cbvprintf_impl+0x43c>)
    18aa:	e7dc      	b.n	1866 <z_cbvprintf_impl+0x2e6>
	prefix = "";
    18ac:	4f40      	ldr	r7, [pc, #256]	; (19b0 <z_cbvprintf_impl+0x430>)
    18ae:	e7db      	b.n	1868 <z_cbvprintf_impl+0x2e8>
		buftop[--i] = c + '0';
    18b0:	4666      	mov	r6, ip
		num /= base;
    18b2:	460a      	mov	r2, r1
    18b4:	4603      	mov	r3, r0
    18b6:	e7de      	b.n	1876 <z_cbvprintf_impl+0x2f6>
			data = va_arg(ap, char *);
    18b8:	f855 6b04 	ldr.w	r6, [r5], #4
			data_len = strlen(data);
    18bc:	4630      	mov	r0, r6
    18be:	f004 fef2 	bl	66a6 <strlen>
			if (precision >= 0 && data_len > precision) {
    18c2:	f1b8 0f00 	cmp.w	r8, #0
			data_len = strlen(data);
    18c6:	4683      	mov	fp, r0
			if (precision >= 0 && data_len > precision) {
    18c8:	db02      	blt.n	18d0 <z_cbvprintf_impl+0x350>
    18ca:	4540      	cmp	r0, r8
    18cc:	bfa8      	it	ge
    18ce:	46c3      	movge	fp, r8
	prefix = "";
    18d0:	4f37      	ldr	r7, [pc, #220]	; (19b0 <z_cbvprintf_impl+0x430>)
			precision = 0;
    18d2:	f04f 0800 	mov.w	r8, #0
		precision -= data_len;
    18d6:	eba8 030b 	sub.w	r3, r8, fp
		if (precision > 0) {
    18da:	2b00      	cmp	r3, #0
    18dc:	dd92      	ble.n	1804 <z_cbvprintf_impl+0x284>
			min_width -= precision;
    18de:	eba4 0408 	sub.w	r4, r4, r8
    18e2:	e7a6      	b.n	1832 <z_cbvprintf_impl+0x2b2>
			buf[0] = c;
    18e4:	f855 3b04 	ldr.w	r3, [r5], #4
    18e8:	f88d 3018 	strb.w	r3, [sp, #24]
		min_width -= data_len;
    18ec:	3c01      	subs	r4, #1
		precision -= data_len;
    18ee:	f04f 33ff 	mov.w	r3, #4294967295
			data_len = 1;
    18f2:	f04f 0b01 	mov.w	fp, #1
			data = buf;
    18f6:	ae06      	add	r6, sp, #24
    18f8:	e79a      	b.n	1830 <z_cbvprintf_impl+0x2b0>
    18fa:	46a0      	mov	r8, r4
    18fc:	e7eb      	b.n	18d6 <z_cbvprintf_impl+0x356>
    18fe:	9302      	str	r3, [sp, #8]
			while (--min_width >= 0) {
				OUTC(' ');
    1900:	9901      	ldr	r1, [sp, #4]
    1902:	2020      	movs	r0, #32
    1904:	47d0      	blx	sl
    1906:	9b02      	ldr	r3, [sp, #8]
			while (--min_width >= 0) {
    1908:	f1b8 0801 	subs.w	r8, r8, #1
    190c:	d5f7      	bpl.n	18fe <z_cbvprintf_impl+0x37e>
    190e:	ea24 72e4 	bic.w	r2, r4, r4, asr #31
    1912:	3c01      	subs	r4, #1
    1914:	4491      	add	r9, r2
    1916:	1aa4      	subs	r4, r4, r2
    1918:	46b8      	mov	r8, r7
    191a:	e006      	b.n	192a <z_cbvprintf_impl+0x3aa>
    191c:	9304      	str	r3, [sp, #16]
    191e:	9202      	str	r2, [sp, #8]
			}
		}
		while (*prefix) {
			OUTC(*prefix++);
    1920:	9901      	ldr	r1, [sp, #4]
    1922:	47d0      	blx	sl
    1924:	9a02      	ldr	r2, [sp, #8]
    1926:	9b04      	ldr	r3, [sp, #16]
    1928:	4690      	mov	r8, r2
		while (*prefix) {
    192a:	4642      	mov	r2, r8
    192c:	f812 0b01 	ldrb.w	r0, [r2], #1
    1930:	2800      	cmp	r0, #0
    1932:	d1f3      	bne.n	191c <z_cbvprintf_impl+0x39c>
    1934:	461a      	mov	r2, r3
		}
		while (--precision >= 0) {
    1936:	3a01      	subs	r2, #1
    1938:	d515      	bpl.n	1966 <z_cbvprintf_impl+0x3e6>
    193a:	2b00      	cmp	r3, #0
    193c:	bfac      	ite	ge
    193e:	ebc7 0703 	rsbge	r7, r7, r3
    1942:	427f      	neglt	r7, r7
    1944:	465b      	mov	r3, fp
			OUTC('0');
		}
		while (--data_len >= 0) {
    1946:	3b01      	subs	r3, #1
    1948:	d515      	bpl.n	1976 <z_cbvprintf_impl+0x3f6>
    194a:	f1bb 0f00 	cmp.w	fp, #0
    194e:	bfa8      	it	ge
    1950:	445f      	addge	r7, fp
    1952:	444f      	add	r7, r9
    1954:	4626      	mov	r6, r4
			OUTC(*data++);
		}
		while (--min_width >= 0) {
    1956:	3e01      	subs	r6, #1
    1958:	d514      	bpl.n	1984 <z_cbvprintf_impl+0x404>
    195a:	2c00      	cmp	r4, #0
    195c:	bfa8      	it	ge
    195e:	193f      	addge	r7, r7, r4
    1960:	eb07 0908 	add.w	r9, r7, r8
    1964:	e616      	b.n	1594 <z_cbvprintf_impl+0x14>
    1966:	9304      	str	r3, [sp, #16]
    1968:	9202      	str	r2, [sp, #8]
			OUTC('0');
    196a:	9901      	ldr	r1, [sp, #4]
    196c:	2030      	movs	r0, #48	; 0x30
    196e:	47d0      	blx	sl
    1970:	9b04      	ldr	r3, [sp, #16]
    1972:	9a02      	ldr	r2, [sp, #8]
    1974:	e7df      	b.n	1936 <z_cbvprintf_impl+0x3b6>
    1976:	9302      	str	r3, [sp, #8]
			OUTC(*data++);
    1978:	9901      	ldr	r1, [sp, #4]
    197a:	f816 0b01 	ldrb.w	r0, [r6], #1
    197e:	47d0      	blx	sl
    1980:	9b02      	ldr	r3, [sp, #8]
    1982:	e7e0      	b.n	1946 <z_cbvprintf_impl+0x3c6>
			OUTC(' ');
    1984:	9901      	ldr	r1, [sp, #4]
    1986:	2020      	movs	r0, #32
    1988:	47d0      	blx	sl
    198a:	e7e4      	b.n	1956 <z_cbvprintf_impl+0x3d6>
				padding_mode = PAD_ZERO;
    198c:	2201      	movs	r2, #1
    198e:	e6d6      	b.n	173e <z_cbvprintf_impl+0x1be>
				precision = va_arg(ap, int);
    1990:	4690      	mov	r8, r2
    1992:	e664      	b.n	165e <z_cbvprintf_impl+0xde>
    1994:	4614      	mov	r4, r2
    1996:	e662      	b.n	165e <z_cbvprintf_impl+0xde>
				length_mod = 'L';
    1998:	234c      	movs	r3, #76	; 0x4c
    199a:	e660      	b.n	165e <z_cbvprintf_impl+0xde>
		}

		goto start;
	}
}
    199c:	4648      	mov	r0, r9
    199e:	b00d      	add	sp, #52	; 0x34
    19a0:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    19a4:	00007dc9 	.word	0x00007dc9
    19a8:	00007a24 	.word	0x00007a24
    19ac:	00007a26 	.word	0x00007a26
    19b0:	000081b2 	.word	0x000081b2
    19b4:	00007a2e 	.word	0x00007a2e
    19b8:	00007a28 	.word	0x00007a28
    19bc:	00007a2b 	.word	0x00007a2b

000019c0 <sys_reboot>:
#include <zephyr/sys/printk.h>

extern void sys_arch_reboot(int type);

FUNC_NORETURN void sys_reboot(int type)
{
    19c0:	b508      	push	{r3, lr}
	__asm__ volatile(
    19c2:	f04f 0220 	mov.w	r2, #32
    19c6:	f3ef 8311 	mrs	r3, BASEPRI
    19ca:	f382 8812 	msr	BASEPRI_MAX, r2
    19ce:	f3bf 8f6f 	isb	sy
	(void)irq_lock();
	sys_clock_disable();

	sys_arch_reboot(type);
    19d2:	f000 fcd1 	bl	2378 <sys_arch_reboot>

	/* should never get here */
	printk("Failed to reboot: spinning endlessly...\n");
    19d6:	4803      	ldr	r0, [pc, #12]	; (19e4 <sys_reboot+0x24>)
    19d8:	f004 fce1 	bl	639e <printk>
 * @note In some architectures, before returning, the function unmasks interrupts
 * unconditionally.
 */
static inline void k_cpu_idle(void)
{
	arch_cpu_idle();
    19dc:	f000 f86a 	bl	1ab4 <arch_cpu_idle>
    19e0:	e7fc      	b.n	19dc <sys_reboot+0x1c>
    19e2:	bf00      	nop
    19e4:	00007a34 	.word	0x00007a34

000019e8 <z_arm_platform_init>:
	 */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r0, =SystemInit
	bx r0
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	b SystemInit
    19e8:	f001 be60 	b.w	36ac <SystemInit>

000019ec <flash_area_open>:
		user_cb(&flash_map[i], user_data);
	}
}

int flash_area_open(uint8_t id, const struct flash_area **fap)
{
    19ec:	b570      	push	{r4, r5, r6, lr}
	const struct flash_area *area;

	if (flash_map == NULL) {
    19ee:	4b11      	ldr	r3, [pc, #68]	; (1a34 <flash_area_open+0x48>)
    19f0:	681c      	ldr	r4, [r3, #0]
{
    19f2:	460d      	mov	r5, r1
	if (flash_map == NULL) {
    19f4:	b1dc      	cbz	r4, 1a2e <flash_area_open+0x42>
extern const struct flash_area *flash_map;
extern const int flash_map_entries;

static inline struct flash_area const *get_flash_area_from_id(int idx)
{
	for (int i = 0; i < flash_map_entries; i++) {
    19f6:	4b10      	ldr	r3, [pc, #64]	; (1a38 <flash_area_open+0x4c>)
    19f8:	6819      	ldr	r1, [r3, #0]
    19fa:	2300      	movs	r3, #0
    19fc:	428b      	cmp	r3, r1
    19fe:	db02      	blt.n	1a06 <flash_area_open+0x1a>
		return -EACCES;
	}

	area = get_flash_area_from_id(id);
	if (area == NULL) {
		return -ENOENT;
    1a00:	f06f 0001 	mvn.w	r0, #1
	}

	*fap = area;

	return 0;
}
    1a04:	bd70      	pop	{r4, r5, r6, pc}
		if (flash_map[i].fa_id == idx) {
    1a06:	4622      	mov	r2, r4
    1a08:	f812 6b10 	ldrb.w	r6, [r2], #16
    1a0c:	4286      	cmp	r6, r0
    1a0e:	d002      	beq.n	1a16 <flash_area_open+0x2a>
	for (int i = 0; i < flash_map_entries; i++) {
    1a10:	3301      	adds	r3, #1
    1a12:	4614      	mov	r4, r2
    1a14:	e7f2      	b.n	19fc <flash_area_open+0x10>
	if (!area->fa_dev || !device_is_ready(area->fa_dev)) {
    1a16:	68e0      	ldr	r0, [r4, #12]
    1a18:	b910      	cbnz	r0, 1a20 <flash_area_open+0x34>
		return -ENODEV;
    1a1a:	f06f 0012 	mvn.w	r0, #18
    1a1e:	e7f1      	b.n	1a04 <flash_area_open+0x18>
 */
__syscall bool device_is_ready(const struct device *dev);

static inline bool z_impl_device_is_ready(const struct device *dev)
{
	return z_device_is_ready(dev);
    1a20:	f005 fa1c 	bl	6e5c <z_device_is_ready>
	if (!area->fa_dev || !device_is_ready(area->fa_dev)) {
    1a24:	2800      	cmp	r0, #0
    1a26:	d0f8      	beq.n	1a1a <flash_area_open+0x2e>
	*fap = area;
    1a28:	602c      	str	r4, [r5, #0]
	return 0;
    1a2a:	2000      	movs	r0, #0
    1a2c:	e7ea      	b.n	1a04 <flash_area_open+0x18>
		return -EACCES;
    1a2e:	f06f 000c 	mvn.w	r0, #12
    1a32:	e7e7      	b.n	1a04 <flash_area_open+0x18>
    1a34:	2000000c 	.word	0x2000000c
    1a38:	000071f8 	.word	0x000071f8

00001a3c <flash_area_get_sectors>:

	return true;
}

int flash_area_get_sectors(int idx, uint32_t *cnt, struct flash_sector *ret)
{
    1a3c:	b570      	push	{r4, r5, r6, lr}
    1a3e:	b088      	sub	sp, #32
    1a40:	4605      	mov	r5, r0
    1a42:	460c      	mov	r4, r1
	int rc = flash_area_open(idx, &fa);
    1a44:	b2c0      	uxtb	r0, r0
    1a46:	4669      	mov	r1, sp
{
    1a48:	4616      	mov	r6, r2
	int rc = flash_area_open(idx, &fa);
    1a4a:	f7ff ffcf 	bl	19ec <flash_area_open>
	if (rc < 0 || fa == NULL) {
    1a4e:	2800      	cmp	r0, #0
    1a50:	db1b      	blt.n	1a8a <flash_area_get_sectors+0x4e>
    1a52:	9800      	ldr	r0, [sp, #0]
    1a54:	b1c8      	cbz	r0, 1a8a <flash_area_get_sectors+0x4e>
	cb_data->area_off = fa->fa_off;
    1a56:	6843      	ldr	r3, [r0, #4]
    1a58:	9302      	str	r3, [sp, #8]
	cb_data->area_len = fa->fa_size;
    1a5a:	6883      	ldr	r3, [r0, #8]
	cb_data->ret_len = *cnt;
    1a5c:	6822      	ldr	r2, [r4, #0]
	cb_data->area_idx = idx;
    1a5e:	9501      	str	r5, [sp, #4]
	cb_data->ret = ret;
    1a60:	e9cd 3603 	strd	r3, r6, [sp, #12]
	cb_data->ret_idx = 0U;
    1a64:	2300      	movs	r3, #0
	cb_data->status = 0;
    1a66:	e9cd 2306 	strd	r2, r3, [sp, #24]
	cb_data->ret_idx = 0U;
    1a6a:	9305      	str	r3, [sp, #20]
	flash_dev = fa->fa_dev;
    1a6c:	68c5      	ldr	r5, [r0, #12]
	flash_area_close(fa);
    1a6e:	f004 fd8b 	bl	6588 <flash_area_close>
	if (flash_dev == NULL) {
    1a72:	b16d      	cbz	r5, 1a90 <flash_area_get_sectors+0x54>
	flash_page_foreach(flash_dev, cb, cb_data);
    1a74:	4628      	mov	r0, r5
    1a76:	4908      	ldr	r1, [pc, #32]	; (1a98 <flash_area_get_sectors+0x5c>)
    1a78:	aa01      	add	r2, sp, #4
    1a7a:	f004 ff6f 	bl	695c <flash_page_foreach>
	if (cb_data->status == 0) {
    1a7e:	9807      	ldr	r0, [sp, #28]
    1a80:	b908      	cbnz	r0, 1a86 <flash_area_get_sectors+0x4a>
		*cnt = cb_data->ret_idx;
    1a82:	9b05      	ldr	r3, [sp, #20]
    1a84:	6023      	str	r3, [r4, #0]
	struct layout_data data;

	return flash_area_layout(idx, cnt, ret, get_sectors_cb, &data);
}
    1a86:	b008      	add	sp, #32
    1a88:	bd70      	pop	{r4, r5, r6, pc}
		return -EINVAL;
    1a8a:	f06f 0015 	mvn.w	r0, #21
    1a8e:	e7fa      	b.n	1a86 <flash_area_get_sectors+0x4a>
		return -ENODEV;
    1a90:	f06f 0012 	mvn.w	r0, #18
	return flash_area_layout(idx, cnt, ret, get_sectors_cb, &data);
    1a94:	e7f7      	b.n	1a86 <flash_area_get_sectors+0x4a>
    1a96:	bf00      	nop
    1a98:	00006627 	.word	0x00006627

00001a9c <nrf_cc3xx_platform_abort_init>:

/** @brief Function to initialize the nrf_cc3xx_platform abort APIs.
 */
void nrf_cc3xx_platform_abort_init(void)
{
	nrf_cc3xx_platform_set_abort(&apis);
    1a9c:	4801      	ldr	r0, [pc, #4]	; (1aa4 <nrf_cc3xx_platform_abort_init+0x8>)
    1a9e:	f002 bd8d 	b.w	45bc <nrf_cc3xx_platform_set_abort>
    1aa2:	bf00      	nop
    1aa4:	0000726c 	.word	0x0000726c

00001aa8 <z_arm_cpu_idle_init>:
 * void z_arm_cpu_idle_init(void);
 */

SECTION_FUNC(TEXT, z_arm_cpu_idle_init)
#if defined(CONFIG_CPU_CORTEX_M)
	ldr	r1, =_SCB_SCR
    1aa8:	4901      	ldr	r1, [pc, #4]	; (1ab0 <z_arm_cpu_idle_init+0x8>)
	movs.n	r2, #_SCR_INIT_BITS
    1aaa:	2210      	movs	r2, #16
	str	r2, [r1]
    1aac:	600a      	str	r2, [r1, #0]
#endif
	bx	lr
    1aae:	4770      	bx	lr
	ldr	r1, =_SCB_SCR
    1ab0:	e000ed10 	.word	0xe000ed10

00001ab4 <arch_cpu_idle>:
	 * before entering low power state.
	 *
	 * Set PRIMASK before configuring BASEPRI to prevent interruption
	 * before wake-up.
	 */
	cpsid	i
    1ab4:	b672      	cpsid	i

	/*
	 * Set wake-up interrupt priority to the lowest and synchronise to
	 * ensure that this is visible to the WFI instruction.
	 */
	eors.n	r0, r0
    1ab6:	4040      	eors	r0, r0
	msr	BASEPRI, r0
    1ab8:	f380 8811 	msr	BASEPRI, r0
	isb
    1abc:	f3bf 8f6f 	isb	sy

	/*
	 * Wait for all memory transactions to complete before entering low
	 * power state.
	 */
	dsb
    1ac0:	f3bf 8f4f 	dsb	sy

	/* Enter low power state */
	wfi
    1ac4:	bf30      	wfi

	/*
	 * Clear PRIMASK and flush instruction buffer to immediately service
	 * the wake-up interrupt.
	 */
	cpsie	i
    1ac6:	b662      	cpsie	i
	isb
    1ac8:	f3bf 8f6f 	isb	sy

	bx	lr
    1acc:	4770      	bx	lr
    1ace:	bf00      	nop

00001ad0 <arch_cpu_atomic_idle>:

	/*
	 * Lock PRIMASK while sleeping: wfe will still get interrupted by
	 * incoming interrupts but the CPU will not service them right away.
	 */
	cpsid	i
    1ad0:	b672      	cpsid	i
	cpsie	i
_irq_disabled:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* r1: zero, for setting BASEPRI (needs a register) */
	eors.n	r1, r1
    1ad2:	4049      	eors	r1, r1

	/* unlock BASEPRI so wfe gets interrupted by incoming interrupts */
	msr	BASEPRI, r1
    1ad4:	f381 8811 	msr	BASEPRI, r1

	wfe
    1ad8:	bf20      	wfe

	msr	BASEPRI, r0
    1ada:	f380 8811 	msr	BASEPRI, r0
	cpsie	i
    1ade:	b662      	cpsie	i
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
	bx	lr
    1ae0:	4770      	bx	lr
    1ae2:	bf00      	nop

00001ae4 <z_arm_fatal_error>:
	LOG_ERR("Faulting instruction address (r15/pc): 0x%08x",
		esf->basic.pc);
}

void z_arm_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
{
    1ae4:	b537      	push	{r0, r1, r2, r4, r5, lr}
    1ae6:	4605      	mov	r5, r0

	if (esf != NULL) {
    1ae8:	460c      	mov	r4, r1
    1aea:	b1c9      	cbz	r1, 1b20 <z_arm_fatal_error+0x3c>
	LOG_ERR("r0/a1:  0x%08x  r1/a2:  0x%08x  r2/a3:  0x%08x",
    1aec:	688b      	ldr	r3, [r1, #8]
    1aee:	9300      	str	r3, [sp, #0]
    1af0:	e9d1 2300 	ldrd	r2, r3, [r1]
    1af4:	480e      	ldr	r0, [pc, #56]	; (1b30 <z_arm_fatal_error+0x4c>)
    1af6:	2145      	movs	r1, #69	; 0x45
    1af8:	f004 fd39 	bl	656e <z_log_minimal_printk>
	LOG_ERR("r3/a4:  0x%08x r12/ip:  0x%08x r14/lr:  0x%08x",
    1afc:	6963      	ldr	r3, [r4, #20]
    1afe:	9300      	str	r3, [sp, #0]
    1b00:	e9d4 2303 	ldrd	r2, r3, [r4, #12]
    1b04:	480b      	ldr	r0, [pc, #44]	; (1b34 <z_arm_fatal_error+0x50>)
    1b06:	2145      	movs	r1, #69	; 0x45
    1b08:	f004 fd31 	bl	656e <z_log_minimal_printk>
	LOG_ERR(" xpsr:  0x%08x", esf->basic.xpsr);
    1b0c:	69e2      	ldr	r2, [r4, #28]
    1b0e:	480a      	ldr	r0, [pc, #40]	; (1b38 <z_arm_fatal_error+0x54>)
    1b10:	2145      	movs	r1, #69	; 0x45
    1b12:	f004 fd2c 	bl	656e <z_log_minimal_printk>
	LOG_ERR("Faulting instruction address (r15/pc): 0x%08x",
    1b16:	69a2      	ldr	r2, [r4, #24]
    1b18:	4808      	ldr	r0, [pc, #32]	; (1b3c <z_arm_fatal_error+0x58>)
    1b1a:	2145      	movs	r1, #69	; 0x45
    1b1c:	f004 fd27 	bl	656e <z_log_minimal_printk>
		esf_dump(esf);
	}
	z_fatal_error(reason, esf);
    1b20:	4621      	mov	r1, r4
    1b22:	4628      	mov	r0, r5
}
    1b24:	b003      	add	sp, #12
    1b26:	e8bd 4030 	ldmia.w	sp!, {r4, r5, lr}
	z_fatal_error(reason, esf);
    1b2a:	f002 bb7b 	b.w	4224 <z_fatal_error>
    1b2e:	bf00      	nop
    1b30:	00007a5d 	.word	0x00007a5d
    1b34:	00007a91 	.word	0x00007a91
    1b38:	00007ac5 	.word	0x00007ac5
    1b3c:	00007ad9 	.word	0x00007ad9

00001b40 <arch_irq_enable>:
#define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
#define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)

void arch_irq_enable(unsigned int irq)
{
	NVIC_EnableIRQ((IRQn_Type)irq);
    1b40:	b240      	sxtb	r0, r0
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
    1b42:	2800      	cmp	r0, #0
    1b44:	db07      	blt.n	1b56 <arch_irq_enable+0x16>
  {
    __COMPILER_BARRIER();
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    1b46:	4a04      	ldr	r2, [pc, #16]	; (1b58 <arch_irq_enable+0x18>)
    1b48:	0941      	lsrs	r1, r0, #5
    1b4a:	2301      	movs	r3, #1
    1b4c:	f000 001f 	and.w	r0, r0, #31
    1b50:	4083      	lsls	r3, r0
    1b52:	f842 3021 	str.w	r3, [r2, r1, lsl #2]
}
    1b56:	4770      	bx	lr
    1b58:	e000e100 	.word	0xe000e100

00001b5c <arch_irq_is_enabled>:
	NVIC_DisableIRQ((IRQn_Type)irq);
}

int arch_irq_is_enabled(unsigned int irq)
{
	return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq));
    1b5c:	4b05      	ldr	r3, [pc, #20]	; (1b74 <arch_irq_is_enabled+0x18>)
    1b5e:	0942      	lsrs	r2, r0, #5
    1b60:	f000 001f 	and.w	r0, r0, #31
    1b64:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
    1b68:	2301      	movs	r3, #1
    1b6a:	fa03 f000 	lsl.w	r0, r3, r0
}
    1b6e:	4010      	ands	r0, r2
    1b70:	4770      	bx	lr
    1b72:	bf00      	nop
    1b74:	e000e100 	.word	0xe000e100

00001b78 <z_arm_irq_priority_set>:
	 */
	__ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1),
		 "invalid priority %d for %d irq! values must be less than %lu\n",
		 prio - _IRQ_PRIO_OFFSET, irq,
		 BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
	NVIC_SetPriority((IRQn_Type)irq, prio);
    1b78:	b240      	sxtb	r0, r0
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
  if ((int32_t)(IRQn) >= 0)
    1b7a:	2800      	cmp	r0, #0
  {
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1b7c:	bfa8      	it	ge
    1b7e:	f100 4060 	addge.w	r0, r0, #3758096384	; 0xe0000000
		prio += _IRQ_PRIO_OFFSET;
    1b82:	f101 0101 	add.w	r1, r1, #1
  }
  else
  {
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1b86:	bfb8      	it	lt
    1b88:	4b06      	ldrlt	r3, [pc, #24]	; (1ba4 <z_arm_irq_priority_set+0x2c>)
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1b8a:	ea4f 1141 	mov.w	r1, r1, lsl #5
    1b8e:	bfac      	ite	ge
    1b90:	f500 4061 	addge.w	r0, r0, #57600	; 0xe100
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1b94:	f000 000f 	andlt.w	r0, r0, #15
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1b98:	b2c9      	uxtb	r1, r1
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1b9a:	bfb4      	ite	lt
    1b9c:	5419      	strblt	r1, [r3, r0]
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1b9e:	f880 1300 	strbge.w	r1, [r0, #768]	; 0x300
}
    1ba2:	4770      	bx	lr
    1ba4:	e000ed14 	.word	0xe000ed14

00001ba8 <z_SysNmiOnReset>:
_ASM_FILE_PROLOGUE

GTEXT(z_SysNmiOnReset)

SECTION_FUNC(TEXT, z_SysNmiOnReset)
    wfi
    1ba8:	bf30      	wfi
    b z_SysNmiOnReset
    1baa:	f7ff bffd 	b.w	1ba8 <z_SysNmiOnReset>
    1bae:	bf00      	nop

00001bb0 <z_arm_prep_c>:

#define VECTOR_ADDRESS ((uintptr_t)_vector_start)

static inline void relocate_vector_table(void)
{
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    1bb0:	4a14      	ldr	r2, [pc, #80]	; (1c04 <z_arm_prep_c+0x54>)
 *
 * This routine prepares for the execution of and runs C code.
 *
 */
void z_arm_prep_c(void)
{
    1bb2:	b508      	push	{r3, lr}
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    1bb4:	4b14      	ldr	r3, [pc, #80]	; (1c08 <z_arm_prep_c+0x58>)
    1bb6:	f022 027f 	bic.w	r2, r2, #127	; 0x7f
    1bba:	609a      	str	r2, [r3, #8]
  __ASM volatile ("dsb 0xF":::"memory");
    1bbc:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    1bc0:	f3bf 8f6f 	isb	sy
	SCB->CPACR &= (~(CPACR_CP10_Msk | CPACR_CP11_Msk));
    1bc4:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
    1bc8:	f422 0270 	bic.w	r2, r2, #15728640	; 0xf00000
    1bcc:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
	SCB->CPACR |= CPACR_CP10_PRIV_ACCESS | CPACR_CP11_PRIV_ACCESS;
    1bd0:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
    1bd4:	f442 02a0 	orr.w	r2, r2, #5242880	; 0x500000
    1bd8:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
	FPU->FPCCR = FPU_FPCCR_ASPEN_Msk | FPU_FPCCR_LSPEN_Msk;
    1bdc:	f04f 4240 	mov.w	r2, #3221225472	; 0xc0000000
    1be0:	f8c3 2234 	str.w	r2, [r3, #564]	; 0x234
  __ASM volatile ("dsb 0xF":::"memory");
    1be4:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    1be8:	f3bf 8f6f 	isb	sy
     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
#if __has_builtin(__builtin_arm_set_fpscr)
// Re-enable using built-in when GCC has been fixed
// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
  __builtin_arm_set_fpscr(fpscr);
    1bec:	2300      	movs	r3, #0
    1bee:	eee1 3a10 	vmsr	fpscr, r3
	relocate_vector_table();
#if defined(CONFIG_CPU_HAS_FPU)
	z_arm_floating_point_init();
#endif
	z_bss_zero();
    1bf2:	f002 fb8f 	bl	4314 <z_bss_zero>
	z_data_copy();
    1bf6:	f002 fbd5 	bl	43a4 <z_data_copy>
#if ((defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)) && defined(CONFIG_INIT_STACKS))
	z_arm_init_stacks();
#endif
	z_arm_interrupt_init();
    1bfa:	f000 fa61 	bl	20c0 <z_arm_interrupt_init>
	z_cstart();
    1bfe:	f002 fb95 	bl	432c <z_cstart>
    1c02:	bf00      	nop
    1c04:	00000000 	.word	0x00000000
    1c08:	e000ed00 	.word	0xe000ed00

00001c0c <z_arm_svc>:
  bne _stack_frame_endif
_stack_frame_msp:
  mrs r0, MSP
_stack_frame_endif:
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    tst lr, #_EXC_RETURN_SPSEL_Msk /* did we come from thread mode ? */
    1c0c:	f01e 0f04 	tst.w	lr, #4
    ite eq  /* if zero (equal), came from handler mode */
    1c10:	bf0c      	ite	eq
        mrseq r0, MSP   /* handler mode, stack frame is on MSP */
    1c12:	f3ef 8008 	mrseq	r0, MSP
        mrsne r0, PSP   /* thread mode, stack frame is on PSP */
    1c16:	f3ef 8009 	mrsne	r0, PSP
#endif


    /* Figure out what SVC call number was invoked */

    ldr r1, [r0, #24]   /* grab address of PC from stack frame */
    1c1a:	6981      	ldr	r1, [r0, #24]
     */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    subs r1, r1, #2
    ldrb r1, [r1]
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    ldrb r1, [r1, #-2]
    1c1c:	f811 1c02 	ldrb.w	r1, [r1, #-2]
#endif
    bne _oops

#endif /* CONFIG_USERSPACE */

    cmp r1, #2
    1c20:	2902      	cmp	r1, #2
    beq _oops
    1c22:	d0ff      	beq.n	1c24 <_oops>

00001c24 <_oops>:
    /* exception return is done in z_arm_int_exit() */
    b z_arm_int_exit
#endif

_oops:
    push {r0, lr}
    1c24:	b501      	push	{r0, lr}
    push {r1, r2}
    push {r4-r11}
    mov  r1, sp /* pointer to _callee_saved_t */
#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
    bl z_do_kernel_oops
    1c26:	f004 fd25 	bl	6674 <z_do_kernel_oops>
     * the MSP to its value prior to entering the function
     */
    add sp, #40
#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
    pop {r0, pc}
    1c2a:	bd01      	pop	{r0, pc}

00001c2c <z_check_thread_stack_fail>:
			fault_addr, psp)) {
		/* Thread stack corruption */
		return thread->stack_info.start;
	}
#else
	if (IS_MPU_GUARD_VIOLATION((uint32_t)z_main_stack,
    1c2c:	f110 0f16 	cmn.w	r0, #22
    1c30:	4b07      	ldr	r3, [pc, #28]	; (1c50 <z_check_thread_stack_fail+0x24>)
    1c32:	d008      	beq.n	1c46 <z_check_thread_stack_fail+0x1a>
    1c34:	4298      	cmp	r0, r3
    1c36:	d308      	bcc.n	1c4a <z_check_thread_stack_fail+0x1e>
    1c38:	3340      	adds	r3, #64	; 0x40
    1c3a:	4283      	cmp	r3, r0
    1c3c:	d905      	bls.n	1c4a <z_check_thread_stack_fail+0x1e>
    1c3e:	428b      	cmp	r3, r1
    1c40:	d903      	bls.n	1c4a <z_check_thread_stack_fail+0x1e>
			guard_len,
			fault_addr, psp)) {
		/* Thread stack corruption */
		return (uint32_t)Z_THREAD_STACK_BUFFER(z_main_stack);
    1c42:	4804      	ldr	r0, [pc, #16]	; (1c54 <z_check_thread_stack_fail+0x28>)
    1c44:	4770      	bx	lr
	if (IS_MPU_GUARD_VIOLATION((uint32_t)z_main_stack,
    1c46:	3340      	adds	r3, #64	; 0x40
    1c48:	e7f9      	b.n	1c3e <z_check_thread_stack_fail+0x12>
	}
#endif
#endif /* CONFIG_USERSPACE */

	return 0;
    1c4a:	2000      	movs	r0, #0
}
    1c4c:	4770      	bx	lr
    1c4e:	bf00      	nop
    1c50:	20001d40 	.word	0x20001d40
    1c54:	20001d80 	.word	0x20001d80

00001c58 <z_arm_switch_to_main_no_multithreading>:

#if !defined(CONFIG_MULTITHREADING) && defined(CONFIG_CPU_CORTEX_M)

FUNC_NORETURN void z_arm_switch_to_main_no_multithreading(
	k_thread_entry_t main_entry, void *p1, void *p2, void *p3)
{
    1c58:	4604      	mov	r4, r0
    1c5a:	4608      	mov	r0, r1
    1c5c:	4611      	mov	r1, r2
    1c5e:	461a      	mov	r2, r3
    1c60:	2300      	movs	r3, #0
    1c62:	eee1 3a10 	vmsr	fpscr, r3
	 */
	register void *p1_inreg __asm__("r0") = p1;
	register void *p2_inreg __asm__("r1") = p2;
	register void *p3_inreg __asm__("r2") = p3;

	__asm__ volatile (
    1c66:	4b08      	ldr	r3, [pc, #32]	; (1c88 <loop+0x2>)
    1c68:	2520      	movs	r5, #32
    1c6a:	f383 8809 	msr	PSP, r3
    1c6e:	b663      	cpsie	if
    1c70:	f04f 0300 	mov.w	r3, #0
    1c74:	f383 8811 	msr	BASEPRI, r3
    1c78:	f3bf 8f6f 	isb	sy
    1c7c:	47a0      	blx	r4
    1c7e:	f385 8811 	msr	BASEPRI, r5
    1c82:	f3bf 8f6f 	isb	sy

00001c86 <loop>:
    1c86:	e7fe      	b.n	1c86 <loop>
	, [_psplim]"r" (psplim)
#endif
	:
	);

	CODE_UNREACHABLE; /* LCOV_EXCL_LINE */
    1c88:	20004580 	.word	0x20004580

00001c8c <_isr_wrapper>:
 *
 */
SECTION_FUNC(TEXT, _isr_wrapper)

#if defined(CONFIG_CPU_CORTEX_M)
	push {r0,lr}		/* r0, lr are now the first items on the stack */
    1c8c:	b501      	push	{r0, lr}
#endif

#endif /* CONFIG_PM */

#if defined(CONFIG_CPU_CORTEX_M)
	mrs r0, IPSR	/* get exception number */
    1c8e:	f3ef 8005 	mrs	r0, IPSR
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r1, =16
	subs r0, r1	/* get IRQ number */
	lsls r0, #3	/* table is 8-byte wide */
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	sub r0, r0, #16	/* get IRQ number */
    1c92:	f1a0 0010 	sub.w	r0, r0, #16
	lsl r0, r0, #3	/* table is 8-byte wide */
    1c96:	ea4f 00c0 	mov.w	r0, r0, lsl #3
	lsl r1, r1, #3
	cmp r0, r1
	bge spurious_continue
#endif /* !CONFIG_CPU_CORTEX_M */

	ldr r1, =_sw_isr_table
    1c9a:	4904      	ldr	r1, [pc, #16]	; (1cac <_isr_wrapper+0x20>)
	add r1, r1, r0	/* table entry: ISRs must have their MSB set to stay
    1c9c:	4401      	add	r1, r0
			 * in thumb mode */

	ldm r1!,{r0,r3}	/* arg in r0, ISR in r3 */
    1c9e:	c909      	ldmia	r1!, {r0, r3}
	blx r3		/* call ISR */
    1ca0:	4798      	blx	r3

#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	pop {r0, r3}
	mov lr, r3
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	pop {r0, lr}
    1ca2:	e8bd 4001 	ldmia.w	sp!, {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

	/* Use 'bx' instead of 'b' because 'bx' can jump further, and use
	 * 'bx' instead of 'blx' because exception return is done in
	 * z_arm_int_exit() */
	ldr r1, =z_arm_int_exit
    1ca6:	4902      	ldr	r1, [pc, #8]	; (1cb0 <_isr_wrapper+0x24>)
	bx r1
    1ca8:	4708      	bx	r1
    1caa:	0000      	.short	0x0000
	ldr r1, =_sw_isr_table
    1cac:	00006fe0 	.word	0x00006fe0
	ldr r1, =z_arm_int_exit
    1cb0:	00001cb5 	.word	0x00001cb5

00001cb4 <z_arm_exc_exit>:
#else
	pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_STACK_SENTINEL */

	bx lr
    1cb4:	4770      	bx	lr
    1cb6:	bf00      	nop

00001cb8 <mem_manage_fault>:
 *
 * @return error code to identify the fatal error reason
 */
static uint32_t mem_manage_fault(z_arch_esf_t *esf, int from_hard_fault,
			      bool *recoverable)
{
    1cb8:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	uint32_t mmfar = -EINVAL;

	PR_FAULT_INFO("***** MPU FAULT *****");

	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
    1cbc:	4c32      	ldr	r4, [pc, #200]	; (1d88 <mem_manage_fault+0xd0>)
{
    1cbe:	4607      	mov	r7, r0
    1cc0:	4688      	mov	r8, r1
	PR_FAULT_INFO("***** MPU FAULT *****");
    1cc2:	4832      	ldr	r0, [pc, #200]	; (1d8c <mem_manage_fault+0xd4>)
    1cc4:	2145      	movs	r1, #69	; 0x45
{
    1cc6:	4615      	mov	r5, r2
	PR_FAULT_INFO("***** MPU FAULT *****");
    1cc8:	f004 fc51 	bl	656e <z_log_minimal_printk>
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
    1ccc:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    1cce:	06de      	lsls	r6, r3, #27
    1cd0:	d503      	bpl.n	1cda <mem_manage_fault+0x22>
		PR_FAULT_INFO("  Stacking error (context area might be"
    1cd2:	482f      	ldr	r0, [pc, #188]	; (1d90 <mem_manage_fault+0xd8>)
    1cd4:	2145      	movs	r1, #69	; 0x45
    1cd6:	f004 fc4a 	bl	656e <z_log_minimal_printk>
			" not valid)");
	}
	if ((SCB->CFSR & SCB_CFSR_MUNSTKERR_Msk) != 0) {
    1cda:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    1cdc:	0718      	lsls	r0, r3, #28
    1cde:	d503      	bpl.n	1ce8 <mem_manage_fault+0x30>
		PR_FAULT_INFO("  Unstacking error");
    1ce0:	482c      	ldr	r0, [pc, #176]	; (1d94 <mem_manage_fault+0xdc>)
    1ce2:	2145      	movs	r1, #69	; 0x45
    1ce4:	f004 fc43 	bl	656e <z_log_minimal_printk>
	}
	if ((SCB->CFSR & SCB_CFSR_DACCVIOL_Msk) != 0) {
    1ce8:	4c27      	ldr	r4, [pc, #156]	; (1d88 <mem_manage_fault+0xd0>)
    1cea:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    1cec:	0799      	lsls	r1, r3, #30
    1cee:	d428      	bmi.n	1d42 <mem_manage_fault+0x8a>
	uint32_t mmfar = -EINVAL;
    1cf0:	f06f 0615 	mvn.w	r6, #21
				/* clear SCB_MMAR[VALID] to reset */
				SCB->CFSR &= ~SCB_CFSR_MMARVALID_Msk;
			}
		}
	}
	if ((SCB->CFSR & SCB_CFSR_IACCVIOL_Msk) != 0) {
    1cf4:	4c24      	ldr	r4, [pc, #144]	; (1d88 <mem_manage_fault+0xd0>)
    1cf6:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    1cf8:	07db      	lsls	r3, r3, #31
    1cfa:	d503      	bpl.n	1d04 <mem_manage_fault+0x4c>
		PR_FAULT_INFO("  Instruction Access Violation");
    1cfc:	4826      	ldr	r0, [pc, #152]	; (1d98 <mem_manage_fault+0xe0>)
    1cfe:	2145      	movs	r1, #69	; 0x45
    1d00:	f004 fc35 	bl	656e <z_log_minimal_printk>
	}
#if defined(CONFIG_ARMV7_M_ARMV8_M_FP)
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    1d04:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    1d06:	069c      	lsls	r4, r3, #26
    1d08:	d503      	bpl.n	1d12 <mem_manage_fault+0x5a>
		PR_FAULT_INFO(
    1d0a:	4824      	ldr	r0, [pc, #144]	; (1d9c <mem_manage_fault+0xe4>)
    1d0c:	2145      	movs	r1, #69	; 0x45
    1d0e:	f004 fc2e 	bl	656e <z_log_minimal_printk>
	 * crossed into an area beyond the thread stack.]
	 *
	 * Data Access Violation errors may or may not be caused by
	 * thread stack overflows.
	 */
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) ||
    1d12:	4c1d      	ldr	r4, [pc, #116]	; (1d88 <mem_manage_fault+0xd0>)
    1d14:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    1d16:	06d8      	lsls	r0, r3, #27
    1d18:	d428      	bmi.n	1d6c <mem_manage_fault+0xb4>
		(SCB->CFSR & SCB_CFSR_DACCVIOL_Msk)) {
    1d1a:	6aa3      	ldr	r3, [r4, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) ||
    1d1c:	0799      	lsls	r1, r3, #30
    1d1e:	d425      	bmi.n	1d6c <mem_manage_fault+0xb4>
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    1d20:	2000      	movs	r0, #0
	 * lazy stacking Memory Manage fault. At the time of writing, this
	 * can happen when printing.  If that's true, we should clear the
	 * pending flag in addition to the clearing the reason for the fault
	 */
#if defined(CONFIG_ARMV7_M_ARMV8_M_FP)
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    1d22:	6aa3      	ldr	r3, [r4, #40]	; 0x28
		SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTPENDED_Msk;
	}
#endif /* CONFIG_ARMV7_M_ARMV8_M_FP */

	/* clear MMFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_MEMFAULTSR_Msk;
    1d24:	4a18      	ldr	r2, [pc, #96]	; (1d88 <mem_manage_fault+0xd0>)
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    1d26:	069b      	lsls	r3, r3, #26
		SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTPENDED_Msk;
    1d28:	bf42      	ittt	mi
    1d2a:	6a63      	ldrmi	r3, [r4, #36]	; 0x24
    1d2c:	f423 5300 	bicmi.w	r3, r3, #8192	; 0x2000
    1d30:	6263      	strmi	r3, [r4, #36]	; 0x24
	SCB->CFSR |= SCB_CFSR_MEMFAULTSR_Msk;
    1d32:	6a93      	ldr	r3, [r2, #40]	; 0x28
    1d34:	f043 03ff 	orr.w	r3, r3, #255	; 0xff
    1d38:	6293      	str	r3, [r2, #40]	; 0x28

	/* Assess whether system shall ignore/recover from this MPU fault. */
	*recoverable = memory_fault_recoverable(esf, true);
    1d3a:	2300      	movs	r3, #0
    1d3c:	702b      	strb	r3, [r5, #0]

	return reason;
}
    1d3e:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		PR_FAULT_INFO("  Data Access Violation");
    1d42:	4817      	ldr	r0, [pc, #92]	; (1da0 <mem_manage_fault+0xe8>)
    1d44:	2145      	movs	r1, #69	; 0x45
    1d46:	f004 fc12 	bl	656e <z_log_minimal_printk>
		uint32_t temp = SCB->MMFAR;
    1d4a:	6b66      	ldr	r6, [r4, #52]	; 0x34
		if ((SCB->CFSR & SCB_CFSR_MMARVALID_Msk) != 0) {
    1d4c:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    1d4e:	061a      	lsls	r2, r3, #24
    1d50:	d5ce      	bpl.n	1cf0 <mem_manage_fault+0x38>
			PR_EXC("  MMFAR Address: 0x%x", mmfar);
    1d52:	4814      	ldr	r0, [pc, #80]	; (1da4 <mem_manage_fault+0xec>)
    1d54:	4632      	mov	r2, r6
    1d56:	2145      	movs	r1, #69	; 0x45
    1d58:	f004 fc09 	bl	656e <z_log_minimal_printk>
			if (from_hard_fault != 0) {
    1d5c:	f1b8 0f00 	cmp.w	r8, #0
    1d60:	d0c8      	beq.n	1cf4 <mem_manage_fault+0x3c>
				SCB->CFSR &= ~SCB_CFSR_MMARVALID_Msk;
    1d62:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    1d64:	f023 0380 	bic.w	r3, r3, #128	; 0x80
    1d68:	62a3      	str	r3, [r4, #40]	; 0x28
    1d6a:	e7c3      	b.n	1cf4 <mem_manage_fault+0x3c>
		if (SCB->ICSR & SCB_ICSR_RETTOBASE_Msk) {
    1d6c:	6863      	ldr	r3, [r4, #4]
    1d6e:	051a      	lsls	r2, r3, #20
    1d70:	d5d6      	bpl.n	1d20 <mem_manage_fault+0x68>
			uint32_t min_stack_ptr = z_check_thread_stack_fail(mmfar,
    1d72:	4639      	mov	r1, r7
    1d74:	4630      	mov	r0, r6
    1d76:	f7ff ff59 	bl	1c2c <z_check_thread_stack_fail>
			if (min_stack_ptr) {
    1d7a:	2800      	cmp	r0, #0
    1d7c:	d0d0      	beq.n	1d20 <mem_manage_fault+0x68>
  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
    1d7e:	f380 8809 	msr	PSP, r0
				reason = K_ERR_STACK_CHK_FAIL;
    1d82:	2002      	movs	r0, #2
    1d84:	e7cd      	b.n	1d22 <mem_manage_fault+0x6a>
    1d86:	bf00      	nop
    1d88:	e000ed00 	.word	0xe000ed00
    1d8c:	00007b0c 	.word	0x00007b0c
    1d90:	00007b27 	.word	0x00007b27
    1d94:	00007b5f 	.word	0x00007b5f
    1d98:	00007baf 	.word	0x00007baf
    1d9c:	00007bd3 	.word	0x00007bd3
    1da0:	00007b77 	.word	0x00007b77
    1da4:	00007b94 	.word	0x00007b94

00001da8 <usage_fault.constprop.0>:
 *
 * See z_arm_fault_dump() for example.
 *
 * @return error code to identify the fatal error reason
 */
static uint32_t usage_fault(const z_arch_esf_t *esf)
    1da8:	b510      	push	{r4, lr}
	uint32_t reason = K_ERR_CPU_EXCEPTION;

	PR_FAULT_INFO("***** USAGE FAULT *****");

	/* bits are sticky: they stack and must be reset */
	if ((SCB->CFSR & SCB_CFSR_DIVBYZERO_Msk) != 0) {
    1daa:	4c1d      	ldr	r4, [pc, #116]	; (1e20 <usage_fault.constprop.0+0x78>)
	PR_FAULT_INFO("***** USAGE FAULT *****");
    1dac:	481d      	ldr	r0, [pc, #116]	; (1e24 <usage_fault.constprop.0+0x7c>)
    1dae:	2145      	movs	r1, #69	; 0x45
    1db0:	f004 fbdd 	bl	656e <z_log_minimal_printk>
	if ((SCB->CFSR & SCB_CFSR_DIVBYZERO_Msk) != 0) {
    1db4:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    1db6:	019b      	lsls	r3, r3, #6
    1db8:	d503      	bpl.n	1dc2 <usage_fault.constprop.0+0x1a>
		PR_FAULT_INFO("  Division by zero");
    1dba:	481b      	ldr	r0, [pc, #108]	; (1e28 <usage_fault.constprop.0+0x80>)
    1dbc:	2145      	movs	r1, #69	; 0x45
    1dbe:	f004 fbd6 	bl	656e <z_log_minimal_printk>
	}
	if ((SCB->CFSR & SCB_CFSR_UNALIGNED_Msk) != 0) {
    1dc2:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    1dc4:	01dc      	lsls	r4, r3, #7
    1dc6:	d503      	bpl.n	1dd0 <usage_fault.constprop.0+0x28>
		PR_FAULT_INFO("  Unaligned memory access");
    1dc8:	4818      	ldr	r0, [pc, #96]	; (1e2c <usage_fault.constprop.0+0x84>)
    1dca:	2145      	movs	r1, #69	; 0x45
    1dcc:	f004 fbcf 	bl	656e <z_log_minimal_printk>
		 */
		reason = K_ERR_STACK_CHK_FAIL;
#endif /* CONFIG_BUILTIN_STACK_GUARD */
	}
#endif /* CONFIG_ARMV8_M_MAINLINE */
	if ((SCB->CFSR & SCB_CFSR_NOCP_Msk) != 0) {
    1dd0:	4c13      	ldr	r4, [pc, #76]	; (1e20 <usage_fault.constprop.0+0x78>)
    1dd2:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    1dd4:	0318      	lsls	r0, r3, #12
    1dd6:	d503      	bpl.n	1de0 <usage_fault.constprop.0+0x38>
		PR_FAULT_INFO("  No coprocessor instructions");
    1dd8:	4815      	ldr	r0, [pc, #84]	; (1e30 <usage_fault.constprop.0+0x88>)
    1dda:	2145      	movs	r1, #69	; 0x45
    1ddc:	f004 fbc7 	bl	656e <z_log_minimal_printk>
	}
	if ((SCB->CFSR & SCB_CFSR_INVPC_Msk) != 0) {
    1de0:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    1de2:	0359      	lsls	r1, r3, #13
    1de4:	d503      	bpl.n	1dee <usage_fault.constprop.0+0x46>
		PR_FAULT_INFO("  Illegal load of EXC_RETURN into PC");
    1de6:	4813      	ldr	r0, [pc, #76]	; (1e34 <usage_fault.constprop.0+0x8c>)
    1de8:	2145      	movs	r1, #69	; 0x45
    1dea:	f004 fbc0 	bl	656e <z_log_minimal_printk>
	}
	if ((SCB->CFSR & SCB_CFSR_INVSTATE_Msk) != 0) {
    1dee:	4c0c      	ldr	r4, [pc, #48]	; (1e20 <usage_fault.constprop.0+0x78>)
    1df0:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    1df2:	039a      	lsls	r2, r3, #14
    1df4:	d503      	bpl.n	1dfe <usage_fault.constprop.0+0x56>
		PR_FAULT_INFO("  Illegal use of the EPSR");
    1df6:	4810      	ldr	r0, [pc, #64]	; (1e38 <usage_fault.constprop.0+0x90>)
    1df8:	2145      	movs	r1, #69	; 0x45
    1dfa:	f004 fbb8 	bl	656e <z_log_minimal_printk>
	}
	if ((SCB->CFSR & SCB_CFSR_UNDEFINSTR_Msk) != 0) {
    1dfe:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    1e00:	03db      	lsls	r3, r3, #15
    1e02:	d503      	bpl.n	1e0c <usage_fault.constprop.0+0x64>
		PR_FAULT_INFO("  Attempt to execute undefined instruction");
    1e04:	480d      	ldr	r0, [pc, #52]	; (1e3c <usage_fault.constprop.0+0x94>)
    1e06:	2145      	movs	r1, #69	; 0x45
    1e08:	f004 fbb1 	bl	656e <z_log_minimal_printk>
	}

	/* clear UFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    1e0c:	4a04      	ldr	r2, [pc, #16]	; (1e20 <usage_fault.constprop.0+0x78>)
    1e0e:	6a93      	ldr	r3, [r2, #40]	; 0x28
    1e10:	ea6f 4303 	mvn.w	r3, r3, lsl #16
    1e14:	ea6f 4313 	mvn.w	r3, r3, lsr #16
    1e18:	6293      	str	r3, [r2, #40]	; 0x28

	return reason;
}
    1e1a:	2000      	movs	r0, #0
    1e1c:	bd10      	pop	{r4, pc}
    1e1e:	bf00      	nop
    1e20:	e000ed00 	.word	0xe000ed00
    1e24:	00007c07 	.word	0x00007c07
    1e28:	00007c24 	.word	0x00007c24
    1e2c:	00007c3c 	.word	0x00007c3c
    1e30:	00007c5b 	.word	0x00007c5b
    1e34:	00007c7e 	.word	0x00007c7e
    1e38:	00007ca8 	.word	0x00007ca8
    1e3c:	00007cc7 	.word	0x00007cc7

00001e40 <bus_fault.constprop.0>:
static int bus_fault(z_arch_esf_t *esf, int from_hard_fault, bool *recoverable)
    1e40:	b570      	push	{r4, r5, r6, lr}
	if (SCB->CFSR & SCB_CFSR_STKERR_Msk) {
    1e42:	4c23      	ldr	r4, [pc, #140]	; (1ed0 <bus_fault.constprop.0+0x90>)
static int bus_fault(z_arch_esf_t *esf, int from_hard_fault, bool *recoverable)
    1e44:	4606      	mov	r6, r0
    1e46:	460d      	mov	r5, r1
	PR_FAULT_INFO("***** BUS FAULT *****");
    1e48:	4822      	ldr	r0, [pc, #136]	; (1ed4 <bus_fault.constprop.0+0x94>)
    1e4a:	2145      	movs	r1, #69	; 0x45
    1e4c:	f004 fb8f 	bl	656e <z_log_minimal_printk>
	if (SCB->CFSR & SCB_CFSR_STKERR_Msk) {
    1e50:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    1e52:	04d9      	lsls	r1, r3, #19
    1e54:	d503      	bpl.n	1e5e <bus_fault.constprop.0+0x1e>
		PR_FAULT_INFO("  Stacking error");
    1e56:	4820      	ldr	r0, [pc, #128]	; (1ed8 <bus_fault.constprop.0+0x98>)
    1e58:	2145      	movs	r1, #69	; 0x45
    1e5a:	f004 fb88 	bl	656e <z_log_minimal_printk>
	if (SCB->CFSR & SCB_CFSR_UNSTKERR_Msk) {
    1e5e:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    1e60:	051a      	lsls	r2, r3, #20
    1e62:	d503      	bpl.n	1e6c <bus_fault.constprop.0+0x2c>
		PR_FAULT_INFO("  Unstacking error");
    1e64:	481d      	ldr	r0, [pc, #116]	; (1edc <bus_fault.constprop.0+0x9c>)
    1e66:	2145      	movs	r1, #69	; 0x45
    1e68:	f004 fb81 	bl	656e <z_log_minimal_printk>
	if (SCB->CFSR & SCB_CFSR_PRECISERR_Msk) {
    1e6c:	4c18      	ldr	r4, [pc, #96]	; (1ed0 <bus_fault.constprop.0+0x90>)
    1e6e:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    1e70:	059b      	lsls	r3, r3, #22
    1e72:	d510      	bpl.n	1e96 <bus_fault.constprop.0+0x56>
		PR_FAULT_INFO("  Precise data bus error");
    1e74:	481a      	ldr	r0, [pc, #104]	; (1ee0 <bus_fault.constprop.0+0xa0>)
    1e76:	2145      	movs	r1, #69	; 0x45
    1e78:	f004 fb79 	bl	656e <z_log_minimal_printk>
		STORE_xFAR(bfar, SCB->BFAR);
    1e7c:	6ba2      	ldr	r2, [r4, #56]	; 0x38
		if ((SCB->CFSR & SCB_CFSR_BFARVALID_Msk) != 0) {
    1e7e:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    1e80:	0418      	lsls	r0, r3, #16
    1e82:	d508      	bpl.n	1e96 <bus_fault.constprop.0+0x56>
			PR_EXC("  BFAR Address: 0x%x", bfar);
    1e84:	4817      	ldr	r0, [pc, #92]	; (1ee4 <bus_fault.constprop.0+0xa4>)
    1e86:	2145      	movs	r1, #69	; 0x45
    1e88:	f004 fb71 	bl	656e <z_log_minimal_printk>
			if (from_hard_fault != 0) {
    1e8c:	b11e      	cbz	r6, 1e96 <bus_fault.constprop.0+0x56>
				SCB->CFSR &= ~SCB_CFSR_BFARVALID_Msk;
    1e8e:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    1e90:	f423 4300 	bic.w	r3, r3, #32768	; 0x8000
    1e94:	62a3      	str	r3, [r4, #40]	; 0x28
	if (SCB->CFSR & SCB_CFSR_IMPRECISERR_Msk) {
    1e96:	4c0e      	ldr	r4, [pc, #56]	; (1ed0 <bus_fault.constprop.0+0x90>)
    1e98:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    1e9a:	0559      	lsls	r1, r3, #21
    1e9c:	d503      	bpl.n	1ea6 <bus_fault.constprop.0+0x66>
		PR_FAULT_INFO("  Imprecise data bus error");
    1e9e:	4812      	ldr	r0, [pc, #72]	; (1ee8 <bus_fault.constprop.0+0xa8>)
    1ea0:	2145      	movs	r1, #69	; 0x45
    1ea2:	f004 fb64 	bl	656e <z_log_minimal_printk>
	if ((SCB->CFSR & SCB_CFSR_IBUSERR_Msk) != 0) {
    1ea6:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    1ea8:	05da      	lsls	r2, r3, #23
    1eaa:	d50b      	bpl.n	1ec4 <bus_fault.constprop.0+0x84>
		PR_FAULT_INFO("  Instruction bus error");
    1eac:	480f      	ldr	r0, [pc, #60]	; (1eec <bus_fault.constprop.0+0xac>)
    1eae:	2145      	movs	r1, #69	; 0x45
		PR_FAULT_INFO("  Floating-point lazy state preservation error");
    1eb0:	f004 fb5d 	bl	656e <z_log_minimal_printk>
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
    1eb4:	4a06      	ldr	r2, [pc, #24]	; (1ed0 <bus_fault.constprop.0+0x90>)
    1eb6:	6a93      	ldr	r3, [r2, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf, true);
    1eb8:	2000      	movs	r0, #0
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
    1eba:	f443 437f 	orr.w	r3, r3, #65280	; 0xff00
    1ebe:	6293      	str	r3, [r2, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf, true);
    1ec0:	7028      	strb	r0, [r5, #0]
}
    1ec2:	bd70      	pop	{r4, r5, r6, pc}
	} else if (SCB->CFSR & SCB_CFSR_LSPERR_Msk) {
    1ec4:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    1ec6:	049b      	lsls	r3, r3, #18
    1ec8:	d5f4      	bpl.n	1eb4 <bus_fault.constprop.0+0x74>
		PR_FAULT_INFO("  Floating-point lazy state preservation error");
    1eca:	4809      	ldr	r0, [pc, #36]	; (1ef0 <bus_fault.constprop.0+0xb0>)
    1ecc:	2145      	movs	r1, #69	; 0x45
    1ece:	e7ef      	b.n	1eb0 <bus_fault.constprop.0+0x70>
    1ed0:	e000ed00 	.word	0xe000ed00
    1ed4:	00007cf7 	.word	0x00007cf7
    1ed8:	00007d12 	.word	0x00007d12
    1edc:	00007b5f 	.word	0x00007b5f
    1ee0:	00007d28 	.word	0x00007d28
    1ee4:	00007d46 	.word	0x00007d46
    1ee8:	00007d60 	.word	0x00007d60
    1eec:	00007d80 	.word	0x00007d80
    1ef0:	00007bd3 	.word	0x00007bd3

00001ef4 <z_arm_fault>:
 * @param callee_regs Callee-saved registers (R4-R11, PSP)
 *
 */
void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return,
	_callee_saved_t *callee_regs)
{
    1ef4:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    1ef8:	4b5d      	ldr	r3, [pc, #372]	; (2070 <z_arm_fault+0x17c>)
    1efa:	685f      	ldr	r7, [r3, #4]
{
    1efc:	b08a      	sub	sp, #40	; 0x28
    1efe:	4605      	mov	r5, r0
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    1f00:	f3c7 0408 	ubfx	r4, r7, #0, #9
	__asm__ volatile(
    1f04:	2600      	movs	r6, #0
    1f06:	f386 8811 	msr	BASEPRI, r6
    1f0a:	f3bf 8f6f 	isb	sy
	if ((exc_return & EXC_RETURN_INDICATOR_PREFIX) !=
    1f0e:	f002 437f 	and.w	r3, r2, #4278190080	; 0xff000000
    1f12:	f1b3 4f7f 	cmp.w	r3, #4278190080	; 0xff000000
    1f16:	d107      	bne.n	1f28 <z_arm_fault+0x34>
	if ((exc_return & EXC_RETURN_MODE_THREAD) &&
    1f18:	f002 030c 	and.w	r3, r2, #12
    1f1c:	2b08      	cmp	r3, #8
    1f1e:	d114      	bne.n	1f4a <z_arm_fault+0x56>
		PR_EXC("SPSEL in thread mode does not indicate PSP");
    1f20:	4854      	ldr	r0, [pc, #336]	; (2074 <z_arm_fault+0x180>)
    1f22:	2145      	movs	r1, #69	; 0x45
    1f24:	f004 fb23 	bl	656e <z_log_minimal_printk>
	*nested_exc = false;
    1f28:	2600      	movs	r6, #0
		return NULL;
    1f2a:	4635      	mov	r5, r6
	*recoverable = false;
    1f2c:	f04f 0800 	mov.w	r8, #0
	switch (fault) {
    1f30:	1ee3      	subs	r3, r4, #3
	*recoverable = false;
    1f32:	f88d 8007 	strb.w	r8, [sp, #7]
	switch (fault) {
    1f36:	2b09      	cmp	r3, #9
    1f38:	f200 8087 	bhi.w	204a <z_arm_fault+0x156>
    1f3c:	e8df f003 	tbb	[pc, r3]
    1f40:	767e7a0a 	.word	0x767e7a0a
    1f44:	85858585 	.word	0x85858585
    1f48:	8285      	.short	0x8285
		if (exc_return & EXC_RETURN_MODE_THREAD) {
    1f4a:	0710      	lsls	r0, r2, #28
			ptr_esf =  (z_arch_esf_t *)psp;
    1f4c:	bf4c      	ite	mi
    1f4e:	460d      	movmi	r5, r1
			*nested_exc = true;
    1f50:	2601      	movpl	r6, #1
    1f52:	e7eb      	b.n	1f2c <z_arm_fault+0x38>
	PR_FAULT_INFO("***** HARD FAULT *****");
    1f54:	4848      	ldr	r0, [pc, #288]	; (2078 <z_arm_fault+0x184>)
	if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk) != 0) {
    1f56:	4c46      	ldr	r4, [pc, #280]	; (2070 <z_arm_fault+0x17c>)
	PR_FAULT_INFO("***** HARD FAULT *****");
    1f58:	2145      	movs	r1, #69	; 0x45
    1f5a:	f004 fb08 	bl	656e <z_log_minimal_printk>
	*recoverable = false;
    1f5e:	f88d 8007 	strb.w	r8, [sp, #7]
	if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk) != 0) {
    1f62:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
    1f64:	079a      	lsls	r2, r3, #30
    1f66:	d505      	bpl.n	1f74 <z_arm_fault+0x80>
		PR_EXC("  Bus fault on vector table read");
    1f68:	4844      	ldr	r0, [pc, #272]	; (207c <z_arm_fault+0x188>)
    1f6a:	2145      	movs	r1, #69	; 0x45
	PR_FAULT_INFO(
    1f6c:	f004 faff 	bl	656e <z_log_minimal_printk>
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    1f70:	2400      	movs	r4, #0
    1f72:	e033      	b.n	1fdc <z_arm_fault+0xe8>
	} else if ((SCB->HFSR & SCB_HFSR_DEBUGEVT_Msk) != 0) {
    1f74:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
    1f76:	2b00      	cmp	r3, #0
    1f78:	da02      	bge.n	1f80 <z_arm_fault+0x8c>
		PR_EXC("  Debug event");
    1f7a:	4841      	ldr	r0, [pc, #260]	; (2080 <z_arm_fault+0x18c>)
    1f7c:	2145      	movs	r1, #69	; 0x45
    1f7e:	e7f5      	b.n	1f6c <z_arm_fault+0x78>
	} else if ((SCB->HFSR & SCB_HFSR_FORCED_Msk) != 0) {
    1f80:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
    1f82:	005b      	lsls	r3, r3, #1
    1f84:	d5f4      	bpl.n	1f70 <z_arm_fault+0x7c>
		PR_EXC("  Fault escalation (see below)");
    1f86:	483f      	ldr	r0, [pc, #252]	; (2084 <z_arm_fault+0x190>)
    1f88:	2145      	movs	r1, #69	; 0x45
    1f8a:	f004 faf0 	bl	656e <z_log_minimal_printk>
	SCB->CCR |= SCB_CCR_BFHFNMIGN_Msk;
    1f8e:	6963      	ldr	r3, [r4, #20]
	uint16_t *ret_addr = (uint16_t *)esf->basic.pc;
    1f90:	69aa      	ldr	r2, [r5, #24]
	SCB->CCR |= SCB_CCR_BFHFNMIGN_Msk;
    1f92:	f443 7380 	orr.w	r3, r3, #256	; 0x100
    1f96:	6163      	str	r3, [r4, #20]
  __ASM volatile ("dsb 0xF":::"memory");
    1f98:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    1f9c:	f3bf 8f6f 	isb	sy
	SCB->CCR &= ~SCB_CCR_BFHFNMIGN_Msk;
    1fa0:	6963      	ldr	r3, [r4, #20]
	uint16_t fault_insn = *(ret_addr - 1);
    1fa2:	f832 2c02 	ldrh.w	r2, [r2, #-2]
	SCB->CCR &= ~SCB_CCR_BFHFNMIGN_Msk;
    1fa6:	f423 7380 	bic.w	r3, r3, #256	; 0x100
    1faa:	6163      	str	r3, [r4, #20]
  __ASM volatile ("dsb 0xF":::"memory");
    1fac:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    1fb0:	f3bf 8f6f 	isb	sy
	if (((fault_insn & 0xff00) == _SVC_OPCODE) &&
    1fb4:	f64d 7302 	movw	r3, #57090	; 0xdf02
    1fb8:	429a      	cmp	r2, r3
    1fba:	d009      	beq.n	1fd0 <z_arm_fault+0xdc>
		} else if ((SCB->CFSR & SCB_CFSR_MEMFAULTSR_Msk) != 0) {
    1fbc:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    1fbe:	b2db      	uxtb	r3, r3
    1fc0:	b333      	cbz	r3, 2010 <z_arm_fault+0x11c>
			reason = mem_manage_fault(esf, 1, recoverable);
    1fc2:	f10d 0207 	add.w	r2, sp, #7
    1fc6:	2101      	movs	r1, #1
		reason = mem_manage_fault(esf, 0, recoverable);
    1fc8:	4628      	mov	r0, r5
    1fca:	f7ff fe75 	bl	1cb8 <mem_manage_fault>
    1fce:	e02f      	b.n	2030 <z_arm_fault+0x13c>
			PR_EXC("ARCH_EXCEPT with reason %x\n", esf->basic.r0);
    1fd0:	682a      	ldr	r2, [r5, #0]
    1fd2:	482d      	ldr	r0, [pc, #180]	; (2088 <z_arm_fault+0x194>)
    1fd4:	2145      	movs	r1, #69	; 0x45
    1fd6:	f004 faca 	bl	656e <z_log_minimal_printk>
			reason = esf->basic.r0;
    1fda:	682c      	ldr	r4, [r5, #0]
#ifdef CONFIG_DEBUG_COREDUMP
	z_arm_coredump_fault_sp = POINTER_TO_UINT(esf);
#endif

	reason = fault_handle(esf, fault, &recoverable);
	if (recoverable) {
    1fdc:	f89d 3007 	ldrb.w	r3, [sp, #7]
    1fe0:	b99b      	cbnz	r3, 200a <z_arm_fault+0x116>
		return;
	}

	/* Copy ESF */
#if !defined(CONFIG_EXTRA_EXCEPTION_INFO)
	memcpy(&esf_copy, esf, sizeof(z_arch_esf_t));
    1fe2:	2220      	movs	r2, #32
    1fe4:	4629      	mov	r1, r5
    1fe6:	a802      	add	r0, sp, #8
    1fe8:	f004 fb74 	bl	66d4 <memcpy>
	/* Overwrite stacked IPSR to mark a nested exception,
	 * or a return to Thread mode. Note that this may be
	 * required, if the retrieved ESF contents are invalid
	 * due to, for instance, a stacking error.
	 */
	if (nested_exc) {
    1fec:	9b09      	ldr	r3, [sp, #36]	; 0x24
    1fee:	2e00      	cmp	r6, #0
    1ff0:	d038      	beq.n	2064 <z_arm_fault+0x170>
		if ((esf_copy.basic.xpsr & IPSR_ISR_Msk) == 0) {
    1ff2:	f3c3 0208 	ubfx	r2, r3, #0, #9
    1ff6:	b922      	cbnz	r2, 2002 <z_arm_fault+0x10e>
			esf_copy.basic.xpsr |= IPSR_ISR_Msk;
    1ff8:	ea6f 2353 	mvn.w	r3, r3, lsr #9
    1ffc:	ea6f 2343 	mvn.w	r3, r3, lsl #9
		}
	} else {
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    2000:	9309      	str	r3, [sp, #36]	; 0x24
	}

	z_arm_fatal_error(reason, &esf_copy);
    2002:	a902      	add	r1, sp, #8
    2004:	4620      	mov	r0, r4
    2006:	f7ff fd6d 	bl	1ae4 <z_arm_fatal_error>
}
    200a:	b00a      	add	sp, #40	; 0x28
    200c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		} else if ((SCB->CFSR & SCB_CFSR_BUSFAULTSR_Msk) != 0) {
    2010:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2012:	f413 4f7f 	tst.w	r3, #65280	; 0xff00
    2016:	d005      	beq.n	2024 <z_arm_fault+0x130>
			reason = bus_fault(esf, 1, recoverable);
    2018:	f10d 0107 	add.w	r1, sp, #7
    201c:	2001      	movs	r0, #1
		reason = bus_fault(esf, 0, recoverable);
    201e:	f7ff ff0f 	bl	1e40 <bus_fault.constprop.0>
    2022:	e005      	b.n	2030 <z_arm_fault+0x13c>
		} else if ((SCB->CFSR & SCB_CFSR_USGFAULTSR_Msk) != 0) {
    2024:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2026:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
    202a:	d3a1      	bcc.n	1f70 <z_arm_fault+0x7c>
			reason = usage_fault(esf);
    202c:	f7ff febc 	bl	1da8 <usage_fault.constprop.0>
    2030:	4604      	mov	r4, r0
    2032:	e7d3      	b.n	1fdc <z_arm_fault+0xe8>
		reason = mem_manage_fault(esf, 0, recoverable);
    2034:	f10d 0207 	add.w	r2, sp, #7
    2038:	2100      	movs	r1, #0
    203a:	e7c5      	b.n	1fc8 <z_arm_fault+0xd4>
		reason = bus_fault(esf, 0, recoverable);
    203c:	f10d 0107 	add.w	r1, sp, #7
    2040:	2000      	movs	r0, #0
    2042:	e7ec      	b.n	201e <z_arm_fault+0x12a>
	PR_FAULT_INFO(
    2044:	4811      	ldr	r0, [pc, #68]	; (208c <z_arm_fault+0x198>)
    2046:	2145      	movs	r1, #69	; 0x45
    2048:	e790      	b.n	1f6c <z_arm_fault+0x78>
	PR_FAULT_INFO("***** %s %d) *****",
    204a:	4911      	ldr	r1, [pc, #68]	; (2090 <z_arm_fault+0x19c>)
    204c:	4a11      	ldr	r2, [pc, #68]	; (2094 <z_arm_fault+0x1a0>)
    204e:	4812      	ldr	r0, [pc, #72]	; (2098 <z_arm_fault+0x1a4>)
    2050:	f417 7ff8 	tst.w	r7, #496	; 0x1f0
    2054:	bf08      	it	eq
    2056:	460a      	moveq	r2, r1
    2058:	f1a4 0310 	sub.w	r3, r4, #16
    205c:	2145      	movs	r1, #69	; 0x45
    205e:	f004 fa86 	bl	656e <z_log_minimal_printk>
}
    2062:	e785      	b.n	1f70 <z_arm_fault+0x7c>
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    2064:	f423 73ff 	bic.w	r3, r3, #510	; 0x1fe
    2068:	f023 0301 	bic.w	r3, r3, #1
    206c:	e7c8      	b.n	2000 <z_arm_fault+0x10c>
    206e:	bf00      	nop
    2070:	e000ed00 	.word	0xe000ed00
    2074:	00007dcb 	.word	0x00007dcb
    2078:	00007dfb 	.word	0x00007dfb
    207c:	00007e17 	.word	0x00007e17
    2080:	00007e3d 	.word	0x00007e3d
    2084:	00007e50 	.word	0x00007e50
    2088:	00007e74 	.word	0x00007e74
    208c:	00007e95 	.word	0x00007e95
    2090:	00007d9d 	.word	0x00007d9d
    2094:	00007db2 	.word	0x00007db2
    2098:	00007ebe 	.word	0x00007ebe

0000209c <z_arm_fault_init>:
 */
void z_arm_fault_init(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
    209c:	4a02      	ldr	r2, [pc, #8]	; (20a8 <z_arm_fault_init+0xc>)
    209e:	6953      	ldr	r3, [r2, #20]
    20a0:	f043 0310 	orr.w	r3, r3, #16
    20a4:	6153      	str	r3, [r2, #20]
	SCB->CCR |= SCB_CCR_STKOFHFNMIGN_Msk;
#endif /* CONFIG_BUILTIN_STACK_GUARD */
#ifdef CONFIG_TRAP_UNALIGNED_ACCESS
	SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif /* CONFIG_TRAP_UNALIGNED_ACCESS */
}
    20a6:	4770      	bx	lr
    20a8:	e000ed00 	.word	0xe000ed00

000020ac <z_arm_bus_fault>:
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_exc_spurious)

	mrs r0, MSP
    20ac:	f3ef 8008 	mrs	r0, MSP
	mrs r1, PSP
    20b0:	f3ef 8109 	mrs	r1, PSP
	push {r0, lr}
    20b4:	b501      	push	{r0, lr}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	push {r4-r11}
#endif
	mov  r3, sp /* pointer to _callee_saved_t */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
	mov r2, lr /* EXC_RETURN */
    20b6:	4672      	mov	r2, lr
	bl z_arm_fault
    20b8:	f7ff ff1c 	bl	1ef4 <z_arm_fault>
	 * in this routine. Therefore, we can just reset
	 * the MSP to its value prior to entering the function
	 */
	add sp, #40
#endif
	pop {r0, pc}
    20bc:	bd01      	pop	{r0, pc}
    20be:	bf00      	nop

000020c0 <z_arm_interrupt_init>:
    20c0:	4804      	ldr	r0, [pc, #16]	; (20d4 <z_arm_interrupt_init+0x14>)
 *
 */

void z_arm_interrupt_init(void)
{
	int irq = 0;
    20c2:	2300      	movs	r3, #0
    20c4:	2120      	movs	r1, #32
    20c6:	18c2      	adds	r2, r0, r3

	for (; irq < CONFIG_NUM_IRQS; irq++) {
    20c8:	3301      	adds	r3, #1
    20ca:	2b30      	cmp	r3, #48	; 0x30
    20cc:	f882 1300 	strb.w	r1, [r2, #768]	; 0x300
    20d0:	d1f9      	bne.n	20c6 <z_arm_interrupt_init+0x6>
		NVIC_SetPriority((IRQn_Type)irq, _IRQ_PRIO_OFFSET);
	}
}
    20d2:	4770      	bx	lr
    20d4:	e000e100 	.word	0xe000e100

000020d8 <__start>:
    strb r0, [r1]
#endif /* CONFIG_DEBUG_THREAD_INFO */

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
    /* Reset CONTROL register */
    movs.n r0, #0
    20d8:	2000      	movs	r0, #0
    msr CONTROL, r0
    20da:	f380 8814 	msr	CONTROL, r0
    isb
    20de:	f3bf 8f6f 	isb	sy
#if defined(CONFIG_PM_S2RAM)
    bl arch_pm_s2ram_resume
#endif /* CONFIG_PM_S2RAM */

#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
    bl z_arm_platform_init
    20e2:	f7ff fc81 	bl	19e8 <z_arm_platform_init>
#endif

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
#if defined(CONFIG_CPU_HAS_ARM_MPU)
    /* Disable MPU */
    movs.n r0, #0
    20e6:	2000      	movs	r0, #0
    ldr r1, =_SCS_MPU_CTRL
    20e8:	490d      	ldr	r1, [pc, #52]	; (2120 <__start+0x48>)
    str r0, [r1]
    20ea:	6008      	str	r0, [r1, #0]
    dsb
    20ec:	f3bf 8f4f 	dsb	sy
#endif /* CONFIG_CPU_HAS_ARM_MPU */
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    20f0:	480c      	ldr	r0, [pc, #48]	; (2124 <__start+0x4c>)
    msr msp, r0
    20f2:	f380 8808 	msr	MSP, r0

    /* Initialize core architecture registers and system blocks */
    bl z_arm_init_arch_hw_at_boot
    20f6:	f000 f82b 	bl	2150 <z_arm_init_arch_hw_at_boot>

    /* lock interrupts: will get unlocked when switch to main task */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    20fa:	2020      	movs	r0, #32
    msr BASEPRI, r0
    20fc:	f380 8811 	msr	BASEPRI, r0

    /*
     * Set PSP and use it to boot without using MSP, so that it
     * gets set to z_interrupt_stacks during initialization.
     */
    ldr r0, =z_interrupt_stacks
    2100:	4809      	ldr	r0, [pc, #36]	; (2128 <__start+0x50>)
    ldr r1, =CONFIG_ISR_STACK_SIZE + MPU_GUARD_ALIGN_AND_SIZE
    2102:	f44f 6104 	mov.w	r1, #2112	; 0x840
    adds r0, r0, r1
    2106:	1840      	adds	r0, r0, r1
    msr PSP, r0
    2108:	f380 8809 	msr	PSP, r0
    mrs r0, CONTROL
    210c:	f3ef 8014 	mrs	r0, CONTROL
    movs r1, #2
    2110:	2102      	movs	r1, #2
    orrs r0, r1 /* CONTROL_SPSEL_Msk */
    2112:	4308      	orrs	r0, r1
    msr CONTROL, r0
    2114:	f380 8814 	msr	CONTROL, r0
    /*
     * When changing the stack pointer, software must use an ISB instruction
     * immediately after the MSR instruction. This ensures that instructions
     * after the ISB instruction execute using the new stack pointer.
     */
    isb
    2118:	f3bf 8f6f 	isb	sy
    /*
     * 'bl' jumps the furthest of the branch instructions that are
     * supported on all platforms. So it is used when jumping to z_arm_prep_c
     * (even though we do not intend to return).
     */
    bl z_arm_prep_c
    211c:	f7ff fd48 	bl	1bb0 <z_arm_prep_c>
    ldr r1, =_SCS_MPU_CTRL
    2120:	e000ed94 	.word	0xe000ed94
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    2124:	20004540 	.word	0x20004540
    ldr r0, =z_interrupt_stacks
    2128:	20001500 	.word	0x20001500

0000212c <z_arm_clear_arm_mpu_config>:
void z_arm_clear_arm_mpu_config(void)
{
	int i;

	int num_regions =
		((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos);
    212c:	4907      	ldr	r1, [pc, #28]	; (214c <z_arm_clear_arm_mpu_config+0x20>)
    212e:	f8d1 2090 	ldr.w	r2, [r1, #144]	; 0x90

	for (i = 0; i < num_regions; i++) {
    2132:	2300      	movs	r3, #0
	int num_regions =
    2134:	f3c2 2207 	ubfx	r2, r2, #8, #8
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
  MPU->RNR = rnr;
  MPU->RASR = 0U;
    2138:	4618      	mov	r0, r3
	for (i = 0; i < num_regions; i++) {
    213a:	4293      	cmp	r3, r2
    213c:	db00      	blt.n	2140 <z_arm_clear_arm_mpu_config+0x14>
		ARM_MPU_ClrRegion(i);
	}
}
    213e:	4770      	bx	lr
  MPU->RNR = rnr;
    2140:	f8c1 3098 	str.w	r3, [r1, #152]	; 0x98
  MPU->RASR = 0U;
    2144:	f8c1 00a0 	str.w	r0, [r1, #160]	; 0xa0
	for (i = 0; i < num_regions; i++) {
    2148:	3301      	adds	r3, #1
    214a:	e7f6      	b.n	213a <z_arm_clear_arm_mpu_config+0xe>
    214c:	e000ed00 	.word	0xe000ed00

00002150 <z_arm_init_arch_hw_at_boot>:
 * This routine resets Cortex-M system control block
 * components and core registers.
 *
 */
void z_arm_init_arch_hw_at_boot(void)
{
    2150:	b508      	push	{r3, lr}
  __ASM volatile ("cpsid i" : : : "memory");
    2152:	b672      	cpsid	i
  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
    2154:	2300      	movs	r3, #0
    2156:	f383 8813 	msr	FAULTMASK, r3

	/* Initialize System Control Block components */

#if defined(CONFIG_CPU_HAS_ARM_MPU) || defined(CONFIG_CPU_HAS_NXP_MPU)
	/* Clear MPU region configuration */
	z_arm_clear_arm_mpu_config();
    215a:	f7ff ffe7 	bl	212c <z_arm_clear_arm_mpu_config>
#endif /* CONFIG_CPU_HAS_ARM_MPU */

	/* Disable NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
		NVIC->ICER[i] = 0xFFFFFFFF;
    215e:	4b14      	ldr	r3, [pc, #80]	; (21b0 <z_arm_init_arch_hw_at_boot+0x60>)
    2160:	f04f 32ff 	mov.w	r2, #4294967295
    2164:	f8c3 2080 	str.w	r2, [r3, #128]	; 0x80
    2168:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
    216c:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
    2170:	f8c3 208c 	str.w	r2, [r3, #140]	; 0x8c
    2174:	f8c3 2090 	str.w	r2, [r3, #144]	; 0x90
    2178:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
    217c:	f8c3 2098 	str.w	r2, [r3, #152]	; 0x98
    2180:	f8c3 209c 	str.w	r2, [r3, #156]	; 0x9c
	}
	/* Clear pending NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) {
		NVIC->ICPR[i] = 0xFFFFFFFF;
    2184:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
    2188:	f8c3 2184 	str.w	r2, [r3, #388]	; 0x184
    218c:	f8c3 2188 	str.w	r2, [r3, #392]	; 0x188
    2190:	f8c3 218c 	str.w	r2, [r3, #396]	; 0x18c
    2194:	f8c3 2190 	str.w	r2, [r3, #400]	; 0x190
    2198:	f8c3 2194 	str.w	r2, [r3, #404]	; 0x194
    219c:	f8c3 2198 	str.w	r2, [r3, #408]	; 0x198
    21a0:	f8c3 219c 	str.w	r2, [r3, #412]	; 0x19c
  __ASM volatile ("cpsie i" : : : "memory");
    21a4:	b662      	cpsie	i
  __ASM volatile ("dsb 0xF":::"memory");
    21a6:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    21aa:	f3bf 8f6f 	isb	sy
	/* Restore Interrupts */
	__enable_irq();

	__DSB();
	__ISB();
}
    21ae:	bd08      	pop	{r3, pc}
    21b0:	e000e100 	.word	0xe000e100

000021b4 <z_arm_configure_static_mpu_regions>:
	/* Configure the static MPU regions within firmware SRAM boundaries.
	 * Start address of the image is given by _image_ram_start. The end
	 * of the firmware SRAM area is marked by __kernel_ram_end, taking
	 * into account the unused SRAM area, as well.
	 */
	arm_core_mpu_configure_static_mpu_regions(static_regions,
    21b4:	4b02      	ldr	r3, [pc, #8]	; (21c0 <z_arm_configure_static_mpu_regions+0xc>)
    21b6:	4a03      	ldr	r2, [pc, #12]	; (21c4 <z_arm_configure_static_mpu_regions+0x10>)
    21b8:	4803      	ldr	r0, [pc, #12]	; (21c8 <z_arm_configure_static_mpu_regions+0x14>)
    21ba:	2102      	movs	r1, #2
    21bc:	f000 b86c 	b.w	2298 <arm_core_mpu_configure_static_mpu_regions>
    21c0:	20040000 	.word	0x20040000
    21c4:	20000000 	.word	0x20000000
    21c8:	00007274 	.word	0x00007274

000021cc <mpu_configure_regions>:
 * sanity check of the memory regions to be programmed.
 */
static int mpu_configure_regions(const struct z_arm_mpu_partition
	regions[], uint8_t regions_num, uint8_t start_reg_index,
	bool do_sanity_check)
{
    21cc:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
#endif /* CPU_CORTEX_M0PLUS | CPU_CORTEX_M3 | CPU_CORTEX_M4 */
}

static inline void set_region_number(uint32_t index)
{
	MPU->RNR = index;
    21ce:	4e24      	ldr	r6, [pc, #144]	; (2260 <mpu_configure_regions+0x94>)
	int i;
	int reg_index = start_reg_index;

	for (i = 0; i < regions_num; i++) {
    21d0:	2500      	movs	r5, #0
    21d2:	428d      	cmp	r5, r1
    21d4:	da0f      	bge.n	21f6 <mpu_configure_regions+0x2a>
		if (regions[i].size == 0U) {
    21d6:	6844      	ldr	r4, [r0, #4]
    21d8:	2c00      	cmp	r4, #0
    21da:	d03e      	beq.n	225a <mpu_configure_regions+0x8e>
			continue;
		}
		/* Non-empty region. */

		if (do_sanity_check &&
    21dc:	b19b      	cbz	r3, 2206 <mpu_configure_regions+0x3a>
	 * and greater or equal to the minimum
	 * MPU region size. Start address of the
	 * partition must align with size.
	 */
	int partition_is_valid =
		((part->size & (part->size - 1U)) == 0U)
    21de:	f104 3cff 	add.w	ip, r4, #4294967295
		&&
		(part->size >= CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)
		&&
    21e2:	ea14 0f0c 	tst.w	r4, ip
    21e6:	d008      	beq.n	21fa <mpu_configure_regions+0x2e>
				(!mpu_partition_is_valid(&regions[i]))) {
			LOG_ERR("Partition %u: sanity check failed.", i);
    21e8:	481e      	ldr	r0, [pc, #120]	; (2264 <mpu_configure_regions+0x98>)
    21ea:	462a      	mov	r2, r5
    21ec:	2145      	movs	r1, #69	; 0x45
		LOG_ERR("Failed to allocate new MPU region %u\n", index);
    21ee:	f004 f9be 	bl	656e <z_log_minimal_printk>
			return -EINVAL;
    21f2:	f06f 0215 	mvn.w	r2, #21
		/* Increment number of programmed MPU indices. */
		reg_index++;
	}

	return reg_index;
}
    21f6:	4610      	mov	r0, r2
    21f8:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
		&&
    21fa:	2c1f      	cmp	r4, #31
    21fc:	d9f4      	bls.n	21e8 <mpu_configure_regions+0x1c>
		((part->start & (part->size - 1U)) == 0U);
    21fe:	6807      	ldr	r7, [r0, #0]
		&&
    2200:	ea1c 0f07 	tst.w	ip, r7
    2204:	d1f0      	bne.n	21e8 <mpu_configure_regions+0x1c>
 * to that power-of-two value.
 */
static inline uint32_t size_to_mpu_rasr_size(uint32_t size)
{
	/* The minimal supported region size is 32 bytes */
	if (size <= 32U) {
    2206:	2c20      	cmp	r4, #32
	region_conf.base = new_region->start;
    2208:	6807      	ldr	r7, [r0, #0]
#if defined(CONFIG_CPU_AARCH32_CORTEX_R)
	(void) size;

	p_attr->rasr = attr->rasr_attr;
#else
	p_attr->rasr = attr->rasr_attr | size_to_mpu_rasr_size(size);
    220a:	f8d0 c008 	ldr.w	ip, [r0, #8]
		reg_index = mpu_configure_region(reg_index, &regions[i]);
    220e:	fa5f fe82 	uxtb.w	lr, r2
	if (size <= 32U) {
    2212:	d910      	bls.n	2236 <mpu_configure_regions+0x6a>
	if (size > (1UL << 31)) {
    2214:	f1b4 4f00 	cmp.w	r4, #2147483648	; 0x80000000
    2218:	d80f      	bhi.n	223a <mpu_configure_regions+0x6e>
	return ((32 - __builtin_clz(size - 1U) - 2 + 1) << MPU_RASR_SIZE_Pos) &
    221a:	3c01      	subs	r4, #1
    221c:	fab4 f484 	clz	r4, r4
    2220:	f1c4 041f 	rsb	r4, r4, #31
    2224:	0064      	lsls	r4, r4, #1
	if (index > (get_num_regions() - 1U)) {
    2226:	f1be 0f07 	cmp.w	lr, #7
	p_attr->rasr = attr->rasr_attr | size_to_mpu_rasr_size(size);
    222a:	ea4c 0c04 	orr.w	ip, ip, r4
    222e:	d906      	bls.n	223e <mpu_configure_regions+0x72>
		LOG_ERR("Failed to allocate new MPU region %u\n", index);
    2230:	480d      	ldr	r0, [pc, #52]	; (2268 <mpu_configure_regions+0x9c>)
    2232:	2145      	movs	r1, #69	; 0x45
    2234:	e7db      	b.n	21ee <mpu_configure_regions+0x22>
		return REGION_32B;
    2236:	2408      	movs	r4, #8
    2238:	e7f5      	b.n	2226 <mpu_configure_regions+0x5a>
		return REGION_4G;
    223a:	243e      	movs	r4, #62	; 0x3e
    223c:	e7f3      	b.n	2226 <mpu_configure_regions+0x5a>
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    223e:	f027 041f 	bic.w	r4, r7, #31
				| MPU_RBAR_VALID_Msk | index;
    2242:	4314      	orrs	r4, r2
    2244:	f044 0410 	orr.w	r4, r4, #16
    2248:	f8c6 2098 	str.w	r2, [r6, #152]	; 0x98
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    224c:	f8c6 409c 	str.w	r4, [r6, #156]	; 0x9c
	MPU->RASR = region_conf->attr.rasr | MPU_RASR_ENABLE_Msk;
    2250:	f04c 0401 	orr.w	r4, ip, #1
    2254:	f8c6 40a0 	str.w	r4, [r6, #160]	; 0xa0
		reg_index++;
    2258:	3201      	adds	r2, #1
	for (i = 0; i < regions_num; i++) {
    225a:	3501      	adds	r5, #1
    225c:	300c      	adds	r0, #12
    225e:	e7b8      	b.n	21d2 <mpu_configure_regions+0x6>
    2260:	e000ed00 	.word	0xe000ed00
    2264:	00007eda 	.word	0x00007eda
    2268:	00007f02 	.word	0x00007f02

0000226c <arm_core_mpu_enable>:
void arm_core_mpu_enable(void)
{
	/* Enable MPU and use the default memory map as a
	 * background region for privileged software access.
	 */
	MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
    226c:	4b04      	ldr	r3, [pc, #16]	; (2280 <arm_core_mpu_enable+0x14>)
    226e:	2205      	movs	r2, #5
    2270:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
  __ASM volatile ("dsb 0xF":::"memory");
    2274:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    2278:	f3bf 8f6f 	isb	sy

	/* Make sure that all the registers are set before proceeding */
	__DSB();
	__ISB();
}
    227c:	4770      	bx	lr
    227e:	bf00      	nop
    2280:	e000ed00 	.word	0xe000ed00

00002284 <arm_core_mpu_disable>:
  __ASM volatile ("dmb 0xF":::"memory");
    2284:	f3bf 8f5f 	dmb	sy
{
	/* Force any outstanding transfers to complete before disabling MPU */
	__DMB();

	/* Disable MPU */
	MPU->CTRL = 0;
    2288:	4b02      	ldr	r3, [pc, #8]	; (2294 <arm_core_mpu_disable+0x10>)
    228a:	2200      	movs	r2, #0
    228c:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
}
    2290:	4770      	bx	lr
    2292:	bf00      	nop
    2294:	e000ed00 	.word	0xe000ed00

00002298 <arm_core_mpu_configure_static_mpu_regions>:
 * @brief configure fixed (static) MPU regions.
 */
void arm_core_mpu_configure_static_mpu_regions(const struct z_arm_mpu_partition
	*static_regions, const uint8_t regions_num,
	const uint32_t background_area_start, const uint32_t background_area_end)
{
    2298:	b510      	push	{r4, lr}
static int mpu_configure_static_mpu_regions(const struct z_arm_mpu_partition
	static_regions[], const uint8_t regions_num,
	const uint32_t background_area_base,
	const uint32_t background_area_end)
{
	int mpu_reg_index = static_regions_num;
    229a:	4c03      	ldr	r4, [pc, #12]	; (22a8 <arm_core_mpu_configure_static_mpu_regions+0x10>)
	 * programmed on top of SRAM region configuration.
	 */
	ARG_UNUSED(background_area_base);
	ARG_UNUSED(background_area_end);

	mpu_reg_index = mpu_configure_regions(static_regions,
    229c:	2301      	movs	r3, #1
    229e:	7822      	ldrb	r2, [r4, #0]
    22a0:	f7ff ff94 	bl	21cc <mpu_configure_regions>
		regions_num, mpu_reg_index, true);

	static_regions_num = mpu_reg_index;
    22a4:	7020      	strb	r0, [r4, #0]
					       background_area_start, background_area_end) == -EINVAL) {

		__ASSERT(0, "Configuring %u static MPU regions failed\n",
			regions_num);
	}
}
    22a6:	bd10      	pop	{r4, pc}
    22a8:	200010bd 	.word	0x200010bd

000022ac <z_arm_mpu_init>:
 */
int z_arm_mpu_init(void)
{
	uint32_t r_index;

	if (mpu_config.num_regions > get_num_regions()) {
    22ac:	4914      	ldr	r1, [pc, #80]	; (2300 <z_arm_mpu_init+0x54>)
    22ae:	6808      	ldr	r0, [r1, #0]
    22b0:	2808      	cmp	r0, #8
{
    22b2:	b510      	push	{r4, lr}
	if (mpu_config.num_regions > get_num_regions()) {
    22b4:	d821      	bhi.n	22fa <z_arm_mpu_init+0x4e>
		return -1;
	}

	LOG_DBG("total region count: %d", get_num_regions());

	arm_core_mpu_disable();
    22b6:	f7ff ffe5 	bl	2284 <arm_core_mpu_disable>
    22ba:	4c12      	ldr	r4, [pc, #72]	; (2304 <z_arm_mpu_init+0x58>)
    22bc:	6849      	ldr	r1, [r1, #4]

	/* Architecture-specific configuration */
	mpu_init();

	/* Program fixed regions configured at SOC definition. */
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    22be:	2200      	movs	r2, #0
    22c0:	4290      	cmp	r0, r2
    22c2:	f101 010c 	add.w	r1, r1, #12
    22c6:	d105      	bne.n	22d4 <z_arm_mpu_init+0x28>
		region_init(r_index, &mpu_config.mpu_regions[r_index]);
	}

	/* Update the number of programmed MPU regions. */
	static_regions_num = mpu_config.num_regions;
    22c8:	4b0f      	ldr	r3, [pc, #60]	; (2308 <z_arm_mpu_init+0x5c>)
    22ca:	7018      	strb	r0, [r3, #0]


	arm_core_mpu_enable();
    22cc:	f7ff ffce 	bl	226c <arm_core_mpu_enable>
		(MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos ==
		NUM_MPU_REGIONS,
		"Invalid number of MPU regions\n");
#endif /* CORTEX_M0PLUS || CPU_CORTEX_M3 || CPU_CORTEX_M4 */

	return 0;
    22d0:	2000      	movs	r0, #0
}
    22d2:	bd10      	pop	{r4, pc}
    22d4:	f8c4 2098 	str.w	r2, [r4, #152]	; 0x98
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    22d8:	f851 3c0c 	ldr.w	r3, [r1, #-12]
    22dc:	f023 031f 	bic.w	r3, r3, #31
				| MPU_RBAR_VALID_Msk | index;
    22e0:	4313      	orrs	r3, r2
    22e2:	f043 0310 	orr.w	r3, r3, #16
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    22e6:	f8c4 309c 	str.w	r3, [r4, #156]	; 0x9c
	MPU->RASR = region_conf->attr.rasr | MPU_RASR_ENABLE_Msk;
    22ea:	f851 3c04 	ldr.w	r3, [r1, #-4]
    22ee:	f043 0301 	orr.w	r3, r3, #1
    22f2:	f8c4 30a0 	str.w	r3, [r4, #160]	; 0xa0
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    22f6:	3201      	adds	r2, #1
    22f8:	e7e2      	b.n	22c0 <z_arm_mpu_init+0x14>
		return -1;
    22fa:	f04f 30ff 	mov.w	r0, #4294967295
    22fe:	e7e8      	b.n	22d2 <z_arm_mpu_init+0x26>
    2300:	0000728c 	.word	0x0000728c
    2304:	e000ed00 	.word	0xe000ed00
    2308:	200010bd 	.word	0x200010bd

0000230c <__stdout_hook_install>:

static int (*_stdout_hook)(int c) = _stdout_hook_default;

void __stdout_hook_install(int (*hook)(int c))
{
	_stdout_hook = hook;
    230c:	4b01      	ldr	r3, [pc, #4]	; (2314 <__stdout_hook_install+0x8>)
    230e:	6018      	str	r0, [r3, #0]
}
    2310:	4770      	bx	lr
    2312:	bf00      	nop
    2314:	20000010 	.word	0x20000010

00002318 <nordicsemi_nrf52_init>:
	nrf_power_gpregret_set(NRF_POWER, (uint8_t)type);
	NVIC_SystemReset();
}

static int nordicsemi_nrf52_init(const struct device *arg)
{
    2318:	b510      	push	{r4, lr}
	__asm__ volatile(
    231a:	f04f 0320 	mov.w	r3, #32
    231e:	f3ef 8011 	mrs	r0, BASEPRI
    2322:	f383 8812 	msr	BASEPRI_MAX, r3
    2326:	f3bf 8f6f 	isb	sy

	key = irq_lock();

#ifdef CONFIG_NRF_ENABLE_ICACHE
	/* Enable the instruction cache */
	NRF_NVMC->ICACHECNF = NVMC_ICACHECNF_CACHEEN_Msk;
    232a:	4a11      	ldr	r2, [pc, #68]	; (2370 <nordicsemi_nrf52_init+0x58>)
    232c:	2301      	movs	r3, #1
    232e:	f8c2 3540 	str.w	r3, [r2, #1344]	; 0x540
#endif

#if NRF_POWER_HAS_DCDCEN
NRF_STATIC_INLINE void nrf_power_dcdcen_set(NRF_POWER_Type * p_reg, bool enable)
{
    p_reg->DCDCEN = (enable ? POWER_DCDCEN_DCDCEN_Enabled : POWER_DCDCEN_DCDCEN_Disabled) <<
    2332:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
{
    #ifndef NRF52_SERIES
        return false;
    #else
        #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    2336:	f04f 5180 	mov.w	r1, #268435456	; 0x10000000
    233a:	f8c2 3578 	str.w	r3, [r2, #1400]	; 0x578
            uint32_t var2 = *(uint32_t *)0x10000134ul;
        #endif
        #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            if (var1 == 0x08)
    233e:	f8d1 4130 	ldr.w	r4, [r1, #304]	; 0x130
    2342:	2c08      	cmp	r4, #8
    2344:	d108      	bne.n	2358 <nordicsemi_nrf52_init+0x40>
            uint32_t var2 = *(uint32_t *)0x10000134ul;
    2346:	f8d1 1134 	ldr.w	r1, [r1, #308]	; 0x134
            {
                switch(var2)
    234a:	2905      	cmp	r1, #5
    234c:	d804      	bhi.n	2358 <nordicsemi_nrf52_init+0x40>
#endif // defined(POWER_RAM_POWER_S0POWER_Msk)

#if NRF_POWER_HAS_DCDCEN_VDDH
NRF_STATIC_INLINE void nrf_power_dcdcen_vddh_set(NRF_POWER_Type * p_reg, bool enable)
{
    if (enable && nrf52_errata_197())
    234e:	4c09      	ldr	r4, [pc, #36]	; (2374 <nordicsemi_nrf52_init+0x5c>)
    2350:	5c61      	ldrb	r1, [r4, r1]
    2352:	b109      	cbz	r1, 2358 <nordicsemi_nrf52_init+0x40>
    {
        // Workaround for anomaly 197 "POWER: DCDC of REG0 not functional".
        *(volatile uint32_t *)0x40000638ul = 1ul;
    2354:	f8c2 3638 	str.w	r3, [r2, #1592]	; 0x638
    }
    p_reg->DCDCEN0 = (enable ? POWER_DCDCEN0_DCDCEN_Enabled : POWER_DCDCEN0_DCDCEN_Disabled) <<
    2358:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    235c:	2201      	movs	r2, #1
    235e:	f8c3 2580 	str.w	r2, [r3, #1408]	; 0x580
	__asm__ volatile(
    2362:	f380 8811 	msr	BASEPRI, r0
    2366:	f3bf 8f6f 	isb	sy
	NMI_INIT();

	irq_unlock(key);

	return 0;
}
    236a:	2000      	movs	r0, #0
    236c:	bd10      	pop	{r4, pc}
    236e:	bf00      	nop
    2370:	4001e000 	.word	0x4001e000
    2374:	00007f3c 	.word	0x00007f3c

00002378 <sys_arch_reboot>:
    *p_gpregret = val;
    2378:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    237c:	b2c0      	uxtb	r0, r0
    237e:	f8c3 051c 	str.w	r0, [r3, #1308]	; 0x51c
  __ASM volatile ("dsb 0xF":::"memory");
    2382:	f3bf 8f4f 	dsb	sy
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
  __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                       buffered write are completed before reset */
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    2386:	4905      	ldr	r1, [pc, #20]	; (239c <sys_arch_reboot+0x24>)
    2388:	4b05      	ldr	r3, [pc, #20]	; (23a0 <sys_arch_reboot+0x28>)
    238a:	68ca      	ldr	r2, [r1, #12]
    238c:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    2390:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    2392:	60cb      	str	r3, [r1, #12]
    2394:	f3bf 8f4f 	dsb	sy
                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
  __DSB();                                                          /* Ensure completion of memory access */

  for(;;)                                                           /* wait until reset */
  {
    __NOP();
    2398:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    239a:	e7fd      	b.n	2398 <sys_arch_reboot+0x20>
    239c:	e000ed00 	.word	0xe000ed00
    23a0:	05fa0004 	.word	0x05fa0004

000023a4 <arch_busy_wait>:

#else // NRFX_CHECK(NRFX_DELAY_DWT_BASED)

NRF_STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us)
{
    if (time_us == 0)
    23a4:	b120      	cbz	r0, 23b0 <arch_busy_wait+0xc>
    typedef void (* delay_func_t)(uint32_t);
    const delay_func_t delay_cycles =
        // Set LSB to 1 to execute the code in the Thumb mode.
        (delay_func_t)((((uint32_t)delay_machine_code) | 1));
    uint32_t cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ;
    delay_cycles(cycles);
    23a6:	4b03      	ldr	r3, [pc, #12]	; (23b4 <arch_busy_wait+0x10>)
    23a8:	0180      	lsls	r0, r0, #6
    23aa:	f043 0301 	orr.w	r3, r3, #1
    23ae:	4718      	bx	r3

void arch_busy_wait(uint32_t time_us)
{
	nrfx_coredep_delay_us(time_us);
}
    23b0:	4770      	bx	lr
    23b2:	bf00      	nop
    23b4:	000071e0 	.word	0x000071e0

000023b8 <onoff_stop>:
}

static clock_control_subsys_t get_subsys(struct onoff_manager *mgr)
{
	struct nrf_clock_control_data *data = CLOCK_DEVICE->data;
	size_t offset = (size_t)(mgr - data->mgr);
    23b8:	4b08      	ldr	r3, [pc, #32]	; (23dc <onoff_stop+0x24>)
	return (clock_control_subsys_t)offset;
}

static void onoff_stop(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    23ba:	b570      	push	{r4, r5, r6, lr}
	size_t offset = (size_t)(mgr - data->mgr);
    23bc:	1ac3      	subs	r3, r0, r3
{
    23be:	460d      	mov	r5, r1
	int res;

	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
    23c0:	4907      	ldr	r1, [pc, #28]	; (23e0 <onoff_stop+0x28>)
	size_t offset = (size_t)(mgr - data->mgr);
    23c2:	109b      	asrs	r3, r3, #2
{
    23c4:	4604      	mov	r4, r0
	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
    23c6:	4359      	muls	r1, r3
    23c8:	4806      	ldr	r0, [pc, #24]	; (23e4 <onoff_stop+0x2c>)
    23ca:	2240      	movs	r2, #64	; 0x40
    23cc:	f004 f9b5 	bl	673a <stop>
	notify(mgr, res);
    23d0:	462b      	mov	r3, r5
	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
    23d2:	4601      	mov	r1, r0
	notify(mgr, res);
    23d4:	4620      	mov	r0, r4
}
    23d6:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	notify(mgr, res);
    23da:	4718      	bx	r3
    23dc:	20000e6c 	.word	0x20000e6c
    23e0:	b6db6db7 	.word	0xb6db6db7
    23e4:	00006f50 	.word	0x00006f50

000023e8 <onoff_start>:
	notify(mgr, 0);
}

static void onoff_start(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    23e8:	b573      	push	{r0, r1, r4, r5, r6, lr}
	size_t offset = (size_t)(mgr - data->mgr);
    23ea:	4c0c      	ldr	r4, [pc, #48]	; (241c <onoff_start+0x34>)
	int err;

	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    23ec:	4a0c      	ldr	r2, [pc, #48]	; (2420 <onoff_start+0x38>)
    23ee:	2340      	movs	r3, #64	; 0x40
	size_t offset = (size_t)(mgr - data->mgr);
    23f0:	1b04      	subs	r4, r0, r4
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    23f2:	9300      	str	r3, [sp, #0]
{
    23f4:	460d      	mov	r5, r1
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    23f6:	460b      	mov	r3, r1
    23f8:	490a      	ldr	r1, [pc, #40]	; (2424 <onoff_start+0x3c>)
	size_t offset = (size_t)(mgr - data->mgr);
    23fa:	10a4      	asrs	r4, r4, #2
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    23fc:	4361      	muls	r1, r4
{
    23fe:	4606      	mov	r6, r0
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    2400:	4809      	ldr	r0, [pc, #36]	; (2428 <onoff_start+0x40>)
    2402:	f004 f9c6 	bl	6792 <async_start>
			  onoff_started_callback, notify, CTX_ONOFF);
	if (err < 0) {
    2406:	1e01      	subs	r1, r0, #0
    2408:	da05      	bge.n	2416 <onoff_start+0x2e>
		notify(mgr, err);
    240a:	4630      	mov	r0, r6
    240c:	462b      	mov	r3, r5
	}
}
    240e:	b002      	add	sp, #8
    2410:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		notify(mgr, err);
    2414:	4718      	bx	r3
}
    2416:	b002      	add	sp, #8
    2418:	bd70      	pop	{r4, r5, r6, pc}
    241a:	bf00      	nop
    241c:	20000e6c 	.word	0x20000e6c
    2420:	00006803 	.word	0x00006803
    2424:	b6db6db7 	.word	0xb6db6db7
    2428:	00006f50 	.word	0x00006f50

0000242c <clk_init>:
	static const struct onoff_transitions transitions = {
		.start = onoff_start,
		.stop = onoff_stop
	};

	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    242c:	2200      	movs	r2, #0
{
    242e:	b570      	push	{r4, r5, r6, lr}
	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    2430:	2101      	movs	r1, #1
{
    2432:	4604      	mov	r4, r0
	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    2434:	4610      	mov	r0, r2
    2436:	f7ff fb9f 	bl	1b78 <z_arm_irq_priority_set>
		    nrfx_isr, nrfx_power_clock_irq_handler, 0);

	nrfx_err = nrfx_clock_init(clock_event_handler);
    243a:	480f      	ldr	r0, [pc, #60]	; (2478 <clk_init+0x4c>)
    243c:	f001 face 	bl	39dc <nrfx_clock_init>
	if (nrfx_err != NRFX_SUCCESS) {
    2440:	4b0e      	ldr	r3, [pc, #56]	; (247c <clk_init+0x50>)
    2442:	4298      	cmp	r0, r3
    2444:	d115      	bne.n	2472 <clk_init+0x46>
		struct nrf_clock_control_data *data = dev->data;

		z_nrf_clock_calibration_init(data->mgr);
	}

	nrfx_clock_enable();
    2446:	f004 fc50 	bl	6cea <nrfx_clock_enable>
	struct nrf_clock_control_data *data = dev->data;
    244a:	6926      	ldr	r6, [r4, #16]
	for (enum clock_control_nrf_type i = 0;
		i < CLOCK_CONTROL_NRF_TYPE_COUNT; i++) {
		struct nrf_clock_control_sub_data *subdata =
						get_sub_data(dev, i);

		err = onoff_manager_init(get_onoff_manager(dev, i),
    244c:	490c      	ldr	r1, [pc, #48]	; (2480 <clk_init+0x54>)
    244e:	4630      	mov	r0, r6
    2450:	f004 f803 	bl	645a <onoff_manager_init>
					 &transitions);
		if (err < 0) {
    2454:	2800      	cmp	r0, #0
    2456:	db0b      	blt.n	2470 <clk_init+0x44>
			return err;
		}

		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    2458:	2501      	movs	r5, #1
    245a:	6435      	str	r5, [r6, #64]	; 0x40
	struct nrf_clock_control_data *data = dev->data;
    245c:	6924      	ldr	r4, [r4, #16]
		err = onoff_manager_init(get_onoff_manager(dev, i),
    245e:	4908      	ldr	r1, [pc, #32]	; (2480 <clk_init+0x54>)
    2460:	f104 001c 	add.w	r0, r4, #28
    2464:	f003 fff9 	bl	645a <onoff_manager_init>
		if (err < 0) {
    2468:	2800      	cmp	r0, #0
    246a:	db01      	blt.n	2470 <clk_init+0x44>
		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    246c:	64e5      	str	r5, [r4, #76]	; 0x4c
	}

	return 0;
    246e:	2000      	movs	r0, #0
}
    2470:	bd70      	pop	{r4, r5, r6, pc}
		return -EIO;
    2472:	f06f 0004 	mvn.w	r0, #4
    2476:	e7fb      	b.n	2470 <clk_init+0x44>
    2478:	000024b9 	.word	0x000024b9
    247c:	0bad0000 	.word	0x0bad0000
    2480:	000072ac 	.word	0x000072ac

00002484 <clkstarted_handle.constprop.0>:
static void clkstarted_handle(const struct device *dev,
    2484:	b570      	push	{r4, r5, r6, lr}
    2486:	4601      	mov	r1, r0
	clock_control_cb_t callback = sub_data->cb;
    2488:	230c      	movs	r3, #12
    248a:	4809      	ldr	r0, [pc, #36]	; (24b0 <clkstarted_handle.constprop.0+0x2c>)
    248c:	434b      	muls	r3, r1
    248e:	18c4      	adds	r4, r0, r3
	void *user_data = sub_data->user_data;
    2490:	e9d4 560e 	ldrd	r5, r6, [r4, #56]	; 0x38
	sub_data->cb = NULL;
    2494:	2200      	movs	r2, #0
	set_on_state(&sub_data->flags);
    2496:	3340      	adds	r3, #64	; 0x40
	sub_data->cb = NULL;
    2498:	63a2      	str	r2, [r4, #56]	; 0x38
	set_on_state(&sub_data->flags);
    249a:	4418      	add	r0, r3
    249c:	f004 f93a 	bl	6714 <set_on_state>
	if (callback) {
    24a0:	b12d      	cbz	r5, 24ae <clkstarted_handle.constprop.0+0x2a>
		callback(dev, (clock_control_subsys_t)type, user_data);
    24a2:	4632      	mov	r2, r6
    24a4:	462b      	mov	r3, r5
    24a6:	4803      	ldr	r0, [pc, #12]	; (24b4 <clkstarted_handle.constprop.0+0x30>)
}
    24a8:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		callback(dev, (clock_control_subsys_t)type, user_data);
    24ac:	4718      	bx	r3
}
    24ae:	bd70      	pop	{r4, r5, r6, pc}
    24b0:	20000e6c 	.word	0x20000e6c
    24b4:	00006f50 	.word	0x00006f50

000024b8 <clock_event_handler>:
	switch (event) {
    24b8:	b110      	cbz	r0, 24c0 <clock_event_handler+0x8>
    24ba:	2801      	cmp	r0, #1
    24bc:	d004      	beq.n	24c8 <clock_event_handler+0x10>
    24be:	4770      	bx	lr
		if (GET_STATUS(data->flags) == CLOCK_CONTROL_STATUS_STARTING) {
    24c0:	4b03      	ldr	r3, [pc, #12]	; (24d0 <clock_event_handler+0x18>)
    24c2:	6c1b      	ldr	r3, [r3, #64]	; 0x40
    24c4:	075b      	lsls	r3, r3, #29
    24c6:	d101      	bne.n	24cc <clock_event_handler+0x14>
		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_LFCLK);
    24c8:	f7ff bfdc 	b.w	2484 <clkstarted_handle.constprop.0>
}
    24cc:	4770      	bx	lr
    24ce:	bf00      	nop
    24d0:	20000e6c 	.word	0x20000e6c

000024d4 <generic_hfclk_start>:
{
    24d4:	b508      	push	{r3, lr}
	__asm__ volatile(
    24d6:	f04f 0320 	mov.w	r3, #32
    24da:	f3ef 8111 	mrs	r1, BASEPRI
    24de:	f383 8812 	msr	BASEPRI_MAX, r3
    24e2:	f3bf 8f6f 	isb	sy
	hfclk_users |= HF_USER_GENERIC;
    24e6:	4a12      	ldr	r2, [pc, #72]	; (2530 <generic_hfclk_start+0x5c>)
    24e8:	6813      	ldr	r3, [r2, #0]
    24ea:	f043 0002 	orr.w	r0, r3, #2
    24ee:	6010      	str	r0, [r2, #0]
	if (hfclk_users & HF_USER_BT) {
    24f0:	07da      	lsls	r2, r3, #31
    24f2:	d408      	bmi.n	2506 <generic_hfclk_start+0x32>
	__asm__ volatile(
    24f4:	f381 8811 	msr	BASEPRI, r1
    24f8:	f3bf 8f6f 	isb	sy
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_start(void)
{
    nrfx_clock_start(NRF_CLOCK_DOMAIN_HFCLK);
    24fc:	2001      	movs	r0, #1
}
    24fe:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    2502:	f004 bbff 	b.w	6d04 <nrfx_clock_start>
            break;
        case NRF_CLOCK_DOMAIN_HFCLK:
            if (p_clk_src != NULL)
            {
                (*(nrf_clock_hfclk_t *)p_clk_src) =
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    2506:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    250a:	f8d3 240c 	ldr.w	r2, [r3, #1036]	; 0x40c
                                        >> CLOCK_HFCLKSTAT_SRC_Pos);
            }
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    250e:	f8d3 340c 	ldr.w	r3, [r3, #1036]	; 0x40c
		if (type == NRF_CLOCK_HFCLK_HIGH_ACCURACY) {
    2512:	07d3      	lsls	r3, r2, #31
    2514:	d5ee      	bpl.n	24f4 <generic_hfclk_start+0x20>
			set_on_state(get_hf_flags());
    2516:	4807      	ldr	r0, [pc, #28]	; (2534 <generic_hfclk_start+0x60>)
    2518:	f004 f8fc 	bl	6714 <set_on_state>
    251c:	f381 8811 	msr	BASEPRI, r1
    2520:	f3bf 8f6f 	isb	sy
		clkstarted_handle(CLOCK_DEVICE,
    2524:	2000      	movs	r0, #0
}
    2526:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
		clkstarted_handle(CLOCK_DEVICE,
    252a:	f7ff bfab 	b.w	2484 <clkstarted_handle.constprop.0>
    252e:	bf00      	nop
    2530:	20000ebc 	.word	0x20000ebc
    2534:	20000eac 	.word	0x20000eac

00002538 <generic_hfclk_stop>:
 *
 * @return Previous value of @a target.
 */
static inline atomic_val_t atomic_and(atomic_t *target, atomic_val_t value)
{
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    2538:	4b09      	ldr	r3, [pc, #36]	; (2560 <generic_hfclk_stop+0x28>)
    253a:	f3bf 8f5b 	dmb	ish
    253e:	e853 2f00 	ldrex	r2, [r3]
    2542:	f022 0102 	bic.w	r1, r2, #2
    2546:	e843 1000 	strex	r0, r1, [r3]
    254a:	2800      	cmp	r0, #0
    254c:	d1f7      	bne.n	253e <generic_hfclk_stop+0x6>
    254e:	f3bf 8f5b 	dmb	ish
	if (atomic_and(&hfclk_users, ~HF_USER_GENERIC) & HF_USER_BT) {
    2552:	07d3      	lsls	r3, r2, #31
    2554:	d402      	bmi.n	255c <generic_hfclk_stop+0x24>
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_stop(void)
{
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLK);
    2556:	2001      	movs	r0, #1
    2558:	f004 bc10 	b.w	6d7c <nrfx_clock_stop>
}
    255c:	4770      	bx	lr
    255e:	bf00      	nop
    2560:	20000ebc 	.word	0x20000ebc

00002564 <z_nrf_clock_control_lf_on>:
{
    2564:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
	return __atomic_exchange_n(target, value, __ATOMIC_SEQ_CST);
    2568:	4936      	ldr	r1, [pc, #216]	; (2644 <z_nrf_clock_control_lf_on+0xe0>)
    256a:	f3bf 8f5b 	dmb	ish
    256e:	4607      	mov	r7, r0
    2570:	2201      	movs	r2, #1
    2572:	e851 3f00 	ldrex	r3, [r1]
    2576:	e841 2000 	strex	r0, r2, [r1]
    257a:	2800      	cmp	r0, #0
    257c:	d1f9      	bne.n	2572 <z_nrf_clock_control_lf_on+0xe>
    257e:	f3bf 8f5b 	dmb	ish
	if (atomic_set(&on, 1) == 0) {
    2582:	b933      	cbnz	r3, 2592 <z_nrf_clock_control_lf_on+0x2e>
 */
static inline void sys_notify_init_spinwait(struct sys_notify *notify)
{
	__ASSERT_NO_MSG(notify != NULL);

	*notify = (struct sys_notify){
    2584:	4930      	ldr	r1, [pc, #192]	; (2648 <z_nrf_clock_control_lf_on+0xe4>)
		err = onoff_request(mgr, &cli);
    2586:	4831      	ldr	r0, [pc, #196]	; (264c <z_nrf_clock_control_lf_on+0xe8>)
    2588:	604b      	str	r3, [r1, #4]
    258a:	60cb      	str	r3, [r1, #12]
    258c:	608a      	str	r2, [r1, #8]
    258e:	f003 ff77 	bl	6480 <onoff_request>
	switch (start_mode) {
    2592:	1e7b      	subs	r3, r7, #1
    2594:	2b01      	cmp	r3, #1
    2596:	d82d      	bhi.n	25f4 <z_nrf_clock_control_lf_on+0x90>
	if ((mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE) &&
    2598:	2f01      	cmp	r7, #1
    259a:	d107      	bne.n	25ac <z_nrf_clock_control_lf_on+0x48>
    return clk_src;
}

NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(NRF_CLOCK_Type const * p_reg)
{
    return (nrf_clock_lfclk_t)((p_reg->LFCLKSRCCOPY & CLOCK_LFCLKSRCCOPY_SRC_Msk)
    259c:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    25a0:	f8d3 341c 	ldr.w	r3, [r3, #1052]	; 0x41c
    25a4:	f003 0303 	and.w	r3, r3, #3
	    (target_type == NRF_CLOCK_LFCLK_Xtal) &&
    25a8:	2b01      	cmp	r3, #1
    25aa:	d023      	beq.n	25f4 <z_nrf_clock_control_lf_on+0x90>
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    25ac:	f004 fc65 	bl	6e7a <k_is_in_isr>
    25b0:	4605      	mov	r5, r0
    25b2:	bb08      	cbnz	r0, 25f8 <z_nrf_clock_control_lf_on+0x94>
	return !z_sys_post_kernel;
    25b4:	4b26      	ldr	r3, [pc, #152]	; (2650 <z_nrf_clock_control_lf_on+0xec>)
    25b6:	781b      	ldrb	r3, [r3, #0]
    25b8:	b1f3      	cbz	r3, 25f8 <z_nrf_clock_control_lf_on+0x94>
    p_reg->INTENCLR = mask;
    25ba:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    25be:	2202      	movs	r2, #2
    25c0:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
	int key = isr_mode ? irq_lock() : 0;
    25c4:	4606      	mov	r6, r0
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    25c6:	f8df 908c 	ldr.w	r9, [pc, #140]	; 2654 <z_nrf_clock_control_lf_on+0xf0>
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    25ca:	f04f 4480 	mov.w	r4, #1073741824	; 0x40000000
    p_reg->LFCLKSRC = (uint32_t)(source);
    25ce:	f04f 0801 	mov.w	r8, #1
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    25d2:	f8d4 3418 	ldr.w	r3, [r4, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    25d6:	f8d4 2418 	ldr.w	r2, [r4, #1048]	; 0x418
    25da:	03d2      	lsls	r2, r2, #15
    25dc:	d516      	bpl.n	260c <z_nrf_clock_control_lf_on+0xa8>
                                        >> CLOCK_LFCLKSTAT_SRC_Pos);
    25de:	f003 0303 	and.w	r3, r3, #3
	while (!(nrfx_clock_is_running(d, (void *)&type)
    25e2:	2b01      	cmp	r3, #1
    25e4:	d001      	beq.n	25ea <z_nrf_clock_control_lf_on+0x86>
		     || (mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE)))) {
    25e6:	2f01      	cmp	r7, #1
    25e8:	d110      	bne.n	260c <z_nrf_clock_control_lf_on+0xa8>
	if (isr_mode) {
    25ea:	b32d      	cbz	r5, 2638 <z_nrf_clock_control_lf_on+0xd4>
    25ec:	f386 8811 	msr	BASEPRI, r6
    25f0:	f3bf 8f6f 	isb	sy
}
    25f4:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
	__asm__ volatile(
    25f8:	f04f 0320 	mov.w	r3, #32
    25fc:	f3ef 8611 	mrs	r6, BASEPRI
    2600:	f383 8812 	msr	BASEPRI_MAX, r3
    2604:	f3bf 8f6f 	isb	sy
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    2608:	2501      	movs	r5, #1
    260a:	e7dc      	b.n	25c6 <z_nrf_clock_control_lf_on+0x62>
 *
 * @param key Interrupt locking key obtained from irq_lock().
 */
static inline void k_cpu_atomic_idle(unsigned int key)
{
	arch_cpu_atomic_idle(key);
    260c:	4630      	mov	r0, r6
    260e:	f7ff fa5f 	bl	1ad0 <arch_cpu_atomic_idle>
    return (nrf_clock_lfclk_t)(p_reg->LFCLKSRC);
    2612:	f8d4 3518 	ldr.w	r3, [r4, #1304]	; 0x518
		if ((target_type ==  NRF_CLOCK_LFCLK_Xtal)
    2616:	2b00      	cmp	r3, #0
    2618:	d1db      	bne.n	25d2 <z_nrf_clock_control_lf_on+0x6e>
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    261a:	f8d4 2104 	ldr.w	r2, [r4, #260]	; 0x104
		    && nrf_clock_event_check(NRF_CLOCK,
    261e:	2a00      	cmp	r2, #0
    2620:	d0d7      	beq.n	25d2 <z_nrf_clock_control_lf_on+0x6e>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2622:	f8c4 3104 	str.w	r3, [r4, #260]	; 0x104
#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE void nrf_event_readback(void * p_event_reg)
{
#if NRFX_CHECK(NRFX_EVENT_READBACK_ENABLED) && !defined(NRF51)
    (void)*((volatile uint32_t *)(p_event_reg));
    2626:	f8d4 3104 	ldr.w	r3, [r4, #260]	; 0x104
    p_reg->LFCLKSRC = (uint32_t)(source);
    262a:	f8c4 8518 	str.w	r8, [r4, #1304]	; 0x518
    262e:	f8c9 8180 	str.w	r8, [r9, #384]	; 0x180
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2632:	f8c4 8008 	str.w	r8, [r4, #8]
}
    2636:	e7cc      	b.n	25d2 <z_nrf_clock_control_lf_on+0x6e>
    p_reg->INTENSET = mask;
    2638:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    263c:	2202      	movs	r2, #2
    263e:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
}
    2642:	e7d7      	b.n	25f4 <z_nrf_clock_control_lf_on+0x90>
    2644:	20000e68 	.word	0x20000e68
    2648:	20000e58 	.word	0x20000e58
    264c:	20000e88 	.word	0x20000e88
    2650:	200014d3 	.word	0x200014d3
    2654:	e000e100 	.word	0xe000e100

00002658 <uart_console_init>:
 * @brief Initialize one UART as the console/debug port
 *
 * @return 0 if successful, otherwise failed.
 */
static int uart_console_init(const struct device *arg)
{
    2658:	b508      	push	{r3, lr}
    265a:	4807      	ldr	r0, [pc, #28]	; (2678 <uart_console_init+0x20>)
    265c:	f004 fbfe 	bl	6e5c <z_device_is_ready>

	ARG_UNUSED(arg);

	if (!device_is_ready(uart_console_dev)) {
    2660:	b138      	cbz	r0, 2672 <uart_console_init+0x1a>
	__stdout_hook_install(console_out);
    2662:	4806      	ldr	r0, [pc, #24]	; (267c <uart_console_init+0x24>)
    2664:	f7ff fe52 	bl	230c <__stdout_hook_install>
	__printk_hook_install(console_out);
    2668:	4804      	ldr	r0, [pc, #16]	; (267c <uart_console_init+0x24>)
    266a:	f7fe fe67 	bl	133c <__printk_hook_install>
		return -ENODEV;
	}

	uart_console_hook_install();

	return 0;
    266e:	2000      	movs	r0, #0
}
    2670:	bd08      	pop	{r3, pc}
		return -ENODEV;
    2672:	f06f 0012 	mvn.w	r0, #18
    2676:	e7fb      	b.n	2670 <uart_console_init+0x18>
    2678:	00006fb0 	.word	0x00006fb0
    267c:	00002681 	.word	0x00002681

00002680 <console_out>:
	if ('\n' == c) {
    2680:	280a      	cmp	r0, #10
{
    2682:	b538      	push	{r3, r4, r5, lr}
    2684:	4d07      	ldr	r5, [pc, #28]	; (26a4 <console_out+0x24>)
    2686:	4604      	mov	r4, r0
	if ('\n' == c) {
    2688:	d104      	bne.n	2694 <console_out+0x14>
					unsigned char out_char)
{
	const struct uart_driver_api *api =
		(const struct uart_driver_api *)dev->api;

	api->poll_out(dev, out_char);
    268a:	68ab      	ldr	r3, [r5, #8]
    268c:	210d      	movs	r1, #13
    268e:	685b      	ldr	r3, [r3, #4]
    2690:	4628      	mov	r0, r5
    2692:	4798      	blx	r3
    2694:	68ab      	ldr	r3, [r5, #8]
    2696:	4803      	ldr	r0, [pc, #12]	; (26a4 <console_out+0x24>)
    2698:	685b      	ldr	r3, [r3, #4]
    269a:	b2e1      	uxtb	r1, r4
    269c:	4798      	blx	r3
}
    269e:	4620      	mov	r0, r4
    26a0:	bd38      	pop	{r3, r4, r5, pc}
    26a2:	bf00      	nop
    26a4:	00006fb0 	.word	0x00006fb0

000026a8 <gpio_nrfx_pin_interrupt_configure>:

static int gpio_nrfx_pin_interrupt_configure(const struct device *port,
					     gpio_pin_t pin,
					     enum gpio_int_mode mode,
					     enum gpio_int_trig trig)
{
    26a8:	b530      	push	{r4, r5, lr}
	return port->config;
    26aa:	6840      	ldr	r0, [r0, #4]
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
    26ac:	7b05      	ldrb	r5, [r0, #12]
    26ae:	f001 041f 	and.w	r4, r1, #31
	nrfx_err_t err;
	uint8_t ch;

	if (mode == GPIO_INT_MODE_DISABLED) {
    26b2:	f5b2 1f00 	cmp.w	r2, #2097152	; 0x200000
{
    26b6:	b085      	sub	sp, #20
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
    26b8:	ea44 1445 	orr.w	r4, r4, r5, lsl #5
	if (mode == GPIO_INT_MODE_DISABLED) {
    26bc:	d105      	bne.n	26ca <gpio_nrfx_pin_interrupt_configure+0x22>
		nrfx_gpiote_trigger_disable(abs_pin);
    26be:	4620      	mov	r0, r4
    26c0:	f001 fc10 	bl	3ee4 <nrfx_gpiote_trigger_disable>

		return 0;
    26c4:	2000      	movs	r0, #0
	}

	nrfx_gpiote_trigger_enable(abs_pin, true);

	return 0;
}
    26c6:	b005      	add	sp, #20
    26c8:	bd30      	pop	{r4, r5, pc}
	nrfx_gpiote_trigger_config_t trigger_config = {
    26ca:	2500      	movs	r5, #0
	if (mode == GPIO_INT_MODE_LEVEL) {
    26cc:	f5b2 0f80 	cmp.w	r2, #4194304	; 0x400000
	nrfx_gpiote_trigger_config_t trigger_config = {
    26d0:	e9cd 5502 	strd	r5, r5, [sp, #8]
	if (mode == GPIO_INT_MODE_LEVEL) {
    26d4:	d114      	bne.n	2700 <gpio_nrfx_pin_interrupt_configure+0x58>
		return trig == GPIO_INT_TRIG_LOW ? NRFX_GPIOTE_TRIGGER_LOW :
    26d6:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
	nrfx_gpiote_trigger_config_t trigger_config = {
    26da:	bf0c      	ite	eq
    26dc:	2304      	moveq	r3, #4
    26de:	2305      	movne	r3, #5
    26e0:	f88d 3008 	strb.w	r3, [sp, #8]
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    26e4:	2300      	movs	r3, #0
    26e6:	4619      	mov	r1, r3
    26e8:	aa02      	add	r2, sp, #8
    26ea:	4620      	mov	r0, r4
    26ec:	f001 fa38 	bl	3b60 <nrfx_gpiote_input_configure>
	if (err != NRFX_SUCCESS) {
    26f0:	4b1f      	ldr	r3, [pc, #124]	; (2770 <gpio_nrfx_pin_interrupt_configure+0xc8>)
    26f2:	4298      	cmp	r0, r3
    26f4:	d139      	bne.n	276a <gpio_nrfx_pin_interrupt_configure+0xc2>
	nrfx_gpiote_trigger_enable(abs_pin, true);
    26f6:	2101      	movs	r1, #1
    26f8:	4620      	mov	r0, r4
    26fa:	f001 fbab 	bl	3e54 <nrfx_gpiote_trigger_enable>
	return 0;
    26fe:	e7e1      	b.n	26c4 <gpio_nrfx_pin_interrupt_configure+0x1c>
	return trig == GPIO_INT_TRIG_BOTH ? NRFX_GPIOTE_TRIGGER_TOGGLE :
    2700:	f1b3 6fc0 	cmp.w	r3, #100663296	; 0x6000000
    2704:	d026      	beq.n	2754 <gpio_nrfx_pin_interrupt_configure+0xac>
    2706:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
    270a:	bf14      	ite	ne
    270c:	2301      	movne	r3, #1
    270e:	2302      	moveq	r3, #2
	nrfx_gpiote_trigger_config_t trigger_config = {
    2710:	f88d 3008 	strb.w	r3, [sp, #8]
	if (!(BIT(pin) & get_port_cfg(port)->edge_sense) &&
    2714:	6883      	ldr	r3, [r0, #8]
    2716:	40cb      	lsrs	r3, r1
    2718:	07d9      	lsls	r1, r3, #31
    271a:	d4e3      	bmi.n	26e4 <gpio_nrfx_pin_interrupt_configure+0x3c>
    271c:	f1b2 7fa0 	cmp.w	r2, #20971520	; 0x1400000
    2720:	d1e0      	bne.n	26e4 <gpio_nrfx_pin_interrupt_configure+0x3c>
NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin)
{
    uint32_t pin_number = *p_pin;
    *p_pin = pin_number & 0x1F;

    return pin_number >> 5;
    2722:	0962      	lsrs	r2, r4, #5
        case 1: return NRF_P1;
    2724:	2a01      	cmp	r2, #1
    *p_pin = pin_number & 0x1F;
    2726:	f004 031f 	and.w	r3, r4, #31
        case 1: return NRF_P1;
    272a:	4a12      	ldr	r2, [pc, #72]	; (2774 <gpio_nrfx_pin_interrupt_configure+0xcc>)
    return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
    272c:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
        case 1: return NRF_P1;
    2730:	bf18      	it	ne
    2732:	f04f 42a0 	movne.w	r2, #1342177280	; 0x50000000
    return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
    2736:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
	    (mode == GPIO_INT_MODE_EDGE) &&
    273a:	07db      	lsls	r3, r3, #31
    273c:	d4d2      	bmi.n	26e4 <gpio_nrfx_pin_interrupt_configure+0x3c>
		err = nrfx_gpiote_channel_get(abs_pin, &ch);
    273e:	f10d 0507 	add.w	r5, sp, #7
    2742:	4629      	mov	r1, r5
    2744:	4620      	mov	r0, r4
    2746:	f001 fb31 	bl	3dac <nrfx_gpiote_channel_get>
		if (err == NRFX_ERROR_INVALID_PARAM) {
    274a:	4b0b      	ldr	r3, [pc, #44]	; (2778 <gpio_nrfx_pin_interrupt_configure+0xd0>)
    274c:	4298      	cmp	r0, r3
    274e:	d003      	beq.n	2758 <gpio_nrfx_pin_interrupt_configure+0xb0>
		trigger_config.p_in_channel = &ch;
    2750:	9503      	str	r5, [sp, #12]
    2752:	e7c7      	b.n	26e4 <gpio_nrfx_pin_interrupt_configure+0x3c>
	return trig == GPIO_INT_TRIG_BOTH ? NRFX_GPIOTE_TRIGGER_TOGGLE :
    2754:	2303      	movs	r3, #3
    2756:	e7db      	b.n	2710 <gpio_nrfx_pin_interrupt_configure+0x68>
			err = nrfx_gpiote_channel_alloc(&ch);
    2758:	4628      	mov	r0, r5
    275a:	f001 fb75 	bl	3e48 <nrfx_gpiote_channel_alloc>
			if (err != NRFX_SUCCESS) {
    275e:	4b04      	ldr	r3, [pc, #16]	; (2770 <gpio_nrfx_pin_interrupt_configure+0xc8>)
    2760:	4298      	cmp	r0, r3
    2762:	d0f5      	beq.n	2750 <gpio_nrfx_pin_interrupt_configure+0xa8>
				return -ENOMEM;
    2764:	f06f 000b 	mvn.w	r0, #11
    2768:	e7ad      	b.n	26c6 <gpio_nrfx_pin_interrupt_configure+0x1e>
		return -EINVAL;
    276a:	f06f 0015 	mvn.w	r0, #21
    276e:	e7aa      	b.n	26c6 <gpio_nrfx_pin_interrupt_configure+0x1e>
    2770:	0bad0000 	.word	0x0bad0000
    2774:	50000300 	.word	0x50000300
    2778:	0bad0004 	.word	0x0bad0004

0000277c <gpio_nrfx_init>:
}

#define GPIOTE_NODE DT_INST(0, nordic_nrf_gpiote)

static int gpio_nrfx_init(const struct device *port)
{
    277c:	b510      	push	{r4, lr}
	nrfx_err_t err;

	if (nrfx_gpiote_is_init()) {
    277e:	f001 fb53 	bl	3e28 <nrfx_gpiote_is_init>
    2782:	4604      	mov	r4, r0
    2784:	b968      	cbnz	r0, 27a2 <gpio_nrfx_init+0x26>
		return 0;
	}

	err = nrfx_gpiote_init(0/*not used*/);
    2786:	f001 fb27 	bl	3dd8 <nrfx_gpiote_init>
	if (err != NRFX_SUCCESS) {
    278a:	4b08      	ldr	r3, [pc, #32]	; (27ac <gpio_nrfx_init+0x30>)
    278c:	4298      	cmp	r0, r3
    278e:	d10a      	bne.n	27a6 <gpio_nrfx_init+0x2a>
		return -EIO;
	}

	nrfx_gpiote_global_callback_set(nrfx_gpio_handler, NULL);
    2790:	4807      	ldr	r0, [pc, #28]	; (27b0 <gpio_nrfx_init+0x34>)
    2792:	4621      	mov	r1, r4
    2794:	f001 fb04 	bl	3da0 <nrfx_gpiote_global_callback_set>

	IRQ_CONNECT(DT_IRQN(GPIOTE_NODE), DT_IRQ(GPIOTE_NODE, priority),
    2798:	4622      	mov	r2, r4
    279a:	2105      	movs	r1, #5
    279c:	2006      	movs	r0, #6
    279e:	f7ff f9eb 	bl	1b78 <z_arm_irq_priority_set>
		return 0;
    27a2:	2000      	movs	r0, #0
		    nrfx_isr, nrfx_gpiote_irq_handler, 0);

	return 0;
}
    27a4:	bd10      	pop	{r4, pc}
		return -EIO;
    27a6:	f06f 0004 	mvn.w	r0, #4
    27aa:	e7fb      	b.n	27a4 <gpio_nrfx_init+0x28>
    27ac:	0bad0000 	.word	0x0bad0000
    27b0:	000027b5 	.word	0x000027b5

000027b4 <nrfx_gpio_handler>:
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    27b4:	0942      	lsrs	r2, r0, #5
{
    27b6:	b570      	push	{r4, r5, r6, lr}
    27b8:	4603      	mov	r3, r0
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    27ba:	d002      	beq.n	27c2 <nrfx_gpio_handler+0xe>
    27bc:	2a01      	cmp	r2, #1
    27be:	d017      	beq.n	27f0 <nrfx_gpio_handler+0x3c>
}
    27c0:	bd70      	pop	{r4, r5, r6, pc}
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    27c2:	4e0d      	ldr	r6, [pc, #52]	; (27f8 <nrfx_gpio_handler+0x44>)
	gpio_fire_callbacks(list, port, BIT(pin));
    27c4:	6932      	ldr	r2, [r6, #16]
    27c6:	6851      	ldr	r1, [r2, #4]
					const struct device *port,
					uint32_t pins)
{
	struct gpio_callback *cb, *tmp;

	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    27c8:	2900      	cmp	r1, #0
    27ca:	d0f9      	beq.n	27c0 <nrfx_gpio_handler+0xc>
    *p_pin = pin_number & 0x1F;
    27cc:	f003 031f 	and.w	r3, r3, #31
    27d0:	2501      	movs	r5, #1
	return node->next;
    27d2:	680c      	ldr	r4, [r1, #0]
    27d4:	409d      	lsls	r5, r3
    27d6:	2900      	cmp	r1, #0
    27d8:	d0f2      	beq.n	27c0 <nrfx_gpio_handler+0xc>
		if (cb->pin_mask & pins) {
    27da:	688a      	ldr	r2, [r1, #8]
    27dc:	402a      	ands	r2, r5
    27de:	d002      	beq.n	27e6 <nrfx_gpio_handler+0x32>
			__ASSERT(cb->handler, "No callback handler!");
			cb->handler(port, cb, cb->pin_mask & pins);
    27e0:	684b      	ldr	r3, [r1, #4]
    27e2:	4630      	mov	r0, r6
    27e4:	4798      	blx	r3
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    27e6:	b12c      	cbz	r4, 27f4 <nrfx_gpio_handler+0x40>
    27e8:	6823      	ldr	r3, [r4, #0]
    27ea:	4621      	mov	r1, r4
    27ec:	461c      	mov	r4, r3
    27ee:	e7f2      	b.n	27d6 <nrfx_gpio_handler+0x22>
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    27f0:	4e02      	ldr	r6, [pc, #8]	; (27fc <nrfx_gpio_handler+0x48>)
    27f2:	e7e7      	b.n	27c4 <nrfx_gpio_handler+0x10>
    27f4:	4623      	mov	r3, r4
    27f6:	e7f8      	b.n	27ea <nrfx_gpio_handler+0x36>
    27f8:	00006f80 	.word	0x00006f80
    27fc:	00006f68 	.word	0x00006f68

00002800 <gpio_nrfx_pin_configure>:
{
    2800:	e92d 41ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr}
	return port->config;
    2804:	6847      	ldr	r7, [r0, #4]
	nrfx_gpiote_pin_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    2806:	7b3b      	ldrb	r3, [r7, #12]
    2808:	f001 051f 	and.w	r5, r1, #31
    280c:	ea45 1543 	orr.w	r5, r5, r3, lsl #5
{
    2810:	460e      	mov	r6, r1
	err = nrfx_gpiote_channel_get(abs_pin, &ch);
    2812:	4628      	mov	r0, r5
    2814:	f10d 0103 	add.w	r1, sp, #3
{
    2818:	4614      	mov	r4, r2
	err = nrfx_gpiote_channel_get(abs_pin, &ch);
    281a:	f001 fac7 	bl	3dac <nrfx_gpiote_channel_get>
	if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == GPIO_DISCONNECTED) {
    281e:	f414 3f40 	tst.w	r4, #196608	; 0x30000
	err = nrfx_gpiote_channel_get(abs_pin, &ch);
    2822:	4680      	mov	r8, r0
	if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == GPIO_DISCONNECTED) {
    2824:	d10b      	bne.n	283e <gpio_nrfx_pin_configure+0x3e>
		(void)nrfx_gpiote_pin_uninit(abs_pin);
    2826:	4628      	mov	r0, r5
    2828:	f001 fb84 	bl	3f34 <nrfx_gpiote_pin_uninit>
		if (free_ch) {
    282c:	4b3d      	ldr	r3, [pc, #244]	; (2924 <gpio_nrfx_pin_configure+0x124>)
    282e:	4598      	cmp	r8, r3
    2830:	d103      	bne.n	283a <gpio_nrfx_pin_configure+0x3a>
			err = nrfx_gpiote_channel_free(ch);
    2832:	f89d 0003 	ldrb.w	r0, [sp, #3]
    2836:	f001 fb01 	bl	3e3c <nrfx_gpiote_channel_free>
		return 0;
    283a:	2000      	movs	r0, #0
    283c:	e00c      	b.n	2858 <gpio_nrfx_pin_configure+0x58>
	nrfx_gpiote_trigger_config_t trigger_config = {
    283e:	2300      	movs	r3, #0
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    2840:	4619      	mov	r1, r3
    2842:	aa02      	add	r2, sp, #8
    2844:	4628      	mov	r0, r5
	nrfx_gpiote_trigger_config_t trigger_config = {
    2846:	e9cd 3302 	strd	r3, r3, [sp, #8]
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    284a:	f001 f989 	bl	3b60 <nrfx_gpiote_input_configure>
	if (err != NRFX_SUCCESS) {
    284e:	4b35      	ldr	r3, [pc, #212]	; (2924 <gpio_nrfx_pin_configure+0x124>)
    2850:	4298      	cmp	r0, r3
    2852:	d004      	beq.n	285e <gpio_nrfx_pin_configure+0x5e>
		return NRF_GPIO_PIN_PULLUP;
    2854:	f06f 0015 	mvn.w	r0, #21
}
    2858:	b004      	add	sp, #16
    285a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	if (free_ch) {
    285e:	4580      	cmp	r8, r0
    2860:	d103      	bne.n	286a <gpio_nrfx_pin_configure+0x6a>
		err = nrfx_gpiote_channel_free(ch);
    2862:	f89d 0003 	ldrb.w	r0, [sp, #3]
    2866:	f001 fae9 	bl	3e3c <nrfx_gpiote_channel_free>
	if (flags & GPIO_OUTPUT) {
    286a:	03a3      	lsls	r3, r4, #14
    286c:	d54b      	bpl.n	2906 <gpio_nrfx_pin_configure+0x106>
	switch (flags & (NRF_GPIO_DRIVE_MSK | GPIO_OPEN_DRAIN)) {
    286e:	f240 3306 	movw	r3, #774	; 0x306
    2872:	4023      	ands	r3, r4
    2874:	f5b3 7f83 	cmp.w	r3, #262	; 0x106
    2878:	d019      	beq.n	28ae <gpio_nrfx_pin_configure+0xae>
    287a:	d80c      	bhi.n	2896 <gpio_nrfx_pin_configure+0x96>
    287c:	2b06      	cmp	r3, #6
    287e:	d017      	beq.n	28b0 <gpio_nrfx_pin_configure+0xb0>
    2880:	d804      	bhi.n	288c <gpio_nrfx_pin_configure+0x8c>
    2882:	b1ab      	cbz	r3, 28b0 <gpio_nrfx_pin_configure+0xb0>
    2884:	2b02      	cmp	r3, #2
    2886:	d1e5      	bne.n	2854 <gpio_nrfx_pin_configure+0x54>
		*drive = NRF_GPIO_PIN_D0S1;
    2888:	2304      	movs	r3, #4
    288a:	e011      	b.n	28b0 <gpio_nrfx_pin_configure+0xb0>
	switch (flags & (NRF_GPIO_DRIVE_MSK | GPIO_OPEN_DRAIN)) {
    288c:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
    2890:	d1e0      	bne.n	2854 <gpio_nrfx_pin_configure+0x54>
		*drive = NRF_GPIO_PIN_H0S1;
    2892:	2301      	movs	r3, #1
    2894:	e00c      	b.n	28b0 <gpio_nrfx_pin_configure+0xb0>
	switch (flags & (NRF_GPIO_DRIVE_MSK | GPIO_OPEN_DRAIN)) {
    2896:	f240 2202 	movw	r2, #514	; 0x202
    289a:	4293      	cmp	r3, r2
    289c:	d027      	beq.n	28ee <gpio_nrfx_pin_configure+0xee>
    289e:	f5b3 7f40 	cmp.w	r3, #768	; 0x300
    28a2:	d026      	beq.n	28f2 <gpio_nrfx_pin_configure+0xf2>
    28a4:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
    28a8:	d1d4      	bne.n	2854 <gpio_nrfx_pin_configure+0x54>
		*drive = NRF_GPIO_PIN_S0H1;
    28aa:	2302      	movs	r3, #2
    28ac:	e000      	b.n	28b0 <gpio_nrfx_pin_configure+0xb0>
		*drive = NRF_GPIO_PIN_H0D1;
    28ae:	2307      	movs	r3, #7
		nrfx_gpiote_output_config_t output_config = {
    28b0:	f88d 3004 	strb.w	r3, [sp, #4]
				NRF_GPIO_PIN_INPUT_CONNECT :
    28b4:	f484 3380 	eor.w	r3, r4, #65536	; 0x10000
    28b8:	f3c3 4300 	ubfx	r3, r3, #16, #1
	if (flags & GPIO_PULL_UP) {
    28bc:	06e0      	lsls	r0, r4, #27
		nrfx_gpiote_output_config_t output_config = {
    28be:	f88d 3005 	strb.w	r3, [sp, #5]
	} else if (flags & GPIO_PULL_DOWN) {
    28c2:	bf54      	ite	pl
    28c4:	f3c4 1340 	ubfxpl	r3, r4, #5, #1
		return NRF_GPIO_PIN_PULLUP;
    28c8:	2303      	movmi	r3, #3
		if (flags & GPIO_OUTPUT_INIT_HIGH) {
    28ca:	0321      	lsls	r1, r4, #12
		nrfx_gpiote_output_config_t output_config = {
    28cc:	f88d 3006 	strb.w	r3, [sp, #6]
		if (flags & GPIO_OUTPUT_INIT_HIGH) {
    28d0:	d511      	bpl.n	28f6 <gpio_nrfx_pin_configure+0xf6>
			nrf_gpio_port_out_set(cfg->port, BIT(pin));
    28d2:	687a      	ldr	r2, [r7, #4]
    28d4:	2301      	movs	r3, #1
    28d6:	40b3      	lsls	r3, r6
    p_reg->OUTSET = set_mask;
    28d8:	f8c2 3508 	str.w	r3, [r2, #1288]	; 0x508
		err = nrfx_gpiote_output_configure(abs_pin, &output_config, NULL);
    28dc:	2200      	movs	r2, #0
    28de:	a901      	add	r1, sp, #4
    28e0:	4628      	mov	r0, r5
    28e2:	f001 f9eb 	bl	3cbc <nrfx_gpiote_output_configure>
	return (err != NRFX_SUCCESS) ? -EINVAL : 0;
    28e6:	4b0f      	ldr	r3, [pc, #60]	; (2924 <gpio_nrfx_pin_configure+0x124>)
    28e8:	4298      	cmp	r0, r3
    28ea:	d0a6      	beq.n	283a <gpio_nrfx_pin_configure+0x3a>
    28ec:	e7b2      	b.n	2854 <gpio_nrfx_pin_configure+0x54>
		*drive = NRF_GPIO_PIN_D0H1;
    28ee:	2305      	movs	r3, #5
    28f0:	e7de      	b.n	28b0 <gpio_nrfx_pin_configure+0xb0>
	switch (flags & (NRF_GPIO_DRIVE_MSK | GPIO_OPEN_DRAIN)) {
    28f2:	2303      	movs	r3, #3
    28f4:	e7dc      	b.n	28b0 <gpio_nrfx_pin_configure+0xb0>
		} else if (flags & GPIO_OUTPUT_INIT_LOW) {
    28f6:	0362      	lsls	r2, r4, #13
			nrf_gpio_port_out_clear(cfg->port, BIT(pin));
    28f8:	bf41      	itttt	mi
    28fa:	2301      	movmi	r3, #1
    28fc:	687a      	ldrmi	r2, [r7, #4]
    28fe:	40b3      	lslmi	r3, r6
    p_reg->OUTCLR = clr_mask;
    2900:	f8c2 350c 	strmi.w	r3, [r2, #1292]	; 0x50c
}
    2904:	e7ea      	b.n	28dc <gpio_nrfx_pin_configure+0xdc>
	if (flags & GPIO_PULL_UP) {
    2906:	06e3      	lsls	r3, r4, #27
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    2908:	f04f 0300 	mov.w	r3, #0
	} else if (flags & GPIO_PULL_DOWN) {
    290c:	bf54      	ite	pl
    290e:	f3c4 1440 	ubfxpl	r4, r4, #5, #1
		return NRF_GPIO_PIN_PULLUP;
    2912:	2403      	movmi	r4, #3
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    2914:	461a      	mov	r2, r3
    2916:	a901      	add	r1, sp, #4
    2918:	4628      	mov	r0, r5
	nrfx_gpiote_input_config_t input_config = {
    291a:	f88d 4004 	strb.w	r4, [sp, #4]
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    291e:	f001 f91f 	bl	3b60 <nrfx_gpiote_input_configure>
    2922:	e7e0      	b.n	28e6 <gpio_nrfx_pin_configure+0xe6>
    2924:	0bad0000 	.word	0x0bad0000

00002928 <flash_nrf_pages_layout>:

static void flash_nrf_pages_layout(const struct device *dev,
				     const struct flash_pages_layout **layout,
				     size_t *layout_size)
{
	*layout = &dev_layout;
    2928:	4b02      	ldr	r3, [pc, #8]	; (2934 <flash_nrf_pages_layout+0xc>)
    292a:	600b      	str	r3, [r1, #0]
	*layout_size = 1;
    292c:	2301      	movs	r3, #1
    292e:	6013      	str	r3, [r2, #0]
}
    2930:	4770      	bx	lr
    2932:	bf00      	nop
    2934:	20000ed8 	.word	0x20000ed8

00002938 <flash_nrf_get_parameters>:
flash_nrf_get_parameters(const struct device *dev)
{
	ARG_UNUSED(dev);

	return &flash_nrf_parameters;
}
    2938:	4800      	ldr	r0, [pc, #0]	; (293c <flash_nrf_get_parameters+0x4>)
    293a:	4770      	bx	lr
    293c:	00007344 	.word	0x00007344

00002940 <nrf_flash_init>:
	.page_layout = flash_nrf_pages_layout,
#endif
};

static int nrf_flash_init(const struct device *dev)
{
    2940:	b510      	push	{r4, lr}
#ifndef CONFIG_SOC_FLASH_NRF_RADIO_SYNC_NONE
	nrf_flash_sync_init();
#endif /* !CONFIG_SOC_FLASH_NRF_RADIO_SYNC_NONE */

#if defined(CONFIG_FLASH_PAGE_LAYOUT)
	dev_layout.pages_count = nrfx_nvmc_flash_page_count_get();
    2942:	f004 fa7f 	bl	6e44 <nrfx_nvmc_flash_page_count_get>
    2946:	4c03      	ldr	r4, [pc, #12]	; (2954 <nrf_flash_init+0x14>)
    2948:	6020      	str	r0, [r4, #0]
	dev_layout.pages_size = nrfx_nvmc_flash_page_size_get();
    294a:	f004 fa77 	bl	6e3c <nrfx_nvmc_flash_page_size_get>
    294e:	6060      	str	r0, [r4, #4]
#endif

	return 0;
}
    2950:	2000      	movs	r0, #0
    2952:	bd10      	pop	{r4, pc}
    2954:	20000ed8 	.word	0x20000ed8

00002958 <flash_nrf_read>:
{
    2958:	b570      	push	{r4, r5, r6, lr}
    295a:	460d      	mov	r5, r1
	if (is_regular_addr_valid(addr, len)) {
    295c:	4628      	mov	r0, r5
    295e:	4619      	mov	r1, r3
{
    2960:	4616      	mov	r6, r2
    2962:	461c      	mov	r4, r3
	if (is_regular_addr_valid(addr, len)) {
    2964:	f003 ffb2 	bl	68cc <is_regular_addr_valid>
    2968:	b940      	cbnz	r0, 297c <flash_nrf_read+0x24>
		LOG_ERR("invalid address: 0x%08lx:%zu",
    296a:	4808      	ldr	r0, [pc, #32]	; (298c <flash_nrf_read+0x34>)
    296c:	4623      	mov	r3, r4
    296e:	462a      	mov	r2, r5
    2970:	2145      	movs	r1, #69	; 0x45
    2972:	f003 fdfc 	bl	656e <z_log_minimal_printk>
    2976:	f06f 0015 	mvn.w	r0, #21
}
    297a:	bd70      	pop	{r4, r5, r6, pc}
	if (!len) {
    297c:	b124      	cbz	r4, 2988 <flash_nrf_read+0x30>
	memcpy(data, (void *)addr, len);
    297e:	4622      	mov	r2, r4
    2980:	4629      	mov	r1, r5
    2982:	4630      	mov	r0, r6
    2984:	f003 fea6 	bl	66d4 <memcpy>
		return 0;
    2988:	2000      	movs	r0, #0
    298a:	e7f6      	b.n	297a <flash_nrf_read+0x22>
    298c:	00007f8b 	.word	0x00007f8b

00002990 <restore_pofwarn.part.0>:
    uint32_t pofcon = p_reg->POFCON;
    2990:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    2994:	f8d2 1510 	ldr.w	r1, [r2, #1296]	; 0x510
    uint32_t pofcon = p_reg->POFCON;
    2998:	f8d2 3510 	ldr.w	r3, [r2, #1296]	; 0x510
        (((uint32_t)thr) << POWER_POFCON_THRESHOLD_Pos) |
    299c:	f001 011e 	and.w	r1, r1, #30
    pofcon &= ~(POWER_POFCON_THRESHOLD_Msk | POWER_POFCON_POF_Msk);
    29a0:	f023 031f 	bic.w	r3, r3, #31
    29a4:	430b      	orrs	r3, r1
    pofcon |=
    29a6:	f043 0301 	orr.w	r3, r3, #1
    p_reg->POFCON = pofcon;
    29aa:	f8c2 3510 	str.w	r3, [r2, #1296]	; 0x510

	if (pofcon_enabled) {
		pof_thr = nrf_power_pofcon_get(NRF_POWER, NULL);

		nrf_power_pofcon_set(NRF_POWER, true, pof_thr);
		pofcon_enabled = false;
    29ae:	4b02      	ldr	r3, [pc, #8]	; (29b8 <restore_pofwarn.part.0+0x28>)
    29b0:	2200      	movs	r2, #0
    29b2:	701a      	strb	r2, [r3, #0]
	}
}
    29b4:	4770      	bx	lr
    29b6:	bf00      	nop
    29b8:	200010be 	.word	0x200010be

000029bc <suspend_pofwarn>:
    #else
        #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\
         || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\
         || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\
         || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    29bc:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
            uint32_t var2 = *(uint32_t *)0x10000134ul;
        #endif
        #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            if (var1 == 0x08)
    29c0:	f8d3 3130 	ldr.w	r3, [r3, #304]	; 0x130
    29c4:	2b08      	cmp	r3, #8
    29c6:	d120      	bne.n	2a0a <suspend_pofwarn+0x4e>
    uint32_t pofcon = p_reg->POFCON;
    29c8:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    29cc:	f8d2 1510 	ldr.w	r1, [r2, #1296]	; 0x510
	if (enabled) {
    29d0:	07cb      	lsls	r3, r1, #31
    29d2:	d51a      	bpl.n	2a0a <suspend_pofwarn+0x4e>
    uint32_t pofcon = p_reg->POFCON;
    29d4:	f8d2 3510 	ldr.w	r3, [r2, #1296]	; 0x510
        (((uint32_t)thr) << POWER_POFCON_THRESHOLD_Pos) |
    29d8:	f001 011e 	and.w	r1, r1, #30
    pofcon &= ~(POWER_POFCON_THRESHOLD_Msk | POWER_POFCON_POF_Msk);
    29dc:	f023 031f 	bic.w	r3, r3, #31
    pofcon |=
    29e0:	430b      	orrs	r3, r1
    p_reg->POFCON = pofcon;
    29e2:	f8c2 3510 	str.w	r3, [r2, #1296]	; 0x510
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    29e6:	f8d2 3108 	ldr.w	r3, [r2, #264]	; 0x108
		if (nrf_power_event_check(NRF_POWER, NRF_POWER_EVENT_POFWARN)) {
    29ea:	b15b      	cbz	r3, 2a04 <suspend_pofwarn+0x48>
    uint32_t pofcon = p_reg->POFCON;
    29ec:	f8d2 3510 	ldr.w	r3, [r2, #1296]	; 0x510
    pofcon &= ~(POWER_POFCON_THRESHOLD_Msk | POWER_POFCON_POF_Msk);
    29f0:	f023 031f 	bic.w	r3, r3, #31
    29f4:	430b      	orrs	r3, r1
    pofcon |=
    29f6:	f043 0301 	orr.w	r3, r3, #1
    p_reg->POFCON = pofcon;
    29fa:	f8c2 3510 	str.w	r3, [r2, #1296]	; 0x510
			return -ECANCELED;
    29fe:	f06f 008b 	mvn.w	r0, #139	; 0x8b
}
    2a02:	4770      	bx	lr
		pofcon_enabled = enabled;
    2a04:	4b02      	ldr	r3, [pc, #8]	; (2a10 <suspend_pofwarn+0x54>)
    2a06:	2201      	movs	r2, #1
    2a08:	701a      	strb	r2, [r3, #0]
		return 0;
    2a0a:	2000      	movs	r0, #0
}
    2a0c:	4770      	bx	lr
    2a0e:	bf00      	nop
    2a10:	200010be 	.word	0x200010be

00002a14 <flash_nrf_erase>:
{
    2a14:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    2a18:	460f      	mov	r7, r1
    2a1a:	4615      	mov	r5, r2
	uint32_t pg_size = nrfx_nvmc_flash_page_size_get();
    2a1c:	f004 fa0e 	bl	6e3c <nrfx_nvmc_flash_page_size_get>
	if (is_regular_addr_valid(addr, size)) {
    2a20:	4629      	mov	r1, r5
	uint32_t pg_size = nrfx_nvmc_flash_page_size_get();
    2a22:	4606      	mov	r6, r0
	if (is_regular_addr_valid(addr, size)) {
    2a24:	4638      	mov	r0, r7
    2a26:	f003 ff51 	bl	68cc <is_regular_addr_valid>
		if (((addr % pg_size) != 0) || ((size % pg_size) != 0)) {
    2a2a:	46b8      	mov	r8, r7
	if (is_regular_addr_valid(addr, size)) {
    2a2c:	b360      	cbz	r0, 2a88 <flash_nrf_erase+0x74>
		if (((addr % pg_size) != 0) || ((size % pg_size) != 0)) {
    2a2e:	fbb7 f3f6 	udiv	r3, r7, r6
    2a32:	fb06 7313 	mls	r3, r6, r3, r7
    2a36:	b923      	cbnz	r3, 2a42 <flash_nrf_erase+0x2e>
    2a38:	fbb5 f4f6 	udiv	r4, r5, r6
    2a3c:	fb06 5414 	mls	r4, r6, r4, r5
    2a40:	b144      	cbz	r4, 2a54 <flash_nrf_erase+0x40>
			LOG_ERR("unaligned address: 0x%08lx:%zu",
    2a42:	4814      	ldr	r0, [pc, #80]	; (2a94 <flash_nrf_erase+0x80>)
    2a44:	462b      	mov	r3, r5
    2a46:	463a      	mov	r2, r7
    2a48:	2145      	movs	r1, #69	; 0x45
		LOG_ERR("invalid address: 0x%08lx:%zu",
    2a4a:	f003 fd90 	bl	656e <z_log_minimal_printk>
			return -EINVAL;
    2a4e:	f06f 0415 	mvn.w	r4, #21
    2a52:	e013      	b.n	2a7c <flash_nrf_erase+0x68>
		if (!n_pages) {
    2a54:	42ae      	cmp	r6, r5
    2a56:	d811      	bhi.n	2a7c <flash_nrf_erase+0x68>
	uint32_t pg_size = nrfx_nvmc_flash_page_size_get();
    2a58:	f004 f9f0 	bl	6e3c <nrfx_nvmc_flash_page_size_get>
	if (pofcon_enabled) {
    2a5c:	4f0e      	ldr	r7, [pc, #56]	; (2a98 <flash_nrf_erase+0x84>)
	uint32_t pg_size = nrfx_nvmc_flash_page_size_get();
    2a5e:	4606      	mov	r6, r0
		if (SUSPEND_POFWARN()) {
    2a60:	f7ff ffac 	bl	29bc <suspend_pofwarn>
    2a64:	4604      	mov	r4, r0
    2a66:	b960      	cbnz	r0, 2a82 <flash_nrf_erase+0x6e>
		(void)nrfx_nvmc_page_erase(e_ctx->flash_addr);
    2a68:	4640      	mov	r0, r8
    2a6a:	f001 fb71 	bl	4150 <nrfx_nvmc_page_erase>
	if (pofcon_enabled) {
    2a6e:	783b      	ldrb	r3, [r7, #0]
    2a70:	b10b      	cbz	r3, 2a76 <flash_nrf_erase+0x62>
    2a72:	f7ff ff8d 	bl	2990 <restore_pofwarn.part.0>
	} while (e_ctx->len > 0);
    2a76:	1bad      	subs	r5, r5, r6
    2a78:	44b0      	add	r8, r6
    2a7a:	d1f1      	bne.n	2a60 <flash_nrf_erase+0x4c>
}
    2a7c:	4620      	mov	r0, r4
    2a7e:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
			return -ECANCELED;
    2a82:	f06f 048b 	mvn.w	r4, #139	; 0x8b
	return ret;
    2a86:	e7f9      	b.n	2a7c <flash_nrf_erase+0x68>
		LOG_ERR("invalid address: 0x%08lx:%zu",
    2a88:	4804      	ldr	r0, [pc, #16]	; (2a9c <flash_nrf_erase+0x88>)
    2a8a:	462b      	mov	r3, r5
    2a8c:	463a      	mov	r2, r7
    2a8e:	2145      	movs	r1, #69	; 0x45
    2a90:	e7db      	b.n	2a4a <flash_nrf_erase+0x36>
    2a92:	bf00      	nop
    2a94:	00007fad 	.word	0x00007fad
    2a98:	200010be 	.word	0x200010be
    2a9c:	00007f8b 	.word	0x00007f8b

00002aa0 <flash_nrf_write>:
{
    2aa0:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    2aa4:	460e      	mov	r6, r1
	if (is_regular_addr_valid(addr, len)) {
    2aa6:	4630      	mov	r0, r6
    2aa8:	4619      	mov	r1, r3
{
    2aaa:	4617      	mov	r7, r2
    2aac:	461c      	mov	r4, r3
	if (is_regular_addr_valid(addr, len)) {
    2aae:	f003 ff0d 	bl	68cc <is_regular_addr_valid>
    2ab2:	b948      	cbnz	r0, 2ac8 <flash_nrf_write+0x28>
		LOG_ERR("invalid address: 0x%08lx:%zu",
    2ab4:	481b      	ldr	r0, [pc, #108]	; (2b24 <flash_nrf_write+0x84>)
    2ab6:	4623      	mov	r3, r4
    2ab8:	4632      	mov	r2, r6
    2aba:	2145      	movs	r1, #69	; 0x45
		LOG_ERR("not word-aligned: 0x%08lx:%zu",
    2abc:	f003 fd57 	bl	656e <z_log_minimal_printk>
		return -EINVAL;
    2ac0:	f06f 0015 	mvn.w	r0, #21
}
    2ac4:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
	if (!is_aligned_32(addr) || (len % sizeof(uint32_t))) {
    2ac8:	ea46 0504 	orr.w	r5, r6, r4
    2acc:	f015 0503 	ands.w	r5, r5, #3
    2ad0:	d004      	beq.n	2adc <flash_nrf_write+0x3c>
		LOG_ERR("not word-aligned: 0x%08lx:%zu",
    2ad2:	4815      	ldr	r0, [pc, #84]	; (2b28 <flash_nrf_write+0x88>)
    2ad4:	4623      	mov	r3, r4
    2ad6:	4632      	mov	r2, r6
    2ad8:	2145      	movs	r1, #69	; 0x45
    2ada:	e7ef      	b.n	2abc <flash_nrf_write+0x1c>
	if (!len) {
    2adc:	b1fc      	cbz	r4, 2b1e <flash_nrf_write+0x7e>
	if (pofcon_enabled) {
    2ade:	f8df 9050 	ldr.w	r9, [pc, #80]	; 2b30 <flash_nrf_write+0x90>
	while (w_ctx->len >= sizeof(uint32_t)) {
    2ae2:	192b      	adds	r3, r5, r4
    2ae4:	2b03      	cmp	r3, #3
    2ae6:	eba6 0805 	sub.w	r8, r6, r5
    2aea:	d806      	bhi.n	2afa <flash_nrf_write+0x5a>

#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE bool nrf_nvmc_ready_check(NRF_NVMC_Type const * p_reg)
{
    return (bool)(p_reg->READY & NVMC_READY_READY_Msk);
    2aec:	4a0f      	ldr	r2, [pc, #60]	; (2b2c <flash_nrf_write+0x8c>)
    2aee:	f8d2 3400 	ldr.w	r3, [r2, #1024]	; 0x400
	while (!nrfx_nvmc_write_done_check()) {
    2af2:	07db      	lsls	r3, r3, #31
    2af4:	d5fb      	bpl.n	2aee <flash_nrf_write+0x4e>
	return FLASH_OP_DONE;
    2af6:	2000      	movs	r0, #0
    2af8:	e7e4      	b.n	2ac4 <flash_nrf_write+0x24>
		if (SUSPEND_POFWARN()) {
    2afa:	f7ff ff5f 	bl	29bc <suspend_pofwarn>
    2afe:	b958      	cbnz	r0, 2b18 <flash_nrf_write+0x78>
				     UNALIGNED_GET((uint32_t *)w_ctx->data_addr));
    2b00:	1b7b      	subs	r3, r7, r5
		nrfx_nvmc_word_write(w_ctx->flash_addr,
    2b02:	4640      	mov	r0, r8
    2b04:	6819      	ldr	r1, [r3, #0]
    2b06:	f001 fb43 	bl	4190 <nrfx_nvmc_word_write>
	if (pofcon_enabled) {
    2b0a:	f899 3000 	ldrb.w	r3, [r9]
    2b0e:	b10b      	cbz	r3, 2b14 <flash_nrf_write+0x74>
    2b10:	f7ff ff3e 	bl	2990 <restore_pofwarn.part.0>
	w_ctx->len -= shift;
    2b14:	3d04      	subs	r5, #4
}
    2b16:	e7e4      	b.n	2ae2 <flash_nrf_write+0x42>
			return -ECANCELED;
    2b18:	f06f 008b 	mvn.w	r0, #139	; 0x8b
	return ret;
    2b1c:	e7d2      	b.n	2ac4 <flash_nrf_write+0x24>
		return 0;
    2b1e:	4620      	mov	r0, r4
    2b20:	e7d0      	b.n	2ac4 <flash_nrf_write+0x24>
    2b22:	bf00      	nop
    2b24:	00007f8b 	.word	0x00007f8b
    2b28:	00007fd1 	.word	0x00007fd1
    2b2c:	4001e000 	.word	0x4001e000
    2b30:	200010be 	.word	0x200010be

00002b34 <uarte_nrfx_poll_out>:
 *
 * @param dev UARTE device struct
 * @param c Character to send
 */
static void uarte_nrfx_poll_out(const struct device *dev, unsigned char c)
{
    2b34:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    2b36:	4604      	mov	r4, r0
	struct uarte_nrfx_data *data = dev->data;
    2b38:	6907      	ldr	r7, [r0, #16]
{
    2b3a:	460d      	mov	r5, r1
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    2b3c:	f004 f99d 	bl	6e7a <k_is_in_isr>
    2b40:	b990      	cbnz	r0, 2b68 <uarte_nrfx_poll_out+0x34>
	return !z_sys_post_kernel;
    2b42:	4b2c      	ldr	r3, [pc, #176]	; (2bf4 <uarte_nrfx_poll_out+0xc0>)
    2b44:	781b      	ldrb	r3, [r3, #0]
    2b46:	b17b      	cbz	r3, 2b68 <uarte_nrfx_poll_out+0x34>
{
    2b48:	2664      	movs	r6, #100	; 0x64
		NRFX_WAIT_FOR(is_tx_ready(dev), 100, 1, res);
    2b4a:	6860      	ldr	r0, [r4, #4]
    2b4c:	f003 ff55 	bl	69fa <is_tx_ready.isra.0>
    2b50:	b9e0      	cbnz	r0, 2b8c <uarte_nrfx_poll_out+0x58>
    2b52:	2001      	movs	r0, #1
    2b54:	f004 f8c7 	bl	6ce6 <nrfx_busy_wait>
    2b58:	3e01      	subs	r6, #1
    2b5a:	d1f6      	bne.n	2b4a <uarte_nrfx_poll_out+0x16>
    2b5c:	e7f4      	b.n	2b48 <uarte_nrfx_poll_out+0x14>
	__asm__ volatile(
    2b5e:	f386 8811 	msr	BASEPRI, r6
    2b62:	f3bf 8f6f 	isb	sy
		"cpsie i;"
		: : : "memory", "cc");
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
}
    2b66:	e7ef      	b.n	2b48 <uarte_nrfx_poll_out+0x14>
	__asm__ volatile(
    2b68:	f04f 0320 	mov.w	r3, #32
    2b6c:	f3ef 8611 	mrs	r6, BASEPRI
    2b70:	f383 8812 	msr	BASEPRI_MAX, r3
    2b74:	f3bf 8f6f 	isb	sy
#endif

	if (isr_mode) {
		while (1) {
			key = irq_lock();
			if (is_tx_ready(dev)) {
    2b78:	6860      	ldr	r0, [r4, #4]
    2b7a:	4631      	mov	r1, r6
    2b7c:	f003 ff3d 	bl	69fa <is_tx_ready.isra.0>
    2b80:	b990      	cbnz	r0, 2ba8 <uarte_nrfx_poll_out+0x74>
	__asm__ volatile(
    2b82:	f386 8811 	msr	BASEPRI, r6
    2b86:	f3bf 8f6f 	isb	sy
}
    2b8a:	e7ed      	b.n	2b68 <uarte_nrfx_poll_out+0x34>
	__asm__ volatile(
    2b8c:	f04f 0320 	mov.w	r3, #32
    2b90:	f3ef 8611 	mrs	r6, BASEPRI
    2b94:	f383 8812 	msr	BASEPRI_MAX, r3
    2b98:	f3bf 8f6f 	isb	sy
			if (is_tx_ready(dev)) {
    2b9c:	6860      	ldr	r0, [r4, #4]
    2b9e:	4631      	mov	r1, r6
    2ba0:	f003 ff2b 	bl	69fa <is_tx_ready.isra.0>
    2ba4:	2800      	cmp	r0, #0
    2ba6:	d0da      	beq.n	2b5e <uarte_nrfx_poll_out+0x2a>
		}
	} else {
		key = wait_tx_ready(dev);
	}

	*data->char_out = c;
    2ba8:	693b      	ldr	r3, [r7, #16]
    2baa:	701d      	strb	r5, [r3, #0]
	const struct uarte_nrfx_config *config = dev->config;
    2bac:	6862      	ldr	r2, [r4, #4]

NRF_STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,
                                               uint8_t  const * p_buffer,
                                               size_t           length)
{
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    2bae:	6938      	ldr	r0, [r7, #16]
	return config->uarte_regs;
    2bb0:	6813      	ldr	r3, [r2, #0]
    2bb2:	f8c3 0544 	str.w	r0, [r3, #1348]	; 0x544
    p_reg->TXD.MAXCNT = length;
    2bb6:	2001      	movs	r0, #1
    2bb8:	f8c3 0548 	str.w	r0, [r3, #1352]	; 0x548
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2bbc:	2000      	movs	r0, #0
    2bbe:	f8c3 0120 	str.w	r0, [r3, #288]	; 0x120
    2bc2:	f8d3 5120 	ldr.w	r5, [r3, #288]	; 0x120
    2bc6:	f8c3 0158 	str.w	r0, [r3, #344]	; 0x158
	if (config->flags & UARTE_CFG_FLAG_LOW_POWER) {
    2bca:	6852      	ldr	r2, [r2, #4]
    2bcc:	f8d3 0158 	ldr.w	r0, [r3, #344]	; 0x158
    2bd0:	06d2      	lsls	r2, r2, #27
    2bd2:	d508      	bpl.n	2be6 <uarte_nrfx_poll_out+0xb2>
	return config->uarte_regs;
    2bd4:	6862      	ldr	r2, [r4, #4]
    2bd6:	6812      	ldr	r2, [r2, #0]
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
    2bd8:	2008      	movs	r0, #8
    2bda:	f8c2 0500 	str.w	r0, [r2, #1280]	; 0x500
    p_reg->INTENSET = mask;
    2bde:	f44f 0280 	mov.w	r2, #4194304	; 0x400000
    2be2:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2be6:	2201      	movs	r2, #1
    2be8:	609a      	str	r2, [r3, #8]
	__asm__ volatile(
    2bea:	f381 8811 	msr	BASEPRI, r1
    2bee:	f3bf 8f6f 	isb	sy
	tx_start(dev, data->char_out, 1);

	irq_unlock(key);
}
    2bf2:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    2bf4:	200014d3 	.word	0x200014d3

00002bf8 <uarte_nrfx_configure>:
{
    2bf8:	b5f0      	push	{r4, r5, r6, r7, lr}
	switch (cfg->stop_bits) {
    2bfa:	794b      	ldrb	r3, [r1, #5]
    2bfc:	2b01      	cmp	r3, #1
    2bfe:	d026      	beq.n	2c4e <uarte_nrfx_configure+0x56>
    2c00:	2b03      	cmp	r3, #3
    2c02:	d121      	bne.n	2c48 <uarte_nrfx_configure+0x50>
		uarte_cfg.stop = NRF_UARTE_STOP_TWO;
    2c04:	2510      	movs	r5, #16
	if (cfg->data_bits != UART_CFG_DATA_BITS_8) {
    2c06:	798b      	ldrb	r3, [r1, #6]
    2c08:	2b03      	cmp	r3, #3
    2c0a:	d11d      	bne.n	2c48 <uarte_nrfx_configure+0x50>
	switch (cfg->flow_ctrl) {
    2c0c:	79ce      	ldrb	r6, [r1, #7]
    2c0e:	b10e      	cbz	r6, 2c14 <uarte_nrfx_configure+0x1c>
    2c10:	2e01      	cmp	r6, #1
    2c12:	d119      	bne.n	2c48 <uarte_nrfx_configure+0x50>
	switch (cfg->parity) {
    2c14:	790a      	ldrb	r2, [r1, #4]
    2c16:	b112      	cbz	r2, 2c1e <uarte_nrfx_configure+0x26>
    2c18:	2a02      	cmp	r2, #2
    2c1a:	d115      	bne.n	2c48 <uarte_nrfx_configure+0x50>
		uarte_cfg.parity = NRF_UARTE_PARITY_INCLUDED;
    2c1c:	220e      	movs	r2, #14
	if (baudrate_set(dev, cfg->baudrate) != 0) {
    2c1e:	680b      	ldr	r3, [r1, #0]
	return config->uarte_regs;
    2c20:	6844      	ldr	r4, [r0, #4]
	switch (baudrate) {
    2c22:	f5b3 4f16 	cmp.w	r3, #38400	; 0x9600
	return config->uarte_regs;
    2c26:	6827      	ldr	r7, [r4, #0]
	switch (baudrate) {
    2c28:	d067      	beq.n	2cfa <uarte_nrfx_configure+0x102>
    2c2a:	d82d      	bhi.n	2c88 <uarte_nrfx_configure+0x90>
    2c2c:	f5b3 5f16 	cmp.w	r3, #9600	; 0x2580
    2c30:	d066      	beq.n	2d00 <uarte_nrfx_configure+0x108>
    2c32:	d816      	bhi.n	2c62 <uarte_nrfx_configure+0x6a>
    2c34:	f5b3 6f96 	cmp.w	r3, #1200	; 0x4b0
    2c38:	d064      	beq.n	2d04 <uarte_nrfx_configure+0x10c>
    2c3a:	d80a      	bhi.n	2c52 <uarte_nrfx_configure+0x5a>
    2c3c:	f5b3 7f96 	cmp.w	r3, #300	; 0x12c
    2c40:	d063      	beq.n	2d0a <uarte_nrfx_configure+0x112>
    2c42:	f5b3 7f16 	cmp.w	r3, #600	; 0x258
    2c46:	d063      	beq.n	2d10 <uarte_nrfx_configure+0x118>
		return -ENOTSUP;
    2c48:	f06f 0085 	mvn.w	r0, #133	; 0x85
    2c4c:	e054      	b.n	2cf8 <uarte_nrfx_configure+0x100>
	switch (cfg->stop_bits) {
    2c4e:	2500      	movs	r5, #0
    2c50:	e7d9      	b.n	2c06 <uarte_nrfx_configure+0xe>
	switch (baudrate) {
    2c52:	f5b3 6f16 	cmp.w	r3, #2400	; 0x960
    2c56:	d05e      	beq.n	2d16 <uarte_nrfx_configure+0x11e>
    2c58:	f5b3 5f96 	cmp.w	r3, #4800	; 0x12c0
    2c5c:	d1f4      	bne.n	2c48 <uarte_nrfx_configure+0x50>
		nrf_baudrate = NRF_UARTE_BAUDRATE_4800;
    2c5e:	4b38      	ldr	r3, [pc, #224]	; (2d40 <uarte_nrfx_configure+0x148>)
    2c60:	e03c      	b.n	2cdc <uarte_nrfx_configure+0xe4>
	switch (baudrate) {
    2c62:	f5b3 4fe1 	cmp.w	r3, #28800	; 0x7080
    2c66:	d059      	beq.n	2d1c <uarte_nrfx_configure+0x124>
    2c68:	d807      	bhi.n	2c7a <uarte_nrfx_configure+0x82>
    2c6a:	f5b3 5f61 	cmp.w	r3, #14400	; 0x3840
    2c6e:	d057      	beq.n	2d20 <uarte_nrfx_configure+0x128>
    2c70:	f5b3 4f96 	cmp.w	r3, #19200	; 0x4b00
    2c74:	d1e8      	bne.n	2c48 <uarte_nrfx_configure+0x50>
		nrf_baudrate = NRF_UARTE_BAUDRATE_19200;
    2c76:	4b33      	ldr	r3, [pc, #204]	; (2d44 <uarte_nrfx_configure+0x14c>)
    2c78:	e030      	b.n	2cdc <uarte_nrfx_configure+0xe4>
	switch (baudrate) {
    2c7a:	f647 2412 	movw	r4, #31250	; 0x7a12
    2c7e:	42a3      	cmp	r3, r4
    2c80:	d1e2      	bne.n	2c48 <uarte_nrfx_configure+0x50>
		nrf_baudrate = NRF_UARTE_BAUDRATE_31250;
    2c82:	f44f 0300 	mov.w	r3, #8388608	; 0x800000
    2c86:	e029      	b.n	2cdc <uarte_nrfx_configure+0xe4>
	switch (baudrate) {
    2c88:	f5b3 3f61 	cmp.w	r3, #230400	; 0x38400
    2c8c:	d04a      	beq.n	2d24 <uarte_nrfx_configure+0x12c>
    2c8e:	d813      	bhi.n	2cb8 <uarte_nrfx_configure+0xc0>
    2c90:	f5b3 3f96 	cmp.w	r3, #76800	; 0x12c00
    2c94:	d049      	beq.n	2d2a <uarte_nrfx_configure+0x132>
    2c96:	d809      	bhi.n	2cac <uarte_nrfx_configure+0xb4>
    2c98:	f64d 24c0 	movw	r4, #56000	; 0xdac0
    2c9c:	42a3      	cmp	r3, r4
    2c9e:	d046      	beq.n	2d2e <uarte_nrfx_configure+0x136>
    2ca0:	f5b3 4f61 	cmp.w	r3, #57600	; 0xe100
    2ca4:	d1d0      	bne.n	2c48 <uarte_nrfx_configure+0x50>
		nrf_baudrate = NRF_UARTE_BAUDRATE_57600;
    2ca6:	f44f 036b 	mov.w	r3, #15400960	; 0xeb0000
    2caa:	e017      	b.n	2cdc <uarte_nrfx_configure+0xe4>
	switch (baudrate) {
    2cac:	f5b3 3fe1 	cmp.w	r3, #115200	; 0x1c200
    2cb0:	d1ca      	bne.n	2c48 <uarte_nrfx_configure+0x50>
		nrf_baudrate = NRF_UARTE_BAUDRATE_115200;
    2cb2:	f04f 73eb 	mov.w	r3, #30801920	; 0x1d60000
    2cb6:	e011      	b.n	2cdc <uarte_nrfx_configure+0xe4>
	switch (baudrate) {
    2cb8:	f5b3 2f61 	cmp.w	r3, #921600	; 0xe1000
    2cbc:	d03a      	beq.n	2d34 <uarte_nrfx_configure+0x13c>
    2cbe:	d808      	bhi.n	2cd2 <uarte_nrfx_configure+0xda>
    2cc0:	4c21      	ldr	r4, [pc, #132]	; (2d48 <uarte_nrfx_configure+0x150>)
    2cc2:	42a3      	cmp	r3, r4
    2cc4:	d039      	beq.n	2d3a <uarte_nrfx_configure+0x142>
    2cc6:	f5b3 2fe1 	cmp.w	r3, #460800	; 0x70800
    2cca:	d1bd      	bne.n	2c48 <uarte_nrfx_configure+0x50>
		nrf_baudrate = NRF_UARTE_BAUDRATE_460800;
    2ccc:	f04f 63e8 	mov.w	r3, #121634816	; 0x7400000
    2cd0:	e004      	b.n	2cdc <uarte_nrfx_configure+0xe4>
	switch (baudrate) {
    2cd2:	4c1e      	ldr	r4, [pc, #120]	; (2d4c <uarte_nrfx_configure+0x154>)
    2cd4:	42a3      	cmp	r3, r4
    2cd6:	d1b7      	bne.n	2c48 <uarte_nrfx_configure+0x50>
		nrf_baudrate = NRF_UARTE_BAUDRATE_1000000;
    2cd8:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
	struct uarte_nrfx_data *data = dev->data;
    2cdc:	6904      	ldr	r4, [r0, #16]
    p_reg->BAUDRATE = baudrate;
    2cde:	f8c7 3524 	str.w	r3, [r7, #1316]	; 0x524
	return config->uarte_regs;
    2ce2:	6843      	ldr	r3, [r0, #4]
                    | (uint32_t)p_cfg->hwfc;
    2ce4:	4335      	orrs	r5, r6
    2ce6:	681b      	ldr	r3, [r3, #0]
    2ce8:	432a      	orrs	r2, r5
    p_reg->CONFIG = (uint32_t)p_cfg->parity
    2cea:	f8c3 256c 	str.w	r2, [r3, #1388]	; 0x56c
	data->uart_config = *cfg;
    2cee:	c903      	ldmia	r1, {r0, r1}
    2cf0:	1d23      	adds	r3, r4, #4
    2cf2:	e883 0003 	stmia.w	r3, {r0, r1}
	return 0;
    2cf6:	2000      	movs	r0, #0
}
    2cf8:	bdf0      	pop	{r4, r5, r6, r7, pc}
		nrf_baudrate = NRF_UARTE_BAUDRATE_38400;
    2cfa:	f44f 031d 	mov.w	r3, #10289152	; 0x9d0000
    2cfe:	e7ed      	b.n	2cdc <uarte_nrfx_configure+0xe4>
		nrf_baudrate = NRF_UARTE_BAUDRATE_9600;
    2d00:	4b13      	ldr	r3, [pc, #76]	; (2d50 <uarte_nrfx_configure+0x158>)
    2d02:	e7eb      	b.n	2cdc <uarte_nrfx_configure+0xe4>
		nrf_baudrate = NRF_UARTE_BAUDRATE_1200;
    2d04:	f44f 239e 	mov.w	r3, #323584	; 0x4f000
    2d08:	e7e8      	b.n	2cdc <uarte_nrfx_configure+0xe4>
		nrf_baudrate = 0x00014000;
    2d0a:	f44f 33a0 	mov.w	r3, #81920	; 0x14000
    2d0e:	e7e5      	b.n	2cdc <uarte_nrfx_configure+0xe4>
	switch (baudrate) {
    2d10:	f44f 331c 	mov.w	r3, #159744	; 0x27000
    2d14:	e7e2      	b.n	2cdc <uarte_nrfx_configure+0xe4>
		nrf_baudrate = NRF_UARTE_BAUDRATE_2400;
    2d16:	f44f 231d 	mov.w	r3, #643072	; 0x9d000
    2d1a:	e7df      	b.n	2cdc <uarte_nrfx_configure+0xe4>
		nrf_baudrate = NRF_UARTE_BAUDRATE_28800;
    2d1c:	4b0d      	ldr	r3, [pc, #52]	; (2d54 <uarte_nrfx_configure+0x15c>)
    2d1e:	e7dd      	b.n	2cdc <uarte_nrfx_configure+0xe4>
		nrf_baudrate = NRF_UARTE_BAUDRATE_14400;
    2d20:	4b0d      	ldr	r3, [pc, #52]	; (2d58 <uarte_nrfx_configure+0x160>)
    2d22:	e7db      	b.n	2cdc <uarte_nrfx_configure+0xe4>
		nrf_baudrate = NRF_UARTE_BAUDRATE_230400;
    2d24:	f04f 736c 	mov.w	r3, #61865984	; 0x3b00000
    2d28:	e7d8      	b.n	2cdc <uarte_nrfx_configure+0xe4>
		nrf_baudrate = NRF_UARTE_BAUDRATE_76800;
    2d2a:	4b0c      	ldr	r3, [pc, #48]	; (2d5c <uarte_nrfx_configure+0x164>)
    2d2c:	e7d6      	b.n	2cdc <uarte_nrfx_configure+0xe4>
		nrf_baudrate = NRF_UARTE_BAUDRATE_56000;
    2d2e:	f44f 0365 	mov.w	r3, #15007744	; 0xe50000
    2d32:	e7d3      	b.n	2cdc <uarte_nrfx_configure+0xe4>
		nrf_baudrate = NRF_UARTE_BAUDRATE_921600;
    2d34:	f04f 6370 	mov.w	r3, #251658240	; 0xf000000
    2d38:	e7d0      	b.n	2cdc <uarte_nrfx_configure+0xe4>
		nrf_baudrate = NRF_UARTE_BAUDRATE_250000;
    2d3a:	f04f 6380 	mov.w	r3, #67108864	; 0x4000000
    2d3e:	e7cd      	b.n	2cdc <uarte_nrfx_configure+0xe4>
    2d40:	0013b000 	.word	0x0013b000
    2d44:	004ea000 	.word	0x004ea000
    2d48:	0003d090 	.word	0x0003d090
    2d4c:	000f4240 	.word	0x000f4240
    2d50:	00275000 	.word	0x00275000
    2d54:	0075c000 	.word	0x0075c000
    2d58:	003af000 	.word	0x003af000
    2d5c:	013a9000 	.word	0x013a9000

00002d60 <uarte_instance_init.constprop.0>:
	nrfx_gppi_channels_enable(BIT(data->ppi_ch_endtx));

	return 0;
}

static int uarte_instance_init(const struct device *dev,
    2d60:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
	const struct uarte_nrfx_config *config = dev->config;
    2d64:	6847      	ldr	r7, [r0, #4]
			       uint8_t interrupts_active)
{
	int err;
	NRF_UARTE_Type *uarte = get_uarte_instance(dev);
	struct uarte_nrfx_data *data = dev->data;
    2d66:	6906      	ldr	r6, [r0, #16]
	return config->uarte_regs;
    2d68:	683c      	ldr	r4, [r7, #0]
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
    2d6a:	2100      	movs	r1, #0
    2d6c:	f8c4 1500 	str.w	r1, [r4, #1280]	; 0x500
	const struct uarte_nrfx_config *cfg = dev->config;

	nrf_uarte_disable(uarte);

	data->dev = dev;
    2d70:	6030      	str	r0, [r6, #0]

#ifdef CONFIG_PINCTRL
	err = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
    2d72:	f8d7 900c 	ldr.w	r9, [r7, #12]
static int uarte_instance_init(const struct device *dev,
    2d76:	4680      	mov	r8, r0
				      uint8_t id)
{
	int ret;
	const struct pinctrl_state *state;

	ret = pinctrl_lookup_state(config, id, &state);
    2d78:	aa01      	add	r2, sp, #4
    2d7a:	4648      	mov	r0, r9
    2d7c:	f003 fea4 	bl	6ac8 <pinctrl_lookup_state>
	if (ret < 0) {
    2d80:	1e05      	subs	r5, r0, #0
    2d82:	db1e      	blt.n	2dc2 <uarte_instance_init.constprop.0+0x62>
		return ret;
	}

	return pinctrl_apply_state_direct(config, state);
    2d84:	9b01      	ldr	r3, [sp, #4]
	return pinctrl_configure_pins(state->pins, state->pin_cnt, reg);
    2d86:	f8d9 2000 	ldr.w	r2, [r9]
    2d8a:	7919      	ldrb	r1, [r3, #4]
    2d8c:	6818      	ldr	r0, [r3, #0]
    2d8e:	f000 faa5 	bl	32dc <pinctrl_configure_pins>
	if (err < 0) {
    2d92:	1e05      	subs	r5, r0, #0
    2d94:	db15      	blt.n	2dc2 <uarte_instance_init.constprop.0+0x62>
	}
#else
	uarte_nrfx_pins_configure(dev, false);
#endif /* CONFIG_PINCTRL */

	err = uarte_nrfx_configure(dev, &data->uart_config);
    2d96:	1d31      	adds	r1, r6, #4
    2d98:	4640      	mov	r0, r8
    2d9a:	f7ff ff2d 	bl	2bf8 <uarte_nrfx_configure>
	if (err) {
    2d9e:	4605      	mov	r5, r0
    2da0:	b978      	cbnz	r0, 2dc2 <uarte_instance_init.constprop.0+0x62>
		return err;
	}

	if (IS_ENABLED(CONFIG_UART_ENHANCED_POLL_OUT) &&
	    cfg->flags & UARTE_CFG_FLAG_PPI_ENDTX) {
    2da2:	687b      	ldr	r3, [r7, #4]
	if (IS_ENABLED(CONFIG_UART_ENHANCED_POLL_OUT) &&
    2da4:	0799      	lsls	r1, r3, #30
    2da6:	d524      	bpl.n	2df2 <uarte_instance_init.constprop.0+0x92>
	ret = gppi_channel_alloc(&data->ppi_ch_endtx);
    2da8:	f106 0018 	add.w	r0, r6, #24
    2dac:	f001 f9fe 	bl	41ac <nrfx_ppi_channel_alloc>
	if (ret != NRFX_SUCCESS) {
    2db0:	4b24      	ldr	r3, [pc, #144]	; (2e44 <uarte_instance_init.constprop.0+0xe4>)
    2db2:	4298      	cmp	r0, r3
    2db4:	d009      	beq.n	2dca <uarte_instance_init.constprop.0+0x6a>
		LOG_ERR("Failed to allocate PPI Channel");
    2db6:	4824      	ldr	r0, [pc, #144]	; (2e48 <uarte_instance_init.constprop.0+0xe8>)
    2db8:	2145      	movs	r1, #69	; 0x45
    2dba:	f003 fbd8 	bl	656e <z_log_minimal_printk>
		return -EIO;
    2dbe:	f06f 0504 	mvn.w	r5, #4

	/* switch off transmitter to save an energy */
	nrf_uarte_task_trigger(uarte, NRF_UARTE_TASK_STOPTX);

	return 0;
}
    2dc2:	4628      	mov	r0, r5
    2dc4:	b003      	add	sp, #12
    2dc6:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
NRF_STATIC_INLINE void nrf_ppi_channel_endpoint_setup(NRF_PPI_Type *    p_reg,
                                                      nrf_ppi_channel_t channel,
                                                      uint32_t          eep,
                                                      uint32_t          tep)
{
    p_reg->CH[(uint32_t) channel].EEP = eep;
    2dca:	7e33      	ldrb	r3, [r6, #24]
    2dcc:	00db      	lsls	r3, r3, #3
    2dce:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    2dd2:	f503 33f8 	add.w	r3, r3, #126976	; 0x1f000
    return (uint32_t)p_reg + (uint32_t)task;
    2dd6:	f104 020c 	add.w	r2, r4, #12
    return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
    2dda:	f504 7190 	add.w	r1, r4, #288	; 0x120
    2dde:	f8c3 1510 	str.w	r1, [r3, #1296]	; 0x510
    p_reg->CH[(uint32_t) channel].TEP = tep;
    2de2:	f8c3 2514 	str.w	r2, [r3, #1300]	; 0x514
	nrfx_gppi_channels_enable(BIT(data->ppi_ch_endtx));
    2de6:	7e32      	ldrb	r2, [r6, #24]
    2de8:	2301      	movs	r3, #1
    2dea:	4093      	lsls	r3, r2
    p_reg->CHENSET = mask;
    2dec:	4a17      	ldr	r2, [pc, #92]	; (2e4c <uarte_instance_init.constprop.0+0xec>)
    2dee:	f8c2 3504 	str.w	r3, [r2, #1284]	; 0x504
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
    2df2:	2308      	movs	r3, #8
    2df4:	f8c4 3500 	str.w	r3, [r4, #1280]	; 0x500
		if (!cfg->disable_rx) {
    2df8:	7a3b      	ldrb	r3, [r7, #8]
    2dfa:	b953      	cbnz	r3, 2e12 <uarte_instance_init.constprop.0+0xb2>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2dfc:	f8c4 3110 	str.w	r3, [r4, #272]	; 0x110
    2e00:	f8d4 3110 	ldr.w	r3, [r4, #272]	; 0x110

NRF_STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
                                               uint8_t *        p_buffer,
                                               size_t           length)
{
    p_reg->RXD.PTR    = (uint32_t)p_buffer;
    2e04:	6973      	ldr	r3, [r6, #20]
    2e06:	f8c4 3534 	str.w	r3, [r4, #1332]	; 0x534
    p_reg->RXD.MAXCNT = length;
    2e0a:	2301      	movs	r3, #1
    2e0c:	f8c4 3538 	str.w	r3, [r4, #1336]	; 0x538
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2e10:	6023      	str	r3, [r4, #0]
	if (!(cfg->flags & UARTE_CFG_FLAG_PPI_ENDTX)) {
    2e12:	687b      	ldr	r3, [r7, #4]
    2e14:	079a      	lsls	r2, r3, #30
    p_reg->INTENSET = mask;
    2e16:	bf5c      	itt	pl
    2e18:	f44f 7380 	movpl.w	r3, #256	; 0x100
    2e1c:	f8c4 3304 	strpl.w	r3, [r4, #772]	; 0x304
	if (cfg->flags & UARTE_CFG_FLAG_LOW_POWER) {
    2e20:	687b      	ldr	r3, [r7, #4]
    2e22:	06db      	lsls	r3, r3, #27
    2e24:	bf44      	itt	mi
    2e26:	f44f 0380 	movmi.w	r3, #4194304	; 0x400000
    2e2a:	f8c4 3304 	strmi.w	r3, [r4, #772]	; 0x304
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    2e2e:	6933      	ldr	r3, [r6, #16]
    2e30:	f8c4 3544 	str.w	r3, [r4, #1348]	; 0x544
    p_reg->TXD.MAXCNT = length;
    2e34:	2300      	movs	r3, #0
    2e36:	f8c4 3548 	str.w	r3, [r4, #1352]	; 0x548
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2e3a:	2301      	movs	r3, #1
    2e3c:	60a3      	str	r3, [r4, #8]
    2e3e:	60e3      	str	r3, [r4, #12]
	return 0;
    2e40:	e7bf      	b.n	2dc2 <uarte_instance_init.constprop.0+0x62>
    2e42:	bf00      	nop
    2e44:	0bad0000 	.word	0x0bad0000
    2e48:	00008018 	.word	0x00008018
    2e4c:	4001f000 	.word	0x4001f000

00002e50 <compare_int_lock>:
	return 0;
#endif
}

static bool compare_int_lock(int32_t chan)
{
    2e50:	b570      	push	{r4, r5, r6, lr}
	atomic_val_t prev = atomic_and(&int_mask, ~BIT(chan));
    2e52:	2301      	movs	r3, #1
    2e54:	4083      	lsls	r3, r0
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    2e56:	4a0e      	ldr	r2, [pc, #56]	; (2e90 <compare_int_lock+0x40>)
    2e58:	f3bf 8f5b 	dmb	ish
    2e5c:	43dc      	mvns	r4, r3
    2e5e:	e852 1f00 	ldrex	r1, [r2]
    2e62:	ea01 0504 	and.w	r5, r1, r4
    2e66:	e842 5600 	strex	r6, r5, [r2]
    2e6a:	2e00      	cmp	r6, #0
    2e6c:	d1f7      	bne.n	2e5e <compare_int_lock+0xe>
    2e6e:	f3bf 8f5b 	dmb	ish

	nrf_rtc_int_disable(RTC, RTC_CHANNEL_INT_MASK(chan));
    2e72:	f44f 3280 	mov.w	r2, #65536	; 0x10000
    2e76:	4082      	lsls	r2, r0
    2e78:	4806      	ldr	r0, [pc, #24]	; (2e94 <compare_int_lock+0x44>)
    2e7a:	f8c0 2308 	str.w	r2, [r0, #776]	; 0x308
  __ASM volatile ("dmb 0xF":::"memory");
    2e7e:	f3bf 8f5f 	dmb	sy
  __ASM volatile ("isb 0xF":::"memory");
    2e82:	f3bf 8f6f 	isb	sy

	__DMB();
	__ISB();

	return prev & BIT(chan);
    2e86:	420b      	tst	r3, r1
}
    2e88:	bf14      	ite	ne
    2e8a:	2001      	movne	r0, #1
    2e8c:	2000      	moveq	r0, #0
    2e8e:	bd70      	pop	{r4, r5, r6, pc}
    2e90:	20000ee4 	.word	0x20000ee4
    2e94:	40011000 	.word	0x40011000

00002e98 <sys_clock_timeout_handler>:
}

static void sys_clock_timeout_handler(int32_t chan,
				      uint64_t expire_time,
				      void *user_data)
{
    2e98:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	uint32_t cc_value = absolute_time_to_cc(expire_time);
	uint64_t dticks = (expire_time - last_count) / CYC_PER_TICK;
    2e9a:	491b      	ldr	r1, [pc, #108]	; (2f08 <sys_clock_timeout_handler+0x70>)
{
    2e9c:	4604      	mov	r4, r0
	return absolute_time & COUNTER_MAX;
    2e9e:	f022 457f 	bic.w	r5, r2, #4278190080	; 0xff000000
	uint64_t dticks = (expire_time - last_count) / CYC_PER_TICK;
    2ea2:	6808      	ldr	r0, [r1, #0]

	last_count += dticks * CYC_PER_TICK;
    2ea4:	e9c1 2300 	strd	r2, r3, [r1]
	return (cc_value >= ANCHOR_RANGE_START) && (cc_value < ANCHOR_RANGE_END);
    2ea8:	f5a5 1300 	sub.w	r3, r5, #2097152	; 0x200000
	uint64_t dticks = (expire_time - last_count) / CYC_PER_TICK;
    2eac:	1a10      	subs	r0, r2, r0
	if (in_anchor_range(cc_value)) {
    2eae:	f5b3 0f40 	cmp.w	r3, #12582912	; 0xc00000
    2eb2:	d30f      	bcc.n	2ed4 <sys_clock_timeout_handler+0x3c>
		 */
		compare_set(chan, last_count + CYC_PER_TICK,
					  sys_clock_timeout_handler, NULL);
	}

	sys_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
    2eb4:	f001 fad6 	bl	4464 <sys_clock_announce>
    return p_reg->CC[ch];
    2eb8:	00a3      	lsls	r3, r4, #2
    2eba:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    2ebe:	f503 3388 	add.w	r3, r3, #69632	; 0x11000
    2ec2:	f8d3 2540 	ldr.w	r2, [r3, #1344]	; 0x540
			   (int32_t)dticks : (dticks > 0));

	if (cc_value == get_comparator(chan)) {
    2ec6:	4295      	cmp	r5, r2
    2ec8:	d11d      	bne.n	2f06 <sys_clock_timeout_handler+0x6e>
    p_reg->CC[ch] = cc_val;
    2eca:	f44f 0200 	mov.w	r2, #8388608	; 0x800000
    2ece:	f8c3 2540 	str.w	r2, [r3, #1344]	; 0x540
}
    2ed2:	e012      	b.n	2efa <sys_clock_timeout_handler+0x62>
		anchor = (((uint64_t)overflow_cnt) << COUNTER_BIT_WIDTH) + cc_value;
    2ed4:	4b0d      	ldr	r3, [pc, #52]	; (2f0c <sys_clock_timeout_handler+0x74>)
    2ed6:	681b      	ldr	r3, [r3, #0]
    2ed8:	0a1a      	lsrs	r2, r3, #8
    2eda:	061b      	lsls	r3, r3, #24
    2edc:	195e      	adds	r6, r3, r5
    2ede:	4b0c      	ldr	r3, [pc, #48]	; (2f10 <sys_clock_timeout_handler+0x78>)
    2ee0:	f142 0700 	adc.w	r7, r2, #0
    2ee4:	e9c3 6700 	strd	r6, r7, [r3]
	sys_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
    2ee8:	f001 fabc 	bl	4464 <sys_clock_announce>
    return p_reg->CC[ch];
    2eec:	4a09      	ldr	r2, [pc, #36]	; (2f14 <sys_clock_timeout_handler+0x7c>)
    2eee:	f504 73a8 	add.w	r3, r4, #336	; 0x150
    2ef2:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
	if (cc_value == get_comparator(chan)) {
    2ef6:	429d      	cmp	r5, r3
    2ef8:	d105      	bne.n	2f06 <sys_clock_timeout_handler+0x6e>
    p_reg->EVTENSET = mask;
    2efa:	4a06      	ldr	r2, [pc, #24]	; (2f14 <sys_clock_timeout_handler+0x7c>)
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    2efc:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    2f00:	40a3      	lsls	r3, r4
    2f02:	f8c2 3344 	str.w	r3, [r2, #836]	; 0x344
		if (!anchor_updated) {
			set_comparator(chan, COUNTER_HALF_SPAN);
		}
		event_enable(chan);
	}
}
    2f06:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    2f08:	20000158 	.word	0x20000158
    2f0c:	20000ee8 	.word	0x20000ee8
    2f10:	20000160 	.word	0x20000160
    2f14:	40011000 	.word	0x40011000

00002f18 <compare_int_unlock>:
	if (key) {
    2f18:	b311      	cbz	r1, 2f60 <compare_int_unlock+0x48>
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    2f1a:	f3bf 8f5b 	dmb	ish
		atomic_or(&int_mask, BIT(chan));
    2f1e:	2301      	movs	r3, #1
    2f20:	4a10      	ldr	r2, [pc, #64]	; (2f64 <compare_int_unlock+0x4c>)
    2f22:	4083      	lsls	r3, r0
    2f24:	e852 cf00 	ldrex	ip, [r2]
    2f28:	ea4c 0c03 	orr.w	ip, ip, r3
    2f2c:	e842 c100 	strex	r1, ip, [r2]
    2f30:	2900      	cmp	r1, #0
    2f32:	d1f7      	bne.n	2f24 <compare_int_unlock+0xc>
    2f34:	f3bf 8f5b 	dmb	ish
    p_reg->INTENSET = mask;
    2f38:	4a0b      	ldr	r2, [pc, #44]	; (2f68 <compare_int_unlock+0x50>)
		nrf_rtc_int_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    2f3a:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    2f3e:	4083      	lsls	r3, r0
    2f40:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
	return __atomic_load_n(target, __ATOMIC_SEQ_CST);
    2f44:	4b09      	ldr	r3, [pc, #36]	; (2f6c <compare_int_unlock+0x54>)
    2f46:	f3bf 8f5b 	dmb	ish
    2f4a:	681b      	ldr	r3, [r3, #0]
    2f4c:	f3bf 8f5b 	dmb	ish
		if (atomic_get(&force_isr_mask) & BIT(chan)) {
    2f50:	40c3      	lsrs	r3, r0
    2f52:	07db      	lsls	r3, r3, #31
    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    2f54:	bf42      	ittt	mi
    2f56:	4b06      	ldrmi	r3, [pc, #24]	; (2f70 <compare_int_unlock+0x58>)
    2f58:	f44f 3200 	movmi.w	r2, #131072	; 0x20000
    2f5c:	f8c3 2100 	strmi.w	r2, [r3, #256]	; 0x100
}
    2f60:	4770      	bx	lr
    2f62:	bf00      	nop
    2f64:	20000ee4 	.word	0x20000ee4
    2f68:	40011000 	.word	0x40011000
    2f6c:	20000ee0 	.word	0x20000ee0
    2f70:	e000e100 	.word	0xe000e100

00002f74 <z_nrf_rtc_timer_read>:
	uint64_t val = ((uint64_t)overflow_cnt) << COUNTER_BIT_WIDTH;
    2f74:	4b0d      	ldr	r3, [pc, #52]	; (2fac <z_nrf_rtc_timer_read+0x38>)
    2f76:	6818      	ldr	r0, [r3, #0]
    2f78:	0a01      	lsrs	r1, r0, #8
    2f7a:	0600      	lsls	r0, r0, #24
  __ASM volatile ("dmb 0xF":::"memory");
    2f7c:	f3bf 8f5f 	dmb	sy
     return p_reg->COUNTER;
    2f80:	4b0b      	ldr	r3, [pc, #44]	; (2fb0 <z_nrf_rtc_timer_read+0x3c>)
    2f82:	f8d3 3504 	ldr.w	r3, [r3, #1284]	; 0x504
	val += cntr;
    2f86:	1818      	adds	r0, r3, r0
    2f88:	f141 0100 	adc.w	r1, r1, #0
	if (cntr < OVERFLOW_RISK_RANGE_END) {
    2f8c:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
    2f90:	d20a      	bcs.n	2fa8 <z_nrf_rtc_timer_read+0x34>
		if (val < anchor) {
    2f92:	4b08      	ldr	r3, [pc, #32]	; (2fb4 <z_nrf_rtc_timer_read+0x40>)
    2f94:	e9d3 2300 	ldrd	r2, r3, [r3]
    2f98:	4290      	cmp	r0, r2
    2f9a:	eb71 0303 	sbcs.w	r3, r1, r3
    2f9e:	d203      	bcs.n	2fa8 <z_nrf_rtc_timer_read+0x34>
			val += COUNTER_SPAN;
    2fa0:	f110 7080 	adds.w	r0, r0, #16777216	; 0x1000000
    2fa4:	f141 0100 	adc.w	r1, r1, #0
}
    2fa8:	4770      	bx	lr
    2faa:	bf00      	nop
    2fac:	20000ee8 	.word	0x20000ee8
    2fb0:	40011000 	.word	0x40011000
    2fb4:	20000160 	.word	0x20000160

00002fb8 <compare_set>:
{
    2fb8:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    2fbc:	4614      	mov	r4, r2
    2fbe:	461d      	mov	r5, r3
    2fc0:	4607      	mov	r7, r0
	key = compare_int_lock(chan);
    2fc2:	f7ff ff45 	bl	2e50 <compare_int_lock>
    2fc6:	9000      	str	r0, [sp, #0]
	uint64_t curr_time = z_nrf_rtc_timer_read();
    2fc8:	f7ff ffd4 	bl	2f74 <z_nrf_rtc_timer_read>
	if (curr_time < target_time) {
    2fcc:	42a0      	cmp	r0, r4
    2fce:	eb71 0305 	sbcs.w	r3, r1, r5
    2fd2:	d27a      	bcs.n	30ca <compare_set+0x112>
		if (target_time - curr_time > COUNTER_SPAN) {
    2fd4:	4b46      	ldr	r3, [pc, #280]	; (30f0 <compare_set+0x138>)
    2fd6:	1a20      	subs	r0, r4, r0
    2fd8:	eb65 0101 	sbc.w	r1, r5, r1
    2fdc:	4298      	cmp	r0, r3
    2fde:	f171 0100 	sbcs.w	r1, r1, #0
    2fe2:	f080 8081 	bcs.w	30e8 <compare_set+0x130>
		if (target_time != cc_data[chan].target_time) {
    2fe6:	4b43      	ldr	r3, [pc, #268]	; (30f4 <compare_set+0x13c>)
    2fe8:	eb03 1307 	add.w	r3, r3, r7, lsl #4
    2fec:	e9d3 2302 	ldrd	r2, r3, [r3, #8]
    2ff0:	429d      	cmp	r5, r3
    2ff2:	bf08      	it	eq
    2ff4:	4294      	cmpeq	r4, r2
    2ff6:	d053      	beq.n	30a0 <compare_set+0xe8>
    2ff8:	ea4f 0a87 	mov.w	sl, r7, lsl #2
    2ffc:	f10a 4a80 	add.w	sl, sl, #1073741824	; 0x40000000
	nrf_rtc_event_clear(RTC, RTC_CHANNEL_EVENT_ADDR(chan));
    3000:	f107 0950 	add.w	r9, r7, #80	; 0x50
    3004:	f50a 3a88 	add.w	sl, sl, #69632	; 0x11000
    3008:	ea4f 0989 	mov.w	r9, r9, lsl #2
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    300c:	fa1f f989 	uxth.w	r9, r9
	return absolute_time & COUNTER_MAX;
    3010:	f024 487f 	bic.w	r8, r4, #4278190080	; 0xff000000
    3014:	f109 4980 	add.w	r9, r9, #1073741824	; 0x40000000
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    3018:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    return p_reg->CC[ch];
    301c:	f8da 0540 	ldr.w	r0, [sl, #1344]	; 0x540
     return p_reg->COUNTER;
    3020:	4a35      	ldr	r2, [pc, #212]	; (30f8 <compare_set+0x140>)
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    3022:	f509 3988 	add.w	r9, r9, #69632	; 0x11000
    3026:	40bb      	lsls	r3, r7
	uint32_t cc_val = abs_val & COUNTER_MAX;
    3028:	4646      	mov	r6, r8
     return p_reg->COUNTER;
    302a:	f8d2 b504 	ldr.w	fp, [r2, #1284]	; 0x504
	return (a - b) & COUNTER_MAX;
    302e:	eba0 000b 	sub.w	r0, r0, fp
    3032:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
	nrf_rtc_cc_set(RTC, chan, cyc & COUNTER_MAX);
    3036:	f02b 417f 	bic.w	r1, fp, #4278190080	; 0xff000000
		if (counter_sub(prev_cc, now) == 1) {
    303a:	2801      	cmp	r0, #1
    p_reg->CC[ch] = cc_val;
    303c:	f8ca 1540 	str.w	r1, [sl, #1344]	; 0x540
    3040:	d105      	bne.n	304e <compare_set+0x96>
    3042:	9301      	str	r3, [sp, #4]
		(void) arch_syscall_invoke1(parm0.x, K_SYSCALL_K_BUSY_WAIT);
		return;
	}
#endif
	compiler_barrier();
	z_impl_k_busy_wait(usec_to_wait);
    3044:	2013      	movs	r0, #19
    3046:	f003 ff1e 	bl	6e86 <z_impl_k_busy_wait>
    304a:	4a2b      	ldr	r2, [pc, #172]	; (30f8 <compare_set+0x140>)
    304c:	9b01      	ldr	r3, [sp, #4]
		if (counter_sub(cc_val, now + 2) > COUNTER_HALF_SPAN) {
    304e:	f10b 0c02 	add.w	ip, fp, #2
	return (a - b) & COUNTER_MAX;
    3052:	eba6 000c 	sub.w	r0, r6, ip
    3056:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
			cc_val = now + 2;
    305a:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    305e:	bf88      	it	hi
    3060:	4666      	movhi	r6, ip
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    3062:	2000      	movs	r0, #0
    3064:	f8c9 0000 	str.w	r0, [r9]
    3068:	f8d9 0000 	ldr.w	r0, [r9]
    p_reg->EVTENSET = mask;
    306c:	f8c2 3344 	str.w	r3, [r2, #836]	; 0x344
	nrf_rtc_cc_set(RTC, chan, cyc & COUNTER_MAX);
    3070:	f026 407f 	bic.w	r0, r6, #4278190080	; 0xff000000
    p_reg->CC[ch] = cc_val;
    3074:	f8ca 0540 	str.w	r0, [sl, #1344]	; 0x540
     return p_reg->COUNTER;
    3078:	f8d2 0504 	ldr.w	r0, [r2, #1284]	; 0x504
	} while ((now2 != now) &&
    307c:	4583      	cmp	fp, r0
    307e:	d006      	beq.n	308e <compare_set+0xd6>
	return (a - b) & COUNTER_MAX;
    3080:	1a30      	subs	r0, r6, r0
    3082:	3802      	subs	r0, #2
    3084:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
	} while ((now2 != now) &&
    3088:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    308c:	d81b      	bhi.n	30c6 <compare_set+0x10e>
	return (a - b) & COUNTER_MAX;
    308e:	eba6 0608 	sub.w	r6, r6, r8
    3092:	f026 467f 	bic.w	r6, r6, #4278190080	; 0xff000000
			target_time += counter_sub(cc_set, cc_value);
    3096:	1936      	adds	r6, r6, r4
    3098:	f145 0300 	adc.w	r3, r5, #0
    309c:	4634      	mov	r4, r6
    309e:	461d      	mov	r5, r3
	cc_data[chan].target_time = target_time;
    30a0:	4914      	ldr	r1, [pc, #80]	; (30f4 <compare_set+0x13c>)
	cc_data[chan].callback = handler;
    30a2:	980c      	ldr	r0, [sp, #48]	; 0x30
	cc_data[chan].target_time = target_time;
    30a4:	013b      	lsls	r3, r7, #4
    30a6:	eb01 1207 	add.w	r2, r1, r7, lsl #4
	cc_data[chan].callback = handler;
    30aa:	50c8      	str	r0, [r1, r3]
	cc_data[chan].user_context = user_data;
    30ac:	9b0d      	ldr	r3, [sp, #52]	; 0x34
    30ae:	6053      	str	r3, [r2, #4]
	cc_data[chan].target_time = target_time;
    30b0:	e9c2 4502 	strd	r4, r5, [r2, #8]
	return ret;
    30b4:	2400      	movs	r4, #0
	compare_int_unlock(chan, key);
    30b6:	4638      	mov	r0, r7
    30b8:	9900      	ldr	r1, [sp, #0]
    30ba:	f7ff ff2d 	bl	2f18 <compare_int_unlock>
}
    30be:	4620      	mov	r0, r4
    30c0:	b003      	add	sp, #12
    30c2:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    30c6:	4630      	mov	r0, r6
    30c8:	e7af      	b.n	302a <compare_set+0x72>
		atomic_or(&force_isr_mask, BIT(chan));
    30ca:	2301      	movs	r3, #1
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    30cc:	4a0b      	ldr	r2, [pc, #44]	; (30fc <compare_set+0x144>)
    30ce:	f3bf 8f5b 	dmb	ish
    30d2:	40bb      	lsls	r3, r7
    30d4:	e852 0f00 	ldrex	r0, [r2]
    30d8:	4318      	orrs	r0, r3
    30da:	e842 0100 	strex	r1, r0, [r2]
    30de:	2900      	cmp	r1, #0
    30e0:	d1f8      	bne.n	30d4 <compare_set+0x11c>
    30e2:	f3bf 8f5b 	dmb	ish
    30e6:	e7db      	b.n	30a0 <compare_set+0xe8>
			return -EINVAL;
    30e8:	f06f 0415 	mvn.w	r4, #21
    30ec:	e7e3      	b.n	30b6 <compare_set+0xfe>
    30ee:	bf00      	nop
    30f0:	01000001 	.word	0x01000001
    30f4:	20000148 	.word	0x20000148
    30f8:	40011000 	.word	0x40011000
    30fc:	20000ee0 	.word	0x20000ee0

00003100 <sys_clock_driver_init>:
{
	return (uint32_t)z_nrf_rtc_timer_read();
}

static int sys_clock_driver_init(const struct device *dev)
{
    3100:	b573      	push	{r0, r1, r4, r5, r6, lr}
			CLOCK_CONTROL_NRF_LF_START_STABLE);

	/* TODO: replace with counter driver to access RTC */
	nrf_rtc_prescaler_set(RTC, 0);
	for (int32_t chan = 0; chan < CHAN_COUNT; chan++) {
		cc_data[chan].target_time = TARGET_TIME_INVALID;
    3102:	4b19      	ldr	r3, [pc, #100]	; (3168 <sys_clock_driver_init+0x68>)
    p_reg->PRESCALER = val;
    3104:	4d19      	ldr	r5, [pc, #100]	; (316c <sys_clock_driver_init+0x6c>)
    3106:	2400      	movs	r4, #0
    3108:	f04f 30ff 	mov.w	r0, #4294967295
    310c:	f04f 31ff 	mov.w	r1, #4294967295
    3110:	f8c5 4508 	str.w	r4, [r5, #1288]	; 0x508
    3114:	e9c3 0102 	strd	r0, r1, [r3, #8]
    p_reg->INTENSET = mask;
    3118:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    311c:	f8c5 3304 	str.w	r3, [r5, #772]	; 0x304
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    3120:	4b13      	ldr	r3, [pc, #76]	; (3170 <sys_clock_driver_init+0x70>)
    3122:	2602      	movs	r6, #2
    3124:	f44f 3200 	mov.w	r2, #131072	; 0x20000

	nrf_rtc_int_enable(RTC, NRF_RTC_INT_OVERFLOW_MASK);

	NVIC_ClearPendingIRQ(RTC_IRQn);

	IRQ_CONNECT(RTC_IRQn, DT_IRQ(DT_NODELABEL(RTC_LABEL), priority),
    3128:	2101      	movs	r1, #1
    312a:	f8c5 6304 	str.w	r6, [r5, #772]	; 0x304
    312e:	2011      	movs	r0, #17
    3130:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
    3134:	4622      	mov	r2, r4
    3136:	f7fe fd1f 	bl	1b78 <z_arm_irq_priority_set>
		    rtc_nrf_isr, 0, 0);
	irq_enable(RTC_IRQn);
    313a:	2011      	movs	r0, #17
    313c:	f7fe fd00 	bl	1b40 <arch_irq_enable>

	nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_CLEAR);
	nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_START);

	int_mask = BIT_MASK(CHAN_COUNT);
    3140:	4a0c      	ldr	r2, [pc, #48]	; (3174 <sys_clock_driver_init+0x74>)
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    3142:	2301      	movs	r3, #1
    3144:	60ab      	str	r3, [r5, #8]
    3146:	602b      	str	r3, [r5, #0]
    3148:	6013      	str	r3, [r2, #0]

	uint32_t initial_timeout = IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
		(COUNTER_HALF_SPAN - 1) :
		(counter() + CYC_PER_TICK);

	compare_set(0, initial_timeout, sys_clock_timeout_handler, NULL);
    314a:	4b0b      	ldr	r3, [pc, #44]	; (3178 <sys_clock_driver_init+0x78>)
    314c:	4a0b      	ldr	r2, [pc, #44]	; (317c <sys_clock_driver_init+0x7c>)
    314e:	9300      	str	r3, [sp, #0]
    3150:	9401      	str	r4, [sp, #4]
    3152:	2300      	movs	r3, #0
    3154:	4620      	mov	r0, r4
    3156:	f7ff ff2f 	bl	2fb8 <compare_set>

	z_nrf_clock_control_lf_on(mode);
    315a:	4630      	mov	r0, r6
    315c:	f7ff fa02 	bl	2564 <z_nrf_clock_control_lf_on>

	return 0;
}
    3160:	4620      	mov	r0, r4
    3162:	b002      	add	sp, #8
    3164:	bd70      	pop	{r4, r5, r6, pc}
    3166:	bf00      	nop
    3168:	20000148 	.word	0x20000148
    316c:	40011000 	.word	0x40011000
    3170:	e000e100 	.word	0xe000e100
    3174:	20000ee4 	.word	0x20000ee4
    3178:	00002e99 	.word	0x00002e99
    317c:	007fffff 	.word	0x007fffff

00003180 <rtc_nrf_isr>:
{
    3180:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    return p_reg->INTENSET & mask;
    3184:	4c33      	ldr	r4, [pc, #204]	; (3254 <rtc_nrf_isr+0xd4>)
    3186:	f8d4 3304 	ldr.w	r3, [r4, #772]	; 0x304
	if (nrf_rtc_int_enable_check(RTC, NRF_RTC_INT_OVERFLOW_MASK) &&
    318a:	079a      	lsls	r2, r3, #30
    318c:	d50b      	bpl.n	31a6 <rtc_nrf_isr+0x26>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    318e:	f8d4 3104 	ldr.w	r3, [r4, #260]	; 0x104
    3192:	b143      	cbz	r3, 31a6 <rtc_nrf_isr+0x26>
		overflow_cnt++;
    3194:	4a30      	ldr	r2, [pc, #192]	; (3258 <rtc_nrf_isr+0xd8>)
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    3196:	2300      	movs	r3, #0
    3198:	f8c4 3104 	str.w	r3, [r4, #260]	; 0x104
    319c:	f8d4 3104 	ldr.w	r3, [r4, #260]	; 0x104
    31a0:	6813      	ldr	r3, [r2, #0]
    31a2:	3301      	adds	r3, #1
    31a4:	6013      	str	r3, [r2, #0]
	__asm__ volatile(
    31a6:	f04f 0320 	mov.w	r3, #32
    31aa:	f3ef 8211 	mrs	r2, BASEPRI
    31ae:	f383 8812 	msr	BASEPRI_MAX, r3
    31b2:	f3bf 8f6f 	isb	sy
    return p_reg->INTENSET & mask;
    31b6:	f8d4 3304 	ldr.w	r3, [r4, #772]	; 0x304
	if (nrf_rtc_int_enable_check(RTC, RTC_CHANNEL_INT_MASK(chan))) {
    31ba:	03db      	lsls	r3, r3, #15
    31bc:	d529      	bpl.n	3212 <rtc_nrf_isr+0x92>
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    31be:	f3bf 8f5b 	dmb	ish
    31c2:	4b26      	ldr	r3, [pc, #152]	; (325c <rtc_nrf_isr+0xdc>)
    31c4:	e853 1f00 	ldrex	r1, [r3]
    31c8:	f021 0001 	bic.w	r0, r1, #1
    31cc:	e843 0500 	strex	r5, r0, [r3]
    31d0:	2d00      	cmp	r5, #0
    31d2:	d1f7      	bne.n	31c4 <rtc_nrf_isr+0x44>
    31d4:	f3bf 8f5b 	dmb	ish
		result = atomic_and(&force_isr_mask, ~BIT(chan)) ||
    31d8:	b911      	cbnz	r1, 31e0 <rtc_nrf_isr+0x60>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    31da:	f8d4 3140 	ldr.w	r3, [r4, #320]	; 0x140
    31de:	b1c3      	cbz	r3, 3212 <rtc_nrf_isr+0x92>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    31e0:	2500      	movs	r5, #0
    31e2:	f8c4 5140 	str.w	r5, [r4, #320]	; 0x140
    31e6:	f8d4 3140 	ldr.w	r3, [r4, #320]	; 0x140
	__asm__ volatile(
    31ea:	f382 8811 	msr	BASEPRI, r2
    31ee:	f3bf 8f6f 	isb	sy
		curr_time = z_nrf_rtc_timer_read();
    31f2:	f7ff febf 	bl	2f74 <z_nrf_rtc_timer_read>
	__asm__ volatile(
    31f6:	f04f 0320 	mov.w	r3, #32
    31fa:	f3ef 8211 	mrs	r2, BASEPRI
    31fe:	f383 8812 	msr	BASEPRI_MAX, r3
    3202:	f3bf 8f6f 	isb	sy
		expire_time = cc_data[chan].target_time;
    3206:	4b16      	ldr	r3, [pc, #88]	; (3260 <rtc_nrf_isr+0xe0>)
    3208:	e9d3 6702 	ldrd	r6, r7, [r3, #8]
		if (curr_time >= expire_time) {
    320c:	42b0      	cmp	r0, r6
    320e:	41b9      	sbcs	r1, r7
    3210:	d206      	bcs.n	3220 <rtc_nrf_isr+0xa0>
	__asm__ volatile(
    3212:	f382 8811 	msr	BASEPRI, r2
    3216:	f3bf 8f6f 	isb	sy
}
    321a:	b003      	add	sp, #12
    321c:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
			cc_data[chan].target_time = TARGET_TIME_INVALID;
    3220:	f04f 38ff 	mov.w	r8, #4294967295
    3224:	f04f 39ff 	mov.w	r9, #4294967295
			user_context = cc_data[chan].user_context;
    3228:	e9d3 1000 	ldrd	r1, r0, [r3]
			cc_data[chan].target_time = TARGET_TIME_INVALID;
    322c:	e9c3 8902 	strd	r8, r9, [r3, #8]
			cc_data[chan].callback = NULL;
    3230:	601d      	str	r5, [r3, #0]
    p_reg->EVTENCLR = mask;
    3232:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    3236:	f8c4 3348 	str.w	r3, [r4, #840]	; 0x348
    323a:	f382 8811 	msr	BASEPRI, r2
    323e:	f3bf 8f6f 	isb	sy
		if (handler) {
    3242:	2900      	cmp	r1, #0
    3244:	d0e9      	beq.n	321a <rtc_nrf_isr+0x9a>
			handler(chan, expire_time, user_context);
    3246:	9000      	str	r0, [sp, #0]
    3248:	4632      	mov	r2, r6
    324a:	463b      	mov	r3, r7
    324c:	4628      	mov	r0, r5
    324e:	4788      	blx	r1
}
    3250:	e7e3      	b.n	321a <rtc_nrf_isr+0x9a>
    3252:	bf00      	nop
    3254:	40011000 	.word	0x40011000
    3258:	20000ee8 	.word	0x20000ee8
    325c:	20000ee0 	.word	0x20000ee0
    3260:	20000148 	.word	0x20000148

00003264 <sys_clock_set_timeout>:
	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    3264:	1c43      	adds	r3, r0, #1
{
    3266:	b513      	push	{r0, r1, r4, lr}
	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    3268:	d021      	beq.n	32ae <sys_clock_set_timeout+0x4a>
	ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
    326a:	2801      	cmp	r0, #1
    326c:	dd21      	ble.n	32b2 <sys_clock_set_timeout+0x4e>
    326e:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    3272:	da20      	bge.n	32b6 <sys_clock_set_timeout+0x52>
    3274:	1e44      	subs	r4, r0, #1
	uint32_t unannounced = z_nrf_rtc_timer_read() - last_count;
    3276:	f7ff fe7d 	bl	2f74 <z_nrf_rtc_timer_read>
    327a:	4b10      	ldr	r3, [pc, #64]	; (32bc <sys_clock_set_timeout+0x58>)
    327c:	e9d3 1300 	ldrd	r1, r3, [r3]
    3280:	1a42      	subs	r2, r0, r1
		ticks = 0;
    3282:	f5b2 0f00 	cmp.w	r2, #8388608	; 0x800000
	if (cyc > MAX_CYCLES) {
    3286:	480e      	ldr	r0, [pc, #56]	; (32c0 <sys_clock_set_timeout+0x5c>)
		ticks = 0;
    3288:	bf28      	it	cs
    328a:	2400      	movcs	r4, #0
	cyc = ticks * CYC_PER_TICK + 1 + unannounced;
    328c:	3201      	adds	r2, #1
    328e:	4422      	add	r2, r4
	if (cyc > MAX_CYCLES) {
    3290:	4282      	cmp	r2, r0
    3292:	bf28      	it	cs
    3294:	4602      	movcs	r2, r0
	uint64_t target_time = cyc + last_count;
    3296:	1852      	adds	r2, r2, r1
    3298:	f04f 0000 	mov.w	r0, #0
	compare_set(0, target_time, sys_clock_timeout_handler, NULL);
    329c:	4909      	ldr	r1, [pc, #36]	; (32c4 <sys_clock_set_timeout+0x60>)
    329e:	9001      	str	r0, [sp, #4]
    32a0:	9100      	str	r1, [sp, #0]
    32a2:	f143 0300 	adc.w	r3, r3, #0
    32a6:	f7ff fe87 	bl	2fb8 <compare_set>
}
    32aa:	b002      	add	sp, #8
    32ac:	bd10      	pop	{r4, pc}
	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    32ae:	4804      	ldr	r0, [pc, #16]	; (32c0 <sys_clock_set_timeout+0x5c>)
    32b0:	e7e0      	b.n	3274 <sys_clock_set_timeout+0x10>
	ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
    32b2:	2400      	movs	r4, #0
    32b4:	e7df      	b.n	3276 <sys_clock_set_timeout+0x12>
    32b6:	4c02      	ldr	r4, [pc, #8]	; (32c0 <sys_clock_set_timeout+0x5c>)
    32b8:	e7dd      	b.n	3276 <sys_clock_set_timeout+0x12>
    32ba:	bf00      	nop
    32bc:	20000158 	.word	0x20000158
    32c0:	007fffff 	.word	0x007fffff
    32c4:	00002e99 	.word	0x00002e99

000032c8 <sys_clock_elapsed>:
{
    32c8:	b508      	push	{r3, lr}
	return (z_nrf_rtc_timer_read() - last_count) / CYC_PER_TICK;
    32ca:	f7ff fe53 	bl	2f74 <z_nrf_rtc_timer_read>
    32ce:	4b02      	ldr	r3, [pc, #8]	; (32d8 <sys_clock_elapsed+0x10>)
    32d0:	681b      	ldr	r3, [r3, #0]
}
    32d2:	1ac0      	subs	r0, r0, r3
    32d4:	bd08      	pop	{r3, pc}
    32d6:	bf00      	nop
    32d8:	20000158 	.word	0x20000158

000032dc <pinctrl_configure_pins>:
#define NRF_PSEL_QSPI(reg, line) ((NRF_QSPI_Type *)reg)->PSEL.line
#endif

int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
			   uintptr_t reg)
{
    32dc:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
        case 1: return NRF_P1;
    32e0:	4e5a      	ldr	r6, [pc, #360]	; (344c <pinctrl_configure_pins+0x170>)
    32e2:	eb00 0181 	add.w	r1, r0, r1, lsl #2
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    32e6:	2701      	movs	r7, #1
	for (uint8_t i = 0U; i < pin_cnt; i++) {
    32e8:	4281      	cmp	r1, r0
    32ea:	d102      	bne.n	32f2 <pinctrl_configure_pins+0x16>
			nrf_gpio_cfg(pin, dir, input, NRF_GET_PULL(pins[i]),
				     drive, NRF_GPIO_PIN_NOSENSE);
		}
	}

	return 0;
    32ec:	2000      	movs	r0, #0
}
    32ee:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		nrf_gpio_pin_drive_t drive = NRF_GET_DRIVE(pins[i]);
    32f2:	6804      	ldr	r4, [r0, #0]
		uint32_t pin = NRF_GET_PIN(pins[i]);
    32f4:	f004 037f 	and.w	r3, r4, #127	; 0x7f
		nrf_gpio_pin_drive_t drive = NRF_GET_DRIVE(pins[i]);
    32f8:	f3c4 2543 	ubfx	r5, r4, #9, #4
			pin = 0xFFFFFFFFU;
    32fc:	2b7f      	cmp	r3, #127	; 0x7f
		switch (NRF_GET_FUN(pins[i])) {
    32fe:	ea4f 4414 	mov.w	r4, r4, lsr #16
			pin = 0xFFFFFFFFU;
    3302:	bf08      	it	eq
    3304:	f04f 33ff 	moveq.w	r3, #4294967295
		switch (NRF_GET_FUN(pins[i])) {
    3308:	2c22      	cmp	r4, #34	; 0x22
    330a:	f200 809b 	bhi.w	3444 <pinctrl_configure_pins+0x168>
    330e:	e8df f004 	tbb	[pc, r4]
    3312:	2412      	.short	0x2412
    3314:	402c4429 	.word	0x402c4429
    3318:	99999944 	.word	0x99999944
    331c:	99704799 	.word	0x99704799
    3320:	99999999 	.word	0x99999999
    3324:	99999999 	.word	0x99999999
    3328:	817e7b73 	.word	0x817e7b73
    332c:	84999999 	.word	0x84999999
    3330:	93908d8a 	.word	0x93908d8a
    3334:	96          	.byte	0x96
    3335:	00          	.byte	0x00
			NRF_PSEL_UART(reg, TXD) = pin;
    3336:	f8c2 350c 	str.w	r3, [r2, #1292]	; 0x50c
    return pin_number >> 5;
    333a:	ea4f 1c53 	mov.w	ip, r3, lsr #5
        case 1: return NRF_P1;
    333e:	f1bc 0f01 	cmp.w	ip, #1
    *p_pin = pin_number & 0x1F;
    3342:	f003 041f 	and.w	r4, r3, #31
        case 1: return NRF_P1;
    3346:	bf14      	ite	ne
    3348:	f04f 4ca0 	movne.w	ip, #1342177280	; 0x50000000
    334c:	46b4      	moveq	ip, r6
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    334e:	fa07 f404 	lsl.w	r4, r7, r4
    p_reg->OUTSET = set_mask;
    3352:	f8cc 4508 	str.w	r4, [ip, #1288]	; 0x508
    3356:	2401      	movs	r4, #1
    3358:	e002      	b.n	3360 <pinctrl_configure_pins+0x84>
			NRF_PSEL_UART(reg, RXD) = pin;
    335a:	f8c2 3514 	str.w	r3, [r2, #1300]	; 0x514
			input = NRF_GPIO_PIN_INPUT_CONNECT;
    335e:	2400      	movs	r4, #0
    3360:	46a6      	mov	lr, r4
    3362:	e024      	b.n	33ae <pinctrl_configure_pins+0xd2>
			NRF_PSEL_UART(reg, RTS) = pin;
    3364:	f8c2 3508 	str.w	r3, [r2, #1288]	; 0x508
			if (write != NO_WRITE) {
    3368:	e7e7      	b.n	333a <pinctrl_configure_pins+0x5e>
			NRF_PSEL_SPIM(reg, SCK) = pin;
    336a:	f8c2 3508 	str.w	r3, [r2, #1288]	; 0x508
			input = NRF_GPIO_PIN_INPUT_CONNECT;
    336e:	2400      	movs	r4, #0
    return pin_number >> 5;
    3370:	ea4f 1e53 	mov.w	lr, r3, lsr #5
        case 1: return NRF_P1;
    3374:	f1be 0f01 	cmp.w	lr, #1
    3378:	bf14      	ite	ne
    337a:	f04f 4ea0 	movne.w	lr, #1342177280	; 0x50000000
    337e:	46b6      	moveq	lr, r6
    *p_pin = pin_number & 0x1F;
    3380:	f003 0c1f 	and.w	ip, r3, #31
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    3384:	fa07 fc0c 	lsl.w	ip, r7, ip
    p_reg->OUTCLR = clr_mask;
    3388:	f8ce c50c 	str.w	ip, [lr, #1292]	; 0x50c
    338c:	f04f 0e01 	mov.w	lr, #1
    3390:	e00d      	b.n	33ae <pinctrl_configure_pins+0xd2>
			NRF_PSEL_SPIM(reg, MOSI) = pin;
    3392:	f8c2 350c 	str.w	r3, [r2, #1292]	; 0x50c
			pin = 0xFFFFFFFFU;
    3396:	2401      	movs	r4, #1
    3398:	e7ea      	b.n	3370 <pinctrl_configure_pins+0x94>
			NRF_PSEL_SPIM(reg, MISO) = pin;
    339a:	f8c2 3510 	str.w	r3, [r2, #1296]	; 0x510
			if (write != NO_WRITE) {
    339e:	e7de      	b.n	335e <pinctrl_configure_pins+0x82>
			NRF_PSEL_TWIM(reg, SCL) = pin;
    33a0:	f8c2 3508 	str.w	r3, [r2, #1288]	; 0x508
			if (drive == NRF_DRIVE_S0S1) {
    33a4:	2d00      	cmp	r5, #0
    33a6:	d1da      	bne.n	335e <pinctrl_configure_pins+0x82>
			input = NRF_GPIO_PIN_INPUT_CONNECT;
    33a8:	2400      	movs	r4, #0
			dir = NRF_GPIO_PIN_DIR_INPUT;
    33aa:	46a6      	mov	lr, r4
				drive = NRF_DRIVE_S0D1;
    33ac:	2506      	movs	r5, #6
			if (NRF_GET_LP(pins[i]) == NRF_LP_ENABLE) {
    33ae:	f850 cb04 	ldr.w	ip, [r0], #4
    33b2:	f40c 5800 	and.w	r8, ip, #8192	; 0x2000
				input = NRF_GPIO_PIN_INPUT_DISCONNECT;
    33b6:	f1b8 0f00 	cmp.w	r8, #0
           ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) |
    33ba:	ea4f 2505 	mov.w	r5, r5, lsl #8
			nrf_gpio_cfg(pin, dir, input, NRF_GET_PULL(pins[i]),
    33be:	f3cc 18c1 	ubfx	r8, ip, #7, #2
    *p_pin = pin_number & 0x1F;
    33c2:	f003 0c1f 	and.w	ip, r3, #31
    return pin_number >> 5;
    33c6:	ea4f 1353 	mov.w	r3, r3, lsr #5
				input = NRF_GPIO_PIN_INPUT_DISCONNECT;
    33ca:	bf1c      	itt	ne
    33cc:	2401      	movne	r4, #1
    33ce:	f04f 0e00 	movne.w	lr, #0
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    33d2:	ea45 0588 	orr.w	r5, r5, r8, lsl #2
        case 0: return NRF_P0;
    33d6:	2b01      	cmp	r3, #1
    33d8:	bf0c      	ite	eq
    33da:	4633      	moveq	r3, r6
    33dc:	f04f 43a0 	movne.w	r3, #1342177280	; 0x50000000
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    33e0:	ea45 050e 	orr.w	r5, r5, lr
    reg->PIN_CNF[pin_number] = cnf;
    33e4:	f50c 7ce0 	add.w	ip, ip, #448	; 0x1c0
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    33e8:	ea45 0544 	orr.w	r5, r5, r4, lsl #1
    reg->PIN_CNF[pin_number] = cnf;
    33ec:	f843 502c 	str.w	r5, [r3, ip, lsl #2]
	for (uint8_t i = 0U; i < pin_cnt; i++) {
    33f0:	e77a      	b.n	32e8 <pinctrl_configure_pins+0xc>
			NRF_PSEL_TWIM(reg, SDA) = pin;
    33f2:	f8c2 350c 	str.w	r3, [r2, #1292]	; 0x50c
			if (drive == NRF_DRIVE_S0S1) {
    33f6:	e7d5      	b.n	33a4 <pinctrl_configure_pins+0xc8>
			NRF_PSEL_PWM(reg, OUT[0]) = pin;
    33f8:	f8c2 3560 	str.w	r3, [r2, #1376]	; 0x560
			write = NRF_GET_INVERT(pins[i]);
    33fc:	6804      	ldr	r4, [r0, #0]
    33fe:	f3c4 3480 	ubfx	r4, r4, #14, #1
    if (value == 0)
    3402:	2c00      	cmp	r4, #0
    3404:	d0c7      	beq.n	3396 <pinctrl_configure_pins+0xba>
    3406:	e798      	b.n	333a <pinctrl_configure_pins+0x5e>
			NRF_PSEL_PWM(reg, OUT[1]) = pin;
    3408:	f8c2 3564 	str.w	r3, [r2, #1380]	; 0x564
			write = NRF_GET_INVERT(pins[i]);
    340c:	e7f6      	b.n	33fc <pinctrl_configure_pins+0x120>
			NRF_PSEL_PWM(reg, OUT[2]) = pin;
    340e:	f8c2 3568 	str.w	r3, [r2, #1384]	; 0x568
			write = NRF_GET_INVERT(pins[i]);
    3412:	e7f3      	b.n	33fc <pinctrl_configure_pins+0x120>
			NRF_PSEL_PWM(reg, OUT[3]) = pin;
    3414:	f8c2 356c 	str.w	r3, [r2, #1388]	; 0x56c
    3418:	e7f0      	b.n	33fc <pinctrl_configure_pins+0x120>
			NRF_PSEL_QSPI(reg, SCK) = pin;
    341a:	f8c2 3524 	str.w	r3, [r2, #1316]	; 0x524
			input = NRF_GPIO_PIN_INPUT_DISCONNECT;
    341e:	2401      	movs	r4, #1
			dir = NRF_GPIO_PIN_DIR_INPUT;
    3420:	f04f 0e00 	mov.w	lr, #0
    3424:	e7c3      	b.n	33ae <pinctrl_configure_pins+0xd2>
			NRF_PSEL_QSPI(reg, CSN) = pin;
    3426:	f8c2 3528 	str.w	r3, [r2, #1320]	; 0x528
    342a:	e786      	b.n	333a <pinctrl_configure_pins+0x5e>
			NRF_PSEL_QSPI(reg, IO0) = pin;
    342c:	f8c2 3530 	str.w	r3, [r2, #1328]	; 0x530
			if (write != NO_WRITE) {
    3430:	e7f5      	b.n	341e <pinctrl_configure_pins+0x142>
			NRF_PSEL_QSPI(reg, IO1) = pin;
    3432:	f8c2 3534 	str.w	r3, [r2, #1332]	; 0x534
    3436:	e7f2      	b.n	341e <pinctrl_configure_pins+0x142>
			NRF_PSEL_QSPI(reg, IO2) = pin;
    3438:	f8c2 3538 	str.w	r3, [r2, #1336]	; 0x538
			if (write != NO_WRITE) {
    343c:	e7ef      	b.n	341e <pinctrl_configure_pins+0x142>
			NRF_PSEL_QSPI(reg, IO3) = pin;
    343e:	f8c2 353c 	str.w	r3, [r2, #1340]	; 0x53c
			if (write != NO_WRITE) {
    3442:	e7ec      	b.n	341e <pinctrl_configure_pins+0x142>
		switch (NRF_GET_FUN(pins[i])) {
    3444:	f06f 0085 	mvn.w	r0, #133	; 0x85
    3448:	e751      	b.n	32ee <pinctrl_configure_pins+0x12>
    344a:	bf00      	nop
    344c:	50000300 	.word	0x50000300

00003450 <find_free_region>:
#include <zephyr/sys/__assert.h>
#include <zephyr/kernel.h>

/* Find the first unused ACL region. */
static int find_free_region(uint32_t *region_idx)
{
    3450:	b530      	push	{r4, r5, lr}
    3452:	490c      	ldr	r1, [pc, #48]	; (3484 <find_free_region+0x34>)
}

NRF_STATIC_INLINE nrf_acl_perm_t nrf_acl_region_perm_get(NRF_ACL_Type const * p_reg,
                                                         uint32_t             region_id)
{
    return (nrf_acl_perm_t)p_reg->ACL[region_id].PERM;
    3454:	4d0c      	ldr	r5, [pc, #48]	; (3488 <find_free_region+0x38>)
    3456:	680b      	ldr	r3, [r1, #0]
    3458:	4602      	mov	r2, r0
	static uint32_t idx;

	while (nrf_acl_region_perm_get(NRF_ACL, idx) != 0) {
    345a:	2400      	movs	r4, #0
    345c:	eb05 1003 	add.w	r0, r5, r3, lsl #4
    3460:	f8d0 0808 	ldr.w	r0, [r0, #2056]	; 0x808
    3464:	b2c0      	uxtb	r0, r0
    3466:	b918      	cbnz	r0, 3470 <find_free_region+0x20>
    3468:	b104      	cbz	r4, 346c <find_free_region+0x1c>
    346a:	600b      	str	r3, [r1, #0]
			*region_idx = idx;
			return -ENOSPC;
		}
	}
	*region_idx = idx;
	return 0;
    346c:	2000      	movs	r0, #0
    346e:	e007      	b.n	3480 <find_free_region+0x30>
		idx++;
    3470:	3301      	adds	r3, #1
		if (idx >= ACL_REGIONS_COUNT) {
    3472:	2b07      	cmp	r3, #7
    3474:	f04f 0401 	mov.w	r4, #1
    3478:	d9f0      	bls.n	345c <find_free_region+0xc>
    347a:	600b      	str	r3, [r1, #0]
			return -ENOSPC;
    347c:	f06f 001b 	mvn.w	r0, #27
			*region_idx = idx;
    3480:	6013      	str	r3, [r2, #0]
}
    3482:	bd30      	pop	{r4, r5, pc}
    3484:	20000eec 	.word	0x20000eec
    3488:	4001e000 	.word	0x4001e000

0000348c <k_sys_fatal_error_handler>:
	defined(CONFIG_SPM_SERVICE_NS_HANDLER_FROM_SPM_FAULT)
	z_spm_ns_fatal_error_handler();
#endif

	if (IS_ENABLED(CONFIG_RESET_ON_FATAL_ERROR)) {
		LOG_ERR("Resetting system");
    348c:	4803      	ldr	r0, [pc, #12]	; (349c <k_sys_fatal_error_handler+0x10>)
{
    348e:	b508      	push	{r3, lr}
		LOG_ERR("Resetting system");
    3490:	2145      	movs	r1, #69	; 0x45
    3492:	f003 f86c 	bl	656e <z_log_minimal_printk>
		sys_arch_reboot(0);
    3496:	2000      	movs	r0, #0
    3498:	f7fe ff6e 	bl	2378 <sys_arch_reboot>
		for (;;) {
			/* Spin endlessly */
		}
	}

	CODE_UNREACHABLE;
    349c:	00008068 	.word	0x00008068

000034a0 <boot_write_magic>:
    return rc;
}

int
boot_write_magic(const struct flash_area *fap)
{
    34a0:	b530      	push	{r4, r5, lr}
    return flash_area_get_size(fap) - BOOT_MAGIC_SZ;
    34a2:	6881      	ldr	r1, [r0, #8]
{
    34a4:	b085      	sub	sp, #20
    return flash_area_get_size(fap) - BOOT_MAGIC_SZ;
    34a6:	3910      	subs	r1, #16
     * returned by boot_magic_off() is the start of magic which is not the
     * start of the flash write boundary and thus writes to the magic will fail.
     * To account for this change, write to magic is first padded with 0xFF
     * before writing to the trailer.
     */
    pad_off = ALIGN_DOWN(off, BOOT_MAX_ALIGN);
    34a8:	f021 0407 	bic.w	r4, r1, #7
{
    34ac:	4605      	mov	r5, r0

    erased_val = flash_area_erased_val(fap);
    34ae:	f003 f8b3 	bl	6618 <flash_area_erased_val>

    memset(&magic[0], erased_val, sizeof(magic));
    34b2:	2210      	movs	r2, #16
    erased_val = flash_area_erased_val(fap);
    34b4:	4601      	mov	r1, r0
    memset(&magic[0], erased_val, sizeof(magic));
    34b6:	4668      	mov	r0, sp
    34b8:	f003 f917 	bl	66ea <memset>
    memcpy(&magic[BOOT_MAGIC_ALIGN_SIZE - BOOT_MAGIC_SZ], BOOT_IMG_MAGIC, BOOT_MAGIC_SZ);
    34bc:	4907      	ldr	r1, [pc, #28]	; (34dc <boot_write_magic+0x3c>)
    34be:	2210      	movs	r2, #16
    34c0:	4668      	mov	r0, sp
    34c2:	f003 f907 	bl	66d4 <memcpy>

    BOOT_LOG_DBG("writing magic; fa_id=%d off=0x%lx (0x%lx)",
                 flash_area_get_id(fap), (unsigned long)off,
                 (unsigned long)(flash_area_get_off(fap) + off));
    rc = flash_area_write(fap, pad_off, &magic[0], BOOT_MAGIC_ALIGN_SIZE);
    34c6:	2310      	movs	r3, #16
    34c8:	466a      	mov	r2, sp
    34ca:	4621      	mov	r1, r4
    34cc:	4628      	mov	r0, r5
    34ce:	f003 f871 	bl	65b4 <flash_area_write>
    if (rc != 0) {
        return BOOT_EFLASH;
    }

    return 0;
}
    34d2:	3800      	subs	r0, #0
    34d4:	bf18      	it	ne
    34d6:	2001      	movne	r0, #1
    34d8:	b005      	add	sp, #20
    34da:	bd30      	pop	{r4, r5, pc}
    34dc:	00007560 	.word	0x00007560

000034e0 <boot_read_swap_state>:
{
    34e0:	b530      	push	{r4, r5, lr}
    34e2:	460d      	mov	r5, r1
    return flash_area_get_size(fap) - BOOT_MAGIC_SZ;
    34e4:	6881      	ldr	r1, [r0, #8]
{
    34e6:	b087      	sub	sp, #28
    rc = flash_area_read(fap, off, magic, BOOT_MAGIC_SZ);
    34e8:	2310      	movs	r3, #16
    34ea:	aa02      	add	r2, sp, #8
    34ec:	3910      	subs	r1, #16
{
    34ee:	4604      	mov	r4, r0
    rc = flash_area_read(fap, off, magic, BOOT_MAGIC_SZ);
    34f0:	f003 f84b 	bl	658a <flash_area_read>
    if (rc < 0) {
    34f4:	2800      	cmp	r0, #0
    34f6:	da02      	bge.n	34fe <boot_read_swap_state+0x1e>
        return BOOT_EFLASH;
    34f8:	2001      	movs	r0, #1
}
    34fa:	b007      	add	sp, #28
    34fc:	bd30      	pop	{r4, r5, pc}
    if (bootutil_buffer_is_erased(fap, magic, BOOT_MAGIC_SZ)) {
    34fe:	2210      	movs	r2, #16
    3500:	a902      	add	r1, sp, #8
    3502:	4620      	mov	r0, r4
    3504:	f003 fb57 	bl	6bb6 <bootutil_buffer_is_erased>
    3508:	2800      	cmp	r0, #0
    350a:	d13a      	bne.n	3582 <boot_read_swap_state+0xa2>
    if (memcmp(magic, BOOT_IMG_MAGIC, BOOT_MAGIC_SZ) == 0) {
    350c:	491e      	ldr	r1, [pc, #120]	; (3588 <boot_read_swap_state+0xa8>)
    350e:	2210      	movs	r2, #16
    3510:	a802      	add	r0, sp, #8
    3512:	f003 f8cf 	bl	66b4 <memcmp>
    return BOOT_MAGIC_BAD;
    3516:	2800      	cmp	r0, #0
        state->magic = boot_magic_decode(magic);
    3518:	bf0c      	ite	eq
    351a:	2301      	moveq	r3, #1
    351c:	2302      	movne	r3, #2
        state->magic = BOOT_MAGIC_UNSET;
    351e:	702b      	strb	r3, [r5, #0]
    off = boot_swap_info_off(fap);
    3520:	4620      	mov	r0, r4
    3522:	f003 fb34 	bl	6b8e <boot_swap_info_off>
    rc = flash_area_read(fap, off, &swap_info, sizeof swap_info);
    3526:	2301      	movs	r3, #1
    off = boot_swap_info_off(fap);
    3528:	4601      	mov	r1, r0
    rc = flash_area_read(fap, off, &swap_info, sizeof swap_info);
    352a:	f10d 0207 	add.w	r2, sp, #7
    352e:	4620      	mov	r0, r4
    3530:	f003 f82b 	bl	658a <flash_area_read>
    if (rc < 0) {
    3534:	2800      	cmp	r0, #0
    3536:	dbdf      	blt.n	34f8 <boot_read_swap_state+0x18>
    state->swap_type = BOOT_GET_SWAP_TYPE(swap_info);
    3538:	f89d 3007 	ldrb.w	r3, [sp, #7]
    353c:	f003 020f 	and.w	r2, r3, #15
    state->image_num = BOOT_GET_IMAGE_NUM(swap_info);
    3540:	091b      	lsrs	r3, r3, #4
    state->swap_type = BOOT_GET_SWAP_TYPE(swap_info);
    3542:	706a      	strb	r2, [r5, #1]
    state->image_num = BOOT_GET_IMAGE_NUM(swap_info);
    3544:	712b      	strb	r3, [r5, #4]
    if (bootutil_buffer_is_erased(fap, &swap_info, sizeof swap_info) ||
    3546:	2201      	movs	r2, #1
    3548:	f10d 0107 	add.w	r1, sp, #7
    354c:	4620      	mov	r0, r4
    354e:	f003 fb32 	bl	6bb6 <bootutil_buffer_is_erased>
    3552:	b910      	cbnz	r0, 355a <boot_read_swap_state+0x7a>
    3554:	786b      	ldrb	r3, [r5, #1]
    3556:	2b04      	cmp	r3, #4
    3558:	d903      	bls.n	3562 <boot_read_swap_state+0x82>
        state->swap_type = BOOT_SWAP_TYPE_NONE;
    355a:	2301      	movs	r3, #1
    355c:	706b      	strb	r3, [r5, #1]
        state->image_num = 0;
    355e:	2300      	movs	r3, #0
    3560:	712b      	strb	r3, [r5, #4]
    return ALIGN_DOWN(boot_magic_off(fap) - BOOT_MAX_ALIGN, BOOT_MAX_ALIGN);
    3562:	68a2      	ldr	r2, [r4, #8]
    3564:	3a18      	subs	r2, #24
    3566:	f022 0207 	bic.w	r2, r2, #7
    return boot_read_flag(fap, copy_done, boot_copy_done_off(fap));
    356a:	3a08      	subs	r2, #8
    356c:	1ca9      	adds	r1, r5, #2
    356e:	4620      	mov	r0, r4
    3570:	f003 fb34 	bl	6bdc <boot_read_flag>
    if (rc) {
    3574:	2800      	cmp	r0, #0
    3576:	d1bf      	bne.n	34f8 <boot_read_swap_state+0x18>
    return boot_read_image_ok(fap, &state->image_ok);
    3578:	1ce9      	adds	r1, r5, #3
    357a:	4620      	mov	r0, r4
    357c:	f003 fb87 	bl	6c8e <boot_read_image_ok>
    3580:	e7bb      	b.n	34fa <boot_read_swap_state+0x1a>
    3582:	2303      	movs	r3, #3
    3584:	e7cb      	b.n	351e <boot_read_swap_state+0x3e>
    3586:	bf00      	nop
    3588:	00007560 	.word	0x00007560

0000358c <boot_swap_type_multi>:
    return boot_write_trailer(fap, off, (const uint8_t *) &swap_info, 1);
}

int
boot_swap_type_multi(int image_index)
{
    358c:	b57f      	push	{r0, r1, r2, r3, r4, r5, r6, lr}
    358e:	4605      	mov	r5, r0

    rc = BOOT_HOOK_CALL(boot_read_swap_state_primary_slot_hook,
                        BOOT_HOOK_REGULAR, image_index, &primary_slot);
    if (rc == BOOT_HOOK_REGULAR)
    {
        rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_PRIMARY(image_index),
    3590:	4669      	mov	r1, sp
    3592:	2002      	movs	r0, #2
    3594:	f003 fb81 	bl	6c9a <boot_read_swap_state_by_id>
                                        &primary_slot);
    }
    if (rc) {
    3598:	4604      	mov	r4, r0
    359a:	b110      	cbz	r0, 35a2 <boot_swap_type_multi+0x16>
        return BOOT_SWAP_TYPE_PANIC;
    359c:	20ff      	movs	r0, #255	; 0xff
        }
    }

    BOOT_LOG_INF("Swap type: none");
    return BOOT_SWAP_TYPE_NONE;
}
    359e:	b004      	add	sp, #16
    35a0:	bd70      	pop	{r4, r5, r6, pc}
    rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_SECONDARY(image_index),
    35a2:	a902      	add	r1, sp, #8
    35a4:	2005      	movs	r0, #5
    35a6:	f003 fb78 	bl	6c9a <boot_read_swap_state_by_id>
    if (rc == BOOT_EFLASH) {
    35aa:	2801      	cmp	r0, #1
    35ac:	d136      	bne.n	361c <boot_swap_type_multi+0x90>
        BOOT_LOG_INF("Secondary image of image pair (%d.) "
    35ae:	4829      	ldr	r0, [pc, #164]	; (3654 <boot_swap_type_multi+0xc8>)
    35b0:	462a      	mov	r2, r5
    35b2:	2149      	movs	r1, #73	; 0x49
    35b4:	f002 ffdb 	bl	656e <z_log_minimal_printk>
        secondary_slot.magic = BOOT_MAGIC_UNSET;
    35b8:	4b27      	ldr	r3, [pc, #156]	; (3658 <boot_swap_type_multi+0xcc>)
    35ba:	9302      	str	r3, [sp, #8]
        secondary_slot.image_num = 0;
    35bc:	f88d 400c 	strb.w	r4, [sp, #12]
        if (boot_magic_compatible_check(table->magic_primary_slot,
    35c0:	f89d 5000 	ldrb.w	r5, [sp]
            boot_magic_compatible_check(table->magic_secondary_slot,
    35c4:	f89d 6008 	ldrb.w	r6, [sp, #8]
    35c8:	4c24      	ldr	r4, [pc, #144]	; (365c <boot_swap_type_multi+0xd0>)
    35ca:	2200      	movs	r2, #0
        if (boot_magic_compatible_check(table->magic_primary_slot,
    35cc:	7820      	ldrb	r0, [r4, #0]
    35ce:	4629      	mov	r1, r5
    35d0:	f003 fae3 	bl	6b9a <boot_magic_compatible_check>
    35d4:	b348      	cbz	r0, 362a <boot_swap_type_multi+0x9e>
            boot_magic_compatible_check(table->magic_secondary_slot,
    35d6:	7860      	ldrb	r0, [r4, #1]
    35d8:	4631      	mov	r1, r6
    35da:	f003 fade 	bl	6b9a <boot_magic_compatible_check>
                                        primary_slot.magic) &&
    35de:	b320      	cbz	r0, 362a <boot_swap_type_multi+0x9e>
            (table->image_ok_primary_slot == BOOT_FLAG_ANY   ||
    35e0:	78a3      	ldrb	r3, [r4, #2]
                                        secondary_slot.magic) &&
    35e2:	2b04      	cmp	r3, #4
    35e4:	d003      	beq.n	35ee <boot_swap_type_multi+0x62>
            (table->image_ok_primary_slot == BOOT_FLAG_ANY   ||
    35e6:	f89d 1003 	ldrb.w	r1, [sp, #3]
    35ea:	4299      	cmp	r1, r3
    35ec:	d11d      	bne.n	362a <boot_swap_type_multi+0x9e>
            (table->image_ok_secondary_slot == BOOT_FLAG_ANY ||
    35ee:	78e3      	ldrb	r3, [r4, #3]
                table->image_ok_primary_slot == primary_slot.image_ok) &&
    35f0:	2b04      	cmp	r3, #4
    35f2:	d003      	beq.n	35fc <boot_swap_type_multi+0x70>
            (table->image_ok_secondary_slot == BOOT_FLAG_ANY ||
    35f4:	f89d 100b 	ldrb.w	r1, [sp, #11]
    35f8:	4299      	cmp	r1, r3
    35fa:	d116      	bne.n	362a <boot_swap_type_multi+0x9e>
            (table->copy_done_primary_slot == BOOT_FLAG_ANY  ||
    35fc:	7923      	ldrb	r3, [r4, #4]
                table->image_ok_secondary_slot == secondary_slot.image_ok) &&
    35fe:	2b04      	cmp	r3, #4
    3600:	d10f      	bne.n	3622 <boot_swap_type_multi+0x96>
            BOOT_LOG_INF("Swap type: %s",
    3602:	7963      	ldrb	r3, [r4, #5]
    3604:	2b02      	cmp	r3, #2
    3606:	d11b      	bne.n	3640 <boot_swap_type_multi+0xb4>
    3608:	4a15      	ldr	r2, [pc, #84]	; (3660 <boot_swap_type_multi+0xd4>)
    360a:	4816      	ldr	r0, [pc, #88]	; (3664 <boot_swap_type_multi+0xd8>)
    360c:	2149      	movs	r1, #73	; 0x49
    360e:	f002 ffae 	bl	656e <z_log_minimal_printk>
            if (table->swap_type != BOOT_SWAP_TYPE_TEST &&
    3612:	7960      	ldrb	r0, [r4, #5]
    3614:	1e83      	subs	r3, r0, #2
    3616:	2b02      	cmp	r3, #2
    3618:	d9c1      	bls.n	359e <boot_swap_type_multi+0x12>
    361a:	e7bf      	b.n	359c <boot_swap_type_multi+0x10>
    } else if (rc) {
    361c:	2800      	cmp	r0, #0
    361e:	d0cf      	beq.n	35c0 <boot_swap_type_multi+0x34>
    3620:	e7bc      	b.n	359c <boot_swap_type_multi+0x10>
            (table->copy_done_primary_slot == BOOT_FLAG_ANY  ||
    3622:	f89d 1002 	ldrb.w	r1, [sp, #2]
    3626:	4299      	cmp	r1, r3
    3628:	d0eb      	beq.n	3602 <boot_swap_type_multi+0x76>
    for (i = 0; i < BOOT_SWAP_TABLES_COUNT; i++) {
    362a:	3201      	adds	r2, #1
    362c:	2a03      	cmp	r2, #3
    362e:	f104 0406 	add.w	r4, r4, #6
    3632:	d1cb      	bne.n	35cc <boot_swap_type_multi+0x40>
    BOOT_LOG_INF("Swap type: none");
    3634:	480c      	ldr	r0, [pc, #48]	; (3668 <boot_swap_type_multi+0xdc>)
    3636:	2149      	movs	r1, #73	; 0x49
    3638:	f002 ff99 	bl	656e <z_log_minimal_printk>
    return BOOT_SWAP_TYPE_NONE;
    363c:	2001      	movs	r0, #1
    363e:	e7ae      	b.n	359e <boot_swap_type_multi+0x12>
            BOOT_LOG_INF("Swap type: %s",
    3640:	2b03      	cmp	r3, #3
    3642:	d005      	beq.n	3650 <boot_swap_type_multi+0xc4>
    3644:	4a09      	ldr	r2, [pc, #36]	; (366c <boot_swap_type_multi+0xe0>)
    3646:	490a      	ldr	r1, [pc, #40]	; (3670 <boot_swap_type_multi+0xe4>)
    3648:	2b04      	cmp	r3, #4
    364a:	bf08      	it	eq
    364c:	460a      	moveq	r2, r1
    364e:	e7dc      	b.n	360a <boot_swap_type_multi+0x7e>
    3650:	4a08      	ldr	r2, [pc, #32]	; (3674 <boot_swap_type_multi+0xe8>)
    3652:	e7da      	b.n	360a <boot_swap_type_multi+0x7e>
    3654:	000080ad 	.word	0x000080ad
    3658:	03030103 	.word	0x03030103
    365c:	00008120 	.word	0x00008120
    3660:	0000808f 	.word	0x0000808f
    3664:	000080f8 	.word	0x000080f8
    3668:	0000810b 	.word	0x0000810b
    366c:	00008094 	.word	0x00008094
    3670:	000080a6 	.word	0x000080a6
    3674:	0000808a 	.word	0x0000808a

00003678 <nrf52_errata_103>:
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    3678:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
            if (var1 == 0x08)
    367c:	f8d3 2130 	ldr.w	r2, [r3, #304]	; 0x130
    3680:	2a08      	cmp	r2, #8
    3682:	d106      	bne.n	3692 <nrf52_errata_103+0x1a>
            uint32_t var2 = *(uint32_t *)0x10000134ul;
    3684:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
                switch(var2)
    3688:	2b05      	cmp	r3, #5
    368a:	d802      	bhi.n	3692 <nrf52_errata_103+0x1a>
    368c:	4a02      	ldr	r2, [pc, #8]	; (3698 <nrf52_errata_103+0x20>)
    368e:	5cd0      	ldrb	r0, [r2, r3]
    3690:	4770      	bx	lr
                        return false;
    3692:	2000      	movs	r0, #0
}
    3694:	4770      	bx	lr
    3696:	bf00      	nop
    3698:	00008138 	.word	0x00008138

0000369c <nvmc_wait>:

/* -- NVMC utility functions -- */
/* Waits until NVMC is done with the current pending action */
void nvmc_wait(void)
{
    while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
    369c:	4a02      	ldr	r2, [pc, #8]	; (36a8 <nvmc_wait+0xc>)
    369e:	f8d2 3400 	ldr.w	r3, [r2, #1024]	; 0x400
    36a2:	2b00      	cmp	r3, #0
    36a4:	d0fb      	beq.n	369e <nvmc_wait+0x2>
}
    36a6:	4770      	bx	lr
    36a8:	4001e000 	.word	0x4001e000

000036ac <SystemInit>:
{
    SystemCoreClock = __SYSTEM_CLOCK_64M;
}

void SystemInit(void)
{
    36ac:	b510      	push	{r4, lr}
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    36ae:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
            if (var1 == 0x08)
    36b2:	f8d3 2130 	ldr.w	r2, [r3, #304]	; 0x130
    36b6:	2a08      	cmp	r2, #8
    36b8:	d14e      	bne.n	3758 <SystemInit+0xac>

    #if NRF52_ERRATA_36_ENABLE_WORKAROUND
        /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_36()){
            NRF_CLOCK->EVENTS_DONE = 0;
    36ba:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    36be:	2100      	movs	r1, #0
    36c0:	f8c2 110c 	str.w	r1, [r2, #268]	; 0x10c
            NRF_CLOCK->EVENTS_CTTO = 0;
    36c4:	f8c2 1110 	str.w	r1, [r2, #272]	; 0x110
            NRF_CLOCK->CTIV = 0;
    36c8:	f8c2 1538 	str.w	r1, [r2, #1336]	; 0x538

    #if NRF52_ERRATA_66_ENABLE_WORKAROUND
        /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_66()){
            NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
    36cc:	f502 4240 	add.w	r2, r2, #49152	; 0xc000
    36d0:	f8d3 1404 	ldr.w	r1, [r3, #1028]	; 0x404
    36d4:	f8c2 1520 	str.w	r1, [r2, #1312]	; 0x520
            NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
    36d8:	f8d3 1408 	ldr.w	r1, [r3, #1032]	; 0x408
    36dc:	f8c2 1524 	str.w	r1, [r2, #1316]	; 0x524
            NRF_TEMP->A2 = NRF_FICR->TEMP.A2;
    36e0:	f8d3 140c 	ldr.w	r1, [r3, #1036]	; 0x40c
    36e4:	f8c2 1528 	str.w	r1, [r2, #1320]	; 0x528
            NRF_TEMP->A3 = NRF_FICR->TEMP.A3;
    36e8:	f8d3 1410 	ldr.w	r1, [r3, #1040]	; 0x410
    36ec:	f8c2 152c 	str.w	r1, [r2, #1324]	; 0x52c
            NRF_TEMP->A4 = NRF_FICR->TEMP.A4;
    36f0:	f8d3 1414 	ldr.w	r1, [r3, #1044]	; 0x414
    36f4:	f8c2 1530 	str.w	r1, [r2, #1328]	; 0x530
            NRF_TEMP->A5 = NRF_FICR->TEMP.A5;
    36f8:	f8d3 1418 	ldr.w	r1, [r3, #1048]	; 0x418
    36fc:	f8c2 1534 	str.w	r1, [r2, #1332]	; 0x534
            NRF_TEMP->B0 = NRF_FICR->TEMP.B0;
    3700:	f8d3 141c 	ldr.w	r1, [r3, #1052]	; 0x41c
    3704:	f8c2 1540 	str.w	r1, [r2, #1344]	; 0x540
            NRF_TEMP->B1 = NRF_FICR->TEMP.B1;
    3708:	f8d3 1420 	ldr.w	r1, [r3, #1056]	; 0x420
    370c:	f8c2 1544 	str.w	r1, [r2, #1348]	; 0x544
            NRF_TEMP->B2 = NRF_FICR->TEMP.B2;
    3710:	f8d3 1424 	ldr.w	r1, [r3, #1060]	; 0x424
    3714:	f8c2 1548 	str.w	r1, [r2, #1352]	; 0x548
            NRF_TEMP->B3 = NRF_FICR->TEMP.B3;
    3718:	f8d3 1428 	ldr.w	r1, [r3, #1064]	; 0x428
    371c:	f8c2 154c 	str.w	r1, [r2, #1356]	; 0x54c
            NRF_TEMP->B4 = NRF_FICR->TEMP.B4;
    3720:	f8d3 142c 	ldr.w	r1, [r3, #1068]	; 0x42c
    3724:	f8c2 1550 	str.w	r1, [r2, #1360]	; 0x550
            NRF_TEMP->B5 = NRF_FICR->TEMP.B5;
    3728:	f8d3 1430 	ldr.w	r1, [r3, #1072]	; 0x430
    372c:	f8c2 1554 	str.w	r1, [r2, #1364]	; 0x554
            NRF_TEMP->T0 = NRF_FICR->TEMP.T0;
    3730:	f8d3 1434 	ldr.w	r1, [r3, #1076]	; 0x434
    3734:	f8c2 1560 	str.w	r1, [r2, #1376]	; 0x560
            NRF_TEMP->T1 = NRF_FICR->TEMP.T1;
    3738:	f8d3 1438 	ldr.w	r1, [r3, #1080]	; 0x438
    373c:	f8c2 1564 	str.w	r1, [r2, #1380]	; 0x564
            NRF_TEMP->T2 = NRF_FICR->TEMP.T2;
    3740:	f8d3 143c 	ldr.w	r1, [r3, #1084]	; 0x43c
    3744:	f8c2 1568 	str.w	r1, [r2, #1384]	; 0x568
            NRF_TEMP->T3 = NRF_FICR->TEMP.T3;
    3748:	f8d3 1440 	ldr.w	r1, [r3, #1088]	; 0x440
    374c:	f8c2 156c 	str.w	r1, [r2, #1388]	; 0x56c
            NRF_TEMP->T4 = NRF_FICR->TEMP.T4;
    3750:	f8d3 3444 	ldr.w	r3, [r3, #1092]	; 0x444
    3754:	f8c2 3570 	str.w	r3, [r2, #1392]	; 0x570
    #endif

    #if NRF52_ERRATA_98_ENABLE_WORKAROUND
        /* Workaround for Errata 98 "NFCT: Not able to communicate with the peer" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_98()){
    3758:	f7ff ff8e 	bl	3678 <nrf52_errata_103>
    375c:	b118      	cbz	r0, 3766 <SystemInit+0xba>
            *(volatile uint32_t *)0x4000568Cul = 0x00038148ul;
    375e:	4b43      	ldr	r3, [pc, #268]	; (386c <SystemInit+0x1c0>)
    3760:	4a43      	ldr	r2, [pc, #268]	; (3870 <SystemInit+0x1c4>)
    3762:	f8c3 268c 	str.w	r2, [r3, #1676]	; 0x68c
    #endif

    #if NRF52_ERRATA_103_ENABLE_WORKAROUND && defined(CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos)
        /* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_103()){
    3766:	f7ff ff87 	bl	3678 <nrf52_errata_103>
    376a:	b118      	cbz	r0, 3774 <SystemInit+0xc8>
            NRF_CCM->MAXPACKETSIZE = 0xFBul;
    376c:	4b41      	ldr	r3, [pc, #260]	; (3874 <SystemInit+0x1c8>)
    376e:	22fb      	movs	r2, #251	; 0xfb
    3770:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
    #endif

    #if NRF52_ERRATA_115_ENABLE_WORKAROUND
        /* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_115()){
    3774:	f7ff ff80 	bl	3678 <nrf52_errata_103>
    3778:	b170      	cbz	r0, 3798 <SystemInit+0xec>
            *(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) | (*(uint32_t *)0x10000258 & 0x0000000F);
    377a:	f04f 4180 	mov.w	r1, #1073741824	; 0x40000000
    377e:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    3782:	f8d1 2ee4 	ldr.w	r2, [r1, #3812]	; 0xee4
    3786:	f8d3 3258 	ldr.w	r3, [r3, #600]	; 0x258
    378a:	f022 020f 	bic.w	r2, r2, #15
    378e:	f003 030f 	and.w	r3, r3, #15
    3792:	4313      	orrs	r3, r2
    3794:	f8c1 3ee4 	str.w	r3, [r1, #3812]	; 0xee4
    #endif

    #if NRF52_ERRATA_120_ENABLE_WORKAROUND
        /* Workaround for Errata 120 "QSPI: Data read or written is corrupted" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_120()){
    3798:	f7ff ff6e 	bl	3678 <nrf52_errata_103>
    379c:	b120      	cbz	r0, 37a8 <SystemInit+0xfc>
            *(volatile uint32_t *)0x40029640ul = 0x200ul;
    379e:	4b36      	ldr	r3, [pc, #216]	; (3878 <SystemInit+0x1cc>)
    37a0:	f44f 7200 	mov.w	r2, #512	; 0x200
    37a4:	f8c3 2640 	str.w	r2, [r3, #1600]	; 0x640
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    37a8:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
            if (var1 == 0x08)
    37ac:	f8d3 3130 	ldr.w	r3, [r3, #304]	; 0x130
    37b0:	2b08      	cmp	r3, #8
    37b2:	d109      	bne.n	37c8 <SystemInit+0x11c>

    #if NRF52_ERRATA_136_ENABLE_WORKAROUND
        /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_136()){
            if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){
    37b4:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    37b8:	f8d3 2400 	ldr.w	r2, [r3, #1024]	; 0x400
    37bc:	07d2      	lsls	r2, r2, #31
                NRF_POWER->RESETREAS =  ~POWER_RESETREAS_RESETPIN_Msk;
    37be:	bf44      	itt	mi
    37c0:	f06f 0201 	mvnmi.w	r2, #1
    37c4:	f8c3 2400 	strmi.w	r2, [r3, #1024]	; 0x400

    /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
     * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
     * operations are not used in your code. */
    #if (__FPU_USED == 1)
        SCB->CPACR |= (3UL << 20) | (3UL << 22);
    37c8:	4a2c      	ldr	r2, [pc, #176]	; (387c <SystemInit+0x1d0>)
    37ca:	f8d2 3088 	ldr.w	r3, [r2, #136]	; 0x88
    37ce:	f443 0370 	orr.w	r3, r3, #15728640	; 0xf00000
    37d2:	f8c2 3088 	str.w	r3, [r2, #136]	; 0x88
  __ASM volatile ("dsb 0xF":::"memory");
    37d6:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    37da:	f3bf 8f6f 	isb	sy
         || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\
         || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\
         || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    37de:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
                        return true;
                }
            }
        #endif
        #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            if (var1 == 0x08)
    37e2:	f8d3 2130 	ldr.w	r2, [r3, #304]	; 0x130
    37e6:	2a08      	cmp	r2, #8
    37e8:	d10e      	bne.n	3808 <SystemInit+0x15c>
            uint32_t var2 = *(uint32_t *)0x10000134ul;
    37ea:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
            {
                switch(var2)
    37ee:	2b05      	cmp	r3, #5
    37f0:	d802      	bhi.n	37f8 <SystemInit+0x14c>
            {
                /* Prevent processor from unlocking APPROTECT soft branch after this point. */
                NRF_APPROTECT->FORCEPROTECT = APPROTECT_FORCEPROTECT_FORCEPROTECT_Force;
            }
        #else
            if (nrf52_configuration_249())
    37f2:	4a23      	ldr	r2, [pc, #140]	; (3880 <SystemInit+0x1d4>)
    37f4:	5cd3      	ldrb	r3, [r2, r3]
    37f6:	b13b      	cbz	r3, 3808 <SystemInit+0x15c>
            {
                /* Load APPROTECT soft branch from UICR.
                   If UICR->APPROTECT is disabled, POWER->APPROTECT will be disabled. */
                NRF_APPROTECT->DISABLE = NRF_UICR->APPROTECT;
    37f8:	f04f 2310 	mov.w	r3, #268439552	; 0x10001000
    37fc:	f8d3 2208 	ldr.w	r2, [r3, #520]	; 0x208
    3800:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    3804:	f8c3 2558 	str.w	r2, [r3, #1368]	; 0x558

    /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
      defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
      reserved for PinReset and not available as normal GPIO. */
    #if defined (CONFIG_GPIO_AS_PINRESET)
        if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
    3808:	f04f 2310 	mov.w	r3, #268439552	; 0x10001000
    380c:	f8d3 2200 	ldr.w	r2, [r3, #512]	; 0x200
    3810:	2a00      	cmp	r2, #0
    3812:	db03      	blt.n	381c <SystemInit+0x170>
            ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
    3814:	f8d3 3204 	ldr.w	r3, [r3, #516]	; 0x204
        if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
    3818:	2b00      	cmp	r3, #0
    381a:	da22      	bge.n	3862 <SystemInit+0x1b6>
    NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
    381c:	4919      	ldr	r1, [pc, #100]	; (3884 <SystemInit+0x1d8>)
    381e:	2301      	movs	r3, #1
            nvmc_config(NVMC_CONFIG_WEN_Wen);
            NRF_UICR->PSELRESET[0] = RESET_PIN;
    3820:	f04f 2010 	mov.w	r0, #268439552	; 0x10001000
    NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
    3824:	f8c1 3504 	str.w	r3, [r1, #1284]	; 0x504
            NRF_UICR->PSELRESET[0] = RESET_PIN;
    3828:	2412      	movs	r4, #18
    nvmc_wait();
    382a:	f7ff ff37 	bl	369c <nvmc_wait>
            NRF_UICR->PSELRESET[0] = RESET_PIN;
    382e:	f8c0 4200 	str.w	r4, [r0, #512]	; 0x200
            nvmc_wait();
    3832:	f7ff ff33 	bl	369c <nvmc_wait>
            NRF_UICR->PSELRESET[1] = RESET_PIN;
    3836:	f8c0 4204 	str.w	r4, [r0, #516]	; 0x204
            nvmc_wait();
    383a:	f7ff ff2f 	bl	369c <nvmc_wait>
    NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
    383e:	2300      	movs	r3, #0
    3840:	f8c1 3504 	str.w	r3, [r1, #1284]	; 0x504
    nvmc_wait();
    3844:	f7ff ff2a 	bl	369c <nvmc_wait>
  __ASM volatile ("dsb 0xF":::"memory");
    3848:	f3bf 8f4f 	dsb	sy
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    384c:	490b      	ldr	r1, [pc, #44]	; (387c <SystemInit+0x1d0>)
    384e:	4b0e      	ldr	r3, [pc, #56]	; (3888 <SystemInit+0x1dc>)
    3850:	68ca      	ldr	r2, [r1, #12]
    3852:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    3856:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    3858:	60cb      	str	r3, [r1, #12]
    385a:	f3bf 8f4f 	dsb	sy
    __NOP();
    385e:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    3860:	e7fd      	b.n	385e <SystemInit+0x1b2>
    SystemCoreClock = __SYSTEM_CLOCK_64M;
    3862:	4b0a      	ldr	r3, [pc, #40]	; (388c <SystemInit+0x1e0>)
    3864:	4a0a      	ldr	r2, [pc, #40]	; (3890 <SystemInit+0x1e4>)
    3866:	601a      	str	r2, [r3, #0]
            NVIC_SystemReset();
        }
    #endif

    SystemCoreClockUpdate();
}
    3868:	bd10      	pop	{r4, pc}
    386a:	bf00      	nop
    386c:	40005000 	.word	0x40005000
    3870:	00038148 	.word	0x00038148
    3874:	4000f000 	.word	0x4000f000
    3878:	40029000 	.word	0x40029000
    387c:	e000ed00 	.word	0xe000ed00
    3880:	00008132 	.word	0x00008132
    3884:	4001e000 	.word	0x4001e000
    3888:	05fa0004 	.word	0x05fa0004
    388c:	2000004c 	.word	0x2000004c
    3890:	03d09000 	.word	0x03d09000

00003894 <nrfx_flag32_alloc>:
{
    return (mask & NRFX_BIT(bitpos)) ? false : true;
}

nrfx_err_t nrfx_flag32_alloc(nrfx_atomic_t * p_mask, uint8_t *p_flag)
{
    3894:	b570      	push	{r4, r5, r6, lr}
        idx = 31 - NRF_CLZ(prev_mask);
        if (idx < 0) {
            return NRFX_ERROR_NO_MEM;
        }

        new_mask = prev_mask & ~NRFX_BIT(idx);
    3896:	2501      	movs	r5, #1
        prev_mask = *p_mask;
    3898:	6802      	ldr	r2, [r0, #0]
	return __atomic_compare_exchange_n(target, &old_value, new_value,
    389a:	f3bf 8f5b 	dmb	ish
        idx = 31 - NRF_CLZ(prev_mask);
    389e:	fab2 f382 	clz	r3, r2
    38a2:	f1c3 031f 	rsb	r3, r3, #31
    38a6:	b2db      	uxtb	r3, r3
        new_mask = prev_mask & ~NRFX_BIT(idx);
    38a8:	fa05 f403 	lsl.w	r4, r5, r3
    38ac:	ea22 0404 	bic.w	r4, r2, r4
    38b0:	e850 6f00 	ldrex	r6, [r0]
    38b4:	4296      	cmp	r6, r2
    38b6:	d104      	bne.n	38c2 <nrfx_flag32_alloc+0x2e>
    38b8:	e840 4c00 	strex	ip, r4, [r0]
    38bc:	f1bc 0f00 	cmp.w	ip, #0
    38c0:	d1f6      	bne.n	38b0 <nrfx_flag32_alloc+0x1c>
    38c2:	f3bf 8f5b 	dmb	ish
    } while (!NRFX_ATOMIC_CAS(p_mask, prev_mask, new_mask));
    38c6:	d1e7      	bne.n	3898 <nrfx_flag32_alloc+0x4>

    *p_flag = idx;

    return NRFX_SUCCESS;
}
    38c8:	4801      	ldr	r0, [pc, #4]	; (38d0 <nrfx_flag32_alloc+0x3c>)
    *p_flag = idx;
    38ca:	700b      	strb	r3, [r1, #0]
}
    38cc:	bd70      	pop	{r4, r5, r6, pc}
    38ce:	bf00      	nop
    38d0:	0bad0000 	.word	0x0bad0000

000038d4 <nrfx_flag32_free>:

nrfx_err_t nrfx_flag32_free(nrfx_atomic_t * p_mask, uint8_t flag)
{
    38d4:	b510      	push	{r4, lr}
    uint32_t new_mask, prev_mask;

    if ((NRFX_BIT(flag) & *p_mask))
    38d6:	6803      	ldr	r3, [r0, #0]
    38d8:	40cb      	lsrs	r3, r1
    38da:	07db      	lsls	r3, r3, #31
    38dc:	d414      	bmi.n	3908 <nrfx_flag32_free+0x34>
        return NRFX_ERROR_INVALID_PARAM;
    }

    do {
        prev_mask = *p_mask;
        new_mask = prev_mask | NRFX_BIT(flag);
    38de:	2301      	movs	r3, #1
    38e0:	408b      	lsls	r3, r1
        prev_mask = *p_mask;
    38e2:	6802      	ldr	r2, [r0, #0]
    38e4:	f3bf 8f5b 	dmb	ish
        new_mask = prev_mask | NRFX_BIT(flag);
    38e8:	ea43 0102 	orr.w	r1, r3, r2
    38ec:	e850 4f00 	ldrex	r4, [r0]
    38f0:	4294      	cmp	r4, r2
    38f2:	d104      	bne.n	38fe <nrfx_flag32_free+0x2a>
    38f4:	e840 1c00 	strex	ip, r1, [r0]
    38f8:	f1bc 0f00 	cmp.w	ip, #0
    38fc:	d1f6      	bne.n	38ec <nrfx_flag32_free+0x18>
    38fe:	f3bf 8f5b 	dmb	ish
    } while (!NRFX_ATOMIC_CAS(p_mask, prev_mask, new_mask));
    3902:	d1ee      	bne.n	38e2 <nrfx_flag32_free+0xe>

    return NRFX_SUCCESS;
    3904:	4801      	ldr	r0, [pc, #4]	; (390c <nrfx_flag32_free+0x38>)
}
    3906:	bd10      	pop	{r4, pc}
        return NRFX_ERROR_INVALID_PARAM;
    3908:	4801      	ldr	r0, [pc, #4]	; (3910 <nrfx_flag32_free+0x3c>)
    390a:	e7fc      	b.n	3906 <nrfx_flag32_free+0x32>
    390c:	0bad0000 	.word	0x0bad0000
    3910:	0bad0004 	.word	0x0bad0004

00003914 <clock_stop>:
    CoreDebug->DEMCR = core_debug;
}
#endif // NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_132)

static void clock_stop(nrf_clock_domain_t domain)
{
    3914:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
    switch (domain)
    3916:	4604      	mov	r4, r0
    3918:	b118      	cbz	r0, 3922 <clock_stop+0xe>
    391a:	2801      	cmp	r0, #1
    391c:	d022      	beq.n	3964 <clock_stop+0x50>
    if (domain == NRF_CLOCK_DOMAIN_HFCLK)
    {
            m_clock_cb.hfclk_started = false;
    }
#endif
}
    391e:	b003      	add	sp, #12
    3920:	bdf0      	pop	{r4, r5, r6, r7, pc}
    p_reg->INTENCLR = mask;
    3922:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    3926:	2202      	movs	r2, #2
    3928:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    392c:	f8c3 0104 	str.w	r0, [r3, #260]	; 0x104
    3930:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    3934:	2201      	movs	r2, #1
    3936:	60da      	str	r2, [r3, #12]
    nrf_clock_hfclk_t *p_clk_src = (domain == NRF_CLOCK_DOMAIN_HFCLK) ? &clk_src : NULL;
    3938:	4607      	mov	r7, r0
    nrf_clock_hfclk_t clk_src = NRF_CLOCK_HFCLK_HIGH_ACCURACY;
    393a:	2301      	movs	r3, #1
    393c:	f88d 3007 	strb.w	r3, [sp, #7]
    3940:	f242 7510 	movw	r5, #10000	; 0x2710
    3944:	f04f 4680 	mov.w	r6, #1073741824	; 0x40000000
    switch (domain)
    3948:	b1cc      	cbz	r4, 397e <clock_stop+0x6a>
    394a:	2c01      	cmp	r4, #1
    394c:	d1e7      	bne.n	391e <clock_stop+0xa>
            if (p_clk_src != NULL)
    394e:	b3c7      	cbz	r7, 39c2 <clock_stop+0xae>
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    3950:	f8d6 340c 	ldr.w	r3, [r6, #1036]	; 0x40c
    3954:	f003 0301 	and.w	r3, r3, #1
                (*(nrf_clock_hfclk_t *)p_clk_src) =
    3958:	703b      	strb	r3, [r7, #0]
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    395a:	f8d6 340c 	ldr.w	r3, [r6, #1036]	; 0x40c
    395e:	03da      	lsls	r2, r3, #15
    3960:	d521      	bpl.n	39a6 <clock_stop+0x92>
    3962:	e016      	b.n	3992 <clock_stop+0x7e>
    p_reg->INTENCLR = mask;
    3964:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3968:	2200      	movs	r2, #0
    p_reg->INTENCLR = mask;
    396a:	f8c3 0308 	str.w	r0, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    396e:	f8c3 2100 	str.w	r2, [r3, #256]	; 0x100
    3972:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    3976:	6058      	str	r0, [r3, #4]
    nrf_clock_hfclk_t *p_clk_src = (domain == NRF_CLOCK_DOMAIN_HFCLK) ? &clk_src : NULL;
    3978:	f10d 0707 	add.w	r7, sp, #7
    397c:	e7dd      	b.n	393a <clock_stop+0x26>
            if (p_clk_src != NULL)
    397e:	b1b7      	cbz	r7, 39ae <clock_stop+0x9a>
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    3980:	f8d6 3418 	ldr.w	r3, [r6, #1048]	; 0x418
                                        >> CLOCK_LFCLKSTAT_SRC_Pos);
    3984:	f003 0303 	and.w	r3, r3, #3
                (*(nrf_clock_lfclk_t *)p_clk_src) =
    3988:	603b      	str	r3, [r7, #0]
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    398a:	f8d6 3418 	ldr.w	r3, [r6, #1048]	; 0x418
    398e:	03d8      	lsls	r0, r3, #15
    3990:	d5c5      	bpl.n	391e <clock_stop+0xa>
    NRFX_WAIT_FOR((!nrfx_clock_is_running(domain, p_clk_src) ||
    3992:	f89d 0007 	ldrb.w	r0, [sp, #7]
    3996:	2801      	cmp	r0, #1
    3998:	d103      	bne.n	39a2 <clock_stop+0x8e>
    399a:	f003 f9a4 	bl	6ce6 <nrfx_busy_wait>
    399e:	3d01      	subs	r5, #1
    39a0:	d1d2      	bne.n	3948 <clock_stop+0x34>
    if (domain == NRF_CLOCK_DOMAIN_HFCLK)
    39a2:	2c01      	cmp	r4, #1
    39a4:	d1bb      	bne.n	391e <clock_stop+0xa>
            m_clock_cb.hfclk_started = false;
    39a6:	4b0c      	ldr	r3, [pc, #48]	; (39d8 <clock_stop+0xc4>)
    39a8:	2200      	movs	r2, #0
    39aa:	715a      	strb	r2, [r3, #5]
    39ac:	e7b7      	b.n	391e <clock_stop+0xa>
    39ae:	f8d6 3418 	ldr.w	r3, [r6, #1048]	; 0x418
    39b2:	03d9      	lsls	r1, r3, #15
    39b4:	d5b3      	bpl.n	391e <clock_stop+0xa>
    NRFX_WAIT_FOR((!nrfx_clock_is_running(domain, p_clk_src) ||
    39b6:	2001      	movs	r0, #1
    39b8:	f003 f995 	bl	6ce6 <nrfx_busy_wait>
    39bc:	3d01      	subs	r5, #1
    39be:	d1f6      	bne.n	39ae <clock_stop+0x9a>
    39c0:	e7ad      	b.n	391e <clock_stop+0xa>
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    39c2:	f8d6 340c 	ldr.w	r3, [r6, #1036]	; 0x40c
    39c6:	03db      	lsls	r3, r3, #15
    39c8:	d5ed      	bpl.n	39a6 <clock_stop+0x92>
    39ca:	2001      	movs	r0, #1
    39cc:	f003 f98b 	bl	6ce6 <nrfx_busy_wait>
    39d0:	3d01      	subs	r5, #1
    39d2:	d1f6      	bne.n	39c2 <clock_stop+0xae>
    39d4:	e7e7      	b.n	39a6 <clock_stop+0x92>
    39d6:	bf00      	nop
    39d8:	20000ef0 	.word	0x20000ef0

000039dc <nrfx_clock_init>:
nrfx_err_t nrfx_clock_init(nrfx_clock_event_handler_t event_handler)
{
    NRFX_ASSERT(event_handler);

    nrfx_err_t err_code = NRFX_SUCCESS;
    if (m_clock_cb.module_initialized)
    39dc:	4b04      	ldr	r3, [pc, #16]	; (39f0 <nrfx_clock_init+0x14>)
    39de:	791a      	ldrb	r2, [r3, #4]
    39e0:	b922      	cbnz	r2, 39ec <nrfx_clock_init+0x10>
    {
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
        m_clock_cb.cal_state = CAL_STATE_IDLE;
#endif
        m_clock_cb.event_handler = event_handler;
        m_clock_cb.module_initialized = true;
    39e2:	2201      	movs	r2, #1
        m_clock_cb.event_handler = event_handler;
    39e4:	6018      	str	r0, [r3, #0]
        m_clock_cb.module_initialized = true;
    39e6:	809a      	strh	r2, [r3, #4]
    nrfx_err_t err_code = NRFX_SUCCESS;
    39e8:	4802      	ldr	r0, [pc, #8]	; (39f4 <nrfx_clock_init+0x18>)
    39ea:	4770      	bx	lr
        err_code = NRFX_ERROR_ALREADY_INITIALIZED;
    39ec:	4802      	ldr	r0, [pc, #8]	; (39f8 <nrfx_clock_init+0x1c>)
#endif
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    39ee:	4770      	bx	lr
    39f0:	20000ef0 	.word	0x20000ef0
    39f4:	0bad0000 	.word	0x0bad0000
    39f8:	0bad000c 	.word	0x0bad000c

000039fc <nrfx_power_clock_irq_handler>:
    }
}
#endif

void nrfx_clock_irq_handler(void)
{
    39fc:	b510      	push	{r4, lr}
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    39fe:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    3a02:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED))
    3a06:	b16a      	cbz	r2, 3a24 <nrfx_power_clock_irq_handler+0x28>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3a08:	2200      	movs	r2, #0
    3a0a:	f8c3 2100 	str.w	r2, [r3, #256]	; 0x100
    3a0e:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    p_reg->INTENCLR = mask;
    3a12:	2201      	movs	r2, #1
    3a14:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
        nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED);
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_HFCLKSTARTED");
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF_STARTED_MASK);

#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_201)
        if (!m_clock_cb.hfclk_started)
    3a18:	4b11      	ldr	r3, [pc, #68]	; (3a60 <nrfx_power_clock_irq_handler+0x64>)
    3a1a:	7958      	ldrb	r0, [r3, #5]
    3a1c:	b910      	cbnz	r0, 3a24 <nrfx_power_clock_irq_handler+0x28>
        {
            m_clock_cb.hfclk_started = true;
    3a1e:	715a      	strb	r2, [r3, #5]
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
    3a20:	681b      	ldr	r3, [r3, #0]
    3a22:	4798      	blx	r3
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    3a24:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    3a28:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
        }
#else
        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
#endif
    }
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED))
    3a2c:	b172      	cbz	r2, 3a4c <nrfx_power_clock_irq_handler+0x50>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3a2e:	2200      	movs	r2, #0
    3a30:	f8c3 2104 	str.w	r2, [r3, #260]	; 0x104
    3a34:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    3a38:	f8d3 2418 	ldr.w	r2, [r3, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    3a3c:	f8d3 1418 	ldr.w	r1, [r3, #1048]	; 0x418
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_LFCLKSTARTED");

#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED)
        nrf_clock_lfclk_t lfclksrc;
        (void)nrf_clock_is_running(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK, &lfclksrc);
        if (lfclksrc == NRF_CLOCK_LFCLK_RC)
    3a40:	0792      	lsls	r2, r2, #30
    3a42:	d104      	bne.n	3a4e <nrfx_power_clock_irq_handler+0x52>
    p_reg->LFCLKSRC = (uint32_t)(source);
    3a44:	2201      	movs	r2, #1
    3a46:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    3a4a:	609a      	str	r2, [r3, #8]
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF192M_STARTED_MASK);

        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK192M_STARTED);
    }
#endif
}
    3a4c:	bd10      	pop	{r4, pc}
    p_reg->INTENCLR = mask;
    3a4e:	2202      	movs	r2, #2
    3a50:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    3a54:	4b02      	ldr	r3, [pc, #8]	; (3a60 <nrfx_power_clock_irq_handler+0x64>)
}
    3a56:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    3a5a:	681b      	ldr	r3, [r3, #0]
    3a5c:	2001      	movs	r0, #1
    3a5e:	4718      	bx	r3
    3a60:	20000ef0 	.word	0x20000ef0

00003a64 <nrf_gpio_pin_port_decode>:
    uint32_t pin_number = *p_pin;
    3a64:	6803      	ldr	r3, [r0, #0]
    *p_pin = pin_number & 0x1F;
    3a66:	f003 021f 	and.w	r2, r3, #31
    return pin_number >> 5;
    3a6a:	095b      	lsrs	r3, r3, #5
        case 0: return NRF_P0;
    3a6c:	2b01      	cmp	r3, #1
    *p_pin = pin_number & 0x1F;
    3a6e:	6002      	str	r2, [r0, #0]
}
    3a70:	4802      	ldr	r0, [pc, #8]	; (3a7c <nrf_gpio_pin_port_decode+0x18>)
    3a72:	bf18      	it	ne
    3a74:	f04f 40a0 	movne.w	r0, #1342177280	; 0x50000000
    3a78:	4770      	bx	lr
    3a7a:	bf00      	nop
    3a7c:	50000300 	.word	0x50000300

00003a80 <pin_in_use_by_te>:
 *
 * @return True if pin uses GPIOTE task/event.
 */
static bool pin_in_use_by_te(uint32_t pin)
{
    return m_cb.pin_flags[pin] & PIN_FLAG_TE_USED;
    3a80:	4b03      	ldr	r3, [pc, #12]	; (3a90 <pin_in_use_by_te+0x10>)
    3a82:	3008      	adds	r0, #8
    3a84:	f833 0010 	ldrh.w	r0, [r3, r0, lsl #1]
}
    3a88:	f3c0 1040 	ubfx	r0, r0, #5, #1
    3a8c:	4770      	bx	lr
    3a8e:	bf00      	nop
    3a90:	20000050 	.word	0x20000050

00003a94 <call_handler>:
    nrf_gpiote_event_t event = nrfx_gpiote_in_event_get(pin);
    return nrf_gpiote_event_address_get(NRF_GPIOTE, event);
}

static void call_handler(nrfx_gpiote_pin_t pin, nrfx_gpiote_trigger_t trigger)
{
    3a94:	b570      	push	{r4, r5, r6, lr}
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    3a96:	f100 0308 	add.w	r3, r0, #8
    3a9a:	4c0c      	ldr	r4, [pc, #48]	; (3acc <call_handler+0x38>)
    3a9c:	f834 3013 	ldrh.w	r3, [r4, r3, lsl #1]
    3aa0:	05da      	lsls	r2, r3, #23
{
    3aa2:	4605      	mov	r5, r0
    3aa4:	460e      	mov	r6, r1
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    3aa6:	d507      	bpl.n	3ab8 <call_handler+0x24>
    3aa8:	f3c3 2343 	ubfx	r3, r3, #9, #4
    nrfx_gpiote_handler_config_t const * handler = channel_handler_get(pin);

    if (handler)
    {
        handler->handler(pin, trigger, handler->p_context);
    3aac:	eb04 02c3 	add.w	r2, r4, r3, lsl #3
    3ab0:	f854 3033 	ldr.w	r3, [r4, r3, lsl #3]
    3ab4:	6852      	ldr	r2, [r2, #4]
    3ab6:	4798      	blx	r3
    }
    if (m_cb.global_handler.handler)
    3ab8:	68a3      	ldr	r3, [r4, #8]
    3aba:	b12b      	cbz	r3, 3ac8 <call_handler+0x34>
    {
        m_cb.global_handler.handler(pin, trigger, m_cb.global_handler.p_context);
    3abc:	68e2      	ldr	r2, [r4, #12]
    3abe:	4631      	mov	r1, r6
    3ac0:	4628      	mov	r0, r5
    }
}
    3ac2:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
        m_cb.global_handler.handler(pin, trigger, m_cb.global_handler.p_context);
    3ac6:	4718      	bx	r3
}
    3ac8:	bd70      	pop	{r4, r5, r6, pc}
    3aca:	bf00      	nop
    3acc:	20000050 	.word	0x20000050

00003ad0 <release_handler>:
{
    3ad0:	b410      	push	{r4}
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    3ad2:	4a13      	ldr	r2, [pc, #76]	; (3b20 <release_handler+0x50>)
    3ad4:	3008      	adds	r0, #8
    3ad6:	f832 3010 	ldrh.w	r3, [r2, r0, lsl #1]
    3ada:	05d9      	lsls	r1, r3, #23
    3adc:	d51c      	bpl.n	3b18 <release_handler+0x48>
    3ade:	f3c3 2143 	ubfx	r1, r3, #9, #4
    m_cb.pin_flags[pin] &= ~PIN_HANDLER_MASK;
    3ae2:	f423 53f8 	bic.w	r3, r3, #7936	; 0x1f00
    3ae6:	f822 3010 	strh.w	r3, [r2, r0, lsl #1]
    for (uint32_t i = 0; i < MAX_PIN_NUMBER; i++)
    3aea:	f102 040e 	add.w	r4, r2, #14
    3aee:	2000      	movs	r0, #0
        if (PIN_GET_HANDLER_ID(m_cb.pin_flags[i]) == handler_id)
    3af0:	f834 3f02 	ldrh.w	r3, [r4, #2]!
    3af4:	f413 7f80 	tst.w	r3, #256	; 0x100
    3af8:	d003      	beq.n	3b02 <release_handler+0x32>
    3afa:	f3c3 2343 	ubfx	r3, r3, #9, #4
    3afe:	4299      	cmp	r1, r3
    3b00:	d00a      	beq.n	3b18 <release_handler+0x48>
    for (uint32_t i = 0; i < MAX_PIN_NUMBER; i++)
    3b02:	3001      	adds	r0, #1
    3b04:	2830      	cmp	r0, #48	; 0x30
    3b06:	d1f3      	bne.n	3af0 <release_handler+0x20>
        m_cb.handlers[handler_id].handler = NULL;
    3b08:	2300      	movs	r3, #0
    3b0a:	f842 3031 	str.w	r3, [r2, r1, lsl #3]
        nrfx_err_t err = nrfx_flag32_free(&m_cb.available_evt_handlers, handler_id);
    3b0e:	4805      	ldr	r0, [pc, #20]	; (3b24 <release_handler+0x54>)
}
    3b10:	f85d 4b04 	ldr.w	r4, [sp], #4
        nrfx_err_t err = nrfx_flag32_free(&m_cb.available_evt_handlers, handler_id);
    3b14:	f7ff bede 	b.w	38d4 <nrfx_flag32_free>
}
    3b18:	f85d 4b04 	ldr.w	r4, [sp], #4
    3b1c:	4770      	bx	lr
    3b1e:	bf00      	nop
    3b20:	20000050 	.word	0x20000050
    3b24:	200000c4 	.word	0x200000c4

00003b28 <pin_handler_trigger_uninit>:
{
    3b28:	b538      	push	{r3, r4, r5, lr}
    3b2a:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin))
    3b2c:	f7ff ffa8 	bl	3a80 <pin_in_use_by_te>
    3b30:	4c09      	ldr	r4, [pc, #36]	; (3b58 <pin_handler_trigger_uninit+0x30>)
    3b32:	f102 0508 	add.w	r5, r2, #8
    3b36:	b140      	cbz	r0, 3b4a <pin_handler_trigger_uninit+0x22>
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    3b38:	f834 3015 	ldrh.w	r3, [r4, r5, lsl #1]
                         ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
}

NRF_STATIC_INLINE void nrf_gpiote_te_default(NRF_GPIOTE_Type * p_reg, uint32_t idx)
{
    p_reg->CONFIG[idx] = 0;
    3b3c:	4907      	ldr	r1, [pc, #28]	; (3b5c <pin_handler_trigger_uninit+0x34>)
        nrf_gpiote_te_default(NRF_GPIOTE, pin_te_get(pin));
    3b3e:	0b5b      	lsrs	r3, r3, #13
    3b40:	f503 73a2 	add.w	r3, r3, #324	; 0x144
    3b44:	2000      	movs	r0, #0
    3b46:	f841 0023 	str.w	r0, [r1, r3, lsl #2]
    release_handler(pin);
    3b4a:	4610      	mov	r0, r2
    3b4c:	f7ff ffc0 	bl	3ad0 <release_handler>
    m_cb.pin_flags[pin] = PIN_FLAG_NOT_USED;
    3b50:	2300      	movs	r3, #0
    3b52:	f824 3015 	strh.w	r3, [r4, r5, lsl #1]
}
    3b56:	bd38      	pop	{r3, r4, r5, pc}
    3b58:	20000050 	.word	0x20000050
    3b5c:	40006000 	.word	0x40006000

00003b60 <nrfx_gpiote_input_configure>:
{
    3b60:	e92d 41ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr}
    3b64:	4604      	mov	r4, r0
    3b66:	4616      	mov	r6, r2
    3b68:	461d      	mov	r5, r3
    if (p_input_config)
    3b6a:	b301      	cbz	r1, 3bae <nrfx_gpiote_input_configure+0x4e>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    3b6c:	4f4e      	ldr	r7, [pc, #312]	; (3ca8 <nrfx_gpiote_input_configure+0x148>)
    3b6e:	f100 0808 	add.w	r8, r0, #8
    return pin_is_output(pin) && pin_in_use_by_te(pin);
    3b72:	f837 3018 	ldrh.w	r3, [r7, r8, lsl #1]
    3b76:	079b      	lsls	r3, r3, #30
    3b78:	d502      	bpl.n	3b80 <nrfx_gpiote_input_configure+0x20>
    3b7a:	f7ff ff81 	bl	3a80 <pin_in_use_by_te>
    3b7e:	bb10      	cbnz	r0, 3bc6 <nrfx_gpiote_input_configure+0x66>
        nrf_gpio_pin_dir_t dir = NRF_GPIO_PIN_DIR_INPUT;
    3b80:	2300      	movs	r3, #0
        nrf_gpio_reconfigure(pin, &dir, &input_connect, &p_input_config->pull, NULL, NULL);
    3b82:	e9cd 3300 	strd	r3, r3, [sp]
        nrf_gpio_pin_dir_t dir = NRF_GPIO_PIN_DIR_INPUT;
    3b86:	f88d 300e 	strb.w	r3, [sp, #14]
        nrf_gpio_pin_input_t input_connect = NRF_GPIO_PIN_INPUT_CONNECT;
    3b8a:	f88d 300f 	strb.w	r3, [sp, #15]
        nrf_gpio_reconfigure(pin, &dir, &input_connect, &p_input_config->pull, NULL, NULL);
    3b8e:	f10d 020f 	add.w	r2, sp, #15
    3b92:	460b      	mov	r3, r1
    3b94:	4620      	mov	r0, r4
    3b96:	f10d 010e 	add.w	r1, sp, #14
    3b9a:	f003 f8f1 	bl	6d80 <nrf_gpio_reconfigure>
        m_cb.pin_flags[pin] &= ~PIN_FLAG_OUTPUT;
    3b9e:	f837 3018 	ldrh.w	r3, [r7, r8, lsl #1]
    3ba2:	f023 0302 	bic.w	r3, r3, #2
        m_cb.pin_flags[pin] |= PIN_FLAG_IN_USE;
    3ba6:	f043 0301 	orr.w	r3, r3, #1
    3baa:	f827 3018 	strh.w	r3, [r7, r8, lsl #1]
    if (p_trigger_config)
    3bae:	b346      	cbz	r6, 3c02 <nrfx_gpiote_input_configure+0xa2>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    3bb0:	4b3d      	ldr	r3, [pc, #244]	; (3ca8 <nrfx_gpiote_input_configure+0x148>)
        nrfx_gpiote_trigger_t trigger = p_trigger_config->trigger;
    3bb2:	f896 c000 	ldrb.w	ip, [r6]
        bool use_evt = p_trigger_config->p_in_channel ? true : false;
    3bb6:	6872      	ldr	r2, [r6, #4]
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    3bb8:	f104 0708 	add.w	r7, r4, #8
    3bbc:	f833 1017 	ldrh.w	r1, [r3, r7, lsl #1]
        if (pin_is_output(pin))
    3bc0:	0788      	lsls	r0, r1, #30
    3bc2:	d502      	bpl.n	3bca <nrfx_gpiote_input_configure+0x6a>
            if (use_evt)
    3bc4:	b1aa      	cbz	r2, 3bf2 <nrfx_gpiote_input_configure+0x92>
            return NRFX_ERROR_INVALID_PARAM;
    3bc6:	4839      	ldr	r0, [pc, #228]	; (3cac <nrfx_gpiote_input_configure+0x14c>)
    3bc8:	e01d      	b.n	3c06 <nrfx_gpiote_input_configure+0xa6>
            m_cb.pin_flags[pin] &= ~(PIN_TE_ID_MASK | PIN_FLAG_TE_USED);
    3bca:	f021 0120 	bic.w	r1, r1, #32
    3bce:	04c9      	lsls	r1, r1, #19
    3bd0:	0cc9      	lsrs	r1, r1, #19
    3bd2:	f823 1017 	strh.w	r1, [r3, r7, lsl #1]
            if (use_evt)
    3bd6:	b162      	cbz	r2, 3bf2 <nrfx_gpiote_input_configure+0x92>
                if (!edge)
    3bd8:	f1bc 0f03 	cmp.w	ip, #3
    3bdc:	d8f3      	bhi.n	3bc6 <nrfx_gpiote_input_configure+0x66>
                uint8_t ch = *p_trigger_config->p_in_channel;
    3bde:	6872      	ldr	r2, [r6, #4]
    3be0:	7816      	ldrb	r6, [r2, #0]
                if (trigger == NRFX_GPIOTE_TRIGGER_NONE)
    3be2:	f1bc 0f00 	cmp.w	ip, #0
    3be6:	d111      	bne.n	3c0c <nrfx_gpiote_input_configure+0xac>
    3be8:	4a31      	ldr	r2, [pc, #196]	; (3cb0 <nrfx_gpiote_input_configure+0x150>)
    3bea:	f506 76a2 	add.w	r6, r6, #324	; 0x144
    3bee:	f842 c026 	str.w	ip, [r2, r6, lsl #2]
        m_cb.pin_flags[pin] &= ~PIN_FLAG_TRIG_MODE_MASK;
    3bf2:	f833 2017 	ldrh.w	r2, [r3, r7, lsl #1]
    3bf6:	f022 021c 	bic.w	r2, r2, #28
        m_cb.pin_flags[pin] |= PIN_FLAG_TRIG_MODE_SET(trigger);
    3bfa:	ea42 028c 	orr.w	r2, r2, ip, lsl #2
    3bfe:	f823 2017 	strh.w	r2, [r3, r7, lsl #1]
    if (p_handler_config)
    3c02:	bb45      	cbnz	r5, 3c56 <nrfx_gpiote_input_configure+0xf6>
        err = NRFX_SUCCESS;
    3c04:	482b      	ldr	r0, [pc, #172]	; (3cb4 <nrfx_gpiote_input_configure+0x154>)
}
    3c06:	b004      	add	sp, #16
    3c08:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
   p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk;
    3c0c:	00b2      	lsls	r2, r6, #2
    3c0e:	f102 4280 	add.w	r2, r2, #1073741824	; 0x40000000
    3c12:	f502 42c0 	add.w	r2, r2, #24576	; 0x6000
                    m_cb.pin_flags[pin] |= PIN_FLAG_TE_ID(ch);
    3c16:	ea41 3146 	orr.w	r1, r1, r6, lsl #13
    3c1a:	f8d2 0510 	ldr.w	r0, [r2, #1296]	; 0x510
    3c1e:	f020 0003 	bic.w	r0, r0, #3
    3c22:	f8c2 0510 	str.w	r0, [r2, #1296]	; 0x510
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk);
    3c26:	f8d2 0510 	ldr.w	r0, [r2, #1296]	; 0x510
    3c2a:	f420 304f 	bic.w	r0, r0, #211968	; 0x33c00
    3c2e:	f420 7040 	bic.w	r0, r0, #768	; 0x300
    3c32:	f8c2 0510 	str.w	r0, [r2, #1296]	; 0x510
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    3c36:	0220      	lsls	r0, r4, #8
    3c38:	f8d2 e510 	ldr.w	lr, [r2, #1296]	; 0x510
    3c3c:	f400 507c 	and.w	r0, r0, #16128	; 0x3f00
    3c40:	ea40 400c 	orr.w	r0, r0, ip, lsl #16
    3c44:	ea40 000e 	orr.w	r0, r0, lr
    3c48:	f041 0120 	orr.w	r1, r1, #32
    3c4c:	f823 1017 	strh.w	r1, [r3, r7, lsl #1]
    3c50:	f8c2 0510 	str.w	r0, [r2, #1296]	; 0x510
    3c54:	e7cd      	b.n	3bf2 <nrfx_gpiote_input_configure+0x92>
        err = pin_handler_set(pin, p_handler_config->handler, p_handler_config->p_context);
    3c56:	e9d5 6700 	ldrd	r6, r7, [r5]
    release_handler(pin);
    3c5a:	4620      	mov	r0, r4
    3c5c:	f7ff ff38 	bl	3ad0 <release_handler>
    if (!handler)
    3c60:	2e00      	cmp	r6, #0
    3c62:	d0cf      	beq.n	3c04 <nrfx_gpiote_input_configure+0xa4>
        if ((m_cb.handlers[i].handler == handler) && (m_cb.handlers[i].p_context == p_context))
    3c64:	4d10      	ldr	r5, [pc, #64]	; (3ca8 <nrfx_gpiote_input_configure+0x148>)
    3c66:	e9d5 2300 	ldrd	r2, r3, [r5]
    3c6a:	4296      	cmp	r6, r2
    3c6c:	d101      	bne.n	3c72 <nrfx_gpiote_input_configure+0x112>
    3c6e:	429f      	cmp	r7, r3
    3c70:	d018      	beq.n	3ca4 <nrfx_gpiote_input_configure+0x144>
        err = nrfx_flag32_alloc(&m_cb.available_evt_handlers, &id);
    3c72:	4811      	ldr	r0, [pc, #68]	; (3cb8 <nrfx_gpiote_input_configure+0x158>)
    3c74:	f10d 010f 	add.w	r1, sp, #15
    3c78:	f7ff fe0c 	bl	3894 <nrfx_flag32_alloc>
        if (err != NRFX_SUCCESS)
    3c7c:	4b0d      	ldr	r3, [pc, #52]	; (3cb4 <nrfx_gpiote_input_configure+0x154>)
    3c7e:	4298      	cmp	r0, r3
    3c80:	d1c1      	bne.n	3c06 <nrfx_gpiote_input_configure+0xa6>
        handler_id = (int32_t)id;
    3c82:	f89d 200f 	ldrb.w	r2, [sp, #15]
    m_cb.handlers[handler_id].handler = handler;
    3c86:	f845 6032 	str.w	r6, [r5, r2, lsl #3]
    m_cb.handlers[handler_id].p_context = p_context;
    3c8a:	eb05 03c2 	add.w	r3, r5, r2, lsl #3
    m_cb.pin_flags[pin] |= PIN_FLAG_HANDLER(handler_id);
    3c8e:	3408      	adds	r4, #8
    m_cb.handlers[handler_id].p_context = p_context;
    3c90:	605f      	str	r7, [r3, #4]
    m_cb.pin_flags[pin] |= PIN_FLAG_HANDLER(handler_id);
    3c92:	f835 3014 	ldrh.w	r3, [r5, r4, lsl #1]
    3c96:	ea43 2342 	orr.w	r3, r3, r2, lsl #9
    3c9a:	f443 7380 	orr.w	r3, r3, #256	; 0x100
    3c9e:	f825 3014 	strh.w	r3, [r5, r4, lsl #1]
    return NRFX_SUCCESS;
    3ca2:	e7af      	b.n	3c04 <nrfx_gpiote_input_configure+0xa4>
        if ((m_cb.handlers[i].handler == handler) && (m_cb.handlers[i].p_context == p_context))
    3ca4:	2200      	movs	r2, #0
    3ca6:	e7ee      	b.n	3c86 <nrfx_gpiote_input_configure+0x126>
    3ca8:	20000050 	.word	0x20000050
    3cac:	0bad0004 	.word	0x0bad0004
    3cb0:	40006000 	.word	0x40006000
    3cb4:	0bad0000 	.word	0x0bad0000
    3cb8:	200000c4 	.word	0x200000c4

00003cbc <nrfx_gpiote_output_configure>:
{
    3cbc:	b5f0      	push	{r4, r5, r6, r7, lr}
    3cbe:	4604      	mov	r4, r0
    3cc0:	b085      	sub	sp, #20
    3cc2:	4615      	mov	r5, r2
    if (p_config)
    3cc4:	b319      	cbz	r1, 3d0e <nrfx_gpiote_output_configure+0x52>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    3cc6:	4e33      	ldr	r6, [pc, #204]	; (3d94 <nrfx_gpiote_output_configure+0xd8>)
    3cc8:	f100 0708 	add.w	r7, r0, #8
    3ccc:	f836 2017 	ldrh.w	r2, [r6, r7, lsl #1]
        if (pin_is_input(pin) && pin_in_use_by_te(pin))
    3cd0:	0793      	lsls	r3, r2, #30
    3cd2:	d403      	bmi.n	3cdc <nrfx_gpiote_output_configure+0x20>
    3cd4:	f7ff fed4 	bl	3a80 <pin_in_use_by_te>
    3cd8:	2800      	cmp	r0, #0
    3cda:	d158      	bne.n	3d8e <nrfx_gpiote_output_configure+0xd2>
        if (pin_has_trigger(pin) && (p_config->input_connect == NRF_GPIO_PIN_INPUT_DISCONNECT))
    3cdc:	f012 0f1c 	tst.w	r2, #28
    3ce0:	d002      	beq.n	3ce8 <nrfx_gpiote_output_configure+0x2c>
    3ce2:	784b      	ldrb	r3, [r1, #1]
    3ce4:	2b01      	cmp	r3, #1
    3ce6:	d052      	beq.n	3d8e <nrfx_gpiote_output_configure+0xd2>
        nrf_gpio_pin_dir_t dir = NRF_GPIO_PIN_DIR_OUTPUT;
    3ce8:	2301      	movs	r3, #1
    3cea:	f88d 300f 	strb.w	r3, [sp, #15]
        nrf_gpio_reconfigure(pin, &dir, &p_config->input_connect, &p_config->pull,
    3cee:	2300      	movs	r3, #0
    3cf0:	e9cd 1300 	strd	r1, r3, [sp]
    3cf4:	1c4a      	adds	r2, r1, #1
    3cf6:	1c8b      	adds	r3, r1, #2
    3cf8:	4620      	mov	r0, r4
    3cfa:	f10d 010f 	add.w	r1, sp, #15
    3cfe:	f003 f83f 	bl	6d80 <nrf_gpio_reconfigure>
        m_cb.pin_flags[pin] |= PIN_FLAG_IN_USE | PIN_FLAG_OUTPUT;
    3d02:	f836 3017 	ldrh.w	r3, [r6, r7, lsl #1]
    3d06:	f043 0303 	orr.w	r3, r3, #3
    3d0a:	f826 3017 	strh.w	r3, [r6, r7, lsl #1]
    if (p_task_config)
    3d0e:	b915      	cbnz	r5, 3d16 <nrfx_gpiote_output_configure+0x5a>
    return NRFX_SUCCESS;
    3d10:	4821      	ldr	r0, [pc, #132]	; (3d98 <nrfx_gpiote_output_configure+0xdc>)
}
    3d12:	b005      	add	sp, #20
    3d14:	bdf0      	pop	{r4, r5, r6, r7, pc}
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    3d16:	4e1f      	ldr	r6, [pc, #124]	; (3d94 <nrfx_gpiote_output_configure+0xd8>)
    3d18:	f104 0708 	add.w	r7, r4, #8
    3d1c:	f836 0017 	ldrh.w	r0, [r6, r7, lsl #1]
        if (pin_is_input(pin))
    3d20:	0783      	lsls	r3, r0, #30
    3d22:	d534      	bpl.n	3d8e <nrfx_gpiote_output_configure+0xd2>
        uint32_t ch = p_task_config->task_ch;
    3d24:	f895 c000 	ldrb.w	ip, [r5]
    p_reg->CONFIG[idx] = 0;
    3d28:	4661      	mov	r1, ip
    3d2a:	0089      	lsls	r1, r1, #2
        m_cb.pin_flags[pin] &= ~(PIN_FLAG_TE_USED | PIN_TE_ID_MASK);
    3d2c:	f020 0020 	bic.w	r0, r0, #32
    3d30:	f101 4180 	add.w	r1, r1, #1073741824	; 0x40000000
    3d34:	04c0      	lsls	r0, r0, #19
    3d36:	f501 41c0 	add.w	r1, r1, #24576	; 0x6000
    3d3a:	0cc0      	lsrs	r0, r0, #19
    3d3c:	f826 0017 	strh.w	r0, [r6, r7, lsl #1]
    3d40:	2300      	movs	r3, #0
    3d42:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
        if (p_task_config->polarity != NRF_GPIOTE_POLARITY_NONE)
    3d46:	786a      	ldrb	r2, [r5, #1]
    3d48:	2a00      	cmp	r2, #0
    3d4a:	d0e1      	beq.n	3d10 <nrfx_gpiote_output_configure+0x54>
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk |
    3d4c:	f8d1 3510 	ldr.w	r3, [r1, #1296]	; 0x510
                                      p_task_config->init_val);
    3d50:	78ad      	ldrb	r5, [r5, #2]
    3d52:	f423 1399 	bic.w	r3, r3, #1253376	; 0x132000
    3d56:	f423 53f8 	bic.w	r3, r3, #7936	; 0x1f00
    3d5a:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    3d5e:	f8d1 e510 	ldr.w	lr, [r1, #1296]	; 0x510
    3d62:	0223      	lsls	r3, r4, #8
    3d64:	f403 537c 	and.w	r3, r3, #16128	; 0x3f00
                        ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk) |
    3d68:	0412      	lsls	r2, r2, #16
    3d6a:	f402 3240 	and.w	r2, r2, #196608	; 0x30000
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    3d6e:	ea43 030e 	orr.w	r3, r3, lr
    3d72:	4313      	orrs	r3, r2
                        ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
    3d74:	052a      	lsls	r2, r5, #20
    3d76:	f402 1280 	and.w	r2, r2, #1048576	; 0x100000
            m_cb.pin_flags[pin] |= PIN_FLAG_TE_ID(ch);
    3d7a:	ea40 304c 	orr.w	r0, r0, ip, lsl #13
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    3d7e:	4313      	orrs	r3, r2
    3d80:	f040 0020 	orr.w	r0, r0, #32
    3d84:	f826 0017 	strh.w	r0, [r6, r7, lsl #1]
    3d88:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
    3d8c:	e7c0      	b.n	3d10 <nrfx_gpiote_output_configure+0x54>
{
    3d8e:	4803      	ldr	r0, [pc, #12]	; (3d9c <nrfx_gpiote_output_configure+0xe0>)
    3d90:	e7bf      	b.n	3d12 <nrfx_gpiote_output_configure+0x56>
    3d92:	bf00      	nop
    3d94:	20000050 	.word	0x20000050
    3d98:	0bad0000 	.word	0x0bad0000
    3d9c:	0bad0004 	.word	0x0bad0004

00003da0 <nrfx_gpiote_global_callback_set>:
    m_cb.global_handler.handler = handler;
    3da0:	4b01      	ldr	r3, [pc, #4]	; (3da8 <nrfx_gpiote_global_callback_set+0x8>)
    m_cb.global_handler.p_context = p_context;
    3da2:	e9c3 0102 	strd	r0, r1, [r3, #8]
}
    3da6:	4770      	bx	lr
    3da8:	20000050 	.word	0x20000050

00003dac <nrfx_gpiote_channel_get>:
{
    3dac:	b508      	push	{r3, lr}
    3dae:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin))
    3db0:	f7ff fe66 	bl	3a80 <pin_in_use_by_te>
    3db4:	b138      	cbz	r0, 3dc6 <nrfx_gpiote_channel_get+0x1a>
        *p_channel = PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    3db6:	4b05      	ldr	r3, [pc, #20]	; (3dcc <nrfx_gpiote_channel_get+0x20>)
        return NRFX_SUCCESS;
    3db8:	4805      	ldr	r0, [pc, #20]	; (3dd0 <nrfx_gpiote_channel_get+0x24>)
        *p_channel = PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    3dba:	3208      	adds	r2, #8
    3dbc:	f833 3012 	ldrh.w	r3, [r3, r2, lsl #1]
    3dc0:	0b5b      	lsrs	r3, r3, #13
    3dc2:	700b      	strb	r3, [r1, #0]
}
    3dc4:	bd08      	pop	{r3, pc}
        return NRFX_ERROR_INVALID_PARAM;
    3dc6:	4803      	ldr	r0, [pc, #12]	; (3dd4 <nrfx_gpiote_channel_get+0x28>)
    3dc8:	e7fc      	b.n	3dc4 <nrfx_gpiote_channel_get+0x18>
    3dca:	bf00      	nop
    3dcc:	20000050 	.word	0x20000050
    3dd0:	0bad0000 	.word	0x0bad0000
    3dd4:	0bad0004 	.word	0x0bad0004

00003dd8 <nrfx_gpiote_init>:
{
    3dd8:	b538      	push	{r3, r4, r5, lr}
    if (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED)
    3dda:	4c0f      	ldr	r4, [pc, #60]	; (3e18 <nrfx_gpiote_init+0x40>)
    3ddc:	f894 5078 	ldrb.w	r5, [r4, #120]	; 0x78
    3de0:	b9bd      	cbnz	r5, 3e12 <nrfx_gpiote_init+0x3a>
    memset(m_cb.pin_flags, 0, sizeof(m_cb.pin_flags));
    3de2:	2260      	movs	r2, #96	; 0x60
    3de4:	4629      	mov	r1, r5
    3de6:	f104 0010 	add.w	r0, r4, #16
    3dea:	f002 fc7e 	bl	66ea <memset>
    NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_GPIOTE));
    3dee:	2006      	movs	r0, #6
    3df0:	f7fd fea6 	bl	1b40 <arch_irq_enable>
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    3df4:	4b09      	ldr	r3, [pc, #36]	; (3e1c <nrfx_gpiote_init+0x44>)
    return err_code;
    3df6:	480a      	ldr	r0, [pc, #40]	; (3e20 <nrfx_gpiote_init+0x48>)
    3df8:	f8c3 517c 	str.w	r5, [r3, #380]	; 0x17c
    3dfc:	f8d3 217c 	ldr.w	r2, [r3, #380]	; 0x17c
    p_reg->INTENSET = mask;
    3e00:	f04f 4200 	mov.w	r2, #2147483648	; 0x80000000
    3e04:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    m_cb.state = NRFX_DRV_STATE_INITIALIZED;
    3e08:	2301      	movs	r3, #1
    3e0a:	f884 3078 	strb.w	r3, [r4, #120]	; 0x78
    m_cb.available_evt_handlers = NRFX_BIT_MASK(NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS);
    3e0e:	6763      	str	r3, [r4, #116]	; 0x74
}
    3e10:	bd38      	pop	{r3, r4, r5, pc}
        return err_code;
    3e12:	4804      	ldr	r0, [pc, #16]	; (3e24 <nrfx_gpiote_init+0x4c>)
    3e14:	e7fc      	b.n	3e10 <nrfx_gpiote_init+0x38>
    3e16:	bf00      	nop
    3e18:	20000050 	.word	0x20000050
    3e1c:	40006000 	.word	0x40006000
    3e20:	0bad0000 	.word	0x0bad0000
    3e24:	0bad0005 	.word	0x0bad0005

00003e28 <nrfx_gpiote_is_init>:
    return (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED) ? true : false;
    3e28:	4b03      	ldr	r3, [pc, #12]	; (3e38 <nrfx_gpiote_is_init+0x10>)
    3e2a:	f893 0078 	ldrb.w	r0, [r3, #120]	; 0x78
}
    3e2e:	3800      	subs	r0, #0
    3e30:	bf18      	it	ne
    3e32:	2001      	movne	r0, #1
    3e34:	4770      	bx	lr
    3e36:	bf00      	nop
    3e38:	20000050 	.word	0x20000050

00003e3c <nrfx_gpiote_channel_free>:
{
    3e3c:	4601      	mov	r1, r0
    return nrfx_flag32_free(&m_cb.available_channels_mask, channel);
    3e3e:	4801      	ldr	r0, [pc, #4]	; (3e44 <nrfx_gpiote_channel_free+0x8>)
    3e40:	f7ff bd48 	b.w	38d4 <nrfx_flag32_free>
    3e44:	200000c0 	.word	0x200000c0

00003e48 <nrfx_gpiote_channel_alloc>:
{
    3e48:	4601      	mov	r1, r0
    return nrfx_flag32_alloc(&m_cb.available_channels_mask, p_channel);
    3e4a:	4801      	ldr	r0, [pc, #4]	; (3e50 <nrfx_gpiote_channel_alloc+0x8>)
    3e4c:	f7ff bd22 	b.w	3894 <nrfx_flag32_alloc>
    3e50:	200000c0 	.word	0x200000c0

00003e54 <nrfx_gpiote_trigger_enable>:
{
    3e54:	b537      	push	{r0, r1, r2, r4, r5, lr}
    3e56:	4604      	mov	r4, r0
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    3e58:	f7ff fe12 	bl	3a80 <pin_in_use_by_te>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    3e5c:	f104 0208 	add.w	r2, r4, #8
    3e60:	4b1e      	ldr	r3, [pc, #120]	; (3edc <nrfx_gpiote_trigger_enable+0x88>)
    3e62:	f833 3012 	ldrh.w	r3, [r3, r2, lsl #1]
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    3e66:	b1e8      	cbz	r0, 3ea4 <nrfx_gpiote_trigger_enable+0x50>
    3e68:	f013 0502 	ands.w	r5, r3, #2
    3e6c:	d11a      	bne.n	3ea4 <nrfx_gpiote_trigger_enable+0x50>
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    3e6e:	0b5b      	lsrs	r3, r3, #13
#endif

NRF_STATIC_INLINE nrf_gpiote_event_t nrf_gpiote_in_event_get(uint8_t index)
{
    NRFX_ASSERT(index < GPIOTE_CH_NUM);
    return (nrf_gpiote_event_t)NRFX_OFFSETOF(NRF_GPIOTE_Type, EVENTS_IN[index]);
    3e70:	009a      	lsls	r2, r3, #2
    return ((uint32_t)p_reg + event);
    3e72:	f102 4080 	add.w	r0, r2, #1073741824	; 0x40000000
    3e76:	f500 40c2 	add.w	r0, r0, #24832	; 0x6100
    3e7a:	f102 4280 	add.w	r2, r2, #1073741824	; 0x40000000
    3e7e:	f502 42c0 	add.w	r2, r2, #24576	; 0x6000
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    3e82:	6005      	str	r5, [r0, #0]
    3e84:	6800      	ldr	r0, [r0, #0]
   p_reg->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event;
    3e86:	f8d2 0510 	ldr.w	r0, [r2, #1296]	; 0x510
    3e8a:	f040 0001 	orr.w	r0, r0, #1
    3e8e:	f8c2 0510 	str.w	r0, [r2, #1296]	; 0x510
        if (int_enable)
    3e92:	b129      	cbz	r1, 3ea0 <nrfx_gpiote_trigger_enable+0x4c>
            nrf_gpiote_int_enable(NRF_GPIOTE, NRFX_BIT(ch));
    3e94:	2201      	movs	r2, #1
    3e96:	fa02 f303 	lsl.w	r3, r2, r3
    p_reg->INTENSET = mask;
    3e9a:	4a11      	ldr	r2, [pc, #68]	; (3ee0 <nrfx_gpiote_trigger_enable+0x8c>)
    3e9c:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
}
    3ea0:	b003      	add	sp, #12
    3ea2:	bd30      	pop	{r4, r5, pc}
    nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    3ea4:	f3c3 0382 	ubfx	r3, r3, #2, #3
    if (trigger == NRFX_GPIOTE_TRIGGER_LOW)
    3ea8:	2b04      	cmp	r3, #4
    3eaa:	d012      	beq.n	3ed2 <nrfx_gpiote_trigger_enable+0x7e>
    else if (trigger == NRFX_GPIOTE_TRIGGER_HIGH)
    3eac:	2b05      	cmp	r3, #5
    3eae:	d012      	beq.n	3ed6 <nrfx_gpiote_trigger_enable+0x82>
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    3eb0:	a801      	add	r0, sp, #4
    3eb2:	9401      	str	r4, [sp, #4]
    3eb4:	f7ff fdd6 	bl	3a64 <nrf_gpio_pin_port_decode>
    return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL);
    3eb8:	9b01      	ldr	r3, [sp, #4]
    return p_reg->IN;
    3eba:	f8d0 1510 	ldr.w	r1, [r0, #1296]	; 0x510
    return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL);
    3ebe:	40d9      	lsrs	r1, r3
    3ec0:	f001 0101 	and.w	r1, r1, #1
    3ec4:	3102      	adds	r1, #2
        nrf_gpio_cfg_sense_set(pin, get_initial_sense(pin));
    3ec6:	4620      	mov	r0, r4
}
    3ec8:	b003      	add	sp, #12
    3eca:	e8bd 4030 	ldmia.w	sp!, {r4, r5, lr}
        nrf_gpio_cfg_sense_set(pin, get_initial_sense(pin));
    3ece:	f002 bfa0 	b.w	6e12 <nrf_gpio_cfg_sense_set>
        sense = NRF_GPIO_PIN_SENSE_LOW;
    3ed2:	2103      	movs	r1, #3
    3ed4:	e7f7      	b.n	3ec6 <nrfx_gpiote_trigger_enable+0x72>
        sense = NRF_GPIO_PIN_SENSE_HIGH;
    3ed6:	2102      	movs	r1, #2
    3ed8:	e7f5      	b.n	3ec6 <nrfx_gpiote_trigger_enable+0x72>
    3eda:	bf00      	nop
    3edc:	20000050 	.word	0x20000050
    3ee0:	40006000 	.word	0x40006000

00003ee4 <nrfx_gpiote_trigger_disable>:
{
    3ee4:	b508      	push	{r3, lr}
    3ee6:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    3ee8:	f7ff fdca 	bl	3a80 <pin_in_use_by_te>
    3eec:	b1c0      	cbz	r0, 3f20 <nrfx_gpiote_trigger_disable+0x3c>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    3eee:	f102 0108 	add.w	r1, r2, #8
    3ef2:	4b0e      	ldr	r3, [pc, #56]	; (3f2c <nrfx_gpiote_trigger_disable+0x48>)
    3ef4:	f833 3011 	ldrh.w	r3, [r3, r1, lsl #1]
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    3ef8:	0799      	lsls	r1, r3, #30
    3efa:	d411      	bmi.n	3f20 <nrfx_gpiote_trigger_disable+0x3c>
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    3efc:	0b5b      	lsrs	r3, r3, #13
        nrf_gpiote_int_disable(NRF_GPIOTE, NRFX_BIT(ch));
    3efe:	2201      	movs	r2, #1
    3f00:	409a      	lsls	r2, r3
    p_reg->INTENCLR = mask;
    3f02:	009b      	lsls	r3, r3, #2
    3f04:	490a      	ldr	r1, [pc, #40]	; (3f30 <nrfx_gpiote_trigger_disable+0x4c>)
    3f06:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    3f0a:	f503 43c0 	add.w	r3, r3, #24576	; 0x6000
    3f0e:	f8c1 2308 	str.w	r2, [r1, #776]	; 0x308
   p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk;
    3f12:	f8d3 2510 	ldr.w	r2, [r3, #1296]	; 0x510
    3f16:	f022 0203 	bic.w	r2, r2, #3
    3f1a:	f8c3 2510 	str.w	r2, [r3, #1296]	; 0x510
}
    3f1e:	bd08      	pop	{r3, pc}
    3f20:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
        nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE);
    3f24:	2100      	movs	r1, #0
    3f26:	4610      	mov	r0, r2
    3f28:	f002 bf73 	b.w	6e12 <nrf_gpio_cfg_sense_set>
    3f2c:	20000050 	.word	0x20000050
    3f30:	40006000 	.word	0x40006000

00003f34 <nrfx_gpiote_pin_uninit>:
{
    3f34:	b513      	push	{r0, r1, r4, lr}
    return m_cb.pin_flags[pin] & PIN_FLAG_IN_USE;
    3f36:	4b0e      	ldr	r3, [pc, #56]	; (3f70 <nrfx_gpiote_pin_uninit+0x3c>)
    3f38:	f100 0208 	add.w	r2, r0, #8
{
    3f3c:	4604      	mov	r4, r0
    return m_cb.pin_flags[pin] & PIN_FLAG_IN_USE;
    3f3e:	f833 3012 	ldrh.w	r3, [r3, r2, lsl #1]
    if (!pin_in_use(pin))
    3f42:	07db      	lsls	r3, r3, #31
    3f44:	d511      	bpl.n	3f6a <nrfx_gpiote_pin_uninit+0x36>
    nrfx_gpiote_trigger_disable(pin);
    3f46:	f7ff ffcd 	bl	3ee4 <nrfx_gpiote_trigger_disable>
    pin_handler_trigger_uninit(pin);
    3f4a:	4620      	mov	r0, r4
    3f4c:	f7ff fdec 	bl	3b28 <pin_handler_trigger_uninit>
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    3f50:	a801      	add	r0, sp, #4
    3f52:	9401      	str	r4, [sp, #4]
    3f54:	f7ff fd86 	bl	3a64 <nrf_gpio_pin_port_decode>
    reg->PIN_CNF[pin_number] = cnf;
    3f58:	9b01      	ldr	r3, [sp, #4]
    3f5a:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    3f5e:	2202      	movs	r2, #2
    3f60:	f840 2023 	str.w	r2, [r0, r3, lsl #2]
    nrf_gpio_cfg(
    3f64:	4803      	ldr	r0, [pc, #12]	; (3f74 <nrfx_gpiote_pin_uninit+0x40>)
}
    3f66:	b002      	add	sp, #8
    3f68:	bd10      	pop	{r4, pc}
        return NRFX_ERROR_INVALID_PARAM;
    3f6a:	4803      	ldr	r0, [pc, #12]	; (3f78 <nrfx_gpiote_pin_uninit+0x44>)
    3f6c:	e7fb      	b.n	3f66 <nrfx_gpiote_pin_uninit+0x32>
    3f6e:	bf00      	nop
    3f70:	20000050 	.word	0x20000050
    3f74:	0bad0000 	.word	0x0bad0000
    3f78:	0bad0004 	.word	0x0bad0004

00003f7c <nrfx_gpiote_irq_handler>:
        call_handler(pin, gpiote_polarity_to_trigger(polarity));
    }
}

void nrfx_gpiote_irq_handler(void)
{
    3f7c:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    3f80:	4b68      	ldr	r3, [pc, #416]	; (4124 <nrfx_gpiote_irq_handler+0x1a8>)
    return p_reg->INTENSET & mask;
    3f82:	4869      	ldr	r0, [pc, #420]	; (4128 <nrfx_gpiote_irq_handler+0x1ac>)
    uint32_t i;
    nrf_gpiote_event_t event = NRF_GPIOTE_EVENT_IN_0;
    uint32_t mask = (uint32_t)NRF_GPIOTE_INT_IN0_MASK;

    /* collect status of all GPIOTE pin events. Processing is done once all are collected and cleared.*/
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    3f84:	4969      	ldr	r1, [pc, #420]	; (412c <nrfx_gpiote_irq_handler+0x1b0>)
    uint32_t status = 0;
    3f86:	2600      	movs	r6, #0
{
    3f88:	b087      	sub	sp, #28
    uint32_t mask = (uint32_t)NRF_GPIOTE_INT_IN0_MASK;
    3f8a:	2201      	movs	r2, #1
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    3f8c:	4634      	mov	r4, r6
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    3f8e:	681d      	ldr	r5, [r3, #0]
    {
        if (nrf_gpiote_event_check(NRF_GPIOTE, event) &&
    3f90:	b135      	cbz	r5, 3fa0 <nrfx_gpiote_irq_handler+0x24>
    return p_reg->INTENSET & mask;
    3f92:	f8d0 5304 	ldr.w	r5, [r0, #772]	; 0x304
    3f96:	4215      	tst	r5, r2
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    3f98:	bf1e      	ittt	ne
    3f9a:	601c      	strne	r4, [r3, #0]
    3f9c:	681d      	ldrne	r5, [r3, #0]
            nrf_gpiote_int_enable_check(NRF_GPIOTE, mask))
        {
            nrf_gpiote_event_clear(NRF_GPIOTE, event);
            status |= mask;
    3f9e:	4316      	orrne	r6, r2
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    3fa0:	3304      	adds	r3, #4
    3fa2:	428b      	cmp	r3, r1
        }
        mask <<= 1;
    3fa4:	ea4f 0242 	mov.w	r2, r2, lsl #1
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    3fa8:	d1f1      	bne.n	3f8e <nrfx_gpiote_irq_handler+0x12>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    3faa:	f8df 917c 	ldr.w	r9, [pc, #380]	; 4128 <nrfx_gpiote_irq_handler+0x1ac>
    3fae:	f8d9 317c 	ldr.w	r3, [r9, #380]	; 0x17c
         * in ascending order. */
        event = (nrf_gpiote_event_t)((uint32_t)event + sizeof(uint32_t));
    }

    /* handle PORT event */
    if (nrf_gpiote_event_check(NRF_GPIOTE, NRF_GPIOTE_EVENT_PORT))
    3fb2:	2b00      	cmp	r3, #0
    3fb4:	f000 8099 	beq.w	40ea <nrfx_gpiote_irq_handler+0x16e>
        *p_masks = gpio_regs[i]->LATCH;
    3fb8:	f04f 43a0 	mov.w	r3, #1342177280	; 0x50000000
    3fbc:	f8d3 2520 	ldr.w	r2, [r3, #1312]	; 0x520
    3fc0:	9204      	str	r2, [sp, #16]
        gpio_regs[i]->LATCH = *p_masks;
    3fc2:	f8c3 2520 	str.w	r2, [r3, #1312]	; 0x520
        *p_masks = gpio_regs[i]->LATCH;
    3fc6:	f8d3 2820 	ldr.w	r2, [r3, #2080]	; 0x820
    3fca:	9205      	str	r2, [sp, #20]
        gpio_regs[i]->LATCH = *p_masks;
    3fcc:	f8c3 2820 	str.w	r2, [r3, #2080]	; 0x820
        for (uint32_t i = 0; i < GPIO_COUNT; i++)
    3fd0:	f04f 0800 	mov.w	r8, #0
            while (latch[i])
    3fd4:	f10d 0a10 	add.w	sl, sp, #16
    3fd8:	ea4f 1348 	mov.w	r3, r8, lsl #5
    3fdc:	9300      	str	r3, [sp, #0]
__STATIC_INLINE void nrf_bitmask_bit_clear(uint32_t bit, void * p_mask)
{
    uint8_t * p_mask8 = (uint8_t *)p_mask;
    uint32_t byte_idx = BITMASK_BYTE_GET(bit);
    bit = BITMASK_RELBIT_GET(bit);
    p_mask8[byte_idx] &= ~(1 << bit);
    3fde:	f04f 0b01 	mov.w	fp, #1
    3fe2:	e049      	b.n	4078 <nrfx_gpiote_irq_handler+0xfc>
                pin += 32 * i;
    3fe4:	9b00      	ldr	r3, [sp, #0]
                nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    3fe6:	4a52      	ldr	r2, [pc, #328]	; (4130 <nrfx_gpiote_irq_handler+0x1b4>)
                uint32_t pin = NRF_CTZ(latch[i]);
    3fe8:	fa94 f4a4 	rbit	r4, r4
    3fec:	fab4 f484 	clz	r4, r4
                pin += 32 * i;
    3ff0:	441c      	add	r4, r3
    uint32_t byte_idx = BITMASK_BYTE_GET(bit);
    3ff2:	08e0      	lsrs	r0, r4, #3
                nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    3ff4:	f104 0308 	add.w	r3, r4, #8
    3ff8:	9403      	str	r4, [sp, #12]
    3ffa:	f832 7013 	ldrh.w	r7, [r2, r3, lsl #1]
    p_mask8[byte_idx] &= ~(1 << bit);
    3ffe:	f81a 3000 	ldrb.w	r3, [sl, r0]
    bit = BITMASK_RELBIT_GET(bit);
    4002:	f004 0207 	and.w	r2, r4, #7
    p_mask8[byte_idx] &= ~(1 << bit);
    4006:	fa0b f202 	lsl.w	r2, fp, r2
    400a:	ea23 0302 	bic.w	r3, r3, r2
    400e:	f80a 3000 	strb.w	r3, [sl, r0]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    4012:	a803      	add	r0, sp, #12
    4014:	f7ff fd26 	bl	3a64 <nrf_gpio_pin_port_decode>
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    4018:	9b03      	ldr	r3, [sp, #12]
    401a:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    401e:	08b9      	lsrs	r1, r7, #2
    4020:	f850 3023 	ldr.w	r3, [r0, r3, lsl #2]
    4024:	f3c7 0582 	ubfx	r5, r7, #2, #3
    if (is_level(trigger))
    4028:	074a      	lsls	r2, r1, #29
                nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    402a:	462f      	mov	r7, r5
                                   GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos);
    402c:	f3c3 4301 	ubfx	r3, r3, #16, #2
    if (is_level(trigger))
    4030:	d52c      	bpl.n	408c <nrfx_gpiote_irq_handler+0x110>
        call_handler(pin, trigger);
    4032:	4620      	mov	r0, r4
    4034:	4639      	mov	r1, r7
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    4036:	b2dd      	uxtb	r5, r3
    4038:	f7ff fd2c 	bl	3a94 <call_handler>
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    403c:	a803      	add	r0, sp, #12
    403e:	9403      	str	r4, [sp, #12]
    4040:	f7ff fd10 	bl	3a64 <nrf_gpio_pin_port_decode>
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    4044:	9b03      	ldr	r3, [sp, #12]
    4046:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    404a:	f850 3023 	ldr.w	r3, [r0, r3, lsl #2]
        if (nrf_gpio_pin_sense_get(pin) == sense)
    404e:	f3c3 4301 	ubfx	r3, r3, #16, #2
    4052:	429d      	cmp	r5, r3
    4054:	d107      	bne.n	4066 <nrfx_gpiote_irq_handler+0xea>
            nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE);
    4056:	2100      	movs	r1, #0
    4058:	4620      	mov	r0, r4
    405a:	f002 feda 	bl	6e12 <nrf_gpio_cfg_sense_set>
            nrf_gpio_cfg_sense_set(pin, sense);
    405e:	4629      	mov	r1, r5
    4060:	4620      	mov	r0, r4
    4062:	f002 fed6 	bl	6e12 <nrf_gpio_cfg_sense_set>
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    4066:	a803      	add	r0, sp, #12
    4068:	9403      	str	r4, [sp, #12]
    406a:	f7ff fcfb 	bl	3a64 <nrf_gpio_pin_port_decode>
    reg->LATCH = (1 << pin_number);
    406e:	9b03      	ldr	r3, [sp, #12]
    4070:	fa0b f303 	lsl.w	r3, fp, r3
    4074:	f8c0 3520 	str.w	r3, [r0, #1312]	; 0x520
            while (latch[i])
    4078:	f85a 4028 	ldr.w	r4, [sl, r8, lsl #2]
    407c:	2c00      	cmp	r4, #0
    407e:	d1b1      	bne.n	3fe4 <nrfx_gpiote_irq_handler+0x68>
        for (uint32_t i = 0; i < GPIO_COUNT; i++)
    4080:	f1b8 0f00 	cmp.w	r8, #0
    4084:	d11d      	bne.n	40c2 <nrfx_gpiote_irq_handler+0x146>
    4086:	f04f 0801 	mov.w	r8, #1
    408a:	e7a5      	b.n	3fd8 <nrfx_gpiote_irq_handler+0x5c>
                NRF_GPIO_PIN_SENSE_LOW : NRF_GPIO_PIN_SENSE_HIGH;
    408c:	2b02      	cmp	r3, #2
    408e:	d10c      	bne.n	40aa <nrfx_gpiote_irq_handler+0x12e>
        nrf_gpio_cfg_sense_set(pin, next_sense);
    4090:	2103      	movs	r1, #3
    4092:	4620      	mov	r0, r4
    4094:	f002 febd 	bl	6e12 <nrf_gpio_cfg_sense_set>
        if ((trigger == NRFX_GPIOTE_TRIGGER_TOGGLE) ||
    4098:	f005 0305 	and.w	r3, r5, #5
    409c:	2b01      	cmp	r3, #1
    409e:	d1e2      	bne.n	4066 <nrfx_gpiote_irq_handler+0xea>
            call_handler(pin, trigger);
    40a0:	4639      	mov	r1, r7
    40a2:	4620      	mov	r0, r4
    40a4:	f7ff fcf6 	bl	3a94 <call_handler>
    40a8:	e7dd      	b.n	4066 <nrfx_gpiote_irq_handler+0xea>
        nrf_gpio_cfg_sense_set(pin, next_sense);
    40aa:	2102      	movs	r1, #2
    40ac:	4620      	mov	r0, r4
    40ae:	9301      	str	r3, [sp, #4]
    40b0:	f002 feaf 	bl	6e12 <nrf_gpio_cfg_sense_set>
        if ((trigger == NRFX_GPIOTE_TRIGGER_TOGGLE) ||
    40b4:	2d03      	cmp	r5, #3
    40b6:	d0f3      	beq.n	40a0 <nrfx_gpiote_irq_handler+0x124>
            (sense == NRF_GPIO_PIN_SENSE_HIGH && trigger == NRFX_GPIOTE_TRIGGER_LOTOHI) ||
    40b8:	9b01      	ldr	r3, [sp, #4]
    40ba:	2b03      	cmp	r3, #3
    40bc:	d1d3      	bne.n	4066 <nrfx_gpiote_irq_handler+0xea>
            (sense == NRF_GPIO_PIN_SENSE_LOW && trigger == NRFX_GPIOTE_TRIGGER_HITOLO))
    40be:	2d02      	cmp	r5, #2
    40c0:	e7ed      	b.n	409e <nrfx_gpiote_irq_handler+0x122>
        *p_masks = gpio_regs[i]->LATCH;
    40c2:	f04f 42a0 	mov.w	r2, #1342177280	; 0x50000000
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    40c6:	f8c9 417c 	str.w	r4, [r9, #380]	; 0x17c
    40ca:	f8d9 317c 	ldr.w	r3, [r9, #380]	; 0x17c
    40ce:	4919      	ldr	r1, [pc, #100]	; (4134 <nrfx_gpiote_irq_handler+0x1b8>)
    40d0:	f8d2 3520 	ldr.w	r3, [r2, #1312]	; 0x520
    40d4:	9304      	str	r3, [sp, #16]
        gpio_regs[i]->LATCH = *p_masks;
    40d6:	f8c2 3520 	str.w	r3, [r2, #1312]	; 0x520
        *p_masks = gpio_regs[i]->LATCH;
    40da:	f8d1 2520 	ldr.w	r2, [r1, #1312]	; 0x520
    40de:	9205      	str	r2, [sp, #20]
        if (latch[port_idx])
    40e0:	4313      	orrs	r3, r2
        gpio_regs[i]->LATCH = *p_masks;
    40e2:	f8c1 2520 	str.w	r2, [r1, #1312]	; 0x520
    40e6:	f47f af73 	bne.w	3fd0 <nrfx_gpiote_irq_handler+0x54>
        mask &= ~NRFX_BIT(ch);
    40ea:	2401      	movs	r4, #1
    while (mask)
    40ec:	b916      	cbnz	r6, 40f4 <nrfx_gpiote_irq_handler+0x178>
        port_event_handle();
    }

    /* Process pin events. */
    gpiote_evt_handle(status);
}
    40ee:	b007      	add	sp, #28
    40f0:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
        uint32_t ch = NRF_CTZ(mask);
    40f4:	fa96 f3a6 	rbit	r3, r6
    40f8:	fab3 f383 	clz	r3, r3
        mask &= ~NRFX_BIT(ch);
    40fc:	fa04 f203 	lsl.w	r2, r4, r3
    4100:	009b      	lsls	r3, r3, #2
    4102:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    4106:	f503 43c0 	add.w	r3, r3, #24576	; 0x6000
    410a:	ea26 0602 	bic.w	r6, r6, r2
    return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
    410e:	f8d3 0510 	ldr.w	r0, [r3, #1296]	; 0x510
    return (nrf_gpiote_polarity_t)((p_reg->CONFIG[idx] & GPIOTE_CONFIG_POLARITY_Msk) >>
    4112:	f8d3 1510 	ldr.w	r1, [r3, #1296]	; 0x510
        call_handler(pin, gpiote_polarity_to_trigger(polarity));
    4116:	f3c0 2005 	ubfx	r0, r0, #8, #6
    411a:	f3c1 4101 	ubfx	r1, r1, #16, #2
    411e:	f7ff fcb9 	bl	3a94 <call_handler>
    4122:	e7e3      	b.n	40ec <nrfx_gpiote_irq_handler+0x170>
    4124:	40006100 	.word	0x40006100
    4128:	40006000 	.word	0x40006000
    412c:	40006120 	.word	0x40006120
    4130:	20000050 	.word	0x20000050
    4134:	50000300 	.word	0x50000300

00004138 <nvmc_word_write>:
    4138:	4a04      	ldr	r2, [pc, #16]	; (414c <nvmc_word_write+0x14>)
    413a:	f8d2 3400 	ldr.w	r3, [r2, #1024]	; 0x400
{
#if defined(NRF9160_XXAA)
    while (!nrf_nvmc_write_ready_check(NRF_NVMC))
    {}
#else
    while (!nrf_nvmc_ready_check(NRF_NVMC))
    413e:	07db      	lsls	r3, r3, #31
    4140:	d5fb      	bpl.n	413a <nvmc_word_write+0x2>
    {}
#endif

    *(volatile uint32_t *)addr = value;
    4142:	6001      	str	r1, [r0, #0]
  __ASM volatile ("dmb 0xF":::"memory");
    4144:	f3bf 8f5f 	dmb	sy
    __DMB();
}
    4148:	4770      	bx	lr
    414a:	bf00      	nop
    414c:	4001e000 	.word	0x4001e000

00004150 <nrfx_nvmc_page_erase>:
NRF_STATIC_INLINE uint32_t nrf_ficr_codepagesize_get(NRF_FICR_Type const * p_reg)
{
#if defined(FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Msk)
    return p_reg->INFO.CODEPAGESIZE;
#else
    return p_reg->CODEPAGESIZE;
    4150:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    4154:	691a      	ldr	r2, [r3, #16]
    return !(addr % flash_page_size_get());
    4156:	fbb0 f3f2 	udiv	r3, r0, r2
    415a:	fb02 0313 	mls	r3, r2, r3, r0

nrfx_err_t nrfx_nvmc_page_erase(uint32_t addr)
{
    NRFX_ASSERT(is_valid_address(addr, false));

    if (!is_page_aligned_check(addr))
    415e:	b973      	cbnz	r3, 417e <nrfx_nvmc_page_erase+0x2e>
#endif

NRF_STATIC_INLINE void nrf_nvmc_mode_set(NRF_NVMC_Type * p_reg,
                                         nrf_nvmc_mode_t mode)
{
    p_reg->CONFIG = (uint32_t)mode;
    4160:	4b08      	ldr	r3, [pc, #32]	; (4184 <nrfx_nvmc_page_erase+0x34>)
    4162:	2202      	movs	r2, #2
    4164:	f8c3 2504 	str.w	r2, [r3, #1284]	; 0x504
    else
    {
        p_reg->ERASEPCR1 = page_addr;
    }
#elif defined(NRF52_SERIES)
    p_reg->ERASEPAGE = page_addr;
    4168:	f8c3 0508 	str.w	r0, [r3, #1288]	; 0x508
    return (bool)(p_reg->READY & NVMC_READY_READY_Msk);
    416c:	f8d3 2400 	ldr.w	r2, [r3, #1024]	; 0x400
        return NRFX_ERROR_INVALID_ADDR;
    }

    nvmc_erase_mode_set();
    nrf_nvmc_page_erase_start(NRF_NVMC, addr);
    while (!nrf_nvmc_ready_check(NRF_NVMC))
    4170:	07d2      	lsls	r2, r2, #31
    4172:	d5fb      	bpl.n	416c <nrfx_nvmc_page_erase+0x1c>
    p_reg->CONFIG = (uint32_t)mode;
    4174:	2200      	movs	r2, #0
    {}
    nvmc_readonly_mode_set();

    return NRFX_SUCCESS;
    4176:	4804      	ldr	r0, [pc, #16]	; (4188 <nrfx_nvmc_page_erase+0x38>)
    4178:	f8c3 2504 	str.w	r2, [r3, #1284]	; 0x504
    417c:	4770      	bx	lr
        return NRFX_ERROR_INVALID_ADDR;
    417e:	4803      	ldr	r0, [pc, #12]	; (418c <nrfx_nvmc_page_erase+0x3c>)
}
    4180:	4770      	bx	lr
    4182:	bf00      	nop
    4184:	4001e000 	.word	0x4001e000
    4188:	0bad0000 	.word	0x0bad0000
    418c:	0bad000a 	.word	0x0bad000a

00004190 <nrfx_nvmc_word_write>:

    nrfx_nvmc_word_write(aligned_addr, partial_word_create(addr, (const uint8_t *)&value, 2));
}

void nrfx_nvmc_word_write(uint32_t addr, uint32_t value)
{
    4190:	b510      	push	{r4, lr}
    4192:	4c05      	ldr	r4, [pc, #20]	; (41a8 <nrfx_nvmc_word_write+0x18>)
    4194:	2301      	movs	r3, #1
    4196:	f8c4 3504 	str.w	r3, [r4, #1284]	; 0x504
    NRFX_ASSERT(is_valid_address(addr, true));
    NRFX_ASSERT(nrfx_is_word_aligned((void const *)addr));

    nvmc_write_mode_set();

    nvmc_word_write(addr, value);
    419a:	f7ff ffcd 	bl	4138 <nvmc_word_write>
    419e:	2300      	movs	r3, #0
    41a0:	f8c4 3504 	str.w	r3, [r4, #1284]	; 0x504

    nvmc_readonly_mode_set();
}
    41a4:	bd10      	pop	{r4, pc}
    41a6:	bf00      	nop
    41a8:	4001e000 	.word	0x4001e000

000041ac <nrfx_ppi_channel_alloc>:
    nrfx_flag32_init(&m_groups_allocated, NRFX_PPI_ALL_APP_GROUPS_MASK);
}


nrfx_err_t nrfx_ppi_channel_alloc(nrf_ppi_channel_t * p_channel)
{
    41ac:	4601      	mov	r1, r0
    return nrfx_flag32_alloc(&m_channels_allocated, (uint8_t *)p_channel);
    41ae:	4801      	ldr	r0, [pc, #4]	; (41b4 <nrfx_ppi_channel_alloc+0x8>)
    41b0:	f7ff bb70 	b.w	3894 <nrfx_flag32_alloc>
    41b4:	200000cc 	.word	0x200000cc

000041b8 <_DoInit>:
                      _DoInit();                                                                     \
                    }                                                                                \
                  } while (0);                                                                       \
                }

static void _DoInit(void) {
    41b8:	b510      	push	{r4, lr}
  volatile SEGGER_RTT_CB* p;   // Volatile to make sure that compiler cannot change the order of accesses to the control block
  //
  // Initialize control block
  //
  p                     = (volatile SEGGER_RTT_CB*)((char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access control block uncached so that nothing in the cache ever becomes dirty and all changes are visible in HW directly
  p->MaxNumUpBuffers    = SEGGER_RTT_MAX_NUM_UP_BUFFERS;
    41ba:	4c14      	ldr	r4, [pc, #80]	; (420c <_DoInit+0x54>)
  p->MaxNumDownBuffers  = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS;
  //
  // Initialize up buffer 0
  //
  p->aUp[0].sName         = "Terminal";
    41bc:	4a14      	ldr	r2, [pc, #80]	; (4210 <_DoInit+0x58>)
  //
  // Finish initialization of the control block.
  // Copy Id string in three steps to make sure "SEGGER RTT" is not found
  // in initializer memory (usually flash) by J-Link
  //
  STRCPY((char*)&p->acID[7], "RTT");
    41be:	4915      	ldr	r1, [pc, #84]	; (4214 <_DoInit+0x5c>)
  p->MaxNumUpBuffers    = SEGGER_RTT_MAX_NUM_UP_BUFFERS;
    41c0:	2303      	movs	r3, #3
    41c2:	6123      	str	r3, [r4, #16]
  p->MaxNumDownBuffers  = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS;
    41c4:	6163      	str	r3, [r4, #20]
  p->aUp[0].pBuffer       = _acUpBuffer;
    41c6:	4b14      	ldr	r3, [pc, #80]	; (4218 <_DoInit+0x60>)
  p->aUp[0].sName         = "Terminal";
    41c8:	61a2      	str	r2, [r4, #24]
  p->aUp[0].pBuffer       = _acUpBuffer;
    41ca:	61e3      	str	r3, [r4, #28]
  p->aUp[0].SizeOfBuffer  = BUFFER_SIZE_UP;
    41cc:	f44f 6380 	mov.w	r3, #1024	; 0x400
    41d0:	6223      	str	r3, [r4, #32]
  p->aUp[0].RdOff         = 0u;
    41d2:	2300      	movs	r3, #0
    41d4:	62a3      	str	r3, [r4, #40]	; 0x28
  p->aUp[0].WrOff         = 0u;
    41d6:	6263      	str	r3, [r4, #36]	; 0x24
  p->aUp[0].Flags         = SEGGER_RTT_MODE_DEFAULT;
    41d8:	62e3      	str	r3, [r4, #44]	; 0x2c
  p->aDown[0].sName         = "Terminal";
    41da:	6622      	str	r2, [r4, #96]	; 0x60
  p->aDown[0].pBuffer       = _acDownBuffer;
    41dc:	4a0f      	ldr	r2, [pc, #60]	; (421c <_DoInit+0x64>)
    41de:	6662      	str	r2, [r4, #100]	; 0x64
  p->aDown[0].SizeOfBuffer  = BUFFER_SIZE_DOWN;
    41e0:	2210      	movs	r2, #16
    41e2:	66a2      	str	r2, [r4, #104]	; 0x68
  STRCPY((char*)&p->acID[7], "RTT");
    41e4:	1de0      	adds	r0, r4, #7
  p->aDown[0].RdOff         = 0u;
    41e6:	6723      	str	r3, [r4, #112]	; 0x70
  p->aDown[0].WrOff         = 0u;
    41e8:	66e3      	str	r3, [r4, #108]	; 0x6c
  p->aDown[0].Flags         = SEGGER_RTT_MODE_DEFAULT;
    41ea:	6763      	str	r3, [r4, #116]	; 0x74
  STRCPY((char*)&p->acID[7], "RTT");
    41ec:	f002 fa51 	bl	6692 <strcpy>
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
    41f0:	f3bf 8f5f 	dmb	sy
  STRCPY((char*)&p->acID[0], "SEGGER");
    41f4:	490a      	ldr	r1, [pc, #40]	; (4220 <_DoInit+0x68>)
    41f6:	4620      	mov	r0, r4
    41f8:	f002 fa4b 	bl	6692 <strcpy>
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
    41fc:	f3bf 8f5f 	dmb	sy
  p->acID[6] = ' ';
    4200:	2320      	movs	r3, #32
    4202:	71a3      	strb	r3, [r4, #6]
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
    4204:	f3bf 8f5f 	dmb	sy
}
    4208:	bd10      	pop	{r4, pc}
    420a:	bf00      	nop
    420c:	20000ef8 	.word	0x20000ef8
    4210:	0000813e 	.word	0x0000813e
    4214:	00008147 	.word	0x00008147
    4218:	200010d3 	.word	0x200010d3
    421c:	200010c3 	.word	0x200010c3
    4220:	0000814b 	.word	0x0000814b

00004224 <z_fatal_error>:
	return 0;
#endif
}

void z_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
{
    4224:	b573      	push	{r0, r1, r4, r5, r6, lr}
    4226:	4604      	mov	r4, r0
    4228:	460d      	mov	r5, r1
	__asm__ volatile(
    422a:	f04f 0320 	mov.w	r3, #32
    422e:	f3ef 8611 	mrs	r6, BASEPRI
    4232:	f383 8812 	msr	BASEPRI_MAX, r3
    4236:	f3bf 8f6f 	isb	sy
	switch (reason) {
    423a:	2804      	cmp	r0, #4
    423c:	bf96      	itet	ls
    423e:	4b12      	ldrls	r3, [pc, #72]	; (4288 <z_fatal_error+0x64>)
    4240:	4b12      	ldrhi	r3, [pc, #72]	; (428c <z_fatal_error+0x68>)
    4242:	f853 3020 	ldrls.w	r3, [r3, r0, lsl #2]
			k_current_get() : NULL;

	/* twister looks for the "ZEPHYR FATAL ERROR" string, don't
	 * change it without also updating twister
	 */
	LOG_ERR(">>> ZEPHYR FATAL ERROR %d: %s on CPU %d", reason,
    4246:	2200      	movs	r2, #0
    4248:	9200      	str	r2, [sp, #0]
    424a:	2145      	movs	r1, #69	; 0x45
    424c:	4602      	mov	r2, r0
    424e:	4810      	ldr	r0, [pc, #64]	; (4290 <z_fatal_error+0x6c>)
    4250:	f002 f98d 	bl	656e <z_log_minimal_printk>
	 * an IRQ or exception was being handled, or thread context.
	 *
	 * See #17656
	 */
#if defined(CONFIG_ARCH_HAS_NESTED_EXCEPTION_DETECTION)
	if ((esf != NULL) && arch_is_in_nested_exception(esf)) {
    4254:	b13d      	cbz	r5, 4266 <z_fatal_error+0x42>
 * @return true if execution state was in handler mode, before
 *              the current exception occurred, otherwise false.
 */
static ALWAYS_INLINE bool arch_is_in_nested_exception(const z_arch_esf_t *esf)
{
	return (esf->basic.xpsr & IPSR_ISR_Msk) ? (true) : (false);
    4256:	69eb      	ldr	r3, [r5, #28]
    4258:	f3c3 0308 	ubfx	r3, r3, #0, #9
    425c:	b11b      	cbz	r3, 4266 <z_fatal_error+0x42>
		LOG_ERR("Fault during interrupt handling\n");
    425e:	480d      	ldr	r0, [pc, #52]	; (4294 <z_fatal_error+0x70>)
    4260:	2145      	movs	r1, #69	; 0x45
    4262:	f002 f984 	bl	656e <z_log_minimal_printk>
	}
#endif

	LOG_ERR("Current thread: %p (%s)", thread,
    4266:	4b0c      	ldr	r3, [pc, #48]	; (4298 <z_fatal_error+0x74>)
    4268:	480c      	ldr	r0, [pc, #48]	; (429c <z_fatal_error+0x78>)
    426a:	2200      	movs	r2, #0
    426c:	2145      	movs	r1, #69	; 0x45
    426e:	f002 f97e 	bl	656e <z_log_minimal_printk>

#ifndef CONFIG_XTENSA
	coredump(reason, esf, thread);
#endif

	k_sys_fatal_error_handler(reason, esf);
    4272:	4629      	mov	r1, r5
    4274:	4620      	mov	r0, r4
    4276:	f7ff f909 	bl	348c <k_sys_fatal_error_handler>
	__asm__ volatile(
    427a:	f386 8811 	msr	BASEPRI, r6
    427e:	f3bf 8f6f 	isb	sy
	arch_irq_unlock(key);

	if (IS_ENABLED(CONFIG_MULTITHREADING)) {
		k_thread_abort(thread);
	}
}
    4282:	b002      	add	sp, #8
    4284:	bd70      	pop	{r4, r5, r6, pc}
    4286:	bf00      	nop
    4288:	000073c0 	.word	0x000073c0
    428c:	00008152 	.word	0x00008152
    4290:	00008160 	.word	0x00008160
    4294:	0000818d 	.word	0x0000818d
    4298:	000081b3 	.word	0x000081b3
    429c:	000081bb 	.word	0x000081bb

000042a0 <z_sys_init_run_level>:
		/* End marker */
		__init_end,
	};
	const struct init_entry *entry;

	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    42a0:	4b0f      	ldr	r3, [pc, #60]	; (42e0 <z_sys_init_run_level+0x40>)
{
    42a2:	b570      	push	{r4, r5, r6, lr}
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    42a4:	f853 4020 	ldr.w	r4, [r3, r0, lsl #2]
    42a8:	3001      	adds	r0, #1
    42aa:	f853 6020 	ldr.w	r6, [r3, r0, lsl #2]
    42ae:	42a6      	cmp	r6, r4
    42b0:	d800      	bhi.n	42b4 <z_sys_init_run_level+0x14>
				dev->state->init_res = rc;
			}
			dev->state->initialized = true;
		}
	}
}
    42b2:	bd70      	pop	{r4, r5, r6, pc}
		int rc = entry->init(dev);
    42b4:	e9d4 3500 	ldrd	r3, r5, [r4]
    42b8:	4628      	mov	r0, r5
    42ba:	4798      	blx	r3
		if (dev != NULL) {
    42bc:	b16d      	cbz	r5, 42da <z_sys_init_run_level+0x3a>
			if (rc != 0) {
    42be:	b138      	cbz	r0, 42d0 <z_sys_init_run_level+0x30>
				if (rc < 0) {
    42c0:	2800      	cmp	r0, #0
    42c2:	bfb8      	it	lt
    42c4:	4240      	neglt	r0, r0
				dev->state->init_res = rc;
    42c6:	68eb      	ldr	r3, [r5, #12]
				if (rc > UINT8_MAX) {
    42c8:	28ff      	cmp	r0, #255	; 0xff
    42ca:	bfa8      	it	ge
    42cc:	20ff      	movge	r0, #255	; 0xff
				dev->state->init_res = rc;
    42ce:	7018      	strb	r0, [r3, #0]
			dev->state->initialized = true;
    42d0:	68ea      	ldr	r2, [r5, #12]
    42d2:	7853      	ldrb	r3, [r2, #1]
    42d4:	f043 0301 	orr.w	r3, r3, #1
    42d8:	7053      	strb	r3, [r2, #1]
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    42da:	3408      	adds	r4, #8
    42dc:	e7e7      	b.n	42ae <z_sys_init_run_level+0xe>
    42de:	bf00      	nop
    42e0:	000073d4 	.word	0x000073d4

000042e4 <bg_thread_main>:
 * This routine completes kernel initialization by invoking the remaining
 * init functions, then invokes application's main() routine.
 */
__boot_func
static void bg_thread_main(void *unused1, void *unused2, void *unused3)
{
    42e4:	b508      	push	{r3, lr}
	 * may perform memory management tasks (except for z_phys_map() which
	 * is allowed at any time)
	 */
	z_mem_manage_init();
#endif /* CONFIG_MMU */
	z_sys_post_kernel = true;
    42e6:	4b09      	ldr	r3, [pc, #36]	; (430c <bg_thread_main+0x28>)
    42e8:	2201      	movs	r2, #1

	z_sys_init_run_level(INIT_LEVEL_POST_KERNEL);
    42ea:	2003      	movs	r0, #3
	z_sys_post_kernel = true;
    42ec:	701a      	strb	r2, [r3, #0]
	z_sys_init_run_level(INIT_LEVEL_POST_KERNEL);
    42ee:	f7ff ffd7 	bl	42a0 <z_sys_init_run_level>
#if CONFIG_STACK_POINTER_RANDOM
	z_stack_adjust_initialized = 1;
#endif
	boot_banner();
    42f2:	f000 f913 	bl	451c <boot_banner>
	void z_cpp_init_static(void);
	z_cpp_init_static();
#endif

	/* Final init level before app starts */
	z_sys_init_run_level(INIT_LEVEL_APPLICATION);
    42f6:	2004      	movs	r0, #4
    42f8:	f7ff ffd2 	bl	42a0 <z_sys_init_run_level>
	z_mem_manage_boot_finish();
#endif /* CONFIG_MMU */

	extern void main(void);

	main();
    42fc:	f7fc f86a 	bl	3d4 <main>

	/* Mark nonessential since main() has no more work to do */
	z_main_thread.base.user_options &= ~K_ESSENTIAL;
    4300:	4a03      	ldr	r2, [pc, #12]	; (4310 <bg_thread_main+0x2c>)
    4302:	7b13      	ldrb	r3, [r2, #12]
    4304:	f023 0301 	bic.w	r3, r3, #1
    4308:	7313      	strb	r3, [r2, #12]

#ifdef CONFIG_COVERAGE_DUMP
	/* Dump coverage data once the main() has exited. */
	gcov_coverage_dump();
#endif
} /* LCOV_EXCL_LINE ... because we just dumped final coverage data */
    430a:	bd08      	pop	{r3, pc}
    430c:	200014d3 	.word	0x200014d3
    4310:	20000168 	.word	0x20000168

00004314 <z_bss_zero>:
{
    4314:	b508      	push	{r3, lr}
	z_early_memset(__bss_start, 0, __bss_end - __bss_start);
    4316:	4803      	ldr	r0, [pc, #12]	; (4324 <z_bss_zero+0x10>)
    4318:	4a03      	ldr	r2, [pc, #12]	; (4328 <z_bss_zero+0x14>)
    431a:	2100      	movs	r1, #0
    431c:	1a12      	subs	r2, r2, r0
    431e:	f002 fda8 	bl	6e72 <z_early_memset>
}
    4322:	bd08      	pop	{r3, pc}
    4324:	20000148 	.word	0x20000148
    4328:	200014d4 	.word	0x200014d4

0000432c <z_cstart>:
 *
 * @return Does not return
 */
__boot_func
FUNC_NORETURN void z_cstart(void)
{
    432c:	b508      	push	{r3, lr}
	/* gcov hook needed to get the coverage report.*/
	gcov_static_init();

	/* initialize early init calls */
	z_sys_init_run_level(INIT_LEVEL_EARLY);
    432e:	2000      	movs	r0, #0
    4330:	f7ff ffb6 	bl	42a0 <z_sys_init_run_level>
 * pointer) register, and switched to automatically when taking an exception.
 *
 */
static ALWAYS_INLINE void z_arm_interrupt_stack_setup(void)
{
	uint32_t msp =
    4334:	4b18      	ldr	r3, [pc, #96]	; (4398 <z_cstart+0x6c>)
  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
    4336:	f383 8808 	msr	MSP, r3
	 * for Cortex-M3 and Cortex-M4 (ARMv7-M) MCUs. For the rest
	 * of ARM Cortex-M processors this setting is enforced by
	 * default and it is not configurable.
	 */
#if defined(CONFIG_CPU_CORTEX_M3) || defined(CONFIG_CPU_CORTEX_M4)
	SCB->CCR |= SCB_CCR_STKALIGN_Msk;
    433a:	4c18      	ldr	r4, [pc, #96]	; (439c <z_cstart+0x70>)
    433c:	6963      	ldr	r3, [r4, #20]
    433e:	f443 7300 	orr.w	r3, r3, #512	; 0x200
    4342:	6163      	str	r3, [r4, #20]
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    4344:	2500      	movs	r5, #0
    4346:	23e0      	movs	r3, #224	; 0xe0
    4348:	f884 3022 	strb.w	r3, [r4, #34]	; 0x22
    434c:	77e5      	strb	r5, [r4, #31]
    434e:	7625      	strb	r5, [r4, #24]
    4350:	7665      	strb	r5, [r4, #25]
    4352:	76a5      	strb	r5, [r4, #26]
    4354:	f884 5020 	strb.w	r5, [r4, #32]
#if defined(CONFIG_ARM_SECURE_FIRMWARE)
	NVIC_SetPriority(SecureFault_IRQn, _EXC_FAULT_PRIO);
#endif /* CONFIG_ARM_SECURE_FIRMWARE */

	/* Enable Usage, Mem, & Bus Faults */
	SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk |
    4358:	6a63      	ldr	r3, [r4, #36]	; 0x24
    435a:	f443 23e0 	orr.w	r3, r3, #458752	; 0x70000
    435e:	6263      	str	r3, [r4, #36]	; 0x24
    4360:	f884 5023 	strb.w	r5, [r4, #35]	; 0x23

static ALWAYS_INLINE void arch_kernel_init(void)
{
	z_arm_interrupt_stack_setup();
	z_arm_exc_setup();
	z_arm_fault_init();
    4364:	f7fd fe9a 	bl	209c <z_arm_fault_init>
	z_arm_cpu_idle_init();
    4368:	f7fd fb9e 	bl	1aa8 <z_arm_cpu_idle_init>
static ALWAYS_INLINE void z_arm_clear_faults(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* Reset all faults */
	SCB->CFSR = SCB_CFSR_USGFAULTSR_Msk |
    436c:	f04f 33ff 	mov.w	r3, #4294967295
    4370:	62a3      	str	r3, [r4, #40]	; 0x28
		    SCB_CFSR_MEMFAULTSR_Msk |
		    SCB_CFSR_BUSFAULTSR_Msk;

	/* Clear all Hard Faults - HFSR is write-one-to-clear */
	SCB->HFSR = 0xffffffff;
    4372:	62e3      	str	r3, [r4, #44]	; 0x2c
	z_arm_clear_faults();
#if defined(CONFIG_ARM_MPU)
	z_arm_mpu_init();
    4374:	f7fd ff9a 	bl	22ac <z_arm_mpu_init>
	 * to set up access permissions for fixed memory sections, such
	 * as Application Memory or No-Cacheable SRAM area.
	 *
	 * This function is invoked once, upon system initialization.
	 */
	z_arm_configure_static_mpu_regions();
    4378:	f7fd ff1c 	bl	21b4 <z_arm_configure_static_mpu_regions>
	struct k_thread dummy_thread;

	z_dummy_thread_init(&dummy_thread);
#endif
	/* do any necessary initialization of static devices */
	z_device_state_init();
    437c:	f002 fd6d 	bl	6e5a <z_device_state_init>

	/* perform basic hardware initialization */
	z_sys_init_run_level(INIT_LEVEL_PRE_KERNEL_1);
    4380:	2001      	movs	r0, #1
    4382:	f7ff ff8d 	bl	42a0 <z_sys_init_run_level>
	z_sys_init_run_level(INIT_LEVEL_PRE_KERNEL_2);
    4386:	2002      	movs	r0, #2
    4388:	f7ff ff8a 	bl	42a0 <z_sys_init_run_level>
#else
#ifdef ARCH_SWITCH_TO_MAIN_NO_MULTITHREADING
	/* Custom ARCH-specific routine to switch to main()
	 * in the case of no multi-threading.
	 */
	ARCH_SWITCH_TO_MAIN_NO_MULTITHREADING(bg_thread_main,
    438c:	4804      	ldr	r0, [pc, #16]	; (43a0 <z_cstart+0x74>)
    438e:	462b      	mov	r3, r5
    4390:	462a      	mov	r2, r5
    4392:	4629      	mov	r1, r5
    4394:	f7fd fc60 	bl	1c58 <z_arm_switch_to_main_no_multithreading>
    4398:	20001d40 	.word	0x20001d40
    439c:	e000ed00 	.word	0xe000ed00
    43a0:	000042e5 	.word	0x000042e5

000043a4 <z_data_copy>:
 * @brief Copy the data section from ROM to RAM
 *
 * This routine copies the data section from ROM to RAM.
 */
void z_data_copy(void)
{
    43a4:	b508      	push	{r3, lr}
	z_early_memcpy(&__data_region_start, &__data_region_load_start,
		       __data_region_end - __data_region_start);
    43a6:	4806      	ldr	r0, [pc, #24]	; (43c0 <z_data_copy+0x1c>)
	z_early_memcpy(&__data_region_start, &__data_region_load_start,
    43a8:	4a06      	ldr	r2, [pc, #24]	; (43c4 <z_data_copy+0x20>)
    43aa:	4907      	ldr	r1, [pc, #28]	; (43c8 <z_data_copy+0x24>)
    43ac:	1a12      	subs	r2, r2, r0
    43ae:	f002 fd62 	bl	6e76 <z_early_memcpy>
#else
	z_early_memcpy(&_app_smem_start, &_app_smem_rom_start,
		       _app_smem_end - _app_smem_start);
#endif /* CONFIG_STACK_CANARIES */
#endif /* CONFIG_USERSPACE */
}
    43b2:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	z_early_memcpy(&__ramfunc_start, &__ramfunc_load_start,
    43b6:	4a05      	ldr	r2, [pc, #20]	; (43cc <z_data_copy+0x28>)
    43b8:	4905      	ldr	r1, [pc, #20]	; (43d0 <z_data_copy+0x2c>)
    43ba:	4806      	ldr	r0, [pc, #24]	; (43d4 <z_data_copy+0x30>)
    43bc:	f002 bd5b 	b.w	6e76 <z_early_memcpy>
    43c0:	20000000 	.word	0x20000000
    43c4:	20000144 	.word	0x20000144
    43c8:	00008254 	.word	0x00008254
    43cc:	00000000 	.word	0x00000000
    43d0:	00008254 	.word	0x00008254
    43d4:	20000000 	.word	0x20000000

000043d8 <elapsed>:
	sys_dlist_remove(&t->node);
}

static int32_t elapsed(void)
{
	return announce_remaining == 0 ? sys_clock_elapsed() : 0U;
    43d8:	4b03      	ldr	r3, [pc, #12]	; (43e8 <elapsed+0x10>)
    43da:	681b      	ldr	r3, [r3, #0]
    43dc:	b90b      	cbnz	r3, 43e2 <elapsed+0xa>
    43de:	f7fe bf73 	b.w	32c8 <sys_clock_elapsed>
}
    43e2:	2000      	movs	r0, #0
    43e4:	4770      	bx	lr
    43e6:	bf00      	nop
    43e8:	20000fa0 	.word	0x20000fa0

000043ec <next_timeout>:

static int32_t next_timeout(void)
{
    43ec:	b510      	push	{r4, lr}
 * @return true if empty, false otherwise
 */

static inline bool sys_dlist_is_empty(sys_dlist_t *list)
{
	return list->head == list;
    43ee:	4b0e      	ldr	r3, [pc, #56]	; (4428 <next_timeout+0x3c>)
    43f0:	681c      	ldr	r4, [r3, #0]
 * @return a pointer to the head element, NULL if list is empty
 */

static inline sys_dnode_t *sys_dlist_peek_head(sys_dlist_t *list)
{
	return sys_dlist_is_empty(list) ? NULL : list->head;
    43f2:	429c      	cmp	r4, r3
    43f4:	d104      	bne.n	4400 <next_timeout+0x14>
	struct _timeout *to = first();
	int32_t ticks_elapsed = elapsed();
    43f6:	f7ff ffef 	bl	43d8 <elapsed>
	int32_t ret;

	if ((to == NULL) ||
	    ((int64_t)(to->dticks - ticks_elapsed) > (int64_t)INT_MAX)) {
		ret = MAX_WAIT;
    43fa:	f06f 4000 	mvn.w	r0, #2147483648	; 0x80000000
	if (_current_cpu->slice_ticks && _current_cpu->slice_ticks < ret) {
		ret = _current_cpu->slice_ticks;
	}
#endif
	return ret;
}
    43fe:	bd10      	pop	{r4, pc}
	int32_t ticks_elapsed = elapsed();
    4400:	f7ff ffea 	bl	43d8 <elapsed>
	if ((to == NULL) ||
    4404:	2c00      	cmp	r4, #0
    4406:	d0f8      	beq.n	43fa <next_timeout+0xe>
	    ((int64_t)(to->dticks - ticks_elapsed) > (int64_t)INT_MAX)) {
    4408:	e9d4 3204 	ldrd	r3, r2, [r4, #16]
    440c:	1a1b      	subs	r3, r3, r0
    440e:	eb62 72e0 	sbc.w	r2, r2, r0, asr #31
	if ((to == NULL) ||
    4412:	f1b3 4f00 	cmp.w	r3, #2147483648	; 0x80000000
    4416:	f172 0100 	sbcs.w	r1, r2, #0
    441a:	daee      	bge.n	43fa <next_timeout+0xe>
		ret = MAX(0, to->dticks - ticks_elapsed);
    441c:	2a00      	cmp	r2, #0
    441e:	bfac      	ite	ge
    4420:	4618      	movge	r0, r3
    4422:	2000      	movlt	r0, #0
	return ret;
    4424:	e7eb      	b.n	43fe <next_timeout+0x12>
    4426:	bf00      	nop
    4428:	200000d0 	.word	0x200000d0

0000442c <remove_timeout>:
{
    442c:	b530      	push	{r4, r5, lr}
 */

static inline sys_dnode_t *sys_dlist_peek_next(sys_dlist_t *list,
					       sys_dnode_t *node)
{
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    442e:	b170      	cbz	r0, 444e <remove_timeout+0x22>
	return (node == list->tail) ? NULL : node->next;
    4430:	4b0b      	ldr	r3, [pc, #44]	; (4460 <remove_timeout+0x34>)
    4432:	685b      	ldr	r3, [r3, #4]
    4434:	4298      	cmp	r0, r3
    4436:	d00a      	beq.n	444e <remove_timeout+0x22>
    4438:	6803      	ldr	r3, [r0, #0]
	if (next(t) != NULL) {
    443a:	b143      	cbz	r3, 444e <remove_timeout+0x22>
		next(t)->dticks += t->dticks;
    443c:	e9d3 2104 	ldrd	r2, r1, [r3, #16]
    4440:	e9d0 4504 	ldrd	r4, r5, [r0, #16]
    4444:	1912      	adds	r2, r2, r4
    4446:	eb41 0105 	adc.w	r1, r1, r5
    444a:	e9c3 2104 	strd	r2, r1, [r3, #16]
 */

static inline void sys_dlist_remove(sys_dnode_t *node)
{
	sys_dnode_t *const prev = node->prev;
	sys_dnode_t *const next = node->next;
    444e:	e9d0 3200 	ldrd	r3, r2, [r0]

	prev->next = next;
    4452:	6013      	str	r3, [r2, #0]
	next->prev = prev;
    4454:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    4456:	2300      	movs	r3, #0
	node->prev = NULL;
    4458:	e9c0 3300 	strd	r3, r3, [r0]
}
    445c:	bd30      	pop	{r4, r5, pc}
    445e:	bf00      	nop
    4460:	200000d0 	.word	0x200000d0

00004464 <sys_clock_announce>:
		}
	}
}

void sys_clock_announce(int32_t ticks)
{
    4464:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    4468:	4603      	mov	r3, r0
	__asm__ volatile(
    446a:	f04f 0220 	mov.w	r2, #32
    446e:	f3ef 8411 	mrs	r4, BASEPRI
    4472:	f382 8812 	msr	BASEPRI_MAX, r2
    4476:	f3bf 8f6f 	isb	sy
		announce_remaining += ticks;
		k_spin_unlock(&timeout_lock, key);
		return;
	}

	announce_remaining = ticks;
    447a:	4f25      	ldr	r7, [pc, #148]	; (4510 <sys_clock_announce+0xac>)
	return list->head == list;
    447c:	f8df 9094 	ldr.w	r9, [pc, #148]	; 4514 <sys_clock_announce+0xb0>
    4480:	f8d9 0000 	ldr.w	r0, [r9]

	while (first() != NULL && first()->dticks <= announce_remaining) {
		struct _timeout *t = first();
		int dt = t->dticks;

		curr_tick += dt;
    4484:	f8df c090 	ldr.w	ip, [pc, #144]	; 4518 <sys_clock_announce+0xb4>
	announce_remaining = ticks;
    4488:	603b      	str	r3, [r7, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    448a:	4548      	cmp	r0, r9
		curr_tick += dt;
    448c:	e9dc 1e00 	ldrd	r1, lr, [ip]
    4490:	ea4f 75e3 	mov.w	r5, r3, asr #31
    4494:	d00c      	beq.n	44b0 <sys_clock_announce+0x4c>
	while (first() != NULL && first()->dticks <= announce_remaining) {
    4496:	b158      	cbz	r0, 44b0 <sys_clock_announce+0x4c>
    4498:	e9d0 8604 	ldrd	r8, r6, [r0, #16]
    449c:	4543      	cmp	r3, r8
    449e:	eb75 0206 	sbcs.w	r2, r5, r6
    44a2:	da17      	bge.n	44d4 <sys_clock_announce+0x70>
		key = k_spin_lock(&timeout_lock);
		announce_remaining -= dt;
	}

	if (first() != NULL) {
		first()->dticks -= announce_remaining;
    44a4:	ebb8 0203 	subs.w	r2, r8, r3
    44a8:	eb66 0605 	sbc.w	r6, r6, r5
    44ac:	e9c0 2604 	strd	r2, r6, [r0, #16]
	}

	curr_tick += announce_remaining;
    44b0:	1859      	adds	r1, r3, r1
    44b2:	eb4e 0505 	adc.w	r5, lr, r5
    44b6:	e9cc 1500 	strd	r1, r5, [ip]
	announce_remaining = 0;
    44ba:	2500      	movs	r5, #0
    44bc:	603d      	str	r5, [r7, #0]

	sys_clock_set_timeout(next_timeout(), false);
    44be:	f7ff ff95 	bl	43ec <next_timeout>
    44c2:	4629      	mov	r1, r5
    44c4:	f7fe fece 	bl	3264 <sys_clock_set_timeout>
	__asm__ volatile(
    44c8:	f384 8811 	msr	BASEPRI, r4
    44cc:	f3bf 8f6f 	isb	sy

	k_spin_unlock(&timeout_lock, key);
}
    44d0:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
		curr_tick += dt;
    44d4:	eb18 0101 	adds.w	r1, r8, r1
    44d8:	eb4e 73e8 	adc.w	r3, lr, r8, asr #31
    44dc:	e9cc 1300 	strd	r1, r3, [ip]
		t->dticks = 0;
    44e0:	2200      	movs	r2, #0
    44e2:	2300      	movs	r3, #0
    44e4:	e9c0 2304 	strd	r2, r3, [r0, #16]
		remove_timeout(t);
    44e8:	f7ff ffa0 	bl	442c <remove_timeout>
    44ec:	f384 8811 	msr	BASEPRI, r4
    44f0:	f3bf 8f6f 	isb	sy
		t->fn(t);
    44f4:	6883      	ldr	r3, [r0, #8]
    44f6:	4798      	blx	r3
	__asm__ volatile(
    44f8:	f04f 0320 	mov.w	r3, #32
    44fc:	f3ef 8411 	mrs	r4, BASEPRI
    4500:	f383 8812 	msr	BASEPRI_MAX, r3
    4504:	f3bf 8f6f 	isb	sy
		announce_remaining -= dt;
    4508:	683b      	ldr	r3, [r7, #0]
    450a:	eba3 0308 	sub.w	r3, r3, r8
    450e:	e7b7      	b.n	4480 <sys_clock_announce+0x1c>
    4510:	20000fa0 	.word	0x20000fa0
    4514:	200000d0 	.word	0x200000d0
    4518:	200001e8 	.word	0x200001e8

0000451c <boot_banner>:
	printk("***** delaying boot " DELAY_STR "ms (per build configuration) *****\n");
	k_busy_wait(CONFIG_BOOT_DELAY * USEC_PER_MSEC);
#endif /* defined(CONFIG_BOOT_DELAY) && (CONFIG_BOOT_DELAY > 0) */

#if CONFIG_BOOT_BANNER
	printk("*** Booting Zephyr OS build " BANNER_VERSION BANNER_POSTFIX " ***\n");
    451c:	4801      	ldr	r0, [pc, #4]	; (4524 <boot_banner+0x8>)
    451e:	f001 bf3e 	b.w	639e <printk>
    4522:	bf00      	nop
    4524:	00008225 	.word	0x00008225

00004528 <nrf_cc3xx_platform_init_no_rng>:
    4528:	b510      	push	{r4, lr}
    452a:	4c0a      	ldr	r4, [pc, #40]	; (4554 <nrf_cc3xx_platform_init_no_rng+0x2c>)
    452c:	6823      	ldr	r3, [r4, #0]
    452e:	b11b      	cbz	r3, 4538 <nrf_cc3xx_platform_init_no_rng+0x10>
    4530:	2301      	movs	r3, #1
    4532:	6023      	str	r3, [r4, #0]
    4534:	2000      	movs	r0, #0
    4536:	bd10      	pop	{r4, pc}
    4538:	f000 f852 	bl	45e0 <CC_LibInitNoRng>
    453c:	2800      	cmp	r0, #0
    453e:	d0f7      	beq.n	4530 <nrf_cc3xx_platform_init_no_rng+0x8>
    4540:	3801      	subs	r0, #1
    4542:	2806      	cmp	r0, #6
    4544:	d803      	bhi.n	454e <nrf_cc3xx_platform_init_no_rng+0x26>
    4546:	4b04      	ldr	r3, [pc, #16]	; (4558 <nrf_cc3xx_platform_init_no_rng+0x30>)
    4548:	f853 0020 	ldr.w	r0, [r3, r0, lsl #2]
    454c:	bd10      	pop	{r4, pc}
    454e:	4803      	ldr	r0, [pc, #12]	; (455c <nrf_cc3xx_platform_init_no_rng+0x34>)
    4550:	bd10      	pop	{r4, pc}
    4552:	bf00      	nop
    4554:	20000fa4 	.word	0x20000fa4
    4558:	000073ec 	.word	0x000073ec
    455c:	ffff8ffe 	.word	0xffff8ffe

00004560 <nrf_cc3xx_platform_abort>:
    4560:	f3bf 8f4f 	dsb	sy
    4564:	4905      	ldr	r1, [pc, #20]	; (457c <nrf_cc3xx_platform_abort+0x1c>)
    4566:	4b06      	ldr	r3, [pc, #24]	; (4580 <nrf_cc3xx_platform_abort+0x20>)
    4568:	68ca      	ldr	r2, [r1, #12]
    456a:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    456e:	4313      	orrs	r3, r2
    4570:	60cb      	str	r3, [r1, #12]
    4572:	f3bf 8f4f 	dsb	sy
    4576:	bf00      	nop
    4578:	e7fd      	b.n	4576 <nrf_cc3xx_platform_abort+0x16>
    457a:	bf00      	nop
    457c:	e000ed00 	.word	0xe000ed00
    4580:	05fa0004 	.word	0x05fa0004

00004584 <CC_PalAbort>:
    4584:	b410      	push	{r4}
    4586:	4b0a      	ldr	r3, [pc, #40]	; (45b0 <CC_PalAbort+0x2c>)
    4588:	490a      	ldr	r1, [pc, #40]	; (45b4 <CC_PalAbort+0x30>)
    458a:	4c0b      	ldr	r4, [pc, #44]	; (45b8 <CC_PalAbort+0x34>)
    458c:	f04f 32fe 	mov.w	r2, #4278124286	; 0xfefefefe
    4590:	f8c3 2400 	str.w	r2, [r3, #1024]	; 0x400
    4594:	6849      	ldr	r1, [r1, #4]
    4596:	f8c3 2404 	str.w	r2, [r3, #1028]	; 0x404
    459a:	f8c3 2408 	str.w	r2, [r3, #1032]	; 0x408
    459e:	f8c3 240c 	str.w	r2, [r3, #1036]	; 0x40c
    45a2:	2300      	movs	r3, #0
    45a4:	f8c4 3500 	str.w	r3, [r4, #1280]	; 0x500
    45a8:	f85d 4b04 	ldr.w	r4, [sp], #4
    45ac:	4708      	bx	r1
    45ae:	bf00      	nop
    45b0:	5002b000 	.word	0x5002b000
    45b4:	200000d8 	.word	0x200000d8
    45b8:	5002a000 	.word	0x5002a000

000045bc <nrf_cc3xx_platform_set_abort>:
    45bc:	e9d0 1200 	ldrd	r1, r2, [r0]
    45c0:	4b01      	ldr	r3, [pc, #4]	; (45c8 <nrf_cc3xx_platform_set_abort+0xc>)
    45c2:	e9c3 1200 	strd	r1, r2, [r3]
    45c6:	4770      	bx	lr
    45c8:	200000d8 	.word	0x200000d8

000045cc <mbedtls_platform_zeroize>:
    45cc:	b138      	cbz	r0, 45de <mbedtls_platform_zeroize+0x12>
    45ce:	b131      	cbz	r1, 45de <mbedtls_platform_zeroize+0x12>
    45d0:	4401      	add	r1, r0
    45d2:	2200      	movs	r2, #0
    45d4:	4603      	mov	r3, r0
    45d6:	3001      	adds	r0, #1
    45d8:	4288      	cmp	r0, r1
    45da:	701a      	strb	r2, [r3, #0]
    45dc:	d1fa      	bne.n	45d4 <mbedtls_platform_zeroize+0x8>
    45de:	4770      	bx	lr

000045e0 <CC_LibInitNoRng>:
    45e0:	b538      	push	{r3, r4, r5, lr}
    45e2:	f000 f82f 	bl	4644 <CC_HalInit>
    45e6:	b120      	cbz	r0, 45f2 <CC_LibInitNoRng+0x12>
    45e8:	2403      	movs	r4, #3
    45ea:	f000 f863 	bl	46b4 <CC_PalTerminate>
    45ee:	4620      	mov	r0, r4
    45f0:	bd38      	pop	{r3, r4, r5, pc}
    45f2:	f000 f831 	bl	4658 <CC_PalInit>
    45f6:	b998      	cbnz	r0, 4620 <CC_LibInitNoRng+0x40>
    45f8:	f000 f8ac 	bl	4754 <CC_PalPowerSaveModeSelect>
    45fc:	b998      	cbnz	r0, 4626 <CC_LibInitNoRng+0x46>
    45fe:	4d0f      	ldr	r5, [pc, #60]	; (463c <CC_LibInitNoRng+0x5c>)
    4600:	f8d5 3928 	ldr.w	r3, [r5, #2344]	; 0x928
    4604:	0e1b      	lsrs	r3, r3, #24
    4606:	2bf0      	cmp	r3, #240	; 0xf0
    4608:	d108      	bne.n	461c <CC_LibInitNoRng+0x3c>
    460a:	f8d5 2a24 	ldr.w	r2, [r5, #2596]	; 0xa24
    460e:	4b0c      	ldr	r3, [pc, #48]	; (4640 <CC_LibInitNoRng+0x60>)
    4610:	429a      	cmp	r2, r3
    4612:	d00a      	beq.n	462a <CC_LibInitNoRng+0x4a>
    4614:	2407      	movs	r4, #7
    4616:	f000 f817 	bl	4648 <CC_HalTerminate>
    461a:	e7e6      	b.n	45ea <CC_LibInitNoRng+0xa>
    461c:	2406      	movs	r4, #6
    461e:	e7fa      	b.n	4616 <CC_LibInitNoRng+0x36>
    4620:	2404      	movs	r4, #4
    4622:	4620      	mov	r0, r4
    4624:	bd38      	pop	{r3, r4, r5, pc}
    4626:	2400      	movs	r4, #0
    4628:	e7f5      	b.n	4616 <CC_LibInitNoRng+0x36>
    462a:	2001      	movs	r0, #1
    462c:	f000 f892 	bl	4754 <CC_PalPowerSaveModeSelect>
    4630:	4604      	mov	r4, r0
    4632:	2800      	cmp	r0, #0
    4634:	d1f7      	bne.n	4626 <CC_LibInitNoRng+0x46>
    4636:	f8c5 0a0c 	str.w	r0, [r5, #2572]	; 0xa0c
    463a:	e7d8      	b.n	45ee <CC_LibInitNoRng+0xe>
    463c:	5002b000 	.word	0x5002b000
    4640:	20e00000 	.word	0x20e00000

00004644 <CC_HalInit>:
    4644:	2000      	movs	r0, #0
    4646:	4770      	bx	lr

00004648 <CC_HalTerminate>:
    4648:	2000      	movs	r0, #0
    464a:	4770      	bx	lr

0000464c <CC_HalMaskInterrupt>:
    464c:	4b01      	ldr	r3, [pc, #4]	; (4654 <CC_HalMaskInterrupt+0x8>)
    464e:	f8c3 0a04 	str.w	r0, [r3, #2564]	; 0xa04
    4652:	4770      	bx	lr
    4654:	5002b000 	.word	0x5002b000

00004658 <CC_PalInit>:
    4658:	b510      	push	{r4, lr}
    465a:	4811      	ldr	r0, [pc, #68]	; (46a0 <CC_PalInit+0x48>)
    465c:	f000 f848 	bl	46f0 <CC_PalMutexCreate>
    4660:	b100      	cbz	r0, 4664 <CC_PalInit+0xc>
    4662:	bd10      	pop	{r4, pc}
    4664:	480f      	ldr	r0, [pc, #60]	; (46a4 <CC_PalInit+0x4c>)
    4666:	f000 f843 	bl	46f0 <CC_PalMutexCreate>
    466a:	2800      	cmp	r0, #0
    466c:	d1f9      	bne.n	4662 <CC_PalInit+0xa>
    466e:	4c0e      	ldr	r4, [pc, #56]	; (46a8 <CC_PalInit+0x50>)
    4670:	4620      	mov	r0, r4
    4672:	f000 f83d 	bl	46f0 <CC_PalMutexCreate>
    4676:	2800      	cmp	r0, #0
    4678:	d1f3      	bne.n	4662 <CC_PalInit+0xa>
    467a:	4b0c      	ldr	r3, [pc, #48]	; (46ac <CC_PalInit+0x54>)
    467c:	480c      	ldr	r0, [pc, #48]	; (46b0 <CC_PalInit+0x58>)
    467e:	601c      	str	r4, [r3, #0]
    4680:	f000 f836 	bl	46f0 <CC_PalMutexCreate>
    4684:	4601      	mov	r1, r0
    4686:	2800      	cmp	r0, #0
    4688:	d1eb      	bne.n	4662 <CC_PalInit+0xa>
    468a:	f000 f82d 	bl	46e8 <CC_PalDmaInit>
    468e:	4604      	mov	r4, r0
    4690:	b108      	cbz	r0, 4696 <CC_PalInit+0x3e>
    4692:	4620      	mov	r0, r4
    4694:	bd10      	pop	{r4, pc}
    4696:	f000 f83f 	bl	4718 <CC_PalPowerSaveModeInit>
    469a:	4620      	mov	r0, r4
    469c:	e7fa      	b.n	4694 <CC_PalInit+0x3c>
    469e:	bf00      	nop
    46a0:	200000ec 	.word	0x200000ec
    46a4:	200000e0 	.word	0x200000e0
    46a8:	200000e8 	.word	0x200000e8
    46ac:	200000f0 	.word	0x200000f0
    46b0:	200000e4 	.word	0x200000e4

000046b4 <CC_PalTerminate>:
    46b4:	b508      	push	{r3, lr}
    46b6:	4808      	ldr	r0, [pc, #32]	; (46d8 <CC_PalTerminate+0x24>)
    46b8:	f000 f824 	bl	4704 <CC_PalMutexDestroy>
    46bc:	4807      	ldr	r0, [pc, #28]	; (46dc <CC_PalTerminate+0x28>)
    46be:	f000 f821 	bl	4704 <CC_PalMutexDestroy>
    46c2:	4807      	ldr	r0, [pc, #28]	; (46e0 <CC_PalTerminate+0x2c>)
    46c4:	f000 f81e 	bl	4704 <CC_PalMutexDestroy>
    46c8:	4806      	ldr	r0, [pc, #24]	; (46e4 <CC_PalTerminate+0x30>)
    46ca:	f000 f81b 	bl	4704 <CC_PalMutexDestroy>
    46ce:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    46d2:	f000 b80b 	b.w	46ec <CC_PalDmaTerminate>
    46d6:	bf00      	nop
    46d8:	200000ec 	.word	0x200000ec
    46dc:	200000e0 	.word	0x200000e0
    46e0:	200000e8 	.word	0x200000e8
    46e4:	200000e4 	.word	0x200000e4

000046e8 <CC_PalDmaInit>:
    46e8:	2000      	movs	r0, #0
    46ea:	4770      	bx	lr

000046ec <CC_PalDmaTerminate>:
    46ec:	4770      	bx	lr
    46ee:	bf00      	nop

000046f0 <CC_PalMutexCreate>:
    46f0:	b508      	push	{r3, lr}
    46f2:	4b03      	ldr	r3, [pc, #12]	; (4700 <CC_PalMutexCreate+0x10>)
    46f4:	6802      	ldr	r2, [r0, #0]
    46f6:	681b      	ldr	r3, [r3, #0]
    46f8:	6810      	ldr	r0, [r2, #0]
    46fa:	4798      	blx	r3
    46fc:	2000      	movs	r0, #0
    46fe:	bd08      	pop	{r3, pc}
    4700:	200000fc 	.word	0x200000fc

00004704 <CC_PalMutexDestroy>:
    4704:	b508      	push	{r3, lr}
    4706:	4b03      	ldr	r3, [pc, #12]	; (4714 <CC_PalMutexDestroy+0x10>)
    4708:	6802      	ldr	r2, [r0, #0]
    470a:	685b      	ldr	r3, [r3, #4]
    470c:	6810      	ldr	r0, [r2, #0]
    470e:	4798      	blx	r3
    4710:	2000      	movs	r0, #0
    4712:	bd08      	pop	{r3, pc}
    4714:	200000fc 	.word	0x200000fc

00004718 <CC_PalPowerSaveModeInit>:
    4718:	b570      	push	{r4, r5, r6, lr}
    471a:	4c09      	ldr	r4, [pc, #36]	; (4740 <CC_PalPowerSaveModeInit+0x28>)
    471c:	4d09      	ldr	r5, [pc, #36]	; (4744 <CC_PalPowerSaveModeInit+0x2c>)
    471e:	6920      	ldr	r0, [r4, #16]
    4720:	68ab      	ldr	r3, [r5, #8]
    4722:	4798      	blx	r3
    4724:	b118      	cbz	r0, 472e <CC_PalPowerSaveModeInit+0x16>
    4726:	4b08      	ldr	r3, [pc, #32]	; (4748 <CC_PalPowerSaveModeInit+0x30>)
    4728:	4808      	ldr	r0, [pc, #32]	; (474c <CC_PalPowerSaveModeInit+0x34>)
    472a:	685b      	ldr	r3, [r3, #4]
    472c:	4798      	blx	r3
    472e:	4a08      	ldr	r2, [pc, #32]	; (4750 <CC_PalPowerSaveModeInit+0x38>)
    4730:	68eb      	ldr	r3, [r5, #12]
    4732:	6920      	ldr	r0, [r4, #16]
    4734:	2100      	movs	r1, #0
    4736:	6011      	str	r1, [r2, #0]
    4738:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    473c:	4718      	bx	r3
    473e:	bf00      	nop
    4740:	2000010c 	.word	0x2000010c
    4744:	200000fc 	.word	0x200000fc
    4748:	200000d8 	.word	0x200000d8
    474c:	00007408 	.word	0x00007408
    4750:	20000fa8 	.word	0x20000fa8

00004754 <CC_PalPowerSaveModeSelect>:
    4754:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    4756:	4d1a      	ldr	r5, [pc, #104]	; (47c0 <CC_PalPowerSaveModeSelect+0x6c>)
    4758:	4e1a      	ldr	r6, [pc, #104]	; (47c4 <CC_PalPowerSaveModeSelect+0x70>)
    475a:	4604      	mov	r4, r0
    475c:	68b2      	ldr	r2, [r6, #8]
    475e:	6928      	ldr	r0, [r5, #16]
    4760:	4790      	blx	r2
    4762:	b9e8      	cbnz	r0, 47a0 <CC_PalPowerSaveModeSelect+0x4c>
    4764:	4f18      	ldr	r7, [pc, #96]	; (47c8 <CC_PalPowerSaveModeSelect+0x74>)
    4766:	683b      	ldr	r3, [r7, #0]
    4768:	b14c      	cbz	r4, 477e <CC_PalPowerSaveModeSelect+0x2a>
    476a:	b1a3      	cbz	r3, 4796 <CC_PalPowerSaveModeSelect+0x42>
    476c:	2b01      	cmp	r3, #1
    476e:	d019      	beq.n	47a4 <CC_PalPowerSaveModeSelect+0x50>
    4770:	3b01      	subs	r3, #1
    4772:	603b      	str	r3, [r7, #0]
    4774:	6928      	ldr	r0, [r5, #16]
    4776:	68f3      	ldr	r3, [r6, #12]
    4778:	4798      	blx	r3
    477a:	2000      	movs	r0, #0
    477c:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    477e:	b943      	cbnz	r3, 4792 <CC_PalPowerSaveModeSelect+0x3e>
    4780:	4a12      	ldr	r2, [pc, #72]	; (47cc <CC_PalPowerSaveModeSelect+0x78>)
    4782:	2101      	movs	r1, #1
    4784:	f8c2 1500 	str.w	r1, [r2, #1280]	; 0x500
    4788:	4911      	ldr	r1, [pc, #68]	; (47d0 <CC_PalPowerSaveModeSelect+0x7c>)
    478a:	f8d1 2910 	ldr.w	r2, [r1, #2320]	; 0x910
    478e:	2a00      	cmp	r2, #0
    4790:	d1fb      	bne.n	478a <CC_PalPowerSaveModeSelect+0x36>
    4792:	3301      	adds	r3, #1
    4794:	603b      	str	r3, [r7, #0]
    4796:	68f3      	ldr	r3, [r6, #12]
    4798:	6928      	ldr	r0, [r5, #16]
    479a:	4798      	blx	r3
    479c:	2000      	movs	r0, #0
    479e:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    47a0:	480c      	ldr	r0, [pc, #48]	; (47d4 <CC_PalPowerSaveModeSelect+0x80>)
    47a2:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    47a4:	4a0a      	ldr	r2, [pc, #40]	; (47d0 <CC_PalPowerSaveModeSelect+0x7c>)
    47a6:	f8d2 3910 	ldr.w	r3, [r2, #2320]	; 0x910
    47aa:	2b00      	cmp	r3, #0
    47ac:	d1fb      	bne.n	47a6 <CC_PalPowerSaveModeSelect+0x52>
    47ae:	4a07      	ldr	r2, [pc, #28]	; (47cc <CC_PalPowerSaveModeSelect+0x78>)
    47b0:	f06f 407e 	mvn.w	r0, #4261412864	; 0xfe000000
    47b4:	f8c2 3500 	str.w	r3, [r2, #1280]	; 0x500
    47b8:	f7ff ff48 	bl	464c <CC_HalMaskInterrupt>
    47bc:	683b      	ldr	r3, [r7, #0]
    47be:	e7d7      	b.n	4770 <CC_PalPowerSaveModeSelect+0x1c>
    47c0:	2000010c 	.word	0x2000010c
    47c4:	200000fc 	.word	0x200000fc
    47c8:	20000fa8 	.word	0x20000fa8
    47cc:	5002a000 	.word	0x5002a000
    47d0:	5002b000 	.word	0x5002b000
    47d4:	ffff8fe9 	.word	0xffff8fe9

000047d8 <mutex_free>:
    47d8:	b510      	push	{r4, lr}
    47da:	4604      	mov	r4, r0
    47dc:	b150      	cbz	r0, 47f4 <mutex_free+0x1c>
    47de:	6863      	ldr	r3, [r4, #4]
    47e0:	f013 5f68 	tst.w	r3, #973078528	; 0x3a000000
    47e4:	d005      	beq.n	47f2 <mutex_free+0x1a>
    47e6:	4a06      	ldr	r2, [pc, #24]	; (4800 <mutex_free+0x28>)
    47e8:	4293      	cmp	r3, r2
    47ea:	d002      	beq.n	47f2 <mutex_free+0x1a>
    47ec:	2300      	movs	r3, #0
    47ee:	6023      	str	r3, [r4, #0]
    47f0:	6062      	str	r2, [r4, #4]
    47f2:	bd10      	pop	{r4, pc}
    47f4:	4b03      	ldr	r3, [pc, #12]	; (4804 <mutex_free+0x2c>)
    47f6:	4804      	ldr	r0, [pc, #16]	; (4808 <mutex_free+0x30>)
    47f8:	685b      	ldr	r3, [r3, #4]
    47fa:	4798      	blx	r3
    47fc:	e7ef      	b.n	47de <mutex_free+0x6>
    47fe:	bf00      	nop
    4800:	a95c5f2c 	.word	0xa95c5f2c
    4804:	200000d8 	.word	0x200000d8
    4808:	00007428 	.word	0x00007428

0000480c <mutex_lock>:
    480c:	b1c8      	cbz	r0, 4842 <mutex_lock+0x36>
    480e:	6843      	ldr	r3, [r0, #4]
    4810:	4a0d      	ldr	r2, [pc, #52]	; (4848 <mutex_lock+0x3c>)
    4812:	4293      	cmp	r3, r2
    4814:	d013      	beq.n	483e <mutex_lock+0x32>
    4816:	f013 5f68 	tst.w	r3, #973078528	; 0x3a000000
    481a:	d00e      	beq.n	483a <mutex_lock+0x2e>
    481c:	2301      	movs	r3, #1
    481e:	e850 2f00 	ldrex	r2, [r0]
    4822:	4619      	mov	r1, r3
    4824:	e840 1c00 	strex	ip, r1, [r0]
    4828:	f09c 0f00 	teq	ip, #0
    482c:	d1f7      	bne.n	481e <mutex_lock+0x12>
    482e:	2a01      	cmp	r2, #1
    4830:	d0f5      	beq.n	481e <mutex_lock+0x12>
    4832:	f3bf 8f5f 	dmb	sy
    4836:	2000      	movs	r0, #0
    4838:	4770      	bx	lr
    483a:	4804      	ldr	r0, [pc, #16]	; (484c <mutex_lock+0x40>)
    483c:	4770      	bx	lr
    483e:	4804      	ldr	r0, [pc, #16]	; (4850 <mutex_lock+0x44>)
    4840:	4770      	bx	lr
    4842:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    4846:	4770      	bx	lr
    4848:	a95c5f2c 	.word	0xa95c5f2c
    484c:	ffff8fe9 	.word	0xffff8fe9
    4850:	ffff8fea 	.word	0xffff8fea

00004854 <mutex_unlock>:
    4854:	b180      	cbz	r0, 4878 <mutex_unlock+0x24>
    4856:	6843      	ldr	r3, [r0, #4]
    4858:	4a09      	ldr	r2, [pc, #36]	; (4880 <mutex_unlock+0x2c>)
    485a:	4293      	cmp	r3, r2
    485c:	d00a      	beq.n	4874 <mutex_unlock+0x20>
    485e:	f013 5f68 	tst.w	r3, #973078528	; 0x3a000000
    4862:	d005      	beq.n	4870 <mutex_unlock+0x1c>
    4864:	f3bf 8f5f 	dmb	sy
    4868:	2300      	movs	r3, #0
    486a:	6003      	str	r3, [r0, #0]
    486c:	4618      	mov	r0, r3
    486e:	4770      	bx	lr
    4870:	4804      	ldr	r0, [pc, #16]	; (4884 <mutex_unlock+0x30>)
    4872:	4770      	bx	lr
    4874:	4804      	ldr	r0, [pc, #16]	; (4888 <mutex_unlock+0x34>)
    4876:	4770      	bx	lr
    4878:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    487c:	4770      	bx	lr
    487e:	bf00      	nop
    4880:	a95c5f2c 	.word	0xa95c5f2c
    4884:	ffff8fe9 	.word	0xffff8fe9
    4888:	ffff8fea 	.word	0xffff8fea

0000488c <mutex_init>:
    488c:	b510      	push	{r4, lr}
    488e:	4604      	mov	r4, r0
    4890:	b120      	cbz	r0, 489c <mutex_init+0x10>
    4892:	4b04      	ldr	r3, [pc, #16]	; (48a4 <mutex_init+0x18>)
    4894:	6063      	str	r3, [r4, #4]
    4896:	2200      	movs	r2, #0
    4898:	6022      	str	r2, [r4, #0]
    489a:	bd10      	pop	{r4, pc}
    489c:	4802      	ldr	r0, [pc, #8]	; (48a8 <mutex_init+0x1c>)
    489e:	f7ff fe71 	bl	4584 <CC_PalAbort>
    48a2:	e7f6      	b.n	4892 <mutex_init+0x6>
    48a4:	3a00003a 	.word	0x3a00003a
    48a8:	00007450 	.word	0x00007450

000048ac <verify_context_ecdsa_verify_secp256r1>:
    48ac:	b130      	cbz	r0, 48bc <verify_context_ecdsa_verify_secp256r1+0x10>
    48ae:	6802      	ldr	r2, [r0, #0]
    48b0:	4b03      	ldr	r3, [pc, #12]	; (48c0 <verify_context_ecdsa_verify_secp256r1+0x14>)
    48b2:	4804      	ldr	r0, [pc, #16]	; (48c4 <verify_context_ecdsa_verify_secp256r1+0x18>)
    48b4:	429a      	cmp	r2, r3
    48b6:	bf08      	it	eq
    48b8:	2000      	moveq	r0, #0
    48ba:	4770      	bx	lr
    48bc:	4802      	ldr	r0, [pc, #8]	; (48c8 <verify_context_ecdsa_verify_secp256r1+0x1c>)
    48be:	4770      	bx	lr
    48c0:	bbaa55dd 	.word	0xbbaa55dd
    48c4:	00f00882 	.word	0x00f00882
    48c8:	00f00871 	.word	0x00f00871

000048cc <nrf_cc310_bl_ecdsa_verify_init_secp256r1>:
    48cc:	b538      	push	{r3, r4, r5, lr}
    48ce:	460d      	mov	r5, r1
    48d0:	4604      	mov	r4, r0
    48d2:	b1b0      	cbz	r0, 4902 <nrf_cc310_bl_ecdsa_verify_init_secp256r1+0x36>
    48d4:	22a0      	movs	r2, #160	; 0xa0
    48d6:	2100      	movs	r1, #0
    48d8:	3004      	adds	r0, #4
    48da:	f002 faf2 	bl	6ec2 <SaSi_PalMemSet>
    48de:	b195      	cbz	r5, 4906 <nrf_cc310_bl_ecdsa_verify_init_secp256r1+0x3a>
    48e0:	2208      	movs	r2, #8
    48e2:	4629      	mov	r1, r5
    48e4:	f104 0064 	add.w	r0, r4, #100	; 0x64
    48e8:	f002 faf1 	bl	6ece <CRYS_COMMON_ReverseMemcpy32>
    48ec:	2208      	movs	r2, #8
    48ee:	f105 0120 	add.w	r1, r5, #32
    48f2:	f104 0084 	add.w	r0, r4, #132	; 0x84
    48f6:	f002 faea 	bl	6ece <CRYS_COMMON_ReverseMemcpy32>
    48fa:	4b04      	ldr	r3, [pc, #16]	; (490c <nrf_cc310_bl_ecdsa_verify_init_secp256r1+0x40>)
    48fc:	6023      	str	r3, [r4, #0]
    48fe:	2000      	movs	r0, #0
    4900:	bd38      	pop	{r3, r4, r5, pc}
    4902:	4803      	ldr	r0, [pc, #12]	; (4910 <nrf_cc310_bl_ecdsa_verify_init_secp256r1+0x44>)
    4904:	e7fc      	b.n	4900 <nrf_cc310_bl_ecdsa_verify_init_secp256r1+0x34>
    4906:	4803      	ldr	r0, [pc, #12]	; (4914 <nrf_cc310_bl_ecdsa_verify_init_secp256r1+0x48>)
    4908:	e7fa      	b.n	4900 <nrf_cc310_bl_ecdsa_verify_init_secp256r1+0x34>
    490a:	bf00      	nop
    490c:	bbaa55dd 	.word	0xbbaa55dd
    4910:	00f00871 	.word	0x00f00871
    4914:	00f00883 	.word	0x00f00883

00004918 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1>:
    4918:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    491c:	4605      	mov	r5, r0
    491e:	460e      	mov	r6, r1
    4920:	4699      	mov	r9, r3
    4922:	4611      	mov	r1, r2
    4924:	f7ff ffc2 	bl	48ac <verify_context_ecdsa_verify_secp256r1>
    4928:	4604      	mov	r4, r0
    492a:	2800      	cmp	r0, #0
    492c:	f040 8084 	bne.w	4a38 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x120>
    4930:	2e00      	cmp	r6, #0
    4932:	f000 8085 	beq.w	4a40 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x128>
    4936:	2900      	cmp	r1, #0
    4938:	f000 8084 	beq.w	4a44 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x12c>
    493c:	f1b9 0f20 	cmp.w	r9, #32
    4940:	f040 8082 	bne.w	4a48 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x130>
    4944:	f105 0444 	add.w	r4, r5, #68	; 0x44
    4948:	2208      	movs	r2, #8
    494a:	f105 0804 	add.w	r8, r5, #4
    494e:	4620      	mov	r0, r4
    4950:	f002 fabd 	bl	6ece <CRYS_COMMON_ReverseMemcpy32>
    4954:	f105 0724 	add.w	r7, r5, #36	; 0x24
    4958:	2208      	movs	r2, #8
    495a:	4631      	mov	r1, r6
    495c:	4640      	mov	r0, r8
    495e:	f002 fab6 	bl	6ece <CRYS_COMMON_ReverseMemcpy32>
    4962:	f106 0120 	add.w	r1, r6, #32
    4966:	2208      	movs	r2, #8
    4968:	4638      	mov	r0, r7
    496a:	f002 fab0 	bl	6ece <CRYS_COMMON_ReverseMemcpy32>
    496e:	a902      	add	r1, sp, #8
    4970:	f44f 7080 	mov.w	r0, #256	; 0x100
    4974:	f841 9d04 	str.w	r9, [r1, #-4]!
    4978:	f002 fa9d 	bl	6eb6 <PkaInitAndMutexLock>
    497c:	2800      	cmp	r0, #0
    497e:	d165      	bne.n	4a4c <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x134>
    4980:	4a33      	ldr	r2, [pc, #204]	; (4a50 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x138>)
    4982:	f44f 7380 	mov.w	r3, #256	; 0x100
    4986:	6013      	str	r3, [r2, #0]
    4988:	2101      	movs	r1, #1
    498a:	6093      	str	r3, [r2, #8]
    498c:	2308      	movs	r3, #8
    498e:	4a31      	ldr	r2, [pc, #196]	; (4a54 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x13c>)
    4990:	f000 fb2e 	bl	4ff0 <PkaCopyDataIntoPkaReg>
    4994:	2101      	movs	r1, #1
    4996:	4608      	mov	r0, r1
    4998:	2305      	movs	r3, #5
    499a:	4a2f      	ldr	r2, [pc, #188]	; (4a58 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x140>)
    499c:	f000 fb28 	bl	4ff0 <PkaCopyDataIntoPkaReg>
    49a0:	2308      	movs	r3, #8
    49a2:	4642      	mov	r2, r8
    49a4:	2101      	movs	r1, #1
    49a6:	201c      	movs	r0, #28
    49a8:	f000 fb22 	bl	4ff0 <PkaCopyDataIntoPkaReg>
    49ac:	2308      	movs	r3, #8
    49ae:	463a      	mov	r2, r7
    49b0:	2101      	movs	r1, #1
    49b2:	2003      	movs	r0, #3
    49b4:	f000 fb1c 	bl	4ff0 <PkaCopyDataIntoPkaReg>
    49b8:	4622      	mov	r2, r4
    49ba:	2308      	movs	r3, #8
    49bc:	2101      	movs	r1, #1
    49be:	2002      	movs	r0, #2
    49c0:	f000 fb16 	bl	4ff0 <PkaCopyDataIntoPkaReg>
    49c4:	2308      	movs	r3, #8
    49c6:	4a25      	ldr	r2, [pc, #148]	; (4a5c <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x144>)
    49c8:	2101      	movs	r1, #1
    49ca:	201a      	movs	r0, #26
    49cc:	f000 fb10 	bl	4ff0 <PkaCopyDataIntoPkaReg>
    49d0:	2305      	movs	r3, #5
    49d2:	4a23      	ldr	r2, [pc, #140]	; (4a60 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x148>)
    49d4:	2101      	movs	r1, #1
    49d6:	201b      	movs	r0, #27
    49d8:	f000 fb0a 	bl	4ff0 <PkaCopyDataIntoPkaReg>
    49dc:	2308      	movs	r3, #8
    49de:	4a21      	ldr	r2, [pc, #132]	; (4a64 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x14c>)
    49e0:	2101      	movs	r1, #1
    49e2:	2014      	movs	r0, #20
    49e4:	f000 fb04 	bl	4ff0 <PkaCopyDataIntoPkaReg>
    49e8:	2308      	movs	r3, #8
    49ea:	4a1f      	ldr	r2, [pc, #124]	; (4a68 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x150>)
    49ec:	2101      	movs	r1, #1
    49ee:	2015      	movs	r0, #21
    49f0:	f000 fafe 	bl	4ff0 <PkaCopyDataIntoPkaReg>
    49f4:	2308      	movs	r3, #8
    49f6:	f105 0264 	add.w	r2, r5, #100	; 0x64
    49fa:	2101      	movs	r1, #1
    49fc:	2016      	movs	r0, #22
    49fe:	f000 faf7 	bl	4ff0 <PkaCopyDataIntoPkaReg>
    4a02:	2308      	movs	r3, #8
    4a04:	f105 0284 	add.w	r2, r5, #132	; 0x84
    4a08:	2101      	movs	r1, #1
    4a0a:	2017      	movs	r0, #23
    4a0c:	f000 faf0 	bl	4ff0 <PkaCopyDataIntoPkaReg>
    4a10:	2308      	movs	r3, #8
    4a12:	4a16      	ldr	r2, [pc, #88]	; (4a6c <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x154>)
    4a14:	2101      	movs	r1, #1
    4a16:	200b      	movs	r0, #11
    4a18:	f000 faea 	bl	4ff0 <PkaCopyDataIntoPkaReg>
    4a1c:	f000 fb44 	bl	50a8 <PkaEcdsaVerify>
    4a20:	4604      	mov	r4, r0
    4a22:	9801      	ldr	r0, [sp, #4]
    4a24:	f000 fad2 	bl	4fcc <PkaFinishAndMutexUnlock>
    4a28:	4b11      	ldr	r3, [pc, #68]	; (4a70 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x158>)
    4a2a:	2c00      	cmp	r4, #0
    4a2c:	bf18      	it	ne
    4a2e:	461c      	movne	r4, r3
    4a30:	21a4      	movs	r1, #164	; 0xa4
    4a32:	4628      	mov	r0, r5
    4a34:	f002 fa47 	bl	6ec6 <SaSi_PalMemSetZero>
    4a38:	4620      	mov	r0, r4
    4a3a:	b003      	add	sp, #12
    4a3c:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
    4a40:	4c0c      	ldr	r4, [pc, #48]	; (4a74 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x15c>)
    4a42:	e7f9      	b.n	4a38 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x120>
    4a44:	4c0c      	ldr	r4, [pc, #48]	; (4a78 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x160>)
    4a46:	e7f7      	b.n	4a38 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x120>
    4a48:	4c0c      	ldr	r4, [pc, #48]	; (4a7c <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x164>)
    4a4a:	e7f5      	b.n	4a38 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x120>
    4a4c:	4c08      	ldr	r4, [pc, #32]	; (4a70 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x158>)
    4a4e:	e7ef      	b.n	4a30 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1+0x118>
    4a50:	5002b090 	.word	0x5002b090
    4a54:	000074b4 	.word	0x000074b4
    4a58:	0000752c 	.word	0x0000752c
    4a5c:	00007474 	.word	0x00007474
    4a60:	00007518 	.word	0x00007518
    4a64:	000074d8 	.word	0x000074d8
    4a68:	000074f8 	.word	0x000074f8
    4a6c:	00007494 	.word	0x00007494
    4a70:	00f00884 	.word	0x00f00884
    4a74:	00f00876 	.word	0x00f00876
    4a78:	00f00880 	.word	0x00f00880
    4a7c:	00f00881 	.word	0x00f00881

00004a80 <set_digest_in_hw_sha256>:
    4a80:	4b0c      	ldr	r3, [pc, #48]	; (4ab4 <set_digest_in_hw_sha256+0x34>)
    4a82:	69c2      	ldr	r2, [r0, #28]
    4a84:	601a      	str	r2, [r3, #0]
    4a86:	6982      	ldr	r2, [r0, #24]
    4a88:	f843 2c04 	str.w	r2, [r3, #-4]
    4a8c:	6942      	ldr	r2, [r0, #20]
    4a8e:	f843 2c08 	str.w	r2, [r3, #-8]
    4a92:	6902      	ldr	r2, [r0, #16]
    4a94:	f843 2c0c 	str.w	r2, [r3, #-12]
    4a98:	68c2      	ldr	r2, [r0, #12]
    4a9a:	f843 2c10 	str.w	r2, [r3, #-16]
    4a9e:	6882      	ldr	r2, [r0, #8]
    4aa0:	f843 2c14 	str.w	r2, [r3, #-20]
    4aa4:	6842      	ldr	r2, [r0, #4]
    4aa6:	f843 2c18 	str.w	r2, [r3, #-24]
    4aaa:	6802      	ldr	r2, [r0, #0]
    4aac:	f843 2c1c 	str.w	r2, [r3, #-28]
    4ab0:	4770      	bx	lr
    4ab2:	bf00      	nop
    4ab4:	5002b65c 	.word	0x5002b65c

00004ab8 <read_digest_in_hw_sha256>:
    4ab8:	4b0c      	ldr	r3, [pc, #48]	; (4aec <read_digest_in_hw_sha256+0x34>)
    4aba:	681b      	ldr	r3, [r3, #0]
    4abc:	61c3      	str	r3, [r0, #28]
    4abe:	4b0c      	ldr	r3, [pc, #48]	; (4af0 <read_digest_in_hw_sha256+0x38>)
    4ac0:	681b      	ldr	r3, [r3, #0]
    4ac2:	6183      	str	r3, [r0, #24]
    4ac4:	4b0b      	ldr	r3, [pc, #44]	; (4af4 <read_digest_in_hw_sha256+0x3c>)
    4ac6:	681b      	ldr	r3, [r3, #0]
    4ac8:	6143      	str	r3, [r0, #20]
    4aca:	4b0b      	ldr	r3, [pc, #44]	; (4af8 <read_digest_in_hw_sha256+0x40>)
    4acc:	681b      	ldr	r3, [r3, #0]
    4ace:	6103      	str	r3, [r0, #16]
    4ad0:	4b0a      	ldr	r3, [pc, #40]	; (4afc <read_digest_in_hw_sha256+0x44>)
    4ad2:	681b      	ldr	r3, [r3, #0]
    4ad4:	60c3      	str	r3, [r0, #12]
    4ad6:	4b0a      	ldr	r3, [pc, #40]	; (4b00 <read_digest_in_hw_sha256+0x48>)
    4ad8:	681b      	ldr	r3, [r3, #0]
    4ada:	6083      	str	r3, [r0, #8]
    4adc:	4b09      	ldr	r3, [pc, #36]	; (4b04 <read_digest_in_hw_sha256+0x4c>)
    4ade:	681b      	ldr	r3, [r3, #0]
    4ae0:	6043      	str	r3, [r0, #4]
    4ae2:	4b09      	ldr	r3, [pc, #36]	; (4b08 <read_digest_in_hw_sha256+0x50>)
    4ae4:	681b      	ldr	r3, [r3, #0]
    4ae6:	6003      	str	r3, [r0, #0]
    4ae8:	4770      	bx	lr
    4aea:	bf00      	nop
    4aec:	5002b65c 	.word	0x5002b65c
    4af0:	5002b658 	.word	0x5002b658
    4af4:	5002b654 	.word	0x5002b654
    4af8:	5002b650 	.word	0x5002b650
    4afc:	5002b64c 	.word	0x5002b64c
    4b00:	5002b648 	.word	0x5002b648
    4b04:	5002b644 	.word	0x5002b644
    4b08:	5002b640 	.word	0x5002b640

00004b0c <verify_context_hash_sha256>:
    4b0c:	b130      	cbz	r0, 4b1c <verify_context_hash_sha256+0x10>
    4b0e:	6802      	ldr	r2, [r0, #0]
    4b10:	4b03      	ldr	r3, [pc, #12]	; (4b20 <verify_context_hash_sha256+0x14>)
    4b12:	4804      	ldr	r0, [pc, #16]	; (4b24 <verify_context_hash_sha256+0x18>)
    4b14:	429a      	cmp	r2, r3
    4b16:	bf08      	it	eq
    4b18:	2000      	moveq	r0, #0
    4b1a:	4770      	bx	lr
    4b1c:	4802      	ldr	r0, [pc, #8]	; (4b28 <verify_context_hash_sha256+0x1c>)
    4b1e:	4770      	bx	lr
    4b20:	bbaa55dd 	.word	0xbbaa55dd
    4b24:	00f00202 	.word	0x00f00202
    4b28:	00f00200 	.word	0x00f00200

00004b2c <nrf_cc310_bl_hash_sha256_init>:
    4b2c:	b538      	push	{r3, r4, r5, lr}
    4b2e:	4604      	mov	r4, r0
    4b30:	b168      	cbz	r0, 4b4e <nrf_cc310_bl_hash_sha256_init+0x22>
    4b32:	1d05      	adds	r5, r0, #4
    4b34:	2170      	movs	r1, #112	; 0x70
    4b36:	4628      	mov	r0, r5
    4b38:	f002 f9c5 	bl	6ec6 <SaSi_PalMemSetZero>
    4b3c:	4628      	mov	r0, r5
    4b3e:	2220      	movs	r2, #32
    4b40:	4904      	ldr	r1, [pc, #16]	; (4b54 <nrf_cc310_bl_hash_sha256_init+0x28>)
    4b42:	f002 f9bc 	bl	6ebe <SaSi_PalMemCopy>
    4b46:	4b04      	ldr	r3, [pc, #16]	; (4b58 <nrf_cc310_bl_hash_sha256_init+0x2c>)
    4b48:	6023      	str	r3, [r4, #0]
    4b4a:	2000      	movs	r0, #0
    4b4c:	bd38      	pop	{r3, r4, r5, pc}
    4b4e:	4803      	ldr	r0, [pc, #12]	; (4b5c <nrf_cc310_bl_hash_sha256_init+0x30>)
    4b50:	e7fc      	b.n	4b4c <nrf_cc310_bl_hash_sha256_init+0x20>
    4b52:	bf00      	nop
    4b54:	00007540 	.word	0x00007540
    4b58:	bbaa55dd 	.word	0xbbaa55dd
    4b5c:	00f00200 	.word	0x00f00200

00004b60 <nrf_cc310_bl_hash_sha256_update>:
    4b60:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
    4b64:	4b28      	ldr	r3, [pc, #160]	; (4c08 <nrf_cc310_bl_hash_sha256_update+0xa8>)
    4b66:	4604      	mov	r4, r0
    4b68:	460e      	mov	r6, r1
    4b6a:	4615      	mov	r5, r2
    4b6c:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
    4b6e:	b085      	sub	sp, #20
    4b70:	466f      	mov	r7, sp
    4b72:	e887 000f 	stmia.w	r7, {r0, r1, r2, r3}
    4b76:	b92d      	cbnz	r5, 4b84 <nrf_cc310_bl_hash_sha256_update+0x24>
    4b78:	f04f 0900 	mov.w	r9, #0
    4b7c:	4648      	mov	r0, r9
    4b7e:	b005      	add	sp, #20
    4b80:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
    4b84:	4620      	mov	r0, r4
    4b86:	f7ff ffc1 	bl	4b0c <verify_context_hash_sha256>
    4b8a:	4681      	mov	r9, r0
    4b8c:	2800      	cmp	r0, #0
    4b8e:	d1f5      	bne.n	4b7c <nrf_cc310_bl_hash_sha256_update+0x1c>
    4b90:	1d23      	adds	r3, r4, #4
    4b92:	9301      	str	r3, [sp, #4]
    4b94:	6a63      	ldr	r3, [r4, #36]	; 0x24
    4b96:	bba3      	cbnz	r3, 4c02 <nrf_cc310_bl_hash_sha256_update+0xa2>
    4b98:	6f23      	ldr	r3, [r4, #112]	; 0x70
    4b9a:	b18b      	cbz	r3, 4bc0 <nrf_cc310_bl_hash_sha256_update+0x60>
    4b9c:	f1c3 0840 	rsb	r8, r3, #64	; 0x40
    4ba0:	45a8      	cmp	r8, r5
    4ba2:	bf28      	it	cs
    4ba4:	46a8      	movcs	r8, r5
    4ba6:	f104 0030 	add.w	r0, r4, #48	; 0x30
    4baa:	4631      	mov	r1, r6
    4bac:	4418      	add	r0, r3
    4bae:	4642      	mov	r2, r8
    4bb0:	f002 f985 	bl	6ebe <SaSi_PalMemCopy>
    4bb4:	6f23      	ldr	r3, [r4, #112]	; 0x70
    4bb6:	4443      	add	r3, r8
    4bb8:	4446      	add	r6, r8
    4bba:	6723      	str	r3, [r4, #112]	; 0x70
    4bbc:	eba5 0508 	sub.w	r5, r5, r8
    4bc0:	6f22      	ldr	r2, [r4, #112]	; 0x70
    4bc2:	2a40      	cmp	r2, #64	; 0x40
    4bc4:	d106      	bne.n	4bd4 <nrf_cc310_bl_hash_sha256_update+0x74>
    4bc6:	f104 0130 	add.w	r1, r4, #48	; 0x30
    4bca:	4638      	mov	r0, r7
    4bcc:	f000 fbae 	bl	532c <nrf_cc310_bl_hash_update_internal>
    4bd0:	2300      	movs	r3, #0
    4bd2:	6723      	str	r3, [r4, #112]	; 0x70
    4bd4:	f005 083f 	and.w	r8, r5, #63	; 0x3f
    4bd8:	f035 053f 	bics.w	r5, r5, #63	; 0x3f
    4bdc:	d005      	beq.n	4bea <nrf_cc310_bl_hash_sha256_update+0x8a>
    4bde:	4631      	mov	r1, r6
    4be0:	462a      	mov	r2, r5
    4be2:	4638      	mov	r0, r7
    4be4:	f000 fba2 	bl	532c <nrf_cc310_bl_hash_update_internal>
    4be8:	442e      	add	r6, r5
    4bea:	f1b8 0f00 	cmp.w	r8, #0
    4bee:	d0c3      	beq.n	4b78 <nrf_cc310_bl_hash_sha256_update+0x18>
    4bf0:	4642      	mov	r2, r8
    4bf2:	4631      	mov	r1, r6
    4bf4:	f104 0030 	add.w	r0, r4, #48	; 0x30
    4bf8:	f002 f961 	bl	6ebe <SaSi_PalMemCopy>
    4bfc:	f8c4 8070 	str.w	r8, [r4, #112]	; 0x70
    4c00:	e7bc      	b.n	4b7c <nrf_cc310_bl_hash_sha256_update+0x1c>
    4c02:	f8df 9008 	ldr.w	r9, [pc, #8]	; 4c0c <nrf_cc310_bl_hash_sha256_update+0xac>
    4c06:	e7b9      	b.n	4b7c <nrf_cc310_bl_hash_sha256_update+0x1c>
    4c08:	000071d0 	.word	0x000071d0
    4c0c:	00f0020c 	.word	0x00f0020c

00004c10 <nrf_cc310_bl_hash_sha256_finalize>:
    4c10:	e92d 41ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr}
    4c14:	4b14      	ldr	r3, [pc, #80]	; (4c68 <nrf_cc310_bl_hash_sha256_finalize+0x58>)
    4c16:	4604      	mov	r4, r0
    4c18:	460e      	mov	r6, r1
    4c1a:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
    4c1c:	466f      	mov	r7, sp
    4c1e:	e887 000f 	stmia.w	r7, {r0, r1, r2, r3}
    4c22:	4620      	mov	r0, r4
    4c24:	f7ff ff72 	bl	4b0c <verify_context_hash_sha256>
    4c28:	4680      	mov	r8, r0
    4c2a:	b9b0      	cbnz	r0, 4c5a <nrf_cc310_bl_hash_sha256_finalize+0x4a>
    4c2c:	b1ce      	cbz	r6, 4c62 <nrf_cc310_bl_hash_sha256_finalize+0x52>
    4c2e:	6a63      	ldr	r3, [r4, #36]	; 0x24
    4c30:	1d25      	adds	r5, r4, #4
    4c32:	9501      	str	r5, [sp, #4]
    4c34:	b93b      	cbnz	r3, 4c46 <nrf_cc310_bl_hash_sha256_finalize+0x36>
    4c36:	2301      	movs	r3, #1
    4c38:	6263      	str	r3, [r4, #36]	; 0x24
    4c3a:	6f22      	ldr	r2, [r4, #112]	; 0x70
    4c3c:	f104 0130 	add.w	r1, r4, #48	; 0x30
    4c40:	4638      	mov	r0, r7
    4c42:	f000 fb73 	bl	532c <nrf_cc310_bl_hash_update_internal>
    4c46:	462b      	mov	r3, r5
    4c48:	3e04      	subs	r6, #4
    4c4a:	3424      	adds	r4, #36	; 0x24
    4c4c:	f853 2b04 	ldr.w	r2, [r3], #4
    4c50:	ba12      	rev	r2, r2
    4c52:	42a3      	cmp	r3, r4
    4c54:	f846 2f04 	str.w	r2, [r6, #4]!
    4c58:	d1f8      	bne.n	4c4c <nrf_cc310_bl_hash_sha256_finalize+0x3c>
    4c5a:	4640      	mov	r0, r8
    4c5c:	b004      	add	sp, #16
    4c5e:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    4c62:	f8df 8008 	ldr.w	r8, [pc, #8]	; 4c6c <nrf_cc310_bl_hash_sha256_finalize+0x5c>
    4c66:	e7f8      	b.n	4c5a <nrf_cc310_bl_hash_sha256_finalize+0x4a>
    4c68:	000071d0 	.word	0x000071d0
    4c6c:	00f00205 	.word	0x00f00205

00004c70 <nrf_cc310_bl_init>:
    4c70:	4b08      	ldr	r3, [pc, #32]	; (4c94 <nrf_cc310_bl_init+0x24>)
    4c72:	681b      	ldr	r3, [r3, #0]
    4c74:	0e1b      	lsrs	r3, r3, #24
    4c76:	2bf0      	cmp	r3, #240	; 0xf0
    4c78:	d108      	bne.n	4c8c <nrf_cc310_bl_init+0x1c>
    4c7a:	4b07      	ldr	r3, [pc, #28]	; (4c98 <nrf_cc310_bl_init+0x28>)
    4c7c:	681a      	ldr	r2, [r3, #0]
    4c7e:	4b07      	ldr	r3, [pc, #28]	; (4c9c <nrf_cc310_bl_init+0x2c>)
    4c80:	429a      	cmp	r2, r3
    4c82:	d105      	bne.n	4c90 <nrf_cc310_bl_init+0x20>
    4c84:	4b06      	ldr	r3, [pc, #24]	; (4ca0 <nrf_cc310_bl_init+0x30>)
    4c86:	2000      	movs	r0, #0
    4c88:	6018      	str	r0, [r3, #0]
    4c8a:	4770      	bx	lr
    4c8c:	2005      	movs	r0, #5
    4c8e:	4770      	bx	lr
    4c90:	2006      	movs	r0, #6
    4c92:	4770      	bx	lr
    4c94:	5002b928 	.word	0x5002b928
    4c98:	5002ba24 	.word	0x5002ba24
    4c9c:	20e00000 	.word	0x20e00000
    4ca0:	5002ba0c 	.word	0x5002ba0c

00004ca4 <PkaSetRegsMapTab>:
    4ca4:	2200      	movs	r2, #0
    4ca6:	b530      	push	{r4, r5, lr}
    4ca8:	0049      	lsls	r1, r1, #1
    4caa:	4613      	mov	r3, r2
    4cac:	3802      	subs	r0, #2
    4cae:	f640 75fc 	movw	r5, #4092	; 0xffc
    4cb2:	f102 54a0 	add.w	r4, r2, #335544320	; 0x14000000
    4cb6:	f504 442c 	add.w	r4, r4, #44032	; 0xac00
    4cba:	00a4      	lsls	r4, r4, #2
    4cbc:	4290      	cmp	r0, r2
    4cbe:	f102 0201 	add.w	r2, r2, #1
    4cc2:	bfca      	itet	gt
    4cc4:	6023      	strgt	r3, [r4, #0]
    4cc6:	6025      	strle	r5, [r4, #0]
    4cc8:	185b      	addgt	r3, r3, r1
    4cca:	2a1e      	cmp	r2, #30
    4ccc:	d1f1      	bne.n	4cb2 <PkaSetRegsMapTab+0xe>
    4cce:	4a04      	ldr	r2, [pc, #16]	; (4ce0 <PkaSetRegsMapTab+0x3c>)
    4cd0:	6013      	str	r3, [r2, #0]
    4cd2:	440b      	add	r3, r1
    4cd4:	6053      	str	r3, [r2, #4]
    4cd6:	4b03      	ldr	r3, [pc, #12]	; (4ce4 <PkaSetRegsMapTab+0x40>)
    4cd8:	4a03      	ldr	r2, [pc, #12]	; (4ce8 <PkaSetRegsMapTab+0x44>)
    4cda:	601a      	str	r2, [r3, #0]
    4cdc:	bd30      	pop	{r4, r5, pc}
    4cde:	bf00      	nop
    4ce0:	5002b078 	.word	0x5002b078
    4ce4:	5002b084 	.word	0x5002b084
    4ce8:	000ff820 	.word	0x000ff820

00004cec <PkaGetRegEffectiveSizeInBits>:
    4cec:	b530      	push	{r4, r5, lr}
    4cee:	4b1e      	ldr	r3, [pc, #120]	; (4d68 <PkaGetRegEffectiveSizeInBits+0x7c>)
    4cf0:	b085      	sub	sp, #20
    4cf2:	461a      	mov	r2, r3
    4cf4:	6819      	ldr	r1, [r3, #0]
    4cf6:	9100      	str	r1, [sp, #0]
    4cf8:	9900      	ldr	r1, [sp, #0]
    4cfa:	07cc      	lsls	r4, r1, #31
    4cfc:	d5fa      	bpl.n	4cf4 <PkaGetRegEffectiveSizeInBits+0x8>
    4cfe:	f100 50a0 	add.w	r0, r0, #335544320	; 0x14000000
    4d02:	f500 402c 	add.w	r0, r0, #44032	; 0xac00
    4d06:	0080      	lsls	r0, r0, #2
    4d08:	6801      	ldr	r1, [r0, #0]
    4d0a:	6813      	ldr	r3, [r2, #0]
    4d0c:	9301      	str	r3, [sp, #4]
    4d0e:	9b01      	ldr	r3, [sp, #4]
    4d10:	07d8      	lsls	r0, r3, #31
    4d12:	d5fa      	bpl.n	4d0a <PkaGetRegEffectiveSizeInBits+0x1e>
    4d14:	4b15      	ldr	r3, [pc, #84]	; (4d6c <PkaGetRegEffectiveSizeInBits+0x80>)
    4d16:	4c16      	ldr	r4, [pc, #88]	; (4d70 <PkaGetRegEffectiveSizeInBits+0x84>)
    4d18:	6818      	ldr	r0, [r3, #0]
    4d1a:	4d16      	ldr	r5, [pc, #88]	; (4d74 <PkaGetRegEffectiveSizeInBits+0x88>)
    4d1c:	301f      	adds	r0, #31
    4d1e:	2320      	movs	r3, #32
    4d20:	fb90 f0f3 	sdiv	r0, r0, r3
    4d24:	3801      	subs	r0, #1
    4d26:	2800      	cmp	r0, #0
    4d28:	da10      	bge.n	4d4c <PkaGetRegEffectiveSizeInBits+0x60>
    4d2a:	2300      	movs	r3, #0
    4d2c:	3001      	adds	r0, #1
    4d2e:	0140      	lsls	r0, r0, #5
    4d30:	b153      	cbz	r3, 4d48 <PkaGetRegEffectiveSizeInBits+0x5c>
    4d32:	f1a0 0120 	sub.w	r1, r0, #32
    4d36:	f04f 4200 	mov.w	r2, #2147483648	; 0x80000000
    4d3a:	4213      	tst	r3, r2
    4d3c:	d104      	bne.n	4d48 <PkaGetRegEffectiveSizeInBits+0x5c>
    4d3e:	3801      	subs	r0, #1
    4d40:	4288      	cmp	r0, r1
    4d42:	ea4f 0252 	mov.w	r2, r2, lsr #1
    4d46:	d1f8      	bne.n	4d3a <PkaGetRegEffectiveSizeInBits+0x4e>
    4d48:	b005      	add	sp, #20
    4d4a:	bd30      	pop	{r4, r5, pc}
    4d4c:	6813      	ldr	r3, [r2, #0]
    4d4e:	9303      	str	r3, [sp, #12]
    4d50:	9b03      	ldr	r3, [sp, #12]
    4d52:	07db      	lsls	r3, r3, #31
    4d54:	d5fa      	bpl.n	4d4c <PkaGetRegEffectiveSizeInBits+0x60>
    4d56:	1843      	adds	r3, r0, r1
    4d58:	6023      	str	r3, [r4, #0]
    4d5a:	682b      	ldr	r3, [r5, #0]
    4d5c:	9302      	str	r3, [sp, #8]
    4d5e:	9b02      	ldr	r3, [sp, #8]
    4d60:	2b00      	cmp	r3, #0
    4d62:	d1e3      	bne.n	4d2c <PkaGetRegEffectiveSizeInBits+0x40>
    4d64:	3801      	subs	r0, #1
    4d66:	e7de      	b.n	4d26 <PkaGetRegEffectiveSizeInBits+0x3a>
    4d68:	5002b0b4 	.word	0x5002b0b4
    4d6c:	5002b0ac 	.word	0x5002b0ac
    4d70:	5002b0e4 	.word	0x5002b0e4
    4d74:	5002b0dc 	.word	0x5002b0dc

00004d78 <PkaGetNextMsBit>:
    4d78:	b5f0      	push	{r4, r5, r6, r7, lr}
    4d7a:	681d      	ldr	r5, [r3, #0]
    4d7c:	b085      	sub	sp, #20
    4d7e:	f001 041f 	and.w	r4, r1, #31
    4d82:	b90d      	cbnz	r5, 4d88 <PkaGetNextMsBit+0x10>
    4d84:	2c1f      	cmp	r4, #31
    4d86:	d125      	bne.n	4dd4 <PkaGetNextMsBit+0x5c>
    4d88:	4d15      	ldr	r5, [pc, #84]	; (4de0 <PkaGetNextMsBit+0x68>)
    4d8a:	462e      	mov	r6, r5
    4d8c:	682f      	ldr	r7, [r5, #0]
    4d8e:	9701      	str	r7, [sp, #4]
    4d90:	9f01      	ldr	r7, [sp, #4]
    4d92:	07ff      	lsls	r7, r7, #31
    4d94:	d5fa      	bpl.n	4d8c <PkaGetNextMsBit+0x14>
    4d96:	f100 50a0 	add.w	r0, r0, #335544320	; 0x14000000
    4d9a:	f500 402c 	add.w	r0, r0, #44032	; 0xac00
    4d9e:	0080      	lsls	r0, r0, #2
    4da0:	6800      	ldr	r0, [r0, #0]
    4da2:	6835      	ldr	r5, [r6, #0]
    4da4:	9503      	str	r5, [sp, #12]
    4da6:	9d03      	ldr	r5, [sp, #12]
    4da8:	07ed      	lsls	r5, r5, #31
    4daa:	d5fa      	bpl.n	4da2 <PkaGetNextMsBit+0x2a>
    4dac:	4d0d      	ldr	r5, [pc, #52]	; (4de4 <PkaGetNextMsBit+0x6c>)
    4dae:	eb00 1061 	add.w	r0, r0, r1, asr #5
    4db2:	6028      	str	r0, [r5, #0]
    4db4:	480c      	ldr	r0, [pc, #48]	; (4de8 <PkaGetNextMsBit+0x70>)
    4db6:	6800      	ldr	r0, [r0, #0]
    4db8:	9002      	str	r0, [sp, #8]
    4dba:	2c1f      	cmp	r4, #31
    4dbc:	bf18      	it	ne
    4dbe:	43c9      	mvnne	r1, r1
    4dc0:	9802      	ldr	r0, [sp, #8]
    4dc2:	bf0f      	iteee	eq
    4dc4:	6010      	streq	r0, [r2, #0]
    4dc6:	f001 011f 	andne.w	r1, r1, #31
    4dca:	fa00 f101 	lslne.w	r1, r0, r1
    4dce:	6011      	strne	r1, [r2, #0]
    4dd0:	2100      	movs	r1, #0
    4dd2:	6019      	str	r1, [r3, #0]
    4dd4:	6810      	ldr	r0, [r2, #0]
    4dd6:	0043      	lsls	r3, r0, #1
    4dd8:	0fc0      	lsrs	r0, r0, #31
    4dda:	6013      	str	r3, [r2, #0]
    4ddc:	b005      	add	sp, #20
    4dde:	bdf0      	pop	{r4, r5, r6, r7, pc}
    4de0:	5002b0b4 	.word	0x5002b0b4
    4de4:	5002b0e4 	.word	0x5002b0e4
    4de8:	5002b0dc 	.word	0x5002b0dc

00004dec <PkaSetRegsSizesTab>:
    4dec:	4b0c      	ldr	r3, [pc, #48]	; (4e20 <PkaSetRegsSizesTab+0x34>)
    4dee:	6018      	str	r0, [r3, #0]
    4df0:	303f      	adds	r0, #63	; 0x3f
    4df2:	f020 003f 	bic.w	r0, r0, #63	; 0x3f
    4df6:	0189      	lsls	r1, r1, #6
    4df8:	3040      	adds	r0, #64	; 0x40
    4dfa:	6058      	str	r0, [r3, #4]
    4dfc:	6099      	str	r1, [r3, #8]
    4dfe:	60d9      	str	r1, [r3, #12]
    4e00:	6119      	str	r1, [r3, #16]
    4e02:	6159      	str	r1, [r3, #20]
    4e04:	6199      	str	r1, [r3, #24]
    4e06:	331c      	adds	r3, #28
    4e08:	4806      	ldr	r0, [pc, #24]	; (4e24 <PkaSetRegsSizesTab+0x38>)
    4e0a:	6019      	str	r1, [r3, #0]
    4e0c:	b082      	sub	sp, #8
    4e0e:	6802      	ldr	r2, [r0, #0]
    4e10:	9201      	str	r2, [sp, #4]
    4e12:	9a01      	ldr	r2, [sp, #4]
    4e14:	07d2      	lsls	r2, r2, #31
    4e16:	d5fa      	bpl.n	4e0e <PkaSetRegsSizesTab+0x22>
    4e18:	6019      	str	r1, [r3, #0]
    4e1a:	b002      	add	sp, #8
    4e1c:	4770      	bx	lr
    4e1e:	bf00      	nop
    4e20:	5002b090 	.word	0x5002b090
    4e24:	5002b0b4 	.word	0x5002b0b4

00004e28 <PkaInitPka>:
    4e28:	b538      	push	{r3, r4, r5, lr}
    4e2a:	f1a0 0320 	sub.w	r3, r0, #32
    4e2e:	f5b3 6f42 	cmp.w	r3, #3104	; 0xc20
    4e32:	4605      	mov	r5, r0
    4e34:	d82c      	bhi.n	4e90 <PkaInitPka+0x68>
    4e36:	288f      	cmp	r0, #143	; 0x8f
    4e38:	d826      	bhi.n	4e88 <PkaInitPka+0x60>
    4e3a:	f100 0347 	add.w	r3, r0, #71	; 0x47
    4e3e:	f100 0466 	add.w	r4, r0, #102	; 0x66
    4e42:	06db      	lsls	r3, r3, #27
    4e44:	ea4f 1454 	mov.w	r4, r4, lsr #5
    4e48:	d000      	beq.n	4e4c <PkaInitPka+0x24>
    4e4a:	3401      	adds	r4, #1
    4e4c:	0164      	lsls	r4, r4, #5
    4e4e:	343f      	adds	r4, #63	; 0x3f
    4e50:	09a4      	lsrs	r4, r4, #6
    4e52:	3401      	adds	r4, #1
    4e54:	b111      	cbz	r1, 4e5c <PkaInitPka+0x34>
    4e56:	42a1      	cmp	r1, r4
    4e58:	d31a      	bcc.n	4e90 <PkaInitPka+0x68>
    4e5a:	460c      	mov	r4, r1
    4e5c:	00e3      	lsls	r3, r4, #3
    4e5e:	f44f 5080 	mov.w	r0, #4096	; 0x1000
    4e62:	fbb0 f0f3 	udiv	r0, r0, r3
    4e66:	2820      	cmp	r0, #32
    4e68:	bf28      	it	cs
    4e6a:	2020      	movcs	r0, #32
    4e6c:	b102      	cbz	r2, 4e70 <PkaInitPka+0x48>
    4e6e:	6010      	str	r0, [r2, #0]
    4e70:	4b08      	ldr	r3, [pc, #32]	; (4e94 <PkaInitPka+0x6c>)
    4e72:	2201      	movs	r2, #1
    4e74:	601a      	str	r2, [r3, #0]
    4e76:	4621      	mov	r1, r4
    4e78:	f7ff ff14 	bl	4ca4 <PkaSetRegsMapTab>
    4e7c:	4628      	mov	r0, r5
    4e7e:	4621      	mov	r1, r4
    4e80:	f7ff ffb4 	bl	4dec <PkaSetRegsSizesTab>
    4e84:	2000      	movs	r0, #0
    4e86:	bd38      	pop	{r3, r4, r5, pc}
    4e88:	f100 041f 	add.w	r4, r0, #31
    4e8c:	0964      	lsrs	r4, r4, #5
    4e8e:	e7dd      	b.n	4e4c <PkaInitPka+0x24>
    4e90:	4801      	ldr	r0, [pc, #4]	; (4e98 <PkaInitPka+0x70>)
    4e92:	e7f8      	b.n	4e86 <PkaInitPka+0x5e>
    4e94:	5002b81c 	.word	0x5002b81c
    4e98:	00f02122 	.word	0x00f02122

00004e9c <PkaClearBlockOfRegs>:
    4e9c:	b5f0      	push	{r4, r5, r6, r7, lr}
    4e9e:	4b45      	ldr	r3, [pc, #276]	; (4fb4 <PkaClearBlockOfRegs+0x118>)
    4ea0:	b089      	sub	sp, #36	; 0x24
    4ea2:	461d      	mov	r5, r3
    4ea4:	681c      	ldr	r4, [r3, #0]
    4ea6:	9401      	str	r4, [sp, #4]
    4ea8:	9c01      	ldr	r4, [sp, #4]
    4eaa:	07e4      	lsls	r4, r4, #31
    4eac:	d5fa      	bpl.n	4ea4 <PkaClearBlockOfRegs+0x8>
    4eae:	4b42      	ldr	r3, [pc, #264]	; (4fb8 <PkaClearBlockOfRegs+0x11c>)
    4eb0:	f8df e10c 	ldr.w	lr, [pc, #268]	; 4fc0 <PkaClearBlockOfRegs+0x124>
    4eb4:	f8df c10c 	ldr.w	ip, [pc, #268]	; 4fc4 <PkaClearBlockOfRegs+0x128>
    4eb8:	4413      	add	r3, r2
    4eba:	009b      	lsls	r3, r3, #2
    4ebc:	2400      	movs	r4, #0
    4ebe:	681a      	ldr	r2, [r3, #0]
    4ec0:	180b      	adds	r3, r1, r0
    4ec2:	2b1e      	cmp	r3, #30
    4ec4:	bf88      	it	hi
    4ec6:	f1c0 011e 	rsbhi	r1, r0, #30
    4eca:	321f      	adds	r2, #31
    4ecc:	180b      	adds	r3, r1, r0
    4ece:	0952      	lsrs	r2, r2, #5
    4ed0:	4353      	muls	r3, r2
    4ed2:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
    4ed6:	bf82      	ittt	hi
    4ed8:	f44f 6180 	movhi.w	r1, #1024	; 0x400
    4edc:	fbb1 f1f2 	udivhi	r1, r1, r2
    4ee0:	1a09      	subhi	r1, r1, r0
    4ee2:	f100 50a0 	add.w	r0, r0, #335544320	; 0x14000000
    4ee6:	f500 402c 	add.w	r0, r0, #44032	; 0xac00
    4eea:	4627      	mov	r7, r4
    4eec:	42a1      	cmp	r1, r4
    4eee:	dc33      	bgt.n	4f58 <PkaClearBlockOfRegs+0xbc>
    4ef0:	682b      	ldr	r3, [r5, #0]
    4ef2:	9304      	str	r3, [sp, #16]
    4ef4:	9b04      	ldr	r3, [sp, #16]
    4ef6:	07db      	lsls	r3, r3, #31
    4ef8:	d5fa      	bpl.n	4ef0 <PkaClearBlockOfRegs+0x54>
    4efa:	4b30      	ldr	r3, [pc, #192]	; (4fbc <PkaClearBlockOfRegs+0x120>)
    4efc:	681b      	ldr	r3, [r3, #0]
    4efe:	6829      	ldr	r1, [r5, #0]
    4f00:	9105      	str	r1, [sp, #20]
    4f02:	9905      	ldr	r1, [sp, #20]
    4f04:	07cf      	lsls	r7, r1, #31
    4f06:	d5fa      	bpl.n	4efe <PkaClearBlockOfRegs+0x62>
    4f08:	4c2d      	ldr	r4, [pc, #180]	; (4fc0 <PkaClearBlockOfRegs+0x124>)
    4f0a:	492e      	ldr	r1, [pc, #184]	; (4fc4 <PkaClearBlockOfRegs+0x128>)
    4f0c:	6023      	str	r3, [r4, #0]
    4f0e:	2300      	movs	r3, #0
    4f10:	461e      	mov	r6, r3
    4f12:	4293      	cmp	r3, r2
    4f14:	f103 0001 	add.w	r0, r3, #1
    4f18:	d140      	bne.n	4f9c <PkaClearBlockOfRegs+0x100>
    4f1a:	f020 0201 	bic.w	r2, r0, #1
    4f1e:	4829      	ldr	r0, [pc, #164]	; (4fc4 <PkaClearBlockOfRegs+0x128>)
    4f20:	4619      	mov	r1, r3
    4f22:	2600      	movs	r6, #0
    4f24:	428a      	cmp	r2, r1
    4f26:	d83c      	bhi.n	4fa2 <PkaClearBlockOfRegs+0x106>
    4f28:	6829      	ldr	r1, [r5, #0]
    4f2a:	9106      	str	r1, [sp, #24]
    4f2c:	9906      	ldr	r1, [sp, #24]
    4f2e:	07ce      	lsls	r6, r1, #31
    4f30:	d5fa      	bpl.n	4f28 <PkaClearBlockOfRegs+0x8c>
    4f32:	4925      	ldr	r1, [pc, #148]	; (4fc8 <PkaClearBlockOfRegs+0x12c>)
    4f34:	6809      	ldr	r1, [r1, #0]
    4f36:	6828      	ldr	r0, [r5, #0]
    4f38:	9007      	str	r0, [sp, #28]
    4f3a:	9807      	ldr	r0, [sp, #28]
    4f3c:	07c0      	lsls	r0, r0, #31
    4f3e:	d5fa      	bpl.n	4f36 <PkaClearBlockOfRegs+0x9a>
    4f40:	6021      	str	r1, [r4, #0]
    4f42:	4820      	ldr	r0, [pc, #128]	; (4fc4 <PkaClearBlockOfRegs+0x128>)
    4f44:	2100      	movs	r1, #0
    4f46:	460c      	mov	r4, r1
    4f48:	428b      	cmp	r3, r1
    4f4a:	d12d      	bne.n	4fa8 <PkaClearBlockOfRegs+0x10c>
    4f4c:	491d      	ldr	r1, [pc, #116]	; (4fc4 <PkaClearBlockOfRegs+0x128>)
    4f4e:	2000      	movs	r0, #0
    4f50:	429a      	cmp	r2, r3
    4f52:	d82c      	bhi.n	4fae <PkaClearBlockOfRegs+0x112>
    4f54:	b009      	add	sp, #36	; 0x24
    4f56:	bdf0      	pop	{r4, r5, r6, r7, pc}
    4f58:	682b      	ldr	r3, [r5, #0]
    4f5a:	9302      	str	r3, [sp, #8]
    4f5c:	9b02      	ldr	r3, [sp, #8]
    4f5e:	07db      	lsls	r3, r3, #31
    4f60:	d5fa      	bpl.n	4f58 <PkaClearBlockOfRegs+0xbc>
    4f62:	1903      	adds	r3, r0, r4
    4f64:	009b      	lsls	r3, r3, #2
    4f66:	681b      	ldr	r3, [r3, #0]
    4f68:	682e      	ldr	r6, [r5, #0]
    4f6a:	9603      	str	r6, [sp, #12]
    4f6c:	9e03      	ldr	r6, [sp, #12]
    4f6e:	07f6      	lsls	r6, r6, #31
    4f70:	d5fa      	bpl.n	4f68 <PkaClearBlockOfRegs+0xcc>
    4f72:	f8ce 3000 	str.w	r3, [lr]
    4f76:	2300      	movs	r3, #0
    4f78:	4293      	cmp	r3, r2
    4f7a:	f103 0301 	add.w	r3, r3, #1
    4f7e:	d106      	bne.n	4f8e <PkaClearBlockOfRegs+0xf2>
    4f80:	4616      	mov	r6, r2
    4f82:	f023 0301 	bic.w	r3, r3, #1
    4f86:	42b3      	cmp	r3, r6
    4f88:	d804      	bhi.n	4f94 <PkaClearBlockOfRegs+0xf8>
    4f8a:	3401      	adds	r4, #1
    4f8c:	e7ae      	b.n	4eec <PkaClearBlockOfRegs+0x50>
    4f8e:	f8cc 7000 	str.w	r7, [ip]
    4f92:	e7f1      	b.n	4f78 <PkaClearBlockOfRegs+0xdc>
    4f94:	f8cc 7000 	str.w	r7, [ip]
    4f98:	3601      	adds	r6, #1
    4f9a:	e7f4      	b.n	4f86 <PkaClearBlockOfRegs+0xea>
    4f9c:	600e      	str	r6, [r1, #0]
    4f9e:	4603      	mov	r3, r0
    4fa0:	e7b7      	b.n	4f12 <PkaClearBlockOfRegs+0x76>
    4fa2:	6006      	str	r6, [r0, #0]
    4fa4:	3101      	adds	r1, #1
    4fa6:	e7bd      	b.n	4f24 <PkaClearBlockOfRegs+0x88>
    4fa8:	6004      	str	r4, [r0, #0]
    4faa:	3101      	adds	r1, #1
    4fac:	e7cc      	b.n	4f48 <PkaClearBlockOfRegs+0xac>
    4fae:	6008      	str	r0, [r1, #0]
    4fb0:	3301      	adds	r3, #1
    4fb2:	e7cd      	b.n	4f50 <PkaClearBlockOfRegs+0xb4>
    4fb4:	5002b0b4 	.word	0x5002b0b4
    4fb8:	1400ac24 	.word	0x1400ac24
    4fbc:	5002b07c 	.word	0x5002b07c
    4fc0:	5002b0d4 	.word	0x5002b0d4
    4fc4:	5002b0d8 	.word	0x5002b0d8
    4fc8:	5002b078 	.word	0x5002b078

00004fcc <PkaFinishAndMutexUnlock>:
    4fcc:	b508      	push	{r3, lr}
    4fce:	b140      	cbz	r0, 4fe2 <PkaFinishAndMutexUnlock+0x16>
    4fd0:	2820      	cmp	r0, #32
    4fd2:	4601      	mov	r1, r0
    4fd4:	f04f 0207 	mov.w	r2, #7
    4fd8:	bf28      	it	cs
    4fda:	2120      	movcs	r1, #32
    4fdc:	2000      	movs	r0, #0
    4fde:	f7ff ff5d 	bl	4e9c <PkaClearBlockOfRegs>
    4fe2:	4b02      	ldr	r3, [pc, #8]	; (4fec <PkaFinishAndMutexUnlock+0x20>)
    4fe4:	2200      	movs	r2, #0
    4fe6:	601a      	str	r2, [r3, #0]
    4fe8:	bd08      	pop	{r3, pc}
    4fea:	bf00      	nop
    4fec:	5002b81c 	.word	0x5002b81c

00004ff0 <PkaCopyDataIntoPkaReg>:
    4ff0:	b5f0      	push	{r4, r5, r6, r7, lr}
    4ff2:	4d29      	ldr	r5, [pc, #164]	; (5098 <PkaCopyDataIntoPkaReg+0xa8>)
    4ff4:	b085      	sub	sp, #20
    4ff6:	462c      	mov	r4, r5
    4ff8:	682e      	ldr	r6, [r5, #0]
    4ffa:	9600      	str	r6, [sp, #0]
    4ffc:	9e00      	ldr	r6, [sp, #0]
    4ffe:	07f6      	lsls	r6, r6, #31
    5000:	d5fa      	bpl.n	4ff8 <PkaCopyDataIntoPkaReg+0x8>
    5002:	f100 50a0 	add.w	r0, r0, #335544320	; 0x14000000
    5006:	f500 402c 	add.w	r0, r0, #44032	; 0xac00
    500a:	0080      	lsls	r0, r0, #2
    500c:	6805      	ldr	r5, [r0, #0]
    500e:	6820      	ldr	r0, [r4, #0]
    5010:	9001      	str	r0, [sp, #4]
    5012:	9801      	ldr	r0, [sp, #4]
    5014:	07c7      	lsls	r7, r0, #31
    5016:	d5fa      	bpl.n	500e <PkaCopyDataIntoPkaReg+0x1e>
    5018:	4820      	ldr	r0, [pc, #128]	; (509c <PkaCopyDataIntoPkaReg+0xac>)
    501a:	4f21      	ldr	r7, [pc, #132]	; (50a0 <PkaCopyDataIntoPkaReg+0xb0>)
    501c:	6005      	str	r5, [r0, #0]
    501e:	eb02 0683 	add.w	r6, r2, r3, lsl #2
    5022:	42b2      	cmp	r2, r6
    5024:	d129      	bne.n	507a <PkaCopyDataIntoPkaReg+0x8a>
    5026:	1c5a      	adds	r2, r3, #1
    5028:	4e1d      	ldr	r6, [pc, #116]	; (50a0 <PkaCopyDataIntoPkaReg+0xb0>)
    502a:	f022 0201 	bic.w	r2, r2, #1
    502e:	2700      	movs	r7, #0
    5030:	429a      	cmp	r2, r3
    5032:	d827      	bhi.n	5084 <PkaCopyDataIntoPkaReg+0x94>
    5034:	6823      	ldr	r3, [r4, #0]
    5036:	9302      	str	r3, [sp, #8]
    5038:	9b02      	ldr	r3, [sp, #8]
    503a:	07de      	lsls	r6, r3, #31
    503c:	d5fa      	bpl.n	5034 <PkaCopyDataIntoPkaReg+0x44>
    503e:	4b19      	ldr	r3, [pc, #100]	; (50a4 <PkaCopyDataIntoPkaReg+0xb4>)
    5040:	440b      	add	r3, r1
    5042:	009b      	lsls	r3, r3, #2
    5044:	681b      	ldr	r3, [r3, #0]
    5046:	331f      	adds	r3, #31
    5048:	095b      	lsrs	r3, r3, #5
    504a:	429a      	cmp	r2, r3
    504c:	d213      	bcs.n	5076 <PkaCopyDataIntoPkaReg+0x86>
    504e:	6821      	ldr	r1, [r4, #0]
    5050:	9103      	str	r1, [sp, #12]
    5052:	9903      	ldr	r1, [sp, #12]
    5054:	07c9      	lsls	r1, r1, #31
    5056:	d5fa      	bpl.n	504e <PkaCopyDataIntoPkaReg+0x5e>
    5058:	4415      	add	r5, r2
    505a:	2100      	movs	r1, #0
    505c:	1a9b      	subs	r3, r3, r2
    505e:	4a10      	ldr	r2, [pc, #64]	; (50a0 <PkaCopyDataIntoPkaReg+0xb0>)
    5060:	6005      	str	r5, [r0, #0]
    5062:	4608      	mov	r0, r1
    5064:	428b      	cmp	r3, r1
    5066:	d810      	bhi.n	508a <PkaCopyDataIntoPkaReg+0x9a>
    5068:	1c5a      	adds	r2, r3, #1
    506a:	490d      	ldr	r1, [pc, #52]	; (50a0 <PkaCopyDataIntoPkaReg+0xb0>)
    506c:	f022 0201 	bic.w	r2, r2, #1
    5070:	2000      	movs	r0, #0
    5072:	429a      	cmp	r2, r3
    5074:	d80c      	bhi.n	5090 <PkaCopyDataIntoPkaReg+0xa0>
    5076:	b005      	add	sp, #20
    5078:	bdf0      	pop	{r4, r5, r6, r7, pc}
    507a:	f852 cb04 	ldr.w	ip, [r2], #4
    507e:	f8c7 c000 	str.w	ip, [r7]
    5082:	e7ce      	b.n	5022 <PkaCopyDataIntoPkaReg+0x32>
    5084:	6037      	str	r7, [r6, #0]
    5086:	3301      	adds	r3, #1
    5088:	e7d2      	b.n	5030 <PkaCopyDataIntoPkaReg+0x40>
    508a:	6010      	str	r0, [r2, #0]
    508c:	3101      	adds	r1, #1
    508e:	e7e9      	b.n	5064 <PkaCopyDataIntoPkaReg+0x74>
    5090:	6008      	str	r0, [r1, #0]
    5092:	3301      	adds	r3, #1
    5094:	e7ed      	b.n	5072 <PkaCopyDataIntoPkaReg+0x82>
    5096:	bf00      	nop
    5098:	5002b0b4 	.word	0x5002b0b4
    509c:	5002b0d4 	.word	0x5002b0d4
    50a0:	5002b0d8 	.word	0x5002b0d8
    50a4:	1400ac24 	.word	0x1400ac24

000050a8 <PkaEcdsaVerify>:
    50a8:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    50ac:	4b81      	ldr	r3, [pc, #516]	; (52b4 <PkaEcdsaVerify+0x20c>)
    50ae:	681d      	ldr	r5, [r3, #0]
    50b0:	6898      	ldr	r0, [r3, #8]
    50b2:	3320      	adds	r3, #32
    50b4:	b0a0      	sub	sp, #128	; 0x80
    50b6:	461e      	mov	r6, r3
    50b8:	681a      	ldr	r2, [r3, #0]
    50ba:	9201      	str	r2, [sp, #4]
    50bc:	9a01      	ldr	r2, [sp, #4]
    50be:	07d7      	lsls	r7, r2, #31
    50c0:	d5fa      	bpl.n	50b8 <PkaEcdsaVerify+0x10>
    50c2:	4b7d      	ldr	r3, [pc, #500]	; (52b8 <PkaEcdsaVerify+0x210>)
    50c4:	4a7d      	ldr	r2, [pc, #500]	; (52bc <PkaEcdsaVerify+0x214>)
    50c6:	601a      	str	r2, [r3, #0]
    50c8:	6832      	ldr	r2, [r6, #0]
    50ca:	9202      	str	r2, [sp, #8]
    50cc:	9a02      	ldr	r2, [sp, #8]
    50ce:	07d4      	lsls	r4, r2, #31
    50d0:	d5fa      	bpl.n	50c8 <PkaEcdsaVerify+0x20>
    50d2:	4a7b      	ldr	r2, [pc, #492]	; (52c0 <PkaEcdsaVerify+0x218>)
    50d4:	601a      	str	r2, [r3, #0]
    50d6:	4a7b      	ldr	r2, [pc, #492]	; (52c4 <PkaEcdsaVerify+0x21c>)
    50d8:	4614      	mov	r4, r2
    50da:	6811      	ldr	r1, [r2, #0]
    50dc:	9103      	str	r1, [sp, #12]
    50de:	9903      	ldr	r1, [sp, #12]
    50e0:	07c9      	lsls	r1, r1, #31
    50e2:	d5fa      	bpl.n	50da <PkaEcdsaVerify+0x32>
    50e4:	4a78      	ldr	r2, [pc, #480]	; (52c8 <PkaEcdsaVerify+0x220>)
    50e6:	6811      	ldr	r1, [r2, #0]
    50e8:	f3c1 2140 	ubfx	r1, r1, #9, #1
    50ec:	6837      	ldr	r7, [r6, #0]
    50ee:	9704      	str	r7, [sp, #16]
    50f0:	9f04      	ldr	r7, [sp, #16]
    50f2:	07ff      	lsls	r7, r7, #31
    50f4:	d5fa      	bpl.n	50ec <PkaEcdsaVerify+0x44>
    50f6:	4f75      	ldr	r7, [pc, #468]	; (52cc <PkaEcdsaVerify+0x224>)
    50f8:	601f      	str	r7, [r3, #0]
    50fa:	6827      	ldr	r7, [r4, #0]
    50fc:	9705      	str	r7, [sp, #20]
    50fe:	9f05      	ldr	r7, [sp, #20]
    5100:	07ff      	lsls	r7, r7, #31
    5102:	d5fa      	bpl.n	50fa <PkaEcdsaVerify+0x52>
    5104:	6817      	ldr	r7, [r2, #0]
    5106:	2900      	cmp	r1, #0
    5108:	f000 80cf 	beq.w	52aa <PkaEcdsaVerify+0x202>
    510c:	05b9      	lsls	r1, r7, #22
    510e:	f140 80cc 	bpl.w	52aa <PkaEcdsaVerify+0x202>
    5112:	6831      	ldr	r1, [r6, #0]
    5114:	9106      	str	r1, [sp, #24]
    5116:	9906      	ldr	r1, [sp, #24]
    5118:	07cf      	lsls	r7, r1, #31
    511a:	d5fa      	bpl.n	5112 <PkaEcdsaVerify+0x6a>
    511c:	496c      	ldr	r1, [pc, #432]	; (52d0 <PkaEcdsaVerify+0x228>)
    511e:	6019      	str	r1, [r3, #0]
    5120:	6821      	ldr	r1, [r4, #0]
    5122:	9107      	str	r1, [sp, #28]
    5124:	9907      	ldr	r1, [sp, #28]
    5126:	07c9      	lsls	r1, r1, #31
    5128:	d5fa      	bpl.n	5120 <PkaEcdsaVerify+0x78>
    512a:	6811      	ldr	r1, [r2, #0]
    512c:	f3c1 2140 	ubfx	r1, r1, #9, #1
    5130:	6837      	ldr	r7, [r6, #0]
    5132:	9708      	str	r7, [sp, #32]
    5134:	9f08      	ldr	r7, [sp, #32]
    5136:	07ff      	lsls	r7, r7, #31
    5138:	d5fa      	bpl.n	5130 <PkaEcdsaVerify+0x88>
    513a:	4f66      	ldr	r7, [pc, #408]	; (52d4 <PkaEcdsaVerify+0x22c>)
    513c:	601f      	str	r7, [r3, #0]
    513e:	6827      	ldr	r7, [r4, #0]
    5140:	9709      	str	r7, [sp, #36]	; 0x24
    5142:	9f09      	ldr	r7, [sp, #36]	; 0x24
    5144:	07ff      	lsls	r7, r7, #31
    5146:	d5fa      	bpl.n	513e <PkaEcdsaVerify+0x96>
    5148:	6812      	ldr	r2, [r2, #0]
    514a:	2900      	cmp	r1, #0
    514c:	f000 80af 	beq.w	52ae <PkaEcdsaVerify+0x206>
    5150:	0591      	lsls	r1, r2, #22
    5152:	f140 80ac 	bpl.w	52ae <PkaEcdsaVerify+0x206>
    5156:	6832      	ldr	r2, [r6, #0]
    5158:	920a      	str	r2, [sp, #40]	; 0x28
    515a:	9a0a      	ldr	r2, [sp, #40]	; 0x28
    515c:	07d2      	lsls	r2, r2, #31
    515e:	d5fa      	bpl.n	5156 <PkaEcdsaVerify+0xae>
    5160:	4a56      	ldr	r2, [pc, #344]	; (52bc <PkaEcdsaVerify+0x214>)
    5162:	601a      	str	r2, [r3, #0]
    5164:	6832      	ldr	r2, [r6, #0]
    5166:	920b      	str	r2, [sp, #44]	; 0x2c
    5168:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
    516a:	07d7      	lsls	r7, r2, #31
    516c:	d5fa      	bpl.n	5164 <PkaEcdsaVerify+0xbc>
    516e:	4a5a      	ldr	r2, [pc, #360]	; (52d8 <PkaEcdsaVerify+0x230>)
    5170:	601a      	str	r2, [r3, #0]
    5172:	6831      	ldr	r1, [r6, #0]
    5174:	910c      	str	r1, [sp, #48]	; 0x30
    5176:	990c      	ldr	r1, [sp, #48]	; 0x30
    5178:	07cc      	lsls	r4, r1, #31
    517a:	d5fa      	bpl.n	5172 <PkaEcdsaVerify+0xca>
    517c:	4957      	ldr	r1, [pc, #348]	; (52dc <PkaEcdsaVerify+0x234>)
    517e:	6019      	str	r1, [r3, #0]
    5180:	6831      	ldr	r1, [r6, #0]
    5182:	910d      	str	r1, [sp, #52]	; 0x34
    5184:	990d      	ldr	r1, [sp, #52]	; 0x34
    5186:	07c9      	lsls	r1, r1, #31
    5188:	d5fa      	bpl.n	5180 <PkaEcdsaVerify+0xd8>
    518a:	4955      	ldr	r1, [pc, #340]	; (52e0 <PkaEcdsaVerify+0x238>)
    518c:	6019      	str	r1, [r3, #0]
    518e:	6831      	ldr	r1, [r6, #0]
    5190:	910e      	str	r1, [sp, #56]	; 0x38
    5192:	990e      	ldr	r1, [sp, #56]	; 0x38
    5194:	07cf      	lsls	r7, r1, #31
    5196:	d5fa      	bpl.n	518e <PkaEcdsaVerify+0xe6>
    5198:	4952      	ldr	r1, [pc, #328]	; (52e4 <PkaEcdsaVerify+0x23c>)
    519a:	6019      	str	r1, [r3, #0]
    519c:	6831      	ldr	r1, [r6, #0]
    519e:	910f      	str	r1, [sp, #60]	; 0x3c
    51a0:	990f      	ldr	r1, [sp, #60]	; 0x3c
    51a2:	07cc      	lsls	r4, r1, #31
    51a4:	d5fa      	bpl.n	519c <PkaEcdsaVerify+0xf4>
    51a6:	4950      	ldr	r1, [pc, #320]	; (52e8 <PkaEcdsaVerify+0x240>)
    51a8:	6019      	str	r1, [r3, #0]
    51aa:	4b50      	ldr	r3, [pc, #320]	; (52ec <PkaEcdsaVerify+0x244>)
    51ac:	461e      	mov	r6, r3
    51ae:	6819      	ldr	r1, [r3, #0]
    51b0:	9110      	str	r1, [sp, #64]	; 0x40
    51b2:	9910      	ldr	r1, [sp, #64]	; 0x40
    51b4:	07c9      	lsls	r1, r1, #31
    51b6:	d5fa      	bpl.n	51ae <PkaEcdsaVerify+0x106>
    51b8:	4c3f      	ldr	r4, [pc, #252]	; (52b8 <PkaEcdsaVerify+0x210>)
    51ba:	4b4d      	ldr	r3, [pc, #308]	; (52f0 <PkaEcdsaVerify+0x248>)
    51bc:	6023      	str	r3, [r4, #0]
    51be:	6833      	ldr	r3, [r6, #0]
    51c0:	9311      	str	r3, [sp, #68]	; 0x44
    51c2:	9b11      	ldr	r3, [sp, #68]	; 0x44
    51c4:	07db      	lsls	r3, r3, #31
    51c6:	d5fa      	bpl.n	51be <PkaEcdsaVerify+0x116>
    51c8:	4b4a      	ldr	r3, [pc, #296]	; (52f4 <PkaEcdsaVerify+0x24c>)
    51ca:	6023      	str	r3, [r4, #0]
    51cc:	6833      	ldr	r3, [r6, #0]
    51ce:	9312      	str	r3, [sp, #72]	; 0x48
    51d0:	9b12      	ldr	r3, [sp, #72]	; 0x48
    51d2:	07df      	lsls	r7, r3, #31
    51d4:	d5fa      	bpl.n	51cc <PkaEcdsaVerify+0x124>
    51d6:	4b48      	ldr	r3, [pc, #288]	; (52f8 <PkaEcdsaVerify+0x250>)
    51d8:	6023      	str	r3, [r4, #0]
    51da:	4b3a      	ldr	r3, [pc, #232]	; (52c4 <PkaEcdsaVerify+0x21c>)
    51dc:	4698      	mov	r8, r3
    51de:	6819      	ldr	r1, [r3, #0]
    51e0:	9113      	str	r1, [sp, #76]	; 0x4c
    51e2:	9913      	ldr	r1, [sp, #76]	; 0x4c
    51e4:	07c9      	lsls	r1, r1, #31
    51e6:	d5fa      	bpl.n	51de <PkaEcdsaVerify+0x136>
    51e8:	4f32      	ldr	r7, [pc, #200]	; (52b4 <PkaEcdsaVerify+0x20c>)
    51ea:	6038      	str	r0, [r7, #0]
    51ec:	6833      	ldr	r3, [r6, #0]
    51ee:	9314      	str	r3, [sp, #80]	; 0x50
    51f0:	9b14      	ldr	r3, [sp, #80]	; 0x50
    51f2:	07db      	lsls	r3, r3, #31
    51f4:	d5fa      	bpl.n	51ec <PkaEcdsaVerify+0x144>
    51f6:	6022      	str	r2, [r4, #0]
    51f8:	6833      	ldr	r3, [r6, #0]
    51fa:	9315      	str	r3, [sp, #84]	; 0x54
    51fc:	9b15      	ldr	r3, [sp, #84]	; 0x54
    51fe:	07d8      	lsls	r0, r3, #31
    5200:	d5fa      	bpl.n	51f8 <PkaEcdsaVerify+0x150>
    5202:	4b3e      	ldr	r3, [pc, #248]	; (52fc <PkaEcdsaVerify+0x254>)
    5204:	6023      	str	r3, [r4, #0]
    5206:	6833      	ldr	r3, [r6, #0]
    5208:	9316      	str	r3, [sp, #88]	; 0x58
    520a:	9b16      	ldr	r3, [sp, #88]	; 0x58
    520c:	07d9      	lsls	r1, r3, #31
    520e:	d5fa      	bpl.n	5206 <PkaEcdsaVerify+0x15e>
    5210:	4b3b      	ldr	r3, [pc, #236]	; (5300 <PkaEcdsaVerify+0x258>)
    5212:	6023      	str	r3, [r4, #0]
    5214:	6833      	ldr	r3, [r6, #0]
    5216:	9317      	str	r3, [sp, #92]	; 0x5c
    5218:	9b17      	ldr	r3, [sp, #92]	; 0x5c
    521a:	07da      	lsls	r2, r3, #31
    521c:	d5fa      	bpl.n	5214 <PkaEcdsaVerify+0x16c>
    521e:	4b39      	ldr	r3, [pc, #228]	; (5304 <PkaEcdsaVerify+0x25c>)
    5220:	6023      	str	r3, [r4, #0]
    5222:	6833      	ldr	r3, [r6, #0]
    5224:	9318      	str	r3, [sp, #96]	; 0x60
    5226:	9b18      	ldr	r3, [sp, #96]	; 0x60
    5228:	07db      	lsls	r3, r3, #31
    522a:	d5fa      	bpl.n	5222 <PkaEcdsaVerify+0x17a>
    522c:	4b36      	ldr	r3, [pc, #216]	; (5308 <PkaEcdsaVerify+0x260>)
    522e:	6023      	str	r3, [r4, #0]
    5230:	6833      	ldr	r3, [r6, #0]
    5232:	9319      	str	r3, [sp, #100]	; 0x64
    5234:	9b19      	ldr	r3, [sp, #100]	; 0x64
    5236:	07d8      	lsls	r0, r3, #31
    5238:	d5fa      	bpl.n	5230 <PkaEcdsaVerify+0x188>
    523a:	4b34      	ldr	r3, [pc, #208]	; (530c <PkaEcdsaVerify+0x264>)
    523c:	6023      	str	r3, [r4, #0]
    523e:	6833      	ldr	r3, [r6, #0]
    5240:	931a      	str	r3, [sp, #104]	; 0x68
    5242:	9b1a      	ldr	r3, [sp, #104]	; 0x68
    5244:	07d9      	lsls	r1, r3, #31
    5246:	d5fa      	bpl.n	523e <PkaEcdsaVerify+0x196>
    5248:	4b31      	ldr	r3, [pc, #196]	; (5310 <PkaEcdsaVerify+0x268>)
    524a:	6023      	str	r3, [r4, #0]
    524c:	6833      	ldr	r3, [r6, #0]
    524e:	931b      	str	r3, [sp, #108]	; 0x6c
    5250:	9b1b      	ldr	r3, [sp, #108]	; 0x6c
    5252:	07da      	lsls	r2, r3, #31
    5254:	d5fa      	bpl.n	524c <PkaEcdsaVerify+0x1a4>
    5256:	4b2f      	ldr	r3, [pc, #188]	; (5314 <PkaEcdsaVerify+0x26c>)
    5258:	6023      	str	r3, [r4, #0]
    525a:	f000 fc1d 	bl	5a98 <PkaSum2ScalarMullt>
    525e:	bb08      	cbnz	r0, 52a4 <PkaEcdsaVerify+0x1fc>
    5260:	f8d8 3000 	ldr.w	r3, [r8]
    5264:	931c      	str	r3, [sp, #112]	; 0x70
    5266:	9b1c      	ldr	r3, [sp, #112]	; 0x70
    5268:	07db      	lsls	r3, r3, #31
    526a:	d5f9      	bpl.n	5260 <PkaEcdsaVerify+0x1b8>
    526c:	603d      	str	r5, [r7, #0]
    526e:	6833      	ldr	r3, [r6, #0]
    5270:	931d      	str	r3, [sp, #116]	; 0x74
    5272:	9b1d      	ldr	r3, [sp, #116]	; 0x74
    5274:	07d9      	lsls	r1, r3, #31
    5276:	d5fa      	bpl.n	526e <PkaEcdsaVerify+0x1c6>
    5278:	4b27      	ldr	r3, [pc, #156]	; (5318 <PkaEcdsaVerify+0x270>)
    527a:	6023      	str	r3, [r4, #0]
    527c:	6833      	ldr	r3, [r6, #0]
    527e:	931e      	str	r3, [sp, #120]	; 0x78
    5280:	9b1e      	ldr	r3, [sp, #120]	; 0x78
    5282:	07da      	lsls	r2, r3, #31
    5284:	d5fa      	bpl.n	527c <PkaEcdsaVerify+0x1d4>
    5286:	4b25      	ldr	r3, [pc, #148]	; (531c <PkaEcdsaVerify+0x274>)
    5288:	6023      	str	r3, [r4, #0]
    528a:	f8d8 3000 	ldr.w	r3, [r8]
    528e:	931f      	str	r3, [sp, #124]	; 0x7c
    5290:	9b1f      	ldr	r3, [sp, #124]	; 0x7c
    5292:	07db      	lsls	r3, r3, #31
    5294:	d5f9      	bpl.n	528a <PkaEcdsaVerify+0x1e2>
    5296:	4b0c      	ldr	r3, [pc, #48]	; (52c8 <PkaEcdsaVerify+0x220>)
    5298:	681b      	ldr	r3, [r3, #0]
    529a:	f413 5f80 	tst.w	r3, #4096	; 0x1000
    529e:	4b20      	ldr	r3, [pc, #128]	; (5320 <PkaEcdsaVerify+0x278>)
    52a0:	bf08      	it	eq
    52a2:	4618      	moveq	r0, r3
    52a4:	b020      	add	sp, #128	; 0x80
    52a6:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    52aa:	481e      	ldr	r0, [pc, #120]	; (5324 <PkaEcdsaVerify+0x27c>)
    52ac:	e7fa      	b.n	52a4 <PkaEcdsaVerify+0x1fc>
    52ae:	481e      	ldr	r0, [pc, #120]	; (5328 <PkaEcdsaVerify+0x280>)
    52b0:	e7f8      	b.n	52a4 <PkaEcdsaVerify+0x1fc>
    52b2:	bf00      	nop
    52b4:	5002b090 	.word	0x5002b090
    52b8:	5002b080 	.word	0x5002b080
    52bc:	51021000 	.word	0x51021000
    52c0:	29721fc0 	.word	0x29721fc0
    52c4:	5002b0b4 	.word	0x5002b0b4
    52c8:	5002b088 	.word	0x5002b088
    52cc:	2901cfc0 	.word	0x2901cfc0
    52d0:	290e1fc0 	.word	0x290e1fc0
    52d4:	29003fc0 	.word	0x29003fc0
    52d8:	49020140 	.word	0x49020140
    52dc:	a8843100 	.word	0xa8843100
    52e0:	49160000 	.word	0x49160000
    52e4:	a1080140 	.word	0xa1080140
    52e8:	88084480 	.word	0x88084480
    52ec:	5002b0b0 	.word	0x5002b0b0
    52f0:	887044c0 	.word	0x887044c0
    52f4:	417a0780 	.word	0x417a0780
    52f8:	417e07c0 	.word	0x417e07c0
    52fc:	496a0000 	.word	0x496a0000
    5300:	49160680 	.word	0x49160680
    5304:	496e0040 	.word	0x496e0040
    5308:	21000200 	.word	0x21000200
    530c:	21208200 	.word	0x21208200
    5310:	21208240 	.word	0x21208240
    5314:	21248280 	.word	0x21248280
    5318:	a161a140 	.word	0xa161a140
    531c:	5161c800 	.word	0x5161c800
    5320:	00f10803 	.word	0x00f10803
    5324:	00f10801 	.word	0x00f10801
    5328:	00f10802 	.word	0x00f10802

0000532c <nrf_cc310_bl_hash_update_internal>:
    532c:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    5330:	4b31      	ldr	r3, [pc, #196]	; (53f8 <nrf_cc310_bl_hash_update_internal+0xcc>)
    5332:	6844      	ldr	r4, [r0, #4]
    5334:	4680      	mov	r8, r0
    5336:	4692      	mov	sl, r2
    5338:	4699      	mov	r9, r3
    533a:	681a      	ldr	r2, [r3, #0]
    533c:	2a00      	cmp	r2, #0
    533e:	d1fc      	bne.n	533a <nrf_cc310_bl_hash_update_internal+0xe>
    5340:	4b2e      	ldr	r3, [pc, #184]	; (53fc <nrf_cc310_bl_hash_update_internal+0xd0>)
    5342:	469b      	mov	fp, r3
    5344:	681a      	ldr	r2, [r3, #0]
    5346:	2a00      	cmp	r2, #0
    5348:	d1fc      	bne.n	5344 <nrf_cc310_bl_hash_update_internal+0x18>
    534a:	f04f 30ff 	mov.w	r0, #4294967295
    534e:	9101      	str	r1, [sp, #4]
    5350:	f000 fc94 	bl	5c7c <SaSi_HalClearInterruptBit>
    5354:	2080      	movs	r0, #128	; 0x80
    5356:	f000 fc97 	bl	5c88 <SaSi_HalMaskInterrupt>
    535a:	4d29      	ldr	r5, [pc, #164]	; (5400 <nrf_cc310_bl_hash_update_internal+0xd4>)
    535c:	4a29      	ldr	r2, [pc, #164]	; (5404 <nrf_cc310_bl_hash_update_internal+0xd8>)
    535e:	4f2a      	ldr	r7, [pc, #168]	; (5408 <nrf_cc310_bl_hash_update_internal+0xdc>)
    5360:	4e2a      	ldr	r6, [pc, #168]	; (540c <nrf_cc310_bl_hash_update_internal+0xe0>)
    5362:	2301      	movs	r3, #1
    5364:	2007      	movs	r0, #7
    5366:	602b      	str	r3, [r5, #0]
    5368:	f5a2 729e 	sub.w	r2, r2, #316	; 0x13c
    536c:	f8c2 013c 	str.w	r0, [r2, #316]	; 0x13c
    5370:	6013      	str	r3, [r2, #0]
    5372:	6a63      	ldr	r3, [r4, #36]	; 0x24
    5374:	603b      	str	r3, [r7, #0]
    5376:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    5378:	6033      	str	r3, [r6, #0]
    537a:	f8d8 3000 	ldr.w	r3, [r8]
    537e:	f842 3c04 	str.w	r3, [r2, #-4]
    5382:	f8d8 3008 	ldr.w	r3, [r8, #8]
    5386:	4620      	mov	r0, r4
    5388:	4798      	blx	r3
    538a:	9901      	ldr	r1, [sp, #4]
    538c:	f8d9 3000 	ldr.w	r3, [r9]
    5390:	2b00      	cmp	r3, #0
    5392:	d1fb      	bne.n	538c <nrf_cc310_bl_hash_update_internal+0x60>
    5394:	f1ba 0f00 	cmp.w	sl, #0
    5398:	d120      	bne.n	53dc <nrf_cc310_bl_hash_update_internal+0xb0>
    539a:	4b1d      	ldr	r3, [pc, #116]	; (5410 <nrf_cc310_bl_hash_update_internal+0xe4>)
    539c:	2204      	movs	r2, #4
    539e:	601a      	str	r2, [r3, #0]
    53a0:	f8d9 3000 	ldr.w	r3, [r9]
    53a4:	2b00      	cmp	r3, #0
    53a6:	d1fb      	bne.n	53a0 <nrf_cc310_bl_hash_update_internal+0x74>
    53a8:	f8db a000 	ldr.w	sl, [fp]
    53ac:	f1ba 0f00 	cmp.w	sl, #0
    53b0:	d1fa      	bne.n	53a8 <nrf_cc310_bl_hash_update_internal+0x7c>
    53b2:	f8d8 300c 	ldr.w	r3, [r8, #12]
    53b6:	4620      	mov	r0, r4
    53b8:	4798      	blx	r3
    53ba:	683b      	ldr	r3, [r7, #0]
    53bc:	6263      	str	r3, [r4, #36]	; 0x24
    53be:	6833      	ldr	r3, [r6, #0]
    53c0:	62a3      	str	r3, [r4, #40]	; 0x28
    53c2:	4b14      	ldr	r3, [pc, #80]	; (5414 <nrf_cc310_bl_hash_update_internal+0xe8>)
    53c4:	f8c3 a000 	str.w	sl, [r3]
    53c8:	f8c3 a144 	str.w	sl, [r3, #324]	; 0x144
    53cc:	f8d9 3000 	ldr.w	r3, [r9]
    53d0:	2b00      	cmp	r3, #0
    53d2:	d1fb      	bne.n	53cc <nrf_cc310_bl_hash_update_internal+0xa0>
    53d4:	602b      	str	r3, [r5, #0]
    53d6:	b003      	add	sp, #12
    53d8:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    53dc:	6a23      	ldr	r3, [r4, #32]
    53de:	2b01      	cmp	r3, #1
    53e0:	bf04      	itt	eq
    53e2:	4a0c      	ldreq	r2, [pc, #48]	; (5414 <nrf_cc310_bl_hash_update_internal+0xe8>)
    53e4:	6013      	streq	r3, [r2, #0]
    53e6:	4b0c      	ldr	r3, [pc, #48]	; (5418 <nrf_cc310_bl_hash_update_internal+0xec>)
    53e8:	2040      	movs	r0, #64	; 0x40
    53ea:	6019      	str	r1, [r3, #0]
    53ec:	f8c3 a004 	str.w	sl, [r3, #4]
    53f0:	f000 fc50 	bl	5c94 <SaSi_HalWaitInterrupt>
    53f4:	e7d4      	b.n	53a0 <nrf_cc310_bl_hash_update_internal+0x74>
    53f6:	bf00      	nop
    53f8:	5002b910 	.word	0x5002b910
    53fc:	5002bc20 	.word	0x5002bc20
    5400:	5002b818 	.word	0x5002b818
    5404:	5002b900 	.word	0x5002b900
    5408:	5002b7cc 	.word	0x5002b7cc
    540c:	5002b7d0 	.word	0x5002b7d0
    5410:	5002b7c8 	.word	0x5002b7c8
    5414:	5002b684 	.word	0x5002b684
    5418:	5002bc28 	.word	0x5002bc28

0000541c <PkaDoubleMdf2Mdf>:
    541c:	b510      	push	{r4, lr}
    541e:	4b54      	ldr	r3, [pc, #336]	; (5570 <PkaDoubleMdf2Mdf+0x154>)
    5420:	b098      	sub	sp, #96	; 0x60
    5422:	4619      	mov	r1, r3
    5424:	681a      	ldr	r2, [r3, #0]
    5426:	9201      	str	r2, [sp, #4]
    5428:	9a01      	ldr	r2, [sp, #4]
    542a:	07d2      	lsls	r2, r2, #31
    542c:	d5fa      	bpl.n	5424 <PkaDoubleMdf2Mdf+0x8>
    542e:	4b51      	ldr	r3, [pc, #324]	; (5574 <PkaDoubleMdf2Mdf+0x158>)
    5430:	4a51      	ldr	r2, [pc, #324]	; (5578 <PkaDoubleMdf2Mdf+0x15c>)
    5432:	601a      	str	r2, [r3, #0]
    5434:	680a      	ldr	r2, [r1, #0]
    5436:	9202      	str	r2, [sp, #8]
    5438:	9a02      	ldr	r2, [sp, #8]
    543a:	07d4      	lsls	r4, r2, #31
    543c:	d5fa      	bpl.n	5434 <PkaDoubleMdf2Mdf+0x18>
    543e:	4a4f      	ldr	r2, [pc, #316]	; (557c <PkaDoubleMdf2Mdf+0x160>)
    5440:	601a      	str	r2, [r3, #0]
    5442:	680a      	ldr	r2, [r1, #0]
    5444:	9203      	str	r2, [sp, #12]
    5446:	9a03      	ldr	r2, [sp, #12]
    5448:	07d0      	lsls	r0, r2, #31
    544a:	d5fa      	bpl.n	5442 <PkaDoubleMdf2Mdf+0x26>
    544c:	484c      	ldr	r0, [pc, #304]	; (5580 <PkaDoubleMdf2Mdf+0x164>)
    544e:	6018      	str	r0, [r3, #0]
    5450:	680a      	ldr	r2, [r1, #0]
    5452:	9204      	str	r2, [sp, #16]
    5454:	9a04      	ldr	r2, [sp, #16]
    5456:	07d2      	lsls	r2, r2, #31
    5458:	d5fa      	bpl.n	5450 <PkaDoubleMdf2Mdf+0x34>
    545a:	4a4a      	ldr	r2, [pc, #296]	; (5584 <PkaDoubleMdf2Mdf+0x168>)
    545c:	601a      	str	r2, [r3, #0]
    545e:	680a      	ldr	r2, [r1, #0]
    5460:	9205      	str	r2, [sp, #20]
    5462:	9a05      	ldr	r2, [sp, #20]
    5464:	07d4      	lsls	r4, r2, #31
    5466:	d5fa      	bpl.n	545e <PkaDoubleMdf2Mdf+0x42>
    5468:	4a47      	ldr	r2, [pc, #284]	; (5588 <PkaDoubleMdf2Mdf+0x16c>)
    546a:	601a      	str	r2, [r3, #0]
    546c:	680a      	ldr	r2, [r1, #0]
    546e:	9206      	str	r2, [sp, #24]
    5470:	9a06      	ldr	r2, [sp, #24]
    5472:	07d2      	lsls	r2, r2, #31
    5474:	d5fa      	bpl.n	546c <PkaDoubleMdf2Mdf+0x50>
    5476:	4a45      	ldr	r2, [pc, #276]	; (558c <PkaDoubleMdf2Mdf+0x170>)
    5478:	601a      	str	r2, [r3, #0]
    547a:	680a      	ldr	r2, [r1, #0]
    547c:	9207      	str	r2, [sp, #28]
    547e:	9a07      	ldr	r2, [sp, #28]
    5480:	07d4      	lsls	r4, r2, #31
    5482:	d5fa      	bpl.n	547a <PkaDoubleMdf2Mdf+0x5e>
    5484:	4a42      	ldr	r2, [pc, #264]	; (5590 <PkaDoubleMdf2Mdf+0x174>)
    5486:	601a      	str	r2, [r3, #0]
    5488:	680a      	ldr	r2, [r1, #0]
    548a:	9208      	str	r2, [sp, #32]
    548c:	9a08      	ldr	r2, [sp, #32]
    548e:	07d2      	lsls	r2, r2, #31
    5490:	d5fa      	bpl.n	5488 <PkaDoubleMdf2Mdf+0x6c>
    5492:	4a40      	ldr	r2, [pc, #256]	; (5594 <PkaDoubleMdf2Mdf+0x178>)
    5494:	601a      	str	r2, [r3, #0]
    5496:	680a      	ldr	r2, [r1, #0]
    5498:	9209      	str	r2, [sp, #36]	; 0x24
    549a:	9a09      	ldr	r2, [sp, #36]	; 0x24
    549c:	07d4      	lsls	r4, r2, #31
    549e:	d5fa      	bpl.n	5496 <PkaDoubleMdf2Mdf+0x7a>
    54a0:	4a3d      	ldr	r2, [pc, #244]	; (5598 <PkaDoubleMdf2Mdf+0x17c>)
    54a2:	601a      	str	r2, [r3, #0]
    54a4:	680a      	ldr	r2, [r1, #0]
    54a6:	920a      	str	r2, [sp, #40]	; 0x28
    54a8:	9a0a      	ldr	r2, [sp, #40]	; 0x28
    54aa:	07d2      	lsls	r2, r2, #31
    54ac:	d5fa      	bpl.n	54a4 <PkaDoubleMdf2Mdf+0x88>
    54ae:	4a3b      	ldr	r2, [pc, #236]	; (559c <PkaDoubleMdf2Mdf+0x180>)
    54b0:	601a      	str	r2, [r3, #0]
    54b2:	680a      	ldr	r2, [r1, #0]
    54b4:	920b      	str	r2, [sp, #44]	; 0x2c
    54b6:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
    54b8:	07d4      	lsls	r4, r2, #31
    54ba:	d5fa      	bpl.n	54b2 <PkaDoubleMdf2Mdf+0x96>
    54bc:	4a38      	ldr	r2, [pc, #224]	; (55a0 <PkaDoubleMdf2Mdf+0x184>)
    54be:	601a      	str	r2, [r3, #0]
    54c0:	680a      	ldr	r2, [r1, #0]
    54c2:	920c      	str	r2, [sp, #48]	; 0x30
    54c4:	9a0c      	ldr	r2, [sp, #48]	; 0x30
    54c6:	07d2      	lsls	r2, r2, #31
    54c8:	d5fa      	bpl.n	54c0 <PkaDoubleMdf2Mdf+0xa4>
    54ca:	4a36      	ldr	r2, [pc, #216]	; (55a4 <PkaDoubleMdf2Mdf+0x188>)
    54cc:	601a      	str	r2, [r3, #0]
    54ce:	680a      	ldr	r2, [r1, #0]
    54d0:	920d      	str	r2, [sp, #52]	; 0x34
    54d2:	9a0d      	ldr	r2, [sp, #52]	; 0x34
    54d4:	07d4      	lsls	r4, r2, #31
    54d6:	d5fa      	bpl.n	54ce <PkaDoubleMdf2Mdf+0xb2>
    54d8:	4a33      	ldr	r2, [pc, #204]	; (55a8 <PkaDoubleMdf2Mdf+0x18c>)
    54da:	601a      	str	r2, [r3, #0]
    54dc:	680a      	ldr	r2, [r1, #0]
    54de:	920e      	str	r2, [sp, #56]	; 0x38
    54e0:	9a0e      	ldr	r2, [sp, #56]	; 0x38
    54e2:	07d2      	lsls	r2, r2, #31
    54e4:	d5fa      	bpl.n	54dc <PkaDoubleMdf2Mdf+0xc0>
    54e6:	4a31      	ldr	r2, [pc, #196]	; (55ac <PkaDoubleMdf2Mdf+0x190>)
    54e8:	601a      	str	r2, [r3, #0]
    54ea:	680a      	ldr	r2, [r1, #0]
    54ec:	920f      	str	r2, [sp, #60]	; 0x3c
    54ee:	9a0f      	ldr	r2, [sp, #60]	; 0x3c
    54f0:	07d4      	lsls	r4, r2, #31
    54f2:	d5fa      	bpl.n	54ea <PkaDoubleMdf2Mdf+0xce>
    54f4:	4a2e      	ldr	r2, [pc, #184]	; (55b0 <PkaDoubleMdf2Mdf+0x194>)
    54f6:	601a      	str	r2, [r3, #0]
    54f8:	680a      	ldr	r2, [r1, #0]
    54fa:	9210      	str	r2, [sp, #64]	; 0x40
    54fc:	9a10      	ldr	r2, [sp, #64]	; 0x40
    54fe:	07d2      	lsls	r2, r2, #31
    5500:	d5fa      	bpl.n	54f8 <PkaDoubleMdf2Mdf+0xdc>
    5502:	4a2c      	ldr	r2, [pc, #176]	; (55b4 <PkaDoubleMdf2Mdf+0x198>)
    5504:	601a      	str	r2, [r3, #0]
    5506:	4b1a      	ldr	r3, [pc, #104]	; (5570 <PkaDoubleMdf2Mdf+0x154>)
    5508:	4619      	mov	r1, r3
    550a:	681c      	ldr	r4, [r3, #0]
    550c:	9411      	str	r4, [sp, #68]	; 0x44
    550e:	9c11      	ldr	r4, [sp, #68]	; 0x44
    5510:	07e4      	lsls	r4, r4, #31
    5512:	d5fa      	bpl.n	550a <PkaDoubleMdf2Mdf+0xee>
    5514:	4b17      	ldr	r3, [pc, #92]	; (5574 <PkaDoubleMdf2Mdf+0x158>)
    5516:	6018      	str	r0, [r3, #0]
    5518:	6808      	ldr	r0, [r1, #0]
    551a:	9012      	str	r0, [sp, #72]	; 0x48
    551c:	9812      	ldr	r0, [sp, #72]	; 0x48
    551e:	07c4      	lsls	r4, r0, #31
    5520:	d5fa      	bpl.n	5518 <PkaDoubleMdf2Mdf+0xfc>
    5522:	601a      	str	r2, [r3, #0]
    5524:	680a      	ldr	r2, [r1, #0]
    5526:	9213      	str	r2, [sp, #76]	; 0x4c
    5528:	9a13      	ldr	r2, [sp, #76]	; 0x4c
    552a:	07d0      	lsls	r0, r2, #31
    552c:	d5fa      	bpl.n	5524 <PkaDoubleMdf2Mdf+0x108>
    552e:	4a12      	ldr	r2, [pc, #72]	; (5578 <PkaDoubleMdf2Mdf+0x15c>)
    5530:	601a      	str	r2, [r3, #0]
    5532:	680a      	ldr	r2, [r1, #0]
    5534:	9214      	str	r2, [sp, #80]	; 0x50
    5536:	9a14      	ldr	r2, [sp, #80]	; 0x50
    5538:	07d2      	lsls	r2, r2, #31
    553a:	d5fa      	bpl.n	5532 <PkaDoubleMdf2Mdf+0x116>
    553c:	4a1e      	ldr	r2, [pc, #120]	; (55b8 <PkaDoubleMdf2Mdf+0x19c>)
    553e:	601a      	str	r2, [r3, #0]
    5540:	680a      	ldr	r2, [r1, #0]
    5542:	9215      	str	r2, [sp, #84]	; 0x54
    5544:	9a15      	ldr	r2, [sp, #84]	; 0x54
    5546:	07d4      	lsls	r4, r2, #31
    5548:	d5fa      	bpl.n	5540 <PkaDoubleMdf2Mdf+0x124>
    554a:	4a1c      	ldr	r2, [pc, #112]	; (55bc <PkaDoubleMdf2Mdf+0x1a0>)
    554c:	601a      	str	r2, [r3, #0]
    554e:	680a      	ldr	r2, [r1, #0]
    5550:	9216      	str	r2, [sp, #88]	; 0x58
    5552:	9a16      	ldr	r2, [sp, #88]	; 0x58
    5554:	07d0      	lsls	r0, r2, #31
    5556:	d5fa      	bpl.n	554e <PkaDoubleMdf2Mdf+0x132>
    5558:	4a19      	ldr	r2, [pc, #100]	; (55c0 <PkaDoubleMdf2Mdf+0x1a4>)
    555a:	601a      	str	r2, [r3, #0]
    555c:	680a      	ldr	r2, [r1, #0]
    555e:	9217      	str	r2, [sp, #92]	; 0x5c
    5560:	9a17      	ldr	r2, [sp, #92]	; 0x5c
    5562:	07d2      	lsls	r2, r2, #31
    5564:	d5fa      	bpl.n	555c <PkaDoubleMdf2Mdf+0x140>
    5566:	4a17      	ldr	r2, [pc, #92]	; (55c4 <PkaDoubleMdf2Mdf+0x1a8>)
    5568:	601a      	str	r2, [r3, #0]
    556a:	b018      	add	sp, #96	; 0x60
    556c:	bd10      	pop	{r4, pc}
    556e:	bf00      	nop
    5570:	5002b0b0 	.word	0x5002b0b0
    5574:	5002b080 	.word	0x5002b080
    5578:	21659300 	.word	0x21659300
    557c:	90310400 	.word	0x90310400
    5580:	90659640 	.word	0x90659640
    5584:	21618300 	.word	0x21618300
    5588:	2130c300 	.word	0x2130c300
    558c:	9064c300 	.word	0x9064c300
    5590:	90618100 	.word	0x90618100
    5594:	21104600 	.word	0x21104600
    5598:	21118100 	.word	0x21118100
    559c:	21444100 	.word	0x21444100
    55a0:	2920c300 	.word	0x2920c300
    55a4:	c810460c 	.word	0xc810460c
    55a8:	21318600 	.word	0x21318600
    55ac:	2160c300 	.word	0x2160c300
    55b0:	2928c140 	.word	0x2928c140
    55b4:	21659640 	.word	0x21659640
    55b8:	90311300 	.word	0x90311300
    55bc:	29259640 	.word	0x29259640
    55c0:	c8144659 	.word	0xc8144659
    55c4:	49320440 	.word	0x49320440

000055c8 <PkaDoubleMdf2Jcb>:
    55c8:	b510      	push	{r4, lr}
    55ca:	4b49      	ldr	r3, [pc, #292]	; (56f0 <PkaDoubleMdf2Jcb+0x128>)
    55cc:	b094      	sub	sp, #80	; 0x50
    55ce:	4619      	mov	r1, r3
    55d0:	681a      	ldr	r2, [r3, #0]
    55d2:	9200      	str	r2, [sp, #0]
    55d4:	9a00      	ldr	r2, [sp, #0]
    55d6:	07d2      	lsls	r2, r2, #31
    55d8:	d5fa      	bpl.n	55d0 <PkaDoubleMdf2Jcb+0x8>
    55da:	4b46      	ldr	r3, [pc, #280]	; (56f4 <PkaDoubleMdf2Jcb+0x12c>)
    55dc:	4a46      	ldr	r2, [pc, #280]	; (56f8 <PkaDoubleMdf2Jcb+0x130>)
    55de:	601a      	str	r2, [r3, #0]
    55e0:	680a      	ldr	r2, [r1, #0]
    55e2:	9201      	str	r2, [sp, #4]
    55e4:	9a01      	ldr	r2, [sp, #4]
    55e6:	07d4      	lsls	r4, r2, #31
    55e8:	d5fa      	bpl.n	55e0 <PkaDoubleMdf2Jcb+0x18>
    55ea:	4a44      	ldr	r2, [pc, #272]	; (56fc <PkaDoubleMdf2Jcb+0x134>)
    55ec:	601a      	str	r2, [r3, #0]
    55ee:	680a      	ldr	r2, [r1, #0]
    55f0:	9202      	str	r2, [sp, #8]
    55f2:	9a02      	ldr	r2, [sp, #8]
    55f4:	07d0      	lsls	r0, r2, #31
    55f6:	d5fa      	bpl.n	55ee <PkaDoubleMdf2Jcb+0x26>
    55f8:	4841      	ldr	r0, [pc, #260]	; (5700 <PkaDoubleMdf2Jcb+0x138>)
    55fa:	6018      	str	r0, [r3, #0]
    55fc:	680a      	ldr	r2, [r1, #0]
    55fe:	9203      	str	r2, [sp, #12]
    5600:	9a03      	ldr	r2, [sp, #12]
    5602:	07d2      	lsls	r2, r2, #31
    5604:	d5fa      	bpl.n	55fc <PkaDoubleMdf2Jcb+0x34>
    5606:	4a3f      	ldr	r2, [pc, #252]	; (5704 <PkaDoubleMdf2Jcb+0x13c>)
    5608:	601a      	str	r2, [r3, #0]
    560a:	680a      	ldr	r2, [r1, #0]
    560c:	9204      	str	r2, [sp, #16]
    560e:	9a04      	ldr	r2, [sp, #16]
    5610:	07d4      	lsls	r4, r2, #31
    5612:	d5fa      	bpl.n	560a <PkaDoubleMdf2Jcb+0x42>
    5614:	4a3c      	ldr	r2, [pc, #240]	; (5708 <PkaDoubleMdf2Jcb+0x140>)
    5616:	601a      	str	r2, [r3, #0]
    5618:	680a      	ldr	r2, [r1, #0]
    561a:	9205      	str	r2, [sp, #20]
    561c:	9a05      	ldr	r2, [sp, #20]
    561e:	07d2      	lsls	r2, r2, #31
    5620:	d5fa      	bpl.n	5618 <PkaDoubleMdf2Jcb+0x50>
    5622:	4a3a      	ldr	r2, [pc, #232]	; (570c <PkaDoubleMdf2Jcb+0x144>)
    5624:	601a      	str	r2, [r3, #0]
    5626:	680a      	ldr	r2, [r1, #0]
    5628:	9206      	str	r2, [sp, #24]
    562a:	9a06      	ldr	r2, [sp, #24]
    562c:	07d4      	lsls	r4, r2, #31
    562e:	d5fa      	bpl.n	5626 <PkaDoubleMdf2Jcb+0x5e>
    5630:	4a37      	ldr	r2, [pc, #220]	; (5710 <PkaDoubleMdf2Jcb+0x148>)
    5632:	601a      	str	r2, [r3, #0]
    5634:	680a      	ldr	r2, [r1, #0]
    5636:	9207      	str	r2, [sp, #28]
    5638:	9a07      	ldr	r2, [sp, #28]
    563a:	07d2      	lsls	r2, r2, #31
    563c:	d5fa      	bpl.n	5634 <PkaDoubleMdf2Jcb+0x6c>
    563e:	4a35      	ldr	r2, [pc, #212]	; (5714 <PkaDoubleMdf2Jcb+0x14c>)
    5640:	601a      	str	r2, [r3, #0]
    5642:	680a      	ldr	r2, [r1, #0]
    5644:	9208      	str	r2, [sp, #32]
    5646:	9a08      	ldr	r2, [sp, #32]
    5648:	07d4      	lsls	r4, r2, #31
    564a:	d5fa      	bpl.n	5642 <PkaDoubleMdf2Jcb+0x7a>
    564c:	4a32      	ldr	r2, [pc, #200]	; (5718 <PkaDoubleMdf2Jcb+0x150>)
    564e:	601a      	str	r2, [r3, #0]
    5650:	680a      	ldr	r2, [r1, #0]
    5652:	9209      	str	r2, [sp, #36]	; 0x24
    5654:	9a09      	ldr	r2, [sp, #36]	; 0x24
    5656:	07d2      	lsls	r2, r2, #31
    5658:	d5fa      	bpl.n	5650 <PkaDoubleMdf2Jcb+0x88>
    565a:	4a30      	ldr	r2, [pc, #192]	; (571c <PkaDoubleMdf2Jcb+0x154>)
    565c:	601a      	str	r2, [r3, #0]
    565e:	680a      	ldr	r2, [r1, #0]
    5660:	920a      	str	r2, [sp, #40]	; 0x28
    5662:	9a0a      	ldr	r2, [sp, #40]	; 0x28
    5664:	07d4      	lsls	r4, r2, #31
    5666:	d5fa      	bpl.n	565e <PkaDoubleMdf2Jcb+0x96>
    5668:	4a2d      	ldr	r2, [pc, #180]	; (5720 <PkaDoubleMdf2Jcb+0x158>)
    566a:	601a      	str	r2, [r3, #0]
    566c:	680a      	ldr	r2, [r1, #0]
    566e:	920b      	str	r2, [sp, #44]	; 0x2c
    5670:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
    5672:	07d2      	lsls	r2, r2, #31
    5674:	d5fa      	bpl.n	566c <PkaDoubleMdf2Jcb+0xa4>
    5676:	4a2b      	ldr	r2, [pc, #172]	; (5724 <PkaDoubleMdf2Jcb+0x15c>)
    5678:	601a      	str	r2, [r3, #0]
    567a:	680a      	ldr	r2, [r1, #0]
    567c:	920c      	str	r2, [sp, #48]	; 0x30
    567e:	9a0c      	ldr	r2, [sp, #48]	; 0x30
    5680:	07d4      	lsls	r4, r2, #31
    5682:	d5fa      	bpl.n	567a <PkaDoubleMdf2Jcb+0xb2>
    5684:	4a28      	ldr	r2, [pc, #160]	; (5728 <PkaDoubleMdf2Jcb+0x160>)
    5686:	601a      	str	r2, [r3, #0]
    5688:	680a      	ldr	r2, [r1, #0]
    568a:	920d      	str	r2, [sp, #52]	; 0x34
    568c:	9a0d      	ldr	r2, [sp, #52]	; 0x34
    568e:	07d2      	lsls	r2, r2, #31
    5690:	d5fa      	bpl.n	5688 <PkaDoubleMdf2Jcb+0xc0>
    5692:	4a26      	ldr	r2, [pc, #152]	; (572c <PkaDoubleMdf2Jcb+0x164>)
    5694:	601a      	str	r2, [r3, #0]
    5696:	680a      	ldr	r2, [r1, #0]
    5698:	920e      	str	r2, [sp, #56]	; 0x38
    569a:	9a0e      	ldr	r2, [sp, #56]	; 0x38
    569c:	07d4      	lsls	r4, r2, #31
    569e:	d5fa      	bpl.n	5696 <PkaDoubleMdf2Jcb+0xce>
    56a0:	4a23      	ldr	r2, [pc, #140]	; (5730 <PkaDoubleMdf2Jcb+0x168>)
    56a2:	601a      	str	r2, [r3, #0]
    56a4:	680a      	ldr	r2, [r1, #0]
    56a6:	920f      	str	r2, [sp, #60]	; 0x3c
    56a8:	9a0f      	ldr	r2, [sp, #60]	; 0x3c
    56aa:	07d2      	lsls	r2, r2, #31
    56ac:	d5fa      	bpl.n	56a4 <PkaDoubleMdf2Jcb+0xdc>
    56ae:	4a21      	ldr	r2, [pc, #132]	; (5734 <PkaDoubleMdf2Jcb+0x16c>)
    56b0:	601a      	str	r2, [r3, #0]
    56b2:	4b0f      	ldr	r3, [pc, #60]	; (56f0 <PkaDoubleMdf2Jcb+0x128>)
    56b4:	4619      	mov	r1, r3
    56b6:	681c      	ldr	r4, [r3, #0]
    56b8:	9410      	str	r4, [sp, #64]	; 0x40
    56ba:	9c10      	ldr	r4, [sp, #64]	; 0x40
    56bc:	07e4      	lsls	r4, r4, #31
    56be:	d5fa      	bpl.n	56b6 <PkaDoubleMdf2Jcb+0xee>
    56c0:	4b0c      	ldr	r3, [pc, #48]	; (56f4 <PkaDoubleMdf2Jcb+0x12c>)
    56c2:	6018      	str	r0, [r3, #0]
    56c4:	6808      	ldr	r0, [r1, #0]
    56c6:	9011      	str	r0, [sp, #68]	; 0x44
    56c8:	9811      	ldr	r0, [sp, #68]	; 0x44
    56ca:	07c4      	lsls	r4, r0, #31
    56cc:	d5fa      	bpl.n	56c4 <PkaDoubleMdf2Jcb+0xfc>
    56ce:	601a      	str	r2, [r3, #0]
    56d0:	680a      	ldr	r2, [r1, #0]
    56d2:	9212      	str	r2, [sp, #72]	; 0x48
    56d4:	9a12      	ldr	r2, [sp, #72]	; 0x48
    56d6:	07d0      	lsls	r0, r2, #31
    56d8:	d5fa      	bpl.n	56d0 <PkaDoubleMdf2Jcb+0x108>
    56da:	4a17      	ldr	r2, [pc, #92]	; (5738 <PkaDoubleMdf2Jcb+0x170>)
    56dc:	601a      	str	r2, [r3, #0]
    56de:	680a      	ldr	r2, [r1, #0]
    56e0:	9213      	str	r2, [sp, #76]	; 0x4c
    56e2:	9a13      	ldr	r2, [sp, #76]	; 0x4c
    56e4:	07d2      	lsls	r2, r2, #31
    56e6:	d5fa      	bpl.n	56de <PkaDoubleMdf2Jcb+0x116>
    56e8:	4a14      	ldr	r2, [pc, #80]	; (573c <PkaDoubleMdf2Jcb+0x174>)
    56ea:	601a      	str	r2, [r3, #0]
    56ec:	b014      	add	sp, #80	; 0x50
    56ee:	bd10      	pop	{r4, pc}
    56f0:	5002b0b0 	.word	0x5002b0b0
    56f4:	5002b080 	.word	0x5002b080
    56f8:	21659080 	.word	0x21659080
    56fc:	90090400 	.word	0x90090400
    5700:	90659640 	.word	0x90659640
    5704:	21618080 	.word	0x21618080
    5708:	21082080 	.word	0x21082080
    570c:	90642080 	.word	0x90642080
    5710:	90618100 	.word	0x90618100
    5714:	21104600 	.word	0x21104600
    5718:	21118100 	.word	0x21118100
    571c:	21444100 	.word	0x21444100
    5720:	29202080 	.word	0x29202080
    5724:	c8104602 	.word	0xc8104602
    5728:	21098600 	.word	0x21098600
    572c:	21602080 	.word	0x21602080
    5730:	29282140 	.word	0x29282140
    5734:	21659640 	.word	0x21659640
    5738:	29259640 	.word	0x29259640
    573c:	c8144659 	.word	0xc8144659

00005740 <PkaAddJcbAfn2Mdf>:
    5740:	b510      	push	{r4, lr}
    5742:	4b50      	ldr	r3, [pc, #320]	; (5884 <PkaAddJcbAfn2Mdf+0x144>)
    5744:	b096      	sub	sp, #88	; 0x58
    5746:	461c      	mov	r4, r3
    5748:	681a      	ldr	r2, [r3, #0]
    574a:	9201      	str	r2, [sp, #4]
    574c:	9a01      	ldr	r2, [sp, #4]
    574e:	07d2      	lsls	r2, r2, #31
    5750:	d5fa      	bpl.n	5748 <PkaAddJcbAfn2Mdf+0x8>
    5752:	4b4d      	ldr	r3, [pc, #308]	; (5888 <PkaAddJcbAfn2Mdf+0x148>)
    5754:	4a4d      	ldr	r2, [pc, #308]	; (588c <PkaAddJcbAfn2Mdf+0x14c>)
    5756:	601a      	str	r2, [r3, #0]
    5758:	6822      	ldr	r2, [r4, #0]
    575a:	9202      	str	r2, [sp, #8]
    575c:	9a02      	ldr	r2, [sp, #8]
    575e:	07d2      	lsls	r2, r2, #31
    5760:	d5fa      	bpl.n	5758 <PkaAddJcbAfn2Mdf+0x18>
    5762:	4a4b      	ldr	r2, [pc, #300]	; (5890 <PkaAddJcbAfn2Mdf+0x150>)
    5764:	601a      	str	r2, [r3, #0]
    5766:	4a4b      	ldr	r2, [pc, #300]	; (5894 <PkaAddJcbAfn2Mdf+0x154>)
    5768:	ea42 4080 	orr.w	r0, r2, r0, lsl #18
    576c:	6822      	ldr	r2, [r4, #0]
    576e:	9203      	str	r2, [sp, #12]
    5770:	9a03      	ldr	r2, [sp, #12]
    5772:	07d2      	lsls	r2, r2, #31
    5774:	d5fa      	bpl.n	576c <PkaAddJcbAfn2Mdf+0x2c>
    5776:	6018      	str	r0, [r3, #0]
    5778:	6822      	ldr	r2, [r4, #0]
    577a:	9204      	str	r2, [sp, #16]
    577c:	9a04      	ldr	r2, [sp, #16]
    577e:	07d0      	lsls	r0, r2, #31
    5780:	d5fa      	bpl.n	5778 <PkaAddJcbAfn2Mdf+0x38>
    5782:	4a45      	ldr	r2, [pc, #276]	; (5898 <PkaAddJcbAfn2Mdf+0x158>)
    5784:	601a      	str	r2, [r3, #0]
    5786:	f5a2 0280 	sub.w	r2, r2, #4194304	; 0x400000
    578a:	ea42 4181 	orr.w	r1, r2, r1, lsl #18
    578e:	6822      	ldr	r2, [r4, #0]
    5790:	9205      	str	r2, [sp, #20]
    5792:	9a05      	ldr	r2, [sp, #20]
    5794:	07d2      	lsls	r2, r2, #31
    5796:	d5fa      	bpl.n	578e <PkaAddJcbAfn2Mdf+0x4e>
    5798:	6019      	str	r1, [r3, #0]
    579a:	6822      	ldr	r2, [r4, #0]
    579c:	9206      	str	r2, [sp, #24]
    579e:	9a06      	ldr	r2, [sp, #24]
    57a0:	07d0      	lsls	r0, r2, #31
    57a2:	d5fa      	bpl.n	579a <PkaAddJcbAfn2Mdf+0x5a>
    57a4:	4a3d      	ldr	r2, [pc, #244]	; (589c <PkaAddJcbAfn2Mdf+0x15c>)
    57a6:	601a      	str	r2, [r3, #0]
    57a8:	6822      	ldr	r2, [r4, #0]
    57aa:	9207      	str	r2, [sp, #28]
    57ac:	9a07      	ldr	r2, [sp, #28]
    57ae:	07d1      	lsls	r1, r2, #31
    57b0:	d5fa      	bpl.n	57a8 <PkaAddJcbAfn2Mdf+0x68>
    57b2:	4a3b      	ldr	r2, [pc, #236]	; (58a0 <PkaAddJcbAfn2Mdf+0x160>)
    57b4:	601a      	str	r2, [r3, #0]
    57b6:	6822      	ldr	r2, [r4, #0]
    57b8:	9208      	str	r2, [sp, #32]
    57ba:	9a08      	ldr	r2, [sp, #32]
    57bc:	07d2      	lsls	r2, r2, #31
    57be:	d5fa      	bpl.n	57b6 <PkaAddJcbAfn2Mdf+0x76>
    57c0:	4a38      	ldr	r2, [pc, #224]	; (58a4 <PkaAddJcbAfn2Mdf+0x164>)
    57c2:	601a      	str	r2, [r3, #0]
    57c4:	6822      	ldr	r2, [r4, #0]
    57c6:	9209      	str	r2, [sp, #36]	; 0x24
    57c8:	9a09      	ldr	r2, [sp, #36]	; 0x24
    57ca:	07d0      	lsls	r0, r2, #31
    57cc:	d5fa      	bpl.n	57c4 <PkaAddJcbAfn2Mdf+0x84>
    57ce:	4a36      	ldr	r2, [pc, #216]	; (58a8 <PkaAddJcbAfn2Mdf+0x168>)
    57d0:	601a      	str	r2, [r3, #0]
    57d2:	6822      	ldr	r2, [r4, #0]
    57d4:	920a      	str	r2, [sp, #40]	; 0x28
    57d6:	9a0a      	ldr	r2, [sp, #40]	; 0x28
    57d8:	07d1      	lsls	r1, r2, #31
    57da:	d5fa      	bpl.n	57d2 <PkaAddJcbAfn2Mdf+0x92>
    57dc:	4a33      	ldr	r2, [pc, #204]	; (58ac <PkaAddJcbAfn2Mdf+0x16c>)
    57de:	601a      	str	r2, [r3, #0]
    57e0:	6822      	ldr	r2, [r4, #0]
    57e2:	920b      	str	r2, [sp, #44]	; 0x2c
    57e4:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
    57e6:	07d2      	lsls	r2, r2, #31
    57e8:	d5fa      	bpl.n	57e0 <PkaAddJcbAfn2Mdf+0xa0>
    57ea:	4a31      	ldr	r2, [pc, #196]	; (58b0 <PkaAddJcbAfn2Mdf+0x170>)
    57ec:	601a      	str	r2, [r3, #0]
    57ee:	6822      	ldr	r2, [r4, #0]
    57f0:	920c      	str	r2, [sp, #48]	; 0x30
    57f2:	9a0c      	ldr	r2, [sp, #48]	; 0x30
    57f4:	07d0      	lsls	r0, r2, #31
    57f6:	d5fa      	bpl.n	57ee <PkaAddJcbAfn2Mdf+0xae>
    57f8:	4a2e      	ldr	r2, [pc, #184]	; (58b4 <PkaAddJcbAfn2Mdf+0x174>)
    57fa:	601a      	str	r2, [r3, #0]
    57fc:	6822      	ldr	r2, [r4, #0]
    57fe:	920d      	str	r2, [sp, #52]	; 0x34
    5800:	9a0d      	ldr	r2, [sp, #52]	; 0x34
    5802:	07d1      	lsls	r1, r2, #31
    5804:	d5fa      	bpl.n	57fc <PkaAddJcbAfn2Mdf+0xbc>
    5806:	4a2c      	ldr	r2, [pc, #176]	; (58b8 <PkaAddJcbAfn2Mdf+0x178>)
    5808:	601a      	str	r2, [r3, #0]
    580a:	6822      	ldr	r2, [r4, #0]
    580c:	920e      	str	r2, [sp, #56]	; 0x38
    580e:	9a0e      	ldr	r2, [sp, #56]	; 0x38
    5810:	07d2      	lsls	r2, r2, #31
    5812:	d5fa      	bpl.n	580a <PkaAddJcbAfn2Mdf+0xca>
    5814:	4a29      	ldr	r2, [pc, #164]	; (58bc <PkaAddJcbAfn2Mdf+0x17c>)
    5816:	601a      	str	r2, [r3, #0]
    5818:	6822      	ldr	r2, [r4, #0]
    581a:	920f      	str	r2, [sp, #60]	; 0x3c
    581c:	9a0f      	ldr	r2, [sp, #60]	; 0x3c
    581e:	07d0      	lsls	r0, r2, #31
    5820:	d5fa      	bpl.n	5818 <PkaAddJcbAfn2Mdf+0xd8>
    5822:	4a27      	ldr	r2, [pc, #156]	; (58c0 <PkaAddJcbAfn2Mdf+0x180>)
    5824:	601a      	str	r2, [r3, #0]
    5826:	6821      	ldr	r1, [r4, #0]
    5828:	9110      	str	r1, [sp, #64]	; 0x40
    582a:	9910      	ldr	r1, [sp, #64]	; 0x40
    582c:	07c9      	lsls	r1, r1, #31
    582e:	d5fa      	bpl.n	5826 <PkaAddJcbAfn2Mdf+0xe6>
    5830:	601a      	str	r2, [r3, #0]
    5832:	4b14      	ldr	r3, [pc, #80]	; (5884 <PkaAddJcbAfn2Mdf+0x144>)
    5834:	461a      	mov	r2, r3
    5836:	6819      	ldr	r1, [r3, #0]
    5838:	9111      	str	r1, [sp, #68]	; 0x44
    583a:	9911      	ldr	r1, [sp, #68]	; 0x44
    583c:	07c8      	lsls	r0, r1, #31
    583e:	d5fa      	bpl.n	5836 <PkaAddJcbAfn2Mdf+0xf6>
    5840:	4b11      	ldr	r3, [pc, #68]	; (5888 <PkaAddJcbAfn2Mdf+0x148>)
    5842:	4920      	ldr	r1, [pc, #128]	; (58c4 <PkaAddJcbAfn2Mdf+0x184>)
    5844:	6019      	str	r1, [r3, #0]
    5846:	6811      	ldr	r1, [r2, #0]
    5848:	9112      	str	r1, [sp, #72]	; 0x48
    584a:	9912      	ldr	r1, [sp, #72]	; 0x48
    584c:	07c9      	lsls	r1, r1, #31
    584e:	d5fa      	bpl.n	5846 <PkaAddJcbAfn2Mdf+0x106>
    5850:	491d      	ldr	r1, [pc, #116]	; (58c8 <PkaAddJcbAfn2Mdf+0x188>)
    5852:	6019      	str	r1, [r3, #0]
    5854:	6811      	ldr	r1, [r2, #0]
    5856:	9113      	str	r1, [sp, #76]	; 0x4c
    5858:	9913      	ldr	r1, [sp, #76]	; 0x4c
    585a:	07cc      	lsls	r4, r1, #31
    585c:	d5fa      	bpl.n	5854 <PkaAddJcbAfn2Mdf+0x114>
    585e:	490b      	ldr	r1, [pc, #44]	; (588c <PkaAddJcbAfn2Mdf+0x14c>)
    5860:	6019      	str	r1, [r3, #0]
    5862:	6811      	ldr	r1, [r2, #0]
    5864:	9114      	str	r1, [sp, #80]	; 0x50
    5866:	9914      	ldr	r1, [sp, #80]	; 0x50
    5868:	07c8      	lsls	r0, r1, #31
    586a:	d5fa      	bpl.n	5862 <PkaAddJcbAfn2Mdf+0x122>
    586c:	4917      	ldr	r1, [pc, #92]	; (58cc <PkaAddJcbAfn2Mdf+0x18c>)
    586e:	6019      	str	r1, [r3, #0]
    5870:	6811      	ldr	r1, [r2, #0]
    5872:	9115      	str	r1, [sp, #84]	; 0x54
    5874:	9915      	ldr	r1, [sp, #84]	; 0x54
    5876:	07c9      	lsls	r1, r1, #31
    5878:	d5fa      	bpl.n	5870 <PkaAddJcbAfn2Mdf+0x130>
    587a:	4a15      	ldr	r2, [pc, #84]	; (58d0 <PkaAddJcbAfn2Mdf+0x190>)
    587c:	601a      	str	r2, [r3, #0]
    587e:	b016      	add	sp, #88	; 0x58
    5880:	bd10      	pop	{r4, pc}
    5882:	bf00      	nop
    5884:	5002b0b0 	.word	0x5002b0b0
    5888:	5002b080 	.word	0x5002b080
    588c:	90410440 	.word	0x90410440
    5890:	29298600 	.word	0x29298600
    5894:	c80110d8 	.word	0xc80110d8
    5898:	90411440 	.word	0x90411440
    589c:	29211440 	.word	0x29211440
    58a0:	21651440 	.word	0x21651440
    58a4:	90403400 	.word	0x90403400
    58a8:	900c3100 	.word	0x900c3100
    58ac:	900c40c0 	.word	0x900c40c0
    58b0:	292030c0 	.word	0x292030c0
    58b4:	900d9640 	.word	0x900d9640
    58b8:	90604100 	.word	0x90604100
    58bc:	c8451603 	.word	0xc8451603
    58c0:	21118600 	.word	0x21118600
    58c4:	21604100 	.word	0x21604100
    58c8:	c8444659 	.word	0xc8444659
    58cc:	90451440 	.word	0x90451440
    58d0:	902d1440 	.word	0x902d1440

000058d4 <PkaJcb2Afn>:
    58d4:	b570      	push	{r4, r5, r6, lr}
    58d6:	4826      	ldr	r0, [pc, #152]	; (5970 <PkaJcb2Afn+0x9c>)
    58d8:	b088      	sub	sp, #32
    58da:	4605      	mov	r5, r0
    58dc:	6804      	ldr	r4, [r0, #0]
    58de:	9400      	str	r4, [sp, #0]
    58e0:	9c00      	ldr	r4, [sp, #0]
    58e2:	07e6      	lsls	r6, r4, #31
    58e4:	d5fa      	bpl.n	58dc <PkaJcb2Afn+0x8>
    58e6:	4823      	ldr	r0, [pc, #140]	; (5974 <PkaJcb2Afn+0xa0>)
    58e8:	4c23      	ldr	r4, [pc, #140]	; (5978 <PkaJcb2Afn+0xa4>)
    58ea:	6004      	str	r4, [r0, #0]
    58ec:	4c23      	ldr	r4, [pc, #140]	; (597c <PkaJcb2Afn+0xa8>)
    58ee:	ea44 4383 	orr.w	r3, r4, r3, lsl #18
    58f2:	682c      	ldr	r4, [r5, #0]
    58f4:	9401      	str	r4, [sp, #4]
    58f6:	9c01      	ldr	r4, [sp, #4]
    58f8:	07e4      	lsls	r4, r4, #31
    58fa:	d5fa      	bpl.n	58f2 <PkaJcb2Afn+0x1e>
    58fc:	6003      	str	r3, [r0, #0]
    58fe:	0193      	lsls	r3, r2, #6
    5900:	ea43 4282 	orr.w	r2, r3, r2, lsl #18
    5904:	f042 4410 	orr.w	r4, r2, #2415919104	; 0x90000000
    5908:	f444 44c0 	orr.w	r4, r4, #24576	; 0x6000
    590c:	682b      	ldr	r3, [r5, #0]
    590e:	9302      	str	r3, [sp, #8]
    5910:	9b02      	ldr	r3, [sp, #8]
    5912:	07de      	lsls	r6, r3, #31
    5914:	d5fa      	bpl.n	590c <PkaJcb2Afn+0x38>
    5916:	6004      	str	r4, [r0, #0]
    5918:	682b      	ldr	r3, [r5, #0]
    591a:	9303      	str	r3, [sp, #12]
    591c:	9b03      	ldr	r3, [sp, #12]
    591e:	07db      	lsls	r3, r3, #31
    5920:	d5fa      	bpl.n	5918 <PkaJcb2Afn+0x44>
    5922:	4b17      	ldr	r3, [pc, #92]	; (5980 <PkaJcb2Afn+0xac>)
    5924:	6003      	str	r3, [r0, #0]
    5926:	018b      	lsls	r3, r1, #6
    5928:	ea43 4181 	orr.w	r1, r3, r1, lsl #18
    592c:	f041 4310 	orr.w	r3, r1, #2415919104	; 0x90000000
    5930:	f443 43c0 	orr.w	r3, r3, #24576	; 0x6000
    5934:	682e      	ldr	r6, [r5, #0]
    5936:	9604      	str	r6, [sp, #16]
    5938:	9e04      	ldr	r6, [sp, #16]
    593a:	07f6      	lsls	r6, r6, #31
    593c:	d5fa      	bpl.n	5934 <PkaJcb2Afn+0x60>
    593e:	6003      	str	r3, [r0, #0]
    5940:	682b      	ldr	r3, [r5, #0]
    5942:	9305      	str	r3, [sp, #20]
    5944:	9b05      	ldr	r3, [sp, #20]
    5946:	07de      	lsls	r6, r3, #31
    5948:	d5fa      	bpl.n	5940 <PkaJcb2Afn+0x6c>
    594a:	6004      	str	r4, [r0, #0]
    594c:	f041 4158 	orr.w	r1, r1, #3623878656	; 0xd8000000
    5950:	682b      	ldr	r3, [r5, #0]
    5952:	9306      	str	r3, [sp, #24]
    5954:	9b06      	ldr	r3, [sp, #24]
    5956:	07dc      	lsls	r4, r3, #31
    5958:	d5fa      	bpl.n	5950 <PkaJcb2Afn+0x7c>
    595a:	6001      	str	r1, [r0, #0]
    595c:	f042 4258 	orr.w	r2, r2, #3623878656	; 0xd8000000
    5960:	682b      	ldr	r3, [r5, #0]
    5962:	9307      	str	r3, [sp, #28]
    5964:	9b07      	ldr	r3, [sp, #28]
    5966:	07db      	lsls	r3, r3, #31
    5968:	d5fa      	bpl.n	5960 <PkaJcb2Afn+0x8c>
    596a:	6002      	str	r2, [r0, #0]
    596c:	b008      	add	sp, #32
    596e:	bd70      	pop	{r4, r5, r6, pc}
    5970:	5002b0b0 	.word	0x5002b0b0
    5974:	5002b080 	.word	0x5002b080
    5978:	290221c0 	.word	0x290221c0
    597c:	98007180 	.word	0x98007180
    5980:	90186180 	.word	0x90186180

00005984 <PkaAddAff>:
    5984:	4b35      	ldr	r3, [pc, #212]	; (5a5c <PkaAddAff+0xd8>)
    5986:	b08e      	sub	sp, #56	; 0x38
    5988:	4619      	mov	r1, r3
    598a:	681a      	ldr	r2, [r3, #0]
    598c:	9200      	str	r2, [sp, #0]
    598e:	9a00      	ldr	r2, [sp, #0]
    5990:	07d2      	lsls	r2, r2, #31
    5992:	d5fa      	bpl.n	598a <PkaAddAff+0x6>
    5994:	4b32      	ldr	r3, [pc, #200]	; (5a60 <PkaAddAff+0xdc>)
    5996:	4a33      	ldr	r2, [pc, #204]	; (5a64 <PkaAddAff+0xe0>)
    5998:	601a      	str	r2, [r3, #0]
    599a:	680a      	ldr	r2, [r1, #0]
    599c:	9201      	str	r2, [sp, #4]
    599e:	9a01      	ldr	r2, [sp, #4]
    59a0:	07d0      	lsls	r0, r2, #31
    59a2:	d5fa      	bpl.n	599a <PkaAddAff+0x16>
    59a4:	4a30      	ldr	r2, [pc, #192]	; (5a68 <PkaAddAff+0xe4>)
    59a6:	601a      	str	r2, [r3, #0]
    59a8:	680a      	ldr	r2, [r1, #0]
    59aa:	9202      	str	r2, [sp, #8]
    59ac:	9a02      	ldr	r2, [sp, #8]
    59ae:	07d2      	lsls	r2, r2, #31
    59b0:	d5fa      	bpl.n	59a8 <PkaAddAff+0x24>
    59b2:	4a2e      	ldr	r2, [pc, #184]	; (5a6c <PkaAddAff+0xe8>)
    59b4:	601a      	str	r2, [r3, #0]
    59b6:	680a      	ldr	r2, [r1, #0]
    59b8:	9203      	str	r2, [sp, #12]
    59ba:	9a03      	ldr	r2, [sp, #12]
    59bc:	07d0      	lsls	r0, r2, #31
    59be:	d5fa      	bpl.n	59b6 <PkaAddAff+0x32>
    59c0:	4a2b      	ldr	r2, [pc, #172]	; (5a70 <PkaAddAff+0xec>)
    59c2:	601a      	str	r2, [r3, #0]
    59c4:	680a      	ldr	r2, [r1, #0]
    59c6:	9204      	str	r2, [sp, #16]
    59c8:	9a04      	ldr	r2, [sp, #16]
    59ca:	07d2      	lsls	r2, r2, #31
    59cc:	d5fa      	bpl.n	59c4 <PkaAddAff+0x40>
    59ce:	4a29      	ldr	r2, [pc, #164]	; (5a74 <PkaAddAff+0xf0>)
    59d0:	601a      	str	r2, [r3, #0]
    59d2:	680a      	ldr	r2, [r1, #0]
    59d4:	9205      	str	r2, [sp, #20]
    59d6:	9a05      	ldr	r2, [sp, #20]
    59d8:	07d0      	lsls	r0, r2, #31
    59da:	d5fa      	bpl.n	59d2 <PkaAddAff+0x4e>
    59dc:	4a26      	ldr	r2, [pc, #152]	; (5a78 <PkaAddAff+0xf4>)
    59de:	601a      	str	r2, [r3, #0]
    59e0:	680a      	ldr	r2, [r1, #0]
    59e2:	9206      	str	r2, [sp, #24]
    59e4:	9a06      	ldr	r2, [sp, #24]
    59e6:	07d2      	lsls	r2, r2, #31
    59e8:	d5fa      	bpl.n	59e0 <PkaAddAff+0x5c>
    59ea:	4a24      	ldr	r2, [pc, #144]	; (5a7c <PkaAddAff+0xf8>)
    59ec:	601a      	str	r2, [r3, #0]
    59ee:	680a      	ldr	r2, [r1, #0]
    59f0:	9207      	str	r2, [sp, #28]
    59f2:	9a07      	ldr	r2, [sp, #28]
    59f4:	07d0      	lsls	r0, r2, #31
    59f6:	d5fa      	bpl.n	59ee <PkaAddAff+0x6a>
    59f8:	4a21      	ldr	r2, [pc, #132]	; (5a80 <PkaAddAff+0xfc>)
    59fa:	601a      	str	r2, [r3, #0]
    59fc:	680a      	ldr	r2, [r1, #0]
    59fe:	9208      	str	r2, [sp, #32]
    5a00:	9a08      	ldr	r2, [sp, #32]
    5a02:	07d2      	lsls	r2, r2, #31
    5a04:	d5fa      	bpl.n	59fc <PkaAddAff+0x78>
    5a06:	4a1f      	ldr	r2, [pc, #124]	; (5a84 <PkaAddAff+0x100>)
    5a08:	601a      	str	r2, [r3, #0]
    5a0a:	680a      	ldr	r2, [r1, #0]
    5a0c:	9209      	str	r2, [sp, #36]	; 0x24
    5a0e:	9a09      	ldr	r2, [sp, #36]	; 0x24
    5a10:	07d0      	lsls	r0, r2, #31
    5a12:	d5fa      	bpl.n	5a0a <PkaAddAff+0x86>
    5a14:	4a1c      	ldr	r2, [pc, #112]	; (5a88 <PkaAddAff+0x104>)
    5a16:	601a      	str	r2, [r3, #0]
    5a18:	680a      	ldr	r2, [r1, #0]
    5a1a:	920a      	str	r2, [sp, #40]	; 0x28
    5a1c:	9a0a      	ldr	r2, [sp, #40]	; 0x28
    5a1e:	07d2      	lsls	r2, r2, #31
    5a20:	d5fa      	bpl.n	5a18 <PkaAddAff+0x94>
    5a22:	4a1a      	ldr	r2, [pc, #104]	; (5a8c <PkaAddAff+0x108>)
    5a24:	601a      	str	r2, [r3, #0]
    5a26:	6808      	ldr	r0, [r1, #0]
    5a28:	900b      	str	r0, [sp, #44]	; 0x2c
    5a2a:	980b      	ldr	r0, [sp, #44]	; 0x2c
    5a2c:	07c0      	lsls	r0, r0, #31
    5a2e:	d5fa      	bpl.n	5a26 <PkaAddAff+0xa2>
    5a30:	601a      	str	r2, [r3, #0]
    5a32:	680a      	ldr	r2, [r1, #0]
    5a34:	920c      	str	r2, [sp, #48]	; 0x30
    5a36:	9a0c      	ldr	r2, [sp, #48]	; 0x30
    5a38:	07d0      	lsls	r0, r2, #31
    5a3a:	d5fa      	bpl.n	5a32 <PkaAddAff+0xae>
    5a3c:	4a14      	ldr	r2, [pc, #80]	; (5a90 <PkaAddAff+0x10c>)
    5a3e:	601a      	str	r2, [r3, #0]
    5a40:	680a      	ldr	r2, [r1, #0]
    5a42:	920d      	str	r2, [sp, #52]	; 0x34
    5a44:	9a0d      	ldr	r2, [sp, #52]	; 0x34
    5a46:	07d2      	lsls	r2, r2, #31
    5a48:	d5fa      	bpl.n	5a40 <PkaAddAff+0xbc>
    5a4a:	4a12      	ldr	r2, [pc, #72]	; (5a94 <PkaAddAff+0x110>)
    5a4c:	601a      	str	r2, [r3, #0]
    5a4e:	210e      	movs	r1, #14
    5a50:	230d      	movs	r3, #13
    5a52:	220f      	movs	r2, #15
    5a54:	2000      	movs	r0, #0
    5a56:	b00e      	add	sp, #56	; 0x38
    5a58:	f7ff bf3c 	b.w	58d4 <PkaJcb2Afn>
    5a5c:	5002b0b0 	.word	0x5002b0b0
    5a60:	5002b080 	.word	0x5002b080
    5a64:	29014380 	.word	0x29014380
    5a68:	21396340 	.word	0x21396340
    5a6c:	29017080 	.word	0x29017080
    5a70:	21542080 	.word	0x21542080
    5a74:	9034d100 	.word	0x9034d100
    5a78:	903440c0 	.word	0x903440c0
    5a7c:	292030c0 	.word	0x292030c0
    5a80:	900d53c0 	.word	0x900d53c0
    5a84:	90384100 	.word	0x90384100
    5a88:	c8082383 	.word	0xc8082383
    5a8c:	2110e380 	.word	0x2110e380
    5a90:	21384100 	.word	0x21384100
    5a94:	c80843cf 	.word	0xc80843cf

00005a98 <PkaSum2ScalarMullt>:
    5a98:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    5a9c:	2301      	movs	r3, #1
    5a9e:	b092      	sub	sp, #72	; 0x48
    5aa0:	e9cd 3303 	strd	r3, r3, [sp, #12]
    5aa4:	4b62      	ldr	r3, [pc, #392]	; (5c30 <PkaSum2ScalarMullt+0x198>)
    5aa6:	461d      	mov	r5, r3
    5aa8:	681a      	ldr	r2, [r3, #0]
    5aaa:	9205      	str	r2, [sp, #20]
    5aac:	9a05      	ldr	r2, [sp, #20]
    5aae:	07d2      	lsls	r2, r2, #31
    5ab0:	d5fa      	bpl.n	5aa8 <PkaSum2ScalarMullt+0x10>
    5ab2:	4c60      	ldr	r4, [pc, #384]	; (5c34 <PkaSum2ScalarMullt+0x19c>)
    5ab4:	4b60      	ldr	r3, [pc, #384]	; (5c38 <PkaSum2ScalarMullt+0x1a0>)
    5ab6:	6023      	str	r3, [r4, #0]
    5ab8:	4b60      	ldr	r3, [pc, #384]	; (5c3c <PkaSum2ScalarMullt+0x1a4>)
    5aba:	4619      	mov	r1, r3
    5abc:	681a      	ldr	r2, [r3, #0]
    5abe:	9206      	str	r2, [sp, #24]
    5ac0:	9a06      	ldr	r2, [sp, #24]
    5ac2:	07d7      	lsls	r7, r2, #31
    5ac4:	d5fa      	bpl.n	5abc <PkaSum2ScalarMullt+0x24>
    5ac6:	4b5e      	ldr	r3, [pc, #376]	; (5c40 <PkaSum2ScalarMullt+0x1a8>)
    5ac8:	681a      	ldr	r2, [r3, #0]
    5aca:	04d6      	lsls	r6, r2, #19
    5acc:	f100 80a8 	bmi.w	5c20 <PkaSum2ScalarMullt+0x188>
    5ad0:	682a      	ldr	r2, [r5, #0]
    5ad2:	9207      	str	r2, [sp, #28]
    5ad4:	9a07      	ldr	r2, [sp, #28]
    5ad6:	07d0      	lsls	r0, r2, #31
    5ad8:	d5fa      	bpl.n	5ad0 <PkaSum2ScalarMullt+0x38>
    5ada:	4a5a      	ldr	r2, [pc, #360]	; (5c44 <PkaSum2ScalarMullt+0x1ac>)
    5adc:	6022      	str	r2, [r4, #0]
    5ade:	680a      	ldr	r2, [r1, #0]
    5ae0:	9208      	str	r2, [sp, #32]
    5ae2:	9a08      	ldr	r2, [sp, #32]
    5ae4:	07d2      	lsls	r2, r2, #31
    5ae6:	d5fa      	bpl.n	5ade <PkaSum2ScalarMullt+0x46>
    5ae8:	681e      	ldr	r6, [r3, #0]
    5aea:	f3c6 3600 	ubfx	r6, r6, #12, #1
    5aee:	2e00      	cmp	r6, #0
    5af0:	f040 8098 	bne.w	5c24 <PkaSum2ScalarMullt+0x18c>
    5af4:	2012      	movs	r0, #18
    5af6:	f7ff f8f9 	bl	4cec <PkaGetRegEffectiveSizeInBits>
    5afa:	4607      	mov	r7, r0
    5afc:	2013      	movs	r0, #19
    5afe:	f7ff f8f5 	bl	4cec <PkaGetRegEffectiveSizeInBits>
    5b02:	4287      	cmp	r7, r0
    5b04:	bf8c      	ite	hi
    5b06:	2012      	movhi	r0, #18
    5b08:	2013      	movls	r0, #19
    5b0a:	f7ff f8ef 	bl	4cec <PkaGetRegEffectiveSizeInBits>
    5b0e:	1e47      	subs	r7, r0, #1
    5b10:	f7ff ff38 	bl	5984 <PkaAddAff>
    5b14:	ab03      	add	r3, sp, #12
    5b16:	aa01      	add	r2, sp, #4
    5b18:	4639      	mov	r1, r7
    5b1a:	2012      	movs	r0, #18
    5b1c:	f7ff f92c 	bl	4d78 <PkaGetNextMsBit>
    5b20:	ab04      	add	r3, sp, #16
    5b22:	4680      	mov	r8, r0
    5b24:	aa02      	add	r2, sp, #8
    5b26:	4639      	mov	r1, r7
    5b28:	2013      	movs	r0, #19
    5b2a:	f7ff f925 	bl	4d78 <PkaGetNextMsBit>
    5b2e:	eb00 0048 	add.w	r0, r0, r8, lsl #1
    5b32:	2802      	cmp	r0, #2
    5b34:	d032      	beq.n	5b9c <PkaSum2ScalarMullt+0x104>
    5b36:	2803      	cmp	r0, #3
    5b38:	d03e      	beq.n	5bb8 <PkaSum2ScalarMullt+0x120>
    5b3a:	2801      	cmp	r0, #1
    5b3c:	d174      	bne.n	5c28 <PkaSum2ScalarMullt+0x190>
    5b3e:	682b      	ldr	r3, [r5, #0]
    5b40:	9309      	str	r3, [sp, #36]	; 0x24
    5b42:	9b09      	ldr	r3, [sp, #36]	; 0x24
    5b44:	07db      	lsls	r3, r3, #31
    5b46:	d5fa      	bpl.n	5b3e <PkaSum2ScalarMullt+0xa6>
    5b48:	4b3f      	ldr	r3, [pc, #252]	; (5c48 <PkaSum2ScalarMullt+0x1b0>)
    5b4a:	6023      	str	r3, [r4, #0]
    5b4c:	682b      	ldr	r3, [r5, #0]
    5b4e:	930a      	str	r3, [sp, #40]	; 0x28
    5b50:	9b0a      	ldr	r3, [sp, #40]	; 0x28
    5b52:	07d8      	lsls	r0, r3, #31
    5b54:	d5fa      	bpl.n	5b4c <PkaSum2ScalarMullt+0xb4>
    5b56:	4b3d      	ldr	r3, [pc, #244]	; (5c4c <PkaSum2ScalarMullt+0x1b4>)
    5b58:	6023      	str	r3, [r4, #0]
    5b5a:	682b      	ldr	r3, [r5, #0]
    5b5c:	930f      	str	r3, [sp, #60]	; 0x3c
    5b5e:	9b0f      	ldr	r3, [sp, #60]	; 0x3c
    5b60:	07d9      	lsls	r1, r3, #31
    5b62:	d5fa      	bpl.n	5b5a <PkaSum2ScalarMullt+0xc2>
    5b64:	4b3a      	ldr	r3, [pc, #232]	; (5c50 <PkaSum2ScalarMullt+0x1b8>)
    5b66:	6023      	str	r3, [r4, #0]
    5b68:	682b      	ldr	r3, [r5, #0]
    5b6a:	9310      	str	r3, [sp, #64]	; 0x40
    5b6c:	9b10      	ldr	r3, [sp, #64]	; 0x40
    5b6e:	07da      	lsls	r2, r3, #31
    5b70:	d5fa      	bpl.n	5b68 <PkaSum2ScalarMullt+0xd0>
    5b72:	4b38      	ldr	r3, [pc, #224]	; (5c54 <PkaSum2ScalarMullt+0x1bc>)
    5b74:	6023      	str	r3, [r4, #0]
    5b76:	682b      	ldr	r3, [r5, #0]
    5b78:	9311      	str	r3, [sp, #68]	; 0x44
    5b7a:	9b11      	ldr	r3, [sp, #68]	; 0x44
    5b7c:	07db      	lsls	r3, r3, #31
    5b7e:	d5fa      	bpl.n	5b76 <PkaSum2ScalarMullt+0xde>
    5b80:	4b35      	ldr	r3, [pc, #212]	; (5c58 <PkaSum2ScalarMullt+0x1c0>)
    5b82:	6023      	str	r3, [r4, #0]
    5b84:	3f01      	subs	r7, #1
    5b86:	d525      	bpl.n	5bd4 <PkaSum2ScalarMullt+0x13c>
    5b88:	2310      	movs	r3, #16
    5b8a:	2219      	movs	r2, #25
    5b8c:	2118      	movs	r1, #24
    5b8e:	2000      	movs	r0, #0
    5b90:	f7ff fea0 	bl	58d4 <PkaJcb2Afn>
    5b94:	4630      	mov	r0, r6
    5b96:	b012      	add	sp, #72	; 0x48
    5b98:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    5b9c:	682b      	ldr	r3, [r5, #0]
    5b9e:	930b      	str	r3, [sp, #44]	; 0x2c
    5ba0:	9b0b      	ldr	r3, [sp, #44]	; 0x2c
    5ba2:	07d9      	lsls	r1, r3, #31
    5ba4:	d5fa      	bpl.n	5b9c <PkaSum2ScalarMullt+0x104>
    5ba6:	4b2d      	ldr	r3, [pc, #180]	; (5c5c <PkaSum2ScalarMullt+0x1c4>)
    5ba8:	6023      	str	r3, [r4, #0]
    5baa:	682b      	ldr	r3, [r5, #0]
    5bac:	930c      	str	r3, [sp, #48]	; 0x30
    5bae:	9b0c      	ldr	r3, [sp, #48]	; 0x30
    5bb0:	07da      	lsls	r2, r3, #31
    5bb2:	d5fa      	bpl.n	5baa <PkaSum2ScalarMullt+0x112>
    5bb4:	4b2a      	ldr	r3, [pc, #168]	; (5c60 <PkaSum2ScalarMullt+0x1c8>)
    5bb6:	e7cf      	b.n	5b58 <PkaSum2ScalarMullt+0xc0>
    5bb8:	682b      	ldr	r3, [r5, #0]
    5bba:	930d      	str	r3, [sp, #52]	; 0x34
    5bbc:	9b0d      	ldr	r3, [sp, #52]	; 0x34
    5bbe:	07db      	lsls	r3, r3, #31
    5bc0:	d5fa      	bpl.n	5bb8 <PkaSum2ScalarMullt+0x120>
    5bc2:	4b28      	ldr	r3, [pc, #160]	; (5c64 <PkaSum2ScalarMullt+0x1cc>)
    5bc4:	6023      	str	r3, [r4, #0]
    5bc6:	682b      	ldr	r3, [r5, #0]
    5bc8:	930e      	str	r3, [sp, #56]	; 0x38
    5bca:	9b0e      	ldr	r3, [sp, #56]	; 0x38
    5bcc:	07d8      	lsls	r0, r3, #31
    5bce:	d5fa      	bpl.n	5bc6 <PkaSum2ScalarMullt+0x12e>
    5bd0:	4b25      	ldr	r3, [pc, #148]	; (5c68 <PkaSum2ScalarMullt+0x1d0>)
    5bd2:	e7c1      	b.n	5b58 <PkaSum2ScalarMullt+0xc0>
    5bd4:	ab03      	add	r3, sp, #12
    5bd6:	aa01      	add	r2, sp, #4
    5bd8:	4639      	mov	r1, r7
    5bda:	2012      	movs	r0, #18
    5bdc:	f7ff f8cc 	bl	4d78 <PkaGetNextMsBit>
    5be0:	ab04      	add	r3, sp, #16
    5be2:	4604      	mov	r4, r0
    5be4:	aa02      	add	r2, sp, #8
    5be6:	4639      	mov	r1, r7
    5be8:	2013      	movs	r0, #19
    5bea:	f7ff f8c5 	bl	4d78 <PkaGetNextMsBit>
    5bee:	eb10 0444 	adds.w	r4, r0, r4, lsl #1
    5bf2:	d102      	bne.n	5bfa <PkaSum2ScalarMullt+0x162>
    5bf4:	f7ff fc12 	bl	541c <PkaDoubleMdf2Mdf>
    5bf8:	e7c4      	b.n	5b84 <PkaSum2ScalarMullt+0xec>
    5bfa:	f7ff fce5 	bl	55c8 <PkaDoubleMdf2Jcb>
    5bfe:	2c02      	cmp	r4, #2
    5c00:	d008      	beq.n	5c14 <PkaSum2ScalarMullt+0x17c>
    5c02:	2c03      	cmp	r4, #3
    5c04:	d009      	beq.n	5c1a <PkaSum2ScalarMullt+0x182>
    5c06:	2c01      	cmp	r4, #1
    5c08:	d110      	bne.n	5c2c <PkaSum2ScalarMullt+0x194>
    5c0a:	2117      	movs	r1, #23
    5c0c:	2016      	movs	r0, #22
    5c0e:	f7ff fd97 	bl	5740 <PkaAddJcbAfn2Mdf>
    5c12:	e7b7      	b.n	5b84 <PkaSum2ScalarMullt+0xec>
    5c14:	2115      	movs	r1, #21
    5c16:	2014      	movs	r0, #20
    5c18:	e7f9      	b.n	5c0e <PkaSum2ScalarMullt+0x176>
    5c1a:	210f      	movs	r1, #15
    5c1c:	200e      	movs	r0, #14
    5c1e:	e7f6      	b.n	5c0e <PkaSum2ScalarMullt+0x176>
    5c20:	4e12      	ldr	r6, [pc, #72]	; (5c6c <PkaSum2ScalarMullt+0x1d4>)
    5c22:	e7b7      	b.n	5b94 <PkaSum2ScalarMullt+0xfc>
    5c24:	4e12      	ldr	r6, [pc, #72]	; (5c70 <PkaSum2ScalarMullt+0x1d8>)
    5c26:	e7b5      	b.n	5b94 <PkaSum2ScalarMullt+0xfc>
    5c28:	4e12      	ldr	r6, [pc, #72]	; (5c74 <PkaSum2ScalarMullt+0x1dc>)
    5c2a:	e7b3      	b.n	5b94 <PkaSum2ScalarMullt+0xfc>
    5c2c:	4e12      	ldr	r6, [pc, #72]	; (5c78 <PkaSum2ScalarMullt+0x1e0>)
    5c2e:	e7b1      	b.n	5b94 <PkaSum2ScalarMullt+0xfc>
    5c30:	5002b0b0 	.word	0x5002b0b0
    5c34:	5002b080 	.word	0x5002b080
    5c38:	514a0800 	.word	0x514a0800
    5c3c:	5002b0b4 	.word	0x5002b0b4
    5c40:	5002b088 	.word	0x5002b088
    5c44:	514e0800 	.word	0x514e0800
    5c48:	495a0600 	.word	0x495a0600
    5c4c:	495e0640 	.word	0x495e0640
    5c50:	41420400 	.word	0x41420400
    5c54:	49421400 	.word	0x49421400
    5c58:	492e0440 	.word	0x492e0440
    5c5c:	49520600 	.word	0x49520600
    5c60:	49560640 	.word	0x49560640
    5c64:	493a0600 	.word	0x493a0600
    5c68:	493e0640 	.word	0x493e0640
    5c6c:	00f10806 	.word	0x00f10806
    5c70:	00f10807 	.word	0x00f10807
    5c74:	00f10804 	.word	0x00f10804
    5c78:	00f10805 	.word	0x00f10805

00005c7c <SaSi_HalClearInterruptBit>:
    5c7c:	4b01      	ldr	r3, [pc, #4]	; (5c84 <SaSi_HalClearInterruptBit+0x8>)
    5c7e:	6018      	str	r0, [r3, #0]
    5c80:	4770      	bx	lr
    5c82:	bf00      	nop
    5c84:	5002ba08 	.word	0x5002ba08

00005c88 <SaSi_HalMaskInterrupt>:
    5c88:	4b01      	ldr	r3, [pc, #4]	; (5c90 <SaSi_HalMaskInterrupt+0x8>)
    5c8a:	6018      	str	r0, [r3, #0]
    5c8c:	4770      	bx	lr
    5c8e:	bf00      	nop
    5c90:	5002ba04 	.word	0x5002ba04

00005c94 <SaSi_HalWaitInterrupt>:
    5c94:	4a03      	ldr	r2, [pc, #12]	; (5ca4 <SaSi_HalWaitInterrupt+0x10>)
    5c96:	6813      	ldr	r3, [r2, #0]
    5c98:	4218      	tst	r0, r3
    5c9a:	d0fc      	beq.n	5c96 <SaSi_HalWaitInterrupt+0x2>
    5c9c:	4a02      	ldr	r2, [pc, #8]	; (5ca8 <SaSi_HalWaitInterrupt+0x14>)
    5c9e:	6010      	str	r0, [r2, #0]
    5ca0:	4618      	mov	r0, r3
    5ca2:	4770      	bx	lr
    5ca4:	5002ba00 	.word	0x5002ba00
    5ca8:	5002ba08 	.word	0x5002ba08

00005cac <flash_area_id_from_multi_image_slot>:
    switch (slot) {
    5cac:	b129      	cbz	r1, 5cba <flash_area_id_from_multi_image_slot+0xe>
    return -EINVAL; /* flash_area_open will fail on that */
    5cae:	2901      	cmp	r1, #1
    5cb0:	bf0c      	ite	eq
    5cb2:	2005      	moveq	r0, #5
    5cb4:	f06f 0015 	mvnne.w	r0, #21
    5cb8:	4770      	bx	lr
    case 0: return FLASH_AREA_IMAGE_PRIMARY(image_index);
    5cba:	2002      	movs	r0, #2
}
    5cbc:	4770      	bx	lr

00005cbe <flash_area_get_device_id>:

uint8_t flash_area_get_device_id(const struct flash_area *fa)
{
	(void)fa;
	return FLASH_DEVICE_ID;
}
    5cbe:	2000      	movs	r0, #0
    5cc0:	4770      	bx	lr

00005cc2 <os_heap_init>:
    mbedtls_memory_buffer_alloc_init(mempool, sizeof(mempool));
}
#else
void os_heap_init(void)
{
}
    5cc2:	4770      	bx	lr

00005cc4 <bootutil_tlv_iter_begin>:
 *          -1 on errors
 */
int
bootutil_tlv_iter_begin(struct image_tlv_iter *it, const struct image_header *hdr,
                        const struct flash_area *fap, uint16_t type, bool prot)
{
    5cc4:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    5cc8:	460e      	mov	r6, r1
    5cca:	4617      	mov	r7, r2
    5ccc:	4699      	mov	r9, r3
    uint32_t off_;
    struct image_tlv_info info;

    if (it == NULL || hdr == NULL || fap == NULL) {
    5cce:	4604      	mov	r4, r0
    5cd0:	b928      	cbnz	r0, 5cde <bootutil_tlv_iter_begin+0x1a>
        return -1;
    5cd2:	f04f 38ff 	mov.w	r8, #4294967295
    it->prot_end = off_ + it->hdr->ih_protect_tlv_size;
    it->tlv_end = off_ + it->hdr->ih_protect_tlv_size + info.it_tlv_tot;
    // position on first TLV
    it->tlv_off = off_ + sizeof(info);
    return 0;
}
    5cd6:	4640      	mov	r0, r8
    5cd8:	b003      	add	sp, #12
    5cda:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
    if (it == NULL || hdr == NULL || fap == NULL) {
    5cde:	2900      	cmp	r1, #0
    5ce0:	d0f7      	beq.n	5cd2 <bootutil_tlv_iter_begin+0xe>
    5ce2:	2a00      	cmp	r2, #0
    5ce4:	d0f5      	beq.n	5cd2 <bootutil_tlv_iter_begin+0xe>
    off_ = BOOT_TLV_OFF(hdr);
    5ce6:	68cb      	ldr	r3, [r1, #12]
    5ce8:	890d      	ldrh	r5, [r1, #8]
    5cea:	441d      	add	r5, r3
    if (LOAD_IMAGE_DATA(hdr, fap, off_, &info, sizeof(info))) {
    5cec:	2304      	movs	r3, #4
    5cee:	eb0d 0203 	add.w	r2, sp, r3
    5cf2:	4629      	mov	r1, r5
    5cf4:	4638      	mov	r0, r7
    5cf6:	f000 fc48 	bl	658a <flash_area_read>
    5cfa:	4680      	mov	r8, r0
    5cfc:	2800      	cmp	r0, #0
    5cfe:	d1e8      	bne.n	5cd2 <bootutil_tlv_iter_begin+0xe>
    if (info.it_magic == IMAGE_TLV_PROT_INFO_MAGIC) {
    5d00:	f8bd 1004 	ldrh.w	r1, [sp, #4]
        if (hdr->ih_protect_tlv_size != info.it_tlv_tot) {
    5d04:	8973      	ldrh	r3, [r6, #10]
    if (info.it_magic == IMAGE_TLV_PROT_INFO_MAGIC) {
    5d06:	f646 1208 	movw	r2, #26888	; 0x6908
    5d0a:	4291      	cmp	r1, r2
    5d0c:	d125      	bne.n	5d5a <bootutil_tlv_iter_begin+0x96>
        if (hdr->ih_protect_tlv_size != info.it_tlv_tot) {
    5d0e:	f8bd 1006 	ldrh.w	r1, [sp, #6]
    5d12:	4299      	cmp	r1, r3
    5d14:	d1dd      	bne.n	5cd2 <bootutil_tlv_iter_begin+0xe>
        if (LOAD_IMAGE_DATA(hdr, fap, off_ + info.it_tlv_tot,
    5d16:	2304      	movs	r3, #4
    5d18:	eb0d 0203 	add.w	r2, sp, r3
    5d1c:	4429      	add	r1, r5
    5d1e:	4638      	mov	r0, r7
    5d20:	f000 fc33 	bl	658a <flash_area_read>
    5d24:	2800      	cmp	r0, #0
    5d26:	d1d4      	bne.n	5cd2 <bootutil_tlv_iter_begin+0xe>
    if (info.it_magic != IMAGE_TLV_INFO_MAGIC) {
    5d28:	f8bd 2004 	ldrh.w	r2, [sp, #4]
    5d2c:	f646 1307 	movw	r3, #26887	; 0x6907
    5d30:	429a      	cmp	r2, r3
    5d32:	d1ce      	bne.n	5cd2 <bootutil_tlv_iter_begin+0xe>
    it->fap = fap;
    5d34:	e9c4 6700 	strd	r6, r7, [r4]
    it->prot = prot;
    5d38:	f89d 3028 	ldrb.w	r3, [sp, #40]	; 0x28
    it->type = type;
    5d3c:	f8a4 9008 	strh.w	r9, [r4, #8]
    it->prot = prot;
    5d40:	72a3      	strb	r3, [r4, #10]
    it->prot_end = off_ + it->hdr->ih_protect_tlv_size;
    5d42:	8973      	ldrh	r3, [r6, #10]
    it->tlv_end = off_ + it->hdr->ih_protect_tlv_size + info.it_tlv_tot;
    5d44:	f8bd 2006 	ldrh.w	r2, [sp, #6]
    it->prot_end = off_ + it->hdr->ih_protect_tlv_size;
    5d48:	442b      	add	r3, r5
    5d4a:	60e3      	str	r3, [r4, #12]
    it->tlv_end = off_ + it->hdr->ih_protect_tlv_size + info.it_tlv_tot;
    5d4c:	8973      	ldrh	r3, [r6, #10]
    5d4e:	4413      	add	r3, r2
    5d50:	442b      	add	r3, r5
    it->tlv_off = off_ + sizeof(info);
    5d52:	3504      	adds	r5, #4
    it->tlv_end = off_ + it->hdr->ih_protect_tlv_size + info.it_tlv_tot;
    5d54:	6163      	str	r3, [r4, #20]
    it->tlv_off = off_ + sizeof(info);
    5d56:	6125      	str	r5, [r4, #16]
    return 0;
    5d58:	e7bd      	b.n	5cd6 <bootutil_tlv_iter_begin+0x12>
    } else if (hdr->ih_protect_tlv_size != 0) {
    5d5a:	2b00      	cmp	r3, #0
    5d5c:	d0e4      	beq.n	5d28 <bootutil_tlv_iter_begin+0x64>
    5d5e:	e7b8      	b.n	5cd2 <bootutil_tlv_iter_begin+0xe>

00005d60 <bootutil_tlv_iter_next>:
 *          -1 on errors
 */
int
bootutil_tlv_iter_next(struct image_tlv_iter *it, uint32_t *off, uint16_t *len,
                       uint16_t *type)
{
    5d60:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
    5d64:	460e      	mov	r6, r1
    5d66:	4617      	mov	r7, r2
    5d68:	461d      	mov	r5, r3
    struct image_tlv tlv;
    int rc;

    if (it == NULL || it->hdr == NULL || it->fap == NULL) {
    5d6a:	4604      	mov	r4, r0
    5d6c:	b920      	cbnz	r0, 5d78 <bootutil_tlv_iter_next+0x18>
        return -1;
    5d6e:	f04f 30ff 	mov.w	r0, #4294967295

        it->tlv_off += sizeof(tlv) + tlv.it_len;
    }

    return 1;
}
    5d72:	b002      	add	sp, #8
    5d74:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    if (it == NULL || it->hdr == NULL || it->fap == NULL) {
    5d78:	6803      	ldr	r3, [r0, #0]
    5d7a:	2b00      	cmp	r3, #0
    5d7c:	d0f7      	beq.n	5d6e <bootutil_tlv_iter_next+0xe>
    5d7e:	6843      	ldr	r3, [r0, #4]
    5d80:	2b00      	cmp	r3, #0
    5d82:	d0f4      	beq.n	5d6e <bootutil_tlv_iter_next+0xe>
        if (it->type == IMAGE_TLV_ANY || tlv.it_type == it->type) {
    5d84:	f64f 78ff 	movw	r8, #65535	; 0xffff
    while (it->tlv_off < it->tlv_end) {
    5d88:	e9d4 2304 	ldrd	r2, r3, [r4, #16]
    5d8c:	429a      	cmp	r2, r3
    5d8e:	d216      	bcs.n	5dbe <bootutil_tlv_iter_next+0x5e>
        if (it->hdr->ih_protect_tlv_size > 0 && it->tlv_off == it->prot_end) {
    5d90:	6823      	ldr	r3, [r4, #0]
    5d92:	895b      	ldrh	r3, [r3, #10]
    5d94:	b123      	cbz	r3, 5da0 <bootutil_tlv_iter_next+0x40>
    5d96:	68e3      	ldr	r3, [r4, #12]
    5d98:	4293      	cmp	r3, r2
            it->tlv_off += sizeof(struct image_tlv_info);
    5d9a:	bf04      	itt	eq
    5d9c:	3304      	addeq	r3, #4
    5d9e:	6123      	streq	r3, [r4, #16]
        rc = LOAD_IMAGE_DATA(it->hdr, it->fap, it->tlv_off, &tlv, sizeof tlv);
    5da0:	2304      	movs	r3, #4
    5da2:	6921      	ldr	r1, [r4, #16]
    5da4:	6860      	ldr	r0, [r4, #4]
    5da6:	eb0d 0203 	add.w	r2, sp, r3
    5daa:	f000 fbee 	bl	658a <flash_area_read>
        if (rc) {
    5dae:	2800      	cmp	r0, #0
    5db0:	d1dd      	bne.n	5d6e <bootutil_tlv_iter_next+0xe>
        if (it->prot && it->tlv_off >= it->prot_end) {
    5db2:	7aa3      	ldrb	r3, [r4, #10]
    5db4:	b12b      	cbz	r3, 5dc2 <bootutil_tlv_iter_next+0x62>
    5db6:	e9d4 3203 	ldrd	r3, r2, [r4, #12]
    5dba:	429a      	cmp	r2, r3
    5dbc:	d301      	bcc.n	5dc2 <bootutil_tlv_iter_next+0x62>
            return 1;
    5dbe:	2001      	movs	r0, #1
    5dc0:	e7d7      	b.n	5d72 <bootutil_tlv_iter_next+0x12>
        if (it->type == IMAGE_TLV_ANY || tlv.it_type == it->type) {
    5dc2:	8923      	ldrh	r3, [r4, #8]
        it->tlv_off += sizeof(tlv) + tlv.it_len;
    5dc4:	f8bd 1006 	ldrh.w	r1, [sp, #6]
        if (it->type == IMAGE_TLV_ANY || tlv.it_type == it->type) {
    5dc8:	4543      	cmp	r3, r8
    5dca:	f101 0204 	add.w	r2, r1, #4
    5dce:	d003      	beq.n	5dd8 <bootutil_tlv_iter_next+0x78>
    5dd0:	f8bd c004 	ldrh.w	ip, [sp, #4]
    5dd4:	459c      	cmp	ip, r3
    5dd6:	d10b      	bne.n	5df0 <bootutil_tlv_iter_next+0x90>
            if (type != NULL) {
    5dd8:	b115      	cbz	r5, 5de0 <bootutil_tlv_iter_next+0x80>
                *type = tlv.it_type;
    5dda:	f8bd 3004 	ldrh.w	r3, [sp, #4]
    5dde:	802b      	strh	r3, [r5, #0]
            *off = it->tlv_off + sizeof(tlv);
    5de0:	6923      	ldr	r3, [r4, #16]
    5de2:	3304      	adds	r3, #4
    5de4:	6033      	str	r3, [r6, #0]
            *len = tlv.it_len;
    5de6:	8039      	strh	r1, [r7, #0]
            it->tlv_off += sizeof(tlv) + tlv.it_len;
    5de8:	6923      	ldr	r3, [r4, #16]
    5dea:	4413      	add	r3, r2
    5dec:	6123      	str	r3, [r4, #16]
            return 0;
    5dee:	e7c0      	b.n	5d72 <bootutil_tlv_iter_next+0x12>
        it->tlv_off += sizeof(tlv) + tlv.it_len;
    5df0:	6923      	ldr	r3, [r4, #16]
    5df2:	4413      	add	r3, r2
    5df4:	6123      	str	r3, [r4, #16]
    5df6:	e7c7      	b.n	5d88 <bootutil_tlv_iter_next+0x28>

00005df8 <bootutil_read_bigint>:
{
    5df8:	b573      	push	{r0, r1, r4, r5, r6, lr}
    5dfa:	460c      	mov	r4, r1
    5dfc:	4606      	mov	r6, r0
    5dfe:	4611      	mov	r1, r2
    if (mbedtls_asn1_get_tag(cp, end, &len, MBEDTLS_ASN1_INTEGER)) {
    5e00:	2302      	movs	r3, #2
    5e02:	aa01      	add	r2, sp, #4
    5e04:	4620      	mov	r0, r4
    5e06:	f000 fa3b 	bl	6280 <mbedtls_asn1_get_tag>
    5e0a:	4605      	mov	r5, r0
    5e0c:	b9e8      	cbnz	r0, 5e4a <bootutil_read_bigint+0x52>
    if (len >= NUM_ECC_BYTES) {
    5e0e:	9a01      	ldr	r2, [sp, #4]
    5e10:	2a1f      	cmp	r2, #31
    5e12:	d90e      	bls.n	5e32 <bootutil_read_bigint+0x3a>
        memcpy(i, *cp + len - NUM_ECC_BYTES, NUM_ECC_BYTES);
    5e14:	6823      	ldr	r3, [r4, #0]
    5e16:	f1a2 0120 	sub.w	r1, r2, #32
    5e1a:	4419      	add	r1, r3
    5e1c:	2220      	movs	r2, #32
    5e1e:	4630      	mov	r0, r6
        memcpy(i + NUM_ECC_BYTES - len, *cp, len);
    5e20:	f000 fc58 	bl	66d4 <memcpy>
    *cp += len;
    5e24:	6823      	ldr	r3, [r4, #0]
    5e26:	9a01      	ldr	r2, [sp, #4]
    5e28:	4413      	add	r3, r2
    5e2a:	6023      	str	r3, [r4, #0]
}
    5e2c:	4628      	mov	r0, r5
    5e2e:	b002      	add	sp, #8
    5e30:	bd70      	pop	{r4, r5, r6, pc}
        memset(i, 0, NUM_ECC_BYTES - len);
    5e32:	4601      	mov	r1, r0
    5e34:	f1c2 0220 	rsb	r2, r2, #32
    5e38:	4630      	mov	r0, r6
    5e3a:	f000 fc56 	bl	66ea <memset>
        memcpy(i + NUM_ECC_BYTES - len, *cp, len);
    5e3e:	9a01      	ldr	r2, [sp, #4]
    5e40:	6821      	ldr	r1, [r4, #0]
    5e42:	f1c2 0020 	rsb	r0, r2, #32
    5e46:	4430      	add	r0, r6
    5e48:	e7ea      	b.n	5e20 <bootutil_read_bigint+0x28>
        return -3;
    5e4a:	f06f 0502 	mvn.w	r5, #2
    5e4e:	e7ed      	b.n	5e2c <bootutil_read_bigint+0x34>

00005e50 <boot_fih_memequal>:
    return memcmp(s1, s2, n);
    5e50:	f000 bc30 	b.w	66b4 <memcmp>

00005e54 <boot_trailer_sz>:
    return BOOT_STATUS_MAX_ENTRIES * boot_status_entry_sz(min_write_sz);
    5e54:	f44f 73c0 	mov.w	r3, #384	; 0x180
    5e58:	4358      	muls	r0, r3
}
    5e5a:	3030      	adds	r0, #48	; 0x30
    5e5c:	4770      	bx	lr

00005e5e <boot_status_entries>:
	return fa->fa_id;
    5e5e:	780b      	ldrb	r3, [r1, #0]
    if (flash_area_get_id(fap) == FLASH_AREA_IMAGE_PRIMARY(image_index) ||
    5e60:	2b02      	cmp	r3, #2
    5e62:	d006      	beq.n	5e72 <boot_status_entries+0x14>
        return BOOT_STATUS_STATE_COUNT * BOOT_STATUS_MAX_ENTRIES;
    5e64:	2b05      	cmp	r3, #5
    5e66:	bf14      	ite	ne
    5e68:	f04f 30ff 	movne.w	r0, #4294967295
    5e6c:	f44f 70c0 	moveq.w	r0, #384	; 0x180
    5e70:	4770      	bx	lr
    5e72:	f44f 70c0 	mov.w	r0, #384	; 0x180
}
    5e76:	4770      	bx	lr

00005e78 <boot_status_off>:
{
    5e78:	b510      	push	{r4, lr}
    5e7a:	4604      	mov	r4, r0
    elem_sz = flash_area_align(fap);
    5e7c:	f000 fbc5 	bl	660a <flash_area_align>
    return flash_area_get_size(fap) - off_from_end;
    5e80:	68a3      	ldr	r3, [r4, #8]
}
    5e82:	f44f 72c0 	mov.w	r2, #384	; 0x180
    return flash_area_get_size(fap) - off_from_end;
    5e86:	3b30      	subs	r3, #48	; 0x30
}
    5e88:	fb02 3010 	mls	r0, r2, r0, r3
    5e8c:	bd10      	pop	{r4, pc}

00005e8e <boot_write_copy_done>:
    return ALIGN_DOWN(boot_magic_off(fap) - BOOT_MAX_ALIGN, BOOT_MAX_ALIGN);
    5e8e:	6881      	ldr	r1, [r0, #8]
    5e90:	3918      	subs	r1, #24
    5e92:	f021 0107 	bic.w	r1, r1, #7
    return boot_write_trailer_flag(fap, off, BOOT_FLAG_SET);
    5e96:	2201      	movs	r2, #1
    5e98:	3908      	subs	r1, #8
    5e9a:	f000 bee7 	b.w	6c6c <boot_write_trailer_flag>

00005e9e <boot_write_swap_size>:
{
    5e9e:	b513      	push	{r0, r1, r4, lr}
    5ea0:	4604      	mov	r4, r0
    5ea2:	9101      	str	r1, [sp, #4]
    return boot_swap_info_off(fap) - BOOT_MAX_ALIGN;
    5ea4:	f000 fe73 	bl	6b8e <boot_swap_info_off>
    return boot_write_trailer(fap, off, (const uint8_t *) &swap_size, 4);
    5ea8:	2304      	movs	r3, #4
    5eaa:	f1a0 0108 	sub.w	r1, r0, #8
    5eae:	eb0d 0203 	add.w	r2, sp, r3
    5eb2:	4620      	mov	r0, r4
    5eb4:	f000 feae 	bl	6c14 <boot_write_trailer>
}
    5eb8:	b002      	add	sp, #8
    5eba:	bd10      	pop	{r4, pc}

00005ebc <boot_read_image_headers>:
{
    5ebc:	b570      	push	{r4, r5, r6, lr}
            rc = boot_read_image_header(state, i, boot_img_hdr(state, i), bs);
    5ebe:	4613      	mov	r3, r2
{
    5ec0:	460e      	mov	r6, r1
    5ec2:	4615      	mov	r5, r2
            rc = boot_read_image_header(state, i, boot_img_hdr(state, i), bs);
    5ec4:	2100      	movs	r1, #0
    5ec6:	4602      	mov	r2, r0
{
    5ec8:	4604      	mov	r4, r0
            rc = boot_read_image_header(state, i, boot_img_hdr(state, i), bs);
    5eca:	f7fa ff27 	bl	d1c <boot_read_image_header>
        if (rc != 0) {
    5ece:	b950      	cbnz	r0, 5ee6 <boot_read_image_headers+0x2a>
            rc = boot_read_image_header(state, i, boot_img_hdr(state, i), bs);
    5ed0:	462b      	mov	r3, r5
    5ed2:	f104 022c 	add.w	r2, r4, #44	; 0x2c
    5ed6:	2101      	movs	r1, #1
    5ed8:	4620      	mov	r0, r4
    5eda:	f7fa ff1f 	bl	d1c <boot_read_image_header>
        if (rc != 0) {
    5ede:	b110      	cbz	r0, 5ee6 <boot_read_image_headers+0x2a>
                return 0;
    5ee0:	2e00      	cmp	r6, #0
    5ee2:	bf08      	it	eq
    5ee4:	2000      	moveq	r0, #0
}
    5ee6:	bd70      	pop	{r4, r5, r6, pc}

00005ee8 <boot_read_image_size.constprop.0.isra.0>:
boot_read_image_size(struct boot_loader_state *state, int slot, uint32_t *size)
    5ee8:	b573      	push	{r0, r1, r4, r5, r6, lr}
    5eea:	4604      	mov	r4, r0
    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
    5eec:	2000      	movs	r0, #0
boot_read_image_size(struct boot_loader_state *state, int slot, uint32_t *size)
    5eee:	460d      	mov	r5, r1
    5ef0:	4616      	mov	r6, r2
    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
    5ef2:	f7ff fedb 	bl	5cac <flash_area_id_from_multi_image_slot>
    rc = flash_area_open(area_id, &fap);
    5ef6:	4669      	mov	r1, sp
    5ef8:	b2c0      	uxtb	r0, r0
    5efa:	f7fb fd77 	bl	19ec <flash_area_open>
    if (rc != 0) {
    5efe:	bb30      	cbnz	r0, 5f4e <boot_read_image_size.constprop.0.isra.0+0x66>
    off = BOOT_TLV_OFF(boot_img_hdr(state, slot));
    5f00:	232c      	movs	r3, #44	; 0x2c
    5f02:	fb03 4405 	mla	r4, r3, r5, r4
    if (flash_area_read(fap, off, &info, sizeof(info))) {
    5f06:	9800      	ldr	r0, [sp, #0]
    off = BOOT_TLV_OFF(boot_img_hdr(state, slot));
    5f08:	68e3      	ldr	r3, [r4, #12]
    5f0a:	8925      	ldrh	r5, [r4, #8]
    5f0c:	441d      	add	r5, r3
    if (flash_area_read(fap, off, &info, sizeof(info))) {
    5f0e:	2304      	movs	r3, #4
    5f10:	eb0d 0203 	add.w	r2, sp, r3
    5f14:	4629      	mov	r1, r5
    5f16:	f000 fb38 	bl	658a <flash_area_read>
    5f1a:	b9c0      	cbnz	r0, 5f4e <boot_read_image_size.constprop.0.isra.0+0x66>
    if (info.it_magic == IMAGE_TLV_PROT_INFO_MAGIC) {
    5f1c:	f8bd 2004 	ldrh.w	r2, [sp, #4]
    protect_tlv_size = boot_img_hdr(state, slot)->ih_protect_tlv_size;
    5f20:	8964      	ldrh	r4, [r4, #10]
        if (flash_area_read(fap, off + info.it_tlv_tot, &info, sizeof(info))) {
    5f22:	9800      	ldr	r0, [sp, #0]
    if (info.it_magic == IMAGE_TLV_PROT_INFO_MAGIC) {
    5f24:	f646 1308 	movw	r3, #26888	; 0x6908
    5f28:	429a      	cmp	r2, r3
    5f2a:	d115      	bne.n	5f58 <boot_read_image_size.constprop.0.isra.0+0x70>
        if (protect_tlv_size != info.it_tlv_tot) {
    5f2c:	f8bd 3006 	ldrh.w	r3, [sp, #6]
    5f30:	429c      	cmp	r4, r3
    5f32:	d10c      	bne.n	5f4e <boot_read_image_size.constprop.0.isra.0+0x66>
        if (flash_area_read(fap, off + info.it_tlv_tot, &info, sizeof(info))) {
    5f34:	2304      	movs	r3, #4
    5f36:	eb0d 0203 	add.w	r2, sp, r3
    5f3a:	1961      	adds	r1, r4, r5
    5f3c:	f000 fb25 	bl	658a <flash_area_read>
    5f40:	b928      	cbnz	r0, 5f4e <boot_read_image_size.constprop.0.isra.0+0x66>
    if (info.it_magic != IMAGE_TLV_INFO_MAGIC) {
    5f42:	f8bd 2004 	ldrh.w	r2, [sp, #4]
    5f46:	f646 1307 	movw	r3, #26887	; 0x6907
    5f4a:	429a      	cmp	r2, r3
    5f4c:	d007      	beq.n	5f5e <boot_read_image_size.constprop.0.isra.0+0x76>
    flash_area_close(fap);
    5f4e:	9800      	ldr	r0, [sp, #0]
    5f50:	f000 fb1a 	bl	6588 <flash_area_close>
}
    5f54:	b002      	add	sp, #8
    5f56:	bd70      	pop	{r4, r5, r6, pc}
    } else if (protect_tlv_size != 0) {
    5f58:	2c00      	cmp	r4, #0
    5f5a:	d0f2      	beq.n	5f42 <boot_read_image_size.constprop.0.isra.0+0x5a>
    5f5c:	e7f7      	b.n	5f4e <boot_read_image_size.constprop.0.isra.0+0x66>
    *size = off + protect_tlv_size + info.it_tlv_tot;
    5f5e:	f8bd 1006 	ldrh.w	r1, [sp, #6]
    5f62:	4421      	add	r1, r4
    5f64:	4429      	add	r1, r5
    5f66:	6031      	str	r1, [r6, #0]
    rc = 0;
    5f68:	e7f1      	b.n	5f4e <boot_read_image_size.constprop.0.isra.0+0x66>

00005f6a <boot_read_sectors>:
{
    5f6a:	b537      	push	{r0, r1, r2, r4, r5, lr}
    5f6c:	4604      	mov	r4, r0
    rc = flash_area_get_sectors(flash_area, &num_sectors, out_sectors);
    5f6e:	6a42      	ldr	r2, [r0, #36]	; 0x24
    uint32_t num_sectors = BOOT_MAX_IMG_SECTORS;
    5f70:	2580      	movs	r5, #128	; 0x80
    rc = flash_area_get_sectors(flash_area, &num_sectors, out_sectors);
    5f72:	a901      	add	r1, sp, #4
    5f74:	2002      	movs	r0, #2
    uint32_t num_sectors = BOOT_MAX_IMG_SECTORS;
    5f76:	9501      	str	r5, [sp, #4]
    rc = flash_area_get_sectors(flash_area, &num_sectors, out_sectors);
    5f78:	f7fb fd60 	bl	1a3c <flash_area_get_sectors>
    if (rc != 0) {
    5f7c:	b958      	cbnz	r0, 5f96 <boot_read_sectors+0x2c>
    *out_num_sectors = num_sectors;
    5f7e:	9b01      	ldr	r3, [sp, #4]
    rc = flash_area_get_sectors(flash_area, &num_sectors, out_sectors);
    5f80:	6d22      	ldr	r2, [r4, #80]	; 0x50
    *out_num_sectors = num_sectors;
    5f82:	62a3      	str	r3, [r4, #40]	; 0x28
    rc = flash_area_get_sectors(flash_area, &num_sectors, out_sectors);
    5f84:	a901      	add	r1, sp, #4
    5f86:	2005      	movs	r0, #5
    uint32_t num_sectors = BOOT_MAX_IMG_SECTORS;
    5f88:	9501      	str	r5, [sp, #4]
    rc = flash_area_get_sectors(flash_area, &num_sectors, out_sectors);
    5f8a:	f7fb fd57 	bl	1a3c <flash_area_get_sectors>
    if (rc != 0) {
    5f8e:	4605      	mov	r5, r0
    5f90:	b128      	cbz	r0, 5f9e <boot_read_sectors+0x34>
        return BOOT_EFLASH_SEC;
    5f92:	2509      	movs	r5, #9
    5f94:	e000      	b.n	5f98 <boot_read_sectors+0x2e>
        return BOOT_EFLASH;
    5f96:	2501      	movs	r5, #1
}
    5f98:	4628      	mov	r0, r5
    5f9a:	b003      	add	sp, #12
    5f9c:	bd30      	pop	{r4, r5, pc}
    *out_num_sectors = num_sectors;
    5f9e:	9b01      	ldr	r3, [sp, #4]
    elem_sz = flash_area_align(BOOT_IMG_AREA(state, BOOT_PRIMARY_SLOT));
    5fa0:	6a20      	ldr	r0, [r4, #32]
    *out_num_sectors = num_sectors;
    5fa2:	6563      	str	r3, [r4, #84]	; 0x54
    elem_sz = flash_area_align(BOOT_IMG_AREA(state, BOOT_PRIMARY_SLOT));
    5fa4:	f000 fb31 	bl	660a <flash_area_align>
    BOOT_WRITE_SZ(state) = boot_write_sz(state);
    5fa8:	65e0      	str	r0, [r4, #92]	; 0x5c
    return 0;
    5faa:	e7f5      	b.n	5f98 <boot_read_sectors+0x2e>

00005fac <boot_status_reset>:
    bs->idx = BOOT_STATUS_IDX_0;
    5fac:	2301      	movs	r3, #1
    5fae:	6003      	str	r3, [r0, #0]
    bs->state = BOOT_STATUS_STATE_0;
    5fb0:	f103 2301 	add.w	r3, r3, #16777472	; 0x1000100
    5fb4:	6043      	str	r3, [r0, #4]
    bs->swap_size = 0;
    5fb6:	2300      	movs	r3, #0
    bs->source = 0;
    5fb8:	e9c0 3302 	strd	r3, r3, [r0, #8]
}
    5fbc:	4770      	bx	lr

00005fbe <boot_status_is_reset>:
            bs->idx == BOOT_STATUS_IDX_0 &&
    5fbe:	7943      	ldrb	r3, [r0, #5]
    5fc0:	2b01      	cmp	r3, #1
    5fc2:	d107      	bne.n	5fd4 <boot_status_is_reset+0x16>
    return (bs->op == BOOT_STATUS_OP_MOVE &&
    5fc4:	6803      	ldr	r3, [r0, #0]
    5fc6:	2b01      	cmp	r3, #1
    5fc8:	d104      	bne.n	5fd4 <boot_status_is_reset+0x16>
            bs->idx == BOOT_STATUS_IDX_0 &&
    5fca:	7900      	ldrb	r0, [r0, #4]
    5fcc:	1e43      	subs	r3, r0, #1
    5fce:	4258      	negs	r0, r3
    5fd0:	4158      	adcs	r0, r3
    5fd2:	4770      	bx	lr
    5fd4:	2000      	movs	r0, #0
}
    5fd6:	4770      	bx	lr

00005fd8 <boot_write_status>:
{
    5fd8:	b57f      	push	{r0, r1, r2, r3, r4, r5, r6, lr}
    5fda:	4606      	mov	r6, r0
    5fdc:	460d      	mov	r5, r1
    rc = flash_area_open(area_id, &fap);
    5fde:	2002      	movs	r0, #2
    5fe0:	a901      	add	r1, sp, #4
    5fe2:	f7fb fd03 	bl	19ec <flash_area_open>
    if (rc != 0) {
    5fe6:	bb38      	cbnz	r0, 6038 <boot_write_status+0x60>
    off = boot_status_off(fap) +
    5fe8:	9801      	ldr	r0, [sp, #4]
    5fea:	f7ff ff45 	bl	5e78 <boot_status_off>
          boot_status_internal_off(bs, BOOT_WRITE_SZ(state));
    5fee:	6df1      	ldr	r1, [r6, #92]	; 0x5c
    off = boot_status_off(fap) +
    5ff0:	4604      	mov	r4, r0
          boot_status_internal_off(bs, BOOT_WRITE_SZ(state));
    5ff2:	4628      	mov	r0, r5
    5ff4:	f000 f8e5 	bl	61c2 <boot_status_internal_off>
    off = boot_status_off(fap) +
    5ff8:	4404      	add	r4, r0
    align = flash_area_align(fap);
    5ffa:	9801      	ldr	r0, [sp, #4]
    5ffc:	f000 fb05 	bl	660a <flash_area_align>
    6000:	4606      	mov	r6, r0
    erased_val = flash_area_erased_val(fap);
    6002:	9801      	ldr	r0, [sp, #4]
    6004:	f000 fb08 	bl	6618 <flash_area_erased_val>
    memset(buf, erased_val, BOOT_MAX_ALIGN);
    6008:	2208      	movs	r2, #8
    erased_val = flash_area_erased_val(fap);
    600a:	4601      	mov	r1, r0
    memset(buf, erased_val, BOOT_MAX_ALIGN);
    600c:	eb0d 0002 	add.w	r0, sp, r2
    6010:	f000 fb6b 	bl	66ea <memset>
    buf[0] = bs->state;
    6014:	792b      	ldrb	r3, [r5, #4]
    6016:	f88d 3008 	strb.w	r3, [sp, #8]
    rc = flash_area_write(fap, off, buf, align);
    601a:	4621      	mov	r1, r4
    601c:	9801      	ldr	r0, [sp, #4]
    601e:	4633      	mov	r3, r6
    6020:	aa02      	add	r2, sp, #8
    6022:	f000 fac7 	bl	65b4 <flash_area_write>
    if (rc != 0) {
    6026:	1e04      	subs	r4, r0, #0
    flash_area_close(fap);
    6028:	9801      	ldr	r0, [sp, #4]
    if (rc != 0) {
    602a:	bf18      	it	ne
    602c:	2401      	movne	r4, #1
    flash_area_close(fap);
    602e:	f000 faab 	bl	6588 <flash_area_close>
}
    6032:	4620      	mov	r0, r4
    6034:	b004      	add	sp, #16
    6036:	bd70      	pop	{r4, r5, r6, pc}
        return BOOT_EFLASH;
    6038:	2401      	movs	r4, #1
    603a:	e7fa      	b.n	6032 <boot_write_status+0x5a>

0000603c <boot_erase_region>:
    return flash_area_erase(fap, off, sz);
    603c:	f000 bacf 	b.w	65de <flash_area_erase>

00006040 <swap_erase_trailer_sectors>:

#if defined(MCUBOOT_SWAP_USING_SCRATCH) || defined(MCUBOOT_SWAP_USING_MOVE)
int
swap_erase_trailer_sectors(const struct boot_loader_state *state,
                           const struct flash_area *fap)
{
    6040:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    6044:	460e      	mov	r6, r1
    int rc;

    BOOT_LOG_DBG("erasing trailer; fa_id=%d", flash_area_get_id(fap));

    image_index = BOOT_CURR_IMG(state);
    fa_id_primary = flash_area_id_from_multi_image_slot(image_index,
    6046:	2100      	movs	r1, #0
{
    6048:	4607      	mov	r7, r0
    fa_id_primary = flash_area_id_from_multi_image_slot(image_index,
    604a:	4608      	mov	r0, r1
    604c:	f7ff fe2e 	bl	5cac <flash_area_id_from_multi_image_slot>
            BOOT_PRIMARY_SLOT);
    fa_id_secondary = flash_area_id_from_multi_image_slot(image_index,
    6050:	2101      	movs	r1, #1
    fa_id_primary = flash_area_id_from_multi_image_slot(image_index,
    6052:	4604      	mov	r4, r0
    fa_id_secondary = flash_area_id_from_multi_image_slot(image_index,
    6054:	2000      	movs	r0, #0
    6056:	f7ff fe29 	bl	5cac <flash_area_id_from_multi_image_slot>
            BOOT_SECONDARY_SLOT);

    if (flash_area_get_id(fap) == fa_id_primary) {
    605a:	7833      	ldrb	r3, [r6, #0]
    605c:	429c      	cmp	r4, r3
    605e:	d021      	beq.n	60a4 <swap_erase_trailer_sectors+0x64>
        slot = BOOT_PRIMARY_SLOT;
    } else if (flash_area_get_id(fap) == fa_id_secondary) {
    6060:	4298      	cmp	r0, r3
    6062:	d121      	bne.n	60a8 <swap_erase_trailer_sectors+0x68>
        slot = BOOT_SECONDARY_SLOT;
    6064:	2501      	movs	r5, #1
    return BOOT_IMG(state, slot).num_sectors;
    6066:	232c      	movs	r3, #44	; 0x2c
    6068:	fb03 7505 	mla	r5, r3, r5, r7
        return BOOT_EFLASH;
    }

    /* delete starting from last sector and moving to beginning */
    sector = boot_img_num_sectors(state, slot) - 1;
    trailer_sz = boot_trailer_sz(BOOT_WRITE_SZ(state));
    606c:	6df8      	ldr	r0, [r7, #92]	; 0x5c
    sector = boot_img_num_sectors(state, slot) - 1;
    606e:	6aac      	ldr	r4, [r5, #40]	; 0x28
    trailer_sz = boot_trailer_sz(BOOT_WRITE_SZ(state));
    6070:	f7ff fef0 	bl	5e54 <boot_trailer_sz>
    sector = boot_img_num_sectors(state, slot) - 1;
    6074:	3c01      	subs	r4, #1
    trailer_sz = boot_trailer_sz(BOOT_WRITE_SZ(state));
    6076:	4607      	mov	r7, r0
    total_sz = 0;
    6078:	f04f 0800 	mov.w	r8, #0
    return flash_sector_get_size(&BOOT_IMG(state, slot).sectors[sector]);
    607c:	6a6b      	ldr	r3, [r5, #36]	; 0x24
    607e:	eb03 02c4 	add.w	r2, r3, r4, lsl #3
    return flash_sector_get_off(&BOOT_IMG(state, slot).sectors[sector]) -
    6082:	f853 1034 	ldr.w	r1, [r3, r4, lsl #3]
	return fs->fs_size;
    6086:	f8d2 9004 	ldr.w	r9, [r2, #4]
    608a:	681b      	ldr	r3, [r3, #0]
    do {
        sz = boot_img_sector_size(state, slot, sector);
        off = boot_img_sector_off(state, slot, sector);
        rc = boot_erase_region(fap, off, sz);
    608c:	464a      	mov	r2, r9
    608e:	1ac9      	subs	r1, r1, r3
    6090:	4630      	mov	r0, r6
        assert(rc == 0);

        sector--;
        total_sz += sz;
    6092:	44c8      	add	r8, r9
        rc = boot_erase_region(fap, off, sz);
    6094:	f7ff ffd2 	bl	603c <boot_erase_region>
    } while (total_sz < trailer_sz);
    6098:	45b8      	cmp	r8, r7
        sector--;
    609a:	f104 34ff 	add.w	r4, r4, #4294967295
    } while (total_sz < trailer_sz);
    609e:	d3ed      	bcc.n	607c <swap_erase_trailer_sectors+0x3c>

    return rc;
}
    60a0:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
        slot = BOOT_PRIMARY_SLOT;
    60a4:	2500      	movs	r5, #0
    60a6:	e7de      	b.n	6066 <swap_erase_trailer_sectors+0x26>
        return BOOT_EFLASH;
    60a8:	2001      	movs	r0, #1
    60aa:	e7f9      	b.n	60a0 <swap_erase_trailer_sectors+0x60>

000060ac <swap_status_init>:

int
swap_status_init(const struct boot_loader_state *state,
                 const struct flash_area *fap,
                 const struct boot_status *bs)
{
    60ac:	b537      	push	{r0, r1, r2, r4, r5, lr}
    60ae:	4615      	mov	r5, r2
    60b0:	460c      	mov	r4, r1

    image_index = BOOT_CURR_IMG(state);

    BOOT_LOG_DBG("initializing status; fa_id=%d", flash_area_get_id(fap));

    rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_SECONDARY(image_index),
    60b2:	2005      	movs	r0, #5
    60b4:	4669      	mov	r1, sp
    60b6:	f000 fdf0 	bl	6c9a <boot_read_swap_state_by_id>
            &swap_state);
    assert(rc == 0);

    if (bs->swap_type != BOOT_SWAP_TYPE_NONE) {
    60ba:	79e9      	ldrb	r1, [r5, #7]
    60bc:	2901      	cmp	r1, #1
    60be:	d003      	beq.n	60c8 <swap_status_init+0x1c>
        rc = boot_write_swap_info(fap, bs->swap_type, image_index);
    60c0:	2200      	movs	r2, #0
    60c2:	4620      	mov	r0, r4
    60c4:	f000 fdfd 	bl	6cc2 <boot_write_swap_info>
        assert(rc == 0);
    }

    if (swap_state.image_ok == BOOT_FLAG_SET) {
    60c8:	f89d 3003 	ldrb.w	r3, [sp, #3]
    60cc:	2b01      	cmp	r3, #1
    60ce:	d102      	bne.n	60d6 <swap_status_init+0x2a>
        rc = boot_write_image_ok(fap);
    60d0:	4620      	mov	r0, r4
    60d2:	f000 fdd5 	bl	6c80 <boot_write_image_ok>
        assert(rc == 0);
    }

    rc = boot_write_swap_size(fap, bs->swap_size);
    60d6:	68a9      	ldr	r1, [r5, #8]
    60d8:	4620      	mov	r0, r4
    60da:	f7ff fee0 	bl	5e9e <boot_write_swap_size>

    rc = boot_write_enc_key(fap, 1, bs);
    assert(rc == 0);
#endif

    rc = boot_write_magic(fap);
    60de:	4620      	mov	r0, r4
    60e0:	f7fd f9de 	bl	34a0 <boot_write_magic>
    assert(rc == 0);

    return 0;
}
    60e4:	2000      	movs	r0, #0
    60e6:	b003      	add	sp, #12
    60e8:	bd30      	pop	{r4, r5, pc}

000060ea <swap_read_status>:

int
swap_read_status(struct boot_loader_state *state, struct boot_status *bs)
{
    60ea:	b573      	push	{r0, r1, r4, r5, r6, lr}
    60ec:	460d      	mov	r5, r1
    60ee:	4606      	mov	r6, r0
    uint32_t off;
    uint8_t swap_info;
    int area_id;
    int rc;

    bs->source = swap_status_source(state);
    60f0:	f7fa fefc 	bl	eec <swap_status_source>
    60f4:	4604      	mov	r4, r0
    60f6:	60e8      	str	r0, [r5, #12]
    switch (bs->source) {
    60f8:	b350      	cbz	r0, 6150 <swap_read_status+0x66>
    60fa:	2802      	cmp	r0, #2
    60fc:	d12d      	bne.n	615a <swap_read_status+0x70>
    default:
        assert(0);
        return BOOT_EBADARGS;
    }

    rc = flash_area_open(area_id, &fap);
    60fe:	a901      	add	r1, sp, #4
    6100:	f7fb fc74 	bl	19ec <flash_area_open>
    if (rc != 0) {
    6104:	bb58      	cbnz	r0, 615e <swap_read_status+0x74>
        return BOOT_EFLASH;
    }

    rc = swap_read_status_bytes(fap, state, bs);
    6106:	9801      	ldr	r0, [sp, #4]
    6108:	462a      	mov	r2, r5
    610a:	4631      	mov	r1, r6
    610c:	f7fa fe54 	bl	db8 <swap_read_status_bytes>
    if (rc == 0) {
    6110:	4604      	mov	r4, r0
    6112:	b9d0      	cbnz	r0, 614a <swap_read_status+0x60>
        off = boot_swap_info_off(fap);
    6114:	9801      	ldr	r0, [sp, #4]
    6116:	f000 fd3a 	bl	6b8e <boot_swap_info_off>
        rc = flash_area_read(fap, off, &swap_info, sizeof swap_info);
    611a:	2301      	movs	r3, #1
        off = boot_swap_info_off(fap);
    611c:	4601      	mov	r1, r0
        rc = flash_area_read(fap, off, &swap_info, sizeof swap_info);
    611e:	f10d 0203 	add.w	r2, sp, #3
    6122:	9801      	ldr	r0, [sp, #4]
    6124:	f000 fa31 	bl	658a <flash_area_read>
        if (rc != 0) {
    6128:	4604      	mov	r4, r0
    612a:	b9a0      	cbnz	r0, 6156 <swap_read_status+0x6c>
            rc = BOOT_EFLASH;
            goto done;
        }

        if (bootutil_buffer_is_erased(fap, &swap_info, sizeof swap_info)) {
    612c:	9801      	ldr	r0, [sp, #4]
    612e:	2201      	movs	r2, #1
    6130:	f10d 0103 	add.w	r1, sp, #3
    6134:	f000 fd3f 	bl	6bb6 <bootutil_buffer_is_erased>
    6138:	b110      	cbz	r0, 6140 <swap_read_status+0x56>
            BOOT_SET_SWAP_INFO(swap_info, 0, BOOT_SWAP_TYPE_NONE);
    613a:	2301      	movs	r3, #1
    613c:	f88d 3003 	strb.w	r3, [sp, #3]
            rc = 0;
        }

        /* Extract the swap type info */
        bs->swap_type = BOOT_GET_SWAP_TYPE(swap_info);
    6140:	f89d 3003 	ldrb.w	r3, [sp, #3]
    6144:	f003 030f 	and.w	r3, r3, #15
    6148:	71eb      	strb	r3, [r5, #7]
    }

done:
    flash_area_close(fap);
    614a:	9801      	ldr	r0, [sp, #4]
    614c:	f000 fa1c 	bl	6588 <flash_area_close>

    return rc;
}
    6150:	4620      	mov	r0, r4
    6152:	b002      	add	sp, #8
    6154:	bd70      	pop	{r4, r5, r6, pc}
            rc = BOOT_EFLASH;
    6156:	2401      	movs	r4, #1
    6158:	e7f7      	b.n	614a <swap_read_status+0x60>
    switch (bs->source) {
    615a:	2407      	movs	r4, #7
    615c:	e7f8      	b.n	6150 <swap_read_status+0x66>
        return BOOT_EFLASH;
    615e:	2401      	movs	r4, #1
    6160:	e7f6      	b.n	6150 <swap_read_status+0x66>

00006162 <swap_set_copy_done>:

int
swap_set_copy_done(uint8_t image_index)
{
    6162:	b513      	push	{r0, r1, r4, lr}
    const struct flash_area *fap;
    int rc;

    rc = flash_area_open(FLASH_AREA_IMAGE_PRIMARY(image_index),
    6164:	2002      	movs	r0, #2
    6166:	a901      	add	r1, sp, #4
    6168:	f7fb fc40 	bl	19ec <flash_area_open>
            &fap);
    if (rc != 0) {
    616c:	b948      	cbnz	r0, 6182 <swap_set_copy_done+0x20>
        return BOOT_EFLASH;
    }

    rc = boot_write_copy_done(fap);
    616e:	9801      	ldr	r0, [sp, #4]
    6170:	f7ff fe8d 	bl	5e8e <boot_write_copy_done>
    6174:	4604      	mov	r4, r0
    flash_area_close(fap);
    6176:	9801      	ldr	r0, [sp, #4]
    6178:	f000 fa06 	bl	6588 <flash_area_close>
    return rc;
}
    617c:	4620      	mov	r0, r4
    617e:	b002      	add	sp, #8
    6180:	bd10      	pop	{r4, pc}
        return BOOT_EFLASH;
    6182:	2401      	movs	r4, #1
    6184:	e7fa      	b.n	617c <swap_set_copy_done+0x1a>

00006186 <swap_set_image_ok>:

int
swap_set_image_ok(uint8_t image_index)
{
    6186:	b51f      	push	{r0, r1, r2, r3, r4, lr}
    const struct flash_area *fap;
    struct boot_swap_state state;
    int rc;

    rc = flash_area_open(FLASH_AREA_IMAGE_PRIMARY(image_index),
    6188:	2002      	movs	r0, #2
    618a:	a901      	add	r1, sp, #4
    618c:	f7fb fc2e 	bl	19ec <flash_area_open>
            &fap);
    if (rc != 0) {
    6190:	b9a8      	cbnz	r0, 61be <swap_set_image_ok+0x38>
        return BOOT_EFLASH;
    }

    rc = boot_read_swap_state(fap, &state);
    6192:	9801      	ldr	r0, [sp, #4]
    6194:	a902      	add	r1, sp, #8
    6196:	f7fd f9a3 	bl	34e0 <boot_read_swap_state>
    if (rc != 0) {
    619a:	4604      	mov	r4, r0
    619c:	b968      	cbnz	r0, 61ba <swap_set_image_ok+0x34>
        rc = BOOT_EFLASH;
        goto out;
    }

    if (state.image_ok == BOOT_FLAG_UNSET) {
    619e:	f89d 300b 	ldrb.w	r3, [sp, #11]
    61a2:	2b03      	cmp	r3, #3
    61a4:	d103      	bne.n	61ae <swap_set_image_ok+0x28>
        rc = boot_write_image_ok(fap);
    61a6:	9801      	ldr	r0, [sp, #4]
    61a8:	f000 fd6a 	bl	6c80 <boot_write_image_ok>
    61ac:	4604      	mov	r4, r0
    }

out:
    flash_area_close(fap);
    61ae:	9801      	ldr	r0, [sp, #4]
    61b0:	f000 f9ea 	bl	6588 <flash_area_close>
    return rc;
}
    61b4:	4620      	mov	r0, r4
    61b6:	b004      	add	sp, #16
    61b8:	bd10      	pop	{r4, pc}
        rc = BOOT_EFLASH;
    61ba:	2401      	movs	r4, #1
    61bc:	e7f7      	b.n	61ae <swap_set_image_ok+0x28>
        return BOOT_EFLASH;
    61be:	2401      	movs	r4, #1
    61c0:	e7f8      	b.n	61b4 <swap_set_image_ok+0x2e>

000061c2 <boot_status_internal_off>:
{
    61c2:	b510      	push	{r4, lr}
            BOOT_STATUS_MOVE_STATE_COUNT : BOOT_STATUS_SWAP_STATE_COUNT);
    61c4:	7943      	ldrb	r3, [r0, #5]
           (bs->state - BOOT_STATUS_STATE_0) * elem_sz;
    61c6:	7902      	ldrb	r2, [r0, #4]
            BOOT_STATUS_MOVE_STATE_COUNT : BOOT_STATUS_SWAP_STATE_COUNT);
    61c8:	2b01      	cmp	r3, #1
               0 : (BOOT_MAX_IMG_SECTORS * BOOT_STATUS_MOVE_STATE_COUNT * elem_sz)) +
    61ca:	bf14      	ite	ne
    61cc:	01cb      	lslne	r3, r1, #7
    61ce:	2300      	moveq	r3, #0
           (bs->state - BOOT_STATUS_STATE_0) * elem_sz;
    61d0:	f102 32ff 	add.w	r2, r2, #4294967295
    off = ((bs->op == BOOT_STATUS_OP_MOVE) ?
    61d4:	fb01 3302 	mla	r3, r1, r2, r3
           (bs->idx - BOOT_STATUS_IDX_0) * idx_sz +
    61d8:	6802      	ldr	r2, [r0, #0]
    idx_sz = elem_sz * ((bs->op == BOOT_STATUS_OP_MOVE) ?
    61da:	bf14      	ite	ne
    61dc:	004c      	lslne	r4, r1, #1
    61de:	460c      	moveq	r4, r1
           (bs->idx - BOOT_STATUS_IDX_0) * idx_sz +
    61e0:	3a01      	subs	r2, #1
}
    61e2:	fb04 3002 	mla	r0, r4, r2, r3
    61e6:	bd10      	pop	{r4, pc}

000061e8 <mbedtls_asn1_get_len>:
 * ASN.1 DER decoding routines
 */
int mbedtls_asn1_get_len( unsigned char **p,
                  const unsigned char *end,
                  size_t *len )
{
    61e8:	b570      	push	{r4, r5, r6, lr}
    if( ( end - *p ) < 1 )
    61ea:	6803      	ldr	r3, [r0, #0]
    61ec:	1acd      	subs	r5, r1, r3
    61ee:	2d00      	cmp	r5, #0
    61f0:	dc02      	bgt.n	61f8 <mbedtls_asn1_get_len+0x10>
        return( MBEDTLS_ERR_ASN1_OUT_OF_DATA );
    61f2:	f06f 005f 	mvn.w	r0, #95	; 0x5f

    if( *len > (size_t) ( end - *p ) )
        return( MBEDTLS_ERR_ASN1_OUT_OF_DATA );

    return( 0 );
}
    61f6:	bd70      	pop	{r4, r5, r6, pc}
    if( ( **p & 0x80 ) == 0 )
    61f8:	f993 6000 	ldrsb.w	r6, [r3]
    61fc:	781c      	ldrb	r4, [r3, #0]
    61fe:	2e00      	cmp	r6, #0
    6200:	db0a      	blt.n	6218 <mbedtls_asn1_get_len+0x30>
        *len = *(*p)++;
    6202:	1c5c      	adds	r4, r3, #1
    6204:	6004      	str	r4, [r0, #0]
    6206:	781b      	ldrb	r3, [r3, #0]
    6208:	6013      	str	r3, [r2, #0]
    if( *len > (size_t) ( end - *p ) )
    620a:	6803      	ldr	r3, [r0, #0]
    620c:	1ac9      	subs	r1, r1, r3
    620e:	6813      	ldr	r3, [r2, #0]
    6210:	428b      	cmp	r3, r1
    6212:	d8ee      	bhi.n	61f2 <mbedtls_asn1_get_len+0xa>
    return( 0 );
    6214:	2000      	movs	r0, #0
    6216:	e7ee      	b.n	61f6 <mbedtls_asn1_get_len+0xe>
        switch( **p & 0x7F )
    6218:	f004 047f 	and.w	r4, r4, #127	; 0x7f
    621c:	3c01      	subs	r4, #1
    621e:	2c03      	cmp	r4, #3
    6220:	d82b      	bhi.n	627a <mbedtls_asn1_get_len+0x92>
    6222:	e8df f004 	tbb	[pc, r4]
    6226:	0a02      	.short	0x0a02
    6228:	2114      	.short	0x2114
            if( ( end - *p ) < 2 )
    622a:	2d01      	cmp	r5, #1
    622c:	d0e1      	beq.n	61f2 <mbedtls_asn1_get_len+0xa>
            *len = (*p)[1];
    622e:	785b      	ldrb	r3, [r3, #1]
    6230:	6013      	str	r3, [r2, #0]
            (*p) += 2;
    6232:	6803      	ldr	r3, [r0, #0]
    6234:	3302      	adds	r3, #2
            (*p) += 5;
    6236:	6003      	str	r3, [r0, #0]
            break;
    6238:	e7e7      	b.n	620a <mbedtls_asn1_get_len+0x22>
            if( ( end - *p ) < 3 )
    623a:	2d02      	cmp	r5, #2
    623c:	ddd9      	ble.n	61f2 <mbedtls_asn1_get_len+0xa>
            *len = ( (size_t)(*p)[1] << 8 ) | (*p)[2];
    623e:	f8b3 3001 	ldrh.w	r3, [r3, #1]
    6242:	ba5b      	rev16	r3, r3
    6244:	b29b      	uxth	r3, r3
    6246:	6013      	str	r3, [r2, #0]
            (*p) += 3;
    6248:	6803      	ldr	r3, [r0, #0]
    624a:	3303      	adds	r3, #3
    624c:	e7f3      	b.n	6236 <mbedtls_asn1_get_len+0x4e>
            if( ( end - *p ) < 4 )
    624e:	2d03      	cmp	r5, #3
    6250:	ddcf      	ble.n	61f2 <mbedtls_asn1_get_len+0xa>
                   ( (size_t)(*p)[2] << 8  ) | (*p)[3];
    6252:	789c      	ldrb	r4, [r3, #2]
            *len = ( (size_t)(*p)[1] << 16 ) |
    6254:	785d      	ldrb	r5, [r3, #1]
                   ( (size_t)(*p)[2] << 8  ) | (*p)[3];
    6256:	78db      	ldrb	r3, [r3, #3]
    6258:	0224      	lsls	r4, r4, #8
            *len = ( (size_t)(*p)[1] << 16 ) |
    625a:	ea44 4405 	orr.w	r4, r4, r5, lsl #16
                   ( (size_t)(*p)[2] << 8  ) | (*p)[3];
    625e:	4323      	orrs	r3, r4
            *len = ( (size_t)(*p)[1] << 16 ) |
    6260:	6013      	str	r3, [r2, #0]
            (*p) += 4;
    6262:	6803      	ldr	r3, [r0, #0]
    6264:	3304      	adds	r3, #4
    6266:	e7e6      	b.n	6236 <mbedtls_asn1_get_len+0x4e>
            if( ( end - *p ) < 5 )
    6268:	2d04      	cmp	r5, #4
    626a:	ddc2      	ble.n	61f2 <mbedtls_asn1_get_len+0xa>
            *len = ( (size_t)(*p)[1] << 24 ) | ( (size_t)(*p)[2] << 16 ) |
    626c:	f8d3 3001 	ldr.w	r3, [r3, #1]
    6270:	ba1b      	rev	r3, r3
    6272:	6013      	str	r3, [r2, #0]
            (*p) += 5;
    6274:	6803      	ldr	r3, [r0, #0]
    6276:	3305      	adds	r3, #5
    6278:	e7dd      	b.n	6236 <mbedtls_asn1_get_len+0x4e>
        switch( **p & 0x7F )
    627a:	f06f 0063 	mvn.w	r0, #99	; 0x63
    627e:	e7ba      	b.n	61f6 <mbedtls_asn1_get_len+0xe>

00006280 <mbedtls_asn1_get_tag>:

int mbedtls_asn1_get_tag( unsigned char **p,
                  const unsigned char *end,
                  size_t *len, int tag )
{
    6280:	b470      	push	{r4, r5, r6}
    if( ( end - *p ) < 1 )
    6282:	6804      	ldr	r4, [r0, #0]
    6284:	1b0e      	subs	r6, r1, r4
    6286:	2e00      	cmp	r6, #0
    6288:	dd07      	ble.n	629a <mbedtls_asn1_get_tag+0x1a>
        return( MBEDTLS_ERR_ASN1_OUT_OF_DATA );

    if( **p != tag )
    628a:	7826      	ldrb	r6, [r4, #0]
    628c:	429e      	cmp	r6, r3
    628e:	d108      	bne.n	62a2 <mbedtls_asn1_get_tag+0x22>
        return( MBEDTLS_ERR_ASN1_UNEXPECTED_TAG );

    (*p)++;
    6290:	3401      	adds	r4, #1
    6292:	6004      	str	r4, [r0, #0]

    return( mbedtls_asn1_get_len( p, end, len ) );
}
    6294:	bc70      	pop	{r4, r5, r6}
    return( mbedtls_asn1_get_len( p, end, len ) );
    6296:	f7ff bfa7 	b.w	61e8 <mbedtls_asn1_get_len>
        return( MBEDTLS_ERR_ASN1_OUT_OF_DATA );
    629a:	f06f 005f 	mvn.w	r0, #95	; 0x5f
}
    629e:	bc70      	pop	{r4, r5, r6}
    62a0:	4770      	bx	lr
        return( MBEDTLS_ERR_ASN1_UNEXPECTED_TAG );
    62a2:	f06f 0061 	mvn.w	r0, #97	; 0x61
    62a6:	e7fa      	b.n	629e <mbedtls_asn1_get_tag+0x1e>

000062a8 <mbedtls_asn1_get_bitstring_null>:
/*
 * Get a bit string without unused bits
 */
int mbedtls_asn1_get_bitstring_null( unsigned char **p, const unsigned char *end,
                             size_t *len )
{
    62a8:	b538      	push	{r3, r4, r5, lr}
    int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED;

    if( ( ret = mbedtls_asn1_get_tag( p, end, len, MBEDTLS_ASN1_BIT_STRING ) ) != 0 )
    62aa:	2303      	movs	r3, #3
{
    62ac:	4604      	mov	r4, r0
    if( ( ret = mbedtls_asn1_get_tag( p, end, len, MBEDTLS_ASN1_BIT_STRING ) ) != 0 )
    62ae:	f7ff ffe7 	bl	6280 <mbedtls_asn1_get_tag>
    62b2:	b918      	cbnz	r0, 62bc <mbedtls_asn1_get_bitstring_null+0x14>
        return( ret );

    if( *len == 0 )
    62b4:	6813      	ldr	r3, [r2, #0]
    62b6:	b913      	cbnz	r3, 62be <mbedtls_asn1_get_bitstring_null+0x16>
        return( MBEDTLS_ERR_ASN1_INVALID_DATA );
    62b8:	f06f 0067 	mvn.w	r0, #103	; 0x67
    if( **p != 0 )
        return( MBEDTLS_ERR_ASN1_INVALID_DATA );
    ++( *p );

    return( 0 );
}
    62bc:	bd38      	pop	{r3, r4, r5, pc}
    --( *len );
    62be:	3b01      	subs	r3, #1
    62c0:	6013      	str	r3, [r2, #0]
    if( **p != 0 )
    62c2:	6823      	ldr	r3, [r4, #0]
    62c4:	781a      	ldrb	r2, [r3, #0]
    62c6:	2a00      	cmp	r2, #0
    62c8:	d1f6      	bne.n	62b8 <mbedtls_asn1_get_bitstring_null+0x10>
    ++( *p );
    62ca:	3301      	adds	r3, #1
    62cc:	6023      	str	r3, [r4, #0]
    return( 0 );
    62ce:	e7f5      	b.n	62bc <mbedtls_asn1_get_bitstring_null+0x14>

000062d0 <mbedtls_asn1_get_alg>:
}

int mbedtls_asn1_get_alg( unsigned char **p,
                  const unsigned char *end,
                  mbedtls_asn1_buf *alg, mbedtls_asn1_buf *params )
{
    62d0:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
    62d4:	4690      	mov	r8, r2
    62d6:	461f      	mov	r7, r3
    int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED;
    size_t len;

    if( ( ret = mbedtls_asn1_get_tag( p, end, &len,
    62d8:	aa01      	add	r2, sp, #4
    62da:	2330      	movs	r3, #48	; 0x30
{
    62dc:	4605      	mov	r5, r0
    62de:	460e      	mov	r6, r1
    if( ( ret = mbedtls_asn1_get_tag( p, end, &len,
    62e0:	f7ff ffce 	bl	6280 <mbedtls_asn1_get_tag>
    62e4:	4604      	mov	r4, r0
    62e6:	b9f0      	cbnz	r0, 6326 <mbedtls_asn1_get_alg+0x56>
            MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) ) != 0 )
        return( ret );

    if( ( end - *p ) < 1 )
    62e8:	682b      	ldr	r3, [r5, #0]
    62ea:	1af6      	subs	r6, r6, r3
    62ec:	2e00      	cmp	r6, #0
    62ee:	dd34      	ble.n	635a <mbedtls_asn1_get_alg+0x8a>
        return( MBEDTLS_ERR_ASN1_OUT_OF_DATA );

    alg->tag = **p;
    62f0:	4642      	mov	r2, r8
    62f2:	781b      	ldrb	r3, [r3, #0]
    62f4:	f842 3b04 	str.w	r3, [r2], #4
    end = *p + len;
    62f8:	9b01      	ldr	r3, [sp, #4]
    62fa:	682e      	ldr	r6, [r5, #0]
    62fc:	441e      	add	r6, r3

    if( ( ret = mbedtls_asn1_get_tag( p, end, &alg->len, MBEDTLS_ASN1_OID ) ) != 0 )
    62fe:	4631      	mov	r1, r6
    6300:	2306      	movs	r3, #6
    6302:	4628      	mov	r0, r5
    6304:	f7ff ffbc 	bl	6280 <mbedtls_asn1_get_tag>
    6308:	4604      	mov	r4, r0
    630a:	b960      	cbnz	r0, 6326 <mbedtls_asn1_get_alg+0x56>
        return( ret );

    alg->p = *p;
    630c:	682b      	ldr	r3, [r5, #0]
    *p += alg->len;
    630e:	f8d8 2004 	ldr.w	r2, [r8, #4]
    alg->p = *p;
    6312:	f8c8 3008 	str.w	r3, [r8, #8]
    *p += alg->len;
    6316:	1899      	adds	r1, r3, r2

    if( *p == end )
    6318:	42b1      	cmp	r1, r6
    *p += alg->len;
    631a:	6029      	str	r1, [r5, #0]
    if( *p == end )
    631c:	d107      	bne.n	632e <mbedtls_asn1_get_alg+0x5e>
    {
        mbedtls_platform_zeroize( params, sizeof(mbedtls_asn1_buf) );
    631e:	210c      	movs	r1, #12
    6320:	4638      	mov	r0, r7
    6322:	f7fe f953 	bl	45cc <mbedtls_platform_zeroize>

    if( *p != end )
        return( MBEDTLS_ERR_ASN1_LENGTH_MISMATCH );

    return( 0 );
}
    6326:	4620      	mov	r0, r4
    6328:	b002      	add	sp, #8
    632a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    params->tag = **p;
    632e:	5c9b      	ldrb	r3, [r3, r2]
    6330:	463a      	mov	r2, r7
    if( ( ret = mbedtls_asn1_get_len( p, end, &params->len ) ) != 0 )
    6332:	4631      	mov	r1, r6
    params->tag = **p;
    6334:	f842 3b04 	str.w	r3, [r2], #4
    (*p)++;
    6338:	682b      	ldr	r3, [r5, #0]
    633a:	3301      	adds	r3, #1
    633c:	602b      	str	r3, [r5, #0]
    if( ( ret = mbedtls_asn1_get_len( p, end, &params->len ) ) != 0 )
    633e:	4628      	mov	r0, r5
    6340:	f7ff ff52 	bl	61e8 <mbedtls_asn1_get_len>
    6344:	b960      	cbnz	r0, 6360 <mbedtls_asn1_get_alg+0x90>
    params->p = *p;
    6346:	682b      	ldr	r3, [r5, #0]
    *p += params->len;
    6348:	687a      	ldr	r2, [r7, #4]
    params->p = *p;
    634a:	60bb      	str	r3, [r7, #8]
    *p += params->len;
    634c:	4413      	add	r3, r2
        return( MBEDTLS_ERR_ASN1_LENGTH_MISMATCH );
    634e:	42b3      	cmp	r3, r6
    *p += params->len;
    6350:	602b      	str	r3, [r5, #0]
        return( MBEDTLS_ERR_ASN1_LENGTH_MISMATCH );
    6352:	bf18      	it	ne
    6354:	f06f 0465 	mvnne.w	r4, #101	; 0x65
    6358:	e7e5      	b.n	6326 <mbedtls_asn1_get_alg+0x56>
        return( MBEDTLS_ERR_ASN1_OUT_OF_DATA );
    635a:	f06f 045f 	mvn.w	r4, #95	; 0x5f
    635e:	e7e2      	b.n	6326 <mbedtls_asn1_get_alg+0x56>
    6360:	4604      	mov	r4, r0
    6362:	e7e0      	b.n	6326 <mbedtls_asn1_get_alg+0x56>

00006364 <cc310_sha256_update>:
{
    6364:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    if ((uint32_t) data < CONFIG_SRAM_BASE_ADDRESS) {
    6366:	f1b1 5f00 	cmp.w	r1, #536870912	; 0x20000000
{
    636a:	af00      	add	r7, sp, #0
    636c:	4605      	mov	r5, r0
    636e:	4614      	mov	r4, r2
    if ((uint32_t) data < CONFIG_SRAM_BASE_ADDRESS) {
    6370:	d210      	bcs.n	6394 <cc310_sha256_update+0x30>
        uint8_t stack_buffer[data_len];
    6372:	1dd3      	adds	r3, r2, #7
    6374:	f023 0307 	bic.w	r3, r3, #7
    if ((uint32_t) data < CONFIG_SRAM_BASE_ADDRESS) {
    6378:	466e      	mov	r6, sp
        uint8_t stack_buffer[data_len];
    637a:	ebad 0d03 	sub.w	sp, sp, r3
        memcpy(stack_buffer, data, block_len);
    637e:	4668      	mov	r0, sp
    6380:	f000 f9a8 	bl	66d4 <memcpy>
        nrf_cc310_bl_hash_sha256_update(ctx, stack_buffer, block_len);
    6384:	4669      	mov	r1, sp
    6386:	4622      	mov	r2, r4
    6388:	4628      	mov	r0, r5
    638a:	f7fe fbe9 	bl	4b60 <nrf_cc310_bl_hash_sha256_update>
    638e:	46b5      	mov	sp, r6
};
    6390:	46bd      	mov	sp, r7
    6392:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
        nrf_cc310_bl_hash_sha256_update(ctx, data, data_len);
    6394:	f7fe fbe4 	bl	4b60 <nrf_cc310_bl_hash_sha256_update>
};
    6398:	e7fa      	b.n	6390 <cc310_sha256_update+0x2c>

0000639a <arch_printk_char_out>:
}
    639a:	2000      	movs	r0, #0
    639c:	4770      	bx	lr

0000639e <printk>:
 *
 * @param fmt formatted string to output
 */

void printk(const char *fmt, ...)
{
    639e:	b40f      	push	{r0, r1, r2, r3}
    63a0:	b507      	push	{r0, r1, r2, lr}
    63a2:	a904      	add	r1, sp, #16
    63a4:	f851 0b04 	ldr.w	r0, [r1], #4
	va_list ap;

	va_start(ap, fmt);
    63a8:	9101      	str	r1, [sp, #4]

	vprintk(fmt, ap);
    63aa:	f7fa ffcd 	bl	1348 <vprintk>

	va_end(ap);
}
    63ae:	b003      	add	sp, #12
    63b0:	f85d eb04 	ldr.w	lr, [sp], #4
    63b4:	b004      	add	sp, #16
    63b6:	4770      	bx	lr

000063b8 <process_recheck>:
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    63b8:	8b03      	ldrh	r3, [r0, #24]
	if ((state == ONOFF_STATE_OFF)
    63ba:	f013 0307 	ands.w	r3, r3, #7
    63be:	d105      	bne.n	63cc <process_recheck+0x14>
	    && !sys_slist_is_empty(&mgr->clients)) {
    63c0:	6803      	ldr	r3, [r0, #0]
		evt = EVT_START;
    63c2:	2b00      	cmp	r3, #0
    63c4:	bf0c      	ite	eq
    63c6:	2000      	moveq	r0, #0
    63c8:	2003      	movne	r0, #3
    63ca:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ON)
    63cc:	2b02      	cmp	r3, #2
    63ce:	d105      	bne.n	63dc <process_recheck+0x24>
		   && (mgr->refs == 0U)) {
    63d0:	8b40      	ldrh	r0, [r0, #26]
    63d2:	fab0 f080 	clz	r0, r0
    63d6:	0940      	lsrs	r0, r0, #5
    63d8:	0080      	lsls	r0, r0, #2
    63da:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ERROR)
    63dc:	2b01      	cmp	r3, #1
    63de:	d105      	bne.n	63ec <process_recheck+0x34>
		   && !sys_slist_is_empty(&mgr->clients)) {
    63e0:	6803      	ldr	r3, [r0, #0]
		evt = EVT_RESET;
    63e2:	2b00      	cmp	r3, #0
    63e4:	bf0c      	ite	eq
    63e6:	2000      	moveq	r0, #0
    63e8:	2005      	movne	r0, #5
    63ea:	4770      	bx	lr
	int evt = EVT_NOP;
    63ec:	2000      	movs	r0, #0
}
    63ee:	4770      	bx	lr

000063f0 <validate_args>:
{
    63f0:	b510      	push	{r4, lr}
    63f2:	460c      	mov	r4, r1
	if ((mgr == NULL) || (cli == NULL)) {
    63f4:	b100      	cbz	r0, 63f8 <validate_args+0x8>
    63f6:	b911      	cbnz	r1, 63fe <validate_args+0xe>
		return -EINVAL;
    63f8:	f06f 0015 	mvn.w	r0, #21
}
    63fc:	bd10      	pop	{r4, pc}
	int rv = sys_notify_validate(&cli->notify);
    63fe:	1d08      	adds	r0, r1, #4
    6400:	f000 f896 	bl	6530 <sys_notify_validate>
	if ((rv == 0)
    6404:	2800      	cmp	r0, #0
    6406:	d1f9      	bne.n	63fc <validate_args+0xc>
	    && ((cli->notify.flags
    6408:	68a3      	ldr	r3, [r4, #8]
    640a:	2b03      	cmp	r3, #3
    640c:	d9f6      	bls.n	63fc <validate_args+0xc>
    640e:	e7f3      	b.n	63f8 <validate_args+0x8>

00006410 <notify_one>:
{
    6410:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    6414:	460d      	mov	r5, r1
    6416:	4607      	mov	r7, r0
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    6418:	4619      	mov	r1, r3
    641a:	1d28      	adds	r0, r5, #4
{
    641c:	4690      	mov	r8, r2
    641e:	461e      	mov	r6, r3
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    6420:	f000 f897 	bl	6552 <sys_notify_finalize>
	if (cb) {
    6424:	4604      	mov	r4, r0
    6426:	b138      	cbz	r0, 6438 <notify_one+0x28>
		cb(mgr, cli, state, res);
    6428:	4633      	mov	r3, r6
    642a:	4642      	mov	r2, r8
    642c:	4629      	mov	r1, r5
    642e:	4638      	mov	r0, r7
    6430:	46a4      	mov	ip, r4
}
    6432:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
		cb(mgr, cli, state, res);
    6436:	4760      	bx	ip
}
    6438:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

0000643c <transition_complete>:
{
    643c:	b410      	push	{r4}
    643e:	f04f 0420 	mov.w	r4, #32
    6442:	f3ef 8211 	mrs	r2, BASEPRI
    6446:	f384 8812 	msr	BASEPRI_MAX, r4
    644a:	f3bf 8f6f 	isb	sy
	mgr->last_res = res;
    644e:	6141      	str	r1, [r0, #20]
}
    6450:	f85d 4b04 	ldr.w	r4, [sp], #4
	process_event(mgr, EVT_COMPLETE, key);
    6454:	2101      	movs	r1, #1
    6456:	f7fa bf85 	b.w	1364 <process_event>

0000645a <onoff_manager_init>:
{
    645a:	b538      	push	{r3, r4, r5, lr}
    645c:	460c      	mov	r4, r1
	if ((mgr == NULL)
    645e:	4605      	mov	r5, r0
    6460:	b158      	cbz	r0, 647a <onoff_manager_init+0x20>
	    || (transitions == NULL)
    6462:	b151      	cbz	r1, 647a <onoff_manager_init+0x20>
	    || (transitions->start == NULL)
    6464:	680b      	ldr	r3, [r1, #0]
    6466:	b143      	cbz	r3, 647a <onoff_manager_init+0x20>
	    || (transitions->stop == NULL)) {
    6468:	684b      	ldr	r3, [r1, #4]
    646a:	b133      	cbz	r3, 647a <onoff_manager_init+0x20>
	*mgr = (struct onoff_manager)ONOFF_MANAGER_INITIALIZER(transitions);
    646c:	221c      	movs	r2, #28
    646e:	2100      	movs	r1, #0
    6470:	f000 f93b 	bl	66ea <memset>
    6474:	612c      	str	r4, [r5, #16]
	return 0;
    6476:	2000      	movs	r0, #0
}
    6478:	bd38      	pop	{r3, r4, r5, pc}
		return -EINVAL;
    647a:	f06f 0015 	mvn.w	r0, #21
    647e:	e7fb      	b.n	6478 <onoff_manager_init+0x1e>

00006480 <onoff_request>:

int onoff_request(struct onoff_manager *mgr,
		  struct onoff_client *cli)
{
    6480:	b570      	push	{r4, r5, r6, lr}
    6482:	4605      	mov	r5, r0
    6484:	460e      	mov	r6, r1
	bool add_client = false;        /* add client to pending list */
	bool start = false;             /* trigger a start transition */
	bool notify = false;            /* do client notification */
	int rv = validate_args(mgr, cli);
    6486:	f7ff ffb3 	bl	63f0 <validate_args>

	if (rv < 0) {
    648a:	1e04      	subs	r4, r0, #0
    648c:	db15      	blt.n	64ba <onoff_request+0x3a>
    648e:	f04f 0320 	mov.w	r3, #32
    6492:	f3ef 8211 	mrs	r2, BASEPRI
    6496:	f383 8812 	msr	BASEPRI_MAX, r3
    649a:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&mgr->lock);
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;

	/* Reject if this would overflow the reference count. */
	if (mgr->refs == SERVICE_REFS_MAX) {
    649e:	8b6b      	ldrh	r3, [r5, #26]
    64a0:	8b2c      	ldrh	r4, [r5, #24]
    64a2:	f64f 71ff 	movw	r1, #65535	; 0xffff
    64a6:	428b      	cmp	r3, r1
    64a8:	f004 0407 	and.w	r4, r4, #7
    64ac:	d107      	bne.n	64be <onoff_request+0x3e>
	__asm__ volatile(
    64ae:	f382 8811 	msr	BASEPRI, r2
    64b2:	f3bf 8f6f 	isb	sy
		rv = -EAGAIN;
    64b6:	f06f 040a 	mvn.w	r4, #10
			notify_one(mgr, cli, state, 0);
		}
	}

	return rv;
}
    64ba:	4620      	mov	r0, r4
    64bc:	bd70      	pop	{r4, r5, r6, pc}
	if (state == ONOFF_STATE_ON) {
    64be:	2c02      	cmp	r4, #2
    64c0:	d10c      	bne.n	64dc <onoff_request+0x5c>
		mgr->refs += 1U;
    64c2:	3301      	adds	r3, #1
    64c4:	836b      	strh	r3, [r5, #26]
    64c6:	f382 8811 	msr	BASEPRI, r2
    64ca:	f3bf 8f6f 	isb	sy
			notify_one(mgr, cli, state, 0);
    64ce:	2300      	movs	r3, #0
    64d0:	4622      	mov	r2, r4
    64d2:	4631      	mov	r1, r6
    64d4:	4628      	mov	r0, r5
    64d6:	f7ff ff9b 	bl	6410 <notify_one>
    64da:	e7ee      	b.n	64ba <onoff_request+0x3a>
	} else if ((state == ONOFF_STATE_OFF)
    64dc:	2c06      	cmp	r4, #6
    64de:	d814      	bhi.n	650a <onoff_request+0x8a>
    64e0:	e8df f004 	tbb	[pc, r4]
    64e4:	13131304 	.word	0x13131304
    64e8:	1a04      	.short	0x1a04
    64ea:	04          	.byte	0x04
    64eb:	00          	.byte	0x00
	parent->next = child;
    64ec:	2300      	movs	r3, #0
    64ee:	6033      	str	r3, [r6, #0]
 *
 * @return A pointer on the last node of the list (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_tail(sys_slist_t *list)
{
	return list->tail;
    64f0:	686b      	ldr	r3, [r5, #4]
 * @param node A pointer on the node to append
 */
static inline void sys_slist_append(sys_slist_t *list,
				    sys_snode_t *node);

Z_GENLIST_APPEND(slist, snode)
    64f2:	b93b      	cbnz	r3, 6504 <onoff_request+0x84>
	list->head = node;
    64f4:	e9c5 6600 	strd	r6, r6, [r5]
	if (start) {
    64f8:	b9ac      	cbnz	r4, 6526 <onoff_request+0xa6>
		process_event(mgr, EVT_RECHECK, key);
    64fa:	2102      	movs	r1, #2
    64fc:	4628      	mov	r0, r5
    64fe:	f7fa ff31 	bl	1364 <process_event>
    6502:	e7da      	b.n	64ba <onoff_request+0x3a>
	parent->next = child;
    6504:	601e      	str	r6, [r3, #0]
	list->tail = node;
    6506:	606e      	str	r6, [r5, #4]
}
    6508:	e7f6      	b.n	64f8 <onoff_request+0x78>
    650a:	f382 8811 	msr	BASEPRI, r2
    650e:	f3bf 8f6f 	isb	sy
		rv = -EIO;
    6512:	f06f 0404 	mvn.w	r4, #4
    6516:	e7d0      	b.n	64ba <onoff_request+0x3a>
    6518:	f382 8811 	msr	BASEPRI, r2
    651c:	f3bf 8f6f 	isb	sy
    6520:	f06f 0485 	mvn.w	r4, #133	; 0x85
    6524:	e7c9      	b.n	64ba <onoff_request+0x3a>
    6526:	f382 8811 	msr	BASEPRI, r2
    652a:	f3bf 8f6f 	isb	sy
		if (notify) {
    652e:	e7c4      	b.n	64ba <onoff_request+0x3a>

00006530 <sys_notify_validate>:

int sys_notify_validate(struct sys_notify *notify)
{
	int rv = 0;

	if (notify == NULL) {
    6530:	4603      	mov	r3, r0
    6532:	b158      	cbz	r0, 654c <sys_notify_validate+0x1c>
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    6534:	6842      	ldr	r2, [r0, #4]
	return method & SYS_NOTIFY_METHOD_MASK;
    6536:	f002 0203 	and.w	r2, r2, #3
		return -EINVAL;
	}

	/* Validate configuration based on mode */
	switch (sys_notify_get_method(notify)) {
    653a:	2a01      	cmp	r2, #1
    653c:	d003      	beq.n	6546 <sys_notify_validate+0x16>
    653e:	2a03      	cmp	r2, #3
    6540:	d104      	bne.n	654c <sys_notify_validate+0x1c>
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		if (notify->method.callback == NULL) {
    6542:	6802      	ldr	r2, [r0, #0]
    6544:	b112      	cbz	r2, 654c <sys_notify_validate+0x1c>
		break;
	}

	/* Clear the result here instead of in all callers. */
	if (rv == 0) {
		notify->result = 0;
    6546:	2000      	movs	r0, #0
    6548:	6098      	str	r0, [r3, #8]
    654a:	4770      	bx	lr
    654c:	f06f 0015 	mvn.w	r0, #21
	}

	return rv;
}
    6550:	4770      	bx	lr

00006552 <sys_notify_finalize>:
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    6552:	6842      	ldr	r2, [r0, #4]
	uint32_t method = sys_notify_get_method(notify);

	/* Store the result and capture secondary notification
	 * information.
	 */
	notify->result = res;
    6554:	6081      	str	r1, [r0, #8]
	return method & SYS_NOTIFY_METHOD_MASK;
    6556:	f002 0203 	and.w	r2, r2, #3
	switch (method) {
    655a:	2a03      	cmp	r2, #3
    655c:	f04f 0200 	mov.w	r2, #0
{
    6560:	4603      	mov	r3, r0
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		rv = notify->method.callback;
    6562:	bf0c      	ite	eq
    6564:	6800      	ldreq	r0, [r0, #0]
	sys_notify_generic_callback rv = NULL;
    6566:	4610      	movne	r0, r2
	/* Mark completion by clearing the flags field to the
	 * completed state, releasing any spin-waiters, then complete
	 * secondary notification.
	 */
	compiler_barrier();
	notify->flags = SYS_NOTIFY_METHOD_COMPLETED;
    6568:	605a      	str	r2, [r3, #4]
	if (IS_ENABLED(CONFIG_POLL) && (sig != NULL)) {
		k_poll_signal_raise(sig, res);
	}

	return rv;
}
    656a:	4770      	bx	lr

0000656c <_ConfigAbsSyms>:
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_BUILD_OUTPUT_META, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_WARN_DEPRECATED, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_ENFORCE_ZEPHYR_STDINT, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_COMPAT_INCLUDES, 1);

GEN_ABS_SYM_END
    656c:	4770      	bx	lr

0000656e <z_log_minimal_printk>:
#include <zephyr/sys/printk.h>

#define HEXDUMP_BYTES_IN_LINE 8U

void z_log_minimal_printk(const char *fmt, ...)
{
    656e:	b40f      	push	{r0, r1, r2, r3}
    6570:	b507      	push	{r0, r1, r2, lr}
    6572:	a904      	add	r1, sp, #16
    6574:	f851 0b04 	ldr.w	r0, [r1], #4
	va_list ap;

	va_start(ap, fmt);
    6578:	9101      	str	r1, [sp, #4]
	vprintk(fmt, ap);
    657a:	f7fa fee5 	bl	1348 <vprintk>
	va_end(ap);
}
    657e:	b003      	add	sp, #12
    6580:	f85d eb04 	ldr.w	lr, [sp], #4
    6584:	b004      	add	sp, #16
    6586:	4770      	bx	lr

00006588 <flash_area_close>:

void flash_area_close(const struct flash_area *fa)
{
	/* nothing to do for now */
}
    6588:	4770      	bx	lr

0000658a <flash_area_read>:


static inline bool is_in_flash_area_bounds(const struct flash_area *fa,
					   off_t off, size_t len)
{
	return (off >= 0) && ((off + len) <= fa->fa_size);
    658a:	2900      	cmp	r1, #0

int flash_area_read(const struct flash_area *fa, off_t off, void *dst,
		    size_t len)
{
    658c:	b430      	push	{r4, r5}
    658e:	4604      	mov	r4, r0
    6590:	4618      	mov	r0, r3
    6592:	db0b      	blt.n	65ac <flash_area_read+0x22>
    6594:	68a5      	ldr	r5, [r4, #8]
    6596:	4408      	add	r0, r1
    6598:	42a8      	cmp	r0, r5
    659a:	d807      	bhi.n	65ac <flash_area_read+0x22>
	if (!is_in_flash_area_bounds(fa, off, len)) {
		return -EINVAL;
	}

	return flash_read(fa->fa_dev, fa->fa_off + off, dst, len);
    659c:	68e0      	ldr	r0, [r4, #12]
    659e:	6864      	ldr	r4, [r4, #4]
    65a0:	4421      	add	r1, r4
				    size_t len)
{
	const struct flash_driver_api *api =
		(const struct flash_driver_api *)dev->api;

	return api->read(dev, offset, data, len);
    65a2:	6884      	ldr	r4, [r0, #8]
    65a4:	6824      	ldr	r4, [r4, #0]
    65a6:	46a4      	mov	ip, r4
}
    65a8:	bc30      	pop	{r4, r5}
    65aa:	4760      	bx	ip
    65ac:	f06f 0015 	mvn.w	r0, #21
    65b0:	bc30      	pop	{r4, r5}
    65b2:	4770      	bx	lr

000065b4 <flash_area_write>:
    65b4:	2900      	cmp	r1, #0

int flash_area_write(const struct flash_area *fa, off_t off, const void *src,
		     size_t len)
{
    65b6:	b430      	push	{r4, r5}
    65b8:	4604      	mov	r4, r0
    65ba:	4618      	mov	r0, r3
    65bc:	db0b      	blt.n	65d6 <flash_area_write+0x22>
    65be:	68a5      	ldr	r5, [r4, #8]
    65c0:	4408      	add	r0, r1
    65c2:	42a8      	cmp	r0, r5
    65c4:	d807      	bhi.n	65d6 <flash_area_write+0x22>
	if (!is_in_flash_area_bounds(fa, off, len)) {
		return -EINVAL;
	}

	return flash_write(fa->fa_dev, fa->fa_off + off, (void *)src, len);
    65c6:	68e0      	ldr	r0, [r4, #12]
    65c8:	6864      	ldr	r4, [r4, #4]
    65ca:	4421      	add	r1, r4
{
	const struct flash_driver_api *api =
		(const struct flash_driver_api *)dev->api;
	int rc;

	rc = api->write(dev, offset, data, len);
    65cc:	6884      	ldr	r4, [r0, #8]
    65ce:	6864      	ldr	r4, [r4, #4]
    65d0:	46a4      	mov	ip, r4
}
    65d2:	bc30      	pop	{r4, r5}
    65d4:	4760      	bx	ip
    65d6:	f06f 0015 	mvn.w	r0, #21
    65da:	bc30      	pop	{r4, r5}
    65dc:	4770      	bx	lr

000065de <flash_area_erase>:
    65de:	2900      	cmp	r1, #0

int flash_area_erase(const struct flash_area *fa, off_t off, size_t len)
{
    65e0:	4603      	mov	r3, r0
    65e2:	b410      	push	{r4}
    65e4:	4610      	mov	r0, r2
    65e6:	db0b      	blt.n	6600 <flash_area_erase+0x22>
    65e8:	689c      	ldr	r4, [r3, #8]
    65ea:	4408      	add	r0, r1
    65ec:	42a0      	cmp	r0, r4
    65ee:	d807      	bhi.n	6600 <flash_area_erase+0x22>
	if (!is_in_flash_area_bounds(fa, off, len)) {
		return -EINVAL;
	}

	return flash_erase(fa->fa_dev, fa->fa_off + off, len);
    65f0:	68d8      	ldr	r0, [r3, #12]
    65f2:	685b      	ldr	r3, [r3, #4]
    65f4:	4419      	add	r1, r3
{
	const struct flash_driver_api *api =
		(const struct flash_driver_api *)dev->api;
	int rc;

	rc = api->erase(dev, offset, size);
    65f6:	6883      	ldr	r3, [r0, #8]
}
    65f8:	f85d 4b04 	ldr.w	r4, [sp], #4
    65fc:	689b      	ldr	r3, [r3, #8]
    65fe:	4718      	bx	r3
    6600:	f06f 0015 	mvn.w	r0, #21
    6604:	f85d 4b04 	ldr.w	r4, [sp], #4
    6608:	4770      	bx	lr

0000660a <flash_area_align>:

uint32_t flash_area_align(const struct flash_area *fa)
{
    660a:	b508      	push	{r3, lr}
	return flash_get_write_block_size(fa->fa_dev);
    660c:	68c0      	ldr	r0, [r0, #12]
static inline size_t z_impl_flash_get_write_block_size(const struct device *dev)
{
	const struct flash_driver_api *api =
		(const struct flash_driver_api *)dev->api;

	return api->get_parameters(dev)->write_block_size;
    660e:	6883      	ldr	r3, [r0, #8]
    6610:	68db      	ldr	r3, [r3, #12]
    6612:	4798      	blx	r3
}
    6614:	6800      	ldr	r0, [r0, #0]
    6616:	bd08      	pop	{r3, pc}

00006618 <flash_area_erased_val>:
{
	return fa->fa_dev;
}

uint8_t flash_area_erased_val(const struct flash_area *fa)
{
    6618:	b508      	push	{r3, lr}
	const struct flash_parameters *param;

	param = flash_get_parameters(fa->fa_dev);
    661a:	68c0      	ldr	r0, [r0, #12]
static inline const struct flash_parameters *z_impl_flash_get_parameters(const struct device *dev)
{
	const struct flash_driver_api *api =
		(const struct flash_driver_api *)dev->api;

	return api->get_parameters(dev);
    661c:	6883      	ldr	r3, [r0, #8]
    661e:	68db      	ldr	r3, [r3, #12]
    6620:	4798      	blx	r3

	return param->erase_value;
}
    6622:	7900      	ldrb	r0, [r0, #4]
    6624:	bd08      	pop	{r3, pc}

00006626 <get_sectors_cb>:
{
    6626:	b570      	push	{r4, r5, r6, lr}
	if (info->start_offset < data->area_off) {
    6628:	684c      	ldr	r4, [r1, #4]
    662a:	6803      	ldr	r3, [r0, #0]
    662c:	42a3      	cmp	r3, r4
    662e:	d201      	bcs.n	6634 <get_sectors_cb+0xe>
		*bail_value = true;
    6630:	2001      	movs	r0, #1
}
    6632:	bd70      	pop	{r4, r5, r6, pc}
	} else if (info->start_offset >= data->area_off + data->area_len) {
    6634:	688a      	ldr	r2, [r1, #8]
    6636:	4422      	add	r2, r4
    6638:	4293      	cmp	r3, r2
    663a:	d301      	bcc.n	6640 <get_sectors_cb+0x1a>
		*bail_value = false;
    663c:	2000      	movs	r0, #0
    663e:	e7f8      	b.n	6632 <get_sectors_cb+0xc>
	} else if (data->ret_idx >= data->ret_len) {
    6640:	e9d1 2503 	ldrd	r2, r5, [r1, #12]
    6644:	694e      	ldr	r6, [r1, #20]
    6646:	42b5      	cmp	r5, r6
    6648:	d303      	bcc.n	6652 <get_sectors_cb+0x2c>
		data->status = -ENOMEM;
    664a:	f06f 030b 	mvn.w	r3, #11
    664e:	618b      	str	r3, [r1, #24]
		return true;
    6650:	e7f4      	b.n	663c <get_sectors_cb+0x16>
	ret[data->ret_idx].fs_off = info->start_offset - data->area_off;
    6652:	1b1b      	subs	r3, r3, r4
    6654:	f842 3035 	str.w	r3, [r2, r5, lsl #3]
	ret[data->ret_idx].fs_size = info->size;
    6658:	6843      	ldr	r3, [r0, #4]
    665a:	6908      	ldr	r0, [r1, #16]
    665c:	eb02 02c0 	add.w	r2, r2, r0, lsl #3
    6660:	6053      	str	r3, [r2, #4]
	data->ret_idx++;
    6662:	690b      	ldr	r3, [r1, #16]
    6664:	3301      	adds	r3, #1
    6666:	610b      	str	r3, [r1, #16]
	return true;
    6668:	e7e2      	b.n	6630 <get_sectors_cb+0xa>

0000666a <abort_function>:
{
    666a:	b508      	push	{r3, lr}
	sys_reboot(SYS_REBOOT_WARM);
    666c:	2000      	movs	r0, #0
    666e:	f7fb f9a7 	bl	19c0 <sys_reboot>

00006672 <nrf_cc3xx_platform_mutex_init>:
/** @brief Function to initialize the nrf_cc3xx_platform mutex APIs
 */
void nrf_cc3xx_platform_mutex_init(void)
{
	// No thread-safe mutexes are required
}
    6672:	4770      	bx	lr

00006674 <z_do_kernel_oops>:
 *
 * @param esf exception frame
 * @param callee_regs Callee-saved registers (R4-R11)
 */
void z_do_kernel_oops(const z_arch_esf_t *esf, _callee_saved_t *callee_regs)
{
    6674:	4601      	mov	r1, r0
	}

#endif /* CONFIG_USERSPACE */

#if !defined(CONFIG_EXTRA_EXCEPTION_INFO)
	z_arm_fatal_error(reason, esf);
    6676:	6800      	ldr	r0, [r0, #0]
    6678:	f7fb ba34 	b.w	1ae4 <z_arm_fatal_error>

0000667c <z_irq_spurious>:
 */
void z_irq_spurious(const void *unused)
{
	ARG_UNUSED(unused);

	z_arm_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
    667c:	2100      	movs	r1, #0
    667e:	2001      	movs	r0, #1
    6680:	f7fb ba30 	b.w	1ae4 <z_arm_fatal_error>

00006684 <z_arm_nmi>:
 * Simply call what is installed in 'static void(*handler)(void)'.
 *
 */

void z_arm_nmi(void)
{
    6684:	b508      	push	{r3, lr}
	handler();
    6686:	f7fb fa8f 	bl	1ba8 <z_SysNmiOnReset>
	z_arm_int_exit();
}
    668a:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	z_arm_int_exit();
    668e:	f7fb bb11 	b.w	1cb4 <z_arm_exc_exit>

00006692 <strcpy>:

char *strcpy(char *ZRESTRICT d, const char *ZRESTRICT s)
{
	char *dest = d;

	while (*s != '\0') {
    6692:	3901      	subs	r1, #1
    6694:	4603      	mov	r3, r0
    6696:	f811 2f01 	ldrb.w	r2, [r1, #1]!
    669a:	b90a      	cbnz	r2, 66a0 <strcpy+0xe>
		*d = *s;
		d++;
		s++;
	}

	*d = '\0';
    669c:	701a      	strb	r2, [r3, #0]

	return dest;
}
    669e:	4770      	bx	lr
		*d = *s;
    66a0:	f803 2b01 	strb.w	r2, [r3], #1
		s++;
    66a4:	e7f7      	b.n	6696 <strcpy+0x4>

000066a6 <strlen>:
 *
 * @return number of bytes in string <s>
 */

size_t strlen(const char *s)
{
    66a6:	4603      	mov	r3, r0
	size_t n = 0;
    66a8:	2000      	movs	r0, #0

	while (*s != '\0') {
    66aa:	5c1a      	ldrb	r2, [r3, r0]
    66ac:	b902      	cbnz	r2, 66b0 <strlen+0xa>
		s++;
		n++;
	}

	return n;
}
    66ae:	4770      	bx	lr
		n++;
    66b0:	3001      	adds	r0, #1
    66b2:	e7fa      	b.n	66aa <strlen+0x4>

000066b4 <memcmp>:
 * @brief Compare two memory areas
 *
 * @return negative # if <m1> < <m2>, 0 if <m1> == <m2>, else positive #
 */
int memcmp(const void *m1, const void *m2, size_t n)
{
    66b4:	b510      	push	{r4, lr}
	const char *c1 = m1;
	const char *c2 = m2;

	if (!n) {
    66b6:	b15a      	cbz	r2, 66d0 <memcmp+0x1c>
    66b8:	3901      	subs	r1, #1
    66ba:	1884      	adds	r4, r0, r2
		return 0;
	}

	while ((--n > 0) && (*c1 == *c2)) {
    66bc:	f810 2b01 	ldrb.w	r2, [r0], #1
    66c0:	f811 3f01 	ldrb.w	r3, [r1, #1]!
    66c4:	42a0      	cmp	r0, r4
    66c6:	d001      	beq.n	66cc <memcmp+0x18>
    66c8:	429a      	cmp	r2, r3
    66ca:	d0f7      	beq.n	66bc <memcmp+0x8>
		c1++;
		c2++;
	}

	return *c1 - *c2;
    66cc:	1ad0      	subs	r0, r2, r3
}
    66ce:	bd10      	pop	{r4, pc}
		return 0;
    66d0:	4610      	mov	r0, r2
    66d2:	e7fc      	b.n	66ce <memcmp+0x1a>

000066d4 <memcpy>:
 *
 * @return pointer to start of destination buffer
 */

void *memcpy(void *ZRESTRICT d, const void *ZRESTRICT s, size_t n)
{
    66d4:	b510      	push	{r4, lr}
    66d6:	1e43      	subs	r3, r0, #1
    66d8:	440a      	add	r2, r1
	}
#endif

	/* do byte-sized copying until finished */

	while (n > 0) {
    66da:	4291      	cmp	r1, r2
    66dc:	d100      	bne.n	66e0 <memcpy+0xc>
		*(d_byte++) = *(s_byte++);
		n--;
	}

	return d;
}
    66de:	bd10      	pop	{r4, pc}
		*(d_byte++) = *(s_byte++);
    66e0:	f811 4b01 	ldrb.w	r4, [r1], #1
    66e4:	f803 4f01 	strb.w	r4, [r3, #1]!
		n--;
    66e8:	e7f7      	b.n	66da <memcpy+0x6>

000066ea <memset>:
void *memset(void *buf, int c, size_t n)
{
	/* do byte-sized initialization until word-aligned or finished */

	unsigned char *d_byte = (unsigned char *)buf;
	unsigned char c_byte = (unsigned char)c;
    66ea:	b2c9      	uxtb	r1, r1
	/* do byte-sized initialization until finished */

	d_byte = (unsigned char *)d_word;
#endif

	while (n > 0) {
    66ec:	4402      	add	r2, r0
	unsigned char *d_byte = (unsigned char *)buf;
    66ee:	4603      	mov	r3, r0
	while (n > 0) {
    66f0:	4293      	cmp	r3, r2
    66f2:	d100      	bne.n	66f6 <memset+0xc>
		*(d_byte++) = c_byte;
		n--;
	}

	return buf;
}
    66f4:	4770      	bx	lr
		*(d_byte++) = c_byte;
    66f6:	f803 1b01 	strb.w	r1, [r3], #1
		n--;
    66fa:	e7f9      	b.n	66f0 <memset+0x6>

000066fc <_stdout_hook_default>:
}
    66fc:	f04f 30ff 	mov.w	r0, #4294967295
    6700:	4770      	bx	lr

00006702 <get_status>:
	return GET_STATUS(get_sub_data(dev, type)->flags);
    6702:	6903      	ldr	r3, [r0, #16]
    6704:	b2c9      	uxtb	r1, r1
    6706:	220c      	movs	r2, #12
    6708:	fb01 3302 	mla	r3, r1, r2, r3
    670c:	6c18      	ldr	r0, [r3, #64]	; 0x40
}
    670e:	f000 0007 	and.w	r0, r0, #7
    6712:	4770      	bx	lr

00006714 <set_on_state>:
	__asm__ volatile(
    6714:	f04f 0320 	mov.w	r3, #32
    6718:	f3ef 8211 	mrs	r2, BASEPRI
    671c:	f383 8812 	msr	BASEPRI_MAX, r3
    6720:	f3bf 8f6f 	isb	sy
	*flags = CLOCK_CONTROL_STATUS_ON | GET_CTX(*flags);
    6724:	6803      	ldr	r3, [r0, #0]
    6726:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
    672a:	f043 0302 	orr.w	r3, r3, #2
    672e:	6003      	str	r3, [r0, #0]
	__asm__ volatile(
    6730:	f382 8811 	msr	BASEPRI, r2
    6734:	f3bf 8f6f 	isb	sy
}
    6738:	4770      	bx	lr

0000673a <stop>:
{
    673a:	b570      	push	{r4, r5, r6, lr}
    673c:	b2c9      	uxtb	r1, r1
	struct nrf_clock_control_data *data = dev->data;
    673e:	6903      	ldr	r3, [r0, #16]
	__asm__ volatile(
    6740:	f04f 0420 	mov.w	r4, #32
    6744:	f3ef 8511 	mrs	r5, BASEPRI
    6748:	f384 8812 	msr	BASEPRI_MAX, r4
    674c:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    6750:	260c      	movs	r6, #12
    6752:	fb06 3401 	mla	r4, r6, r1, r3
    6756:	6c24      	ldr	r4, [r4, #64]	; 0x40
	if ((current_ctx != 0) && (current_ctx != ctx)) {
    6758:	f014 04c0 	ands.w	r4, r4, #192	; 0xc0
    675c:	d008      	beq.n	6770 <stop+0x36>
    675e:	42a2      	cmp	r2, r4
    6760:	d006      	beq.n	6770 <stop+0x36>
	__asm__ volatile(
    6762:	f385 8811 	msr	BASEPRI, r5
    6766:	f3bf 8f6f 	isb	sy
		err = -EPERM;
    676a:	f04f 30ff 	mov.w	r0, #4294967295
}
    676e:	bd70      	pop	{r4, r5, r6, pc}
		*flags = CLOCK_CONTROL_STATUS_OFF;
    6770:	4371      	muls	r1, r6
    6772:	440b      	add	r3, r1
    6774:	2201      	movs	r2, #1
    6776:	641a      	str	r2, [r3, #64]	; 0x40
    6778:	f385 8811 	msr	BASEPRI, r5
    677c:	f3bf 8f6f 	isb	sy
	get_sub_config(dev, type)->stop();
    6780:	6843      	ldr	r3, [r0, #4]
    6782:	440b      	add	r3, r1
    6784:	685b      	ldr	r3, [r3, #4]
    6786:	4798      	blx	r3
	return 0;
    6788:	2000      	movs	r0, #0
    678a:	e7f0      	b.n	676e <stop+0x34>

0000678c <api_stop>:
	return stop(dev, subsys, CTX_API);
    678c:	2280      	movs	r2, #128	; 0x80
    678e:	f7ff bfd4 	b.w	673a <stop>

00006792 <async_start>:
{
    6792:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    6794:	9f06      	ldr	r7, [sp, #24]
	struct nrf_clock_control_data *data = dev->data;
    6796:	6904      	ldr	r4, [r0, #16]
	return &data->subsys[type];
    6798:	b2c9      	uxtb	r1, r1
	__asm__ volatile(
    679a:	f04f 0520 	mov.w	r5, #32
    679e:	f3ef 8611 	mrs	r6, BASEPRI
    67a2:	f385 8812 	msr	BASEPRI_MAX, r5
    67a6:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    67aa:	250c      	movs	r5, #12
    67ac:	4369      	muls	r1, r5
    67ae:	440c      	add	r4, r1
    67b0:	6c25      	ldr	r5, [r4, #64]	; 0x40
	if ((*flags & (STATUS_MASK)) == CLOCK_CONTROL_STATUS_OFF) {
    67b2:	f005 0c07 	and.w	ip, r5, #7
    67b6:	f1bc 0f01 	cmp.w	ip, #1
    67ba:	d10b      	bne.n	67d4 <async_start+0x42>
		*flags = CLOCK_CONTROL_STATUS_STARTING | ctx;
    67bc:	6427      	str	r7, [r4, #64]	; 0x40
	__asm__ volatile(
    67be:	f386 8811 	msr	BASEPRI, r6
    67c2:	f3bf 8f6f 	isb	sy
	subdata->user_data = user_data;
    67c6:	e9c4 230e 	strd	r2, r3, [r4, #56]	; 0x38
	 get_sub_config(dev, type)->start();
    67ca:	6843      	ldr	r3, [r0, #4]
    67cc:	585b      	ldr	r3, [r3, r1]
    67ce:	4798      	blx	r3
	return 0;
    67d0:	2000      	movs	r0, #0
}
    67d2:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	uint32_t current_ctx = GET_CTX(*flags);
    67d4:	f005 05c0 	and.w	r5, r5, #192	; 0xc0
	} else if (current_ctx != ctx) {
    67d8:	42af      	cmp	r7, r5
    67da:	f386 8811 	msr	BASEPRI, r6
    67de:	f3bf 8f6f 	isb	sy
		err = -EALREADY;
    67e2:	bf0c      	ite	eq
    67e4:	f06f 0077 	mvneq.w	r0, #119	; 0x77
		err = -EPERM;
    67e8:	f04f 30ff 	movne.w	r0, #4294967295
    67ec:	e7f1      	b.n	67d2 <async_start+0x40>

000067ee <api_start>:
{
    67ee:	b513      	push	{r0, r1, r4, lr}
	return async_start(dev, subsys, cb, user_data, CTX_API);
    67f0:	2480      	movs	r4, #128	; 0x80
    67f2:	9400      	str	r4, [sp, #0]
    67f4:	f7ff ffcd 	bl	6792 <async_start>
}
    67f8:	b002      	add	sp, #8
    67fa:	bd10      	pop	{r4, pc}

000067fc <api_blocking_start>:
}
    67fc:	f06f 0085 	mvn.w	r0, #133	; 0x85
    6800:	4770      	bx	lr

00006802 <onoff_started_callback>:
{
    6802:	b410      	push	{r4}
	return &data->mgr[type];
    6804:	6900      	ldr	r0, [r0, #16]
    6806:	b2cb      	uxtb	r3, r1
	notify(mgr, 0);
    6808:	241c      	movs	r4, #28
    680a:	fb03 0004 	mla	r0, r3, r4, r0
    680e:	2100      	movs	r1, #0
}
    6810:	f85d 4b04 	ldr.w	r4, [sp], #4
	notify(mgr, 0);
    6814:	4710      	bx	r2

00006816 <lfclk_start>:
    nrfx_clock_start(NRF_CLOCK_DOMAIN_LFCLK);
    6816:	2000      	movs	r0, #0
    6818:	f000 ba74 	b.w	6d04 <nrfx_clock_start>

0000681c <lfclk_stop>:
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
    681c:	2000      	movs	r0, #0
    681e:	f000 baad 	b.w	6d7c <nrfx_clock_stop>

00006822 <gpio_nrfx_port_get_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    6822:	6843      	ldr	r3, [r0, #4]
    6824:	685b      	ldr	r3, [r3, #4]
    return p_reg->IN;
    6826:	f8d3 3510 	ldr.w	r3, [r3, #1296]	; 0x510
	*value = nrf_gpio_port_in_read(reg);
    682a:	600b      	str	r3, [r1, #0]
}
    682c:	2000      	movs	r0, #0
    682e:	4770      	bx	lr

00006830 <gpio_nrfx_port_set_masked_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    6830:	6843      	ldr	r3, [r0, #4]
    6832:	685b      	ldr	r3, [r3, #4]
	const uint32_t set_mask = value & mask;
    6834:	ea02 0001 	and.w	r0, r2, r1
	const uint32_t clear_mask = (~set_mask) & mask;
    6838:	ea21 0102 	bic.w	r1, r1, r2
    p_reg->OUTSET = set_mask;
    683c:	f8c3 0508 	str.w	r0, [r3, #1288]	; 0x508
    p_reg->OUTCLR = clr_mask;
    6840:	f8c3 150c 	str.w	r1, [r3, #1292]	; 0x50c
}
    6844:	2000      	movs	r0, #0
    6846:	4770      	bx	lr

00006848 <gpio_nrfx_port_set_bits_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    6848:	6843      	ldr	r3, [r0, #4]
    684a:	685b      	ldr	r3, [r3, #4]
}
    684c:	2000      	movs	r0, #0
    p_reg->OUTSET = set_mask;
    684e:	f8c3 1508 	str.w	r1, [r3, #1288]	; 0x508
    6852:	4770      	bx	lr

00006854 <gpio_nrfx_port_clear_bits_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    6854:	6843      	ldr	r3, [r0, #4]
    6856:	685b      	ldr	r3, [r3, #4]
}
    6858:	2000      	movs	r0, #0
    p_reg->OUTCLR = clr_mask;
    685a:	f8c3 150c 	str.w	r1, [r3, #1292]	; 0x50c
    685e:	4770      	bx	lr

00006860 <gpio_nrfx_port_toggle_bits>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    6860:	6843      	ldr	r3, [r0, #4]
    6862:	685a      	ldr	r2, [r3, #4]
    return p_reg->OUT;
    6864:	f8d2 3504 	ldr.w	r3, [r2, #1284]	; 0x504
	const uint32_t set_mask = value & mask;
    6868:	ea21 0003 	bic.w	r0, r1, r3
	const uint32_t clear_mask = (~value) & mask;
    686c:	400b      	ands	r3, r1
    p_reg->OUTSET = set_mask;
    686e:	f8c2 0508 	str.w	r0, [r2, #1288]	; 0x508
    p_reg->OUTCLR = clr_mask;
    6872:	f8c2 350c 	str.w	r3, [r2, #1292]	; 0x50c
}
    6876:	2000      	movs	r0, #0
    6878:	4770      	bx	lr

0000687a <gpio_nrfx_manage_callback>:
{
    687a:	b510      	push	{r4, lr}
	return port->data;
    687c:	6903      	ldr	r3, [r0, #16]
	return list->head;
    687e:	6858      	ldr	r0, [r3, #4]
	if (!sys_slist_is_empty(callbacks)) {
    6880:	b1f8      	cbz	r0, 68c2 <gpio_nrfx_manage_callback+0x48>
 */
static inline bool sys_slist_find_and_remove(sys_slist_t *list,
					     sys_snode_t *node);

/** @} */
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    6882:	4288      	cmp	r0, r1
    6884:	d119      	bne.n	68ba <gpio_nrfx_manage_callback+0x40>
Z_GENLIST_REMOVE(slist, snode)
    6886:	689c      	ldr	r4, [r3, #8]
	return node->next;
    6888:	6808      	ldr	r0, [r1, #0]
	list->head = node;
    688a:	6058      	str	r0, [r3, #4]
Z_GENLIST_REMOVE(slist, snode)
    688c:	42a1      	cmp	r1, r4
    688e:	d100      	bne.n	6892 <gpio_nrfx_manage_callback+0x18>
	list->tail = node;
    6890:	6098      	str	r0, [r3, #8]
	parent->next = child;
    6892:	2000      	movs	r0, #0
    6894:	6008      	str	r0, [r1, #0]
	if (set) {
    6896:	b12a      	cbz	r2, 68a4 <gpio_nrfx_manage_callback+0x2a>
	return list->head;
    6898:	685a      	ldr	r2, [r3, #4]
	parent->next = child;
    689a:	600a      	str	r2, [r1, #0]
Z_GENLIST_PREPEND(slist, snode)
    689c:	689a      	ldr	r2, [r3, #8]
	list->head = node;
    689e:	6059      	str	r1, [r3, #4]
Z_GENLIST_PREPEND(slist, snode)
    68a0:	b902      	cbnz	r2, 68a4 <gpio_nrfx_manage_callback+0x2a>
	list->tail = node;
    68a2:	6099      	str	r1, [r3, #8]
	return 0;
    68a4:	2000      	movs	r0, #0
	return gpio_manage_callback(&get_port_data(port)->callbacks,
    68a6:	e010      	b.n	68ca <gpio_nrfx_manage_callback+0x50>
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    68a8:	4281      	cmp	r1, r0
    68aa:	d106      	bne.n	68ba <gpio_nrfx_manage_callback+0x40>
	return node->next;
    68ac:	6808      	ldr	r0, [r1, #0]
	parent->next = child;
    68ae:	6020      	str	r0, [r4, #0]
Z_GENLIST_REMOVE(slist, snode)
    68b0:	6898      	ldr	r0, [r3, #8]
    68b2:	4281      	cmp	r1, r0
    68b4:	d1ed      	bne.n	6892 <gpio_nrfx_manage_callback+0x18>
	list->tail = node;
    68b6:	609c      	str	r4, [r3, #8]
}
    68b8:	e7eb      	b.n	6892 <gpio_nrfx_manage_callback+0x18>
	return node->next;
    68ba:	4604      	mov	r4, r0
    68bc:	6800      	ldr	r0, [r0, #0]
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    68be:	2800      	cmp	r0, #0
    68c0:	d1f2      	bne.n	68a8 <gpio_nrfx_manage_callback+0x2e>
			if (!set) {
    68c2:	2a00      	cmp	r2, #0
    68c4:	d1e8      	bne.n	6898 <gpio_nrfx_manage_callback+0x1e>
				return -EINVAL;
    68c6:	f06f 0015 	mvn.w	r0, #21
}
    68ca:	bd10      	pop	{r4, pc}

000068cc <is_regular_addr_valid>:
{
    68cc:	b538      	push	{r3, r4, r5, lr}
    68ce:	4605      	mov	r5, r0
    68d0:	460c      	mov	r4, r1
	return is_within_bounds(addr, len, 0, nrfx_nvmc_flash_size_get());
    68d2:	f000 faad 	bl	6e30 <nrfx_nvmc_flash_size_get>
			(addr < (boundary_start + boundary_size)) &&
    68d6:	2d00      	cmp	r5, #0
    68d8:	db07      	blt.n	68ea <is_regular_addr_valid+0x1e>
	return (addr >= boundary_start &&
    68da:	42a8      	cmp	r0, r5
    68dc:	d905      	bls.n	68ea <is_regular_addr_valid+0x1e>
			(len <= (boundary_start + boundary_size - addr)));
    68de:	1b40      	subs	r0, r0, r5
			(addr < (boundary_start + boundary_size)) &&
    68e0:	4284      	cmp	r4, r0
    68e2:	bf8c      	ite	hi
    68e4:	2000      	movhi	r0, #0
    68e6:	2001      	movls	r0, #1
}
    68e8:	bd38      	pop	{r3, r4, r5, pc}
			(addr < (boundary_start + boundary_size)) &&
    68ea:	2000      	movs	r0, #0
    68ec:	e7fc      	b.n	68e8 <is_regular_addr_valid+0x1c>

000068ee <flash_get_page_info>:

#include <zephyr/drivers/flash.h>

static int flash_get_page_info(const struct device *dev, off_t offs,
			       uint32_t index, struct flash_pages_info *info)
{
    68ee:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
    68f2:	461c      	mov	r4, r3
    68f4:	4690      	mov	r8, r2
	const struct flash_driver_api *api = dev->api;
	const struct flash_pages_layout *layout;
	size_t layout_size;
	uint32_t index_jmp;

	info->start_offset = 0;
    68f6:	2300      	movs	r3, #0
	const struct flash_driver_api *api = dev->api;
    68f8:	6882      	ldr	r2, [r0, #8]
	info->start_offset = 0;
    68fa:	6023      	str	r3, [r4, #0]
	info->index = 0U;
    68fc:	60a3      	str	r3, [r4, #8]

	api->page_layout(dev, &layout, &layout_size);
    68fe:	6913      	ldr	r3, [r2, #16]
{
    6900:	460d      	mov	r5, r1
	api->page_layout(dev, &layout, &layout_size);
    6902:	aa01      	add	r2, sp, #4
    6904:	4669      	mov	r1, sp
    6906:	4798      	blx	r3

	while (layout_size--) {
    6908:	9b01      	ldr	r3, [sp, #4]
    690a:	1e5a      	subs	r2, r3, #1
    690c:	9201      	str	r2, [sp, #4]
    690e:	b923      	cbnz	r3, 691a <flash_get_page_info+0x2c>
		}

		layout++;
	}

	return -EINVAL; /* page at offs or idx doesn't exist */
    6910:	f06f 0015 	mvn.w	r0, #21
}
    6914:	b002      	add	sp, #8
    6916:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		info->size = layout->pages_size;
    691a:	9800      	ldr	r0, [sp, #0]
			index_jmp = index - info->index;
    691c:	68a2      	ldr	r2, [r4, #8]
		info->size = layout->pages_size;
    691e:	6847      	ldr	r7, [r0, #4]
			index_jmp = (offs - info->start_offset) / info->size;
    6920:	6821      	ldr	r1, [r4, #0]
		info->size = layout->pages_size;
    6922:	6067      	str	r7, [r4, #4]
		if (offs == 0) {
    6924:	b985      	cbnz	r5, 6948 <flash_get_page_info+0x5a>
			index_jmp = index - info->index;
    6926:	eba8 0302 	sub.w	r3, r8, r2
		index_jmp = MIN(index_jmp, layout->pages_count);
    692a:	6806      	ldr	r6, [r0, #0]
    692c:	42b3      	cmp	r3, r6
    692e:	bf28      	it	cs
    6930:	4633      	movcs	r3, r6
		info->index += index_jmp;
    6932:	441a      	add	r2, r3
		info->start_offset += (index_jmp * info->size);
    6934:	fb03 1107 	mla	r1, r3, r7, r1
    6938:	6021      	str	r1, [r4, #0]
		info->index += index_jmp;
    693a:	60a2      	str	r2, [r4, #8]
		if (index_jmp < layout->pages_count) {
    693c:	6802      	ldr	r2, [r0, #0]
    693e:	429a      	cmp	r2, r3
    6940:	d806      	bhi.n	6950 <flash_get_page_info+0x62>
		layout++;
    6942:	3008      	adds	r0, #8
    6944:	9000      	str	r0, [sp, #0]
    6946:	e7df      	b.n	6908 <flash_get_page_info+0x1a>
			index_jmp = (offs - info->start_offset) / info->size;
    6948:	1a6b      	subs	r3, r5, r1
    694a:	fbb3 f3f7 	udiv	r3, r3, r7
    694e:	e7ec      	b.n	692a <flash_get_page_info+0x3c>
			return 0;
    6950:	2000      	movs	r0, #0
    6952:	e7df      	b.n	6914 <flash_get_page_info+0x26>

00006954 <z_impl_flash_get_page_info_by_offs>:

int z_impl_flash_get_page_info_by_offs(const struct device *dev, off_t offs,
				       struct flash_pages_info *info)
{
    6954:	4613      	mov	r3, r2
	return flash_get_page_info(dev, offs, 0U, info);
    6956:	2200      	movs	r2, #0
    6958:	f7ff bfc9 	b.w	68ee <flash_get_page_info>

0000695c <flash_page_foreach>:
	return count;
}

void flash_page_foreach(const struct device *dev, flash_page_cb cb,
			void *data)
{
    695c:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
	const struct flash_pages_layout *layout;
	struct flash_pages_info page_info;
	size_t block, num_blocks, page = 0, i;
	off_t off = 0;

	api->page_layout(dev, &layout, &num_blocks);
    6960:	6883      	ldr	r3, [r0, #8]
{
    6962:	b086      	sub	sp, #24
	api->page_layout(dev, &layout, &num_blocks);
    6964:	691b      	ldr	r3, [r3, #16]
{
    6966:	4688      	mov	r8, r1
    6968:	4691      	mov	r9, r2
	api->page_layout(dev, &layout, &num_blocks);
    696a:	a901      	add	r1, sp, #4
    696c:	aa02      	add	r2, sp, #8
    696e:	4798      	blx	r3
	off_t off = 0;
    6970:	2400      	movs	r4, #0
	size_t block, num_blocks, page = 0, i;
    6972:	46a2      	mov	sl, r4

	for (block = 0; block < num_blocks; block++) {
    6974:	4625      	mov	r5, r4
    6976:	9b02      	ldr	r3, [sp, #8]
    6978:	42ab      	cmp	r3, r5
    697a:	d802      	bhi.n	6982 <flash_page_foreach+0x26>

			off += page_info.size;
			page++;
		}
	}
}
    697c:	b006      	add	sp, #24
    697e:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
		const struct flash_pages_layout *l = &layout[block];
    6982:	9f01      	ldr	r7, [sp, #4]
    6984:	eb07 07c5 	add.w	r7, r7, r5, lsl #3
		for (i = 0; i < l->pages_count; i++) {
    6988:	2600      	movs	r6, #0
		page_info.size = l->pages_size;
    698a:	687b      	ldr	r3, [r7, #4]
    698c:	9304      	str	r3, [sp, #16]
		for (i = 0; i < l->pages_count; i++) {
    698e:	683a      	ldr	r2, [r7, #0]
    6990:	42b2      	cmp	r2, r6
    6992:	eb0a 0306 	add.w	r3, sl, r6
    6996:	d802      	bhi.n	699e <flash_page_foreach+0x42>
	for (block = 0; block < num_blocks; block++) {
    6998:	3501      	adds	r5, #1
    699a:	469a      	mov	sl, r3
    699c:	e7eb      	b.n	6976 <flash_page_foreach+0x1a>
			page_info.start_offset = off;
    699e:	9403      	str	r4, [sp, #12]
			page_info.index = page;
    69a0:	9305      	str	r3, [sp, #20]
			if (!cb(&page_info, data)) {
    69a2:	4649      	mov	r1, r9
    69a4:	a803      	add	r0, sp, #12
    69a6:	47c0      	blx	r8
    69a8:	2800      	cmp	r0, #0
    69aa:	d0e7      	beq.n	697c <flash_page_foreach+0x20>
			off += page_info.size;
    69ac:	9b04      	ldr	r3, [sp, #16]
		for (i = 0; i < l->pages_count; i++) {
    69ae:	3601      	adds	r6, #1
			off += page_info.size;
    69b0:	441c      	add	r4, r3
		for (i = 0; i < l->pages_count; i++) {
    69b2:	e7ec      	b.n	698e <flash_page_foreach+0x32>

000069b4 <uarte_nrfx_config_get>:
	struct uarte_nrfx_data *data = dev->data;
    69b4:	6902      	ldr	r2, [r0, #16]
{
    69b6:	460b      	mov	r3, r1
	*cfg = data->uart_config;
    69b8:	e9d2 0101 	ldrd	r0, r1, [r2, #4]
    69bc:	e883 0003 	stmia.w	r3, {r0, r1}
}
    69c0:	2000      	movs	r0, #0
    69c2:	4770      	bx	lr

000069c4 <uarte_nrfx_err_check>:
	return config->uarte_regs;
    69c4:	6843      	ldr	r3, [r0, #4]
    69c6:	681b      	ldr	r3, [r3, #0]
    uint32_t errsrc_mask = p_reg->ERRORSRC;
    69c8:	f8d3 0480 	ldr.w	r0, [r3, #1152]	; 0x480
    p_reg->ERRORSRC = errsrc_mask;
    69cc:	f8c3 0480 	str.w	r0, [r3, #1152]	; 0x480
}
    69d0:	4770      	bx	lr

000069d2 <uarte_nrfx_poll_in>:
	return config->uarte_regs;
    69d2:	6843      	ldr	r3, [r0, #4]
	const struct uarte_nrfx_data *data = dev->data;
    69d4:	6902      	ldr	r2, [r0, #16]
	return config->uarte_regs;
    69d6:	681b      	ldr	r3, [r3, #0]
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    69d8:	f8d3 0110 	ldr.w	r0, [r3, #272]	; 0x110
	if (!nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDRX)) {
    69dc:	b150      	cbz	r0, 69f4 <uarte_nrfx_poll_in+0x22>
	*c = *data->rx_data;
    69de:	6952      	ldr	r2, [r2, #20]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    69e0:	2000      	movs	r0, #0
    69e2:	7812      	ldrb	r2, [r2, #0]
    69e4:	700a      	strb	r2, [r1, #0]
    69e6:	f8c3 0110 	str.w	r0, [r3, #272]	; 0x110
    69ea:	f8d3 2110 	ldr.w	r2, [r3, #272]	; 0x110
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    69ee:	2201      	movs	r2, #1
    69f0:	601a      	str	r2, [r3, #0]
	return 0;
    69f2:	4770      	bx	lr
		return -1;
    69f4:	f04f 30ff 	mov.w	r0, #4294967295
}
    69f8:	4770      	bx	lr

000069fa <is_tx_ready.isra.0>:
	return config->uarte_regs;
    69fa:	6802      	ldr	r2, [r0, #0]
static bool is_tx_ready(const struct device *dev)
    69fc:	4603      	mov	r3, r0
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    69fe:	f8d2 0158 	ldr.w	r0, [r2, #344]	; 0x158
	return nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED) ||
    6a02:	b940      	cbnz	r0, 6a16 <is_tx_ready.isra.0+0x1c>
	bool ppi_endtx = config->flags & UARTE_CFG_FLAG_PPI_ENDTX;
    6a04:	685b      	ldr	r3, [r3, #4]
	return nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED) ||
    6a06:	079b      	lsls	r3, r3, #30
    6a08:	d406      	bmi.n	6a18 <is_tx_ready.isra.0+0x1e>
    6a0a:	f8d2 0120 	ldr.w	r0, [r2, #288]	; 0x120
    6a0e:	3800      	subs	r0, #0
    6a10:	bf18      	it	ne
    6a12:	2001      	movne	r0, #1
    6a14:	4770      	bx	lr
    6a16:	2001      	movs	r0, #1
}
    6a18:	4770      	bx	lr

00006a1a <uarte_nrfx_isr_int>:
	const struct uarte_nrfx_config *config = dev->config;
    6a1a:	6842      	ldr	r2, [r0, #4]
	return config->uarte_regs;
    6a1c:	6813      	ldr	r3, [r2, #0]
    return p_reg->INTENSET & mask;
    6a1e:	f8d3 1304 	ldr.w	r1, [r3, #772]	; 0x304
	if (nrf_uarte_int_enable_check(uarte, NRF_UARTE_INT_ENDTX_MASK) &&
    6a22:	05c9      	lsls	r1, r1, #23
    6a24:	d518      	bpl.n	6a58 <uarte_nrfx_isr_int+0x3e>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    6a26:	f8d3 1120 	ldr.w	r1, [r3, #288]	; 0x120
    6a2a:	b1a9      	cbz	r1, 6a58 <uarte_nrfx_isr_int+0x3e>
	__asm__ volatile(
    6a2c:	f04f 0020 	mov.w	r0, #32
    6a30:	f3ef 8111 	mrs	r1, BASEPRI
    6a34:	f380 8812 	msr	BASEPRI_MAX, r0
    6a38:	f3bf 8f6f 	isb	sy
    6a3c:	f8d3 0120 	ldr.w	r0, [r3, #288]	; 0x120
	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDTX)) {
    6a40:	b130      	cbz	r0, 6a50 <uarte_nrfx_isr_int+0x36>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    6a42:	2000      	movs	r0, #0
    6a44:	f8c3 0120 	str.w	r0, [r3, #288]	; 0x120
    6a48:	f8d3 0120 	ldr.w	r0, [r3, #288]	; 0x120
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    6a4c:	2001      	movs	r0, #1
    6a4e:	60d8      	str	r0, [r3, #12]
	__asm__ volatile(
    6a50:	f381 8811 	msr	BASEPRI, r1
    6a54:	f3bf 8f6f 	isb	sy
	if (config->flags & UARTE_CFG_FLAG_LOW_POWER) {
    6a58:	6852      	ldr	r2, [r2, #4]
    6a5a:	06d2      	lsls	r2, r2, #27
    6a5c:	d515      	bpl.n	6a8a <uarte_nrfx_isr_int+0x70>
	__asm__ volatile(
    6a5e:	f04f 0120 	mov.w	r1, #32
    6a62:	f3ef 8211 	mrs	r2, BASEPRI
    6a66:	f381 8812 	msr	BASEPRI_MAX, r1
    6a6a:	f3bf 8f6f 	isb	sy
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    6a6e:	f8d3 1158 	ldr.w	r1, [r3, #344]	; 0x158
		if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED)) {
    6a72:	b111      	cbz	r1, 6a7a <uarte_nrfx_isr_int+0x60>
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
    6a74:	2100      	movs	r1, #0
    6a76:	f8c3 1500 	str.w	r1, [r3, #1280]	; 0x500
    p_reg->INTENCLR = mask;
    6a7a:	f44f 0180 	mov.w	r1, #4194304	; 0x400000
    6a7e:	f8c3 1308 	str.w	r1, [r3, #776]	; 0x308
	__asm__ volatile(
    6a82:	f382 8811 	msr	BASEPRI, r2
    6a86:	f3bf 8f6f 	isb	sy
}
    6a8a:	4770      	bx	lr

00006a8c <uarte_1_init>:
#ifdef CONFIG_UART_0_NRF_UARTE
UART_NRF_UARTE_DEVICE(0);
#endif

#ifdef CONFIG_UART_1_NRF_UARTE
UART_NRF_UARTE_DEVICE(1);
    6a8c:	b510      	push	{r4, lr}
    6a8e:	2200      	movs	r2, #0
    6a90:	4604      	mov	r4, r0
    6a92:	2101      	movs	r1, #1
    6a94:	2028      	movs	r0, #40	; 0x28
    6a96:	f7fb f86f 	bl	1b78 <z_arm_irq_priority_set>
    6a9a:	2028      	movs	r0, #40	; 0x28
    6a9c:	f7fb f850 	bl	1b40 <arch_irq_enable>
    6aa0:	4620      	mov	r0, r4
    6aa2:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    6aa6:	f7fc b95b 	b.w	2d60 <uarte_instance_init.constprop.0>

00006aaa <uarte_0_init>:
UART_NRF_UARTE_DEVICE(0);
    6aaa:	b510      	push	{r4, lr}
    6aac:	2200      	movs	r2, #0
    6aae:	4604      	mov	r4, r0
    6ab0:	2101      	movs	r1, #1
    6ab2:	2002      	movs	r0, #2
    6ab4:	f7fb f860 	bl	1b78 <z_arm_irq_priority_set>
    6ab8:	2002      	movs	r0, #2
    6aba:	f7fb f841 	bl	1b40 <arch_irq_enable>
    6abe:	4620      	mov	r0, r4
    6ac0:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    6ac4:	f7fc b94c 	b.w	2d60 <uarte_instance_init.constprop.0>

00006ac8 <pinctrl_lookup_state>:

#include <zephyr/drivers/pinctrl.h>

int pinctrl_lookup_state(const struct pinctrl_dev_config *config, uint8_t id,
			 const struct pinctrl_state **state)
{
    6ac8:	b570      	push	{r4, r5, r6, lr}
	*state = &config->states[0];
    6aca:	6843      	ldr	r3, [r0, #4]
	while (*state <= &config->states[config->state_cnt - 1U]) {
    6acc:	f06f 4660 	mvn.w	r6, #3758096384	; 0xe0000000
	*state = &config->states[0];
    6ad0:	6013      	str	r3, [r2, #0]
	while (*state <= &config->states[config->state_cnt - 1U]) {
    6ad2:	7a05      	ldrb	r5, [r0, #8]
    6ad4:	6844      	ldr	r4, [r0, #4]
    6ad6:	4435      	add	r5, r6
    6ad8:	eb04 04c5 	add.w	r4, r4, r5, lsl #3
    6adc:	42a3      	cmp	r3, r4
    6ade:	d902      	bls.n	6ae6 <pinctrl_lookup_state+0x1e>
		}

		(*state)++;
	}

	return -ENOENT;
    6ae0:	f06f 0001 	mvn.w	r0, #1
}
    6ae4:	bd70      	pop	{r4, r5, r6, pc}
		if (id == (*state)->id) {
    6ae6:	795c      	ldrb	r4, [r3, #5]
    6ae8:	428c      	cmp	r4, r1
    6aea:	d001      	beq.n	6af0 <pinctrl_lookup_state+0x28>
		(*state)++;
    6aec:	3308      	adds	r3, #8
    6aee:	e7ef      	b.n	6ad0 <pinctrl_lookup_state+0x8>
			return 0;
    6af0:	2000      	movs	r0, #0
    6af2:	e7f7      	b.n	6ae4 <pinctrl_lookup_state+0x1c>

00006af4 <fprotect_set_permission>:

static int fprotect_set_permission(uint32_t start, size_t length,
				   size_t permission)
{
    6af4:	b573      	push	{r0, r1, r4, r5, r6, lr}
    6af6:	4605      	mov	r5, r0
	__ASSERT_NO_MSG(nrf_ficr_codepagesize_get(NRF_FICR) ==
			CONFIG_FPROTECT_BLOCK_SIZE);

	uint32_t region_idx;
	int result = find_free_region(&region_idx);
    6af8:	a801      	add	r0, sp, #4
{
    6afa:	460c      	mov	r4, r1
    6afc:	4616      	mov	r6, r2
	int result = find_free_region(&region_idx);
    6afe:	f7fc fca7 	bl	3450 <find_free_region>

	if (result != 0) {
    6b02:	bb70      	cbnz	r0, 6b62 <fprotect_set_permission+0x6e>
    6b04:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    6b08:	6919      	ldr	r1, [r3, #16]
		return result;
	}

	if (start % nrf_ficr_codepagesize_get(NRF_FICR) != 0 ||
    6b0a:	fbb5 f2f1 	udiv	r2, r5, r1
    6b0e:	fb01 5212 	mls	r2, r1, r2, r5
    6b12:	bb42      	cbnz	r2, 6b66 <fprotect_set_permission+0x72>
    6b14:	6919      	ldr	r1, [r3, #16]
	    length % nrf_ficr_codepagesize_get(NRF_FICR) != 0 ||
    6b16:	fbb4 f2f1 	udiv	r2, r4, r1
    6b1a:	fb01 4212 	mls	r2, r1, r2, r4
	if (start % nrf_ficr_codepagesize_get(NRF_FICR) != 0 ||
    6b1e:	bb12      	cbnz	r2, 6b66 <fprotect_set_permission+0x72>
    6b20:	691a      	ldr	r2, [r3, #16]
NRF_STATIC_INLINE uint32_t nrf_ficr_codesize_get(NRF_FICR_Type const * p_reg)
{
#if defined(FICR_INFO_CODESIZE_CODESIZE_Msk)
    return p_reg->INFO.CODESIZE;
#else
    return p_reg->CODESIZE;
    6b22:	695b      	ldr	r3, [r3, #20]
	    length > NRF_ACL_REGION_SIZE_MAX || length == 0) {
    6b24:	4353      	muls	r3, r2
	    length % nrf_ficr_codepagesize_get(NRF_FICR) != 0 ||
    6b26:	42a3      	cmp	r3, r4
    6b28:	d31d      	bcc.n	6b66 <fprotect_set_permission+0x72>
	    length > NRF_ACL_REGION_SIZE_MAX || length == 0) {
    6b2a:	b1e4      	cbz	r4, 6b66 <fprotect_set_permission+0x72>
		return -EINVAL;
	}

	nrf_acl_region_set(NRF_ACL, region_idx, start, length, permission);
    6b2c:	9b01      	ldr	r3, [sp, #4]
    p_reg->ACL[region_id].ADDR = address;
    6b2e:	011b      	lsls	r3, r3, #4
    6b30:	f103 4180 	add.w	r1, r3, #1073741824	; 0x40000000
    6b34:	f501 31f0 	add.w	r1, r1, #122880	; 0x1e000
    6b38:	f8c1 5800 	str.w	r5, [r1, #2048]	; 0x800
    p_reg->ACL[region_id].SIZE = size;
    6b3c:	f8c1 4804 	str.w	r4, [r1, #2052]	; 0x804
    p_reg->ACL[region_id].PERM = perm;
    6b40:	f8c1 6808 	str.w	r6, [r1, #2056]	; 0x808
    return (uint32_t)p_reg->ACL[region_id].ADDR;
    6b44:	f8d1 2800 	ldr.w	r2, [r1, #2048]	; 0x800

	if ((nrf_acl_region_address_get(NRF_ACL, region_idx) != start)
    6b48:	4295      	cmp	r5, r2
    6b4a:	d10f      	bne.n	6b6c <fprotect_set_permission+0x78>
    return (size_t)p_reg->ACL[region_id].SIZE;
    6b4c:	f8d1 2804 	ldr.w	r2, [r1, #2052]	; 0x804
		|| (nrf_acl_region_size_get(NRF_ACL, region_idx) != length)
    6b50:	4294      	cmp	r4, r2
    6b52:	d10b      	bne.n	6b6c <fprotect_set_permission+0x78>
    return (nrf_acl_perm_t)p_reg->ACL[region_id].PERM;
    6b54:	f8d1 3808 	ldr.w	r3, [r1, #2056]	; 0x808
		|| (nrf_acl_region_perm_get(NRF_ACL, region_idx) != permission)) {
    6b58:	b2db      	uxtb	r3, r3
		return -EFAULT;
    6b5a:	42b3      	cmp	r3, r6
    6b5c:	bf18      	it	ne
    6b5e:	f06f 000d 	mvnne.w	r0, #13
	}

	return 0;
}
    6b62:	b002      	add	sp, #8
    6b64:	bd70      	pop	{r4, r5, r6, pc}
		return -EINVAL;
    6b66:	f06f 0015 	mvn.w	r0, #21
    6b6a:	e7fa      	b.n	6b62 <fprotect_set_permission+0x6e>
		return -EFAULT;
    6b6c:	f06f 000d 	mvn.w	r0, #13
    6b70:	e7f7      	b.n	6b62 <fprotect_set_permission+0x6e>

00006b72 <fprotect_area>:
	return 0;
}

int fprotect_area(uint32_t start, size_t length)
{
	return fprotect_set_permission(start, length,
    6b72:	2202      	movs	r2, #2
    6b74:	f7ff bfbe 	b.w	6af4 <fprotect_set_permission>

00006b78 <hw_cc3xx_init_internal>:

	/* Initialize the cc3xx HW with or without RNG support */
#if CONFIG_ENTROPY_CC3XX
	res = nrf_cc3xx_platform_init();
#else
	res = nrf_cc3xx_platform_init_no_rng();
    6b78:	f7fd bcd6 	b.w	4528 <nrf_cc3xx_platform_init_no_rng>

00006b7c <hw_cc3xx_init>:

	return res;
}

static int hw_cc3xx_init(const struct device *dev)
{
    6b7c:	b508      	push	{r3, lr}
	int res;

	/* Set the RTOS abort APIs */
	nrf_cc3xx_platform_abort_init();
    6b7e:	f7fa ff8d 	bl	1a9c <nrf_cc3xx_platform_abort_init>

	/* Set the RTOS mutex APIs */
	nrf_cc3xx_platform_mutex_init();
    6b82:	f7ff fd76 	bl	6672 <nrf_cc3xx_platform_mutex_init>

	/* Enable the hardware */
	res = hw_cc3xx_init_internal(dev);
	return res;
}
    6b86:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	res = nrf_cc3xx_platform_init_no_rng();
    6b8a:	f7fd bccd 	b.w	4528 <nrf_cc3xx_platform_init_no_rng>

00006b8e <boot_swap_info_off>:
    return ALIGN_DOWN(boot_magic_off(fap) - BOOT_MAX_ALIGN, BOOT_MAX_ALIGN);
    6b8e:	6880      	ldr	r0, [r0, #8]
    6b90:	3818      	subs	r0, #24
    6b92:	f020 0007 	bic.w	r0, r0, #7
}
    6b96:	3810      	subs	r0, #16
    6b98:	4770      	bx	lr

00006b9a <boot_magic_compatible_check>:
    switch (tbl_val) {
    6b9a:	2804      	cmp	r0, #4
    6b9c:	d009      	beq.n	6bb2 <boot_magic_compatible_check+0x18>
    6b9e:	2805      	cmp	r0, #5
    6ba0:	d103      	bne.n	6baa <boot_magic_compatible_check+0x10>
        return val != BOOT_MAGIC_GOOD;
    6ba2:	1e48      	subs	r0, r1, #1
    6ba4:	bf18      	it	ne
    6ba6:	2001      	movne	r0, #1
    6ba8:	4770      	bx	lr
        return tbl_val == val;
    6baa:	1a43      	subs	r3, r0, r1
    6bac:	4258      	negs	r0, r3
    6bae:	4158      	adcs	r0, r3
    6bb0:	4770      	bx	lr
    switch (tbl_val) {
    6bb2:	2001      	movs	r0, #1
}
    6bb4:	4770      	bx	lr

00006bb6 <bootutil_buffer_is_erased>:
{
    6bb6:	b538      	push	{r3, r4, r5, lr}
    6bb8:	4615      	mov	r5, r2
    if (buffer == NULL || len == 0) {
    6bba:	460c      	mov	r4, r1
    6bbc:	b161      	cbz	r1, 6bd8 <bootutil_buffer_is_erased+0x22>
    6bbe:	b15a      	cbz	r2, 6bd8 <bootutil_buffer_is_erased+0x22>
    erased_val = flash_area_erased_val(area);
    6bc0:	f7ff fd2a 	bl	6618 <flash_area_erased_val>
    for (i = 0, u8b = (uint8_t *)buffer; i < len; i++) {
    6bc4:	4425      	add	r5, r4
    6bc6:	4621      	mov	r1, r4
        if (u8b[i] != erased_val) {
    6bc8:	f811 3b01 	ldrb.w	r3, [r1], #1
    6bcc:	4283      	cmp	r3, r0
    6bce:	d103      	bne.n	6bd8 <bootutil_buffer_is_erased+0x22>
    for (i = 0, u8b = (uint8_t *)buffer; i < len; i++) {
    6bd0:	42a9      	cmp	r1, r5
    6bd2:	d1f9      	bne.n	6bc8 <bootutil_buffer_is_erased+0x12>
    return true;
    6bd4:	2001      	movs	r0, #1
}
    6bd6:	bd38      	pop	{r3, r4, r5, pc}
        return false;
    6bd8:	2000      	movs	r0, #0
    6bda:	e7fc      	b.n	6bd6 <bootutil_buffer_is_erased+0x20>

00006bdc <boot_read_flag>:
{
    6bdc:	b538      	push	{r3, r4, r5, lr}
    6bde:	460c      	mov	r4, r1
    rc = flash_area_read(fap, off, flag, sizeof *flag);
    6be0:	2301      	movs	r3, #1
{
    6be2:	4611      	mov	r1, r2
    rc = flash_area_read(fap, off, flag, sizeof *flag);
    6be4:	4622      	mov	r2, r4
{
    6be6:	4605      	mov	r5, r0
    rc = flash_area_read(fap, off, flag, sizeof *flag);
    6be8:	f7ff fccf 	bl	658a <flash_area_read>
    if (rc < 0) {
    6bec:	2800      	cmp	r0, #0
    6bee:	db0f      	blt.n	6c10 <boot_read_flag+0x34>
    if (bootutil_buffer_is_erased(fap, flag, sizeof *flag)) {
    6bf0:	2201      	movs	r2, #1
    6bf2:	4621      	mov	r1, r4
    6bf4:	4628      	mov	r0, r5
    6bf6:	f7ff ffde 	bl	6bb6 <bootutil_buffer_is_erased>
    6bfa:	b938      	cbnz	r0, 6c0c <boot_read_flag+0x30>
    if (flag != BOOT_FLAG_SET) {
    6bfc:	7823      	ldrb	r3, [r4, #0]
    return BOOT_FLAG_SET;
    6bfe:	2b01      	cmp	r3, #1
        *flag = boot_flag_decode(*flag);
    6c00:	bf14      	ite	ne
    6c02:	2302      	movne	r3, #2
    6c04:	2301      	moveq	r3, #1
    6c06:	7023      	strb	r3, [r4, #0]
    6c08:	2000      	movs	r0, #0
}
    6c0a:	bd38      	pop	{r3, r4, r5, pc}
    6c0c:	2303      	movs	r3, #3
    6c0e:	e7fa      	b.n	6c06 <boot_read_flag+0x2a>
        return BOOT_EFLASH;
    6c10:	2001      	movs	r0, #1
    6c12:	e7fa      	b.n	6c0a <boot_read_flag+0x2e>

00006c14 <boot_write_trailer>:
{
    6c14:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    6c18:	461d      	mov	r5, r3
    6c1a:	4606      	mov	r6, r0
    6c1c:	460f      	mov	r7, r1
    6c1e:	4690      	mov	r8, r2
    align = flash_area_align(fap);
    6c20:	f7ff fcf3 	bl	660a <flash_area_align>
    align = ALIGN_UP(inlen, align);
    6c24:	1e6c      	subs	r4, r5, #1
    6c26:	4404      	add	r4, r0
    6c28:	4240      	negs	r0, r0
    6c2a:	4004      	ands	r4, r0
    if (align > BOOT_MAX_ALIGN) {
    6c2c:	2c08      	cmp	r4, #8
    6c2e:	d81a      	bhi.n	6c66 <boot_write_trailer+0x52>
    erased_val = flash_area_erased_val(fap);
    6c30:	4630      	mov	r0, r6
    6c32:	f7ff fcf1 	bl	6618 <flash_area_erased_val>
    memcpy(buf, inbuf, inlen);
    6c36:	462a      	mov	r2, r5
    erased_val = flash_area_erased_val(fap);
    6c38:	4681      	mov	r9, r0
    memcpy(buf, inbuf, inlen);
    6c3a:	4641      	mov	r1, r8
    6c3c:	4668      	mov	r0, sp
    6c3e:	f7ff fd49 	bl	66d4 <memcpy>
    memset(&buf[inlen], erased_val, align - inlen);
    6c42:	1b62      	subs	r2, r4, r5
    6c44:	4649      	mov	r1, r9
    6c46:	eb0d 0005 	add.w	r0, sp, r5
    6c4a:	f7ff fd4e 	bl	66ea <memset>
    rc = flash_area_write(fap, off, buf, align);
    6c4e:	4623      	mov	r3, r4
    6c50:	466a      	mov	r2, sp
    6c52:	4639      	mov	r1, r7
    6c54:	4630      	mov	r0, r6
    6c56:	f7ff fcad 	bl	65b4 <flash_area_write>
    if (rc != 0) {
    6c5a:	3800      	subs	r0, #0
    6c5c:	bf18      	it	ne
    6c5e:	2001      	movne	r0, #1
}
    6c60:	b003      	add	sp, #12
    6c62:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
        return -1;
    6c66:	f04f 30ff 	mov.w	r0, #4294967295
    6c6a:	e7f9      	b.n	6c60 <boot_write_trailer+0x4c>

00006c6c <boot_write_trailer_flag>:
{
    6c6c:	b507      	push	{r0, r1, r2, lr}
    return boot_write_trailer(fap, off, buf, 1);
    6c6e:	2301      	movs	r3, #1
    const uint8_t buf[1] = { flag_val };
    6c70:	f88d 2004 	strb.w	r2, [sp, #4]
    return boot_write_trailer(fap, off, buf, 1);
    6c74:	aa01      	add	r2, sp, #4
    6c76:	f7ff ffcd 	bl	6c14 <boot_write_trailer>
}
    6c7a:	b003      	add	sp, #12
    6c7c:	f85d fb04 	ldr.w	pc, [sp], #4

00006c80 <boot_write_image_ok>:
    return ALIGN_DOWN(boot_magic_off(fap) - BOOT_MAX_ALIGN, BOOT_MAX_ALIGN);
    6c80:	6881      	ldr	r1, [r0, #8]
    6c82:	3918      	subs	r1, #24
    return boot_write_trailer_flag(fap, off, BOOT_FLAG_SET);
    6c84:	2201      	movs	r2, #1
    6c86:	f021 0107 	bic.w	r1, r1, #7
    6c8a:	f7ff bfef 	b.w	6c6c <boot_write_trailer_flag>

00006c8e <boot_read_image_ok>:
    return ALIGN_DOWN(boot_magic_off(fap) - BOOT_MAX_ALIGN, BOOT_MAX_ALIGN);
    6c8e:	6882      	ldr	r2, [r0, #8]
    6c90:	3a18      	subs	r2, #24
    return boot_read_flag(fap, image_ok, boot_image_ok_off(fap));
    6c92:	f022 0207 	bic.w	r2, r2, #7
    6c96:	f7ff bfa1 	b.w	6bdc <boot_read_flag>

00006c9a <boot_read_swap_state_by_id>:
{
    6c9a:	b513      	push	{r0, r1, r4, lr}
    6c9c:	460c      	mov	r4, r1
    rc = flash_area_open(flash_area_id, &fap);
    6c9e:	b2c0      	uxtb	r0, r0
    6ca0:	a901      	add	r1, sp, #4
    6ca2:	f7fa fea3 	bl	19ec <flash_area_open>
    if (rc != 0) {
    6ca6:	b950      	cbnz	r0, 6cbe <boot_read_swap_state_by_id+0x24>
    rc = boot_read_swap_state(fap, state);
    6ca8:	4621      	mov	r1, r4
    6caa:	9801      	ldr	r0, [sp, #4]
    6cac:	f7fc fc18 	bl	34e0 <boot_read_swap_state>
    6cb0:	4604      	mov	r4, r0
    flash_area_close(fap);
    6cb2:	9801      	ldr	r0, [sp, #4]
    6cb4:	f7ff fc68 	bl	6588 <flash_area_close>
}
    6cb8:	4620      	mov	r0, r4
    6cba:	b002      	add	sp, #8
    6cbc:	bd10      	pop	{r4, pc}
        return BOOT_EFLASH;
    6cbe:	2401      	movs	r4, #1
    6cc0:	e7fa      	b.n	6cb8 <boot_read_swap_state_by_id+0x1e>

00006cc2 <boot_write_swap_info>:
{
    6cc2:	b513      	push	{r0, r1, r4, lr}
    BOOT_SET_SWAP_INFO(swap_info, image_num, swap_type);
    6cc4:	ea41 1102 	orr.w	r1, r1, r2, lsl #4
{
    6cc8:	4604      	mov	r4, r0
    BOOT_SET_SWAP_INFO(swap_info, image_num, swap_type);
    6cca:	f88d 1007 	strb.w	r1, [sp, #7]
    off = boot_swap_info_off(fap);
    6cce:	f7ff ff5e 	bl	6b8e <boot_swap_info_off>
    return boot_write_trailer(fap, off, (const uint8_t *) &swap_info, 1);
    6cd2:	2301      	movs	r3, #1
    off = boot_swap_info_off(fap);
    6cd4:	4601      	mov	r1, r0
    return boot_write_trailer(fap, off, (const uint8_t *) &swap_info, 1);
    6cd6:	f10d 0207 	add.w	r2, sp, #7
    6cda:	4620      	mov	r0, r4
    6cdc:	f7ff ff9a 	bl	6c14 <boot_write_trailer>
}
    6ce0:	b002      	add	sp, #8
    6ce2:	bd10      	pop	{r4, pc}

00006ce4 <nrfx_isr>:
#include <zephyr/kernel.h>
#include <soc/nrfx_coredep.h>

void nrfx_isr(const void *irq_handler)
{
	((nrfx_irq_handler_t)irq_handler)();
    6ce4:	4700      	bx	r0

00006ce6 <nrfx_busy_wait>:
    6ce6:	f000 b8ce 	b.w	6e86 <z_impl_k_busy_wait>

00006cea <nrfx_clock_enable>:
{
    6cea:	b508      	push	{r3, lr}
    priority = NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY;
#else
    #error "This code is not supposed to be compiled when neither POWER nor CLOCK is enabled."
#endif

    if (!NRFX_IRQ_IS_ENABLED(nrfx_get_irq_number(NRF_CLOCK)))
    6cec:	2000      	movs	r0, #0
    6cee:	f7fa ff35 	bl	1b5c <arch_irq_is_enabled>
    6cf2:	b908      	cbnz	r0, 6cf8 <nrfx_clock_enable+0xe>
    {
        NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_CLOCK), priority);
        NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_CLOCK));
    6cf4:	f7fa ff24 	bl	1b40 <arch_irq_enable>
    p_reg->LFCLKSRC = (uint32_t)(source);
    6cf8:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    6cfc:	2200      	movs	r2, #0
    6cfe:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
}
    6d02:	bd08      	pop	{r3, pc}

00006d04 <nrfx_clock_start>:
{
    6d04:	b508      	push	{r3, lr}
    switch (domain)
    6d06:	b110      	cbz	r0, 6d0e <nrfx_clock_start+0xa>
    6d08:	2801      	cmp	r0, #1
    6d0a:	d02c      	beq.n	6d66 <nrfx_clock_start+0x62>
}
    6d0c:	bd08      	pop	{r3, pc}
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    6d0e:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    6d12:	f8d2 3418 	ldr.w	r3, [r2, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    6d16:	f8d2 1418 	ldr.w	r1, [r2, #1048]	; 0x418
    6d1a:	03c8      	lsls	r0, r1, #15
    6d1c:	d40b      	bmi.n	6d36 <nrfx_clock_start+0x32>
            return ((p_reg->LFCLKRUN & CLOCK_LFCLKRUN_STATUS_Msk)
    6d1e:	f8d2 3414 	ldr.w	r3, [r2, #1044]	; 0x414
                else if (nrf_clock_start_task_check(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK))
    6d22:	07d9      	lsls	r1, r3, #31
    6d24:	d50f      	bpl.n	6d46 <nrfx_clock_start+0x42>
    return (nrf_clock_lfclk_t)((p_reg->LFCLKSRCCOPY & CLOCK_LFCLKSRCCOPY_SRC_Msk)
    6d26:	f8d2 341c 	ldr.w	r3, [r2, #1052]	; 0x41c
    is_correct_clk = is_correct_clk || (*p_lfclksrc == NRF_CLOCK_LFCLK_RC);
    6d2a:	079b      	lsls	r3, r3, #30
    6d2c:	d408      	bmi.n	6d40 <nrfx_clock_start+0x3c>
    p_reg->INTENSET = mask;
    6d2e:	2302      	movs	r3, #2
    6d30:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
                        break;
    6d34:	e7ea      	b.n	6d0c <nrfx_clock_start+0x8>
                                        >> CLOCK_LFCLKSTAT_SRC_Pos);
    6d36:	f003 0303 	and.w	r3, r3, #3
    is_correct_clk = is_correct_clk || (*p_lfclksrc == NRF_CLOCK_LFCLK_RC);
    6d3a:	2b01      	cmp	r3, #1
    6d3c:	d004      	beq.n	6d48 <nrfx_clock_start+0x44>
    6d3e:	b113      	cbz	r3, 6d46 <nrfx_clock_start+0x42>
        clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
    6d40:	2000      	movs	r0, #0
    6d42:	f7fc fde7 	bl	3914 <clock_stop>
        *p_lfclksrc = clock_initial_lfclksrc_get();
    6d46:	2300      	movs	r3, #0
    p_reg->LFCLKSRC = (uint32_t)(source);
    6d48:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    6d4c:	f8c2 3518 	str.w	r3, [r2, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    6d50:	2300      	movs	r3, #0
    6d52:	f8c2 3104 	str.w	r3, [r2, #260]	; 0x104
    6d56:	f8d2 3104 	ldr.w	r3, [r2, #260]	; 0x104
    p_reg->INTENSET = mask;
    6d5a:	2302      	movs	r3, #2
    6d5c:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    6d60:	2301      	movs	r3, #1
    6d62:	6093      	str	r3, [r2, #8]
}
    6d64:	e7d2      	b.n	6d0c <nrfx_clock_start+0x8>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    6d66:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    6d6a:	2200      	movs	r2, #0
    6d6c:	f8c3 2100 	str.w	r2, [r3, #256]	; 0x100
    6d70:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    p_reg->INTENSET = mask;
    6d74:	f8c3 0304 	str.w	r0, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    6d78:	6018      	str	r0, [r3, #0]
}
    6d7a:	e7c7      	b.n	6d0c <nrfx_clock_start+0x8>

00006d7c <nrfx_clock_stop>:
    clock_stop(domain);
    6d7c:	f7fc bdca 	b.w	3914 <clock_stop>

00006d80 <nrf_gpio_reconfigure>:
{
    6d80:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
    6d82:	9001      	str	r0, [sp, #4]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    6d84:	a801      	add	r0, sp, #4
{
    6d86:	e9dd 4708 	ldrd	r4, r7, [sp, #32]
    6d8a:	4616      	mov	r6, r2
    6d8c:	461d      	mov	r5, r3
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    6d8e:	f7fc fe69 	bl	3a64 <nrf_gpio_pin_port_decode>
    uint32_t cnf = reg->PIN_CNF[pin_number];
    6d92:	9b01      	ldr	r3, [sp, #4]
                         (p_input ? GPIO_PIN_CNF_INPUT_Msk : 0) |
    6d94:	f1b6 0c00 	subs.w	ip, r6, #0
    6d98:	bf18      	it	ne
    6d9a:	f04f 0c01 	movne.w	ip, #1
    6d9e:	eb00 0083 	add.w	r0, r0, r3, lsl #2
    uint32_t to_update = (p_dir   ? GPIO_PIN_CNF_DIR_Msk   : 0) |
    6da2:	1e0b      	subs	r3, r1, #0
    6da4:	bf18      	it	ne
    6da6:	2301      	movne	r3, #1
                         (p_pull  ? GPIO_PIN_CNF_PULL_Msk  : 0) |
    6da8:	2d00      	cmp	r5, #0
    uint32_t to_update = (p_dir   ? GPIO_PIN_CNF_DIR_Msk   : 0) |
    6daa:	ea43 034c 	orr.w	r3, r3, ip, lsl #1
                         (p_pull  ? GPIO_PIN_CNF_PULL_Msk  : 0) |
    6dae:	bf14      	ite	ne
    6db0:	f04f 0c0c 	movne.w	ip, #12
    6db4:	f04f 0c00 	moveq.w	ip, #0
                         (p_drive ? GPIO_PIN_CNF_DRIVE_Msk : 0) |
    6db8:	2c00      	cmp	r4, #0
                         (p_input ? GPIO_PIN_CNF_INPUT_Msk : 0) |
    6dba:	ea43 030c 	orr.w	r3, r3, ip
                         (p_drive ? GPIO_PIN_CNF_DRIVE_Msk : 0) |
    6dbe:	bf14      	ite	ne
    6dc0:	f44f 6ce0 	movne.w	ip, #1792	; 0x700
    6dc4:	f04f 0c00 	moveq.w	ip, #0
                         (p_sense ? GPIO_PIN_CNF_SENSE_Msk : 0);
    6dc8:	2f00      	cmp	r7, #0
                         (p_pull  ? GPIO_PIN_CNF_PULL_Msk  : 0) |
    6dca:	ea43 030c 	orr.w	r3, r3, ip
    uint32_t cnf = reg->PIN_CNF[pin_number];
    6dce:	f8d0 2700 	ldr.w	r2, [r0, #1792]	; 0x700
                         (p_sense ? GPIO_PIN_CNF_SENSE_Msk : 0);
    6dd2:	bf14      	ite	ne
    6dd4:	f44f 3c40 	movne.w	ip, #196608	; 0x30000
    6dd8:	f04f 0c00 	moveq.w	ip, #0
    uint32_t to_update = (p_dir   ? GPIO_PIN_CNF_DIR_Msk   : 0) |
    6ddc:	ea43 030c 	orr.w	r3, r3, ip
    cnf &= ~to_update;
    6de0:	ea22 0303 	bic.w	r3, r2, r3
    cnf |= ((uint32_t)(p_dir   ? *p_dir   : 0) << GPIO_PIN_CNF_DIR_Pos)   |
    6de4:	b101      	cbz	r1, 6de8 <nrf_gpio_reconfigure+0x68>
    6de6:	7809      	ldrb	r1, [r1, #0]
           ((uint32_t)(p_input ? *p_input : 0) << GPIO_PIN_CNF_INPUT_Pos) |
    6de8:	b10e      	cbz	r6, 6dee <nrf_gpio_reconfigure+0x6e>
    6dea:	7836      	ldrb	r6, [r6, #0]
    6dec:	0076      	lsls	r6, r6, #1
    6dee:	4319      	orrs	r1, r3
           ((uint32_t)(p_pull  ? *p_pull  : 0) << GPIO_PIN_CNF_PULL_Pos)  |
    6df0:	b10d      	cbz	r5, 6df6 <nrf_gpio_reconfigure+0x76>
    6df2:	782d      	ldrb	r5, [r5, #0]
    6df4:	00ad      	lsls	r5, r5, #2
    6df6:	4331      	orrs	r1, r6
           ((uint32_t)(p_drive ? *p_drive : 0) << GPIO_PIN_CNF_DRIVE_Pos) |
    6df8:	b10c      	cbz	r4, 6dfe <nrf_gpio_reconfigure+0x7e>
    6dfa:	7824      	ldrb	r4, [r4, #0]
    6dfc:	0224      	lsls	r4, r4, #8
    6dfe:	4329      	orrs	r1, r5
           ((uint32_t)(p_sense ? *p_sense : 0)<< GPIO_PIN_CNF_SENSE_Pos);
    6e00:	b10f      	cbz	r7, 6e06 <nrf_gpio_reconfigure+0x86>
    6e02:	783f      	ldrb	r7, [r7, #0]
    6e04:	043f      	lsls	r7, r7, #16
    cnf |= ((uint32_t)(p_dir   ? *p_dir   : 0) << GPIO_PIN_CNF_DIR_Pos)   |
    6e06:	430c      	orrs	r4, r1
    6e08:	433c      	orrs	r4, r7
    reg->PIN_CNF[pin_number] = cnf;
    6e0a:	f8c0 4700 	str.w	r4, [r0, #1792]	; 0x700
}
    6e0e:	b003      	add	sp, #12
    6e10:	bdf0      	pop	{r4, r5, r6, r7, pc}

00006e12 <nrf_gpio_cfg_sense_set>:
{
    6e12:	b51f      	push	{r0, r1, r2, r3, r4, lr}
    nrf_gpio_reconfigure(pin_number, NULL, NULL, NULL, NULL, &sense_config);
    6e14:	f10d 030f 	add.w	r3, sp, #15
    6e18:	9301      	str	r3, [sp, #4]
    6e1a:	2300      	movs	r3, #0
{
    6e1c:	f88d 100f 	strb.w	r1, [sp, #15]
    nrf_gpio_reconfigure(pin_number, NULL, NULL, NULL, NULL, &sense_config);
    6e20:	9300      	str	r3, [sp, #0]
    6e22:	461a      	mov	r2, r3
    6e24:	4619      	mov	r1, r3
    6e26:	f7ff ffab 	bl	6d80 <nrf_gpio_reconfigure>
}
    6e2a:	b005      	add	sp, #20
    6e2c:	f85d fb04 	ldr.w	pc, [sp], #4

00006e30 <nrfx_nvmc_flash_size_get>:
    return p_reg->CODEPAGESIZE;
    6e30:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    6e34:	691a      	ldr	r2, [r3, #16]
    return p_reg->CODESIZE;
    6e36:	6958      	ldr	r0, [r3, #20]
}

uint32_t nrfx_nvmc_flash_size_get(void)
{
    return flash_total_size_get();
}
    6e38:	4350      	muls	r0, r2
    6e3a:	4770      	bx	lr

00006e3c <nrfx_nvmc_flash_page_size_get>:
    return p_reg->CODEPAGESIZE;
    6e3c:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    6e40:	6918      	ldr	r0, [r3, #16]

uint32_t nrfx_nvmc_flash_page_size_get(void)
{
    return flash_page_size_get();
}
    6e42:	4770      	bx	lr

00006e44 <nrfx_nvmc_flash_page_count_get>:
    return p_reg->CODESIZE;
    6e44:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    6e48:	6958      	ldr	r0, [r3, #20]

uint32_t nrfx_nvmc_flash_page_count_get(void)
{
    return flash_page_count_get();
}
    6e4a:	4770      	bx	lr

00006e4c <SEGGER_RTT_Init>:
*    Initializes the RTT Control Block.
*    Should be used in RAM targets, at start of the application.
*
*/
void SEGGER_RTT_Init (void) {
  _DoInit();
    6e4c:	f7fd b9b4 	b.w	41b8 <_DoInit>

00006e50 <rtt_init>:
 */

K_MUTEX_DEFINE(rtt_term_mutex);

static int rtt_init(const struct device *unused)
{
    6e50:	b508      	push	{r3, lr}
	ARG_UNUSED(unused);

	SEGGER_RTT_Init();
    6e52:	f7ff fffb 	bl	6e4c <SEGGER_RTT_Init>

	return 0;
}
    6e56:	2000      	movs	r0, #0
    6e58:	bd08      	pop	{r3, pc}

00006e5a <z_device_state_init>:

	while (dev < __device_end) {
		z_object_init(dev);
		++dev;
	}
}
    6e5a:	4770      	bx	lr

00006e5c <z_device_is_ready>:
{
	/*
	 * if an invalid device pointer is passed as argument, this call
	 * reports the `device` as not ready for usage.
	 */
	if (dev == NULL) {
    6e5c:	b140      	cbz	r0, 6e70 <z_device_is_ready+0x14>
		return false;
	}

	return dev->state->initialized && (dev->state->init_res == 0U);
    6e5e:	68c3      	ldr	r3, [r0, #12]
    6e60:	7858      	ldrb	r0, [r3, #1]
    6e62:	f010 0001 	ands.w	r0, r0, #1
    6e66:	bf1e      	ittt	ne
    6e68:	7818      	ldrbne	r0, [r3, #0]
    6e6a:	fab0 f080 	clzne	r0, r0
    6e6e:	0940      	lsrne	r0, r0, #5
}
    6e70:	4770      	bx	lr

00006e72 <z_early_memset>:
	(void) memset(dst, c, n);
    6e72:	f7ff bc3a 	b.w	66ea <memset>

00006e76 <z_early_memcpy>:
	(void) memcpy(dst, src, n);
    6e76:	f7ff bc2d 	b.w	66d4 <memcpy>

00006e7a <k_is_in_isr>:
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    6e7a:	f3ef 8005 	mrs	r0, IPSR
}

bool k_is_in_isr(void)
{
	return arch_is_in_isr();
}
    6e7e:	3800      	subs	r0, #0
    6e80:	bf18      	it	ne
    6e82:	2001      	movne	r0, #1
    6e84:	4770      	bx	lr

00006e86 <z_impl_k_busy_wait>:
#endif

void z_impl_k_busy_wait(uint32_t usec_to_wait)
{
	SYS_PORT_TRACING_FUNC_ENTER(k_thread, busy_wait, usec_to_wait);
	if (usec_to_wait == 0U) {
    6e86:	b108      	cbz	r0, 6e8c <z_impl_k_busy_wait+0x6>
		if ((current_cycles - start_cycles) >= cycles_to_wait) {
			break;
		}
	}
#else
	arch_busy_wait(usec_to_wait);
    6e88:	f7fb ba8c 	b.w	23a4 <arch_busy_wait>
#endif /* CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT */
	SYS_PORT_TRACING_FUNC_EXIT(k_thread, busy_wait, usec_to_wait);
}
    6e8c:	4770      	bx	lr

00006e8e <_OffsetAbsSyms>:

#include <gen_offset.h>

#include "offsets_aarch32.c"

GEN_ABS_SYM_END
    6e8e:	4770      	bx	lr

00006e90 <nrf_cc310_bl_ecdsa_verify_secp256r1>:
    6e90:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    6e94:	9f06      	ldr	r7, [sp, #24]
    6e96:	4604      	mov	r4, r0
    6e98:	4615      	mov	r5, r2
    6e9a:	461e      	mov	r6, r3
    6e9c:	f7fd fd16 	bl	48cc <nrf_cc310_bl_ecdsa_verify_init_secp256r1>
    6ea0:	b938      	cbnz	r0, 6eb2 <nrf_cc310_bl_ecdsa_verify_secp256r1+0x22>
    6ea2:	463b      	mov	r3, r7
    6ea4:	4632      	mov	r2, r6
    6ea6:	4629      	mov	r1, r5
    6ea8:	4620      	mov	r0, r4
    6eaa:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
    6eae:	f7fd bd33 	b.w	4918 <nrf_cc310_bl_ecdsa_verify_hash_secp256r1>
    6eb2:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00006eb6 <PkaInitAndMutexLock>:
    6eb6:	460a      	mov	r2, r1
    6eb8:	2100      	movs	r1, #0
    6eba:	f7fd bfb5 	b.w	4e28 <PkaInitPka>

00006ebe <SaSi_PalMemCopy>:
    6ebe:	f7ff bc09 	b.w	66d4 <memcpy>

00006ec2 <SaSi_PalMemSet>:
    6ec2:	f7ff bc12 	b.w	66ea <memset>

00006ec6 <SaSi_PalMemSetZero>:
    6ec6:	460a      	mov	r2, r1
    6ec8:	2100      	movs	r1, #0
    6eca:	f7ff bc0e 	b.w	66ea <memset>

00006ece <CRYS_COMMON_ReverseMemcpy32>:
    6ece:	eb01 0282 	add.w	r2, r1, r2, lsl #2
    6ed2:	3804      	subs	r0, #4
    6ed4:	428a      	cmp	r2, r1
    6ed6:	d101      	bne.n	6edc <CRYS_COMMON_ReverseMemcpy32+0xe>
    6ed8:	2000      	movs	r0, #0
    6eda:	4770      	bx	lr
    6edc:	f852 3d04 	ldr.w	r3, [r2, #-4]!
    6ee0:	ba1b      	rev	r3, r3
    6ee2:	f840 3f04 	str.w	r3, [r0, #4]!
    6ee6:	e7f5      	b.n	6ed4 <CRYS_COMMON_ReverseMemcpy32+0x6>
