
zephyr.elf:     file format elf32-littlearm


Disassembly of section rom_start:

00000000 <_vector_table>:
	return cb(str, strl, ctx);
}

int cbvprintf_package(void *packaged, size_t len, uint32_t flags,
		      const char *fmt, va_list ap)
{
   0:	80 19 00 20 c9 19 00 00 af 60 00 00 9d 19 00 00     ... .....`......
	bool rws_pos_en = !!(flags & CBPRINTF_PACKAGE_ADD_RW_STR_POS);
	/* Get number of first read only strings present in the string.
	 * There is always at least 1 (fmt) but flags can indicate more, e.g
	 * fixed prefix appended to all strings.
	 */
	int fros_cnt = 1 + Z_CBPRINTF_PACKAGE_FIRST_RO_STR_CNT_GET(flags);
  10:	9d 19 00 00 9d 19 00 00 9d 19 00 00 9d 19 00 00     ................
	...

	/*
	 * Otherwise we must ensure we can store at least
	 * the pointer to the format string itself.
	 */
	if (buf0 != NULL && BUF_OFFSET + sizeof(char *) > len) {
  2c:	dd 16 00 00 9d 19 00 00 00 00 00 00 85 16 00 00     ................
		buf += len % CBPRINTF_PACKAGE_ALIGNMENT;
  3c:	9d 19 00 00                                         ....

00000040 <_irq_vector_table>:
		len = CBPRINTF_PACKAGE_ALIGNMENT - (len % CBPRINTF_PACKAGE_ALIGNMENT);
  40:	5d 17 00 00 5d 17 00 00 5d 17 00 00 5d 17 00 00     ]...]...]...]...
	int arg_idx	      = -1; /* Argument index. Preincremented thus starting from -1.*/
  50:	5d 17 00 00 5d 17 00 00 5d 17 00 00 5d 17 00 00     ]...]...]...]...
		/* copy va_list data over to our buffer */
		if (is_str_arg) {
			s = va_arg(ap, char *);
process_string:
			if (buf0 != NULL) {
				*(const char **)buf = s;
  60:	5d 17 00 00 5d 17 00 00 5d 17 00 00 5d 17 00 00     ]...]...]...]...
#else
	#define RO_START 0
	#define RO_END 0
#endif

	return (((const char *)addr >= (const char *)RO_START) &&
  70:	5d 17 00 00 5d 17 00 00 5d 17 00 00 5d 17 00 00     ]...]...]...]...
			bool do_ro = !!(flags & CBPRINTF_PACKAGE_ADD_RO_STR_POS);

			if (is_ro && !do_ro) {
				/* nothing to do */
			} else {
				uint32_t s_ptr_idx = BUF_OFFSET / sizeof(int);
  80:	5d 17 00 00 5d 17 00 00 5d 17 00 00 5d 17 00 00     ]...]...]...]...
				if (do_ro && s_ptr_idx > STR_POS_MASK) {
					__ASSERT(false, "String with too many arguments");
					return -EINVAL;
				}

				if (s_idx >= ARRAY_SIZE(str_ptr_pos)) {
  90:	5d 17 00 00 5d 17 00 00 5d 17 00 00 5d 17 00 00     ]...]...]...]...
					/*
					 * Remember string pointer location.
					 * We will append non-ro strings later.
					 */
					str_ptr_pos[s_idx] = s_ptr_idx;
					str_ptr_arg[s_idx] = arg_idx;
  a0:	5d 17 00 00 5d 17 00 00 5d 17 00 00 5d 17 00 00     ]...]...]...]...
					if (is_ro) {
						/* flag read-only string. */
						str_ptr_pos[s_idx] |= STR_POS_RO_FLAG;
						s_ro_cnt++;
					} else {
						s_rw_cnt++;
  b0:	5d 17 00 00 5d 17 00 00 5d 17 00 00 5d 17 00 00     ]...]...]...]...
			switch (*fmt) {
  c0:	5d 17 00 00 5d 17 00 00 5d 17 00 00 5d 17 00 00     ]...]...]...]...
  d0:	5d 17 00 00 5d 17 00 00 5d 17 00 00 5d 17 00 00     ]...]...]...]...
  e0:	5d 17 00 00 5d 17 00 00 5d 17 00 00 5d 17 00 00     ]...]...]...]...
  f0:	5d 17 00 00 5d 17 00 00 5d 17 00 00 5d 17 00 00     ]...]...]...]...
 100:	5d 17 00 00 5d 17 00 00 5d 17 00 00 5d 17 00 00     ]...]...]...]...
 110:	5d 17 00 00 5d 17 00 00 5d 17 00 00 5d 17 00 00     ]...]...]...]...
				align = VA_STACK_ALIGN(void *);
 120:	5d 17 00 00 5d 17 00 00 5d 17 00 00 5d 17 00 00     ]...]...]...]...
			switch (*fmt) {
 130:	5d 17 00 00 5d 17 00 00 5d 17 00 00 5d 17 00 00     ]...]...]...]...
 140:	5d 17 00 00 5d 17 00 00 5d 17 00 00 5d 17 00 00     ]...]...]...]...
		if (buf0 != NULL && BUF_OFFSET + size > len) {
 150:	5d 17 00 00                                         ]...

Disassembly of section text:

00000154 <__aeabi_uldivmod>:
     154:	b953      	cbnz	r3, 16c <__aeabi_uldivmod+0x18>
     156:	b94a      	cbnz	r2, 16c <__aeabi_uldivmod+0x18>
     158:	2900      	cmp	r1, #0
     15a:	bf08      	it	eq
     15c:	2800      	cmpeq	r0, #0
		if (is_str_arg) {
     15e:	bf1c      	itt	ne
     160:	f04f 31ff 	movne.w	r1, #4294967295
				s_idx++;
			}
			buf += sizeof(char *);

			is_str_arg = false;
		} else if (size == sizeof(int)) {
     164:	f04f 30ff 	movne.w	r0, #4294967295
			int v = va_arg(ap, int);
     168:	f000 b80c 	b.w	184 <__aeabi_idiv0>

			if (buf0 != NULL) {
				*(int *)buf = v;
			}
			buf += sizeof(int);
     16c:	f1ad 0c08 	sub.w	ip, sp, #8
     170:	e96d ce04 	strd	ip, lr, [sp, #-16]!
				arg_idx--;
     174:	f000 f808 	bl	188 <__udivmoddi4>
				parsing = false;
     178:	f8dd e004 	ldr.w	lr, [sp, #4]
				continue;
     17c:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
				if (fmt[-1] == 'l') {
     180:	b004      	add	sp, #16
     182:	4770      	bx	lr

00000184 <__aeabi_idiv0>:
     184:	4770      	bx	lr
					if (fmt[-2] == 'l') {
     186:	bf00      	nop

00000188 <__udivmoddi4>:
     188:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
				parsing = false;
     18c:	4686      	mov	lr, r0
					if (fmt[-2] == 'l') {
     18e:	468c      	mov	ip, r1
     190:	4608      	mov	r0, r1
						align = VA_STACK_ALIGN(long long);
     192:	9e08      	ldr	r6, [sp, #32]
     194:	4615      	mov	r5, r2
				size = sizeof(void *);
     196:	4674      	mov	r4, lr
     198:	4619      	mov	r1, r3
					v.ld = va_arg(ap, long double);
     19a:	2b00      	cmp	r3, #0
     19c:	f040 80c1 	bne.w	322 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xa2>
     1a0:	4285      	cmp	r5, r0
				buf = (void *) ROUND_UP(buf, align);
     1a2:	fab2 f282 	clz	r2, r2
     1a6:	d945      	bls.n	234 <__data_size+0x58>
					v.ld = va_arg(ap, long double);
     1a8:	b14a      	cbz	r2, 1be <__udivmoddi4+0x36>
     1aa:	f1c2 0320 	rsb	r3, r2, #32
					if (BUF_OFFSET + size > len) {
     1ae:	fa00 fc02 	lsl.w	ip, r0, r2
     1b2:	4095      	lsls	r5, r2
     1b4:	4094      	lsls	r4, r2
     1b6:	fa2e f303 	lsr.w	r3, lr, r3
						*(long double *)buf = v.ld;
     1ba:	ea43 0c0c 	orr.w	ip, r3, ip
				parsing = false;
     1be:	ea4f 4e15 	mov.w	lr, r5, lsr #16
			switch (*fmt) {
     1c2:	b2a8      	uxth	r0, r5
     1c4:	0c23      	lsrs	r3, r4, #16
     1c6:	fbbc f8fe 	udiv	r8, ip, lr
			if (*++fmt == '\0') {
     1ca:	fb0e cc18 	mls	ip, lr, r8, ip
     1ce:	fb08 f900 	mul.w	r9, r8, r0
			if (!parsing) {
     1d2:	ea43 430c 	orr.w	r3, r3, ip, lsl #16
     1d6:	4599      	cmp	r9, r3
				if (*fmt == '%') {
     1d8:	d928      	bls.n	22c <__data_size+0x50>
     1da:	18eb      	adds	r3, r5, r3
					parsing = true;
     1dc:	f108 37ff 	add.w	r7, r8, #4294967295
					arg_idx++;
     1e0:	d204      	bcs.n	1ec <__data_size+0x10>
     1e2:	4599      	cmp	r9, r3
     1e4:	d902      	bls.n	1ec <__data_size+0x10>
				align = VA_STACK_ALIGN(size_t);
     1e6:	f1a8 0702 	sub.w	r7, r8, #2
     1ea:	442b      	add	r3, r5
			switch (*fmt) {
     1ec:	eba3 0309 	sub.w	r3, r3, r9
     1f0:	b2a4      	uxth	r4, r4
				parsing = false;
     1f2:	fbb3 fcfe 	udiv	ip, r3, lr

			if (buf0 != NULL) {
				*(long *)buf = v;
			}
			buf += sizeof(long);
		} else if (size == sizeof(long long)) {
     1f6:	fb0e 331c 	mls	r3, lr, ip, r3
					return -EINVAL;
     1fa:	fb0c f000 	mul.w	r0, ip, r0
     1fe:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
			long long v = va_arg(ap, long long);
     202:	42a0      	cmp	r0, r4
     204:	d914      	bls.n	230 <__data_size+0x54>
     206:	192c      	adds	r4, r5, r4
     208:	f10c 33ff 	add.w	r3, ip, #4294967295

			if (buf0 != NULL) {
				if (Z_CBPRINTF_VA_STACK_LL_DBL_MEMCPY) {
					memcpy(buf, &v, sizeof(long long));
				} else {
					*(long long *)buf = v;
     20c:	d204      	bcs.n	218 <__data_size+0x3c>
     20e:	42a0      	cmp	r0, r4
				}
			}
			buf += sizeof(long long);
     210:	d902      	bls.n	218 <__data_size+0x3c>
     212:	f1ac 0302 	sub.w	r3, ip, #2
		if (is_str_arg) {
     216:	442c      	add	r4, r5
		} else if (size == sizeof(int)) {
     218:	1a24      	subs	r4, r4, r0
     21a:	ea43 4007 	orr.w	r0, r3, r7, lsl #16
			int v = va_arg(ap, int);
     21e:	b11e      	cbz	r6, 228 <__data_size+0x4c>
			if (buf0 != NULL) {
     220:	40d4      	lsrs	r4, r2
		} else if (size == sizeof(long long)) {
     222:	2300      	movs	r3, #0
     224:	6034      	str	r4, [r6, #0]
			long long v = va_arg(ap, long long);
     226:	6073      	str	r3, [r6, #4]
     228:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
     22c:	4647      	mov	r7, r8
     22e:	e7dd      	b.n	1ec <__data_size+0x10>
     230:	4663      	mov	r3, ip
			if (buf0 != NULL) {
     232:	e7f1      	b.n	218 <__data_size+0x3c>
			bool is_ro = (fros_cnt-- > 0) ? true : ptr_in_rodata(s);
     234:	bb92      	cbnz	r2, 29c <CONFIG_PM_PARTITION_SIZE_PROVISION+0x1c>
     236:	1b43      	subs	r3, r0, r5
     238:	2101      	movs	r1, #1
			s = va_arg(ap, char *);
     23a:	ea4f 4e15 	mov.w	lr, r5, lsr #16
     23e:	b2af      	uxth	r7, r5
     240:	0c20      	lsrs	r0, r4, #16
			if (is_ro && !do_ro) {
     242:	fbb3 fcfe 	udiv	ip, r3, lr
     246:	fb0e 331c 	mls	r3, lr, ip, r3
			bool is_ro = (fros_cnt-- > 0) ? true : ptr_in_rodata(s);
     24a:	fb0c f807 	mul.w	r8, ip, r7
				uint32_t s_ptr_idx = BUF_OFFSET / sizeof(int);
     24e:	ea40 4303 	orr.w	r3, r0, r3, lsl #16
     252:	4598      	cmp	r8, r3
				if (do_ro && s_ptr_idx > STR_POS_MASK) {
     254:	d961      	bls.n	31a <CONFIG_PM_PARTITION_SIZE_PROVISION+0x9a>
     256:	18eb      	adds	r3, r5, r3
     258:	f10c 30ff 	add.w	r0, ip, #4294967295
				if (s_idx >= ARRAY_SIZE(str_ptr_pos)) {
     25c:	d204      	bcs.n	268 <__data_size+0x8c>
				if (buf0 != NULL) {
     25e:	4598      	cmp	r8, r3
					str_ptr_pos[s_idx] = s_ptr_idx;
     260:	d902      	bls.n	268 <__data_size+0x8c>
     262:	f1ac 0002 	sub.w	r0, ip, #2
     266:	442b      	add	r3, r5
					str_ptr_arg[s_idx] = arg_idx;
     268:	eba3 0308 	sub.w	r3, r3, r8
					str_ptr_pos[s_idx] = s_ptr_idx;
     26c:	b2a4      	uxth	r4, r4
     26e:	fbb3 fcfe 	udiv	ip, r3, lr
					str_ptr_arg[s_idx] = arg_idx;
     272:	fb0e 331c 	mls	r3, lr, ip, r3
					if (is_ro) {
     276:	fb0c f707 	mul.w	r7, ip, r7
     27a:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
						str_ptr_pos[s_idx] |= STR_POS_RO_FLAG;
     27e:	42a7      	cmp	r7, r4
     280:	d94d      	bls.n	31e <CONFIG_PM_PARTITION_SIZE_PROVISION+0x9e>
     282:	192c      	adds	r4, r5, r4
						s_ro_cnt++;
     284:	f10c 33ff 	add.w	r3, ip, #4294967295
				s_idx++;
     288:	d204      	bcs.n	294 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x14>
					if (BUF_OFFSET + size > len) {
     28a:	42a7      	cmp	r7, r4
     28c:	d902      	bls.n	294 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x14>
			switch (*fmt) {
     28e:	f1ac 0302 	sub.w	r3, ip, #2
			buf += sizeof(char *);
     292:	442c      	add	r4, r5
					if (BUF_OFFSET + size > len) {
     294:	1be4      	subs	r4, r4, r7
     296:	ea43 4000 	orr.w	r0, r3, r0, lsl #16
			bool is_ro = (fros_cnt-- > 0) ? true : ptr_in_rodata(s);
     29a:	e7c0      	b.n	21e <__data_size+0x42>
     29c:	f1c2 0320 	rsb	r3, r2, #32
				} else if (is_ro) {
     2a0:	4095      	lsls	r5, r2
     2a2:	4094      	lsls	r4, r2
					len += 1;
     2a4:	fa20 f103 	lsr.w	r1, r0, r3
				} else if (rws_pos_en) {
     2a8:	fa2e f303 	lsr.w	r3, lr, r3
     2ac:	ea4f 4e15 	mov.w	lr, r5, lsr #16
					len += strlen(s) + 1 + 1;
     2b0:	4090      	lsls	r0, r2
     2b2:	b2af      	uxth	r7, r5
     2b4:	4303      	orrs	r3, r0
     2b6:	fbb1 fcfe 	udiv	ip, r1, lr
     2ba:	fb0e 101c 	mls	r0, lr, ip, r1
     2be:	0c19      	lsrs	r1, r3, #16
     2c0:	fb0c f807 	mul.w	r8, ip, r7
	 * We remember the size of the argument list as a multiple of
	 * sizeof(int) and limit it to a 8-bit field. That means 1020 bytes
	 * worth of va_list, or about 127 arguments on a 64-bit system
	 * (twice that on 32-bit systems). That ought to be good enough.
	 */
	if (BUF_OFFSET / sizeof(int) > 255) {
     2c4:	ea41 4100 	orr.w	r1, r1, r0, lsl #16
     2c8:	4588      	cmp	r8, r1

	/*
	 * If all we wanted was to count required buffer size
	 * then we have it now.
	 */
	if (buf0 == NULL) {
     2ca:	d922      	bls.n	312 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x92>
		return BUF_OFFSET + len - CBPRINTF_PACKAGE_ALIGNMENT;
     2cc:	1869      	adds	r1, r5, r1
     2ce:	f10c 30ff 	add.w	r0, ip, #4294967295
     2d2:	d204      	bcs.n	2de <CONFIG_PM_PARTITION_SIZE_PROVISION+0x5e>
     2d4:	4588      	cmp	r8, r1
     2d6:	d902      	bls.n	2de <CONFIG_PM_PARTITION_SIZE_PROVISION+0x5e>
     2d8:	f1ac 0002 	sub.w	r0, ip, #2
	*(char **)buf0 = NULL;

	/* Record end of argument list. */
	pkg_hdr->desc.len = BUF_OFFSET / sizeof(int);

	if (rws_pos_en) {
     2dc:	4429      	add	r1, r5
	pkg_hdr->desc.len = BUF_OFFSET / sizeof(int);
     2de:	eba1 0108 	sub.w	r1, r1, r8
     2e2:	b29b      	uxth	r3, r3
		/* Strings are appended, update location counter. */
		pkg_hdr->desc.str_cnt = 0;
		pkg_hdr->desc.rw_str_cnt = s_rw_cnt;
     2e4:	fbb1 fcfe 	udiv	ip, r1, lr
	if (rws_pos_en) {
     2e8:	fb0e 111c 	mls	r1, lr, ip, r1
		/* Strings are appended, update append counter. */
		pkg_hdr->desc.str_cnt = s_rw_cnt;
		pkg_hdr->desc.rw_str_cnt = 0;
	}

	pkg_hdr->desc.ro_str_cnt = s_ro_cnt;
     2ec:	fb0c f707 	mul.w	r7, ip, r7
#ifdef CONFIG_CBPRINTF_PACKAGE_HEADER_STORE_CREATION_FLAGS
	pkg_hdr->desc.pkg_flags = flags;
#endif

	/* Store strings pointer locations of read only strings. */
	if (s_ro_cnt) {
     2f0:	ea43 4301 	orr.w	r3, r3, r1, lsl #16
     2f4:	429f      	cmp	r7, r3
		for (i = 0; i < s_idx; i++) {
     2f6:	d90e      	bls.n	316 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x96>
     2f8:	18eb      	adds	r3, r5, r3
			}

			uint8_t pos = str_ptr_pos[i] & STR_POS_MASK;

			/* make sure it fits */
			if (BUF_OFFSET + 1 > len) {
     2fa:	f10c 31ff 	add.w	r1, ip, #4294967295
		for (i = 0; i < s_idx; i++) {
     2fe:	d204      	bcs.n	30a <CONFIG_PM_PARTITION_SIZE_PROVISION+0x8a>
     300:	429f      	cmp	r7, r3
			continue;
		}

		if (rws_pos_en) {
			size = 0;
			*buf++ = str_ptr_arg[i];
     302:	d902      	bls.n	30a <CONFIG_PM_PARTITION_SIZE_PROVISION+0x8a>
     304:	f1ac 0102 	sub.w	r1, ip, #2
			/* find the string length including terminating '\0' */
			size = strlen(s) + 1;
		}

		/* make sure it fits */
		if (BUF_OFFSET + 1 + size > len) {
     308:	442b      	add	r3, r5
     30a:	1bdb      	subs	r3, r3, r7
     30c:	ea41 4100 	orr.w	r1, r1, r0, lsl #16
			*buf++ = str_ptr_arg[i];
     310:	e793      	b.n	23a <__data_size+0x5e>
     312:	4660      	mov	r0, ip
	for (i = 0; i < s_idx; i++) {
     314:	e7e3      	b.n	2de <CONFIG_PM_PARTITION_SIZE_PROVISION+0x5e>
     316:	4661      	mov	r1, ip
	/*
	 * TODO: remove pointers for appended strings since they're useless.
	 * TODO: explore leveraging same mechanism to remove alignment padding
	 */

	return BUF_OFFSET;
     318:	e7f7      	b.n	30a <CONFIG_PM_PARTITION_SIZE_PROVISION+0x8a>
     31a:	4660      	mov	r0, ip
		pkg_hdr->desc.str_cnt = s_rw_cnt;
     31c:	e7a4      	b.n	268 <__data_size+0x8c>
		pkg_hdr->desc.rw_str_cnt = 0;
     31e:	4663      	mov	r3, ip
			if (!(str_ptr_pos[i] & STR_POS_RO_FLAG)) {
     320:	e7b8      	b.n	294 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x14>
     322:	4283      	cmp	r3, r0
     324:	d906      	bls.n	334 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xb4>
     326:	b916      	cbnz	r6, 32e <CONFIG_PM_PARTITION_SIZE_PROVISION+0xae>
			if (BUF_OFFSET + 1 > len) {
     328:	2100      	movs	r1, #0
     32a:	4608      	mov	r0, r1
     32c:	e77c      	b.n	228 <__data_size+0x4c>
			uint8_t pos = str_ptr_pos[i] & STR_POS_MASK;
     32e:	e9c6 e000 	strd	lr, r0, [r6]
			if (BUF_OFFSET + 1 > len) {
     332:	e7f9      	b.n	328 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xa8>
     334:	fab3 f783 	clz	r7, r3
			*buf++ = pos;
     338:	b98f      	cbnz	r7, 35e <CONFIG_PM_PARTITION_SIZE_PROVISION+0xde>
		for (i = 0; i < s_idx; i++) {
     33a:	4283      	cmp	r3, r0
     33c:	d301      	bcc.n	342 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xc2>
		if (s_ro_cnt && str_ptr_pos[i] & STR_POS_RO_FLAG) {
     33e:	4572      	cmp	r2, lr
     340:	d808      	bhi.n	354 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xd4>
     342:	ebbe 0402 	subs.w	r4, lr, r2
     346:	eb60 0303 	sbc.w	r3, r0, r3
     34a:	2001      	movs	r0, #1
		if (rws_pos_en) {
     34c:	469c      	mov	ip, r3
     34e:	b91e      	cbnz	r6, 358 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xd8>
			*buf++ = str_ptr_arg[i];
     350:	2100      	movs	r1, #0
     352:	e769      	b.n	228 <__data_size+0x4c>
     354:	4638      	mov	r0, r7
     356:	e7fa      	b.n	34e <CONFIG_PM_PARTITION_SIZE_PROVISION+0xce>
			size = 0;
     358:	e9c6 4c00 	strd	r4, ip, [r6]
		if (BUF_OFFSET + 1 + size > len) {
     35c:	e7f8      	b.n	350 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xd0>
     35e:	f1c7 0c20 	rsb	ip, r7, #32
     362:	40bb      	lsls	r3, r7
     364:	fa0e f507 	lsl.w	r5, lr, r7
		*buf++ = str_ptr_pos[i];
     368:	fa22 f40c 	lsr.w	r4, r2, ip
     36c:	fa2e f10c 	lsr.w	r1, lr, ip
		memcpy(buf, s, size);
     370:	40ba      	lsls	r2, r7
     372:	431c      	orrs	r4, r3
     374:	fa20 f30c 	lsr.w	r3, r0, ip
		buf += size;
     378:	40b8      	lsls	r0, r7
     37a:	ea4f 4914 	mov.w	r9, r4, lsr #16
	for (i = 0; i < s_idx; i++) {
     37e:	4301      	orrs	r1, r0
     380:	fa1f fe84 	uxth.w	lr, r4
     384:	fbb3 f8f9 	udiv	r8, r3, r9
			s = *(char **)(buf0 + str_ptr_pos[i] * sizeof(int));
     388:	fb09 3018 	mls	r0, r9, r8, r3
     38c:	0c0b      	lsrs	r3, r1, #16
     38e:	fb08 fa0e 	mul.w	sl, r8, lr
			size = strlen(s) + 1;
     392:	ea43 4300 	orr.w	r3, r3, r0, lsl #16
			*(char **)(buf0 + str_ptr_pos[i] * sizeof(int)) = NULL;
     396:	459a      	cmp	sl, r3
			size = strlen(s) + 1;
     398:	d940      	bls.n	41c <CONFIG_FLASH_SIZE+0x1c>
     39a:	18e3      	adds	r3, r4, r3
     39c:	f108 30ff 	add.w	r0, r8, #4294967295
		return -EFAULT;
     3a0:	d204      	bcs.n	3ac <CONFIG_PM_PARTITION_SIZE_PROVISION+0x12c>
     3a2:	459a      	cmp	sl, r3
     3a4:	d902      	bls.n	3ac <CONFIG_PM_PARTITION_SIZE_PROVISION+0x12c>
     3a6:	f1a8 0002 	sub.w	r0, r8, #2
     3aa:	4423      	add	r3, r4
     3ac:	eba3 030a 	sub.w	r3, r3, sl
     3b0:	b289      	uxth	r1, r1
     3b2:	fbb3 f8f9 	udiv	r8, r3, r9
     3b6:	fb09 3318 	mls	r3, r9, r8, r3
     3ba:	fb08 fe0e 	mul.w	lr, r8, lr
     3be:	ea41 4103 	orr.w	r1, r1, r3, lsl #16
     3c2:	458e      	cmp	lr, r1
     3c4:	d92c      	bls.n	420 <CONFIG_FLASH_SIZE+0x20>
     3c6:	1861      	adds	r1, r4, r1
     3c8:	f108 33ff 	add.w	r3, r8, #4294967295
     3cc:	d204      	bcs.n	3d8 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x158>
     3ce:	458e      	cmp	lr, r1
     3d0:	d902      	bls.n	3d8 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x158>
     3d2:	f1a8 0302 	sub.w	r3, r8, #2
     3d6:	4421      	add	r1, r4
     3d8:	ea43 4000 	orr.w	r0, r3, r0, lsl #16
     3dc:	eba1 010e 	sub.w	r1, r1, lr
     3e0:	fba0 9802 	umull	r9, r8, r0, r2
     3e4:	4541      	cmp	r1, r8
     3e6:	46ce      	mov	lr, r9
     3e8:	4643      	mov	r3, r8
     3ea:	d302      	bcc.n	3f2 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x172>
     3ec:	d106      	bne.n	3fc <CONFIG_PM_PARTITION_SIZE_PROVISION+0x17c>
     3ee:	454d      	cmp	r5, r9
     3f0:	d204      	bcs.n	3fc <CONFIG_PM_PARTITION_SIZE_PROVISION+0x17c>
     3f2:	3801      	subs	r0, #1
     3f4:	ebb9 0e02 	subs.w	lr, r9, r2
     3f8:	eb68 0304 	sbc.w	r3, r8, r4
     3fc:	2e00      	cmp	r6, #0
     3fe:	d0a7      	beq.n	350 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xd0>
     400:	ebb5 020e 	subs.w	r2, r5, lr
     404:	eb61 0103 	sbc.w	r1, r1, r3
     408:	fa01 fc0c 	lsl.w	ip, r1, ip
     40c:	fa22 f307 	lsr.w	r3, r2, r7
     410:	40f9      	lsrs	r1, r7
     412:	ea4c 0303 	orr.w	r3, ip, r3
     416:	e9c6 3100 	strd	r3, r1, [r6]
     41a:	e799      	b.n	350 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xd0>
     41c:	4640      	mov	r0, r8
     41e:	e7c5      	b.n	3ac <CONFIG_PM_PARTITION_SIZE_PROVISION+0x12c>
     420:	4643      	mov	r3, r8
     422:	e7d9      	b.n	3d8 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x158>

00000424 <main>:
#define SPI_FLASH_TEST_REGION_OFFSET 0xff000
#endif
#define SPI_FLASH_SECTOR_SIZE        4096

void main(void)
{
     424:	e92d 47ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
	uint8_t buf[sizeof(expected)];
	const struct device *flash_dev;
	int rc;

	flash_dev = DEVICE_DT_GET(DT_ALIAS(spi_flash0));
	printk("flash_dev->name: %s\n", flash_dev->name);
     428:	4c44      	ldr	r4, [pc, #272]	; (53c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x54>)
	const uint8_t expected[] = { 0x55, 0xaa, 0x66, 0x99 };
     42a:	4b45      	ldr	r3, [pc, #276]	; (540 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x58>)
	printk("flash_dev->name: %s\n", flash_dev->name);
     42c:	6825      	ldr	r5, [r4, #0]
     42e:	4845      	ldr	r0, [pc, #276]	; (544 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x5c>)
     430:	4629      	mov	r1, r5
	const uint8_t expected[] = { 0x55, 0xaa, 0x66, 0x99 };
     432:	9302      	str	r3, [sp, #8]
	printk("flash_dev->name: %s\n", flash_dev->name);
     434:	f005 fcd9 	bl	5dea <printk>
	printk("flash_dev->config: %p\n", flash_dev->config);
     438:	6861      	ldr	r1, [r4, #4]
     43a:	4843      	ldr	r0, [pc, #268]	; (548 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x60>)
     43c:	f005 fcd5 	bl	5dea <printk>
	printk("flash_dev->driver_api: %p\n", flash_dev->api);
     440:	68a1      	ldr	r1, [r4, #8]
     442:	4842      	ldr	r0, [pc, #264]	; (54c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x64>)
     444:	f005 fcd1 	bl	5dea <printk>
	printk("flash_dev->status: %d\n", flash_dev->state);
     448:	68e1      	ldr	r1, [r4, #12]
     44a:	4841      	ldr	r0, [pc, #260]	; (550 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x68>)
     44c:	f005 fccd 	bl	5dea <printk>
	printk("flash_dev->data: %p\n", flash_dev->data);
     450:	6921      	ldr	r1, [r4, #16]
     452:	4840      	ldr	r0, [pc, #256]	; (554 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x6c>)
     454:	f005 fcc9 	bl	5dea <printk>
 */
__syscall bool device_is_ready(const struct device *dev);

static inline bool z_impl_device_is_ready(const struct device *dev)
{
	return z_device_is_ready(dev);
     458:	4620      	mov	r0, r4
     45a:	f004 fb81 	bl	4b60 <z_device_is_ready>

	if (!device_is_ready(flash_dev)) {
		printk("%s: device not ready.\n", flash_dev->name);
     45e:	4629      	mov	r1, r5
	if (!device_is_ready(flash_dev)) {
     460:	b928      	cbnz	r0, 46e <main+0x4a>
		printk("%s: device not ready.\n", flash_dev->name);
     462:	483d      	ldr	r0, [pc, #244]	; (558 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x70>)
     464:	f005 fcc1 	bl	5dea <printk>
			       *wp, *rp, (*rp == *wp) ? "match" : "MISMATCH");
			++rp;
			++wp;
		}
	}
}
     468:	b004      	add	sp, #16
     46a:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
	printf("\n%s SPI flash testing\n", flash_dev->name);
     46e:	483b      	ldr	r0, [pc, #236]	; (55c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x74>)
     470:	f001 fcca 	bl	1e08 <printf>
	printf("==========================\n");
     474:	483a      	ldr	r0, [pc, #232]	; (560 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x78>)
     476:	f001 fcc7 	bl	1e08 <printf>
	printf("\nTest 1: Flash erase\n");
     47a:	483a      	ldr	r0, [pc, #232]	; (564 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x7c>)
     47c:	f001 fcc4 	bl	1e08 <printf>
{
	const struct flash_driver_api *api =
		(const struct flash_driver_api *)dev->api;
	int rc;

	rc = api->erase(dev, offset, size);
     480:	68a3      	ldr	r3, [r4, #8]
     482:	f44f 217f 	mov.w	r1, #1044480	; 0xff000
     486:	f44f 5280 	mov.w	r2, #4096	; 0x1000
     48a:	4620      	mov	r0, r4
     48c:	689b      	ldr	r3, [r3, #8]
     48e:	4798      	blx	r3
	if (rc != 0) {
     490:	4601      	mov	r1, r0
     492:	b1b8      	cbz	r0, 4c4 <main+0xa0>
		printf("Flash erase failed! %d\n", rc);
     494:	4834      	ldr	r0, [pc, #208]	; (568 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x80>)
     496:	f001 fcb7 	bl	1e08 <printf>
	printf("\nTest 2: Flash write\n");
     49a:	4834      	ldr	r0, [pc, #208]	; (56c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x84>)
     49c:	f001 fcb4 	bl	1e08 <printf>
	printf("Attempting to write %zu bytes\n", len);
     4a0:	2104      	movs	r1, #4
     4a2:	4833      	ldr	r0, [pc, #204]	; (570 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x88>)
     4a4:	f001 fcb0 	bl	1e08 <printf>
	rc = api->write(dev, offset, data, len);
     4a8:	68a4      	ldr	r4, [r4, #8]
     4aa:	f44f 217f 	mov.w	r1, #1044480	; 0xff000
     4ae:	2304      	movs	r3, #4
     4b0:	6865      	ldr	r5, [r4, #4]
     4b2:	4822      	ldr	r0, [pc, #136]	; (53c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x54>)
     4b4:	aa02      	add	r2, sp, #8
     4b6:	47a8      	blx	r5
	if (rc != 0) {
     4b8:	4601      	mov	r1, r0
     4ba:	b138      	cbz	r0, 4cc <main+0xa8>
		printf("Flash write failed! %d\n", rc);
     4bc:	482d      	ldr	r0, [pc, #180]	; (574 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x8c>)
		printf("Flash read failed! %d\n", rc);
     4be:	f001 fca3 	bl	1e08 <printf>
		return;
     4c2:	e7d1      	b.n	468 <main+0x44>
		printf("Flash erase succeeded!\n");
     4c4:	482c      	ldr	r0, [pc, #176]	; (578 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x90>)
     4c6:	f001 fc9f 	bl	1e08 <printf>
     4ca:	e7e6      	b.n	49a <main+0x76>
	memset(buf, 0, len);
     4cc:	ad03      	add	r5, sp, #12
     4ce:	2204      	movs	r2, #4
     4d0:	4628      	mov	r0, r5
     4d2:	f005 fe5f 	bl	6194 <memset>
	return api->read(dev, offset, data, len);
     4d6:	f44f 217f 	mov.w	r1, #1044480	; 0xff000
     4da:	2304      	movs	r3, #4
     4dc:	462a      	mov	r2, r5
     4de:	6824      	ldr	r4, [r4, #0]
     4e0:	4816      	ldr	r0, [pc, #88]	; (53c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x54>)
     4e2:	47a0      	blx	r4
	if (rc != 0) {
     4e4:	4601      	mov	r1, r0
     4e6:	b108      	cbz	r0, 4ec <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x4>
		printf("Flash read failed! %d\n", rc);
     4e8:	4824      	ldr	r0, [pc, #144]	; (57c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x94>)
     4ea:	e7e8      	b.n	4be <main+0x9a>
	if (memcmp(expected, buf, len) == 0) {
     4ec:	2204      	movs	r2, #4
     4ee:	4629      	mov	r1, r5
     4f0:	a802      	add	r0, sp, #8
     4f2:	f005 fe1d 	bl	6130 <memcmp>
     4f6:	b918      	cbnz	r0, 500 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x18>
		printf("Data read matches data written. Good!!\n");
     4f8:	4821      	ldr	r0, [pc, #132]	; (580 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x98>)
     4fa:	f001 fc85 	bl	1e08 <printf>
     4fe:	e7b3      	b.n	468 <main+0x44>
		printf("Data read does not match data written!!\n");
     500:	4820      	ldr	r0, [pc, #128]	; (584 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x9c>)
     502:	f001 fc81 	bl	1e08 <printf>
		while (rp < rpe) {
     506:	462f      	mov	r7, r5
     508:	2605      	movs	r6, #5
			printf("%08x wrote %02x read %02x %s\n",
     50a:	f8df 807c 	ldr.w	r8, [pc, #124]	; 588 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xa0>
     50e:	f8df 907c 	ldr.w	r9, [pc, #124]	; 58c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xa4>
     512:	f8df a07c 	ldr.w	sl, [pc, #124]	; 590 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0xa8>
     516:	ac02      	add	r4, sp, #8
		while (rp < rpe) {
     518:	3e01      	subs	r6, #1
     51a:	d0a5      	beq.n	468 <main+0x44>
			       *wp, *rp, (*rp == *wp) ? "match" : "MISMATCH");
     51c:	f814 2b01 	ldrb.w	r2, [r4], #1
			       (uint32_t)(SPI_FLASH_TEST_REGION_OFFSET + (rp - buf)),
     520:	1b79      	subs	r1, r7, r5
			       *wp, *rp, (*rp == *wp) ? "match" : "MISMATCH");
     522:	f817 3b01 	ldrb.w	r3, [r7], #1
			printf("%08x wrote %02x read %02x %s\n",
     526:	f501 217f 	add.w	r1, r1, #1044480	; 0xff000
     52a:	429a      	cmp	r2, r3
     52c:	bf14      	ite	ne
     52e:	4640      	movne	r0, r8
     530:	4648      	moveq	r0, r9
     532:	9000      	str	r0, [sp, #0]
     534:	4650      	mov	r0, sl
     536:	f001 fc67 	bl	1e08 <printf>
			++wp;
     53a:	e7ed      	b.n	518 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x30>
     53c:	00006fa0 	.word	0x00006fa0
     540:	9966aa55 	.word	0x9966aa55
     544:	00007585 	.word	0x00007585
     548:	0000759a 	.word	0x0000759a
     54c:	000075b1 	.word	0x000075b1
     550:	000075cc 	.word	0x000075cc
     554:	000075e3 	.word	0x000075e3
     558:	000075f8 	.word	0x000075f8
     55c:	0000760f 	.word	0x0000760f
     560:	00007626 	.word	0x00007626
     564:	00007642 	.word	0x00007642
     568:	00007658 	.word	0x00007658
     56c:	00007688 	.word	0x00007688
     570:	0000769e 	.word	0x0000769e
     574:	000076bd 	.word	0x000076bd
     578:	00007670 	.word	0x00007670
     57c:	000076d5 	.word	0x000076d5
     580:	000076ec 	.word	0x000076ec
     584:	00007714 	.word	0x00007714
     588:	0000757c 	.word	0x0000757c
     58c:	00007576 	.word	0x00007576
     590:	0000773d 	.word	0x0000773d

00000594 <char_out>:
}

static int char_out(int c, void *ctx_p)
{
	(void) ctx_p;
	return _char_out(c);
     594:	4b01      	ldr	r3, [pc, #4]	; (59c <char_out+0x8>)
     596:	681b      	ldr	r3, [r3, #0]
     598:	4718      	bx	r3
     59a:	bf00      	nop
     59c:	20000000 	.word	0x20000000

000005a0 <__printk_hook_install>:
	_char_out = fn;
     5a0:	4b01      	ldr	r3, [pc, #4]	; (5a8 <__printk_hook_install+0x8>)
     5a2:	6018      	str	r0, [r3, #0]
}
     5a4:	4770      	bx	lr
     5a6:	bf00      	nop
     5a8:	20000000 	.word	0x20000000

000005ac <vprintk>:
}

void vprintk(const char *fmt, va_list ap)
{
     5ac:	b507      	push	{r0, r1, r2, lr}
     5ae:	460b      	mov	r3, r1
int cbvprintf(cbprintf_cb out, void *ctx, const char *format, va_list ap);
#else
static inline
int cbvprintf(cbprintf_cb out, void *ctx, const char *format, va_list ap)
{
	return z_cbvprintf_impl(out, ctx, format, ap, 0);
     5b0:	2100      	movs	r1, #0
     5b2:	4602      	mov	r2, r0
     5b4:	9100      	str	r1, [sp, #0]
     5b6:	4803      	ldr	r0, [pc, #12]	; (5c4 <vprintk+0x18>)
     5b8:	f000 f914 	bl	7e4 <z_cbvprintf_impl>

#ifdef CONFIG_PRINTK_SYNC
		k_spin_unlock(&lock, key);
#endif
	}
}
     5bc:	b003      	add	sp, #12
     5be:	f85d fb04 	ldr.w	pc, [sp], #4
     5c2:	bf00      	nop
     5c4:	00000595 	.word	0x00000595

000005c8 <process_event>:
 * regions.
 */
static void process_event(struct onoff_manager *mgr,
			  int evt,
			  k_spinlock_key_t key)
{
     5c8:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
	sys_slist_t clients;
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     5cc:	8b05      	ldrh	r5, [r0, #24]
{
     5ce:	4604      	mov	r4, r0
	__ASSERT_NO_MSG(evt != EVT_NOP);

	/* If this is a nested call record the event for processing in
	 * the top invocation.
	 */
	if (processing) {
     5d0:	0728      	lsls	r0, r5, #28
{
     5d2:	4690      	mov	r8, r2
	if (processing) {
     5d4:	d411      	bmi.n	5fa <process_event+0x32>

	sys_slist_init(&clients);
	do {
		onoff_transition_fn transit = NULL;

		if (evt == EVT_RECHECK) {
     5d6:	2902      	cmp	r1, #2
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     5d8:	f005 0507 	and.w	r5, r5, #7
		if (evt == EVT_RECHECK) {
     5dc:	f040 80cd 	bne.w	77a <process_event+0x1b2>
			evt = process_recheck(mgr);
     5e0:	4620      	mov	r0, r4
     5e2:	f005 fc19 	bl	5e18 <process_recheck>
		}

		if (evt == EVT_NOP) {
     5e6:	b178      	cbz	r0, 608 <process_event+0x40>
			break;
		}

		res = 0;
		if (evt == EVT_COMPLETE) {
     5e8:	3801      	subs	r0, #1
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     5ea:	8b21      	ldrh	r1, [r4, #24]
     5ec:	2804      	cmp	r0, #4
     5ee:	d811      	bhi.n	614 <process_event+0x4c>
     5f0:	e8df f000 	tbb	[pc, r0]
     5f4:	856d10c3 	.word	0x856d10c3
     5f8:	95          	.byte	0x95
     5f9:	00          	.byte	0x00
		if (evt == EVT_COMPLETE) {
     5fa:	2901      	cmp	r1, #1
			mgr->flags |= ONOFF_FLAG_COMPLETE;
     5fc:	bf0c      	ite	eq
     5fe:	f045 0510 	orreq.w	r5, r5, #16
			mgr->flags |= ONOFF_FLAG_RECHECK;
     602:	f045 0520 	orrne.w	r5, r5, #32
     606:	8325      	strh	r5, [r4, #24]
	__asm__ volatile(
		"cpsie i;"
		"isb"
		: : : "memory");
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	__asm__ volatile(
     608:	f388 8811 	msr	BASEPRI, r8
     60c:	f3bf 8f6f 	isb	sy
		state = mgr->flags & ONOFF_STATE_MASK;
	} while (evt != EVT_NOP);

out:
	k_spin_unlock(&mgr->lock, key);
}
     610:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     614:	f001 0a07 	and.w	sl, r1, #7
				   && !sys_slist_is_empty(&mgr->monitors);
     618:	45aa      	cmp	sl, r5
     61a:	f000 80a6 	beq.w	76a <process_event+0x1a2>
	 * a memory barrier when used like this, and we don't have a
	 * Zephyr framework for that.
	 */
	atomic_clear(&l->locked);
#endif
	arch_irq_unlock(key.key);
     61e:	2700      	movs	r7, #0
     620:	46b9      	mov	r9, r7
     622:	463e      	mov	r6, r7
     624:	68a3      	ldr	r3, [r4, #8]
     626:	2b00      	cmp	r3, #0
     628:	f000 80bd 	beq.w	7a6 <process_event+0x1de>
			uint32_t flags = mgr->flags | ONOFF_FLAG_PROCESSING;
     62c:	f041 0108 	orr.w	r1, r1, #8
			mgr->flags = flags;
     630:	8321      	strh	r1, [r4, #24]
     632:	f388 8811 	msr	BASEPRI, r8
     636:	f3bf 8f6f 	isb	sy
 *
 * @return A pointer on the first node of the list (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_head(sys_slist_t *list)
{
	return list->head;
     63a:	68a1      	ldr	r1, [r4, #8]
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
     63c:	2900      	cmp	r1, #0
     63e:	f000 80bb 	beq.w	7b8 <process_event+0x1f0>
	return node->next;
     642:	680d      	ldr	r5, [r1, #0]
     644:	2900      	cmp	r1, #0
     646:	f000 80b7 	beq.w	7b8 <process_event+0x1f0>
		mon->callback(mgr, mon, state, res);
     64a:	4633      	mov	r3, r6
     64c:	4652      	mov	r2, sl
     64e:	4620      	mov	r0, r4
     650:	f8d1 8004 	ldr.w	r8, [r1, #4]
     654:	47c0      	blx	r8
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
     656:	2d00      	cmp	r5, #0
     658:	d076      	beq.n	748 <process_event+0x180>
     65a:	682b      	ldr	r3, [r5, #0]
     65c:	4629      	mov	r1, r5
     65e:	461d      	mov	r5, r3
     660:	e7f0      	b.n	644 <process_event+0x7c>
     662:	f001 0307 	and.w	r3, r1, #7
		   || (state == ONOFF_STATE_RESETTING)) {
     666:	1f5a      	subs	r2, r3, #5
	} else if ((state == ONOFF_STATE_TO_ON)
     668:	2a01      	cmp	r2, #1
     66a:	d81b      	bhi.n	6a4 <process_event+0xdc>
	list->head = NULL;
     66c:	2200      	movs	r2, #0
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     66e:	f021 0107 	bic.w	r1, r1, #7
		if (state == ONOFF_STATE_TO_ON) {
     672:	2b06      	cmp	r3, #6
		*clients = mgr->clients;
     674:	6827      	ldr	r7, [r4, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     676:	b289      	uxth	r1, r1
	list->tail = NULL;
     678:	e9c4 2200 	strd	r2, r2, [r4]
		if (state == ONOFF_STATE_TO_ON) {
     67c:	d109      	bne.n	692 <process_event+0xca>
     67e:	463b      	mov	r3, r7
     680:	e003      	b.n	68a <process_event+0xc2>
				mgr->refs += 1U;
     682:	8b62      	ldrh	r2, [r4, #26]
     684:	3201      	adds	r2, #1
     686:	8362      	strh	r2, [r4, #26]
	return node->next;
     688:	681b      	ldr	r3, [r3, #0]
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
     68a:	2b00      	cmp	r3, #0
     68c:	d1f9      	bne.n	682 <process_event+0xba>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     68e:	f041 0102 	orr.w	r1, r1, #2
		if (process_recheck(mgr) != EVT_NOP) {
     692:	4620      	mov	r0, r4
	mgr->flags = (state & ONOFF_STATE_MASK)
     694:	8321      	strh	r1, [r4, #24]
		if (process_recheck(mgr) != EVT_NOP) {
     696:	f005 fbbf 	bl	5e18 <process_recheck>
     69a:	2800      	cmp	r0, #0
     69c:	d07b      	beq.n	796 <process_event+0x1ce>
			mgr->flags |= ONOFF_FLAG_RECHECK;
     69e:	f041 0120 	orr.w	r1, r1, #32
     6a2:	e077      	b.n	794 <process_event+0x1cc>
	} else if (state == ONOFF_STATE_TO_OFF) {
     6a4:	2b04      	cmp	r3, #4
     6a6:	d10a      	bne.n	6be <process_event+0xf6>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     6a8:	f021 0107 	bic.w	r1, r1, #7
     6ac:	b289      	uxth	r1, r1
		if (process_recheck(mgr) != EVT_NOP) {
     6ae:	4620      	mov	r0, r4
	mgr->flags = (state & ONOFF_STATE_MASK)
     6b0:	8321      	strh	r1, [r4, #24]
		if (process_recheck(mgr) != EVT_NOP) {
     6b2:	f005 fbb1 	bl	5e18 <process_recheck>
     6b6:	b110      	cbz	r0, 6be <process_event+0xf6>
			mgr->flags |= ONOFF_FLAG_RECHECK;
     6b8:	f041 0120 	orr.w	r1, r1, #32
     6bc:	8321      	strh	r1, [r4, #24]
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     6be:	8b21      	ldrh	r1, [r4, #24]
     6c0:	f001 0a07 	and.w	sl, r1, #7
				   && !sys_slist_is_empty(&mgr->monitors);
     6c4:	45aa      	cmp	sl, r5
     6c6:	d050      	beq.n	76a <process_event+0x1a2>
     6c8:	2700      	movs	r7, #0
		onoff_transition_fn transit = NULL;
     6ca:	46b9      	mov	r9, r7
     6cc:	e7aa      	b.n	624 <process_event+0x5c>
			transit = mgr->transitions->start;
     6ce:	6923      	ldr	r3, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     6d0:	f021 0107 	bic.w	r1, r1, #7
     6d4:	f041 0106 	orr.w	r1, r1, #6
				   && !sys_slist_is_empty(&mgr->monitors);
     6d8:	2d06      	cmp	r5, #6
			transit = mgr->transitions->start;
     6da:	f8d3 9000 	ldr.w	r9, [r3]
	mgr->flags = (state & ONOFF_STATE_MASK)
     6de:	8321      	strh	r1, [r4, #24]
				   && !sys_slist_is_empty(&mgr->monitors);
     6e0:	d12d      	bne.n	73e <process_event+0x176>
		    || (transit != NULL)) {
     6e2:	f1b9 0f00 	cmp.w	r9, #0
     6e6:	d040      	beq.n	76a <process_event+0x1a2>
			uint32_t flags = mgr->flags | ONOFF_FLAG_PROCESSING;
     6e8:	f041 0108 	orr.w	r1, r1, #8
			mgr->flags = flags;
     6ec:	8321      	strh	r1, [r4, #24]
     6ee:	f388 8811 	msr	BASEPRI, r8
     6f2:	f3bf 8f6f 	isb	sy
				transit(mgr, transition_complete);
     6f6:	4620      	mov	r0, r4
     6f8:	4939      	ldr	r1, [pc, #228]	; (7e0 <process_event+0x218>)
     6fa:	47c8      	blx	r9
     6fc:	e029      	b.n	752 <process_event+0x18a>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     6fe:	f021 0107 	bic.w	r1, r1, #7
			transit = mgr->transitions->stop;
     702:	6923      	ldr	r3, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     704:	f041 0104 	orr.w	r1, r1, #4
     708:	b289      	uxth	r1, r1
				   && !sys_slist_is_empty(&mgr->monitors);
     70a:	2d04      	cmp	r5, #4
			transit = mgr->transitions->stop;
     70c:	f8d3 9004 	ldr.w	r9, [r3, #4]
	mgr->flags = (state & ONOFF_STATE_MASK)
     710:	8321      	strh	r1, [r4, #24]
				   && !sys_slist_is_empty(&mgr->monitors);
     712:	d0e6      	beq.n	6e2 <process_event+0x11a>
     714:	2700      	movs	r7, #0
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     716:	f04f 0a04 	mov.w	sl, #4
		res = 0;
     71a:	463e      	mov	r6, r7
     71c:	e782      	b.n	624 <process_event+0x5c>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     71e:	f021 0107 	bic.w	r1, r1, #7
			transit = mgr->transitions->reset;
     722:	6923      	ldr	r3, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     724:	f041 0105 	orr.w	r1, r1, #5
     728:	b289      	uxth	r1, r1
				   && !sys_slist_is_empty(&mgr->monitors);
     72a:	2d05      	cmp	r5, #5
			transit = mgr->transitions->reset;
     72c:	f8d3 9008 	ldr.w	r9, [r3, #8]
	mgr->flags = (state & ONOFF_STATE_MASK)
     730:	8321      	strh	r1, [r4, #24]
				   && !sys_slist_is_empty(&mgr->monitors);
     732:	d0d6      	beq.n	6e2 <process_event+0x11a>
     734:	2700      	movs	r7, #0
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     736:	f04f 0a05 	mov.w	sl, #5
		res = 0;
     73a:	463e      	mov	r6, r7
     73c:	e772      	b.n	624 <process_event+0x5c>
				   && !sys_slist_is_empty(&mgr->monitors);
     73e:	2700      	movs	r7, #0
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     740:	f04f 0a06 	mov.w	sl, #6
		res = 0;
     744:	463e      	mov	r6, r7
     746:	e76d      	b.n	624 <process_event+0x5c>
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
     748:	462b      	mov	r3, r5
     74a:	e787      	b.n	65c <process_event+0x94>
			if (transit != NULL) {
     74c:	f1b9 0f00 	cmp.w	r9, #0
     750:	d1d1      	bne.n	6f6 <process_event+0x12e>
	__asm__ volatile(
     752:	f04f 0320 	mov.w	r3, #32
     756:	f3ef 8811 	mrs	r8, BASEPRI
     75a:	f383 8812 	msr	BASEPRI_MAX, r3
     75e:	f3bf 8f6f 	isb	sy
			mgr->flags &= ~ONOFF_FLAG_PROCESSING;
     762:	8b23      	ldrh	r3, [r4, #24]
     764:	f023 0308 	bic.w	r3, r3, #8
     768:	8323      	strh	r3, [r4, #24]
		if ((mgr->flags & ONOFF_FLAG_COMPLETE) != 0) {
     76a:	8b25      	ldrh	r5, [r4, #24]
     76c:	06ea      	lsls	r2, r5, #27
     76e:	d52e      	bpl.n	7ce <process_event+0x206>
			mgr->flags &= ~ONOFF_FLAG_COMPLETE;
     770:	f025 0310 	bic.w	r3, r5, #16
     774:	8323      	strh	r3, [r4, #24]
		state = mgr->flags & ONOFF_STATE_MASK;
     776:	f005 0507 	and.w	r5, r5, #7
			res = mgr->last_res;
     77a:	6966      	ldr	r6, [r4, #20]
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     77c:	8b21      	ldrh	r1, [r4, #24]
	if (res < 0) {
     77e:	2e00      	cmp	r6, #0
     780:	f6bf af6f 	bge.w	662 <process_event+0x9a>
	list->head = NULL;
     784:	2300      	movs	r3, #0
		*clients = mgr->clients;
     786:	6827      	ldr	r7, [r4, #0]
	list->tail = NULL;
     788:	e9c4 3300 	strd	r3, r3, [r4]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     78c:	f021 0107 	bic.w	r1, r1, #7
     790:	f041 0101 	orr.w	r1, r1, #1
			mgr->flags |= ONOFF_FLAG_RECHECK;
     794:	8321      	strh	r1, [r4, #24]
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     796:	8b21      	ldrh	r1, [r4, #24]
     798:	f04f 0900 	mov.w	r9, #0
     79c:	f001 0a07 	and.w	sl, r1, #7
				   && !sys_slist_is_empty(&mgr->monitors);
     7a0:	45aa      	cmp	sl, r5
     7a2:	f47f af3f 	bne.w	624 <process_event+0x5c>
		    || !sys_slist_is_empty(&clients)
     7a6:	2f00      	cmp	r7, #0
     7a8:	d09b      	beq.n	6e2 <process_event+0x11a>
			uint32_t flags = mgr->flags | ONOFF_FLAG_PROCESSING;
     7aa:	f041 0108 	orr.w	r1, r1, #8
			mgr->flags = flags;
     7ae:	8321      	strh	r1, [r4, #24]
	__asm__ volatile(
     7b0:	f388 8811 	msr	BASEPRI, r8
     7b4:	f3bf 8f6f 	isb	sy
			if (!sys_slist_is_empty(&clients)) {
     7b8:	2f00      	cmp	r7, #0
     7ba:	d0c7      	beq.n	74c <process_event+0x184>
	return node->next;
     7bc:	683d      	ldr	r5, [r7, #0]
		notify_one(mgr, cli, state, res);
     7be:	4639      	mov	r1, r7
     7c0:	4633      	mov	r3, r6
     7c2:	4652      	mov	r2, sl
     7c4:	4620      	mov	r0, r4
     7c6:	f005 fb53 	bl	5e70 <notify_one>
	list->head = node;
     7ca:	462f      	mov	r7, r5
	while (!sys_slist_is_empty(list)) {
     7cc:	e7f4      	b.n	7b8 <process_event+0x1f0>
		} else if ((mgr->flags & ONOFF_FLAG_RECHECK) != 0) {
     7ce:	06ab      	lsls	r3, r5, #26
     7d0:	f57f af1a 	bpl.w	608 <process_event+0x40>
			mgr->flags &= ~ONOFF_FLAG_RECHECK;
     7d4:	f025 0320 	bic.w	r3, r5, #32
			mgr->flags &= ~ONOFF_FLAG_COMPLETE;
     7d8:	8323      	strh	r3, [r4, #24]
		state = mgr->flags & ONOFF_STATE_MASK;
     7da:	f005 0507 	and.w	r5, r5, #7
		if (evt == EVT_RECHECK) {
     7de:	e6ff      	b.n	5e0 <process_event+0x18>
     7e0:	00005e9d 	.word	0x00005e9d

000007e4 <z_cbvprintf_impl>:
	return (int)count;
}

int z_cbvprintf_impl(cbprintf_cb out, void *ctx, const char *fp,
		     va_list ap, uint32_t flags)
{
     7e4:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     7e8:	4681      	mov	r9, r0
     7ea:	468b      	mov	fp, r1
     7ec:	4617      	mov	r7, r2
     7ee:	461c      	mov	r4, r3
	char buf[CONVERTED_BUFLEN];
	size_t count = 0;
     7f0:	2500      	movs	r5, #0
{
     7f2:	b095      	sub	sp, #84	; 0x54
		return rc; \
	} \
	count += rc; \
} while (false)

	while (*fp != 0) {
     7f4:	7838      	ldrb	r0, [r7, #0]
     7f6:	b908      	cbnz	r0, 7fc <z_cbvprintf_impl+0x18>
			OUTC(' ');
			--width;
		}
	}

	return count;
     7f8:	4628      	mov	r0, r5
     7fa:	e357      	b.n	eac <CONFIG_ISR_STACK_SIZE+0x6ac>
			OUTC(*fp++);
     7fc:	1c7b      	adds	r3, r7, #1
		if (*fp != '%') {
     7fe:	2825      	cmp	r0, #37	; 0x25
			OUTC(*fp++);
     800:	9303      	str	r3, [sp, #12]
		if (*fp != '%') {
     802:	d006      	beq.n	812 <CONFIG_ISR_STACK_SIZE+0x12>
			OUTC('%');
     804:	4659      	mov	r1, fp
     806:	47c8      	blx	r9
     808:	2800      	cmp	r0, #0
     80a:	f2c0 834f 	blt.w	eac <CONFIG_ISR_STACK_SIZE+0x6ac>
     80e:	3501      	adds	r5, #1
		if (bps == NULL) {
     810:	e1fb      	b.n	c0a <CONFIG_ISR_STACK_SIZE+0x40a>
		} state = {
     812:	2218      	movs	r2, #24
     814:	2100      	movs	r1, #0
     816:	a80e      	add	r0, sp, #56	; 0x38
     818:	f005 fcbc 	bl	6194 <memset>
	if (*sp == '%') {
     81c:	787b      	ldrb	r3, [r7, #1]
     81e:	2b25      	cmp	r3, #37	; 0x25
     820:	d07d      	beq.n	91e <CONFIG_ISR_STACK_SIZE+0x11e>
     822:	2300      	movs	r3, #0
     824:	4698      	mov	r8, r3
     826:	469e      	mov	lr, r3
     828:	469c      	mov	ip, r3
     82a:	461e      	mov	r6, r3
     82c:	1c78      	adds	r0, r7, #1
     82e:	4601      	mov	r1, r0
		switch (*sp) {
     830:	f810 2b01 	ldrb.w	r2, [r0], #1
     834:	2a2b      	cmp	r2, #43	; 0x2b
     836:	f000 80a1 	beq.w	97c <CONFIG_ISR_STACK_SIZE+0x17c>
     83a:	f200 8098 	bhi.w	96e <CONFIG_ISR_STACK_SIZE+0x16e>
     83e:	2a20      	cmp	r2, #32
     840:	f000 809f 	beq.w	982 <CONFIG_ISR_STACK_SIZE+0x182>
     844:	2a23      	cmp	r2, #35	; 0x23
     846:	f000 809f 	beq.w	988 <CONFIG_ISR_STACK_SIZE+0x188>
     84a:	b12b      	cbz	r3, 858 <CONFIG_ISR_STACK_SIZE+0x58>
     84c:	f89d 3040 	ldrb.w	r3, [sp, #64]	; 0x40
     850:	f043 0340 	orr.w	r3, r3, #64	; 0x40
     854:	f88d 3040 	strb.w	r3, [sp, #64]	; 0x40
     858:	f1b8 0f00 	cmp.w	r8, #0
     85c:	d005      	beq.n	86a <CONFIG_ISR_STACK_SIZE+0x6a>
     85e:	f89d 3040 	ldrb.w	r3, [sp, #64]	; 0x40
     862:	f043 0320 	orr.w	r3, r3, #32
     866:	f88d 3040 	strb.w	r3, [sp, #64]	; 0x40
     86a:	f1be 0f00 	cmp.w	lr, #0
     86e:	d005      	beq.n	87c <CONFIG_ISR_STACK_SIZE+0x7c>
     870:	f89d 3040 	ldrb.w	r3, [sp, #64]	; 0x40
     874:	f043 0310 	orr.w	r3, r3, #16
     878:	f88d 3040 	strb.w	r3, [sp, #64]	; 0x40
     87c:	f1bc 0f00 	cmp.w	ip, #0
     880:	d005      	beq.n	88e <CONFIG_ISR_STACK_SIZE+0x8e>
     882:	f89d 3040 	ldrb.w	r3, [sp, #64]	; 0x40
     886:	f043 0308 	orr.w	r3, r3, #8
     88a:	f88d 3040 	strb.w	r3, [sp, #64]	; 0x40
     88e:	b12e      	cbz	r6, 89c <CONFIG_ISR_STACK_SIZE+0x9c>
     890:	f89d 3040 	ldrb.w	r3, [sp, #64]	; 0x40
     894:	f043 0304 	orr.w	r3, r3, #4
     898:	f88d 3040 	strb.w	r3, [sp, #64]	; 0x40
	if (conv->flag_zero && conv->flag_dash) {
     89c:	f89d 3040 	ldrb.w	r3, [sp, #64]	; 0x40
     8a0:	f003 0044 	and.w	r0, r3, #68	; 0x44
     8a4:	2844      	cmp	r0, #68	; 0x44
     8a6:	d103      	bne.n	8b0 <CONFIG_ISR_STACK_SIZE+0xb0>
		conv->flag_zero = false;
     8a8:	f36f 1386 	bfc	r3, #6, #1
     8ac:	f88d 3040 	strb.w	r3, [sp, #64]	; 0x40
	conv->width_present = true;
     8b0:	f89d 3040 	ldrb.w	r3, [sp, #64]	; 0x40
	if (*sp == '*') {
     8b4:	2a2a      	cmp	r2, #42	; 0x2a
	conv->width_present = true;
     8b6:	f043 0380 	orr.w	r3, r3, #128	; 0x80
     8ba:	f88d 3040 	strb.w	r3, [sp, #64]	; 0x40
	if (*sp == '*') {
     8be:	d17f      	bne.n	9c0 <CONFIG_ISR_STACK_SIZE+0x1c0>
		conv->width_star = true;
     8c0:	f89d 2041 	ldrb.w	r2, [sp, #65]	; 0x41
		return ++sp;
     8c4:	1c4b      	adds	r3, r1, #1
		conv->width_star = true;
     8c6:	f042 0201 	orr.w	r2, r2, #1
     8ca:	f88d 2041 	strb.w	r2, [sp, #65]	; 0x41
	conv->prec_present = (*sp == '.');
     8ce:	781a      	ldrb	r2, [r3, #0]
     8d0:	2a2e      	cmp	r2, #46	; 0x2e
     8d2:	bf0c      	ite	eq
     8d4:	2101      	moveq	r1, #1
     8d6:	2100      	movne	r1, #0
     8d8:	f89d 2041 	ldrb.w	r2, [sp, #65]	; 0x41
     8dc:	f361 0241 	bfi	r2, r1, #1, #1
     8e0:	f88d 2041 	strb.w	r2, [sp, #65]	; 0x41
	if (!conv->prec_present) {
     8e4:	d178      	bne.n	9d8 <CONFIG_ISR_STACK_SIZE+0x1d8>
	if (*sp == '*') {
     8e6:	785a      	ldrb	r2, [r3, #1]
     8e8:	2a2a      	cmp	r2, #42	; 0x2a
     8ea:	d06e      	beq.n	9ca <CONFIG_ISR_STACK_SIZE+0x1ca>
	size_t val = 0;
     8ec:	2200      	movs	r2, #0
		val = 10U * val + *sp++ - '0';
     8ee:	f04f 0c0a 	mov.w	ip, #10
	++sp;
     8f2:	3301      	adds	r3, #1
			(((unsigned)c) <= (unsigned)'~'));
}

static inline int isdigit(int a)
{
	return (int)(((unsigned)(a)-(unsigned)'0') < 10U);
     8f4:	4619      	mov	r1, r3
     8f6:	f811 0b01 	ldrb.w	r0, [r1], #1
     8fa:	f1a0 0630 	sub.w	r6, r0, #48	; 0x30
	while (isdigit((int)(unsigned char)*sp)) {
     8fe:	2e09      	cmp	r6, #9
     900:	f240 8095 	bls.w	a2e <CONFIG_ISR_STACK_SIZE+0x22e>
	conv->unsupported |= ((conv->prec_value < 0)
     904:	f89d 1040 	ldrb.w	r1, [sp, #64]	; 0x40
	conv->prec_value = prec;
     908:	9212      	str	r2, [sp, #72]	; 0x48
	conv->unsupported |= ((conv->prec_value < 0)
     90a:	f3c1 0040 	ubfx	r0, r1, #1, #1
     90e:	ea40 70d2 	orr.w	r0, r0, r2, lsr #31
     912:	460a      	mov	r2, r1
     914:	f360 0241 	bfi	r2, r0, #1, #1
     918:	f88d 2040 	strb.w	r2, [sp, #64]	; 0x40
	return sp;
     91c:	e05c      	b.n	9d8 <CONFIG_ISR_STACK_SIZE+0x1d8>
		conv->specifier = *sp++;
     91e:	1cba      	adds	r2, r7, #2
     920:	9203      	str	r2, [sp, #12]
     922:	f88d 3043 	strb.w	r3, [sp, #67]	; 0x43
		if (conv->width_star) {
     926:	f89d 3041 	ldrb.w	r3, [sp, #65]	; 0x41
     92a:	07da      	lsls	r2, r3, #31
     92c:	f140 812e 	bpl.w	b8c <CONFIG_ISR_STACK_SIZE+0x38c>
			width = va_arg(ap, int);
     930:	f854 8b04 	ldr.w	r8, [r4], #4
			if (width < 0) {
     934:	f1b8 0f00 	cmp.w	r8, #0
     938:	da07      	bge.n	94a <CONFIG_ISR_STACK_SIZE+0x14a>
				conv->flag_dash = true;
     93a:	f89d 2040 	ldrb.w	r2, [sp, #64]	; 0x40
				width = -width;
     93e:	f1c8 0800 	rsb	r8, r8, #0
				conv->flag_dash = true;
     942:	f042 0204 	orr.w	r2, r2, #4
     946:	f88d 2040 	strb.w	r2, [sp, #64]	; 0x40
		if (conv->prec_star) {
     94a:	075e      	lsls	r6, r3, #29
     94c:	f140 8127 	bpl.w	b9e <CONFIG_ISR_STACK_SIZE+0x39e>
			int arg = va_arg(ap, int);
     950:	f854 ab04 	ldr.w	sl, [r4], #4
			if (arg < 0) {
     954:	f1ba 0f00 	cmp.w	sl, #0
     958:	f280 8126 	bge.w	ba8 <CONFIG_ISR_STACK_SIZE+0x3a8>
				conv->prec_present = false;
     95c:	f89d 3041 	ldrb.w	r3, [sp, #65]	; 0x41
     960:	f36f 0341 	bfc	r3, #1, #1
     964:	f88d 3041 	strb.w	r3, [sp, #65]	; 0x41
		int precision = -1;
     968:	f04f 3aff 	mov.w	sl, #4294967295
     96c:	e11c      	b.n	ba8 <CONFIG_ISR_STACK_SIZE+0x3a8>
		switch (*sp) {
     96e:	2a2d      	cmp	r2, #45	; 0x2d
     970:	d00d      	beq.n	98e <CONFIG_ISR_STACK_SIZE+0x18e>
     972:	2a30      	cmp	r2, #48	; 0x30
     974:	f47f af69 	bne.w	84a <CONFIG_ISR_STACK_SIZE+0x4a>
     978:	2301      	movs	r3, #1
	} while (loop);
     97a:	e758      	b.n	82e <CONFIG_ISR_STACK_SIZE+0x2e>
		switch (*sp) {
     97c:	f04f 0c01 	mov.w	ip, #1
     980:	e755      	b.n	82e <CONFIG_ISR_STACK_SIZE+0x2e>
     982:	f04f 0e01 	mov.w	lr, #1
     986:	e752      	b.n	82e <CONFIG_ISR_STACK_SIZE+0x2e>
     988:	f04f 0801 	mov.w	r8, #1
     98c:	e74f      	b.n	82e <CONFIG_ISR_STACK_SIZE+0x2e>
     98e:	2601      	movs	r6, #1
     990:	e74d      	b.n	82e <CONFIG_ISR_STACK_SIZE+0x2e>
		val = 10U * val + *sp++ - '0';
     992:	4603      	mov	r3, r0
     994:	fb0e 6202 	mla	r2, lr, r2, r6
     998:	3a30      	subs	r2, #48	; 0x30
     99a:	4618      	mov	r0, r3
     99c:	f810 6b01 	ldrb.w	r6, [r0], #1
     9a0:	f1a6 0c30 	sub.w	ip, r6, #48	; 0x30
	while (isdigit((int)(unsigned char)*sp)) {
     9a4:	f1bc 0f09 	cmp.w	ip, #9
     9a8:	d9f3      	bls.n	992 <CONFIG_ISR_STACK_SIZE+0x192>
	if (sp != wp) {
     9aa:	4299      	cmp	r1, r3
     9ac:	d08f      	beq.n	8ce <CONFIG_ISR_STACK_SIZE+0xce>
		conv->unsupported |= ((conv->width_value < 0)
     9ae:	f89d 1040 	ldrb.w	r1, [sp, #64]	; 0x40
		conv->width_value = width;
     9b2:	9211      	str	r2, [sp, #68]	; 0x44
				      || (width != (size_t)conv->width_value));
     9b4:	0fd2      	lsrs	r2, r2, #31
		conv->unsupported |= ((conv->width_value < 0)
     9b6:	f362 0141 	bfi	r1, r2, #1, #1
     9ba:	f88d 1040 	strb.w	r1, [sp, #64]	; 0x40
     9be:	e786      	b.n	8ce <CONFIG_ISR_STACK_SIZE+0xce>
     9c0:	460b      	mov	r3, r1
	size_t val = 0;
     9c2:	2200      	movs	r2, #0
		val = 10U * val + *sp++ - '0';
     9c4:	f04f 0e0a 	mov.w	lr, #10
     9c8:	e7e7      	b.n	99a <CONFIG_ISR_STACK_SIZE+0x19a>
		conv->prec_star = true;
     9ca:	f89d 2041 	ldrb.w	r2, [sp, #65]	; 0x41
		return ++sp;
     9ce:	3302      	adds	r3, #2
		conv->prec_star = true;
     9d0:	f042 0204 	orr.w	r2, r2, #4
     9d4:	f88d 2041 	strb.w	r2, [sp, #65]	; 0x41
	switch (*sp) {
     9d8:	781a      	ldrb	r2, [r3, #0]
     9da:	2a6c      	cmp	r2, #108	; 0x6c
     9dc:	d047      	beq.n	a6e <CONFIG_ISR_STACK_SIZE+0x26e>
     9de:	d82b      	bhi.n	a38 <CONFIG_ISR_STACK_SIZE+0x238>
     9e0:	2a68      	cmp	r2, #104	; 0x68
     9e2:	d031      	beq.n	a48 <CONFIG_ISR_STACK_SIZE+0x248>
     9e4:	2a6a      	cmp	r2, #106	; 0x6a
     9e6:	d04b      	beq.n	a80 <CONFIG_ISR_STACK_SIZE+0x280>
     9e8:	2a4c      	cmp	r2, #76	; 0x4c
     9ea:	d051      	beq.n	a90 <CONFIG_ISR_STACK_SIZE+0x290>
	conv->specifier = *sp++;
     9ec:	461a      	mov	r2, r3
     9ee:	f812 3b01 	ldrb.w	r3, [r2], #1
	switch (conv->specifier) {
     9f2:	2b78      	cmp	r3, #120	; 0x78
	conv->specifier = *sp++;
     9f4:	9203      	str	r2, [sp, #12]
     9f6:	f88d 3043 	strb.w	r3, [sp, #67]	; 0x43
		if (conv->length_mod == LENGTH_UPPER_L) {
     9fa:	f89d 2041 	ldrb.w	r2, [sp, #65]	; 0x41
	switch (conv->specifier) {
     9fe:	f200 80be 	bhi.w	b7e <CONFIG_ISR_STACK_SIZE+0x37e>
     a02:	2b6d      	cmp	r3, #109	; 0x6d
     a04:	d851      	bhi.n	aaa <CONFIG_ISR_STACK_SIZE+0x2aa>
     a06:	2b69      	cmp	r3, #105	; 0x69
     a08:	f200 80b9 	bhi.w	b7e <CONFIG_ISR_STACK_SIZE+0x37e>
     a0c:	2b57      	cmp	r3, #87	; 0x57
     a0e:	d867      	bhi.n	ae0 <CONFIG_ISR_STACK_SIZE+0x2e0>
     a10:	2b41      	cmp	r3, #65	; 0x41
     a12:	d003      	beq.n	a1c <CONFIG_ISR_STACK_SIZE+0x21c>
     a14:	3b45      	subs	r3, #69	; 0x45
     a16:	2b02      	cmp	r3, #2
     a18:	f200 80b1 	bhi.w	b7e <CONFIG_ISR_STACK_SIZE+0x37e>
		conv->specifier_cat = SPECIFIER_FP;
     a1c:	2204      	movs	r2, #4
     a1e:	f89d 3042 	ldrb.w	r3, [sp, #66]	; 0x42
     a22:	f362 0302 	bfi	r3, r2, #0, #3
     a26:	f88d 3042 	strb.w	r3, [sp, #66]	; 0x42
			unsupported = true;
     a2a:	2301      	movs	r3, #1
			break;
     a2c:	e073      	b.n	b16 <CONFIG_ISR_STACK_SIZE+0x316>
		val = 10U * val + *sp++ - '0';
     a2e:	fb0c 0202 	mla	r2, ip, r2, r0
     a32:	460b      	mov	r3, r1
     a34:	3a30      	subs	r2, #48	; 0x30
     a36:	e75d      	b.n	8f4 <CONFIG_ISR_STACK_SIZE+0xf4>
	switch (*sp) {
     a38:	2a74      	cmp	r2, #116	; 0x74
     a3a:	d025      	beq.n	a88 <CONFIG_ISR_STACK_SIZE+0x288>
     a3c:	2a7a      	cmp	r2, #122	; 0x7a
     a3e:	d1d5      	bne.n	9ec <CONFIG_ISR_STACK_SIZE+0x1ec>
		conv->length_mod = LENGTH_Z;
     a40:	2106      	movs	r1, #6
     a42:	f89d 2041 	ldrb.w	r2, [sp, #65]	; 0x41
     a46:	e00c      	b.n	a62 <CONFIG_ISR_STACK_SIZE+0x262>
		if (*++sp == 'h') {
     a48:	785a      	ldrb	r2, [r3, #1]
     a4a:	2a68      	cmp	r2, #104	; 0x68
     a4c:	f89d 2041 	ldrb.w	r2, [sp, #65]	; 0x41
     a50:	d106      	bne.n	a60 <CONFIG_ISR_STACK_SIZE+0x260>
			conv->length_mod = LENGTH_HH;
     a52:	2101      	movs	r1, #1
			conv->length_mod = LENGTH_LL;
     a54:	f361 02c6 	bfi	r2, r1, #3, #4
     a58:	f88d 2041 	strb.w	r2, [sp, #65]	; 0x41
			++sp;
     a5c:	3302      	adds	r3, #2
     a5e:	e7c5      	b.n	9ec <CONFIG_ISR_STACK_SIZE+0x1ec>
			conv->length_mod = LENGTH_H;
     a60:	2102      	movs	r1, #2
     a62:	f361 02c6 	bfi	r2, r1, #3, #4
     a66:	f88d 2041 	strb.w	r2, [sp, #65]	; 0x41
		if (*++sp == 'h') {
     a6a:	3301      	adds	r3, #1
     a6c:	e7be      	b.n	9ec <CONFIG_ISR_STACK_SIZE+0x1ec>
		if (*++sp == 'l') {
     a6e:	785a      	ldrb	r2, [r3, #1]
     a70:	2a6c      	cmp	r2, #108	; 0x6c
     a72:	f89d 2041 	ldrb.w	r2, [sp, #65]	; 0x41
     a76:	d101      	bne.n	a7c <CONFIG_ISR_STACK_SIZE+0x27c>
			conv->length_mod = LENGTH_LL;
     a78:	2104      	movs	r1, #4
     a7a:	e7eb      	b.n	a54 <CONFIG_ISR_STACK_SIZE+0x254>
			conv->length_mod = LENGTH_L;
     a7c:	2103      	movs	r1, #3
     a7e:	e7f0      	b.n	a62 <CONFIG_ISR_STACK_SIZE+0x262>
		conv->length_mod = LENGTH_J;
     a80:	2105      	movs	r1, #5
     a82:	f89d 2041 	ldrb.w	r2, [sp, #65]	; 0x41
     a86:	e7ec      	b.n	a62 <CONFIG_ISR_STACK_SIZE+0x262>
		conv->length_mod = LENGTH_T;
     a88:	2107      	movs	r1, #7
     a8a:	f89d 2041 	ldrb.w	r2, [sp, #65]	; 0x41
     a8e:	e7e8      	b.n	a62 <CONFIG_ISR_STACK_SIZE+0x262>
		conv->unsupported = true;
     a90:	f8bd 2040 	ldrh.w	r2, [sp, #64]	; 0x40
     a94:	f422 42f0 	bic.w	r2, r2, #30720	; 0x7800
     a98:	f022 0202 	bic.w	r2, r2, #2
     a9c:	f442 4280 	orr.w	r2, r2, #16384	; 0x4000
     aa0:	f042 0202 	orr.w	r2, r2, #2
     aa4:	f8ad 2040 	strh.w	r2, [sp, #64]	; 0x40
		break;
     aa8:	e7df      	b.n	a6a <CONFIG_ISR_STACK_SIZE+0x26a>
	switch (conv->specifier) {
     aaa:	3b6e      	subs	r3, #110	; 0x6e
     aac:	b2d9      	uxtb	r1, r3
     aae:	2301      	movs	r3, #1
     ab0:	408b      	lsls	r3, r1
     ab2:	f240 4182 	movw	r1, #1154	; 0x482
     ab6:	420b      	tst	r3, r1
     ab8:	d137      	bne.n	b2a <CONFIG_ISR_STACK_SIZE+0x32a>
     aba:	f013 0f24 	tst.w	r3, #36	; 0x24
     abe:	d151      	bne.n	b64 <CONFIG_ISR_STACK_SIZE+0x364>
     ac0:	07d8      	lsls	r0, r3, #31
     ac2:	d55c      	bpl.n	b7e <CONFIG_ISR_STACK_SIZE+0x37e>
		conv->specifier_cat = SPECIFIER_PTR;
     ac4:	2103      	movs	r1, #3
     ac6:	f89d 3042 	ldrb.w	r3, [sp, #66]	; 0x42
     aca:	f361 0302 	bfi	r3, r1, #0, #3
     ace:	f88d 3042 	strb.w	r3, [sp, #66]	; 0x42
		if (conv->length_mod == LENGTH_UPPER_L) {
     ad2:	f002 0378 	and.w	r3, r2, #120	; 0x78
     ad6:	f1a3 0140 	sub.w	r1, r3, #64	; 0x40
     ada:	424b      	negs	r3, r1
     adc:	414b      	adcs	r3, r1
     ade:	e01a      	b.n	b16 <CONFIG_ISR_STACK_SIZE+0x316>
     ae0:	2001      	movs	r0, #1
	switch (conv->specifier) {
     ae2:	f1a3 0158 	sub.w	r1, r3, #88	; 0x58
     ae6:	b2c9      	uxtb	r1, r1
     ae8:	fa00 f101 	lsl.w	r1, r0, r1
     aec:	f411 4f62 	tst.w	r1, #57856	; 0xe200
     af0:	d194      	bne.n	a1c <CONFIG_ISR_STACK_SIZE+0x21c>
     af2:	f640 0601 	movw	r6, #2049	; 0x801
     af6:	4231      	tst	r1, r6
     af8:	d11d      	bne.n	b36 <CONFIG_ISR_STACK_SIZE+0x336>
     afa:	f411 3f04 	tst.w	r1, #135168	; 0x21000
     afe:	d03e      	beq.n	b7e <CONFIG_ISR_STACK_SIZE+0x37e>
		conv->specifier_cat = SPECIFIER_SINT;
     b00:	f89d 3042 	ldrb.w	r3, [sp, #66]	; 0x42
     b04:	f360 0302 	bfi	r3, r0, #0, #3
		if (conv->length_mod == LENGTH_UPPER_L) {
     b08:	f002 0278 	and.w	r2, r2, #120	; 0x78
     b0c:	2a40      	cmp	r2, #64	; 0x40
		conv->specifier_cat = SPECIFIER_SINT;
     b0e:	f88d 3042 	strb.w	r3, [sp, #66]	; 0x42
		if (conv->length_mod == LENGTH_UPPER_L) {
     b12:	d034      	beq.n	b7e <CONFIG_ISR_STACK_SIZE+0x37e>
	bool unsupported = false;
     b14:	2300      	movs	r3, #0
	conv->unsupported |= unsupported;
     b16:	f89d 2040 	ldrb.w	r2, [sp, #64]	; 0x40
     b1a:	f3c2 0140 	ubfx	r1, r2, #1, #1
     b1e:	430b      	orrs	r3, r1
     b20:	f363 0241 	bfi	r2, r3, #1, #1
     b24:	f88d 2040 	strb.w	r2, [sp, #64]	; 0x40
	return sp;
     b28:	e6fd      	b.n	926 <CONFIG_ISR_STACK_SIZE+0x126>
		conv->specifier_cat = SPECIFIER_UINT;
     b2a:	2102      	movs	r1, #2
     b2c:	f89d 3042 	ldrb.w	r3, [sp, #66]	; 0x42
     b30:	f361 0302 	bfi	r3, r1, #0, #3
     b34:	e7e8      	b.n	b08 <CONFIG_ISR_STACK_SIZE+0x308>
     b36:	2002      	movs	r0, #2
     b38:	f89d 1042 	ldrb.w	r1, [sp, #66]	; 0x42
		if (conv->length_mod == LENGTH_UPPER_L) {
     b3c:	f002 0278 	and.w	r2, r2, #120	; 0x78
		conv->specifier_cat = SPECIFIER_UINT;
     b40:	f360 0102 	bfi	r1, r0, #0, #3
		if (conv->length_mod == LENGTH_UPPER_L) {
     b44:	2a40      	cmp	r2, #64	; 0x40
		conv->specifier_cat = SPECIFIER_UINT;
     b46:	f88d 1042 	strb.w	r1, [sp, #66]	; 0x42
			conv->invalid = true;
     b4a:	bf02      	ittt	eq
     b4c:	f89d 1040 	ldrbeq.w	r1, [sp, #64]	; 0x40
     b50:	f041 0101 	orreq.w	r1, r1, #1
     b54:	f88d 1040 	strbeq.w	r1, [sp, #64]	; 0x40
		if (conv->specifier == 'c') {
     b58:	2b63      	cmp	r3, #99	; 0x63
     b5a:	d1db      	bne.n	b14 <CONFIG_ISR_STACK_SIZE+0x314>
			unsupported = (conv->length_mod != LENGTH_NONE);
     b5c:	1e13      	subs	r3, r2, #0
     b5e:	bf18      	it	ne
     b60:	2301      	movne	r3, #1
     b62:	e7d8      	b.n	b16 <CONFIG_ISR_STACK_SIZE+0x316>
		conv->specifier_cat = SPECIFIER_PTR;
     b64:	2103      	movs	r1, #3
     b66:	f89d 3042 	ldrb.w	r3, [sp, #66]	; 0x42
		if (conv->length_mod != LENGTH_NONE) {
     b6a:	f012 0f78 	tst.w	r2, #120	; 0x78
		conv->specifier_cat = SPECIFIER_PTR;
     b6e:	f361 0302 	bfi	r3, r1, #0, #3
     b72:	f88d 3042 	strb.w	r3, [sp, #66]	; 0x42
		if (conv->length_mod != LENGTH_NONE) {
     b76:	bf14      	ite	ne
     b78:	2301      	movne	r3, #1
     b7a:	2300      	moveq	r3, #0
     b7c:	e7cb      	b.n	b16 <CONFIG_ISR_STACK_SIZE+0x316>
		conv->invalid = true;
     b7e:	f89d 3040 	ldrb.w	r3, [sp, #64]	; 0x40
     b82:	f043 0301 	orr.w	r3, r3, #1
     b86:	f88d 3040 	strb.w	r3, [sp, #64]	; 0x40
		break;
     b8a:	e7c3      	b.n	b14 <CONFIG_ISR_STACK_SIZE+0x314>
		} else if (conv->width_present) {
     b8c:	f99d 2040 	ldrsb.w	r2, [sp, #64]	; 0x40
     b90:	2a00      	cmp	r2, #0
		int width = -1;
     b92:	bfac      	ite	ge
     b94:	f04f 38ff 	movge.w	r8, #4294967295
			width = conv->width_value;
     b98:	f8dd 8044 	ldrlt.w	r8, [sp, #68]	; 0x44
     b9c:	e6d5      	b.n	94a <CONFIG_ISR_STACK_SIZE+0x14a>
		} else if (conv->prec_present) {
     b9e:	0798      	lsls	r0, r3, #30
     ba0:	f57f aee2 	bpl.w	968 <CONFIG_ISR_STACK_SIZE+0x168>
			precision = conv->prec_value;
     ba4:	f8dd a048 	ldr.w	sl, [sp, #72]	; 0x48
		conv->pad0_value = 0;
     ba8:	2300      	movs	r3, #0
		conv->pad0_pre_exp = 0;
     baa:	e9cd 3311 	strd	r3, r3, [sp, #68]	; 0x44
			= (enum specifier_cat_enum)conv->specifier_cat;
     bae:	f89d 3042 	ldrb.w	r3, [sp, #66]	; 0x42
			= (enum length_mod_enum)conv->length_mod;
     bb2:	f89d 1041 	ldrb.w	r1, [sp, #65]	; 0x41
		enum specifier_cat_enum specifier_cat
     bb6:	f003 0307 	and.w	r3, r3, #7
		if (specifier_cat == SPECIFIER_SINT) {
     bba:	2b01      	cmp	r3, #1
			= (enum length_mod_enum)conv->length_mod;
     bbc:	f3c1 01c3 	ubfx	r1, r1, #3, #4
		if (specifier_cat == SPECIFIER_SINT) {
     bc0:	d133      	bne.n	c2a <CONFIG_ISR_STACK_SIZE+0x42a>
			switch (length_mod) {
     bc2:	1ecb      	subs	r3, r1, #3
     bc4:	2b04      	cmp	r3, #4
     bc6:	d804      	bhi.n	bd2 <CONFIG_ISR_STACK_SIZE+0x3d2>
     bc8:	e8df f003 	tbb	[pc, r3]
     bcc:	21464621 	.word	0x21464621
     bd0:	21          	.byte	0x21
     bd1:	00          	.byte	0x00
				value->sint = va_arg(ap, int);
     bd2:	6823      	ldr	r3, [r4, #0]
			if (length_mod == LENGTH_HH) {
     bd4:	2901      	cmp	r1, #1
				value->sint = va_arg(ap, int);
     bd6:	ea4f 72e3 	mov.w	r2, r3, asr #31
     bda:	e9cd 320e 	strd	r3, r2, [sp, #56]	; 0x38
			if (length_mod == LENGTH_HH) {
     bde:	d11c      	bne.n	c1a <CONFIG_ISR_STACK_SIZE+0x41a>
				value->sint = (signed char)value->sint;
     be0:	f99d 3038 	ldrsb.w	r3, [sp, #56]	; 0x38
     be4:	17da      	asrs	r2, r3, #31
     be6:	e9cd 320e 	strd	r3, r2, [sp, #56]	; 0x38
				value->sint = va_arg(ap, int);
     bea:	3404      	adds	r4, #4
		if (conv->invalid || conv->unsupported) {
     bec:	f89d 3040 	ldrb.w	r3, [sp, #64]	; 0x40
     bf0:	f013 0603 	ands.w	r6, r3, #3
     bf4:	d050      	beq.n	c98 <CONFIG_ISR_STACK_SIZE+0x498>
			OUTS(sp, fp);
     bf6:	463a      	mov	r2, r7
     bf8:	4659      	mov	r1, fp
     bfa:	4648      	mov	r0, r9
     bfc:	9b03      	ldr	r3, [sp, #12]
     bfe:	f005 fa2a 	bl	6056 <outs>
     c02:	2800      	cmp	r0, #0
     c04:	f2c0 8152 	blt.w	eac <CONFIG_ISR_STACK_SIZE+0x6ac>
     c08:	4405      	add	r5, r0
			continue;
     c0a:	9f03      	ldr	r7, [sp, #12]
     c0c:	e5f2      	b.n	7f4 <z_cbvprintf_impl+0x10>
					(sint_value_type)va_arg(ap, ptrdiff_t);
     c0e:	f854 3b04 	ldr.w	r3, [r4], #4
     c12:	17da      	asrs	r2, r3, #31
				value->uint = (unsigned char)value->uint;
     c14:	e9cd 320e 	strd	r3, r2, [sp, #56]	; 0x38
     c18:	e7e8      	b.n	bec <CONFIG_ISR_STACK_SIZE+0x3ec>
			} else if (length_mod == LENGTH_H) {
     c1a:	2902      	cmp	r1, #2
     c1c:	d1e5      	bne.n	bea <CONFIG_ISR_STACK_SIZE+0x3ea>
				value->sint = (short)value->sint;
     c1e:	b21a      	sxth	r2, r3
     c20:	f343 33c0 	sbfx	r3, r3, #15, #1
     c24:	e9cd 230e 	strd	r2, r3, [sp, #56]	; 0x38
     c28:	e7df      	b.n	bea <CONFIG_ISR_STACK_SIZE+0x3ea>
		} else if (specifier_cat == SPECIFIER_UINT) {
     c2a:	2b02      	cmp	r3, #2
     c2c:	d124      	bne.n	c78 <CONFIG_ISR_STACK_SIZE+0x478>
			switch (length_mod) {
     c2e:	1ecb      	subs	r3, r1, #3
     c30:	2b04      	cmp	r3, #4
     c32:	d804      	bhi.n	c3e <CONFIG_ISR_STACK_SIZE+0x43e>
     c34:	e8df f003 	tbb	[pc, r3]
     c38:	18101018 	.word	0x18101018
     c3c:	18          	.byte	0x18
     c3d:	00          	.byte	0x00
			if (length_mod == LENGTH_HH) {
     c3e:	2901      	cmp	r1, #1
     c40:	f04f 0200 	mov.w	r2, #0
				value->uint = va_arg(ap, unsigned int);
     c44:	f854 3b04 	ldr.w	r3, [r4], #4
			if (length_mod == LENGTH_HH) {
     c48:	d014      	beq.n	c74 <CONFIG_ISR_STACK_SIZE+0x474>
			} else if (length_mod == LENGTH_H) {
     c4a:	2902      	cmp	r1, #2
				value->uint = va_arg(ap, unsigned int);
     c4c:	e9cd 320e 	strd	r3, r2, [sp, #56]	; 0x38
			} else if (length_mod == LENGTH_H) {
     c50:	d1cc      	bne.n	bec <CONFIG_ISR_STACK_SIZE+0x3ec>
				value->uint = (unsigned short)value->uint;
     c52:	b29b      	uxth	r3, r3
			value->ptr = va_arg(ap, void *);
     c54:	930e      	str	r3, [sp, #56]	; 0x38
     c56:	e7c9      	b.n	bec <CONFIG_ISR_STACK_SIZE+0x3ec>
					(uint_value_type)va_arg(ap,
     c58:	3407      	adds	r4, #7
     c5a:	f024 0407 	bic.w	r4, r4, #7
				value->uint =
     c5e:	e8f4 2302 	ldrd	r2, r3, [r4], #8
     c62:	e9cd 230e 	strd	r2, r3, [sp, #56]	; 0x38
			if (length_mod == LENGTH_HH) {
     c66:	e7c1      	b.n	bec <CONFIG_ISR_STACK_SIZE+0x3ec>
					(uint_value_type)va_arg(ap, size_t);
     c68:	f854 3b04 	ldr.w	r3, [r4], #4
     c6c:	930e      	str	r3, [sp, #56]	; 0x38
     c6e:	2300      	movs	r3, #0
     c70:	930f      	str	r3, [sp, #60]	; 0x3c
			} else if (length_mod == LENGTH_H) {
     c72:	e7bb      	b.n	bec <CONFIG_ISR_STACK_SIZE+0x3ec>
				value->uint = (unsigned char)value->uint;
     c74:	b2db      	uxtb	r3, r3
     c76:	e7cd      	b.n	c14 <CONFIG_ISR_STACK_SIZE+0x414>
		} else if (specifier_cat == SPECIFIER_FP) {
     c78:	2b04      	cmp	r3, #4
     c7a:	d108      	bne.n	c8e <CONFIG_ISR_STACK_SIZE+0x48e>
					(sint_value_type)va_arg(ap, long long);
     c7c:	3407      	adds	r4, #7
				value->ldbl = va_arg(ap, long double);
     c7e:	f024 0407 	bic.w	r4, r4, #7
     c82:	e9d4 2300 	ldrd	r2, r3, [r4]
     c86:	3408      	adds	r4, #8
     c88:	e9cd 230e 	strd	r2, r3, [sp, #56]	; 0x38
     c8c:	e7ae      	b.n	bec <CONFIG_ISR_STACK_SIZE+0x3ec>
		} else if (specifier_cat == SPECIFIER_PTR) {
     c8e:	2b03      	cmp	r3, #3
     c90:	d1ac      	bne.n	bec <CONFIG_ISR_STACK_SIZE+0x3ec>
			value->ptr = va_arg(ap, void *);
     c92:	f854 3b04 	ldr.w	r3, [r4], #4
     c96:	e7dd      	b.n	c54 <CONFIG_ISR_STACK_SIZE+0x454>
		switch (conv->specifier) {
     c98:	f89d 0043 	ldrb.w	r0, [sp, #67]	; 0x43
     c9c:	2878      	cmp	r0, #120	; 0x78
     c9e:	d8b4      	bhi.n	c0a <CONFIG_ISR_STACK_SIZE+0x40a>
     ca0:	2862      	cmp	r0, #98	; 0x62
     ca2:	d81c      	bhi.n	cde <CONFIG_ISR_STACK_SIZE+0x4de>
     ca4:	2825      	cmp	r0, #37	; 0x25
     ca6:	f43f adad 	beq.w	804 <CONFIG_ISR_STACK_SIZE+0x4>
     caa:	2858      	cmp	r0, #88	; 0x58
     cac:	d1ad      	bne.n	c0a <CONFIG_ISR_STACK_SIZE+0x40a>
			bps = encode_uint(value->uint, conv, buf, bpe);
     cae:	e9dd 010e 	ldrd	r0, r1, [sp, #56]	; 0x38
     cb2:	f10d 0336 	add.w	r3, sp, #54	; 0x36
     cb6:	9300      	str	r3, [sp, #0]
     cb8:	aa10      	add	r2, sp, #64	; 0x40
     cba:	ab08      	add	r3, sp, #32
     cbc:	f005 f985 	bl	5fca <encode_uint>
			if (precision >= 0) {
     cc0:	f1ba 0f00 	cmp.w	sl, #0
			bps = encode_uint(value->uint, conv, buf, bpe);
     cc4:	4607      	mov	r7, r0
			if (precision >= 0) {
     cc6:	f280 8099 	bge.w	dfc <CONFIG_ISR_STACK_SIZE+0x5fc>
		if (bps == NULL) {
     cca:	2f00      	cmp	r7, #0
     ccc:	d09d      	beq.n	c0a <CONFIG_ISR_STACK_SIZE+0x40a>
		size_t nj_len = (bpe - bps);
     cce:	f10d 0336 	add.w	r3, sp, #54	; 0x36
     cd2:	1bd8      	subs	r0, r3, r7
		if (sign != 0) {
     cd4:	2e00      	cmp	r6, #0
     cd6:	f000 80c0 	beq.w	e5a <CONFIG_ISR_STACK_SIZE+0x65a>
			nj_len += 1U;
     cda:	3001      	adds	r0, #1
     cdc:	e0bd      	b.n	e5a <CONFIG_ISR_STACK_SIZE+0x65a>
		switch (conv->specifier) {
     cde:	3863      	subs	r0, #99	; 0x63
     ce0:	2815      	cmp	r0, #21
     ce2:	d892      	bhi.n	c0a <CONFIG_ISR_STACK_SIZE+0x40a>
     ce4:	a201      	add	r2, pc, #4	; (adr r2, cec <CONFIG_ISR_STACK_SIZE+0x4ec>)
     ce6:	f852 f020 	ldr.w	pc, [r2, r0, lsl #2]
     cea:	bf00      	nop
     cec:	00000dc1 	.word	0x00000dc1
     cf0:	00000dd3 	.word	0x00000dd3
     cf4:	00000c0b 	.word	0x00000c0b
     cf8:	00000c0b 	.word	0x00000c0b
     cfc:	00000c0b 	.word	0x00000c0b
     d00:	00000c0b 	.word	0x00000c0b
     d04:	00000dd3 	.word	0x00000dd3
     d08:	00000c0b 	.word	0x00000c0b
     d0c:	00000c0b 	.word	0x00000c0b
     d10:	00000c0b 	.word	0x00000c0b
     d14:	00000c0b 	.word	0x00000c0b
     d18:	00000e5f 	.word	0x00000e5f
     d1c:	00000df7 	.word	0x00000df7
     d20:	00000e1d 	.word	0x00000e1d
     d24:	00000c0b 	.word	0x00000c0b
     d28:	00000c0b 	.word	0x00000c0b
     d2c:	00000d45 	.word	0x00000d45
     d30:	00000c0b 	.word	0x00000c0b
     d34:	00000df7 	.word	0x00000df7
     d38:	00000c0b 	.word	0x00000c0b
     d3c:	00000c0b 	.word	0x00000c0b
     d40:	00000df7 	.word	0x00000df7
			if (precision >= 0) {
     d44:	f1ba 0f00 	cmp.w	sl, #0
			bps = (const char *)value->ptr;
     d48:	9f0e      	ldr	r7, [sp, #56]	; 0x38
			if (precision >= 0) {
     d4a:	db35      	blt.n	db8 <CONFIG_ISR_STACK_SIZE+0x5b8>
				len = strnlen(bps, precision);
     d4c:	4651      	mov	r1, sl
     d4e:	4638      	mov	r0, r7
     d50:	f005 f9e5 	bl	611e <strnlen>
			bpe = bps + len;
     d54:	eb07 0a00 	add.w	sl, r7, r0
		if (bps == NULL) {
     d58:	2f00      	cmp	r7, #0
     d5a:	f43f af56 	beq.w	c0a <CONFIG_ISR_STACK_SIZE+0x40a>
		char sign = 0;
     d5e:	2600      	movs	r6, #0
		if (conv->altform_0c) {
     d60:	f89d 3042 	ldrb.w	r3, [sp, #66]	; 0x42
     d64:	f013 0210 	ands.w	r2, r3, #16
     d68:	9205      	str	r2, [sp, #20]
     d6a:	f000 8092 	beq.w	e92 <CONFIG_ISR_STACK_SIZE+0x692>
			nj_len += 2U;
     d6e:	3002      	adds	r0, #2
		if (conv->pad_fp) {
     d70:	065b      	lsls	r3, r3, #25
		nj_len += conv->pad0_value;
     d72:	9a11      	ldr	r2, [sp, #68]	; 0x44
			nj_len += conv->pad0_pre_exp;
     d74:	bf48      	it	mi
     d76:	9b12      	ldrmi	r3, [sp, #72]	; 0x48
		nj_len += conv->pad0_value;
     d78:	4410      	add	r0, r2
			nj_len += conv->pad0_pre_exp;
     d7a:	bf48      	it	mi
     d7c:	18c0      	addmi	r0, r0, r3
		if (width > 0) {
     d7e:	f1b8 0f00 	cmp.w	r8, #0
		nj_len += conv->pad0_value;
     d82:	9204      	str	r2, [sp, #16]
		if (width > 0) {
     d84:	f340 809f 	ble.w	ec6 <CONFIG_ISR_STACK_SIZE+0x6c6>
			if (!conv->flag_dash) {
     d88:	f89d 2040 	ldrb.w	r2, [sp, #64]	; 0x40
			width -= (int)nj_len;
     d8c:	eba8 0800 	sub.w	r8, r8, r0
			if (!conv->flag_dash) {
     d90:	f3c2 0380 	ubfx	r3, r2, #2, #1
     d94:	0750      	lsls	r0, r2, #29
     d96:	9306      	str	r3, [sp, #24]
     d98:	f100 8095 	bmi.w	ec6 <CONFIG_ISR_STACK_SIZE+0x6c6>
				if (conv->flag_zero) {
     d9c:	0651      	lsls	r1, r2, #25
     d9e:	f140 8088 	bpl.w	eb2 <CONFIG_ISR_STACK_SIZE+0x6b2>
					if (sign != 0) {
     da2:	b13e      	cbz	r6, db4 <CONFIG_ISR_STACK_SIZE+0x5b4>
						OUTC(sign);
     da4:	4659      	mov	r1, fp
     da6:	4630      	mov	r0, r6
     da8:	47c8      	blx	r9
     daa:	2800      	cmp	r0, #0
     dac:	db7e      	blt.n	eac <CONFIG_ISR_STACK_SIZE+0x6ac>
     dae:	9b06      	ldr	r3, [sp, #24]
     db0:	3501      	adds	r5, #1
     db2:	461e      	mov	r6, r3
					pad = '0';
     db4:	2230      	movs	r2, #48	; 0x30
     db6:	e07d      	b.n	eb4 <CONFIG_ISR_STACK_SIZE+0x6b4>
				len = strlen(bps);
     db8:	4638      	mov	r0, r7
     dba:	f005 f9a9 	bl	6110 <strlen>
     dbe:	e7c9      	b.n	d54 <CONFIG_ISR_STACK_SIZE+0x554>
			buf[0] = CHAR_IS_SIGNED ? value->sint : value->uint;
     dc0:	9b0e      	ldr	r3, [sp, #56]	; 0x38
		char sign = 0;
     dc2:	2600      	movs	r6, #0
		size_t nj_len = (bpe - bps);
     dc4:	2001      	movs	r0, #1
			buf[0] = CHAR_IS_SIGNED ? value->sint : value->uint;
     dc6:	f88d 3020 	strb.w	r3, [sp, #32]
			bps = buf;
     dca:	af08      	add	r7, sp, #32
			bpe = buf + 1;
     dcc:	f10d 0a21 	add.w	sl, sp, #33	; 0x21
     dd0:	e7c6      	b.n	d60 <CONFIG_ISR_STACK_SIZE+0x560>
			if (conv->flag_plus) {
     dd2:	0719      	lsls	r1, r3, #28
			} else if (conv->flag_space) {
     dd4:	bf5a      	itte	pl
     dd6:	f3c3 1300 	ubfxpl	r3, r3, #4, #1
     dda:	015e      	lslpl	r6, r3, #5
				sign = '+';
     ddc:	262b      	movmi	r6, #43	; 0x2b
			sint = value->sint;
     dde:	e9dd 230e 	ldrd	r2, r3, [sp, #56]	; 0x38
			if (sint < 0) {
     de2:	2b00      	cmp	r3, #0
     de4:	f6bf af63 	bge.w	cae <CONFIG_ISR_STACK_SIZE+0x4ae>
				value->uint = (uint_value_type)-sint;
     de8:	4252      	negs	r2, r2
     dea:	eb63 0343 	sbc.w	r3, r3, r3, lsl #1
				sign = '-';
     dee:	262d      	movs	r6, #45	; 0x2d
				value->uint = (uint_value_type)-sint;
     df0:	e9cd 230e 	strd	r2, r3, [sp, #56]	; 0x38
     df4:	e75b      	b.n	cae <CONFIG_ISR_STACK_SIZE+0x4ae>
		switch (conv->specifier) {
     df6:	2600      	movs	r6, #0
     df8:	e759      	b.n	cae <CONFIG_ISR_STACK_SIZE+0x4ae>
		char sign = 0;
     dfa:	2600      	movs	r6, #0
				conv->flag_zero = false;
     dfc:	f89d 2040 	ldrb.w	r2, [sp, #64]	; 0x40
				size_t len = bpe - bps;
     e00:	f10d 0336 	add.w	r3, sp, #54	; 0x36
     e04:	1bdb      	subs	r3, r3, r7
				conv->flag_zero = false;
     e06:	f36f 1286 	bfc	r2, #6, #1
				if (len < (size_t)precision) {
     e0a:	459a      	cmp	sl, r3
				conv->flag_zero = false;
     e0c:	f88d 2040 	strb.w	r2, [sp, #64]	; 0x40
				if (len < (size_t)precision) {
     e10:	f67f af5b 	bls.w	cca <CONFIG_ISR_STACK_SIZE+0x4ca>
					conv->pad0_value = precision - (int)len;
     e14:	ebaa 0303 	sub.w	r3, sl, r3
     e18:	9311      	str	r3, [sp, #68]	; 0x44
     e1a:	e756      	b.n	cca <CONFIG_ISR_STACK_SIZE+0x4ca>
			if (value->ptr != NULL) {
     e1c:	980e      	ldr	r0, [sp, #56]	; 0x38
     e1e:	b390      	cbz	r0, e86 <CONFIG_ISR_STACK_SIZE+0x686>
				bps = encode_uint((uintptr_t)value->ptr, conv,
     e20:	f10d 0336 	add.w	r3, sp, #54	; 0x36
     e24:	9300      	str	r3, [sp, #0]
     e26:	2100      	movs	r1, #0
     e28:	ab08      	add	r3, sp, #32
     e2a:	aa10      	add	r2, sp, #64	; 0x40
     e2c:	f005 f8cd 	bl	5fca <encode_uint>
				conv->altform_0c = true;
     e30:	f8bd 3042 	ldrh.w	r3, [sp, #66]	; 0x42
			if (precision >= 0) {
     e34:	f1ba 0f00 	cmp.w	sl, #0
				conv->altform_0c = true;
     e38:	f003 03ef 	and.w	r3, r3, #239	; 0xef
     e3c:	f443 43f0 	orr.w	r3, r3, #30720	; 0x7800
     e40:	f043 0310 	orr.w	r3, r3, #16
				bps = encode_uint((uintptr_t)value->ptr, conv,
     e44:	4607      	mov	r7, r0
				conv->altform_0c = true;
     e46:	f8ad 3042 	strh.w	r3, [sp, #66]	; 0x42
			if (precision >= 0) {
     e4a:	dad6      	bge.n	dfa <CONFIG_ISR_STACK_SIZE+0x5fa>
		if (bps == NULL) {
     e4c:	2800      	cmp	r0, #0
     e4e:	f43f aedc 	beq.w	c0a <CONFIG_ISR_STACK_SIZE+0x40a>
		char sign = 0;
     e52:	2600      	movs	r6, #0
		size_t nj_len = (bpe - bps);
     e54:	f10d 0336 	add.w	r3, sp, #54	; 0x36
     e58:	1a18      	subs	r0, r3, r0
		if (sign != 0) {
     e5a:	469a      	mov	sl, r3
     e5c:	e780      	b.n	d60 <CONFIG_ISR_STACK_SIZE+0x560>
				store_count(conv, value->ptr, count);
     e5e:	9b0e      	ldr	r3, [sp, #56]	; 0x38
	switch ((enum length_mod_enum)conv->length_mod) {
     e60:	2907      	cmp	r1, #7
     e62:	f63f aed2 	bhi.w	c0a <CONFIG_ISR_STACK_SIZE+0x40a>
     e66:	e8df f001 	tbb	[pc, r1]
     e6a:	040c      	.short	0x040c
     e6c:	08080c06 	.word	0x08080c06
     e70:	0c0c      	.short	0x0c0c
		*(signed char *)dp = (signed char)count;
     e72:	701d      	strb	r5, [r3, #0]
		if (bps == NULL) {
     e74:	e6c9      	b.n	c0a <CONFIG_ISR_STACK_SIZE+0x40a>
		*(short *)dp = (short)count;
     e76:	801d      	strh	r5, [r3, #0]
		if (bps == NULL) {
     e78:	e6c7      	b.n	c0a <CONFIG_ISR_STACK_SIZE+0x40a>
		*(intmax_t *)dp = (intmax_t)count;
     e7a:	17ea      	asrs	r2, r5, #31
     e7c:	e9c3 5200 	strd	r5, r2, [r3]
		if (bps == NULL) {
     e80:	e6c3      	b.n	c0a <CONFIG_ISR_STACK_SIZE+0x40a>
		*(ptrdiff_t *)dp = (ptrdiff_t)count;
     e82:	601d      	str	r5, [r3, #0]
		if (bps == NULL) {
     e84:	e6c1      	b.n	c0a <CONFIG_ISR_STACK_SIZE+0x40a>
     e86:	4f2f      	ldr	r7, [pc, #188]	; (f44 <CONFIG_ISR_STACK_SIZE+0x744>)
		char sign = 0;
     e88:	4606      	mov	r6, r0
			bpe = bps + 5;
     e8a:	f107 0a05 	add.w	sl, r7, #5
		size_t nj_len = (bpe - bps);
     e8e:	2005      	movs	r0, #5
     e90:	e766      	b.n	d60 <CONFIG_ISR_STACK_SIZE+0x560>
		} else if (conv->altform_0) {
     e92:	071a      	lsls	r2, r3, #28
			nj_len += 1U;
     e94:	bf48      	it	mi
     e96:	3001      	addmi	r0, #1
     e98:	e76a      	b.n	d70 <CONFIG_ISR_STACK_SIZE+0x570>
					OUTC(pad);
     e9a:	4610      	mov	r0, r2
     e9c:	9307      	str	r3, [sp, #28]
     e9e:	9206      	str	r2, [sp, #24]
     ea0:	4659      	mov	r1, fp
     ea2:	47c8      	blx	r9
     ea4:	e9dd 2306 	ldrd	r2, r3, [sp, #24]
     ea8:	2800      	cmp	r0, #0
     eaa:	da04      	bge.n	eb6 <CONFIG_ISR_STACK_SIZE+0x6b6>
#undef OUTS
#undef OUTC
}
     eac:	b015      	add	sp, #84	; 0x54
     eae:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
				char pad = ' ';
     eb2:	2220      	movs	r2, #32
					pad = '0';
     eb4:	4643      	mov	r3, r8
				while (width-- > 0) {
     eb6:	4619      	mov	r1, r3
     eb8:	2900      	cmp	r1, #0
     eba:	f103 33ff 	add.w	r3, r3, #4294967295
     ebe:	dcec      	bgt.n	e9a <CONFIG_ISR_STACK_SIZE+0x69a>
     ec0:	4445      	add	r5, r8
     ec2:	4698      	mov	r8, r3
     ec4:	1a6d      	subs	r5, r5, r1
		if (sign != 0) {
     ec6:	b12e      	cbz	r6, ed4 <CONFIG_ISR_STACK_SIZE+0x6d4>
			OUTC(sign);
     ec8:	4659      	mov	r1, fp
     eca:	4630      	mov	r0, r6
     ecc:	47c8      	blx	r9
     ece:	2800      	cmp	r0, #0
     ed0:	dbec      	blt.n	eac <CONFIG_ISR_STACK_SIZE+0x6ac>
     ed2:	3501      	adds	r5, #1
			if (conv->altform_0c | conv->altform_0) {
     ed4:	f89d 3042 	ldrb.w	r3, [sp, #66]	; 0x42
     ed8:	06da      	lsls	r2, r3, #27
     eda:	d401      	bmi.n	ee0 <CONFIG_ISR_STACK_SIZE+0x6e0>
     edc:	071b      	lsls	r3, r3, #28
     ede:	d505      	bpl.n	eec <CONFIG_ISR_STACK_SIZE+0x6ec>
				OUTC('0');
     ee0:	4659      	mov	r1, fp
     ee2:	2030      	movs	r0, #48	; 0x30
     ee4:	47c8      	blx	r9
     ee6:	2800      	cmp	r0, #0
     ee8:	dbe0      	blt.n	eac <CONFIG_ISR_STACK_SIZE+0x6ac>
     eea:	3501      	adds	r5, #1
			if (conv->altform_0c) {
     eec:	9b05      	ldr	r3, [sp, #20]
     eee:	b133      	cbz	r3, efe <CONFIG_ISR_STACK_SIZE+0x6fe>
				OUTC(conv->specifier);
     ef0:	4659      	mov	r1, fp
     ef2:	f89d 0043 	ldrb.w	r0, [sp, #67]	; 0x43
     ef6:	47c8      	blx	r9
     ef8:	2800      	cmp	r0, #0
     efa:	dbd7      	blt.n	eac <CONFIG_ISR_STACK_SIZE+0x6ac>
     efc:	3501      	adds	r5, #1
			while (pad_len-- > 0) {
     efe:	9e04      	ldr	r6, [sp, #16]
     f00:	442e      	add	r6, r5
     f02:	e005      	b.n	f10 <CONFIG_ISR_STACK_SIZE+0x710>
				OUTC('0');
     f04:	4659      	mov	r1, fp
     f06:	2030      	movs	r0, #48	; 0x30
     f08:	47c8      	blx	r9
     f0a:	2800      	cmp	r0, #0
     f0c:	dbce      	blt.n	eac <CONFIG_ISR_STACK_SIZE+0x6ac>
     f0e:	3501      	adds	r5, #1
			while (pad_len-- > 0) {
     f10:	1b73      	subs	r3, r6, r5
     f12:	2b00      	cmp	r3, #0
     f14:	dcf6      	bgt.n	f04 <CONFIG_ISR_STACK_SIZE+0x704>
			OUTS(bps, bpe);
     f16:	4653      	mov	r3, sl
     f18:	463a      	mov	r2, r7
     f1a:	4659      	mov	r1, fp
     f1c:	4648      	mov	r0, r9
     f1e:	f005 f89a 	bl	6056 <outs>
     f22:	2800      	cmp	r0, #0
     f24:	dbc2      	blt.n	eac <CONFIG_ISR_STACK_SIZE+0x6ac>
     f26:	4405      	add	r5, r0
		while (width > 0) {
     f28:	44a8      	add	r8, r5
     f2a:	eba8 0305 	sub.w	r3, r8, r5
     f2e:	2b00      	cmp	r3, #0
     f30:	f77f ae6b 	ble.w	c0a <CONFIG_ISR_STACK_SIZE+0x40a>
			OUTC(' ');
     f34:	4659      	mov	r1, fp
     f36:	2020      	movs	r0, #32
     f38:	47c8      	blx	r9
     f3a:	2800      	cmp	r0, #0
     f3c:	dbb6      	blt.n	eac <CONFIG_ISR_STACK_SIZE+0x6ac>
     f3e:	3501      	adds	r5, #1
			--width;
     f40:	e7f3      	b.n	f2a <CONFIG_ISR_STACK_SIZE+0x72a>
     f42:	bf00      	nop
     f44:	0000776c 	.word	0x0000776c

00000f48 <sys_reboot>:
#include <zephyr/sys/printk.h>

extern void sys_arch_reboot(int type);

FUNC_NORETURN void sys_reboot(int type)
{
     f48:	b508      	push	{r3, lr}
	__asm__ volatile(
     f4a:	f04f 0220 	mov.w	r2, #32
     f4e:	f3ef 8311 	mrs	r3, BASEPRI
     f52:	f382 8812 	msr	BASEPRI_MAX, r2
     f56:	f3bf 8f6f 	isb	sy
	(void)irq_lock();
	sys_clock_disable();

	sys_arch_reboot(type);
     f5a:	f000 fd65 	bl	1a28 <sys_arch_reboot>

	/* should never get here */
	printk("Failed to reboot: spinning endlessly...\n");
     f5e:	4803      	ldr	r0, [pc, #12]	; (f6c <sys_reboot+0x24>)
     f60:	f004 ff43 	bl	5dea <printk>
 * @note In some architectures, before returning, the function unmasks interrupts
 * unconditionally.
 */
static inline void k_cpu_idle(void)
{
	arch_cpu_idle();
     f64:	f000 fae8 	bl	1538 <arch_cpu_idle>
     f68:	e7fc      	b.n	f64 <sys_reboot+0x1c>
     f6a:	bf00      	nop
     f6c:	00007772 	.word	0x00007772

00000f70 <nrf_gpio_pin_control_select.constprop.0>:

#if NRF_GPIO_HAS_SEL
NRF_STATIC_INLINE void nrf_gpio_pin_control_select(uint32_t pin_number, nrf_gpio_pin_sel_t ctrl)
{
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_MCUSEL_Msk;
     f70:	4b05      	ldr	r3, [pc, #20]	; (f88 <nrf_gpio_pin_control_select.constprop.0+0x18>)
     f72:	eb03 0080 	add.w	r0, r3, r0, lsl #2
     f76:	f8d0 3200 	ldr.w	r3, [r0, #512]	; 0x200
     f7a:	f023 43e0 	bic.w	r3, r3, #1879048192	; 0x70000000
    reg->PIN_CNF[pin_number] = cnf | (ctrl << GPIO_PIN_CNF_MCUSEL_Pos);
     f7e:	f043 5340 	orr.w	r3, r3, #805306368	; 0x30000000
     f82:	f8c0 3200 	str.w	r3, [r0, #512]	; 0x200
}
     f86:	4770      	bx	lr
     f88:	50842500 	.word	0x50842500

00000f8c <nordicsemi_nrf53_init>:
	return true;
}
#endif /* CONFIG_SOC_NRF53_ANOMALY_160_WORKAROUND */

static int nordicsemi_nrf53_init(const struct device *arg)
{
     f8c:	b538      	push	{r3, r4, r5, lr}
     f8e:	f04f 0320 	mov.w	r3, #32
     f92:	f3ef 8511 	mrs	r5, BASEPRI
     f96:	f383 8812 	msr	BASEPRI_MAX, r3
     f9a:	f3bf 8f6f 	isb	sy

#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE void nrf_cache_enable(NRF_CACHE_Type * p_reg)
{
    p_reg->ENABLE = CACHE_ENABLE_ENABLE_Enabled;
     f9e:	2101      	movs	r1, #1
     fa0:	4b1a      	ldr	r3, [pc, #104]	; (100c <CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE+0xc>)
}

NRF_STATIC_INLINE void nrf_oscillators_lfxo_cap_set(NRF_OSCILLATORS_Type *     p_reg,
                                                    nrf_oscillators_lfxo_cap_t cap)
{
    p_reg->XOSC32KI.INTCAP = (uint32_t)cap;
     fa2:	4a1b      	ldr	r2, [pc, #108]	; (1010 <CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE+0x10>)
     fa4:	f8c3 1500 	str.w	r1, [r3, #1280]	; 0x500
     fa8:	2302      	movs	r3, #2
#if !defined(CONFIG_BUILD_WITH_TFM)
	/* This can only be done from secure code.
	 * This is handled by the TF-M platform so we skip it when TF-M is
	 * enabled.
	 */
	nrf_gpio_pin_control_select(PIN_XL1, NRF_GPIO_PIN_SEL_PERIPHERAL);
     faa:	2000      	movs	r0, #0
     fac:	f8c2 36d0 	str.w	r3, [r2, #1744]	; 0x6d0
     fb0:	f7ff ffde 	bl	f70 <nrf_gpio_pin_control_select.constprop.0>
	nrf_gpio_pin_control_select(PIN_XL2, NRF_GPIO_PIN_SEL_PERIPHERAL);
     fb4:	4608      	mov	r0, r1
     fb6:	f7ff ffdb 	bl	f70 <nrf_gpio_pin_control_select.constprop.0>
	*((volatile uint32_t *)0x5000470C) = 0x7Eul;
     fba:	237e      	movs	r3, #126	; 0x7e
	*((volatile uint32_t *)0x50002118) = 0x7Ful;
     fbc:	207f      	movs	r0, #127	; 0x7f
	*((volatile uint32_t *)0x5000470C) = 0x7Eul;
     fbe:	f8c2 370c 	str.w	r3, [r2, #1804]	; 0x70c
	*((volatile uint32_t *)0x5000493C) = 0x7Eul;
     fc2:	f8c2 393c 	str.w	r3, [r2, #2364]	; 0x93c
	*((volatile uint32_t *)0x50002118) = 0x7Ful;
     fc6:	4b13      	ldr	r3, [pc, #76]	; (1014 <CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE+0x14>)
	*((volatile uint32_t *)0x50039E04) = 0x0ul;
     fc8:	4c13      	ldr	r4, [pc, #76]	; (1018 <CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE+0x18>)
	*((volatile uint32_t *)0x50002118) = 0x7Ful;
     fca:	f8c3 0118 	str.w	r0, [r3, #280]	; 0x118
	*((volatile uint32_t *)0x50039E04) = 0x0ul;
     fce:	2000      	movs	r0, #0
     fd0:	f8c4 0e04 	str.w	r0, [r4, #3588]	; 0xe04
	*((volatile uint32_t *)0x50039E08) = 0x0ul;
     fd4:	f8c4 0e08 	str.w	r0, [r4, #3592]	; 0xe08
	*((volatile uint32_t *)0x50101110) = 0x0ul;
     fd8:	f504 2448 	add.w	r4, r4, #819200	; 0xc8000
     fdc:	f8c4 0110 	str.w	r0, [r4, #272]	; 0x110
	*((volatile uint32_t *)0x50002124) = 0x0ul;
     fe0:	f8c3 0124 	str.w	r0, [r3, #292]	; 0x124
	*((volatile uint32_t *)0x5000212C) = 0x0ul;
     fe4:	f8c3 012c 	str.w	r0, [r3, #300]	; 0x12c
	*((volatile uint32_t *)0x502012A0) = 0x0ul;
     fe8:	f503 13ff 	add.w	r3, r3, #2088960	; 0x1fe000
     fec:	f503 5380 	add.w	r3, r3, #4096	; 0x1000
     ff0:	f8c3 02a0 	str.w	r0, [r3, #672]	; 0x2a0
NRF_STATIC_INLINE void nrf_regulators_dcdcen_set(NRF_REGULATORS_Type * p_reg, bool enable)
{
#if defined(REGULATORS_DCDCEN_DCDCEN_Msk)
    p_reg->DCDCEN = (enable ? REGULATORS_DCDCEN_DCDCEN_Msk : 0);
#else
    p_reg->VREGMAIN.DCDCEN = (enable ? REGULATORS_VREGMAIN_DCDCEN_DCDCEN_Msk : 0);
     ff4:	f8c2 1704 	str.w	r1, [r2, #1796]	; 0x704
#endif

#if NRF_REGULATORS_HAS_DCDCEN_RADIO
NRF_STATIC_INLINE void nrf_regulators_dcdcen_radio_set(NRF_REGULATORS_Type * p_reg, bool enable)
{
    p_reg->VREGRADIO.DCDCEN = (enable) ? REGULATORS_VREGRADIO_DCDCEN_DCDCEN_Enabled :
     ff8:	f8c2 1904 	str.w	r1, [r2, #2308]	; 0x904
    p_reg->VREGH.DCDCEN = (enable) ? REGULATORS_VREGH_DCDCEN_DCDCEN_Enabled :
     ffc:	f8c2 1b00 	str.w	r1, [r2, #2816]	; 0xb00
	__asm__ volatile(
    1000:	f385 8811 	msr	BASEPRI, r5
    1004:	f3bf 8f6f 	isb	sy
	NMI_INIT();

	irq_unlock(key);

	return 0;
}
    1008:	bd38      	pop	{r3, r4, r5, pc}
    100a:	bf00      	nop
    100c:	50001000 	.word	0x50001000
    1010:	50004000 	.word	0x50004000
    1014:	50002000 	.word	0x50002000
    1018:	50039000 	.word	0x50039000

0000101c <z_arm_on_enter_cpu_idle>:
	uint8_t oldest = (current + 1) % ARRAY_SIZE(timestamps);
    101c:	2305      	movs	r3, #5
{
    101e:	b570      	push	{r4, r5, r6, lr}
	uint8_t oldest = (current + 1) % ARRAY_SIZE(timestamps);
    1020:	4d17      	ldr	r5, [pc, #92]	; (1080 <z_arm_on_enter_cpu_idle+0x64>)
    1022:	4e18      	ldr	r6, [pc, #96]	; (1084 <z_arm_on_enter_cpu_idle+0x68>)
    1024:	782c      	ldrb	r4, [r5, #0]
    1026:	3401      	adds	r4, #1
    1028:	fbb4 f3f3 	udiv	r3, r4, r3
    102c:	eb03 0383 	add.w	r3, r3, r3, lsl #2
    1030:	1ae4      	subs	r4, r4, r3
#ifndef _ASMLANGUAGE
extern uint32_t sys_clock_cycle_get_32(void);

static inline uint32_t arch_k_cycle_get_32(void)
{
	return sys_clock_cycle_get_32();
    1032:	f005 fbcf 	bl	67d4 <sys_clock_cycle_get_32>
	if (timestamps_filled &&
    1036:	4a14      	ldr	r2, [pc, #80]	; (1088 <z_arm_on_enter_cpu_idle+0x6c>)
    1038:	4b14      	ldr	r3, [pc, #80]	; (108c <z_arm_on_enter_cpu_idle+0x70>)
    103a:	7811      	ldrb	r1, [r2, #0]
    103c:	b151      	cbz	r1, 1054 <z_arm_on_enter_cpu_idle+0x38>
	    (now - timestamps[oldest]) < (window_cycles + 1)) {
    103e:	f856 1024 	ldr.w	r1, [r6, r4, lsl #2]
    1042:	1a40      	subs	r0, r0, r1
	if (timestamps_filled &&
    1044:	2807      	cmp	r0, #7
    1046:	d805      	bhi.n	1054 <z_arm_on_enter_cpu_idle+0x38>
		if (!suppress_warning) {
    1048:	781a      	ldrb	r2, [r3, #0]
    104a:	b90a      	cbnz	r2, 1050 <z_arm_on_enter_cpu_idle+0x34>
			suppress_warning = true;
    104c:	2201      	movs	r2, #1
    104e:	701a      	strb	r2, [r3, #0]
		return false;
    1050:	2000      	movs	r0, #0
}
    1052:	bd70      	pop	{r4, r5, r6, pc}
	suppress_warning = false;
    1054:	2100      	movs	r1, #0
    1056:	7019      	strb	r1, [r3, #0]
    nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}

NRF_STATIC_INLINE bool nrf_power_event_check(NRF_POWER_Type const * p_reg, nrf_power_event_t event)
{
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    1058:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    105c:	f8d3 0114 	ldr.w	r0, [r3, #276]	; 0x114
	if (nrf_power_event_check(NRF_POWER, NRF_POWER_EVENT_SLEEPENTER)) {
    1060:	b138      	cbz	r0, 1072 <z_arm_on_enter_cpu_idle+0x56>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    1062:	f8c3 1114 	str.w	r1, [r3, #276]	; 0x114
#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE void nrf_event_readback(void * p_event_reg)
{
#if NRFX_CHECK(NRFX_EVENT_READBACK_ENABLED) && !defined(NRF51)
    (void)*((volatile uint32_t *)(p_event_reg));
    1066:	f8d3 3114 	ldr.w	r3, [r3, #276]	; 0x114
	uint8_t oldest = (current + 1) % ARRAY_SIZE(timestamps);
    106a:	702c      	strb	r4, [r5, #0]
		if (current == 0) {
    106c:	b90c      	cbnz	r4, 1072 <z_arm_on_enter_cpu_idle+0x56>
			timestamps_filled = true;
    106e:	2301      	movs	r3, #1
    1070:	7013      	strb	r3, [r2, #0]
	timestamps[current] = k_cycle_get_32();
    1072:	782c      	ldrb	r4, [r5, #0]
    1074:	f005 fbae 	bl	67d4 <sys_clock_cycle_get_32>
    1078:	f846 0024 	str.w	r0, [r6, r4, lsl #2]
	return true;
    107c:	2001      	movs	r0, #1
    107e:	e7e8      	b.n	1052 <z_arm_on_enter_cpu_idle+0x36>
    1080:	20000c32 	.word	0x20000c32
    1084:	20000368 	.word	0x20000368
    1088:	20000c31 	.word	0x20000c31
    108c:	20000c30 	.word	0x20000c30

00001090 <arch_busy_wait>:

#else // NRFX_CHECK(NRFX_DELAY_DWT_BASED)

NRF_STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us)
{
    if (time_us == 0)
    1090:	b148      	cbz	r0, 10a6 <arch_busy_wait+0x16>

    typedef void (* delay_func_t)(uint32_t);
    const delay_func_t delay_cycles =
        // Set LSB to 1 to execute the code in the Thumb mode.
        (delay_func_t)((((uint32_t)delay_machine_code) | 1));
    uint32_t cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ;
    1092:	4b05      	ldr	r3, [pc, #20]	; (10a8 <arch_busy_wait+0x18>)
    1094:	4a05      	ldr	r2, [pc, #20]	; (10ac <arch_busy_wait+0x1c>)
    1096:	681b      	ldr	r3, [r3, #0]
    1098:	fbb3 f3f2 	udiv	r3, r3, r2
    delay_cycles(cycles);
    109c:	4358      	muls	r0, r3
    109e:	4b04      	ldr	r3, [pc, #16]	; (10b0 <arch_busy_wait+0x20>)
    10a0:	f043 0301 	orr.w	r3, r3, #1
    10a4:	4718      	bx	r3

void arch_busy_wait(uint32_t time_us)
{
	nrfx_coredep_delay_us(time_us);
}
    10a6:	4770      	bx	lr
    10a8:	200000f0 	.word	0x200000f0
    10ac:	000f4240 	.word	0x000f4240
    10b0:	00007290 	.word	0x00007290

000010b4 <pm_state_set>:
/* Invoke Low Power/System Off specific Tasks */
__weak void pm_state_set(enum pm_state state, uint8_t substate_id)
{
	ARG_UNUSED(substate_id);

	switch (state) {
    10b4:	2806      	cmp	r0, #6
    10b6:	d107      	bne.n	10c8 <pm_state_set+0x14>
    p_reg->SYSTEMOFF = REGULATORS_SYSTEMOFF_SYSTEMOFF_Msk;
    10b8:	2201      	movs	r2, #1
    10ba:	4b04      	ldr	r3, [pc, #16]	; (10cc <pm_state_set+0x18>)
    10bc:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
  \details Acts as a special kind of Data Memory Barrier.
           It completes when all explicit memory accesses before this instruction complete.
 */
__STATIC_FORCEINLINE void __DSB(void)
{
  __ASM volatile ("dsb 0xF":::"memory");
    10c0:	f3bf 8f4f 	dsb	sy
        __WFE();
    10c4:	bf20      	wfe
    while (true)
    10c6:	e7fd      	b.n	10c4 <pm_state_set+0x10>
		break;
	default:
		LOG_DBG("Unsupported power state %u", state);
		break;
	}
}
    10c8:	4770      	bx	lr
    10ca:	bf00      	nop
    10cc:	50004000 	.word	0x50004000

000010d0 <z_arm_platform_init>:
	 */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r0, =SystemInit
	bx r0
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	b SystemInit
    10d0:	f002 baf0 	b.w	36b4 <SystemInit>

000010d4 <pm_state_notify>:
/*
 * Function called to notify when the system is entering / exiting a
 * power state
 */
static inline void pm_state_notify(bool entering_state)
{
    10d4:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    10d8:	4605      	mov	r5, r0
	__asm__ volatile(
    10da:	f04f 0320 	mov.w	r3, #32
    10de:	f3ef 8611 	mrs	r6, BASEPRI
    10e2:	f383 8812 	msr	BASEPRI_MAX, r3
    10e6:	f3bf 8f6f 	isb	sy
		} else {
			callback = notifier->state_exit;
		}

		if (callback) {
			callback(z_cpus_pm_state[_current_cpu->id].state);
    10ea:	f04f 090c 	mov.w	r9, #12
	return list->head;
    10ee:	4b0d      	ldr	r3, [pc, #52]	; (1124 <pm_state_notify+0x50>)
    10f0:	4f0d      	ldr	r7, [pc, #52]	; (1128 <pm_state_notify+0x54>)
    10f2:	681c      	ldr	r4, [r3, #0]
    10f4:	f8df 8034 	ldr.w	r8, [pc, #52]	; 112c <pm_state_notify+0x58>
	SYS_SLIST_FOR_EACH_CONTAINER(&pm_notifiers, notifier, _node) {
    10f8:	b92c      	cbnz	r4, 1106 <pm_state_notify+0x32>
	__asm__ volatile(
    10fa:	f386 8811 	msr	BASEPRI, r6
    10fe:	f3bf 8f6f 	isb	sy
		}
	}
	k_spin_unlock(&pm_notifier_lock, pm_notifier_key);
}
    1102:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
			callback = notifier->state_exit;
    1106:	e9d4 2301 	ldrd	r2, r3, [r4, #4]
			callback = notifier->state_entry;
    110a:	2d00      	cmp	r5, #0
    110c:	bf18      	it	ne
    110e:	4613      	movne	r3, r2
		if (callback) {
    1110:	b12b      	cbz	r3, 111e <pm_state_notify+0x4a>
			callback(z_cpus_pm_state[_current_cpu->id].state);
    1112:	f898 2014 	ldrb.w	r2, [r8, #20]
    1116:	fb09 f202 	mul.w	r2, r9, r2
    111a:	5cb8      	ldrb	r0, [r7, r2]
    111c:	4798      	blx	r3
	return node->next;
    111e:	6824      	ldr	r4, [r4, #0]
    1120:	e7ea      	b.n	10f8 <pm_state_notify+0x24>
    1122:	bf00      	nop
    1124:	20000394 	.word	0x20000394
    1128:	20000388 	.word	0x20000388
    112c:	20000a20 	.word	0x20000a20

00001130 <pm_system_resume>:
 *
 * @return true if the bit was set, false if it wasn't.
 */
static inline bool atomic_test_and_clear_bit(atomic_t *target, int bit)
{
	atomic_val_t mask = ATOMIC_MASK(bit);
    1130:	2201      	movs	r2, #1

void pm_system_resume(void)
{
    1132:	b570      	push	{r4, r5, r6, lr}
	uint8_t id = CURRENT_CPU;
    1134:	4b16      	ldr	r3, [pc, #88]	; (1190 <pm_system_resume+0x60>)
    1136:	7d1c      	ldrb	r4, [r3, #20]
    1138:	f004 031f 	and.w	r3, r4, #31
    113c:	409a      	lsls	r2, r3
	atomic_val_t old;

	old = atomic_and(ATOMIC_ELEM(target, bit), ~mask);
    113e:	43d0      	mvns	r0, r2
 *
 * @return Previous value of @a target.
 */
static inline atomic_val_t atomic_and(atomic_t *target, atomic_val_t value)
{
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    1140:	4b14      	ldr	r3, [pc, #80]	; (1194 <pm_system_resume+0x64>)
    1142:	0961      	lsrs	r1, r4, #5
    1144:	eb03 0381 	add.w	r3, r3, r1, lsl #2
    1148:	e8d3 1fef 	ldaex	r1, [r3]
    114c:	ea01 0500 	and.w	r5, r1, r0
    1150:	e8c3 5fe6 	stlex	r6, r5, [r3]
    1154:	2e00      	cmp	r6, #0
    1156:	d1f7      	bne.n	1148 <pm_system_resume+0x18>
	 * that caused the wake. This hook will be called from the ISR.
	 * For such CPU LPS states, do post operations and restores here.
	 * The kernel scheduler will get control after the ISR finishes
	 * and it may schedule another thread.
	 */
	if (atomic_test_and_clear_bit(z_post_ops_required, id)) {
    1158:	420a      	tst	r2, r1
    115a:	d013      	beq.n	1184 <pm_system_resume+0x54>
	if (pm_state_exit_post_ops != NULL) {
    115c:	4b0e      	ldr	r3, [pc, #56]	; (1198 <pm_system_resume+0x68>)
    115e:	4d0f      	ldr	r5, [pc, #60]	; (119c <pm_system_resume+0x6c>)
    1160:	b18b      	cbz	r3, 1186 <pm_system_resume+0x56>
		pm_state_exit_post_ops(info->state, info->substate_id);
    1162:	230c      	movs	r3, #12
    1164:	4363      	muls	r3, r4
    1166:	18ea      	adds	r2, r5, r3
    1168:	7851      	ldrb	r1, [r2, #1]
    116a:	5ce8      	ldrb	r0, [r5, r3]
    116c:	f004 ff8b 	bl	6086 <pm_state_exit_post_ops>
		pm_exit_pos_ops(&z_cpus_pm_state[id]);
		pm_state_notify(false);
    1170:	2000      	movs	r0, #0
    1172:	f7ff ffaf 	bl	10d4 <pm_state_notify>
		z_cpus_pm_state[id] = (struct pm_state_info){PM_STATE_ACTIVE,
    1176:	230c      	movs	r3, #12
    1178:	435c      	muls	r4, r3
    117a:	2300      	movs	r3, #0
    117c:	192a      	adds	r2, r5, r4
    117e:	512b      	str	r3, [r5, r4]
    1180:	e9c2 3301 	strd	r3, r3, [r2, #4]
			0, 0};
	}
}
    1184:	bd70      	pop	{r4, r5, r6, pc}
    1186:	f383 8811 	msr	BASEPRI, r3
    118a:	f3bf 8f6f 	isb	sy
		"cpsie i;"
		: : : "memory", "cc");
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
}
    118e:	e7ef      	b.n	1170 <pm_system_resume+0x40>
    1190:	20000a20 	.word	0x20000a20
    1194:	2000039c 	.word	0x2000039c
    1198:	00006087 	.word	0x00006087
    119c:	20000388 	.word	0x20000388

000011a0 <pm_system_suspend>:

	return true;
}

bool pm_system_suspend(int32_t ticks)
{
    11a0:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	uint8_t id = CURRENT_CPU;
    11a4:	4b32      	ldr	r3, [pc, #200]	; (1270 <pm_system_suspend+0xd0>)
{
    11a6:	4607      	mov	r7, r0
	uint8_t id = CURRENT_CPU;
    11a8:	7d1d      	ldrb	r5, [r3, #20]
	__asm__ volatile(
    11aa:	f04f 0320 	mov.w	r3, #32
    11ae:	f3ef 8811 	mrs	r8, BASEPRI
    11b2:	f383 8812 	msr	BASEPRI_MAX, r3
    11b6:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key;

	SYS_PORT_TRACING_FUNC_ENTER(pm, system_suspend, ticks);

	key = k_spin_lock(&pm_forced_state_lock);
	if (z_cpus_pm_forced_state[id].state != PM_STATE_ACTIVE) {
    11ba:	240c      	movs	r4, #12
    11bc:	436c      	muls	r4, r5
    11be:	4b2d      	ldr	r3, [pc, #180]	; (1274 <pm_system_suspend+0xd4>)
    11c0:	4e2d      	ldr	r6, [pc, #180]	; (1278 <pm_system_suspend+0xd8>)
    11c2:	5d19      	ldrb	r1, [r3, r4]
    11c4:	191a      	adds	r2, r3, r4
    11c6:	2900      	cmp	r1, #0
    11c8:	d047      	beq.n	125a <pm_system_suspend+0xba>
		z_cpus_pm_state[id] = z_cpus_pm_forced_state[id];
    11ca:	ca07      	ldmia	r2, {r0, r1, r2}
    11cc:	eb06 0c04 	add.w	ip, r6, r4
    11d0:	e88c 0007 	stmia.w	ip, {r0, r1, r2}
		z_cpus_pm_forced_state[id].state = PM_STATE_ACTIVE;
    11d4:	2200      	movs	r2, #0
    11d6:	551a      	strb	r2, [r3, r4]
	__asm__ volatile(
    11d8:	f388 8811 	msr	BASEPRI, r8
    11dc:	f3bf 8f6f 	isb	sy
			z_cpus_pm_state[id] = *info;
		}
	}
	k_spin_unlock(&pm_forced_state_lock, key);

	if (z_cpus_pm_state[id].state == PM_STATE_ACTIVE) {
    11e0:	230c      	movs	r3, #12
    11e2:	436b      	muls	r3, r5
    11e4:	5cf0      	ldrb	r0, [r6, r3]
    11e6:	18f2      	adds	r2, r6, r3
    11e8:	b3a8      	cbz	r0, 1256 <pm_system_suspend+0xb6>
		SYS_PORT_TRACING_FUNC_EXIT(pm, system_suspend, ticks,
				   z_cpus_pm_state[id].state);
		return false;
	}

	if (ticks != K_TICKS_FOREVER) {
    11ea:	1c7b      	adds	r3, r7, #1
    11ec:	d010      	beq.n	1210 <pm_system_suspend+0x70>
		} else {
			return t * ((uint64_t)to_hz / from_hz);
		}
	} else {
		if (result32) {
			return (uint32_t)((t * to_hz + off) / from_hz);
    11ee:	f44f 4000 	mov.w	r0, #32768	; 0x8000
    11f2:	2100      	movs	r1, #0
    11f4:	f8d2 c008 	ldr.w	ip, [r2, #8]
    11f8:	4c20      	ldr	r4, [pc, #128]	; (127c <pm_system_suspend+0xdc>)
    11fa:	2300      	movs	r3, #0
    11fc:	fbec 4100 	umlal	r4, r1, ip, r0
    1200:	4a1f      	ldr	r2, [pc, #124]	; (1280 <pm_system_suspend+0xe0>)
    1202:	4620      	mov	r0, r4
    1204:	f7fe ffa6 	bl	154 <__aeabi_uldivmod>
		/*
		 * We need to set the timer to interrupt a little bit early to
		 * accommodate the time required by the CPU to fully wake up.
		 */
		z_set_timeout_expiry(ticks -
    1208:	2101      	movs	r1, #1
    120a:	1a38      	subs	r0, r7, r0
    120c:	f005 fe24 	bl	6e58 <z_set_timeout_expiry>
	 * state. We don't want to be scheduled out yet, first we need
	 * to send a notification about leaving the idle state. So,
	 * we lock the scheduler here and unlock just after we have
	 * sent the notification in pm_system_resume().
	 */
	k_sched_lock();
    1210:	f004 f9b6 	bl	5580 <k_sched_lock>
	pm_stats_start();
	/* Enter power state */
	pm_state_notify(true);
    1214:	2001      	movs	r0, #1
    1216:	f7ff ff5d 	bl	10d4 <pm_state_notify>
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    121a:	4b1a      	ldr	r3, [pc, #104]	; (1284 <pm_system_suspend+0xe4>)
 */
static inline void atomic_set_bit(atomic_t *target, int bit)
{
	atomic_val_t mask = ATOMIC_MASK(bit);

	(void)atomic_or(ATOMIC_ELEM(target, bit), mask);
    121c:	096a      	lsrs	r2, r5, #5
    121e:	eb03 0382 	add.w	r3, r3, r2, lsl #2
	atomic_val_t mask = ATOMIC_MASK(bit);
    1222:	2201      	movs	r2, #1
    1224:	f005 011f 	and.w	r1, r5, #31
    1228:	408a      	lsls	r2, r1
    122a:	e8d3 0fef 	ldaex	r0, [r3]
    122e:	4310      	orrs	r0, r2
    1230:	e8c3 0fe1 	stlex	r1, r0, [r3]
    1234:	2900      	cmp	r1, #0
    1236:	d1f8      	bne.n	122a <pm_system_suspend+0x8a>
	if (pm_state_set != NULL) {
    1238:	4b13      	ldr	r3, [pc, #76]	; (1288 <pm_system_suspend+0xe8>)
    123a:	b13b      	cbz	r3, 124c <pm_system_suspend+0xac>
		pm_state_set(info->state, info->substate_id);
    123c:	230c      	movs	r3, #12
    123e:	fb03 f005 	mul.w	r0, r3, r5
    1242:	1833      	adds	r3, r6, r0
    1244:	7859      	ldrb	r1, [r3, #1]
    1246:	5c30      	ldrb	r0, [r6, r0]
    1248:	f7ff ff34 	bl	10b4 <pm_state_set>
	if (atomic_add(&z_cpus_active, 1) == 0) {
		pm_resume_devices();
	}
#endif
	pm_stats_update(z_cpus_pm_state[id].state);
	pm_system_resume();
    124c:	f7ff ff70 	bl	1130 <pm_system_resume>
	k_sched_unlock();
    1250:	f004 f9aa 	bl	55a8 <k_sched_unlock>
	SYS_PORT_TRACING_FUNC_EXIT(pm, system_suspend, ticks,
				   z_cpus_pm_state[id].state);

	return true;
    1254:	2001      	movs	r0, #1
}
    1256:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		info = pm_policy_next_state(id, ticks);
    125a:	4601      	mov	r1, r0
    125c:	4628      	mov	r0, r5
    125e:	f000 f815 	bl	128c <pm_policy_next_state>
		if (info != NULL) {
    1262:	2800      	cmp	r0, #0
    1264:	d0b8      	beq.n	11d8 <pm_system_suspend+0x38>
			z_cpus_pm_state[id] = *info;
    1266:	c807      	ldmia	r0, {r0, r1, r2}
    1268:	4434      	add	r4, r6
    126a:	e884 0007 	stmia.w	r4, {r0, r1, r2}
    126e:	e7b3      	b.n	11d8 <pm_system_suspend+0x38>
    1270:	20000a20 	.word	0x20000a20
    1274:	2000037c 	.word	0x2000037c
    1278:	20000388 	.word	0x20000388
    127c:	000f423f 	.word	0x000f423f
    1280:	000f4240 	.word	0x000f4240
    1284:	2000039c 	.word	0x2000039c
    1288:	000010b5 	.word	0x000010b5

0000128c <pm_policy_next_state>:
	}
}

#ifdef CONFIG_PM_POLICY_DEFAULT
const struct pm_state_info *pm_policy_next_state(uint8_t cpu, int32_t ticks)
{
    128c:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    1290:	b085      	sub	sp, #20
    1292:	460e      	mov	r6, r1
	uint8_t num_cpu_states;
	const struct pm_state_info *cpu_states;

	num_cpu_states = pm_state_cpu_get_all(cpu, &cpu_states);
    1294:	a903      	add	r1, sp, #12
    1296:	f000 f843 	bl	1320 <pm_state_cpu_get_all>
    129a:	f44f 4700 	mov.w	r7, #32768	; 0x8000
    129e:	4604      	mov	r4, r0
    12a0:	f04f 0b00 	mov.w	fp, #0

		min_residency = k_us_to_ticks_ceil32(state->min_residency_us);
		exit_latency = k_us_to_ticks_ceil32(state->exit_latency_us);

		/* skip state if it brings too much latency */
		if ((max_latency_ticks != K_TICKS_FOREVER) &&
    12a4:	4b1b      	ldr	r3, [pc, #108]	; (1314 <pm_policy_next_state+0x88>)
    12a6:	9d03      	ldr	r5, [sp, #12]
    12a8:	f8d3 a000 	ldr.w	sl, [r3]
	for (int16_t i = (int16_t)num_cpu_states - 1; i >= 0; i--) {
    12ac:	1e43      	subs	r3, r0, #1
    12ae:	b21b      	sxth	r3, r3
    12b0:	eb03 0343 	add.w	r3, r3, r3, lsl #1
    12b4:	f8df 8060 	ldr.w	r8, [pc, #96]	; 1318 <pm_policy_next_state+0x8c>
    12b8:	eb05 0583 	add.w	r5, r5, r3, lsl #2
    12bc:	b924      	cbnz	r4, 12c8 <pm_policy_next_state+0x3c>
		    (ticks >= (min_residency + exit_latency))) {
			return state;
		}
	}

	return NULL;
    12be:	46a1      	mov	r9, r4
}
    12c0:	4648      	mov	r0, r9
    12c2:	b005      	add	sp, #20
    12c4:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    12c8:	46c4      	mov	ip, r8
    12ca:	4659      	mov	r1, fp
    12cc:	6868      	ldr	r0, [r5, #4]
    12ce:	2300      	movs	r3, #0
    12d0:	fbe0 c107 	umlal	ip, r1, r0, r7
    12d4:	4a11      	ldr	r2, [pc, #68]	; (131c <pm_policy_next_state+0x90>)
    12d6:	4660      	mov	r0, ip
    12d8:	f7fe ff3c 	bl	154 <__aeabi_uldivmod>
    12dc:	46c4      	mov	ip, r8
    12de:	4659      	mov	r1, fp
    12e0:	9001      	str	r0, [sp, #4]
    12e2:	68a8      	ldr	r0, [r5, #8]
    12e4:	2300      	movs	r3, #0
    12e6:	fbe0 c107 	umlal	ip, r1, r0, r7
    12ea:	4a0c      	ldr	r2, [pc, #48]	; (131c <pm_policy_next_state+0x90>)
    12ec:	4660      	mov	r0, ip
    12ee:	f7fe ff31 	bl	154 <__aeabi_uldivmod>
		if ((max_latency_ticks != K_TICKS_FOREVER) &&
    12f2:	f1ba 3fff 	cmp.w	sl, #4294967295
		const struct pm_state_info *state = &cpu_states[i];
    12f6:	46a9      	mov	r9, r5
		if ((max_latency_ticks != K_TICKS_FOREVER) &&
    12f8:	d001      	beq.n	12fe <pm_policy_next_state+0x72>
    12fa:	4582      	cmp	sl, r0
    12fc:	d905      	bls.n	130a <pm_policy_next_state+0x7e>
		if ((ticks == K_TICKS_FOREVER) ||
    12fe:	1c73      	adds	r3, r6, #1
    1300:	d0de      	beq.n	12c0 <pm_policy_next_state+0x34>
		    (ticks >= (min_residency + exit_latency))) {
    1302:	9b01      	ldr	r3, [sp, #4]
    1304:	4418      	add	r0, r3
		if ((ticks == K_TICKS_FOREVER) ||
    1306:	42b0      	cmp	r0, r6
    1308:	d9da      	bls.n	12c0 <pm_policy_next_state+0x34>
	for (int16_t i = (int16_t)num_cpu_states - 1; i >= 0; i--) {
    130a:	3c01      	subs	r4, #1
    130c:	b2a4      	uxth	r4, r4
    130e:	3d0c      	subs	r5, #12
    1310:	e7d4      	b.n	12bc <pm_policy_next_state+0x30>
    1312:	bf00      	nop
    1314:	20000004 	.word	0x20000004
    1318:	000f423f 	.word	0x000f423f
    131c:	000f4240 	.word	0x000f4240

00001320 <pm_state_cpu_get_all>:
	DT_FOREACH_CHILD_SEP(DT_PATH(cpus), DT_NUM_CPU_POWER_STATES, (,))
};

uint8_t pm_state_cpu_get_all(uint8_t cpu, const struct pm_state_info **states)
{
	if (cpu >= ARRAY_SIZE(cpus_states)) {
    1320:	b908      	cbnz	r0, 1326 <pm_state_cpu_get_all+0x6>
		return 0;
	}

	*states = cpus_states[cpu];
    1322:	4b02      	ldr	r3, [pc, #8]	; (132c <pm_state_cpu_get_all+0xc>)
    1324:	600b      	str	r3, [r1, #0]

	return states_per_cpu[cpu];
}
    1326:	2000      	movs	r0, #0
    1328:	4770      	bx	lr
    132a:	bf00      	nop
    132c:	00007298 	.word	0x00007298

00001330 <nrf_cc3xx_platform_abort_init>:

/** @brief Function to initialize the nrf_cc3xx_platform abort APIs.
 */
void nrf_cc3xx_platform_abort_init(void)
{
	nrf_cc3xx_platform_set_abort(&apis);
    1330:	4801      	ldr	r0, [pc, #4]	; (1338 <nrf_cc3xx_platform_abort_init+0x8>)
    1332:	f004 bc15 	b.w	5b60 <nrf_cc3xx_platform_set_abort>
    1336:	bf00      	nop
    1338:	00007298 	.word	0x00007298

0000133c <mutex_free_platform>:
}


/** @brief Static function to free a mutex
 */
static void mutex_free_platform(nrf_cc3xx_platform_mutex_t *mutex) {
    133c:	b538      	push	{r3, r4, r5, lr}
    /* Ensure that the mutex is valid (not NULL) */
    if (mutex == NULL) {
    133e:	4604      	mov	r4, r0
    1340:	b918      	cbnz	r0, 134a <mutex_free_platform+0xe>
        platform_abort_apis.abort_fn(
    1342:	4b0f      	ldr	r3, [pc, #60]	; (1380 <mutex_free_platform+0x44>)
    1344:	480f      	ldr	r0, [pc, #60]	; (1384 <mutex_free_platform+0x48>)
    1346:	685b      	ldr	r3, [r3, #4]
    1348:	4798      	blx	r3
            "mutex_init called with NULL parameter");
    }

    /* Check if we are freeing a mutex that is atomic */
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ATOMIC ||
    134a:	6861      	ldr	r1, [r4, #4]
    134c:	f5b1 3f68 	cmp.w	r1, #237568	; 0x3a000
    1350:	d00f      	beq.n	1372 <mutex_free_platform+0x36>
    1352:	f5b1 0f68 	cmp.w	r1, #15204352	; 0xe80000
    1356:	d00c      	beq.n	1372 <mutex_free_platform+0x36>
        /*Nothing to free*/
        return;
    }

    /* Check if we are freeing a mutex that isn't initialized */
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID) {
    1358:	4d0b      	ldr	r5, [pc, #44]	; (1388 <mutex_free_platform+0x4c>)
    135a:	42a9      	cmp	r1, r5
    135c:	d009      	beq.n	1372 <mutex_free_platform+0x36>
        /*Nothing to free*/
        return;
    }

    /* Check if the mutex was allocated or being statically defined */
    if ((mutex->flags & NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ALLOCATED) != 0) {
    135e:	f411 6168 	ands.w	r1, r1, #3712	; 0xe80
    1362:	d007      	beq.n	1374 <mutex_free_platform+0x38>
        k_mem_slab_free(&mutex_slab, &mutex->mutex);
    1364:	4621      	mov	r1, r4
    1366:	4809      	ldr	r0, [pc, #36]	; (138c <mutex_free_platform+0x50>)
    1368:	f005 fc61 	bl	6c2e <k_mem_slab_free>
        mutex->mutex = NULL;
    136c:	2300      	movs	r3, #0
    136e:	6023      	str	r3, [r4, #0]
    else {
        memset(mutex->mutex, 0, sizeof(struct k_mutex));
    }

    /* Reset the mutex to invalid state */
    mutex->flags = NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID;
    1370:	6065      	str	r5, [r4, #4]
}
    1372:	bd38      	pop	{r3, r4, r5, pc}
        memset(mutex->mutex, 0, sizeof(struct k_mutex));
    1374:	2214      	movs	r2, #20
    1376:	6820      	ldr	r0, [r4, #0]
    1378:	f004 ff0c 	bl	6194 <memset>
    137c:	e7f8      	b.n	1370 <mutex_free_platform+0x34>
    137e:	bf00      	nop
    1380:	2000017c 	.word	0x2000017c
    1384:	000077a2 	.word	0x000077a2
    1388:	a95c5f2c 	.word	0xa95c5f2c
    138c:	200008a0 	.word	0x200008a0

00001390 <mutex_lock_platform>:


/** @brief Static function to lock a mutex
 */
static int32_t mutex_lock_platform(nrf_cc3xx_platform_mutex_t *mutex) {
    1390:	b508      	push	{r3, lr}
    int ret;
    struct k_mutex * p_mutex;

    /* Ensure that the mutex param is valid (not NULL) */
    if(mutex == NULL) {
    1392:	b360      	cbz	r0, 13ee <mutex_lock_platform+0x5e>
        return NRF_CC3XX_PLATFORM_ERROR_PARAM_NULL;
    }

    switch (mutex->flags) {
    1394:	6843      	ldr	r3, [r0, #4]
    1396:	f5b3 3f68 	cmp.w	r3, #237568	; 0x3a000
    139a:	d00e      	beq.n	13ba <mutex_lock_platform+0x2a>
    139c:	f5b3 0f68 	cmp.w	r3, #15204352	; 0xe80000
    13a0:	d018      	beq.n	13d4 <mutex_lock_platform+0x44>

#endif /* defined(NRF5340_XXAA_APPLICATION) */

    default:
        /* Ensure that the mutex has been initialized */
        if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID) {
    13a2:	4a14      	ldr	r2, [pc, #80]	; (13f4 <mutex_lock_platform+0x64>)
    13a4:	4293      	cmp	r3, r2
    13a6:	d020      	beq.n	13ea <mutex_lock_platform+0x5a>
            return NRF_CC3XX_PLATFORM_ERROR_MUTEX_NOT_INITIALIZED;
        }

        p_mutex = (struct k_mutex *)mutex->mutex;
    13a8:	6800      	ldr	r0, [r0, #0]
		union { struct { uintptr_t lo, hi; } split; k_timeout_t val; } parm1 = { .val = timeout };
		return (int) arch_syscall_invoke3(parm0.x, parm1.split.lo, parm1.split.hi, K_SYSCALL_K_MUTEX_LOCK);
	}
#endif
	compiler_barrier();
	return z_impl_k_mutex_lock(mutex, timeout);
    13aa:	f04f 32ff 	mov.w	r2, #4294967295
    13ae:	f04f 33ff 	mov.w	r3, #4294967295
    13b2:	f003 fddd 	bl	4f70 <z_impl_k_mutex_lock>

        ret = k_mutex_lock(p_mutex, K_FOREVER);
        if (ret == 0) {
    13b6:	b158      	cbz	r0, 13d0 <mutex_lock_platform+0x40>
    13b8:	e015      	b.n	13e6 <mutex_lock_platform+0x56>
	return __atomic_compare_exchange_n(target, &old_value, new_value,
    13ba:	2201      	movs	r2, #1
    13bc:	6803      	ldr	r3, [r0, #0]
    13be:	e8d3 1fef 	ldaex	r1, [r3]
    13c2:	2900      	cmp	r1, #0
    13c4:	d103      	bne.n	13ce <mutex_lock_platform+0x3e>
    13c6:	e8c3 2fe0 	stlex	r0, r2, [r3]
    13ca:	2800      	cmp	r0, #0
    13cc:	d1f7      	bne.n	13be <mutex_lock_platform+0x2e>
                       NRF_CC3XX_PLATFORM_SUCCESS :
    13ce:	d10a      	bne.n	13e6 <mutex_lock_platform+0x56>
            return NRF_CC3XX_PLATFORM_SUCCESS;
    13d0:	2000      	movs	r0, #0
        } else {
            return NRF_CC3XX_PLATFORM_ERROR_MUTEX_FAILED;
        }
    }
}
    13d2:	bd08      	pop	{r3, pc}
        return nrf_mutex_lock(NRF_MUTEX, *((uint8_t *)mutex->mutex)) ?
    13d4:	6803      	ldr	r3, [r0, #0]

#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE bool nrf_mutex_lock(NRF_MUTEX_Type * p_reg, uint8_t mutex)
{
    return (p_reg->MUTEX[mutex] == MUTEX_MUTEX_MUTEX_Unlocked);
    13d6:	4a08      	ldr	r2, [pc, #32]	; (13f8 <mutex_lock_platform+0x68>)
    13d8:	781b      	ldrb	r3, [r3, #0]
    13da:	f503 7380 	add.w	r3, r3, #256	; 0x100
    13de:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
                       NRF_CC3XX_PLATFORM_SUCCESS :
    13e2:	2b00      	cmp	r3, #0
    13e4:	d0f4      	beq.n	13d0 <mutex_lock_platform+0x40>
                       NRF_CC3XX_PLATFORM_SUCCESS :
    13e6:	4805      	ldr	r0, [pc, #20]	; (13fc <mutex_lock_platform+0x6c>)
    13e8:	e7f3      	b.n	13d2 <mutex_lock_platform+0x42>
            return NRF_CC3XX_PLATFORM_ERROR_MUTEX_NOT_INITIALIZED;
    13ea:	4805      	ldr	r0, [pc, #20]	; (1400 <mutex_lock_platform+0x70>)
    13ec:	e7f1      	b.n	13d2 <mutex_lock_platform+0x42>
        return NRF_CC3XX_PLATFORM_ERROR_PARAM_NULL;
    13ee:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    13f2:	e7ee      	b.n	13d2 <mutex_lock_platform+0x42>
    13f4:	a95c5f2c 	.word	0xa95c5f2c
    13f8:	50030000 	.word	0x50030000
    13fc:	ffff8fe9 	.word	0xffff8fe9
    1400:	ffff8fea 	.word	0xffff8fea

00001404 <mutex_unlock_platform>:

/** @brief Static function to unlock a mutex
 */
static int32_t mutex_unlock_platform(nrf_cc3xx_platform_mutex_t *mutex) {
    1404:	b508      	push	{r3, lr}
    struct k_mutex * p_mutex;

    /* Ensure that the mutex param is valid (not NULL) */
    if(mutex == NULL) {
    1406:	b320      	cbz	r0, 1452 <mutex_unlock_platform+0x4e>
        return NRF_CC3XX_PLATFORM_ERROR_PARAM_NULL;
    }

    switch (mutex->flags)
    1408:	6843      	ldr	r3, [r0, #4]
    140a:	f5b3 3f68 	cmp.w	r3, #237568	; 0x3a000
    140e:	d009      	beq.n	1424 <mutex_unlock_platform+0x20>
    1410:	f5b3 0f68 	cmp.w	r3, #15204352	; 0xe80000
    1414:	d013      	beq.n	143e <mutex_unlock_platform+0x3a>

#endif /* defined(NRF5340_XXAA_APPLICATION) */

    default:
        /* Ensure that the mutex has been initialized */
        if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID) {
    1416:	4a11      	ldr	r2, [pc, #68]	; (145c <mutex_unlock_platform+0x58>)
    1418:	4293      	cmp	r3, r2
    141a:	d01d      	beq.n	1458 <mutex_unlock_platform+0x54>
            return NRF_CC3XX_PLATFORM_ERROR_MUTEX_NOT_INITIALIZED;
        }

        p_mutex = (struct k_mutex *)mutex->mutex;
    141c:	6800      	ldr	r0, [r0, #0]
		union { uintptr_t x; struct k_mutex * val; } parm0 = { .val = mutex };
		return (int) arch_syscall_invoke1(parm0.x, K_SYSCALL_K_MUTEX_UNLOCK);
	}
#endif
	compiler_barrier();
	return z_impl_k_mutex_unlock(mutex);
    141e:	f003 fe21 	bl	5064 <z_impl_k_mutex_unlock>
    1422:	e014      	b.n	144e <mutex_unlock_platform+0x4a>
    1424:	2200      	movs	r2, #0
    1426:	6803      	ldr	r3, [r0, #0]
    1428:	e8d3 1fef 	ldaex	r1, [r3]
    142c:	2901      	cmp	r1, #1
    142e:	d103      	bne.n	1438 <mutex_unlock_platform+0x34>
    1430:	e8c3 2fe0 	stlex	r0, r2, [r3]
    1434:	2800      	cmp	r0, #0
    1436:	d1f7      	bne.n	1428 <mutex_unlock_platform+0x24>
                       NRF_CC3XX_PLATFORM_SUCCESS :
    1438:	d009      	beq.n	144e <mutex_unlock_platform+0x4a>
    143a:	4809      	ldr	r0, [pc, #36]	; (1460 <mutex_unlock_platform+0x5c>)

        k_mutex_unlock(p_mutex);
        return NRF_CC3XX_PLATFORM_SUCCESS;
    }
}
    143c:	bd08      	pop	{r3, pc}
}

NRF_STATIC_INLINE void nrf_mutex_unlock(NRF_MUTEX_Type * p_reg, uint8_t mutex)
{
    p_reg->MUTEX[mutex] = MUTEX_MUTEX_MUTEX_Unlocked;
    143e:	2100      	movs	r1, #0
        nrf_mutex_unlock(NRF_MUTEX, *((uint8_t *)mutex->mutex));
    1440:	6803      	ldr	r3, [r0, #0]
    1442:	4a08      	ldr	r2, [pc, #32]	; (1464 <mutex_unlock_platform+0x60>)
    1444:	781b      	ldrb	r3, [r3, #0]
    1446:	f503 7380 	add.w	r3, r3, #256	; 0x100
    144a:	f842 1023 	str.w	r1, [r2, r3, lsl #2]
        return NRF_CC3XX_PLATFORM_SUCCESS;
    144e:	2000      	movs	r0, #0
    1450:	e7f4      	b.n	143c <mutex_unlock_platform+0x38>
        return NRF_CC3XX_PLATFORM_ERROR_PARAM_NULL;
    1452:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    1456:	e7f1      	b.n	143c <mutex_unlock_platform+0x38>
            return NRF_CC3XX_PLATFORM_ERROR_MUTEX_NOT_INITIALIZED;
    1458:	4803      	ldr	r0, [pc, #12]	; (1468 <mutex_unlock_platform+0x64>)
    145a:	e7ef      	b.n	143c <mutex_unlock_platform+0x38>
    145c:	a95c5f2c 	.word	0xa95c5f2c
    1460:	ffff8fe9 	.word	0xffff8fe9
    1464:	50030000 	.word	0x50030000
    1468:	ffff8fea 	.word	0xffff8fea

0000146c <mutex_init_platform>:
static void mutex_init_platform(nrf_cc3xx_platform_mutex_t *mutex) {
    146c:	b510      	push	{r4, lr}
    if (mutex == NULL) {
    146e:	4604      	mov	r4, r0
    1470:	b918      	cbnz	r0, 147a <mutex_init_platform+0xe>
        platform_abort_apis.abort_fn(
    1472:	4b1d      	ldr	r3, [pc, #116]	; (14e8 <mutex_init_platform+0x7c>)
    1474:	481d      	ldr	r0, [pc, #116]	; (14ec <mutex_init_platform+0x80>)
    1476:	685b      	ldr	r3, [r3, #4]
    1478:	4798      	blx	r3
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ATOMIC ||
    147a:	6863      	ldr	r3, [r4, #4]
    147c:	f5b3 3f68 	cmp.w	r3, #237568	; 0x3a000
    1480:	d02f      	beq.n	14e2 <mutex_init_platform+0x76>
    1482:	f5b3 0f68 	cmp.w	r3, #15204352	; 0xe80000
    1486:	d02c      	beq.n	14e2 <mutex_init_platform+0x76>
    if ((mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID && mutex->mutex == NULL) ||
    1488:	4a19      	ldr	r2, [pc, #100]	; (14f0 <mutex_init_platform+0x84>)
    148a:	4293      	cmp	r3, r2
    148c:	d119      	bne.n	14c2 <mutex_init_platform+0x56>
    148e:	6823      	ldr	r3, [r4, #0]
    1490:	bb03      	cbnz	r3, 14d4 <mutex_init_platform+0x68>
        ret = k_mem_slab_alloc(&mutex_slab, &mutex->mutex, K_FOREVER);
    1492:	f04f 32ff 	mov.w	r2, #4294967295
    1496:	f04f 33ff 	mov.w	r3, #4294967295
    149a:	4621      	mov	r1, r4
    149c:	4815      	ldr	r0, [pc, #84]	; (14f4 <mutex_init_platform+0x88>)
    149e:	f003 fc91 	bl	4dc4 <k_mem_slab_alloc>
        if(ret != 0 || mutex->mutex == NULL)
    14a2:	b908      	cbnz	r0, 14a8 <mutex_init_platform+0x3c>
    14a4:	6823      	ldr	r3, [r4, #0]
    14a6:	b91b      	cbnz	r3, 14b0 <mutex_init_platform+0x44>
            platform_abort_apis.abort_fn(
    14a8:	4b0f      	ldr	r3, [pc, #60]	; (14e8 <mutex_init_platform+0x7c>)
    14aa:	4813      	ldr	r0, [pc, #76]	; (14f8 <mutex_init_platform+0x8c>)
    14ac:	685b      	ldr	r3, [r3, #4]
    14ae:	4798      	blx	r3
        memset(mutex->mutex, 0, sizeof(struct k_mutex));
    14b0:	2214      	movs	r2, #20
    14b2:	2100      	movs	r1, #0
    14b4:	6820      	ldr	r0, [r4, #0]
    14b6:	f004 fe6d 	bl	6194 <memset>
        mutex->flags |= NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ALLOCATED;
    14ba:	f44f 6368 	mov.w	r3, #3712	; 0xe80
    14be:	6063      	str	r3, [r4, #4]
    14c0:	e008      	b.n	14d4 <mutex_init_platform+0x68>
    switch(flags){
    14c2:	f5b3 3f68 	cmp.w	r3, #237568	; 0x3a000
    14c6:	d80d      	bhi.n	14e4 <mutex_init_platform+0x78>
    14c8:	2b3a      	cmp	r3, #58	; 0x3a
    14ca:	d003      	beq.n	14d4 <mutex_init_platform+0x68>
    14cc:	f640 62ba 	movw	r2, #3770	; 0xeba
    14d0:	4293      	cmp	r3, r2
    14d2:	d1de      	bne.n	1492 <mutex_init_platform+0x26>
    p_mutex = (struct k_mutex *)mutex->mutex;
    14d4:	6820      	ldr	r0, [r4, #0]
	return z_impl_k_mutex_init(mutex);
    14d6:	f005 fbe8 	bl	6caa <z_impl_k_mutex_init>
    mutex->flags |= NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_VALID;
    14da:	6863      	ldr	r3, [r4, #4]
    14dc:	f043 033a 	orr.w	r3, r3, #58	; 0x3a
    14e0:	6063      	str	r3, [r4, #4]
}
    14e2:	bd10      	pop	{r4, pc}
    switch(flags){
    14e4:	4a05      	ldr	r2, [pc, #20]	; (14fc <mutex_init_platform+0x90>)
    14e6:	e7f3      	b.n	14d0 <mutex_init_platform+0x64>
    14e8:	2000017c 	.word	0x2000017c
    14ec:	000077a2 	.word	0x000077a2
    14f0:	a95c5f2c 	.word	0xa95c5f2c
    14f4:	200008a0 	.word	0x200008a0
    14f8:	000077c8 	.word	0x000077c8
    14fc:	3a00003a 	.word	0x3a00003a

00001500 <nrf_cc3xx_platform_mutex_init>:
};

/** @brief Function to initialize the nrf_cc3xx_platform mutex APIs
 */
void nrf_cc3xx_platform_mutex_init(void)
{
    1500:	b508      	push	{r3, lr}
    k_mem_slab_init(&mutex_slab,
    1502:	4906      	ldr	r1, [pc, #24]	; (151c <nrf_cc3xx_platform_mutex_init+0x1c>)
    1504:	2340      	movs	r3, #64	; 0x40
    1506:	2214      	movs	r2, #20
    1508:	4805      	ldr	r0, [pc, #20]	; (1520 <nrf_cc3xx_platform_mutex_init+0x20>)
    150a:	f005 fb82 	bl	6c12 <k_mem_slab_init>
                mutex_slab_buffer,
                sizeof(struct k_mutex),
                NUM_MUTEXES);

    nrf_cc3xx_platform_set_mutexes(&mutex_apis, &mutexes);
}
    150e:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    nrf_cc3xx_platform_set_mutexes(&mutex_apis, &mutexes);
    1512:	4904      	ldr	r1, [pc, #16]	; (1524 <nrf_cc3xx_platform_mutex_init+0x24>)
    1514:	4804      	ldr	r0, [pc, #16]	; (1528 <nrf_cc3xx_platform_mutex_init+0x28>)
    1516:	f004 bb95 	b.w	5c44 <nrf_cc3xx_platform_set_mutexes>
    151a:	bf00      	nop
    151c:	200003a0 	.word	0x200003a0
    1520:	200008a0 	.word	0x200008a0
    1524:	000072a0 	.word	0x000072a0
    1528:	000072b4 	.word	0x000072b4

0000152c <z_arm_cpu_idle_init>:
 * void z_arm_cpu_idle_init(void);
 */

SECTION_FUNC(TEXT, z_arm_cpu_idle_init)
#if defined(CONFIG_CPU_CORTEX_M)
	ldr	r1, =_SCB_SCR
    152c:	4901      	ldr	r1, [pc, #4]	; (1534 <z_arm_cpu_idle_init+0x8>)
	movs.n	r2, #_SCR_INIT_BITS
    152e:	2210      	movs	r2, #16
	str	r2, [r1]
    1530:	600a      	str	r2, [r1, #0]
#endif
	bx	lr
    1532:	4770      	bx	lr
	ldr	r1, =_SCB_SCR
    1534:	e000ed10 	.word	0xe000ed10

00001538 <arch_cpu_idle>:
	 * before entering low power state.
	 *
	 * Set PRIMASK before configuring BASEPRI to prevent interruption
	 * before wake-up.
	 */
	cpsid	i
    1538:	b672      	cpsid	i

	/*
	 * Set wake-up interrupt priority to the lowest and synchronise to
	 * ensure that this is visible to the WFI instruction.
	 */
	eors.n	r0, r0
    153a:	4040      	eors	r0, r0
	msr	BASEPRI, r0
    153c:	f380 8811 	msr	BASEPRI, r0
	isb
    1540:	f3bf 8f6f 	isb	sy
	 * (i.e. if the caller sets _kernel.idle).
	 */
#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */

	/* Enter low power state */
	_sleep_if_allowed wfi
    1544:	b501      	push	{r0, lr}
    1546:	f7ff fd69 	bl	101c <z_arm_on_enter_cpu_idle>
    154a:	2800      	cmp	r0, #0
    154c:	d002      	beq.n	1554 <_skip_0>
    154e:	f3bf 8f4f 	dsb	sy
    1552:	bf30      	wfi

00001554 <_skip_0>:
    1554:	e8bd 4001 	ldmia.w	sp!, {r0, lr}

	/*
	 * Clear PRIMASK and flush instruction buffer to immediately service
	 * the wake-up interrupt.
	 */
	cpsie	i
    1558:	b662      	cpsie	i
	isb
    155a:	f3bf 8f6f 	isb	sy

	bx	lr
    155e:	4770      	bx	lr

00001560 <arch_cpu_atomic_idle>:

	/*
	 * Lock PRIMASK while sleeping: wfe will still get interrupted by
	 * incoming interrupts but the CPU will not service them right away.
	 */
	cpsid	i
    1560:	b672      	cpsid	i
	cpsie	i
_irq_disabled:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* r1: zero, for setting BASEPRI (needs a register) */
	eors.n	r1, r1
    1562:	4049      	eors	r1, r1

	/* unlock BASEPRI so wfe gets interrupted by incoming interrupts */
	msr	BASEPRI, r1
    1564:	f381 8811 	msr	BASEPRI, r1

	_sleep_if_allowed wfe
    1568:	b501      	push	{r0, lr}
    156a:	f7ff fd57 	bl	101c <z_arm_on_enter_cpu_idle>
    156e:	2800      	cmp	r0, #0
    1570:	d002      	beq.n	1578 <_skip_1>
    1572:	f3bf 8f4f 	dsb	sy
    1576:	bf20      	wfe

00001578 <_skip_1>:
    1578:	e8bd 4001 	ldmia.w	sp!, {r0, lr}

	msr	BASEPRI, r0
    157c:	f380 8811 	msr	BASEPRI, r0
	cpsie	i
    1580:	b662      	cpsie	i
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
	bx	lr
    1582:	4770      	bx	lr

00001584 <arch_irq_enable>:
#define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
#define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)

void arch_irq_enable(unsigned int irq)
{
	NVIC_EnableIRQ((IRQn_Type)irq);
    1584:	b240      	sxtb	r0, r0
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
    1586:	2800      	cmp	r0, #0
    1588:	db07      	blt.n	159a <arch_irq_enable+0x16>
  {
    __COMPILER_BARRIER();
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    158a:	2301      	movs	r3, #1
    158c:	0941      	lsrs	r1, r0, #5
    158e:	4a03      	ldr	r2, [pc, #12]	; (159c <arch_irq_enable+0x18>)
    1590:	f000 001f 	and.w	r0, r0, #31
    1594:	4083      	lsls	r3, r0
    1596:	f842 3021 	str.w	r3, [r2, r1, lsl #2]
}
    159a:	4770      	bx	lr
    159c:	e000e100 	.word	0xe000e100

000015a0 <arch_irq_disable>:

void arch_irq_disable(unsigned int irq)
{
	NVIC_DisableIRQ((IRQn_Type)irq);
    15a0:	b240      	sxtb	r0, r0
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
    15a2:	2800      	cmp	r0, #0
    15a4:	db0c      	blt.n	15c0 <arch_irq_disable+0x20>
  {
    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    15a6:	2201      	movs	r2, #1
    15a8:	4906      	ldr	r1, [pc, #24]	; (15c4 <arch_irq_disable+0x24>)
    15aa:	0943      	lsrs	r3, r0, #5
    15ac:	f000 001f 	and.w	r0, r0, #31
    15b0:	4082      	lsls	r2, r0
    15b2:	3320      	adds	r3, #32
    15b4:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
    15b8:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    15bc:	f3bf 8f6f 	isb	sy
}
    15c0:	4770      	bx	lr
    15c2:	bf00      	nop
    15c4:	e000e100 	.word	0xe000e100

000015c8 <arch_irq_is_enabled>:

int arch_irq_is_enabled(unsigned int irq)
{
	return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq));
    15c8:	4b05      	ldr	r3, [pc, #20]	; (15e0 <arch_irq_is_enabled+0x18>)
    15ca:	0942      	lsrs	r2, r0, #5
    15cc:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
    15d0:	2301      	movs	r3, #1
    15d2:	f000 001f 	and.w	r0, r0, #31
    15d6:	fa03 f000 	lsl.w	r0, r3, r0
}
    15da:	4010      	ands	r0, r2
    15dc:	4770      	bx	lr
    15de:	bf00      	nop
    15e0:	e000e100 	.word	0xe000e100

000015e4 <z_arm_irq_priority_set>:
	 */
	__ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1),
		 "invalid priority %d for %d irq! values must be less than %lu\n",
		 prio - _IRQ_PRIO_OFFSET, irq,
		 BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
	NVIC_SetPriority((IRQn_Type)irq, prio);
    15e4:	b240      	sxtb	r0, r0
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
  if ((int32_t)(IRQn) >= 0)
    15e6:	2800      	cmp	r0, #0
		prio += _IRQ_PRIO_OFFSET;
    15e8:	f101 0101 	add.w	r1, r1, #1
  {
    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    15ec:	bfac      	ite	ge
    15ee:	f100 4060 	addge.w	r0, r0, #3758096384	; 0xe0000000
  }
  else
  {
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    15f2:	4b06      	ldrlt	r3, [pc, #24]	; (160c <z_arm_irq_priority_set+0x28>)
    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    15f4:	ea4f 1141 	mov.w	r1, r1, lsl #5
    15f8:	b2c9      	uxtb	r1, r1
    15fa:	bfab      	itete	ge
    15fc:	f500 4061 	addge.w	r0, r0, #57600	; 0xe100
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1600:	f000 000f 	andlt.w	r0, r0, #15
    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1604:	f880 1300 	strbge.w	r1, [r0, #768]	; 0x300
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1608:	5419      	strblt	r1, [r3, r0]
}
    160a:	4770      	bx	lr
    160c:	e000ed14 	.word	0xe000ed14

00001610 <z_SysNmiOnReset>:
_ASM_FILE_PROLOGUE

GTEXT(z_SysNmiOnReset)

SECTION_FUNC(TEXT, z_SysNmiOnReset)
    wfi
    1610:	bf30      	wfi
    b z_SysNmiOnReset
    1612:	f7ff bffd 	b.w	1610 <z_SysNmiOnReset>
    1616:	bf00      	nop

00001618 <z_arm_prep_c>:

#define VECTOR_ADDRESS ((uintptr_t)_vector_start)

static inline void relocate_vector_table(void)
{
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    1618:	4a0b      	ldr	r2, [pc, #44]	; (1648 <z_arm_prep_c+0x30>)
 *
 * This routine prepares for the execution of and runs C code.
 *
 */
void z_arm_prep_c(void)
{
    161a:	b508      	push	{r3, lr}
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    161c:	4b0b      	ldr	r3, [pc, #44]	; (164c <z_arm_prep_c+0x34>)
    161e:	f022 027f 	bic.w	r2, r2, #127	; 0x7f
    1622:	609a      	str	r2, [r3, #8]
  __ASM volatile ("dsb 0xF":::"memory");
    1624:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    1628:	f3bf 8f6f 	isb	sy
	SCB->CPACR &= (~(CPACR_CP10_Msk | CPACR_CP11_Msk));
    162c:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
    1630:	f422 0270 	bic.w	r2, r2, #15728640	; 0xf00000
    1634:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
	relocate_vector_table();
#if defined(CONFIG_CPU_HAS_FPU)
	z_arm_floating_point_init();
#endif
	z_bss_zero();
    1638:	f003 fb04 	bl	4c44 <z_bss_zero>
	z_data_copy();
    163c:	f004 f8de 	bl	57fc <z_data_copy>
#if ((defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)) && defined(CONFIG_INIT_STACKS))
	z_arm_init_stacks();
#endif
	z_arm_interrupt_init();
    1640:	f000 f9b6 	bl	19b0 <z_arm_interrupt_init>
	z_cstart();
    1644:	f003 fb3e 	bl	4cc4 <z_cstart>
    1648:	00000000 	.word	0x00000000
    164c:	e000ed00 	.word	0xe000ed00

00001650 <arch_swap>:
 * as BASEPRI is not available.
 */
int arch_swap(unsigned int key)
{
	/* store off key and return value */
	_current->arch.basepri = key;
    1650:	4a09      	ldr	r2, [pc, #36]	; (1678 <arch_swap+0x28>)
	_current->arch.swap_return_value = _k_neg_eagain;
    1652:	490a      	ldr	r1, [pc, #40]	; (167c <arch_swap+0x2c>)
	_current->arch.basepri = key;
    1654:	6893      	ldr	r3, [r2, #8]
	_current->arch.swap_return_value = _k_neg_eagain;
    1656:	6809      	ldr	r1, [r1, #0]
	_current->arch.basepri = key;
    1658:	6758      	str	r0, [r3, #116]	; 0x74
	_current->arch.swap_return_value = _k_neg_eagain;
    165a:	6799      	str	r1, [r3, #120]	; 0x78

#if defined(CONFIG_CPU_CORTEX_M)
	/* set pending bit to make sure we will take a PendSV exception */
	SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    165c:	4908      	ldr	r1, [pc, #32]	; (1680 <arch_swap+0x30>)
    165e:	684b      	ldr	r3, [r1, #4]
    1660:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
    1664:	604b      	str	r3, [r1, #4]
    1666:	2300      	movs	r3, #0
    1668:	f383 8811 	msr	BASEPRI, r3
    166c:	f3bf 8f6f 	isb	sy
#endif

	/* Context switch is performed here. Returning implies the
	 * thread has been context-switched-in again.
	 */
	return _current->arch.swap_return_value;
    1670:	6893      	ldr	r3, [r2, #8]
}
    1672:	6f98      	ldr	r0, [r3, #120]	; 0x78
    1674:	4770      	bx	lr
    1676:	bf00      	nop
    1678:	20000a20 	.word	0x20000a20
    167c:	000074b8 	.word	0x000074b8
    1680:	e000ed00 	.word	0xe000ed00

00001684 <z_arm_pendsv>:
    pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_INSTRUMENT_THREAD_SWITCHING */

    /* load _kernel into r1 and current k_thread into r2 */
    ldr r1, =_kernel
    1684:	4913      	ldr	r1, [pc, #76]	; (16d4 <z_arm_pendsv+0x50>)
    ldr r2, [r1, #_kernel_offset_to_current]
    1686:	688a      	ldr	r2, [r1, #8]
    /* Store LSB of LR (EXC_RETURN) to the thread's 'mode' word. */
    strb lr, [r2, #_thread_offset_to_mode_exc_return]
#endif

    /* addr of callee-saved regs in thread in r0 */
    ldr r0, =_thread_offset_to_callee_saved
    1688:	f04f 0030 	mov.w	r0, #48	; 0x30
    add r0, r2
    168c:	4410      	add	r0, r2

    /* save callee-saved + psp in thread */
#if defined(CONFIG_CPU_CORTEX_M)
    mrs ip, PSP
    168e:	f3ef 8c09 	mrs	ip, PSP
    mov r6, r11
    mov r7, ip
    /* store r8-12 */
    stmea r0!, {r3-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    stmia r0, {v1-v8, ip}
    1692:	e880 1ff0 	stmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}

    /* Protect the kernel state while we play with the thread lists */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    1696:	2020      	movs	r0, #32
    msr BASEPRI_MAX, r0
    1698:	f380 8812 	msr	BASEPRI_MAX, r0
    isb /* Make the effect of disabling interrupts be realized immediately */
    169c:	f3bf 8f6f 	isb	sy
     * the new thread is context-switched in since all decisions
     * to pend PendSV have been taken with the current kernel
     * state and this is what we're handling currently.
     */
#if defined(CONFIG_CPU_CORTEX_M)
    ldr v4, =_SCS_ICSR
    16a0:	4f0d      	ldr	r7, [pc, #52]	; (16d8 <z_arm_pendsv+0x54>)
    ldr v3, =_SCS_ICSR_UNPENDSV
    16a2:	f04f 6600 	mov.w	r6, #134217728	; 0x8000000
#endif

    /* _kernel is still in r1 */

    /* fetch the thread to run from the ready queue cache */
    ldr r2, [r1, #_kernel_offset_to_ready_q_cache]
    16a6:	69ca      	ldr	r2, [r1, #28]

    str r2, [r1, #_kernel_offset_to_current]
    16a8:	608a      	str	r2, [r1, #8]
     * has been handled.
     */

    /* _SCS_ICSR is still in v4 and _SCS_ICSR_UNPENDSV in v3 */
#if defined(CONFIG_CPU_CORTEX_M)
    str v3, [v4, #0]
    16aa:	603e      	str	r6, [r7, #0]

    ldr r0, [r4]
    movs.n r3, #0
    str r3, [r4]
#else
    ldr r0, [r2, #_thread_offset_to_basepri]
    16ac:	6f50      	ldr	r0, [r2, #116]	; 0x74
    movs r3, #0
    16ae:	2300      	movs	r3, #0
    str r3, [r2, #_thread_offset_to_basepri]
    16b0:	6753      	str	r3, [r2, #116]	; 0x74
    /* restore r4-r7, go back 9*4 bytes to the start of the stored block */
    subs r0, #36
    ldmia r0!, {r4-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    /* restore BASEPRI for the incoming thread */
    msr BASEPRI, r0
    16b2:	f380 8811 	msr	BASEPRI, r0
    isb

#endif

    /* load callee-saved + psp from thread */
    add r0, r2, #_thread_offset_to_callee_saved
    16b6:	f102 0030 	add.w	r0, r2, #48	; 0x30
    ldmia r0, {v1-v8, ip}
    16ba:	e890 1ff0 	ldmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
    msr PSP, ip
    16be:	f38c 8809 	msr	PSP, ip
#endif

#ifdef CONFIG_BUILTIN_STACK_GUARD
    /* r2 contains k_thread */
    add r0, r2, #0
    16c2:	f102 0000 	add.w	r0, r2, #0
    push {r2, lr}
    16c6:	b504      	push	{r2, lr}
    bl configure_builtin_stack_guard
    16c8:	f004 fcf8 	bl	60bc <configure_builtin_stack_guard>
    pop {r2, lr}
    16cc:	e8bd 4004 	ldmia.w	sp!, {r2, lr}

    /*
     * Cortex-M: return from PendSV exception
     * Cortex-R: return to the caller (z_arm_{exc,int}_exit, or z_arm_svc)
     */
    bx lr
    16d0:	4770      	bx	lr
    16d2:	0000      	.short	0x0000
    ldr r1, =_kernel
    16d4:	20000a20 	.word	0x20000a20
    ldr v4, =_SCS_ICSR
    16d8:	e000ed04 	.word	0xe000ed04

000016dc <z_arm_svc>:
  bne _stack_frame_endif
_stack_frame_msp:
  mrs r0, MSP
_stack_frame_endif:
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    tst lr, #_EXC_RETURN_SPSEL_Msk /* did we come from thread mode ? */
    16dc:	f01e 0f04 	tst.w	lr, #4
    ite eq  /* if zero (equal), came from handler mode */
    16e0:	bf0c      	ite	eq
        mrseq r0, MSP   /* handler mode, stack frame is on MSP */
    16e2:	f3ef 8008 	mrseq	r0, MSP
        mrsne r0, PSP   /* thread mode, stack frame is on PSP */
    16e6:	f3ef 8009 	mrsne	r0, PSP
#endif


    /* Figure out what SVC call number was invoked */

    ldr r1, [r0, #24]   /* grab address of PC from stack frame */
    16ea:	6981      	ldr	r1, [r0, #24]
     */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    subs r1, r1, #2
    ldrb r1, [r1]
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    ldrb r1, [r1, #-2]
    16ec:	f811 1c02 	ldrb.w	r1, [r1, #-2]
#endif
    bne _oops

#endif /* CONFIG_USERSPACE */

    cmp r1, #2
    16f0:	2902      	cmp	r1, #2
    beq _oops
    16f2:	d0ff      	beq.n	16f4 <_oops>

000016f4 <_oops>:
    /* exception return is done in z_arm_int_exit() */
    b z_arm_int_exit
#endif

_oops:
    push {r0, lr}
    16f4:	b501      	push	{r0, lr}
    push {r1, r2}
    push {r4-r11}
    mov  r1, sp /* pointer to _callee_saved_t */
#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
    bl z_do_kernel_oops
    16f6:	f004 fcd2 	bl	609e <z_do_kernel_oops>
     * the MSP to its value prior to entering the function
     */
    add sp, #40
#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
    pop {r0, pc}
    16fa:	bd01      	pop	{r0, pc}

000016fc <arch_new_thread>:

#if defined(CONFIG_CPU_CORTEX_M)
	/* force ARM mode by clearing LSB of address */
	iframe->pc &= 0xfffffffe;
#endif
	iframe->a1 = (uint32_t)entry;
    16fc:	f842 3c20 	str.w	r3, [r2, #-32]
	iframe->a2 = (uint32_t)p1;
    1700:	9b00      	ldr	r3, [sp, #0]
	iframe->pc &= 0xfffffffe;
    1702:	490b      	ldr	r1, [pc, #44]	; (1730 <arch_new_thread+0x34>)
	iframe->a2 = (uint32_t)p1;
    1704:	f842 3c1c 	str.w	r3, [r2, #-28]
	iframe->a3 = (uint32_t)p2;
    1708:	9b01      	ldr	r3, [sp, #4]
	iframe->pc &= 0xfffffffe;
    170a:	f021 0101 	bic.w	r1, r1, #1
	iframe->a3 = (uint32_t)p2;
    170e:	f842 3c18 	str.w	r3, [r2, #-24]
	iframe->a4 = (uint32_t)p3;
    1712:	9b02      	ldr	r3, [sp, #8]
	iframe->pc &= 0xfffffffe;
    1714:	f842 1c08 	str.w	r1, [r2, #-8]
	iframe->a4 = (uint32_t)p3;
    1718:	f842 3c14 	str.w	r3, [r2, #-20]

#if defined(CONFIG_CPU_CORTEX_M)
	iframe->xpsr =
    171c:	f04f 7380 	mov.w	r3, #16777216	; 0x1000000
    1720:	f842 3c04 	str.w	r3, [r2, #-4]
		((uintptr_t)iframe - sizeof(struct __fpu_sf));
	memset(iframe, 0, sizeof(struct __fpu_sf));
#endif

	thread->callee_saved.psp = (uint32_t)iframe;
	thread->arch.basepri = 0;
    1724:	2300      	movs	r3, #0
	iframe = Z_STACK_PTR_TO_FRAME(struct __basic_sf, stack_ptr);
    1726:	3a20      	subs	r2, #32
	thread->callee_saved.psp = (uint32_t)iframe;
    1728:	6502      	str	r2, [r0, #80]	; 0x50
	thread->arch.basepri = 0;
    172a:	6743      	str	r3, [r0, #116]	; 0x74
#endif
	/*
	 * initial values in all other registers/thread entries are
	 * irrelevant.
	 */
}
    172c:	4770      	bx	lr
    172e:	bf00      	nop
    1730:	00005e05 	.word	0x00005e05

00001734 <arch_switch_to_main_thread>:
void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr,
				k_thread_entry_t _main)
{
	z_arm_prepare_switch_to_main();

	_current = main_thread;
    1734:	4b08      	ldr	r3, [pc, #32]	; (1758 <arch_switch_to_main_thread+0x24>)
    1736:	6098      	str	r0, [r3, #8]
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
  // without main extensions, the non-secure PSPLIM is RAZ/WI
  (void)ProcStackPtrLimit;
#else
  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
    1738:	6e43      	ldr	r3, [r0, #100]	; 0x64
    173a:	f383 880b 	msr	PSPLIM, r3

	/*
	 * Set PSP to the highest address of the main stack
	 * before enabling interrupts and jumping to main.
	 */
	__asm__ volatile (
    173e:	4610      	mov	r0, r2
    1740:	f381 8809 	msr	PSP, r1
    1744:	2100      	movs	r1, #0
    1746:	b663      	cpsie	if
    1748:	f381 8811 	msr	BASEPRI, r1
    174c:	f3bf 8f6f 	isb	sy
    1750:	2200      	movs	r2, #0
    1752:	2300      	movs	r3, #0
    1754:	f004 fb56 	bl	5e04 <z_thread_entry>
	:
	: "r" (_main), "r" (stack_ptr)
	: "r0" /* not to be overwritten by msr PSP, %1 */
	);

	CODE_UNREACHABLE;
    1758:	20000a20 	.word	0x20000a20

0000175c <_isr_wrapper>:
 *
 */
SECTION_FUNC(TEXT, _isr_wrapper)

#if defined(CONFIG_CPU_CORTEX_M)
	push {r0,lr}		/* r0, lr are now the first items on the stack */
    175c:	b501      	push	{r0, lr}
	 * Disable interrupts to prevent nesting while exiting idle state. This
	 * is only necessary for the Cortex-M because it is the only ARM
	 * architecture variant that automatically enables interrupts when
	 * entering an ISR.
	 */
	cpsid i  /* PRIMASK = 1 */
    175e:	b672      	cpsid	i
#endif

	/* is this a wakeup from idle ? */
	ldr r2, =_kernel
    1760:	4a0b      	ldr	r2, [pc, #44]	; (1790 <_isr_wrapper+0x34>)
	/* requested idle duration, in ticks */
	ldr r0, [r2, #_kernel_offset_to_idle]
    1762:	6990      	ldr	r0, [r2, #24]
	cmp r0, #0
    1764:	2800      	cmp	r0, #0
	str r1, [r2, #_kernel_offset_to_idle]
	bl z_pm_save_idle_exit
_idle_state_cleared:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	ittt ne
    1766:	bf1e      	ittt	ne
	movne	r1, #0
    1768:	2100      	movne	r1, #0
		/* clear kernel idle state */
		strne	r1, [r2, #_kernel_offset_to_idle]
    176a:	6191      	strne	r1, [r2, #24]
		blne	z_pm_save_idle_exit
    176c:	f005 fa8e 	blne	6c8c <z_pm_save_idle_exit>
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
	cpsie i		/* re-enable interrupts (PRIMASK = 0) */
    1770:	b662      	cpsie	i
#endif

#endif /* CONFIG_PM */

#if defined(CONFIG_CPU_CORTEX_M)
	mrs r0, IPSR	/* get exception number */
    1772:	f3ef 8005 	mrs	r0, IPSR
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r1, =16
	subs r0, r1	/* get IRQ number */
	lsls r0, #3	/* table is 8-byte wide */
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	sub r0, r0, #16	/* get IRQ number */
    1776:	f1a0 0010 	sub.w	r0, r0, #16
	lsl r0, r0, #3	/* table is 8-byte wide */
    177a:	ea4f 00c0 	mov.w	r0, r0, lsl #3
	lsl r1, r1, #3
	cmp r0, r1
	bge spurious_continue
#endif /* !CONFIG_CPU_CORTEX_M */

	ldr r1, =_sw_isr_table
    177e:	4905      	ldr	r1, [pc, #20]	; (1794 <_isr_wrapper+0x38>)
	add r1, r1, r0	/* table entry: ISRs must have their MSB set to stay
    1780:	4401      	add	r1, r0
			 * in thumb mode */

	ldm r1!,{r0,r3}	/* arg in r0, ISR in r3 */
    1782:	c909      	ldmia	r1!, {r0, r3}
	blx r3		/* call ISR */
    1784:	4798      	blx	r3

#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	pop {r0, r3}
	mov lr, r3
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	pop {r0, lr}
    1786:	e8bd 4001 	ldmia.w	sp!, {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

	/* Use 'bx' instead of 'b' because 'bx' can jump further, and use
	 * 'bx' instead of 'blx' because exception return is done in
	 * z_arm_int_exit() */
	ldr r1, =z_arm_int_exit
    178a:	4903      	ldr	r1, [pc, #12]	; (1798 <_isr_wrapper+0x3c>)
	bx r1
    178c:	4708      	bx	r1
    178e:	0000      	.short	0x0000
	ldr r2, =_kernel
    1790:	20000a20 	.word	0x20000a20
	ldr r1, =_sw_isr_table
    1794:	00006fb8 	.word	0x00006fb8
	ldr r1, =z_arm_int_exit
    1798:	0000179d 	.word	0x0000179d

0000179c <z_arm_exc_exit>:
 */

SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_exc_exit)

#ifdef CONFIG_PREEMPT_ENABLED
	ldr r3, =_kernel
    179c:	4b04      	ldr	r3, [pc, #16]	; (17b0 <_EXIT_EXC+0x2>)

	ldr r1, [r3, #_kernel_offset_to_current]
    179e:	6899      	ldr	r1, [r3, #8]
	ldr r0, [r3, #_kernel_offset_to_ready_q_cache]
    17a0:	69d8      	ldr	r0, [r3, #28]
	cmp r0, r1
    17a2:	4288      	cmp	r0, r1
	beq _EXIT_EXC
    17a4:	d003      	beq.n	17ae <_EXIT_EXC>

	/* context switch required, pend the PendSV exception */
	ldr r1, =_SCS_ICSR
    17a6:	4903      	ldr	r1, [pc, #12]	; (17b4 <_EXIT_EXC+0x6>)
	ldr r2, =_SCS_ICSR_PENDSV
    17a8:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
	str r2, [r1]
    17ac:	600a      	str	r2, [r1, #0]

000017ae <_EXIT_EXC>:
#else
	pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_STACK_SENTINEL */

	bx lr
    17ae:	4770      	bx	lr
	ldr r3, =_kernel
    17b0:	20000a20 	.word	0x20000a20
	ldr r1, =_SCS_ICSR
    17b4:	e000ed04 	.word	0xe000ed04

000017b8 <usage_fault.constprop.0>:
	uint32_t reason = K_ERR_CPU_EXCEPTION;

	PR_FAULT_INFO("***** USAGE FAULT *****");

	/* bits are sticky: they stack and must be reset */
	if ((SCB->CFSR & SCB_CFSR_DIVBYZERO_Msk) != 0) {
    17b8:	4b08      	ldr	r3, [pc, #32]	; (17dc <usage_fault.constprop.0+0x24>)
    17ba:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Division by zero");
	}
	if ((SCB->CFSR & SCB_CFSR_UNALIGNED_Msk) != 0) {
    17bc:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Unaligned memory access");
	}
#if defined(CONFIG_ARMV8_M_MAINLINE)
	if ((SCB->CFSR & SCB_CFSR_STKOF_Msk) != 0) {
    17be:	6a98      	ldr	r0, [r3, #40]	; 0x28
		 */
		reason = K_ERR_STACK_CHK_FAIL;
#endif /* CONFIG_BUILTIN_STACK_GUARD */
	}
#endif /* CONFIG_ARMV8_M_MAINLINE */
	if ((SCB->CFSR & SCB_CFSR_NOCP_Msk) != 0) {
    17c0:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  No coprocessor instructions");
	}
	if ((SCB->CFSR & SCB_CFSR_INVPC_Msk) != 0) {
    17c2:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Illegal load of EXC_RETURN into PC");
	}
	if ((SCB->CFSR & SCB_CFSR_INVSTATE_Msk) != 0) {
    17c4:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Illegal use of the EPSR");
	}
	if ((SCB->CFSR & SCB_CFSR_UNDEFINSTR_Msk) != 0) {
    17c6:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Attempt to execute undefined instruction");
	}

	/* clear UFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    17c8:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_STKOF_Msk) != 0) {
    17ca:	f3c0 5000 	ubfx	r0, r0, #20, #1
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    17ce:	ea6f 4202 	mvn.w	r2, r2, lsl #16
    17d2:	ea6f 4212 	mvn.w	r2, r2, lsr #16

	return reason;
}
    17d6:	0040      	lsls	r0, r0, #1
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    17d8:	629a      	str	r2, [r3, #40]	; 0x28
}
    17da:	4770      	bx	lr
    17dc:	e000ed00 	.word	0xe000ed00

000017e0 <bus_fault.constprop.0>:
	if (SCB->CFSR & SCB_CFSR_STKERR_Msk) {
    17e0:	4b0d      	ldr	r3, [pc, #52]	; (1818 <bus_fault.constprop.0+0x38>)
    17e2:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if (SCB->CFSR & SCB_CFSR_UNSTKERR_Msk) {
    17e4:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if (SCB->CFSR & SCB_CFSR_PRECISERR_Msk) {
    17e6:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    17e8:	0592      	lsls	r2, r2, #22
    17ea:	d508      	bpl.n	17fe <bus_fault.constprop.0+0x1e>
		STORE_xFAR(bfar, SCB->BFAR);
    17ec:	6b9a      	ldr	r2, [r3, #56]	; 0x38
		if ((SCB->CFSR & SCB_CFSR_BFARVALID_Msk) != 0) {
    17ee:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    17f0:	0412      	lsls	r2, r2, #16
    17f2:	d504      	bpl.n	17fe <bus_fault.constprop.0+0x1e>
			if (from_hard_fault != 0) {
    17f4:	b118      	cbz	r0, 17fe <bus_fault.constprop.0+0x1e>
				SCB->CFSR &= ~SCB_CFSR_BFARVALID_Msk;
    17f6:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    17f8:	f422 4200 	bic.w	r2, r2, #32768	; 0x8000
    17fc:	629a      	str	r2, [r3, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf, true);
    17fe:	2000      	movs	r0, #0
	if (SCB->CFSR & SCB_CFSR_IMPRECISERR_Msk) {
    1800:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_IBUSERR_Msk) != 0) {
    1802:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    1804:	05d2      	lsls	r2, r2, #23
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
    1806:	4a04      	ldr	r2, [pc, #16]	; (1818 <bus_fault.constprop.0+0x38>)
	} else if (SCB->CFSR & SCB_CFSR_LSPERR_Msk) {
    1808:	bf58      	it	pl
    180a:	6a9b      	ldrpl	r3, [r3, #40]	; 0x28
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
    180c:	6a93      	ldr	r3, [r2, #40]	; 0x28
    180e:	f443 437f 	orr.w	r3, r3, #65280	; 0xff00
    1812:	6293      	str	r3, [r2, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf, true);
    1814:	7008      	strb	r0, [r1, #0]
}
    1816:	4770      	bx	lr
    1818:	e000ed00 	.word	0xe000ed00

0000181c <mem_manage_fault.constprop.0>:
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
    181c:	4b12      	ldr	r3, [pc, #72]	; (1868 <mem_manage_fault.constprop.0+0x4c>)
    181e:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_MUNSTKERR_Msk) != 0) {
    1820:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_DACCVIOL_Msk) != 0) {
    1822:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    1824:	0792      	lsls	r2, r2, #30
    1826:	d508      	bpl.n	183a <mem_manage_fault.constprop.0+0x1e>
		uint32_t temp = SCB->MMFAR;
    1828:	6b5a      	ldr	r2, [r3, #52]	; 0x34
		if ((SCB->CFSR & SCB_CFSR_MMARVALID_Msk) != 0) {
    182a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    182c:	0612      	lsls	r2, r2, #24
    182e:	d504      	bpl.n	183a <mem_manage_fault.constprop.0+0x1e>
			if (from_hard_fault != 0) {
    1830:	b118      	cbz	r0, 183a <mem_manage_fault.constprop.0+0x1e>
				SCB->CFSR &= ~SCB_CFSR_MMARVALID_Msk;
    1832:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    1834:	f022 0280 	bic.w	r2, r2, #128	; 0x80
    1838:	629a      	str	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_IACCVIOL_Msk) != 0) {
    183a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    183c:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) ||
    183e:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    1840:	06d0      	lsls	r0, r2, #27
	*recoverable = memory_fault_recoverable(esf, true);
    1842:	f04f 0000 	mov.w	r0, #0
		(SCB->CFSR & SCB_CFSR_DACCVIOL_Msk)) {
    1846:	bf58      	it	pl
    1848:	6a9b      	ldrpl	r3, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    184a:	4b07      	ldr	r3, [pc, #28]	; (1868 <mem_manage_fault.constprop.0+0x4c>)
    184c:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    184e:	0692      	lsls	r2, r2, #26
		SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTPENDED_Msk;
    1850:	bf42      	ittt	mi
    1852:	6a5a      	ldrmi	r2, [r3, #36]	; 0x24
    1854:	f422 5200 	bicmi.w	r2, r2, #8192	; 0x2000
    1858:	625a      	strmi	r2, [r3, #36]	; 0x24
	SCB->CFSR |= SCB_CFSR_MEMFAULTSR_Msk;
    185a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    185c:	f042 02ff 	orr.w	r2, r2, #255	; 0xff
    1860:	629a      	str	r2, [r3, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf, true);
    1862:	7008      	strb	r0, [r1, #0]
}
    1864:	4770      	bx	lr
    1866:	bf00      	nop
    1868:	e000ed00 	.word	0xe000ed00

0000186c <z_arm_fault>:
 * @param callee_regs Callee-saved registers (R4-R11, PSP)
 *
 */
void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return,
	_callee_saved_t *callee_regs)
{
    186c:	b570      	push	{r4, r5, r6, lr}
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    186e:	4b44      	ldr	r3, [pc, #272]	; (1980 <z_arm_fault+0x114>)
{
    1870:	4606      	mov	r6, r0
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    1872:	685b      	ldr	r3, [r3, #4]
    1874:	2500      	movs	r5, #0
{
    1876:	b08a      	sub	sp, #40	; 0x28
    1878:	f3c3 0308 	ubfx	r3, r3, #0, #9
    187c:	f385 8811 	msr	BASEPRI, r5
    1880:	f3bf 8f6f 	isb	sy
	if ((exc_return & EXC_RETURN_INDICATOR_PREFIX) !=
    1884:	f002 407f 	and.w	r0, r2, #4278190080	; 0xff000000
    1888:	f1b0 4f7f 	cmp.w	r0, #4278190080	; 0xff000000
    188c:	d111      	bne.n	18b2 <z_arm_fault+0x46>
	if ((exc_return & EXC_RETURN_MODE_THREAD) &&
    188e:	f002 000c 	and.w	r0, r2, #12
    1892:	2808      	cmp	r0, #8
    1894:	d00d      	beq.n	18b2 <z_arm_fault+0x46>
		if (exc_return & EXC_RETURN_MODE_THREAD) {
    1896:	0710      	lsls	r0, r2, #28
			ptr_esf =  (z_arch_esf_t *)psp;
    1898:	bf4c      	ite	mi
    189a:	460e      	movmi	r6, r1
			*nested_exc = true;
    189c:	2501      	movpl	r5, #1
	*recoverable = false;
    189e:	2200      	movs	r2, #0
	switch (fault) {
    18a0:	3b03      	subs	r3, #3
	*recoverable = false;
    18a2:	f88d 2007 	strb.w	r2, [sp, #7]
	switch (fault) {
    18a6:	2b03      	cmp	r3, #3
    18a8:	d805      	bhi.n	18b6 <z_arm_fault+0x4a>
    18aa:	e8df f003 	tbb	[pc, r3]
    18ae:	5c1e      	.short	0x5c1e
    18b0:	5960      	.short	0x5960
		return NULL;
    18b2:	462e      	mov	r6, r5
    18b4:	e7f3      	b.n	189e <z_arm_fault+0x32>
    18b6:	2400      	movs	r4, #0
#ifdef CONFIG_DEBUG_COREDUMP
	z_arm_coredump_fault_sp = POINTER_TO_UINT(esf);
#endif

	reason = fault_handle(esf, fault, &recoverable);
	if (recoverable) {
    18b8:	f89d 3007 	ldrb.w	r3, [sp, #7]
    18bc:	b99b      	cbnz	r3, 18e6 <z_arm_fault+0x7a>
		return;
	}

	/* Copy ESF */
#if !defined(CONFIG_EXTRA_EXCEPTION_INFO)
	memcpy(&esf_copy, esf, sizeof(z_arch_esf_t));
    18be:	2220      	movs	r2, #32
    18c0:	4631      	mov	r1, r6
    18c2:	a802      	add	r0, sp, #8
    18c4:	f004 fc5b 	bl	617e <memcpy>
	/* Overwrite stacked IPSR to mark a nested exception,
	 * or a return to Thread mode. Note that this may be
	 * required, if the retrieved ESF contents are invalid
	 * due to, for instance, a stacking error.
	 */
	if (nested_exc) {
    18c8:	9b09      	ldr	r3, [sp, #36]	; 0x24
    18ca:	2d00      	cmp	r5, #0
    18cc:	d053      	beq.n	1976 <z_arm_fault+0x10a>
		if ((esf_copy.basic.xpsr & IPSR_ISR_Msk) == 0) {
    18ce:	f3c3 0208 	ubfx	r2, r3, #0, #9
    18d2:	b922      	cbnz	r2, 18de <z_arm_fault+0x72>
			esf_copy.basic.xpsr |= IPSR_ISR_Msk;
    18d4:	ea6f 2353 	mvn.w	r3, r3, lsr #9
    18d8:	ea6f 2343 	mvn.w	r3, r3, lsl #9
		}
	} else {
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    18dc:	9309      	str	r3, [sp, #36]	; 0x24
	}

	z_arm_fatal_error(reason, &esf_copy);
    18de:	4620      	mov	r0, r4
    18e0:	a902      	add	r1, sp, #8
    18e2:	f004 fbda 	bl	609a <z_arm_fatal_error>
}
    18e6:	b00a      	add	sp, #40	; 0x28
    18e8:	bd70      	pop	{r4, r5, r6, pc}
	if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk) != 0) {
    18ea:	4b25      	ldr	r3, [pc, #148]	; (1980 <z_arm_fault+0x114>)
    18ec:	6ada      	ldr	r2, [r3, #44]	; 0x2c
    18ee:	0791      	lsls	r1, r2, #30
    18f0:	d4e1      	bmi.n	18b6 <z_arm_fault+0x4a>
	} else if ((SCB->HFSR & SCB_HFSR_DEBUGEVT_Msk) != 0) {
    18f2:	6ada      	ldr	r2, [r3, #44]	; 0x2c
    18f4:	2a00      	cmp	r2, #0
    18f6:	dbde      	blt.n	18b6 <z_arm_fault+0x4a>
	} else if ((SCB->HFSR & SCB_HFSR_FORCED_Msk) != 0) {
    18f8:	6ada      	ldr	r2, [r3, #44]	; 0x2c
    18fa:	0052      	lsls	r2, r2, #1
    18fc:	d5db      	bpl.n	18b6 <z_arm_fault+0x4a>
	SCB->CCR |= SCB_CCR_BFHFNMIGN_Msk;
    18fe:	695a      	ldr	r2, [r3, #20]
	uint16_t *ret_addr = (uint16_t *)esf->basic.pc;
    1900:	69b1      	ldr	r1, [r6, #24]
	SCB->CCR |= SCB_CCR_BFHFNMIGN_Msk;
    1902:	f442 7280 	orr.w	r2, r2, #256	; 0x100
    1906:	615a      	str	r2, [r3, #20]
  __ASM volatile ("dsb 0xF":::"memory");
    1908:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    190c:	f3bf 8f6f 	isb	sy
	SCB->CCR &= ~SCB_CCR_BFHFNMIGN_Msk;
    1910:	695a      	ldr	r2, [r3, #20]
	uint16_t fault_insn = *(ret_addr - 1);
    1912:	f831 1c02 	ldrh.w	r1, [r1, #-2]
	SCB->CCR &= ~SCB_CCR_BFHFNMIGN_Msk;
    1916:	f422 7280 	bic.w	r2, r2, #256	; 0x100
    191a:	615a      	str	r2, [r3, #20]
  __ASM volatile ("dsb 0xF":::"memory");
    191c:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    1920:	f3bf 8f6f 	isb	sy
	if (((fault_insn & 0xff00) == _SVC_OPCODE) &&
    1924:	f64d 7202 	movw	r2, #57090	; 0xdf02
    1928:	4291      	cmp	r1, r2
    192a:	d009      	beq.n	1940 <z_arm_fault+0xd4>
		} else if ((SCB->CFSR & SCB_CFSR_MEMFAULTSR_Msk) != 0) {
    192c:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    192e:	b2d2      	uxtb	r2, r2
    1930:	b142      	cbz	r2, 1944 <z_arm_fault+0xd8>
			reason = mem_manage_fault(esf, 1, recoverable);
    1932:	2001      	movs	r0, #1
    1934:	f10d 0107 	add.w	r1, sp, #7
		reason = mem_manage_fault(esf, 0, recoverable);
    1938:	f7ff ff70 	bl	181c <mem_manage_fault.constprop.0>
		reason = usage_fault(esf);
    193c:	4604      	mov	r4, r0
		break;
    193e:	e7bb      	b.n	18b8 <z_arm_fault+0x4c>
			reason = esf->basic.r0;
    1940:	6834      	ldr	r4, [r6, #0]
    1942:	e7b9      	b.n	18b8 <z_arm_fault+0x4c>
		} else if ((SCB->CFSR & SCB_CFSR_BUSFAULTSR_Msk) != 0) {
    1944:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    1946:	f412 4f7f 	tst.w	r2, #65280	; 0xff00
    194a:	d005      	beq.n	1958 <z_arm_fault+0xec>
			reason = bus_fault(esf, 1, recoverable);
    194c:	2001      	movs	r0, #1
    194e:	f10d 0107 	add.w	r1, sp, #7
		reason = bus_fault(esf, 0, recoverable);
    1952:	f7ff ff45 	bl	17e0 <bus_fault.constprop.0>
    1956:	e7f1      	b.n	193c <z_arm_fault+0xd0>
		} else if ((SCB->CFSR & SCB_CFSR_USGFAULTSR_Msk) != 0) {
    1958:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    195a:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
    195e:	d3aa      	bcc.n	18b6 <z_arm_fault+0x4a>
		reason = usage_fault(esf);
    1960:	f7ff ff2a 	bl	17b8 <usage_fault.constprop.0>
    1964:	e7ea      	b.n	193c <z_arm_fault+0xd0>
		reason = mem_manage_fault(esf, 0, recoverable);
    1966:	2000      	movs	r0, #0
    1968:	f10d 0107 	add.w	r1, sp, #7
    196c:	e7e4      	b.n	1938 <z_arm_fault+0xcc>
		reason = bus_fault(esf, 0, recoverable);
    196e:	2000      	movs	r0, #0
    1970:	f10d 0107 	add.w	r1, sp, #7
    1974:	e7ed      	b.n	1952 <z_arm_fault+0xe6>
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    1976:	f423 73ff 	bic.w	r3, r3, #510	; 0x1fe
    197a:	f023 0301 	bic.w	r3, r3, #1
    197e:	e7ad      	b.n	18dc <z_arm_fault+0x70>
    1980:	e000ed00 	.word	0xe000ed00

00001984 <z_arm_fault_init>:
 */
void z_arm_fault_init(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
    1984:	4b04      	ldr	r3, [pc, #16]	; (1998 <z_arm_fault_init+0x14>)
    1986:	695a      	ldr	r2, [r3, #20]
    1988:	f042 0210 	orr.w	r2, r2, #16
    198c:	615a      	str	r2, [r3, #20]
	 *
	 * For Non-Secure Firmware this could allow the Non-Secure Main
	 * Stack to attempt to descend into secure region, in which case a
	 * Secure Hard Fault will occur and we can track the fault from there.
	 */
	SCB->CCR |= SCB_CCR_STKOFHFNMIGN_Msk;
    198e:	695a      	ldr	r2, [r3, #20]
    1990:	f442 6280 	orr.w	r2, r2, #1024	; 0x400
    1994:	615a      	str	r2, [r3, #20]
#endif /* CONFIG_BUILTIN_STACK_GUARD */
#ifdef CONFIG_TRAP_UNALIGNED_ACCESS
	SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif /* CONFIG_TRAP_UNALIGNED_ACCESS */
}
    1996:	4770      	bx	lr
    1998:	e000ed00 	.word	0xe000ed00

0000199c <z_arm_bus_fault>:
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_exc_spurious)

	mrs r0, MSP
    199c:	f3ef 8008 	mrs	r0, MSP
	mrs r1, PSP
    19a0:	f3ef 8109 	mrs	r1, PSP
	push {r0, lr}
    19a4:	b501      	push	{r0, lr}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	push {r4-r11}
#endif
	mov  r3, sp /* pointer to _callee_saved_t */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
	mov r2, lr /* EXC_RETURN */
    19a6:	4672      	mov	r2, lr
	bl z_arm_fault
    19a8:	f7ff ff60 	bl	186c <z_arm_fault>
	 * in this routine. Therefore, we can just reset
	 * the MSP to its value prior to entering the function
	 */
	add sp, #40
#endif
	pop {r0, pc}
    19ac:	bd01      	pop	{r0, pc}
    19ae:	bf00      	nop

000019b0 <z_arm_interrupt_init>:
 *
 */

void z_arm_interrupt_init(void)
{
	int irq = 0;
    19b0:	2300      	movs	r3, #0
    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    19b2:	2120      	movs	r1, #32
    19b4:	4803      	ldr	r0, [pc, #12]	; (19c4 <z_arm_interrupt_init+0x14>)
    19b6:	18c2      	adds	r2, r0, r3

	for (; irq < CONFIG_NUM_IRQS; irq++) {
    19b8:	3301      	adds	r3, #1
    19ba:	2b45      	cmp	r3, #69	; 0x45
    19bc:	f882 1300 	strb.w	r1, [r2, #768]	; 0x300
    19c0:	d1f9      	bne.n	19b6 <z_arm_interrupt_init+0x6>
		NVIC_SetPriority((IRQn_Type)irq, _IRQ_PRIO_OFFSET);
	}
}
    19c2:	4770      	bx	lr
    19c4:	e000e100 	.word	0xe000e100

000019c8 <__start>:
    strb r0, [r1]
#endif /* CONFIG_DEBUG_THREAD_INFO */

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
    /* Reset CONTROL register */
    movs.n r0, #0
    19c8:	2000      	movs	r0, #0
    msr CONTROL, r0
    19ca:	f380 8814 	msr	CONTROL, r0
    isb
    19ce:	f3bf 8f6f 	isb	sy
#if defined(CONFIG_CPU_CORTEX_M_HAS_SPLIM)
    /* Clear SPLIM registers */
    movs.n r0, #0
    19d2:	2000      	movs	r0, #0
    msr MSPLIM, r0
    19d4:	f380 880a 	msr	MSPLIM, r0
    msr PSPLIM, r0
    19d8:	f380 880b 	msr	PSPLIM, r0
#if defined(CONFIG_PM_S2RAM)
    bl arch_pm_s2ram_resume
#endif /* CONFIG_PM_S2RAM */

#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
    bl z_arm_platform_init
    19dc:	f7ff fb78 	bl	10d0 <z_arm_platform_init>
#endif

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
#if defined(CONFIG_CPU_HAS_ARM_MPU)
    /* Disable MPU */
    movs.n r0, #0
    19e0:	2000      	movs	r0, #0
    ldr r1, =_SCS_MPU_CTRL
    19e2:	490e      	ldr	r1, [pc, #56]	; (1a1c <__start+0x54>)
    str r0, [r1]
    19e4:	6008      	str	r0, [r1, #0]
    dsb
    19e6:	f3bf 8f4f 	dsb	sy
#endif /* CONFIG_CPU_HAS_ARM_MPU */
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    19ea:	480d      	ldr	r0, [pc, #52]	; (1a20 <__start+0x58>)
    msr msp, r0
    19ec:	f380 8808 	msr	MSP, r0

    /* Initialize core architecture registers and system blocks */
    bl z_arm_init_arch_hw_at_boot
    19f0:	f000 f83e 	bl	1a70 <z_arm_init_arch_hw_at_boot>

    /* lock interrupts: will get unlocked when switch to main task */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    19f4:	2020      	movs	r0, #32
    msr BASEPRI, r0
    19f6:	f380 8811 	msr	BASEPRI, r0

    /*
     * Set PSP and use it to boot without using MSP, so that it
     * gets set to z_interrupt_stacks during initialization.
     */
    ldr r0, =z_interrupt_stacks
    19fa:	480a      	ldr	r0, [pc, #40]	; (1a24 <__start+0x5c>)
    ldr r1, =CONFIG_ISR_STACK_SIZE + MPU_GUARD_ALIGN_AND_SIZE
    19fc:	f44f 6100 	mov.w	r1, #2048	; 0x800
    adds r0, r0, r1
    1a00:	1840      	adds	r0, r0, r1
    msr PSP, r0
    1a02:	f380 8809 	msr	PSP, r0
    mrs r0, CONTROL
    1a06:	f3ef 8014 	mrs	r0, CONTROL
    movs r1, #2
    1a0a:	2102      	movs	r1, #2
    orrs r0, r1 /* CONTROL_SPSEL_Msk */
    1a0c:	4308      	orrs	r0, r1
    msr CONTROL, r0
    1a0e:	f380 8814 	msr	CONTROL, r0
    /*
     * When changing the stack pointer, software must use an ISB instruction
     * immediately after the MSR instruction. This ensures that instructions
     * after the ISB instruction execute using the new stack pointer.
     */
    isb
    1a12:	f3bf 8f6f 	isb	sy
    /*
     * 'bl' jumps the furthest of the branch instructions that are
     * supported on all platforms. So it is used when jumping to z_arm_prep_c
     * (even though we do not intend to return).
     */
    bl z_arm_prep_c
    1a16:	f7ff fdff 	bl	1618 <z_arm_prep_c>
    1a1a:	0000      	.short	0x0000
    ldr r1, =_SCS_MPU_CTRL
    1a1c:	e000ed94 	.word	0xe000ed94
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    1a20:	20001980 	.word	0x20001980
    ldr r0, =z_interrupt_stacks
    1a24:	20000c40 	.word	0x20000c40

00001a28 <sys_arch_reboot>:
  __ASM volatile ("dsb 0xF":::"memory");
    1a28:	f3bf 8f4f 	dsb	sy
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
  __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                       buffered write are completed before reset */
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    1a2c:	4905      	ldr	r1, [pc, #20]	; (1a44 <sys_arch_reboot+0x1c>)
    1a2e:	4b06      	ldr	r3, [pc, #24]	; (1a48 <sys_arch_reboot+0x20>)
    1a30:	68ca      	ldr	r2, [r1, #12]
    1a32:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    1a36:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    1a38:	60cb      	str	r3, [r1, #12]
    1a3a:	f3bf 8f4f 	dsb	sy
                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
  __DSB();                                                          /* Ensure completion of memory access */

  for(;;)                                                           /* wait until reset */
  {
    __NOP();
    1a3e:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    1a40:	e7fd      	b.n	1a3e <sys_arch_reboot+0x16>
    1a42:	bf00      	nop
    1a44:	e000ed00 	.word	0xe000ed00
    1a48:	05fa0004 	.word	0x05fa0004

00001a4c <z_arm_clear_arm_mpu_config>:
	int i;

	int num_regions =
		((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos);

	for (i = 0; i < num_regions; i++) {
    1a4c:	2300      	movs	r3, #0
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
{
  mpu->RNR = rnr;
  mpu->RLAR = 0U;
    1a4e:	4618      	mov	r0, r3
		((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos);
    1a50:	4906      	ldr	r1, [pc, #24]	; (1a6c <z_arm_clear_arm_mpu_config+0x20>)
    1a52:	f8d1 2090 	ldr.w	r2, [r1, #144]	; 0x90
	int num_regions =
    1a56:	f3c2 2207 	ubfx	r2, r2, #8, #8
	for (i = 0; i < num_regions; i++) {
    1a5a:	4293      	cmp	r3, r2
    1a5c:	db00      	blt.n	1a60 <z_arm_clear_arm_mpu_config+0x14>
		ARM_MPU_ClrRegion(i);
	}
}
    1a5e:	4770      	bx	lr
  mpu->RNR = rnr;
    1a60:	f8c1 3098 	str.w	r3, [r1, #152]	; 0x98
  mpu->RLAR = 0U;
    1a64:	f8c1 00a0 	str.w	r0, [r1, #160]	; 0xa0
	for (i = 0; i < num_regions; i++) {
    1a68:	3301      	adds	r3, #1
    1a6a:	e7f6      	b.n	1a5a <z_arm_clear_arm_mpu_config+0xe>
    1a6c:	e000ed00 	.word	0xe000ed00

00001a70 <z_arm_init_arch_hw_at_boot>:
 * This routine resets Cortex-M system control block
 * components and core registers.
 *
 */
void z_arm_init_arch_hw_at_boot(void)
{
    1a70:	b510      	push	{r4, lr}
  __ASM volatile ("cpsid i" : : : "memory");
    1a72:	b672      	cpsid	i
  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
    1a74:	2400      	movs	r4, #0
    1a76:	f384 8813 	msr	FAULTMASK, r4

	/* Initialize System Control Block components */

#if defined(CONFIG_CPU_HAS_ARM_MPU) || defined(CONFIG_CPU_HAS_NXP_MPU)
	/* Clear MPU region configuration */
	z_arm_clear_arm_mpu_config();
    1a7a:	f7ff ffe7 	bl	1a4c <z_arm_clear_arm_mpu_config>
    1a7e:	4623      	mov	r3, r4
#endif /* CONFIG_CPU_HAS_ARM_MPU */

	/* Disable NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
		NVIC->ICER[i] = 0xFFFFFFFF;
    1a80:	f04f 30ff 	mov.w	r0, #4294967295
    1a84:	4a0c      	ldr	r2, [pc, #48]	; (1ab8 <z_arm_init_arch_hw_at_boot+0x48>)
    1a86:	f103 0120 	add.w	r1, r3, #32
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
    1a8a:	3301      	adds	r3, #1
    1a8c:	2b10      	cmp	r3, #16
		NVIC->ICER[i] = 0xFFFFFFFF;
    1a8e:	f842 0021 	str.w	r0, [r2, r1, lsl #2]
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
    1a92:	d1f8      	bne.n	1a86 <z_arm_init_arch_hw_at_boot+0x16>
    1a94:	2300      	movs	r3, #0
	}
	/* Clear pending NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) {
		NVIC->ICPR[i] = 0xFFFFFFFF;
    1a96:	f04f 30ff 	mov.w	r0, #4294967295
    1a9a:	4a07      	ldr	r2, [pc, #28]	; (1ab8 <z_arm_init_arch_hw_at_boot+0x48>)
    1a9c:	f103 0160 	add.w	r1, r3, #96	; 0x60
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) {
    1aa0:	3301      	adds	r3, #1
    1aa2:	2b10      	cmp	r3, #16
		NVIC->ICPR[i] = 0xFFFFFFFF;
    1aa4:	f842 0021 	str.w	r0, [r2, r1, lsl #2]
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) {
    1aa8:	d1f8      	bne.n	1a9c <z_arm_init_arch_hw_at_boot+0x2c>
  __ASM volatile ("cpsie i" : : : "memory");
    1aaa:	b662      	cpsie	i
  __ASM volatile ("dsb 0xF":::"memory");
    1aac:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    1ab0:	f3bf 8f6f 	isb	sy
	/* Restore Interrupts */
	__enable_irq();

	__DSB();
	__ISB();
}
    1ab4:	bd10      	pop	{r4, pc}
    1ab6:	bf00      	nop
    1ab8:	e000e100 	.word	0xe000e100

00001abc <z_impl_k_thread_abort>:
#include <zephyr/wait_q.h>
#include <zephyr/sys/__assert.h>

void z_impl_k_thread_abort(k_tid_t thread)
{
	if (_current == thread) {
    1abc:	4b08      	ldr	r3, [pc, #32]	; (1ae0 <z_impl_k_thread_abort+0x24>)
    1abe:	689b      	ldr	r3, [r3, #8]
    1ac0:	4283      	cmp	r3, r0
    1ac2:	d10b      	bne.n	1adc <z_impl_k_thread_abort+0x20>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    1ac4:	f3ef 8305 	mrs	r3, IPSR
		if (arch_is_in_isr()) {
    1ac8:	b143      	cbz	r3, 1adc <z_impl_k_thread_abort+0x20>
			 * should no longer run after we return, so
			 * Trigger PendSV, in case we are in one of the
			 * situations where the isr check is true but there
			 * is not an implicit scheduler invocation.
			 */
			SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    1aca:	4b06      	ldr	r3, [pc, #24]	; (1ae4 <z_impl_k_thread_abort+0x28>)
    1acc:	685a      	ldr	r2, [r3, #4]
    1ace:	f042 5280 	orr.w	r2, r2, #268435456	; 0x10000000
    1ad2:	605a      	str	r2, [r3, #4]
			/* Clear any system calls that may be pending
			 * as they have a higher priority than the PendSV
			 * handler and will check the stack of the thread
			 * being aborted.
			 */
			SCB->SHCSR &= ~SCB_SHCSR_SVCALLPENDED_Msk;
    1ad4:	6a5a      	ldr	r2, [r3, #36]	; 0x24
    1ad6:	f422 4200 	bic.w	r2, r2, #32768	; 0x8000
    1ada:	625a      	str	r2, [r3, #36]	; 0x24
		}
	}

	z_thread_abort(thread);
    1adc:	f003 be2e 	b.w	573c <z_thread_abort>
    1ae0:	20000a20 	.word	0x20000a20
    1ae4:	e000ed00 	.word	0xe000ed00

00001ae8 <z_arm_configure_static_mpu_regions>:
 *
 * For some MPU architectures, such as the unmodified ARMv8-M MPU,
 * the function must execute with MPU enabled.
 */
void z_arm_configure_static_mpu_regions(void)
{
    1ae8:	b51f      	push	{r0, r1, r2, r3, r4, lr}
	 * into account the unused SRAM area, as well.
	 */
#ifdef CONFIG_AARCH32_ARMV8_R
	arm_core_mpu_disable();
#endif
	arm_core_mpu_configure_static_mpu_regions(static_regions,
    1aea:	4c09      	ldr	r4, [pc, #36]	; (1b10 <z_arm_configure_static_mpu_regions+0x28>)
    1aec:	4a09      	ldr	r2, [pc, #36]	; (1b14 <z_arm_configure_static_mpu_regions+0x2c>)
    1aee:	4623      	mov	r3, r4
    1af0:	2101      	movs	r1, #1
    1af2:	4809      	ldr	r0, [pc, #36]	; (1b18 <z_arm_configure_static_mpu_regions+0x30>)
    1af4:	f000 f8ea 	bl	1ccc <arm_core_mpu_configure_static_mpu_regions>
	/* Define a constant array of z_arm_mpu_partition objects that holds the
	 * boundaries of the areas, inside which dynamic region programming
	 * is allowed. The information is passed to the underlying driver at
	 * initialization.
	 */
	const struct z_arm_mpu_partition dyn_region_areas[] = {
    1af8:	2300      	movs	r3, #0
    1afa:	9303      	str	r3, [sp, #12]
		{
		.start = _MPU_DYNAMIC_REGIONS_AREA_START,
    1afc:	4b07      	ldr	r3, [pc, #28]	; (1b1c <z_arm_configure_static_mpu_regions+0x34>)
		.size =  _MPU_DYNAMIC_REGIONS_AREA_SIZE,
		}
	};

	arm_core_mpu_mark_areas_for_dynamic_regions(dyn_region_areas,
    1afe:	2101      	movs	r1, #1
		.size =  _MPU_DYNAMIC_REGIONS_AREA_SIZE,
    1b00:	1ae4      	subs	r4, r4, r3
	arm_core_mpu_mark_areas_for_dynamic_regions(dyn_region_areas,
    1b02:	a801      	add	r0, sp, #4
	const struct z_arm_mpu_partition dyn_region_areas[] = {
    1b04:	9301      	str	r3, [sp, #4]
    1b06:	9402      	str	r4, [sp, #8]
	arm_core_mpu_mark_areas_for_dynamic_regions(dyn_region_areas,
    1b08:	f000 f8ea 	bl	1ce0 <arm_core_mpu_mark_areas_for_dynamic_regions>
		ARRAY_SIZE(dyn_region_areas));
#endif /* CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS */
}
    1b0c:	b004      	add	sp, #16
    1b0e:	bd10      	pop	{r4, pc}
    1b10:	20070000 	.word	0x20070000
    1b14:	20000000 	.word	0x20000000
    1b18:	000072c4 	.word	0x000072c4
    1b1c:	20000240 	.word	0x20000240

00001b20 <region_init>:
 * Note:
 *   The caller must provide a valid region index.
 */
static void region_init(const uint32_t index,
	const struct arm_mpu_region *region_conf)
{
    1b20:	b510      	push	{r4, lr}
	mpu_set_region(
		/* RNR */
		index,
		/* RBAR */
		(region_conf->base & MPU_RBAR_BASE_Msk)
		| (region_conf->attr.rbar &
    1b22:	7a0c      	ldrb	r4, [r1, #8]
		(region_conf->base & MPU_RBAR_BASE_Msk)
    1b24:	680b      	ldr	r3, [r1, #0]
		| (region_conf->attr.rbar &
    1b26:	f004 021f 	and.w	r2, r4, #31
		(region_conf->base & MPU_RBAR_BASE_Msk)
    1b2a:	f023 031f 	bic.w	r3, r3, #31
		| (region_conf->attr.rbar &
    1b2e:	431a      	orrs	r2, r3
			(MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)),
		/* RLAR */
		(region_conf->attr.r_limit & MPU_RLAR_LIMIT_Msk)
    1b30:	68cb      	ldr	r3, [r1, #12]
		| ((region_conf->attr.mair_idx << MPU_RLAR_AttrIndx_Pos)
    1b32:	0964      	lsrs	r4, r4, #5
		(region_conf->attr.r_limit & MPU_RLAR_LIMIT_Msk)
    1b34:	f023 031f 	bic.w	r3, r3, #31
	MPU->RNR = rnr;
    1b38:	4905      	ldr	r1, [pc, #20]	; (1b50 <region_init+0x30>)
		| ((region_conf->attr.mair_idx << MPU_RLAR_AttrIndx_Pos)
    1b3a:	ea43 0344 	orr.w	r3, r3, r4, lsl #1
			& MPU_RLAR_AttrIndx_Msk)
		| MPU_RLAR_EN_Msk
    1b3e:	f043 0301 	orr.w	r3, r3, #1
	MPU->RNR = rnr;
    1b42:	f8c1 0098 	str.w	r0, [r1, #152]	; 0x98
	MPU->RBAR = rbar;
    1b46:	f8c1 209c 	str.w	r2, [r1, #156]	; 0x9c
	MPU->RLAR = rlar;
    1b4a:	f8c1 30a0 	str.w	r3, [r1, #160]	; 0xa0
	);

	LOG_DBG("[%d] 0x%08x 0x%08x 0x%08x 0x%08x",
			index, region_conf->base, region_conf->attr.rbar,
			region_conf->attr.mair_idx, region_conf->attr.r_limit);
}
    1b4e:	bd10      	pop	{r4, pc}
    1b50:	e000ed00 	.word	0xe000ed00

00001b54 <mpu_configure_regions_and_partition.constprop.0>:
 * sanity check of the memory regions to be programmed.
 *
 * The function performs a full partition of the background memory
 * area, effectively, leaving no space in this area uncovered by MPU.
 */
static int mpu_configure_regions_and_partition(const struct z_arm_mpu_partition
    1b54:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    1b58:	460f      	mov	r7, r1
    1b5a:	4614      	mov	r4, r2
	bool do_sanity_check)
{
	int i;
	int reg_index = start_reg_index;

	for (i = 0; i < regions_num; i++) {
    1b5c:	4606      	mov	r6, r0
    1b5e:	f04f 0800 	mov.w	r8, #0
	MPU->RNR = rnr;
    1b62:	4d4e      	ldr	r5, [pc, #312]	; (1c9c <mpu_configure_regions_and_partition.constprop.0+0x148>)
static int mpu_configure_regions_and_partition(const struct z_arm_mpu_partition
    1b64:	b085      	sub	sp, #20
	for (i = 0; i < regions_num; i++) {
    1b66:	45b8      	cmp	r8, r7
    1b68:	f280 8094 	bge.w	1c94 <mpu_configure_regions_and_partition.constprop.0+0x140>
		if (regions[i].size == 0U) {
    1b6c:	f8d6 9004 	ldr.w	r9, [r6, #4]
    1b70:	f1b9 0f00 	cmp.w	r9, #0
    1b74:	d036      	beq.n	1be4 <mpu_configure_regions_and_partition.constprop.0+0x90>
		&&
    1b76:	f1b9 0f1f 	cmp.w	r9, #31
    1b7a:	f240 8089 	bls.w	1c90 <mpu_configure_regions_and_partition.constprop.0+0x13c>
		&&
    1b7e:	f019 0f1f 	tst.w	r9, #31
    1b82:	f040 8085 	bne.w	1c90 <mpu_configure_regions_and_partition.constprop.0+0x13c>
		((part->start &
    1b86:	f8d6 a000 	ldr.w	sl, [r6]
		&&
    1b8a:	f01a 0f1f 	tst.w	sl, #31
    1b8e:	d17f      	bne.n	1c90 <mpu_configure_regions_and_partition.constprop.0+0x13c>
	uint32_t region_start_addr = arm_cmse_mpu_region_get(start);
    1b90:	4650      	mov	r0, sl
    1b92:	f004 fa97 	bl	60c4 <arm_cmse_mpu_region_get>
    1b96:	4683      	mov	fp, r0
	uint32_t region_end_addr = arm_cmse_mpu_region_get(start + size - 1);
    1b98:	eb09 000a 	add.w	r0, r9, sl
    1b9c:	3801      	subs	r0, #1
    1b9e:	f004 fa91 	bl	60c4 <arm_cmse_mpu_region_get>
	if (region_start_addr == region_end_addr) {
    1ba2:	4583      	cmp	fp, r0
    1ba4:	d174      	bne.n	1c90 <mpu_configure_regions_and_partition.constprop.0+0x13c>
		 * inside which the new region will be configured.
		 */
		int u_reg_index =
			get_region_index(regions[i].start, regions[i].size);

		if ((u_reg_index == -EINVAL) ||
    1ba6:	f11b 0f16 	cmn.w	fp, #22
    1baa:	d071      	beq.n	1c90 <mpu_configure_regions_and_partition.constprop.0+0x13c>
    1bac:	455c      	cmp	r4, fp
    1bae:	dd6f      	ble.n	1c90 <mpu_configure_regions_and_partition.constprop.0+0x13c>
	MPU->RNR = rnr;
    1bb0:	f8c5 b098 	str.w	fp, [r5, #152]	; 0x98
	return MPU->RBAR;
    1bb4:	f8d5 109c 	ldr.w	r1, [r5, #156]	; 0x9c
	MPU->RNR = rnr;
    1bb8:	f8c5 b098 	str.w	fp, [r5, #152]	; 0x98
	return MPU->RLAR;
    1bbc:	f8d5 30a0 	ldr.w	r3, [r5, #160]	; 0xa0
	return mpu_get_rbar() & MPU_RBAR_BASE_Msk;
    1bc0:	f021 011f 	bic.w	r1, r1, #31
	return (mpu_get_rlar() & MPU_RLAR_LIMIT_Msk) | (~MPU_RLAR_LIMIT_Msk);
    1bc4:	f043 0a1f 	orr.w	sl, r3, #31
		 * The new memory region is to be placed inside the underlying
		 * region, possibly splitting the underlying region into two.
		 */
		uint32_t u_reg_base = mpu_region_get_base(u_reg_index);
		uint32_t u_reg_last = mpu_region_get_last_addr(u_reg_index);
		uint32_t reg_last = regions[i].start + regions[i].size - 1;
    1bc8:	e9d6 3200 	ldrd	r3, r2, [r6]
    1bcc:	441a      	add	r2, r3

		if ((regions[i].start == u_reg_base) &&
    1bce:	4299      	cmp	r1, r3
		uint32_t reg_last = regions[i].start + regions[i].size - 1;
    1bd0:	f102 39ff 	add.w	r9, r2, #4294967295
		if ((regions[i].start == u_reg_base) &&
    1bd4:	d11e      	bne.n	1c14 <mpu_configure_regions_and_partition.constprop.0+0xc0>
    1bd6:	45ca      	cmp	sl, r9
    1bd8:	d108      	bne.n	1bec <mpu_configure_regions_and_partition.constprop.0+0x98>
			 * underlying region. In this case we simply
			 * update the partition attributes of the
			 * underlying region with those of the new
			 * region.
			 */
			mpu_configure_region(u_reg_index, &regions[i]);
    1bda:	4631      	mov	r1, r6
    1bdc:	fa5f f08b 	uxtb.w	r0, fp
    1be0:	f004 fa79 	bl	60d6 <mpu_configure_region>
	for (i = 0; i < regions_num; i++) {
    1be4:	f108 0801 	add.w	r8, r8, #1
    1be8:	360c      	adds	r6, #12
    1bea:	e7bc      	b.n	1b66 <mpu_configure_regions_and_partition.constprop.0+0x12>
			 */
			mpu_region_set_base(u_reg_index,
				regions[i].start + regions[i].size);

			reg_index =
				mpu_configure_region(reg_index, &regions[i]);
    1bec:	4631      	mov	r1, r6
	MPU->RNR = rnr;
    1bee:	f8c5 b098 	str.w	fp, [r5, #152]	; 0x98
	return MPU->RBAR;
    1bf2:	f8d5 309c 	ldr.w	r3, [r5, #156]	; 0x9c
		     | (base & MPU_RBAR_BASE_Msk));
    1bf6:	f022 021f 	bic.w	r2, r2, #31
	mpu_set_rbar((mpu_get_rbar() & (~MPU_RBAR_BASE_Msk))
    1bfa:	f003 031f 	and.w	r3, r3, #31
		     | (base & MPU_RBAR_BASE_Msk));
    1bfe:	4313      	orrs	r3, r2
	MPU->RBAR = rbar;
    1c00:	f8c5 309c 	str.w	r3, [r5, #156]	; 0x9c
				mpu_configure_region(reg_index, &regions[i]);
    1c04:	b2e0      	uxtb	r0, r4
			 */
			mpu_region_set_limit(u_reg_index,
				regions[i].start - 1);

			reg_index =
				mpu_configure_region(reg_index, &regions[i]);
    1c06:	f004 fa66 	bl	60d6 <mpu_configure_region>

			if (reg_index == -EINVAL) {
    1c0a:	f110 0f16 	cmn.w	r0, #22
    1c0e:	d03f      	beq.n	1c90 <mpu_configure_regions_and_partition.constprop.0+0x13c>

			if (reg_index == -EINVAL) {
				return reg_index;
			}

			reg_index++;
    1c10:	1c44      	adds	r4, r0, #1
    1c12:	e7e7      	b.n	1be4 <mpu_configure_regions_and_partition.constprop.0+0x90>
	MPU->RNR = rnr;
    1c14:	f8c5 b098 	str.w	fp, [r5, #152]	; 0x98
	return MPU->RLAR;
    1c18:	f8d5 20a0 	ldr.w	r2, [r5, #160]	; 0xa0
				regions[i].start - 1);
    1c1c:	3b01      	subs	r3, #1
		     | (limit & MPU_RLAR_LIMIT_Msk));
    1c1e:	f023 031f 	bic.w	r3, r3, #31
	mpu_set_rlar((mpu_get_rlar() & (~MPU_RLAR_LIMIT_Msk))
    1c22:	f002 021f 	and.w	r2, r2, #31
		     | (limit & MPU_RLAR_LIMIT_Msk));
    1c26:	4313      	orrs	r3, r2
		} else if (reg_last == u_reg_last) {
    1c28:	45ca      	cmp	sl, r9
				mpu_configure_region(reg_index, &regions[i]);
    1c2a:	4631      	mov	r1, r6
				mpu_configure_region(reg_index, &regions[i]);
    1c2c:	b2e0      	uxtb	r0, r4
	MPU->RLAR = rlar;
    1c2e:	f8c5 30a0 	str.w	r3, [r5, #160]	; 0xa0
		} else if (reg_last == u_reg_last) {
    1c32:	d0e8      	beq.n	1c06 <mpu_configure_regions_and_partition.constprop.0+0xb2>
				mpu_configure_region(reg_index, &regions[i]);
    1c34:	f004 fa4f 	bl	60d6 <mpu_configure_region>
			if (reg_index == -EINVAL) {
    1c38:	f110 0f16 	cmn.w	r0, #22
    1c3c:	d028      	beq.n	1c90 <mpu_configure_regions_and_partition.constprop.0+0x13c>
	MPU->RNR = rnr;
    1c3e:	f8c5 b098 	str.w	fp, [r5, #152]	; 0x98
	return MPU->RBAR;
    1c42:	f8d5 209c 	ldr.w	r2, [r5, #156]	; 0x9c
	attr->rbar = mpu_get_rbar() &
    1c46:	f89d 3008 	ldrb.w	r3, [sp, #8]
			REGION_LIMIT_ADDR((regions[i].start +
    1c4a:	f10a 3aff 	add.w	sl, sl, #4294967295
	attr->rbar = mpu_get_rbar() &
    1c4e:	f362 0304 	bfi	r3, r2, #0, #5
    1c52:	f88d 3008 	strb.w	r3, [sp, #8]
	return MPU->RLAR;
    1c56:	f8d5 30a0 	ldr.w	r3, [r5, #160]	; 0xa0
	attr->mair_idx = (mpu_get_rlar() & MPU_RLAR_AttrIndx_Msk) >>
    1c5a:	f89d 2008 	ldrb.w	r2, [sp, #8]
    1c5e:	085b      	lsrs	r3, r3, #1
    1c60:	f363 1247 	bfi	r2, r3, #5, #3
    1c64:	f88d 2008 	strb.w	r2, [sp, #8]
			fill_region.base = regions[i].start +
    1c68:	e9d6 3200 	ldrd	r3, r2, [r6]
    1c6c:	4413      	add	r3, r2
    1c6e:	9300      	str	r3, [sp, #0]
			REGION_LIMIT_ADDR((regions[i].start +
    1c70:	f023 031f 	bic.w	r3, r3, #31
			reg_index++;
    1c74:	1c41      	adds	r1, r0, #1
			REGION_LIMIT_ADDR((regions[i].start +
    1c76:	4453      	add	r3, sl
    1c78:	eba3 0309 	sub.w	r3, r3, r9
    1c7c:	b2c8      	uxtb	r0, r1
    1c7e:	f023 031f 	bic.w	r3, r3, #31

static int region_allocate_and_init(const uint8_t index,
	const struct arm_mpu_region *region_conf)
{
	/* Attempt to allocate new region index. */
	if (index > (get_num_regions() - 1U)) {
    1c82:	2807      	cmp	r0, #7
			fill_region.attr.r_limit =
    1c84:	9303      	str	r3, [sp, #12]
    1c86:	d803      	bhi.n	1c90 <mpu_configure_regions_and_partition.constprop.0+0x13c>
	}

	LOG_DBG("Program MPU region at index 0x%x", index);

	/* Program region */
	region_init(index, region_conf);
    1c88:	4669      	mov	r1, sp
    1c8a:	f7ff ff49 	bl	1b20 <region_init>
    1c8e:	e7bf      	b.n	1c10 <mpu_configure_regions_and_partition.constprop.0+0xbc>
			return -EINVAL;
    1c90:	f06f 0415 	mvn.w	r4, #21
		}
	}

	return reg_index;
}
    1c94:	4620      	mov	r0, r4
    1c96:	b005      	add	sp, #20
    1c98:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    1c9c:	e000ed00 	.word	0xe000ed00

00001ca0 <arm_core_mpu_enable>:
	 * background region for privileged software access if desired.
	 */
#if defined(CONFIG_MPU_DISABLE_BACKGROUND_MAP)
	MPU->CTRL = MPU_CTRL_ENABLE_Msk;
#else
	MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
    1ca0:	2205      	movs	r2, #5
    1ca2:	4b04      	ldr	r3, [pc, #16]	; (1cb4 <arm_core_mpu_enable+0x14>)
    1ca4:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
  __ASM volatile ("dsb 0xF":::"memory");
    1ca8:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    1cac:	f3bf 8f6f 	isb	sy
#endif

	/* Make sure that all the registers are set before proceeding */
	__DSB();
	__ISB();
}
    1cb0:	4770      	bx	lr
    1cb2:	bf00      	nop
    1cb4:	e000ed00 	.word	0xe000ed00

00001cb8 <arm_core_mpu_disable>:
  __ASM volatile ("dmb 0xF":::"memory");
    1cb8:	f3bf 8f5f 	dmb	sy
{
	/* Force any outstanding transfers to complete before disabling MPU */
	__DMB();

	/* Disable MPU */
	MPU->CTRL = 0;
    1cbc:	2200      	movs	r2, #0
    1cbe:	4b02      	ldr	r3, [pc, #8]	; (1cc8 <arm_core_mpu_disable+0x10>)
    1cc0:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
}
    1cc4:	4770      	bx	lr
    1cc6:	bf00      	nop
    1cc8:	e000ed00 	.word	0xe000ed00

00001ccc <arm_core_mpu_configure_static_mpu_regions>:
 * @brief configure fixed (static) MPU regions.
 */
void arm_core_mpu_configure_static_mpu_regions(const struct z_arm_mpu_partition
	*static_regions, const uint8_t regions_num,
	const uint32_t background_area_start, const uint32_t background_area_end)
{
    1ccc:	b510      	push	{r4, lr}
static int mpu_configure_static_mpu_regions(const struct z_arm_mpu_partition
	static_regions[], const uint8_t regions_num,
	const uint32_t background_area_base,
	const uint32_t background_area_end)
{
	int mpu_reg_index = static_regions_num;
    1cce:	4c03      	ldr	r4, [pc, #12]	; (1cdc <arm_core_mpu_configure_static_mpu_regions+0x10>)
	 * given boundaries.
	 */
	ARG_UNUSED(background_area_base);
	ARG_UNUSED(background_area_end);

	mpu_reg_index = mpu_configure_regions_and_partition(static_regions,
    1cd0:	7822      	ldrb	r2, [r4, #0]
    1cd2:	f7ff ff3f 	bl	1b54 <mpu_configure_regions_and_partition.constprop.0>
		regions_num, mpu_reg_index, true);

	static_regions_num = mpu_reg_index;
    1cd6:	7020      	strb	r0, [r4, #0]
					       background_area_start, background_area_end) == -EINVAL) {

		__ASSERT(0, "Configuring %u static MPU regions failed\n",
			regions_num);
	}
}
    1cd8:	bd10      	pop	{r4, pc}
    1cda:	bf00      	nop
    1cdc:	20000c33 	.word	0x20000c33

00001ce0 <arm_core_mpu_mark_areas_for_dynamic_regions>:
 * @brief mark memory areas for dynamic region configuration
 */
void arm_core_mpu_mark_areas_for_dynamic_regions(
	const struct z_arm_mpu_partition dyn_region_areas[],
	const uint8_t dyn_region_areas_num)
{
    1ce0:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    1ce4:	4d29      	ldr	r5, [pc, #164]	; (1d8c <arm_core_mpu_mark_areas_for_dynamic_regions+0xac>)
    1ce6:	468a      	mov	sl, r1

/* This internal function marks and stores the configuration of memory areas
 * where dynamic region programming is allowed. Return zero on success, or
 * -EINVAL on error.
 */
static int mpu_mark_areas_for_dynamic_regions(
    1ce8:	4606      	mov	r6, r0
{
	/* In ARMv8-M architecture we need to store the index values
	 * and the default configuration of the MPU regions, inside
	 * which dynamic memory regions may be programmed at run-time.
	 */
	for (int i = 0; i < dyn_region_areas_num; i++) {
    1cea:	f04f 0800 	mov.w	r8, #0
    1cee:	46ab      	mov	fp, r5
	MPU->RNR = rnr;
    1cf0:	4f27      	ldr	r7, [pc, #156]	; (1d90 <arm_core_mpu_mark_areas_for_dynamic_regions+0xb0>)
	for (int i = 0; i < dyn_region_areas_num; i++) {
    1cf2:	45d0      	cmp	r8, sl
    1cf4:	da1b      	bge.n	1d2e <arm_core_mpu_mark_areas_for_dynamic_regions+0x4e>
		if (dyn_region_areas[i].size == 0U) {
    1cf6:	f8d6 9004 	ldr.w	r9, [r6, #4]
    1cfa:	f1b9 0f00 	cmp.w	r9, #0
    1cfe:	d03f      	beq.n	1d80 <arm_core_mpu_mark_areas_for_dynamic_regions+0xa0>
		}
		/* Non-empty area */

		/* Retrieve HW MPU region index */
		dyn_reg_info[i].index =
			get_region_index(dyn_region_areas[i].start,
    1d00:	6831      	ldr	r1, [r6, #0]
	uint32_t region_start_addr = arm_cmse_mpu_region_get(start);
    1d02:	4608      	mov	r0, r1
    1d04:	9101      	str	r1, [sp, #4]
    1d06:	f004 f9dd 	bl	60c4 <arm_cmse_mpu_region_get>
	uint32_t region_end_addr = arm_cmse_mpu_region_get(start + size - 1);
    1d0a:	9901      	ldr	r1, [sp, #4]
	uint32_t region_start_addr = arm_cmse_mpu_region_get(start);
    1d0c:	4604      	mov	r4, r0
	uint32_t region_end_addr = arm_cmse_mpu_region_get(start + size - 1);
    1d0e:	eb09 0001 	add.w	r0, r9, r1
    1d12:	3801      	subs	r0, #1
    1d14:	f004 f9d6 	bl	60c4 <arm_cmse_mpu_region_get>
	if (region_start_addr == region_end_addr) {
    1d18:	4284      	cmp	r4, r0
    1d1a:	f04f 0214 	mov.w	r2, #20
    1d1e:	4b1d      	ldr	r3, [pc, #116]	; (1d94 <arm_core_mpu_mark_areas_for_dynamic_regions+0xb4>)
    1d20:	d008      	beq.n	1d34 <arm_core_mpu_mark_areas_for_dynamic_regions+0x54>
		dyn_reg_info[i].index =
    1d22:	fb02 f308 	mul.w	r3, r2, r8
    1d26:	f06f 0215 	mvn.w	r2, #21
    1d2a:	f84b 2003 	str.w	r2, [fp, r3]
						 dyn_region_areas_num) == -EINVAL) {

		__ASSERT(0, "Marking %u areas for dynamic regions failed\n",
			dyn_region_areas_num);
	}
}
    1d2e:	b003      	add	sp, #12
    1d30:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
					dyn_region_areas[i].size);

		if (dyn_reg_info[i].index == -EINVAL) {
    1d34:	f114 0f16 	cmn.w	r4, #22
		dyn_reg_info[i].index =
    1d38:	602c      	str	r4, [r5, #0]
		if (dyn_reg_info[i].index == -EINVAL) {
    1d3a:	d0f8      	beq.n	1d2e <arm_core_mpu_mark_areas_for_dynamic_regions+0x4e>

			return -EINVAL;
		}

		if (dyn_reg_info[i].index >= static_regions_num) {
    1d3c:	7819      	ldrb	r1, [r3, #0]
    1d3e:	42a1      	cmp	r1, r4
    1d40:	ddf5      	ble.n	1d2e <arm_core_mpu_mark_areas_for_dynamic_regions+0x4e>
	attr->rbar = mpu_get_rbar() &
    1d42:	fb02 b008 	mla	r0, r2, r8, fp
	MPU->RNR = rnr;
    1d46:	f8c7 4098 	str.w	r4, [r7, #152]	; 0x98
    1d4a:	f8c7 4098 	str.w	r4, [r7, #152]	; 0x98
	return MPU->RBAR;
    1d4e:	f8d7 409c 	ldr.w	r4, [r7, #156]	; 0x9c
	attr->rbar = mpu_get_rbar() &
    1d52:	f100 0108 	add.w	r1, r0, #8
    1d56:	7b00      	ldrb	r0, [r0, #12]
    1d58:	f364 0004 	bfi	r0, r4, #0, #5
    1d5c:	7108      	strb	r0, [r1, #4]
	return MPU->RLAR;
    1d5e:	f8d7 00a0 	ldr.w	r0, [r7, #160]	; 0xa0
	attr->mair_idx = (mpu_get_rlar() & MPU_RLAR_AttrIndx_Msk) >>
    1d62:	790c      	ldrb	r4, [r1, #4]
    1d64:	0840      	lsrs	r0, r0, #1
    1d66:	f360 1447 	bfi	r4, r0, #5, #3
    1d6a:	710c      	strb	r4, [r1, #4]
	return MPU->RBAR;
    1d6c:	f8d7 109c 	ldr.w	r1, [r7, #156]	; 0x9c
	region_conf->base = mpu_get_rbar() & MPU_RBAR_BASE_Msk;
    1d70:	f021 011f 	bic.w	r1, r1, #31
    1d74:	6069      	str	r1, [r5, #4]
	return MPU->RLAR;
    1d76:	f8d7 10a0 	ldr.w	r1, [r7, #160]	; 0xa0
	region_conf->attr.r_limit = mpu_get_rlar() & MPU_RLAR_LIMIT_Msk;
    1d7a:	f021 011f 	bic.w	r1, r1, #31
    1d7e:	6129      	str	r1, [r5, #16]
	for (int i = 0; i < dyn_region_areas_num; i++) {
    1d80:	f108 0801 	add.w	r8, r8, #1
    1d84:	3514      	adds	r5, #20
    1d86:	360c      	adds	r6, #12
    1d88:	e7b3      	b.n	1cf2 <arm_core_mpu_mark_areas_for_dynamic_regions+0x12>
    1d8a:	bf00      	nop
    1d8c:	200008bc 	.word	0x200008bc
    1d90:	e000ed00 	.word	0xe000ed00
    1d94:	20000c33 	.word	0x20000c33

00001d98 <z_arm_mpu_init>:
 *
 * This function provides the default configuration mechanism for the Memory
 * Protection Unit (MPU).
 */
int z_arm_mpu_init(void)
{
    1d98:	b538      	push	{r3, r4, r5, lr}
	uint32_t r_index;

	if (mpu_config.num_regions > get_num_regions()) {
    1d9a:	4d0e      	ldr	r5, [pc, #56]	; (1dd4 <z_arm_mpu_init+0x3c>)
    1d9c:	682c      	ldr	r4, [r5, #0]
    1d9e:	2c08      	cmp	r4, #8
    1da0:	d815      	bhi.n	1dce <z_arm_mpu_init+0x36>

	/* Architecture-specific configuration */
	mpu_init();

	/* Program fixed regions configured at SOC definition. */
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    1da2:	2000      	movs	r0, #0
	arm_core_mpu_disable();
    1da4:	f7ff ff88 	bl	1cb8 <arm_core_mpu_disable>
	MPU->MAIR0 = mair0;
    1da8:	4b0b      	ldr	r3, [pc, #44]	; (1dd8 <z_arm_mpu_init+0x40>)
    1daa:	4a0c      	ldr	r2, [pc, #48]	; (1ddc <z_arm_mpu_init+0x44>)
    1dac:	f8c3 20c0 	str.w	r2, [r3, #192]	; 0xc0
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    1db0:	4284      	cmp	r4, r0
    1db2:	d105      	bne.n	1dc0 <z_arm_mpu_init+0x28>
		region_init(r_index, &mpu_config.mpu_regions[r_index]);
	}

	/* Update the number of programmed MPU regions. */
	static_regions_num = mpu_config.num_regions;
    1db4:	4b0a      	ldr	r3, [pc, #40]	; (1de0 <z_arm_mpu_init+0x48>)
		(MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos ==
		NUM_MPU_REGIONS,
		"Invalid number of MPU regions\n");
#endif /* CORTEX_M0PLUS || CPU_CORTEX_M3 || CPU_CORTEX_M4 */

	return 0;
    1db6:	2000      	movs	r0, #0
	static_regions_num = mpu_config.num_regions;
    1db8:	701c      	strb	r4, [r3, #0]
	arm_core_mpu_enable();
    1dba:	f7ff ff71 	bl	1ca0 <arm_core_mpu_enable>
}
    1dbe:	bd38      	pop	{r3, r4, r5, pc}
		region_init(r_index, &mpu_config.mpu_regions[r_index]);
    1dc0:	6869      	ldr	r1, [r5, #4]
    1dc2:	eb01 1100 	add.w	r1, r1, r0, lsl #4
    1dc6:	f7ff feab 	bl	1b20 <region_init>
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    1dca:	3001      	adds	r0, #1
    1dcc:	e7f0      	b.n	1db0 <z_arm_mpu_init+0x18>
		return -1;
    1dce:	f04f 30ff 	mov.w	r0, #4294967295
    1dd2:	e7f4      	b.n	1dbe <z_arm_mpu_init+0x26>
    1dd4:	000072d0 	.word	0x000072d0
    1dd8:	e000ed00 	.word	0xe000ed00
    1ddc:	0044ffaa 	.word	0x0044ffaa
    1de0:	20000c33 	.word	0x20000c33

00001de4 <__stdout_hook_install>:

static int (*_stdout_hook)(int c) = _stdout_hook_default;

void __stdout_hook_install(int (*hook)(int c))
{
	_stdout_hook = hook;
    1de4:	4b01      	ldr	r3, [pc, #4]	; (1dec <__stdout_hook_install+0x8>)
    1de6:	6018      	str	r0, [r3, #0]
}
    1de8:	4770      	bx	lr
    1dea:	bf00      	nop
    1dec:	20000028 	.word	0x20000028

00001df0 <z_impl_zephyr_fputc>:

int z_impl_zephyr_fputc(int c, FILE *stream)
{
	return (stream == stdout || stream == stderr) ? _stdout_hook(c) : EOF;
    1df0:	3902      	subs	r1, #2
    1df2:	2901      	cmp	r1, #1
    1df4:	d802      	bhi.n	1dfc <z_impl_zephyr_fputc+0xc>
    1df6:	4b03      	ldr	r3, [pc, #12]	; (1e04 <z_impl_zephyr_fputc+0x14>)
    1df8:	681b      	ldr	r3, [r3, #0]
    1dfa:	4718      	bx	r3
}
    1dfc:	f04f 30ff 	mov.w	r0, #4294967295
    1e00:	4770      	bx	lr
    1e02:	bf00      	nop
    1e04:	20000028 	.word	0x20000028

00001e08 <printf>:

	return r;
}

int printf(const char *ZRESTRICT format, ...)
{
    1e08:	b40f      	push	{r0, r1, r2, r3}
    1e0a:	b51f      	push	{r0, r1, r2, r3, r4, lr}
    1e0c:	2100      	movs	r1, #0
    1e0e:	ab06      	add	r3, sp, #24
    1e10:	f853 2b04 	ldr.w	r2, [r3], #4
    1e14:	4805      	ldr	r0, [pc, #20]	; (1e2c <printf+0x24>)
    1e16:	9100      	str	r1, [sp, #0]
    1e18:	2102      	movs	r1, #2
	va_list vargs;
	int     r;

	va_start(vargs, format);
    1e1a:	9303      	str	r3, [sp, #12]
    1e1c:	f7fe fce2 	bl	7e4 <z_cbvprintf_impl>
	r = cbvprintf(fputc, DESC(stdout), format, vargs);
	va_end(vargs);

	return r;
}
    1e20:	b005      	add	sp, #20
    1e22:	f85d eb04 	ldr.w	lr, [sp], #4
    1e26:	b004      	add	sp, #16
    1e28:	4770      	bx	lr
    1e2a:	bf00      	nop
    1e2c:	000061ad 	.word	0x000061ad

00001e30 <onoff_stop>:
}

static clock_control_subsys_t get_subsys(struct onoff_manager *mgr)
{
	struct nrf_clock_control_data *data = CLOCK_DEVICE->data;
	size_t offset = (size_t)(mgr - data->mgr);
    1e30:	4b08      	ldr	r3, [pc, #32]	; (1e54 <onoff_stop+0x24>)
	return (clock_control_subsys_t)offset;
}

static void onoff_stop(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    1e32:	b570      	push	{r4, r5, r6, lr}
	size_t offset = (size_t)(mgr - data->mgr);
    1e34:	1ac3      	subs	r3, r0, r3
{
    1e36:	460d      	mov	r5, r1
	int res;

	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
    1e38:	4907      	ldr	r1, [pc, #28]	; (1e58 <onoff_stop+0x28>)
	size_t offset = (size_t)(mgr - data->mgr);
    1e3a:	109b      	asrs	r3, r3, #2
{
    1e3c:	4604      	mov	r4, r0
	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
    1e3e:	4359      	muls	r1, r3
    1e40:	2240      	movs	r2, #64	; 0x40
    1e42:	4806      	ldr	r0, [pc, #24]	; (1e5c <onoff_stop+0x2c>)
    1e44:	f004 f9d0 	bl	61e8 <stop>
	notify(mgr, res);
    1e48:	462b      	mov	r3, r5
	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
    1e4a:	4601      	mov	r1, r0
	notify(mgr, res);
    1e4c:	4620      	mov	r0, r4
}
    1e4e:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	notify(mgr, res);
    1e52:	4718      	bx	r3
    1e54:	200008e4 	.word	0x200008e4
    1e58:	b6db6db7 	.word	0xb6db6db7
    1e5c:	00006f10 	.word	0x00006f10

00001e60 <onoff_start>:
static void onoff_start(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
	int err;

	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    1e60:	2340      	movs	r3, #64	; 0x40
{
    1e62:	b573      	push	{r0, r1, r4, r5, r6, lr}
	size_t offset = (size_t)(mgr - data->mgr);
    1e64:	4c0b      	ldr	r4, [pc, #44]	; (1e94 <onoff_start+0x34>)
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    1e66:	9300      	str	r3, [sp, #0]
	size_t offset = (size_t)(mgr - data->mgr);
    1e68:	1b04      	subs	r4, r0, r4
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    1e6a:	460b      	mov	r3, r1
{
    1e6c:	460d      	mov	r5, r1
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    1e6e:	490a      	ldr	r1, [pc, #40]	; (1e98 <onoff_start+0x38>)
	size_t offset = (size_t)(mgr - data->mgr);
    1e70:	10a4      	asrs	r4, r4, #2
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    1e72:	4361      	muls	r1, r4
{
    1e74:	4606      	mov	r6, r0
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    1e76:	4a09      	ldr	r2, [pc, #36]	; (1e9c <onoff_start+0x3c>)
    1e78:	4809      	ldr	r0, [pc, #36]	; (1ea0 <onoff_start+0x40>)
    1e7a:	f004 f9e2 	bl	6242 <async_start>
			  onoff_started_callback, notify, CTX_ONOFF);
	if (err < 0) {
    1e7e:	1e01      	subs	r1, r0, #0
    1e80:	da05      	bge.n	1e8e <onoff_start+0x2e>
		notify(mgr, err);
    1e82:	4630      	mov	r0, r6
    1e84:	462b      	mov	r3, r5
	}
}
    1e86:	b002      	add	sp, #8
    1e88:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		notify(mgr, err);
    1e8c:	4718      	bx	r3
}
    1e8e:	b002      	add	sp, #8
    1e90:	bd70      	pop	{r4, r5, r6, pc}
    1e92:	bf00      	nop
    1e94:	200008e4 	.word	0x200008e4
    1e98:	b6db6db7 	.word	0xb6db6db7
    1e9c:	000062af 	.word	0x000062af
    1ea0:	00006f10 	.word	0x00006f10

00001ea4 <clk_init>:
#endif /* NRF_CLOCK_HAS_HFCLKAUDIO */
#endif
}

static int clk_init(const struct device *dev)
{
    1ea4:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
	static const struct onoff_transitions transitions = {
		.start = onoff_start,
		.stop = onoff_stop
	};

	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    1ea8:	2200      	movs	r2, #0
    1eaa:	2101      	movs	r1, #1
{
    1eac:	4606      	mov	r6, r0
	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    1eae:	2005      	movs	r0, #5
    1eb0:	f7ff fb98 	bl	15e4 <z_arm_irq_priority_set>
		    nrfx_isr, nrfx_power_clock_irq_handler, 0);

	nrfx_err = nrfx_clock_init(clock_event_handler);
    1eb4:	4811      	ldr	r0, [pc, #68]	; (1efc <clk_init+0x58>)
    1eb6:	f001 fce9 	bl	388c <nrfx_clock_init>
	if (nrfx_err != NRFX_SUCCESS) {
    1eba:	4b11      	ldr	r3, [pc, #68]	; (1f00 <clk_init+0x5c>)
    1ebc:	4298      	cmp	r0, r3
    1ebe:	d119      	bne.n	1ef4 <clk_init+0x50>
		struct nrf_clock_control_data *data = dev->data;

		z_nrf_clock_calibration_init(data->mgr);
	}

	nrfx_clock_enable();
    1ec0:	f004 fd74 	bl	69ac <nrfx_clock_enable>
    1ec4:	2400      	movs	r4, #0
	return &data->mgr[type];
    1ec6:	f04f 091c 	mov.w	r9, #28
					 &transitions);
		if (err < 0) {
			return err;
		}

		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    1eca:	270c      	movs	r7, #12
		err = onoff_manager_init(get_onoff_manager(dev, i),
    1ecc:	f8df 8034 	ldr.w	r8, [pc, #52]	; 1f04 <clk_init+0x60>
	struct nrf_clock_control_data *data = dev->data;
    1ed0:	6935      	ldr	r5, [r6, #16]
		err = onoff_manager_init(get_onoff_manager(dev, i),
    1ed2:	4641      	mov	r1, r8
    1ed4:	fb09 5004 	mla	r0, r9, r4, r5
    1ed8:	f003 ffee 	bl	5eb8 <onoff_manager_init>
		if (err < 0) {
    1edc:	2800      	cmp	r0, #0
    1ede:	db07      	blt.n	1ef0 <clk_init+0x4c>
		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    1ee0:	2301      	movs	r3, #1
    1ee2:	fb07 5504 	mla	r5, r7, r4, r5
		i < CLOCK_CONTROL_NRF_TYPE_COUNT; i++) {
    1ee6:	441c      	add	r4, r3
    1ee8:	2c04      	cmp	r4, #4
		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    1eea:	67ab      	str	r3, [r5, #120]	; 0x78
		i < CLOCK_CONTROL_NRF_TYPE_COUNT; i++) {
    1eec:	d1f0      	bne.n	1ed0 <clk_init+0x2c>
	}

	return 0;
    1eee:	2000      	movs	r0, #0
}
    1ef0:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
		return -EIO;
    1ef4:	f06f 0004 	mvn.w	r0, #4
    1ef8:	e7fa      	b.n	1ef0 <clk_init+0x4c>
    1efa:	bf00      	nop
    1efc:	00001f3d 	.word	0x00001f3d
    1f00:	0bad0000 	.word	0x0bad0000
    1f04:	000072f8 	.word	0x000072f8

00001f08 <clkstarted_handle.constprop.0>:
static void clkstarted_handle(const struct device *dev,
    1f08:	4601      	mov	r1, r0
	clock_control_cb_t callback = sub_data->cb;
    1f0a:	230c      	movs	r3, #12
	sub_data->cb = NULL;
    1f0c:	2200      	movs	r2, #0
	clock_control_cb_t callback = sub_data->cb;
    1f0e:	434b      	muls	r3, r1
static void clkstarted_handle(const struct device *dev,
    1f10:	b570      	push	{r4, r5, r6, lr}
	clock_control_cb_t callback = sub_data->cb;
    1f12:	4808      	ldr	r0, [pc, #32]	; (1f34 <clkstarted_handle.constprop.0+0x2c>)
    1f14:	18c4      	adds	r4, r0, r3
	set_on_state(&sub_data->flags);
    1f16:	3378      	adds	r3, #120	; 0x78
    1f18:	4418      	add	r0, r3
	void *user_data = sub_data->user_data;
    1f1a:	e9d4 561c 	ldrd	r5, r6, [r4, #112]	; 0x70
	sub_data->cb = NULL;
    1f1e:	6722      	str	r2, [r4, #112]	; 0x70
	set_on_state(&sub_data->flags);
    1f20:	f004 f94f 	bl	61c2 <set_on_state>
	if (callback) {
    1f24:	b12d      	cbz	r5, 1f32 <clkstarted_handle.constprop.0+0x2a>
		callback(dev, (clock_control_subsys_t)type, user_data);
    1f26:	4632      	mov	r2, r6
    1f28:	462b      	mov	r3, r5
}
    1f2a:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		callback(dev, (clock_control_subsys_t)type, user_data);
    1f2e:	4802      	ldr	r0, [pc, #8]	; (1f38 <clkstarted_handle.constprop.0+0x30>)
    1f30:	4718      	bx	r3
}
    1f32:	bd70      	pop	{r4, r5, r6, pc}
    1f34:	200008e4 	.word	0x200008e4
    1f38:	00006f10 	.word	0x00006f10

00001f3c <clock_event_handler>:
	switch (event) {
    1f3c:	2805      	cmp	r0, #5
    1f3e:	d811      	bhi.n	1f64 <clock_event_handler+0x28>
    1f40:	e8df f000 	tbb	[pc, r0]
    1f44:	10100e03 	.word	0x10100e03
    1f48:	0a0c      	.short	0x0a0c
		if (GET_STATUS(data->flags) == CLOCK_CONTROL_STATUS_STARTING) {
    1f4a:	4b07      	ldr	r3, [pc, #28]	; (1f68 <clock_event_handler+0x2c>)
    1f4c:	6f98      	ldr	r0, [r3, #120]	; 0x78
    1f4e:	f010 0007 	ands.w	r0, r0, #7
    1f52:	d107      	bne.n	1f64 <clock_event_handler+0x28>
		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_LFCLK);
    1f54:	f7ff bfd8 	b.w	1f08 <clkstarted_handle.constprop.0>
		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_HFCLK192M);
    1f58:	2002      	movs	r0, #2
    1f5a:	e7fb      	b.n	1f54 <clock_event_handler+0x18>
		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_HFCLKAUDIO);
    1f5c:	2003      	movs	r0, #3
    1f5e:	e7f9      	b.n	1f54 <clock_event_handler+0x18>
		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_LFCLK);
    1f60:	2001      	movs	r0, #1
    1f62:	e7f7      	b.n	1f54 <clock_event_handler+0x18>
}
    1f64:	4770      	bx	lr
    1f66:	bf00      	nop
    1f68:	200008e4 	.word	0x200008e4

00001f6c <generic_hfclk_start>:
{
    1f6c:	b508      	push	{r3, lr}
	__asm__ volatile(
    1f6e:	f04f 0320 	mov.w	r3, #32
    1f72:	f3ef 8111 	mrs	r1, BASEPRI
    1f76:	f383 8812 	msr	BASEPRI_MAX, r3
    1f7a:	f3bf 8f6f 	isb	sy
	hfclk_users |= HF_USER_GENERIC;
    1f7e:	4a12      	ldr	r2, [pc, #72]	; (1fc8 <generic_hfclk_start+0x5c>)
    1f80:	6813      	ldr	r3, [r2, #0]
    1f82:	f043 0002 	orr.w	r0, r3, #2
    1f86:	6010      	str	r0, [r2, #0]
	if (hfclk_users & HF_USER_BT) {
    1f88:	07da      	lsls	r2, r3, #31
    1f8a:	d408      	bmi.n	1f9e <generic_hfclk_start+0x32>
	__asm__ volatile(
    1f8c:	f381 8811 	msr	BASEPRI, r1
    1f90:	f3bf 8f6f 	isb	sy
}
    1f94:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_start(void)
{
    nrfx_clock_start(NRF_CLOCK_DOMAIN_HFCLK);
    1f98:	2001      	movs	r0, #1
    1f9a:	f004 bd19 	b.w	69d0 <nrfx_clock_start>
            break;
        case NRF_CLOCK_DOMAIN_HFCLK:
            if (p_clk_src != NULL)
            {
                (*(nrf_clock_hfclk_t *)p_clk_src) =
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    1f9e:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    1fa2:	f8d3 240c 	ldr.w	r2, [r3, #1036]	; 0x40c
                                        >> CLOCK_HFCLKSTAT_SRC_Pos);
            }
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    1fa6:	f8d3 340c 	ldr.w	r3, [r3, #1036]	; 0x40c
		if (type == NRF_CLOCK_HFCLK_HIGH_ACCURACY) {
    1faa:	07d3      	lsls	r3, r2, #31
    1fac:	d5ee      	bpl.n	1f8c <generic_hfclk_start+0x20>
			set_on_state(get_hf_flags());
    1fae:	4807      	ldr	r0, [pc, #28]	; (1fcc <generic_hfclk_start+0x60>)
    1fb0:	f004 f907 	bl	61c2 <set_on_state>
    1fb4:	f381 8811 	msr	BASEPRI, r1
    1fb8:	f3bf 8f6f 	isb	sy
}
    1fbc:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
		clkstarted_handle(CLOCK_DEVICE,
    1fc0:	2000      	movs	r0, #0
    1fc2:	f7ff bfa1 	b.w	1f08 <clkstarted_handle.constprop.0>
    1fc6:	bf00      	nop
    1fc8:	20000984 	.word	0x20000984
    1fcc:	2000095c 	.word	0x2000095c

00001fd0 <api_blocking_start>:
{
    1fd0:	b51f      	push	{r0, r1, r2, r3, r4, lr}
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    1fd2:	2200      	movs	r2, #0
    1fd4:	2301      	movs	r3, #1
    1fd6:	e9cd 2302 	strd	r2, r3, [sp, #8]
	err = api_start(dev, subsys, blocking_start_callback, &sem);
    1fda:	466b      	mov	r3, sp
    1fdc:	4a08      	ldr	r2, [pc, #32]	; (2000 <CONFIG_NRF_SPU_RAM_REGION_SIZE>)
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    1fde:	f8cd d000 	str.w	sp, [sp]
    1fe2:	f8cd d004 	str.w	sp, [sp, #4]
	err = api_start(dev, subsys, blocking_start_callback, &sem);
    1fe6:	f004 f95b 	bl	62a0 <api_start>
	if (err < 0) {
    1fea:	2800      	cmp	r0, #0
    1fec:	db05      	blt.n	1ffa <api_blocking_start+0x2a>
		union { struct { uintptr_t lo, hi; } split; k_timeout_t val; } parm1 = { .val = timeout };
		return (int) arch_syscall_invoke3(parm0.x, parm1.split.lo, parm1.split.hi, K_SYSCALL_K_SEM_TAKE);
	}
#endif
	compiler_barrier();
	return z_impl_k_sem_take(sem, timeout);
    1fee:	f44f 4280 	mov.w	r2, #16384	; 0x4000
    1ff2:	2300      	movs	r3, #0
    1ff4:	4668      	mov	r0, sp
    1ff6:	f003 f891 	bl	511c <z_impl_k_sem_take>
}
    1ffa:	b005      	add	sp, #20
    1ffc:	f85d fb04 	ldr.w	pc, [sp], #4
    2000:	000062e5 	.word	0x000062e5

00002004 <generic_hfclk_stop>:
{
    2004:	b510      	push	{r4, lr}
	__asm__ volatile(
    2006:	f04f 0320 	mov.w	r3, #32
    200a:	f3ef 8411 	mrs	r4, BASEPRI
    200e:	f383 8812 	msr	BASEPRI_MAX, r3
    2012:	f3bf 8f6f 	isb	sy
	hfclk_users &= ~HF_USER_GENERIC;
    2016:	4a07      	ldr	r2, [pc, #28]	; (2034 <generic_hfclk_stop+0x30>)
    2018:	6813      	ldr	r3, [r2, #0]
    201a:	f023 0102 	bic.w	r1, r3, #2
	if (!(hfclk_users & HF_USER_BT)) {
    201e:	07db      	lsls	r3, r3, #31
	hfclk_users &= ~HF_USER_GENERIC;
    2020:	6011      	str	r1, [r2, #0]
	if (!(hfclk_users & HF_USER_BT)) {
    2022:	d402      	bmi.n	202a <generic_hfclk_stop+0x26>
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_stop(void)
{
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLK);
    2024:	2001      	movs	r0, #1
    2026:	f004 fd32 	bl	6a8e <nrfx_clock_stop>
	__asm__ volatile(
    202a:	f384 8811 	msr	BASEPRI, r4
    202e:	f3bf 8f6f 	isb	sy
}
    2032:	bd10      	pop	{r4, pc}
    2034:	20000984 	.word	0x20000984

00002038 <z_nrf_clock_control_lf_on>:
{
    2038:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	return __atomic_exchange_n(target, value, __ATOMIC_SEQ_CST);
    203c:	2201      	movs	r2, #1
    203e:	4607      	mov	r7, r0
    2040:	4937      	ldr	r1, [pc, #220]	; (2120 <z_nrf_clock_control_lf_on+0xe8>)
    2042:	e8d1 3fef 	ldaex	r3, [r1]
    2046:	e8c1 2fe0 	stlex	r0, r2, [r1]
    204a:	2800      	cmp	r0, #0
    204c:	d1f9      	bne.n	2042 <z_nrf_clock_control_lf_on+0xa>
	if (atomic_set(&on, 1) == 0) {
    204e:	b933      	cbnz	r3, 205e <z_nrf_clock_control_lf_on+0x26>
 */
static inline void sys_notify_init_spinwait(struct sys_notify *notify)
{
	__ASSERT_NO_MSG(notify != NULL);

	*notify = (struct sys_notify){
    2050:	4934      	ldr	r1, [pc, #208]	; (2124 <z_nrf_clock_control_lf_on+0xec>)
		err = onoff_request(mgr, &cli);
    2052:	4835      	ldr	r0, [pc, #212]	; (2128 <z_nrf_clock_control_lf_on+0xf0>)
    2054:	604b      	str	r3, [r1, #4]
    2056:	60cb      	str	r3, [r1, #12]
    2058:	608a      	str	r2, [r1, #8]
    205a:	f003 ff40 	bl	5ede <onoff_request>
	switch (start_mode) {
    205e:	1e7b      	subs	r3, r7, #1
    2060:	2b01      	cmp	r3, #1
    2062:	d82b      	bhi.n	20bc <z_nrf_clock_control_lf_on+0x84>
	if ((mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE) &&
    2064:	2f01      	cmp	r7, #1
    2066:	d107      	bne.n	2078 <z_nrf_clock_control_lf_on+0x40>
    return clk_src;
}

NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(NRF_CLOCK_Type const * p_reg)
{
    return (nrf_clock_lfclk_t)((p_reg->LFCLKSRCCOPY & CLOCK_LFCLKSRCCOPY_SRC_Msk)
    2068:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    206c:	f8d3 341c 	ldr.w	r3, [r3, #1052]	; 0x41c
	    (target_type == NRF_CLOCK_LFCLK_Xtal) &&
    2070:	f003 0303 	and.w	r3, r3, #3
    2074:	2b02      	cmp	r3, #2
    2076:	d021      	beq.n	20bc <z_nrf_clock_control_lf_on+0x84>
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    2078:	f004 fe02 	bl	6c80 <k_is_in_isr>
    207c:	4605      	mov	r5, r0
    207e:	b9f8      	cbnz	r0, 20c0 <z_nrf_clock_control_lf_on+0x88>
	return !z_sys_post_kernel;
    2080:	4b2a      	ldr	r3, [pc, #168]	; (212c <z_nrf_clock_control_lf_on+0xf4>)
    2082:	781b      	ldrb	r3, [r3, #0]
    2084:	b1e3      	cbz	r3, 20c0 <z_nrf_clock_control_lf_on+0x88>
    p_reg->INTENCLR = mask;
    2086:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    208a:	2202      	movs	r2, #2
	int key = isr_mode ? irq_lock() : 0;
    208c:	4606      	mov	r6, r0
    208e:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    2092:	f04f 2450 	mov.w	r4, #1342197760	; 0x50005000
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    2096:	f8df 8098 	ldr.w	r8, [pc, #152]	; 2130 <z_nrf_clock_control_lf_on+0xf8>
    209a:	f8d4 3418 	ldr.w	r3, [r4, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    209e:	f8d4 2418 	ldr.w	r2, [r4, #1048]	; 0x418
    20a2:	03d2      	lsls	r2, r2, #15
    20a4:	d516      	bpl.n	20d4 <z_nrf_clock_control_lf_on+0x9c>
	while (!(nrfx_clock_is_running(d, (void *)&type)
    20a6:	f003 0303 	and.w	r3, r3, #3
    20aa:	2b02      	cmp	r3, #2
    20ac:	d001      	beq.n	20b2 <z_nrf_clock_control_lf_on+0x7a>
		     || (mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE)))) {
    20ae:	2f01      	cmp	r7, #1
    20b0:	d110      	bne.n	20d4 <z_nrf_clock_control_lf_on+0x9c>
	if (isr_mode) {
    20b2:	b375      	cbz	r5, 2112 <z_nrf_clock_control_lf_on+0xda>
    20b4:	f386 8811 	msr	BASEPRI, r6
    20b8:	f3bf 8f6f 	isb	sy
}
    20bc:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	__asm__ volatile(
    20c0:	f04f 0320 	mov.w	r3, #32
    20c4:	f3ef 8611 	mrs	r6, BASEPRI
    20c8:	f383 8812 	msr	BASEPRI_MAX, r3
    20cc:	f3bf 8f6f 	isb	sy
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    20d0:	2501      	movs	r5, #1
    20d2:	e7de      	b.n	2092 <z_nrf_clock_control_lf_on+0x5a>
			if (isr_mode || !IS_ENABLED(CONFIG_MULTITHREADING)) {
    20d4:	b1c5      	cbz	r5, 2108 <z_nrf_clock_control_lf_on+0xd0>
 *
 * @param key Interrupt locking key obtained from irq_lock().
 */
static inline void k_cpu_atomic_idle(unsigned int key)
{
	arch_cpu_atomic_idle(key);
    20d6:	4630      	mov	r0, r6
    20d8:	f7ff fa42 	bl	1560 <arch_cpu_atomic_idle>
    return (nrf_clock_lfclk_t)(p_reg->LFCLKSRC);
    20dc:	f8d4 3518 	ldr.w	r3, [r4, #1304]	; 0x518
		if ((target_type ==  NRF_CLOCK_LFCLK_Xtal)
    20e0:	b2db      	uxtb	r3, r3
    20e2:	2b01      	cmp	r3, #1
    20e4:	d1d9      	bne.n	209a <z_nrf_clock_control_lf_on+0x62>
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    20e6:	f8d4 2104 	ldr.w	r2, [r4, #260]	; 0x104
		    && nrf_clock_event_check(NRF_CLOCK,
    20ea:	2a00      	cmp	r2, #0
    20ec:	d0d5      	beq.n	209a <z_nrf_clock_control_lf_on+0x62>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    20ee:	2200      	movs	r2, #0
    20f0:	f8c4 2104 	str.w	r2, [r4, #260]	; 0x104
    20f4:	f8d4 2104 	ldr.w	r2, [r4, #260]	; 0x104
    p_reg->LFCLKSRC = (uint32_t)(source);
    20f8:	2202      	movs	r2, #2
    20fa:	f8c4 2518 	str.w	r2, [r4, #1304]	; 0x518
    20fe:	2220      	movs	r2, #32
    2100:	f8c8 2180 	str.w	r2, [r8, #384]	; 0x180
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2104:	60a3      	str	r3, [r4, #8]
}
    2106:	e7c8      	b.n	209a <z_nrf_clock_control_lf_on+0x62>
	return z_impl_k_sleep(timeout);
    2108:	2100      	movs	r1, #0
    210a:	2021      	movs	r0, #33	; 0x21
    210c:	f003 faf6 	bl	56fc <z_impl_k_sleep>
	return k_sleep(Z_TIMEOUT_MS(ms));
    2110:	e7e4      	b.n	20dc <z_nrf_clock_control_lf_on+0xa4>
    p_reg->INTENSET = mask;
    2112:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    2116:	2202      	movs	r2, #2
    2118:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
}
    211c:	e7ce      	b.n	20bc <z_nrf_clock_control_lf_on+0x84>
    211e:	bf00      	nop
    2120:	200008e0 	.word	0x200008e0
    2124:	200008d0 	.word	0x200008d0
    2128:	20000900 	.word	0x20000900
    212c:	20000c3f 	.word	0x20000c3f
    2130:	e000e100 	.word	0xe000e100

00002134 <uart_console_init>:
 * @brief Initialize one UART as the console/debug port
 *
 * @return 0 if successful, otherwise failed.
 */
static int uart_console_init(const struct device *arg)
{
    2134:	b508      	push	{r3, lr}
    2136:	4807      	ldr	r0, [pc, #28]	; (2154 <uart_console_init+0x20>)
    2138:	f002 fd12 	bl	4b60 <z_device_is_ready>

	ARG_UNUSED(arg);

	if (!device_is_ready(uart_console_dev)) {
    213c:	b138      	cbz	r0, 214e <uart_console_init+0x1a>
	__stdout_hook_install(console_out);
    213e:	4806      	ldr	r0, [pc, #24]	; (2158 <uart_console_init+0x24>)
    2140:	f7ff fe50 	bl	1de4 <__stdout_hook_install>
	__printk_hook_install(console_out);
    2144:	4804      	ldr	r0, [pc, #16]	; (2158 <uart_console_init+0x24>)
    2146:	f7fe fa2b 	bl	5a0 <__printk_hook_install>
		return -ENODEV;
	}

	uart_console_hook_install();

	return 0;
    214a:	2000      	movs	r0, #0
}
    214c:	bd08      	pop	{r3, pc}
		return -ENODEV;
    214e:	f06f 0012 	mvn.w	r0, #18
    2152:	e7fb      	b.n	214c <uart_console_init+0x18>
    2154:	00006f58 	.word	0x00006f58
    2158:	0000215d 	.word	0x0000215d

0000215c <console_out>:
	if ('\n' == c) {
    215c:	280a      	cmp	r0, #10
{
    215e:	b538      	push	{r3, r4, r5, lr}
    2160:	4604      	mov	r4, r0
    2162:	4d07      	ldr	r5, [pc, #28]	; (2180 <console_out+0x24>)
	if ('\n' == c) {
    2164:	d104      	bne.n	2170 <console_out+0x14>
					unsigned char out_char)
{
	const struct uart_driver_api *api =
		(const struct uart_driver_api *)dev->api;

	api->poll_out(dev, out_char);
    2166:	68ab      	ldr	r3, [r5, #8]
    2168:	210d      	movs	r1, #13
    216a:	4628      	mov	r0, r5
    216c:	685b      	ldr	r3, [r3, #4]
    216e:	4798      	blx	r3
    2170:	68ab      	ldr	r3, [r5, #8]
    2172:	4803      	ldr	r0, [pc, #12]	; (2180 <console_out+0x24>)
    2174:	685b      	ldr	r3, [r3, #4]
    2176:	b2e1      	uxtb	r1, r4
    2178:	4798      	blx	r3
}
    217a:	4620      	mov	r0, r4
    217c:	bd38      	pop	{r3, r4, r5, pc}
    217e:	bf00      	nop
    2180:	00006f58 	.word	0x00006f58

00002184 <gpio_nrfx_pin_interrupt_configure>:

static int gpio_nrfx_pin_interrupt_configure(const struct device *port,
					     gpio_pin_t pin,
					     enum gpio_int_mode mode,
					     enum gpio_int_trig trig)
{
    2184:	b530      	push	{r4, r5, lr}
	return port->config;
    2186:	6840      	ldr	r0, [r0, #4]
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
    2188:	f001 041f 	and.w	r4, r1, #31
    218c:	7b05      	ldrb	r5, [r0, #12]
	nrfx_err_t err;
	uint8_t ch;

	if (mode == GPIO_INT_MODE_DISABLED) {
    218e:	f5b2 1f00 	cmp.w	r2, #2097152	; 0x200000
{
    2192:	b085      	sub	sp, #20
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
    2194:	ea44 1445 	orr.w	r4, r4, r5, lsl #5
	if (mode == GPIO_INT_MODE_DISABLED) {
    2198:	d105      	bne.n	21a6 <gpio_nrfx_pin_interrupt_configure+0x22>
		nrfx_gpiote_trigger_disable(abs_pin);
    219a:	4620      	mov	r0, r4
    219c:	f001 fe26 	bl	3dec <nrfx_gpiote_trigger_disable>

		return 0;
    21a0:	2000      	movs	r0, #0
	}

	nrfx_gpiote_trigger_enable(abs_pin, true);

	return 0;
}
    21a2:	b005      	add	sp, #20
    21a4:	bd30      	pop	{r4, r5, pc}
	nrfx_gpiote_trigger_config_t trigger_config = {
    21a6:	2500      	movs	r5, #0
	if (mode == GPIO_INT_MODE_LEVEL) {
    21a8:	f5b2 0f80 	cmp.w	r2, #4194304	; 0x400000
	nrfx_gpiote_trigger_config_t trigger_config = {
    21ac:	e9cd 5502 	strd	r5, r5, [sp, #8]
	if (mode == GPIO_INT_MODE_LEVEL) {
    21b0:	d114      	bne.n	21dc <gpio_nrfx_pin_interrupt_configure+0x58>
		return trig == GPIO_INT_TRIG_LOW ? NRFX_GPIOTE_TRIGGER_LOW :
    21b2:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
	nrfx_gpiote_trigger_config_t trigger_config = {
    21b6:	bf0c      	ite	eq
    21b8:	2304      	moveq	r3, #4
    21ba:	2305      	movne	r3, #5
    21bc:	f88d 3008 	strb.w	r3, [sp, #8]
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    21c0:	2300      	movs	r3, #0
    21c2:	4620      	mov	r0, r4
    21c4:	4619      	mov	r1, r3
    21c6:	aa02      	add	r2, sp, #8
    21c8:	f001 fc4e 	bl	3a68 <nrfx_gpiote_input_configure>
	if (err != NRFX_SUCCESS) {
    21cc:	4b1f      	ldr	r3, [pc, #124]	; (224c <gpio_nrfx_pin_interrupt_configure+0xc8>)
    21ce:	4298      	cmp	r0, r3
    21d0:	d138      	bne.n	2244 <gpio_nrfx_pin_interrupt_configure+0xc0>
	nrfx_gpiote_trigger_enable(abs_pin, true);
    21d2:	2101      	movs	r1, #1
    21d4:	4620      	mov	r0, r4
    21d6:	f001 fdc3 	bl	3d60 <nrfx_gpiote_trigger_enable>
	return 0;
    21da:	e7e1      	b.n	21a0 <gpio_nrfx_pin_interrupt_configure+0x1c>
	return trig == GPIO_INT_TRIG_BOTH ? NRFX_GPIOTE_TRIGGER_TOGGLE :
    21dc:	f1b3 6fc0 	cmp.w	r3, #100663296	; 0x6000000
    21e0:	d025      	beq.n	222e <gpio_nrfx_pin_interrupt_configure+0xaa>
    21e2:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
    21e6:	bf14      	ite	ne
    21e8:	2301      	movne	r3, #1
    21ea:	2302      	moveq	r3, #2
	nrfx_gpiote_trigger_config_t trigger_config = {
    21ec:	f88d 3008 	strb.w	r3, [sp, #8]
	if (!(BIT(pin) & get_port_cfg(port)->edge_sense) &&
    21f0:	6883      	ldr	r3, [r0, #8]
    21f2:	40cb      	lsrs	r3, r1
    21f4:	07d9      	lsls	r1, r3, #31
    21f6:	d4e3      	bmi.n	21c0 <gpio_nrfx_pin_interrupt_configure+0x3c>
    21f8:	f1b2 7fa0 	cmp.w	r2, #20971520	; 0x1400000
    21fc:	d1e0      	bne.n	21c0 <gpio_nrfx_pin_interrupt_configure+0x3c>
        case 1: return NRF_P1;
    21fe:	4a14      	ldr	r2, [pc, #80]	; (2250 <gpio_nrfx_pin_interrupt_configure+0xcc>)
    2200:	4814      	ldr	r0, [pc, #80]	; (2254 <gpio_nrfx_pin_interrupt_configure+0xd0>)
NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin)
{
    uint32_t pin_number = *p_pin;
    *p_pin = pin_number & 0x1F;

    return pin_number >> 5;
    2202:	0961      	lsrs	r1, r4, #5
        case 1: return NRF_P1;
    2204:	2901      	cmp	r1, #1
    2206:	bf08      	it	eq
    2208:	4602      	moveq	r2, r0
    *p_pin = pin_number & 0x1F;
    220a:	f004 031f 	and.w	r3, r4, #31
    return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
    220e:	3380      	adds	r3, #128	; 0x80
    2210:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
	    (mode == GPIO_INT_MODE_EDGE) &&
    2214:	07db      	lsls	r3, r3, #31
    2216:	d4d3      	bmi.n	21c0 <gpio_nrfx_pin_interrupt_configure+0x3c>
		err = nrfx_gpiote_channel_get(abs_pin, &ch);
    2218:	f10d 0507 	add.w	r5, sp, #7
    221c:	4629      	mov	r1, r5
    221e:	4620      	mov	r0, r4
    2220:	f001 fd4a 	bl	3cb8 <nrfx_gpiote_channel_get>
		if (err == NRFX_ERROR_INVALID_PARAM) {
    2224:	4b0c      	ldr	r3, [pc, #48]	; (2258 <gpio_nrfx_pin_interrupt_configure+0xd4>)
    2226:	4298      	cmp	r0, r3
    2228:	d003      	beq.n	2232 <gpio_nrfx_pin_interrupt_configure+0xae>
		trigger_config.p_in_channel = &ch;
    222a:	9503      	str	r5, [sp, #12]
    222c:	e7c8      	b.n	21c0 <gpio_nrfx_pin_interrupt_configure+0x3c>
	return trig == GPIO_INT_TRIG_BOTH ? NRFX_GPIOTE_TRIGGER_TOGGLE :
    222e:	2303      	movs	r3, #3
    2230:	e7dc      	b.n	21ec <gpio_nrfx_pin_interrupt_configure+0x68>
			err = nrfx_gpiote_channel_alloc(&ch);
    2232:	4628      	mov	r0, r5
    2234:	f001 fd8e 	bl	3d54 <nrfx_gpiote_channel_alloc>
			if (err != NRFX_SUCCESS) {
    2238:	4b04      	ldr	r3, [pc, #16]	; (224c <gpio_nrfx_pin_interrupt_configure+0xc8>)
    223a:	4298      	cmp	r0, r3
    223c:	d0f5      	beq.n	222a <gpio_nrfx_pin_interrupt_configure+0xa6>
				return -ENOMEM;
    223e:	f06f 000b 	mvn.w	r0, #11
    2242:	e7ae      	b.n	21a2 <gpio_nrfx_pin_interrupt_configure+0x1e>
		return -EINVAL;
    2244:	f06f 0015 	mvn.w	r0, #21
    2248:	e7ab      	b.n	21a2 <gpio_nrfx_pin_interrupt_configure+0x1e>
    224a:	bf00      	nop
    224c:	0bad0000 	.word	0x0bad0000
    2250:	50842500 	.word	0x50842500
    2254:	50842800 	.word	0x50842800
    2258:	0bad0004 	.word	0x0bad0004

0000225c <gpio_nrfx_init>:
}

#define GPIOTE_NODE DT_INST(0, nordic_nrf_gpiote)

static int gpio_nrfx_init(const struct device *port)
{
    225c:	b510      	push	{r4, lr}
	nrfx_err_t err;

	if (nrfx_gpiote_is_init()) {
    225e:	f001 fd69 	bl	3d34 <nrfx_gpiote_is_init>
    2262:	4604      	mov	r4, r0
    2264:	b968      	cbnz	r0, 2282 <gpio_nrfx_init+0x26>
		return 0;
	}

	err = nrfx_gpiote_init(0/*not used*/);
    2266:	f001 fd3d 	bl	3ce4 <nrfx_gpiote_init>
	if (err != NRFX_SUCCESS) {
    226a:	4b08      	ldr	r3, [pc, #32]	; (228c <gpio_nrfx_init+0x30>)
    226c:	4298      	cmp	r0, r3
    226e:	d10a      	bne.n	2286 <gpio_nrfx_init+0x2a>
		return -EIO;
	}

	nrfx_gpiote_global_callback_set(nrfx_gpio_handler, NULL);
    2270:	4621      	mov	r1, r4
    2272:	4807      	ldr	r0, [pc, #28]	; (2290 <gpio_nrfx_init+0x34>)
    2274:	f001 fd1a 	bl	3cac <nrfx_gpiote_global_callback_set>

	IRQ_CONNECT(DT_IRQN(GPIOTE_NODE), DT_IRQ(GPIOTE_NODE, priority),
    2278:	4622      	mov	r2, r4
    227a:	2105      	movs	r1, #5
    227c:	200d      	movs	r0, #13
    227e:	f7ff f9b1 	bl	15e4 <z_arm_irq_priority_set>
		return 0;
    2282:	2000      	movs	r0, #0
		    nrfx_isr, nrfx_gpiote_irq_handler, 0);

	return 0;
}
    2284:	bd10      	pop	{r4, pc}
		return -EIO;
    2286:	f06f 0004 	mvn.w	r0, #4
    228a:	e7fb      	b.n	2284 <gpio_nrfx_init+0x28>
    228c:	0bad0000 	.word	0x0bad0000
    2290:	00002295 	.word	0x00002295

00002294 <nrfx_gpio_handler>:
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    2294:	0942      	lsrs	r2, r0, #5
{
    2296:	4603      	mov	r3, r0
    2298:	b570      	push	{r4, r5, r6, lr}
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    229a:	d002      	beq.n	22a2 <nrfx_gpio_handler+0xe>
    229c:	2a01      	cmp	r2, #1
    229e:	d017      	beq.n	22d0 <nrfx_gpio_handler+0x3c>
}
    22a0:	bd70      	pop	{r4, r5, r6, pc}
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    22a2:	4e0d      	ldr	r6, [pc, #52]	; (22d8 <nrfx_gpio_handler+0x44>)
	gpio_fire_callbacks(list, port, BIT(pin));
    22a4:	6932      	ldr	r2, [r6, #16]
    22a6:	6851      	ldr	r1, [r2, #4]
					const struct device *port,
					uint32_t pins)
{
	struct gpio_callback *cb, *tmp;

	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    22a8:	2900      	cmp	r1, #0
    22aa:	d0f9      	beq.n	22a0 <nrfx_gpio_handler+0xc>
    22ac:	2501      	movs	r5, #1
    *p_pin = pin_number & 0x1F;
    22ae:	f003 031f 	and.w	r3, r3, #31
    22b2:	680c      	ldr	r4, [r1, #0]
    22b4:	409d      	lsls	r5, r3
    22b6:	2900      	cmp	r1, #0
    22b8:	d0f2      	beq.n	22a0 <nrfx_gpio_handler+0xc>
		if (cb->pin_mask & pins) {
    22ba:	688a      	ldr	r2, [r1, #8]
    22bc:	402a      	ands	r2, r5
    22be:	d002      	beq.n	22c6 <nrfx_gpio_handler+0x32>
			__ASSERT(cb->handler, "No callback handler!");
			cb->handler(port, cb, cb->pin_mask & pins);
    22c0:	4630      	mov	r0, r6
    22c2:	684b      	ldr	r3, [r1, #4]
    22c4:	4798      	blx	r3
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    22c6:	b12c      	cbz	r4, 22d4 <nrfx_gpio_handler+0x40>
    22c8:	6823      	ldr	r3, [r4, #0]
    22ca:	4621      	mov	r1, r4
    22cc:	461c      	mov	r4, r3
    22ce:	e7f2      	b.n	22b6 <nrfx_gpio_handler+0x22>
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    22d0:	4e02      	ldr	r6, [pc, #8]	; (22dc <nrfx_gpio_handler+0x48>)
    22d2:	e7e7      	b.n	22a4 <nrfx_gpio_handler+0x10>
    22d4:	4623      	mov	r3, r4
    22d6:	e7f8      	b.n	22ca <nrfx_gpio_handler+0x36>
    22d8:	00006f40 	.word	0x00006f40
    22dc:	00006f28 	.word	0x00006f28

000022e0 <gpio_nrfx_pin_configure>:
{
    22e0:	e92d 41ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr}
	return port->config;
    22e4:	6847      	ldr	r7, [r0, #4]
	nrfx_gpiote_pin_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    22e6:	f001 051f 	and.w	r5, r1, #31
    22ea:	7b3b      	ldrb	r3, [r7, #12]
{
    22ec:	4614      	mov	r4, r2
	nrfx_gpiote_pin_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    22ee:	ea45 1543 	orr.w	r5, r5, r3, lsl #5
{
    22f2:	460e      	mov	r6, r1
	err = nrfx_gpiote_channel_get(abs_pin, &ch);
    22f4:	4628      	mov	r0, r5
    22f6:	f10d 0103 	add.w	r1, sp, #3
    22fa:	f001 fcdd 	bl	3cb8 <nrfx_gpiote_channel_get>
	if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == GPIO_DISCONNECTED) {
    22fe:	f414 3f40 	tst.w	r4, #196608	; 0x30000
	err = nrfx_gpiote_channel_get(abs_pin, &ch);
    2302:	4680      	mov	r8, r0
	if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == GPIO_DISCONNECTED) {
    2304:	d10b      	bne.n	231e <gpio_nrfx_pin_configure+0x3e>
		(void)nrfx_gpiote_pin_uninit(abs_pin);
    2306:	4628      	mov	r0, r5
    2308:	f001 fd98 	bl	3e3c <nrfx_gpiote_pin_uninit>
		if (free_ch) {
    230c:	4b3c      	ldr	r3, [pc, #240]	; (2400 <gpio_nrfx_pin_configure+0x120>)
    230e:	4598      	cmp	r8, r3
    2310:	d103      	bne.n	231a <gpio_nrfx_pin_configure+0x3a>
			err = nrfx_gpiote_channel_free(ch);
    2312:	f89d 0003 	ldrb.w	r0, [sp, #3]
    2316:	f001 fd17 	bl	3d48 <nrfx_gpiote_channel_free>
		return 0;
    231a:	2000      	movs	r0, #0
    231c:	e00c      	b.n	2338 <gpio_nrfx_pin_configure+0x58>
	nrfx_gpiote_trigger_config_t trigger_config = {
    231e:	2300      	movs	r3, #0
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    2320:	4628      	mov	r0, r5
    2322:	4619      	mov	r1, r3
    2324:	aa02      	add	r2, sp, #8
	nrfx_gpiote_trigger_config_t trigger_config = {
    2326:	e9cd 3302 	strd	r3, r3, [sp, #8]
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    232a:	f001 fb9d 	bl	3a68 <nrfx_gpiote_input_configure>
	if (err != NRFX_SUCCESS) {
    232e:	4b34      	ldr	r3, [pc, #208]	; (2400 <gpio_nrfx_pin_configure+0x120>)
    2330:	4298      	cmp	r0, r3
    2332:	d004      	beq.n	233e <gpio_nrfx_pin_configure+0x5e>
		return NRF_GPIO_PIN_PULLUP;
    2334:	f06f 0015 	mvn.w	r0, #21
}
    2338:	b004      	add	sp, #16
    233a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	if (free_ch) {
    233e:	4580      	cmp	r8, r0
    2340:	d103      	bne.n	234a <gpio_nrfx_pin_configure+0x6a>
		err = nrfx_gpiote_channel_free(ch);
    2342:	f89d 0003 	ldrb.w	r0, [sp, #3]
    2346:	f001 fcff 	bl	3d48 <nrfx_gpiote_channel_free>
	if (flags & GPIO_OUTPUT) {
    234a:	03a3      	lsls	r3, r4, #14
    234c:	d549      	bpl.n	23e2 <gpio_nrfx_pin_configure+0x102>
	switch (flags & (NRF_GPIO_DRIVE_MSK | GPIO_OPEN_DRAIN)) {
    234e:	f240 3306 	movw	r3, #774	; 0x306
    2352:	4023      	ands	r3, r4
    2354:	f5b3 7f83 	cmp.w	r3, #262	; 0x106
    2358:	d019      	beq.n	238e <gpio_nrfx_pin_configure+0xae>
    235a:	d80c      	bhi.n	2376 <gpio_nrfx_pin_configure+0x96>
    235c:	2b06      	cmp	r3, #6
    235e:	d017      	beq.n	2390 <gpio_nrfx_pin_configure+0xb0>
    2360:	d804      	bhi.n	236c <gpio_nrfx_pin_configure+0x8c>
    2362:	b1ab      	cbz	r3, 2390 <gpio_nrfx_pin_configure+0xb0>
    2364:	2b02      	cmp	r3, #2
    2366:	d1e5      	bne.n	2334 <gpio_nrfx_pin_configure+0x54>
		*drive = NRF_GPIO_PIN_D0S1;
    2368:	2304      	movs	r3, #4
    236a:	e011      	b.n	2390 <gpio_nrfx_pin_configure+0xb0>
	switch (flags & (NRF_GPIO_DRIVE_MSK | GPIO_OPEN_DRAIN)) {
    236c:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
    2370:	d1e0      	bne.n	2334 <gpio_nrfx_pin_configure+0x54>
		*drive = NRF_GPIO_PIN_H0S1;
    2372:	2301      	movs	r3, #1
    2374:	e00c      	b.n	2390 <gpio_nrfx_pin_configure+0xb0>
	switch (flags & (NRF_GPIO_DRIVE_MSK | GPIO_OPEN_DRAIN)) {
    2376:	f240 2202 	movw	r2, #514	; 0x202
    237a:	4293      	cmp	r3, r2
    237c:	d026      	beq.n	23cc <gpio_nrfx_pin_configure+0xec>
    237e:	f5b3 7f40 	cmp.w	r3, #768	; 0x300
    2382:	d025      	beq.n	23d0 <gpio_nrfx_pin_configure+0xf0>
    2384:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
    2388:	d1d4      	bne.n	2334 <gpio_nrfx_pin_configure+0x54>
		*drive = NRF_GPIO_PIN_S0H1;
    238a:	2302      	movs	r3, #2
    238c:	e000      	b.n	2390 <gpio_nrfx_pin_configure+0xb0>
		*drive = NRF_GPIO_PIN_H0D1;
    238e:	2307      	movs	r3, #7
		nrfx_gpiote_output_config_t output_config = {
    2390:	f88d 3004 	strb.w	r3, [sp, #4]
				NRF_GPIO_PIN_INPUT_CONNECT :
    2394:	f484 3380 	eor.w	r3, r4, #65536	; 0x10000
    2398:	f3c3 4300 	ubfx	r3, r3, #16, #1
	if (flags & GPIO_PULL_UP) {
    239c:	06e0      	lsls	r0, r4, #27
		nrfx_gpiote_output_config_t output_config = {
    239e:	f88d 3005 	strb.w	r3, [sp, #5]
		return NRF_GPIO_PIN_PULLUP;
    23a2:	bf4c      	ite	mi
    23a4:	2303      	movmi	r3, #3
	} else if (flags & GPIO_PULL_DOWN) {
    23a6:	f3c4 1340 	ubfxpl	r3, r4, #5, #1
		if (flags & GPIO_OUTPUT_INIT_HIGH) {
    23aa:	0321      	lsls	r1, r4, #12
		nrfx_gpiote_output_config_t output_config = {
    23ac:	f88d 3006 	strb.w	r3, [sp, #6]
		if (flags & GPIO_OUTPUT_INIT_HIGH) {
    23b0:	d510      	bpl.n	23d4 <gpio_nrfx_pin_configure+0xf4>
			nrf_gpio_port_out_set(cfg->port, BIT(pin));
    23b2:	2301      	movs	r3, #1
    23b4:	687a      	ldr	r2, [r7, #4]
    23b6:	40b3      	lsls	r3, r6
    p_reg->OUTSET = set_mask;
    23b8:	6093      	str	r3, [r2, #8]
		err = nrfx_gpiote_output_configure(abs_pin, &output_config, NULL);
    23ba:	2200      	movs	r2, #0
    23bc:	4628      	mov	r0, r5
    23be:	a901      	add	r1, sp, #4
    23c0:	f001 fc00 	bl	3bc4 <nrfx_gpiote_output_configure>
	return (err != NRFX_SUCCESS) ? -EINVAL : 0;
    23c4:	4b0e      	ldr	r3, [pc, #56]	; (2400 <gpio_nrfx_pin_configure+0x120>)
    23c6:	4298      	cmp	r0, r3
    23c8:	d0a7      	beq.n	231a <gpio_nrfx_pin_configure+0x3a>
    23ca:	e7b3      	b.n	2334 <gpio_nrfx_pin_configure+0x54>
		*drive = NRF_GPIO_PIN_D0H1;
    23cc:	2305      	movs	r3, #5
    23ce:	e7df      	b.n	2390 <gpio_nrfx_pin_configure+0xb0>
	switch (flags & (NRF_GPIO_DRIVE_MSK | GPIO_OPEN_DRAIN)) {
    23d0:	2303      	movs	r3, #3
    23d2:	e7dd      	b.n	2390 <gpio_nrfx_pin_configure+0xb0>
		} else if (flags & GPIO_OUTPUT_INIT_LOW) {
    23d4:	0362      	lsls	r2, r4, #13
			nrf_gpio_port_out_clear(cfg->port, BIT(pin));
    23d6:	bf41      	itttt	mi
    23d8:	2301      	movmi	r3, #1
    23da:	687a      	ldrmi	r2, [r7, #4]
    23dc:	40b3      	lslmi	r3, r6
    p_reg->OUTCLR = clr_mask;
    23de:	60d3      	strmi	r3, [r2, #12]
}
    23e0:	e7eb      	b.n	23ba <gpio_nrfx_pin_configure+0xda>
	if (flags & GPIO_PULL_UP) {
    23e2:	06e3      	lsls	r3, r4, #27
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    23e4:	f04f 0300 	mov.w	r3, #0
		return NRF_GPIO_PIN_PULLUP;
    23e8:	bf4c      	ite	mi
    23ea:	2403      	movmi	r4, #3
	} else if (flags & GPIO_PULL_DOWN) {
    23ec:	f3c4 1440 	ubfxpl	r4, r4, #5, #1
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    23f0:	461a      	mov	r2, r3
    23f2:	4628      	mov	r0, r5
    23f4:	a901      	add	r1, sp, #4
	nrfx_gpiote_input_config_t input_config = {
    23f6:	f88d 4004 	strb.w	r4, [sp, #4]
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    23fa:	f001 fb35 	bl	3a68 <nrfx_gpiote_input_configure>
    23fe:	e7e1      	b.n	23c4 <gpio_nrfx_pin_configure+0xe4>
    2400:	0bad0000 	.word	0x0bad0000

00002404 <transfer_next_chunk>:
	return 0;
}
#endif

static void transfer_next_chunk(const struct device *dev)
{
    2404:	b57f      	push	{r0, r1, r2, r3, r4, r5, r6, lr}
	struct spi_nrfx_data *dev_data = dev->data;
    2406:	6904      	ldr	r4, [r0, #16]
	const struct spi_nrfx_config *dev_config = dev->config;
    2408:	6846      	ldr	r6, [r0, #4]
 * directions have a continuous buffer, i.e. the maximum SPI transfer that
 * can be done with DMA that handles only non-scattered buffers.
 */
static inline size_t spi_context_max_continuous_chunk(struct spi_context *ctx)
{
	if (!ctx->tx_len) {
    240a:	6ca5      	ldr	r5, [r4, #72]	; 0x48
		return ctx->rx_len;
    240c:	6d23      	ldr	r3, [r4, #80]	; 0x50
	if (!ctx->tx_len) {
    240e:	b98d      	cbnz	r5, 2434 <transfer_next_chunk+0x30>
	struct spi_context *ctx = &dev_data->ctx;
	int error = 0;

	size_t chunk_len = spi_context_max_continuous_chunk(ctx);

	if (chunk_len > 0) {
    2410:	2b00      	cmp	r3, #0
    2412:	d137      	bne.n	2484 <transfer_next_chunk+0x80>
	int error = 0;
    2414:	461d      	mov	r5, r3
	_spi_context_cs_control(ctx, on, false);
    2416:	2200      	movs	r2, #0
    2418:	4620      	mov	r0, r4
    241a:	4611      	mov	r1, r2
    241c:	f003 ffde 	bl	63dc <_spi_context_cs_control>
	ctx->sync_status = status;
    2420:	6325      	str	r5, [r4, #48]	; 0x30
		(void) arch_syscall_invoke1(parm0.x, K_SYSCALL_K_SEM_GIVE);
		return;
	}
#endif
	compiler_barrier();
	z_impl_k_sem_give(sem);
    2422:	f104 0020 	add.w	r0, r4, #32
    2426:	f002 fe59 	bl	50dc <z_impl_k_sem_give>
	spi_context_cs_control(ctx, false);

	LOG_DBG("Transaction finished with status %d", error);

	spi_context_complete(ctx, dev, error);
	dev_data->busy = false;
    242a:	2300      	movs	r3, #0
    242c:	f884 305c 	strb.w	r3, [r4, #92]	; 0x5c
}
    2430:	b004      	add	sp, #16
    2432:	bd70      	pop	{r4, r5, r6, pc}
		const uint8_t *tx_buf = ctx->tx_buf;
    2434:	6c61      	ldr	r1, [r4, #68]	; 0x44
	} else if (!ctx->rx_len) {
    2436:	bb0b      	cbnz	r3, 247c <transfer_next_chunk+0x78>
	return !!(ctx->tx_buf && ctx->tx_len);
    2438:	bb39      	cbnz	r1, 248a <transfer_next_chunk+0x86>
		if (chunk_len > MAX_CHUNK_LEN) {
    243a:	f64f 72ff 	movw	r2, #65535	; 0xffff
    243e:	42aa      	cmp	r2, r5
    2440:	bf28      	it	cs
    2442:	462a      	movcs	r2, r5
    2444:	6c63      	ldr	r3, [r4, #68]	; 0x44
		dev_data->chunk_len = chunk_len;
    2446:	65a2      	str	r2, [r4, #88]	; 0x58
		xfer.p_tx_buffer = tx_buf;
    2448:	9100      	str	r1, [sp, #0]
    244a:	b11b      	cbz	r3, 2454 <transfer_next_chunk+0x50>
    244c:	6ca3      	ldr	r3, [r4, #72]	; 0x48
		xfer.tx_length   = spi_context_tx_buf_on(ctx) ? chunk_len : 0;
    244e:	2b00      	cmp	r3, #0
    2450:	bf18      	it	ne
    2452:	4613      	movne	r3, r2
    2454:	9301      	str	r3, [sp, #4]
		xfer.p_rx_buffer = ctx->rx_buf;
    2456:	6ce3      	ldr	r3, [r4, #76]	; 0x4c
    2458:	9302      	str	r3, [sp, #8]
	return !!(ctx->rx_buf && ctx->rx_len);
    245a:	b11b      	cbz	r3, 2464 <transfer_next_chunk+0x60>
    245c:	6d23      	ldr	r3, [r4, #80]	; 0x50
		xfer.rx_length   = spi_context_rx_buf_on(ctx) ? chunk_len : 0;
    245e:	2b00      	cmp	r3, #0
    2460:	bf18      	it	ne
    2462:	4613      	movne	r3, r2
			result = nrfx_spim_xfer(&dev_config->spim, &xfer, 0);
    2464:	2200      	movs	r2, #0
    2466:	4669      	mov	r1, sp
    2468:	4630      	mov	r0, r6
		xfer.rx_length   = spi_context_rx_buf_on(ctx) ? chunk_len : 0;
    246a:	9303      	str	r3, [sp, #12]
			result = nrfx_spim_xfer(&dev_config->spim, &xfer, 0);
    246c:	f002 fade 	bl	4a2c <nrfx_spim_xfer>
			if (result == NRFX_SUCCESS) {
    2470:	4b0d      	ldr	r3, [pc, #52]	; (24a8 <transfer_next_chunk+0xa4>)
    2472:	4298      	cmp	r0, r3
    2474:	d0dc      	beq.n	2430 <transfer_next_chunk+0x2c>
			error = -EIO;
    2476:	f06f 0504 	mvn.w	r5, #4
    247a:	e7cc      	b.n	2416 <transfer_next_chunk+0x12>
		return ctx->tx_len;
	}

	return MIN(ctx->tx_len, ctx->rx_len);
    247c:	429d      	cmp	r5, r3
    247e:	bf28      	it	cs
    2480:	461d      	movcs	r5, r3
    2482:	e7d9      	b.n	2438 <transfer_next_chunk+0x34>
		const uint8_t *tx_buf = ctx->tx_buf;
    2484:	461d      	mov	r5, r3
    2486:	6c61      	ldr	r1, [r4, #68]	; 0x44
	return !!(ctx->tx_buf && ctx->tx_len);
    2488:	e7d7      	b.n	243a <transfer_next_chunk+0x36>

#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE bool nrfx_is_in_ram(void const * p_object)
{
    return ((((uint32_t)p_object) & 0xE0000000u) == 0x20000000u);
    248a:	f001 4360 	and.w	r3, r1, #3758096384	; 0xe0000000
		if (spi_context_tx_buf_on(ctx) && !nrfx_is_in_ram(tx_buf)) {
    248e:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
    2492:	d0d2      	beq.n	243a <transfer_next_chunk+0x36>
			if (chunk_len > CONFIG_SPI_NRFX_RAM_BUFFER_SIZE) {
    2494:	2d08      	cmp	r5, #8
    2496:	bf28      	it	cs
    2498:	2508      	movcs	r5, #8
			memcpy(dev_data->buffer, tx_buf, chunk_len);
    249a:	6e20      	ldr	r0, [r4, #96]	; 0x60
    249c:	462a      	mov	r2, r5
    249e:	f003 fe6e 	bl	617e <memcpy>
			tx_buf = dev_data->buffer;
    24a2:	6e21      	ldr	r1, [r4, #96]	; 0x60
    24a4:	e7c9      	b.n	243a <transfer_next_chunk+0x36>
    24a6:	bf00      	nop
    24a8:	0bad0000 	.word	0x0bad0000

000024ac <spi_nrfx_transceive>:

static int spi_nrfx_transceive(const struct device *dev,
			       const struct spi_config *spi_cfg,
			       const struct spi_buf_set *tx_bufs,
			       const struct spi_buf_set *rx_bufs)
{
    24ac:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    24b0:	469b      	mov	fp, r3
	if ((spi_cfg->operation & SPI_LOCK_ON) &&
    24b2:	888b      	ldrh	r3, [r1, #4]
    24b4:	4680      	mov	r8, r0
	struct spi_nrfx_data *dev_data = dev->data;
    24b6:	6904      	ldr	r4, [r0, #16]
    24b8:	0498      	lsls	r0, r3, #18
{
    24ba:	460e      	mov	r6, r1
    24bc:	4691      	mov	r9, r2
    24be:	b08b      	sub	sp, #44	; 0x2c
    24c0:	f100 80e3 	bmi.w	268a <spi_nrfx_transceive+0x1de>
	return z_impl_k_sem_take(sem, timeout);
    24c4:	f04f 32ff 	mov.w	r2, #4294967295
    24c8:	f04f 33ff 	mov.w	r3, #4294967295
    24cc:	f104 0010 	add.w	r0, r4, #16
    24d0:	f002 fe24 	bl	511c <z_impl_k_sem_take>
	ctx->owner = spi_cfg;
    24d4:	6066      	str	r6, [r4, #4]
	const struct spi_nrfx_config *dev_config = dev->config;
    24d6:	f8d8 3004 	ldr.w	r3, [r8, #4]
	struct spi_nrfx_data *dev_data = dev->data;
    24da:	f8d8 a010 	ldr.w	sl, [r8, #16]
	uint32_t max_freq = dev_config->max_freq;
    24de:	689d      	ldr	r5, [r3, #8]
	const struct spi_nrfx_config *dev_config = dev->config;
    24e0:	9301      	str	r3, [sp, #4]
	if (dev_data->initialized && spi_context_configured(ctx, spi_cfg)) {
    24e2:	f89a 305d 	ldrb.w	r3, [sl, #93]	; 0x5d
    24e6:	9302      	str	r3, [sp, #8]
    24e8:	b11b      	cbz	r3, 24f2 <spi_nrfx_transceive+0x46>
    24ea:	f8da 3000 	ldr.w	r3, [sl]
    24ee:	429e      	cmp	r6, r3
    24f0:	d079      	beq.n	25e6 <spi_nrfx_transceive+0x13a>
	if (spi_cfg->operation & SPI_HALF_DUPLEX) {
    24f2:	88b7      	ldrh	r7, [r6, #4]
    24f4:	0539      	lsls	r1, r7, #20
    24f6:	f100 80fd 	bmi.w	26f4 <spi_nrfx_transceive+0x248>
	if (spi_cfg->operation & SPI_MODE_LOOP) {
    24fa:	f017 0f09 	tst.w	r7, #9
    24fe:	f040 80f6 	bne.w	26ee <spi_nrfx_transceive+0x242>
	if (SPI_WORD_SIZE_GET(spi_cfg->operation) != 8) {
    2502:	f3c7 1345 	ubfx	r3, r7, #5, #6
    2506:	2b08      	cmp	r3, #8
    2508:	f040 80f1 	bne.w	26ee <spi_nrfx_transceive+0x242>
	if (spi_cfg->frequency < 125000) {
    250c:	6833      	ldr	r3, [r6, #0]
    250e:	9303      	str	r3, [sp, #12]
    2510:	9a03      	ldr	r2, [sp, #12]
    2512:	4b84      	ldr	r3, [pc, #528]	; (2724 <spi_nrfx_transceive+0x278>)
    2514:	429a      	cmp	r2, r3
    2516:	f240 80ea 	bls.w	26ee <spi_nrfx_transceive+0x242>
	if (max_freq > 16000000 &&
    251a:	4b83      	ldr	r3, [pc, #524]	; (2728 <spi_nrfx_transceive+0x27c>)
    251c:	429d      	cmp	r5, r3
    251e:	d907      	bls.n	2530 <spi_nrfx_transceive+0x84>
                        CLOCK_HFCLKCTRL_HCLK_Msk);
}

NRF_STATIC_INLINE nrf_clock_hfclk_div_t nrf_clock_hfclk_div_get(NRF_CLOCK_Type const * p_reg)
{
    return (nrf_clock_hfclk_div_t)((p_reg->HFCLKCTRL & CLOCK_HFCLKCTRL_HCLK_Msk)
    2520:	f04f 2250 	mov.w	r2, #1342197760	; 0x50005000
    2524:	f8d2 2558 	ldr.w	r2, [r2, #1368]	; 0x558
		max_freq = 16000000;
    2528:	f012 0f03 	tst.w	r2, #3
    252c:	bf18      	it	ne
    252e:	461d      	movne	r5, r3
	config = dev_config->def_config;
    2530:	9b01      	ldr	r3, [sp, #4]
    2532:	f10d 0c10 	add.w	ip, sp, #16
    2536:	f103 0e0c 	add.w	lr, r3, #12
    253a:	e8be 000f 	ldmia.w	lr!, {r0, r1, r2, r3}
    253e:	e8ac 000f 	stmia.w	ip!, {r0, r1, r2, r3}
	config.frequency = get_nrf_spim_frequency(MIN(spi_cfg->frequency,
    2542:	9b03      	ldr	r3, [sp, #12]
	config = dev_config->def_config;
    2544:	e89e 0003 	ldmia.w	lr, {r0, r1}
	config.frequency = get_nrf_spim_frequency(MIN(spi_cfg->frequency,
    2548:	42ab      	cmp	r3, r5
    254a:	bf28      	it	cs
    254c:	462b      	movcs	r3, r5
    254e:	461d      	mov	r5, r3
	if (frequency < 250000) {
    2550:	4b76      	ldr	r3, [pc, #472]	; (272c <spi_nrfx_transceive+0x280>)
	config = dev_config->def_config;
    2552:	e88c 0003 	stmia.w	ip, {r0, r1}
	if (frequency < 250000) {
    2556:	429d      	cmp	r5, r3
    2558:	f240 80a0 	bls.w	269c <spi_nrfx_transceive+0x1f0>
	} else if (frequency < 500000) {
    255c:	4b74      	ldr	r3, [pc, #464]	; (2730 <spi_nrfx_transceive+0x284>)
    255e:	429d      	cmp	r5, r3
    2560:	f240 809f 	bls.w	26a2 <spi_nrfx_transceive+0x1f6>
	} else if (frequency < 1000000) {
    2564:	4b73      	ldr	r3, [pc, #460]	; (2734 <spi_nrfx_transceive+0x288>)
    2566:	429d      	cmp	r5, r3
    2568:	f240 809e 	bls.w	26a8 <spi_nrfx_transceive+0x1fc>
	} else if (frequency < 2000000) {
    256c:	4b72      	ldr	r3, [pc, #456]	; (2738 <spi_nrfx_transceive+0x28c>)
    256e:	429d      	cmp	r5, r3
    2570:	f240 809d 	bls.w	26ae <spi_nrfx_transceive+0x202>
	} else if (frequency < 4000000) {
    2574:	4b71      	ldr	r3, [pc, #452]	; (273c <spi_nrfx_transceive+0x290>)
    2576:	429d      	cmp	r5, r3
    2578:	f240 809c 	bls.w	26b4 <spi_nrfx_transceive+0x208>
	} else if (frequency < 8000000) {
    257c:	4b70      	ldr	r3, [pc, #448]	; (2740 <spi_nrfx_transceive+0x294>)
    257e:	429d      	cmp	r5, r3
    2580:	f0c0 809b 	bcc.w	26ba <spi_nrfx_transceive+0x20e>
	} else if (frequency < 16000000) {
    2584:	4b68      	ldr	r3, [pc, #416]	; (2728 <spi_nrfx_transceive+0x27c>)
    2586:	429d      	cmp	r5, r3
    2588:	f0c0 809a 	bcc.w	26c0 <spi_nrfx_transceive+0x214>
		return NRF_SPIM_FREQ_16M;
    258c:	4b6d      	ldr	r3, [pc, #436]	; (2744 <spi_nrfx_transceive+0x298>)
    258e:	429d      	cmp	r5, r3
    2590:	bf2c      	ite	cs
    2592:	f04f 55a0 	movcs.w	r5, #335544320	; 0x14000000
    2596:	f04f 6520 	movcc.w	r5, #167772160	; 0xa000000
	if (SPI_MODE_GET(operation) & SPI_MODE_CPOL) {
    259a:	07ba      	lsls	r2, r7, #30
	config.frequency = get_nrf_spim_frequency(MIN(spi_cfg->frequency,
    259c:	9506      	str	r5, [sp, #24]
	if (SPI_MODE_GET(operation) & SPI_MODE_CPOL) {
    259e:	f007 0304 	and.w	r3, r7, #4
    25a2:	f140 8090 	bpl.w	26c6 <spi_nrfx_transceive+0x21a>
			return NRF_SPIM_MODE_2;
    25a6:	2b00      	cmp	r3, #0
    25a8:	bf14      	ite	ne
    25aa:	2303      	movne	r3, #3
    25ac:	2302      	moveq	r3, #2
	config.mode      = get_nrf_spim_mode(spi_cfg->operation);
    25ae:	f88d 301c 	strb.w	r3, [sp, #28]
	if (dev_data->initialized) {
    25b2:	9b02      	ldr	r3, [sp, #8]
	if (operation & SPI_TRANSFER_LSB) {
    25b4:	f3c7 1700 	ubfx	r7, r7, #4, #1
	config.bit_order = get_nrf_spim_bit_order(spi_cfg->operation);
    25b8:	f88d 701d 	strb.w	r7, [sp, #29]
	if (dev_data->initialized) {
    25bc:	b12b      	cbz	r3, 25ca <spi_nrfx_transceive+0x11e>
		nrfx_spim_uninit(&dev_config->spim);
    25be:	9801      	ldr	r0, [sp, #4]
    25c0:	f002 f9e2 	bl	4988 <nrfx_spim_uninit>
		dev_data->initialized = false;
    25c4:	2300      	movs	r3, #0
    25c6:	f88a 305d 	strb.w	r3, [sl, #93]	; 0x5d
	result = nrfx_spim_init(&dev_config->spim, &config,
    25ca:	4653      	mov	r3, sl
    25cc:	4a5e      	ldr	r2, [pc, #376]	; (2748 <spi_nrfx_transceive+0x29c>)
    25ce:	9801      	ldr	r0, [sp, #4]
    25d0:	a904      	add	r1, sp, #16
    25d2:	f002 f8bb 	bl	474c <nrfx_spim_init>
	if (result != NRFX_SUCCESS) {
    25d6:	4b5d      	ldr	r3, [pc, #372]	; (274c <spi_nrfx_transceive+0x2a0>)
    25d8:	4298      	cmp	r0, r3
    25da:	d178      	bne.n	26ce <spi_nrfx_transceive+0x222>
	dev_data->initialized = true;
    25dc:	2301      	movs	r3, #1
	ctx->config = spi_cfg;
    25de:	f8ca 6000 	str.w	r6, [sl]
	dev_data->initialized = true;
    25e2:	f88a 305d 	strb.w	r3, [sl, #93]	; 0x5d
		dev_data->busy = true;
    25e6:	2301      	movs	r3, #1
    25e8:	f884 305c 	strb.w	r3, [r4, #92]	; 0x5c
	ctx->current_tx = tx_bufs ? tx_bufs->buffers : NULL;
    25ec:	f1b9 0f00 	cmp.w	r9, #0
    25f0:	f040 8083 	bne.w	26fa <spi_nrfx_transceive+0x24e>
    25f4:	f8c4 9034 	str.w	r9, [r4, #52]	; 0x34
	ctx->tx_count = ctx->current_tx ? tx_bufs->count : 0;
    25f8:	2300      	movs	r3, #0
    25fa:	63a3      	str	r3, [r4, #56]	; 0x38
		spi_context_get_next_buf(&ctx->current_tx, &ctx->tx_count,
    25fc:	f104 0248 	add.w	r2, r4, #72	; 0x48
    2600:	f104 0138 	add.w	r1, r4, #56	; 0x38
    2604:	f104 0034 	add.w	r0, r4, #52	; 0x34
    2608:	f003 fec1 	bl	638e <spi_context_get_next_buf.constprop.0>
	ctx->tx_buf = (const uint8_t *)
    260c:	6460      	str	r0, [r4, #68]	; 0x44
	ctx->current_rx = rx_bufs ? rx_bufs->buffers : NULL;
    260e:	f1bb 0f00 	cmp.w	fp, #0
    2612:	d17b      	bne.n	270c <spi_nrfx_transceive+0x260>
    2614:	f8c4 b03c 	str.w	fp, [r4, #60]	; 0x3c
	ctx->rx_count = ctx->current_rx ? rx_bufs->count : 0;
    2618:	2300      	movs	r3, #0
    261a:	6423      	str	r3, [r4, #64]	; 0x40
		spi_context_get_next_buf(&ctx->current_rx, &ctx->rx_count,
    261c:	f104 0250 	add.w	r2, r4, #80	; 0x50
    2620:	f104 0140 	add.w	r1, r4, #64	; 0x40
    2624:	f104 003c 	add.w	r0, r4, #60	; 0x3c
    2628:	f003 feb1 	bl	638e <spi_context_get_next_buf.constprop.0>
	ctx->sync_status = 0;
    262c:	2600      	movs	r6, #0
	_spi_context_cs_control(ctx, on, false);
    262e:	2101      	movs	r1, #1
    2630:	4632      	mov	r2, r6
	ctx->rx_buf = (uint8_t *)
    2632:	64e0      	str	r0, [r4, #76]	; 0x4c
	ctx->sync_status = 0;
    2634:	6326      	str	r6, [r4, #48]	; 0x30
	_spi_context_cs_control(ctx, on, false);
    2636:	4620      	mov	r0, r4
    2638:	f003 fed0 	bl	63dc <_spi_context_cs_control>
		transfer_next_chunk(dev);
    263c:	4640      	mov	r0, r8
    263e:	f7ff fee1 	bl	2404 <transfer_next_chunk>
		timeout_ms = MAX(ctx->tx_len, ctx->rx_len) * 8 * 1000 /
    2642:	6d25      	ldr	r5, [r4, #80]	; 0x50
    2644:	6ca3      	ldr	r3, [r4, #72]	; 0x48
			     ctx->config->frequency;
    2646:	4627      	mov	r7, r4
		timeout_ms = MAX(ctx->tx_len, ctx->rx_len) * 8 * 1000 /
    2648:	429d      	cmp	r5, r3
    264a:	bf38      	it	cc
    264c:	461d      	movcc	r5, r3
    264e:	f44f 53fa 	mov.w	r3, #8000	; 0x1f40
    2652:	435d      	muls	r5, r3
			     ctx->config->frequency;
    2654:	f857 3b20 	ldr.w	r3, [r7], #32
			/* Faster algorithm but source is first multiplied by target frequency
			 * and it can overflow even though final result would not overflow.
			 * Kconfig option shall prevent use of this algorithm when there is a
			 * risk of overflow.
			 */
			return ((t * to_hz + off) / from_hz);
    2658:	f44f 4c00 	mov.w	ip, #32768	; 0x8000
		timeout_ms = MAX(ctx->tx_len, ctx->rx_len) * 8 * 1000 /
    265c:	681b      	ldr	r3, [r3, #0]
    265e:	4631      	mov	r1, r6
    2660:	fbb5 f5f3 	udiv	r5, r5, r3
    2664:	f240 30e7 	movw	r0, #999	; 0x3e7
		timeout_ms += CONFIG_SPI_COMPLETION_TIMEOUT_TOLERANCE;
    2668:	35c8      	adds	r5, #200	; 0xc8
    266a:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    266e:	2300      	movs	r3, #0
    2670:	fbe5 010c 	umlal	r0, r1, r5, ip
    2674:	f7fd fd6e 	bl	154 <__aeabi_uldivmod>
    2678:	4602      	mov	r2, r0
    267a:	460b      	mov	r3, r1
    267c:	4638      	mov	r0, r7
    267e:	f002 fd4d 	bl	511c <z_impl_k_sem_take>
	if (k_sem_take(&ctx->sync, timeout)) {
    2682:	2800      	cmp	r0, #0
    2684:	d14a      	bne.n	271c <spi_nrfx_transceive+0x270>
	status = ctx->sync_status;
    2686:	6b25      	ldr	r5, [r4, #48]	; 0x30
	return status;
    2688:	e023      	b.n	26d2 <spi_nrfx_transceive+0x226>
	if ((spi_cfg->operation & SPI_LOCK_ON) &&
    268a:	69a3      	ldr	r3, [r4, #24]
    268c:	2b00      	cmp	r3, #0
    268e:	f47f af19 	bne.w	24c4 <spi_nrfx_transceive+0x18>
		(k_sem_count_get(&ctx->lock) == 0) &&
    2692:	6863      	ldr	r3, [r4, #4]
    2694:	4299      	cmp	r1, r3
    2696:	f47f af15 	bne.w	24c4 <spi_nrfx_transceive+0x18>
    269a:	e71c      	b.n	24d6 <spi_nrfx_transceive+0x2a>
		return NRF_SPIM_FREQ_125K;
    269c:	f04f 7500 	mov.w	r5, #33554432	; 0x2000000
    26a0:	e77b      	b.n	259a <spi_nrfx_transceive+0xee>
		return NRF_SPIM_FREQ_250K;
    26a2:	f04f 6580 	mov.w	r5, #67108864	; 0x4000000
    26a6:	e778      	b.n	259a <spi_nrfx_transceive+0xee>
		return NRF_SPIM_FREQ_500K;
    26a8:	f04f 6500 	mov.w	r5, #134217728	; 0x8000000
    26ac:	e775      	b.n	259a <spi_nrfx_transceive+0xee>
		return NRF_SPIM_FREQ_1M;
    26ae:	f04f 5580 	mov.w	r5, #268435456	; 0x10000000
    26b2:	e772      	b.n	259a <spi_nrfx_transceive+0xee>
		return NRF_SPIM_FREQ_2M;
    26b4:	f04f 5500 	mov.w	r5, #536870912	; 0x20000000
    26b8:	e76f      	b.n	259a <spi_nrfx_transceive+0xee>
		return NRF_SPIM_FREQ_4M;
    26ba:	f04f 4580 	mov.w	r5, #1073741824	; 0x40000000
    26be:	e76c      	b.n	259a <spi_nrfx_transceive+0xee>
		return NRF_SPIM_FREQ_8M;
    26c0:	f04f 4500 	mov.w	r5, #2147483648	; 0x80000000
    26c4:	e769      	b.n	259a <spi_nrfx_transceive+0xee>
		if (SPI_MODE_GET(operation) & SPI_MODE_CPHA) {
    26c6:	3b00      	subs	r3, #0
    26c8:	bf18      	it	ne
    26ca:	2301      	movne	r3, #1
    26cc:	e76f      	b.n	25ae <spi_nrfx_transceive+0x102>
		return -EIO;
    26ce:	f06f 0504 	mvn.w	r5, #4
	if (!(ctx->config->operation & SPI_LOCK_ON)) {
    26d2:	6823      	ldr	r3, [r4, #0]
    26d4:	889b      	ldrh	r3, [r3, #4]
    26d6:	f413 5300 	ands.w	r3, r3, #8192	; 0x2000
    26da:	d104      	bne.n	26e6 <spi_nrfx_transceive+0x23a>
		ctx->owner = NULL;
    26dc:	6063      	str	r3, [r4, #4]
	z_impl_k_sem_give(sem);
    26de:	f104 0010 	add.w	r0, r4, #16
    26e2:	f002 fcfb 	bl	50dc <z_impl_k_sem_give>
	return transceive(dev, spi_cfg, tx_bufs, rx_bufs, false, NULL, NULL);
}
    26e6:	4628      	mov	r0, r5
    26e8:	b00b      	add	sp, #44	; 0x2c
    26ea:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		return -EINVAL;
    26ee:	f06f 0515 	mvn.w	r5, #21
    26f2:	e7ee      	b.n	26d2 <spi_nrfx_transceive+0x226>
		return -ENOTSUP;
    26f4:	f06f 0585 	mvn.w	r5, #133	; 0x85
    26f8:	e7eb      	b.n	26d2 <spi_nrfx_transceive+0x226>
	ctx->current_tx = tx_bufs ? tx_bufs->buffers : NULL;
    26fa:	f8d9 3000 	ldr.w	r3, [r9]
    26fe:	6363      	str	r3, [r4, #52]	; 0x34
	ctx->tx_count = ctx->current_tx ? tx_bufs->count : 0;
    2700:	2b00      	cmp	r3, #0
    2702:	f43f af79 	beq.w	25f8 <spi_nrfx_transceive+0x14c>
    2706:	f8d9 3004 	ldr.w	r3, [r9, #4]
    270a:	e776      	b.n	25fa <spi_nrfx_transceive+0x14e>
	ctx->current_rx = rx_bufs ? rx_bufs->buffers : NULL;
    270c:	f8db 3000 	ldr.w	r3, [fp]
    2710:	63e3      	str	r3, [r4, #60]	; 0x3c
	ctx->rx_count = ctx->current_rx ? rx_bufs->count : 0;
    2712:	2b00      	cmp	r3, #0
    2714:	d080      	beq.n	2618 <spi_nrfx_transceive+0x16c>
    2716:	f8db 3004 	ldr.w	r3, [fp, #4]
    271a:	e77e      	b.n	261a <spi_nrfx_transceive+0x16e>
		return -ETIMEDOUT;
    271c:	f06f 0573 	mvn.w	r5, #115	; 0x73
    2720:	e7d7      	b.n	26d2 <spi_nrfx_transceive+0x226>
    2722:	bf00      	nop
    2724:	0001e847 	.word	0x0001e847
    2728:	00f42400 	.word	0x00f42400
    272c:	0003d08f 	.word	0x0003d08f
    2730:	0007a11f 	.word	0x0007a11f
    2734:	000f423f 	.word	0x000f423f
    2738:	001e847f 	.word	0x001e847f
    273c:	003d08ff 	.word	0x003d08ff
    2740:	007a1200 	.word	0x007a1200
    2744:	01e84800 	.word	0x01e84800
    2748:	00006511 	.word	0x00006511
    274c:	0bad0000 	.word	0x0bad0000

00002750 <qspi_get_zephyr_ret_code>:
/**
 * @brief Converts NRFX return codes to the zephyr ones
 */
static inline int qspi_get_zephyr_ret_code(nrfx_err_t res)
{
	switch (res) {
    2750:	f100 4074 	add.w	r0, r0, #4093640704	; 0xf4000000
    2754:	f500 00a6 	add.w	r0, r0, #5439488	; 0x530000
    2758:	280a      	cmp	r0, #10
    275a:	bf9a      	itte	ls
    275c:	4b02      	ldrls	r3, [pc, #8]	; (2768 <qspi_get_zephyr_ret_code+0x18>)
    275e:	f933 0010 	ldrshls.w	r0, [r3, r0, lsl #1]
{
    2762:	f06f 000f 	mvnhi.w	r0, #15
	case NRFX_ERROR_BUSY:
	case NRFX_ERROR_TIMEOUT:
	default:
		return -EBUSY;
	}
}
    2766:	4770      	bx	lr
    2768:	00007560 	.word	0x00007560

0000276c <qspi_nor_pages_layout>:

static void qspi_nor_pages_layout(const struct device *dev,
				  const struct flash_pages_layout **layout,
				  size_t *layout_size)
{
	*layout = &dev_layout;
    276c:	4b02      	ldr	r3, [pc, #8]	; (2778 <qspi_nor_pages_layout+0xc>)
    276e:	600b      	str	r3, [r1, #0]
	*layout_size = 1;
    2770:	2301      	movs	r3, #1
    2772:	6013      	str	r3, [r2, #0]
}
    2774:	4770      	bx	lr
    2776:	bf00      	nop
    2778:	0000744c 	.word	0x0000744c

0000277c <qspi_flash_get_parameters>:
		.write_block_size = 4,
		.erase_value = 0xff,
	};

	return &qspi_flash_parameters;
}
    277c:	4800      	ldr	r0, [pc, #0]	; (2780 <qspi_flash_get_parameters+0x4>)
    277e:	4770      	bx	lr
    2780:	000073e0 	.word	0x000073e0

00002784 <qspi_wait_for_completion.isra.0>:
	if (res == NRFX_SUCCESS) {
    2784:	4b05      	ldr	r3, [pc, #20]	; (279c <qspi_wait_for_completion.isra.0+0x18>)
    2786:	4299      	cmp	r1, r3
    2788:	d106      	bne.n	2798 <qspi_wait_for_completion.isra.0+0x14>
	return z_impl_k_sem_take(sem, timeout);
    278a:	f04f 32ff 	mov.w	r2, #4294967295
    278e:	f04f 33ff 	mov.w	r3, #4294967295
    2792:	3020      	adds	r0, #32
    2794:	f002 bcc2 	b.w	511c <z_impl_k_sem_take>
}
    2798:	4770      	bx	lr
    279a:	bf00      	nop
    279c:	0bad0000 	.word	0x0bad0000

000027a0 <qspi_device_init>:
{
    27a0:	b570      	push	{r4, r5, r6, lr}
	struct qspi_nor_data *dev_data = dev->data;
    27a2:	6905      	ldr	r5, [r0, #16]
{
    27a4:	4604      	mov	r4, r0
	if (!qspi_initialized) {
    27a6:	4e0f      	ldr	r6, [pc, #60]	; (27e4 <qspi_device_init+0x44>)
	qspi_lock(dev);
    27a8:	4628      	mov	r0, r5
    27aa:	f003 fefc 	bl	65a6 <qspi_lock.isra.0>
	k_sem_give(&dev_data->count);
    27ae:	f105 0030 	add.w	r0, r5, #48	; 0x30
    27b2:	f003 fef0 	bl	6596 <k_sem_give>
	if (!qspi_initialized) {
    27b6:	7833      	ldrb	r3, [r6, #0]
    27b8:	b98b      	cbnz	r3, 27de <qspi_device_init+0x3e>
		res = nrfx_qspi_init(&dev_config->nrfx_cfg,
    27ba:	462a      	mov	r2, r5
    27bc:	490a      	ldr	r1, [pc, #40]	; (27e8 <qspi_device_init+0x48>)
    27be:	6860      	ldr	r0, [r4, #4]
    27c0:	f001 fd94 	bl	42ec <nrfx_qspi_init>
		ret = qspi_get_zephyr_ret_code(res);
    27c4:	f7ff ffc4 	bl	2750 <qspi_get_zephyr_ret_code>
		qspi_initialized = (ret == 0);
    27c8:	fab0 f380 	clz	r3, r0
    27cc:	4605      	mov	r5, r0
    27ce:	095b      	lsrs	r3, r3, #5
    27d0:	7033      	strb	r3, [r6, #0]
	k_sem_give(&dev_data->sem);
    27d2:	6920      	ldr	r0, [r4, #16]
    27d4:	3010      	adds	r0, #16
    27d6:	f003 fede 	bl	6596 <k_sem_give>
}
    27da:	4628      	mov	r0, r5
    27dc:	bd70      	pop	{r4, r5, r6, pc}
	int ret = 0;
    27de:	2500      	movs	r5, #0
    27e0:	e7f7      	b.n	27d2 <qspi_device_init+0x32>
    27e2:	bf00      	nop
    27e4:	20000c3c 	.word	0x20000c3c
    27e8:	0000659b 	.word	0x0000659b

000027ec <qspi_device_uninit>:
{
    27ec:	b538      	push	{r3, r4, r5, lr}
    27ee:	4604      	mov	r4, r0
	qspi_lock(dev);
    27f0:	6900      	ldr	r0, [r0, #16]
    27f2:	f003 fed8 	bl	65a6 <qspi_lock.isra.0>
	struct qspi_nor_data *dev_data = dev->data;
    27f6:	6925      	ldr	r5, [r4, #16]
    27f8:	2200      	movs	r2, #0
    27fa:	2300      	movs	r3, #0
    27fc:	f105 0030 	add.w	r0, r5, #48	; 0x30
    2800:	f002 fc8c 	bl	511c <z_impl_k_sem_take>
	if (last) {
    2804:	6bab      	ldr	r3, [r5, #56]	; 0x38
    2806:	b94b      	cbnz	r3, 281c <qspi_device_uninit+0x30>
		while (nrfx_qspi_mem_busy_check() != NRFX_SUCCESS) {
    2808:	4d0a      	ldr	r5, [pc, #40]	; (2834 <qspi_device_uninit+0x48>)
    280a:	f001 fe89 	bl	4520 <nrfx_qspi_mem_busy_check>
    280e:	42a8      	cmp	r0, r5
    2810:	d10a      	bne.n	2828 <qspi_device_uninit+0x3c>
		nrfx_qspi_uninit();
    2812:	f001 fea7 	bl	4564 <nrfx_qspi_uninit>
		qspi_initialized = false;
    2816:	2200      	movs	r2, #0
    2818:	4b07      	ldr	r3, [pc, #28]	; (2838 <qspi_device_uninit+0x4c>)
    281a:	701a      	strb	r2, [r3, #0]
	k_sem_give(&dev_data->sem);
    281c:	6920      	ldr	r0, [r4, #16]
}
    281e:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
	k_sem_give(&dev_data->sem);
    2822:	3010      	adds	r0, #16
    2824:	f003 beb7 	b.w	6596 <k_sem_give>
	return z_impl_k_sleep(timeout);
    2828:	2100      	movs	r1, #0
    282a:	f240 6067 	movw	r0, #1639	; 0x667
    282e:	f002 ff65 	bl	56fc <z_impl_k_sleep>
    2832:	e7ea      	b.n	280a <qspi_device_uninit+0x1e>
    2834:	0bad0000 	.word	0x0bad0000
    2838:	20000c3c 	.word	0x20000c3c

0000283c <qspi_nor_read>:
{
    283c:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    2840:	4607      	mov	r7, r0
    2842:	4688      	mov	r8, r1
    2844:	461c      	mov	r4, r3
	if (!dest) {
    2846:	4616      	mov	r6, r2
{
    2848:	b085      	sub	sp, #20
	if (!dest) {
    284a:	2a00      	cmp	r2, #0
    284c:	f000 809a 	beq.w	2984 <qspi_nor_read+0x148>
	if (!size) {
    2850:	2b00      	cmp	r3, #0
    2852:	f000 8095 	beq.w	2980 <qspi_nor_read+0x144>
	if (addr < 0 ||
    2856:	2900      	cmp	r1, #0
	const struct qspi_nor_config *params = dev->config;
    2858:	6842      	ldr	r2, [r0, #4]
	if (addr < 0 ||
    285a:	f2c0 8093 	blt.w	2984 <qspi_nor_read+0x148>
    285e:	6992      	ldr	r2, [r2, #24]
	    (addr + size) > params->size) {
    2860:	18cb      	adds	r3, r1, r3
	if (addr < 0 ||
    2862:	4293      	cmp	r3, r2
    2864:	f200 808e 	bhi.w	2984 <qspi_nor_read+0x148>
	int rc = qspi_device_init(dev);
    2868:	f7ff ff9a 	bl	27a0 <qspi_device_init>
	if (rc != 0) {
    286c:	4605      	mov	r5, r0
    286e:	2800      	cmp	r0, #0
    2870:	d17f      	bne.n	2972 <qspi_nor_read+0x136>
	qspi_lock(dev);
    2872:	f1c8 0500 	rsb	r5, r8, #0
    2876:	f005 0503 	and.w	r5, r5, #3
    287a:	6938      	ldr	r0, [r7, #16]
    287c:	f003 fe93 	bl	65a6 <qspi_lock.isra.0>
	if (flash_prefix > size) {
    2880:	42a5      	cmp	r5, r4
    2882:	bf28      	it	cs
    2884:	4625      	movcs	r5, r4
	off_t dest_prefix = (WORD_SIZE - (off_t)dptr % WORD_SIZE) % WORD_SIZE;
    2886:	4273      	negs	r3, r6
    2888:	f003 0303 	and.w	r3, r3, #3
    288c:	f006 0903 	and.w	r9, r6, #3
    2890:	bf58      	it	pl
    2892:	f1c3 0900 	rsbpl	r9, r3, #0
    2896:	f1c9 0900 	rsb	r9, r9, #0
    289a:	f009 0903 	and.w	r9, r9, #3
    289e:	45a1      	cmp	r9, r4
    28a0:	bf28      	it	cs
    28a2:	46a1      	movcs	r9, r4
	off_t flash_suffix = (size - flash_prefix) % WORD_SIZE;
    28a4:	1b63      	subs	r3, r4, r5
			    (size - dest_prefix) % WORD_SIZE;
    28a6:	eba4 0409 	sub.w	r4, r4, r9
    28aa:	f024 0403 	bic.w	r4, r4, #3
	off_t flash_middle = size - flash_prefix - flash_suffix;
    28ae:	f023 0a03 	bic.w	sl, r3, #3
	if (flash_middle > dest_middle) {
    28b2:	45a2      	cmp	sl, r4
		flash_suffix = size - flash_prefix - flash_middle;
    28b4:	bfc8      	it	gt
    28b6:	46a2      	movgt	sl, r4
    28b8:	f003 0b03 	and.w	fp, r3, #3
    28bc:	bfc8      	it	gt
    28be:	eba3 0b04 	subgt.w	fp, r3, r4
	if (flash_middle != 0) {
    28c2:	f1ba 0f00 	cmp.w	sl, #0
    28c6:	d018      	beq.n	28fa <qspi_nor_read+0xbe>
		res = nrfx_qspi_read(dptr + dest_prefix, flash_middle,
    28c8:	eb06 0309 	add.w	r3, r6, r9
    28cc:	eb08 0205 	add.w	r2, r8, r5
    28d0:	4651      	mov	r1, sl
    28d2:	4618      	mov	r0, r3
    28d4:	9301      	str	r3, [sp, #4]
    28d6:	f004 f943 	bl	6b60 <nrfx_qspi_read>
    28da:	4604      	mov	r4, r0
		qspi_wait_for_completion(dev, res);
    28dc:	4601      	mov	r1, r0
    28de:	6938      	ldr	r0, [r7, #16]
    28e0:	f7ff ff50 	bl	2784 <qspi_wait_for_completion.isra.0>
		if (res != NRFX_SUCCESS) {
    28e4:	4a29      	ldr	r2, [pc, #164]	; (298c <qspi_nor_read+0x150>)
    28e6:	4294      	cmp	r4, r2
    28e8:	d13b      	bne.n	2962 <qspi_nor_read+0x126>
		if (flash_prefix != dest_prefix) {
    28ea:	454d      	cmp	r5, r9
    28ec:	d005      	beq.n	28fa <qspi_nor_read+0xbe>
			memmove(dptr + flash_prefix, dptr + dest_prefix, flash_middle);
    28ee:	9b01      	ldr	r3, [sp, #4]
    28f0:	4652      	mov	r2, sl
    28f2:	4619      	mov	r1, r3
    28f4:	1970      	adds	r0, r6, r5
    28f6:	f003 fc2b 	bl	6150 <memmove>
	if (flash_prefix != 0) {
    28fa:	b1bd      	cbz	r5, 292c <qspi_nor_read+0xf0>
				     (WORD_SIZE - flash_prefix));
    28fc:	f1c5 0904 	rsb	r9, r5, #4
		res = nrfx_qspi_read(buf, WORD_SIZE, addr -
    2900:	2104      	movs	r1, #4
    2902:	eba8 0209 	sub.w	r2, r8, r9
    2906:	a802      	add	r0, sp, #8
    2908:	f004 f92a 	bl	6b60 <nrfx_qspi_read>
    290c:	4604      	mov	r4, r0
		qspi_wait_for_completion(dev, res);
    290e:	4601      	mov	r1, r0
    2910:	6938      	ldr	r0, [r7, #16]
    2912:	f7ff ff37 	bl	2784 <qspi_wait_for_completion.isra.0>
		if (res != NRFX_SUCCESS) {
    2916:	4b1d      	ldr	r3, [pc, #116]	; (298c <qspi_nor_read+0x150>)
    2918:	429c      	cmp	r4, r3
    291a:	d122      	bne.n	2962 <qspi_nor_read+0x126>
		memcpy(dptr, buf + WORD_SIZE - flash_prefix, flash_prefix);
    291c:	f109 0308 	add.w	r3, r9, #8
    2920:	462a      	mov	r2, r5
    2922:	4630      	mov	r0, r6
    2924:	eb0d 0103 	add.w	r1, sp, r3
    2928:	f003 fc29 	bl	617e <memcpy>
	if (flash_suffix != 0) {
    292c:	f1bb 0f00 	cmp.w	fp, #0
    2930:	d016      	beq.n	2960 <qspi_nor_read+0x124>
		res = nrfx_qspi_read(buf, WORD_SIZE * 2,
    2932:	2108      	movs	r1, #8
				     addr + flash_prefix + flash_middle);
    2934:	eb08 0205 	add.w	r2, r8, r5
		res = nrfx_qspi_read(buf, WORD_SIZE * 2,
    2938:	4452      	add	r2, sl
    293a:	eb0d 0001 	add.w	r0, sp, r1
    293e:	f004 f90f 	bl	6b60 <nrfx_qspi_read>
    2942:	4604      	mov	r4, r0
		qspi_wait_for_completion(dev, res);
    2944:	4601      	mov	r1, r0
    2946:	6938      	ldr	r0, [r7, #16]
    2948:	f7ff ff1c 	bl	2784 <qspi_wait_for_completion.isra.0>
		if (res != NRFX_SUCCESS) {
    294c:	4b0f      	ldr	r3, [pc, #60]	; (298c <qspi_nor_read+0x150>)
    294e:	429c      	cmp	r4, r3
    2950:	d107      	bne.n	2962 <qspi_nor_read+0x126>
		memcpy(dptr + flash_prefix + flash_middle, buf, flash_suffix);
    2952:	eb0a 0005 	add.w	r0, sl, r5
    2956:	465a      	mov	r2, fp
    2958:	a902      	add	r1, sp, #8
    295a:	4430      	add	r0, r6
    295c:	f003 fc0f 	bl	617e <memcpy>
	return res;
    2960:	4c0a      	ldr	r4, [pc, #40]	; (298c <qspi_nor_read+0x150>)
	k_sem_give(&dev_data->sem);
    2962:	6938      	ldr	r0, [r7, #16]
    2964:	3010      	adds	r0, #16
    2966:	f003 fe16 	bl	6596 <k_sem_give>
	rc = qspi_get_zephyr_ret_code(res);
    296a:	4620      	mov	r0, r4
    296c:	f7ff fef0 	bl	2750 <qspi_get_zephyr_ret_code>
    2970:	4605      	mov	r5, r0
	qspi_device_uninit(dev);
    2972:	4638      	mov	r0, r7
    2974:	f7ff ff3a 	bl	27ec <qspi_device_uninit>
}
    2978:	4628      	mov	r0, r5
    297a:	b005      	add	sp, #20
    297c:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		return 0;
    2980:	461d      	mov	r5, r3
    2982:	e7f9      	b.n	2978 <qspi_nor_read+0x13c>
		return -EINVAL;
    2984:	f06f 0515 	mvn.w	r5, #21
    2988:	e7f6      	b.n	2978 <qspi_nor_read+0x13c>
    298a:	bf00      	nop
    298c:	0bad0000 	.word	0x0bad0000

00002990 <qspi_nor_init>:

#if NRF_CLOCK_HAS_HFCLK192M
NRF_STATIC_INLINE
void nrf_clock_hfclk192m_div_set(NRF_CLOCK_Type * p_reg, nrf_clock_hfclk_div_t divider)
{
    p_reg->HFCLK192MCTRL = (((uint8_t)(divider) << CLOCK_HFCLK192MCTRL_HCLK192M_Pos) &
    2990:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    2994:	2202      	movs	r2, #2
{
    2996:	b570      	push	{r4, r5, r6, lr}
    2998:	f8c3 25b8 	str.w	r2, [r3, #1464]	; 0x5b8
	int ret = pinctrl_apply_state(dev_config->pcfg, PINCTRL_STATE_DEFAULT);
    299c:	6843      	ldr	r3, [r0, #4]
{
    299e:	b086      	sub	sp, #24
	int ret = pinctrl_apply_state(dev_config->pcfg, PINCTRL_STATE_DEFAULT);
    29a0:	6a1d      	ldr	r5, [r3, #32]
{
    29a2:	4604      	mov	r4, r0
				      uint8_t id)
{
	int ret;
	const struct pinctrl_state *state;

	ret = pinctrl_lookup_state(config, id, &state);
    29a4:	2100      	movs	r1, #0
    29a6:	4628      	mov	r0, r5
    29a8:	aa03      	add	r2, sp, #12
    29aa:	f003 ff17 	bl	67dc <pinctrl_lookup_state>
	if (ret < 0) {
    29ae:	2800      	cmp	r0, #0
    29b0:	db4e      	blt.n	2a50 <qspi_nor_init+0xc0>
		return ret;
	}

	return pinctrl_apply_state_direct(config, state);
    29b2:	9b03      	ldr	r3, [sp, #12]
	return pinctrl_configure_pins(state->pins, state->pin_cnt, reg);
    29b4:	682a      	ldr	r2, [r5, #0]
    29b6:	7919      	ldrb	r1, [r3, #4]
    29b8:	6818      	ldr	r0, [r3, #0]
    29ba:	f000 fd99 	bl	34f0 <pinctrl_configure_pins>
	if (ret < 0) {
    29be:	2800      	cmp	r0, #0
    29c0:	db46      	blt.n	2a50 <qspi_nor_init+0xc0>
	IRQ_CONNECT(DT_IRQN(QSPI_NODE), DT_IRQ(QSPI_NODE, priority),
    29c2:	2200      	movs	r2, #0
    29c4:	2101      	movs	r1, #1
    29c6:	202b      	movs	r0, #43	; 0x2b
    29c8:	f7fe fe0c 	bl	15e4 <z_arm_irq_priority_set>
	const struct qspi_nor_config *dev_config = dev->config;
    29cc:	6865      	ldr	r5, [r4, #4]
	nrfx_err_t res = nrfx_qspi_init(&dev_config->nrfx_cfg,
    29ce:	6922      	ldr	r2, [r4, #16]
    29d0:	4628      	mov	r0, r5
    29d2:	4933      	ldr	r1, [pc, #204]	; (2aa0 <qspi_nor_init+0x110>)
    29d4:	f001 fc8a 	bl	42ec <nrfx_qspi_init>
	int ret = qspi_get_zephyr_ret_code(res);
    29d8:	f7ff feba 	bl	2750 <qspi_get_zephyr_ret_code>
	if (ret < 0) {
    29dc:	2800      	cmp	r0, #0
    29de:	db37      	blt.n	2a50 <qspi_nor_init+0xc0>
		bool qe_value = (prot_if->writeoc == NRF_QSPI_WRITEOC_PP4IO) ||
    29e0:	7aeb      	ldrb	r3, [r5, #11]
				(prot_if->readoc == NRF_QSPI_READOC_READ4IO) ||
    29e2:	3b02      	subs	r3, #2
    29e4:	2b01      	cmp	r3, #1
    29e6:	d935      	bls.n	2a54 <qspi_nor_init+0xc4>
				(prot_if->writeoc == NRF_QSPI_WRITEOC_PP4O)  ||
    29e8:	7aad      	ldrb	r5, [r5, #10]
    29ea:	3d03      	subs	r5, #3
    29ec:	2d01      	cmp	r5, #1
    29ee:	bf8c      	ite	hi
    29f0:	2500      	movhi	r5, #0
    29f2:	2501      	movls	r5, #1
		ret = qspi_rdsr(dev, sr_num);
    29f4:	4620      	mov	r0, r4
    29f6:	f003 fe34 	bl	6662 <qspi_rdsr.constprop.0>
		if (ret < 0) {
    29fa:	2800      	cmp	r0, #0
    29fc:	db28      	blt.n	2a50 <qspi_nor_init+0xc0>
		uint8_t sr = (uint8_t)ret;
    29fe:	b2c2      	uxtb	r2, r0
		if (qe_state != qe_value) {
    2a00:	f3c0 1080 	ubfx	r0, r0, #6, #1
    2a04:	4285      	cmp	r5, r0
    2a06:	ad01      	add	r5, sp, #4
    2a08:	d126      	bne.n	2a58 <qspi_nor_init+0xc8>
	qspi_device_uninit(dev);
    2a0a:	4620      	mov	r0, r4
    2a0c:	f7ff feee 	bl	27ec <qspi_device_uninit>
	const struct qspi_cmd cmd = {
    2a10:	2603      	movs	r6, #3
    2a12:	2300      	movs	r3, #0
    2a14:	e9cd 6302 	strd	r6, r3, [sp, #8]
    2a18:	9304      	str	r3, [sp, #16]
    2a1a:	239f      	movs	r3, #159	; 0x9f
	int ret = qspi_device_init(dev);
    2a1c:	4620      	mov	r0, r4
	const struct qspi_buf rx_buf = {
    2a1e:	f8cd d004 	str.w	sp, [sp, #4]
	const struct qspi_cmd cmd = {
    2a22:	f88d 300c 	strb.w	r3, [sp, #12]
    2a26:	9505      	str	r5, [sp, #20]
	int ret = qspi_device_init(dev);
    2a28:	f7ff feba 	bl	27a0 <qspi_device_init>
	if (ret == 0) {
    2a2c:	4602      	mov	r2, r0
    2a2e:	bb88      	cbnz	r0, 2a94 <qspi_nor_init+0x104>
		ret = qspi_send_cmd(dev, &cmd, false);
    2a30:	4620      	mov	r0, r4
    2a32:	a903      	add	r1, sp, #12
    2a34:	f003 fdc4 	bl	65c0 <qspi_send_cmd>
    2a38:	4605      	mov	r5, r0
	qspi_device_uninit(dev);
    2a3a:	4620      	mov	r0, r4
    2a3c:	f7ff fed6 	bl	27ec <qspi_device_uninit>
	if (ret != 0) {
    2a40:	bb5d      	cbnz	r5, 2a9a <qspi_nor_init+0x10a>
	if (memcmp(qnc->id, id, SPI_NOR_MAX_ID_LEN) != 0) {
    2a42:	6860      	ldr	r0, [r4, #4]
    2a44:	4632      	mov	r2, r6
    2a46:	4669      	mov	r1, sp
    2a48:	301c      	adds	r0, #28
    2a4a:	f003 fb71 	bl	6130 <memcmp>
    2a4e:	bb20      	cbnz	r0, 2a9a <qspi_nor_init+0x10a>
}
    2a50:	b006      	add	sp, #24
    2a52:	bd70      	pop	{r4, r5, r6, pc}
				(prot_if->readoc == NRF_QSPI_READOC_READ4IO) ||
    2a54:	2501      	movs	r5, #1
    2a56:	e7cd      	b.n	29f4 <qspi_nor_init+0x64>
	uint8_t sr_array[2] = {0};
    2a58:	2300      	movs	r3, #0
			sr ^= qe_mask;
    2a5a:	f082 0240 	eor.w	r2, r2, #64	; 0x40
	uint8_t sr_array[2] = {0};
    2a5e:	f8ad 3000 	strh.w	r3, [sp]
		sr_array[0] = sr_val;
    2a62:	f88d 2000 	strb.w	r2, [sp]
	const struct qspi_buf sr_buf = {
    2a66:	2201      	movs	r2, #1
	ret = qspi_send_cmd(dev, &cmd, true);
    2a68:	4620      	mov	r0, r4
    2a6a:	a903      	add	r1, sp, #12
	struct qspi_cmd cmd = {
    2a6c:	e9cd 2302 	strd	r2, r3, [sp, #8]
	const struct qspi_buf sr_buf = {
    2a70:	f8cd d004 	str.w	sp, [sp, #4]
	struct qspi_cmd cmd = {
    2a74:	9305      	str	r3, [sp, #20]
    2a76:	f88d 200c 	strb.w	r2, [sp, #12]
    2a7a:	9504      	str	r5, [sp, #16]
	ret = qspi_send_cmd(dev, &cmd, true);
    2a7c:	f003 fda0 	bl	65c0 <qspi_send_cmd>
	if (ret == 0) {
    2a80:	2800      	cmp	r0, #0
    2a82:	d1e5      	bne.n	2a50 <qspi_nor_init+0xc0>
		ret = qspi_rdsr(dev, 1);
    2a84:	4620      	mov	r0, r4
    2a86:	f003 fdec 	bl	6662 <qspi_rdsr.constprop.0>
		 && ((ret & SPI_NOR_WIP_BIT) != 0U));
    2a8a:	2800      	cmp	r0, #0
    2a8c:	dbe0      	blt.n	2a50 <qspi_nor_init+0xc0>
    2a8e:	07c3      	lsls	r3, r0, #31
    2a90:	d4f8      	bmi.n	2a84 <qspi_nor_init+0xf4>
    2a92:	e7ba      	b.n	2a0a <qspi_nor_init+0x7a>
	qspi_device_uninit(dev);
    2a94:	4620      	mov	r0, r4
    2a96:	f7ff fea9 	bl	27ec <qspi_device_uninit>
		return -ENODEV;
    2a9a:	f06f 0012 	mvn.w	r0, #18
    2a9e:	e7d7      	b.n	2a50 <qspi_nor_init+0xc0>
    2aa0:	0000659b 	.word	0x0000659b

00002aa4 <qspi_nor_erase>:
{
    2aa4:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
	if (addr < 0 ||
    2aa8:	1e0d      	subs	r5, r1, #0
{
    2aaa:	4606      	mov	r6, r0
    2aac:	4690      	mov	r8, r2
	const struct qspi_nor_config *params = dev->config;
    2aae:	f8d0 9004 	ldr.w	r9, [r0, #4]
	if (addr < 0 ||
    2ab2:	db6a      	blt.n	2b8a <qspi_nor_erase+0xe6>
    2ab4:	f8d9 3018 	ldr.w	r3, [r9, #24]
	    (addr + size) > params->size) {
    2ab8:	18aa      	adds	r2, r5, r2
	if (addr < 0 ||
    2aba:	429a      	cmp	r2, r3
    2abc:	d865      	bhi.n	2b8a <qspi_nor_erase+0xe6>
	if ((addr % QSPI_SECTOR_SIZE) != 0) {
    2abe:	f3c5 020b 	ubfx	r2, r5, #0, #12
	if ((size == 0) || (size % QSPI_SECTOR_SIZE) != 0) {
    2ac2:	f1b8 0f00 	cmp.w	r8, #0
    2ac6:	d060      	beq.n	2b8a <qspi_nor_erase+0xe6>
    2ac8:	f3c8 030b 	ubfx	r3, r8, #0, #12
    2acc:	4313      	orrs	r3, r2
    2ace:	d15c      	bne.n	2b8a <qspi_nor_erase+0xe6>
	rv = qspi_device_init(dev);
    2ad0:	f7ff fe66 	bl	27a0 <qspi_device_init>
	if (rv != 0) {
    2ad4:	4604      	mov	r4, r0
    2ad6:	bb68      	cbnz	r0, 2b34 <qspi_nor_erase+0x90>
	qspi_trans_lock(dev);
    2ad8:	6930      	ldr	r0, [r6, #16]
    2ada:	f003 fd6b 	bl	65b4 <qspi_trans_lock.isra.0>
	rv = qspi_nor_write_protection_set(dev, false);
    2ade:	4621      	mov	r1, r4
    2ae0:	4630      	mov	r0, r6
    2ae2:	f003 fda9 	bl	6638 <qspi_nor_write_protection_set>
	if (rv != 0) {
    2ae6:	4604      	mov	r4, r0
    2ae8:	bb08      	cbnz	r0, 2b2e <qspi_nor_erase+0x8a>
	qspi_lock(dev);
    2aea:	6930      	ldr	r0, [r6, #16]
    2aec:	f003 fd5b 	bl	65a6 <qspi_lock.isra.0>
		if (res == NRFX_SUCCESS) {
    2af0:	f8df a09c 	ldr.w	sl, [pc, #156]	; 2b90 <qspi_nor_erase+0xec>
		if (size == params->size) {
    2af4:	f8d9 3018 	ldr.w	r3, [r9, #24]
    2af8:	4543      	cmp	r3, r8
    2afa:	d121      	bne.n	2b40 <qspi_nor_erase+0x9c>
			res = nrfx_qspi_chip_erase();
    2afc:	f004 f833 	bl	6b66 <nrfx_qspi_chip_erase>
    2b00:	46c3      	mov	fp, r8
    2b02:	4607      	mov	r7, r0
		qspi_wait_for_completion(dev, res);
    2b04:	4639      	mov	r1, r7
    2b06:	6930      	ldr	r0, [r6, #16]
    2b08:	f7ff fe3c 	bl	2784 <qspi_wait_for_completion.isra.0>
		if (res == NRFX_SUCCESS) {
    2b0c:	4557      	cmp	r7, sl
    2b0e:	d12c      	bne.n	2b6a <qspi_nor_erase+0xc6>
	while (size > 0) {
    2b10:	ebb8 080b 	subs.w	r8, r8, fp
			addr += adj;
    2b14:	445d      	add	r5, fp
	while (size > 0) {
    2b16:	d1ed      	bne.n	2af4 <qspi_nor_erase+0x50>
	k_sem_give(&dev_data->sem);
    2b18:	6930      	ldr	r0, [r6, #16]
    2b1a:	3010      	adds	r0, #16
    2b1c:	f003 fd3b 	bl	6596 <k_sem_give>
	int rv2 = qspi_nor_write_protection_set(dev, true);
    2b20:	2101      	movs	r1, #1
    2b22:	4630      	mov	r0, r6
    2b24:	f003 fd88 	bl	6638 <qspi_nor_write_protection_set>
    2b28:	2c00      	cmp	r4, #0
    2b2a:	bf08      	it	eq
    2b2c:	4604      	moveq	r4, r0
	k_sem_give(&dev_data->trans);
    2b2e:	6930      	ldr	r0, [r6, #16]
    2b30:	f003 fd31 	bl	6596 <k_sem_give>
	qspi_device_uninit(dev);
    2b34:	4630      	mov	r0, r6
    2b36:	f7ff fe59 	bl	27ec <qspi_device_uninit>
}
    2b3a:	4620      	mov	r0, r4
    2b3c:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
		} else if ((size >= QSPI_BLOCK_SIZE) &&
    2b40:	f5b8 3f80 	cmp.w	r8, #65536	; 0x10000
    2b44:	d309      	bcc.n	2b5a <qspi_nor_erase+0xb6>
			   QSPI_IS_BLOCK_ALIGNED(addr)) {
    2b46:	b2ab      	uxth	r3, r5
		} else if ((size >= QSPI_BLOCK_SIZE) &&
    2b48:	b9a3      	cbnz	r3, 2b74 <qspi_nor_erase+0xd0>
			res = nrfx_qspi_erase(NRF_QSPI_ERASE_LEN_64KB, addr);
    2b4a:	4629      	mov	r1, r5
    2b4c:	2001      	movs	r0, #1
    2b4e:	f001 fd57 	bl	4600 <nrfx_qspi_erase>
			adj = QSPI_BLOCK_SIZE;
    2b52:	f44f 3b80 	mov.w	fp, #65536	; 0x10000
			res = nrfx_qspi_erase(NRF_QSPI_ERASE_LEN_64KB, addr);
    2b56:	4607      	mov	r7, r0
			adj = QSPI_BLOCK_SIZE;
    2b58:	e7d4      	b.n	2b04 <qspi_nor_erase+0x60>
		} else if ((size >= QSPI_SECTOR_SIZE) &&
    2b5a:	f5b8 5f80 	cmp.w	r8, #4096	; 0x1000
    2b5e:	d209      	bcs.n	2b74 <qspi_nor_erase+0xd0>
		qspi_wait_for_completion(dev, res);
    2b60:	490c      	ldr	r1, [pc, #48]	; (2b94 <qspi_nor_erase+0xf0>)
    2b62:	6930      	ldr	r0, [r6, #16]
    2b64:	f7ff fe0e 	bl	2784 <qspi_wait_for_completion.isra.0>
			res = NRFX_ERROR_INVALID_PARAM;
    2b68:	4f0a      	ldr	r7, [pc, #40]	; (2b94 <qspi_nor_erase+0xf0>)
			rv = qspi_get_zephyr_ret_code(res);
    2b6a:	4638      	mov	r0, r7
    2b6c:	f7ff fdf0 	bl	2750 <qspi_get_zephyr_ret_code>
    2b70:	4604      	mov	r4, r0
			break;
    2b72:	e7d1      	b.n	2b18 <qspi_nor_erase+0x74>
			   QSPI_IS_SECTOR_ALIGNED(addr)) {
    2b74:	f3c5 000b 	ubfx	r0, r5, #0, #12
		} else if ((size >= QSPI_SECTOR_SIZE) &&
    2b78:	2800      	cmp	r0, #0
    2b7a:	d1f1      	bne.n	2b60 <qspi_nor_erase+0xbc>
			res = nrfx_qspi_erase(NRF_QSPI_ERASE_LEN_4KB, addr);
    2b7c:	4629      	mov	r1, r5
    2b7e:	f001 fd3f 	bl	4600 <nrfx_qspi_erase>
			adj = QSPI_SECTOR_SIZE;
    2b82:	f44f 5b80 	mov.w	fp, #4096	; 0x1000
			res = nrfx_qspi_erase(NRF_QSPI_ERASE_LEN_4KB, addr);
    2b86:	4607      	mov	r7, r0
			adj = QSPI_SECTOR_SIZE;
    2b88:	e7bc      	b.n	2b04 <qspi_nor_erase+0x60>
		return -EINVAL;
    2b8a:	f06f 0415 	mvn.w	r4, #21
    2b8e:	e7d4      	b.n	2b3a <qspi_nor_erase+0x96>
    2b90:	0bad0000 	.word	0x0bad0000
    2b94:	0bad0004 	.word	0x0bad0004

00002b98 <qspi_nor_write>:
{
    2b98:	e92d 47f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, r9, sl, lr}
    2b9c:	4605      	mov	r5, r0
    2b9e:	460f      	mov	r7, r1
    2ba0:	461e      	mov	r6, r3
	if (!src) {
    2ba2:	4690      	mov	r8, r2
    2ba4:	2a00      	cmp	r2, #0
    2ba6:	f000 8085 	beq.w	2cb4 <qspi_nor_write+0x11c>
	if ((size == 0)
    2baa:	2b00      	cmp	r3, #0
    2bac:	f000 8082 	beq.w	2cb4 <qspi_nor_write+0x11c>
	    || ((size > 4) && ((size % 4U) != 0))) {
    2bb0:	2b04      	cmp	r3, #4
    2bb2:	d901      	bls.n	2bb8 <qspi_nor_write+0x20>
    2bb4:	079a      	lsls	r2, r3, #30
    2bb6:	d17d      	bne.n	2cb4 <qspi_nor_write+0x11c>
	if ((addr % 4U) != 0) {
    2bb8:	07bb      	lsls	r3, r7, #30
    2bba:	d17b      	bne.n	2cb4 <qspi_nor_write+0x11c>
	if (addr < 0 ||
    2bbc:	2f00      	cmp	r7, #0
	const struct qspi_nor_config *params = dev->config;
    2bbe:	686a      	ldr	r2, [r5, #4]
	if (addr < 0 ||
    2bc0:	db78      	blt.n	2cb4 <qspi_nor_write+0x11c>
    2bc2:	6992      	ldr	r2, [r2, #24]
	    (addr + size) > params->size) {
    2bc4:	19bb      	adds	r3, r7, r6
	if (addr < 0 ||
    2bc6:	4293      	cmp	r3, r2
    2bc8:	d874      	bhi.n	2cb4 <qspi_nor_write+0x11c>
	int rc = qspi_device_init(dev);
    2bca:	4628      	mov	r0, r5
    2bcc:	f7ff fde8 	bl	27a0 <qspi_device_init>
	if (rc != 0) {
    2bd0:	4604      	mov	r4, r0
    2bd2:	2800      	cmp	r0, #0
    2bd4:	d163      	bne.n	2c9e <qspi_nor_write+0x106>
	qspi_trans_lock(dev);
    2bd6:	6928      	ldr	r0, [r5, #16]
    2bd8:	f003 fcec 	bl	65b4 <qspi_trans_lock.isra.0>
	res = qspi_nor_write_protection_set(dev, false);
    2bdc:	4621      	mov	r1, r4
    2bde:	4628      	mov	r0, r5
    2be0:	f003 fd2a 	bl	6638 <qspi_nor_write_protection_set>
    2be4:	4604      	mov	r4, r0
	qspi_lock(dev);
    2be6:	6928      	ldr	r0, [r5, #16]
    2be8:	f003 fcdd 	bl	65a6 <qspi_lock.isra.0>
	if (!res) {
    2bec:	2c00      	cmp	r4, #0
    2bee:	d143      	bne.n	2c78 <qspi_nor_write+0xe0>
		if (size < 4U) {
    2bf0:	2e03      	cmp	r6, #3
    2bf2:	d81e      	bhi.n	2c32 <qspi_nor_write+0x9a>
	res = nrfx_qspi_read(buf, sizeof(buf), addr);
    2bf4:	2104      	movs	r1, #4
    2bf6:	463a      	mov	r2, r7
    2bf8:	eb0d 0001 	add.w	r0, sp, r1
    2bfc:	f003 ffb0 	bl	6b60 <nrfx_qspi_read>
    2c00:	4604      	mov	r4, r0
	qspi_wait_for_completion(dev, res);
    2c02:	4601      	mov	r1, r0
    2c04:	6928      	ldr	r0, [r5, #16]
    2c06:	f7ff fdbd 	bl	2784 <qspi_wait_for_completion.isra.0>
	if (res == NRFX_SUCCESS) {
    2c0a:	4b2c      	ldr	r3, [pc, #176]	; (2cbc <qspi_nor_write+0x124>)
    2c0c:	429c      	cmp	r4, r3
    2c0e:	d133      	bne.n	2c78 <qspi_nor_write+0xe0>
		memcpy(buf, sptr, slen);
    2c10:	4632      	mov	r2, r6
    2c12:	4641      	mov	r1, r8
    2c14:	a801      	add	r0, sp, #4
    2c16:	f003 fab2 	bl	617e <memcpy>
		res = nrfx_qspi_write(buf, sizeof(buf), addr);
    2c1a:	2104      	movs	r1, #4
    2c1c:	463a      	mov	r2, r7
    2c1e:	eb0d 0001 	add.w	r0, sp, r1
			res = nrfx_qspi_write(src, size, addr);
    2c22:	f003 ff9a 	bl	6b5a <nrfx_qspi_write>
    2c26:	4604      	mov	r4, r0
			qspi_wait_for_completion(dev, res);
    2c28:	4601      	mov	r1, r0
    2c2a:	6928      	ldr	r0, [r5, #16]
    2c2c:	f7ff fdaa 	bl	2784 <qspi_wait_for_completion.isra.0>
    2c30:	e022      	b.n	2c78 <qspi_nor_write+0xe0>
    2c32:	f008 4360 	and.w	r3, r8, #3758096384	; 0xe0000000
		} else if (!nrfx_is_in_ram(src)) {
    2c36:	f1b3 5f00 	cmp.w	r3, #536870912	; 0x20000000
    2c3a:	d037      	beq.n	2cac <qspi_nor_write+0x114>
			if (res == NRFX_SUCCESS) {
    2c3c:	f8df a07c 	ldr.w	sl, [pc, #124]	; 2cbc <qspi_nor_write+0x124>
			size_t len = MIN(slen, sizeof(buf));
    2c40:	2e04      	cmp	r6, #4
    2c42:	46b1      	mov	r9, r6
    2c44:	bf28      	it	cs
    2c46:	f04f 0904 	movcs.w	r9, #4
			memcpy(buf, sp, len);
    2c4a:	4641      	mov	r1, r8
    2c4c:	464a      	mov	r2, r9
    2c4e:	a801      	add	r0, sp, #4
    2c50:	f003 fa95 	bl	617e <memcpy>
			res = nrfx_qspi_write(buf, sizeof(buf), addr);
    2c54:	2104      	movs	r1, #4
    2c56:	463a      	mov	r2, r7
    2c58:	eb0d 0001 	add.w	r0, sp, r1
    2c5c:	f003 ff7d 	bl	6b5a <nrfx_qspi_write>
    2c60:	4604      	mov	r4, r0
			qspi_wait_for_completion(dev, res);
    2c62:	4601      	mov	r1, r0
    2c64:	6928      	ldr	r0, [r5, #16]
    2c66:	f7ff fd8d 	bl	2784 <qspi_wait_for_completion.isra.0>
			if (res == NRFX_SUCCESS) {
    2c6a:	4554      	cmp	r4, sl
    2c6c:	d104      	bne.n	2c78 <qspi_nor_write+0xe0>
		while ((slen > 0) && (res == NRFX_SUCCESS)) {
    2c6e:	ebb6 0609 	subs.w	r6, r6, r9
				sp += len;
    2c72:	44c8      	add	r8, r9
				addr += len;
    2c74:	444f      	add	r7, r9
		while ((slen > 0) && (res == NRFX_SUCCESS)) {
    2c76:	d1e3      	bne.n	2c40 <qspi_nor_write+0xa8>
	k_sem_give(&dev_data->sem);
    2c78:	6928      	ldr	r0, [r5, #16]
    2c7a:	3010      	adds	r0, #16
    2c7c:	f003 fc8b 	bl	6596 <k_sem_give>
	int res2 = qspi_nor_write_protection_set(dev, true);
    2c80:	2101      	movs	r1, #1
    2c82:	4628      	mov	r0, r5
    2c84:	f003 fcd8 	bl	6638 <qspi_nor_write_protection_set>
    2c88:	4606      	mov	r6, r0
	k_sem_give(&dev_data->trans);
    2c8a:	6928      	ldr	r0, [r5, #16]
    2c8c:	f003 fc83 	bl	6596 <k_sem_give>
	rc = qspi_get_zephyr_ret_code(res);
    2c90:	2c00      	cmp	r4, #0
    2c92:	bf14      	ite	ne
    2c94:	4620      	movne	r0, r4
    2c96:	4630      	moveq	r0, r6
    2c98:	f7ff fd5a 	bl	2750 <qspi_get_zephyr_ret_code>
    2c9c:	4604      	mov	r4, r0
	qspi_device_uninit(dev);
    2c9e:	4628      	mov	r0, r5
    2ca0:	f7ff fda4 	bl	27ec <qspi_device_uninit>
}
    2ca4:	4620      	mov	r0, r4
    2ca6:	b002      	add	sp, #8
    2ca8:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
			res = nrfx_qspi_write(src, size, addr);
    2cac:	463a      	mov	r2, r7
    2cae:	4631      	mov	r1, r6
    2cb0:	4640      	mov	r0, r8
    2cb2:	e7b6      	b.n	2c22 <qspi_nor_write+0x8a>
		return -EINVAL;
    2cb4:	f06f 0415 	mvn.w	r4, #21
    2cb8:	e7f4      	b.n	2ca4 <qspi_nor_write+0x10c>
    2cba:	bf00      	nop
    2cbc:	0bad0000 	.word	0x0bad0000

00002cc0 <flash_nrf_pages_layout>:

static void flash_nrf_pages_layout(const struct device *dev,
				     const struct flash_pages_layout **layout,
				     size_t *layout_size)
{
	*layout = &dev_layout;
    2cc0:	4b02      	ldr	r3, [pc, #8]	; (2ccc <flash_nrf_pages_layout+0xc>)
    2cc2:	600b      	str	r3, [r1, #0]
	*layout_size = 1;
    2cc4:	2301      	movs	r3, #1
    2cc6:	6013      	str	r3, [r2, #0]
}
    2cc8:	4770      	bx	lr
    2cca:	bf00      	nop
    2ccc:	200009a0 	.word	0x200009a0

00002cd0 <flash_nrf_get_parameters>:
flash_nrf_get_parameters(const struct device *dev)
{
	ARG_UNUSED(dev);

	return &flash_nrf_parameters;
}
    2cd0:	4800      	ldr	r0, [pc, #0]	; (2cd4 <flash_nrf_get_parameters+0x4>)
    2cd2:	4770      	bx	lr
    2cd4:	00007468 	.word	0x00007468

00002cd8 <nrf_flash_init>:
	.page_layout = flash_nrf_pages_layout,
#endif
};

static int nrf_flash_init(const struct device *dev)
{
    2cd8:	b510      	push	{r4, lr}
	return z_impl_k_sem_init(sem, initial_count, limit);
    2cda:	2201      	movs	r2, #1
    2cdc:	4806      	ldr	r0, [pc, #24]	; (2cf8 <nrf_flash_init+0x20>)
    2cde:	4611      	mov	r1, r2
    2ce0:	f003 ffea 	bl	6cb8 <z_impl_k_sem_init>
#ifndef CONFIG_SOC_FLASH_NRF_RADIO_SYNC_NONE
	nrf_flash_sync_init();
#endif /* !CONFIG_SOC_FLASH_NRF_RADIO_SYNC_NONE */

#if defined(CONFIG_FLASH_PAGE_LAYOUT)
	dev_layout.pages_count = nrfx_nvmc_flash_page_count_get();
    2ce4:	f003 ff33 	bl	6b4e <nrfx_nvmc_flash_page_count_get>
    2ce8:	4c04      	ldr	r4, [pc, #16]	; (2cfc <nrf_flash_init+0x24>)
    2cea:	6020      	str	r0, [r4, #0]
	dev_layout.pages_size = nrfx_nvmc_flash_page_size_get();
    2cec:	f003 ff2c 	bl	6b48 <nrfx_nvmc_flash_page_size_get>
    2cf0:	6060      	str	r0, [r4, #4]
#endif

	return 0;
}
    2cf2:	2000      	movs	r0, #0
    2cf4:	bd10      	pop	{r4, pc}
    2cf6:	bf00      	nop
    2cf8:	200009a8 	.word	0x200009a8
    2cfc:	200009a0 	.word	0x200009a0

00002d00 <flash_nrf_erase>:
{
    2d00:	b570      	push	{r4, r5, r6, lr}
    2d02:	460c      	mov	r4, r1
    2d04:	4615      	mov	r5, r2
	uint32_t pg_size = nrfx_nvmc_flash_page_size_get();
    2d06:	f003 ff1f 	bl	6b48 <nrfx_nvmc_flash_page_size_get>
	if (is_regular_addr_valid(addr, size)) {
    2d0a:	4629      	mov	r1, r5
	uint32_t pg_size = nrfx_nvmc_flash_page_size_get();
    2d0c:	4606      	mov	r6, r0
	if (is_regular_addr_valid(addr, size)) {
    2d0e:	4620      	mov	r0, r4
    2d10:	f003 fcc2 	bl	6698 <is_regular_addr_valid>
    2d14:	b308      	cbz	r0, 2d5a <flash_nrf_erase+0x5a>
		if (((addr % pg_size) != 0) || ((size % pg_size) != 0)) {
    2d16:	fbb4 f3f6 	udiv	r3, r4, r6
    2d1a:	fb06 4313 	mls	r3, r6, r3, r4
    2d1e:	b9e3      	cbnz	r3, 2d5a <flash_nrf_erase+0x5a>
    2d20:	fbb5 f3f6 	udiv	r3, r5, r6
    2d24:	fb06 5313 	mls	r3, r6, r3, r5
    2d28:	b9bb      	cbnz	r3, 2d5a <flash_nrf_erase+0x5a>
		if (!n_pages) {
    2d2a:	42ae      	cmp	r6, r5
    2d2c:	d901      	bls.n	2d32 <flash_nrf_erase+0x32>
			return 0;
    2d2e:	2000      	movs	r0, #0
}
    2d30:	bd70      	pop	{r4, r5, r6, pc}
	return z_impl_k_sem_take(sem, timeout);
    2d32:	f04f 32ff 	mov.w	r2, #4294967295
    2d36:	f04f 33ff 	mov.w	r3, #4294967295
    2d3a:	4809      	ldr	r0, [pc, #36]	; (2d60 <flash_nrf_erase+0x60>)
    2d3c:	f002 f9ee 	bl	511c <z_impl_k_sem_take>

#endif /* !CONFIG_SOC_FLASH_NRF_RADIO_SYNC_NONE */

static int erase_op(void *context)
{
	uint32_t pg_size = nrfx_nvmc_flash_page_size_get();
    2d40:	f003 ff02 	bl	6b48 <nrfx_nvmc_flash_page_size_get>
    2d44:	4606      	mov	r6, r0
		if (nrfx_nvmc_page_partial_erase_continue()) {
			e_ctx->len -= pg_size;
			e_ctx->flash_addr += pg_size;
		}
#else
		(void)nrfx_nvmc_page_erase(e_ctx->flash_addr);
    2d46:	4620      	mov	r0, r4
    2d48:	f001 f98e 	bl	4068 <nrfx_nvmc_page_erase>
			}

		}
#endif /* !CONFIG_SOC_FLASH_NRF_RADIO_SYNC_NONE */

	} while (e_ctx->len > 0);
    2d4c:	1bad      	subs	r5, r5, r6
    2d4e:	4434      	add	r4, r6
    2d50:	d1f9      	bne.n	2d46 <flash_nrf_erase+0x46>
	z_impl_k_sem_give(sem);
    2d52:	4803      	ldr	r0, [pc, #12]	; (2d60 <flash_nrf_erase+0x60>)
    2d54:	f002 f9c2 	bl	50dc <z_impl_k_sem_give>
}
    2d58:	e7e9      	b.n	2d2e <flash_nrf_erase+0x2e>
			return -EINVAL;
    2d5a:	f06f 0015 	mvn.w	r0, #21
    2d5e:	e7e7      	b.n	2d30 <flash_nrf_erase+0x30>
    2d60:	200009a8 	.word	0x200009a8

00002d64 <flash_nrf_write>:
{
    2d64:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    2d66:	460e      	mov	r6, r1
	if (is_regular_addr_valid(addr, len)) {
    2d68:	4619      	mov	r1, r3
    2d6a:	4630      	mov	r0, r6
{
    2d6c:	4617      	mov	r7, r2
    2d6e:	461c      	mov	r4, r3
	if (is_regular_addr_valid(addr, len)) {
    2d70:	f003 fc92 	bl	6698 <is_regular_addr_valid>
    2d74:	b308      	cbz	r0, 2dba <flash_nrf_write+0x56>
	if (!is_aligned_32(addr) || (len % sizeof(uint32_t))) {
    2d76:	ea44 0506 	orr.w	r5, r4, r6
    2d7a:	f015 0503 	ands.w	r5, r5, #3
    2d7e:	d11c      	bne.n	2dba <flash_nrf_write+0x56>
	if (!len) {
    2d80:	b1a4      	cbz	r4, 2dac <flash_nrf_write+0x48>
	return z_impl_k_sem_take(sem, timeout);
    2d82:	f04f 32ff 	mov.w	r2, #4294967295
    2d86:	f04f 33ff 	mov.w	r3, #4294967295
    2d8a:	480d      	ldr	r0, [pc, #52]	; (2dc0 <flash_nrf_write+0x5c>)
    2d8c:	f002 f9c6 	bl	511c <z_impl_k_sem_take>
	w_ctx->flash_addr += shift;
	w_ctx->data_addr += shift;
	w_ctx->len -= shift;
}

static int write_op(void *context)
    2d90:	f024 0403 	bic.w	r4, r4, #3
		}
#endif /* !CONFIG_SOC_FLASH_NRF_RADIO_SYNC_NONE */
	}
#endif /* CONFIG_SOC_FLASH_NRF_EMULATE_ONE_BYTE_WRITE_ACCESS */
	/* Write all the 4-byte aligned data */
	while (w_ctx->len >= sizeof(uint32_t)) {
    2d94:	42a5      	cmp	r5, r4
    2d96:	eb06 0005 	add.w	r0, r6, r5
    2d9a:	d109      	bne.n	2db0 <flash_nrf_write+0x4c>

#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE bool nrf_nvmc_ready_check(NRF_NVMC_Type const * p_reg)
{
    return (bool)(p_reg->READY & NVMC_READY_READY_Msk);
    2d9c:	4a09      	ldr	r2, [pc, #36]	; (2dc4 <flash_nrf_write+0x60>)
    2d9e:	f8d2 3400 	ldr.w	r3, [r2, #1024]	; 0x400
	while (!nrfx_nvmc_write_done_check()) {
    2da2:	07db      	lsls	r3, r3, #31
    2da4:	d5fb      	bpl.n	2d9e <flash_nrf_write+0x3a>
	z_impl_k_sem_give(sem);
    2da6:	4806      	ldr	r0, [pc, #24]	; (2dc0 <flash_nrf_write+0x5c>)
    2da8:	f002 f998 	bl	50dc <z_impl_k_sem_give>
		return -EINVAL;
    2dac:	2000      	movs	r0, #0
}
    2dae:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
		if (SUSPEND_POFWARN()) {
			return -ECANCELED;
		}

		nrfx_nvmc_word_write(w_ctx->flash_addr,
    2db0:	5979      	ldr	r1, [r7, r5]
    2db2:	f001 f977 	bl	40a4 <nrfx_nvmc_word_write>
	w_ctx->len -= shift;
    2db6:	3504      	adds	r5, #4
}
    2db8:	e7ec      	b.n	2d94 <flash_nrf_write+0x30>
		return -EINVAL;
    2dba:	f06f 0015 	mvn.w	r0, #21
    2dbe:	e7f6      	b.n	2dae <flash_nrf_write+0x4a>
    2dc0:	200009a8 	.word	0x200009a8
    2dc4:	50039000 	.word	0x50039000

00002dc8 <uarte_nrfx_configure>:
	return 0;
}

static int uarte_nrfx_configure(const struct device *dev,
				const struct uart_config *cfg)
{
    2dc8:	b5f0      	push	{r4, r5, r6, r7, lr}
	struct uarte_nrfx_data *data = dev->data;
	nrf_uarte_config_t uarte_cfg;

#if defined(UARTE_CONFIG_STOP_Msk)
	switch (cfg->stop_bits) {
    2dca:	794b      	ldrb	r3, [r1, #5]
    2dcc:	2b01      	cmp	r3, #1
    2dce:	d029      	beq.n	2e24 <uarte_nrfx_configure+0x5c>
    2dd0:	2b03      	cmp	r3, #3
    2dd2:	d124      	bne.n	2e1e <uarte_nrfx_configure+0x56>
	case UART_CFG_STOP_BITS_1:
		uarte_cfg.stop = NRF_UARTE_STOP_ONE;
		break;
	case UART_CFG_STOP_BITS_2:
		uarte_cfg.stop = NRF_UARTE_STOP_TWO;
    2dd4:	2710      	movs	r7, #16
	if (cfg->stop_bits != UART_CFG_STOP_BITS_1) {
		return -ENOTSUP;
	}
#endif

	if (cfg->data_bits != UART_CFG_DATA_BITS_8) {
    2dd6:	798b      	ldrb	r3, [r1, #6]
    2dd8:	2b03      	cmp	r3, #3
    2dda:	d120      	bne.n	2e1e <uarte_nrfx_configure+0x56>
		return -ENOTSUP;
	}

	switch (cfg->flow_ctrl) {
    2ddc:	79ce      	ldrb	r6, [r1, #7]
    2dde:	b10e      	cbz	r6, 2de4 <uarte_nrfx_configure+0x1c>
    2de0:	2e01      	cmp	r6, #1
    2de2:	d11c      	bne.n	2e1e <uarte_nrfx_configure+0x56>
	}

#if defined(UARTE_CONFIG_PARITYTYPE_Msk)
	uarte_cfg.paritytype = NRF_UARTE_PARITYTYPE_EVEN;
#endif
	switch (cfg->parity) {
    2de4:	790a      	ldrb	r2, [r1, #4]
    2de6:	2a01      	cmp	r2, #1
    2de8:	d01e      	beq.n	2e28 <uarte_nrfx_configure+0x60>
    2dea:	2a02      	cmp	r2, #2
    2dec:	d020      	beq.n	2e30 <uarte_nrfx_configure+0x68>
    2dee:	b9b2      	cbnz	r2, 2e1e <uarte_nrfx_configure+0x56>
    2df0:	4614      	mov	r4, r2
#endif
	default:
		return -ENOTSUP;
	}

	if (baudrate_set(dev, cfg->baudrate) != 0) {
    2df2:	680b      	ldr	r3, [r1, #0]
	return config->uarte_regs;
    2df4:	6845      	ldr	r5, [r0, #4]
	switch (baudrate) {
    2df6:	f5b3 4f16 	cmp.w	r3, #38400	; 0x9600
	return config->uarte_regs;
    2dfa:	f8d5 c000 	ldr.w	ip, [r5]
	switch (baudrate) {
    2dfe:	d06e      	beq.n	2ede <uarte_nrfx_configure+0x116>
    2e00:	d833      	bhi.n	2e6a <uarte_nrfx_configure+0xa2>
    2e02:	f5b3 5f16 	cmp.w	r3, #9600	; 0x2580
    2e06:	d06d      	beq.n	2ee4 <uarte_nrfx_configure+0x11c>
    2e08:	d81c      	bhi.n	2e44 <uarte_nrfx_configure+0x7c>
    2e0a:	f5b3 6f96 	cmp.w	r3, #1200	; 0x4b0
    2e0e:	d06b      	beq.n	2ee8 <uarte_nrfx_configure+0x120>
    2e10:	d810      	bhi.n	2e34 <uarte_nrfx_configure+0x6c>
    2e12:	f5b3 7f96 	cmp.w	r3, #300	; 0x12c
    2e16:	d06a      	beq.n	2eee <uarte_nrfx_configure+0x126>
    2e18:	f5b3 7f16 	cmp.w	r3, #600	; 0x258
    2e1c:	d06a      	beq.n	2ef4 <uarte_nrfx_configure+0x12c>
		return -ENOTSUP;
    2e1e:	f06f 0085 	mvn.w	r0, #133	; 0x85
    2e22:	e05b      	b.n	2edc <uarte_nrfx_configure+0x114>
	switch (cfg->stop_bits) {
    2e24:	2700      	movs	r7, #0
    2e26:	e7d6      	b.n	2dd6 <uarte_nrfx_configure+0xe>
		uarte_cfg.paritytype = NRF_UARTE_PARITYTYPE_ODD;
    2e28:	f44f 7480 	mov.w	r4, #256	; 0x100
		uarte_cfg.parity = NRF_UARTE_PARITY_INCLUDED;
    2e2c:	220e      	movs	r2, #14
    2e2e:	e7e0      	b.n	2df2 <uarte_nrfx_configure+0x2a>
	uarte_cfg.paritytype = NRF_UARTE_PARITYTYPE_EVEN;
    2e30:	2400      	movs	r4, #0
    2e32:	e7fb      	b.n	2e2c <uarte_nrfx_configure+0x64>
	switch (baudrate) {
    2e34:	f5b3 6f16 	cmp.w	r3, #2400	; 0x960
    2e38:	d05f      	beq.n	2efa <uarte_nrfx_configure+0x132>
    2e3a:	f5b3 5f96 	cmp.w	r3, #4800	; 0x12c0
    2e3e:	d1ee      	bne.n	2e1e <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_4800;
    2e40:	4b38      	ldr	r3, [pc, #224]	; (2f24 <uarte_nrfx_configure+0x15c>)
    2e42:	e03c      	b.n	2ebe <uarte_nrfx_configure+0xf6>
	switch (baudrate) {
    2e44:	f5b3 4fe1 	cmp.w	r3, #28800	; 0x7080
    2e48:	d05a      	beq.n	2f00 <uarte_nrfx_configure+0x138>
    2e4a:	d807      	bhi.n	2e5c <uarte_nrfx_configure+0x94>
    2e4c:	f5b3 5f61 	cmp.w	r3, #14400	; 0x3840
    2e50:	d058      	beq.n	2f04 <uarte_nrfx_configure+0x13c>
    2e52:	f5b3 4f96 	cmp.w	r3, #19200	; 0x4b00
    2e56:	d1e2      	bne.n	2e1e <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_19200;
    2e58:	4b33      	ldr	r3, [pc, #204]	; (2f28 <uarte_nrfx_configure+0x160>)
    2e5a:	e030      	b.n	2ebe <uarte_nrfx_configure+0xf6>
	switch (baudrate) {
    2e5c:	f647 2512 	movw	r5, #31250	; 0x7a12
    2e60:	42ab      	cmp	r3, r5
    2e62:	d1dc      	bne.n	2e1e <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_31250;
    2e64:	f44f 0300 	mov.w	r3, #8388608	; 0x800000
    2e68:	e029      	b.n	2ebe <uarte_nrfx_configure+0xf6>
	switch (baudrate) {
    2e6a:	f5b3 3f61 	cmp.w	r3, #230400	; 0x38400
    2e6e:	d04b      	beq.n	2f08 <uarte_nrfx_configure+0x140>
    2e70:	d813      	bhi.n	2e9a <uarte_nrfx_configure+0xd2>
    2e72:	f5b3 3f96 	cmp.w	r3, #76800	; 0x12c00
    2e76:	d04a      	beq.n	2f0e <uarte_nrfx_configure+0x146>
    2e78:	d809      	bhi.n	2e8e <uarte_nrfx_configure+0xc6>
    2e7a:	f64d 25c0 	movw	r5, #56000	; 0xdac0
    2e7e:	42ab      	cmp	r3, r5
    2e80:	d047      	beq.n	2f12 <uarte_nrfx_configure+0x14a>
    2e82:	f5b3 4f61 	cmp.w	r3, #57600	; 0xe100
    2e86:	d1ca      	bne.n	2e1e <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_57600;
    2e88:	f44f 036b 	mov.w	r3, #15400960	; 0xeb0000
    2e8c:	e017      	b.n	2ebe <uarte_nrfx_configure+0xf6>
	switch (baudrate) {
    2e8e:	f5b3 3fe1 	cmp.w	r3, #115200	; 0x1c200
    2e92:	d1c4      	bne.n	2e1e <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_115200;
    2e94:	f04f 73eb 	mov.w	r3, #30801920	; 0x1d60000
    2e98:	e011      	b.n	2ebe <uarte_nrfx_configure+0xf6>
	switch (baudrate) {
    2e9a:	f5b3 2f61 	cmp.w	r3, #921600	; 0xe1000
    2e9e:	d03b      	beq.n	2f18 <uarte_nrfx_configure+0x150>
    2ea0:	d808      	bhi.n	2eb4 <uarte_nrfx_configure+0xec>
    2ea2:	4d22      	ldr	r5, [pc, #136]	; (2f2c <uarte_nrfx_configure+0x164>)
    2ea4:	42ab      	cmp	r3, r5
    2ea6:	d03a      	beq.n	2f1e <uarte_nrfx_configure+0x156>
    2ea8:	f5b3 2fe1 	cmp.w	r3, #460800	; 0x70800
    2eac:	d1b7      	bne.n	2e1e <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_460800;
    2eae:	f04f 63e8 	mov.w	r3, #121634816	; 0x7400000
    2eb2:	e004      	b.n	2ebe <uarte_nrfx_configure+0xf6>
	switch (baudrate) {
    2eb4:	4d1e      	ldr	r5, [pc, #120]	; (2f30 <uarte_nrfx_configure+0x168>)
    2eb6:	42ab      	cmp	r3, r5
    2eb8:	d1b1      	bne.n	2e1e <uarte_nrfx_configure+0x56>
		nrf_baudrate = NRF_UARTE_BAUDRATE_1000000;
    2eba:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
	struct uarte_nrfx_data *data = dev->data;
    2ebe:	6905      	ldr	r5, [r0, #16]
                    | (uint32_t)p_cfg->hwfc;
}

NRF_STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate)
{
    p_reg->BAUDRATE = baudrate;
    2ec0:	f8cc 3524 	str.w	r3, [ip, #1316]	; 0x524
	return config->uarte_regs;
    2ec4:	6843      	ldr	r3, [r0, #4]
                    | (uint32_t)p_cfg->stop
    2ec6:	433a      	orrs	r2, r7
    2ec8:	681b      	ldr	r3, [r3, #0]
                    | (uint32_t)p_cfg->hwfc;
    2eca:	4334      	orrs	r4, r6
    2ecc:	4322      	orrs	r2, r4
    p_reg->CONFIG = (uint32_t)p_cfg->parity
    2ece:	f8c3 256c 	str.w	r2, [r3, #1388]	; 0x56c
		return -ENOTSUP;
	}

	nrf_uarte_configure(get_uarte_instance(dev), &uarte_cfg);

	data->uart_config = *cfg;
    2ed2:	1d2b      	adds	r3, r5, #4
    2ed4:	c903      	ldmia	r1, {r0, r1}
    2ed6:	e883 0003 	stmia.w	r3, {r0, r1}

	return 0;
    2eda:	2000      	movs	r0, #0
}
    2edc:	bdf0      	pop	{r4, r5, r6, r7, pc}
		nrf_baudrate = NRF_UARTE_BAUDRATE_38400;
    2ede:	f44f 031d 	mov.w	r3, #10289152	; 0x9d0000
    2ee2:	e7ec      	b.n	2ebe <uarte_nrfx_configure+0xf6>
		nrf_baudrate = NRF_UARTE_BAUDRATE_9600;
    2ee4:	4b13      	ldr	r3, [pc, #76]	; (2f34 <uarte_nrfx_configure+0x16c>)
    2ee6:	e7ea      	b.n	2ebe <uarte_nrfx_configure+0xf6>
		nrf_baudrate = NRF_UARTE_BAUDRATE_1200;
    2ee8:	f44f 239e 	mov.w	r3, #323584	; 0x4f000
    2eec:	e7e7      	b.n	2ebe <uarte_nrfx_configure+0xf6>
		nrf_baudrate = 0x00014000;
    2eee:	f44f 33a0 	mov.w	r3, #81920	; 0x14000
    2ef2:	e7e4      	b.n	2ebe <uarte_nrfx_configure+0xf6>
	switch (baudrate) {
    2ef4:	f44f 331c 	mov.w	r3, #159744	; 0x27000
    2ef8:	e7e1      	b.n	2ebe <uarte_nrfx_configure+0xf6>
		nrf_baudrate = NRF_UARTE_BAUDRATE_2400;
    2efa:	f44f 231d 	mov.w	r3, #643072	; 0x9d000
    2efe:	e7de      	b.n	2ebe <uarte_nrfx_configure+0xf6>
		nrf_baudrate = NRF_UARTE_BAUDRATE_28800;
    2f00:	4b0d      	ldr	r3, [pc, #52]	; (2f38 <uarte_nrfx_configure+0x170>)
    2f02:	e7dc      	b.n	2ebe <uarte_nrfx_configure+0xf6>
		nrf_baudrate = NRF_UARTE_BAUDRATE_14400;
    2f04:	4b0d      	ldr	r3, [pc, #52]	; (2f3c <uarte_nrfx_configure+0x174>)
    2f06:	e7da      	b.n	2ebe <uarte_nrfx_configure+0xf6>
		nrf_baudrate = NRF_UARTE_BAUDRATE_230400;
    2f08:	f04f 736c 	mov.w	r3, #61865984	; 0x3b00000
    2f0c:	e7d7      	b.n	2ebe <uarte_nrfx_configure+0xf6>
		nrf_baudrate = NRF_UARTE_BAUDRATE_76800;
    2f0e:	4b0c      	ldr	r3, [pc, #48]	; (2f40 <uarte_nrfx_configure+0x178>)
    2f10:	e7d5      	b.n	2ebe <uarte_nrfx_configure+0xf6>
		nrf_baudrate = NRF_UARTE_BAUDRATE_56000;
    2f12:	f44f 0365 	mov.w	r3, #15007744	; 0xe50000
    2f16:	e7d2      	b.n	2ebe <uarte_nrfx_configure+0xf6>
		nrf_baudrate = NRF_UARTE_BAUDRATE_921600;
    2f18:	f04f 6370 	mov.w	r3, #251658240	; 0xf000000
    2f1c:	e7cf      	b.n	2ebe <uarte_nrfx_configure+0xf6>
		nrf_baudrate = NRF_UARTE_BAUDRATE_250000;
    2f1e:	f04f 6380 	mov.w	r3, #67108864	; 0x4000000
    2f22:	e7cc      	b.n	2ebe <uarte_nrfx_configure+0xf6>
    2f24:	0013b000 	.word	0x0013b000
    2f28:	004ea000 	.word	0x004ea000
    2f2c:	0003d090 	.word	0x0003d090
    2f30:	000f4240 	.word	0x000f4240
    2f34:	00275000 	.word	0x00275000
    2f38:	0075c000 	.word	0x0075c000
    2f3c:	003af000 	.word	0x003af000
    2f40:	013a9000 	.word	0x013a9000

00002f44 <uarte_0_init>:
		(__attribute__((__section__(LINKER_DT_NODE_REGION_NAME(	       \
			DT_PHANDLE(UARTE(idx), memory_regions)))))),	       \
		())

#ifdef CONFIG_UART_0_NRF_UARTE
UART_NRF_UARTE_DEVICE(0);
    2f44:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    2f48:	4680      	mov	r8, r0
    2f4a:	2200      	movs	r2, #0
    2f4c:	2101      	movs	r1, #1
    2f4e:	2008      	movs	r0, #8
    2f50:	f7fe fb48 	bl	15e4 <z_arm_irq_priority_set>
    2f54:	2008      	movs	r0, #8
    2f56:	f7fe fb15 	bl	1584 <arch_irq_enable>
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
    2f5a:	2100      	movs	r1, #0
	const struct uarte_nrfx_config *config = dev->config;
    2f5c:	f8d8 7004 	ldr.w	r7, [r8, #4]
	struct uarte_nrfx_data *data = dev->data;
    2f60:	f8d8 6010 	ldr.w	r6, [r8, #16]
	return config->uarte_regs;
    2f64:	683c      	ldr	r4, [r7, #0]
	ret = pinctrl_lookup_state(config, id, &state);
    2f66:	aa01      	add	r2, sp, #4
    2f68:	f8c4 1500 	str.w	r1, [r4, #1280]	; 0x500
	data->dev = dev;
    2f6c:	f8c6 8000 	str.w	r8, [r6]
	err = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
    2f70:	f8d7 900c 	ldr.w	r9, [r7, #12]
    2f74:	4648      	mov	r0, r9
    2f76:	f003 fc31 	bl	67dc <pinctrl_lookup_state>
	if (ret < 0) {
    2f7a:	1e05      	subs	r5, r0, #0
    2f7c:	db4d      	blt.n	301a <uarte_0_init+0xd6>
	return pinctrl_apply_state_direct(config, state);
    2f7e:	9b01      	ldr	r3, [sp, #4]
	return pinctrl_configure_pins(state->pins, state->pin_cnt, reg);
    2f80:	f8d9 2000 	ldr.w	r2, [r9]
    2f84:	7919      	ldrb	r1, [r3, #4]
    2f86:	6818      	ldr	r0, [r3, #0]
    2f88:	f000 fab2 	bl	34f0 <pinctrl_configure_pins>
	if (err < 0) {
    2f8c:	1e05      	subs	r5, r0, #0
    2f8e:	db44      	blt.n	301a <uarte_0_init+0xd6>
	err = uarte_nrfx_configure(dev, &data->uart_config);
    2f90:	4640      	mov	r0, r8
    2f92:	1d31      	adds	r1, r6, #4
    2f94:	f7ff ff18 	bl	2dc8 <uarte_nrfx_configure>
	if (err) {
    2f98:	4605      	mov	r5, r0
    2f9a:	2800      	cmp	r0, #0
    2f9c:	d13d      	bne.n	301a <uarte_0_init+0xd6>
	    cfg->flags & UARTE_CFG_FLAG_PPI_ENDTX) {
    2f9e:	687b      	ldr	r3, [r7, #4]
	if (IS_ENABLED(CONFIG_UART_ENHANCED_POLL_OUT) &&
    2fa0:	0799      	lsls	r1, r3, #30
    2fa2:	d513      	bpl.n	2fcc <uarte_0_init+0x88>
	ret = gppi_channel_alloc(&data->ppi_ch_endtx);
    2fa4:	f106 0018 	add.w	r0, r6, #24
    2fa8:	f000 fcd8 	bl	395c <nrfx_dppi_channel_alloc>
	if (ret != NRFX_SUCCESS) {
    2fac:	4b1e      	ldr	r3, [pc, #120]	; (3028 <uarte_0_init+0xe4>)
    2fae:	4298      	cmp	r0, r3
    2fb0:	d137      	bne.n	3022 <uarte_0_init+0xde>
}

__STATIC_INLINE void nrfx_gppi_event_endpoint_setup(uint8_t channel, uint32_t eep)
{
    NRFX_ASSERT(eep);
    *((volatile uint32_t *)(eep + 0x80uL)) = ((uint32_t)channel | DPPIC_SUBSCRIBE_CHG_EN_EN_Msk);
    2fb2:	7e33      	ldrb	r3, [r6, #24]
    2fb4:	f043 4300 	orr.w	r3, r3, #2147483648	; 0x80000000
    2fb8:	f8c4 31a0 	str.w	r3, [r4, #416]	; 0x1a0
}

__STATIC_INLINE void nrfx_gppi_task_endpoint_setup(uint8_t channel, uint32_t tep)
{
    NRFX_ASSERT(tep);
    *((volatile uint32_t *)(tep + 0x80uL)) = ((uint32_t)channel | DPPIC_SUBSCRIBE_CHG_EN_EN_Msk);
    2fbc:	f8c4 308c 	str.w	r3, [r4, #140]	; 0x8c
	nrfx_gppi_channels_enable(BIT(data->ppi_ch_endtx));
    2fc0:	2301      	movs	r3, #1
    2fc2:	7e32      	ldrb	r2, [r6, #24]
    2fc4:	4093      	lsls	r3, r2
    p_reg->CHENCLR = 0xFFFFFFFFuL;
}

NRF_STATIC_INLINE void nrf_dppi_channels_enable(NRF_DPPIC_Type * p_reg, uint32_t mask)
{
    p_reg->CHENSET = mask;
    2fc6:	4a19      	ldr	r2, [pc, #100]	; (302c <uarte_0_init+0xe8>)
    2fc8:	f8c2 3504 	str.w	r3, [r2, #1284]	; 0x504
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
    2fcc:	2308      	movs	r3, #8
    2fce:	f8c4 3500 	str.w	r3, [r4, #1280]	; 0x500
		if (!cfg->disable_rx) {
    2fd2:	7a3b      	ldrb	r3, [r7, #8]
    2fd4:	b953      	cbnz	r3, 2fec <uarte_0_init+0xa8>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2fd6:	f8c4 3110 	str.w	r3, [r4, #272]	; 0x110
    2fda:	f8d4 3110 	ldr.w	r3, [r4, #272]	; 0x110

NRF_STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
                                               uint8_t *        p_buffer,
                                               size_t           length)
{
    p_reg->RXD.PTR    = (uint32_t)p_buffer;
    2fde:	6973      	ldr	r3, [r6, #20]
    2fe0:	f8c4 3534 	str.w	r3, [r4, #1332]	; 0x534
    p_reg->RXD.MAXCNT = length;
    2fe4:	2301      	movs	r3, #1
    2fe6:	f8c4 3538 	str.w	r3, [r4, #1336]	; 0x538
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2fea:	6023      	str	r3, [r4, #0]
	if (!(cfg->flags & UARTE_CFG_FLAG_PPI_ENDTX)) {
    2fec:	687b      	ldr	r3, [r7, #4]
    2fee:	079a      	lsls	r2, r3, #30
    p_reg->INTENSET = mask;
    2ff0:	bf5c      	itt	pl
    2ff2:	f44f 7380 	movpl.w	r3, #256	; 0x100
    2ff6:	f8c4 3304 	strpl.w	r3, [r4, #772]	; 0x304
	if (cfg->flags & UARTE_CFG_FLAG_LOW_POWER) {
    2ffa:	687b      	ldr	r3, [r7, #4]
    2ffc:	06db      	lsls	r3, r3, #27
    2ffe:	bf44      	itt	mi
    3000:	f44f 0380 	movmi.w	r3, #4194304	; 0x400000
    3004:	f8c4 3304 	strmi.w	r3, [r4, #772]	; 0x304
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    3008:	6933      	ldr	r3, [r6, #16]
    300a:	f8c4 3544 	str.w	r3, [r4, #1348]	; 0x544
    p_reg->TXD.MAXCNT = length;
    300e:	2300      	movs	r3, #0
    3010:	f8c4 3548 	str.w	r3, [r4, #1352]	; 0x548
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    3014:	2301      	movs	r3, #1
    3016:	60a3      	str	r3, [r4, #8]
    3018:	60e3      	str	r3, [r4, #12]
UART_NRF_UARTE_DEVICE(0);
    301a:	4628      	mov	r0, r5
    301c:	b003      	add	sp, #12
    301e:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
		return -EIO;
    3022:	f06f 0504 	mvn.w	r5, #4
UART_NRF_UARTE_DEVICE(0);
    3026:	e7f8      	b.n	301a <uarte_0_init+0xd6>
    3028:	0bad0000 	.word	0x0bad0000
    302c:	50017000 	.word	0x50017000

00003030 <uarte_nrfx_poll_out>:
{
    3030:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    3032:	4604      	mov	r4, r0
    3034:	460d      	mov	r5, r1
	struct uarte_nrfx_data *data = dev->data;
    3036:	6907      	ldr	r7, [r0, #16]
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    3038:	f003 fe22 	bl	6c80 <k_is_in_isr>
    303c:	b9b0      	cbnz	r0, 306c <uarte_nrfx_poll_out+0x3c>
	return !z_sys_post_kernel;
    303e:	4b2e      	ldr	r3, [pc, #184]	; (30f8 <uarte_nrfx_poll_out+0xc8>)
    3040:	781b      	ldrb	r3, [r3, #0]
    3042:	b19b      	cbz	r3, 306c <uarte_nrfx_poll_out+0x3c>
{
    3044:	2664      	movs	r6, #100	; 0x64
		NRFX_WAIT_FOR(is_tx_ready(dev), 100, 1, res);
    3046:	6860      	ldr	r0, [r4, #4]
    3048:	f003 fb6e 	bl	6728 <is_tx_ready.isra.0>
    304c:	bb00      	cbnz	r0, 3090 <uarte_nrfx_poll_out+0x60>
    304e:	2001      	movs	r0, #1
    3050:	f003 fbe7 	bl	6822 <nrfx_busy_wait>
    3054:	3e01      	subs	r6, #1
    3056:	d1f6      	bne.n	3046 <uarte_nrfx_poll_out+0x16>
	return z_impl_k_sleep(timeout);
    3058:	2100      	movs	r1, #0
    305a:	2021      	movs	r0, #33	; 0x21
    305c:	f002 fb4e 	bl	56fc <z_impl_k_sleep>
	return k_sleep(Z_TIMEOUT_MS(ms));
    3060:	e7f0      	b.n	3044 <uarte_nrfx_poll_out+0x14>
	__asm__ volatile(
    3062:	f386 8811 	msr	BASEPRI, r6
    3066:	f3bf 8f6f 	isb	sy
}
    306a:	e7f5      	b.n	3058 <uarte_nrfx_poll_out+0x28>
	__asm__ volatile(
    306c:	f04f 0320 	mov.w	r3, #32
    3070:	f3ef 8611 	mrs	r6, BASEPRI
    3074:	f383 8812 	msr	BASEPRI_MAX, r3
    3078:	f3bf 8f6f 	isb	sy
			if (is_tx_ready(dev)) {
    307c:	6860      	ldr	r0, [r4, #4]
    307e:	4631      	mov	r1, r6
    3080:	f003 fb52 	bl	6728 <is_tx_ready.isra.0>
    3084:	b990      	cbnz	r0, 30ac <uarte_nrfx_poll_out+0x7c>
	__asm__ volatile(
    3086:	f386 8811 	msr	BASEPRI, r6
    308a:	f3bf 8f6f 	isb	sy
}
    308e:	e7ed      	b.n	306c <uarte_nrfx_poll_out+0x3c>
	__asm__ volatile(
    3090:	f04f 0320 	mov.w	r3, #32
    3094:	f3ef 8611 	mrs	r6, BASEPRI
    3098:	f383 8812 	msr	BASEPRI_MAX, r3
    309c:	f3bf 8f6f 	isb	sy
			if (is_tx_ready(dev)) {
    30a0:	6860      	ldr	r0, [r4, #4]
    30a2:	4631      	mov	r1, r6
    30a4:	f003 fb40 	bl	6728 <is_tx_ready.isra.0>
    30a8:	2800      	cmp	r0, #0
    30aa:	d0da      	beq.n	3062 <uarte_nrfx_poll_out+0x32>
	*data->char_out = c;
    30ac:	693b      	ldr	r3, [r7, #16]
    30ae:	701d      	strb	r5, [r3, #0]
	const struct uarte_nrfx_config *config = dev->config;
    30b0:	6862      	ldr	r2, [r4, #4]
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    30b2:	6938      	ldr	r0, [r7, #16]
	return config->uarte_regs;
    30b4:	6813      	ldr	r3, [r2, #0]
    30b6:	f8c3 0544 	str.w	r0, [r3, #1348]	; 0x544
    p_reg->TXD.MAXCNT = length;
    30ba:	2001      	movs	r0, #1
    30bc:	f8c3 0548 	str.w	r0, [r3, #1352]	; 0x548
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    30c0:	2000      	movs	r0, #0
    30c2:	f8c3 0120 	str.w	r0, [r3, #288]	; 0x120
    30c6:	f8d3 5120 	ldr.w	r5, [r3, #288]	; 0x120
    30ca:	f8c3 0158 	str.w	r0, [r3, #344]	; 0x158
	if (config->flags & UARTE_CFG_FLAG_LOW_POWER) {
    30ce:	6852      	ldr	r2, [r2, #4]
    30d0:	f8d3 0158 	ldr.w	r0, [r3, #344]	; 0x158
    30d4:	06d2      	lsls	r2, r2, #27
    30d6:	d508      	bpl.n	30ea <uarte_nrfx_poll_out+0xba>
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
    30d8:	2008      	movs	r0, #8
	return config->uarte_regs;
    30da:	6862      	ldr	r2, [r4, #4]
    30dc:	6812      	ldr	r2, [r2, #0]
    30de:	f8c2 0500 	str.w	r0, [r2, #1280]	; 0x500
    p_reg->INTENSET = mask;
    30e2:	f44f 0280 	mov.w	r2, #4194304	; 0x400000
    30e6:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    30ea:	2201      	movs	r2, #1
    30ec:	609a      	str	r2, [r3, #8]
	__asm__ volatile(
    30ee:	f381 8811 	msr	BASEPRI, r1
    30f2:	f3bf 8f6f 	isb	sy
}
    30f6:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    30f8:	20000c3f 	.word	0x20000c3f

000030fc <compare_int_lock>:
#endif
}

static bool compare_int_lock(int32_t chan)
{
	atomic_val_t prev = atomic_and(&int_mask, ~BIT(chan));
    30fc:	2301      	movs	r3, #1
    30fe:	4083      	lsls	r3, r0
{
    3100:	b570      	push	{r4, r5, r6, lr}
	atomic_val_t prev = atomic_and(&int_mask, ~BIT(chan));
    3102:	43dc      	mvns	r4, r3
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    3104:	4a0b      	ldr	r2, [pc, #44]	; (3134 <compare_int_lock+0x38>)
    3106:	e8d2 1fef 	ldaex	r1, [r2]
    310a:	ea01 0504 	and.w	r5, r1, r4
    310e:	e8c2 5fe6 	stlex	r6, r5, [r2]
    3112:	2e00      	cmp	r6, #0
    3114:	d1f7      	bne.n	3106 <compare_int_lock+0xa>

	nrf_rtc_int_disable(RTC, RTC_CHANNEL_INT_MASK(chan));
    3116:	f44f 3280 	mov.w	r2, #65536	; 0x10000
    311a:	4082      	lsls	r2, r0
    p_reg->INTENSET = mask;
}

NRF_STATIC_INLINE void nrf_rtc_int_disable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->INTENCLR = mask;
    311c:	4806      	ldr	r0, [pc, #24]	; (3138 <compare_int_lock+0x3c>)
    311e:	f8c0 2308 	str.w	r2, [r0, #776]	; 0x308
    3122:	f3bf 8f5f 	dmb	sy
  __ASM volatile ("isb 0xF":::"memory");
    3126:	f3bf 8f6f 	isb	sy

	__DMB();
	__ISB();

	return prev & BIT(chan);
    312a:	420b      	tst	r3, r1
}
    312c:	bf14      	ite	ne
    312e:	2001      	movne	r0, #1
    3130:	2000      	moveq	r0, #0
    3132:	bd70      	pop	{r4, r5, r6, pc}
    3134:	200009bc 	.word	0x200009bc
    3138:	50015000 	.word	0x50015000

0000313c <sys_clock_timeout_handler>:
}

static void sys_clock_timeout_handler(int32_t chan,
				      uint64_t expire_time,
				      void *user_data)
{
    313c:	b470      	push	{r4, r5, r6}
	uint32_t cc_value = absolute_time_to_cc(expire_time);
	uint32_t dticks = (uint32_t)(expire_time - last_count) / CYC_PER_TICK;
    313e:	490e      	ldr	r1, [pc, #56]	; (3178 <sys_clock_timeout_handler+0x3c>)
	return absolute_time & COUNTER_MAX;
    3140:	f022 467f 	bic.w	r6, r2, #4278190080	; 0xff000000
	uint32_t dticks = (uint32_t)(expire_time - last_count) / CYC_PER_TICK;
    3144:	e9d1 3400 	ldrd	r3, r4, [r1]
    3148:	1ad0      	subs	r0, r2, r3

	last_count += dticks * CYC_PER_TICK;
    314a:	18c3      	adds	r3, r0, r3
    314c:	f144 0400 	adc.w	r4, r4, #0
    3150:	e9c1 3400 	strd	r3, r4, [r1]
	return (cc_value >= ANCHOR_RANGE_START) && (cc_value < ANCHOR_RANGE_END);
    3154:	f5a6 1300 	sub.w	r3, r6, #2097152	; 0x200000
	if (in_anchor_range(cc_value)) {
    3158:	f5b3 0f40 	cmp.w	r3, #12582912	; 0xc00000
    315c:	d209      	bcs.n	3172 <sys_clock_timeout_handler+0x36>
		anchor = (((uint64_t)overflow_cnt) << COUNTER_BIT_WIDTH) + cc_value;
    315e:	4b07      	ldr	r3, [pc, #28]	; (317c <sys_clock_timeout_handler+0x40>)
    3160:	681b      	ldr	r3, [r3, #0]
    3162:	0a1a      	lsrs	r2, r3, #8
    3164:	061b      	lsls	r3, r3, #24
    3166:	199c      	adds	r4, r3, r6
    3168:	4b05      	ldr	r3, [pc, #20]	; (3180 <sys_clock_timeout_handler+0x44>)
    316a:	f142 0500 	adc.w	r5, r2, #0
    316e:	e9c3 4500 	strd	r4, r5, [r3]
		compare_set(chan, last_count + CYC_PER_TICK,
					  sys_clock_timeout_handler, NULL);
	}

	sys_clock_announce(dticks);
}
    3172:	bc70      	pop	{r4, r5, r6}
	sys_clock_announce(dticks);
    3174:	f002 bc28 	b.w	59c8 <sys_clock_announce>
    3178:	20000250 	.word	0x20000250
    317c:	200009c0 	.word	0x200009c0
    3180:	20000258 	.word	0x20000258

00003184 <compare_int_unlock>:
	if (key) {
    3184:	b1d9      	cbz	r1, 31be <compare_int_unlock+0x3a>
		atomic_or(&int_mask, BIT(chan));
    3186:	2301      	movs	r3, #1
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    3188:	4a0d      	ldr	r2, [pc, #52]	; (31c0 <compare_int_unlock+0x3c>)
    318a:	4083      	lsls	r3, r0
    318c:	e8d2 cfef 	ldaex	ip, [r2]
    3190:	ea4c 0c03 	orr.w	ip, ip, r3
    3194:	e8c2 cfe1 	stlex	r1, ip, [r2]
    3198:	2900      	cmp	r1, #0
    319a:	d1f7      	bne.n	318c <compare_int_unlock+0x8>
		nrf_rtc_int_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    319c:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    p_reg->INTENSET = mask;
    31a0:	4a08      	ldr	r2, [pc, #32]	; (31c4 <compare_int_unlock+0x40>)
    31a2:	4083      	lsls	r3, r0
    31a4:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
	return __atomic_load_n(target, __ATOMIC_SEQ_CST);
    31a8:	4b07      	ldr	r3, [pc, #28]	; (31c8 <compare_int_unlock+0x44>)
    31aa:	e8d3 3faf 	lda	r3, [r3]
		if (atomic_get(&force_isr_mask) & BIT(chan)) {
    31ae:	40c3      	lsrs	r3, r0
    31b0:	07db      	lsls	r3, r3, #31
    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    31b2:	bf42      	ittt	mi
    31b4:	f44f 1200 	movmi.w	r2, #2097152	; 0x200000
    31b8:	4b04      	ldrmi	r3, [pc, #16]	; (31cc <compare_int_unlock+0x48>)
    31ba:	f8c3 2100 	strmi.w	r2, [r3, #256]	; 0x100
}
    31be:	4770      	bx	lr
    31c0:	200009bc 	.word	0x200009bc
    31c4:	50015000 	.word	0x50015000
    31c8:	200009b8 	.word	0x200009b8
    31cc:	e000e100 	.word	0xe000e100

000031d0 <z_nrf_rtc_timer_read>:
	uint64_t val = ((uint64_t)overflow_cnt) << COUNTER_BIT_WIDTH;
    31d0:	4b0d      	ldr	r3, [pc, #52]	; (3208 <z_nrf_rtc_timer_read+0x38>)
    31d2:	6818      	ldr	r0, [r3, #0]
    31d4:	0a01      	lsrs	r1, r0, #8
    31d6:	0600      	lsls	r0, r0, #24
  __ASM volatile ("dmb 0xF":::"memory");
    31d8:	f3bf 8f5f 	dmb	sy
    nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}

NRF_STATIC_INLINE uint32_t nrf_rtc_counter_get(NRF_RTC_Type const * p_reg)
{
     return p_reg->COUNTER;
    31dc:	4b0b      	ldr	r3, [pc, #44]	; (320c <z_nrf_rtc_timer_read+0x3c>)
    31de:	f8d3 3504 	ldr.w	r3, [r3, #1284]	; 0x504
	val += cntr;
    31e2:	1818      	adds	r0, r3, r0
    31e4:	f141 0100 	adc.w	r1, r1, #0
	if (cntr < OVERFLOW_RISK_RANGE_END) {
    31e8:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
    31ec:	d20a      	bcs.n	3204 <z_nrf_rtc_timer_read+0x34>
		if (val < anchor) {
    31ee:	4b08      	ldr	r3, [pc, #32]	; (3210 <z_nrf_rtc_timer_read+0x40>)
    31f0:	e9d3 2300 	ldrd	r2, r3, [r3]
    31f4:	4290      	cmp	r0, r2
    31f6:	eb71 0303 	sbcs.w	r3, r1, r3
    31fa:	d203      	bcs.n	3204 <z_nrf_rtc_timer_read+0x34>
			val += COUNTER_SPAN;
    31fc:	f110 7080 	adds.w	r0, r0, #16777216	; 0x1000000
    3200:	f141 0100 	adc.w	r1, r1, #0
}
    3204:	4770      	bx	lr
    3206:	bf00      	nop
    3208:	200009c0 	.word	0x200009c0
    320c:	50015000 	.word	0x50015000
    3210:	20000258 	.word	0x20000258

00003214 <compare_set>:
{
    3214:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    3218:	4616      	mov	r6, r2
    321a:	461f      	mov	r7, r3
    321c:	4604      	mov	r4, r0
	key = compare_int_lock(chan);
    321e:	f7ff ff6d 	bl	30fc <compare_int_lock>
    3222:	9000      	str	r0, [sp, #0]
	uint64_t curr_time = z_nrf_rtc_timer_read();
    3224:	f7ff ffd4 	bl	31d0 <z_nrf_rtc_timer_read>
	if (curr_time < target_time) {
    3228:	42b0      	cmp	r0, r6
    322a:	eb71 0307 	sbcs.w	r3, r1, r7
    322e:	d250      	bcs.n	32d2 <compare_set+0xbe>
		if (target_time - curr_time > COUNTER_HALF_SPAN) {
    3230:	4b38      	ldr	r3, [pc, #224]	; (3314 <compare_set+0x100>)
    3232:	1a30      	subs	r0, r6, r0
    3234:	eb67 0101 	sbc.w	r1, r7, r1
    3238:	4298      	cmp	r0, r3
    323a:	f171 0100 	sbcs.w	r1, r1, #0
    323e:	d265      	bcs.n	330c <compare_set+0xf8>
		if (target_time != cc_data[chan].target_time) {
    3240:	4b35      	ldr	r3, [pc, #212]	; (3318 <compare_set+0x104>)
    3242:	eb03 1304 	add.w	r3, r3, r4, lsl #4
    3246:	e9d3 2302 	ldrd	r2, r3, [r3, #8]
    324a:	429f      	cmp	r7, r3
    324c:	bf08      	it	eq
    324e:	4296      	cmpeq	r6, r2
    3250:	d049      	beq.n	32e6 <compare_set+0xd2>
	nrf_rtc_event_disable(RTC, RTC_CHANNEL_INT_MASK(chan));
    3252:	f44f 3980 	mov.w	r9, #65536	; 0x10000
    p_reg->EVTENSET = mask;
}

NRF_STATIC_INLINE void nrf_rtc_event_disable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->EVTENCLR = mask;
    3256:	4931      	ldr	r1, [pc, #196]	; (331c <compare_set+0x108>)
    3258:	fa09 f904 	lsl.w	r9, r9, r4
	event_clear(chan);
    325c:	4620      	mov	r0, r4
	return absolute_time & COUNTER_MAX;
    325e:	f026 4b7f 	bic.w	fp, r6, #4278190080	; 0xff000000
    3262:	f8c1 9348 	str.w	r9, [r1, #840]	; 0x348
	event_clear(chan);
    3266:	f003 faa9 	bl	67bc <event_clear>
	uint32_t cc_inc = MIN_CYCLES_FROM_NOW;
    326a:	f04f 0a03 	mov.w	sl, #3
	uint32_t cc_val = req_cc;
    326e:	4658      	mov	r0, fp
	return nrf_rtc_event_check(RTC, RTC_CHANNEL_EVENT_ADDR(chan));
    3270:	f104 0550 	add.w	r5, r4, #80	; 0x50
    3274:	00ad      	lsls	r5, r5, #2
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    3276:	b2ad      	uxth	r5, r5
    3278:	f105 2550 	add.w	r5, r5, #1342197760	; 0x50005000
    p_reg->CC[ch] = cc_val;
    327c:	f504 73a8 	add.w	r3, r4, #336	; 0x150
		if (counter_sub(cc_val, now + MIN_CYCLES_FROM_NOW) >
    3280:	4a27      	ldr	r2, [pc, #156]	; (3320 <compare_set+0x10c>)
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    3282:	f505 3580 	add.w	r5, r5, #65536	; 0x10000
    p_reg->CC[ch] = cc_val;
    3286:	9301      	str	r3, [sp, #4]
    3288:	f8dd c004 	ldr.w	ip, [sp, #4]
	nrf_rtc_cc_set(RTC, chan, cyc & COUNTER_MAX);
    328c:	f020 437f 	bic.w	r3, r0, #4278190080	; 0xff000000
    3290:	f841 302c 	str.w	r3, [r1, ip, lsl #2]
    p_reg->EVTENSET = mask;
    3294:	f8c1 9344 	str.w	r9, [r1, #836]	; 0x344
     return p_reg->COUNTER;
    3298:	f8d1 8504 	ldr.w	r8, [r1, #1284]	; 0x504
	return (a - b) & COUNTER_MAX;
    329c:	eba0 0008 	sub.w	r0, r0, r8
    32a0:	3803      	subs	r0, #3
    32a2:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
		if (counter_sub(cc_val, now + MIN_CYCLES_FROM_NOW) >
    32a6:	4290      	cmp	r0, r2
    32a8:	d91d      	bls.n	32e6 <compare_set+0xd2>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    32aa:	6828      	ldr	r0, [r5, #0]
			if (event_check(chan)) {
    32ac:	b160      	cbz	r0, 32c8 <compare_set+0xb4>
     return p_reg->COUNTER;
    32ae:	f8d1 8504 	ldr.w	r8, [r1, #1284]	; 0x504
	return (a - b) & COUNTER_MAX;
    32b2:	eba8 000b 	sub.w	r0, r8, fp
    32b6:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
				if (counter_sub(now, req_cc) > COUNTER_HALF_SPAN) {
    32ba:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    32be:	d912      	bls.n	32e6 <compare_set+0xd2>
					event_clear(chan);
    32c0:	4620      	mov	r0, r4
    32c2:	f003 fa7b 	bl	67bc <event_clear>
    32c6:	4a16      	ldr	r2, [pc, #88]	; (3320 <compare_set+0x10c>)
			cc_val = now + cc_inc;
    32c8:	eb0a 0008 	add.w	r0, sl, r8
			cc_inc++;
    32cc:	f10a 0a01 	add.w	sl, sl, #1
	for (;;) {
    32d0:	e7da      	b.n	3288 <compare_set+0x74>
		atomic_or(&force_isr_mask, BIT(chan));
    32d2:	2301      	movs	r3, #1
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    32d4:	4a13      	ldr	r2, [pc, #76]	; (3324 <compare_set+0x110>)
    32d6:	40a3      	lsls	r3, r4
    32d8:	e8d2 0fef 	ldaex	r0, [r2]
    32dc:	4318      	orrs	r0, r3
    32de:	e8c2 0fe1 	stlex	r1, r0, [r2]
    32e2:	2900      	cmp	r1, #0
    32e4:	d1f8      	bne.n	32d8 <compare_set+0xc4>
	return ret;
    32e6:	2500      	movs	r5, #0
	cc_data[chan].target_time = target_time;
    32e8:	490b      	ldr	r1, [pc, #44]	; (3318 <compare_set+0x104>)
	cc_data[chan].callback = handler;
    32ea:	980c      	ldr	r0, [sp, #48]	; 0x30
	cc_data[chan].target_time = target_time;
    32ec:	0123      	lsls	r3, r4, #4
    32ee:	eb01 1204 	add.w	r2, r1, r4, lsl #4
	cc_data[chan].callback = handler;
    32f2:	50c8      	str	r0, [r1, r3]
	cc_data[chan].target_time = target_time;
    32f4:	e9c2 6702 	strd	r6, r7, [r2, #8]
	cc_data[chan].user_context = user_data;
    32f8:	9b0d      	ldr	r3, [sp, #52]	; 0x34
    32fa:	6053      	str	r3, [r2, #4]
	compare_int_unlock(chan, key);
    32fc:	4620      	mov	r0, r4
    32fe:	9900      	ldr	r1, [sp, #0]
    3300:	f7ff ff40 	bl	3184 <compare_int_unlock>
}
    3304:	4628      	mov	r0, r5
    3306:	b003      	add	sp, #12
    3308:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
			return -EINVAL;
    330c:	f06f 0515 	mvn.w	r5, #21
    3310:	e7f4      	b.n	32fc <compare_set+0xe8>
    3312:	bf00      	nop
    3314:	00800001 	.word	0x00800001
    3318:	20000240 	.word	0x20000240
    331c:	50015000 	.word	0x50015000
    3320:	007ffffd 	.word	0x007ffffd
    3324:	200009b8 	.word	0x200009b8

00003328 <sys_clock_driver_init>:
{
	return (uint32_t)z_nrf_rtc_timer_read();
}

static int sys_clock_driver_init(const struct device *dev)
{
    3328:	b573      	push	{r0, r1, r4, r5, r6, lr}
    p_reg->PRESCALER = val;
    332a:	2400      	movs	r4, #0
			CLOCK_CONTROL_NRF_LF_START_STABLE);

	/* TODO: replace with counter driver to access RTC */
	nrf_rtc_prescaler_set(RTC, 0);
	for (int32_t chan = 0; chan < CHAN_COUNT; chan++) {
		cc_data[chan].target_time = TARGET_TIME_INVALID;
    332c:	f04f 30ff 	mov.w	r0, #4294967295
    3330:	f04f 31ff 	mov.w	r1, #4294967295
    3334:	4d16      	ldr	r5, [pc, #88]	; (3390 <sys_clock_driver_init+0x68>)
    3336:	4b17      	ldr	r3, [pc, #92]	; (3394 <sys_clock_driver_init+0x6c>)
    3338:	f8c5 4508 	str.w	r4, [r5, #1288]	; 0x508
    333c:	e9c3 0102 	strd	r0, r1, [r3, #8]
    p_reg->INTENSET = mask;
    3340:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    3344:	2602      	movs	r6, #2
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    3346:	f44f 1200 	mov.w	r2, #2097152	; 0x200000
    334a:	f8c5 3304 	str.w	r3, [r5, #772]	; 0x304
    334e:	4b12      	ldr	r3, [pc, #72]	; (3398 <sys_clock_driver_init+0x70>)

	nrf_rtc_int_enable(RTC, NRF_RTC_INT_OVERFLOW_MASK);

	NVIC_ClearPendingIRQ(RTC_IRQn);

	IRQ_CONNECT(RTC_IRQn, DT_IRQ(DT_NODELABEL(RTC_LABEL), priority),
    3350:	2101      	movs	r1, #1
    3352:	f8c5 6304 	str.w	r6, [r5, #772]	; 0x304
    3356:	2015      	movs	r0, #21
    3358:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
    335c:	4622      	mov	r2, r4
    335e:	f7fe f941 	bl	15e4 <z_arm_irq_priority_set>
		    rtc_nrf_isr, 0, 0);
	irq_enable(RTC_IRQn);
    3362:	2015      	movs	r0, #21
    3364:	f7fe f90e 	bl	1584 <arch_irq_enable>
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    3368:	2301      	movs	r3, #1

	nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_CLEAR);
	nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_START);

	int_mask = BIT_MASK(CHAN_COUNT);
    336a:	4a0c      	ldr	r2, [pc, #48]	; (339c <sys_clock_driver_init+0x74>)
    336c:	60ab      	str	r3, [r5, #8]
    336e:	602b      	str	r3, [r5, #0]
    3370:	6013      	str	r3, [r2, #0]
	}

	uint32_t initial_timeout = IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
		MAX_CYCLES : CYC_PER_TICK;

	compare_set(0, initial_timeout, sys_clock_timeout_handler, NULL);
    3372:	4b0b      	ldr	r3, [pc, #44]	; (33a0 <sys_clock_driver_init+0x78>)
    3374:	4a0b      	ldr	r2, [pc, #44]	; (33a4 <sys_clock_driver_init+0x7c>)
    3376:	9300      	str	r3, [sp, #0]
    3378:	4620      	mov	r0, r4
    337a:	2300      	movs	r3, #0
    337c:	9401      	str	r4, [sp, #4]
    337e:	f7ff ff49 	bl	3214 <compare_set>

	z_nrf_clock_control_lf_on(mode);
    3382:	4630      	mov	r0, r6
    3384:	f7fe fe58 	bl	2038 <z_nrf_clock_control_lf_on>

	return 0;
}
    3388:	4620      	mov	r0, r4
    338a:	b002      	add	sp, #8
    338c:	bd70      	pop	{r4, r5, r6, pc}
    338e:	bf00      	nop
    3390:	50015000 	.word	0x50015000
    3394:	20000240 	.word	0x20000240
    3398:	e000e100 	.word	0xe000e100
    339c:	200009bc 	.word	0x200009bc
    33a0:	0000313d 	.word	0x0000313d
    33a4:	007fffff 	.word	0x007fffff

000033a8 <rtc_nrf_isr>:
{
    33a8:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    return p_reg->INTENSET & mask;
    33ac:	4b2e      	ldr	r3, [pc, #184]	; (3468 <rtc_nrf_isr+0xc0>)
    33ae:	f8d3 2304 	ldr.w	r2, [r3, #772]	; 0x304
	if (nrf_rtc_int_enable_check(RTC, NRF_RTC_INT_OVERFLOW_MASK) &&
    33b2:	0790      	lsls	r0, r2, #30
    33b4:	d50b      	bpl.n	33ce <rtc_nrf_isr+0x26>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    33b6:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
    33ba:	b142      	cbz	r2, 33ce <rtc_nrf_isr+0x26>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    33bc:	2200      	movs	r2, #0
    33be:	f8c3 2104 	str.w	r2, [r3, #260]	; 0x104
		overflow_cnt++;
    33c2:	4a2a      	ldr	r2, [pc, #168]	; (346c <rtc_nrf_isr+0xc4>)
    33c4:	f8d3 3104 	ldr.w	r3, [r3, #260]	; 0x104
    33c8:	6813      	ldr	r3, [r2, #0]
    33ca:	3301      	adds	r3, #1
    33cc:	6013      	str	r3, [r2, #0]
    return p_reg->INTENSET & mask;
    33ce:	4a26      	ldr	r2, [pc, #152]	; (3468 <rtc_nrf_isr+0xc0>)
    33d0:	f8d2 3304 	ldr.w	r3, [r2, #772]	; 0x304
	if (nrf_rtc_int_enable_check(RTC, RTC_CHANNEL_INT_MASK(chan))) {
    33d4:	03d9      	lsls	r1, r3, #15
    33d6:	d527      	bpl.n	3428 <rtc_nrf_isr+0x80>
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    33d8:	4b25      	ldr	r3, [pc, #148]	; (3470 <rtc_nrf_isr+0xc8>)
    33da:	e8d3 1fef 	ldaex	r1, [r3]
    33de:	f021 0001 	bic.w	r0, r1, #1
    33e2:	e8c3 0fe4 	stlex	r4, r0, [r3]
    33e6:	2c00      	cmp	r4, #0
    33e8:	d1f7      	bne.n	33da <rtc_nrf_isr+0x32>
		if ((atomic_and(&force_isr_mask, ~BIT(chan)) & BIT(chan)) ||
    33ea:	07cb      	lsls	r3, r1, #31
    33ec:	d402      	bmi.n	33f4 <rtc_nrf_isr+0x4c>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    33ee:	f8d2 3140 	ldr.w	r3, [r2, #320]	; 0x140
    33f2:	b1cb      	cbz	r3, 3428 <rtc_nrf_isr+0x80>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    33f4:	2500      	movs	r5, #0
    33f6:	4c1c      	ldr	r4, [pc, #112]	; (3468 <rtc_nrf_isr+0xc0>)
    33f8:	f8c4 5140 	str.w	r5, [r4, #320]	; 0x140
    33fc:	f8d4 3140 	ldr.w	r3, [r4, #320]	; 0x140
		curr_time = z_nrf_rtc_timer_read();
    3400:	f7ff fee6 	bl	31d0 <z_nrf_rtc_timer_read>
	__asm__ volatile(
    3404:	f04f 0320 	mov.w	r3, #32
    3408:	f3ef 8211 	mrs	r2, BASEPRI
    340c:	f383 8812 	msr	BASEPRI_MAX, r3
    3410:	f3bf 8f6f 	isb	sy
		expire_time = cc_data[chan].target_time;
    3414:	4b17      	ldr	r3, [pc, #92]	; (3474 <rtc_nrf_isr+0xcc>)
    3416:	e9d3 6702 	ldrd	r6, r7, [r3, #8]
		if (curr_time >= expire_time) {
    341a:	42b0      	cmp	r0, r6
    341c:	41b9      	sbcs	r1, r7
    341e:	d206      	bcs.n	342e <rtc_nrf_isr+0x86>
	__asm__ volatile(
    3420:	f382 8811 	msr	BASEPRI, r2
    3424:	f3bf 8f6f 	isb	sy
}
    3428:	b003      	add	sp, #12
    342a:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
			cc_data[chan].target_time = TARGET_TIME_INVALID;
    342e:	f04f 38ff 	mov.w	r8, #4294967295
			user_context = cc_data[chan].user_context;
    3432:	e9d3 1000 	ldrd	r1, r0, [r3]
			cc_data[chan].target_time = TARGET_TIME_INVALID;
    3436:	f04f 39ff 	mov.w	r9, #4294967295
			cc_data[chan].callback = NULL;
    343a:	601d      	str	r5, [r3, #0]
			cc_data[chan].target_time = TARGET_TIME_INVALID;
    343c:	e9c3 8902 	strd	r8, r9, [r3, #8]
    p_reg->EVTENCLR = mask;
    3440:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    3444:	f8c4 3348 	str.w	r3, [r4, #840]	; 0x348
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    3448:	f8c4 5140 	str.w	r5, [r4, #320]	; 0x140
    344c:	f8d4 3140 	ldr.w	r3, [r4, #320]	; 0x140
    3450:	f382 8811 	msr	BASEPRI, r2
    3454:	f3bf 8f6f 	isb	sy
		if (handler) {
    3458:	2900      	cmp	r1, #0
    345a:	d0e5      	beq.n	3428 <rtc_nrf_isr+0x80>
			handler(chan, expire_time, user_context);
    345c:	9000      	str	r0, [sp, #0]
    345e:	4632      	mov	r2, r6
    3460:	463b      	mov	r3, r7
    3462:	4628      	mov	r0, r5
    3464:	4788      	blx	r1
    3466:	e7df      	b.n	3428 <rtc_nrf_isr+0x80>
    3468:	50015000 	.word	0x50015000
    346c:	200009c0 	.word	0x200009c0
    3470:	200009b8 	.word	0x200009b8
    3474:	20000240 	.word	0x20000240

00003478 <sys_clock_set_timeout>:
	if (ticks == K_TICKS_FOREVER) {
    3478:	1c43      	adds	r3, r0, #1
{
    347a:	b513      	push	{r0, r1, r4, lr}
	if (ticks == K_TICKS_FOREVER) {
    347c:	d021      	beq.n	34c2 <sys_clock_set_timeout+0x4a>
		cyc = CLAMP(ticks, 1, (int32_t)MAX_TICKS);
    347e:	2801      	cmp	r0, #1
    3480:	dd21      	ble.n	34c6 <sys_clock_set_timeout+0x4e>
    3482:	4a12      	ldr	r2, [pc, #72]	; (34cc <sys_clock_set_timeout+0x54>)
    3484:	4b12      	ldr	r3, [pc, #72]	; (34d0 <sys_clock_set_timeout+0x58>)
    3486:	4290      	cmp	r0, r2
    3488:	bfd4      	ite	le
    348a:	4604      	movle	r4, r0
    348c:	461c      	movgt	r4, r3
	uint32_t unannounced = z_nrf_rtc_timer_read() - last_count;
    348e:	f7ff fe9f 	bl	31d0 <z_nrf_rtc_timer_read>
    3492:	4b10      	ldr	r3, [pc, #64]	; (34d4 <sys_clock_set_timeout+0x5c>)
	if (cyc > MAX_CYCLES) {
    3494:	490e      	ldr	r1, [pc, #56]	; (34d0 <sys_clock_set_timeout+0x58>)
	uint32_t unannounced = z_nrf_rtc_timer_read() - last_count;
    3496:	e9d3 2300 	ldrd	r2, r3, [r3]
    349a:	1a80      	subs	r0, r0, r2
		cyc = 0;
    349c:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    34a0:	bf28      	it	cs
    34a2:	2400      	movcs	r4, #0
	cyc += unannounced;
    34a4:	4404      	add	r4, r0
	if (cyc > MAX_CYCLES) {
    34a6:	428c      	cmp	r4, r1
    34a8:	bf28      	it	cs
    34aa:	460c      	movcs	r4, r1
	uint64_t target_time = cyc + last_count;
    34ac:	2000      	movs	r0, #0
	compare_set(0, target_time, sys_clock_timeout_handler, NULL);
    34ae:	490a      	ldr	r1, [pc, #40]	; (34d8 <sys_clock_set_timeout+0x60>)
	uint64_t target_time = cyc + last_count;
    34b0:	18a2      	adds	r2, r4, r2
	compare_set(0, target_time, sys_clock_timeout_handler, NULL);
    34b2:	9001      	str	r0, [sp, #4]
    34b4:	9100      	str	r1, [sp, #0]
    34b6:	f143 0300 	adc.w	r3, r3, #0
    34ba:	f7ff feab 	bl	3214 <compare_set>
}
    34be:	b002      	add	sp, #8
    34c0:	bd10      	pop	{r4, pc}
		cyc = MAX_TICKS * CYC_PER_TICK;
    34c2:	4c03      	ldr	r4, [pc, #12]	; (34d0 <sys_clock_set_timeout+0x58>)
    34c4:	e7e3      	b.n	348e <sys_clock_set_timeout+0x16>
		cyc = CLAMP(ticks, 1, (int32_t)MAX_TICKS);
    34c6:	2401      	movs	r4, #1
    34c8:	e7e1      	b.n	348e <sys_clock_set_timeout+0x16>
    34ca:	bf00      	nop
    34cc:	007ffffe 	.word	0x007ffffe
    34d0:	007fffff 	.word	0x007fffff
    34d4:	20000250 	.word	0x20000250
    34d8:	0000313d 	.word	0x0000313d

000034dc <sys_clock_elapsed>:
{
    34dc:	b508      	push	{r3, lr}
	return (z_nrf_rtc_timer_read() - last_count) / CYC_PER_TICK;
    34de:	f7ff fe77 	bl	31d0 <z_nrf_rtc_timer_read>
    34e2:	4b02      	ldr	r3, [pc, #8]	; (34ec <sys_clock_elapsed+0x10>)
    34e4:	681b      	ldr	r3, [r3, #0]
}
    34e6:	1ac0      	subs	r0, r0, r3
    34e8:	bd08      	pop	{r3, pc}
    34ea:	bf00      	nop
    34ec:	20000250 	.word	0x20000250

000034f0 <pinctrl_configure_pins>:
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    34f0:	f04f 0c01 	mov.w	ip, #1
#define NRF_PSEL_QSPI(reg, line) ((NRF_QSPI_Type *)reg)->PSEL.line
#endif

int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
			   uintptr_t reg)
{
    34f4:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
        case 1: return NRF_P1;
    34f8:	4e5b      	ldr	r6, [pc, #364]	; (3668 <pinctrl_configure_pins+0x178>)
    34fa:	4f5c      	ldr	r7, [pc, #368]	; (366c <pinctrl_configure_pins+0x17c>)
    34fc:	eb00 0181 	add.w	r1, r0, r1, lsl #2
	for (uint8_t i = 0U; i < pin_cnt; i++) {
    3500:	4281      	cmp	r1, r0
    3502:	d102      	bne.n	350a <pinctrl_configure_pins+0x1a>
			nrf_gpio_cfg(pin, dir, input, NRF_GET_PULL(pins[i]),
				     drive, NRF_GPIO_PIN_NOSENSE);
		}
	}

	return 0;
    3504:	2000      	movs	r0, #0
}
    3506:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
		nrf_gpio_pin_drive_t drive = NRF_GET_DRIVE(pins[i]);
    350a:	6804      	ldr	r4, [r0, #0]
		uint32_t pin = NRF_GET_PIN(pins[i]);
    350c:	f004 037f 	and.w	r3, r4, #127	; 0x7f
		nrf_gpio_pin_drive_t drive = NRF_GET_DRIVE(pins[i]);
    3510:	f3c4 2543 	ubfx	r5, r4, #9, #4
			pin = 0xFFFFFFFFU;
    3514:	2b7f      	cmp	r3, #127	; 0x7f
		switch (NRF_GET_FUN(pins[i])) {
    3516:	ea4f 4414 	mov.w	r4, r4, lsr #16
			pin = 0xFFFFFFFFU;
    351a:	bf08      	it	eq
    351c:	f04f 33ff 	moveq.w	r3, #4294967295
		switch (NRF_GET_FUN(pins[i])) {
    3520:	2c22      	cmp	r4, #34	; 0x22
    3522:	f200 809d 	bhi.w	3660 <pinctrl_configure_pins+0x170>
    3526:	e8df f004 	tbb	[pc, r4]
    352a:	2312      	.short	0x2312
    352c:	3e2b4228 	.word	0x3e2b4228
    3530:	9b9b9b42 	.word	0x9b9b9b42
    3534:	9b72459b 	.word	0x9b72459b
    3538:	9b9b9b9b 	.word	0x9b9b9b9b
    353c:	9b9b9b9b 	.word	0x9b9b9b9b
    3540:	83807d75 	.word	0x83807d75
    3544:	869b9b9b 	.word	0x869b9b9b
    3548:	95928f8c 	.word	0x95928f8c
    354c:	98          	.byte	0x98
    354d:	00          	.byte	0x00
			NRF_PSEL_UART(reg, TXD) = pin;
    354e:	f8c2 350c 	str.w	r3, [r2, #1292]	; 0x50c
    return pin_number >> 5;
    3552:	ea4f 1853 	mov.w	r8, r3, lsr #5
        case 1: return NRF_P1;
    3556:	f1b8 0f01 	cmp.w	r8, #1
    355a:	bf14      	ite	ne
    355c:	46b6      	movne	lr, r6
    355e:	46be      	moveq	lr, r7
    *p_pin = pin_number & 0x1F;
    3560:	f003 041f 	and.w	r4, r3, #31
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    3564:	fa0c f404 	lsl.w	r4, ip, r4
    p_reg->OUTSET = set_mask;
    3568:	f8ce 4008 	str.w	r4, [lr, #8]
    356c:	2401      	movs	r4, #1
    356e:	e002      	b.n	3576 <pinctrl_configure_pins+0x86>
			NRF_PSEL_UART(reg, RXD) = pin;
    3570:	f8c2 3514 	str.w	r3, [r2, #1300]	; 0x514
			input = NRF_GPIO_PIN_INPUT_CONNECT;
    3574:	2400      	movs	r4, #0
    3576:	46a6      	mov	lr, r4
    3578:	e023      	b.n	35c2 <pinctrl_configure_pins+0xd2>
			NRF_PSEL_UART(reg, RTS) = pin;
    357a:	f8c2 3508 	str.w	r3, [r2, #1288]	; 0x508
			if (write != NO_WRITE) {
    357e:	e7e8      	b.n	3552 <pinctrl_configure_pins+0x62>
			input = NRF_GPIO_PIN_INPUT_CONNECT;
    3580:	2400      	movs	r4, #0
			NRF_PSEL_SPIM(reg, SCK) = pin;
    3582:	f8c2 3508 	str.w	r3, [r2, #1288]	; 0x508
    return pin_number >> 5;
    3586:	ea4f 1953 	mov.w	r9, r3, lsr #5
        case 1: return NRF_P1;
    358a:	f1b9 0f01 	cmp.w	r9, #1
    358e:	bf14      	ite	ne
    3590:	46b0      	movne	r8, r6
    3592:	46b8      	moveq	r8, r7
    *p_pin = pin_number & 0x1F;
    3594:	f003 0e1f 	and.w	lr, r3, #31
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    3598:	fa0c fe0e 	lsl.w	lr, ip, lr
    p_reg->OUTCLR = clr_mask;
    359c:	f8c8 e00c 	str.w	lr, [r8, #12]
    35a0:	f04f 0e01 	mov.w	lr, #1
    35a4:	e00d      	b.n	35c2 <pinctrl_configure_pins+0xd2>
			NRF_PSEL_SPIM(reg, MOSI) = pin;
    35a6:	f8c2 350c 	str.w	r3, [r2, #1292]	; 0x50c
			pin = 0xFFFFFFFFU;
    35aa:	2401      	movs	r4, #1
    35ac:	e7eb      	b.n	3586 <pinctrl_configure_pins+0x96>
			NRF_PSEL_SPIM(reg, MISO) = pin;
    35ae:	f8c2 3510 	str.w	r3, [r2, #1296]	; 0x510
			if (write != NO_WRITE) {
    35b2:	e7df      	b.n	3574 <pinctrl_configure_pins+0x84>
			NRF_PSEL_TWIM(reg, SCL) = pin;
    35b4:	f8c2 3508 	str.w	r3, [r2, #1288]	; 0x508
			if (drive == NRF_DRIVE_S0S1) {
    35b8:	2d00      	cmp	r5, #0
    35ba:	d1db      	bne.n	3574 <pinctrl_configure_pins+0x84>
			input = NRF_GPIO_PIN_INPUT_CONNECT;
    35bc:	2400      	movs	r4, #0
				drive = NRF_DRIVE_S0D1;
    35be:	2506      	movs	r5, #6
			dir = NRF_GPIO_PIN_DIR_INPUT;
    35c0:	46a6      	mov	lr, r4
			if (NRF_GET_LP(pins[i]) == NRF_LP_ENABLE) {
    35c2:	f850 ab04 	ldr.w	sl, [r0], #4
    *p_pin = pin_number & 0x1F;
    35c6:	f003 091f 	and.w	r9, r3, #31
    35ca:	f40a 5800 	and.w	r8, sl, #8192	; 0x2000
				input = NRF_GPIO_PIN_INPUT_DISCONNECT;
    35ce:	f1b8 0f00 	cmp.w	r8, #0
    return pin_number >> 5;
    35d2:	ea4f 1353 	mov.w	r3, r3, lsr #5
    35d6:	bf1c      	itt	ne
    35d8:	2401      	movne	r4, #1
    35da:	f04f 0e00 	movne.w	lr, #0
        case 0: return NRF_P0;
    35de:	2b01      	cmp	r3, #1
    35e0:	bf0c      	ite	eq
    35e2:	46b8      	moveq	r8, r7
    35e4:	46b0      	movne	r8, r6
    35e6:	eb08 0889 	add.w	r8, r8, r9, lsl #2
    uint32_t cnf = reg->PIN_CNF[pin_number] & GPIO_PIN_CNF_MCUSEL_Msk;
    35ea:	f8d8 3200 	ldr.w	r3, [r8, #512]	; 0x200
			nrf_gpio_cfg(pin, dir, input, NRF_GET_PULL(pins[i]),
    35ee:	f3ca 1ac1 	ubfx	sl, sl, #7, #2
    35f2:	f003 49e0 	and.w	r9, r3, #1879048192	; 0x70000000
           ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) |
    35f6:	022b      	lsls	r3, r5, #8
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    35f8:	ea43 038a 	orr.w	r3, r3, sl, lsl #2
    35fc:	ea43 030e 	orr.w	r3, r3, lr
    3600:	ea43 0344 	orr.w	r3, r3, r4, lsl #1
    cnf |= ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)     |
    3604:	ea43 0309 	orr.w	r3, r3, r9
    reg->PIN_CNF[pin_number] = cnf;
    3608:	f8c8 3200 	str.w	r3, [r8, #512]	; 0x200
	for (uint8_t i = 0U; i < pin_cnt; i++) {
    360c:	e778      	b.n	3500 <pinctrl_configure_pins+0x10>
			NRF_PSEL_TWIM(reg, SDA) = pin;
    360e:	f8c2 350c 	str.w	r3, [r2, #1292]	; 0x50c
			if (drive == NRF_DRIVE_S0S1) {
    3612:	e7d1      	b.n	35b8 <pinctrl_configure_pins+0xc8>
			NRF_PSEL_PWM(reg, OUT[0]) = pin;
    3614:	f8c2 3560 	str.w	r3, [r2, #1376]	; 0x560
			write = NRF_GET_INVERT(pins[i]);
    3618:	6804      	ldr	r4, [r0, #0]
    361a:	f3c4 3480 	ubfx	r4, r4, #14, #1
    if (value == 0)
    361e:	2c00      	cmp	r4, #0
    3620:	d0c3      	beq.n	35aa <pinctrl_configure_pins+0xba>
    3622:	e796      	b.n	3552 <pinctrl_configure_pins+0x62>
			NRF_PSEL_PWM(reg, OUT[1]) = pin;
    3624:	f8c2 3564 	str.w	r3, [r2, #1380]	; 0x564
			write = NRF_GET_INVERT(pins[i]);
    3628:	e7f6      	b.n	3618 <pinctrl_configure_pins+0x128>
			NRF_PSEL_PWM(reg, OUT[2]) = pin;
    362a:	f8c2 3568 	str.w	r3, [r2, #1384]	; 0x568
			write = NRF_GET_INVERT(pins[i]);
    362e:	e7f3      	b.n	3618 <pinctrl_configure_pins+0x128>
			NRF_PSEL_PWM(reg, OUT[3]) = pin;
    3630:	f8c2 356c 	str.w	r3, [r2, #1388]	; 0x56c
    3634:	e7f0      	b.n	3618 <pinctrl_configure_pins+0x128>
			NRF_PSEL_QSPI(reg, SCK) = pin;
    3636:	f8c2 3524 	str.w	r3, [r2, #1316]	; 0x524
			input = NRF_GPIO_PIN_INPUT_DISCONNECT;
    363a:	2401      	movs	r4, #1
			dir = NRF_GPIO_PIN_DIR_INPUT;
    363c:	f04f 0e00 	mov.w	lr, #0
    3640:	e7bf      	b.n	35c2 <pinctrl_configure_pins+0xd2>
			NRF_PSEL_QSPI(reg, CSN) = pin;
    3642:	f8c2 3528 	str.w	r3, [r2, #1320]	; 0x528
    3646:	e784      	b.n	3552 <pinctrl_configure_pins+0x62>
			NRF_PSEL_QSPI(reg, IO0) = pin;
    3648:	f8c2 3530 	str.w	r3, [r2, #1328]	; 0x530
			if (write != NO_WRITE) {
    364c:	e7f5      	b.n	363a <pinctrl_configure_pins+0x14a>
			NRF_PSEL_QSPI(reg, IO1) = pin;
    364e:	f8c2 3534 	str.w	r3, [r2, #1332]	; 0x534
    3652:	e7f2      	b.n	363a <pinctrl_configure_pins+0x14a>
			NRF_PSEL_QSPI(reg, IO2) = pin;
    3654:	f8c2 3538 	str.w	r3, [r2, #1336]	; 0x538
			if (write != NO_WRITE) {
    3658:	e7ef      	b.n	363a <pinctrl_configure_pins+0x14a>
			NRF_PSEL_QSPI(reg, IO3) = pin;
    365a:	f8c2 353c 	str.w	r3, [r2, #1340]	; 0x53c
			if (write != NO_WRITE) {
    365e:	e7ec      	b.n	363a <pinctrl_configure_pins+0x14a>
		switch (NRF_GET_FUN(pins[i])) {
    3660:	f06f 0085 	mvn.w	r0, #133	; 0x85
    3664:	e74f      	b.n	3506 <pinctrl_configure_pins+0x16>
    3666:	bf00      	nop
    3668:	50842500 	.word	0x50842500
    366c:	50842800 	.word	0x50842800

00003670 <nrf53_errata_42>:
            #if defined(NRF_APPLICATION)
                #if defined(NRF_TRUSTZONE_NONSECURE)
                    uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul));
                    uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul));
                #else
                    uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul));
    3670:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    3674:	f8d3 2130 	ldr.w	r2, [r3, #304]	; 0x130
                    uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul));
    3678:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
                #endif
            #endif
        #endif
        #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
            #if defined (NRF_APPLICATION)
                if (var1 == 0x07)
    367c:	2a07      	cmp	r2, #7
    367e:	d105      	bne.n	368c <nrf53_errata_42+0x1c>
                {
                    switch(var2)
    3680:	3b02      	subs	r3, #2
    3682:	2b03      	cmp	r3, #3
    3684:	d802      	bhi.n	368c <nrf53_errata_42+0x1c>
    3686:	4a02      	ldr	r2, [pc, #8]	; (3690 <nrf53_errata_42+0x20>)
    3688:	5cd0      	ldrb	r0, [r2, r3]
    368a:	4770      	bx	lr
                    {
                        case 0x02ul:
                            return true;
                        case 0x03ul:
                            return false;
    368c:	2000      	movs	r0, #0
                }
            #endif
        #endif
        return false;
    #endif
}
    368e:	4770      	bx	lr
    3690:	000078ac 	.word	0x000078ac

00003694 <SystemCoreClockUpdate>:
void SystemCoreClockUpdate(void)
{
#if defined(NRF_TRUSTZONE_NONSECURE)
    SystemCoreClock = __SYSTEM_CLOCK_MAX >> (NRF_CLOCK_NS->HFCLKCTRL & (CLOCK_HFCLKCTRL_HCLK_Msk));
#else
    SystemCoreClock = __SYSTEM_CLOCK_MAX >> (NRF_CLOCK_S->HFCLKCTRL & (CLOCK_HFCLKCTRL_HCLK_Msk));
    3694:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    3698:	f8d3 2558 	ldr.w	r2, [r3, #1368]	; 0x558
    369c:	4b03      	ldr	r3, [pc, #12]	; (36ac <SystemCoreClockUpdate+0x18>)
    369e:	f002 0203 	and.w	r2, r2, #3
    36a2:	40d3      	lsrs	r3, r2
    36a4:	4a02      	ldr	r2, [pc, #8]	; (36b0 <SystemCoreClockUpdate+0x1c>)
    36a6:	6013      	str	r3, [r2, #0]
#endif
}
    36a8:	4770      	bx	lr
    36aa:	bf00      	nop
    36ac:	07a12000 	.word	0x07a12000
    36b0:	200000f0 	.word	0x200000f0

000036b4 <SystemInit>:

void SystemInit(void)
{
    36b4:	b508      	push	{r3, lr}
            SAU->CTRL |= (1 << SAU_CTRL_ALLNS_Pos);
        #endif

        /* Workaround for Errata 97 "ERASEPROTECT, APPROTECT, or startup problems" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf53_errata_97())
    36b6:	f7ff ffdb 	bl	3670 <nrf53_errata_42>
    36ba:	b158      	cbz	r0, 36d4 <SystemInit+0x20>
        {
            if (*((volatile uint32_t *)0x50004A20ul) == 0)
    36bc:	4b4f      	ldr	r3, [pc, #316]	; (37fc <SystemInit+0x148>)
    36be:	f8d3 2a20 	ldr.w	r2, [r3, #2592]	; 0xa20
    36c2:	b93a      	cbnz	r2, 36d4 <SystemInit+0x20>
            {
                *((volatile uint32_t *)0x50004A20ul) = 0xDul;
    36c4:	210d      	movs	r1, #13
    36c6:	f8c3 1a20 	str.w	r1, [r3, #2592]	; 0xa20
                *((volatile uint32_t *)0x5000491Cul) = 0x1ul;
    36ca:	2101      	movs	r1, #1
    36cc:	f8c3 191c 	str.w	r1, [r3, #2332]	; 0x91c
                *((volatile uint32_t *)0x5000491Cul) = 0x0ul;
    36d0:	f8c3 291c 	str.w	r2, [r3, #2332]	; 0x91c
{
    36d4:	2200      	movs	r2, #0
    36d6:	00d3      	lsls	r3, r2, #3
    36d8:	f503 037f 	add.w	r3, r3, #16711680	; 0xff0000
        }

        /* Trimming of the device. Copy all the trimming values from FICR into the target addresses. Trim
         until one ADDR is not initialized. */
        uint32_t index = 0;
        for (index = 0; index < 32ul && NRF_FICR_S->TRIMCNF[index].ADDR != (uint32_t *)0xFFFFFFFFul; index++){
    36dc:	f8d3 1300 	ldr.w	r1, [r3, #768]	; 0x300
    36e0:	3101      	adds	r1, #1
    36e2:	d007      	beq.n	36f4 <SystemInit+0x40>
            #if defined ( __ICCARM__ )
                /* IAR will complain about the order of volatile pointer accesses. */
                #pragma diag_suppress=Pa082
            #endif
            *((volatile uint32_t *)NRF_FICR_S->TRIMCNF[index].ADDR) = NRF_FICR_S->TRIMCNF[index].DATA;
    36e4:	f8d3 1300 	ldr.w	r1, [r3, #768]	; 0x300
        for (index = 0; index < 32ul && NRF_FICR_S->TRIMCNF[index].ADDR != (uint32_t *)0xFFFFFFFFul; index++){
    36e8:	3201      	adds	r2, #1
            *((volatile uint32_t *)NRF_FICR_S->TRIMCNF[index].ADDR) = NRF_FICR_S->TRIMCNF[index].DATA;
    36ea:	f8d3 3304 	ldr.w	r3, [r3, #772]	; 0x304
        for (index = 0; index < 32ul && NRF_FICR_S->TRIMCNF[index].ADDR != (uint32_t *)0xFFFFFFFFul; index++){
    36ee:	2a20      	cmp	r2, #32
            *((volatile uint32_t *)NRF_FICR_S->TRIMCNF[index].ADDR) = NRF_FICR_S->TRIMCNF[index].DATA;
    36f0:	600b      	str	r3, [r1, #0]
        for (index = 0; index < 32ul && NRF_FICR_S->TRIMCNF[index].ADDR != (uint32_t *)0xFFFFFFFFul; index++){
    36f2:	d1f0      	bne.n	36d6 <SystemInit+0x22>
        }

        /* errata 64 must be before errata 42, as errata 42 is dependant on the changes in errata 64*/
        /* Workaround for Errata 64 "VREGMAIN has invalid configuration when CPU is running at 128 MHz" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf53_errata_64())
    36f4:	f7ff ffbc 	bl	3670 <nrf53_errata_42>
    36f8:	2800      	cmp	r0, #0
    36fa:	d176      	bne.n	37ea <SystemInit+0x136>
            *((volatile uint32_t *)0x5000473Cul) = 0x3ul;
        }

        /* Workaround for Errata 42 "Reset value of HFCLKCTRL is invalid" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf53_errata_42())
    36fc:	f7ff ffb8 	bl	3670 <nrf53_errata_42>
    3700:	b140      	cbz	r0, 3714 <SystemInit+0x60>
        {
            *((volatile uint32_t *)0x50039530ul) = 0xBEEF0044ul;
    3702:	4b3f      	ldr	r3, [pc, #252]	; (3800 <SystemInit+0x14c>)
    3704:	4a3f      	ldr	r2, [pc, #252]	; (3804 <SystemInit+0x150>)
    3706:	f8c3 2530 	str.w	r2, [r3, #1328]	; 0x530
            NRF_CLOCK_S->HFCLKCTRL = CLOCK_HFCLKCTRL_HCLK_Div2 << CLOCK_HFCLKCTRL_HCLK_Pos;
    370a:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    370e:	2201      	movs	r2, #1
    3710:	f8c3 2558 	str.w	r2, [r3, #1368]	; 0x558
            #if defined(NRF_APPLICATION)
                #if defined(NRF_TRUSTZONE_NONSECURE)
                    uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul));
                    uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul));
                #else
                    uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul));
    3714:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    3718:	f8d3 2130 	ldr.w	r2, [r3, #304]	; 0x130
                    uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul));
    371c:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
                #endif
            #endif
        #endif
        #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
            #if defined (NRF_APPLICATION)
                if (var1 == 0x07)
    3720:	2a07      	cmp	r2, #7
    3722:	d109      	bne.n	3738 <SystemInit+0x84>
                {
                    switch(var2)
    3724:	3b02      	subs	r3, #2
    3726:	2b03      	cmp	r3, #3
    3728:	d806      	bhi.n	3738 <SystemInit+0x84>
        }

        /* Workaround for Errata 46 "Higher power consumption of LFRC" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf53_errata_46())
    372a:	4a37      	ldr	r2, [pc, #220]	; (3808 <SystemInit+0x154>)
    372c:	5cd3      	ldrb	r3, [r2, r3]
    372e:	b11b      	cbz	r3, 3738 <SystemInit+0x84>
        {
            *((volatile uint32_t *)0x5003254Cul) = 0;
    3730:	2200      	movs	r2, #0
    3732:	4b36      	ldr	r3, [pc, #216]	; (380c <SystemInit+0x158>)
    3734:	f8c3 254c 	str.w	r2, [r3, #1356]	; 0x54c
        }

        /* Workaround for Errata 49 "SLEEPENTER and SLEEPEXIT events asserted after pin reset" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf53_errata_49())
    3738:	f7ff ff9a 	bl	3670 <nrf53_errata_42>
    373c:	b150      	cbz	r0, 3754 <SystemInit+0xa0>
        {
            if (NRF_RESET_S->RESETREAS & RESET_RESETREAS_RESETPIN_Msk)
    373e:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    3742:	f8d3 2400 	ldr.w	r2, [r3, #1024]	; 0x400
    3746:	07d1      	lsls	r1, r2, #31
            {
                NRF_POWER_S->EVENTS_SLEEPENTER = 0;
    3748:	bf42      	ittt	mi
    374a:	2200      	movmi	r2, #0
    374c:	f8c3 2114 	strmi.w	r2, [r3, #276]	; 0x114
                NRF_POWER_S->EVENTS_SLEEPEXIT = 0;
    3750:	f8c3 2118 	strmi.w	r2, [r3, #280]	; 0x118
            #if defined(NRF_APPLICATION)
                #if defined(NRF_TRUSTZONE_NONSECURE)
                    uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul));
                    uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul));
                #else
                    uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul));
    3754:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    3758:	f8d3 2130 	ldr.w	r2, [r3, #304]	; 0x130
                    uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul));
    375c:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
            #endif
        #endif
        #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340)
            #if defined (NRF_APPLICATION)\
             || defined (NRF_NETWORK)
                if (var1 == 0x07)
    3760:	2a07      	cmp	r2, #7
    3762:	d109      	bne.n	3778 <SystemInit+0xc4>

        /* Workaround for Errata 55 "Bits in RESETREAS are set when they should not be" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf53_errata_55())
        {
            if (NRF_RESET_S->RESETREAS & RESET_RESETREAS_RESETPIN_Msk){
    3764:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    3768:	f8d3 2400 	ldr.w	r2, [r3, #1024]	; 0x400
    376c:	07d2      	lsls	r2, r2, #31
                NRF_RESET_S->RESETREAS = ~RESET_RESETREAS_RESETPIN_Msk;
    376e:	bf44      	itt	mi
    3770:	f06f 0201 	mvnmi.w	r2, #1
    3774:	f8c3 2400 	strmi.w	r2, [r3, #1024]	; 0x400
            }
        }

        /* Workaround for Errata 69 "VREGMAIN configuration is not retained in System OFF" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf53_errata_69())
    3778:	f7ff ff7a 	bl	3670 <nrf53_errata_42>
    377c:	b118      	cbz	r0, 3786 <SystemInit+0xd2>
        {
            *((volatile uint32_t *)0x5000470Cul) =0x65ul;
    377e:	2265      	movs	r2, #101	; 0x65
    3780:	4b1e      	ldr	r3, [pc, #120]	; (37fc <SystemInit+0x148>)
    3782:	f8c3 270c 	str.w	r2, [r3, #1804]	; 0x70c
                    uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul));
    3786:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    378a:	f8d3 2130 	ldr.w	r2, [r3, #304]	; 0x130
                    uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul));
    378e:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
                if (var1 == 0x07)
    3792:	2a07      	cmp	r2, #7
    3794:	d116      	bne.n	37c4 <SystemInit+0x110>
        }

        if (nrf53_errata_140())
        {
            if (*(volatile uint32_t *)0x50032420 & 0x80000000)
    3796:	4b1d      	ldr	r3, [pc, #116]	; (380c <SystemInit+0x158>)
    3798:	f8d3 3420 	ldr.w	r3, [r3, #1056]	; 0x420
    379c:	2b00      	cmp	r3, #0
    379e:	da11      	bge.n	37c4 <SystemInit+0x110>
            {
                /* Reset occured during calibration */
                NRF_CLOCK_S->LFCLKSRC = CLOCK_LFCLKSRC_SRC_LFSYNT;
    37a0:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    37a4:	2203      	movs	r2, #3
    37a6:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
                NRF_CLOCK_S->TASKS_LFCLKSTART = 1;
    37aa:	2201      	movs	r2, #1
    37ac:	609a      	str	r2, [r3, #8]
                while (NRF_CLOCK_S->EVENTS_LFCLKSTARTED == 0) {}
    37ae:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
    37b2:	2a00      	cmp	r2, #0
    37b4:	d0fb      	beq.n	37ae <SystemInit+0xfa>
                NRF_CLOCK_S->EVENTS_LFCLKSTARTED = 0;
    37b6:	2200      	movs	r2, #0
    37b8:	f8c3 2104 	str.w	r2, [r3, #260]	; 0x104
                NRF_CLOCK_S->TASKS_LFCLKSTOP = 1;
    37bc:	2201      	movs	r2, #1
    37be:	60da      	str	r2, [r3, #12]
                NRF_CLOCK_S->LFCLKSRC = CLOCK_LFCLKSRC_SRC_LFRC;
    37c0:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518

        #endif

        /* Allow Non-Secure code to run FPU instructions.
         * If only the secure code should control FPU power state these registers should be configured accordingly in the secure application code. */
        SCB->NSACR |= (3UL << 10);
    37c4:	4a12      	ldr	r2, [pc, #72]	; (3810 <SystemInit+0x15c>)
    37c6:	f8d2 308c 	ldr.w	r3, [r2, #140]	; 0x8c
    37ca:	f443 6340 	orr.w	r3, r3, #3072	; 0xc00
    37ce:	f8c2 308c 	str.w	r3, [r2, #140]	; 0x8c
                /* Do nothing, allow user code to handle APPROTECT. Use this if you want to enable authenticated debug. */

        #else
            /* Load APPROTECT soft branch from UICR.
               If UICR->APPROTECT is disabled, CTRLAP->APPROTECT will be disabled. */
            NRF_CTRLAP_S->APPROTECT.DISABLE = NRF_UICR_S->APPROTECT;
    37d2:	4a10      	ldr	r2, [pc, #64]	; (3814 <SystemInit+0x160>)
    37d4:	4b10      	ldr	r3, [pc, #64]	; (3818 <SystemInit+0x164>)
    37d6:	6811      	ldr	r1, [r2, #0]
    37d8:	f8c3 1544 	str.w	r1, [r3, #1348]	; 0x544
                /* Do nothing, allow user code to handle SECURE APPROTECT. Use this if you want to enable authenticated debug. */

        #else
            /* Load SECURE APPROTECT soft branch from UICR.
               If UICR->SECUREAPPROTECT is disabled, CTRLAP->SECUREAPPROTECT will be disabled. */
            NRF_CTRLAP_S->SECUREAPPROTECT.DISABLE = NRF_UICR_S->SECUREAPPROTECT;
    37dc:	69d2      	ldr	r2, [r2, #28]
    37de:	f8c3 254c 	str.w	r2, [r3, #1356]	; 0x54c
        __DSB();
        __ISB();
    #endif

    SystemCoreClockUpdate();
}
    37e2:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    SystemCoreClockUpdate();
    37e6:	f7ff bf55 	b.w	3694 <SystemCoreClockUpdate>
            *((volatile uint32_t *)0x5000470Cul) = 0x29ul;
    37ea:	2229      	movs	r2, #41	; 0x29
    37ec:	4b03      	ldr	r3, [pc, #12]	; (37fc <SystemInit+0x148>)
    37ee:	f8c3 270c 	str.w	r2, [r3, #1804]	; 0x70c
            *((volatile uint32_t *)0x5000473Cul) = 0x3ul;
    37f2:	2203      	movs	r2, #3
    37f4:	f8c3 273c 	str.w	r2, [r3, #1852]	; 0x73c
    37f8:	e780      	b.n	36fc <SystemInit+0x48>
    37fa:	bf00      	nop
    37fc:	50004000 	.word	0x50004000
    3800:	50039000 	.word	0x50039000
    3804:	beef0044 	.word	0xbeef0044
    3808:	000078a8 	.word	0x000078a8
    380c:	50032000 	.word	0x50032000
    3810:	e000ed00 	.word	0xe000ed00
    3814:	00ff8000 	.word	0x00ff8000
    3818:	50006000 	.word	0x50006000

0000381c <nrfx_flag32_alloc>:
{
    return (mask & NRFX_BIT(bitpos)) ? false : true;
}

nrfx_err_t nrfx_flag32_alloc(nrfx_atomic_t * p_mask, uint8_t *p_flag)
{
    381c:	b570      	push	{r4, r5, r6, lr}
        idx = 31 - NRF_CLZ(prev_mask);
        if (idx < 0) {
            return NRFX_ERROR_NO_MEM;
        }

        new_mask = prev_mask & ~NRFX_BIT(idx);
    381e:	2501      	movs	r5, #1
        prev_mask = *p_mask;
    3820:	6802      	ldr	r2, [r0, #0]
        idx = 31 - NRF_CLZ(prev_mask);
    3822:	fab2 f382 	clz	r3, r2
    3826:	f1c3 031f 	rsb	r3, r3, #31
    382a:	b2db      	uxtb	r3, r3
        new_mask = prev_mask & ~NRFX_BIT(idx);
    382c:	fa05 f403 	lsl.w	r4, r5, r3
    3830:	ea22 0404 	bic.w	r4, r2, r4
	return __atomic_compare_exchange_n(target, &old_value, new_value,
    3834:	e8d0 6fef 	ldaex	r6, [r0]
    3838:	4296      	cmp	r6, r2
    383a:	d104      	bne.n	3846 <nrfx_flag32_alloc+0x2a>
    383c:	e8c0 4fec 	stlex	ip, r4, [r0]
    3840:	f1bc 0f00 	cmp.w	ip, #0
    3844:	d1f6      	bne.n	3834 <nrfx_flag32_alloc+0x18>
    } while (!NRFX_ATOMIC_CAS(p_mask, prev_mask, new_mask));
    3846:	d1eb      	bne.n	3820 <nrfx_flag32_alloc+0x4>

    *p_flag = idx;

    return NRFX_SUCCESS;
}
    3848:	4801      	ldr	r0, [pc, #4]	; (3850 <nrfx_flag32_alloc+0x34>)
    *p_flag = idx;
    384a:	700b      	strb	r3, [r1, #0]
}
    384c:	bd70      	pop	{r4, r5, r6, pc}
    384e:	bf00      	nop
    3850:	0bad0000 	.word	0x0bad0000

00003854 <nrfx_flag32_free>:

nrfx_err_t nrfx_flag32_free(nrfx_atomic_t * p_mask, uint8_t flag)
{
    3854:	b510      	push	{r4, lr}
    uint32_t new_mask, prev_mask;

    if ((NRFX_BIT(flag) & *p_mask))
    3856:	6803      	ldr	r3, [r0, #0]
    3858:	40cb      	lsrs	r3, r1
    385a:	07db      	lsls	r3, r3, #31
    385c:	d410      	bmi.n	3880 <nrfx_flag32_free+0x2c>
        return NRFX_ERROR_INVALID_PARAM;
    }

    do {
        prev_mask = *p_mask;
        new_mask = prev_mask | NRFX_BIT(flag);
    385e:	2301      	movs	r3, #1
    3860:	408b      	lsls	r3, r1
        prev_mask = *p_mask;
    3862:	6802      	ldr	r2, [r0, #0]
        new_mask = prev_mask | NRFX_BIT(flag);
    3864:	ea43 0102 	orr.w	r1, r3, r2
    3868:	e8d0 4fef 	ldaex	r4, [r0]
    386c:	4294      	cmp	r4, r2
    386e:	d104      	bne.n	387a <nrfx_flag32_free+0x26>
    3870:	e8c0 1fec 	stlex	ip, r1, [r0]
    3874:	f1bc 0f00 	cmp.w	ip, #0
    3878:	d1f6      	bne.n	3868 <nrfx_flag32_free+0x14>
    } while (!NRFX_ATOMIC_CAS(p_mask, prev_mask, new_mask));
    387a:	d1f2      	bne.n	3862 <nrfx_flag32_free+0xe>

    return NRFX_SUCCESS;
    387c:	4801      	ldr	r0, [pc, #4]	; (3884 <nrfx_flag32_free+0x30>)
}
    387e:	bd10      	pop	{r4, pc}
        return NRFX_ERROR_INVALID_PARAM;
    3880:	4801      	ldr	r0, [pc, #4]	; (3888 <nrfx_flag32_free+0x34>)
    3882:	e7fc      	b.n	387e <nrfx_flag32_free+0x2a>
    3884:	0bad0000 	.word	0x0bad0000
    3888:	0bad0004 	.word	0x0bad0004

0000388c <nrfx_clock_init>:
nrfx_err_t nrfx_clock_init(nrfx_clock_event_handler_t event_handler)
{
    NRFX_ASSERT(event_handler);

    nrfx_err_t err_code = NRFX_SUCCESS;
    if (m_clock_cb.module_initialized)
    388c:	4b04      	ldr	r3, [pc, #16]	; (38a0 <nrfx_clock_init+0x14>)
    388e:	791a      	ldrb	r2, [r3, #4]
    3890:	b922      	cbnz	r2, 389c <nrfx_clock_init+0x10>
    {
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
        m_clock_cb.cal_state = CAL_STATE_IDLE;
#endif
        m_clock_cb.event_handler = event_handler;
        m_clock_cb.module_initialized = true;
    3892:	2201      	movs	r2, #1
        m_clock_cb.event_handler = event_handler;
    3894:	6018      	str	r0, [r3, #0]
        m_clock_cb.module_initialized = true;
    3896:	711a      	strb	r2, [r3, #4]
    nrfx_err_t err_code = NRFX_SUCCESS;
    3898:	4802      	ldr	r0, [pc, #8]	; (38a4 <nrfx_clock_init+0x18>)
    389a:	4770      	bx	lr
        err_code = NRFX_ERROR_ALREADY_INITIALIZED;
    389c:	4802      	ldr	r0, [pc, #8]	; (38a8 <nrfx_clock_init+0x1c>)
#endif
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    389e:	4770      	bx	lr
    38a0:	200009c4 	.word	0x200009c4
    38a4:	0bad0000 	.word	0x0bad0000
    38a8:	0bad000c 	.word	0x0bad000c

000038ac <nrfx_power_clock_irq_handler>:
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    38ac:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    }
}
#endif

void nrfx_clock_irq_handler(void)
{
    38b0:	b510      	push	{r4, lr}
    38b2:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED))
    38b6:	b152      	cbz	r2, 38ce <nrfx_power_clock_irq_handler+0x22>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    38b8:	2000      	movs	r0, #0
    38ba:	f8c3 0100 	str.w	r0, [r3, #256]	; 0x100
    38be:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    p_reg->INTENCLR = mask;
    38c2:	2201      	movs	r2, #1
    38c4:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
        {
            m_clock_cb.hfclk_started = true;
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
        }
#else
        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
    38c8:	4b23      	ldr	r3, [pc, #140]	; (3958 <nrfx_power_clock_irq_handler+0xac>)
    38ca:	681b      	ldr	r3, [r3, #0]
    38cc:	4798      	blx	r3
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    38ce:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    38d2:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
#endif
    }
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED))
    38d6:	b18a      	cbz	r2, 38fc <nrfx_power_clock_irq_handler+0x50>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    38d8:	2200      	movs	r2, #0
    38da:	f8c3 2104 	str.w	r2, [r3, #260]	; 0x104
    38de:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    38e2:	f8d3 2418 	ldr.w	r2, [r3, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    38e6:	f8d3 1418 	ldr.w	r1, [r3, #1048]	; 0x418
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_LFCLKSTARTED");

#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED)
        nrf_clock_lfclk_t lfclksrc;
        (void)nrf_clock_is_running(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK, &lfclksrc);
        if (lfclksrc == NRF_CLOCK_LFCLK_RC)
    38ea:	f002 0203 	and.w	r2, r2, #3
    38ee:	2a01      	cmp	r2, #1
    38f0:	f04f 0102 	mov.w	r1, #2
    38f4:	d128      	bne.n	3948 <nrfx_power_clock_irq_handler+0x9c>
    p_reg->LFCLKSRC = (uint32_t)(source);
    38f6:	f8c3 1518 	str.w	r1, [r3, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    38fa:	609a      	str	r2, [r3, #8]
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    38fc:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    3900:	f8d3 2120 	ldr.w	r2, [r3, #288]	; 0x120
        m_clock_cb.event_handler(NRFX_CLOCK_EVT_CAL_DONE);
    }
#endif // NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)

#if NRF_CLOCK_HAS_HFCLKAUDIO
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKAUDIOSTARTED))
    3904:	b162      	cbz	r2, 3920 <nrfx_power_clock_irq_handler+0x74>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3906:	2200      	movs	r2, #0
    3908:	f8c3 2120 	str.w	r2, [r3, #288]	; 0x120
    390c:	f8d3 2120 	ldr.w	r2, [r3, #288]	; 0x120
    p_reg->INTENCLR = mask;
    3910:	f44f 7280 	mov.w	r2, #256	; 0x100
    3914:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    {
        nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKAUDIOSTARTED);
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_HFCLKAUDIOSTARTED");
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HFAUDIO_STARTED_MASK);

        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLKAUDIO_STARTED);
    3918:	4b0f      	ldr	r3, [pc, #60]	; (3958 <nrfx_power_clock_irq_handler+0xac>)
    391a:	2004      	movs	r0, #4
    391c:	681b      	ldr	r3, [r3, #0]
    391e:	4798      	blx	r3
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    3920:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    3924:	f8d3 2124 	ldr.w	r2, [r3, #292]	; 0x124
    }
#endif

#if NRF_CLOCK_HAS_HFCLK192M
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLK192MSTARTED))
    3928:	b1aa      	cbz	r2, 3956 <nrfx_power_clock_irq_handler+0xaa>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    392a:	2200      	movs	r2, #0
    392c:	f8c3 2124 	str.w	r2, [r3, #292]	; 0x124
    3930:	f8d3 2124 	ldr.w	r2, [r3, #292]	; 0x124
    p_reg->INTENCLR = mask;
    3934:	f44f 7200 	mov.w	r2, #512	; 0x200
    3938:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    {
        nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLK192MSTARTED);
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_HFCLK192MSTARTED");
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF192M_STARTED_MASK);

        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK192M_STARTED);
    393c:	4b06      	ldr	r3, [pc, #24]	; (3958 <nrfx_power_clock_irq_handler+0xac>)
    393e:	2005      	movs	r0, #5
    }
#endif
}
    3940:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK192M_STARTED);
    3944:	681b      	ldr	r3, [r3, #0]
    3946:	4718      	bx	r3
    3948:	f8c3 1308 	str.w	r1, [r3, #776]	; 0x308
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    394c:	4b02      	ldr	r3, [pc, #8]	; (3958 <nrfx_power_clock_irq_handler+0xac>)
    394e:	2001      	movs	r0, #1
    3950:	681b      	ldr	r3, [r3, #0]
    3952:	4798      	blx	r3
    3954:	e7d2      	b.n	38fc <nrfx_power_clock_irq_handler+0x50>
}
    3956:	bd10      	pop	{r4, pc}
    3958:	200009c4 	.word	0x200009c4

0000395c <nrfx_dppi_channel_alloc>:
    // Clear all allocated groups.
    m_allocated_groups = DPPI_AVAILABLE_GROUPS_MASK;
}

nrfx_err_t nrfx_dppi_channel_alloc(uint8_t * p_channel)
{
    395c:	4601      	mov	r1, r0
    return nrfx_flag32_alloc(&m_allocated_channels, p_channel);
    395e:	4801      	ldr	r0, [pc, #4]	; (3964 <nrfx_dppi_channel_alloc+0x8>)
    3960:	f7ff bf5c 	b.w	381c <nrfx_flag32_alloc>
    3964:	200000f4 	.word	0x200000f4

00003968 <nrf_gpio_pin_port_decode>:
    uint32_t pin_number = *p_pin;
    3968:	6803      	ldr	r3, [r0, #0]
    *p_pin = pin_number & 0x1F;
    396a:	f003 021f 	and.w	r2, r3, #31
    396e:	6002      	str	r2, [r0, #0]
}
    3970:	4a03      	ldr	r2, [pc, #12]	; (3980 <nrf_gpio_pin_port_decode+0x18>)
    3972:	4804      	ldr	r0, [pc, #16]	; (3984 <nrf_gpio_pin_port_decode+0x1c>)
    return pin_number >> 5;
    3974:	095b      	lsrs	r3, r3, #5
}
    3976:	2b01      	cmp	r3, #1
    3978:	bf18      	it	ne
    397a:	4610      	movne	r0, r2
    397c:	4770      	bx	lr
    397e:	bf00      	nop
    3980:	50842500 	.word	0x50842500
    3984:	50842800 	.word	0x50842800

00003988 <pin_in_use_by_te>:
 *
 * @return True if pin uses GPIOTE task/event.
 */
static bool pin_in_use_by_te(uint32_t pin)
{
    return m_cb.pin_flags[pin] & PIN_FLAG_TE_USED;
    3988:	4b03      	ldr	r3, [pc, #12]	; (3998 <pin_in_use_by_te+0x10>)
    398a:	3008      	adds	r0, #8
    398c:	f833 0010 	ldrh.w	r0, [r3, r0, lsl #1]
}
    3990:	f3c0 1040 	ubfx	r0, r0, #5, #1
    3994:	4770      	bx	lr
    3996:	bf00      	nop
    3998:	200000f8 	.word	0x200000f8

0000399c <call_handler>:
    nrf_gpiote_event_t event = nrfx_gpiote_in_event_get(pin);
    return nrf_gpiote_event_address_get(NRF_GPIOTE, event);
}

static void call_handler(nrfx_gpiote_pin_t pin, nrfx_gpiote_trigger_t trigger)
{
    399c:	b570      	push	{r4, r5, r6, lr}
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    399e:	4c0d      	ldr	r4, [pc, #52]	; (39d4 <call_handler+0x38>)
    39a0:	f100 0308 	add.w	r3, r0, #8
    39a4:	f834 3013 	ldrh.w	r3, [r4, r3, lsl #1]
{
    39a8:	4605      	mov	r5, r0
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    39aa:	05da      	lsls	r2, r3, #23
{
    39ac:	460e      	mov	r6, r1
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    39ae:	d507      	bpl.n	39c0 <call_handler+0x24>
    39b0:	f3c3 2343 	ubfx	r3, r3, #9, #4
    nrfx_gpiote_handler_config_t const * handler = channel_handler_get(pin);

    if (handler)
    {
        handler->handler(pin, trigger, handler->p_context);
    39b4:	eb04 02c3 	add.w	r2, r4, r3, lsl #3
    39b8:	6852      	ldr	r2, [r2, #4]
    39ba:	f854 3033 	ldr.w	r3, [r4, r3, lsl #3]
    39be:	4798      	blx	r3
    }
    if (m_cb.global_handler.handler)
    39c0:	68a3      	ldr	r3, [r4, #8]
    39c2:	b12b      	cbz	r3, 39d0 <call_handler+0x34>
    {
        m_cb.global_handler.handler(pin, trigger, m_cb.global_handler.p_context);
    39c4:	4631      	mov	r1, r6
    39c6:	4628      	mov	r0, r5
    39c8:	68e2      	ldr	r2, [r4, #12]
    }
}
    39ca:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
        m_cb.global_handler.handler(pin, trigger, m_cb.global_handler.p_context);
    39ce:	4718      	bx	r3
}
    39d0:	bd70      	pop	{r4, r5, r6, pc}
    39d2:	bf00      	nop
    39d4:	200000f8 	.word	0x200000f8

000039d8 <release_handler>:
{
    39d8:	b410      	push	{r4}
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    39da:	4a12      	ldr	r2, [pc, #72]	; (3a24 <release_handler+0x4c>)
    39dc:	3008      	adds	r0, #8
    39de:	f832 3010 	ldrh.w	r3, [r2, r0, lsl #1]
    39e2:	05d9      	lsls	r1, r3, #23
    39e4:	d51b      	bpl.n	3a1e <release_handler+0x46>
    39e6:	f3c3 2143 	ubfx	r1, r3, #9, #4
    m_cb.pin_flags[pin] &= ~PIN_HANDLER_MASK;
    39ea:	f423 53f8 	bic.w	r3, r3, #7936	; 0x1f00
    39ee:	f822 3010 	strh.w	r3, [r2, r0, lsl #1]
    for (uint32_t i = 0; i < MAX_PIN_NUMBER; i++)
    39f2:	2000      	movs	r0, #0
    39f4:	f102 040e 	add.w	r4, r2, #14
        if (PIN_GET_HANDLER_ID(m_cb.pin_flags[i]) == handler_id)
    39f8:	f834 3f02 	ldrh.w	r3, [r4, #2]!
    39fc:	f413 7f80 	tst.w	r3, #256	; 0x100
    3a00:	d003      	beq.n	3a0a <release_handler+0x32>
    3a02:	f3c3 2343 	ubfx	r3, r3, #9, #4
    3a06:	4299      	cmp	r1, r3
    3a08:	d009      	beq.n	3a1e <release_handler+0x46>
    for (uint32_t i = 0; i < MAX_PIN_NUMBER; i++)
    3a0a:	3001      	adds	r0, #1
    3a0c:	2830      	cmp	r0, #48	; 0x30
    3a0e:	d1f3      	bne.n	39f8 <release_handler+0x20>
        m_cb.handlers[handler_id].handler = NULL;
    3a10:	2300      	movs	r3, #0
    3a12:	f842 3031 	str.w	r3, [r2, r1, lsl #3]
        nrfx_err_t err = nrfx_flag32_free(&m_cb.available_evt_handlers, handler_id);
    3a16:	4804      	ldr	r0, [pc, #16]	; (3a28 <release_handler+0x50>)
}
    3a18:	bc10      	pop	{r4}
        nrfx_err_t err = nrfx_flag32_free(&m_cb.available_evt_handlers, handler_id);
    3a1a:	f7ff bf1b 	b.w	3854 <nrfx_flag32_free>
}
    3a1e:	bc10      	pop	{r4}
    3a20:	4770      	bx	lr
    3a22:	bf00      	nop
    3a24:	200000f8 	.word	0x200000f8
    3a28:	2000016c 	.word	0x2000016c

00003a2c <pin_handler_trigger_uninit>:
{
    3a2c:	b538      	push	{r3, r4, r5, lr}
    3a2e:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin))
    3a30:	f7ff ffaa 	bl	3988 <pin_in_use_by_te>
    3a34:	4c0b      	ldr	r4, [pc, #44]	; (3a64 <pin_handler_trigger_uninit+0x38>)
    3a36:	f102 0508 	add.w	r5, r2, #8
    3a3a:	b160      	cbz	r0, 3a56 <pin_handler_trigger_uninit+0x2a>
                         ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
}

NRF_STATIC_INLINE void nrf_gpiote_te_default(NRF_GPIOTE_Type * p_reg, uint32_t idx)
{
    p_reg->CONFIG[idx] = 0;
    3a3c:	2100      	movs	r1, #0
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    3a3e:	f834 3015 	ldrh.w	r3, [r4, r5, lsl #1]
        nrf_gpiote_te_default(NRF_GPIOTE, pin_te_get(pin));
    3a42:	0b5b      	lsrs	r3, r3, #13
    3a44:	009b      	lsls	r3, r3, #2
    3a46:	f103 43a0 	add.w	r3, r3, #1342177280	; 0x50000000
    3a4a:	f503 4350 	add.w	r3, r3, #53248	; 0xd000
    3a4e:	f8c3 1510 	str.w	r1, [r3, #1296]	; 0x510
#if defined(NRF9160_XXAA) || defined(NRF5340_XXAA)
    p_reg->CONFIG[idx] = 0;
    3a52:	f8c3 1510 	str.w	r1, [r3, #1296]	; 0x510
    release_handler(pin);
    3a56:	4610      	mov	r0, r2
    3a58:	f7ff ffbe 	bl	39d8 <release_handler>
    m_cb.pin_flags[pin] = PIN_FLAG_NOT_USED;
    3a5c:	2300      	movs	r3, #0
    3a5e:	f824 3015 	strh.w	r3, [r4, r5, lsl #1]
}
    3a62:	bd38      	pop	{r3, r4, r5, pc}
    3a64:	200000f8 	.word	0x200000f8

00003a68 <nrfx_gpiote_input_configure>:
{
    3a68:	e92d 41ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr}
    3a6c:	4604      	mov	r4, r0
    3a6e:	4690      	mov	r8, r2
    3a70:	461d      	mov	r5, r3
    if (p_input_config)
    3a72:	b301      	cbz	r1, 3ab6 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x1e>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    3a74:	4e4f      	ldr	r6, [pc, #316]	; (3bb4 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x11c>)
    3a76:	f100 0708 	add.w	r7, r0, #8
    return pin_is_output(pin) && pin_in_use_by_te(pin);
    3a7a:	f836 3017 	ldrh.w	r3, [r6, r7, lsl #1]
    3a7e:	079b      	lsls	r3, r3, #30
    3a80:	d502      	bpl.n	3a88 <nrfx_gpiote_input_configure+0x20>
    3a82:	f7ff ff81 	bl	3988 <pin_in_use_by_te>
    3a86:	bb28      	cbnz	r0, 3ad4 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x3c>
        nrf_gpio_pin_dir_t dir = NRF_GPIO_PIN_DIR_INPUT;
    3a88:	2300      	movs	r3, #0
        nrf_gpio_reconfigure(pin, &dir, &input_connect, &p_input_config->pull, NULL, NULL);
    3a8a:	4620      	mov	r0, r4
    3a8c:	e9cd 3300 	strd	r3, r3, [sp]
        nrf_gpio_pin_dir_t dir = NRF_GPIO_PIN_DIR_INPUT;
    3a90:	f88d 300e 	strb.w	r3, [sp, #14]
        nrf_gpio_pin_input_t input_connect = NRF_GPIO_PIN_INPUT_CONNECT;
    3a94:	f88d 300f 	strb.w	r3, [sp, #15]
        nrf_gpio_reconfigure(pin, &dir, &input_connect, &p_input_config->pull, NULL, NULL);
    3a98:	f10d 020f 	add.w	r2, sp, #15
    3a9c:	460b      	mov	r3, r1
    3a9e:	f10d 010e 	add.w	r1, sp, #14
    3aa2:	f002 fff6 	bl	6a92 <nrf_gpio_reconfigure>
        m_cb.pin_flags[pin] &= ~PIN_FLAG_OUTPUT;
    3aa6:	f836 3017 	ldrh.w	r3, [r6, r7, lsl #1]
    3aaa:	f023 0302 	bic.w	r3, r3, #2
        m_cb.pin_flags[pin] |= PIN_FLAG_IN_USE;
    3aae:	f043 0301 	orr.w	r3, r3, #1
    3ab2:	f826 3017 	strh.w	r3, [r6, r7, lsl #1]
    if (p_trigger_config)
    3ab6:	f1b8 0f00 	cmp.w	r8, #0
    3aba:	d02d      	beq.n	3b18 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x80>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    3abc:	4e3d      	ldr	r6, [pc, #244]	; (3bb4 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x11c>)
    3abe:	f104 0708 	add.w	r7, r4, #8
    3ac2:	f836 1017 	ldrh.w	r1, [r6, r7, lsl #1]
        nrfx_gpiote_trigger_t trigger = p_trigger_config->trigger;
    3ac6:	f898 0000 	ldrb.w	r0, [r8]
        if (pin_is_output(pin))
    3aca:	078a      	lsls	r2, r1, #30
        bool use_evt = p_trigger_config->p_in_channel ? true : false;
    3acc:	f8d8 3004 	ldr.w	r3, [r8, #4]
        if (pin_is_output(pin))
    3ad0:	d502      	bpl.n	3ad8 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x40>
            if (use_evt)
    3ad2:	b1cb      	cbz	r3, 3b08 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x70>
            return NRFX_ERROR_INVALID_PARAM;
    3ad4:	4838      	ldr	r0, [pc, #224]	; (3bb8 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x120>)
    3ad6:	e021      	b.n	3b1c <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x84>
            m_cb.pin_flags[pin] &= ~(PIN_TE_ID_MASK | PIN_FLAG_TE_USED);
    3ad8:	f021 0120 	bic.w	r1, r1, #32
    3adc:	04c9      	lsls	r1, r1, #19
    3ade:	0cc9      	lsrs	r1, r1, #19
    3ae0:	f826 1017 	strh.w	r1, [r6, r7, lsl #1]
            if (use_evt)
    3ae4:	b183      	cbz	r3, 3b08 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x70>
                if (!edge)
    3ae6:	2803      	cmp	r0, #3
    3ae8:	d8f4      	bhi.n	3ad4 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x3c>
                uint8_t ch = *p_trigger_config->p_in_channel;
    3aea:	f8d8 3004 	ldr.w	r3, [r8, #4]
    3aee:	f893 c000 	ldrb.w	ip, [r3]
                if (trigger == NRFX_GPIOTE_TRIGGER_NONE)
    3af2:	4662      	mov	r2, ip
    3af4:	0092      	lsls	r2, r2, #2
    3af6:	f102 42a0 	add.w	r2, r2, #1342177280	; 0x50000000
    3afa:	f502 4250 	add.w	r2, r2, #53248	; 0xd000
    3afe:	b980      	cbnz	r0, 3b22 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x8a>
    p_reg->CONFIG[idx] = 0;
    3b00:	f8c2 0510 	str.w	r0, [r2, #1296]	; 0x510
    p_reg->CONFIG[idx] = 0;
    3b04:	f8c2 0510 	str.w	r0, [r2, #1296]	; 0x510
        m_cb.pin_flags[pin] &= ~PIN_FLAG_TRIG_MODE_MASK;
    3b08:	f836 3017 	ldrh.w	r3, [r6, r7, lsl #1]
    3b0c:	f023 031c 	bic.w	r3, r3, #28
        m_cb.pin_flags[pin] |= PIN_FLAG_TRIG_MODE_SET(trigger);
    3b10:	ea43 0380 	orr.w	r3, r3, r0, lsl #2
    3b14:	f826 3017 	strh.w	r3, [r6, r7, lsl #1]
    if (p_handler_config)
    3b18:	bb1d      	cbnz	r5, 3b62 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0xca>
        err = NRFX_SUCCESS;
    3b1a:	4828      	ldr	r0, [pc, #160]	; (3bbc <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x124>)
}
    3b1c:	b004      	add	sp, #16
    3b1e:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
   p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk;
    3b22:	f8d2 3510 	ldr.w	r3, [r2, #1296]	; 0x510
                    m_cb.pin_flags[pin] |= PIN_FLAG_TE_ID(ch);
    3b26:	ea41 314c 	orr.w	r1, r1, ip, lsl #13
    3b2a:	f023 0303 	bic.w	r3, r3, #3
    3b2e:	f8c2 3510 	str.w	r3, [r2, #1296]	; 0x510
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk);
    3b32:	f8d2 3510 	ldr.w	r3, [r2, #1296]	; 0x510
    3b36:	f041 0120 	orr.w	r1, r1, #32
    3b3a:	f423 334f 	bic.w	r3, r3, #211968	; 0x33c00
    3b3e:	f423 7340 	bic.w	r3, r3, #768	; 0x300
    3b42:	f8c2 3510 	str.w	r3, [r2, #1296]	; 0x510
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    3b46:	0223      	lsls	r3, r4, #8
    3b48:	f8d2 e510 	ldr.w	lr, [r2, #1296]	; 0x510
    3b4c:	f403 537c 	and.w	r3, r3, #16128	; 0x3f00
    3b50:	ea43 4300 	orr.w	r3, r3, r0, lsl #16
    3b54:	ea43 030e 	orr.w	r3, r3, lr
    3b58:	f8c2 3510 	str.w	r3, [r2, #1296]	; 0x510
    3b5c:	f826 1017 	strh.w	r1, [r6, r7, lsl #1]
    3b60:	e7d2      	b.n	3b08 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x70>
    release_handler(pin);
    3b62:	4620      	mov	r0, r4
        err = pin_handler_set(pin, p_handler_config->handler, p_handler_config->p_context);
    3b64:	e9d5 6700 	ldrd	r6, r7, [r5]
    release_handler(pin);
    3b68:	f7ff ff36 	bl	39d8 <release_handler>
    if (!handler)
    3b6c:	2e00      	cmp	r6, #0
    3b6e:	d0d4      	beq.n	3b1a <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x82>
        if ((m_cb.handlers[i].handler == handler) && (m_cb.handlers[i].p_context == p_context))
    3b70:	4d10      	ldr	r5, [pc, #64]	; (3bb4 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x11c>)
    3b72:	e9d5 2300 	ldrd	r2, r3, [r5]
    3b76:	4296      	cmp	r6, r2
    3b78:	d101      	bne.n	3b7e <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0xe6>
    3b7a:	429f      	cmp	r7, r3
    3b7c:	d018      	beq.n	3bb0 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x118>
        err = nrfx_flag32_alloc(&m_cb.available_evt_handlers, &id);
    3b7e:	4810      	ldr	r0, [pc, #64]	; (3bc0 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x128>)
    3b80:	f10d 010f 	add.w	r1, sp, #15
    3b84:	f7ff fe4a 	bl	381c <nrfx_flag32_alloc>
        if (err != NRFX_SUCCESS)
    3b88:	4b0c      	ldr	r3, [pc, #48]	; (3bbc <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x124>)
    3b8a:	4298      	cmp	r0, r3
    3b8c:	d1c6      	bne.n	3b1c <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x84>
        handler_id = (int32_t)id;
    3b8e:	f89d 200f 	ldrb.w	r2, [sp, #15]
    m_cb.handlers[handler_id].p_context = p_context;
    3b92:	eb05 03c2 	add.w	r3, r5, r2, lsl #3
    m_cb.pin_flags[pin] |= PIN_FLAG_HANDLER(handler_id);
    3b96:	3408      	adds	r4, #8
    m_cb.handlers[handler_id].p_context = p_context;
    3b98:	605f      	str	r7, [r3, #4]
    m_cb.pin_flags[pin] |= PIN_FLAG_HANDLER(handler_id);
    3b9a:	f835 3014 	ldrh.w	r3, [r5, r4, lsl #1]
    m_cb.handlers[handler_id].handler = handler;
    3b9e:	f845 6032 	str.w	r6, [r5, r2, lsl #3]
    m_cb.pin_flags[pin] |= PIN_FLAG_HANDLER(handler_id);
    3ba2:	ea43 2342 	orr.w	r3, r3, r2, lsl #9
    3ba6:	f443 7380 	orr.w	r3, r3, #256	; 0x100
    3baa:	f825 3014 	strh.w	r3, [r5, r4, lsl #1]
    return NRFX_SUCCESS;
    3bae:	e7b4      	b.n	3b1a <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0x82>
        if ((m_cb.handlers[i].handler == handler) && (m_cb.handlers[i].p_context == p_context))
    3bb0:	2200      	movs	r2, #0
    3bb2:	e7ee      	b.n	3b92 <CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT+0xfa>
    3bb4:	200000f8 	.word	0x200000f8
    3bb8:	0bad0004 	.word	0x0bad0004
    3bbc:	0bad0000 	.word	0x0bad0000
    3bc0:	2000016c 	.word	0x2000016c

00003bc4 <nrfx_gpiote_output_configure>:
{
    3bc4:	b5f0      	push	{r4, r5, r6, r7, lr}
    3bc6:	4604      	mov	r4, r0
    3bc8:	4615      	mov	r5, r2
    3bca:	b085      	sub	sp, #20
    if (p_config)
    3bcc:	b319      	cbz	r1, 3c16 <nrfx_gpiote_output_configure+0x52>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    3bce:	4e34      	ldr	r6, [pc, #208]	; (3ca0 <nrfx_gpiote_output_configure+0xdc>)
    3bd0:	f100 0708 	add.w	r7, r0, #8
    3bd4:	f836 2017 	ldrh.w	r2, [r6, r7, lsl #1]
        if (pin_is_input(pin) && pin_in_use_by_te(pin))
    3bd8:	0793      	lsls	r3, r2, #30
    3bda:	d403      	bmi.n	3be4 <nrfx_gpiote_output_configure+0x20>
    3bdc:	f7ff fed4 	bl	3988 <pin_in_use_by_te>
    3be0:	2800      	cmp	r0, #0
    3be2:	d15a      	bne.n	3c9a <nrfx_gpiote_output_configure+0xd6>
        if (pin_has_trigger(pin) && (p_config->input_connect == NRF_GPIO_PIN_INPUT_DISCONNECT))
    3be4:	f012 0f1c 	tst.w	r2, #28
    3be8:	d002      	beq.n	3bf0 <nrfx_gpiote_output_configure+0x2c>
    3bea:	784b      	ldrb	r3, [r1, #1]
    3bec:	2b01      	cmp	r3, #1
    3bee:	d054      	beq.n	3c9a <nrfx_gpiote_output_configure+0xd6>
        nrf_gpio_pin_dir_t dir = NRF_GPIO_PIN_DIR_OUTPUT;
    3bf0:	2301      	movs	r3, #1
    3bf2:	f88d 300f 	strb.w	r3, [sp, #15]
        nrf_gpio_reconfigure(pin, &dir, &p_config->input_connect, &p_config->pull,
    3bf6:	2300      	movs	r3, #0
    3bf8:	1c4a      	adds	r2, r1, #1
    3bfa:	e9cd 1300 	strd	r1, r3, [sp]
    3bfe:	4620      	mov	r0, r4
    3c00:	1c8b      	adds	r3, r1, #2
    3c02:	f10d 010f 	add.w	r1, sp, #15
    3c06:	f002 ff44 	bl	6a92 <nrf_gpio_reconfigure>
        m_cb.pin_flags[pin] |= PIN_FLAG_IN_USE | PIN_FLAG_OUTPUT;
    3c0a:	f836 3017 	ldrh.w	r3, [r6, r7, lsl #1]
    3c0e:	f043 0303 	orr.w	r3, r3, #3
    3c12:	f826 3017 	strh.w	r3, [r6, r7, lsl #1]
    if (p_task_config)
    3c16:	b915      	cbnz	r5, 3c1e <nrfx_gpiote_output_configure+0x5a>
    return NRFX_SUCCESS;
    3c18:	4822      	ldr	r0, [pc, #136]	; (3ca4 <nrfx_gpiote_output_configure+0xe0>)
}
    3c1a:	b005      	add	sp, #20
    3c1c:	bdf0      	pop	{r4, r5, r6, r7, pc}
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    3c1e:	4e20      	ldr	r6, [pc, #128]	; (3ca0 <nrfx_gpiote_output_configure+0xdc>)
    3c20:	f104 0708 	add.w	r7, r4, #8
    3c24:	f836 0017 	ldrh.w	r0, [r6, r7, lsl #1]
        if (pin_is_input(pin))
    3c28:	0783      	lsls	r3, r0, #30
    3c2a:	d536      	bpl.n	3c9a <nrfx_gpiote_output_configure+0xd6>
        uint32_t ch = p_task_config->task_ch;
    3c2c:	f895 c000 	ldrb.w	ip, [r5]
    p_reg->CONFIG[idx] = 0;
    3c30:	2300      	movs	r3, #0
    3c32:	4661      	mov	r1, ip
        m_cb.pin_flags[pin] &= ~(PIN_FLAG_TE_USED | PIN_TE_ID_MASK);
    3c34:	f020 0020 	bic.w	r0, r0, #32
    3c38:	0089      	lsls	r1, r1, #2
    3c3a:	f101 41a0 	add.w	r1, r1, #1342177280	; 0x50000000
    3c3e:	04c0      	lsls	r0, r0, #19
    3c40:	f501 4150 	add.w	r1, r1, #53248	; 0xd000
    3c44:	0cc0      	lsrs	r0, r0, #19
    3c46:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
    3c4a:	f826 0017 	strh.w	r0, [r6, r7, lsl #1]
    p_reg->CONFIG[idx] = 0;
    3c4e:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
        if (p_task_config->polarity != NRF_GPIOTE_POLARITY_NONE)
    3c52:	786a      	ldrb	r2, [r5, #1]
    3c54:	2a00      	cmp	r2, #0
    3c56:	d0df      	beq.n	3c18 <nrfx_gpiote_output_configure+0x54>
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk |
    3c58:	f8d1 3510 	ldr.w	r3, [r1, #1296]	; 0x510
                                      p_task_config->init_val);
    3c5c:	78ad      	ldrb	r5, [r5, #2]
    3c5e:	f423 1399 	bic.w	r3, r3, #1253376	; 0x132000
    3c62:	f423 53f8 	bic.w	r3, r3, #7936	; 0x1f00
    3c66:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    3c6a:	f8d1 e510 	ldr.w	lr, [r1, #1296]	; 0x510
    3c6e:	0223      	lsls	r3, r4, #8
    3c70:	f403 537c 	and.w	r3, r3, #16128	; 0x3f00
                        ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk) |
    3c74:	0412      	lsls	r2, r2, #16
    3c76:	f402 3240 	and.w	r2, r2, #196608	; 0x30000
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    3c7a:	ea43 030e 	orr.w	r3, r3, lr
    3c7e:	4313      	orrs	r3, r2
                        ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
    3c80:	052a      	lsls	r2, r5, #20
    3c82:	f402 1280 	and.w	r2, r2, #1048576	; 0x100000
            m_cb.pin_flags[pin] |= PIN_FLAG_TE_ID(ch);
    3c86:	ea40 304c 	orr.w	r0, r0, ip, lsl #13
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    3c8a:	4313      	orrs	r3, r2
    3c8c:	f040 0020 	orr.w	r0, r0, #32
    3c90:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
    3c94:	f826 0017 	strh.w	r0, [r6, r7, lsl #1]
    3c98:	e7be      	b.n	3c18 <nrfx_gpiote_output_configure+0x54>
{
    3c9a:	4803      	ldr	r0, [pc, #12]	; (3ca8 <nrfx_gpiote_output_configure+0xe4>)
    3c9c:	e7bd      	b.n	3c1a <nrfx_gpiote_output_configure+0x56>
    3c9e:	bf00      	nop
    3ca0:	200000f8 	.word	0x200000f8
    3ca4:	0bad0000 	.word	0x0bad0000
    3ca8:	0bad0004 	.word	0x0bad0004

00003cac <nrfx_gpiote_global_callback_set>:
    m_cb.global_handler.handler = handler;
    3cac:	4b01      	ldr	r3, [pc, #4]	; (3cb4 <nrfx_gpiote_global_callback_set+0x8>)
    m_cb.global_handler.p_context = p_context;
    3cae:	e9c3 0102 	strd	r0, r1, [r3, #8]
}
    3cb2:	4770      	bx	lr
    3cb4:	200000f8 	.word	0x200000f8

00003cb8 <nrfx_gpiote_channel_get>:
{
    3cb8:	b508      	push	{r3, lr}
    3cba:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin))
    3cbc:	f7ff fe64 	bl	3988 <pin_in_use_by_te>
    3cc0:	b138      	cbz	r0, 3cd2 <nrfx_gpiote_channel_get+0x1a>
        *p_channel = PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    3cc2:	4b05      	ldr	r3, [pc, #20]	; (3cd8 <nrfx_gpiote_channel_get+0x20>)
    3cc4:	3208      	adds	r2, #8
    3cc6:	f833 3012 	ldrh.w	r3, [r3, r2, lsl #1]
        return NRFX_SUCCESS;
    3cca:	4804      	ldr	r0, [pc, #16]	; (3cdc <nrfx_gpiote_channel_get+0x24>)
        *p_channel = PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    3ccc:	0b5b      	lsrs	r3, r3, #13
    3cce:	700b      	strb	r3, [r1, #0]
}
    3cd0:	bd08      	pop	{r3, pc}
        return NRFX_ERROR_INVALID_PARAM;
    3cd2:	4803      	ldr	r0, [pc, #12]	; (3ce0 <nrfx_gpiote_channel_get+0x28>)
    3cd4:	e7fc      	b.n	3cd0 <nrfx_gpiote_channel_get+0x18>
    3cd6:	bf00      	nop
    3cd8:	200000f8 	.word	0x200000f8
    3cdc:	0bad0000 	.word	0x0bad0000
    3ce0:	0bad0004 	.word	0x0bad0004

00003ce4 <nrfx_gpiote_init>:
{
    3ce4:	b538      	push	{r3, r4, r5, lr}
    if (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED)
    3ce6:	4c0f      	ldr	r4, [pc, #60]	; (3d24 <nrfx_gpiote_init+0x40>)
    3ce8:	f894 5078 	ldrb.w	r5, [r4, #120]	; 0x78
    3cec:	b9bd      	cbnz	r5, 3d1e <nrfx_gpiote_init+0x3a>
    memset(m_cb.pin_flags, 0, sizeof(m_cb.pin_flags));
    3cee:	2260      	movs	r2, #96	; 0x60
    3cf0:	4629      	mov	r1, r5
    3cf2:	f104 0010 	add.w	r0, r4, #16
    3cf6:	f002 fa4d 	bl	6194 <memset>
    NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_GPIOTE));
    3cfa:	200d      	movs	r0, #13
    3cfc:	f7fd fc42 	bl	1584 <arch_irq_enable>
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    3d00:	4b09      	ldr	r3, [pc, #36]	; (3d28 <nrfx_gpiote_init+0x44>)
    return err_code;
    3d02:	480a      	ldr	r0, [pc, #40]	; (3d2c <nrfx_gpiote_init+0x48>)
    3d04:	f8c3 517c 	str.w	r5, [r3, #380]	; 0x17c
    3d08:	f8d3 217c 	ldr.w	r2, [r3, #380]	; 0x17c
    p_reg->INTENSET = mask;
    3d0c:	f04f 4200 	mov.w	r2, #2147483648	; 0x80000000
    3d10:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    m_cb.state = NRFX_DRV_STATE_INITIALIZED;
    3d14:	2301      	movs	r3, #1
    3d16:	f884 3078 	strb.w	r3, [r4, #120]	; 0x78
    m_cb.available_evt_handlers = NRFX_BIT_MASK(NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS);
    3d1a:	6763      	str	r3, [r4, #116]	; 0x74
}
    3d1c:	bd38      	pop	{r3, r4, r5, pc}
        return err_code;
    3d1e:	4804      	ldr	r0, [pc, #16]	; (3d30 <nrfx_gpiote_init+0x4c>)
    3d20:	e7fc      	b.n	3d1c <nrfx_gpiote_init+0x38>
    3d22:	bf00      	nop
    3d24:	200000f8 	.word	0x200000f8
    3d28:	5000d000 	.word	0x5000d000
    3d2c:	0bad0000 	.word	0x0bad0000
    3d30:	0bad0005 	.word	0x0bad0005

00003d34 <nrfx_gpiote_is_init>:
    return (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED) ? true : false;
    3d34:	4b03      	ldr	r3, [pc, #12]	; (3d44 <nrfx_gpiote_is_init+0x10>)
    3d36:	f893 0078 	ldrb.w	r0, [r3, #120]	; 0x78
}
    3d3a:	3800      	subs	r0, #0
    3d3c:	bf18      	it	ne
    3d3e:	2001      	movne	r0, #1
    3d40:	4770      	bx	lr
    3d42:	bf00      	nop
    3d44:	200000f8 	.word	0x200000f8

00003d48 <nrfx_gpiote_channel_free>:
{
    3d48:	4601      	mov	r1, r0
    return nrfx_flag32_free(&m_cb.available_channels_mask, channel);
    3d4a:	4801      	ldr	r0, [pc, #4]	; (3d50 <nrfx_gpiote_channel_free+0x8>)
    3d4c:	f7ff bd82 	b.w	3854 <nrfx_flag32_free>
    3d50:	20000168 	.word	0x20000168

00003d54 <nrfx_gpiote_channel_alloc>:
{
    3d54:	4601      	mov	r1, r0
    return nrfx_flag32_alloc(&m_cb.available_channels_mask, p_channel);
    3d56:	4801      	ldr	r0, [pc, #4]	; (3d5c <nrfx_gpiote_channel_alloc+0x8>)
    3d58:	f7ff bd60 	b.w	381c <nrfx_flag32_alloc>
    3d5c:	20000168 	.word	0x20000168

00003d60 <nrfx_gpiote_trigger_enable>:
{
    3d60:	b537      	push	{r0, r1, r2, r4, r5, lr}
    3d62:	4604      	mov	r4, r0
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    3d64:	f7ff fe10 	bl	3988 <pin_in_use_by_te>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    3d68:	4b1e      	ldr	r3, [pc, #120]	; (3de4 <nrfx_gpiote_trigger_enable+0x84>)
    3d6a:	f104 0208 	add.w	r2, r4, #8
    3d6e:	f833 3012 	ldrh.w	r3, [r3, r2, lsl #1]
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    3d72:	b1e8      	cbz	r0, 3db0 <nrfx_gpiote_trigger_enable+0x50>
    3d74:	f013 0502 	ands.w	r5, r3, #2
    3d78:	d11a      	bne.n	3db0 <nrfx_gpiote_trigger_enable+0x50>
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    3d7a:	0b5b      	lsrs	r3, r3, #13
#endif

NRF_STATIC_INLINE nrf_gpiote_event_t nrf_gpiote_in_event_get(uint8_t index)
{
    NRFX_ASSERT(index < GPIOTE_CH_NUM);
    return (nrf_gpiote_event_t)NRFX_OFFSETOF(NRF_GPIOTE_Type, EVENTS_IN[index]);
    3d7c:	009a      	lsls	r2, r3, #2
    return ((uint32_t)p_reg + event);
    3d7e:	f102 40a0 	add.w	r0, r2, #1342177280	; 0x50000000
    3d82:	f500 4051 	add.w	r0, r0, #53504	; 0xd100
    3d86:	f102 42a0 	add.w	r2, r2, #1342177280	; 0x50000000
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    3d8a:	6005      	str	r5, [r0, #0]
    3d8c:	f502 4250 	add.w	r2, r2, #53248	; 0xd000
    3d90:	6800      	ldr	r0, [r0, #0]
   p_reg->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event;
    3d92:	f8d2 0510 	ldr.w	r0, [r2, #1296]	; 0x510
    3d96:	f040 0001 	orr.w	r0, r0, #1
    3d9a:	f8c2 0510 	str.w	r0, [r2, #1296]	; 0x510
        if (int_enable)
    3d9e:	b129      	cbz	r1, 3dac <nrfx_gpiote_trigger_enable+0x4c>
            nrf_gpiote_int_enable(NRF_GPIOTE, NRFX_BIT(ch));
    3da0:	2201      	movs	r2, #1
    3da2:	fa02 f303 	lsl.w	r3, r2, r3
    p_reg->INTENSET = mask;
    3da6:	4a10      	ldr	r2, [pc, #64]	; (3de8 <nrfx_gpiote_trigger_enable+0x88>)
    3da8:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
}
    3dac:	b003      	add	sp, #12
    3dae:	bd30      	pop	{r4, r5, pc}
    nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    3db0:	f3c3 0382 	ubfx	r3, r3, #2, #3
    if (trigger == NRFX_GPIOTE_TRIGGER_LOW)
    3db4:	2b04      	cmp	r3, #4
    3db6:	d011      	beq.n	3ddc <nrfx_gpiote_trigger_enable+0x7c>
    else if (trigger == NRFX_GPIOTE_TRIGGER_HIGH)
    3db8:	2b05      	cmp	r3, #5
    3dba:	d011      	beq.n	3de0 <nrfx_gpiote_trigger_enable+0x80>
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    3dbc:	a801      	add	r0, sp, #4
    3dbe:	9401      	str	r4, [sp, #4]
    3dc0:	f7ff fdd2 	bl	3968 <nrf_gpio_pin_port_decode>
    return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL);
    3dc4:	9b01      	ldr	r3, [sp, #4]
    return p_reg->IN;
    3dc6:	6901      	ldr	r1, [r0, #16]
    return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL);
    3dc8:	40d9      	lsrs	r1, r3
    3dca:	f001 0101 	and.w	r1, r1, #1
    3dce:	3102      	adds	r1, #2
        nrf_gpio_cfg_sense_set(pin, get_initial_sense(pin));
    3dd0:	4620      	mov	r0, r4
}
    3dd2:	b003      	add	sp, #12
    3dd4:	e8bd 4030 	ldmia.w	sp!, {r4, r5, lr}
        nrf_gpio_cfg_sense_set(pin, get_initial_sense(pin));
    3dd8:	f002 bea4 	b.w	6b24 <nrf_gpio_cfg_sense_set>
        sense = NRF_GPIO_PIN_SENSE_LOW;
    3ddc:	2103      	movs	r1, #3
    3dde:	e7f7      	b.n	3dd0 <nrfx_gpiote_trigger_enable+0x70>
        sense = NRF_GPIO_PIN_SENSE_HIGH;
    3de0:	2102      	movs	r1, #2
    3de2:	e7f5      	b.n	3dd0 <nrfx_gpiote_trigger_enable+0x70>
    3de4:	200000f8 	.word	0x200000f8
    3de8:	5000d000 	.word	0x5000d000

00003dec <nrfx_gpiote_trigger_disable>:
{
    3dec:	b508      	push	{r3, lr}
    3dee:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    3df0:	f7ff fdca 	bl	3988 <pin_in_use_by_te>
    3df4:	b1c0      	cbz	r0, 3e28 <nrfx_gpiote_trigger_disable+0x3c>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    3df6:	4b0f      	ldr	r3, [pc, #60]	; (3e34 <nrfx_gpiote_trigger_disable+0x48>)
    3df8:	f102 0108 	add.w	r1, r2, #8
    3dfc:	f833 3011 	ldrh.w	r3, [r3, r1, lsl #1]
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    3e00:	0799      	lsls	r1, r3, #30
    3e02:	d411      	bmi.n	3e28 <nrfx_gpiote_trigger_disable+0x3c>
        nrf_gpiote_int_disable(NRF_GPIOTE, NRFX_BIT(ch));
    3e04:	2201      	movs	r2, #1
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    3e06:	0b5b      	lsrs	r3, r3, #13
        nrf_gpiote_int_disable(NRF_GPIOTE, NRFX_BIT(ch));
    3e08:	409a      	lsls	r2, r3
    p_reg->INTENCLR = mask;
    3e0a:	490b      	ldr	r1, [pc, #44]	; (3e38 <nrfx_gpiote_trigger_disable+0x4c>)
    3e0c:	009b      	lsls	r3, r3, #2
    3e0e:	f103 43a0 	add.w	r3, r3, #1342177280	; 0x50000000
    3e12:	f8c1 2308 	str.w	r2, [r1, #776]	; 0x308
   p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk;
    3e16:	f503 4350 	add.w	r3, r3, #53248	; 0xd000
    3e1a:	f8d3 2510 	ldr.w	r2, [r3, #1296]	; 0x510
    3e1e:	f022 0203 	bic.w	r2, r2, #3
    3e22:	f8c3 2510 	str.w	r2, [r3, #1296]	; 0x510
}
    3e26:	bd08      	pop	{r3, pc}
        nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE);
    3e28:	2100      	movs	r1, #0
}
    3e2a:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
        nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE);
    3e2e:	4610      	mov	r0, r2
    3e30:	f002 be78 	b.w	6b24 <nrf_gpio_cfg_sense_set>
    3e34:	200000f8 	.word	0x200000f8
    3e38:	5000d000 	.word	0x5000d000

00003e3c <nrfx_gpiote_pin_uninit>:
{
    3e3c:	b513      	push	{r0, r1, r4, lr}
    return m_cb.pin_flags[pin] & PIN_FLAG_IN_USE;
    3e3e:	4b10      	ldr	r3, [pc, #64]	; (3e80 <nrfx_gpiote_pin_uninit+0x44>)
    3e40:	f100 0208 	add.w	r2, r0, #8
    3e44:	f833 3012 	ldrh.w	r3, [r3, r2, lsl #1]
{
    3e48:	4604      	mov	r4, r0
    if (!pin_in_use(pin))
    3e4a:	07db      	lsls	r3, r3, #31
    3e4c:	d516      	bpl.n	3e7c <nrfx_gpiote_pin_uninit+0x40>
    nrfx_gpiote_trigger_disable(pin);
    3e4e:	f7ff ffcd 	bl	3dec <nrfx_gpiote_trigger_disable>
    pin_handler_trigger_uninit(pin);
    3e52:	4620      	mov	r0, r4
    3e54:	f7ff fdea 	bl	3a2c <pin_handler_trigger_uninit>
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    3e58:	a801      	add	r0, sp, #4
    3e5a:	9401      	str	r4, [sp, #4]
    3e5c:	f7ff fd84 	bl	3968 <nrf_gpio_pin_port_decode>
    uint32_t cnf = reg->PIN_CNF[pin_number] & GPIO_PIN_CNF_MCUSEL_Msk;
    3e60:	9b01      	ldr	r3, [sp, #4]
    3e62:	eb00 0083 	add.w	r0, r0, r3, lsl #2
    3e66:	f8d0 3200 	ldr.w	r3, [r0, #512]	; 0x200
    3e6a:	f003 43e0 	and.w	r3, r3, #1879048192	; 0x70000000
    cnf |= ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)     |
    3e6e:	f043 0302 	orr.w	r3, r3, #2
    reg->PIN_CNF[pin_number] = cnf;
    3e72:	f8c0 3200 	str.w	r3, [r0, #512]	; 0x200
    nrf_gpio_cfg(
    3e76:	4803      	ldr	r0, [pc, #12]	; (3e84 <nrfx_gpiote_pin_uninit+0x48>)
}
    3e78:	b002      	add	sp, #8
    3e7a:	bd10      	pop	{r4, pc}
        return NRFX_ERROR_INVALID_PARAM;
    3e7c:	4802      	ldr	r0, [pc, #8]	; (3e88 <nrfx_gpiote_pin_uninit+0x4c>)
    3e7e:	e7fb      	b.n	3e78 <nrfx_gpiote_pin_uninit+0x3c>
    3e80:	200000f8 	.word	0x200000f8
    3e84:	0bad0000 	.word	0x0bad0000
    3e88:	0bad0004 	.word	0x0bad0004

00003e8c <nrfx_gpiote_irq_handler>:
        call_handler(pin, gpiote_polarity_to_trigger(polarity));
    }
}

void nrfx_gpiote_irq_handler(void)
{
    3e8c:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    uint32_t status = 0;
    3e90:	2600      	movs	r6, #0
    uint32_t i;
    nrf_gpiote_event_t event = NRF_GPIOTE_EVENT_IN_0;
    uint32_t mask = (uint32_t)NRF_GPIOTE_INT_IN0_MASK;
    3e92:	2201      	movs	r2, #1
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    3e94:	4634      	mov	r4, r6
{
    3e96:	4b63      	ldr	r3, [pc, #396]	; (4024 <CONFIG_COVERAGE_GCOV_HEAP_SIZE+0x24>)
    return p_reg->INTENSET & mask;
    3e98:	4863      	ldr	r0, [pc, #396]	; (4028 <CONFIG_COVERAGE_GCOV_HEAP_SIZE+0x28>)

    /* collect status of all GPIOTE pin events. Processing is done once all are collected and cleared.*/
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    3e9a:	4964      	ldr	r1, [pc, #400]	; (402c <CONFIG_COVERAGE_GCOV_HEAP_SIZE+0x2c>)
{
    3e9c:	b087      	sub	sp, #28
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    3e9e:	681d      	ldr	r5, [r3, #0]
    {
        if (nrf_gpiote_event_check(NRF_GPIOTE, event) &&
    3ea0:	b135      	cbz	r5, 3eb0 <nrfx_gpiote_irq_handler+0x24>
    return p_reg->INTENSET & mask;
    3ea2:	f8d0 5304 	ldr.w	r5, [r0, #772]	; 0x304
    3ea6:	4215      	tst	r5, r2
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    3ea8:	bf1e      	ittt	ne
    3eaa:	601c      	strne	r4, [r3, #0]
    3eac:	681d      	ldrne	r5, [r3, #0]
            nrf_gpiote_int_enable_check(NRF_GPIOTE, mask))
        {
            nrf_gpiote_event_clear(NRF_GPIOTE, event);
            status |= mask;
    3eae:	4316      	orrne	r6, r2
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    3eb0:	3304      	adds	r3, #4
    3eb2:	428b      	cmp	r3, r1
        }
        mask <<= 1;
    3eb4:	ea4f 0242 	mov.w	r2, r2, lsl #1
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    3eb8:	d1f1      	bne.n	3e9e <nrfx_gpiote_irq_handler+0x12>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    3eba:	f8df a16c 	ldr.w	sl, [pc, #364]	; 4028 <CONFIG_COVERAGE_GCOV_HEAP_SIZE+0x28>
    3ebe:	f8da 317c 	ldr.w	r3, [sl, #380]	; 0x17c
         * in ascending order. */
        event = (nrf_gpiote_event_t)((uint32_t)event + sizeof(uint32_t));
    }

    /* handle PORT event */
    if (nrf_gpiote_event_check(NRF_GPIOTE, NRF_GPIOTE_EVENT_PORT))
    3ec2:	2b00      	cmp	r3, #0
    3ec4:	f000 8091 	beq.w	3fea <nrfx_gpiote_irq_handler+0x15e>
        *p_masks = gpio_regs[i]->LATCH;
    3ec8:	f8df 8164 	ldr.w	r8, [pc, #356]	; 4030 <CONFIG_COVERAGE_GCOV_HEAP_SIZE+0x30>
    3ecc:	f8d8 3020 	ldr.w	r3, [r8, #32]
    3ed0:	9304      	str	r3, [sp, #16]
        gpio_regs[i]->LATCH = *p_masks;
    3ed2:	f8c8 3020 	str.w	r3, [r8, #32]
        *p_masks = gpio_regs[i]->LATCH;
    3ed6:	4b57      	ldr	r3, [pc, #348]	; (4034 <CONFIG_COVERAGE_GCOV_HEAP_SIZE+0x34>)
    3ed8:	6a1a      	ldr	r2, [r3, #32]
    3eda:	9205      	str	r2, [sp, #20]
        gpio_regs[i]->LATCH = *p_masks;
    3edc:	621a      	str	r2, [r3, #32]
        for (uint32_t i = 0; i < GPIO_COUNT; i++)
    3ede:	f04f 0900 	mov.w	r9, #0
            while (latch[i])
    3ee2:	f10d 0b10 	add.w	fp, sp, #16
    3ee6:	ea4f 1349 	mov.w	r3, r9, lsl #5
    3eea:	9300      	str	r3, [sp, #0]
    3eec:	e048      	b.n	3f80 <nrfx_gpiote_irq_handler+0xf4>
                uint32_t pin = NRF_CTZ(latch[i]);
    3eee:	fa94 f4a4 	rbit	r4, r4
    3ef2:	fab4 f484 	clz	r4, r4
                pin += 32 * i;
    3ef6:	9b00      	ldr	r3, [sp, #0]
                nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    3ef8:	4a4f      	ldr	r2, [pc, #316]	; (4038 <CONFIG_COVERAGE_GCOV_HEAP_SIZE+0x38>)
                pin += 32 * i;
    3efa:	441c      	add	r4, r3
                nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    3efc:	f104 0308 	add.w	r3, r4, #8
    3f00:	f832 7013 	ldrh.w	r7, [r2, r3, lsl #1]
__STATIC_INLINE void nrf_bitmask_bit_clear(uint32_t bit, void * p_mask)
{
    uint8_t * p_mask8 = (uint8_t *)p_mask;
    uint32_t byte_idx = BITMASK_BYTE_GET(bit);
    bit = BITMASK_RELBIT_GET(bit);
    p_mask8[byte_idx] &= ~(1 << bit);
    3f04:	2301      	movs	r3, #1
    uint32_t byte_idx = BITMASK_BYTE_GET(bit);
    3f06:	08e0      	lsrs	r0, r4, #3
    bit = BITMASK_RELBIT_GET(bit);
    3f08:	f004 0207 	and.w	r2, r4, #7
    p_mask8[byte_idx] &= ~(1 << bit);
    3f0c:	fa03 f202 	lsl.w	r2, r3, r2
    3f10:	f81b 3000 	ldrb.w	r3, [fp, r0]
    3f14:	9403      	str	r4, [sp, #12]
    3f16:	ea23 0302 	bic.w	r3, r3, r2
    3f1a:	f80b 3000 	strb.w	r3, [fp, r0]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    3f1e:	a803      	add	r0, sp, #12
    3f20:	f7ff fd22 	bl	3968 <nrf_gpio_pin_port_decode>
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    3f24:	9b03      	ldr	r3, [sp, #12]
    3f26:	08b9      	lsrs	r1, r7, #2
    3f28:	3380      	adds	r3, #128	; 0x80
    3f2a:	f850 3023 	ldr.w	r3, [r0, r3, lsl #2]
    3f2e:	f3c7 0582 	ubfx	r5, r7, #2, #3
    if (is_level(trigger))
    3f32:	074a      	lsls	r2, r1, #29
                nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    3f34:	462f      	mov	r7, r5
                                   GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos);
    3f36:	f3c3 4301 	ubfx	r3, r3, #16, #2
    if (is_level(trigger))
    3f3a:	d52b      	bpl.n	3f94 <nrfx_gpiote_irq_handler+0x108>
        call_handler(pin, trigger);
    3f3c:	4620      	mov	r0, r4
    3f3e:	4639      	mov	r1, r7
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    3f40:	b2dd      	uxtb	r5, r3
    3f42:	f7ff fd2b 	bl	399c <call_handler>
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    3f46:	a803      	add	r0, sp, #12
    3f48:	9403      	str	r4, [sp, #12]
    3f4a:	f7ff fd0d 	bl	3968 <nrf_gpio_pin_port_decode>
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    3f4e:	9b03      	ldr	r3, [sp, #12]
    3f50:	3380      	adds	r3, #128	; 0x80
    3f52:	f850 3023 	ldr.w	r3, [r0, r3, lsl #2]
        if (nrf_gpio_pin_sense_get(pin) == sense)
    3f56:	f3c3 4301 	ubfx	r3, r3, #16, #2
    3f5a:	429d      	cmp	r5, r3
    3f5c:	d107      	bne.n	3f6e <nrfx_gpiote_irq_handler+0xe2>
            nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE);
    3f5e:	2100      	movs	r1, #0
    3f60:	4620      	mov	r0, r4
    3f62:	f002 fddf 	bl	6b24 <nrf_gpio_cfg_sense_set>
            nrf_gpio_cfg_sense_set(pin, sense);
    3f66:	4629      	mov	r1, r5
    3f68:	4620      	mov	r0, r4
    3f6a:	f002 fddb 	bl	6b24 <nrf_gpio_cfg_sense_set>
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    3f6e:	a803      	add	r0, sp, #12
    3f70:	9403      	str	r4, [sp, #12]
    3f72:	f7ff fcf9 	bl	3968 <nrf_gpio_pin_port_decode>
    reg->LATCH = (1 << pin_number);
    3f76:	2201      	movs	r2, #1
    3f78:	9b03      	ldr	r3, [sp, #12]
    3f7a:	fa02 f303 	lsl.w	r3, r2, r3
    3f7e:	6203      	str	r3, [r0, #32]
            while (latch[i])
    3f80:	f85b 4029 	ldr.w	r4, [fp, r9, lsl #2]
    3f84:	2c00      	cmp	r4, #0
    3f86:	d1b2      	bne.n	3eee <nrfx_gpiote_irq_handler+0x62>
        for (uint32_t i = 0; i < GPIO_COUNT; i++)
    3f88:	f1b9 0f00 	cmp.w	r9, #0
    3f8c:	d11d      	bne.n	3fca <nrfx_gpiote_irq_handler+0x13e>
    3f8e:	f04f 0901 	mov.w	r9, #1
    3f92:	e7a8      	b.n	3ee6 <nrfx_gpiote_irq_handler+0x5a>
                NRF_GPIO_PIN_SENSE_LOW : NRF_GPIO_PIN_SENSE_HIGH;
    3f94:	2b02      	cmp	r3, #2
    3f96:	d10c      	bne.n	3fb2 <nrfx_gpiote_irq_handler+0x126>
        nrf_gpio_cfg_sense_set(pin, next_sense);
    3f98:	2103      	movs	r1, #3
    3f9a:	4620      	mov	r0, r4
    3f9c:	f002 fdc2 	bl	6b24 <nrf_gpio_cfg_sense_set>
        if ((trigger == NRFX_GPIOTE_TRIGGER_TOGGLE) ||
    3fa0:	f005 0305 	and.w	r3, r5, #5
    3fa4:	2b01      	cmp	r3, #1
    3fa6:	d1e2      	bne.n	3f6e <nrfx_gpiote_irq_handler+0xe2>
            call_handler(pin, trigger);
    3fa8:	4639      	mov	r1, r7
    3faa:	4620      	mov	r0, r4
    3fac:	f7ff fcf6 	bl	399c <call_handler>
    3fb0:	e7dd      	b.n	3f6e <nrfx_gpiote_irq_handler+0xe2>
        nrf_gpio_cfg_sense_set(pin, next_sense);
    3fb2:	2102      	movs	r1, #2
    3fb4:	4620      	mov	r0, r4
    3fb6:	9301      	str	r3, [sp, #4]
    3fb8:	f002 fdb4 	bl	6b24 <nrf_gpio_cfg_sense_set>
        if ((trigger == NRFX_GPIOTE_TRIGGER_TOGGLE) ||
    3fbc:	2d03      	cmp	r5, #3
    3fbe:	d0f3      	beq.n	3fa8 <nrfx_gpiote_irq_handler+0x11c>
            (sense == NRF_GPIO_PIN_SENSE_HIGH && trigger == NRFX_GPIOTE_TRIGGER_LOTOHI) ||
    3fc0:	9b01      	ldr	r3, [sp, #4]
    3fc2:	2b03      	cmp	r3, #3
    3fc4:	d1d3      	bne.n	3f6e <nrfx_gpiote_irq_handler+0xe2>
            (sense == NRF_GPIO_PIN_SENSE_LOW && trigger == NRFX_GPIOTE_TRIGGER_HITOLO))
    3fc6:	2d02      	cmp	r5, #2
    3fc8:	e7ed      	b.n	3fa6 <nrfx_gpiote_irq_handler+0x11a>
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    3fca:	f8ca 417c 	str.w	r4, [sl, #380]	; 0x17c
    3fce:	f8da 317c 	ldr.w	r3, [sl, #380]	; 0x17c
        *p_masks = gpio_regs[i]->LATCH;
    3fd2:	f8d8 3020 	ldr.w	r3, [r8, #32]
    3fd6:	4917      	ldr	r1, [pc, #92]	; (4034 <CONFIG_COVERAGE_GCOV_HEAP_SIZE+0x34>)
    3fd8:	9304      	str	r3, [sp, #16]
        gpio_regs[i]->LATCH = *p_masks;
    3fda:	f8c8 3020 	str.w	r3, [r8, #32]
        *p_masks = gpio_regs[i]->LATCH;
    3fde:	6a0a      	ldr	r2, [r1, #32]
        if (latch[port_idx])
    3fe0:	4313      	orrs	r3, r2
    3fe2:	9205      	str	r2, [sp, #20]
        gpio_regs[i]->LATCH = *p_masks;
    3fe4:	620a      	str	r2, [r1, #32]
    3fe6:	f47f af7a 	bne.w	3ede <nrfx_gpiote_irq_handler+0x52>
        mask &= ~NRFX_BIT(ch);
    3fea:	2401      	movs	r4, #1
    while (mask)
    3fec:	b916      	cbnz	r6, 3ff4 <nrfx_gpiote_irq_handler+0x168>
        port_event_handle();
    }

    /* Process pin events. */
    gpiote_evt_handle(status);
}
    3fee:	b007      	add	sp, #28
    3ff0:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
        uint32_t ch = NRF_CTZ(mask);
    3ff4:	fa96 f3a6 	rbit	r3, r6
    3ff8:	fab3 f383 	clz	r3, r3
        mask &= ~NRFX_BIT(ch);
    3ffc:	fa04 f203 	lsl.w	r2, r4, r3
    4000:	009b      	lsls	r3, r3, #2
    4002:	f103 43a0 	add.w	r3, r3, #1342177280	; 0x50000000
    4006:	f503 4350 	add.w	r3, r3, #53248	; 0xd000
    return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
    400a:	f8d3 0510 	ldr.w	r0, [r3, #1296]	; 0x510
    return (nrf_gpiote_polarity_t)((p_reg->CONFIG[idx] & GPIOTE_CONFIG_POLARITY_Msk) >>
    400e:	f8d3 1510 	ldr.w	r1, [r3, #1296]	; 0x510
        call_handler(pin, gpiote_polarity_to_trigger(polarity));
    4012:	f3c0 2005 	ubfx	r0, r0, #8, #6
    4016:	f3c1 4101 	ubfx	r1, r1, #16, #2
        mask &= ~NRFX_BIT(ch);
    401a:	ea26 0602 	bic.w	r6, r6, r2
        call_handler(pin, gpiote_polarity_to_trigger(polarity));
    401e:	f7ff fcbd 	bl	399c <call_handler>
    4022:	e7e3      	b.n	3fec <nrfx_gpiote_irq_handler+0x160>
    4024:	5000d100 	.word	0x5000d100
    4028:	5000d000 	.word	0x5000d000
    402c:	5000d120 	.word	0x5000d120
    4030:	50842500 	.word	0x50842500
    4034:	50842800 	.word	0x50842800
    4038:	200000f8 	.word	0x200000f8

0000403c <nvmc_readonly_mode_set>:

#if defined(NVMC_CONFIGNS_WEN_Msk)
NRF_STATIC_INLINE void nrf_nvmc_nonsecure_mode_set(NRF_NVMC_Type *    p_reg,
                                                   nrf_nvmc_ns_mode_t mode)
{
    p_reg->CONFIGNS = (uint32_t)mode;
    403c:	2200      	movs	r2, #0
    403e:	4b03      	ldr	r3, [pc, #12]	; (404c <nvmc_readonly_mode_set+0x10>)
    4040:	f8c3 2584 	str.w	r2, [r3, #1412]	; 0x584
    p_reg->CONFIG = (uint32_t)mode;
    4044:	f8c3 2504 	str.w	r2, [r3, #1284]	; 0x504
    nrf_nvmc_nonsecure_mode_set(NRF_NVMC, NRF_NVMC_NS_MODE_READONLY);
#endif
#if !defined(NRF_TRUSTZONE_NONSECURE)
    nrf_nvmc_mode_set(NRF_NVMC, NRF_NVMC_MODE_READONLY);
#endif
}
    4048:	4770      	bx	lr
    404a:	bf00      	nop
    404c:	50039000 	.word	0x50039000

00004050 <nvmc_word_write>:
    return (bool)(p_reg->READY & NVMC_READY_READY_Msk);
    4050:	4a04      	ldr	r2, [pc, #16]	; (4064 <nvmc_word_write+0x14>)
    4052:	f8d2 3400 	ldr.w	r3, [r2, #1024]	; 0x400
{
#if defined(NRF9160_XXAA)
    while (!nrf_nvmc_write_ready_check(NRF_NVMC))
    {}
#else
    while (!nrf_nvmc_ready_check(NRF_NVMC))
    4056:	07db      	lsls	r3, r3, #31
    4058:	d5fb      	bpl.n	4052 <nvmc_word_write+0x2>
    {}
#endif

    *(volatile uint32_t *)addr = value;
    405a:	6001      	str	r1, [r0, #0]
    405c:	f3bf 8f5f 	dmb	sy
    __DMB();
}
    4060:	4770      	bx	lr
    4062:	bf00      	nop
    4064:	50039000 	.word	0x50039000

00004068 <nrfx_nvmc_page_erase>:
        nvmc_word_write(addr + (NVMC_BYTES_IN_WORD * i), ((uint32_t const *)src)[i]);
    }
}

nrfx_err_t nrfx_nvmc_page_erase(uint32_t addr)
{
    4068:	b508      	push	{r3, lr}
    return !(addr % flash_page_size_get());
    406a:	f3c0 030b 	ubfx	r3, r0, #0, #12
    NRFX_ASSERT(is_valid_address(addr, false));

    if (!is_page_aligned_check(addr))
    406e:	b983      	cbnz	r3, 4092 <nrfx_nvmc_page_erase+0x2a>
    p_reg->CONFIGNS = (uint32_t)mode;
    4070:	2202      	movs	r2, #2
    4072:	4b09      	ldr	r3, [pc, #36]	; (4098 <nrfx_nvmc_page_erase+0x30>)
    4074:	f8c3 2584 	str.w	r2, [r3, #1412]	; 0x584
    p_reg->CONFIG = (uint32_t)mode;
    4078:	f8c3 2504 	str.w	r2, [r3, #1284]	; 0x504
        p_reg->ERASEPCR1 = page_addr;
    }
#elif defined(NRF52_SERIES)
    p_reg->ERASEPAGE = page_addr;
#elif defined(NRF9160_XXAA) || defined(NRF5340_XXAA_APPLICATION) || defined(NRF5340_XXAA_NETWORK)
    *(volatile uint32_t *)page_addr = 0xFFFFFFFF;
    407c:	f04f 32ff 	mov.w	r2, #4294967295
    4080:	6002      	str	r2, [r0, #0]
    return (bool)(p_reg->READY & NVMC_READY_READY_Msk);
    4082:	f8d3 2400 	ldr.w	r2, [r3, #1024]	; 0x400
        return NRFX_ERROR_INVALID_ADDR;
    }

    nvmc_erase_mode_set();
    nrf_nvmc_page_erase_start(NRF_NVMC, addr);
    while (!nrf_nvmc_ready_check(NRF_NVMC))
    4086:	07d2      	lsls	r2, r2, #31
    4088:	d5fb      	bpl.n	4082 <nrfx_nvmc_page_erase+0x1a>
    {}
    nvmc_readonly_mode_set();
    408a:	f7ff ffd7 	bl	403c <nvmc_readonly_mode_set>

    return NRFX_SUCCESS;
    408e:	4803      	ldr	r0, [pc, #12]	; (409c <nrfx_nvmc_page_erase+0x34>)
}
    4090:	bd08      	pop	{r3, pc}
        return NRFX_ERROR_INVALID_ADDR;
    4092:	4803      	ldr	r0, [pc, #12]	; (40a0 <nrfx_nvmc_page_erase+0x38>)
    4094:	e7fc      	b.n	4090 <nrfx_nvmc_page_erase+0x28>
    4096:	bf00      	nop
    4098:	50039000 	.word	0x50039000
    409c:	0bad0000 	.word	0x0bad0000
    40a0:	0bad000a 	.word	0x0bad000a

000040a4 <nrfx_nvmc_word_write>:
    p_reg->CONFIGNS = (uint32_t)mode;
    40a4:	2201      	movs	r2, #1

    nrfx_nvmc_word_write(aligned_addr, partial_word_create(addr, (const uint8_t *)&value, 2));
}

void nrfx_nvmc_word_write(uint32_t addr, uint32_t value)
{
    40a6:	b508      	push	{r3, lr}
    40a8:	4b05      	ldr	r3, [pc, #20]	; (40c0 <nrfx_nvmc_word_write+0x1c>)
    40aa:	f8c3 2584 	str.w	r2, [r3, #1412]	; 0x584
    p_reg->CONFIG = (uint32_t)mode;
    40ae:	f8c3 2504 	str.w	r2, [r3, #1284]	; 0x504
    NRFX_ASSERT(is_valid_address(addr, true));
    NRFX_ASSERT(nrfx_is_word_aligned((void const *)addr));

    nvmc_write_mode_set();

    nvmc_word_write(addr, value);
    40b2:	f7ff ffcd 	bl	4050 <nvmc_word_write>

    nvmc_readonly_mode_set();
}
    40b6:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    nvmc_readonly_mode_set();
    40ba:	f7ff bfbf 	b.w	403c <nvmc_readonly_mode_set>
    40be:	bf00      	nop
    40c0:	50039000 	.word	0x50039000

000040c4 <qspi_xfer>:

static nrfx_err_t qspi_xfer(void *            p_buffer,
                            size_t            length,
                            uint32_t          address,
                            nrfx_qspi_state_t desired_state)
{
    40c4:	b570      	push	{r4, r5, r6, lr}
    40c6:	f000 4460 	and.w	r4, r0, #3758096384	; 0xe0000000
    NRFX_ASSERT(m_cb.state != NRFX_QSPI_STATE_UNINITIALIZED);
    NRFX_ASSERT(p_buffer != NULL);

    if (!nrfx_is_in_ram(p_buffer) || !nrfx_is_word_aligned(p_buffer))
    40ca:	f1b4 5f00 	cmp.w	r4, #536870912	; 0x20000000
    40ce:	d168      	bne.n	41a2 <qspi_xfer+0xde>
    40d0:	0784      	lsls	r4, r0, #30
    40d2:	d166      	bne.n	41a2 <qspi_xfer+0xde>
    {
        return NRFX_ERROR_INVALID_ADDR;
    }

    if ((m_cb.state != NRFX_QSPI_STATE_IDLE) &&
    40d4:	4d35      	ldr	r5, [pc, #212]	; (41ac <qspi_xfer+0xe8>)
    40d6:	f895 4030 	ldrb.w	r4, [r5, #48]	; 0x30
    40da:	2c01      	cmp	r4, #1
    40dc:	d001      	beq.n	40e2 <qspi_xfer+0x1e>
    40de:	429c      	cmp	r4, r3
    40e0:	d161      	bne.n	41a6 <qspi_xfer+0xe2>
    {
        return NRFX_ERROR_BUSY;
    }

    bool is_first_buffer = false;
    if (m_cb.handler)
    40e2:	682c      	ldr	r4, [r5, #0]
    40e4:	bb04      	cbnz	r4, 4128 <qspi_xfer+0x64>
            is_first_buffer = true;
        }
    }

    nrf_qspi_task_t task;
    if (desired_state == NRFX_QSPI_STATE_WRITE)
    40e6:	2b02      	cmp	r3, #2
    40e8:	4b31      	ldr	r3, [pc, #196]	; (41b0 <qspi_xfer+0xec>)
NRF_STATIC_INLINE void nrf_qspi_write_buffer_set(NRF_QSPI_Type * p_reg,
                                                 void const    * p_buffer,
                                                 uint32_t        length,
                                                 uint32_t        dest_addr)
{
    p_reg->WRITE.DST = dest_addr;
    40ea:	bf0b      	itete	eq
    40ec:	f8c3 2510 	streq.w	r2, [r3, #1296]	; 0x510
NRF_STATIC_INLINE void nrf_qspi_read_buffer_set(NRF_QSPI_Type * p_reg,
                                                void          * p_buffer,
                                                uint32_t        length,
                                                uint32_t        src_addr)
{
    p_reg->READ.SRC = src_addr;
    40f0:	f8c3 2504 	strne.w	r2, [r3, #1284]	; 0x504
    p_reg->WRITE.SRC = (uint32_t) p_buffer;
    40f4:	f8c3 0514 	streq.w	r0, [r3, #1300]	; 0x514
    p_reg->READ.DST = (uint32_t) p_buffer;
    40f8:	f8c3 0508 	strne.w	r0, [r3, #1288]	; 0x508
    p_reg->WRITE.CNT = length;
    40fc:	bf0b      	itete	eq
    40fe:	f8c3 1518 	streq.w	r1, [r3, #1304]	; 0x518
    p_reg->READ.CNT = length;
    4102:	f8c3 150c 	strne.w	r1, [r3, #1292]	; 0x50c
    {
        nrf_qspi_write_buffer_set(NRF_QSPI, p_buffer, length, address);
        task = NRF_QSPI_TASK_WRITESTART;
    4106:	2208      	moveq	r2, #8
    }
    else
    {
        nrf_qspi_read_buffer_set(NRF_QSPI, p_buffer, length, address);
        task = NRF_QSPI_TASK_READSTART;
    4108:	2204      	movne	r2, #4
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    410a:	2100      	movs	r1, #0
    410c:	f8c3 1100 	str.w	r1, [r3, #256]	; 0x100
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    4110:	f102 43a0 	add.w	r3, r2, #1342177280	; 0x50000000
    4114:	2201      	movs	r2, #1
    4116:	f503 332c 	add.w	r3, r3, #176128	; 0x2b000
    411a:	601a      	str	r2, [r3, #0]
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    411c:	4a24      	ldr	r2, [pc, #144]	; (41b0 <qspi_xfer+0xec>)
    411e:	f8d2 3100 	ldr.w	r3, [r2, #256]	; 0x100

    if (!m_cb.handler)
    {
        nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY);
        nrf_qspi_task_trigger(NRF_QSPI, task);
        while (!nrf_qspi_event_check(NRF_QSPI, NRF_QSPI_EVENT_READY))
    4122:	2b00      	cmp	r3, #0
    4124:	d0fb      	beq.n	411e <qspi_xfer+0x5a>
    4126:	e00d      	b.n	4144 <qspi_xfer+0x80>
        if (m_cb.p_buffer_primary)
    4128:	68ae      	ldr	r6, [r5, #8]
    412a:	4c21      	ldr	r4, [pc, #132]	; (41b0 <qspi_xfer+0xec>)
    412c:	b166      	cbz	r6, 4148 <qspi_xfer+0x84>
    if (desired_state == NRFX_QSPI_STATE_WRITE)
    412e:	2b02      	cmp	r3, #2
            m_cb.p_buffer_secondary = p_buffer;
    4130:	60e8      	str	r0, [r5, #12]
            m_cb.size_secondary     = length;
    4132:	6169      	str	r1, [r5, #20]
            m_cb.addr_secondary     = address;
    4134:	61ea      	str	r2, [r5, #28]
    if (desired_state == NRFX_QSPI_STATE_WRITE)
    4136:	d12d      	bne.n	4194 <qspi_xfer+0xd0>
    p_reg->WRITE.DST = dest_addr;
    4138:	f8c4 2510 	str.w	r2, [r4, #1296]	; 0x510
    p_reg->WRITE.SRC = (uint32_t) p_buffer;
    413c:	f8c4 0514 	str.w	r0, [r4, #1300]	; 0x514
    p_reg->WRITE.CNT = length;
    4140:	f8c4 1518 	str.w	r1, [r4, #1304]	; 0x518
        nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY);
        nrf_qspi_int_enable(NRF_QSPI, NRF_QSPI_INT_READY_MASK);
        nrf_qspi_task_trigger(NRF_QSPI, task);
    }

    return NRFX_SUCCESS;
    4144:	481b      	ldr	r0, [pc, #108]	; (41b4 <qspi_xfer+0xf0>)
}
    4146:	bd70      	pop	{r4, r5, r6, pc}
    if (desired_state == NRFX_QSPI_STATE_WRITE)
    4148:	2b02      	cmp	r3, #2
            m_cb.state = desired_state;
    414a:	f885 3030 	strb.w	r3, [r5, #48]	; 0x30
            m_cb.size_primary     = length;
    414e:	6129      	str	r1, [r5, #16]
            m_cb.addr_primary     = address;
    4150:	61aa      	str	r2, [r5, #24]
            m_cb.p_buffer_primary = p_buffer;
    4152:	60a8      	str	r0, [r5, #8]
    p_reg->WRITE.DST = dest_addr;
    4154:	bf0c      	ite	eq
    4156:	f8c4 2510 	streq.w	r2, [r4, #1296]	; 0x510
    p_reg->READ.SRC = src_addr;
    415a:	f8c4 2504 	strne.w	r2, [r4, #1284]	; 0x504
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    415e:	f04f 0200 	mov.w	r2, #0
    p_reg->WRITE.SRC = (uint32_t) p_buffer;
    4162:	bf0b      	itete	eq
    4164:	f8c4 0514 	streq.w	r0, [r4, #1300]	; 0x514
    p_reg->READ.DST = (uint32_t) p_buffer;
    4168:	f8c4 0508 	strne.w	r0, [r4, #1288]	; 0x508
    p_reg->WRITE.CNT = length;
    416c:	f8c4 1518 	streq.w	r1, [r4, #1304]	; 0x518
    p_reg->READ.CNT = length;
    4170:	f8c4 150c 	strne.w	r1, [r4, #1292]	; 0x50c
        task = NRF_QSPI_TASK_WRITESTART;
    4174:	bf08      	it	eq
    4176:	2308      	moveq	r3, #8
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    4178:	490d      	ldr	r1, [pc, #52]	; (41b0 <qspi_xfer+0xec>)
        task = NRF_QSPI_TASK_READSTART;
    417a:	bf18      	it	ne
    417c:	2304      	movne	r3, #4
    417e:	f8c1 2100 	str.w	r2, [r1, #256]	; 0x100
    p_reg->INTENSET = mask;
    4182:	2201      	movs	r2, #1
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    4184:	f103 43a0 	add.w	r3, r3, #1342177280	; 0x50000000
    4188:	f503 332c 	add.w	r3, r3, #176128	; 0x2b000
    p_reg->INTENSET = mask;
    418c:	f8c1 2304 	str.w	r2, [r1, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    4190:	601a      	str	r2, [r3, #0]
}
    4192:	e7d7      	b.n	4144 <qspi_xfer+0x80>
    p_reg->READ.SRC = src_addr;
    4194:	f8c4 2504 	str.w	r2, [r4, #1284]	; 0x504
    p_reg->READ.DST = (uint32_t) p_buffer;
    4198:	f8c4 0508 	str.w	r0, [r4, #1288]	; 0x508
    p_reg->READ.CNT = length;
    419c:	f8c4 150c 	str.w	r1, [r4, #1292]	; 0x50c
    else if (is_first_buffer)
    41a0:	e7d0      	b.n	4144 <qspi_xfer+0x80>
        return NRFX_ERROR_INVALID_ADDR;
    41a2:	4805      	ldr	r0, [pc, #20]	; (41b8 <qspi_xfer+0xf4>)
    41a4:	e7cf      	b.n	4146 <qspi_xfer+0x82>
        return NRFX_ERROR_BUSY;
    41a6:	4805      	ldr	r0, [pc, #20]	; (41bc <qspi_xfer+0xf8>)
    41a8:	e7cd      	b.n	4146 <qspi_xfer+0x82>
    41aa:	bf00      	nop
    41ac:	200009cc 	.word	0x200009cc
    41b0:	5002b000 	.word	0x5002b000
    41b4:	0bad0000 	.word	0x0bad0000
    41b8:	0bad000a 	.word	0x0bad000a
    41bc:	0bad000b 	.word	0x0bad000b

000041c0 <qspi_ready_wait>:
        nrf_gpio_cfg_default(pins.io3_pin);
    }
}

static nrfx_err_t qspi_ready_wait(void)
{
    41c0:	b538      	push	{r3, r4, r5, lr}
    41c2:	2464      	movs	r4, #100	; 0x64
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    41c4:	4d06      	ldr	r5, [pc, #24]	; (41e0 <qspi_ready_wait+0x20>)
    41c6:	f8d5 3100 	ldr.w	r3, [r5, #256]	; 0x100
    bool result;
    NRFX_WAIT_FOR(nrf_qspi_event_check(NRF_QSPI, NRF_QSPI_EVENT_READY),
    41ca:	b933      	cbnz	r3, 41da <qspi_ready_wait+0x1a>
    41cc:	200a      	movs	r0, #10
    41ce:	f002 fb28 	bl	6822 <nrfx_busy_wait>
    41d2:	3c01      	subs	r4, #1
    41d4:	d1f7      	bne.n	41c6 <qspi_ready_wait+0x6>
                                       QSPI_DEF_WAIT_ATTEMPTS,
                                       QSPI_DEF_WAIT_TIME_US,
                                       result);
    if (!result)
    {
        return NRFX_ERROR_TIMEOUT;
    41d6:	4803      	ldr	r0, [pc, #12]	; (41e4 <qspi_ready_wait+0x24>)
    }

    return NRFX_SUCCESS;
}
    41d8:	bd38      	pop	{r3, r4, r5, pc}
    return NRFX_SUCCESS;
    41da:	4803      	ldr	r0, [pc, #12]	; (41e8 <qspi_ready_wait+0x28>)
    41dc:	e7fc      	b.n	41d8 <qspi_ready_wait+0x18>
    41de:	bf00      	nop
    41e0:	5002b000 	.word	0x5002b000
    41e4:	0bad0007 	.word	0x0bad0007
    41e8:	0bad0000 	.word	0x0bad0000

000041ec <qspi_event_xfer_handle.constprop.0>:
}
#endif

static void qspi_event_xfer_handle(nrfx_qspi_evt_ext_xfer_t * p_xfer)
{
    p_xfer->p_buffer = (uint8_t *)m_cb.p_buffer_primary;
    41ec:	4b08      	ldr	r3, [pc, #32]	; (4210 <qspi_event_xfer_handle.constprop.0+0x24>)
    41ee:	689a      	ldr	r2, [r3, #8]
    41f0:	625a      	str	r2, [r3, #36]	; 0x24
    p_xfer->size     = m_cb.size_primary;
    41f2:	691a      	ldr	r2, [r3, #16]
    41f4:	629a      	str	r2, [r3, #40]	; 0x28
    p_xfer->addr     = m_cb.addr_primary;
    41f6:	699a      	ldr	r2, [r3, #24]
    41f8:	62da      	str	r2, [r3, #44]	; 0x2c
    if (m_cb.p_buffer_secondary)
    41fa:	68da      	ldr	r2, [r3, #12]
    {
        m_cb.p_buffer_primary = m_cb.p_buffer_secondary;
    41fc:	609a      	str	r2, [r3, #8]
    if (m_cb.p_buffer_secondary)
    41fe:	b132      	cbz	r2, 420e <qspi_event_xfer_handle.constprop.0+0x22>
        m_cb.size_primary     = m_cb.size_secondary;
    4200:	695a      	ldr	r2, [r3, #20]
    4202:	611a      	str	r2, [r3, #16]
        m_cb.addr_primary     = m_cb.addr_secondary;
    4204:	69da      	ldr	r2, [r3, #28]
    4206:	619a      	str	r2, [r3, #24]

        m_cb.p_buffer_secondary = NULL;
    4208:	2200      	movs	r2, #0
    420a:	60da      	str	r2, [r3, #12]
    420c:	4770      	bx	lr
    }
    else
    {
        m_cb.p_buffer_primary = NULL;
    }
}
    420e:	4770      	bx	lr
    4210:	200009cc 	.word	0x200009cc

00004214 <nrf_gpio_cfg.constprop.0>:
NRF_STATIC_INLINE void nrf_gpio_cfg(
    4214:	b510      	push	{r4, lr}
        case 0: return NRF_P0;
    4216:	4a0a      	ldr	r2, [pc, #40]	; (4240 <nrf_gpio_cfg.constprop.0+0x2c>)
    4218:	4c0a      	ldr	r4, [pc, #40]	; (4244 <nrf_gpio_cfg.constprop.0+0x30>)
    *p_pin = pin_number & 0x1F;
    421a:	f000 031f 	and.w	r3, r0, #31
    return pin_number >> 5;
    421e:	0940      	lsrs	r0, r0, #5
        case 0: return NRF_P0;
    4220:	2801      	cmp	r0, #1
    4222:	bf18      	it	ne
    4224:	4622      	movne	r2, r4
    uint32_t cnf = reg->PIN_CNF[pin_number] & GPIO_PIN_CNF_MCUSEL_Msk;
    4226:	eb02 0283 	add.w	r2, r2, r3, lsl #2
    422a:	f8d2 3200 	ldr.w	r3, [r2, #512]	; 0x200
    422e:	f003 43e0 	and.w	r3, r3, #1879048192	; 0x70000000
    4232:	ea43 2301 	orr.w	r3, r3, r1, lsl #8
    cnf |= ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)     |
    4236:	f043 0302 	orr.w	r3, r3, #2
    reg->PIN_CNF[pin_number] = cnf;
    423a:	f8c2 3200 	str.w	r3, [r2, #512]	; 0x200
}
    423e:	bd10      	pop	{r4, pc}
    4240:	50842800 	.word	0x50842800
    4244:	50842500 	.word	0x50842500

00004248 <nrf_qspi_cinstrdata_get.constprop.0>:
        default:
            break;
    }
}

NRF_STATIC_INLINE void nrf_qspi_cinstrdata_get(NRF_QSPI_Type const * p_reg,
    4248:	b510      	push	{r4, lr}
                                               nrf_qspi_cinstr_len_t length,
                                               void *                p_rx_data)
{
    uint8_t *p_rx_data_8 = (uint8_t *) p_rx_data;

    uint32_t reg1 = p_reg->CINSTRDAT1;
    424a:	4b0e      	ldr	r3, [pc, #56]	; (4284 <nrf_qspi_cinstrdata_get.constprop.0+0x3c>)
    uint32_t reg0 = p_reg->CINSTRDAT0;
    switch (length)
    424c:	3802      	subs	r0, #2
    uint32_t reg1 = p_reg->CINSTRDAT1;
    424e:	f8d3 263c 	ldr.w	r2, [r3, #1596]	; 0x63c
    uint32_t reg0 = p_reg->CINSTRDAT0;
    4252:	f8d3 3638 	ldr.w	r3, [r3, #1592]	; 0x638
    switch (length)
    4256:	2807      	cmp	r0, #7
    4258:	d813      	bhi.n	4282 <nrf_qspi_cinstrdata_get.constprop.0+0x3a>
    425a:	e8df f000 	tbb	[pc, r0]
    425e:	0f11      	.short	0x0f11
    4260:	080a0b0d 	.word	0x080a0b0d
    4264:	0406      	.short	0x0406
    {
        case NRF_QSPI_CINSTR_LEN_9B:
            p_rx_data_8[7] = (uint8_t)(reg1 >> QSPI_CINSTRDAT1_BYTE7_Pos);
    4266:	0e10      	lsrs	r0, r2, #24
    4268:	71c8      	strb	r0, [r1, #7]
            /* FALLTHROUGH */
        case NRF_QSPI_CINSTR_LEN_8B:
            p_rx_data_8[6] = (uint8_t)(reg1 >> QSPI_CINSTRDAT1_BYTE6_Pos);
    426a:	0c10      	lsrs	r0, r2, #16
    426c:	7188      	strb	r0, [r1, #6]
            /* FALLTHROUGH */
        case NRF_QSPI_CINSTR_LEN_7B:
            p_rx_data_8[5] = (uint8_t)(reg1 >> QSPI_CINSTRDAT1_BYTE5_Pos);
    426e:	0a10      	lsrs	r0, r2, #8
    4270:	7148      	strb	r0, [r1, #5]
            /* FALLTHROUGH */
        case NRF_QSPI_CINSTR_LEN_6B:
            p_rx_data_8[4] = (uint8_t)(reg1);
    4272:	710a      	strb	r2, [r1, #4]
            /* FALLTHROUGH */
        case NRF_QSPI_CINSTR_LEN_5B:
            p_rx_data_8[3] = (uint8_t)(reg0 >> QSPI_CINSTRDAT0_BYTE3_Pos);
    4274:	0e1a      	lsrs	r2, r3, #24
    4276:	70ca      	strb	r2, [r1, #3]
            /* FALLTHROUGH */
        case NRF_QSPI_CINSTR_LEN_4B:
            p_rx_data_8[2] = (uint8_t)(reg0 >> QSPI_CINSTRDAT0_BYTE2_Pos);
    4278:	0c1a      	lsrs	r2, r3, #16
    427a:	708a      	strb	r2, [r1, #2]
            /* FALLTHROUGH */
        case NRF_QSPI_CINSTR_LEN_3B:
            p_rx_data_8[1] = (uint8_t)(reg0 >> QSPI_CINSTRDAT0_BYTE1_Pos);
    427c:	0a1a      	lsrs	r2, r3, #8
    427e:	704a      	strb	r2, [r1, #1]
            /* FALLTHROUGH */
        case NRF_QSPI_CINSTR_LEN_2B:
            p_rx_data_8[0] = (uint8_t)(reg0);
    4280:	700b      	strb	r3, [r1, #0]
            /* Send only opcode. Case to avoid compiler warnings. */
            break;
        default:
            break;
    }
}
    4282:	bd10      	pop	{r4, pc}
    4284:	5002b000 	.word	0x5002b000

00004288 <nrf_qspi_cinstrdata_set.constprop.0>:
    switch (length)
    4288:	3802      	subs	r0, #2
    428a:	2807      	cmp	r0, #7
    428c:	d81f      	bhi.n	42ce <nrf_qspi_cinstrdata_set.constprop.0+0x46>
    428e:	e8df f000 	tbb	[pc, r0]
    4292:	2729      	.short	0x2729
    4294:	21231125 	.word	0x21231125
    4298:	041f      	.short	0x041f
            reg |= ((uint32_t)p_tx_data_8[7]) << QSPI_CINSTRDAT1_BYTE7_Pos;
    429a:	79cb      	ldrb	r3, [r1, #7]
    429c:	061b      	lsls	r3, r3, #24
            reg |= ((uint32_t)p_tx_data_8[6]) << QSPI_CINSTRDAT1_BYTE6_Pos;
    429e:	798a      	ldrb	r2, [r1, #6]
    42a0:	ea43 4302 	orr.w	r3, r3, r2, lsl #16
            reg |= ((uint32_t)p_tx_data_8[5]) << QSPI_CINSTRDAT1_BYTE5_Pos;
    42a4:	794a      	ldrb	r2, [r1, #5]
    42a6:	ea43 2302 	orr.w	r3, r3, r2, lsl #8
            reg |= ((uint32_t)p_tx_data_8[4]);
    42aa:	790a      	ldrb	r2, [r1, #4]
    42ac:	4313      	orrs	r3, r2
            p_reg->CINSTRDAT1 = reg;
    42ae:	4a0e      	ldr	r2, [pc, #56]	; (42e8 <nrf_qspi_cinstrdata_set.constprop.0+0x60>)
    42b0:	f8c2 363c 	str.w	r3, [r2, #1596]	; 0x63c
            reg |= ((uint32_t)p_tx_data_8[3]) << QSPI_CINSTRDAT0_BYTE3_Pos;
    42b4:	78cb      	ldrb	r3, [r1, #3]
    42b6:	061b      	lsls	r3, r3, #24
            reg |= ((uint32_t)p_tx_data_8[2]) << QSPI_CINSTRDAT0_BYTE2_Pos;
    42b8:	788a      	ldrb	r2, [r1, #2]
    42ba:	ea43 4302 	orr.w	r3, r3, r2, lsl #16
            reg |= ((uint32_t)p_tx_data_8[1]) << QSPI_CINSTRDAT0_BYTE1_Pos;
    42be:	784a      	ldrb	r2, [r1, #1]
    42c0:	ea43 2302 	orr.w	r3, r3, r2, lsl #8
            reg |= ((uint32_t)p_tx_data_8[0]);
    42c4:	780a      	ldrb	r2, [r1, #0]
    42c6:	4313      	orrs	r3, r2
            p_reg->CINSTRDAT0 = reg;
    42c8:	4a07      	ldr	r2, [pc, #28]	; (42e8 <nrf_qspi_cinstrdata_set.constprop.0+0x60>)
    42ca:	f8c2 3638 	str.w	r3, [r2, #1592]	; 0x638
}
    42ce:	4770      	bx	lr
    switch (length)
    42d0:	2300      	movs	r3, #0
    42d2:	e7e4      	b.n	429e <nrf_qspi_cinstrdata_set.constprop.0+0x16>
    42d4:	2300      	movs	r3, #0
    42d6:	e7e5      	b.n	42a4 <nrf_qspi_cinstrdata_set.constprop.0+0x1c>
    42d8:	2300      	movs	r3, #0
    42da:	e7e6      	b.n	42aa <nrf_qspi_cinstrdata_set.constprop.0+0x22>
    42dc:	2300      	movs	r3, #0
    42de:	e7eb      	b.n	42b8 <nrf_qspi_cinstrdata_set.constprop.0+0x30>
    42e0:	2300      	movs	r3, #0
    42e2:	e7ec      	b.n	42be <nrf_qspi_cinstrdata_set.constprop.0+0x36>
    42e4:	2300      	movs	r3, #0
    42e6:	e7ed      	b.n	42c4 <nrf_qspi_cinstrdata_set.constprop.0+0x3c>
    42e8:	5002b000 	.word	0x5002b000

000042ec <nrfx_qspi_init>:
{
    42ec:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    if (m_cb.state != NRFX_QSPI_STATE_UNINITIALIZED)
    42ee:	4f67      	ldr	r7, [pc, #412]	; (448c <nrfx_qspi_init+0x1a0>)
{
    42f0:	4604      	mov	r4, r0
    if (m_cb.state != NRFX_QSPI_STATE_UNINITIALIZED)
    42f2:	f897 3030 	ldrb.w	r3, [r7, #48]	; 0x30
{
    42f6:	460d      	mov	r5, r1
    42f8:	4616      	mov	r6, r2
    if (m_cb.state != NRFX_QSPI_STATE_UNINITIALIZED)
    42fa:	2b00      	cmp	r3, #0
    42fc:	f040 80c2 	bne.w	4484 <nrfx_qspi_init+0x198>
    if (p_config->skip_gpio_cfg && p_config->skip_psel_cfg)
    4300:	7cc2      	ldrb	r2, [r0, #19]
    4302:	b112      	cbz	r2, 430a <nrfx_qspi_init+0x1e>
    4304:	7d03      	ldrb	r3, [r0, #20]
    4306:	2b00      	cmp	r3, #0
    4308:	d16c      	bne.n	43e4 <nrfx_qspi_init+0xf8>
    if ((p_config->pins.sck_pin == NRF_QSPI_PIN_NOT_CONNECTED) ||
    430a:	7920      	ldrb	r0, [r4, #4]
    430c:	28ff      	cmp	r0, #255	; 0xff
    430e:	f000 80bb 	beq.w	4488 <nrfx_qspi_init+0x19c>
    4312:	7963      	ldrb	r3, [r4, #5]
    4314:	2bff      	cmp	r3, #255	; 0xff
    4316:	f000 80b7 	beq.w	4488 <nrfx_qspi_init+0x19c>
        (p_config->pins.csn_pin == NRF_QSPI_PIN_NOT_CONNECTED) ||
    431a:	79a3      	ldrb	r3, [r4, #6]
    431c:	2bff      	cmp	r3, #255	; 0xff
    431e:	f000 80b3 	beq.w	4488 <nrfx_qspi_init+0x19c>
        (p_config->pins.io1_pin == NRF_QSPI_PIN_NOT_CONNECTED))
    4322:	79e1      	ldrb	r1, [r4, #7]
        (p_config->pins.io0_pin == NRF_QSPI_PIN_NOT_CONNECTED) ||
    4324:	29ff      	cmp	r1, #255	; 0xff
    4326:	f000 80af 	beq.w	4488 <nrfx_qspi_init+0x19c>
        (p_config->pins.csn_pin != QSPI_CSN_DEDICATED) ||
    432a:	6863      	ldr	r3, [r4, #4]
    if ((p_config->pins.sck_pin != QSPI_SCK_DEDICATED) ||
    432c:	f8df c160 	ldr.w	ip, [pc, #352]	; 4490 <nrfx_qspi_init+0x1a4>
        (p_config->pins.csn_pin != QSPI_CSN_DEDICATED) ||
    4330:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
    if ((p_config->pins.sck_pin != QSPI_SCK_DEDICATED) ||
    4334:	4563      	cmp	r3, ip
    4336:	f040 80a7 	bne.w	4488 <nrfx_qspi_init+0x19c>
        (p_config->pins.io0_pin != QSPI_IO0_DEDICATED) ||
    433a:	290e      	cmp	r1, #14
    433c:	f040 80a4 	bne.w	4488 <nrfx_qspi_init+0x19c>
        (p_config->pins.io2_pin != NRF_QSPI_PIN_NOT_CONNECTED &&
    4340:	7a23      	ldrb	r3, [r4, #8]
        (p_config->pins.io1_pin != QSPI_IO1_DEDICATED) ||
    4342:	2bff      	cmp	r3, #255	; 0xff
    4344:	d002      	beq.n	434c <nrfx_qspi_init+0x60>
        (p_config->pins.io2_pin != NRF_QSPI_PIN_NOT_CONNECTED &&
    4346:	2b0f      	cmp	r3, #15
    4348:	f040 809e 	bne.w	4488 <nrfx_qspi_init+0x19c>
        (p_config->pins.io3_pin != NRF_QSPI_PIN_NOT_CONNECTED &&
    434c:	7a63      	ldrb	r3, [r4, #9]
         p_config->pins.io2_pin != QSPI_IO2_DEDICATED) ||
    434e:	2bff      	cmp	r3, #255	; 0xff
    4350:	d002      	beq.n	4358 <nrfx_qspi_init+0x6c>
        (p_config->pins.io3_pin != NRF_QSPI_PIN_NOT_CONNECTED &&
    4352:	2b10      	cmp	r3, #16
    4354:	f040 8098 	bne.w	4488 <nrfx_qspi_init+0x19c>
    if (!p_config->skip_gpio_cfg)
    4358:	b9b2      	cbnz	r2, 4388 <nrfx_qspi_init+0x9c>
        QSPI_PIN_INIT(p_config->pins.sck_pin);
    435a:	2103      	movs	r1, #3
    435c:	f7ff ff5a 	bl	4214 <nrf_gpio_cfg.constprop.0>
        QSPI_PIN_INIT(p_config->pins.csn_pin);
    4360:	7960      	ldrb	r0, [r4, #5]
    4362:	f7ff ff57 	bl	4214 <nrf_gpio_cfg.constprop.0>
        QSPI_PIN_INIT(p_config->pins.io0_pin);
    4366:	79a0      	ldrb	r0, [r4, #6]
    4368:	f7ff ff54 	bl	4214 <nrf_gpio_cfg.constprop.0>
        QSPI_PIN_INIT(p_config->pins.io1_pin);
    436c:	79e0      	ldrb	r0, [r4, #7]
    436e:	f7ff ff51 	bl	4214 <nrf_gpio_cfg.constprop.0>
        if (p_config->pins.io2_pin != NRF_QSPI_PIN_NOT_CONNECTED)
    4372:	7a20      	ldrb	r0, [r4, #8]
    4374:	28ff      	cmp	r0, #255	; 0xff
    4376:	d001      	beq.n	437c <nrfx_qspi_init+0x90>
            QSPI_PIN_INIT(p_config->pins.io2_pin);
    4378:	f7ff ff4c 	bl	4214 <nrf_gpio_cfg.constprop.0>
        if (p_config->pins.io3_pin != NRF_QSPI_PIN_NOT_CONNECTED)
    437c:	7a60      	ldrb	r0, [r4, #9]
    437e:	28ff      	cmp	r0, #255	; 0xff
    4380:	d002      	beq.n	4388 <nrfx_qspi_init+0x9c>
            QSPI_PIN_INIT(p_config->pins.io3_pin);
    4382:	2103      	movs	r1, #3
    4384:	f7ff ff46 	bl	4214 <nrf_gpio_cfg.constprop.0>
    if (!p_config->skip_psel_cfg)
    4388:	7d23      	ldrb	r3, [r4, #20]
    438a:	bb5b      	cbnz	r3, 43e4 <nrfx_qspi_init+0xf8>
    p_reg->PSEL.SCK = NRF_QSPI_PIN_VAL(p_pins->sck_pin);
    438c:	7923      	ldrb	r3, [r4, #4]
    438e:	2bff      	cmp	r3, #255	; 0xff
    4390:	bf14      	ite	ne
    4392:	461a      	movne	r2, r3
    4394:	f04f 32ff 	moveq.w	r2, #4294967295
    4398:	4b3e      	ldr	r3, [pc, #248]	; (4494 <nrfx_qspi_init+0x1a8>)
    439a:	f8c3 2524 	str.w	r2, [r3, #1316]	; 0x524
    p_reg->PSEL.CSN = NRF_QSPI_PIN_VAL(p_pins->csn_pin);
    439e:	7962      	ldrb	r2, [r4, #5]
    43a0:	2aff      	cmp	r2, #255	; 0xff
    43a2:	bf08      	it	eq
    43a4:	f04f 32ff 	moveq.w	r2, #4294967295
    43a8:	f8c3 2528 	str.w	r2, [r3, #1320]	; 0x528
    p_reg->PSEL.IO0 = NRF_QSPI_PIN_VAL(p_pins->io0_pin);
    43ac:	79a2      	ldrb	r2, [r4, #6]
    43ae:	2aff      	cmp	r2, #255	; 0xff
    43b0:	bf08      	it	eq
    43b2:	f04f 32ff 	moveq.w	r2, #4294967295
    43b6:	f8c3 2530 	str.w	r2, [r3, #1328]	; 0x530
    p_reg->PSEL.IO1 = NRF_QSPI_PIN_VAL(p_pins->io1_pin);
    43ba:	79e2      	ldrb	r2, [r4, #7]
    43bc:	2aff      	cmp	r2, #255	; 0xff
    43be:	bf08      	it	eq
    43c0:	f04f 32ff 	moveq.w	r2, #4294967295
    43c4:	f8c3 2534 	str.w	r2, [r3, #1332]	; 0x534
    p_reg->PSEL.IO2 = NRF_QSPI_PIN_VAL(p_pins->io2_pin);
    43c8:	7a22      	ldrb	r2, [r4, #8]
    43ca:	2aff      	cmp	r2, #255	; 0xff
    43cc:	bf08      	it	eq
    43ce:	f04f 32ff 	moveq.w	r2, #4294967295
    43d2:	f8c3 2538 	str.w	r2, [r3, #1336]	; 0x538
    p_reg->PSEL.IO3 = NRF_QSPI_PIN_VAL(p_pins->io3_pin);
    43d6:	7a62      	ldrb	r2, [r4, #9]
    43d8:	2aff      	cmp	r2, #255	; 0xff
    43da:	bf08      	it	eq
    43dc:	f04f 32ff 	moveq.w	r2, #4294967295
    43e0:	f8c3 253c 	str.w	r2, [r3, #1340]	; 0x53c
    nrf_qspi_xip_offset_set(NRF_QSPI, p_config->xip_offset);
    43e4:	6823      	ldr	r3, [r4, #0]
    p_reg->XIPOFFSET = xip_offset;
    43e6:	4a2b      	ldr	r2, [pc, #172]	; (4494 <nrfx_qspi_init+0x1a8>)
    43e8:	f8c2 3540 	str.w	r3, [r2, #1344]	; 0x540
    config |= ((uint32_t)p_config->addrmode)   << QSPI_IFCONFIG0_ADDRMODE_Pos;
    43ec:	7b23      	ldrb	r3, [r4, #12]
    config |= ((uint32_t)p_config->writeoc)    << QSPI_IFCONFIG0_WRITEOC_Pos;
    43ee:	7ae0      	ldrb	r0, [r4, #11]
    uint32_t config = p_config->readoc;
    43f0:	7aa1      	ldrb	r1, [r4, #10]
    config |= ((uint32_t)p_config->addrmode)   << QSPI_IFCONFIG0_ADDRMODE_Pos;
    43f2:	019b      	lsls	r3, r3, #6
    43f4:	ea43 03c0 	orr.w	r3, r3, r0, lsl #3
    43f8:	430b      	orrs	r3, r1
    config |= (p_config->dpmconfig ? 1U : 0U ) << QSPI_IFCONFIG0_DPMENABLE_Pos;
    43fa:	7b61      	ldrb	r1, [r4, #13]
    43fc:	ea43 13c1 	orr.w	r3, r3, r1, lsl #7
    p_reg->IFCONFIG0 = config;
    4400:	f8c2 3544 	str.w	r3, [r2, #1348]	; 0x544
    if (p_config->phy_if.sck_freq == NRF_QSPI_FREQ_DIV1)
    4404:	7c61      	ldrb	r1, [r4, #17]
    return p_reg->IFCONFIG0;
    4406:	f8d2 3544 	ldr.w	r3, [r2, #1348]	; 0x544
    440a:	bbb1      	cbnz	r1, 447a <nrfx_qspi_init+0x18e>
        regval |= ((1 << 16) | (1 << 17));
    440c:	f443 3340 	orr.w	r3, r3, #196608	; 0x30000
    p_reg->IFCONFIG0 = regval;
    4410:	f8c2 3544 	str.w	r3, [r2, #1348]	; 0x544
}
#endif

NRF_STATIC_INLINE void nrf_qspi_iftiming_set(NRF_QSPI_Type * p_reg, uint8_t rxdelay)
{
    p_reg->IFTIMING = ((uint32_t)rxdelay << QSPI_IFTIMING_RXDELAY_Pos) & QSPI_IFTIMING_RXDELAY_Msk;
    4414:	f44f 63c0 	mov.w	r3, #1536	; 0x600
    4418:	f8c2 3640 	str.w	r3, [r2, #1600]	; 0x640
    uint32_t config = p_reg->IFCONFIG1 & 0x00FFFF00;
    441c:	f8d2 1600 	ldr.w	r1, [r2, #1536]	; 0x600
    config |= p_config->sck_delay;
    4420:	7ba3      	ldrb	r3, [r4, #14]
    uint32_t config = p_reg->IFCONFIG1 & 0x00FFFF00;
    4422:	f021 417f 	bic.w	r1, r1, #4278190080	; 0xff000000
    4426:	f021 01ff 	bic.w	r1, r1, #255	; 0xff
    config |= p_config->sck_delay;
    442a:	430b      	orrs	r3, r1
    config |= (p_config->dpmen ? 1U : 0U)      << QSPI_IFCONFIG1_DPMEN_Pos;
    442c:	7be1      	ldrb	r1, [r4, #15]
    442e:	ea43 6301 	orr.w	r3, r3, r1, lsl #24
    config |= ((uint32_t)(p_config->spi_mode)) << QSPI_IFCONFIG1_SPIMODE_Pos;
    4432:	7c21      	ldrb	r1, [r4, #16]
    4434:	ea43 6341 	orr.w	r3, r3, r1, lsl #25
    config |= ((uint32_t)(p_config->sck_freq)) << QSPI_IFCONFIG1_SCKFREQ_Pos;
    4438:	7c61      	ldrb	r1, [r4, #17]
    443a:	ea43 7301 	orr.w	r3, r3, r1, lsl #28
    p_reg->IFCONFIG1 = config;
    443e:	f8c2 3600 	str.w	r3, [r2, #1536]	; 0x600
    m_cb.skip_gpio_cfg = p_config->skip_gpio_cfg;
    4442:	7ce3      	ldrb	r3, [r4, #19]
    m_cb.p_context = p_context;
    4444:	e9c7 5600 	strd	r5, r6, [r7]
    m_cb.skip_gpio_cfg = p_config->skip_gpio_cfg;
    4448:	f887 3031 	strb.w	r3, [r7, #49]	; 0x31
    p_reg->INTENCLR = mask;
    444c:	2301      	movs	r3, #1
    444e:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
    if (handler)
    4452:	b115      	cbz	r5, 445a <nrfx_qspi_init+0x16e>
        NRFX_IRQ_ENABLE(QSPI_IRQn);
    4454:	202b      	movs	r0, #43	; 0x2b
    4456:	f7fd f895 	bl	1584 <arch_irq_enable>
    m_cb.p_buffer_primary = NULL;
    445a:	2100      	movs	r1, #0
    m_cb.state = NRFX_QSPI_STATE_IDLE;
    445c:	2201      	movs	r2, #1
    m_cb.p_buffer_secondary = NULL;
    445e:	e9c7 1102 	strd	r1, r1, [r7, #8]
    p_reg->ENABLE = (QSPI_ENABLE_ENABLE_Enabled << QSPI_ENABLE_ENABLE_Pos);
    4462:	4b0c      	ldr	r3, [pc, #48]	; (4494 <nrfx_qspi_init+0x1a8>)
    m_cb.state = NRFX_QSPI_STATE_IDLE;
    4464:	f887 2030 	strb.w	r2, [r7, #48]	; 0x30
    4468:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    446c:	f8c3 1100 	str.w	r1, [r3, #256]	; 0x100
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    4470:	601a      	str	r2, [r3, #0]
}
    4472:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
    return qspi_ready_wait();
    4476:	f7ff bea3 	b.w	41c0 <qspi_ready_wait>
        regval &= ~(1 << 17);
    447a:	f423 3300 	bic.w	r3, r3, #131072	; 0x20000
        regval |=  (1 << 16);
    447e:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
    4482:	e7c5      	b.n	4410 <nrfx_qspi_init+0x124>
        return NRFX_ERROR_INVALID_STATE;
    4484:	4804      	ldr	r0, [pc, #16]	; (4498 <nrfx_qspi_init+0x1ac>)
}
    4486:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
        return NRFX_ERROR_INVALID_PARAM;
    4488:	4804      	ldr	r0, [pc, #16]	; (449c <nrfx_qspi_init+0x1b0>)
    448a:	e7fc      	b.n	4486 <nrfx_qspi_init+0x19a>
    448c:	200009cc 	.word	0x200009cc
    4490:	000d1211 	.word	0x000d1211
    4494:	5002b000 	.word	0x5002b000
    4498:	0bad0005 	.word	0x0bad0005
    449c:	0bad0004 	.word	0x0bad0004

000044a0 <nrfx_qspi_cinstr_xfer>:
{
    44a0:	b570      	push	{r4, r5, r6, lr}
    44a2:	4614      	mov	r4, r2
    if (m_cb.state != NRFX_QSPI_STATE_IDLE)
    44a4:	4a19      	ldr	r2, [pc, #100]	; (450c <nrfx_qspi_cinstr_xfer+0x6c>)
{
    44a6:	4605      	mov	r5, r0
    if (m_cb.state != NRFX_QSPI_STATE_IDLE)
    44a8:	f892 2030 	ldrb.w	r2, [r2, #48]	; 0x30
    44ac:	2a01      	cmp	r2, #1
    44ae:	d12b      	bne.n	4508 <nrfx_qspi_cinstr_xfer+0x68>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    44b0:	2200      	movs	r2, #0
    44b2:	4e17      	ldr	r6, [pc, #92]	; (4510 <nrfx_qspi_cinstr_xfer+0x70>)
    44b4:	f8c6 2100 	str.w	r2, [r6, #256]	; 0x100
    if (p_tx_buffer)
    44b8:	b111      	cbz	r1, 44c0 <nrfx_qspi_cinstr_xfer+0x20>
        nrf_qspi_cinstrdata_set(NRF_QSPI, p_config->length, p_tx_buffer);
    44ba:	7840      	ldrb	r0, [r0, #1]
    44bc:	f7ff fee4 	bl	4288 <nrf_qspi_cinstrdata_set.constprop.0>
    p_reg->INTENCLR = mask;
    44c0:	2301      	movs	r3, #1
    44c2:	f8c6 3308 	str.w	r3, [r6, #776]	; 0x308
                         ((uint32_t)p_config->io2_level << QSPI_CINSTRCONF_LIO2_Pos) |
    44c6:	78ab      	ldrb	r3, [r5, #2]
                         ((uint32_t)p_config->length    << QSPI_CINSTRCONF_LENGTH_Pos) |
    44c8:	786a      	ldrb	r2, [r5, #1]
                         ((uint32_t)p_config->io2_level << QSPI_CINSTRCONF_LIO2_Pos) |
    44ca:	031b      	lsls	r3, r3, #12
                         ((uint32_t)p_config->length    << QSPI_CINSTRCONF_LENGTH_Pos) |
    44cc:	ea43 2302 	orr.w	r3, r3, r2, lsl #8
    p_reg->CINSTRCONF = (((uint32_t)p_config->opcode    << QSPI_CINSTRCONF_OPCODE_Pos) |
    44d0:	782a      	ldrb	r2, [r5, #0]
                         ((uint32_t)p_config->length    << QSPI_CINSTRCONF_LENGTH_Pos) |
    44d2:	4313      	orrs	r3, r2
                         ((uint32_t)p_config->io3_level << QSPI_CINSTRCONF_LIO3_Pos) |
    44d4:	78ea      	ldrb	r2, [r5, #3]
                         ((uint32_t)p_config->io2_level << QSPI_CINSTRCONF_LIO2_Pos) |
    44d6:	ea43 3342 	orr.w	r3, r3, r2, lsl #13
                         ((uint32_t)p_config->wipwait   << QSPI_CINSTRCONF_WIPWAIT_Pos) |
    44da:	792a      	ldrb	r2, [r5, #4]
                         ((uint32_t)p_config->io3_level << QSPI_CINSTRCONF_LIO3_Pos) |
    44dc:	ea43 3382 	orr.w	r3, r3, r2, lsl #14
                         ((uint32_t)p_config->wren      << QSPI_CINSTRCONF_WREN_Pos));
    44e0:	796a      	ldrb	r2, [r5, #5]
                         ((uint32_t)p_config->wipwait   << QSPI_CINSTRCONF_WIPWAIT_Pos) |
    44e2:	ea43 33c2 	orr.w	r3, r3, r2, lsl #15
    p_reg->CINSTRCONF = (((uint32_t)p_config->opcode    << QSPI_CINSTRCONF_OPCODE_Pos) |
    44e6:	f8c6 3634 	str.w	r3, [r6, #1588]	; 0x634
    if (qspi_ready_wait() == NRFX_ERROR_TIMEOUT)
    44ea:	f7ff fe69 	bl	41c0 <qspi_ready_wait>
    44ee:	4b09      	ldr	r3, [pc, #36]	; (4514 <nrfx_qspi_cinstr_xfer+0x74>)
    44f0:	4298      	cmp	r0, r3
    44f2:	d008      	beq.n	4506 <nrfx_qspi_cinstr_xfer+0x66>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    44f4:	2300      	movs	r3, #0
    44f6:	f8c6 3100 	str.w	r3, [r6, #256]	; 0x100
    if (p_rx_buffer)
    44fa:	b11c      	cbz	r4, 4504 <nrfx_qspi_cinstr_xfer+0x64>
        nrf_qspi_cinstrdata_get(NRF_QSPI, p_config->length, p_rx_buffer);
    44fc:	4621      	mov	r1, r4
    44fe:	7868      	ldrb	r0, [r5, #1]
    4500:	f7ff fea2 	bl	4248 <nrf_qspi_cinstrdata_get.constprop.0>
        return NRFX_ERROR_BUSY;
    4504:	4804      	ldr	r0, [pc, #16]	; (4518 <nrfx_qspi_cinstr_xfer+0x78>)
}
    4506:	bd70      	pop	{r4, r5, r6, pc}
        return NRFX_ERROR_BUSY;
    4508:	4804      	ldr	r0, [pc, #16]	; (451c <nrfx_qspi_cinstr_xfer+0x7c>)
    450a:	e7fc      	b.n	4506 <nrfx_qspi_cinstr_xfer+0x66>
    450c:	200009cc 	.word	0x200009cc
    4510:	5002b000 	.word	0x5002b000
    4514:	0bad0007 	.word	0x0bad0007
    4518:	0bad0000 	.word	0x0bad0000
    451c:	0bad000b 	.word	0x0bad000b

00004520 <nrfx_qspi_mem_busy_check>:
{
    4520:	b51f      	push	{r0, r1, r2, r3, r4, lr}
    uint8_t status_value = 0;
    4522:	2300      	movs	r3, #0
    nrf_qspi_cinstr_conf_t const config = {
    4524:	4a0c      	ldr	r2, [pc, #48]	; (4558 <nrfx_qspi_mem_busy_check+0x38>)
    ret_code = nrfx_qspi_cinstr_xfer(&config, &status_value, &status_value);
    4526:	a802      	add	r0, sp, #8
    nrf_qspi_cinstr_conf_t const config = {
    4528:	9202      	str	r2, [sp, #8]
    ret_code = nrfx_qspi_cinstr_xfer(&config, &status_value, &status_value);
    452a:	f10d 0207 	add.w	r2, sp, #7
    452e:	4611      	mov	r1, r2
    uint8_t status_value = 0;
    4530:	f88d 3007 	strb.w	r3, [sp, #7]
    nrf_qspi_cinstr_conf_t const config = {
    4534:	f8ad 300c 	strh.w	r3, [sp, #12]
    ret_code = nrfx_qspi_cinstr_xfer(&config, &status_value, &status_value);
    4538:	f7ff ffb2 	bl	44a0 <nrfx_qspi_cinstr_xfer>
    if (ret_code != NRFX_SUCCESS)
    453c:	4b07      	ldr	r3, [pc, #28]	; (455c <nrfx_qspi_mem_busy_check+0x3c>)
    453e:	4298      	cmp	r0, r3
    4540:	d106      	bne.n	4550 <nrfx_qspi_mem_busy_check+0x30>
    if ((status_value & QSPI_MEM_STATUSREG_WIP_Pos) != 0x00)
    4542:	f89d 3007 	ldrb.w	r3, [sp, #7]
        return NRFX_ERROR_BUSY;
    4546:	f013 0f01 	tst.w	r3, #1
    454a:	4b05      	ldr	r3, [pc, #20]	; (4560 <nrfx_qspi_mem_busy_check+0x40>)
    454c:	bf18      	it	ne
    454e:	4618      	movne	r0, r3
}
    4550:	b005      	add	sp, #20
    4552:	f85d fb04 	ldr.w	pc, [sp], #4
    4556:	bf00      	nop
    4558:	01000205 	.word	0x01000205
    455c:	0bad0000 	.word	0x0bad0000
    4560:	0bad000b 	.word	0x0bad000b

00004564 <nrfx_qspi_uninit>:
{
    4564:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    NRFX_IRQ_DISABLE(QSPI_IRQn);
    4568:	202b      	movs	r0, #43	; 0x2b
    456a:	f7fd f819 	bl	15a0 <arch_irq_disable>
    return (bool)((p_reg->CINSTRCONF & (QSPI_CINSTRCONF_LFEN_Msk | QSPI_CINSTRCONF_LFSTOP_Msk))
    456e:	4b21      	ldr	r3, [pc, #132]	; (45f4 <nrfx_qspi_uninit+0x90>)
    if (!m_cb.skip_gpio_cfg)
    4570:	4e21      	ldr	r6, [pc, #132]	; (45f8 <nrfx_qspi_uninit+0x94>)
    4572:	f8d3 2634 	ldr.w	r2, [r3, #1588]	; 0x634
    4576:	f402 3240 	and.w	r2, r2, #196608	; 0x30000
    if (nrf_qspi_cinstr_long_transfer_is_ongoing(NRF_QSPI))
    457a:	f5b2 3f80 	cmp.w	r2, #65536	; 0x10000
    p_reg->CINSTRCONF = mask;
    457e:	bf04      	itt	eq
    4580:	4a1e      	ldreq	r2, [pc, #120]	; (45fc <nrfx_qspi_uninit+0x98>)
    4582:	f8c3 2634 	streq.w	r2, [r3, #1588]	; 0x634
    p_reg->INTENCLR = mask;
    4586:	2201      	movs	r2, #1
    4588:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    458c:	611a      	str	r2, [r3, #16]
    p_reg->ENABLE = (QSPI_ENABLE_ENABLE_Disabled << QSPI_ENABLE_ENABLE_Pos);
    458e:	2200      	movs	r2, #0
    4590:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    4594:	f8c3 2100 	str.w	r2, [r3, #256]	; 0x100
    if (!m_cb.skip_gpio_cfg)
    4598:	f896 2031 	ldrb.w	r2, [r6, #49]	; 0x31
    459c:	bb22      	cbnz	r2, 45e8 <nrfx_qspi_uninit+0x84>
    p_pins->sck_pin = (uint8_t)p_reg->PSEL.SCK;
    459e:	f8d3 0524 	ldr.w	r0, [r3, #1316]	; 0x524
    p_pins->csn_pin = (uint8_t)p_reg->PSEL.CSN;
    45a2:	f8d3 9528 	ldr.w	r9, [r3, #1320]	; 0x528
    nrf_gpio_cfg_default(pins.sck_pin);
    45a6:	b2c0      	uxtb	r0, r0
    p_pins->io0_pin = (uint8_t)p_reg->PSEL.IO0;
    45a8:	f8d3 8530 	ldr.w	r8, [r3, #1328]	; 0x530
    p_pins->io1_pin = (uint8_t)p_reg->PSEL.IO1;
    45ac:	f8d3 7534 	ldr.w	r7, [r3, #1332]	; 0x534
    p_pins->io2_pin = (uint8_t)p_reg->PSEL.IO2;
    45b0:	f8d3 5538 	ldr.w	r5, [r3, #1336]	; 0x538
    p_pins->io3_pin = (uint8_t)p_reg->PSEL.IO3;
    45b4:	f8d3 453c 	ldr.w	r4, [r3, #1340]	; 0x53c
    45b8:	f002 facc 	bl	6b54 <nrf_gpio_cfg_default>
    nrf_gpio_cfg_default(pins.csn_pin);
    45bc:	fa5f f089 	uxtb.w	r0, r9
    45c0:	f002 fac8 	bl	6b54 <nrf_gpio_cfg_default>
    nrf_gpio_cfg_default(pins.io0_pin);
    45c4:	fa5f f088 	uxtb.w	r0, r8
    45c8:	f002 fac4 	bl	6b54 <nrf_gpio_cfg_default>
    nrf_gpio_cfg_default(pins.io1_pin);
    45cc:	b2f8      	uxtb	r0, r7
    45ce:	f002 fac1 	bl	6b54 <nrf_gpio_cfg_default>
    if (pins.io2_pin != NRF_QSPI_PIN_NOT_CONNECTED)
    45d2:	b2e8      	uxtb	r0, r5
    45d4:	28ff      	cmp	r0, #255	; 0xff
    45d6:	b2e4      	uxtb	r4, r4
    45d8:	d001      	beq.n	45de <nrfx_qspi_uninit+0x7a>
        nrf_gpio_cfg_default(pins.io2_pin);
    45da:	f002 fabb 	bl	6b54 <nrf_gpio_cfg_default>
    if (pins.io3_pin != NRF_QSPI_PIN_NOT_CONNECTED)
    45de:	2cff      	cmp	r4, #255	; 0xff
    45e0:	d002      	beq.n	45e8 <nrfx_qspi_uninit+0x84>
        nrf_gpio_cfg_default(pins.io3_pin);
    45e2:	4620      	mov	r0, r4
    45e4:	f002 fab6 	bl	6b54 <nrf_gpio_cfg_default>
    m_cb.state = NRFX_QSPI_STATE_UNINITIALIZED;
    45e8:	2300      	movs	r3, #0
    45ea:	f886 3030 	strb.w	r3, [r6, #48]	; 0x30
}
    45ee:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
    45f2:	bf00      	nop
    45f4:	5002b000 	.word	0x5002b000
    45f8:	200009cc 	.word	0x200009cc
    45fc:	00030100 	.word	0x00030100

00004600 <nrfx_qspi_erase>:
    if (!nrfx_is_word_aligned((void const *)start_address))
    4600:	078b      	lsls	r3, r1, #30
    4602:	d121      	bne.n	4648 <nrfx_qspi_erase+0x48>
    if (m_cb.handler && m_cb.state != NRFX_QSPI_STATE_IDLE)
    4604:	4a12      	ldr	r2, [pc, #72]	; (4650 <nrfx_qspi_erase+0x50>)
    4606:	6813      	ldr	r3, [r2, #0]
    4608:	b11b      	cbz	r3, 4612 <nrfx_qspi_erase+0x12>
    460a:	f892 3030 	ldrb.w	r3, [r2, #48]	; 0x30
    460e:	2b01      	cmp	r3, #1
    4610:	d11c      	bne.n	464c <nrfx_qspi_erase+0x4c>
    m_cb.state = NRFX_QSPI_STATE_ERASE;
    4612:	2304      	movs	r3, #4
    4614:	f882 3030 	strb.w	r3, [r2, #48]	; 0x30
    p_reg->ERASE.PTR = erase_addr;
    4618:	4b0e      	ldr	r3, [pc, #56]	; (4654 <nrfx_qspi_erase+0x54>)
    461a:	f8c3 151c 	str.w	r1, [r3, #1308]	; 0x51c
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    461e:	2100      	movs	r1, #0
    p_reg->ERASE.LEN = len;
    4620:	f8c3 0520 	str.w	r0, [r3, #1312]	; 0x520
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    4624:	f8c3 1100 	str.w	r1, [r3, #256]	; 0x100
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    4628:	2101      	movs	r1, #1
    462a:	60d9      	str	r1, [r3, #12]
    if (!m_cb.handler)
    462c:	6810      	ldr	r0, [r2, #0]
    462e:	b940      	cbnz	r0, 4642 <nrfx_qspi_erase+0x42>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    4630:	f8d3 1100 	ldr.w	r1, [r3, #256]	; 0x100
        while (!nrf_qspi_event_check(NRF_QSPI, NRF_QSPI_EVENT_READY))
    4634:	2900      	cmp	r1, #0
    4636:	d0fb      	beq.n	4630 <nrfx_qspi_erase+0x30>
        m_cb.state = NRFX_QSPI_STATE_IDLE;
    4638:	2301      	movs	r3, #1
    463a:	f882 3030 	strb.w	r3, [r2, #48]	; 0x30
        return NRFX_ERROR_BUSY;
    463e:	4806      	ldr	r0, [pc, #24]	; (4658 <nrfx_qspi_erase+0x58>)
    4640:	4770      	bx	lr
    p_reg->INTENSET = mask;
    4642:	f8c3 1304 	str.w	r1, [r3, #772]	; 0x304
}
    4646:	e7fa      	b.n	463e <nrfx_qspi_erase+0x3e>
        return NRFX_ERROR_INVALID_ADDR;
    4648:	4804      	ldr	r0, [pc, #16]	; (465c <nrfx_qspi_erase+0x5c>)
    464a:	4770      	bx	lr
        return NRFX_ERROR_BUSY;
    464c:	4804      	ldr	r0, [pc, #16]	; (4660 <nrfx_qspi_erase+0x60>)
}
    464e:	4770      	bx	lr
    4650:	200009cc 	.word	0x200009cc
    4654:	5002b000 	.word	0x5002b000
    4658:	0bad0000 	.word	0x0bad0000
    465c:	0bad000a 	.word	0x0bad000a
    4660:	0bad000b 	.word	0x0bad000b

00004664 <nrfx_qspi_irq_handler>:
            break;
    }
}

void nrfx_qspi_irq_handler(void)
{
    4664:	b510      	push	{r4, lr}
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    4666:	4b17      	ldr	r3, [pc, #92]	; (46c4 <nrfx_qspi_irq_handler+0x60>)
    4668:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    // Catch Event ready interrupts
    if (nrf_qspi_event_check(NRF_QSPI, NRF_QSPI_EVENT_READY))
    466c:	b1e2      	cbz	r2, 46a8 <nrfx_qspi_irq_handler+0x44>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    466e:	2200      	movs	r2, #0
    switch (m_cb.state)
    4670:	4c15      	ldr	r4, [pc, #84]	; (46c8 <nrfx_qspi_irq_handler+0x64>)
    4672:	f8c3 2100 	str.w	r2, [r3, #256]	; 0x100
    4676:	f894 2030 	ldrb.w	r2, [r4, #48]	; 0x30
    467a:	2a03      	cmp	r2, #3
    467c:	d015      	beq.n	46aa <nrfx_qspi_irq_handler+0x46>
    467e:	2a04      	cmp	r2, #4
    4680:	d015      	beq.n	46ae <nrfx_qspi_irq_handler+0x4a>
    4682:	2a02      	cmp	r2, #2
    4684:	d104      	bne.n	4690 <nrfx_qspi_irq_handler+0x2c>
            p_event->type = NRFX_QSPI_EVENT_WRITE_DONE;
    4686:	2301      	movs	r3, #1
            p_event->type = NRFX_QSPI_EVENT_READ_DONE;
    4688:	f884 3020 	strb.w	r3, [r4, #32]
            qspi_event_xfer_handle(&p_event->data.xfer);
    468c:	f7ff fdae 	bl	41ec <qspi_event_xfer_handle.constprop.0>
    {
        nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY);

        qspi_extended_event_process(&m_cb.evt_ext);
        if (!m_cb.p_buffer_primary)
    4690:	68a3      	ldr	r3, [r4, #8]
    4692:	b913      	cbnz	r3, 469a <nrfx_qspi_irq_handler+0x36>
        {
            m_cb.state = NRFX_QSPI_STATE_IDLE;
    4694:	2301      	movs	r3, #1
    4696:	f884 3030 	strb.w	r3, [r4, #48]	; 0x30
        }

        m_cb.handler(NRFX_QSPI_EVENT_DONE, m_cb.p_context);
    469a:	e9d4 3100 	ldrd	r3, r1, [r4]
    469e:	2000      	movs	r0, #0
    46a0:	4798      	blx	r3
        m_cb.evt_ext.type = NRFX_QSPI_EVENT_NONE;
    46a2:	2300      	movs	r3, #0
    46a4:	f884 3020 	strb.w	r3, [r4, #32]
    }
}
    46a8:	bd10      	pop	{r4, pc}
            p_event->type = NRFX_QSPI_EVENT_READ_DONE;
    46aa:	2302      	movs	r3, #2
    46ac:	e7ec      	b.n	4688 <nrfx_qspi_irq_handler+0x24>
            p_event->type = NRFX_QSPI_EVENT_ERASE_DONE;
    46ae:	2203      	movs	r2, #3
    46b0:	f884 2020 	strb.w	r2, [r4, #32]
    return p_reg->ERASE.PTR;
    46b4:	f8d3 251c 	ldr.w	r2, [r3, #1308]	; 0x51c
    p_erase->addr = nrf_qspi_erase_ptr_get(NRF_QSPI);
    46b8:	6262      	str	r2, [r4, #36]	; 0x24
    return (nrf_qspi_erase_len_t)p_reg->ERASE.LEN;
    46ba:	f8d3 3520 	ldr.w	r3, [r3, #1312]	; 0x520
    46be:	f884 3028 	strb.w	r3, [r4, #40]	; 0x28
}
    46c2:	e7e5      	b.n	4690 <nrfx_qspi_irq_handler+0x2c>
    46c4:	5002b000 	.word	0x5002b000
    46c8:	200009cc 	.word	0x200009cc

000046cc <nrf_gpio_pin_clear>:
        case 0: return NRF_P0;
    46cc:	4a05      	ldr	r2, [pc, #20]	; (46e4 <nrf_gpio_pin_clear+0x18>)
    46ce:	4b06      	ldr	r3, [pc, #24]	; (46e8 <nrf_gpio_pin_clear+0x1c>)
    *p_pin = pin_number & 0x1F;
    46d0:	f000 011f 	and.w	r1, r0, #31
    return pin_number >> 5;
    46d4:	0940      	lsrs	r0, r0, #5
        case 0: return NRF_P0;
    46d6:	2801      	cmp	r0, #1
    46d8:	bf18      	it	ne
    46da:	4613      	movne	r3, r2
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    46dc:	2201      	movs	r2, #1
    46de:	408a      	lsls	r2, r1
    p_reg->OUTCLR = clr_mask;
    46e0:	60da      	str	r2, [r3, #12]
}
    46e2:	4770      	bx	lr
    46e4:	50842500 	.word	0x50842500
    46e8:	50842800 	.word	0x50842800

000046ec <nrf_gpio_cfg.constprop.0>:
NRF_STATIC_INLINE void nrf_gpio_cfg(
    46ec:	b570      	push	{r4, r5, r6, lr}
        case 0: return NRF_P0;
    46ee:	4c0d      	ldr	r4, [pc, #52]	; (4724 <nrf_gpio_cfg.constprop.0+0x38>)
    46f0:	4e0d      	ldr	r6, [pc, #52]	; (4728 <nrf_gpio_cfg.constprop.0+0x3c>)
    *p_pin = pin_number & 0x1F;
    46f2:	f000 051f 	and.w	r5, r0, #31
    return pin_number >> 5;
    46f6:	0940      	lsrs	r0, r0, #5
        case 0: return NRF_P0;
    46f8:	2801      	cmp	r0, #1
    46fa:	bf18      	it	ne
    46fc:	4634      	movne	r4, r6
           ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) |
    46fe:	f89d 0010 	ldrb.w	r0, [sp, #16]
    4702:	eb04 0485 	add.w	r4, r4, r5, lsl #2
    4706:	0200      	lsls	r0, r0, #8
    uint32_t cnf = reg->PIN_CNF[pin_number] & GPIO_PIN_CNF_MCUSEL_Msk;
    4708:	f8d4 5200 	ldr.w	r5, [r4, #512]	; 0x200
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    470c:	ea40 0083 	orr.w	r0, r0, r3, lsl #2
    4710:	4308      	orrs	r0, r1
    uint32_t cnf = reg->PIN_CNF[pin_number] & GPIO_PIN_CNF_MCUSEL_Msk;
    4712:	f005 45e0 	and.w	r5, r5, #1879048192	; 0x70000000
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    4716:	ea40 0042 	orr.w	r0, r0, r2, lsl #1
    cnf |= ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)     |
    471a:	4328      	orrs	r0, r5
    reg->PIN_CNF[pin_number] = cnf;
    471c:	f8c4 0200 	str.w	r0, [r4, #512]	; 0x200
}
    4720:	bd70      	pop	{r4, r5, r6, pc}
    4722:	bf00      	nop
    4724:	50842800 	.word	0x50842800
    4728:	50842500 	.word	0x50842500

0000472c <nrf_gpio_pin_set>:
        case 0: return NRF_P0;
    472c:	4a05      	ldr	r2, [pc, #20]	; (4744 <nrf_gpio_pin_set+0x18>)
    472e:	4b06      	ldr	r3, [pc, #24]	; (4748 <nrf_gpio_pin_set+0x1c>)
    *p_pin = pin_number & 0x1F;
    4730:	f000 011f 	and.w	r1, r0, #31
    return pin_number >> 5;
    4734:	0940      	lsrs	r0, r0, #5
        case 0: return NRF_P0;
    4736:	2801      	cmp	r0, #1
    4738:	bf18      	it	ne
    473a:	4613      	movne	r3, r2
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    473c:	2201      	movs	r2, #1
    473e:	408a      	lsls	r2, r1
    p_reg->OUTSET = set_mask;
    4740:	609a      	str	r2, [r3, #8]
}
    4742:	4770      	bx	lr
    4744:	50842500 	.word	0x50842500
    4748:	50842800 	.word	0x50842800

0000474c <nrfx_spim_init>:

nrfx_err_t nrfx_spim_init(nrfx_spim_t const *        p_instance,
                          nrfx_spim_config_t const * p_config,
                          nrfx_spim_evt_handler_t    handler,
                          void *                     p_context)
{
    474c:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    NRFX_ASSERT(p_config);
    spim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
    NRF_SPIM_Type * p_spim = (NRF_SPIM_Type *)p_instance->p_reg;
    nrfx_err_t err_code;

    if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED)
    4750:	4d87      	ldr	r5, [pc, #540]	; (4970 <nrfx_spim_init+0x224>)
    spim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
    4752:	7907      	ldrb	r7, [r0, #4]
{
    4754:	460c      	mov	r4, r1
    if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED)
    4756:	eb05 1147 	add.w	r1, r5, r7, lsl #5
    475a:	7f09      	ldrb	r1, [r1, #28]
{
    475c:	4680      	mov	r8, r0
    if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED)
    475e:	2900      	cmp	r1, #0
    4760:	f040 8100 	bne.w	4964 <nrfx_spim_init+0x218>
        return err_code;
    }

#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED)
    // Check if SPIM instance supports the extended features.
    if (
    4764:	2f00      	cmp	r7, #0
    4766:	f040 80ff 	bne.w	4968 <nrfx_spim_init+0x21c>
    NRF_SPIM_Type * p_spim = (NRF_SPIM_Type *)p_instance->p_reg;
    476a:	f8d0 9000 	ldr.w	r9, [r0]
        (!SPIM_SUPPORTED_FREQ_VALIDATE(p_instance->drv_inst_idx, p_config->frequency)) ||
    476e:	68a0      	ldr	r0, [r4, #8]
        ((p_config->use_hw_ss) &&
         !SPIM_HW_CSN_PRESENT_VALIDATE(p_instance->drv_inst_idx)) ||
        ((p_config->dcx_pin != NRFX_SPIM_PIN_NOT_USED) &&
    4770:	7be6      	ldrb	r6, [r4, #15]
        (!SPIM_SUPPORTED_FREQ_VALIDATE(p_instance->drv_inst_idx, p_config->frequency)) ||
    4772:	f1b0 6f20 	cmp.w	r0, #167772160	; 0xa000000

#if NRF_SPIM_HAS_32_MHZ_FREQ && defined(NRF5340_XXAA_APPLICATION)
    // Check if dedicated SPIM pins are used, unless both GPIO configuration
    // and pin selection are to be skipped (pin numbers may be not specified
    // in such case).
    if (!(p_config->skip_gpio_cfg && p_config->skip_psel_cfg) &&
    4776:	7ce1      	ldrb	r1, [r4, #19]
        (!SPIM_SUPPORTED_FREQ_VALIDATE(p_instance->drv_inst_idx, p_config->frequency)) ||
    4778:	d027      	beq.n	47ca <nrfx_spim_init+0x7e>
    477a:	f1b0 5fa0 	cmp.w	r0, #335544320	; 0x14000000
    477e:	d124      	bne.n	47ca <nrfx_spim_init+0x7e>
    if (!(p_config->skip_gpio_cfg && p_config->skip_psel_cfg) &&
    4780:	b119      	cbz	r1, 478a <nrfx_spim_init+0x3e>
    4782:	7d20      	ldrb	r0, [r4, #20]
    4784:	2800      	cmp	r0, #0
    4786:	f040 80d5 	bne.w	4934 <nrfx_spim_init+0x1e8>
    478a:	487a      	ldr	r0, [pc, #488]	; (4974 <nrfx_spim_init+0x228>)
    478c:	4581      	cmp	r9, r0
    478e:	d11c      	bne.n	47ca <nrfx_spim_init+0x7e>
            SPIM_MISO_DEDICATED = NRF_GPIO_PIN_MAP(0, 10),
            SPIM_CSN_DEDICATED  = NRF_GPIO_PIN_MAP(0, 11),
            SPIM_DCX_DEDICATED  = NRF_GPIO_PIN_MAP(0, 12),
        };

        if (!SPIM_DEDICATED_PIN_VALIDATE(p_config->sck_pin, SPIM_SCK_DEDICATED) ||
    4790:	7820      	ldrb	r0, [r4, #0]
    4792:	28ff      	cmp	r0, #255	; 0xff
    4794:	d002      	beq.n	479c <nrfx_spim_init+0x50>
    4796:	2808      	cmp	r0, #8
    4798:	f040 80e8 	bne.w	496c <nrfx_spim_init+0x220>
            !SPIM_DEDICATED_PIN_VALIDATE(p_config->ss_pin,  SPIM_CSN_DEDICATED) ||
    479c:	78e0      	ldrb	r0, [r4, #3]
        if (!SPIM_DEDICATED_PIN_VALIDATE(p_config->sck_pin, SPIM_SCK_DEDICATED) ||
    479e:	28ff      	cmp	r0, #255	; 0xff
    47a0:	d002      	beq.n	47a8 <nrfx_spim_init+0x5c>
            !SPIM_DEDICATED_PIN_VALIDATE(p_config->ss_pin,  SPIM_CSN_DEDICATED) ||
    47a2:	280b      	cmp	r0, #11
    47a4:	f040 80e2 	bne.w	496c <nrfx_spim_init+0x220>
    47a8:	2eff      	cmp	r6, #255	; 0xff
    47aa:	d002      	beq.n	47b2 <nrfx_spim_init+0x66>
#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED)
            !SPIM_DEDICATED_PIN_VALIDATE(p_config->dcx_pin, SPIM_DCX_DEDICATED) ||
    47ac:	2e0c      	cmp	r6, #12
    47ae:	f040 80dd 	bne.w	496c <nrfx_spim_init+0x220>
#endif
            !SPIM_DEDICATED_PIN_VALIDATE(p_config->mosi_pin, SPIM_MOSI_DEDICATED) ||
    47b2:	7860      	ldrb	r0, [r4, #1]
            !SPIM_DEDICATED_PIN_VALIDATE(p_config->dcx_pin, SPIM_DCX_DEDICATED) ||
    47b4:	28ff      	cmp	r0, #255	; 0xff
    47b6:	d002      	beq.n	47be <nrfx_spim_init+0x72>
            !SPIM_DEDICATED_PIN_VALIDATE(p_config->mosi_pin, SPIM_MOSI_DEDICATED) ||
    47b8:	2809      	cmp	r0, #9
    47ba:	f040 80d7 	bne.w	496c <nrfx_spim_init+0x220>
            !SPIM_DEDICATED_PIN_VALIDATE(p_config->miso_pin, SPIM_MISO_DEDICATED))
    47be:	78a0      	ldrb	r0, [r4, #2]
            !SPIM_DEDICATED_PIN_VALIDATE(p_config->mosi_pin, SPIM_MOSI_DEDICATED) ||
    47c0:	28ff      	cmp	r0, #255	; 0xff
    47c2:	d002      	beq.n	47ca <nrfx_spim_init+0x7e>
            !SPIM_DEDICATED_PIN_VALIDATE(p_config->miso_pin, SPIM_MISO_DEDICATED))
    47c4:	280a      	cmp	r0, #10
    47c6:	f040 80d1 	bne.w	496c <nrfx_spim_init+0x220>
        return err_code;
    }
#endif // NRFX_CHECK(NRFX_PRS_ENABLED)

    p_cb->handler = handler;
    p_cb->p_context = p_context;
    47ca:	e9c5 2300 	strd	r2, r3, [r5]

    p_cb->skip_gpio_cfg = p_config->skip_gpio_cfg;
    47ce:	7fab      	ldrb	r3, [r5, #30]
    47d0:	f361 0300 	bfi	r3, r1, #0, #1
    47d4:	77ab      	strb	r3, [r5, #30]
    p_cb->ss_active_high = p_config->ss_active_high;
    47d6:	7922      	ldrb	r2, [r4, #4]
    47d8:	b2db      	uxtb	r3, r3
    47da:	f362 0341 	bfi	r3, r2, #1, #1
    47de:	77ab      	strb	r3, [r5, #30]
#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED)
    p_cb->use_hw_ss = p_config->use_hw_ss;
    47e0:	7c62      	ldrb	r2, [r4, #17]
    47e2:	b2db      	uxtb	r3, r3
    47e4:	f362 0382 	bfi	r3, r2, #2, #1
    47e8:	77ab      	strb	r3, [r5, #30]
#endif
    p_cb->ss_pin = p_config->ss_pin;
    47ea:	78e3      	ldrb	r3, [r4, #3]
    47ec:	77eb      	strb	r3, [r5, #31]
    if (!p_config->skip_gpio_cfg)
    47ee:	7ce3      	ldrb	r3, [r4, #19]
    NRF_SPIM_Type * p_spim = (NRF_SPIM_Type *)p_instance->p_reg;
    47f0:	f8d8 6000 	ldr.w	r6, [r8]
    if (!p_config->skip_gpio_cfg)
    47f4:	2b00      	cmp	r3, #0
    47f6:	d142      	bne.n	487e <nrfx_spim_init+0x132>
                    : NRF_GPIO_PIN_S0S1;
    47f8:	68a3      	ldr	r3, [r4, #8]
        nrf_gpio_pin_write(p_config->sck_pin,
    47fa:	7820      	ldrb	r0, [r4, #0]
                    : NRF_GPIO_PIN_S0S1;
    47fc:	f1b3 5fa0 	cmp.w	r3, #335544320	; 0x14000000
    if (value == 0)
    4800:	7b23      	ldrb	r3, [r4, #12]
    4802:	bf08      	it	eq
    4804:	2703      	moveq	r7, #3
    4806:	2b01      	cmp	r3, #1
    4808:	f200 8096 	bhi.w	4938 <nrfx_spim_init+0x1ec>
        nrf_gpio_pin_clear(pin_number);
    480c:	f7ff ff5e 	bl	46cc <nrf_gpio_pin_clear>
        nrf_gpio_cfg(p_config->sck_pin,
    4810:	2300      	movs	r3, #0
    4812:	9700      	str	r7, [sp, #0]
    4814:	7820      	ldrb	r0, [r4, #0]
    4816:	461a      	mov	r2, r3
    4818:	2101      	movs	r1, #1
    481a:	f7ff ff67 	bl	46ec <nrf_gpio_cfg.constprop.0>
        if (p_config->mosi_pin != NRFX_SPIM_PIN_NOT_USED)
    481e:	7860      	ldrb	r0, [r4, #1]
    4820:	28ff      	cmp	r0, #255	; 0xff
    4822:	d008      	beq.n	4836 <nrfx_spim_init+0xea>
    4824:	f7ff ff52 	bl	46cc <nrf_gpio_pin_clear>
            nrf_gpio_cfg(p_config->mosi_pin,
    4828:	2201      	movs	r2, #1
    482a:	9700      	str	r7, [sp, #0]
    482c:	2300      	movs	r3, #0
    482e:	4611      	mov	r1, r2
    4830:	7860      	ldrb	r0, [r4, #1]
    4832:	f7ff ff5b 	bl	46ec <nrf_gpio_cfg.constprop.0>
        if (p_config->miso_pin != NRFX_SPIM_PIN_NOT_USED)
    4836:	78a0      	ldrb	r0, [r4, #2]
    4838:	28ff      	cmp	r0, #255	; 0xff
    483a:	d005      	beq.n	4848 <nrfx_spim_init+0xfc>
            nrf_gpio_cfg(p_config->miso_pin,
    483c:	2200      	movs	r2, #0
    483e:	9700      	str	r7, [sp, #0]
    4840:	4611      	mov	r1, r2
    4842:	7ba3      	ldrb	r3, [r4, #14]
    4844:	f7ff ff52 	bl	46ec <nrf_gpio_cfg.constprop.0>
        if (p_config->ss_pin != NRFX_SPIM_PIN_NOT_USED)
    4848:	78e0      	ldrb	r0, [r4, #3]
    484a:	28ff      	cmp	r0, #255	; 0xff
    484c:	d00b      	beq.n	4866 <nrfx_spim_init+0x11a>
    if (value == 0)
    484e:	7923      	ldrb	r3, [r4, #4]
    4850:	2b00      	cmp	r3, #0
    4852:	d074      	beq.n	493e <nrfx_spim_init+0x1f2>
        nrf_gpio_pin_clear(pin_number);
    4854:	f7ff ff3a 	bl	46cc <nrf_gpio_pin_clear>
            nrf_gpio_cfg(p_config->ss_pin,
    4858:	2201      	movs	r2, #1
    485a:	9700      	str	r7, [sp, #0]
    485c:	2300      	movs	r3, #0
    485e:	4611      	mov	r1, r2
    4860:	78e0      	ldrb	r0, [r4, #3]
    4862:	f7ff ff43 	bl	46ec <nrf_gpio_cfg.constprop.0>
        if (p_config->dcx_pin != NRFX_SPIM_PIN_NOT_USED)
    4866:	7be0      	ldrb	r0, [r4, #15]
    4868:	28ff      	cmp	r0, #255	; 0xff
    486a:	d008      	beq.n	487e <nrfx_spim_init+0x132>
        nrf_gpio_pin_set(pin_number);
    486c:	f7ff ff5e 	bl	472c <nrf_gpio_pin_set>
            nrf_gpio_cfg(p_config->dcx_pin,
    4870:	2201      	movs	r2, #1
    4872:	9700      	str	r7, [sp, #0]
    4874:	2300      	movs	r3, #0
    4876:	4611      	mov	r1, r2
    4878:	7be0      	ldrb	r0, [r4, #15]
    487a:	f7ff ff37 	bl	46ec <nrf_gpio_cfg.constprop.0>
    if (!p_config->skip_psel_cfg)
    487e:	7d23      	ldrb	r3, [r4, #20]
    4880:	bb6b      	cbnz	r3, 48de <nrfx_spim_init+0x192>
        uint32_t mosi_pin = (p_config->mosi_pin != NRFX_SPIM_PIN_NOT_USED)
    4882:	7863      	ldrb	r3, [r4, #1]
        nrf_spim_pins_set(p_spim, p_config->sck_pin, mosi_pin, miso_pin);
    4884:	7821      	ldrb	r1, [r4, #0]
                            : NRF_SPIM_PIN_NOT_CONNECTED;
    4886:	2bff      	cmp	r3, #255	; 0xff
    4888:	bf18      	it	ne
    488a:	461a      	movne	r2, r3
        uint32_t miso_pin = (p_config->miso_pin != NRFX_SPIM_PIN_NOT_USED)
    488c:	78a3      	ldrb	r3, [r4, #2]
                            : NRF_SPIM_PIN_NOT_CONNECTED;
    488e:	bf08      	it	eq
    4890:	f04f 32ff 	moveq.w	r2, #4294967295
                            : NRF_SPIM_PIN_NOT_CONNECTED;
    4894:	2bff      	cmp	r3, #255	; 0xff
    4896:	bf08      	it	eq
    4898:	f04f 33ff 	moveq.w	r3, #4294967295
NRF_STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_reg,
                                         uint32_t        sck_pin,
                                         uint32_t        mosi_pin,
                                         uint32_t        miso_pin)
{
    p_reg->PSEL.SCK  = sck_pin;
    489c:	f8c6 1508 	str.w	r1, [r6, #1288]	; 0x508
    p_reg->PSEL.MOSI = mosi_pin;
    48a0:	f8c6 250c 	str.w	r2, [r6, #1292]	; 0x50c
    p_reg->PSEL.MISO = miso_pin;
    48a4:	f8c6 3510 	str.w	r3, [r6, #1296]	; 0x510
        if (SPIM_HW_CSN_PRESENT_VALIDATE(p_instance->drv_inst_idx))
    48a8:	f898 3004 	ldrb.w	r3, [r8, #4]
    48ac:	b9bb      	cbnz	r3, 48de <nrfx_spim_init+0x192>
            if (p_config->ss_pin != NRFX_SPIM_PIN_NOT_USED &&
    48ae:	78e3      	ldrb	r3, [r4, #3]
    48b0:	2bff      	cmp	r3, #255	; 0xff
    48b2:	d047      	beq.n	4944 <nrfx_spim_init+0x1f8>
    48b4:	7c62      	ldrb	r2, [r4, #17]
    48b6:	2a00      	cmp	r2, #0
    48b8:	d044      	beq.n	4944 <nrfx_spim_init+0x1f8>
                                    (p_config->ss_active_high == true
    48ba:	7921      	ldrb	r1, [r4, #4]
                nrf_spim_csn_configure(p_spim,
    48bc:	7ca2      	ldrb	r2, [r4, #18]
NRF_STATIC_INLINE void nrf_spim_csn_configure(NRF_SPIM_Type *    p_reg,
                                              uint32_t           pin,
                                              nrf_spim_csn_pol_t polarity,
                                              uint32_t           duration)
{
    p_reg->PSEL.CSN = pin;
    48be:	f8c6 3514 	str.w	r3, [r6, #1300]	; 0x514
    p_reg->CSNPOL = polarity;
    48c2:	f8c6 1568 	str.w	r1, [r6, #1384]	; 0x568
    p_reg->IFTIMING.CSNDUR = duration;
    48c6:	f8c6 2564 	str.w	r2, [r6, #1380]	; 0x564
        if (SPIM_DCX_PRESENT_VALIDATE(p_instance->drv_inst_idx))
    48ca:	f898 3004 	ldrb.w	r3, [r8, #4]
    48ce:	b933      	cbnz	r3, 48de <nrfx_spim_init+0x192>
            uint32_t dcx_pin = (p_config->dcx_pin != NRFX_SPIM_PIN_NOT_USED)
    48d0:	7be3      	ldrb	r3, [r4, #15]
                               : NRF_SPIM_PIN_NOT_CONNECTED;
    48d2:	2bff      	cmp	r3, #255	; 0xff
    48d4:	bf08      	it	eq
    48d6:	f04f 33ff 	moveq.w	r3, #4294967295

#if NRF_SPIM_DCX_PRESENT
NRF_STATIC_INLINE void nrf_spim_dcx_pin_set(NRF_SPIM_Type * p_reg,
                                            uint32_t        dcx_pin)
{
    p_reg->PSELDCX = dcx_pin;
    48da:	f8c6 356c 	str.w	r3, [r6, #1388]	; 0x56c

    configure_pins(p_instance, p_config);

#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED)
    // Change rx delay
    nrf_spim_iftiming_set(p_spim, p_config->rx_delay);
    48de:	7c23      	ldrb	r3, [r4, #16]

#if NRF_SPIM_RXDELAY_PRESENT
NRF_STATIC_INLINE void nrf_spim_iftiming_set(NRF_SPIM_Type * p_reg,
                                             uint32_t        rxdelay)
{
    p_reg->IFTIMING.RXDELAY = rxdelay;
    48e0:	f8c9 3560 	str.w	r3, [r9, #1376]	; 0x560
#endif // defined(SPIM_STALLSTAT_TX_Msk)

NRF_STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type *      p_reg,
                                              nrf_spim_frequency_t frequency)
{
    p_reg->FREQUENCY = (uint32_t)frequency;
    48e4:	68a3      	ldr	r3, [r4, #8]
    48e6:	f8c9 3524 	str.w	r3, [r9, #1316]	; 0x524
NRF_STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type *      p_reg,
                                          nrf_spim_mode_t      spi_mode,
                                          nrf_spim_bit_order_t spi_bit_order)
{
    uint32_t config = (spi_bit_order == NRF_SPIM_BIT_ORDER_MSB_FIRST ?
        SPIM_CONFIG_ORDER_MsbFirst : SPIM_CONFIG_ORDER_LsbFirst);
    48ea:	7b63      	ldrb	r3, [r4, #13]
#endif

    nrf_spim_frequency_set(p_spim, p_config->frequency);
    nrf_spim_configure(p_spim, p_config->mode, p_config->bit_order);
    48ec:	7b22      	ldrb	r2, [r4, #12]
    48ee:	3b00      	subs	r3, #0
    48f0:	bf18      	it	ne
    48f2:	2301      	movne	r3, #1
    switch (spi_mode)
    48f4:	2a02      	cmp	r2, #2
    48f6:	d02f      	beq.n	4958 <nrfx_spim_init+0x20c>
    48f8:	2a03      	cmp	r2, #3
    48fa:	d030      	beq.n	495e <nrfx_spim_init+0x212>
    48fc:	2a01      	cmp	r2, #1
    48fe:	d101      	bne.n	4904 <nrfx_spim_init+0x1b8>
        config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
                  (SPIM_CONFIG_CPHA_Leading    << SPIM_CONFIG_CPHA_Pos);
        break;

    case NRF_SPIM_MODE_1:
        config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
    4900:	f043 0302 	orr.w	r3, r3, #2
    case NRF_SPIM_MODE_3:
        config |= (SPIM_CONFIG_CPOL_ActiveLow  << SPIM_CONFIG_CPOL_Pos) |
                  (SPIM_CONFIG_CPHA_Trailing   << SPIM_CONFIG_CPHA_Pos);
        break;
    }
    p_reg->CONFIG = config;
    4904:	f8c9 3554 	str.w	r3, [r9, #1364]	; 0x554
}

NRF_STATIC_INLINE void nrf_spim_orc_set(NRF_SPIM_Type * p_reg,
                                        uint8_t         orc)
{
    p_reg->ORC = orc;
    4908:	79a3      	ldrb	r3, [r4, #6]
    490a:	f8c9 35c0 	str.w	r3, [r9, #1472]	; 0x5c0
    p_reg->ENABLE = (SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos);
    490e:	2307      	movs	r3, #7
    4910:	f8c9 3500 	str.w	r3, [r9, #1280]	; 0x500

    nrf_spim_orc_set(p_spim, p_config->orc);

    nrf_spim_enable(p_spim);

    if (p_cb->handler)
    4914:	682b      	ldr	r3, [r5, #0]
    4916:	b12b      	cbz	r3, 4924 <nrfx_spim_init+0x1d8>
    return ((((uint32_t)p_object) & 0x3u) == 0u);
}

NRF_STATIC_INLINE IRQn_Type nrfx_get_irq_number(void const * p_reg)
{
    return (IRQn_Type)NRFX_IRQ_NUMBER_GET(p_reg);
    4918:	f8d8 0000 	ldr.w	r0, [r8]
    {
        NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(p_instance->p_reg),
            p_config->irq_priority);
        NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_instance->p_reg));
    491c:	f340 3007 	sbfx	r0, r0, #12, #8
    4920:	f7fc fe30 	bl	1584 <arch_irq_enable>
    }

    p_cb->transfer_in_progress = false;
    4924:	2300      	movs	r3, #0
    4926:	776b      	strb	r3, [r5, #29]
    p_cb->state = NRFX_DRV_STATE_INITIALIZED;
    4928:	2301      	movs	r3, #1

    err_code = NRFX_SUCCESS;
    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
    492a:	4813      	ldr	r0, [pc, #76]	; (4978 <nrfx_spim_init+0x22c>)
    p_cb->state = NRFX_DRV_STATE_INITIALIZED;
    492c:	772b      	strb	r3, [r5, #28]
}
    492e:	b003      	add	sp, #12
    4930:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
    if (!(p_config->skip_gpio_cfg && p_config->skip_psel_cfg) &&
    4934:	4601      	mov	r1, r0
    4936:	e748      	b.n	47ca <nrfx_spim_init+0x7e>
    4938:	f7ff fef8 	bl	472c <nrf_gpio_pin_set>
    493c:	e768      	b.n	4810 <nrfx_spim_init+0xc4>
    493e:	f7ff fef5 	bl	472c <nrf_gpio_pin_set>
    4942:	e789      	b.n	4858 <nrfx_spim_init+0x10c>
    p_reg->PSEL.CSN = pin;
    4944:	f04f 33ff 	mov.w	r3, #4294967295
    4948:	f8c6 3514 	str.w	r3, [r6, #1300]	; 0x514
    p_reg->CSNPOL = polarity;
    494c:	2300      	movs	r3, #0
    494e:	f8c6 3568 	str.w	r3, [r6, #1384]	; 0x568
    p_reg->IFTIMING.CSNDUR = duration;
    4952:	f8c6 3564 	str.w	r3, [r6, #1380]	; 0x564
}
    4956:	e7b8      	b.n	48ca <nrfx_spim_init+0x17e>
        config |= (SPIM_CONFIG_CPOL_ActiveLow  << SPIM_CONFIG_CPOL_Pos) |
    4958:	f043 0304 	orr.w	r3, r3, #4
        break;
    495c:	e7d2      	b.n	4904 <nrfx_spim_init+0x1b8>
        config |= (SPIM_CONFIG_CPOL_ActiveLow  << SPIM_CONFIG_CPOL_Pos) |
    495e:	f043 0306 	orr.w	r3, r3, #6
        break;
    4962:	e7cf      	b.n	4904 <nrfx_spim_init+0x1b8>
        return err_code;
    4964:	4805      	ldr	r0, [pc, #20]	; (497c <nrfx_spim_init+0x230>)
    4966:	e7e2      	b.n	492e <nrfx_spim_init+0x1e2>
        return err_code;
    4968:	4805      	ldr	r0, [pc, #20]	; (4980 <nrfx_spim_init+0x234>)
    496a:	e7e0      	b.n	492e <nrfx_spim_init+0x1e2>
            return err_code;
    496c:	4805      	ldr	r0, [pc, #20]	; (4984 <nrfx_spim_init+0x238>)
    496e:	e7de      	b.n	492e <nrfx_spim_init+0x1e2>
    4970:	20000a00 	.word	0x20000a00
    4974:	5000a000 	.word	0x5000a000
    4978:	0bad0000 	.word	0x0bad0000
    497c:	0bad0005 	.word	0x0bad0005
    4980:	0bad0003 	.word	0x0bad0003
    4984:	0bad0004 	.word	0x0bad0004

00004988 <nrfx_spim_uninit>:

    nrf_gpio_cfg_default(pin);
}

void nrfx_spim_uninit(nrfx_spim_t const * p_instance)
{
    4988:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
    spim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
    498c:	7903      	ldrb	r3, [r0, #4]
    NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED);
    NRF_SPIM_Type * p_spim = p_instance->p_reg;

    if (p_cb->handler)
    498e:	4d25      	ldr	r5, [pc, #148]	; (4a24 <nrfx_spim_uninit+0x9c>)
    4990:	015e      	lsls	r6, r3, #5
    4992:	eb05 1843 	add.w	r8, r5, r3, lsl #5
    4996:	59ab      	ldr	r3, [r5, r6]
{
    4998:	4607      	mov	r7, r0
    NRF_SPIM_Type * p_spim = p_instance->p_reg;
    499a:	6804      	ldr	r4, [r0, #0]
    if (p_cb->handler)
    499c:	b1cb      	cbz	r3, 49d2 <nrfx_spim_uninit+0x4a>
    {
        NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_instance->p_reg));
    499e:	f344 3007 	sbfx	r0, r4, #12, #8
    49a2:	f7fc fdfd 	bl	15a0 <arch_irq_disable>
    p_reg->INTENCLR = mask;
    49a6:	4b20      	ldr	r3, [pc, #128]	; (4a28 <nrfx_spim_uninit+0xa0>)
    49a8:	f8c4 3308 	str.w	r3, [r4, #776]	; 0x308
        nrf_spim_int_disable(p_spim, NRF_SPIM_ALL_INTS_MASK);
        if (p_cb->transfer_in_progress)
    49ac:	f898 301d 	ldrb.w	r3, [r8, #29]
    49b0:	b17b      	cbz	r3, 49d2 <nrfx_spim_uninit+0x4a>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    49b2:	2301      	movs	r3, #1
    49b4:	f04f 0864 	mov.w	r8, #100	; 0x64
    49b8:	6163      	str	r3, [r4, #20]
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    49ba:	f8d4 3104 	ldr.w	r3, [r4, #260]	; 0x104
    NRFX_WAIT_FOR(nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_STOPPED), 100, 1, stopped);
    49be:	b92b      	cbnz	r3, 49cc <nrfx_spim_uninit+0x44>
    49c0:	2001      	movs	r0, #1
    49c2:	f001 ff2e 	bl	6822 <nrfx_busy_wait>
    49c6:	f1b8 0801 	subs.w	r8, r8, #1
    49ca:	d1f6      	bne.n	49ba <nrfx_spim_uninit+0x32>
    p_cb->transfer_in_progress = false;
    49cc:	2200      	movs	r2, #0
    49ce:	19ab      	adds	r3, r5, r6
    49d0:	775a      	strb	r2, [r3, #29]
    p_reg->ENABLE = (SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos);
    49d2:	2300      	movs	r3, #0
    49d4:	f8c4 3500 	str.w	r3, [r4, #1280]	; 0x500
        }
    }

    nrf_spim_disable(p_spim);

    if (!p_cb->skip_gpio_cfg)
    49d8:	19ab      	adds	r3, r5, r6
    49da:	7f9b      	ldrb	r3, [r3, #30]
    49dc:	07db      	lsls	r3, r3, #31
    49de:	d41b      	bmi.n	4a18 <nrfx_spim_uninit+0x90>
    return p_reg->PSEL.SCK;
    49e0:	f8d4 0508 	ldr.w	r0, [r4, #1288]	; 0x508
    {
        spim_pin_uninit(nrf_spim_sck_pin_get(p_spim));
    49e4:	f002 f8c3 	bl	6b6e <spim_pin_uninit>
    return p_reg->PSEL.MISO;
    49e8:	f8d4 0510 	ldr.w	r0, [r4, #1296]	; 0x510
        spim_pin_uninit(nrf_spim_miso_pin_get(p_spim));
    49ec:	f002 f8bf 	bl	6b6e <spim_pin_uninit>
    return p_reg->PSEL.MOSI;
    49f0:	f8d4 050c 	ldr.w	r0, [r4, #1292]	; 0x50c
        spim_pin_uninit(nrf_spim_mosi_pin_get(p_spim));
    49f4:	f002 f8bb 	bl	6b6e <spim_pin_uninit>
#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED)
        if (SPIM_DCX_PRESENT_VALIDATE(p_instance->drv_inst_idx))
    49f8:	793b      	ldrb	r3, [r7, #4]
    49fa:	b91b      	cbnz	r3, 4a04 <nrfx_spim_uninit+0x7c>
    return p_reg->PSELDCX;
    49fc:	f8d4 056c 	ldr.w	r0, [r4, #1388]	; 0x56c
        {
            spim_pin_uninit(nrf_spim_dcx_pin_get(p_spim));
    4a00:	f002 f8b5 	bl	6b6e <spim_pin_uninit>
        }
#endif
        if (p_cb->ss_pin != NRFX_SPIM_PIN_NOT_USED)
    4a04:	19ab      	adds	r3, r5, r6
    4a06:	7fd8      	ldrb	r0, [r3, #31]
    4a08:	28ff      	cmp	r0, #255	; 0xff
    4a0a:	d005      	beq.n	4a18 <nrfx_spim_uninit+0x90>
    nrf_gpio_cfg(
    4a0c:	2300      	movs	r3, #0
    4a0e:	2201      	movs	r2, #1
    4a10:	4619      	mov	r1, r3
    4a12:	9300      	str	r3, [sp, #0]
    4a14:	f7ff fe6a 	bl	46ec <nrf_gpio_cfg.constprop.0>

#if NRFX_CHECK(NRFX_PRS_ENABLED)
    nrfx_prs_release(p_instance->p_reg);
#endif

    p_cb->state = NRFX_DRV_STATE_UNINITIALIZED;
    4a18:	2300      	movs	r3, #0
    4a1a:	4435      	add	r5, r6
    4a1c:	772b      	strb	r3, [r5, #28]
}
    4a1e:	b002      	add	sp, #8
    4a20:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    4a24:	20000a00 	.word	0x20000a00
    4a28:	00080152 	.word	0x00080152

00004a2c <nrfx_spim_xfer>:
}

nrfx_err_t nrfx_spim_xfer(nrfx_spim_t const *           p_instance,
                          nrfx_spim_xfer_desc_t const * p_xfer_desc,
                          uint32_t                      flags)
{
    4a2c:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    spim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
    4a30:	4f38      	ldr	r7, [pc, #224]	; (4b14 <nrfx_spim_xfer+0xe8>)
    4a32:	7903      	ldrb	r3, [r0, #4]
{
    4a34:	4615      	mov	r5, r2
    spim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
    4a36:	eb07 1843 	add.w	r8, r7, r3, lsl #5
#endif
                (p_cb->ss_pin == NRFX_SPIM_PIN_NOT_USED));

    nrfx_err_t err_code = NRFX_SUCCESS;

    if (p_cb->transfer_in_progress)
    4a3a:	f898 201d 	ldrb.w	r2, [r8, #29]
{
    4a3e:	4681      	mov	r9, r0
    4a40:	460c      	mov	r4, r1
    if (p_cb->transfer_in_progress)
    4a42:	015e      	lsls	r6, r3, #5
    4a44:	2a00      	cmp	r2, #0
    4a46:	d163      	bne.n	4b10 <nrfx_spim_xfer+0xe4>
                         NRFX_LOG_ERROR_STRING_GET(err_code));
        return err_code;
    }
    else
    {
        if (p_cb->handler && !(flags & (NRFX_SPIM_FLAG_REPEATED_XFER |
    4a48:	59ba      	ldr	r2, [r7, r6]
    4a4a:	b12a      	cbz	r2, 4a58 <nrfx_spim_xfer+0x2c>
    4a4c:	f015 0f14 	tst.w	r5, #20
                                        NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER)))
        {
            p_cb->transfer_in_progress = true;
    4a50:	bf04      	itt	eq
    4a52:	2201      	moveq	r2, #1
    4a54:	f888 201d 	strbeq.w	r2, [r8, #29]
        }
    }

    p_cb->evt.xfer_desc = *p_xfer_desc;
    4a58:	eb07 0c06 	add.w	ip, r7, r6
    4a5c:	f10c 0c0c 	add.w	ip, ip, #12
    4a60:	e894 000f 	ldmia.w	r4, {r0, r1, r2, r3}
    4a64:	e88c 000f 	stmia.w	ip, {r0, r1, r2, r3}

    set_ss_pin_state(p_cb, true);
    4a68:	2101      	movs	r1, #1
    4a6a:	4640      	mov	r0, r8
    4a6c:	f002 f88b 	bl	6b86 <set_ss_pin_state>
    if ((p_xfer_desc->p_tx_buffer != NULL && !nrfx_is_in_ram(p_xfer_desc->p_tx_buffer)) ||
    4a70:	6821      	ldr	r1, [r4, #0]

    return spim_xfer(p_instance->p_reg, p_cb,  p_xfer_desc, flags);
    4a72:	f8d9 3000 	ldr.w	r3, [r9]
    if ((p_xfer_desc->p_tx_buffer != NULL && !nrfx_is_in_ram(p_xfer_desc->p_tx_buffer)) ||
    4a76:	b121      	cbz	r1, 4a82 <nrfx_spim_xfer+0x56>
    return ((((uint32_t)p_object) & 0xE0000000u) == 0x20000000u);
    4a78:	f001 4260 	and.w	r2, r1, #3758096384	; 0xe0000000
    4a7c:	f1b2 5f00 	cmp.w	r2, #536870912	; 0x20000000
    4a80:	d106      	bne.n	4a90 <nrfx_spim_xfer+0x64>
        (p_xfer_desc->p_rx_buffer != NULL && !nrfx_is_in_ram(p_xfer_desc->p_rx_buffer)))
    4a82:	68a2      	ldr	r2, [r4, #8]
    if ((p_xfer_desc->p_tx_buffer != NULL && !nrfx_is_in_ram(p_xfer_desc->p_tx_buffer)) ||
    4a84:	b152      	cbz	r2, 4a9c <nrfx_spim_xfer+0x70>
    4a86:	f002 4260 	and.w	r2, r2, #3758096384	; 0xe0000000
        (p_xfer_desc->p_rx_buffer != NULL && !nrfx_is_in_ram(p_xfer_desc->p_rx_buffer)))
    4a8a:	f1b2 5f00 	cmp.w	r2, #536870912	; 0x20000000
    4a8e:	d005      	beq.n	4a9c <nrfx_spim_xfer+0x70>
        p_cb->transfer_in_progress = false;
    4a90:	2300      	movs	r3, #0
    4a92:	443e      	add	r6, r7
        return err_code;
    4a94:	4820      	ldr	r0, [pc, #128]	; (4b18 <nrfx_spim_xfer+0xec>)
        p_cb->transfer_in_progress = false;
    4a96:	7773      	strb	r3, [r6, #29]
}
    4a98:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
    nrf_spim_tx_buffer_set(p_spim, p_xfer_desc->p_tx_buffer, p_xfer_desc->tx_length);
    4a9c:	6862      	ldr	r2, [r4, #4]
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    4a9e:	f8c3 1544 	str.w	r1, [r3, #1348]	; 0x544
    p_reg->TXD.MAXCNT = length;
    4aa2:	f8c3 2548 	str.w	r2, [r3, #1352]	; 0x548
    p_reg->RXD.PTR    = (uint32_t)p_buffer;
    4aa6:	e9d4 1202 	ldrd	r1, r2, [r4, #8]
    4aaa:	f8c3 1534 	str.w	r1, [r3, #1332]	; 0x534
    p_reg->RXD.MAXCNT = length;
    4aae:	f8c3 2538 	str.w	r2, [r3, #1336]	; 0x538
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    4ab2:	2200      	movs	r2, #0
    4ab4:	f8c3 2118 	str.w	r2, [r3, #280]	; 0x118
    4ab8:	f8d3 2118 	ldr.w	r2, [r3, #280]	; 0x118
    if (NRFX_SPIM_FLAG_TX_POSTINC & flags)
    4abc:	f015 0201 	ands.w	r2, r5, #1
}


NRF_STATIC_INLINE void nrf_spim_tx_list_enable(NRF_SPIM_Type * p_reg)
{
    p_reg->TXD.LIST = SPIM_TXD_LIST_LIST_ArrayList << SPIM_TXD_LIST_LIST_Pos;
    4ac0:	bf18      	it	ne
    4ac2:	2201      	movne	r2, #1
}

NRF_STATIC_INLINE void nrf_spim_tx_list_disable(NRF_SPIM_Type * p_reg)
{
    p_reg->TXD.LIST = SPIM_TXD_LIST_LIST_Disabled << SPIM_TXD_LIST_LIST_Pos;
    4ac4:	f8c3 2550 	str.w	r2, [r3, #1360]	; 0x550
    if (NRFX_SPIM_FLAG_RX_POSTINC & flags)
    4ac8:	f015 0202 	ands.w	r2, r5, #2
}

NRF_STATIC_INLINE void nrf_spim_rx_list_enable(NRF_SPIM_Type * p_reg)
{
    p_reg->RXD.LIST = SPIM_RXD_LIST_LIST_ArrayList << SPIM_RXD_LIST_LIST_Pos;
    4acc:	bf18      	it	ne
    4ace:	2201      	movne	r2, #1
}

NRF_STATIC_INLINE void nrf_spim_rx_list_disable(NRF_SPIM_Type * p_reg)
{
    p_reg->RXD.LIST = SPIM_RXD_LIST_LIST_Disabled << SPIM_RXD_LIST_LIST_Pos;
    4ad0:	f8c3 2540 	str.w	r2, [r3, #1344]	; 0x540
    if (!(flags & NRFX_SPIM_FLAG_HOLD_XFER))
    4ad4:	072a      	lsls	r2, r5, #28
    4ad6:	d507      	bpl.n	4ae8 <nrfx_spim_xfer+0xbc>
    if (!p_cb->handler)
    4ad8:	59ba      	ldr	r2, [r7, r6]
    4ada:	b972      	cbnz	r2, 4afa <nrfx_spim_xfer+0xce>
        set_ss_pin_state(p_cb, false);
    4adc:	2100      	movs	r1, #0
    4ade:	4640      	mov	r0, r8
    4ae0:	f002 f851 	bl	6b86 <set_ss_pin_state>
    return err_code;
    4ae4:	480d      	ldr	r0, [pc, #52]	; (4b1c <nrfx_spim_xfer+0xf0>)
    4ae6:	e7d7      	b.n	4a98 <nrfx_spim_xfer+0x6c>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    4ae8:	2201      	movs	r2, #1
    4aea:	611a      	str	r2, [r3, #16]
    if (!p_cb->handler)
    4aec:	59ba      	ldr	r2, [r7, r6]
    4aee:	b922      	cbnz	r2, 4afa <nrfx_spim_xfer+0xce>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    4af0:	f8d3 2118 	ldr.w	r2, [r3, #280]	; 0x118
            while (!nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_END))
    4af4:	2a00      	cmp	r2, #0
    4af6:	d0fb      	beq.n	4af0 <nrfx_spim_xfer+0xc4>
    4af8:	e7f0      	b.n	4adc <nrfx_spim_xfer+0xb0>
    if (!enable)
    4afa:	f015 0f04 	tst.w	r5, #4
    4afe:	f04f 0240 	mov.w	r2, #64	; 0x40
    4b02:	d002      	beq.n	4b0a <nrfx_spim_xfer+0xde>
    p_reg->INTENCLR = mask;
    4b04:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
}
    4b08:	e7ec      	b.n	4ae4 <nrfx_spim_xfer+0xb8>
    p_reg->INTENSET = mask;
    4b0a:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
}
    4b0e:	e7e9      	b.n	4ae4 <nrfx_spim_xfer+0xb8>
        return err_code;
    4b10:	4803      	ldr	r0, [pc, #12]	; (4b20 <nrfx_spim_xfer+0xf4>)
    4b12:	e7c1      	b.n	4a98 <nrfx_spim_xfer+0x6c>
    4b14:	20000a00 	.word	0x20000a00
    4b18:	0bad000a 	.word	0x0bad000a
    4b1c:	0bad0000 	.word	0x0bad0000
    4b20:	0bad000b 	.word	0x0bad000b

00004b24 <nrfx_spim_4_irq_handler>:
}
#endif

#if NRFX_CHECK(NRFX_SPIM4_ENABLED)
void nrfx_spim_4_irq_handler(void)
{
    4b24:	b570      	push	{r4, r5, r6, lr}
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    4b26:	4b0c      	ldr	r3, [pc, #48]	; (4b58 <nrfx_spim_4_irq_handler+0x34>)
    4b28:	f8d3 2118 	ldr.w	r2, [r3, #280]	; 0x118
    if (nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_END))
    4b2c:	b192      	cbz	r2, 4b54 <nrfx_spim_4_irq_handler+0x30>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    4b2e:	2500      	movs	r5, #0
    set_ss_pin_state(p_cb, false);
    4b30:	4c0a      	ldr	r4, [pc, #40]	; (4b5c <nrfx_spim_4_irq_handler+0x38>)
    4b32:	4629      	mov	r1, r5
    4b34:	4620      	mov	r0, r4
    4b36:	f8c3 5118 	str.w	r5, [r3, #280]	; 0x118
    4b3a:	f8d3 3118 	ldr.w	r3, [r3, #280]	; 0x118
    4b3e:	f002 f822 	bl	6b86 <set_ss_pin_state>
    p_cb->handler(&p_cb->evt, p_cb->p_context);
    4b42:	e9d4 3100 	ldrd	r3, r1, [r4]
    p_cb->transfer_in_progress = false;
    4b46:	7765      	strb	r5, [r4, #29]
    p_cb->evt.type = NRFX_SPIM_EVENT_DONE;
    4b48:	7225      	strb	r5, [r4, #8]
    p_cb->handler(&p_cb->evt, p_cb->p_context);
    4b4a:	f104 0008 	add.w	r0, r4, #8
    irq_handler(NRF_SPIM4, &m_cb[NRFX_SPIM4_INST_IDX]);
}
    4b4e:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    p_cb->handler(&p_cb->evt, p_cb->p_context);
    4b52:	4718      	bx	r3
}
    4b54:	bd70      	pop	{r4, r5, r6, pc}
    4b56:	bf00      	nop
    4b58:	5000a000 	.word	0x5000a000
    4b5c:	20000a00 	.word	0x20000a00

00004b60 <z_device_is_ready>:
	*devices = __device_start;
	return __device_end - __device_start;
}

bool z_device_is_ready(const struct device *dev)
{
    4b60:	b510      	push	{r4, lr}
	/*
	 * if an invalid device pointer is passed as argument, this call
	 * reports the `device` as not ready for usage.
	 */
	if (dev == NULL) {
    4b62:	4604      	mov	r4, r0
    4b64:	b920      	cbnz	r0, 4b70 <z_device_is_ready+0x10>
		printk("device_is_ready: invalid device pointer\n");
    4b66:	4814      	ldr	r0, [pc, #80]	; (4bb8 <z_device_is_ready+0x58>)
    4b68:	f001 f93f 	bl	5dea <printk>
		return false;
    4b6c:	4620      	mov	r0, r4
	else if (dev->state->init_res != 0) {
        printk("Device initialization failed: error code %d\n", dev->state->init_res);
    }
	
	return dev->state->initialized && (dev->state->init_res == 0U);
}
    4b6e:	bd10      	pop	{r4, pc}
	printk("device_is_ready: %s\n", dev->name);
    4b70:	6801      	ldr	r1, [r0, #0]
    4b72:	4812      	ldr	r0, [pc, #72]	; (4bbc <z_device_is_ready+0x5c>)
    4b74:	f001 f939 	bl	5dea <printk>
	printk("device_is_ready: initialized=%d, init_res=%d\n", dev->state->initialized, dev->state->init_res);
    4b78:	68e3      	ldr	r3, [r4, #12]
    4b7a:	4811      	ldr	r0, [pc, #68]	; (4bc0 <z_device_is_ready+0x60>)
    4b7c:	7859      	ldrb	r1, [r3, #1]
    4b7e:	781a      	ldrb	r2, [r3, #0]
    4b80:	f001 0101 	and.w	r1, r1, #1
    4b84:	f001 f931 	bl	5dea <printk>
	if (dev->state->init_res == 19) {
    4b88:	68e3      	ldr	r3, [r4, #12]
    4b8a:	7819      	ldrb	r1, [r3, #0]
    4b8c:	2913      	cmp	r1, #19
    4b8e:	d10c      	bne.n	4baa <z_device_is_ready+0x4a>
    	printk("Device initialization failed: No such device\n");
    4b90:	480c      	ldr	r0, [pc, #48]	; (4bc4 <z_device_is_ready+0x64>)
    4b92:	f001 f92a 	bl	5dea <printk>
	return dev->state->initialized && (dev->state->init_res == 0U);
    4b96:	68e3      	ldr	r3, [r4, #12]
    4b98:	7858      	ldrb	r0, [r3, #1]
    4b9a:	f010 0001 	ands.w	r0, r0, #1
    4b9e:	bf1e      	ittt	ne
    4ba0:	7818      	ldrbne	r0, [r3, #0]
    4ba2:	fab0 f080 	clzne	r0, r0
    4ba6:	0940      	lsrne	r0, r0, #5
    4ba8:	e7e1      	b.n	4b6e <z_device_is_ready+0xe>
	else if (dev->state->init_res != 0) {
    4baa:	2900      	cmp	r1, #0
    4bac:	d0f3      	beq.n	4b96 <z_device_is_ready+0x36>
        printk("Device initialization failed: error code %d\n", dev->state->init_res);
    4bae:	4806      	ldr	r0, [pc, #24]	; (4bc8 <z_device_is_ready+0x68>)
    4bb0:	f001 f91b 	bl	5dea <printk>
    4bb4:	e7ef      	b.n	4b96 <z_device_is_ready+0x36>
    4bb6:	bf00      	nop
    4bb8:	000078db 	.word	0x000078db
    4bbc:	00007904 	.word	0x00007904
    4bc0:	00007919 	.word	0x00007919
    4bc4:	00007947 	.word	0x00007947
    4bc8:	00007975 	.word	0x00007975

00004bcc <z_sys_init_run_level>:
		/* End marker */
		__init_end,
	};
	const struct init_entry *entry;

	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    4bcc:	4b0f      	ldr	r3, [pc, #60]	; (4c0c <z_sys_init_run_level+0x40>)
{
    4bce:	b570      	push	{r4, r5, r6, lr}
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    4bd0:	f853 4020 	ldr.w	r4, [r3, r0, lsl #2]
    4bd4:	3001      	adds	r0, #1
    4bd6:	f853 6020 	ldr.w	r6, [r3, r0, lsl #2]
    4bda:	42a6      	cmp	r6, r4
    4bdc:	d800      	bhi.n	4be0 <z_sys_init_run_level+0x14>
				dev->state->init_res = rc;
			}
			dev->state->initialized = true;
		}
	}
}
    4bde:	bd70      	pop	{r4, r5, r6, pc}
		int rc = entry->init(dev);
    4be0:	e9d4 3500 	ldrd	r3, r5, [r4]
    4be4:	4628      	mov	r0, r5
    4be6:	4798      	blx	r3
		if (dev != NULL) {
    4be8:	b16d      	cbz	r5, 4c06 <z_sys_init_run_level+0x3a>
			if (rc != 0) {
    4bea:	b138      	cbz	r0, 4bfc <z_sys_init_run_level+0x30>
				if (rc < 0) {
    4bec:	2800      	cmp	r0, #0
    4bee:	bfb8      	it	lt
    4bf0:	4240      	neglt	r0, r0
				if (rc > UINT8_MAX) {
    4bf2:	28ff      	cmp	r0, #255	; 0xff
    4bf4:	bfa8      	it	ge
    4bf6:	20ff      	movge	r0, #255	; 0xff
				dev->state->init_res = rc;
    4bf8:	68eb      	ldr	r3, [r5, #12]
    4bfa:	7018      	strb	r0, [r3, #0]
			dev->state->initialized = true;
    4bfc:	68ea      	ldr	r2, [r5, #12]
    4bfe:	7853      	ldrb	r3, [r2, #1]
    4c00:	f043 0301 	orr.w	r3, r3, #1
    4c04:	7053      	strb	r3, [r2, #1]
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    4c06:	3408      	adds	r4, #8
    4c08:	e7e7      	b.n	4bda <z_sys_init_run_level+0xe>
    4c0a:	bf00      	nop
    4c0c:	000074bc 	.word	0x000074bc

00004c10 <bg_thread_main>:
	 * may perform memory management tasks (except for z_phys_map() which
	 * is allowed at any time)
	 */
	z_mem_manage_init();
#endif /* CONFIG_MMU */
	z_sys_post_kernel = true;
    4c10:	2201      	movs	r2, #1
{
    4c12:	b508      	push	{r3, lr}
	z_sys_post_kernel = true;
    4c14:	4b09      	ldr	r3, [pc, #36]	; (4c3c <bg_thread_main+0x2c>)

	z_sys_init_run_level(INIT_LEVEL_POST_KERNEL);
    4c16:	2003      	movs	r0, #3
	z_sys_post_kernel = true;
    4c18:	701a      	strb	r2, [r3, #0]
	z_sys_init_run_level(INIT_LEVEL_POST_KERNEL);
    4c1a:	f7ff ffd7 	bl	4bcc <z_sys_init_run_level>
#if CONFIG_STACK_POINTER_RANDOM
	z_stack_adjust_initialized = 1;
#endif
	boot_banner();
    4c1e:	f000 ff49 	bl	5ab4 <boot_banner>
	void z_cpp_init_static(void);
	z_cpp_init_static();
#endif

	/* Final init level before app starts */
	z_sys_init_run_level(INIT_LEVEL_APPLICATION);
    4c22:	2004      	movs	r0, #4
    4c24:	f7ff ffd2 	bl	4bcc <z_sys_init_run_level>

	z_init_static_threads();
    4c28:	f000 f92a 	bl	4e80 <z_init_static_threads>
	extern int main(void);
#else
	extern void main(void);
#endif

	(void)main();
    4c2c:	f7fb fbfa 	bl	424 <main>

	/* Mark nonessential since main() has no more work to do */
	z_main_thread.base.user_options &= ~K_ESSENTIAL;
    4c30:	4a03      	ldr	r2, [pc, #12]	; (4c40 <bg_thread_main+0x30>)
    4c32:	7b13      	ldrb	r3, [r2, #12]
    4c34:	f023 0301 	bic.w	r3, r3, #1
    4c38:	7313      	strb	r3, [r2, #12]

#ifdef CONFIG_COVERAGE_DUMP
	/* Dump coverage data once the main() has exited. */
	gcov_coverage_dump();
#endif
} /* LCOV_EXCL_LINE ... because we just dumped final coverage data */
    4c3a:	bd08      	pop	{r3, pc}
    4c3c:	20000c3f 	.word	0x20000c3f
    4c40:	200002e0 	.word	0x200002e0

00004c44 <z_bss_zero>:
{
    4c44:	b508      	push	{r3, lr}
	z_early_memset(__bss_start, 0, __bss_end - __bss_start);
    4c46:	4803      	ldr	r0, [pc, #12]	; (4c54 <z_bss_zero+0x10>)
    4c48:	4a03      	ldr	r2, [pc, #12]	; (4c58 <z_bss_zero+0x14>)
    4c4a:	2100      	movs	r1, #0
    4c4c:	1a12      	subs	r2, r2, r0
    4c4e:	f001 ffc6 	bl	6bde <z_early_memset>
}
    4c52:	bd08      	pop	{r3, pc}
    4c54:	20000240 	.word	0x20000240
    4c58:	20000c40 	.word	0x20000c40

00004c5c <z_init_cpu>:

#else
	char *tname = NULL;
#endif /* CONFIG_THREAD_NAME */

	z_setup_new_thread(thread, stack,
    4c5c:	2300      	movs	r3, #0
    4c5e:	2201      	movs	r2, #1
	thread->base.is_idle = 1U;
#endif
}

void z_init_cpu(int id)
{
    4c60:	b570      	push	{r4, r5, r6, lr}
    4c62:	b086      	sub	sp, #24
	z_setup_new_thread(thread, stack,
    4c64:	e9cd 2304 	strd	r2, r3, [sp, #16]
    4c68:	220f      	movs	r2, #15
    4c6a:	9301      	str	r3, [sp, #4]
    4c6c:	e9cd 3202 	strd	r3, r2, [sp, #8]
			  CONFIG_IDLE_STACK_SIZE, idle, &_kernel.cpus[i],
    4c70:	2318      	movs	r3, #24
	z_setup_new_thread(thread, stack,
    4c72:	f44f 72a0 	mov.w	r2, #320	; 0x140
			  CONFIG_IDLE_STACK_SIZE, idle, &_kernel.cpus[i],
    4c76:	4d0e      	ldr	r5, [pc, #56]	; (4cb0 <z_init_cpu+0x54>)
	struct k_thread *thread = &z_idle_threads[i];
    4c78:	4e0e      	ldr	r6, [pc, #56]	; (4cb4 <z_init_cpu+0x58>)
			  CONFIG_IDLE_STACK_SIZE, idle, &_kernel.cpus[i],
    4c7a:	fb03 5500 	mla	r5, r3, r0, r5
	z_setup_new_thread(thread, stack,
    4c7e:	490e      	ldr	r1, [pc, #56]	; (4cb8 <z_init_cpu+0x5c>)
	struct k_thread *thread = &z_idle_threads[i];
    4c80:	eb06 16c0 	add.w	r6, r6, r0, lsl #7
{
    4c84:	4604      	mov	r4, r0
	z_setup_new_thread(thread, stack,
    4c86:	fb02 1100 	mla	r1, r2, r0, r1
    4c8a:	4b0c      	ldr	r3, [pc, #48]	; (4cbc <z_init_cpu+0x60>)
    4c8c:	4630      	mov	r0, r6
    4c8e:	9500      	str	r5, [sp, #0]
    4c90:	f000 f8c6 	bl	4e20 <z_setup_new_thread>
	SYS_PORT_TRACING_FUNC(k_thread, sched_resume, thread);
}

static inline void z_mark_thread_as_started(struct k_thread *thread)
{
	thread->base.thread_state &= ~_THREAD_PRESTART;
    4c94:	7b73      	ldrb	r3, [r6, #13]
	init_idle_thread(id);
	_kernel.cpus[id].idle_thread = &z_idle_threads[id];
	_kernel.cpus[id].id = id;
    4c96:	752c      	strb	r4, [r5, #20]
    4c98:	f023 0304 	bic.w	r3, r3, #4
    4c9c:	7373      	strb	r3, [r6, #13]
	_kernel.cpus[id].irq_stack =
		(Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[id]) +
    4c9e:	4b08      	ldr	r3, [pc, #32]	; (4cc0 <z_init_cpu+0x64>)
    4ca0:	3401      	adds	r4, #1
    4ca2:	eb03 23c4 	add.w	r3, r3, r4, lsl #11
	_kernel.cpus[id].idle_thread = &z_idle_threads[id];
    4ca6:	60ee      	str	r6, [r5, #12]
	_kernel.cpus[id].irq_stack =
    4ca8:	606b      	str	r3, [r5, #4]
		 K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[id]));
#ifdef CONFIG_SCHED_THREAD_USAGE_ALL
	_kernel.cpus[id].usage.track_usage =
		CONFIG_SCHED_THREAD_USAGE_AUTO_ENABLE;
#endif
}
    4caa:	b006      	add	sp, #24
    4cac:	bd70      	pop	{r4, r5, r6, pc}
    4cae:	bf00      	nop
    4cb0:	20000a20 	.word	0x20000a20
    4cb4:	20000260 	.word	0x20000260
    4cb8:	20001440 	.word	0x20001440
    4cbc:	00004f39 	.word	0x00004f39
    4cc0:	20000c40 	.word	0x20000c40

00004cc4 <z_cstart>:
 *
 * @return Does not return
 */
__boot_func
FUNC_NORETURN void z_cstart(void)
{
    4cc4:	b580      	push	{r7, lr}
	/* gcov hook needed to get the coverage report.*/
	gcov_static_init();

	/* initialize early init calls */
	z_sys_init_run_level(INIT_LEVEL_EARLY);
    4cc6:	2000      	movs	r0, #0
{
    4cc8:	b0a6      	sub	sp, #152	; 0x98
	z_sys_init_run_level(INIT_LEVEL_EARLY);
    4cca:	f7ff ff7f 	bl	4bcc <z_sys_init_run_level>
 *
 */
static ALWAYS_INLINE void z_arm_interrupt_stack_setup(void)
{
	uint32_t msp =
		(uint32_t)(Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[0])) +
    4cce:	4b2d      	ldr	r3, [pc, #180]	; (4d84 <z_cstart+0xc0>)
	uint32_t msp =
    4cd0:	f503 6200 	add.w	r2, r3, #2048	; 0x800
  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
    4cd4:	f382 8808 	msr	MSP, r2
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
  // without main extensions, the non-secure MSPLIM is RAZ/WI
  (void)MainStackPtrLimit;
#else
  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
    4cd8:	f383 880a 	msr	MSPLIM, r3
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    4cdc:	2400      	movs	r4, #0
    4cde:	23e0      	movs	r3, #224	; 0xe0
    4ce0:	4d29      	ldr	r5, [pc, #164]	; (4d88 <z_cstart+0xc4>)

#ifdef CONFIG_TIMESLICE_PER_THREAD
	dummy_thread->base.slice_ticks = 0;
#endif

	_current_cpu->current = dummy_thread;
    4ce2:	4e2a      	ldr	r6, [pc, #168]	; (4d8c <z_cstart+0xc8>)
    4ce4:	f885 3022 	strb.w	r3, [r5, #34]	; 0x22
    4ce8:	77ec      	strb	r4, [r5, #31]
    4cea:	762c      	strb	r4, [r5, #24]
    4cec:	766c      	strb	r4, [r5, #25]
    4cee:	76ac      	strb	r4, [r5, #26]
    4cf0:	f885 4020 	strb.w	r4, [r5, #32]
#if defined(CONFIG_ARM_SECURE_FIRMWARE)
	NVIC_SetPriority(SecureFault_IRQn, _EXC_FAULT_PRIO);
#endif /* CONFIG_ARM_SECURE_FIRMWARE */

	/* Enable Usage, Mem, & Bus Faults */
	SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk |
    4cf4:	6a6b      	ldr	r3, [r5, #36]	; 0x24
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    4cf6:	4f26      	ldr	r7, [pc, #152]	; (4d90 <z_cstart+0xcc>)
    4cf8:	f443 23e0 	orr.w	r3, r3, #458752	; 0x70000
    4cfc:	626b      	str	r3, [r5, #36]	; 0x24
    4cfe:	f885 4023 	strb.w	r4, [r5, #35]	; 0x23

static ALWAYS_INLINE void arch_kernel_init(void)
{
	z_arm_interrupt_stack_setup();
	z_arm_exc_setup();
	z_arm_fault_init();
    4d02:	f7fc fe3f 	bl	1984 <z_arm_fault_init>
	z_arm_cpu_idle_init();
    4d06:	f7fc fc11 	bl	152c <z_arm_cpu_idle_init>
static ALWAYS_INLINE void z_arm_clear_faults(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* Reset all faults */
	SCB->CFSR = SCB_CFSR_USGFAULTSR_Msk |
    4d0a:	f04f 33ff 	mov.w	r3, #4294967295
    4d0e:	62ab      	str	r3, [r5, #40]	; 0x28
		    SCB_CFSR_MEMFAULTSR_Msk |
		    SCB_CFSR_BUSFAULTSR_Msk;

	/* Clear all Hard Faults - HFSR is write-one-to-clear */
	SCB->HFSR = 0xffffffff;
    4d10:	62eb      	str	r3, [r5, #44]	; 0x2c
	z_arm_clear_faults();
#if defined(CONFIG_ARM_MPU)
	z_arm_mpu_init();
    4d12:	f7fd f841 	bl	1d98 <z_arm_mpu_init>
	 * to set up access permissions for fixed memory sections, such
	 * as Application Memory or No-Cacheable SRAM area.
	 *
	 * This function is invoked once, upon system initialization.
	 */
	z_arm_configure_static_mpu_regions();
    4d16:	f7fc fee7 	bl	1ae8 <z_arm_configure_static_mpu_regions>
	dummy_thread->base.user_options = K_ESSENTIAL;
    4d1a:	f240 1301 	movw	r3, #257	; 0x101
    4d1e:	f8ad 3024 	strh.w	r3, [sp, #36]	; 0x24
	_current_cpu->current = dummy_thread;
    4d22:	ab06      	add	r3, sp, #24
    4d24:	60b3      	str	r3, [r6, #8]
	dummy_thread->stack_info.size = 0U;
    4d26:	e9cd 441f 	strd	r4, r4, [sp, #124]	; 0x7c
	dummy_thread->resource_pool = NULL;
    4d2a:	9422      	str	r4, [sp, #136]	; 0x88
	struct k_thread dummy_thread;

	z_dummy_thread_init(&dummy_thread);
#endif
	/* do any necessary initialization of static devices */
	z_device_state_init();
    4d2c:	f001 ff3b 	bl	6ba6 <z_device_state_init>

	/* perform basic hardware initialization */
	z_sys_init_run_level(INIT_LEVEL_PRE_KERNEL_1);
    4d30:	2001      	movs	r0, #1
    4d32:	f7ff ff4b 	bl	4bcc <z_sys_init_run_level>
	z_sys_init_run_level(INIT_LEVEL_PRE_KERNEL_2);
    4d36:	2002      	movs	r0, #2
	_kernel.ready_q.cache = &z_main_thread;
    4d38:	4d16      	ldr	r5, [pc, #88]	; (4d94 <z_cstart+0xd0>)
	z_sys_init_run_level(INIT_LEVEL_PRE_KERNEL_2);
    4d3a:	f7ff ff47 	bl	4bcc <z_sys_init_run_level>
	z_sched_init();
    4d3e:	f000 fc4f 	bl	55e0 <z_sched_init>
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    4d42:	4b15      	ldr	r3, [pc, #84]	; (4d98 <z_cstart+0xd4>)
	_kernel.ready_q.cache = &z_main_thread;
    4d44:	61f5      	str	r5, [r6, #28]
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    4d46:	9305      	str	r3, [sp, #20]
    4d48:	2301      	movs	r3, #1
    4d4a:	4914      	ldr	r1, [pc, #80]	; (4d9c <z_cstart+0xd8>)
    4d4c:	f44f 6280 	mov.w	r2, #1024	; 0x400
    4d50:	e9cd 4303 	strd	r4, r3, [sp, #12]
    4d54:	4628      	mov	r0, r5
    4d56:	463b      	mov	r3, r7
    4d58:	e9cd 4401 	strd	r4, r4, [sp, #4]
    4d5c:	9400      	str	r4, [sp, #0]
    4d5e:	f000 f85f 	bl	4e20 <z_setup_new_thread>
    4d62:	4606      	mov	r6, r0
    4d64:	7b6a      	ldrb	r2, [r5, #13]
	z_ready_thread(&z_main_thread);
    4d66:	4628      	mov	r0, r5
    4d68:	f022 0204 	bic.w	r2, r2, #4
    4d6c:	736a      	strb	r2, [r5, #13]
    4d6e:	f002 f80b 	bl	6d88 <z_ready_thread>
	z_init_cpu(0);
    4d72:	4620      	mov	r0, r4
    4d74:	f7ff ff72 	bl	4c5c <z_init_cpu>
	arch_switch_to_main_thread(&z_main_thread, stack_ptr, bg_thread_main);
    4d78:	463a      	mov	r2, r7
    4d7a:	4631      	mov	r1, r6
    4d7c:	4628      	mov	r0, r5
    4d7e:	f7fc fcd9 	bl	1734 <arch_switch_to_main_thread>
	CODE_UNREACHABLE; /* LCOV_EXCL_LINE */
    4d82:	bf00      	nop
    4d84:	20000c40 	.word	0x20000c40
    4d88:	e000ed00 	.word	0xe000ed00
    4d8c:	20000a20 	.word	0x20000a20
    4d90:	00004c11 	.word	0x00004c11
    4d94:	200002e0 	.word	0x200002e0
    4d98:	000079a2 	.word	0x000079a2
    4d9c:	20001580 	.word	0x20001580

00004da0 <init_mem_slab_module>:
 *
 * @return 0 on success, fails otherwise.
 */
static int init_mem_slab_module(const struct device *dev)
{
	int rc = 0;
    4da0:	2000      	movs	r0, #0
{
    4da2:	b538      	push	{r3, r4, r5, lr}
	ARG_UNUSED(dev);

	STRUCT_SECTION_FOREACH(k_mem_slab, slab) {
    4da4:	4c05      	ldr	r4, [pc, #20]	; (4dbc <init_mem_slab_module+0x1c>)
    4da6:	4d06      	ldr	r5, [pc, #24]	; (4dc0 <init_mem_slab_module+0x20>)
    4da8:	42ac      	cmp	r4, r5
    4daa:	d300      	bcc.n	4dae <init_mem_slab_module+0xe>
		z_object_init(slab);
	}

out:
	return rc;
}
    4dac:	bd38      	pop	{r3, r4, r5, pc}
		rc = create_free_list(slab);
    4dae:	4620      	mov	r0, r4
    4db0:	f001 ff19 	bl	6be6 <create_free_list>
		if (rc < 0) {
    4db4:	2800      	cmp	r0, #0
    4db6:	dbf9      	blt.n	4dac <init_mem_slab_module+0xc>
	STRUCT_SECTION_FOREACH(k_mem_slab, slab) {
    4db8:	341c      	adds	r4, #28
    4dba:	e7f5      	b.n	4da8 <init_mem_slab_module+0x8>
    4dbc:	200001ea 	.word	0x200001ea
    4dc0:	200001ea 	.word	0x200001ea

00004dc4 <k_mem_slab_alloc>:

	return rc;
}

int k_mem_slab_alloc(struct k_mem_slab *slab, void **mem, k_timeout_t timeout)
{
    4dc4:	b573      	push	{r0, r1, r4, r5, r6, lr}
    4dc6:	460c      	mov	r4, r1
	__asm__ volatile(
    4dc8:	f04f 0520 	mov.w	r5, #32
    4dcc:	f3ef 8111 	mrs	r1, BASEPRI
    4dd0:	f385 8812 	msr	BASEPRI_MAX, r5
    4dd4:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&slab->lock);
	int result;

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_mem_slab, alloc, slab, timeout);

	if (slab->free_list != NULL) {
    4dd8:	6945      	ldr	r5, [r0, #20]
    4dda:	b15d      	cbz	r5, 4df4 <k_mem_slab_alloc+0x30>
		/* take a free block */
		*mem = slab->free_list;
    4ddc:	6025      	str	r5, [r4, #0]
		slab->free_list = *(char **)(slab->free_list);
    4dde:	682b      	ldr	r3, [r5, #0]
    4de0:	6143      	str	r3, [r0, #20]
		slab->num_used++;
    4de2:	6983      	ldr	r3, [r0, #24]
    4de4:	3301      	adds	r3, #1
    4de6:	6183      	str	r3, [r0, #24]

#ifdef CONFIG_MEM_SLAB_TRACE_MAX_UTILIZATION
		slab->max_used = MAX(slab->num_used, slab->max_used);
#endif

		result = 0;
    4de8:	2000      	movs	r0, #0
	__asm__ volatile(
    4dea:	f381 8811 	msr	BASEPRI, r1
    4dee:	f3bf 8f6f 	isb	sy

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mem_slab, alloc, slab, timeout, result);

	k_spin_unlock(&slab->lock, key);

	return result;
    4df2:	e011      	b.n	4e18 <k_mem_slab_alloc+0x54>
	} else if (K_TIMEOUT_EQ(timeout, K_NO_WAIT) ||
    4df4:	ea52 0603 	orrs.w	r6, r2, r3
    4df8:	d103      	bne.n	4e02 <k_mem_slab_alloc+0x3e>
		result = -ENOMEM;
    4dfa:	f06f 000b 	mvn.w	r0, #11
		*mem = NULL;
    4dfe:	6025      	str	r5, [r4, #0]
		result = -ENOMEM;
    4e00:	e7f3      	b.n	4dea <k_mem_slab_alloc+0x26>
		result = z_pend_curr(&slab->lock, key, &slab->wait_q, timeout);
    4e02:	e9cd 2300 	strd	r2, r3, [sp]
    4e06:	4602      	mov	r2, r0
    4e08:	3008      	adds	r0, #8
    4e0a:	f000 faf3 	bl	53f4 <z_pend_curr>
		if (result == 0) {
    4e0e:	b918      	cbnz	r0, 4e18 <k_mem_slab_alloc+0x54>
			*mem = _current->base.swap_data;
    4e10:	4b02      	ldr	r3, [pc, #8]	; (4e1c <k_mem_slab_alloc+0x58>)
    4e12:	689b      	ldr	r3, [r3, #8]
    4e14:	695b      	ldr	r3, [r3, #20]
    4e16:	6023      	str	r3, [r4, #0]
}
    4e18:	b002      	add	sp, #8
    4e1a:	bd70      	pop	{r4, r5, r6, pc}
    4e1c:	20000a20 	.word	0x20000a20

00004e20 <z_setup_new_thread>:
char *z_setup_new_thread(struct k_thread *new_thread,
			 k_thread_stack_t *stack, size_t stack_size,
			 k_thread_entry_t entry,
			 void *p1, void *p2, void *p3,
			 int prio, uint32_t options, const char *name)
{
    4e20:	e92d 41ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr}
void z_init_thread_base(struct _thread_base *thread_base, int priority,
		       uint32_t initial_state, unsigned int options)
{
	/* k_q_node is initialized upon first insertion in a list */
	thread_base->pended_on = NULL;
	thread_base->user_options = (uint8_t)options;
    4e24:	9e0e      	ldr	r6, [sp, #56]	; 0x38
	SYS_DLIST_FOR_EACH_CONTAINER(&((wq)->waitq), thread_ptr, \
				     base.qnode_dlist)

static inline void z_waitq_init(_wait_q_t *w)
{
	sys_dlist_init(&w->waitq);
    4e26:	f100 0558 	add.w	r5, r0, #88	; 0x58
    4e2a:	7306      	strb	r6, [r0, #12]
	thread_base->thread_state = (uint8_t)initial_state;
    4e2c:	2604      	movs	r6, #4
 */

static inline void sys_dlist_init(sys_dlist_t *list)
{
	list->head = (sys_dnode_t *)list;
	list->tail = (sys_dnode_t *)list;
    4e2e:	e9c0 5516 	strd	r5, r5, [r0, #88]	; 0x58
	thread_base->pended_on = NULL;
    4e32:	2500      	movs	r5, #0
{
    4e34:	4604      	mov	r4, r0
	thread_base->thread_state = (uint8_t)initial_state;
    4e36:	7346      	strb	r6, [r0, #13]

	thread_base->prio = priority;
    4e38:	9e0d      	ldr	r6, [sp, #52]	; 0x34
 */

static inline void sys_dnode_init(sys_dnode_t *node)
{
	node->next = NULL;
	node->prev = NULL;
    4e3a:	e9c0 5506 	strd	r5, r5, [r0, #24]
    4e3e:	7386      	strb	r6, [r0, #14]
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    4e40:	1dd6      	adds	r6, r2, #7
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    4e42:	9a0c      	ldr	r2, [sp, #48]	; 0x30
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    4e44:	f026 0607 	bic.w	r6, r6, #7
	new_thread->stack_info.size = stack_buf_size;
    4e48:	e9c0 1619 	strd	r1, r6, [r0, #100]	; 0x64
	thread_base->pended_on = NULL;
    4e4c:	6085      	str	r5, [r0, #8]

	thread_base->sched_locked = 0U;
    4e4e:	73c5      	strb	r5, [r0, #15]
	new_thread->stack_info.delta = delta;
    4e50:	66c5      	str	r5, [r0, #108]	; 0x6c
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    4e52:	9202      	str	r2, [sp, #8]
    4e54:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
	stack_ptr = (char *)stack + stack_obj_size;
    4e56:	eb01 0806 	add.w	r8, r1, r6
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    4e5a:	9201      	str	r2, [sp, #4]
    4e5c:	9a0a      	ldr	r2, [sp, #40]	; 0x28
    4e5e:	9200      	str	r2, [sp, #0]
    4e60:	4642      	mov	r2, r8
    4e62:	f7fc fc4b 	bl	16fc <arch_new_thread>
	if (!_current) {
    4e66:	4b05      	ldr	r3, [pc, #20]	; (4e7c <z_setup_new_thread+0x5c>)
	new_thread->init_data = NULL;
    4e68:	6565      	str	r5, [r4, #84]	; 0x54
	if (!_current) {
    4e6a:	689b      	ldr	r3, [r3, #8]
    4e6c:	b103      	cbz	r3, 4e70 <z_setup_new_thread+0x50>
	new_thread->resource_pool = _current->resource_pool;
    4e6e:	6f1b      	ldr	r3, [r3, #112]	; 0x70
}
    4e70:	4640      	mov	r0, r8
    4e72:	6723      	str	r3, [r4, #112]	; 0x70
    4e74:	b004      	add	sp, #16
    4e76:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    4e7a:	bf00      	nop
    4e7c:	20000a20 	.word	0x20000a20

00004e80 <z_init_static_threads>:
{
    4e80:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
    4e84:	4c29      	ldr	r4, [pc, #164]	; (4f2c <z_init_static_threads+0xac>)
	_FOREACH_STATIC_THREAD(thread_data) {
    4e86:	4d2a      	ldr	r5, [pc, #168]	; (4f30 <z_init_static_threads+0xb0>)
{
    4e88:	b087      	sub	sp, #28
    4e8a:	4626      	mov	r6, r4
	_FOREACH_STATIC_THREAD(thread_data) {
    4e8c:	42ae      	cmp	r6, r5
    4e8e:	f104 0430 	add.w	r4, r4, #48	; 0x30
    4e92:	d30f      	bcc.n	4eb4 <z_init_static_threads+0x34>
	k_sched_lock();
    4e94:	f000 fb74 	bl	5580 <k_sched_lock>
    4e98:	f44f 4600 	mov.w	r6, #32768	; 0x8000
    4e9c:	f240 37e7 	movw	r7, #999	; 0x3e7
	_FOREACH_STATIC_THREAD(thread_data) {
    4ea0:	4c22      	ldr	r4, [pc, #136]	; (4f2c <z_init_static_threads+0xac>)

extern void z_thread_timeout(struct _timeout *timeout);

static inline void z_add_thread_timeout(struct k_thread *thread, k_timeout_t ticks)
{
	z_add_timeout(&thread->base.timeout, z_thread_timeout, ticks);
    4ea2:	f8df 9090 	ldr.w	r9, [pc, #144]	; 4f34 <z_init_static_threads+0xb4>
    4ea6:	42ac      	cmp	r4, r5
    4ea8:	d320      	bcc.n	4eec <z_init_static_threads+0x6c>
}
    4eaa:	b007      	add	sp, #28
    4eac:	e8bd 43f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, lr}
	k_sched_unlock();
    4eb0:	f000 bb7a 	b.w	55a8 <k_sched_unlock>
		z_setup_new_thread(
    4eb4:	f854 3c04 	ldr.w	r3, [r4, #-4]
    4eb8:	9305      	str	r3, [sp, #20]
    4eba:	f854 3c10 	ldr.w	r3, [r4, #-16]
    4ebe:	9304      	str	r3, [sp, #16]
    4ec0:	f854 3c14 	ldr.w	r3, [r4, #-20]
    4ec4:	9303      	str	r3, [sp, #12]
    4ec6:	f854 3c18 	ldr.w	r3, [r4, #-24]
    4eca:	9302      	str	r3, [sp, #8]
    4ecc:	f854 3c1c 	ldr.w	r3, [r4, #-28]
    4ed0:	9301      	str	r3, [sp, #4]
    4ed2:	f854 3c20 	ldr.w	r3, [r4, #-32]
    4ed6:	9300      	str	r3, [sp, #0]
    4ed8:	e954 230a 	ldrd	r2, r3, [r4, #-40]	; 0x28
    4edc:	e954 010c 	ldrd	r0, r1, [r4, #-48]	; 0x30
    4ee0:	f7ff ff9e 	bl	4e20 <z_setup_new_thread>
		thread_data->init_thread->init_data = thread_data;
    4ee4:	f854 3c30 	ldr.w	r3, [r4, #-48]
    4ee8:	655e      	str	r6, [r3, #84]	; 0x54
	_FOREACH_STATIC_THREAD(thread_data) {
    4eea:	e7ce      	b.n	4e8a <z_init_static_threads+0xa>
		if (thread_data->init_delay != K_TICKS_FOREVER) {
    4eec:	6a63      	ldr	r3, [r4, #36]	; 0x24
    4eee:	1c5a      	adds	r2, r3, #1
    4ef0:	d00d      	beq.n	4f0e <z_init_static_threads+0x8e>
    4ef2:	2100      	movs	r1, #0
    4ef4:	4638      	mov	r0, r7
					    K_MSEC(thread_data->init_delay));
    4ef6:	ea23 73e3 	bic.w	r3, r3, r3, asr #31
    4efa:	fbc3 0106 	smlal	r0, r1, r3, r6
	if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) {
    4efe:	ea51 33c3 	orrs.w	r3, r1, r3, lsl #15
			schedule_new_thread(thread_data->init_thread,
    4f02:	f8d4 8000 	ldr.w	r8, [r4]
	if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) {
    4f06:	d104      	bne.n	4f12 <z_init_static_threads+0x92>
	z_sched_start(thread);
    4f08:	4640      	mov	r0, r8
    4f0a:	f000 fae9 	bl	54e0 <z_sched_start>
	_FOREACH_STATIC_THREAD(thread_data) {
    4f0e:	3430      	adds	r4, #48	; 0x30
    4f10:	e7c9      	b.n	4ea6 <z_init_static_threads+0x26>
    4f12:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    4f16:	2300      	movs	r3, #0
    4f18:	f7fb f91c 	bl	154 <__aeabi_uldivmod>
    4f1c:	4602      	mov	r2, r0
    4f1e:	460b      	mov	r3, r1
    4f20:	f108 0018 	add.w	r0, r8, #24
    4f24:	4649      	mov	r1, r9
    4f26:	f000 fcd1 	bl	58cc <z_add_timeout>
    4f2a:	e7f0      	b.n	4f0e <z_init_static_threads+0x8e>
    4f2c:	000071e0 	.word	0x000071e0
    4f30:	000071e0 	.word	0x000071e0
    4f34:	00006cf5 	.word	0x00006cf5

00004f38 <idle>:
#endif	/* CONFIG_PM */
	sys_clock_idle_exit();
}

void idle(void *unused1, void *unused2, void *unused3)
{
    4f38:	b508      	push	{r3, lr}
		 * higher level construct.
		 */
		(void) arch_irq_lock();

#ifdef CONFIG_PM
		_kernel.idle = z_get_next_timeout_expiry();
    4f3a:	4c0b      	ldr	r4, [pc, #44]	; (4f68 <idle+0x30>)
	return !z_sys_post_kernel;
    4f3c:	4d0b      	ldr	r5, [pc, #44]	; (4f6c <idle+0x34>)
	__asm__ volatile(
    4f3e:	f04f 0220 	mov.w	r2, #32
    4f42:	f3ef 8311 	mrs	r3, BASEPRI
    4f46:	f382 8812 	msr	BASEPRI_MAX, r2
    4f4a:	f3bf 8f6f 	isb	sy
    4f4e:	f001 ff73 	bl	6e38 <z_get_next_timeout_expiry>
		 * processing in those cases i.e. skips k_cpu_idle().
		 * The kernel's idle processing re-enables interrupts
		 * which is essential for the kernel's scheduling
		 * logic.
		 */
		if (k_is_pre_kernel() || !pm_system_suspend(_kernel.idle)) {
    4f52:	782b      	ldrb	r3, [r5, #0]
		_kernel.idle = z_get_next_timeout_expiry();
    4f54:	61a0      	str	r0, [r4, #24]
		if (k_is_pre_kernel() || !pm_system_suspend(_kernel.idle)) {
    4f56:	b913      	cbnz	r3, 4f5e <idle+0x26>
	arch_cpu_idle();
    4f58:	f7fc faee 	bl	1538 <arch_cpu_idle>
}
    4f5c:	e7ef      	b.n	4f3e <idle+0x6>
    4f5e:	f7fc f91f 	bl	11a0 <pm_system_suspend>
    4f62:	2800      	cmp	r0, #0
    4f64:	d1eb      	bne.n	4f3e <idle+0x6>
    4f66:	e7f7      	b.n	4f58 <idle+0x20>
    4f68:	20000a20 	.word	0x20000a20
    4f6c:	20000c3f 	.word	0x20000c3f

00004f70 <z_impl_k_mutex_lock>:
	}
	return false;
}

int z_impl_k_mutex_lock(struct k_mutex *mutex, k_timeout_t timeout)
{
    4f70:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
    4f74:	4604      	mov	r4, r0
    4f76:	4617      	mov	r7, r2
    4f78:	461e      	mov	r6, r3
    4f7a:	f04f 0320 	mov.w	r3, #32
    4f7e:	f3ef 8811 	mrs	r8, BASEPRI
    4f82:	f383 8812 	msr	BASEPRI_MAX, r3
    4f86:	f3bf 8f6f 	isb	sy

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_mutex, lock, mutex, timeout);

	key = k_spin_lock(&lock);

	if (likely((mutex->lock_count == 0U) || (mutex->owner == _current))) {
    4f8a:	68c3      	ldr	r3, [r0, #12]
    4f8c:	4a33      	ldr	r2, [pc, #204]	; (505c <z_impl_k_mutex_lock+0xec>)
    4f8e:	b17b      	cbz	r3, 4fb0 <z_impl_k_mutex_lock+0x40>
    4f90:	6880      	ldr	r0, [r0, #8]
    4f92:	6891      	ldr	r1, [r2, #8]
    4f94:	4288      	cmp	r0, r1
    4f96:	d019      	beq.n	4fcc <z_impl_k_mutex_lock+0x5c>
		SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mutex, lock, mutex, timeout, 0);

		return 0;
	}

	if (unlikely(K_TIMEOUT_EQ(timeout, K_NO_WAIT))) {
    4f98:	ea57 0306 	orrs.w	r3, r7, r6
    4f9c:	d118      	bne.n	4fd0 <z_impl_k_mutex_lock+0x60>
	__asm__ volatile(
    4f9e:	f388 8811 	msr	BASEPRI, r8
    4fa2:	f3bf 8f6f 	isb	sy
		k_spin_unlock(&lock, key);

		SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mutex, lock, mutex, timeout, -EBUSY);

		return -EBUSY;
    4fa6:	f06f 000f 	mvn.w	r0, #15
	}

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mutex, lock, mutex, timeout, -EAGAIN);

	return -EAGAIN;
}
    4faa:	b002      	add	sp, #8
    4fac:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
					_current->base.prio :
    4fb0:	6891      	ldr	r1, [r2, #8]
    4fb2:	f991 100e 	ldrsb.w	r1, [r1, #14]
		mutex->lock_count++;
    4fb6:	3301      	adds	r3, #1
    4fb8:	60e3      	str	r3, [r4, #12]
		mutex->owner = _current;
    4fba:	6893      	ldr	r3, [r2, #8]
		mutex->owner_orig_prio = (mutex->lock_count == 0U) ?
    4fbc:	6121      	str	r1, [r4, #16]
		mutex->owner = _current;
    4fbe:	60a3      	str	r3, [r4, #8]
    4fc0:	f388 8811 	msr	BASEPRI, r8
    4fc4:	f3bf 8f6f 	isb	sy
		return 0;
    4fc8:	2000      	movs	r0, #0
    4fca:	e7ee      	b.n	4faa <z_impl_k_mutex_lock+0x3a>
					_current->base.prio :
    4fcc:	6921      	ldr	r1, [r4, #16]
    4fce:	e7f2      	b.n	4fb6 <z_impl_k_mutex_lock+0x46>
	new_prio = new_prio_for_inheritance(_current->base.prio,
    4fd0:	f991 100e 	ldrsb.w	r1, [r1, #14]
    4fd4:	f990 300e 	ldrsb.w	r3, [r0, #14]
	return prio >= CONFIG_PRIORITY_CEILING;
}

static inline int z_get_new_prio_with_ceiling(int prio)
{
	return z_is_under_prio_ceiling(prio) ? prio : CONFIG_PRIORITY_CEILING;
    4fd8:	f06f 027e 	mvn.w	r2, #126	; 0x7e
    4fdc:	4299      	cmp	r1, r3
    4fde:	bfa8      	it	ge
    4fe0:	4619      	movge	r1, r3
    4fe2:	4291      	cmp	r1, r2
    4fe4:	bfb8      	it	lt
    4fe6:	4611      	movlt	r1, r2
	if (z_is_prio_higher(new_prio, mutex->owner->base.prio)) {
    4fe8:	428b      	cmp	r3, r1
    4fea:	dd2e      	ble.n	504a <z_impl_k_mutex_lock+0xda>
		resched = adjust_owner_prio(mutex, new_prio);
    4fec:	f001 fe55 	bl	6c9a <adjust_owner_prio.isra.0>
    4ff0:	4605      	mov	r5, r0
	int got_mutex = z_pend_curr(&lock, key, &mutex->wait_q, timeout);
    4ff2:	4622      	mov	r2, r4
    4ff4:	4641      	mov	r1, r8
    4ff6:	e9cd 7600 	strd	r7, r6, [sp]
    4ffa:	4819      	ldr	r0, [pc, #100]	; (5060 <z_impl_k_mutex_lock+0xf0>)
    4ffc:	f000 f9fa 	bl	53f4 <z_pend_curr>
	if (got_mutex == 0) {
    5000:	2800      	cmp	r0, #0
    5002:	d0e1      	beq.n	4fc8 <z_impl_k_mutex_lock+0x58>
	__asm__ volatile(
    5004:	f04f 0320 	mov.w	r3, #32
    5008:	f3ef 8611 	mrs	r6, BASEPRI
    500c:	f383 8812 	msr	BASEPRI_MAX, r3
    5010:	f3bf 8f6f 	isb	sy
	if (likely(mutex->owner != NULL)) {
    5014:	68a0      	ldr	r0, [r4, #8]
    5016:	b1d0      	cbz	r0, 504e <z_impl_k_mutex_lock+0xde>
 * @return true if empty, false otherwise
 */

static inline bool sys_dlist_is_empty(sys_dlist_t *list)
{
	return list->head == list;
    5018:	6823      	ldr	r3, [r4, #0]
			new_prio_for_inheritance(waiter->base.prio, mutex->owner_orig_prio) :
    501a:	6921      	ldr	r1, [r4, #16]
 * @return a pointer to the head element, NULL if list is empty
 */

static inline sys_dnode_t *sys_dlist_peek_head(sys_dlist_t *list)
{
	return sys_dlist_is_empty(list) ? NULL : list->head;
    501c:	429c      	cmp	r4, r3
    501e:	d00a      	beq.n	5036 <z_impl_k_mutex_lock+0xc6>
    5020:	b14b      	cbz	r3, 5036 <z_impl_k_mutex_lock+0xc6>
    5022:	f993 300e 	ldrsb.w	r3, [r3, #14]
    5026:	4299      	cmp	r1, r3
    5028:	bfa8      	it	ge
    502a:	4619      	movge	r1, r3
    502c:	f06f 037e 	mvn.w	r3, #126	; 0x7e
    5030:	4299      	cmp	r1, r3
    5032:	bfb8      	it	lt
    5034:	4619      	movlt	r1, r3
		resched = adjust_owner_prio(mutex, new_prio) || resched;
    5036:	f001 fe30 	bl	6c9a <adjust_owner_prio.isra.0>
    503a:	b140      	cbz	r0, 504e <z_impl_k_mutex_lock+0xde>
		z_reschedule(&lock, key);
    503c:	4631      	mov	r1, r6
    503e:	4808      	ldr	r0, [pc, #32]	; (5060 <z_impl_k_mutex_lock+0xf0>)
    5040:	f000 fa3c 	bl	54bc <z_reschedule>
	return -EAGAIN;
    5044:	f06f 000a 	mvn.w	r0, #10
    5048:	e7af      	b.n	4faa <z_impl_k_mutex_lock+0x3a>
	bool resched = false;
    504a:	2500      	movs	r5, #0
    504c:	e7d1      	b.n	4ff2 <z_impl_k_mutex_lock+0x82>
	if (resched) {
    504e:	2d00      	cmp	r5, #0
    5050:	d1f4      	bne.n	503c <z_impl_k_mutex_lock+0xcc>
	__asm__ volatile(
    5052:	f386 8811 	msr	BASEPRI, r6
    5056:	f3bf 8f6f 	isb	sy
    505a:	e7f3      	b.n	5044 <z_impl_k_mutex_lock+0xd4>
    505c:	20000a20 	.word	0x20000a20
    5060:	20000c40 	.word	0x20000c40

00005064 <z_impl_k_mutex_unlock>:
}
#include <syscalls/k_mutex_lock_mrsh.c>
#endif

int z_impl_k_mutex_unlock(struct k_mutex *mutex)
{
    5064:	b538      	push	{r3, r4, r5, lr}

	__ASSERT(!arch_is_in_isr(), "mutexes cannot be used inside ISRs");

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_mutex, unlock, mutex);

	CHECKIF(mutex->owner == NULL) {
    5066:	6883      	ldr	r3, [r0, #8]
{
    5068:	4604      	mov	r4, r0
	CHECKIF(mutex->owner == NULL) {
    506a:	b36b      	cbz	r3, 50c8 <z_impl_k_mutex_unlock+0x64>
		return -EINVAL;
	}
	/*
	 * The current thread does not own the mutex.
	 */
	CHECKIF(mutex->owner != _current) {
    506c:	4a19      	ldr	r2, [pc, #100]	; (50d4 <z_impl_k_mutex_unlock+0x70>)
    506e:	6892      	ldr	r2, [r2, #8]
    5070:	4293      	cmp	r3, r2
    5072:	d12c      	bne.n	50ce <z_impl_k_mutex_unlock+0x6a>

	/*
	 * If we are the owner and count is greater than 1, then decrement
	 * the count and return and keep current thread as the owner.
	 */
	if (mutex->lock_count > 1U) {
    5074:	68c3      	ldr	r3, [r0, #12]
    5076:	2b01      	cmp	r3, #1
    5078:	d903      	bls.n	5082 <z_impl_k_mutex_unlock+0x1e>
		mutex->lock_count--;
    507a:	3b01      	subs	r3, #1
    507c:	60c3      	str	r3, [r0, #12]


k_mutex_unlock_return:
	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mutex, unlock, mutex, 0);

	return 0;
    507e:	2000      	movs	r0, #0
}
    5080:	bd38      	pop	{r3, r4, r5, pc}
	__asm__ volatile(
    5082:	f04f 0320 	mov.w	r3, #32
    5086:	f3ef 8511 	mrs	r5, BASEPRI
    508a:	f383 8812 	msr	BASEPRI_MAX, r3
    508e:	f3bf 8f6f 	isb	sy
	adjust_owner_prio(mutex, mutex->owner_orig_prio);
    5092:	6901      	ldr	r1, [r0, #16]
    5094:	6880      	ldr	r0, [r0, #8]
    5096:	f001 fe00 	bl	6c9a <adjust_owner_prio.isra.0>
	new_owner = z_unpend_first_thread(&mutex->wait_q);
    509a:	4620      	mov	r0, r4
    509c:	f001 fe84 	bl	6da8 <z_unpend_first_thread>
	mutex->owner = new_owner;
    50a0:	60a0      	str	r0, [r4, #8]
	if (new_owner != NULL) {
    50a2:	b158      	cbz	r0, 50bc <z_impl_k_mutex_unlock+0x58>
		mutex->owner_orig_prio = new_owner->base.prio;
    50a4:	f990 200e 	ldrsb.w	r2, [r0, #14]
    50a8:	6122      	str	r2, [r4, #16]
}

static ALWAYS_INLINE void
arch_thread_return_value_set(struct k_thread *thread, unsigned int value)
{
	thread->arch.swap_return_value = value;
    50aa:	2200      	movs	r2, #0
    50ac:	6782      	str	r2, [r0, #120]	; 0x78
		z_ready_thread(new_owner);
    50ae:	f001 fe6b 	bl	6d88 <z_ready_thread>
		z_reschedule(&lock, key);
    50b2:	4629      	mov	r1, r5
    50b4:	4808      	ldr	r0, [pc, #32]	; (50d8 <z_impl_k_mutex_unlock+0x74>)
    50b6:	f000 fa01 	bl	54bc <z_reschedule>
    50ba:	e7e0      	b.n	507e <z_impl_k_mutex_unlock+0x1a>
		mutex->lock_count = 0U;
    50bc:	60e0      	str	r0, [r4, #12]
	__asm__ volatile(
    50be:	f385 8811 	msr	BASEPRI, r5
    50c2:	f3bf 8f6f 	isb	sy
    50c6:	e7da      	b.n	507e <z_impl_k_mutex_unlock+0x1a>
		return -EINVAL;
    50c8:	f06f 0015 	mvn.w	r0, #21
    50cc:	e7d8      	b.n	5080 <z_impl_k_mutex_unlock+0x1c>
		return -EPERM;
    50ce:	f04f 30ff 	mov.w	r0, #4294967295
    50d2:	e7d5      	b.n	5080 <z_impl_k_mutex_unlock+0x1c>
    50d4:	20000a20 	.word	0x20000a20
    50d8:	20000c40 	.word	0x20000c40

000050dc <z_impl_k_sem_give>:
	ARG_UNUSED(sem);
#endif
}

void z_impl_k_sem_give(struct k_sem *sem)
{
    50dc:	b538      	push	{r3, r4, r5, lr}
    50de:	4604      	mov	r4, r0
	__asm__ volatile(
    50e0:	f04f 0320 	mov.w	r3, #32
    50e4:	f3ef 8511 	mrs	r5, BASEPRI
    50e8:	f383 8812 	msr	BASEPRI_MAX, r3
    50ec:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&lock);
	struct k_thread *thread;

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_sem, give, sem);

	thread = z_unpend_first_thread(&sem->wait_q);
    50f0:	f001 fe5a 	bl	6da8 <z_unpend_first_thread>

	if (thread != NULL) {
    50f4:	b148      	cbz	r0, 510a <z_impl_k_sem_give+0x2e>
    50f6:	2200      	movs	r2, #0
    50f8:	6782      	str	r2, [r0, #120]	; 0x78
		arch_thread_return_value_set(thread, 0);
		z_ready_thread(thread);
    50fa:	f001 fe45 	bl	6d88 <z_ready_thread>
	} else {
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
		handle_poll_events(sem);
	}

	z_reschedule(&lock, key);
    50fe:	4629      	mov	r1, r5

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_sem, give, sem);
}
    5100:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
	z_reschedule(&lock, key);
    5104:	4804      	ldr	r0, [pc, #16]	; (5118 <z_impl_k_sem_give+0x3c>)
    5106:	f000 b9d9 	b.w	54bc <z_reschedule>
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
    510a:	e9d4 3202 	ldrd	r3, r2, [r4, #8]
    510e:	429a      	cmp	r2, r3
    5110:	bf18      	it	ne
    5112:	3301      	addne	r3, #1
    5114:	60a3      	str	r3, [r4, #8]
}
    5116:	e7f2      	b.n	50fe <z_impl_k_sem_give+0x22>
    5118:	20000c40 	.word	0x20000c40

0000511c <z_impl_k_sem_take>:
}
#include <syscalls/k_sem_give_mrsh.c>
#endif

int z_impl_k_sem_take(struct k_sem *sem, k_timeout_t timeout)
{
    511c:	b513      	push	{r0, r1, r4, lr}
    511e:	f04f 0420 	mov.w	r4, #32
    5122:	f3ef 8111 	mrs	r1, BASEPRI
    5126:	f384 8812 	msr	BASEPRI_MAX, r4
    512a:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&lock);

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_sem, take, sem, timeout);

	if (likely(sem->count > 0U)) {
    512e:	6884      	ldr	r4, [r0, #8]
    5130:	b144      	cbz	r4, 5144 <z_impl_k_sem_take+0x28>
		sem->count--;
    5132:	3c01      	subs	r4, #1
    5134:	6084      	str	r4, [r0, #8]
	__asm__ volatile(
    5136:	f381 8811 	msr	BASEPRI, r1
    513a:	f3bf 8f6f 	isb	sy
		k_spin_unlock(&lock, key);
		ret = 0;
    513e:	2000      	movs	r0, #0

out:
	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_sem, take, sem, timeout, ret);

	return ret;
}
    5140:	b002      	add	sp, #8
    5142:	bd10      	pop	{r4, pc}
	if (K_TIMEOUT_EQ(timeout, K_NO_WAIT)) {
    5144:	ea52 0403 	orrs.w	r4, r2, r3
    5148:	d106      	bne.n	5158 <z_impl_k_sem_take+0x3c>
    514a:	f381 8811 	msr	BASEPRI, r1
    514e:	f3bf 8f6f 	isb	sy
		ret = -EBUSY;
    5152:	f06f 000f 	mvn.w	r0, #15
    5156:	e7f3      	b.n	5140 <z_impl_k_sem_take+0x24>
	ret = z_pend_curr(&lock, key, &sem->wait_q, timeout);
    5158:	e9cd 2300 	strd	r2, r3, [sp]
    515c:	4602      	mov	r2, r0
    515e:	4802      	ldr	r0, [pc, #8]	; (5168 <z_impl_k_sem_take+0x4c>)
    5160:	f000 f948 	bl	53f4 <z_pend_curr>
	return ret;
    5164:	e7ec      	b.n	5140 <z_impl_k_sem_take+0x24>
    5166:	bf00      	nop
    5168:	20000c40 	.word	0x20000c40

0000516c <z_reset_time_slice>:
 */
static struct k_thread *pending_current;
#endif

void z_reset_time_slice(struct k_thread *curr)
{
    516c:	b538      	push	{r3, r4, r5, lr}
	int ret = slice_ticks;
    516e:	4d07      	ldr	r5, [pc, #28]	; (518c <z_reset_time_slice+0x20>)
    5170:	682c      	ldr	r4, [r5, #0]
	/* Add the elapsed time since the last announced tick to the
	 * slice count, as we'll see those "expired" ticks arrive in a
	 * FUTURE z_time_slice() call.
	 */
	if (slice_time(curr) != 0) {
    5172:	b154      	cbz	r4, 518a <z_reset_time_slice+0x1e>
		_current_cpu->slice_ticks = slice_time(curr) + sys_clock_elapsed();
    5174:	f7fe f9b2 	bl	34dc <sys_clock_elapsed>
    5178:	4b05      	ldr	r3, [pc, #20]	; (5190 <z_reset_time_slice+0x24>)
    517a:	4404      	add	r4, r0
    517c:	611c      	str	r4, [r3, #16]
		z_set_timeout_expiry(slice_time(curr), false);
    517e:	6828      	ldr	r0, [r5, #0]
    5180:	2100      	movs	r1, #0
	}
}
    5182:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
		z_set_timeout_expiry(slice_time(curr), false);
    5186:	f001 be67 	b.w	6e58 <z_set_timeout_expiry>
}
    518a:	bd38      	pop	{r3, r4, r5, pc}
    518c:	20000a50 	.word	0x20000a50
    5190:	20000a20 	.word	0x20000a20

00005194 <update_cache>:
	}
#endif
}

static void update_cache(int preempt_ok)
{
    5194:	b538      	push	{r3, r4, r5, lr}
	return list->head == list;
    5196:	4d0d      	ldr	r5, [pc, #52]	; (51cc <update_cache+0x38>)
    5198:	462b      	mov	r3, r5
    519a:	f853 4f20 	ldr.w	r4, [r3, #32]!
	return sys_dlist_is_empty(list) ? NULL : list->head;
    519e:	429c      	cmp	r4, r3
    51a0:	d000      	beq.n	51a4 <update_cache+0x10>
	return (thread != NULL) ? thread : _current_cpu->idle_thread;
    51a2:	b904      	cbnz	r4, 51a6 <update_cache+0x12>
    51a4:	68ec      	ldr	r4, [r5, #12]
	if (z_is_thread_prevented_from_running(_current)) {
    51a6:	68ab      	ldr	r3, [r5, #8]
	if (preempt_ok != 0) {
    51a8:	b938      	cbnz	r0, 51ba <update_cache+0x26>
	if (z_is_thread_prevented_from_running(_current)) {
    51aa:	7b5a      	ldrb	r2, [r3, #13]
    51ac:	06d2      	lsls	r2, r2, #27
    51ae:	d104      	bne.n	51ba <update_cache+0x26>
	if (IS_ENABLED(CONFIG_SWAP_NONATOMIC)
    51b0:	69a2      	ldr	r2, [r4, #24]
    51b2:	b912      	cbnz	r2, 51ba <update_cache+0x26>
	if (is_preempt(_current) || is_metairq(thread)) {
    51b4:	89da      	ldrh	r2, [r3, #14]
    51b6:	2a7f      	cmp	r2, #127	; 0x7f
    51b8:	d805      	bhi.n	51c6 <update_cache+0x32>
#ifndef CONFIG_SMP
	struct k_thread *thread = next_up();

	if (should_preempt(thread, preempt_ok)) {
#ifdef CONFIG_TIMESLICING
		if (thread != _current) {
    51ba:	429c      	cmp	r4, r3
    51bc:	d002      	beq.n	51c4 <update_cache+0x30>
			z_reset_time_slice(thread);
    51be:	4620      	mov	r0, r4
    51c0:	f7ff ffd4 	bl	516c <z_reset_time_slice>
		}
#endif
		update_metairq_preempt(thread);
		_kernel.ready_q.cache = thread;
    51c4:	4623      	mov	r3, r4
    51c6:	61eb      	str	r3, [r5, #28]
	 * thread because if the thread gets preempted for whatever
	 * reason the scheduler will make the same decision anyway.
	 */
	_current_cpu->swap_ok = preempt_ok;
#endif
}
    51c8:	bd38      	pop	{r3, r4, r5, pc}
    51ca:	bf00      	nop
    51cc:	20000a20 	.word	0x20000a20

000051d0 <move_thread_to_end_of_prio_q>:
{
    51d0:	b570      	push	{r4, r5, r6, lr}
	if (z_is_thread_queued(thread)) {
    51d2:	f990 200d 	ldrsb.w	r2, [r0, #13]
{
    51d6:	4601      	mov	r1, r0
	if (z_is_thread_queued(thread)) {
    51d8:	2a00      	cmp	r2, #0
	return (thread->base.thread_state & state) != 0U;
    51da:	7b43      	ldrb	r3, [r0, #13]
    51dc:	da04      	bge.n	51e8 <move_thread_to_end_of_prio_q+0x18>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    51de:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    51e2:	7343      	strb	r3, [r0, #13]

void z_priq_dumb_remove(sys_dlist_t *pq, struct k_thread *thread)
{
	__ASSERT_NO_MSG(!z_is_idle_thread_object(thread));

	sys_dlist_remove(&thread->base.qnode_dlist);
    51e4:	f001 fd74 	bl	6cd0 <sys_dlist_remove>
	return list->head == list;
    51e8:	4a15      	ldr	r2, [pc, #84]	; (5240 <move_thread_to_end_of_prio_q+0x70>)
	thread->base.thread_state |= _THREAD_QUEUED;
    51ea:	7b4b      	ldrb	r3, [r1, #13]
    51ec:	4610      	mov	r0, r2
    51ee:	f063 037f 	orn	r3, r3, #127	; 0x7f
    51f2:	734b      	strb	r3, [r1, #13]
    51f4:	f850 3f20 	ldr.w	r3, [r0, #32]!
 */

static inline sys_dnode_t *sys_dlist_peek_next_no_check(sys_dlist_t *list,
							sys_dnode_t *node)
{
	return (node == list->tail) ? NULL : node->next;
    51f8:	6a54      	ldr	r4, [r2, #36]	; 0x24
	return sys_dlist_is_empty(list) ? NULL : list->head;
    51fa:	4283      	cmp	r3, r0
    51fc:	bf08      	it	eq
    51fe:	2300      	moveq	r3, #0
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    5200:	b923      	cbnz	r3, 520c <move_thread_to_end_of_prio_q+0x3c>
static inline void sys_dlist_append(sys_dlist_t *list, sys_dnode_t *node)
{
	sys_dnode_t *const tail = list->tail;

	node->next = list;
	node->prev = tail;
    5202:	e9c1 0400 	strd	r0, r4, [r1]

	tail->next = node;
    5206:	6021      	str	r1, [r4, #0]
	list->tail = node;
    5208:	6251      	str	r1, [r2, #36]	; 0x24
}
    520a:	e00c      	b.n	5226 <move_thread_to_end_of_prio_q+0x56>
	int32_t b1 = thread_1->base.prio;
    520c:	f991 500e 	ldrsb.w	r5, [r1, #14]
	int32_t b2 = thread_2->base.prio;
    5210:	f993 600e 	ldrsb.w	r6, [r3, #14]
	if (b1 != b2) {
    5214:	42b5      	cmp	r5, r6
    5216:	d00e      	beq.n	5236 <move_thread_to_end_of_prio_q+0x66>
		if (z_sched_prio_cmp(thread, t) > 0) {
    5218:	42ae      	cmp	r6, r5
    521a:	dd0c      	ble.n	5236 <move_thread_to_end_of_prio_q+0x66>
 * @param successor the position before which "node" will be inserted
 * @param node the element to insert
 */
static inline void sys_dlist_insert(sys_dnode_t *successor, sys_dnode_t *node)
{
	sys_dnode_t *const prev = successor->prev;
    521c:	6858      	ldr	r0, [r3, #4]

	node->prev = prev;
	node->next = successor;
    521e:	e9c1 3000 	strd	r3, r0, [r1]
	prev->next = node;
    5222:	6001      	str	r1, [r0, #0]
	successor->prev = node;
    5224:	6059      	str	r1, [r3, #4]
	update_cache(thread == _current);
    5226:	6890      	ldr	r0, [r2, #8]
}
    5228:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	update_cache(thread == _current);
    522c:	1a43      	subs	r3, r0, r1
    522e:	4258      	negs	r0, r3
    5230:	4158      	adcs	r0, r3
    5232:	f7ff bfaf 	b.w	5194 <update_cache>
	return (node == list->tail) ? NULL : node->next;
    5236:	429c      	cmp	r4, r3
    5238:	d0e3      	beq.n	5202 <move_thread_to_end_of_prio_q+0x32>
    523a:	681b      	ldr	r3, [r3, #0]
    523c:	e7e0      	b.n	5200 <move_thread_to_end_of_prio_q+0x30>
    523e:	bf00      	nop
    5240:	20000a20 	.word	0x20000a20

00005244 <ready_thread>:
{
    5244:	b470      	push	{r4, r5, r6}
	if (!z_is_thread_queued(thread) && z_is_thread_ready(thread)) {
    5246:	f990 300d 	ldrsb.w	r3, [r0, #13]
    524a:	7b42      	ldrb	r2, [r0, #13]
    524c:	2b00      	cmp	r3, #0
    524e:	db29      	blt.n	52a4 <ready_thread+0x60>
	return !((z_is_thread_prevented_from_running(thread)) != 0U ||
    5250:	06d3      	lsls	r3, r2, #27
    5252:	d127      	bne.n	52a4 <ready_thread+0x60>
	return node->next != NULL;
    5254:	6983      	ldr	r3, [r0, #24]
    5256:	bb2b      	cbnz	r3, 52a4 <ready_thread+0x60>
	return list->head == list;
    5258:	4913      	ldr	r1, [pc, #76]	; (52a8 <ready_thread+0x64>)
	thread->base.thread_state |= _THREAD_QUEUED;
    525a:	f062 027f 	orn	r2, r2, #127	; 0x7f
    525e:	7342      	strb	r2, [r0, #13]
    5260:	460a      	mov	r2, r1
    5262:	f852 4f20 	ldr.w	r4, [r2, #32]!
	return sys_dlist_is_empty(list) ? NULL : list->head;
    5266:	4294      	cmp	r4, r2
    5268:	bf18      	it	ne
    526a:	4623      	movne	r3, r4
	return (node == list->tail) ? NULL : node->next;
    526c:	6a4c      	ldr	r4, [r1, #36]	; 0x24
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    526e:	b923      	cbnz	r3, 527a <ready_thread+0x36>
	node->prev = tail;
    5270:	e9c0 2400 	strd	r2, r4, [r0]
	tail->next = node;
    5274:	6020      	str	r0, [r4, #0]
	list->tail = node;
    5276:	6248      	str	r0, [r1, #36]	; 0x24
}
    5278:	e00c      	b.n	5294 <ready_thread+0x50>
	int32_t b1 = thread_1->base.prio;
    527a:	f990 500e 	ldrsb.w	r5, [r0, #14]
	int32_t b2 = thread_2->base.prio;
    527e:	f993 600e 	ldrsb.w	r6, [r3, #14]
	if (b1 != b2) {
    5282:	42b5      	cmp	r5, r6
    5284:	d00a      	beq.n	529c <ready_thread+0x58>
		if (z_sched_prio_cmp(thread, t) > 0) {
    5286:	42ae      	cmp	r6, r5
    5288:	dd08      	ble.n	529c <ready_thread+0x58>
	sys_dnode_t *const prev = successor->prev;
    528a:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
    528c:	e9c0 3200 	strd	r3, r2, [r0]
	prev->next = node;
    5290:	6010      	str	r0, [r2, #0]
	successor->prev = node;
    5292:	6058      	str	r0, [r3, #4]
		update_cache(0);
    5294:	2000      	movs	r0, #0
}
    5296:	bc70      	pop	{r4, r5, r6}
		update_cache(0);
    5298:	f7ff bf7c 	b.w	5194 <update_cache>
	return (node == list->tail) ? NULL : node->next;
    529c:	42a3      	cmp	r3, r4
    529e:	d0e7      	beq.n	5270 <ready_thread+0x2c>
    52a0:	681b      	ldr	r3, [r3, #0]
    52a2:	e7e4      	b.n	526e <ready_thread+0x2a>
}
    52a4:	bc70      	pop	{r4, r5, r6}
    52a6:	4770      	bx	lr
    52a8:	20000a20 	.word	0x20000a20

000052ac <unready_thread>:
{
    52ac:	b508      	push	{r3, lr}
	if (z_is_thread_queued(thread)) {
    52ae:	f990 200d 	ldrsb.w	r2, [r0, #13]
{
    52b2:	4601      	mov	r1, r0
	if (z_is_thread_queued(thread)) {
    52b4:	2a00      	cmp	r2, #0
	return (thread->base.thread_state & state) != 0U;
    52b6:	7b43      	ldrb	r3, [r0, #13]
    52b8:	da04      	bge.n	52c4 <unready_thread+0x18>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    52ba:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    52be:	7343      	strb	r3, [r0, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    52c0:	f001 fd06 	bl	6cd0 <sys_dlist_remove>
	update_cache(thread == _current);
    52c4:	4b04      	ldr	r3, [pc, #16]	; (52d8 <unready_thread+0x2c>)
    52c6:	6898      	ldr	r0, [r3, #8]
    52c8:	1a43      	subs	r3, r0, r1
    52ca:	4258      	negs	r0, r3
    52cc:	4158      	adcs	r0, r3
}
    52ce:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	update_cache(thread == _current);
    52d2:	f7ff bf5f 	b.w	5194 <update_cache>
    52d6:	bf00      	nop
    52d8:	20000a20 	.word	0x20000a20

000052dc <pend_locked>:
{
    52dc:	b570      	push	{r4, r5, r6, lr}
    52de:	4615      	mov	r5, r2
    52e0:	461c      	mov	r4, r3
    52e2:	4606      	mov	r6, r0
	add_to_waitq_locked(thread, wait_q);
    52e4:	f001 fd28 	bl	6d38 <add_to_waitq_locked>
	if (!K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    52e8:	f1b4 3fff 	cmp.w	r4, #4294967295
    52ec:	bf08      	it	eq
    52ee:	f1b5 3fff 	cmpeq.w	r5, #4294967295
    52f2:	d008      	beq.n	5306 <pend_locked+0x2a>
    52f4:	462a      	mov	r2, r5
    52f6:	4623      	mov	r3, r4
    52f8:	f106 0018 	add.w	r0, r6, #24
    52fc:	4902      	ldr	r1, [pc, #8]	; (5308 <pend_locked+0x2c>)
}
    52fe:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    5302:	f000 bae3 	b.w	58cc <z_add_timeout>
    5306:	bd70      	pop	{r4, r5, r6, pc}
    5308:	00006cf5 	.word	0x00006cf5

0000530c <k_sched_time_slice_set>:
{
    530c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    530e:	4604      	mov	r4, r0
    5310:	460d      	mov	r5, r1
	__asm__ volatile(
    5312:	f04f 0320 	mov.w	r3, #32
    5316:	f3ef 8711 	mrs	r7, BASEPRI
    531a:	f383 8812 	msr	BASEPRI_MAX, r3
    531e:	f3bf 8f6f 	isb	sy
			return (uint32_t)((t * to_hz + off) / from_hz);
    5322:	2600      	movs	r6, #0
    5324:	f44f 4c00 	mov.w	ip, #32768	; 0x8000
    5328:	f240 30e7 	movw	r0, #999	; 0x3e7
    532c:	4631      	mov	r1, r6
    532e:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    5332:	2300      	movs	r3, #0
    5334:	fbe4 010c 	umlal	r0, r1, r4, ip
    5338:	f7fa ff0c 	bl	154 <__aeabi_uldivmod>
		if (IS_ENABLED(CONFIG_TICKLESS_KERNEL) && slice > 0) {
    533c:	42b4      	cmp	r4, r6
    533e:	dd02      	ble.n	5346 <k_sched_time_slice_set+0x3a>
			slice_ticks = MAX(2, slice_ticks);
    5340:	2802      	cmp	r0, #2
    5342:	bfb8      	it	lt
    5344:	2002      	movlt	r0, #2
		slice_ticks = k_ms_to_ticks_ceil32(slice);
    5346:	4a07      	ldr	r2, [pc, #28]	; (5364 <k_sched_time_slice_set+0x58>)
		_current_cpu->slice_ticks = 0;
    5348:	4b07      	ldr	r3, [pc, #28]	; (5368 <k_sched_time_slice_set+0x5c>)
		slice_ticks = k_ms_to_ticks_ceil32(slice);
    534a:	6010      	str	r0, [r2, #0]
		slice_max_prio = prio;
    534c:	4a07      	ldr	r2, [pc, #28]	; (536c <k_sched_time_slice_set+0x60>)
		z_reset_time_slice(_current);
    534e:	6898      	ldr	r0, [r3, #8]
		_current_cpu->slice_ticks = 0;
    5350:	611e      	str	r6, [r3, #16]
		slice_max_prio = prio;
    5352:	6015      	str	r5, [r2, #0]
		z_reset_time_slice(_current);
    5354:	f7ff ff0a 	bl	516c <z_reset_time_slice>
	__asm__ volatile(
    5358:	f387 8811 	msr	BASEPRI, r7
    535c:	f3bf 8f6f 	isb	sy
}
    5360:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    5362:	bf00      	nop
    5364:	20000a50 	.word	0x20000a50
    5368:	20000a20 	.word	0x20000a20
    536c:	20000a4c 	.word	0x20000a4c

00005370 <z_time_slice>:
{
    5370:	b538      	push	{r3, r4, r5, lr}
	__asm__ volatile(
    5372:	f04f 0320 	mov.w	r3, #32
    5376:	f3ef 8511 	mrs	r5, BASEPRI
    537a:	f383 8812 	msr	BASEPRI_MAX, r3
    537e:	f3bf 8f6f 	isb	sy
	if (pending_current == _current) {
    5382:	4b17      	ldr	r3, [pc, #92]	; (53e0 <z_time_slice+0x70>)
    5384:	4a17      	ldr	r2, [pc, #92]	; (53e4 <z_time_slice+0x74>)
    5386:	689c      	ldr	r4, [r3, #8]
    5388:	6811      	ldr	r1, [r2, #0]
    538a:	428c      	cmp	r4, r1
    538c:	d107      	bne.n	539e <z_time_slice+0x2e>
	z_reset_time_slice(curr);
    538e:	4620      	mov	r0, r4
    5390:	f7ff feec 	bl	516c <z_reset_time_slice>
	__asm__ volatile(
    5394:	f385 8811 	msr	BASEPRI, r5
    5398:	f3bf 8f6f 	isb	sy
}
    539c:	bd38      	pop	{r3, r4, r5, pc}
	pending_current = NULL;
    539e:	2100      	movs	r1, #0
    53a0:	6011      	str	r1, [r2, #0]
	int ret = slice_ticks;
    53a2:	4a11      	ldr	r2, [pc, #68]	; (53e8 <z_time_slice+0x78>)
	if (slice_time(_current) && sliceable(_current)) {
    53a4:	6812      	ldr	r2, [r2, #0]
    53a6:	b1c2      	cbz	r2, 53da <z_time_slice+0x6a>
		&& !z_is_idle_thread_object(thread);
    53a8:	89e2      	ldrh	r2, [r4, #14]
    53aa:	2a7f      	cmp	r2, #127	; 0x7f
    53ac:	d815      	bhi.n	53da <z_time_slice+0x6a>
		&& !z_is_thread_prevented_from_running(thread)
    53ae:	7b62      	ldrb	r2, [r4, #13]
    53b0:	06d2      	lsls	r2, r2, #27
    53b2:	d112      	bne.n	53da <z_time_slice+0x6a>
		&& !z_is_prio_higher(thread->base.prio, slice_max_prio)
    53b4:	4a0d      	ldr	r2, [pc, #52]	; (53ec <z_time_slice+0x7c>)
    53b6:	f994 100e 	ldrsb.w	r1, [r4, #14]
    53ba:	6812      	ldr	r2, [r2, #0]
    53bc:	4291      	cmp	r1, r2
    53be:	db0c      	blt.n	53da <z_time_slice+0x6a>
		&& !z_is_idle_thread_object(thread);
    53c0:	4a0b      	ldr	r2, [pc, #44]	; (53f0 <z_time_slice+0x80>)
    53c2:	4294      	cmp	r4, r2
    53c4:	d009      	beq.n	53da <z_time_slice+0x6a>
		if (ticks >= _current_cpu->slice_ticks) {
    53c6:	691a      	ldr	r2, [r3, #16]
    53c8:	4282      	cmp	r2, r0
    53ca:	dc03      	bgt.n	53d4 <z_time_slice+0x64>
		move_thread_to_end_of_prio_q(curr);
    53cc:	4620      	mov	r0, r4
    53ce:	f7ff feff 	bl	51d0 <move_thread_to_end_of_prio_q>
    53d2:	e7dc      	b.n	538e <z_time_slice+0x1e>
			_current_cpu->slice_ticks -= ticks;
    53d4:	1a12      	subs	r2, r2, r0
		_current_cpu->slice_ticks = 0;
    53d6:	611a      	str	r2, [r3, #16]
    53d8:	e7dc      	b.n	5394 <z_time_slice+0x24>
    53da:	2200      	movs	r2, #0
    53dc:	e7fb      	b.n	53d6 <z_time_slice+0x66>
    53de:	bf00      	nop
    53e0:	20000a20 	.word	0x20000a20
    53e4:	20000a48 	.word	0x20000a48
    53e8:	20000a50 	.word	0x20000a50
    53ec:	20000a4c 	.word	0x20000a4c
    53f0:	20000260 	.word	0x20000260

000053f4 <z_pend_curr>:
{
    53f4:	b570      	push	{r4, r5, r6, lr}
	pending_current = _current;
    53f6:	480c      	ldr	r0, [pc, #48]	; (5428 <z_pend_curr+0x34>)
    53f8:	4d0c      	ldr	r5, [pc, #48]	; (542c <z_pend_curr+0x38>)
    53fa:	6886      	ldr	r6, [r0, #8]
{
    53fc:	460c      	mov	r4, r1
	pending_current = _current;
    53fe:	602e      	str	r6, [r5, #0]
{
    5400:	4611      	mov	r1, r2
    5402:	e9dd 2304 	ldrd	r2, r3, [sp, #16]
	__asm__ volatile(
    5406:	f04f 0620 	mov.w	r6, #32
    540a:	f3ef 8511 	mrs	r5, BASEPRI
    540e:	f386 8812 	msr	BASEPRI_MAX, r6
    5412:	f3bf 8f6f 	isb	sy
	pend_locked(_current, wait_q, timeout);
    5416:	6880      	ldr	r0, [r0, #8]
    5418:	f7ff ff60 	bl	52dc <pend_locked>
	ret = arch_swap(key);
    541c:	4620      	mov	r0, r4
}
    541e:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    5422:	f7fc b915 	b.w	1650 <arch_swap>
    5426:	bf00      	nop
    5428:	20000a20 	.word	0x20000a20
    542c:	20000a48 	.word	0x20000a48

00005430 <z_set_prio>:
{
    5430:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    5432:	4604      	mov	r4, r0
    5434:	f04f 0320 	mov.w	r3, #32
    5438:	f3ef 8611 	mrs	r6, BASEPRI
    543c:	f383 8812 	msr	BASEPRI_MAX, r3
    5440:	f3bf 8f6f 	isb	sy
	uint8_t state = thread->base.thread_state;
    5444:	7b43      	ldrb	r3, [r0, #13]
				thread->base.prio = prio;
    5446:	b249      	sxtb	r1, r1
	return !((z_is_thread_prevented_from_running(thread)) != 0U ||
    5448:	06da      	lsls	r2, r3, #27
    544a:	d119      	bne.n	5480 <z_set_prio+0x50>
	return node->next != NULL;
    544c:	6985      	ldr	r5, [r0, #24]
    544e:	b9bd      	cbnz	r5, 5480 <z_set_prio+0x50>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    5450:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    5454:	7343      	strb	r3, [r0, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    5456:	f001 fc3b 	bl	6cd0 <sys_dlist_remove>
	thread->base.thread_state |= _THREAD_QUEUED;
    545a:	7b43      	ldrb	r3, [r0, #13]
	return list->head == list;
    545c:	4a16      	ldr	r2, [pc, #88]	; (54b8 <z_set_prio+0x88>)
    545e:	f063 037f 	orn	r3, r3, #127	; 0x7f
    5462:	7343      	strb	r3, [r0, #13]
    5464:	4613      	mov	r3, r2
				thread->base.prio = prio;
    5466:	7381      	strb	r1, [r0, #14]
    5468:	f853 0f20 	ldr.w	r0, [r3, #32]!
	return sys_dlist_is_empty(list) ? NULL : list->head;
    546c:	4298      	cmp	r0, r3
    546e:	bf18      	it	ne
    5470:	4605      	movne	r5, r0
	return (node == list->tail) ? NULL : node->next;
    5472:	6a50      	ldr	r0, [r2, #36]	; 0x24
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    5474:	b95d      	cbnz	r5, 548e <z_set_prio+0x5e>
	node->prev = tail;
    5476:	e9c4 3000 	strd	r3, r0, [r4]
	tail->next = node;
    547a:	6004      	str	r4, [r0, #0]
	list->tail = node;
    547c:	6254      	str	r4, [r2, #36]	; 0x24
}
    547e:	e011      	b.n	54a4 <z_set_prio+0x74>
    5480:	2000      	movs	r0, #0
			thread->base.prio = prio;
    5482:	73a1      	strb	r1, [r4, #14]
	__asm__ volatile(
    5484:	f386 8811 	msr	BASEPRI, r6
    5488:	f3bf 8f6f 	isb	sy
}
    548c:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	int32_t b2 = thread_2->base.prio;
    548e:	f995 700e 	ldrsb.w	r7, [r5, #14]
	if (b1 != b2) {
    5492:	42b9      	cmp	r1, r7
    5494:	d00b      	beq.n	54ae <z_set_prio+0x7e>
		if (z_sched_prio_cmp(thread, t) > 0) {
    5496:	428f      	cmp	r7, r1
    5498:	dd09      	ble.n	54ae <z_set_prio+0x7e>
	sys_dnode_t *const prev = successor->prev;
    549a:	686b      	ldr	r3, [r5, #4]
	node->next = successor;
    549c:	e9c4 5300 	strd	r5, r3, [r4]
	prev->next = node;
    54a0:	601c      	str	r4, [r3, #0]
	successor->prev = node;
    54a2:	606c      	str	r4, [r5, #4]
			update_cache(1);
    54a4:	2001      	movs	r0, #1
    54a6:	f7ff fe75 	bl	5194 <update_cache>
    54aa:	2001      	movs	r0, #1
    54ac:	e7ea      	b.n	5484 <z_set_prio+0x54>
	return (node == list->tail) ? NULL : node->next;
    54ae:	42a8      	cmp	r0, r5
    54b0:	d0e1      	beq.n	5476 <z_set_prio+0x46>
    54b2:	682d      	ldr	r5, [r5, #0]
    54b4:	e7de      	b.n	5474 <z_set_prio+0x44>
    54b6:	bf00      	nop
    54b8:	20000a20 	.word	0x20000a20

000054bc <z_reschedule>:
	return arch_irq_unlocked(key) && !arch_is_in_isr();
    54bc:	b949      	cbnz	r1, 54d2 <z_reschedule+0x16>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    54be:	f3ef 8005 	mrs	r0, IPSR
    54c2:	b930      	cbnz	r0, 54d2 <z_reschedule+0x16>
	new_thread = _kernel.ready_q.cache;
    54c4:	4b05      	ldr	r3, [pc, #20]	; (54dc <z_reschedule+0x20>)
	if (resched(key.key) && need_swap()) {
    54c6:	69da      	ldr	r2, [r3, #28]
    54c8:	689b      	ldr	r3, [r3, #8]
    54ca:	429a      	cmp	r2, r3
    54cc:	d001      	beq.n	54d2 <z_reschedule+0x16>
    54ce:	f7fc b8bf 	b.w	1650 <arch_swap>
    54d2:	f381 8811 	msr	BASEPRI, r1
    54d6:	f3bf 8f6f 	isb	sy
}
    54da:	4770      	bx	lr
    54dc:	20000a20 	.word	0x20000a20

000054e0 <z_sched_start>:
{
    54e0:	b510      	push	{r4, lr}
	__asm__ volatile(
    54e2:	f04f 0220 	mov.w	r2, #32
    54e6:	f3ef 8411 	mrs	r4, BASEPRI
    54ea:	f382 8812 	msr	BASEPRI_MAX, r2
    54ee:	f3bf 8f6f 	isb	sy
	return (thread->base.thread_state & _THREAD_PRESTART) == 0U;
    54f2:	7b42      	ldrb	r2, [r0, #13]
	if (z_has_thread_started(thread)) {
    54f4:	0751      	lsls	r1, r2, #29
    54f6:	d404      	bmi.n	5502 <z_sched_start+0x22>
	__asm__ volatile(
    54f8:	f384 8811 	msr	BASEPRI, r4
    54fc:	f3bf 8f6f 	isb	sy
}
    5500:	bd10      	pop	{r4, pc}
	thread->base.thread_state &= ~_THREAD_PRESTART;
    5502:	f022 0204 	bic.w	r2, r2, #4
    5506:	7342      	strb	r2, [r0, #13]
	ready_thread(thread);
    5508:	f7ff fe9c 	bl	5244 <ready_thread>
	z_reschedule(&sched_spinlock, key);
    550c:	4621      	mov	r1, r4
}
    550e:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	z_reschedule(&sched_spinlock, key);
    5512:	4801      	ldr	r0, [pc, #4]	; (5518 <z_sched_start+0x38>)
    5514:	f7ff bfd2 	b.w	54bc <z_reschedule>
    5518:	20000c40 	.word	0x20000c40

0000551c <z_impl_k_thread_suspend>:
{
    551c:	b570      	push	{r4, r5, r6, lr}
    551e:	4604      	mov	r4, r0
}

static inline int z_abort_thread_timeout(struct k_thread *thread)
{
	return z_abort_timeout(&thread->base.timeout);
    5520:	3018      	adds	r0, #24
    5522:	f001 fc73 	bl	6e0c <z_abort_timeout>
	__asm__ volatile(
    5526:	f04f 0320 	mov.w	r3, #32
    552a:	f3ef 8611 	mrs	r6, BASEPRI
    552e:	f383 8812 	msr	BASEPRI_MAX, r3
    5532:	f3bf 8f6f 	isb	sy
		if (z_is_thread_queued(thread)) {
    5536:	f994 200d 	ldrsb.w	r2, [r4, #13]
	return (thread->base.thread_state & state) != 0U;
    553a:	7b63      	ldrb	r3, [r4, #13]
    553c:	2a00      	cmp	r2, #0
    553e:	da05      	bge.n	554c <z_impl_k_thread_suspend+0x30>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    5540:	f003 037f 	and.w	r3, r3, #127	; 0x7f
	sys_dlist_remove(&thread->base.qnode_dlist);
    5544:	4620      	mov	r0, r4
	thread->base.thread_state &= ~_THREAD_QUEUED;
    5546:	7363      	strb	r3, [r4, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    5548:	f001 fbc2 	bl	6cd0 <sys_dlist_remove>
		update_cache(thread == _current);
    554c:	4d0b      	ldr	r5, [pc, #44]	; (557c <z_impl_k_thread_suspend+0x60>)
	thread->base.thread_state |= _THREAD_SUSPENDED;
    554e:	7b63      	ldrb	r3, [r4, #13]
    5550:	68a8      	ldr	r0, [r5, #8]
    5552:	f043 0310 	orr.w	r3, r3, #16
    5556:	7363      	strb	r3, [r4, #13]
    5558:	1b03      	subs	r3, r0, r4
    555a:	4258      	negs	r0, r3
    555c:	4158      	adcs	r0, r3
    555e:	f7ff fe19 	bl	5194 <update_cache>
	__asm__ volatile(
    5562:	f386 8811 	msr	BASEPRI, r6
    5566:	f3bf 8f6f 	isb	sy
	if (thread == _current) {
    556a:	68ab      	ldr	r3, [r5, #8]
    556c:	42a3      	cmp	r3, r4
    556e:	d103      	bne.n	5578 <z_impl_k_thread_suspend+0x5c>
}
    5570:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		z_reschedule_unlocked();
    5574:	f001 bc40 	b.w	6df8 <z_reschedule_unlocked>
}
    5578:	bd70      	pop	{r4, r5, r6, pc}
    557a:	bf00      	nop
    557c:	20000a20 	.word	0x20000a20

00005580 <k_sched_lock>:
	__asm__ volatile(
    5580:	f04f 0320 	mov.w	r3, #32
    5584:	f3ef 8111 	mrs	r1, BASEPRI
    5588:	f383 8812 	msr	BASEPRI_MAX, r3
    558c:	f3bf 8f6f 	isb	sy
static inline void z_sched_lock(void)
{
	__ASSERT(!arch_is_in_isr(), "");
	__ASSERT(_current->base.sched_locked != 1U, "");

	--_current->base.sched_locked;
    5590:	4b04      	ldr	r3, [pc, #16]	; (55a4 <k_sched_lock+0x24>)
    5592:	689a      	ldr	r2, [r3, #8]
    5594:	7bd3      	ldrb	r3, [r2, #15]
    5596:	3b01      	subs	r3, #1
    5598:	73d3      	strb	r3, [r2, #15]
	__asm__ volatile(
    559a:	f381 8811 	msr	BASEPRI, r1
    559e:	f3bf 8f6f 	isb	sy
}
    55a2:	4770      	bx	lr
    55a4:	20000a20 	.word	0x20000a20

000055a8 <k_sched_unlock>:
{
    55a8:	b510      	push	{r4, lr}
	__asm__ volatile(
    55aa:	f04f 0320 	mov.w	r3, #32
    55ae:	f3ef 8411 	mrs	r4, BASEPRI
    55b2:	f383 8812 	msr	BASEPRI_MAX, r3
    55b6:	f3bf 8f6f 	isb	sy
		++_current->base.sched_locked;
    55ba:	4b08      	ldr	r3, [pc, #32]	; (55dc <k_sched_unlock+0x34>)
		update_cache(0);
    55bc:	2000      	movs	r0, #0
		++_current->base.sched_locked;
    55be:	689a      	ldr	r2, [r3, #8]
    55c0:	7bd3      	ldrb	r3, [r2, #15]
    55c2:	3301      	adds	r3, #1
    55c4:	73d3      	strb	r3, [r2, #15]
		update_cache(0);
    55c6:	f7ff fde5 	bl	5194 <update_cache>
	__asm__ volatile(
    55ca:	f384 8811 	msr	BASEPRI, r4
    55ce:	f3bf 8f6f 	isb	sy
}
    55d2:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	z_reschedule_unlocked();
    55d6:	f001 bc0f 	b.w	6df8 <z_reschedule_unlocked>
    55da:	bf00      	nop
    55dc:	20000a20 	.word	0x20000a20

000055e0 <z_sched_init>:
#else
	init_ready_q(&_kernel.ready_q);
#endif

#ifdef CONFIG_TIMESLICING
	k_sched_time_slice_set(CONFIG_TIMESLICE_SIZE,
    55e0:	2100      	movs	r1, #0
	list->head = (sys_dnode_t *)list;
    55e2:	4b04      	ldr	r3, [pc, #16]	; (55f4 <z_sched_init+0x14>)
    55e4:	4608      	mov	r0, r1
    55e6:	f103 0220 	add.w	r2, r3, #32
	list->tail = (sys_dnode_t *)list;
    55ea:	e9c3 2208 	strd	r2, r2, [r3, #32]
    55ee:	f7ff be8d 	b.w	530c <k_sched_time_slice_set>
    55f2:	bf00      	nop
    55f4:	20000a20 	.word	0x20000a20

000055f8 <z_impl_k_yield>:
	return !(k_is_pre_kernel() || k_is_in_isr() ||
		 z_is_idle_thread_object(_current));
}

void z_impl_k_yield(void)
{
    55f8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	__asm__ volatile(
    55fa:	f04f 0320 	mov.w	r3, #32
    55fe:	f3ef 8511 	mrs	r5, BASEPRI
    5602:	f383 8812 	msr	BASEPRI_MAX, r3
    5606:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&sched_spinlock);

	if (!IS_ENABLED(CONFIG_SMP) ||
	    z_is_thread_queued(_current)) {
		dequeue_thread(_current);
    560a:	4919      	ldr	r1, [pc, #100]	; (5670 <z_impl_k_yield+0x78>)
    560c:	6888      	ldr	r0, [r1, #8]
	thread->base.thread_state &= ~_THREAD_QUEUED;
    560e:	7b43      	ldrb	r3, [r0, #13]
    5610:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    5614:	7343      	strb	r3, [r0, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    5616:	f001 fb5b 	bl	6cd0 <sys_dlist_remove>
	return list->head == list;
    561a:	4608      	mov	r0, r1
	}
	queue_thread(_current);
    561c:	688b      	ldr	r3, [r1, #8]
	thread->base.thread_state |= _THREAD_QUEUED;
    561e:	7b5a      	ldrb	r2, [r3, #13]
    5620:	f062 027f 	orn	r2, r2, #127	; 0x7f
    5624:	735a      	strb	r2, [r3, #13]
    5626:	f850 2f20 	ldr.w	r2, [r0, #32]!
	return (node == list->tail) ? NULL : node->next;
    562a:	6a4c      	ldr	r4, [r1, #36]	; 0x24
	return sys_dlist_is_empty(list) ? NULL : list->head;
    562c:	4282      	cmp	r2, r0
    562e:	bf08      	it	eq
    5630:	2200      	moveq	r2, #0
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    5632:	b922      	cbnz	r2, 563e <z_impl_k_yield+0x46>
	node->prev = tail;
    5634:	e9c3 0400 	strd	r0, r4, [r3]
	tail->next = node;
    5638:	6023      	str	r3, [r4, #0]
	list->tail = node;
    563a:	624b      	str	r3, [r1, #36]	; 0x24
}
    563c:	e00c      	b.n	5658 <z_impl_k_yield+0x60>
	int32_t b1 = thread_1->base.prio;
    563e:	f993 600e 	ldrsb.w	r6, [r3, #14]
	int32_t b2 = thread_2->base.prio;
    5642:	f992 700e 	ldrsb.w	r7, [r2, #14]
	if (b1 != b2) {
    5646:	42be      	cmp	r6, r7
    5648:	d00e      	beq.n	5668 <z_impl_k_yield+0x70>
		if (z_sched_prio_cmp(thread, t) > 0) {
    564a:	42b7      	cmp	r7, r6
    564c:	dd0c      	ble.n	5668 <z_impl_k_yield+0x70>
	sys_dnode_t *const prev = successor->prev;
    564e:	6851      	ldr	r1, [r2, #4]
	node->next = successor;
    5650:	e9c3 2100 	strd	r2, r1, [r3]
	prev->next = node;
    5654:	600b      	str	r3, [r1, #0]
	successor->prev = node;
    5656:	6053      	str	r3, [r2, #4]
	update_cache(1);
    5658:	2001      	movs	r0, #1
    565a:	f7ff fd9b 	bl	5194 <update_cache>
    565e:	4628      	mov	r0, r5
	z_swap(&sched_spinlock, key);
}
    5660:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
    5664:	f7fb bff4 	b.w	1650 <arch_swap>
	return (node == list->tail) ? NULL : node->next;
    5668:	42a2      	cmp	r2, r4
    566a:	d0e3      	beq.n	5634 <z_impl_k_yield+0x3c>
    566c:	6812      	ldr	r2, [r2, #0]
    566e:	e7e0      	b.n	5632 <z_impl_k_yield+0x3a>
    5670:	20000a20 	.word	0x20000a20

00005674 <z_tick_sleep>:
	__ASSERT(!arch_is_in_isr(), "");

	LOG_DBG("thread %p for %lu ticks", _current, (unsigned long)ticks);

	/* wait of 0 ms is treated as a 'yield' */
	if (ticks == 0) {
    5674:	ea50 0301 	orrs.w	r3, r0, r1
{
    5678:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    567c:	4605      	mov	r5, r0
    567e:	460e      	mov	r6, r1
	if (ticks == 0) {
    5680:	d103      	bne.n	568a <z_tick_sleep+0x16>
	z_impl_k_yield();
    5682:	f7ff ffb9 	bl	55f8 <z_impl_k_yield>
		k_yield();
		return 0;
    5686:	2000      	movs	r0, #0
    5688:	e02c      	b.n	56e4 <z_tick_sleep+0x70>
	}

	k_timeout_t timeout = Z_TIMEOUT_TICKS(ticks);
	if (Z_TICK_ABS(ticks) <= 0) {
    568a:	1c83      	adds	r3, r0, #2
    568c:	f171 33ff 	sbcs.w	r3, r1, #4294967295
    5690:	db2a      	blt.n	56e8 <z_tick_sleep+0x74>
		expected_wakeup_ticks = ticks + sys_clock_tick_get_32();
    5692:	f001 fbfd 	bl	6e90 <sys_clock_tick_get_32>
    5696:	182c      	adds	r4, r5, r0
    5698:	f04f 0320 	mov.w	r3, #32
    569c:	f3ef 8811 	mrs	r8, BASEPRI
    56a0:	f383 8812 	msr	BASEPRI_MAX, r3
    56a4:	f3bf 8f6f 	isb	sy
	}

	k_spinlock_key_t key = k_spin_lock(&sched_spinlock);

#if defined(CONFIG_TIMESLICING) && defined(CONFIG_SWAP_NONATOMIC)
	pending_current = _current;
    56a8:	4f11      	ldr	r7, [pc, #68]	; (56f0 <z_tick_sleep+0x7c>)
    56aa:	4b12      	ldr	r3, [pc, #72]	; (56f4 <z_tick_sleep+0x80>)
    56ac:	68b8      	ldr	r0, [r7, #8]
    56ae:	6018      	str	r0, [r3, #0]
#endif
	unready_thread(_current);
    56b0:	f7ff fdfc 	bl	52ac <unready_thread>
	z_add_thread_timeout(_current, timeout);
    56b4:	68b8      	ldr	r0, [r7, #8]
	z_add_timeout(&thread->base.timeout, z_thread_timeout, ticks);
    56b6:	4910      	ldr	r1, [pc, #64]	; (56f8 <z_tick_sleep+0x84>)
    56b8:	462a      	mov	r2, r5
    56ba:	4633      	mov	r3, r6
    56bc:	3018      	adds	r0, #24
    56be:	f000 f905 	bl	58cc <z_add_timeout>
	z_mark_thread_as_suspended(_current);
    56c2:	68ba      	ldr	r2, [r7, #8]
    56c4:	4640      	mov	r0, r8
	thread->base.thread_state |= _THREAD_SUSPENDED;
    56c6:	7b53      	ldrb	r3, [r2, #13]
    56c8:	f043 0310 	orr.w	r3, r3, #16
    56cc:	7353      	strb	r3, [r2, #13]
    56ce:	f7fb ffbf 	bl	1650 <arch_swap>

	(void)z_swap(&sched_spinlock, key);

	__ASSERT(!z_is_thread_state_set(_current, _THREAD_SUSPENDED), "");

	ticks = (k_ticks_t)expected_wakeup_ticks - sys_clock_tick_get_32();
    56d2:	f001 fbdd 	bl	6e90 <sys_clock_tick_get_32>
    56d6:	1a20      	subs	r0, r4, r0
    56d8:	eb63 0303 	sbc.w	r3, r3, r3
	if (ticks > 0) {
    56dc:	2801      	cmp	r0, #1
    56de:	f173 0300 	sbcs.w	r3, r3, #0
    56e2:	dbd0      	blt.n	5686 <z_tick_sleep+0x12>
		return ticks;
	}
#endif

	return 0;
}
    56e4:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		expected_wakeup_ticks = Z_TICK_ABS(ticks);
    56e8:	f06f 0401 	mvn.w	r4, #1
    56ec:	1a24      	subs	r4, r4, r0
    56ee:	e7d3      	b.n	5698 <z_tick_sleep+0x24>
    56f0:	20000a20 	.word	0x20000a20
    56f4:	20000a48 	.word	0x20000a48
    56f8:	00006cf5 	.word	0x00006cf5

000056fc <z_impl_k_sleep>:
	__ASSERT(!arch_is_in_isr(), "");

	SYS_PORT_TRACING_FUNC_ENTER(k_thread, sleep, timeout);

	/* in case of K_FOREVER, we suspend */
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    56fc:	f1b1 3fff 	cmp.w	r1, #4294967295
    5700:	bf08      	it	eq
    5702:	f1b0 3fff 	cmpeq.w	r0, #4294967295
{
    5706:	b508      	push	{r3, lr}
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    5708:	d106      	bne.n	5718 <z_impl_k_sleep+0x1c>
		k_thread_suspend(_current);
    570a:	4b08      	ldr	r3, [pc, #32]	; (572c <z_impl_k_sleep+0x30>)
    570c:	6898      	ldr	r0, [r3, #8]
	z_impl_k_thread_suspend(thread);
    570e:	f7ff ff05 	bl	551c <z_impl_k_thread_suspend>

		SYS_PORT_TRACING_FUNC_EXIT(k_thread, sleep, timeout, (int32_t) K_TICKS_FOREVER);

		return (int32_t) K_TICKS_FOREVER;
    5712:	f04f 30ff 	mov.w	r0, #4294967295
	int32_t ret = k_ticks_to_ms_floor64(ticks);

	SYS_PORT_TRACING_FUNC_EXIT(k_thread, sleep, timeout, ret);

	return ret;
}
    5716:	bd08      	pop	{r3, pc}
	ticks = z_tick_sleep(ticks);
    5718:	f7ff ffac 	bl	5674 <z_tick_sleep>
			return ((t * to_hz + off) / from_hz);
    571c:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
    5720:	fb80 0303 	smull	r0, r3, r0, r3
    5724:	0bc0      	lsrs	r0, r0, #15
    5726:	ea40 4043 	orr.w	r0, r0, r3, lsl #17
	return ret;
    572a:	e7f4      	b.n	5716 <z_impl_k_sleep+0x1a>
    572c:	20000a20 	.word	0x20000a20

00005730 <z_impl_z_current_get>:

#ifdef CONFIG_SMP
	arch_irq_unlock(k);
#endif
	return ret;
}
    5730:	4b01      	ldr	r3, [pc, #4]	; (5738 <z_impl_z_current_get+0x8>)
    5732:	6898      	ldr	r0, [r3, #8]
    5734:	4770      	bx	lr
    5736:	bf00      	nop
    5738:	20000a20 	.word	0x20000a20

0000573c <z_thread_abort>:
#endif
	}
}

void z_thread_abort(struct k_thread *thread)
{
    573c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    5740:	4604      	mov	r4, r0
    5742:	f04f 0320 	mov.w	r3, #32
    5746:	f3ef 8611 	mrs	r6, BASEPRI
    574a:	f383 8812 	msr	BASEPRI_MAX, r3
    574e:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&sched_spinlock);

	if ((thread->base.user_options & K_ESSENTIAL) != 0) {
    5752:	7b03      	ldrb	r3, [r0, #12]
    5754:	07d9      	lsls	r1, r3, #31
    5756:	d50b      	bpl.n	5770 <z_thread_abort+0x34>
	__asm__ volatile(
    5758:	f386 8811 	msr	BASEPRI, r6
    575c:	f3bf 8f6f 	isb	sy
		k_spin_unlock(&sched_spinlock, key);
		__ASSERT(false, "aborting essential thread %p", thread);
		k_panic();
    5760:	4040      	eors	r0, r0
    5762:	f380 8811 	msr	BASEPRI, r0
    5766:	f04f 0004 	mov.w	r0, #4
    576a:	df02      	svc	2
	if (thread == _current && !arch_is_in_isr()) {
		z_swap(&sched_spinlock, key);
		__ASSERT(false, "aborted _current back from dead");
	}
	k_spin_unlock(&sched_spinlock, key);
}
    576c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	if ((thread->base.thread_state & _THREAD_DEAD) != 0U) {
    5770:	7b43      	ldrb	r3, [r0, #13]
    5772:	071a      	lsls	r2, r3, #28
    5774:	d504      	bpl.n	5780 <z_thread_abort+0x44>
    5776:	f386 8811 	msr	BASEPRI, r6
    577a:	f3bf 8f6f 	isb	sy
    577e:	e7f5      	b.n	576c <z_thread_abort+0x30>
		thread->base.thread_state &= ~_THREAD_ABORTING;
    5780:	f023 0220 	bic.w	r2, r3, #32
    5784:	f042 0108 	orr.w	r1, r2, #8
		if (z_is_thread_queued(thread)) {
    5788:	09d2      	lsrs	r2, r2, #7
    578a:	d120      	bne.n	57ce <z_thread_abort+0x92>
		thread->base.thread_state &= ~_THREAD_ABORTING;
    578c:	7341      	strb	r1, [r0, #13]
		if (thread->base.pended_on != NULL) {
    578e:	68a3      	ldr	r3, [r4, #8]
    5790:	b113      	cbz	r3, 5798 <z_thread_abort+0x5c>
			unpend_thread_no_timeout(thread);
    5792:	4620      	mov	r0, r4
    5794:	f001 faa4 	bl	6ce0 <unpend_thread_no_timeout>
	return z_abort_timeout(&thread->base.timeout);
    5798:	f104 0018 	add.w	r0, r4, #24
    579c:	f001 fb36 	bl	6e0c <z_abort_timeout>
    57a0:	f04f 0800 	mov.w	r8, #0
}

static inline struct k_thread *z_waitq_head(_wait_q_t *w)
{
	return (struct k_thread *)sys_dlist_peek_head(&w->waitq);
    57a4:	f104 0758 	add.w	r7, r4, #88	; 0x58
	return list->head == list;
    57a8:	6da5      	ldr	r5, [r4, #88]	; 0x58
	return sys_dlist_is_empty(list) ? NULL : list->head;
    57aa:	42bd      	cmp	r5, r7
    57ac:	d000      	beq.n	57b0 <z_thread_abort+0x74>
	while ((thread = z_waitq_head(wait_q)) != NULL) {
    57ae:	b9b5      	cbnz	r5, 57de <z_thread_abort+0xa2>
		update_cache(1);
    57b0:	2001      	movs	r0, #1
    57b2:	f7ff fcef 	bl	5194 <update_cache>
	if (thread == _current && !arch_is_in_isr()) {
    57b6:	4b10      	ldr	r3, [pc, #64]	; (57f8 <z_thread_abort+0xbc>)
    57b8:	689b      	ldr	r3, [r3, #8]
    57ba:	42a3      	cmp	r3, r4
    57bc:	d1db      	bne.n	5776 <z_thread_abort+0x3a>
    57be:	f3ef 8305 	mrs	r3, IPSR
    57c2:	2b00      	cmp	r3, #0
    57c4:	d1d7      	bne.n	5776 <z_thread_abort+0x3a>
    57c6:	4630      	mov	r0, r6
    57c8:	f7fb ff42 	bl	1650 <arch_swap>
	return ret;
    57cc:	e7d3      	b.n	5776 <z_thread_abort+0x3a>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    57ce:	f003 035f 	and.w	r3, r3, #95	; 0x5f
    57d2:	f043 0308 	orr.w	r3, r3, #8
    57d6:	7343      	strb	r3, [r0, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    57d8:	f001 fa7a 	bl	6cd0 <sys_dlist_remove>
}
    57dc:	e7d7      	b.n	578e <z_thread_abort+0x52>
		unpend_thread_no_timeout(thread);
    57de:	4628      	mov	r0, r5
    57e0:	f001 fa7e 	bl	6ce0 <unpend_thread_no_timeout>
    57e4:	f105 0018 	add.w	r0, r5, #24
    57e8:	f001 fb10 	bl	6e0c <z_abort_timeout>
		ready_thread(thread);
    57ec:	4628      	mov	r0, r5
    57ee:	f8c5 8078 	str.w	r8, [r5, #120]	; 0x78
    57f2:	f7ff fd27 	bl	5244 <ready_thread>
    57f6:	e7d7      	b.n	57a8 <z_thread_abort+0x6c>
    57f8:	20000a20 	.word	0x20000a20

000057fc <z_data_copy>:
 * @brief Copy the data section from ROM to RAM
 *
 * This routine copies the data section from ROM to RAM.
 */
void z_data_copy(void)
{
    57fc:	b508      	push	{r3, lr}
	z_early_memcpy(&__data_region_start, &__data_region_load_start,
		       __data_region_end - __data_region_start);
    57fe:	4806      	ldr	r0, [pc, #24]	; (5818 <z_data_copy+0x1c>)
	z_early_memcpy(&__data_region_start, &__data_region_load_start,
    5800:	4a06      	ldr	r2, [pc, #24]	; (581c <z_data_copy+0x20>)
    5802:	4907      	ldr	r1, [pc, #28]	; (5820 <z_data_copy+0x24>)
    5804:	1a12      	subs	r2, r2, r0
    5806:	f001 f9ec 	bl	6be2 <z_early_memcpy>
#else
	z_early_memcpy(&_app_smem_start, &_app_smem_rom_start,
		       _app_smem_end - _app_smem_start);
#endif /* CONFIG_STACK_CANARIES */
#endif /* CONFIG_USERSPACE */
}
    580a:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	z_early_memcpy(&__ramfunc_start, &__ramfunc_load_start,
    580e:	4a05      	ldr	r2, [pc, #20]	; (5824 <z_data_copy+0x28>)
    5810:	4905      	ldr	r1, [pc, #20]	; (5828 <z_data_copy+0x2c>)
    5812:	4806      	ldr	r0, [pc, #24]	; (582c <z_data_copy+0x30>)
    5814:	f001 b9e5 	b.w	6be2 <z_early_memcpy>
    5818:	20000000 	.word	0x20000000
    581c:	2000023c 	.word	0x2000023c
    5820:	000079d8 	.word	0x000079d8
    5824:	00000000 	.word	0x00000000
    5828:	000079d8 	.word	0x000079d8
    582c:	20000000 	.word	0x20000000

00005830 <elapsed>:
	sys_dlist_remove(&t->node);
}

static int32_t elapsed(void)
{
	return announce_remaining == 0 ? sys_clock_elapsed() : 0U;
    5830:	4b03      	ldr	r3, [pc, #12]	; (5840 <elapsed+0x10>)
    5832:	681b      	ldr	r3, [r3, #0]
    5834:	b90b      	cbnz	r3, 583a <elapsed+0xa>
    5836:	f7fd be51 	b.w	34dc <sys_clock_elapsed>
}
    583a:	2000      	movs	r0, #0
    583c:	4770      	bx	lr
    583e:	bf00      	nop
    5840:	20000a54 	.word	0x20000a54

00005844 <next_timeout>:

static int32_t next_timeout(void)
{
    5844:	b510      	push	{r4, lr}
	return list->head == list;
    5846:	4b11      	ldr	r3, [pc, #68]	; (588c <next_timeout+0x48>)
    5848:	681c      	ldr	r4, [r3, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    584a:	429c      	cmp	r4, r3
    584c:	d10a      	bne.n	5864 <next_timeout+0x20>
	struct _timeout *to = first();
	int32_t ticks_elapsed = elapsed();
    584e:	f7ff ffef 	bl	5830 <elapsed>
	int32_t ret;

	if ((to == NULL) ||
	    ((int64_t)(to->dticks - ticks_elapsed) > (int64_t)INT_MAX)) {
		ret = MAX_WAIT;
    5852:	f06f 4000 	mvn.w	r0, #2147483648	; 0x80000000
	} else {
		ret = MAX(0, to->dticks - ticks_elapsed);
	}

#ifdef CONFIG_TIMESLICING
	if (_current_cpu->slice_ticks && _current_cpu->slice_ticks < ret) {
    5856:	4b0e      	ldr	r3, [pc, #56]	; (5890 <next_timeout+0x4c>)
    5858:	691b      	ldr	r3, [r3, #16]
    585a:	b113      	cbz	r3, 5862 <next_timeout+0x1e>
    585c:	4298      	cmp	r0, r3
    585e:	bfa8      	it	ge
    5860:	4618      	movge	r0, r3
		ret = _current_cpu->slice_ticks;
	}
#endif
	return ret;
}
    5862:	bd10      	pop	{r4, pc}
	int32_t ticks_elapsed = elapsed();
    5864:	f7ff ffe4 	bl	5830 <elapsed>
	if ((to == NULL) ||
    5868:	2c00      	cmp	r4, #0
    586a:	d0f2      	beq.n	5852 <next_timeout+0xe>
	    ((int64_t)(to->dticks - ticks_elapsed) > (int64_t)INT_MAX)) {
    586c:	e9d4 3204 	ldrd	r3, r2, [r4, #16]
    5870:	1a1b      	subs	r3, r3, r0
    5872:	eb62 72e0 	sbc.w	r2, r2, r0, asr #31
	if ((to == NULL) ||
    5876:	f1b3 4f00 	cmp.w	r3, #2147483648	; 0x80000000
    587a:	f172 0100 	sbcs.w	r1, r2, #0
    587e:	dae8      	bge.n	5852 <next_timeout+0xe>
		ret = MAX(0, to->dticks - ticks_elapsed);
    5880:	2a00      	cmp	r2, #0
    5882:	bfac      	ite	ge
    5884:	4618      	movge	r0, r3
    5886:	2000      	movlt	r0, #0
    5888:	e7e5      	b.n	5856 <next_timeout+0x12>
    588a:	bf00      	nop
    588c:	20000174 	.word	0x20000174
    5890:	20000a20 	.word	0x20000a20

00005894 <remove_timeout>:
{
    5894:	b530      	push	{r4, r5, lr}
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    5896:	b170      	cbz	r0, 58b6 <remove_timeout+0x22>
	return (node == list->tail) ? NULL : node->next;
    5898:	4b0b      	ldr	r3, [pc, #44]	; (58c8 <remove_timeout+0x34>)
    589a:	685b      	ldr	r3, [r3, #4]
    589c:	4298      	cmp	r0, r3
    589e:	d00a      	beq.n	58b6 <remove_timeout+0x22>
    58a0:	6803      	ldr	r3, [r0, #0]
	if (next(t) != NULL) {
    58a2:	b143      	cbz	r3, 58b6 <remove_timeout+0x22>
		next(t)->dticks += t->dticks;
    58a4:	e9d3 2104 	ldrd	r2, r1, [r3, #16]
    58a8:	e9d0 4504 	ldrd	r4, r5, [r0, #16]
    58ac:	1912      	adds	r2, r2, r4
    58ae:	eb41 0105 	adc.w	r1, r1, r5
    58b2:	e9c3 2104 	strd	r2, r1, [r3, #16]
 */

static inline void sys_dlist_remove(sys_dnode_t *node)
{
	sys_dnode_t *const prev = node->prev;
	sys_dnode_t *const next = node->next;
    58b6:	e9d0 3200 	ldrd	r3, r2, [r0]

	prev->next = next;
    58ba:	6013      	str	r3, [r2, #0]
	next->prev = prev;
    58bc:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    58be:	2300      	movs	r3, #0
	node->prev = NULL;
    58c0:	e9c0 3300 	strd	r3, r3, [r0]
}
    58c4:	bd30      	pop	{r4, r5, pc}
    58c6:	bf00      	nop
    58c8:	20000174 	.word	0x20000174

000058cc <z_add_timeout>:

void z_add_timeout(struct _timeout *to, _timeout_func_t fn,
		   k_timeout_t timeout)
{
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    58cc:	f1b3 3fff 	cmp.w	r3, #4294967295
    58d0:	bf08      	it	eq
    58d2:	f1b2 3fff 	cmpeq.w	r2, #4294967295
{
    58d6:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    58d8:	4604      	mov	r4, r0
    58da:	461d      	mov	r5, r3
    58dc:	4616      	mov	r6, r2
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    58de:	d061      	beq.n	59a4 <z_add_timeout+0xd8>
#ifdef CONFIG_KERNEL_COHERENCE
	__ASSERT_NO_MSG(arch_mem_coherent(to));
#endif

	__ASSERT(!sys_dnode_is_linked(&to->node), "");
	to->fn = fn;
    58e0:	6081      	str	r1, [r0, #8]
	__asm__ volatile(
    58e2:	f04f 0320 	mov.w	r3, #32
    58e6:	f3ef 8711 	mrs	r7, BASEPRI
    58ea:	f383 8812 	msr	BASEPRI_MAX, r3
    58ee:	f3bf 8f6f 	isb	sy

	LOCKED(&timeout_lock) {
		struct _timeout *t;

		if (IS_ENABLED(CONFIG_TIMEOUT_64BIT) &&
    58f2:	3201      	adds	r2, #1
    58f4:	f175 33ff 	sbcs.w	r3, r5, #4294967295
    58f8:	da24      	bge.n	5944 <z_add_timeout+0x78>
		    Z_TICK_ABS(timeout.ticks) >= 0) {
			k_ticks_t ticks = Z_TICK_ABS(timeout.ticks) - curr_tick;
    58fa:	f06f 0301 	mvn.w	r3, #1
    58fe:	492f      	ldr	r1, [pc, #188]	; (59bc <z_add_timeout+0xf0>)
    5900:	e9d1 2000 	ldrd	r2, r0, [r1]
    5904:	1a9b      	subs	r3, r3, r2
    5906:	f04f 32ff 	mov.w	r2, #4294967295
    590a:	eb62 0000 	sbc.w	r0, r2, r0
    590e:	1b9e      	subs	r6, r3, r6
    5910:	eb60 0005 	sbc.w	r0, r0, r5

			to->dticks = MAX(1, ticks);
    5914:	2e01      	cmp	r6, #1
    5916:	f170 0300 	sbcs.w	r3, r0, #0
    591a:	da01      	bge.n	5920 <z_add_timeout+0x54>
    591c:	2601      	movs	r6, #1
    591e:	2000      	movs	r0, #0
    5920:	e9c4 6004 	strd	r6, r0, [r4, #16]
	return list->head == list;
    5924:	4e26      	ldr	r6, [pc, #152]	; (59c0 <z_add_timeout+0xf4>)
    5926:	f8d6 c000 	ldr.w	ip, [r6]
	return (node == list->tail) ? NULL : node->next;
    592a:	6875      	ldr	r5, [r6, #4]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    592c:	45b4      	cmp	ip, r6
    592e:	bf08      	it	eq
    5930:	f04f 0c00 	moveq.w	ip, #0
		} else {
			to->dticks = timeout.ticks + 1 + elapsed();
		}

		for (t = first(); t != NULL; t = next(t)) {
    5934:	f1bc 0f00 	cmp.w	ip, #0
    5938:	d10d      	bne.n	5956 <z_add_timeout+0x8a>
	node->prev = tail;
    593a:	e9c4 6500 	strd	r6, r5, [r4]
	tail->next = node;
    593e:	602c      	str	r4, [r5, #0]
	list->tail = node;
    5940:	6074      	str	r4, [r6, #4]
}
    5942:	e01c      	b.n	597e <z_add_timeout+0xb2>
			to->dticks = timeout.ticks + 1 + elapsed();
    5944:	f7ff ff74 	bl	5830 <elapsed>
    5948:	3601      	adds	r6, #1
    594a:	f145 0500 	adc.w	r5, r5, #0
    594e:	1836      	adds	r6, r6, r0
    5950:	eb45 70e0 	adc.w	r0, r5, r0, asr #31
    5954:	e7e4      	b.n	5920 <z_add_timeout+0x54>
			if (t->dticks > to->dticks) {
    5956:	e9dc 2004 	ldrd	r2, r0, [ip, #16]
    595a:	e9d4 3104 	ldrd	r3, r1, [r4, #16]
    595e:	4293      	cmp	r3, r2
    5960:	eb71 0e00 	sbcs.w	lr, r1, r0
    5964:	da1f      	bge.n	59a6 <z_add_timeout+0xda>
				t->dticks -= to->dticks;
    5966:	1ad2      	subs	r2, r2, r3
	sys_dnode_t *const prev = successor->prev;
    5968:	f8dc 3004 	ldr.w	r3, [ip, #4]
    596c:	eb60 0001 	sbc.w	r0, r0, r1
    5970:	e9cc 2004 	strd	r2, r0, [ip, #16]
	node->next = successor;
    5974:	e9c4 c300 	strd	ip, r3, [r4]
	prev->next = node;
    5978:	601c      	str	r4, [r3, #0]
	successor->prev = node;
    597a:	f8cc 4004 	str.w	r4, [ip, #4]
	return list->head == list;
    597e:	6833      	ldr	r3, [r6, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    5980:	42b3      	cmp	r3, r6
    5982:	d00b      	beq.n	599c <z_add_timeout+0xd0>

		if (t == NULL) {
			sys_dlist_append(&timeout_list, &to->node);
		}

		if (to == first()) {
    5984:	429c      	cmp	r4, r3
    5986:	d109      	bne.n	599c <z_add_timeout+0xd0>
			 * last announcement, and slice_ticks is based
			 * on that. It means that the time remaining for
			 * the next announcement can be less than
			 * slice_ticks.
			 */
			int32_t next_time = next_timeout();
    5988:	f7ff ff5c 	bl	5844 <next_timeout>

			if (next_time == 0 ||
    598c:	b118      	cbz	r0, 5996 <z_add_timeout+0xca>
			    _current_cpu->slice_ticks != next_time) {
    598e:	4b0d      	ldr	r3, [pc, #52]	; (59c4 <z_add_timeout+0xf8>)
			if (next_time == 0 ||
    5990:	691b      	ldr	r3, [r3, #16]
    5992:	4283      	cmp	r3, r0
    5994:	d002      	beq.n	599c <z_add_timeout+0xd0>
				sys_clock_set_timeout(next_time, false);
    5996:	2100      	movs	r1, #0
    5998:	f7fd fd6e 	bl	3478 <sys_clock_set_timeout>
	__asm__ volatile(
    599c:	f387 8811 	msr	BASEPRI, r7
    59a0:	f3bf 8f6f 	isb	sy
#else
			sys_clock_set_timeout(next_timeout(), false);
#endif	/* CONFIG_TIMESLICING */
		}
	}
}
    59a4:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
			to->dticks -= t->dticks;
    59a6:	1a9b      	subs	r3, r3, r2
    59a8:	eb61 0100 	sbc.w	r1, r1, r0
	return (node == list->tail) ? NULL : node->next;
    59ac:	45ac      	cmp	ip, r5
    59ae:	e9c4 3104 	strd	r3, r1, [r4, #16]
    59b2:	d0c2      	beq.n	593a <z_add_timeout+0x6e>
    59b4:	f8dc c000 	ldr.w	ip, [ip]
    59b8:	e7bc      	b.n	5934 <z_add_timeout+0x68>
    59ba:	bf00      	nop
    59bc:	20000360 	.word	0x20000360
    59c0:	20000174 	.word	0x20000174
    59c4:	20000a20 	.word	0x20000a20

000059c8 <sys_clock_announce>:
		}
	}
}

void sys_clock_announce(int32_t ticks)
{
    59c8:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    59cc:	4604      	mov	r4, r0
#ifdef CONFIG_TIMESLICING
	z_time_slice(ticks);
    59ce:	f7ff fccf 	bl	5370 <z_time_slice>
	__asm__ volatile(
    59d2:	f04f 0320 	mov.w	r3, #32
    59d6:	f3ef 8611 	mrs	r6, BASEPRI
    59da:	f383 8812 	msr	BASEPRI_MAX, r3
    59de:	f3bf 8f6f 	isb	sy
		announce_remaining += ticks;
		k_spin_unlock(&timeout_lock, key);
		return;
	}

	announce_remaining = ticks;
    59e2:	4f24      	ldr	r7, [pc, #144]	; (5a74 <sys_clock_announce+0xac>)
	return list->head == list;
    59e4:	f8df 8090 	ldr.w	r8, [pc, #144]	; 5a78 <sys_clock_announce+0xb0>
    59e8:	f8d8 0000 	ldr.w	r0, [r8]

	while (first() != NULL && first()->dticks <= announce_remaining) {
		struct _timeout *t = first();
		int dt = t->dticks;

		curr_tick += dt;
    59ec:	4a23      	ldr	r2, [pc, #140]	; (5a7c <sys_clock_announce+0xb4>)
	return sys_dlist_is_empty(list) ? NULL : list->head;
    59ee:	4540      	cmp	r0, r8
	announce_remaining = ticks;
    59f0:	603c      	str	r4, [r7, #0]
	return list->head == list;
    59f2:	ea4f 71e4 	mov.w	r1, r4, asr #31
		curr_tick += dt;
    59f6:	e9d2 3e00 	ldrd	r3, lr, [r2]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    59fa:	d00b      	beq.n	5a14 <sys_clock_announce+0x4c>
	while (first() != NULL && first()->dticks <= announce_remaining) {
    59fc:	b150      	cbz	r0, 5a14 <sys_clock_announce+0x4c>
    59fe:	e9d0 5c04 	ldrd	r5, ip, [r0, #16]
    5a02:	42ac      	cmp	r4, r5
    5a04:	eb71 090c 	sbcs.w	r9, r1, ip
    5a08:	da17      	bge.n	5a3a <sys_clock_announce+0x72>
		key = k_spin_lock(&timeout_lock);
		announce_remaining -= dt;
	}

	if (first() != NULL) {
		first()->dticks -= announce_remaining;
    5a0a:	1b2d      	subs	r5, r5, r4
    5a0c:	eb6c 0c01 	sbc.w	ip, ip, r1
    5a10:	e9c0 5c04 	strd	r5, ip, [r0, #16]
	}

	curr_tick += announce_remaining;
    5a14:	18e3      	adds	r3, r4, r3
	announce_remaining = 0;
    5a16:	f04f 0400 	mov.w	r4, #0
	curr_tick += announce_remaining;
    5a1a:	eb4e 0101 	adc.w	r1, lr, r1
    5a1e:	e9c2 3100 	strd	r3, r1, [r2]
	announce_remaining = 0;
    5a22:	603c      	str	r4, [r7, #0]

	sys_clock_set_timeout(next_timeout(), false);
    5a24:	f7ff ff0e 	bl	5844 <next_timeout>
    5a28:	4621      	mov	r1, r4
    5a2a:	f7fd fd25 	bl	3478 <sys_clock_set_timeout>
	__asm__ volatile(
    5a2e:	f386 8811 	msr	BASEPRI, r6
    5a32:	f3bf 8f6f 	isb	sy

	k_spin_unlock(&timeout_lock, key);
}
    5a36:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
		curr_tick += dt;
    5a3a:	18eb      	adds	r3, r5, r3
    5a3c:	eb4e 71e5 	adc.w	r1, lr, r5, asr #31
    5a40:	e9c2 3100 	strd	r3, r1, [r2]
		t->dticks = 0;
    5a44:	2200      	movs	r2, #0
    5a46:	2300      	movs	r3, #0
    5a48:	e9c0 2304 	strd	r2, r3, [r0, #16]
		remove_timeout(t);
    5a4c:	f7ff ff22 	bl	5894 <remove_timeout>
    5a50:	f386 8811 	msr	BASEPRI, r6
    5a54:	f3bf 8f6f 	isb	sy
		t->fn(t);
    5a58:	6883      	ldr	r3, [r0, #8]
    5a5a:	4798      	blx	r3
	__asm__ volatile(
    5a5c:	f04f 0320 	mov.w	r3, #32
    5a60:	f3ef 8611 	mrs	r6, BASEPRI
    5a64:	f383 8812 	msr	BASEPRI_MAX, r3
    5a68:	f3bf 8f6f 	isb	sy
		announce_remaining -= dt;
    5a6c:	683c      	ldr	r4, [r7, #0]
    5a6e:	1b64      	subs	r4, r4, r5
    5a70:	e7ba      	b.n	59e8 <sys_clock_announce+0x20>
    5a72:	bf00      	nop
    5a74:	20000a54 	.word	0x20000a54
    5a78:	20000174 	.word	0x20000174
    5a7c:	20000360 	.word	0x20000360

00005a80 <sys_clock_tick_get>:

int64_t sys_clock_tick_get(void)
{
    5a80:	b510      	push	{r4, lr}
    5a82:	f04f 0320 	mov.w	r3, #32
    5a86:	f3ef 8411 	mrs	r4, BASEPRI
    5a8a:	f383 8812 	msr	BASEPRI_MAX, r3
    5a8e:	f3bf 8f6f 	isb	sy
	uint64_t t = 0U;

	LOCKED(&timeout_lock) {
		t = curr_tick + elapsed();
    5a92:	f7ff fecd 	bl	5830 <elapsed>
    5a96:	4603      	mov	r3, r0
    5a98:	4a05      	ldr	r2, [pc, #20]	; (5ab0 <sys_clock_tick_get+0x30>)
    5a9a:	e9d2 0100 	ldrd	r0, r1, [r2]
    5a9e:	1818      	adds	r0, r3, r0
    5aa0:	eb41 71e3 	adc.w	r1, r1, r3, asr #31
	__asm__ volatile(
    5aa4:	f384 8811 	msr	BASEPRI, r4
    5aa8:	f3bf 8f6f 	isb	sy
	}
	return t;
}
    5aac:	bd10      	pop	{r4, pc}
    5aae:	bf00      	nop
    5ab0:	20000360 	.word	0x20000360

00005ab4 <boot_banner>:
	printk("***** delaying boot " DELAY_STR "ms (per build configuration) *****\n");
	k_busy_wait(CONFIG_BOOT_DELAY * USEC_PER_MSEC);
#endif /* defined(CONFIG_BOOT_DELAY) && (CONFIG_BOOT_DELAY > 0) */

#if CONFIG_BOOT_BANNER
	printk("*** Booting Zephyr OS build " BANNER_VERSION BANNER_POSTFIX " ***\n");
    5ab4:	4801      	ldr	r0, [pc, #4]	; (5abc <boot_banner+0x8>)
    5ab6:	f000 b998 	b.w	5dea <printk>
    5aba:	bf00      	nop
    5abc:	000079aa 	.word	0x000079aa

00005ac0 <nrf_cc3xx_platform_init_no_rng>:
    5ac0:	b510      	push	{r4, lr}
    5ac2:	4c0a      	ldr	r4, [pc, #40]	; (5aec <nrf_cc3xx_platform_init_no_rng+0x2c>)
    5ac4:	6823      	ldr	r3, [r4, #0]
    5ac6:	b11b      	cbz	r3, 5ad0 <nrf_cc3xx_platform_init_no_rng+0x10>
    5ac8:	2301      	movs	r3, #1
    5aca:	2000      	movs	r0, #0
    5acc:	6023      	str	r3, [r4, #0]
    5ace:	bd10      	pop	{r4, pc}
    5ad0:	f000 f8f4 	bl	5cbc <CC_LibInitNoRng>
    5ad4:	2800      	cmp	r0, #0
    5ad6:	d0f7      	beq.n	5ac8 <nrf_cc3xx_platform_init_no_rng+0x8>
    5ad8:	3801      	subs	r0, #1
    5ada:	2807      	cmp	r0, #7
    5adc:	d803      	bhi.n	5ae6 <nrf_cc3xx_platform_init_no_rng+0x26>
    5ade:	4b04      	ldr	r3, [pc, #16]	; (5af0 <nrf_cc3xx_platform_init_no_rng+0x30>)
    5ae0:	f853 0020 	ldr.w	r0, [r3, r0, lsl #2]
    5ae4:	bd10      	pop	{r4, pc}
    5ae6:	4803      	ldr	r0, [pc, #12]	; (5af4 <nrf_cc3xx_platform_init_no_rng+0x34>)
    5ae8:	bd10      	pop	{r4, pc}
    5aea:	bf00      	nop
    5aec:	20000a58 	.word	0x20000a58
    5af0:	000074d4 	.word	0x000074d4
    5af4:	ffff8ffe 	.word	0xffff8ffe

00005af8 <nrf_cc3xx_platform_abort>:
    5af8:	f3bf 8f4f 	dsb	sy
    5afc:	4905      	ldr	r1, [pc, #20]	; (5b14 <nrf_cc3xx_platform_abort+0x1c>)
    5afe:	4b06      	ldr	r3, [pc, #24]	; (5b18 <nrf_cc3xx_platform_abort+0x20>)
    5b00:	68ca      	ldr	r2, [r1, #12]
    5b02:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    5b06:	4313      	orrs	r3, r2
    5b08:	60cb      	str	r3, [r1, #12]
    5b0a:	f3bf 8f4f 	dsb	sy
    5b0e:	bf00      	nop
    5b10:	e7fd      	b.n	5b0e <nrf_cc3xx_platform_abort+0x16>
    5b12:	bf00      	nop
    5b14:	e000ed00 	.word	0xe000ed00
    5b18:	05fa0004 	.word	0x05fa0004

00005b1c <CC_PalAbort>:
    5b1c:	b430      	push	{r4, r5}
    5b1e:	f04f 32fe 	mov.w	r2, #4278124286	; 0xfefefefe
    5b22:	2500      	movs	r5, #0
    5b24:	4b0b      	ldr	r3, [pc, #44]	; (5b54 <CC_PalAbort+0x38>)
    5b26:	4c0c      	ldr	r4, [pc, #48]	; (5b58 <CC_PalAbort+0x3c>)
    5b28:	490c      	ldr	r1, [pc, #48]	; (5b5c <CC_PalAbort+0x40>)
    5b2a:	6849      	ldr	r1, [r1, #4]
    5b2c:	f8c3 2400 	str.w	r2, [r3, #1024]	; 0x400
    5b30:	f8c3 2404 	str.w	r2, [r3, #1028]	; 0x404
    5b34:	f8c3 2408 	str.w	r2, [r3, #1032]	; 0x408
    5b38:	f8c3 240c 	str.w	r2, [r3, #1036]	; 0x40c
    5b3c:	f8c3 2410 	str.w	r2, [r3, #1040]	; 0x410
    5b40:	f8c3 2414 	str.w	r2, [r3, #1044]	; 0x414
    5b44:	f8c3 2418 	str.w	r2, [r3, #1048]	; 0x418
    5b48:	f8c3 241c 	str.w	r2, [r3, #1052]	; 0x41c
    5b4c:	f8c4 5500 	str.w	r5, [r4, #1280]	; 0x500
    5b50:	bc30      	pop	{r4, r5}
    5b52:	4708      	bx	r1
    5b54:	50845000 	.word	0x50845000
    5b58:	50844000 	.word	0x50844000
    5b5c:	2000017c 	.word	0x2000017c

00005b60 <nrf_cc3xx_platform_set_abort>:
    5b60:	4b02      	ldr	r3, [pc, #8]	; (5b6c <nrf_cc3xx_platform_set_abort+0xc>)
    5b62:	e9d0 1200 	ldrd	r1, r2, [r0]
    5b66:	e9c3 1200 	strd	r1, r2, [r3]
    5b6a:	4770      	bx	lr
    5b6c:	2000017c 	.word	0x2000017c

00005b70 <mutex_free>:
    5b70:	b510      	push	{r4, lr}
    5b72:	4604      	mov	r4, r0
    5b74:	b150      	cbz	r0, 5b8c <mutex_free+0x1c>
    5b76:	6863      	ldr	r3, [r4, #4]
    5b78:	f013 5f68 	tst.w	r3, #973078528	; 0x3a000000
    5b7c:	d005      	beq.n	5b8a <mutex_free+0x1a>
    5b7e:	4a06      	ldr	r2, [pc, #24]	; (5b98 <mutex_free+0x28>)
    5b80:	4293      	cmp	r3, r2
    5b82:	d002      	beq.n	5b8a <mutex_free+0x1a>
    5b84:	2300      	movs	r3, #0
    5b86:	6062      	str	r2, [r4, #4]
    5b88:	6023      	str	r3, [r4, #0]
    5b8a:	bd10      	pop	{r4, pc}
    5b8c:	4b03      	ldr	r3, [pc, #12]	; (5b9c <mutex_free+0x2c>)
    5b8e:	4804      	ldr	r0, [pc, #16]	; (5ba0 <mutex_free+0x30>)
    5b90:	685b      	ldr	r3, [r3, #4]
    5b92:	4798      	blx	r3
    5b94:	e7ef      	b.n	5b76 <mutex_free+0x6>
    5b96:	bf00      	nop
    5b98:	a95c5f2c 	.word	0xa95c5f2c
    5b9c:	2000017c 	.word	0x2000017c
    5ba0:	000074f4 	.word	0x000074f4

00005ba4 <mutex_lock>:
    5ba4:	b1c8      	cbz	r0, 5bda <mutex_lock+0x36>
    5ba6:	6843      	ldr	r3, [r0, #4]
    5ba8:	4a0d      	ldr	r2, [pc, #52]	; (5be0 <mutex_lock+0x3c>)
    5baa:	4293      	cmp	r3, r2
    5bac:	d013      	beq.n	5bd6 <mutex_lock+0x32>
    5bae:	f013 5f68 	tst.w	r3, #973078528	; 0x3a000000
    5bb2:	d00e      	beq.n	5bd2 <mutex_lock+0x2e>
    5bb4:	2301      	movs	r3, #1
    5bb6:	e850 2f00 	ldrex	r2, [r0]
    5bba:	4619      	mov	r1, r3
    5bbc:	e840 1c00 	strex	ip, r1, [r0]
    5bc0:	f09c 0f00 	teq	ip, #0
    5bc4:	d1f7      	bne.n	5bb6 <mutex_lock+0x12>
    5bc6:	2a01      	cmp	r2, #1
    5bc8:	d0f5      	beq.n	5bb6 <mutex_lock+0x12>
    5bca:	f3bf 8f5f 	dmb	sy
    5bce:	2000      	movs	r0, #0
    5bd0:	4770      	bx	lr
    5bd2:	4804      	ldr	r0, [pc, #16]	; (5be4 <mutex_lock+0x40>)
    5bd4:	4770      	bx	lr
    5bd6:	4804      	ldr	r0, [pc, #16]	; (5be8 <mutex_lock+0x44>)
    5bd8:	4770      	bx	lr
    5bda:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    5bde:	4770      	bx	lr
    5be0:	a95c5f2c 	.word	0xa95c5f2c
    5be4:	ffff8fe9 	.word	0xffff8fe9
    5be8:	ffff8fea 	.word	0xffff8fea

00005bec <mutex_unlock>:
    5bec:	4603      	mov	r3, r0
    5bee:	b180      	cbz	r0, 5c12 <mutex_unlock+0x26>
    5bf0:	6842      	ldr	r2, [r0, #4]
    5bf2:	4909      	ldr	r1, [pc, #36]	; (5c18 <mutex_unlock+0x2c>)
    5bf4:	428a      	cmp	r2, r1
    5bf6:	d00a      	beq.n	5c0e <mutex_unlock+0x22>
    5bf8:	f012 5f68 	tst.w	r2, #973078528	; 0x3a000000
    5bfc:	d005      	beq.n	5c0a <mutex_unlock+0x1e>
    5bfe:	f3bf 8f5f 	dmb	sy
    5c02:	2200      	movs	r2, #0
    5c04:	4610      	mov	r0, r2
    5c06:	601a      	str	r2, [r3, #0]
    5c08:	4770      	bx	lr
    5c0a:	4804      	ldr	r0, [pc, #16]	; (5c1c <mutex_unlock+0x30>)
    5c0c:	4770      	bx	lr
    5c0e:	4804      	ldr	r0, [pc, #16]	; (5c20 <mutex_unlock+0x34>)
    5c10:	4770      	bx	lr
    5c12:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    5c16:	4770      	bx	lr
    5c18:	a95c5f2c 	.word	0xa95c5f2c
    5c1c:	ffff8fe9 	.word	0xffff8fe9
    5c20:	ffff8fea 	.word	0xffff8fea

00005c24 <mutex_init>:
    5c24:	b510      	push	{r4, lr}
    5c26:	4604      	mov	r4, r0
    5c28:	b120      	cbz	r0, 5c34 <mutex_init+0x10>
    5c2a:	2300      	movs	r3, #0
    5c2c:	4a03      	ldr	r2, [pc, #12]	; (5c3c <mutex_init+0x18>)
    5c2e:	6023      	str	r3, [r4, #0]
    5c30:	6062      	str	r2, [r4, #4]
    5c32:	bd10      	pop	{r4, pc}
    5c34:	4802      	ldr	r0, [pc, #8]	; (5c40 <mutex_init+0x1c>)
    5c36:	f7ff ff71 	bl	5b1c <CC_PalAbort>
    5c3a:	e7f6      	b.n	5c2a <mutex_init+0x6>
    5c3c:	3a00003a 	.word	0x3a00003a
    5c40:	0000751c 	.word	0x0000751c

00005c44 <nrf_cc3xx_platform_set_mutexes>:
    5c44:	b570      	push	{r4, r5, r6, lr}
    5c46:	4c19      	ldr	r4, [pc, #100]	; (5cac <nrf_cc3xx_platform_set_mutexes+0x68>)
    5c48:	f8d0 c004 	ldr.w	ip, [r0, #4]
    5c4c:	6806      	ldr	r6, [r0, #0]
    5c4e:	f8c4 c004 	str.w	ip, [r4, #4]
    5c52:	f8d0 c008 	ldr.w	ip, [r0, #8]
    5c56:	68c0      	ldr	r0, [r0, #12]
    5c58:	f8c4 c008 	str.w	ip, [r4, #8]
    5c5c:	60e0      	str	r0, [r4, #12]
    5c5e:	6026      	str	r6, [r4, #0]
    5c60:	6808      	ldr	r0, [r1, #0]
    5c62:	4b13      	ldr	r3, [pc, #76]	; (5cb0 <nrf_cc3xx_platform_set_mutexes+0x6c>)
    5c64:	4d13      	ldr	r5, [pc, #76]	; (5cb4 <nrf_cc3xx_platform_set_mutexes+0x70>)
    5c66:	6018      	str	r0, [r3, #0]
    5c68:	6848      	ldr	r0, [r1, #4]
    5c6a:	f8d5 2118 	ldr.w	r2, [r5, #280]	; 0x118
    5c6e:	6058      	str	r0, [r3, #4]
    5c70:	6888      	ldr	r0, [r1, #8]
    5c72:	f012 5f68 	tst.w	r2, #973078528	; 0x3a000000
    5c76:	6098      	str	r0, [r3, #8]
    5c78:	68c8      	ldr	r0, [r1, #12]
    5c7a:	6909      	ldr	r1, [r1, #16]
    5c7c:	60d8      	str	r0, [r3, #12]
    5c7e:	6119      	str	r1, [r3, #16]
    5c80:	d012      	beq.n	5ca8 <nrf_cc3xx_platform_set_mutexes+0x64>
    5c82:	2300      	movs	r3, #0
    5c84:	4a0c      	ldr	r2, [pc, #48]	; (5cb8 <nrf_cc3xx_platform_set_mutexes+0x74>)
    5c86:	f505 708a 	add.w	r0, r5, #276	; 0x114
    5c8a:	f8c5 3114 	str.w	r3, [r5, #276]	; 0x114
    5c8e:	f8c5 31b8 	str.w	r3, [r5, #440]	; 0x1b8
    5c92:	f8c5 2118 	str.w	r2, [r5, #280]	; 0x118
    5c96:	f8c5 21bc 	str.w	r2, [r5, #444]	; 0x1bc
    5c9a:	47b0      	blx	r6
    5c9c:	6823      	ldr	r3, [r4, #0]
    5c9e:	f505 70dc 	add.w	r0, r5, #440	; 0x1b8
    5ca2:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    5ca6:	4718      	bx	r3
    5ca8:	bd70      	pop	{r4, r5, r6, pc}
    5caa:	bf00      	nop
    5cac:	2000018c 	.word	0x2000018c
    5cb0:	2000019c 	.word	0x2000019c
    5cb4:	20000a70 	.word	0x20000a70
    5cb8:	a95c5f2c 	.word	0xa95c5f2c

00005cbc <CC_LibInitNoRng>:
    5cbc:	b508      	push	{r3, lr}
    5cbe:	f000 f811 	bl	5ce4 <CC_HalInit>
    5cc2:	b930      	cbnz	r0, 5cd2 <CC_LibInitNoRng+0x16>
    5cc4:	f000 f810 	bl	5ce8 <CC_PalInit>
    5cc8:	b938      	cbnz	r0, 5cda <CC_LibInitNoRng+0x1e>
    5cca:	4a05      	ldr	r2, [pc, #20]	; (5ce0 <CC_LibInitNoRng+0x24>)
    5ccc:	f8c2 0a0c 	str.w	r0, [r2, #2572]	; 0xa0c
    5cd0:	bd08      	pop	{r3, pc}
    5cd2:	f000 f837 	bl	5d44 <CC_PalTerminate>
    5cd6:	2003      	movs	r0, #3
    5cd8:	bd08      	pop	{r3, pc}
    5cda:	2004      	movs	r0, #4
    5cdc:	bd08      	pop	{r3, pc}
    5cde:	bf00      	nop
    5ce0:	50845000 	.word	0x50845000

00005ce4 <CC_HalInit>:
    5ce4:	2000      	movs	r0, #0
    5ce6:	4770      	bx	lr

00005ce8 <CC_PalInit>:
    5ce8:	b510      	push	{r4, lr}
    5cea:	4811      	ldr	r0, [pc, #68]	; (5d30 <CC_PalInit+0x48>)
    5cec:	f000 f848 	bl	5d80 <CC_PalMutexCreate>
    5cf0:	b100      	cbz	r0, 5cf4 <CC_PalInit+0xc>
    5cf2:	bd10      	pop	{r4, pc}
    5cf4:	480f      	ldr	r0, [pc, #60]	; (5d34 <CC_PalInit+0x4c>)
    5cf6:	f000 f843 	bl	5d80 <CC_PalMutexCreate>
    5cfa:	2800      	cmp	r0, #0
    5cfc:	d1f9      	bne.n	5cf2 <CC_PalInit+0xa>
    5cfe:	4c0e      	ldr	r4, [pc, #56]	; (5d38 <CC_PalInit+0x50>)
    5d00:	4620      	mov	r0, r4
    5d02:	f000 f83d 	bl	5d80 <CC_PalMutexCreate>
    5d06:	2800      	cmp	r0, #0
    5d08:	d1f3      	bne.n	5cf2 <CC_PalInit+0xa>
    5d0a:	4b0c      	ldr	r3, [pc, #48]	; (5d3c <CC_PalInit+0x54>)
    5d0c:	480c      	ldr	r0, [pc, #48]	; (5d40 <CC_PalInit+0x58>)
    5d0e:	601c      	str	r4, [r3, #0]
    5d10:	f000 f836 	bl	5d80 <CC_PalMutexCreate>
    5d14:	4601      	mov	r1, r0
    5d16:	2800      	cmp	r0, #0
    5d18:	d1eb      	bne.n	5cf2 <CC_PalInit+0xa>
    5d1a:	f000 f82d 	bl	5d78 <CC_PalDmaInit>
    5d1e:	4604      	mov	r4, r0
    5d20:	b108      	cbz	r0, 5d26 <CC_PalInit+0x3e>
    5d22:	4620      	mov	r0, r4
    5d24:	bd10      	pop	{r4, pc}
    5d26:	f000 f83f 	bl	5da8 <CC_PalPowerSaveModeInit>
    5d2a:	4620      	mov	r0, r4
    5d2c:	e7fa      	b.n	5d24 <CC_PalInit+0x3c>
    5d2e:	bf00      	nop
    5d30:	200001d4 	.word	0x200001d4
    5d34:	200001c8 	.word	0x200001c8
    5d38:	200001d0 	.word	0x200001d0
    5d3c:	200001d8 	.word	0x200001d8
    5d40:	200001cc 	.word	0x200001cc

00005d44 <CC_PalTerminate>:
    5d44:	b508      	push	{r3, lr}
    5d46:	4808      	ldr	r0, [pc, #32]	; (5d68 <CC_PalTerminate+0x24>)
    5d48:	f000 f824 	bl	5d94 <CC_PalMutexDestroy>
    5d4c:	4807      	ldr	r0, [pc, #28]	; (5d6c <CC_PalTerminate+0x28>)
    5d4e:	f000 f821 	bl	5d94 <CC_PalMutexDestroy>
    5d52:	4807      	ldr	r0, [pc, #28]	; (5d70 <CC_PalTerminate+0x2c>)
    5d54:	f000 f81e 	bl	5d94 <CC_PalMutexDestroy>
    5d58:	4806      	ldr	r0, [pc, #24]	; (5d74 <CC_PalTerminate+0x30>)
    5d5a:	f000 f81b 	bl	5d94 <CC_PalMutexDestroy>
    5d5e:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    5d62:	f000 b80b 	b.w	5d7c <CC_PalDmaTerminate>
    5d66:	bf00      	nop
    5d68:	200001d4 	.word	0x200001d4
    5d6c:	200001c8 	.word	0x200001c8
    5d70:	200001d0 	.word	0x200001d0
    5d74:	200001cc 	.word	0x200001cc

00005d78 <CC_PalDmaInit>:
    5d78:	2000      	movs	r0, #0
    5d7a:	4770      	bx	lr

00005d7c <CC_PalDmaTerminate>:
    5d7c:	4770      	bx	lr
    5d7e:	bf00      	nop

00005d80 <CC_PalMutexCreate>:
    5d80:	b508      	push	{r3, lr}
    5d82:	4b03      	ldr	r3, [pc, #12]	; (5d90 <CC_PalMutexCreate+0x10>)
    5d84:	6802      	ldr	r2, [r0, #0]
    5d86:	681b      	ldr	r3, [r3, #0]
    5d88:	6810      	ldr	r0, [r2, #0]
    5d8a:	4798      	blx	r3
    5d8c:	2000      	movs	r0, #0
    5d8e:	bd08      	pop	{r3, pc}
    5d90:	2000018c 	.word	0x2000018c

00005d94 <CC_PalMutexDestroy>:
    5d94:	b508      	push	{r3, lr}
    5d96:	4b03      	ldr	r3, [pc, #12]	; (5da4 <CC_PalMutexDestroy+0x10>)
    5d98:	6802      	ldr	r2, [r0, #0]
    5d9a:	685b      	ldr	r3, [r3, #4]
    5d9c:	6810      	ldr	r0, [r2, #0]
    5d9e:	4798      	blx	r3
    5da0:	2000      	movs	r0, #0
    5da2:	bd08      	pop	{r3, pc}
    5da4:	2000018c 	.word	0x2000018c

00005da8 <CC_PalPowerSaveModeInit>:
    5da8:	b570      	push	{r4, r5, r6, lr}
    5daa:	4c09      	ldr	r4, [pc, #36]	; (5dd0 <CC_PalPowerSaveModeInit+0x28>)
    5dac:	4d09      	ldr	r5, [pc, #36]	; (5dd4 <CC_PalPowerSaveModeInit+0x2c>)
    5dae:	6920      	ldr	r0, [r4, #16]
    5db0:	68ab      	ldr	r3, [r5, #8]
    5db2:	4798      	blx	r3
    5db4:	b118      	cbz	r0, 5dbe <CC_PalPowerSaveModeInit+0x16>
    5db6:	4b08      	ldr	r3, [pc, #32]	; (5dd8 <CC_PalPowerSaveModeInit+0x30>)
    5db8:	4808      	ldr	r0, [pc, #32]	; (5ddc <CC_PalPowerSaveModeInit+0x34>)
    5dba:	685b      	ldr	r3, [r3, #4]
    5dbc:	4798      	blx	r3
    5dbe:	2100      	movs	r1, #0
    5dc0:	4a07      	ldr	r2, [pc, #28]	; (5de0 <CC_PalPowerSaveModeInit+0x38>)
    5dc2:	68eb      	ldr	r3, [r5, #12]
    5dc4:	6011      	str	r1, [r2, #0]
    5dc6:	6920      	ldr	r0, [r4, #16]
    5dc8:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    5dcc:	4718      	bx	r3
    5dce:	bf00      	nop
    5dd0:	2000019c 	.word	0x2000019c
    5dd4:	2000018c 	.word	0x2000018c
    5dd8:	2000017c 	.word	0x2000017c
    5ddc:	00007540 	.word	0x00007540
    5de0:	20000a6c 	.word	0x20000a6c

00005de4 <_OffsetAbsSyms>:

#include <gen_offset.h>

#include "offsets_aarch32.c"

GEN_ABS_SYM_END
    5de4:	4770      	bx	lr

00005de6 <arch_printk_char_out>:
}
    5de6:	2000      	movs	r0, #0
    5de8:	4770      	bx	lr

00005dea <printk>:
 *
 * @param fmt formatted string to output
 */

void printk(const char *fmt, ...)
{
    5dea:	b40f      	push	{r0, r1, r2, r3}
    5dec:	b507      	push	{r0, r1, r2, lr}
    5dee:	a904      	add	r1, sp, #16
    5df0:	f851 0b04 	ldr.w	r0, [r1], #4
	va_list ap;

	va_start(ap, fmt);
    5df4:	9101      	str	r1, [sp, #4]

	vprintk(fmt, ap);
    5df6:	f7fa fbd9 	bl	5ac <vprintk>

	va_end(ap);
}
    5dfa:	b003      	add	sp, #12
    5dfc:	f85d eb04 	ldr.w	lr, [sp], #4
    5e00:	b004      	add	sp, #16
    5e02:	4770      	bx	lr

00005e04 <z_thread_entry>:
 * This routine does not return, and is marked as such so the compiler won't
 * generate preamble code that is only used by functions that actually return.
 */
FUNC_NORETURN void z_thread_entry(k_thread_entry_t entry,
				 void *p1, void *p2, void *p3)
{
    5e04:	4604      	mov	r4, r0
    5e06:	b508      	push	{r3, lr}
    5e08:	4608      	mov	r0, r1
    5e0a:	4611      	mov	r1, r2
#ifdef CONFIG_THREAD_LOCAL_STORAGE
	z_tls_current = z_current_get();
#endif
	entry(p1, p2, p3);
    5e0c:	461a      	mov	r2, r3
    5e0e:	47a0      	blx	r4
	return z_impl_z_current_get();
    5e10:	f7ff fc8e 	bl	5730 <z_impl_z_current_get>
	z_impl_k_thread_abort(thread);
    5e14:	f7fb fe52 	bl	1abc <z_impl_k_thread_abort>

00005e18 <process_recheck>:
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    5e18:	8b03      	ldrh	r3, [r0, #24]
	if ((state == ONOFF_STATE_OFF)
    5e1a:	f013 0307 	ands.w	r3, r3, #7
    5e1e:	d105      	bne.n	5e2c <process_recheck+0x14>
	    && !sys_slist_is_empty(&mgr->clients)) {
    5e20:	6803      	ldr	r3, [r0, #0]
		evt = EVT_START;
    5e22:	2b00      	cmp	r3, #0
    5e24:	bf0c      	ite	eq
    5e26:	2000      	moveq	r0, #0
    5e28:	2003      	movne	r0, #3
    5e2a:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ON)
    5e2c:	2b02      	cmp	r3, #2
    5e2e:	d105      	bne.n	5e3c <process_recheck+0x24>
		   && (mgr->refs == 0U)) {
    5e30:	8b40      	ldrh	r0, [r0, #26]
    5e32:	fab0 f080 	clz	r0, r0
    5e36:	0940      	lsrs	r0, r0, #5
    5e38:	0080      	lsls	r0, r0, #2
    5e3a:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ERROR)
    5e3c:	2b01      	cmp	r3, #1
    5e3e:	d105      	bne.n	5e4c <process_recheck+0x34>
		   && !sys_slist_is_empty(&mgr->clients)) {
    5e40:	6803      	ldr	r3, [r0, #0]
		evt = EVT_RESET;
    5e42:	2b00      	cmp	r3, #0
    5e44:	bf0c      	ite	eq
    5e46:	2000      	moveq	r0, #0
    5e48:	2005      	movne	r0, #5
    5e4a:	4770      	bx	lr
	int evt = EVT_NOP;
    5e4c:	2000      	movs	r0, #0
}
    5e4e:	4770      	bx	lr

00005e50 <validate_args>:
{
    5e50:	b510      	push	{r4, lr}
    5e52:	460c      	mov	r4, r1
	if ((mgr == NULL) || (cli == NULL)) {
    5e54:	b100      	cbz	r0, 5e58 <validate_args+0x8>
    5e56:	b911      	cbnz	r1, 5e5e <validate_args+0xe>
		return -EINVAL;
    5e58:	f06f 0015 	mvn.w	r0, #21
}
    5e5c:	bd10      	pop	{r4, pc}
	int rv = sys_notify_validate(&cli->notify);
    5e5e:	1d08      	adds	r0, r1, #4
    5e60:	f000 f895 	bl	5f8e <sys_notify_validate>
	if ((rv == 0)
    5e64:	2800      	cmp	r0, #0
    5e66:	d1f9      	bne.n	5e5c <validate_args+0xc>
	    && ((cli->notify.flags
    5e68:	68a3      	ldr	r3, [r4, #8]
    5e6a:	2b03      	cmp	r3, #3
    5e6c:	d9f6      	bls.n	5e5c <validate_args+0xc>
    5e6e:	e7f3      	b.n	5e58 <validate_args+0x8>

00005e70 <notify_one>:
{
    5e70:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    5e74:	460d      	mov	r5, r1
    5e76:	4607      	mov	r7, r0
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    5e78:	4619      	mov	r1, r3
    5e7a:	1d28      	adds	r0, r5, #4
{
    5e7c:	4690      	mov	r8, r2
    5e7e:	461e      	mov	r6, r3
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    5e80:	f000 f896 	bl	5fb0 <sys_notify_finalize>
	if (cb) {
    5e84:	4604      	mov	r4, r0
    5e86:	b138      	cbz	r0, 5e98 <notify_one+0x28>
		cb(mgr, cli, state, res);
    5e88:	4633      	mov	r3, r6
    5e8a:	4642      	mov	r2, r8
    5e8c:	4629      	mov	r1, r5
    5e8e:	4638      	mov	r0, r7
    5e90:	46a4      	mov	ip, r4
}
    5e92:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
		cb(mgr, cli, state, res);
    5e96:	4760      	bx	ip
}
    5e98:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00005e9c <transition_complete>:
{
    5e9c:	b410      	push	{r4}
	__asm__ volatile(
    5e9e:	f04f 0420 	mov.w	r4, #32
    5ea2:	f3ef 8211 	mrs	r2, BASEPRI
    5ea6:	f384 8812 	msr	BASEPRI_MAX, r4
    5eaa:	f3bf 8f6f 	isb	sy
	mgr->last_res = res;
    5eae:	6141      	str	r1, [r0, #20]
}
    5eb0:	bc10      	pop	{r4}
	process_event(mgr, EVT_COMPLETE, key);
    5eb2:	2101      	movs	r1, #1
    5eb4:	f7fa bb88 	b.w	5c8 <process_event>

00005eb8 <onoff_manager_init>:
{
    5eb8:	b538      	push	{r3, r4, r5, lr}
    5eba:	460c      	mov	r4, r1
	if ((mgr == NULL)
    5ebc:	4605      	mov	r5, r0
    5ebe:	b158      	cbz	r0, 5ed8 <onoff_manager_init+0x20>
	    || (transitions == NULL)
    5ec0:	b151      	cbz	r1, 5ed8 <onoff_manager_init+0x20>
	    || (transitions->start == NULL)
    5ec2:	680b      	ldr	r3, [r1, #0]
    5ec4:	b143      	cbz	r3, 5ed8 <onoff_manager_init+0x20>
	    || (transitions->stop == NULL)) {
    5ec6:	684b      	ldr	r3, [r1, #4]
    5ec8:	b133      	cbz	r3, 5ed8 <onoff_manager_init+0x20>
	*mgr = (struct onoff_manager)ONOFF_MANAGER_INITIALIZER(transitions);
    5eca:	221c      	movs	r2, #28
    5ecc:	2100      	movs	r1, #0
    5ece:	f000 f961 	bl	6194 <memset>
	return 0;
    5ed2:	2000      	movs	r0, #0
	*mgr = (struct onoff_manager)ONOFF_MANAGER_INITIALIZER(transitions);
    5ed4:	612c      	str	r4, [r5, #16]
}
    5ed6:	bd38      	pop	{r3, r4, r5, pc}
		return -EINVAL;
    5ed8:	f06f 0015 	mvn.w	r0, #21
    5edc:	e7fb      	b.n	5ed6 <onoff_manager_init+0x1e>

00005ede <onoff_request>:

int onoff_request(struct onoff_manager *mgr,
		  struct onoff_client *cli)
{
    5ede:	b570      	push	{r4, r5, r6, lr}
    5ee0:	4605      	mov	r5, r0
    5ee2:	460e      	mov	r6, r1
	bool add_client = false;        /* add client to pending list */
	bool start = false;             /* trigger a start transition */
	bool notify = false;            /* do client notification */
	int rv = validate_args(mgr, cli);
    5ee4:	f7ff ffb4 	bl	5e50 <validate_args>

	if (rv < 0) {
    5ee8:	1e04      	subs	r4, r0, #0
    5eea:	db15      	blt.n	5f18 <onoff_request+0x3a>
    5eec:	f04f 0320 	mov.w	r3, #32
    5ef0:	f3ef 8211 	mrs	r2, BASEPRI
    5ef4:	f383 8812 	msr	BASEPRI_MAX, r3
    5ef8:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&mgr->lock);
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;

	/* Reject if this would overflow the reference count. */
	if (mgr->refs == SERVICE_REFS_MAX) {
    5efc:	f64f 71ff 	movw	r1, #65535	; 0xffff
    5f00:	8b6b      	ldrh	r3, [r5, #26]
    5f02:	8b2c      	ldrh	r4, [r5, #24]
    5f04:	428b      	cmp	r3, r1
    5f06:	f004 0407 	and.w	r4, r4, #7
    5f0a:	d107      	bne.n	5f1c <onoff_request+0x3e>
	__asm__ volatile(
    5f0c:	f382 8811 	msr	BASEPRI, r2
    5f10:	f3bf 8f6f 	isb	sy
		rv = -EAGAIN;
    5f14:	f06f 040a 	mvn.w	r4, #10
			notify_one(mgr, cli, state, 0);
		}
	}

	return rv;
}
    5f18:	4620      	mov	r0, r4
    5f1a:	bd70      	pop	{r4, r5, r6, pc}
	if (state == ONOFF_STATE_ON) {
    5f1c:	2c02      	cmp	r4, #2
    5f1e:	d10c      	bne.n	5f3a <onoff_request+0x5c>
		mgr->refs += 1U;
    5f20:	3301      	adds	r3, #1
    5f22:	836b      	strh	r3, [r5, #26]
    5f24:	f382 8811 	msr	BASEPRI, r2
    5f28:	f3bf 8f6f 	isb	sy
			notify_one(mgr, cli, state, 0);
    5f2c:	2300      	movs	r3, #0
    5f2e:	4622      	mov	r2, r4
    5f30:	4631      	mov	r1, r6
    5f32:	4628      	mov	r0, r5
    5f34:	f7ff ff9c 	bl	5e70 <notify_one>
    5f38:	e7ee      	b.n	5f18 <onoff_request+0x3a>
	} else if ((state == ONOFF_STATE_OFF)
    5f3a:	2c06      	cmp	r4, #6
    5f3c:	d814      	bhi.n	5f68 <onoff_request+0x8a>
    5f3e:	e8df f004 	tbb	[pc, r4]
    5f42:	1304      	.short	0x1304
    5f44:	1a041313 	.word	0x1a041313
    5f48:	04          	.byte	0x04
    5f49:	00          	.byte	0x00
	parent->next = child;
    5f4a:	2300      	movs	r3, #0
    5f4c:	6033      	str	r3, [r6, #0]
 *
 * @return A pointer on the last node of the list (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_tail(sys_slist_t *list)
{
	return list->tail;
    5f4e:	686b      	ldr	r3, [r5, #4]
 * @param node A pointer on the node to append
 */
static inline void sys_slist_append(sys_slist_t *list,
				    sys_snode_t *node);

Z_GENLIST_APPEND(slist, snode)
    5f50:	b93b      	cbnz	r3, 5f62 <onoff_request+0x84>
	list->head = node;
    5f52:	e9c5 6600 	strd	r6, r6, [r5]
	if (start) {
    5f56:	b9ac      	cbnz	r4, 5f84 <onoff_request+0xa6>
		process_event(mgr, EVT_RECHECK, key);
    5f58:	2102      	movs	r1, #2
    5f5a:	4628      	mov	r0, r5
    5f5c:	f7fa fb34 	bl	5c8 <process_event>
    5f60:	e7da      	b.n	5f18 <onoff_request+0x3a>
	parent->next = child;
    5f62:	601e      	str	r6, [r3, #0]
	list->tail = node;
    5f64:	606e      	str	r6, [r5, #4]
}
    5f66:	e7f6      	b.n	5f56 <onoff_request+0x78>
    5f68:	f382 8811 	msr	BASEPRI, r2
    5f6c:	f3bf 8f6f 	isb	sy
		rv = -EIO;
    5f70:	f06f 0404 	mvn.w	r4, #4
    5f74:	e7d0      	b.n	5f18 <onoff_request+0x3a>
    5f76:	f382 8811 	msr	BASEPRI, r2
    5f7a:	f3bf 8f6f 	isb	sy
    5f7e:	f06f 0485 	mvn.w	r4, #133	; 0x85
    5f82:	e7c9      	b.n	5f18 <onoff_request+0x3a>
    5f84:	f382 8811 	msr	BASEPRI, r2
    5f88:	f3bf 8f6f 	isb	sy
		if (notify) {
    5f8c:	e7c4      	b.n	5f18 <onoff_request+0x3a>

00005f8e <sys_notify_validate>:

int sys_notify_validate(struct sys_notify *notify)
{
	int rv = 0;

	if (notify == NULL) {
    5f8e:	4603      	mov	r3, r0
    5f90:	b158      	cbz	r0, 5faa <sys_notify_validate+0x1c>
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    5f92:	6842      	ldr	r2, [r0, #4]
	return method & SYS_NOTIFY_METHOD_MASK;
    5f94:	f002 0203 	and.w	r2, r2, #3
		return -EINVAL;
	}

	/* Validate configuration based on mode */
	switch (sys_notify_get_method(notify)) {
    5f98:	2a01      	cmp	r2, #1
    5f9a:	d003      	beq.n	5fa4 <sys_notify_validate+0x16>
    5f9c:	2a03      	cmp	r2, #3
    5f9e:	d104      	bne.n	5faa <sys_notify_validate+0x1c>
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		if (notify->method.callback == NULL) {
    5fa0:	6802      	ldr	r2, [r0, #0]
    5fa2:	b112      	cbz	r2, 5faa <sys_notify_validate+0x1c>
		break;
	}

	/* Clear the result here instead of in all callers. */
	if (rv == 0) {
		notify->result = 0;
    5fa4:	2000      	movs	r0, #0
    5fa6:	6098      	str	r0, [r3, #8]
    5fa8:	4770      	bx	lr
    5faa:	f06f 0015 	mvn.w	r0, #21
	}

	return rv;
}
    5fae:	4770      	bx	lr

00005fb0 <sys_notify_finalize>:
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    5fb0:	6842      	ldr	r2, [r0, #4]

sys_notify_generic_callback sys_notify_finalize(struct sys_notify *notify,
						    int res)
{
    5fb2:	4603      	mov	r3, r0
	return method & SYS_NOTIFY_METHOD_MASK;
    5fb4:	f002 0203 	and.w	r2, r2, #3

	/* Store the result and capture secondary notification
	 * information.
	 */
	notify->result = res;
	switch (method) {
    5fb8:	2a03      	cmp	r2, #3
    5fba:	f04f 0200 	mov.w	r2, #0
	notify->result = res;
    5fbe:	6081      	str	r1, [r0, #8]
	sys_notify_generic_callback rv = NULL;
    5fc0:	bf14      	ite	ne
    5fc2:	4610      	movne	r0, r2
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		rv = notify->method.callback;
    5fc4:	6800      	ldreq	r0, [r0, #0]
	/* Mark completion by clearing the flags field to the
	 * completed state, releasing any spin-waiters, then complete
	 * secondary notification.
	 */
	compiler_barrier();
	notify->flags = SYS_NOTIFY_METHOD_COMPLETED;
    5fc6:	605a      	str	r2, [r3, #4]
	if (IS_ENABLED(CONFIG_POLL) && (sig != NULL)) {
		k_poll_signal_raise(sig, res);
	}

	return rv;
}
    5fc8:	4770      	bx	lr

00005fca <encode_uint>:
{
    5fca:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    5fce:	469a      	mov	sl, r3
	bool upcase = isupper((int)conv->specifier);
    5fd0:	78d3      	ldrb	r3, [r2, #3]
{
    5fd2:	4680      	mov	r8, r0
	switch (specifier) {
    5fd4:	2b6f      	cmp	r3, #111	; 0x6f
{
    5fd6:	460f      	mov	r7, r1
    5fd8:	4615      	mov	r5, r2
	return (int)(((unsigned)(a)-(unsigned)'A') < 26U);
    5fda:	f1a3 0b41 	sub.w	fp, r3, #65	; 0x41
	switch (specifier) {
    5fde:	d029      	beq.n	6034 <encode_uint+0x6a>
    5fe0:	d824      	bhi.n	602c <encode_uint+0x62>
		return 10;
    5fe2:	2b58      	cmp	r3, #88	; 0x58
    5fe4:	bf0c      	ite	eq
    5fe6:	2610      	moveq	r6, #16
    5fe8:	260a      	movne	r6, #10
	char *bp = bps + (bpe - bps);
    5fea:	f8dd 9028 	ldr.w	r9, [sp, #40]	; 0x28
		unsigned int lsv = (unsigned int)(value % radix);
    5fee:	4632      	mov	r2, r6
    5ff0:	2300      	movs	r3, #0
    5ff2:	4640      	mov	r0, r8
    5ff4:	4639      	mov	r1, r7
    5ff6:	f7fa f8ad 	bl	154 <__aeabi_uldivmod>
		*--bp = (lsv <= 9) ? ('0' + lsv)
    5ffa:	2a09      	cmp	r2, #9
    5ffc:	b2d4      	uxtb	r4, r2
    5ffe:	d81e      	bhi.n	603e <encode_uint+0x74>
    6000:	3430      	adds	r4, #48	; 0x30
	} while ((value != 0) && (bps < bp));
    6002:	45b0      	cmp	r8, r6
		*--bp = (lsv <= 9) ? ('0' + lsv)
    6004:	b2e4      	uxtb	r4, r4
	} while ((value != 0) && (bps < bp));
    6006:	f177 0700 	sbcs.w	r7, r7, #0
		*--bp = (lsv <= 9) ? ('0' + lsv)
    600a:	f809 4d01 	strb.w	r4, [r9, #-1]!
	} while ((value != 0) && (bps < bp));
    600e:	d301      	bcc.n	6014 <encode_uint+0x4a>
    6010:	45d1      	cmp	r9, sl
    6012:	d811      	bhi.n	6038 <encode_uint+0x6e>
	if (conv->flag_hash) {
    6014:	782b      	ldrb	r3, [r5, #0]
    6016:	069b      	lsls	r3, r3, #26
    6018:	d505      	bpl.n	6026 <encode_uint+0x5c>
		if (radix == 8) {
    601a:	2e08      	cmp	r6, #8
    601c:	d115      	bne.n	604a <encode_uint+0x80>
			conv->altform_0 = true;
    601e:	78ab      	ldrb	r3, [r5, #2]
    6020:	f043 0308 	orr.w	r3, r3, #8
			conv->altform_0c = true;
    6024:	70ab      	strb	r3, [r5, #2]
}
    6026:	4648      	mov	r0, r9
    6028:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
	switch (specifier) {
    602c:	f003 03f7 	and.w	r3, r3, #247	; 0xf7
		return 10;
    6030:	2b70      	cmp	r3, #112	; 0x70
    6032:	e7d7      	b.n	5fe4 <encode_uint+0x1a>
	switch (specifier) {
    6034:	2608      	movs	r6, #8
    6036:	e7d8      	b.n	5fea <encode_uint+0x20>
		value /= radix;
    6038:	4680      	mov	r8, r0
    603a:	460f      	mov	r7, r1
    603c:	e7d7      	b.n	5fee <encode_uint+0x24>
		*--bp = (lsv <= 9) ? ('0' + lsv)
    603e:	f1bb 0f19 	cmp.w	fp, #25
    6042:	bf94      	ite	ls
    6044:	3437      	addls	r4, #55	; 0x37
    6046:	3457      	addhi	r4, #87	; 0x57
    6048:	e7db      	b.n	6002 <encode_uint+0x38>
		} else if (radix == 16) {
    604a:	2e10      	cmp	r6, #16
    604c:	d1eb      	bne.n	6026 <encode_uint+0x5c>
			conv->altform_0c = true;
    604e:	78ab      	ldrb	r3, [r5, #2]
    6050:	f043 0310 	orr.w	r3, r3, #16
    6054:	e7e6      	b.n	6024 <encode_uint+0x5a>

00006056 <outs>:
{
    6056:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    605a:	4607      	mov	r7, r0
    605c:	4688      	mov	r8, r1
    605e:	4615      	mov	r5, r2
    6060:	461e      	mov	r6, r3
	while ((sp < ep) || ((ep == NULL) && *sp)) {
    6062:	4614      	mov	r4, r2
    6064:	42b4      	cmp	r4, r6
    6066:	d305      	bcc.n	6074 <outs+0x1e>
    6068:	b10e      	cbz	r6, 606e <outs+0x18>
	return (int)count;
    606a:	1b60      	subs	r0, r4, r5
    606c:	e008      	b.n	6080 <outs+0x2a>
	while ((sp < ep) || ((ep == NULL) && *sp)) {
    606e:	7823      	ldrb	r3, [r4, #0]
    6070:	2b00      	cmp	r3, #0
    6072:	d0fa      	beq.n	606a <outs+0x14>
		int rc = out((int)*sp++, ctx);
    6074:	4641      	mov	r1, r8
    6076:	f814 0b01 	ldrb.w	r0, [r4], #1
    607a:	47b8      	blx	r7
		if (rc < 0) {
    607c:	2800      	cmp	r0, #0
    607e:	daf1      	bge.n	6064 <outs+0xe>
}
    6080:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00006084 <_ConfigAbsSyms>:
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_BUILD_OUTPUT_BIN, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_WARN_DEPRECATED, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_ENFORCE_ZEPHYR_STDINT, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_COMPAT_INCLUDES, 1);

GEN_ABS_SYM_END
    6084:	4770      	bx	lr

00006086 <pm_state_exit_post_ops>:
    6086:	2300      	movs	r3, #0
    6088:	f383 8811 	msr	BASEPRI, r3
    608c:	f3bf 8f6f 	isb	sy
	/*
	 * System is now in active mode. Reenable interrupts which were disabled
	 * when OS started idling code.
	 */
	irq_unlock(0);
}
    6090:	4770      	bx	lr

00006092 <abort_function>:
	sys_reboot(SYS_REBOOT_WARM);
    6092:	2000      	movs	r0, #0
{
    6094:	b508      	push	{r3, lr}
	sys_reboot(SYS_REBOOT_WARM);
    6096:	f7fa ff57 	bl	f48 <sys_reboot>

0000609a <z_arm_fatal_error>:
{

	if (esf != NULL) {
		esf_dump(esf);
	}
	z_fatal_error(reason, esf);
    609a:	f000 bd85 	b.w	6ba8 <z_fatal_error>

0000609e <z_do_kernel_oops>:
 *
 * @param esf exception frame
 * @param callee_regs Callee-saved registers (R4-R11)
 */
void z_do_kernel_oops(const z_arch_esf_t *esf, _callee_saved_t *callee_regs)
{
    609e:	4601      	mov	r1, r0
	z_fatal_error(reason, esf);
    60a0:	6800      	ldr	r0, [r0, #0]
    60a2:	f000 bd81 	b.w	6ba8 <z_fatal_error>

000060a6 <z_irq_spurious>:
 */
void z_irq_spurious(const void *unused)
{
	ARG_UNUSED(unused);

	z_arm_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
    60a6:	2100      	movs	r1, #0
    60a8:	2001      	movs	r0, #1
    60aa:	f7ff bff6 	b.w	609a <z_arm_fatal_error>

000060ae <z_arm_nmi>:
 * Simply call what is installed in 'static void(*handler)(void)'.
 *
 */

void z_arm_nmi(void)
{
    60ae:	b508      	push	{r3, lr}
	handler();
    60b0:	f7fb faae 	bl	1610 <z_SysNmiOnReset>
	z_arm_int_exit();
}
    60b4:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	z_arm_int_exit();
    60b8:	f7fb bb70 	b.w	179c <z_arm_exc_exit>

000060bc <configure_builtin_stack_guard>:
  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
    60bc:	6e43      	ldr	r3, [r0, #100]	; 0x64
    60be:	f383 880b 	msr	PSPLIM, r3
}
    60c2:	4770      	bx	lr

000060c4 <arm_cmse_mpu_region_get>:
__CMSE_TT_ASM ()

__extension__ static __inline __attribute__ ((__always_inline__))
cmse_address_info_t
cmse_TT (void *__p)
__CMSE_TT_ASM ()
    60c4:	e840 f300 	tt	r3, r0
int arm_cmse_mpu_region_get(uint32_t addr)
{
	cmse_address_info_t addr_info =	cmse_TT((void *)addr);

	if (addr_info.flags.mpu_region_valid) {
		return addr_info.flags.mpu_region;
    60c8:	f413 3f80 	tst.w	r3, #65536	; 0x10000
    60cc:	b2d8      	uxtb	r0, r3
	}

	return -EINVAL;
}
    60ce:	bf08      	it	eq
    60d0:	f06f 0015 	mvneq.w	r0, #21
    60d4:	4770      	bx	lr

000060d6 <mpu_configure_region>:
{
    60d6:	b57f      	push	{r0, r1, r2, r3, r4, r5, r6, lr}
	p_attr->rbar = attr->rbar &
    60d8:	890a      	ldrh	r2, [r1, #8]
    60da:	894e      	ldrh	r6, [r1, #10]
	region_conf.base = new_region->start;
    60dc:	680b      	ldr	r3, [r1, #0]
		&new_region->attr, new_region->start, new_region->size);
    60de:	684d      	ldr	r5, [r1, #4]
    60e0:	f002 021f 	and.w	r2, r2, #31
    60e4:	ea42 1246 	orr.w	r2, r2, r6, lsl #5
	region_conf.base = new_region->start;
    60e8:	9300      	str	r3, [sp, #0]
    60ea:	f88d 2008 	strb.w	r2, [sp, #8]
	p_attr->r_limit = REGION_LIMIT_ADDR(base, size);
    60ee:	f023 031f 	bic.w	r3, r3, #31
    60f2:	1e6a      	subs	r2, r5, #1
    60f4:	4413      	add	r3, r2
    60f6:	f023 031f 	bic.w	r3, r3, #31
	if (index > (get_num_regions() - 1U)) {
    60fa:	2807      	cmp	r0, #7
    60fc:	9303      	str	r3, [sp, #12]
    60fe:	d804      	bhi.n	610a <mpu_configure_region+0x34>
	region_init(index, region_conf);
    6100:	4669      	mov	r1, sp
    6102:	f7fb fd0d 	bl	1b20 <region_init>
}
    6106:	b004      	add	sp, #16
    6108:	bd70      	pop	{r4, r5, r6, pc}
		return -EINVAL;
    610a:	f06f 0015 	mvn.w	r0, #21
	return region_allocate_and_init(index,
    610e:	e7fa      	b.n	6106 <mpu_configure_region+0x30>

00006110 <strlen>:
 *
 * @return number of bytes in string <s>
 */

size_t strlen(const char *s)
{
    6110:	4603      	mov	r3, r0
	size_t n = 0;
    6112:	2000      	movs	r0, #0

	while (*s != '\0') {
    6114:	5c1a      	ldrb	r2, [r3, r0]
    6116:	b902      	cbnz	r2, 611a <strlen+0xa>
		s++;
		n++;
	}

	return n;
}
    6118:	4770      	bx	lr
		n++;
    611a:	3001      	adds	r0, #1
    611c:	e7fa      	b.n	6114 <strlen+0x4>

0000611e <strnlen>:
 *
 * @return number of bytes in fixed-size string <s>
 */

size_t strnlen(const char *s, size_t maxlen)
{
    611e:	4603      	mov	r3, r0
	size_t n = 0;
    6120:	2000      	movs	r0, #0

	while (*s != '\0' && n < maxlen) {
    6122:	5c1a      	ldrb	r2, [r3, r0]
    6124:	b10a      	cbz	r2, 612a <strnlen+0xc>
    6126:	4288      	cmp	r0, r1
    6128:	d100      	bne.n	612c <strnlen+0xe>
		s++;
		n++;
	}

	return n;
}
    612a:	4770      	bx	lr
		n++;
    612c:	3001      	adds	r0, #1
    612e:	e7f8      	b.n	6122 <strnlen+0x4>

00006130 <memcmp>:
 * @brief Compare two memory areas
 *
 * @return negative # if <m1> < <m2>, 0 if <m1> == <m2>, else positive #
 */
int memcmp(const void *m1, const void *m2, size_t n)
{
    6130:	b510      	push	{r4, lr}
	const char *c1 = m1;
	const char *c2 = m2;

	if (!n) {
    6132:	b15a      	cbz	r2, 614c <memcmp+0x1c>
    6134:	3901      	subs	r1, #1
    6136:	1884      	adds	r4, r0, r2
		return 0;
	}

	while ((--n > 0) && (*c1 == *c2)) {
    6138:	f810 2b01 	ldrb.w	r2, [r0], #1
    613c:	f811 3f01 	ldrb.w	r3, [r1, #1]!
    6140:	42a0      	cmp	r0, r4
    6142:	d001      	beq.n	6148 <memcmp+0x18>
    6144:	429a      	cmp	r2, r3
    6146:	d0f7      	beq.n	6138 <memcmp+0x8>
		c1++;
		c2++;
	}

	return *c1 - *c2;
    6148:	1ad0      	subs	r0, r2, r3
}
    614a:	bd10      	pop	{r4, pc}
		return 0;
    614c:	4610      	mov	r0, r2
    614e:	e7fc      	b.n	614a <memcmp+0x1a>

00006150 <memmove>:
void *memmove(void *d, const void *s, size_t n)
{
	char *dest = d;
	const char *src  = s;

	if ((size_t) (dest - src) < n) {
    6150:	1a43      	subs	r3, r0, r1
    6152:	4293      	cmp	r3, r2
{
    6154:	b510      	push	{r4, lr}
    6156:	eb00 0302 	add.w	r3, r0, r2
	if ((size_t) (dest - src) < n) {
    615a:	d308      	bcc.n	616e <memmove+0x1e>
	char *dest = d;
    615c:	4602      	mov	r2, r0
    615e:	3901      	subs	r1, #1
			n--;
			dest[n] = src[n];
		}
	} else {
		/* It is safe to perform a forward-copy */
		while (n > 0) {
    6160:	429a      	cmp	r2, r3
    6162:	d00b      	beq.n	617c <memmove+0x2c>
			*dest = *src;
    6164:	f811 4f01 	ldrb.w	r4, [r1, #1]!
    6168:	f802 4b01 	strb.w	r4, [r2], #1
			dest++;
			src++;
			n--;
    616c:	e7f8      	b.n	6160 <memmove+0x10>
    616e:	440a      	add	r2, r1
			dest[n] = src[n];
    6170:	f812 4d01 	ldrb.w	r4, [r2, #-1]!
		while (n > 0) {
    6174:	428a      	cmp	r2, r1
			dest[n] = src[n];
    6176:	f803 4d01 	strb.w	r4, [r3, #-1]!
		while (n > 0) {
    617a:	d1f9      	bne.n	6170 <memmove+0x20>
		}
	}

	return d;
}
    617c:	bd10      	pop	{r4, pc}

0000617e <memcpy>:
 *
 * @return pointer to start of destination buffer
 */

void *memcpy(void *ZRESTRICT d, const void *ZRESTRICT s, size_t n)
{
    617e:	b510      	push	{r4, lr}
    6180:	1e43      	subs	r3, r0, #1
    6182:	440a      	add	r2, r1
	}
#endif

	/* do byte-sized copying until finished */

	while (n > 0) {
    6184:	4291      	cmp	r1, r2
    6186:	d100      	bne.n	618a <memcpy+0xc>
		*(d_byte++) = *(s_byte++);
		n--;
	}

	return d;
}
    6188:	bd10      	pop	{r4, pc}
		*(d_byte++) = *(s_byte++);
    618a:	f811 4b01 	ldrb.w	r4, [r1], #1
    618e:	f803 4f01 	strb.w	r4, [r3, #1]!
		n--;
    6192:	e7f7      	b.n	6184 <memcpy+0x6>

00006194 <memset>:

void *memset(void *buf, int c, size_t n)
{
	/* do byte-sized initialization until word-aligned or finished */

	unsigned char *d_byte = (unsigned char *)buf;
    6194:	4603      	mov	r3, r0
	unsigned char c_byte = (unsigned char)c;
    6196:	b2c9      	uxtb	r1, r1
	/* do byte-sized initialization until finished */

	d_byte = (unsigned char *)d_word;
#endif

	while (n > 0) {
    6198:	4402      	add	r2, r0
    619a:	4293      	cmp	r3, r2
    619c:	d100      	bne.n	61a0 <memset+0xc>
		*(d_byte++) = c_byte;
		n--;
	}

	return buf;
}
    619e:	4770      	bx	lr
		*(d_byte++) = c_byte;
    61a0:	f803 1b01 	strb.w	r1, [r3], #1
		n--;
    61a4:	e7f9      	b.n	619a <memset+0x6>

000061a6 <_stdout_hook_default>:
}
    61a6:	f04f 30ff 	mov.w	r0, #4294967295
    61aa:	4770      	bx	lr

000061ac <fputc>:
		union { uintptr_t x; FILE * val; } parm1 = { .val = stream };
		return (int) arch_syscall_invoke2(parm0.x, parm1.x, K_SYSCALL_ZEPHYR_FPUTC);
	}
#endif
	compiler_barrier();
	return z_impl_zephyr_fputc(c, stream);
    61ac:	f7fb be20 	b.w	1df0 <z_impl_zephyr_fputc>

000061b0 <get_status>:
	return GET_STATUS(get_sub_data(dev, type)->flags);
    61b0:	220c      	movs	r2, #12
    61b2:	6903      	ldr	r3, [r0, #16]
    61b4:	b2c9      	uxtb	r1, r1
    61b6:	fb01 3302 	mla	r3, r1, r2, r3
    61ba:	6f98      	ldr	r0, [r3, #120]	; 0x78
}
    61bc:	f000 0007 	and.w	r0, r0, #7
    61c0:	4770      	bx	lr

000061c2 <set_on_state>:
	__asm__ volatile(
    61c2:	f04f 0320 	mov.w	r3, #32
    61c6:	f3ef 8211 	mrs	r2, BASEPRI
    61ca:	f383 8812 	msr	BASEPRI_MAX, r3
    61ce:	f3bf 8f6f 	isb	sy
	*flags = CLOCK_CONTROL_STATUS_ON | GET_CTX(*flags);
    61d2:	6803      	ldr	r3, [r0, #0]
    61d4:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
    61d8:	f043 0302 	orr.w	r3, r3, #2
    61dc:	6003      	str	r3, [r0, #0]
	__asm__ volatile(
    61de:	f382 8811 	msr	BASEPRI, r2
    61e2:	f3bf 8f6f 	isb	sy
}
    61e6:	4770      	bx	lr

000061e8 <stop>:
{
    61e8:	b570      	push	{r4, r5, r6, lr}
    61ea:	b2c9      	uxtb	r1, r1
	struct nrf_clock_control_data *data = dev->data;
    61ec:	6903      	ldr	r3, [r0, #16]
	__asm__ volatile(
    61ee:	f04f 0420 	mov.w	r4, #32
    61f2:	f3ef 8511 	mrs	r5, BASEPRI
    61f6:	f384 8812 	msr	BASEPRI_MAX, r4
    61fa:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    61fe:	260c      	movs	r6, #12
    6200:	fb06 3401 	mla	r4, r6, r1, r3
    6204:	6fa4      	ldr	r4, [r4, #120]	; 0x78
	if ((current_ctx != 0) && (current_ctx != ctx)) {
    6206:	f014 04c0 	ands.w	r4, r4, #192	; 0xc0
    620a:	d008      	beq.n	621e <stop+0x36>
    620c:	42a2      	cmp	r2, r4
    620e:	d006      	beq.n	621e <stop+0x36>
	__asm__ volatile(
    6210:	f385 8811 	msr	BASEPRI, r5
    6214:	f3bf 8f6f 	isb	sy
		err = -EPERM;
    6218:	f04f 30ff 	mov.w	r0, #4294967295
}
    621c:	bd70      	pop	{r4, r5, r6, pc}
		*flags = CLOCK_CONTROL_STATUS_OFF;
    621e:	2201      	movs	r2, #1
    6220:	fb06 3301 	mla	r3, r6, r1, r3
    6224:	679a      	str	r2, [r3, #120]	; 0x78
    6226:	f385 8811 	msr	BASEPRI, r5
    622a:	f3bf 8f6f 	isb	sy
	get_sub_config(dev, type)->stop();
    622e:	6843      	ldr	r3, [r0, #4]
    6230:	eb03 03c1 	add.w	r3, r3, r1, lsl #3
    6234:	685b      	ldr	r3, [r3, #4]
    6236:	4798      	blx	r3
	return 0;
    6238:	2000      	movs	r0, #0
    623a:	e7ef      	b.n	621c <stop+0x34>

0000623c <api_stop>:
	return stop(dev, subsys, CTX_API);
    623c:	2280      	movs	r2, #128	; 0x80
    623e:	f7ff bfd3 	b.w	61e8 <stop>

00006242 <async_start>:
{
    6242:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    6244:	9f06      	ldr	r7, [sp, #24]
	struct nrf_clock_control_data *data = dev->data;
    6246:	6904      	ldr	r4, [r0, #16]
	return &data->subsys[type];
    6248:	b2c9      	uxtb	r1, r1
	__asm__ volatile(
    624a:	f04f 0520 	mov.w	r5, #32
    624e:	f3ef 8611 	mrs	r6, BASEPRI
    6252:	f385 8812 	msr	BASEPRI_MAX, r5
    6256:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    625a:	250c      	movs	r5, #12
    625c:	fb05 4401 	mla	r4, r5, r1, r4
    6260:	6fa5      	ldr	r5, [r4, #120]	; 0x78
	if ((*flags & (STATUS_MASK)) == CLOCK_CONTROL_STATUS_OFF) {
    6262:	f005 0c07 	and.w	ip, r5, #7
    6266:	f1bc 0f01 	cmp.w	ip, #1
    626a:	d10c      	bne.n	6286 <async_start+0x44>
		*flags = CLOCK_CONTROL_STATUS_STARTING | ctx;
    626c:	67a7      	str	r7, [r4, #120]	; 0x78
	__asm__ volatile(
    626e:	f386 8811 	msr	BASEPRI, r6
    6272:	f3bf 8f6f 	isb	sy
	subdata->user_data = user_data;
    6276:	e9c4 231c 	strd	r2, r3, [r4, #112]	; 0x70
	 get_sub_config(dev, type)->start();
    627a:	6843      	ldr	r3, [r0, #4]
    627c:	f853 3031 	ldr.w	r3, [r3, r1, lsl #3]
    6280:	4798      	blx	r3
	return 0;
    6282:	2000      	movs	r0, #0
}
    6284:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	uint32_t current_ctx = GET_CTX(*flags);
    6286:	f005 05c0 	and.w	r5, r5, #192	; 0xc0
	} else if (current_ctx != ctx) {
    628a:	42af      	cmp	r7, r5
    628c:	f386 8811 	msr	BASEPRI, r6
    6290:	f3bf 8f6f 	isb	sy
		err = -EALREADY;
    6294:	bf0c      	ite	eq
    6296:	f06f 0077 	mvneq.w	r0, #119	; 0x77
		err = -EPERM;
    629a:	f04f 30ff 	movne.w	r0, #4294967295
    629e:	e7f1      	b.n	6284 <async_start+0x42>

000062a0 <api_start>:
{
    62a0:	b513      	push	{r0, r1, r4, lr}
	return async_start(dev, subsys, cb, user_data, CTX_API);
    62a2:	2480      	movs	r4, #128	; 0x80
    62a4:	9400      	str	r4, [sp, #0]
    62a6:	f7ff ffcc 	bl	6242 <async_start>
}
    62aa:	b002      	add	sp, #8
    62ac:	bd10      	pop	{r4, pc}

000062ae <onoff_started_callback>:
{
    62ae:	b410      	push	{r4}
	notify(mgr, 0);
    62b0:	241c      	movs	r4, #28
	return &data->mgr[type];
    62b2:	6900      	ldr	r0, [r0, #16]
    62b4:	b2cb      	uxtb	r3, r1
	notify(mgr, 0);
    62b6:	fb03 0004 	mla	r0, r3, r4, r0
    62ba:	2100      	movs	r1, #0
}
    62bc:	bc10      	pop	{r4}
	notify(mgr, 0);
    62be:	4710      	bx	r2

000062c0 <hfclkaudio_start>:
	nrfx_clock_start(NRF_CLOCK_DOMAIN_HFCLKAUDIO);
    62c0:	2003      	movs	r0, #3
    62c2:	f000 bb85 	b.w	69d0 <nrfx_clock_start>

000062c6 <hfclk192m_start>:
	nrfx_clock_start(NRF_CLOCK_DOMAIN_HFCLK192M);
    62c6:	2002      	movs	r0, #2
    62c8:	f000 bb82 	b.w	69d0 <nrfx_clock_start>

000062cc <lfclk_start>:
    nrfx_clock_start(NRF_CLOCK_DOMAIN_LFCLK);
    62cc:	2000      	movs	r0, #0
    62ce:	f000 bb7f 	b.w	69d0 <nrfx_clock_start>

000062d2 <hfclkaudio_stop>:
	nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLKAUDIO);
    62d2:	2003      	movs	r0, #3
    62d4:	f000 bbdb 	b.w	6a8e <nrfx_clock_stop>

000062d8 <hfclk192m_stop>:
	nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLK192M);
    62d8:	2002      	movs	r0, #2
    62da:	f000 bbd8 	b.w	6a8e <nrfx_clock_stop>

000062de <lfclk_stop>:
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
    62de:	2000      	movs	r0, #0
    62e0:	f000 bbd5 	b.w	6a8e <nrfx_clock_stop>

000062e4 <blocking_start_callback>:
{
    62e4:	4610      	mov	r0, r2
	z_impl_k_sem_give(sem);
    62e6:	f7fe bef9 	b.w	50dc <z_impl_k_sem_give>

000062ea <gpio_nrfx_port_get_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    62ea:	6843      	ldr	r3, [r0, #4]
}
    62ec:	2000      	movs	r0, #0
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    62ee:	685b      	ldr	r3, [r3, #4]
    return p_reg->IN;
    62f0:	691b      	ldr	r3, [r3, #16]
	*value = nrf_gpio_port_in_read(reg);
    62f2:	600b      	str	r3, [r1, #0]
}
    62f4:	4770      	bx	lr

000062f6 <gpio_nrfx_port_set_masked_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    62f6:	6843      	ldr	r3, [r0, #4]
	const uint32_t set_mask = value & mask;
    62f8:	ea02 0001 	and.w	r0, r2, r1
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    62fc:	685b      	ldr	r3, [r3, #4]
	const uint32_t clear_mask = (~set_mask) & mask;
    62fe:	ea21 0102 	bic.w	r1, r1, r2
    p_reg->OUTSET = set_mask;
    6302:	6098      	str	r0, [r3, #8]
}
    6304:	2000      	movs	r0, #0
    p_reg->OUTCLR = clr_mask;
    6306:	60d9      	str	r1, [r3, #12]
    6308:	4770      	bx	lr

0000630a <gpio_nrfx_port_set_bits_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    630a:	6843      	ldr	r3, [r0, #4]
}
    630c:	2000      	movs	r0, #0
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    630e:	685b      	ldr	r3, [r3, #4]
    p_reg->OUTSET = set_mask;
    6310:	6099      	str	r1, [r3, #8]
}
    6312:	4770      	bx	lr

00006314 <gpio_nrfx_port_clear_bits_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    6314:	6843      	ldr	r3, [r0, #4]
}
    6316:	2000      	movs	r0, #0
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    6318:	685b      	ldr	r3, [r3, #4]
    p_reg->OUTCLR = clr_mask;
    631a:	60d9      	str	r1, [r3, #12]
}
    631c:	4770      	bx	lr

0000631e <gpio_nrfx_port_toggle_bits>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    631e:	6843      	ldr	r3, [r0, #4]
    6320:	685a      	ldr	r2, [r3, #4]
    return p_reg->OUT;
    6322:	6853      	ldr	r3, [r2, #4]
	const uint32_t set_mask = value & mask;
    6324:	ea21 0003 	bic.w	r0, r1, r3
	const uint32_t clear_mask = (~value) & mask;
    6328:	400b      	ands	r3, r1
    p_reg->OUTSET = set_mask;
    632a:	6090      	str	r0, [r2, #8]
}
    632c:	2000      	movs	r0, #0
    p_reg->OUTCLR = clr_mask;
    632e:	60d3      	str	r3, [r2, #12]
    6330:	4770      	bx	lr

00006332 <gpio_nrfx_manage_callback>:
{
    6332:	b510      	push	{r4, lr}
	return port->data;
    6334:	6903      	ldr	r3, [r0, #16]
	return list->head;
    6336:	6858      	ldr	r0, [r3, #4]
	if (!sys_slist_is_empty(callbacks)) {
    6338:	b1f8      	cbz	r0, 637a <gpio_nrfx_manage_callback+0x48>
 */
static inline bool sys_slist_find_and_remove(sys_slist_t *list,
					     sys_snode_t *node);

/** @} */
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    633a:	4288      	cmp	r0, r1
    633c:	d119      	bne.n	6372 <gpio_nrfx_manage_callback+0x40>
Z_GENLIST_REMOVE(slist, snode)
    633e:	689c      	ldr	r4, [r3, #8]
	return node->next;
    6340:	6808      	ldr	r0, [r1, #0]
Z_GENLIST_REMOVE(slist, snode)
    6342:	42a1      	cmp	r1, r4
	list->head = node;
    6344:	6058      	str	r0, [r3, #4]
Z_GENLIST_REMOVE(slist, snode)
    6346:	d100      	bne.n	634a <gpio_nrfx_manage_callback+0x18>
	list->tail = node;
    6348:	6098      	str	r0, [r3, #8]
	parent->next = child;
    634a:	2000      	movs	r0, #0
    634c:	6008      	str	r0, [r1, #0]
	if (set) {
    634e:	b12a      	cbz	r2, 635c <gpio_nrfx_manage_callback+0x2a>
	return list->head;
    6350:	685a      	ldr	r2, [r3, #4]
	parent->next = child;
    6352:	600a      	str	r2, [r1, #0]
Z_GENLIST_PREPEND(slist, snode)
    6354:	689a      	ldr	r2, [r3, #8]
	list->head = node;
    6356:	6059      	str	r1, [r3, #4]
Z_GENLIST_PREPEND(slist, snode)
    6358:	b902      	cbnz	r2, 635c <gpio_nrfx_manage_callback+0x2a>
	list->tail = node;
    635a:	6099      	str	r1, [r3, #8]
	return 0;
    635c:	2000      	movs	r0, #0
	return gpio_manage_callback(&get_port_data(port)->callbacks,
    635e:	e010      	b.n	6382 <gpio_nrfx_manage_callback+0x50>
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    6360:	4281      	cmp	r1, r0
    6362:	d106      	bne.n	6372 <gpio_nrfx_manage_callback+0x40>
	return node->next;
    6364:	6808      	ldr	r0, [r1, #0]
	parent->next = child;
    6366:	6020      	str	r0, [r4, #0]
Z_GENLIST_REMOVE(slist, snode)
    6368:	6898      	ldr	r0, [r3, #8]
    636a:	4281      	cmp	r1, r0
    636c:	d1ed      	bne.n	634a <gpio_nrfx_manage_callback+0x18>
	list->tail = node;
    636e:	609c      	str	r4, [r3, #8]
}
    6370:	e7eb      	b.n	634a <gpio_nrfx_manage_callback+0x18>
	return node->next;
    6372:	4604      	mov	r4, r0
    6374:	6800      	ldr	r0, [r0, #0]
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    6376:	2800      	cmp	r0, #0
    6378:	d1f2      	bne.n	6360 <gpio_nrfx_manage_callback+0x2e>
			if (!set) {
    637a:	2a00      	cmp	r2, #0
    637c:	d1e8      	bne.n	6350 <gpio_nrfx_manage_callback+0x1e>
				return -EINVAL;
    637e:	f06f 0015 	mvn.w	r0, #21
}
    6382:	bd10      	pop	{r4, pc}

00006384 <irq_connect4>:
#ifdef CONFIG_SPI_3_NRF_SPIM
SPI_NRFX_SPIM_DEFINE(3);
#endif

#ifdef CONFIG_SPI_4_NRF_SPIM
SPI_NRFX_SPIM_DEFINE(4);
    6384:	2200      	movs	r2, #0
    6386:	2101      	movs	r1, #1
    6388:	200a      	movs	r0, #10
    638a:	f7fb b92b 	b.w	15e4 <z_arm_irq_priority_set>

0000638e <spi_context_get_next_buf.constprop.0>:
static inline void *spi_context_get_next_buf(const struct spi_buf **current,
    638e:	b510      	push	{r4, lr}
	while (*count) {
    6390:	680b      	ldr	r3, [r1, #0]
    6392:	b913      	cbnz	r3, 639a <spi_context_get_next_buf.constprop.0+0xc>
	return NULL;
    6394:	4618      	mov	r0, r3
	*buf_len = 0;
    6396:	6013      	str	r3, [r2, #0]
	return NULL;
    6398:	e005      	b.n	63a6 <spi_context_get_next_buf.constprop.0+0x18>
		if (((*current)->len / dfs) != 0) {
    639a:	6803      	ldr	r3, [r0, #0]
    639c:	685c      	ldr	r4, [r3, #4]
    639e:	b11c      	cbz	r4, 63a8 <spi_context_get_next_buf.constprop.0+0x1a>
			*buf_len = (*current)->len / dfs;
    63a0:	6014      	str	r4, [r2, #0]
			return (*current)->buf;
    63a2:	6803      	ldr	r3, [r0, #0]
    63a4:	6818      	ldr	r0, [r3, #0]
}
    63a6:	bd10      	pop	{r4, pc}
		++(*current);
    63a8:	3308      	adds	r3, #8
    63aa:	6003      	str	r3, [r0, #0]
		--(*count);
    63ac:	680b      	ldr	r3, [r1, #0]
    63ae:	3b01      	subs	r3, #1
    63b0:	600b      	str	r3, [r1, #0]
    63b2:	e7ed      	b.n	6390 <spi_context_get_next_buf.constprop.0+0x2>

000063b4 <gpio_pin_set_dt.isra.0>:
 *
 * @param spec GPIO specification from devicetree
 * @param value Value assigned to the pin.
 * @return a value from gpio_pin_set()
 */
static inline int gpio_pin_set_dt(const struct gpio_dt_spec *spec, int value)
    63b4:	4603      	mov	r3, r0
    63b6:	460a      	mov	r2, r1
	if (data->invert & (gpio_port_pins_t)BIT(pin)) {
    63b8:	7919      	ldrb	r1, [r3, #4]
    63ba:	2301      	movs	r3, #1
{
	return gpio_pin_set(spec->port, spec->pin, value);
    63bc:	6800      	ldr	r0, [r0, #0]
	if (data->invert & (gpio_port_pins_t)BIT(pin)) {
    63be:	fa03 f101 	lsl.w	r1, r3, r1
    63c2:	6903      	ldr	r3, [r0, #16]
    63c4:	681b      	ldr	r3, [r3, #0]
    63c6:	4219      	tst	r1, r3
		value = (value != 0) ? 0 : 1;
    63c8:	bf18      	it	ne
    63ca:	f082 0201 	eorne.w	r2, r2, #1
	if (value != 0)	{
    63ce:	b112      	cbz	r2, 63d6 <gpio_pin_set_dt.isra.0+0x22>
	return api->port_set_bits_raw(port, pins);
    63d0:	6883      	ldr	r3, [r0, #8]
    63d2:	68db      	ldr	r3, [r3, #12]
	return api->port_clear_bits_raw(port, pins);
    63d4:	4718      	bx	r3
    63d6:	6883      	ldr	r3, [r0, #8]
    63d8:	691b      	ldr	r3, [r3, #16]
    63da:	e7fb      	b.n	63d4 <gpio_pin_set_dt.isra.0+0x20>

000063dc <_spi_context_cs_control>:
{
    63dc:	b538      	push	{r3, r4, r5, lr}
	if (ctx->config && ctx->config->cs && ctx->config->cs->gpio.port) {
    63de:	6803      	ldr	r3, [r0, #0]
{
    63e0:	4604      	mov	r4, r0
	if (ctx->config && ctx->config->cs && ctx->config->cs->gpio.port) {
    63e2:	b1e3      	cbz	r3, 641e <_spi_context_cs_control+0x42>
    63e4:	6898      	ldr	r0, [r3, #8]
    63e6:	b1d0      	cbz	r0, 641e <_spi_context_cs_control+0x42>
    63e8:	6805      	ldr	r5, [r0, #0]
    63ea:	b1c5      	cbz	r5, 641e <_spi_context_cs_control+0x42>
		if (on) {
    63ec:	b149      	cbz	r1, 6402 <_spi_context_cs_control+0x26>
			gpio_pin_set_dt(&ctx->config->cs->gpio, 1);
    63ee:	2101      	movs	r1, #1
    63f0:	f7ff ffe0 	bl	63b4 <gpio_pin_set_dt.isra.0>
			k_busy_wait(ctx->config->cs->delay);
    63f4:	6823      	ldr	r3, [r4, #0]
    63f6:	689b      	ldr	r3, [r3, #8]
    63f8:	6898      	ldr	r0, [r3, #8]
}
    63fa:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
	z_impl_k_busy_wait(usec_to_wait);
    63fe:	f000 bd4b 	b.w	6e98 <z_impl_k_busy_wait>
			if (!force_off &&
    6402:	b912      	cbnz	r2, 640a <_spi_context_cs_control+0x2e>
    6404:	889b      	ldrh	r3, [r3, #4]
    6406:	04db      	lsls	r3, r3, #19
    6408:	d409      	bmi.n	641e <_spi_context_cs_control+0x42>
			k_busy_wait(ctx->config->cs->delay);
    640a:	6880      	ldr	r0, [r0, #8]
    640c:	f000 fd44 	bl	6e98 <z_impl_k_busy_wait>
			gpio_pin_set_dt(&ctx->config->cs->gpio, 0);
    6410:	6823      	ldr	r3, [r4, #0]
    6412:	2100      	movs	r1, #0
    6414:	6898      	ldr	r0, [r3, #8]
}
    6416:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
			gpio_pin_set_dt(&ctx->config->cs->gpio, 0);
    641a:	f7ff bfcb 	b.w	63b4 <gpio_pin_set_dt.isra.0>
}
    641e:	bd38      	pop	{r3, r4, r5, pc}

00006420 <spi_context_unlock_unconditionally>:
{
    6420:	b510      	push	{r4, lr}
	_spi_context_cs_control(ctx, false, true);
    6422:	2201      	movs	r2, #1
    6424:	2100      	movs	r1, #0
{
    6426:	4604      	mov	r4, r0
	_spi_context_cs_control(ctx, false, true);
    6428:	f7ff ffd8 	bl	63dc <_spi_context_cs_control>
	if (!k_sem_count_get(&ctx->lock)) {
    642c:	69a3      	ldr	r3, [r4, #24]
    642e:	b933      	cbnz	r3, 643e <spi_context_unlock_unconditionally+0x1e>
		ctx->owner = NULL;
    6430:	6063      	str	r3, [r4, #4]
	z_impl_k_sem_give(sem);
    6432:	f104 0010 	add.w	r0, r4, #16
}
    6436:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    643a:	f7fe be4f 	b.w	50dc <z_impl_k_sem_give>
    643e:	bd10      	pop	{r4, pc}

00006440 <spi_nrfx_release>:
{
    6440:	b510      	push	{r4, lr}
	struct spi_nrfx_data *dev_data = dev->data;
    6442:	6900      	ldr	r0, [r0, #16]
	if (!spi_context_configured(&dev_data->ctx, spi_cfg)) {
    6444:	6803      	ldr	r3, [r0, #0]
    6446:	428b      	cmp	r3, r1
    6448:	d106      	bne.n	6458 <spi_nrfx_release+0x18>
	if (dev_data->busy) {
    644a:	f890 405c 	ldrb.w	r4, [r0, #92]	; 0x5c
    644e:	b934      	cbnz	r4, 645e <spi_nrfx_release+0x1e>
	spi_context_unlock_unconditionally(&dev_data->ctx);
    6450:	f7ff ffe6 	bl	6420 <spi_context_unlock_unconditionally>
	return 0;
    6454:	4620      	mov	r0, r4
}
    6456:	bd10      	pop	{r4, pc}
		return -EINVAL;
    6458:	f06f 0015 	mvn.w	r0, #21
    645c:	e7fb      	b.n	6456 <spi_nrfx_release+0x16>
		return -EBUSY;
    645e:	f06f 000f 	mvn.w	r0, #15
    6462:	e7f8      	b.n	6456 <spi_nrfx_release+0x16>

00006464 <spi_nrfx_init>:
{
    6464:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
	const struct spi_nrfx_config *dev_config = dev->config;
    6468:	6844      	ldr	r4, [r0, #4]
	struct spi_nrfx_data *dev_data = dev->data;
    646a:	6905      	ldr	r5, [r0, #16]
	err = pinctrl_apply_state(dev_config->pcfg, PINCTRL_STATE_DEFAULT);
    646c:	6aa6      	ldr	r6, [r4, #40]	; 0x28
	ret = pinctrl_lookup_state(config, id, &state);
    646e:	2100      	movs	r1, #0
    6470:	4630      	mov	r0, r6
    6472:	aa01      	add	r2, sp, #4
    6474:	f000 f9b2 	bl	67dc <pinctrl_lookup_state>
	if (ret < 0) {
    6478:	2800      	cmp	r0, #0
    647a:	db43      	blt.n	6504 <spi_nrfx_init+0xa0>
	return pinctrl_apply_state_direct(config, state);
    647c:	9b01      	ldr	r3, [sp, #4]
	return pinctrl_configure_pins(state->pins, state->pin_cnt, reg);
    647e:	6832      	ldr	r2, [r6, #0]
    6480:	7919      	ldrb	r1, [r3, #4]
    6482:	6818      	ldr	r0, [r3, #0]
    6484:	f7fd f834 	bl	34f0 <pinctrl_configure_pins>
	if (err < 0) {
    6488:	2800      	cmp	r0, #0
    648a:	db3b      	blt.n	6504 <spi_nrfx_init+0xa0>
		data->invert |= (gpio_port_pins_t)BIT(pin);
    648c:	2601      	movs	r6, #1
	dev_config->irq_connect();
    648e:	6a63      	ldr	r3, [r4, #36]	; 0x24
    6490:	4798      	blx	r3
	for (cs_gpio = ctx->cs_gpios; cs_gpio < &ctx->cs_gpios[ctx->num_cs_gpios]; cs_gpio++) {
    6492:	68ac      	ldr	r4, [r5, #8]
    6494:	3408      	adds	r4, #8
    6496:	e9d5 3202 	ldrd	r3, r2, [r5, #8]
    649a:	eb03 03c2 	add.w	r3, r3, r2, lsl #3
    649e:	f1a4 0208 	sub.w	r2, r4, #8
    64a2:	4293      	cmp	r3, r2
    64a4:	d804      	bhi.n	64b0 <spi_nrfx_init+0x4c>
	spi_context_unlock_unconditionally(&dev_data->ctx);
    64a6:	4628      	mov	r0, r5
    64a8:	f7ff ffba 	bl	6420 <spi_context_unlock_unconditionally>
	return 0;
    64ac:	2000      	movs	r0, #0
	return 0;
    64ae:	e029      	b.n	6504 <spi_nrfx_init+0xa0>
		if (!device_is_ready(cs_gpio->port)) {
    64b0:	f854 0c08 	ldr.w	r0, [r4, #-8]
    64b4:	f7fe fb54 	bl	4b60 <z_device_is_ready>
    64b8:	b338      	cbz	r0, 650a <spi_nrfx_init+0xa6>
	return gpio_pin_configure(spec->port,
    64ba:	f854 0c08 	ldr.w	r0, [r4, #-8]
				  spec->pin,
    64be:	f814 1c04 	ldrb.w	r1, [r4, #-4]
				  spec->dt_flags | extra_flags);
    64c2:	f834 3c02 	ldrh.w	r3, [r4, #-2]
	struct gpio_driver_data *data =
    64c6:	f8d0 c010 	ldr.w	ip, [r0, #16]
	    && ((flags & GPIO_ACTIVE_LOW) != 0)) {
    64ca:	07da      	lsls	r2, r3, #31
		data->invert |= (gpio_port_pins_t)BIT(pin);
    64cc:	f8dc 7000 	ldr.w	r7, [ip]
	return gpio_pin_configure(spec->port,
    64d0:	bf54      	ite	pl
    64d2:	f443 13b0 	orrpl.w	r3, r3, #1441792	; 0x160000
		flags ^= GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH;
    64d6:	f483 13d0 	eormi.w	r3, r3, #1703936	; 0x1a0000
	flags &= ~GPIO_OUTPUT_INIT_LOGICAL;
    64da:	f423 1280 	bic.w	r2, r3, #1048576	; 0x100000
		data->invert |= (gpio_port_pins_t)BIT(pin);
    64de:	fa06 fe01 	lsl.w	lr, r6, r1
	if ((flags & GPIO_ACTIVE_LOW) != 0) {
    64e2:	07db      	lsls	r3, r3, #31
	const struct gpio_driver_api *api =
    64e4:	f8d0 8008 	ldr.w	r8, [r0, #8]
		data->invert |= (gpio_port_pins_t)BIT(pin);
    64e8:	bf4c      	ite	mi
    64ea:	ea4e 0707 	orrmi.w	r7, lr, r7
		data->invert &= ~(gpio_port_pins_t)BIT(pin);
    64ee:	ea27 070e 	bicpl.w	r7, r7, lr
    64f2:	f8cc 7000 	str.w	r7, [ip]
	return api->pin_configure(port, pin, flags);
    64f6:	f8d8 3000 	ldr.w	r3, [r8]
    64fa:	4798      	blx	r3
		if (ret < 0) {
    64fc:	2800      	cmp	r0, #0
    64fe:	f104 0408 	add.w	r4, r4, #8
    6502:	dac8      	bge.n	6496 <spi_nrfx_init+0x32>
}
    6504:	b002      	add	sp, #8
    6506:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
			return -ENODEV;
    650a:	f06f 0012 	mvn.w	r0, #18
	if (err < 0) {
    650e:	e7f9      	b.n	6504 <spi_nrfx_init+0xa0>

00006510 <event_handler>:
{
    6510:	b538      	push	{r3, r4, r5, lr}
	if (p_event->type == NRFX_SPIM_EVENT_DONE) {
    6512:	7803      	ldrb	r3, [r0, #0]
{
    6514:	460c      	mov	r4, r1
	if (p_event->type == NRFX_SPIM_EVENT_DONE) {
    6516:	2b00      	cmp	r3, #0
    6518:	d13c      	bne.n	6594 <event_handler+0x84>
	if (!ctx->tx_len) {
    651a:	6c8b      	ldr	r3, [r1, #72]	; 0x48
		spi_context_update_tx(&dev_data->ctx, 1, dev_data->chunk_len);
    651c:	6d8d      	ldr	r5, [r1, #88]	; 0x58
    651e:	b193      	cbz	r3, 6546 <event_handler+0x36>
	if (len > ctx->tx_len) {
    6520:	429d      	cmp	r5, r3
    6522:	d810      	bhi.n	6546 <event_handler+0x36>
	ctx->tx_len -= len;
    6524:	1b5b      	subs	r3, r3, r5
    6526:	648b      	str	r3, [r1, #72]	; 0x48
	if (!ctx->tx_len) {
    6528:	bb43      	cbnz	r3, 657c <event_handler+0x6c>
		++ctx->current_tx;
    652a:	6b4b      	ldr	r3, [r1, #52]	; 0x34
			spi_context_get_next_buf(&ctx->current_tx,
    652c:	f101 0248 	add.w	r2, r1, #72	; 0x48
		++ctx->current_tx;
    6530:	3308      	adds	r3, #8
    6532:	634b      	str	r3, [r1, #52]	; 0x34
		--ctx->tx_count;
    6534:	6b8b      	ldr	r3, [r1, #56]	; 0x38
			spi_context_get_next_buf(&ctx->current_tx,
    6536:	f104 0034 	add.w	r0, r4, #52	; 0x34
		--ctx->tx_count;
    653a:	3b01      	subs	r3, #1
    653c:	638b      	str	r3, [r1, #56]	; 0x38
			spi_context_get_next_buf(&ctx->current_tx,
    653e:	3138      	adds	r1, #56	; 0x38
    6540:	f7ff ff25 	bl	638e <spi_context_get_next_buf.constprop.0>
		ctx->tx_buf = (const uint8_t *)
    6544:	6460      	str	r0, [r4, #68]	; 0x44
	if (!ctx->rx_len) {
    6546:	6d23      	ldr	r3, [r4, #80]	; 0x50
    6548:	b19b      	cbz	r3, 6572 <event_handler+0x62>
	if (len > ctx->rx_len) {
    654a:	429d      	cmp	r5, r3
    654c:	d811      	bhi.n	6572 <event_handler+0x62>
	ctx->rx_len -= len;
    654e:	1b5b      	subs	r3, r3, r5
    6550:	6523      	str	r3, [r4, #80]	; 0x50
	if (!ctx->rx_len) {
    6552:	b9cb      	cbnz	r3, 6588 <event_handler+0x78>
		++ctx->current_rx;
    6554:	6be3      	ldr	r3, [r4, #60]	; 0x3c
			spi_context_get_next_buf(&ctx->current_rx,
    6556:	f104 0250 	add.w	r2, r4, #80	; 0x50
		++ctx->current_rx;
    655a:	3308      	adds	r3, #8
    655c:	63e3      	str	r3, [r4, #60]	; 0x3c
		--ctx->rx_count;
    655e:	6c23      	ldr	r3, [r4, #64]	; 0x40
			spi_context_get_next_buf(&ctx->current_rx,
    6560:	f104 0140 	add.w	r1, r4, #64	; 0x40
		--ctx->rx_count;
    6564:	3b01      	subs	r3, #1
    6566:	6423      	str	r3, [r4, #64]	; 0x40
			spi_context_get_next_buf(&ctx->current_rx,
    6568:	f104 003c 	add.w	r0, r4, #60	; 0x3c
    656c:	f7ff ff0f 	bl	638e <spi_context_get_next_buf.constprop.0>
		ctx->rx_buf = (uint8_t *)
    6570:	64e0      	str	r0, [r4, #76]	; 0x4c
		transfer_next_chunk(dev_data->dev);
    6572:	6d60      	ldr	r0, [r4, #84]	; 0x54
}
    6574:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
		transfer_next_chunk(dev_data->dev);
    6578:	f7fb bf44 	b.w	2404 <transfer_next_chunk>
	} else if (ctx->tx_buf) {
    657c:	6c4b      	ldr	r3, [r1, #68]	; 0x44
    657e:	2b00      	cmp	r3, #0
    6580:	d0e1      	beq.n	6546 <event_handler+0x36>
		ctx->tx_buf += dfs * len;
    6582:	442b      	add	r3, r5
    6584:	644b      	str	r3, [r1, #68]	; 0x44
    6586:	e7de      	b.n	6546 <event_handler+0x36>
	} else if (ctx->rx_buf) {
    6588:	6ce3      	ldr	r3, [r4, #76]	; 0x4c
    658a:	2b00      	cmp	r3, #0
    658c:	d0f1      	beq.n	6572 <event_handler+0x62>
		ctx->rx_buf += dfs * len;
    658e:	442b      	add	r3, r5
    6590:	64e3      	str	r3, [r4, #76]	; 0x4c
    6592:	e7ee      	b.n	6572 <event_handler+0x62>
}
    6594:	bd38      	pop	{r3, r4, r5, pc}

00006596 <k_sem_give>:
    6596:	f7fe bda1 	b.w	50dc <z_impl_k_sem_give>

0000659a <qspi_handler>:
	if (event == NRFX_QSPI_EVENT_DONE) {
    659a:	b918      	cbnz	r0, 65a4 <qspi_handler+0xa>
	k_sem_give(&dev_data->sync);
    659c:	f101 0020 	add.w	r0, r1, #32
    65a0:	f7ff bff9 	b.w	6596 <k_sem_give>
}
    65a4:	4770      	bx	lr

000065a6 <qspi_lock.isra.0>:
	return z_impl_k_sem_take(sem, timeout);
    65a6:	f04f 32ff 	mov.w	r2, #4294967295
    65aa:	f04f 33ff 	mov.w	r3, #4294967295
    65ae:	3010      	adds	r0, #16
    65b0:	f7fe bdb4 	b.w	511c <z_impl_k_sem_take>

000065b4 <qspi_trans_lock.isra.0>:
    65b4:	f04f 32ff 	mov.w	r2, #4294967295
    65b8:	f04f 33ff 	mov.w	r3, #4294967295
    65bc:	f7fe bdae 	b.w	511c <z_impl_k_sem_take>

000065c0 <qspi_send_cmd>:
{
    65c0:	b573      	push	{r0, r1, r4, r5, r6, lr}
	if (cmd->tx_buf) {
    65c2:	684c      	ldr	r4, [r1, #4]
{
    65c4:	4605      	mov	r5, r0
	if (cmd->tx_buf) {
    65c6:	b36c      	cbz	r4, 6624 <qspi_send_cmd+0x64>
		tx_buf = cmd->tx_buf->buf;
    65c8:	e9d4 4300 	ldrd	r4, r3, [r4]
	if (cmd->rx_buf) {
    65cc:	6888      	ldr	r0, [r1, #8]
    65ce:	b358      	cbz	r0, 6628 <qspi_send_cmd+0x68>
		rx_len = cmd->rx_buf->len;
    65d0:	e9d0 6000 	ldrd	r6, r0, [r0]
	if ((rx_len != 0) && (tx_len != 0)) {
    65d4:	b348      	cbz	r0, 662a <qspi_send_cmd+0x6a>
    65d6:	b343      	cbz	r3, 662a <qspi_send_cmd+0x6a>
		if (rx_len != tx_len) {
    65d8:	4298      	cmp	r0, r3
    65da:	d129      	bne.n	6630 <qspi_send_cmd+0x70>
		xfer_len += tx_len;
    65dc:	3301      	adds	r3, #1
	if (xfer_len > NRF_QSPI_CINSTR_LEN_9B) {
    65de:	2b09      	cmp	r3, #9
    65e0:	d826      	bhi.n	6630 <qspi_send_cmd+0x70>
	nrf_qspi_cinstr_conf_t cinstr_cfg = {
    65e2:	f88d 3001 	strb.w	r3, [sp, #1]
    65e6:	f240 1301 	movw	r3, #257	; 0x101
    65ea:	f8ad 3002 	strh.w	r3, [sp, #2]
    65ee:	2300      	movs	r3, #0
    65f0:	7809      	ldrb	r1, [r1, #0]
	qspi_lock(dev);
    65f2:	6928      	ldr	r0, [r5, #16]
	nrf_qspi_cinstr_conf_t cinstr_cfg = {
    65f4:	f88d 3004 	strb.w	r3, [sp, #4]
    65f8:	f88d 1000 	strb.w	r1, [sp]
    65fc:	f88d 2005 	strb.w	r2, [sp, #5]
	qspi_lock(dev);
    6600:	f7ff ffd1 	bl	65a6 <qspi_lock.isra.0>
	int res = nrfx_qspi_cinstr_xfer(&cinstr_cfg, tx_buf, rx_buf);
    6604:	4621      	mov	r1, r4
    6606:	4632      	mov	r2, r6
    6608:	4668      	mov	r0, sp
    660a:	f7fd ff49 	bl	44a0 <nrfx_qspi_cinstr_xfer>
    660e:	4604      	mov	r4, r0
	k_sem_give(&dev_data->sem);
    6610:	6928      	ldr	r0, [r5, #16]
    6612:	3010      	adds	r0, #16
    6614:	f7ff ffbf 	bl	6596 <k_sem_give>
	return qspi_get_zephyr_ret_code(res);
    6618:	4620      	mov	r0, r4
}
    661a:	b002      	add	sp, #8
    661c:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	return qspi_get_zephyr_ret_code(res);
    6620:	f7fc b896 	b.w	2750 <qspi_get_zephyr_ret_code>
	size_t tx_len = 0;
    6624:	4623      	mov	r3, r4
    6626:	e7d1      	b.n	65cc <qspi_send_cmd+0xc>
	void *rx_buf = NULL;
    6628:	4606      	mov	r6, r0
		xfer_len += tx_len + rx_len;
    662a:	3301      	adds	r3, #1
    662c:	4403      	add	r3, r0
    662e:	e7d6      	b.n	65de <qspi_send_cmd+0x1e>
}
    6630:	f06f 0015 	mvn.w	r0, #21
    6634:	b002      	add	sp, #8
    6636:	bd70      	pop	{r4, r5, r6, pc}

00006638 <qspi_nor_write_protection_set>:
{
    6638:	b51f      	push	{r0, r1, r2, r3, r4, lr}
	struct qspi_cmd cmd = {
    663a:	2200      	movs	r2, #0
    663c:	4291      	cmp	r1, r2
    663e:	bf0c      	ite	eq
    6640:	2306      	moveq	r3, #6
    6642:	2304      	movne	r3, #4
	if (qspi_send_cmd(dev, &cmd, false) != 0) {
    6644:	a901      	add	r1, sp, #4
	struct qspi_cmd cmd = {
    6646:	e9cd 2201 	strd	r2, r2, [sp, #4]
    664a:	9203      	str	r2, [sp, #12]
    664c:	f88d 3004 	strb.w	r3, [sp, #4]
	if (qspi_send_cmd(dev, &cmd, false) != 0) {
    6650:	f7ff ffb6 	bl	65c0 <qspi_send_cmd>
		ret = -EIO;
    6654:	2800      	cmp	r0, #0
}
    6656:	bf18      	it	ne
    6658:	f06f 0004 	mvnne.w	r0, #4
    665c:	b005      	add	sp, #20
    665e:	f85d fb04 	ldr.w	pc, [sp], #4

00006662 <qspi_rdsr.constprop.0>:
static int qspi_rdsr(const struct device *dev, uint8_t sr_num)
    6662:	b57f      	push	{r0, r1, r2, r3, r4, r5, r6, lr}
	uint8_t sr = 0xFF;
    6664:	23ff      	movs	r3, #255	; 0xff
    6666:	f88d 3003 	strb.w	r3, [sp, #3]
	const struct qspi_buf sr_buf = {
    666a:	f10d 0303 	add.w	r3, sp, #3
	struct qspi_cmd cmd = {
    666e:	2200      	movs	r2, #0
	const struct qspi_buf sr_buf = {
    6670:	9301      	str	r3, [sp, #4]
	struct qspi_cmd cmd = {
    6672:	2301      	movs	r3, #1
    6674:	e9cd 3202 	strd	r3, r2, [sp, #8]
    6678:	2305      	movs	r3, #5
	int ret = qspi_send_cmd(dev, &cmd, false);
    667a:	a903      	add	r1, sp, #12
	struct qspi_cmd cmd = {
    667c:	f88d 300c 	strb.w	r3, [sp, #12]
    6680:	ab01      	add	r3, sp, #4
    6682:	9204      	str	r2, [sp, #16]
    6684:	9305      	str	r3, [sp, #20]
	int ret = qspi_send_cmd(dev, &cmd, false);
    6686:	f7ff ff9b 	bl	65c0 <qspi_send_cmd>
	return (ret < 0) ? ret : sr;
    668a:	2800      	cmp	r0, #0
    668c:	bfa8      	it	ge
    668e:	f89d 0003 	ldrbge.w	r0, [sp, #3]
}
    6692:	b007      	add	sp, #28
    6694:	f85d fb04 	ldr.w	pc, [sp], #4

00006698 <is_regular_addr_valid>:
{
    6698:	b538      	push	{r3, r4, r5, lr}
    669a:	4605      	mov	r5, r0
    669c:	460c      	mov	r4, r1
	return is_within_bounds(addr, len, 0, nrfx_nvmc_flash_size_get());
    669e:	f000 fa50 	bl	6b42 <nrfx_nvmc_flash_size_get>
			(addr < (boundary_start + boundary_size)) &&
    66a2:	2d00      	cmp	r5, #0
    66a4:	db07      	blt.n	66b6 <is_regular_addr_valid+0x1e>
	return (addr >= boundary_start &&
    66a6:	42a8      	cmp	r0, r5
    66a8:	d905      	bls.n	66b6 <is_regular_addr_valid+0x1e>
			(len <= (boundary_start + boundary_size - addr)));
    66aa:	1b40      	subs	r0, r0, r5
			(addr < (boundary_start + boundary_size)) &&
    66ac:	4284      	cmp	r4, r0
    66ae:	bf8c      	ite	hi
    66b0:	2000      	movhi	r0, #0
    66b2:	2001      	movls	r0, #1
}
    66b4:	bd38      	pop	{r3, r4, r5, pc}
			(addr < (boundary_start + boundary_size)) &&
    66b6:	2000      	movs	r0, #0
    66b8:	e7fc      	b.n	66b4 <is_regular_addr_valid+0x1c>

000066ba <flash_nrf_read>:
{
    66ba:	b570      	push	{r4, r5, r6, lr}
    66bc:	460d      	mov	r5, r1
	if (is_regular_addr_valid(addr, len)) {
    66be:	4619      	mov	r1, r3
    66c0:	4628      	mov	r0, r5
{
    66c2:	4616      	mov	r6, r2
    66c4:	461c      	mov	r4, r3
	if (is_regular_addr_valid(addr, len)) {
    66c6:	f7ff ffe7 	bl	6698 <is_regular_addr_valid>
    66ca:	b138      	cbz	r0, 66dc <flash_nrf_read+0x22>
	if (!len) {
    66cc:	b124      	cbz	r4, 66d8 <flash_nrf_read+0x1e>
	memcpy(data, (void *)addr, len);
    66ce:	4622      	mov	r2, r4
    66d0:	4629      	mov	r1, r5
    66d2:	4630      	mov	r0, r6
    66d4:	f7ff fd53 	bl	617e <memcpy>
		return 0;
    66d8:	2000      	movs	r0, #0
}
    66da:	bd70      	pop	{r4, r5, r6, pc}
		return -EINVAL;
    66dc:	f06f 0015 	mvn.w	r0, #21
    66e0:	e7fb      	b.n	66da <flash_nrf_read+0x20>

000066e2 <uarte_nrfx_config_get>:
{
    66e2:	460b      	mov	r3, r1
	struct uarte_nrfx_data *data = dev->data;
    66e4:	6902      	ldr	r2, [r0, #16]
	*cfg = data->uart_config;
    66e6:	e9d2 0101 	ldrd	r0, r1, [r2, #4]
    66ea:	e883 0003 	stmia.w	r3, {r0, r1}
}
    66ee:	2000      	movs	r0, #0
    66f0:	4770      	bx	lr

000066f2 <uarte_nrfx_err_check>:
	return config->uarte_regs;
    66f2:	6843      	ldr	r3, [r0, #4]
    66f4:	681b      	ldr	r3, [r3, #0]
    uint32_t errsrc_mask = p_reg->ERRORSRC;
    66f6:	f8d3 0480 	ldr.w	r0, [r3, #1152]	; 0x480
    p_reg->ERRORSRC = errsrc_mask;
    66fa:	f8c3 0480 	str.w	r0, [r3, #1152]	; 0x480
}
    66fe:	4770      	bx	lr

00006700 <uarte_nrfx_poll_in>:
	return config->uarte_regs;
    6700:	6843      	ldr	r3, [r0, #4]
	const struct uarte_nrfx_data *data = dev->data;
    6702:	6902      	ldr	r2, [r0, #16]
	return config->uarte_regs;
    6704:	681b      	ldr	r3, [r3, #0]
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    6706:	f8d3 0110 	ldr.w	r0, [r3, #272]	; 0x110
	if (!nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDRX)) {
    670a:	b150      	cbz	r0, 6722 <uarte_nrfx_poll_in+0x22>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    670c:	2000      	movs	r0, #0
	*c = *data->rx_data;
    670e:	6952      	ldr	r2, [r2, #20]
    6710:	7812      	ldrb	r2, [r2, #0]
    6712:	700a      	strb	r2, [r1, #0]
    6714:	f8c3 0110 	str.w	r0, [r3, #272]	; 0x110
    6718:	f8d3 2110 	ldr.w	r2, [r3, #272]	; 0x110
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    671c:	2201      	movs	r2, #1
    671e:	601a      	str	r2, [r3, #0]
	return 0;
    6720:	4770      	bx	lr
		return -1;
    6722:	f04f 30ff 	mov.w	r0, #4294967295
}
    6726:	4770      	bx	lr

00006728 <is_tx_ready.isra.0>:
	return config->uarte_regs;
    6728:	6802      	ldr	r2, [r0, #0]
static bool is_tx_ready(const struct device *dev)
    672a:	4603      	mov	r3, r0
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    672c:	f8d2 0158 	ldr.w	r0, [r2, #344]	; 0x158
	return nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED) ||
    6730:	b940      	cbnz	r0, 6744 <is_tx_ready.isra.0+0x1c>
	bool ppi_endtx = config->flags & UARTE_CFG_FLAG_PPI_ENDTX;
    6732:	685b      	ldr	r3, [r3, #4]
	return nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED) ||
    6734:	079b      	lsls	r3, r3, #30
    6736:	d406      	bmi.n	6746 <is_tx_ready.isra.0+0x1e>
    6738:	f8d2 0120 	ldr.w	r0, [r2, #288]	; 0x120
    673c:	3800      	subs	r0, #0
    673e:	bf18      	it	ne
    6740:	2001      	movne	r0, #1
    6742:	4770      	bx	lr
    6744:	2001      	movs	r0, #1
}
    6746:	4770      	bx	lr

00006748 <uarte_nrfx_isr_int>:
	const struct uarte_nrfx_config *config = dev->config;
    6748:	6842      	ldr	r2, [r0, #4]
	return config->uarte_regs;
    674a:	6813      	ldr	r3, [r2, #0]
    return p_reg->INTENSET & mask;
    674c:	f8d3 1304 	ldr.w	r1, [r3, #772]	; 0x304
	if (nrf_uarte_int_enable_check(uarte, NRF_UARTE_INT_ENDTX_MASK) &&
    6750:	05c9      	lsls	r1, r1, #23
    6752:	d518      	bpl.n	6786 <uarte_nrfx_isr_int+0x3e>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    6754:	f8d3 1120 	ldr.w	r1, [r3, #288]	; 0x120
    6758:	b1a9      	cbz	r1, 6786 <uarte_nrfx_isr_int+0x3e>
	__asm__ volatile(
    675a:	f04f 0020 	mov.w	r0, #32
    675e:	f3ef 8111 	mrs	r1, BASEPRI
    6762:	f380 8812 	msr	BASEPRI_MAX, r0
    6766:	f3bf 8f6f 	isb	sy
    676a:	f8d3 0120 	ldr.w	r0, [r3, #288]	; 0x120
	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDTX)) {
    676e:	b130      	cbz	r0, 677e <uarte_nrfx_isr_int+0x36>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    6770:	2000      	movs	r0, #0
    6772:	f8c3 0120 	str.w	r0, [r3, #288]	; 0x120
    6776:	f8d3 0120 	ldr.w	r0, [r3, #288]	; 0x120
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    677a:	2001      	movs	r0, #1
    677c:	60d8      	str	r0, [r3, #12]
	__asm__ volatile(
    677e:	f381 8811 	msr	BASEPRI, r1
    6782:	f3bf 8f6f 	isb	sy
	if (config->flags & UARTE_CFG_FLAG_LOW_POWER) {
    6786:	6852      	ldr	r2, [r2, #4]
    6788:	06d2      	lsls	r2, r2, #27
    678a:	d515      	bpl.n	67b8 <uarte_nrfx_isr_int+0x70>
	__asm__ volatile(
    678c:	f04f 0120 	mov.w	r1, #32
    6790:	f3ef 8211 	mrs	r2, BASEPRI
    6794:	f381 8812 	msr	BASEPRI_MAX, r1
    6798:	f3bf 8f6f 	isb	sy
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    679c:	f8d3 1158 	ldr.w	r1, [r3, #344]	; 0x158
		if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED)) {
    67a0:	b111      	cbz	r1, 67a8 <uarte_nrfx_isr_int+0x60>
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
    67a2:	2100      	movs	r1, #0
    67a4:	f8c3 1500 	str.w	r1, [r3, #1280]	; 0x500
    p_reg->INTENCLR = mask;
    67a8:	f44f 0180 	mov.w	r1, #4194304	; 0x400000
    67ac:	f8c3 1308 	str.w	r1, [r3, #776]	; 0x308
	__asm__ volatile(
    67b0:	f382 8811 	msr	BASEPRI, r2
    67b4:	f3bf 8f6f 	isb	sy
}
    67b8:	4770      	bx	lr

000067ba <sys_clock_idle_exit>:
{
}

void __weak sys_clock_idle_exit(void)
{
}
    67ba:	4770      	bx	lr

000067bc <event_clear>:
    67bc:	2200      	movs	r2, #0
	nrf_rtc_event_clear(RTC, RTC_CHANNEL_EVENT_ADDR(chan));
    67be:	f100 0350 	add.w	r3, r0, #80	; 0x50
    67c2:	009b      	lsls	r3, r3, #2
    67c4:	b29b      	uxth	r3, r3
    67c6:	f103 2350 	add.w	r3, r3, #1342197760	; 0x50005000
    67ca:	f503 3380 	add.w	r3, r3, #65536	; 0x10000
    67ce:	601a      	str	r2, [r3, #0]
    67d0:	681b      	ldr	r3, [r3, #0]
}
    67d2:	4770      	bx	lr

000067d4 <sys_clock_cycle_get_32>:
{
    67d4:	b508      	push	{r3, lr}
	return (uint32_t)z_nrf_rtc_timer_read();
    67d6:	f7fc fcfb 	bl	31d0 <z_nrf_rtc_timer_read>
}
    67da:	bd08      	pop	{r3, pc}

000067dc <pinctrl_lookup_state>:

#include <zephyr/drivers/pinctrl.h>

int pinctrl_lookup_state(const struct pinctrl_dev_config *config, uint8_t id,
			 const struct pinctrl_state **state)
{
    67dc:	b530      	push	{r4, r5, lr}
	*state = &config->states[0];
    67de:	6843      	ldr	r3, [r0, #4]
    67e0:	6013      	str	r3, [r2, #0]
	while (*state < &config->states[config->state_cnt]) {
    67e2:	7a05      	ldrb	r5, [r0, #8]
    67e4:	6844      	ldr	r4, [r0, #4]
    67e6:	eb04 04c5 	add.w	r4, r4, r5, lsl #3
    67ea:	42a3      	cmp	r3, r4
    67ec:	d302      	bcc.n	67f4 <pinctrl_lookup_state+0x18>
		}

		(*state)++;
	}

	return -ENOENT;
    67ee:	f06f 0001 	mvn.w	r0, #1
}
    67f2:	bd30      	pop	{r4, r5, pc}
		if (id == (*state)->id) {
    67f4:	795c      	ldrb	r4, [r3, #5]
    67f6:	428c      	cmp	r4, r1
    67f8:	d001      	beq.n	67fe <pinctrl_lookup_state+0x22>
		(*state)++;
    67fa:	3308      	adds	r3, #8
    67fc:	e7f0      	b.n	67e0 <pinctrl_lookup_state+0x4>
			return 0;
    67fe:	2000      	movs	r0, #0
    6800:	e7f7      	b.n	67f2 <pinctrl_lookup_state+0x16>

00006802 <k_sys_fatal_error_handler>:

	LOG_PANIC();

	if (IS_ENABLED(CONFIG_RESET_ON_FATAL_ERROR)) {
		LOG_ERR("Resetting system");
		sys_arch_reboot(0);
    6802:	2000      	movs	r0, #0
{
    6804:	b508      	push	{r3, lr}
		sys_arch_reboot(0);
    6806:	f7fb f90f 	bl	1a28 <sys_arch_reboot>

0000680a <hw_cc3xx_init_internal>:

	/* Initialize the cc3xx HW with or without RNG support */
#if CONFIG_ENTROPY_CC3XX
	res = nrf_cc3xx_platform_init();
#else
	res = nrf_cc3xx_platform_init_no_rng();
    680a:	f7ff b959 	b.w	5ac0 <nrf_cc3xx_platform_init_no_rng>

0000680e <hw_cc3xx_init>:

	return res;
}

static int hw_cc3xx_init(const struct device *dev)
{
    680e:	b508      	push	{r3, lr}
	int res;

	/* Set the RTOS abort APIs */
	nrf_cc3xx_platform_abort_init();
    6810:	f7fa fd8e 	bl	1330 <nrf_cc3xx_platform_abort_init>

	/* Set the RTOS mutex APIs */
	nrf_cc3xx_platform_mutex_init();
    6814:	f7fa fe74 	bl	1500 <nrf_cc3xx_platform_mutex_init>

	/* Enable the hardware */
	res = hw_cc3xx_init_internal(dev);
	return res;
}
    6818:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	res = nrf_cc3xx_platform_init_no_rng();
    681c:	f7ff b950 	b.w	5ac0 <nrf_cc3xx_platform_init_no_rng>

00006820 <nrfx_isr>:
#include <zephyr/kernel.h>
#include <soc/nrfx_coredep.h>

void nrfx_isr(const void *irq_handler)
{
	((nrfx_irq_handler_t)irq_handler)();
    6820:	4700      	bx	r0

00006822 <nrfx_busy_wait>:
	z_impl_k_busy_wait(usec_to_wait);
    6822:	f000 bb39 	b.w	6e98 <z_impl_k_busy_wait>

00006826 <clock_stop>:
{
    6826:	b573      	push	{r0, r1, r4, r5, r6, lr}
    switch (domain)
    6828:	2803      	cmp	r0, #3
    682a:	f200 80a7 	bhi.w	697c <clock_stop+0x156>
    682e:	e8df f000 	tbb	[pc, r0]
    6832:	1902      	.short	0x1902
    6834:	3527      	.short	0x3527
    6836:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    683a:	2202      	movs	r2, #2
    683c:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    6840:	2200      	movs	r2, #0
    6842:	f8c3 2104 	str.w	r2, [r3, #260]	; 0x104
    6846:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    684a:	2201      	movs	r2, #1
    684c:	60da      	str	r2, [r3, #12]
    nrf_clock_hfclk_t *p_clk_src = (domain == NRF_CLOCK_DOMAIN_HFCLK) ? &clk_src : NULL;
    684e:	2400      	movs	r4, #0
    nrf_clock_hfclk_t clk_src = NRF_CLOCK_HFCLK_HIGH_ACCURACY;
    6850:	2301      	movs	r3, #1
    6852:	f88d 3007 	strb.w	r3, [sp, #7]
    switch (domain)
    6856:	2803      	cmp	r0, #3
    6858:	f200 8090 	bhi.w	697c <clock_stop+0x156>
    685c:	e8df f000 	tbb	[pc, r0]
    6860:	9a78692c 	.word	0x9a78692c
    p_reg->INTENCLR = mask;
    6864:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    6868:	2201      	movs	r2, #1
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    686a:	2100      	movs	r1, #0
    p_reg->INTENCLR = mask;
    686c:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    6870:	f8c3 1100 	str.w	r1, [r3, #256]	; 0x100
    6874:	f8d3 1100 	ldr.w	r1, [r3, #256]	; 0x100
    nrf_clock_hfclk_t *p_clk_src = (domain == NRF_CLOCK_DOMAIN_HFCLK) ? &clk_src : NULL;
    6878:	f10d 0407 	add.w	r4, sp, #7
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    687c:	605a      	str	r2, [r3, #4]
    687e:	e7e7      	b.n	6850 <clock_stop+0x2a>
    p_reg->INTENCLR = mask;
    6880:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    6884:	f44f 7200 	mov.w	r2, #512	; 0x200
    6888:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    688c:	2200      	movs	r2, #0
    688e:	f8c3 2124 	str.w	r2, [r3, #292]	; 0x124
    6892:	f8d3 2124 	ldr.w	r2, [r3, #292]	; 0x124
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    6896:	2201      	movs	r2, #1
    6898:	625a      	str	r2, [r3, #36]	; 0x24
    689a:	e7d8      	b.n	684e <clock_stop+0x28>
    p_reg->INTENCLR = mask;
    689c:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    68a0:	f44f 7280 	mov.w	r2, #256	; 0x100
    68a4:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    68a8:	2200      	movs	r2, #0
    68aa:	f8c3 2120 	str.w	r2, [r3, #288]	; 0x120
    68ae:	f8d3 2120 	ldr.w	r2, [r3, #288]	; 0x120
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    68b2:	2201      	movs	r2, #1
    68b4:	61da      	str	r2, [r3, #28]
    68b6:	e7ca      	b.n	684e <clock_stop+0x28>
    switch (domain)
    68b8:	f242 7510 	movw	r5, #10000	; 0x2710
    68bc:	f04f 2650 	mov.w	r6, #1342197760	; 0x50005000
            if (p_clk_src != NULL)
    68c0:	b36c      	cbz	r4, 691e <clock_stop+0xf8>
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    68c2:	f8d6 3418 	ldr.w	r3, [r6, #1048]	; 0x418
    68c6:	f003 0303 	and.w	r3, r3, #3
                (*(nrf_clock_lfclk_t *)p_clk_src) =
    68ca:	7023      	strb	r3, [r4, #0]
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    68cc:	f8d6 3418 	ldr.w	r3, [r6, #1048]	; 0x418
    68d0:	03d9      	lsls	r1, r3, #15
    68d2:	d553      	bpl.n	697c <clock_stop+0x156>
    NRFX_WAIT_FOR((!nrfx_clock_is_running(domain, p_clk_src) ||
    68d4:	f89d 0007 	ldrb.w	r0, [sp, #7]
    68d8:	2801      	cmp	r0, #1
    68da:	d14f      	bne.n	697c <clock_stop+0x156>
    68dc:	f7ff ffa1 	bl	6822 <nrfx_busy_wait>
    68e0:	3d01      	subs	r5, #1
    68e2:	d1ed      	bne.n	68c0 <clock_stop+0x9a>
    68e4:	e04a      	b.n	697c <clock_stop+0x156>
    68e6:	f89d 0007 	ldrb.w	r0, [sp, #7]
    68ea:	2801      	cmp	r0, #1
    68ec:	d146      	bne.n	697c <clock_stop+0x156>
    68ee:	f7ff ff98 	bl	6822 <nrfx_busy_wait>
    68f2:	3d01      	subs	r5, #1
    68f4:	d152      	bne.n	699c <clock_stop+0x176>
    68f6:	e041      	b.n	697c <clock_stop+0x156>
    68f8:	f89d 0007 	ldrb.w	r0, [sp, #7]
    68fc:	2801      	cmp	r0, #1
    68fe:	d13d      	bne.n	697c <clock_stop+0x156>
    6900:	f7ff ff8f 	bl	6822 <nrfx_busy_wait>
    6904:	3d01      	subs	r5, #1
    6906:	d039      	beq.n	697c <clock_stop+0x156>
            if (p_clk_src != NULL)
    6908:	b1c4      	cbz	r4, 693c <clock_stop+0x116>
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    690a:	f8d6 340c 	ldr.w	r3, [r6, #1036]	; 0x40c
    690e:	f003 0301 	and.w	r3, r3, #1
                (*(nrf_clock_hfclk_t *)p_clk_src) =
    6912:	7023      	strb	r3, [r4, #0]
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    6914:	f8d6 340c 	ldr.w	r3, [r6, #1036]	; 0x40c
    6918:	03db      	lsls	r3, r3, #15
    691a:	d52f      	bpl.n	697c <clock_stop+0x156>
    691c:	e7ec      	b.n	68f8 <clock_stop+0xd2>
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    691e:	f8d6 3418 	ldr.w	r3, [r6, #1048]	; 0x418
    6922:	03da      	lsls	r2, r3, #15
    6924:	d52a      	bpl.n	697c <clock_stop+0x156>
    6926:	2001      	movs	r0, #1
    6928:	f7ff ff7b 	bl	6822 <nrfx_busy_wait>
    692c:	3d01      	subs	r5, #1
    692e:	d1f6      	bne.n	691e <clock_stop+0xf8>
    6930:	e024      	b.n	697c <clock_stop+0x156>
    switch (domain)
    6932:	f242 7510 	movw	r5, #10000	; 0x2710
    6936:	f04f 2650 	mov.w	r6, #1342197760	; 0x50005000
    693a:	e7e5      	b.n	6908 <clock_stop+0xe2>
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    693c:	f8d6 340c 	ldr.w	r3, [r6, #1036]	; 0x40c
    6940:	03d8      	lsls	r0, r3, #15
    6942:	d51b      	bpl.n	697c <clock_stop+0x156>
    6944:	2001      	movs	r0, #1
    6946:	f7ff ff6c 	bl	6822 <nrfx_busy_wait>
    694a:	3d01      	subs	r5, #1
    694c:	d1f6      	bne.n	693c <clock_stop+0x116>
    694e:	e015      	b.n	697c <clock_stop+0x156>
    switch (domain)
    6950:	f242 7510 	movw	r5, #10000	; 0x2710
    6954:	f04f 2650 	mov.w	r6, #1342197760	; 0x50005000
            if (p_clk_src != NULL)
    6958:	b194      	cbz	r4, 6980 <clock_stop+0x15a>
                    (nrf_clock_hfclk_t)((p_reg->HFCLK192MSTAT & CLOCK_HFCLK192MSTAT_SRC_Msk)
    695a:	f8d6 345c 	ldr.w	r3, [r6, #1116]	; 0x45c
    695e:	f003 0301 	and.w	r3, r3, #1
                (*(nrf_clock_hfclk_t *)p_clk_src) =
    6962:	7023      	strb	r3, [r4, #0]
            if ((p_reg->HFCLK192MSTAT & CLOCK_HFCLK192MSTAT_STATE_Msk)
    6964:	f8d6 345c 	ldr.w	r3, [r6, #1116]	; 0x45c
    6968:	03d9      	lsls	r1, r3, #15
    696a:	d507      	bpl.n	697c <clock_stop+0x156>
    696c:	f89d 0007 	ldrb.w	r0, [sp, #7]
    6970:	2801      	cmp	r0, #1
    6972:	d103      	bne.n	697c <clock_stop+0x156>
    6974:	f7ff ff55 	bl	6822 <nrfx_busy_wait>
    6978:	3d01      	subs	r5, #1
    697a:	d1ed      	bne.n	6958 <clock_stop+0x132>
}
    697c:	b002      	add	sp, #8
    697e:	bd70      	pop	{r4, r5, r6, pc}
    6980:	f8d6 345c 	ldr.w	r3, [r6, #1116]	; 0x45c
    6984:	03da      	lsls	r2, r3, #15
    6986:	d5f9      	bpl.n	697c <clock_stop+0x156>
    NRFX_WAIT_FOR((!nrfx_clock_is_running(domain, p_clk_src) ||
    6988:	2001      	movs	r0, #1
    698a:	f7ff ff4a 	bl	6822 <nrfx_busy_wait>
    698e:	3d01      	subs	r5, #1
    6990:	d1f6      	bne.n	6980 <clock_stop+0x15a>
    6992:	e7f3      	b.n	697c <clock_stop+0x156>
    switch (domain)
    6994:	f242 7510 	movw	r5, #10000	; 0x2710
            return (p_reg->HFCLKAUDIOSTAT & CLOCK_HFCLKAUDIOSTAT_STATE_Msk) ==
    6998:	f04f 2650 	mov.w	r6, #1342197760	; 0x50005000
    699c:	f8d6 3454 	ldr.w	r3, [r6, #1108]	; 0x454
    69a0:	03db      	lsls	r3, r3, #15
    69a2:	d5eb      	bpl.n	697c <clock_stop+0x156>
    69a4:	2c00      	cmp	r4, #0
    69a6:	d19e      	bne.n	68e6 <clock_stop+0xc0>
    69a8:	2001      	movs	r0, #1
    69aa:	e7a0      	b.n	68ee <clock_stop+0xc8>

000069ac <nrfx_clock_enable>:
{
    69ac:	b508      	push	{r3, lr}
    priority = NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY;
#else
    #error "This code is not supposed to be compiled when neither POWER nor CLOCK is enabled."
#endif

    if (!NRFX_IRQ_IS_ENABLED(nrfx_get_irq_number(NRF_CLOCK)))
    69ae:	2005      	movs	r0, #5
    69b0:	f7fa fe0a 	bl	15c8 <arch_irq_is_enabled>
    69b4:	b910      	cbnz	r0, 69bc <nrfx_clock_enable+0x10>
    {
        NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_CLOCK), priority);
        NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_CLOCK));
    69b6:	2005      	movs	r0, #5
    69b8:	f7fa fde4 	bl	1584 <arch_irq_enable>
    p_reg->LFCLKSRC = (uint32_t)(source);
    69bc:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    69c0:	2201      	movs	r2, #1
    69c2:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
    p_reg->HFCLKSRC = (uint32_t)(source);
    69c6:	f8c3 2514 	str.w	r2, [r3, #1300]	; 0x514
                                   >> CLOCK_HFCLK192MCTRL_HCLK192M_Pos);
}

NRF_STATIC_INLINE void nrf_clock_hfclk192m_src_set(NRF_CLOCK_Type * p_reg, nrf_clock_hfclk_t source)
{
    p_reg->HFCLK192MSRC = (uint32_t)(source);
    69ca:	f8c3 2580 	str.w	r2, [r3, #1408]	; 0x580
}
    69ce:	bd08      	pop	{r3, pc}

000069d0 <nrfx_clock_start>:
{
    69d0:	b508      	push	{r3, lr}
    switch (domain)
    69d2:	2803      	cmp	r0, #3
    69d4:	d819      	bhi.n	6a0a <nrfx_clock_start+0x3a>
    69d6:	e8df f000 	tbb	[pc, r0]
    69da:	3202      	.short	0x3202
    69dc:	4c3e      	.short	0x4c3e
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    69de:	f04f 2250 	mov.w	r2, #1342197760	; 0x50005000
    69e2:	f8d2 3418 	ldr.w	r3, [r2, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    69e6:	f8d2 1418 	ldr.w	r1, [r2, #1048]	; 0x418
    69ea:	03c9      	lsls	r1, r1, #15
    69ec:	d40e      	bmi.n	6a0c <nrfx_clock_start+0x3c>
            return ((p_reg->LFCLKRUN & CLOCK_LFCLKRUN_STATUS_Msk)
    69ee:	f8d2 3414 	ldr.w	r3, [r2, #1044]	; 0x414
                else if (nrf_clock_start_task_check(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK))
    69f2:	07db      	lsls	r3, r3, #31
    69f4:	d513      	bpl.n	6a1e <nrfx_clock_start+0x4e>
    return (nrf_clock_lfclk_t)((p_reg->LFCLKSRCCOPY & CLOCK_LFCLKSRCCOPY_SRC_Msk)
    69f6:	f8d2 341c 	ldr.w	r3, [r2, #1052]	; 0x41c
    69fa:	f003 0303 	and.w	r3, r3, #3
    is_correct_clk = is_correct_clk || (*p_lfclksrc == NRF_CLOCK_LFCLK_RC);
    69fe:	3b01      	subs	r3, #1
    6a00:	2b01      	cmp	r3, #1
    6a02:	d809      	bhi.n	6a18 <nrfx_clock_start+0x48>
    p_reg->INTENSET = mask;
    6a04:	2302      	movs	r3, #2
    6a06:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
}
    6a0a:	bd08      	pop	{r3, pc}
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    6a0c:	f003 0303 	and.w	r3, r3, #3
    is_correct_clk = is_correct_clk || (*p_lfclksrc == NRF_CLOCK_LFCLK_RC);
    6a10:	2b02      	cmp	r3, #2
    6a12:	d005      	beq.n	6a20 <nrfx_clock_start+0x50>
    6a14:	2b01      	cmp	r3, #1
    6a16:	d002      	beq.n	6a1e <nrfx_clock_start+0x4e>
        clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
    6a18:	2000      	movs	r0, #0
    6a1a:	f7ff ff04 	bl	6826 <clock_stop>
        *p_lfclksrc = clock_initial_lfclksrc_get();
    6a1e:	2301      	movs	r3, #1
    p_reg->LFCLKSRC = (uint32_t)(source);
    6a20:	f04f 2250 	mov.w	r2, #1342197760	; 0x50005000
    6a24:	f8c2 3518 	str.w	r3, [r2, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    6a28:	2300      	movs	r3, #0
    6a2a:	f8c2 3104 	str.w	r3, [r2, #260]	; 0x104
    6a2e:	f8d2 3104 	ldr.w	r3, [r2, #260]	; 0x104
    p_reg->INTENSET = mask;
    6a32:	2302      	movs	r3, #2
    6a34:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    6a38:	2301      	movs	r3, #1
    6a3a:	6093      	str	r3, [r2, #8]
}
    6a3c:	e7e5      	b.n	6a0a <nrfx_clock_start+0x3a>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    6a3e:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    6a42:	2200      	movs	r2, #0
    6a44:	f8c3 2100 	str.w	r2, [r3, #256]	; 0x100
    6a48:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    p_reg->INTENSET = mask;
    6a4c:	2201      	movs	r2, #1
    6a4e:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    6a52:	601a      	str	r2, [r3, #0]
}
    6a54:	e7d9      	b.n	6a0a <nrfx_clock_start+0x3a>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    6a56:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    6a5a:	2200      	movs	r2, #0
    6a5c:	f8c3 2124 	str.w	r2, [r3, #292]	; 0x124
    6a60:	f8d3 2124 	ldr.w	r2, [r3, #292]	; 0x124
    p_reg->INTENSET = mask;
    6a64:	f44f 7200 	mov.w	r2, #512	; 0x200
    6a68:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    6a6c:	2201      	movs	r2, #1
    6a6e:	621a      	str	r2, [r3, #32]
}
    6a70:	e7cb      	b.n	6a0a <nrfx_clock_start+0x3a>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    6a72:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    6a76:	2200      	movs	r2, #0
    6a78:	f8c3 2120 	str.w	r2, [r3, #288]	; 0x120
    6a7c:	f8d3 2120 	ldr.w	r2, [r3, #288]	; 0x120
    p_reg->INTENSET = mask;
    6a80:	f44f 7280 	mov.w	r2, #256	; 0x100
    6a84:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    6a88:	2201      	movs	r2, #1
    6a8a:	619a      	str	r2, [r3, #24]
}
    6a8c:	e7bd      	b.n	6a0a <nrfx_clock_start+0x3a>

00006a8e <nrfx_clock_stop>:
    clock_stop(domain);
    6a8e:	f7ff beca 	b.w	6826 <clock_stop>

00006a92 <nrf_gpio_reconfigure>:
{
    6a92:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
    6a94:	4616      	mov	r6, r2
    6a96:	e9dd 4708 	ldrd	r4, r7, [sp, #32]
    6a9a:	9001      	str	r0, [sp, #4]
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    6a9c:	a801      	add	r0, sp, #4
{
    6a9e:	461d      	mov	r5, r3
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    6aa0:	f7fc ff62 	bl	3968 <nrf_gpio_pin_port_decode>
    uint32_t cnf = reg->PIN_CNF[pin_number];
    6aa4:	9b01      	ldr	r3, [sp, #4]
                         (p_input ? GPIO_PIN_CNF_INPUT_Msk : 0) |
    6aa6:	f1b6 0c00 	subs.w	ip, r6, #0
    6aaa:	bf18      	it	ne
    6aac:	f04f 0c01 	movne.w	ip, #1
    6ab0:	eb00 0083 	add.w	r0, r0, r3, lsl #2
    uint32_t to_update = (p_dir   ? GPIO_PIN_CNF_DIR_Msk   : 0) |
    6ab4:	1e0b      	subs	r3, r1, #0
    6ab6:	bf18      	it	ne
    6ab8:	2301      	movne	r3, #1
                         (p_pull  ? GPIO_PIN_CNF_PULL_Msk  : 0) |
    6aba:	2d00      	cmp	r5, #0
    uint32_t to_update = (p_dir   ? GPIO_PIN_CNF_DIR_Msk   : 0) |
    6abc:	ea43 034c 	orr.w	r3, r3, ip, lsl #1
                         (p_pull  ? GPIO_PIN_CNF_PULL_Msk  : 0) |
    6ac0:	bf14      	ite	ne
    6ac2:	f04f 0c0c 	movne.w	ip, #12
    6ac6:	f04f 0c00 	moveq.w	ip, #0
                         (p_drive ? GPIO_PIN_CNF_DRIVE_Msk : 0) |
    6aca:	2c00      	cmp	r4, #0
                         (p_input ? GPIO_PIN_CNF_INPUT_Msk : 0) |
    6acc:	ea43 030c 	orr.w	r3, r3, ip
                         (p_drive ? GPIO_PIN_CNF_DRIVE_Msk : 0) |
    6ad0:	bf14      	ite	ne
    6ad2:	f44f 6c70 	movne.w	ip, #3840	; 0xf00
    6ad6:	f04f 0c00 	moveq.w	ip, #0
                         (p_sense ? GPIO_PIN_CNF_SENSE_Msk : 0);
    6ada:	2f00      	cmp	r7, #0
                         (p_pull  ? GPIO_PIN_CNF_PULL_Msk  : 0) |
    6adc:	ea43 030c 	orr.w	r3, r3, ip
                         (p_sense ? GPIO_PIN_CNF_SENSE_Msk : 0);
    6ae0:	bf14      	ite	ne
    6ae2:	f44f 3c40 	movne.w	ip, #196608	; 0x30000
    6ae6:	f04f 0c00 	moveq.w	ip, #0
    uint32_t cnf = reg->PIN_CNF[pin_number];
    6aea:	f8d0 2200 	ldr.w	r2, [r0, #512]	; 0x200
    uint32_t to_update = (p_dir   ? GPIO_PIN_CNF_DIR_Msk   : 0) |
    6aee:	ea43 030c 	orr.w	r3, r3, ip
    cnf &= ~to_update;
    6af2:	ea22 0303 	bic.w	r3, r2, r3
    cnf |= ((uint32_t)(p_dir   ? *p_dir   : 0) << GPIO_PIN_CNF_DIR_Pos)   |
    6af6:	b101      	cbz	r1, 6afa <nrf_gpio_reconfigure+0x68>
    6af8:	7809      	ldrb	r1, [r1, #0]
           ((uint32_t)(p_input ? *p_input : 0) << GPIO_PIN_CNF_INPUT_Pos) |
    6afa:	b10e      	cbz	r6, 6b00 <nrf_gpio_reconfigure+0x6e>
    6afc:	7836      	ldrb	r6, [r6, #0]
    6afe:	0076      	lsls	r6, r6, #1
    6b00:	4319      	orrs	r1, r3
           ((uint32_t)(p_pull  ? *p_pull  : 0) << GPIO_PIN_CNF_PULL_Pos)  |
    6b02:	b10d      	cbz	r5, 6b08 <nrf_gpio_reconfigure+0x76>
    6b04:	782d      	ldrb	r5, [r5, #0]
    6b06:	00ad      	lsls	r5, r5, #2
    6b08:	4331      	orrs	r1, r6
           ((uint32_t)(p_drive ? *p_drive : 0) << GPIO_PIN_CNF_DRIVE_Pos) |
    6b0a:	b10c      	cbz	r4, 6b10 <nrf_gpio_reconfigure+0x7e>
    6b0c:	7824      	ldrb	r4, [r4, #0]
    6b0e:	0224      	lsls	r4, r4, #8
    6b10:	4329      	orrs	r1, r5
           ((uint32_t)(p_sense ? *p_sense : 0)<< GPIO_PIN_CNF_SENSE_Pos);
    6b12:	b10f      	cbz	r7, 6b18 <nrf_gpio_reconfigure+0x86>
    6b14:	783f      	ldrb	r7, [r7, #0]
    6b16:	043f      	lsls	r7, r7, #16
    cnf |= ((uint32_t)(p_dir   ? *p_dir   : 0) << GPIO_PIN_CNF_DIR_Pos)   |
    6b18:	430c      	orrs	r4, r1
    6b1a:	433c      	orrs	r4, r7
    reg->PIN_CNF[pin_number] = cnf;
    6b1c:	f8c0 4200 	str.w	r4, [r0, #512]	; 0x200
}
    6b20:	b003      	add	sp, #12
    6b22:	bdf0      	pop	{r4, r5, r6, r7, pc}

00006b24 <nrf_gpio_cfg_sense_set>:
{
    6b24:	b51f      	push	{r0, r1, r2, r3, r4, lr}
    nrf_gpio_reconfigure(pin_number, NULL, NULL, NULL, NULL, &sense_config);
    6b26:	f10d 030f 	add.w	r3, sp, #15
    6b2a:	9301      	str	r3, [sp, #4]
    6b2c:	2300      	movs	r3, #0
{
    6b2e:	f88d 100f 	strb.w	r1, [sp, #15]
    nrf_gpio_reconfigure(pin_number, NULL, NULL, NULL, NULL, &sense_config);
    6b32:	461a      	mov	r2, r3
    6b34:	4619      	mov	r1, r3
    6b36:	9300      	str	r3, [sp, #0]
    6b38:	f7ff ffab 	bl	6a92 <nrf_gpio_reconfigure>
}
    6b3c:	b005      	add	sp, #20
    6b3e:	f85d fb04 	ldr.w	pc, [sp], #4

00006b42 <nrfx_nvmc_flash_size_get>:
}

uint32_t nrfx_nvmc_flash_size_get(void)
{
    return flash_total_size_get();
}
    6b42:	f44f 1080 	mov.w	r0, #1048576	; 0x100000
    6b46:	4770      	bx	lr

00006b48 <nrfx_nvmc_flash_page_size_get>:

uint32_t nrfx_nvmc_flash_page_size_get(void)
{
    return flash_page_size_get();
}
    6b48:	f44f 5080 	mov.w	r0, #4096	; 0x1000
    6b4c:	4770      	bx	lr

00006b4e <nrfx_nvmc_flash_page_count_get>:

uint32_t nrfx_nvmc_flash_page_count_get(void)
{
    return flash_page_count_get();
}
    6b4e:	f44f 7080 	mov.w	r0, #256	; 0x100
    6b52:	4770      	bx	lr

00006b54 <nrf_gpio_cfg_default>:
    nrf_gpio_cfg(
    6b54:	2100      	movs	r1, #0
    6b56:	f7fd bb5d 	b.w	4214 <nrf_gpio_cfg.constprop.0>

00006b5a <nrfx_qspi_write>:
    return qspi_xfer((void *)p_tx_buffer, tx_buffer_length, dst_address, NRFX_QSPI_STATE_WRITE);
    6b5a:	2302      	movs	r3, #2
    6b5c:	f7fd bab2 	b.w	40c4 <qspi_xfer>

00006b60 <nrfx_qspi_read>:
    return qspi_xfer((void *)p_rx_buffer, rx_buffer_length, src_address, NRFX_QSPI_STATE_READ);
    6b60:	2303      	movs	r3, #3
    6b62:	f7fd baaf 	b.w	40c4 <qspi_xfer>

00006b66 <nrfx_qspi_chip_erase>:
    return nrfx_qspi_erase(NRF_QSPI_ERASE_LEN_ALL, 0);
    6b66:	2100      	movs	r1, #0
    6b68:	2002      	movs	r0, #2
    6b6a:	f7fd bd49 	b.w	4600 <nrfx_qspi_erase>

00006b6e <spim_pin_uninit>:
    if (pin == NRF_SPIM_PIN_NOT_CONNECTED)
    6b6e:	1c43      	adds	r3, r0, #1
{
    6b70:	b507      	push	{r0, r1, r2, lr}
    if (pin == NRF_SPIM_PIN_NOT_CONNECTED)
    6b72:	d005      	beq.n	6b80 <spim_pin_uninit+0x12>
    6b74:	2300      	movs	r3, #0
    6b76:	2201      	movs	r2, #1
    6b78:	4619      	mov	r1, r3
    6b7a:	9300      	str	r3, [sp, #0]
    6b7c:	f7fd fdb6 	bl	46ec <nrf_gpio_cfg.constprop.0>
}
    6b80:	b003      	add	sp, #12
    6b82:	f85d fb04 	ldr.w	pc, [sp], #4

00006b86 <set_ss_pin_state>:
    if (p_cb->use_hw_ss)
    6b86:	7f83      	ldrb	r3, [r0, #30]
    6b88:	075a      	lsls	r2, r3, #29
    6b8a:	d40b      	bmi.n	6ba4 <set_ss_pin_state+0x1e>
    if (p_cb->ss_pin != NRFX_SPIM_PIN_NOT_USED)
    6b8c:	7fc0      	ldrb	r0, [r0, #31]
    6b8e:	28ff      	cmp	r0, #255	; 0xff
    6b90:	d008      	beq.n	6ba4 <set_ss_pin_state+0x1e>
        nrf_gpio_pin_write(p_cb->ss_pin,
    6b92:	079b      	lsls	r3, r3, #30
    6b94:	bf58      	it	pl
    6b96:	f081 0101 	eorpl.w	r1, r1, #1
    if (value == 0)
    6b9a:	b909      	cbnz	r1, 6ba0 <set_ss_pin_state+0x1a>
        nrf_gpio_pin_clear(pin_number);
    6b9c:	f7fd bd96 	b.w	46cc <nrf_gpio_pin_clear>
        nrf_gpio_pin_set(pin_number);
    6ba0:	f7fd bdc4 	b.w	472c <nrf_gpio_pin_set>
}
    6ba4:	4770      	bx	lr

00006ba6 <z_device_state_init>:
}
    6ba6:	4770      	bx	lr

00006ba8 <z_fatal_error>:
	return 0;
#endif
}

void z_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
{
    6ba8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    6baa:	4605      	mov	r5, r0
    6bac:	460e      	mov	r6, r1
	__asm__ volatile(
    6bae:	f04f 0320 	mov.w	r3, #32
    6bb2:	f3ef 8711 	mrs	r7, BASEPRI
    6bb6:	f383 8812 	msr	BASEPRI_MAX, r3
    6bba:	f3bf 8f6f 	isb	sy
	return z_impl_z_current_get();
    6bbe:	f7fe fdb7 	bl	5730 <z_impl_z_current_get>

#ifndef CONFIG_XTENSA
	coredump(reason, esf, thread);
#endif

	k_sys_fatal_error_handler(reason, esf);
    6bc2:	4631      	mov	r1, r6
    6bc4:	4604      	mov	r4, r0
    6bc6:	4628      	mov	r0, r5
    6bc8:	f7ff fe1b 	bl	6802 <k_sys_fatal_error_handler>
	__asm__ volatile(
    6bcc:	f387 8811 	msr	BASEPRI, r7
    6bd0:	f3bf 8f6f 	isb	sy
	z_impl_k_thread_abort(thread);
    6bd4:	4620      	mov	r0, r4
	arch_irq_unlock(key);

	if (IS_ENABLED(CONFIG_MULTITHREADING)) {
		k_thread_abort(thread);
	}
}
    6bd6:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
    6bda:	f7fa bf6f 	b.w	1abc <z_impl_k_thread_abort>

00006bde <z_early_memset>:
	(void) memset(dst, c, n);
    6bde:	f7ff bad9 	b.w	6194 <memset>

00006be2 <z_early_memcpy>:
	(void) memcpy(dst, src, n);
    6be2:	f7ff bacc 	b.w	617e <memcpy>

00006be6 <create_free_list>:
	CHECKIF(((slab->block_size | (uintptr_t)slab->buffer) &
    6be6:	e9d0 3203 	ldrd	r3, r2, [r0, #12]
    6bea:	4313      	orrs	r3, r2
    6bec:	f013 0303 	ands.w	r3, r3, #3
    6bf0:	d10c      	bne.n	6c0c <create_free_list+0x26>
	slab->free_list = NULL;
    6bf2:	6143      	str	r3, [r0, #20]
	for (j = 0U; j < slab->num_blocks; j++) {
    6bf4:	6881      	ldr	r1, [r0, #8]
    6bf6:	4299      	cmp	r1, r3
    6bf8:	d801      	bhi.n	6bfe <create_free_list+0x18>
	return 0;
    6bfa:	2000      	movs	r0, #0
    6bfc:	4770      	bx	lr
		*(char **)p = slab->free_list;
    6bfe:	6941      	ldr	r1, [r0, #20]
	for (j = 0U; j < slab->num_blocks; j++) {
    6c00:	3301      	adds	r3, #1
		*(char **)p = slab->free_list;
    6c02:	6011      	str	r1, [r2, #0]
		p += slab->block_size;
    6c04:	68c1      	ldr	r1, [r0, #12]
		slab->free_list = p;
    6c06:	6142      	str	r2, [r0, #20]
		p += slab->block_size;
    6c08:	440a      	add	r2, r1
	for (j = 0U; j < slab->num_blocks; j++) {
    6c0a:	e7f3      	b.n	6bf4 <create_free_list+0xe>
		return -EINVAL;
    6c0c:	f06f 0015 	mvn.w	r0, #21
}
    6c10:	4770      	bx	lr

00006c12 <k_mem_slab_init>:
{
    6c12:	b510      	push	{r4, lr}
	slab->block_size = block_size;
    6c14:	e9c0 3202 	strd	r3, r2, [r0, #8]
	slab->num_used = 0U;
    6c18:	2300      	movs	r3, #0
	slab->buffer = buffer;
    6c1a:	6101      	str	r1, [r0, #16]
	slab->num_used = 0U;
    6c1c:	6183      	str	r3, [r0, #24]
{
    6c1e:	4604      	mov	r4, r0
	rc = create_free_list(slab);
    6c20:	f7ff ffe1 	bl	6be6 <create_free_list>
	if (rc < 0) {
    6c24:	2800      	cmp	r0, #0
	list->tail = (sys_dnode_t *)list;
    6c26:	bfa8      	it	ge
    6c28:	e9c4 4400 	strdge	r4, r4, [r4]
}
    6c2c:	bd10      	pop	{r4, pc}

00006c2e <k_mem_slab_free>:

void k_mem_slab_free(struct k_mem_slab *slab, void **mem)
{
    6c2e:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    6c30:	4604      	mov	r4, r0
    6c32:	460d      	mov	r5, r1
	__asm__ volatile(
    6c34:	f04f 0320 	mov.w	r3, #32
    6c38:	f3ef 8611 	mrs	r6, BASEPRI
    6c3c:	f383 8812 	msr	BASEPRI_MAX, r3
    6c40:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&slab->lock);

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_mem_slab, free, slab);
	if (slab->free_list == NULL && IS_ENABLED(CONFIG_MULTITHREADING)) {
    6c44:	6947      	ldr	r7, [r0, #20]
    6c46:	b977      	cbnz	r7, 6c66 <k_mem_slab_free+0x38>
		struct k_thread *pending_thread = z_unpend_first_thread(&slab->wait_q);
    6c48:	f000 f8ae 	bl	6da8 <z_unpend_first_thread>

		if (pending_thread != NULL) {
    6c4c:	b158      	cbz	r0, 6c66 <k_mem_slab_free+0x38>
			SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mem_slab, free, slab);

			z_thread_return_value_set_with_data(pending_thread, 0, *mem);
    6c4e:	682a      	ldr	r2, [r5, #0]
    6c50:	6787      	str	r7, [r0, #120]	; 0x78
z_thread_return_value_set_with_data(struct k_thread *thread,
				   unsigned int value,
				   void *data)
{
	arch_thread_return_value_set(thread, value);
	thread->base.swap_data = data;
    6c52:	6142      	str	r2, [r0, #20]
			z_ready_thread(pending_thread);
    6c54:	f000 f898 	bl	6d88 <z_ready_thread>
			z_reschedule(&slab->lock, key);
    6c58:	4631      	mov	r1, r6
    6c5a:	f104 0008 	add.w	r0, r4, #8
	slab->num_used--;

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_mem_slab, free, slab);

	k_spin_unlock(&slab->lock, key);
}
    6c5e:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
			z_reschedule(&slab->lock, key);
    6c62:	f7fe bc2b 	b.w	54bc <z_reschedule>
	**(char ***) mem = slab->free_list;
    6c66:	682b      	ldr	r3, [r5, #0]
    6c68:	6962      	ldr	r2, [r4, #20]
    6c6a:	601a      	str	r2, [r3, #0]
	slab->free_list = *(char **) mem;
    6c6c:	682b      	ldr	r3, [r5, #0]
    6c6e:	6163      	str	r3, [r4, #20]
	slab->num_used--;
    6c70:	69a3      	ldr	r3, [r4, #24]
    6c72:	3b01      	subs	r3, #1
    6c74:	61a3      	str	r3, [r4, #24]
	__asm__ volatile(
    6c76:	f386 8811 	msr	BASEPRI, r6
    6c7a:	f3bf 8f6f 	isb	sy
}
    6c7e:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}

00006c80 <k_is_in_isr>:
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    6c80:	f3ef 8005 	mrs	r0, IPSR
}
    6c84:	3800      	subs	r0, #0
    6c86:	bf18      	it	ne
    6c88:	2001      	movne	r0, #1
    6c8a:	4770      	bx	lr

00006c8c <z_pm_save_idle_exit>:
{
    6c8c:	b508      	push	{r3, lr}
	pm_system_resume();
    6c8e:	f7fa fa4f 	bl	1130 <pm_system_resume>
}
    6c92:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	sys_clock_idle_exit();
    6c96:	f7ff bd90 	b.w	67ba <sys_clock_idle_exit>

00006c9a <adjust_owner_prio.isra.0>:
	if (mutex->owner->base.prio != new_prio) {
    6c9a:	f990 300e 	ldrsb.w	r3, [r0, #14]
    6c9e:	428b      	cmp	r3, r1
    6ca0:	d001      	beq.n	6ca6 <adjust_owner_prio.isra.0+0xc>
		return z_set_prio(mutex->owner, new_prio);
    6ca2:	f7fe bbc5 	b.w	5430 <z_set_prio>
}
    6ca6:	2000      	movs	r0, #0
    6ca8:	4770      	bx	lr

00006caa <z_impl_k_mutex_init>:
{
    6caa:	4603      	mov	r3, r0
	mutex->owner = NULL;
    6cac:	2000      	movs	r0, #0
    6cae:	e9c3 3300 	strd	r3, r3, [r3]
	mutex->lock_count = 0U;
    6cb2:	e9c3 0002 	strd	r0, r0, [r3, #8]
}
    6cb6:	4770      	bx	lr

00006cb8 <z_impl_k_sem_init>:
	CHECKIF(limit == 0U || limit > K_SEM_MAX_LIMIT || initial_count > limit) {
    6cb8:	b13a      	cbz	r2, 6cca <z_impl_k_sem_init+0x12>
    6cba:	428a      	cmp	r2, r1
    6cbc:	d305      	bcc.n	6cca <z_impl_k_sem_init+0x12>
	sem->limit = limit;
    6cbe:	e9c0 1202 	strd	r1, r2, [r0, #8]
    6cc2:	e9c0 0000 	strd	r0, r0, [r0]
	return 0;
    6cc6:	2000      	movs	r0, #0
    6cc8:	4770      	bx	lr
		return -EINVAL;
    6cca:	f06f 0015 	mvn.w	r0, #21
}
    6cce:	4770      	bx	lr

00006cd0 <sys_dlist_remove>:
	sys_dnode_t *const next = node->next;
    6cd0:	e9d0 3200 	ldrd	r3, r2, [r0]
	prev->next = next;
    6cd4:	6013      	str	r3, [r2, #0]
	next->prev = prev;
    6cd6:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    6cd8:	2300      	movs	r3, #0
	node->prev = NULL;
    6cda:	e9c0 3300 	strd	r3, r3, [r0]
	sys_dnode_init(node);
}
    6cde:	4770      	bx	lr

00006ce0 <unpend_thread_no_timeout>:
{
    6ce0:	b508      	push	{r3, lr}
	sys_dlist_remove(&thread->base.qnode_dlist);
    6ce2:	f7ff fff5 	bl	6cd0 <sys_dlist_remove>
	thread->base.thread_state &= ~_THREAD_PENDING;
    6ce6:	7b43      	ldrb	r3, [r0, #13]
    6ce8:	f023 0302 	bic.w	r3, r3, #2
    6cec:	7343      	strb	r3, [r0, #13]
	thread->base.pended_on = NULL;
    6cee:	2300      	movs	r3, #0
    6cf0:	6083      	str	r3, [r0, #8]
}
    6cf2:	bd08      	pop	{r3, pc}

00006cf4 <z_thread_timeout>:
{
    6cf4:	4601      	mov	r1, r0
    6cf6:	b510      	push	{r4, lr}
	__asm__ volatile(
    6cf8:	f04f 0320 	mov.w	r3, #32
    6cfc:	f3ef 8411 	mrs	r4, BASEPRI
    6d00:	f383 8812 	msr	BASEPRI_MAX, r3
    6d04:	f3bf 8f6f 	isb	sy
		if (!killed) {
    6d08:	f810 3c0b 	ldrb.w	r3, [r0, #-11]
    6d0c:	f013 0f28 	tst.w	r3, #40	; 0x28
    6d10:	d10d      	bne.n	6d2e <z_thread_timeout+0x3a>
			if (thread->base.pended_on != NULL) {
    6d12:	f851 3c10 	ldr.w	r3, [r1, #-16]
	struct k_thread *thread = CONTAINER_OF(timeout,
    6d16:	3818      	subs	r0, #24
			if (thread->base.pended_on != NULL) {
    6d18:	b10b      	cbz	r3, 6d1e <z_thread_timeout+0x2a>
				unpend_thread_no_timeout(thread);
    6d1a:	f7ff ffe1 	bl	6ce0 <unpend_thread_no_timeout>
	thread->base.thread_state &= ~_THREAD_SUSPENDED;
    6d1e:	f811 3c0b 	ldrb.w	r3, [r1, #-11]
    6d22:	f023 0314 	bic.w	r3, r3, #20
    6d26:	f801 3c0b 	strb.w	r3, [r1, #-11]
			ready_thread(thread);
    6d2a:	f7fe fa8b 	bl	5244 <ready_thread>
	__asm__ volatile(
    6d2e:	f384 8811 	msr	BASEPRI, r4
    6d32:	f3bf 8f6f 	isb	sy
}
    6d36:	bd10      	pop	{r4, pc}

00006d38 <add_to_waitq_locked>:
{
    6d38:	b538      	push	{r3, r4, r5, lr}
    6d3a:	4604      	mov	r4, r0
    6d3c:	460d      	mov	r5, r1
	unready_thread(thread);
    6d3e:	f7fe fab5 	bl	52ac <unready_thread>
	thread->base.thread_state |= _THREAD_PENDING;
    6d42:	7b63      	ldrb	r3, [r4, #13]
    6d44:	f043 0302 	orr.w	r3, r3, #2
    6d48:	7363      	strb	r3, [r4, #13]
	if (wait_q != NULL) {
    6d4a:	b1e5      	cbz	r5, 6d86 <add_to_waitq_locked+0x4e>
		thread->base.pended_on = wait_q;
    6d4c:	60a5      	str	r5, [r4, #8]
	return list->head == list;
    6d4e:	682b      	ldr	r3, [r5, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    6d50:	429d      	cmp	r5, r3
    6d52:	d109      	bne.n	6d68 <add_to_waitq_locked+0x30>
	sys_dnode_t *const tail = list->tail;
    6d54:	686b      	ldr	r3, [r5, #4]
	node->prev = tail;
    6d56:	e9c4 5300 	strd	r5, r3, [r4]
	tail->next = node;
    6d5a:	601c      	str	r4, [r3, #0]
	list->tail = node;
    6d5c:	606c      	str	r4, [r5, #4]
}
    6d5e:	e012      	b.n	6d86 <add_to_waitq_locked+0x4e>
	return (node == list->tail) ? NULL : node->next;
    6d60:	686a      	ldr	r2, [r5, #4]
    6d62:	4293      	cmp	r3, r2
    6d64:	d0f6      	beq.n	6d54 <add_to_waitq_locked+0x1c>
    6d66:	681b      	ldr	r3, [r3, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    6d68:	2b00      	cmp	r3, #0
    6d6a:	d0f3      	beq.n	6d54 <add_to_waitq_locked+0x1c>
	int32_t b1 = thread_1->base.prio;
    6d6c:	f994 200e 	ldrsb.w	r2, [r4, #14]
	int32_t b2 = thread_2->base.prio;
    6d70:	f993 100e 	ldrsb.w	r1, [r3, #14]
	if (b1 != b2) {
    6d74:	428a      	cmp	r2, r1
    6d76:	d0f3      	beq.n	6d60 <add_to_waitq_locked+0x28>
		if (z_sched_prio_cmp(thread, t) > 0) {
    6d78:	4291      	cmp	r1, r2
    6d7a:	ddf1      	ble.n	6d60 <add_to_waitq_locked+0x28>
	sys_dnode_t *const prev = successor->prev;
    6d7c:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
    6d7e:	e9c4 3200 	strd	r3, r2, [r4]
	prev->next = node;
    6d82:	6014      	str	r4, [r2, #0]
	successor->prev = node;
    6d84:	605c      	str	r4, [r3, #4]
}
    6d86:	bd38      	pop	{r3, r4, r5, pc}

00006d88 <z_ready_thread>:
{
    6d88:	b510      	push	{r4, lr}
	__asm__ volatile(
    6d8a:	f04f 0320 	mov.w	r3, #32
    6d8e:	f3ef 8411 	mrs	r4, BASEPRI
    6d92:	f383 8812 	msr	BASEPRI_MAX, r3
    6d96:	f3bf 8f6f 	isb	sy
			ready_thread(thread);
    6d9a:	f7fe fa53 	bl	5244 <ready_thread>
	__asm__ volatile(
    6d9e:	f384 8811 	msr	BASEPRI, r4
    6da2:	f3bf 8f6f 	isb	sy
}
    6da6:	bd10      	pop	{r4, pc}

00006da8 <z_unpend_first_thread>:
{
    6da8:	b538      	push	{r3, r4, r5, lr}
	__asm__ volatile(
    6daa:	f04f 0320 	mov.w	r3, #32
    6dae:	f3ef 8511 	mrs	r5, BASEPRI
    6db2:	f383 8812 	msr	BASEPRI_MAX, r3
    6db6:	f3bf 8f6f 	isb	sy
	return list->head == list;
    6dba:	6804      	ldr	r4, [r0, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    6dbc:	42a0      	cmp	r0, r4
    6dbe:	d00d      	beq.n	6ddc <z_unpend_first_thread+0x34>
		if (thread != NULL) {
    6dc0:	b134      	cbz	r4, 6dd0 <z_unpend_first_thread+0x28>
			unpend_thread_no_timeout(thread);
    6dc2:	4620      	mov	r0, r4
    6dc4:	f7ff ff8c 	bl	6ce0 <unpend_thread_no_timeout>
    6dc8:	f104 0018 	add.w	r0, r4, #24
    6dcc:	f000 f81e 	bl	6e0c <z_abort_timeout>
	__asm__ volatile(
    6dd0:	f385 8811 	msr	BASEPRI, r5
    6dd4:	f3bf 8f6f 	isb	sy
}
    6dd8:	4620      	mov	r0, r4
    6dda:	bd38      	pop	{r3, r4, r5, pc}
    6ddc:	2400      	movs	r4, #0
    6dde:	e7f7      	b.n	6dd0 <z_unpend_first_thread+0x28>

00006de0 <z_reschedule_irqlock>:
	return arch_irq_unlocked(key) && !arch_is_in_isr();
    6de0:	4603      	mov	r3, r0
    6de2:	b920      	cbnz	r0, 6dee <z_reschedule_irqlock+0xe>
    6de4:	f3ef 8205 	mrs	r2, IPSR
    6de8:	b90a      	cbnz	r2, 6dee <z_reschedule_irqlock+0xe>
	ret = arch_swap(key);
    6dea:	f7fa bc31 	b.w	1650 <arch_swap>
    6dee:	f383 8811 	msr	BASEPRI, r3
    6df2:	f3bf 8f6f 	isb	sy
}
    6df6:	4770      	bx	lr

00006df8 <z_reschedule_unlocked>:
	__asm__ volatile(
    6df8:	f04f 0320 	mov.w	r3, #32
    6dfc:	f3ef 8011 	mrs	r0, BASEPRI
    6e00:	f383 8812 	msr	BASEPRI_MAX, r3
    6e04:	f3bf 8f6f 	isb	sy
	(void) z_reschedule_irqlock(arch_irq_lock());
    6e08:	f7ff bfea 	b.w	6de0 <z_reschedule_irqlock>

00006e0c <z_abort_timeout>:
{
    6e0c:	b510      	push	{r4, lr}
    6e0e:	f04f 0220 	mov.w	r2, #32
    6e12:	f3ef 8411 	mrs	r4, BASEPRI
    6e16:	f382 8812 	msr	BASEPRI_MAX, r2
    6e1a:	f3bf 8f6f 	isb	sy
		if (sys_dnode_is_linked(&to->node)) {
    6e1e:	6803      	ldr	r3, [r0, #0]
    6e20:	b13b      	cbz	r3, 6e32 <z_abort_timeout+0x26>
			remove_timeout(to);
    6e22:	f7fe fd37 	bl	5894 <remove_timeout>
			ret = 0;
    6e26:	2000      	movs	r0, #0
	__asm__ volatile(
    6e28:	f384 8811 	msr	BASEPRI, r4
    6e2c:	f3bf 8f6f 	isb	sy
}
    6e30:	bd10      	pop	{r4, pc}
	int ret = -EINVAL;
    6e32:	f06f 0015 	mvn.w	r0, #21
    6e36:	e7f7      	b.n	6e28 <z_abort_timeout+0x1c>

00006e38 <z_get_next_timeout_expiry>:
{
    6e38:	b510      	push	{r4, lr}
	__asm__ volatile(
    6e3a:	f04f 0320 	mov.w	r3, #32
    6e3e:	f3ef 8411 	mrs	r4, BASEPRI
    6e42:	f383 8812 	msr	BASEPRI_MAX, r3
    6e46:	f3bf 8f6f 	isb	sy
		ret = next_timeout();
    6e4a:	f7fe fcfb 	bl	5844 <next_timeout>
	__asm__ volatile(
    6e4e:	f384 8811 	msr	BASEPRI, r4
    6e52:	f3bf 8f6f 	isb	sy
}
    6e56:	bd10      	pop	{r4, pc}

00006e58 <z_set_timeout_expiry>:
{
    6e58:	b570      	push	{r4, r5, r6, lr}
    6e5a:	4604      	mov	r4, r0
    6e5c:	460d      	mov	r5, r1
	__asm__ volatile(
    6e5e:	f04f 0320 	mov.w	r3, #32
    6e62:	f3ef 8611 	mrs	r6, BASEPRI
    6e66:	f383 8812 	msr	BASEPRI_MAX, r3
    6e6a:	f3bf 8f6f 	isb	sy
		int next_to = next_timeout();
    6e6e:	f7fe fce9 	bl	5844 <next_timeout>
			      || (ticks <= next_to);
    6e72:	2801      	cmp	r0, #1
    6e74:	dd07      	ble.n	6e86 <z_set_timeout_expiry+0x2e>
    6e76:	42a0      	cmp	r0, r4
    6e78:	db05      	blt.n	6e86 <z_set_timeout_expiry+0x2e>
			sys_clock_set_timeout(MIN(ticks, next_to), is_idle);
    6e7a:	42a0      	cmp	r0, r4
    6e7c:	4629      	mov	r1, r5
    6e7e:	bfa8      	it	ge
    6e80:	4620      	movge	r0, r4
    6e82:	f7fc faf9 	bl	3478 <sys_clock_set_timeout>
	__asm__ volatile(
    6e86:	f386 8811 	msr	BASEPRI, r6
    6e8a:	f3bf 8f6f 	isb	sy
}
    6e8e:	bd70      	pop	{r4, r5, r6, pc}

00006e90 <sys_clock_tick_get_32>:

uint32_t sys_clock_tick_get_32(void)
{
    6e90:	b508      	push	{r3, lr}
#ifdef CONFIG_TICKLESS_KERNEL
	return (uint32_t)sys_clock_tick_get();
    6e92:	f7fe fdf5 	bl	5a80 <sys_clock_tick_get>
#else
	return (uint32_t)curr_tick;
#endif
}
    6e96:	bd08      	pop	{r3, pc}

00006e98 <z_impl_k_busy_wait>:
#endif

void z_impl_k_busy_wait(uint32_t usec_to_wait)
{
	SYS_PORT_TRACING_FUNC_ENTER(k_thread, busy_wait, usec_to_wait);
	if (usec_to_wait == 0U) {
    6e98:	b108      	cbz	r0, 6e9e <z_impl_k_busy_wait+0x6>
		if ((current_cycles - start_cycles) >= cycles_to_wait) {
			break;
		}
	}
#else
	arch_busy_wait(usec_to_wait);
    6e9a:	f7fa b8f9 	b.w	1090 <arch_busy_wait>
#endif /* CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT */
	SYS_PORT_TRACING_FUNC_EXIT(k_thread, busy_wait, usec_to_wait);
}
    6e9e:	4770      	bx	lr
