
zephyr.elf:     file format elf32-littlearm


Disassembly of section rom_start:

00000000 <_vector_table>:
#include <syscalls/z_errno_mrsh.c>

#else
int *z_impl_z_errno(void)
{
	return &_current->errno_var;
   0:	b0 0c 00 20 49 23 00 00 05 58 00 00 79 23 00 00     ... I#...X..y#..
  10:	79 23 00 00 79 23 00 00 79 23 00 00 79 23 00 00     y#..y#..y#..y#..
	...
  2c:	5d 21 00 00 79 23 00 00 00 00 00 00 05 21 00 00     ]!..y#.......!..
  3c:	d3 56 00 00                                         .V..

00000040 <_irq_vector_table>:
  40:	09 23 00 00 09 23 00 00 09 23 00 00 09 23 00 00     .#...#...#...#..
  50:	09 23 00 00 09 23 00 00 09 23 00 00 09 23 00 00     .#...#...#...#..
  60:	09 23 00 00 09 23 00 00 09 23 00 00 09 23 00 00     .#...#...#...#..
  70:	09 23 00 00 09 23 00 00 09 23 00 00 09 23 00 00     .#...#...#...#..
  80:	09 23 00 00 09 23 00 00 09 23 00 00 09 23 00 00     .#...#...#...#..
  90:	09 23 00 00 09 23 00 00 09 23 00 00 09 23 00 00     .#...#...#...#..
  a0:	09 23 00 00 09 23 00 00 09 23 00 00 09 23 00 00     .#...#...#...#..
  b0:	09 23 00 00 09 23 00 00 09 23 00 00 09 23 00 00     .#...#...#...#..
  c0:	09 23 00 00 09 23 00 00 09 23 00 00 09 23 00 00     .#...#...#...#..
  d0:	09 23 00 00 09 23 00 00 09 23 00 00 09 23 00 00     .#...#...#...#..
  e0:	09 23 00 00 09 23 00 00 09 23 00 00 09 23 00 00     .#...#...#...#..
  f0:	09 23 00 00 09 23 00 00 09 23 00 00 09 23 00 00     .#...#...#...#..
 100:	09 23 00 00 09 23 00 00 09 23 00 00 09 23 00 00     .#...#...#...#..
 110:	09 23 00 00 09 23 00 00 09 23 00 00 09 23 00 00     .#...#...#...#..
 120:	09 23 00 00 09 23 00 00 09 23 00 00 09 23 00 00     .#...#...#...#..
 130:	09 23 00 00 09 23 00 00 09 23 00 00 09 23 00 00     .#...#...#...#..
 140:	09 23 00 00                                         .#..

00000144 <_vector_end>:
	...

00000200 <m_firmware_info>:
 200:	de e6 1e 28 4c bb ce 8f 02 5b 00 00 3c 00 00 00     ...(L....[..<...
 210:	00 80 00 00 01 00 00 00 00 00 00 00 00 00 00 00     ................
 220:	ff ff 02 91 00 00 00 00 00 00 00 00 00 00 00 00     ................
	...

Disassembly of section text:

0000023c <__aeabi_uldivmod>:
     23c:	b953      	cbnz	r3, 254 <__aeabi_uldivmod+0x18>
     23e:	b94a      	cbnz	r2, 254 <__aeabi_uldivmod+0x18>
     240:	2900      	cmp	r1, #0
     242:	bf08      	it	eq
     244:	2800      	cmpeq	r0, #0
     246:	bf1c      	itt	ne
     248:	f04f 31ff 	movne.w	r1, #4294967295	; 0xffffffff
     24c:	f04f 30ff 	movne.w	r0, #4294967295	; 0xffffffff
     250:	f000 b980 	b.w	554 <__aeabi_idiv0>
     254:	f1ad 0c08 	sub.w	ip, sp, #8
     258:	e96d ce04 	strd	ip, lr, [sp, #-16]!
     25c:	f000 f806 	bl	26c <__udivmoddi4>
     260:	f8dd e004 	ldr.w	lr, [sp, #4]
     264:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
     268:	b004      	add	sp, #16
     26a:	4770      	bx	lr

0000026c <__udivmoddi4>:
     26c:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     270:	9d09      	ldr	r5, [sp, #36]	; 0x24
     272:	4604      	mov	r4, r0
     274:	4688      	mov	r8, r1
     276:	2b00      	cmp	r3, #0
     278:	f040 8084 	bne.w	384 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x104>
     27c:	428a      	cmp	r2, r1
     27e:	4617      	mov	r7, r2
     280:	d943      	bls.n	30a <CONFIG_PM_PARTITION_SIZE_PROVISION+0x8a>
     282:	fab2 f282 	clz	r2, r2
     286:	b142      	cbz	r2, 29a <CONFIG_PM_PARTITION_SIZE_PROVISION+0x1a>
     288:	f1c2 0020 	rsb	r0, r2, #32
     28c:	4091      	lsls	r1, r2
     28e:	4097      	lsls	r7, r2
     290:	fa24 f000 	lsr.w	r0, r4, r0
     294:	4094      	lsls	r4, r2
     296:	ea40 0801 	orr.w	r8, r0, r1
     29a:	ea4f 4c17 	mov.w	ip, r7, lsr #16
     29e:	0c23      	lsrs	r3, r4, #16
     2a0:	fa1f fe87 	uxth.w	lr, r7
     2a4:	fbb8 f6fc 	udiv	r6, r8, ip
     2a8:	fb0c 8116 	mls	r1, ip, r6, r8
     2ac:	fb06 f00e 	mul.w	r0, r6, lr
     2b0:	ea43 4301 	orr.w	r3, r3, r1, lsl #16
     2b4:	4298      	cmp	r0, r3
     2b6:	d907      	bls.n	2c8 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x48>
     2b8:	18fb      	adds	r3, r7, r3
     2ba:	f106 31ff 	add.w	r1, r6, #4294967295	; 0xffffffff
     2be:	d202      	bcs.n	2c6 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x46>
     2c0:	4298      	cmp	r0, r3
     2c2:	f200 8131 	bhi.w	528 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x40>
     2c6:	460e      	mov	r6, r1
     2c8:	1a19      	subs	r1, r3, r0
     2ca:	b2a3      	uxth	r3, r4
     2cc:	fbb1 f0fc 	udiv	r0, r1, ip
     2d0:	fb0c 1110 	mls	r1, ip, r0, r1
     2d4:	fb00 fe0e 	mul.w	lr, r0, lr
     2d8:	ea43 4401 	orr.w	r4, r3, r1, lsl #16
     2dc:	45a6      	cmp	lr, r4
     2de:	d907      	bls.n	2f0 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x70>
     2e0:	193c      	adds	r4, r7, r4
     2e2:	f100 33ff 	add.w	r3, r0, #4294967295	; 0xffffffff
     2e6:	d202      	bcs.n	2ee <CONFIG_PM_PARTITION_SIZE_PROVISION+0x6e>
     2e8:	45a6      	cmp	lr, r4
     2ea:	f200 811a 	bhi.w	522 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x3a>
     2ee:	4618      	mov	r0, r3
     2f0:	ea40 4006 	orr.w	r0, r0, r6, lsl #16
     2f4:	eba4 040e 	sub.w	r4, r4, lr
     2f8:	2600      	movs	r6, #0
     2fa:	b11d      	cbz	r5, 304 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x84>
     2fc:	40d4      	lsrs	r4, r2
     2fe:	2300      	movs	r3, #0
     300:	e9c5 4300 	strd	r4, r3, [r5]
     304:	4631      	mov	r1, r6
     306:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
     30a:	b902      	cbnz	r2, 30e <CONFIG_PM_PARTITION_SIZE_PROVISION+0x8e>
     30c:	deff      	udf	#255	; 0xff
     30e:	fab2 f282 	clz	r2, r2
     312:	2a00      	cmp	r2, #0
     314:	d152      	bne.n	3bc <CONFIG_PM_PARTITION_SIZE_PROVISION+0x13c>
     316:	1bcb      	subs	r3, r1, r7
     318:	ea4f 4e17 	mov.w	lr, r7, lsr #16
     31c:	fa1f f887 	uxth.w	r8, r7
     320:	2601      	movs	r6, #1
     322:	0c21      	lsrs	r1, r4, #16
     324:	fbb3 fcfe 	udiv	ip, r3, lr
     328:	fb0e 301c 	mls	r0, lr, ip, r3
     32c:	fb08 f90c 	mul.w	r9, r8, ip
     330:	ea41 4100 	orr.w	r1, r1, r0, lsl #16
     334:	4589      	cmp	r9, r1
     336:	d90b      	bls.n	350 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xd0>
     338:	1879      	adds	r1, r7, r1
     33a:	f10c 33ff 	add.w	r3, ip, #4294967295	; 0xffffffff
     33e:	bf2c      	ite	cs
     340:	2001      	movcs	r0, #1
     342:	2000      	movcc	r0, #0
     344:	4589      	cmp	r9, r1
     346:	d902      	bls.n	34e <CONFIG_PM_PARTITION_SIZE_PROVISION+0xce>
     348:	2800      	cmp	r0, #0
     34a:	f000 80f0 	beq.w	52e <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x46>
     34e:	469c      	mov	ip, r3
     350:	eba1 0109 	sub.w	r1, r1, r9
     354:	b2a3      	uxth	r3, r4
     356:	fbb1 f0fe 	udiv	r0, r1, lr
     35a:	fb0e 1110 	mls	r1, lr, r0, r1
     35e:	fb08 f800 	mul.w	r8, r8, r0
     362:	ea43 4401 	orr.w	r4, r3, r1, lsl #16
     366:	45a0      	cmp	r8, r4
     368:	d907      	bls.n	37a <CONFIG_PM_PARTITION_SIZE_PROVISION+0xfa>
     36a:	193c      	adds	r4, r7, r4
     36c:	f100 33ff 	add.w	r3, r0, #4294967295	; 0xffffffff
     370:	d202      	bcs.n	378 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xf8>
     372:	45a0      	cmp	r8, r4
     374:	f200 80d2 	bhi.w	51c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x34>
     378:	4618      	mov	r0, r3
     37a:	eba4 0408 	sub.w	r4, r4, r8
     37e:	ea40 400c 	orr.w	r0, r0, ip, lsl #16
     382:	e7ba      	b.n	2fa <CONFIG_PM_PARTITION_SIZE_PROVISION+0x7a>
     384:	428b      	cmp	r3, r1
     386:	d909      	bls.n	39c <CONFIG_PM_PARTITION_SIZE_PROVISION+0x11c>
     388:	2d00      	cmp	r5, #0
     38a:	f000 80be 	beq.w	50a <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x22>
     38e:	2600      	movs	r6, #0
     390:	e9c5 0100 	strd	r0, r1, [r5]
     394:	4630      	mov	r0, r6
     396:	4631      	mov	r1, r6
     398:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
     39c:	fab3 f683 	clz	r6, r3
     3a0:	2e00      	cmp	r6, #0
     3a2:	d14d      	bne.n	440 <CONFIG_FLASH_SIZE+0x40>
     3a4:	428b      	cmp	r3, r1
     3a6:	f0c0 80b3 	bcc.w	510 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x28>
     3aa:	4282      	cmp	r2, r0
     3ac:	f240 80b0 	bls.w	510 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x28>
     3b0:	4630      	mov	r0, r6
     3b2:	2d00      	cmp	r5, #0
     3b4:	d0a6      	beq.n	304 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x84>
     3b6:	e9c5 4800 	strd	r4, r8, [r5]
     3ba:	e7a3      	b.n	304 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x84>
     3bc:	4097      	lsls	r7, r2
     3be:	f1c2 0320 	rsb	r3, r2, #32
     3c2:	fa01 f002 	lsl.w	r0, r1, r2
     3c6:	ea4f 4e17 	mov.w	lr, r7, lsr #16
     3ca:	40d9      	lsrs	r1, r3
     3cc:	fa24 f303 	lsr.w	r3, r4, r3
     3d0:	fa1f f887 	uxth.w	r8, r7
     3d4:	4094      	lsls	r4, r2
     3d6:	4303      	orrs	r3, r0
     3d8:	fbb1 f0fe 	udiv	r0, r1, lr
     3dc:	0c1e      	lsrs	r6, r3, #16
     3de:	fb0e 1110 	mls	r1, lr, r0, r1
     3e2:	fb00 fc08 	mul.w	ip, r0, r8
     3e6:	ea46 4101 	orr.w	r1, r6, r1, lsl #16
     3ea:	458c      	cmp	ip, r1
     3ec:	d90e      	bls.n	40c <CONFIG_FLASH_SIZE+0xc>
     3ee:	1879      	adds	r1, r7, r1
     3f0:	f100 36ff 	add.w	r6, r0, #4294967295	; 0xffffffff
     3f4:	bf2c      	ite	cs
     3f6:	f04f 0901 	movcs.w	r9, #1
     3fa:	f04f 0900 	movcc.w	r9, #0
     3fe:	458c      	cmp	ip, r1
     400:	d903      	bls.n	40a <CONFIG_FLASH_SIZE+0xa>
     402:	f1b9 0f00 	cmp.w	r9, #0
     406:	f000 8096 	beq.w	536 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x4e>
     40a:	4630      	mov	r0, r6
     40c:	eba1 010c 	sub.w	r1, r1, ip
     410:	b29b      	uxth	r3, r3
     412:	fbb1 f6fe 	udiv	r6, r1, lr
     416:	fb0e 1116 	mls	r1, lr, r6, r1
     41a:	fb06 fc08 	mul.w	ip, r6, r8
     41e:	ea43 4101 	orr.w	r1, r3, r1, lsl #16
     422:	458c      	cmp	ip, r1
     424:	d907      	bls.n	436 <CONFIG_FLASH_SIZE+0x36>
     426:	1879      	adds	r1, r7, r1
     428:	f106 33ff 	add.w	r3, r6, #4294967295	; 0xffffffff
     42c:	d202      	bcs.n	434 <CONFIG_FLASH_SIZE+0x34>
     42e:	458c      	cmp	ip, r1
     430:	f200 8088 	bhi.w	544 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x5c>
     434:	461e      	mov	r6, r3
     436:	eba1 030c 	sub.w	r3, r1, ip
     43a:	ea46 4600 	orr.w	r6, r6, r0, lsl #16
     43e:	e770      	b.n	322 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xa2>
     440:	f1c6 0720 	rsb	r7, r6, #32
     444:	fa03 f406 	lsl.w	r4, r3, r6
     448:	fa02 fc06 	lsl.w	ip, r2, r6
     44c:	fa01 fe06 	lsl.w	lr, r1, r6
     450:	40fa      	lsrs	r2, r7
     452:	fa20 f807 	lsr.w	r8, r0, r7
     456:	40f9      	lsrs	r1, r7
     458:	fa00 f306 	lsl.w	r3, r0, r6
     45c:	4322      	orrs	r2, r4
     45e:	ea48 040e 	orr.w	r4, r8, lr
     462:	ea4f 4812 	mov.w	r8, r2, lsr #16
     466:	ea4f 4e14 	mov.w	lr, r4, lsr #16
     46a:	fa1f f982 	uxth.w	r9, r2
     46e:	fbb1 faf8 	udiv	sl, r1, r8
     472:	fb08 111a 	mls	r1, r8, sl, r1
     476:	fb0a f009 	mul.w	r0, sl, r9
     47a:	ea4e 4e01 	orr.w	lr, lr, r1, lsl #16
     47e:	4570      	cmp	r0, lr
     480:	d90e      	bls.n	4a0 <CONFIG_FLASH_SIZE+0xa0>
     482:	eb12 0e0e 	adds.w	lr, r2, lr
     486:	f10a 31ff 	add.w	r1, sl, #4294967295	; 0xffffffff
     48a:	bf2c      	ite	cs
     48c:	f04f 0b01 	movcs.w	fp, #1
     490:	f04f 0b00 	movcc.w	fp, #0
     494:	4570      	cmp	r0, lr
     496:	d902      	bls.n	49e <CONFIG_FLASH_SIZE+0x9e>
     498:	f1bb 0f00 	cmp.w	fp, #0
     49c:	d04e      	beq.n	53c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x54>
     49e:	468a      	mov	sl, r1
     4a0:	ebae 0e00 	sub.w	lr, lr, r0
     4a4:	b2a4      	uxth	r4, r4
     4a6:	fbbe f0f8 	udiv	r0, lr, r8
     4aa:	fb08 ee10 	mls	lr, r8, r0, lr
     4ae:	fb00 f909 	mul.w	r9, r0, r9
     4b2:	ea44 4e0e 	orr.w	lr, r4, lr, lsl #16
     4b6:	45f1      	cmp	r9, lr
     4b8:	d907      	bls.n	4ca <CONFIG_FLASH_SIZE+0xca>
     4ba:	eb12 0e0e 	adds.w	lr, r2, lr
     4be:	f100 31ff 	add.w	r1, r0, #4294967295	; 0xffffffff
     4c2:	d201      	bcs.n	4c8 <CONFIG_FLASH_SIZE+0xc8>
     4c4:	45f1      	cmp	r9, lr
     4c6:	d840      	bhi.n	54a <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x62>
     4c8:	4608      	mov	r0, r1
     4ca:	ea40 400a 	orr.w	r0, r0, sl, lsl #16
     4ce:	ebae 0e09 	sub.w	lr, lr, r9
     4d2:	fba0 890c 	umull	r8, r9, r0, ip
     4d6:	45ce      	cmp	lr, r9
     4d8:	4641      	mov	r1, r8
     4da:	464c      	mov	r4, r9
     4dc:	d302      	bcc.n	4e4 <CONFIG_FLASH_SIZE+0xe4>
     4de:	d106      	bne.n	4ee <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x6>
     4e0:	4543      	cmp	r3, r8
     4e2:	d204      	bcs.n	4ee <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x6>
     4e4:	3801      	subs	r0, #1
     4e6:	ebb8 010c 	subs.w	r1, r8, ip
     4ea:	eb69 0402 	sbc.w	r4, r9, r2
     4ee:	b37d      	cbz	r5, 550 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x68>
     4f0:	1a5a      	subs	r2, r3, r1
     4f2:	eb6e 0e04 	sbc.w	lr, lr, r4
     4f6:	40f2      	lsrs	r2, r6
     4f8:	fa0e f707 	lsl.w	r7, lr, r7
     4fc:	fa2e f306 	lsr.w	r3, lr, r6
     500:	2600      	movs	r6, #0
     502:	4317      	orrs	r7, r2
     504:	e9c5 7300 	strd	r7, r3, [r5]
     508:	e6fc      	b.n	304 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x84>
     50a:	462e      	mov	r6, r5
     50c:	4628      	mov	r0, r5
     50e:	e6f9      	b.n	304 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x84>
     510:	1a84      	subs	r4, r0, r2
     512:	eb61 0103 	sbc.w	r1, r1, r3
     516:	2001      	movs	r0, #1
     518:	4688      	mov	r8, r1
     51a:	e74a      	b.n	3b2 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x132>
     51c:	3802      	subs	r0, #2
     51e:	443c      	add	r4, r7
     520:	e72b      	b.n	37a <CONFIG_PM_PARTITION_SIZE_PROVISION+0xfa>
     522:	3802      	subs	r0, #2
     524:	443c      	add	r4, r7
     526:	e6e3      	b.n	2f0 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x70>
     528:	3e02      	subs	r6, #2
     52a:	443b      	add	r3, r7
     52c:	e6cc      	b.n	2c8 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x48>
     52e:	f1ac 0c02 	sub.w	ip, ip, #2
     532:	4439      	add	r1, r7
     534:	e70c      	b.n	350 <CONFIG_PM_PARTITION_SIZE_PROVISION+0xd0>
     536:	3802      	subs	r0, #2
     538:	4439      	add	r1, r7
     53a:	e767      	b.n	40c <CONFIG_FLASH_SIZE+0xc>
     53c:	f1aa 0a02 	sub.w	sl, sl, #2
     540:	4496      	add	lr, r2
     542:	e7ad      	b.n	4a0 <CONFIG_FLASH_SIZE+0xa0>
     544:	3e02      	subs	r6, #2
     546:	4439      	add	r1, r7
     548:	e775      	b.n	436 <CONFIG_FLASH_SIZE+0x36>
     54a:	3802      	subs	r0, #2
     54c:	4496      	add	lr, r2
     54e:	e7bc      	b.n	4ca <CONFIG_FLASH_SIZE+0xca>
     550:	462e      	mov	r6, r5
     552:	e6d7      	b.n	304 <CONFIG_PM_PARTITION_SIZE_PROVISION+0x84>

00000554 <__aeabi_idiv0>:
     554:	4770      	bx	lr
     556:	bf00      	nop

00000558 <__gnu_cmse_nonsecure_call>:
     558:	e92d 4fe0 	stmdb	sp!, {r5, r6, r7, r8, r9, sl, fp, lr}
     55c:	4627      	mov	r7, r4
     55e:	46a0      	mov	r8, r4
     560:	46a1      	mov	r9, r4
     562:	46a2      	mov	sl, r4
     564:	46a3      	mov	fp, r4
     566:	46a4      	mov	ip, r4
     568:	ed2d 8b10 	vpush	{d8-d15}
     56c:	f04f 0500 	mov.w	r5, #0
     570:	ec45 5b18 	vmov	d8, r5, r5
     574:	ec45 5a19 	vmov	s18, s19, r5, r5
     578:	ec45 5a1a 	vmov	s20, s21, r5, r5
     57c:	ec45 5a1b 	vmov	s22, s23, r5, r5
     580:	ec45 5a1c 	vmov	s24, s25, r5, r5
     584:	ec45 5a1d 	vmov	s26, s27, r5, r5
     588:	ec45 5a1e 	vmov	s28, s29, r5, r5
     58c:	ec45 5a1f 	vmov	s30, s31, r5, r5
     590:	eef1 5a10 	vmrs	r5, fpscr
     594:	f64f 7660 	movw	r6, #65376	; 0xff60
     598:	f6c0 76ff 	movt	r6, #4095	; 0xfff
     59c:	4035      	ands	r5, r6
     59e:	eee1 5a10 	vmsr	fpscr, r5
     5a2:	f384 8800 	msr	CPSR_f, r4
     5a6:	4625      	mov	r5, r4
     5a8:	4626      	mov	r6, r4
     5aa:	47a4      	blxns	r4
     5ac:	ecbd 8b10 	vpop	{d8-d15}
     5b0:	e8bd 8fe0 	ldmia.w	sp!, {r5, r6, r7, r8, r9, sl, fp, pc}

000005b4 <char_out>:

static int char_out(int c, void *ctx_p)
{
	struct out_context *ctx = ctx_p;

	ctx->count++;
     5b4:	680b      	ldr	r3, [r1, #0]
     5b6:	3301      	adds	r3, #1
     5b8:	600b      	str	r3, [r1, #0]
	return _char_out(c);
     5ba:	4b01      	ldr	r3, [pc, #4]	; (5c0 <char_out+0xc>)
     5bc:	681b      	ldr	r3, [r3, #0]
     5be:	4718      	bx	r3
     5c0:	20000000 	.word	0x20000000

000005c4 <vprintk>:
#endif
	}
}
#else
void vprintk(const char *fmt, va_list ap)
{
     5c4:	b507      	push	{r0, r1, r2, lr}
     5c6:	460b      	mov	r3, r1
	struct out_context ctx = { 0 };
     5c8:	2100      	movs	r1, #0
{
     5ca:	4602      	mov	r2, r0
	struct out_context ctx = { 0 };
     5cc:	9101      	str	r1, [sp, #4]
#ifdef CONFIG_PRINTK_SYNC
	k_spinlock_key_t key = k_spin_lock(&lock);
#endif

	cbvprintf(char_out, &ctx, fmt, ap);
     5ce:	4803      	ldr	r0, [pc, #12]	; (5dc <vprintk+0x18>)
     5d0:	a901      	add	r1, sp, #4
     5d2:	f000 f8e9 	bl	7a8 <cbvprintf>

#ifdef CONFIG_PRINTK_SYNC
	k_spin_unlock(&lock, key);
#endif
}
     5d6:	b003      	add	sp, #12
     5d8:	f85d fb04 	ldr.w	pc, [sp], #4
     5dc:	000005b5 	.word	0x000005b5

000005e0 <process_event>:
 * regions.
 */
static void process_event(struct onoff_manager *mgr,
			  int evt,
			  k_spinlock_key_t key)
{
     5e0:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
	sys_slist_t clients;
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     5e4:	f8b0 9018 	ldrh.w	r9, [r0, #24]
{
     5e8:	4604      	mov	r4, r0
	__ASSERT_NO_MSG(evt != EVT_NOP);

	/* If this is a nested call record the event for processing in
	 * the top invocation.
	 */
	if (processing) {
     5ea:	f019 0808 	ands.w	r8, r9, #8
{
     5ee:	4693      	mov	fp, r2
	if (processing) {
     5f0:	d00e      	beq.n	610 <process_event+0x30>
		if (evt == EVT_COMPLETE) {
     5f2:	2901      	cmp	r1, #1
			mgr->flags |= ONOFF_FLAG_COMPLETE;
     5f4:	bf0c      	ite	eq
     5f6:	f049 0910 	orreq.w	r9, r9, #16
		} else {
			__ASSERT_NO_MSG(evt == EVT_RECHECK);

			mgr->flags |= ONOFF_FLAG_RECHECK;
     5fa:	f049 0920 	orrne.w	r9, r9, #32
     5fe:	f8a0 9018 	strh.w	r9, [r0, #24]
	__asm__ volatile(
		"cpsie i;"
		"isb"
		: : : "memory");
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	__asm__ volatile(
     602:	f38b 8811 	msr	BASEPRI, fp
     606:	f3bf 8f6f 	isb	sy
		state = mgr->flags & ONOFF_STATE_MASK;
	} while (evt != EVT_NOP);

out:
	k_spin_unlock(&mgr->lock, key);
}
     60a:	b003      	add	sp, #12
     60c:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
				transit(mgr, transition_complete);
     610:	f8df a190 	ldr.w	sl, [pc, #400]	; 7a4 <process_event+0x1c4>
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     614:	f009 0907 	and.w	r9, r9, #7
		if (evt == EVT_RECHECK) {
     618:	2902      	cmp	r1, #2
     61a:	d107      	bne.n	62c <process_event+0x4c>
			evt = process_recheck(mgr);
     61c:	4620      	mov	r0, r4
     61e:	f004 fd94 	bl	514a <process_recheck>
		if (evt == EVT_NOP) {
     622:	2800      	cmp	r0, #0
     624:	d0ed      	beq.n	602 <process_event+0x22>
		if (evt == EVT_COMPLETE) {
     626:	2801      	cmp	r0, #1
     628:	8b23      	ldrh	r3, [r4, #24]
     62a:	d14b      	bne.n	6c4 <process_event+0xe4>
			res = mgr->last_res;
     62c:	6967      	ldr	r7, [r4, #20]
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     62e:	8b21      	ldrh	r1, [r4, #24]
	if (res < 0) {
     630:	2f00      	cmp	r7, #0
     632:	da15      	bge.n	660 <process_event+0x80>
		*clients = mgr->clients;
     634:	6825      	ldr	r5, [r4, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     636:	f021 0107 	bic.w	r1, r1, #7
 * @param list A pointer on the list to initialize
 */
static inline void sys_slist_init(sys_slist_t *list)
{
	list->head = NULL;
	list->tail = NULL;
     63a:	e9c4 8800 	strd	r8, r8, [r4]
     63e:	f041 0101 	orr.w	r1, r1, #1
	mgr->flags = (state & ONOFF_STATE_MASK)
     642:	8321      	strh	r1, [r4, #24]
		onoff_transition_fn transit = NULL;
     644:	2600      	movs	r6, #0
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
     646:	8b21      	ldrh	r1, [r4, #24]
     648:	f001 0207 	and.w	r2, r1, #7
				   && !sys_slist_is_empty(&mgr->monitors);
     64c:	454a      	cmp	r2, r9
     64e:	d002      	beq.n	656 <process_event+0x76>
		if (do_monitors
     650:	68a3      	ldr	r3, [r4, #8]
     652:	2b00      	cmp	r3, #0
     654:	d157      	bne.n	706 <process_event+0x126>
		    || !sys_slist_is_empty(&clients)
     656:	b90d      	cbnz	r5, 65c <process_event+0x7c>
		    || (transit != NULL)) {
     658:	2e00      	cmp	r6, #0
     65a:	d06f      	beq.n	73c <process_event+0x15c>
     65c:	2300      	movs	r3, #0
     65e:	e053      	b.n	708 <process_event+0x128>
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
     660:	f001 0307 	and.w	r3, r1, #7
		   || (state == ONOFF_STATE_RESETTING)) {
     664:	1f5a      	subs	r2, r3, #5
	} else if ((state == ONOFF_STATE_TO_ON)
     666:	2a01      	cmp	r2, #1
     668:	d81d      	bhi.n	6a6 <process_event+0xc6>
		*clients = mgr->clients;
     66a:	f021 0107 	bic.w	r1, r1, #7
		if (state == ONOFF_STATE_TO_ON) {
     66e:	2b06      	cmp	r3, #6
		*clients = mgr->clients;
     670:	6825      	ldr	r5, [r4, #0]
	list->head = NULL;
     672:	b289      	uxth	r1, r1
	list->tail = NULL;
     674:	e9c4 8800 	strd	r8, r8, [r4]
		if (state == ONOFF_STATE_TO_ON) {
     678:	d10a      	bne.n	690 <process_event+0xb0>
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
     67a:	b13d      	cbz	r5, 68c <process_event+0xac>
     67c:	462a      	mov	r2, r5
     67e:	8b63      	ldrh	r3, [r4, #26]
 *
 * @return a pointer on the next node (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_next_no_check(sys_snode_t *node);

Z_GENLIST_PEEK_NEXT_NO_CHECK(slist, snode)
     680:	6812      	ldr	r2, [r2, #0]
				mgr->refs += 1U;
     682:	3301      	adds	r3, #1
     684:	b29b      	uxth	r3, r3
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
     686:	2a00      	cmp	r2, #0
     688:	d1fa      	bne.n	680 <process_event+0xa0>
     68a:	8363      	strh	r3, [r4, #26]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     68c:	f041 0102 	orr.w	r1, r1, #2
		if (process_recheck(mgr) != EVT_NOP) {
     690:	4620      	mov	r0, r4
	mgr->flags = (state & ONOFF_STATE_MASK)
     692:	8321      	strh	r1, [r4, #24]
		if (process_recheck(mgr) != EVT_NOP) {
     694:	f004 fd59 	bl	514a <process_recheck>
     698:	2800      	cmp	r0, #0
     69a:	d0d3      	beq.n	644 <process_event+0x64>
			mgr->flags |= ONOFF_FLAG_RECHECK;
     69c:	8b23      	ldrh	r3, [r4, #24]
     69e:	f043 0320 	orr.w	r3, r3, #32
     6a2:	8323      	strh	r3, [r4, #24]
     6a4:	e7ce      	b.n	644 <process_event+0x64>
	} else if (state == ONOFF_STATE_TO_OFF) {
     6a6:	2b04      	cmp	r3, #4
     6a8:	d10a      	bne.n	6c0 <process_event+0xe0>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     6aa:	f021 0107 	bic.w	r1, r1, #7
     6ae:	b289      	uxth	r1, r1
		if (process_recheck(mgr) != EVT_NOP) {
     6b0:	4620      	mov	r0, r4
	mgr->flags = (state & ONOFF_STATE_MASK)
     6b2:	8321      	strh	r1, [r4, #24]
		if (process_recheck(mgr) != EVT_NOP) {
     6b4:	f004 fd49 	bl	514a <process_recheck>
     6b8:	b110      	cbz	r0, 6c0 <process_event+0xe0>
			mgr->flags |= ONOFF_FLAG_RECHECK;
     6ba:	f041 0120 	orr.w	r1, r1, #32
     6be:	8321      	strh	r1, [r4, #24]
     6c0:	2500      	movs	r5, #0
     6c2:	e7bf      	b.n	644 <process_event+0x64>
		} else if (evt == EVT_START) {
     6c4:	2803      	cmp	r0, #3
     6c6:	d109      	bne.n	6dc <process_event+0xfc>
			transit = mgr->transitions->start;
     6c8:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     6ca:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->start;
     6ce:	6816      	ldr	r6, [r2, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     6d0:	f043 0306 	orr.w	r3, r3, #6
}
     6d4:	2500      	movs	r5, #0
	mgr->flags = (state & ONOFF_STATE_MASK)
     6d6:	8323      	strh	r3, [r4, #24]
		res = 0;
     6d8:	462f      	mov	r7, r5
     6da:	e7b4      	b.n	646 <process_event+0x66>
		} else if (evt == EVT_STOP) {
     6dc:	2804      	cmp	r0, #4
     6de:	d106      	bne.n	6ee <process_event+0x10e>
			transit = mgr->transitions->stop;
     6e0:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     6e2:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->stop;
     6e6:	6856      	ldr	r6, [r2, #4]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     6e8:	f043 0304 	orr.w	r3, r3, #4
     6ec:	e7f2      	b.n	6d4 <process_event+0xf4>
		} else if (evt == EVT_RESET) {
     6ee:	2805      	cmp	r0, #5
     6f0:	d106      	bne.n	700 <process_event+0x120>
			transit = mgr->transitions->reset;
     6f2:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     6f4:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->reset;
     6f8:	6896      	ldr	r6, [r2, #8]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
     6fa:	f043 0305 	orr.w	r3, r3, #5
     6fe:	e7e9      	b.n	6d4 <process_event+0xf4>
     700:	2500      	movs	r5, #0
		onoff_transition_fn transit = NULL;
     702:	462e      	mov	r6, r5
     704:	e7e8      	b.n	6d8 <process_event+0xf8>
				   && !sys_slist_is_empty(&mgr->monitors);
     706:	2301      	movs	r3, #1
			uint32_t flags = mgr->flags | ONOFF_FLAG_PROCESSING;
     708:	f041 0108 	orr.w	r1, r1, #8
			mgr->flags = flags;
     70c:	8321      	strh	r1, [r4, #24]
     70e:	f38b 8811 	msr	BASEPRI, fp
     712:	f3bf 8f6f 	isb	sy
			if (do_monitors) {
     716:	bb03      	cbnz	r3, 75a <process_event+0x17a>
	while (!sys_slist_is_empty(list)) {
     718:	2d00      	cmp	r5, #0
     71a:	d131      	bne.n	780 <process_event+0x1a0>
			if (transit != NULL) {
     71c:	b116      	cbz	r6, 724 <process_event+0x144>
				transit(mgr, transition_complete);
     71e:	4651      	mov	r1, sl
     720:	4620      	mov	r0, r4
     722:	47b0      	blx	r6
	__asm__ volatile(
     724:	f04f 0320 	mov.w	r3, #32
     728:	f3ef 8b11 	mrs	fp, BASEPRI
     72c:	f383 8811 	msr	BASEPRI, r3
     730:	f3bf 8f6f 	isb	sy
			mgr->flags &= ~ONOFF_FLAG_PROCESSING;
     734:	8b23      	ldrh	r3, [r4, #24]
     736:	f023 0308 	bic.w	r3, r3, #8
     73a:	8323      	strh	r3, [r4, #24]
		if ((mgr->flags & ONOFF_FLAG_COMPLETE) != 0) {
     73c:	8b23      	ldrh	r3, [r4, #24]
     73e:	06da      	lsls	r2, r3, #27
     740:	d527      	bpl.n	792 <process_event+0x1b2>
			evt = EVT_COMPLETE;
     742:	2101      	movs	r1, #1
			mgr->flags &= ~ONOFF_FLAG_COMPLETE;
     744:	f023 0310 	bic.w	r3, r3, #16
     748:	8323      	strh	r3, [r4, #24]
		state = mgr->flags & ONOFF_STATE_MASK;
     74a:	f8b4 9018 	ldrh.w	r9, [r4, #24]
     74e:	f009 0907 	and.w	r9, r9, #7
	} while (evt != EVT_NOP);
     752:	2900      	cmp	r1, #0
     754:	f47f af60 	bne.w	618 <process_event+0x38>
out:
     758:	e753      	b.n	602 <process_event+0x22>
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
     75a:	68a1      	ldr	r1, [r4, #8]
     75c:	2900      	cmp	r1, #0
     75e:	d0db      	beq.n	718 <process_event+0x138>
     760:	f8d1 9000 	ldr.w	r9, [r1]
		mon->callback(mgr, mon, state, res);
     764:	463b      	mov	r3, r7
     766:	4620      	mov	r0, r4
     768:	f8d1 b004 	ldr.w	fp, [r1, #4]
     76c:	9201      	str	r2, [sp, #4]
     76e:	47d8      	blx	fp
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
     770:	9a01      	ldr	r2, [sp, #4]
     772:	f1b9 0f00 	cmp.w	r9, #0
     776:	d0cf      	beq.n	718 <process_event+0x138>
     778:	4649      	mov	r1, r9
     77a:	f8d9 9000 	ldr.w	r9, [r9]
     77e:	e7f1      	b.n	764 <process_event+0x184>
 *
 * @return A pointer to the first node of the list
 */
static inline sys_snode_t *sys_slist_get_not_empty(sys_slist_t *list);

Z_GENLIST_GET_NOT_EMPTY(slist, snode)
     780:	4629      	mov	r1, r5
		notify_one(mgr, cli, state, res);
     782:	463b      	mov	r3, r7
     784:	4620      	mov	r0, r4
     786:	9201      	str	r2, [sp, #4]
     788:	682d      	ldr	r5, [r5, #0]
     78a:	f004 fcfa 	bl	5182 <notify_one>
	while (!sys_slist_is_empty(list)) {
     78e:	9a01      	ldr	r2, [sp, #4]
     790:	e7c2      	b.n	718 <process_event+0x138>
		} else if ((mgr->flags & ONOFF_FLAG_RECHECK) != 0) {
     792:	f013 0120 	ands.w	r1, r3, #32
			mgr->flags &= ~ONOFF_FLAG_RECHECK;
     796:	bf1e      	ittt	ne
     798:	f023 0320 	bicne.w	r3, r3, #32
			evt = EVT_RECHECK;
     79c:	2102      	movne	r1, #2
			mgr->flags &= ~ONOFF_FLAG_RECHECK;
     79e:	8323      	strhne	r3, [r4, #24]
			evt = EVT_RECHECK;
     7a0:	e7d3      	b.n	74a <process_event+0x16a>
     7a2:	bf00      	nop
     7a4:	000051af 	.word	0x000051af

000007a8 <cbvprintf>:

	return (int)count;
}

int cbvprintf(cbprintf_cb out, void *ctx, const char *fp, va_list ap)
{
     7a8:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     7ac:	4688      	mov	r8, r1
     7ae:	4691      	mov	r9, r2
     7b0:	461c      	mov	r4, r3
	char buf[CONVERTED_BUFLEN];
	size_t count = 0;
     7b2:	2500      	movs	r5, #0
{
     7b4:	b0a5      	sub	sp, #148	; 0x94
     7b6:	9003      	str	r0, [sp, #12]
		return rc; \
	} \
	count += rc; \
} while (false)

	while (*fp != 0) {
     7b8:	f899 0000 	ldrb.w	r0, [r9]
     7bc:	b910      	cbnz	r0, 7c4 <cbvprintf+0x1c>
			OUTC(' ');
			--width;
		}
	}

	return count;
     7be:	4628      	mov	r0, r5
     7c0:	f000 be18 	b.w	13f4 <CONFIG_ISR_STACK_SIZE+0xbf4>
		if (*fp != '%') {
     7c4:	f109 0301 	add.w	r3, r9, #1
     7c8:	2825      	cmp	r0, #37	; 0x25
     7ca:	9309      	str	r3, [sp, #36]	; 0x24
     7cc:	d007      	beq.n	7de <cbvprintf+0x36>
			OUTC(*fp++);
     7ce:	4641      	mov	r1, r8
			OUTC('%');
     7d0:	9b03      	ldr	r3, [sp, #12]
     7d2:	4798      	blx	r3
     7d4:	2800      	cmp	r0, #0
     7d6:	f2c0 860d 	blt.w	13f4 <CONFIG_ISR_STACK_SIZE+0xbf4>
     7da:	3501      	adds	r5, #1
		if (bps == NULL) {
     7dc:	e245      	b.n	c6a <CONFIG_ISR_STACK_SIZE+0x46a>
		} state = {
     7de:	2218      	movs	r2, #24
     7e0:	2100      	movs	r1, #0
     7e2:	a816      	add	r0, sp, #88	; 0x58
     7e4:	f005 f8a3 	bl	592e <memset>
	if (*sp == '%') {
     7e8:	f899 3001 	ldrb.w	r3, [r9, #1]
     7ec:	2b25      	cmp	r3, #37	; 0x25
     7ee:	d079      	beq.n	8e4 <CONFIG_ISR_STACK_SIZE+0xe4>
     7f0:	2200      	movs	r2, #0
     7f2:	4616      	mov	r6, r2
     7f4:	4696      	mov	lr, r2
     7f6:	4617      	mov	r7, r2
     7f8:	4694      	mov	ip, r2
     7fa:	9809      	ldr	r0, [sp, #36]	; 0x24
     7fc:	4601      	mov	r1, r0
		switch (*sp) {
     7fe:	f810 3b01 	ldrb.w	r3, [r0], #1
     802:	2b2b      	cmp	r3, #43	; 0x2b
     804:	f000 809e 	beq.w	944 <CONFIG_ISR_STACK_SIZE+0x144>
     808:	f200 8095 	bhi.w	936 <CONFIG_ISR_STACK_SIZE+0x136>
     80c:	2b20      	cmp	r3, #32
     80e:	f000 809b 	beq.w	948 <CONFIG_ISR_STACK_SIZE+0x148>
     812:	2b23      	cmp	r3, #35	; 0x23
     814:	f000 809b 	beq.w	94e <CONFIG_ISR_STACK_SIZE+0x14e>
     818:	f1bc 0f00 	cmp.w	ip, #0
     81c:	d005      	beq.n	82a <CONFIG_ISR_STACK_SIZE+0x2a>
     81e:	f89d 0060 	ldrb.w	r0, [sp, #96]	; 0x60
     822:	f040 0004 	orr.w	r0, r0, #4
     826:	f88d 0060 	strb.w	r0, [sp, #96]	; 0x60
     82a:	b12f      	cbz	r7, 838 <CONFIG_ISR_STACK_SIZE+0x38>
     82c:	f89d 0060 	ldrb.w	r0, [sp, #96]	; 0x60
     830:	f040 0008 	orr.w	r0, r0, #8
     834:	f88d 0060 	strb.w	r0, [sp, #96]	; 0x60
     838:	f1be 0f00 	cmp.w	lr, #0
     83c:	d005      	beq.n	84a <CONFIG_ISR_STACK_SIZE+0x4a>
     83e:	f89d 0060 	ldrb.w	r0, [sp, #96]	; 0x60
     842:	f040 0010 	orr.w	r0, r0, #16
     846:	f88d 0060 	strb.w	r0, [sp, #96]	; 0x60
     84a:	b12e      	cbz	r6, 858 <CONFIG_ISR_STACK_SIZE+0x58>
     84c:	f89d 0060 	ldrb.w	r0, [sp, #96]	; 0x60
     850:	f040 0020 	orr.w	r0, r0, #32
     854:	f88d 0060 	strb.w	r0, [sp, #96]	; 0x60
     858:	b12a      	cbz	r2, 866 <CONFIG_ISR_STACK_SIZE+0x66>
     85a:	f89d 2060 	ldrb.w	r2, [sp, #96]	; 0x60
     85e:	f042 0240 	orr.w	r2, r2, #64	; 0x40
     862:	f88d 2060 	strb.w	r2, [sp, #96]	; 0x60
	if (conv->flag_zero && conv->flag_dash) {
     866:	f89d 2060 	ldrb.w	r2, [sp, #96]	; 0x60
     86a:	f002 0044 	and.w	r0, r2, #68	; 0x44
     86e:	2844      	cmp	r0, #68	; 0x44
     870:	d103      	bne.n	87a <CONFIG_ISR_STACK_SIZE+0x7a>
		conv->flag_zero = false;
     872:	f36f 1286 	bfc	r2, #6, #1
     876:	f88d 2060 	strb.w	r2, [sp, #96]	; 0x60
	conv->width_present = true;
     87a:	f89d 2060 	ldrb.w	r2, [sp, #96]	; 0x60
	if (*sp == '*') {
     87e:	2b2a      	cmp	r3, #42	; 0x2a
	conv->width_present = true;
     880:	f042 0280 	orr.w	r2, r2, #128	; 0x80
     884:	f88d 2060 	strb.w	r2, [sp, #96]	; 0x60
	if (*sp == '*') {
     888:	d17c      	bne.n	984 <CONFIG_ISR_STACK_SIZE+0x184>
		conv->width_star = true;
     88a:	f89d 2061 	ldrb.w	r2, [sp, #97]	; 0x61
     88e:	1c4b      	adds	r3, r1, #1
     890:	f042 0201 	orr.w	r2, r2, #1
     894:	f88d 2061 	strb.w	r2, [sp, #97]	; 0x61
	conv->prec_present = (*sp == '.');
     898:	781a      	ldrb	r2, [r3, #0]
     89a:	2a2e      	cmp	r2, #46	; 0x2e
     89c:	bf0c      	ite	eq
     89e:	2101      	moveq	r1, #1
     8a0:	2100      	movne	r1, #0
     8a2:	f89d 2061 	ldrb.w	r2, [sp, #97]	; 0x61
     8a6:	f361 0241 	bfi	r2, r1, #1, #1
     8aa:	f88d 2061 	strb.w	r2, [sp, #97]	; 0x61
	if (!conv->prec_present) {
     8ae:	d175      	bne.n	99c <CONFIG_ISR_STACK_SIZE+0x19c>
	if (*sp == '*') {
     8b0:	785a      	ldrb	r2, [r3, #1]
     8b2:	2a2a      	cmp	r2, #42	; 0x2a
     8b4:	d06b      	beq.n	98e <CONFIG_ISR_STACK_SIZE+0x18e>
	size_t val = 0;
     8b6:	2100      	movs	r1, #0
		val = 10U * val + *sp++ - '0';
     8b8:	260a      	movs	r6, #10
     8ba:	3301      	adds	r3, #1
			(((unsigned)c) <= (unsigned)'~'));
}

static inline int isdigit(int a)
{
	return (int)(((unsigned)(a)-(unsigned)'0') < 10U);
     8bc:	4618      	mov	r0, r3
     8be:	f810 2b01 	ldrb.w	r2, [r0], #1
     8c2:	f1a2 0730 	sub.w	r7, r2, #48	; 0x30
	while (isdigit((int)(unsigned char)*sp)) {
     8c6:	2f09      	cmp	r7, #9
     8c8:	f240 80aa 	bls.w	a20 <CONFIG_ISR_STACK_SIZE+0x220>
	conv->unsupported |= ((conv->prec_value < 0)
     8cc:	f89d 2060 	ldrb.w	r2, [sp, #96]	; 0x60
	conv->prec_value = prec;
     8d0:	911a      	str	r1, [sp, #104]	; 0x68
	conv->unsupported |= ((conv->prec_value < 0)
     8d2:	f3c2 0040 	ubfx	r0, r2, #1, #1
     8d6:	ea40 71d1 	orr.w	r1, r0, r1, lsr #31
     8da:	f361 0241 	bfi	r2, r1, #1, #1
     8de:	f88d 2060 	strb.w	r2, [sp, #96]	; 0x60
	return sp;
     8e2:	e05b      	b.n	99c <CONFIG_ISR_STACK_SIZE+0x19c>
		conv->specifier = *sp++;
     8e4:	f109 0202 	add.w	r2, r9, #2
     8e8:	9209      	str	r2, [sp, #36]	; 0x24
     8ea:	f88d 3063 	strb.w	r3, [sp, #99]	; 0x63
		if (conv->width_star) {
     8ee:	f89d 3061 	ldrb.w	r3, [sp, #97]	; 0x61
     8f2:	07de      	lsls	r6, r3, #31
     8f4:	f140 816f 	bpl.w	bd6 <CONFIG_ISR_STACK_SIZE+0x3d6>
			width = va_arg(ap, int);
     8f8:	f854 2b04 	ldr.w	r2, [r4], #4
			if (width < 0) {
     8fc:	2a00      	cmp	r2, #0
			width = va_arg(ap, int);
     8fe:	9208      	str	r2, [sp, #32]
			if (width < 0) {
     900:	da08      	bge.n	914 <CONFIG_ISR_STACK_SIZE+0x114>
				conv->flag_dash = true;
     902:	f89d 2060 	ldrb.w	r2, [sp, #96]	; 0x60
     906:	f042 0204 	orr.w	r2, r2, #4
     90a:	f88d 2060 	strb.w	r2, [sp, #96]	; 0x60
				width = -width;
     90e:	9a08      	ldr	r2, [sp, #32]
     910:	4252      	negs	r2, r2
		int width = -1;
     912:	9208      	str	r2, [sp, #32]
		if (conv->prec_star) {
     914:	0758      	lsls	r0, r3, #29
     916:	f140 8166 	bpl.w	be6 <CONFIG_ISR_STACK_SIZE+0x3e6>
			int arg = va_arg(ap, int);
     91a:	f854 7b04 	ldr.w	r7, [r4], #4
			if (arg < 0) {
     91e:	2f00      	cmp	r7, #0
     920:	f280 8165 	bge.w	bee <CONFIG_ISR_STACK_SIZE+0x3ee>
				conv->prec_present = false;
     924:	f89d 3061 	ldrb.w	r3, [sp, #97]	; 0x61
     928:	f36f 0341 	bfc	r3, #1, #1
     92c:	f88d 3061 	strb.w	r3, [sp, #97]	; 0x61
		int precision = -1;
     930:	f04f 37ff 	mov.w	r7, #4294967295	; 0xffffffff
     934:	e15b      	b.n	bee <CONFIG_ISR_STACK_SIZE+0x3ee>
		switch (*sp) {
     936:	2b2d      	cmp	r3, #45	; 0x2d
     938:	d00b      	beq.n	952 <CONFIG_ISR_STACK_SIZE+0x152>
     93a:	2b30      	cmp	r3, #48	; 0x30
     93c:	f47f af6c 	bne.w	818 <CONFIG_ISR_STACK_SIZE+0x18>
			conv->flag_zero = true;
     940:	2201      	movs	r2, #1
	} while (loop);
     942:	e75b      	b.n	7fc <cbvprintf+0x54>
			conv->flag_plus = true;
     944:	2701      	movs	r7, #1
     946:	e759      	b.n	7fc <cbvprintf+0x54>
			conv->flag_space = true;
     948:	f04f 0e01 	mov.w	lr, #1
     94c:	e756      	b.n	7fc <cbvprintf+0x54>
			conv->flag_hash = true;
     94e:	2601      	movs	r6, #1
     950:	e754      	b.n	7fc <cbvprintf+0x54>
		switch (*sp) {
     952:	f04f 0c01 	mov.w	ip, #1
     956:	e751      	b.n	7fc <cbvprintf+0x54>
		val = 10U * val + *sp++ - '0';
     958:	4633      	mov	r3, r6
     95a:	fb0c 0202 	mla	r2, ip, r2, r0
     95e:	3a30      	subs	r2, #48	; 0x30
     960:	461e      	mov	r6, r3
     962:	f816 0b01 	ldrb.w	r0, [r6], #1
     966:	f1a0 0730 	sub.w	r7, r0, #48	; 0x30
	while (isdigit((int)(unsigned char)*sp)) {
     96a:	2f09      	cmp	r7, #9
     96c:	d9f4      	bls.n	958 <CONFIG_ISR_STACK_SIZE+0x158>
	if (sp != wp) {
     96e:	4299      	cmp	r1, r3
     970:	d092      	beq.n	898 <CONFIG_ISR_STACK_SIZE+0x98>
		conv->unsupported |= ((conv->width_value < 0)
     972:	f89d 1060 	ldrb.w	r1, [sp, #96]	; 0x60
		conv->width_value = width;
     976:	9219      	str	r2, [sp, #100]	; 0x64
				      || (width != (size_t)conv->width_value));
     978:	0fd2      	lsrs	r2, r2, #31
		conv->unsupported |= ((conv->width_value < 0)
     97a:	f362 0141 	bfi	r1, r2, #1, #1
     97e:	f88d 1060 	strb.w	r1, [sp, #96]	; 0x60
     982:	e789      	b.n	898 <CONFIG_ISR_STACK_SIZE+0x98>
     984:	460b      	mov	r3, r1
	size_t val = 0;
     986:	2200      	movs	r2, #0
		val = 10U * val + *sp++ - '0';
     988:	f04f 0c0a 	mov.w	ip, #10
     98c:	e7e8      	b.n	960 <CONFIG_ISR_STACK_SIZE+0x160>
		conv->prec_star = true;
     98e:	f89d 2061 	ldrb.w	r2, [sp, #97]	; 0x61
		return ++sp;
     992:	3302      	adds	r3, #2
		conv->prec_star = true;
     994:	f042 0204 	orr.w	r2, r2, #4
     998:	f88d 2061 	strb.w	r2, [sp, #97]	; 0x61
	switch (*sp) {
     99c:	4619      	mov	r1, r3
     99e:	f811 2b01 	ldrb.w	r2, [r1], #1
     9a2:	2a6c      	cmp	r2, #108	; 0x6c
     9a4:	d05c      	beq.n	a60 <CONFIG_ISR_STACK_SIZE+0x260>
     9a6:	d840      	bhi.n	a2a <CONFIG_ISR_STACK_SIZE+0x22a>
     9a8:	2a68      	cmp	r2, #104	; 0x68
     9aa:	d046      	beq.n	a3a <CONFIG_ISR_STACK_SIZE+0x23a>
     9ac:	2a6a      	cmp	r2, #106	; 0x6a
     9ae:	d061      	beq.n	a74 <CONFIG_ISR_STACK_SIZE+0x274>
     9b0:	2a4c      	cmp	r2, #76	; 0x4c
     9b2:	d067      	beq.n	a84 <CONFIG_ISR_STACK_SIZE+0x284>
     9b4:	4619      	mov	r1, r3
	conv->specifier = *sp++;
     9b6:	460b      	mov	r3, r1
     9b8:	f813 2b01 	ldrb.w	r2, [r3], #1
	switch (conv->specifier) {
     9bc:	2a78      	cmp	r2, #120	; 0x78
	conv->specifier = *sp++;
     9be:	9309      	str	r3, [sp, #36]	; 0x24
     9c0:	f88d 2063 	strb.w	r2, [sp, #99]	; 0x63
	switch (conv->specifier) {
     9c4:	f200 80df 	bhi.w	b86 <CONFIG_ISR_STACK_SIZE+0x386>
     9c8:	2a57      	cmp	r2, #87	; 0x57
     9ca:	d868      	bhi.n	a9e <CONFIG_ISR_STACK_SIZE+0x29e>
     9cc:	2a41      	cmp	r2, #65	; 0x41
     9ce:	d004      	beq.n	9da <CONFIG_ISR_STACK_SIZE+0x1da>
     9d0:	f1a2 0345 	sub.w	r3, r2, #69	; 0x45
     9d4:	2b02      	cmp	r3, #2
     9d6:	f200 80d6 	bhi.w	b86 <CONFIG_ISR_STACK_SIZE+0x386>
		conv->specifier_cat = SPECIFIER_FP;
     9da:	2104      	movs	r1, #4
     9dc:	f89d 3062 	ldrb.w	r3, [sp, #98]	; 0x62
			|| (conv->specifier == 'A');
     9e0:	f002 02df 	and.w	r2, r2, #223	; 0xdf
     9e4:	f1a2 0a41 	sub.w	sl, r2, #65	; 0x41
		conv->specifier_cat = SPECIFIER_FP;
     9e8:	f361 0302 	bfi	r3, r1, #0, #3
			|| (conv->specifier == 'A');
     9ec:	f1da 0200 	rsbs	r2, sl, #0
		conv->specifier_a = (conv->specifier == 'a')
     9f0:	f89d 1061 	ldrb.w	r1, [sp, #97]	; 0x61
			|| (conv->specifier == 'A');
     9f4:	eb42 020a 	adc.w	r2, r2, sl
		conv->specifier_a = (conv->specifier == 'a')
     9f8:	f362 11c7 	bfi	r1, r2, #7, #1
		if (conv->specifier_a
     9fc:	060a      	lsls	r2, r1, #24
		conv->specifier_cat = SPECIFIER_FP;
     9fe:	f88d 3062 	strb.w	r3, [sp, #98]	; 0x62
		conv->specifier_a = (conv->specifier == 'a')
     a02:	f88d 1061 	strb.w	r1, [sp, #97]	; 0x61
		if (conv->specifier_a
     a06:	b2cb      	uxtb	r3, r1
     a08:	f100 80e3 	bmi.w	bd2 <CONFIG_ISR_STACK_SIZE+0x3d2>
		if (conv->length_mod == LENGTH_L) {
     a0c:	f003 0278 	and.w	r2, r3, #120	; 0x78
     a10:	2a18      	cmp	r2, #24
     a12:	f040 80b5 	bne.w	b80 <CONFIG_ISR_STACK_SIZE+0x380>
			conv->length_mod = LENGTH_NONE;
     a16:	f36f 03c6 	bfc	r3, #3, #4
     a1a:	f88d 3061 	strb.w	r3, [sp, #97]	; 0x61
     a1e:	e09c      	b.n	b5a <CONFIG_ISR_STACK_SIZE+0x35a>
		val = 10U * val + *sp++ - '0';
     a20:	fb06 2101 	mla	r1, r6, r1, r2
     a24:	4603      	mov	r3, r0
     a26:	3930      	subs	r1, #48	; 0x30
     a28:	e748      	b.n	8bc <CONFIG_ISR_STACK_SIZE+0xbc>
	switch (*sp) {
     a2a:	2a74      	cmp	r2, #116	; 0x74
     a2c:	d026      	beq.n	a7c <CONFIG_ISR_STACK_SIZE+0x27c>
     a2e:	2a7a      	cmp	r2, #122	; 0x7a
     a30:	d1c0      	bne.n	9b4 <CONFIG_ISR_STACK_SIZE+0x1b4>
		conv->length_mod = LENGTH_Z;
     a32:	2206      	movs	r2, #6
     a34:	f89d 3061 	ldrb.w	r3, [sp, #97]	; 0x61
     a38:	e00d      	b.n	a56 <CONFIG_ISR_STACK_SIZE+0x256>
		if (*++sp == 'h') {
     a3a:	785a      	ldrb	r2, [r3, #1]
     a3c:	2a68      	cmp	r2, #104	; 0x68
     a3e:	f89d 2061 	ldrb.w	r2, [sp, #97]	; 0x61
     a42:	d106      	bne.n	a52 <CONFIG_ISR_STACK_SIZE+0x252>
			conv->length_mod = LENGTH_HH;
     a44:	2101      	movs	r1, #1
			conv->length_mod = LENGTH_LL;
     a46:	f361 02c6 	bfi	r2, r1, #3, #4
     a4a:	f88d 2061 	strb.w	r2, [sp, #97]	; 0x61
			++sp;
     a4e:	1c99      	adds	r1, r3, #2
     a50:	e7b1      	b.n	9b6 <CONFIG_ISR_STACK_SIZE+0x1b6>
			conv->length_mod = LENGTH_H;
     a52:	4613      	mov	r3, r2
     a54:	2202      	movs	r2, #2
		conv->length_mod = LENGTH_T;
     a56:	f362 03c6 	bfi	r3, r2, #3, #4
     a5a:	f88d 3061 	strb.w	r3, [sp, #97]	; 0x61
		break;
     a5e:	e7aa      	b.n	9b6 <CONFIG_ISR_STACK_SIZE+0x1b6>
		if (*++sp == 'l') {
     a60:	785a      	ldrb	r2, [r3, #1]
     a62:	2a6c      	cmp	r2, #108	; 0x6c
     a64:	f89d 2061 	ldrb.w	r2, [sp, #97]	; 0x61
     a68:	d101      	bne.n	a6e <CONFIG_ISR_STACK_SIZE+0x26e>
			conv->length_mod = LENGTH_LL;
     a6a:	2104      	movs	r1, #4
     a6c:	e7eb      	b.n	a46 <CONFIG_ISR_STACK_SIZE+0x246>
			conv->length_mod = LENGTH_L;
     a6e:	4613      	mov	r3, r2
     a70:	2203      	movs	r2, #3
     a72:	e7f0      	b.n	a56 <CONFIG_ISR_STACK_SIZE+0x256>
		conv->length_mod = LENGTH_J;
     a74:	2205      	movs	r2, #5
     a76:	f89d 3061 	ldrb.w	r3, [sp, #97]	; 0x61
     a7a:	e7ec      	b.n	a56 <CONFIG_ISR_STACK_SIZE+0x256>
		conv->length_mod = LENGTH_T;
     a7c:	2207      	movs	r2, #7
     a7e:	f89d 3061 	ldrb.w	r3, [sp, #97]	; 0x61
     a82:	e7e8      	b.n	a56 <CONFIG_ISR_STACK_SIZE+0x256>
		conv->unsupported = true;
     a84:	f8bd 3060 	ldrh.w	r3, [sp, #96]	; 0x60
     a88:	f423 43f0 	bic.w	r3, r3, #30720	; 0x7800
     a8c:	f023 0302 	bic.w	r3, r3, #2
     a90:	f443 4380 	orr.w	r3, r3, #16384	; 0x4000
     a94:	f043 0302 	orr.w	r3, r3, #2
     a98:	f8ad 3060 	strh.w	r3, [sp, #96]	; 0x60
		break;
     a9c:	e78b      	b.n	9b6 <CONFIG_ISR_STACK_SIZE+0x1b6>
     a9e:	f1a2 0358 	sub.w	r3, r2, #88	; 0x58
     aa2:	2b20      	cmp	r3, #32
     aa4:	d86f      	bhi.n	b86 <CONFIG_ISR_STACK_SIZE+0x386>
     aa6:	a101      	add	r1, pc, #4	; (adr r1, aac <CONFIG_ISR_STACK_SIZE+0x2ac>)
     aa8:	f851 f023 	ldr.w	pc, [r1, r3, lsl #2]
     aac:	00000b5f 	.word	0x00000b5f
     ab0:	00000b87 	.word	0x00000b87
     ab4:	00000b87 	.word	0x00000b87
     ab8:	00000b87 	.word	0x00000b87
     abc:	00000b87 	.word	0x00000b87
     ac0:	00000b87 	.word	0x00000b87
     ac4:	00000b87 	.word	0x00000b87
     ac8:	00000b87 	.word	0x00000b87
     acc:	00000b87 	.word	0x00000b87
     ad0:	000009db 	.word	0x000009db
     ad4:	00000b87 	.word	0x00000b87
     ad8:	00000b5f 	.word	0x00000b5f
     adc:	00000b31 	.word	0x00000b31
     ae0:	000009db 	.word	0x000009db
     ae4:	000009db 	.word	0x000009db
     ae8:	000009db 	.word	0x000009db
     aec:	00000b87 	.word	0x00000b87
     af0:	00000b31 	.word	0x00000b31
     af4:	00000b87 	.word	0x00000b87
     af8:	00000b87 	.word	0x00000b87
     afc:	00000b87 	.word	0x00000b87
     b00:	00000b87 	.word	0x00000b87
     b04:	00000b95 	.word	0x00000b95
     b08:	00000b5f 	.word	0x00000b5f
     b0c:	00000bb5 	.word	0x00000bb5
     b10:	00000b87 	.word	0x00000b87
     b14:	00000b87 	.word	0x00000b87
     b18:	00000bb5 	.word	0x00000bb5
     b1c:	00000b87 	.word	0x00000b87
     b20:	00000b5f 	.word	0x00000b5f
     b24:	00000b87 	.word	0x00000b87
     b28:	00000b87 	.word	0x00000b87
     b2c:	00000b5f 	.word	0x00000b5f
		conv->specifier_cat = SPECIFIER_SINT;
     b30:	2101      	movs	r1, #1
     b32:	f89d 3062 	ldrb.w	r3, [sp, #98]	; 0x62
		conv->specifier_cat = SPECIFIER_UINT;
     b36:	f361 0302 	bfi	r3, r1, #0, #3
     b3a:	f88d 3062 	strb.w	r3, [sp, #98]	; 0x62
		if (conv->length_mod == LENGTH_UPPER_L) {
     b3e:	f89d 3061 	ldrb.w	r3, [sp, #97]	; 0x61
     b42:	f003 0378 	and.w	r3, r3, #120	; 0x78
     b46:	2b40      	cmp	r3, #64	; 0x40
			conv->invalid = true;
     b48:	bf02      	ittt	eq
     b4a:	f89d 1060 	ldrbeq.w	r1, [sp, #96]	; 0x60
     b4e:	f041 0101 	orreq.w	r1, r1, #1
     b52:	f88d 1060 	strbeq.w	r1, [sp, #96]	; 0x60
		if (conv->specifier == 'c') {
     b56:	2a63      	cmp	r2, #99	; 0x63
     b58:	d005      	beq.n	b66 <CONFIG_ISR_STACK_SIZE+0x366>
	bool unsupported = false;
     b5a:	2300      	movs	r3, #0
     b5c:	e006      	b.n	b6c <CONFIG_ISR_STACK_SIZE+0x36c>
		conv->specifier_cat = SPECIFIER_UINT;
     b5e:	2102      	movs	r1, #2
     b60:	f89d 3062 	ldrb.w	r3, [sp, #98]	; 0x62
     b64:	e7e7      	b.n	b36 <CONFIG_ISR_STACK_SIZE+0x336>
			unsupported = (conv->length_mod != LENGTH_NONE);
     b66:	3b00      	subs	r3, #0
     b68:	bf18      	it	ne
     b6a:	2301      	movne	r3, #1
	conv->unsupported |= unsupported;
     b6c:	f89d 2060 	ldrb.w	r2, [sp, #96]	; 0x60
     b70:	f3c2 0140 	ubfx	r1, r2, #1, #1
     b74:	430b      	orrs	r3, r1
     b76:	f363 0241 	bfi	r2, r3, #1, #1
     b7a:	f88d 2060 	strb.w	r2, [sp, #96]	; 0x60
	return sp;
     b7e:	e6b6      	b.n	8ee <CONFIG_ISR_STACK_SIZE+0xee>
		} else if ((conv->length_mod != LENGTH_NONE)
     b80:	f013 0f38 	tst.w	r3, #56	; 0x38
     b84:	d0e9      	beq.n	b5a <CONFIG_ISR_STACK_SIZE+0x35a>
			conv->invalid = true;
     b86:	f89d 3060 	ldrb.w	r3, [sp, #96]	; 0x60
     b8a:	f043 0301 	orr.w	r3, r3, #1
     b8e:	f88d 3060 	strb.w	r3, [sp, #96]	; 0x60
     b92:	e7e2      	b.n	b5a <CONFIG_ISR_STACK_SIZE+0x35a>
		conv->specifier_cat = SPECIFIER_PTR;
     b94:	2203      	movs	r2, #3
     b96:	f89d 3062 	ldrb.w	r3, [sp, #98]	; 0x62
     b9a:	f362 0302 	bfi	r3, r2, #0, #3
     b9e:	f88d 3062 	strb.w	r3, [sp, #98]	; 0x62
		if (conv->length_mod == LENGTH_UPPER_L) {
     ba2:	f89d 3061 	ldrb.w	r3, [sp, #97]	; 0x61
     ba6:	f003 0378 	and.w	r3, r3, #120	; 0x78
     baa:	f1a3 0740 	sub.w	r7, r3, #64	; 0x40
     bae:	427b      	negs	r3, r7
     bb0:	417b      	adcs	r3, r7
     bb2:	e7db      	b.n	b6c <CONFIG_ISR_STACK_SIZE+0x36c>
		conv->specifier_cat = SPECIFIER_PTR;
     bb4:	2203      	movs	r2, #3
     bb6:	f89d 3062 	ldrb.w	r3, [sp, #98]	; 0x62
     bba:	f362 0302 	bfi	r3, r2, #0, #3
     bbe:	f88d 3062 	strb.w	r3, [sp, #98]	; 0x62
		if (conv->length_mod != LENGTH_NONE) {
     bc2:	f89d 3061 	ldrb.w	r3, [sp, #97]	; 0x61
     bc6:	f013 0f78 	tst.w	r3, #120	; 0x78
     bca:	bf14      	ite	ne
     bcc:	2301      	movne	r3, #1
     bce:	2300      	moveq	r3, #0
     bd0:	e7cc      	b.n	b6c <CONFIG_ISR_STACK_SIZE+0x36c>
			unsupported = true;
     bd2:	2301      	movs	r3, #1
     bd4:	e7ca      	b.n	b6c <CONFIG_ISR_STACK_SIZE+0x36c>
		} else if (conv->width_present) {
     bd6:	f99d 2060 	ldrsb.w	r2, [sp, #96]	; 0x60
     bda:	2a00      	cmp	r2, #0
		int width = -1;
     bdc:	bfac      	ite	ge
     bde:	f04f 32ff 	movge.w	r2, #4294967295	; 0xffffffff
			width = conv->width_value;
     be2:	9a19      	ldrlt	r2, [sp, #100]	; 0x64
     be4:	e695      	b.n	912 <CONFIG_ISR_STACK_SIZE+0x112>
		} else if (conv->prec_present) {
     be6:	0799      	lsls	r1, r3, #30
     be8:	f57f aea2 	bpl.w	930 <CONFIG_ISR_STACK_SIZE+0x130>
			precision = conv->prec_value;
     bec:	9f1a      	ldr	r7, [sp, #104]	; 0x68
		conv->pad0_value = 0;
     bee:	2300      	movs	r3, #0
		conv->pad0_pre_exp = 0;
     bf0:	e9cd 3319 	strd	r3, r3, [sp, #100]	; 0x64
		    && (conv->specifier_cat == SPECIFIER_FP)
     bf4:	f89d 3062 	ldrb.w	r3, [sp, #98]	; 0x62
		if (IS_ENABLED(CONFIG_CBPRINTF_FP_SUPPORT)
     bf8:	f003 0307 	and.w	r3, r3, #7
     bfc:	2b04      	cmp	r3, #4
     bfe:	d109      	bne.n	c14 <CONFIG_ISR_STACK_SIZE+0x414>
		    && !conv->prec_present) {
     c00:	f89d 3061 	ldrb.w	r3, [sp, #97]	; 0x61
     c04:	079a      	lsls	r2, r3, #30
     c06:	d405      	bmi.n	c14 <CONFIG_ISR_STACK_SIZE+0x414>
			if (conv->specifier_a) {
     c08:	f99d 3061 	ldrsb.w	r3, [sp, #97]	; 0x61
				precision = 6;
     c0c:	2b00      	cmp	r3, #0
     c0e:	bfb4      	ite	lt
     c10:	270d      	movlt	r7, #13
     c12:	2706      	movge	r7, #6
			= (enum specifier_cat_enum)conv->specifier_cat;
     c14:	f89d 3062 	ldrb.w	r3, [sp, #98]	; 0x62
			= (enum length_mod_enum)conv->length_mod;
     c18:	f89d 1061 	ldrb.w	r1, [sp, #97]	; 0x61
		enum specifier_cat_enum specifier_cat
     c1c:	f003 0307 	and.w	r3, r3, #7
		if (specifier_cat == SPECIFIER_SINT) {
     c20:	2b01      	cmp	r3, #1
			= (enum length_mod_enum)conv->length_mod;
     c22:	f3c1 01c3 	ubfx	r1, r1, #3, #4
		if (specifier_cat == SPECIFIER_SINT) {
     c26:	d136      	bne.n	c96 <CONFIG_ISR_STACK_SIZE+0x496>
			switch (length_mod) {
     c28:	1ecb      	subs	r3, r1, #3
     c2a:	2b04      	cmp	r3, #4
     c2c:	d820      	bhi.n	c70 <CONFIG_ISR_STACK_SIZE+0x470>
     c2e:	e8df f003 	tbb	[pc, r3]
     c32:	0703      	.short	0x0703
     c34:	1f07      	.short	0x1f07
     c36:	1f          	.byte	0x1f
     c37:	00          	.byte	0x00
					value->sint = va_arg(ap, long);
     c38:	f854 2b04 	ldr.w	r2, [r4], #4
				value->sint = (short)value->sint;
     c3c:	17d3      	asrs	r3, r2, #31
     c3e:	e004      	b.n	c4a <CONFIG_ISR_STACK_SIZE+0x44a>
					(sint_value_type)va_arg(ap, intmax_t);
     c40:	3407      	adds	r4, #7
     c42:	f024 0407 	bic.w	r4, r4, #7
				value->sint =
     c46:	e8f4 2302 	ldrd	r2, r3, [r4], #8
				value->sint = (short)value->sint;
     c4a:	e9cd 2316 	strd	r2, r3, [sp, #88]	; 0x58
		if (conv->invalid || conv->unsupported) {
     c4e:	f89d 6060 	ldrb.w	r6, [sp, #96]	; 0x60
     c52:	07b3      	lsls	r3, r6, #30
     c54:	d055      	beq.n	d02 <CONFIG_ISR_STACK_SIZE+0x502>
			OUTS(sp, fp);
     c56:	464a      	mov	r2, r9
     c58:	4641      	mov	r1, r8
     c5a:	9b09      	ldr	r3, [sp, #36]	; 0x24
     c5c:	9803      	ldr	r0, [sp, #12]
     c5e:	f004 fc87 	bl	5570 <outs>
     c62:	2800      	cmp	r0, #0
     c64:	f2c0 83c6 	blt.w	13f4 <CONFIG_ISR_STACK_SIZE+0xbf4>
     c68:	4405      	add	r5, r0
			while (pad_len-- > 0) {
     c6a:	f8dd 9024 	ldr.w	r9, [sp, #36]	; 0x24
     c6e:	e5a3      	b.n	7b8 <cbvprintf+0x10>
					(sint_value_type)va_arg(ap, ptrdiff_t);
     c70:	f854 2b04 	ldr.w	r2, [r4], #4
			if (length_mod == LENGTH_HH) {
     c74:	2901      	cmp	r1, #1
					(sint_value_type)va_arg(ap, ptrdiff_t);
     c76:	ea4f 73e2 	mov.w	r3, r2, asr #31
     c7a:	e9cd 2316 	strd	r2, r3, [sp, #88]	; 0x58
			if (length_mod == LENGTH_HH) {
     c7e:	d105      	bne.n	c8c <CONFIG_ISR_STACK_SIZE+0x48c>
				value->uint = (unsigned char)value->uint;
     c80:	f89d 3058 	ldrb.w	r3, [sp, #88]	; 0x58
				value->uint = (unsigned short)value->uint;
     c84:	9316      	str	r3, [sp, #88]	; 0x58
     c86:	2300      	movs	r3, #0
     c88:	9317      	str	r3, [sp, #92]	; 0x5c
     c8a:	e7e0      	b.n	c4e <CONFIG_ISR_STACK_SIZE+0x44e>
			} else if (length_mod == LENGTH_H) {
     c8c:	2902      	cmp	r1, #2
     c8e:	d1de      	bne.n	c4e <CONFIG_ISR_STACK_SIZE+0x44e>
				value->sint = (short)value->sint;
     c90:	f9bd 2058 	ldrsh.w	r2, [sp, #88]	; 0x58
     c94:	e7d2      	b.n	c3c <CONFIG_ISR_STACK_SIZE+0x43c>
		} else if (specifier_cat == SPECIFIER_UINT) {
     c96:	2b02      	cmp	r3, #2
     c98:	d123      	bne.n	ce2 <CONFIG_ISR_STACK_SIZE+0x4e2>
			switch (length_mod) {
     c9a:	1ecb      	subs	r3, r1, #3
     c9c:	2b04      	cmp	r3, #4
     c9e:	d813      	bhi.n	cc8 <CONFIG_ISR_STACK_SIZE+0x4c8>
     ca0:	e8df f003 	tbb	[pc, r3]
     ca4:	120a0a03 	.word	0x120a0a03
     ca8:	12          	.byte	0x12
     ca9:	00          	.byte	0x00
				if ((!WCHAR_IS_SIGNED)
     caa:	2300      	movs	r3, #0
					value->uint = (wchar_t)va_arg(ap,
     cac:	6822      	ldr	r2, [r4, #0]
     cae:	1d20      	adds	r0, r4, #4
     cb0:	9216      	str	r2, [sp, #88]	; 0x58
     cb2:	9317      	str	r3, [sp, #92]	; 0x5c
					(uint_value_type)va_arg(ap, size_t);
     cb4:	4604      	mov	r4, r0
     cb6:	e7ca      	b.n	c4e <CONFIG_ISR_STACK_SIZE+0x44e>
					(uint_value_type)va_arg(ap,
     cb8:	3407      	adds	r4, #7
     cba:	f024 0007 	bic.w	r0, r4, #7
				value->uint =
     cbe:	e8f0 2302 	ldrd	r2, r3, [r0], #8
     cc2:	e9cd 2316 	strd	r2, r3, [sp, #88]	; 0x58
				break;
     cc6:	e7f5      	b.n	cb4 <CONFIG_ISR_STACK_SIZE+0x4b4>
					(uint_value_type)va_arg(ap, size_t);
     cc8:	f854 3b04 	ldr.w	r3, [r4], #4
			if (length_mod == LENGTH_HH) {
     ccc:	2901      	cmp	r1, #1
					(uint_value_type)va_arg(ap, size_t);
     cce:	9316      	str	r3, [sp, #88]	; 0x58
     cd0:	f04f 0300 	mov.w	r3, #0
     cd4:	9317      	str	r3, [sp, #92]	; 0x5c
			if (length_mod == LENGTH_HH) {
     cd6:	d0d3      	beq.n	c80 <CONFIG_ISR_STACK_SIZE+0x480>
			} else if (length_mod == LENGTH_H) {
     cd8:	2902      	cmp	r1, #2
     cda:	d1b8      	bne.n	c4e <CONFIG_ISR_STACK_SIZE+0x44e>
				value->uint = (unsigned short)value->uint;
     cdc:	f8bd 3058 	ldrh.w	r3, [sp, #88]	; 0x58
     ce0:	e7d0      	b.n	c84 <CONFIG_ISR_STACK_SIZE+0x484>
		} else if (specifier_cat == SPECIFIER_FP) {
     ce2:	2b04      	cmp	r3, #4
     ce4:	d107      	bne.n	cf6 <CONFIG_ISR_STACK_SIZE+0x4f6>
			if (length_mod == LENGTH_UPPER_L) {
     ce6:	3407      	adds	r4, #7
     ce8:	f024 0407 	bic.w	r4, r4, #7
     cec:	e8f4 2302 	ldrd	r2, r3, [r4], #8
				value->ldbl = va_arg(ap, long double);
     cf0:	e9cd 2316 	strd	r2, r3, [sp, #88]	; 0x58
     cf4:	e7ab      	b.n	c4e <CONFIG_ISR_STACK_SIZE+0x44e>
		} else if (specifier_cat == SPECIFIER_PTR) {
     cf6:	2b03      	cmp	r3, #3
			value->ptr = va_arg(ap, void *);
     cf8:	bf04      	itt	eq
     cfa:	f854 3b04 	ldreq.w	r3, [r4], #4
     cfe:	9316      	streq	r3, [sp, #88]	; 0x58
     d00:	e7a5      	b.n	c4e <CONFIG_ISR_STACK_SIZE+0x44e>
		switch (conv->specifier) {
     d02:	f89d 9063 	ldrb.w	r9, [sp, #99]	; 0x63
     d06:	f1b9 0f78 	cmp.w	r9, #120	; 0x78
     d0a:	d8ae      	bhi.n	c6a <CONFIG_ISR_STACK_SIZE+0x46a>
     d0c:	f1b9 0f57 	cmp.w	r9, #87	; 0x57
     d10:	f200 80a7 	bhi.w	e62 <CONFIG_ISR_STACK_SIZE+0x662>
     d14:	f1b9 0f25 	cmp.w	r9, #37	; 0x25
     d18:	f000 80ee 	beq.w	ef8 <CONFIG_ISR_STACK_SIZE+0x6f8>
     d1c:	f1b9 0f24 	cmp.w	r9, #36	; 0x24
     d20:	d9a3      	bls.n	c6a <CONFIG_ISR_STACK_SIZE+0x46a>
     d22:	f1b9 0f41 	cmp.w	r9, #65	; 0x41
     d26:	d003      	beq.n	d30 <CONFIG_ISR_STACK_SIZE+0x530>
     d28:	f1a9 0345 	sub.w	r3, r9, #69	; 0x45
     d2c:	2b02      	cmp	r3, #2
     d2e:	d89c      	bhi.n	c6a <CONFIG_ISR_STACK_SIZE+0x46a>
	} u = {
     d30:	e9dd 2316 	ldrd	r2, r3, [sp, #88]	; 0x58
	if ((u.u64 & SIGN_MASK) != 0U) {
     d34:	2a00      	cmp	r2, #0
     d36:	f173 0100 	sbcs.w	r1, r3, #0
     d3a:	f2c0 81d5 	blt.w	10e8 <CONFIG_ISR_STACK_SIZE+0x8e8>
	} else if (conv->flag_plus) {
     d3e:	0731      	lsls	r1, r6, #28
     d40:	f100 81d4 	bmi.w	10ec <CONFIG_ISR_STACK_SIZE+0x8ec>
		*sign = ' ';
     d44:	f016 0610 	ands.w	r6, r6, #16
     d48:	bf18      	it	ne
     d4a:	2620      	movne	r6, #32
	int exp = (u.u64 >> FRACTION_BITS) & BIT_MASK(EXPONENT_BITS);
     d4c:	f3c3 5b0a 	ubfx	fp, r3, #20, #11
	uint64_t fract = u.u64 & BIT64_MASK(FRACTION_BITS);
     d50:	f3c3 0313 	ubfx	r3, r3, #0, #20
     d54:	9206      	str	r2, [sp, #24]
     d56:	9307      	str	r3, [sp, #28]
     d58:	e9dd 2306 	ldrd	r2, r3, [sp, #24]
     d5c:	e9cd 2312 	strd	r2, r3, [sp, #72]	; 0x48
	bool is_subnormal = (exp == 0) && (fract != 0);
     d60:	f1bb 0f00 	cmp.w	fp, #0
     d64:	f040 81c4 	bne.w	10f0 <CONFIG_ISR_STACK_SIZE+0x8f0>
     d68:	e9dd 3206 	ldrd	r3, r2, [sp, #24]
     d6c:	4313      	orrs	r3, r2
     d6e:	bf14      	ite	ne
     d70:	f04f 0c01 	movne.w	ip, #1
     d74:	f04f 0c00 	moveq.w	ip, #0
	if ((exp | fract) != 0) {
     d78:	4658      	mov	r0, fp
	fract <<= EXPONENT_BITS;
     d7a:	9907      	ldr	r1, [sp, #28]
		c = 'f';
     d7c:	f1b9 0f46 	cmp.w	r9, #70	; 0x46
	fract <<= EXPONENT_BITS;
     d80:	ea4f 23c1 	mov.w	r3, r1, lsl #11
     d84:	9906      	ldr	r1, [sp, #24]
		c = 'f';
     d86:	bf08      	it	eq
     d88:	f04f 0966 	moveq.w	r9, #102	; 0x66
	fract <<= EXPONENT_BITS;
     d8c:	02ca      	lsls	r2, r1, #11
     d8e:	ea43 5351 	orr.w	r3, r3, r1, lsr #21
	if ((exp | fract) != 0) {
     d92:	ea4b 0102 	orr.w	r1, fp, r2
     d96:	910c      	str	r1, [sp, #48]	; 0x30
     d98:	17c1      	asrs	r1, r0, #31
     d9a:	4319      	orrs	r1, r3
     d9c:	910d      	str	r1, [sp, #52]	; 0x34
     d9e:	e9dd 010c 	ldrd	r0, r1, [sp, #48]	; 0x30
     da2:	4301      	orrs	r1, r0
	fract &= ~SIGN_MASK;
     da4:	e9cd 2312 	strd	r2, r3, [sp, #72]	; 0x48
	if ((exp | fract) != 0) {
     da8:	f000 8215 	beq.w	11d6 <CONFIG_ISR_STACK_SIZE+0x9d6>
		if (is_subnormal) {
     dac:	f1bc 0f00 	cmp.w	ip, #0
     db0:	f040 81d5 	bne.w	115e <CONFIG_ISR_STACK_SIZE+0x95e>
		fract |= BIT_63;
     db4:	9b12      	ldr	r3, [sp, #72]	; 0x48
		fract *= 5U;
     db6:	2105      	movs	r1, #5
		fract |= BIT_63;
     db8:	9304      	str	r3, [sp, #16]
     dba:	9b13      	ldr	r3, [sp, #76]	; 0x4c
		exp -= (1023 - 1);	/* +1 since .1 vs 1. */
     dbc:	f2ab 3bfe 	subw	fp, fp, #1022	; 0x3fe
		fract |= BIT_63;
     dc0:	f043 4300 	orr.w	r3, r3, #2147483648	; 0x80000000
     dc4:	9305      	str	r3, [sp, #20]
     dc6:	e9dd 2304 	ldrd	r2, r3, [sp, #16]
     dca:	e9cd 2312 	strd	r2, r3, [sp, #72]	; 0x48
     dce:	2300      	movs	r3, #0
     dd0:	461a      	mov	r2, r3
	while (exp < -2) {
     dd2:	f11b 0f02 	cmn.w	fp, #2
     dd6:	f2c0 81cb 	blt.w	1170 <CONFIG_ISR_STACK_SIZE+0x970>
     dda:	b11b      	cbz	r3, de4 <CONFIG_ISR_STACK_SIZE+0x5e4>
     ddc:	e9dd 0104 	ldrd	r0, r1, [sp, #16]
     de0:	e9cd 0112 	strd	r0, r1, [sp, #72]	; 0x48
	while (exp > 0) {
     de4:	e9dd 3112 	ldrd	r3, r1, [sp, #72]	; 0x48
     de8:	f1bb 0f00 	cmp.w	fp, #0
     dec:	f300 81db 	bgt.w	11a6 <CONFIG_ISR_STACK_SIZE+0x9a6>
	fract >>= (4 - exp);
     df0:	9913      	ldr	r1, [sp, #76]	; 0x4c
     df2:	9b12      	ldr	r3, [sp, #72]	; 0x48
     df4:	f1cb 0004 	rsb	r0, fp, #4
     df8:	f10b 0b1c 	add.w	fp, fp, #28
     dfc:	fa01 fb0b 	lsl.w	fp, r1, fp
     e00:	f1a0 0c20 	sub.w	ip, r0, #32
     e04:	40c3      	lsrs	r3, r0
     e06:	fa21 fc0c 	lsr.w	ip, r1, ip
     e0a:	ea43 030b 	orr.w	r3, r3, fp
     e0e:	ea43 030c 	orr.w	r3, r3, ip
     e12:	40c1      	lsrs	r1, r0
     e14:	e9cd 3112 	strd	r3, r1, [sp, #72]	; 0x48
	if ((c == 'g') || (c == 'G')) {
     e18:	f009 03df 	and.w	r3, r9, #223	; 0xdf
     e1c:	2b47      	cmp	r3, #71	; 0x47
     e1e:	f040 81e1 	bne.w	11e4 <CONFIG_ISR_STACK_SIZE+0x9e4>
		if (decexp < (-4 + 1) || decexp > precision) {
     e22:	1cd0      	adds	r0, r2, #3
     e24:	db02      	blt.n	e2c <CONFIG_ISR_STACK_SIZE+0x62c>
     e26:	4297      	cmp	r7, r2
     e28:	f280 81d8 	bge.w	11dc <CONFIG_ISR_STACK_SIZE+0x9dc>
			c += 'e' - 'g';  /* e or E */
     e2c:	f1a9 0902 	sub.w	r9, r9, #2
			if (precision > 0) {
     e30:	2f00      	cmp	r7, #0
			c += 'e' - 'g';  /* e or E */
     e32:	fa5f f989 	uxtb.w	r9, r9
			if (precision > 0) {
     e36:	dd00      	ble.n	e3a <CONFIG_ISR_STACK_SIZE+0x63a>
				precision--;
     e38:	3f01      	subs	r7, #1
		if (!conv->flag_hash && (precision > 0)) {
     e3a:	f89d 3060 	ldrb.w	r3, [sp, #96]	; 0x60
     e3e:	0699      	lsls	r1, r3, #26
     e40:	f100 81d0 	bmi.w	11e4 <CONFIG_ISR_STACK_SIZE+0x9e4>
     e44:	2f00      	cmp	r7, #0
     e46:	bfd4      	ite	le
     e48:	2300      	movle	r3, #0
     e4a:	2301      	movgt	r3, #1
	if (c == 'f') {
     e4c:	f1b9 0f66 	cmp.w	r9, #102	; 0x66
	bool prune_zero = false;
     e50:	930e      	str	r3, [sp, #56]	; 0x38
	if (c == 'f') {
     e52:	f040 81c9 	bne.w	11e8 <CONFIG_ISR_STACK_SIZE+0x9e8>
		if (decimals < 0) {
     e56:	18bb      	adds	r3, r7, r2
     e58:	f140 81c7 	bpl.w	11ea <CONFIG_ISR_STACK_SIZE+0x9ea>
			decimals = 0;
     e5c:	f04f 0a00 	mov.w	sl, #0
     e60:	e1c7      	b.n	11f2 <CONFIG_ISR_STACK_SIZE+0x9f2>
     e62:	f1a9 0358 	sub.w	r3, r9, #88	; 0x58
     e66:	2b20      	cmp	r3, #32
     e68:	f63f aeff 	bhi.w	c6a <CONFIG_ISR_STACK_SIZE+0x46a>
     e6c:	a201      	add	r2, pc, #4	; (adr r2, e74 <CONFIG_ISR_STACK_SIZE+0x674>)
     e6e:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
     e72:	bf00      	nop
     e74:	00001089 	.word	0x00001089
     e78:	00000c6b 	.word	0x00000c6b
     e7c:	00000c6b 	.word	0x00000c6b
     e80:	00000c6b 	.word	0x00000c6b
     e84:	00000c6b 	.word	0x00000c6b
     e88:	00000c6b 	.word	0x00000c6b
     e8c:	00000c6b 	.word	0x00000c6b
     e90:	00000c6b 	.word	0x00000c6b
     e94:	00000c6b 	.word	0x00000c6b
     e98:	00000d31 	.word	0x00000d31
     e9c:	00000c6b 	.word	0x00000c6b
     ea0:	00000f25 	.word	0x00000f25
     ea4:	00001029 	.word	0x00001029
     ea8:	00000d31 	.word	0x00000d31
     eac:	00000d31 	.word	0x00000d31
     eb0:	00000d31 	.word	0x00000d31
     eb4:	00000c6b 	.word	0x00000c6b
     eb8:	00001029 	.word	0x00001029
     ebc:	00000c6b 	.word	0x00000c6b
     ec0:	00000c6b 	.word	0x00000c6b
     ec4:	00000c6b 	.word	0x00000c6b
     ec8:	00000c6b 	.word	0x00000c6b
     ecc:	000010bf 	.word	0x000010bf
     ed0:	00001089 	.word	0x00001089
     ed4:	0000108d 	.word	0x0000108d
     ed8:	00000c6b 	.word	0x00000c6b
     edc:	00000c6b 	.word	0x00000c6b
     ee0:	00000eff 	.word	0x00000eff
     ee4:	00000c6b 	.word	0x00000c6b
     ee8:	00001089 	.word	0x00001089
     eec:	00000c6b 	.word	0x00000c6b
     ef0:	00000c6b 	.word	0x00000c6b
     ef4:	00001089 	.word	0x00001089
			OUTC('%');
     ef8:	4641      	mov	r1, r8
     efa:	4648      	mov	r0, r9
     efc:	e468      	b.n	7d0 <cbvprintf+0x28>
			if (precision >= 0) {
     efe:	2f00      	cmp	r7, #0
			bps = (const char *)value->ptr;
     f00:	f8dd 9058 	ldr.w	r9, [sp, #88]	; 0x58
			if (precision >= 0) {
     f04:	db0a      	blt.n	f1c <CONFIG_ISR_STACK_SIZE+0x71c>
				len = strnlen(bps, precision);
     f06:	4639      	mov	r1, r7
     f08:	4648      	mov	r0, r9
     f0a:	f004 fcb5 	bl	5878 <strnlen>
		char sign = 0;
     f0e:	2600      	movs	r6, #0
			bpe = bps + len;
     f10:	eb09 0a00 	add.w	sl, r9, r0
		if (bps == NULL) {
     f14:	f1b9 0f00 	cmp.w	r9, #0
     f18:	d10c      	bne.n	f34 <CONFIG_ISR_STACK_SIZE+0x734>
     f1a:	e6a6      	b.n	c6a <CONFIG_ISR_STACK_SIZE+0x46a>
				len = strlen(bps);
     f1c:	4648      	mov	r0, r9
     f1e:	f004 fca4 	bl	586a <strlen>
     f22:	e7f4      	b.n	f0e <CONFIG_ISR_STACK_SIZE+0x70e>
		char sign = 0;
     f24:	2600      	movs	r6, #0
			buf[0] = CHAR_IS_SIGNED ? value->sint : value->uint;
     f26:	9b16      	ldr	r3, [sp, #88]	; 0x58
			bpe = buf + 1;
     f28:	f10d 0a75 	add.w	sl, sp, #117	; 0x75
			buf[0] = CHAR_IS_SIGNED ? value->sint : value->uint;
     f2c:	f88d 3074 	strb.w	r3, [sp, #116]	; 0x74
				bps = encode_float(value->dbl, conv, precision,
     f30:	f10d 0974 	add.w	r9, sp, #116	; 0x74
		size_t nj_len = (bpe - bps);
     f34:	ebaa 0209 	sub.w	r2, sl, r9
		if (sign != 0) {
     f38:	b106      	cbz	r6, f3c <CONFIG_ISR_STACK_SIZE+0x73c>
			nj_len += 1U;
     f3a:	3201      	adds	r2, #1
		if (conv->altform_0c) {
     f3c:	f89d 0062 	ldrb.w	r0, [sp, #98]	; 0x62
     f40:	06c3      	lsls	r3, r0, #27
     f42:	f140 824c 	bpl.w	13de <CONFIG_ISR_STACK_SIZE+0xbde>
			nj_len += 2U;
     f46:	3202      	adds	r2, #2
		nj_len += conv->pad0_value;
     f48:	9919      	ldr	r1, [sp, #100]	; 0x64
		if (conv->pad_fp) {
     f4a:	0640      	lsls	r0, r0, #25
		nj_len += conv->pad0_value;
     f4c:	440a      	add	r2, r1
		if (width > 0) {
     f4e:	9b08      	ldr	r3, [sp, #32]
			nj_len += conv->pad0_pre_exp;
     f50:	bf44      	itt	mi
     f52:	991a      	ldrmi	r1, [sp, #104]	; 0x68
     f54:	1852      	addmi	r2, r2, r1
		if (width > 0) {
     f56:	2b00      	cmp	r3, #0
     f58:	dd25      	ble.n	fa6 <CONFIG_ISR_STACK_SIZE+0x7a6>
			width -= (int)nj_len;
     f5a:	1a9b      	subs	r3, r3, r2
			if (!conv->flag_dash) {
     f5c:	f89d 2060 	ldrb.w	r2, [sp, #96]	; 0x60
     f60:	0751      	lsls	r1, r2, #29
     f62:	f3c2 0b80 	ubfx	fp, r2, #2, #1
     f66:	f100 824c 	bmi.w	1402 <CONFIG_ISR_STACK_SIZE+0xc02>
				if (conv->flag_zero) {
     f6a:	0657      	lsls	r7, r2, #25
     f6c:	f140 8245 	bpl.w	13fa <CONFIG_ISR_STACK_SIZE+0xbfa>
					if (sign != 0) {
     f70:	2e00      	cmp	r6, #0
     f72:	f000 8244 	beq.w	13fe <CONFIG_ISR_STACK_SIZE+0xbfe>
     f76:	9308      	str	r3, [sp, #32]
						OUTC(sign);
     f78:	4641      	mov	r1, r8
     f7a:	4630      	mov	r0, r6
     f7c:	9b03      	ldr	r3, [sp, #12]
     f7e:	4798      	blx	r3
     f80:	2800      	cmp	r0, #0
     f82:	f2c0 8237 	blt.w	13f4 <CONFIG_ISR_STACK_SIZE+0xbf4>
						sign = 0;
     f86:	465e      	mov	r6, fp
					pad = '0';
     f88:	2730      	movs	r7, #48	; 0x30
     f8a:	9b08      	ldr	r3, [sp, #32]
						OUTC(sign);
     f8c:	3501      	adds	r5, #1
					pad = '0';
     f8e:	9308      	str	r3, [sp, #32]
     f90:	eb03 0b05 	add.w	fp, r3, r5
     f94:	9b08      	ldr	r3, [sp, #32]
     f96:	ebab 0503 	sub.w	r5, fp, r3
				while (width-- > 0) {
     f9a:	2b00      	cmp	r3, #0
     f9c:	f103 33ff 	add.w	r3, r3, #4294967295	; 0xffffffff
     fa0:	9308      	str	r3, [sp, #32]
     fa2:	f300 8220 	bgt.w	13e6 <CONFIG_ISR_STACK_SIZE+0xbe6>
		if (sign != 0) {
     fa6:	b13e      	cbz	r6, fb8 <CONFIG_ISR_STACK_SIZE+0x7b8>
			OUTC(sign);
     fa8:	4641      	mov	r1, r8
     faa:	4630      	mov	r0, r6
     fac:	9b03      	ldr	r3, [sp, #12]
     fae:	4798      	blx	r3
     fb0:	2800      	cmp	r0, #0
     fb2:	f2c0 821f 	blt.w	13f4 <CONFIG_ISR_STACK_SIZE+0xbf4>
     fb6:	3501      	adds	r5, #1
		if (IS_ENABLED(CONFIG_CBPRINTF_FP_SUPPORT) && conv->pad_fp) {
     fb8:	f89d 2062 	ldrb.w	r2, [sp, #98]	; 0x62
     fbc:	0656      	lsls	r6, r2, #25
     fbe:	f140 827e 	bpl.w	14be <CONFIG_ISR_STACK_SIZE+0xcbe>
			if (conv->specifier_a) {
     fc2:	f99d 2061 	ldrsb.w	r2, [sp, #97]	; 0x61
     fc6:	2a00      	cmp	r2, #0
     fc8:	f2c0 821d 	blt.w	1406 <CONFIG_ISR_STACK_SIZE+0xc06>
     fcc:	eba5 0509 	sub.w	r5, r5, r9
				while (isdigit((int)*cp)) {
     fd0:	f899 0000 	ldrb.w	r0, [r9]
     fd4:	464f      	mov	r7, r9
     fd6:	f1a0 0230 	sub.w	r2, r0, #48	; 0x30
     fda:	2a09      	cmp	r2, #9
     fdc:	eb05 0b09 	add.w	fp, r5, r9
     fe0:	f109 0901 	add.w	r9, r9, #1
     fe4:	f240 823f 	bls.w	1466 <CONFIG_ISR_STACK_SIZE+0xc66>
				if (!conv->pad_postdp) {
     fe8:	f89d 2062 	ldrb.w	r2, [sp, #98]	; 0x62
				pad_len = conv->pad0_value;
     fec:	9e19      	ldr	r6, [sp, #100]	; 0x64
				if (!conv->pad_postdp) {
     fee:	0690      	lsls	r0, r2, #26
     ff0:	d408      	bmi.n	1004 <CONFIG_ISR_STACK_SIZE+0x804>
     ff2:	eb06 090b 	add.w	r9, r6, fp
					while (pad_len-- > 0) {
     ff6:	2e00      	cmp	r6, #0
     ff8:	eba9 0b06 	sub.w	fp, r9, r6
     ffc:	f106 36ff 	add.w	r6, r6, #4294967295	; 0xffffffff
    1000:	f300 8238 	bgt.w	1474 <CONFIG_ISR_STACK_SIZE+0xc74>
				if (*cp == '.') {
    1004:	7838      	ldrb	r0, [r7, #0]
    1006:	282e      	cmp	r0, #46	; 0x2e
    1008:	d10b      	bne.n	1022 <CONFIG_ISR_STACK_SIZE+0x822>
					OUTC(*cp++);
    100a:	4641      	mov	r1, r8
    100c:	9b03      	ldr	r3, [sp, #12]
    100e:	4798      	blx	r3
						OUTC('0');
    1010:	2800      	cmp	r0, #0
    1012:	f2c0 81ef 	blt.w	13f4 <CONFIG_ISR_STACK_SIZE+0xbf4>
					while (pad_len-- > 0) {
    1016:	2e00      	cmp	r6, #0
						OUTC('0');
    1018:	f10b 0b01 	add.w	fp, fp, #1
					while (pad_len-- > 0) {
    101c:	f300 8232 	bgt.w	1484 <CONFIG_ISR_STACK_SIZE+0xc84>
					OUTC(*cp++);
    1020:	3701      	adds	r7, #1
    1022:	ebab 0b07 	sub.w	fp, fp, r7
    1026:	e238      	b.n	149a <CONFIG_ISR_STACK_SIZE+0xc9a>
			if (conv->flag_plus) {
    1028:	0730      	lsls	r0, r6, #28
    102a:	d42b      	bmi.n	1084 <CONFIG_ISR_STACK_SIZE+0x884>
				sign = ' ';
    102c:	f016 0610 	ands.w	r6, r6, #16
    1030:	bf18      	it	ne
    1032:	2620      	movne	r6, #32
			if (value->sint < 0) {
    1034:	e9dd 2316 	ldrd	r2, r3, [sp, #88]	; 0x58
    1038:	2a00      	cmp	r2, #0
    103a:	f173 0100 	sbcs.w	r1, r3, #0
    103e:	da05      	bge.n	104c <CONFIG_ISR_STACK_SIZE+0x84c>
				sign = '-';
    1040:	262d      	movs	r6, #45	; 0x2d
				value->uint = (uint_value_type)-value->sint;
    1042:	4252      	negs	r2, r2
    1044:	eb63 0343 	sbc.w	r3, r3, r3, lsl #1
    1048:	e9cd 2316 	strd	r2, r3, [sp, #88]	; 0x58
			bps = encode_uint(value->uint, conv, buf, bpe);
    104c:	e9dd 0116 	ldrd	r0, r1, [sp, #88]	; 0x58
    1050:	f10d 038d 	add.w	r3, sp, #141	; 0x8d
    1054:	9300      	str	r3, [sp, #0]
    1056:	aa18      	add	r2, sp, #96	; 0x60
    1058:	ab1d      	add	r3, sp, #116	; 0x74
    105a:	f004 fa3e 	bl	54da <encode_uint>
    105e:	4681      	mov	r9, r0
			if (precision >= 0) {
    1060:	2f00      	cmp	r7, #0
    1062:	f10d 038d 	add.w	r3, sp, #141	; 0x8d
    1066:	db0b      	blt.n	1080 <CONFIG_ISR_STACK_SIZE+0x880>
				conv->flag_zero = false;
    1068:	f89d 1060 	ldrb.w	r1, [sp, #96]	; 0x60
				size_t len = bpe - bps;
    106c:	eba3 0209 	sub.w	r2, r3, r9
				conv->flag_zero = false;
    1070:	f36f 1186 	bfc	r1, #6, #1
				if (len < (size_t)precision) {
    1074:	4297      	cmp	r7, r2
				conv->flag_zero = false;
    1076:	f88d 1060 	strb.w	r1, [sp, #96]	; 0x60
				if (len < (size_t)precision) {
    107a:	d901      	bls.n	1080 <CONFIG_ISR_STACK_SIZE+0x880>
					conv->pad0_value = precision - (int)len;
    107c:	1abf      	subs	r7, r7, r2
    107e:	9719      	str	r7, [sp, #100]	; 0x64
		const char *bpe = buf + sizeof(buf);
    1080:	469a      	mov	sl, r3
    1082:	e747      	b.n	f14 <CONFIG_ISR_STACK_SIZE+0x714>
				sign = '+';
    1084:	262b      	movs	r6, #43	; 0x2b
    1086:	e7d5      	b.n	1034 <CONFIG_ISR_STACK_SIZE+0x834>
		switch (conv->specifier) {
    1088:	2600      	movs	r6, #0
    108a:	e7df      	b.n	104c <CONFIG_ISR_STACK_SIZE+0x84c>
			if (value->ptr != NULL) {
    108c:	9816      	ldr	r0, [sp, #88]	; 0x58
    108e:	2800      	cmp	r0, #0
    1090:	f000 819f 	beq.w	13d2 <CONFIG_ISR_STACK_SIZE+0xbd2>
				bps = encode_uint((uintptr_t)value->ptr, conv,
    1094:	f10d 038d 	add.w	r3, sp, #141	; 0x8d
    1098:	9300      	str	r3, [sp, #0]
    109a:	2100      	movs	r1, #0
    109c:	ab1d      	add	r3, sp, #116	; 0x74
    109e:	aa18      	add	r2, sp, #96	; 0x60
    10a0:	f004 fa1b 	bl	54da <encode_uint>
				conv->altform_0c = true;
    10a4:	f8bd 3062 	ldrh.w	r3, [sp, #98]	; 0x62
				bps = encode_uint((uintptr_t)value->ptr, conv,
    10a8:	4681      	mov	r9, r0
				conv->altform_0c = true;
    10aa:	f003 03ef 	and.w	r3, r3, #239	; 0xef
    10ae:	f443 43f0 	orr.w	r3, r3, #30720	; 0x7800
    10b2:	f043 0310 	orr.w	r3, r3, #16
		char sign = 0;
    10b6:	2600      	movs	r6, #0
				conv->altform_0c = true;
    10b8:	f8ad 3062 	strh.w	r3, [sp, #98]	; 0x62
				goto prec_int_pad0;
    10bc:	e7d0      	b.n	1060 <CONFIG_ISR_STACK_SIZE+0x860>
				store_count(conv, value->ptr, count);
    10be:	9b16      	ldr	r3, [sp, #88]	; 0x58
	switch ((enum length_mod_enum)conv->length_mod) {
    10c0:	2907      	cmp	r1, #7
    10c2:	f63f add2 	bhi.w	c6a <CONFIG_ISR_STACK_SIZE+0x46a>
    10c6:	e8df f001 	tbb	[pc, r1]
    10ca:	040d      	.short	0x040d
    10cc:	08080d06 	.word	0x08080d06
    10d0:	0d0d      	.short	0x0d0d
		*(signed char *)dp = (signed char)count;
    10d2:	701d      	strb	r5, [r3, #0]
		break;
    10d4:	e5c9      	b.n	c6a <CONFIG_ISR_STACK_SIZE+0x46a>
		*(short *)dp = (short)count;
    10d6:	801d      	strh	r5, [r3, #0]
		break;
    10d8:	e5c7      	b.n	c6a <CONFIG_ISR_STACK_SIZE+0x46a>
		*(intmax_t *)dp = (intmax_t)count;
    10da:	4628      	mov	r0, r5
    10dc:	17e9      	asrs	r1, r5, #31
    10de:	e9c3 0100 	strd	r0, r1, [r3]
		break;
    10e2:	e5c2      	b.n	c6a <CONFIG_ISR_STACK_SIZE+0x46a>
		*(ptrdiff_t *)dp = (ptrdiff_t)count;
    10e4:	601d      	str	r5, [r3, #0]
		break;
    10e6:	e5c0      	b.n	c6a <CONFIG_ISR_STACK_SIZE+0x46a>
		*sign = '-';
    10e8:	262d      	movs	r6, #45	; 0x2d
    10ea:	e62f      	b.n	d4c <CONFIG_ISR_STACK_SIZE+0x54c>
		*sign = '+';
    10ec:	262b      	movs	r6, #43	; 0x2b
    10ee:	e62d      	b.n	d4c <CONFIG_ISR_STACK_SIZE+0x54c>
	if (exp == BIT_MASK(EXPONENT_BITS)) {
    10f0:	f240 73ff 	movw	r3, #2047	; 0x7ff
    10f4:	459b      	cmp	fp, r3
    10f6:	d12d      	bne.n	1154 <CONFIG_ISR_STACK_SIZE+0x954>
		if (fract == 0) {
    10f8:	e9dd 2306 	ldrd	r2, r3, [sp, #24]
    10fc:	4313      	orrs	r3, r2
    10fe:	f1a9 0941 	sub.w	r9, r9, #65	; 0x41
    1102:	d118      	bne.n	1136 <CONFIG_ISR_STACK_SIZE+0x936>
			if (isupper((int)c)) {
    1104:	f1b9 0f19 	cmp.w	r9, #25
				*buf++ = 'I';
    1108:	bf95      	itete	ls
    110a:	f644 6349 	movwls	r3, #20041	; 0x4e49
				*buf++ = 'i';
    110e:	f646 6369 	movwhi	r3, #28265	; 0x6e69
				*buf++ = 'I';
    1112:	f8ad 3074 	strhls.w	r3, [sp, #116]	; 0x74
				*buf++ = 'i';
    1116:	f8ad 3074 	strhhi.w	r3, [sp, #116]	; 0x74
				*buf++ = 'F';
    111a:	bf94      	ite	ls
    111c:	2346      	movls	r3, #70	; 0x46
				*buf++ = 'f';
    111e:	2366      	movhi	r3, #102	; 0x66
				*buf++ = 'n';
    1120:	f88d 3076 	strb.w	r3, [sp, #118]	; 0x76
		conv->flag_zero = false;
    1124:	f89d 3060 	ldrb.w	r3, [sp, #96]	; 0x60
		*bpe = buf;
    1128:	f10d 0a77 	add.w	sl, sp, #119	; 0x77
		conv->flag_zero = false;
    112c:	f36f 1386 	bfc	r3, #6, #1
    1130:	f88d 3060 	strb.w	r3, [sp, #96]	; 0x60
		return bps;
    1134:	e6fc      	b.n	f30 <CONFIG_ISR_STACK_SIZE+0x730>
			if (isupper((int)c)) {
    1136:	f1b9 0f19 	cmp.w	r9, #25
				*buf++ = 'N';
    113a:	bf95      	itete	ls
    113c:	f244 134e 	movwls	r3, #16718	; 0x414e
				*buf++ = 'n';
    1140:	f246 136e 	movwhi	r3, #24942	; 0x616e
				*buf++ = 'N';
    1144:	f8ad 3074 	strhls.w	r3, [sp, #116]	; 0x74
				*buf++ = 'n';
    1148:	f8ad 3074 	strhhi.w	r3, [sp, #116]	; 0x74
				*buf++ = 'N';
    114c:	bf94      	ite	ls
    114e:	234e      	movls	r3, #78	; 0x4e
				*buf++ = 'n';
    1150:	236e      	movhi	r3, #110	; 0x6e
    1152:	e7e5      	b.n	1120 <CONFIG_ISR_STACK_SIZE+0x920>
	bool is_subnormal = (exp == 0) && (fract != 0);
    1154:	f04f 0c00 	mov.w	ip, #0
    1158:	e60e      	b.n	d78 <CONFIG_ISR_STACK_SIZE+0x578>
				exp--;
    115a:	f10b 3bff 	add.w	fp, fp, #4294967295	; 0xffffffff
			while (((fract <<= 1) & BIT_63) == 0) {
    115e:	1892      	adds	r2, r2, r2
    1160:	415b      	adcs	r3, r3
    1162:	2a00      	cmp	r2, #0
    1164:	f173 0100 	sbcs.w	r1, r3, #0
    1168:	daf7      	bge.n	115a <CONFIG_ISR_STACK_SIZE+0x95a>
    116a:	e9cd 2312 	strd	r2, r3, [sp, #72]	; 0x48
    116e:	e621      	b.n	db4 <CONFIG_ISR_STACK_SIZE+0x5b4>
			fract >>= 1;
    1170:	9b04      	ldr	r3, [sp, #16]
    1172:	9805      	ldr	r0, [sp, #20]
    1174:	085b      	lsrs	r3, r3, #1
    1176:	ea43 73c0 	orr.w	r3, r3, r0, lsl #31
    117a:	0840      	lsrs	r0, r0, #1
		} while ((uint32_t)(fract >> 32) >= (UINT32_MAX / 5U));
    117c:	f1b0 3f33 	cmp.w	r0, #858993459	; 0x33333333
    1180:	46dc      	mov	ip, fp
			fract >>= 1;
    1182:	e9cd 3004 	strd	r3, r0, [sp, #16]
			exp++;
    1186:	f10b 0b01 	add.w	fp, fp, #1
		} while ((uint32_t)(fract >> 32) >= (UINT32_MAX / 5U));
    118a:	d2f1      	bcs.n	1170 <CONFIG_ISR_STACK_SIZE+0x970>
		fract *= 5U;
    118c:	fba3 ab01 	umull	sl, fp, r3, r1
    1190:	4348      	muls	r0, r1
    1192:	e9cd ab04 	strd	sl, fp, [sp, #16]
    1196:	9b05      	ldr	r3, [sp, #20]
		exp++;
    1198:	f10c 0b02 	add.w	fp, ip, #2
		fract *= 5U;
    119c:	18c3      	adds	r3, r0, r3
    119e:	9305      	str	r3, [sp, #20]
		decexp--;
    11a0:	3a01      	subs	r2, #1
    11a2:	2301      	movs	r3, #1
    11a4:	e615      	b.n	dd2 <CONFIG_ISR_STACK_SIZE+0x5d2>
		fract += 2;
    11a6:	3302      	adds	r3, #2
    11a8:	f141 0100 	adc.w	r1, r1, #0
		_ldiv5(&fract);
    11ac:	a812      	add	r0, sp, #72	; 0x48
		fract += 2;
    11ae:	e9cd 3112 	strd	r3, r1, [sp, #72]	; 0x48
    11b2:	920e      	str	r2, [sp, #56]	; 0x38
		_ldiv5(&fract);
    11b4:	f004 f95b 	bl	546e <_ldiv5>
		exp--;
    11b8:	e9dd 0112 	ldrd	r0, r1, [sp, #72]	; 0x48
		decexp++;
    11bc:	9a0e      	ldr	r2, [sp, #56]	; 0x38
		exp--;
    11be:	f10b 3bff 	add.w	fp, fp, #4294967295	; 0xffffffff
		decexp++;
    11c2:	3201      	adds	r2, #1
			fract <<= 1;
    11c4:	1800      	adds	r0, r0, r0
    11c6:	4149      	adcs	r1, r1
		} while (!(fract & BIT_63));
    11c8:	2800      	cmp	r0, #0
    11ca:	f171 0300 	sbcs.w	r3, r1, #0
			exp--;
    11ce:	f10b 3bff 	add.w	fp, fp, #4294967295	; 0xffffffff
		} while (!(fract & BIT_63));
    11d2:	daf7      	bge.n	11c4 <CONFIG_ISR_STACK_SIZE+0x9c4>
    11d4:	e604      	b.n	de0 <CONFIG_ISR_STACK_SIZE+0x5e0>
    11d6:	2200      	movs	r2, #0
    11d8:	4693      	mov	fp, r2
    11da:	e609      	b.n	df0 <CONFIG_ISR_STACK_SIZE+0x5f0>
			c = 'f';
    11dc:	f04f 0966 	mov.w	r9, #102	; 0x66
			precision -= decexp;
    11e0:	1abf      	subs	r7, r7, r2
    11e2:	e62a      	b.n	e3a <CONFIG_ISR_STACK_SIZE+0x63a>
	bool prune_zero = false;
    11e4:	2300      	movs	r3, #0
    11e6:	e631      	b.n	e4c <CONFIG_ISR_STACK_SIZE+0x64c>
		decimals = precision + 1;
    11e8:	1c7b      	adds	r3, r7, #1
	if (decimals > 16) {
    11ea:	2b10      	cmp	r3, #16
    11ec:	bfa8      	it	ge
    11ee:	2310      	movge	r3, #16
    11f0:	469a      	mov	sl, r3
    11f2:	2110      	movs	r1, #16
	uint64_t round = BIT64(59); /* 0.5 */
    11f4:	2000      	movs	r0, #0
    11f6:	9111      	str	r1, [sp, #68]	; 0x44
    11f8:	f04f 6100 	mov.w	r1, #134217728	; 0x8000000
    11fc:	e9cd 0114 	strd	r0, r1, [sp, #80]	; 0x50
	while (decimals--) {
    1200:	e9dd 1014 	ldrd	r1, r0, [sp, #80]	; 0x50
    1204:	f10a 3aff 	add.w	sl, sl, #4294967295	; 0xffffffff
    1208:	f1ba 3fff 	cmp.w	sl, #4294967295	; 0xffffffff
    120c:	d11f      	bne.n	124e <CONFIG_ISR_STACK_SIZE+0xa4e>
	fract += round;
    120e:	9b12      	ldr	r3, [sp, #72]	; 0x48
    1210:	18cb      	adds	r3, r1, r3
    1212:	930a      	str	r3, [sp, #40]	; 0x28
    1214:	9b13      	ldr	r3, [sp, #76]	; 0x4c
	if (fract >= BIT64(60)) {
    1216:	f06f 4170 	mvn.w	r1, #4026531840	; 0xf0000000
	fract += round;
    121a:	eb40 0303 	adc.w	r3, r0, r3
	if (fract >= BIT64(60)) {
    121e:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
	fract += round;
    1222:	930b      	str	r3, [sp, #44]	; 0x2c
	if (fract >= BIT64(60)) {
    1224:	e9dd ab0a 	ldrd	sl, fp, [sp, #40]	; 0x28
    1228:	4559      	cmp	r1, fp
    122a:	bf08      	it	eq
    122c:	4550      	cmpeq	r0, sl
    122e:	d31a      	bcc.n	1266 <CONFIG_ISR_STACK_SIZE+0xa66>
	fract += round;
    1230:	4650      	mov	r0, sl
    1232:	4659      	mov	r1, fp
    1234:	e9cd 0112 	strd	r0, r1, [sp, #72]	; 0x48
	if (c == 'f') {
    1238:	f1b9 0f66 	cmp.w	r9, #102	; 0x66
    123c:	d153      	bne.n	12e6 <CONFIG_ISR_STACK_SIZE+0xae6>
		if (decexp > 0) {
    123e:	2a00      	cmp	r2, #0
    1240:	dc20      	bgt.n	1284 <CONFIG_ISR_STACK_SIZE+0xa84>
			*buf++ = '0';
    1242:	2330      	movs	r3, #48	; 0x30
    1244:	f10d 0a75 	add.w	sl, sp, #117	; 0x75
    1248:	f88d 3074 	strb.w	r3, [sp, #116]	; 0x74
    124c:	e02b      	b.n	12a6 <CONFIG_ISR_STACK_SIZE+0xaa6>
	*v >>= 1;
    124e:	0849      	lsrs	r1, r1, #1
    1250:	ea41 71c0 	orr.w	r1, r1, r0, lsl #31
    1254:	0840      	lsrs	r0, r0, #1
    1256:	e9cd 1014 	strd	r1, r0, [sp, #80]	; 0x50
	_ldiv5(v);
    125a:	a814      	add	r0, sp, #80	; 0x50
    125c:	920f      	str	r2, [sp, #60]	; 0x3c
    125e:	f004 f906 	bl	546e <_ldiv5>
    1262:	9a0f      	ldr	r2, [sp, #60]	; 0x3c
}
    1264:	e7cc      	b.n	1200 <CONFIG_ISR_STACK_SIZE+0xa00>
	*v >>= 1;
    1266:	9b0a      	ldr	r3, [sp, #40]	; 0x28
    1268:	920f      	str	r2, [sp, #60]	; 0x3c
    126a:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
    126c:	085b      	lsrs	r3, r3, #1
    126e:	ea43 73c2 	orr.w	r3, r3, r2, lsl #31
    1272:	0851      	lsrs	r1, r2, #1
	_ldiv5(v);
    1274:	a812      	add	r0, sp, #72	; 0x48
	*v >>= 1;
    1276:	e9cd 3112 	strd	r3, r1, [sp, #72]	; 0x48
	_ldiv5(v);
    127a:	f004 f8f8 	bl	546e <_ldiv5>
		decexp++;
    127e:	9a0f      	ldr	r2, [sp, #60]	; 0x3c
    1280:	3201      	adds	r2, #1
    1282:	e7d9      	b.n	1238 <CONFIG_ISR_STACK_SIZE+0xa38>
	char *buf = bps;
    1284:	f10d 0a74 	add.w	sl, sp, #116	; 0x74
			while (decexp > 0 && digit_count > 0) {
    1288:	9911      	ldr	r1, [sp, #68]	; 0x44
    128a:	2900      	cmp	r1, #0
    128c:	dd09      	ble.n	12a2 <CONFIG_ISR_STACK_SIZE+0xaa2>
				*buf++ = _get_digit(&fract, &digit_count);
    128e:	a911      	add	r1, sp, #68	; 0x44
    1290:	a812      	add	r0, sp, #72	; 0x48
    1292:	920f      	str	r2, [sp, #60]	; 0x3c
    1294:	f004 f90a 	bl	54ac <_get_digit>
			while (decexp > 0 && digit_count > 0) {
    1298:	9a0f      	ldr	r2, [sp, #60]	; 0x3c
				*buf++ = _get_digit(&fract, &digit_count);
    129a:	f80a 0b01 	strb.w	r0, [sl], #1
			while (decexp > 0 && digit_count > 0) {
    129e:	3a01      	subs	r2, #1
    12a0:	d1f2      	bne.n	1288 <CONFIG_ISR_STACK_SIZE+0xa88>
			conv->pad0_value = decexp;
    12a2:	9219      	str	r2, [sp, #100]	; 0x64
			decexp = 0;
    12a4:	2200      	movs	r2, #0
		if (conv->flag_hash || (precision > 0)) {
    12a6:	f89d 1060 	ldrb.w	r1, [sp, #96]	; 0x60
    12aa:	0688      	lsls	r0, r1, #26
    12ac:	d401      	bmi.n	12b2 <CONFIG_ISR_STACK_SIZE+0xab2>
    12ae:	2f00      	cmp	r7, #0
    12b0:	dd3f      	ble.n	1332 <CONFIG_ISR_STACK_SIZE+0xb32>
			*buf++ = '.';
    12b2:	4653      	mov	r3, sl
    12b4:	212e      	movs	r1, #46	; 0x2e
    12b6:	f803 1b01 	strb.w	r1, [r3], #1
		if (decexp < 0 && precision > 0) {
    12ba:	b192      	cbz	r2, 12e2 <CONFIG_ISR_STACK_SIZE+0xae2>
    12bc:	2f00      	cmp	r7, #0
    12be:	dd76      	ble.n	13ae <CONFIG_ISR_STACK_SIZE+0xbae>
			conv->pad0_value = -decexp;
    12c0:	4251      	negs	r1, r2
    12c2:	42b9      	cmp	r1, r7
    12c4:	bfa8      	it	ge
    12c6:	4639      	movge	r1, r7
			conv->pad_postdp = (conv->pad0_value > 0);
    12c8:	2900      	cmp	r1, #0
			conv->pad0_value = -decexp;
    12ca:	9119      	str	r1, [sp, #100]	; 0x64
			precision -= conv->pad0_value;
    12cc:	eba7 0701 	sub.w	r7, r7, r1
			conv->pad_postdp = (conv->pad0_value > 0);
    12d0:	bfd4      	ite	le
    12d2:	2100      	movle	r1, #0
    12d4:	2101      	movgt	r1, #1
    12d6:	f89d 0062 	ldrb.w	r0, [sp, #98]	; 0x62
    12da:	f361 1045 	bfi	r0, r1, #5, #1
    12de:	f88d 0062 	strb.w	r0, [sp, #98]	; 0x62
			*buf++ = '.';
    12e2:	469a      	mov	sl, r3
    12e4:	e020      	b.n	1328 <CONFIG_ISR_STACK_SIZE+0xb28>
		*buf = _get_digit(&fract, &digit_count);
    12e6:	a911      	add	r1, sp, #68	; 0x44
    12e8:	a812      	add	r0, sp, #72	; 0x48
    12ea:	920f      	str	r2, [sp, #60]	; 0x3c
    12ec:	f004 f8de 	bl	54ac <_get_digit>
		if (*buf++ != '0') {
    12f0:	9a0f      	ldr	r2, [sp, #60]	; 0x3c
		if (conv->flag_hash || (precision > 0)) {
    12f2:	f89d 3060 	ldrb.w	r3, [sp, #96]	; 0x60
		if (*buf++ != '0') {
    12f6:	2830      	cmp	r0, #48	; 0x30
			decexp--;
    12f8:	bf18      	it	ne
    12fa:	f102 32ff 	addne.w	r2, r2, #4294967295	; 0xffffffff
		if (conv->flag_hash || (precision > 0)) {
    12fe:	0699      	lsls	r1, r3, #26
		*buf = _get_digit(&fract, &digit_count);
    1300:	f88d 0074 	strb.w	r0, [sp, #116]	; 0x74
		if (conv->flag_hash || (precision > 0)) {
    1304:	d401      	bmi.n	130a <CONFIG_ISR_STACK_SIZE+0xb0a>
    1306:	2f00      	cmp	r7, #0
    1308:	dd53      	ble.n	13b2 <CONFIG_ISR_STACK_SIZE+0xbb2>
			*buf++ = '.';
    130a:	232e      	movs	r3, #46	; 0x2e
    130c:	f88d 3075 	strb.w	r3, [sp, #117]	; 0x75
    1310:	f10d 0376 	add.w	r3, sp, #118	; 0x76
    1314:	e7e5      	b.n	12e2 <CONFIG_ISR_STACK_SIZE+0xae2>
		*buf++ = _get_digit(&fract, &digit_count);
    1316:	a911      	add	r1, sp, #68	; 0x44
    1318:	a812      	add	r0, sp, #72	; 0x48
    131a:	920f      	str	r2, [sp, #60]	; 0x3c
    131c:	f004 f8c6 	bl	54ac <_get_digit>
    1320:	9a0f      	ldr	r2, [sp, #60]	; 0x3c
    1322:	f80a 0b01 	strb.w	r0, [sl], #1
		precision--;
    1326:	3f01      	subs	r7, #1
	while (precision > 0 && digit_count > 0) {
    1328:	2f00      	cmp	r7, #0
    132a:	dd02      	ble.n	1332 <CONFIG_ISR_STACK_SIZE+0xb32>
    132c:	9911      	ldr	r1, [sp, #68]	; 0x44
    132e:	2900      	cmp	r1, #0
    1330:	dcf1      	bgt.n	1316 <CONFIG_ISR_STACK_SIZE+0xb16>
	if (prune_zero) {
    1332:	9b0e      	ldr	r3, [sp, #56]	; 0x38
    1334:	2b00      	cmp	r3, #0
    1336:	d13f      	bne.n	13b8 <CONFIG_ISR_STACK_SIZE+0xbb8>
	conv->pad0_pre_exp = precision;
    1338:	971a      	str	r7, [sp, #104]	; 0x68
	if ((c == 'e') || (c == 'E')) {
    133a:	f009 01df 	and.w	r1, r9, #223	; 0xdf
    133e:	2945      	cmp	r1, #69	; 0x45
    1340:	d123      	bne.n	138a <CONFIG_ISR_STACK_SIZE+0xb8a>
		if (decexp < 0) {
    1342:	2a00      	cmp	r2, #0
			*buf++ = '-';
    1344:	bfb4      	ite	lt
    1346:	212d      	movlt	r1, #45	; 0x2d
			*buf++ = '+';
    1348:	212b      	movge	r1, #43	; 0x2b
		*buf++ = c;
    134a:	4650      	mov	r0, sl
			decexp = -decexp;
    134c:	bfb8      	it	lt
    134e:	4252      	neglt	r2, r2
		if (decexp >= 100) {
    1350:	2a63      	cmp	r2, #99	; 0x63
		*buf++ = c;
    1352:	f800 9b02 	strb.w	r9, [r0], #2
			*buf++ = '-';
    1356:	f88a 1001 	strb.w	r1, [sl, #1]
		if (decexp >= 100) {
    135a:	dd0a      	ble.n	1372 <CONFIG_ISR_STACK_SIZE+0xb72>
			*buf++ = (decexp / 100) + '0';
    135c:	2764      	movs	r7, #100	; 0x64
    135e:	fb92 f1f7 	sdiv	r1, r2, r7
			decexp %= 100;
    1362:	fb07 2211 	mls	r2, r7, r1, r2
			*buf++ = (decexp / 100) + '0';
    1366:	f101 0c30 	add.w	ip, r1, #48	; 0x30
    136a:	f10a 0003 	add.w	r0, sl, #3
    136e:	f88a c002 	strb.w	ip, [sl, #2]
		*buf++ = (decexp / 10) + '0';
    1372:	270a      	movs	r7, #10
    1374:	fb92 f1f7 	sdiv	r1, r2, r7
    1378:	4682      	mov	sl, r0
		*buf++ = (decexp % 10) + '0';
    137a:	fb07 2211 	mls	r2, r7, r1, r2
		*buf++ = (decexp / 10) + '0';
    137e:	f101 0c30 	add.w	ip, r1, #48	; 0x30
		*buf++ = (decexp % 10) + '0';
    1382:	3230      	adds	r2, #48	; 0x30
		*buf++ = (decexp / 10) + '0';
    1384:	f80a cb02 	strb.w	ip, [sl], #2
		*buf++ = (decexp % 10) + '0';
    1388:	7042      	strb	r2, [r0, #1]
		|| (conv->pad0_pre_exp > 0);
    138a:	9a19      	ldr	r2, [sp, #100]	; 0x64
    138c:	2a00      	cmp	r2, #0
    138e:	dc1e      	bgt.n	13ce <CONFIG_ISR_STACK_SIZE+0xbce>
    1390:	9a1a      	ldr	r2, [sp, #104]	; 0x68
    1392:	2a00      	cmp	r2, #0
    1394:	bfd4      	ite	le
    1396:	2200      	movle	r2, #0
    1398:	2201      	movgt	r2, #1
	conv->pad_fp = (conv->pad0_value > 0)
    139a:	f89d 1062 	ldrb.w	r1, [sp, #98]	; 0x62
    139e:	f362 1186 	bfi	r1, r2, #6, #1
	*buf = 0;
    13a2:	2200      	movs	r2, #0
	conv->pad_fp = (conv->pad0_value > 0)
    13a4:	f88d 1062 	strb.w	r1, [sp, #98]	; 0x62
	*buf = 0;
    13a8:	f88a 2000 	strb.w	r2, [sl]
	return bps;
    13ac:	e5c0      	b.n	f30 <CONFIG_ISR_STACK_SIZE+0x730>
			*buf++ = '.';
    13ae:	469a      	mov	sl, r3
    13b0:	e7bf      	b.n	1332 <CONFIG_ISR_STACK_SIZE+0xb32>
		if (*buf++ != '0') {
    13b2:	f10d 0a75 	add.w	sl, sp, #117	; 0x75
    13b6:	e7bc      	b.n	1332 <CONFIG_ISR_STACK_SIZE+0xb32>
		conv->pad0_pre_exp = 0;
    13b8:	2100      	movs	r1, #0
    13ba:	911a      	str	r1, [sp, #104]	; 0x68
		while (*--buf == '0') {
    13bc:	4650      	mov	r0, sl
    13be:	f81a 1d01 	ldrb.w	r1, [sl, #-1]!
    13c2:	2930      	cmp	r1, #48	; 0x30
    13c4:	d0fa      	beq.n	13bc <CONFIG_ISR_STACK_SIZE+0xbbc>
		if (*buf != '.') {
    13c6:	292e      	cmp	r1, #46	; 0x2e
    13c8:	bf18      	it	ne
    13ca:	4682      	movne	sl, r0
    13cc:	e7b5      	b.n	133a <CONFIG_ISR_STACK_SIZE+0xb3a>
		|| (conv->pad0_pre_exp > 0);
    13ce:	2201      	movs	r2, #1
    13d0:	e7e3      	b.n	139a <CONFIG_ISR_STACK_SIZE+0xb9a>
			bpe = bps + 5;
    13d2:	f8df a13c 	ldr.w	sl, [pc, #316]	; 1510 <CONFIG_ISR_STACK_SIZE+0xd10>
		char sign = 0;
    13d6:	4606      	mov	r6, r0
			bps = "(nil)";
    13d8:	f1aa 0905 	sub.w	r9, sl, #5
    13dc:	e5aa      	b.n	f34 <CONFIG_ISR_STACK_SIZE+0x734>
		} else if (conv->altform_0) {
    13de:	0707      	lsls	r7, r0, #28
			nj_len += 1U;
    13e0:	bf48      	it	mi
    13e2:	3201      	addmi	r2, #1
    13e4:	e5b0      	b.n	f48 <CONFIG_ISR_STACK_SIZE+0x748>
					OUTC(pad);
    13e6:	4641      	mov	r1, r8
    13e8:	4638      	mov	r0, r7
    13ea:	9b03      	ldr	r3, [sp, #12]
    13ec:	4798      	blx	r3
    13ee:	2800      	cmp	r0, #0
    13f0:	f6bf add0 	bge.w	f94 <CONFIG_ISR_STACK_SIZE+0x794>
#undef OUTS
#undef OUTC
}
    13f4:	b025      	add	sp, #148	; 0x94
    13f6:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
				char pad = ' ';
    13fa:	2720      	movs	r7, #32
    13fc:	e5c7      	b.n	f8e <CONFIG_ISR_STACK_SIZE+0x78e>
					pad = '0';
    13fe:	2730      	movs	r7, #48	; 0x30
    1400:	e5c5      	b.n	f8e <CONFIG_ISR_STACK_SIZE+0x78e>
			width -= (int)nj_len;
    1402:	9308      	str	r3, [sp, #32]
    1404:	e5cf      	b.n	fa6 <CONFIG_ISR_STACK_SIZE+0x7a6>
    1406:	eba5 0b09 	sub.w	fp, r5, r9
    140a:	464e      	mov	r6, r9
    140c:	eb0b 0509 	add.w	r5, fp, r9
				while (*cp != 'p') {
    1410:	f819 0b01 	ldrb.w	r0, [r9], #1
    1414:	2870      	cmp	r0, #112	; 0x70
    1416:	d120      	bne.n	145a <CONFIG_ISR_STACK_SIZE+0xc5a>
			while (pad_len-- > 0) {
    1418:	9a1a      	ldr	r2, [sp, #104]	; 0x68
    141a:	eb02 0905 	add.w	r9, r2, r5
    141e:	eba9 0205 	sub.w	r2, r9, r5
    1422:	2a00      	cmp	r2, #0
    1424:	dc43      	bgt.n	14ae <CONFIG_ISR_STACK_SIZE+0xcae>
			OUTS(cp, bpe);
    1426:	4653      	mov	r3, sl
    1428:	4632      	mov	r2, r6
			OUTS(bps, bpe);
    142a:	4641      	mov	r1, r8
    142c:	9803      	ldr	r0, [sp, #12]
    142e:	f004 f89f 	bl	5570 <outs>
    1432:	2800      	cmp	r0, #0
    1434:	dbde      	blt.n	13f4 <CONFIG_ISR_STACK_SIZE+0xbf4>
    1436:	9b08      	ldr	r3, [sp, #32]
    1438:	4428      	add	r0, r5
    143a:	4403      	add	r3, r0
			while (pad_len-- > 0) {
    143c:	4605      	mov	r5, r0
    143e:	469a      	mov	sl, r3
		while (width > 0) {
    1440:	ebaa 0305 	sub.w	r3, sl, r5
    1444:	2b00      	cmp	r3, #0
    1446:	f77f ac10 	ble.w	c6a <CONFIG_ISR_STACK_SIZE+0x46a>
			OUTC(' ');
    144a:	4641      	mov	r1, r8
    144c:	2020      	movs	r0, #32
    144e:	9b03      	ldr	r3, [sp, #12]
    1450:	4798      	blx	r3
    1452:	2800      	cmp	r0, #0
    1454:	dbce      	blt.n	13f4 <CONFIG_ISR_STACK_SIZE+0xbf4>
    1456:	3501      	adds	r5, #1
			--width;
    1458:	e7f2      	b.n	1440 <CONFIG_ISR_STACK_SIZE+0xc40>
					OUTC(*cp++);
    145a:	4641      	mov	r1, r8
    145c:	9b03      	ldr	r3, [sp, #12]
    145e:	4798      	blx	r3
    1460:	2800      	cmp	r0, #0
    1462:	dad2      	bge.n	140a <CONFIG_ISR_STACK_SIZE+0xc0a>
    1464:	e7c6      	b.n	13f4 <CONFIG_ISR_STACK_SIZE+0xbf4>
					OUTC(*cp++);
    1466:	4641      	mov	r1, r8
    1468:	9b03      	ldr	r3, [sp, #12]
    146a:	4798      	blx	r3
    146c:	2800      	cmp	r0, #0
    146e:	f6bf adaf 	bge.w	fd0 <CONFIG_ISR_STACK_SIZE+0x7d0>
    1472:	e7bf      	b.n	13f4 <CONFIG_ISR_STACK_SIZE+0xbf4>
						OUTC('0');
    1474:	4641      	mov	r1, r8
    1476:	2030      	movs	r0, #48	; 0x30
    1478:	9b03      	ldr	r3, [sp, #12]
    147a:	4798      	blx	r3
    147c:	2800      	cmp	r0, #0
    147e:	f6bf adba 	bge.w	ff6 <CONFIG_ISR_STACK_SIZE+0x7f6>
    1482:	e7b7      	b.n	13f4 <CONFIG_ISR_STACK_SIZE+0xbf4>
						OUTC('0');
    1484:	4641      	mov	r1, r8
    1486:	2030      	movs	r0, #48	; 0x30
    1488:	9b03      	ldr	r3, [sp, #12]
    148a:	4798      	blx	r3
    148c:	3e01      	subs	r6, #1
    148e:	e5bf      	b.n	1010 <CONFIG_ISR_STACK_SIZE+0x810>
					OUTC(*cp++);
    1490:	4641      	mov	r1, r8
    1492:	9b03      	ldr	r3, [sp, #12]
    1494:	4798      	blx	r3
    1496:	2800      	cmp	r0, #0
    1498:	dbac      	blt.n	13f4 <CONFIG_ISR_STACK_SIZE+0xbf4>
    149a:	463e      	mov	r6, r7
    149c:	eb0b 0507 	add.w	r5, fp, r7
				while (isdigit((int)*cp)) {
    14a0:	f817 0b01 	ldrb.w	r0, [r7], #1
    14a4:	f1a0 0230 	sub.w	r2, r0, #48	; 0x30
    14a8:	2a09      	cmp	r2, #9
    14aa:	d9f1      	bls.n	1490 <CONFIG_ISR_STACK_SIZE+0xc90>
    14ac:	e7b4      	b.n	1418 <CONFIG_ISR_STACK_SIZE+0xc18>
				OUTC('0');
    14ae:	4641      	mov	r1, r8
    14b0:	2030      	movs	r0, #48	; 0x30
    14b2:	9b03      	ldr	r3, [sp, #12]
    14b4:	4798      	blx	r3
    14b6:	2800      	cmp	r0, #0
    14b8:	db9c      	blt.n	13f4 <CONFIG_ISR_STACK_SIZE+0xbf4>
    14ba:	3501      	adds	r5, #1
    14bc:	e7af      	b.n	141e <CONFIG_ISR_STACK_SIZE+0xc1e>
			if (conv->altform_0c | conv->altform_0) {
    14be:	06d1      	lsls	r1, r2, #27
    14c0:	d401      	bmi.n	14c6 <CONFIG_ISR_STACK_SIZE+0xcc6>
    14c2:	0712      	lsls	r2, r2, #28
    14c4:	d506      	bpl.n	14d4 <CONFIG_ISR_STACK_SIZE+0xcd4>
				OUTC('0');
    14c6:	4641      	mov	r1, r8
    14c8:	2030      	movs	r0, #48	; 0x30
    14ca:	9b03      	ldr	r3, [sp, #12]
    14cc:	4798      	blx	r3
    14ce:	2800      	cmp	r0, #0
    14d0:	db90      	blt.n	13f4 <CONFIG_ISR_STACK_SIZE+0xbf4>
    14d2:	3501      	adds	r5, #1
			if (conv->altform_0c) {
    14d4:	f89d 2062 	ldrb.w	r2, [sp, #98]	; 0x62
    14d8:	06d3      	lsls	r3, r2, #27
    14da:	d507      	bpl.n	14ec <CONFIG_ISR_STACK_SIZE+0xcec>
				OUTC(conv->specifier);
    14dc:	4641      	mov	r1, r8
    14de:	f89d 0063 	ldrb.w	r0, [sp, #99]	; 0x63
    14e2:	9b03      	ldr	r3, [sp, #12]
    14e4:	4798      	blx	r3
    14e6:	2800      	cmp	r0, #0
    14e8:	db84      	blt.n	13f4 <CONFIG_ISR_STACK_SIZE+0xbf4>
    14ea:	3501      	adds	r5, #1
			while (pad_len-- > 0) {
    14ec:	9e19      	ldr	r6, [sp, #100]	; 0x64
    14ee:	442e      	add	r6, r5
    14f0:	1b72      	subs	r2, r6, r5
    14f2:	2a00      	cmp	r2, #0
    14f4:	dc02      	bgt.n	14fc <CONFIG_ISR_STACK_SIZE+0xcfc>
			OUTS(bps, bpe);
    14f6:	4653      	mov	r3, sl
    14f8:	464a      	mov	r2, r9
    14fa:	e796      	b.n	142a <CONFIG_ISR_STACK_SIZE+0xc2a>
				OUTC('0');
    14fc:	4641      	mov	r1, r8
    14fe:	2030      	movs	r0, #48	; 0x30
    1500:	9b03      	ldr	r3, [sp, #12]
    1502:	4798      	blx	r3
    1504:	2800      	cmp	r0, #0
    1506:	f6ff af75 	blt.w	13f4 <CONFIG_ISR_STACK_SIZE+0xbf4>
    150a:	3501      	adds	r5, #1
    150c:	e7f0      	b.n	14f0 <CONFIG_ISR_STACK_SIZE+0xcf0>
    150e:	bf00      	nop
    1510:	0000620e 	.word	0x0000620e

00001514 <nordicsemi_nrf91_init>:
    1514:	f04f 0220 	mov.w	r2, #32
    1518:	f3ef 8311 	mrs	r3, BASEPRI
    151c:	f382 8811 	msr	BASEPRI, r2
    1520:	f3bf 8f6f 	isb	sy

	key = irq_lock();

#ifdef CONFIG_NRF_ENABLE_ICACHE
	/* Enable the instruction cache */
	NRF_NVMC->ICACHECNF = NVMC_ICACHECNF_CACHEEN_Msk;
    1524:	2101      	movs	r1, #1
    1526:	4a04      	ldr	r2, [pc, #16]	; (1538 <nordicsemi_nrf91_init+0x24>)
    1528:	f8c2 1540 	str.w	r1, [r2, #1344]	; 0x540
	__asm__ volatile(
    152c:	f383 8811 	msr	BASEPRI, r3
    1530:	f3bf 8f6f 	isb	sy
	NMI_INIT();

	irq_unlock(key);

	return 0;
}
    1534:	2000      	movs	r0, #0
    1536:	4770      	bx	lr
    1538:	50039000 	.word	0x50039000

0000153c <arch_busy_wait>:

#else // NRFX_CHECK(NRFX_DELAY_DWT_BASED)

NRF_STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us)
{
    if (time_us == 0)
    153c:	b120      	cbz	r0, 1548 <arch_busy_wait+0xc>
    };

    typedef void (* delay_func_t)(uint32_t);
    const delay_func_t delay_cycles =
        // Set LSB to 1 to execute the code in the Thumb mode.
        (delay_func_t)((((uint32_t)delay_machine_code) | 1));
    153e:	4b03      	ldr	r3, [pc, #12]	; (154c <arch_busy_wait+0x10>)
    uint32_t cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ;
    delay_cycles(cycles);
    1540:	0180      	lsls	r0, r0, #6
    1542:	f043 0301 	orr.w	r3, r3, #1
    1546:	4718      	bx	r3

void arch_busy_wait(uint32_t time_us)
{
	nrfx_coredep_delay_us(time_us);
}
    1548:	4770      	bx	lr
    154a:	bf00      	nop
    154c:	00005f50 	.word	0x00005f50

00001550 <sys_reboot>:

extern void sys_arch_reboot(int type);
extern void sys_clock_disable(void);

void sys_reboot(int type)
{
    1550:	b507      	push	{r0, r1, r2, lr}
    1552:	9001      	str	r0, [sp, #4]
	__asm__ volatile(
    1554:	f04f 0220 	mov.w	r2, #32
    1558:	f3ef 8311 	mrs	r3, BASEPRI
    155c:	f382 8811 	msr	BASEPRI, r2
    1560:	f3bf 8f6f 	isb	sy
	(void)irq_lock();
#ifdef CONFIG_SYS_CLOCK_EXISTS
	sys_clock_disable();
    1564:	f004 f8b7 	bl	56d6 <sys_clock_disable>
#endif

	sys_arch_reboot(type);
    1568:	9801      	ldr	r0, [sp, #4]
    156a:	f001 f827 	bl	25bc <sys_arch_reboot>

	/* should never get here */
	printk("Failed to reboot: spinning endlessly...\n");
    156e:	4803      	ldr	r0, [pc, #12]	; (157c <sys_reboot+0x2c>)
    1570:	f003 fdde 	bl	5130 <printk>
 *
 * @return N/A
 */
static inline void k_cpu_idle(void)
{
	arch_cpu_idle();
    1574:	f000 fe76 	bl	2264 <arch_cpu_idle>
    1578:	e7fc      	b.n	1574 <sys_reboot+0x24>
    157a:	bf00      	nop
    157c:	0000620f 	.word	0x0000620f

00001580 <onoff_stop>:
}

static clock_control_subsys_t get_subsys(struct onoff_manager *mgr)
{
	struct nrf_clock_control_data *data = CLOCK_DEVICE->data;
	size_t offset = (size_t)(mgr - data->mgr);
    1580:	4a0e      	ldr	r2, [pc, #56]	; (15bc <onoff_stop+0x3c>)
	return (clock_control_subsys_t)offset;
}

static void onoff_stop(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    1582:	b570      	push	{r4, r5, r6, lr}
	size_t offset = (size_t)(mgr - data->mgr);
    1584:	1a84      	subs	r4, r0, r2
{
    1586:	4605      	mov	r5, r0
	err = set_off_state(&subdata->flags, ctx);
    1588:	200c      	movs	r0, #12
{
    158a:	460e      	mov	r6, r1
	err = set_off_state(&subdata->flags, ctx);
    158c:	2140      	movs	r1, #64	; 0x40
	size_t offset = (size_t)(mgr - data->mgr);
    158e:	10a3      	asrs	r3, r4, #2
    1590:	4c0b      	ldr	r4, [pc, #44]	; (15c0 <onoff_stop+0x40>)
    1592:	435c      	muls	r4, r3
    1594:	b2e4      	uxtb	r4, r4
	err = set_off_state(&subdata->flags, ctx);
    1596:	fb00 2004 	mla	r0, r0, r4, r2
    159a:	4408      	add	r0, r1
    159c:	f004 f80d 	bl	55ba <set_off_state>
	if (err < 0) {
    15a0:	1e01      	subs	r1, r0, #0
    15a2:	db05      	blt.n	15b0 <onoff_stop+0x30>
	get_sub_config(dev, type)->stop();
    15a4:	4b07      	ldr	r3, [pc, #28]	; (15c4 <onoff_stop+0x44>)
    15a6:	eb03 04c4 	add.w	r4, r3, r4, lsl #3
    15aa:	6863      	ldr	r3, [r4, #4]
    15ac:	4798      	blx	r3
	return 0;
    15ae:	2100      	movs	r1, #0
	int res;

	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
	notify(mgr, res);
    15b0:	4628      	mov	r0, r5
    15b2:	4633      	mov	r3, r6
}
    15b4:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	notify(mgr, res);
    15b8:	4718      	bx	r3
    15ba:	bf00      	nop
    15bc:	20000240 	.word	0x20000240
    15c0:	b6db6db7 	.word	0xb6db6db7
    15c4:	00005f6c 	.word	0x00005f6c

000015c8 <onoff_start>:
	notify(mgr, 0);
}

static void onoff_start(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    15c8:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	err = set_starting_state(&subdata->flags, ctx);
    15cc:	250c      	movs	r5, #12
	size_t offset = (size_t)(mgr - data->mgr);
    15ce:	4e10      	ldr	r6, [pc, #64]	; (1610 <onoff_start+0x48>)
{
    15d0:	4680      	mov	r8, r0
	size_t offset = (size_t)(mgr - data->mgr);
    15d2:	1b84      	subs	r4, r0, r6
    15d4:	10a3      	asrs	r3, r4, #2
    15d6:	4c0f      	ldr	r4, [pc, #60]	; (1614 <onoff_start+0x4c>)
{
    15d8:	460f      	mov	r7, r1
	size_t offset = (size_t)(mgr - data->mgr);
    15da:	435c      	muls	r4, r3
    15dc:	b2e4      	uxtb	r4, r4
	err = set_starting_state(&subdata->flags, ctx);
    15de:	4365      	muls	r5, r4
    15e0:	f105 0040 	add.w	r0, r5, #64	; 0x40
    15e4:	2140      	movs	r1, #64	; 0x40
    15e6:	4430      	add	r0, r6
    15e8:	f004 f800 	bl	55ec <set_starting_state>
	if (err < 0) {
    15ec:	1e01      	subs	r1, r0, #0
    15ee:	db09      	blt.n	1604 <onoff_start+0x3c>
	subdata->cb = cb;
    15f0:	4a09      	ldr	r2, [pc, #36]	; (1618 <onoff_start+0x50>)
    15f2:	1973      	adds	r3, r6, r5
	subdata->user_data = user_data;
    15f4:	e9c3 270e 	strd	r2, r7, [r3, #56]	; 0x38
	 get_sub_config(dev, type)->start();
    15f8:	4b08      	ldr	r3, [pc, #32]	; (161c <onoff_start+0x54>)
    15fa:	f853 3034 	ldr.w	r3, [r3, r4, lsl #3]
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
			  onoff_started_callback, notify, CTX_ONOFF);
	if (err < 0) {
		notify(mgr, err);
	}
}
    15fe:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
	 get_sub_config(dev, type)->start();
    1602:	4718      	bx	r3
		notify(mgr, err);
    1604:	4640      	mov	r0, r8
    1606:	463b      	mov	r3, r7
}
    1608:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
		notify(mgr, err);
    160c:	4718      	bx	r3
    160e:	bf00      	nop
    1610:	20000240 	.word	0x20000240
    1614:	b6db6db7 	.word	0xb6db6db7
    1618:	0000564f 	.word	0x0000564f
    161c:	00005f6c 	.word	0x00005f6c

00001620 <clk_init>:
		break;
	}
}

static int clk_init(const struct device *dev)
{
    1620:	b570      	push	{r4, r5, r6, lr}
	static const struct onoff_transitions transitions = {
		.start = onoff_start,
		.stop = onoff_stop
	};

	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    1622:	2200      	movs	r2, #0
    1624:	2101      	movs	r1, #1
{
    1626:	4604      	mov	r4, r0
	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    1628:	2005      	movs	r0, #5
    162a:	f000 fdc5 	bl	21b8 <z_arm_irq_priority_set>
		    nrfx_isr, nrfx_power_clock_irq_handler, 0);
	irq_enable(DT_INST_IRQN(0));
    162e:	2005      	movs	r0, #5
    1630:	f000 fda4 	bl	217c <arch_irq_enable>

	nrfx_err = nrfx_clock_init(clock_event_handler);
    1634:	480f      	ldr	r0, [pc, #60]	; (1674 <clk_init+0x54>)
    1636:	f001 fccb 	bl	2fd0 <nrfx_clock_init>
	if (nrfx_err != NRFX_SUCCESS) {
    163a:	4b0f      	ldr	r3, [pc, #60]	; (1678 <clk_init+0x58>)
    163c:	4298      	cmp	r0, r3
    163e:	d115      	bne.n	166c <clk_init+0x4c>
		struct nrf_clock_control_data *data = dev->data;

		z_nrf_clock_calibration_init(data->mgr);
	}

	nrfx_clock_enable();
    1640:	f004 f9f3 	bl	5a2a <nrfx_clock_enable>

	for (enum clock_control_nrf_type i = 0;
		i < CLOCK_CONTROL_NRF_TYPE_COUNT; i++) {
		struct nrf_clock_control_sub_data *subdata =
						get_sub_data(dev, i);
    1644:	68e6      	ldr	r6, [r4, #12]

		err = onoff_manager_init(get_onoff_manager(dev, i),
    1646:	490d      	ldr	r1, [pc, #52]	; (167c <clk_init+0x5c>)
    1648:	4630      	mov	r0, r6
    164a:	f003 fdce 	bl	51ea <onoff_manager_init>
					 &transitions);
		if (err < 0) {
    164e:	2800      	cmp	r0, #0
    1650:	db0b      	blt.n	166a <clk_init+0x4a>
			return err;
		}

		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    1652:	2501      	movs	r5, #1
    1654:	6435      	str	r5, [r6, #64]	; 0x40
						get_sub_data(dev, i);
    1656:	68e4      	ldr	r4, [r4, #12]
		err = onoff_manager_init(get_onoff_manager(dev, i),
    1658:	4908      	ldr	r1, [pc, #32]	; (167c <clk_init+0x5c>)
    165a:	f104 001c 	add.w	r0, r4, #28
    165e:	f003 fdc4 	bl	51ea <onoff_manager_init>
		if (err < 0) {
    1662:	2800      	cmp	r0, #0
    1664:	db01      	blt.n	166a <clk_init+0x4a>
	}

	return 0;
    1666:	2000      	movs	r0, #0
		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    1668:	64e5      	str	r5, [r4, #76]	; 0x4c
}
    166a:	bd70      	pop	{r4, r5, r6, pc}
		return -EIO;
    166c:	f06f 0004 	mvn.w	r0, #4
    1670:	e7fb      	b.n	166a <clk_init+0x4a>
    1672:	bf00      	nop
    1674:	000016bd 	.word	0x000016bd
    1678:	0bad0000 	.word	0x0bad0000
    167c:	00005f7c 	.word	0x00005f7c

00001680 <clkstarted_handle.constprop.0>:
static void clkstarted_handle(const struct device *dev,
    1680:	b573      	push	{r0, r1, r4, r5, r6, lr}
	clock_control_cb_t callback = sub_data->cb;
    1682:	230c      	movs	r3, #12
static void clkstarted_handle(const struct device *dev,
    1684:	4601      	mov	r1, r0
	sub_data->cb = NULL;
    1686:	2600      	movs	r6, #0
	clock_control_cb_t callback = sub_data->cb;
    1688:	434b      	muls	r3, r1
    168a:	480a      	ldr	r0, [pc, #40]	; (16b4 <clkstarted_handle.constprop.0+0x34>)
    168c:	18c4      	adds	r4, r0, r3
	set_on_state(&sub_data->flags);
    168e:	3340      	adds	r3, #64	; 0x40
	void *user_data = sub_data->user_data;
    1690:	e9d4 520e 	ldrd	r5, r2, [r4, #56]	; 0x38
	set_on_state(&sub_data->flags);
    1694:	4418      	add	r0, r3
	sub_data->cb = NULL;
    1696:	63a6      	str	r6, [r4, #56]	; 0x38
	void *user_data = sub_data->user_data;
    1698:	9201      	str	r2, [sp, #4]
	set_on_state(&sub_data->flags);
    169a:	f003 ffc5 	bl	5628 <set_on_state>
	if (callback) {
    169e:	b135      	cbz	r5, 16ae <clkstarted_handle.constprop.0+0x2e>
		callback(dev, (clock_control_subsys_t)type, user_data);
    16a0:	462b      	mov	r3, r5
    16a2:	9a01      	ldr	r2, [sp, #4]
    16a4:	4804      	ldr	r0, [pc, #16]	; (16b8 <clkstarted_handle.constprop.0+0x38>)
}
    16a6:	b002      	add	sp, #8
    16a8:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		callback(dev, (clock_control_subsys_t)type, user_data);
    16ac:	4718      	bx	r3
}
    16ae:	b002      	add	sp, #8
    16b0:	bd70      	pop	{r4, r5, r6, pc}
    16b2:	bf00      	nop
    16b4:	20000240 	.word	0x20000240
    16b8:	20000090 	.word	0x20000090

000016bc <clock_event_handler>:
	switch (event) {
    16bc:	b110      	cbz	r0, 16c4 <clock_event_handler+0x8>
    16be:	2801      	cmp	r0, #1
    16c0:	d004      	beq.n	16cc <clock_event_handler+0x10>
    16c2:	4770      	bx	lr
		if (GET_STATUS(data->flags) == CLOCK_CONTROL_STATUS_STARTING) {
    16c4:	4b03      	ldr	r3, [pc, #12]	; (16d4 <clock_event_handler+0x18>)
    16c6:	6c1b      	ldr	r3, [r3, #64]	; 0x40
    16c8:	075b      	lsls	r3, r3, #29
    16ca:	d101      	bne.n	16d0 <clock_event_handler+0x14>
		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_LFCLK);
    16cc:	f7ff bfd8 	b.w	1680 <clkstarted_handle.constprop.0>
}
    16d0:	4770      	bx	lr
    16d2:	bf00      	nop
    16d4:	20000240 	.word	0x20000240

000016d8 <generic_hfclk_start>:
{
    16d8:	b508      	push	{r3, lr}
    16da:	f04f 0320 	mov.w	r3, #32
    16de:	f3ef 8111 	mrs	r1, BASEPRI
    16e2:	f383 8811 	msr	BASEPRI, r3
    16e6:	f3bf 8f6f 	isb	sy
	hfclk_users |= HF_USER_GENERIC;
    16ea:	4a12      	ldr	r2, [pc, #72]	; (1734 <generic_hfclk_start+0x5c>)
    16ec:	6813      	ldr	r3, [r2, #0]
    16ee:	f043 0002 	orr.w	r0, r3, #2
	if (hfclk_users & HF_USER_BT) {
    16f2:	f013 0301 	ands.w	r3, r3, #1
	hfclk_users |= HF_USER_GENERIC;
    16f6:	6010      	str	r0, [r2, #0]
	if (hfclk_users & HF_USER_BT) {
    16f8:	d00c      	beq.n	1714 <generic_hfclk_start+0x3c>
            break;
        case NRF_CLOCK_DOMAIN_HFCLK:
            if (p_clk_src != NULL)
            {
                (*(nrf_clock_hfclk_t *)p_clk_src) =
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    16fa:	f04f 2250 	mov.w	r2, #1342197760	; 0x50005000
    16fe:	f8d2 340c 	ldr.w	r3, [r2, #1036]	; 0x40c
                                        >> CLOCK_HFCLKSTAT_SRC_Pos);
            }
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    1702:	f8d2 240c 	ldr.w	r2, [r2, #1036]	; 0x40c
		if (type == NRF_CLOCK_HFCLK_HIGH_ACCURACY) {
    1706:	f013 0301 	ands.w	r3, r3, #1
    170a:	d003      	beq.n	1714 <generic_hfclk_start+0x3c>
			set_on_state(get_hf_flags());
    170c:	480a      	ldr	r0, [pc, #40]	; (1738 <generic_hfclk_start+0x60>)
    170e:	f003 ff8b 	bl	5628 <set_on_state>
			already_started = true;
    1712:	2301      	movs	r3, #1
	__asm__ volatile(
    1714:	f381 8811 	msr	BASEPRI, r1
    1718:	f3bf 8f6f 	isb	sy
	if (already_started) {
    171c:	b123      	cbz	r3, 1728 <generic_hfclk_start+0x50>
}
    171e:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
		clkstarted_handle(CLOCK_DEVICE,
    1722:	2000      	movs	r0, #0
    1724:	f7ff bfac 	b.w	1680 <clkstarted_handle.constprop.0>
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_start(void)
{
    nrfx_clock_start(NRF_CLOCK_DOMAIN_HFCLK);
    1728:	2001      	movs	r0, #1
}
    172a:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    172e:	f001 bc5f 	b.w	2ff0 <nrfx_clock_start>
    1732:	bf00      	nop
    1734:	20000290 	.word	0x20000290
    1738:	20000280 	.word	0x20000280

0000173c <generic_hfclk_stop>:
 * @return Previous value of @a target.
 */
#ifdef CONFIG_ATOMIC_OPERATIONS_BUILTIN
static inline atomic_val_t atomic_and(atomic_t *target, atomic_val_t value)
{
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    173c:	4b07      	ldr	r3, [pc, #28]	; (175c <generic_hfclk_stop+0x20>)
    173e:	e8d3 2fef 	ldaex	r2, [r3]
    1742:	f022 0102 	bic.w	r1, r2, #2
    1746:	e8c3 1fe0 	stlex	r0, r1, [r3]
    174a:	2800      	cmp	r0, #0
    174c:	d1f7      	bne.n	173e <generic_hfclk_stop+0x2>
	if (atomic_and(&hfclk_users, ~HF_USER_GENERIC) & HF_USER_BT) {
    174e:	07d3      	lsls	r3, r2, #31
    1750:	d402      	bmi.n	1758 <generic_hfclk_stop+0x1c>
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_stop(void)
{
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLK);
    1752:	2001      	movs	r0, #1
    1754:	f001 bc7e 	b.w	3054 <nrfx_clock_stop>
}
    1758:	4770      	bx	lr
    175a:	bf00      	nop
    175c:	20000290 	.word	0x20000290

00001760 <api_blocking_start>:
{
    1760:	b51f      	push	{r0, r1, r2, r3, r4, lr}
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    1762:	2200      	movs	r2, #0
    1764:	2301      	movs	r3, #1
    1766:	e9cd 2302 	strd	r2, r3, [sp, #8]
	err = api_start(dev, subsys, blocking_start_callback, &sem);
    176a:	466b      	mov	r3, sp
    176c:	4a08      	ldr	r2, [pc, #32]	; (1790 <api_blocking_start+0x30>)
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    176e:	f8cd d000 	str.w	sp, [sp]
    1772:	f8cd d004 	str.w	sp, [sp, #4]
	err = api_start(dev, subsys, blocking_start_callback, &sem);
    1776:	f003 ff91 	bl	569c <api_start>
	if (err < 0) {
    177a:	2800      	cmp	r0, #0
    177c:	db05      	blt.n	178a <api_blocking_start+0x2a>
		parm0.val = timeout;
		return (int) arch_syscall_invoke3(*(uintptr_t *)&sem, parm0.split.lo, parm0.split.hi, K_SYSCALL_K_SEM_TAKE);
	}
#endif
	compiler_barrier();
	return z_impl_k_sem_take(sem, timeout);
    177e:	f44f 4280 	mov.w	r2, #16384	; 0x4000
    1782:	2300      	movs	r3, #0
    1784:	4668      	mov	r0, sp
    1786:	f002 fafd 	bl	3d84 <z_impl_k_sem_take>
}
    178a:	b005      	add	sp, #20
    178c:	f85d fb04 	ldr.w	pc, [sp], #4
    1790:	0000566f 	.word	0x0000566f

00001794 <z_nrf_clock_control_lf_on>:
{
    1794:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
	return __atomic_exchange_n(target, value, __ATOMIC_SEQ_CST);
    1798:	2201      	movs	r2, #1
    179a:	4606      	mov	r6, r0
    179c:	4939      	ldr	r1, [pc, #228]	; (1884 <z_nrf_clock_control_lf_on+0xf0>)
    179e:	e8d1 3fef 	ldaex	r3, [r1]
    17a2:	e8c1 2fe0 	stlex	r0, r2, [r1]
    17a6:	2800      	cmp	r0, #0
    17a8:	d1f9      	bne.n	179e <z_nrf_clock_control_lf_on+0xa>
	if (atomic_set(&on, 1) == 0) {
    17aa:	b933      	cbnz	r3, 17ba <z_nrf_clock_control_lf_on+0x26>
 */
static inline void sys_notify_init_spinwait(struct sys_notify *notify)
{
	__ASSERT_NO_MSG(notify != NULL);

	*notify = (struct sys_notify){
    17ac:	4936      	ldr	r1, [pc, #216]	; (1888 <z_nrf_clock_control_lf_on+0xf4>)
		err = onoff_request(mgr, &cli);
    17ae:	4837      	ldr	r0, [pc, #220]	; (188c <z_nrf_clock_control_lf_on+0xf8>)
    17b0:	604b      	str	r3, [r1, #4]
    17b2:	60cb      	str	r3, [r1, #12]
    17b4:	608a      	str	r2, [r1, #8]
    17b6:	f003 fd2b 	bl	5210 <onoff_request>
	switch (start_mode) {
    17ba:	1e73      	subs	r3, r6, #1
    17bc:	2b01      	cmp	r3, #1
    17be:	d832      	bhi.n	1826 <z_nrf_clock_control_lf_on+0x92>
	if ((mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE) &&
    17c0:	2e01      	cmp	r6, #1
    17c2:	d107      	bne.n	17d4 <z_nrf_clock_control_lf_on+0x40>
    return clk_src;
}

NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(NRF_CLOCK_Type const * p_reg)
{
    return (nrf_clock_lfclk_t)((p_reg->LFCLKSRCCOPY & CLOCK_LFCLKSRCCOPY_SRC_Msk)
    17c4:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    17c8:	f8d3 341c 	ldr.w	r3, [r3, #1052]	; 0x41c
	    (target_type == NRF_CLOCK_LFCLK_Xtal) &&
    17cc:	f003 0303 	and.w	r3, r3, #3
    17d0:	2b02      	cmp	r3, #2
    17d2:	d028      	beq.n	1826 <z_nrf_clock_control_lf_on+0x92>
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    17d4:	f004 fa19 	bl	5c0a <k_is_in_isr>
    17d8:	4604      	mov	r4, r0
    17da:	b918      	cbnz	r0, 17e4 <z_nrf_clock_control_lf_on+0x50>
	return !z_sys_post_kernel;
    17dc:	4b2c      	ldr	r3, [pc, #176]	; (1890 <z_nrf_clock_control_lf_on+0xfc>)
	int key = isr_mode ? irq_lock() : 0;
    17de:	781b      	ldrb	r3, [r3, #0]
    17e0:	2b00      	cmp	r3, #0
    17e2:	d147      	bne.n	1874 <z_nrf_clock_control_lf_on+0xe0>
	__asm__ volatile(
    17e4:	f04f 0320 	mov.w	r3, #32
    17e8:	f3ef 8511 	mrs	r5, BASEPRI
    17ec:	f383 8811 	msr	BASEPRI, r3
    17f0:	f3bf 8f6f 	isb	sy
    17f4:	2401      	movs	r4, #1
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    17f6:	4f27      	ldr	r7, [pc, #156]	; (1894 <z_nrf_clock_control_lf_on+0x100>)
 */
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
  {
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    17f8:	f8df 809c 	ldr.w	r8, [pc, #156]	; 1898 <z_nrf_clock_control_lf_on+0x104>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    17fc:	f8df 909c 	ldr.w	r9, [pc, #156]	; 189c <z_nrf_clock_control_lf_on+0x108>
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    1800:	f04f 2250 	mov.w	r2, #1342197760	; 0x50005000
    1804:	f8d2 3418 	ldr.w	r3, [r2, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    1808:	f8d2 2418 	ldr.w	r2, [r2, #1048]	; 0x418
    180c:	03d2      	lsls	r2, r2, #15
    180e:	d50c      	bpl.n	182a <z_nrf_clock_control_lf_on+0x96>
	while (!(nrfx_clock_is_running(d, (void *)&type)
    1810:	f003 0303 	and.w	r3, r3, #3
    1814:	2b02      	cmp	r3, #2
    1816:	d001      	beq.n	181c <z_nrf_clock_control_lf_on+0x88>
		     || (mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE)))) {
    1818:	2e01      	cmp	r6, #1
    181a:	d106      	bne.n	182a <z_nrf_clock_control_lf_on+0x96>
	if (isr_mode) {
    181c:	b324      	cbz	r4, 1868 <z_nrf_clock_control_lf_on+0xd4>
	__asm__ volatile(
    181e:	f385 8811 	msr	BASEPRI, r5
    1822:	f3bf 8f6f 	isb	sy
}
    1826:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
			if (isr_mode) {
    182a:	b1c4      	cbz	r4, 185e <z_nrf_clock_control_lf_on+0xca>
 *
 * @return N/A
 */
static inline void k_cpu_atomic_idle(unsigned int key)
{
	arch_cpu_atomic_idle(key);
    182c:	4628      	mov	r0, r5
    182e:	f000 fd27 	bl	2280 <arch_cpu_atomic_idle>
    return (nrf_clock_lfclk_t)(p_reg->LFCLKSRC);
    1832:	f04f 2250 	mov.w	r2, #1342197760	; 0x50005000
    1836:	f8d2 3518 	ldr.w	r3, [r2, #1304]	; 0x518
		if ((target_type ==  NRF_CLOCK_LFCLK_Xtal)
    183a:	b2db      	uxtb	r3, r3
    183c:	2b01      	cmp	r3, #1
    183e:	d1df      	bne.n	1800 <z_nrf_clock_control_lf_on+0x6c>
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    1840:	6839      	ldr	r1, [r7, #0]
		    && nrf_clock_event_check(NRF_CLOCK,
    1842:	2900      	cmp	r1, #0
    1844:	d0dc      	beq.n	1800 <z_nrf_clock_control_lf_on+0x6c>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    1846:	2100      	movs	r1, #0
    1848:	6039      	str	r1, [r7, #0]
#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE void nrf_event_readback(void * p_event_reg)
{
#if NRFX_CHECK(NRFX_EVENT_READBACK_ENABLED) && !defined(NRF51)
    (void)*((volatile uint32_t *)(p_event_reg));
    184a:	6839      	ldr	r1, [r7, #0]
    p_reg->LFCLKSRC = (uint32_t)(source);
    184c:	2102      	movs	r1, #2
    184e:	f8c2 1518 	str.w	r1, [r2, #1304]	; 0x518
    1852:	2220      	movs	r2, #32
    1854:	f8c8 2180 	str.w	r2, [r8, #384]	; 0x180
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    1858:	f8c9 3000 	str.w	r3, [r9]
}
    185c:	e7d0      	b.n	1800 <z_nrf_clock_control_lf_on+0x6c>
	return z_impl_k_sleep(timeout);
    185e:	2100      	movs	r1, #0
    1860:	2021      	movs	r0, #33	; 0x21
    1862:	f002 fa47 	bl	3cf4 <z_impl_k_sleep>
	return k_sleep(Z_TIMEOUT_MS(ms));
    1866:	e7e4      	b.n	1832 <z_nrf_clock_control_lf_on+0x9e>
    p_reg->INTENSET = mask;
    1868:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    186c:	2202      	movs	r2, #2
    186e:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
}
    1872:	e7d8      	b.n	1826 <z_nrf_clock_control_lf_on+0x92>
    p_reg->INTENCLR = mask;
    1874:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    1878:	2202      	movs	r2, #2
	int key = isr_mode ? irq_lock() : 0;
    187a:	4605      	mov	r5, r0
    187c:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
}
    1880:	e7b9      	b.n	17f6 <z_nrf_clock_control_lf_on+0x62>
    1882:	bf00      	nop
    1884:	20000294 	.word	0x20000294
    1888:	20000230 	.word	0x20000230
    188c:	2000025c 	.word	0x2000025c
    1890:	200008ae 	.word	0x200008ae
    1894:	50005104 	.word	0x50005104
    1898:	e000e100 	.word	0xe000e100
    189c:	50005008 	.word	0x50005008

000018a0 <sys_clock_timeout_handler>:

static void sys_clock_timeout_handler(uint32_t chan,
				      uint32_t cc_value,
				      void *user_data)
{
	uint32_t dticks = counter_sub(cc_value, last_count) / CYC_PER_TICK;
    18a0:	4a04      	ldr	r2, [pc, #16]	; (18b4 <sys_clock_timeout_handler+0x14>)
    18a2:	6813      	ldr	r3, [r2, #0]
	return (a - b) & COUNTER_MAX;
    18a4:	1ac9      	subs	r1, r1, r3
    18a6:	f021 407f 	bic.w	r0, r1, #4278190080	; 0xff000000

	last_count += dticks * CYC_PER_TICK;
    18aa:	4403      	add	r3, r0
    18ac:	6013      	str	r3, [r2, #0]
		 */
		compare_set(chan, last_count + CYC_PER_TICK,
					  sys_clock_timeout_handler, NULL);
	}

	z_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
    18ae:	f002 bc2d 	b.w	410c <z_clock_announce>
    18b2:	bf00      	nop
    18b4:	200002a4 	.word	0x200002a4

000018b8 <set_absolute_alarm>:
{
    18b8:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    18bc:	f44f 3780 	mov.w	r7, #65536	; 0x10000
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
}

NRF_STATIC_INLINE void nrf_rtc_event_clear(NRF_RTC_Type * p_reg, nrf_rtc_event_t event)
{
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    18c0:	f04f 0900 	mov.w	r9, #0
    18c4:	0086      	lsls	r6, r0, #2
	nrf_rtc_event_clear(RTC, RTC_CHANNEL_EVENT_ADDR(chan));
    18c6:	f100 0450 	add.w	r4, r0, #80	; 0x50
    18ca:	f106 2650 	add.w	r6, r6, #1342197760	; 0x50005000
    18ce:	00a4      	lsls	r4, r4, #2
    18d0:	f506 3680 	add.w	r6, r6, #65536	; 0x10000
    18d4:	b2a4      	uxth	r4, r4
    18d6:	f104 2450 	add.w	r4, r4, #1342197760	; 0x50005000
    return p_reg->CC[ch];
    18da:	f8d6 3540 	ldr.w	r3, [r6, #1344]	; 0x540
    nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}

NRF_STATIC_INLINE uint32_t nrf_rtc_counter_get(NRF_RTC_Type const * p_reg)
{
     return p_reg->COUNTER;
    18de:	f8df 806c 	ldr.w	r8, [pc, #108]	; 194c <set_absolute_alarm+0x94>
	uint32_t cc_val = abs_val & COUNTER_MAX;
    18e2:	f021 457f 	bic.w	r5, r1, #4278190080	; 0xff000000
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    18e6:	f504 3480 	add.w	r4, r4, #65536	; 0x10000
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    18ea:	4087      	lsls	r7, r0
     return p_reg->COUNTER;
    18ec:	f8d8 a504 	ldr.w	sl, [r8, #1284]	; 0x504
	return (a - b) & COUNTER_MAX;
    18f0:	eba3 030a 	sub.w	r3, r3, sl
    18f4:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
	nrf_rtc_cc_set(RTC, chan, cyc & COUNTER_MAX);
    18f8:	f02a 427f 	bic.w	r2, sl, #4278190080	; 0xff000000
		if (counter_sub(prev_cc, now) == 1) {
    18fc:	2b01      	cmp	r3, #1
    p_reg->CC[ch] = cc_val;
    18fe:	f8c6 2540 	str.w	r2, [r6, #1344]	; 0x540
    1902:	d102      	bne.n	190a <set_absolute_alarm+0x52>
	z_impl_k_busy_wait(usec_to_wait);
    1904:	2013      	movs	r0, #19
    1906:	f004 f986 	bl	5c16 <z_impl_k_busy_wait>
		if (counter_sub(cc_val, now + 2) > COUNTER_HALF_SPAN) {
    190a:	f10a 0202 	add.w	r2, sl, #2
	return (a - b) & COUNTER_MAX;
    190e:	1aab      	subs	r3, r5, r2
    1910:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
			cc_val = now + 2;
    1914:	f5b3 0f00 	cmp.w	r3, #8388608	; 0x800000
    1918:	bf88      	it	hi
    191a:	4615      	movhi	r5, r2
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    191c:	f8c4 9000 	str.w	r9, [r4]
    1920:	6823      	ldr	r3, [r4, #0]
	nrf_rtc_cc_set(RTC, chan, cyc & COUNTER_MAX);
    1922:	f025 437f 	bic.w	r3, r5, #4278190080	; 0xff000000
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
}

NRF_STATIC_INLINE void nrf_rtc_event_enable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->EVTENSET = mask;
    1926:	f8c8 7344 	str.w	r7, [r8, #836]	; 0x344
    p_reg->CC[ch] = cc_val;
    192a:	f8c6 3540 	str.w	r3, [r6, #1344]	; 0x540
     return p_reg->COUNTER;
    192e:	f8d8 3504 	ldr.w	r3, [r8, #1284]	; 0x504
		 (counter_sub(cc_val, now2 + 2) > COUNTER_HALF_SPAN));
    1932:	459a      	cmp	sl, r3
    1934:	d006      	beq.n	1944 <set_absolute_alarm+0x8c>
	return (a - b) & COUNTER_MAX;
    1936:	1aeb      	subs	r3, r5, r3
    1938:	3b02      	subs	r3, #2
    193a:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
	} while ((now2 != now) &&
    193e:	f5b3 0f00 	cmp.w	r3, #8388608	; 0x800000
    1942:	d801      	bhi.n	1948 <set_absolute_alarm+0x90>
}
    1944:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
		prev_cc = cc_val;
    1948:	462b      	mov	r3, r5
    194a:	e7cf      	b.n	18ec <set_absolute_alarm+0x34>
    194c:	50015000 	.word	0x50015000

00001950 <rtc_nrf_isr>:
 * probably better abstract that at some point (e.g. query and reset
 * it by pointer at runtime, maybe?) so we don't have this leaky
 * symbol.
 */
void rtc_nrf_isr(const void *arg)
{
    1950:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	ARG_UNUSED(arg);

	for (uint32_t chan = 0; chan < CHAN_COUNT; chan++) {
    1952:	2400      	movs	r4, #0
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    1954:	4627      	mov	r7, r4
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    1956:	4e0f      	ldr	r6, [pc, #60]	; (1994 <rtc_nrf_isr+0x44>)
    1958:	4b0f      	ldr	r3, [pc, #60]	; (1998 <rtc_nrf_isr+0x48>)
    return p_reg->INTENSET & mask;
    195a:	4a10      	ldr	r2, [pc, #64]	; (199c <rtc_nrf_isr+0x4c>)
    195c:	4618      	mov	r0, r3
    195e:	681d      	ldr	r5, [r3, #0]
    1960:	b104      	cbz	r4, 1964 <rtc_nrf_isr+0x14>
				handler(chan, cc_val,
					cc_data[chan].user_context);
			}
		}
	}
}
    1962:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    1964:	f8d2 1304 	ldr.w	r1, [r2, #772]	; 0x304
		if (nrf_rtc_int_enable_check(RTC, RTC_CHANNEL_INT_MASK(chan)) &&
    1968:	03c9      	lsls	r1, r1, #15
    196a:	d5fa      	bpl.n	1962 <rtc_nrf_isr+0x12>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    196c:	6831      	ldr	r1, [r6, #0]
    196e:	2900      	cmp	r1, #0
    1970:	d0f7      	beq.n	1962 <rtc_nrf_isr+0x12>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    1972:	6034      	str	r4, [r6, #0]
    1974:	6831      	ldr	r1, [r6, #0]
}

NRF_STATIC_INLINE void nrf_rtc_event_disable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->EVTENCLR = mask;
    1976:	f44f 3180 	mov.w	r1, #65536	; 0x10000
    197a:	f8c2 1348 	str.w	r1, [r2, #840]	; 0x348
	for (uint32_t chan = 0; chan < CHAN_COUNT; chan++) {
    197e:	2401      	movs	r4, #1
    return p_reg->CC[ch];
    1980:	f8d2 1540 	ldr.w	r1, [r2, #1344]	; 0x540
			if (handler) {
    1984:	b125      	cbz	r5, 1990 <rtc_nrf_isr+0x40>
				handler(chan, cc_val,
    1986:	2000      	movs	r0, #0
    1988:	685a      	ldr	r2, [r3, #4]
    198a:	601f      	str	r7, [r3, #0]
    198c:	47a8      	blx	r5
    198e:	e7e3      	b.n	1958 <rtc_nrf_isr+0x8>
    1990:	6005      	str	r5, [r0, #0]
}
    1992:	e7e6      	b.n	1962 <rtc_nrf_isr+0x12>
    1994:	50015140 	.word	0x50015140
    1998:	20000298 	.word	0x20000298
    199c:	50015000 	.word	0x50015000

000019a0 <z_clock_driver_init>:

	atomic_or(&alloc_mask, BIT(chan));
}

int z_clock_driver_init(const struct device *device)
{
    19a0:	b538      	push	{r3, r4, r5, lr}
    p_reg->PRESCALER = val;
    19a2:	2400      	movs	r4, #0
    p_reg->INTENSET = mask;
    19a4:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    19a8:	f44f 1200 	mov.w	r2, #2097152	; 0x200000
    p_reg->PRESCALER = val;
    19ac:	4d0d      	ldr	r5, [pc, #52]	; (19e4 <z_clock_driver_init+0x44>)
		nrf_rtc_int_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
	}

	NVIC_ClearPendingIRQ(RTC_IRQn);

	IRQ_CONNECT(RTC_IRQn, DT_IRQ(DT_NODELABEL(RTC_LABEL), priority),
    19ae:	2101      	movs	r1, #1
    19b0:	f8c5 4508 	str.w	r4, [r5, #1288]	; 0x508
    p_reg->INTENSET = mask;
    19b4:	f8c5 3304 	str.w	r3, [r5, #772]	; 0x304
    19b8:	4b0b      	ldr	r3, [pc, #44]	; (19e8 <z_clock_driver_init+0x48>)
    19ba:	2015      	movs	r0, #21
    19bc:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
    19c0:	4622      	mov	r2, r4
    19c2:	f000 fbf9 	bl	21b8 <z_arm_irq_priority_set>
		    rtc_nrf_isr, 0, 0);
	irq_enable(RTC_IRQn);
    19c6:	2015      	movs	r0, #21
    19c8:	f000 fbd8 	bl	217c <arch_irq_enable>
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    19cc:	2301      	movs	r3, #1
    19ce:	4a07      	ldr	r2, [pc, #28]	; (19ec <z_clock_driver_init+0x4c>)
	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
		compare_set(0, counter() + CYC_PER_TICK,
			    sys_clock_timeout_handler, NULL);
	}

	z_nrf_clock_control_lf_on(mode);
    19d0:	2002      	movs	r0, #2
    19d2:	6013      	str	r3, [r2, #0]
	int_mask = BIT_MASK(CHAN_COUNT);
    19d4:	4a06      	ldr	r2, [pc, #24]	; (19f0 <z_clock_driver_init+0x50>)
    19d6:	602b      	str	r3, [r5, #0]
    19d8:	6013      	str	r3, [r2, #0]
	z_nrf_clock_control_lf_on(mode);
    19da:	f7ff fedb 	bl	1794 <z_nrf_clock_control_lf_on>

	return 0;
}
    19de:	4620      	mov	r0, r4
    19e0:	bd38      	pop	{r3, r4, r5, pc}
    19e2:	bf00      	nop
    19e4:	50015000 	.word	0x50015000
    19e8:	e000e100 	.word	0xe000e100
    19ec:	50015008 	.word	0x50015008
    19f0:	200002a0 	.word	0x200002a0

000019f4 <z_clock_set_timeout>:

	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
		return;
	}

	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    19f4:	4b13      	ldr	r3, [pc, #76]	; (1a44 <z_clock_set_timeout+0x50>)
    19f6:	f1b0 3fff 	cmp.w	r0, #4294967295	; 0xffffffff
    19fa:	bf08      	it	eq
    19fc:	4618      	moveq	r0, r3
	ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
    19fe:	3801      	subs	r0, #1
    1a00:	2800      	cmp	r0, #0
    1a02:	dd1c      	ble.n	1a3e <z_clock_set_timeout+0x4a>
    1a04:	4298      	cmp	r0, r3
    1a06:	bfa8      	it	ge
    1a08:	4618      	movge	r0, r3
     return p_reg->COUNTER;
    1a0a:	4b0f      	ldr	r3, [pc, #60]	; (1a48 <z_clock_set_timeout+0x54>)
    1a0c:	f8d3 2504 	ldr.w	r2, [r3, #1284]	; 0x504

	uint32_t unannounced = counter_sub(counter(), last_count);
    1a10:	4b0e      	ldr	r3, [pc, #56]	; (1a4c <z_clock_set_timeout+0x58>)
    1a12:	6819      	ldr	r1, [r3, #0]
	return (a - b) & COUNTER_MAX;
    1a14:	1a52      	subs	r2, r2, r1
	 * duration, then force an announce to avoid loss of a wrap
	 * event.  This can happen if new timeouts keep being set
	 * before the existing one triggers the interrupt.
	 */
	if (unannounced >= COUNTER_HALF_SPAN) {
		ticks = 0;
    1a16:	f412 0f00 	tst.w	r2, #8388608	; 0x800000
    1a1a:	bf18      	it	ne
    1a1c:	2000      	movne	r0, #0
	return (a - b) & COUNTER_MAX;
    1a1e:	f022 437f 	bic.w	r3, r2, #4278190080	; 0xff000000
	}

	/* Get the cycles from last_count to the tick boundary after
	 * the requested ticks have passed starting now.
	 */
	cyc = ticks * CYC_PER_TICK + 1 + unannounced;
    1a22:	3301      	adds	r3, #1
	cc_data[chan].callback = handler;
    1a24:	4a0a      	ldr	r2, [pc, #40]	; (1a50 <z_clock_set_timeout+0x5c>)
	cyc = ticks * CYC_PER_TICK + 1 + unannounced;
    1a26:	4403      	add	r3, r0
	cc_data[chan].callback = handler;
    1a28:	480a      	ldr	r0, [pc, #40]	; (1a54 <z_clock_set_timeout+0x60>)
    1a2a:	6010      	str	r0, [r2, #0]
	cc_data[chan].user_context = user_data;
    1a2c:	2000      	movs	r0, #0
    1a2e:	6050      	str	r0, [r2, #4]
	set_absolute_alarm(chan, cc_value);
    1a30:	4a04      	ldr	r2, [pc, #16]	; (1a44 <z_clock_set_timeout+0x50>)
    1a32:	4293      	cmp	r3, r2
    1a34:	bf94      	ite	ls
    1a36:	18c9      	addls	r1, r1, r3
    1a38:	1889      	addhi	r1, r1, r2
    1a3a:	f7ff bf3d 	b.w	18b8 <set_absolute_alarm>
	ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
    1a3e:	2000      	movs	r0, #0
    1a40:	e7e3      	b.n	1a0a <z_clock_set_timeout+0x16>
    1a42:	bf00      	nop
    1a44:	007fffff 	.word	0x007fffff
    1a48:	50015000 	.word	0x50015000
    1a4c:	200002a4 	.word	0x200002a4
    1a50:	20000298 	.word	0x20000298
    1a54:	000018a1 	.word	0x000018a1

00001a58 <z_clock_elapsed>:
	__asm__ volatile(
    1a58:	f04f 0220 	mov.w	r2, #32
    1a5c:	f3ef 8311 	mrs	r3, BASEPRI
    1a60:	f382 8811 	msr	BASEPRI, r2
    1a64:	f3bf 8f6f 	isb	sy
    1a68:	4a06      	ldr	r2, [pc, #24]	; (1a84 <z_clock_elapsed+0x2c>)
    1a6a:	f8d2 0504 	ldr.w	r0, [r2, #1284]	; 0x504
	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
		return 0;
	}

	k_spinlock_key_t key = k_spin_lock(&lock);
	uint32_t ret = counter_sub(counter(), last_count) / CYC_PER_TICK;
    1a6e:	4a06      	ldr	r2, [pc, #24]	; (1a88 <z_clock_elapsed+0x30>)
	return (a - b) & COUNTER_MAX;
    1a70:	6812      	ldr	r2, [r2, #0]
    1a72:	1a80      	subs	r0, r0, r2
    1a74:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
	__asm__ volatile(
    1a78:	f383 8811 	msr	BASEPRI, r3
    1a7c:	f3bf 8f6f 	isb	sy

	k_spin_unlock(&lock, key);
	return ret;
}
    1a80:	4770      	bx	lr
    1a82:	bf00      	nop
    1a84:	50015000 	.word	0x50015000
    1a88:	200002a4 	.word	0x200002a4

00001a8c <config_regions>:
}
#endif /* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS */


static void config_regions(bool ram, size_t start, size_t end, uint32_t perm)
{
    1a8c:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
	const size_t region_size = ram ? RAM_SECURE_ATTRIBUTION_REGION_SIZE
					: FLASH_SECURE_ATTRIBUTION_REGION_SIZE;
    1a8e:	2800      	cmp	r0, #0
{
    1a90:	461c      	mov	r4, r3
					: FLASH_SECURE_ATTRIBUTION_REGION_SIZE;
    1a92:	bf14      	ite	ne
    1a94:	f44f 5300 	movne.w	r3, #8192	; 0x2000
    1a98:	f44f 4300 	moveq.w	r3, #32768	; 0x8000

	__ASSERT_NO_MSG(end >= start);
	if (end <= start) {
    1a9c:	428a      	cmp	r2, r1
    1a9e:	d941      	bls.n	1b24 <config_regions+0x98>
    1aa0:	460d      	mov	r5, r1
    1aa2:	4f21      	ldr	r7, [pc, #132]	; (1b28 <config_regions+0x9c>)
		return;
	}

	for (size_t i = start; i < end; i++) {
		if (ram) {
    1aa4:	2800      	cmp	r0, #0
    1aa6:	d03a      	beq.n	1b1e <config_regions+0x92>
			NRF_SPU->RAMREGION[i].PERM = perm;
    1aa8:	f505 76e0 	add.w	r6, r5, #448	; 0x1c0
		} else {
			NRF_SPU->FLASHREGION[i].PERM = perm;
    1aac:	f847 4026 	str.w	r4, [r7, r6, lsl #2]
	for (size_t i = start; i < end; i++) {
    1ab0:	1c6e      	adds	r6, r5, #1
    1ab2:	42b2      	cmp	r2, r6
    1ab4:	d131      	bne.n	1b1a <config_regions+0x8e>
		}
	}

	PRINT("%02u %02u 0x%05x 0x%05x \t", start, end - 1,
    1ab6:	435a      	muls	r2, r3
    1ab8:	481c      	ldr	r0, [pc, #112]	; (1b2c <config_regions+0xa0>)
    1aba:	434b      	muls	r3, r1
    1abc:	9200      	str	r2, [sp, #0]
    1abe:	462a      	mov	r2, r5
    1ac0:	f003 fb36 	bl	5130 <printk>
				region_size * start, region_size * end);
	PRINT("%s", perm & (ram ? SRAM_SECURE : FLASH_SECURE) ? "Secure\t\t" :
    1ac4:	4b1a      	ldr	r3, [pc, #104]	; (1b30 <config_regions+0xa4>)
    1ac6:	f014 0f10 	tst.w	r4, #16
    1aca:	491a      	ldr	r1, [pc, #104]	; (1b34 <config_regions+0xa8>)
    1acc:	481a      	ldr	r0, [pc, #104]	; (1b38 <config_regions+0xac>)
    1ace:	bf08      	it	eq
    1ad0:	4619      	moveq	r1, r3
    1ad2:	f003 fb2d 	bl	5130 <printk>
								"Non-Secure\t");
	PRINT("%c", perm & (ram ? SRAM_READ : FLASH_READ)  ? 'r' : '-');
    1ad6:	f014 0f04 	tst.w	r4, #4
    1ada:	bf14      	ite	ne
    1adc:	2172      	movne	r1, #114	; 0x72
    1ade:	212d      	moveq	r1, #45	; 0x2d
    1ae0:	4816      	ldr	r0, [pc, #88]	; (1b3c <config_regions+0xb0>)
    1ae2:	f003 fb25 	bl	5130 <printk>
	PRINT("%c", perm & (ram ? SRAM_WRITE : FLASH_WRITE) ? 'w' : '-');
    1ae6:	f014 0f02 	tst.w	r4, #2
    1aea:	bf14      	ite	ne
    1aec:	2177      	movne	r1, #119	; 0x77
    1aee:	212d      	moveq	r1, #45	; 0x2d
    1af0:	4812      	ldr	r0, [pc, #72]	; (1b3c <config_regions+0xb0>)
    1af2:	f003 fb1d 	bl	5130 <printk>
	PRINT("%c", perm & (ram ? SRAM_EXEC : FLASH_EXEC)  ? 'x' : '-');
    1af6:	f014 0f01 	tst.w	r4, #1
    1afa:	bf0c      	ite	eq
    1afc:	212d      	moveq	r1, #45	; 0x2d
    1afe:	2178      	movne	r1, #120	; 0x78
    1b00:	480e      	ldr	r0, [pc, #56]	; (1b3c <config_regions+0xb0>)
    1b02:	f003 fb15 	bl	5130 <printk>
	PRINT("%c", perm & (ram ? SRAM_LOCK : FLASH_LOCK)  ? 'l' : '-');
    1b06:	216c      	movs	r1, #108	; 0x6c
    1b08:	480c      	ldr	r0, [pc, #48]	; (1b3c <config_regions+0xb0>)
    1b0a:	f003 fb11 	bl	5130 <printk>
	PRINT("\n");
    1b0e:	480c      	ldr	r0, [pc, #48]	; (1b40 <config_regions+0xb4>)
}
    1b10:	b003      	add	sp, #12
    1b12:	e8bd 40f0 	ldmia.w	sp!, {r4, r5, r6, r7, lr}
	PRINT("\n");
    1b16:	f003 bb0b 	b.w	5130 <printk>
    1b1a:	4635      	mov	r5, r6
    1b1c:	e7c2      	b.n	1aa4 <config_regions+0x18>
			NRF_SPU->FLASHREGION[i].PERM = perm;
    1b1e:	f505 76c0 	add.w	r6, r5, #384	; 0x180
    1b22:	e7c3      	b.n	1aac <config_regions+0x20>
}
    1b24:	b003      	add	sp, #12
    1b26:	bdf0      	pop	{r4, r5, r6, r7, pc}
    1b28:	50003000 	.word	0x50003000
    1b2c:	00006257 	.word	0x00006257
    1b30:	0000624b 	.word	0x0000624b
    1b34:	00006242 	.word	0x00006242
    1b38:	000063d6 	.word	0x000063d6
    1b3c:	00006271 	.word	0x00006271
    1b40:	000065ac 	.word	0x000065ac

00001b44 <spm_config_peripheral.constprop.0>:
		     SPU_PERIPHID_PERM_SECUREMAPPING_Split;

	return present && (usel || split);
}

static int spm_config_peripheral(uint8_t id, bool dma_present)
    1b44:	b508      	push	{r3, lr}
	 * Assign DMA capabilities and lock down the attribution.
	 *
	 * Note: the function assumes that the peripheral ID matches
	 * the IRQ line.
	 */
	NVIC_DisableIRQ(id);
    1b46:	b243      	sxtb	r3, r0
  if ((int32_t)(IRQn) >= 0)
    1b48:	2b00      	cmp	r3, #0
    1b4a:	db0c      	blt.n	1b66 <spm_config_peripheral.constprop.0+0x22>
    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    1b4c:	2201      	movs	r2, #1
    1b4e:	f000 011f 	and.w	r1, r0, #31
    1b52:	408a      	lsls	r2, r1
    1b54:	095b      	lsrs	r3, r3, #5
    1b56:	4910      	ldr	r1, [pc, #64]	; (1b98 <spm_config_peripheral.constprop.0+0x54>)
    1b58:	3320      	adds	r3, #32
    1b5a:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
  \details Acts as a special kind of Data Memory Barrier.
           It completes when all explicit memory accesses before this instruction complete.
 */
__STATIC_FORCEINLINE void __DSB(void)
{
  __ASM volatile ("dsb 0xF":::"memory");
    1b5e:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    1b62:	f3bf 8f6f 	isb	sy
	const uint32_t perm = NRF_SPU->PERIPHID[id].PERM;
    1b66:	0083      	lsls	r3, r0, #2
    1b68:	f103 43a0 	add.w	r3, r3, #1342177280	; 0x50000000
    1b6c:	f503 5340 	add.w	r3, r3, #12288	; 0x3000
	if (id == NRFX_PERIPHERAL_ID_GET(NRF_GPIOTE1_NS)) {
    1b70:	2831      	cmp	r0, #49	; 0x31
	const uint32_t perm = NRF_SPU->PERIPHID[id].PERM;
    1b72:	f8d3 2800 	ldr.w	r2, [r3, #2048]	; 0x800
	if (id == NRFX_PERIPHERAL_ID_GET(NRF_GPIOTE1_NS)) {
    1b76:	d006      	beq.n	1b86 <spm_config_peripheral.constprop.0+0x42>
	return present && (usel || split);
    1b78:	2a00      	cmp	r2, #0
    1b7a:	da07      	bge.n	1b8c <spm_config_peripheral.constprop.0+0x48>
	bool usel = (perm & SPU_PERIPHID_PERM_SECUREMAPPING_Msk) ==
    1b7c:	f002 0203 	and.w	r2, r2, #3
	return present && (usel || split);
    1b80:	3a02      	subs	r2, #2
    1b82:	2a01      	cmp	r2, #1
    1b84:	d802      	bhi.n	1b8c <spm_config_peripheral.constprop.0+0x48>

	if (usel_or_split(id)) {
		NRF_SPU->PERIPHID[id].PERM = PERIPH_PRESENT | PERIPH_NONSEC |
    1b86:	4a05      	ldr	r2, [pc, #20]	; (1b9c <spm_config_peripheral.constprop.0+0x58>)
    1b88:	f8c3 2800 	str.w	r2, [r3, #2048]	; 0x800
	}

	/* Even for non-present peripherals we force IRQs to be routed
	 * to Non-Secure state.
	 */
	irq_target_state_set(id, IRQ_TARGET_STATE_NON_SECURE);
    1b8c:	2101      	movs	r1, #1
    1b8e:	f003 fe01 	bl	5794 <irq_target_state_set>
	return 0;
}
    1b92:	2000      	movs	r0, #0
    1b94:	bd08      	pop	{r3, pc}
    1b96:	bf00      	nop
    1b98:	e000e100 	.word	0xe000e100
    1b9c:	80000100 	.word	0x80000100

00001ba0 <spm_jump>:
	tz_nonsecure_fpu_access_enable();
#endif /* CONFIG_ARMV7_M_ARMV8_M_FP */
}

void spm_jump(void)
{
    1ba0:	b530      	push	{r4, r5, lr}
	 * The assumption is that the MSP is located at VTOR_NS[0].
	 */
	uint32_t *vtor_ns = (uint32_t *)NON_SECURE_APP_ADDRESS;

	PRINT("SPM: NS image at 0x%x\n", (uint32_t)vtor_ns);
	PRINT("SPM: NS MSP at 0x%x\n", vtor_ns[0]);
    1ba2:	f44f 4440 	mov.w	r4, #49152	; 0xc000
	PRINT("SPM: NS reset vector at 0x%x\n", vtor_ns[1]);
    1ba6:	f24c 0504 	movw	r5, #49156	; 0xc004
{
    1baa:	b085      	sub	sp, #20
	PRINT("SPM: NS image at 0x%x\n", (uint32_t)vtor_ns);
    1bac:	f44f 4140 	mov.w	r1, #49152	; 0xc000
    1bb0:	482c      	ldr	r0, [pc, #176]	; (1c64 <spm_jump+0xc4>)
    1bb2:	f003 fabd 	bl	5130 <printk>
	PRINT("SPM: NS MSP at 0x%x\n", vtor_ns[0]);
    1bb6:	6821      	ldr	r1, [r4, #0]
    1bb8:	482b      	ldr	r0, [pc, #172]	; (1c68 <spm_jump+0xc8>)
    1bba:	f003 fab9 	bl	5130 <printk>
	PRINT("SPM: NS reset vector at 0x%x\n", vtor_ns[1]);
    1bbe:	6829      	ldr	r1, [r5, #0]
    1bc0:	482a      	ldr	r0, [pc, #168]	; (1c6c <spm_jump+0xcc>)
    1bc2:	f003 fab5 	bl	5130 <printk>

	/* Configure Non-Secure stack */
	tz_nonsecure_setup_conf_t spm_ns_conf = {
    1bc6:	2210      	movs	r2, #16
    1bc8:	2100      	movs	r1, #0
    1bca:	4668      	mov	r0, sp
    1bcc:	f003 feaf 	bl	592e <memset>
		.vtor_ns = (uint32_t)vtor_ns,
		.msp_ns = vtor_ns[0],
    1bd0:	6823      	ldr	r3, [r4, #0]
	tz_nonsecure_state_setup(spm_ns_conf);
    1bd2:	4668      	mov	r0, sp
	tz_nonsecure_setup_conf_t spm_ns_conf = {
    1bd4:	9300      	str	r3, [sp, #0]
    1bd6:	9402      	str	r4, [sp, #8]
	tz_nonsecure_state_setup(spm_ns_conf);
    1bd8:	f000 fe9a 	bl	2910 <tz_nonsecure_state_setup>
	tz_nonsecure_exception_prio_config(1);
    1bdc:	2001      	movs	r0, #1
    1bde:	f000 fec7 	bl	2970 <tz_nonsecure_exception_prio_config>
	tz_nbanked_exception_target_state_set(0);
    1be2:	2000      	movs	r0, #0
    1be4:	f000 feb0 	bl	2948 <tz_nbanked_exception_target_state_set>
	tz_nonsecure_system_reset_req_block(
    1be8:	2000      	movs	r0, #0
    1bea:	f000 fed5 	bl	2998 <tz_nonsecure_system_reset_req_block>
	tz_sau_configure(0, 1);
    1bee:	2101      	movs	r1, #1
    1bf0:	2000      	movs	r0, #0
    1bf2:	f000 feef 	bl	29d4 <tz_sau_configure>
	tz_nonsecure_fpu_access_enable();
    1bf6:	f000 fee3 	bl	29c0 <tz_nonsecure_fpu_access_enable>

	spm_configure_ns(&spm_ns_conf);

	/* Generate function pointer for Non-Secure function call. */
	TZ_NONSECURE_FUNC_PTR_DECLARE(reset_ns);
	reset_ns = TZ_NONSECURE_FUNC_PTR_CREATE(vtor_ns[1]);
    1bfa:	682c      	ldr	r4, [r5, #0]

	if (TZ_NONSECURE_FUNC_PTR_IS_NS(reset_ns)) {
		PRINT("SPM: prepare to jump to Non-Secure image.\n");
    1bfc:	481c      	ldr	r0, [pc, #112]	; (1c70 <spm_jump+0xd0>)
    1bfe:	f003 fa97 	bl	5130 <printk>
		/* Note: Move UARTE0 before jumping, if it is
		 * to be used on the Non-Secure domain.
		 */

		/* Configure UARTE0 as non-secure */
		spm_config_peripheral(
    1c02:	2008      	movs	r0, #8
    1c04:	f7ff ff9e 	bl	1b44 <spm_config_peripheral.constprop.0>
	reset_ns = TZ_NONSECURE_FUNC_PTR_CREATE(vtor_ns[1]);
    1c08:	f024 0401 	bic.w	r4, r4, #1
  __ASM volatile ("dsb 0xF":::"memory");
    1c0c:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    1c10:	f3bf 8f6f 	isb	sy

		__DSB();
		__ISB();

		/* Jump to Non-Secure firmware */
		reset_ns();
    1c14:	0864      	lsrs	r4, r4, #1
    1c16:	0064      	lsls	r4, r4, #1
    1c18:	4620      	mov	r0, r4
    1c1a:	4621      	mov	r1, r4
    1c1c:	4622      	mov	r2, r4
    1c1e:	4623      	mov	r3, r4
    1c20:	eeb7 0a00 	vmov.f32	s0, #112	; 0x3f800000  1.0
    1c24:	eef7 0a00 	vmov.f32	s1, #112	; 0x3f800000  1.0
    1c28:	eeb7 1a00 	vmov.f32	s2, #112	; 0x3f800000  1.0
    1c2c:	eef7 1a00 	vmov.f32	s3, #112	; 0x3f800000  1.0
    1c30:	eeb7 2a00 	vmov.f32	s4, #112	; 0x3f800000  1.0
    1c34:	eef7 2a00 	vmov.f32	s5, #112	; 0x3f800000  1.0
    1c38:	eeb7 3a00 	vmov.f32	s6, #112	; 0x3f800000  1.0
    1c3c:	eef7 3a00 	vmov.f32	s7, #112	; 0x3f800000  1.0
    1c40:	eeb7 4a00 	vmov.f32	s8, #112	; 0x3f800000  1.0
    1c44:	eef7 4a00 	vmov.f32	s9, #112	; 0x3f800000  1.0
    1c48:	eeb7 5a00 	vmov.f32	s10, #112	; 0x3f800000  1.0
    1c4c:	eef7 5a00 	vmov.f32	s11, #112	; 0x3f800000  1.0
    1c50:	eeb7 6a00 	vmov.f32	s12, #112	; 0x3f800000  1.0
    1c54:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
    1c58:	eeb7 7a00 	vmov.f32	s14, #112	; 0x3f800000  1.0
    1c5c:	eef7 7a00 	vmov.f32	s15, #112	; 0x3f800000  1.0
    1c60:	f7fe fc7a 	bl	558 <__gnu_cmse_nonsecure_call>

		CODE_UNREACHABLE;
    1c64:	00006274 	.word	0x00006274
    1c68:	0000628b 	.word	0x0000628b
    1c6c:	000062a0 	.word	0x000062a0
    1c70:	000062be 	.word	0x000062be

00001c74 <spm_config>:
		      (uint32_t)reset_ns);
	}
}

void spm_config(void)
{
    1c74:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
	PRINT("Flash regions\t\tDomain\t\tPermissions\n");
    1c78:	483b      	ldr	r0, [pc, #236]	; (1d68 <spm_config+0xf4>)
    1c7a:	f003 fa59 	bl	5130 <printk>
	config_regions(false, 0, NON_SECURE_FLASH_REGION_INDEX,
    1c7e:	2100      	movs	r1, #0
    1c80:	f240 1317 	movw	r3, #279	; 0x117
    1c84:	4608      	mov	r0, r1
    1c86:	2201      	movs	r2, #1
    1c88:	f7ff ff00 	bl	1a8c <config_regions>
	config_regions(false, NON_SECURE_FLASH_REGION_INDEX,
    1c8c:	f240 1307 	movw	r3, #263	; 0x107
    1c90:	2220      	movs	r2, #32
    1c92:	2101      	movs	r1, #1
    1c94:	2000      	movs	r0, #0
    1c96:	f7ff fef9 	bl	1a8c <config_regions>
	PRINT("\n");
    1c9a:	4834      	ldr	r0, [pc, #208]	; (1d6c <spm_config+0xf8>)
    1c9c:	f003 fa48 	bl	5130 <printk>
	uint32_t nsc_size = FLASH_NSC_SIZE_FROM_ADDR(__sg_start);
    1ca0:	4b33      	ldr	r3, [pc, #204]	; (1d70 <spm_config+0xfc>)
                                            bool               lock_conf)
{
    NRFX_ASSERT(!(p_reg->FLASHNSC[flash_nsc_id].REGION & SPU_FLASHNSC_REGION_LOCK_Msk));
    NRFX_ASSERT(!(p_reg->FLASHNSC[flash_nsc_id].SIZE & SPU_FLASHNSC_SIZE_LOCK_Msk));

    p_reg->FLASHNSC[flash_nsc_id].REGION = (uint32_t)region_number |
    1ca2:	4a34      	ldr	r2, [pc, #208]	; (1d74 <spm_config+0x100>)
    1ca4:	f3c3 31c4 	ubfx	r1, r3, #15, #5
    1ca8:	f3c3 030e 	ubfx	r3, r3, #0, #15
    1cac:	f5c3 4300 	rsb	r3, r3, #32768	; 0x8000
        (lock_conf ? SPU_FLASHNSC_REGION_LOCK_Msk : 0);
    p_reg->FLASHNSC[flash_nsc_id].SIZE = (uint32_t)flash_nsc_size |
    1cb0:	f3c3 1343 	ubfx	r3, r3, #5, #4
    p_reg->FLASHNSC[flash_nsc_id].REGION = (uint32_t)region_number |
    1cb4:	f8c2 1500 	str.w	r1, [r2, #1280]	; 0x500
    p_reg->FLASHNSC[flash_nsc_id].SIZE = (uint32_t)flash_nsc_size |
    1cb8:	f8c2 3504 	str.w	r3, [r2, #1284]	; 0x504
	PRINT("Non-secure callable region 0 placed in flash region %d with size %d.\n",
    1cbc:	f8d2 1500 	ldr.w	r1, [r2, #1280]	; 0x500
    1cc0:	f8d2 2504 	ldr.w	r2, [r2, #1284]	; 0x504
    1cc4:	482c      	ldr	r0, [pc, #176]	; (1d78 <spm_config+0x104>)
    1cc6:	0152      	lsls	r2, r2, #5
    1cc8:	f003 fa32 	bl	5130 <printk>
	PRINT("\n");
    1ccc:	4827      	ldr	r0, [pc, #156]	; (1d6c <spm_config+0xf8>)
    1cce:	f003 fa2f 	bl	5130 <printk>
	int err = spm_secure_services_init();
    1cd2:	f003 fd01 	bl	56d8 <spm_secure_services_init>
	if (err != 0) {
    1cd6:	4601      	mov	r1, r0
    1cd8:	b110      	cbz	r0, 1ce0 <spm_config+0x6c>
		PRINT("Could not initialize secure services (err %d).\n", err);
    1cda:	4828      	ldr	r0, [pc, #160]	; (1d7c <spm_config+0x108>)
    1cdc:	f003 fa28 	bl	5130 <printk>
	NRF_SPU->DPPI[0].PERM = mask;
    1ce0:	2400      	movs	r4, #0
	PRINT("SRAM region\t\tDomain\t\tPermissions\n");
    1ce2:	4827      	ldr	r0, [pc, #156]	; (1d80 <spm_config+0x10c>)
    1ce4:	f003 fa24 	bl	5130 <printk>
	config_regions(true, 0, NON_SECURE_RAM_REGION_INDEX,
    1ce8:	f240 1317 	movw	r3, #279	; 0x117
    1cec:	2208      	movs	r2, #8
    1cee:	2100      	movs	r1, #0
    1cf0:	2001      	movs	r0, #1
    1cf2:	f7ff fecb 	bl	1a8c <config_regions>
	NRF_SPU->DPPI[0].PERM = mask;
    1cf6:	4d1f      	ldr	r5, [pc, #124]	; (1d74 <spm_config+0x100>)
	config_regions(true, NON_SECURE_RAM_REGION_INDEX,
    1cf8:	f240 1307 	movw	r3, #263	; 0x107
    1cfc:	2220      	movs	r2, #32
    1cfe:	2108      	movs	r1, #8
    1d00:	2001      	movs	r0, #1
    1d02:	f7ff fec3 	bl	1a8c <config_regions>
	PRINT("\n");
    1d06:	4819      	ldr	r0, [pc, #100]	; (1d6c <spm_config+0xf8>)
    1d08:	f003 fa12 	bl	5130 <printk>
	NRF_SPU->DPPI[0].PERM = mask;
    1d0c:	f8c5 4480 	str.w	r4, [r5, #1152]	; 0x480
	PRINT("Peripheral\t\tDomain\t\tStatus\n");
    1d10:	481c      	ldr	r0, [pc, #112]	; (1d84 <spm_config+0x110>)
    1d12:	f003 fa0d 	bl	5130 <printk>
		PRINT("%02u %-21s%s", i, periph[i].name,
    1d16:	4f1c      	ldr	r7, [pc, #112]	; (1d88 <spm_config+0x114>)
		NRF_SPU->GPIOPORT[0].PERM = 0;
    1d18:	f8c5 44c0 	str.w	r4, [r5, #1216]	; 0x4c0
		PRINT("%02u %-21s%s", i, periph[i].name,
    1d1c:	f8df 807c 	ldr.w	r8, [pc, #124]	; 1d9c <spm_config+0x128>
    1d20:	4d1a      	ldr	r5, [pc, #104]	; (1d8c <spm_config+0x118>)
    1d22:	f8df 907c 	ldr.w	r9, [pc, #124]	; 1da0 <spm_config+0x12c>
    1d26:	796e      	ldrb	r6, [r5, #5]
    1d28:	4621      	mov	r1, r4
    1d2a:	2e00      	cmp	r6, #0
    1d2c:	bf14      	ite	ne
    1d2e:	463b      	movne	r3, r7
    1d30:	4643      	moveq	r3, r8
    1d32:	4648      	mov	r0, r9
    1d34:	682a      	ldr	r2, [r5, #0]
    1d36:	f003 f9fb 	bl	5130 <printk>
		if (!periph[i].nonsecure) {
    1d3a:	b966      	cbnz	r6, 1d56 <spm_config+0xe2>
			PRINT("\tSKIP\n");
    1d3c:	4814      	ldr	r0, [pc, #80]	; (1d90 <spm_config+0x11c>)
	for (size_t i = 0; i < ARRAY_SIZE(periph); i++) {
    1d3e:	3401      	adds	r4, #1
			PRINT("\tOK\n");
    1d40:	f003 f9f6 	bl	5130 <printk>
	for (size_t i = 0; i < ARRAY_SIZE(periph); i++) {
    1d44:	2c1a      	cmp	r4, #26
    1d46:	f105 0508 	add.w	r5, r5, #8
    1d4a:	d1ec      	bne.n	1d26 <spm_config+0xb2>
	PRINT("\n");
    1d4c:	4807      	ldr	r0, [pc, #28]	; (1d6c <spm_config+0xf8>)
	spm_config_flash();
	spm_config_sram();
	spm_config_peripherals();
}
    1d4e:	e8bd 43f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
	PRINT("\n");
    1d52:	f003 b9ed 	b.w	5130 <printk>
		err = spm_config_peripheral(periph[i].id, false);
    1d56:	7928      	ldrb	r0, [r5, #4]
    1d58:	f7ff fef4 	bl	1b44 <spm_config_peripheral.constprop.0>
		if (err) {
    1d5c:	b108      	cbz	r0, 1d62 <spm_config+0xee>
			PRINT("\tERROR\n");
    1d5e:	480d      	ldr	r0, [pc, #52]	; (1d94 <spm_config+0x120>)
    1d60:	e7ed      	b.n	1d3e <spm_config+0xca>
			PRINT("\tOK\n");
    1d62:	480d      	ldr	r0, [pc, #52]	; (1d98 <spm_config+0x124>)
    1d64:	e7eb      	b.n	1d3e <spm_config+0xca>
    1d66:	bf00      	nop
    1d68:	000062f4 	.word	0x000062f4
    1d6c:	000065ac 	.word	0x000065ac
    1d70:	00007fe0 	.word	0x00007fe0
    1d74:	50003000 	.word	0x50003000
    1d78:	00006318 	.word	0x00006318
    1d7c:	0000635e 	.word	0x0000635e
    1d80:	0000638e 	.word	0x0000638e
    1d84:	000063b0 	.word	0x000063b0
    1d88:	000062e9 	.word	0x000062e9
    1d8c:	00005f88 	.word	0x00005f88
    1d90:	000063d9 	.word	0x000063d9
    1d94:	000063e0 	.word	0x000063e0
    1d98:	000063e8 	.word	0x000063e8
    1d9c:	0000624f 	.word	0x0000624f
    1da0:	000063cc 	.word	0x000063cc

00001da4 <__acle_se_spm_request_read_nse>:
};


__TZ_NONSECURE_ENTRY_FUNC
int spm_request_read_nse(void *destination, uint32_t addr, size_t len)
{
    1da4:	b570      	push	{r4, r5, r6, lr}
    1da6:	460c      	mov	r4, r1
    1da8:	4615      	mov	r5, r2
		 .size = FICR_PUBLIC_SIZE},
		{.start = FICR_RESTRICTED_ADDR,
		 .size = FICR_RESTRICTED_SIZE},
	};

	if (destination == NULL || len <= 0) {
    1daa:	4606      	mov	r6, r0
    1dac:	bbb0      	cbnz	r0, 1e1c <__acle_se_spm_request_read_nse+0x78>
		return -EINVAL;
    1dae:	f06f 0015 	mvn.w	r0, #21
			return 0;
		}
	}

	return -EPERM;
}
    1db2:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    1db6:	4671      	mov	r1, lr
    1db8:	4672      	mov	r2, lr
    1dba:	4673      	mov	r3, lr
    1dbc:	eeb7 0a00 	vmov.f32	s0, #112	; 0x3f800000  1.0
    1dc0:	eef7 0a00 	vmov.f32	s1, #112	; 0x3f800000  1.0
    1dc4:	eeb7 1a00 	vmov.f32	s2, #112	; 0x3f800000  1.0
    1dc8:	eef7 1a00 	vmov.f32	s3, #112	; 0x3f800000  1.0
    1dcc:	eeb7 2a00 	vmov.f32	s4, #112	; 0x3f800000  1.0
    1dd0:	eef7 2a00 	vmov.f32	s5, #112	; 0x3f800000  1.0
    1dd4:	eeb7 3a00 	vmov.f32	s6, #112	; 0x3f800000  1.0
    1dd8:	eef7 3a00 	vmov.f32	s7, #112	; 0x3f800000  1.0
    1ddc:	eeb7 4a00 	vmov.f32	s8, #112	; 0x3f800000  1.0
    1de0:	eef7 4a00 	vmov.f32	s9, #112	; 0x3f800000  1.0
    1de4:	eeb7 5a00 	vmov.f32	s10, #112	; 0x3f800000  1.0
    1de8:	eef7 5a00 	vmov.f32	s11, #112	; 0x3f800000  1.0
    1dec:	eeb7 6a00 	vmov.f32	s12, #112	; 0x3f800000  1.0
    1df0:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
    1df4:	eeb7 7a00 	vmov.f32	s14, #112	; 0x3f800000  1.0
    1df8:	eef7 7a00 	vmov.f32	s15, #112	; 0x3f800000  1.0
    1dfc:	f38e 8c00 	msr	CPSR_fs, lr
    1e00:	b410      	push	{r4}
    1e02:	eef1 ca10 	vmrs	ip, fpscr
    1e06:	f64f 7460 	movw	r4, #65376	; 0xff60
    1e0a:	f6c0 74ff 	movt	r4, #4095	; 0xfff
    1e0e:	ea0c 0c04 	and.w	ip, ip, r4
    1e12:	eee1 ca10 	vmsr	fpscr, ip
    1e16:	bc10      	pop	{r4}
    1e18:	46f4      	mov	ip, lr
    1e1a:	4774      	bxns	lr
	if (destination == NULL || len <= 0) {
    1e1c:	2a00      	cmp	r2, #0
    1e1e:	d0c6      	beq.n	1dae <__acle_se_spm_request_read_nse+0xa>
	return arm_cmse_addr_is_secure(ptr) == 1;
    1e20:	f003 fd1e 	bl	5860 <arm_cmse_addr_is_secure>
	if (ptr_in_secure_area((intptr_t)destination)) {
    1e24:	2801      	cmp	r0, #1
    1e26:	d0c2      	beq.n	1dae <__acle_se_spm_request_read_nse+0xa>
		if (addr >= start && addr + len <= start + size) {
    1e28:	4b0c      	ldr	r3, [pc, #48]	; (1e5c <__acle_se_spm_request_read_nse+0xb8>)
    1e2a:	429c      	cmp	r4, r3
    1e2c:	d90b      	bls.n	1e46 <__acle_se_spm_request_read_nse+0xa2>
    1e2e:	192a      	adds	r2, r5, r4
    1e30:	f603 231d 	addw	r3, r3, #2589	; 0xa1d
    1e34:	429a      	cmp	r2, r3
    1e36:	d809      	bhi.n	1e4c <__acle_se_spm_request_read_nse+0xa8>
			memcpy(destination, (const void *)addr, len);
    1e38:	462a      	mov	r2, r5
    1e3a:	4621      	mov	r1, r4
    1e3c:	4630      	mov	r0, r6
    1e3e:	f003 fd4b 	bl	58d8 <memcpy>
			return 0;
    1e42:	2000      	movs	r0, #0
    1e44:	e7b5      	b.n	1db2 <__acle_se_spm_request_read_nse+0xe>
		if (addr >= start && addr + len <= start + size) {
    1e46:	4b06      	ldr	r3, [pc, #24]	; (1e60 <__acle_se_spm_request_read_nse+0xbc>)
    1e48:	429c      	cmp	r4, r3
    1e4a:	d903      	bls.n	1e54 <__acle_se_spm_request_read_nse+0xb0>
    1e4c:	4b05      	ldr	r3, [pc, #20]	; (1e64 <__acle_se_spm_request_read_nse+0xc0>)
    1e4e:	192a      	adds	r2, r5, r4
    1e50:	429a      	cmp	r2, r3
    1e52:	d9f1      	bls.n	1e38 <__acle_se_spm_request_read_nse+0x94>
	return -EPERM;
    1e54:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
    1e58:	e7ab      	b.n	1db2 <__acle_se_spm_request_read_nse+0xe>
    1e5a:	bf00      	nop
    1e5c:	00ff0203 	.word	0x00ff0203
    1e60:	00ff012f 	.word	0x00ff012f
    1e64:	00ff0138 	.word	0x00ff0138

00001e68 <__acle_se_spm_firmware_info_nse>:
#endif /* CONFIG_SPM_SERVICE_S0_ACTIVE */

#ifdef CONFIG_SPM_SERVICE_FIND_FIRMWARE_INFO
__TZ_NONSECURE_ENTRY_FUNC
int spm_firmware_info_nse(uint32_t fw_address, struct fw_info *info)
{
    1e68:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    1e6c:	4681      	mov	r9, r0
	const struct fw_info *tmp_info;

	if (info == NULL) {
    1e6e:	460d      	mov	r5, r1
{
    1e70:	b085      	sub	sp, #20
	if (info == NULL) {
    1e72:	2900      	cmp	r1, #0
    1e74:	d05d      	beq.n	1f32 <__acle_se_spm_firmware_info_nse+0xca>
	return arm_cmse_addr_is_secure(ptr) == 1;
    1e76:	f003 fcf3 	bl	5860 <arm_cmse_addr_is_secure>
		return -EINVAL;
	}

	/* Ensure that fw_address is within secure area */
	if (!ptr_in_secure_area(fw_address)) {
    1e7a:	2801      	cmp	r0, #1
    1e7c:	d159      	bne.n	1f32 <__acle_se_spm_firmware_info_nse+0xca>
	return arm_cmse_addr_is_secure(ptr) == 1;
    1e7e:	4628      	mov	r0, r5
    1e80:	f003 fcee 	bl	5860 <arm_cmse_addr_is_secure>
		return -EINVAL;
	}

	/* Ensure that *info is in non-secure RAM */
	if (ptr_in_secure_area((intptr_t)info)) {
    1e84:	2801      	cmp	r0, #1
    1e86:	d054      	beq.n	1f32 <__acle_se_spm_firmware_info_nse+0xca>
 */
static inline const struct fw_info *fw_info_find(uint32_t firmware_address)
{
	const struct fw_info *finfo;

	for (uint32_t i = 0; i < FW_INFO_OFFSET_COUNT; i++) {
    1e88:	f04f 0800 	mov.w	r8, #0
    1e8c:	f8df b0b4 	ldr.w	fp, [pc, #180]	; 1f44 <__acle_se_spm_firmware_info_nse+0xdc>
	const uint32_t fw_info_magic[] = {FIRMWARE_INFO_MAGIC};
    1e90:	f8df a0b4 	ldr.w	sl, [pc, #180]	; 1f48 <__acle_se_spm_firmware_info_nse+0xe0>
    1e94:	af01      	add	r7, sp, #4
		finfo = fw_info_check(firmware_address +
						fw_info_allowed_offsets[i]);
    1e96:	f85b 6b04 	ldr.w	r6, [fp], #4
	const uint32_t fw_info_magic[] = {FIRMWARE_INFO_MAGIC};
    1e9a:	e89a 0007 	ldmia.w	sl, {r0, r1, r2}
		finfo = fw_info_check(firmware_address +
    1e9e:	444e      	add	r6, r9
	const uint32_t fw_info_magic[] = {FIRMWARE_INFO_MAGIC};
    1ea0:	e887 0007 	stmia.w	r7, {r0, r1, r2}
	if (memcmp(finfo->magic, fw_info_magic, CONFIG_FW_INFO_MAGIC_LEN)
    1ea4:	220c      	movs	r2, #12
    1ea6:	4639      	mov	r1, r7
    1ea8:	4630      	mov	r0, r6
    1eaa:	f003 fcee 	bl	588a <memcmp>
    1eae:	4604      	mov	r4, r0
    1eb0:	b908      	cbnz	r0, 1eb6 <__acle_se_spm_firmware_info_nse+0x4e>
		if (finfo) {
    1eb2:	2e00      	cmp	r6, #0
    1eb4:	d140      	bne.n	1f38 <__acle_se_spm_firmware_info_nse+0xd0>
	for (uint32_t i = 0; i < FW_INFO_OFFSET_COUNT; i++) {
    1eb6:	f108 0801 	add.w	r8, r8, #1
    1eba:	f1b8 0f05 	cmp.w	r8, #5
    1ebe:	d1ea      	bne.n	1e96 <__acle_se_spm_firmware_info_nse+0x2e>
	if (tmp_info != NULL) {
		memcpy(info, tmp_info, sizeof(*tmp_info));
		return 0;
	}

	return -EFAULT;
    1ec0:	f06f 040d 	mvn.w	r4, #13
}
    1ec4:	4620      	mov	r0, r4
    1ec6:	b005      	add	sp, #20
    1ec8:	eeb7 0a00 	vmov.f32	s0, #112	; 0x3f800000  1.0
    1ecc:	eef7 0a00 	vmov.f32	s1, #112	; 0x3f800000  1.0
    1ed0:	eeb7 1a00 	vmov.f32	s2, #112	; 0x3f800000  1.0
    1ed4:	eef7 1a00 	vmov.f32	s3, #112	; 0x3f800000  1.0
    1ed8:	eeb7 2a00 	vmov.f32	s4, #112	; 0x3f800000  1.0
    1edc:	eef7 2a00 	vmov.f32	s5, #112	; 0x3f800000  1.0
    1ee0:	eeb7 3a00 	vmov.f32	s6, #112	; 0x3f800000  1.0
    1ee4:	eef7 3a00 	vmov.f32	s7, #112	; 0x3f800000  1.0
    1ee8:	eeb7 4a00 	vmov.f32	s8, #112	; 0x3f800000  1.0
    1eec:	eef7 4a00 	vmov.f32	s9, #112	; 0x3f800000  1.0
    1ef0:	eeb7 5a00 	vmov.f32	s10, #112	; 0x3f800000  1.0
    1ef4:	eef7 5a00 	vmov.f32	s11, #112	; 0x3f800000  1.0
    1ef8:	eeb7 6a00 	vmov.f32	s12, #112	; 0x3f800000  1.0
    1efc:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
    1f00:	eeb7 7a00 	vmov.f32	s14, #112	; 0x3f800000  1.0
    1f04:	e8bd 4ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    1f08:	4671      	mov	r1, lr
    1f0a:	4672      	mov	r2, lr
    1f0c:	4673      	mov	r3, lr
    1f0e:	eef7 7a00 	vmov.f32	s15, #112	; 0x3f800000  1.0
    1f12:	f38e 8c00 	msr	CPSR_fs, lr
    1f16:	b410      	push	{r4}
    1f18:	eef1 ca10 	vmrs	ip, fpscr
    1f1c:	f64f 7460 	movw	r4, #65376	; 0xff60
    1f20:	f6c0 74ff 	movt	r4, #4095	; 0xfff
    1f24:	ea0c 0c04 	and.w	ip, ip, r4
    1f28:	eee1 ca10 	vmsr	fpscr, ip
    1f2c:	bc10      	pop	{r4}
    1f2e:	46f4      	mov	ip, lr
    1f30:	4774      	bxns	lr
		return -EINVAL;
    1f32:	f06f 0415 	mvn.w	r4, #21
    1f36:	e7c5      	b.n	1ec4 <__acle_se_spm_firmware_info_nse+0x5c>
		memcpy(info, tmp_info, sizeof(*tmp_info));
    1f38:	223c      	movs	r2, #60	; 0x3c
    1f3a:	4631      	mov	r1, r6
    1f3c:	4628      	mov	r0, r5
    1f3e:	f003 fccb 	bl	58d8 <memcpy>
		return 0;
    1f42:	e7bf      	b.n	1ec4 <__acle_se_spm_firmware_info_nse+0x5c>
    1f44:	00006058 	.word	0x00006058
    1f48:	00005f20 	.word	0x00005f20

00001f4c <nrf_cc3xx_platform_abort_init>:

/** @brief Function to initialize the nrf_cc3xx_platform abort APIs.
 */
void nrf_cc3xx_platform_abort_init(void)
{
	nrf_cc3xx_platform_set_abort(&apis);
    1f4c:	4801      	ldr	r0, [pc, #4]	; (1f54 <nrf_cc3xx_platform_abort_init+0x8>)
    1f4e:	f002 bbb5 	b.w	46bc <nrf_cc3xx_platform_set_abort>
    1f52:	bf00      	nop
    1f54:	0000606c 	.word	0x0000606c

00001f58 <mutex_unlock_platform>:
    }
}

/** @brief Static function to unlock a mutex
 */
static int32_t mutex_unlock_platform(nrf_cc3xx_platform_mutex_t *mutex) {
    1f58:	b508      	push	{r3, lr}
    struct k_mutex * p_mutex;

    /* Ensure that the mutex param is valid (not NULL) */
    if(mutex == NULL) {
    1f5a:	b1b0      	cbz	r0, 1f8a <mutex_unlock_platform+0x32>
        return NRF_CC3XX_PLATFORM_ERROR_PARAM_NULL;
    }

    switch (mutex->flags)
    1f5c:	6843      	ldr	r3, [r0, #4]
    1f5e:	2b04      	cmp	r3, #4
    1f60:	d10d      	bne.n	1f7e <mutex_unlock_platform+0x26>
	return __atomic_compare_exchange_n(target, &old_value, new_value,
    1f62:	2200      	movs	r2, #0
    1f64:	6803      	ldr	r3, [r0, #0]
    1f66:	e8d3 1fef 	ldaex	r1, [r3]
    1f6a:	2901      	cmp	r1, #1
    1f6c:	d103      	bne.n	1f76 <mutex_unlock_platform+0x1e>
    1f6e:	e8c3 2fe0 	stlex	r0, r2, [r3]
    1f72:	2800      	cmp	r0, #0
    1f74:	d1f7      	bne.n	1f66 <mutex_unlock_platform+0xe>
    {
    case NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ATOMIC:
        return atomic_cas((atomic_t *)mutex->mutex, 1, 0) ?
                       NRF_CC3XX_PLATFORM_SUCCESS :
    1f76:	4807      	ldr	r0, [pc, #28]	; (1f94 <mutex_unlock_platform+0x3c>)
    1f78:	bf08      	it	eq
    1f7a:	4610      	moveq	r0, r2
        p_mutex = (struct k_mutex *)mutex->mutex;

        k_mutex_unlock(p_mutex);
        return NRF_CC3XX_PLATFORM_SUCCESS;
    }
}
    1f7c:	bd08      	pop	{r3, pc}
        if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID) {
    1f7e:	b13b      	cbz	r3, 1f90 <mutex_unlock_platform+0x38>
        p_mutex = (struct k_mutex *)mutex->mutex;
    1f80:	6800      	ldr	r0, [r0, #0]
	return z_impl_k_mutex_unlock(mutex);
    1f82:	f001 fb07 	bl	3594 <z_impl_k_mutex_unlock>
        return NRF_CC3XX_PLATFORM_SUCCESS;
    1f86:	2000      	movs	r0, #0
    1f88:	e7f8      	b.n	1f7c <mutex_unlock_platform+0x24>
        return NRF_CC3XX_PLATFORM_ERROR_PARAM_NULL;
    1f8a:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    1f8e:	e7f5      	b.n	1f7c <mutex_unlock_platform+0x24>
            return NRF_CC3XX_PLATFORM_ERROR_MUTEX_NOT_INITIALIZED;
    1f90:	4801      	ldr	r0, [pc, #4]	; (1f98 <mutex_unlock_platform+0x40>)
    1f92:	e7f3      	b.n	1f7c <mutex_unlock_platform+0x24>
    1f94:	ffff8fe9 	.word	0xffff8fe9
    1f98:	ffff8fea 	.word	0xffff8fea

00001f9c <mutex_free_platform>:
static void mutex_free_platform(nrf_cc3xx_platform_mutex_t *mutex) {
    1f9c:	b510      	push	{r4, lr}
    if (mutex == NULL) {
    1f9e:	4604      	mov	r4, r0
    1fa0:	b918      	cbnz	r0, 1faa <mutex_free_platform+0xe>
        platform_abort_apis.abort_fn(
    1fa2:	4b0d      	ldr	r3, [pc, #52]	; (1fd8 <mutex_free_platform+0x3c>)
    1fa4:	480d      	ldr	r0, [pc, #52]	; (1fdc <mutex_free_platform+0x40>)
    1fa6:	685b      	ldr	r3, [r3, #4]
    1fa8:	4798      	blx	r3
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ATOMIC ||
    1faa:	6861      	ldr	r1, [r4, #4]
    1fac:	2908      	cmp	r1, #8
    1fae:	d00d      	beq.n	1fcc <mutex_free_platform+0x30>
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID) {
    1fb0:	f031 0304 	bics.w	r3, r1, #4
    1fb4:	d00a      	beq.n	1fcc <mutex_free_platform+0x30>
    if ((mutex->flags & NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ALLOCATED) != 0) {
    1fb6:	f011 0102 	ands.w	r1, r1, #2
    1fba:	d008      	beq.n	1fce <mutex_free_platform+0x32>
        k_mem_slab_free(&mutex_slab, &mutex->mutex);
    1fbc:	4621      	mov	r1, r4
    1fbe:	4808      	ldr	r0, [pc, #32]	; (1fe0 <mutex_free_platform+0x44>)
    1fc0:	f001 fa46 	bl	3450 <k_mem_slab_free>
        mutex->mutex = NULL;
    1fc4:	2300      	movs	r3, #0
    1fc6:	6023      	str	r3, [r4, #0]
    mutex->flags = NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID;
    1fc8:	2300      	movs	r3, #0
    1fca:	6063      	str	r3, [r4, #4]
}
    1fcc:	bd10      	pop	{r4, pc}
        memset(mutex->mutex, 0, sizeof(struct k_mutex));
    1fce:	2214      	movs	r2, #20
    1fd0:	6820      	ldr	r0, [r4, #0]
    1fd2:	f003 fcac 	bl	592e <memset>
    1fd6:	e7f7      	b.n	1fc8 <mutex_free_platform+0x2c>
    1fd8:	20000044 	.word	0x20000044
    1fdc:	000064e9 	.word	0x000064e9
    1fe0:	200002a8 	.word	0x200002a8

00001fe4 <mutex_init_platform>:
static void mutex_init_platform(nrf_cc3xx_platform_mutex_t *mutex) {
    1fe4:	b510      	push	{r4, lr}
    if (mutex == NULL) {
    1fe6:	4604      	mov	r4, r0
    1fe8:	b918      	cbnz	r0, 1ff2 <mutex_init_platform+0xe>
        platform_abort_apis.abort_fn(
    1fea:	4b16      	ldr	r3, [pc, #88]	; (2044 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x44>)
    1fec:	4816      	ldr	r0, [pc, #88]	; (2048 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x48>)
    1fee:	685b      	ldr	r3, [r3, #4]
    1ff0:	4798      	blx	r3
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ATOMIC ||
    1ff2:	6863      	ldr	r3, [r4, #4]
    1ff4:	2b04      	cmp	r3, #4
    1ff6:	d023      	beq.n	2040 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x40>
    1ff8:	2b08      	cmp	r3, #8
    1ffa:	d021      	beq.n	2040 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x40>
    if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID &&
    1ffc:	b9cb      	cbnz	r3, 2032 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x32>
    1ffe:	6823      	ldr	r3, [r4, #0]
    2000:	b9bb      	cbnz	r3, 2032 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x32>
        ret = k_mem_slab_alloc(&mutex_slab, &mutex->mutex, K_FOREVER);
    2002:	f04f 32ff 	mov.w	r2, #4294967295	; 0xffffffff
    2006:	f04f 33ff 	mov.w	r3, #4294967295	; 0xffffffff
    200a:	4621      	mov	r1, r4
    200c:	480f      	ldr	r0, [pc, #60]	; (204c <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x4c>)
    200e:	f001 f9ed 	bl	33ec <k_mem_slab_alloc>
        if(ret != 0 || mutex->mutex == NULL)
    2012:	b908      	cbnz	r0, 2018 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x18>
    2014:	6823      	ldr	r3, [r4, #0]
    2016:	b91b      	cbnz	r3, 2020 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x20>
            platform_abort_apis.abort_fn(
    2018:	4b0a      	ldr	r3, [pc, #40]	; (2044 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x44>)
    201a:	480d      	ldr	r0, [pc, #52]	; (2050 <CONFIG_NRF_SPU_RAM_REGION_SIZE+0x50>)
    201c:	685b      	ldr	r3, [r3, #4]
    201e:	4798      	blx	r3
        memset(mutex->mutex, 0, sizeof(struct k_mutex));
    2020:	2214      	movs	r2, #20
    2022:	2100      	movs	r1, #0
    2024:	6820      	ldr	r0, [r4, #0]
    2026:	f003 fc82 	bl	592e <memset>
        mutex->flags |= NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_ALLOCATED;
    202a:	6863      	ldr	r3, [r4, #4]
    202c:	f043 0302 	orr.w	r3, r3, #2
    2030:	6063      	str	r3, [r4, #4]
    p_mutex = (struct k_mutex *)mutex->mutex;
    2032:	6820      	ldr	r0, [r4, #0]
	return z_impl_k_mutex_init(mutex);
    2034:	f003 fd3d 	bl	5ab2 <z_impl_k_mutex_init>
    mutex->flags |= NRF_CC3XX_PLATFORM_MUTEX_MASK_IS_VALID;
    2038:	6863      	ldr	r3, [r4, #4]
    203a:	f043 0301 	orr.w	r3, r3, #1
    203e:	6063      	str	r3, [r4, #4]
}
    2040:	bd10      	pop	{r4, pc}
    2042:	bf00      	nop
    2044:	20000044 	.word	0x20000044
    2048:	000064e9 	.word	0x000064e9
    204c:	200002a8 	.word	0x200002a8
    2050:	0000650f 	.word	0x0000650f

00002054 <mutex_lock_platform>:
static int32_t mutex_lock_platform(nrf_cc3xx_platform_mutex_t *mutex) {
    2054:	b508      	push	{r3, lr}
    if(mutex == NULL) {
    2056:	b1e8      	cbz	r0, 2094 <mutex_lock_platform+0x40>
    switch (mutex->flags) {
    2058:	6843      	ldr	r3, [r0, #4]
    205a:	2b04      	cmp	r3, #4
    205c:	d10c      	bne.n	2078 <mutex_lock_platform+0x24>
    205e:	2201      	movs	r2, #1
    2060:	6803      	ldr	r3, [r0, #0]
    2062:	e8d3 1fef 	ldaex	r1, [r3]
    2066:	2900      	cmp	r1, #0
    2068:	d103      	bne.n	2072 <mutex_lock_platform+0x1e>
    206a:	e8c3 2fe0 	stlex	r0, r2, [r3]
    206e:	2800      	cmp	r0, #0
    2070:	d1f7      	bne.n	2062 <mutex_lock_platform+0xe>
                       NRF_CC3XX_PLATFORM_SUCCESS :
    2072:	d10b      	bne.n	208c <mutex_lock_platform+0x38>
    2074:	2000      	movs	r0, #0
}
    2076:	bd08      	pop	{r3, pc}
        if (mutex->flags == NRF_CC3XX_PLATFORM_MUTEX_MASK_INVALID) {
    2078:	b153      	cbz	r3, 2090 <mutex_lock_platform+0x3c>
        p_mutex = (struct k_mutex *)mutex->mutex;
    207a:	6800      	ldr	r0, [r0, #0]
	return z_impl_k_mutex_lock(mutex, timeout);
    207c:	f04f 32ff 	mov.w	r2, #4294967295	; 0xffffffff
    2080:	f04f 33ff 	mov.w	r3, #4294967295	; 0xffffffff
    2084:	f001 fa0e 	bl	34a4 <z_impl_k_mutex_lock>
        if (ret == 0) {
    2088:	2800      	cmp	r0, #0
    208a:	d0f3      	beq.n	2074 <mutex_lock_platform+0x20>
                       NRF_CC3XX_PLATFORM_SUCCESS :
    208c:	4803      	ldr	r0, [pc, #12]	; (209c <mutex_lock_platform+0x48>)
    208e:	e7f2      	b.n	2076 <mutex_lock_platform+0x22>
            return NRF_CC3XX_PLATFORM_ERROR_MUTEX_NOT_INITIALIZED;
    2090:	4803      	ldr	r0, [pc, #12]	; (20a0 <mutex_lock_platform+0x4c>)
    2092:	e7f0      	b.n	2076 <mutex_lock_platform+0x22>
        return NRF_CC3XX_PLATFORM_ERROR_PARAM_NULL;
    2094:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    2098:	e7ed      	b.n	2076 <mutex_lock_platform+0x22>
    209a:	bf00      	nop
    209c:	ffff8fe9 	.word	0xffff8fe9
    20a0:	ffff8fea 	.word	0xffff8fea

000020a4 <nrf_cc3xx_platform_mutex_init>:
};

/** @brief Function to initialize the nrf_cc3xx_platform mutex APIs
 */
void nrf_cc3xx_platform_mutex_init(void)
{
    20a4:	b508      	push	{r3, lr}
    k_mem_slab_init(&mutex_slab,
    20a6:	4906      	ldr	r1, [pc, #24]	; (20c0 <nrf_cc3xx_platform_mutex_init+0x1c>)
    20a8:	2340      	movs	r3, #64	; 0x40
    20aa:	2214      	movs	r2, #20
    20ac:	4805      	ldr	r0, [pc, #20]	; (20c4 <nrf_cc3xx_platform_mutex_init+0x20>)
    20ae:	f003 fce5 	bl	5a7c <k_mem_slab_init>
                mutex_slab_buffer,
                sizeof(struct k_mutex),
                NUM_MUTEXES);

    nrf_cc3xx_platform_set_mutexes(&mutex_apis, &mutexes);
}
    20b2:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    nrf_cc3xx_platform_set_mutexes(&mutex_apis, &mutexes);
    20b6:	4904      	ldr	r1, [pc, #16]	; (20c8 <nrf_cc3xx_platform_mutex_init+0x24>)
    20b8:	4804      	ldr	r0, [pc, #16]	; (20cc <nrf_cc3xx_platform_mutex_init+0x28>)
    20ba:	f002 bb51 	b.w	4760 <nrf_cc3xx_platform_set_mutexes>
    20be:	bf00      	nop
    20c0:	200002c4 	.word	0x200002c4
    20c4:	200002a8 	.word	0x200002a8
    20c8:	00006084 	.word	0x00006084
    20cc:	00006074 	.word	0x00006074

000020d0 <arch_swap>:
 * as BASEPRI is not available.
 */
int arch_swap(unsigned int key)
{
	/* store off key and return value */
	_current->arch.basepri = key;
    20d0:	4a09      	ldr	r2, [pc, #36]	; (20f8 <arch_swap+0x28>)
	_current->arch.swap_return_value = _k_neg_eagain;
    20d2:	490a      	ldr	r1, [pc, #40]	; (20fc <arch_swap+0x2c>)
	_current->arch.basepri = key;
    20d4:	6893      	ldr	r3, [r2, #8]
	_current->arch.swap_return_value = _k_neg_eagain;
    20d6:	6809      	ldr	r1, [r1, #0]
	_current->arch.basepri = key;
    20d8:	6798      	str	r0, [r3, #120]	; 0x78
	_current->arch.swap_return_value = _k_neg_eagain;
    20da:	67d9      	str	r1, [r3, #124]	; 0x7c

#if defined(CONFIG_CPU_CORTEX_M)
	/* set pending bit to make sure we will take a PendSV exception */
	SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    20dc:	4908      	ldr	r1, [pc, #32]	; (2100 <arch_swap+0x30>)
    20de:	684b      	ldr	r3, [r1, #4]
    20e0:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
    20e4:	604b      	str	r3, [r1, #4]
    20e6:	2300      	movs	r3, #0
    20e8:	f383 8811 	msr	BASEPRI, r3
    20ec:	f3bf 8f6f 	isb	sy
#endif

	/* Context switch is performed here. Returning implies the
	 * thread has been context-switched-in again.
	 */
	return _current->arch.swap_return_value;
    20f0:	6893      	ldr	r3, [r2, #8]
}
    20f2:	6fd8      	ldr	r0, [r3, #124]	; 0x7c
    20f4:	4770      	bx	lr
    20f6:	bf00      	nop
    20f8:	2000084c 	.word	0x2000084c
    20fc:	000060fc 	.word	0x000060fc
    2100:	e000ed00 	.word	0xe000ed00

00002104 <z_arm_pendsv>:
    pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_TRACING */

    /* load _kernel into r1 and current k_thread into r2 */
    ldr r1, =_kernel
    2104:	4913      	ldr	r1, [pc, #76]	; (2154 <z_arm_pendsv+0x50>)
    ldr r2, [r1, #_kernel_offset_to_current]
    2106:	688a      	ldr	r2, [r1, #8]

    /* addr of callee-saved regs in thread in r0 */
    ldr r0, =_thread_offset_to_callee_saved
    2108:	f04f 0038 	mov.w	r0, #56	; 0x38
    add r0, r2
    210c:	4410      	add	r0, r2

    /* save callee-saved + psp in thread */
#if defined(CONFIG_CPU_CORTEX_M)
    mrs ip, PSP
    210e:	f3ef 8c09 	mrs	ip, PSP
    mov r6, r11
    mov r7, ip
    /* store r8-12 */
    stmea r0!, {r3-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    stmia r0, {v1-v8, ip}
    2112:	e880 1ff0 	stmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}

    /* Protect the kernel state while we play with the thread lists */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    2116:	2020      	movs	r0, #32
    msr BASEPRI, r0
    2118:	f380 8811 	msr	BASEPRI, r0
    isb /* Make the effect of disabling interrupts be realized immediately */
    211c:	f3bf 8f6f 	isb	sy
     * the new thread is context-switched in since all decisions
     * to pend PendSV have been taken with the current kernel
     * state and this is what we're handling currently.
     */
#if defined(CONFIG_CPU_CORTEX_M)
    ldr v4, =_SCS_ICSR
    2120:	4f0d      	ldr	r7, [pc, #52]	; (2158 <z_arm_pendsv+0x54>)
    ldr v3, =_SCS_ICSR_UNPENDSV
    2122:	f04f 6600 	mov.w	r6, #134217728	; 0x8000000
#endif

    /* _kernel is still in r1 */

    /* fetch the thread to run from the ready queue cache */
    ldr r2, [r1, #_kernel_offset_to_ready_q_cache]
    2126:	6a8a      	ldr	r2, [r1, #40]	; 0x28

    str r2, [r1, #_kernel_offset_to_current]
    2128:	608a      	str	r2, [r1, #8]
     * has been handled.
     */

    /* _SCS_ICSR is still in v4 and _SCS_ICSR_UNPENDSV in v3 */
#if defined(CONFIG_CPU_CORTEX_M)
    str v3, [v4, #0]
    212a:	603e      	str	r6, [r7, #0]

    ldr r0, [r4]
    movs.n r3, #0
    str r3, [r4]
#else
    ldr r0, [r2, #_thread_offset_to_basepri]
    212c:	6f90      	ldr	r0, [r2, #120]	; 0x78
    movs r3, #0
    212e:	2300      	movs	r3, #0
    str r3, [r2, #_thread_offset_to_basepri]
    2130:	6793      	str	r3, [r2, #120]	; 0x78
    /* restore r4-r7, go back 9*4 bytes to the start of the stored block */
    subs r0, #36
    ldmia r0!, {r4-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    /* restore BASEPRI for the incoming thread */
    msr BASEPRI, r0
    2132:	f380 8811 	msr	BASEPRI, r0
    isb

#endif

    /* load callee-saved + psp from thread */
    add r0, r2, #_thread_offset_to_callee_saved
    2136:	f102 0038 	add.w	r0, r2, #56	; 0x38
    ldmia r0, {v1-v8, ip}
    213a:	e890 1ff0 	ldmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
    msr PSP, ip
    213e:	f38c 8809 	msr	PSP, ip
#endif

#ifdef CONFIG_BUILTIN_STACK_GUARD
    /* r2 contains k_thread */
    add r0, r2, #0
    2142:	f102 0000 	add.w	r0, r2, #0
    push {r2, lr}
    2146:	b504      	push	{r2, lr}
    bl configure_builtin_stack_guard
    2148:	f003 fb52 	bl	57f0 <configure_builtin_stack_guard>
    pop {r2, lr}
    214c:	e8bd 4004 	ldmia.w	sp!, {r2, lr}

    /*
     * Cortex-M: return from PendSV exception
     * Cortex-R: return to the caller (_IntExit or z_arm_svc)
     */
    bx lr
    2150:	4770      	bx	lr
    2152:	0000      	.short	0x0000
    ldr r1, =_kernel
    2154:	2000084c 	.word	0x2000084c
    ldr v4, =_SCS_ICSR
    2158:	e000ed04 	.word	0xe000ed04

0000215c <z_arm_svc>:
  bne _stack_frame_endif
_stack_frame_msp:
  mrs r0, MSP
_stack_frame_endif:
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    tst lr, #0x4    /* did we come from thread mode ? */
    215c:	f01e 0f04 	tst.w	lr, #4
    ite eq  /* if zero (equal), came from handler mode */
    2160:	bf0c      	ite	eq
        mrseq r0, MSP   /* handler mode, stack frame is on MSP */
    2162:	f3ef 8008 	mrseq	r0, MSP
        mrsne r0, PSP   /* thread mode, stack frame is on PSP */
    2166:	f3ef 8009 	mrsne	r0, PSP
#endif


    /* Figure out what SVC call number was invoked */

    ldr r1, [r0, #24]   /* grab address of PC from stack frame */
    216a:	6981      	ldr	r1, [r0, #24]
     */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    subs r1, r1, #2
    ldrb r1, [r1]
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    ldrb r1, [r1, #-2]
    216c:	f811 1c02 	ldrb.w	r1, [r1, #-2]
#endif
    bne _oops

#endif /* CONFIG_USERSPACE */

    cmp r1, #2
    2170:	2902      	cmp	r1, #2
    beq _oops
    2172:	d0ff      	beq.n	2174 <_oops>

00002174 <_oops>:
    /* exception return is done in z_arm_int_exit() */
    b z_arm_int_exit
#endif

_oops:
    push {r0, lr}
    2174:	b501      	push	{r0, lr}
    bl z_do_kernel_oops
    2176:	f003 fb41 	bl	57fc <z_do_kernel_oops>
    /* return from SVC exception is done here */
    pop {r0, pc}
    217a:	bd01      	pop	{r0, pc}

0000217c <arch_irq_enable>:
#define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
#define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)

void arch_irq_enable(unsigned int irq)
{
	NVIC_EnableIRQ((IRQn_Type)irq);
    217c:	b243      	sxtb	r3, r0
  if ((int32_t)(IRQn) >= 0)
    217e:	2b00      	cmp	r3, #0
    2180:	db08      	blt.n	2194 <arch_irq_enable+0x18>
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    2182:	2201      	movs	r2, #1
    2184:	f000 001f 	and.w	r0, r0, #31
    2188:	fa02 f000 	lsl.w	r0, r2, r0
    218c:	4a02      	ldr	r2, [pc, #8]	; (2198 <arch_irq_enable+0x1c>)
    218e:	095b      	lsrs	r3, r3, #5
    2190:	f842 0023 	str.w	r0, [r2, r3, lsl #2]
}
    2194:	4770      	bx	lr
    2196:	bf00      	nop
    2198:	e000e100 	.word	0xe000e100

0000219c <arch_irq_is_enabled>:
	NVIC_DisableIRQ((IRQn_Type)irq);
}

int arch_irq_is_enabled(unsigned int irq)
{
	return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq));
    219c:	4b05      	ldr	r3, [pc, #20]	; (21b4 <arch_irq_is_enabled+0x18>)
    219e:	0942      	lsrs	r2, r0, #5
    21a0:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
    21a4:	2301      	movs	r3, #1
    21a6:	f000 001f 	and.w	r0, r0, #31
    21aa:	fa03 f000 	lsl.w	r0, r3, r0
}
    21ae:	4010      	ands	r0, r2
    21b0:	4770      	bx	lr
    21b2:	bf00      	nop
    21b4:	e000e100 	.word	0xe000e100

000021b8 <z_arm_irq_priority_set>:
	 */
	__ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1),
		 "invalid priority %d! values must be less than %lu\n",
		 prio - _IRQ_PRIO_OFFSET,
		 BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
	NVIC_SetPriority((IRQn_Type)irq, prio);
    21b8:	b243      	sxtb	r3, r0
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
  if ((int32_t)(IRQn) >= 0)
    21ba:	2b00      	cmp	r3, #0
	prio += _IRQ_PRIO_OFFSET;
    21bc:	f101 0101 	add.w	r1, r1, #1
  {
    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    21c0:	bfac      	ite	ge
    21c2:	f103 4360 	addge.w	r3, r3, #3758096384	; 0xe0000000
  }
  else
  {
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    21c6:	4b06      	ldrlt	r3, [pc, #24]	; (21e0 <z_arm_irq_priority_set+0x28>)
    21c8:	ea4f 1141 	mov.w	r1, r1, lsl #5
    21cc:	b2c9      	uxtb	r1, r1
    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    21ce:	bfab      	itete	ge
    21d0:	f503 4361 	addge.w	r3, r3, #57600	; 0xe100
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    21d4:	f000 000f 	andlt.w	r0, r0, #15
    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    21d8:	f883 1300 	strbge.w	r1, [r3, #768]	; 0x300
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    21dc:	5419      	strblt	r1, [r3, r0]
}
    21de:	4770      	bx	lr
    21e0:	e000ed14 	.word	0xe000ed14

000021e4 <arch_new_thread>:

#if defined(CONFIG_CPU_CORTEX_M)
	/* force ARM mode by clearing LSB of address */
	iframe->pc &= 0xfffffffe;
#endif
	iframe->a1 = (uint32_t)entry;
    21e4:	f842 3c20 	str.w	r3, [r2, #-32]
	iframe->a2 = (uint32_t)p1;
    21e8:	9b00      	ldr	r3, [sp, #0]
	iframe->pc &= 0xfffffffe;
    21ea:	490b      	ldr	r1, [pc, #44]	; (2218 <arch_new_thread+0x34>)
	iframe->a2 = (uint32_t)p1;
    21ec:	f842 3c1c 	str.w	r3, [r2, #-28]
	iframe->a3 = (uint32_t)p2;
    21f0:	9b01      	ldr	r3, [sp, #4]
	iframe->pc &= 0xfffffffe;
    21f2:	f021 0101 	bic.w	r1, r1, #1
	iframe->a3 = (uint32_t)p2;
    21f6:	f842 3c18 	str.w	r3, [r2, #-24]
	iframe->a4 = (uint32_t)p3;
    21fa:	9b02      	ldr	r3, [sp, #8]
	iframe->pc &= 0xfffffffe;
    21fc:	f842 1c08 	str.w	r1, [r2, #-8]
	iframe->a4 = (uint32_t)p3;
    2200:	f842 3c14 	str.w	r3, [r2, #-20]

#if defined(CONFIG_CPU_CORTEX_M)
	iframe->xpsr =
    2204:	f04f 7380 	mov.w	r3, #16777216	; 0x1000000
    2208:	f842 3c04 	str.w	r3, [r2, #-4]
	iframe->xpsr |= T_BIT;
#endif /* CONFIG_COMPILER_ISA_THUMB2 */
#endif /* CONFIG_CPU_CORTEX_M */

	thread->callee_saved.psp = (uint32_t)iframe;
	thread->arch.basepri = 0;
    220c:	2300      	movs	r3, #0
	iframe = Z_STACK_PTR_TO_FRAME(struct __basic_sf, stack_ptr);
    220e:	3a20      	subs	r2, #32
	thread->callee_saved.psp = (uint32_t)iframe;
    2210:	6582      	str	r2, [r0, #88]	; 0x58
	thread->arch.basepri = 0;
    2212:	6783      	str	r3, [r0, #120]	; 0x78
#endif
	/*
	 * initial values in all other registers/thread entries are
	 * irrelevant.
	 */
}
    2214:	4770      	bx	lr
    2216:	bf00      	nop
    2218:	000052a3 	.word	0x000052a3

0000221c <arch_switch_to_main_thread>:
#endif
}

void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr,
				k_thread_entry_t _main)
{
    221c:	b508      	push	{r3, lr}
    221e:	4604      	mov	r4, r0
    2220:	460e      	mov	r6, r1
    2222:	4615      	mov	r5, r2
  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
    2224:	2300      	movs	r3, #0
    2226:	eee1 3a10 	vmsr	fpscr, r3
	z_arm_configure_static_mpu_regions();
    222a:	f000 fa07 	bl	263c <z_arm_configure_static_mpu_regions>
	z_arm_prepare_switch_to_main();

	_current = main_thread;
    222e:	4b09      	ldr	r3, [pc, #36]	; (2254 <arch_switch_to_main_thread+0x38>)
    2230:	609c      	str	r4, [r3, #8]
  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
    2232:	6ea3      	ldr	r3, [r4, #104]	; 0x68
    2234:	f383 880b 	msr	PSPLIM, r3

	/*
	 * Set PSP to the highest address of the main stack
	 * before enabling interrupts and jumping to main.
	 */
	__asm__ volatile (
    2238:	4628      	mov	r0, r5
    223a:	f386 8809 	msr	PSP, r6
    223e:	2100      	movs	r1, #0
    2240:	b663      	cpsie	if
    2242:	f381 8811 	msr	BASEPRI, r1
    2246:	f3bf 8f6f 	isb	sy
    224a:	2200      	movs	r2, #0
    224c:	2300      	movs	r3, #0
    224e:	f003 f828 	bl	52a2 <z_thread_entry>
	:
	: "r" (_main), "r" (stack_ptr)
	: "r0" /* not to be overwritten by msr PSP, %1 */
	);

	CODE_UNREACHABLE;
    2252:	bf00      	nop
    2254:	2000084c 	.word	0x2000084c

00002258 <z_arm_cpu_idle_init>:
 * void z_arm_cpu_idle_init(void);
 */

SECTION_FUNC(TEXT, z_arm_cpu_idle_init)
#if defined(CONFIG_CPU_CORTEX_M)
	ldr	r1, =_SCB_SCR
    2258:	4901      	ldr	r1, [pc, #4]	; (2260 <z_arm_cpu_idle_init+0x8>)
	movs.n	r2, #_SCR_INIT_BITS
    225a:	2210      	movs	r2, #16
	str	r2, [r1]
    225c:	600a      	str	r2, [r1, #0]
#endif
	bx	lr
    225e:	4770      	bx	lr
	ldr	r1, =_SCB_SCR
    2260:	e000ed10 	.word	0xe000ed10

00002264 <arch_cpu_idle>:
	 * before entering low power state.
	 *
	 * Set PRIMASK before configuring BASEPRI to prevent interruption
	 * before wake-up.
	 */
	cpsid	i
    2264:	b672      	cpsid	i

	/*
	 * Set wake-up interrupt priority to the lowest and synchronise to
	 * ensure that this is visible to the WFI instruction.
	 */
	eors.n	r0, r0
    2266:	4040      	eors	r0, r0
	msr	BASEPRI, r0
    2268:	f380 8811 	msr	BASEPRI, r0
	isb
    226c:	f3bf 8f6f 	isb	sy

	/*
	 * Wait for all memory transactions to complete before entering low
	 * power state.
	 */
	dsb
    2270:	f3bf 8f4f 	dsb	sy

	/* Enter low power state */
	wfi
    2274:	bf30      	wfi

	/*
	 * Clear PRIMASK and flush instruction buffer to immediately service
	 * the wake-up interrupt.
	 */
	cpsie	i
    2276:	b662      	cpsie	i
	isb
    2278:	f3bf 8f6f 	isb	sy

	bx	lr
    227c:	4770      	bx	lr
    227e:	bf00      	nop

00002280 <arch_cpu_atomic_idle>:

	/*
	 * Lock PRIMASK while sleeping: wfe will still get interrupted by
	 * incoming interrupts but the CPU will not service them right away.
	 */
	cpsid	i
    2280:	b672      	cpsid	i
	cpsie	i
_irq_disabled:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* r1: zero, for setting BASEPRI (needs a register) */
	eors.n	r1, r1
    2282:	4049      	eors	r1, r1

	/* unlock BASEPRI so wfe gets interrupted by incoming interrupts */
	msr	BASEPRI, r1
    2284:	f381 8811 	msr	BASEPRI, r1

	wfe
    2288:	bf20      	wfe

	msr	BASEPRI, r0
    228a:	f380 8811 	msr	BASEPRI, r0
	cpsie	i
    228e:	b662      	cpsie	i
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
	bx	lr
    2290:	4770      	bx	lr
    2292:	bf00      	nop

00002294 <z_SysNmiOnReset>:
_ASM_FILE_PROLOGUE

GTEXT(z_SysNmiOnReset)

SECTION_FUNC(TEXT, z_SysNmiOnReset)
    wfi
    2294:	bf30      	wfi
    b z_SysNmiOnReset
    2296:	f7ff bffd 	b.w	2294 <z_SysNmiOnReset>
    229a:	bf00      	nop

0000229c <z_arm_prep_c>:
#else
#define VECTOR_ADDRESS CONFIG_SRAM_BASE_ADDRESS
#endif
static inline void relocate_vector_table(void)
{
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    229c:	4a17      	ldr	r2, [pc, #92]	; (22fc <z_arm_prep_c+0x60>)
 * This routine prepares for the execution of and runs C code.
 *
 * @return N/A
 */
void z_arm_prep_c(void)
{
    229e:	b508      	push	{r3, lr}
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    22a0:	4b17      	ldr	r3, [pc, #92]	; (2300 <z_arm_prep_c+0x64>)
    22a2:	f022 027f 	bic.w	r2, r2, #127	; 0x7f
    22a6:	609a      	str	r2, [r3, #8]
  __ASM volatile ("dsb 0xF":::"memory");
    22a8:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    22ac:	f3bf 8f6f 	isb	sy
	SCB->CPACR &= (~(CPACR_CP10_Msk | CPACR_CP11_Msk));
    22b0:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
    22b4:	f422 0270 	bic.w	r2, r2, #15728640	; 0xf00000
    22b8:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
	SCB->CPACR |= CPACR_CP10_PRIV_ACCESS | CPACR_CP11_PRIV_ACCESS;
    22bc:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
    22c0:	f442 02a0 	orr.w	r2, r2, #5242880	; 0x500000
    22c4:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
	FPU->FPCCR &= (~(FPU_FPCCR_ASPEN_Msk | FPU_FPCCR_LSPEN_Msk));
    22c8:	4a0e      	ldr	r2, [pc, #56]	; (2304 <z_arm_prep_c+0x68>)
    22ca:	6853      	ldr	r3, [r2, #4]
    22cc:	f023 4340 	bic.w	r3, r3, #3221225472	; 0xc0000000
    22d0:	6053      	str	r3, [r2, #4]
  __ASM volatile ("dsb 0xF":::"memory");
    22d2:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    22d6:	f3bf 8f6f 	isb	sy
  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
    22da:	2300      	movs	r3, #0
    22dc:	eee1 3a10 	vmsr	fpscr, r3
  __ASM volatile ("MRS %0, control" : "=r" (result) );
    22e0:	f3ef 8314 	mrs	r3, CONTROL
	__set_CONTROL(__get_CONTROL() & (~(CONTROL_FPCA_Msk)));
    22e4:	f023 0304 	bic.w	r3, r3, #4
  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
    22e8:	f383 8814 	msr	CONTROL, r3
	relocate_vector_table();
#if defined(CONFIG_CPU_HAS_FPU)
	z_arm_floating_point_init();
#endif
	z_bss_zero();
    22ec:	f000 ffb2 	bl	3254 <z_bss_zero>
	z_data_copy();
    22f0:	f001 fe14 	bl	3f1c <z_data_copy>
#if defined(CONFIG_ARMV7_R) && defined(CONFIG_INIT_STACKS)
	z_arm_init_stacks();
#endif
	z_arm_interrupt_init();
    22f4:	f000 f974 	bl	25e0 <z_arm_interrupt_init>
	z_cstart();
    22f8:	f000 ffd0 	bl	329c <z_cstart>
    22fc:	00000000 	.word	0x00000000
    2300:	e000ed00 	.word	0xe000ed00
    2304:	e000ef30 	.word	0xe000ef30

00002308 <_isr_wrapper>:
 * @return N/A
 */
SECTION_FUNC(TEXT, _isr_wrapper)

#if defined(CONFIG_CPU_CORTEX_M)
	push {r0,lr}		/* r0, lr are now the first items on the stack */
    2308:	b501      	push	{r0, lr}
	 * Disable interrupts to prevent nesting while exiting idle state. This
	 * is only necessary for the Cortex-M because it is the only ARM
	 * architecture variant that automatically enables interrupts when
	 * entering an ISR.
	 */
	cpsid i  /* PRIMASK = 1 */
    230a:	b672      	cpsid	i
#endif

	/* is this a wakeup from idle ? */
	ldr r2, =_kernel
    230c:	4a0b      	ldr	r2, [pc, #44]	; (233c <_isr_wrapper+0x34>)
	/* requested idle duration, in ticks */
	ldr r0, [r2, #_kernel_offset_to_idle]
    230e:	6a50      	ldr	r0, [r2, #36]	; 0x24
	cmp r0, #0
    2310:	2800      	cmp	r0, #0
	str r1, [r2, #_kernel_offset_to_idle]
	bl z_pm_save_idle_exit
_idle_state_cleared:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	ittt ne
    2312:	bf1e      	ittt	ne
	movne	r1, #0
    2314:	2100      	movne	r1, #0
		/* clear kernel idle state */
		strne	r1, [r2, #_kernel_offset_to_idle]
    2316:	6251      	strne	r1, [r2, #36]	; 0x24
		blne	z_pm_save_idle_exit
    2318:	f003 fbae 	blne	5a78 <z_pm_save_idle_exit>
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
	cpsie i		/* re-enable interrupts (PRIMASK = 0) */
    231c:	b662      	cpsie	i
#endif

#endif /* CONFIG_PM */

#if defined(CONFIG_CPU_CORTEX_M)
	mrs r0, IPSR	/* get exception number */
    231e:	f3ef 8005 	mrs	r0, IPSR
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r1, =16
	subs r0, r1	/* get IRQ number */
	lsls r0, #3	/* table is 8-byte wide */
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	sub r0, r0, #16	/* get IRQ number */
    2322:	f1a0 0010 	sub.w	r0, r0, #16
	lsl r0, r0, #3	/* table is 8-byte wide */
    2326:	ea4f 00c0 	mov.w	r0, r0, lsl #3
	 * interface function.
	 */
	cpsie i
#endif /* !CONFIG_CPU_CORTEX_M */

	ldr r1, =_sw_isr_table
    232a:	4905      	ldr	r1, [pc, #20]	; (2340 <_isr_wrapper+0x38>)
	add r1, r1, r0	/* table entry: ISRs must have their MSB set to stay
    232c:	4401      	add	r1, r0
			 * in thumb mode */

	ldm r1!,{r0,r3}	/* arg in r0, ISR in r3 */
    232e:	c909      	ldmia	r1!, {r0, r3}
	blx r3		/* call ISR */
    2330:	4798      	blx	r3

#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	pop {r0, r3}
	mov lr, r3
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	pop {r0, lr}
    2332:	e8bd 4001 	ldmia.w	sp!, {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

	/* Use 'bx' instead of 'b' because 'bx' can jump further, and use
	 * 'bx' instead of 'blx' because exception return is done in
	 * z_arm_int_exit() */
	ldr r1, =z_arm_int_exit
    2336:	4903      	ldr	r1, [pc, #12]	; (2344 <_isr_wrapper+0x3c>)
	bx r1
    2338:	4708      	bx	r1
    233a:	0000      	.short	0x0000
	ldr r2, =_kernel
    233c:	2000084c 	.word	0x2000084c
	ldr r1, =_sw_isr_table
    2340:	00005d10 	.word	0x00005d10
	ldr r1, =z_arm_int_exit
    2344:	000025a1 	.word	0x000025a1

00002348 <__start>:
#endif /* CONFIG_CPU_CORTEX_M_HAS_SPLIM */

#endif /* CONFIG_INIT_ARCH_HW_AT_BOOT */

#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
    bl z_platform_init
    2348:	f003 f92c 	bl	55a4 <z_platform_init>

    /* lock interrupts: will get unlocked when switch to main task */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    234c:	2020      	movs	r0, #32
    msr BASEPRI, r0
    234e:	f380 8811 	msr	BASEPRI, r0

    /*
     * Set PSP and use it to boot without using MSP, so that it
     * gets set to z_interrupt_stacks during initialization.
     */
    ldr r0, =z_interrupt_stacks
    2352:	4808      	ldr	r0, [pc, #32]	; (2374 <__start+0x2c>)
    ldr r1, =CONFIG_ISR_STACK_SIZE + MPU_GUARD_ALIGN_AND_SIZE
    2354:	f44f 6100 	mov.w	r1, #2048	; 0x800
    adds r0, r0, r1
    2358:	1840      	adds	r0, r0, r1
    msr PSP, r0
    235a:	f380 8809 	msr	PSP, r0
    mrs r0, CONTROL
    235e:	f3ef 8014 	mrs	r0, CONTROL
    movs r1, #2
    2362:	2102      	movs	r1, #2
    orrs r0, r1 /* CONTROL_SPSEL_Msk */
    2364:	4308      	orrs	r0, r1
    msr CONTROL, r0
    2366:	f380 8814 	msr	CONTROL, r0
    /*
     * When changing the stack pointer, software must use an ISB instruction
     * immediately after the MSR instruction. This ensures that instructions
     * after the ISB instruction execute using the new stack pointer.
     */
    isb
    236a:	f3bf 8f6f 	isb	sy
    /*
     * 'bl' jumps the furthest of the branch instructions that are
     * supported on all platforms. So it is used when jumping to z_arm_prep_c
     * (even though we do not intend to return).
     */
    bl z_arm_prep_c
    236e:	f7ff ff95 	bl	229c <z_arm_prep_c>
    2372:	0000      	.short	0x0000
    ldr r0, =z_interrupt_stacks
    2374:	20000df0 	.word	0x20000df0

00002378 <z_arm_bus_fault>:
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_exc_spurious)

	mrs r0, MSP
    2378:	f3ef 8008 	mrs	r0, MSP
	mrs r1, PSP
    237c:	f3ef 8109 	mrs	r1, PSP
	push {r0, lr}
    2380:	b501      	push	{r0, lr}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	push {r4-r11}
#endif
	mov  r3, sp /* pointer to _callee_saved_t */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
	mov r2, lr /* EXC_RETURN */
    2382:	4672      	mov	r2, lr
	bl z_arm_fault
    2384:	f000 f874 	bl	2470 <z_arm_fault>
	 * in this routine. Therefore, we can just reset
	 * the MSP to its value prior to entering the function
	 */
	add sp, #40
#endif
	pop {r0, pc}
    2388:	bd01      	pop	{r0, pc}
    238a:	bf00      	nop

0000238c <mem_manage_fault.isra.0>:
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	uint32_t mmfar = -EINVAL;

	PR_FAULT_INFO("***** MPU FAULT *****");

	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
    238c:	4b0e      	ldr	r3, [pc, #56]	; (23c8 <mem_manage_fault.isra.0+0x3c>)
    238e:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Stacking error (context area might be"
			" not valid)");
	}
	if ((SCB->CFSR & SCB_CFSR_MUNSTKERR_Msk) != 0) {
    2390:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Unstacking error");
	}
	if ((SCB->CFSR & SCB_CFSR_DACCVIOL_Msk) != 0) {
    2392:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    2394:	0792      	lsls	r2, r2, #30
    2396:	d508      	bpl.n	23aa <mem_manage_fault.isra.0+0x1e>
		 * The MMFAR address is valid only if this bit is 1.
		 *
		 * Software must follow this sequence because another higher
		 * priority exception might change the MMFAR value.
		 */
		uint32_t temp = SCB->MMFAR;
    2398:	6b5a      	ldr	r2, [r3, #52]	; 0x34

		if ((SCB->CFSR & SCB_CFSR_MMARVALID_Msk) != 0) {
    239a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    239c:	0612      	lsls	r2, r2, #24
    239e:	d504      	bpl.n	23aa <mem_manage_fault.isra.0+0x1e>
			mmfar = temp;
			PR_EXC("  MMFAR Address: 0x%x", mmfar);
			if (from_hard_fault) {
    23a0:	b118      	cbz	r0, 23aa <mem_manage_fault.isra.0+0x1e>
				/* clear SCB_MMAR[VALID] to reset */
				SCB->CFSR &= ~SCB_CFSR_MMARVALID_Msk;
    23a2:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    23a4:	f022 0280 	bic.w	r2, r2, #128	; 0x80
    23a8:	629a      	str	r2, [r3, #40]	; 0x28

	/* clear MMFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_MEMFAULTSR_Msk;

	/* Assess whether system shall ignore/recover from this MPU fault. */
	*recoverable = memory_fault_recoverable(esf);
    23aa:	2000      	movs	r0, #0
	if ((SCB->CFSR & SCB_CFSR_IACCVIOL_Msk) != 0) {
    23ac:	4b06      	ldr	r3, [pc, #24]	; (23c8 <mem_manage_fault.isra.0+0x3c>)
    23ae:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    23b0:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) ||
    23b2:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    23b4:	06d2      	lsls	r2, r2, #27
		(SCB->CFSR & SCB_CFSR_DACCVIOL_Msk)) {
    23b6:	bf58      	it	pl
    23b8:	6a9a      	ldrpl	r2, [r3, #40]	; 0x28
	SCB->CFSR |= SCB_CFSR_MEMFAULTSR_Msk;
    23ba:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    23bc:	f042 02ff 	orr.w	r2, r2, #255	; 0xff
    23c0:	629a      	str	r2, [r3, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf);
    23c2:	7008      	strb	r0, [r1, #0]

	return reason;
}
    23c4:	4770      	bx	lr
    23c6:	bf00      	nop
    23c8:	e000ed00 	.word	0xe000ed00

000023cc <bus_fault.isra.0>:
{
	uint32_t reason = K_ERR_CPU_EXCEPTION;

	PR_FAULT_INFO("***** BUS FAULT *****");

	if (SCB->CFSR & SCB_CFSR_STKERR_Msk) {
    23cc:	4b0d      	ldr	r3, [pc, #52]	; (2404 <bus_fault.isra.0+0x38>)
    23ce:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Stacking error");
	}
	if (SCB->CFSR & SCB_CFSR_UNSTKERR_Msk) {
    23d0:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Unstacking error");
	}
	if (SCB->CFSR & SCB_CFSR_PRECISERR_Msk) {
    23d2:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    23d4:	0592      	lsls	r2, r2, #22
    23d6:	d508      	bpl.n	23ea <bus_fault.isra.0+0x1e>
		 * The BFAR address is valid only if this bit is 1.
		 *
		 * Software must follow this sequence because another
		 * higher priority exception might change the BFAR value.
		 */
		STORE_xFAR(bfar, SCB->BFAR);
    23d8:	6b9a      	ldr	r2, [r3, #56]	; 0x38

		if ((SCB->CFSR & SCB_CFSR_BFARVALID_Msk) != 0) {
    23da:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    23dc:	0412      	lsls	r2, r2, #16
    23de:	d504      	bpl.n	23ea <bus_fault.isra.0+0x1e>
			PR_EXC("  BFAR Address: 0x%x", bfar);
			if (from_hard_fault) {
    23e0:	b118      	cbz	r0, 23ea <bus_fault.isra.0+0x1e>
				/* clear SCB_CFSR_BFAR[VALID] to reset */
				SCB->CFSR &= ~SCB_CFSR_BFARVALID_Msk;
    23e2:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    23e4:	f422 4200 	bic.w	r2, r2, #32768	; 0x8000
    23e8:	629a      	str	r2, [r3, #40]	; 0x28
#endif /* defined(CONFIG_ARM_MPU) && defined(CONFIG_CPU_HAS_NXP_MPU) */

	/* clear BFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;

	*recoverable = memory_fault_recoverable(esf);
    23ea:	2000      	movs	r0, #0
	if (SCB->CFSR & SCB_CFSR_IMPRECISERR_Msk) {
    23ec:	4b05      	ldr	r3, [pc, #20]	; (2404 <bus_fault.isra.0+0x38>)
    23ee:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_IBUSERR_Msk) != 0) {
    23f0:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    23f2:	05d2      	lsls	r2, r2, #23
	} else if (SCB->CFSR & SCB_CFSR_LSPERR_Msk) {
    23f4:	bf58      	it	pl
    23f6:	6a9a      	ldrpl	r2, [r3, #40]	; 0x28
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
    23f8:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    23fa:	f442 427f 	orr.w	r2, r2, #65280	; 0xff00
    23fe:	629a      	str	r2, [r3, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf);
    2400:	7008      	strb	r0, [r1, #0]

	return reason;
}
    2402:	4770      	bx	lr
    2404:	e000ed00 	.word	0xe000ed00

00002408 <usage_fault.isra.0>:
	uint32_t reason = K_ERR_CPU_EXCEPTION;

	PR_FAULT_INFO("***** USAGE FAULT *****");

	/* bits are sticky: they stack and must be reset */
	if ((SCB->CFSR & SCB_CFSR_DIVBYZERO_Msk) != 0) {
    2408:	4b09      	ldr	r3, [pc, #36]	; (2430 <usage_fault.isra.0+0x28>)
    240a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Division by zero");
	}
	if ((SCB->CFSR & SCB_CFSR_UNALIGNED_Msk) != 0) {
    240c:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Unaligned memory access");
	}
#if defined(CONFIG_ARMV8_M_MAINLINE)
	if ((SCB->CFSR & SCB_CFSR_STKOF_Msk) != 0) {
    240e:	6a98      	ldr	r0, [r3, #40]	; 0x28
		 */
		reason = K_ERR_STACK_CHK_FAIL;
#endif /* CONFIG_BUILTIN_STACK_GUARD */
	}
#endif /* CONFIG_ARMV8_M_MAINLINE */
	if ((SCB->CFSR & SCB_CFSR_NOCP_Msk) != 0) {
    2410:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  No coprocessor instructions");
	}
	if ((SCB->CFSR & SCB_CFSR_INVPC_Msk) != 0) {
    2412:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Illegal load of EXC_RETURN into PC");
	}
	if ((SCB->CFSR & SCB_CFSR_INVSTATE_Msk) != 0) {
    2414:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Illegal use of the EPSR");
	}
	if ((SCB->CFSR & SCB_CFSR_UNDEFINSTR_Msk) != 0) {
    2416:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Attempt to execute undefined instruction");
	}

	/* clear UFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    2418:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_STKOF_Msk) != 0) {
    241a:	f410 1080 	ands.w	r0, r0, #1048576	; 0x100000
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    241e:	ea6f 4202 	mvn.w	r2, r2, lsl #16
    2422:	ea6f 4212 	mvn.w	r2, r2, lsr #16

	return reason;
}
    2426:	bf18      	it	ne
    2428:	2002      	movne	r0, #2
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    242a:	629a      	str	r2, [r3, #40]	; 0x28
}
    242c:	4770      	bx	lr
    242e:	bf00      	nop
    2430:	e000ed00 	.word	0xe000ed00

00002434 <secure_fault.isra.0>:
 */
static void secure_fault(const z_arch_esf_t *esf)
{
	PR_FAULT_INFO("***** SECURE FAULT *****");

	STORE_xFAR(sfar, SAU->SFAR);
    2434:	4b0d      	ldr	r3, [pc, #52]	; (246c <secure_fault.isra.0+0x38>)
    2436:	699a      	ldr	r2, [r3, #24]
	if ((SAU->SFSR & SAU_SFSR_SFARVALID_Msk) != 0) {
    2438:	695a      	ldr	r2, [r3, #20]
		PR_EXC("  Address: 0x%x", sfar);
	}

	/* bits are sticky: they stack and must be reset */
	if ((SAU->SFSR & SAU_SFSR_INVEP_Msk) != 0) {
    243a:	695a      	ldr	r2, [r3, #20]
    243c:	07d0      	lsls	r0, r2, #31
    243e:	d40f      	bmi.n	2460 <secure_fault.isra.0+0x2c>
		PR_FAULT_INFO("  Invalid entry point");
	} else if ((SAU->SFSR & SAU_SFSR_INVIS_Msk) != 0) {
    2440:	695a      	ldr	r2, [r3, #20]
    2442:	0791      	lsls	r1, r2, #30
    2444:	d40c      	bmi.n	2460 <secure_fault.isra.0+0x2c>
		PR_FAULT_INFO("  Invalid integrity signature");
	} else if ((SAU->SFSR & SAU_SFSR_INVER_Msk) != 0) {
    2446:	695a      	ldr	r2, [r3, #20]
    2448:	0752      	lsls	r2, r2, #29
    244a:	d409      	bmi.n	2460 <secure_fault.isra.0+0x2c>
		PR_FAULT_INFO("  Invalid exception return");
	} else if ((SAU->SFSR & SAU_SFSR_AUVIOL_Msk) != 0) {
    244c:	695a      	ldr	r2, [r3, #20]
    244e:	0710      	lsls	r0, r2, #28
    2450:	d406      	bmi.n	2460 <secure_fault.isra.0+0x2c>
		PR_FAULT_INFO("  Attribution unit violation");
	} else if ((SAU->SFSR & SAU_SFSR_INVTRAN_Msk) != 0) {
    2452:	695a      	ldr	r2, [r3, #20]
    2454:	06d1      	lsls	r1, r2, #27
    2456:	d403      	bmi.n	2460 <secure_fault.isra.0+0x2c>
		PR_FAULT_INFO("  Invalid transition");
	} else if ((SAU->SFSR & SAU_SFSR_LSPERR_Msk) != 0) {
    2458:	695a      	ldr	r2, [r3, #20]
    245a:	0692      	lsls	r2, r2, #26
		PR_FAULT_INFO("  Lazy state preservation");
	} else if ((SAU->SFSR & SAU_SFSR_LSERR_Msk) != 0) {
    245c:	bf58      	it	pl
    245e:	695a      	ldrpl	r2, [r3, #20]
		PR_FAULT_INFO("  Lazy state error");
	}

	/* clear SFSR sticky bits */
	SAU->SFSR |= 0xFF;
    2460:	695a      	ldr	r2, [r3, #20]
    2462:	f042 02ff 	orr.w	r2, r2, #255	; 0xff
    2466:	615a      	str	r2, [r3, #20]
}
    2468:	4770      	bx	lr
    246a:	bf00      	nop
    246c:	e000edd0 	.word	0xe000edd0

00002470 <z_arm_fault>:
 * @param callee_regs Callee-saved registers (R4-R11, PSP)
 *
 */
void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return,
	_callee_saved_t *callee_regs)
{
    2470:	b5f0      	push	{r4, r5, r6, r7, lr}
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    2472:	4b41      	ldr	r3, [pc, #260]	; (2578 <z_arm_fault+0x108>)
    2474:	2500      	movs	r5, #0
    2476:	685b      	ldr	r3, [r3, #4]
{
    2478:	b08b      	sub	sp, #44	; 0x2c
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    247a:	f3c3 0308 	ubfx	r3, r3, #0, #9
    247e:	f385 8811 	msr	BASEPRI, r5
    2482:	f3bf 8f6f 	isb	sy
	if ((exc_return & EXC_RETURN_INDICATOR_PREFIX) !=
    2486:	f002 447f 	and.w	r4, r2, #4278190080	; 0xff000000
    248a:	f1b4 4f7f 	cmp.w	r4, #4278190080	; 0xff000000
    248e:	d11e      	bne.n	24ce <z_arm_fault+0x5e>
	if ((exc_return & EXC_RETURN_EXCEPTION_SECURE_Secure) == 0U) {
    2490:	f012 0401 	ands.w	r4, r2, #1
    2494:	d01a      	beq.n	24cc <z_arm_fault+0x5c>
	if (exc_return & EXC_RETURN_RETURN_STACK_Secure) {
    2496:	0656      	lsls	r6, r2, #25
    2498:	f002 0408 	and.w	r4, r2, #8
    249c:	d467      	bmi.n	256e <z_arm_fault+0xfe>
		if (exc_return & EXC_RETURN_SPSEL_PROCESS) {
    249e:	f082 0204 	eor.w	r2, r2, #4
    24a2:	f3c2 0580 	ubfx	r5, r2, #2, #1
		if (exc_return & EXC_RETURN_MODE_THREAD) {
    24a6:	b164      	cbz	r4, 24c2 <z_arm_fault+0x52>
  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
    24a8:	f3ef 8689 	mrs	r6, PSP_NS
	*recoverable = false;
    24ac:	2200      	movs	r2, #0
    24ae:	3b03      	subs	r3, #3
    24b0:	f88d 2007 	strb.w	r2, [sp, #7]
	switch (fault) {
    24b4:	2b04      	cmp	r3, #4
    24b6:	d84b      	bhi.n	2550 <z_arm_fault+0xe0>
    24b8:	e8df f003 	tbb	[pc, r3]
    24bc:	41504c0b 	.word	0x41504c0b
    24c0:	48          	.byte	0x48
    24c1:	00          	.byte	0x00
  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
    24c2:	f3ef 8688 	mrs	r6, MSP_NS
  return(result);
    24c6:	e7f1      	b.n	24ac <z_arm_fault+0x3c>
			ptr_esf =  (z_arch_esf_t *)psp;
    24c8:	460e      	mov	r6, r1
    24ca:	e7ef      	b.n	24ac <z_arm_fault+0x3c>
	*nested_exc = false;
    24cc:	4625      	mov	r5, r4
		return NULL;
    24ce:	462e      	mov	r6, r5
    24d0:	e7ec      	b.n	24ac <z_arm_fault+0x3c>
	if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk) != 0) {
    24d2:	4b29      	ldr	r3, [pc, #164]	; (2578 <z_arm_fault+0x108>)
    24d4:	6ada      	ldr	r2, [r3, #44]	; 0x2c
    24d6:	0792      	lsls	r2, r2, #30
    24d8:	d43a      	bmi.n	2550 <z_arm_fault+0xe0>
	} else if ((SCB->HFSR & SCB_HFSR_FORCED_Msk) != 0) {
    24da:	6adc      	ldr	r4, [r3, #44]	; 0x2c
    24dc:	f014 4480 	ands.w	r4, r4, #1073741824	; 0x40000000
    24e0:	d008      	beq.n	24f4 <z_arm_fault+0x84>
		if (SCB_MMFSR != 0) {
    24e2:	3328      	adds	r3, #40	; 0x28
    24e4:	781b      	ldrb	r3, [r3, #0]
    24e6:	b1eb      	cbz	r3, 2524 <z_arm_fault+0xb4>
			reason = mem_manage_fault(esf, 1, recoverable);
    24e8:	2001      	movs	r0, #1
    24ea:	f10d 0107 	add.w	r1, sp, #7
		reason = mem_manage_fault(esf, 0, recoverable);
    24ee:	f7ff ff4d 	bl	238c <mem_manage_fault.isra.0>
    24f2:	4604      	mov	r4, r0
#ifdef CONFIG_DEBUG_COREDUMP
	z_arm_coredump_fault_sp = POINTER_TO_UINT(esf);
#endif

	reason = fault_handle(esf, fault, &recoverable);
	if (recoverable) {
    24f4:	f89d 3007 	ldrb.w	r3, [sp, #7]
    24f8:	b993      	cbnz	r3, 2520 <z_arm_fault+0xb0>
		return;
	}

	/* Copy ESF */
#if !defined(CONFIG_EXTRA_EXCEPTION_INFO)
	memcpy(&esf_copy, esf, sizeof(z_arch_esf_t));
    24fa:	2220      	movs	r2, #32
    24fc:	4631      	mov	r1, r6
    24fe:	a802      	add	r0, sp, #8
    2500:	f003 f9ea 	bl	58d8 <memcpy>
	/* Overwrite stacked IPSR to mark a nested exception,
	 * or a return to Thread mode. Note that this may be
	 * required, if the retrieved ESF contents are invalid
	 * due to, for instance, a stacking error.
	 */
	if (nested_exc) {
    2504:	9b09      	ldr	r3, [sp, #36]	; 0x24
    2506:	b36d      	cbz	r5, 2564 <z_arm_fault+0xf4>
		if ((esf_copy.basic.xpsr & IPSR_ISR_Msk) == 0) {
    2508:	f3c3 0208 	ubfx	r2, r3, #0, #9
    250c:	b922      	cbnz	r2, 2518 <z_arm_fault+0xa8>
			esf_copy.basic.xpsr |= IPSR_ISR_Msk;
    250e:	ea6f 2353 	mvn.w	r3, r3, lsr #9
    2512:	ea6f 2343 	mvn.w	r3, r3, lsl #9
		}
	} else {
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    2516:	9309      	str	r3, [sp, #36]	; 0x24
	}

	z_arm_fatal_error(reason, &esf_copy);
    2518:	4620      	mov	r0, r4
    251a:	a902      	add	r1, sp, #8
    251c:	f003 f96c 	bl	57f8 <z_arm_fatal_error>
}
    2520:	b00b      	add	sp, #44	; 0x2c
    2522:	bdf0      	pop	{r4, r5, r6, r7, pc}
		} else if (SCB_BFSR != 0) {
    2524:	4b15      	ldr	r3, [pc, #84]	; (257c <z_arm_fault+0x10c>)
    2526:	781b      	ldrb	r3, [r3, #0]
    2528:	b12b      	cbz	r3, 2536 <z_arm_fault+0xc6>
			reason = bus_fault(esf, 1, recoverable);
    252a:	2001      	movs	r0, #1
    252c:	f10d 0107 	add.w	r1, sp, #7
		reason = bus_fault(esf, 0, recoverable);
    2530:	f7ff ff4c 	bl	23cc <bus_fault.isra.0>
    2534:	e7dd      	b.n	24f2 <z_arm_fault+0x82>
		} else if (SCB_UFSR != 0) {
    2536:	4b12      	ldr	r3, [pc, #72]	; (2580 <z_arm_fault+0x110>)
    2538:	881f      	ldrh	r7, [r3, #0]
    253a:	b2bf      	uxth	r7, r7
    253c:	b117      	cbz	r7, 2544 <z_arm_fault+0xd4>
		reason = usage_fault(esf);
    253e:	f7ff ff63 	bl	2408 <usage_fault.isra.0>
    2542:	e7d6      	b.n	24f2 <z_arm_fault+0x82>
		} else if (SAU->SFSR != 0) {
    2544:	4b0f      	ldr	r3, [pc, #60]	; (2584 <z_arm_fault+0x114>)
    2546:	695c      	ldr	r4, [r3, #20]
    2548:	2c00      	cmp	r4, #0
    254a:	d0d3      	beq.n	24f4 <z_arm_fault+0x84>
		secure_fault(esf);
    254c:	f7ff ff72 	bl	2434 <secure_fault.isra.0>
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    2550:	2400      	movs	r4, #0
    2552:	e7cf      	b.n	24f4 <z_arm_fault+0x84>
		reason = mem_manage_fault(esf, 0, recoverable);
    2554:	2000      	movs	r0, #0
    2556:	f10d 0107 	add.w	r1, sp, #7
    255a:	e7c8      	b.n	24ee <z_arm_fault+0x7e>
		reason = bus_fault(esf, 0, recoverable);
    255c:	2000      	movs	r0, #0
    255e:	f10d 0107 	add.w	r1, sp, #7
    2562:	e7e5      	b.n	2530 <z_arm_fault+0xc0>
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    2564:	f423 73ff 	bic.w	r3, r3, #510	; 0x1fe
    2568:	f023 0301 	bic.w	r3, r3, #1
    256c:	e7d3      	b.n	2516 <z_arm_fault+0xa6>
		if (exc_return & EXC_RETURN_MODE_THREAD) {
    256e:	2c00      	cmp	r4, #0
    2570:	d1aa      	bne.n	24c8 <z_arm_fault+0x58>
			ptr_esf = (z_arch_esf_t *)msp;
    2572:	4606      	mov	r6, r0
			*nested_exc = true;
    2574:	2501      	movs	r5, #1
    2576:	e799      	b.n	24ac <z_arm_fault+0x3c>
    2578:	e000ed00 	.word	0xe000ed00
    257c:	e000ed29 	.word	0xe000ed29
    2580:	e000ed2a 	.word	0xe000ed2a
    2584:	e000edd0 	.word	0xe000edd0

00002588 <z_arm_fault_init>:
 */
void z_arm_fault_init(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
    2588:	4b04      	ldr	r3, [pc, #16]	; (259c <z_arm_fault_init+0x14>)
    258a:	695a      	ldr	r2, [r3, #20]
    258c:	f042 0210 	orr.w	r2, r2, #16
    2590:	615a      	str	r2, [r3, #20]
	 *
	 * For Non-Secure Firmware this could allow the Non-Secure Main
	 * Stack to attempt to descend into secure region, in which case a
	 * Secure Hard Fault will occur and we can track the fault from there.
	 */
	SCB->CCR |= SCB_CCR_STKOFHFNMIGN_Msk;
    2592:	695a      	ldr	r2, [r3, #20]
    2594:	f442 6280 	orr.w	r2, r2, #1024	; 0x400
    2598:	615a      	str	r2, [r3, #20]
#endif /* CONFIG_BUILTIN_STACK_GUARD */
}
    259a:	4770      	bx	lr
    259c:	e000ed00 	.word	0xe000ed00

000025a0 <z_arm_exc_exit>:
 */

SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_exc_exit)

#ifdef CONFIG_PREEMPT_ENABLED
	ldr r3, =_kernel
    25a0:	4b04      	ldr	r3, [pc, #16]	; (25b4 <_EXIT_EXC+0x2>)

	ldr r1, [r3, #_kernel_offset_to_current]
    25a2:	6899      	ldr	r1, [r3, #8]
	ldr r0, [r3, #_kernel_offset_to_ready_q_cache]
    25a4:	6a98      	ldr	r0, [r3, #40]	; 0x28
	cmp r0, r1
    25a6:	4288      	cmp	r0, r1
	beq _EXIT_EXC
    25a8:	d003      	beq.n	25b2 <_EXIT_EXC>

	/* context switch required, pend the PendSV exception */
	ldr r1, =_SCS_ICSR
    25aa:	4903      	ldr	r1, [pc, #12]	; (25b8 <_EXIT_EXC+0x6>)
	ldr r2, =_SCS_ICSR_PENDSV
    25ac:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
	str r2, [r1]
    25b0:	600a      	str	r2, [r1, #0]

000025b2 <_EXIT_EXC>:
#else
	pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_STACK_SENTINEL */

	bx lr
    25b2:	4770      	bx	lr
	ldr r3, =_kernel
    25b4:	2000084c 	.word	0x2000084c
	ldr r1, =_SCS_ICSR
    25b8:	e000ed04 	.word	0xe000ed04

000025bc <sys_arch_reboot>:
  __ASM volatile ("dsb 0xF":::"memory");
    25bc:	f3bf 8f4f 	dsb	sy
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
  __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                       buffered write are completed before reset */
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    25c0:	4905      	ldr	r1, [pc, #20]	; (25d8 <sys_arch_reboot+0x1c>)
    25c2:	4b06      	ldr	r3, [pc, #24]	; (25dc <sys_arch_reboot+0x20>)
    25c4:	68ca      	ldr	r2, [r1, #12]
    25c6:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    25ca:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    25cc:	60cb      	str	r3, [r1, #12]
    25ce:	f3bf 8f4f 	dsb	sy
                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
  __DSB();                                                          /* Ensure completion of memory access */

  for(;;)                                                           /* wait until reset */
  {
    __NOP();
    25d2:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    25d4:	e7fd      	b.n	25d2 <sys_arch_reboot+0x16>
    25d6:	bf00      	nop
    25d8:	e000ed00 	.word	0xe000ed00
    25dc:	05fa0004 	.word	0x05fa0004

000025e0 <z_arm_interrupt_init>:
 * @return N/A
 */

void z_arm_interrupt_init(void)
{
	int irq = 0;
    25e0:	2300      	movs	r3, #0
    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    25e2:	2120      	movs	r1, #32
    25e4:	4803      	ldr	r0, [pc, #12]	; (25f4 <z_arm_interrupt_init+0x14>)
    25e6:	18c2      	adds	r2, r0, r3

	for (; irq < CONFIG_NUM_IRQS; irq++) {
    25e8:	3301      	adds	r3, #1
    25ea:	2b41      	cmp	r3, #65	; 0x41
    25ec:	f882 1300 	strb.w	r1, [r2, #768]	; 0x300
    25f0:	d1f9      	bne.n	25e6 <z_arm_interrupt_init+0x6>
		NVIC_SetPriority((IRQn_Type)irq, _IRQ_PRIO_OFFSET);
	}
}
    25f2:	4770      	bx	lr
    25f4:	e000e100 	.word	0xe000e100

000025f8 <z_impl_k_thread_abort>:
#include <kswap.h>
#include <wait_q.h>
#include <sys/__assert.h>

void z_impl_k_thread_abort(k_tid_t thread)
{
    25f8:	b508      	push	{r3, lr}
	if (_current == thread) {
    25fa:	4b0e      	ldr	r3, [pc, #56]	; (2634 <z_impl_k_thread_abort+0x3c>)
    25fc:	689b      	ldr	r3, [r3, #8]
    25fe:	4283      	cmp	r3, r0
    2600:	d107      	bne.n	2612 <z_impl_k_thread_abort+0x1a>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    2602:	f3ef 8305 	mrs	r3, IPSR
		if (arch_is_in_isr()) {
    2606:	b193      	cbz	r3, 262e <z_impl_k_thread_abort+0x36>
			 * should no longer run after we return, so
			 * Trigger PendSV, in case we are in one of the
			 * situations where the isr check is true but there
			 * is not an implicit scheduler invocation.
			 */
			SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    2608:	4a0b      	ldr	r2, [pc, #44]	; (2638 <z_impl_k_thread_abort+0x40>)
    260a:	6853      	ldr	r3, [r2, #4]
    260c:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
    2610:	6053      	str	r3, [r2, #4]
		} else {
			z_self_abort(); /* Never returns */
		}
	}

	z_thread_single_abort(thread);
    2612:	f001 f9c7 	bl	39a4 <z_thread_single_abort>
	__asm__ volatile(
    2616:	f04f 0320 	mov.w	r3, #32
    261a:	f3ef 8011 	mrs	r0, BASEPRI
    261e:	f383 8811 	msr	BASEPRI, r3
    2622:	f3bf 8f6f 	isb	sy

	/* The abort handler might have altered the ready queue. */
	z_reschedule_unlocked();
}
    2626:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	(void) z_pend_curr_irqlock(arch_irq_lock(), wait_q, timeout);
}

static inline void z_reschedule_unlocked(void)
{
	(void) z_reschedule_irqlock(arch_irq_lock());
    262a:	f003 ba49 	b.w	5ac0 <z_reschedule_irqlock>
			z_self_abort(); /* Never returns */
    262e:	f001 fc61 	bl	3ef4 <z_self_abort>
    2632:	bf00      	nop
    2634:	2000084c 	.word	0x2000084c
    2638:	e000ed00 	.word	0xe000ed00

0000263c <z_arm_configure_static_mpu_regions>:
 *
 * For some MPU architectures, such as the unmodified ARMv8-M MPU,
 * the function must execute with MPU enabled.
 */
void z_arm_configure_static_mpu_regions(void)
{
    263c:	b51f      	push	{r0, r1, r2, r3, r4, lr}
	/* Configure the static MPU regions within firmware SRAM boundaries.
	 * Start address of the image is given by _image_ram_start. The end
	 * of the firmware SRAM area is marked by __kernel_ram_end, taking
	 * into account the unused SRAM area, as well.
	 */
	arm_core_mpu_configure_static_mpu_regions(static_regions,
    263e:	4c09      	ldr	r4, [pc, #36]	; (2664 <z_arm_configure_static_mpu_regions+0x28>)
    2640:	4a09      	ldr	r2, [pc, #36]	; (2668 <z_arm_configure_static_mpu_regions+0x2c>)
    2642:	4623      	mov	r3, r4
    2644:	2101      	movs	r1, #1
    2646:	4809      	ldr	r0, [pc, #36]	; (266c <z_arm_configure_static_mpu_regions+0x30>)
    2648:	f000 f902 	bl	2850 <arm_core_mpu_configure_static_mpu_regions>
	/* Define a constant array of z_arm_mpu_partition objects that holds the
	 * boundaries of the areas, inside which dynamic region programming
	 * is allowed. The information is passed to the underlying driver at
	 * initialization.
	 */
	const struct z_arm_mpu_partition dyn_region_areas[] = {
    264c:	2300      	movs	r3, #0
    264e:	9303      	str	r3, [sp, #12]
		{
		.start = _MPU_DYNAMIC_REGIONS_AREA_START,
    2650:	4b07      	ldr	r3, [pc, #28]	; (2670 <z_arm_configure_static_mpu_regions+0x34>)
		.size =  _MPU_DYNAMIC_REGIONS_AREA_SIZE,
		}
	};

	arm_core_mpu_mark_areas_for_dynamic_regions(dyn_region_areas,
    2652:	2101      	movs	r1, #1
		.size =  _MPU_DYNAMIC_REGIONS_AREA_SIZE,
    2654:	1ae4      	subs	r4, r4, r3
	arm_core_mpu_mark_areas_for_dynamic_regions(dyn_region_areas,
    2656:	a801      	add	r0, sp, #4
	const struct z_arm_mpu_partition dyn_region_areas[] = {
    2658:	9301      	str	r3, [sp, #4]
    265a:	9402      	str	r4, [sp, #8]
	arm_core_mpu_mark_areas_for_dynamic_regions(dyn_region_areas,
    265c:	f000 f902 	bl	2864 <arm_core_mpu_mark_areas_for_dynamic_regions>
		ARRAY_SIZE(dyn_region_areas));
#endif /* CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS */
}
    2660:	b004      	add	sp, #16
    2662:	bd10      	pop	{r4, pc}
    2664:	20010000 	.word	0x20010000
    2668:	20000000 	.word	0x20000000
    266c:	00006098 	.word	0x00006098
    2670:	20000128 	.word	0x20000128

00002674 <region_init>:
 * Note:
 *   The caller must provide a valid region index.
 */
static void region_init(const uint32_t index,
	const struct arm_mpu_region *region_conf)
{
    2674:	b510      	push	{r4, lr}
	ARM_MPU_SetRegion(
		/* RNR */
		index,
		/* RBAR */
		(region_conf->base & MPU_RBAR_BASE_Msk)
    2676:	680b      	ldr	r3, [r1, #0]
		| (region_conf->attr.rbar &
    2678:	7a0c      	ldrb	r4, [r1, #8]
		(region_conf->base & MPU_RBAR_BASE_Msk)
    267a:	f023 021f 	bic.w	r2, r3, #31
		| (region_conf->attr.rbar &
    267e:	f004 031f 	and.w	r3, r4, #31
    2682:	431a      	orrs	r2, r3
			(MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)),
		/* RLAR */
		(region_conf->attr.r_limit & MPU_RLAR_LIMIT_Msk)
    2684:	68cb      	ldr	r3, [r1, #12]
		| ((region_conf->attr.mair_idx << MPU_RLAR_AttrIndx_Pos)
    2686:	0964      	lsrs	r4, r4, #5
		(region_conf->attr.r_limit & MPU_RLAR_LIMIT_Msk)
    2688:	f023 031f 	bic.w	r3, r3, #31
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/   
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
  mpu->RNR = rnr;
    268c:	4904      	ldr	r1, [pc, #16]	; (26a0 <region_init+0x2c>)
		| ((region_conf->attr.mair_idx << MPU_RLAR_AttrIndx_Pos)
    268e:	ea43 0344 	orr.w	r3, r3, r4, lsl #1
			& MPU_RLAR_AttrIndx_Msk)
		| MPU_RLAR_EN_Msk
    2692:	f043 0301 	orr.w	r3, r3, #1
    2696:	6088      	str	r0, [r1, #8]
  mpu->RBAR = rbar;
    2698:	60ca      	str	r2, [r1, #12]
  mpu->RLAR = rlar;
    269a:	610b      	str	r3, [r1, #16]
	);

	LOG_DBG("[%d] 0x%08x 0x%08x 0x%08x 0x%08x",
			index, region_conf->base, region_conf->attr.rbar,
			region_conf->attr.mair_idx, region_conf->attr.r_limit);
}
    269c:	bd10      	pop	{r4, pc}
    269e:	bf00      	nop
    26a0:	e000ed90 	.word	0xe000ed90

000026a4 <mpu_configure_regions_and_partition.constprop.0>:
 * sanity check of the memory regions to be programmed.
 *
 * The function performs a full partition of the background memory
 * area, effectively, leaving no space in this area uncovered by MPU.
 */
static int mpu_configure_regions_and_partition(const struct z_arm_mpu_partition
    26a4:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    26a8:	4688      	mov	r8, r1
    26aa:	4614      	mov	r4, r2
	bool do_sanity_check)
{
	int i;
	int reg_index = start_reg_index;

	for (i = 0; i < regions_num; i++) {
    26ac:	4606      	mov	r6, r0
    26ae:	f04f 0900 	mov.w	r9, #0
	MPU->RNR = index;
    26b2:	4d4a      	ldr	r5, [pc, #296]	; (27dc <mpu_configure_regions_and_partition.constprop.0+0x138>)
static int mpu_configure_regions_and_partition(const struct z_arm_mpu_partition
    26b4:	b085      	sub	sp, #20
	for (i = 0; i < regions_num; i++) {
    26b6:	45c1      	cmp	r9, r8
    26b8:	da05      	bge.n	26c6 <mpu_configure_regions_and_partition.constprop.0+0x22>
		if (regions[i].size == 0U) {
    26ba:	6877      	ldr	r7, [r6, #4]
    26bc:	b3bf      	cbz	r7, 272e <mpu_configure_regions_and_partition.constprop.0+0x8a>
		&&
    26be:	2f1f      	cmp	r7, #31
    26c0:	d805      	bhi.n	26ce <mpu_configure_regions_and_partition.constprop.0+0x2a>

			reg_index =
				mpu_configure_region(reg_index, &regions[i]);

			if (reg_index == -EINVAL) {
				return reg_index;
    26c2:	f06f 0415 	mvn.w	r4, #21
			reg_index++;
		}
	}

	return reg_index;
}
    26c6:	4620      	mov	r0, r4
    26c8:	b005      	add	sp, #20
    26ca:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		&&
    26ce:	06fb      	lsls	r3, r7, #27
    26d0:	d1f7      	bne.n	26c2 <mpu_configure_regions_and_partition.constprop.0+0x1e>
		((part->start &
    26d2:	f8d6 a000 	ldr.w	sl, [r6]
		&&
    26d6:	f01a 0f1f 	tst.w	sl, #31
    26da:	d1f2      	bne.n	26c2 <mpu_configure_regions_and_partition.constprop.0+0x1e>
	uint32_t region_start_addr = arm_cmse_mpu_region_get(start);
    26dc:	4650      	mov	r0, sl
    26de:	f003 f8b5 	bl	584c <arm_cmse_mpu_region_get>
    26e2:	4683      	mov	fp, r0
	uint32_t region_end_addr = arm_cmse_mpu_region_get(start + size - 1);
    26e4:	eb07 000a 	add.w	r0, r7, sl
    26e8:	3801      	subs	r0, #1
    26ea:	f003 f8af 	bl	584c <arm_cmse_mpu_region_get>
	if (region_start_addr == region_end_addr) {
    26ee:	4583      	cmp	fp, r0
    26f0:	d1e7      	bne.n	26c2 <mpu_configure_regions_and_partition.constprop.0+0x1e>
		if ((u_reg_index == -EINVAL) ||
    26f2:	f11b 0f16 	cmn.w	fp, #22
    26f6:	d0e4      	beq.n	26c2 <mpu_configure_regions_and_partition.constprop.0+0x1e>
			(u_reg_index > (reg_index - 1))) {
    26f8:	1e63      	subs	r3, r4, #1
		if ((u_reg_index == -EINVAL) ||
    26fa:	455b      	cmp	r3, fp
    26fc:	dbe1      	blt.n	26c2 <mpu_configure_regions_and_partition.constprop.0+0x1e>
	MPU->RNR = index;
    26fe:	f8c5 b008 	str.w	fp, [r5, #8]
	return MPU->RBAR & MPU_RBAR_BASE_Msk;
    2702:	68e9      	ldr	r1, [r5, #12]
	MPU->RNR = index;
    2704:	f8c5 b008 	str.w	fp, [r5, #8]
	return (MPU->RLAR & MPU_RLAR_LIMIT_Msk) | (~MPU_RLAR_LIMIT_Msk);
    2708:	692f      	ldr	r7, [r5, #16]
	return MPU->RBAR & MPU_RBAR_BASE_Msk;
    270a:	f021 011f 	bic.w	r1, r1, #31
		uint32_t reg_last = regions[i].start + regions[i].size - 1;
    270e:	e9d6 3200 	ldrd	r3, r2, [r6]
    2712:	441a      	add	r2, r3
		if ((regions[i].start == u_reg_base) &&
    2714:	4299      	cmp	r1, r3
	return (MPU->RLAR & MPU_RLAR_LIMIT_Msk) | (~MPU_RLAR_LIMIT_Msk);
    2716:	f047 071f 	orr.w	r7, r7, #31
		uint32_t reg_last = regions[i].start + regions[i].size - 1;
    271a:	f102 3aff 	add.w	sl, r2, #4294967295	; 0xffffffff
		if ((regions[i].start == u_reg_base) &&
    271e:	d11c      	bne.n	275a <mpu_configure_regions_and_partition.constprop.0+0xb6>
    2720:	4557      	cmp	r7, sl
    2722:	d108      	bne.n	2736 <mpu_configure_regions_and_partition.constprop.0+0x92>
			mpu_configure_region(u_reg_index, &regions[i]);
    2724:	4631      	mov	r1, r6
    2726:	fa5f f08b 	uxtb.w	r0, fp
    272a:	f003 f872 	bl	5812 <mpu_configure_region>
	for (i = 0; i < regions_num; i++) {
    272e:	f109 0901 	add.w	r9, r9, #1
    2732:	360c      	adds	r6, #12
    2734:	e7bf      	b.n	26b6 <mpu_configure_regions_and_partition.constprop.0+0x12>
				mpu_configure_region(reg_index, &regions[i]);
    2736:	4631      	mov	r1, r6
	MPU->RNR = index;
    2738:	f8c5 b008 	str.w	fp, [r5, #8]
	MPU->RBAR = (MPU->RBAR & (~MPU_RBAR_BASE_Msk))
    273c:	68eb      	ldr	r3, [r5, #12]
		| (base & MPU_RBAR_BASE_Msk);
    273e:	f022 021f 	bic.w	r2, r2, #31
	MPU->RBAR = (MPU->RBAR & (~MPU_RBAR_BASE_Msk))
    2742:	f003 031f 	and.w	r3, r3, #31
		| (base & MPU_RBAR_BASE_Msk);
    2746:	431a      	orrs	r2, r3
	MPU->RBAR = (MPU->RBAR & (~MPU_RBAR_BASE_Msk))
    2748:	60ea      	str	r2, [r5, #12]
				mpu_configure_region(reg_index, &regions[i]);
    274a:	b2e0      	uxtb	r0, r4
				mpu_configure_region(reg_index, &regions[i]);
    274c:	f003 f861 	bl	5812 <mpu_configure_region>
			if (reg_index == -EINVAL) {
    2750:	f110 0f16 	cmn.w	r0, #22
    2754:	d0b5      	beq.n	26c2 <mpu_configure_regions_and_partition.constprop.0+0x1e>
			reg_index++;
    2756:	1c44      	adds	r4, r0, #1
    2758:	e7e9      	b.n	272e <mpu_configure_regions_and_partition.constprop.0+0x8a>
		} else if (reg_last == u_reg_last) {
    275a:	3b01      	subs	r3, #1
    275c:	4557      	cmp	r7, sl
    275e:	b2e0      	uxtb	r0, r4
    2760:	f023 031f 	bic.w	r3, r3, #31
	MPU->RNR = index;
    2764:	f8c5 b008 	str.w	fp, [r5, #8]
		} else if (reg_last == u_reg_last) {
    2768:	d106      	bne.n	2778 <mpu_configure_regions_and_partition.constprop.0+0xd4>
	MPU->RLAR = (MPU->RLAR & (~MPU_RLAR_LIMIT_Msk))
    276a:	692a      	ldr	r2, [r5, #16]
				mpu_configure_region(reg_index, &regions[i]);
    276c:	4631      	mov	r1, r6
	MPU->RLAR = (MPU->RLAR & (~MPU_RLAR_LIMIT_Msk))
    276e:	f002 021f 	and.w	r2, r2, #31
		| (limit & MPU_RLAR_LIMIT_Msk);
    2772:	4313      	orrs	r3, r2
	MPU->RLAR = (MPU->RLAR & (~MPU_RLAR_LIMIT_Msk))
    2774:	612b      	str	r3, [r5, #16]
			reg_index =
    2776:	e7e9      	b.n	274c <mpu_configure_regions_and_partition.constprop.0+0xa8>
	MPU->RLAR = (MPU->RLAR & (~MPU_RLAR_LIMIT_Msk))
    2778:	6929      	ldr	r1, [r5, #16]
    277a:	f001 011f 	and.w	r1, r1, #31
		| (limit & MPU_RLAR_LIMIT_Msk);
    277e:	430b      	orrs	r3, r1
	MPU->RLAR = (MPU->RLAR & (~MPU_RLAR_LIMIT_Msk))
    2780:	612b      	str	r3, [r5, #16]
				mpu_configure_region(reg_index, &regions[i]);
    2782:	4631      	mov	r1, r6
    2784:	f003 f845 	bl	5812 <mpu_configure_region>
			if (reg_index == -EINVAL) {
    2788:	f110 0f16 	cmn.w	r0, #22
    278c:	d099      	beq.n	26c2 <mpu_configure_regions_and_partition.constprop.0+0x1e>
	MPU->RNR = index;
    278e:	f8c5 b008 	str.w	fp, [r5, #8]
	attr->rbar = MPU->RBAR &
    2792:	68ea      	ldr	r2, [r5, #12]
    2794:	f89d 3008 	ldrb.w	r3, [sp, #8]
			REGION_LIMIT_ADDR((regions[i].start +
    2798:	3f01      	subs	r7, #1
	attr->rbar = MPU->RBAR &
    279a:	f362 0304 	bfi	r3, r2, #0, #5
    279e:	f88d 3008 	strb.w	r3, [sp, #8]
	attr->mair_idx = (MPU->RLAR & MPU_RLAR_AttrIndx_Msk) >>
    27a2:	692b      	ldr	r3, [r5, #16]
    27a4:	f89d 2008 	ldrb.w	r2, [sp, #8]
    27a8:	085b      	lsrs	r3, r3, #1
    27aa:	f363 1247 	bfi	r2, r3, #5, #3
    27ae:	f88d 2008 	strb.w	r2, [sp, #8]
			fill_region.base = regions[i].start +
    27b2:	e9d6 3200 	ldrd	r3, r2, [r6]
    27b6:	4413      	add	r3, r2
    27b8:	9300      	str	r3, [sp, #0]
			REGION_LIMIT_ADDR((regions[i].start +
    27ba:	f023 031f 	bic.w	r3, r3, #31
    27be:	443b      	add	r3, r7
			reg_index++;
    27c0:	1c44      	adds	r4, r0, #1
			REGION_LIMIT_ADDR((regions[i].start +
    27c2:	eba3 0a0a 	sub.w	sl, r3, sl
    27c6:	b2e0      	uxtb	r0, r4
    27c8:	f02a 031f 	bic.w	r3, sl, #31

static int region_allocate_and_init(const uint8_t index,
	const struct arm_mpu_region *region_conf)
{
	/* Attempt to allocate new region index. */
	if (index > (get_num_regions() - 1U)) {
    27cc:	280f      	cmp	r0, #15
			fill_region.attr.r_limit =
    27ce:	9303      	str	r3, [sp, #12]
    27d0:	f63f af77 	bhi.w	26c2 <mpu_configure_regions_and_partition.constprop.0+0x1e>
	}

	LOG_DBG("Program MPU region at index 0x%x", index);

	/* Program region */
	region_init(index, region_conf);
    27d4:	4669      	mov	r1, sp
    27d6:	f7ff ff4d 	bl	2674 <region_init>
    27da:	e7bc      	b.n	2756 <mpu_configure_regions_and_partition.constprop.0+0xb2>
    27dc:	e000ed90 	.word	0xe000ed90

000027e0 <arm_core_mpu_enable>:
void arm_core_mpu_enable(void)
{
	/* Enable MPU and use the default memory map as a
	 * background region for privileged software access.
	 */
	MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
    27e0:	2205      	movs	r2, #5
    27e2:	4b03      	ldr	r3, [pc, #12]	; (27f0 <arm_core_mpu_enable+0x10>)
    27e4:	605a      	str	r2, [r3, #4]
  __ASM volatile ("dsb 0xF":::"memory");
    27e6:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    27ea:	f3bf 8f6f 	isb	sy

	/* Make sure that all the registers are set before proceeding */
	__DSB();
	__ISB();
}
    27ee:	4770      	bx	lr
    27f0:	e000ed90 	.word	0xe000ed90

000027f4 <arm_core_mpu_disable>:
  \details Ensures the apparent order of the explicit memory operations before
           and after the instruction, without ensuring their completion.
 */
__STATIC_FORCEINLINE void __DMB(void)
{
  __ASM volatile ("dmb 0xF":::"memory");
    27f4:	f3bf 8f5f 	dmb	sy
{
	/* Force any outstanding transfers to complete before disabling MPU */
	__DMB();

	/* Disable MPU */
	MPU->CTRL = 0;
    27f8:	2200      	movs	r2, #0
    27fa:	4b01      	ldr	r3, [pc, #4]	; (2800 <arm_core_mpu_disable+0xc>)
    27fc:	605a      	str	r2, [r3, #4]
}
    27fe:	4770      	bx	lr
    2800:	e000ed90 	.word	0xe000ed90

00002804 <arm_mpu_init>:
 *
 * This function provides the default configuration mechanism for the Memory
 * Protection Unit (MPU).
 */
static int arm_mpu_init(const struct device *arg)
{
    2804:	b538      	push	{r3, r4, r5, lr}
	uint32_t r_index;

	if (mpu_config.num_regions > get_num_regions()) {
    2806:	4c0e      	ldr	r4, [pc, #56]	; (2840 <arm_mpu_init+0x3c>)
    2808:	6825      	ldr	r5, [r4, #0]
    280a:	2d10      	cmp	r5, #16
    280c:	d814      	bhi.n	2838 <arm_mpu_init+0x34>
		return -1;
	}

	LOG_DBG("total region count: %d", get_num_regions());

	arm_core_mpu_disable();
    280e:	f7ff fff1 	bl	27f4 <arm_core_mpu_disable>

	/* Architecture-specific configuration */
	mpu_init();

	/* Program fixed regions configured at SOC definition. */
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    2812:	2000      	movs	r0, #0
	MPU->MAIR0 =
    2814:	4b0b      	ldr	r3, [pc, #44]	; (2844 <arm_mpu_init+0x40>)
    2816:	4a0c      	ldr	r2, [pc, #48]	; (2848 <arm_mpu_init+0x44>)
    2818:	631a      	str	r2, [r3, #48]	; 0x30
    281a:	4285      	cmp	r5, r0
    281c:	d105      	bne.n	282a <arm_mpu_init+0x26>
		region_init(r_index, &mpu_config.mpu_regions[r_index]);
	}

	/* Update the number of programmed MPU regions. */
	static_regions_num = mpu_config.num_regions;
    281e:	4b0b      	ldr	r3, [pc, #44]	; (284c <arm_mpu_init+0x48>)
    2820:	701d      	strb	r5, [r3, #0]


	arm_core_mpu_enable();
    2822:	f7ff ffdd 	bl	27e0 <arm_core_mpu_enable>
	__ASSERT(
		(MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos ==
		NUM_MPU_REGIONS,
		"Invalid number of MPU regions\n");
#endif /* CORTEX_M0PLUS || CPU_CORTEX_M3 || CPU_CORTEX_M4 */
	return 0;
    2826:	2000      	movs	r0, #0
}
    2828:	bd38      	pop	{r3, r4, r5, pc}
		region_init(r_index, &mpu_config.mpu_regions[r_index]);
    282a:	6861      	ldr	r1, [r4, #4]
    282c:	eb01 1100 	add.w	r1, r1, r0, lsl #4
    2830:	f7ff ff20 	bl	2674 <region_init>
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    2834:	3001      	adds	r0, #1
    2836:	e7f0      	b.n	281a <arm_mpu_init+0x16>
		return -1;
    2838:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
    283c:	e7f4      	b.n	2828 <arm_mpu_init+0x24>
    283e:	bf00      	nop
    2840:	000060a4 	.word	0x000060a4
    2844:	e000ed90 	.word	0xe000ed90
    2848:	0044ffaa 	.word	0x0044ffaa
    284c:	200008ac 	.word	0x200008ac

00002850 <arm_core_mpu_configure_static_mpu_regions>:
{
    2850:	b510      	push	{r4, lr}
static int mpu_configure_static_mpu_regions(const struct z_arm_mpu_partition
	static_regions[], const uint8_t regions_num,
	const uint32_t background_area_base,
	const uint32_t background_area_end)
{
	int mpu_reg_index = static_regions_num;
    2852:	4c03      	ldr	r4, [pc, #12]	; (2860 <arm_core_mpu_configure_static_mpu_regions+0x10>)
	 * given boundaries.
	 */
	ARG_UNUSED(background_area_base);
	ARG_UNUSED(background_area_end);

	mpu_reg_index = mpu_configure_regions_and_partition(static_regions,
    2854:	7822      	ldrb	r2, [r4, #0]
    2856:	f7ff ff25 	bl	26a4 <mpu_configure_regions_and_partition.constprop.0>
		regions_num, mpu_reg_index, true);

	static_regions_num = mpu_reg_index;
    285a:	7020      	strb	r0, [r4, #0]
}
    285c:	bd10      	pop	{r4, pc}
    285e:	bf00      	nop
    2860:	200008ac 	.word	0x200008ac

00002864 <arm_core_mpu_mark_areas_for_dynamic_regions>:
{
    2864:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    2868:	4d26      	ldr	r5, [pc, #152]	; (2904 <arm_core_mpu_mark_areas_for_dynamic_regions+0xa0>)
    286a:	468a      	mov	sl, r1
{
	/* In ARMv8-M architecture we need to store the index values
	 * and the default configuration of the MPU regions, inside
	 * which dynamic memory regions may be programmed at run-time.
	 */
	for (int i = 0; i < dyn_region_areas_num; i++) {
    286c:	4606      	mov	r6, r0
    286e:	f04f 0800 	mov.w	r8, #0
    2872:	46ab      	mov	fp, r5
	MPU->RNR = index;
    2874:	4f24      	ldr	r7, [pc, #144]	; (2908 <arm_core_mpu_mark_areas_for_dynamic_regions+0xa4>)
	for (int i = 0; i < dyn_region_areas_num; i++) {
    2876:	45d0      	cmp	r8, sl
    2878:	da1b      	bge.n	28b2 <arm_core_mpu_mark_areas_for_dynamic_regions+0x4e>
		if (dyn_region_areas[i].size == 0U) {
    287a:	f8d6 9004 	ldr.w	r9, [r6, #4]
    287e:	f1b9 0f00 	cmp.w	r9, #0
    2882:	d039      	beq.n	28f8 <arm_core_mpu_mark_areas_for_dynamic_regions+0x94>
		}
		/* Non-empty area */

		/* Retrieve HW MPU region index */
		dyn_reg_info[i].index =
			get_region_index(dyn_region_areas[i].start,
    2884:	6831      	ldr	r1, [r6, #0]
	uint32_t region_start_addr = arm_cmse_mpu_region_get(start);
    2886:	4608      	mov	r0, r1
    2888:	9101      	str	r1, [sp, #4]
    288a:	f002 ffdf 	bl	584c <arm_cmse_mpu_region_get>
	uint32_t region_end_addr = arm_cmse_mpu_region_get(start + size - 1);
    288e:	9901      	ldr	r1, [sp, #4]
	uint32_t region_start_addr = arm_cmse_mpu_region_get(start);
    2890:	4604      	mov	r4, r0
	uint32_t region_end_addr = arm_cmse_mpu_region_get(start + size - 1);
    2892:	eb09 0001 	add.w	r0, r9, r1
    2896:	3801      	subs	r0, #1
    2898:	f002 ffd8 	bl	584c <arm_cmse_mpu_region_get>
	if (region_start_addr == region_end_addr) {
    289c:	4284      	cmp	r4, r0
    289e:	f04f 0214 	mov.w	r2, #20
    28a2:	4b1a      	ldr	r3, [pc, #104]	; (290c <arm_core_mpu_mark_areas_for_dynamic_regions+0xa8>)
    28a4:	d008      	beq.n	28b8 <arm_core_mpu_mark_areas_for_dynamic_regions+0x54>
		dyn_reg_info[i].index =
    28a6:	f06f 0315 	mvn.w	r3, #21
    28aa:	fb02 f808 	mul.w	r8, r2, r8
    28ae:	f84b 3008 	str.w	r3, [fp, r8]
}
    28b2:	b003      	add	sp, #12
    28b4:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
					dyn_region_areas[i].size);

		if (dyn_reg_info[i].index == -EINVAL) {
    28b8:	f114 0f16 	cmn.w	r4, #22
		dyn_reg_info[i].index =
    28bc:	602c      	str	r4, [r5, #0]
		if (dyn_reg_info[i].index == -EINVAL) {
    28be:	d0f8      	beq.n	28b2 <arm_core_mpu_mark_areas_for_dynamic_regions+0x4e>

			return -EINVAL;
		}

		if (dyn_reg_info[i].index >= static_regions_num) {
    28c0:	7819      	ldrb	r1, [r3, #0]
    28c2:	42a1      	cmp	r1, r4
    28c4:	ddf5      	ble.n	28b2 <arm_core_mpu_mark_areas_for_dynamic_regions+0x4e>
	attr->rbar = MPU->RBAR &
    28c6:	fb02 b008 	mla	r0, r2, r8, fp
	MPU->RNR = index;
    28ca:	60bc      	str	r4, [r7, #8]
	MPU->RNR = index;
    28cc:	60bc      	str	r4, [r7, #8]
	attr->rbar = MPU->RBAR &
    28ce:	68fc      	ldr	r4, [r7, #12]
    28d0:	f100 0108 	add.w	r1, r0, #8
    28d4:	7b00      	ldrb	r0, [r0, #12]
    28d6:	f364 0004 	bfi	r0, r4, #0, #5
    28da:	7108      	strb	r0, [r1, #4]
	attr->mair_idx = (MPU->RLAR & MPU_RLAR_AttrIndx_Msk) >>
    28dc:	6938      	ldr	r0, [r7, #16]
    28de:	790c      	ldrb	r4, [r1, #4]
    28e0:	0840      	lsrs	r0, r0, #1
    28e2:	f360 1447 	bfi	r4, r0, #5, #3
    28e6:	710c      	strb	r4, [r1, #4]
	region_conf->base = (MPU->RBAR & MPU_RBAR_BASE_Msk);
    28e8:	68f9      	ldr	r1, [r7, #12]
    28ea:	f021 011f 	bic.w	r1, r1, #31
    28ee:	6069      	str	r1, [r5, #4]
	region_conf->attr.r_limit = MPU->RLAR & MPU_RLAR_LIMIT_Msk;
    28f0:	6939      	ldr	r1, [r7, #16]
    28f2:	f021 011f 	bic.w	r1, r1, #31
    28f6:	6129      	str	r1, [r5, #16]
	for (int i = 0; i < dyn_region_areas_num; i++) {
    28f8:	f108 0801 	add.w	r8, r8, #1
    28fc:	3514      	adds	r5, #20
    28fe:	360c      	adds	r6, #12
    2900:	e7b9      	b.n	2876 <arm_core_mpu_mark_areas_for_dynamic_regions+0x12>
    2902:	bf00      	nop
    2904:	200007c4 	.word	0x200007c4
    2908:	e000ed90 	.word	0xe000ed90
    290c:	200008ac 	.word	0x200008ac

00002910 <tz_nonsecure_state_setup>:
}
#endif /* CONFIG_ARMV8_M_MAINLINE */

void tz_nonsecure_state_setup(const tz_nonsecure_setup_conf_t *p_ns_conf)
{
	configure_nonsecure_vtor_offset(p_ns_conf->vtor_ns);
    2910:	6882      	ldr	r2, [r0, #8]
	SCB_NS->VTOR = vtor_ns;
    2912:	4b0c      	ldr	r3, [pc, #48]	; (2944 <tz_nonsecure_state_setup+0x34>)
    2914:	609a      	str	r2, [r3, #8]
  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
    2916:	6803      	ldr	r3, [r0, #0]
    2918:	f383 8888 	msr	MSP_NS, r3
  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
    291c:	6843      	ldr	r3, [r0, #4]
    291e:	f383 8889 	msr	PSP_NS, r3
	configure_nonsecure_psp(p_ns_conf->psp_ns);
	/* Select which stack-pointer to use (MSP or PSP) and
	 * the privilege level for thread mode.
	 */
	configure_nonsecure_control(p_ns_conf->control_ns.spsel,
		p_ns_conf->control_ns.npriv);
    2922:	7b02      	ldrb	r2, [r0, #12]
    2924:	f002 0101 	and.w	r1, r2, #1
  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
    2928:	f3ef 8394 	mrs	r3, CONTROL_NS
	control_ns &= ~(CONTROL_SPSEL_Msk | CONTROL_nPRIV_Msk);
    292c:	f023 0303 	bic.w	r3, r3, #3
	if (spsel_ns) {
    2930:	0792      	lsls	r2, r2, #30
		control_ns |= CONTROL_SPSEL_Msk;
    2932:	bf48      	it	mi
    2934:	f043 0302 	orrmi.w	r3, r3, #2
	if (npriv_ns) {
    2938:	b109      	cbz	r1, 293e <tz_nonsecure_state_setup+0x2e>
		control_ns |= CONTROL_nPRIV_Msk;
    293a:	f043 0301 	orr.w	r3, r3, #1
  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
    293e:	f383 8894 	msr	CONTROL_NS, r3
}
    2942:	4770      	bx	lr
    2944:	e002ed00 	.word	0xe002ed00

00002948 <tz_nbanked_exception_target_state_set>:

void tz_nbanked_exception_target_state_set(int secure_state)
{
	uint32_t aircr_payload = SCB->AIRCR & (~(SCB_AIRCR_VECTKEY_Msk));
    2948:	4a08      	ldr	r2, [pc, #32]	; (296c <tz_nbanked_exception_target_state_set+0x24>)
    294a:	68d3      	ldr	r3, [r2, #12]
	if (secure_state) {
    294c:	b148      	cbz	r0, 2962 <tz_nbanked_exception_target_state_set+0x1a>
		aircr_payload &= ~(SCB_AIRCR_BFHFNMINS_Msk);
    294e:	f423 5300 	bic.w	r3, r3, #8192	; 0x2000
    2952:	041b      	lsls	r3, r3, #16
    2954:	0c1b      	lsrs	r3, r3, #16
	} else {
		aircr_payload |= SCB_AIRCR_BFHFNMINS_Msk;
	}
	SCB->AIRCR = ((AIRCR_VECT_KEY_PERMIT_WRITE << SCB_AIRCR_VECTKEY_Pos)
			& SCB_AIRCR_VECTKEY_Msk)
		| aircr_payload;
    2956:	f043 63bf 	orr.w	r3, r3, #100139008	; 0x5f80000
    295a:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
	SCB->AIRCR = ((AIRCR_VECT_KEY_PERMIT_WRITE << SCB_AIRCR_VECTKEY_Pos)
    295e:	60d3      	str	r3, [r2, #12]
}
    2960:	4770      	bx	lr
	uint32_t aircr_payload = SCB->AIRCR & (~(SCB_AIRCR_VECTKEY_Msk));
    2962:	b29b      	uxth	r3, r3
		aircr_payload |= SCB_AIRCR_BFHFNMINS_Msk;
    2964:	f443 5300 	orr.w	r3, r3, #8192	; 0x2000
    2968:	e7f5      	b.n	2956 <tz_nbanked_exception_target_state_set+0xe>
    296a:	bf00      	nop
    296c:	e000ed00 	.word	0xe000ed00

00002970 <tz_nonsecure_exception_prio_config>:

void tz_nonsecure_exception_prio_config(int secure_boost)
{
	uint32_t aircr_payload = SCB->AIRCR & (~(SCB_AIRCR_VECTKEY_Msk));
    2970:	4a08      	ldr	r2, [pc, #32]	; (2994 <tz_nonsecure_exception_prio_config+0x24>)
    2972:	68d3      	ldr	r3, [r2, #12]
	if (secure_boost) {
    2974:	b140      	cbz	r0, 2988 <tz_nonsecure_exception_prio_config+0x18>
	uint32_t aircr_payload = SCB->AIRCR & (~(SCB_AIRCR_VECTKEY_Msk));
    2976:	b29b      	uxth	r3, r3
		aircr_payload |= SCB_AIRCR_PRIS_Msk;
    2978:	f443 4380 	orr.w	r3, r3, #16384	; 0x4000
	} else {
		aircr_payload &= ~(SCB_AIRCR_PRIS_Msk);
	}
	SCB->AIRCR = ((AIRCR_VECT_KEY_PERMIT_WRITE << SCB_AIRCR_VECTKEY_Pos)
			& SCB_AIRCR_VECTKEY_Msk)
		| aircr_payload;
    297c:	f043 63bf 	orr.w	r3, r3, #100139008	; 0x5f80000
    2980:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
	SCB->AIRCR = ((AIRCR_VECT_KEY_PERMIT_WRITE << SCB_AIRCR_VECTKEY_Pos)
    2984:	60d3      	str	r3, [r2, #12]
}
    2986:	4770      	bx	lr
		aircr_payload &= ~(SCB_AIRCR_PRIS_Msk);
    2988:	f423 4380 	bic.w	r3, r3, #16384	; 0x4000
    298c:	041b      	lsls	r3, r3, #16
    298e:	0c1b      	lsrs	r3, r3, #16
    2990:	e7f4      	b.n	297c <tz_nonsecure_exception_prio_config+0xc>
    2992:	bf00      	nop
    2994:	e000ed00 	.word	0xe000ed00

00002998 <tz_nonsecure_system_reset_req_block>:

void tz_nonsecure_system_reset_req_block(int block)
{
	uint32_t aircr_payload = SCB->AIRCR & (~(SCB_AIRCR_VECTKEY_Msk));
    2998:	4a08      	ldr	r2, [pc, #32]	; (29bc <tz_nonsecure_system_reset_req_block+0x24>)
    299a:	68d3      	ldr	r3, [r2, #12]
	if (block) {
    299c:	b140      	cbz	r0, 29b0 <tz_nonsecure_system_reset_req_block+0x18>
	uint32_t aircr_payload = SCB->AIRCR & (~(SCB_AIRCR_VECTKEY_Msk));
    299e:	b29b      	uxth	r3, r3
		aircr_payload |= SCB_AIRCR_SYSRESETREQS_Msk;
    29a0:	f043 0308 	orr.w	r3, r3, #8
	} else {
		aircr_payload &= ~(SCB_AIRCR_SYSRESETREQS_Msk);
	}
	SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)
			& SCB_AIRCR_VECTKEY_Msk)
		| aircr_payload;
    29a4:	f043 63bf 	orr.w	r3, r3, #100139008	; 0x5f80000
    29a8:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
	SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)
    29ac:	60d3      	str	r3, [r2, #12]
}
    29ae:	4770      	bx	lr
		aircr_payload &= ~(SCB_AIRCR_SYSRESETREQS_Msk);
    29b0:	f023 0308 	bic.w	r3, r3, #8
    29b4:	041b      	lsls	r3, r3, #16
    29b6:	0c1b      	lsrs	r3, r3, #16
    29b8:	e7f4      	b.n	29a4 <tz_nonsecure_system_reset_req_block+0xc>
    29ba:	bf00      	nop
    29bc:	e000ed00 	.word	0xe000ed00

000029c0 <tz_nonsecure_fpu_access_enable>:

#if defined(CONFIG_ARMV7_M_ARMV8_M_FP)
void tz_nonsecure_fpu_access_enable(void)
{
	SCB->NSACR |=
    29c0:	4a03      	ldr	r2, [pc, #12]	; (29d0 <tz_nonsecure_fpu_access_enable+0x10>)
    29c2:	f8d2 308c 	ldr.w	r3, [r2, #140]	; 0x8c
    29c6:	f443 6340 	orr.w	r3, r3, #3072	; 0xc00
    29ca:	f8c2 308c 	str.w	r3, [r2, #140]	; 0x8c
		(1UL << SCB_NSACR_CP10_Pos) | (1UL << SCB_NSACR_CP11_Pos);
}
    29ce:	4770      	bx	lr
    29d0:	e000ed00 	.word	0xe000ed00

000029d4 <tz_sau_configure>:
#endif /* CONFIG_ARMV7_M_ARMV8_M_FP */

void tz_sau_configure(int enable, int allns)
{
	if (enable) {
    29d4:	4b08      	ldr	r3, [pc, #32]	; (29f8 <tz_sau_configure+0x24>)
  \brief   Enable SAU
  \details Enables the Security Attribution Unit (SAU).
 */
__STATIC_INLINE void TZ_SAU_Enable(void)
{
    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
    29d6:	681a      	ldr	r2, [r3, #0]
    29d8:	b118      	cbz	r0, 29e2 <tz_sau_configure+0xe>
    29da:	f042 0201 	orr.w	r2, r2, #1
	} else {
		TZ_SAU_Disable();
		if (allns) {
			SAU->CTRL |= SAU_CTRL_ALLNS_Msk;
		} else {
			SAU->CTRL &= ~(SAU_CTRL_ALLNS_Msk);
    29de:	601a      	str	r2, [r3, #0]
		}
	}
}
    29e0:	4770      	bx	lr
  \brief   Disable SAU
  \details Disables the Security Attribution Unit (SAU).
 */
__STATIC_INLINE void TZ_SAU_Disable(void)
{
    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
    29e2:	f022 0201 	bic.w	r2, r2, #1
    29e6:	601a      	str	r2, [r3, #0]
			SAU->CTRL |= SAU_CTRL_ALLNS_Msk;
    29e8:	681a      	ldr	r2, [r3, #0]
		if (allns) {
    29ea:	b111      	cbz	r1, 29f2 <tz_sau_configure+0x1e>
			SAU->CTRL |= SAU_CTRL_ALLNS_Msk;
    29ec:	f042 0202 	orr.w	r2, r2, #2
    29f0:	e7f5      	b.n	29de <tz_sau_configure+0xa>
			SAU->CTRL &= ~(SAU_CTRL_ALLNS_Msk);
    29f2:	f022 0202 	bic.w	r2, r2, #2
    29f6:	e7f2      	b.n	29de <tz_sau_configure+0xa>
    29f8:	e000edd0 	.word	0xe000edd0

000029fc <nrf_gpio_cfg_sense_set>:

NRF_STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t             pin_number,
                                              nrf_gpio_pin_sense_t sense_config)
{
    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_SENSE_Msk;
    29fc:	4a06      	ldr	r2, [pc, #24]	; (2a18 <nrf_gpio_cfg_sense_set+0x1c>)
}

NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin)
{
    uint32_t pin_number = *p_pin;
    *p_pin = pin_number & 0x1F;
    29fe:	f000 001f 	and.w	r0, r0, #31
    2a02:	eb02 0080 	add.w	r0, r2, r0, lsl #2
    uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_SENSE_Msk;
    2a06:	f8d0 3200 	ldr.w	r3, [r0, #512]	; 0x200
    2a0a:	f423 3340 	bic.w	r3, r3, #196608	; 0x30000
    reg->PIN_CNF[pin_number] = cnf | (sense_config << GPIO_PIN_CNF_SENSE_Pos);
    2a0e:	ea43 4101 	orr.w	r1, r3, r1, lsl #16
    2a12:	f8c0 1200 	str.w	r1, [r0, #512]	; 0x200
}
    2a16:	4770      	bx	lr
    2a18:	50842500 	.word	0x50842500

00002a1c <gpio_nrfx_init>:
}

#define GPIOTE_NODE DT_INST(0, nordic_nrf_gpiote)

static int gpio_nrfx_init(const struct device *port)
{
    2a1c:	b508      	push	{r3, lr}
	static bool gpio_initialized;

	if (!gpio_initialized) {
    2a1e:	4b09      	ldr	r3, [pc, #36]	; (2a44 <gpio_nrfx_init+0x28>)
    2a20:	781a      	ldrb	r2, [r3, #0]
    2a22:	b96a      	cbnz	r2, 2a40 <gpio_nrfx_init+0x24>
		gpio_initialized = true;
    2a24:	2101      	movs	r1, #1
		IRQ_CONNECT(DT_IRQN(GPIOTE_NODE), DT_IRQ(GPIOTE_NODE, priority),
    2a26:	200d      	movs	r0, #13
		gpio_initialized = true;
    2a28:	7019      	strb	r1, [r3, #0]
		IRQ_CONNECT(DT_IRQN(GPIOTE_NODE), DT_IRQ(GPIOTE_NODE, priority),
    2a2a:	2105      	movs	r1, #5
    2a2c:	f7ff fbc4 	bl	21b8 <z_arm_irq_priority_set>
			    gpiote_event_handler, NULL, 0);

		irq_enable(DT_IRQN(GPIOTE_NODE));
    2a30:	200d      	movs	r0, #13
    2a32:	f7ff fba3 	bl	217c <arch_irq_enable>
    return ((uint32_t)p_reg + event);
}

NRF_STATIC_INLINE void nrf_gpiote_int_enable(NRF_GPIOTE_Type * p_reg, uint32_t mask)
{
    p_reg->INTENSET = mask;
    2a36:	f04f 4200 	mov.w	r2, #2147483648	; 0x80000000
    2a3a:	4b03      	ldr	r3, [pc, #12]	; (2a48 <gpio_nrfx_init+0x2c>)
    2a3c:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
		nrf_gpiote_int_enable(NRF_GPIOTE, NRF_GPIOTE_INT_PORT_MASK);
	}

	return 0;
}
    2a40:	2000      	movs	r0, #0
    2a42:	bd08      	pop	{r3, pc}
    2a44:	200008ad 	.word	0x200008ad
    2a48:	5000d000 	.word	0x5000d000

00002a4c <gpio_nrfx_pin_interrupt_configure>:
{
    2a4c:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
    2a4e:	460e      	mov	r6, r1
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
    2a50:	6841      	ldr	r1, [r0, #4]
    2a52:	f006 051f 	and.w	r5, r6, #31
    2a56:	7a09      	ldrb	r1, [r1, #8]
	if ((mode == GPIO_INT_MODE_EDGE) &&
    2a58:	f5b2 3fa0 	cmp.w	r2, #81920	; 0x14000
	struct gpio_nrfx_data *data = get_port_data(port);
    2a5c:	68c7      	ldr	r7, [r0, #12]
	if ((mode == GPIO_INT_MODE_EDGE) &&
    2a5e:	ea45 1541 	orr.w	r5, r5, r1, lsl #5
    2a62:	d10a      	bne.n	2a7a <gpio_nrfx_pin_interrupt_configure+0x2e>
    return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
    2a64:	485c      	ldr	r0, [pc, #368]	; (2bd8 <gpio_nrfx_pin_interrupt_configure+0x18c>)
    *p_pin = pin_number & 0x1F;
    2a66:	f005 011f 	and.w	r1, r5, #31
    return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
    2a6a:	3180      	adds	r1, #128	; 0x80
    2a6c:	f850 1021 	ldr.w	r1, [r0, r1, lsl #2]
    2a70:	07c8      	lsls	r0, r1, #31
    2a72:	d507      	bpl.n	2a84 <gpio_nrfx_pin_interrupt_configure+0x38>
		return -ENOTSUP;
    2a74:	f06f 0022 	mvn.w	r0, #34	; 0x22
    2a78:	e093      	b.n	2ba2 <gpio_nrfx_pin_interrupt_configure+0x156>
	WRITE_BIT(data->pin_int_en, pin, mode != GPIO_INT_MODE_DISABLED);
    2a7a:	f5b2 5f00 	cmp.w	r2, #8192	; 0x2000
    2a7e:	68f9      	ldr	r1, [r7, #12]
    2a80:	f000 8091 	beq.w	2ba6 <gpio_nrfx_pin_interrupt_configure+0x15a>
    2a84:	2101      	movs	r1, #1
    2a86:	68f8      	ldr	r0, [r7, #12]
    2a88:	40b1      	lsls	r1, r6
    2a8a:	4301      	orrs	r1, r0
    2a8c:	60f9      	str	r1, [r7, #12]
	WRITE_BIT(data->trig_edge, pin, mode == GPIO_INT_MODE_EDGE);
    2a8e:	2101      	movs	r1, #1
    2a90:	6978      	ldr	r0, [r7, #20]
    2a92:	40b1      	lsls	r1, r6
    2a94:	f5b2 3fa0 	cmp.w	r2, #81920	; 0x14000
    2a98:	bf0c      	ite	eq
    2a9a:	4308      	orreq	r0, r1
    2a9c:	4388      	bicne	r0, r1
    2a9e:	6178      	str	r0, [r7, #20]
	for (size_t i = 0; i < GPIOTE_CH_NUM; i++) {
    2aa0:	2000      	movs	r0, #0
    2aa2:	69ba      	ldr	r2, [r7, #24]
	WRITE_BIT(data->double_edge, pin, trig == GPIO_INT_TRIG_BOTH);
    2aa4:	f5b3 2fc0 	cmp.w	r3, #393216	; 0x60000
    2aa8:	bf0c      	ite	eq
    2aaa:	430a      	orreq	r2, r1
    2aac:	438a      	bicne	r2, r1
    2aae:	61ba      	str	r2, [r7, #24]
	WRITE_BIT(data->int_active_level, pin, trig == GPIO_INT_TRIG_HIGH);
    2ab0:	693a      	ldr	r2, [r7, #16]
    2ab2:	f5b3 2f80 	cmp.w	r3, #262144	; 0x40000
    2ab6:	bf0c      	ite	eq
    2ab8:	4311      	orreq	r1, r2
    2aba:	ea22 0101 	bicne.w	r1, r2, r1
    p_reg->INTENCLR = mask;
}

NRF_STATIC_INLINE uint32_t nrf_gpiote_int_enable_check(NRF_GPIOTE_Type const * p_reg, uint32_t mask)
{
    return p_reg->INTENSET & mask;
    2abe:	4a47      	ldr	r2, [pc, #284]	; (2bdc <gpio_nrfx_pin_interrupt_configure+0x190>)
    2ac0:	6139      	str	r1, [r7, #16]
    2ac2:	f8d2 3304 	ldr.w	r3, [r2, #772]	; 0x304
    2ac6:	b2db      	uxtb	r3, r3
                        ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk);
}

NRF_STATIC_INLINE uint32_t nrf_gpiote_event_pin_get(NRF_GPIOTE_Type const * p_reg, uint32_t idx)
{
    return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
    2ac8:	f500 71a2 	add.w	r1, r0, #324	; 0x144
    2acc:	f852 1021 	ldr.w	r1, [r2, r1, lsl #2]
    2ad0:	f3c1 2104 	ubfx	r1, r1, #8, #5
		if ((nrf_gpiote_event_pin_get(NRF_GPIOTE, i) == abs_pin)
    2ad4:	428d      	cmp	r5, r1
    2ad6:	d16b      	bne.n	2bb0 <gpio_nrfx_pin_interrupt_configure+0x164>
		    && (intenset & BIT(i))) {
    2ad8:	fa23 f100 	lsr.w	r1, r3, r0
    2adc:	07c9      	lsls	r1, r1, #31
    2ade:	d567      	bpl.n	2bb0 <gpio_nrfx_pin_interrupt_configure+0x164>
   p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Event;
    2ae0:	0083      	lsls	r3, r0, #2
    2ae2:	f103 43a0 	add.w	r3, r3, #1342177280	; 0x50000000
    2ae6:	f503 4350 	add.w	r3, r3, #53248	; 0xd000
    2aea:	f8d3 1510 	ldr.w	r1, [r3, #1296]	; 0x510
    2aee:	f021 0101 	bic.w	r1, r1, #1
    2af2:	f8c3 1510 	str.w	r1, [r3, #1296]	; 0x510
			nrf_gpiote_int_disable(NRF_GPIOTE, BIT(i));
    2af6:	2301      	movs	r3, #1
    2af8:	4083      	lsls	r3, r0
    p_reg->INTENCLR = mask;
    2afa:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
			nrfx_gpiote_channel_free(i);
    2afe:	b2c0      	uxtb	r0, r0
    2b00:	f000 fb1e 	bl	3140 <nrfx_gpiote_channel_free>
	nrf_gpio_cfg_sense_set(abs_pin, NRF_GPIO_PIN_NOSENSE);
    2b04:	4628      	mov	r0, r5
    2b06:	2100      	movs	r1, #0
    2b08:	f7ff ff78 	bl	29fc <nrf_gpio_cfg_sense_set>
	if (data->pin_int_en & BIT(pin)) {
    2b0c:	68f8      	ldr	r0, [r7, #12]
    2b0e:	40f0      	lsrs	r0, r6
    2b10:	f010 0001 	ands.w	r0, r0, #1
    2b14:	d045      	beq.n	2ba2 <gpio_nrfx_pin_interrupt_configure+0x156>
		if (data->trig_edge & BIT(pin)) {
    2b16:	6978      	ldr	r0, [r7, #20]
    2b18:	40f0      	lsrs	r0, r6
    2b1a:	f010 0401 	ands.w	r4, r0, #1
    2b1e:	d04e      	beq.n	2bbe <gpio_nrfx_pin_interrupt_configure+0x172>
			if (data->double_edge & BIT(pin)) {
    2b20:	69bb      	ldr	r3, [r7, #24]
	if (nrfx_gpiote_channel_alloc(&channel) != NRFX_SUCCESS) {
    2b22:	f10d 0007 	add.w	r0, sp, #7
			if (data->double_edge & BIT(pin)) {
    2b26:	40f3      	lsrs	r3, r6
    2b28:	07db      	lsls	r3, r3, #31
			} else if ((data->int_active_level & BIT(pin)) != 0U) {
    2b2a:	bf57      	itett	pl
    2b2c:	6939      	ldrpl	r1, [r7, #16]
				pol = NRF_GPIOTE_POLARITY_TOGGLE;
    2b2e:	2603      	movmi	r6, #3
			} else if ((data->int_active_level & BIT(pin)) != 0U) {
    2b30:	fa21 f606 	lsrpl.w	r6, r1, r6
    2b34:	f006 0601 	andpl.w	r6, r6, #1
    2b38:	bf5c      	itt	pl
    2b3a:	f1c6 0602 	rsbpl	r6, r6, #2
    2b3e:	b2f6      	uxtbpl	r6, r6
	if (nrfx_gpiote_channel_alloc(&channel) != NRFX_SUCCESS) {
    2b40:	f000 fb20 	bl	3184 <nrfx_gpiote_channel_alloc>
    2b44:	4b26      	ldr	r3, [pc, #152]	; (2be0 <gpio_nrfx_pin_interrupt_configure+0x194>)
    2b46:	4298      	cmp	r0, r3
    2b48:	d136      	bne.n	2bb8 <gpio_nrfx_pin_interrupt_configure+0x16c>
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    2b4a:	2000      	movs	r0, #0
	nrf_gpiote_event_t evt = offsetof(NRF_GPIOTE_Type, EVENTS_IN[channel]);
    2b4c:	f89d 1007 	ldrb.w	r1, [sp, #7]
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    2b50:	022d      	lsls	r5, r5, #8
    2b52:	008b      	lsls	r3, r1, #2
    2b54:	f103 43a0 	add.w	r3, r3, #1342177280	; 0x50000000
    2b58:	f503 4350 	add.w	r3, r3, #53248	; 0xd000
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk);
    2b5c:	f8d3 2510 	ldr.w	r2, [r3, #1296]	; 0x510
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    2b60:	f405 55f8 	and.w	r5, r5, #7936	; 0x1f00
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk);
    2b64:	f422 3247 	bic.w	r2, r2, #203776	; 0x31c00
    2b68:	f422 7240 	bic.w	r2, r2, #768	; 0x300
    2b6c:	f8c3 2510 	str.w	r2, [r3, #1296]	; 0x510
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    2b70:	f8d3 2510 	ldr.w	r2, [r3, #1296]	; 0x510
    2b74:	4315      	orrs	r5, r2
    return ((uint32_t)p_reg + event);
    2b76:	008a      	lsls	r2, r1, #2
    2b78:	f102 42a0 	add.w	r2, r2, #1342177280	; 0x50000000
    2b7c:	f502 4251 	add.w	r2, r2, #53504	; 0xd100
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    2b80:	ea45 4606 	orr.w	r6, r5, r6, lsl #16
    2b84:	f8c3 6510 	str.w	r6, [r3, #1296]	; 0x510
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    2b88:	6010      	str	r0, [r2, #0]
    2b8a:	6812      	ldr	r2, [r2, #0]
   p_reg->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event;
    2b8c:	f8d3 2510 	ldr.w	r2, [r3, #1296]	; 0x510
    2b90:	f042 0201 	orr.w	r2, r2, #1
    2b94:	f8c3 2510 	str.w	r2, [r3, #1296]	; 0x510
	nrf_gpiote_int_enable(NRF_GPIOTE, BIT(channel));
    2b98:	2301      	movs	r3, #1
    p_reg->INTENSET = mask;
    2b9a:	4a10      	ldr	r2, [pc, #64]	; (2bdc <gpio_nrfx_pin_interrupt_configure+0x190>)
    2b9c:	408b      	lsls	r3, r1
    2b9e:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
}
    2ba2:	b003      	add	sp, #12
    2ba4:	bdf0      	pop	{r4, r5, r6, r7, pc}
	WRITE_BIT(data->pin_int_en, pin, mode != GPIO_INT_MODE_DISABLED);
    2ba6:	2001      	movs	r0, #1
    2ba8:	40b0      	lsls	r0, r6
    2baa:	ea21 0100 	bic.w	r1, r1, r0
    2bae:	e76d      	b.n	2a8c <gpio_nrfx_pin_interrupt_configure+0x40>
	for (size_t i = 0; i < GPIOTE_CH_NUM; i++) {
    2bb0:	3001      	adds	r0, #1
    2bb2:	2808      	cmp	r0, #8
    2bb4:	d188      	bne.n	2ac8 <gpio_nrfx_pin_interrupt_configure+0x7c>
    2bb6:	e7a5      	b.n	2b04 <gpio_nrfx_pin_interrupt_configure+0xb8>
		return -ENODEV;
    2bb8:	f06f 0012 	mvn.w	r0, #18
    2bbc:	e7f1      	b.n	2ba2 <gpio_nrfx_pin_interrupt_configure+0x156>
	if ((BIT(pin) & data->int_active_level) != 0U) {
    2bbe:	6939      	ldr	r1, [r7, #16]
			nrf_gpio_cfg_sense_set(abs_pin, sense);
    2bc0:	4628      	mov	r0, r5
	if ((BIT(pin) & data->int_active_level) != 0U) {
    2bc2:	40f1      	lsrs	r1, r6
    2bc4:	f001 0101 	and.w	r1, r1, #1
    2bc8:	f1c1 0103 	rsb	r1, r1, #3
			nrf_gpio_cfg_sense_set(abs_pin, sense);
    2bcc:	b2c9      	uxtb	r1, r1
    2bce:	f7ff ff15 	bl	29fc <nrf_gpio_cfg_sense_set>
	int res = 0;
    2bd2:	4620      	mov	r0, r4
    2bd4:	e7e5      	b.n	2ba2 <gpio_nrfx_pin_interrupt_configure+0x156>
    2bd6:	bf00      	nop
    2bd8:	50842500 	.word	0x50842500
    2bdc:	5000d000 	.word	0x5000d000
    2be0:	0bad0000 	.word	0x0bad0000

00002be4 <gpio_nrfx_config>:
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    2be4:	4b28      	ldr	r3, [pc, #160]	; (2c88 <gpio_nrfx_config+0xa4>)
{
    2be6:	b570      	push	{r4, r5, r6, lr}
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    2be8:	6846      	ldr	r6, [r0, #4]
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    2bea:	4828      	ldr	r0, [pc, #160]	; (2c8c <gpio_nrfx_config+0xa8>)
    2bec:	4013      	ands	r3, r2
    2bee:	4283      	cmp	r3, r0
    2bf0:	d03b      	beq.n	2c6a <gpio_nrfx_config+0x86>
    2bf2:	d80d      	bhi.n	2c10 <gpio_nrfx_config+0x2c>
    2bf4:	2b06      	cmp	r3, #6
    2bf6:	d015      	beq.n	2c24 <gpio_nrfx_config+0x40>
    2bf8:	d805      	bhi.n	2c06 <gpio_nrfx_config+0x22>
    2bfa:	b19b      	cbz	r3, 2c24 <gpio_nrfx_config+0x40>
    2bfc:	2b02      	cmp	r3, #2
    2bfe:	d036      	beq.n	2c6e <gpio_nrfx_config+0x8a>
    2c00:	f06f 0015 	mvn.w	r0, #21
    2c04:	e030      	b.n	2c68 <gpio_nrfx_config+0x84>
    2c06:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
    2c0a:	d1f9      	bne.n	2c00 <gpio_nrfx_config+0x1c>
		drive = NRF_GPIO_PIN_H0S1;
    2c0c:	2301      	movs	r3, #1
    2c0e:	e009      	b.n	2c24 <gpio_nrfx_config+0x40>
	switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
    2c10:	481f      	ldr	r0, [pc, #124]	; (2c90 <gpio_nrfx_config+0xac>)
    2c12:	4283      	cmp	r3, r0
    2c14:	d02d      	beq.n	2c72 <gpio_nrfx_config+0x8e>
    2c16:	f5b3 0fa0 	cmp.w	r3, #5242880	; 0x500000
    2c1a:	d02c      	beq.n	2c76 <gpio_nrfx_config+0x92>
    2c1c:	f5b3 0f80 	cmp.w	r3, #4194304	; 0x400000
    2c20:	d1ee      	bne.n	2c00 <gpio_nrfx_config+0x1c>
		drive = NRF_GPIO_PIN_S0H1;
    2c22:	2302      	movs	r3, #2
	if ((flags & GPIO_PULL_UP) != 0) {
    2c24:	06d0      	lsls	r0, r2, #27
		pull = NRF_GPIO_PIN_PULLUP;
    2c26:	bf4c      	ite	mi
    2c28:	2503      	movmi	r5, #3
		pull = NRF_GPIO_PIN_NOPULL;
    2c2a:	f3c2 1540 	ubfxpl	r5, r2, #5, #1
		: NRF_GPIO_PIN_INPUT_DISCONNECT;
    2c2e:	f482 7480 	eor.w	r4, r2, #256	; 0x100
	if ((flags & GPIO_OUTPUT) != 0) {
    2c32:	f412 7f00 	tst.w	r2, #512	; 0x200
	dir = ((flags & GPIO_OUTPUT) != 0)
    2c36:	f3c2 2040 	ubfx	r0, r2, #9, #1
		: NRF_GPIO_PIN_INPUT_DISCONNECT;
    2c3a:	f3c4 2400 	ubfx	r4, r4, #8, #1
	if ((flags & GPIO_OUTPUT) != 0) {
    2c3e:	d006      	beq.n	2c4e <gpio_nrfx_config+0x6a>
		if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
    2c40:	f412 6f00 	tst.w	r2, #2048	; 0x800
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    2c44:	6876      	ldr	r6, [r6, #4]
		if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
    2c46:	d018      	beq.n	2c7a <gpio_nrfx_config+0x96>
			nrf_gpio_port_out_set(reg, BIT(pin));
    2c48:	2201      	movs	r2, #1
    2c4a:	408a      	lsls	r2, r1
    p_reg->OUTSET = set_mask;
    2c4c:	60b2      	str	r2, [r6, #8]
                               | ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos)
    2c4e:	ea40 0244 	orr.w	r2, r0, r4, lsl #1
	return 0;
    2c52:	2000      	movs	r0, #0
    2c54:	ea42 2303 	orr.w	r3, r2, r3, lsl #8
    *p_pin = pin_number & 0x1F;
    2c58:	f001 011f 	and.w	r1, r1, #31
    reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)
    2c5c:	4a0d      	ldr	r2, [pc, #52]	; (2c94 <gpio_nrfx_config+0xb0>)
                               | ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos)
    2c5e:	ea43 0385 	orr.w	r3, r3, r5, lsl #2
    reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)
    2c62:	3180      	adds	r1, #128	; 0x80
    2c64:	f842 3021 	str.w	r3, [r2, r1, lsl #2]
}
    2c68:	bd70      	pop	{r4, r5, r6, pc}
		drive = NRF_GPIO_PIN_H0D1;
    2c6a:	2307      	movs	r3, #7
    2c6c:	e7da      	b.n	2c24 <gpio_nrfx_config+0x40>
		drive = NRF_GPIO_PIN_D0S1;
    2c6e:	2304      	movs	r3, #4
    2c70:	e7d8      	b.n	2c24 <gpio_nrfx_config+0x40>
		drive = NRF_GPIO_PIN_D0H1;
    2c72:	2305      	movs	r3, #5
    2c74:	e7d6      	b.n	2c24 <gpio_nrfx_config+0x40>
		drive = NRF_GPIO_PIN_H0H1;
    2c76:	2303      	movs	r3, #3
    2c78:	e7d4      	b.n	2c24 <gpio_nrfx_config+0x40>
		} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
    2c7a:	0552      	lsls	r2, r2, #21
			nrf_gpio_port_out_clear(reg, BIT(pin));
    2c7c:	bf42      	ittt	mi
    2c7e:	2201      	movmi	r2, #1
    2c80:	408a      	lslmi	r2, r1
    p_reg->OUTCLR = clr_mask;
    2c82:	60f2      	strmi	r2, [r6, #12]
}
    2c84:	e7e3      	b.n	2c4e <gpio_nrfx_config+0x6a>
    2c86:	bf00      	nop
    2c88:	00f00006 	.word	0x00f00006
    2c8c:	00100006 	.word	0x00100006
    2c90:	00400002 	.word	0x00400002
    2c94:	50842500 	.word	0x50842500

00002c98 <gpiote_event_handler>:
{
    2c98:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    2c9c:	4f3c      	ldr	r7, [pc, #240]	; (2d90 <gpiote_event_handler+0xf8>)
    2c9e:	683e      	ldr	r6, [r7, #0]
	if (port_event) {
    2ca0:	2e00      	cmp	r6, #0
    2ca2:	d04f      	beq.n	2d44 <gpiote_event_handler+0xac>
	uint32_t bit = 1U << pin;
    2ca4:	f04f 0801 	mov.w	r8, #1
	uint32_t pin = 0U;
    2ca8:	f04f 0900 	mov.w	r9, #0
	uint32_t out = data->pin_int_en;
    2cac:	4b39      	ldr	r3, [pc, #228]	; (2d94 <gpiote_event_handler+0xfc>)
    2cae:	68dd      	ldr	r5, [r3, #12]
	out &= ~data->trig_edge & ~data->double_edge;
    2cb0:	e9d3 2105 	ldrd	r2, r1, [r3, #20]
    2cb4:	430a      	orrs	r2, r1
    2cb6:	ea25 0502 	bic.w	r5, r5, r2
    return p_reg->IN;
    2cba:	4a37      	ldr	r2, [pc, #220]	; (2d98 <gpiote_event_handler+0x100>)
	uint32_t pin_states = ~(port_in ^ data->int_active_level);
    2cbc:	691b      	ldr	r3, [r3, #16]
    2cbe:	6914      	ldr	r4, [r2, #16]
    2cc0:	405c      	eors	r4, r3
	uint32_t out = pin_states & level_pins;
    2cc2:	ea25 0404 	bic.w	r4, r5, r4
	while (level_pins) {
    2cc6:	bb75      	cbnz	r5, 2d26 <gpiote_event_handler+0x8e>
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    2cc8:	603d      	str	r5, [r7, #0]
    2cca:	683b      	ldr	r3, [r7, #0]
	uint32_t fired_triggers[GPIO_COUNT] = {0};
    2ccc:	2300      	movs	r3, #0
		if (nrf_gpiote_int_enable_check(NRF_GPIOTE, BIT(i)) &&
    2cce:	2501      	movs	r5, #1
    2cd0:	461f      	mov	r7, r3
    return p_reg->INTENSET & mask;
    2cd2:	4832      	ldr	r0, [pc, #200]	; (2d9c <gpiote_event_handler+0x104>)
    2cd4:	f8d0 2304 	ldr.w	r2, [r0, #772]	; 0x304
    2cd8:	fa05 f103 	lsl.w	r1, r5, r3
    2cdc:	4211      	tst	r1, r2
    2cde:	d011      	beq.n	2d04 <gpiote_event_handler+0x6c>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    2ce0:	009a      	lsls	r2, r3, #2
    2ce2:	f102 42a0 	add.w	r2, r2, #1342177280	; 0x50000000
    2ce6:	f502 4251 	add.w	r2, r2, #53504	; 0xd100
    2cea:	6811      	ldr	r1, [r2, #0]
    2cec:	b151      	cbz	r1, 2d04 <gpiote_event_handler+0x6c>
    return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
    2cee:	f503 71a2 	add.w	r1, r3, #324	; 0x144
    2cf2:	f850 1021 	ldr.w	r1, [r0, r1, lsl #2]
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    2cf6:	6017      	str	r7, [r2, #0]
    return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
    2cf8:	f3c1 2104 	ubfx	r1, r1, #8, #5
			fired_triggers[abs_pin / 32U] |= BIT(abs_pin % 32);
    2cfc:	fa05 f101 	lsl.w	r1, r5, r1
    2d00:	6812      	ldr	r2, [r2, #0]
    2d02:	430c      	orrs	r4, r1
	for (size_t i = 0; i < GPIOTE_CH_NUM; i++) {
    2d04:	3301      	adds	r3, #1
    2d06:	2b08      	cmp	r3, #8
    2d08:	d1e4      	bne.n	2cd4 <gpiote_event_handler+0x3c>
	if (fired_triggers[0]) {
    2d0a:	b9ec      	cbnz	r4, 2d48 <gpiote_event_handler+0xb0>
	if (port_event) {
    2d0c:	b14e      	cbz	r6, 2d22 <gpiote_event_handler+0x8a>
	uint32_t bit = 1U << pin;
    2d0e:	2601      	movs	r6, #1
	uint32_t pin = 0U;
    2d10:	2700      	movs	r7, #0
	uint32_t out = data->pin_int_en;
    2d12:	4d20      	ldr	r5, [pc, #128]	; (2d94 <gpiote_event_handler+0xfc>)
    2d14:	68ec      	ldr	r4, [r5, #12]
	out &= ~data->trig_edge & ~data->double_edge;
    2d16:	e9d5 2105 	ldrd	r2, r1, [r5, #20]
    2d1a:	430a      	orrs	r2, r1
    2d1c:	ea24 0402 	bic.w	r4, r4, r2
	while (level_pins) {
    2d20:	bb1c      	cbnz	r4, 2d6a <gpiote_event_handler+0xd2>
}
    2d22:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
		if (level_pins & bit) {
    2d26:	ea15 0f08 	tst.w	r5, r8
    2d2a:	d006      	beq.n	2d3a <gpiote_event_handler+0xa2>
			nrf_gpio_cfg_sense_set(abs_pin, NRF_GPIO_PIN_NOSENSE);
    2d2c:	2100      	movs	r1, #0
    2d2e:	f009 001f 	and.w	r0, r9, #31
    2d32:	f7ff fe63 	bl	29fc <nrf_gpio_cfg_sense_set>
			level_pins &= ~bit;
    2d36:	ea25 0508 	bic.w	r5, r5, r8
		++pin;
    2d3a:	f109 0901 	add.w	r9, r9, #1
		bit <<= 1;
    2d3e:	ea4f 0848 	mov.w	r8, r8, lsl #1
    2d42:	e7c0      	b.n	2cc6 <gpiote_event_handler+0x2e>
	uint32_t fired_triggers[GPIO_COUNT] = {0};
    2d44:	4634      	mov	r4, r6
    2d46:	e7c1      	b.n	2ccc <gpiote_event_handler+0x34>
					const struct device *port,
					uint32_t pins)
{
	struct gpio_callback *cb, *tmp;

	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    2d48:	4b12      	ldr	r3, [pc, #72]	; (2d94 <gpiote_event_handler+0xfc>)
    2d4a:	6859      	ldr	r1, [r3, #4]
    2d4c:	2900      	cmp	r1, #0
    2d4e:	d0dd      	beq.n	2d0c <gpiote_event_handler+0x74>
Z_GENLIST_PEEK_NEXT_NO_CHECK(slist, snode)
    2d50:	680d      	ldr	r5, [r1, #0]
		if (cb->pin_mask & pins) {
			__ASSERT(cb->handler, "No callback handler!");
			cb->handler(port, cb, cb->pin_mask & pins);
    2d52:	4f13      	ldr	r7, [pc, #76]	; (2da0 <gpiote_event_handler+0x108>)
		if (cb->pin_mask & pins) {
    2d54:	688a      	ldr	r2, [r1, #8]
    2d56:	4022      	ands	r2, r4
    2d58:	d002      	beq.n	2d60 <gpiote_event_handler+0xc8>
			cb->handler(port, cb, cb->pin_mask & pins);
    2d5a:	4638      	mov	r0, r7
    2d5c:	684b      	ldr	r3, [r1, #4]
    2d5e:	4798      	blx	r3
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    2d60:	2d00      	cmp	r5, #0
    2d62:	d0d3      	beq.n	2d0c <gpiote_event_handler+0x74>
    2d64:	4629      	mov	r1, r5
    2d66:	682d      	ldr	r5, [r5, #0]
    2d68:	e7f4      	b.n	2d54 <gpiote_event_handler+0xbc>
		if (level_pins & bit) {
    2d6a:	4226      	tst	r6, r4
    2d6c:	d00c      	beq.n	2d88 <gpiote_event_handler+0xf0>
	if ((BIT(pin) & data->int_active_level) != 0U) {
    2d6e:	6929      	ldr	r1, [r5, #16]
			nrf_gpio_cfg_sense_set(abs_pin, sense);
    2d70:	f007 001f 	and.w	r0, r7, #31
	if ((BIT(pin) & data->int_active_level) != 0U) {
    2d74:	40f9      	lsrs	r1, r7
    2d76:	f001 0101 	and.w	r1, r1, #1
    2d7a:	f1c1 0103 	rsb	r1, r1, #3
			nrf_gpio_cfg_sense_set(abs_pin, sense);
    2d7e:	b2c9      	uxtb	r1, r1
    2d80:	f7ff fe3c 	bl	29fc <nrf_gpio_cfg_sense_set>
			level_pins &= ~bit;
    2d84:	ea24 0406 	bic.w	r4, r4, r6
		++pin;
    2d88:	3701      	adds	r7, #1
		bit <<= 1;
    2d8a:	0076      	lsls	r6, r6, #1
    2d8c:	e7c8      	b.n	2d20 <gpiote_event_handler+0x88>
    2d8e:	bf00      	nop
    2d90:	5000d17c 	.word	0x5000d17c
    2d94:	200007d8 	.word	0x200007d8
    2d98:	50842500 	.word	0x50842500
    2d9c:	5000d000 	.word	0x5000d000
    2da0:	200000b0 	.word	0x200000b0

00002da4 <check_ext_api_requests>:
	}
};
#endif

static int check_ext_api_requests(const struct device *dev)
{
    2da4:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
	(void)dev;

	const struct fw_info_ext_api_request *ext_api_req =
			skip_ext_apis(&m_firmware_info);

	for (uint32_t i = 0; i < m_firmware_info.ext_api_request_num; i++) {
    2da8:	2500      	movs	r5, #0
			skip_ext_apis(&m_firmware_info);
    2daa:	4c21      	ldr	r4, [pc, #132]	; (2e30 <check_ext_api_requests+0x8c>)
 */
static inline const struct fw_info_ext_api *fw_info_ext_api_check(
							uint32_t ext_api_addr)
{
	const struct fw_info_ext_api *ext_api;
	const uint32_t ext_api_magic[] = {EXT_API_MAGIC};
    2dac:	4e21      	ldr	r6, [pc, #132]	; (2e34 <check_ext_api_requests+0x90>)
	for (uint32_t i = 0; i < m_firmware_info.ext_api_request_num; i++) {
    2dae:	f854 8c04 	ldr.w	r8, [r4, #-4]
			/* EXT_API hard requirement not met. */
			printk("ERROR: Cannot fulfill EXT_API request.\r\n");
			k_panic();
		} else {
			/* EXT_API soft requirement not met. */
			printk("WARNING: Optional EXT_API request not "
    2db2:	f8df 9088 	ldr.w	r9, [pc, #136]	; 2e3c <check_ext_api_requests+0x98>
{
    2db6:	b085      	sub	sp, #20
	for (uint32_t i = 0; i < m_firmware_info.ext_api_request_num; i++) {
    2db8:	45a8      	cmp	r8, r5
    2dba:	d803      	bhi.n	2dc4 <check_ext_api_requests+0x20>
		}
		ADVANCE_EXT_API_REQ(ext_api_req);
	}

	return 0;
}
    2dbc:	2000      	movs	r0, #0
    2dbe:	b005      	add	sp, #20
    2dc0:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
		if (fw_info_ext_api_check((uint32_t)*(ext_api_req->ext_api))
    2dc4:	6a63      	ldr	r3, [r4, #36]	; 0x24
    2dc6:	e896 0007 	ldmia.w	r6, {r0, r1, r2}
    2dca:	681f      	ldr	r7, [r3, #0]
    2dcc:	ab01      	add	r3, sp, #4
    2dce:	e883 0007 	stmia.w	r3, {r0, r1, r2}

	ext_api = (const struct fw_info_ext_api *)(ext_api_addr);
	if (memcmp(ext_api->magic, ext_api_magic, CONFIG_FW_INFO_MAGIC_LEN)
    2dd2:	220c      	movs	r2, #12
    2dd4:	4619      	mov	r1, r3
    2dd6:	4638      	mov	r0, r7
    2dd8:	f002 fd57 	bl	588a <memcmp>
    2ddc:	b990      	cbnz	r0, 2e04 <check_ext_api_requests+0x60>
    2dde:	b18f      	cbz	r7, 2e04 <check_ext_api_requests+0x60>
			&& ext_api_satisfies_req(*(ext_api_req->ext_api),
    2de0:	6a63      	ldr	r3, [r4, #36]	; 0x24
	const uint32_t req_id = ext_api_req->request.ext_api_id;
    2de2:	6921      	ldr	r1, [r4, #16]
			&& ext_api_satisfies_req(*(ext_api_req->ext_api),
    2de4:	681b      	ldr	r3, [r3, #0]
	return ((ext_api->ext_api_id == req_id)
    2de6:	691a      	ldr	r2, [r3, #16]
		&& ((ext_api->ext_api_flags & req_flags) == req_flags));
    2de8:	4291      	cmp	r1, r2
    2dea:	d10b      	bne.n	2e04 <check_ext_api_requests+0x60>
		&&  (ext_api->ext_api_version >= req_min_version)
    2dec:	699a      	ldr	r2, [r3, #24]
	const uint32_t req_min_version = ext_api_req->request.ext_api_version;
    2dee:	69a1      	ldr	r1, [r4, #24]
		&&  (ext_api->ext_api_version >= req_min_version)
    2df0:	4291      	cmp	r1, r2
    2df2:	d807      	bhi.n	2e04 <check_ext_api_requests+0x60>
	const uint32_t req_max_version = ext_api_req->ext_api_max_version;
    2df4:	69e1      	ldr	r1, [r4, #28]
		&&  (ext_api->ext_api_version <  req_max_version)
    2df6:	4291      	cmp	r1, r2
    2df8:	d904      	bls.n	2e04 <check_ext_api_requests+0x60>
	const uint32_t req_flags = ext_api_req->request.ext_api_flags;
    2dfa:	6962      	ldr	r2, [r4, #20]
		&& ((ext_api->ext_api_flags & req_flags) == req_flags));
    2dfc:	695b      	ldr	r3, [r3, #20]
    2dfe:	ea32 0303 	bics.w	r3, r2, r3
    2e02:	d00a      	beq.n	2e1a <check_ext_api_requests+0x76>
		} else if (ext_api_req->required) {
    2e04:	6a27      	ldr	r7, [r4, #32]
    2e06:	b167      	cbz	r7, 2e22 <check_ext_api_requests+0x7e>
			printk("ERROR: Cannot fulfill EXT_API request.\r\n");
    2e08:	480b      	ldr	r0, [pc, #44]	; (2e38 <check_ext_api_requests+0x94>)
    2e0a:	f002 f991 	bl	5130 <printk>
			k_panic();
    2e0e:	4040      	eors	r0, r0
    2e10:	f380 8811 	msr	BASEPRI, r0
    2e14:	f04f 0004 	mov.w	r0, #4
    2e18:	df02      	svc	2
		ADVANCE_EXT_API_REQ(ext_api_req);
    2e1a:	68e3      	ldr	r3, [r4, #12]
	for (uint32_t i = 0; i < m_firmware_info.ext_api_request_num; i++) {
    2e1c:	3501      	adds	r5, #1
		ADVANCE_EXT_API_REQ(ext_api_req);
    2e1e:	441c      	add	r4, r3
	for (uint32_t i = 0; i < m_firmware_info.ext_api_request_num; i++) {
    2e20:	e7ca      	b.n	2db8 <check_ext_api_requests+0x14>
			printk("WARNING: Optional EXT_API request not "
    2e22:	4648      	mov	r0, r9
    2e24:	f002 f984 	bl	5130 <printk>
			*ext_api_req->ext_api = NULL;
    2e28:	6a63      	ldr	r3, [r4, #36]	; 0x24
    2e2a:	601f      	str	r7, [r3, #0]
    2e2c:	e7f5      	b.n	2e1a <check_ext_api_requests+0x76>
    2e2e:	bf00      	nop
    2e30:	0000023c 	.word	0x0000023c
    2e34:	00005f2c 	.word	0x00005f2c
    2e38:	00006552 	.word	0x00006552
    2e3c:	0000657b 	.word	0x0000657b

00002e40 <nrf91_errata_14>:
    #ifndef NRF91_SERIES
        return false;
    #else
        #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160)
            uint32_t var1 = *(uint32_t *)0x00FF0130ul;
            uint32_t var2 = *(uint32_t *)0x00FF0134ul;
    2e40:	4b05      	ldr	r3, [pc, #20]	; (2e58 <nrf91_errata_14+0x18>)
    2e42:	6818      	ldr	r0, [r3, #0]
            uint32_t var1 = *(uint32_t *)0x00FF0130ul;
    2e44:	3b04      	subs	r3, #4
        #endif
        #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160)
            if (var1 == 0x09)
    2e46:	681b      	ldr	r3, [r3, #0]
    2e48:	2b09      	cmp	r3, #9
    2e4a:	d103      	bne.n	2e54 <nrf91_errata_14+0x14>
            {
                switch(var2)
    2e4c:	1e43      	subs	r3, r0, #1
    2e4e:	4258      	negs	r0, r3
    2e50:	4158      	adcs	r0, r3
    2e52:	4770      	bx	lr
                    default:
                        return false;
                }
            }
        #endif
        return false;
    2e54:	2000      	movs	r0, #0
    #endif
}
    2e56:	4770      	bx	lr
    2e58:	00ff0134 	.word	0x00ff0134

00002e5c <SystemInit>:
        /* Perform Secure-mode initialization routines. */

        /* Set all ARM SAU regions to NonSecure if TrustZone extensions are enabled.
        * Nordic SPU should handle Secure Attribution tasks */
        #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
          SAU->CTRL |= (1 << SAU_CTRL_ALLNS_Pos);
    2e5c:	4a4f      	ldr	r2, [pc, #316]	; (2f9c <SystemInit+0x140>)
{
    2e5e:	b508      	push	{r3, lr}
          SAU->CTRL |= (1 << SAU_CTRL_ALLNS_Pos);
    2e60:	6813      	ldr	r3, [r2, #0]
    2e62:	f043 0302 	orr.w	r3, r3, #2
    2e66:	6013      	str	r3, [r2, #0]
            uint32_t var1 = *(uint32_t *)0x00FF0130ul;
    2e68:	4b4d      	ldr	r3, [pc, #308]	; (2fa0 <SystemInit+0x144>)
            if (var1 == 0x09)
    2e6a:	681b      	ldr	r3, [r3, #0]
    2e6c:	2b09      	cmp	r3, #9
        #endif
        
        /* Workaround for Errata 6 "POWER: SLEEPENTER and SLEEPEXIT events asserted after pin reset" found at the Errata document
            for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf91_errata_6()){
            NRF_POWER_S->EVENTS_SLEEPENTER = (POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos);
    2e6e:	bf01      	itttt	eq
    2e70:	f04f 2350 	moveq.w	r3, #1342197760	; 0x50005000
    2e74:	2200      	moveq	r2, #0
    2e76:	f8c3 2114 	streq.w	r2, [r3, #276]	; 0x114
            NRF_POWER_S->EVENTS_SLEEPEXIT = (POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos);
    2e7a:	f8c3 2118 	streq.w	r2, [r3, #280]	; 0x118
        }

        /* Workaround for Errata 14 "REGULATORS: LDO mode at startup" found at the Errata document
            for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf91_errata_14()){
    2e7e:	f7ff ffdf 	bl	2e40 <nrf91_errata_14>
    2e82:	b130      	cbz	r0, 2e92 <SystemInit+0x36>
            *((volatile uint32_t *)0x50004A38) = 0x01ul;
    2e84:	2301      	movs	r3, #1
    2e86:	4a47      	ldr	r2, [pc, #284]	; (2fa4 <SystemInit+0x148>)
    2e88:	6013      	str	r3, [r2, #0]
            NRF_REGULATORS_S->DCDCEN = REGULATORS_DCDCEN_DCDCEN_Enabled << REGULATORS_DCDCEN_DCDCEN_Pos;
    2e8a:	f6a2 2238 	subw	r2, r2, #2616	; 0xa38
    2e8e:	f8c2 3578 	str.w	r3, [r2, #1400]	; 0x578
{
    #ifndef NRF91_SERIES
        return false;
    #else
        #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160)
            uint32_t var1 = *(uint32_t *)0x00FF0130ul;
    2e92:	4b43      	ldr	r3, [pc, #268]	; (2fa0 <SystemInit+0x144>)
            uint32_t var2 = *(uint32_t *)0x00FF0134ul;
        #endif
        #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160)
            if (var1 == 0x09)
    2e94:	681b      	ldr	r3, [r3, #0]
    2e96:	2b09      	cmp	r3, #9
    2e98:	d107      	bne.n	2eaa <SystemInit+0x4e>
            uint32_t var2 = *(uint32_t *)0x00FF0134ul;
    2e9a:	4b43      	ldr	r3, [pc, #268]	; (2fa8 <SystemInit+0x14c>)
            {
                switch(var2)
    2e9c:	681b      	ldr	r3, [r3, #0]
    2e9e:	2b01      	cmp	r3, #1
        }

        /* Workaround for Errata 15 "REGULATORS: LDO mode at startup" found at the Errata document
            for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf91_errata_15()){
            NRF_REGULATORS_S->DCDCEN = REGULATORS_DCDCEN_DCDCEN_Enabled << REGULATORS_DCDCEN_DCDCEN_Pos;
    2ea0:	bf1e      	ittt	ne
    2ea2:	2201      	movne	r2, #1
    2ea4:	4b41      	ldrne	r3, [pc, #260]	; (2fac <SystemInit+0x150>)
    2ea6:	f8c3 2578 	strne.w	r2, [r3, #1400]	; 0x578
        }

        /* Workaround for Errata 20 "RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
            for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf91_errata_20()){
    2eaa:	f7ff ffc9 	bl	2e40 <nrf91_errata_14>
    2eae:	b110      	cbz	r0, 2eb6 <SystemInit+0x5a>
            *((volatile uint32_t *)0x5003AEE4) = 0xE;
    2eb0:	220e      	movs	r2, #14
    2eb2:	4b3f      	ldr	r3, [pc, #252]	; (2fb0 <SystemInit+0x154>)
    2eb4:	601a      	str	r2, [r3, #0]
            uint32_t var1 = *(uint32_t *)0x00FF0130ul;
    2eb6:	4b3a      	ldr	r3, [pc, #232]	; (2fa0 <SystemInit+0x144>)
            if (var1 == 0x09)
    2eb8:	681b      	ldr	r3, [r3, #0]
    2eba:	2b09      	cmp	r3, #9
    2ebc:	d104      	bne.n	2ec8 <SystemInit+0x6c>
        }

        /* Workaround for Errata 31 "XOSC32k Startup Failure" found at the Errata document
            for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf91_errata_31()){
            *((volatile uint32_t *)0x5000470Cul) = 0x0;
    2ebe:	2200      	movs	r2, #0
    2ec0:	4b3c      	ldr	r3, [pc, #240]	; (2fb4 <SystemInit+0x158>)
    2ec2:	601a      	str	r2, [r3, #0]
            *((volatile uint32_t *)0x50004710ul) = 0x1;
    2ec4:	2201      	movs	r2, #1
    2ec6:	605a      	str	r2, [r3, #4]
{
    2ec8:	2200      	movs	r2, #0
    2eca:	00d3      	lsls	r3, r2, #3
    2ecc:	f503 037f 	add.w	r3, r3, #16711680	; 0xff0000
        }

        /* Trimming of the device. Copy all the trimming values from FICR into the target addresses. Trim
         until one ADDR is not initialized. */
        uint32_t index = 0;
        for (index = 0; index < 256ul && NRF_FICR_S->TRIMCNF[index].ADDR != 0xFFFFFFFFul; index++){
    2ed0:	f8d3 1300 	ldr.w	r1, [r3, #768]	; 0x300
    2ed4:	3101      	adds	r1, #1
    2ed6:	d008      	beq.n	2eea <SystemInit+0x8e>
          #if defined ( __ICCARM__ )
              #pragma diag_suppress=Pa082
          #endif
          *(volatile uint32_t *)NRF_FICR_S->TRIMCNF[index].ADDR = NRF_FICR_S->TRIMCNF[index].DATA;
    2ed8:	f8d3 1300 	ldr.w	r1, [r3, #768]	; 0x300
        for (index = 0; index < 256ul && NRF_FICR_S->TRIMCNF[index].ADDR != 0xFFFFFFFFul; index++){
    2edc:	3201      	adds	r2, #1
          *(volatile uint32_t *)NRF_FICR_S->TRIMCNF[index].ADDR = NRF_FICR_S->TRIMCNF[index].DATA;
    2ede:	f8d3 3304 	ldr.w	r3, [r3, #772]	; 0x304
        for (index = 0; index < 256ul && NRF_FICR_S->TRIMCNF[index].ADDR != 0xFFFFFFFFul; index++){
    2ee2:	f5b2 7f80 	cmp.w	r2, #256	; 0x100
          *(volatile uint32_t *)NRF_FICR_S->TRIMCNF[index].ADDR = NRF_FICR_S->TRIMCNF[index].DATA;
    2ee6:	600b      	str	r3, [r1, #0]
        for (index = 0; index < 256ul && NRF_FICR_S->TRIMCNF[index].ADDR != 0xFFFFFFFFul; index++){
    2ee8:	d1ef      	bne.n	2eca <SystemInit+0x6e>
    }
    
    
    bool uicr_HFXOSRC_erased()
    {
        if ((NRF_UICR_S->HFXOSRC & UICR_HFXOSRC_HFXOSRC_Msk) != UICR_HFXOSRC_HFXOSRC_TCXO) {
    2eea:	4b33      	ldr	r3, [pc, #204]	; (2fb8 <SystemInit+0x15c>)
    2eec:	69da      	ldr	r2, [r3, #28]
        if (uicr_HFXOSRC_erased() || uicr_HFXOCNT_erased()) {
    2eee:	07d1      	lsls	r1, r2, #31
    2ef0:	d53b      	bpl.n	2f6a <SystemInit+0x10e>
          while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
    2ef2:	4b32      	ldr	r3, [pc, #200]	; (2fbc <SystemInit+0x160>)
    2ef4:	4619      	mov	r1, r3
    2ef6:	f8d3 2400 	ldr.w	r2, [r3, #1024]	; 0x400
    2efa:	2a01      	cmp	r2, #1
    2efc:	d1fb      	bne.n	2ef6 <SystemInit+0x9a>
          NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Wen;
    2efe:	f8c3 2504 	str.w	r2, [r3, #1284]	; 0x504
          while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
    2f02:	f8d1 3400 	ldr.w	r3, [r1, #1024]	; 0x400
    2f06:	2b01      	cmp	r3, #1
    2f08:	d1fb      	bne.n	2f02 <SystemInit+0xa6>
        if ((NRF_UICR_S->HFXOSRC & UICR_HFXOSRC_HFXOSRC_Msk) != UICR_HFXOSRC_HFXOSRC_TCXO) {
    2f0a:	4b2b      	ldr	r3, [pc, #172]	; (2fb8 <SystemInit+0x15c>)
    2f0c:	69da      	ldr	r2, [r3, #28]
          if (uicr_HFXOSRC_erased()){
    2f0e:	07d2      	lsls	r2, r2, #31
    2f10:	d508      	bpl.n	2f24 <SystemInit+0xc8>
            uicr_erased_value = NRF_UICR_S->HFXOSRC;
    2f12:	69da      	ldr	r2, [r3, #28]
            while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
    2f14:	4929      	ldr	r1, [pc, #164]	; (2fbc <SystemInit+0x160>)
            uicr_new_value = (uicr_erased_value & ~UICR_HFXOSRC_HFXOSRC_Msk) | UICR_HFXOSRC_HFXOSRC_TCXO;
    2f16:	f022 0201 	bic.w	r2, r2, #1
            NRF_UICR_S->HFXOSRC = uicr_new_value;
    2f1a:	61da      	str	r2, [r3, #28]
            while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
    2f1c:	f8d1 2400 	ldr.w	r2, [r1, #1024]	; 0x400
    2f20:	2a01      	cmp	r2, #1
    2f22:	d1fb      	bne.n	2f1c <SystemInit+0xc0>
        if (NRF_UICR_S->HFXOCNT == 0xFFFFFFFFul) {
    2f24:	6a1a      	ldr	r2, [r3, #32]
    2f26:	3201      	adds	r2, #1
    2f28:	d10a      	bne.n	2f40 <SystemInit+0xe4>
            uicr_erased_value = NRF_UICR_S->HFXOCNT;
    2f2a:	6a1a      	ldr	r2, [r3, #32]
            uicr_new_value = (uicr_erased_value & ~UICR_HFXOCNT_HFXOCNT_Msk) | 0x20;
    2f2c:	f022 02ff 	bic.w	r2, r2, #255	; 0xff
    2f30:	f042 0220 	orr.w	r2, r2, #32
            NRF_UICR_S->HFXOCNT = uicr_new_value;
    2f34:	621a      	str	r2, [r3, #32]
            while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
    2f36:	4a21      	ldr	r2, [pc, #132]	; (2fbc <SystemInit+0x160>)
    2f38:	f8d2 3400 	ldr.w	r3, [r2, #1024]	; 0x400
    2f3c:	2b01      	cmp	r3, #1
    2f3e:	d1fb      	bne.n	2f38 <SystemInit+0xdc>
          NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Ren;
    2f40:	2200      	movs	r2, #0
    2f42:	4b1e      	ldr	r3, [pc, #120]	; (2fbc <SystemInit+0x160>)
    2f44:	f8c3 2504 	str.w	r2, [r3, #1284]	; 0x504
          while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready);
    2f48:	f8d3 2400 	ldr.w	r2, [r3, #1024]	; 0x400
    2f4c:	2a01      	cmp	r2, #1
    2f4e:	d1fb      	bne.n	2f48 <SystemInit+0xec>
  __ASM volatile ("dsb 0xF":::"memory");
    2f50:	f3bf 8f4f 	dsb	sy
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    2f54:	491a      	ldr	r1, [pc, #104]	; (2fc0 <SystemInit+0x164>)
    2f56:	4b1b      	ldr	r3, [pc, #108]	; (2fc4 <SystemInit+0x168>)
    2f58:	68ca      	ldr	r2, [r1, #12]
    2f5a:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    2f5e:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    2f60:	60cb      	str	r3, [r1, #12]
    2f62:	f3bf 8f4f 	dsb	sy
    __NOP();
    2f66:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    2f68:	e7fd      	b.n	2f66 <SystemInit+0x10a>
        if (NRF_UICR_S->HFXOCNT == 0xFFFFFFFFul) {
    2f6a:	6a1b      	ldr	r3, [r3, #32]
    2f6c:	3301      	adds	r3, #1
    2f6e:	d0c0      	beq.n	2ef2 <SystemInit+0x96>
        SCB->NSACR |= (3UL << 10);
    2f70:	4b13      	ldr	r3, [pc, #76]	; (2fc0 <SystemInit+0x164>)
    2f72:	f8d3 208c 	ldr.w	r2, [r3, #140]	; 0x8c
    2f76:	f442 6240 	orr.w	r2, r2, #3072	; 0xc00
    2f7a:	f8c3 208c 	str.w	r2, [r3, #140]	; 0x8c
      SCB->CPACR |= (3UL << 20) | (3UL << 22);
    2f7e:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
    2f82:	f442 0270 	orr.w	r2, r2, #15728640	; 0xf00000
    2f86:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
    2f8a:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    2f8e:	f3bf 8f6f 	isb	sy
    SystemCoreClock = __SYSTEM_CLOCK;
    2f92:	4b0d      	ldr	r3, [pc, #52]	; (2fc8 <SystemInit+0x16c>)
    2f94:	4a0d      	ldr	r2, [pc, #52]	; (2fcc <SystemInit+0x170>)
    2f96:	601a      	str	r2, [r3, #0]
}
    2f98:	bd08      	pop	{r3, pc}
    2f9a:	bf00      	nop
    2f9c:	e000edd0 	.word	0xe000edd0
    2fa0:	00ff0130 	.word	0x00ff0130
    2fa4:	50004a38 	.word	0x50004a38
    2fa8:	00ff0134 	.word	0x00ff0134
    2fac:	50004000 	.word	0x50004000
    2fb0:	5003aee4 	.word	0x5003aee4
    2fb4:	5000470c 	.word	0x5000470c
    2fb8:	00ff8000 	.word	0x00ff8000
    2fbc:	50039000 	.word	0x50039000
    2fc0:	e000ed00 	.word	0xe000ed00
    2fc4:	05fa0004 	.word	0x05fa0004
    2fc8:	20000024 	.word	0x20000024
    2fcc:	03d09000 	.word	0x03d09000

00002fd0 <nrfx_clock_init>:
nrfx_err_t nrfx_clock_init(nrfx_clock_event_handler_t event_handler)
{
    NRFX_ASSERT(event_handler);

    nrfx_err_t err_code = NRFX_SUCCESS;
    if (m_clock_cb.module_initialized)
    2fd0:	4b04      	ldr	r3, [pc, #16]	; (2fe4 <nrfx_clock_init+0x14>)
    2fd2:	791a      	ldrb	r2, [r3, #4]
    2fd4:	b922      	cbnz	r2, 2fe0 <nrfx_clock_init+0x10>
    {
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
        m_clock_cb.cal_state = CAL_STATE_IDLE;
#endif
        m_clock_cb.event_handler = event_handler;
        m_clock_cb.module_initialized = true;
    2fd6:	2201      	movs	r2, #1
        m_clock_cb.event_handler = event_handler;
    2fd8:	6018      	str	r0, [r3, #0]
        m_clock_cb.module_initialized = true;
    2fda:	711a      	strb	r2, [r3, #4]
    nrfx_err_t err_code = NRFX_SUCCESS;
    2fdc:	4802      	ldr	r0, [pc, #8]	; (2fe8 <nrfx_clock_init+0x18>)
    2fde:	4770      	bx	lr
        err_code = NRFX_ERROR_ALREADY_INITIALIZED;
    2fe0:	4802      	ldr	r0, [pc, #8]	; (2fec <nrfx_clock_init+0x1c>)
#endif
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    2fe2:	4770      	bx	lr
    2fe4:	200007f4 	.word	0x200007f4
    2fe8:	0bad0000 	.word	0x0bad0000
    2fec:	0bad000c 	.word	0x0bad000c

00002ff0 <nrfx_clock_start>:
}

void nrfx_clock_start(nrf_clock_domain_t domain)
{
    NRFX_ASSERT(m_clock_cb.module_initialized);
    switch (domain)
    2ff0:	b110      	cbz	r0, 2ff8 <nrfx_clock_start+0x8>
    2ff2:	2801      	cmp	r0, #1
    2ff4:	d020      	beq.n	3038 <nrfx_clock_start+0x48>
    2ff6:	4770      	bx	lr
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    2ff8:	f04f 2250 	mov.w	r2, #1342197760	; 0x50005000
    2ffc:	f8d2 3418 	ldr.w	r3, [r2, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    3000:	f8d2 1418 	ldr.w	r1, [r2, #1048]	; 0x418
    3004:	03c9      	lsls	r1, r1, #15
    3006:	d511      	bpl.n	302c <nrfx_clock_start+0x3c>
    {
        case NRF_CLOCK_DOMAIN_LFCLK:
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED)
            {
                nrf_clock_lfclk_t lfclksrc;
                if (nrf_clock_is_running(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK, &lfclksrc) &&
    3008:	f003 0303 	and.w	r3, r3, #3
    300c:	2b02      	cmp	r3, #2
    300e:	d10d      	bne.n	302c <nrfx_clock_start+0x3c>
    p_reg->LFCLKSRC = (uint32_t)(source);
    3010:	f8c2 3518 	str.w	r3, [r2, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3014:	2200      	movs	r2, #0
    3016:	4b0d      	ldr	r3, [pc, #52]	; (304c <nrfx_clock_start+0x5c>)
    3018:	601a      	str	r2, [r3, #0]
    301a:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENSET = mask;
    301c:	2202      	movs	r2, #2
    301e:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    3022:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    3026:	2201      	movs	r2, #1
    3028:	609a      	str	r2, [r3, #8]
}
    302a:	4770      	bx	lr
    p_reg->LFCLKSRC = (uint32_t)(source);
    302c:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    3030:	2201      	movs	r2, #1
    3032:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
}
    3036:	e7ed      	b.n	3014 <nrfx_clock_start+0x24>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3038:	2200      	movs	r2, #0
    303a:	4b05      	ldr	r3, [pc, #20]	; (3050 <nrfx_clock_start+0x60>)
    303c:	601a      	str	r2, [r3, #0]
    303e:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENSET = mask;
    3040:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    3044:	f8c3 0304 	str.w	r0, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    3048:	6018      	str	r0, [r3, #0]
#endif
        default:
            NRFX_ASSERT(0);
            break;
    }
}
    304a:	4770      	bx	lr
    304c:	50005104 	.word	0x50005104
    3050:	50005100 	.word	0x50005100

00003054 <nrfx_clock_stop>:

void nrfx_clock_stop(nrf_clock_domain_t domain)
{
    3054:	b538      	push	{r3, r4, r5, lr}
    NRFX_ASSERT(m_clock_cb.module_initialized);
    switch (domain)
    3056:	b110      	cbz	r0, 305e <nrfx_clock_stop+0xa>
    3058:	2801      	cmp	r0, #1
    305a:	d018      	beq.n	308e <nrfx_clock_stop+0x3a>
    if (domain == NRF_CLOCK_DOMAIN_HFCLK)
    {
            m_clock_cb.hfclk_started = false;
    }
#endif
}
    305c:	bd38      	pop	{r3, r4, r5, pc}
    p_reg->INTENCLR = mask;
    305e:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    3062:	2202      	movs	r2, #2
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    3064:	2101      	movs	r1, #1
    3066:	f242 7510 	movw	r5, #10000	; 0x2710
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    306a:	461c      	mov	r4, r3
    p_reg->INTENCLR = mask;
    306c:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3070:	4a15      	ldr	r2, [pc, #84]	; (30c8 <nrfx_clock_stop+0x74>)
    3072:	6010      	str	r0, [r2, #0]
    3074:	6812      	ldr	r2, [r2, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    3076:	4a15      	ldr	r2, [pc, #84]	; (30cc <nrfx_clock_stop+0x78>)
    3078:	6011      	str	r1, [r2, #0]
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    307a:	f8d4 3418 	ldr.w	r3, [r4, #1048]	; 0x418
    307e:	03db      	lsls	r3, r3, #15
    3080:	d5ec      	bpl.n	305c <nrfx_clock_stop+0x8>
        NRFX_WAIT_FOR(!nrfx_clock_is_running(domain, NULL), 10000, 1, stopped);
    3082:	2001      	movs	r0, #1
    3084:	f002 fccf 	bl	5a26 <nrfx_busy_wait>
    3088:	3d01      	subs	r5, #1
    308a:	d1f6      	bne.n	307a <nrfx_clock_stop+0x26>
    308c:	e7e6      	b.n	305c <nrfx_clock_stop+0x8>
    p_reg->INTENCLR = mask;
    308e:	f04f 2450 	mov.w	r4, #1342197760	; 0x50005000
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3092:	2200      	movs	r2, #0
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    3094:	f242 7510 	movw	r5, #10000	; 0x2710
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3098:	4b0d      	ldr	r3, [pc, #52]	; (30d0 <nrfx_clock_stop+0x7c>)
    p_reg->INTENCLR = mask;
    309a:	f8c4 0308 	str.w	r0, [r4, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    309e:	601a      	str	r2, [r3, #0]
    30a0:	681b      	ldr	r3, [r3, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    30a2:	4b0c      	ldr	r3, [pc, #48]	; (30d4 <nrfx_clock_stop+0x80>)
    30a4:	6018      	str	r0, [r3, #0]
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    30a6:	f8d4 340c 	ldr.w	r3, [r4, #1036]	; 0x40c
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    30aa:	f8d4 240c 	ldr.w	r2, [r4, #1036]	; 0x40c
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    30ae:	f003 0301 	and.w	r3, r3, #1
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    30b2:	03d2      	lsls	r2, r2, #15
    30b4:	d5d2      	bpl.n	305c <nrfx_clock_stop+0x8>
        NRFX_WAIT_FOR((!nrfx_clock_is_running(domain, &clk_src) ||
    30b6:	2b00      	cmp	r3, #0
    30b8:	d0d0      	beq.n	305c <nrfx_clock_stop+0x8>
    30ba:	2001      	movs	r0, #1
    30bc:	f002 fcb3 	bl	5a26 <nrfx_busy_wait>
    30c0:	3d01      	subs	r5, #1
    30c2:	d1f0      	bne.n	30a6 <nrfx_clock_stop+0x52>
    30c4:	e7ca      	b.n	305c <nrfx_clock_stop+0x8>
    30c6:	bf00      	nop
    30c8:	50005104 	.word	0x50005104
    30cc:	5000500c 	.word	0x5000500c
    30d0:	50005100 	.word	0x50005100
    30d4:	50005004 	.word	0x50005004

000030d8 <nrfx_power_clock_irq_handler>:
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    30d8:	4b16      	ldr	r3, [pc, #88]	; (3134 <nrfx_power_clock_irq_handler+0x5c>)
    }
}
#endif

void nrfx_clock_irq_handler(void)
{
    30da:	b510      	push	{r4, lr}
    30dc:	681a      	ldr	r2, [r3, #0]
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED))
    30de:	b152      	cbz	r2, 30f6 <nrfx_power_clock_irq_handler+0x1e>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    30e0:	2000      	movs	r0, #0
    30e2:	6018      	str	r0, [r3, #0]
    30e4:	681b      	ldr	r3, [r3, #0]
    p_reg->INTENCLR = mask;
    30e6:	2201      	movs	r2, #1
    30e8:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    30ec:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
        {
            m_clock_cb.hfclk_started = true;
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
        }
#else
        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
    30f0:	4b11      	ldr	r3, [pc, #68]	; (3138 <nrfx_power_clock_irq_handler+0x60>)
    30f2:	681b      	ldr	r3, [r3, #0]
    30f4:	4798      	blx	r3
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    30f6:	4b11      	ldr	r3, [pc, #68]	; (313c <nrfx_power_clock_irq_handler+0x64>)
    30f8:	681a      	ldr	r2, [r3, #0]
#endif
    }
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED))
    30fa:	b18a      	cbz	r2, 3120 <nrfx_power_clock_irq_handler+0x48>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    30fc:	2200      	movs	r2, #0
    30fe:	601a      	str	r2, [r3, #0]
    3100:	681b      	ldr	r3, [r3, #0]
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    3102:	f04f 2350 	mov.w	r3, #1342197760	; 0x50005000
    3106:	f8d3 2418 	ldr.w	r2, [r3, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    310a:	f8d3 1418 	ldr.w	r1, [r3, #1048]	; 0x418
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_LFCLKSTARTED");

#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED)
        nrf_clock_lfclk_t lfclksrc;
        (void)nrf_clock_is_running(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK, &lfclksrc);
        if (lfclksrc == NRF_CLOCK_LFCLK_RC)
    310e:	f002 0203 	and.w	r2, r2, #3
    3112:	2a01      	cmp	r2, #1
    3114:	f04f 0102 	mov.w	r1, #2
    3118:	d103      	bne.n	3122 <nrfx_power_clock_irq_handler+0x4a>
    p_reg->LFCLKSRC = (uint32_t)(source);
    311a:	f8c3 1518 	str.w	r1, [r3, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    311e:	609a      	str	r2, [r3, #8]
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF192M_STARTED_MASK);

        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK192M_STARTED);
    }
#endif
}
    3120:	bd10      	pop	{r4, pc}
    p_reg->INTENCLR = mask;
    3122:	f8c3 1308 	str.w	r1, [r3, #776]	; 0x308
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    3126:	4b04      	ldr	r3, [pc, #16]	; (3138 <nrfx_power_clock_irq_handler+0x60>)
    3128:	2001      	movs	r0, #1
}
    312a:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    312e:	681b      	ldr	r3, [r3, #0]
    3130:	4718      	bx	r3
    3132:	bf00      	nop
    3134:	50005100 	.word	0x50005100
    3138:	200007f4 	.word	0x200007f4
    313c:	50005104 	.word	0x50005104

00003140 <nrfx_gpiote_channel_free>:
    return m_cb.allocated_channels_mask & (1UL << index);
}

static bool is_app_channel(uint8_t index)
{
    return NRFX_GPIOTE_APP_CHANNELS_MASK & (1UL << index);
    3140:	2301      	movs	r3, #1
    3142:	fa03 f000 	lsl.w	r0, r3, r0

nrfx_err_t nrfx_gpiote_channel_free(uint8_t channel)
{
    nrfx_err_t err_code = NRFX_SUCCESS;

    if (!is_app_channel(channel))
    3146:	f010 0fff 	tst.w	r0, #255	; 0xff
    314a:	d012      	beq.n	3172 <nrfx_gpiote_channel_free+0x32>
    314c:	f04f 0320 	mov.w	r3, #32
    3150:	f3ef 8111 	mrs	r1, BASEPRI
    3154:	f383 8811 	msr	BASEPRI, r3
    3158:	f3bf 8f6f 	isb	sy
    m_cb.allocated_channels_mask &= ~(1UL << index);
    315c:	4a06      	ldr	r2, [pc, #24]	; (3178 <nrfx_gpiote_channel_free+0x38>)
    315e:	6cd3      	ldr	r3, [r2, #76]	; 0x4c
    3160:	ea23 0000 	bic.w	r0, r3, r0
    3164:	64d0      	str	r0, [r2, #76]	; 0x4c
	__asm__ volatile(
    3166:	f381 8811 	msr	BASEPRI, r1
    316a:	f3bf 8f6f 	isb	sy
    316e:	4803      	ldr	r0, [pc, #12]	; (317c <nrfx_gpiote_channel_free+0x3c>)
    3170:	4770      	bx	lr
    {
        err_code = NRFX_ERROR_INVALID_PARAM;
    3172:	4803      	ldr	r0, [pc, #12]	; (3180 <nrfx_gpiote_channel_free+0x40>)
        NRFX_CRITICAL_SECTION_EXIT();
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    3174:	4770      	bx	lr
    3176:	bf00      	nop
    3178:	200007fc 	.word	0x200007fc
    317c:	0bad0000 	.word	0x0bad0000
    3180:	0bad0004 	.word	0x0bad0004

00003184 <nrfx_gpiote_channel_alloc>:

nrfx_err_t nrfx_gpiote_channel_alloc(uint8_t * p_channel)
{
    3184:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    nrfx_err_t err_code = NRFX_ERROR_NO_MEM;
    uint32_t mask = NRFX_GPIOTE_APP_CHANNELS_MASK;
    3188:	22ff      	movs	r2, #255	; 0xff
{
    318a:	2400      	movs	r4, #0
    return m_cb.allocated_channels_mask & (1UL << index);
    318c:	2601      	movs	r6, #1
{
    318e:	4605      	mov	r5, r0
    return m_cb.allocated_channels_mask & (1UL << index);
    3190:	f8df e058 	ldr.w	lr, [pc, #88]	; 31ec <nrfx_gpiote_channel_alloc+0x68>
    nrfx_err_t err_code = NRFX_ERROR_NO_MEM;
    3194:	4814      	ldr	r0, [pc, #80]	; (31e8 <nrfx_gpiote_channel_alloc+0x64>)
        NRFX_CRITICAL_SECTION_ENTER();
        if ((mask & (1UL << ch_idx)) && (!is_allocated_channel(ch_idx)))
        {
            channel_allocated_set(ch_idx);
            *p_channel = ch_idx;
            err_code = NRFX_SUCCESS;
    3196:	f8df 8058 	ldr.w	r8, [pc, #88]	; 31f0 <nrfx_gpiote_channel_alloc+0x6c>
    319a:	b2e3      	uxtb	r3, r4
	__asm__ volatile(
    319c:	f04f 0120 	mov.w	r1, #32
    31a0:	f3ef 8c11 	mrs	ip, BASEPRI
    31a4:	f381 8811 	msr	BASEPRI, r1
    31a8:	f3bf 8f6f 	isb	sy
        if ((mask & (1UL << ch_idx)) && (!is_allocated_channel(ch_idx)))
    31ac:	fa22 f103 	lsr.w	r1, r2, r3
    31b0:	07c9      	lsls	r1, r1, #31
    31b2:	d50a      	bpl.n	31ca <nrfx_gpiote_channel_alloc+0x46>
    return m_cb.allocated_channels_mask & (1UL << index);
    31b4:	f8de 104c 	ldr.w	r1, [lr, #76]	; 0x4c
    31b8:	fa06 f703 	lsl.w	r7, r6, r3
        if ((mask & (1UL << ch_idx)) && (!is_allocated_channel(ch_idx)))
    31bc:	4239      	tst	r1, r7
            err_code = NRFX_SUCCESS;
    31be:	bf01      	itttt	eq
    31c0:	4640      	moveq	r0, r8
    m_cb.allocated_channels_mask |= (1UL << index);
    31c2:	4339      	orreq	r1, r7
    31c4:	f8ce 104c 	streq.w	r1, [lr, #76]	; 0x4c
            *p_channel = ch_idx;
    31c8:	702b      	strbeq	r3, [r5, #0]
	__asm__ volatile(
    31ca:	f38c 8811 	msr	BASEPRI, ip
    31ce:	f3bf 8f6f 	isb	sy
        }
        NRFX_CRITICAL_SECTION_EXIT();

        if (err_code == NRFX_SUCCESS)
    31d2:	4540      	cmp	r0, r8
    31d4:	d005      	beq.n	31e2 <nrfx_gpiote_channel_alloc+0x5e>
        {
            NRFX_LOG_INFO("Allocated channel: %d.", ch_idx);
            break;
        }

        mask &= ~(1UL << ch_idx);
    31d6:	fa06 f303 	lsl.w	r3, r6, r3
    for (uint8_t ch_idx = 0; mask != 0; ch_idx++)
    31da:	439a      	bics	r2, r3
    31dc:	f104 0401 	add.w	r4, r4, #1
    31e0:	d1db      	bne.n	319a <nrfx_gpiote_channel_alloc+0x16>
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    31e2:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    31e6:	bf00      	nop
    31e8:	0bad0002 	.word	0x0bad0002
    31ec:	200007fc 	.word	0x200007fc
    31f0:	0bad0000 	.word	0x0bad0000

000031f4 <idle>:
#else
#define IDLE_YIELD_IF_COOP() do { } while (false)
#endif

void idle(void *p1, void *unused2, void *unused3)
{
    31f4:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    31f6:	4605      	mov	r5, r0
		 */
		int key = arch_irq_lock();
		struct k_thread *to_abort = cpu->pending_abort;

		if (to_abort) {
			cpu->pending_abort = NULL;
    31f8:	2700      	movs	r7, #0
		 * saves no power and does not improve latency.  But it's an
		 * API we need to honor...
		 */
		z_set_timeout_expiry((ticks < IDLE_THRESH) ? 1 : ticks, true);
#ifdef CONFIG_PM
		_kernel.idle = ticks;
    31fa:	4e15      	ldr	r6, [pc, #84]	; (3250 <idle+0x5c>)
	__asm__ volatile(
    31fc:	f04f 0220 	mov.w	r2, #32
    3200:	f3ef 8311 	mrs	r3, BASEPRI
    3204:	f382 8811 	msr	BASEPRI, r2
    3208:	f3bf 8f6f 	isb	sy
		struct k_thread *to_abort = cpu->pending_abort;
    320c:	6928      	ldr	r0, [r5, #16]
		if (to_abort) {
    320e:	b188      	cbz	r0, 3234 <idle+0x40>
			cpu->pending_abort = NULL;
    3210:	612f      	str	r7, [r5, #16]
	__asm__ volatile(
    3212:	f383 8811 	msr	BASEPRI, r3
    3216:	f3bf 8f6f 	isb	sy
			z_thread_single_abort(to_abort);
    321a:	f000 fbc3 	bl	39a4 <z_thread_single_abort>
	__asm__ volatile(
    321e:	f04f 0320 	mov.w	r3, #32
    3222:	f3ef 8011 	mrs	r0, BASEPRI
    3226:	f383 8811 	msr	BASEPRI, r3
    322a:	f3bf 8f6f 	isb	sy
    322e:	f002 fc47 	bl	5ac0 <z_reschedule_irqlock>
			continue;
    3232:	e7e3      	b.n	31fc <idle+0x8>
		int32_t ticks = z_get_next_timeout_expiry();
    3234:	f002 fd0a 	bl	5c4c <z_get_next_timeout_expiry>
		z_set_timeout_expiry((ticks < IDLE_THRESH) ? 1 : ticks, true);
    3238:	2101      	movs	r1, #1
		int32_t ticks = z_get_next_timeout_expiry();
    323a:	4604      	mov	r4, r0
		z_set_timeout_expiry((ticks < IDLE_THRESH) ? 1 : ticks, true);
    323c:	2802      	cmp	r0, #2
    323e:	bfd8      	it	le
    3240:	4608      	movle	r0, r1
    3242:	f002 fd13 	bl	5c6c <z_set_timeout_expiry>
		_kernel.idle = ticks;
    3246:	6274      	str	r4, [r6, #36]	; 0x24
	arch_cpu_idle();
    3248:	f7ff f80c 	bl	2264 <arch_cpu_idle>
}
    324c:	e7d6      	b.n	31fc <idle+0x8>
    324e:	bf00      	nop
    3250:	2000084c 	.word	0x2000084c

00003254 <z_bss_zero>:
 *
 * @return N/A
 */
void z_bss_zero(void)
{
	(void)memset(__bss_start, 0, __bss_end - __bss_start);
    3254:	4802      	ldr	r0, [pc, #8]	; (3260 <z_bss_zero+0xc>)
    3256:	4a03      	ldr	r2, [pc, #12]	; (3264 <z_bss_zero+0x10>)
    3258:	2100      	movs	r1, #0
    325a:	1a12      	subs	r2, r2, r0
    325c:	f002 bb67 	b.w	592e <memset>
    3260:	20000128 	.word	0x20000128
    3264:	200008b0 	.word	0x200008b0

00003268 <bg_thread_main>:
{
	ARG_UNUSED(unused1);
	ARG_UNUSED(unused2);
	ARG_UNUSED(unused3);

	z_sys_post_kernel = true;
    3268:	2201      	movs	r2, #1
{
    326a:	b508      	push	{r3, lr}
	z_sys_post_kernel = true;
    326c:	4b09      	ldr	r3, [pc, #36]	; (3294 <bg_thread_main+0x2c>)

	z_sys_init_run_level(_SYS_INIT_LEVEL_POST_KERNEL);
    326e:	2002      	movs	r0, #2
	z_sys_post_kernel = true;
    3270:	701a      	strb	r2, [r3, #0]
	z_sys_init_run_level(_SYS_INIT_LEVEL_POST_KERNEL);
    3272:	f000 ffcf 	bl	4214 <z_sys_init_run_level>
#if CONFIG_STACK_POINTER_RANDOM
	z_stack_adjust_initialized = 1;
#endif
	boot_banner();
    3276:	f002 fcd2 	bl	5c1e <boot_banner>
	__do_global_ctors_aux();
	__do_init_array_aux();
#endif

	/* Final init level before app starts */
	z_sys_init_run_level(_SYS_INIT_LEVEL_APPLICATION);
    327a:	2003      	movs	r0, #3
    327c:	f000 ffca 	bl	4214 <z_sys_init_run_level>

	z_init_static_threads();
    3280:	f000 fdda 	bl	3e38 <z_init_static_threads>
	z_timestamp_main = k_cycle_get_32();
#endif

	extern void main(void);

	main();
    3284:	f001 ff2e 	bl	50e4 <main>

	/* Mark nonessenrial since main() has no more work to do */
	z_main_thread.base.user_options &= ~K_ESSENTIAL;
    3288:	4a03      	ldr	r2, [pc, #12]	; (3298 <bg_thread_main+0x30>)
    328a:	7b13      	ldrb	r3, [r2, #12]
    328c:	f023 0301 	bic.w	r3, r3, #1
    3290:	7313      	strb	r3, [r2, #12]

#ifdef CONFIG_COVERAGE_DUMP
	/* Dump coverage data once the main() has exited. */
	gcov_coverage_dump();
#endif
} /* LCOV_EXCL_LINE ... because we just dumped final coverage data */
    3292:	bd08      	pop	{r3, pc}
    3294:	200008ae 	.word	0x200008ae
    3298:	200001a8 	.word	0x200001a8

0000329c <z_cstart>:
 * cleared/zeroed.
 *
 * @return Does not return
 */
FUNC_NORETURN void z_cstart(void)
{
    329c:	e92d 4880 	stmdb	sp!, {r7, fp, lr}
 * @return N/A
 */
static ALWAYS_INLINE void z_arm_interrupt_stack_setup(void)
{
	uint32_t msp =
		(uint32_t)(Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[0])) +
    32a0:	4b37      	ldr	r3, [pc, #220]	; (3380 <z_cstart+0xe4>)
    32a2:	b0a7      	sub	sp, #156	; 0x9c
	uint32_t msp =
    32a4:	f503 6900 	add.w	r9, r3, #2048	; 0x800
  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
    32a8:	f389 8808 	msr	MSP, r9
  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
    32ac:	f383 880a 	msr	MSPLIM, r3
    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    32b0:	2400      	movs	r4, #0
    32b2:	23e0      	movs	r3, #224	; 0xe0
    32b4:	4d33      	ldr	r5, [pc, #204]	; (3384 <z_cstart+0xe8>)
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    32b6:	f04f 0b01 	mov.w	fp, #1
    32ba:	f885 3022 	strb.w	r3, [r5, #34]	; 0x22
    32be:	77ec      	strb	r4, [r5, #31]
    32c0:	762c      	strb	r4, [r5, #24]
    32c2:	766c      	strb	r4, [r5, #25]
    32c4:	76ac      	strb	r4, [r5, #26]
    32c6:	76ec      	strb	r4, [r5, #27]
#if defined(CONFIG_ARM_SECURE_FIRMWARE)
	NVIC_SetPriority(SecureFault_IRQn, _EXC_FAULT_PRIO);
#endif /* CONFIG_ARM_SECURE_FIRMWARE */

	/* Enable Usage, Mem, & Bus Faults */
	SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk |
    32c8:	6a6b      	ldr	r3, [r5, #36]	; 0x24
	_kernel.ready_q.cache = &z_main_thread;
    32ca:	4e2f      	ldr	r6, [pc, #188]	; (3388 <z_cstart+0xec>)
    32cc:	f443 23e0 	orr.w	r3, r3, #458752	; 0x70000
    32d0:	626b      	str	r3, [r5, #36]	; 0x24
		      SCB_SHCSR_BUSFAULTENA_Msk;
#if defined(CONFIG_ARM_SECURE_FIRMWARE)
	/* Enable Secure Fault */
	SCB->SHCSR |= SCB_SHCSR_SECUREFAULTENA_Msk;
    32d2:	6a6b      	ldr	r3, [r5, #36]	; 0x24
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    32d4:	f8df a0cc 	ldr.w	sl, [pc, #204]	; 33a4 <z_cstart+0x108>
    32d8:	f443 2300 	orr.w	r3, r3, #524288	; 0x80000
    32dc:	626b      	str	r3, [r5, #36]	; 0x24
	/* Clear BFAR before setting BusFaults to target Non-Secure state. */
	SCB->BFAR = 0;
    32de:	63ac      	str	r4, [r5, #56]	; 0x38

static ALWAYS_INLINE void arch_kernel_init(void)
{
	z_arm_interrupt_stack_setup();
	z_arm_exc_setup();
	z_arm_fault_init();
    32e0:	f7ff f952 	bl	2588 <z_arm_fault_init>
	z_arm_cpu_idle_init();
    32e4:	f7fe ffb8 	bl	2258 <z_arm_cpu_idle_init>
static ALWAYS_INLINE void z_arm_clear_faults(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* Reset all faults */
	SCB->CFSR = SCB_CFSR_USGFAULTSR_Msk |
    32e8:	f04f 33ff 	mov.w	r3, #4294967295	; 0xffffffff
    32ec:	62ab      	str	r3, [r5, #40]	; 0x28
		    SCB_CFSR_MEMFAULTSR_Msk |
		    SCB_CFSR_BUSFAULTSR_Msk;

	/* Clear all Hard Faults - HFSR is write-one-to-clear */
	SCB->HFSR = 0xffffffff;
    32ee:	62eb      	str	r3, [r5, #44]	; 0x2c
{
	dummy_thread->base.thread_state = _THREAD_DUMMY;
#ifdef CONFIG_SCHED_CPU_MASK
	dummy_thread->base.cpu_mask = -1;
#endif
	dummy_thread->base.user_options = K_ESSENTIAL;
    32f0:	f240 1301 	movw	r3, #257	; 0x101
#endif
#ifdef CONFIG_USERSPACE
	dummy_thread->mem_domain_info.mem_domain = &k_mem_domain_default;
#endif

	_current_cpu->current = dummy_thread;
    32f4:	4d25      	ldr	r5, [pc, #148]	; (338c <z_cstart+0xf0>)
	dummy_thread->base.user_options = K_ESSENTIAL;
    32f6:	f8ad 3024 	strh.w	r3, [sp, #36]	; 0x24
	_current_cpu->current = dummy_thread;
    32fa:	ab06      	add	r3, sp, #24
    32fc:	60ab      	str	r3, [r5, #8]

	z_dummy_thread_init(&dummy_thread);
#endif

	/* perform basic hardware initialization */
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_1);
    32fe:	4620      	mov	r0, r4
	dummy_thread->stack_info.size = 0U;
    3300:	e9cd 4420 	strd	r4, r4, [sp, #128]	; 0x80
    3304:	f000 ff86 	bl	4214 <z_sys_init_run_level>
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_2);
    3308:	2001      	movs	r0, #1
    330a:	f000 ff83 	bl	4214 <z_sys_init_run_level>
	z_sched_init();
    330e:	f000 fc99 	bl	3c44 <z_sched_init>
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    3312:	4b1f      	ldr	r3, [pc, #124]	; (3390 <z_cstart+0xf4>)
	_kernel.ready_q.cache = &z_main_thread;
    3314:	62ae      	str	r6, [r5, #40]	; 0x28
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    3316:	f44f 6280 	mov.w	r2, #1024	; 0x400
    331a:	491e      	ldr	r1, [pc, #120]	; (3394 <z_cstart+0xf8>)
    331c:	9305      	str	r3, [sp, #20]
    331e:	4630      	mov	r0, r6
    3320:	4653      	mov	r3, sl
    3322:	e9cd 4b03 	strd	r4, fp, [sp, #12]
    3326:	e9cd 4401 	strd	r4, r4, [sp, #4]
    332a:	9400      	str	r4, [sp, #0]
    332c:	f000 fd54 	bl	3dd8 <z_setup_new_thread>
	sys_trace_thread_resume(thread);
}

static inline void z_mark_thread_as_started(struct k_thread *thread)
{
	thread->base.thread_state &= ~_THREAD_PRESTART;
    3330:	7b73      	ldrb	r3, [r6, #13]
    3332:	4680      	mov	r8, r0
    3334:	f023 0304 	bic.w	r3, r3, #4
	z_ready_thread(&z_main_thread);
    3338:	4630      	mov	r0, r6
    333a:	7373      	strb	r3, [r6, #13]
    333c:	f002 fbe8 	bl	5b10 <z_ready_thread>
	z_setup_new_thread(thread, stack,
    3340:	230f      	movs	r3, #15
    3342:	4f15      	ldr	r7, [pc, #84]	; (3398 <z_cstart+0xfc>)
    3344:	f44f 72a0 	mov.w	r2, #320	; 0x140
    3348:	e9cd 4302 	strd	r4, r3, [sp, #8]
    334c:	4913      	ldr	r1, [pc, #76]	; (339c <z_cstart+0x100>)
    334e:	4b14      	ldr	r3, [pc, #80]	; (33a0 <z_cstart+0x104>)
    3350:	4638      	mov	r0, r7
    3352:	e9cd b404 	strd	fp, r4, [sp, #16]
    3356:	e9cd 5400 	strd	r5, r4, [sp]
    335a:	f000 fd3d 	bl	3dd8 <z_setup_new_thread>
    335e:	7b7b      	ldrb	r3, [r7, #13]
	arch_switch_to_main_thread(&z_main_thread, stack_ptr, bg_thread_main);
    3360:	4652      	mov	r2, sl
    3362:	f023 0304 	bic.w	r3, r3, #4
    3366:	737b      	strb	r3, [r7, #13]
 * @return N/A
 */

static inline void sys_dlist_init(sys_dlist_t *list)
{
	list->head = (sys_dnode_t *)list;
    3368:	f105 031c 	add.w	r3, r5, #28
    336c:	4641      	mov	r1, r8
    336e:	4630      	mov	r0, r6
	list->tail = (sys_dnode_t *)list;
    3370:	e9c5 3307 	strd	r3, r3, [r5, #28]
		_kernel.cpus[i].idle_thread = &z_idle_threads[i];
    3374:	60ef      	str	r7, [r5, #12]
		_kernel.cpus[i].id = i;
    3376:	762c      	strb	r4, [r5, #24]
		_kernel.cpus[i].irq_stack =
    3378:	f8c5 9004 	str.w	r9, [r5, #4]
	arch_switch_to_main_thread(&z_main_thread, stack_ptr, bg_thread_main);
    337c:	f7fe ff4e 	bl	221c <arch_switch_to_main_thread>
	CODE_UNREACHABLE; /* LCOV_EXCL_LINE */
    3380:	20000df0 	.word	0x20000df0
    3384:	e000ed00 	.word	0xe000ed00
    3388:	200001a8 	.word	0x200001a8
    338c:	2000084c 	.word	0x2000084c
    3390:	000065b9 	.word	0x000065b9
    3394:	200008b0 	.word	0x200008b0
    3398:	20000128 	.word	0x20000128
    339c:	20000cb0 	.word	0x20000cb0
    33a0:	000031f5 	.word	0x000031f5
    33a4:	00003269 	.word	0x00003269

000033a8 <init_mem_slab_module>:
 * Perform any initialization that wasn't done at build time.
 *
 * @return N/A
 */
static int init_mem_slab_module(const struct device *dev)
{
    33a8:	b570      	push	{r4, r5, r6, lr}
	int rc = 0;
	ARG_UNUSED(dev);

	Z_STRUCT_SECTION_FOREACH(k_mem_slab, slab) {
    33aa:	4b0e      	ldr	r3, [pc, #56]	; (33e4 <init_mem_slab_module+0x3c>)
    33ac:	4c0e      	ldr	r4, [pc, #56]	; (33e8 <init_mem_slab_module+0x40>)
    33ae:	42a3      	cmp	r3, r4
    33b0:	d301      	bcc.n	33b6 <init_mem_slab_module+0xe>
		}
		SYS_TRACING_OBJ_INIT(k_mem_slab, slab);
		z_object_init(slab);
	}

out:
    33b2:	2000      	movs	r0, #0
	return rc;
}
    33b4:	bd70      	pop	{r4, r5, r6, pc}
	CHECKIF(((slab->block_size | (uintptr_t)slab->buffer) &
    33b6:	e9d3 0103 	ldrd	r0, r1, [r3, #12]
    33ba:	ea41 0200 	orr.w	r2, r1, r0
    33be:	f012 0203 	ands.w	r2, r2, #3
    33c2:	d10b      	bne.n	33dc <init_mem_slab_module+0x34>
	for (j = 0U; j < slab->num_blocks; j++) {
    33c4:	689d      	ldr	r5, [r3, #8]
	slab->free_list = NULL;
    33c6:	615a      	str	r2, [r3, #20]
	for (j = 0U; j < slab->num_blocks; j++) {
    33c8:	42aa      	cmp	r2, r5
    33ca:	d101      	bne.n	33d0 <init_mem_slab_module+0x28>
	Z_STRUCT_SECTION_FOREACH(k_mem_slab, slab) {
    33cc:	331c      	adds	r3, #28
    33ce:	e7ee      	b.n	33ae <init_mem_slab_module+0x6>
		*(char **)p = slab->free_list;
    33d0:	695e      	ldr	r6, [r3, #20]
	for (j = 0U; j < slab->num_blocks; j++) {
    33d2:	3201      	adds	r2, #1
		*(char **)p = slab->free_list;
    33d4:	600e      	str	r6, [r1, #0]
		slab->free_list = p;
    33d6:	6159      	str	r1, [r3, #20]
		p += slab->block_size;
    33d8:	4401      	add	r1, r0
	for (j = 0U; j < slab->num_blocks; j++) {
    33da:	e7f5      	b.n	33c8 <init_mem_slab_module+0x20>
		return -EINVAL;
    33dc:	f06f 0015 	mvn.w	r0, #21
	return rc;
    33e0:	e7e8      	b.n	33b4 <init_mem_slab_module+0xc>
    33e2:	bf00      	nop
    33e4:	200000d4 	.word	0x200000d4
    33e8:	200000d4 	.word	0x200000d4

000033ec <k_mem_slab_alloc>:
out:
	return rc;
}

int k_mem_slab_alloc(struct k_mem_slab *slab, void **mem, k_timeout_t timeout)
{
    33ec:	b5d3      	push	{r0, r1, r4, r6, r7, lr}
    33ee:	460c      	mov	r4, r1
    33f0:	4616      	mov	r6, r2
    33f2:	461f      	mov	r7, r3
    33f4:	f04f 0320 	mov.w	r3, #32
    33f8:	f3ef 8111 	mrs	r1, BASEPRI
    33fc:	f383 8811 	msr	BASEPRI, r3
    3400:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&lock);
	int result;

	if (slab->free_list != NULL) {
    3404:	6943      	ldr	r3, [r0, #20]
    3406:	b15b      	cbz	r3, 3420 <k_mem_slab_alloc+0x34>
		/* take a free block */
		*mem = slab->free_list;
    3408:	6023      	str	r3, [r4, #0]
		slab->free_list = *(char **)(slab->free_list);
    340a:	681b      	ldr	r3, [r3, #0]
    340c:	6143      	str	r3, [r0, #20]
		slab->num_used++;
    340e:	6983      	ldr	r3, [r0, #24]
    3410:	3301      	adds	r3, #1
    3412:	6183      	str	r3, [r0, #24]

#ifdef CONFIG_MEM_SLAB_TRACE_MAX_UTILIZATION
		slab->max_used = MAX(slab->num_used, slab->max_used);
#endif

		result = 0;
    3414:	2000      	movs	r0, #0
	__asm__ volatile(
    3416:	f381 8811 	msr	BASEPRI, r1
    341a:	f3bf 8f6f 	isb	sy
		return result;
	}

	k_spin_unlock(&lock, key);

	return result;
    341e:	e011      	b.n	3444 <k_mem_slab_alloc+0x58>
	} else if (K_TIMEOUT_EQ(timeout, K_NO_WAIT)) {
    3420:	ea56 0207 	orrs.w	r2, r6, r7
    3424:	d103      	bne.n	342e <k_mem_slab_alloc+0x42>
		result = -ENOMEM;
    3426:	f06f 000b 	mvn.w	r0, #11
		*mem = NULL;
    342a:	6023      	str	r3, [r4, #0]
		result = -ENOMEM;
    342c:	e7f3      	b.n	3416 <k_mem_slab_alloc+0x2a>
		result = z_pend_curr(&lock, key, &slab->wait_q, timeout);
    342e:	4602      	mov	r2, r0
    3430:	e9cd 6700 	strd	r6, r7, [sp]
    3434:	4804      	ldr	r0, [pc, #16]	; (3448 <k_mem_slab_alloc+0x5c>)
    3436:	f000 fb77 	bl	3b28 <z_pend_curr>
		if (result == 0) {
    343a:	b918      	cbnz	r0, 3444 <k_mem_slab_alloc+0x58>
			*mem = _current->base.swap_data;
    343c:	4b03      	ldr	r3, [pc, #12]	; (344c <k_mem_slab_alloc+0x60>)
    343e:	689b      	ldr	r3, [r3, #8]
    3440:	695b      	ldr	r3, [r3, #20]
    3442:	6023      	str	r3, [r4, #0]
}
    3444:	b002      	add	sp, #8
    3446:	bdd0      	pop	{r4, r6, r7, pc}
    3448:	200008af 	.word	0x200008af
    344c:	2000084c 	.word	0x2000084c

00003450 <k_mem_slab_free>:

void k_mem_slab_free(struct k_mem_slab *slab, void **mem)
{
    3450:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    3452:	4604      	mov	r4, r0
    3454:	460d      	mov	r5, r1
	__asm__ volatile(
    3456:	f04f 0320 	mov.w	r3, #32
    345a:	f3ef 8611 	mrs	r6, BASEPRI
    345e:	f383 8811 	msr	BASEPRI, r3
    3462:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&lock);

	if (slab->free_list == NULL) {
    3466:	6947      	ldr	r7, [r0, #20]
    3468:	b96f      	cbnz	r7, 3486 <k_mem_slab_free+0x36>
		struct k_thread *pending_thread = z_unpend_first_thread(&slab->wait_q);
    346a:	f002 fba9 	bl	5bc0 <z_unpend_first_thread>

		if (pending_thread != NULL) {
    346e:	b150      	cbz	r0, 3486 <k_mem_slab_free+0x36>
			z_thread_return_value_set_with_data(pending_thread, 0, *mem);
    3470:	682a      	ldr	r2, [r5, #0]
}

static ALWAYS_INLINE void
arch_thread_return_value_set(struct k_thread *thread, unsigned int value)
{
	thread->arch.swap_return_value = value;
    3472:	67c7      	str	r7, [r0, #124]	; 0x7c
z_thread_return_value_set_with_data(struct k_thread *thread,
				   unsigned int value,
				   void *data)
{
	arch_thread_return_value_set(thread, value);
	thread->base.swap_data = data;
    3474:	6142      	str	r2, [r0, #20]
			z_ready_thread(pending_thread);
    3476:	f002 fb4b 	bl	5b10 <z_ready_thread>
			z_reschedule(&lock, key);
    347a:	4631      	mov	r1, r6
	}
	**(char ***) mem = slab->free_list;
	slab->free_list = *(char **) mem;
	slab->num_used--;
	k_spin_unlock(&lock, key);
}
    347c:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
			z_reschedule(&lock, key);
    3480:	4807      	ldr	r0, [pc, #28]	; (34a0 <k_mem_slab_free+0x50>)
    3482:	f000 b90f 	b.w	36a4 <z_reschedule>
	**(char ***) mem = slab->free_list;
    3486:	682b      	ldr	r3, [r5, #0]
    3488:	6962      	ldr	r2, [r4, #20]
    348a:	601a      	str	r2, [r3, #0]
	slab->free_list = *(char **) mem;
    348c:	682b      	ldr	r3, [r5, #0]
    348e:	6163      	str	r3, [r4, #20]
	slab->num_used--;
    3490:	69a3      	ldr	r3, [r4, #24]
    3492:	3b01      	subs	r3, #1
    3494:	61a3      	str	r3, [r4, #24]
	__asm__ volatile(
    3496:	f386 8811 	msr	BASEPRI, r6
    349a:	f3bf 8f6f 	isb	sy
}
    349e:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    34a0:	200008af 	.word	0x200008af

000034a4 <z_impl_k_mutex_lock>:
	}
	return false;
}

int z_impl_k_mutex_lock(struct k_mutex *mutex, k_timeout_t timeout)
{
    34a4:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
    34a8:	4604      	mov	r4, r0
    34aa:	4616      	mov	r6, r2
    34ac:	461f      	mov	r7, r3
	__asm__ volatile(
    34ae:	f04f 0320 	mov.w	r3, #32
    34b2:	f3ef 8811 	mrs	r8, BASEPRI
    34b6:	f383 8811 	msr	BASEPRI, r3
    34ba:	f3bf 8f6f 	isb	sy
	__ASSERT(!arch_is_in_isr(), "mutexes cannot be used inside ISRs");

	sys_trace_mutex_lock(mutex);
	key = k_spin_lock(&lock);

	if (likely((mutex->lock_count == 0U) || (mutex->owner == _current))) {
    34be:	68c3      	ldr	r3, [r0, #12]
    34c0:	4a32      	ldr	r2, [pc, #200]	; (358c <z_impl_k_mutex_lock+0xe8>)
    34c2:	b16b      	cbz	r3, 34e0 <z_impl_k_mutex_lock+0x3c>
    34c4:	6880      	ldr	r0, [r0, #8]
    34c6:	6891      	ldr	r1, [r2, #8]
    34c8:	4288      	cmp	r0, r1
    34ca:	d019      	beq.n	3500 <z_impl_k_mutex_lock+0x5c>
		sys_trace_end_call(SYS_TRACE_ID_MUTEX_LOCK);

		return 0;
	}

	if (unlikely(K_TIMEOUT_EQ(timeout, K_NO_WAIT))) {
    34cc:	ea56 0307 	orrs.w	r3, r6, r7
    34d0:	d118      	bne.n	3504 <z_impl_k_mutex_lock+0x60>
	__asm__ volatile(
    34d2:	f388 8811 	msr	BASEPRI, r8
    34d6:	f3bf 8f6f 	isb	sy
		k_spin_unlock(&lock, key);
		sys_trace_end_call(SYS_TRACE_ID_MUTEX_LOCK);
		return -EBUSY;
    34da:	f06f 000f 	mvn.w	r0, #15
    34de:	e00c      	b.n	34fa <z_impl_k_mutex_lock+0x56>
					_current->base.prio :
    34e0:	6891      	ldr	r1, [r2, #8]
    34e2:	f991 100e 	ldrsb.w	r1, [r1, #14]
		mutex->lock_count++;
    34e6:	3301      	adds	r3, #1
    34e8:	60e3      	str	r3, [r4, #12]
		mutex->owner = _current;
    34ea:	6893      	ldr	r3, [r2, #8]
		mutex->owner_orig_prio = (mutex->lock_count == 0U) ?
    34ec:	6121      	str	r1, [r4, #16]
		mutex->owner = _current;
    34ee:	60a3      	str	r3, [r4, #8]
    34f0:	f388 8811 	msr	BASEPRI, r8
    34f4:	f3bf 8f6f 	isb	sy
		return 0;
    34f8:	2000      	movs	r0, #0
		k_spin_unlock(&lock, key);
	}

	sys_trace_end_call(SYS_TRACE_ID_MUTEX_LOCK);
	return -EAGAIN;
}
    34fa:	b002      	add	sp, #8
    34fc:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
					_current->base.prio :
    3500:	6921      	ldr	r1, [r4, #16]
    3502:	e7f0      	b.n	34e6 <z_impl_k_mutex_lock+0x42>
	new_prio = new_prio_for_inheritance(_current->base.prio,
    3504:	f990 300e 	ldrsb.w	r3, [r0, #14]
    3508:	f991 100e 	ldrsb.w	r1, [r1, #14]
    350c:	4299      	cmp	r1, r3
    350e:	bfa8      	it	ge
    3510:	4619      	movge	r1, r3
    3512:	ea21 71e1 	bic.w	r1, r1, r1, asr #31
	if (z_is_prio_higher(new_prio, mutex->owner->base.prio)) {
    3516:	4299      	cmp	r1, r3
    3518:	da2c      	bge.n	3574 <z_impl_k_mutex_lock+0xd0>
		return z_set_prio(mutex->owner, new_prio);
    351a:	f000 fb53 	bl	3bc4 <z_set_prio>
    351e:	4605      	mov	r5, r0
	int got_mutex = z_pend_curr(&lock, key, &mutex->wait_q, timeout);
    3520:	4622      	mov	r2, r4
    3522:	4641      	mov	r1, r8
    3524:	e9cd 6700 	strd	r6, r7, [sp]
    3528:	4819      	ldr	r0, [pc, #100]	; (3590 <z_impl_k_mutex_lock+0xec>)
    352a:	f000 fafd 	bl	3b28 <z_pend_curr>
	if (got_mutex == 0) {
    352e:	2800      	cmp	r0, #0
    3530:	d0e3      	beq.n	34fa <z_impl_k_mutex_lock+0x56>
	__asm__ volatile(
    3532:	f04f 0320 	mov.w	r3, #32
    3536:	f3ef 8611 	mrs	r6, BASEPRI
    353a:	f383 8811 	msr	BASEPRI, r3
    353e:	f3bf 8f6f 	isb	sy
 * @return true if empty, false otherwise
 */

static inline bool sys_dlist_is_empty(sys_dlist_t *list)
{
	return list->head == list;
    3542:	6823      	ldr	r3, [r4, #0]
    3544:	6921      	ldr	r1, [r4, #16]
 * @return a pointer to the head element, NULL if list is empty
 */

static inline sys_dnode_t *sys_dlist_peek_head(sys_dlist_t *list)
{
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3546:	42a3      	cmp	r3, r4
    3548:	d007      	beq.n	355a <z_impl_k_mutex_lock+0xb6>
		new_prio_for_inheritance(waiter->base.prio, mutex->owner_orig_prio) :
    354a:	b133      	cbz	r3, 355a <z_impl_k_mutex_lock+0xb6>
    354c:	f993 300e 	ldrsb.w	r3, [r3, #14]
    3550:	4299      	cmp	r1, r3
    3552:	bfa8      	it	ge
    3554:	4619      	movge	r1, r3
    3556:	ea21 71e1 	bic.w	r1, r1, r1, asr #31
	resched = adjust_owner_prio(mutex, new_prio) || resched;
    355a:	68a0      	ldr	r0, [r4, #8]
	if (mutex->owner->base.prio != new_prio) {
    355c:	f990 300e 	ldrsb.w	r3, [r0, #14]
    3560:	4299      	cmp	r1, r3
    3562:	d109      	bne.n	3578 <z_impl_k_mutex_lock+0xd4>
	if (resched) {
    3564:	b16d      	cbz	r5, 3582 <z_impl_k_mutex_lock+0xde>
		z_reschedule(&lock, key);
    3566:	4631      	mov	r1, r6
    3568:	4809      	ldr	r0, [pc, #36]	; (3590 <z_impl_k_mutex_lock+0xec>)
    356a:	f000 f89b 	bl	36a4 <z_reschedule>
	return -EAGAIN;
    356e:	f06f 000a 	mvn.w	r0, #10
    3572:	e7c2      	b.n	34fa <z_impl_k_mutex_lock+0x56>
	bool resched = false;
    3574:	2500      	movs	r5, #0
    3576:	e7d3      	b.n	3520 <z_impl_k_mutex_lock+0x7c>
		return z_set_prio(mutex->owner, new_prio);
    3578:	f000 fb24 	bl	3bc4 <z_set_prio>
	resched = adjust_owner_prio(mutex, new_prio) || resched;
    357c:	2800      	cmp	r0, #0
    357e:	d1f2      	bne.n	3566 <z_impl_k_mutex_lock+0xc2>
    3580:	e7f0      	b.n	3564 <z_impl_k_mutex_lock+0xc0>
	__asm__ volatile(
    3582:	f386 8811 	msr	BASEPRI, r6
    3586:	f3bf 8f6f 	isb	sy
    358a:	e7f0      	b.n	356e <z_impl_k_mutex_lock+0xca>
    358c:	2000084c 	.word	0x2000084c
    3590:	200008af 	.word	0x200008af

00003594 <z_impl_k_mutex_unlock>:
}
#include <syscalls/k_mutex_lock_mrsh.c>
#endif

int z_impl_k_mutex_unlock(struct k_mutex *mutex)
{
    3594:	b538      	push	{r3, r4, r5, lr}
	struct k_thread *new_owner;

	__ASSERT(!arch_is_in_isr(), "mutexes cannot be used inside ISRs");

	CHECKIF(mutex->owner == NULL) {
    3596:	6883      	ldr	r3, [r0, #8]
{
    3598:	4604      	mov	r4, r0
	CHECKIF(mutex->owner == NULL) {
    359a:	2b00      	cmp	r3, #0
    359c:	d036      	beq.n	360c <z_impl_k_mutex_unlock+0x78>
		return -EINVAL;
	}
	/*
	 * The current thread does not own the mutex.
	 */
	CHECKIF(mutex->owner != _current) {
    359e:	4a1e      	ldr	r2, [pc, #120]	; (3618 <z_impl_k_mutex_unlock+0x84>)
    35a0:	6892      	ldr	r2, [r2, #8]
    35a2:	4293      	cmp	r3, r2
    35a4:	d135      	bne.n	3612 <z_impl_k_mutex_unlock+0x7e>
{
#ifdef CONFIG_PREEMPT_ENABLED
	__ASSERT(!arch_is_in_isr(), "");
	__ASSERT(_current->base.sched_locked != 1, "");

	--_current->base.sched_locked;
    35a6:	7bda      	ldrb	r2, [r3, #15]
    35a8:	3a01      	subs	r2, #1
    35aa:	73da      	strb	r2, [r3, #15]

	/*
	 * If we are the owner and count is greater than 1, then decrement
	 * the count and return and keep current thread as the owner.
	 */
	if (mutex->lock_count - 1U != 0U) {
    35ac:	68c3      	ldr	r3, [r0, #12]
    35ae:	2b01      	cmp	r3, #1
    35b0:	d005      	beq.n	35be <z_impl_k_mutex_unlock+0x2a>
		mutex->lock_count--;
    35b2:	3b01      	subs	r3, #1
    35b4:	60c3      	str	r3, [r0, #12]
		k_spin_unlock(&lock, key);
	}


k_mutex_unlock_return:
	k_sched_unlock();
    35b6:	f000 f8d9 	bl	376c <k_sched_unlock>
	sys_trace_end_call(SYS_TRACE_ID_MUTEX_UNLOCK);

	return 0;
    35ba:	2000      	movs	r0, #0
}
    35bc:	bd38      	pop	{r3, r4, r5, pc}
	__asm__ volatile(
    35be:	f04f 0320 	mov.w	r3, #32
    35c2:	f3ef 8511 	mrs	r5, BASEPRI
    35c6:	f383 8811 	msr	BASEPRI, r3
    35ca:	f3bf 8f6f 	isb	sy
	adjust_owner_prio(mutex, mutex->owner_orig_prio);
    35ce:	6901      	ldr	r1, [r0, #16]
    35d0:	6880      	ldr	r0, [r0, #8]
	if (mutex->owner->base.prio != new_prio) {
    35d2:	f990 300e 	ldrsb.w	r3, [r0, #14]
    35d6:	4299      	cmp	r1, r3
    35d8:	d001      	beq.n	35de <z_impl_k_mutex_unlock+0x4a>
		return z_set_prio(mutex->owner, new_prio);
    35da:	f000 faf3 	bl	3bc4 <z_set_prio>
	new_owner = z_unpend_first_thread(&mutex->wait_q);
    35de:	4620      	mov	r0, r4
    35e0:	f002 faee 	bl	5bc0 <z_unpend_first_thread>
	mutex->owner = new_owner;
    35e4:	60a0      	str	r0, [r4, #8]
	if (new_owner != NULL) {
    35e6:	b158      	cbz	r0, 3600 <z_impl_k_mutex_unlock+0x6c>
		mutex->owner_orig_prio = new_owner->base.prio;
    35e8:	f990 200e 	ldrsb.w	r2, [r0, #14]
    35ec:	6122      	str	r2, [r4, #16]
    35ee:	2200      	movs	r2, #0
    35f0:	67c2      	str	r2, [r0, #124]	; 0x7c
		z_ready_thread(new_owner);
    35f2:	f002 fa8d 	bl	5b10 <z_ready_thread>
		z_reschedule(&lock, key);
    35f6:	4629      	mov	r1, r5
    35f8:	4808      	ldr	r0, [pc, #32]	; (361c <z_impl_k_mutex_unlock+0x88>)
    35fa:	f000 f853 	bl	36a4 <z_reschedule>
    35fe:	e7da      	b.n	35b6 <z_impl_k_mutex_unlock+0x22>
		mutex->lock_count = 0U;
    3600:	60e0      	str	r0, [r4, #12]
	__asm__ volatile(
    3602:	f385 8811 	msr	BASEPRI, r5
    3606:	f3bf 8f6f 	isb	sy
    360a:	e7d4      	b.n	35b6 <z_impl_k_mutex_unlock+0x22>
		return -EINVAL;
    360c:	f06f 0015 	mvn.w	r0, #21
    3610:	e7d4      	b.n	35bc <z_impl_k_mutex_unlock+0x28>
		return -EPERM;
    3612:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
    3616:	e7d1      	b.n	35bc <z_impl_k_mutex_unlock+0x28>
    3618:	2000084c 	.word	0x2000084c
    361c:	200008af 	.word	0x200008af

00003620 <z_reset_time_slice>:
 */
static struct k_thread *pending_current;
#endif

void z_reset_time_slice(void)
{
    3620:	b510      	push	{r4, lr}
	/* Add the elapsed time since the last announced tick to the
	 * slice count, as we'll see those "expired" ticks arrive in a
	 * FUTURE z_time_slice() call.
	 */
	if (slice_time != 0) {
    3622:	4c08      	ldr	r4, [pc, #32]	; (3644 <z_reset_time_slice+0x24>)
    3624:	6823      	ldr	r3, [r4, #0]
    3626:	b15b      	cbz	r3, 3640 <z_reset_time_slice+0x20>
		_current_cpu->slice_ticks = slice_time + z_clock_elapsed();
    3628:	f7fe fa16 	bl	1a58 <z_clock_elapsed>
    362c:	6822      	ldr	r2, [r4, #0]
    362e:	4906      	ldr	r1, [pc, #24]	; (3648 <z_reset_time_slice+0x28>)
    3630:	4410      	add	r0, r2
    3632:	6148      	str	r0, [r1, #20]
		z_set_timeout_expiry(slice_time, false);
	}
}
    3634:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
		z_set_timeout_expiry(slice_time, false);
    3638:	2100      	movs	r1, #0
    363a:	4610      	mov	r0, r2
    363c:	f002 bb16 	b.w	5c6c <z_set_timeout_expiry>
}
    3640:	bd10      	pop	{r4, pc}
    3642:	bf00      	nop
    3644:	20000888 	.word	0x20000888
    3648:	2000084c 	.word	0x2000084c

0000364c <k_sched_time_slice_set>:

void k_sched_time_slice_set(int32_t slice, int prio)
{
    364c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    364e:	460c      	mov	r4, r1
	__asm__ volatile(
    3650:	f04f 0320 	mov.w	r3, #32
    3654:	f3ef 8511 	mrs	r5, BASEPRI
    3658:	f383 8811 	msr	BASEPRI, r3
    365c:	f3bf 8f6f 	isb	sy
		} else {
			return t * (to_hz / from_hz);
		}
	} else {
		if (result32) {
			return (uint32_t)((t * to_hz + off) / from_hz);
    3660:	f44f 4100 	mov.w	r1, #32768	; 0x8000
    3664:	f240 36e7 	movw	r6, #999	; 0x3e7
    3668:	2700      	movs	r7, #0
	LOCKED(&sched_spinlock) {
		_current_cpu->slice_ticks = 0;
    366a:	2200      	movs	r2, #0
    366c:	fbe1 6700 	umlal	r6, r7, r1, r0
    3670:	4b09      	ldr	r3, [pc, #36]	; (3698 <k_sched_time_slice_set+0x4c>)
    3672:	4630      	mov	r0, r6
    3674:	615a      	str	r2, [r3, #20]
    3676:	4639      	mov	r1, r7
    3678:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    367c:	2300      	movs	r3, #0
    367e:	f7fc fddd 	bl	23c <__aeabi_uldivmod>
		slice_time = k_ms_to_ticks_ceil32(slice);
    3682:	4b06      	ldr	r3, [pc, #24]	; (369c <k_sched_time_slice_set+0x50>)
    3684:	6018      	str	r0, [r3, #0]
		slice_max_prio = prio;
    3686:	4b06      	ldr	r3, [pc, #24]	; (36a0 <k_sched_time_slice_set+0x54>)
    3688:	601c      	str	r4, [r3, #0]
		z_reset_time_slice();
    368a:	f7ff ffc9 	bl	3620 <z_reset_time_slice>
	__asm__ volatile(
    368e:	f385 8811 	msr	BASEPRI, r5
    3692:	f3bf 8f6f 	isb	sy
	}
}
    3696:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    3698:	2000084c 	.word	0x2000084c
    369c:	20000888 	.word	0x20000888
    36a0:	20000884 	.word	0x20000884

000036a4 <z_reschedule>:
{
#ifdef CONFIG_SMP
	_current_cpu->swap_ok = 0;
#endif

	return arch_irq_unlocked(key) && !arch_is_in_isr();
    36a4:	b949      	cbnz	r1, 36ba <z_reschedule+0x16>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    36a6:	f3ef 8005 	mrs	r0, IPSR
    36aa:	b930      	cbnz	r0, 36ba <z_reschedule+0x16>
	return _kernel.ready_q.cache;
    36ac:	4b05      	ldr	r3, [pc, #20]	; (36c4 <z_reschedule+0x20>)
#endif
}

void z_reschedule(struct k_spinlock *lock, k_spinlock_key_t key)
{
	if (resched(key.key) && need_swap()) {
    36ae:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    36b0:	689b      	ldr	r3, [r3, #8]
    36b2:	429a      	cmp	r2, r3
    36b4:	d001      	beq.n	36ba <z_reschedule+0x16>
	ret = arch_swap(key);
    36b6:	f7fe bd0b 	b.w	20d0 <arch_swap>
    36ba:	f381 8811 	msr	BASEPRI, r1
    36be:	f3bf 8f6f 	isb	sy
		z_swap(lock, key);
	} else {
		k_spin_unlock(lock, key);
	}
}
    36c2:	4770      	bx	lr
    36c4:	2000084c 	.word	0x2000084c

000036c8 <k_sched_lock>:
	__asm__ volatile(
    36c8:	f04f 0320 	mov.w	r3, #32
    36cc:	f3ef 8111 	mrs	r1, BASEPRI
    36d0:	f383 8811 	msr	BASEPRI, r3
    36d4:	f3bf 8f6f 	isb	sy
	--_current->base.sched_locked;
    36d8:	4b04      	ldr	r3, [pc, #16]	; (36ec <k_sched_lock+0x24>)
    36da:	689a      	ldr	r2, [r3, #8]
    36dc:	7bd3      	ldrb	r3, [r2, #15]
    36de:	3b01      	subs	r3, #1
    36e0:	73d3      	strb	r3, [r2, #15]
	__asm__ volatile(
    36e2:	f381 8811 	msr	BASEPRI, r1
    36e6:	f3bf 8f6f 	isb	sy
void k_sched_lock(void)
{
	LOCKED(&sched_spinlock) {
		z_sched_lock();
	}
}
    36ea:	4770      	bx	lr
    36ec:	2000084c 	.word	0x2000084c

000036f0 <z_priq_dumb_remove>:
}

void z_priq_dumb_remove(sys_dlist_t *pq, struct k_thread *thread)
{
#if defined(CONFIG_SWAP_NONATOMIC) && defined(CONFIG_SCHED_DUMB)
	if (pq == &_kernel.ready_q.runq && thread == _current &&
    36f0:	4b09      	ldr	r3, [pc, #36]	; (3718 <z_priq_dumb_remove+0x28>)
    36f2:	f103 022c 	add.w	r2, r3, #44	; 0x2c
    36f6:	4282      	cmp	r2, r0
    36f8:	d105      	bne.n	3706 <z_priq_dumb_remove+0x16>
    36fa:	689b      	ldr	r3, [r3, #8]
    36fc:	428b      	cmp	r3, r1
    36fe:	d102      	bne.n	3706 <z_priq_dumb_remove+0x16>
    3700:	7b4b      	ldrb	r3, [r1, #13]
    3702:	06db      	lsls	r3, r3, #27
    3704:	d106      	bne.n	3714 <z_priq_dumb_remove+0x24>
 * @return N/A
 */

static inline void sys_dlist_remove(sys_dnode_t *node)
{
	node->prev->next = node->next;
    3706:	e9d1 3200 	ldrd	r3, r2, [r1]
    370a:	6013      	str	r3, [r2, #0]
	node->next->prev = node->prev;
    370c:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    370e:	2300      	movs	r3, #0
	node->prev = NULL;
    3710:	e9c1 3300 	strd	r3, r3, [r1]
#endif

	__ASSERT_NO_MSG(!z_is_idle_thread_object(thread));

	sys_dlist_remove(&thread->base.qnode_dlist);
}
    3714:	4770      	bx	lr
    3716:	bf00      	nop
    3718:	2000084c 	.word	0x2000084c

0000371c <update_cache>:
{
    371c:	b538      	push	{r3, r4, r5, lr}
    371e:	4c12      	ldr	r4, [pc, #72]	; (3768 <update_cache+0x4c>)
    3720:	4601      	mov	r1, r0
	if (_current_cpu->pending_abort != NULL) {
    3722:	6923      	ldr	r3, [r4, #16]
    3724:	68a2      	ldr	r2, [r4, #8]
    3726:	b10b      	cbz	r3, 372c <update_cache+0x10>
	return thread ? thread : _current_cpu->idle_thread;
    3728:	68e5      	ldr	r5, [r4, #12]
    372a:	e00c      	b.n	3746 <update_cache+0x2a>
	thread = _priq_run_best(&_kernel.ready_q.runq);
    372c:	f104 002c 	add.w	r0, r4, #44	; 0x2c
    3730:	f002 f9e8 	bl	5b04 <z_priq_dumb_best>
    3734:	4605      	mov	r5, r0
	if (_current->base.thread_state & _THREAD_ABORTING) {
    3736:	7b53      	ldrb	r3, [r2, #13]
    3738:	0698      	lsls	r0, r3, #26
		_current->base.thread_state |= _THREAD_DEAD;
    373a:	bf44      	itt	mi
    373c:	f043 0308 	orrmi.w	r3, r3, #8
    3740:	7353      	strbmi	r3, [r2, #13]
	return thread ? thread : _current_cpu->idle_thread;
    3742:	2d00      	cmp	r5, #0
    3744:	d0f0      	beq.n	3728 <update_cache+0xc>
	if (preempt_ok != 0) {
    3746:	b949      	cbnz	r1, 375c <update_cache+0x40>
	if (z_is_thread_prevented_from_running(_current)) {
    3748:	7b53      	ldrb	r3, [r2, #13]
    374a:	06db      	lsls	r3, r3, #27
    374c:	d106      	bne.n	375c <update_cache+0x40>
	if (IS_ENABLED(CONFIG_SWAP_NONATOMIC)
    374e:	69ab      	ldr	r3, [r5, #24]
    3750:	b923      	cbnz	r3, 375c <update_cache+0x40>
	if (is_preempt(_current) || is_metairq(thread)) {
    3752:	89d3      	ldrh	r3, [r2, #14]
    3754:	2b7f      	cmp	r3, #127	; 0x7f
    3756:	d901      	bls.n	375c <update_cache+0x40>
		_kernel.ready_q.cache = _current;
    3758:	62a2      	str	r2, [r4, #40]	; 0x28
}
    375a:	bd38      	pop	{r3, r4, r5, pc}
		if (thread != _current) {
    375c:	4295      	cmp	r5, r2
    375e:	d001      	beq.n	3764 <update_cache+0x48>
			z_reset_time_slice();
    3760:	f7ff ff5e 	bl	3620 <z_reset_time_slice>
		_kernel.ready_q.cache = thread;
    3764:	62a5      	str	r5, [r4, #40]	; 0x28
}
    3766:	e7f8      	b.n	375a <update_cache+0x3e>
    3768:	2000084c 	.word	0x2000084c

0000376c <k_sched_unlock>:
{
    376c:	b510      	push	{r4, lr}
	__asm__ volatile(
    376e:	f04f 0320 	mov.w	r3, #32
    3772:	f3ef 8411 	mrs	r4, BASEPRI
    3776:	f383 8811 	msr	BASEPRI, r3
    377a:	f3bf 8f6f 	isb	sy
		++_current->base.sched_locked;
    377e:	4b08      	ldr	r3, [pc, #32]	; (37a0 <k_sched_unlock+0x34>)
		update_cache(0);
    3780:	2000      	movs	r0, #0
		++_current->base.sched_locked;
    3782:	689a      	ldr	r2, [r3, #8]
    3784:	7bd3      	ldrb	r3, [r2, #15]
    3786:	3301      	adds	r3, #1
    3788:	73d3      	strb	r3, [r2, #15]
		update_cache(0);
    378a:	f7ff ffc7 	bl	371c <update_cache>
	__asm__ volatile(
    378e:	f384 8811 	msr	BASEPRI, r4
    3792:	f3bf 8f6f 	isb	sy
}
    3796:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	z_reschedule_unlocked();
    379a:	f002 b99d 	b.w	5ad8 <z_reschedule_unlocked>
    379e:	bf00      	nop
    37a0:	2000084c 	.word	0x2000084c

000037a4 <ready_thread>:
{
    37a4:	b470      	push	{r4, r5, r6}
	if (!z_is_thread_queued(thread) && z_is_thread_ready(thread)) {
    37a6:	f990 200d 	ldrsb.w	r2, [r0, #13]
	return z_is_thread_state_set(thread, _THREAD_QUEUED);
    37aa:	7b43      	ldrb	r3, [r0, #13]
    37ac:	2a00      	cmp	r2, #0
    37ae:	db29      	blt.n	3804 <ready_thread+0x60>
	return !((z_is_thread_prevented_from_running(thread)) != 0U ||
    37b0:	06db      	lsls	r3, r3, #27
    37b2:	d127      	bne.n	3804 <ready_thread+0x60>
    37b4:	6983      	ldr	r3, [r0, #24]
    37b6:	bb2b      	cbnz	r3, 3804 <ready_thread+0x60>
	return list->head == list;
    37b8:	4a13      	ldr	r2, [pc, #76]	; (3808 <ready_thread+0x64>)
	return sys_dlist_is_empty(list) ? NULL : list->head;
    37ba:	f102 012c 	add.w	r1, r2, #44	; 0x2c
    37be:	e9d2 340b 	ldrd	r3, r4, [r2, #44]	; 0x2c
    37c2:	428b      	cmp	r3, r1
    37c4:	d018      	beq.n	37f8 <ready_thread+0x54>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    37c6:	b1bb      	cbz	r3, 37f8 <ready_thread+0x54>
	if (thread_1->base.prio < thread_2->base.prio) {
    37c8:	f990 500e 	ldrsb.w	r5, [r0, #14]
    37cc:	f993 600e 	ldrsb.w	r6, [r3, #14]
    37d0:	42ae      	cmp	r6, r5
    37d2:	dd0c      	ble.n	37ee <ready_thread+0x4a>
	node->prev = successor->prev;
    37d4:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
    37d6:	e9c0 3200 	strd	r3, r2, [r0]
	successor->prev->next = node;
    37da:	6010      	str	r0, [r2, #0]
	successor->prev = node;
    37dc:	6058      	str	r0, [r3, #4]
	thread->base.thread_state |= states;
    37de:	7b43      	ldrb	r3, [r0, #13]
    37e0:	f063 037f 	orn	r3, r3, #127	; 0x7f
    37e4:	7343      	strb	r3, [r0, #13]
}
    37e6:	bc70      	pop	{r4, r5, r6}
		update_cache(0);
    37e8:	2000      	movs	r0, #0
    37ea:	f7ff bf97 	b.w	371c <update_cache>
	return (node == list->tail) ? NULL : node->next;
    37ee:	429c      	cmp	r4, r3
    37f0:	d002      	beq.n	37f8 <ready_thread+0x54>
    37f2:	681b      	ldr	r3, [r3, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    37f4:	2b00      	cmp	r3, #0
    37f6:	d1e9      	bne.n	37cc <ready_thread+0x28>
	node->prev = list->tail;
    37f8:	e9c0 1400 	strd	r1, r4, [r0]
	list->tail->next = node;
    37fc:	6b13      	ldr	r3, [r2, #48]	; 0x30
    37fe:	6018      	str	r0, [r3, #0]
	list->tail = node;
    3800:	6310      	str	r0, [r2, #48]	; 0x30
}
    3802:	e7ec      	b.n	37de <ready_thread+0x3a>
}
    3804:	bc70      	pop	{r4, r5, r6}
    3806:	4770      	bx	lr
    3808:	2000084c 	.word	0x2000084c

0000380c <z_sched_start>:
{
    380c:	b510      	push	{r4, lr}
	__asm__ volatile(
    380e:	f04f 0220 	mov.w	r2, #32
    3812:	f3ef 8411 	mrs	r4, BASEPRI
    3816:	f382 8811 	msr	BASEPRI, r2
    381a:	f3bf 8f6f 	isb	sy
	if (z_has_thread_started(thread)) {
    381e:	7b42      	ldrb	r2, [r0, #13]
    3820:	0751      	lsls	r1, r2, #29
    3822:	d404      	bmi.n	382e <z_sched_start+0x22>
	__asm__ volatile(
    3824:	f384 8811 	msr	BASEPRI, r4
    3828:	f3bf 8f6f 	isb	sy
}
    382c:	bd10      	pop	{r4, pc}
	thread->base.thread_state &= ~_THREAD_PRESTART;
    382e:	f022 0204 	bic.w	r2, r2, #4
    3832:	7342      	strb	r2, [r0, #13]
	ready_thread(thread);
    3834:	f7ff ffb6 	bl	37a4 <ready_thread>
	z_reschedule(&sched_spinlock, key);
    3838:	4621      	mov	r1, r4
}
    383a:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	z_reschedule(&sched_spinlock, key);
    383e:	4801      	ldr	r0, [pc, #4]	; (3844 <z_sched_start+0x38>)
    3840:	f7ff bf30 	b.w	36a4 <z_reschedule>
    3844:	200008af 	.word	0x200008af

00003848 <move_thread_to_end_of_prio_q>:
{
    3848:	b570      	push	{r4, r5, r6, lr}
	if (z_is_thread_queued(thread)) {
    384a:	f990 300d 	ldrsb.w	r3, [r0, #13]
{
    384e:	4601      	mov	r1, r0
	if (z_is_thread_queued(thread)) {
    3850:	2b00      	cmp	r3, #0
    3852:	da02      	bge.n	385a <move_thread_to_end_of_prio_q+0x12>
		_priq_run_remove(&_kernel.ready_q.runq, thread);
    3854:	4816      	ldr	r0, [pc, #88]	; (38b0 <move_thread_to_end_of_prio_q+0x68>)
    3856:	f7ff ff4b 	bl	36f0 <z_priq_dumb_remove>
	return list->head == list;
    385a:	4a16      	ldr	r2, [pc, #88]	; (38b4 <move_thread_to_end_of_prio_q+0x6c>)
	return sys_dlist_is_empty(list) ? NULL : list->head;
    385c:	f102 002c 	add.w	r0, r2, #44	; 0x2c
    3860:	e9d2 340b 	ldrd	r3, r4, [r2, #44]	; 0x2c
    3864:	4283      	cmp	r3, r0
    3866:	d01c      	beq.n	38a2 <move_thread_to_end_of_prio_q+0x5a>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    3868:	b1db      	cbz	r3, 38a2 <move_thread_to_end_of_prio_q+0x5a>
	if (thread_1->base.prio < thread_2->base.prio) {
    386a:	f991 500e 	ldrsb.w	r5, [r1, #14]
    386e:	f993 600e 	ldrsb.w	r6, [r3, #14]
    3872:	42ae      	cmp	r6, r5
    3874:	dd10      	ble.n	3898 <move_thread_to_end_of_prio_q+0x50>
	node->prev = successor->prev;
    3876:	6858      	ldr	r0, [r3, #4]
	node->next = successor;
    3878:	e9c1 3000 	strd	r3, r0, [r1]
	successor->prev->next = node;
    387c:	6001      	str	r1, [r0, #0]
	successor->prev = node;
    387e:	6059      	str	r1, [r3, #4]
	thread->base.thread_state |= states;
    3880:	7b4b      	ldrb	r3, [r1, #13]
	update_cache(thread == _current);
    3882:	6890      	ldr	r0, [r2, #8]
    3884:	f063 037f 	orn	r3, r3, #127	; 0x7f
    3888:	734b      	strb	r3, [r1, #13]
    388a:	1a43      	subs	r3, r0, r1
    388c:	4258      	negs	r0, r3
    388e:	4158      	adcs	r0, r3
}
    3890:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	update_cache(thread == _current);
    3894:	f7ff bf42 	b.w	371c <update_cache>
	return (node == list->tail) ? NULL : node->next;
    3898:	429c      	cmp	r4, r3
    389a:	d002      	beq.n	38a2 <move_thread_to_end_of_prio_q+0x5a>
    389c:	681b      	ldr	r3, [r3, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    389e:	2b00      	cmp	r3, #0
    38a0:	d1e5      	bne.n	386e <move_thread_to_end_of_prio_q+0x26>
	node->prev = list->tail;
    38a2:	e9c1 0400 	strd	r0, r4, [r1]
	list->tail->next = node;
    38a6:	6b13      	ldr	r3, [r2, #48]	; 0x30
    38a8:	6019      	str	r1, [r3, #0]
	list->tail = node;
    38aa:	6311      	str	r1, [r2, #48]	; 0x30
}
    38ac:	e7e8      	b.n	3880 <move_thread_to_end_of_prio_q+0x38>
    38ae:	bf00      	nop
    38b0:	20000878 	.word	0x20000878
    38b4:	2000084c 	.word	0x2000084c

000038b8 <z_time_slice>:
{
    38b8:	4601      	mov	r1, r0
    38ba:	b570      	push	{r4, r5, r6, lr}
	__asm__ volatile(
    38bc:	f04f 0320 	mov.w	r3, #32
    38c0:	f3ef 8411 	mrs	r4, BASEPRI
    38c4:	f383 8811 	msr	BASEPRI, r3
    38c8:	f3bf 8f6f 	isb	sy
	if (pending_current == _current) {
    38cc:	4b16      	ldr	r3, [pc, #88]	; (3928 <z_time_slice+0x70>)
    38ce:	4a17      	ldr	r2, [pc, #92]	; (392c <z_time_slice+0x74>)
    38d0:	6898      	ldr	r0, [r3, #8]
    38d2:	6815      	ldr	r5, [r2, #0]
    38d4:	42a8      	cmp	r0, r5
    38d6:	461d      	mov	r5, r3
    38d8:	d106      	bne.n	38e8 <z_time_slice+0x30>
			z_reset_time_slice();
    38da:	f7ff fea1 	bl	3620 <z_reset_time_slice>
	__asm__ volatile(
    38de:	f384 8811 	msr	BASEPRI, r4
    38e2:	f3bf 8f6f 	isb	sy
}
    38e6:	bd70      	pop	{r4, r5, r6, pc}
	pending_current = NULL;
    38e8:	2600      	movs	r6, #0
    38ea:	6016      	str	r6, [r2, #0]
	if (slice_time && sliceable(_current)) {
    38ec:	4a10      	ldr	r2, [pc, #64]	; (3930 <z_time_slice+0x78>)
    38ee:	6812      	ldr	r2, [r2, #0]
    38f0:	b1ba      	cbz	r2, 3922 <z_time_slice+0x6a>
		&& !z_is_idle_thread_object(thread);
    38f2:	89c2      	ldrh	r2, [r0, #14]
    38f4:	2a7f      	cmp	r2, #127	; 0x7f
    38f6:	d814      	bhi.n	3922 <z_time_slice+0x6a>
		&& !z_is_thread_prevented_from_running(thread)
    38f8:	7b42      	ldrb	r2, [r0, #13]
    38fa:	06d2      	lsls	r2, r2, #27
    38fc:	d111      	bne.n	3922 <z_time_slice+0x6a>
		&& !z_is_prio_higher(thread->base.prio, slice_max_prio)
    38fe:	4a0d      	ldr	r2, [pc, #52]	; (3934 <z_time_slice+0x7c>)
    3900:	f990 600e 	ldrsb.w	r6, [r0, #14]
    3904:	6812      	ldr	r2, [r2, #0]
    3906:	4296      	cmp	r6, r2
    3908:	db0b      	blt.n	3922 <z_time_slice+0x6a>
		&& !z_is_idle_thread_object(thread);
    390a:	4a0b      	ldr	r2, [pc, #44]	; (3938 <z_time_slice+0x80>)
    390c:	4290      	cmp	r0, r2
    390e:	d008      	beq.n	3922 <z_time_slice+0x6a>
		if (ticks >= _current_cpu->slice_ticks) {
    3910:	695a      	ldr	r2, [r3, #20]
    3912:	428a      	cmp	r2, r1
    3914:	dc02      	bgt.n	391c <z_time_slice+0x64>
			move_thread_to_end_of_prio_q(_current);
    3916:	f7ff ff97 	bl	3848 <move_thread_to_end_of_prio_q>
    391a:	e7de      	b.n	38da <z_time_slice+0x22>
			_current_cpu->slice_ticks -= ticks;
    391c:	1a52      	subs	r2, r2, r1
    391e:	615a      	str	r2, [r3, #20]
    3920:	e7dd      	b.n	38de <z_time_slice+0x26>
		_current_cpu->slice_ticks = 0;
    3922:	2300      	movs	r3, #0
    3924:	616b      	str	r3, [r5, #20]
    3926:	e7da      	b.n	38de <z_time_slice+0x26>
    3928:	2000084c 	.word	0x2000084c
    392c:	20000880 	.word	0x20000880
    3930:	20000888 	.word	0x20000888
    3934:	20000884 	.word	0x20000884
    3938:	20000128 	.word	0x20000128

0000393c <z_impl_k_thread_suspend>:
{
    393c:	b570      	push	{r4, r5, r6, lr}
    393e:	4604      	mov	r4, r0
	z_add_timeout(&th->base.timeout, z_thread_timeout, ticks);
}

static inline int z_abort_thread_timeout(struct k_thread *thread)
{
	return z_abort_timeout(&thread->base.timeout);
    3940:	3018      	adds	r0, #24
    3942:	f002 f96d 	bl	5c20 <z_abort_timeout>
	__asm__ volatile(
    3946:	f04f 0320 	mov.w	r3, #32
    394a:	f3ef 8611 	mrs	r6, BASEPRI
    394e:	f383 8811 	msr	BASEPRI, r3
    3952:	f3bf 8f6f 	isb	sy
		if (z_is_thread_queued(thread)) {
    3956:	f994 300d 	ldrsb.w	r3, [r4, #13]
    395a:	2b00      	cmp	r3, #0
    395c:	da07      	bge.n	396e <z_impl_k_thread_suspend+0x32>
			_priq_run_remove(&_kernel.ready_q.runq, thread);
    395e:	4621      	mov	r1, r4
    3960:	480e      	ldr	r0, [pc, #56]	; (399c <z_impl_k_thread_suspend+0x60>)
    3962:	f7ff fec5 	bl	36f0 <z_priq_dumb_remove>
	thread->base.thread_state &= ~states;
    3966:	7b63      	ldrb	r3, [r4, #13]
    3968:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    396c:	7363      	strb	r3, [r4, #13]
		update_cache(thread == _current);
    396e:	4d0c      	ldr	r5, [pc, #48]	; (39a0 <z_impl_k_thread_suspend+0x64>)
	thread->base.thread_state |= _THREAD_SUSPENDED;
    3970:	7b63      	ldrb	r3, [r4, #13]
    3972:	68a8      	ldr	r0, [r5, #8]
    3974:	f043 0310 	orr.w	r3, r3, #16
    3978:	7363      	strb	r3, [r4, #13]
    397a:	1b03      	subs	r3, r0, r4
    397c:	4258      	negs	r0, r3
    397e:	4158      	adcs	r0, r3
    3980:	f7ff fecc 	bl	371c <update_cache>
	__asm__ volatile(
    3984:	f386 8811 	msr	BASEPRI, r6
    3988:	f3bf 8f6f 	isb	sy
	if (thread == _current) {
    398c:	68ab      	ldr	r3, [r5, #8]
    398e:	42a3      	cmp	r3, r4
    3990:	d103      	bne.n	399a <z_impl_k_thread_suspend+0x5e>
}
    3992:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		z_reschedule_unlocked();
    3996:	f002 b89f 	b.w	5ad8 <z_reschedule_unlocked>
}
    399a:	bd70      	pop	{r4, r5, r6, pc}
    399c:	20000878 	.word	0x20000878
    39a0:	2000084c 	.word	0x2000084c

000039a4 <z_thread_single_abort>:
{
    39a4:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    39a8:	4604      	mov	r4, r0
	__asm__ volatile(
    39aa:	f04f 0320 	mov.w	r3, #32
    39ae:	f3ef 8211 	mrs	r2, BASEPRI
    39b2:	f383 8811 	msr	BASEPRI, r3
    39b6:	f3bf 8f6f 	isb	sy
	if ((thread->base.thread_state &
    39ba:	7b43      	ldrb	r3, [r0, #13]
    39bc:	f013 0f28 	tst.w	r3, #40	; 0x28
    39c0:	d005      	beq.n	39ce <z_thread_single_abort+0x2a>
	__asm__ volatile(
    39c2:	f382 8811 	msr	BASEPRI, r2
    39c6:	f3bf 8f6f 	isb	sy
}
    39ca:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	thread->base.thread_state |= _THREAD_ABORTING;
    39ce:	f043 0320 	orr.w	r3, r3, #32
    39d2:	7343      	strb	r3, [r0, #13]
    39d4:	f382 8811 	msr	BASEPRI, r2
    39d8:	f3bf 8f6f 	isb	sy
    39dc:	3018      	adds	r0, #24
    39de:	f002 f91f 	bl	5c20 <z_abort_timeout>
	__asm__ volatile(
    39e2:	f04f 0320 	mov.w	r3, #32
    39e6:	f3ef 8611 	mrs	r6, BASEPRI
    39ea:	f383 8811 	msr	BASEPRI, r3
    39ee:	f3bf 8f6f 	isb	sy
	return !((z_is_thread_prevented_from_running(thread)) != 0U ||
    39f2:	7b63      	ldrb	r3, [r4, #13]
    39f4:	06d8      	lsls	r0, r3, #27
    39f6:	d116      	bne.n	3a26 <z_thread_single_abort+0x82>
		if (z_is_thread_ready(thread)) {
    39f8:	69a2      	ldr	r2, [r4, #24]
    39fa:	b9a2      	cbnz	r2, 3a26 <z_thread_single_abort+0x82>
			if (z_is_thread_queued(thread)) {
    39fc:	0619      	lsls	r1, r3, #24
    39fe:	d507      	bpl.n	3a10 <z_thread_single_abort+0x6c>
				_priq_run_remove(&_kernel.ready_q.runq,
    3a00:	4621      	mov	r1, r4
    3a02:	4826      	ldr	r0, [pc, #152]	; (3a9c <z_thread_single_abort+0xf8>)
    3a04:	f7ff fe74 	bl	36f0 <z_priq_dumb_remove>
	thread->base.thread_state &= ~states;
    3a08:	7b63      	ldrb	r3, [r4, #13]
    3a0a:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    3a0e:	7363      	strb	r3, [r4, #13]
			update_cache(thread == _current);
    3a10:	4b23      	ldr	r3, [pc, #140]	; (3aa0 <z_thread_single_abort+0xfc>)
    3a12:	6898      	ldr	r0, [r3, #8]
    3a14:	1b02      	subs	r2, r0, r4
    3a16:	4250      	negs	r0, r2
    3a18:	4150      	adcs	r0, r2
    3a1a:	f7ff fe7f 	bl	371c <update_cache>
			waiter->base.pended_on = NULL;
    3a1e:	2700      	movs	r7, #0
	sys_dlist_init(&w->waitq);
}

static inline struct k_thread *z_waitq_head(_wait_q_t *w)
{
	return (struct k_thread *)sys_dlist_peek_head(&w->waitq);
    3a20:	f104 0830 	add.w	r8, r4, #48	; 0x30
    3a24:	e01d      	b.n	3a62 <z_thread_single_abort+0xbe>
			if (z_is_thread_pending(thread)) {
    3a26:	079b      	lsls	r3, r3, #30
    3a28:	d5f9      	bpl.n	3a1e <z_thread_single_abort+0x7a>
				_priq_wait_remove(&pended_on(thread)->waitq,
    3a2a:	4621      	mov	r1, r4
    3a2c:	68a0      	ldr	r0, [r4, #8]
    3a2e:	f7ff fe5f 	bl	36f0 <z_priq_dumb_remove>
	thread->base.thread_state &= ~_THREAD_PENDING;
    3a32:	7b63      	ldrb	r3, [r4, #13]
    3a34:	f023 0302 	bic.w	r3, r3, #2
    3a38:	7363      	strb	r3, [r4, #13]
				thread->base.pended_on = NULL;
    3a3a:	2300      	movs	r3, #0
    3a3c:	60a3      	str	r3, [r4, #8]
    3a3e:	e7ee      	b.n	3a1e <z_thread_single_abort+0x7a>
    3a40:	f105 0018 	add.w	r0, r5, #24
    3a44:	f002 f8ec 	bl	5c20 <z_abort_timeout>
			_priq_wait_remove(&pended_on(waiter)->waitq, waiter);
    3a48:	68a8      	ldr	r0, [r5, #8]
    3a4a:	4629      	mov	r1, r5
    3a4c:	f7ff fe50 	bl	36f0 <z_priq_dumb_remove>
    3a50:	7b6b      	ldrb	r3, [r5, #13]
			ready_thread(waiter);
    3a52:	4628      	mov	r0, r5
    3a54:	f023 0302 	bic.w	r3, r3, #2
    3a58:	736b      	strb	r3, [r5, #13]
			waiter->base.pended_on = NULL;
    3a5a:	60af      	str	r7, [r5, #8]
    3a5c:	67ef      	str	r7, [r5, #124]	; 0x7c
			ready_thread(waiter);
    3a5e:	f7ff fea1 	bl	37a4 <ready_thread>
	return list->head == list;
    3a62:	6b25      	ldr	r5, [r4, #48]	; 0x30
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3a64:	4545      	cmp	r5, r8
    3a66:	d001      	beq.n	3a6c <z_thread_single_abort+0xc8>
		while ((waiter = z_waitq_head(&thread->base.join_waiters)) !=
    3a68:	2d00      	cmp	r5, #0
    3a6a:	d1e9      	bne.n	3a40 <z_thread_single_abort+0x9c>
		if (z_is_idle_thread_object(_current)) {
    3a6c:	4b0c      	ldr	r3, [pc, #48]	; (3aa0 <z_thread_single_abort+0xfc>)
    3a6e:	689a      	ldr	r2, [r3, #8]
    3a70:	4b0c      	ldr	r3, [pc, #48]	; (3aa4 <z_thread_single_abort+0x100>)
    3a72:	429a      	cmp	r2, r3
    3a74:	d102      	bne.n	3a7c <z_thread_single_abort+0xd8>
			update_cache(1);
    3a76:	2001      	movs	r0, #1
    3a78:	f7ff fe50 	bl	371c <update_cache>
		thread->base.thread_state |= _THREAD_DEAD;
    3a7c:	7b63      	ldrb	r3, [r4, #13]
    3a7e:	f043 0308 	orr.w	r3, r3, #8
    3a82:	7363      	strb	r3, [r4, #13]
		fn_abort = thread->fn_abort;
    3a84:	6e23      	ldr	r3, [r4, #96]	; 0x60
	__asm__ volatile(
    3a86:	f386 8811 	msr	BASEPRI, r6
    3a8a:	f3bf 8f6f 	isb	sy
	if (fn_abort != NULL) {
    3a8e:	2b00      	cmp	r3, #0
    3a90:	d09b      	beq.n	39ca <z_thread_single_abort+0x26>
		fn_abort(thread);
    3a92:	4620      	mov	r0, r4
}
    3a94:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
		fn_abort(thread);
    3a98:	4718      	bx	r3
    3a9a:	bf00      	nop
    3a9c:	20000878 	.word	0x20000878
    3aa0:	2000084c 	.word	0x2000084c
    3aa4:	20000128 	.word	0x20000128

00003aa8 <unready_thread>:
{
    3aa8:	b508      	push	{r3, lr}
	if (z_is_thread_queued(thread)) {
    3aaa:	f990 300d 	ldrsb.w	r3, [r0, #13]
{
    3aae:	4601      	mov	r1, r0
	if (z_is_thread_queued(thread)) {
    3ab0:	2b00      	cmp	r3, #0
    3ab2:	da06      	bge.n	3ac2 <unready_thread+0x1a>
		_priq_run_remove(&_kernel.ready_q.runq, thread);
    3ab4:	4807      	ldr	r0, [pc, #28]	; (3ad4 <unready_thread+0x2c>)
    3ab6:	f7ff fe1b 	bl	36f0 <z_priq_dumb_remove>
	thread->base.thread_state &= ~states;
    3aba:	7b4b      	ldrb	r3, [r1, #13]
    3abc:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    3ac0:	734b      	strb	r3, [r1, #13]
	update_cache(thread == _current);
    3ac2:	4b05      	ldr	r3, [pc, #20]	; (3ad8 <unready_thread+0x30>)
    3ac4:	6898      	ldr	r0, [r3, #8]
    3ac6:	1a43      	subs	r3, r0, r1
    3ac8:	4258      	negs	r0, r3
    3aca:	4158      	adcs	r0, r3
}
    3acc:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	update_cache(thread == _current);
    3ad0:	f7ff be24 	b.w	371c <update_cache>
    3ad4:	20000878 	.word	0x20000878
    3ad8:	2000084c 	.word	0x2000084c

00003adc <pend>:
{
    3adc:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    3ae0:	4606      	mov	r6, r0
    3ae2:	4614      	mov	r4, r2
    3ae4:	461d      	mov	r5, r3
	__asm__ volatile(
    3ae6:	f04f 0320 	mov.w	r3, #32
    3aea:	f3ef 8711 	mrs	r7, BASEPRI
    3aee:	f383 8811 	msr	BASEPRI, r3
    3af2:	f3bf 8f6f 	isb	sy
		add_to_waitq_locked(thread, wait_q);
    3af6:	f002 f83b 	bl	5b70 <add_to_waitq_locked>
	__asm__ volatile(
    3afa:	f387 8811 	msr	BASEPRI, r7
    3afe:	f3bf 8f6f 	isb	sy
	if (!K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    3b02:	1c6b      	adds	r3, r5, #1
    3b04:	bf08      	it	eq
    3b06:	f1b4 3fff 	cmpeq.w	r4, #4294967295	; 0xffffffff
    3b0a:	d008      	beq.n	3b1e <pend+0x42>
	z_add_timeout(&th->base.timeout, z_thread_timeout, ticks);
    3b0c:	4622      	mov	r2, r4
    3b0e:	462b      	mov	r3, r5
    3b10:	f106 0018 	add.w	r0, r6, #24
    3b14:	4903      	ldr	r1, [pc, #12]	; (3b24 <pend+0x48>)
}
    3b16:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
    3b1a:	f000 ba69 	b.w	3ff0 <z_add_timeout>
    3b1e:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    3b22:	bf00      	nop
    3b24:	00005b31 	.word	0x00005b31

00003b28 <z_pend_curr>:
{
    3b28:	b510      	push	{r4, lr}
    3b2a:	460c      	mov	r4, r1
	pending_current = _current;
    3b2c:	4b06      	ldr	r3, [pc, #24]	; (3b48 <z_pend_curr+0x20>)
{
    3b2e:	4611      	mov	r1, r2
	pending_current = _current;
    3b30:	6898      	ldr	r0, [r3, #8]
    3b32:	4b06      	ldr	r3, [pc, #24]	; (3b4c <z_pend_curr+0x24>)
    3b34:	6018      	str	r0, [r3, #0]
	pend(_current, wait_q, timeout);
    3b36:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
    3b3a:	f7ff ffcf 	bl	3adc <pend>
    3b3e:	4620      	mov	r0, r4
}
    3b40:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    3b44:	f7fe bac4 	b.w	20d0 <arch_swap>
    3b48:	2000084c 	.word	0x2000084c
    3b4c:	20000880 	.word	0x20000880

00003b50 <z_tick_sleep.part.0>:
	z_impl_k_yield();
}
#include <syscalls/k_yield_mrsh.c>
#endif

static int32_t z_tick_sleep(k_ticks_t ticks)
    3b50:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
    3b52:	4605      	mov	r5, r0
    3b54:	9101      	str	r1, [sp, #4]
		return 0;
	}

	k_timeout_t timeout = Z_TIMEOUT_TICKS(ticks);

	expected_wakeup_ticks = ticks + z_tick_get_32();
    3b56:	f002 f8a4 	bl	5ca2 <z_tick_get_32>
    3b5a:	4604      	mov	r4, r0
	__asm__ volatile(
    3b5c:	f04f 0220 	mov.w	r2, #32
    3b60:	f3ef 8711 	mrs	r7, BASEPRI
    3b64:	f382 8811 	msr	BASEPRI, r2
    3b68:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&sched_spinlock);

#if defined(CONFIG_TIMESLICING) && defined(CONFIG_SWAP_NONATOMIC)
	pending_current = _current;
    3b6c:	4e12      	ldr	r6, [pc, #72]	; (3bb8 <z_tick_sleep.part.0+0x68>)
    3b6e:	4a13      	ldr	r2, [pc, #76]	; (3bbc <z_tick_sleep.part.0+0x6c>)
    3b70:	68b0      	ldr	r0, [r6, #8]
    3b72:	6010      	str	r0, [r2, #0]
#endif
	unready_thread(_current);
    3b74:	f7ff ff98 	bl	3aa8 <unready_thread>
	z_add_thread_timeout(_current, timeout);
    3b78:	68b0      	ldr	r0, [r6, #8]
    3b7a:	4911      	ldr	r1, [pc, #68]	; (3bc0 <z_tick_sleep.part.0+0x70>)
    3b7c:	462a      	mov	r2, r5
    3b7e:	9b01      	ldr	r3, [sp, #4]
    3b80:	3018      	adds	r0, #24
    3b82:	f000 fa35 	bl	3ff0 <z_add_timeout>
	z_mark_thread_as_suspended(_current);
    3b86:	68b2      	ldr	r2, [r6, #8]
    3b88:	4638      	mov	r0, r7
	thread->base.thread_state |= _THREAD_SUSPENDED;
    3b8a:	7b53      	ldrb	r3, [r2, #13]
    3b8c:	f043 0310 	orr.w	r3, r3, #16
    3b90:	7353      	strb	r3, [r2, #13]
    3b92:	f7fe fa9d 	bl	20d0 <arch_swap>
	expected_wakeup_ticks = ticks + z_tick_get_32();
    3b96:	1960      	adds	r0, r4, r5

	(void)z_swap(&sched_spinlock, key);

	__ASSERT(!z_is_thread_state_set(_current, _THREAD_SUSPENDED), "");

	ticks = (k_ticks_t)expected_wakeup_ticks - z_tick_get_32();
    3b98:	4604      	mov	r4, r0
    3b9a:	f002 f882 	bl	5ca2 <z_tick_get_32>
    3b9e:	2500      	movs	r5, #0
    3ba0:	1a24      	subs	r4, r4, r0
    3ba2:	f165 0500 	sbc.w	r5, r5, #0
    3ba6:	2c00      	cmp	r4, #0
    3ba8:	f175 0300 	sbcs.w	r3, r5, #0
    3bac:	bfb8      	it	lt
    3bae:	2400      	movlt	r4, #0
		return ticks;
	}
#endif

	return 0;
}
    3bb0:	4620      	mov	r0, r4
    3bb2:	b003      	add	sp, #12
    3bb4:	bdf0      	pop	{r4, r5, r6, r7, pc}
    3bb6:	bf00      	nop
    3bb8:	2000084c 	.word	0x2000084c
    3bbc:	20000880 	.word	0x20000880
    3bc0:	00005b31 	.word	0x00005b31

00003bc4 <z_set_prio>:
{
    3bc4:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    3bc6:	4604      	mov	r4, r0
    3bc8:	f04f 0320 	mov.w	r3, #32
    3bcc:	f3ef 8711 	mrs	r7, BASEPRI
    3bd0:	f383 8811 	msr	BASEPRI, r3
    3bd4:	f3bf 8f6f 	isb	sy
	return !((z_is_thread_prevented_from_running(thread)) != 0U ||
    3bd8:	7b43      	ldrb	r3, [r0, #13]
    3bda:	b24e      	sxtb	r6, r1
    3bdc:	06db      	lsls	r3, r3, #27
    3bde:	d12c      	bne.n	3c3a <z_set_prio+0x76>
		if (need_sched) {
    3be0:	6983      	ldr	r3, [r0, #24]
    3be2:	bb53      	cbnz	r3, 3c3a <z_set_prio+0x76>
				_priq_run_remove(&_kernel.ready_q.runq, thread);
    3be4:	4d16      	ldr	r5, [pc, #88]	; (3c40 <z_set_prio+0x7c>)
    3be6:	4621      	mov	r1, r4
    3be8:	f105 002c 	add.w	r0, r5, #44	; 0x2c
    3bec:	f7ff fd80 	bl	36f0 <z_priq_dumb_remove>
	return list->head == list;
    3bf0:	6aeb      	ldr	r3, [r5, #44]	; 0x2c
    3bf2:	462a      	mov	r2, r5
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3bf4:	4283      	cmp	r3, r0
				thread->base.prio = prio;
    3bf6:	73a6      	strb	r6, [r4, #14]
    3bf8:	d018      	beq.n	3c2c <z_set_prio+0x68>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    3bfa:	b1bb      	cbz	r3, 3c2c <z_set_prio+0x68>
    3bfc:	6b29      	ldr	r1, [r5, #48]	; 0x30
	if (thread_1->base.prio < thread_2->base.prio) {
    3bfe:	f993 500e 	ldrsb.w	r5, [r3, #14]
    3c02:	42b5      	cmp	r5, r6
    3c04:	dd0d      	ble.n	3c22 <z_set_prio+0x5e>
	node->prev = successor->prev;
    3c06:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
    3c08:	e9c4 3200 	strd	r3, r2, [r4]
	successor->prev->next = node;
    3c0c:	6014      	str	r4, [r2, #0]
	successor->prev = node;
    3c0e:	605c      	str	r4, [r3, #4]
			update_cache(1);
    3c10:	2001      	movs	r0, #1
    3c12:	f7ff fd83 	bl	371c <update_cache>
    3c16:	2001      	movs	r0, #1
	__asm__ volatile(
    3c18:	f387 8811 	msr	BASEPRI, r7
    3c1c:	f3bf 8f6f 	isb	sy
}
    3c20:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	return (node == list->tail) ? NULL : node->next;
    3c22:	428b      	cmp	r3, r1
    3c24:	d002      	beq.n	3c2c <z_set_prio+0x68>
    3c26:	681b      	ldr	r3, [r3, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    3c28:	2b00      	cmp	r3, #0
    3c2a:	d1e8      	bne.n	3bfe <z_set_prio+0x3a>
	node->prev = list->tail;
    3c2c:	6b13      	ldr	r3, [r2, #48]	; 0x30
	node->next = list;
    3c2e:	6020      	str	r0, [r4, #0]
	node->prev = list->tail;
    3c30:	6063      	str	r3, [r4, #4]
	list->tail->next = node;
    3c32:	6b13      	ldr	r3, [r2, #48]	; 0x30
    3c34:	601c      	str	r4, [r3, #0]
	list->tail = node;
    3c36:	6314      	str	r4, [r2, #48]	; 0x30
}
    3c38:	e7ea      	b.n	3c10 <z_set_prio+0x4c>
			thread->base.prio = prio;
    3c3a:	2000      	movs	r0, #0
    3c3c:	73a6      	strb	r6, [r4, #14]
    3c3e:	e7eb      	b.n	3c18 <z_set_prio+0x54>
    3c40:	2000084c 	.word	0x2000084c

00003c44 <z_sched_init>:
	k_sched_time_slice_set(CONFIG_TIMESLICE_SIZE,
    3c44:	2100      	movs	r1, #0
	list->head = (sys_dnode_t *)list;
    3c46:	4b04      	ldr	r3, [pc, #16]	; (3c58 <z_sched_init+0x14>)
    3c48:	4608      	mov	r0, r1
    3c4a:	f103 022c 	add.w	r2, r3, #44	; 0x2c
	list->tail = (sys_dnode_t *)list;
    3c4e:	e9c3 220b 	strd	r2, r2, [r3, #44]	; 0x2c
    3c52:	f7ff bcfb 	b.w	364c <k_sched_time_slice_set>
    3c56:	bf00      	nop
    3c58:	2000084c 	.word	0x2000084c

00003c5c <z_impl_k_yield>:
{
    3c5c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	if (!z_is_idle_thread_object(_current)) {
    3c5e:	4c23      	ldr	r4, [pc, #140]	; (3cec <z_impl_k_yield+0x90>)
    3c60:	4b23      	ldr	r3, [pc, #140]	; (3cf0 <z_impl_k_yield+0x94>)
    3c62:	68a2      	ldr	r2, [r4, #8]
    3c64:	429a      	cmp	r2, r3
    3c66:	d028      	beq.n	3cba <z_impl_k_yield+0x5e>
	__asm__ volatile(
    3c68:	f04f 0320 	mov.w	r3, #32
    3c6c:	f3ef 8511 	mrs	r5, BASEPRI
    3c70:	f383 8811 	msr	BASEPRI, r3
    3c74:	f3bf 8f6f 	isb	sy
				_priq_run_remove(&_kernel.ready_q.runq,
    3c78:	f104 002c 	add.w	r0, r4, #44	; 0x2c
    3c7c:	68a1      	ldr	r1, [r4, #8]
    3c7e:	f7ff fd37 	bl	36f0 <z_priq_dumb_remove>
	return list->head == list;
    3c82:	6ae2      	ldr	r2, [r4, #44]	; 0x2c
			_priq_run_add(&_kernel.ready_q.runq, _current);
    3c84:	68a3      	ldr	r3, [r4, #8]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3c86:	4282      	cmp	r2, r0
    3c88:	d028      	beq.n	3cdc <z_impl_k_yield+0x80>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    3c8a:	b33a      	cbz	r2, 3cdc <z_impl_k_yield+0x80>
    3c8c:	6b26      	ldr	r6, [r4, #48]	; 0x30
	if (thread_1->base.prio < thread_2->base.prio) {
    3c8e:	f993 100e 	ldrsb.w	r1, [r3, #14]
    3c92:	f992 700e 	ldrsb.w	r7, [r2, #14]
    3c96:	428f      	cmp	r7, r1
    3c98:	dd1b      	ble.n	3cd2 <z_impl_k_yield+0x76>
	node->prev = successor->prev;
    3c9a:	6851      	ldr	r1, [r2, #4]
	node->next = successor;
    3c9c:	e9c3 2100 	strd	r2, r1, [r3]
	successor->prev->next = node;
    3ca0:	600b      	str	r3, [r1, #0]
	successor->prev = node;
    3ca2:	6053      	str	r3, [r2, #4]
	thread->base.thread_state |= states;
    3ca4:	7b5a      	ldrb	r2, [r3, #13]
			update_cache(1);
    3ca6:	2001      	movs	r0, #1
    3ca8:	f062 027f 	orn	r2, r2, #127	; 0x7f
    3cac:	735a      	strb	r2, [r3, #13]
    3cae:	f7ff fd35 	bl	371c <update_cache>
	__asm__ volatile(
    3cb2:	f385 8811 	msr	BASEPRI, r5
    3cb6:	f3bf 8f6f 	isb	sy
	__asm__ volatile(
    3cba:	f04f 0320 	mov.w	r3, #32
    3cbe:	f3ef 8011 	mrs	r0, BASEPRI
    3cc2:	f383 8811 	msr	BASEPRI, r3
    3cc6:	f3bf 8f6f 	isb	sy
}
    3cca:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
    3cce:	f7fe b9ff 	b.w	20d0 <arch_swap>
	return (node == list->tail) ? NULL : node->next;
    3cd2:	4296      	cmp	r6, r2
    3cd4:	d002      	beq.n	3cdc <z_impl_k_yield+0x80>
    3cd6:	6812      	ldr	r2, [r2, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    3cd8:	2a00      	cmp	r2, #0
    3cda:	d1da      	bne.n	3c92 <z_impl_k_yield+0x36>
	node->prev = list->tail;
    3cdc:	6b22      	ldr	r2, [r4, #48]	; 0x30
	node->next = list;
    3cde:	6018      	str	r0, [r3, #0]
	node->prev = list->tail;
    3ce0:	605a      	str	r2, [r3, #4]
	list->tail->next = node;
    3ce2:	6b22      	ldr	r2, [r4, #48]	; 0x30
    3ce4:	6013      	str	r3, [r2, #0]
	list->tail = node;
    3ce6:	6323      	str	r3, [r4, #48]	; 0x30
}
    3ce8:	e7dc      	b.n	3ca4 <z_impl_k_yield+0x48>
    3cea:	bf00      	nop
    3cec:	2000084c 	.word	0x2000084c
    3cf0:	20000128 	.word	0x20000128

00003cf4 <z_impl_k_sleep>:

	__ASSERT(!arch_is_in_isr(), "");
	sys_trace_void(SYS_TRACE_ID_SLEEP);

	/* in case of K_FOREVER, we suspend */
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    3cf4:	f1b1 3fff 	cmp.w	r1, #4294967295	; 0xffffffff
    3cf8:	bf08      	it	eq
    3cfa:	f1b0 3fff 	cmpeq.w	r0, #4294967295	; 0xffffffff
{
    3cfe:	b508      	push	{r3, lr}
    3d00:	4602      	mov	r2, r0
    3d02:	460b      	mov	r3, r1
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    3d04:	d106      	bne.n	3d14 <z_impl_k_sleep+0x20>
		k_thread_suspend(_current);
    3d06:	4b0b      	ldr	r3, [pc, #44]	; (3d34 <z_impl_k_sleep+0x40>)
    3d08:	6898      	ldr	r0, [r3, #8]
	z_impl_k_thread_suspend(thread);
    3d0a:	f7ff fe17 	bl	393c <z_impl_k_thread_suspend>
		return (int32_t) K_TICKS_FOREVER;
    3d0e:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
	ticks = timeout.ticks;

	ticks = z_tick_sleep(ticks);
	sys_trace_end_call(SYS_TRACE_ID_SLEEP);
	return k_ticks_to_ms_floor64(ticks);
}
    3d12:	bd08      	pop	{r3, pc}
	if (ticks == 0) {
    3d14:	4313      	orrs	r3, r2
    3d16:	d10a      	bne.n	3d2e <z_impl_k_sleep+0x3a>
	z_impl_k_yield();
    3d18:	f7ff ffa0 	bl	3c5c <z_impl_k_yield>
		return 0;
    3d1c:	2000      	movs	r0, #0
		} else {
			return (t * to_hz + off) / from_hz;
    3d1e:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
    3d22:	fb80 2303 	smull	r2, r3, r0, r3
    3d26:	0bd0      	lsrs	r0, r2, #15
    3d28:	ea40 4043 	orr.w	r0, r0, r3, lsl #17
	return k_ticks_to_ms_floor64(ticks);
    3d2c:	e7f1      	b.n	3d12 <z_impl_k_sleep+0x1e>
    3d2e:	f7ff ff0f 	bl	3b50 <z_tick_sleep.part.0>
    3d32:	e7f4      	b.n	3d1e <z_impl_k_sleep+0x2a>
    3d34:	2000084c 	.word	0x2000084c

00003d38 <z_impl_k_current_get>:

#ifdef CONFIG_SMP
	arch_irq_unlock(k);
#endif
	return ret;
}
    3d38:	4b01      	ldr	r3, [pc, #4]	; (3d40 <z_impl_k_current_get+0x8>)
    3d3a:	6898      	ldr	r0, [r3, #8]
    3d3c:	4770      	bx	lr
    3d3e:	bf00      	nop
    3d40:	2000084c 	.word	0x2000084c

00003d44 <z_impl_k_sem_give>:
	ARG_UNUSED(sem);
#endif
}

void z_impl_k_sem_give(struct k_sem *sem)
{
    3d44:	b538      	push	{r3, r4, r5, lr}
    3d46:	4604      	mov	r4, r0
    3d48:	f04f 0320 	mov.w	r3, #32
    3d4c:	f3ef 8511 	mrs	r5, BASEPRI
    3d50:	f383 8811 	msr	BASEPRI, r3
    3d54:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&lock);
	struct k_thread *thread;

	sys_trace_semaphore_give(sem);
	thread = z_unpend_first_thread(&sem->wait_q);
    3d58:	f001 ff32 	bl	5bc0 <z_unpend_first_thread>

	if (thread != NULL) {
    3d5c:	b148      	cbz	r0, 3d72 <z_impl_k_sem_give+0x2e>
    3d5e:	2200      	movs	r2, #0
    3d60:	67c2      	str	r2, [r0, #124]	; 0x7c
		arch_thread_return_value_set(thread, 0);
		z_ready_thread(thread);
    3d62:	f001 fed5 	bl	5b10 <z_ready_thread>
	} else {
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
		handle_poll_events(sem);
	}

	z_reschedule(&lock, key);
    3d66:	4629      	mov	r1, r5
	sys_trace_end_call(SYS_TRACE_ID_SEMA_GIVE);
}
    3d68:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
	z_reschedule(&lock, key);
    3d6c:	4804      	ldr	r0, [pc, #16]	; (3d80 <z_impl_k_sem_give+0x3c>)
    3d6e:	f7ff bc99 	b.w	36a4 <z_reschedule>
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
    3d72:	e9d4 3202 	ldrd	r3, r2, [r4, #8]
    3d76:	429a      	cmp	r2, r3
    3d78:	bf18      	it	ne
    3d7a:	3301      	addne	r3, #1
    3d7c:	60a3      	str	r3, [r4, #8]
		handle_poll_events(sem);
    3d7e:	e7f2      	b.n	3d66 <z_impl_k_sem_give+0x22>
    3d80:	200008af 	.word	0x200008af

00003d84 <z_impl_k_sem_take>:
}
#include <syscalls/k_sem_give_mrsh.c>
#endif

int z_impl_k_sem_take(struct k_sem *sem, k_timeout_t timeout)
{
    3d84:	b537      	push	{r0, r1, r2, r4, r5, lr}
    3d86:	4614      	mov	r4, r2
    3d88:	461d      	mov	r5, r3
    3d8a:	f04f 0320 	mov.w	r3, #32
    3d8e:	f3ef 8111 	mrs	r1, BASEPRI
    3d92:	f383 8811 	msr	BASEPRI, r3
    3d96:	f3bf 8f6f 	isb	sy
		  K_TIMEOUT_EQ(timeout, K_NO_WAIT)), "");

	k_spinlock_key_t key = k_spin_lock(&lock);
	sys_trace_semaphore_take(sem);

	if (likely(sem->count > 0U)) {
    3d9a:	6883      	ldr	r3, [r0, #8]
    3d9c:	b143      	cbz	r3, 3db0 <z_impl_k_sem_take+0x2c>
		sem->count--;
    3d9e:	3b01      	subs	r3, #1
    3da0:	6083      	str	r3, [r0, #8]
	__asm__ volatile(
    3da2:	f381 8811 	msr	BASEPRI, r1
    3da6:	f3bf 8f6f 	isb	sy
		k_spin_unlock(&lock, key);
		ret = 0;
    3daa:	2000      	movs	r0, #0
	ret = z_pend_curr(&lock, key, &sem->wait_q, timeout);

out:
	sys_trace_end_call(SYS_TRACE_ID_SEMA_TAKE);
	return ret;
}
    3dac:	b003      	add	sp, #12
    3dae:	bd30      	pop	{r4, r5, pc}
	if (K_TIMEOUT_EQ(timeout, K_NO_WAIT)) {
    3db0:	ea54 0305 	orrs.w	r3, r4, r5
    3db4:	d106      	bne.n	3dc4 <z_impl_k_sem_take+0x40>
    3db6:	f381 8811 	msr	BASEPRI, r1
    3dba:	f3bf 8f6f 	isb	sy
		ret = -EBUSY;
    3dbe:	f06f 000f 	mvn.w	r0, #15
    3dc2:	e7f3      	b.n	3dac <z_impl_k_sem_take+0x28>
	ret = z_pend_curr(&lock, key, &sem->wait_q, timeout);
    3dc4:	4602      	mov	r2, r0
    3dc6:	e9cd 4500 	strd	r4, r5, [sp]
    3dca:	4802      	ldr	r0, [pc, #8]	; (3dd4 <z_impl_k_sem_take+0x50>)
    3dcc:	f7ff feac 	bl	3b28 <z_pend_curr>
	return ret;
    3dd0:	e7ec      	b.n	3dac <z_impl_k_sem_take+0x28>
    3dd2:	bf00      	nop
    3dd4:	200008af 	.word	0x200008af

00003dd8 <z_setup_new_thread>:
char *z_setup_new_thread(struct k_thread *new_thread,
			 k_thread_stack_t *stack, size_t stack_size,
			 k_thread_entry_t entry,
			 void *p1, void *p2, void *p3,
			 int prio, uint32_t options, const char *name)
{
    3dd8:	e92d 41b0 	stmdb	sp!, {r4, r5, r7, r8, lr}
	sys_dlist_init(&w->waitq);
    3ddc:	f100 0530 	add.w	r5, r0, #48	; 0x30
    3de0:	b085      	sub	sp, #20
	list->tail = (sys_dnode_t *)list;
    3de2:	e9c0 550c 	strd	r5, r5, [r0, #48]	; 0x30
void z_init_thread_base(struct _thread_base *thread_base, int priority,
		       uint32_t initial_state, unsigned int options)
{
	/* k_q_node is initialized upon first insertion in a list */

	thread_base->user_options = (uint8_t)options;
    3de6:	9d0e      	ldr	r5, [sp, #56]	; 0x38
{
    3de8:	4604      	mov	r4, r0
	thread_base->user_options = (uint8_t)options;
    3dea:	7305      	strb	r5, [r0, #12]
	thread_base->thread_state = (uint8_t)initial_state;
    3dec:	2504      	movs	r5, #4
    3dee:	7345      	strb	r5, [r0, #13]

	thread_base->prio = priority;
    3df0:	9d0d      	ldr	r5, [sp, #52]	; 0x34
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    3df2:	3207      	adds	r2, #7
	thread_base->prio = priority;
    3df4:	7385      	strb	r5, [r0, #14]

	thread_base->sched_locked = 0U;
    3df6:	2500      	movs	r5, #0
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    3df8:	f022 0207 	bic.w	r2, r2, #7
	new_thread->stack_info.size = stack_buf_size;
    3dfc:	e9c0 121a 	strd	r1, r2, [r0, #104]	; 0x68
	stack_ptr = (char *)stack + stack_obj_size;
    3e00:	eb01 0802 	add.w	r8, r1, r2
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    3e04:	9a0c      	ldr	r2, [sp, #48]	; 0x30
	node->prev = NULL;
    3e06:	e9c0 5506 	strd	r5, r5, [r0, #24]
	thread_base->sched_locked = 0U;
    3e0a:	73c5      	strb	r5, [r0, #15]
	new_thread->stack_info.delta = delta;
    3e0c:	6705      	str	r5, [r0, #112]	; 0x70
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    3e0e:	9202      	str	r2, [sp, #8]
    3e10:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
    3e12:	9201      	str	r2, [sp, #4]
    3e14:	9a0a      	ldr	r2, [sp, #40]	; 0x28
    3e16:	9200      	str	r2, [sp, #0]
    3e18:	4642      	mov	r2, r8
    3e1a:	f7fe f9e3 	bl	21e4 <arch_new_thread>
	if (!_current) {
    3e1e:	4b05      	ldr	r3, [pc, #20]	; (3e34 <z_setup_new_thread+0x5c>)
	new_thread->fn_abort = NULL;
    3e20:	e9c4 5517 	strd	r5, r5, [r4, #92]	; 0x5c
	if (!_current) {
    3e24:	689b      	ldr	r3, [r3, #8]
    3e26:	b103      	cbz	r3, 3e2a <z_setup_new_thread+0x52>
	new_thread->resource_pool = _current->resource_pool;
    3e28:	6f5b      	ldr	r3, [r3, #116]	; 0x74
}
    3e2a:	4640      	mov	r0, r8
    3e2c:	6763      	str	r3, [r4, #116]	; 0x74
    3e2e:	b005      	add	sp, #20
    3e30:	e8bd 81b0 	ldmia.w	sp!, {r4, r5, r7, r8, pc}
    3e34:	2000084c 	.word	0x2000084c

00003e38 <z_init_static_threads>:
{
    3e38:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
	_FOREACH_STATIC_THREAD(thread_data) {
    3e3c:	4e2a      	ldr	r6, [pc, #168]	; (3ee8 <z_init_static_threads+0xb0>)
    3e3e:	4d2b      	ldr	r5, [pc, #172]	; (3eec <z_init_static_threads+0xb4>)
    3e40:	46b0      	mov	r8, r6
{
    3e42:	b086      	sub	sp, #24
	_FOREACH_STATIC_THREAD(thread_data) {
    3e44:	42b5      	cmp	r5, r6
    3e46:	f105 0430 	add.w	r4, r5, #48	; 0x30
    3e4a:	d310      	bcc.n	3e6e <z_init_static_threads+0x36>
	k_sched_lock();
    3e4c:	f7ff fc3c 	bl	36c8 <k_sched_lock>
    3e50:	f44f 4900 	mov.w	r9, #32768	; 0x8000
    3e54:	f240 36e7 	movw	r6, #999	; 0x3e7
    3e58:	2700      	movs	r7, #0
	_FOREACH_STATIC_THREAD(thread_data) {
    3e5a:	4c24      	ldr	r4, [pc, #144]	; (3eec <z_init_static_threads+0xb4>)
    3e5c:	f8df a090 	ldr.w	sl, [pc, #144]	; 3ef0 <z_init_static_threads+0xb8>
    3e60:	4544      	cmp	r4, r8
    3e62:	d321      	bcc.n	3ea8 <z_init_static_threads+0x70>
}
    3e64:	b006      	add	sp, #24
    3e66:	e8bd 47f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
	k_sched_unlock();
    3e6a:	f7ff bc7f 	b.w	376c <k_sched_unlock>
		z_setup_new_thread(
    3e6e:	f854 3c04 	ldr.w	r3, [r4, #-4]
    3e72:	9305      	str	r3, [sp, #20]
    3e74:	f854 3c10 	ldr.w	r3, [r4, #-16]
    3e78:	9304      	str	r3, [sp, #16]
    3e7a:	f854 3c14 	ldr.w	r3, [r4, #-20]
    3e7e:	9303      	str	r3, [sp, #12]
    3e80:	f854 3c18 	ldr.w	r3, [r4, #-24]
    3e84:	9302      	str	r3, [sp, #8]
    3e86:	f854 3c1c 	ldr.w	r3, [r4, #-28]
    3e8a:	9301      	str	r3, [sp, #4]
    3e8c:	f854 3c20 	ldr.w	r3, [r4, #-32]
    3e90:	9300      	str	r3, [sp, #0]
    3e92:	e954 230a 	ldrd	r2, r3, [r4, #-40]	; 0x28
    3e96:	e954 010c 	ldrd	r0, r1, [r4, #-48]	; 0x30
    3e9a:	f7ff ff9d 	bl	3dd8 <z_setup_new_thread>
		thread_data->init_thread->init_data = thread_data;
    3e9e:	f854 3c30 	ldr.w	r3, [r4, #-48]
    3ea2:	65dd      	str	r5, [r3, #92]	; 0x5c
    3ea4:	4625      	mov	r5, r4
    3ea6:	e7cd      	b.n	3e44 <z_init_static_threads+0xc>
		if (thread_data->init_delay != K_TICKS_FOREVER) {
    3ea8:	6a63      	ldr	r3, [r4, #36]	; 0x24
    3eaa:	1c5a      	adds	r2, r3, #1
    3eac:	d00d      	beq.n	3eca <z_init_static_threads+0x92>
    3eae:	4630      	mov	r0, r6
    3eb0:	4639      	mov	r1, r7
					    K_MSEC(thread_data->init_delay));
    3eb2:	ea23 73e3 	bic.w	r3, r3, r3, asr #31
    3eb6:	fbc9 0103 	smlal	r0, r1, r9, r3
	if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) {
    3eba:	42b9      	cmp	r1, r7
    3ebc:	bf08      	it	eq
    3ebe:	42b0      	cmpeq	r0, r6
			schedule_new_thread(thread_data->init_thread,
    3ec0:	6825      	ldr	r5, [r4, #0]
	if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) {
    3ec2:	d104      	bne.n	3ece <z_init_static_threads+0x96>
	z_sched_start(thread);
    3ec4:	4628      	mov	r0, r5
    3ec6:	f7ff fca1 	bl	380c <z_sched_start>
	_FOREACH_STATIC_THREAD(thread_data) {
    3eca:	3430      	adds	r4, #48	; 0x30
    3ecc:	e7c8      	b.n	3e60 <z_init_static_threads+0x28>
    3ece:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    3ed2:	2300      	movs	r3, #0
    3ed4:	f7fc f9b2 	bl	23c <__aeabi_uldivmod>
    3ed8:	4602      	mov	r2, r0
    3eda:	460b      	mov	r3, r1
    3edc:	f105 0018 	add.w	r0, r5, #24
    3ee0:	4651      	mov	r1, sl
    3ee2:	f000 f885 	bl	3ff0 <z_add_timeout>
    3ee6:	e7f0      	b.n	3eca <z_init_static_threads+0x92>
    3ee8:	200000d4 	.word	0x200000d4
    3eec:	200000d4 	.word	0x200000d4
    3ef0:	00005b31 	.word	0x00005b31

00003ef4 <z_self_abort>:
#include <syscall_handler.h>
#include <logging/log.h>
LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);

FUNC_NORETURN void z_self_abort(void)
{
    3ef4:	b508      	push	{r3, lr}
	__asm__ volatile(
    3ef6:	f04f 0320 	mov.w	r3, #32
    3efa:	f3ef 8411 	mrs	r4, BASEPRI
    3efe:	f383 8811 	msr	BASEPRI, r3
    3f02:	f3bf 8f6f 	isb	sy
	 * while we set this up
	 */
	key = arch_irq_lock();
	cpu = _current_cpu;
	__ASSERT(cpu->pending_abort == NULL, "already have a thread to abort");
	cpu->pending_abort = _current;
    3f06:	4b04      	ldr	r3, [pc, #16]	; (3f18 <z_self_abort+0x24>)
    3f08:	6898      	ldr	r0, [r3, #8]
    3f0a:	6118      	str	r0, [r3, #16]
	z_impl_k_thread_suspend(thread);
    3f0c:	f7ff fd16 	bl	393c <z_impl_k_thread_suspend>
    3f10:	4620      	mov	r0, r4
    3f12:	f7fe f8dd 	bl	20d0 <arch_swap>
		_current, cpu->idle_thread);

	k_thread_suspend(_current);
	z_swap_irqlock(key);
	__ASSERT(false, "should never get here");
	CODE_UNREACHABLE; /* LCOV_EXCL_LINE */
    3f16:	bf00      	nop
    3f18:	2000084c 	.word	0x2000084c

00003f1c <z_data_copy>:
 * This routine copies the data section from ROM to RAM.
 *
 * @return N/A
 */
void z_data_copy(void)
{
    3f1c:	b508      	push	{r3, lr}
	(void)memcpy(&__data_ram_start, &__data_rom_start,
		 __data_ram_end - __data_ram_start);
    3f1e:	4806      	ldr	r0, [pc, #24]	; (3f38 <z_data_copy+0x1c>)
	(void)memcpy(&__data_ram_start, &__data_rom_start,
    3f20:	4a06      	ldr	r2, [pc, #24]	; (3f3c <z_data_copy+0x20>)
    3f22:	4907      	ldr	r1, [pc, #28]	; (3f40 <z_data_copy+0x24>)
    3f24:	1a12      	subs	r2, r2, r0
    3f26:	f001 fcd7 	bl	58d8 <memcpy>
#else
	(void)memcpy(&_app_smem_start, &_app_smem_rom_start,
		 _app_smem_end - _app_smem_start);
#endif /* CONFIG_STACK_CANARIES */
#endif /* CONFIG_USERSPACE */
}
    3f2a:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	(void)memcpy(&_ramfunc_ram_start, &_ramfunc_rom_start,
    3f2e:	4a05      	ldr	r2, [pc, #20]	; (3f44 <z_data_copy+0x28>)
    3f30:	4905      	ldr	r1, [pc, #20]	; (3f48 <z_data_copy+0x2c>)
    3f32:	4806      	ldr	r0, [pc, #24]	; (3f4c <z_data_copy+0x30>)
    3f34:	f001 bcd0 	b.w	58d8 <memcpy>
    3f38:	20000000 	.word	0x20000000
    3f3c:	20000124 	.word	0x20000124
    3f40:	000065c4 	.word	0x000065c4
    3f44:	00000000 	.word	0x00000000
    3f48:	000065c4 	.word	0x000065c4
    3f4c:	20000000 	.word	0x20000000

00003f50 <elapsed>:
	sys_dlist_remove(&t->node);
}

static int32_t elapsed(void)
{
	return announce_remaining == 0 ? z_clock_elapsed() : 0U;
    3f50:	4b03      	ldr	r3, [pc, #12]	; (3f60 <elapsed+0x10>)
    3f52:	681b      	ldr	r3, [r3, #0]
    3f54:	b90b      	cbnz	r3, 3f5a <elapsed+0xa>
    3f56:	f7fd bd7f 	b.w	1a58 <z_clock_elapsed>
}
    3f5a:	2000      	movs	r0, #0
    3f5c:	4770      	bx	lr
    3f5e:	bf00      	nop
    3f60:	2000088c 	.word	0x2000088c

00003f64 <remove_timeout>:
{
    3f64:	b530      	push	{r4, r5, lr}
    3f66:	6803      	ldr	r3, [r0, #0]
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    3f68:	b168      	cbz	r0, 3f86 <remove_timeout+0x22>
    3f6a:	4a0a      	ldr	r2, [pc, #40]	; (3f94 <remove_timeout+0x30>)
	return (node == list->tail) ? NULL : node->next;
    3f6c:	6852      	ldr	r2, [r2, #4]
    3f6e:	4290      	cmp	r0, r2
    3f70:	d009      	beq.n	3f86 <remove_timeout+0x22>
	if (next(t) != NULL) {
    3f72:	b143      	cbz	r3, 3f86 <remove_timeout+0x22>
		next(t)->dticks += t->dticks;
    3f74:	e9d3 2104 	ldrd	r2, r1, [r3, #16]
    3f78:	e9d0 4504 	ldrd	r4, r5, [r0, #16]
    3f7c:	1912      	adds	r2, r2, r4
    3f7e:	eb45 0101 	adc.w	r1, r5, r1
    3f82:	e9c3 2104 	strd	r2, r1, [r3, #16]
	node->prev->next = node->next;
    3f86:	6842      	ldr	r2, [r0, #4]
    3f88:	6013      	str	r3, [r2, #0]
	node->next->prev = node->prev;
    3f8a:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    3f8c:	2300      	movs	r3, #0
	node->prev = NULL;
    3f8e:	e9c0 3300 	strd	r3, r3, [r0]
}
    3f92:	bd30      	pop	{r4, r5, pc}
    3f94:	20000028 	.word	0x20000028

00003f98 <next_timeout>:
	return list->head == list;
    3f98:	4b13      	ldr	r3, [pc, #76]	; (3fe8 <next_timeout+0x50>)

static int32_t next_timeout(void)
{
    3f9a:	b510      	push	{r4, lr}
    3f9c:	681c      	ldr	r4, [r3, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    3f9e:	429c      	cmp	r4, r3
    3fa0:	bf08      	it	eq
    3fa2:	2400      	moveq	r4, #0
	struct _timeout *to = first();
	int32_t ticks_elapsed = elapsed();
    3fa4:	f7ff ffd4 	bl	3f50 <elapsed>
	int32_t ret = to == NULL ? MAX_WAIT
    3fa8:	b1cc      	cbz	r4, 3fde <next_timeout+0x46>
		: CLAMP(to->dticks - ticks_elapsed, 0, MAX_WAIT);
    3faa:	e9d4 2304 	ldrd	r2, r3, [r4, #16]
    3fae:	1a12      	subs	r2, r2, r0
    3fb0:	eb63 73e0 	sbc.w	r3, r3, r0, asr #31
	int32_t ret = to == NULL ? MAX_WAIT
    3fb4:	2a01      	cmp	r2, #1
    3fb6:	f173 0100 	sbcs.w	r1, r3, #0
    3fba:	db13      	blt.n	3fe4 <next_timeout+0x4c>
		: CLAMP(to->dticks - ticks_elapsed, 0, MAX_WAIT);
    3fbc:	4610      	mov	r0, r2
    3fbe:	f06f 4200 	mvn.w	r2, #2147483648	; 0x80000000
    3fc2:	4619      	mov	r1, r3
    3fc4:	2300      	movs	r3, #0
    3fc6:	4282      	cmp	r2, r0
    3fc8:	eb73 0401 	sbcs.w	r4, r3, r1
    3fcc:	da00      	bge.n	3fd0 <next_timeout+0x38>
    3fce:	4610      	mov	r0, r2

#ifdef CONFIG_TIMESLICING
	if (_current_cpu->slice_ticks && _current_cpu->slice_ticks < ret) {
    3fd0:	4b06      	ldr	r3, [pc, #24]	; (3fec <next_timeout+0x54>)
    3fd2:	695b      	ldr	r3, [r3, #20]
    3fd4:	b113      	cbz	r3, 3fdc <next_timeout+0x44>
    3fd6:	4298      	cmp	r0, r3
    3fd8:	bfa8      	it	ge
    3fda:	4618      	movge	r0, r3
		ret = _current_cpu->slice_ticks;
	}
#endif
	return ret;
}
    3fdc:	bd10      	pop	{r4, pc}
	int32_t ret = to == NULL ? MAX_WAIT
    3fde:	f06f 4000 	mvn.w	r0, #2147483648	; 0x80000000
    3fe2:	e7f5      	b.n	3fd0 <next_timeout+0x38>
    3fe4:	2000      	movs	r0, #0
    3fe6:	e7f3      	b.n	3fd0 <next_timeout+0x38>
    3fe8:	20000028 	.word	0x20000028
    3fec:	2000084c 	.word	0x2000084c

00003ff0 <z_add_timeout>:

void z_add_timeout(struct _timeout *to, _timeout_func_t fn,
		   k_timeout_t timeout)
{
    3ff0:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    3ff4:	9101      	str	r1, [sp, #4]
    3ff6:	4619      	mov	r1, r3
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    3ff8:	1c4b      	adds	r3, r1, #1
    3ffa:	bf08      	it	eq
    3ffc:	f1b2 3fff 	cmpeq.w	r2, #4294967295	; 0xffffffff
{
    4000:	4682      	mov	sl, r0
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    4002:	d070      	beq.n	40e6 <z_add_timeout+0xf6>
	__ASSERT_NO_MSG(arch_mem_coherent(to));
#endif

	k_ticks_t ticks = timeout.ticks + 1;

	if (IS_ENABLED(CONFIG_TIMEOUT_64BIT) && Z_TICK_ABS(ticks) >= 0) {
    4004:	f06f 0301 	mvn.w	r3, #1
    4008:	f04f 3bff 	mov.w	fp, #4294967295	; 0xffffffff
	k_ticks_t ticks = timeout.ticks + 1;
    400c:	1c54      	adds	r4, r2, #1
    400e:	f141 0500 	adc.w	r5, r1, #0
	if (IS_ENABLED(CONFIG_TIMEOUT_64BIT) && Z_TICK_ABS(ticks) >= 0) {
    4012:	ebb3 0804 	subs.w	r8, r3, r4
    4016:	eb6b 0905 	sbc.w	r9, fp, r5
    401a:	f1b8 0f00 	cmp.w	r8, #0
    401e:	f179 0300 	sbcs.w	r3, r9, #0
    4022:	db0f      	blt.n	4044 <z_add_timeout+0x54>
		ticks = Z_TICK_ABS(ticks) - (curr_tick + elapsed());
    4024:	f7ff ff94 	bl	3f50 <elapsed>
    4028:	f06f 0301 	mvn.w	r3, #1
    402c:	4a34      	ldr	r2, [pc, #208]	; (4100 <z_add_timeout+0x110>)
    402e:	e9d2 1c00 	ldrd	r1, ip, [r2]
    4032:	1a5b      	subs	r3, r3, r1
    4034:	eb6b 020c 	sbc.w	r2, fp, ip
    4038:	1b1e      	subs	r6, r3, r4
    403a:	eb62 0705 	sbc.w	r7, r2, r5
    403e:	1a34      	subs	r4, r6, r0
    4040:	eb67 75e0 	sbc.w	r5, r7, r0, asr #31
	}

	__ASSERT(!sys_dnode_is_linked(&to->node), "");
	to->fn = fn;
    4044:	9b01      	ldr	r3, [sp, #4]
    4046:	f8ca 3008 	str.w	r3, [sl, #8]
    404a:	f04f 0320 	mov.w	r3, #32
    404e:	f3ef 8611 	mrs	r6, BASEPRI
    4052:	f383 8811 	msr	BASEPRI, r3
    4056:	f3bf 8f6f 	isb	sy
	ticks = MAX(1, ticks);

	LOCKED(&timeout_lock) {
		struct _timeout *t;

		to->dticks = ticks + elapsed();
    405a:	f7ff ff79 	bl	3f50 <elapsed>
	ticks = MAX(1, ticks);
    405e:	2c01      	cmp	r4, #1
    4060:	f175 0300 	sbcs.w	r3, r5, #0
    4064:	bfbc      	itt	lt
    4066:	2401      	movlt	r4, #1
    4068:	2500      	movlt	r5, #0
	return list->head == list;
    406a:	4b26      	ldr	r3, [pc, #152]	; (4104 <z_add_timeout+0x114>)
		to->dticks = ticks + elapsed();
    406c:	1824      	adds	r4, r4, r0
    406e:	681a      	ldr	r2, [r3, #0]
    4070:	eb45 75e0 	adc.w	r5, r5, r0, asr #31
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4074:	429a      	cmp	r2, r3
    4076:	e9ca 4504 	strd	r4, r5, [sl, #16]
    407a:	d001      	beq.n	4080 <z_add_timeout+0x90>
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    407c:	685f      	ldr	r7, [r3, #4]
		for (t = first(); t != NULL; t = next(t)) {
    407e:	b952      	cbnz	r2, 4096 <z_add_timeout+0xa6>
	node->prev = list->tail;
    4080:	685a      	ldr	r2, [r3, #4]
	node->next = list;
    4082:	f8ca 3000 	str.w	r3, [sl]
	node->prev = list->tail;
    4086:	f8ca 2004 	str.w	r2, [sl, #4]
	list->tail->next = node;
    408a:	685a      	ldr	r2, [r3, #4]
    408c:	f8c2 a000 	str.w	sl, [r2]
	list->tail = node;
    4090:	f8c3 a004 	str.w	sl, [r3, #4]
}
    4094:	e014      	b.n	40c0 <z_add_timeout+0xd0>
			if (t->dticks > to->dticks) {
    4096:	e9d2 8904 	ldrd	r8, r9, [r2, #16]
    409a:	e9da 4504 	ldrd	r4, r5, [sl, #16]
    409e:	4544      	cmp	r4, r8
    40a0:	eb75 0109 	sbcs.w	r1, r5, r9
    40a4:	da22      	bge.n	40ec <z_add_timeout+0xfc>
				t->dticks -= to->dticks;
    40a6:	ebb8 0004 	subs.w	r0, r8, r4
    40aa:	eb69 0105 	sbc.w	r1, r9, r5
    40ae:	e9c2 0104 	strd	r0, r1, [r2, #16]
	node->prev = successor->prev;
    40b2:	6851      	ldr	r1, [r2, #4]
	node->next = successor;
    40b4:	e9ca 2100 	strd	r2, r1, [sl]
	successor->prev->next = node;
    40b8:	f8c1 a000 	str.w	sl, [r1]
	successor->prev = node;
    40bc:	f8c2 a004 	str.w	sl, [r2, #4]
	return list->head == list;
    40c0:	681a      	ldr	r2, [r3, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    40c2:	429a      	cmp	r2, r3
    40c4:	d00b      	beq.n	40de <z_add_timeout+0xee>

		if (t == NULL) {
			sys_dlist_append(&timeout_list, &to->node);
		}

		if (to == first()) {
    40c6:	4592      	cmp	sl, r2
    40c8:	d109      	bne.n	40de <z_add_timeout+0xee>
			 * last announcement, and slice_ticks is based
			 * on that. It means the that time remaining for
			 * the next announcement can be lesser than
			 * slice_ticks.
			 */
			int32_t next_time = next_timeout();
    40ca:	f7ff ff65 	bl	3f98 <next_timeout>

			if (next_time == 0 ||
    40ce:	b118      	cbz	r0, 40d8 <z_add_timeout+0xe8>
			    _current_cpu->slice_ticks != next_time) {
    40d0:	4b0d      	ldr	r3, [pc, #52]	; (4108 <z_add_timeout+0x118>)
			if (next_time == 0 ||
    40d2:	695b      	ldr	r3, [r3, #20]
    40d4:	4283      	cmp	r3, r0
    40d6:	d002      	beq.n	40de <z_add_timeout+0xee>
				z_clock_set_timeout(next_time, false);
    40d8:	2100      	movs	r1, #0
    40da:	f7fd fc8b 	bl	19f4 <z_clock_set_timeout>
	__asm__ volatile(
    40de:	f386 8811 	msr	BASEPRI, r6
    40e2:	f3bf 8f6f 	isb	sy
#else
			z_clock_set_timeout(next_timeout(), false);
#endif	/* CONFIG_TIMESLICING */
		}
	}
}
    40e6:	b003      	add	sp, #12
    40e8:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
			to->dticks -= t->dticks;
    40ec:	ebb4 0008 	subs.w	r0, r4, r8
    40f0:	eb65 0109 	sbc.w	r1, r5, r9
	return (node == list->tail) ? NULL : node->next;
    40f4:	42ba      	cmp	r2, r7
    40f6:	e9ca 0104 	strd	r0, r1, [sl, #16]
    40fa:	d0c1      	beq.n	4080 <z_add_timeout+0x90>
    40fc:	6812      	ldr	r2, [r2, #0]
    40fe:	e7be      	b.n	407e <z_add_timeout+0x8e>
    4100:	20000228 	.word	0x20000228
    4104:	20000028 	.word	0x20000028
    4108:	2000084c 	.word	0x2000084c

0000410c <z_clock_announce>:
		}
	}
}

void z_clock_announce(int32_t ticks)
{
    410c:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    4110:	4606      	mov	r6, r0
#ifdef CONFIG_TIMESLICING
	z_time_slice(ticks);
    4112:	f7ff fbd1 	bl	38b8 <z_time_slice>
	__asm__ volatile(
    4116:	f04f 0320 	mov.w	r3, #32
    411a:	f3ef 8411 	mrs	r4, BASEPRI
    411e:	f383 8811 	msr	BASEPRI, r3
    4122:	f3bf 8f6f 	isb	sy
#endif

	k_spinlock_key_t key = k_spin_lock(&timeout_lock);

	announce_remaining = ticks;
    4126:	f8df a0b0 	ldr.w	sl, [pc, #176]	; 41d8 <z_clock_announce+0xcc>
    412a:	4d2a      	ldr	r5, [pc, #168]	; (41d4 <z_clock_announce+0xc8>)
    412c:	4651      	mov	r1, sl
	return list->head == list;
    412e:	f8df b0ac 	ldr.w	fp, [pc, #172]	; 41dc <z_clock_announce+0xd0>
    4132:	602e      	str	r6, [r5, #0]
    4134:	f8d5 c000 	ldr.w	ip, [r5]
    4138:	f8db 0000 	ldr.w	r0, [fp]
    413c:	4662      	mov	r2, ip
    413e:	e9da 8900 	ldrd	r8, r9, [sl]
    4142:	17d3      	asrs	r3, r2, #31
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4144:	4558      	cmp	r0, fp
    4146:	e9cd 2300 	strd	r2, r3, [sp]
    414a:	d00d      	beq.n	4168 <z_clock_announce+0x5c>

	while (first() != NULL && first()->dticks <= announce_remaining) {
    414c:	b160      	cbz	r0, 4168 <z_clock_announce+0x5c>
    414e:	e9d0 6704 	ldrd	r6, r7, [r0, #16]
    4152:	45b4      	cmp	ip, r6
    4154:	41bb      	sbcs	r3, r7
    4156:	da1d      	bge.n	4194 <z_clock_announce+0x88>
		t->fn(t);
		key = k_spin_lock(&timeout_lock);
	}

	if (first() != NULL) {
		first()->dticks -= announce_remaining;
    4158:	9b00      	ldr	r3, [sp, #0]
    415a:	ebb6 0c03 	subs.w	ip, r6, r3
    415e:	9b01      	ldr	r3, [sp, #4]
    4160:	eb67 0603 	sbc.w	r6, r7, r3
    4164:	e9c0 c604 	strd	ip, r6, [r0, #16]
	}

	curr_tick += announce_remaining;
	announce_remaining = 0;
    4168:	2600      	movs	r6, #0
	curr_tick += announce_remaining;
    416a:	9b00      	ldr	r3, [sp, #0]
	announce_remaining = 0;
    416c:	602e      	str	r6, [r5, #0]
	curr_tick += announce_remaining;
    416e:	eb13 0208 	adds.w	r2, r3, r8
    4172:	9b01      	ldr	r3, [sp, #4]
    4174:	eb43 0309 	adc.w	r3, r3, r9
    4178:	e9c1 2300 	strd	r2, r3, [r1]

	z_clock_set_timeout(next_timeout(), false);
    417c:	f7ff ff0c 	bl	3f98 <next_timeout>
    4180:	4631      	mov	r1, r6
    4182:	f7fd fc37 	bl	19f4 <z_clock_set_timeout>
	__asm__ volatile(
    4186:	f384 8811 	msr	BASEPRI, r4
    418a:	f3bf 8f6f 	isb	sy

	k_spin_unlock(&timeout_lock, key);
}
    418e:	b003      	add	sp, #12
    4190:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		t->dticks = 0;
    4194:	2200      	movs	r2, #0
    4196:	2300      	movs	r3, #0
		curr_tick += dt;
    4198:	eb18 0806 	adds.w	r8, r8, r6
    419c:	eb49 79e6 	adc.w	r9, r9, r6, asr #31
		t->dticks = 0;
    41a0:	e9c0 2304 	strd	r2, r3, [r0, #16]
		announce_remaining -= dt;
    41a4:	ebac 0606 	sub.w	r6, ip, r6
		curr_tick += dt;
    41a8:	e9ca 8900 	strd	r8, r9, [sl]
		announce_remaining -= dt;
    41ac:	602e      	str	r6, [r5, #0]
		remove_timeout(t);
    41ae:	f7ff fed9 	bl	3f64 <remove_timeout>
    41b2:	f384 8811 	msr	BASEPRI, r4
    41b6:	f3bf 8f6f 	isb	sy
		t->fn(t);
    41ba:	6883      	ldr	r3, [r0, #8]
    41bc:	4798      	blx	r3
	__asm__ volatile(
    41be:	f04f 0320 	mov.w	r3, #32
    41c2:	f3ef 8411 	mrs	r4, BASEPRI
    41c6:	f383 8811 	msr	BASEPRI, r3
    41ca:	f3bf 8f6f 	isb	sy

	/* Note that we need to use the underlying arch-specific lock
	 * implementation.  The "irq_lock()" API in SMP context is
	 * actually a wrapper for a global spinlock!
	 */
	k.key = arch_irq_lock();
    41ce:	4902      	ldr	r1, [pc, #8]	; (41d8 <z_clock_announce+0xcc>)
#endif

#ifdef CONFIG_SPIN_VALIDATE
	z_spin_lock_set_owner(l);
#endif
	return k;
    41d0:	e7b0      	b.n	4134 <z_clock_announce+0x28>
    41d2:	bf00      	nop
    41d4:	2000088c 	.word	0x2000088c
    41d8:	20000228 	.word	0x20000228
    41dc:	20000028 	.word	0x20000028

000041e0 <z_tick_get>:

int64_t z_tick_get(void)
{
    41e0:	b510      	push	{r4, lr}
    41e2:	f04f 0320 	mov.w	r3, #32
    41e6:	f3ef 8411 	mrs	r4, BASEPRI
    41ea:	f383 8811 	msr	BASEPRI, r3
    41ee:	f3bf 8f6f 	isb	sy
	uint64_t t = 0U;

	LOCKED(&timeout_lock) {
		t = curr_tick + z_clock_elapsed();
    41f2:	f7fd fc31 	bl	1a58 <z_clock_elapsed>
    41f6:	4b06      	ldr	r3, [pc, #24]	; (4210 <z_tick_get+0x30>)
    41f8:	e9d3 2300 	ldrd	r2, r3, [r3]
    41fc:	1812      	adds	r2, r2, r0
    41fe:	f143 0300 	adc.w	r3, r3, #0
	__asm__ volatile(
    4202:	f384 8811 	msr	BASEPRI, r4
    4206:	f3bf 8f6f 	isb	sy
	}
	return t;
}
    420a:	4610      	mov	r0, r2
    420c:	4619      	mov	r1, r3
    420e:	bd10      	pop	{r4, pc}
    4210:	20000228 	.word	0x20000228

00004214 <z_sys_init_run_level>:
 * off and the next one begins.
 *
 * @param level init level to run.
 */
void z_sys_init_run_level(int32_t level)
{
    4214:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
		/* End marker */
		__init_end,
	};
	const struct init_entry *entry;

	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    4216:	4b10      	ldr	r3, [pc, #64]	; (4258 <z_sys_init_run_level+0x44>)
			/* Initialization failed.
			 * Set the init status bit so device is not declared ready.
			 */
			sys_bitfield_set_bit(
				(mem_addr_t) __device_init_status_start,
				(dev - __device_start));
    4218:	4f10      	ldr	r7, [pc, #64]	; (425c <z_sys_init_run_level+0x48>)
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    421a:	f853 5020 	ldr.w	r5, [r3, r0, lsl #2]
    421e:	3001      	adds	r0, #1
    4220:	f853 6020 	ldr.w	r6, [r3, r0, lsl #2]
    4224:	42ae      	cmp	r6, r5
    4226:	d800      	bhi.n	422a <z_sys_init_run_level+0x16>
		}
	}
}
    4228:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
		if ((entry->init(dev) != 0) && (dev != NULL)) {
    422a:	e9d5 3400 	ldrd	r3, r4, [r5]
    422e:	4620      	mov	r0, r4
    4230:	4798      	blx	r3
    4232:	b170      	cbz	r0, 4252 <z_sys_init_run_level+0x3e>
    4234:	b16c      	cbz	r4, 4252 <z_sys_init_run_level+0x3e>

static ALWAYS_INLINE void sys_set_bit(mem_addr_t addr, unsigned int bit)
{
	uint32_t temp = *(volatile uint32_t *)addr;

	*(volatile uint32_t *)addr = temp | (1 << bit);
    4236:	2301      	movs	r3, #1
				(dev - __device_start));
    4238:	1be4      	subs	r4, r4, r7
	void sys_bitfield_set_bit(mem_addr_t addr, unsigned int bit)
{
	/* Doing memory offsets in terms of 32-bit values to prevent
	 * alignment issues
	 */
	sys_set_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
    423a:	4a09      	ldr	r2, [pc, #36]	; (4260 <z_sys_init_run_level+0x4c>)
    423c:	1124      	asrs	r4, r4, #4
    423e:	0961      	lsrs	r1, r4, #5
	uint32_t temp = *(volatile uint32_t *)addr;
    4240:	f852 0021 	ldr.w	r0, [r2, r1, lsl #2]
	sys_set_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
    4244:	f004 041f 	and.w	r4, r4, #31
	*(volatile uint32_t *)addr = temp | (1 << bit);
    4248:	fa03 f404 	lsl.w	r4, r3, r4
    424c:	4304      	orrs	r4, r0
    424e:	f842 4021 	str.w	r4, [r2, r1, lsl #2]
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    4252:	3508      	adds	r5, #8
    4254:	e7e6      	b.n	4224 <z_sys_init_run_level+0x10>
    4256:	bf00      	nop
    4258:	00006100 	.word	0x00006100
    425c:	20000090 	.word	0x20000090
    4260:	200000d0 	.word	0x200000d0

00004264 <statics_init>:
	z_waitq_init(&h->wait_q);
	sys_heap_init(&h->heap, mem, bytes);
}

static int statics_init(const struct device *unused)
{
    4264:	b538      	push	{r3, r4, r5, lr}
	ARG_UNUSED(unused);
	Z_STRUCT_SECTION_FOREACH(k_heap, h) {
    4266:	4c06      	ldr	r4, [pc, #24]	; (4280 <statics_init+0x1c>)
    4268:	4d06      	ldr	r5, [pc, #24]	; (4284 <statics_init+0x20>)
    426a:	42ac      	cmp	r4, r5
    426c:	d301      	bcc.n	4272 <statics_init+0xe>
		k_heap_init(h, h->heap.init_mem, h->heap.init_bytes);
	}
	return 0;
}
    426e:	2000      	movs	r0, #0
    4270:	bd38      	pop	{r3, r4, r5, pc}
		k_heap_init(h, h->heap.init_mem, h->heap.init_bytes);
    4272:	4620      	mov	r0, r4
    4274:	e9d4 1201 	ldrd	r1, r2, [r4, #4]
    4278:	f001 fd17 	bl	5caa <k_heap_init>
	Z_STRUCT_SECTION_FOREACH(k_heap, h) {
    427c:	3414      	adds	r4, #20
    427e:	e7f4      	b.n	426a <statics_init+0x6>
    4280:	200000d4 	.word	0x200000d4
    4284:	200000d4 	.word	0x200000d4

00004288 <CC_PalMemCopyPlat>:
    4288:	f001 bb0f 	b.w	58aa <memmove>

0000428c <CC_PalMemSetZeroPlat>:
    428c:	460a      	mov	r2, r1
    428e:	2100      	movs	r1, #0
    4290:	f001 bb4d 	b.w	592e <memset>

00004294 <CC_PalInit>:
    4294:	b510      	push	{r4, lr}
    4296:	4811      	ldr	r0, [pc, #68]	; (42dc <CC_PalInit+0x48>)
    4298:	f000 f848 	bl	432c <CC_PalMutexCreate>
    429c:	b100      	cbz	r0, 42a0 <CC_PalInit+0xc>
    429e:	bd10      	pop	{r4, pc}
    42a0:	480f      	ldr	r0, [pc, #60]	; (42e0 <CC_PalInit+0x4c>)
    42a2:	f000 f843 	bl	432c <CC_PalMutexCreate>
    42a6:	2800      	cmp	r0, #0
    42a8:	d1f9      	bne.n	429e <CC_PalInit+0xa>
    42aa:	4c0e      	ldr	r4, [pc, #56]	; (42e4 <CC_PalInit+0x50>)
    42ac:	4620      	mov	r0, r4
    42ae:	f000 f83d 	bl	432c <CC_PalMutexCreate>
    42b2:	2800      	cmp	r0, #0
    42b4:	d1f3      	bne.n	429e <CC_PalInit+0xa>
    42b6:	4b0c      	ldr	r3, [pc, #48]	; (42e8 <CC_PalInit+0x54>)
    42b8:	480c      	ldr	r0, [pc, #48]	; (42ec <CC_PalInit+0x58>)
    42ba:	601c      	str	r4, [r3, #0]
    42bc:	f000 f836 	bl	432c <CC_PalMutexCreate>
    42c0:	4601      	mov	r1, r0
    42c2:	2800      	cmp	r0, #0
    42c4:	d1eb      	bne.n	429e <CC_PalInit+0xa>
    42c6:	f000 f82d 	bl	4324 <CC_PalDmaInit>
    42ca:	4604      	mov	r4, r0
    42cc:	b108      	cbz	r0, 42d2 <CC_PalInit+0x3e>
    42ce:	4620      	mov	r0, r4
    42d0:	bd10      	pop	{r4, pc}
    42d2:	f000 f851 	bl	4378 <CC_PalPowerSaveModeInit>
    42d6:	4620      	mov	r0, r4
    42d8:	e7fa      	b.n	42d0 <CC_PalInit+0x3c>
    42da:	bf00      	nop
    42dc:	2000003c 	.word	0x2000003c
    42e0:	20000030 	.word	0x20000030
    42e4:	20000038 	.word	0x20000038
    42e8:	20000040 	.word	0x20000040
    42ec:	20000034 	.word	0x20000034

000042f0 <CC_PalTerminate>:
    42f0:	b508      	push	{r3, lr}
    42f2:	4808      	ldr	r0, [pc, #32]	; (4314 <CC_PalTerminate+0x24>)
    42f4:	f000 f824 	bl	4340 <CC_PalMutexDestroy>
    42f8:	4807      	ldr	r0, [pc, #28]	; (4318 <CC_PalTerminate+0x28>)
    42fa:	f000 f821 	bl	4340 <CC_PalMutexDestroy>
    42fe:	4807      	ldr	r0, [pc, #28]	; (431c <CC_PalTerminate+0x2c>)
    4300:	f000 f81e 	bl	4340 <CC_PalMutexDestroy>
    4304:	4806      	ldr	r0, [pc, #24]	; (4320 <CC_PalTerminate+0x30>)
    4306:	f000 f81b 	bl	4340 <CC_PalMutexDestroy>
    430a:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    430e:	f000 b80b 	b.w	4328 <CC_PalDmaTerminate>
    4312:	bf00      	nop
    4314:	2000003c 	.word	0x2000003c
    4318:	20000030 	.word	0x20000030
    431c:	20000038 	.word	0x20000038
    4320:	20000034 	.word	0x20000034

00004324 <CC_PalDmaInit>:
    4324:	2000      	movs	r0, #0
    4326:	4770      	bx	lr

00004328 <CC_PalDmaTerminate>:
    4328:	4770      	bx	lr
    432a:	bf00      	nop

0000432c <CC_PalMutexCreate>:
    432c:	b508      	push	{r3, lr}
    432e:	4b03      	ldr	r3, [pc, #12]	; (433c <CC_PalMutexCreate+0x10>)
    4330:	6802      	ldr	r2, [r0, #0]
    4332:	681b      	ldr	r3, [r3, #0]
    4334:	6810      	ldr	r0, [r2, #0]
    4336:	4798      	blx	r3
    4338:	2000      	movs	r0, #0
    433a:	bd08      	pop	{r3, pc}
    433c:	20000054 	.word	0x20000054

00004340 <CC_PalMutexDestroy>:
    4340:	b508      	push	{r3, lr}
    4342:	4b03      	ldr	r3, [pc, #12]	; (4350 <CC_PalMutexDestroy+0x10>)
    4344:	6802      	ldr	r2, [r0, #0]
    4346:	685b      	ldr	r3, [r3, #4]
    4348:	6810      	ldr	r0, [r2, #0]
    434a:	4798      	blx	r3
    434c:	2000      	movs	r0, #0
    434e:	bd08      	pop	{r3, pc}
    4350:	20000054 	.word	0x20000054

00004354 <CC_PalMutexLock>:
    4354:	4b02      	ldr	r3, [pc, #8]	; (4360 <CC_PalMutexLock+0xc>)
    4356:	6802      	ldr	r2, [r0, #0]
    4358:	689b      	ldr	r3, [r3, #8]
    435a:	6810      	ldr	r0, [r2, #0]
    435c:	4718      	bx	r3
    435e:	bf00      	nop
    4360:	20000054 	.word	0x20000054

00004364 <CC_PalMutexUnlock>:
    4364:	b508      	push	{r3, lr}
    4366:	4b03      	ldr	r3, [pc, #12]	; (4374 <CC_PalMutexUnlock+0x10>)
    4368:	6802      	ldr	r2, [r0, #0]
    436a:	68db      	ldr	r3, [r3, #12]
    436c:	6810      	ldr	r0, [r2, #0]
    436e:	4798      	blx	r3
    4370:	2000      	movs	r0, #0
    4372:	bd08      	pop	{r3, pc}
    4374:	20000054 	.word	0x20000054

00004378 <CC_PalPowerSaveModeInit>:
    4378:	b570      	push	{r4, r5, r6, lr}
    437a:	4c09      	ldr	r4, [pc, #36]	; (43a0 <CC_PalPowerSaveModeInit+0x28>)
    437c:	4d09      	ldr	r5, [pc, #36]	; (43a4 <CC_PalPowerSaveModeInit+0x2c>)
    437e:	6920      	ldr	r0, [r4, #16]
    4380:	68ab      	ldr	r3, [r5, #8]
    4382:	4798      	blx	r3
    4384:	b118      	cbz	r0, 438e <CC_PalPowerSaveModeInit+0x16>
    4386:	4b08      	ldr	r3, [pc, #32]	; (43a8 <CC_PalPowerSaveModeInit+0x30>)
    4388:	4808      	ldr	r0, [pc, #32]	; (43ac <CC_PalPowerSaveModeInit+0x34>)
    438a:	685b      	ldr	r3, [r3, #4]
    438c:	4798      	blx	r3
    438e:	2100      	movs	r1, #0
    4390:	4a07      	ldr	r2, [pc, #28]	; (43b0 <CC_PalPowerSaveModeInit+0x38>)
    4392:	68eb      	ldr	r3, [r5, #12]
    4394:	6011      	str	r1, [r2, #0]
    4396:	6920      	ldr	r0, [r4, #16]
    4398:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    439c:	4718      	bx	r3
    439e:	bf00      	nop
    43a0:	20000064 	.word	0x20000064
    43a4:	20000054 	.word	0x20000054
    43a8:	20000044 	.word	0x20000044
    43ac:	00006114 	.word	0x00006114
    43b0:	20000890 	.word	0x20000890

000043b4 <CC_PalPowerSaveModeSelect>:
    43b4:	b570      	push	{r4, r5, r6, lr}
    43b6:	4d1a      	ldr	r5, [pc, #104]	; (4420 <CC_PalPowerSaveModeSelect+0x6c>)
    43b8:	4e1a      	ldr	r6, [pc, #104]	; (4424 <CC_PalPowerSaveModeSelect+0x70>)
    43ba:	4604      	mov	r4, r0
    43bc:	68b2      	ldr	r2, [r6, #8]
    43be:	6928      	ldr	r0, [r5, #16]
    43c0:	4790      	blx	r2
    43c2:	b9f0      	cbnz	r0, 4402 <CC_PalPowerSaveModeSelect+0x4e>
    43c4:	b15c      	cbz	r4, 43de <CC_PalPowerSaveModeSelect+0x2a>
    43c6:	4c18      	ldr	r4, [pc, #96]	; (4428 <CC_PalPowerSaveModeSelect+0x74>)
    43c8:	6823      	ldr	r3, [r4, #0]
    43ca:	b1ab      	cbz	r3, 43f8 <CC_PalPowerSaveModeSelect+0x44>
    43cc:	2b01      	cmp	r3, #1
    43ce:	d01a      	beq.n	4406 <CC_PalPowerSaveModeSelect+0x52>
    43d0:	3b01      	subs	r3, #1
    43d2:	6023      	str	r3, [r4, #0]
    43d4:	6928      	ldr	r0, [r5, #16]
    43d6:	68f3      	ldr	r3, [r6, #12]
    43d8:	4798      	blx	r3
    43da:	2000      	movs	r0, #0
    43dc:	bd70      	pop	{r4, r5, r6, pc}
    43de:	4c12      	ldr	r4, [pc, #72]	; (4428 <CC_PalPowerSaveModeSelect+0x74>)
    43e0:	6821      	ldr	r1, [r4, #0]
    43e2:	b939      	cbnz	r1, 43f4 <CC_PalPowerSaveModeSelect+0x40>
    43e4:	2001      	movs	r0, #1
    43e6:	4b11      	ldr	r3, [pc, #68]	; (442c <CC_PalPowerSaveModeSelect+0x78>)
    43e8:	4a11      	ldr	r2, [pc, #68]	; (4430 <CC_PalPowerSaveModeSelect+0x7c>)
    43ea:	f8c3 0500 	str.w	r0, [r3, #1280]	; 0x500
    43ee:	6813      	ldr	r3, [r2, #0]
    43f0:	2b00      	cmp	r3, #0
    43f2:	d1fc      	bne.n	43ee <CC_PalPowerSaveModeSelect+0x3a>
    43f4:	3101      	adds	r1, #1
    43f6:	6021      	str	r1, [r4, #0]
    43f8:	68f3      	ldr	r3, [r6, #12]
    43fa:	6928      	ldr	r0, [r5, #16]
    43fc:	4798      	blx	r3
    43fe:	2000      	movs	r0, #0
    4400:	bd70      	pop	{r4, r5, r6, pc}
    4402:	480c      	ldr	r0, [pc, #48]	; (4434 <CC_PalPowerSaveModeSelect+0x80>)
    4404:	bd70      	pop	{r4, r5, r6, pc}
    4406:	4a0a      	ldr	r2, [pc, #40]	; (4430 <CC_PalPowerSaveModeSelect+0x7c>)
    4408:	6813      	ldr	r3, [r2, #0]
    440a:	2b00      	cmp	r3, #0
    440c:	d1fc      	bne.n	4408 <CC_PalPowerSaveModeSelect+0x54>
    440e:	4a07      	ldr	r2, [pc, #28]	; (442c <CC_PalPowerSaveModeSelect+0x78>)
    4410:	f06f 407e 	mvn.w	r0, #4261412864	; 0xfe000000
    4414:	f8c2 3500 	str.w	r3, [r2, #1280]	; 0x500
    4418:	f000 f820 	bl	445c <CC_HalMaskInterrupt>
    441c:	6823      	ldr	r3, [r4, #0]
    441e:	e7d7      	b.n	43d0 <CC_PalPowerSaveModeSelect+0x1c>
    4420:	20000064 	.word	0x20000064
    4424:	20000054 	.word	0x20000054
    4428:	20000890 	.word	0x20000890
    442c:	50840000 	.word	0x50840000
    4430:	50841910 	.word	0x50841910
    4434:	ffff8fe9 	.word	0xffff8fe9

00004438 <CC_HalInit>:
    4438:	2000      	movs	r0, #0
    443a:	4770      	bx	lr

0000443c <CC_HalTerminate>:
    443c:	2000      	movs	r0, #0
    443e:	4770      	bx	lr

00004440 <CC_HalClearInterruptBit>:
    4440:	0543      	lsls	r3, r0, #21
    4442:	d503      	bpl.n	444c <CC_HalClearInterruptBit+0xc>
    4444:	f04f 32ff 	mov.w	r2, #4294967295	; 0xffffffff
    4448:	4b02      	ldr	r3, [pc, #8]	; (4454 <CC_HalClearInterruptBit+0x14>)
    444a:	601a      	str	r2, [r3, #0]
    444c:	4b02      	ldr	r3, [pc, #8]	; (4458 <CC_HalClearInterruptBit+0x18>)
    444e:	6018      	str	r0, [r3, #0]
    4450:	4770      	bx	lr
    4452:	bf00      	nop
    4454:	50841108 	.word	0x50841108
    4458:	50841a08 	.word	0x50841a08

0000445c <CC_HalMaskInterrupt>:
    445c:	4b01      	ldr	r3, [pc, #4]	; (4464 <CC_HalMaskInterrupt+0x8>)
    445e:	6018      	str	r0, [r3, #0]
    4460:	4770      	bx	lr
    4462:	bf00      	nop
    4464:	50841a04 	.word	0x50841a04

00004468 <CC_HalWaitInterruptRND>:
    4468:	b108      	cbz	r0, 446e <CC_HalWaitInterruptRND+0x6>
    446a:	f000 b803 	b.w	4474 <CC_PalWaitInterruptRND>
    446e:	f44f 0075 	mov.w	r0, #16056320	; 0xf50000
    4472:	4770      	bx	lr

00004474 <CC_PalWaitInterruptRND>:
    4474:	4602      	mov	r2, r0
    4476:	4807      	ldr	r0, [pc, #28]	; (4494 <CC_PalWaitInterruptRND+0x20>)
    4478:	6803      	ldr	r3, [r0, #0]
    447a:	4213      	tst	r3, r2
    447c:	d0fc      	beq.n	4478 <CC_PalWaitInterruptRND+0x4>
    447e:	b121      	cbz	r1, 448a <CC_PalWaitInterruptRND+0x16>
    4480:	4b05      	ldr	r3, [pc, #20]	; (4498 <CC_PalWaitInterruptRND+0x24>)
    4482:	4806      	ldr	r0, [pc, #24]	; (449c <CC_PalWaitInterruptRND+0x28>)
    4484:	681b      	ldr	r3, [r3, #0]
    4486:	600b      	str	r3, [r1, #0]
    4488:	6003      	str	r3, [r0, #0]
    448a:	4b05      	ldr	r3, [pc, #20]	; (44a0 <CC_PalWaitInterruptRND+0x2c>)
    448c:	2000      	movs	r0, #0
    448e:	601a      	str	r2, [r3, #0]
    4490:	4770      	bx	lr
    4492:	bf00      	nop
    4494:	50841a00 	.word	0x50841a00
    4498:	50841104 	.word	0x50841104
    449c:	50841108 	.word	0x50841108
    44a0:	50841a08 	.word	0x50841a08

000044a4 <mbedtls_platform_setup>:
    44a4:	f000 b89e 	b.w	45e4 <nrf_cc3xx_platform_init>

000044a8 <mbedtls_platform_zeroize>:
    44a8:	b138      	cbz	r0, 44ba <mbedtls_platform_zeroize+0x12>
    44aa:	b131      	cbz	r1, 44ba <mbedtls_platform_zeroize+0x12>
    44ac:	2200      	movs	r2, #0
    44ae:	4401      	add	r1, r0
    44b0:	4603      	mov	r3, r0
    44b2:	3001      	adds	r0, #1
    44b4:	4281      	cmp	r1, r0
    44b6:	701a      	strb	r2, [r3, #0]
    44b8:	d1fa      	bne.n	44b0 <mbedtls_platform_zeroize+0x8>
    44ba:	4770      	bx	lr

000044bc <mbedtls_hardware_poll>:
    44bc:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    44c0:	f5ad 7d1a 	sub.w	sp, sp, #616	; 0x268
    44c4:	460e      	mov	r6, r1
    44c6:	9205      	str	r2, [sp, #20]
    44c8:	2100      	movs	r1, #0
    44ca:	4614      	mov	r4, r2
    44cc:	a812      	add	r0, sp, #72	; 0x48
    44ce:	f44f 7208 	mov.w	r2, #544	; 0x220
    44d2:	461d      	mov	r5, r3
    44d4:	f001 fa2b 	bl	592e <memset>
    44d8:	2100      	movs	r1, #0
    44da:	2228      	movs	r2, #40	; 0x28
    44dc:	a808      	add	r0, sp, #32
    44de:	9106      	str	r1, [sp, #24]
    44e0:	f001 fa25 	bl	592e <memset>
    44e4:	2e00      	cmp	r6, #0
    44e6:	d03c      	beq.n	4562 <mbedtls_hardware_poll+0xa6>
    44e8:	2d00      	cmp	r5, #0
    44ea:	d03a      	beq.n	4562 <mbedtls_hardware_poll+0xa6>
    44ec:	2c00      	cmp	r4, #0
    44ee:	d038      	beq.n	4562 <mbedtls_hardware_poll+0xa6>
    44f0:	2104      	movs	r1, #4
    44f2:	a806      	add	r0, sp, #24
    44f4:	f7ff feca 	bl	428c <CC_PalMemSetZeroPlat>
    44f8:	a808      	add	r0, sp, #32
    44fa:	2128      	movs	r1, #40	; 0x28
    44fc:	f7ff fec6 	bl	428c <CC_PalMemSetZeroPlat>
    4500:	a808      	add	r0, sp, #32
    4502:	f000 f831 	bl	4568 <RNG_PLAT_SetUserRngParameters>
    4506:	b178      	cbz	r0, 4528 <mbedtls_hardware_poll+0x6c>
    4508:	f04f 37ff 	mov.w	r7, #4294967295	; 0xffffffff
    450c:	f44f 7108 	mov.w	r1, #544	; 0x220
    4510:	a812      	add	r0, sp, #72	; 0x48
    4512:	f7ff ffc9 	bl	44a8 <mbedtls_platform_zeroize>
    4516:	2104      	movs	r1, #4
    4518:	a806      	add	r0, sp, #24
    451a:	f7ff ffc5 	bl	44a8 <mbedtls_platform_zeroize>
    451e:	4638      	mov	r0, r7
    4520:	f50d 7d1a 	add.w	sp, sp, #616	; 0x268
    4524:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    4528:	ab12      	add	r3, sp, #72	; 0x48
    452a:	f10d 081c 	add.w	r8, sp, #28
    452e:	4602      	mov	r2, r0
    4530:	e9cd 5301 	strd	r5, r3, [sp, #4]
    4534:	9003      	str	r0, [sp, #12]
    4536:	ab05      	add	r3, sp, #20
    4538:	a908      	add	r1, sp, #32
    453a:	f8cd 8000 	str.w	r8, [sp]
    453e:	a806      	add	r0, sp, #24
    4540:	f000 fd2a 	bl	4f98 <LLF_RND_GetTrngSource>
    4544:	2800      	cmp	r0, #0
    4546:	d1df      	bne.n	4508 <mbedtls_hardware_poll+0x4c>
    4548:	682b      	ldr	r3, [r5, #0]
    454a:	42a3      	cmp	r3, r4
    454c:	d3dc      	bcc.n	4508 <mbedtls_hardware_poll+0x4c>
    454e:	f8d8 1000 	ldr.w	r1, [r8]
    4552:	4607      	mov	r7, r0
    4554:	4622      	mov	r2, r4
    4556:	4630      	mov	r0, r6
    4558:	3108      	adds	r1, #8
    455a:	f7ff fe95 	bl	4288 <CC_PalMemCopyPlat>
    455e:	602c      	str	r4, [r5, #0]
    4560:	e7d4      	b.n	450c <mbedtls_hardware_poll+0x50>
    4562:	f04f 37ff 	mov.w	r7, #4294967295	; 0xffffffff
    4566:	e7da      	b.n	451e <mbedtls_hardware_poll+0x62>

00004568 <RNG_PLAT_SetUserRngParameters>:
    4568:	231c      	movs	r3, #28
    456a:	b530      	push	{r4, r5, lr}
    456c:	b083      	sub	sp, #12
    456e:	a901      	add	r1, sp, #4
    4570:	4604      	mov	r4, r0
    4572:	9301      	str	r3, [sp, #4]
    4574:	f000 f9e4 	bl	4940 <CC_PalTrngParamGet>
    4578:	4605      	mov	r5, r0
    457a:	b938      	cbnz	r0, 458c <RNG_PLAT_SetUserRngParameters+0x24>
    457c:	9b01      	ldr	r3, [sp, #4]
    457e:	2b1c      	cmp	r3, #28
    4580:	d007      	beq.n	4592 <RNG_PLAT_SetUserRngParameters+0x2a>
    4582:	4d16      	ldr	r5, [pc, #88]	; (45dc <RNG_PLAT_SetUserRngParameters+0x74>)
    4584:	4620      	mov	r0, r4
    4586:	211c      	movs	r1, #28
    4588:	f7ff fe80 	bl	428c <CC_PalMemSetZeroPlat>
    458c:	4628      	mov	r0, r5
    458e:	b003      	add	sp, #12
    4590:	bd30      	pop	{r4, r5, pc}
    4592:	2101      	movs	r1, #1
    4594:	e9d4 3200 	ldrd	r3, r2, [r4]
    4598:	3b00      	subs	r3, #0
    459a:	bf18      	it	ne
    459c:	2301      	movne	r3, #1
    459e:	61e1      	str	r1, [r4, #28]
    45a0:	b10a      	cbz	r2, 45a6 <RNG_PLAT_SetUserRngParameters+0x3e>
    45a2:	f043 0302 	orr.w	r3, r3, #2
    45a6:	68a2      	ldr	r2, [r4, #8]
    45a8:	b932      	cbnz	r2, 45b8 <RNG_PLAT_SetUserRngParameters+0x50>
    45aa:	68e2      	ldr	r2, [r4, #12]
    45ac:	b942      	cbnz	r2, 45c0 <RNG_PLAT_SetUserRngParameters+0x58>
    45ae:	e9c4 3208 	strd	r3, r2, [r4, #32]
    45b2:	b98b      	cbnz	r3, 45d8 <RNG_PLAT_SetUserRngParameters+0x70>
    45b4:	4d0a      	ldr	r5, [pc, #40]	; (45e0 <RNG_PLAT_SetUserRngParameters+0x78>)
    45b6:	e7e5      	b.n	4584 <RNG_PLAT_SetUserRngParameters+0x1c>
    45b8:	68e2      	ldr	r2, [r4, #12]
    45ba:	f043 0304 	orr.w	r3, r3, #4
    45be:	b13a      	cbz	r2, 45d0 <RNG_PLAT_SetUserRngParameters+0x68>
    45c0:	2200      	movs	r2, #0
    45c2:	4628      	mov	r0, r5
    45c4:	f043 0308 	orr.w	r3, r3, #8
    45c8:	e9c4 3208 	strd	r3, r2, [r4, #32]
    45cc:	b003      	add	sp, #12
    45ce:	bd30      	pop	{r4, r5, pc}
    45d0:	4615      	mov	r5, r2
    45d2:	e9c4 3208 	strd	r3, r2, [r4, #32]
    45d6:	e7d9      	b.n	458c <RNG_PLAT_SetUserRngParameters+0x24>
    45d8:	4615      	mov	r5, r2
    45da:	e7d7      	b.n	458c <RNG_PLAT_SetUserRngParameters+0x24>
    45dc:	00f00c37 	.word	0x00f00c37
    45e0:	00f00c0e 	.word	0x00f00c0e

000045e4 <nrf_cc3xx_platform_init>:
    45e4:	b510      	push	{r4, lr}
    45e6:	4c0c      	ldr	r4, [pc, #48]	; (4618 <nrf_cc3xx_platform_init+0x34>)
    45e8:	6823      	ldr	r3, [r4, #0]
    45ea:	b113      	cbz	r3, 45f2 <nrf_cc3xx_platform_init+0xe>
    45ec:	4b0b      	ldr	r3, [pc, #44]	; (461c <nrf_cc3xx_platform_init+0x38>)
    45ee:	681b      	ldr	r3, [r3, #0]
    45f0:	b92b      	cbnz	r3, 45fe <nrf_cc3xx_platform_init+0x1a>
    45f2:	f000 f965 	bl	48c0 <CC_LibInit>
    45f6:	b930      	cbnz	r0, 4606 <nrf_cc3xx_platform_init+0x22>
    45f8:	2201      	movs	r2, #1
    45fa:	4b08      	ldr	r3, [pc, #32]	; (461c <nrf_cc3xx_platform_init+0x38>)
    45fc:	601a      	str	r2, [r3, #0]
    45fe:	2301      	movs	r3, #1
    4600:	2000      	movs	r0, #0
    4602:	6023      	str	r3, [r4, #0]
    4604:	bd10      	pop	{r4, pc}
    4606:	3801      	subs	r0, #1
    4608:	2806      	cmp	r0, #6
    460a:	d901      	bls.n	4610 <nrf_cc3xx_platform_init+0x2c>
    460c:	4804      	ldr	r0, [pc, #16]	; (4620 <nrf_cc3xx_platform_init+0x3c>)
    460e:	bd10      	pop	{r4, pc}
    4610:	4b04      	ldr	r3, [pc, #16]	; (4624 <nrf_cc3xx_platform_init+0x40>)
    4612:	f853 0020 	ldr.w	r0, [r3, r0, lsl #2]
    4616:	bd10      	pop	{r4, pc}
    4618:	20000894 	.word	0x20000894
    461c:	20000898 	.word	0x20000898
    4620:	ffff8ffe 	.word	0xffff8ffe
    4624:	00006134 	.word	0x00006134

00004628 <nrf_cc3xx_platform_init_no_rng>:
    4628:	b510      	push	{r4, lr}
    462a:	4c0a      	ldr	r4, [pc, #40]	; (4654 <nrf_cc3xx_platform_init_no_rng+0x2c>)
    462c:	6823      	ldr	r3, [r4, #0]
    462e:	b11b      	cbz	r3, 4638 <nrf_cc3xx_platform_init_no_rng+0x10>
    4630:	2301      	movs	r3, #1
    4632:	2000      	movs	r0, #0
    4634:	6023      	str	r3, [r4, #0]
    4636:	bd10      	pop	{r4, pc}
    4638:	f000 f8ae 	bl	4798 <CC_LibInitNoRng>
    463c:	2800      	cmp	r0, #0
    463e:	d0f7      	beq.n	4630 <nrf_cc3xx_platform_init_no_rng+0x8>
    4640:	3801      	subs	r0, #1
    4642:	2806      	cmp	r0, #6
    4644:	d803      	bhi.n	464e <nrf_cc3xx_platform_init_no_rng+0x26>
    4646:	4b04      	ldr	r3, [pc, #16]	; (4658 <nrf_cc3xx_platform_init_no_rng+0x30>)
    4648:	f853 0020 	ldr.w	r0, [r3, r0, lsl #2]
    464c:	bd10      	pop	{r4, pc}
    464e:	4803      	ldr	r0, [pc, #12]	; (465c <nrf_cc3xx_platform_init_no_rng+0x34>)
    4650:	bd10      	pop	{r4, pc}
    4652:	bf00      	nop
    4654:	20000894 	.word	0x20000894
    4658:	00006134 	.word	0x00006134
    465c:	ffff8ffe 	.word	0xffff8ffe

00004660 <nrf_cc3xx_platform_abort>:
    4660:	f3bf 8f4f 	dsb	sy
    4664:	4905      	ldr	r1, [pc, #20]	; (467c <nrf_cc3xx_platform_abort+0x1c>)
    4666:	4b06      	ldr	r3, [pc, #24]	; (4680 <nrf_cc3xx_platform_abort+0x20>)
    4668:	68ca      	ldr	r2, [r1, #12]
    466a:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    466e:	4313      	orrs	r3, r2
    4670:	60cb      	str	r3, [r1, #12]
    4672:	f3bf 8f4f 	dsb	sy
    4676:	bf00      	nop
    4678:	e7fd      	b.n	4676 <nrf_cc3xx_platform_abort+0x16>
    467a:	bf00      	nop
    467c:	e000ed00 	.word	0xe000ed00
    4680:	05fa0004 	.word	0x05fa0004

00004684 <CC_PalAbort>:
    4684:	f04f 33fe 	mov.w	r3, #4278124286	; 0xfefefefe
    4688:	2100      	movs	r1, #0
    468a:	b430      	push	{r4, r5}
    468c:	4a06      	ldr	r2, [pc, #24]	; (46a8 <CC_PalAbort+0x24>)
    468e:	4d07      	ldr	r5, [pc, #28]	; (46ac <CC_PalAbort+0x28>)
    4690:	4c07      	ldr	r4, [pc, #28]	; (46b0 <CC_PalAbort+0x2c>)
    4692:	602b      	str	r3, [r5, #0]
    4694:	6013      	str	r3, [r2, #0]
    4696:	6023      	str	r3, [r4, #0]
    4698:	4a06      	ldr	r2, [pc, #24]	; (46b4 <CC_PalAbort+0x30>)
    469a:	4c07      	ldr	r4, [pc, #28]	; (46b8 <CC_PalAbort+0x34>)
    469c:	60eb      	str	r3, [r5, #12]
    469e:	6863      	ldr	r3, [r4, #4]
    46a0:	f8c2 1500 	str.w	r1, [r2, #1280]	; 0x500
    46a4:	bc30      	pop	{r4, r5}
    46a6:	4718      	bx	r3
    46a8:	50841404 	.word	0x50841404
    46ac:	50841400 	.word	0x50841400
    46b0:	50841408 	.word	0x50841408
    46b4:	50840000 	.word	0x50840000
    46b8:	20000044 	.word	0x20000044

000046bc <nrf_cc3xx_platform_set_abort>:
    46bc:	4b02      	ldr	r3, [pc, #8]	; (46c8 <nrf_cc3xx_platform_set_abort+0xc>)
    46be:	e9d0 1200 	ldrd	r1, r2, [r0]
    46c2:	e9c3 1200 	strd	r1, r2, [r3]
    46c6:	4770      	bx	lr
    46c8:	20000044 	.word	0x20000044

000046cc <mutex_unlock>:
    46cc:	b148      	cbz	r0, 46e2 <mutex_unlock+0x16>
    46ce:	6843      	ldr	r3, [r0, #4]
    46d0:	b12b      	cbz	r3, 46de <mutex_unlock+0x12>
    46d2:	f3bf 8f5f 	dmb	sy
    46d6:	2300      	movs	r3, #0
    46d8:	6003      	str	r3, [r0, #0]
    46da:	4618      	mov	r0, r3
    46dc:	4770      	bx	lr
    46de:	4802      	ldr	r0, [pc, #8]	; (46e8 <mutex_unlock+0x1c>)
    46e0:	4770      	bx	lr
    46e2:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    46e6:	4770      	bx	lr
    46e8:	ffff8fea 	.word	0xffff8fea

000046ec <mutex_free>:
    46ec:	b510      	push	{r4, lr}
    46ee:	4604      	mov	r4, r0
    46f0:	b128      	cbz	r0, 46fe <mutex_free+0x12>
    46f2:	6863      	ldr	r3, [r4, #4]
    46f4:	b113      	cbz	r3, 46fc <mutex_free+0x10>
    46f6:	2300      	movs	r3, #0
    46f8:	6023      	str	r3, [r4, #0]
    46fa:	6063      	str	r3, [r4, #4]
    46fc:	bd10      	pop	{r4, pc}
    46fe:	4b02      	ldr	r3, [pc, #8]	; (4708 <mutex_free+0x1c>)
    4700:	4802      	ldr	r0, [pc, #8]	; (470c <mutex_free+0x20>)
    4702:	685b      	ldr	r3, [r3, #4]
    4704:	4798      	blx	r3
    4706:	e7f4      	b.n	46f2 <mutex_free+0x6>
    4708:	20000044 	.word	0x20000044
    470c:	00006150 	.word	0x00006150

00004710 <mutex_init>:
    4710:	b510      	push	{r4, lr}
    4712:	4604      	mov	r4, r0
    4714:	b130      	cbz	r0, 4724 <mutex_init+0x14>
    4716:	2200      	movs	r2, #0
    4718:	6863      	ldr	r3, [r4, #4]
    471a:	6022      	str	r2, [r4, #0]
    471c:	f043 0301 	orr.w	r3, r3, #1
    4720:	6063      	str	r3, [r4, #4]
    4722:	bd10      	pop	{r4, pc}
    4724:	4801      	ldr	r0, [pc, #4]	; (472c <mutex_init+0x1c>)
    4726:	f7ff ffad 	bl	4684 <CC_PalAbort>
    472a:	e7f4      	b.n	4716 <mutex_init+0x6>
    472c:	00006178 	.word	0x00006178

00004730 <mutex_lock>:
    4730:	b180      	cbz	r0, 4754 <mutex_lock+0x24>
    4732:	6843      	ldr	r3, [r0, #4]
    4734:	b163      	cbz	r3, 4750 <mutex_lock+0x20>
    4736:	2201      	movs	r2, #1
    4738:	e8d0 3fef 	ldaex	r3, [r0]
    473c:	e8c0 2fe1 	stlex	r1, r2, [r0]
    4740:	2900      	cmp	r1, #0
    4742:	d1f9      	bne.n	4738 <mutex_lock+0x8>
    4744:	2b01      	cmp	r3, #1
    4746:	d0f7      	beq.n	4738 <mutex_lock+0x8>
    4748:	f3bf 8f5f 	dmb	sy
    474c:	2000      	movs	r0, #0
    474e:	4770      	bx	lr
    4750:	4802      	ldr	r0, [pc, #8]	; (475c <mutex_lock+0x2c>)
    4752:	4770      	bx	lr
    4754:	f46f 40e0 	mvn.w	r0, #28672	; 0x7000
    4758:	4770      	bx	lr
    475a:	bf00      	nop
    475c:	ffff8fea 	.word	0xffff8fea

00004760 <nrf_cc3xx_platform_set_mutexes>:
    4760:	b470      	push	{r4, r5, r6}
    4762:	4b0b      	ldr	r3, [pc, #44]	; (4790 <nrf_cc3xx_platform_set_mutexes+0x30>)
    4764:	6806      	ldr	r6, [r0, #0]
    4766:	68c2      	ldr	r2, [r0, #12]
    4768:	e9d0 5401 	ldrd	r5, r4, [r0, #4]
    476c:	e9c3 4202 	strd	r4, r2, [r3, #8]
    4770:	e9c3 6500 	strd	r6, r5, [r3]
    4774:	e9d1 0203 	ldrd	r0, r2, [r1, #12]
    4778:	680e      	ldr	r6, [r1, #0]
    477a:	4b06      	ldr	r3, [pc, #24]	; (4794 <nrf_cc3xx_platform_set_mutexes+0x34>)
    477c:	e9d1 5401 	ldrd	r5, r4, [r1, #4]
    4780:	e9c3 6500 	strd	r6, r5, [r3]
    4784:	e9c3 4002 	strd	r4, r0, [r3, #8]
    4788:	611a      	str	r2, [r3, #16]
    478a:	bc70      	pop	{r4, r5, r6}
    478c:	4770      	bx	lr
    478e:	bf00      	nop
    4790:	20000054 	.word	0x20000054
    4794:	20000064 	.word	0x20000064

00004798 <CC_LibInitNoRng>:
    4798:	b510      	push	{r4, lr}
    479a:	f7ff fe4d 	bl	4438 <CC_HalInit>
    479e:	b120      	cbz	r0, 47aa <CC_LibInitNoRng+0x12>
    47a0:	2403      	movs	r4, #3
    47a2:	f7ff fda5 	bl	42f0 <CC_PalTerminate>
    47a6:	4620      	mov	r0, r4
    47a8:	bd10      	pop	{r4, pc}
    47aa:	f7ff fd73 	bl	4294 <CC_PalInit>
    47ae:	b990      	cbnz	r0, 47d6 <CC_LibInitNoRng+0x3e>
    47b0:	f7ff fe00 	bl	43b4 <CC_PalPowerSaveModeSelect>
    47b4:	b990      	cbnz	r0, 47dc <CC_LibInitNoRng+0x44>
    47b6:	4b0f      	ldr	r3, [pc, #60]	; (47f4 <CC_LibInitNoRng+0x5c>)
    47b8:	681b      	ldr	r3, [r3, #0]
    47ba:	0e1b      	lsrs	r3, r3, #24
    47bc:	2bf0      	cmp	r3, #240	; 0xf0
    47be:	d108      	bne.n	47d2 <CC_LibInitNoRng+0x3a>
    47c0:	4a0d      	ldr	r2, [pc, #52]	; (47f8 <CC_LibInitNoRng+0x60>)
    47c2:	4b0e      	ldr	r3, [pc, #56]	; (47fc <CC_LibInitNoRng+0x64>)
    47c4:	6812      	ldr	r2, [r2, #0]
    47c6:	429a      	cmp	r2, r3
    47c8:	d00a      	beq.n	47e0 <CC_LibInitNoRng+0x48>
    47ca:	2407      	movs	r4, #7
    47cc:	f7ff fe36 	bl	443c <CC_HalTerminate>
    47d0:	e7e7      	b.n	47a2 <CC_LibInitNoRng+0xa>
    47d2:	2406      	movs	r4, #6
    47d4:	e7fa      	b.n	47cc <CC_LibInitNoRng+0x34>
    47d6:	2404      	movs	r4, #4
    47d8:	4620      	mov	r0, r4
    47da:	bd10      	pop	{r4, pc}
    47dc:	2400      	movs	r4, #0
    47de:	e7f5      	b.n	47cc <CC_LibInitNoRng+0x34>
    47e0:	2001      	movs	r0, #1
    47e2:	f7ff fde7 	bl	43b4 <CC_PalPowerSaveModeSelect>
    47e6:	4604      	mov	r4, r0
    47e8:	2800      	cmp	r0, #0
    47ea:	d1f7      	bne.n	47dc <CC_LibInitNoRng+0x44>
    47ec:	4b04      	ldr	r3, [pc, #16]	; (4800 <CC_LibInitNoRng+0x68>)
    47ee:	6018      	str	r0, [r3, #0]
    47f0:	e7d9      	b.n	47a6 <CC_LibInitNoRng+0xe>
    47f2:	bf00      	nop
    47f4:	50841928 	.word	0x50841928
    47f8:	50841a24 	.word	0x50841a24
    47fc:	20e00000 	.word	0x20e00000
    4800:	50841a0c 	.word	0x50841a0c

00004804 <CC_LibInitRngModule>:
    4804:	b530      	push	{r4, r5, lr}
    4806:	f5ad 7d15 	sub.w	sp, sp, #596	; 0x254
    480a:	f44f 7208 	mov.w	r2, #544	; 0x220
    480e:	2100      	movs	r1, #0
    4810:	a80c      	add	r0, sp, #48	; 0x30
    4812:	f001 f88c 	bl	592e <memset>
    4816:	2100      	movs	r1, #0
    4818:	2228      	movs	r2, #40	; 0x28
    481a:	a802      	add	r0, sp, #8
    481c:	9101      	str	r1, [sp, #4]
    481e:	f001 f886 	bl	592e <memset>
    4822:	a802      	add	r0, sp, #8
    4824:	f7ff fea0 	bl	4568 <RNG_PLAT_SetUserRngParameters>
    4828:	b120      	cbz	r0, 4834 <CC_LibInitRngModule+0x30>
    482a:	2405      	movs	r4, #5
    482c:	4620      	mov	r0, r4
    482e:	f50d 7d15 	add.w	sp, sp, #596	; 0x254
    4832:	bd30      	pop	{r4, r5, pc}
    4834:	4d1d      	ldr	r5, [pc, #116]	; (48ac <CC_LibInitRngModule+0xa8>)
    4836:	f04f 31ff 	mov.w	r1, #4294967295	; 0xffffffff
    483a:	6828      	ldr	r0, [r5, #0]
    483c:	f7ff fd8a 	bl	4354 <CC_PalMutexLock>
    4840:	4604      	mov	r4, r0
    4842:	b9e8      	cbnz	r0, 4880 <CC_LibInitRngModule+0x7c>
    4844:	2000      	movs	r0, #0
    4846:	f7ff fdb5 	bl	43b4 <CC_PalPowerSaveModeSelect>
    484a:	bb58      	cbnz	r0, 48a4 <CC_LibInitRngModule+0xa0>
    484c:	aa0c      	add	r2, sp, #48	; 0x30
    484e:	a902      	add	r1, sp, #8
    4850:	a801      	add	r0, sp, #4
    4852:	f000 fbed 	bl	5030 <LLF_RND_RunTrngStartupTest>
    4856:	4604      	mov	r4, r0
    4858:	2001      	movs	r0, #1
    485a:	f7ff fdab 	bl	43b4 <CC_PalPowerSaveModeSelect>
    485e:	b9e8      	cbnz	r0, 489c <CC_LibInitRngModule+0x98>
    4860:	6828      	ldr	r0, [r5, #0]
    4862:	f7ff fd7f 	bl	4364 <CC_PalMutexUnlock>
    4866:	b928      	cbnz	r0, 4874 <CC_LibInitRngModule+0x70>
    4868:	2c00      	cmp	r4, #0
    486a:	d1de      	bne.n	482a <CC_LibInitRngModule+0x26>
    486c:	4620      	mov	r0, r4
    486e:	f50d 7d15 	add.w	sp, sp, #596	; 0x254
    4872:	bd30      	pop	{r4, r5, pc}
    4874:	480e      	ldr	r0, [pc, #56]	; (48b0 <CC_LibInitRngModule+0xac>)
    4876:	f7ff ff05 	bl	4684 <CC_PalAbort>
    487a:	2c00      	cmp	r4, #0
    487c:	d0f6      	beq.n	486c <CC_LibInitRngModule+0x68>
    487e:	e7d4      	b.n	482a <CC_LibInitRngModule+0x26>
    4880:	480c      	ldr	r0, [pc, #48]	; (48b4 <CC_LibInitRngModule+0xb0>)
    4882:	f7ff feff 	bl	4684 <CC_PalAbort>
    4886:	2c01      	cmp	r4, #1
    4888:	d1dc      	bne.n	4844 <CC_LibInitRngModule+0x40>
    488a:	6828      	ldr	r0, [r5, #0]
    488c:	f7ff fd6a 	bl	4364 <CC_PalMutexUnlock>
    4890:	2800      	cmp	r0, #0
    4892:	d0ca      	beq.n	482a <CC_LibInitRngModule+0x26>
    4894:	4806      	ldr	r0, [pc, #24]	; (48b0 <CC_LibInitRngModule+0xac>)
    4896:	f7ff fef5 	bl	4684 <CC_PalAbort>
    489a:	e7c6      	b.n	482a <CC_LibInitRngModule+0x26>
    489c:	4806      	ldr	r0, [pc, #24]	; (48b8 <CC_LibInitRngModule+0xb4>)
    489e:	f7ff fef1 	bl	4684 <CC_PalAbort>
    48a2:	e7dd      	b.n	4860 <CC_LibInitRngModule+0x5c>
    48a4:	4805      	ldr	r0, [pc, #20]	; (48bc <CC_LibInitRngModule+0xb8>)
    48a6:	f7ff feed 	bl	4684 <CC_PalAbort>
    48aa:	e7cf      	b.n	484c <CC_LibInitRngModule+0x48>
    48ac:	20000040 	.word	0x20000040
    48b0:	000061b4 	.word	0x000061b4
    48b4:	0000619c 	.word	0x0000619c
    48b8:	000061ec 	.word	0x000061ec
    48bc:	000061cc 	.word	0x000061cc

000048c0 <CC_LibInit>:
    48c0:	b508      	push	{r3, lr}
    48c2:	f7ff fdb9 	bl	4438 <CC_HalInit>
    48c6:	b118      	cbz	r0, 48d0 <CC_LibInit+0x10>
    48c8:	f7ff fd12 	bl	42f0 <CC_PalTerminate>
    48cc:	2003      	movs	r0, #3
    48ce:	bd08      	pop	{r3, pc}
    48d0:	f7ff fce0 	bl	4294 <CC_PalInit>
    48d4:	b9c0      	cbnz	r0, 4908 <CC_LibInit+0x48>
    48d6:	f7ff fd6d 	bl	43b4 <CC_PalPowerSaveModeSelect>
    48da:	b9b8      	cbnz	r0, 490c <CC_LibInit+0x4c>
    48dc:	4b14      	ldr	r3, [pc, #80]	; (4930 <CC_LibInit+0x70>)
    48de:	681b      	ldr	r3, [r3, #0]
    48e0:	0e1b      	lsrs	r3, r3, #24
    48e2:	2bf0      	cmp	r3, #240	; 0xf0
    48e4:	d10a      	bne.n	48fc <CC_LibInit+0x3c>
    48e6:	4a13      	ldr	r2, [pc, #76]	; (4934 <CC_LibInit+0x74>)
    48e8:	4b13      	ldr	r3, [pc, #76]	; (4938 <CC_LibInit+0x78>)
    48ea:	6812      	ldr	r2, [r2, #0]
    48ec:	429a      	cmp	r2, r3
    48ee:	d017      	beq.n	4920 <CC_LibInit+0x60>
    48f0:	f7ff fda4 	bl	443c <CC_HalTerminate>
    48f4:	f7ff fcfc 	bl	42f0 <CC_PalTerminate>
    48f8:	2007      	movs	r0, #7
    48fa:	bd08      	pop	{r3, pc}
    48fc:	f7ff fd9e 	bl	443c <CC_HalTerminate>
    4900:	f7ff fcf6 	bl	42f0 <CC_PalTerminate>
    4904:	2006      	movs	r0, #6
    4906:	bd08      	pop	{r3, pc}
    4908:	2004      	movs	r0, #4
    490a:	bd08      	pop	{r3, pc}
    490c:	f7ff fd96 	bl	443c <CC_HalTerminate>
    4910:	f7ff fcee 	bl	42f0 <CC_PalTerminate>
    4914:	f7ff ff76 	bl	4804 <CC_LibInitRngModule>
    4918:	2800      	cmp	r0, #0
    491a:	bf18      	it	ne
    491c:	2005      	movne	r0, #5
    491e:	bd08      	pop	{r3, pc}
    4920:	2001      	movs	r0, #1
    4922:	f7ff fd47 	bl	43b4 <CC_PalPowerSaveModeSelect>
    4926:	2800      	cmp	r0, #0
    4928:	d1f0      	bne.n	490c <CC_LibInit+0x4c>
    492a:	4b04      	ldr	r3, [pc, #16]	; (493c <CC_LibInit+0x7c>)
    492c:	6018      	str	r0, [r3, #0]
    492e:	e7f1      	b.n	4914 <CC_LibInit+0x54>
    4930:	50841928 	.word	0x50841928
    4934:	50841a24 	.word	0x50841a24
    4938:	20e00000 	.word	0x20e00000
    493c:	50841a0c 	.word	0x50841a0c

00004940 <CC_PalTrngParamGet>:
    4940:	2800      	cmp	r0, #0
    4942:	d066      	beq.n	4a12 <CC_PalTrngParamGet+0xd2>
    4944:	2900      	cmp	r1, #0
    4946:	d064      	beq.n	4a12 <CC_PalTrngParamGet+0xd2>
    4948:	680b      	ldr	r3, [r1, #0]
    494a:	2b1c      	cmp	r3, #28
    494c:	d161      	bne.n	4a12 <CC_PalTrngParamGet+0xd2>
    494e:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    4952:	4a3b      	ldr	r2, [pc, #236]	; (4a40 <CC_PalTrngParamGet+0x100>)
    4954:	f8d3 1c10 	ldr.w	r1, [r3, #3088]	; 0xc10
    4958:	4291      	cmp	r1, r2
    495a:	d05c      	beq.n	4a16 <CC_PalTrngParamGet+0xd6>
    495c:	f8d3 2c10 	ldr.w	r2, [r3, #3088]	; 0xc10
    4960:	3201      	adds	r2, #1
    4962:	d058      	beq.n	4a16 <CC_PalTrngParamGet+0xd6>
    4964:	f8d3 2c10 	ldr.w	r2, [r3, #3088]	; 0xc10
    4968:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    496c:	6002      	str	r2, [r0, #0]
    496e:	f8d3 1c14 	ldr.w	r1, [r3, #3092]	; 0xc14
    4972:	4a34      	ldr	r2, [pc, #208]	; (4a44 <CC_PalTrngParamGet+0x104>)
    4974:	4291      	cmp	r1, r2
    4976:	d060      	beq.n	4a3a <CC_PalTrngParamGet+0xfa>
    4978:	f8d3 2c14 	ldr.w	r2, [r3, #3092]	; 0xc14
    497c:	3201      	adds	r2, #1
    497e:	d05c      	beq.n	4a3a <CC_PalTrngParamGet+0xfa>
    4980:	f8d3 2c14 	ldr.w	r2, [r3, #3092]	; 0xc14
    4984:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    4988:	6042      	str	r2, [r0, #4]
    498a:	f8d3 2c18 	ldr.w	r2, [r3, #3096]	; 0xc18
    498e:	f512 7f94 	cmn.w	r2, #296	; 0x128
    4992:	d04f      	beq.n	4a34 <CC_PalTrngParamGet+0xf4>
    4994:	f8d3 2c18 	ldr.w	r2, [r3, #3096]	; 0xc18
    4998:	3201      	adds	r2, #1
    499a:	d04b      	beq.n	4a34 <CC_PalTrngParamGet+0xf4>
    499c:	f8d3 2c18 	ldr.w	r2, [r3, #3096]	; 0xc18
    49a0:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    49a4:	6082      	str	r2, [r0, #8]
    49a6:	f8d3 1c1c 	ldr.w	r1, [r3, #3100]	; 0xc1c
    49aa:	4a27      	ldr	r2, [pc, #156]	; (4a48 <CC_PalTrngParamGet+0x108>)
    49ac:	4291      	cmp	r1, r2
    49ae:	d03e      	beq.n	4a2e <CC_PalTrngParamGet+0xee>
    49b0:	f8d3 2c1c 	ldr.w	r2, [r3, #3100]	; 0xc1c
    49b4:	3201      	adds	r2, #1
    49b6:	d03a      	beq.n	4a2e <CC_PalTrngParamGet+0xee>
    49b8:	f8d3 2c1c 	ldr.w	r2, [r3, #3100]	; 0xc1c
    49bc:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    49c0:	60c2      	str	r2, [r0, #12]
    49c2:	f8d3 2c00 	ldr.w	r2, [r3, #3072]	; 0xc00
    49c6:	3270      	adds	r2, #112	; 0x70
    49c8:	d02f      	beq.n	4a2a <CC_PalTrngParamGet+0xea>
    49ca:	f8d3 2c00 	ldr.w	r2, [r3, #3072]	; 0xc00
    49ce:	3201      	adds	r2, #1
    49d0:	d02b      	beq.n	4a2a <CC_PalTrngParamGet+0xea>
    49d2:	f8d3 2c00 	ldr.w	r2, [r3, #3072]	; 0xc00
    49d6:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    49da:	6102      	str	r2, [r0, #16]
    49dc:	f8d3 2c04 	ldr.w	r2, [r3, #3076]	; 0xc04
    49e0:	32af      	adds	r2, #175	; 0xaf
    49e2:	d020      	beq.n	4a26 <CC_PalTrngParamGet+0xe6>
    49e4:	f8d3 2c04 	ldr.w	r2, [r3, #3076]	; 0xc04
    49e8:	3201      	adds	r2, #1
    49ea:	d01c      	beq.n	4a26 <CC_PalTrngParamGet+0xe6>
    49ec:	f8d3 2c04 	ldr.w	r2, [r3, #3076]	; 0xc04
    49f0:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    49f4:	6142      	str	r2, [r0, #20]
    49f6:	f8d3 1c08 	ldr.w	r1, [r3, #3080]	; 0xc08
    49fa:	4a14      	ldr	r2, [pc, #80]	; (4a4c <CC_PalTrngParamGet+0x10c>)
    49fc:	4291      	cmp	r1, r2
    49fe:	d00d      	beq.n	4a1c <CC_PalTrngParamGet+0xdc>
    4a00:	f8d3 2c08 	ldr.w	r2, [r3, #3080]	; 0xc08
    4a04:	3201      	adds	r2, #1
    4a06:	d009      	beq.n	4a1c <CC_PalTrngParamGet+0xdc>
    4a08:	f8d3 3c08 	ldr.w	r3, [r3, #3080]	; 0xc08
    4a0c:	6183      	str	r3, [r0, #24]
    4a0e:	2000      	movs	r0, #0
    4a10:	4770      	bx	lr
    4a12:	2001      	movs	r0, #1
    4a14:	4770      	bx	lr
    4a16:	f640 02fc 	movw	r2, #2300	; 0x8fc
    4a1a:	e7a5      	b.n	4968 <CC_PalTrngParamGet+0x28>
    4a1c:	f240 3337 	movw	r3, #823	; 0x337
    4a20:	6183      	str	r3, [r0, #24]
    4a22:	2000      	movs	r0, #0
    4a24:	4770      	bx	lr
    4a26:	2251      	movs	r2, #81	; 0x51
    4a28:	e7e2      	b.n	49f0 <CC_PalTrngParamGet+0xb0>
    4a2a:	2290      	movs	r2, #144	; 0x90
    4a2c:	e7d3      	b.n	49d6 <CC_PalTrngParamGet+0x96>
    4a2e:	f642 1204 	movw	r2, #10500	; 0x2904
    4a32:	e7c3      	b.n	49bc <CC_PalTrngParamGet+0x7c>
    4a34:	f640 62d8 	movw	r2, #3800	; 0xed8
    4a38:	e7b2      	b.n	49a0 <CC_PalTrngParamGet+0x60>
    4a3a:	f242 02d0 	movw	r2, #8400	; 0x20d0
    4a3e:	e7a1      	b.n	4984 <CC_PalTrngParamGet+0x44>
    4a40:	fffff8fc 	.word	0xfffff8fc
    4a44:	ffff20d0 	.word	0xffff20d0
    4a48:	ffff2904 	.word	0xffff2904
    4a4c:	fffff337 	.word	0xfffff337

00004a50 <startTrngHW>:
    4a50:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    4a54:	2800      	cmp	r0, #0
    4a56:	d077      	beq.n	4b48 <startTrngHW+0xf8>
    4a58:	460c      	mov	r4, r1
    4a5a:	2900      	cmp	r1, #0
    4a5c:	d074      	beq.n	4b48 <startTrngHW+0xf8>
    4a5e:	461d      	mov	r5, r3
    4a60:	2b00      	cmp	r3, #0
    4a62:	d071      	beq.n	4b48 <startTrngHW+0xf8>
    4a64:	4606      	mov	r6, r0
    4a66:	b11a      	cbz	r2, 4a70 <startTrngHW+0x20>
    4a68:	2201      	movs	r2, #1
    4a6a:	2300      	movs	r3, #0
    4a6c:	602a      	str	r2, [r5, #0]
    4a6e:	6003      	str	r3, [r0, #0]
    4a70:	682b      	ldr	r3, [r5, #0]
    4a72:	2b00      	cmp	r3, #0
    4a74:	d064      	beq.n	4b40 <startTrngHW+0xf0>
    4a76:	4629      	mov	r1, r5
    4a78:	4620      	mov	r0, r4
    4a7a:	f000 fb15 	bl	50a8 <LLF_RND_GetFastestRosc>
    4a7e:	4607      	mov	r7, r0
    4a80:	2800      	cmp	r0, #0
    4a82:	d15e      	bne.n	4b42 <startTrngHW+0xf2>
    4a84:	4621      	mov	r1, r4
    4a86:	6828      	ldr	r0, [r5, #0]
    4a88:	f000 faf0 	bl	506c <LLF_RND_GetRoscSampleCnt>
    4a8c:	4607      	mov	r7, r0
    4a8e:	2800      	cmp	r0, #0
    4a90:	d157      	bne.n	4b42 <startTrngHW+0xf2>
    4a92:	682b      	ldr	r3, [r5, #0]
    4a94:	2b08      	cmp	r3, #8
    4a96:	d066      	beq.n	4b66 <startTrngHW+0x116>
    4a98:	2b04      	cmp	r3, #4
    4a9a:	d067      	beq.n	4b6c <startTrngHW+0x11c>
    4a9c:	f1a3 0802 	sub.w	r8, r3, #2
    4aa0:	fab8 f888 	clz	r8, r8
    4aa4:	ea4f 1858 	mov.w	r8, r8, lsr #5
    4aa8:	2301      	movs	r3, #1
    4aaa:	469c      	mov	ip, r3
    4aac:	4a31      	ldr	r2, [pc, #196]	; (4b74 <startTrngHW+0x124>)
    4aae:	4932      	ldr	r1, [pc, #200]	; (4b78 <startTrngHW+0x128>)
    4ab0:	6013      	str	r3, [r2, #0]
    4ab2:	4610      	mov	r0, r2
    4ab4:	600b      	str	r3, [r1, #0]
    4ab6:	3a94      	subs	r2, #148	; 0x94
    4ab8:	f8c0 c000 	str.w	ip, [r0]
    4abc:	6a63      	ldr	r3, [r4, #36]	; 0x24
    4abe:	6013      	str	r3, [r2, #0]
    4ac0:	6811      	ldr	r1, [r2, #0]
    4ac2:	428b      	cmp	r3, r1
    4ac4:	d1f8      	bne.n	4ab8 <startTrngHW+0x68>
    4ac6:	f04f 0900 	mov.w	r9, #0
    4aca:	4b2c      	ldr	r3, [pc, #176]	; (4b7c <startTrngHW+0x12c>)
    4acc:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
    4ad0:	f8c3 9000 	str.w	r9, [r3]
    4ad4:	f7ff fcb4 	bl	4440 <CC_HalClearInterruptBit>
    4ad8:	4b29      	ldr	r3, [pc, #164]	; (4b80 <startTrngHW+0x130>)
    4ada:	4a2a      	ldr	r2, [pc, #168]	; (4b84 <startTrngHW+0x134>)
    4adc:	4648      	mov	r0, r9
    4ade:	601a      	str	r2, [r3, #0]
    4ae0:	f7ff fcbc 	bl	445c <CC_HalMaskInterrupt>
    4ae4:	4a28      	ldr	r2, [pc, #160]	; (4b88 <startTrngHW+0x138>)
    4ae6:	4b29      	ldr	r3, [pc, #164]	; (4b8c <startTrngHW+0x13c>)
    4ae8:	f8c2 8000 	str.w	r8, [r2]
    4aec:	6818      	ldr	r0, [r3, #0]
    4aee:	f440 6080 	orr.w	r0, r0, #1024	; 0x400
    4af2:	f7ff fcb3 	bl	445c <CC_HalMaskInterrupt>
    4af6:	220a      	movs	r2, #10
    4af8:	4b25      	ldr	r3, [pc, #148]	; (4b90 <startTrngHW+0x140>)
    4afa:	601a      	str	r2, [r3, #0]
    4afc:	9a08      	ldr	r2, [sp, #32]
    4afe:	6923      	ldr	r3, [r4, #16]
    4b00:	2a01      	cmp	r2, #1
    4b02:	6a61      	ldr	r1, [r4, #36]	; 0x24
    4b04:	d024      	beq.n	4b50 <startTrngHW+0x100>
    4b06:	4a23      	ldr	r2, [pc, #140]	; (4b94 <startTrngHW+0x144>)
    4b08:	fba2 2303 	umull	r2, r3, r2, r3
    4b0c:	091b      	lsrs	r3, r3, #4
    4b0e:	2201      	movs	r2, #1
    4b10:	fb03 f301 	mul.w	r3, r3, r1
    4b14:	eb03 0343 	add.w	r3, r3, r3, lsl #1
    4b18:	491f      	ldr	r1, [pc, #124]	; (4b98 <startTrngHW+0x148>)
    4b1a:	03db      	lsls	r3, r3, #15
    4b1c:	099b      	lsrs	r3, r3, #6
    4b1e:	600b      	str	r3, [r1, #0]
    4b20:	4b16      	ldr	r3, [pc, #88]	; (4b7c <startTrngHW+0x12c>)
    4b22:	4638      	mov	r0, r7
    4b24:	601a      	str	r2, [r3, #0]
    4b26:	6833      	ldr	r3, [r6, #0]
    4b28:	682a      	ldr	r2, [r5, #0]
    4b2a:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
    4b2e:	ea43 6302 	orr.w	r3, r3, r2, lsl #24
    4b32:	6033      	str	r3, [r6, #0]
    4b34:	682a      	ldr	r2, [r5, #0]
    4b36:	ea43 2302 	orr.w	r3, r3, r2, lsl #8
    4b3a:	6033      	str	r3, [r6, #0]
    4b3c:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
    4b40:	4f16      	ldr	r7, [pc, #88]	; (4b9c <startTrngHW+0x14c>)
    4b42:	4638      	mov	r0, r7
    4b44:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
    4b48:	4f15      	ldr	r7, [pc, #84]	; (4ba0 <startTrngHW+0x150>)
    4b4a:	4638      	mov	r0, r7
    4b4c:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
    4b50:	f44f 037f 	mov.w	r3, #16711680	; 0xff0000
    4b54:	f8d3 2c0c 	ldr.w	r2, [r3, #3084]	; 0xc0c
    4b58:	3201      	adds	r2, #1
    4b5a:	d002      	beq.n	4b62 <startTrngHW+0x112>
    4b5c:	f8d3 3c0c 	ldr.w	r3, [r3, #3084]	; 0xc0c
    4b60:	e7d1      	b.n	4b06 <startTrngHW+0xb6>
    4b62:	2316      	movs	r3, #22
    4b64:	e7d3      	b.n	4b0e <startTrngHW+0xbe>
    4b66:	f04f 0803 	mov.w	r8, #3
    4b6a:	e79d      	b.n	4aa8 <startTrngHW+0x58>
    4b6c:	f04f 0802 	mov.w	r8, #2
    4b70:	e79a      	b.n	4aa8 <startTrngHW+0x58>
    4b72:	bf00      	nop
    4b74:	508411c4 	.word	0x508411c4
    4b78:	50841140 	.word	0x50841140
    4b7c:	5084112c 	.word	0x5084112c
    4b80:	50841100 	.word	0x50841100
    4b84:	0ffffffe 	.word	0x0ffffffe
    4b88:	5084110c 	.word	0x5084110c
    4b8c:	50841a04 	.word	0x50841a04
    4b90:	50841138 	.word	0x50841138
    4b94:	aaaaaaab 	.word	0xaaaaaaab
    4b98:	508411d8 	.word	0x508411d8
    4b9c:	00f10c31 	.word	0x00f10c31
    4ba0:	00f10c35 	.word	0x00f10c35

00004ba4 <LLF_RND_RepetitionCounterTest.part.0>:
    4ba4:	b4f0      	push	{r4, r5, r6, r7}
    4ba6:	2400      	movs	r4, #0
    4ba8:	00c9      	lsls	r1, r1, #3
    4baa:	4626      	mov	r6, r4
    4bac:	4627      	mov	r7, r4
    4bae:	f101 3cff 	add.w	ip, r1, #4294967295	; 0xffffffff
    4bb2:	e006      	b.n	4bc2 <LLF_RND_RepetitionCounterTest.part.0+0x1e>
    4bb4:	429f      	cmp	r7, r3
    4bb6:	d015      	beq.n	4be4 <LLF_RND_RepetitionCounterTest.part.0+0x40>
    4bb8:	2601      	movs	r6, #1
    4bba:	4565      	cmp	r5, ip
    4bbc:	d818      	bhi.n	4bf0 <LLF_RND_RepetitionCounterTest.part.0+0x4c>
    4bbe:	462c      	mov	r4, r5
    4bc0:	461f      	mov	r7, r3
    4bc2:	0963      	lsrs	r3, r4, #5
    4bc4:	f850 3023 	ldr.w	r3, [r0, r3, lsl #2]
    4bc8:	f004 011f 	and.w	r1, r4, #31
    4bcc:	40cb      	lsrs	r3, r1
    4bce:	291f      	cmp	r1, #31
    4bd0:	f104 0501 	add.w	r5, r4, #1
    4bd4:	bf18      	it	ne
    4bd6:	f003 0301 	andne.w	r3, r3, #1
    4bda:	2c00      	cmp	r4, #0
    4bdc:	d1ea      	bne.n	4bb4 <LLF_RND_RepetitionCounterTest.part.0+0x10>
    4bde:	2601      	movs	r6, #1
    4be0:	4635      	mov	r5, r6
    4be2:	e7ec      	b.n	4bbe <LLF_RND_RepetitionCounterTest.part.0+0x1a>
    4be4:	3601      	adds	r6, #1
    4be6:	4296      	cmp	r6, r2
    4be8:	d1e7      	bne.n	4bba <LLF_RND_RepetitionCounterTest.part.0+0x16>
    4bea:	4803      	ldr	r0, [pc, #12]	; (4bf8 <LLF_RND_RepetitionCounterTest.part.0+0x54>)
    4bec:	bcf0      	pop	{r4, r5, r6, r7}
    4bee:	4770      	bx	lr
    4bf0:	2000      	movs	r0, #0
    4bf2:	bcf0      	pop	{r4, r5, r6, r7}
    4bf4:	4770      	bx	lr
    4bf6:	bf00      	nop
    4bf8:	00f10c36 	.word	0x00f10c36

00004bfc <LLF_RND_AdaptiveProportionTest>:
    4bfc:	2800      	cmp	r0, #0
    4bfe:	d05f      	beq.n	4cc0 <LLF_RND_AdaptiveProportionTest+0xc4>
    4c00:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    4c04:	1e4c      	subs	r4, r1, #1
    4c06:	f5b4 7f04 	cmp.w	r4, #528	; 0x210
    4c0a:	d226      	bcs.n	4c5a <LLF_RND_AdaptiveProportionTest+0x5e>
    4c0c:	b32b      	cbz	r3, 4c5a <LLF_RND_AdaptiveProportionTest+0x5e>
    4c0e:	b322      	cbz	r2, 4c5a <LLF_RND_AdaptiveProportionTest+0x5e>
    4c10:	00cc      	lsls	r4, r1, #3
    4c12:	2b01      	cmp	r3, #1
    4c14:	f104 3eff 	add.w	lr, r4, #4294967295	; 0xffffffff
    4c18:	d02f      	beq.n	4c7a <LLF_RND_AdaptiveProportionTest+0x7e>
    4c1a:	2100      	movs	r1, #0
    4c1c:	468c      	mov	ip, r1
    4c1e:	460f      	mov	r7, r1
    4c20:	460d      	mov	r5, r1
    4c22:	f103 38ff 	add.w	r8, r3, #4294967295	; 0xffffffff
    4c26:	094c      	lsrs	r4, r1, #5
    4c28:	f850 4024 	ldr.w	r4, [r0, r4, lsl #2]
    4c2c:	f001 061f 	and.w	r6, r1, #31
    4c30:	40f4      	lsrs	r4, r6
    4c32:	2e1f      	cmp	r6, #31
    4c34:	bf18      	it	ne
    4c36:	f004 0401 	andne.w	r4, r4, #1
    4c3a:	b921      	cbnz	r1, 4c46 <LLF_RND_AdaptiveProportionTest+0x4a>
    4c3c:	2501      	movs	r5, #1
    4c3e:	46ac      	mov	ip, r5
    4c40:	4629      	mov	r1, r5
    4c42:	4627      	mov	r7, r4
    4c44:	e7ef      	b.n	4c26 <LLF_RND_AdaptiveProportionTest+0x2a>
    4c46:	42ab      	cmp	r3, r5
    4c48:	d013      	beq.n	4c72 <LLF_RND_AdaptiveProportionTest+0x76>
    4c4a:	42a7      	cmp	r7, r4
    4c4c:	d101      	bne.n	4c52 <LLF_RND_AdaptiveProportionTest+0x56>
    4c4e:	f10c 0c01 	add.w	ip, ip, #1
    4c52:	4545      	cmp	r5, r8
    4c54:	d104      	bne.n	4c60 <LLF_RND_AdaptiveProportionTest+0x64>
    4c56:	4562      	cmp	r2, ip
    4c58:	d202      	bcs.n	4c60 <LLF_RND_AdaptiveProportionTest+0x64>
    4c5a:	481a      	ldr	r0, [pc, #104]	; (4cc4 <LLF_RND_AdaptiveProportionTest+0xc8>)
    4c5c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    4c60:	463c      	mov	r4, r7
    4c62:	3101      	adds	r1, #1
    4c64:	458e      	cmp	lr, r1
    4c66:	f105 0501 	add.w	r5, r5, #1
    4c6a:	d2ea      	bcs.n	4c42 <LLF_RND_AdaptiveProportionTest+0x46>
    4c6c:	2000      	movs	r0, #0
    4c6e:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    4c72:	2500      	movs	r5, #0
    4c74:	f04f 0c01 	mov.w	ip, #1
    4c78:	e7f3      	b.n	4c62 <LLF_RND_AdaptiveProportionTest+0x66>
    4c7a:	2600      	movs	r6, #0
    4c7c:	46b4      	mov	ip, r6
    4c7e:	4637      	mov	r7, r6
    4c80:	4631      	mov	r1, r6
    4c82:	094b      	lsrs	r3, r1, #5
    4c84:	f850 3023 	ldr.w	r3, [r0, r3, lsl #2]
    4c88:	f001 051f 	and.w	r5, r1, #31
    4c8c:	40eb      	lsrs	r3, r5
    4c8e:	2d1f      	cmp	r5, #31
    4c90:	bf18      	it	ne
    4c92:	f003 0301 	andne.w	r3, r3, #1
    4c96:	b139      	cbz	r1, 4ca8 <LLF_RND_AdaptiveProportionTest+0xac>
    4c98:	b95f      	cbnz	r7, 4cb2 <LLF_RND_AdaptiveProportionTest+0xb6>
    4c9a:	459c      	cmp	ip, r3
    4c9c:	d001      	beq.n	4ca2 <LLF_RND_AdaptiveProportionTest+0xa6>
    4c9e:	4663      	mov	r3, ip
    4ca0:	e008      	b.n	4cb4 <LLF_RND_AdaptiveProportionTest+0xb8>
    4ca2:	4663      	mov	r3, ip
    4ca4:	3601      	adds	r6, #1
    4ca6:	e005      	b.n	4cb4 <LLF_RND_AdaptiveProportionTest+0xb8>
    4ca8:	2601      	movs	r6, #1
    4caa:	4631      	mov	r1, r6
    4cac:	469c      	mov	ip, r3
    4cae:	2701      	movs	r7, #1
    4cb0:	e7e7      	b.n	4c82 <LLF_RND_AdaptiveProportionTest+0x86>
    4cb2:	463e      	mov	r6, r7
    4cb4:	42b2      	cmp	r2, r6
    4cb6:	d3d0      	bcc.n	4c5a <LLF_RND_AdaptiveProportionTest+0x5e>
    4cb8:	3101      	adds	r1, #1
    4cba:	42a1      	cmp	r1, r4
    4cbc:	d1f6      	bne.n	4cac <LLF_RND_AdaptiveProportionTest+0xb0>
    4cbe:	e7d5      	b.n	4c6c <LLF_RND_AdaptiveProportionTest+0x70>
    4cc0:	4800      	ldr	r0, [pc, #0]	; (4cc4 <LLF_RND_AdaptiveProportionTest+0xc8>)
    4cc2:	4770      	bx	lr
    4cc4:	00f10c37 	.word	0x00f10c37

00004cc8 <getTrngSource>:
    4cc8:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    4ccc:	b08d      	sub	sp, #52	; 0x34
    4cce:	9e18      	ldr	r6, [sp, #96]	; 0x60
    4cd0:	4607      	mov	r7, r0
    4cd2:	460c      	mov	r4, r1
    4cd4:	9d17      	ldr	r5, [sp, #92]	; 0x5c
    4cd6:	2e00      	cmp	r6, #0
    4cd8:	d14c      	bne.n	4d74 <getTrngSource+0xac>
    4cda:	f8d1 b010 	ldr.w	fp, [r1, #16]
    4cde:	2100      	movs	r1, #0
    4ce0:	601d      	str	r5, [r3, #0]
    4ce2:	9b16      	ldr	r3, [sp, #88]	; 0x58
    4ce4:	6019      	str	r1, [r3, #0]
    4ce6:	2a00      	cmp	r2, #0
    4ce8:	f000 811e 	beq.w	4f28 <getTrngSource+0x260>
    4cec:	4a9a      	ldr	r2, [pc, #616]	; (4f58 <getTrngSource+0x290>)
    4cee:	4b9b      	ldr	r3, [pc, #620]	; (4f5c <getTrngSource+0x294>)
    4cf0:	6811      	ldr	r1, [r2, #0]
    4cf2:	6a62      	ldr	r2, [r4, #36]	; 0x24
    4cf4:	681b      	ldr	r3, [r3, #0]
    4cf6:	429a      	cmp	r2, r3
    4cf8:	d147      	bne.n	4d8a <getTrngSource+0xc2>
    4cfa:	290a      	cmp	r1, #10
    4cfc:	d145      	bne.n	4d8a <getTrngSource+0xc2>
    4cfe:	78fb      	ldrb	r3, [r7, #3]
    4d00:	9304      	str	r3, [sp, #16]
    4d02:	2304      	movs	r3, #4
    4d04:	46b8      	mov	r8, r7
    4d06:	9302      	str	r3, [sp, #8]
    4d08:	4b95      	ldr	r3, [pc, #596]	; (4f60 <getTrngSource+0x298>)
    4d0a:	fba3 230b 	umull	r2, r3, r3, fp
    4d0e:	ea4f 0a93 	mov.w	sl, r3, lsr #2
    4d12:	eb0a 034a 	add.w	r3, sl, sl, lsl #1
    4d16:	f105 0208 	add.w	r2, r5, #8
    4d1a:	9203      	str	r2, [sp, #12]
    4d1c:	ebab 0a43 	sub.w	sl, fp, r3, lsl #1
    4d20:	9b16      	ldr	r3, [sp, #88]	; 0x58
    4d22:	f8c3 b000 	str.w	fp, [r3]
    4d26:	f1bb 0f00 	cmp.w	fp, #0
    4d2a:	f000 80c3 	beq.w	4eb4 <getTrngSource+0x1ec>
    4d2e:	465d      	mov	r5, fp
    4d30:	f04f 0900 	mov.w	r9, #0
    4d34:	9e03      	ldr	r6, [sp, #12]
    4d36:	f000 f9c7 	bl	50c8 <LLF_RND_TurnOffTrng>
    4d3a:	2300      	movs	r3, #0
    4d3c:	9305      	str	r3, [sp, #20]
    4d3e:	f1b8 0f00 	cmp.w	r8, #0
    4d42:	f000 80e5 	beq.w	4f10 <getTrngSource+0x248>
    4d46:	2c00      	cmp	r4, #0
    4d48:	f000 80e2 	beq.w	4f10 <getTrngSource+0x248>
    4d4c:	9b04      	ldr	r3, [sp, #16]
    4d4e:	2b00      	cmp	r3, #0
    4d50:	f000 80dc 	beq.w	4f0c <getTrngSource+0x244>
    4d54:	4620      	mov	r0, r4
    4d56:	a904      	add	r1, sp, #16
    4d58:	f000 f9a6 	bl	50a8 <LLF_RND_GetFastestRosc>
    4d5c:	b1b8      	cbz	r0, 4d8e <getTrngSource+0xc6>
    4d5e:	4b81      	ldr	r3, [pc, #516]	; (4f64 <getTrngSource+0x29c>)
    4d60:	4298      	cmp	r0, r3
    4d62:	f040 80a7 	bne.w	4eb4 <getTrngSource+0x1ec>
    4d66:	9002      	str	r0, [sp, #8]
    4d68:	f000 f9ae 	bl	50c8 <LLF_RND_TurnOffTrng>
    4d6c:	9802      	ldr	r0, [sp, #8]
    4d6e:	b00d      	add	sp, #52	; 0x34
    4d70:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    4d74:	f44f 017f 	mov.w	r1, #16711680	; 0xff0000
    4d78:	f8d1 0c0c 	ldr.w	r0, [r1, #3084]	; 0xc0c
    4d7c:	3001      	adds	r0, #1
    4d7e:	bf0c      	ite	eq
    4d80:	f44f 7b04 	moveq.w	fp, #528	; 0x210
    4d84:	f8d1 bc0c 	ldrne.w	fp, [r1, #3084]	; 0xc0c
    4d88:	e7a9      	b.n	4cde <getTrngSource+0x16>
    4d8a:	4877      	ldr	r0, [pc, #476]	; (4f68 <getTrngSource+0x2a0>)
    4d8c:	e7eb      	b.n	4d66 <getTrngSource+0x9e>
    4d8e:	4621      	mov	r1, r4
    4d90:	9804      	ldr	r0, [sp, #16]
    4d92:	f000 f96b 	bl	506c <LLF_RND_GetRoscSampleCnt>
    4d96:	2800      	cmp	r0, #0
    4d98:	d1e1      	bne.n	4d5e <getTrngSource+0x96>
    4d9a:	9f04      	ldr	r7, [sp, #16]
    4d9c:	2f08      	cmp	r7, #8
    4d9e:	f000 80b9 	beq.w	4f14 <getTrngSource+0x24c>
    4da2:	2f04      	cmp	r7, #4
    4da4:	f000 80b8 	beq.w	4f18 <getTrngSource+0x250>
    4da8:	f1a7 0702 	sub.w	r7, r7, #2
    4dac:	fab7 f787 	clz	r7, r7
    4db0:	097f      	lsrs	r7, r7, #5
    4db2:	2301      	movs	r3, #1
    4db4:	4619      	mov	r1, r3
    4db6:	486d      	ldr	r0, [pc, #436]	; (4f6c <getTrngSource+0x2a4>)
    4db8:	6003      	str	r3, [r0, #0]
    4dba:	f840 3c84 	str.w	r3, [r0, #-132]
    4dbe:	4b6b      	ldr	r3, [pc, #428]	; (4f6c <getTrngSource+0x2a4>)
    4dc0:	4866      	ldr	r0, [pc, #408]	; (4f5c <getTrngSource+0x294>)
    4dc2:	6019      	str	r1, [r3, #0]
    4dc4:	6a63      	ldr	r3, [r4, #36]	; 0x24
    4dc6:	6003      	str	r3, [r0, #0]
    4dc8:	6800      	ldr	r0, [r0, #0]
    4dca:	4283      	cmp	r3, r0
    4dcc:	d1f7      	bne.n	4dbe <getTrngSource+0xf6>
    4dce:	2300      	movs	r3, #0
    4dd0:	4a67      	ldr	r2, [pc, #412]	; (4f70 <getTrngSource+0x2a8>)
    4dd2:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
    4dd6:	6013      	str	r3, [r2, #0]
    4dd8:	f7ff fb32 	bl	4440 <CC_HalClearInterruptBit>
    4ddc:	2300      	movs	r3, #0
    4dde:	4965      	ldr	r1, [pc, #404]	; (4f74 <getTrngSource+0x2ac>)
    4de0:	4618      	mov	r0, r3
    4de2:	4b65      	ldr	r3, [pc, #404]	; (4f78 <getTrngSource+0x2b0>)
    4de4:	6019      	str	r1, [r3, #0]
    4de6:	f7ff fb39 	bl	445c <CC_HalMaskInterrupt>
    4dea:	4964      	ldr	r1, [pc, #400]	; (4f7c <getTrngSource+0x2b4>)
    4dec:	4b64      	ldr	r3, [pc, #400]	; (4f80 <getTrngSource+0x2b8>)
    4dee:	600f      	str	r7, [r1, #0]
    4df0:	6818      	ldr	r0, [r3, #0]
    4df2:	4f5b      	ldr	r7, [pc, #364]	; (4f60 <getTrngSource+0x298>)
    4df4:	f440 6080 	orr.w	r0, r0, #1024	; 0x400
    4df8:	f7ff fb30 	bl	445c <CC_HalMaskInterrupt>
    4dfc:	210a      	movs	r1, #10
    4dfe:	2201      	movs	r2, #1
    4e00:	4b55      	ldr	r3, [pc, #340]	; (4f58 <getTrngSource+0x290>)
    4e02:	4860      	ldr	r0, [pc, #384]	; (4f84 <getTrngSource+0x2bc>)
    4e04:	6019      	str	r1, [r3, #0]
    4e06:	6921      	ldr	r1, [r4, #16]
    4e08:	6a63      	ldr	r3, [r4, #36]	; 0x24
    4e0a:	fba7 c101 	umull	ip, r1, r7, r1
    4e0e:	0909      	lsrs	r1, r1, #4
    4e10:	fb03 f301 	mul.w	r3, r3, r1
    4e14:	eb03 0343 	add.w	r3, r3, r3, lsl #1
    4e18:	03db      	lsls	r3, r3, #15
    4e1a:	099b      	lsrs	r3, r3, #6
    4e1c:	6003      	str	r3, [r0, #0]
    4e1e:	4b54      	ldr	r3, [pc, #336]	; (4f70 <getTrngSource+0x2a8>)
    4e20:	a805      	add	r0, sp, #20
    4e22:	601a      	str	r2, [r3, #0]
    4e24:	9904      	ldr	r1, [sp, #16]
    4e26:	f8d8 2000 	ldr.w	r2, [r8]
    4e2a:	020b      	lsls	r3, r1, #8
    4e2c:	ea43 6301 	orr.w	r3, r3, r1, lsl #24
    4e30:	f022 427f 	bic.w	r2, r2, #4278190080	; 0xff000000
    4e34:	4313      	orrs	r3, r2
    4e36:	f8c8 3000 	str.w	r3, [r8]
    4e3a:	f000 f907 	bl	504c <LLF_RND_WaitRngInterrupt>
    4e3e:	2800      	cmp	r0, #0
    4e40:	d18d      	bne.n	4d5e <getTrngSource+0x96>
    4e42:	4b51      	ldr	r3, [pc, #324]	; (4f88 <getTrngSource+0x2c0>)
    4e44:	fba7 2705 	umull	r2, r7, r7, r5
    4e48:	681a      	ldr	r2, [r3, #0]
    4e4a:	3314      	adds	r3, #20
    4e4c:	9206      	str	r2, [sp, #24]
    4e4e:	f853 2c10 	ldr.w	r2, [r3, #-16]
    4e52:	ebb9 0f97 	cmp.w	r9, r7, lsr #2
    4e56:	9207      	str	r2, [sp, #28]
    4e58:	f853 2c0c 	ldr.w	r2, [r3, #-12]
    4e5c:	9208      	str	r2, [sp, #32]
    4e5e:	f853 2c08 	ldr.w	r2, [r3, #-8]
    4e62:	9209      	str	r2, [sp, #36]	; 0x24
    4e64:	f853 2c04 	ldr.w	r2, [r3, #-4]
    4e68:	920a      	str	r2, [sp, #40]	; 0x28
    4e6a:	681b      	ldr	r3, [r3, #0]
    4e6c:	930b      	str	r3, [sp, #44]	; 0x2c
    4e6e:	d102      	bne.n	4e76 <getTrngSource+0x1ae>
    4e70:	f1ba 0f00 	cmp.w	sl, #0
    4e74:	d141      	bne.n	4efa <getTrngSource+0x232>
    4e76:	2218      	movs	r2, #24
    4e78:	4630      	mov	r0, r6
    4e7a:	eb0d 0102 	add.w	r1, sp, r2
    4e7e:	f7ff fa03 	bl	4288 <CC_PalMemCopyPlat>
    4e82:	3d18      	subs	r5, #24
    4e84:	3618      	adds	r6, #24
    4e86:	f109 0901 	add.w	r9, r9, #1
    4e8a:	2d00      	cmp	r5, #0
    4e8c:	f47f af53 	bne.w	4d36 <getTrngSource+0x6e>
    4e90:	f5bb 7f04 	cmp.w	fp, #528	; 0x210
    4e94:	d85d      	bhi.n	4f52 <getTrngSource+0x28a>
    4e96:	9d03      	ldr	r5, [sp, #12]
    4e98:	4659      	mov	r1, fp
    4e9a:	4628      	mov	r0, r5
    4e9c:	6962      	ldr	r2, [r4, #20]
    4e9e:	f7ff fe81 	bl	4ba4 <LLF_RND_RepetitionCounterTest.part.0>
    4ea2:	2800      	cmp	r0, #0
    4ea4:	d04b      	beq.n	4f3e <getTrngSource+0x276>
    4ea6:	2300      	movs	r3, #0
    4ea8:	9a16      	ldr	r2, [sp, #88]	; 0x58
    4eaa:	6013      	str	r3, [r2, #0]
    4eac:	4b2d      	ldr	r3, [pc, #180]	; (4f64 <getTrngSource+0x29c>)
    4eae:	4298      	cmp	r0, r3
    4eb0:	f43f af59 	beq.w	4d66 <getTrngSource+0x9e>
    4eb4:	9d04      	ldr	r5, [sp, #16]
    4eb6:	2d08      	cmp	r5, #8
    4eb8:	d034      	beq.n	4f24 <getTrngSource+0x25c>
    4eba:	2200      	movs	r2, #0
    4ebc:	ab04      	add	r3, sp, #16
    4ebe:	4621      	mov	r1, r4
    4ec0:	4640      	mov	r0, r8
    4ec2:	006d      	lsls	r5, r5, #1
    4ec4:	9200      	str	r2, [sp, #0]
    4ec6:	9504      	str	r5, [sp, #16]
    4ec8:	f7ff fdc2 	bl	4a50 <startTrngHW>
    4ecc:	4b2f      	ldr	r3, [pc, #188]	; (4f8c <getTrngSource+0x2c4>)
    4ece:	4298      	cmp	r0, r3
    4ed0:	d024      	beq.n	4f1c <getTrngSource+0x254>
    4ed2:	2800      	cmp	r0, #0
    4ed4:	f47f af47 	bne.w	4d66 <getTrngSource+0x9e>
    4ed8:	f8d8 2000 	ldr.w	r2, [r8]
    4edc:	0a13      	lsrs	r3, r2, #8
    4ede:	f403 037f 	and.w	r3, r3, #16711680	; 0xff0000
    4ee2:	4313      	orrs	r3, r2
    4ee4:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
    4ee8:	f8c8 3000 	str.w	r3, [r8]
    4eec:	9b02      	ldr	r3, [sp, #8]
    4eee:	3b01      	subs	r3, #1
    4ef0:	9302      	str	r3, [sp, #8]
    4ef2:	f47f af15 	bne.w	4d20 <getTrngSource+0x58>
    4ef6:	2000      	movs	r0, #0
    4ef8:	e735      	b.n	4d66 <getTrngSource+0x9e>
    4efa:	4630      	mov	r0, r6
    4efc:	4652      	mov	r2, sl
    4efe:	a906      	add	r1, sp, #24
    4f00:	f7ff f9c2 	bl	4288 <CC_PalMemCopyPlat>
    4f04:	eba5 050a 	sub.w	r5, r5, sl
    4f08:	4456      	add	r6, sl
    4f0a:	e7bc      	b.n	4e86 <getTrngSource+0x1be>
    4f0c:	481f      	ldr	r0, [pc, #124]	; (4f8c <getTrngSource+0x2c4>)
    4f0e:	e726      	b.n	4d5e <getTrngSource+0x96>
    4f10:	481f      	ldr	r0, [pc, #124]	; (4f90 <getTrngSource+0x2c8>)
    4f12:	e724      	b.n	4d5e <getTrngSource+0x96>
    4f14:	2703      	movs	r7, #3
    4f16:	e74c      	b.n	4db2 <getTrngSource+0xea>
    4f18:	2702      	movs	r7, #2
    4f1a:	e74a      	b.n	4db2 <getTrngSource+0xea>
    4f1c:	6a23      	ldr	r3, [r4, #32]
    4f1e:	2b00      	cmp	r3, #0
    4f20:	f43f af21 	beq.w	4d66 <getTrngSource+0x9e>
    4f24:	481b      	ldr	r0, [pc, #108]	; (4f94 <getTrngSource+0x2cc>)
    4f26:	e71e      	b.n	4d66 <getTrngSource+0x9e>
    4f28:	2201      	movs	r2, #1
    4f2a:	4621      	mov	r1, r4
    4f2c:	4638      	mov	r0, r7
    4f2e:	9600      	str	r6, [sp, #0]
    4f30:	ab04      	add	r3, sp, #16
    4f32:	f7ff fd8d 	bl	4a50 <startTrngHW>
    4f36:	2800      	cmp	r0, #0
    4f38:	f43f aee3 	beq.w	4d02 <getTrngSource+0x3a>
    4f3c:	e713      	b.n	4d66 <getTrngSource+0x9e>
    4f3e:	f44f 6380 	mov.w	r3, #1024	; 0x400
    4f42:	4659      	mov	r1, fp
    4f44:	4628      	mov	r0, r5
    4f46:	69a2      	ldr	r2, [r4, #24]
    4f48:	f7ff fe58 	bl	4bfc <LLF_RND_AdaptiveProportionTest>
    4f4c:	2800      	cmp	r0, #0
    4f4e:	d1aa      	bne.n	4ea6 <getTrngSource+0x1de>
    4f50:	e7d1      	b.n	4ef6 <getTrngSource+0x22e>
    4f52:	9b16      	ldr	r3, [sp, #88]	; 0x58
    4f54:	601d      	str	r5, [r3, #0]
    4f56:	e7ad      	b.n	4eb4 <getTrngSource+0x1ec>
    4f58:	50841138 	.word	0x50841138
    4f5c:	50841130 	.word	0x50841130
    4f60:	aaaaaaab 	.word	0xaaaaaaab
    4f64:	00f10c02 	.word	0x00f10c02
    4f68:	00f10c30 	.word	0x00f10c30
    4f6c:	508411c4 	.word	0x508411c4
    4f70:	5084112c 	.word	0x5084112c
    4f74:	0ffffffe 	.word	0x0ffffffe
    4f78:	50841100 	.word	0x50841100
    4f7c:	5084110c 	.word	0x5084110c
    4f80:	50841a04 	.word	0x50841a04
    4f84:	508411d8 	.word	0x508411d8
    4f88:	50841114 	.word	0x50841114
    4f8c:	00f10c31 	.word	0x00f10c31
    4f90:	00f10c35 	.word	0x00f10c35
    4f94:	00f10c32 	.word	0x00f10c32

00004f98 <LLF_RND_GetTrngSource>:
    4f98:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    4f9c:	4e1f      	ldr	r6, [pc, #124]	; (501c <LLF_RND_GetTrngSource+0x84>)
    4f9e:	b084      	sub	sp, #16
    4fa0:	4604      	mov	r4, r0
    4fa2:	460d      	mov	r5, r1
    4fa4:	6830      	ldr	r0, [r6, #0]
    4fa6:	f04f 31ff 	mov.w	r1, #4294967295	; 0xffffffff
    4faa:	4690      	mov	r8, r2
    4fac:	9f0c      	ldr	r7, [sp, #48]	; 0x30
    4fae:	f7ff f9d1 	bl	4354 <CC_PalMutexLock>
    4fb2:	b9d8      	cbnz	r0, 4fec <LLF_RND_GetTrngSource+0x54>
    4fb4:	2000      	movs	r0, #0
    4fb6:	f7ff f9fd 	bl	43b4 <CC_PalPowerSaveModeSelect>
    4fba:	b9f8      	cbnz	r0, 4ffc <LLF_RND_GetTrngSource+0x64>
    4fbc:	2300      	movs	r3, #0
    4fbe:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
    4fc0:	4620      	mov	r0, r4
    4fc2:	9200      	str	r2, [sp, #0]
    4fc4:	9302      	str	r3, [sp, #8]
    4fc6:	4642      	mov	r2, r8
    4fc8:	4629      	mov	r1, r5
    4fca:	9b0a      	ldr	r3, [sp, #40]	; 0x28
    4fcc:	9701      	str	r7, [sp, #4]
    4fce:	f7ff fe7b 	bl	4cc8 <getTrngSource>
    4fd2:	4604      	mov	r4, r0
    4fd4:	2001      	movs	r0, #1
    4fd6:	f7ff f9ed 	bl	43b4 <CC_PalPowerSaveModeSelect>
    4fda:	b9d0      	cbnz	r0, 5012 <LLF_RND_GetTrngSource+0x7a>
    4fdc:	6830      	ldr	r0, [r6, #0]
    4fde:	f7ff f9c1 	bl	4364 <CC_PalMutexUnlock>
    4fe2:	b978      	cbnz	r0, 5004 <LLF_RND_GetTrngSource+0x6c>
    4fe4:	4620      	mov	r0, r4
    4fe6:	b004      	add	sp, #16
    4fe8:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    4fec:	480c      	ldr	r0, [pc, #48]	; (5020 <LLF_RND_GetTrngSource+0x88>)
    4fee:	f7ff fb49 	bl	4684 <CC_PalAbort>
    4ff2:	2000      	movs	r0, #0
    4ff4:	f7ff f9de 	bl	43b4 <CC_PalPowerSaveModeSelect>
    4ff8:	2800      	cmp	r0, #0
    4ffa:	d0df      	beq.n	4fbc <LLF_RND_GetTrngSource+0x24>
    4ffc:	4809      	ldr	r0, [pc, #36]	; (5024 <LLF_RND_GetTrngSource+0x8c>)
    4ffe:	f7ff fb41 	bl	4684 <CC_PalAbort>
    5002:	e7db      	b.n	4fbc <LLF_RND_GetTrngSource+0x24>
    5004:	4808      	ldr	r0, [pc, #32]	; (5028 <LLF_RND_GetTrngSource+0x90>)
    5006:	f7ff fb3d 	bl	4684 <CC_PalAbort>
    500a:	4620      	mov	r0, r4
    500c:	b004      	add	sp, #16
    500e:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    5012:	4806      	ldr	r0, [pc, #24]	; (502c <LLF_RND_GetTrngSource+0x94>)
    5014:	f7ff fb36 	bl	4684 <CC_PalAbort>
    5018:	e7e0      	b.n	4fdc <LLF_RND_GetTrngSource+0x44>
    501a:	bf00      	nop
    501c:	20000040 	.word	0x20000040
    5020:	0000619c 	.word	0x0000619c
    5024:	000061cc 	.word	0x000061cc
    5028:	000061b4 	.word	0x000061b4
    502c:	000061ec 	.word	0x000061ec

00005030 <LLF_RND_RunTrngStartupTest>:
    5030:	b510      	push	{r4, lr}
    5032:	2401      	movs	r4, #1
    5034:	b086      	sub	sp, #24
    5036:	ab05      	add	r3, sp, #20
    5038:	e9cd 2401 	strd	r2, r4, [sp, #4]
    503c:	9300      	str	r3, [sp, #0]
    503e:	2200      	movs	r2, #0
    5040:	ab04      	add	r3, sp, #16
    5042:	f7ff fe41 	bl	4cc8 <getTrngSource>
    5046:	b006      	add	sp, #24
    5048:	bd10      	pop	{r4, pc}
    504a:	bf00      	nop

0000504c <LLF_RND_WaitRngInterrupt>:
    504c:	4601      	mov	r1, r0
    504e:	b508      	push	{r3, lr}
    5050:	f44f 6080 	mov.w	r0, #1024	; 0x400
    5054:	f7ff fa08 	bl	4468 <CC_HalWaitInterruptRND>
    5058:	2300      	movs	r3, #0
    505a:	4902      	ldr	r1, [pc, #8]	; (5064 <LLF_RND_WaitRngInterrupt+0x18>)
    505c:	4a02      	ldr	r2, [pc, #8]	; (5068 <LLF_RND_WaitRngInterrupt+0x1c>)
    505e:	600b      	str	r3, [r1, #0]
    5060:	6013      	str	r3, [r2, #0]
    5062:	bd08      	pop	{r3, pc}
    5064:	508411c8 	.word	0x508411c8
    5068:	5084112c 	.word	0x5084112c

0000506c <LLF_RND_GetRoscSampleCnt>:
    506c:	3801      	subs	r0, #1
    506e:	2807      	cmp	r0, #7
    5070:	d805      	bhi.n	507e <LLF_RND_GetRoscSampleCnt+0x12>
    5072:	e8df f000 	tbb	[pc, r0]
    5076:	0e0a      	.short	0x0e0a
    5078:	04041204 	.word	0x04041204
    507c:	0604      	.short	0x0604
    507e:	4809      	ldr	r0, [pc, #36]	; (50a4 <LLF_RND_GetRoscSampleCnt+0x38>)
    5080:	4770      	bx	lr
    5082:	68cb      	ldr	r3, [r1, #12]
    5084:	2000      	movs	r0, #0
    5086:	624b      	str	r3, [r1, #36]	; 0x24
    5088:	4770      	bx	lr
    508a:	680b      	ldr	r3, [r1, #0]
    508c:	2000      	movs	r0, #0
    508e:	624b      	str	r3, [r1, #36]	; 0x24
    5090:	4770      	bx	lr
    5092:	684b      	ldr	r3, [r1, #4]
    5094:	2000      	movs	r0, #0
    5096:	624b      	str	r3, [r1, #36]	; 0x24
    5098:	4770      	bx	lr
    509a:	688b      	ldr	r3, [r1, #8]
    509c:	2000      	movs	r0, #0
    509e:	624b      	str	r3, [r1, #36]	; 0x24
    50a0:	4770      	bx	lr
    50a2:	bf00      	nop
    50a4:	00f10c31 	.word	0x00f10c31

000050a8 <LLF_RND_GetFastestRosc>:
    50a8:	680b      	ldr	r3, [r1, #0]
    50aa:	e002      	b.n	50b2 <LLF_RND_GetFastestRosc+0xa>
    50ac:	2b08      	cmp	r3, #8
    50ae:	600b      	str	r3, [r1, #0]
    50b0:	d806      	bhi.n	50c0 <LLF_RND_GetFastestRosc+0x18>
    50b2:	6a02      	ldr	r2, [r0, #32]
    50b4:	4213      	tst	r3, r2
    50b6:	ea4f 0343 	mov.w	r3, r3, lsl #1
    50ba:	d0f7      	beq.n	50ac <LLF_RND_GetFastestRosc+0x4>
    50bc:	2000      	movs	r0, #0
    50be:	4770      	bx	lr
    50c0:	4800      	ldr	r0, [pc, #0]	; (50c4 <LLF_RND_GetFastestRosc+0x1c>)
    50c2:	4770      	bx	lr
    50c4:	00f10c31 	.word	0x00f10c31

000050c8 <LLF_RND_TurnOffTrng>:
    50c8:	2300      	movs	r3, #0
    50ca:	4904      	ldr	r1, [pc, #16]	; (50dc <LLF_RND_TurnOffTrng+0x14>)
    50cc:	4a04      	ldr	r2, [pc, #16]	; (50e0 <LLF_RND_TurnOffTrng+0x18>)
    50ce:	600b      	str	r3, [r1, #0]
    50d0:	f44f 6080 	mov.w	r0, #1024	; 0x400
    50d4:	6013      	str	r3, [r2, #0]
    50d6:	f7ff b9b3 	b.w	4440 <CC_HalClearInterruptBit>
    50da:	bf00      	nop
    50dc:	5084112c 	.word	0x5084112c
    50e0:	508411c4 	.word	0x508411c4

000050e4 <main>:
 *  0 kB  |---------------------|
 */


void main(void)
{
    50e4:	b508      	push	{r3, lr}
	spm_config();
    50e6:	f7fc fdc5 	bl	1c74 <spm_config>
	spm_jump();
}
    50ea:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	spm_jump();
    50ee:	f7fc bd57 	b.w	1ba0 <spm_jump>

000050f2 <sys_notify_validate>:

int sys_notify_validate(struct sys_notify *notify)
{
	int rv = 0;

	if (notify == NULL) {
    50f2:	b160      	cbz	r0, 510e <sys_notify_validate+0x1c>
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    50f4:	6843      	ldr	r3, [r0, #4]
	return method & SYS_NOTIFY_METHOD_MASK;
    50f6:	f003 0303 	and.w	r3, r3, #3
		return -EINVAL;
	}

	/* Validate configuration based on mode */
	switch (sys_notify_get_method(notify)) {
    50fa:	2b01      	cmp	r3, #1
    50fc:	d003      	beq.n	5106 <sys_notify_validate+0x14>
    50fe:	2b03      	cmp	r3, #3
    5100:	d105      	bne.n	510e <sys_notify_validate+0x1c>
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		if (notify->method.callback == NULL) {
    5102:	6803      	ldr	r3, [r0, #0]
    5104:	b11b      	cbz	r3, 510e <sys_notify_validate+0x1c>
		break;
	}

	/* Clear the result here instead of in all callers. */
	if (rv == 0) {
		notify->result = 0;
    5106:	2300      	movs	r3, #0
    5108:	6083      	str	r3, [r0, #8]
    510a:	4618      	mov	r0, r3
    510c:	4770      	bx	lr
		return -EINVAL;
    510e:	f06f 0015 	mvn.w	r0, #21
	}

	return rv;
}
    5112:	4770      	bx	lr

00005114 <sys_notify_finalize>:
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    5114:	2200      	movs	r2, #0
    5116:	6843      	ldr	r3, [r0, #4]
	uint32_t method = sys_notify_get_method(notify);

	/* Store the result and capture secondary notification
	 * information.
	 */
	notify->result = res;
    5118:	6081      	str	r1, [r0, #8]
	return method & SYS_NOTIFY_METHOD_MASK;
    511a:	f003 0303 	and.w	r3, r3, #3
	switch (method) {
    511e:	2b03      	cmp	r3, #3
	sys_notify_generic_callback rv = 0;
    5120:	bf14      	ite	ne
    5122:	4613      	movne	r3, r2
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		rv = notify->method.callback;
    5124:	6803      	ldreq	r3, [r0, #0]
	/* Mark completion by clearing the flags field to the
	 * completed state, releasing any spin-waiters, then complete
	 * secondary notification.
	 */
	compiler_barrier();
	notify->flags = SYS_NOTIFY_METHOD_COMPLETED;
    5126:	6042      	str	r2, [r0, #4]
	if (IS_ENABLED(CONFIG_POLL) && (sig != NULL)) {
		k_poll_signal_raise(sig, res);
	}

	return rv;
}
    5128:	4618      	mov	r0, r3
    512a:	4770      	bx	lr

0000512c <arch_printk_char_out>:
}
    512c:	2000      	movs	r0, #0
    512e:	4770      	bx	lr

00005130 <printk>:
 * @param fmt formatted string to output
 *
 * @return N/A
 */
void printk(const char *fmt, ...)
{
    5130:	b40f      	push	{r0, r1, r2, r3}
    5132:	b507      	push	{r0, r1, r2, lr}
    5134:	a904      	add	r1, sp, #16
    5136:	f851 0b04 	ldr.w	r0, [r1], #4
	va_list ap;

	va_start(ap, fmt);
    513a:	9101      	str	r1, [sp, #4]

	if (IS_ENABLED(CONFIG_LOG_PRINTK)) {
		log_printk(fmt, ap);
	} else {
		vprintk(fmt, ap);
    513c:	f7fb fa42 	bl	5c4 <vprintk>
	}
	va_end(ap);
}
    5140:	b003      	add	sp, #12
    5142:	f85d eb04 	ldr.w	lr, [sp], #4
    5146:	b004      	add	sp, #16
    5148:	4770      	bx	lr

0000514a <process_recheck>:
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    514a:	8b03      	ldrh	r3, [r0, #24]
	if ((state == ONOFF_STATE_OFF)
    514c:	f013 0307 	ands.w	r3, r3, #7
    5150:	d105      	bne.n	515e <process_recheck+0x14>
	    && !sys_slist_is_empty(&mgr->clients)) {
    5152:	6803      	ldr	r3, [r0, #0]
    5154:	2b00      	cmp	r3, #0
		evt = EVT_START;
    5156:	bf0c      	ite	eq
    5158:	2000      	moveq	r0, #0
    515a:	2003      	movne	r0, #3
    515c:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ON)
    515e:	2b02      	cmp	r3, #2
    5160:	d105      	bne.n	516e <process_recheck+0x24>
		   && (mgr->refs == 0U)) {
    5162:	8b43      	ldrh	r3, [r0, #26]
    5164:	2b00      	cmp	r3, #0
		evt = EVT_STOP;
    5166:	bf14      	ite	ne
    5168:	2000      	movne	r0, #0
    516a:	2004      	moveq	r0, #4
    516c:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ERROR)
    516e:	2b01      	cmp	r3, #1
    5170:	d105      	bne.n	517e <process_recheck+0x34>
		   && !sys_slist_is_empty(&mgr->clients)) {
    5172:	6803      	ldr	r3, [r0, #0]
    5174:	2b00      	cmp	r3, #0
		evt = EVT_RESET;
    5176:	bf0c      	ite	eq
    5178:	2000      	moveq	r0, #0
    517a:	2005      	movne	r0, #5
    517c:	4770      	bx	lr
	int evt = EVT_NOP;
    517e:	2000      	movs	r0, #0
}
    5180:	4770      	bx	lr

00005182 <notify_one>:
{
    5182:	b573      	push	{r0, r1, r4, r5, r6, lr}
    5184:	460d      	mov	r5, r1
    5186:	4606      	mov	r6, r0
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    5188:	4619      	mov	r1, r3
    518a:	1d28      	adds	r0, r5, #4
{
    518c:	9201      	str	r2, [sp, #4]
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    518e:	9300      	str	r3, [sp, #0]
    5190:	f7ff ffc0 	bl	5114 <sys_notify_finalize>
	if (cb) {
    5194:	4604      	mov	r4, r0
    5196:	b140      	cbz	r0, 51aa <notify_one+0x28>
		cb(mgr, cli, state, res);
    5198:	e9dd 3200 	ldrd	r3, r2, [sp]
    519c:	4629      	mov	r1, r5
    519e:	4630      	mov	r0, r6
    51a0:	46a4      	mov	ip, r4
}
    51a2:	b002      	add	sp, #8
    51a4:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		cb(mgr, cli, state, res);
    51a8:	4760      	bx	ip
}
    51aa:	b002      	add	sp, #8
    51ac:	bd70      	pop	{r4, r5, r6, pc}

000051ae <transition_complete>:
{
    51ae:	b410      	push	{r4}
	__asm__ volatile(
    51b0:	f04f 0420 	mov.w	r4, #32
    51b4:	f3ef 8211 	mrs	r2, BASEPRI
    51b8:	f384 8811 	msr	BASEPRI, r4
    51bc:	f3bf 8f6f 	isb	sy
	mgr->last_res = res;
    51c0:	6141      	str	r1, [r0, #20]
}
    51c2:	f85d 4b04 	ldr.w	r4, [sp], #4
	process_event(mgr, EVT_COMPLETE, key);
    51c6:	2101      	movs	r1, #1
    51c8:	f7fb ba0a 	b.w	5e0 <process_event>

000051cc <validate_args>:
{
    51cc:	b510      	push	{r4, lr}
    51ce:	460c      	mov	r4, r1
	if ((mgr == NULL) || (cli == NULL)) {
    51d0:	b140      	cbz	r0, 51e4 <validate_args+0x18>
    51d2:	b139      	cbz	r1, 51e4 <validate_args+0x18>
	int rv = sys_notify_validate(&cli->notify);
    51d4:	1d08      	adds	r0, r1, #4
    51d6:	f7ff ff8c 	bl	50f2 <sys_notify_validate>
	if ((rv == 0)
    51da:	b928      	cbnz	r0, 51e8 <validate_args+0x1c>
	    && ((cli->notify.flags
    51dc:	68a3      	ldr	r3, [r4, #8]
    51de:	f033 0303 	bics.w	r3, r3, #3
    51e2:	d001      	beq.n	51e8 <validate_args+0x1c>
		rv = -EINVAL;
    51e4:	f06f 0015 	mvn.w	r0, #21
}
    51e8:	bd10      	pop	{r4, pc}

000051ea <onoff_manager_init>:
{
    51ea:	b538      	push	{r3, r4, r5, lr}
    51ec:	460c      	mov	r4, r1
	if ((mgr == NULL)
    51ee:	4605      	mov	r5, r0
    51f0:	b158      	cbz	r0, 520a <onoff_manager_init+0x20>
	    || (transitions == NULL)
    51f2:	b151      	cbz	r1, 520a <onoff_manager_init+0x20>
	    || (transitions->start == NULL)
    51f4:	680b      	ldr	r3, [r1, #0]
    51f6:	b143      	cbz	r3, 520a <onoff_manager_init+0x20>
	    || (transitions->stop == NULL)) {
    51f8:	684b      	ldr	r3, [r1, #4]
    51fa:	b133      	cbz	r3, 520a <onoff_manager_init+0x20>
	*mgr = (struct onoff_manager)ONOFF_MANAGER_INITIALIZER(transitions);
    51fc:	221c      	movs	r2, #28
    51fe:	2100      	movs	r1, #0
    5200:	f000 fb95 	bl	592e <memset>
	return 0;
    5204:	2000      	movs	r0, #0
	*mgr = (struct onoff_manager)ONOFF_MANAGER_INITIALIZER(transitions);
    5206:	612c      	str	r4, [r5, #16]
}
    5208:	bd38      	pop	{r3, r4, r5, pc}
		return -EINVAL;
    520a:	f06f 0015 	mvn.w	r0, #21
    520e:	e7fb      	b.n	5208 <onoff_manager_init+0x1e>

00005210 <onoff_request>:

int onoff_request(struct onoff_manager *mgr,
		  struct onoff_client *cli)
{
    5210:	b570      	push	{r4, r5, r6, lr}
    5212:	4604      	mov	r4, r0
    5214:	460e      	mov	r6, r1
	bool add_client = false;        /* add client to pending list */
	bool start = false;             /* trigger a start transition */
	bool notify = false;            /* do client notification */
	int rv = validate_args(mgr, cli);
    5216:	f7ff ffd9 	bl	51cc <validate_args>

	if (rv < 0) {
    521a:	1e05      	subs	r5, r0, #0
    521c:	db31      	blt.n	5282 <onoff_request+0x72>
    521e:	f04f 0320 	mov.w	r3, #32
    5222:	f3ef 8111 	mrs	r1, BASEPRI
    5226:	f383 8811 	msr	BASEPRI, r3
    522a:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&mgr->lock);
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;

	/* Reject if this would overflow the reference count. */
	if (mgr->refs == SERVICE_REFS_MAX) {
    522e:	f64f 75ff 	movw	r5, #65535	; 0xffff
    5232:	8b63      	ldrh	r3, [r4, #26]
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    5234:	8b20      	ldrh	r0, [r4, #24]
	if (mgr->refs == SERVICE_REFS_MAX) {
    5236:	42ab      	cmp	r3, r5
    5238:	f000 0207 	and.w	r2, r0, #7
    523c:	d02e      	beq.n	529c <onoff_request+0x8c>
		rv = -EAGAIN;
		goto out;
	}

	rv = state;
	if (state == ONOFF_STATE_ON) {
    523e:	2a02      	cmp	r2, #2
    5240:	d10e      	bne.n	5260 <onoff_request+0x50>
		/* Increment reference count, notify in exit */
		notify = true;
		mgr->refs += 1U;
    5242:	3301      	adds	r3, #1
    5244:	8363      	strh	r3, [r4, #26]
	rv = state;
    5246:	4615      	mov	r5, r2
		notify = true;
    5248:	2301      	movs	r3, #1
	__asm__ volatile(
    524a:	f381 8811 	msr	BASEPRI, r1
    524e:	f3bf 8f6f 	isb	sy
	if (start) {
		process_event(mgr, EVT_RECHECK, key);
	} else {
		k_spin_unlock(&mgr->lock, key);

		if (notify) {
    5252:	b1b3      	cbz	r3, 5282 <onoff_request+0x72>
			notify_one(mgr, cli, state, 0);
    5254:	2300      	movs	r3, #0
    5256:	4631      	mov	r1, r6
    5258:	4620      	mov	r0, r4
    525a:	f7ff ff92 	bl	5182 <notify_one>
    525e:	e010      	b.n	5282 <onoff_request+0x72>
	} else if ((state == ONOFF_STATE_OFF)
    5260:	0783      	lsls	r3, r0, #30
    5262:	d001      	beq.n	5268 <onoff_request+0x58>
		   || (state == ONOFF_STATE_TO_ON)) {
    5264:	2a06      	cmp	r2, #6
    5266:	d10e      	bne.n	5286 <onoff_request+0x76>
	parent->next = child;
    5268:	2300      	movs	r3, #0
    526a:	6033      	str	r3, [r6, #0]
Z_GENLIST_APPEND(slist, snode)
    526c:	6863      	ldr	r3, [r4, #4]
    526e:	b993      	cbnz	r3, 5296 <onoff_request+0x86>
	list->head = node;
    5270:	e9c4 6600 	strd	r6, r6, [r4]
	if (start) {
    5274:	4615      	mov	r5, r2
    5276:	b962      	cbnz	r2, 5292 <onoff_request+0x82>
		process_event(mgr, EVT_RECHECK, key);
    5278:	460a      	mov	r2, r1
    527a:	4620      	mov	r0, r4
    527c:	2102      	movs	r1, #2
    527e:	f7fb f9af 	bl	5e0 <process_event>
		}
	}

	return rv;
}
    5282:	4628      	mov	r0, r5
    5284:	bd70      	pop	{r4, r5, r6, pc}
		rv = -EIO;
    5286:	2a05      	cmp	r2, #5
    5288:	bf0c      	ite	eq
    528a:	f06f 0522 	mvneq.w	r5, #34	; 0x22
    528e:	f06f 0504 	mvnne.w	r5, #4
    5292:	2300      	movs	r3, #0
    5294:	e7d9      	b.n	524a <onoff_request+0x3a>
	parent->next = child;
    5296:	601e      	str	r6, [r3, #0]
	list->tail = node;
    5298:	6066      	str	r6, [r4, #4]
}
    529a:	e7eb      	b.n	5274 <onoff_request+0x64>
		rv = -EAGAIN;
    529c:	f06f 050a 	mvn.w	r5, #10
    52a0:	e7f7      	b.n	5292 <onoff_request+0x82>

000052a2 <z_thread_entry>:
 * This routine does not return, and is marked as such so the compiler won't
 * generate preamble code that is only used by functions that actually return.
 */
FUNC_NORETURN void z_thread_entry(k_thread_entry_t entry,
				 void *p1, void *p2, void *p3)
{
    52a2:	4604      	mov	r4, r0
    52a4:	b508      	push	{r3, lr}
    52a6:	4608      	mov	r0, r1
    52a8:	4611      	mov	r1, r2
	entry(p1, p2, p3);
    52aa:	461a      	mov	r2, r3
    52ac:	47a0      	blx	r4
	return z_impl_k_current_get();
    52ae:	f7fe fd43 	bl	3d38 <z_impl_k_current_get>
	z_impl_k_thread_abort(thread);
    52b2:	f7fd f9a1 	bl	25f8 <z_impl_k_thread_abort>

000052b6 <chunk_field>:
				 enum chunk_fields f)
{
	chunk_unit_t *buf = chunk_buf(h);
	void *cmem = &buf[c];

	if (big_heap(h)) {
    52b6:	6883      	ldr	r3, [r0, #8]
	void *cmem = &buf[c];
    52b8:	eb00 01c1 	add.w	r1, r0, r1, lsl #3
	if (big_heap(h)) {
    52bc:	f5b3 4f00 	cmp.w	r3, #32768	; 0x8000
		return ((uint32_t *)cmem)[f];
    52c0:	bf2c      	ite	cs
    52c2:	f851 0022 	ldrcs.w	r0, [r1, r2, lsl #2]
	} else {
		return ((uint16_t *)cmem)[f];
    52c6:	f831 0012 	ldrhcc.w	r0, [r1, r2, lsl #1]
	}
}
    52ca:	4770      	bx	lr

000052cc <chunk_set>:
			     enum chunk_fields f, chunkid_t val)
{
	CHECK(c <= h->len);

	chunk_unit_t *buf = chunk_buf(h);
	void *cmem = &buf[c];
    52cc:	eb00 01c1 	add.w	r1, r0, r1, lsl #3

	if (big_heap(h)) {
    52d0:	6880      	ldr	r0, [r0, #8]
    52d2:	f5b0 4f00 	cmp.w	r0, #32768	; 0x8000
		CHECK(val == (uint32_t)val);
		((uint32_t *)cmem)[f] = val;
    52d6:	bf2c      	ite	cs
    52d8:	f841 3022 	strcs.w	r3, [r1, r2, lsl #2]
	} else {
		CHECK(val == (uint16_t)val);
		((uint16_t *)cmem)[f] = val;
    52dc:	f821 3012 	strhcc.w	r3, [r1, r2, lsl #1]
	}
}
    52e0:	4770      	bx	lr

000052e2 <chunk_size>:
	return chunk_field(h, c, SIZE_AND_USED) & 1U;
}

static inline size_t chunk_size(struct z_heap *h, chunkid_t c)
{
	return chunk_field(h, c, SIZE_AND_USED) >> 1;
    52e2:	2201      	movs	r2, #1
{
    52e4:	b508      	push	{r3, lr}
	return chunk_field(h, c, SIZE_AND_USED) >> 1;
    52e6:	f7ff ffe6 	bl	52b6 <chunk_field>
}
    52ea:	0840      	lsrs	r0, r0, #1
    52ec:	bd08      	pop	{r3, pc}

000052ee <set_chunk_used>:
static inline void set_chunk_used(struct z_heap *h, chunkid_t c, bool used)
{
	chunk_unit_t *buf = chunk_buf(h);
	void *cmem = &buf[c];

	if (big_heap(h)) {
    52ee:	6883      	ldr	r3, [r0, #8]
	void *cmem = &buf[c];
    52f0:	eb00 01c1 	add.w	r1, r0, r1, lsl #3
	if (big_heap(h)) {
    52f4:	f5b3 4f00 	cmp.w	r3, #32768	; 0x8000
    52f8:	d308      	bcc.n	530c <set_chunk_used+0x1e>
		if (used) {
    52fa:	684b      	ldr	r3, [r1, #4]
    52fc:	b11a      	cbz	r2, 5306 <set_chunk_used+0x18>
			((uint32_t *)cmem)[SIZE_AND_USED] |= 1U;
    52fe:	f043 0301 	orr.w	r3, r3, #1
		} else {
			((uint32_t *)cmem)[SIZE_AND_USED] &= ~1U;
    5302:	604b      	str	r3, [r1, #4]
    5304:	4770      	bx	lr
    5306:	f023 0301 	bic.w	r3, r3, #1
    530a:	e7fa      	b.n	5302 <set_chunk_used+0x14>
		}
	} else {
		if (used) {
    530c:	884b      	ldrh	r3, [r1, #2]
    530e:	b11a      	cbz	r2, 5318 <set_chunk_used+0x2a>
			((uint16_t *)cmem)[SIZE_AND_USED] |= 1U;
    5310:	f043 0301 	orr.w	r3, r3, #1
		} else {
			((uint16_t *)cmem)[SIZE_AND_USED] &= ~1U;
    5314:	804b      	strh	r3, [r1, #2]
		}
	}
}
    5316:	4770      	bx	lr
			((uint16_t *)cmem)[SIZE_AND_USED] &= ~1U;
    5318:	f023 0301 	bic.w	r3, r3, #1
    531c:	e7fa      	b.n	5314 <set_chunk_used+0x26>

0000531e <set_chunk_size>:
 * when its size is modified, and potential set_chunk_used() is always
 * invoked after set_chunk_size().
 */
static inline void set_chunk_size(struct z_heap *h, chunkid_t c, size_t size)
{
	chunk_set(h, c, SIZE_AND_USED, size << 1);
    531e:	0053      	lsls	r3, r2, #1
    5320:	2201      	movs	r2, #1
    5322:	f7ff bfd3 	b.w	52cc <chunk_set>

00005326 <bucket_idx>:
	return big_heap(h) && chunk_size(h, c) == 1U;
}

static inline size_t chunk_header_bytes(struct z_heap *h)
{
	return big_heap(h) ? 8 : 4;
    5326:	6880      	ldr	r0, [r0, #8]
	return bytes_to_chunksz(h, 1);
}

static inline int bucket_idx(struct z_heap *h, size_t sz)
{
	size_t usable_sz = sz - min_chunk_size(h) + 1;
    5328:	3101      	adds	r1, #1
	return (bytes + CHUNK_UNIT - 1U) / CHUNK_UNIT;
    532a:	f5b0 4f00 	cmp.w	r0, #32768	; 0x8000
    532e:	bf2c      	ite	cs
    5330:	2002      	movcs	r0, #2
    5332:	2001      	movcc	r0, #1
	size_t usable_sz = sz - min_chunk_size(h) + 1;
    5334:	1a08      	subs	r0, r1, r0
	return 31 - __builtin_clz(usable_sz);
    5336:	fab0 f080 	clz	r0, r0
}
    533a:	f1c0 001f 	rsb	r0, r0, #31
    533e:	4770      	bx	lr

00005340 <free_list_add>:
		set_prev_free_chunk(h, second, c);
	}
}

static void free_list_add(struct z_heap *h, chunkid_t c)
{
    5340:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    5344:	4604      	mov	r4, r0
    5346:	460d      	mov	r5, r1
	return sizeof(void *) > 4U || chunks > 0x7fffU;
    5348:	f7ff ffcb 	bl	52e2 <chunk_size>
	return big_heap(h) && chunk_size(h, c) == 1U;
    534c:	68a3      	ldr	r3, [r4, #8]
    534e:	4601      	mov	r1, r0
    5350:	f5b3 4f00 	cmp.w	r3, #32768	; 0x8000
    5354:	d301      	bcc.n	535a <free_list_add+0x1a>
	if (!solo_free_header(h, c)) {
    5356:	2801      	cmp	r0, #1
    5358:	d035      	beq.n	53c6 <free_list_add+0x86>
		int bidx = bucket_idx(h, chunk_size(h, c));
    535a:	4620      	mov	r0, r4
    535c:	f7ff ffe3 	bl	5326 <bucket_idx>
	if (b->next == 0U) {
    5360:	eb04 0280 	add.w	r2, r4, r0, lsl #2
    5364:	6916      	ldr	r6, [r2, #16]
    5366:	b99e      	cbnz	r6, 5390 <free_list_add+0x50>
		h->avail_buckets |= (1 << bidx);
    5368:	2301      	movs	r3, #1
    536a:	fa03 f000 	lsl.w	r0, r3, r0
    536e:	68e3      	ldr	r3, [r4, #12]
	chunk_set(h, c, FREE_PREV, prev);
    5370:	4629      	mov	r1, r5
    5372:	4303      	orrs	r3, r0
    5374:	60e3      	str	r3, [r4, #12]
    5376:	4620      	mov	r0, r4
		b->next = c;
    5378:	6115      	str	r5, [r2, #16]
    537a:	462b      	mov	r3, r5
    537c:	2202      	movs	r2, #2
    537e:	f7ff ffa5 	bl	52cc <chunk_set>
	chunk_set(h, c, FREE_NEXT, next);
    5382:	2203      	movs	r2, #3
    5384:	4629      	mov	r1, r5
	chunk_set(h, c, FREE_PREV, prev);
    5386:	4620      	mov	r0, r4
		free_list_add_bidx(h, c, bidx);
	}
}
    5388:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
    538c:	f7ff bf9e 	b.w	52cc <chunk_set>
	return chunk_field(h, c, FREE_PREV);
    5390:	2202      	movs	r2, #2
    5392:	4631      	mov	r1, r6
    5394:	4620      	mov	r0, r4
    5396:	f7ff ff8e 	bl	52b6 <chunk_field>
    539a:	4607      	mov	r7, r0
	chunk_set(h, c, FREE_PREV, prev);
    539c:	4603      	mov	r3, r0
    539e:	2202      	movs	r2, #2
    53a0:	4629      	mov	r1, r5
    53a2:	4620      	mov	r0, r4
    53a4:	f7ff ff92 	bl	52cc <chunk_set>
	chunk_set(h, c, FREE_NEXT, next);
    53a8:	4633      	mov	r3, r6
    53aa:	2203      	movs	r2, #3
    53ac:	4629      	mov	r1, r5
    53ae:	4620      	mov	r0, r4
    53b0:	f7ff ff8c 	bl	52cc <chunk_set>
    53b4:	2203      	movs	r2, #3
    53b6:	4639      	mov	r1, r7
    53b8:	462b      	mov	r3, r5
    53ba:	4620      	mov	r0, r4
    53bc:	f7ff ff86 	bl	52cc <chunk_set>
	chunk_set(h, c, FREE_PREV, prev);
    53c0:	2202      	movs	r2, #2
    53c2:	4631      	mov	r1, r6
    53c4:	e7df      	b.n	5386 <free_list_add+0x46>
    53c6:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

000053ca <sys_heap_init>:
	return big_heap_bytes(size) ? 8 : 4;
    53ca:	f5b2 2f80 	cmp.w	r2, #262144	; 0x40000
		return ptr2;
	}
}

void sys_heap_init(struct sys_heap *heap, void *mem, size_t bytes)
{
    53ce:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    53d0:	bf2c      	ite	cs
    53d2:	2508      	movcs	r5, #8
    53d4:	2504      	movcc	r5, #4
	CHECK(end > addr);
	__ASSERT(buf_sz > chunksz(sizeof(struct z_heap)), "heap size is too small");

	struct z_heap *h = (struct z_heap *)addr;
	heap->heap = h;
	h->chunk0_hdr_area = 0;
    53d6:	2300      	movs	r3, #0
	bytes -= heap_footer_bytes(bytes);
    53d8:	1b55      	subs	r5, r2, r5
	h->chunk0_hdr_area = 0;
    53da:	2200      	movs	r2, #0
	uintptr_t addr = ROUND_UP(mem, CHUNK_UNIT);
    53dc:	1dcc      	adds	r4, r1, #7
    53de:	f024 0407 	bic.w	r4, r4, #7
	heap->heap = h;
    53e2:	6004      	str	r4, [r0, #0]
	h->chunk0_hdr_area = 0;
    53e4:	e9c4 2300 	strd	r2, r3, [r4]
	h->len = buf_sz;
	h->avail_buckets = 0;
    53e8:	2300      	movs	r3, #0
	uintptr_t end = ROUND_DOWN((uint8_t *)mem + bytes, CHUNK_UNIT);
    53ea:	440d      	add	r5, r1
    53ec:	f025 0507 	bic.w	r5, r5, #7
	size_t buf_sz = (end - addr) / CHUNK_UNIT;
    53f0:	1b2d      	subs	r5, r5, r4
    53f2:	08ed      	lsrs	r5, r5, #3

	int nb_buckets = bucket_idx(h, buf_sz) + 1;
    53f4:	4629      	mov	r1, r5
    53f6:	4620      	mov	r0, r4
	h->len = buf_sz;
    53f8:	60a5      	str	r5, [r4, #8]
	h->avail_buckets = 0;
    53fa:	60e3      	str	r3, [r4, #12]
	int nb_buckets = bucket_idx(h, buf_sz) + 1;
    53fc:	f7ff ff93 	bl	5326 <bucket_idx>
	size_t chunk0_size = chunksz(sizeof(struct z_heap) +
    5400:	0086      	lsls	r6, r0, #2
	int nb_buckets = bucket_idx(h, buf_sz) + 1;
    5402:	1c41      	adds	r1, r0, #1
				     nb_buckets * sizeof(struct z_heap_bucket));

	__ASSERT(chunk0_size + min_chunk_size(h) < buf_sz, "heap size is too small");

	for (int i = 0; i < nb_buckets; i++) {
		h->buckets[i].next = 0;
    5404:	4618      	mov	r0, r3
	return (bytes + CHUNK_UNIT - 1U) / CHUNK_UNIT;
    5406:	361b      	adds	r6, #27
    5408:	08f6      	lsrs	r6, r6, #3
	for (int i = 0; i < nb_buckets; i++) {
    540a:	f104 0210 	add.w	r2, r4, #16
    540e:	428b      	cmp	r3, r1
    5410:	db29      	blt.n	5466 <sys_heap_init+0x9c>
	}

	/* chunk containing our struct z_heap */
	set_chunk_size(h, 0, chunk0_size);
    5412:	4632      	mov	r2, r6
    5414:	4620      	mov	r0, r4
    5416:	2100      	movs	r1, #0
    5418:	f7ff ff81 	bl	531e <set_chunk_size>
	set_chunk_used(h, 0, true);

	/* chunk containing the free heap */
	set_chunk_size(h, chunk0_size, buf_sz - chunk0_size);
    541c:	1baf      	subs	r7, r5, r6
	set_chunk_used(h, 0, true);
    541e:	4620      	mov	r0, r4
    5420:	2201      	movs	r2, #1
    5422:	2100      	movs	r1, #0
    5424:	f7ff ff63 	bl	52ee <set_chunk_used>
	set_chunk_size(h, chunk0_size, buf_sz - chunk0_size);
    5428:	463a      	mov	r2, r7
    542a:	4631      	mov	r1, r6
    542c:	f7ff ff77 	bl	531e <set_chunk_size>
	chunk_set(h, c, LEFT_SIZE, size);
    5430:	4633      	mov	r3, r6
    5432:	4631      	mov	r1, r6
    5434:	4620      	mov	r0, r4
    5436:	2200      	movs	r2, #0
    5438:	f7ff ff48 	bl	52cc <chunk_set>
	set_left_chunk_size(h, chunk0_size, chunk0_size);

	/* the end marker chunk */
	set_chunk_size(h, buf_sz, 0);
    543c:	4629      	mov	r1, r5
    543e:	4620      	mov	r0, r4
    5440:	2200      	movs	r2, #0
    5442:	f7ff ff6c 	bl	531e <set_chunk_size>
    5446:	463b      	mov	r3, r7
    5448:	4629      	mov	r1, r5
    544a:	4620      	mov	r0, r4
    544c:	2200      	movs	r2, #0
    544e:	f7ff ff3d 	bl	52cc <chunk_set>
	set_left_chunk_size(h, buf_sz, buf_sz - chunk0_size);
	set_chunk_used(h, buf_sz, true);
    5452:	4629      	mov	r1, r5
    5454:	4620      	mov	r0, r4
    5456:	2201      	movs	r2, #1
    5458:	f7ff ff49 	bl	52ee <set_chunk_used>

	free_list_add(h, chunk0_size);
    545c:	4631      	mov	r1, r6
}
    545e:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
	free_list_add(h, chunk0_size);
    5462:	f7ff bf6d 	b.w	5340 <free_list_add>
		h->buckets[i].next = 0;
    5466:	f842 0b04 	str.w	r0, [r2], #4
	for (int i = 0; i < nb_buckets; i++) {
    546a:	3301      	adds	r3, #1
    546c:	e7cf      	b.n	540e <sys_heap_init+0x44>

0000546e <_ldiv5>:
{
    546e:	e92d 48f0 	stmdb	sp!, {r4, r5, r6, r7, fp, lr}
	uint32_t v_lo = *v;
    5472:	e9d0 2400 	ldrd	r2, r4, [r0]
	__asm__ ("" : "+r" (m));
    5476:	f04f 3333 	mov.w	r3, #858993459	; 0x33333333
	result += (uint64_t)v_lo * m;
    547a:	fba2 bc03 	umull	fp, ip, r2, r3
    547e:	eb1b 0603 	adds.w	r6, fp, r3
    5482:	eb4c 0503 	adc.w	r5, ip, r3
	result >>= 32;
    5486:	462f      	mov	r7, r5
    5488:	2600      	movs	r6, #0
	result += (uint64_t)v_hi * m;
    548a:	fba4 4503 	umull	r4, r5, r4, r3
    548e:	eb1b 0204 	adds.w	r2, fp, r4
    5492:	eb4c 0105 	adc.w	r1, ip, r5
    5496:	19d2      	adds	r2, r2, r7
	result >>= 32;
    5498:	4632      	mov	r2, r6
	result += (uint64_t)v_hi * m;
    549a:	eb46 0101 	adc.w	r1, r6, r1
	result += (uint64_t)v_hi * m;
    549e:	1863      	adds	r3, r4, r1
    54a0:	eb45 0202 	adc.w	r2, r5, r2
	*v = result;
    54a4:	e9c0 3200 	strd	r3, r2, [r0]
}
    54a8:	e8bd 88f0 	ldmia.w	sp!, {r4, r5, r6, r7, fp, pc}

000054ac <_get_digit>:
	if (*digit_count > 0) {
    54ac:	680b      	ldr	r3, [r1, #0]
{
    54ae:	b570      	push	{r4, r5, r6, lr}
	if (*digit_count > 0) {
    54b0:	2b00      	cmp	r3, #0
    54b2:	dd10      	ble.n	54d6 <_get_digit+0x2a>
		--*digit_count;
    54b4:	3b01      	subs	r3, #1
    54b6:	600b      	str	r3, [r1, #0]
		*fr *= 10U;
    54b8:	210a      	movs	r1, #10
    54ba:	6802      	ldr	r2, [r0, #0]
    54bc:	6844      	ldr	r4, [r0, #4]
    54be:	fba2 5601 	umull	r5, r6, r2, r1
    54c2:	fb01 6604 	mla	r6, r1, r4, r6
		*fr &= (BIT64(60) - 1U);
    54c6:	f026 4370 	bic.w	r3, r6, #4026531840	; 0xf0000000
    54ca:	e9c0 5300 	strd	r5, r3, [r0]
		rval = ((*fr >> 60) & 0xF) + '0';
    54ce:	0f31      	lsrs	r1, r6, #28
    54d0:	3130      	adds	r1, #48	; 0x30
}
    54d2:	4608      	mov	r0, r1
    54d4:	bd70      	pop	{r4, r5, r6, pc}
		rval = '0';
    54d6:	2130      	movs	r1, #48	; 0x30
    54d8:	e7fb      	b.n	54d2 <_get_digit+0x26>

000054da <encode_uint>:
{
    54da:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    54de:	4699      	mov	r9, r3
	bool upcase = isupper((int)conv->specifier);
    54e0:	78d3      	ldrb	r3, [r2, #3]
{
    54e2:	4614      	mov	r4, r2
	switch (specifier) {
    54e4:	2b6f      	cmp	r3, #111	; 0x6f
	return (int)(((unsigned)(a)-(unsigned)'A') < 26U);
    54e6:	f1a3 0241 	sub.w	r2, r3, #65	; 0x41
{
    54ea:	4606      	mov	r6, r0
    54ec:	460f      	mov	r7, r1
    54ee:	9201      	str	r2, [sp, #4]
	switch (specifier) {
    54f0:	d02d      	beq.n	554e <encode_uint+0x74>
    54f2:	d828      	bhi.n	5546 <encode_uint+0x6c>
		return 16;
    54f4:	2b58      	cmp	r3, #88	; 0x58
    54f6:	bf14      	ite	ne
    54f8:	250a      	movne	r5, #10
    54fa:	2510      	moveq	r5, #16
		unsigned int lsv = (unsigned int)(value % radix);
    54fc:	46aa      	mov	sl, r5
    54fe:	f04f 0b00 	mov.w	fp, #0
	char *bp = bps + (bpe - bps);
    5502:	f8dd 8030 	ldr.w	r8, [sp, #48]	; 0x30
		unsigned int lsv = (unsigned int)(value % radix);
    5506:	4652      	mov	r2, sl
    5508:	465b      	mov	r3, fp
    550a:	4630      	mov	r0, r6
    550c:	4639      	mov	r1, r7
    550e:	f7fa fe95 	bl	23c <__aeabi_uldivmod>
		*--bp = (lsv <= 9) ? ('0' + lsv)
    5512:	2a09      	cmp	r2, #9
    5514:	b2d3      	uxtb	r3, r2
    5516:	d81f      	bhi.n	5558 <encode_uint+0x7e>
    5518:	3330      	adds	r3, #48	; 0x30
	} while ((value != 0) && (bps < bp));
    551a:	455f      	cmp	r7, fp
		*--bp = (lsv <= 9) ? ('0' + lsv)
    551c:	b2db      	uxtb	r3, r3
	} while ((value != 0) && (bps < bp));
    551e:	bf08      	it	eq
    5520:	4556      	cmpeq	r6, sl
		*--bp = (lsv <= 9) ? ('0' + lsv)
    5522:	f808 3d01 	strb.w	r3, [r8, #-1]!
	} while ((value != 0) && (bps < bp));
    5526:	d301      	bcc.n	552c <encode_uint+0x52>
    5528:	45c8      	cmp	r8, r9
    552a:	d812      	bhi.n	5552 <encode_uint+0x78>
	if (conv->flag_hash) {
    552c:	7823      	ldrb	r3, [r4, #0]
    552e:	069b      	lsls	r3, r3, #26
    5530:	d505      	bpl.n	553e <encode_uint+0x64>
		if (radix == 8) {
    5532:	2d08      	cmp	r5, #8
    5534:	d116      	bne.n	5564 <encode_uint+0x8a>
			conv->altform_0 = true;
    5536:	78a3      	ldrb	r3, [r4, #2]
    5538:	f043 0308 	orr.w	r3, r3, #8
			conv->altform_0c = true;
    553c:	70a3      	strb	r3, [r4, #2]
}
    553e:	4640      	mov	r0, r8
    5540:	b003      	add	sp, #12
    5542:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
	switch (specifier) {
    5546:	f003 03f7 	and.w	r3, r3, #247	; 0xf7
		return 16;
    554a:	2b70      	cmp	r3, #112	; 0x70
    554c:	e7d3      	b.n	54f6 <encode_uint+0x1c>
	switch (specifier) {
    554e:	2508      	movs	r5, #8
    5550:	e7d4      	b.n	54fc <encode_uint+0x22>
		value /= radix;
    5552:	4606      	mov	r6, r0
    5554:	460f      	mov	r7, r1
    5556:	e7d6      	b.n	5506 <encode_uint+0x2c>
		*--bp = (lsv <= 9) ? ('0' + lsv)
    5558:	9a01      	ldr	r2, [sp, #4]
    555a:	2a19      	cmp	r2, #25
    555c:	bf94      	ite	ls
    555e:	3337      	addls	r3, #55	; 0x37
    5560:	3357      	addhi	r3, #87	; 0x57
    5562:	e7da      	b.n	551a <encode_uint+0x40>
		} else if (radix == 16) {
    5564:	2d10      	cmp	r5, #16
    5566:	d1ea      	bne.n	553e <encode_uint+0x64>
			conv->altform_0c = true;
    5568:	78a3      	ldrb	r3, [r4, #2]
    556a:	f043 0310 	orr.w	r3, r3, #16
    556e:	e7e5      	b.n	553c <encode_uint+0x62>

00005570 <outs>:
{
    5570:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    5574:	4680      	mov	r8, r0
    5576:	4689      	mov	r9, r1
    5578:	4616      	mov	r6, r2
    557a:	461f      	mov	r7, r3
	while ((sp < ep) || ((ep == NULL) && *sp)) {
    557c:	4615      	mov	r5, r2
    557e:	42bd      	cmp	r5, r7
    5580:	eba5 0406 	sub.w	r4, r5, r6
    5584:	d305      	bcc.n	5592 <outs+0x22>
    5586:	b10f      	cbz	r7, 558c <outs+0x1c>
	return (int)count;
    5588:	4620      	mov	r0, r4
    558a:	e008      	b.n	559e <outs+0x2e>
	while ((sp < ep) || ((ep == NULL) && *sp)) {
    558c:	782b      	ldrb	r3, [r5, #0]
    558e:	2b00      	cmp	r3, #0
    5590:	d0fa      	beq.n	5588 <outs+0x18>
		int rc = out((int)*sp++, ctx);
    5592:	4649      	mov	r1, r9
    5594:	f815 0b01 	ldrb.w	r0, [r5], #1
    5598:	47c0      	blx	r8
		if (rc < 0) {
    559a:	2800      	cmp	r0, #0
    559c:	daef      	bge.n	557e <outs+0xe>
}
    559e:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}

000055a2 <_ConfigAbsSyms>:
GEN_ABSOLUTE_SYM(CONFIG_OUTPUT_PRINT_MEMORY_USAGE, 1);
GEN_ABSOLUTE_SYM(CONFIG_BUILD_OUTPUT_BIN, 1);
GEN_ABSOLUTE_SYM(CONFIG_REBOOT, 1);
GEN_ABSOLUTE_SYM(CONFIG_COMPAT_INCLUDES, 1);

GEN_ABS_SYM_END
    55a2:	4770      	bx	lr

000055a4 <z_platform_init>:

void z_platform_init(void)
{
	SystemInit();
    55a4:	f7fd bc5a 	b.w	2e5c <SystemInit>

000055a8 <get_status>:
	return GET_STATUS(get_sub_data(dev, type)->flags);
    55a8:	b2cb      	uxtb	r3, r1
    55aa:	210c      	movs	r1, #12
    55ac:	68c2      	ldr	r2, [r0, #12]
    55ae:	fb03 2101 	mla	r1, r3, r1, r2
    55b2:	6c08      	ldr	r0, [r1, #64]	; 0x40
}
    55b4:	f000 0007 	and.w	r0, r0, #7
    55b8:	4770      	bx	lr

000055ba <set_off_state>:
	__asm__ volatile(
    55ba:	f04f 0320 	mov.w	r3, #32
    55be:	f3ef 8211 	mrs	r2, BASEPRI
    55c2:	f383 8811 	msr	BASEPRI, r3
    55c6:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    55ca:	6803      	ldr	r3, [r0, #0]
	if ((current_ctx != 0) && (current_ctx != ctx)) {
    55cc:	f013 03c0 	ands.w	r3, r3, #192	; 0xc0
    55d0:	d001      	beq.n	55d6 <set_off_state+0x1c>
    55d2:	428b      	cmp	r3, r1
    55d4:	d107      	bne.n	55e6 <set_off_state+0x2c>
		*flags = CLOCK_CONTROL_STATUS_OFF;
    55d6:	2301      	movs	r3, #1
    55d8:	6003      	str	r3, [r0, #0]
	int err = 0;
    55da:	2000      	movs	r0, #0
	__asm__ volatile(
    55dc:	f382 8811 	msr	BASEPRI, r2
    55e0:	f3bf 8f6f 	isb	sy
}
    55e4:	4770      	bx	lr
		err = -EPERM;
    55e6:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
    55ea:	e7f7      	b.n	55dc <set_off_state+0x22>

000055ec <set_starting_state>:
{
    55ec:	b510      	push	{r4, lr}
	__asm__ volatile(
    55ee:	f04f 0320 	mov.w	r3, #32
    55f2:	f3ef 8211 	mrs	r2, BASEPRI
    55f6:	f383 8811 	msr	BASEPRI, r3
    55fa:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    55fe:	6803      	ldr	r3, [r0, #0]
	if ((*flags & (STATUS_MASK)) == CLOCK_CONTROL_STATUS_OFF) {
    5600:	f003 0407 	and.w	r4, r3, #7
    5604:	2c01      	cmp	r4, #1
    5606:	d106      	bne.n	5616 <set_starting_state+0x2a>
		*flags = CLOCK_CONTROL_STATUS_STARTING | ctx;
    5608:	6001      	str	r1, [r0, #0]
	int err = 0;
    560a:	2000      	movs	r0, #0
	__asm__ volatile(
    560c:	f382 8811 	msr	BASEPRI, r2
    5610:	f3bf 8f6f 	isb	sy
}
    5614:	bd10      	pop	{r4, pc}
	uint32_t current_ctx = GET_CTX(*flags);
    5616:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
	} else if (current_ctx != ctx) {
    561a:	428b      	cmp	r3, r1
		err = -EALREADY;
    561c:	bf14      	ite	ne
    561e:	f04f 30ff 	movne.w	r0, #4294967295	; 0xffffffff
    5622:	f06f 0044 	mvneq.w	r0, #68	; 0x44
    5626:	e7f1      	b.n	560c <set_starting_state+0x20>

00005628 <set_on_state>:
	__asm__ volatile(
    5628:	f04f 0320 	mov.w	r3, #32
    562c:	f3ef 8211 	mrs	r2, BASEPRI
    5630:	f383 8811 	msr	BASEPRI, r3
    5634:	f3bf 8f6f 	isb	sy
	*flags = CLOCK_CONTROL_STATUS_ON | GET_CTX(*flags);
    5638:	6803      	ldr	r3, [r0, #0]
    563a:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
    563e:	f043 0302 	orr.w	r3, r3, #2
    5642:	6003      	str	r3, [r0, #0]
	__asm__ volatile(
    5644:	f382 8811 	msr	BASEPRI, r2
    5648:	f3bf 8f6f 	isb	sy
}
    564c:	4770      	bx	lr

0000564e <onoff_started_callback>:
{
    564e:	b410      	push	{r4}
	notify(mgr, 0);
    5650:	241c      	movs	r4, #28
	return &data->mgr[type];
    5652:	68c0      	ldr	r0, [r0, #12]
    5654:	b2cb      	uxtb	r3, r1
	notify(mgr, 0);
    5656:	fb03 0004 	mla	r0, r3, r4, r0
    565a:	2100      	movs	r1, #0
}
    565c:	f85d 4b04 	ldr.w	r4, [sp], #4
	notify(mgr, 0);
    5660:	4710      	bx	r2

00005662 <lfclk_start>:
    nrfx_clock_start(NRF_CLOCK_DOMAIN_LFCLK);
    5662:	2000      	movs	r0, #0
    5664:	f7fd bcc4 	b.w	2ff0 <nrfx_clock_start>

00005668 <lfclk_stop>:
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
    5668:	2000      	movs	r0, #0
    566a:	f7fd bcf3 	b.w	3054 <nrfx_clock_stop>

0000566e <blocking_start_callback>:
{
    566e:	4610      	mov	r0, r2
		arch_syscall_invoke1(*(uintptr_t *)&sem, K_SYSCALL_K_SEM_GIVE);
		return;
	}
#endif
	compiler_barrier();
	z_impl_k_sem_give(sem);
    5670:	f7fe bb68 	b.w	3d44 <z_impl_k_sem_give>

00005674 <api_stop>:
{
    5674:	b538      	push	{r3, r4, r5, lr}
	err = set_off_state(&subdata->flags, ctx);
    5676:	230c      	movs	r3, #12
    5678:	b2cc      	uxtb	r4, r1
    567a:	4363      	muls	r3, r4
{
    567c:	4605      	mov	r5, r0
	err = set_off_state(&subdata->flags, ctx);
    567e:	68c0      	ldr	r0, [r0, #12]
    5680:	3340      	adds	r3, #64	; 0x40
    5682:	2180      	movs	r1, #128	; 0x80
    5684:	4418      	add	r0, r3
    5686:	f7ff ff98 	bl	55ba <set_off_state>
	if (err < 0) {
    568a:	2800      	cmp	r0, #0
    568c:	db05      	blt.n	569a <api_stop+0x26>
	get_sub_config(dev, type)->stop();
    568e:	6869      	ldr	r1, [r5, #4]
    5690:	eb01 04c4 	add.w	r4, r1, r4, lsl #3
    5694:	6863      	ldr	r3, [r4, #4]
    5696:	4798      	blx	r3
	return 0;
    5698:	2000      	movs	r0, #0
}
    569a:	bd38      	pop	{r3, r4, r5, pc}

0000569c <api_start>:
{
    569c:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
	err = set_starting_state(&subdata->flags, ctx);
    56a0:	270c      	movs	r7, #12
    56a2:	b2cd      	uxtb	r5, r1
    56a4:	436f      	muls	r7, r5
	struct nrf_clock_control_sub_data *subdata = get_sub_data(dev, type);
    56a6:	68c4      	ldr	r4, [r0, #12]
{
    56a8:	4606      	mov	r6, r0
	err = set_starting_state(&subdata->flags, ctx);
    56aa:	f107 0040 	add.w	r0, r7, #64	; 0x40
    56ae:	2180      	movs	r1, #128	; 0x80
    56b0:	4420      	add	r0, r4
{
    56b2:	4690      	mov	r8, r2
    56b4:	4699      	mov	r9, r3
	err = set_starting_state(&subdata->flags, ctx);
    56b6:	f7ff ff99 	bl	55ec <set_starting_state>
	if (err < 0) {
    56ba:	2800      	cmp	r0, #0
    56bc:	db07      	blt.n	56ce <api_start+0x32>
	subdata->cb = cb;
    56be:	443c      	add	r4, r7
	subdata->user_data = user_data;
    56c0:	e9c4 890e 	strd	r8, r9, [r4, #56]	; 0x38
	 get_sub_config(dev, type)->start();
    56c4:	6873      	ldr	r3, [r6, #4]
    56c6:	f853 3035 	ldr.w	r3, [r3, r5, lsl #3]
    56ca:	4798      	blx	r3
	return 0;
    56cc:	2000      	movs	r0, #0
}
    56ce:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}

000056d2 <z_clock_isr>:
/* Weak-linked noop defaults for optional driver interfaces: */

void __weak z_clock_isr(void *arg)
{
	__ASSERT_NO_MSG(false);
}
    56d2:	4770      	bx	lr

000056d4 <z_clock_idle_exit>:
{
}

void __weak z_clock_idle_exit(void)
{
}
    56d4:	4770      	bx	lr

000056d6 <sys_clock_disable>:
    56d6:	4770      	bx	lr

000056d8 <spm_secure_services_init>:
	mbedtls_platform_context platform_ctx = {0};
    56d8:	2300      	movs	r3, #0
{
    56da:	b507      	push	{r0, r1, r2, lr}
	err = mbedtls_platform_setup(&platform_ctx);
    56dc:	a801      	add	r0, sp, #4
	mbedtls_platform_context platform_ctx = {0};
    56de:	f88d 3004 	strb.w	r3, [sp, #4]
	err = mbedtls_platform_setup(&platform_ctx);
    56e2:	f7fe fedf 	bl	44a4 <mbedtls_platform_setup>
}
    56e6:	b003      	add	sp, #12
    56e8:	f85d fb04 	ldr.w	pc, [sp], #4

000056ec <__acle_se_spm_request_random_number_nse>:
{
    56ec:	b570      	push	{r4, r5, r6, lr}
    56ee:	4606      	mov	r6, r0
    56f0:	460c      	mov	r4, r1
    56f2:	4615      	mov	r5, r2
	return arm_cmse_addr_is_secure(ptr) == 1;
    56f4:	f000 f8b4 	bl	5860 <arm_cmse_addr_is_secure>
	if (ptr_in_secure_area((intptr_t)output) ||
    56f8:	2801      	cmp	r0, #1
    56fa:	d136      	bne.n	576a <__acle_se_spm_request_random_number_nse+0x7e>
		return -EINVAL;
    56fc:	f06f 0015 	mvn.w	r0, #21
}
    5700:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    5704:	4671      	mov	r1, lr
    5706:	4672      	mov	r2, lr
    5708:	4673      	mov	r3, lr
    570a:	eeb7 0a00 	vmov.f32	s0, #112	; 0x3f800000  1.0
    570e:	eef7 0a00 	vmov.f32	s1, #112	; 0x3f800000  1.0
    5712:	eeb7 1a00 	vmov.f32	s2, #112	; 0x3f800000  1.0
    5716:	eef7 1a00 	vmov.f32	s3, #112	; 0x3f800000  1.0
    571a:	eeb7 2a00 	vmov.f32	s4, #112	; 0x3f800000  1.0
    571e:	eef7 2a00 	vmov.f32	s5, #112	; 0x3f800000  1.0
    5722:	eeb7 3a00 	vmov.f32	s6, #112	; 0x3f800000  1.0
    5726:	eef7 3a00 	vmov.f32	s7, #112	; 0x3f800000  1.0
    572a:	eeb7 4a00 	vmov.f32	s8, #112	; 0x3f800000  1.0
    572e:	eef7 4a00 	vmov.f32	s9, #112	; 0x3f800000  1.0
    5732:	eeb7 5a00 	vmov.f32	s10, #112	; 0x3f800000  1.0
    5736:	eef7 5a00 	vmov.f32	s11, #112	; 0x3f800000  1.0
    573a:	eeb7 6a00 	vmov.f32	s12, #112	; 0x3f800000  1.0
    573e:	eef7 6a00 	vmov.f32	s13, #112	; 0x3f800000  1.0
    5742:	eeb7 7a00 	vmov.f32	s14, #112	; 0x3f800000  1.0
    5746:	eef7 7a00 	vmov.f32	s15, #112	; 0x3f800000  1.0
    574a:	f38e 8c00 	msr	CPSR_fs, lr
    574e:	b410      	push	{r4}
    5750:	eef1 ca10 	vmrs	ip, fpscr
    5754:	f64f 7460 	movw	r4, #65376	; 0xff60
    5758:	f6c0 74ff 	movt	r4, #4095	; 0xfff
    575c:	ea0c 0c04 	and.w	ip, ip, r4
    5760:	eee1 ca10 	vmsr	fpscr, ip
    5764:	bc10      	pop	{r4}
    5766:	46f4      	mov	ip, lr
    5768:	4774      	bxns	lr
	return arm_cmse_addr_is_secure(ptr) == 1;
    576a:	4628      	mov	r0, r5
    576c:	f000 f878 	bl	5860 <arm_cmse_addr_is_secure>
	if (ptr_in_secure_area((intptr_t)output) ||
    5770:	2801      	cmp	r0, #1
    5772:	d0c3      	beq.n	56fc <__acle_se_spm_request_random_number_nse+0x10>
	if (len != MBEDTLS_ENTROPY_MAX_GATHER) {
    5774:	2c90      	cmp	r4, #144	; 0x90
    5776:	d1c1      	bne.n	56fc <__acle_se_spm_request_random_number_nse+0x10>
	err = mbedtls_hardware_poll(NULL, output, len, olen);
    5778:	462b      	mov	r3, r5
    577a:	4622      	mov	r2, r4
    577c:	4631      	mov	r1, r6
    577e:	2000      	movs	r0, #0
    5780:	f7fe fe9c 	bl	44bc <mbedtls_hardware_poll>
	return err;
    5784:	e7bc      	b.n	5700 <__acle_se_spm_request_random_number_nse+0x14>

00005786 <abort_function>:
	sys_reboot(SYS_REBOOT_WARM);
    5786:	2000      	movs	r0, #0
    5788:	f7fb bee2 	b.w	1550 <sys_reboot>

0000578c <z_irq_spurious>:
 */
void z_irq_spurious(const void *unused)
{
	ARG_UNUSED(unused);

	z_arm_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
    578c:	2100      	movs	r1, #0
    578e:	2001      	movs	r0, #1
    5790:	f000 b832 	b.w	57f8 <z_arm_fatal_error>

00005794 <irq_target_state_set>:
irq_target_state_t irq_target_state_set(unsigned int irq,
	irq_target_state_t irq_target_state)
{
	uint32_t result;

	if (irq_target_state == IRQ_TARGET_STATE_SECURE) {
    5794:	b243      	sxtb	r3, r0
    5796:	b9c9      	cbnz	r1, 57cc <irq_target_state_set+0x38>
  if ((int32_t)(IRQn) >= 0)
    5798:	2b00      	cmp	r3, #0
    579a:	db15      	blt.n	57c8 <irq_target_state_set+0x34>
    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
    579c:	2101      	movs	r1, #1
    579e:	095b      	lsrs	r3, r3, #5
    57a0:	009b      	lsls	r3, r3, #2
    57a2:	f103 4360 	add.w	r3, r3, #3758096384	; 0xe0000000
    57a6:	f503 4361 	add.w	r3, r3, #57600	; 0xe100
    57aa:	f8d3 2280 	ldr.w	r2, [r3, #640]	; 0x280
    57ae:	f000 001f 	and.w	r0, r0, #31
    57b2:	4081      	lsls	r1, r0
    57b4:	ea22 0201 	bic.w	r2, r2, r1
    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
    57b8:	f8c3 2280 	str.w	r2, [r3, #640]	; 0x280
    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
    57bc:	f8d3 1280 	ldr.w	r1, [r3, #640]	; 0x280
    57c0:	40c1      	lsrs	r1, r0
    57c2:	f001 0101 	and.w	r1, r1, #1
	} else {
		/* Set target to Non-Secure */
		result = NVIC_SetTargetState(irq);
	}

	if (result) {
    57c6:	b2c9      	uxtb	r1, r1
		return IRQ_TARGET_STATE_NON_SECURE;
	} else {
		return IRQ_TARGET_STATE_SECURE;
	}
}
    57c8:	4608      	mov	r0, r1
    57ca:	4770      	bx	lr
  if ((int32_t)(IRQn) >= 0)
    57cc:	2b00      	cmp	r3, #0
    57ce:	db0d      	blt.n	57ec <irq_target_state_set+0x58>
    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
    57d0:	2201      	movs	r2, #1
    57d2:	095b      	lsrs	r3, r3, #5
    57d4:	009b      	lsls	r3, r3, #2
    57d6:	f103 4360 	add.w	r3, r3, #3758096384	; 0xe0000000
    57da:	f503 4361 	add.w	r3, r3, #57600	; 0xe100
    57de:	f8d3 1280 	ldr.w	r1, [r3, #640]	; 0x280
    57e2:	f000 001f 	and.w	r0, r0, #31
    57e6:	4082      	lsls	r2, r0
    57e8:	430a      	orrs	r2, r1
    57ea:	e7e5      	b.n	57b8 <irq_target_state_set+0x24>
		return IRQ_TARGET_STATE_SECURE;
    57ec:	2100      	movs	r1, #0
    57ee:	e7eb      	b.n	57c8 <irq_target_state_set+0x34>

000057f0 <configure_builtin_stack_guard>:
  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
    57f0:	6e83      	ldr	r3, [r0, #104]	; 0x68
    57f2:	f383 880b 	msr	PSPLIM, r3
}
    57f6:	4770      	bx	lr

000057f8 <z_arm_fatal_error>:
{

	if (esf != NULL) {
		esf_dump(esf);
	}
	z_fatal_error(reason, esf);
    57f8:	f000 b922 	b.w	5a40 <z_fatal_error>

000057fc <z_do_kernel_oops>:
 *   fault handler will executed insted of the SVC.
 *
 * @param esf exception frame
 */
void z_do_kernel_oops(const z_arch_esf_t *esf)
{
    57fc:	4601      	mov	r1, r0
	z_fatal_error(reason, esf);
    57fe:	6800      	ldr	r0, [r0, #0]
    5800:	f000 b91e 	b.w	5a40 <z_fatal_error>

00005804 <z_arm_nmi>:
 *
 * @return N/A
 */

void z_arm_nmi(void)
{
    5804:	b508      	push	{r3, lr}
	handler();
    5806:	f7fc fd45 	bl	2294 <z_SysNmiOnReset>
	z_arm_int_exit();
}
    580a:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	z_arm_int_exit();
    580e:	f7fc bec7 	b.w	25a0 <z_arm_exc_exit>

00005812 <mpu_configure_region>:
{
    5812:	b57f      	push	{r0, r1, r2, r3, r4, r5, r6, lr}
	p_attr->rbar = attr->rbar &
    5814:	890a      	ldrh	r2, [r1, #8]
    5816:	7a8e      	ldrb	r6, [r1, #10]
	region_conf.base = new_region->start;
    5818:	680b      	ldr	r3, [r1, #0]
	get_region_attr_from_mpu_partition_info(&region_conf.attr,
    581a:	684d      	ldr	r5, [r1, #4]
    581c:	f002 021f 	and.w	r2, r2, #31
    5820:	ea42 1246 	orr.w	r2, r2, r6, lsl #5
	region_conf.base = new_region->start;
    5824:	9300      	str	r3, [sp, #0]
    5826:	f88d 2008 	strb.w	r2, [sp, #8]
	p_attr->r_limit = REGION_LIMIT_ADDR(base, size);
    582a:	f023 031f 	bic.w	r3, r3, #31
    582e:	1e6a      	subs	r2, r5, #1
    5830:	4413      	add	r3, r2
    5832:	f023 031f 	bic.w	r3, r3, #31
	if (index > (get_num_regions() - 1U)) {
    5836:	280f      	cmp	r0, #15
    5838:	9303      	str	r3, [sp, #12]
    583a:	d804      	bhi.n	5846 <mpu_configure_region+0x34>
	region_init(index, region_conf);
    583c:	4669      	mov	r1, sp
    583e:	f7fc ff19 	bl	2674 <region_init>
}
    5842:	b004      	add	sp, #16
    5844:	bd70      	pop	{r4, r5, r6, pc}
		return -EINVAL;
    5846:	f06f 0015 	mvn.w	r0, #21
	return region_allocate_and_init(index,
    584a:	e7fa      	b.n	5842 <mpu_configure_region+0x30>

0000584c <arm_cmse_mpu_region_get>:
__CMSE_TT_ASM ()

__extension__ static __inline __attribute__ ((__always_inline__))
cmse_address_info_t
cmse_TT (void *__p)
__CMSE_TT_ASM ()
    584c:	e840 f000 	tt	r0, r0
    5850:	b2c3      	uxtb	r3, r0

int arm_cmse_mpu_region_get(uint32_t addr)
{
	cmse_address_info_t addr_info =	cmse_TT((void *)addr);

	if (addr_info.flags.mpu_region_valid) {
    5852:	f410 3f80 	tst.w	r0, #65536	; 0x10000
		return addr_info.flags.mpu_region;
	}

	return -EINVAL;
}
    5856:	bf14      	ite	ne
    5858:	4618      	movne	r0, r3
    585a:	f06f 0015 	mvneq.w	r0, #21
    585e:	4770      	bx	lr

00005860 <arm_cmse_addr_is_secure>:
    5860:	e840 f000 	tt	r0, r0
int arm_cmse_addr_is_secure(uint32_t addr)
{
	cmse_address_info_t addr_info =	cmse_TT((void *)addr);

	return addr_info.flags.secure;
}
    5864:	f3c0 5080 	ubfx	r0, r0, #22, #1
    5868:	4770      	bx	lr

0000586a <strlen>:
 *
 * @return number of bytes in string <s>
 */

size_t strlen(const char *s)
{
    586a:	4603      	mov	r3, r0
	size_t n = 0;
    586c:	2000      	movs	r0, #0

	while (*s != '\0') {
    586e:	5c1a      	ldrb	r2, [r3, r0]
    5870:	b902      	cbnz	r2, 5874 <strlen+0xa>
		s++;
		n++;
	}

	return n;
}
    5872:	4770      	bx	lr
		n++;
    5874:	3001      	adds	r0, #1
    5876:	e7fa      	b.n	586e <strlen+0x4>

00005878 <strnlen>:
 *
 * @return number of bytes in fixed-size string <s>
 */

size_t strnlen(const char *s, size_t maxlen)
{
    5878:	4603      	mov	r3, r0
	size_t n = 0;
    587a:	2000      	movs	r0, #0

	while (*s != '\0' && n < maxlen) {
    587c:	5c1a      	ldrb	r2, [r3, r0]
    587e:	b10a      	cbz	r2, 5884 <strnlen+0xc>
    5880:	4288      	cmp	r0, r1
    5882:	d100      	bne.n	5886 <strnlen+0xe>
		s++;
		n++;
	}

	return n;
}
    5884:	4770      	bx	lr
		n++;
    5886:	3001      	adds	r0, #1
    5888:	e7f8      	b.n	587c <strnlen+0x4>

0000588a <memcmp>:
 * @brief Compare two memory areas
 *
 * @return negative # if <m1> < <m2>, 0 if <m1> == <m2>, else positive #
 */
int memcmp(const void *m1, const void *m2, size_t n)
{
    588a:	b510      	push	{r4, lr}
	const char *c1 = m1;
	const char *c2 = m2;

	if (!n) {
    588c:	b15a      	cbz	r2, 58a6 <memcmp+0x1c>
    588e:	3901      	subs	r1, #1
    5890:	1884      	adds	r4, r0, r2
		return 0;
	}

	while ((--n > 0) && (*c1 == *c2)) {
    5892:	f810 2b01 	ldrb.w	r2, [r0], #1
    5896:	f811 3f01 	ldrb.w	r3, [r1, #1]!
    589a:	42a0      	cmp	r0, r4
    589c:	d001      	beq.n	58a2 <memcmp+0x18>
    589e:	429a      	cmp	r2, r3
    58a0:	d0f7      	beq.n	5892 <memcmp+0x8>
		c1++;
		c2++;
	}

	return *c1 - *c2;
    58a2:	1ad0      	subs	r0, r2, r3
}
    58a4:	bd10      	pop	{r4, pc}
		return 0;
    58a6:	4610      	mov	r0, r2
    58a8:	e7fc      	b.n	58a4 <memcmp+0x1a>

000058aa <memmove>:
void *memmove(void *d, const void *s, size_t n)
{
	char *dest = d;
	const char *src  = s;

	if ((size_t) (dest - src) < n) {
    58aa:	1a43      	subs	r3, r0, r1
    58ac:	4293      	cmp	r3, r2
{
    58ae:	b510      	push	{r4, lr}
    58b0:	eb00 0302 	add.w	r3, r0, r2
	if ((size_t) (dest - src) < n) {
    58b4:	d308      	bcc.n	58c8 <memmove+0x1e>
	char *dest = d;
    58b6:	4602      	mov	r2, r0
    58b8:	3901      	subs	r1, #1
			n--;
			dest[n] = src[n];
		}
	} else {
		/* It is safe to perform a forward-copy */
		while (n > 0) {
    58ba:	429a      	cmp	r2, r3
    58bc:	d00b      	beq.n	58d6 <memmove+0x2c>
			*dest = *src;
    58be:	f811 4f01 	ldrb.w	r4, [r1, #1]!
    58c2:	f802 4b01 	strb.w	r4, [r2], #1
			dest++;
			src++;
			n--;
    58c6:	e7f8      	b.n	58ba <memmove+0x10>
    58c8:	440a      	add	r2, r1
			dest[n] = src[n];
    58ca:	f812 4d01 	ldrb.w	r4, [r2, #-1]!
		while (n > 0) {
    58ce:	428a      	cmp	r2, r1
			dest[n] = src[n];
    58d0:	f803 4d01 	strb.w	r4, [r3, #-1]!
		while (n > 0) {
    58d4:	d1f9      	bne.n	58ca <memmove+0x20>
		}
	}

	return d;
}
    58d6:	bd10      	pop	{r4, pc}

000058d8 <memcpy>:
 *
 * @return pointer to start of destination buffer
 */

void *memcpy(void *_MLIBC_RESTRICT d, const void *_MLIBC_RESTRICT s, size_t n)
{
    58d8:	b5f0      	push	{r4, r5, r6, r7, lr}

	unsigned char *d_byte = (unsigned char *)d;
	const unsigned char *s_byte = (const unsigned char *)s;
	const uintptr_t mask = sizeof(mem_word_t) - 1;

	if ((((uintptr_t)d ^ (uintptr_t)s_byte) & mask) == 0) {
    58da:	ea81 0400 	eor.w	r4, r1, r0
    58de:	07a5      	lsls	r5, r4, #30
    58e0:	4603      	mov	r3, r0
    58e2:	d00b      	beq.n	58fc <memcpy+0x24>
    58e4:	3b01      	subs	r3, #1
    58e6:	440a      	add	r2, r1
		s_byte = (unsigned char *)s_word;
	}

	/* do byte-sized copying until finished */

	while (n > 0) {
    58e8:	4291      	cmp	r1, r2
    58ea:	d11b      	bne.n	5924 <memcpy+0x4c>
		*(d_byte++) = *(s_byte++);
		n--;
	}

	return d;
}
    58ec:	bdf0      	pop	{r4, r5, r6, r7, pc}
			if (n == 0) {
    58ee:	2a00      	cmp	r2, #0
    58f0:	d0fc      	beq.n	58ec <memcpy+0x14>
			*(d_byte++) = *(s_byte++);
    58f2:	f811 4b01 	ldrb.w	r4, [r1], #1
			n--;
    58f6:	3a01      	subs	r2, #1
			*(d_byte++) = *(s_byte++);
    58f8:	f803 4b01 	strb.w	r4, [r3], #1
		while (((uintptr_t)d_byte) & mask) {
    58fc:	079c      	lsls	r4, r3, #30
    58fe:	d1f6      	bne.n	58ee <memcpy+0x16>
    5900:	f022 0403 	bic.w	r4, r2, #3
    5904:	1f1d      	subs	r5, r3, #4
    5906:	0896      	lsrs	r6, r2, #2
    5908:	190f      	adds	r7, r1, r4
		while (n >= sizeof(mem_word_t)) {
    590a:	42b9      	cmp	r1, r7
    590c:	d105      	bne.n	591a <memcpy+0x42>
    590e:	f06f 0503 	mvn.w	r5, #3
    5912:	4423      	add	r3, r4
    5914:	fb05 2206 	mla	r2, r5, r6, r2
    5918:	e7e4      	b.n	58e4 <memcpy+0xc>
			*(d_word++) = *(s_word++);
    591a:	f851 cb04 	ldr.w	ip, [r1], #4
    591e:	f845 cf04 	str.w	ip, [r5, #4]!
			n -= sizeof(mem_word_t);
    5922:	e7f2      	b.n	590a <memcpy+0x32>
		*(d_byte++) = *(s_byte++);
    5924:	f811 4b01 	ldrb.w	r4, [r1], #1
    5928:	f803 4f01 	strb.w	r4, [r3, #1]!
		n--;
    592c:	e7dc      	b.n	58e8 <memcpy+0x10>

0000592e <memset>:

void *memset(void *buf, int c, size_t n)
{
	/* do byte-sized initialization until word-aligned or finished */

	unsigned char *d_byte = (unsigned char *)buf;
    592e:	4603      	mov	r3, r0
{
    5930:	b570      	push	{r4, r5, r6, lr}
	unsigned char c_byte = (unsigned char)c;
    5932:	b2c9      	uxtb	r1, r1

	while (((uintptr_t)d_byte) & (sizeof(mem_word_t) - 1)) {
    5934:	079c      	lsls	r4, r3, #30
    5936:	d111      	bne.n	595c <memset+0x2e>
	/* do word-sized initialization as long as possible */

	mem_word_t *d_word = (mem_word_t *)d_byte;
	mem_word_t c_word = (mem_word_t)c_byte;

	c_word |= c_word << 8;
    5938:	ea41 2401 	orr.w	r4, r1, r1, lsl #8
	c_word |= c_word << 16;
    593c:	f022 0603 	bic.w	r6, r2, #3
    5940:	ea44 4504 	orr.w	r5, r4, r4, lsl #16
#if Z_MEM_WORD_T_WIDTH > 32
	c_word |= c_word << 32;
#endif

	while (n >= sizeof(mem_word_t)) {
    5944:	441e      	add	r6, r3
    5946:	0894      	lsrs	r4, r2, #2
    5948:	42b3      	cmp	r3, r6
    594a:	d10d      	bne.n	5968 <memset+0x3a>
    594c:	f06f 0503 	mvn.w	r5, #3
    5950:	fb05 2204 	mla	r2, r5, r4, r2
    5954:	441a      	add	r2, r3

	/* do byte-sized initialization until finished */

	d_byte = (unsigned char *)d_word;

	while (n > 0) {
    5956:	4293      	cmp	r3, r2
    5958:	d109      	bne.n	596e <memset+0x40>
		*(d_byte++) = c_byte;
		n--;
	}

	return buf;
}
    595a:	bd70      	pop	{r4, r5, r6, pc}
		if (n == 0) {
    595c:	2a00      	cmp	r2, #0
    595e:	d0fc      	beq.n	595a <memset+0x2c>
		*(d_byte++) = c_byte;
    5960:	f803 1b01 	strb.w	r1, [r3], #1
		n--;
    5964:	3a01      	subs	r2, #1
    5966:	e7e5      	b.n	5934 <memset+0x6>
		*(d_word++) = c_word;
    5968:	f843 5b04 	str.w	r5, [r3], #4
		n -= sizeof(mem_word_t);
    596c:	e7ec      	b.n	5948 <memset+0x1a>
		*(d_byte++) = c_byte;
    596e:	f803 1b01 	strb.w	r1, [r3], #1
		n--;
    5972:	e7f0      	b.n	5956 <memset+0x28>

00005974 <gpio_nrfx_port_get_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    5974:	6843      	ldr	r3, [r0, #4]
}
    5976:	2000      	movs	r0, #0
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    5978:	685b      	ldr	r3, [r3, #4]
    597a:	691b      	ldr	r3, [r3, #16]
	*value = nrf_gpio_port_in_read(reg);
    597c:	600b      	str	r3, [r1, #0]
}
    597e:	4770      	bx	lr

00005980 <gpio_nrfx_port_set_masked_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    5980:	6843      	ldr	r3, [r0, #4]
    5982:	685b      	ldr	r3, [r3, #4]
    return p_reg->OUT;
    5984:	6858      	ldr	r0, [r3, #4]
	nrf_gpio_port_out_write(reg, value_tmp | (mask & value));
    5986:	4042      	eors	r2, r0
    5988:	400a      	ands	r2, r1
    598a:	4042      	eors	r2, r0
    p_reg->OUT = value;
    598c:	605a      	str	r2, [r3, #4]
}
    598e:	2000      	movs	r0, #0
    5990:	4770      	bx	lr

00005992 <gpio_nrfx_port_set_bits_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    5992:	6843      	ldr	r3, [r0, #4]
}
    5994:	2000      	movs	r0, #0
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    5996:	685b      	ldr	r3, [r3, #4]
    p_reg->OUTSET = set_mask;
    5998:	6099      	str	r1, [r3, #8]
}
    599a:	4770      	bx	lr

0000599c <gpio_nrfx_port_clear_bits_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    599c:	6843      	ldr	r3, [r0, #4]
}
    599e:	2000      	movs	r0, #0
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    59a0:	685b      	ldr	r3, [r3, #4]
    p_reg->OUTCLR = clr_mask;
    59a2:	60d9      	str	r1, [r3, #12]
}
    59a4:	4770      	bx	lr

000059a6 <gpio_nrfx_port_toggle_bits>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    59a6:	6843      	ldr	r3, [r0, #4]
}
    59a8:	2000      	movs	r0, #0
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    59aa:	685a      	ldr	r2, [r3, #4]
    return p_reg->OUT;
    59ac:	6853      	ldr	r3, [r2, #4]
	nrf_gpio_port_out_write(reg, value ^ mask);
    59ae:	4059      	eors	r1, r3
    p_reg->OUT = value;
    59b0:	6051      	str	r1, [r2, #4]
}
    59b2:	4770      	bx	lr

000059b4 <gpio_nrfx_manage_callback>:
	return gpio_manage_callback(&get_port_data(port)->callbacks,
    59b4:	68c3      	ldr	r3, [r0, #12]
{
    59b6:	b530      	push	{r4, r5, lr}
Z_GENLIST_IS_EMPTY(slist)
    59b8:	6858      	ldr	r0, [r3, #4]
	if (!sys_slist_is_empty(callbacks)) {
    59ba:	b158      	cbz	r0, 59d4 <gpio_nrfx_manage_callback+0x20>
 * @return true if node was removed
 */
static inline bool sys_slist_find_and_remove(sys_slist_t *list,
					     sys_snode_t *node);

Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    59bc:	2400      	movs	r4, #0
    59be:	4281      	cmp	r1, r0
    59c0:	d113      	bne.n	59ea <gpio_nrfx_manage_callback+0x36>
Z_GENLIST_REMOVE(slist, snode)
    59c2:	6808      	ldr	r0, [r1, #0]
    59c4:	b95c      	cbnz	r4, 59de <gpio_nrfx_manage_callback+0x2a>
    59c6:	689c      	ldr	r4, [r3, #8]
	list->head = node;
    59c8:	6058      	str	r0, [r3, #4]
Z_GENLIST_REMOVE(slist, snode)
    59ca:	42a1      	cmp	r1, r4
    59cc:	d100      	bne.n	59d0 <gpio_nrfx_manage_callback+0x1c>
	list->tail = node;
    59ce:	6098      	str	r0, [r3, #8]
	parent->next = child;
    59d0:	2000      	movs	r0, #0
    59d2:	6008      	str	r0, [r1, #0]
	if (set) {
    59d4:	b972      	cbnz	r2, 59f4 <gpio_nrfx_manage_callback+0x40>
	return 0;
    59d6:	2000      	movs	r0, #0
}
    59d8:	bd30      	pop	{r4, r5, pc}
    59da:	4628      	mov	r0, r5
    59dc:	e7ef      	b.n	59be <gpio_nrfx_manage_callback+0xa>
    59de:	6020      	str	r0, [r4, #0]
Z_GENLIST_REMOVE(slist, snode)
    59e0:	6898      	ldr	r0, [r3, #8]
    59e2:	4281      	cmp	r1, r0
	list->tail = node;
    59e4:	bf08      	it	eq
    59e6:	609c      	streq	r4, [r3, #8]
}
    59e8:	e7f2      	b.n	59d0 <gpio_nrfx_manage_callback+0x1c>
Z_GENLIST_PEEK_NEXT_NO_CHECK(slist, snode)
    59ea:	6805      	ldr	r5, [r0, #0]
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    59ec:	4604      	mov	r4, r0
    59ee:	2d00      	cmp	r5, #0
    59f0:	d1f3      	bne.n	59da <gpio_nrfx_manage_callback+0x26>
			if (!set) {
    59f2:	b13a      	cbz	r2, 5a04 <gpio_nrfx_manage_callback+0x50>
Z_GENLIST_PREPEND(slist, snode)
    59f4:	685a      	ldr	r2, [r3, #4]
	parent->next = child;
    59f6:	600a      	str	r2, [r1, #0]
Z_GENLIST_PREPEND(slist, snode)
    59f8:	6898      	ldr	r0, [r3, #8]
	list->head = node;
    59fa:	6059      	str	r1, [r3, #4]
Z_GENLIST_PREPEND(slist, snode)
    59fc:	2800      	cmp	r0, #0
    59fe:	d1ea      	bne.n	59d6 <gpio_nrfx_manage_callback+0x22>
	list->tail = node;
    5a00:	6099      	str	r1, [r3, #8]
}
    5a02:	e7e9      	b.n	59d8 <gpio_nrfx_manage_callback+0x24>
				return -EINVAL;
    5a04:	f06f 0015 	mvn.w	r0, #21
	return gpio_manage_callback(&get_port_data(port)->callbacks,
    5a08:	e7e6      	b.n	59d8 <gpio_nrfx_manage_callback+0x24>

00005a0a <k_sys_fatal_error_handler>:
	ARG_UNUSED(reason);

	LOG_PANIC();

	LOG_ERR("Resetting system");
	sys_arch_reboot(0);
    5a0a:	2000      	movs	r0, #0
{
    5a0c:	b508      	push	{r3, lr}
	sys_arch_reboot(0);
    5a0e:	f7fc fdd5 	bl	25bc <sys_arch_reboot>

00005a12 <hw_cc3xx_init>:
#include <nrf_cc3xx_platform.h>

#if CONFIG_HW_CC3XX

static int hw_cc3xx_init(const struct device *dev)
{
    5a12:	b508      	push	{r3, lr}
	int res;

	__ASSERT_NO_MSG(dev != NULL);

	/* Set the RTOS abort APIs */
	nrf_cc3xx_platform_abort_init();
    5a14:	f7fc fa9a 	bl	1f4c <nrf_cc3xx_platform_abort_init>

	/* Set the RTOS mutex APIs */
	nrf_cc3xx_platform_mutex_init();
    5a18:	f7fc fb44 	bl	20a4 <nrf_cc3xx_platform_mutex_init>
	res = nrf_cc3xx_platform_init();
#else
	res = nrf_cc3xx_platform_init_no_rng();
#endif
	return res;
}
    5a1c:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	res = nrf_cc3xx_platform_init_no_rng();
    5a20:	f7fe be02 	b.w	4628 <nrf_cc3xx_platform_init_no_rng>

00005a24 <nrfx_isr>:
#include <nrfx.h>
#include <kernel.h>

void nrfx_isr(const void *irq_handler)
{
	((nrfx_irq_handler_t)irq_handler)();
    5a24:	4700      	bx	r0

00005a26 <nrfx_busy_wait>:
	z_impl_k_busy_wait(usec_to_wait);
    5a26:	f000 b8f6 	b.w	5c16 <z_impl_k_busy_wait>

00005a2a <nrfx_clock_enable>:
{
    5a2a:	b508      	push	{r3, lr}
    priority = NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY;
#else
    #error "This code is not supposed to be compiled when neither POWER nor CLOCK is enabled."
#endif

    if (!NRFX_IRQ_IS_ENABLED(nrfx_get_irq_number(NRF_CLOCK)))
    5a2c:	2005      	movs	r0, #5
    5a2e:	f7fc fbb5 	bl	219c <arch_irq_is_enabled>
    5a32:	b920      	cbnz	r0, 5a3e <nrfx_clock_enable+0x14>
}
    5a34:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    {
        NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_CLOCK), priority);
        NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_CLOCK));
    5a38:	2005      	movs	r0, #5
    5a3a:	f7fc bb9f 	b.w	217c <arch_irq_enable>
    5a3e:	bd08      	pop	{r3, pc}

00005a40 <z_fatal_error>:
	return 0;
#endif
}

void z_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
{
    5a40:	b573      	push	{r0, r1, r4, r5, r6, lr}
    5a42:	4605      	mov	r5, r0
    5a44:	9101      	str	r1, [sp, #4]
	__asm__ volatile(
    5a46:	f04f 0320 	mov.w	r3, #32
    5a4a:	f3ef 8611 	mrs	r6, BASEPRI
    5a4e:	f383 8811 	msr	BASEPRI, r3
    5a52:	f3bf 8f6f 	isb	sy
	return z_impl_k_current_get();
    5a56:	f7fe f96f 	bl	3d38 <z_impl_k_current_get>
	LOG_ERR("Current thread: %p (%s)", thread,
		log_strdup(thread_name_get(thread)));

	z_coredump(reason, esf, thread);

	k_sys_fatal_error_handler(reason, esf);
    5a5a:	9901      	ldr	r1, [sp, #4]
    5a5c:	4604      	mov	r4, r0
    5a5e:	4628      	mov	r0, r5
    5a60:	f7ff ffd3 	bl	5a0a <k_sys_fatal_error_handler>
	__asm__ volatile(
    5a64:	f386 8811 	msr	BASEPRI, r6
    5a68:	f3bf 8f6f 	isb	sy
	z_impl_k_thread_abort(thread);
    5a6c:	4620      	mov	r0, r4
#endif /*CONFIG_ARCH_HAS_NESTED_EXCEPTION_DETECTION */
	}

	arch_irq_unlock(key);
	k_thread_abort(thread);
}
    5a6e:	b002      	add	sp, #8
    5a70:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    5a74:	f7fc bdc0 	b.w	25f8 <z_impl_k_thread_abort>

00005a78 <z_pm_save_idle_exit>:
	z_clock_idle_exit();
    5a78:	f7ff be2c 	b.w	56d4 <z_clock_idle_exit>

00005a7c <k_mem_slab_init>:
{
    5a7c:	b530      	push	{r4, r5, lr}
	slab->num_used = 0U;
    5a7e:	2400      	movs	r4, #0
    5a80:	6184      	str	r4, [r0, #24]
	CHECKIF(((slab->block_size | (uintptr_t)slab->buffer) &
    5a82:	ea41 0402 	orr.w	r4, r1, r2
    5a86:	f014 0403 	ands.w	r4, r4, #3
	slab->block_size = block_size;
    5a8a:	e9c0 3202 	strd	r3, r2, [r0, #8]
	slab->buffer = buffer;
    5a8e:	6101      	str	r1, [r0, #16]
	CHECKIF(((slab->block_size | (uintptr_t)slab->buffer) &
    5a90:	d10c      	bne.n	5aac <k_mem_slab_init+0x30>
	slab->free_list = NULL;
    5a92:	6144      	str	r4, [r0, #20]
	for (j = 0U; j < slab->num_blocks; j++) {
    5a94:	42a3      	cmp	r3, r4
    5a96:	d103      	bne.n	5aa0 <k_mem_slab_init+0x24>
	list->tail = (sys_dnode_t *)list;
    5a98:	e9c0 0000 	strd	r0, r0, [r0]
}
    5a9c:	2000      	movs	r0, #0
}
    5a9e:	bd30      	pop	{r4, r5, pc}
		*(char **)p = slab->free_list;
    5aa0:	6945      	ldr	r5, [r0, #20]
	for (j = 0U; j < slab->num_blocks; j++) {
    5aa2:	3401      	adds	r4, #1
		*(char **)p = slab->free_list;
    5aa4:	600d      	str	r5, [r1, #0]
		slab->free_list = p;
    5aa6:	6141      	str	r1, [r0, #20]
		p += slab->block_size;
    5aa8:	4411      	add	r1, r2
	for (j = 0U; j < slab->num_blocks; j++) {
    5aaa:	e7f3      	b.n	5a94 <k_mem_slab_init+0x18>
		return -EINVAL;
    5aac:	f06f 0015 	mvn.w	r0, #21
	return rc;
    5ab0:	e7f5      	b.n	5a9e <k_mem_slab_init+0x22>

00005ab2 <z_impl_k_mutex_init>:
	mutex->owner = NULL;
    5ab2:	2300      	movs	r3, #0
    5ab4:	e9c0 0000 	strd	r0, r0, [r0]
	mutex->lock_count = 0U;
    5ab8:	e9c0 3302 	strd	r3, r3, [r0, #8]
}
    5abc:	4618      	mov	r0, r3
    5abe:	4770      	bx	lr

00005ac0 <z_reschedule_irqlock>:
	return arch_irq_unlocked(key) && !arch_is_in_isr();
    5ac0:	4603      	mov	r3, r0
    5ac2:	b920      	cbnz	r0, 5ace <z_reschedule_irqlock+0xe>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    5ac4:	f3ef 8205 	mrs	r2, IPSR
    5ac8:	b90a      	cbnz	r2, 5ace <z_reschedule_irqlock+0xe>
    5aca:	f7fc bb01 	b.w	20d0 <arch_swap>
    5ace:	f383 8811 	msr	BASEPRI, r3
    5ad2:	f3bf 8f6f 	isb	sy
}
    5ad6:	4770      	bx	lr

00005ad8 <z_reschedule_unlocked>:
	__asm__ volatile(
    5ad8:	f04f 0320 	mov.w	r3, #32
    5adc:	f3ef 8011 	mrs	r0, BASEPRI
    5ae0:	f383 8811 	msr	BASEPRI, r3
    5ae4:	f3bf 8f6f 	isb	sy
	(void) z_reschedule_irqlock(arch_irq_lock());
    5ae8:	f7ff bfea 	b.w	5ac0 <z_reschedule_irqlock>

00005aec <unpend_thread_no_timeout>:
{
    5aec:	4601      	mov	r1, r0
    5aee:	b508      	push	{r3, lr}
	_priq_wait_remove(&pended_on(thread)->waitq, thread);
    5af0:	6880      	ldr	r0, [r0, #8]
    5af2:	f7fd fdfd 	bl	36f0 <z_priq_dumb_remove>
	thread->base.thread_state &= ~_THREAD_PENDING;
    5af6:	7b4b      	ldrb	r3, [r1, #13]
    5af8:	f023 0302 	bic.w	r3, r3, #2
    5afc:	734b      	strb	r3, [r1, #13]
	thread->base.pended_on = NULL;
    5afe:	2300      	movs	r3, #0
    5b00:	608b      	str	r3, [r1, #8]
}
    5b02:	bd08      	pop	{r3, pc}

00005b04 <z_priq_dumb_best>:
	return list->head == list;
    5b04:	6803      	ldr	r3, [r0, #0]
}
    5b06:	4298      	cmp	r0, r3
    5b08:	bf14      	ite	ne
    5b0a:	4618      	movne	r0, r3
    5b0c:	2000      	moveq	r0, #0
    5b0e:	4770      	bx	lr

00005b10 <z_ready_thread>:
{
    5b10:	b510      	push	{r4, lr}
    5b12:	f04f 0320 	mov.w	r3, #32
    5b16:	f3ef 8411 	mrs	r4, BASEPRI
    5b1a:	f383 8811 	msr	BASEPRI, r3
    5b1e:	f3bf 8f6f 	isb	sy
		ready_thread(thread);
    5b22:	f7fd fe3f 	bl	37a4 <ready_thread>
	__asm__ volatile(
    5b26:	f384 8811 	msr	BASEPRI, r4
    5b2a:	f3bf 8f6f 	isb	sy
}
    5b2e:	bd10      	pop	{r4, pc}

00005b30 <z_thread_timeout>:
{
    5b30:	b537      	push	{r0, r1, r2, r4, r5, lr}
    5b32:	4604      	mov	r4, r0
	__asm__ volatile(
    5b34:	f04f 0320 	mov.w	r3, #32
    5b38:	f3ef 8511 	mrs	r5, BASEPRI
    5b3c:	f383 8811 	msr	BASEPRI, r3
    5b40:	f3bf 8f6f 	isb	sy
		if (thread->base.pended_on != NULL) {
    5b44:	f854 3c10 	ldr.w	r3, [r4, #-16]
		struct k_thread *thread = CONTAINER_OF(timeout,
    5b48:	3818      	subs	r0, #24
		if (thread->base.pended_on != NULL) {
    5b4a:	b11b      	cbz	r3, 5b54 <z_thread_timeout+0x24>
			unpend_thread_no_timeout(thread);
    5b4c:	9001      	str	r0, [sp, #4]
    5b4e:	f7ff ffcd 	bl	5aec <unpend_thread_no_timeout>
    5b52:	9801      	ldr	r0, [sp, #4]
	thread->base.thread_state &= ~_THREAD_SUSPENDED;
    5b54:	f814 3c0b 	ldrb.w	r3, [r4, #-11]
    5b58:	f023 0314 	bic.w	r3, r3, #20
    5b5c:	f804 3c0b 	strb.w	r3, [r4, #-11]
		ready_thread(thread);
    5b60:	f7fd fe20 	bl	37a4 <ready_thread>
	__asm__ volatile(
    5b64:	f385 8811 	msr	BASEPRI, r5
    5b68:	f3bf 8f6f 	isb	sy
}
    5b6c:	b003      	add	sp, #12
    5b6e:	bd30      	pop	{r4, r5, pc}

00005b70 <add_to_waitq_locked>:
{
    5b70:	b538      	push	{r3, r4, r5, lr}
    5b72:	4604      	mov	r4, r0
    5b74:	460d      	mov	r5, r1
	unready_thread(thread);
    5b76:	f7fd ff97 	bl	3aa8 <unready_thread>
	thread->base.thread_state |= _THREAD_PENDING;
    5b7a:	7b63      	ldrb	r3, [r4, #13]
    5b7c:	f043 0302 	orr.w	r3, r3, #2
    5b80:	7363      	strb	r3, [r4, #13]
	if (wait_q != NULL) {
    5b82:	b17d      	cbz	r5, 5ba4 <add_to_waitq_locked+0x34>
    5b84:	682b      	ldr	r3, [r5, #0]
		thread->base.pended_on = wait_q;
    5b86:	60a5      	str	r5, [r4, #8]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    5b88:	429d      	cmp	r5, r3
    5b8a:	d012      	beq.n	5bb2 <add_to_waitq_locked+0x42>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    5b8c:	b18b      	cbz	r3, 5bb2 <add_to_waitq_locked+0x42>
	if (thread_1->base.prio < thread_2->base.prio) {
    5b8e:	f994 200e 	ldrsb.w	r2, [r4, #14]
    5b92:	f993 100e 	ldrsb.w	r1, [r3, #14]
    5b96:	4291      	cmp	r1, r2
    5b98:	dd05      	ble.n	5ba6 <add_to_waitq_locked+0x36>
	node->prev = successor->prev;
    5b9a:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
    5b9c:	e9c4 3200 	strd	r3, r2, [r4]
	successor->prev->next = node;
    5ba0:	6014      	str	r4, [r2, #0]
	successor->prev = node;
    5ba2:	605c      	str	r4, [r3, #4]
}
    5ba4:	bd38      	pop	{r3, r4, r5, pc}
	return (node == list->tail) ? NULL : node->next;
    5ba6:	6869      	ldr	r1, [r5, #4]
    5ba8:	428b      	cmp	r3, r1
    5baa:	d002      	beq.n	5bb2 <add_to_waitq_locked+0x42>
    5bac:	681b      	ldr	r3, [r3, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    5bae:	2b00      	cmp	r3, #0
    5bb0:	d1ef      	bne.n	5b92 <add_to_waitq_locked+0x22>
	node->prev = list->tail;
    5bb2:	686b      	ldr	r3, [r5, #4]
	node->next = list;
    5bb4:	6025      	str	r5, [r4, #0]
	node->prev = list->tail;
    5bb6:	6063      	str	r3, [r4, #4]
	list->tail->next = node;
    5bb8:	686b      	ldr	r3, [r5, #4]
    5bba:	601c      	str	r4, [r3, #0]
	list->tail = node;
    5bbc:	606c      	str	r4, [r5, #4]
}
    5bbe:	e7f1      	b.n	5ba4 <add_to_waitq_locked+0x34>

00005bc0 <z_unpend_first_thread>:
{
    5bc0:	b538      	push	{r3, r4, r5, lr}
	__asm__ volatile(
    5bc2:	f04f 0320 	mov.w	r3, #32
    5bc6:	f3ef 8211 	mrs	r2, BASEPRI
    5bca:	f383 8811 	msr	BASEPRI, r3
    5bce:	f3bf 8f6f 	isb	sy
		ret = _priq_wait_best(&wait_q->waitq);
    5bd2:	f7ff ff97 	bl	5b04 <z_priq_dumb_best>
    5bd6:	4604      	mov	r4, r0
	__asm__ volatile(
    5bd8:	f382 8811 	msr	BASEPRI, r2
    5bdc:	f3bf 8f6f 	isb	sy

static inline struct k_thread *z_unpend1_no_timeout(_wait_q_t *wait_q)
{
	struct k_thread *thread = z_find_first_thread_to_unpend(wait_q, NULL);

	if (thread != NULL) {
    5be0:	b188      	cbz	r0, 5c06 <z_unpend_first_thread+0x46>
	__asm__ volatile(
    5be2:	f04f 0320 	mov.w	r3, #32
    5be6:	f3ef 8511 	mrs	r5, BASEPRI
    5bea:	f383 8811 	msr	BASEPRI, r3
    5bee:	f3bf 8f6f 	isb	sy
		unpend_thread_no_timeout(thread);
    5bf2:	f7ff ff7b 	bl	5aec <unpend_thread_no_timeout>
	__asm__ volatile(
    5bf6:	f385 8811 	msr	BASEPRI, r5
    5bfa:	f3bf 8f6f 	isb	sy
	return z_abort_timeout(&thread->base.timeout);
    5bfe:	f104 0018 	add.w	r0, r4, #24
    5c02:	f000 f80d 	bl	5c20 <z_abort_timeout>
}
    5c06:	4620      	mov	r0, r4
    5c08:	bd38      	pop	{r3, r4, r5, pc}

00005c0a <k_is_in_isr>:
    5c0a:	f3ef 8005 	mrs	r0, IPSR
}
    5c0e:	3800      	subs	r0, #0
    5c10:	bf18      	it	ne
    5c12:	2001      	movne	r0, #1
    5c14:	4770      	bx	lr

00005c16 <z_impl_k_busy_wait>:
	if (usec_to_wait == 0) {
    5c16:	b108      	cbz	r0, 5c1c <z_impl_k_busy_wait+0x6>
	arch_busy_wait(usec_to_wait);
    5c18:	f7fb bc90 	b.w	153c <arch_busy_wait>
}
    5c1c:	4770      	bx	lr

00005c1e <boot_banner>:
#else
	printk("*** Booting Zephyr OS version %s %s ***\n",
	       KERNEL_VERSION_STRING, BOOT_DELAY_BANNER);
#endif
#endif
}
    5c1e:	4770      	bx	lr

00005c20 <z_abort_timeout>:
{
    5c20:	b510      	push	{r4, lr}
	__asm__ volatile(
    5c22:	f04f 0220 	mov.w	r2, #32
    5c26:	f3ef 8411 	mrs	r4, BASEPRI
    5c2a:	f382 8811 	msr	BASEPRI, r2
    5c2e:	f3bf 8f6f 	isb	sy
		if (sys_dnode_is_linked(&to->node)) {
    5c32:	6803      	ldr	r3, [r0, #0]
    5c34:	b13b      	cbz	r3, 5c46 <z_abort_timeout+0x26>
			remove_timeout(to);
    5c36:	f7fe f995 	bl	3f64 <remove_timeout>
			ret = 0;
    5c3a:	2000      	movs	r0, #0
	__asm__ volatile(
    5c3c:	f384 8811 	msr	BASEPRI, r4
    5c40:	f3bf 8f6f 	isb	sy
}
    5c44:	bd10      	pop	{r4, pc}
	int ret = -EINVAL;
    5c46:	f06f 0015 	mvn.w	r0, #21
    5c4a:	e7f7      	b.n	5c3c <z_abort_timeout+0x1c>

00005c4c <z_get_next_timeout_expiry>:
{
    5c4c:	b510      	push	{r4, lr}
	__asm__ volatile(
    5c4e:	f04f 0320 	mov.w	r3, #32
    5c52:	f3ef 8411 	mrs	r4, BASEPRI
    5c56:	f383 8811 	msr	BASEPRI, r3
    5c5a:	f3bf 8f6f 	isb	sy
		ret = next_timeout();
    5c5e:	f7fe f99b 	bl	3f98 <next_timeout>
	__asm__ volatile(
    5c62:	f384 8811 	msr	BASEPRI, r4
    5c66:	f3bf 8f6f 	isb	sy
}
    5c6a:	bd10      	pop	{r4, pc}

00005c6c <z_set_timeout_expiry>:
{
    5c6c:	b537      	push	{r0, r1, r2, r4, r5, lr}
    5c6e:	4604      	mov	r4, r0
    5c70:	9101      	str	r1, [sp, #4]
	__asm__ volatile(
    5c72:	f04f 0320 	mov.w	r3, #32
    5c76:	f3ef 8511 	mrs	r5, BASEPRI
    5c7a:	f383 8811 	msr	BASEPRI, r3
    5c7e:	f3bf 8f6f 	isb	sy
		int next_to = next_timeout();
    5c82:	f7fe f989 	bl	3f98 <next_timeout>
		if (!imminent && (sooner || IS_ENABLED(CONFIG_SMP))) {
    5c86:	2801      	cmp	r0, #1
    5c88:	dd05      	ble.n	5c96 <z_set_timeout_expiry+0x2a>
    5c8a:	42a0      	cmp	r0, r4
    5c8c:	9901      	ldr	r1, [sp, #4]
    5c8e:	dd02      	ble.n	5c96 <z_set_timeout_expiry+0x2a>
			z_clock_set_timeout(ticks, is_idle);
    5c90:	4620      	mov	r0, r4
    5c92:	f7fb feaf 	bl	19f4 <z_clock_set_timeout>
	__asm__ volatile(
    5c96:	f385 8811 	msr	BASEPRI, r5
    5c9a:	f3bf 8f6f 	isb	sy
}
    5c9e:	b003      	add	sp, #12
    5ca0:	bd30      	pop	{r4, r5, pc}

00005ca2 <z_tick_get_32>:

uint32_t z_tick_get_32(void)
{
    5ca2:	b508      	push	{r3, lr}
#ifdef CONFIG_TICKLESS_KERNEL
	return (uint32_t)z_tick_get();
    5ca4:	f7fe fa9c 	bl	41e0 <z_tick_get>
#else
	return (uint32_t)curr_tick;
#endif
}
    5ca8:	bd08      	pop	{r3, pc}

00005caa <k_heap_init>:
{
    5caa:	b410      	push	{r4}
	sys_dlist_init(&w->waitq);
    5cac:	f100 040c 	add.w	r4, r0, #12
	list->tail = (sys_dnode_t *)list;
    5cb0:	e9c0 4403 	strd	r4, r4, [r0, #12]
}
    5cb4:	f85d 4b04 	ldr.w	r4, [sp], #4
	sys_heap_init(&h->heap, mem, bytes);
    5cb8:	f7ff bb87 	b.w	53ca <sys_heap_init>

00005cbc <_OffsetAbsSyms>:
#include "offsets_aarch64.c"
#else
#include "offsets_aarch32.c"
#endif

GEN_ABS_SYM_END
    5cbc:	4770      	bx	lr

Disassembly of section .gnu.sgstubs:

00006700 <spm_firmware_info_nse-0x18e0>:
	...

00007fe0 <spm_firmware_info_nse>:
    7fe0:	e97f e97f 	sg
    7fe4:	f7f9 bf40 	b.w	1e68 <__acle_se_spm_firmware_info_nse>

00007fe8 <spm_request_random_number_nse>:
    7fe8:	e97f e97f 	sg
    7fec:	f7fd bb7e 	b.w	56ec <__acle_se_spm_request_random_number_nse>

00007ff0 <spm_request_read_nse>:
    7ff0:	e97f e97f 	sg
    7ff4:	f7f9 bed6 	b.w	1da4 <__acle_se_spm_request_read_nse>
	...
