/*
 * Generated by gen_defines.py
 *
 * DTS input file:
 *   /home/bergm006/Downloads/advanced_non_blocking_internal_timer/build_dk/zephyr/zephyr.dts.pre
 *
 * Directories with bindings:
 *   /home/bergm006/ncs/v2.7.0/nrf/dts/bindings, $ZEPHYR_BASE/dts/bindings
 *
 * Node dependency ordering (ordinal and path):
 *   0   /
 *   1   /aliases
 *   2   /analog-connector
 *   3   /chosen
 *   4   /connector
 *   5   /entropy_bt_hci
 *   6   /soc
 *   7   /soc/interrupt-controller@e000e100
 *   8   /soc/timer@40009000
 *   9   /sw-pwm
 *   10  /soc/gpiote@40006000
 *   11  /soc/gpio@50000000
 *   12  /buttons
 *   13  /buttons/button_0
 *   14  /buttons/button_1
 *   15  /buttons/button_2
 *   16  /buttons/button_3
 *   17  /cpus
 *   18  /cpus/cpu@0
 *   19  /cpus/cpu@0/itm@e0000000
 *   20  /leds
 *   21  /leds/led_0
 *   22  /leds/led_1
 *   23  /leds/led_2
 *   24  /leds/led_3
 *   25  /pin-controller
 *   26  /pin-controller/i2c0_default
 *   27  /pin-controller/i2c0_default/group1
 *   28  /pin-controller/i2c0_sleep
 *   29  /pin-controller/i2c0_sleep/group1
 *   30  /pin-controller/i2c1_default
 *   31  /pin-controller/i2c1_default/group1
 *   32  /pin-controller/i2c1_sleep
 *   33  /pin-controller/i2c1_sleep/group1
 *   34  /pin-controller/pwm0_default
 *   35  /pin-controller/pwm0_default/group1
 *   36  /pin-controller/pwm0_sleep
 *   37  /pin-controller/pwm0_sleep/group1
 *   38  /pin-controller/qspi_default
 *   39  /pin-controller/qspi_default/group1
 *   40  /pin-controller/qspi_sleep
 *   41  /pin-controller/qspi_sleep/group1
 *   42  /pin-controller/qspi_sleep/group2
 *   43  /pin-controller/spi0_default
 *   44  /pin-controller/spi0_default/group1
 *   45  /pin-controller/spi0_sleep
 *   46  /pin-controller/spi0_sleep/group1
 *   47  /pin-controller/spi1_default
 *   48  /pin-controller/spi1_default/group1
 *   49  /pin-controller/spi1_sleep
 *   50  /pin-controller/spi1_sleep/group1
 *   51  /pin-controller/spi2_default
 *   52  /pin-controller/spi2_default/group1
 *   53  /pin-controller/spi2_sleep
 *   54  /pin-controller/spi2_sleep/group1
 *   55  /pin-controller/spi3_default
 *   56  /pin-controller/spi3_default/group1
 *   57  /pin-controller/spi3_sleep
 *   58  /pin-controller/spi3_sleep/group1
 *   59  /pin-controller/uart0_default
 *   60  /pin-controller/uart0_default/group1
 *   61  /pin-controller/uart0_default/group2
 *   62  /pin-controller/uart0_sleep
 *   63  /pin-controller/uart0_sleep/group1
 *   64  /pin-controller/uart1_default
 *   65  /pin-controller/uart1_default/group1
 *   66  /pin-controller/uart1_default/group2
 *   67  /pin-controller/uart1_sleep
 *   68  /pin-controller/uart1_sleep/group1
 *   69  /soc/pwm@4001c000
 *   70  /pwmleds
 *   71  /pwmleds/pwm_led_0
 *   72  /soc/acl@4001e000
 *   73  /soc/adc@40007000
 *   74  /soc/ccm@4000f000
 *   75  /soc/clock@40000000
 *   76  /soc/comparator@40013000
 *   77  /soc/crypto@5002a000
 *   78  /soc/ecb@4000e000
 *   79  /soc/egu@40014000
 *   80  /soc/egu@40015000
 *   81  /soc/egu@40016000
 *   82  /soc/egu@40017000
 *   83  /soc/egu@40018000
 *   84  /soc/egu@40019000
 *   85  /soc/ficr@10000000
 *   86  /soc/i2c@40003000
 *   87  /soc/i2c@40004000
 *   88  /soc/i2s@40025000
 *   89  /soc/memory@20000000
 *   90  /soc/mwu@40020000
 *   91  /soc/nfct@40005000
 *   92  /soc/pdm@4001d000
 *   93  /soc/ppi@4001f000
 *   94  /soc/pwm@40021000
 *   95  /soc/pwm@40022000
 *   96  /soc/pwm@4002d000
 *   97  /soc/qdec@40012000
 *   98  /soc/random@4000d000
 *   99  /soc/rtc@4000b000
 *   100 /soc/rtc@40011000
 *   101 /soc/rtc@40024000
 *   102 /soc/spi@40003000
 *   103 /soc/spi@40004000
 *   104 /soc/spi@40023000
 *   105 /soc/gpio@50000300
 *   106 /soc/spi@4002f000
 *   107 /soc/temp@4000c000
 *   108 /soc/timer@40008000
 *   109 /soc/timer@4000a000
 *   110 /soc/timer@4001a000
 *   111 /soc/timer@4001b000
 *   112 /soc/timer@e000e010
 *   113 /soc/uart@40002000
 *   114 /soc/uart@40028000
 *   115 /soc/uicr@10001000
 *   116 /soc/usbd@40027000
 *   117 /soc/watchdog@40010000
 *   118 /soc/flash-controller@4001e000
 *   119 /soc/flash-controller@4001e000/flash@0
 *   120 /soc/flash-controller@4001e000/flash@0/partitions
 *   121 /soc/flash-controller@4001e000/flash@0/partitions/partition@0
 *   122 /soc/flash-controller@4001e000/flash@0/partitions/partition@c000
 *   123 /soc/flash-controller@4001e000/flash@0/partitions/partition@82000
 *   124 /soc/flash-controller@4001e000/flash@0/partitions/partition@f8000
 *   125 /soc/power@40000000
 *   126 /soc/power@40000000/gpregret1@4000051c
 *   127 /soc/power@40000000/gpregret2@40000520
 *   128 /soc/qspi@40029000
 *   129 /soc/qspi@40029000/mx25r6435f@0
 *   130 /soc/radio@40001000
 *   131 /soc/radio@40001000/ieee802154
 *
 * Definitions derived from these nodes in dependency order are next,
 * followed by /chosen nodes.
 */

/* Used to remove brackets from around a single argument */
#define DT_DEBRACKET_INTERNAL(...) __VA_ARGS__

/*
 * Devicetree node: /
 *
 * Node identifier: DT_N
 */

/* Node's full path: */
#define DT_N_PATH "/"

/* Node's name with unit-address: */
#define DT_N_FULL_NAME "/"

/* Helper macros for child nodes of this node. */
#define DT_N_CHILD_NUM 12
#define DT_N_CHILD_NUM_STATUS_OKAY 11
#define DT_N_FOREACH_CHILD(fn) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_pin_controller) fn(DT_N_S_entropy_bt_hci) fn(DT_N_S_sw_pwm) fn(DT_N_S_cpus) fn(DT_N_S_leds) fn(DT_N_S_pwmleds) fn(DT_N_S_buttons) fn(DT_N_S_connector) fn(DT_N_S_analog_connector)
#define DT_N_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_chosen) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_entropy_bt_hci) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_sw_pwm) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_analog_connector)
#define DT_N_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_pin_controller, __VA_ARGS__) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) fn(DT_N_S_sw_pwm, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_pwmleds, __VA_ARGS__) fn(DT_N_S_buttons, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_analog_connector, __VA_ARGS__)
#define DT_N_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_chosen, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_sw_pwm, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_analog_connector, __VA_ARGS__)
#define DT_N_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_pin_controller) fn(DT_N_S_entropy_bt_hci) fn(DT_N_S_cpus) fn(DT_N_S_leds) fn(DT_N_S_pwmleds) fn(DT_N_S_buttons) fn(DT_N_S_connector) fn(DT_N_S_analog_connector)
#define DT_N_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_chosen) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_entropy_bt_hci) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_analog_connector)
#define DT_N_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_pin_controller, __VA_ARGS__) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_pwmleds, __VA_ARGS__) fn(DT_N_S_buttons, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_analog_connector, __VA_ARGS__)
#define DT_N_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_chosen, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pwmleds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_analog_connector, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_ORD 0
#define DT_N_ORD_STR_SORTABLE 00000

/* Ordinals for what this node depends on directly: */
#define DT_N_REQUIRES_ORDS /* nothing */

/* Ordinals for what depends directly on this node: */
#define DT_N_SUPPORTS_ORDS \
	1, /* /aliases */ \
	2, /* /analog-connector */ \
	3, /* /chosen */ \
	4, /* /connector */ \
	5, /* /entropy_bt_hci */ \
	6, /* /soc */ \
	9, /* /sw-pwm */ \
	12, /* /buttons */ \
	17, /* /cpus */ \
	20, /* /leds */ \
	25, /* /pin-controller */ \
	70, /* /pwmleds */

/* Existence and alternate IDs: */
#define DT_N_EXISTS 1
#define DT_N_INST_0_nordic_nrf52840_dk_nrf52840 DT_N

/* Macros for properties that are special in the specification: */
#define DT_N_REG_NUM 0
#define DT_N_RANGES_NUM 0
#define DT_N_FOREACH_RANGE(fn) 
#define DT_N_IRQ_NUM 0
#define DT_N_IRQ_LEVEL 0
#define DT_N_COMPAT_MATCHES_nordic_nrf52840_dk_nrf52840 1
#define DT_N_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_COMPAT_MODEL_IDX_0 "nrf52840-dk-nrf52840"
#define DT_N_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_P_compatible {"nordic,nrf52840-dk-nrf52840"}
#define DT_N_P_compatible_IDX_0 "nordic,nrf52840-dk-nrf52840"
#define DT_N_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf52840-dk-nrf52840
#define DT_N_P_compatible_IDX_0_STRING_TOKEN nordic_nrf52840_dk_nrf52840
#define DT_N_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF52840_DK_NRF52840
#define DT_N_P_compatible_IDX_0_EXISTS 1
#define DT_N_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N, compatible, 0)
#define DT_N_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N, compatible, 0)
#define DT_N_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N, compatible, 0, __VA_ARGS__)
#define DT_N_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N, compatible, 0, __VA_ARGS__)
#define DT_N_P_compatible_LEN 1
#define DT_N_P_compatible_EXISTS 1

/*
 * Devicetree node: /aliases
 *
 * Node identifier: DT_N_S_aliases
 */

/* Node's full path: */
#define DT_N_S_aliases_PATH "/aliases"

/* Node's name with unit-address: */
#define DT_N_S_aliases_FULL_NAME "aliases"

/* Node parent (/) identifier: */
#define DT_N_S_aliases_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_aliases_CHILD_IDX 1

/* Helper macros for child nodes of this node. */
#define DT_N_S_aliases_CHILD_NUM 0
#define DT_N_S_aliases_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_aliases_FOREACH_CHILD(fn) 
#define DT_N_S_aliases_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_aliases_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_aliases_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_aliases_ORD 1
#define DT_N_S_aliases_ORD_STR_SORTABLE 00001

/* Ordinals for what this node depends on directly: */
#define DT_N_S_aliases_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_aliases_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_aliases_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_aliases_REG_NUM 0
#define DT_N_S_aliases_RANGES_NUM 0
#define DT_N_S_aliases_FOREACH_RANGE(fn) 
#define DT_N_S_aliases_IRQ_NUM 0
#define DT_N_S_aliases_IRQ_LEVEL 0
#define DT_N_S_aliases_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_aliases_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /analog-connector
 *
 * Node identifier: DT_N_S_analog_connector
 *
 * Binding (compatible = arduino,uno-adc):
 *   $ZEPHYR_BASE/dts/bindings/adc/arduino,uno-adc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_analog_connector_PATH "/analog-connector"

/* Node's name with unit-address: */
#define DT_N_S_analog_connector_FULL_NAME "analog-connector"

/* Node parent (/) identifier: */
#define DT_N_S_analog_connector_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_analog_connector_CHILD_IDX 11

/* Helper macros for child nodes of this node. */
#define DT_N_S_analog_connector_CHILD_NUM 0
#define DT_N_S_analog_connector_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_analog_connector_FOREACH_CHILD(fn) 
#define DT_N_S_analog_connector_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_analog_connector_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_analog_connector_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_analog_connector_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_analog_connector_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_analog_connector_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_analog_connector_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_analog_connector_ORD 2
#define DT_N_S_analog_connector_ORD_STR_SORTABLE 00002

/* Ordinals for what this node depends on directly: */
#define DT_N_S_analog_connector_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_analog_connector_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_analog_connector_EXISTS 1
#define DT_N_INST_0_arduino_uno_adc DT_N_S_analog_connector
#define DT_N_NODELABEL_arduino_adc  DT_N_S_analog_connector

/* Macros for properties that are special in the specification: */
#define DT_N_S_analog_connector_REG_NUM 0
#define DT_N_S_analog_connector_RANGES_NUM 0
#define DT_N_S_analog_connector_FOREACH_RANGE(fn) 
#define DT_N_S_analog_connector_IRQ_NUM 0
#define DT_N_S_analog_connector_IRQ_LEVEL 0
#define DT_N_S_analog_connector_COMPAT_MATCHES_arduino_uno_adc 1
#define DT_N_S_analog_connector_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_analog_connector_COMPAT_VENDOR_IDX_0 "Arduino"
#define DT_N_S_analog_connector_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_analog_connector_COMPAT_MODEL_IDX_0 "uno-adc"
#define DT_N_S_analog_connector_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_analog_connector_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_analog_connector_P_wakeup_source 0
#define DT_N_S_analog_connector_P_wakeup_source_EXISTS 1
#define DT_N_S_analog_connector_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_analog_connector_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_analog_connector_P_compatible {"arduino,uno-adc"}
#define DT_N_S_analog_connector_P_compatible_IDX_0 "arduino,uno-adc"
#define DT_N_S_analog_connector_P_compatible_IDX_0_STRING_UNQUOTED arduino,uno-adc
#define DT_N_S_analog_connector_P_compatible_IDX_0_STRING_TOKEN arduino_uno_adc
#define DT_N_S_analog_connector_P_compatible_IDX_0_STRING_UPPER_TOKEN ARDUINO_UNO_ADC
#define DT_N_S_analog_connector_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_analog_connector_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_analog_connector, compatible, 0)
#define DT_N_S_analog_connector_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_analog_connector, compatible, 0)
#define DT_N_S_analog_connector_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_analog_connector, compatible, 0, __VA_ARGS__)
#define DT_N_S_analog_connector_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_analog_connector, compatible, 0, __VA_ARGS__)
#define DT_N_S_analog_connector_P_compatible_LEN 1
#define DT_N_S_analog_connector_P_compatible_EXISTS 1
#define DT_N_S_analog_connector_P_zephyr_deferred_init 0
#define DT_N_S_analog_connector_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /chosen
 *
 * Node identifier: DT_N_S_chosen
 */

/* Node's full path: */
#define DT_N_S_chosen_PATH "/chosen"

/* Node's name with unit-address: */
#define DT_N_S_chosen_FULL_NAME "chosen"

/* Node parent (/) identifier: */
#define DT_N_S_chosen_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_chosen_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_chosen_CHILD_NUM 0
#define DT_N_S_chosen_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_chosen_FOREACH_CHILD(fn) 
#define DT_N_S_chosen_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_chosen_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_chosen_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_chosen_ORD 3
#define DT_N_S_chosen_ORD_STR_SORTABLE 00003

/* Ordinals for what this node depends on directly: */
#define DT_N_S_chosen_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_chosen_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_chosen_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_chosen_REG_NUM 0
#define DT_N_S_chosen_RANGES_NUM 0
#define DT_N_S_chosen_FOREACH_RANGE(fn) 
#define DT_N_S_chosen_IRQ_NUM 0
#define DT_N_S_chosen_IRQ_LEVEL 0
#define DT_N_S_chosen_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_chosen_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /connector
 *
 * Node identifier: DT_N_S_connector
 *
 * Binding (compatible = arduino-header-r3):
 *   $ZEPHYR_BASE/dts/bindings/gpio/arduino-header-r3.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_connector_PATH "/connector"

/* Node's name with unit-address: */
#define DT_N_S_connector_FULL_NAME "connector"

/* Node parent (/) identifier: */
#define DT_N_S_connector_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_connector_CHILD_IDX 10

/* Helper macros for child nodes of this node. */
#define DT_N_S_connector_CHILD_NUM 0
#define DT_N_S_connector_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_connector_FOREACH_CHILD(fn) 
#define DT_N_S_connector_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_connector_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_connector_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_connector_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_connector_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_connector_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_connector_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_connector_ORD 4
#define DT_N_S_connector_ORD_STR_SORTABLE 00004

/* Ordinals for what this node depends on directly: */
#define DT_N_S_connector_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_connector_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_connector_EXISTS 1
#define DT_N_INST_0_arduino_header_r3 DT_N_S_connector
#define DT_N_NODELABEL_arduino_header DT_N_S_connector

/* Macros for properties that are special in the specification: */
#define DT_N_S_connector_REG_NUM 0
#define DT_N_S_connector_RANGES_NUM 0
#define DT_N_S_connector_FOREACH_RANGE(fn) 
#define DT_N_S_connector_IRQ_NUM 0
#define DT_N_S_connector_IRQ_LEVEL 0
#define DT_N_S_connector_COMPAT_MATCHES_arduino_header_r3 1
#define DT_N_S_connector_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_connector_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_connector_P_wakeup_source 0
#define DT_N_S_connector_P_wakeup_source_EXISTS 1
#define DT_N_S_connector_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_connector_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_connector_P_compatible {"arduino-header-r3"}
#define DT_N_S_connector_P_compatible_IDX_0 "arduino-header-r3"
#define DT_N_S_connector_P_compatible_IDX_0_STRING_UNQUOTED arduino-header-r3
#define DT_N_S_connector_P_compatible_IDX_0_STRING_TOKEN arduino_header_r3
#define DT_N_S_connector_P_compatible_IDX_0_STRING_UPPER_TOKEN ARDUINO_HEADER_R3
#define DT_N_S_connector_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_connector_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_connector, compatible, 0)
#define DT_N_S_connector_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_connector, compatible, 0)
#define DT_N_S_connector_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_connector, compatible, 0, __VA_ARGS__)
#define DT_N_S_connector_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_connector, compatible, 0, __VA_ARGS__)
#define DT_N_S_connector_P_compatible_LEN 1
#define DT_N_S_connector_P_compatible_EXISTS 1
#define DT_N_S_connector_P_zephyr_deferred_init 0
#define DT_N_S_connector_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /entropy_bt_hci
 *
 * Node identifier: DT_N_S_entropy_bt_hci
 *
 * Binding (compatible = zephyr,bt-hci-entropy):
 *   $ZEPHYR_BASE/dts/bindings/bluetooth/zephyr,bt-hci-entropy.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_entropy_bt_hci_PATH "/entropy_bt_hci"

/* Node's name with unit-address: */
#define DT_N_S_entropy_bt_hci_FULL_NAME "entropy_bt_hci"

/* Node parent (/) identifier: */
#define DT_N_S_entropy_bt_hci_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_entropy_bt_hci_CHILD_IDX 4

/* Helper macros for child nodes of this node. */
#define DT_N_S_entropy_bt_hci_CHILD_NUM 0
#define DT_N_S_entropy_bt_hci_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD(fn) 
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_entropy_bt_hci_ORD 5
#define DT_N_S_entropy_bt_hci_ORD_STR_SORTABLE 00005

/* Ordinals for what this node depends on directly: */
#define DT_N_S_entropy_bt_hci_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_entropy_bt_hci_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_entropy_bt_hci_EXISTS 1
#define DT_N_INST_0_zephyr_bt_hci_entropy DT_N_S_entropy_bt_hci
#define DT_N_NODELABEL_rng_hci            DT_N_S_entropy_bt_hci

/* Macros for properties that are special in the specification: */
#define DT_N_S_entropy_bt_hci_REG_NUM 0
#define DT_N_S_entropy_bt_hci_RANGES_NUM 0
#define DT_N_S_entropy_bt_hci_FOREACH_RANGE(fn) 
#define DT_N_S_entropy_bt_hci_IRQ_NUM 0
#define DT_N_S_entropy_bt_hci_IRQ_LEVEL 0
#define DT_N_S_entropy_bt_hci_COMPAT_MATCHES_zephyr_bt_hci_entropy 1
#define DT_N_S_entropy_bt_hci_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_entropy_bt_hci_COMPAT_VENDOR_IDX_0 "Zephyr-specific binding"
#define DT_N_S_entropy_bt_hci_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_entropy_bt_hci_COMPAT_MODEL_IDX_0 "bt-hci-entropy"
#define DT_N_S_entropy_bt_hci_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_entropy_bt_hci_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_entropy_bt_hci_P_wakeup_source 0
#define DT_N_S_entropy_bt_hci_P_wakeup_source_EXISTS 1
#define DT_N_S_entropy_bt_hci_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_entropy_bt_hci_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_entropy_bt_hci_P_status "okay"
#define DT_N_S_entropy_bt_hci_P_status_STRING_UNQUOTED okay
#define DT_N_S_entropy_bt_hci_P_status_STRING_TOKEN okay
#define DT_N_S_entropy_bt_hci_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_entropy_bt_hci_P_status_IDX_0 "okay"
#define DT_N_S_entropy_bt_hci_P_status_IDX_0_EXISTS 1
#define DT_N_S_entropy_bt_hci_P_status_ENUM_IDX 1
#define DT_N_S_entropy_bt_hci_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_entropy_bt_hci_P_status_ENUM_TOKEN okay
#define DT_N_S_entropy_bt_hci_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_entropy_bt_hci, status, 0)
#define DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_entropy_bt_hci, status, 0)
#define DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_entropy_bt_hci, status, 0, __VA_ARGS__)
#define DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_entropy_bt_hci, status, 0, __VA_ARGS__)
#define DT_N_S_entropy_bt_hci_P_status_LEN 1
#define DT_N_S_entropy_bt_hci_P_status_EXISTS 1
#define DT_N_S_entropy_bt_hci_P_compatible {"zephyr,bt-hci-entropy"}
#define DT_N_S_entropy_bt_hci_P_compatible_IDX_0 "zephyr,bt-hci-entropy"
#define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_STRING_UNQUOTED zephyr,bt-hci-entropy
#define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_STRING_TOKEN zephyr_bt_hci_entropy
#define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_BT_HCI_ENTROPY
#define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_entropy_bt_hci, compatible, 0)
#define DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_entropy_bt_hci, compatible, 0)
#define DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_entropy_bt_hci, compatible, 0, __VA_ARGS__)
#define DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_entropy_bt_hci, compatible, 0, __VA_ARGS__)
#define DT_N_S_entropy_bt_hci_P_compatible_LEN 1
#define DT_N_S_entropy_bt_hci_P_compatible_EXISTS 1
#define DT_N_S_entropy_bt_hci_P_zephyr_deferred_init 0
#define DT_N_S_entropy_bt_hci_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc
 *
 * Node identifier: DT_N_S_soc
 */

/* Node's full path: */
#define DT_N_S_soc_PATH "/soc"

/* Node's name with unit-address: */
#define DT_N_S_soc_FULL_NAME "soc"

/* Node parent (/) identifier: */
#define DT_N_S_soc_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_CHILD_IDX 2

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_CHILD_NUM 55
#define DT_N_S_soc_CHILD_NUM_STATUS_OKAY 34
#define DT_N_S_soc_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_ficr_10000000) fn(DT_N_S_soc_S_uicr_10001000) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_clock_40000000) fn(DT_N_S_soc_S_power_40000000) fn(DT_N_S_soc_S_radio_40001000) fn(DT_N_S_soc_S_uart_40002000) fn(DT_N_S_soc_S_i2c_40003000) fn(DT_N_S_soc_S_spi_40003000) fn(DT_N_S_soc_S_i2c_40004000) fn(DT_N_S_soc_S_spi_40004000) fn(DT_N_S_soc_S_nfct_40005000) fn(DT_N_S_soc_S_gpiote_40006000) fn(DT_N_S_soc_S_adc_40007000) fn(DT_N_S_soc_S_timer_40008000) fn(DT_N_S_soc_S_timer_40009000) fn(DT_N_S_soc_S_timer_4000a000) fn(DT_N_S_soc_S_rtc_4000b000) fn(DT_N_S_soc_S_temp_4000c000) fn(DT_N_S_soc_S_random_4000d000) fn(DT_N_S_soc_S_ecb_4000e000) fn(DT_N_S_soc_S_ccm_4000f000) fn(DT_N_S_soc_S_watchdog_40010000) fn(DT_N_S_soc_S_rtc_40011000) fn(DT_N_S_soc_S_qdec_40012000) fn(DT_N_S_soc_S_comparator_40013000) fn(DT_N_S_soc_S_egu_40014000) fn(DT_N_S_soc_S_egu_40015000) fn(DT_N_S_soc_S_egu_40016000) fn(DT_N_S_soc_S_egu_40017000) fn(DT_N_S_soc_S_egu_40018000) fn(DT_N_S_soc_S_egu_40019000) fn(DT_N_S_soc_S_timer_4001a000) fn(DT_N_S_soc_S_timer_4001b000) fn(DT_N_S_soc_S_pwm_4001c000) fn(DT_N_S_soc_S_pdm_4001d000) fn(DT_N_S_soc_S_acl_4001e000) fn(DT_N_S_soc_S_flash_controller_4001e000) fn(DT_N_S_soc_S_ppi_4001f000) fn(DT_N_S_soc_S_mwu_40020000) fn(DT_N_S_soc_S_pwm_40021000) fn(DT_N_S_soc_S_pwm_40022000) fn(DT_N_S_soc_S_spi_40023000) fn(DT_N_S_soc_S_rtc_40024000) fn(DT_N_S_soc_S_i2s_40025000) fn(DT_N_S_soc_S_usbd_40027000) fn(DT_N_S_soc_S_uart_40028000) fn(DT_N_S_soc_S_qspi_40029000) fn(DT_N_S_soc_S_pwm_4002d000) fn(DT_N_S_soc_S_spi_4002f000) fn(DT_N_S_soc_S_gpio_50000000) fn(DT_N_S_soc_S_gpio_50000300) fn(DT_N_S_soc_S_crypto_5002a000)
#define DT_N_S_soc_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_e000e100) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_e000e010) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ficr_10000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uicr_10001000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_clock_40000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_power_40000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_radio_40001000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uart_40002000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_40003000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40003000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_40004000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40004000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_nfct_40005000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpiote_40006000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40007000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_40008000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_40009000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_4000a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rtc_4000b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_temp_4000c000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_random_4000d000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ecb_4000e000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ccm_4000f000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_watchdog_40010000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rtc_40011000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_qdec_40012000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_comparator_40013000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_egu_40014000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_egu_40015000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_egu_40016000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_egu_40017000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_egu_40018000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_egu_40019000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_4001a000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_4001b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pwm_4001c000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pdm_4001d000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_acl_4001e000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_4001e000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ppi_4001f000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_mwu_40020000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pwm_40021000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pwm_40022000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40023000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rtc_40024000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2s_40025000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_usbd_40027000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uart_40028000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_qspi_40029000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pwm_4002d000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_4002f000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpio_50000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpio_50000300) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_crypto_5002a000)
#define DT_N_S_soc_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) fn(DT_N_S_soc_S_ficr_10000000, __VA_ARGS__) fn(DT_N_S_soc_S_uicr_10001000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_soc_S_clock_40000000, __VA_ARGS__) fn(DT_N_S_soc_S_power_40000000, __VA_ARGS__) fn(DT_N_S_soc_S_radio_40001000, __VA_ARGS__) fn(DT_N_S_soc_S_uart_40002000, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40003000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40003000, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40004000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40004000, __VA_ARGS__) fn(DT_N_S_soc_S_nfct_40005000, __VA_ARGS__) fn(DT_N_S_soc_S_gpiote_40006000, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40007000, __VA_ARGS__) fn(DT_N_S_soc_S_timer_40008000, __VA_ARGS__) fn(DT_N_S_soc_S_timer_40009000, __VA_ARGS__) fn(DT_N_S_soc_S_timer_4000a000, __VA_ARGS__) fn(DT_N_S_soc_S_rtc_4000b000, __VA_ARGS__) fn(DT_N_S_soc_S_temp_4000c000, __VA_ARGS__) fn(DT_N_S_soc_S_random_4000d000, __VA_ARGS__) fn(DT_N_S_soc_S_ecb_4000e000, __VA_ARGS__) fn(DT_N_S_soc_S_ccm_4000f000, __VA_ARGS__) fn(DT_N_S_soc_S_watchdog_40010000, __VA_ARGS__) fn(DT_N_S_soc_S_rtc_40011000, __VA_ARGS__) fn(DT_N_S_soc_S_qdec_40012000, __VA_ARGS__) fn(DT_N_S_soc_S_comparator_40013000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40014000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40015000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40016000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40017000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40018000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40019000, __VA_ARGS__) fn(DT_N_S_soc_S_timer_4001a000, __VA_ARGS__) fn(DT_N_S_soc_S_timer_4001b000, __VA_ARGS__) fn(DT_N_S_soc_S_pwm_4001c000, __VA_ARGS__) fn(DT_N_S_soc_S_pdm_4001d000, __VA_ARGS__) fn(DT_N_S_soc_S_acl_4001e000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_4001e000, __VA_ARGS__) fn(DT_N_S_soc_S_ppi_4001f000, __VA_ARGS__) fn(DT_N_S_soc_S_mwu_40020000, __VA_ARGS__) fn(DT_N_S_soc_S_pwm_40021000, __VA_ARGS__) fn(DT_N_S_soc_S_pwm_40022000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40023000, __VA_ARGS__) fn(DT_N_S_soc_S_rtc_40024000, __VA_ARGS__) fn(DT_N_S_soc_S_i2s_40025000, __VA_ARGS__) fn(DT_N_S_soc_S_usbd_40027000, __VA_ARGS__) fn(DT_N_S_soc_S_uart_40028000, __VA_ARGS__) fn(DT_N_S_soc_S_qspi_40029000, __VA_ARGS__) fn(DT_N_S_soc_S_pwm_4002d000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_4002f000, __VA_ARGS__) fn(DT_N_S_soc_S_gpio_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_gpio_50000300, __VA_ARGS__) fn(DT_N_S_soc_S_crypto_5002a000, __VA_ARGS__)
#define DT_N_S_soc_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ficr_10000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uicr_10001000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_clock_40000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_power_40000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_radio_40001000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uart_40002000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_40003000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40003000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_40004000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40004000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_nfct_40005000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpiote_40006000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40007000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_40008000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_40009000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_4000a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rtc_4000b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_temp_4000c000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_random_4000d000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ecb_4000e000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ccm_4000f000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_watchdog_40010000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rtc_40011000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_qdec_40012000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_comparator_40013000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_egu_40014000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_egu_40015000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_egu_40016000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_egu_40017000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_egu_40018000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_egu_40019000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_4001a000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_timer_4001b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pwm_4001c000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pdm_4001d000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_acl_4001e000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_4001e000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ppi_4001f000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_mwu_40020000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pwm_40021000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pwm_40022000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40023000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rtc_40024000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2s_40025000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_usbd_40027000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uart_40028000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_qspi_40029000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pwm_4002d000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_4002f000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpio_50000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpio_50000300, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_crypto_5002a000, __VA_ARGS__)
#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_ficr_10000000) fn(DT_N_S_soc_S_uicr_10001000) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_clock_40000000) fn(DT_N_S_soc_S_power_40000000) fn(DT_N_S_soc_S_radio_40001000) fn(DT_N_S_soc_S_uart_40002000) fn(DT_N_S_soc_S_i2c_40003000) fn(DT_N_S_soc_S_spi_40004000) fn(DT_N_S_soc_S_gpiote_40006000) fn(DT_N_S_soc_S_adc_40007000) fn(DT_N_S_soc_S_temp_4000c000) fn(DT_N_S_soc_S_random_4000d000) fn(DT_N_S_soc_S_ecb_4000e000) fn(DT_N_S_soc_S_ccm_4000f000) fn(DT_N_S_soc_S_watchdog_40010000) fn(DT_N_S_soc_S_egu_40014000) fn(DT_N_S_soc_S_egu_40015000) fn(DT_N_S_soc_S_egu_40016000) fn(DT_N_S_soc_S_egu_40017000) fn(DT_N_S_soc_S_egu_40018000) fn(DT_N_S_soc_S_egu_40019000) fn(DT_N_S_soc_S_pwm_4001c000) fn(DT_N_S_soc_S_acl_4001e000) fn(DT_N_S_soc_S_flash_controller_4001e000) fn(DT_N_S_soc_S_ppi_4001f000) fn(DT_N_S_soc_S_mwu_40020000) fn(DT_N_S_soc_S_usbd_40027000) fn(DT_N_S_soc_S_qspi_40029000) fn(DT_N_S_soc_S_spi_4002f000) fn(DT_N_S_soc_S_gpio_50000000) fn(DT_N_S_soc_S_gpio_50000300) fn(DT_N_S_soc_S_crypto_5002a000)
#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_e000e100) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ficr_10000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uicr_10001000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_20000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_clock_40000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_power_40000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_radio_40001000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uart_40002000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_40003000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40004000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpiote_40006000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40007000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_temp_4000c000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_random_4000d000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ecb_4000e000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ccm_4000f000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_watchdog_40010000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_egu_40014000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_egu_40015000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_egu_40016000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_egu_40017000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_egu_40018000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_egu_40019000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pwm_4001c000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_acl_4001e000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_4001e000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ppi_4001f000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_mwu_40020000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_usbd_40027000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_qspi_40029000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_4002f000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpio_50000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpio_50000300) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_crypto_5002a000)
#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_ficr_10000000, __VA_ARGS__) fn(DT_N_S_soc_S_uicr_10001000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_soc_S_clock_40000000, __VA_ARGS__) fn(DT_N_S_soc_S_power_40000000, __VA_ARGS__) fn(DT_N_S_soc_S_radio_40001000, __VA_ARGS__) fn(DT_N_S_soc_S_uart_40002000, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40003000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40004000, __VA_ARGS__) fn(DT_N_S_soc_S_gpiote_40006000, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40007000, __VA_ARGS__) fn(DT_N_S_soc_S_temp_4000c000, __VA_ARGS__) fn(DT_N_S_soc_S_random_4000d000, __VA_ARGS__) fn(DT_N_S_soc_S_ecb_4000e000, __VA_ARGS__) fn(DT_N_S_soc_S_ccm_4000f000, __VA_ARGS__) fn(DT_N_S_soc_S_watchdog_40010000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40014000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40015000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40016000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40017000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40018000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40019000, __VA_ARGS__) fn(DT_N_S_soc_S_pwm_4001c000, __VA_ARGS__) fn(DT_N_S_soc_S_acl_4001e000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_4001e000, __VA_ARGS__) fn(DT_N_S_soc_S_ppi_4001f000, __VA_ARGS__) fn(DT_N_S_soc_S_mwu_40020000, __VA_ARGS__) fn(DT_N_S_soc_S_usbd_40027000, __VA_ARGS__) fn(DT_N_S_soc_S_qspi_40029000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_4002f000, __VA_ARGS__) fn(DT_N_S_soc_S_gpio_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_gpio_50000300, __VA_ARGS__) fn(DT_N_S_soc_S_crypto_5002a000, __VA_ARGS__)
#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ficr_10000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uicr_10001000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_clock_40000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_power_40000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_radio_40001000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uart_40002000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_40003000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_40004000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpiote_40006000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_40007000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_temp_4000c000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_random_4000d000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ecb_4000e000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ccm_4000f000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_watchdog_40010000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_egu_40014000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_egu_40015000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_egu_40016000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_egu_40017000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_egu_40018000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_egu_40019000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pwm_4001c000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_acl_4001e000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_4001e000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ppi_4001f000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_mwu_40020000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_usbd_40027000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_qspi_40029000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_4002f000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpio_50000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpio_50000300, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_crypto_5002a000, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_ORD 6
#define DT_N_S_soc_ORD_STR_SORTABLE 00006

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_SUPPORTS_ORDS \
	7, /* /soc/interrupt-controller@e000e100 */ \
	8, /* /soc/timer@40009000 */ \
	10, /* /soc/gpiote@40006000 */ \
	11, /* /soc/gpio@50000000 */ \
	69, /* /soc/pwm@4001c000 */ \
	72, /* /soc/acl@4001e000 */ \
	73, /* /soc/adc@40007000 */ \
	74, /* /soc/ccm@4000f000 */ \
	75, /* /soc/clock@40000000 */ \
	76, /* /soc/comparator@40013000 */ \
	77, /* /soc/crypto@5002a000 */ \
	78, /* /soc/ecb@4000e000 */ \
	79, /* /soc/egu@40014000 */ \
	80, /* /soc/egu@40015000 */ \
	81, /* /soc/egu@40016000 */ \
	82, /* /soc/egu@40017000 */ \
	83, /* /soc/egu@40018000 */ \
	84, /* /soc/egu@40019000 */ \
	85, /* /soc/ficr@10000000 */ \
	86, /* /soc/i2c@40003000 */ \
	87, /* /soc/i2c@40004000 */ \
	88, /* /soc/i2s@40025000 */ \
	89, /* /soc/memory@20000000 */ \
	90, /* /soc/mwu@40020000 */ \
	91, /* /soc/nfct@40005000 */ \
	92, /* /soc/pdm@4001d000 */ \
	93, /* /soc/ppi@4001f000 */ \
	94, /* /soc/pwm@40021000 */ \
	95, /* /soc/pwm@40022000 */ \
	96, /* /soc/pwm@4002d000 */ \
	97, /* /soc/qdec@40012000 */ \
	98, /* /soc/random@4000d000 */ \
	99, /* /soc/rtc@4000b000 */ \
	100, /* /soc/rtc@40011000 */ \
	101, /* /soc/rtc@40024000 */ \
	102, /* /soc/spi@40003000 */ \
	103, /* /soc/spi@40004000 */ \
	104, /* /soc/spi@40023000 */ \
	105, /* /soc/gpio@50000300 */ \
	106, /* /soc/spi@4002f000 */ \
	107, /* /soc/temp@4000c000 */ \
	108, /* /soc/timer@40008000 */ \
	109, /* /soc/timer@4000a000 */ \
	110, /* /soc/timer@4001a000 */ \
	111, /* /soc/timer@4001b000 */ \
	112, /* /soc/timer@e000e010 */ \
	113, /* /soc/uart@40002000 */ \
	114, /* /soc/uart@40028000 */ \
	115, /* /soc/uicr@10001000 */ \
	116, /* /soc/usbd@40027000 */ \
	117, /* /soc/watchdog@40010000 */ \
	118, /* /soc/flash-controller@4001e000 */ \
	125, /* /soc/power@40000000 */ \
	128, /* /soc/qspi@40029000 */ \
	130, /* /soc/radio@40001000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_EXISTS 1
#define DT_N_INST_0_nordic_nrf52840_qiaa DT_N_S_soc
#define DT_N_INST_0_nordic_nrf52840      DT_N_S_soc
#define DT_N_INST_0_nordic_nrf52         DT_N_S_soc
#define DT_N_INST_0_simple_bus           DT_N_S_soc

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_REG_NUM 0
#define DT_N_S_soc_RANGES_NUM 0
#define DT_N_S_soc_FOREACH_RANGE(fn) 
#define DT_N_S_soc_IRQ_NUM 0
#define DT_N_S_soc_IRQ_LEVEL 0
#define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf52840_qiaa 1
#define DT_N_S_soc_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_COMPAT_MODEL_IDX_0 "nrf52840-qiaa"
#define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf52840 1
#define DT_N_S_soc_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_COMPAT_VENDOR_IDX_1 "Nordic Semiconductor"
#define DT_N_S_soc_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_COMPAT_MODEL_IDX_1 "nrf52840"
#define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf52 1
#define DT_N_S_soc_COMPAT_VENDOR_IDX_2_EXISTS 1
#define DT_N_S_soc_COMPAT_VENDOR_IDX_2 "Nordic Semiconductor"
#define DT_N_S_soc_COMPAT_MODEL_IDX_2_EXISTS 1
#define DT_N_S_soc_COMPAT_MODEL_IDX_2 "nrf52"
#define DT_N_S_soc_COMPAT_MATCHES_simple_bus 1
#define DT_N_S_soc_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_P_compatible {"nordic,nrf52840-qiaa", "nordic,nrf52840", "nordic,nrf52", "simple-bus"}
#define DT_N_S_soc_P_compatible_IDX_0 "nordic,nrf52840-qiaa"
#define DT_N_S_soc_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf52840-qiaa
#define DT_N_S_soc_P_compatible_IDX_0_STRING_TOKEN nordic_nrf52840_qiaa
#define DT_N_S_soc_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF52840_QIAA
#define DT_N_S_soc_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_P_compatible_IDX_1 "nordic,nrf52840"
#define DT_N_S_soc_P_compatible_IDX_1_STRING_UNQUOTED nordic,nrf52840
#define DT_N_S_soc_P_compatible_IDX_1_STRING_TOKEN nordic_nrf52840
#define DT_N_S_soc_P_compatible_IDX_1_STRING_UPPER_TOKEN NORDIC_NRF52840
#define DT_N_S_soc_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_P_compatible_IDX_2 "nordic,nrf52"
#define DT_N_S_soc_P_compatible_IDX_2_STRING_UNQUOTED nordic,nrf52
#define DT_N_S_soc_P_compatible_IDX_2_STRING_TOKEN nordic_nrf52
#define DT_N_S_soc_P_compatible_IDX_2_STRING_UPPER_TOKEN NORDIC_NRF52
#define DT_N_S_soc_P_compatible_IDX_2_EXISTS 1
#define DT_N_S_soc_P_compatible_IDX_3 "simple-bus"
#define DT_N_S_soc_P_compatible_IDX_3_STRING_UNQUOTED simple-bus
#define DT_N_S_soc_P_compatible_IDX_3_STRING_TOKEN simple_bus
#define DT_N_S_soc_P_compatible_IDX_3_STRING_UPPER_TOKEN SIMPLE_BUS
#define DT_N_S_soc_P_compatible_IDX_3_EXISTS 1
#define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc, compatible, 0) \
	fn(DT_N_S_soc, compatible, 1) \
	fn(DT_N_S_soc, compatible, 2) \
	fn(DT_N_S_soc, compatible, 3)
#define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc, compatible, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc, compatible, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc, compatible, 3)
#define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc, compatible, 1, __VA_ARGS__) \
	fn(DT_N_S_soc, compatible, 2, __VA_ARGS__) \
	fn(DT_N_S_soc, compatible, 3, __VA_ARGS__)
#define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc, compatible, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc, compatible, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc, compatible, 3, __VA_ARGS__)
#define DT_N_S_soc_P_compatible_LEN 4
#define DT_N_S_soc_P_compatible_EXISTS 1
#define DT_N_S_soc_P_ranges_EXISTS 1

/*
 * Devicetree node: /soc/interrupt-controller@e000e100
 *
 * Node identifier: DT_N_S_soc_S_interrupt_controller_e000e100
 *
 * Binding (compatible = arm,v7m-nvic):
 *   $ZEPHYR_BASE/dts/bindings/interrupt-controller/arm,v7m-nvic.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_PATH "/soc/interrupt-controller@e000e100"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_FULL_NAME "interrupt-controller@e000e100"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_interrupt_controller_e000e100_CHILD_NUM 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_ORD 7
#define DT_N_S_soc_S_interrupt_controller_e000e100_ORD_STR_SORTABLE 00007

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_REQUIRES_ORDS \
	6, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_SUPPORTS_ORDS \
	8, /* /soc/timer@40009000 */ \
	10, /* /soc/gpiote@40006000 */ \
	69, /* /soc/pwm@4001c000 */ \
	73, /* /soc/adc@40007000 */ \
	74, /* /soc/ccm@4000f000 */ \
	75, /* /soc/clock@40000000 */ \
	76, /* /soc/comparator@40013000 */ \
	77, /* /soc/crypto@5002a000 */ \
	78, /* /soc/ecb@4000e000 */ \
	79, /* /soc/egu@40014000 */ \
	80, /* /soc/egu@40015000 */ \
	81, /* /soc/egu@40016000 */ \
	82, /* /soc/egu@40017000 */ \
	83, /* /soc/egu@40018000 */ \
	84, /* /soc/egu@40019000 */ \
	86, /* /soc/i2c@40003000 */ \
	87, /* /soc/i2c@40004000 */ \
	88, /* /soc/i2s@40025000 */ \
	91, /* /soc/nfct@40005000 */ \
	92, /* /soc/pdm@4001d000 */ \
	94, /* /soc/pwm@40021000 */ \
	95, /* /soc/pwm@40022000 */ \
	96, /* /soc/pwm@4002d000 */ \
	97, /* /soc/qdec@40012000 */ \
	98, /* /soc/random@4000d000 */ \
	99, /* /soc/rtc@4000b000 */ \
	100, /* /soc/rtc@40011000 */ \
	101, /* /soc/rtc@40024000 */ \
	102, /* /soc/spi@40003000 */ \
	103, /* /soc/spi@40004000 */ \
	104, /* /soc/spi@40023000 */ \
	106, /* /soc/spi@4002f000 */ \
	107, /* /soc/temp@4000c000 */ \
	108, /* /soc/timer@40008000 */ \
	109, /* /soc/timer@4000a000 */ \
	110, /* /soc/timer@4001a000 */ \
	111, /* /soc/timer@4001b000 */ \
	113, /* /soc/uart@40002000 */ \
	114, /* /soc/uart@40028000 */ \
	116, /* /soc/usbd@40027000 */ \
	117, /* /soc/watchdog@40010000 */ \
	125, /* /soc/power@40000000 */ \
	128, /* /soc/qspi@40029000 */ \
	130, /* /soc/radio@40001000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_EXISTS 1
#define DT_N_INST_0_arm_v7m_nvic DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_NODELABEL_nvic      DT_N_S_soc_S_interrupt_controller_e000e100

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_NUM 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_VAL_ADDRESS 3758153984 /* 0xe000e100 */
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_VAL_SIZE 3072 /* 0xc00 */
#define DT_N_S_soc_S_interrupt_controller_e000e100_RANGES_NUM 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_interrupt_controller_e000e100_IRQ_NUM 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_IRQ_LEVEL 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_MATCHES_arm_v7m_nvic 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_VENDOR_IDX_0 "ARM Ltd."
#define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_MODEL_IDX_0 "v7m-nvic"
#define DT_N_S_soc_S_interrupt_controller_e000e100_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_interrupt_controller 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_interrupt_controller_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_wakeup_source 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible {"arm,v7m-nvic"}
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0 "arm,v7m-nvic"
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_STRING_UNQUOTED arm,v7m-nvic
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_STRING_TOKEN arm_v7m_nvic
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_V7M_NVIC
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0)
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0)
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_LEN 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg {3758153984 /* 0xe000e100 */, 3072 /* 0xc00 */}
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_0 3758153984
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_1 3072
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits 3
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits_EXISTS 1

/*
 * Devicetree node: /soc/timer@40009000
 *
 * Node identifier: DT_N_S_soc_S_timer_40009000
 *
 * Binding (compatible = nordic,nrf-timer):
 *   $ZEPHYR_BASE/dts/bindings/timer/nordic,nrf-timer.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timer_40009000_PATH "/soc/timer@40009000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timer_40009000_FULL_NAME "timer@40009000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timer_40009000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timer_40009000_CHILD_IDX 17

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timer_40009000_CHILD_NUM 0
#define DT_N_S_soc_S_timer_40009000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timer_40009000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timer_40009000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timer_40009000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timer_40009000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timer_40009000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timer_40009000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timer_40009000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timer_40009000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timer_40009000_ORD 8
#define DT_N_S_soc_S_timer_40009000_ORD_STR_SORTABLE 00008

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timer_40009000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timer_40009000_SUPPORTS_ORDS \
	9, /* /sw-pwm */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timer_40009000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_timer DT_N_S_soc_S_timer_40009000
#define DT_N_NODELABEL_timer1        DT_N_S_soc_S_timer_40009000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timer_40009000_REG_NUM 1
#define DT_N_S_soc_S_timer_40009000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_40009000_REG_IDX_0_VAL_ADDRESS 1073778688 /* 0x40009000 */
#define DT_N_S_soc_S_timer_40009000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_timer_40009000_RANGES_NUM 0
#define DT_N_S_soc_S_timer_40009000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timer_40009000_IRQ_NUM 1
#define DT_N_S_soc_S_timer_40009000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_40009000_IRQ_IDX_0_VAL_irq 9
#define DT_N_S_soc_S_timer_40009000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timer_40009000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_40009000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_timer_40009000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timer_40009000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timer_40009000_IRQ_LEVEL 1
#define DT_N_S_soc_S_timer_40009000_COMPAT_MATCHES_nordic_nrf_timer 1
#define DT_N_S_soc_S_timer_40009000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_40009000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_timer_40009000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_40009000_COMPAT_MODEL_IDX_0 "nrf-timer"
#define DT_N_S_soc_S_timer_40009000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timer_40009000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timer_40009000_P_wakeup_source 0
#define DT_N_S_soc_S_timer_40009000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timer_40009000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timer_40009000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_timer_40009000_P_status "disabled"
#define DT_N_S_soc_S_timer_40009000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timer_40009000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timer_40009000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timer_40009000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timer_40009000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_40009000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_timer_40009000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timer_40009000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_timer_40009000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timer_40009000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timer_40009000, status, 0)
#define DT_N_S_soc_S_timer_40009000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timer_40009000, status, 0)
#define DT_N_S_soc_S_timer_40009000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timer_40009000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_40009000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timer_40009000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_40009000_P_status_LEN 1
#define DT_N_S_soc_S_timer_40009000_P_status_EXISTS 1
#define DT_N_S_soc_S_timer_40009000_P_compatible {"nordic,nrf-timer"}
#define DT_N_S_soc_S_timer_40009000_P_compatible_IDX_0 "nordic,nrf-timer"
#define DT_N_S_soc_S_timer_40009000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-timer
#define DT_N_S_soc_S_timer_40009000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_timer
#define DT_N_S_soc_S_timer_40009000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TIMER
#define DT_N_S_soc_S_timer_40009000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_40009000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timer_40009000, compatible, 0)
#define DT_N_S_soc_S_timer_40009000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timer_40009000, compatible, 0)
#define DT_N_S_soc_S_timer_40009000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timer_40009000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_40009000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timer_40009000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_40009000_P_compatible_LEN 1
#define DT_N_S_soc_S_timer_40009000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timer_40009000_P_reg {1073778688 /* 0x40009000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_timer_40009000_P_reg_IDX_0 1073778688
#define DT_N_S_soc_S_timer_40009000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_40009000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_timer_40009000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timer_40009000_P_reg_EXISTS 1
#define DT_N_S_soc_S_timer_40009000_P_interrupts {9 /* 0x9 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_timer_40009000_P_interrupts_IDX_0 9
#define DT_N_S_soc_S_timer_40009000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_40009000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_timer_40009000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timer_40009000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timer_40009000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timer_40009000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timer_40009000_P_cc_num 4
#define DT_N_S_soc_S_timer_40009000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_timer_40009000_P_max_bit_width 32
#define DT_N_S_soc_S_timer_40009000_P_max_bit_width_EXISTS 1
#define DT_N_S_soc_S_timer_40009000_P_max_frequency 16000000
#define DT_N_S_soc_S_timer_40009000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_timer_40009000_P_prescaler 0
#define DT_N_S_soc_S_timer_40009000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_timer_40009000_P_zli 0
#define DT_N_S_soc_S_timer_40009000_P_zli_EXISTS 1

/*
 * Devicetree node: /sw-pwm
 *
 * Node identifier: DT_N_S_sw_pwm
 *
 * Binding (compatible = nordic,nrf-sw-pwm):
 *   $ZEPHYR_BASE/dts/bindings/pwm/nordic,nrf-sw-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_sw_pwm_PATH "/sw-pwm"

/* Node's name with unit-address: */
#define DT_N_S_sw_pwm_FULL_NAME "sw-pwm"

/* Node parent (/) identifier: */
#define DT_N_S_sw_pwm_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_sw_pwm_CHILD_IDX 5

/* Helper macros for child nodes of this node. */
#define DT_N_S_sw_pwm_CHILD_NUM 0
#define DT_N_S_sw_pwm_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_sw_pwm_FOREACH_CHILD(fn) 
#define DT_N_S_sw_pwm_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_sw_pwm_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_sw_pwm_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_sw_pwm_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_sw_pwm_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_sw_pwm_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_sw_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_sw_pwm_ORD 9
#define DT_N_S_sw_pwm_ORD_STR_SORTABLE 00009

/* Ordinals for what this node depends on directly: */
#define DT_N_S_sw_pwm_REQUIRES_ORDS \
	0, /* / */ \
	8, /* /soc/timer@40009000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_sw_pwm_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_sw_pwm_EXISTS 1
#define DT_N_INST_0_nordic_nrf_sw_pwm DT_N_S_sw_pwm
#define DT_N_NODELABEL_sw_pwm         DT_N_S_sw_pwm

/* Macros for properties that are special in the specification: */
#define DT_N_S_sw_pwm_REG_NUM 0
#define DT_N_S_sw_pwm_RANGES_NUM 0
#define DT_N_S_sw_pwm_FOREACH_RANGE(fn) 
#define DT_N_S_sw_pwm_IRQ_NUM 0
#define DT_N_S_sw_pwm_IRQ_LEVEL 0
#define DT_N_S_sw_pwm_COMPAT_MATCHES_nordic_nrf_sw_pwm 1
#define DT_N_S_sw_pwm_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_sw_pwm_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_sw_pwm_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_sw_pwm_COMPAT_MODEL_IDX_0 "nrf-sw-pwm"
#define DT_N_S_sw_pwm_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_sw_pwm_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_sw_pwm_P_wakeup_source 0
#define DT_N_S_sw_pwm_P_wakeup_source_EXISTS 1
#define DT_N_S_sw_pwm_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_sw_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_sw_pwm_P_status "disabled"
#define DT_N_S_sw_pwm_P_status_STRING_UNQUOTED disabled
#define DT_N_S_sw_pwm_P_status_STRING_TOKEN disabled
#define DT_N_S_sw_pwm_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_sw_pwm_P_status_IDX_0 "disabled"
#define DT_N_S_sw_pwm_P_status_IDX_0_EXISTS 1
#define DT_N_S_sw_pwm_P_status_ENUM_IDX 2
#define DT_N_S_sw_pwm_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_sw_pwm_P_status_ENUM_TOKEN disabled
#define DT_N_S_sw_pwm_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_sw_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_sw_pwm, status, 0)
#define DT_N_S_sw_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_sw_pwm, status, 0)
#define DT_N_S_sw_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_sw_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_sw_pwm_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_sw_pwm, status, 0, __VA_ARGS__)
#define DT_N_S_sw_pwm_P_status_LEN 1
#define DT_N_S_sw_pwm_P_status_EXISTS 1
#define DT_N_S_sw_pwm_P_compatible {"nordic,nrf-sw-pwm"}
#define DT_N_S_sw_pwm_P_compatible_IDX_0 "nordic,nrf-sw-pwm"
#define DT_N_S_sw_pwm_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-sw-pwm
#define DT_N_S_sw_pwm_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_sw_pwm
#define DT_N_S_sw_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SW_PWM
#define DT_N_S_sw_pwm_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_sw_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_sw_pwm, compatible, 0)
#define DT_N_S_sw_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_sw_pwm, compatible, 0)
#define DT_N_S_sw_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_sw_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_sw_pwm_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_sw_pwm, compatible, 0, __VA_ARGS__)
#define DT_N_S_sw_pwm_P_compatible_LEN 1
#define DT_N_S_sw_pwm_P_compatible_EXISTS 1
#define DT_N_S_sw_pwm_P_zephyr_deferred_init 0
#define DT_N_S_sw_pwm_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_sw_pwm_P_generator DT_N_S_soc_S_timer_40009000
#define DT_N_S_sw_pwm_P_generator_IDX_0 DT_N_S_soc_S_timer_40009000
#define DT_N_S_sw_pwm_P_generator_IDX_0_PH DT_N_S_soc_S_timer_40009000
#define DT_N_S_sw_pwm_P_generator_IDX_0_EXISTS 1
#define DT_N_S_sw_pwm_P_generator_FOREACH_PROP_ELEM(fn) fn(DT_N_S_sw_pwm, generator, 0)
#define DT_N_S_sw_pwm_P_generator_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_sw_pwm, generator, 0)
#define DT_N_S_sw_pwm_P_generator_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_sw_pwm, generator, 0, __VA_ARGS__)
#define DT_N_S_sw_pwm_P_generator_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_sw_pwm, generator, 0, __VA_ARGS__)
#define DT_N_S_sw_pwm_P_generator_LEN 1
#define DT_N_S_sw_pwm_P_generator_EXISTS 1
#define DT_N_S_sw_pwm_P_clock_prescaler 0
#define DT_N_S_sw_pwm_P_clock_prescaler_EXISTS 1

/*
 * Devicetree node: /soc/gpiote@40006000
 *
 * Node identifier: DT_N_S_soc_S_gpiote_40006000
 *
 * Binding (compatible = nordic,nrf-gpiote):
 *   $ZEPHYR_BASE/dts/bindings/gpio/nordic,nrf-gpiote.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_gpiote_40006000_PATH "/soc/gpiote@40006000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_gpiote_40006000_FULL_NAME "gpiote@40006000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_gpiote_40006000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_gpiote_40006000_CHILD_IDX 14

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_gpiote_40006000_CHILD_NUM 0
#define DT_N_S_soc_S_gpiote_40006000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_gpiote_40006000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_gpiote_40006000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_gpiote_40006000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_gpiote_40006000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_gpiote_40006000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_gpiote_40006000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_gpiote_40006000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_gpiote_40006000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_gpiote_40006000_ORD 10
#define DT_N_S_soc_S_gpiote_40006000_ORD_STR_SORTABLE 00010

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_gpiote_40006000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_gpiote_40006000_SUPPORTS_ORDS \
	11, /* /soc/gpio@50000000 */ \
	105, /* /soc/gpio@50000300 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_gpiote_40006000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_gpiote DT_N_S_soc_S_gpiote_40006000
#define DT_N_NODELABEL_gpiote         DT_N_S_soc_S_gpiote_40006000
#define DT_N_NODELABEL_gpiote0        DT_N_S_soc_S_gpiote_40006000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_gpiote_40006000_REG_NUM 1
#define DT_N_S_soc_S_gpiote_40006000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_40006000_REG_IDX_0_VAL_ADDRESS 1073766400 /* 0x40006000 */
#define DT_N_S_soc_S_gpiote_40006000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_gpiote_40006000_RANGES_NUM 0
#define DT_N_S_soc_S_gpiote_40006000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_gpiote_40006000_IRQ_NUM 1
#define DT_N_S_soc_S_gpiote_40006000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_40006000_IRQ_IDX_0_VAL_irq 6
#define DT_N_S_soc_S_gpiote_40006000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_gpiote_40006000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_40006000_IRQ_IDX_0_VAL_priority 5
#define DT_N_S_soc_S_gpiote_40006000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_gpiote_40006000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_gpiote_40006000_IRQ_LEVEL 1
#define DT_N_S_soc_S_gpiote_40006000_COMPAT_MATCHES_nordic_nrf_gpiote 1
#define DT_N_S_soc_S_gpiote_40006000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_40006000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_gpiote_40006000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_40006000_COMPAT_MODEL_IDX_0 "nrf-gpiote"
#define DT_N_S_soc_S_gpiote_40006000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_gpiote_40006000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_gpiote_40006000_P_wakeup_source 0
#define DT_N_S_soc_S_gpiote_40006000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_gpiote_40006000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_gpiote_40006000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_gpiote_40006000_P_status "okay"
#define DT_N_S_soc_S_gpiote_40006000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_gpiote_40006000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_gpiote_40006000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_gpiote_40006000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_gpiote_40006000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_40006000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_gpiote_40006000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_gpiote_40006000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_gpiote_40006000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_gpiote_40006000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpiote_40006000, status, 0)
#define DT_N_S_soc_S_gpiote_40006000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpiote_40006000, status, 0)
#define DT_N_S_soc_S_gpiote_40006000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpiote_40006000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpiote_40006000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpiote_40006000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpiote_40006000_P_status_LEN 1
#define DT_N_S_soc_S_gpiote_40006000_P_status_EXISTS 1
#define DT_N_S_soc_S_gpiote_40006000_P_compatible {"nordic,nrf-gpiote"}
#define DT_N_S_soc_S_gpiote_40006000_P_compatible_IDX_0 "nordic,nrf-gpiote"
#define DT_N_S_soc_S_gpiote_40006000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpiote
#define DT_N_S_soc_S_gpiote_40006000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpiote
#define DT_N_S_soc_S_gpiote_40006000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPIOTE
#define DT_N_S_soc_S_gpiote_40006000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_40006000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpiote_40006000, compatible, 0)
#define DT_N_S_soc_S_gpiote_40006000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpiote_40006000, compatible, 0)
#define DT_N_S_soc_S_gpiote_40006000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpiote_40006000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpiote_40006000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpiote_40006000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpiote_40006000_P_compatible_LEN 1
#define DT_N_S_soc_S_gpiote_40006000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_gpiote_40006000_P_reg {1073766400 /* 0x40006000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_gpiote_40006000_P_reg_IDX_0 1073766400
#define DT_N_S_soc_S_gpiote_40006000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_40006000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_gpiote_40006000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_gpiote_40006000_P_reg_EXISTS 1
#define DT_N_S_soc_S_gpiote_40006000_P_interrupts {6 /* 0x6 */, 5 /* 0x5 */}
#define DT_N_S_soc_S_gpiote_40006000_P_interrupts_IDX_0 6
#define DT_N_S_soc_S_gpiote_40006000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_40006000_P_interrupts_IDX_1 5
#define DT_N_S_soc_S_gpiote_40006000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_gpiote_40006000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_gpiote_40006000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_gpiote_40006000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_gpiote_40006000_P_instance 0
#define DT_N_S_soc_S_gpiote_40006000_P_instance_EXISTS 1

/*
 * Devicetree node: /soc/gpio@50000000
 *
 * Node identifier: DT_N_S_soc_S_gpio_50000000
 *
 * Binding (compatible = nordic,nrf-gpio):
 *   $ZEPHYR_BASE/dts/bindings/gpio/nordic,nrf-gpio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_gpio_50000000_PATH "/soc/gpio@50000000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_gpio_50000000_FULL_NAME "gpio@50000000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_gpio_50000000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_gpio_50000000_CHILD_IDX 52

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_gpio_50000000_CHILD_NUM 0
#define DT_N_S_soc_S_gpio_50000000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_gpio_50000000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_gpio_50000000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_gpio_50000000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_gpio_50000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_gpio_50000000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_gpio_50000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_gpio_50000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_gpio_50000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_gpio_50000000_ORD 11
#define DT_N_S_soc_S_gpio_50000000_ORD_STR_SORTABLE 00011

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_gpio_50000000_REQUIRES_ORDS \
	6, /* /soc */ \
	10, /* /soc/gpiote@40006000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_gpio_50000000_SUPPORTS_ORDS \
	12, /* /buttons */ \
	13, /* /buttons/button_0 */ \
	14, /* /buttons/button_1 */ \
	15, /* /buttons/button_2 */ \
	16, /* /buttons/button_3 */ \
	20, /* /leds */ \
	21, /* /leds/led_0 */ \
	22, /* /leds/led_1 */ \
	23, /* /leds/led_2 */ \
	24, /* /leds/led_3 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_gpio_50000000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_gpio DT_N_S_soc_S_gpio_50000000
#define DT_N_NODELABEL_gpio0        DT_N_S_soc_S_gpio_50000000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_gpio_50000000_REG_NUM 2
#define DT_N_S_soc_S_gpio_50000000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_REG_IDX_0_VAL_ADDRESS 1342177280 /* 0x50000000 */
#define DT_N_S_soc_S_gpio_50000000_REG_IDX_0_VAL_SIZE 512 /* 0x200 */
#define DT_N_S_soc_S_gpio_50000000_REG_IDX_1_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_REG_IDX_1_VAL_ADDRESS 1342178560 /* 0x50000500 */
#define DT_N_S_soc_S_gpio_50000000_REG_IDX_1_VAL_SIZE 768 /* 0x300 */
#define DT_N_S_soc_S_gpio_50000000_RANGES_NUM 0
#define DT_N_S_soc_S_gpio_50000000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_gpio_50000000_IRQ_NUM 0
#define DT_N_S_soc_S_gpio_50000000_IRQ_LEVEL 0
#define DT_N_S_soc_S_gpio_50000000_COMPAT_MATCHES_nordic_nrf_gpio 1
#define DT_N_S_soc_S_gpio_50000000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_gpio_50000000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_COMPAT_MODEL_IDX_0 "nrf-gpio"
#define DT_N_S_soc_S_gpio_50000000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_gpio_50000000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_gpio_50000000_P_gpio_controller 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_ngpios 32
#define DT_N_S_soc_S_gpio_50000000_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_reserved_ranges {0 /* 0x0 */, 2 /* 0x2 */, 6 /* 0x6 */, 1 /* 0x1 */, 8 /* 0x8 */, 3 /* 0x3 */, 17 /* 0x11 */, 7 /* 0x7 */}
#define DT_N_S_soc_S_gpio_50000000_P_gpio_reserved_ranges_IDX_0 0
#define DT_N_S_soc_S_gpio_50000000_P_gpio_reserved_ranges_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_reserved_ranges_IDX_1 2
#define DT_N_S_soc_S_gpio_50000000_P_gpio_reserved_ranges_IDX_1_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_reserved_ranges_IDX_2 6
#define DT_N_S_soc_S_gpio_50000000_P_gpio_reserved_ranges_IDX_2_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_reserved_ranges_IDX_3 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_reserved_ranges_IDX_3_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_reserved_ranges_IDX_4 8
#define DT_N_S_soc_S_gpio_50000000_P_gpio_reserved_ranges_IDX_4_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_reserved_ranges_IDX_5 3
#define DT_N_S_soc_S_gpio_50000000_P_gpio_reserved_ranges_IDX_5_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_reserved_ranges_IDX_6 17
#define DT_N_S_soc_S_gpio_50000000_P_gpio_reserved_ranges_IDX_6_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_reserved_ranges_IDX_7 7
#define DT_N_S_soc_S_gpio_50000000_P_gpio_reserved_ranges_IDX_7_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_reserved_ranges_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpio_50000000, gpio_reserved_ranges, 0) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_reserved_ranges, 1) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_reserved_ranges, 2) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_reserved_ranges, 3) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_reserved_ranges, 4) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_reserved_ranges, 5) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_reserved_ranges, 6) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_reserved_ranges, 7)
#define DT_N_S_soc_S_gpio_50000000_P_gpio_reserved_ranges_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpio_50000000, gpio_reserved_ranges, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_reserved_ranges, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_reserved_ranges, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_reserved_ranges, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_reserved_ranges, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_reserved_ranges, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_reserved_ranges, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_reserved_ranges, 7)
#define DT_N_S_soc_S_gpio_50000000_P_gpio_reserved_ranges_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpio_50000000, gpio_reserved_ranges, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_reserved_ranges, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_reserved_ranges, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_reserved_ranges, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_reserved_ranges, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_reserved_ranges, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_reserved_ranges, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_reserved_ranges, 7, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_50000000_P_gpio_reserved_ranges_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpio_50000000, gpio_reserved_ranges, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_reserved_ranges, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_reserved_ranges, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_reserved_ranges, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_reserved_ranges, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_reserved_ranges, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_reserved_ranges, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_reserved_ranges, 7, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_50000000_P_gpio_reserved_ranges_LEN 8
#define DT_N_S_soc_S_gpio_50000000_P_gpio_reserved_ranges_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names {"XL1", "XL2", "AREF", "A0", "A1", "RTS", "TXD", "CTS", "RXD", "NFC1", "NFC2", "BUTTON1", "BUTTON2", "LED1", "LED2", "LED3", "LED4", "QSPI CS", "RESET", "QSPI CLK", "QSPI DIO0", "QSPI DIO1", "QSPI DIO2", "QSPI DIO3", "BUTTON3", "BUTTON4", "SDA", "SCL", "A2", "A3", "A4", "A5"}
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_0 "XL1"
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_0_STRING_UNQUOTED XL1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_0_STRING_TOKEN XL1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_0_STRING_UPPER_TOKEN XL1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_1 "XL2"
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_1_STRING_UNQUOTED XL2
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_1_STRING_TOKEN XL2
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_1_STRING_UPPER_TOKEN XL2
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_2 "AREF"
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_2_STRING_UNQUOTED AREF
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_2_STRING_TOKEN AREF
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_2_STRING_UPPER_TOKEN AREF
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_2_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_3 "A0"
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_3_STRING_UNQUOTED A0
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_3_STRING_TOKEN A0
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_3_STRING_UPPER_TOKEN A0
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_3_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_4 "A1"
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_4_STRING_UNQUOTED A1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_4_STRING_TOKEN A1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_4_STRING_UPPER_TOKEN A1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_4_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_5 "RTS"
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_5_STRING_UNQUOTED RTS
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_5_STRING_TOKEN RTS
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_5_STRING_UPPER_TOKEN RTS
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_5_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_6 "TXD"
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_6_STRING_UNQUOTED TXD
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_6_STRING_TOKEN TXD
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_6_STRING_UPPER_TOKEN TXD
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_6_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_7 "CTS"
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_7_STRING_UNQUOTED CTS
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_7_STRING_TOKEN CTS
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_7_STRING_UPPER_TOKEN CTS
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_7_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_8 "RXD"
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_8_STRING_UNQUOTED RXD
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_8_STRING_TOKEN RXD
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_8_STRING_UPPER_TOKEN RXD
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_8_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_9 "NFC1"
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_9_STRING_UNQUOTED NFC1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_9_STRING_TOKEN NFC1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_9_STRING_UPPER_TOKEN NFC1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_9_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_10 "NFC2"
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_10_STRING_UNQUOTED NFC2
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_10_STRING_TOKEN NFC2
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_10_STRING_UPPER_TOKEN NFC2
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_10_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_11 "BUTTON1"
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_11_STRING_UNQUOTED BUTTON1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_11_STRING_TOKEN BUTTON1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_11_STRING_UPPER_TOKEN BUTTON1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_11_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_12 "BUTTON2"
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_12_STRING_UNQUOTED BUTTON2
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_12_STRING_TOKEN BUTTON2
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_12_STRING_UPPER_TOKEN BUTTON2
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_12_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_13 "LED1"
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_13_STRING_UNQUOTED LED1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_13_STRING_TOKEN LED1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_13_STRING_UPPER_TOKEN LED1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_13_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_14 "LED2"
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_14_STRING_UNQUOTED LED2
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_14_STRING_TOKEN LED2
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_14_STRING_UPPER_TOKEN LED2
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_14_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_15 "LED3"
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_15_STRING_UNQUOTED LED3
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_15_STRING_TOKEN LED3
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_15_STRING_UPPER_TOKEN LED3
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_15_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_16 "LED4"
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_16_STRING_UNQUOTED LED4
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_16_STRING_TOKEN LED4
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_16_STRING_UPPER_TOKEN LED4
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_16_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_17 "QSPI CS"
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_17_STRING_UNQUOTED QSPI CS
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_17_STRING_TOKEN QSPI_CS
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_17_STRING_UPPER_TOKEN QSPI_CS
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_17_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_18 "RESET"
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_18_STRING_UNQUOTED RESET
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_18_STRING_TOKEN RESET
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_18_STRING_UPPER_TOKEN RESET
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_18_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_19 "QSPI CLK"
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_19_STRING_UNQUOTED QSPI CLK
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_19_STRING_TOKEN QSPI_CLK
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_19_STRING_UPPER_TOKEN QSPI_CLK
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_19_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_20 "QSPI DIO0"
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_20_STRING_UNQUOTED QSPI DIO0
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_20_STRING_TOKEN QSPI_DIO0
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_20_STRING_UPPER_TOKEN QSPI_DIO0
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_20_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_21 "QSPI DIO1"
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_21_STRING_UNQUOTED QSPI DIO1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_21_STRING_TOKEN QSPI_DIO1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_21_STRING_UPPER_TOKEN QSPI_DIO1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_21_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_22 "QSPI DIO2"
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_22_STRING_UNQUOTED QSPI DIO2
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_22_STRING_TOKEN QSPI_DIO2
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_22_STRING_UPPER_TOKEN QSPI_DIO2
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_22_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_23 "QSPI DIO3"
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_23_STRING_UNQUOTED QSPI DIO3
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_23_STRING_TOKEN QSPI_DIO3
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_23_STRING_UPPER_TOKEN QSPI_DIO3
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_23_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_24 "BUTTON3"
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_24_STRING_UNQUOTED BUTTON3
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_24_STRING_TOKEN BUTTON3
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_24_STRING_UPPER_TOKEN BUTTON3
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_24_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_25 "BUTTON4"
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_25_STRING_UNQUOTED BUTTON4
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_25_STRING_TOKEN BUTTON4
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_25_STRING_UPPER_TOKEN BUTTON4
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_25_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_26 "SDA"
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_26_STRING_UNQUOTED SDA
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_26_STRING_TOKEN SDA
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_26_STRING_UPPER_TOKEN SDA
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_26_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_27 "SCL"
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_27_STRING_UNQUOTED SCL
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_27_STRING_TOKEN SCL
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_27_STRING_UPPER_TOKEN SCL
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_27_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_28 "A2"
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_28_STRING_UNQUOTED A2
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_28_STRING_TOKEN A2
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_28_STRING_UPPER_TOKEN A2
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_28_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_29 "A3"
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_29_STRING_UNQUOTED A3
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_29_STRING_TOKEN A3
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_29_STRING_UPPER_TOKEN A3
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_29_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_30 "A4"
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_30_STRING_UNQUOTED A4
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_30_STRING_TOKEN A4
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_30_STRING_UPPER_TOKEN A4
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_30_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_31 "A5"
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_31_STRING_UNQUOTED A5
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_31_STRING_TOKEN A5
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_31_STRING_UPPER_TOKEN A5
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_IDX_31_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 0) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 1) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 2) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 3) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 4) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 5) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 6) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 7) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 8) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 9) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 10) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 11) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 12) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 13) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 14) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 15) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 16) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 17) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 18) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 19) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 20) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 21) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 22) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 23) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 24) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 25) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 26) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 27) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 28) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 29) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 30) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 31)
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 7) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 8) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 9) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 10) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 11) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 12) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 13) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 14) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 15) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 16) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 17) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 18) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 19) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 20) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 21) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 22) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 23) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 24) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 25) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 26) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 27) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 28) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 29) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 30) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 31)
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 7, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 8, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 9, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 10, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 11, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 12, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 13, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 14, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 15, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 16, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 17, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 18, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 19, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 20, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 21, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 22, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 23, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 24, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 25, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 26, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 27, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 28, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 29, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 30, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 31, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 16, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 17, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 18, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 19, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 20, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 21, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 22, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 23, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 24, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 25, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 26, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 27, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 28, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 29, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 30, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000000, gpio_line_names, 31, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_LEN 32
#define DT_N_S_soc_S_gpio_50000000_P_gpio_line_names_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_wakeup_source 0
#define DT_N_S_soc_S_gpio_50000000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_gpio_50000000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_status "okay"
#define DT_N_S_soc_S_gpio_50000000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_gpio_50000000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_gpio_50000000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_gpio_50000000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_gpio_50000000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_gpio_50000000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_gpio_50000000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_gpio_50000000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpio_50000000, status, 0)
#define DT_N_S_soc_S_gpio_50000000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpio_50000000, status, 0)
#define DT_N_S_soc_S_gpio_50000000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpio_50000000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_50000000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpio_50000000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_50000000_P_status_LEN 1
#define DT_N_S_soc_S_gpio_50000000_P_status_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_compatible {"nordic,nrf-gpio"}
#define DT_N_S_soc_S_gpio_50000000_P_compatible_IDX_0 "nordic,nrf-gpio"
#define DT_N_S_soc_S_gpio_50000000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpio
#define DT_N_S_soc_S_gpio_50000000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpio
#define DT_N_S_soc_S_gpio_50000000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPIO
#define DT_N_S_soc_S_gpio_50000000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpio_50000000, compatible, 0)
#define DT_N_S_soc_S_gpio_50000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpio_50000000, compatible, 0)
#define DT_N_S_soc_S_gpio_50000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpio_50000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_50000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpio_50000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_50000000_P_compatible_LEN 1
#define DT_N_S_soc_S_gpio_50000000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_reg {1342177280 /* 0x50000000 */, 512 /* 0x200 */, 1342178560 /* 0x50000500 */, 768 /* 0x300 */}
#define DT_N_S_soc_S_gpio_50000000_P_reg_IDX_0 1342177280
#define DT_N_S_soc_S_gpio_50000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_reg_IDX_1 512
#define DT_N_S_soc_S_gpio_50000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_reg_IDX_2 1342178560
#define DT_N_S_soc_S_gpio_50000000_P_reg_IDX_2_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_reg_IDX_3 768
#define DT_N_S_soc_S_gpio_50000000_P_reg_IDX_3_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_reg_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_gpio_50000000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpiote_instance DT_N_S_soc_S_gpiote_40006000
#define DT_N_S_soc_S_gpio_50000000_P_gpiote_instance_IDX_0 DT_N_S_soc_S_gpiote_40006000
#define DT_N_S_soc_S_gpio_50000000_P_gpiote_instance_IDX_0_PH DT_N_S_soc_S_gpiote_40006000
#define DT_N_S_soc_S_gpio_50000000_P_gpiote_instance_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_gpiote_instance_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpio_50000000, gpiote_instance, 0)
#define DT_N_S_soc_S_gpio_50000000_P_gpiote_instance_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpio_50000000, gpiote_instance, 0)
#define DT_N_S_soc_S_gpio_50000000_P_gpiote_instance_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpio_50000000, gpiote_instance, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_50000000_P_gpiote_instance_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpio_50000000, gpiote_instance, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_50000000_P_gpiote_instance_LEN 1
#define DT_N_S_soc_S_gpio_50000000_P_gpiote_instance_EXISTS 1
#define DT_N_S_soc_S_gpio_50000000_P_port 0
#define DT_N_S_soc_S_gpio_50000000_P_port_EXISTS 1

/*
 * Devicetree node: /buttons
 *
 * Node identifier: DT_N_S_buttons
 *
 * Binding (compatible = gpio-keys):
 *   $ZEPHYR_BASE/dts/bindings/input/gpio-keys.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_buttons_PATH "/buttons"

/* Node's name with unit-address: */
#define DT_N_S_buttons_FULL_NAME "buttons"

/* Node parent (/) identifier: */
#define DT_N_S_buttons_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_buttons_CHILD_IDX 9

/* Helper macros for child nodes of this node. */
#define DT_N_S_buttons_CHILD_NUM 4
#define DT_N_S_buttons_CHILD_NUM_STATUS_OKAY 4
#define DT_N_S_buttons_FOREACH_CHILD(fn) fn(DT_N_S_buttons_S_button_0) fn(DT_N_S_buttons_S_button_1) fn(DT_N_S_buttons_S_button_2) fn(DT_N_S_buttons_S_button_3)
#define DT_N_S_buttons_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_buttons_S_button_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_3)
#define DT_N_S_buttons_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_0, __VA_ARGS__) fn(DT_N_S_buttons_S_button_1, __VA_ARGS__) fn(DT_N_S_buttons_S_button_2, __VA_ARGS__) fn(DT_N_S_buttons_S_button_3, __VA_ARGS__)
#define DT_N_S_buttons_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_3, __VA_ARGS__)
#define DT_N_S_buttons_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_buttons_S_button_0) fn(DT_N_S_buttons_S_button_1) fn(DT_N_S_buttons_S_button_2) fn(DT_N_S_buttons_S_button_3)
#define DT_N_S_buttons_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_buttons_S_button_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_3)
#define DT_N_S_buttons_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_0, __VA_ARGS__) fn(DT_N_S_buttons_S_button_1, __VA_ARGS__) fn(DT_N_S_buttons_S_button_2, __VA_ARGS__) fn(DT_N_S_buttons_S_button_3, __VA_ARGS__)
#define DT_N_S_buttons_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_buttons_S_button_3, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_buttons_ORD 12
#define DT_N_S_buttons_ORD_STR_SORTABLE 00012

/* Ordinals for what this node depends on directly: */
#define DT_N_S_buttons_REQUIRES_ORDS \
	0, /* / */ \
	11, /* /soc/gpio@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_buttons_SUPPORTS_ORDS \
	13, /* /buttons/button_0 */ \
	14, /* /buttons/button_1 */ \
	15, /* /buttons/button_2 */ \
	16, /* /buttons/button_3 */

/* Existence and alternate IDs: */
#define DT_N_S_buttons_EXISTS 1
#define DT_N_INST_0_gpio_keys DT_N_S_buttons

/* Macros for properties that are special in the specification: */
#define DT_N_S_buttons_REG_NUM 0
#define DT_N_S_buttons_RANGES_NUM 0
#define DT_N_S_buttons_FOREACH_RANGE(fn) 
#define DT_N_S_buttons_IRQ_NUM 0
#define DT_N_S_buttons_IRQ_LEVEL 0
#define DT_N_S_buttons_COMPAT_MATCHES_gpio_keys 1
#define DT_N_S_buttons_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_buttons_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_buttons_P_wakeup_source 0
#define DT_N_S_buttons_P_wakeup_source_EXISTS 1
#define DT_N_S_buttons_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_buttons_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_buttons_P_compatible {"gpio-keys"}
#define DT_N_S_buttons_P_compatible_IDX_0 "gpio-keys"
#define DT_N_S_buttons_P_compatible_IDX_0_STRING_UNQUOTED gpio-keys
#define DT_N_S_buttons_P_compatible_IDX_0_STRING_TOKEN gpio_keys
#define DT_N_S_buttons_P_compatible_IDX_0_STRING_UPPER_TOKEN GPIO_KEYS
#define DT_N_S_buttons_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_buttons_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons, compatible, 0)
#define DT_N_S_buttons_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons, compatible, 0)
#define DT_N_S_buttons_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons, compatible, 0, __VA_ARGS__)
#define DT_N_S_buttons_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons, compatible, 0, __VA_ARGS__)
#define DT_N_S_buttons_P_compatible_LEN 1
#define DT_N_S_buttons_P_compatible_EXISTS 1
#define DT_N_S_buttons_P_zephyr_deferred_init 0
#define DT_N_S_buttons_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_buttons_P_debounce_interval_ms 30
#define DT_N_S_buttons_P_debounce_interval_ms_EXISTS 1
#define DT_N_S_buttons_P_polling_mode 0
#define DT_N_S_buttons_P_polling_mode_EXISTS 1

/*
 * Devicetree node: /buttons/button_0
 *
 * Node identifier: DT_N_S_buttons_S_button_0
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_buttons_S_button_0_PATH "/buttons/button_0"

/* Node's name with unit-address: */
#define DT_N_S_buttons_S_button_0_FULL_NAME "button_0"

/* Node parent (/buttons) identifier: */
#define DT_N_S_buttons_S_button_0_PARENT DT_N_S_buttons

/* Node's index in its parent's list of children: */
#define DT_N_S_buttons_S_button_0_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_buttons_S_button_0_CHILD_NUM 0
#define DT_N_S_buttons_S_button_0_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_buttons_S_button_0_FOREACH_CHILD(fn) 
#define DT_N_S_buttons_S_button_0_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_buttons_S_button_0_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_buttons_S_button_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_buttons_S_button_0_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_buttons_S_button_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_buttons_S_button_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_buttons_S_button_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_buttons_S_button_0_ORD 13
#define DT_N_S_buttons_S_button_0_ORD_STR_SORTABLE 00013

/* Ordinals for what this node depends on directly: */
#define DT_N_S_buttons_S_button_0_REQUIRES_ORDS \
	11, /* /soc/gpio@50000000 */ \
	12, /* /buttons */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_buttons_S_button_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_buttons_S_button_0_EXISTS 1
#define DT_N_ALIAS_sw0             DT_N_S_buttons_S_button_0
#define DT_N_ALIAS_mcuboot_button0 DT_N_S_buttons_S_button_0
#define DT_N_NODELABEL_button0     DT_N_S_buttons_S_button_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_buttons_S_button_0_REG_NUM 0
#define DT_N_S_buttons_S_button_0_RANGES_NUM 0
#define DT_N_S_buttons_S_button_0_FOREACH_RANGE(fn) 
#define DT_N_S_buttons_S_button_0_IRQ_NUM 0
#define DT_N_S_buttons_S_button_0_IRQ_LEVEL 0
#define DT_N_S_buttons_S_button_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_buttons_S_button_0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_PH DT_N_S_soc_S_gpio_50000000
#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_pin 11
#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_flags 17
#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_buttons_S_button_0_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_0, gpios, 0)
#define DT_N_S_buttons_S_button_0_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_0, gpios, 0)
#define DT_N_S_buttons_S_button_0_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_0, gpios, 0, __VA_ARGS__)
#define DT_N_S_buttons_S_button_0_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_0, gpios, 0, __VA_ARGS__)
#define DT_N_S_buttons_S_button_0_P_gpios_LEN 1
#define DT_N_S_buttons_S_button_0_P_gpios_EXISTS 1
#define DT_N_S_buttons_S_button_0_P_label "Push button switch 0"
#define DT_N_S_buttons_S_button_0_P_label_STRING_UNQUOTED Push button switch 0
#define DT_N_S_buttons_S_button_0_P_label_STRING_TOKEN Push_button_switch_0
#define DT_N_S_buttons_S_button_0_P_label_STRING_UPPER_TOKEN PUSH_BUTTON_SWITCH_0
#define DT_N_S_buttons_S_button_0_P_label_IDX_0 "Push button switch 0"
#define DT_N_S_buttons_S_button_0_P_label_IDX_0_EXISTS 1
#define DT_N_S_buttons_S_button_0_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_0, label, 0)
#define DT_N_S_buttons_S_button_0_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_0, label, 0)
#define DT_N_S_buttons_S_button_0_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_0, label, 0, __VA_ARGS__)
#define DT_N_S_buttons_S_button_0_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_0, label, 0, __VA_ARGS__)
#define DT_N_S_buttons_S_button_0_P_label_LEN 1
#define DT_N_S_buttons_S_button_0_P_label_EXISTS 1
#define DT_N_S_buttons_S_button_0_P_zephyr_code 11
#define DT_N_S_buttons_S_button_0_P_zephyr_code_EXISTS 1

/*
 * Devicetree node: /buttons/button_1
 *
 * Node identifier: DT_N_S_buttons_S_button_1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_buttons_S_button_1_PATH "/buttons/button_1"

/* Node's name with unit-address: */
#define DT_N_S_buttons_S_button_1_FULL_NAME "button_1"

/* Node parent (/buttons) identifier: */
#define DT_N_S_buttons_S_button_1_PARENT DT_N_S_buttons

/* Node's index in its parent's list of children: */
#define DT_N_S_buttons_S_button_1_CHILD_IDX 1

/* Helper macros for child nodes of this node. */
#define DT_N_S_buttons_S_button_1_CHILD_NUM 0
#define DT_N_S_buttons_S_button_1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_buttons_S_button_1_FOREACH_CHILD(fn) 
#define DT_N_S_buttons_S_button_1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_buttons_S_button_1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_buttons_S_button_1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_buttons_S_button_1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_buttons_S_button_1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_buttons_S_button_1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_buttons_S_button_1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_buttons_S_button_1_ORD 14
#define DT_N_S_buttons_S_button_1_ORD_STR_SORTABLE 00014

/* Ordinals for what this node depends on directly: */
#define DT_N_S_buttons_S_button_1_REQUIRES_ORDS \
	11, /* /soc/gpio@50000000 */ \
	12, /* /buttons */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_buttons_S_button_1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_buttons_S_button_1_EXISTS 1
#define DT_N_ALIAS_sw1         DT_N_S_buttons_S_button_1
#define DT_N_NODELABEL_button1 DT_N_S_buttons_S_button_1

/* Macros for properties that are special in the specification: */
#define DT_N_S_buttons_S_button_1_REG_NUM 0
#define DT_N_S_buttons_S_button_1_RANGES_NUM 0
#define DT_N_S_buttons_S_button_1_FOREACH_RANGE(fn) 
#define DT_N_S_buttons_S_button_1_IRQ_NUM 0
#define DT_N_S_buttons_S_button_1_IRQ_LEVEL 0
#define DT_N_S_buttons_S_button_1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_buttons_S_button_1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_PH DT_N_S_soc_S_gpio_50000000
#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_pin 12
#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_flags 17
#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_buttons_S_button_1_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_1, gpios, 0)
#define DT_N_S_buttons_S_button_1_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_1, gpios, 0)
#define DT_N_S_buttons_S_button_1_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_1, gpios, 0, __VA_ARGS__)
#define DT_N_S_buttons_S_button_1_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_1, gpios, 0, __VA_ARGS__)
#define DT_N_S_buttons_S_button_1_P_gpios_LEN 1
#define DT_N_S_buttons_S_button_1_P_gpios_EXISTS 1
#define DT_N_S_buttons_S_button_1_P_label "Push button switch 1"
#define DT_N_S_buttons_S_button_1_P_label_STRING_UNQUOTED Push button switch 1
#define DT_N_S_buttons_S_button_1_P_label_STRING_TOKEN Push_button_switch_1
#define DT_N_S_buttons_S_button_1_P_label_STRING_UPPER_TOKEN PUSH_BUTTON_SWITCH_1
#define DT_N_S_buttons_S_button_1_P_label_IDX_0 "Push button switch 1"
#define DT_N_S_buttons_S_button_1_P_label_IDX_0_EXISTS 1
#define DT_N_S_buttons_S_button_1_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_1, label, 0)
#define DT_N_S_buttons_S_button_1_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_1, label, 0)
#define DT_N_S_buttons_S_button_1_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_1, label, 0, __VA_ARGS__)
#define DT_N_S_buttons_S_button_1_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_1, label, 0, __VA_ARGS__)
#define DT_N_S_buttons_S_button_1_P_label_LEN 1
#define DT_N_S_buttons_S_button_1_P_label_EXISTS 1
#define DT_N_S_buttons_S_button_1_P_zephyr_code 2
#define DT_N_S_buttons_S_button_1_P_zephyr_code_EXISTS 1

/*
 * Devicetree node: /buttons/button_2
 *
 * Node identifier: DT_N_S_buttons_S_button_2
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_buttons_S_button_2_PATH "/buttons/button_2"

/* Node's name with unit-address: */
#define DT_N_S_buttons_S_button_2_FULL_NAME "button_2"

/* Node parent (/buttons) identifier: */
#define DT_N_S_buttons_S_button_2_PARENT DT_N_S_buttons

/* Node's index in its parent's list of children: */
#define DT_N_S_buttons_S_button_2_CHILD_IDX 2

/* Helper macros for child nodes of this node. */
#define DT_N_S_buttons_S_button_2_CHILD_NUM 0
#define DT_N_S_buttons_S_button_2_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_buttons_S_button_2_FOREACH_CHILD(fn) 
#define DT_N_S_buttons_S_button_2_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_buttons_S_button_2_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_buttons_S_button_2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_buttons_S_button_2_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_buttons_S_button_2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_buttons_S_button_2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_buttons_S_button_2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_buttons_S_button_2_ORD 15
#define DT_N_S_buttons_S_button_2_ORD_STR_SORTABLE 00015

/* Ordinals for what this node depends on directly: */
#define DT_N_S_buttons_S_button_2_REQUIRES_ORDS \
	11, /* /soc/gpio@50000000 */ \
	12, /* /buttons */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_buttons_S_button_2_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_buttons_S_button_2_EXISTS 1
#define DT_N_ALIAS_sw2         DT_N_S_buttons_S_button_2
#define DT_N_NODELABEL_button2 DT_N_S_buttons_S_button_2

/* Macros for properties that are special in the specification: */
#define DT_N_S_buttons_S_button_2_REG_NUM 0
#define DT_N_S_buttons_S_button_2_RANGES_NUM 0
#define DT_N_S_buttons_S_button_2_FOREACH_RANGE(fn) 
#define DT_N_S_buttons_S_button_2_IRQ_NUM 0
#define DT_N_S_buttons_S_button_2_IRQ_LEVEL 0
#define DT_N_S_buttons_S_button_2_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_buttons_S_button_2_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_PH DT_N_S_soc_S_gpio_50000000
#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_pin 24
#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_flags 17
#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_buttons_S_button_2_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_2, gpios, 0)
#define DT_N_S_buttons_S_button_2_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_2, gpios, 0)
#define DT_N_S_buttons_S_button_2_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_2, gpios, 0, __VA_ARGS__)
#define DT_N_S_buttons_S_button_2_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_2, gpios, 0, __VA_ARGS__)
#define DT_N_S_buttons_S_button_2_P_gpios_LEN 1
#define DT_N_S_buttons_S_button_2_P_gpios_EXISTS 1
#define DT_N_S_buttons_S_button_2_P_label "Push button switch 2"
#define DT_N_S_buttons_S_button_2_P_label_STRING_UNQUOTED Push button switch 2
#define DT_N_S_buttons_S_button_2_P_label_STRING_TOKEN Push_button_switch_2
#define DT_N_S_buttons_S_button_2_P_label_STRING_UPPER_TOKEN PUSH_BUTTON_SWITCH_2
#define DT_N_S_buttons_S_button_2_P_label_IDX_0 "Push button switch 2"
#define DT_N_S_buttons_S_button_2_P_label_IDX_0_EXISTS 1
#define DT_N_S_buttons_S_button_2_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_2, label, 0)
#define DT_N_S_buttons_S_button_2_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_2, label, 0)
#define DT_N_S_buttons_S_button_2_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_2, label, 0, __VA_ARGS__)
#define DT_N_S_buttons_S_button_2_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_2, label, 0, __VA_ARGS__)
#define DT_N_S_buttons_S_button_2_P_label_LEN 1
#define DT_N_S_buttons_S_button_2_P_label_EXISTS 1
#define DT_N_S_buttons_S_button_2_P_zephyr_code 3
#define DT_N_S_buttons_S_button_2_P_zephyr_code_EXISTS 1

/*
 * Devicetree node: /buttons/button_3
 *
 * Node identifier: DT_N_S_buttons_S_button_3
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_buttons_S_button_3_PATH "/buttons/button_3"

/* Node's name with unit-address: */
#define DT_N_S_buttons_S_button_3_FULL_NAME "button_3"

/* Node parent (/buttons) identifier: */
#define DT_N_S_buttons_S_button_3_PARENT DT_N_S_buttons

/* Node's index in its parent's list of children: */
#define DT_N_S_buttons_S_button_3_CHILD_IDX 3

/* Helper macros for child nodes of this node. */
#define DT_N_S_buttons_S_button_3_CHILD_NUM 0
#define DT_N_S_buttons_S_button_3_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_buttons_S_button_3_FOREACH_CHILD(fn) 
#define DT_N_S_buttons_S_button_3_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_buttons_S_button_3_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_buttons_S_button_3_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_buttons_S_button_3_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_buttons_S_button_3_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_buttons_S_button_3_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_buttons_S_button_3_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_buttons_S_button_3_ORD 16
#define DT_N_S_buttons_S_button_3_ORD_STR_SORTABLE 00016

/* Ordinals for what this node depends on directly: */
#define DT_N_S_buttons_S_button_3_REQUIRES_ORDS \
	11, /* /soc/gpio@50000000 */ \
	12, /* /buttons */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_buttons_S_button_3_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_buttons_S_button_3_EXISTS 1
#define DT_N_ALIAS_sw3         DT_N_S_buttons_S_button_3
#define DT_N_NODELABEL_button3 DT_N_S_buttons_S_button_3

/* Macros for properties that are special in the specification: */
#define DT_N_S_buttons_S_button_3_REG_NUM 0
#define DT_N_S_buttons_S_button_3_RANGES_NUM 0
#define DT_N_S_buttons_S_button_3_FOREACH_RANGE(fn) 
#define DT_N_S_buttons_S_button_3_IRQ_NUM 0
#define DT_N_S_buttons_S_button_3_IRQ_LEVEL 0
#define DT_N_S_buttons_S_button_3_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_buttons_S_button_3_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_PH DT_N_S_soc_S_gpio_50000000
#define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_VAL_pin 25
#define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_VAL_flags 17
#define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_buttons_S_button_3_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_3, gpios, 0)
#define DT_N_S_buttons_S_button_3_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_3, gpios, 0)
#define DT_N_S_buttons_S_button_3_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_3, gpios, 0, __VA_ARGS__)
#define DT_N_S_buttons_S_button_3_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_3, gpios, 0, __VA_ARGS__)
#define DT_N_S_buttons_S_button_3_P_gpios_LEN 1
#define DT_N_S_buttons_S_button_3_P_gpios_EXISTS 1
#define DT_N_S_buttons_S_button_3_P_label "Push button switch 3"
#define DT_N_S_buttons_S_button_3_P_label_STRING_UNQUOTED Push button switch 3
#define DT_N_S_buttons_S_button_3_P_label_STRING_TOKEN Push_button_switch_3
#define DT_N_S_buttons_S_button_3_P_label_STRING_UPPER_TOKEN PUSH_BUTTON_SWITCH_3
#define DT_N_S_buttons_S_button_3_P_label_IDX_0 "Push button switch 3"
#define DT_N_S_buttons_S_button_3_P_label_IDX_0_EXISTS 1
#define DT_N_S_buttons_S_button_3_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_buttons_S_button_3, label, 0)
#define DT_N_S_buttons_S_button_3_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_buttons_S_button_3, label, 0)
#define DT_N_S_buttons_S_button_3_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_buttons_S_button_3, label, 0, __VA_ARGS__)
#define DT_N_S_buttons_S_button_3_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_buttons_S_button_3, label, 0, __VA_ARGS__)
#define DT_N_S_buttons_S_button_3_P_label_LEN 1
#define DT_N_S_buttons_S_button_3_P_label_EXISTS 1
#define DT_N_S_buttons_S_button_3_P_zephyr_code 4
#define DT_N_S_buttons_S_button_3_P_zephyr_code_EXISTS 1

/*
 * Devicetree node: /cpus
 *
 * Node identifier: DT_N_S_cpus
 */

/* Node's full path: */
#define DT_N_S_cpus_PATH "/cpus"

/* Node's name with unit-address: */
#define DT_N_S_cpus_FULL_NAME "cpus"

/* Node parent (/) identifier: */
#define DT_N_S_cpus_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_cpus_CHILD_IDX 6

/* Helper macros for child nodes of this node. */
#define DT_N_S_cpus_CHILD_NUM 1
#define DT_N_S_cpus_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_cpus_FOREACH_CHILD(fn) fn(DT_N_S_cpus_S_cpu_0)
#define DT_N_S_cpus_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0)
#define DT_N_S_cpus_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)
#define DT_N_S_cpus_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)
#define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_cpus_S_cpu_0)
#define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0)
#define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)
#define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_cpus_ORD 17
#define DT_N_S_cpus_ORD_STR_SORTABLE 00017

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_SUPPORTS_ORDS \
	18, /* /cpus/cpu@0 */

/* Existence and alternate IDs: */
#define DT_N_S_cpus_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_cpus_REG_NUM 0
#define DT_N_S_cpus_RANGES_NUM 0
#define DT_N_S_cpus_FOREACH_RANGE(fn) 
#define DT_N_S_cpus_IRQ_NUM 0
#define DT_N_S_cpus_IRQ_LEVEL 0
#define DT_N_S_cpus_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_cpus_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /cpus/cpu@0
 *
 * Node identifier: DT_N_S_cpus_S_cpu_0
 *
 * Binding (compatible = arm,cortex-m4f):
 *   $ZEPHYR_BASE/dts/bindings/cpu/arm,cortex-m4f.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_cpus_S_cpu_0_PATH "/cpus/cpu@0"

/* Node's name with unit-address: */
#define DT_N_S_cpus_S_cpu_0_FULL_NAME "cpu@0"

/* Node parent (/cpus) identifier: */
#define DT_N_S_cpus_S_cpu_0_PARENT DT_N_S_cpus

/* Node's index in its parent's list of children: */
#define DT_N_S_cpus_S_cpu_0_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_cpus_S_cpu_0_CHILD_NUM 1
#define DT_N_S_cpus_S_cpu_0_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD(fn) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000)
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000)
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000)
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000)
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_cpus_S_cpu_0_ORD 18
#define DT_N_S_cpus_S_cpu_0_ORD_STR_SORTABLE 00018

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_S_cpu_0_REQUIRES_ORDS \
	17, /* /cpus */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_S_cpu_0_SUPPORTS_ORDS \
	19, /* /cpus/cpu@0/itm@e0000000 */

/* Existence and alternate IDs: */
#define DT_N_S_cpus_S_cpu_0_EXISTS 1
#define DT_N_INST_0_arm_cortex_m4f DT_N_S_cpus_S_cpu_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_cpus_S_cpu_0_REG_NUM 1
#define DT_N_S_cpus_S_cpu_0_REG_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_cpus_S_cpu_0_RANGES_NUM 0
#define DT_N_S_cpus_S_cpu_0_FOREACH_RANGE(fn) 
#define DT_N_S_cpus_S_cpu_0_IRQ_NUM 0
#define DT_N_S_cpus_S_cpu_0_IRQ_LEVEL 0
#define DT_N_S_cpus_S_cpu_0_COMPAT_MATCHES_arm_cortex_m4f 1
#define DT_N_S_cpus_S_cpu_0_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_COMPAT_VENDOR_IDX_0 "ARM Ltd."
#define DT_N_S_cpus_S_cpu_0_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_COMPAT_MODEL_IDX_0 "cortex-m4f"
#define DT_N_S_cpus_S_cpu_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_cpus_S_cpu_0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_cpus_S_cpu_0_P_wakeup_source 0
#define DT_N_S_cpus_S_cpu_0_P_wakeup_source_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_cpus_S_cpu_0_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_compatible {"arm,cortex-m4f"}
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0 "arm,cortex-m4f"
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_STRING_UNQUOTED arm,cortex-m4f
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_STRING_TOKEN arm_cortex_m4f
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_CORTEX_M4F
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0, compatible, 0)
#define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0, compatible, 0)
#define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_P_compatible_LEN 1
#define DT_N_S_cpus_S_cpu_0_P_compatible_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_reg {0 /* 0x0 */}
#define DT_N_S_cpus_S_cpu_0_P_reg_IDX_0 0
#define DT_N_S_cpus_S_cpu_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_reg_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_zephyr_deferred_init 0
#define DT_N_S_cpus_S_cpu_0_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /cpus/cpu@0/itm@e0000000
 *
 * Node identifier: DT_N_S_cpus_S_cpu_0_S_itm_e0000000
 *
 * Binding (compatible = arm,armv7m-itm):
 *   $ZEPHYR_BASE/dts/bindings/debug/arm,armv7m-itm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_PATH "/cpus/cpu@0/itm@e0000000"

/* Node's name with unit-address: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FULL_NAME "itm@e0000000"

/* Node parent (/cpus/cpu@0) identifier: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_PARENT DT_N_S_cpus_S_cpu_0

/* Node's index in its parent's list of children: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_CHILD_NUM 0
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD(fn) 
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_ORD 19
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_ORD_STR_SORTABLE 00019

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_REQUIRES_ORDS \
	18, /* /cpus/cpu@0 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_EXISTS 1
#define DT_N_INST_0_arm_armv7m_itm DT_N_S_cpus_S_cpu_0_S_itm_e0000000
#define DT_N_NODELABEL_itm         DT_N_S_cpus_S_cpu_0_S_itm_e0000000

/* Macros for properties that are special in the specification: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_REG_NUM 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_REG_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_REG_IDX_0_VAL_ADDRESS 3758096384 /* 0xe0000000 */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_RANGES_NUM 0
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_FOREACH_RANGE(fn) 
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_IRQ_NUM 0
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_IRQ_LEVEL 0
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_COMPAT_MATCHES_arm_armv7m_itm 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_COMPAT_VENDOR_IDX_0 "ARM Ltd."
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_COMPAT_MODEL_IDX_0 "armv7m-itm"
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_wakeup_source 0
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_wakeup_source_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible {"arm,armv7m-itm"}
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_IDX_0 "arm,armv7m-itm"
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_IDX_0_STRING_UNQUOTED arm,armv7m-itm
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_IDX_0_STRING_TOKEN arm_armv7m_itm
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_ARMV7M_ITM
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, compatible, 0)
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, compatible, 0)
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_LEN 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_compatible_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg {3758096384 /* 0xe0000000 */, 4096 /* 0x1000 */}
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg_IDX_0 3758096384
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg_IDX_1 4096
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_reg_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_zephyr_deferred_init 0
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_swo_ref_frequency 32000000
#define DT_N_S_cpus_S_cpu_0_S_itm_e0000000_P_swo_ref_frequency_EXISTS 1

/*
 * Devicetree node: /leds
 *
 * Node identifier: DT_N_S_leds
 *
 * Binding (compatible = gpio-leds):
 *   $ZEPHYR_BASE/dts/bindings/led/gpio-leds.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_leds_PATH "/leds"

/* Node's name with unit-address: */
#define DT_N_S_leds_FULL_NAME "leds"

/* Node parent (/) identifier: */
#define DT_N_S_leds_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_leds_CHILD_IDX 7

/* Helper macros for child nodes of this node. */
#define DT_N_S_leds_CHILD_NUM 4
#define DT_N_S_leds_CHILD_NUM_STATUS_OKAY 4
#define DT_N_S_leds_FOREACH_CHILD(fn) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_leds_S_led_3)
#define DT_N_S_leds_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_leds_S_led_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_3)
#define DT_N_S_leds_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__) fn(DT_N_S_leds_S_led_3, __VA_ARGS__)
#define DT_N_S_leds_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_3, __VA_ARGS__)
#define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_leds_S_led_3)
#define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_leds_S_led_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_3)
#define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__) fn(DT_N_S_leds_S_led_3, __VA_ARGS__)
#define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds_S_led_3, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_leds_ORD 20
#define DT_N_S_leds_ORD_STR_SORTABLE 00020

/* Ordinals for what this node depends on directly: */
#define DT_N_S_leds_REQUIRES_ORDS \
	0, /* / */ \
	11, /* /soc/gpio@50000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_leds_SUPPORTS_ORDS \
	21, /* /leds/led_0 */ \
	22, /* /leds/led_1 */ \
	23, /* /leds/led_2 */ \
	24, /* /leds/led_3 */

/* Existence and alternate IDs: */
#define DT_N_S_leds_EXISTS 1
#define DT_N_INST_0_gpio_leds DT_N_S_leds

/* Macros for properties that are special in the specification: */
#define DT_N_S_leds_REG_NUM 0
#define DT_N_S_leds_RANGES_NUM 0
#define DT_N_S_leds_FOREACH_RANGE(fn) 
#define DT_N_S_leds_IRQ_NUM 0
#define DT_N_S_leds_IRQ_LEVEL 0
#define DT_N_S_leds_COMPAT_MATCHES_gpio_leds 1
#define DT_N_S_leds_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_leds_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_leds_P_compatible {"gpio-leds"}
#define DT_N_S_leds_P_compatible_IDX_0 "gpio-leds"
#define DT_N_S_leds_P_compatible_IDX_0_STRING_UNQUOTED gpio-leds
#define DT_N_S_leds_P_compatible_IDX_0_STRING_TOKEN gpio_leds
#define DT_N_S_leds_P_compatible_IDX_0_STRING_UPPER_TOKEN GPIO_LEDS
#define DT_N_S_leds_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds, compatible, 0)
#define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds, compatible, 0)
#define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds, compatible, 0, __VA_ARGS__)
#define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds, compatible, 0, __VA_ARGS__)
#define DT_N_S_leds_P_compatible_LEN 1
#define DT_N_S_leds_P_compatible_EXISTS 1

/*
 * Devicetree node: /leds/led_0
 *
 * Node identifier: DT_N_S_leds_S_led_0
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_leds_S_led_0_PATH "/leds/led_0"

/* Node's name with unit-address: */
#define DT_N_S_leds_S_led_0_FULL_NAME "led_0"

/* Node parent (/leds) identifier: */
#define DT_N_S_leds_S_led_0_PARENT DT_N_S_leds

/* Node's index in its parent's list of children: */
#define DT_N_S_leds_S_led_0_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_leds_S_led_0_CHILD_NUM 0
#define DT_N_S_leds_S_led_0_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_leds_S_led_0_FOREACH_CHILD(fn) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_leds_S_led_0_ORD 21
#define DT_N_S_leds_S_led_0_ORD_STR_SORTABLE 00021

/* Ordinals for what this node depends on directly: */
#define DT_N_S_leds_S_led_0_REQUIRES_ORDS \
	11, /* /soc/gpio@50000000 */ \
	20, /* /leds */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_leds_S_led_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_leds_S_led_0_EXISTS 1
#define DT_N_ALIAS_led0            DT_N_S_leds_S_led_0
#define DT_N_ALIAS_bootloader_led0 DT_N_S_leds_S_led_0
#define DT_N_ALIAS_mcuboot_led0    DT_N_S_leds_S_led_0
#define DT_N_NODELABEL_led0        DT_N_S_leds_S_led_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_leds_S_led_0_REG_NUM 0
#define DT_N_S_leds_S_led_0_RANGES_NUM 0
#define DT_N_S_leds_S_led_0_FOREACH_RANGE(fn) 
#define DT_N_S_leds_S_led_0_IRQ_NUM 0
#define DT_N_S_leds_S_led_0_IRQ_LEVEL 0
#define DT_N_S_leds_S_led_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_leds_S_led_0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_PH DT_N_S_soc_S_gpio_50000000
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_pin 13
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_flags 1
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_0, gpios, 0)
#define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_0, gpios, 0)
#define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, gpios, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, gpios, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_0_P_gpios_LEN 1
#define DT_N_S_leds_S_led_0_P_gpios_EXISTS 1
#define DT_N_S_leds_S_led_0_P_label "Green LED 0"
#define DT_N_S_leds_S_led_0_P_label_STRING_UNQUOTED Green LED 0
#define DT_N_S_leds_S_led_0_P_label_STRING_TOKEN Green_LED_0
#define DT_N_S_leds_S_led_0_P_label_STRING_UPPER_TOKEN GREEN_LED_0
#define DT_N_S_leds_S_led_0_P_label_IDX_0 "Green LED 0"
#define DT_N_S_leds_S_led_0_P_label_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_0, label, 0)
#define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_0, label, 0)
#define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, label, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, label, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_0_P_label_LEN 1
#define DT_N_S_leds_S_led_0_P_label_EXISTS 1

/*
 * Devicetree node: /leds/led_1
 *
 * Node identifier: DT_N_S_leds_S_led_1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_leds_S_led_1_PATH "/leds/led_1"

/* Node's name with unit-address: */
#define DT_N_S_leds_S_led_1_FULL_NAME "led_1"

/* Node parent (/leds) identifier: */
#define DT_N_S_leds_S_led_1_PARENT DT_N_S_leds

/* Node's index in its parent's list of children: */
#define DT_N_S_leds_S_led_1_CHILD_IDX 1

/* Helper macros for child nodes of this node. */
#define DT_N_S_leds_S_led_1_CHILD_NUM 0
#define DT_N_S_leds_S_led_1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_leds_S_led_1_FOREACH_CHILD(fn) 
#define DT_N_S_leds_S_led_1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_leds_S_led_1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_leds_S_led_1_ORD 22
#define DT_N_S_leds_S_led_1_ORD_STR_SORTABLE 00022

/* Ordinals for what this node depends on directly: */
#define DT_N_S_leds_S_led_1_REQUIRES_ORDS \
	11, /* /soc/gpio@50000000 */ \
	20, /* /leds */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_leds_S_led_1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_leds_S_led_1_EXISTS 1
#define DT_N_ALIAS_led1     DT_N_S_leds_S_led_1
#define DT_N_NODELABEL_led1 DT_N_S_leds_S_led_1

/* Macros for properties that are special in the specification: */
#define DT_N_S_leds_S_led_1_REG_NUM 0
#define DT_N_S_leds_S_led_1_RANGES_NUM 0
#define DT_N_S_leds_S_led_1_FOREACH_RANGE(fn) 
#define DT_N_S_leds_S_led_1_IRQ_NUM 0
#define DT_N_S_leds_S_led_1_IRQ_LEVEL 0
#define DT_N_S_leds_S_led_1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_leds_S_led_1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_PH DT_N_S_soc_S_gpio_50000000
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_pin 14
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_flags 1
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_leds_S_led_1_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_1, gpios, 0)
#define DT_N_S_leds_S_led_1_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_1, gpios, 0)
#define DT_N_S_leds_S_led_1_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_1, gpios, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_1_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_1, gpios, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_1_P_gpios_LEN 1
#define DT_N_S_leds_S_led_1_P_gpios_EXISTS 1
#define DT_N_S_leds_S_led_1_P_label "Green LED 1"
#define DT_N_S_leds_S_led_1_P_label_STRING_UNQUOTED Green LED 1
#define DT_N_S_leds_S_led_1_P_label_STRING_TOKEN Green_LED_1
#define DT_N_S_leds_S_led_1_P_label_STRING_UPPER_TOKEN GREEN_LED_1
#define DT_N_S_leds_S_led_1_P_label_IDX_0 "Green LED 1"
#define DT_N_S_leds_S_led_1_P_label_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_1_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_1, label, 0)
#define DT_N_S_leds_S_led_1_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_1, label, 0)
#define DT_N_S_leds_S_led_1_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_1, label, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_1_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_1, label, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_1_P_label_LEN 1
#define DT_N_S_leds_S_led_1_P_label_EXISTS 1

/*
 * Devicetree node: /leds/led_2
 *
 * Node identifier: DT_N_S_leds_S_led_2
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_leds_S_led_2_PATH "/leds/led_2"

/* Node's name with unit-address: */
#define DT_N_S_leds_S_led_2_FULL_NAME "led_2"

/* Node parent (/leds) identifier: */
#define DT_N_S_leds_S_led_2_PARENT DT_N_S_leds

/* Node's index in its parent's list of children: */
#define DT_N_S_leds_S_led_2_CHILD_IDX 2

/* Helper macros for child nodes of this node. */
#define DT_N_S_leds_S_led_2_CHILD_NUM 0
#define DT_N_S_leds_S_led_2_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_leds_S_led_2_FOREACH_CHILD(fn) 
#define DT_N_S_leds_S_led_2_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_leds_S_led_2_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_leds_S_led_2_ORD 23
#define DT_N_S_leds_S_led_2_ORD_STR_SORTABLE 00023

/* Ordinals for what this node depends on directly: */
#define DT_N_S_leds_S_led_2_REQUIRES_ORDS \
	11, /* /soc/gpio@50000000 */ \
	20, /* /leds */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_leds_S_led_2_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_leds_S_led_2_EXISTS 1
#define DT_N_ALIAS_led2     DT_N_S_leds_S_led_2
#define DT_N_NODELABEL_led2 DT_N_S_leds_S_led_2

/* Macros for properties that are special in the specification: */
#define DT_N_S_leds_S_led_2_REG_NUM 0
#define DT_N_S_leds_S_led_2_RANGES_NUM 0
#define DT_N_S_leds_S_led_2_FOREACH_RANGE(fn) 
#define DT_N_S_leds_S_led_2_IRQ_NUM 0
#define DT_N_S_leds_S_led_2_IRQ_LEVEL 0
#define DT_N_S_leds_S_led_2_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_leds_S_led_2_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_PH DT_N_S_soc_S_gpio_50000000
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_pin 15
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_flags 1
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_leds_S_led_2_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_2, gpios, 0)
#define DT_N_S_leds_S_led_2_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_2, gpios, 0)
#define DT_N_S_leds_S_led_2_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_2, gpios, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_2_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_2, gpios, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_2_P_gpios_LEN 1
#define DT_N_S_leds_S_led_2_P_gpios_EXISTS 1
#define DT_N_S_leds_S_led_2_P_label "Green LED 2"
#define DT_N_S_leds_S_led_2_P_label_STRING_UNQUOTED Green LED 2
#define DT_N_S_leds_S_led_2_P_label_STRING_TOKEN Green_LED_2
#define DT_N_S_leds_S_led_2_P_label_STRING_UPPER_TOKEN GREEN_LED_2
#define DT_N_S_leds_S_led_2_P_label_IDX_0 "Green LED 2"
#define DT_N_S_leds_S_led_2_P_label_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_2_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_2, label, 0)
#define DT_N_S_leds_S_led_2_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_2, label, 0)
#define DT_N_S_leds_S_led_2_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_2, label, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_2_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_2, label, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_2_P_label_LEN 1
#define DT_N_S_leds_S_led_2_P_label_EXISTS 1

/*
 * Devicetree node: /leds/led_3
 *
 * Node identifier: DT_N_S_leds_S_led_3
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_leds_S_led_3_PATH "/leds/led_3"

/* Node's name with unit-address: */
#define DT_N_S_leds_S_led_3_FULL_NAME "led_3"

/* Node parent (/leds) identifier: */
#define DT_N_S_leds_S_led_3_PARENT DT_N_S_leds

/* Node's index in its parent's list of children: */
#define DT_N_S_leds_S_led_3_CHILD_IDX 3

/* Helper macros for child nodes of this node. */
#define DT_N_S_leds_S_led_3_CHILD_NUM 0
#define DT_N_S_leds_S_led_3_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_leds_S_led_3_FOREACH_CHILD(fn) 
#define DT_N_S_leds_S_led_3_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_leds_S_led_3_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_3_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_leds_S_led_3_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_leds_S_led_3_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_leds_S_led_3_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_3_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_leds_S_led_3_ORD 24
#define DT_N_S_leds_S_led_3_ORD_STR_SORTABLE 00024

/* Ordinals for what this node depends on directly: */
#define DT_N_S_leds_S_led_3_REQUIRES_ORDS \
	11, /* /soc/gpio@50000000 */ \
	20, /* /leds */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_leds_S_led_3_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_leds_S_led_3_EXISTS 1
#define DT_N_ALIAS_led3     DT_N_S_leds_S_led_3
#define DT_N_NODELABEL_led3 DT_N_S_leds_S_led_3

/* Macros for properties that are special in the specification: */
#define DT_N_S_leds_S_led_3_REG_NUM 0
#define DT_N_S_leds_S_led_3_RANGES_NUM 0
#define DT_N_S_leds_S_led_3_FOREACH_RANGE(fn) 
#define DT_N_S_leds_S_led_3_IRQ_NUM 0
#define DT_N_S_leds_S_led_3_IRQ_LEVEL 0
#define DT_N_S_leds_S_led_3_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_leds_S_led_3_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_PH DT_N_S_soc_S_gpio_50000000
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_pin 16
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_flags 1
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_leds_S_led_3_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_3, gpios, 0)
#define DT_N_S_leds_S_led_3_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_3, gpios, 0)
#define DT_N_S_leds_S_led_3_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_3, gpios, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_3_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_3, gpios, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_3_P_gpios_LEN 1
#define DT_N_S_leds_S_led_3_P_gpios_EXISTS 1
#define DT_N_S_leds_S_led_3_P_label "Green LED 3"
#define DT_N_S_leds_S_led_3_P_label_STRING_UNQUOTED Green LED 3
#define DT_N_S_leds_S_led_3_P_label_STRING_TOKEN Green_LED_3
#define DT_N_S_leds_S_led_3_P_label_STRING_UPPER_TOKEN GREEN_LED_3
#define DT_N_S_leds_S_led_3_P_label_IDX_0 "Green LED 3"
#define DT_N_S_leds_S_led_3_P_label_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_3_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_3, label, 0)
#define DT_N_S_leds_S_led_3_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_3, label, 0)
#define DT_N_S_leds_S_led_3_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_3, label, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_3_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_3, label, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_3_P_label_LEN 1
#define DT_N_S_leds_S_led_3_P_label_EXISTS 1

/*
 * Devicetree node: /pin-controller
 *
 * Node identifier: DT_N_S_pin_controller
 *
 * Binding (compatible = nordic,nrf-pinctrl):
 *   $ZEPHYR_BASE/dts/bindings/pinctrl/nordic,nrf-pinctrl.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_PATH "/pin-controller"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_FULL_NAME "pin-controller"

/* Node parent (/) identifier: */
#define DT_N_S_pin_controller_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_CHILD_IDX 3

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_CHILD_NUM 20
#define DT_N_S_pin_controller_CHILD_NUM_STATUS_OKAY 20
#define DT_N_S_pin_controller_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_uart0_default) fn(DT_N_S_pin_controller_S_uart0_sleep) fn(DT_N_S_pin_controller_S_uart1_default) fn(DT_N_S_pin_controller_S_uart1_sleep) fn(DT_N_S_pin_controller_S_i2c0_default) fn(DT_N_S_pin_controller_S_i2c0_sleep) fn(DT_N_S_pin_controller_S_i2c1_default) fn(DT_N_S_pin_controller_S_i2c1_sleep) fn(DT_N_S_pin_controller_S_pwm0_default) fn(DT_N_S_pin_controller_S_pwm0_sleep) fn(DT_N_S_pin_controller_S_spi0_default) fn(DT_N_S_pin_controller_S_spi0_sleep) fn(DT_N_S_pin_controller_S_spi1_default) fn(DT_N_S_pin_controller_S_spi1_sleep) fn(DT_N_S_pin_controller_S_spi2_default) fn(DT_N_S_pin_controller_S_spi2_sleep) fn(DT_N_S_pin_controller_S_qspi_default) fn(DT_N_S_pin_controller_S_qspi_sleep) fn(DT_N_S_pin_controller_S_spi3_default) fn(DT_N_S_pin_controller_S_spi3_sleep)
#define DT_N_S_pin_controller_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c0_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c0_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c1_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c1_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi0_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi0_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi1_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi1_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi2_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi2_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi3_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi3_sleep)
#define DT_N_S_pin_controller_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi1_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi2_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi2_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_sleep, __VA_ARGS__)
#define DT_N_S_pin_controller_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c0_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c0_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c1_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c1_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi0_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi0_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi1_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi1_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi2_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi2_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi3_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi3_sleep, __VA_ARGS__)
#define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_uart0_default) fn(DT_N_S_pin_controller_S_uart0_sleep) fn(DT_N_S_pin_controller_S_uart1_default) fn(DT_N_S_pin_controller_S_uart1_sleep) fn(DT_N_S_pin_controller_S_i2c0_default) fn(DT_N_S_pin_controller_S_i2c0_sleep) fn(DT_N_S_pin_controller_S_i2c1_default) fn(DT_N_S_pin_controller_S_i2c1_sleep) fn(DT_N_S_pin_controller_S_pwm0_default) fn(DT_N_S_pin_controller_S_pwm0_sleep) fn(DT_N_S_pin_controller_S_spi0_default) fn(DT_N_S_pin_controller_S_spi0_sleep) fn(DT_N_S_pin_controller_S_spi1_default) fn(DT_N_S_pin_controller_S_spi1_sleep) fn(DT_N_S_pin_controller_S_spi2_default) fn(DT_N_S_pin_controller_S_spi2_sleep) fn(DT_N_S_pin_controller_S_qspi_default) fn(DT_N_S_pin_controller_S_qspi_sleep) fn(DT_N_S_pin_controller_S_spi3_default) fn(DT_N_S_pin_controller_S_spi3_sleep)
#define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c0_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c0_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c1_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c1_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi0_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi0_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi1_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi1_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi2_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi2_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi3_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi3_sleep)
#define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi1_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi2_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi2_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_sleep, __VA_ARGS__)
#define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c0_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c0_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c1_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c1_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_pwm0_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi0_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi0_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi1_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi1_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi2_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi2_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi3_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spi3_sleep, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_ORD 25
#define DT_N_S_pin_controller_ORD_STR_SORTABLE 00025

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_SUPPORTS_ORDS \
	26, /* /pin-controller/i2c0_default */ \
	28, /* /pin-controller/i2c0_sleep */ \
	30, /* /pin-controller/i2c1_default */ \
	32, /* /pin-controller/i2c1_sleep */ \
	34, /* /pin-controller/pwm0_default */ \
	36, /* /pin-controller/pwm0_sleep */ \
	38, /* /pin-controller/qspi_default */ \
	40, /* /pin-controller/qspi_sleep */ \
	43, /* /pin-controller/spi0_default */ \
	45, /* /pin-controller/spi0_sleep */ \
	47, /* /pin-controller/spi1_default */ \
	49, /* /pin-controller/spi1_sleep */ \
	51, /* /pin-controller/spi2_default */ \
	53, /* /pin-controller/spi2_sleep */ \
	55, /* /pin-controller/spi3_default */ \
	57, /* /pin-controller/spi3_sleep */ \
	59, /* /pin-controller/uart0_default */ \
	62, /* /pin-controller/uart0_sleep */ \
	64, /* /pin-controller/uart1_default */ \
	67, /* /pin-controller/uart1_sleep */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_EXISTS 1
#define DT_N_INST_0_nordic_nrf_pinctrl DT_N_S_pin_controller
#define DT_N_NODELABEL_pinctrl         DT_N_S_pin_controller

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_REG_NUM 0
#define DT_N_S_pin_controller_RANGES_NUM 0
#define DT_N_S_pin_controller_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_IRQ_NUM 0
#define DT_N_S_pin_controller_IRQ_LEVEL 0
#define DT_N_S_pin_controller_COMPAT_MATCHES_nordic_nrf_pinctrl 1
#define DT_N_S_pin_controller_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_pin_controller_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_COMPAT_MODEL_IDX_0 "nrf-pinctrl"
#define DT_N_S_pin_controller_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_P_wakeup_source 0
#define DT_N_S_pin_controller_P_wakeup_source_EXISTS 1
#define DT_N_S_pin_controller_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_pin_controller_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_pin_controller_P_compatible {"nordic,nrf-pinctrl"}
#define DT_N_S_pin_controller_P_compatible_IDX_0 "nordic,nrf-pinctrl"
#define DT_N_S_pin_controller_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pinctrl
#define DT_N_S_pin_controller_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pinctrl
#define DT_N_S_pin_controller_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PINCTRL
#define DT_N_S_pin_controller_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller, compatible, 0)
#define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller, compatible, 0)
#define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller, compatible, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller, compatible, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_P_compatible_LEN 1
#define DT_N_S_pin_controller_P_compatible_EXISTS 1
#define DT_N_S_pin_controller_P_zephyr_deferred_init 0
#define DT_N_S_pin_controller_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /pin-controller/i2c0_default
 *
 * Node identifier: DT_N_S_pin_controller_S_i2c0_default
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_i2c0_default_PATH "/pin-controller/i2c0_default"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_i2c0_default_FULL_NAME "i2c0_default"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_i2c0_default_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_i2c0_default_CHILD_IDX 4

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_i2c0_default_CHILD_NUM 1
#define DT_N_S_pin_controller_S_i2c0_default_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1)
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1)
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1)
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1)
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_i2c0_default_ORD 26
#define DT_N_S_pin_controller_S_i2c0_default_ORD_STR_SORTABLE 00026

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_i2c0_default_REQUIRES_ORDS \
	25, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_i2c0_default_SUPPORTS_ORDS \
	27, /* /pin-controller/i2c0_default/group1 */ \
	86, /* /soc/i2c@40003000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_i2c0_default_EXISTS 1
#define DT_N_NODELABEL_i2c0_default DT_N_S_pin_controller_S_i2c0_default

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_i2c0_default_REG_NUM 0
#define DT_N_S_pin_controller_S_i2c0_default_RANGES_NUM 0
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_i2c0_default_IRQ_NUM 0
#define DT_N_S_pin_controller_S_i2c0_default_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_i2c0_default_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_i2c0_default_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/i2c0_default/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_i2c0_default_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_PATH "/pin-controller/i2c0_default/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/i2c0_default) identifier: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_PARENT DT_N_S_pin_controller_S_i2c0_default

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_ORD 27
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_ORD_STR_SORTABLE 00027

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_REQUIRES_ORDS \
	26, /* /pin-controller/i2c0_default */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_low_power_enable 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_psels {1572890 /* 0x18001a */, 1441819 /* 0x16001b */}
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_psels_IDX_0 1572890
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_psels_IDX_1 1441819
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, psels, 1)
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, psels, 1)
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_psels_LEN 2
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/i2c0_sleep
 *
 * Node identifier: DT_N_S_pin_controller_S_i2c0_sleep
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_i2c0_sleep_PATH "/pin-controller/i2c0_sleep"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_i2c0_sleep_FULL_NAME "i2c0_sleep"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_i2c0_sleep_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_i2c0_sleep_CHILD_IDX 5

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_i2c0_sleep_CHILD_NUM 1
#define DT_N_S_pin_controller_S_i2c0_sleep_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_i2c0_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1)
#define DT_N_S_pin_controller_S_i2c0_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1)
#define DT_N_S_pin_controller_S_i2c0_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c0_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c0_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1)
#define DT_N_S_pin_controller_S_i2c0_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1)
#define DT_N_S_pin_controller_S_i2c0_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c0_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_i2c0_sleep_ORD 28
#define DT_N_S_pin_controller_S_i2c0_sleep_ORD_STR_SORTABLE 00028

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_i2c0_sleep_REQUIRES_ORDS \
	25, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_i2c0_sleep_SUPPORTS_ORDS \
	29, /* /pin-controller/i2c0_sleep/group1 */ \
	86, /* /soc/i2c@40003000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_i2c0_sleep_EXISTS 1
#define DT_N_NODELABEL_i2c0_sleep DT_N_S_pin_controller_S_i2c0_sleep

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_i2c0_sleep_REG_NUM 0
#define DT_N_S_pin_controller_S_i2c0_sleep_RANGES_NUM 0
#define DT_N_S_pin_controller_S_i2c0_sleep_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_i2c0_sleep_IRQ_NUM 0
#define DT_N_S_pin_controller_S_i2c0_sleep_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_i2c0_sleep_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_i2c0_sleep_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/i2c0_sleep/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_i2c0_sleep_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_PATH "/pin-controller/i2c0_sleep/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/i2c0_sleep) identifier: */
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_PARENT DT_N_S_pin_controller_S_i2c0_sleep

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_ORD 29
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_ORD_STR_SORTABLE 00029

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_REQUIRES_ORDS \
	28, /* /pin-controller/i2c0_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_low_power_enable 1
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_psels {1572890 /* 0x18001a */, 1441819 /* 0x16001b */}
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_psels_IDX_0 1572890
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_psels_IDX_1 1441819
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1, psels, 1)
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1, psels, 1)
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_psels_LEN 2
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_i2c0_sleep_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/i2c1_default
 *
 * Node identifier: DT_N_S_pin_controller_S_i2c1_default
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_i2c1_default_PATH "/pin-controller/i2c1_default"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_i2c1_default_FULL_NAME "i2c1_default"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_i2c1_default_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_i2c1_default_CHILD_IDX 6

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_i2c1_default_CHILD_NUM 1
#define DT_N_S_pin_controller_S_i2c1_default_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1)
#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1)
#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1)
#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1)
#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_i2c1_default_ORD 30
#define DT_N_S_pin_controller_S_i2c1_default_ORD_STR_SORTABLE 00030

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_i2c1_default_REQUIRES_ORDS \
	25, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_i2c1_default_SUPPORTS_ORDS \
	31, /* /pin-controller/i2c1_default/group1 */ \
	87, /* /soc/i2c@40004000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_i2c1_default_EXISTS 1
#define DT_N_NODELABEL_i2c1_default DT_N_S_pin_controller_S_i2c1_default

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_i2c1_default_REG_NUM 0
#define DT_N_S_pin_controller_S_i2c1_default_RANGES_NUM 0
#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_i2c1_default_IRQ_NUM 0
#define DT_N_S_pin_controller_S_i2c1_default_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_i2c1_default_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_i2c1_default_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/i2c1_default/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_i2c1_default_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_PATH "/pin-controller/i2c1_default/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/i2c1_default) identifier: */
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_PARENT DT_N_S_pin_controller_S_i2c1_default

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_ORD 31
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_ORD_STR_SORTABLE 00031

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_REQUIRES_ORDS \
	30, /* /pin-controller/i2c1_default */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_low_power_enable 0
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels {1572894 /* 0x18001e */, 1441823 /* 0x16001f */}
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_IDX_0 1572894
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_IDX_1 1441823
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, psels, 1)
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, psels, 1)
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_LEN 2
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/i2c1_sleep
 *
 * Node identifier: DT_N_S_pin_controller_S_i2c1_sleep
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_i2c1_sleep_PATH "/pin-controller/i2c1_sleep"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_i2c1_sleep_FULL_NAME "i2c1_sleep"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_i2c1_sleep_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_i2c1_sleep_CHILD_IDX 7

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_i2c1_sleep_CHILD_NUM 1
#define DT_N_S_pin_controller_S_i2c1_sleep_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1)
#define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1)
#define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1)
#define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1)
#define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_i2c1_sleep_ORD 32
#define DT_N_S_pin_controller_S_i2c1_sleep_ORD_STR_SORTABLE 00032

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_i2c1_sleep_REQUIRES_ORDS \
	25, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_i2c1_sleep_SUPPORTS_ORDS \
	33, /* /pin-controller/i2c1_sleep/group1 */ \
	87, /* /soc/i2c@40004000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_i2c1_sleep_EXISTS 1
#define DT_N_NODELABEL_i2c1_sleep DT_N_S_pin_controller_S_i2c1_sleep

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_i2c1_sleep_REG_NUM 0
#define DT_N_S_pin_controller_S_i2c1_sleep_RANGES_NUM 0
#define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_i2c1_sleep_IRQ_NUM 0
#define DT_N_S_pin_controller_S_i2c1_sleep_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_i2c1_sleep_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_i2c1_sleep_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/i2c1_sleep/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_i2c1_sleep_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_PATH "/pin-controller/i2c1_sleep/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/i2c1_sleep) identifier: */
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_PARENT DT_N_S_pin_controller_S_i2c1_sleep

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_ORD 33
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_ORD_STR_SORTABLE 00033

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_REQUIRES_ORDS \
	32, /* /pin-controller/i2c1_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_low_power_enable 1
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels {1572894 /* 0x18001e */, 1441823 /* 0x16001f */}
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_IDX_0 1572894
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_IDX_1 1441823
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, psels, 1)
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, psels, 1)
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_LEN 2
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/pwm0_default
 *
 * Node identifier: DT_N_S_pin_controller_S_pwm0_default
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_pwm0_default_PATH "/pin-controller/pwm0_default"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_pwm0_default_FULL_NAME "pwm0_default"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_pwm0_default_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_pwm0_default_CHILD_IDX 8

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_pwm0_default_CHILD_NUM 1
#define DT_N_S_pin_controller_S_pwm0_default_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_pwm0_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1)
#define DT_N_S_pin_controller_S_pwm0_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1)
#define DT_N_S_pin_controller_S_pwm0_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_pwm0_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_pwm0_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1)
#define DT_N_S_pin_controller_S_pwm0_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1)
#define DT_N_S_pin_controller_S_pwm0_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_pwm0_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_pwm0_default_ORD 34
#define DT_N_S_pin_controller_S_pwm0_default_ORD_STR_SORTABLE 00034

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_pwm0_default_REQUIRES_ORDS \
	25, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_pwm0_default_SUPPORTS_ORDS \
	35, /* /pin-controller/pwm0_default/group1 */ \
	69, /* /soc/pwm@4001c000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_pwm0_default_EXISTS 1
#define DT_N_NODELABEL_pwm0_default DT_N_S_pin_controller_S_pwm0_default

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_pwm0_default_REG_NUM 0
#define DT_N_S_pin_controller_S_pwm0_default_RANGES_NUM 0
#define DT_N_S_pin_controller_S_pwm0_default_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_pwm0_default_IRQ_NUM 0
#define DT_N_S_pin_controller_S_pwm0_default_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_pwm0_default_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_pwm0_default_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/pwm0_default/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_pwm0_default_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_PATH "/pin-controller/pwm0_default/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/pwm0_default) identifier: */
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_PARENT DT_N_S_pin_controller_S_pwm0_default

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_ORD 35
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_ORD_STR_SORTABLE 00035

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_REQUIRES_ORDS \
	34, /* /pin-controller/pwm0_default */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_low_power_enable 0
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_psels {2883597 /* 0x2c000d */}
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_psels_IDX_0 2883597
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1, psels, 0)
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1, psels, 0)
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1, psels, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1, psels, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_psels_LEN 1
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_nordic_invert 1
#define DT_N_S_pin_controller_S_pwm0_default_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/pwm0_sleep
 *
 * Node identifier: DT_N_S_pin_controller_S_pwm0_sleep
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_pwm0_sleep_PATH "/pin-controller/pwm0_sleep"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_pwm0_sleep_FULL_NAME "pwm0_sleep"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_pwm0_sleep_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_pwm0_sleep_CHILD_IDX 9

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_pwm0_sleep_CHILD_NUM 1
#define DT_N_S_pin_controller_S_pwm0_sleep_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1)
#define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1)
#define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1)
#define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1)
#define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_pwm0_sleep_ORD 36
#define DT_N_S_pin_controller_S_pwm0_sleep_ORD_STR_SORTABLE 00036

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_pwm0_sleep_REQUIRES_ORDS \
	25, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_pwm0_sleep_SUPPORTS_ORDS \
	37, /* /pin-controller/pwm0_sleep/group1 */ \
	69, /* /soc/pwm@4001c000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_pwm0_sleep_EXISTS 1
#define DT_N_NODELABEL_pwm0_sleep DT_N_S_pin_controller_S_pwm0_sleep

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_pwm0_sleep_REG_NUM 0
#define DT_N_S_pin_controller_S_pwm0_sleep_RANGES_NUM 0
#define DT_N_S_pin_controller_S_pwm0_sleep_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_pwm0_sleep_IRQ_NUM 0
#define DT_N_S_pin_controller_S_pwm0_sleep_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_pwm0_sleep_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_pwm0_sleep_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/pwm0_sleep/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_pwm0_sleep_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_PATH "/pin-controller/pwm0_sleep/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/pwm0_sleep) identifier: */
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_PARENT DT_N_S_pin_controller_S_pwm0_sleep

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_ORD 37
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_ORD_STR_SORTABLE 00037

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_REQUIRES_ORDS \
	36, /* /pin-controller/pwm0_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_low_power_enable 1
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels {2883597 /* 0x2c000d */}
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels_IDX_0 2883597
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, psels, 0)
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, psels, 0)
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, psels, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, psels, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels_LEN 1
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_pwm0_sleep_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/qspi_default
 *
 * Node identifier: DT_N_S_pin_controller_S_qspi_default
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_qspi_default_PATH "/pin-controller/qspi_default"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_qspi_default_FULL_NAME "qspi_default"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_qspi_default_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_qspi_default_CHILD_IDX 16

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_qspi_default_CHILD_NUM 1
#define DT_N_S_pin_controller_S_qspi_default_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_qspi_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_qspi_default_S_group1)
#define DT_N_S_pin_controller_S_qspi_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_qspi_default_S_group1)
#define DT_N_S_pin_controller_S_qspi_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_qspi_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_qspi_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_qspi_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_qspi_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_qspi_default_S_group1)
#define DT_N_S_pin_controller_S_qspi_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_qspi_default_S_group1)
#define DT_N_S_pin_controller_S_qspi_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_qspi_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_qspi_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_qspi_default_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_qspi_default_ORD 38
#define DT_N_S_pin_controller_S_qspi_default_ORD_STR_SORTABLE 00038

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_qspi_default_REQUIRES_ORDS \
	25, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_qspi_default_SUPPORTS_ORDS \
	39, /* /pin-controller/qspi_default/group1 */ \
	128, /* /soc/qspi@40029000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_qspi_default_EXISTS 1
#define DT_N_NODELABEL_qspi_default DT_N_S_pin_controller_S_qspi_default

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_qspi_default_REG_NUM 0
#define DT_N_S_pin_controller_S_qspi_default_RANGES_NUM 0
#define DT_N_S_pin_controller_S_qspi_default_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_qspi_default_IRQ_NUM 0
#define DT_N_S_pin_controller_S_qspi_default_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_qspi_default_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_qspi_default_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/qspi_default/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_qspi_default_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_qspi_default_S_group1_PATH "/pin-controller/qspi_default/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_qspi_default_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/qspi_default) identifier: */
#define DT_N_S_pin_controller_S_qspi_default_S_group1_PARENT DT_N_S_pin_controller_S_qspi_default

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_qspi_default_S_group1_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_qspi_default_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_qspi_default_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_qspi_default_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_qspi_default_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_qspi_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_qspi_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_qspi_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_qspi_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_qspi_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_qspi_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_qspi_default_S_group1_ORD 39
#define DT_N_S_pin_controller_S_qspi_default_S_group1_ORD_STR_SORTABLE 00039

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_qspi_default_S_group1_REQUIRES_ORDS \
	38, /* /pin-controller/qspi_default */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_qspi_default_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_qspi_default_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_qspi_default_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_qspi_default_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_qspi_default_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_qspi_default_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_qspi_default_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_qspi_default_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_qspi_default_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_qspi_default_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_qspi_default_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_qspi_default_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_qspi_default_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_qspi_default_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_qspi_default_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_qspi_default_S_group1_P_low_power_enable 0
#define DT_N_S_pin_controller_S_qspi_default_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels {3801107 /* 0x3a0013 */, 4063252 /* 0x3e0014 */, 4194325 /* 0x400015 */, 4325398 /* 0x420016 */, 4456471 /* 0x440017 */, 3932177 /* 0x3c0011 */}
#define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_0 3801107
#define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_1 4063252
#define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_2 4194325
#define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_2_EXISTS 1
#define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_3 4325398
#define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_3_EXISTS 1
#define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_4 4456471
#define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_4_EXISTS 1
#define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_5 3932177
#define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_IDX_5_EXISTS 1
#define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 1) \
	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 2) \
	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 3) \
	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 4) \
	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 5)
#define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 5)
#define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 1, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 2, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 3, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 4, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 5, __VA_ARGS__)
#define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_qspi_default_S_group1, psels, 5, __VA_ARGS__)
#define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_LEN 6
#define DT_N_S_pin_controller_S_qspi_default_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_qspi_default_S_group1_P_nordic_drive_mode 3
#define DT_N_S_pin_controller_S_qspi_default_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_qspi_default_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_qspi_default_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/qspi_sleep
 *
 * Node identifier: DT_N_S_pin_controller_S_qspi_sleep
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_qspi_sleep_PATH "/pin-controller/qspi_sleep"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_qspi_sleep_FULL_NAME "qspi_sleep"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_qspi_sleep_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_qspi_sleep_CHILD_IDX 17

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_qspi_sleep_CHILD_NUM 2
#define DT_N_S_pin_controller_S_qspi_sleep_CHILD_NUM_STATUS_OKAY 2
#define DT_N_S_pin_controller_S_qspi_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2)
#define DT_N_S_pin_controller_S_qspi_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2)
#define DT_N_S_pin_controller_S_qspi_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_qspi_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_qspi_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2)
#define DT_N_S_pin_controller_S_qspi_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2)
#define DT_N_S_pin_controller_S_qspi_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_qspi_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_qspi_sleep_ORD 40
#define DT_N_S_pin_controller_S_qspi_sleep_ORD_STR_SORTABLE 00040

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_qspi_sleep_REQUIRES_ORDS \
	25, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_qspi_sleep_SUPPORTS_ORDS \
	41, /* /pin-controller/qspi_sleep/group1 */ \
	42, /* /pin-controller/qspi_sleep/group2 */ \
	128, /* /soc/qspi@40029000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_qspi_sleep_EXISTS 1
#define DT_N_NODELABEL_qspi_sleep DT_N_S_pin_controller_S_qspi_sleep

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_qspi_sleep_REG_NUM 0
#define DT_N_S_pin_controller_S_qspi_sleep_RANGES_NUM 0
#define DT_N_S_pin_controller_S_qspi_sleep_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_qspi_sleep_IRQ_NUM 0
#define DT_N_S_pin_controller_S_qspi_sleep_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_qspi_sleep_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_qspi_sleep_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/qspi_sleep/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_qspi_sleep_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_PATH "/pin-controller/qspi_sleep/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/qspi_sleep) identifier: */
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_PARENT DT_N_S_pin_controller_S_qspi_sleep

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_ORD 41
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_ORD_STR_SORTABLE 00041

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_REQUIRES_ORDS \
	40, /* /pin-controller/qspi_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_low_power_enable 1
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels {3801107 /* 0x3a0013 */, 4063252 /* 0x3e0014 */, 4194325 /* 0x400015 */, 4325398 /* 0x420016 */, 4456471 /* 0x440017 */}
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_IDX_0 3801107
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_IDX_1 4063252
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_IDX_2 4194325
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_IDX_2_EXISTS 1
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_IDX_3 4325398
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_IDX_3_EXISTS 1
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_IDX_4 4456471
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_IDX_4_EXISTS 1
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 1) \
	fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 2) \
	fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 3) \
	fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 4)
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 4)
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 1, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 2, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 3, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 4, __VA_ARGS__)
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, psels, 4, __VA_ARGS__)
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_LEN 5
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_qspi_sleep_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/qspi_sleep/group2
 *
 * Node identifier: DT_N_S_pin_controller_S_qspi_sleep_S_group2
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_PATH "/pin-controller/qspi_sleep/group2"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FULL_NAME "group2"

/* Node parent (/pin-controller/qspi_sleep) identifier: */
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_PARENT DT_N_S_pin_controller_S_qspi_sleep

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_CHILD_IDX 1

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_CHILD_NUM 0
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_ORD 42
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_ORD_STR_SORTABLE 00042

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_REQUIRES_ORDS \
	40, /* /pin-controller/qspi_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_REG_NUM 0
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_RANGES_NUM 0
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_IRQ_NUM 0
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_bias_disable 0
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_bias_pull_up 1
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_low_power_enable 1
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_psels {3932177 /* 0x3c0011 */}
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_psels_IDX_0 3932177
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2, psels, 0)
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2, psels, 0)
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2, psels, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2, psels, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_psels_LEN 1
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_nordic_invert 0
#define DT_N_S_pin_controller_S_qspi_sleep_S_group2_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/spi0_default
 *
 * Node identifier: DT_N_S_pin_controller_S_spi0_default
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spi0_default_PATH "/pin-controller/spi0_default"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spi0_default_FULL_NAME "spi0_default"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_spi0_default_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spi0_default_CHILD_IDX 10

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spi0_default_CHILD_NUM 1
#define DT_N_S_pin_controller_S_spi0_default_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_spi0_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_spi0_default_S_group1)
#define DT_N_S_pin_controller_S_spi0_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi0_default_S_group1)
#define DT_N_S_pin_controller_S_spi0_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi0_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi0_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi0_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi0_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_spi0_default_S_group1)
#define DT_N_S_pin_controller_S_spi0_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi0_default_S_group1)
#define DT_N_S_pin_controller_S_spi0_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi0_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi0_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi0_default_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spi0_default_ORD 43
#define DT_N_S_pin_controller_S_spi0_default_ORD_STR_SORTABLE 00043

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spi0_default_REQUIRES_ORDS \
	25, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spi0_default_SUPPORTS_ORDS \
	44, /* /pin-controller/spi0_default/group1 */ \
	102, /* /soc/spi@40003000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spi0_default_EXISTS 1
#define DT_N_NODELABEL_spi0_default DT_N_S_pin_controller_S_spi0_default

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spi0_default_REG_NUM 0
#define DT_N_S_pin_controller_S_spi0_default_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spi0_default_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spi0_default_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spi0_default_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spi0_default_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spi0_default_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/spi0_default/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_spi0_default_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spi0_default_S_group1_PATH "/pin-controller/spi0_default/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spi0_default_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/spi0_default) identifier: */
#define DT_N_S_pin_controller_S_spi0_default_S_group1_PARENT DT_N_S_pin_controller_S_spi0_default

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spi0_default_S_group1_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spi0_default_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_spi0_default_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_spi0_default_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_spi0_default_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spi0_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spi0_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_spi0_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_spi0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spi0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spi0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spi0_default_S_group1_ORD 44
#define DT_N_S_pin_controller_S_spi0_default_S_group1_ORD_STR_SORTABLE 00044

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spi0_default_S_group1_REQUIRES_ORDS \
	43, /* /pin-controller/spi0_default */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spi0_default_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spi0_default_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spi0_default_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_spi0_default_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spi0_default_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spi0_default_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spi0_default_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spi0_default_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spi0_default_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_spi0_default_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_spi0_default_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_spi0_default_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_spi0_default_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_spi0_default_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_spi0_default_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_spi0_default_S_group1_P_low_power_enable 0
#define DT_N_S_pin_controller_S_spi0_default_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_spi0_default_S_group1_P_psels {524315 /* 0x8001b */, 655386 /* 0xa001a */, 786461 /* 0xc001d */}
#define DT_N_S_pin_controller_S_spi0_default_S_group1_P_psels_IDX_0 524315
#define DT_N_S_pin_controller_S_spi0_default_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_spi0_default_S_group1_P_psels_IDX_1 655386
#define DT_N_S_pin_controller_S_spi0_default_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_spi0_default_S_group1_P_psels_IDX_2 786461
#define DT_N_S_pin_controller_S_spi0_default_S_group1_P_psels_IDX_2_EXISTS 1
#define DT_N_S_pin_controller_S_spi0_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_spi0_default_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_spi0_default_S_group1, psels, 1) \
	fn(DT_N_S_pin_controller_S_spi0_default_S_group1, psels, 2)
#define DT_N_S_pin_controller_S_spi0_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi0_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi0_default_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi0_default_S_group1, psels, 2)
#define DT_N_S_pin_controller_S_spi0_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi0_default_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi0_default_S_group1, psels, 1, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi0_default_S_group1, psels, 2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi0_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi0_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi0_default_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi0_default_S_group1, psels, 2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi0_default_S_group1_P_psels_LEN 3
#define DT_N_S_pin_controller_S_spi0_default_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_spi0_default_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_spi0_default_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_spi0_default_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_spi0_default_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/spi0_sleep
 *
 * Node identifier: DT_N_S_pin_controller_S_spi0_sleep
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spi0_sleep_PATH "/pin-controller/spi0_sleep"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spi0_sleep_FULL_NAME "spi0_sleep"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_spi0_sleep_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spi0_sleep_CHILD_IDX 11

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spi0_sleep_CHILD_NUM 1
#define DT_N_S_pin_controller_S_spi0_sleep_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_spi0_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_spi0_sleep_S_group1)
#define DT_N_S_pin_controller_S_spi0_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi0_sleep_S_group1)
#define DT_N_S_pin_controller_S_spi0_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi0_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi0_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi0_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi0_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_spi0_sleep_S_group1)
#define DT_N_S_pin_controller_S_spi0_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi0_sleep_S_group1)
#define DT_N_S_pin_controller_S_spi0_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi0_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi0_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi0_sleep_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spi0_sleep_ORD 45
#define DT_N_S_pin_controller_S_spi0_sleep_ORD_STR_SORTABLE 00045

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spi0_sleep_REQUIRES_ORDS \
	25, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spi0_sleep_SUPPORTS_ORDS \
	46, /* /pin-controller/spi0_sleep/group1 */ \
	102, /* /soc/spi@40003000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spi0_sleep_EXISTS 1
#define DT_N_NODELABEL_spi0_sleep DT_N_S_pin_controller_S_spi0_sleep

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spi0_sleep_REG_NUM 0
#define DT_N_S_pin_controller_S_spi0_sleep_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spi0_sleep_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spi0_sleep_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spi0_sleep_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spi0_sleep_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spi0_sleep_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/spi0_sleep/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_spi0_sleep_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_PATH "/pin-controller/spi0_sleep/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/spi0_sleep) identifier: */
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_PARENT DT_N_S_pin_controller_S_spi0_sleep

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_ORD 46
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_ORD_STR_SORTABLE 00046

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_REQUIRES_ORDS \
	45, /* /pin-controller/spi0_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_P_low_power_enable 1
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_P_psels {524315 /* 0x8001b */, 655386 /* 0xa001a */, 786461 /* 0xc001d */}
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_P_psels_IDX_0 524315
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_P_psels_IDX_1 655386
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_P_psels_IDX_2 786461
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_P_psels_IDX_2_EXISTS 1
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_spi0_sleep_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_spi0_sleep_S_group1, psels, 1) \
	fn(DT_N_S_pin_controller_S_spi0_sleep_S_group1, psels, 2)
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi0_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi0_sleep_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi0_sleep_S_group1, psels, 2)
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi0_sleep_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi0_sleep_S_group1, psels, 1, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi0_sleep_S_group1, psels, 2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi0_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi0_sleep_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi0_sleep_S_group1, psels, 2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_P_psels_LEN 3
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_spi0_sleep_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/spi1_default
 *
 * Node identifier: DT_N_S_pin_controller_S_spi1_default
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spi1_default_PATH "/pin-controller/spi1_default"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spi1_default_FULL_NAME "spi1_default"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_spi1_default_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spi1_default_CHILD_IDX 12

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spi1_default_CHILD_NUM 1
#define DT_N_S_pin_controller_S_spi1_default_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_spi1_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_spi1_default_S_group1)
#define DT_N_S_pin_controller_S_spi1_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi1_default_S_group1)
#define DT_N_S_pin_controller_S_spi1_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi1_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi1_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi1_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi1_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_spi1_default_S_group1)
#define DT_N_S_pin_controller_S_spi1_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi1_default_S_group1)
#define DT_N_S_pin_controller_S_spi1_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi1_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi1_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi1_default_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spi1_default_ORD 47
#define DT_N_S_pin_controller_S_spi1_default_ORD_STR_SORTABLE 00047

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spi1_default_REQUIRES_ORDS \
	25, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spi1_default_SUPPORTS_ORDS \
	48, /* /pin-controller/spi1_default/group1 */ \
	103, /* /soc/spi@40004000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spi1_default_EXISTS 1
#define DT_N_NODELABEL_spi1_default DT_N_S_pin_controller_S_spi1_default

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spi1_default_REG_NUM 0
#define DT_N_S_pin_controller_S_spi1_default_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spi1_default_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spi1_default_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spi1_default_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spi1_default_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spi1_default_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/spi1_default/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_spi1_default_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spi1_default_S_group1_PATH "/pin-controller/spi1_default/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spi1_default_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/spi1_default) identifier: */
#define DT_N_S_pin_controller_S_spi1_default_S_group1_PARENT DT_N_S_pin_controller_S_spi1_default

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spi1_default_S_group1_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spi1_default_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_spi1_default_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_spi1_default_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_spi1_default_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spi1_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spi1_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_spi1_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_spi1_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spi1_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spi1_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spi1_default_S_group1_ORD 48
#define DT_N_S_pin_controller_S_spi1_default_S_group1_ORD_STR_SORTABLE 00048

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spi1_default_S_group1_REQUIRES_ORDS \
	47, /* /pin-controller/spi1_default */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spi1_default_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spi1_default_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spi1_default_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_spi1_default_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spi1_default_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spi1_default_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spi1_default_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spi1_default_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spi1_default_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_spi1_default_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_spi1_default_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_default_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_spi1_default_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_default_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_spi1_default_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_default_S_group1_P_low_power_enable 0
#define DT_N_S_pin_controller_S_spi1_default_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_default_S_group1_P_psels {524319 /* 0x8001f */, 655390 /* 0xa001e */, 786472 /* 0xc0028 */}
#define DT_N_S_pin_controller_S_spi1_default_S_group1_P_psels_IDX_0 524319
#define DT_N_S_pin_controller_S_spi1_default_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_default_S_group1_P_psels_IDX_1 655390
#define DT_N_S_pin_controller_S_spi1_default_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_default_S_group1_P_psels_IDX_2 786472
#define DT_N_S_pin_controller_S_spi1_default_S_group1_P_psels_IDX_2_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_spi1_default_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_spi1_default_S_group1, psels, 1) \
	fn(DT_N_S_pin_controller_S_spi1_default_S_group1, psels, 2)
#define DT_N_S_pin_controller_S_spi1_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi1_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi1_default_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi1_default_S_group1, psels, 2)
#define DT_N_S_pin_controller_S_spi1_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi1_default_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi1_default_S_group1, psels, 1, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi1_default_S_group1, psels, 2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi1_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi1_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi1_default_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi1_default_S_group1, psels, 2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi1_default_S_group1_P_psels_LEN 3
#define DT_N_S_pin_controller_S_spi1_default_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_default_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_spi1_default_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_default_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_spi1_default_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/spi1_sleep
 *
 * Node identifier: DT_N_S_pin_controller_S_spi1_sleep
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spi1_sleep_PATH "/pin-controller/spi1_sleep"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spi1_sleep_FULL_NAME "spi1_sleep"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_spi1_sleep_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spi1_sleep_CHILD_IDX 13

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spi1_sleep_CHILD_NUM 1
#define DT_N_S_pin_controller_S_spi1_sleep_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_spi1_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_spi1_sleep_S_group1)
#define DT_N_S_pin_controller_S_spi1_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi1_sleep_S_group1)
#define DT_N_S_pin_controller_S_spi1_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi1_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi1_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi1_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi1_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_spi1_sleep_S_group1)
#define DT_N_S_pin_controller_S_spi1_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi1_sleep_S_group1)
#define DT_N_S_pin_controller_S_spi1_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi1_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi1_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi1_sleep_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spi1_sleep_ORD 49
#define DT_N_S_pin_controller_S_spi1_sleep_ORD_STR_SORTABLE 00049

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spi1_sleep_REQUIRES_ORDS \
	25, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spi1_sleep_SUPPORTS_ORDS \
	50, /* /pin-controller/spi1_sleep/group1 */ \
	103, /* /soc/spi@40004000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spi1_sleep_EXISTS 1
#define DT_N_NODELABEL_spi1_sleep DT_N_S_pin_controller_S_spi1_sleep

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spi1_sleep_REG_NUM 0
#define DT_N_S_pin_controller_S_spi1_sleep_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spi1_sleep_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spi1_sleep_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spi1_sleep_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spi1_sleep_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spi1_sleep_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/spi1_sleep/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_spi1_sleep_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_PATH "/pin-controller/spi1_sleep/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/spi1_sleep) identifier: */
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_PARENT DT_N_S_pin_controller_S_spi1_sleep

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_ORD 50
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_ORD_STR_SORTABLE 00050

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_REQUIRES_ORDS \
	49, /* /pin-controller/spi1_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_P_low_power_enable 1
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_P_psels {524319 /* 0x8001f */, 655390 /* 0xa001e */, 786472 /* 0xc0028 */}
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_P_psels_IDX_0 524319
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_P_psels_IDX_1 655390
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_P_psels_IDX_2 786472
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_P_psels_IDX_2_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_spi1_sleep_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_spi1_sleep_S_group1, psels, 1) \
	fn(DT_N_S_pin_controller_S_spi1_sleep_S_group1, psels, 2)
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi1_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi1_sleep_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi1_sleep_S_group1, psels, 2)
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi1_sleep_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi1_sleep_S_group1, psels, 1, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi1_sleep_S_group1, psels, 2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi1_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi1_sleep_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi1_sleep_S_group1, psels, 2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_P_psels_LEN 3
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_spi1_sleep_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/spi2_default
 *
 * Node identifier: DT_N_S_pin_controller_S_spi2_default
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spi2_default_PATH "/pin-controller/spi2_default"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spi2_default_FULL_NAME "spi2_default"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_spi2_default_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spi2_default_CHILD_IDX 14

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spi2_default_CHILD_NUM 1
#define DT_N_S_pin_controller_S_spi2_default_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_spi2_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_spi2_default_S_group1)
#define DT_N_S_pin_controller_S_spi2_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi2_default_S_group1)
#define DT_N_S_pin_controller_S_spi2_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi2_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi2_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi2_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi2_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_spi2_default_S_group1)
#define DT_N_S_pin_controller_S_spi2_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi2_default_S_group1)
#define DT_N_S_pin_controller_S_spi2_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi2_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi2_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi2_default_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spi2_default_ORD 51
#define DT_N_S_pin_controller_S_spi2_default_ORD_STR_SORTABLE 00051

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spi2_default_REQUIRES_ORDS \
	25, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spi2_default_SUPPORTS_ORDS \
	52, /* /pin-controller/spi2_default/group1 */ \
	104, /* /soc/spi@40023000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spi2_default_EXISTS 1
#define DT_N_NODELABEL_spi2_default DT_N_S_pin_controller_S_spi2_default

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spi2_default_REG_NUM 0
#define DT_N_S_pin_controller_S_spi2_default_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spi2_default_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spi2_default_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spi2_default_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spi2_default_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spi2_default_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/spi2_default/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_spi2_default_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spi2_default_S_group1_PATH "/pin-controller/spi2_default/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spi2_default_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/spi2_default) identifier: */
#define DT_N_S_pin_controller_S_spi2_default_S_group1_PARENT DT_N_S_pin_controller_S_spi2_default

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spi2_default_S_group1_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spi2_default_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_spi2_default_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spi2_default_S_group1_ORD 52
#define DT_N_S_pin_controller_S_spi2_default_S_group1_ORD_STR_SORTABLE 00052

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spi2_default_S_group1_REQUIRES_ORDS \
	51, /* /pin-controller/spi2_default */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spi2_default_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spi2_default_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spi2_default_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_spi2_default_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spi2_default_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spi2_default_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spi2_default_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_low_power_enable 0
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels {524307 /* 0x80013 */, 655380 /* 0xa0014 */, 786453 /* 0xc0015 */}
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_IDX_0 524307
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_IDX_1 655380
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_IDX_2 786453
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_IDX_2_EXISTS 1
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_spi2_default_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_spi2_default_S_group1, psels, 1) \
	fn(DT_N_S_pin_controller_S_spi2_default_S_group1, psels, 2)
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi2_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi2_default_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi2_default_S_group1, psels, 2)
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi2_default_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi2_default_S_group1, psels, 1, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi2_default_S_group1, psels, 2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi2_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi2_default_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi2_default_S_group1, psels, 2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_LEN 3
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/spi2_sleep
 *
 * Node identifier: DT_N_S_pin_controller_S_spi2_sleep
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spi2_sleep_PATH "/pin-controller/spi2_sleep"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spi2_sleep_FULL_NAME "spi2_sleep"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_spi2_sleep_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spi2_sleep_CHILD_IDX 15

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spi2_sleep_CHILD_NUM 1
#define DT_N_S_pin_controller_S_spi2_sleep_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_spi2_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1)
#define DT_N_S_pin_controller_S_spi2_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1)
#define DT_N_S_pin_controller_S_spi2_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi2_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi2_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1)
#define DT_N_S_pin_controller_S_spi2_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1)
#define DT_N_S_pin_controller_S_spi2_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi2_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spi2_sleep_ORD 53
#define DT_N_S_pin_controller_S_spi2_sleep_ORD_STR_SORTABLE 00053

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spi2_sleep_REQUIRES_ORDS \
	25, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spi2_sleep_SUPPORTS_ORDS \
	54, /* /pin-controller/spi2_sleep/group1 */ \
	104, /* /soc/spi@40023000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spi2_sleep_EXISTS 1
#define DT_N_NODELABEL_spi2_sleep DT_N_S_pin_controller_S_spi2_sleep

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spi2_sleep_REG_NUM 0
#define DT_N_S_pin_controller_S_spi2_sleep_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spi2_sleep_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spi2_sleep_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spi2_sleep_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spi2_sleep_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spi2_sleep_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/spi2_sleep/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_spi2_sleep_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_PATH "/pin-controller/spi2_sleep/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/spi2_sleep) identifier: */
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_PARENT DT_N_S_pin_controller_S_spi2_sleep

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_ORD 54
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_ORD_STR_SORTABLE 00054

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_REQUIRES_ORDS \
	53, /* /pin-controller/spi2_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_low_power_enable 1
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels {524307 /* 0x80013 */, 655380 /* 0xa0014 */, 786453 /* 0xc0015 */}
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_IDX_0 524307
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_IDX_1 655380
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_IDX_2 786453
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_IDX_2_EXISTS 1
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, psels, 1) \
	fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, psels, 2)
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, psels, 2)
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, psels, 1, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, psels, 2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, psels, 2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_LEN 3
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/spi3_default
 *
 * Node identifier: DT_N_S_pin_controller_S_spi3_default
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spi3_default_PATH "/pin-controller/spi3_default"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spi3_default_FULL_NAME "spi3_default"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_spi3_default_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spi3_default_CHILD_IDX 18

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spi3_default_CHILD_NUM 1
#define DT_N_S_pin_controller_S_spi3_default_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_spi3_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_spi3_default_S_group1)
#define DT_N_S_pin_controller_S_spi3_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi3_default_S_group1)
#define DT_N_S_pin_controller_S_spi3_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi3_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi3_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi3_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi3_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_spi3_default_S_group1)
#define DT_N_S_pin_controller_S_spi3_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi3_default_S_group1)
#define DT_N_S_pin_controller_S_spi3_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi3_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi3_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi3_default_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spi3_default_ORD 55
#define DT_N_S_pin_controller_S_spi3_default_ORD_STR_SORTABLE 00055

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spi3_default_REQUIRES_ORDS \
	25, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spi3_default_SUPPORTS_ORDS \
	56, /* /pin-controller/spi3_default/group1 */ \
	106, /* /soc/spi@4002f000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spi3_default_EXISTS 1
#define DT_N_NODELABEL_spi3_default DT_N_S_pin_controller_S_spi3_default

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spi3_default_REG_NUM 0
#define DT_N_S_pin_controller_S_spi3_default_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spi3_default_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spi3_default_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spi3_default_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spi3_default_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spi3_default_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/spi3_default/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_spi3_default_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spi3_default_S_group1_PATH "/pin-controller/spi3_default/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spi3_default_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/spi3_default) identifier: */
#define DT_N_S_pin_controller_S_spi3_default_S_group1_PARENT DT_N_S_pin_controller_S_spi3_default

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spi3_default_S_group1_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spi3_default_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_spi3_default_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_spi3_default_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_spi3_default_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spi3_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spi3_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_spi3_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_spi3_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spi3_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spi3_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spi3_default_S_group1_ORD 56
#define DT_N_S_pin_controller_S_spi3_default_S_group1_ORD_STR_SORTABLE 00056

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spi3_default_S_group1_REQUIRES_ORDS \
	55, /* /pin-controller/spi3_default */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spi3_default_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spi3_default_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spi3_default_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_spi3_default_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spi3_default_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spi3_default_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spi3_default_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spi3_default_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spi3_default_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_low_power_enable 0
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels {524335 /* 0x8002f */, 786478 /* 0xc002e */, 655405 /* 0xa002d */}
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_IDX_0 524335
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_IDX_1 786478
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_IDX_2 655405
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_IDX_2_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 1) \
	fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 2)
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 2)
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 1, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi3_default_S_group1, psels, 2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_LEN 3
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_spi3_default_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/spi3_sleep
 *
 * Node identifier: DT_N_S_pin_controller_S_spi3_sleep
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spi3_sleep_PATH "/pin-controller/spi3_sleep"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spi3_sleep_FULL_NAME "spi3_sleep"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_spi3_sleep_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spi3_sleep_CHILD_IDX 19

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spi3_sleep_CHILD_NUM 1
#define DT_N_S_pin_controller_S_spi3_sleep_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_spi3_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1)
#define DT_N_S_pin_controller_S_spi3_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1)
#define DT_N_S_pin_controller_S_spi3_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi3_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi3_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1)
#define DT_N_S_pin_controller_S_spi3_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1)
#define DT_N_S_pin_controller_S_spi3_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi3_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spi3_sleep_ORD 57
#define DT_N_S_pin_controller_S_spi3_sleep_ORD_STR_SORTABLE 00057

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spi3_sleep_REQUIRES_ORDS \
	25, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spi3_sleep_SUPPORTS_ORDS \
	58, /* /pin-controller/spi3_sleep/group1 */ \
	106, /* /soc/spi@4002f000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spi3_sleep_EXISTS 1
#define DT_N_NODELABEL_spi3_sleep DT_N_S_pin_controller_S_spi3_sleep

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spi3_sleep_REG_NUM 0
#define DT_N_S_pin_controller_S_spi3_sleep_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spi3_sleep_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spi3_sleep_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spi3_sleep_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spi3_sleep_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spi3_sleep_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/spi3_sleep/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_spi3_sleep_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_PATH "/pin-controller/spi3_sleep/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/spi3_sleep) identifier: */
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_PARENT DT_N_S_pin_controller_S_spi3_sleep

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_ORD 58
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_ORD_STR_SORTABLE 00058

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_REQUIRES_ORDS \
	57, /* /pin-controller/spi3_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_low_power_enable 1
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels {524335 /* 0x8002f */, 786478 /* 0xc002e */, 655405 /* 0xa002d */}
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_IDX_0 524335
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_IDX_1 786478
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_IDX_2 655405
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_IDX_2_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 1) \
	fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 2)
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 2)
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 1, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, psels, 2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_LEN 3
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_spi3_sleep_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/uart0_default
 *
 * Node identifier: DT_N_S_pin_controller_S_uart0_default
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_uart0_default_PATH "/pin-controller/uart0_default"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_uart0_default_FULL_NAME "uart0_default"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_uart0_default_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_uart0_default_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_uart0_default_CHILD_NUM 2
#define DT_N_S_pin_controller_S_uart0_default_CHILD_NUM_STATUS_OKAY 2
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_uart0_default_S_group1) fn(DT_N_S_pin_controller_S_uart0_default_S_group2)
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_default_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_default_S_group2)
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_default_S_group2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_uart0_default_S_group1) fn(DT_N_S_pin_controller_S_uart0_default_S_group2)
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_default_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_default_S_group2)
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_default_S_group2, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_uart0_default_ORD 59
#define DT_N_S_pin_controller_S_uart0_default_ORD_STR_SORTABLE 00059

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_uart0_default_REQUIRES_ORDS \
	25, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_uart0_default_SUPPORTS_ORDS \
	60, /* /pin-controller/uart0_default/group1 */ \
	61, /* /pin-controller/uart0_default/group2 */ \
	113, /* /soc/uart@40002000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_uart0_default_EXISTS 1
#define DT_N_NODELABEL_uart0_default DT_N_S_pin_controller_S_uart0_default

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_uart0_default_REG_NUM 0
#define DT_N_S_pin_controller_S_uart0_default_RANGES_NUM 0
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_uart0_default_IRQ_NUM 0
#define DT_N_S_pin_controller_S_uart0_default_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_uart0_default_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_uart0_default_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/uart0_default/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_uart0_default_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_PATH "/pin-controller/uart0_default/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/uart0_default) identifier: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_PARENT DT_N_S_pin_controller_S_uart0_default

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_ORD 60
#define DT_N_S_pin_controller_S_uart0_default_S_group1_ORD_STR_SORTABLE 00060

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_REQUIRES_ORDS \
	59, /* /pin-controller/uart0_default */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_low_power_enable 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels {6 /* 0x6 */, 262149 /* 0x40005 */}
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_IDX_0 6
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_IDX_1 262149
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 1)
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 1)
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_LEN 2
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/uart0_default/group2
 *
 * Node identifier: DT_N_S_pin_controller_S_uart0_default_S_group2
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_uart0_default_S_group2_PATH "/pin-controller/uart0_default/group2"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FULL_NAME "group2"

/* Node parent (/pin-controller/uart0_default) identifier: */
#define DT_N_S_pin_controller_S_uart0_default_S_group2_PARENT DT_N_S_pin_controller_S_uart0_default

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_uart0_default_S_group2_CHILD_IDX 1

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_uart0_default_S_group2_CHILD_NUM 0
#define DT_N_S_pin_controller_S_uart0_default_S_group2_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_uart0_default_S_group2_ORD 61
#define DT_N_S_pin_controller_S_uart0_default_S_group2_ORD_STR_SORTABLE 00061

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_uart0_default_S_group2_REQUIRES_ORDS \
	59, /* /pin-controller/uart0_default */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_uart0_default_S_group2_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_uart0_default_S_group2_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_uart0_default_S_group2_REG_NUM 0
#define DT_N_S_pin_controller_S_uart0_default_S_group2_RANGES_NUM 0
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_IRQ_NUM 0
#define DT_N_S_pin_controller_S_uart0_default_S_group2_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_uart0_default_S_group2_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_uart0_default_S_group2_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_disable 0
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_pull_up 1
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_low_power_enable 0
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels {131080 /* 0x20008 */, 393223 /* 0x60007 */}
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_IDX_0 131080
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_IDX_1 393223
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 0) \
	fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 1)
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 1)
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_LEN 2
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_nordic_invert 0
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/uart0_sleep
 *
 * Node identifier: DT_N_S_pin_controller_S_uart0_sleep
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_uart0_sleep_PATH "/pin-controller/uart0_sleep"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_uart0_sleep_FULL_NAME "uart0_sleep"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_uart0_sleep_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_uart0_sleep_CHILD_IDX 1

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_uart0_sleep_CHILD_NUM 1
#define DT_N_S_pin_controller_S_uart0_sleep_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1)
#define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1)
#define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1)
#define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1)
#define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_uart0_sleep_ORD 62
#define DT_N_S_pin_controller_S_uart0_sleep_ORD_STR_SORTABLE 00062

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_uart0_sleep_REQUIRES_ORDS \
	25, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_uart0_sleep_SUPPORTS_ORDS \
	63, /* /pin-controller/uart0_sleep/group1 */ \
	113, /* /soc/uart@40002000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_uart0_sleep_EXISTS 1
#define DT_N_NODELABEL_uart0_sleep DT_N_S_pin_controller_S_uart0_sleep

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_uart0_sleep_REG_NUM 0
#define DT_N_S_pin_controller_S_uart0_sleep_RANGES_NUM 0
#define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_uart0_sleep_IRQ_NUM 0
#define DT_N_S_pin_controller_S_uart0_sleep_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_uart0_sleep_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_uart0_sleep_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/uart0_sleep/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_uart0_sleep_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_PATH "/pin-controller/uart0_sleep/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/uart0_sleep) identifier: */
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_PARENT DT_N_S_pin_controller_S_uart0_sleep

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_ORD 63
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_ORD_STR_SORTABLE 00063

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_REQUIRES_ORDS \
	62, /* /pin-controller/uart0_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_low_power_enable 1
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels {6 /* 0x6 */, 131080 /* 0x20008 */, 262149 /* 0x40005 */, 393223 /* 0x60007 */}
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_0 6
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_1 131080
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_2 262149
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_2_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_3 393223
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_3_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 1) \
	fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 2) \
	fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 3)
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 3)
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 1, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 2, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 3, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 3, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_LEN 4
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/uart1_default
 *
 * Node identifier: DT_N_S_pin_controller_S_uart1_default
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_uart1_default_PATH "/pin-controller/uart1_default"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_uart1_default_FULL_NAME "uart1_default"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_uart1_default_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_uart1_default_CHILD_IDX 2

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_uart1_default_CHILD_NUM 2
#define DT_N_S_pin_controller_S_uart1_default_CHILD_NUM_STATUS_OKAY 2
#define DT_N_S_pin_controller_S_uart1_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_uart1_default_S_group1) fn(DT_N_S_pin_controller_S_uart1_default_S_group2)
#define DT_N_S_pin_controller_S_uart1_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart1_default_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_default_S_group2)
#define DT_N_S_pin_controller_S_uart1_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default_S_group2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart1_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_default_S_group2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart1_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_uart1_default_S_group1) fn(DT_N_S_pin_controller_S_uart1_default_S_group2)
#define DT_N_S_pin_controller_S_uart1_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart1_default_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_default_S_group2)
#define DT_N_S_pin_controller_S_uart1_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default_S_group2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart1_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart1_default_S_group2, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_uart1_default_ORD 64
#define DT_N_S_pin_controller_S_uart1_default_ORD_STR_SORTABLE 00064

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_uart1_default_REQUIRES_ORDS \
	25, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_uart1_default_SUPPORTS_ORDS \
	65, /* /pin-controller/uart1_default/group1 */ \
	66, /* /pin-controller/uart1_default/group2 */ \
	114, /* /soc/uart@40028000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_uart1_default_EXISTS 1
#define DT_N_NODELABEL_uart1_default DT_N_S_pin_controller_S_uart1_default

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_uart1_default_REG_NUM 0
#define DT_N_S_pin_controller_S_uart1_default_RANGES_NUM 0
#define DT_N_S_pin_controller_S_uart1_default_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_uart1_default_IRQ_NUM 0
#define DT_N_S_pin_controller_S_uart1_default_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_uart1_default_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_uart1_default_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/uart1_default/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_uart1_default_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_uart1_default_S_group1_PATH "/pin-controller/uart1_default/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_uart1_default_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/uart1_default) identifier: */
#define DT_N_S_pin_controller_S_uart1_default_S_group1_PARENT DT_N_S_pin_controller_S_uart1_default

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_uart1_default_S_group1_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_uart1_default_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_uart1_default_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_uart1_default_S_group1_ORD 65
#define DT_N_S_pin_controller_S_uart1_default_S_group1_ORD_STR_SORTABLE 00065

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_uart1_default_S_group1_REQUIRES_ORDS \
	64, /* /pin-controller/uart1_default */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_uart1_default_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_uart1_default_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_uart1_default_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_uart1_default_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_uart1_default_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_uart1_default_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_uart1_default_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_uart1_default_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_uart1_default_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_uart1_default_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_uart1_default_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_uart1_default_S_group1_P_bias_pull_up 1
#define DT_N_S_pin_controller_S_uart1_default_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_uart1_default_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_uart1_default_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_uart1_default_S_group1_P_low_power_enable 0
#define DT_N_S_pin_controller_S_uart1_default_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels {131105 /* 0x20021 */}
#define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_IDX_0 131105
#define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, psels, 0)
#define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, psels, 0)
#define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, psels, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, psels, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_LEN 1
#define DT_N_S_pin_controller_S_uart1_default_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_uart1_default_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_uart1_default_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_uart1_default_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_uart1_default_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/uart1_default/group2
 *
 * Node identifier: DT_N_S_pin_controller_S_uart1_default_S_group2
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_uart1_default_S_group2_PATH "/pin-controller/uart1_default/group2"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_uart1_default_S_group2_FULL_NAME "group2"

/* Node parent (/pin-controller/uart1_default) identifier: */
#define DT_N_S_pin_controller_S_uart1_default_S_group2_PARENT DT_N_S_pin_controller_S_uart1_default

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_uart1_default_S_group2_CHILD_IDX 1

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_uart1_default_S_group2_CHILD_NUM 0
#define DT_N_S_pin_controller_S_uart1_default_S_group2_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_uart1_default_S_group2_ORD 66
#define DT_N_S_pin_controller_S_uart1_default_S_group2_ORD_STR_SORTABLE 00066

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_uart1_default_S_group2_REQUIRES_ORDS \
	64, /* /pin-controller/uart1_default */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_uart1_default_S_group2_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_uart1_default_S_group2_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_uart1_default_S_group2_REG_NUM 0
#define DT_N_S_pin_controller_S_uart1_default_S_group2_RANGES_NUM 0
#define DT_N_S_pin_controller_S_uart1_default_S_group2_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_uart1_default_S_group2_IRQ_NUM 0
#define DT_N_S_pin_controller_S_uart1_default_S_group2_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_uart1_default_S_group2_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_uart1_default_S_group2_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_uart1_default_S_group2_P_bias_disable 0
#define DT_N_S_pin_controller_S_uart1_default_S_group2_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_uart1_default_S_group2_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_uart1_default_S_group2_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_uart1_default_S_group2_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_uart1_default_S_group2_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_uart1_default_S_group2_P_low_power_enable 0
#define DT_N_S_pin_controller_S_uart1_default_S_group2_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels {34 /* 0x22 */}
#define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_IDX_0 34
#define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart1_default_S_group2, psels, 0)
#define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart1_default_S_group2, psels, 0)
#define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart1_default_S_group2, psels, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart1_default_S_group2, psels, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_LEN 1
#define DT_N_S_pin_controller_S_uart1_default_S_group2_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_uart1_default_S_group2_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_uart1_default_S_group2_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_uart1_default_S_group2_P_nordic_invert 0
#define DT_N_S_pin_controller_S_uart1_default_S_group2_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /pin-controller/uart1_sleep
 *
 * Node identifier: DT_N_S_pin_controller_S_uart1_sleep
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_uart1_sleep_PATH "/pin-controller/uart1_sleep"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_uart1_sleep_FULL_NAME "uart1_sleep"

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_uart1_sleep_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_uart1_sleep_CHILD_IDX 3

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_uart1_sleep_CHILD_NUM 1
#define DT_N_S_pin_controller_S_uart1_sleep_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1)
#define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1)
#define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1)
#define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1)
#define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_uart1_sleep_ORD 67
#define DT_N_S_pin_controller_S_uart1_sleep_ORD_STR_SORTABLE 00067

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_uart1_sleep_REQUIRES_ORDS \
	25, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_uart1_sleep_SUPPORTS_ORDS \
	68, /* /pin-controller/uart1_sleep/group1 */ \
	114, /* /soc/uart@40028000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_uart1_sleep_EXISTS 1
#define DT_N_NODELABEL_uart1_sleep DT_N_S_pin_controller_S_uart1_sleep

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_uart1_sleep_REG_NUM 0
#define DT_N_S_pin_controller_S_uart1_sleep_RANGES_NUM 0
#define DT_N_S_pin_controller_S_uart1_sleep_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_uart1_sleep_IRQ_NUM 0
#define DT_N_S_pin_controller_S_uart1_sleep_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_uart1_sleep_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_uart1_sleep_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/uart1_sleep/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_uart1_sleep_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_PATH "/pin-controller/uart1_sleep/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FULL_NAME "group1"

/* Node parent (/pin-controller/uart1_sleep) identifier: */
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_PARENT DT_N_S_pin_controller_S_uart1_sleep

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_ORD 68
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_ORD_STR_SORTABLE 00068

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_REQUIRES_ORDS \
	67, /* /pin-controller/uart1_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_low_power_enable 1
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_low_power_enable_EXISTS 1
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels {131105 /* 0x20021 */, 34 /* 0x22 */}
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_IDX_0 131105
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_IDX_1 34
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 0) \
	fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 1)
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 1)
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, psels, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_LEN 2
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_psels_EXISTS 1
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_nordic_drive_mode 0
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_nordic_drive_mode_EXISTS 1
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_nordic_invert 0
#define DT_N_S_pin_controller_S_uart1_sleep_S_group1_P_nordic_invert_EXISTS 1

/*
 * Devicetree node: /soc/pwm@4001c000
 *
 * Node identifier: DT_N_S_soc_S_pwm_4001c000
 *
 * Binding (compatible = nordic,nrf-pwm):
 *   $ZEPHYR_BASE/dts/bindings/pwm/nordic,nrf-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pwm_4001c000_PATH "/soc/pwm@4001c000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pwm_4001c000_FULL_NAME "pwm@4001c000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_pwm_4001c000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pwm_4001c000_CHILD_IDX 36

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pwm_4001c000_CHILD_NUM 0
#define DT_N_S_soc_S_pwm_4001c000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pwm_4001c000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pwm_4001c000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pwm_4001c000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pwm_4001c000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pwm_4001c000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pwm_4001c000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pwm_4001c000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pwm_4001c000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pwm_4001c000_ORD 69
#define DT_N_S_soc_S_pwm_4001c000_ORD_STR_SORTABLE 00069

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pwm_4001c000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */ \
	34, /* /pin-controller/pwm0_default */ \
	36, /* /pin-controller/pwm0_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pwm_4001c000_SUPPORTS_ORDS \
	70, /* /pwmleds */ \
	71, /* /pwmleds/pwm_led_0 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pwm_4001c000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_pwm DT_N_S_soc_S_pwm_4001c000
#define DT_N_NODELABEL_pwm0        DT_N_S_soc_S_pwm_4001c000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pwm_4001c000_REG_NUM 1
#define DT_N_S_soc_S_pwm_4001c000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_4001c000_REG_IDX_0_VAL_ADDRESS 1073856512 /* 0x4001c000 */
#define DT_N_S_soc_S_pwm_4001c000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_pwm_4001c000_RANGES_NUM 0
#define DT_N_S_soc_S_pwm_4001c000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pwm_4001c000_IRQ_NUM 1
#define DT_N_S_soc_S_pwm_4001c000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_4001c000_IRQ_IDX_0_VAL_irq 28
#define DT_N_S_soc_S_pwm_4001c000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_pwm_4001c000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_4001c000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_pwm_4001c000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_pwm_4001c000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_pwm_4001c000_IRQ_LEVEL 1
#define DT_N_S_soc_S_pwm_4001c000_COMPAT_MATCHES_nordic_nrf_pwm 1
#define DT_N_S_soc_S_pwm_4001c000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_4001c000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_pwm_4001c000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_4001c000_COMPAT_MODEL_IDX_0 "nrf-pwm"
#define DT_N_S_soc_S_pwm_4001c000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pwm_4001c000_PINCTRL_NUM 2
#define DT_N_S_soc_S_pwm_4001c000_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_4001c000_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_pwm_4001c000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_pwm_4001c000_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_pwm_4001c000_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_pwm_4001c000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_pwm0_default
#define DT_N_S_soc_S_pwm_4001c000_PINCTRL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pwm_4001c000_PINCTRL_IDX_1_TOKEN sleep
#define DT_N_S_soc_S_pwm_4001c000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP
#define DT_N_S_soc_S_pwm_4001c000_PINCTRL_NAME_sleep_EXISTS 1
#define DT_N_S_soc_S_pwm_4001c000_PINCTRL_NAME_sleep_IDX 1
#define DT_N_S_soc_S_pwm_4001c000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_pwm0_sleep

/* Generic property macros: */
#define DT_N_S_soc_S_pwm_4001c000_P_wakeup_source 0
#define DT_N_S_soc_S_pwm_4001c000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_pwm_4001c000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_pwm_4001c000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_pwm_4001c000_P_status "okay"
#define DT_N_S_soc_S_pwm_4001c000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_pwm_4001c000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_pwm_4001c000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_pwm_4001c000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_pwm_4001c000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_4001c000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_pwm_4001c000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_pwm_4001c000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_pwm_4001c000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_pwm_4001c000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pwm_4001c000, status, 0)
#define DT_N_S_soc_S_pwm_4001c000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pwm_4001c000, status, 0)
#define DT_N_S_soc_S_pwm_4001c000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pwm_4001c000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pwm_4001c000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pwm_4001c000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pwm_4001c000_P_status_LEN 1
#define DT_N_S_soc_S_pwm_4001c000_P_status_EXISTS 1
#define DT_N_S_soc_S_pwm_4001c000_P_compatible {"nordic,nrf-pwm"}
#define DT_N_S_soc_S_pwm_4001c000_P_compatible_IDX_0 "nordic,nrf-pwm"
#define DT_N_S_soc_S_pwm_4001c000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pwm
#define DT_N_S_soc_S_pwm_4001c000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pwm
#define DT_N_S_soc_S_pwm_4001c000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PWM
#define DT_N_S_soc_S_pwm_4001c000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_4001c000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pwm_4001c000, compatible, 0)
#define DT_N_S_soc_S_pwm_4001c000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pwm_4001c000, compatible, 0)
#define DT_N_S_soc_S_pwm_4001c000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pwm_4001c000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pwm_4001c000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pwm_4001c000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pwm_4001c000_P_compatible_LEN 1
#define DT_N_S_soc_S_pwm_4001c000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_pwm_4001c000_P_reg {1073856512 /* 0x4001c000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_pwm_4001c000_P_reg_IDX_0 1073856512
#define DT_N_S_soc_S_pwm_4001c000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_4001c000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_pwm_4001c000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pwm_4001c000_P_reg_EXISTS 1
#define DT_N_S_soc_S_pwm_4001c000_P_interrupts {28 /* 0x1c */, 1 /* 0x1 */}
#define DT_N_S_soc_S_pwm_4001c000_P_interrupts_IDX_0 28
#define DT_N_S_soc_S_pwm_4001c000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_4001c000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_pwm_4001c000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pwm_4001c000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_pwm_4001c000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_pwm_4001c000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_pwm0_default
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_pwm0_default
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pwm_4001c000, pinctrl_0, 0)
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pwm_4001c000, pinctrl_0, 0)
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pwm_4001c000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pwm_4001c000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_0_LEN 1
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_pwm0_sleep
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_pwm0_sleep
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_1_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pwm_4001c000, pinctrl_1, 0)
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pwm_4001c000, pinctrl_1, 0)
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pwm_4001c000, pinctrl_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pwm_4001c000, pinctrl_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_1_LEN 1
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_1_EXISTS 1
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_names {"default", "sleep"}
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_names_IDX_1 "sleep"
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pwm_4001c000, pinctrl_names, 0) \
	fn(DT_N_S_soc_S_pwm_4001c000, pinctrl_names, 1)
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pwm_4001c000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_pwm_4001c000, pinctrl_names, 1)
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pwm_4001c000, pinctrl_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_pwm_4001c000, pinctrl_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pwm_4001c000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_pwm_4001c000, pinctrl_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_names_LEN 2
#define DT_N_S_soc_S_pwm_4001c000_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_pwm_4001c000_P_center_aligned 0
#define DT_N_S_soc_S_pwm_4001c000_P_center_aligned_EXISTS 1

/*
 * Devicetree node: /pwmleds
 *
 * Node identifier: DT_N_S_pwmleds
 *
 * Binding (compatible = pwm-leds):
 *   $ZEPHYR_BASE/dts/bindings/led/pwm-leds.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pwmleds_PATH "/pwmleds"

/* Node's name with unit-address: */
#define DT_N_S_pwmleds_FULL_NAME "pwmleds"

/* Node parent (/) identifier: */
#define DT_N_S_pwmleds_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_pwmleds_CHILD_IDX 8

/* Helper macros for child nodes of this node. */
#define DT_N_S_pwmleds_CHILD_NUM 1
#define DT_N_S_pwmleds_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pwmleds_FOREACH_CHILD(fn) fn(DT_N_S_pwmleds_S_pwm_led_0)
#define DT_N_S_pwmleds_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pwmleds_S_pwm_led_0)
#define DT_N_S_pwmleds_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pwmleds_S_pwm_led_0, __VA_ARGS__)
#define DT_N_S_pwmleds_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pwmleds_S_pwm_led_0, __VA_ARGS__)
#define DT_N_S_pwmleds_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pwmleds_S_pwm_led_0)
#define DT_N_S_pwmleds_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pwmleds_S_pwm_led_0)
#define DT_N_S_pwmleds_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pwmleds_S_pwm_led_0, __VA_ARGS__)
#define DT_N_S_pwmleds_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pwmleds_S_pwm_led_0, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_pwmleds_ORD 70
#define DT_N_S_pwmleds_ORD_STR_SORTABLE 00070

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pwmleds_REQUIRES_ORDS \
	0, /* / */ \
	69, /* /soc/pwm@4001c000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pwmleds_SUPPORTS_ORDS \
	71, /* /pwmleds/pwm_led_0 */

/* Existence and alternate IDs: */
#define DT_N_S_pwmleds_EXISTS 1
#define DT_N_INST_0_pwm_leds DT_N_S_pwmleds

/* Macros for properties that are special in the specification: */
#define DT_N_S_pwmleds_REG_NUM 0
#define DT_N_S_pwmleds_RANGES_NUM 0
#define DT_N_S_pwmleds_FOREACH_RANGE(fn) 
#define DT_N_S_pwmleds_IRQ_NUM 0
#define DT_N_S_pwmleds_IRQ_LEVEL 0
#define DT_N_S_pwmleds_COMPAT_MATCHES_pwm_leds 1
#define DT_N_S_pwmleds_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pwmleds_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pwmleds_P_compatible {"pwm-leds"}
#define DT_N_S_pwmleds_P_compatible_IDX_0 "pwm-leds"
#define DT_N_S_pwmleds_P_compatible_IDX_0_STRING_UNQUOTED pwm-leds
#define DT_N_S_pwmleds_P_compatible_IDX_0_STRING_TOKEN pwm_leds
#define DT_N_S_pwmleds_P_compatible_IDX_0_STRING_UPPER_TOKEN PWM_LEDS
#define DT_N_S_pwmleds_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_pwmleds_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pwmleds, compatible, 0)
#define DT_N_S_pwmleds_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pwmleds, compatible, 0)
#define DT_N_S_pwmleds_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pwmleds, compatible, 0, __VA_ARGS__)
#define DT_N_S_pwmleds_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pwmleds, compatible, 0, __VA_ARGS__)
#define DT_N_S_pwmleds_P_compatible_LEN 1
#define DT_N_S_pwmleds_P_compatible_EXISTS 1

/*
 * Devicetree node: /pwmleds/pwm_led_0
 *
 * Node identifier: DT_N_S_pwmleds_S_pwm_led_0
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pwmleds_S_pwm_led_0_PATH "/pwmleds/pwm_led_0"

/* Node's name with unit-address: */
#define DT_N_S_pwmleds_S_pwm_led_0_FULL_NAME "pwm_led_0"

/* Node parent (/pwmleds) identifier: */
#define DT_N_S_pwmleds_S_pwm_led_0_PARENT DT_N_S_pwmleds

/* Node's index in its parent's list of children: */
#define DT_N_S_pwmleds_S_pwm_led_0_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_pwmleds_S_pwm_led_0_CHILD_NUM 0
#define DT_N_S_pwmleds_S_pwm_led_0_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_CHILD(fn) 
#define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_pwmleds_S_pwm_led_0_ORD 71
#define DT_N_S_pwmleds_S_pwm_led_0_ORD_STR_SORTABLE 00071

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pwmleds_S_pwm_led_0_REQUIRES_ORDS \
	69, /* /soc/pwm@4001c000 */ \
	70, /* /pwmleds */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pwmleds_S_pwm_led_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pwmleds_S_pwm_led_0_EXISTS 1
#define DT_N_ALIAS_pwm_led0     DT_N_S_pwmleds_S_pwm_led_0
#define DT_N_NODELABEL_pwm_led0 DT_N_S_pwmleds_S_pwm_led_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_pwmleds_S_pwm_led_0_REG_NUM 0
#define DT_N_S_pwmleds_S_pwm_led_0_RANGES_NUM 0
#define DT_N_S_pwmleds_S_pwm_led_0_FOREACH_RANGE(fn) 
#define DT_N_S_pwmleds_S_pwm_led_0_IRQ_NUM 0
#define DT_N_S_pwmleds_S_pwm_led_0_IRQ_LEVEL 0
#define DT_N_S_pwmleds_S_pwm_led_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pwmleds_S_pwm_led_0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_IDX_0_EXISTS 1
#define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_IDX_0_PH DT_N_S_soc_S_pwm_4001c000
#define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_IDX_0_VAL_channel 0
#define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_IDX_0_VAL_channel_EXISTS 1
#define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_IDX_0_VAL_period 20000000
#define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_IDX_0_VAL_period_EXISTS 1
#define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_IDX_0_VAL_flags 1
#define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pwmleds_S_pwm_led_0, pwms, 0)
#define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pwmleds_S_pwm_led_0, pwms, 0)
#define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pwmleds_S_pwm_led_0, pwms, 0, __VA_ARGS__)
#define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pwmleds_S_pwm_led_0, pwms, 0, __VA_ARGS__)
#define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_LEN 1
#define DT_N_S_pwmleds_S_pwm_led_0_P_pwms_EXISTS 1

/*
 * Devicetree node: /soc/acl@4001e000
 *
 * Node identifier: DT_N_S_soc_S_acl_4001e000
 *
 * Binding (compatible = nordic,nrf-acl):
 *   $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-acl.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_acl_4001e000_PATH "/soc/acl@4001e000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_acl_4001e000_FULL_NAME "acl@4001e000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_acl_4001e000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_acl_4001e000_CHILD_IDX 38

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_acl_4001e000_CHILD_NUM 0
#define DT_N_S_soc_S_acl_4001e000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_acl_4001e000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_acl_4001e000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_acl_4001e000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_acl_4001e000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_acl_4001e000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_acl_4001e000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_acl_4001e000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_acl_4001e000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_acl_4001e000_ORD 72
#define DT_N_S_soc_S_acl_4001e000_ORD_STR_SORTABLE 00072

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_acl_4001e000_REQUIRES_ORDS \
	6, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_acl_4001e000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_acl_4001e000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_acl DT_N_S_soc_S_acl_4001e000
#define DT_N_NODELABEL_acl         DT_N_S_soc_S_acl_4001e000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_acl_4001e000_REG_NUM 1
#define DT_N_S_soc_S_acl_4001e000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_acl_4001e000_REG_IDX_0_VAL_ADDRESS 1073864704 /* 0x4001e000 */
#define DT_N_S_soc_S_acl_4001e000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_acl_4001e000_RANGES_NUM 0
#define DT_N_S_soc_S_acl_4001e000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_acl_4001e000_IRQ_NUM 0
#define DT_N_S_soc_S_acl_4001e000_IRQ_LEVEL 0
#define DT_N_S_soc_S_acl_4001e000_COMPAT_MATCHES_nordic_nrf_acl 1
#define DT_N_S_soc_S_acl_4001e000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_acl_4001e000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_acl_4001e000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_acl_4001e000_COMPAT_MODEL_IDX_0 "nrf-acl"
#define DT_N_S_soc_S_acl_4001e000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_acl_4001e000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_acl_4001e000_P_wakeup_source 0
#define DT_N_S_soc_S_acl_4001e000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_acl_4001e000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_acl_4001e000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_acl_4001e000_P_status "okay"
#define DT_N_S_soc_S_acl_4001e000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_acl_4001e000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_acl_4001e000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_acl_4001e000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_acl_4001e000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_acl_4001e000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_acl_4001e000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_acl_4001e000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_acl_4001e000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_acl_4001e000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_acl_4001e000, status, 0)
#define DT_N_S_soc_S_acl_4001e000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_acl_4001e000, status, 0)
#define DT_N_S_soc_S_acl_4001e000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_acl_4001e000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_acl_4001e000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_acl_4001e000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_acl_4001e000_P_status_LEN 1
#define DT_N_S_soc_S_acl_4001e000_P_status_EXISTS 1
#define DT_N_S_soc_S_acl_4001e000_P_compatible {"nordic,nrf-acl"}
#define DT_N_S_soc_S_acl_4001e000_P_compatible_IDX_0 "nordic,nrf-acl"
#define DT_N_S_soc_S_acl_4001e000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-acl
#define DT_N_S_soc_S_acl_4001e000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_acl
#define DT_N_S_soc_S_acl_4001e000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_ACL
#define DT_N_S_soc_S_acl_4001e000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_acl_4001e000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_acl_4001e000, compatible, 0)
#define DT_N_S_soc_S_acl_4001e000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_acl_4001e000, compatible, 0)
#define DT_N_S_soc_S_acl_4001e000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_acl_4001e000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_acl_4001e000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_acl_4001e000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_acl_4001e000_P_compatible_LEN 1
#define DT_N_S_soc_S_acl_4001e000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_acl_4001e000_P_reg {1073864704 /* 0x4001e000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_acl_4001e000_P_reg_IDX_0 1073864704
#define DT_N_S_soc_S_acl_4001e000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_acl_4001e000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_acl_4001e000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_acl_4001e000_P_reg_EXISTS 1
#define DT_N_S_soc_S_acl_4001e000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_acl_4001e000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/adc@40007000
 *
 * Node identifier: DT_N_S_soc_S_adc_40007000
 *
 * Binding (compatible = nordic,nrf-saadc):
 *   $ZEPHYR_BASE/dts/bindings/adc/nordic,nrf-saadc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_adc_40007000_PATH "/soc/adc@40007000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_adc_40007000_FULL_NAME "adc@40007000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_adc_40007000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_adc_40007000_CHILD_IDX 15

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_adc_40007000_CHILD_NUM 0
#define DT_N_S_soc_S_adc_40007000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_adc_40007000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_adc_40007000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_adc_40007000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_adc_40007000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_adc_40007000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_adc_40007000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_adc_40007000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_adc_40007000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_adc_40007000_ORD 73
#define DT_N_S_soc_S_adc_40007000_ORD_STR_SORTABLE 00073

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_adc_40007000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_adc_40007000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_adc_40007000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_saadc DT_N_S_soc_S_adc_40007000
#define DT_N_NODELABEL_adc           DT_N_S_soc_S_adc_40007000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_adc_40007000_REG_NUM 1
#define DT_N_S_soc_S_adc_40007000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40007000_REG_IDX_0_VAL_ADDRESS 1073770496 /* 0x40007000 */
#define DT_N_S_soc_S_adc_40007000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_adc_40007000_RANGES_NUM 0
#define DT_N_S_soc_S_adc_40007000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_adc_40007000_IRQ_NUM 1
#define DT_N_S_soc_S_adc_40007000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40007000_IRQ_IDX_0_VAL_irq 7
#define DT_N_S_soc_S_adc_40007000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_adc_40007000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40007000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_adc_40007000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_adc_40007000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_adc_40007000_IRQ_LEVEL 1
#define DT_N_S_soc_S_adc_40007000_COMPAT_MATCHES_nordic_nrf_saadc 1
#define DT_N_S_soc_S_adc_40007000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40007000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_adc_40007000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40007000_COMPAT_MODEL_IDX_0 "nrf-saadc"
#define DT_N_S_soc_S_adc_40007000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_adc_40007000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_adc_40007000_P_wakeup_source 0
#define DT_N_S_soc_S_adc_40007000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_adc_40007000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_adc_40007000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_adc_40007000_P_status "okay"
#define DT_N_S_soc_S_adc_40007000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_adc_40007000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_adc_40007000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_adc_40007000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_adc_40007000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40007000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_adc_40007000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_adc_40007000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_adc_40007000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_adc_40007000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40007000, status, 0)
#define DT_N_S_soc_S_adc_40007000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40007000, status, 0)
#define DT_N_S_soc_S_adc_40007000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40007000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40007000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40007000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40007000_P_status_LEN 1
#define DT_N_S_soc_S_adc_40007000_P_status_EXISTS 1
#define DT_N_S_soc_S_adc_40007000_P_compatible {"nordic,nrf-saadc"}
#define DT_N_S_soc_S_adc_40007000_P_compatible_IDX_0 "nordic,nrf-saadc"
#define DT_N_S_soc_S_adc_40007000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-saadc
#define DT_N_S_soc_S_adc_40007000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_saadc
#define DT_N_S_soc_S_adc_40007000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SAADC
#define DT_N_S_soc_S_adc_40007000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40007000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40007000, compatible, 0)
#define DT_N_S_soc_S_adc_40007000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40007000, compatible, 0)
#define DT_N_S_soc_S_adc_40007000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40007000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40007000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40007000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_40007000_P_compatible_LEN 1
#define DT_N_S_soc_S_adc_40007000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_adc_40007000_P_reg {1073770496 /* 0x40007000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_adc_40007000_P_reg_IDX_0 1073770496
#define DT_N_S_soc_S_adc_40007000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40007000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_adc_40007000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_40007000_P_reg_EXISTS 1
#define DT_N_S_soc_S_adc_40007000_P_interrupts {7 /* 0x7 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_adc_40007000_P_interrupts_IDX_0 7
#define DT_N_S_soc_S_adc_40007000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_40007000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_adc_40007000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_40007000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_adc_40007000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_adc_40007000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/ccm@4000f000
 *
 * Node identifier: DT_N_S_soc_S_ccm_4000f000
 *
 * Binding (compatible = nordic,nrf-ccm):
 *   $ZEPHYR_BASE/dts/bindings/crypto/nordic,nrf-ccm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_ccm_4000f000_PATH "/soc/ccm@4000f000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_ccm_4000f000_FULL_NAME "ccm@4000f000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_ccm_4000f000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_ccm_4000f000_CHILD_IDX 23

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_ccm_4000f000_CHILD_NUM 0
#define DT_N_S_soc_S_ccm_4000f000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_ccm_4000f000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_ccm_4000f000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_ccm_4000f000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_ccm_4000f000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_ccm_4000f000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_ccm_4000f000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_ccm_4000f000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_ccm_4000f000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_ccm_4000f000_ORD 74
#define DT_N_S_soc_S_ccm_4000f000_ORD_STR_SORTABLE 00074

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_ccm_4000f000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_ccm_4000f000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_ccm_4000f000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_ccm DT_N_S_soc_S_ccm_4000f000
#define DT_N_NODELABEL_ccm         DT_N_S_soc_S_ccm_4000f000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_ccm_4000f000_REG_NUM 1
#define DT_N_S_soc_S_ccm_4000f000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ccm_4000f000_REG_IDX_0_VAL_ADDRESS 1073803264 /* 0x4000f000 */
#define DT_N_S_soc_S_ccm_4000f000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_ccm_4000f000_RANGES_NUM 0
#define DT_N_S_soc_S_ccm_4000f000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_ccm_4000f000_IRQ_NUM 1
#define DT_N_S_soc_S_ccm_4000f000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ccm_4000f000_IRQ_IDX_0_VAL_irq 15
#define DT_N_S_soc_S_ccm_4000f000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_ccm_4000f000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ccm_4000f000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_ccm_4000f000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_ccm_4000f000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_ccm_4000f000_IRQ_LEVEL 1
#define DT_N_S_soc_S_ccm_4000f000_COMPAT_MATCHES_nordic_nrf_ccm 1
#define DT_N_S_soc_S_ccm_4000f000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ccm_4000f000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_ccm_4000f000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ccm_4000f000_COMPAT_MODEL_IDX_0 "nrf-ccm"
#define DT_N_S_soc_S_ccm_4000f000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_ccm_4000f000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_ccm_4000f000_P_wakeup_source 0
#define DT_N_S_soc_S_ccm_4000f000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_ccm_4000f000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_ccm_4000f000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_ccm_4000f000_P_status "okay"
#define DT_N_S_soc_S_ccm_4000f000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_ccm_4000f000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_ccm_4000f000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_ccm_4000f000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_ccm_4000f000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ccm_4000f000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_ccm_4000f000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_ccm_4000f000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_ccm_4000f000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_ccm_4000f000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ccm_4000f000, status, 0)
#define DT_N_S_soc_S_ccm_4000f000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ccm_4000f000, status, 0)
#define DT_N_S_soc_S_ccm_4000f000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ccm_4000f000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ccm_4000f000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ccm_4000f000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ccm_4000f000_P_status_LEN 1
#define DT_N_S_soc_S_ccm_4000f000_P_status_EXISTS 1
#define DT_N_S_soc_S_ccm_4000f000_P_compatible {"nordic,nrf-ccm"}
#define DT_N_S_soc_S_ccm_4000f000_P_compatible_IDX_0 "nordic,nrf-ccm"
#define DT_N_S_soc_S_ccm_4000f000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-ccm
#define DT_N_S_soc_S_ccm_4000f000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_ccm
#define DT_N_S_soc_S_ccm_4000f000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_CCM
#define DT_N_S_soc_S_ccm_4000f000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ccm_4000f000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ccm_4000f000, compatible, 0)
#define DT_N_S_soc_S_ccm_4000f000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ccm_4000f000, compatible, 0)
#define DT_N_S_soc_S_ccm_4000f000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ccm_4000f000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ccm_4000f000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ccm_4000f000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ccm_4000f000_P_compatible_LEN 1
#define DT_N_S_soc_S_ccm_4000f000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_ccm_4000f000_P_reg {1073803264 /* 0x4000f000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_ccm_4000f000_P_reg_IDX_0 1073803264
#define DT_N_S_soc_S_ccm_4000f000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ccm_4000f000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_ccm_4000f000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_ccm_4000f000_P_reg_EXISTS 1
#define DT_N_S_soc_S_ccm_4000f000_P_interrupts {15 /* 0xf */, 1 /* 0x1 */}
#define DT_N_S_soc_S_ccm_4000f000_P_interrupts_IDX_0 15
#define DT_N_S_soc_S_ccm_4000f000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ccm_4000f000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_ccm_4000f000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_ccm_4000f000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_ccm_4000f000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_ccm_4000f000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_ccm_4000f000_P_length_field_length_8_bits 1
#define DT_N_S_soc_S_ccm_4000f000_P_length_field_length_8_bits_EXISTS 1
#define DT_N_S_soc_S_ccm_4000f000_P_headermask_supported 0
#define DT_N_S_soc_S_ccm_4000f000_P_headermask_supported_EXISTS 1

/*
 * Devicetree node: /soc/clock@40000000
 *
 * Node identifier: DT_N_S_soc_S_clock_40000000
 *
 * Binding (compatible = nordic,nrf-clock):
 *   $ZEPHYR_BASE/dts/bindings/clock/nordic,nrf-clock.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_clock_40000000_PATH "/soc/clock@40000000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_clock_40000000_FULL_NAME "clock@40000000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_clock_40000000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_clock_40000000_CHILD_IDX 5

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_clock_40000000_CHILD_NUM 0
#define DT_N_S_soc_S_clock_40000000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_clock_40000000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_clock_40000000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_clock_40000000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_clock_40000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_clock_40000000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_clock_40000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_clock_40000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_clock_40000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_clock_40000000_ORD 75
#define DT_N_S_soc_S_clock_40000000_ORD_STR_SORTABLE 00075

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_clock_40000000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_clock_40000000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_clock_40000000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_clock DT_N_S_soc_S_clock_40000000
#define DT_N_NODELABEL_clock         DT_N_S_soc_S_clock_40000000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_clock_40000000_REG_NUM 1
#define DT_N_S_soc_S_clock_40000000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_clock_40000000_REG_IDX_0_VAL_ADDRESS 1073741824 /* 0x40000000 */
#define DT_N_S_soc_S_clock_40000000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_clock_40000000_RANGES_NUM 0
#define DT_N_S_soc_S_clock_40000000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_clock_40000000_IRQ_NUM 1
#define DT_N_S_soc_S_clock_40000000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_clock_40000000_IRQ_IDX_0_VAL_irq 0
#define DT_N_S_soc_S_clock_40000000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_clock_40000000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_clock_40000000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_clock_40000000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_clock_40000000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_clock_40000000_IRQ_LEVEL 1
#define DT_N_S_soc_S_clock_40000000_COMPAT_MATCHES_nordic_nrf_clock 1
#define DT_N_S_soc_S_clock_40000000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_clock_40000000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_clock_40000000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_clock_40000000_COMPAT_MODEL_IDX_0 "nrf-clock"
#define DT_N_S_soc_S_clock_40000000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_clock_40000000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_clock_40000000_P_wakeup_source 0
#define DT_N_S_soc_S_clock_40000000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_clock_40000000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_clock_40000000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_clock_40000000_P_status "okay"
#define DT_N_S_soc_S_clock_40000000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_clock_40000000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_clock_40000000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_clock_40000000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_clock_40000000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_clock_40000000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_clock_40000000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_clock_40000000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_clock_40000000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_clock_40000000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_clock_40000000, status, 0)
#define DT_N_S_soc_S_clock_40000000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_clock_40000000, status, 0)
#define DT_N_S_soc_S_clock_40000000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_clock_40000000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_clock_40000000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_clock_40000000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_clock_40000000_P_status_LEN 1
#define DT_N_S_soc_S_clock_40000000_P_status_EXISTS 1
#define DT_N_S_soc_S_clock_40000000_P_compatible {"nordic,nrf-clock"}
#define DT_N_S_soc_S_clock_40000000_P_compatible_IDX_0 "nordic,nrf-clock"
#define DT_N_S_soc_S_clock_40000000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-clock
#define DT_N_S_soc_S_clock_40000000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_clock
#define DT_N_S_soc_S_clock_40000000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_CLOCK
#define DT_N_S_soc_S_clock_40000000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_clock_40000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_clock_40000000, compatible, 0)
#define DT_N_S_soc_S_clock_40000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_clock_40000000, compatible, 0)
#define DT_N_S_soc_S_clock_40000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_clock_40000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_clock_40000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_clock_40000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_clock_40000000_P_compatible_LEN 1
#define DT_N_S_soc_S_clock_40000000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_clock_40000000_P_reg {1073741824 /* 0x40000000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_clock_40000000_P_reg_IDX_0 1073741824
#define DT_N_S_soc_S_clock_40000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_clock_40000000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_clock_40000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_clock_40000000_P_reg_EXISTS 1
#define DT_N_S_soc_S_clock_40000000_P_interrupts {0 /* 0x0 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_clock_40000000_P_interrupts_IDX_0 0
#define DT_N_S_soc_S_clock_40000000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_clock_40000000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_clock_40000000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_clock_40000000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_clock_40000000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_clock_40000000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/comparator@40013000
 *
 * Node identifier: DT_N_S_soc_S_comparator_40013000
 *
 * Binding (compatible = nordic,nrf-comp):
 *   $ZEPHYR_BASE/dts/bindings/sensor/nordic,nrf-comp.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_comparator_40013000_PATH "/soc/comparator@40013000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_comparator_40013000_FULL_NAME "comparator@40013000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_comparator_40013000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_comparator_40013000_CHILD_IDX 27

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_comparator_40013000_CHILD_NUM 0
#define DT_N_S_soc_S_comparator_40013000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_comparator_40013000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_comparator_40013000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_comparator_40013000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_comparator_40013000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_comparator_40013000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_comparator_40013000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_comparator_40013000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_comparator_40013000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_comparator_40013000_ORD 76
#define DT_N_S_soc_S_comparator_40013000_ORD_STR_SORTABLE 00076

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_comparator_40013000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_comparator_40013000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_comparator_40013000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_comp DT_N_S_soc_S_comparator_40013000
#define DT_N_NODELABEL_comp         DT_N_S_soc_S_comparator_40013000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_comparator_40013000_REG_NUM 1
#define DT_N_S_soc_S_comparator_40013000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40013000_REG_IDX_0_VAL_ADDRESS 1073819648 /* 0x40013000 */
#define DT_N_S_soc_S_comparator_40013000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_comparator_40013000_RANGES_NUM 0
#define DT_N_S_soc_S_comparator_40013000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_comparator_40013000_IRQ_NUM 1
#define DT_N_S_soc_S_comparator_40013000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40013000_IRQ_IDX_0_VAL_irq 19
#define DT_N_S_soc_S_comparator_40013000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_comparator_40013000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40013000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_comparator_40013000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_comparator_40013000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_comparator_40013000_IRQ_LEVEL 1
#define DT_N_S_soc_S_comparator_40013000_COMPAT_MATCHES_nordic_nrf_comp 1
#define DT_N_S_soc_S_comparator_40013000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40013000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_comparator_40013000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40013000_COMPAT_MODEL_IDX_0 "nrf-comp"
#define DT_N_S_soc_S_comparator_40013000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_comparator_40013000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_comparator_40013000_P_wakeup_source 0
#define DT_N_S_soc_S_comparator_40013000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_comparator_40013000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_comparator_40013000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_comparator_40013000_P_status "disabled"
#define DT_N_S_soc_S_comparator_40013000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_comparator_40013000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_comparator_40013000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_comparator_40013000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_comparator_40013000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40013000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_comparator_40013000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_comparator_40013000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_comparator_40013000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_comparator_40013000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_comparator_40013000, status, 0)
#define DT_N_S_soc_S_comparator_40013000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_comparator_40013000, status, 0)
#define DT_N_S_soc_S_comparator_40013000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_comparator_40013000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40013000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_comparator_40013000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40013000_P_status_LEN 1
#define DT_N_S_soc_S_comparator_40013000_P_status_EXISTS 1
#define DT_N_S_soc_S_comparator_40013000_P_compatible {"nordic,nrf-comp"}
#define DT_N_S_soc_S_comparator_40013000_P_compatible_IDX_0 "nordic,nrf-comp"
#define DT_N_S_soc_S_comparator_40013000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-comp
#define DT_N_S_soc_S_comparator_40013000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_comp
#define DT_N_S_soc_S_comparator_40013000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_COMP
#define DT_N_S_soc_S_comparator_40013000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40013000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_comparator_40013000, compatible, 0)
#define DT_N_S_soc_S_comparator_40013000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_comparator_40013000, compatible, 0)
#define DT_N_S_soc_S_comparator_40013000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_comparator_40013000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40013000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_comparator_40013000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_comparator_40013000_P_compatible_LEN 1
#define DT_N_S_soc_S_comparator_40013000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_comparator_40013000_P_reg {1073819648 /* 0x40013000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_comparator_40013000_P_reg_IDX_0 1073819648
#define DT_N_S_soc_S_comparator_40013000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40013000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_comparator_40013000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_comparator_40013000_P_reg_EXISTS 1
#define DT_N_S_soc_S_comparator_40013000_P_interrupts {19 /* 0x13 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_comparator_40013000_P_interrupts_IDX_0 19
#define DT_N_S_soc_S_comparator_40013000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_comparator_40013000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_comparator_40013000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_comparator_40013000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_comparator_40013000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_comparator_40013000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/crypto@5002a000
 *
 * Node identifier: DT_N_S_soc_S_crypto_5002a000
 *
 * Binding (compatible = arm,cryptocell-310):
 *   $ZEPHYR_BASE/dts/bindings/crypto/arm,cryptocell-310.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_crypto_5002a000_PATH "/soc/crypto@5002a000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_crypto_5002a000_FULL_NAME "crypto@5002a000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_crypto_5002a000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_crypto_5002a000_CHILD_IDX 54

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_crypto_5002a000_CHILD_NUM 0
#define DT_N_S_soc_S_crypto_5002a000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_crypto_5002a000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_crypto_5002a000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_crypto_5002a000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_crypto_5002a000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_crypto_5002a000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_crypto_5002a000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_crypto_5002a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_crypto_5002a000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_crypto_5002a000_ORD 77
#define DT_N_S_soc_S_crypto_5002a000_ORD_STR_SORTABLE 00077

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_crypto_5002a000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_crypto_5002a000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_crypto_5002a000_EXISTS 1
#define DT_N_INST_0_nordic_cryptocell  DT_N_S_soc_S_crypto_5002a000
#define DT_N_INST_0_arm_cryptocell_310 DT_N_S_soc_S_crypto_5002a000
#define DT_N_NODELABEL_cryptocell      DT_N_S_soc_S_crypto_5002a000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_crypto_5002a000_REG_NUM 2
#define DT_N_S_soc_S_crypto_5002a000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_5002a000_REG_IDX_0_VAL_ADDRESS 1342349312 /* 0x5002a000 */
#define DT_N_S_soc_S_crypto_5002a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_crypto_5002a000_REG_IDX_1_EXISTS 1
#define DT_N_S_soc_S_crypto_5002a000_REG_IDX_1_VAL_ADDRESS 1342353408 /* 0x5002b000 */
#define DT_N_S_soc_S_crypto_5002a000_REG_IDX_1_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_crypto_5002a000_REG_NAME_wrapper_VAL_ADDRESS DT_N_S_soc_S_crypto_5002a000_REG_IDX_0_VAL_ADDRESS
#define DT_N_S_soc_S_crypto_5002a000_REG_NAME_wrapper_VAL_SIZE DT_N_S_soc_S_crypto_5002a000_REG_IDX_0_VAL_SIZE
#define DT_N_S_soc_S_crypto_5002a000_REG_NAME_core_VAL_ADDRESS DT_N_S_soc_S_crypto_5002a000_REG_IDX_1_VAL_ADDRESS
#define DT_N_S_soc_S_crypto_5002a000_REG_NAME_core_VAL_SIZE DT_N_S_soc_S_crypto_5002a000_REG_IDX_1_VAL_SIZE
#define DT_N_S_soc_S_crypto_5002a000_RANGES_NUM 0
#define DT_N_S_soc_S_crypto_5002a000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_crypto_5002a000_IRQ_NUM 1
#define DT_N_S_soc_S_crypto_5002a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_5002a000_IRQ_IDX_0_VAL_irq 42
#define DT_N_S_soc_S_crypto_5002a000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_crypto_5002a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_5002a000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_crypto_5002a000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_crypto_5002a000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_crypto_5002a000_IRQ_LEVEL 1
#define DT_N_S_soc_S_crypto_5002a000_COMPAT_MATCHES_nordic_cryptocell 1
#define DT_N_S_soc_S_crypto_5002a000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_5002a000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_crypto_5002a000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_5002a000_COMPAT_MODEL_IDX_0 "cryptocell"
#define DT_N_S_soc_S_crypto_5002a000_COMPAT_MATCHES_arm_cryptocell_310 1
#define DT_N_S_soc_S_crypto_5002a000_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_crypto_5002a000_COMPAT_VENDOR_IDX_1 "ARM Ltd."
#define DT_N_S_soc_S_crypto_5002a000_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_crypto_5002a000_COMPAT_MODEL_IDX_1 "cryptocell-310"
#define DT_N_S_soc_S_crypto_5002a000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_crypto_5002a000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_crypto_5002a000_P_wakeup_source 0
#define DT_N_S_soc_S_crypto_5002a000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_crypto_5002a000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_crypto_5002a000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_crypto_5002a000_P_status "okay"
#define DT_N_S_soc_S_crypto_5002a000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_crypto_5002a000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_crypto_5002a000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_crypto_5002a000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_crypto_5002a000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_5002a000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_crypto_5002a000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_crypto_5002a000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_crypto_5002a000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_crypto_5002a000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_crypto_5002a000, status, 0)
#define DT_N_S_soc_S_crypto_5002a000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_crypto_5002a000, status, 0)
#define DT_N_S_soc_S_crypto_5002a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_crypto_5002a000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_crypto_5002a000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crypto_5002a000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_crypto_5002a000_P_status_LEN 1
#define DT_N_S_soc_S_crypto_5002a000_P_status_EXISTS 1
#define DT_N_S_soc_S_crypto_5002a000_P_compatible {"nordic,cryptocell", "arm,cryptocell-310"}
#define DT_N_S_soc_S_crypto_5002a000_P_compatible_IDX_0 "nordic,cryptocell"
#define DT_N_S_soc_S_crypto_5002a000_P_compatible_IDX_0_STRING_UNQUOTED nordic,cryptocell
#define DT_N_S_soc_S_crypto_5002a000_P_compatible_IDX_0_STRING_TOKEN nordic_cryptocell
#define DT_N_S_soc_S_crypto_5002a000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_CRYPTOCELL
#define DT_N_S_soc_S_crypto_5002a000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_5002a000_P_compatible_IDX_1 "arm,cryptocell-310"
#define DT_N_S_soc_S_crypto_5002a000_P_compatible_IDX_1_STRING_UNQUOTED arm,cryptocell-310
#define DT_N_S_soc_S_crypto_5002a000_P_compatible_IDX_1_STRING_TOKEN arm_cryptocell_310
#define DT_N_S_soc_S_crypto_5002a000_P_compatible_IDX_1_STRING_UPPER_TOKEN ARM_CRYPTOCELL_310
#define DT_N_S_soc_S_crypto_5002a000_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_crypto_5002a000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_crypto_5002a000, compatible, 0) \
	fn(DT_N_S_soc_S_crypto_5002a000, compatible, 1)
#define DT_N_S_soc_S_crypto_5002a000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_crypto_5002a000, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_crypto_5002a000, compatible, 1)
#define DT_N_S_soc_S_crypto_5002a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_crypto_5002a000, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_crypto_5002a000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_crypto_5002a000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crypto_5002a000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_crypto_5002a000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_crypto_5002a000_P_compatible_LEN 2
#define DT_N_S_soc_S_crypto_5002a000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_crypto_5002a000_P_reg {1342349312 /* 0x5002a000 */, 4096 /* 0x1000 */, 1342353408 /* 0x5002b000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_crypto_5002a000_P_reg_IDX_0 1342349312
#define DT_N_S_soc_S_crypto_5002a000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_5002a000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_crypto_5002a000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_crypto_5002a000_P_reg_IDX_2 1342353408
#define DT_N_S_soc_S_crypto_5002a000_P_reg_IDX_2_EXISTS 1
#define DT_N_S_soc_S_crypto_5002a000_P_reg_IDX_3 4096
#define DT_N_S_soc_S_crypto_5002a000_P_reg_IDX_3_EXISTS 1
#define DT_N_S_soc_S_crypto_5002a000_P_reg_EXISTS 1
#define DT_N_S_soc_S_crypto_5002a000_P_reg_names {"wrapper", "core"}
#define DT_N_S_soc_S_crypto_5002a000_P_reg_names_IDX_0 "wrapper"
#define DT_N_S_soc_S_crypto_5002a000_P_reg_names_IDX_0_STRING_UNQUOTED wrapper
#define DT_N_S_soc_S_crypto_5002a000_P_reg_names_IDX_0_STRING_TOKEN wrapper
#define DT_N_S_soc_S_crypto_5002a000_P_reg_names_IDX_0_STRING_UPPER_TOKEN WRAPPER
#define DT_N_S_soc_S_crypto_5002a000_P_reg_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_5002a000_P_reg_names_IDX_1 "core"
#define DT_N_S_soc_S_crypto_5002a000_P_reg_names_IDX_1_STRING_UNQUOTED core
#define DT_N_S_soc_S_crypto_5002a000_P_reg_names_IDX_1_STRING_TOKEN core
#define DT_N_S_soc_S_crypto_5002a000_P_reg_names_IDX_1_STRING_UPPER_TOKEN CORE
#define DT_N_S_soc_S_crypto_5002a000_P_reg_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_crypto_5002a000_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_crypto_5002a000, reg_names, 0) \
	fn(DT_N_S_soc_S_crypto_5002a000, reg_names, 1)
#define DT_N_S_soc_S_crypto_5002a000_P_reg_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_crypto_5002a000, reg_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_crypto_5002a000, reg_names, 1)
#define DT_N_S_soc_S_crypto_5002a000_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_crypto_5002a000, reg_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_crypto_5002a000, reg_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_crypto_5002a000_P_reg_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_crypto_5002a000, reg_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_crypto_5002a000, reg_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_crypto_5002a000_P_reg_names_LEN 2
#define DT_N_S_soc_S_crypto_5002a000_P_reg_names_EXISTS 1
#define DT_N_S_soc_S_crypto_5002a000_P_interrupts {42 /* 0x2a */, 1 /* 0x1 */}
#define DT_N_S_soc_S_crypto_5002a000_P_interrupts_IDX_0 42
#define DT_N_S_soc_S_crypto_5002a000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_5002a000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_crypto_5002a000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_crypto_5002a000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_crypto_5002a000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_crypto_5002a000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/ecb@4000e000
 *
 * Node identifier: DT_N_S_soc_S_ecb_4000e000
 *
 * Binding (compatible = nordic,nrf-ecb):
 *   $ZEPHYR_BASE/dts/bindings/crypto/nordic,nrf-ecb.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_ecb_4000e000_PATH "/soc/ecb@4000e000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_ecb_4000e000_FULL_NAME "ecb@4000e000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_ecb_4000e000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_ecb_4000e000_CHILD_IDX 22

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_ecb_4000e000_CHILD_NUM 0
#define DT_N_S_soc_S_ecb_4000e000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_ecb_4000e000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_ecb_4000e000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_ecb_4000e000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_ecb_4000e000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_ecb_4000e000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_ecb_4000e000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_ecb_4000e000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_ecb_4000e000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_ecb_4000e000_ORD 78
#define DT_N_S_soc_S_ecb_4000e000_ORD_STR_SORTABLE 00078

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_ecb_4000e000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_ecb_4000e000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_ecb_4000e000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_ecb DT_N_S_soc_S_ecb_4000e000
#define DT_N_NODELABEL_ecb         DT_N_S_soc_S_ecb_4000e000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_ecb_4000e000_REG_NUM 1
#define DT_N_S_soc_S_ecb_4000e000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ecb_4000e000_REG_IDX_0_VAL_ADDRESS 1073799168 /* 0x4000e000 */
#define DT_N_S_soc_S_ecb_4000e000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_ecb_4000e000_RANGES_NUM 0
#define DT_N_S_soc_S_ecb_4000e000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_ecb_4000e000_IRQ_NUM 1
#define DT_N_S_soc_S_ecb_4000e000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ecb_4000e000_IRQ_IDX_0_VAL_irq 14
#define DT_N_S_soc_S_ecb_4000e000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_ecb_4000e000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ecb_4000e000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_ecb_4000e000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_ecb_4000e000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_ecb_4000e000_IRQ_LEVEL 1
#define DT_N_S_soc_S_ecb_4000e000_COMPAT_MATCHES_nordic_nrf_ecb 1
#define DT_N_S_soc_S_ecb_4000e000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ecb_4000e000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_ecb_4000e000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ecb_4000e000_COMPAT_MODEL_IDX_0 "nrf-ecb"
#define DT_N_S_soc_S_ecb_4000e000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_ecb_4000e000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_ecb_4000e000_P_wakeup_source 0
#define DT_N_S_soc_S_ecb_4000e000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_ecb_4000e000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_ecb_4000e000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_ecb_4000e000_P_status "okay"
#define DT_N_S_soc_S_ecb_4000e000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_ecb_4000e000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_ecb_4000e000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_ecb_4000e000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_ecb_4000e000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ecb_4000e000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_ecb_4000e000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_ecb_4000e000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_ecb_4000e000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_ecb_4000e000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ecb_4000e000, status, 0)
#define DT_N_S_soc_S_ecb_4000e000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ecb_4000e000, status, 0)
#define DT_N_S_soc_S_ecb_4000e000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ecb_4000e000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ecb_4000e000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ecb_4000e000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ecb_4000e000_P_status_LEN 1
#define DT_N_S_soc_S_ecb_4000e000_P_status_EXISTS 1
#define DT_N_S_soc_S_ecb_4000e000_P_compatible {"nordic,nrf-ecb"}
#define DT_N_S_soc_S_ecb_4000e000_P_compatible_IDX_0 "nordic,nrf-ecb"
#define DT_N_S_soc_S_ecb_4000e000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-ecb
#define DT_N_S_soc_S_ecb_4000e000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_ecb
#define DT_N_S_soc_S_ecb_4000e000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_ECB
#define DT_N_S_soc_S_ecb_4000e000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ecb_4000e000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ecb_4000e000, compatible, 0)
#define DT_N_S_soc_S_ecb_4000e000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ecb_4000e000, compatible, 0)
#define DT_N_S_soc_S_ecb_4000e000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ecb_4000e000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ecb_4000e000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ecb_4000e000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ecb_4000e000_P_compatible_LEN 1
#define DT_N_S_soc_S_ecb_4000e000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_ecb_4000e000_P_reg {1073799168 /* 0x4000e000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_ecb_4000e000_P_reg_IDX_0 1073799168
#define DT_N_S_soc_S_ecb_4000e000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ecb_4000e000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_ecb_4000e000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_ecb_4000e000_P_reg_EXISTS 1
#define DT_N_S_soc_S_ecb_4000e000_P_interrupts {14 /* 0xe */, 1 /* 0x1 */}
#define DT_N_S_soc_S_ecb_4000e000_P_interrupts_IDX_0 14
#define DT_N_S_soc_S_ecb_4000e000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ecb_4000e000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_ecb_4000e000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_ecb_4000e000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_ecb_4000e000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_ecb_4000e000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/egu@40014000
 *
 * Node identifier: DT_N_S_soc_S_egu_40014000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-egu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_egu_40014000_PATH "/soc/egu@40014000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_egu_40014000_FULL_NAME "egu@40014000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_egu_40014000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_egu_40014000_CHILD_IDX 28

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_egu_40014000_CHILD_NUM 0
#define DT_N_S_soc_S_egu_40014000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_egu_40014000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_egu_40014000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_egu_40014000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_egu_40014000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_egu_40014000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_egu_40014000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_egu_40014000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_egu_40014000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_egu_40014000_ORD 79
#define DT_N_S_soc_S_egu_40014000_ORD_STR_SORTABLE 00079

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_egu_40014000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_egu_40014000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_egu_40014000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_egu DT_N_S_soc_S_egu_40014000
#define DT_N_INST_0_nordic_nrf_swi DT_N_S_soc_S_egu_40014000
#define DT_N_NODELABEL_egu0        DT_N_S_soc_S_egu_40014000
#define DT_N_NODELABEL_swi0        DT_N_S_soc_S_egu_40014000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_egu_40014000_REG_NUM 1
#define DT_N_S_soc_S_egu_40014000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40014000_REG_IDX_0_VAL_ADDRESS 1073823744 /* 0x40014000 */
#define DT_N_S_soc_S_egu_40014000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_egu_40014000_RANGES_NUM 0
#define DT_N_S_soc_S_egu_40014000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_egu_40014000_IRQ_NUM 1
#define DT_N_S_soc_S_egu_40014000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40014000_IRQ_IDX_0_VAL_irq 20
#define DT_N_S_soc_S_egu_40014000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_egu_40014000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40014000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_egu_40014000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_egu_40014000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_egu_40014000_IRQ_LEVEL 1
#define DT_N_S_soc_S_egu_40014000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_egu_40014000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40014000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_egu_40014000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40014000_COMPAT_MODEL_IDX_0 "nrf-egu"
#define DT_N_S_soc_S_egu_40014000_COMPAT_MATCHES_nordic_nrf_swi 1
#define DT_N_S_soc_S_egu_40014000_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_egu_40014000_COMPAT_VENDOR_IDX_1 "Nordic Semiconductor"
#define DT_N_S_soc_S_egu_40014000_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_egu_40014000_COMPAT_MODEL_IDX_1 "nrf-swi"
#define DT_N_S_soc_S_egu_40014000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_egu_40014000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_egu_40014000_P_wakeup_source 0
#define DT_N_S_soc_S_egu_40014000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_egu_40014000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_egu_40014000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_egu_40014000_P_status "okay"
#define DT_N_S_soc_S_egu_40014000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_egu_40014000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_egu_40014000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_egu_40014000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_egu_40014000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40014000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_egu_40014000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_egu_40014000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_egu_40014000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_egu_40014000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_egu_40014000, status, 0)
#define DT_N_S_soc_S_egu_40014000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_egu_40014000, status, 0)
#define DT_N_S_soc_S_egu_40014000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_egu_40014000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_egu_40014000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_egu_40014000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_egu_40014000_P_status_LEN 1
#define DT_N_S_soc_S_egu_40014000_P_status_EXISTS 1
#define DT_N_S_soc_S_egu_40014000_P_compatible {"nordic,nrf-egu", "nordic,nrf-swi"}
#define DT_N_S_soc_S_egu_40014000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_egu_40014000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-egu
#define DT_N_S_soc_S_egu_40014000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu
#define DT_N_S_soc_S_egu_40014000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU
#define DT_N_S_soc_S_egu_40014000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40014000_P_compatible_IDX_1 "nordic,nrf-swi"
#define DT_N_S_soc_S_egu_40014000_P_compatible_IDX_1_STRING_UNQUOTED nordic,nrf-swi
#define DT_N_S_soc_S_egu_40014000_P_compatible_IDX_1_STRING_TOKEN nordic_nrf_swi
#define DT_N_S_soc_S_egu_40014000_P_compatible_IDX_1_STRING_UPPER_TOKEN NORDIC_NRF_SWI
#define DT_N_S_soc_S_egu_40014000_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_egu_40014000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_egu_40014000, compatible, 0) \
	fn(DT_N_S_soc_S_egu_40014000, compatible, 1)
#define DT_N_S_soc_S_egu_40014000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_egu_40014000, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_egu_40014000, compatible, 1)
#define DT_N_S_soc_S_egu_40014000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_egu_40014000, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_egu_40014000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_egu_40014000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_egu_40014000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_egu_40014000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_egu_40014000_P_compatible_LEN 2
#define DT_N_S_soc_S_egu_40014000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_egu_40014000_P_reg {1073823744 /* 0x40014000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_egu_40014000_P_reg_IDX_0 1073823744
#define DT_N_S_soc_S_egu_40014000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40014000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_egu_40014000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_egu_40014000_P_reg_EXISTS 1
#define DT_N_S_soc_S_egu_40014000_P_interrupts {20 /* 0x14 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_egu_40014000_P_interrupts_IDX_0 20
#define DT_N_S_soc_S_egu_40014000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40014000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_egu_40014000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_egu_40014000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_egu_40014000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_egu_40014000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/egu@40015000
 *
 * Node identifier: DT_N_S_soc_S_egu_40015000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-egu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_egu_40015000_PATH "/soc/egu@40015000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_egu_40015000_FULL_NAME "egu@40015000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_egu_40015000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_egu_40015000_CHILD_IDX 29

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_egu_40015000_CHILD_NUM 0
#define DT_N_S_soc_S_egu_40015000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_egu_40015000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_egu_40015000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_egu_40015000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_egu_40015000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_egu_40015000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_egu_40015000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_egu_40015000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_egu_40015000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_egu_40015000_ORD 80
#define DT_N_S_soc_S_egu_40015000_ORD_STR_SORTABLE 00080

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_egu_40015000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_egu_40015000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_egu_40015000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_egu DT_N_S_soc_S_egu_40015000
#define DT_N_INST_1_nordic_nrf_swi DT_N_S_soc_S_egu_40015000
#define DT_N_NODELABEL_egu1        DT_N_S_soc_S_egu_40015000
#define DT_N_NODELABEL_swi1        DT_N_S_soc_S_egu_40015000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_egu_40015000_REG_NUM 1
#define DT_N_S_soc_S_egu_40015000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40015000_REG_IDX_0_VAL_ADDRESS 1073827840 /* 0x40015000 */
#define DT_N_S_soc_S_egu_40015000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_egu_40015000_RANGES_NUM 0
#define DT_N_S_soc_S_egu_40015000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_egu_40015000_IRQ_NUM 1
#define DT_N_S_soc_S_egu_40015000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40015000_IRQ_IDX_0_VAL_irq 21
#define DT_N_S_soc_S_egu_40015000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_egu_40015000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40015000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_egu_40015000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_egu_40015000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_egu_40015000_IRQ_LEVEL 1
#define DT_N_S_soc_S_egu_40015000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_egu_40015000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40015000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_egu_40015000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40015000_COMPAT_MODEL_IDX_0 "nrf-egu"
#define DT_N_S_soc_S_egu_40015000_COMPAT_MATCHES_nordic_nrf_swi 1
#define DT_N_S_soc_S_egu_40015000_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_egu_40015000_COMPAT_VENDOR_IDX_1 "Nordic Semiconductor"
#define DT_N_S_soc_S_egu_40015000_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_egu_40015000_COMPAT_MODEL_IDX_1 "nrf-swi"
#define DT_N_S_soc_S_egu_40015000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_egu_40015000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_egu_40015000_P_wakeup_source 0
#define DT_N_S_soc_S_egu_40015000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_egu_40015000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_egu_40015000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_egu_40015000_P_status "okay"
#define DT_N_S_soc_S_egu_40015000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_egu_40015000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_egu_40015000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_egu_40015000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_egu_40015000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40015000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_egu_40015000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_egu_40015000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_egu_40015000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_egu_40015000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_egu_40015000, status, 0)
#define DT_N_S_soc_S_egu_40015000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_egu_40015000, status, 0)
#define DT_N_S_soc_S_egu_40015000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_egu_40015000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_egu_40015000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_egu_40015000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_egu_40015000_P_status_LEN 1
#define DT_N_S_soc_S_egu_40015000_P_status_EXISTS 1
#define DT_N_S_soc_S_egu_40015000_P_compatible {"nordic,nrf-egu", "nordic,nrf-swi"}
#define DT_N_S_soc_S_egu_40015000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_egu_40015000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-egu
#define DT_N_S_soc_S_egu_40015000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu
#define DT_N_S_soc_S_egu_40015000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU
#define DT_N_S_soc_S_egu_40015000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40015000_P_compatible_IDX_1 "nordic,nrf-swi"
#define DT_N_S_soc_S_egu_40015000_P_compatible_IDX_1_STRING_UNQUOTED nordic,nrf-swi
#define DT_N_S_soc_S_egu_40015000_P_compatible_IDX_1_STRING_TOKEN nordic_nrf_swi
#define DT_N_S_soc_S_egu_40015000_P_compatible_IDX_1_STRING_UPPER_TOKEN NORDIC_NRF_SWI
#define DT_N_S_soc_S_egu_40015000_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_egu_40015000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_egu_40015000, compatible, 0) \
	fn(DT_N_S_soc_S_egu_40015000, compatible, 1)
#define DT_N_S_soc_S_egu_40015000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_egu_40015000, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_egu_40015000, compatible, 1)
#define DT_N_S_soc_S_egu_40015000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_egu_40015000, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_egu_40015000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_egu_40015000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_egu_40015000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_egu_40015000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_egu_40015000_P_compatible_LEN 2
#define DT_N_S_soc_S_egu_40015000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_egu_40015000_P_reg {1073827840 /* 0x40015000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_egu_40015000_P_reg_IDX_0 1073827840
#define DT_N_S_soc_S_egu_40015000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40015000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_egu_40015000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_egu_40015000_P_reg_EXISTS 1
#define DT_N_S_soc_S_egu_40015000_P_interrupts {21 /* 0x15 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_egu_40015000_P_interrupts_IDX_0 21
#define DT_N_S_soc_S_egu_40015000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40015000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_egu_40015000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_egu_40015000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_egu_40015000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_egu_40015000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/egu@40016000
 *
 * Node identifier: DT_N_S_soc_S_egu_40016000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-egu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_egu_40016000_PATH "/soc/egu@40016000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_egu_40016000_FULL_NAME "egu@40016000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_egu_40016000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_egu_40016000_CHILD_IDX 30

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_egu_40016000_CHILD_NUM 0
#define DT_N_S_soc_S_egu_40016000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_egu_40016000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_egu_40016000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_egu_40016000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_egu_40016000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_egu_40016000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_egu_40016000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_egu_40016000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_egu_40016000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_egu_40016000_ORD 81
#define DT_N_S_soc_S_egu_40016000_ORD_STR_SORTABLE 00081

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_egu_40016000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_egu_40016000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_egu_40016000_EXISTS 1
#define DT_N_INST_2_nordic_nrf_egu DT_N_S_soc_S_egu_40016000
#define DT_N_INST_2_nordic_nrf_swi DT_N_S_soc_S_egu_40016000
#define DT_N_NODELABEL_egu2        DT_N_S_soc_S_egu_40016000
#define DT_N_NODELABEL_swi2        DT_N_S_soc_S_egu_40016000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_egu_40016000_REG_NUM 1
#define DT_N_S_soc_S_egu_40016000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40016000_REG_IDX_0_VAL_ADDRESS 1073831936 /* 0x40016000 */
#define DT_N_S_soc_S_egu_40016000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_egu_40016000_RANGES_NUM 0
#define DT_N_S_soc_S_egu_40016000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_egu_40016000_IRQ_NUM 1
#define DT_N_S_soc_S_egu_40016000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40016000_IRQ_IDX_0_VAL_irq 22
#define DT_N_S_soc_S_egu_40016000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_egu_40016000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40016000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_egu_40016000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_egu_40016000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_egu_40016000_IRQ_LEVEL 1
#define DT_N_S_soc_S_egu_40016000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_egu_40016000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40016000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_egu_40016000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40016000_COMPAT_MODEL_IDX_0 "nrf-egu"
#define DT_N_S_soc_S_egu_40016000_COMPAT_MATCHES_nordic_nrf_swi 1
#define DT_N_S_soc_S_egu_40016000_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_egu_40016000_COMPAT_VENDOR_IDX_1 "Nordic Semiconductor"
#define DT_N_S_soc_S_egu_40016000_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_egu_40016000_COMPAT_MODEL_IDX_1 "nrf-swi"
#define DT_N_S_soc_S_egu_40016000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_egu_40016000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_egu_40016000_P_wakeup_source 0
#define DT_N_S_soc_S_egu_40016000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_egu_40016000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_egu_40016000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_egu_40016000_P_status "okay"
#define DT_N_S_soc_S_egu_40016000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_egu_40016000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_egu_40016000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_egu_40016000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_egu_40016000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40016000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_egu_40016000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_egu_40016000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_egu_40016000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_egu_40016000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_egu_40016000, status, 0)
#define DT_N_S_soc_S_egu_40016000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_egu_40016000, status, 0)
#define DT_N_S_soc_S_egu_40016000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_egu_40016000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_egu_40016000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_egu_40016000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_egu_40016000_P_status_LEN 1
#define DT_N_S_soc_S_egu_40016000_P_status_EXISTS 1
#define DT_N_S_soc_S_egu_40016000_P_compatible {"nordic,nrf-egu", "nordic,nrf-swi"}
#define DT_N_S_soc_S_egu_40016000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_egu_40016000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-egu
#define DT_N_S_soc_S_egu_40016000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu
#define DT_N_S_soc_S_egu_40016000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU
#define DT_N_S_soc_S_egu_40016000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40016000_P_compatible_IDX_1 "nordic,nrf-swi"
#define DT_N_S_soc_S_egu_40016000_P_compatible_IDX_1_STRING_UNQUOTED nordic,nrf-swi
#define DT_N_S_soc_S_egu_40016000_P_compatible_IDX_1_STRING_TOKEN nordic_nrf_swi
#define DT_N_S_soc_S_egu_40016000_P_compatible_IDX_1_STRING_UPPER_TOKEN NORDIC_NRF_SWI
#define DT_N_S_soc_S_egu_40016000_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_egu_40016000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_egu_40016000, compatible, 0) \
	fn(DT_N_S_soc_S_egu_40016000, compatible, 1)
#define DT_N_S_soc_S_egu_40016000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_egu_40016000, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_egu_40016000, compatible, 1)
#define DT_N_S_soc_S_egu_40016000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_egu_40016000, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_egu_40016000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_egu_40016000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_egu_40016000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_egu_40016000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_egu_40016000_P_compatible_LEN 2
#define DT_N_S_soc_S_egu_40016000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_egu_40016000_P_reg {1073831936 /* 0x40016000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_egu_40016000_P_reg_IDX_0 1073831936
#define DT_N_S_soc_S_egu_40016000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40016000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_egu_40016000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_egu_40016000_P_reg_EXISTS 1
#define DT_N_S_soc_S_egu_40016000_P_interrupts {22 /* 0x16 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_egu_40016000_P_interrupts_IDX_0 22
#define DT_N_S_soc_S_egu_40016000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40016000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_egu_40016000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_egu_40016000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_egu_40016000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_egu_40016000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/egu@40017000
 *
 * Node identifier: DT_N_S_soc_S_egu_40017000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-egu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_egu_40017000_PATH "/soc/egu@40017000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_egu_40017000_FULL_NAME "egu@40017000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_egu_40017000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_egu_40017000_CHILD_IDX 31

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_egu_40017000_CHILD_NUM 0
#define DT_N_S_soc_S_egu_40017000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_egu_40017000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_egu_40017000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_egu_40017000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_egu_40017000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_egu_40017000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_egu_40017000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_egu_40017000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_egu_40017000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_egu_40017000_ORD 82
#define DT_N_S_soc_S_egu_40017000_ORD_STR_SORTABLE 00082

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_egu_40017000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_egu_40017000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_egu_40017000_EXISTS 1
#define DT_N_INST_3_nordic_nrf_egu DT_N_S_soc_S_egu_40017000
#define DT_N_INST_3_nordic_nrf_swi DT_N_S_soc_S_egu_40017000
#define DT_N_NODELABEL_egu3        DT_N_S_soc_S_egu_40017000
#define DT_N_NODELABEL_swi3        DT_N_S_soc_S_egu_40017000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_egu_40017000_REG_NUM 1
#define DT_N_S_soc_S_egu_40017000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40017000_REG_IDX_0_VAL_ADDRESS 1073836032 /* 0x40017000 */
#define DT_N_S_soc_S_egu_40017000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_egu_40017000_RANGES_NUM 0
#define DT_N_S_soc_S_egu_40017000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_egu_40017000_IRQ_NUM 1
#define DT_N_S_soc_S_egu_40017000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40017000_IRQ_IDX_0_VAL_irq 23
#define DT_N_S_soc_S_egu_40017000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_egu_40017000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40017000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_egu_40017000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_egu_40017000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_egu_40017000_IRQ_LEVEL 1
#define DT_N_S_soc_S_egu_40017000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_egu_40017000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40017000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_egu_40017000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40017000_COMPAT_MODEL_IDX_0 "nrf-egu"
#define DT_N_S_soc_S_egu_40017000_COMPAT_MATCHES_nordic_nrf_swi 1
#define DT_N_S_soc_S_egu_40017000_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_egu_40017000_COMPAT_VENDOR_IDX_1 "Nordic Semiconductor"
#define DT_N_S_soc_S_egu_40017000_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_egu_40017000_COMPAT_MODEL_IDX_1 "nrf-swi"
#define DT_N_S_soc_S_egu_40017000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_egu_40017000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_egu_40017000_P_wakeup_source 0
#define DT_N_S_soc_S_egu_40017000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_egu_40017000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_egu_40017000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_egu_40017000_P_status "okay"
#define DT_N_S_soc_S_egu_40017000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_egu_40017000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_egu_40017000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_egu_40017000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_egu_40017000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40017000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_egu_40017000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_egu_40017000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_egu_40017000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_egu_40017000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_egu_40017000, status, 0)
#define DT_N_S_soc_S_egu_40017000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_egu_40017000, status, 0)
#define DT_N_S_soc_S_egu_40017000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_egu_40017000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_egu_40017000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_egu_40017000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_egu_40017000_P_status_LEN 1
#define DT_N_S_soc_S_egu_40017000_P_status_EXISTS 1
#define DT_N_S_soc_S_egu_40017000_P_compatible {"nordic,nrf-egu", "nordic,nrf-swi"}
#define DT_N_S_soc_S_egu_40017000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_egu_40017000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-egu
#define DT_N_S_soc_S_egu_40017000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu
#define DT_N_S_soc_S_egu_40017000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU
#define DT_N_S_soc_S_egu_40017000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40017000_P_compatible_IDX_1 "nordic,nrf-swi"
#define DT_N_S_soc_S_egu_40017000_P_compatible_IDX_1_STRING_UNQUOTED nordic,nrf-swi
#define DT_N_S_soc_S_egu_40017000_P_compatible_IDX_1_STRING_TOKEN nordic_nrf_swi
#define DT_N_S_soc_S_egu_40017000_P_compatible_IDX_1_STRING_UPPER_TOKEN NORDIC_NRF_SWI
#define DT_N_S_soc_S_egu_40017000_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_egu_40017000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_egu_40017000, compatible, 0) \
	fn(DT_N_S_soc_S_egu_40017000, compatible, 1)
#define DT_N_S_soc_S_egu_40017000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_egu_40017000, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_egu_40017000, compatible, 1)
#define DT_N_S_soc_S_egu_40017000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_egu_40017000, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_egu_40017000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_egu_40017000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_egu_40017000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_egu_40017000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_egu_40017000_P_compatible_LEN 2
#define DT_N_S_soc_S_egu_40017000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_egu_40017000_P_reg {1073836032 /* 0x40017000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_egu_40017000_P_reg_IDX_0 1073836032
#define DT_N_S_soc_S_egu_40017000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40017000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_egu_40017000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_egu_40017000_P_reg_EXISTS 1
#define DT_N_S_soc_S_egu_40017000_P_interrupts {23 /* 0x17 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_egu_40017000_P_interrupts_IDX_0 23
#define DT_N_S_soc_S_egu_40017000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40017000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_egu_40017000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_egu_40017000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_egu_40017000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_egu_40017000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/egu@40018000
 *
 * Node identifier: DT_N_S_soc_S_egu_40018000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-egu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_egu_40018000_PATH "/soc/egu@40018000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_egu_40018000_FULL_NAME "egu@40018000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_egu_40018000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_egu_40018000_CHILD_IDX 32

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_egu_40018000_CHILD_NUM 0
#define DT_N_S_soc_S_egu_40018000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_egu_40018000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_egu_40018000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_egu_40018000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_egu_40018000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_egu_40018000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_egu_40018000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_egu_40018000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_egu_40018000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_egu_40018000_ORD 83
#define DT_N_S_soc_S_egu_40018000_ORD_STR_SORTABLE 00083

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_egu_40018000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_egu_40018000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_egu_40018000_EXISTS 1
#define DT_N_INST_4_nordic_nrf_egu DT_N_S_soc_S_egu_40018000
#define DT_N_INST_4_nordic_nrf_swi DT_N_S_soc_S_egu_40018000
#define DT_N_NODELABEL_egu4        DT_N_S_soc_S_egu_40018000
#define DT_N_NODELABEL_swi4        DT_N_S_soc_S_egu_40018000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_egu_40018000_REG_NUM 1
#define DT_N_S_soc_S_egu_40018000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40018000_REG_IDX_0_VAL_ADDRESS 1073840128 /* 0x40018000 */
#define DT_N_S_soc_S_egu_40018000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_egu_40018000_RANGES_NUM 0
#define DT_N_S_soc_S_egu_40018000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_egu_40018000_IRQ_NUM 1
#define DT_N_S_soc_S_egu_40018000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40018000_IRQ_IDX_0_VAL_irq 24
#define DT_N_S_soc_S_egu_40018000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_egu_40018000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40018000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_egu_40018000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_egu_40018000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_egu_40018000_IRQ_LEVEL 1
#define DT_N_S_soc_S_egu_40018000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_egu_40018000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40018000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_egu_40018000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40018000_COMPAT_MODEL_IDX_0 "nrf-egu"
#define DT_N_S_soc_S_egu_40018000_COMPAT_MATCHES_nordic_nrf_swi 1
#define DT_N_S_soc_S_egu_40018000_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_egu_40018000_COMPAT_VENDOR_IDX_1 "Nordic Semiconductor"
#define DT_N_S_soc_S_egu_40018000_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_egu_40018000_COMPAT_MODEL_IDX_1 "nrf-swi"
#define DT_N_S_soc_S_egu_40018000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_egu_40018000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_egu_40018000_P_wakeup_source 0
#define DT_N_S_soc_S_egu_40018000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_egu_40018000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_egu_40018000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_egu_40018000_P_status "okay"
#define DT_N_S_soc_S_egu_40018000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_egu_40018000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_egu_40018000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_egu_40018000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_egu_40018000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40018000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_egu_40018000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_egu_40018000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_egu_40018000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_egu_40018000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_egu_40018000, status, 0)
#define DT_N_S_soc_S_egu_40018000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_egu_40018000, status, 0)
#define DT_N_S_soc_S_egu_40018000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_egu_40018000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_egu_40018000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_egu_40018000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_egu_40018000_P_status_LEN 1
#define DT_N_S_soc_S_egu_40018000_P_status_EXISTS 1
#define DT_N_S_soc_S_egu_40018000_P_compatible {"nordic,nrf-egu", "nordic,nrf-swi"}
#define DT_N_S_soc_S_egu_40018000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_egu_40018000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-egu
#define DT_N_S_soc_S_egu_40018000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu
#define DT_N_S_soc_S_egu_40018000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU
#define DT_N_S_soc_S_egu_40018000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40018000_P_compatible_IDX_1 "nordic,nrf-swi"
#define DT_N_S_soc_S_egu_40018000_P_compatible_IDX_1_STRING_UNQUOTED nordic,nrf-swi
#define DT_N_S_soc_S_egu_40018000_P_compatible_IDX_1_STRING_TOKEN nordic_nrf_swi
#define DT_N_S_soc_S_egu_40018000_P_compatible_IDX_1_STRING_UPPER_TOKEN NORDIC_NRF_SWI
#define DT_N_S_soc_S_egu_40018000_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_egu_40018000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_egu_40018000, compatible, 0) \
	fn(DT_N_S_soc_S_egu_40018000, compatible, 1)
#define DT_N_S_soc_S_egu_40018000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_egu_40018000, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_egu_40018000, compatible, 1)
#define DT_N_S_soc_S_egu_40018000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_egu_40018000, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_egu_40018000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_egu_40018000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_egu_40018000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_egu_40018000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_egu_40018000_P_compatible_LEN 2
#define DT_N_S_soc_S_egu_40018000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_egu_40018000_P_reg {1073840128 /* 0x40018000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_egu_40018000_P_reg_IDX_0 1073840128
#define DT_N_S_soc_S_egu_40018000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40018000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_egu_40018000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_egu_40018000_P_reg_EXISTS 1
#define DT_N_S_soc_S_egu_40018000_P_interrupts {24 /* 0x18 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_egu_40018000_P_interrupts_IDX_0 24
#define DT_N_S_soc_S_egu_40018000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40018000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_egu_40018000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_egu_40018000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_egu_40018000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_egu_40018000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/egu@40019000
 *
 * Node identifier: DT_N_S_soc_S_egu_40019000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-egu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_egu_40019000_PATH "/soc/egu@40019000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_egu_40019000_FULL_NAME "egu@40019000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_egu_40019000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_egu_40019000_CHILD_IDX 33

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_egu_40019000_CHILD_NUM 0
#define DT_N_S_soc_S_egu_40019000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_egu_40019000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_egu_40019000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_egu_40019000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_egu_40019000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_egu_40019000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_egu_40019000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_egu_40019000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_egu_40019000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_egu_40019000_ORD 84
#define DT_N_S_soc_S_egu_40019000_ORD_STR_SORTABLE 00084

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_egu_40019000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_egu_40019000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_egu_40019000_EXISTS 1
#define DT_N_INST_5_nordic_nrf_egu DT_N_S_soc_S_egu_40019000
#define DT_N_INST_5_nordic_nrf_swi DT_N_S_soc_S_egu_40019000
#define DT_N_NODELABEL_egu5        DT_N_S_soc_S_egu_40019000
#define DT_N_NODELABEL_swi5        DT_N_S_soc_S_egu_40019000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_egu_40019000_REG_NUM 1
#define DT_N_S_soc_S_egu_40019000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40019000_REG_IDX_0_VAL_ADDRESS 1073844224 /* 0x40019000 */
#define DT_N_S_soc_S_egu_40019000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_egu_40019000_RANGES_NUM 0
#define DT_N_S_soc_S_egu_40019000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_egu_40019000_IRQ_NUM 1
#define DT_N_S_soc_S_egu_40019000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40019000_IRQ_IDX_0_VAL_irq 25
#define DT_N_S_soc_S_egu_40019000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_egu_40019000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40019000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_egu_40019000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_egu_40019000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_egu_40019000_IRQ_LEVEL 1
#define DT_N_S_soc_S_egu_40019000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_egu_40019000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40019000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_egu_40019000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40019000_COMPAT_MODEL_IDX_0 "nrf-egu"
#define DT_N_S_soc_S_egu_40019000_COMPAT_MATCHES_nordic_nrf_swi 1
#define DT_N_S_soc_S_egu_40019000_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_egu_40019000_COMPAT_VENDOR_IDX_1 "Nordic Semiconductor"
#define DT_N_S_soc_S_egu_40019000_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_egu_40019000_COMPAT_MODEL_IDX_1 "nrf-swi"
#define DT_N_S_soc_S_egu_40019000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_egu_40019000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_egu_40019000_P_wakeup_source 0
#define DT_N_S_soc_S_egu_40019000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_egu_40019000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_egu_40019000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_egu_40019000_P_status "okay"
#define DT_N_S_soc_S_egu_40019000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_egu_40019000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_egu_40019000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_egu_40019000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_egu_40019000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40019000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_egu_40019000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_egu_40019000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_egu_40019000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_egu_40019000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_egu_40019000, status, 0)
#define DT_N_S_soc_S_egu_40019000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_egu_40019000, status, 0)
#define DT_N_S_soc_S_egu_40019000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_egu_40019000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_egu_40019000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_egu_40019000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_egu_40019000_P_status_LEN 1
#define DT_N_S_soc_S_egu_40019000_P_status_EXISTS 1
#define DT_N_S_soc_S_egu_40019000_P_compatible {"nordic,nrf-egu", "nordic,nrf-swi"}
#define DT_N_S_soc_S_egu_40019000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_egu_40019000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-egu
#define DT_N_S_soc_S_egu_40019000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_egu
#define DT_N_S_soc_S_egu_40019000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_EGU
#define DT_N_S_soc_S_egu_40019000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40019000_P_compatible_IDX_1 "nordic,nrf-swi"
#define DT_N_S_soc_S_egu_40019000_P_compatible_IDX_1_STRING_UNQUOTED nordic,nrf-swi
#define DT_N_S_soc_S_egu_40019000_P_compatible_IDX_1_STRING_TOKEN nordic_nrf_swi
#define DT_N_S_soc_S_egu_40019000_P_compatible_IDX_1_STRING_UPPER_TOKEN NORDIC_NRF_SWI
#define DT_N_S_soc_S_egu_40019000_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_egu_40019000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_egu_40019000, compatible, 0) \
	fn(DT_N_S_soc_S_egu_40019000, compatible, 1)
#define DT_N_S_soc_S_egu_40019000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_egu_40019000, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_egu_40019000, compatible, 1)
#define DT_N_S_soc_S_egu_40019000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_egu_40019000, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_egu_40019000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_egu_40019000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_egu_40019000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_egu_40019000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_egu_40019000_P_compatible_LEN 2
#define DT_N_S_soc_S_egu_40019000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_egu_40019000_P_reg {1073844224 /* 0x40019000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_egu_40019000_P_reg_IDX_0 1073844224
#define DT_N_S_soc_S_egu_40019000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40019000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_egu_40019000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_egu_40019000_P_reg_EXISTS 1
#define DT_N_S_soc_S_egu_40019000_P_interrupts {25 /* 0x19 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_egu_40019000_P_interrupts_IDX_0 25
#define DT_N_S_soc_S_egu_40019000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_egu_40019000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_egu_40019000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_egu_40019000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_egu_40019000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_egu_40019000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/ficr@10000000
 *
 * Node identifier: DT_N_S_soc_S_ficr_10000000
 *
 * Binding (compatible = nordic,nrf-ficr):
 *   $ZEPHYR_BASE/dts/bindings/misc/nordic,nrf-ficr.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_ficr_10000000_PATH "/soc/ficr@10000000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_ficr_10000000_FULL_NAME "ficr@10000000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_ficr_10000000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_ficr_10000000_CHILD_IDX 2

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_ficr_10000000_CHILD_NUM 0
#define DT_N_S_soc_S_ficr_10000000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_ficr_10000000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_ficr_10000000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_ficr_10000000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_ficr_10000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_ficr_10000000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_ficr_10000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_ficr_10000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_ficr_10000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_ficr_10000000_ORD 85
#define DT_N_S_soc_S_ficr_10000000_ORD_STR_SORTABLE 00085

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_ficr_10000000_REQUIRES_ORDS \
	6, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_ficr_10000000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_ficr_10000000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_ficr DT_N_S_soc_S_ficr_10000000
#define DT_N_NODELABEL_ficr         DT_N_S_soc_S_ficr_10000000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_ficr_10000000_REG_NUM 1
#define DT_N_S_soc_S_ficr_10000000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ficr_10000000_REG_IDX_0_VAL_ADDRESS 268435456 /* 0x10000000 */
#define DT_N_S_soc_S_ficr_10000000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_ficr_10000000_RANGES_NUM 0
#define DT_N_S_soc_S_ficr_10000000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_ficr_10000000_IRQ_NUM 0
#define DT_N_S_soc_S_ficr_10000000_IRQ_LEVEL 0
#define DT_N_S_soc_S_ficr_10000000_COMPAT_MATCHES_nordic_nrf_ficr 1
#define DT_N_S_soc_S_ficr_10000000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ficr_10000000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_ficr_10000000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ficr_10000000_COMPAT_MODEL_IDX_0 "nrf-ficr"
#define DT_N_S_soc_S_ficr_10000000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_ficr_10000000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_ficr_10000000_P_wakeup_source 0
#define DT_N_S_soc_S_ficr_10000000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_ficr_10000000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_ficr_10000000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_ficr_10000000_P_status "okay"
#define DT_N_S_soc_S_ficr_10000000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_ficr_10000000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_ficr_10000000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_ficr_10000000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_ficr_10000000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ficr_10000000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_ficr_10000000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_ficr_10000000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_ficr_10000000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_ficr_10000000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ficr_10000000, status, 0)
#define DT_N_S_soc_S_ficr_10000000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ficr_10000000, status, 0)
#define DT_N_S_soc_S_ficr_10000000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ficr_10000000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ficr_10000000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ficr_10000000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ficr_10000000_P_status_LEN 1
#define DT_N_S_soc_S_ficr_10000000_P_status_EXISTS 1
#define DT_N_S_soc_S_ficr_10000000_P_compatible {"nordic,nrf-ficr"}
#define DT_N_S_soc_S_ficr_10000000_P_compatible_IDX_0 "nordic,nrf-ficr"
#define DT_N_S_soc_S_ficr_10000000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-ficr
#define DT_N_S_soc_S_ficr_10000000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_ficr
#define DT_N_S_soc_S_ficr_10000000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_FICR
#define DT_N_S_soc_S_ficr_10000000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ficr_10000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ficr_10000000, compatible, 0)
#define DT_N_S_soc_S_ficr_10000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ficr_10000000, compatible, 0)
#define DT_N_S_soc_S_ficr_10000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ficr_10000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ficr_10000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ficr_10000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ficr_10000000_P_compatible_LEN 1
#define DT_N_S_soc_S_ficr_10000000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_ficr_10000000_P_reg {268435456 /* 0x10000000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_ficr_10000000_P_reg_IDX_0 268435456
#define DT_N_S_soc_S_ficr_10000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ficr_10000000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_ficr_10000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_ficr_10000000_P_reg_EXISTS 1
#define DT_N_S_soc_S_ficr_10000000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_ficr_10000000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/i2c@40003000
 *
 * Node identifier: DT_N_S_soc_S_i2c_40003000
 *
 * Binding (compatible = nordic,nrf-twi):
 *   $ZEPHYR_BASE/dts/bindings/i2c/nordic,nrf-twi.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_i2c_40003000_PATH "/soc/i2c@40003000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_i2c_40003000_FULL_NAME "i2c@40003000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_i2c_40003000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_i2c_40003000_CHILD_IDX 9

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_i2c_40003000_CHILD_NUM 0
#define DT_N_S_soc_S_i2c_40003000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_i2c_40003000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_i2c_40003000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_i2c_40003000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_i2c_40003000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_i2c_40003000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_i2c_40003000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_i2c_40003000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_i2c_40003000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_i2c_40003000_ORD 86
#define DT_N_S_soc_S_i2c_40003000_ORD_STR_SORTABLE 00086

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_i2c_40003000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */ \
	26, /* /pin-controller/i2c0_default */ \
	28, /* /pin-controller/i2c0_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_i2c_40003000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_i2c_40003000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_twi DT_N_S_soc_S_i2c_40003000
#define DT_N_NODELABEL_i2c0        DT_N_S_soc_S_i2c_40003000
#define DT_N_NODELABEL_arduino_i2c DT_N_S_soc_S_i2c_40003000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_i2c_40003000_REG_NUM 1
#define DT_N_S_soc_S_i2c_40003000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_REG_IDX_0_VAL_ADDRESS 1073754112 /* 0x40003000 */
#define DT_N_S_soc_S_i2c_40003000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_i2c_40003000_RANGES_NUM 0
#define DT_N_S_soc_S_i2c_40003000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_i2c_40003000_IRQ_NUM 1
#define DT_N_S_soc_S_i2c_40003000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_IRQ_IDX_0_VAL_irq 3
#define DT_N_S_soc_S_i2c_40003000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_i2c_40003000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_i2c_40003000_IRQ_LEVEL 1
#define DT_N_S_soc_S_i2c_40003000_COMPAT_MATCHES_nordic_nrf_twi 1
#define DT_N_S_soc_S_i2c_40003000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_i2c_40003000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_COMPAT_MODEL_IDX_0 "nrf-twi"
#define DT_N_S_soc_S_i2c_40003000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_i2c_40003000_PINCTRL_NUM 2
#define DT_N_S_soc_S_i2c_40003000_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_i2c_40003000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_i2c_40003000_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_i2c_40003000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_i2c0_default
#define DT_N_S_soc_S_i2c_40003000_PINCTRL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_PINCTRL_IDX_1_TOKEN sleep
#define DT_N_S_soc_S_i2c_40003000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP
#define DT_N_S_soc_S_i2c_40003000_PINCTRL_NAME_sleep_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_PINCTRL_NAME_sleep_IDX 1
#define DT_N_S_soc_S_i2c_40003000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_i2c0_sleep

/* Generic property macros: */
#define DT_N_S_soc_S_i2c_40003000_P_wakeup_source 0
#define DT_N_S_soc_S_i2c_40003000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_i2c_40003000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_P_status "okay"
#define DT_N_S_soc_S_i2c_40003000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_i2c_40003000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_i2c_40003000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_i2c_40003000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_i2c_40003000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_i2c_40003000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_i2c_40003000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_i2c_40003000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40003000, status, 0)
#define DT_N_S_soc_S_i2c_40003000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40003000, status, 0)
#define DT_N_S_soc_S_i2c_40003000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40003000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40003000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40003000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40003000_P_status_LEN 1
#define DT_N_S_soc_S_i2c_40003000_P_status_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_P_compatible {"nordic,nrf-twi"}
#define DT_N_S_soc_S_i2c_40003000_P_compatible_IDX_0 "nordic,nrf-twi"
#define DT_N_S_soc_S_i2c_40003000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-twi
#define DT_N_S_soc_S_i2c_40003000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_twi
#define DT_N_S_soc_S_i2c_40003000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TWI
#define DT_N_S_soc_S_i2c_40003000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40003000, compatible, 0)
#define DT_N_S_soc_S_i2c_40003000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40003000, compatible, 0)
#define DT_N_S_soc_S_i2c_40003000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40003000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40003000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40003000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40003000_P_compatible_LEN 1
#define DT_N_S_soc_S_i2c_40003000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_P_reg {1073754112 /* 0x40003000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_i2c_40003000_P_reg_IDX_0 1073754112
#define DT_N_S_soc_S_i2c_40003000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_i2c_40003000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_P_reg_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_P_interrupts {3 /* 0x3 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_i2c_40003000_P_interrupts_IDX_0 3
#define DT_N_S_soc_S_i2c_40003000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_i2c_40003000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_i2c_40003000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_P_clock_frequency 100000
#define DT_N_S_soc_S_i2c_40003000_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_P_sq_size 4
#define DT_N_S_soc_S_i2c_40003000_P_sq_size_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_P_cq_size 4
#define DT_N_S_soc_S_i2c_40003000_P_cq_size_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_i2c0_default
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_i2c0_default
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40003000, pinctrl_0, 0)
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40003000, pinctrl_0, 0)
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40003000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40003000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_0_LEN 1
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_i2c0_sleep
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_i2c0_sleep
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_1_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40003000, pinctrl_1, 0)
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40003000, pinctrl_1, 0)
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40003000, pinctrl_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40003000, pinctrl_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_1_LEN 1
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_names {"default", "sleep"}
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_names_IDX_1 "sleep"
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40003000, pinctrl_names, 0) \
	fn(DT_N_S_soc_S_i2c_40003000, pinctrl_names, 1)
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40003000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2c_40003000, pinctrl_names, 1)
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40003000, pinctrl_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_i2c_40003000, pinctrl_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40003000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2c_40003000, pinctrl_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_names_LEN 2
#define DT_N_S_soc_S_i2c_40003000_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_i2c_40003000_P_easydma_maxcnt_bits 16
#define DT_N_S_soc_S_i2c_40003000_P_easydma_maxcnt_bits_EXISTS 1

/*
 * Devicetree node: /soc/i2c@40004000
 *
 * Node identifier: DT_N_S_soc_S_i2c_40004000
 *
 * Binding (compatible = nordic,nrf-twi):
 *   $ZEPHYR_BASE/dts/bindings/i2c/nordic,nrf-twi.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_i2c_40004000_PATH "/soc/i2c@40004000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_i2c_40004000_FULL_NAME "i2c@40004000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_i2c_40004000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_i2c_40004000_CHILD_IDX 11

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_i2c_40004000_CHILD_NUM 0
#define DT_N_S_soc_S_i2c_40004000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_i2c_40004000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_i2c_40004000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_i2c_40004000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_i2c_40004000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_i2c_40004000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_i2c_40004000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_i2c_40004000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_i2c_40004000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_i2c_40004000_ORD 87
#define DT_N_S_soc_S_i2c_40004000_ORD_STR_SORTABLE 00087

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_i2c_40004000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */ \
	30, /* /pin-controller/i2c1_default */ \
	32, /* /pin-controller/i2c1_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_i2c_40004000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_i2c_40004000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_twi DT_N_S_soc_S_i2c_40004000
#define DT_N_NODELABEL_i2c1        DT_N_S_soc_S_i2c_40004000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_i2c_40004000_REG_NUM 1
#define DT_N_S_soc_S_i2c_40004000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_REG_IDX_0_VAL_ADDRESS 1073758208 /* 0x40004000 */
#define DT_N_S_soc_S_i2c_40004000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_i2c_40004000_RANGES_NUM 0
#define DT_N_S_soc_S_i2c_40004000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_i2c_40004000_IRQ_NUM 1
#define DT_N_S_soc_S_i2c_40004000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_IRQ_IDX_0_VAL_irq 4
#define DT_N_S_soc_S_i2c_40004000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_i2c_40004000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_i2c_40004000_IRQ_LEVEL 1
#define DT_N_S_soc_S_i2c_40004000_COMPAT_MATCHES_nordic_nrf_twi 1
#define DT_N_S_soc_S_i2c_40004000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_i2c_40004000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_COMPAT_MODEL_IDX_0 "nrf-twi"
#define DT_N_S_soc_S_i2c_40004000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_i2c_40004000_PINCTRL_NUM 2
#define DT_N_S_soc_S_i2c_40004000_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_i2c_40004000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_i2c_40004000_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_i2c_40004000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_i2c1_default
#define DT_N_S_soc_S_i2c_40004000_PINCTRL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_PINCTRL_IDX_1_TOKEN sleep
#define DT_N_S_soc_S_i2c_40004000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP
#define DT_N_S_soc_S_i2c_40004000_PINCTRL_NAME_sleep_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_PINCTRL_NAME_sleep_IDX 1
#define DT_N_S_soc_S_i2c_40004000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_i2c1_sleep

/* Generic property macros: */
#define DT_N_S_soc_S_i2c_40004000_P_wakeup_source 0
#define DT_N_S_soc_S_i2c_40004000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_i2c_40004000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_P_status "disabled"
#define DT_N_S_soc_S_i2c_40004000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_i2c_40004000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_i2c_40004000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_i2c_40004000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_i2c_40004000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_i2c_40004000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_i2c_40004000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_i2c_40004000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40004000, status, 0)
#define DT_N_S_soc_S_i2c_40004000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40004000, status, 0)
#define DT_N_S_soc_S_i2c_40004000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40004000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40004000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40004000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40004000_P_status_LEN 1
#define DT_N_S_soc_S_i2c_40004000_P_status_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_P_compatible {"nordic,nrf-twi"}
#define DT_N_S_soc_S_i2c_40004000_P_compatible_IDX_0 "nordic,nrf-twi"
#define DT_N_S_soc_S_i2c_40004000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-twi
#define DT_N_S_soc_S_i2c_40004000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_twi
#define DT_N_S_soc_S_i2c_40004000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TWI
#define DT_N_S_soc_S_i2c_40004000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40004000, compatible, 0)
#define DT_N_S_soc_S_i2c_40004000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40004000, compatible, 0)
#define DT_N_S_soc_S_i2c_40004000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40004000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40004000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40004000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40004000_P_compatible_LEN 1
#define DT_N_S_soc_S_i2c_40004000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_P_reg {1073758208 /* 0x40004000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_i2c_40004000_P_reg_IDX_0 1073758208
#define DT_N_S_soc_S_i2c_40004000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_i2c_40004000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_P_reg_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_P_interrupts {4 /* 0x4 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_i2c_40004000_P_interrupts_IDX_0 4
#define DT_N_S_soc_S_i2c_40004000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_i2c_40004000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_i2c_40004000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_P_clock_frequency 100000
#define DT_N_S_soc_S_i2c_40004000_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_P_sq_size 4
#define DT_N_S_soc_S_i2c_40004000_P_sq_size_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_P_cq_size 4
#define DT_N_S_soc_S_i2c_40004000_P_cq_size_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_i2c1_default
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_i2c1_default
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40004000, pinctrl_0, 0)
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40004000, pinctrl_0, 0)
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40004000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40004000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_0_LEN 1
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_i2c1_sleep
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_i2c1_sleep
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_1_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40004000, pinctrl_1, 0)
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40004000, pinctrl_1, 0)
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40004000, pinctrl_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40004000, pinctrl_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_1_LEN 1
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_names {"default", "sleep"}
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_names_IDX_1 "sleep"
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40004000, pinctrl_names, 0) \
	fn(DT_N_S_soc_S_i2c_40004000, pinctrl_names, 1)
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40004000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2c_40004000, pinctrl_names, 1)
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40004000, pinctrl_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_i2c_40004000, pinctrl_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40004000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2c_40004000, pinctrl_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_names_LEN 2
#define DT_N_S_soc_S_i2c_40004000_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_i2c_40004000_P_easydma_maxcnt_bits 16
#define DT_N_S_soc_S_i2c_40004000_P_easydma_maxcnt_bits_EXISTS 1

/*
 * Devicetree node: /soc/i2s@40025000
 *
 * Node identifier: DT_N_S_soc_S_i2s_40025000
 *
 * Binding (compatible = nordic,nrf-i2s):
 *   $ZEPHYR_BASE/dts/bindings/i2s/nordic,nrf-i2s.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_i2s_40025000_PATH "/soc/i2s@40025000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_i2s_40025000_FULL_NAME "i2s@40025000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_i2s_40025000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_i2s_40025000_CHILD_IDX 46

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_i2s_40025000_CHILD_NUM 0
#define DT_N_S_soc_S_i2s_40025000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_i2s_40025000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_i2s_40025000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_i2s_40025000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_i2s_40025000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_i2s_40025000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_i2s_40025000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_i2s_40025000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_i2s_40025000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_i2s_40025000_ORD 88
#define DT_N_S_soc_S_i2s_40025000_ORD_STR_SORTABLE 00088

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_i2s_40025000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_i2s_40025000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_i2s_40025000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_i2s DT_N_S_soc_S_i2s_40025000
#define DT_N_NODELABEL_i2s0        DT_N_S_soc_S_i2s_40025000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_i2s_40025000_REG_NUM 1
#define DT_N_S_soc_S_i2s_40025000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40025000_REG_IDX_0_VAL_ADDRESS 1073893376 /* 0x40025000 */
#define DT_N_S_soc_S_i2s_40025000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_i2s_40025000_RANGES_NUM 0
#define DT_N_S_soc_S_i2s_40025000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_i2s_40025000_IRQ_NUM 1
#define DT_N_S_soc_S_i2s_40025000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40025000_IRQ_IDX_0_VAL_irq 37
#define DT_N_S_soc_S_i2s_40025000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2s_40025000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40025000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_i2s_40025000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2s_40025000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_i2s_40025000_IRQ_LEVEL 1
#define DT_N_S_soc_S_i2s_40025000_COMPAT_MATCHES_nordic_nrf_i2s 1
#define DT_N_S_soc_S_i2s_40025000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40025000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_i2s_40025000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40025000_COMPAT_MODEL_IDX_0 "nrf-i2s"
#define DT_N_S_soc_S_i2s_40025000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_i2s_40025000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_i2s_40025000_P_wakeup_source 0
#define DT_N_S_soc_S_i2s_40025000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_i2s_40025000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_i2s_40025000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_i2s_40025000_P_status "disabled"
#define DT_N_S_soc_S_i2s_40025000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_i2s_40025000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_i2s_40025000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_i2s_40025000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_i2s_40025000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40025000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_i2s_40025000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_i2s_40025000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_i2s_40025000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_i2s_40025000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40025000, status, 0)
#define DT_N_S_soc_S_i2s_40025000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40025000, status, 0)
#define DT_N_S_soc_S_i2s_40025000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40025000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_40025000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40025000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_40025000_P_status_LEN 1
#define DT_N_S_soc_S_i2s_40025000_P_status_EXISTS 1
#define DT_N_S_soc_S_i2s_40025000_P_compatible {"nordic,nrf-i2s"}
#define DT_N_S_soc_S_i2s_40025000_P_compatible_IDX_0 "nordic,nrf-i2s"
#define DT_N_S_soc_S_i2s_40025000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-i2s
#define DT_N_S_soc_S_i2s_40025000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_i2s
#define DT_N_S_soc_S_i2s_40025000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_I2S
#define DT_N_S_soc_S_i2s_40025000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40025000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40025000, compatible, 0)
#define DT_N_S_soc_S_i2s_40025000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40025000, compatible, 0)
#define DT_N_S_soc_S_i2s_40025000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40025000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_40025000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40025000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_40025000_P_compatible_LEN 1
#define DT_N_S_soc_S_i2s_40025000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_i2s_40025000_P_reg {1073893376 /* 0x40025000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_i2s_40025000_P_reg_IDX_0 1073893376
#define DT_N_S_soc_S_i2s_40025000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40025000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_i2s_40025000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2s_40025000_P_reg_EXISTS 1
#define DT_N_S_soc_S_i2s_40025000_P_interrupts {37 /* 0x25 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_i2s_40025000_P_interrupts_IDX_0 37
#define DT_N_S_soc_S_i2s_40025000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40025000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_i2s_40025000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2s_40025000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_i2s_40025000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_i2s_40025000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_i2s_40025000_P_clock_source "PCLK32M_HFXO"
#define DT_N_S_soc_S_i2s_40025000_P_clock_source_STRING_UNQUOTED PCLK32M_HFXO
#define DT_N_S_soc_S_i2s_40025000_P_clock_source_STRING_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_i2s_40025000_P_clock_source_STRING_UPPER_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_i2s_40025000_P_clock_source_IDX_0 "PCLK32M_HFXO"
#define DT_N_S_soc_S_i2s_40025000_P_clock_source_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_40025000_P_clock_source_ENUM_IDX 1
#define DT_N_S_soc_S_i2s_40025000_P_clock_source_ENUM_VAL_PCLK32M_HFXO_EXISTS 1
#define DT_N_S_soc_S_i2s_40025000_P_clock_source_ENUM_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_i2s_40025000_P_clock_source_ENUM_UPPER_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_i2s_40025000_P_clock_source_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40025000, clock_source, 0)
#define DT_N_S_soc_S_i2s_40025000_P_clock_source_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40025000, clock_source, 0)
#define DT_N_S_soc_S_i2s_40025000_P_clock_source_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40025000, clock_source, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_40025000_P_clock_source_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40025000, clock_source, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_40025000_P_clock_source_LEN 1
#define DT_N_S_soc_S_i2s_40025000_P_clock_source_EXISTS 1

/*
 * Devicetree node: /soc/memory@20000000
 *
 * Node identifier: DT_N_S_soc_S_memory_20000000
 *
 * Binding (compatible = mmio-sram):
 *   $ZEPHYR_BASE/dts/bindings/sram/mmio-sram.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_memory_20000000_PATH "/soc/memory@20000000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_memory_20000000_FULL_NAME "memory@20000000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_memory_20000000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_memory_20000000_CHILD_IDX 4

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_memory_20000000_CHILD_NUM 0
#define DT_N_S_soc_S_memory_20000000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_memory_20000000_ORD 89
#define DT_N_S_soc_S_memory_20000000_ORD_STR_SORTABLE 00089

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_memory_20000000_REQUIRES_ORDS \
	6, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_memory_20000000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_memory_20000000_EXISTS 1
#define DT_N_INST_0_mmio_sram DT_N_S_soc_S_memory_20000000
#define DT_N_NODELABEL_sram0  DT_N_S_soc_S_memory_20000000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_memory_20000000_REG_NUM 1
#define DT_N_S_soc_S_memory_20000000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_REG_IDX_0_VAL_ADDRESS 536870912 /* 0x20000000 */
#define DT_N_S_soc_S_memory_20000000_REG_IDX_0_VAL_SIZE 262144 /* 0x40000 */
#define DT_N_S_soc_S_memory_20000000_RANGES_NUM 0
#define DT_N_S_soc_S_memory_20000000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_memory_20000000_IRQ_NUM 0
#define DT_N_S_soc_S_memory_20000000_IRQ_LEVEL 0
#define DT_N_S_soc_S_memory_20000000_COMPAT_MATCHES_mmio_sram 1
#define DT_N_S_soc_S_memory_20000000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_memory_20000000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_memory_20000000_P_wakeup_source 0
#define DT_N_S_soc_S_memory_20000000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_memory_20000000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_compatible {"mmio-sram"}
#define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0 "mmio-sram"
#define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_STRING_UNQUOTED mmio-sram
#define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_STRING_TOKEN mmio_sram
#define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_STRING_UPPER_TOKEN MMIO_SRAM
#define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_20000000, compatible, 0)
#define DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_20000000, compatible, 0)
#define DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_20000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_20000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_20000000_P_compatible_LEN 1
#define DT_N_S_soc_S_memory_20000000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_reg {536870912 /* 0x20000000 */, 262144 /* 0x40000 */}
#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_0 536870912
#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_1 262144
#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_reg_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_memory_20000000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/mwu@40020000
 *
 * Node identifier: DT_N_S_soc_S_mwu_40020000
 *
 * Binding (compatible = nordic,nrf-mwu):
 *   $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-mwu.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_mwu_40020000_PATH "/soc/mwu@40020000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_mwu_40020000_FULL_NAME "mwu@40020000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_mwu_40020000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_mwu_40020000_CHILD_IDX 41

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_mwu_40020000_CHILD_NUM 0
#define DT_N_S_soc_S_mwu_40020000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_mwu_40020000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_mwu_40020000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_mwu_40020000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_mwu_40020000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_mwu_40020000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_mwu_40020000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_mwu_40020000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_mwu_40020000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_mwu_40020000_ORD 90
#define DT_N_S_soc_S_mwu_40020000_ORD_STR_SORTABLE 00090

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_mwu_40020000_REQUIRES_ORDS \
	6, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_mwu_40020000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_mwu_40020000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_mwu DT_N_S_soc_S_mwu_40020000
#define DT_N_NODELABEL_mwu         DT_N_S_soc_S_mwu_40020000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_mwu_40020000_REG_NUM 1
#define DT_N_S_soc_S_mwu_40020000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mwu_40020000_REG_IDX_0_VAL_ADDRESS 1073872896 /* 0x40020000 */
#define DT_N_S_soc_S_mwu_40020000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_mwu_40020000_RANGES_NUM 0
#define DT_N_S_soc_S_mwu_40020000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_mwu_40020000_IRQ_NUM 0
#define DT_N_S_soc_S_mwu_40020000_IRQ_LEVEL 0
#define DT_N_S_soc_S_mwu_40020000_COMPAT_MATCHES_nordic_nrf_mwu 1
#define DT_N_S_soc_S_mwu_40020000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mwu_40020000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_mwu_40020000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mwu_40020000_COMPAT_MODEL_IDX_0 "nrf-mwu"
#define DT_N_S_soc_S_mwu_40020000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_mwu_40020000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_mwu_40020000_P_wakeup_source 0
#define DT_N_S_soc_S_mwu_40020000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_mwu_40020000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_mwu_40020000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_mwu_40020000_P_status "okay"
#define DT_N_S_soc_S_mwu_40020000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_mwu_40020000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_mwu_40020000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_mwu_40020000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_mwu_40020000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mwu_40020000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_mwu_40020000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_mwu_40020000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_mwu_40020000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_mwu_40020000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_mwu_40020000, status, 0)
#define DT_N_S_soc_S_mwu_40020000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_mwu_40020000, status, 0)
#define DT_N_S_soc_S_mwu_40020000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_mwu_40020000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mwu_40020000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_mwu_40020000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mwu_40020000_P_status_LEN 1
#define DT_N_S_soc_S_mwu_40020000_P_status_EXISTS 1
#define DT_N_S_soc_S_mwu_40020000_P_compatible {"nordic,nrf-mwu"}
#define DT_N_S_soc_S_mwu_40020000_P_compatible_IDX_0 "nordic,nrf-mwu"
#define DT_N_S_soc_S_mwu_40020000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-mwu
#define DT_N_S_soc_S_mwu_40020000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_mwu
#define DT_N_S_soc_S_mwu_40020000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_MWU
#define DT_N_S_soc_S_mwu_40020000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mwu_40020000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_mwu_40020000, compatible, 0)
#define DT_N_S_soc_S_mwu_40020000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_mwu_40020000, compatible, 0)
#define DT_N_S_soc_S_mwu_40020000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_mwu_40020000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mwu_40020000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_mwu_40020000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mwu_40020000_P_compatible_LEN 1
#define DT_N_S_soc_S_mwu_40020000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_mwu_40020000_P_reg {1073872896 /* 0x40020000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_mwu_40020000_P_reg_IDX_0 1073872896
#define DT_N_S_soc_S_mwu_40020000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mwu_40020000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_mwu_40020000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_mwu_40020000_P_reg_EXISTS 1
#define DT_N_S_soc_S_mwu_40020000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_mwu_40020000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/nfct@40005000
 *
 * Node identifier: DT_N_S_soc_S_nfct_40005000
 *
 * Binding (compatible = nordic,nrf-nfct):
 *   $ZEPHYR_BASE/dts/bindings/net/wireless/nordic,nrf-nfct.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_nfct_40005000_PATH "/soc/nfct@40005000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_nfct_40005000_FULL_NAME "nfct@40005000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_nfct_40005000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_nfct_40005000_CHILD_IDX 13

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_nfct_40005000_CHILD_NUM 0
#define DT_N_S_soc_S_nfct_40005000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_nfct_40005000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_nfct_40005000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_nfct_40005000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_nfct_40005000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_nfct_40005000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_nfct_40005000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_nfct_40005000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_nfct_40005000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_nfct_40005000_ORD 91
#define DT_N_S_soc_S_nfct_40005000_ORD_STR_SORTABLE 00091

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_nfct_40005000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_nfct_40005000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_nfct_40005000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_nfct DT_N_S_soc_S_nfct_40005000
#define DT_N_NODELABEL_nfct         DT_N_S_soc_S_nfct_40005000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_nfct_40005000_REG_NUM 1
#define DT_N_S_soc_S_nfct_40005000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_nfct_40005000_REG_IDX_0_VAL_ADDRESS 1073762304 /* 0x40005000 */
#define DT_N_S_soc_S_nfct_40005000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_nfct_40005000_RANGES_NUM 0
#define DT_N_S_soc_S_nfct_40005000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_nfct_40005000_IRQ_NUM 1
#define DT_N_S_soc_S_nfct_40005000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_nfct_40005000_IRQ_IDX_0_VAL_irq 5
#define DT_N_S_soc_S_nfct_40005000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_nfct_40005000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_nfct_40005000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_nfct_40005000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_nfct_40005000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_nfct_40005000_IRQ_LEVEL 1
#define DT_N_S_soc_S_nfct_40005000_COMPAT_MATCHES_nordic_nrf_nfct 1
#define DT_N_S_soc_S_nfct_40005000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_nfct_40005000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_nfct_40005000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_nfct_40005000_COMPAT_MODEL_IDX_0 "nrf-nfct"
#define DT_N_S_soc_S_nfct_40005000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_nfct_40005000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_nfct_40005000_P_wakeup_source 0
#define DT_N_S_soc_S_nfct_40005000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_nfct_40005000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_nfct_40005000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_nfct_40005000_P_status "disabled"
#define DT_N_S_soc_S_nfct_40005000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_nfct_40005000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_nfct_40005000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_nfct_40005000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_nfct_40005000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_nfct_40005000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_nfct_40005000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_nfct_40005000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_nfct_40005000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_nfct_40005000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_nfct_40005000, status, 0)
#define DT_N_S_soc_S_nfct_40005000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_nfct_40005000, status, 0)
#define DT_N_S_soc_S_nfct_40005000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_nfct_40005000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_nfct_40005000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_nfct_40005000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_nfct_40005000_P_status_LEN 1
#define DT_N_S_soc_S_nfct_40005000_P_status_EXISTS 1
#define DT_N_S_soc_S_nfct_40005000_P_compatible {"nordic,nrf-nfct"}
#define DT_N_S_soc_S_nfct_40005000_P_compatible_IDX_0 "nordic,nrf-nfct"
#define DT_N_S_soc_S_nfct_40005000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-nfct
#define DT_N_S_soc_S_nfct_40005000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_nfct
#define DT_N_S_soc_S_nfct_40005000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_NFCT
#define DT_N_S_soc_S_nfct_40005000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_nfct_40005000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_nfct_40005000, compatible, 0)
#define DT_N_S_soc_S_nfct_40005000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_nfct_40005000, compatible, 0)
#define DT_N_S_soc_S_nfct_40005000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_nfct_40005000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_nfct_40005000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_nfct_40005000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_nfct_40005000_P_compatible_LEN 1
#define DT_N_S_soc_S_nfct_40005000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_nfct_40005000_P_reg {1073762304 /* 0x40005000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_nfct_40005000_P_reg_IDX_0 1073762304
#define DT_N_S_soc_S_nfct_40005000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_nfct_40005000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_nfct_40005000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_nfct_40005000_P_reg_EXISTS 1
#define DT_N_S_soc_S_nfct_40005000_P_interrupts {5 /* 0x5 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_nfct_40005000_P_interrupts_IDX_0 5
#define DT_N_S_soc_S_nfct_40005000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_nfct_40005000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_nfct_40005000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_nfct_40005000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_nfct_40005000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_nfct_40005000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/pdm@4001d000
 *
 * Node identifier: DT_N_S_soc_S_pdm_4001d000
 *
 * Binding (compatible = nordic,nrf-pdm):
 *   $ZEPHYR_BASE/dts/bindings/audio/nordic,nrf-pdm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pdm_4001d000_PATH "/soc/pdm@4001d000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pdm_4001d000_FULL_NAME "pdm@4001d000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_pdm_4001d000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pdm_4001d000_CHILD_IDX 37

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pdm_4001d000_CHILD_NUM 0
#define DT_N_S_soc_S_pdm_4001d000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pdm_4001d000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pdm_4001d000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pdm_4001d000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pdm_4001d000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pdm_4001d000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pdm_4001d000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pdm_4001d000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pdm_4001d000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pdm_4001d000_ORD 92
#define DT_N_S_soc_S_pdm_4001d000_ORD_STR_SORTABLE 00092

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pdm_4001d000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pdm_4001d000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pdm_4001d000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_pdm DT_N_S_soc_S_pdm_4001d000
#define DT_N_NODELABEL_pdm0        DT_N_S_soc_S_pdm_4001d000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pdm_4001d000_REG_NUM 1
#define DT_N_S_soc_S_pdm_4001d000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pdm_4001d000_REG_IDX_0_VAL_ADDRESS 1073860608 /* 0x4001d000 */
#define DT_N_S_soc_S_pdm_4001d000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_pdm_4001d000_RANGES_NUM 0
#define DT_N_S_soc_S_pdm_4001d000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pdm_4001d000_IRQ_NUM 1
#define DT_N_S_soc_S_pdm_4001d000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pdm_4001d000_IRQ_IDX_0_VAL_irq 29
#define DT_N_S_soc_S_pdm_4001d000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_pdm_4001d000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pdm_4001d000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_pdm_4001d000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_pdm_4001d000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_pdm_4001d000_IRQ_LEVEL 1
#define DT_N_S_soc_S_pdm_4001d000_COMPAT_MATCHES_nordic_nrf_pdm 1
#define DT_N_S_soc_S_pdm_4001d000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pdm_4001d000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_pdm_4001d000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pdm_4001d000_COMPAT_MODEL_IDX_0 "nrf-pdm"
#define DT_N_S_soc_S_pdm_4001d000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pdm_4001d000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pdm_4001d000_P_wakeup_source 0
#define DT_N_S_soc_S_pdm_4001d000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_pdm_4001d000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_pdm_4001d000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_pdm_4001d000_P_status "disabled"
#define DT_N_S_soc_S_pdm_4001d000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_pdm_4001d000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_pdm_4001d000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_pdm_4001d000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_pdm_4001d000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pdm_4001d000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_pdm_4001d000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_pdm_4001d000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_pdm_4001d000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_pdm_4001d000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pdm_4001d000, status, 0)
#define DT_N_S_soc_S_pdm_4001d000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pdm_4001d000, status, 0)
#define DT_N_S_soc_S_pdm_4001d000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pdm_4001d000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pdm_4001d000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pdm_4001d000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pdm_4001d000_P_status_LEN 1
#define DT_N_S_soc_S_pdm_4001d000_P_status_EXISTS 1
#define DT_N_S_soc_S_pdm_4001d000_P_compatible {"nordic,nrf-pdm"}
#define DT_N_S_soc_S_pdm_4001d000_P_compatible_IDX_0 "nordic,nrf-pdm"
#define DT_N_S_soc_S_pdm_4001d000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pdm
#define DT_N_S_soc_S_pdm_4001d000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pdm
#define DT_N_S_soc_S_pdm_4001d000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PDM
#define DT_N_S_soc_S_pdm_4001d000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pdm_4001d000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pdm_4001d000, compatible, 0)
#define DT_N_S_soc_S_pdm_4001d000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pdm_4001d000, compatible, 0)
#define DT_N_S_soc_S_pdm_4001d000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pdm_4001d000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pdm_4001d000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pdm_4001d000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pdm_4001d000_P_compatible_LEN 1
#define DT_N_S_soc_S_pdm_4001d000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_pdm_4001d000_P_reg {1073860608 /* 0x4001d000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_pdm_4001d000_P_reg_IDX_0 1073860608
#define DT_N_S_soc_S_pdm_4001d000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pdm_4001d000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_pdm_4001d000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pdm_4001d000_P_reg_EXISTS 1
#define DT_N_S_soc_S_pdm_4001d000_P_interrupts {29 /* 0x1d */, 1 /* 0x1 */}
#define DT_N_S_soc_S_pdm_4001d000_P_interrupts_IDX_0 29
#define DT_N_S_soc_S_pdm_4001d000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pdm_4001d000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_pdm_4001d000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pdm_4001d000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_pdm_4001d000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_pdm_4001d000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_pdm_4001d000_P_clock_source "PCLK32M_HFXO"
#define DT_N_S_soc_S_pdm_4001d000_P_clock_source_STRING_UNQUOTED PCLK32M_HFXO
#define DT_N_S_soc_S_pdm_4001d000_P_clock_source_STRING_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_pdm_4001d000_P_clock_source_STRING_UPPER_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_pdm_4001d000_P_clock_source_IDX_0 "PCLK32M_HFXO"
#define DT_N_S_soc_S_pdm_4001d000_P_clock_source_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pdm_4001d000_P_clock_source_ENUM_IDX 1
#define DT_N_S_soc_S_pdm_4001d000_P_clock_source_ENUM_VAL_PCLK32M_HFXO_EXISTS 1
#define DT_N_S_soc_S_pdm_4001d000_P_clock_source_ENUM_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_pdm_4001d000_P_clock_source_ENUM_UPPER_TOKEN PCLK32M_HFXO
#define DT_N_S_soc_S_pdm_4001d000_P_clock_source_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pdm_4001d000, clock_source, 0)
#define DT_N_S_soc_S_pdm_4001d000_P_clock_source_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pdm_4001d000, clock_source, 0)
#define DT_N_S_soc_S_pdm_4001d000_P_clock_source_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pdm_4001d000, clock_source, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pdm_4001d000_P_clock_source_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pdm_4001d000, clock_source, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pdm_4001d000_P_clock_source_LEN 1
#define DT_N_S_soc_S_pdm_4001d000_P_clock_source_EXISTS 1
#define DT_N_S_soc_S_pdm_4001d000_P_queue_size 4
#define DT_N_S_soc_S_pdm_4001d000_P_queue_size_EXISTS 1

/*
 * Devicetree node: /soc/ppi@4001f000
 *
 * Node identifier: DT_N_S_soc_S_ppi_4001f000
 *
 * Binding (compatible = nordic,nrf-ppi):
 *   $ZEPHYR_BASE/dts/bindings/misc/nordic,nrf-ppi.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_ppi_4001f000_PATH "/soc/ppi@4001f000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_ppi_4001f000_FULL_NAME "ppi@4001f000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_ppi_4001f000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_ppi_4001f000_CHILD_IDX 40

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_ppi_4001f000_CHILD_NUM 0
#define DT_N_S_soc_S_ppi_4001f000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_ppi_4001f000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_ppi_4001f000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_ppi_4001f000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_ppi_4001f000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_ppi_4001f000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_ppi_4001f000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_ppi_4001f000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_ppi_4001f000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_ppi_4001f000_ORD 93
#define DT_N_S_soc_S_ppi_4001f000_ORD_STR_SORTABLE 00093

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_ppi_4001f000_REQUIRES_ORDS \
	6, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_ppi_4001f000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_ppi_4001f000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_ppi DT_N_S_soc_S_ppi_4001f000
#define DT_N_NODELABEL_ppi         DT_N_S_soc_S_ppi_4001f000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_ppi_4001f000_REG_NUM 1
#define DT_N_S_soc_S_ppi_4001f000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ppi_4001f000_REG_IDX_0_VAL_ADDRESS 1073868800 /* 0x4001f000 */
#define DT_N_S_soc_S_ppi_4001f000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_ppi_4001f000_RANGES_NUM 0
#define DT_N_S_soc_S_ppi_4001f000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_ppi_4001f000_IRQ_NUM 0
#define DT_N_S_soc_S_ppi_4001f000_IRQ_LEVEL 0
#define DT_N_S_soc_S_ppi_4001f000_COMPAT_MATCHES_nordic_nrf_ppi 1
#define DT_N_S_soc_S_ppi_4001f000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ppi_4001f000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_ppi_4001f000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ppi_4001f000_COMPAT_MODEL_IDX_0 "nrf-ppi"
#define DT_N_S_soc_S_ppi_4001f000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_ppi_4001f000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_ppi_4001f000_P_wakeup_source 0
#define DT_N_S_soc_S_ppi_4001f000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_ppi_4001f000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_ppi_4001f000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_ppi_4001f000_P_status "okay"
#define DT_N_S_soc_S_ppi_4001f000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_ppi_4001f000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_ppi_4001f000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_ppi_4001f000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_ppi_4001f000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ppi_4001f000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_ppi_4001f000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_ppi_4001f000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_ppi_4001f000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_ppi_4001f000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ppi_4001f000, status, 0)
#define DT_N_S_soc_S_ppi_4001f000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ppi_4001f000, status, 0)
#define DT_N_S_soc_S_ppi_4001f000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ppi_4001f000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ppi_4001f000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ppi_4001f000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ppi_4001f000_P_status_LEN 1
#define DT_N_S_soc_S_ppi_4001f000_P_status_EXISTS 1
#define DT_N_S_soc_S_ppi_4001f000_P_compatible {"nordic,nrf-ppi"}
#define DT_N_S_soc_S_ppi_4001f000_P_compatible_IDX_0 "nordic,nrf-ppi"
#define DT_N_S_soc_S_ppi_4001f000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-ppi
#define DT_N_S_soc_S_ppi_4001f000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_ppi
#define DT_N_S_soc_S_ppi_4001f000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PPI
#define DT_N_S_soc_S_ppi_4001f000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ppi_4001f000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ppi_4001f000, compatible, 0)
#define DT_N_S_soc_S_ppi_4001f000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ppi_4001f000, compatible, 0)
#define DT_N_S_soc_S_ppi_4001f000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ppi_4001f000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ppi_4001f000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ppi_4001f000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ppi_4001f000_P_compatible_LEN 1
#define DT_N_S_soc_S_ppi_4001f000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_ppi_4001f000_P_reg {1073868800 /* 0x4001f000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_ppi_4001f000_P_reg_IDX_0 1073868800
#define DT_N_S_soc_S_ppi_4001f000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ppi_4001f000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_ppi_4001f000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_ppi_4001f000_P_reg_EXISTS 1
#define DT_N_S_soc_S_ppi_4001f000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_ppi_4001f000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/pwm@40021000
 *
 * Node identifier: DT_N_S_soc_S_pwm_40021000
 *
 * Binding (compatible = nordic,nrf-pwm):
 *   $ZEPHYR_BASE/dts/bindings/pwm/nordic,nrf-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pwm_40021000_PATH "/soc/pwm@40021000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pwm_40021000_FULL_NAME "pwm@40021000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_pwm_40021000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pwm_40021000_CHILD_IDX 42

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pwm_40021000_CHILD_NUM 0
#define DT_N_S_soc_S_pwm_40021000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pwm_40021000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pwm_40021000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pwm_40021000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pwm_40021000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pwm_40021000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pwm_40021000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pwm_40021000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pwm_40021000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pwm_40021000_ORD 94
#define DT_N_S_soc_S_pwm_40021000_ORD_STR_SORTABLE 00094

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pwm_40021000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pwm_40021000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pwm_40021000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_pwm DT_N_S_soc_S_pwm_40021000
#define DT_N_NODELABEL_pwm1        DT_N_S_soc_S_pwm_40021000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pwm_40021000_REG_NUM 1
#define DT_N_S_soc_S_pwm_40021000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_40021000_REG_IDX_0_VAL_ADDRESS 1073876992 /* 0x40021000 */
#define DT_N_S_soc_S_pwm_40021000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_pwm_40021000_RANGES_NUM 0
#define DT_N_S_soc_S_pwm_40021000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pwm_40021000_IRQ_NUM 1
#define DT_N_S_soc_S_pwm_40021000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_40021000_IRQ_IDX_0_VAL_irq 33
#define DT_N_S_soc_S_pwm_40021000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_pwm_40021000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_40021000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_pwm_40021000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_pwm_40021000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_pwm_40021000_IRQ_LEVEL 1
#define DT_N_S_soc_S_pwm_40021000_COMPAT_MATCHES_nordic_nrf_pwm 1
#define DT_N_S_soc_S_pwm_40021000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_40021000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_pwm_40021000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_40021000_COMPAT_MODEL_IDX_0 "nrf-pwm"
#define DT_N_S_soc_S_pwm_40021000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pwm_40021000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pwm_40021000_P_wakeup_source 0
#define DT_N_S_soc_S_pwm_40021000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_pwm_40021000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_pwm_40021000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_pwm_40021000_P_status "disabled"
#define DT_N_S_soc_S_pwm_40021000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_pwm_40021000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_pwm_40021000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_pwm_40021000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_pwm_40021000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_40021000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_pwm_40021000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_pwm_40021000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_pwm_40021000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_pwm_40021000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pwm_40021000, status, 0)
#define DT_N_S_soc_S_pwm_40021000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pwm_40021000, status, 0)
#define DT_N_S_soc_S_pwm_40021000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pwm_40021000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pwm_40021000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pwm_40021000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pwm_40021000_P_status_LEN 1
#define DT_N_S_soc_S_pwm_40021000_P_status_EXISTS 1
#define DT_N_S_soc_S_pwm_40021000_P_compatible {"nordic,nrf-pwm"}
#define DT_N_S_soc_S_pwm_40021000_P_compatible_IDX_0 "nordic,nrf-pwm"
#define DT_N_S_soc_S_pwm_40021000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pwm
#define DT_N_S_soc_S_pwm_40021000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pwm
#define DT_N_S_soc_S_pwm_40021000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PWM
#define DT_N_S_soc_S_pwm_40021000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_40021000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pwm_40021000, compatible, 0)
#define DT_N_S_soc_S_pwm_40021000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pwm_40021000, compatible, 0)
#define DT_N_S_soc_S_pwm_40021000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pwm_40021000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pwm_40021000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pwm_40021000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pwm_40021000_P_compatible_LEN 1
#define DT_N_S_soc_S_pwm_40021000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_pwm_40021000_P_reg {1073876992 /* 0x40021000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_pwm_40021000_P_reg_IDX_0 1073876992
#define DT_N_S_soc_S_pwm_40021000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_40021000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_pwm_40021000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pwm_40021000_P_reg_EXISTS 1
#define DT_N_S_soc_S_pwm_40021000_P_interrupts {33 /* 0x21 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_pwm_40021000_P_interrupts_IDX_0 33
#define DT_N_S_soc_S_pwm_40021000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_40021000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_pwm_40021000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pwm_40021000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_pwm_40021000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_pwm_40021000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_pwm_40021000_P_center_aligned 0
#define DT_N_S_soc_S_pwm_40021000_P_center_aligned_EXISTS 1

/*
 * Devicetree node: /soc/pwm@40022000
 *
 * Node identifier: DT_N_S_soc_S_pwm_40022000
 *
 * Binding (compatible = nordic,nrf-pwm):
 *   $ZEPHYR_BASE/dts/bindings/pwm/nordic,nrf-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pwm_40022000_PATH "/soc/pwm@40022000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pwm_40022000_FULL_NAME "pwm@40022000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_pwm_40022000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pwm_40022000_CHILD_IDX 43

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pwm_40022000_CHILD_NUM 0
#define DT_N_S_soc_S_pwm_40022000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pwm_40022000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pwm_40022000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pwm_40022000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pwm_40022000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pwm_40022000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pwm_40022000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pwm_40022000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pwm_40022000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pwm_40022000_ORD 95
#define DT_N_S_soc_S_pwm_40022000_ORD_STR_SORTABLE 00095

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pwm_40022000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pwm_40022000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pwm_40022000_EXISTS 1
#define DT_N_INST_2_nordic_nrf_pwm DT_N_S_soc_S_pwm_40022000
#define DT_N_NODELABEL_pwm2        DT_N_S_soc_S_pwm_40022000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pwm_40022000_REG_NUM 1
#define DT_N_S_soc_S_pwm_40022000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_40022000_REG_IDX_0_VAL_ADDRESS 1073881088 /* 0x40022000 */
#define DT_N_S_soc_S_pwm_40022000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_pwm_40022000_RANGES_NUM 0
#define DT_N_S_soc_S_pwm_40022000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pwm_40022000_IRQ_NUM 1
#define DT_N_S_soc_S_pwm_40022000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_40022000_IRQ_IDX_0_VAL_irq 34
#define DT_N_S_soc_S_pwm_40022000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_pwm_40022000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_40022000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_pwm_40022000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_pwm_40022000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_pwm_40022000_IRQ_LEVEL 1
#define DT_N_S_soc_S_pwm_40022000_COMPAT_MATCHES_nordic_nrf_pwm 1
#define DT_N_S_soc_S_pwm_40022000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_40022000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_pwm_40022000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_40022000_COMPAT_MODEL_IDX_0 "nrf-pwm"
#define DT_N_S_soc_S_pwm_40022000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pwm_40022000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pwm_40022000_P_wakeup_source 0
#define DT_N_S_soc_S_pwm_40022000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_pwm_40022000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_pwm_40022000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_pwm_40022000_P_status "disabled"
#define DT_N_S_soc_S_pwm_40022000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_pwm_40022000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_pwm_40022000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_pwm_40022000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_pwm_40022000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_40022000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_pwm_40022000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_pwm_40022000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_pwm_40022000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_pwm_40022000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pwm_40022000, status, 0)
#define DT_N_S_soc_S_pwm_40022000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pwm_40022000, status, 0)
#define DT_N_S_soc_S_pwm_40022000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pwm_40022000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pwm_40022000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pwm_40022000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pwm_40022000_P_status_LEN 1
#define DT_N_S_soc_S_pwm_40022000_P_status_EXISTS 1
#define DT_N_S_soc_S_pwm_40022000_P_compatible {"nordic,nrf-pwm"}
#define DT_N_S_soc_S_pwm_40022000_P_compatible_IDX_0 "nordic,nrf-pwm"
#define DT_N_S_soc_S_pwm_40022000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pwm
#define DT_N_S_soc_S_pwm_40022000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pwm
#define DT_N_S_soc_S_pwm_40022000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PWM
#define DT_N_S_soc_S_pwm_40022000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_40022000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pwm_40022000, compatible, 0)
#define DT_N_S_soc_S_pwm_40022000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pwm_40022000, compatible, 0)
#define DT_N_S_soc_S_pwm_40022000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pwm_40022000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pwm_40022000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pwm_40022000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pwm_40022000_P_compatible_LEN 1
#define DT_N_S_soc_S_pwm_40022000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_pwm_40022000_P_reg {1073881088 /* 0x40022000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_pwm_40022000_P_reg_IDX_0 1073881088
#define DT_N_S_soc_S_pwm_40022000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_40022000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_pwm_40022000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pwm_40022000_P_reg_EXISTS 1
#define DT_N_S_soc_S_pwm_40022000_P_interrupts {34 /* 0x22 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_pwm_40022000_P_interrupts_IDX_0 34
#define DT_N_S_soc_S_pwm_40022000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_40022000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_pwm_40022000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pwm_40022000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_pwm_40022000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_pwm_40022000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_pwm_40022000_P_center_aligned 0
#define DT_N_S_soc_S_pwm_40022000_P_center_aligned_EXISTS 1

/*
 * Devicetree node: /soc/pwm@4002d000
 *
 * Node identifier: DT_N_S_soc_S_pwm_4002d000
 *
 * Binding (compatible = nordic,nrf-pwm):
 *   $ZEPHYR_BASE/dts/bindings/pwm/nordic,nrf-pwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pwm_4002d000_PATH "/soc/pwm@4002d000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pwm_4002d000_FULL_NAME "pwm@4002d000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_pwm_4002d000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pwm_4002d000_CHILD_IDX 50

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pwm_4002d000_CHILD_NUM 0
#define DT_N_S_soc_S_pwm_4002d000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pwm_4002d000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pwm_4002d000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pwm_4002d000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pwm_4002d000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pwm_4002d000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pwm_4002d000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pwm_4002d000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pwm_4002d000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pwm_4002d000_ORD 96
#define DT_N_S_soc_S_pwm_4002d000_ORD_STR_SORTABLE 00096

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pwm_4002d000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pwm_4002d000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pwm_4002d000_EXISTS 1
#define DT_N_INST_3_nordic_nrf_pwm DT_N_S_soc_S_pwm_4002d000
#define DT_N_NODELABEL_pwm3        DT_N_S_soc_S_pwm_4002d000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pwm_4002d000_REG_NUM 1
#define DT_N_S_soc_S_pwm_4002d000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_4002d000_REG_IDX_0_VAL_ADDRESS 1073926144 /* 0x4002d000 */
#define DT_N_S_soc_S_pwm_4002d000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_pwm_4002d000_RANGES_NUM 0
#define DT_N_S_soc_S_pwm_4002d000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pwm_4002d000_IRQ_NUM 1
#define DT_N_S_soc_S_pwm_4002d000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_4002d000_IRQ_IDX_0_VAL_irq 45
#define DT_N_S_soc_S_pwm_4002d000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_pwm_4002d000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_4002d000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_pwm_4002d000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_pwm_4002d000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_pwm_4002d000_IRQ_LEVEL 1
#define DT_N_S_soc_S_pwm_4002d000_COMPAT_MATCHES_nordic_nrf_pwm 1
#define DT_N_S_soc_S_pwm_4002d000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_4002d000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_pwm_4002d000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_4002d000_COMPAT_MODEL_IDX_0 "nrf-pwm"
#define DT_N_S_soc_S_pwm_4002d000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pwm_4002d000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pwm_4002d000_P_wakeup_source 0
#define DT_N_S_soc_S_pwm_4002d000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_pwm_4002d000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_pwm_4002d000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_pwm_4002d000_P_status "disabled"
#define DT_N_S_soc_S_pwm_4002d000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_pwm_4002d000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_pwm_4002d000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_pwm_4002d000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_pwm_4002d000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_4002d000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_pwm_4002d000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_pwm_4002d000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_pwm_4002d000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_pwm_4002d000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pwm_4002d000, status, 0)
#define DT_N_S_soc_S_pwm_4002d000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pwm_4002d000, status, 0)
#define DT_N_S_soc_S_pwm_4002d000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pwm_4002d000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pwm_4002d000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pwm_4002d000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pwm_4002d000_P_status_LEN 1
#define DT_N_S_soc_S_pwm_4002d000_P_status_EXISTS 1
#define DT_N_S_soc_S_pwm_4002d000_P_compatible {"nordic,nrf-pwm"}
#define DT_N_S_soc_S_pwm_4002d000_P_compatible_IDX_0 "nordic,nrf-pwm"
#define DT_N_S_soc_S_pwm_4002d000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-pwm
#define DT_N_S_soc_S_pwm_4002d000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_pwm
#define DT_N_S_soc_S_pwm_4002d000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_PWM
#define DT_N_S_soc_S_pwm_4002d000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_4002d000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pwm_4002d000, compatible, 0)
#define DT_N_S_soc_S_pwm_4002d000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pwm_4002d000, compatible, 0)
#define DT_N_S_soc_S_pwm_4002d000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pwm_4002d000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pwm_4002d000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pwm_4002d000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pwm_4002d000_P_compatible_LEN 1
#define DT_N_S_soc_S_pwm_4002d000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_pwm_4002d000_P_reg {1073926144 /* 0x4002d000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_pwm_4002d000_P_reg_IDX_0 1073926144
#define DT_N_S_soc_S_pwm_4002d000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_4002d000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_pwm_4002d000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pwm_4002d000_P_reg_EXISTS 1
#define DT_N_S_soc_S_pwm_4002d000_P_interrupts {45 /* 0x2d */, 1 /* 0x1 */}
#define DT_N_S_soc_S_pwm_4002d000_P_interrupts_IDX_0 45
#define DT_N_S_soc_S_pwm_4002d000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pwm_4002d000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_pwm_4002d000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pwm_4002d000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_pwm_4002d000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_pwm_4002d000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_pwm_4002d000_P_center_aligned 0
#define DT_N_S_soc_S_pwm_4002d000_P_center_aligned_EXISTS 1

/*
 * Devicetree node: /soc/qdec@40012000
 *
 * Node identifier: DT_N_S_soc_S_qdec_40012000
 *
 * Binding (compatible = nordic,nrf-qdec):
 *   $ZEPHYR_BASE/dts/bindings/sensor/nordic,nrf-qdec.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_qdec_40012000_PATH "/soc/qdec@40012000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_qdec_40012000_FULL_NAME "qdec@40012000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_qdec_40012000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_qdec_40012000_CHILD_IDX 26

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_qdec_40012000_CHILD_NUM 0
#define DT_N_S_soc_S_qdec_40012000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_qdec_40012000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_qdec_40012000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_qdec_40012000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_qdec_40012000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_qdec_40012000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_qdec_40012000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_qdec_40012000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_qdec_40012000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_qdec_40012000_ORD 97
#define DT_N_S_soc_S_qdec_40012000_ORD_STR_SORTABLE 00097

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_qdec_40012000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_qdec_40012000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_qdec_40012000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_qdec DT_N_S_soc_S_qdec_40012000
#define DT_N_NODELABEL_qdec         DT_N_S_soc_S_qdec_40012000
#define DT_N_NODELABEL_qdec0        DT_N_S_soc_S_qdec_40012000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_qdec_40012000_REG_NUM 1
#define DT_N_S_soc_S_qdec_40012000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qdec_40012000_REG_IDX_0_VAL_ADDRESS 1073815552 /* 0x40012000 */
#define DT_N_S_soc_S_qdec_40012000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_qdec_40012000_RANGES_NUM 0
#define DT_N_S_soc_S_qdec_40012000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_qdec_40012000_IRQ_NUM 1
#define DT_N_S_soc_S_qdec_40012000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qdec_40012000_IRQ_IDX_0_VAL_irq 18
#define DT_N_S_soc_S_qdec_40012000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_qdec_40012000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qdec_40012000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_qdec_40012000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_qdec_40012000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_qdec_40012000_IRQ_LEVEL 1
#define DT_N_S_soc_S_qdec_40012000_COMPAT_MATCHES_nordic_nrf_qdec 1
#define DT_N_S_soc_S_qdec_40012000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qdec_40012000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_qdec_40012000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qdec_40012000_COMPAT_MODEL_IDX_0 "nrf-qdec"
#define DT_N_S_soc_S_qdec_40012000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_qdec_40012000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_qdec_40012000_P_wakeup_source 0
#define DT_N_S_soc_S_qdec_40012000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_qdec_40012000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_qdec_40012000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_qdec_40012000_P_status "disabled"
#define DT_N_S_soc_S_qdec_40012000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_qdec_40012000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_qdec_40012000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_qdec_40012000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_qdec_40012000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qdec_40012000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_qdec_40012000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_qdec_40012000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_qdec_40012000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_qdec_40012000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_qdec_40012000, status, 0)
#define DT_N_S_soc_S_qdec_40012000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_qdec_40012000, status, 0)
#define DT_N_S_soc_S_qdec_40012000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_qdec_40012000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_qdec_40012000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_qdec_40012000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_qdec_40012000_P_status_LEN 1
#define DT_N_S_soc_S_qdec_40012000_P_status_EXISTS 1
#define DT_N_S_soc_S_qdec_40012000_P_compatible {"nordic,nrf-qdec"}
#define DT_N_S_soc_S_qdec_40012000_P_compatible_IDX_0 "nordic,nrf-qdec"
#define DT_N_S_soc_S_qdec_40012000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-qdec
#define DT_N_S_soc_S_qdec_40012000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_qdec
#define DT_N_S_soc_S_qdec_40012000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_QDEC
#define DT_N_S_soc_S_qdec_40012000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qdec_40012000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_qdec_40012000, compatible, 0)
#define DT_N_S_soc_S_qdec_40012000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_qdec_40012000, compatible, 0)
#define DT_N_S_soc_S_qdec_40012000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_qdec_40012000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_qdec_40012000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_qdec_40012000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_qdec_40012000_P_compatible_LEN 1
#define DT_N_S_soc_S_qdec_40012000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_qdec_40012000_P_reg {1073815552 /* 0x40012000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_qdec_40012000_P_reg_IDX_0 1073815552
#define DT_N_S_soc_S_qdec_40012000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qdec_40012000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_qdec_40012000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_qdec_40012000_P_reg_EXISTS 1
#define DT_N_S_soc_S_qdec_40012000_P_interrupts {18 /* 0x12 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_qdec_40012000_P_interrupts_IDX_0 18
#define DT_N_S_soc_S_qdec_40012000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qdec_40012000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_qdec_40012000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_qdec_40012000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_qdec_40012000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_qdec_40012000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/random@4000d000
 *
 * Node identifier: DT_N_S_soc_S_random_4000d000
 *
 * Binding (compatible = nordic,nrf-rng):
 *   $ZEPHYR_BASE/dts/bindings/rng/nordic,nrf-rng.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_random_4000d000_PATH "/soc/random@4000d000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_random_4000d000_FULL_NAME "random@4000d000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_random_4000d000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_random_4000d000_CHILD_IDX 21

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_random_4000d000_CHILD_NUM 0
#define DT_N_S_soc_S_random_4000d000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_random_4000d000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_random_4000d000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_random_4000d000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_random_4000d000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_random_4000d000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_random_4000d000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_random_4000d000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_random_4000d000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_random_4000d000_ORD 98
#define DT_N_S_soc_S_random_4000d000_ORD_STR_SORTABLE 00098

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_random_4000d000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_random_4000d000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_random_4000d000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_rng DT_N_S_soc_S_random_4000d000
#define DT_N_NODELABEL_rng         DT_N_S_soc_S_random_4000d000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_random_4000d000_REG_NUM 1
#define DT_N_S_soc_S_random_4000d000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_random_4000d000_REG_IDX_0_VAL_ADDRESS 1073795072 /* 0x4000d000 */
#define DT_N_S_soc_S_random_4000d000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_random_4000d000_RANGES_NUM 0
#define DT_N_S_soc_S_random_4000d000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_random_4000d000_IRQ_NUM 1
#define DT_N_S_soc_S_random_4000d000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_random_4000d000_IRQ_IDX_0_VAL_irq 13
#define DT_N_S_soc_S_random_4000d000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_random_4000d000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_random_4000d000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_random_4000d000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_random_4000d000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_random_4000d000_IRQ_LEVEL 1
#define DT_N_S_soc_S_random_4000d000_COMPAT_MATCHES_nordic_nrf_rng 1
#define DT_N_S_soc_S_random_4000d000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_random_4000d000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_random_4000d000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_random_4000d000_COMPAT_MODEL_IDX_0 "nrf-rng"
#define DT_N_S_soc_S_random_4000d000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_random_4000d000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_random_4000d000_P_wakeup_source 0
#define DT_N_S_soc_S_random_4000d000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_random_4000d000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_random_4000d000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_random_4000d000_P_status "okay"
#define DT_N_S_soc_S_random_4000d000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_random_4000d000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_random_4000d000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_random_4000d000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_random_4000d000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_random_4000d000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_random_4000d000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_random_4000d000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_random_4000d000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_random_4000d000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_random_4000d000, status, 0)
#define DT_N_S_soc_S_random_4000d000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_random_4000d000, status, 0)
#define DT_N_S_soc_S_random_4000d000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_random_4000d000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_random_4000d000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_random_4000d000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_random_4000d000_P_status_LEN 1
#define DT_N_S_soc_S_random_4000d000_P_status_EXISTS 1
#define DT_N_S_soc_S_random_4000d000_P_compatible {"nordic,nrf-rng"}
#define DT_N_S_soc_S_random_4000d000_P_compatible_IDX_0 "nordic,nrf-rng"
#define DT_N_S_soc_S_random_4000d000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-rng
#define DT_N_S_soc_S_random_4000d000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_rng
#define DT_N_S_soc_S_random_4000d000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_RNG
#define DT_N_S_soc_S_random_4000d000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_random_4000d000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_random_4000d000, compatible, 0)
#define DT_N_S_soc_S_random_4000d000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_random_4000d000, compatible, 0)
#define DT_N_S_soc_S_random_4000d000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_random_4000d000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_random_4000d000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_random_4000d000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_random_4000d000_P_compatible_LEN 1
#define DT_N_S_soc_S_random_4000d000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_random_4000d000_P_reg {1073795072 /* 0x4000d000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_random_4000d000_P_reg_IDX_0 1073795072
#define DT_N_S_soc_S_random_4000d000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_random_4000d000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_random_4000d000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_random_4000d000_P_reg_EXISTS 1
#define DT_N_S_soc_S_random_4000d000_P_interrupts {13 /* 0xd */, 1 /* 0x1 */}
#define DT_N_S_soc_S_random_4000d000_P_interrupts_IDX_0 13
#define DT_N_S_soc_S_random_4000d000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_random_4000d000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_random_4000d000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_random_4000d000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_random_4000d000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_random_4000d000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/rtc@4000b000
 *
 * Node identifier: DT_N_S_soc_S_rtc_4000b000
 *
 * Binding (compatible = nordic,nrf-rtc):
 *   $ZEPHYR_BASE/dts/bindings/rtc/nordic,nrf-rtc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_rtc_4000b000_PATH "/soc/rtc@4000b000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_rtc_4000b000_FULL_NAME "rtc@4000b000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_rtc_4000b000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_rtc_4000b000_CHILD_IDX 19

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_rtc_4000b000_CHILD_NUM 0
#define DT_N_S_soc_S_rtc_4000b000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_rtc_4000b000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_rtc_4000b000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_rtc_4000b000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_rtc_4000b000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_rtc_4000b000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_rtc_4000b000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_rtc_4000b000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_rtc_4000b000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_rtc_4000b000_ORD 99
#define DT_N_S_soc_S_rtc_4000b000_ORD_STR_SORTABLE 00099

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_rtc_4000b000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_rtc_4000b000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_rtc_4000b000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_rtc DT_N_S_soc_S_rtc_4000b000
#define DT_N_NODELABEL_rtc0        DT_N_S_soc_S_rtc_4000b000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_rtc_4000b000_REG_NUM 1
#define DT_N_S_soc_S_rtc_4000b000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_4000b000_REG_IDX_0_VAL_ADDRESS 1073786880 /* 0x4000b000 */
#define DT_N_S_soc_S_rtc_4000b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_rtc_4000b000_RANGES_NUM 0
#define DT_N_S_soc_S_rtc_4000b000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_rtc_4000b000_IRQ_NUM 1
#define DT_N_S_soc_S_rtc_4000b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_4000b000_IRQ_IDX_0_VAL_irq 11
#define DT_N_S_soc_S_rtc_4000b000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_rtc_4000b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_4000b000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_rtc_4000b000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_rtc_4000b000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_rtc_4000b000_IRQ_LEVEL 1
#define DT_N_S_soc_S_rtc_4000b000_COMPAT_MATCHES_nordic_nrf_rtc 1
#define DT_N_S_soc_S_rtc_4000b000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_4000b000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_rtc_4000b000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_4000b000_COMPAT_MODEL_IDX_0 "nrf-rtc"
#define DT_N_S_soc_S_rtc_4000b000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_rtc_4000b000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_rtc_4000b000_P_wakeup_source 0
#define DT_N_S_soc_S_rtc_4000b000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_rtc_4000b000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_rtc_4000b000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_rtc_4000b000_P_status "disabled"
#define DT_N_S_soc_S_rtc_4000b000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_rtc_4000b000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_rtc_4000b000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_rtc_4000b000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_rtc_4000b000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_4000b000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_rtc_4000b000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_rtc_4000b000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_rtc_4000b000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_rtc_4000b000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rtc_4000b000, status, 0)
#define DT_N_S_soc_S_rtc_4000b000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rtc_4000b000, status, 0)
#define DT_N_S_soc_S_rtc_4000b000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rtc_4000b000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_4000b000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rtc_4000b000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_4000b000_P_status_LEN 1
#define DT_N_S_soc_S_rtc_4000b000_P_status_EXISTS 1
#define DT_N_S_soc_S_rtc_4000b000_P_compatible {"nordic,nrf-rtc"}
#define DT_N_S_soc_S_rtc_4000b000_P_compatible_IDX_0 "nordic,nrf-rtc"
#define DT_N_S_soc_S_rtc_4000b000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-rtc
#define DT_N_S_soc_S_rtc_4000b000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_rtc
#define DT_N_S_soc_S_rtc_4000b000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_RTC
#define DT_N_S_soc_S_rtc_4000b000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_4000b000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rtc_4000b000, compatible, 0)
#define DT_N_S_soc_S_rtc_4000b000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rtc_4000b000, compatible, 0)
#define DT_N_S_soc_S_rtc_4000b000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rtc_4000b000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_4000b000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rtc_4000b000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_4000b000_P_compatible_LEN 1
#define DT_N_S_soc_S_rtc_4000b000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_rtc_4000b000_P_reg {1073786880 /* 0x4000b000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_rtc_4000b000_P_reg_IDX_0 1073786880
#define DT_N_S_soc_S_rtc_4000b000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_4000b000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_rtc_4000b000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_rtc_4000b000_P_reg_EXISTS 1
#define DT_N_S_soc_S_rtc_4000b000_P_interrupts {11 /* 0xb */, 1 /* 0x1 */}
#define DT_N_S_soc_S_rtc_4000b000_P_interrupts_IDX_0 11
#define DT_N_S_soc_S_rtc_4000b000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_4000b000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_rtc_4000b000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_rtc_4000b000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_rtc_4000b000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_rtc_4000b000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_rtc_4000b000_P_clock_frequency 32768
#define DT_N_S_soc_S_rtc_4000b000_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_rtc_4000b000_P_prescaler 1
#define DT_N_S_soc_S_rtc_4000b000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_rtc_4000b000_P_cc_num 3
#define DT_N_S_soc_S_rtc_4000b000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_rtc_4000b000_P_ppi_wrap 0
#define DT_N_S_soc_S_rtc_4000b000_P_ppi_wrap_EXISTS 1
#define DT_N_S_soc_S_rtc_4000b000_P_fixed_top 0
#define DT_N_S_soc_S_rtc_4000b000_P_fixed_top_EXISTS 1
#define DT_N_S_soc_S_rtc_4000b000_P_zli 0
#define DT_N_S_soc_S_rtc_4000b000_P_zli_EXISTS 1

/*
 * Devicetree node: /soc/rtc@40011000
 *
 * Node identifier: DT_N_S_soc_S_rtc_40011000
 *
 * Binding (compatible = nordic,nrf-rtc):
 *   $ZEPHYR_BASE/dts/bindings/rtc/nordic,nrf-rtc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_rtc_40011000_PATH "/soc/rtc@40011000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_rtc_40011000_FULL_NAME "rtc@40011000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_rtc_40011000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_rtc_40011000_CHILD_IDX 25

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_rtc_40011000_CHILD_NUM 0
#define DT_N_S_soc_S_rtc_40011000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_rtc_40011000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_rtc_40011000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_rtc_40011000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_rtc_40011000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_rtc_40011000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_rtc_40011000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_rtc_40011000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_rtc_40011000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_rtc_40011000_ORD 100
#define DT_N_S_soc_S_rtc_40011000_ORD_STR_SORTABLE 00100

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_rtc_40011000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_rtc_40011000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_rtc_40011000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_rtc DT_N_S_soc_S_rtc_40011000
#define DT_N_NODELABEL_rtc1        DT_N_S_soc_S_rtc_40011000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_rtc_40011000_REG_NUM 1
#define DT_N_S_soc_S_rtc_40011000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40011000_REG_IDX_0_VAL_ADDRESS 1073811456 /* 0x40011000 */
#define DT_N_S_soc_S_rtc_40011000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_rtc_40011000_RANGES_NUM 0
#define DT_N_S_soc_S_rtc_40011000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_rtc_40011000_IRQ_NUM 1
#define DT_N_S_soc_S_rtc_40011000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40011000_IRQ_IDX_0_VAL_irq 17
#define DT_N_S_soc_S_rtc_40011000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_rtc_40011000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40011000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_rtc_40011000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_rtc_40011000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_rtc_40011000_IRQ_LEVEL 1
#define DT_N_S_soc_S_rtc_40011000_COMPAT_MATCHES_nordic_nrf_rtc 1
#define DT_N_S_soc_S_rtc_40011000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40011000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_rtc_40011000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40011000_COMPAT_MODEL_IDX_0 "nrf-rtc"
#define DT_N_S_soc_S_rtc_40011000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_rtc_40011000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_rtc_40011000_P_wakeup_source 0
#define DT_N_S_soc_S_rtc_40011000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_rtc_40011000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_rtc_40011000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_rtc_40011000_P_status "disabled"
#define DT_N_S_soc_S_rtc_40011000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_rtc_40011000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_rtc_40011000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_rtc_40011000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_rtc_40011000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40011000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_rtc_40011000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_rtc_40011000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_rtc_40011000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_rtc_40011000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rtc_40011000, status, 0)
#define DT_N_S_soc_S_rtc_40011000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rtc_40011000, status, 0)
#define DT_N_S_soc_S_rtc_40011000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rtc_40011000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40011000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rtc_40011000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40011000_P_status_LEN 1
#define DT_N_S_soc_S_rtc_40011000_P_status_EXISTS 1
#define DT_N_S_soc_S_rtc_40011000_P_compatible {"nordic,nrf-rtc"}
#define DT_N_S_soc_S_rtc_40011000_P_compatible_IDX_0 "nordic,nrf-rtc"
#define DT_N_S_soc_S_rtc_40011000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-rtc
#define DT_N_S_soc_S_rtc_40011000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_rtc
#define DT_N_S_soc_S_rtc_40011000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_RTC
#define DT_N_S_soc_S_rtc_40011000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40011000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rtc_40011000, compatible, 0)
#define DT_N_S_soc_S_rtc_40011000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rtc_40011000, compatible, 0)
#define DT_N_S_soc_S_rtc_40011000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rtc_40011000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40011000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rtc_40011000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40011000_P_compatible_LEN 1
#define DT_N_S_soc_S_rtc_40011000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_rtc_40011000_P_reg {1073811456 /* 0x40011000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_rtc_40011000_P_reg_IDX_0 1073811456
#define DT_N_S_soc_S_rtc_40011000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40011000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_rtc_40011000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_rtc_40011000_P_reg_EXISTS 1
#define DT_N_S_soc_S_rtc_40011000_P_interrupts {17 /* 0x11 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_rtc_40011000_P_interrupts_IDX_0 17
#define DT_N_S_soc_S_rtc_40011000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40011000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_rtc_40011000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_rtc_40011000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_rtc_40011000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_rtc_40011000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_rtc_40011000_P_clock_frequency 32768
#define DT_N_S_soc_S_rtc_40011000_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_rtc_40011000_P_prescaler 1
#define DT_N_S_soc_S_rtc_40011000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_rtc_40011000_P_cc_num 4
#define DT_N_S_soc_S_rtc_40011000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_rtc_40011000_P_ppi_wrap 0
#define DT_N_S_soc_S_rtc_40011000_P_ppi_wrap_EXISTS 1
#define DT_N_S_soc_S_rtc_40011000_P_fixed_top 0
#define DT_N_S_soc_S_rtc_40011000_P_fixed_top_EXISTS 1
#define DT_N_S_soc_S_rtc_40011000_P_zli 0
#define DT_N_S_soc_S_rtc_40011000_P_zli_EXISTS 1

/*
 * Devicetree node: /soc/rtc@40024000
 *
 * Node identifier: DT_N_S_soc_S_rtc_40024000
 *
 * Binding (compatible = nordic,nrf-rtc):
 *   $ZEPHYR_BASE/dts/bindings/rtc/nordic,nrf-rtc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_rtc_40024000_PATH "/soc/rtc@40024000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_rtc_40024000_FULL_NAME "rtc@40024000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_rtc_40024000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_rtc_40024000_CHILD_IDX 45

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_rtc_40024000_CHILD_NUM 0
#define DT_N_S_soc_S_rtc_40024000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_rtc_40024000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_rtc_40024000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_rtc_40024000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_rtc_40024000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_rtc_40024000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_rtc_40024000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_rtc_40024000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_rtc_40024000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_rtc_40024000_ORD 101
#define DT_N_S_soc_S_rtc_40024000_ORD_STR_SORTABLE 00101

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_rtc_40024000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_rtc_40024000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_rtc_40024000_EXISTS 1
#define DT_N_INST_2_nordic_nrf_rtc DT_N_S_soc_S_rtc_40024000
#define DT_N_NODELABEL_rtc2        DT_N_S_soc_S_rtc_40024000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_rtc_40024000_REG_NUM 1
#define DT_N_S_soc_S_rtc_40024000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40024000_REG_IDX_0_VAL_ADDRESS 1073889280 /* 0x40024000 */
#define DT_N_S_soc_S_rtc_40024000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_rtc_40024000_RANGES_NUM 0
#define DT_N_S_soc_S_rtc_40024000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_rtc_40024000_IRQ_NUM 1
#define DT_N_S_soc_S_rtc_40024000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40024000_IRQ_IDX_0_VAL_irq 36
#define DT_N_S_soc_S_rtc_40024000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_rtc_40024000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40024000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_rtc_40024000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_rtc_40024000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_rtc_40024000_IRQ_LEVEL 1
#define DT_N_S_soc_S_rtc_40024000_COMPAT_MATCHES_nordic_nrf_rtc 1
#define DT_N_S_soc_S_rtc_40024000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40024000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_rtc_40024000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40024000_COMPAT_MODEL_IDX_0 "nrf-rtc"
#define DT_N_S_soc_S_rtc_40024000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_rtc_40024000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_rtc_40024000_P_wakeup_source 0
#define DT_N_S_soc_S_rtc_40024000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_rtc_40024000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_rtc_40024000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_rtc_40024000_P_status "disabled"
#define DT_N_S_soc_S_rtc_40024000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_rtc_40024000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_rtc_40024000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_rtc_40024000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_rtc_40024000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40024000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_rtc_40024000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_rtc_40024000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_rtc_40024000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_rtc_40024000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rtc_40024000, status, 0)
#define DT_N_S_soc_S_rtc_40024000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rtc_40024000, status, 0)
#define DT_N_S_soc_S_rtc_40024000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rtc_40024000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40024000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rtc_40024000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40024000_P_status_LEN 1
#define DT_N_S_soc_S_rtc_40024000_P_status_EXISTS 1
#define DT_N_S_soc_S_rtc_40024000_P_compatible {"nordic,nrf-rtc"}
#define DT_N_S_soc_S_rtc_40024000_P_compatible_IDX_0 "nordic,nrf-rtc"
#define DT_N_S_soc_S_rtc_40024000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-rtc
#define DT_N_S_soc_S_rtc_40024000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_rtc
#define DT_N_S_soc_S_rtc_40024000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_RTC
#define DT_N_S_soc_S_rtc_40024000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40024000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rtc_40024000, compatible, 0)
#define DT_N_S_soc_S_rtc_40024000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rtc_40024000, compatible, 0)
#define DT_N_S_soc_S_rtc_40024000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rtc_40024000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40024000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rtc_40024000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_40024000_P_compatible_LEN 1
#define DT_N_S_soc_S_rtc_40024000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_rtc_40024000_P_reg {1073889280 /* 0x40024000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_rtc_40024000_P_reg_IDX_0 1073889280
#define DT_N_S_soc_S_rtc_40024000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40024000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_rtc_40024000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_rtc_40024000_P_reg_EXISTS 1
#define DT_N_S_soc_S_rtc_40024000_P_interrupts {36 /* 0x24 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_rtc_40024000_P_interrupts_IDX_0 36
#define DT_N_S_soc_S_rtc_40024000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_40024000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_rtc_40024000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_rtc_40024000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_rtc_40024000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_rtc_40024000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_rtc_40024000_P_clock_frequency 32768
#define DT_N_S_soc_S_rtc_40024000_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_rtc_40024000_P_prescaler 1
#define DT_N_S_soc_S_rtc_40024000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_rtc_40024000_P_cc_num 4
#define DT_N_S_soc_S_rtc_40024000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_rtc_40024000_P_ppi_wrap 0
#define DT_N_S_soc_S_rtc_40024000_P_ppi_wrap_EXISTS 1
#define DT_N_S_soc_S_rtc_40024000_P_fixed_top 0
#define DT_N_S_soc_S_rtc_40024000_P_fixed_top_EXISTS 1
#define DT_N_S_soc_S_rtc_40024000_P_zli 0
#define DT_N_S_soc_S_rtc_40024000_P_zli_EXISTS 1

/*
 * Devicetree node: /soc/spi@40003000
 *
 * Node identifier: DT_N_S_soc_S_spi_40003000
 *
 * Binding (compatible = nordic,nrf-spi):
 *   $ZEPHYR_BASE/dts/bindings/spi/nordic,nrf-spi.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_spi_40003000_PATH "/soc/spi@40003000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_spi_40003000_FULL_NAME "spi@40003000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_spi_40003000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_spi_40003000_CHILD_IDX 10

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_spi_40003000_CHILD_NUM 0
#define DT_N_S_soc_S_spi_40003000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_spi_40003000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_spi_40003000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_spi_40003000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_spi_40003000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_spi_40003000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_spi_40003000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_spi_40003000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_spi_40003000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_spi_40003000_ORD 102
#define DT_N_S_soc_S_spi_40003000_ORD_STR_SORTABLE 00102

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_spi_40003000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */ \
	43, /* /pin-controller/spi0_default */ \
	45, /* /pin-controller/spi0_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_spi_40003000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_spi_40003000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_spi DT_N_S_soc_S_spi_40003000
#define DT_N_NODELABEL_spi0        DT_N_S_soc_S_spi_40003000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_spi_40003000_REG_NUM 1
#define DT_N_S_soc_S_spi_40003000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_REG_IDX_0_VAL_ADDRESS 1073754112 /* 0x40003000 */
#define DT_N_S_soc_S_spi_40003000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_spi_40003000_RANGES_NUM 0
#define DT_N_S_soc_S_spi_40003000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_spi_40003000_IRQ_NUM 1
#define DT_N_S_soc_S_spi_40003000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_IRQ_IDX_0_VAL_irq 3
#define DT_N_S_soc_S_spi_40003000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_spi_40003000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_spi_40003000_IRQ_LEVEL 1
#define DT_N_S_soc_S_spi_40003000_COMPAT_MATCHES_nordic_nrf_spi 1
#define DT_N_S_soc_S_spi_40003000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_spi_40003000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_COMPAT_MODEL_IDX_0 "nrf-spi"
#define DT_N_S_soc_S_spi_40003000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_spi_40003000_PINCTRL_NUM 2
#define DT_N_S_soc_S_spi_40003000_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_spi_40003000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_spi_40003000_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_spi_40003000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_spi0_default
#define DT_N_S_soc_S_spi_40003000_PINCTRL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_PINCTRL_IDX_1_TOKEN sleep
#define DT_N_S_soc_S_spi_40003000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP
#define DT_N_S_soc_S_spi_40003000_PINCTRL_NAME_sleep_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_PINCTRL_NAME_sleep_IDX 1
#define DT_N_S_soc_S_spi_40003000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_spi0_sleep

/* Generic property macros: */
#define DT_N_S_soc_S_spi_40003000_P_wakeup_source 0
#define DT_N_S_soc_S_spi_40003000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_spi_40003000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_P_status "disabled"
#define DT_N_S_soc_S_spi_40003000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_spi_40003000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_spi_40003000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_spi_40003000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_spi_40003000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_spi_40003000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_spi_40003000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_spi_40003000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40003000, status, 0)
#define DT_N_S_soc_S_spi_40003000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003000, status, 0)
#define DT_N_S_soc_S_spi_40003000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40003000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40003000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003000_P_status_LEN 1
#define DT_N_S_soc_S_spi_40003000_P_status_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_P_compatible {"nordic,nrf-spi"}
#define DT_N_S_soc_S_spi_40003000_P_compatible_IDX_0 "nordic,nrf-spi"
#define DT_N_S_soc_S_spi_40003000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-spi
#define DT_N_S_soc_S_spi_40003000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spi
#define DT_N_S_soc_S_spi_40003000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPI
#define DT_N_S_soc_S_spi_40003000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40003000, compatible, 0)
#define DT_N_S_soc_S_spi_40003000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003000, compatible, 0)
#define DT_N_S_soc_S_spi_40003000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40003000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40003000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003000_P_compatible_LEN 1
#define DT_N_S_soc_S_spi_40003000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_P_reg {1073754112 /* 0x40003000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_spi_40003000_P_reg_IDX_0 1073754112
#define DT_N_S_soc_S_spi_40003000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_spi_40003000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_P_reg_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_P_interrupts {3 /* 0x3 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_spi_40003000_P_interrupts_IDX_0 3
#define DT_N_S_soc_S_spi_40003000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_spi_40003000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_spi_40003000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_spi0_default
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_spi0_default
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40003000, pinctrl_0, 0)
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003000, pinctrl_0, 0)
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40003000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40003000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_0_LEN 1
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_spi0_sleep
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_spi0_sleep
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_1_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40003000, pinctrl_1, 0)
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003000, pinctrl_1, 0)
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40003000, pinctrl_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40003000, pinctrl_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_1_LEN 1
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_1_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_names {"default", "sleep"}
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_names_IDX_1 "sleep"
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40003000, pinctrl_names, 0) \
	fn(DT_N_S_soc_S_spi_40003000, pinctrl_names, 1)
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40003000, pinctrl_names, 1)
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40003000, pinctrl_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_spi_40003000, pinctrl_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40003000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40003000, pinctrl_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_names_LEN 2
#define DT_N_S_soc_S_spi_40003000_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_P_max_frequency 8000000
#define DT_N_S_soc_S_spi_40003000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_P_overrun_character 255
#define DT_N_S_soc_S_spi_40003000_P_overrun_character_EXISTS 1
#define DT_N_S_soc_S_spi_40003000_P_easydma_maxcnt_bits 16
#define DT_N_S_soc_S_spi_40003000_P_easydma_maxcnt_bits_EXISTS 1

/*
 * Devicetree node: /soc/spi@40004000
 *
 * Node identifier: DT_N_S_soc_S_spi_40004000
 *
 * Binding (compatible = nordic,nrf-spi):
 *   $ZEPHYR_BASE/dts/bindings/spi/nordic,nrf-spi.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_spi_40004000_PATH "/soc/spi@40004000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_spi_40004000_FULL_NAME "spi@40004000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_spi_40004000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_spi_40004000_CHILD_IDX 12

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_spi_40004000_CHILD_NUM 0
#define DT_N_S_soc_S_spi_40004000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_spi_40004000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_spi_40004000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_spi_40004000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_spi_40004000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_spi_40004000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_spi_40004000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_spi_40004000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_spi_40004000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_spi_40004000_ORD 103
#define DT_N_S_soc_S_spi_40004000_ORD_STR_SORTABLE 00103

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_spi_40004000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */ \
	47, /* /pin-controller/spi1_default */ \
	49, /* /pin-controller/spi1_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_spi_40004000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_spi_40004000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_spi DT_N_S_soc_S_spi_40004000
#define DT_N_NODELABEL_spi1        DT_N_S_soc_S_spi_40004000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_spi_40004000_REG_NUM 1
#define DT_N_S_soc_S_spi_40004000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_REG_IDX_0_VAL_ADDRESS 1073758208 /* 0x40004000 */
#define DT_N_S_soc_S_spi_40004000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_spi_40004000_RANGES_NUM 0
#define DT_N_S_soc_S_spi_40004000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_spi_40004000_IRQ_NUM 1
#define DT_N_S_soc_S_spi_40004000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_IRQ_IDX_0_VAL_irq 4
#define DT_N_S_soc_S_spi_40004000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_spi_40004000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_spi_40004000_IRQ_LEVEL 1
#define DT_N_S_soc_S_spi_40004000_COMPAT_MATCHES_nordic_nrf_spi 1
#define DT_N_S_soc_S_spi_40004000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_spi_40004000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_COMPAT_MODEL_IDX_0 "nrf-spi"
#define DT_N_S_soc_S_spi_40004000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_spi_40004000_PINCTRL_NUM 2
#define DT_N_S_soc_S_spi_40004000_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_spi_40004000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_spi_40004000_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_spi_40004000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_spi1_default
#define DT_N_S_soc_S_spi_40004000_PINCTRL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_PINCTRL_IDX_1_TOKEN sleep
#define DT_N_S_soc_S_spi_40004000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP
#define DT_N_S_soc_S_spi_40004000_PINCTRL_NAME_sleep_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_PINCTRL_NAME_sleep_IDX 1
#define DT_N_S_soc_S_spi_40004000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_spi1_sleep

/* Generic property macros: */
#define DT_N_S_soc_S_spi_40004000_P_wakeup_source 0
#define DT_N_S_soc_S_spi_40004000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_spi_40004000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_P_status "okay"
#define DT_N_S_soc_S_spi_40004000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_spi_40004000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_spi_40004000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_spi_40004000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_spi_40004000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_spi_40004000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_spi_40004000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_spi_40004000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40004000, status, 0)
#define DT_N_S_soc_S_spi_40004000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40004000, status, 0)
#define DT_N_S_soc_S_spi_40004000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40004000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40004000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40004000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40004000_P_status_LEN 1
#define DT_N_S_soc_S_spi_40004000_P_status_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_P_compatible {"nordic,nrf-spi"}
#define DT_N_S_soc_S_spi_40004000_P_compatible_IDX_0 "nordic,nrf-spi"
#define DT_N_S_soc_S_spi_40004000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-spi
#define DT_N_S_soc_S_spi_40004000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spi
#define DT_N_S_soc_S_spi_40004000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPI
#define DT_N_S_soc_S_spi_40004000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40004000, compatible, 0)
#define DT_N_S_soc_S_spi_40004000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40004000, compatible, 0)
#define DT_N_S_soc_S_spi_40004000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40004000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40004000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40004000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40004000_P_compatible_LEN 1
#define DT_N_S_soc_S_spi_40004000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_P_reg {1073758208 /* 0x40004000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_spi_40004000_P_reg_IDX_0 1073758208
#define DT_N_S_soc_S_spi_40004000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_spi_40004000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_P_reg_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_P_interrupts {4 /* 0x4 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_spi_40004000_P_interrupts_IDX_0 4
#define DT_N_S_soc_S_spi_40004000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_spi_40004000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_spi_40004000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_spi1_default
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_spi1_default
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40004000, pinctrl_0, 0)
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40004000, pinctrl_0, 0)
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40004000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40004000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_0_LEN 1
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_spi1_sleep
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_spi1_sleep
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_1_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40004000, pinctrl_1, 0)
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40004000, pinctrl_1, 0)
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40004000, pinctrl_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40004000, pinctrl_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_1_LEN 1
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_1_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_names {"default", "sleep"}
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_names_IDX_1 "sleep"
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40004000, pinctrl_names, 0) \
	fn(DT_N_S_soc_S_spi_40004000, pinctrl_names, 1)
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40004000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40004000, pinctrl_names, 1)
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40004000, pinctrl_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_spi_40004000, pinctrl_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40004000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40004000, pinctrl_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_names_LEN 2
#define DT_N_S_soc_S_spi_40004000_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_P_max_frequency 8000000
#define DT_N_S_soc_S_spi_40004000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_P_overrun_character 255
#define DT_N_S_soc_S_spi_40004000_P_overrun_character_EXISTS 1
#define DT_N_S_soc_S_spi_40004000_P_easydma_maxcnt_bits 16
#define DT_N_S_soc_S_spi_40004000_P_easydma_maxcnt_bits_EXISTS 1

/*
 * Devicetree node: /soc/spi@40023000
 *
 * Node identifier: DT_N_S_soc_S_spi_40023000
 *
 * Binding (compatible = nordic,nrf-spi):
 *   $ZEPHYR_BASE/dts/bindings/spi/nordic,nrf-spi.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_spi_40023000_PATH "/soc/spi@40023000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_spi_40023000_FULL_NAME "spi@40023000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_spi_40023000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_spi_40023000_CHILD_IDX 44

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_spi_40023000_CHILD_NUM 0
#define DT_N_S_soc_S_spi_40023000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_spi_40023000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_spi_40023000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_spi_40023000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_spi_40023000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_spi_40023000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_spi_40023000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_spi_40023000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_spi_40023000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_spi_40023000_ORD 104
#define DT_N_S_soc_S_spi_40023000_ORD_STR_SORTABLE 00104

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_spi_40023000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */ \
	51, /* /pin-controller/spi2_default */ \
	53, /* /pin-controller/spi2_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_spi_40023000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_spi_40023000_EXISTS 1
#define DT_N_INST_2_nordic_nrf_spi DT_N_S_soc_S_spi_40023000
#define DT_N_NODELABEL_spi2        DT_N_S_soc_S_spi_40023000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_spi_40023000_REG_NUM 1
#define DT_N_S_soc_S_spi_40023000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_REG_IDX_0_VAL_ADDRESS 1073885184 /* 0x40023000 */
#define DT_N_S_soc_S_spi_40023000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_spi_40023000_RANGES_NUM 0
#define DT_N_S_soc_S_spi_40023000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_spi_40023000_IRQ_NUM 1
#define DT_N_S_soc_S_spi_40023000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_IRQ_IDX_0_VAL_irq 35
#define DT_N_S_soc_S_spi_40023000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_spi_40023000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_spi_40023000_IRQ_LEVEL 1
#define DT_N_S_soc_S_spi_40023000_COMPAT_MATCHES_nordic_nrf_spi 1
#define DT_N_S_soc_S_spi_40023000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_spi_40023000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_COMPAT_MODEL_IDX_0 "nrf-spi"
#define DT_N_S_soc_S_spi_40023000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_spi_40023000_PINCTRL_NUM 2
#define DT_N_S_soc_S_spi_40023000_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_spi_40023000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_spi_40023000_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_spi_40023000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_spi2_default
#define DT_N_S_soc_S_spi_40023000_PINCTRL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_PINCTRL_IDX_1_TOKEN sleep
#define DT_N_S_soc_S_spi_40023000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP
#define DT_N_S_soc_S_spi_40023000_PINCTRL_NAME_sleep_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_PINCTRL_NAME_sleep_IDX 1
#define DT_N_S_soc_S_spi_40023000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_spi2_sleep

/* Generic property macros: */
#define DT_N_S_soc_S_spi_40023000_P_wakeup_source 0
#define DT_N_S_soc_S_spi_40023000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_spi_40023000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_P_status "disabled"
#define DT_N_S_soc_S_spi_40023000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_spi_40023000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_spi_40023000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_spi_40023000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_spi_40023000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_spi_40023000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_spi_40023000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_spi_40023000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40023000, status, 0)
#define DT_N_S_soc_S_spi_40023000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40023000, status, 0)
#define DT_N_S_soc_S_spi_40023000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40023000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40023000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40023000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40023000_P_status_LEN 1
#define DT_N_S_soc_S_spi_40023000_P_status_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_P_compatible {"nordic,nrf-spi"}
#define DT_N_S_soc_S_spi_40023000_P_compatible_IDX_0 "nordic,nrf-spi"
#define DT_N_S_soc_S_spi_40023000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-spi
#define DT_N_S_soc_S_spi_40023000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spi
#define DT_N_S_soc_S_spi_40023000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPI
#define DT_N_S_soc_S_spi_40023000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40023000, compatible, 0)
#define DT_N_S_soc_S_spi_40023000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40023000, compatible, 0)
#define DT_N_S_soc_S_spi_40023000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40023000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40023000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40023000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40023000_P_compatible_LEN 1
#define DT_N_S_soc_S_spi_40023000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_P_reg {1073885184 /* 0x40023000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_spi_40023000_P_reg_IDX_0 1073885184
#define DT_N_S_soc_S_spi_40023000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_spi_40023000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_P_reg_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_P_interrupts {35 /* 0x23 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_spi_40023000_P_interrupts_IDX_0 35
#define DT_N_S_soc_S_spi_40023000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_spi_40023000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_spi_40023000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_spi2_default
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_spi2_default
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40023000, pinctrl_0, 0)
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40023000, pinctrl_0, 0)
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40023000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40023000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_0_LEN 1
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_spi2_sleep
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_spi2_sleep
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_1_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40023000, pinctrl_1, 0)
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40023000, pinctrl_1, 0)
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40023000, pinctrl_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40023000, pinctrl_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_1_LEN 1
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_1_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_names {"default", "sleep"}
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_names_IDX_1 "sleep"
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40023000, pinctrl_names, 0) \
	fn(DT_N_S_soc_S_spi_40023000, pinctrl_names, 1)
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40023000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40023000, pinctrl_names, 1)
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40023000, pinctrl_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_spi_40023000, pinctrl_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40023000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_40023000, pinctrl_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_names_LEN 2
#define DT_N_S_soc_S_spi_40023000_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_P_max_frequency 8000000
#define DT_N_S_soc_S_spi_40023000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_P_overrun_character 255
#define DT_N_S_soc_S_spi_40023000_P_overrun_character_EXISTS 1
#define DT_N_S_soc_S_spi_40023000_P_easydma_maxcnt_bits 16
#define DT_N_S_soc_S_spi_40023000_P_easydma_maxcnt_bits_EXISTS 1

/*
 * Devicetree node: /soc/gpio@50000300
 *
 * Node identifier: DT_N_S_soc_S_gpio_50000300
 *
 * Binding (compatible = nordic,nrf-gpio):
 *   $ZEPHYR_BASE/dts/bindings/gpio/nordic,nrf-gpio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_gpio_50000300_PATH "/soc/gpio@50000300"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_gpio_50000300_FULL_NAME "gpio@50000300"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_gpio_50000300_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_gpio_50000300_CHILD_IDX 53

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_gpio_50000300_CHILD_NUM 0
#define DT_N_S_soc_S_gpio_50000300_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_gpio_50000300_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_gpio_50000300_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_gpio_50000300_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_gpio_50000300_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_gpio_50000300_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_gpio_50000300_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_gpio_50000300_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_gpio_50000300_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_gpio_50000300_ORD 105
#define DT_N_S_soc_S_gpio_50000300_ORD_STR_SORTABLE 00105

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_gpio_50000300_REQUIRES_ORDS \
	6, /* /soc */ \
	10, /* /soc/gpiote@40006000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_gpio_50000300_SUPPORTS_ORDS \
	106, /* /soc/spi@4002f000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_gpio_50000300_EXISTS 1
#define DT_N_INST_1_nordic_nrf_gpio DT_N_S_soc_S_gpio_50000300
#define DT_N_NODELABEL_gpio1        DT_N_S_soc_S_gpio_50000300

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_gpio_50000300_REG_NUM 2
#define DT_N_S_soc_S_gpio_50000300_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_REG_IDX_0_VAL_ADDRESS 1342178048 /* 0x50000300 */
#define DT_N_S_soc_S_gpio_50000300_REG_IDX_0_VAL_SIZE 512 /* 0x200 */
#define DT_N_S_soc_S_gpio_50000300_REG_IDX_1_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_REG_IDX_1_VAL_ADDRESS 1342179328 /* 0x50000800 */
#define DT_N_S_soc_S_gpio_50000300_REG_IDX_1_VAL_SIZE 768 /* 0x300 */
#define DT_N_S_soc_S_gpio_50000300_RANGES_NUM 0
#define DT_N_S_soc_S_gpio_50000300_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_gpio_50000300_IRQ_NUM 0
#define DT_N_S_soc_S_gpio_50000300_IRQ_LEVEL 0
#define DT_N_S_soc_S_gpio_50000300_COMPAT_MATCHES_nordic_nrf_gpio 1
#define DT_N_S_soc_S_gpio_50000300_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_gpio_50000300_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_COMPAT_MODEL_IDX_0 "nrf-gpio"
#define DT_N_S_soc_S_gpio_50000300_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_gpio_50000300_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_gpio_50000300_P_gpio_controller 1
#define DT_N_S_soc_S_gpio_50000300_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_ngpios 16
#define DT_N_S_soc_S_gpio_50000300_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names {"", "D0", "D1", "D2", "D3", "D4", "D5", "D6", "D7", "", "D8", "D9", "D10", "D11", "D12", "D13"}
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_0 ""
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_0_STRING_UNQUOTED 
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_0_STRING_TOKEN 
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_0_STRING_UPPER_TOKEN 
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_1 "D0"
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_1_STRING_UNQUOTED D0
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_1_STRING_TOKEN D0
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_1_STRING_UPPER_TOKEN D0
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_2 "D1"
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_2_STRING_UNQUOTED D1
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_2_STRING_TOKEN D1
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_2_STRING_UPPER_TOKEN D1
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_2_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_3 "D2"
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_3_STRING_UNQUOTED D2
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_3_STRING_TOKEN D2
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_3_STRING_UPPER_TOKEN D2
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_3_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_4 "D3"
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_4_STRING_UNQUOTED D3
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_4_STRING_TOKEN D3
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_4_STRING_UPPER_TOKEN D3
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_4_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_5 "D4"
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_5_STRING_UNQUOTED D4
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_5_STRING_TOKEN D4
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_5_STRING_UPPER_TOKEN D4
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_5_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_6 "D5"
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_6_STRING_UNQUOTED D5
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_6_STRING_TOKEN D5
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_6_STRING_UPPER_TOKEN D5
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_6_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_7 "D6"
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_7_STRING_UNQUOTED D6
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_7_STRING_TOKEN D6
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_7_STRING_UPPER_TOKEN D6
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_7_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_8 "D7"
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_8_STRING_UNQUOTED D7
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_8_STRING_TOKEN D7
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_8_STRING_UPPER_TOKEN D7
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_8_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_9 ""
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_9_STRING_UNQUOTED 
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_9_STRING_TOKEN 
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_9_STRING_UPPER_TOKEN 
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_9_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_10 "D8"
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_10_STRING_UNQUOTED D8
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_10_STRING_TOKEN D8
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_10_STRING_UPPER_TOKEN D8
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_10_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_11 "D9"
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_11_STRING_UNQUOTED D9
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_11_STRING_TOKEN D9
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_11_STRING_UPPER_TOKEN D9
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_11_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_12 "D10"
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_12_STRING_UNQUOTED D10
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_12_STRING_TOKEN D10
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_12_STRING_UPPER_TOKEN D10
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_12_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_13 "D11"
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_13_STRING_UNQUOTED D11
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_13_STRING_TOKEN D11
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_13_STRING_UPPER_TOKEN D11
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_13_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_14 "D12"
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_14_STRING_UNQUOTED D12
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_14_STRING_TOKEN D12
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_14_STRING_UPPER_TOKEN D12
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_14_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_15 "D13"
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_15_STRING_UNQUOTED D13
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_15_STRING_TOKEN D13
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_15_STRING_UPPER_TOKEN D13
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_IDX_15_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 0) \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 1) \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 2) \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 3) \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 4) \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 5) \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 6) \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 7) \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 8) \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 9) \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 10) \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 11) \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 12) \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 13) \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 14) \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 15)
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 7) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 8) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 9) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 10) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 11) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 12) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 13) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 14) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 15)
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 7, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 8, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 9, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 10, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 11, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 12, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 13, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 14, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 15, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio_50000300, gpio_line_names, 15, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_LEN 16
#define DT_N_S_soc_S_gpio_50000300_P_gpio_line_names_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_wakeup_source 0
#define DT_N_S_soc_S_gpio_50000300_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_gpio_50000300_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_status "okay"
#define DT_N_S_soc_S_gpio_50000300_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_gpio_50000300_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_gpio_50000300_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_gpio_50000300_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_gpio_50000300_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_gpio_50000300_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_gpio_50000300_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_gpio_50000300_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpio_50000300, status, 0)
#define DT_N_S_soc_S_gpio_50000300_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpio_50000300, status, 0)
#define DT_N_S_soc_S_gpio_50000300_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpio_50000300, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_50000300_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpio_50000300, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_50000300_P_status_LEN 1
#define DT_N_S_soc_S_gpio_50000300_P_status_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_compatible {"nordic,nrf-gpio"}
#define DT_N_S_soc_S_gpio_50000300_P_compatible_IDX_0 "nordic,nrf-gpio"
#define DT_N_S_soc_S_gpio_50000300_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpio
#define DT_N_S_soc_S_gpio_50000300_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpio
#define DT_N_S_soc_S_gpio_50000300_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPIO
#define DT_N_S_soc_S_gpio_50000300_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpio_50000300, compatible, 0)
#define DT_N_S_soc_S_gpio_50000300_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpio_50000300, compatible, 0)
#define DT_N_S_soc_S_gpio_50000300_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpio_50000300, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_50000300_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpio_50000300, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_50000300_P_compatible_LEN 1
#define DT_N_S_soc_S_gpio_50000300_P_compatible_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_reg {1342178048 /* 0x50000300 */, 512 /* 0x200 */, 1342179328 /* 0x50000800 */, 768 /* 0x300 */}
#define DT_N_S_soc_S_gpio_50000300_P_reg_IDX_0 1342178048
#define DT_N_S_soc_S_gpio_50000300_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_reg_IDX_1 512
#define DT_N_S_soc_S_gpio_50000300_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_reg_IDX_2 1342179328
#define DT_N_S_soc_S_gpio_50000300_P_reg_IDX_2_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_reg_IDX_3 768
#define DT_N_S_soc_S_gpio_50000300_P_reg_IDX_3_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_reg_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_gpio_50000300_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_gpiote_instance DT_N_S_soc_S_gpiote_40006000
#define DT_N_S_soc_S_gpio_50000300_P_gpiote_instance_IDX_0 DT_N_S_soc_S_gpiote_40006000
#define DT_N_S_soc_S_gpio_50000300_P_gpiote_instance_IDX_0_PH DT_N_S_soc_S_gpiote_40006000
#define DT_N_S_soc_S_gpio_50000300_P_gpiote_instance_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_gpiote_instance_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpio_50000300, gpiote_instance, 0)
#define DT_N_S_soc_S_gpio_50000300_P_gpiote_instance_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpio_50000300, gpiote_instance, 0)
#define DT_N_S_soc_S_gpio_50000300_P_gpiote_instance_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpio_50000300, gpiote_instance, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_50000300_P_gpiote_instance_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpio_50000300, gpiote_instance, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_50000300_P_gpiote_instance_LEN 1
#define DT_N_S_soc_S_gpio_50000300_P_gpiote_instance_EXISTS 1
#define DT_N_S_soc_S_gpio_50000300_P_port 1
#define DT_N_S_soc_S_gpio_50000300_P_port_EXISTS 1

/*
 * Devicetree node: /soc/spi@4002f000
 *
 * Node identifier: DT_N_S_soc_S_spi_4002f000
 *
 * Binding (compatible = nordic,nrf-spim):
 *   $ZEPHYR_BASE/dts/bindings/spi/nordic,nrf-spim.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_spi_4002f000_PATH "/soc/spi@4002f000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_spi_4002f000_FULL_NAME "spi@4002f000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_spi_4002f000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_spi_4002f000_CHILD_IDX 51

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_spi_4002f000_CHILD_NUM 0
#define DT_N_S_soc_S_spi_4002f000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_spi_4002f000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_spi_4002f000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_spi_4002f000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_spi_4002f000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_spi_4002f000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_spi_4002f000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_spi_4002f000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_spi_4002f000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_spi_4002f000_ORD 106
#define DT_N_S_soc_S_spi_4002f000_ORD_STR_SORTABLE 00106

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_spi_4002f000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */ \
	55, /* /pin-controller/spi3_default */ \
	57, /* /pin-controller/spi3_sleep */ \
	105, /* /soc/gpio@50000300 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_spi_4002f000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_spi_4002f000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_spim DT_N_S_soc_S_spi_4002f000
#define DT_N_NODELABEL_spi3         DT_N_S_soc_S_spi_4002f000
#define DT_N_NODELABEL_arduino_spi  DT_N_S_soc_S_spi_4002f000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_spi_4002f000_REG_NUM 1
#define DT_N_S_soc_S_spi_4002f000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_REG_IDX_0_VAL_ADDRESS 1073934336 /* 0x4002f000 */
#define DT_N_S_soc_S_spi_4002f000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_spi_4002f000_RANGES_NUM 0
#define DT_N_S_soc_S_spi_4002f000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_spi_4002f000_IRQ_NUM 1
#define DT_N_S_soc_S_spi_4002f000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_IRQ_IDX_0_VAL_irq 47
#define DT_N_S_soc_S_spi_4002f000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_spi_4002f000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_spi_4002f000_IRQ_LEVEL 1
#define DT_N_S_soc_S_spi_4002f000_COMPAT_MATCHES_nordic_nrf_spim 1
#define DT_N_S_soc_S_spi_4002f000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_spi_4002f000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_COMPAT_MODEL_IDX_0 "nrf-spim"
#define DT_N_S_soc_S_spi_4002f000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_spi_4002f000_PINCTRL_NUM 2
#define DT_N_S_soc_S_spi_4002f000_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_spi_4002f000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_spi_4002f000_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_spi_4002f000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_spi3_default
#define DT_N_S_soc_S_spi_4002f000_PINCTRL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_PINCTRL_IDX_1_TOKEN sleep
#define DT_N_S_soc_S_spi_4002f000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP
#define DT_N_S_soc_S_spi_4002f000_PINCTRL_NAME_sleep_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_PINCTRL_NAME_sleep_IDX 1
#define DT_N_S_soc_S_spi_4002f000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_spi3_sleep

/* Generic property macros: */
#define DT_N_S_soc_S_spi_4002f000_P_wakeup_source 0
#define DT_N_S_soc_S_spi_4002f000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_spi_4002f000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_P_status "okay"
#define DT_N_S_soc_S_spi_4002f000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_spi_4002f000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_spi_4002f000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_spi_4002f000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_spi_4002f000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_spi_4002f000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_spi_4002f000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_spi_4002f000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_4002f000, status, 0)
#define DT_N_S_soc_S_spi_4002f000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_4002f000, status, 0)
#define DT_N_S_soc_S_spi_4002f000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_4002f000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_4002f000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_4002f000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_4002f000_P_status_LEN 1
#define DT_N_S_soc_S_spi_4002f000_P_status_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_P_compatible {"nordic,nrf-spim"}
#define DT_N_S_soc_S_spi_4002f000_P_compatible_IDX_0 "nordic,nrf-spim"
#define DT_N_S_soc_S_spi_4002f000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-spim
#define DT_N_S_soc_S_spi_4002f000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_spim
#define DT_N_S_soc_S_spi_4002f000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_SPIM
#define DT_N_S_soc_S_spi_4002f000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_4002f000, compatible, 0)
#define DT_N_S_soc_S_spi_4002f000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_4002f000, compatible, 0)
#define DT_N_S_soc_S_spi_4002f000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_4002f000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_4002f000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_4002f000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_4002f000_P_compatible_LEN 1
#define DT_N_S_soc_S_spi_4002f000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_P_reg {1073934336 /* 0x4002f000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_spi_4002f000_P_reg_IDX_0 1073934336
#define DT_N_S_soc_S_spi_4002f000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_spi_4002f000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_P_reg_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_P_interrupts {47 /* 0x2f */, 1 /* 0x1 */}
#define DT_N_S_soc_S_spi_4002f000_P_interrupts_IDX_0 47
#define DT_N_S_soc_S_spi_4002f000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_spi_4002f000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_spi_4002f000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_P_cs_gpios_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_P_cs_gpios_IDX_0_PH DT_N_S_soc_S_gpio_50000300
#define DT_N_S_soc_S_spi_4002f000_P_cs_gpios_IDX_0_VAL_pin 12
#define DT_N_S_soc_S_spi_4002f000_P_cs_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_P_cs_gpios_IDX_0_VAL_flags 1
#define DT_N_S_soc_S_spi_4002f000_P_cs_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_P_cs_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_4002f000, cs_gpios, 0)
#define DT_N_S_soc_S_spi_4002f000_P_cs_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_4002f000, cs_gpios, 0)
#define DT_N_S_soc_S_spi_4002f000_P_cs_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_4002f000, cs_gpios, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_4002f000_P_cs_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_4002f000, cs_gpios, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_4002f000_P_cs_gpios_LEN 1
#define DT_N_S_soc_S_spi_4002f000_P_cs_gpios_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_spi3_default
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_spi3_default
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_4002f000, pinctrl_0, 0)
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_4002f000, pinctrl_0, 0)
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_4002f000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_4002f000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_0_LEN 1
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_spi3_sleep
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_spi3_sleep
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_1_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_4002f000, pinctrl_1, 0)
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_4002f000, pinctrl_1, 0)
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_4002f000, pinctrl_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_4002f000, pinctrl_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_1_LEN 1
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_1_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_names {"default", "sleep"}
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_names_IDX_1 "sleep"
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_4002f000, pinctrl_names, 0) \
	fn(DT_N_S_soc_S_spi_4002f000, pinctrl_names, 1)
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_4002f000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_4002f000, pinctrl_names, 1)
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_4002f000, pinctrl_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_spi_4002f000, pinctrl_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_4002f000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_4002f000, pinctrl_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_names_LEN 2
#define DT_N_S_soc_S_spi_4002f000_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_P_max_frequency 32000000
#define DT_N_S_soc_S_spi_4002f000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_P_overrun_character 255
#define DT_N_S_soc_S_spi_4002f000_P_overrun_character_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_P_easydma_maxcnt_bits 16
#define DT_N_S_soc_S_spi_4002f000_P_easydma_maxcnt_bits_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_P_anomaly_58_workaround 0
#define DT_N_S_soc_S_spi_4002f000_P_anomaly_58_workaround_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_P_rx_delay_supported 1
#define DT_N_S_soc_S_spi_4002f000_P_rx_delay_supported_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_P_rx_delay 2
#define DT_N_S_soc_S_spi_4002f000_P_rx_delay_ENUM_IDX 2
#define DT_N_S_soc_S_spi_4002f000_P_rx_delay_ENUM_VAL_2_EXISTS 1
#define DT_N_S_soc_S_spi_4002f000_P_rx_delay_EXISTS 1

/*
 * Devicetree node: /soc/temp@4000c000
 *
 * Node identifier: DT_N_S_soc_S_temp_4000c000
 *
 * Binding (compatible = nordic,nrf-temp):
 *   $ZEPHYR_BASE/dts/bindings/sensor/nordic,nrf-temp.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_temp_4000c000_PATH "/soc/temp@4000c000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_temp_4000c000_FULL_NAME "temp@4000c000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_temp_4000c000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_temp_4000c000_CHILD_IDX 20

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_temp_4000c000_CHILD_NUM 0
#define DT_N_S_soc_S_temp_4000c000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_temp_4000c000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_temp_4000c000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_temp_4000c000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_temp_4000c000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_temp_4000c000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_temp_4000c000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_temp_4000c000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_temp_4000c000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_temp_4000c000_ORD 107
#define DT_N_S_soc_S_temp_4000c000_ORD_STR_SORTABLE 00107

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_temp_4000c000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_temp_4000c000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_temp_4000c000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_temp DT_N_S_soc_S_temp_4000c000
#define DT_N_NODELABEL_temp         DT_N_S_soc_S_temp_4000c000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_temp_4000c000_REG_NUM 1
#define DT_N_S_soc_S_temp_4000c000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_temp_4000c000_REG_IDX_0_VAL_ADDRESS 1073790976 /* 0x4000c000 */
#define DT_N_S_soc_S_temp_4000c000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_temp_4000c000_RANGES_NUM 0
#define DT_N_S_soc_S_temp_4000c000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_temp_4000c000_IRQ_NUM 1
#define DT_N_S_soc_S_temp_4000c000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_temp_4000c000_IRQ_IDX_0_VAL_irq 12
#define DT_N_S_soc_S_temp_4000c000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_temp_4000c000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_temp_4000c000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_temp_4000c000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_temp_4000c000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_temp_4000c000_IRQ_LEVEL 1
#define DT_N_S_soc_S_temp_4000c000_COMPAT_MATCHES_nordic_nrf_temp 1
#define DT_N_S_soc_S_temp_4000c000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_temp_4000c000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_temp_4000c000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_temp_4000c000_COMPAT_MODEL_IDX_0 "nrf-temp"
#define DT_N_S_soc_S_temp_4000c000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_temp_4000c000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_temp_4000c000_P_wakeup_source 0
#define DT_N_S_soc_S_temp_4000c000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_temp_4000c000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_temp_4000c000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_temp_4000c000_P_status "okay"
#define DT_N_S_soc_S_temp_4000c000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_temp_4000c000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_temp_4000c000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_temp_4000c000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_temp_4000c000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_temp_4000c000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_temp_4000c000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_temp_4000c000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_temp_4000c000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_temp_4000c000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_temp_4000c000, status, 0)
#define DT_N_S_soc_S_temp_4000c000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_temp_4000c000, status, 0)
#define DT_N_S_soc_S_temp_4000c000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_temp_4000c000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_temp_4000c000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_temp_4000c000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_temp_4000c000_P_status_LEN 1
#define DT_N_S_soc_S_temp_4000c000_P_status_EXISTS 1
#define DT_N_S_soc_S_temp_4000c000_P_compatible {"nordic,nrf-temp"}
#define DT_N_S_soc_S_temp_4000c000_P_compatible_IDX_0 "nordic,nrf-temp"
#define DT_N_S_soc_S_temp_4000c000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-temp
#define DT_N_S_soc_S_temp_4000c000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_temp
#define DT_N_S_soc_S_temp_4000c000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TEMP
#define DT_N_S_soc_S_temp_4000c000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_temp_4000c000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_temp_4000c000, compatible, 0)
#define DT_N_S_soc_S_temp_4000c000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_temp_4000c000, compatible, 0)
#define DT_N_S_soc_S_temp_4000c000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_temp_4000c000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_temp_4000c000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_temp_4000c000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_temp_4000c000_P_compatible_LEN 1
#define DT_N_S_soc_S_temp_4000c000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_temp_4000c000_P_reg {1073790976 /* 0x4000c000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_temp_4000c000_P_reg_IDX_0 1073790976
#define DT_N_S_soc_S_temp_4000c000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_temp_4000c000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_temp_4000c000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_temp_4000c000_P_reg_EXISTS 1
#define DT_N_S_soc_S_temp_4000c000_P_interrupts {12 /* 0xc */, 1 /* 0x1 */}
#define DT_N_S_soc_S_temp_4000c000_P_interrupts_IDX_0 12
#define DT_N_S_soc_S_temp_4000c000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_temp_4000c000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_temp_4000c000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_temp_4000c000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_temp_4000c000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_temp_4000c000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/timer@40008000
 *
 * Node identifier: DT_N_S_soc_S_timer_40008000
 *
 * Binding (compatible = nordic,nrf-timer):
 *   $ZEPHYR_BASE/dts/bindings/timer/nordic,nrf-timer.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timer_40008000_PATH "/soc/timer@40008000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timer_40008000_FULL_NAME "timer@40008000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timer_40008000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timer_40008000_CHILD_IDX 16

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timer_40008000_CHILD_NUM 0
#define DT_N_S_soc_S_timer_40008000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timer_40008000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timer_40008000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timer_40008000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timer_40008000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timer_40008000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timer_40008000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timer_40008000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timer_40008000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timer_40008000_ORD 108
#define DT_N_S_soc_S_timer_40008000_ORD_STR_SORTABLE 00108

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timer_40008000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timer_40008000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timer_40008000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_timer DT_N_S_soc_S_timer_40008000
#define DT_N_NODELABEL_timer0        DT_N_S_soc_S_timer_40008000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timer_40008000_REG_NUM 1
#define DT_N_S_soc_S_timer_40008000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_40008000_REG_IDX_0_VAL_ADDRESS 1073774592 /* 0x40008000 */
#define DT_N_S_soc_S_timer_40008000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_timer_40008000_RANGES_NUM 0
#define DT_N_S_soc_S_timer_40008000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timer_40008000_IRQ_NUM 1
#define DT_N_S_soc_S_timer_40008000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_40008000_IRQ_IDX_0_VAL_irq 8
#define DT_N_S_soc_S_timer_40008000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timer_40008000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_40008000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_timer_40008000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timer_40008000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timer_40008000_IRQ_LEVEL 1
#define DT_N_S_soc_S_timer_40008000_COMPAT_MATCHES_nordic_nrf_timer 1
#define DT_N_S_soc_S_timer_40008000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_40008000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_timer_40008000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_40008000_COMPAT_MODEL_IDX_0 "nrf-timer"
#define DT_N_S_soc_S_timer_40008000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timer_40008000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timer_40008000_P_wakeup_source 0
#define DT_N_S_soc_S_timer_40008000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timer_40008000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timer_40008000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_timer_40008000_P_status "disabled"
#define DT_N_S_soc_S_timer_40008000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timer_40008000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timer_40008000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timer_40008000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timer_40008000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_40008000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_timer_40008000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timer_40008000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_timer_40008000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timer_40008000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timer_40008000, status, 0)
#define DT_N_S_soc_S_timer_40008000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timer_40008000, status, 0)
#define DT_N_S_soc_S_timer_40008000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timer_40008000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_40008000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timer_40008000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_40008000_P_status_LEN 1
#define DT_N_S_soc_S_timer_40008000_P_status_EXISTS 1
#define DT_N_S_soc_S_timer_40008000_P_compatible {"nordic,nrf-timer"}
#define DT_N_S_soc_S_timer_40008000_P_compatible_IDX_0 "nordic,nrf-timer"
#define DT_N_S_soc_S_timer_40008000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-timer
#define DT_N_S_soc_S_timer_40008000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_timer
#define DT_N_S_soc_S_timer_40008000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TIMER
#define DT_N_S_soc_S_timer_40008000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_40008000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timer_40008000, compatible, 0)
#define DT_N_S_soc_S_timer_40008000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timer_40008000, compatible, 0)
#define DT_N_S_soc_S_timer_40008000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timer_40008000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_40008000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timer_40008000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_40008000_P_compatible_LEN 1
#define DT_N_S_soc_S_timer_40008000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timer_40008000_P_reg {1073774592 /* 0x40008000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_timer_40008000_P_reg_IDX_0 1073774592
#define DT_N_S_soc_S_timer_40008000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_40008000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_timer_40008000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timer_40008000_P_reg_EXISTS 1
#define DT_N_S_soc_S_timer_40008000_P_interrupts {8 /* 0x8 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_timer_40008000_P_interrupts_IDX_0 8
#define DT_N_S_soc_S_timer_40008000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_40008000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_timer_40008000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timer_40008000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timer_40008000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timer_40008000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timer_40008000_P_cc_num 4
#define DT_N_S_soc_S_timer_40008000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_timer_40008000_P_max_bit_width 32
#define DT_N_S_soc_S_timer_40008000_P_max_bit_width_EXISTS 1
#define DT_N_S_soc_S_timer_40008000_P_max_frequency 16000000
#define DT_N_S_soc_S_timer_40008000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_timer_40008000_P_prescaler 0
#define DT_N_S_soc_S_timer_40008000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_timer_40008000_P_zli 0
#define DT_N_S_soc_S_timer_40008000_P_zli_EXISTS 1

/*
 * Devicetree node: /soc/timer@4000a000
 *
 * Node identifier: DT_N_S_soc_S_timer_4000a000
 *
 * Binding (compatible = nordic,nrf-timer):
 *   $ZEPHYR_BASE/dts/bindings/timer/nordic,nrf-timer.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timer_4000a000_PATH "/soc/timer@4000a000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timer_4000a000_FULL_NAME "timer@4000a000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timer_4000a000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timer_4000a000_CHILD_IDX 18

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timer_4000a000_CHILD_NUM 0
#define DT_N_S_soc_S_timer_4000a000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timer_4000a000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timer_4000a000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timer_4000a000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timer_4000a000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timer_4000a000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timer_4000a000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timer_4000a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timer_4000a000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timer_4000a000_ORD 109
#define DT_N_S_soc_S_timer_4000a000_ORD_STR_SORTABLE 00109

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timer_4000a000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timer_4000a000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timer_4000a000_EXISTS 1
#define DT_N_INST_2_nordic_nrf_timer DT_N_S_soc_S_timer_4000a000
#define DT_N_NODELABEL_timer2        DT_N_S_soc_S_timer_4000a000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timer_4000a000_REG_NUM 1
#define DT_N_S_soc_S_timer_4000a000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4000a000_REG_IDX_0_VAL_ADDRESS 1073782784 /* 0x4000a000 */
#define DT_N_S_soc_S_timer_4000a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_timer_4000a000_RANGES_NUM 0
#define DT_N_S_soc_S_timer_4000a000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timer_4000a000_IRQ_NUM 1
#define DT_N_S_soc_S_timer_4000a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4000a000_IRQ_IDX_0_VAL_irq 10
#define DT_N_S_soc_S_timer_4000a000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timer_4000a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4000a000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_timer_4000a000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timer_4000a000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timer_4000a000_IRQ_LEVEL 1
#define DT_N_S_soc_S_timer_4000a000_COMPAT_MATCHES_nordic_nrf_timer 1
#define DT_N_S_soc_S_timer_4000a000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4000a000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_timer_4000a000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4000a000_COMPAT_MODEL_IDX_0 "nrf-timer"
#define DT_N_S_soc_S_timer_4000a000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timer_4000a000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timer_4000a000_P_wakeup_source 0
#define DT_N_S_soc_S_timer_4000a000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timer_4000a000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timer_4000a000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_timer_4000a000_P_status "disabled"
#define DT_N_S_soc_S_timer_4000a000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timer_4000a000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timer_4000a000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timer_4000a000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timer_4000a000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4000a000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_timer_4000a000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timer_4000a000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_timer_4000a000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timer_4000a000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timer_4000a000, status, 0)
#define DT_N_S_soc_S_timer_4000a000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timer_4000a000, status, 0)
#define DT_N_S_soc_S_timer_4000a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timer_4000a000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_4000a000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timer_4000a000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_4000a000_P_status_LEN 1
#define DT_N_S_soc_S_timer_4000a000_P_status_EXISTS 1
#define DT_N_S_soc_S_timer_4000a000_P_compatible {"nordic,nrf-timer"}
#define DT_N_S_soc_S_timer_4000a000_P_compatible_IDX_0 "nordic,nrf-timer"
#define DT_N_S_soc_S_timer_4000a000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-timer
#define DT_N_S_soc_S_timer_4000a000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_timer
#define DT_N_S_soc_S_timer_4000a000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TIMER
#define DT_N_S_soc_S_timer_4000a000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4000a000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timer_4000a000, compatible, 0)
#define DT_N_S_soc_S_timer_4000a000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timer_4000a000, compatible, 0)
#define DT_N_S_soc_S_timer_4000a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timer_4000a000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_4000a000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timer_4000a000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_4000a000_P_compatible_LEN 1
#define DT_N_S_soc_S_timer_4000a000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timer_4000a000_P_reg {1073782784 /* 0x4000a000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_timer_4000a000_P_reg_IDX_0 1073782784
#define DT_N_S_soc_S_timer_4000a000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4000a000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_timer_4000a000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timer_4000a000_P_reg_EXISTS 1
#define DT_N_S_soc_S_timer_4000a000_P_interrupts {10 /* 0xa */, 1 /* 0x1 */}
#define DT_N_S_soc_S_timer_4000a000_P_interrupts_IDX_0 10
#define DT_N_S_soc_S_timer_4000a000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4000a000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_timer_4000a000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timer_4000a000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timer_4000a000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timer_4000a000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timer_4000a000_P_cc_num 4
#define DT_N_S_soc_S_timer_4000a000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_timer_4000a000_P_max_bit_width 32
#define DT_N_S_soc_S_timer_4000a000_P_max_bit_width_EXISTS 1
#define DT_N_S_soc_S_timer_4000a000_P_max_frequency 16000000
#define DT_N_S_soc_S_timer_4000a000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_timer_4000a000_P_prescaler 0
#define DT_N_S_soc_S_timer_4000a000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_timer_4000a000_P_zli 0
#define DT_N_S_soc_S_timer_4000a000_P_zli_EXISTS 1

/*
 * Devicetree node: /soc/timer@4001a000
 *
 * Node identifier: DT_N_S_soc_S_timer_4001a000
 *
 * Binding (compatible = nordic,nrf-timer):
 *   $ZEPHYR_BASE/dts/bindings/timer/nordic,nrf-timer.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timer_4001a000_PATH "/soc/timer@4001a000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timer_4001a000_FULL_NAME "timer@4001a000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timer_4001a000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timer_4001a000_CHILD_IDX 34

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timer_4001a000_CHILD_NUM 0
#define DT_N_S_soc_S_timer_4001a000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timer_4001a000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timer_4001a000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timer_4001a000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timer_4001a000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timer_4001a000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timer_4001a000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timer_4001a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timer_4001a000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timer_4001a000_ORD 110
#define DT_N_S_soc_S_timer_4001a000_ORD_STR_SORTABLE 00110

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timer_4001a000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timer_4001a000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timer_4001a000_EXISTS 1
#define DT_N_INST_3_nordic_nrf_timer DT_N_S_soc_S_timer_4001a000
#define DT_N_NODELABEL_timer3        DT_N_S_soc_S_timer_4001a000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timer_4001a000_REG_NUM 1
#define DT_N_S_soc_S_timer_4001a000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4001a000_REG_IDX_0_VAL_ADDRESS 1073848320 /* 0x4001a000 */
#define DT_N_S_soc_S_timer_4001a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_timer_4001a000_RANGES_NUM 0
#define DT_N_S_soc_S_timer_4001a000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timer_4001a000_IRQ_NUM 1
#define DT_N_S_soc_S_timer_4001a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4001a000_IRQ_IDX_0_VAL_irq 26
#define DT_N_S_soc_S_timer_4001a000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timer_4001a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4001a000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_timer_4001a000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timer_4001a000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timer_4001a000_IRQ_LEVEL 1
#define DT_N_S_soc_S_timer_4001a000_COMPAT_MATCHES_nordic_nrf_timer 1
#define DT_N_S_soc_S_timer_4001a000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4001a000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_timer_4001a000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4001a000_COMPAT_MODEL_IDX_0 "nrf-timer"
#define DT_N_S_soc_S_timer_4001a000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timer_4001a000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timer_4001a000_P_wakeup_source 0
#define DT_N_S_soc_S_timer_4001a000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timer_4001a000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timer_4001a000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_timer_4001a000_P_status "disabled"
#define DT_N_S_soc_S_timer_4001a000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timer_4001a000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timer_4001a000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timer_4001a000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timer_4001a000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4001a000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_timer_4001a000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timer_4001a000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_timer_4001a000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timer_4001a000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timer_4001a000, status, 0)
#define DT_N_S_soc_S_timer_4001a000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timer_4001a000, status, 0)
#define DT_N_S_soc_S_timer_4001a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timer_4001a000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_4001a000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timer_4001a000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_4001a000_P_status_LEN 1
#define DT_N_S_soc_S_timer_4001a000_P_status_EXISTS 1
#define DT_N_S_soc_S_timer_4001a000_P_compatible {"nordic,nrf-timer"}
#define DT_N_S_soc_S_timer_4001a000_P_compatible_IDX_0 "nordic,nrf-timer"
#define DT_N_S_soc_S_timer_4001a000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-timer
#define DT_N_S_soc_S_timer_4001a000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_timer
#define DT_N_S_soc_S_timer_4001a000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TIMER
#define DT_N_S_soc_S_timer_4001a000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4001a000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timer_4001a000, compatible, 0)
#define DT_N_S_soc_S_timer_4001a000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timer_4001a000, compatible, 0)
#define DT_N_S_soc_S_timer_4001a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timer_4001a000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_4001a000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timer_4001a000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_4001a000_P_compatible_LEN 1
#define DT_N_S_soc_S_timer_4001a000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timer_4001a000_P_reg {1073848320 /* 0x4001a000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_timer_4001a000_P_reg_IDX_0 1073848320
#define DT_N_S_soc_S_timer_4001a000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4001a000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_timer_4001a000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timer_4001a000_P_reg_EXISTS 1
#define DT_N_S_soc_S_timer_4001a000_P_interrupts {26 /* 0x1a */, 1 /* 0x1 */}
#define DT_N_S_soc_S_timer_4001a000_P_interrupts_IDX_0 26
#define DT_N_S_soc_S_timer_4001a000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4001a000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_timer_4001a000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timer_4001a000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timer_4001a000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timer_4001a000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timer_4001a000_P_cc_num 6
#define DT_N_S_soc_S_timer_4001a000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_timer_4001a000_P_max_bit_width 32
#define DT_N_S_soc_S_timer_4001a000_P_max_bit_width_EXISTS 1
#define DT_N_S_soc_S_timer_4001a000_P_max_frequency 16000000
#define DT_N_S_soc_S_timer_4001a000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_timer_4001a000_P_prescaler 0
#define DT_N_S_soc_S_timer_4001a000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_timer_4001a000_P_zli 0
#define DT_N_S_soc_S_timer_4001a000_P_zli_EXISTS 1

/*
 * Devicetree node: /soc/timer@4001b000
 *
 * Node identifier: DT_N_S_soc_S_timer_4001b000
 *
 * Binding (compatible = nordic,nrf-timer):
 *   $ZEPHYR_BASE/dts/bindings/timer/nordic,nrf-timer.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timer_4001b000_PATH "/soc/timer@4001b000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timer_4001b000_FULL_NAME "timer@4001b000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timer_4001b000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timer_4001b000_CHILD_IDX 35

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timer_4001b000_CHILD_NUM 0
#define DT_N_S_soc_S_timer_4001b000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timer_4001b000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timer_4001b000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timer_4001b000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timer_4001b000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timer_4001b000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timer_4001b000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timer_4001b000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timer_4001b000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timer_4001b000_ORD 111
#define DT_N_S_soc_S_timer_4001b000_ORD_STR_SORTABLE 00111

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timer_4001b000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timer_4001b000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timer_4001b000_EXISTS 1
#define DT_N_INST_4_nordic_nrf_timer DT_N_S_soc_S_timer_4001b000
#define DT_N_NODELABEL_timer4        DT_N_S_soc_S_timer_4001b000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timer_4001b000_REG_NUM 1
#define DT_N_S_soc_S_timer_4001b000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4001b000_REG_IDX_0_VAL_ADDRESS 1073852416 /* 0x4001b000 */
#define DT_N_S_soc_S_timer_4001b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_timer_4001b000_RANGES_NUM 0
#define DT_N_S_soc_S_timer_4001b000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timer_4001b000_IRQ_NUM 1
#define DT_N_S_soc_S_timer_4001b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4001b000_IRQ_IDX_0_VAL_irq 27
#define DT_N_S_soc_S_timer_4001b000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_timer_4001b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4001b000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_timer_4001b000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_timer_4001b000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_timer_4001b000_IRQ_LEVEL 1
#define DT_N_S_soc_S_timer_4001b000_COMPAT_MATCHES_nordic_nrf_timer 1
#define DT_N_S_soc_S_timer_4001b000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4001b000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_timer_4001b000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4001b000_COMPAT_MODEL_IDX_0 "nrf-timer"
#define DT_N_S_soc_S_timer_4001b000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timer_4001b000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timer_4001b000_P_wakeup_source 0
#define DT_N_S_soc_S_timer_4001b000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timer_4001b000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timer_4001b000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_timer_4001b000_P_status "disabled"
#define DT_N_S_soc_S_timer_4001b000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timer_4001b000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timer_4001b000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timer_4001b000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timer_4001b000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4001b000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_timer_4001b000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timer_4001b000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_timer_4001b000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timer_4001b000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timer_4001b000, status, 0)
#define DT_N_S_soc_S_timer_4001b000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timer_4001b000, status, 0)
#define DT_N_S_soc_S_timer_4001b000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timer_4001b000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_4001b000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timer_4001b000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_4001b000_P_status_LEN 1
#define DT_N_S_soc_S_timer_4001b000_P_status_EXISTS 1
#define DT_N_S_soc_S_timer_4001b000_P_compatible {"nordic,nrf-timer"}
#define DT_N_S_soc_S_timer_4001b000_P_compatible_IDX_0 "nordic,nrf-timer"
#define DT_N_S_soc_S_timer_4001b000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-timer
#define DT_N_S_soc_S_timer_4001b000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_timer
#define DT_N_S_soc_S_timer_4001b000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_TIMER
#define DT_N_S_soc_S_timer_4001b000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4001b000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timer_4001b000, compatible, 0)
#define DT_N_S_soc_S_timer_4001b000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timer_4001b000, compatible, 0)
#define DT_N_S_soc_S_timer_4001b000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timer_4001b000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_4001b000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timer_4001b000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_4001b000_P_compatible_LEN 1
#define DT_N_S_soc_S_timer_4001b000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timer_4001b000_P_reg {1073852416 /* 0x4001b000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_timer_4001b000_P_reg_IDX_0 1073852416
#define DT_N_S_soc_S_timer_4001b000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4001b000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_timer_4001b000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timer_4001b000_P_reg_EXISTS 1
#define DT_N_S_soc_S_timer_4001b000_P_interrupts {27 /* 0x1b */, 1 /* 0x1 */}
#define DT_N_S_soc_S_timer_4001b000_P_interrupts_IDX_0 27
#define DT_N_S_soc_S_timer_4001b000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_4001b000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_timer_4001b000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timer_4001b000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_timer_4001b000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timer_4001b000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_timer_4001b000_P_cc_num 6
#define DT_N_S_soc_S_timer_4001b000_P_cc_num_EXISTS 1
#define DT_N_S_soc_S_timer_4001b000_P_max_bit_width 32
#define DT_N_S_soc_S_timer_4001b000_P_max_bit_width_EXISTS 1
#define DT_N_S_soc_S_timer_4001b000_P_max_frequency 16000000
#define DT_N_S_soc_S_timer_4001b000_P_max_frequency_EXISTS 1
#define DT_N_S_soc_S_timer_4001b000_P_prescaler 0
#define DT_N_S_soc_S_timer_4001b000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_timer_4001b000_P_zli 0
#define DT_N_S_soc_S_timer_4001b000_P_zli_EXISTS 1

/*
 * Devicetree node: /soc/timer@e000e010
 *
 * Node identifier: DT_N_S_soc_S_timer_e000e010
 *
 * Binding (compatible = arm,armv7m-systick):
 *   $ZEPHYR_BASE/dts/bindings/timer/arm,armv7m-systick.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_timer_e000e010_PATH "/soc/timer@e000e010"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_timer_e000e010_FULL_NAME "timer@e000e010"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timer_e000e010_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_timer_e000e010_CHILD_IDX 1

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_timer_e000e010_CHILD_NUM 0
#define DT_N_S_soc_S_timer_e000e010_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_timer_e000e010_ORD 112
#define DT_N_S_soc_S_timer_e000e010_ORD_STR_SORTABLE 00112

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_timer_e000e010_REQUIRES_ORDS \
	6, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_timer_e000e010_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timer_e000e010_EXISTS 1
#define DT_N_INST_0_arm_armv7m_systick DT_N_S_soc_S_timer_e000e010
#define DT_N_NODELABEL_systick         DT_N_S_soc_S_timer_e000e010

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_timer_e000e010_REG_NUM 1
#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_VAL_ADDRESS 3758153744 /* 0xe000e010 */
#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_VAL_SIZE 16 /* 0x10 */
#define DT_N_S_soc_S_timer_e000e010_RANGES_NUM 0
#define DT_N_S_soc_S_timer_e000e010_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_timer_e000e010_IRQ_NUM 0
#define DT_N_S_soc_S_timer_e000e010_IRQ_LEVEL 0
#define DT_N_S_soc_S_timer_e000e010_COMPAT_MATCHES_arm_armv7m_systick 1
#define DT_N_S_soc_S_timer_e000e010_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_COMPAT_VENDOR_IDX_0 "ARM Ltd."
#define DT_N_S_soc_S_timer_e000e010_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_COMPAT_MODEL_IDX_0 "armv7m-systick"
#define DT_N_S_soc_S_timer_e000e010_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_timer_e000e010_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_timer_e000e010_P_wakeup_source 0
#define DT_N_S_soc_S_timer_e000e010_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_timer_e000e010_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_status "disabled"
#define DT_N_S_soc_S_timer_e000e010_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_timer_e000e010_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_timer_e000e010_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timer_e000e010_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_timer_e000e010_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_timer_e000e010_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_timer_e000e010_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_timer_e000e010_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timer_e000e010, status, 0)
#define DT_N_S_soc_S_timer_e000e010_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timer_e000e010, status, 0)
#define DT_N_S_soc_S_timer_e000e010_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timer_e000e010, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_e000e010_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timer_e000e010, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_e000e010_P_status_LEN 1
#define DT_N_S_soc_S_timer_e000e010_P_status_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_compatible {"arm,armv7m-systick"}
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0 "arm,armv7m-systick"
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_STRING_UNQUOTED arm,armv7m-systick
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_STRING_TOKEN arm_armv7m_systick
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_ARMV7M_SYSTICK
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0)
#define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0)
#define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_timer_e000e010_P_compatible_LEN 1
#define DT_N_S_soc_S_timer_e000e010_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_reg {3758153744 /* 0xe000e010 */, 16 /* 0x10 */}
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_0 3758153744
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_1 16
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_reg_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_timer_e000e010_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/uart@40002000
 *
 * Node identifier: DT_N_S_soc_S_uart_40002000
 *
 * Binding (compatible = nordic,nrf-uarte):
 *   $ZEPHYR_BASE/dts/bindings/serial/nordic,nrf-uarte.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_uart_40002000_PATH "/soc/uart@40002000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_uart_40002000_FULL_NAME "uart@40002000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_uart_40002000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_uart_40002000_CHILD_IDX 8

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_uart_40002000_CHILD_NUM 0
#define DT_N_S_soc_S_uart_40002000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_uart_40002000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_uart_40002000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_uart_40002000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_uart_40002000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_uart_40002000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_uart_40002000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_uart_40002000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_uart_40002000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_uart_40002000_ORD 113
#define DT_N_S_soc_S_uart_40002000_ORD_STR_SORTABLE 00113

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_uart_40002000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */ \
	59, /* /pin-controller/uart0_default */ \
	62, /* /pin-controller/uart0_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_uart_40002000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_uart_40002000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_uarte DT_N_S_soc_S_uart_40002000
#define DT_N_NODELABEL_uart0         DT_N_S_soc_S_uart_40002000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_uart_40002000_REG_NUM 1
#define DT_N_S_soc_S_uart_40002000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_REG_IDX_0_VAL_ADDRESS 1073750016 /* 0x40002000 */
#define DT_N_S_soc_S_uart_40002000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_uart_40002000_RANGES_NUM 0
#define DT_N_S_soc_S_uart_40002000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_uart_40002000_IRQ_NUM 1
#define DT_N_S_soc_S_uart_40002000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_IRQ_IDX_0_VAL_irq 2
#define DT_N_S_soc_S_uart_40002000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_uart_40002000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_uart_40002000_IRQ_LEVEL 1
#define DT_N_S_soc_S_uart_40002000_COMPAT_MATCHES_nordic_nrf_uarte 1
#define DT_N_S_soc_S_uart_40002000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_uart_40002000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_COMPAT_MODEL_IDX_0 "nrf-uarte"
#define DT_N_S_soc_S_uart_40002000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_uart_40002000_PINCTRL_NUM 2
#define DT_N_S_soc_S_uart_40002000_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_uart_40002000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_uart_40002000_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_uart_40002000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_uart0_default
#define DT_N_S_soc_S_uart_40002000_PINCTRL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_PINCTRL_IDX_1_TOKEN sleep
#define DT_N_S_soc_S_uart_40002000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP
#define DT_N_S_soc_S_uart_40002000_PINCTRL_NAME_sleep_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_PINCTRL_NAME_sleep_IDX 1
#define DT_N_S_soc_S_uart_40002000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_uart0_sleep

/* Generic property macros: */
#define DT_N_S_soc_S_uart_40002000_P_wakeup_source 0
#define DT_N_S_soc_S_uart_40002000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_uart_40002000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_P_status "okay"
#define DT_N_S_soc_S_uart_40002000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_uart_40002000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_uart_40002000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_uart_40002000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_uart_40002000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_uart_40002000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_uart_40002000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_uart_40002000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_40002000, status, 0)
#define DT_N_S_soc_S_uart_40002000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_40002000, status, 0)
#define DT_N_S_soc_S_uart_40002000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_40002000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_40002000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_40002000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_40002000_P_status_LEN 1
#define DT_N_S_soc_S_uart_40002000_P_status_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_P_compatible {"nordic,nrf-uarte"}
#define DT_N_S_soc_S_uart_40002000_P_compatible_IDX_0 "nordic,nrf-uarte"
#define DT_N_S_soc_S_uart_40002000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-uarte
#define DT_N_S_soc_S_uart_40002000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uarte
#define DT_N_S_soc_S_uart_40002000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UARTE
#define DT_N_S_soc_S_uart_40002000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_40002000, compatible, 0)
#define DT_N_S_soc_S_uart_40002000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_40002000, compatible, 0)
#define DT_N_S_soc_S_uart_40002000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_40002000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_40002000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_40002000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_40002000_P_compatible_LEN 1
#define DT_N_S_soc_S_uart_40002000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_P_reg {1073750016 /* 0x40002000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_uart_40002000_P_reg_IDX_0 1073750016
#define DT_N_S_soc_S_uart_40002000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_uart_40002000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_P_reg_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_P_interrupts {2 /* 0x2 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_uart_40002000_P_interrupts_IDX_0 2
#define DT_N_S_soc_S_uart_40002000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_uart_40002000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_uart_40002000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_P_current_speed 115200
#define DT_N_S_soc_S_uart_40002000_P_current_speed_ENUM_IDX 12
#define DT_N_S_soc_S_uart_40002000_P_current_speed_ENUM_VAL_115200_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_P_current_speed_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_P_hw_flow_control 0
#define DT_N_S_soc_S_uart_40002000_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_uart0_default
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_uart0_default
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_40002000, pinctrl_0, 0)
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_40002000, pinctrl_0, 0)
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_40002000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_40002000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_0_LEN 1
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_uart0_sleep
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_uart0_sleep
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_1_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_40002000, pinctrl_1, 0)
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_40002000, pinctrl_1, 0)
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_40002000, pinctrl_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_40002000, pinctrl_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_1_LEN 1
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_1_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_names {"default", "sleep"}
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_names_IDX_1 "sleep"
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_40002000, pinctrl_names, 0) \
	fn(DT_N_S_soc_S_uart_40002000, pinctrl_names, 1)
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_40002000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_uart_40002000, pinctrl_names, 1)
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_40002000, pinctrl_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_uart_40002000, pinctrl_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_40002000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_uart_40002000, pinctrl_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_names_LEN 2
#define DT_N_S_soc_S_uart_40002000_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_uart_40002000_P_disable_rx 0
#define DT_N_S_soc_S_uart_40002000_P_disable_rx_EXISTS 1

/*
 * Devicetree node: /soc/uart@40028000
 *
 * Node identifier: DT_N_S_soc_S_uart_40028000
 *
 * Binding (compatible = nordic,nrf-uarte):
 *   $ZEPHYR_BASE/dts/bindings/serial/nordic,nrf-uarte.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_uart_40028000_PATH "/soc/uart@40028000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_uart_40028000_FULL_NAME "uart@40028000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_uart_40028000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_uart_40028000_CHILD_IDX 48

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_uart_40028000_CHILD_NUM 0
#define DT_N_S_soc_S_uart_40028000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_uart_40028000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_uart_40028000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_uart_40028000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_uart_40028000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_uart_40028000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_uart_40028000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_uart_40028000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_uart_40028000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_uart_40028000_ORD 114
#define DT_N_S_soc_S_uart_40028000_ORD_STR_SORTABLE 00114

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_uart_40028000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */ \
	64, /* /pin-controller/uart1_default */ \
	67, /* /pin-controller/uart1_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_uart_40028000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_uart_40028000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_uarte  DT_N_S_soc_S_uart_40028000
#define DT_N_NODELABEL_uart1          DT_N_S_soc_S_uart_40028000
#define DT_N_NODELABEL_arduino_serial DT_N_S_soc_S_uart_40028000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_uart_40028000_REG_NUM 1
#define DT_N_S_soc_S_uart_40028000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_REG_IDX_0_VAL_ADDRESS 1073905664 /* 0x40028000 */
#define DT_N_S_soc_S_uart_40028000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_uart_40028000_RANGES_NUM 0
#define DT_N_S_soc_S_uart_40028000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_uart_40028000_IRQ_NUM 1
#define DT_N_S_soc_S_uart_40028000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_IRQ_IDX_0_VAL_irq 40
#define DT_N_S_soc_S_uart_40028000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_uart_40028000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_uart_40028000_IRQ_LEVEL 1
#define DT_N_S_soc_S_uart_40028000_COMPAT_MATCHES_nordic_nrf_uarte 1
#define DT_N_S_soc_S_uart_40028000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_uart_40028000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_COMPAT_MODEL_IDX_0 "nrf-uarte"
#define DT_N_S_soc_S_uart_40028000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_uart_40028000_PINCTRL_NUM 2
#define DT_N_S_soc_S_uart_40028000_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_uart_40028000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_uart_40028000_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_uart_40028000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_uart1_default
#define DT_N_S_soc_S_uart_40028000_PINCTRL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_PINCTRL_IDX_1_TOKEN sleep
#define DT_N_S_soc_S_uart_40028000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP
#define DT_N_S_soc_S_uart_40028000_PINCTRL_NAME_sleep_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_PINCTRL_NAME_sleep_IDX 1
#define DT_N_S_soc_S_uart_40028000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_uart1_sleep

/* Generic property macros: */
#define DT_N_S_soc_S_uart_40028000_P_wakeup_source 0
#define DT_N_S_soc_S_uart_40028000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_uart_40028000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_P_status "disabled"
#define DT_N_S_soc_S_uart_40028000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_uart_40028000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_uart_40028000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_uart_40028000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_uart_40028000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_uart_40028000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_P_status_ENUM_TOKEN disabled
#define DT_N_S_soc_S_uart_40028000_P_status_ENUM_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_uart_40028000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_40028000, status, 0)
#define DT_N_S_soc_S_uart_40028000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_40028000, status, 0)
#define DT_N_S_soc_S_uart_40028000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_40028000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_40028000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_40028000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_40028000_P_status_LEN 1
#define DT_N_S_soc_S_uart_40028000_P_status_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_P_compatible {"nordic,nrf-uarte"}
#define DT_N_S_soc_S_uart_40028000_P_compatible_IDX_0 "nordic,nrf-uarte"
#define DT_N_S_soc_S_uart_40028000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-uarte
#define DT_N_S_soc_S_uart_40028000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uarte
#define DT_N_S_soc_S_uart_40028000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UARTE
#define DT_N_S_soc_S_uart_40028000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_40028000, compatible, 0)
#define DT_N_S_soc_S_uart_40028000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_40028000, compatible, 0)
#define DT_N_S_soc_S_uart_40028000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_40028000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_40028000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_40028000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_40028000_P_compatible_LEN 1
#define DT_N_S_soc_S_uart_40028000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_P_reg {1073905664 /* 0x40028000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_uart_40028000_P_reg_IDX_0 1073905664
#define DT_N_S_soc_S_uart_40028000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_uart_40028000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_P_reg_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_P_interrupts {40 /* 0x28 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_uart_40028000_P_interrupts_IDX_0 40
#define DT_N_S_soc_S_uart_40028000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_uart_40028000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_uart_40028000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_P_current_speed 115200
#define DT_N_S_soc_S_uart_40028000_P_current_speed_ENUM_IDX 12
#define DT_N_S_soc_S_uart_40028000_P_current_speed_ENUM_VAL_115200_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_P_current_speed_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_P_hw_flow_control 0
#define DT_N_S_soc_S_uart_40028000_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_uart1_default
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_uart1_default
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_40028000, pinctrl_0, 0)
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_40028000, pinctrl_0, 0)
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_40028000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_40028000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_0_LEN 1
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_uart1_sleep
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_uart1_sleep
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_1_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_40028000, pinctrl_1, 0)
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_40028000, pinctrl_1, 0)
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_40028000, pinctrl_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_40028000, pinctrl_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_1_LEN 1
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_1_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_names {"default", "sleep"}
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_names_IDX_1 "sleep"
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_40028000, pinctrl_names, 0) \
	fn(DT_N_S_soc_S_uart_40028000, pinctrl_names, 1)
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_40028000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_uart_40028000, pinctrl_names, 1)
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_40028000, pinctrl_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_uart_40028000, pinctrl_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_40028000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_uart_40028000, pinctrl_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_names_LEN 2
#define DT_N_S_soc_S_uart_40028000_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_uart_40028000_P_disable_rx 0
#define DT_N_S_soc_S_uart_40028000_P_disable_rx_EXISTS 1

/*
 * Devicetree node: /soc/uicr@10001000
 *
 * Node identifier: DT_N_S_soc_S_uicr_10001000
 *
 * Binding (compatible = nordic,nrf-uicr):
 *   $ZEPHYR_BASE/dts/bindings/arm/nordic,nrf-uicr.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_uicr_10001000_PATH "/soc/uicr@10001000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_uicr_10001000_FULL_NAME "uicr@10001000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_uicr_10001000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_uicr_10001000_CHILD_IDX 3

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_uicr_10001000_CHILD_NUM 0
#define DT_N_S_soc_S_uicr_10001000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_uicr_10001000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_uicr_10001000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_uicr_10001000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_uicr_10001000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_uicr_10001000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_uicr_10001000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_uicr_10001000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_uicr_10001000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_uicr_10001000_ORD 115
#define DT_N_S_soc_S_uicr_10001000_ORD_STR_SORTABLE 00115

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_uicr_10001000_REQUIRES_ORDS \
	6, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_uicr_10001000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_uicr_10001000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_uicr DT_N_S_soc_S_uicr_10001000
#define DT_N_NODELABEL_uicr         DT_N_S_soc_S_uicr_10001000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_uicr_10001000_REG_NUM 1
#define DT_N_S_soc_S_uicr_10001000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uicr_10001000_REG_IDX_0_VAL_ADDRESS 268439552 /* 0x10001000 */
#define DT_N_S_soc_S_uicr_10001000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_uicr_10001000_RANGES_NUM 0
#define DT_N_S_soc_S_uicr_10001000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_uicr_10001000_IRQ_NUM 0
#define DT_N_S_soc_S_uicr_10001000_IRQ_LEVEL 0
#define DT_N_S_soc_S_uicr_10001000_COMPAT_MATCHES_nordic_nrf_uicr 1
#define DT_N_S_soc_S_uicr_10001000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uicr_10001000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_uicr_10001000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uicr_10001000_COMPAT_MODEL_IDX_0 "nrf-uicr"
#define DT_N_S_soc_S_uicr_10001000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_uicr_10001000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_uicr_10001000_P_wakeup_source 0
#define DT_N_S_soc_S_uicr_10001000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_uicr_10001000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_uicr_10001000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_uicr_10001000_P_status "okay"
#define DT_N_S_soc_S_uicr_10001000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_uicr_10001000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_uicr_10001000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_uicr_10001000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_uicr_10001000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uicr_10001000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_uicr_10001000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_uicr_10001000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_uicr_10001000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_uicr_10001000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uicr_10001000, status, 0)
#define DT_N_S_soc_S_uicr_10001000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uicr_10001000, status, 0)
#define DT_N_S_soc_S_uicr_10001000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uicr_10001000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uicr_10001000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uicr_10001000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uicr_10001000_P_status_LEN 1
#define DT_N_S_soc_S_uicr_10001000_P_status_EXISTS 1
#define DT_N_S_soc_S_uicr_10001000_P_compatible {"nordic,nrf-uicr"}
#define DT_N_S_soc_S_uicr_10001000_P_compatible_IDX_0 "nordic,nrf-uicr"
#define DT_N_S_soc_S_uicr_10001000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-uicr
#define DT_N_S_soc_S_uicr_10001000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_uicr
#define DT_N_S_soc_S_uicr_10001000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_UICR
#define DT_N_S_soc_S_uicr_10001000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uicr_10001000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uicr_10001000, compatible, 0)
#define DT_N_S_soc_S_uicr_10001000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uicr_10001000, compatible, 0)
#define DT_N_S_soc_S_uicr_10001000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uicr_10001000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uicr_10001000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uicr_10001000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uicr_10001000_P_compatible_LEN 1
#define DT_N_S_soc_S_uicr_10001000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_uicr_10001000_P_reg {268439552 /* 0x10001000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_uicr_10001000_P_reg_IDX_0 268439552
#define DT_N_S_soc_S_uicr_10001000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uicr_10001000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_uicr_10001000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_uicr_10001000_P_reg_EXISTS 1
#define DT_N_S_soc_S_uicr_10001000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_uicr_10001000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_uicr_10001000_P_nfct_pins_as_gpios 0
#define DT_N_S_soc_S_uicr_10001000_P_nfct_pins_as_gpios_EXISTS 1
#define DT_N_S_soc_S_uicr_10001000_P_gpio_as_nreset 1
#define DT_N_S_soc_S_uicr_10001000_P_gpio_as_nreset_EXISTS 1

/*
 * Devicetree node: /soc/usbd@40027000
 *
 * Node identifier: DT_N_S_soc_S_usbd_40027000
 *
 * Binding (compatible = nordic,nrf-usbd):
 *   $ZEPHYR_BASE/dts/bindings/usb/nordic,nrf-usbd.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_usbd_40027000_PATH "/soc/usbd@40027000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_usbd_40027000_FULL_NAME "usbd@40027000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_usbd_40027000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_usbd_40027000_CHILD_IDX 47

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_usbd_40027000_CHILD_NUM 0
#define DT_N_S_soc_S_usbd_40027000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_usbd_40027000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_usbd_40027000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_usbd_40027000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_usbd_40027000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_usbd_40027000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_usbd_40027000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_usbd_40027000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_usbd_40027000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_usbd_40027000_ORD 116
#define DT_N_S_soc_S_usbd_40027000_ORD_STR_SORTABLE 00116

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_usbd_40027000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_usbd_40027000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_usbd_40027000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_usbd DT_N_S_soc_S_usbd_40027000
#define DT_N_NODELABEL_usbd         DT_N_S_soc_S_usbd_40027000
#define DT_N_NODELABEL_zephyr_udc0  DT_N_S_soc_S_usbd_40027000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_usbd_40027000_REG_NUM 1
#define DT_N_S_soc_S_usbd_40027000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usbd_40027000_REG_IDX_0_VAL_ADDRESS 1073901568 /* 0x40027000 */
#define DT_N_S_soc_S_usbd_40027000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_usbd_40027000_RANGES_NUM 0
#define DT_N_S_soc_S_usbd_40027000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_usbd_40027000_IRQ_NUM 1
#define DT_N_S_soc_S_usbd_40027000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usbd_40027000_IRQ_IDX_0_VAL_irq 39
#define DT_N_S_soc_S_usbd_40027000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_usbd_40027000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usbd_40027000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_usbd_40027000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_usbd_40027000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_usbd_40027000_IRQ_LEVEL 1
#define DT_N_S_soc_S_usbd_40027000_COMPAT_MATCHES_nordic_nrf_usbd 1
#define DT_N_S_soc_S_usbd_40027000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usbd_40027000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_usbd_40027000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usbd_40027000_COMPAT_MODEL_IDX_0 "nrf-usbd"
#define DT_N_S_soc_S_usbd_40027000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_usbd_40027000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_usbd_40027000_P_wakeup_source 0
#define DT_N_S_soc_S_usbd_40027000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_usbd_40027000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_usbd_40027000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_usbd_40027000_P_status "okay"
#define DT_N_S_soc_S_usbd_40027000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_usbd_40027000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_usbd_40027000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_usbd_40027000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_usbd_40027000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usbd_40027000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_usbd_40027000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_usbd_40027000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_usbd_40027000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_usbd_40027000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usbd_40027000, status, 0)
#define DT_N_S_soc_S_usbd_40027000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usbd_40027000, status, 0)
#define DT_N_S_soc_S_usbd_40027000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usbd_40027000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usbd_40027000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usbd_40027000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usbd_40027000_P_status_LEN 1
#define DT_N_S_soc_S_usbd_40027000_P_status_EXISTS 1
#define DT_N_S_soc_S_usbd_40027000_P_compatible {"nordic,nrf-usbd"}
#define DT_N_S_soc_S_usbd_40027000_P_compatible_IDX_0 "nordic,nrf-usbd"
#define DT_N_S_soc_S_usbd_40027000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-usbd
#define DT_N_S_soc_S_usbd_40027000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_usbd
#define DT_N_S_soc_S_usbd_40027000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_USBD
#define DT_N_S_soc_S_usbd_40027000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usbd_40027000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usbd_40027000, compatible, 0)
#define DT_N_S_soc_S_usbd_40027000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usbd_40027000, compatible, 0)
#define DT_N_S_soc_S_usbd_40027000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usbd_40027000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usbd_40027000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usbd_40027000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usbd_40027000_P_compatible_LEN 1
#define DT_N_S_soc_S_usbd_40027000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_usbd_40027000_P_reg {1073901568 /* 0x40027000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_usbd_40027000_P_reg_IDX_0 1073901568
#define DT_N_S_soc_S_usbd_40027000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usbd_40027000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_usbd_40027000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_usbd_40027000_P_reg_EXISTS 1
#define DT_N_S_soc_S_usbd_40027000_P_interrupts {39 /* 0x27 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_usbd_40027000_P_interrupts_IDX_0 39
#define DT_N_S_soc_S_usbd_40027000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usbd_40027000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_usbd_40027000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_usbd_40027000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_usbd_40027000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_usbd_40027000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_usbd_40027000_P_num_bidir_endpoints 1
#define DT_N_S_soc_S_usbd_40027000_P_num_bidir_endpoints_EXISTS 1
#define DT_N_S_soc_S_usbd_40027000_P_num_in_endpoints 7
#define DT_N_S_soc_S_usbd_40027000_P_num_in_endpoints_EXISTS 1
#define DT_N_S_soc_S_usbd_40027000_P_num_out_endpoints 7
#define DT_N_S_soc_S_usbd_40027000_P_num_out_endpoints_EXISTS 1
#define DT_N_S_soc_S_usbd_40027000_P_num_isoin_endpoints 1
#define DT_N_S_soc_S_usbd_40027000_P_num_isoin_endpoints_EXISTS 1
#define DT_N_S_soc_S_usbd_40027000_P_num_isoout_endpoints 1
#define DT_N_S_soc_S_usbd_40027000_P_num_isoout_endpoints_EXISTS 1

/*
 * Devicetree node: /soc/watchdog@40010000
 *
 * Node identifier: DT_N_S_soc_S_watchdog_40010000
 *
 * Binding (compatible = nordic,nrf-wdt):
 *   $ZEPHYR_BASE/dts/bindings/watchdog/nordic,nrf-wdt.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_watchdog_40010000_PATH "/soc/watchdog@40010000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_watchdog_40010000_FULL_NAME "watchdog@40010000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_watchdog_40010000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_watchdog_40010000_CHILD_IDX 24

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_watchdog_40010000_CHILD_NUM 0
#define DT_N_S_soc_S_watchdog_40010000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_watchdog_40010000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_watchdog_40010000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_watchdog_40010000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_watchdog_40010000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_watchdog_40010000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_watchdog_40010000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_watchdog_40010000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_watchdog_40010000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_watchdog_40010000_ORD 117
#define DT_N_S_soc_S_watchdog_40010000_ORD_STR_SORTABLE 00117

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_watchdog_40010000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_watchdog_40010000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_watchdog_40010000_EXISTS 1
#define DT_N_ALIAS_watchdog0       DT_N_S_soc_S_watchdog_40010000
#define DT_N_INST_0_nordic_nrf_wdt DT_N_S_soc_S_watchdog_40010000
#define DT_N_NODELABEL_wdt         DT_N_S_soc_S_watchdog_40010000
#define DT_N_NODELABEL_wdt0        DT_N_S_soc_S_watchdog_40010000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_watchdog_40010000_REG_NUM 1
#define DT_N_S_soc_S_watchdog_40010000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40010000_REG_IDX_0_VAL_ADDRESS 1073807360 /* 0x40010000 */
#define DT_N_S_soc_S_watchdog_40010000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_watchdog_40010000_RANGES_NUM 0
#define DT_N_S_soc_S_watchdog_40010000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_watchdog_40010000_IRQ_NUM 1
#define DT_N_S_soc_S_watchdog_40010000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40010000_IRQ_IDX_0_VAL_irq 16
#define DT_N_S_soc_S_watchdog_40010000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_watchdog_40010000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40010000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_watchdog_40010000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_watchdog_40010000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_watchdog_40010000_IRQ_LEVEL 1
#define DT_N_S_soc_S_watchdog_40010000_COMPAT_MATCHES_nordic_nrf_wdt 1
#define DT_N_S_soc_S_watchdog_40010000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40010000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_watchdog_40010000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40010000_COMPAT_MODEL_IDX_0 "nrf-wdt"
#define DT_N_S_soc_S_watchdog_40010000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_watchdog_40010000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_watchdog_40010000_P_wakeup_source 0
#define DT_N_S_soc_S_watchdog_40010000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_watchdog_40010000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_watchdog_40010000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_watchdog_40010000_P_status "okay"
#define DT_N_S_soc_S_watchdog_40010000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_watchdog_40010000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_watchdog_40010000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_watchdog_40010000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_watchdog_40010000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40010000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_watchdog_40010000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_watchdog_40010000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_watchdog_40010000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_watchdog_40010000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_watchdog_40010000, status, 0)
#define DT_N_S_soc_S_watchdog_40010000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_40010000, status, 0)
#define DT_N_S_soc_S_watchdog_40010000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_watchdog_40010000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40010000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_watchdog_40010000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40010000_P_status_LEN 1
#define DT_N_S_soc_S_watchdog_40010000_P_status_EXISTS 1
#define DT_N_S_soc_S_watchdog_40010000_P_compatible {"nordic,nrf-wdt"}
#define DT_N_S_soc_S_watchdog_40010000_P_compatible_IDX_0 "nordic,nrf-wdt"
#define DT_N_S_soc_S_watchdog_40010000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-wdt
#define DT_N_S_soc_S_watchdog_40010000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_wdt
#define DT_N_S_soc_S_watchdog_40010000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_WDT
#define DT_N_S_soc_S_watchdog_40010000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40010000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_watchdog_40010000, compatible, 0)
#define DT_N_S_soc_S_watchdog_40010000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_40010000, compatible, 0)
#define DT_N_S_soc_S_watchdog_40010000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_watchdog_40010000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40010000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_watchdog_40010000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_40010000_P_compatible_LEN 1
#define DT_N_S_soc_S_watchdog_40010000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_watchdog_40010000_P_reg {1073807360 /* 0x40010000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_watchdog_40010000_P_reg_IDX_0 1073807360
#define DT_N_S_soc_S_watchdog_40010000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40010000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_watchdog_40010000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_watchdog_40010000_P_reg_EXISTS 1
#define DT_N_S_soc_S_watchdog_40010000_P_interrupts {16 /* 0x10 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_watchdog_40010000_P_interrupts_IDX_0 16
#define DT_N_S_soc_S_watchdog_40010000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_40010000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_watchdog_40010000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_watchdog_40010000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_watchdog_40010000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_watchdog_40010000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@4001e000
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_4001e000
 *
 * Binding (compatible = nordic,nrf52-flash-controller):
 *   $ZEPHYR_BASE/dts/bindings/flash_controller/nordic,nrf52-flash-controller.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_4001e000_PATH "/soc/flash-controller@4001e000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_4001e000_FULL_NAME "flash-controller@4001e000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_flash_controller_4001e000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_4001e000_CHILD_IDX 39

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_4001e000_CHILD_NUM 1
#define DT_N_S_soc_S_flash_controller_4001e000_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_soc_S_flash_controller_4001e000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0)
#define DT_N_S_soc_S_flash_controller_4001e000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0)
#define DT_N_S_soc_S_flash_controller_4001e000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_4001e000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_4001e000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0)
#define DT_N_S_soc_S_flash_controller_4001e000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0)
#define DT_N_S_soc_S_flash_controller_4001e000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_4001e000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_4001e000_ORD 118
#define DT_N_S_soc_S_flash_controller_4001e000_ORD_STR_SORTABLE 00118

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_4001e000_REQUIRES_ORDS \
	6, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_4001e000_SUPPORTS_ORDS \
	119, /* /soc/flash-controller@4001e000/flash@0 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_4001e000_EXISTS 1
#define DT_N_INST_0_nordic_nrf52_flash_controller DT_N_S_soc_S_flash_controller_4001e000
#define DT_N_NODELABEL_flash_controller           DT_N_S_soc_S_flash_controller_4001e000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_4001e000_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_4001e000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_REG_IDX_0_VAL_ADDRESS 1073864704 /* 0x4001e000 */
#define DT_N_S_soc_S_flash_controller_4001e000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_flash_controller_4001e000_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_4001e000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_4001e000_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_4001e000_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_4001e000_COMPAT_MATCHES_nordic_nrf52_flash_controller 1
#define DT_N_S_soc_S_flash_controller_4001e000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_flash_controller_4001e000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_COMPAT_MODEL_IDX_0 "nrf52-flash-controller"
#define DT_N_S_soc_S_flash_controller_4001e000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_4001e000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_4001e000_P_wakeup_source 0
#define DT_N_S_soc_S_flash_controller_4001e000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_flash_controller_4001e000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_P_compatible {"nordic,nrf52-flash-controller"}
#define DT_N_S_soc_S_flash_controller_4001e000_P_compatible_IDX_0 "nordic,nrf52-flash-controller"
#define DT_N_S_soc_S_flash_controller_4001e000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf52-flash-controller
#define DT_N_S_soc_S_flash_controller_4001e000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf52_flash_controller
#define DT_N_S_soc_S_flash_controller_4001e000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF52_FLASH_CONTROLLER
#define DT_N_S_soc_S_flash_controller_4001e000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_4001e000, compatible, 0)
#define DT_N_S_soc_S_flash_controller_4001e000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_4001e000, compatible, 0)
#define DT_N_S_soc_S_flash_controller_4001e000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_4001e000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_4001e000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_4001e000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_4001e000_P_compatible_LEN 1
#define DT_N_S_soc_S_flash_controller_4001e000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_P_reg {1073864704 /* 0x4001e000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_flash_controller_4001e000_P_reg_IDX_0 1073864704
#define DT_N_S_soc_S_flash_controller_4001e000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_flash_controller_4001e000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_P_reg_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_flash_controller_4001e000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_P_partial_erase 1
#define DT_N_S_soc_S_flash_controller_4001e000_P_partial_erase_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@4001e000/flash@0
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_4001e000_S_flash_0
 *
 * Binding (compatible = soc-nv-flash):
 *   $ZEPHYR_BASE/dts/bindings/mtd/soc-nv-flash.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_PATH "/soc/flash-controller@4001e000/flash@0"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_FULL_NAME "flash@0"

/* Node parent (/soc/flash-controller@4001e000) identifier: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_PARENT DT_N_S_soc_S_flash_controller_4001e000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_CHILD_NUM 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_ORD 119
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_ORD_STR_SORTABLE 00119

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_REQUIRES_ORDS \
	118, /* /soc/flash-controller@4001e000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_SUPPORTS_ORDS \
	120, /* /soc/flash-controller@4001e000/flash@0/partitions */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_EXISTS 1
#define DT_N_INST_0_soc_nv_flash DT_N_S_soc_S_flash_controller_4001e000_S_flash_0
#define DT_N_NODELABEL_flash0    DT_N_S_soc_S_flash_controller_4001e000_S_flash_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_REG_IDX_0_VAL_SIZE 1048576 /* 0x100000 */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_COMPAT_MATCHES_soc_nv_flash 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_P_wakeup_source 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_P_compatible {"soc-nv-flash"}
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_P_compatible_IDX_0 "soc-nv-flash"
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_P_compatible_IDX_0_STRING_UNQUOTED soc-nv-flash
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_P_compatible_IDX_0_STRING_TOKEN soc_nv_flash
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_P_compatible_IDX_0_STRING_UPPER_TOKEN SOC_NV_FLASH
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0, compatible, 0)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0, compatible, 0)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_P_compatible_LEN 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_P_compatible_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_P_reg {0 /* 0x0 */, 1048576 /* 0x100000 */}
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_P_reg_IDX_0 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_P_reg_IDX_1 1048576
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_P_reg_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_P_erase_block_size 4096
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_P_erase_block_size_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_P_write_block_size 4
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_P_write_block_size_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@4001e000/flash@0/partitions
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions
 *
 * Binding (compatible = fixed-partitions):
 *   $ZEPHYR_BASE/dts/bindings/mtd/fixed-partitions.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_PATH "/soc/flash-controller@4001e000/flash@0/partitions"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_FULL_NAME "partitions"

/* Node parent (/soc/flash-controller@4001e000/flash@0) identifier: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_PARENT DT_N_S_soc_S_flash_controller_4001e000_S_flash_0

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_CHILD_NUM 4
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_CHILD_NUM_STATUS_OKAY 4
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_ORD 120
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_ORD_STR_SORTABLE 00120

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_REQUIRES_ORDS \
	119, /* /soc/flash-controller@4001e000/flash@0 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_SUPPORTS_ORDS \
	121, /* /soc/flash-controller@4001e000/flash@0/partitions/partition@0 */ \
	122, /* /soc/flash-controller@4001e000/flash@0/partitions/partition@c000 */ \
	123, /* /soc/flash-controller@4001e000/flash@0/partitions/partition@82000 */ \
	124, /* /soc/flash-controller@4001e000/flash@0/partitions/partition@f8000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_EXISTS 1
#define DT_N_INST_0_fixed_partitions DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_REG_NUM 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_COMPAT_MATCHES_fixed_partitions 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /soc/flash-controller@4001e000/flash@0/partitions/partition@0
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_PATH "/soc/flash-controller@4001e000/flash@0/partitions/partition@0"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_FULL_NAME "partition@0"

/* Node parent (/soc/flash-controller@4001e000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_PARENT DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_CHILD_NUM 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_ORD 121
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_ORD_STR_SORTABLE 00121

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_REQUIRES_ORDS \
	120, /* /soc/flash-controller@4001e000/flash@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_EXISTS 1
#define DT_N_NODELABEL_boot_partition DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_VAL_SIZE 49152 /* 0xc000 */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_PARTITION_ID 0

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_P_label "mcuboot"
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_P_label_STRING_UNQUOTED mcuboot
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_P_label_STRING_TOKEN mcuboot
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_P_label_STRING_UPPER_TOKEN MCUBOOT
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_P_label_IDX_0 "mcuboot"
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_P_label_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0, label, 0)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0, label, 0)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_P_label_LEN 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_P_label_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_P_read_only 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_P_read_only_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_P_reg {0 /* 0x0 */, 49152 /* 0xc000 */}
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_0 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_1 49152
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@4001e000/flash@0/partitions/partition@c000
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_PATH "/soc/flash-controller@4001e000/flash@0/partitions/partition@c000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_FULL_NAME "partition@c000"

/* Node parent (/soc/flash-controller@4001e000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_PARENT DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_CHILD_IDX 1

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_CHILD_NUM 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_ORD 122
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_ORD_STR_SORTABLE 00122

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_REQUIRES_ORDS \
	120, /* /soc/flash-controller@4001e000/flash@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_EXISTS 1
#define DT_N_NODELABEL_slot0_partition DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_REG_IDX_0_VAL_ADDRESS 49152 /* 0xc000 */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_REG_IDX_0_VAL_SIZE 483328 /* 0x76000 */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_PARTITION_ID 1

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_P_label "image-0"
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_P_label_STRING_UNQUOTED image-0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_P_label_STRING_TOKEN image_0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_P_label_STRING_UPPER_TOKEN IMAGE_0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_P_label_IDX_0 "image-0"
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_P_label_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000, label, 0)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000, label, 0)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_P_label_LEN 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_P_label_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_P_read_only 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_P_reg {49152 /* 0xc000 */, 483328 /* 0x76000 */}
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_P_reg_IDX_0 49152
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_P_reg_IDX_1 483328
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@4001e000/flash@0/partitions/partition@82000
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_PATH "/soc/flash-controller@4001e000/flash@0/partitions/partition@82000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_FULL_NAME "partition@82000"

/* Node parent (/soc/flash-controller@4001e000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_PARENT DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_CHILD_IDX 2

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_CHILD_NUM 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_ORD 123
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_ORD_STR_SORTABLE 00123

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_REQUIRES_ORDS \
	120, /* /soc/flash-controller@4001e000/flash@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_EXISTS 1
#define DT_N_NODELABEL_slot1_partition DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_REG_IDX_0_VAL_ADDRESS 532480 /* 0x82000 */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_REG_IDX_0_VAL_SIZE 483328 /* 0x76000 */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_PARTITION_ID 2

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_P_label "image-1"
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_P_label_STRING_UNQUOTED image-1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_P_label_STRING_TOKEN image_1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_P_label_STRING_UPPER_TOKEN IMAGE_1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_P_label_IDX_0 "image-1"
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_P_label_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000, label, 0)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000, label, 0)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_P_label_LEN 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_P_label_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_P_read_only 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_P_reg {532480 /* 0x82000 */, 483328 /* 0x76000 */}
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_P_reg_IDX_0 532480
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_P_reg_IDX_1 483328
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@4001e000/flash@0/partitions/partition@f8000
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_PATH "/soc/flash-controller@4001e000/flash@0/partitions/partition@f8000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_FULL_NAME "partition@f8000"

/* Node parent (/soc/flash-controller@4001e000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_PARENT DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_CHILD_IDX 3

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_CHILD_NUM 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_ORD 124
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_ORD_STR_SORTABLE 00124

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_REQUIRES_ORDS \
	120, /* /soc/flash-controller@4001e000/flash@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_EXISTS 1
#define DT_N_NODELABEL_storage_partition DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_REG_IDX_0_VAL_ADDRESS 1015808 /* 0xf8000 */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_REG_IDX_0_VAL_SIZE 32768 /* 0x8000 */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_PARTITION_ID 3

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_P_label "storage"
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_P_label_STRING_UNQUOTED storage
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_P_label_STRING_TOKEN storage
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_P_label_STRING_UPPER_TOKEN STORAGE
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_P_label_IDX_0 "storage"
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_P_label_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000, label, 0)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000, label, 0)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_P_label_LEN 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_P_label_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_P_read_only 0
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_P_reg {1015808 /* 0xf8000 */, 32768 /* 0x8000 */}
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_P_reg_IDX_0 1015808
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_P_reg_IDX_1 32768
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/power@40000000
 *
 * Node identifier: DT_N_S_soc_S_power_40000000
 *
 * Binding (compatible = nordic,nrf-power):
 *   $ZEPHYR_BASE/dts/bindings/power/nordic,nrf-power.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_power_40000000_PATH "/soc/power@40000000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_power_40000000_FULL_NAME "power@40000000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_power_40000000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_power_40000000_CHILD_IDX 6

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_power_40000000_CHILD_NUM 2
#define DT_N_S_soc_S_power_40000000_CHILD_NUM_STATUS_OKAY 2
#define DT_N_S_soc_S_power_40000000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c) fn(DT_N_S_soc_S_power_40000000_S_gpregret2_40000520)
#define DT_N_S_soc_S_power_40000000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_power_40000000_S_gpregret2_40000520)
#define DT_N_S_soc_S_power_40000000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c, __VA_ARGS__) fn(DT_N_S_soc_S_power_40000000_S_gpregret2_40000520, __VA_ARGS__)
#define DT_N_S_soc_S_power_40000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_power_40000000_S_gpregret2_40000520, __VA_ARGS__)
#define DT_N_S_soc_S_power_40000000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c) fn(DT_N_S_soc_S_power_40000000_S_gpregret2_40000520)
#define DT_N_S_soc_S_power_40000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_power_40000000_S_gpregret2_40000520)
#define DT_N_S_soc_S_power_40000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c, __VA_ARGS__) fn(DT_N_S_soc_S_power_40000000_S_gpregret2_40000520, __VA_ARGS__)
#define DT_N_S_soc_S_power_40000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_power_40000000_S_gpregret2_40000520, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_power_40000000_ORD 125
#define DT_N_S_soc_S_power_40000000_ORD_STR_SORTABLE 00125

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_power_40000000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_power_40000000_SUPPORTS_ORDS \
	126, /* /soc/power@40000000/gpregret1@4000051c */ \
	127, /* /soc/power@40000000/gpregret2@40000520 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_power_40000000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_power DT_N_S_soc_S_power_40000000
#define DT_N_NODELABEL_power         DT_N_S_soc_S_power_40000000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_power_40000000_REG_NUM 1
#define DT_N_S_soc_S_power_40000000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_power_40000000_REG_IDX_0_VAL_ADDRESS 1073741824 /* 0x40000000 */
#define DT_N_S_soc_S_power_40000000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_power_40000000_RANGES_NUM 0
#define DT_N_S_soc_S_power_40000000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_power_40000000_IRQ_NUM 1
#define DT_N_S_soc_S_power_40000000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_power_40000000_IRQ_IDX_0_VAL_irq 0
#define DT_N_S_soc_S_power_40000000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_power_40000000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_power_40000000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_power_40000000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_power_40000000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_power_40000000_IRQ_LEVEL 1
#define DT_N_S_soc_S_power_40000000_COMPAT_MATCHES_nordic_nrf_power 1
#define DT_N_S_soc_S_power_40000000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_power_40000000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_power_40000000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_power_40000000_COMPAT_MODEL_IDX_0 "nrf-power"
#define DT_N_S_soc_S_power_40000000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_power_40000000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_power_40000000_P_wakeup_source 0
#define DT_N_S_soc_S_power_40000000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_power_40000000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_power_40000000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_power_40000000_P_status "okay"
#define DT_N_S_soc_S_power_40000000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_power_40000000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_power_40000000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_power_40000000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_power_40000000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_power_40000000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_power_40000000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_power_40000000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_power_40000000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_power_40000000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_power_40000000, status, 0)
#define DT_N_S_soc_S_power_40000000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_power_40000000, status, 0)
#define DT_N_S_soc_S_power_40000000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_power_40000000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_power_40000000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_power_40000000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_power_40000000_P_status_LEN 1
#define DT_N_S_soc_S_power_40000000_P_status_EXISTS 1
#define DT_N_S_soc_S_power_40000000_P_compatible {"nordic,nrf-power"}
#define DT_N_S_soc_S_power_40000000_P_compatible_IDX_0 "nordic,nrf-power"
#define DT_N_S_soc_S_power_40000000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-power
#define DT_N_S_soc_S_power_40000000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_power
#define DT_N_S_soc_S_power_40000000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_POWER
#define DT_N_S_soc_S_power_40000000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_power_40000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_power_40000000, compatible, 0)
#define DT_N_S_soc_S_power_40000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_power_40000000, compatible, 0)
#define DT_N_S_soc_S_power_40000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_power_40000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_power_40000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_power_40000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_power_40000000_P_compatible_LEN 1
#define DT_N_S_soc_S_power_40000000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_power_40000000_P_reg {1073741824 /* 0x40000000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_power_40000000_P_reg_IDX_0 1073741824
#define DT_N_S_soc_S_power_40000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_power_40000000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_power_40000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_power_40000000_P_reg_EXISTS 1
#define DT_N_S_soc_S_power_40000000_P_interrupts {0 /* 0x0 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_power_40000000_P_interrupts_IDX_0 0
#define DT_N_S_soc_S_power_40000000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_power_40000000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_power_40000000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_power_40000000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_power_40000000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_power_40000000_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/power@40000000/gpregret1@4000051c
 *
 * Node identifier: DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c
 *
 * Binding (compatible = nordic,nrf-gpregret):
 *   $ZEPHYR_BASE/dts/bindings/retained_mem/nordic,nrf-gpreget.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_PATH "/soc/power@40000000/gpregret1@4000051c"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_FULL_NAME "gpregret1@4000051c"

/* Node parent (/soc/power@40000000) identifier: */
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_PARENT DT_N_S_soc_S_power_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_CHILD_NUM 0
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_ORD 126
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_ORD_STR_SORTABLE 00126

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_REQUIRES_ORDS \
	125, /* /soc/power@40000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_EXISTS 1
#define DT_N_INST_0_nordic_nrf_gpregret DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c
#define DT_N_NODELABEL_gpregret1        DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_REG_NUM 1
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_REG_IDX_0_VAL_ADDRESS 1073743132 /* 0x4000051c */
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_REG_IDX_0_VAL_SIZE 1 /* 0x1 */
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_RANGES_NUM 0
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_IRQ_NUM 0
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_IRQ_LEVEL 0
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_COMPAT_MATCHES_nordic_nrf_gpregret 1
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_COMPAT_MODEL_IDX_0 "nrf-gpregret"
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_wakeup_source 0
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_status "okay"
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c, status, 0)
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c, status, 0)
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_status_LEN 1
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_status_EXISTS 1
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_compatible {"nordic,nrf-gpregret"}
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_compatible_IDX_0 "nordic,nrf-gpregret"
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpregret
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpregret
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPREGRET
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c, compatible, 0)
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c, compatible, 0)
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_compatible_LEN 1
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_compatible_EXISTS 1
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_reg {1073743132 /* 0x4000051c */, 1 /* 0x1 */}
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_reg_IDX_0 1073743132
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_reg_IDX_1 1
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_reg_EXISTS 1
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/power@40000000/gpregret2@40000520
 *
 * Node identifier: DT_N_S_soc_S_power_40000000_S_gpregret2_40000520
 *
 * Binding (compatible = nordic,nrf-gpregret):
 *   $ZEPHYR_BASE/dts/bindings/retained_mem/nordic,nrf-gpreget.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_PATH "/soc/power@40000000/gpregret2@40000520"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_FULL_NAME "gpregret2@40000520"

/* Node parent (/soc/power@40000000) identifier: */
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_PARENT DT_N_S_soc_S_power_40000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_CHILD_IDX 1

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_CHILD_NUM 0
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_ORD 127
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_ORD_STR_SORTABLE 00127

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_REQUIRES_ORDS \
	125, /* /soc/power@40000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_EXISTS 1
#define DT_N_INST_1_nordic_nrf_gpregret DT_N_S_soc_S_power_40000000_S_gpregret2_40000520
#define DT_N_NODELABEL_gpregret2        DT_N_S_soc_S_power_40000000_S_gpregret2_40000520

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_REG_NUM 1
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_REG_IDX_0_VAL_ADDRESS 1073743136 /* 0x40000520 */
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_REG_IDX_0_VAL_SIZE 1 /* 0x1 */
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_RANGES_NUM 0
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_IRQ_NUM 0
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_IRQ_LEVEL 0
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_COMPAT_MATCHES_nordic_nrf_gpregret 1
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_COMPAT_MODEL_IDX_0 "nrf-gpregret"
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_wakeup_source 0
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_status "okay"
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_power_40000000_S_gpregret2_40000520, status, 0)
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_power_40000000_S_gpregret2_40000520, status, 0)
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_power_40000000_S_gpregret2_40000520, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_power_40000000_S_gpregret2_40000520, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_status_LEN 1
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_status_EXISTS 1
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_compatible {"nordic,nrf-gpregret"}
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_compatible_IDX_0 "nordic,nrf-gpregret"
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-gpregret
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_gpregret
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_GPREGRET
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_power_40000000_S_gpregret2_40000520, compatible, 0)
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_power_40000000_S_gpregret2_40000520, compatible, 0)
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_power_40000000_S_gpregret2_40000520, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_power_40000000_S_gpregret2_40000520, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_compatible_LEN 1
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_compatible_EXISTS 1
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_reg {1073743136 /* 0x40000520 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_reg_IDX_0 1073743136
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_reg_IDX_1 1
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_reg_EXISTS 1
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_power_40000000_S_gpregret2_40000520_P_zephyr_deferred_init_EXISTS 1

/*
 * Devicetree node: /soc/qspi@40029000
 *
 * Node identifier: DT_N_S_soc_S_qspi_40029000
 *
 * Binding (compatible = nordic,nrf-qspi):
 *   $ZEPHYR_BASE/dts/bindings/flash_controller/nordic,nrf-qspi.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_qspi_40029000_PATH "/soc/qspi@40029000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_qspi_40029000_FULL_NAME "qspi@40029000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_qspi_40029000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_qspi_40029000_CHILD_IDX 49

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_qspi_40029000_CHILD_NUM 1
#define DT_N_S_soc_S_qspi_40029000_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_soc_S_qspi_40029000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0)
#define DT_N_S_soc_S_qspi_40029000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0)
#define DT_N_S_soc_S_qspi_40029000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, __VA_ARGS__)
#define DT_N_S_soc_S_qspi_40029000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, __VA_ARGS__)
#define DT_N_S_soc_S_qspi_40029000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0)
#define DT_N_S_soc_S_qspi_40029000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0)
#define DT_N_S_soc_S_qspi_40029000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, __VA_ARGS__)
#define DT_N_S_soc_S_qspi_40029000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_qspi_40029000_ORD 128
#define DT_N_S_soc_S_qspi_40029000_ORD_STR_SORTABLE 00128

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_qspi_40029000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */ \
	38, /* /pin-controller/qspi_default */ \
	40, /* /pin-controller/qspi_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_qspi_40029000_SUPPORTS_ORDS \
	129, /* /soc/qspi@40029000/mx25r6435f@0 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_qspi_40029000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_qspi DT_N_S_soc_S_qspi_40029000
#define DT_N_NODELABEL_qspi         DT_N_S_soc_S_qspi_40029000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_qspi_40029000_REG_NUM 2
#define DT_N_S_soc_S_qspi_40029000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_REG_IDX_0_VAL_ADDRESS 1073909760 /* 0x40029000 */
#define DT_N_S_soc_S_qspi_40029000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_qspi_40029000_REG_IDX_1_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_REG_IDX_1_VAL_ADDRESS 301989888 /* 0x12000000 */
#define DT_N_S_soc_S_qspi_40029000_REG_IDX_1_VAL_SIZE 134217728 /* 0x8000000 */
#define DT_N_S_soc_S_qspi_40029000_REG_NAME_qspi_VAL_ADDRESS DT_N_S_soc_S_qspi_40029000_REG_IDX_0_VAL_ADDRESS
#define DT_N_S_soc_S_qspi_40029000_REG_NAME_qspi_VAL_SIZE DT_N_S_soc_S_qspi_40029000_REG_IDX_0_VAL_SIZE
#define DT_N_S_soc_S_qspi_40029000_REG_NAME_qspi_mm_VAL_ADDRESS DT_N_S_soc_S_qspi_40029000_REG_IDX_1_VAL_ADDRESS
#define DT_N_S_soc_S_qspi_40029000_REG_NAME_qspi_mm_VAL_SIZE DT_N_S_soc_S_qspi_40029000_REG_IDX_1_VAL_SIZE
#define DT_N_S_soc_S_qspi_40029000_RANGES_NUM 0
#define DT_N_S_soc_S_qspi_40029000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_qspi_40029000_IRQ_NUM 1
#define DT_N_S_soc_S_qspi_40029000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_IRQ_IDX_0_VAL_irq 41
#define DT_N_S_soc_S_qspi_40029000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_qspi_40029000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_qspi_40029000_IRQ_LEVEL 1
#define DT_N_S_soc_S_qspi_40029000_COMPAT_MATCHES_nordic_nrf_qspi 1
#define DT_N_S_soc_S_qspi_40029000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_qspi_40029000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_COMPAT_MODEL_IDX_0 "nrf-qspi"
#define DT_N_S_soc_S_qspi_40029000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_qspi_40029000_PINCTRL_NUM 2
#define DT_N_S_soc_S_qspi_40029000_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_qspi_40029000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_qspi_40029000_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_qspi_40029000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_qspi_default
#define DT_N_S_soc_S_qspi_40029000_PINCTRL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_PINCTRL_IDX_1_TOKEN sleep
#define DT_N_S_soc_S_qspi_40029000_PINCTRL_IDX_1_UPPER_TOKEN SLEEP
#define DT_N_S_soc_S_qspi_40029000_PINCTRL_NAME_sleep_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_PINCTRL_NAME_sleep_IDX 1
#define DT_N_S_soc_S_qspi_40029000_PINCTRL_NAME_sleep_IDX_0_PH DT_N_S_pin_controller_S_qspi_sleep

/* Generic property macros: */
#define DT_N_S_soc_S_qspi_40029000_P_wakeup_source 0
#define DT_N_S_soc_S_qspi_40029000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_qspi_40029000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_P_status "okay"
#define DT_N_S_soc_S_qspi_40029000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_qspi_40029000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_qspi_40029000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_qspi_40029000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_qspi_40029000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_qspi_40029000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_qspi_40029000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_qspi_40029000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_qspi_40029000, status, 0)
#define DT_N_S_soc_S_qspi_40029000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_qspi_40029000, status, 0)
#define DT_N_S_soc_S_qspi_40029000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_qspi_40029000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_qspi_40029000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_qspi_40029000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_qspi_40029000_P_status_LEN 1
#define DT_N_S_soc_S_qspi_40029000_P_status_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_P_compatible {"nordic,nrf-qspi"}
#define DT_N_S_soc_S_qspi_40029000_P_compatible_IDX_0 "nordic,nrf-qspi"
#define DT_N_S_soc_S_qspi_40029000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-qspi
#define DT_N_S_soc_S_qspi_40029000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_qspi
#define DT_N_S_soc_S_qspi_40029000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_QSPI
#define DT_N_S_soc_S_qspi_40029000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_qspi_40029000, compatible, 0)
#define DT_N_S_soc_S_qspi_40029000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_qspi_40029000, compatible, 0)
#define DT_N_S_soc_S_qspi_40029000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_qspi_40029000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_qspi_40029000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_qspi_40029000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_qspi_40029000_P_compatible_LEN 1
#define DT_N_S_soc_S_qspi_40029000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_P_reg {1073909760 /* 0x40029000 */, 4096 /* 0x1000 */, 301989888 /* 0x12000000 */, 134217728 /* 0x8000000 */}
#define DT_N_S_soc_S_qspi_40029000_P_reg_IDX_0 1073909760
#define DT_N_S_soc_S_qspi_40029000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_qspi_40029000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_P_reg_IDX_2 301989888
#define DT_N_S_soc_S_qspi_40029000_P_reg_IDX_2_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_P_reg_IDX_3 134217728
#define DT_N_S_soc_S_qspi_40029000_P_reg_IDX_3_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_P_reg_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_P_reg_names {"qspi", "qspi_mm"}
#define DT_N_S_soc_S_qspi_40029000_P_reg_names_IDX_0 "qspi"
#define DT_N_S_soc_S_qspi_40029000_P_reg_names_IDX_0_STRING_UNQUOTED qspi
#define DT_N_S_soc_S_qspi_40029000_P_reg_names_IDX_0_STRING_TOKEN qspi
#define DT_N_S_soc_S_qspi_40029000_P_reg_names_IDX_0_STRING_UPPER_TOKEN QSPI
#define DT_N_S_soc_S_qspi_40029000_P_reg_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_P_reg_names_IDX_1 "qspi_mm"
#define DT_N_S_soc_S_qspi_40029000_P_reg_names_IDX_1_STRING_UNQUOTED qspi_mm
#define DT_N_S_soc_S_qspi_40029000_P_reg_names_IDX_1_STRING_TOKEN qspi_mm
#define DT_N_S_soc_S_qspi_40029000_P_reg_names_IDX_1_STRING_UPPER_TOKEN QSPI_MM
#define DT_N_S_soc_S_qspi_40029000_P_reg_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_qspi_40029000, reg_names, 0) \
	fn(DT_N_S_soc_S_qspi_40029000, reg_names, 1)
#define DT_N_S_soc_S_qspi_40029000_P_reg_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_qspi_40029000, reg_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000, reg_names, 1)
#define DT_N_S_soc_S_qspi_40029000_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_qspi_40029000, reg_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000, reg_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_qspi_40029000_P_reg_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_qspi_40029000, reg_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000, reg_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_qspi_40029000_P_reg_names_LEN 2
#define DT_N_S_soc_S_qspi_40029000_P_reg_names_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_P_interrupts {41 /* 0x29 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_qspi_40029000_P_interrupts_IDX_0 41
#define DT_N_S_soc_S_qspi_40029000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_qspi_40029000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_qspi_40029000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_qspi_default
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_qspi_default
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_qspi_40029000, pinctrl_0, 0)
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_qspi_40029000, pinctrl_0, 0)
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_qspi_40029000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_qspi_40029000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_0_LEN 1
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_1_IDX_0 DT_N_S_pin_controller_S_qspi_sleep
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_1_IDX_0_PH DT_N_S_pin_controller_S_qspi_sleep
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_1_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_1_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_qspi_40029000, pinctrl_1, 0)
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_qspi_40029000, pinctrl_1, 0)
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_qspi_40029000, pinctrl_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_1_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_qspi_40029000, pinctrl_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_1_LEN 1
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_1_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_names {"default", "sleep"}
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_names_IDX_1 "sleep"
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_names_IDX_1_STRING_UNQUOTED sleep
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_names_IDX_1_STRING_TOKEN sleep
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_names_IDX_1_STRING_UPPER_TOKEN SLEEP
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_qspi_40029000, pinctrl_names, 0) \
	fn(DT_N_S_soc_S_qspi_40029000, pinctrl_names, 1)
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_qspi_40029000, pinctrl_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000, pinctrl_names, 1)
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_qspi_40029000, pinctrl_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000, pinctrl_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_qspi_40029000, pinctrl_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000, pinctrl_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_names_LEN 2
#define DT_N_S_soc_S_qspi_40029000_P_pinctrl_names_EXISTS 1

/*
 * Devicetree node: /soc/qspi@40029000/mx25r6435f@0
 *
 * Node identifier: DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0
 *
 * Binding (compatible = nordic,qspi-nor):
 *   $ZEPHYR_BASE/dts/bindings/mtd/nordic,qspi-nor.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_PATH "/soc/qspi@40029000/mx25r6435f@0"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_FULL_NAME "mx25r6435f@0"

/* Node parent (/soc/qspi@40029000) identifier: */
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_PARENT DT_N_S_soc_S_qspi_40029000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_CHILD_NUM 0
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_ORD 129
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_ORD_STR_SORTABLE 00129

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_REQUIRES_ORDS \
	128, /* /soc/qspi@40029000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_EXISTS 1
#define DT_N_ALIAS_spi_flash0       DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0
#define DT_N_INST_0_nordic_qspi_nor DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0
#define DT_N_NODELABEL_mx25r64      DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0

/* Bus info (controller: '/soc/qspi@40029000', type: '['qspi']') */
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_BUS_qspi 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_BUS DT_N_S_soc_S_qspi_40029000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_REG_NUM 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_RANGES_NUM 0
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_IRQ_NUM 0
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_IRQ_LEVEL 0
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_COMPAT_MATCHES_nordic_qspi_nor 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_COMPAT_MODEL_IDX_0 "qspi-nor"
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_wakeup_source 0
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_compatible {"nordic,qspi-nor"}
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_compatible_IDX_0 "nordic,qspi-nor"
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_compatible_IDX_0_STRING_UNQUOTED nordic,qspi-nor
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_compatible_IDX_0_STRING_TOKEN nordic_qspi_nor
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_QSPI_NOR
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, compatible, 0)
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, compatible, 0)
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_compatible_LEN 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_compatible_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_reg {0 /* 0x0 */}
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_reg_IDX_0 0
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_reg_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_jedec_id {194 /* 0xc2 */, 40 /* 0x28 */, 23 /* 0x17 */}
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_jedec_id_IDX_0 194
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_jedec_id_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_jedec_id_IDX_1 40
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_jedec_id_IDX_1_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_jedec_id_IDX_2 23
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_jedec_id_IDX_2_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_jedec_id_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, jedec_id, 0) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, jedec_id, 1) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, jedec_id, 2)
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_jedec_id_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, jedec_id, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, jedec_id, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, jedec_id, 2)
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_jedec_id_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, jedec_id, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, jedec_id, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, jedec_id, 2, __VA_ARGS__)
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_jedec_id_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, jedec_id, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, jedec_id, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, jedec_id, 2, __VA_ARGS__)
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_jedec_id_LEN 3
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_jedec_id_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_size 67108864
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_size_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp {229 /* 0xe5 */, 32 /* 0x20 */, 241 /* 0xf1 */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 3 /* 0x3 */, 68 /* 0x44 */, 235 /* 0xeb */, 8 /* 0x8 */, 107 /* 0x6b */, 8 /* 0x8 */, 59 /* 0x3b */, 4 /* 0x4 */, 187 /* 0xbb */, 238 /* 0xee */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 0 /* 0x0 */, 255 /* 0xff */, 255 /* 0xff */, 255 /* 0xff */, 0 /* 0x0 */, 255 /* 0xff */, 12 /* 0xc */, 32 /* 0x20 */, 15 /* 0xf */, 82 /* 0x52 */, 16 /* 0x10 */, 216 /* 0xd8 */, 0 /* 0x0 */, 255 /* 0xff */, 35 /* 0x23 */, 114 /* 0x72 */, 245 /* 0xf5 */, 0 /* 0x0 */, 130 /* 0x82 */, 237 /* 0xed */, 4 /* 0x4 */, 204 /* 0xcc */, 68 /* 0x44 */, 131 /* 0x83 */, 104 /* 0x68 */, 68 /* 0x44 */, 48 /* 0x30 */, 176 /* 0xb0 */, 48 /* 0x30 */, 176 /* 0xb0 */, 247 /* 0xf7 */, 196 /* 0xc4 */, 213 /* 0xd5 */, 92 /* 0x5c */, 0 /* 0x0 */, 190 /* 0xbe */, 41 /* 0x29 */, 255 /* 0xff */, 240 /* 0xf0 */, 208 /* 0xd0 */, 255 /* 0xff */, 255 /* 0xff */}
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_0 229
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_1 32
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_1_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_2 241
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_2_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_3 255
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_3_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_4 255
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_4_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_5 255
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_5_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_6 255
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_6_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_7 3
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_7_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_8 68
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_8_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_9 235
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_9_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_10 8
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_10_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_11 107
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_11_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_12 8
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_12_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_13 59
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_13_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_14 4
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_14_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_15 187
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_15_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_16 238
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_16_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_17 255
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_17_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_18 255
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_18_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_19 255
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_19_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_20 255
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_20_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_21 255
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_21_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_22 0
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_22_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_23 255
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_23_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_24 255
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_24_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_25 255
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_25_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_26 0
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_26_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_27 255
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_27_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_28 12
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_28_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_29 32
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_29_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_30 15
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_30_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_31 82
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_31_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_32 16
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_32_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_33 216
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_33_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_34 0
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_34_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_35 255
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_35_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_36 35
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_36_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_37 114
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_37_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_38 245
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_38_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_39 0
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_39_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_40 130
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_40_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_41 237
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_41_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_42 4
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_42_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_43 204
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_43_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_44 68
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_44_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_45 131
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_45_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_46 104
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_46_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_47 68
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_47_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_48 48
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_48_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_49 176
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_49_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_50 48
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_50_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_51 176
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_51_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_52 247
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_52_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_53 196
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_53_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_54 213
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_54_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_55 92
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_55_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_56 0
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_56_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_57 190
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_57_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_58 41
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_58_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_59 255
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_59_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_60 240
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_60_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_61 208
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_61_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_62 255
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_62_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_63 255
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_IDX_63_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 0) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 1) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 2) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 3) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 4) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 5) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 6) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 7) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 8) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 9) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 10) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 11) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 12) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 13) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 14) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 15) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 16) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 17) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 18) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 19) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 20) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 21) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 22) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 23) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 24) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 25) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 26) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 27) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 28) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 29) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 30) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 31) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 32) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 33) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 34) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 35) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 36) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 37) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 38) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 39) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 40) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 41) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 42) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 43) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 44) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 45) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 46) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 47) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 48) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 49) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 50) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 51) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 52) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 53) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 54) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 55) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 56) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 57) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 58) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 59) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 60) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 61) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 62) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 63)
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 7) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 8) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 9) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 10) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 11) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 12) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 13) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 14) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 15) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 16) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 17) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 18) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 19) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 20) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 21) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 22) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 23) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 24) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 25) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 26) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 27) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 28) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 29) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 30) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 31) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 32) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 33) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 34) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 35) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 36) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 37) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 38) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 39) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 40) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 41) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 42) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 43) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 44) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 45) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 46) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 47) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 48) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 49) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 50) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 51) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 52) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 53) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 54) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 55) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 56) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 57) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 58) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 59) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 60) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 61) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 62) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 63)
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 1, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 2, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 3, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 4, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 5, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 6, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 7, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 8, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 9, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 10, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 11, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 12, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 13, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 14, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 15, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 16, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 17, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 18, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 19, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 20, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 21, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 22, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 23, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 24, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 25, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 26, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 27, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 28, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 29, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 30, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 31, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 32, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 33, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 34, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 35, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 36, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 37, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 38, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 39, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 40, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 41, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 42, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 43, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 44, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 45, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 46, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 47, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 48, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 49, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 50, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 51, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 52, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 53, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 54, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 55, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 56, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 57, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 58, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 59, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 60, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 61, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 62, __VA_ARGS__) \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 63, __VA_ARGS__)
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 10, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 11, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 12, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 13, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 14, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 15, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 16, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 17, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 18, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 19, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 20, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 21, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 22, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 23, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 24, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 25, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 26, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 27, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 28, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 29, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 30, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 31, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 32, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 33, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 34, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 35, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 36, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 37, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 38, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 39, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 40, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 41, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 42, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 43, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 44, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 45, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 46, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 47, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 48, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 49, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 50, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 51, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 52, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 53, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 54, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 55, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 56, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 57, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 58, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 59, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 60, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 61, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 62, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, sfdp_bfp, 63, __VA_ARGS__)
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_LEN 64
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sfdp_bfp_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_quad_enable_requirements "S1B6"
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_quad_enable_requirements_STRING_UNQUOTED S1B6
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_quad_enable_requirements_STRING_TOKEN S1B6
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_quad_enable_requirements_STRING_UPPER_TOKEN S1B6
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_quad_enable_requirements_IDX_0 "S1B6"
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_quad_enable_requirements_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_quad_enable_requirements_ENUM_IDX 2
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_quad_enable_requirements_ENUM_VAL_S1B6_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_quad_enable_requirements_ENUM_TOKEN S1B6
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_quad_enable_requirements_ENUM_UPPER_TOKEN S1B6
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_quad_enable_requirements_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, quad_enable_requirements, 0)
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_quad_enable_requirements_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, quad_enable_requirements, 0)
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_quad_enable_requirements_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, quad_enable_requirements, 0, __VA_ARGS__)
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_quad_enable_requirements_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, quad_enable_requirements, 0, __VA_ARGS__)
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_quad_enable_requirements_LEN 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_quad_enable_requirements_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_requires_ulbpr 0
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_requires_ulbpr_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_has_dpd 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_has_dpd_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_t_enter_dpd 10000
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_t_enter_dpd_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_t_exit_dpd 35000
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_t_exit_dpd_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_readoc "read4io"
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_readoc_STRING_UNQUOTED read4io
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_readoc_STRING_TOKEN read4io
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_readoc_STRING_UPPER_TOKEN READ4IO
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_readoc_IDX_0 "read4io"
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_readoc_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_readoc_ENUM_IDX 4
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_readoc_ENUM_VAL_read4io_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_readoc_ENUM_TOKEN read4io
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_readoc_ENUM_UPPER_TOKEN READ4IO
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_readoc_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, readoc, 0)
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_readoc_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, readoc, 0)
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_readoc_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, readoc, 0, __VA_ARGS__)
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_readoc_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, readoc, 0, __VA_ARGS__)
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_readoc_LEN 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_readoc_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_writeoc "pp4io"
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_writeoc_STRING_UNQUOTED pp4io
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_writeoc_STRING_TOKEN pp4io
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_writeoc_STRING_UPPER_TOKEN PP4IO
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_writeoc_IDX_0 "pp4io"
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_writeoc_IDX_0_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_writeoc_ENUM_IDX 3
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_writeoc_ENUM_VAL_pp4io_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_writeoc_ENUM_TOKEN pp4io
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_writeoc_ENUM_UPPER_TOKEN PP4IO
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_writeoc_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, writeoc, 0)
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_writeoc_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, writeoc, 0)
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_writeoc_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, writeoc, 0, __VA_ARGS__)
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_writeoc_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, writeoc, 0, __VA_ARGS__)
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_writeoc_LEN 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_writeoc_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_address_size_32 0
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_address_size_32_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_ppsize_512 0
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_ppsize_512_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sck_delay 0
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sck_delay_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_cpha 0
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_cpha_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_cpol 0
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_cpol_EXISTS 1
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sck_frequency 8000000
#define DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0_P_sck_frequency_EXISTS 1

/*
 * Devicetree node: /soc/radio@40001000
 *
 * Node identifier: DT_N_S_soc_S_radio_40001000
 *
 * Binding (compatible = nordic,nrf-radio):
 *   $ZEPHYR_BASE/dts/bindings/net/wireless/nordic,nrf-radio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_radio_40001000_PATH "/soc/radio@40001000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_radio_40001000_FULL_NAME "radio@40001000"

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_radio_40001000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_radio_40001000_CHILD_IDX 7

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_radio_40001000_CHILD_NUM 1
#define DT_N_S_soc_S_radio_40001000_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_soc_S_radio_40001000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_radio_40001000_S_ieee802154)
#define DT_N_S_soc_S_radio_40001000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_radio_40001000_S_ieee802154)
#define DT_N_S_soc_S_radio_40001000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_radio_40001000_S_ieee802154, __VA_ARGS__)
#define DT_N_S_soc_S_radio_40001000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_radio_40001000_S_ieee802154, __VA_ARGS__)
#define DT_N_S_soc_S_radio_40001000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_radio_40001000_S_ieee802154)
#define DT_N_S_soc_S_radio_40001000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_radio_40001000_S_ieee802154)
#define DT_N_S_soc_S_radio_40001000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_radio_40001000_S_ieee802154, __VA_ARGS__)
#define DT_N_S_soc_S_radio_40001000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_radio_40001000_S_ieee802154, __VA_ARGS__)

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_radio_40001000_ORD 130
#define DT_N_S_soc_S_radio_40001000_ORD_STR_SORTABLE 00130

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_radio_40001000_REQUIRES_ORDS \
	6, /* /soc */ \
	7, /* /soc/interrupt-controller@e000e100 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_radio_40001000_SUPPORTS_ORDS \
	131, /* /soc/radio@40001000/ieee802154 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_radio_40001000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_radio DT_N_S_soc_S_radio_40001000
#define DT_N_NODELABEL_radio         DT_N_S_soc_S_radio_40001000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_radio_40001000_REG_NUM 1
#define DT_N_S_soc_S_radio_40001000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_REG_IDX_0_VAL_ADDRESS 1073745920 /* 0x40001000 */
#define DT_N_S_soc_S_radio_40001000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_radio_40001000_RANGES_NUM 0
#define DT_N_S_soc_S_radio_40001000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_radio_40001000_IRQ_NUM 1
#define DT_N_S_soc_S_radio_40001000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_IRQ_IDX_0_VAL_irq 1
#define DT_N_S_soc_S_radio_40001000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_radio_40001000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_S_soc_S_radio_40001000_IRQ_LEVEL 1
#define DT_N_S_soc_S_radio_40001000_COMPAT_MATCHES_nordic_nrf_radio 1
#define DT_N_S_soc_S_radio_40001000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_radio_40001000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_COMPAT_MODEL_IDX_0 "nrf-radio"
#define DT_N_S_soc_S_radio_40001000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_radio_40001000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_radio_40001000_P_wakeup_source 0
#define DT_N_S_soc_S_radio_40001000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_radio_40001000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_P_status "okay"
#define DT_N_S_soc_S_radio_40001000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_radio_40001000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_radio_40001000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_radio_40001000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_radio_40001000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_radio_40001000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_radio_40001000_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_radio_40001000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_radio_40001000, status, 0)
#define DT_N_S_soc_S_radio_40001000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_radio_40001000, status, 0)
#define DT_N_S_soc_S_radio_40001000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_radio_40001000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_radio_40001000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_radio_40001000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_radio_40001000_P_status_LEN 1
#define DT_N_S_soc_S_radio_40001000_P_status_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_P_compatible {"nordic,nrf-radio"}
#define DT_N_S_soc_S_radio_40001000_P_compatible_IDX_0 "nordic,nrf-radio"
#define DT_N_S_soc_S_radio_40001000_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-radio
#define DT_N_S_soc_S_radio_40001000_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_radio
#define DT_N_S_soc_S_radio_40001000_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_RADIO
#define DT_N_S_soc_S_radio_40001000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_radio_40001000, compatible, 0)
#define DT_N_S_soc_S_radio_40001000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_radio_40001000, compatible, 0)
#define DT_N_S_soc_S_radio_40001000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_radio_40001000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_radio_40001000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_radio_40001000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_radio_40001000_P_compatible_LEN 1
#define DT_N_S_soc_S_radio_40001000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_P_reg {1073745920 /* 0x40001000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_radio_40001000_P_reg_IDX_0 1073745920
#define DT_N_S_soc_S_radio_40001000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_radio_40001000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_P_reg_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_P_interrupts {1 /* 0x1 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_radio_40001000_P_interrupts_IDX_0 1
#define DT_N_S_soc_S_radio_40001000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_radio_40001000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_radio_40001000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_P_dfe_supported 0
#define DT_N_S_soc_S_radio_40001000_P_dfe_supported_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_P_ieee802154_supported 1
#define DT_N_S_soc_S_radio_40001000_P_ieee802154_supported_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_P_ble_2mbps_supported 1
#define DT_N_S_soc_S_radio_40001000_P_ble_2mbps_supported_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_P_ble_coded_phy_supported 1
#define DT_N_S_soc_S_radio_40001000_P_ble_coded_phy_supported_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_P_tx_high_power_supported 1
#define DT_N_S_soc_S_radio_40001000_P_tx_high_power_supported_EXISTS 1

/*
 * Devicetree node: /soc/radio@40001000/ieee802154
 *
 * Node identifier: DT_N_S_soc_S_radio_40001000_S_ieee802154
 *
 * Binding (compatible = nordic,nrf-ieee802154):
 *   $ZEPHYR_BASE/dts/bindings/ieee802154/nordic,nrf-ieee802154.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_PATH "/soc/radio@40001000/ieee802154"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_FULL_NAME "ieee802154"

/* Node parent (/soc/radio@40001000) identifier: */
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_PARENT DT_N_S_soc_S_radio_40001000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_CHILD_IDX 0

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_CHILD_NUM 0
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_ORD 131
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_ORD_STR_SORTABLE 00131

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_REQUIRES_ORDS \
	130, /* /soc/radio@40001000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_EXISTS 1
#define DT_N_INST_0_nordic_nrf_ieee802154 DT_N_S_soc_S_radio_40001000_S_ieee802154
#define DT_N_NODELABEL_ieee802154         DT_N_S_soc_S_radio_40001000_S_ieee802154

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_REG_NUM 0
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_RANGES_NUM 0
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_IRQ_NUM 0
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_IRQ_LEVEL 0
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_COMPAT_MATCHES_nordic_nrf_ieee802154 1
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_COMPAT_VENDOR_IDX_0 "Nordic Semiconductor"
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_COMPAT_MODEL_IDX_0 "nrf-ieee802154"
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_wakeup_source 0
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_status "okay"
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_status_ENUM_TOKEN okay
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_status_ENUM_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_radio_40001000_S_ieee802154, status, 0)
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_radio_40001000_S_ieee802154, status, 0)
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_radio_40001000_S_ieee802154, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_radio_40001000_S_ieee802154, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_status_LEN 1
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_status_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_compatible {"nordic,nrf-ieee802154"}
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_compatible_IDX_0 "nordic,nrf-ieee802154"
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_compatible_IDX_0_STRING_UNQUOTED nordic,nrf-ieee802154
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_compatible_IDX_0_STRING_TOKEN nordic_nrf_ieee802154
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_compatible_IDX_0_STRING_UPPER_TOKEN NORDIC_NRF_IEEE802154
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_radio_40001000_S_ieee802154, compatible, 0)
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_radio_40001000_S_ieee802154, compatible, 0)
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_radio_40001000_S_ieee802154, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_radio_40001000_S_ieee802154, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_compatible_LEN 1
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_compatible_EXISTS 1
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_radio_40001000_S_ieee802154_P_zephyr_deferred_init_EXISTS 1

/*
 * Chosen nodes
 */
#define DT_CHOSEN_zephyr_entropy                 DT_N_S_soc_S_crypto_5002a000
#define DT_CHOSEN_zephyr_entropy_EXISTS          1
#define DT_CHOSEN_zephyr_flash_controller        DT_N_S_soc_S_flash_controller_4001e000
#define DT_CHOSEN_zephyr_flash_controller_EXISTS 1
#define DT_CHOSEN_zephyr_console                 DT_N_S_soc_S_uart_40002000
#define DT_CHOSEN_zephyr_console_EXISTS          1
#define DT_CHOSEN_zephyr_shell_uart              DT_N_S_soc_S_uart_40002000
#define DT_CHOSEN_zephyr_shell_uart_EXISTS       1
#define DT_CHOSEN_zephyr_uart_mcumgr             DT_N_S_soc_S_uart_40002000
#define DT_CHOSEN_zephyr_uart_mcumgr_EXISTS      1
#define DT_CHOSEN_zephyr_bt_mon_uart             DT_N_S_soc_S_uart_40002000
#define DT_CHOSEN_zephyr_bt_mon_uart_EXISTS      1
#define DT_CHOSEN_zephyr_bt_c2h_uart             DT_N_S_soc_S_uart_40002000
#define DT_CHOSEN_zephyr_bt_c2h_uart_EXISTS      1
#define DT_CHOSEN_zephyr_sram                    DT_N_S_soc_S_memory_20000000
#define DT_CHOSEN_zephyr_sram_EXISTS             1
#define DT_CHOSEN_zephyr_flash                   DT_N_S_soc_S_flash_controller_4001e000_S_flash_0
#define DT_CHOSEN_zephyr_flash_EXISTS            1
#define DT_CHOSEN_zephyr_code_partition          DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000
#define DT_CHOSEN_zephyr_code_partition_EXISTS   1
#define DT_CHOSEN_zephyr_ieee802154              DT_N_S_soc_S_radio_40001000_S_ieee802154
#define DT_CHOSEN_zephyr_ieee802154_EXISTS       1

/* Macros for iterating over all nodes and enabled nodes */
#define DT_FOREACH_HELPER(fn) fn(DT_N) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_ficr_10000000) fn(DT_N_S_soc_S_uicr_10001000) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_clock_40000000) fn(DT_N_S_soc_S_power_40000000) fn(DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c) fn(DT_N_S_soc_S_power_40000000_S_gpregret2_40000520) fn(DT_N_S_soc_S_radio_40001000) fn(DT_N_S_soc_S_radio_40001000_S_ieee802154) fn(DT_N_S_soc_S_uart_40002000) fn(DT_N_S_soc_S_i2c_40003000) fn(DT_N_S_soc_S_spi_40003000) fn(DT_N_S_soc_S_i2c_40004000) fn(DT_N_S_soc_S_spi_40004000) fn(DT_N_S_soc_S_nfct_40005000) fn(DT_N_S_soc_S_gpiote_40006000) fn(DT_N_S_soc_S_adc_40007000) fn(DT_N_S_soc_S_timer_40008000) fn(DT_N_S_soc_S_timer_40009000) fn(DT_N_S_soc_S_timer_4000a000) fn(DT_N_S_soc_S_rtc_4000b000) fn(DT_N_S_soc_S_temp_4000c000) fn(DT_N_S_soc_S_random_4000d000) fn(DT_N_S_soc_S_ecb_4000e000) fn(DT_N_S_soc_S_ccm_4000f000) fn(DT_N_S_soc_S_watchdog_40010000) fn(DT_N_S_soc_S_rtc_40011000) fn(DT_N_S_soc_S_qdec_40012000) fn(DT_N_S_soc_S_comparator_40013000) fn(DT_N_S_soc_S_egu_40014000) fn(DT_N_S_soc_S_egu_40015000) fn(DT_N_S_soc_S_egu_40016000) fn(DT_N_S_soc_S_egu_40017000) fn(DT_N_S_soc_S_egu_40018000) fn(DT_N_S_soc_S_egu_40019000) fn(DT_N_S_soc_S_timer_4001a000) fn(DT_N_S_soc_S_timer_4001b000) fn(DT_N_S_soc_S_pwm_4001c000) fn(DT_N_S_soc_S_pdm_4001d000) fn(DT_N_S_soc_S_acl_4001e000) fn(DT_N_S_soc_S_flash_controller_4001e000) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000) fn(DT_N_S_soc_S_ppi_4001f000) fn(DT_N_S_soc_S_mwu_40020000) fn(DT_N_S_soc_S_pwm_40021000) fn(DT_N_S_soc_S_pwm_40022000) fn(DT_N_S_soc_S_spi_40023000) fn(DT_N_S_soc_S_rtc_40024000) fn(DT_N_S_soc_S_i2s_40025000) fn(DT_N_S_soc_S_usbd_40027000) fn(DT_N_S_soc_S_uart_40028000) fn(DT_N_S_soc_S_qspi_40029000) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0) fn(DT_N_S_soc_S_pwm_4002d000) fn(DT_N_S_soc_S_spi_4002f000) fn(DT_N_S_soc_S_gpio_50000000) fn(DT_N_S_soc_S_gpio_50000300) fn(DT_N_S_soc_S_crypto_5002a000) fn(DT_N_S_pin_controller) fn(DT_N_S_pin_controller_S_uart0_default) fn(DT_N_S_pin_controller_S_uart0_default_S_group1) fn(DT_N_S_pin_controller_S_uart0_default_S_group2) fn(DT_N_S_pin_controller_S_uart0_sleep) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1) fn(DT_N_S_pin_controller_S_uart1_default) fn(DT_N_S_pin_controller_S_uart1_default_S_group1) fn(DT_N_S_pin_controller_S_uart1_default_S_group2) fn(DT_N_S_pin_controller_S_uart1_sleep) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1) fn(DT_N_S_pin_controller_S_i2c0_default) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1) fn(DT_N_S_pin_controller_S_i2c0_sleep) fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1) fn(DT_N_S_pin_controller_S_i2c1_default) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1) fn(DT_N_S_pin_controller_S_i2c1_sleep) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1) fn(DT_N_S_pin_controller_S_pwm0_default) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1) fn(DT_N_S_pin_controller_S_pwm0_sleep) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1) fn(DT_N_S_pin_controller_S_spi0_default) fn(DT_N_S_pin_controller_S_spi0_default_S_group1) fn(DT_N_S_pin_controller_S_spi0_sleep) fn(DT_N_S_pin_controller_S_spi0_sleep_S_group1) fn(DT_N_S_pin_controller_S_spi1_default) fn(DT_N_S_pin_controller_S_spi1_default_S_group1) fn(DT_N_S_pin_controller_S_spi1_sleep) fn(DT_N_S_pin_controller_S_spi1_sleep_S_group1) fn(DT_N_S_pin_controller_S_spi2_default) fn(DT_N_S_pin_controller_S_spi2_default_S_group1) fn(DT_N_S_pin_controller_S_spi2_sleep) fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1) fn(DT_N_S_pin_controller_S_qspi_default) fn(DT_N_S_pin_controller_S_qspi_default_S_group1) fn(DT_N_S_pin_controller_S_qspi_sleep) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2) fn(DT_N_S_pin_controller_S_spi3_default) fn(DT_N_S_pin_controller_S_spi3_default_S_group1) fn(DT_N_S_pin_controller_S_spi3_sleep) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1) fn(DT_N_S_entropy_bt_hci) fn(DT_N_S_sw_pwm) fn(DT_N_S_cpus) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000) fn(DT_N_S_leds) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_leds_S_led_3) fn(DT_N_S_pwmleds) fn(DT_N_S_pwmleds_S_pwm_led_0) fn(DT_N_S_buttons) fn(DT_N_S_buttons_S_button_0) fn(DT_N_S_buttons_S_button_1) fn(DT_N_S_buttons_S_button_2) fn(DT_N_S_buttons_S_button_3) fn(DT_N_S_connector) fn(DT_N_S_analog_connector)
#define DT_FOREACH_OKAY_HELPER(fn) fn(DT_N) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_ficr_10000000) fn(DT_N_S_soc_S_uicr_10001000) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_clock_40000000) fn(DT_N_S_soc_S_power_40000000) fn(DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c) fn(DT_N_S_soc_S_power_40000000_S_gpregret2_40000520) fn(DT_N_S_soc_S_radio_40001000) fn(DT_N_S_soc_S_radio_40001000_S_ieee802154) fn(DT_N_S_soc_S_uart_40002000) fn(DT_N_S_soc_S_i2c_40003000) fn(DT_N_S_soc_S_spi_40004000) fn(DT_N_S_soc_S_gpiote_40006000) fn(DT_N_S_soc_S_adc_40007000) fn(DT_N_S_soc_S_temp_4000c000) fn(DT_N_S_soc_S_random_4000d000) fn(DT_N_S_soc_S_ecb_4000e000) fn(DT_N_S_soc_S_ccm_4000f000) fn(DT_N_S_soc_S_watchdog_40010000) fn(DT_N_S_soc_S_egu_40014000) fn(DT_N_S_soc_S_egu_40015000) fn(DT_N_S_soc_S_egu_40016000) fn(DT_N_S_soc_S_egu_40017000) fn(DT_N_S_soc_S_egu_40018000) fn(DT_N_S_soc_S_egu_40019000) fn(DT_N_S_soc_S_pwm_4001c000) fn(DT_N_S_soc_S_acl_4001e000) fn(DT_N_S_soc_S_flash_controller_4001e000) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000) fn(DT_N_S_soc_S_ppi_4001f000) fn(DT_N_S_soc_S_mwu_40020000) fn(DT_N_S_soc_S_usbd_40027000) fn(DT_N_S_soc_S_qspi_40029000) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0) fn(DT_N_S_soc_S_spi_4002f000) fn(DT_N_S_soc_S_gpio_50000000) fn(DT_N_S_soc_S_gpio_50000300) fn(DT_N_S_soc_S_crypto_5002a000) fn(DT_N_S_pin_controller) fn(DT_N_S_pin_controller_S_uart0_default) fn(DT_N_S_pin_controller_S_uart0_default_S_group1) fn(DT_N_S_pin_controller_S_uart0_default_S_group2) fn(DT_N_S_pin_controller_S_uart0_sleep) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1) fn(DT_N_S_pin_controller_S_uart1_default) fn(DT_N_S_pin_controller_S_uart1_default_S_group1) fn(DT_N_S_pin_controller_S_uart1_default_S_group2) fn(DT_N_S_pin_controller_S_uart1_sleep) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1) fn(DT_N_S_pin_controller_S_i2c0_default) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1) fn(DT_N_S_pin_controller_S_i2c0_sleep) fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1) fn(DT_N_S_pin_controller_S_i2c1_default) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1) fn(DT_N_S_pin_controller_S_i2c1_sleep) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1) fn(DT_N_S_pin_controller_S_pwm0_default) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1) fn(DT_N_S_pin_controller_S_pwm0_sleep) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1) fn(DT_N_S_pin_controller_S_spi0_default) fn(DT_N_S_pin_controller_S_spi0_default_S_group1) fn(DT_N_S_pin_controller_S_spi0_sleep) fn(DT_N_S_pin_controller_S_spi0_sleep_S_group1) fn(DT_N_S_pin_controller_S_spi1_default) fn(DT_N_S_pin_controller_S_spi1_default_S_group1) fn(DT_N_S_pin_controller_S_spi1_sleep) fn(DT_N_S_pin_controller_S_spi1_sleep_S_group1) fn(DT_N_S_pin_controller_S_spi2_default) fn(DT_N_S_pin_controller_S_spi2_default_S_group1) fn(DT_N_S_pin_controller_S_spi2_sleep) fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1) fn(DT_N_S_pin_controller_S_qspi_default) fn(DT_N_S_pin_controller_S_qspi_default_S_group1) fn(DT_N_S_pin_controller_S_qspi_sleep) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2) fn(DT_N_S_pin_controller_S_spi3_default) fn(DT_N_S_pin_controller_S_spi3_default_S_group1) fn(DT_N_S_pin_controller_S_spi3_sleep) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1) fn(DT_N_S_entropy_bt_hci) fn(DT_N_S_cpus) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000) fn(DT_N_S_leds) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_leds_S_led_3) fn(DT_N_S_pwmleds) fn(DT_N_S_pwmleds_S_pwm_led_0) fn(DT_N_S_buttons) fn(DT_N_S_buttons_S_button_0) fn(DT_N_S_buttons_S_button_1) fn(DT_N_S_buttons_S_button_2) fn(DT_N_S_buttons_S_button_3) fn(DT_N_S_connector) fn(DT_N_S_analog_connector)
#define DT_FOREACH_VARGS_HELPER(fn, ...) fn(DT_N, __VA_ARGS__) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) fn(DT_N_S_soc_S_ficr_10000000, __VA_ARGS__) fn(DT_N_S_soc_S_uicr_10001000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_soc_S_clock_40000000, __VA_ARGS__) fn(DT_N_S_soc_S_power_40000000, __VA_ARGS__) fn(DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c, __VA_ARGS__) fn(DT_N_S_soc_S_power_40000000_S_gpregret2_40000520, __VA_ARGS__) fn(DT_N_S_soc_S_radio_40001000, __VA_ARGS__) fn(DT_N_S_soc_S_radio_40001000_S_ieee802154, __VA_ARGS__) fn(DT_N_S_soc_S_uart_40002000, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40003000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40003000, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40004000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40004000, __VA_ARGS__) fn(DT_N_S_soc_S_nfct_40005000, __VA_ARGS__) fn(DT_N_S_soc_S_gpiote_40006000, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40007000, __VA_ARGS__) fn(DT_N_S_soc_S_timer_40008000, __VA_ARGS__) fn(DT_N_S_soc_S_timer_40009000, __VA_ARGS__) fn(DT_N_S_soc_S_timer_4000a000, __VA_ARGS__) fn(DT_N_S_soc_S_rtc_4000b000, __VA_ARGS__) fn(DT_N_S_soc_S_temp_4000c000, __VA_ARGS__) fn(DT_N_S_soc_S_random_4000d000, __VA_ARGS__) fn(DT_N_S_soc_S_ecb_4000e000, __VA_ARGS__) fn(DT_N_S_soc_S_ccm_4000f000, __VA_ARGS__) fn(DT_N_S_soc_S_watchdog_40010000, __VA_ARGS__) fn(DT_N_S_soc_S_rtc_40011000, __VA_ARGS__) fn(DT_N_S_soc_S_qdec_40012000, __VA_ARGS__) fn(DT_N_S_soc_S_comparator_40013000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40014000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40015000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40016000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40017000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40018000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40019000, __VA_ARGS__) fn(DT_N_S_soc_S_timer_4001a000, __VA_ARGS__) fn(DT_N_S_soc_S_timer_4001b000, __VA_ARGS__) fn(DT_N_S_soc_S_pwm_4001c000, __VA_ARGS__) fn(DT_N_S_soc_S_pdm_4001d000, __VA_ARGS__) fn(DT_N_S_soc_S_acl_4001e000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_4001e000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000, __VA_ARGS__) fn(DT_N_S_soc_S_ppi_4001f000, __VA_ARGS__) fn(DT_N_S_soc_S_mwu_40020000, __VA_ARGS__) fn(DT_N_S_soc_S_pwm_40021000, __VA_ARGS__) fn(DT_N_S_soc_S_pwm_40022000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40023000, __VA_ARGS__) fn(DT_N_S_soc_S_rtc_40024000, __VA_ARGS__) fn(DT_N_S_soc_S_i2s_40025000, __VA_ARGS__) fn(DT_N_S_soc_S_usbd_40027000, __VA_ARGS__) fn(DT_N_S_soc_S_uart_40028000, __VA_ARGS__) fn(DT_N_S_soc_S_qspi_40029000, __VA_ARGS__) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, __VA_ARGS__) fn(DT_N_S_soc_S_pwm_4002d000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_4002f000, __VA_ARGS__) fn(DT_N_S_soc_S_gpio_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_gpio_50000300, __VA_ARGS__) fn(DT_N_S_soc_S_crypto_5002a000, __VA_ARGS__) fn(DT_N_S_pin_controller, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default_S_group2, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi0_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi1_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi1_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi1_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi2_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi2_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi2_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) fn(DT_N_S_sw_pwm, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__) fn(DT_N_S_leds_S_led_3, __VA_ARGS__) fn(DT_N_S_pwmleds, __VA_ARGS__) fn(DT_N_S_pwmleds_S_pwm_led_0, __VA_ARGS__) fn(DT_N_S_buttons, __VA_ARGS__) fn(DT_N_S_buttons_S_button_0, __VA_ARGS__) fn(DT_N_S_buttons_S_button_1, __VA_ARGS__) fn(DT_N_S_buttons_S_button_2, __VA_ARGS__) fn(DT_N_S_buttons_S_button_3, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_analog_connector, __VA_ARGS__)
#define DT_FOREACH_OKAY_VARGS_HELPER(fn, ...) fn(DT_N, __VA_ARGS__) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_ficr_10000000, __VA_ARGS__) fn(DT_N_S_soc_S_uicr_10001000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_soc_S_clock_40000000, __VA_ARGS__) fn(DT_N_S_soc_S_power_40000000, __VA_ARGS__) fn(DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c, __VA_ARGS__) fn(DT_N_S_soc_S_power_40000000_S_gpregret2_40000520, __VA_ARGS__) fn(DT_N_S_soc_S_radio_40001000, __VA_ARGS__) fn(DT_N_S_soc_S_radio_40001000_S_ieee802154, __VA_ARGS__) fn(DT_N_S_soc_S_uart_40002000, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40003000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40004000, __VA_ARGS__) fn(DT_N_S_soc_S_gpiote_40006000, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40007000, __VA_ARGS__) fn(DT_N_S_soc_S_temp_4000c000, __VA_ARGS__) fn(DT_N_S_soc_S_random_4000d000, __VA_ARGS__) fn(DT_N_S_soc_S_ecb_4000e000, __VA_ARGS__) fn(DT_N_S_soc_S_ccm_4000f000, __VA_ARGS__) fn(DT_N_S_soc_S_watchdog_40010000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40014000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40015000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40016000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40017000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40018000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40019000, __VA_ARGS__) fn(DT_N_S_soc_S_pwm_4001c000, __VA_ARGS__) fn(DT_N_S_soc_S_acl_4001e000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_4001e000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000, __VA_ARGS__) fn(DT_N_S_soc_S_ppi_4001f000, __VA_ARGS__) fn(DT_N_S_soc_S_mwu_40020000, __VA_ARGS__) fn(DT_N_S_soc_S_usbd_40027000, __VA_ARGS__) fn(DT_N_S_soc_S_qspi_40029000, __VA_ARGS__) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, __VA_ARGS__) fn(DT_N_S_soc_S_spi_4002f000, __VA_ARGS__) fn(DT_N_S_soc_S_gpio_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_gpio_50000300, __VA_ARGS__) fn(DT_N_S_soc_S_crypto_5002a000, __VA_ARGS__) fn(DT_N_S_pin_controller, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_default_S_group2, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart1_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c0_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_pwm0_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi0_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi1_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi1_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi1_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi2_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi2_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi2_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_qspi_sleep_S_group2, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi3_sleep_S_group1, __VA_ARGS__) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__) fn(DT_N_S_leds_S_led_3, __VA_ARGS__) fn(DT_N_S_pwmleds, __VA_ARGS__) fn(DT_N_S_pwmleds_S_pwm_led_0, __VA_ARGS__) fn(DT_N_S_buttons, __VA_ARGS__) fn(DT_N_S_buttons_S_button_0, __VA_ARGS__) fn(DT_N_S_buttons_S_button_1, __VA_ARGS__) fn(DT_N_S_buttons_S_button_2, __VA_ARGS__) fn(DT_N_S_buttons_S_button_3, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_analog_connector, __VA_ARGS__)
#define DT_COMPAT_fixed_partitions_LABEL_mcuboot DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_0
#define DT_COMPAT_fixed_partitions_LABEL_mcuboot_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_image_0 DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_c000
#define DT_COMPAT_fixed_partitions_LABEL_image_0_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_image_1 DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_82000
#define DT_COMPAT_fixed_partitions_LABEL_image_1_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_storage DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions_S_partition_f8000
#define DT_COMPAT_fixed_partitions_LABEL_storage_EXISTS 1

/*
 * Macros for compatibles with status "okay" nodes
 */
#define DT_COMPAT_HAS_OKAY_nordic_nrf52840_dk_nrf52840 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf52840_qiaa 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf52840 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf52 1
#define DT_COMPAT_HAS_OKAY_simple_bus 1
#define DT_COMPAT_HAS_OKAY_arm_v7m_nvic 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_ficr 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_uicr 1
#define DT_COMPAT_HAS_OKAY_mmio_sram 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_clock 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_power 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_gpregret 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_radio 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_ieee802154 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_uarte 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_twi 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_spi 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_gpiote 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_saadc 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_temp 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_rng 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_ecb 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_ccm 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_wdt 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_egu 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_swi 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_pwm 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_acl 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf52_flash_controller 1
#define DT_COMPAT_HAS_OKAY_soc_nv_flash 1
#define DT_COMPAT_HAS_OKAY_fixed_partitions 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_ppi 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_mwu 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_usbd 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_qspi 1
#define DT_COMPAT_HAS_OKAY_nordic_qspi_nor 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_spim 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_gpio 1
#define DT_COMPAT_HAS_OKAY_nordic_cryptocell 1
#define DT_COMPAT_HAS_OKAY_arm_cryptocell_310 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_pinctrl 1
#define DT_COMPAT_HAS_OKAY_zephyr_bt_hci_entropy 1
#define DT_COMPAT_HAS_OKAY_arm_cortex_m4f 1
#define DT_COMPAT_HAS_OKAY_arm_armv7m_itm 1
#define DT_COMPAT_HAS_OKAY_gpio_leds 1
#define DT_COMPAT_HAS_OKAY_pwm_leds 1
#define DT_COMPAT_HAS_OKAY_gpio_keys 1
#define DT_COMPAT_HAS_OKAY_arduino_header_r3 1
#define DT_COMPAT_HAS_OKAY_arduino_uno_adc 1

/*
 * Macros for status "okay" instances of each compatible
 */
#define DT_N_INST_nordic_nrf52840_dk_nrf52840_NUM_OKAY 1
#define DT_N_INST_nordic_nrf52840_qiaa_NUM_OKAY 1
#define DT_N_INST_nordic_nrf52840_NUM_OKAY 1
#define DT_N_INST_nordic_nrf52_NUM_OKAY 1
#define DT_N_INST_simple_bus_NUM_OKAY 1
#define DT_N_INST_arm_v7m_nvic_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_ficr_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_uicr_NUM_OKAY 1
#define DT_N_INST_mmio_sram_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_clock_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_power_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_gpregret_NUM_OKAY 2
#define DT_N_INST_nordic_nrf_radio_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_ieee802154_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_uarte_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_twi_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_spi_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_gpiote_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_saadc_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_temp_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_rng_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_ecb_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_ccm_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_wdt_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_egu_NUM_OKAY 6
#define DT_N_INST_nordic_nrf_swi_NUM_OKAY 6
#define DT_N_INST_nordic_nrf_pwm_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_acl_NUM_OKAY 1
#define DT_N_INST_nordic_nrf52_flash_controller_NUM_OKAY 1
#define DT_N_INST_soc_nv_flash_NUM_OKAY 1
#define DT_N_INST_fixed_partitions_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_ppi_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_mwu_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_usbd_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_qspi_NUM_OKAY 1
#define DT_N_INST_nordic_qspi_nor_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_spim_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_gpio_NUM_OKAY 2
#define DT_N_INST_nordic_cryptocell_NUM_OKAY 1
#define DT_N_INST_arm_cryptocell_310_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_pinctrl_NUM_OKAY 1
#define DT_N_INST_zephyr_bt_hci_entropy_NUM_OKAY 1
#define DT_N_INST_arm_cortex_m4f_NUM_OKAY 1
#define DT_N_INST_arm_armv7m_itm_NUM_OKAY 1
#define DT_N_INST_gpio_leds_NUM_OKAY 1
#define DT_N_INST_pwm_leds_NUM_OKAY 1
#define DT_N_INST_gpio_keys_NUM_OKAY 1
#define DT_N_INST_arduino_header_r3_NUM_OKAY 1
#define DT_N_INST_arduino_uno_adc_NUM_OKAY 1
#define DT_FOREACH_OKAY_nordic_nrf52840_dk_nrf52840(fn) fn(DT_N)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf52840_dk_nrf52840(fn, ...) fn(DT_N, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf52840_dk_nrf52840(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf52840_dk_nrf52840(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf52840_qiaa(fn) fn(DT_N_S_soc)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf52840_qiaa(fn, ...) fn(DT_N_S_soc, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf52840_qiaa(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf52840_qiaa(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf52840(fn) fn(DT_N_S_soc)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf52840(fn, ...) fn(DT_N_S_soc, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf52840(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf52840(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf52(fn) fn(DT_N_S_soc)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf52(fn, ...) fn(DT_N_S_soc, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf52(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf52(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_simple_bus(fn) fn(DT_N_S_soc)
#define DT_FOREACH_OKAY_VARGS_simple_bus(fn, ...) fn(DT_N_S_soc, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_simple_bus(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_simple_bus(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_arm_v7m_nvic(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100)
#define DT_FOREACH_OKAY_VARGS_arm_v7m_nvic(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_arm_v7m_nvic(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_arm_v7m_nvic(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_ficr(fn) fn(DT_N_S_soc_S_ficr_10000000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_ficr(fn, ...) fn(DT_N_S_soc_S_ficr_10000000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_ficr(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_ficr(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_uicr(fn) fn(DT_N_S_soc_S_uicr_10001000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_uicr(fn, ...) fn(DT_N_S_soc_S_uicr_10001000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_uicr(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_uicr(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_mmio_sram(fn) fn(DT_N_S_soc_S_memory_20000000)
#define DT_FOREACH_OKAY_VARGS_mmio_sram(fn, ...) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_mmio_sram(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_mmio_sram(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_clock(fn) fn(DT_N_S_soc_S_clock_40000000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_clock(fn, ...) fn(DT_N_S_soc_S_clock_40000000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_clock(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_clock(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_power(fn) fn(DT_N_S_soc_S_power_40000000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_power(fn, ...) fn(DT_N_S_soc_S_power_40000000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_power(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_power(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_gpregret(fn) fn(DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c) fn(DT_N_S_soc_S_power_40000000_S_gpregret2_40000520)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_gpregret(fn, ...) fn(DT_N_S_soc_S_power_40000000_S_gpregret1_4000051c, __VA_ARGS__) fn(DT_N_S_soc_S_power_40000000_S_gpregret2_40000520, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_gpregret(fn) fn(0) fn(1)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_gpregret(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_radio(fn) fn(DT_N_S_soc_S_radio_40001000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_radio(fn, ...) fn(DT_N_S_soc_S_radio_40001000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_radio(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_radio(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_ieee802154(fn) fn(DT_N_S_soc_S_radio_40001000_S_ieee802154)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_ieee802154(fn, ...) fn(DT_N_S_soc_S_radio_40001000_S_ieee802154, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_ieee802154(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_ieee802154(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_uarte(fn) fn(DT_N_S_soc_S_uart_40002000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_uarte(fn, ...) fn(DT_N_S_soc_S_uart_40002000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_uarte(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_uarte(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_twi(fn) fn(DT_N_S_soc_S_i2c_40003000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_twi(fn, ...) fn(DT_N_S_soc_S_i2c_40003000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_twi(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_twi(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_spi(fn) fn(DT_N_S_soc_S_spi_40004000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_spi(fn, ...) fn(DT_N_S_soc_S_spi_40004000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_spi(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_spi(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_gpiote(fn) fn(DT_N_S_soc_S_gpiote_40006000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_gpiote(fn, ...) fn(DT_N_S_soc_S_gpiote_40006000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_gpiote(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_gpiote(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_saadc(fn) fn(DT_N_S_soc_S_adc_40007000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_saadc(fn, ...) fn(DT_N_S_soc_S_adc_40007000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_saadc(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_saadc(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_temp(fn) fn(DT_N_S_soc_S_temp_4000c000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_temp(fn, ...) fn(DT_N_S_soc_S_temp_4000c000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_temp(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_temp(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_rng(fn) fn(DT_N_S_soc_S_random_4000d000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_rng(fn, ...) fn(DT_N_S_soc_S_random_4000d000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_rng(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_rng(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_ecb(fn) fn(DT_N_S_soc_S_ecb_4000e000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_ecb(fn, ...) fn(DT_N_S_soc_S_ecb_4000e000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_ecb(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_ecb(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_ccm(fn) fn(DT_N_S_soc_S_ccm_4000f000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_ccm(fn, ...) fn(DT_N_S_soc_S_ccm_4000f000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_ccm(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_ccm(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_wdt(fn) fn(DT_N_S_soc_S_watchdog_40010000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_wdt(fn, ...) fn(DT_N_S_soc_S_watchdog_40010000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_wdt(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_wdt(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_egu(fn) fn(DT_N_S_soc_S_egu_40014000) fn(DT_N_S_soc_S_egu_40015000) fn(DT_N_S_soc_S_egu_40016000) fn(DT_N_S_soc_S_egu_40017000) fn(DT_N_S_soc_S_egu_40018000) fn(DT_N_S_soc_S_egu_40019000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_egu(fn, ...) fn(DT_N_S_soc_S_egu_40014000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40015000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40016000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40017000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40018000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40019000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_egu(fn) fn(0) fn(1) fn(2) fn(3) fn(4) fn(5)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_egu(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) fn(2, __VA_ARGS__) fn(3, __VA_ARGS__) fn(4, __VA_ARGS__) fn(5, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_swi(fn) fn(DT_N_S_soc_S_egu_40014000) fn(DT_N_S_soc_S_egu_40015000) fn(DT_N_S_soc_S_egu_40016000) fn(DT_N_S_soc_S_egu_40017000) fn(DT_N_S_soc_S_egu_40018000) fn(DT_N_S_soc_S_egu_40019000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_swi(fn, ...) fn(DT_N_S_soc_S_egu_40014000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40015000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40016000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40017000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40018000, __VA_ARGS__) fn(DT_N_S_soc_S_egu_40019000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_swi(fn) fn(0) fn(1) fn(2) fn(3) fn(4) fn(5)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_swi(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) fn(2, __VA_ARGS__) fn(3, __VA_ARGS__) fn(4, __VA_ARGS__) fn(5, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_pwm(fn) fn(DT_N_S_soc_S_pwm_4001c000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_pwm(fn, ...) fn(DT_N_S_soc_S_pwm_4001c000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_pwm(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_pwm(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_acl(fn) fn(DT_N_S_soc_S_acl_4001e000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_acl(fn, ...) fn(DT_N_S_soc_S_acl_4001e000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_acl(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_acl(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf52_flash_controller(fn) fn(DT_N_S_soc_S_flash_controller_4001e000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf52_flash_controller(fn, ...) fn(DT_N_S_soc_S_flash_controller_4001e000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf52_flash_controller(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf52_flash_controller(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_soc_nv_flash(fn) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0)
#define DT_FOREACH_OKAY_VARGS_soc_nv_flash(fn, ...) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_soc_nv_flash(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_soc_nv_flash(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_fixed_partitions(fn) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions)
#define DT_FOREACH_OKAY_VARGS_fixed_partitions(fn, ...) fn(DT_N_S_soc_S_flash_controller_4001e000_S_flash_0_S_partitions, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_fixed_partitions(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_fixed_partitions(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_ppi(fn) fn(DT_N_S_soc_S_ppi_4001f000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_ppi(fn, ...) fn(DT_N_S_soc_S_ppi_4001f000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_ppi(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_ppi(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_mwu(fn) fn(DT_N_S_soc_S_mwu_40020000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_mwu(fn, ...) fn(DT_N_S_soc_S_mwu_40020000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_mwu(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_mwu(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_usbd(fn) fn(DT_N_S_soc_S_usbd_40027000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_usbd(fn, ...) fn(DT_N_S_soc_S_usbd_40027000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_usbd(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_usbd(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_qspi(fn) fn(DT_N_S_soc_S_qspi_40029000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_qspi(fn, ...) fn(DT_N_S_soc_S_qspi_40029000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_qspi(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_qspi(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_qspi_nor(fn) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0)
#define DT_FOREACH_OKAY_VARGS_nordic_qspi_nor(fn, ...) fn(DT_N_S_soc_S_qspi_40029000_S_mx25r6435f_0, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_qspi_nor(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_qspi_nor(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_spim(fn) fn(DT_N_S_soc_S_spi_4002f000)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_spim(fn, ...) fn(DT_N_S_soc_S_spi_4002f000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_spim(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_spim(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_gpio(fn) fn(DT_N_S_soc_S_gpio_50000000) fn(DT_N_S_soc_S_gpio_50000300)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_gpio(fn, ...) fn(DT_N_S_soc_S_gpio_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_gpio_50000300, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_gpio(fn) fn(0) fn(1)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_gpio(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_cryptocell(fn) fn(DT_N_S_soc_S_crypto_5002a000)
#define DT_FOREACH_OKAY_VARGS_nordic_cryptocell(fn, ...) fn(DT_N_S_soc_S_crypto_5002a000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_cryptocell(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_cryptocell(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_arm_cryptocell_310(fn) fn(DT_N_S_soc_S_crypto_5002a000)
#define DT_FOREACH_OKAY_VARGS_arm_cryptocell_310(fn, ...) fn(DT_N_S_soc_S_crypto_5002a000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_arm_cryptocell_310(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_arm_cryptocell_310(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_nordic_nrf_pinctrl(fn) fn(DT_N_S_pin_controller)
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_pinctrl(fn, ...) fn(DT_N_S_pin_controller, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_nordic_nrf_pinctrl(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_pinctrl(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_zephyr_bt_hci_entropy(fn) fn(DT_N_S_entropy_bt_hci)
#define DT_FOREACH_OKAY_VARGS_zephyr_bt_hci_entropy(fn, ...) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_zephyr_bt_hci_entropy(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_zephyr_bt_hci_entropy(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_arm_cortex_m4f(fn) fn(DT_N_S_cpus_S_cpu_0)
#define DT_FOREACH_OKAY_VARGS_arm_cortex_m4f(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_arm_cortex_m4f(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_arm_cortex_m4f(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_arm_armv7m_itm(fn) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000)
#define DT_FOREACH_OKAY_VARGS_arm_armv7m_itm(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_itm_e0000000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_arm_armv7m_itm(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_arm_armv7m_itm(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_gpio_leds(fn) fn(DT_N_S_leds)
#define DT_FOREACH_OKAY_VARGS_gpio_leds(fn, ...) fn(DT_N_S_leds, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_gpio_leds(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_gpio_leds(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_pwm_leds(fn) fn(DT_N_S_pwmleds)
#define DT_FOREACH_OKAY_VARGS_pwm_leds(fn, ...) fn(DT_N_S_pwmleds, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_pwm_leds(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_pwm_leds(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_gpio_keys(fn) fn(DT_N_S_buttons)
#define DT_FOREACH_OKAY_VARGS_gpio_keys(fn, ...) fn(DT_N_S_buttons, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_gpio_keys(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_gpio_keys(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_arduino_header_r3(fn) fn(DT_N_S_connector)
#define DT_FOREACH_OKAY_VARGS_arduino_header_r3(fn, ...) fn(DT_N_S_connector, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_arduino_header_r3(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_arduino_header_r3(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_arduino_uno_adc(fn) fn(DT_N_S_analog_connector)
#define DT_FOREACH_OKAY_VARGS_arduino_uno_adc(fn, ...) fn(DT_N_S_analog_connector, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_arduino_uno_adc(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_arduino_uno_adc(fn, ...) fn(0, __VA_ARGS__)

/*
 * Bus information for status "okay" nodes of each compatible
 */
#define DT_COMPAT_nordic_qspi_nor_BUS_qspi 1
