/*******************************************************************************
* \file		s6e2ccxj.h
* 
* \version  1.0
*
* \date		7/29/2016
*
* \brief	CMSIS Core Peripheral Access Layer Header File for s6e2ccxj Device
*
********************************************************************************
* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY
* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
* PURPOSE.
*******************************************************************************/

#ifndef _S6E2CCXJ_H_
#define _S6E2CCXJ_H_
#define __S6E2CCXJ_H__
#define __S6E2CC_H__

#if defined __cplusplus
extern "C" {
#endif

#define FM_GENERAL_MCUHEADER_VERSION              0201


#ifndef FM_DEVICE_PACKAGE_S6E_J
#define FM_DEVICE_PACKAGE_S6E_J
#endif 

/*******************************************************************************
* Configuration of the Cortex-M4 Processor and Core Peripherals
*******************************************************************************/
#define FM4_DEVICE_TYPE                           3
#define FM_DEVICE_TYPE                            4003u
#define FM_CORE_TYPE_FM4                          1
#define __CM4_REV                                 0x0001
#define __MPU_PRESENT                             1
#define __NVIC_PRIO_BITS                          4
#define __Vendor_SysTickConfig                    0
#define __FPU_PRESENT                             1
#define __FPU_DP                                  0
#define __ICACHE_PRESENT                          0
#define __DCACHE_PRESENT                          0
#define __DTCM_PRESENT                            0

/*******************************************************************************
* Peripheral Types
*******************************************************************************/
#define FM4_ADC_TYPE_A                            1
#define FM4_BT_TYPE_A                             1
#define FM4_BTIOSEL03_TYPE_A                      1
#define FM4_BTIOSEL47_TYPE_A                      1
#define FM4_BTIOSEL8B_TYPE_A                      1
#define FM4_BTIOSELCF_TYPE_A                      1
#define FM4_CAN_TYPE_A                            1
#define FM4_CANFD_TYPE_A                          1
#define FM4_CANPRES_TYPE_A                        1
#define FM4_CLK_GATING_TYPE_B                     1
#define FM4_CRC_TYPE_A                            1
#define FM4_CRG_TYPE_B                            1
#define FM4_CRTRIM_TYPE_A                         1
#define FM4_DAC_TYPE_A                            1
#define FM4_DMAC_TYPE_A                           1
#define FM4_DS_TYPE_A                             1
#define FM4_DSTC_TYPE_A                           1
#define FM4_DT_TYPE_A                             1
#define FM4_DUALFLASH_IF_TYPE_A                   1
#define FM4_ECC_CAPTURE_TYPE_A                    1
#define FM4_ETHERNET_CONTROL_TYPE_A               1
#define FM4_ETHERNET_MAC_TYPE_A                   1
#define FM4_EXBUS_TYPE_B                          1
#define FM4_EXTI_TYPE_A                           1
#define FM4_FLASH_IF_TYPE_B                       1
#define FM4_GPIO_TYPE_B                           1
#define FM4_HSSPI_TYPE_A                          1
#define FM4_HWWDT_TYPE_A                          1
#define FM4_I2S_TYPE_A                            1
#define FM4_I2SPRE_TYPE_A                         1
#define FM4_INTREQ_TYPE_B                         1
#define FM4_LSCRP_TYPE_A                          1
#define FM4_LVD_TYPE_A                            1
#define FM4_MFS_TYPE_B                            1
#define FM4_MFT_TYPE_B                            1
#define FM4_MFT_PPG_TYPE_A                        1
#define FM4_PCRC_TYPE_A                           1
#define FM4_QPRC_TYPE_B                           1
#define FM4_QPRC_NF_TYPE_A                        1
#define FM4_RTC_TYPE_A                            1
#define FM4_SBSSR_TYPE_A                          1
#define FM4_SDIF_TYPE_A                           1
#define FM4_SWWDT_TYPE_A                          1
#define FM4_UNIQUE_ID_TYPE_A                      1
#define FM4_USB_TYPE_A                            1
#define FM4_USBETHERCLK_TYPE_A                    1
#define FM4_WC_TYPE_A                             1

/*******************************************************************************
* Available Peripherals
*******************************************************************************/
#define FM4_ADC_AVAILABLE                         1
#define FM_ADC_AVAILABLE                          1
#define FM4_BT_AVAILABLE                          1
#define FM_BT_AVAILABLE                           1
#define FM4_BT_PPG_AVAILABLE                      1
#define FM_BT_PPG_AVAILABLE                       1
#define FM4_BT_PWC_AVAILABLE                      1
#define FM_BT_PWC_AVAILABLE                       1
#define FM4_BT_PWM_AVAILABLE                      1
#define FM_BT_PWM_AVAILABLE                       1
#define FM4_BT_RT_AVAILABLE                       1
#define FM_BT_RT_AVAILABLE                        1
#define FM4_BTIOSEL03_AVAILABLE                   1
#define FM_BTIOSEL03_AVAILABLE                    1
#define FM4_BTIOSEL47_AVAILABLE                   1
#define FM_BTIOSEL47_AVAILABLE                    1
#define FM4_BTIOSEL8B_AVAILABLE                   1
#define FM_BTIOSEL8B_AVAILABLE                    1
#define FM4_BTIOSELCF_AVAILABLE                   1
#define FM_BTIOSELCF_AVAILABLE                    1
#define FM4_CAN_AVAILABLE                         1
#define FM_CAN_AVAILABLE                          1
#define FM4_CANFD_AVAILABLE                       1
#define FM_CANFD_AVAILABLE                        1
#define FM4_CANPRES_AVAILABLE                     1
#define FM_CANPRES_AVAILABLE                      1
#define FM4_CLK_GATING_AVAILABLE                  1
#define FM_CLK_GATING_AVAILABLE                   1
#define FM4_CRC_AVAILABLE                         1
#define FM_CRC_AVAILABLE                          1
#define FM4_CRG_AVAILABLE                         1
#define FM_CRG_AVAILABLE                          1
#define FM4_CRTRIM_AVAILABLE                      1
#define FM_CRTRIM_AVAILABLE                       1
#define FM4_DAC_AVAILABLE                         1
#define FM_DAC_AVAILABLE                          1
#define FM4_DMAC_AVAILABLE                        1
#define FM_DMAC_AVAILABLE                         1
#define FM4_DS_AVAILABLE                          1
#define FM_DS_AVAILABLE                           1
#define FM4_DSTC_AVAILABLE                        1
#define FM_DSTC_AVAILABLE                         1
#define FM4_DT_AVAILABLE                          1
#define FM_DT_AVAILABLE                           1
#define FM4_DUALFLASH_IF_AVAILABLE                1
#define FM_DUALFLASH_IF_AVAILABLE                 1
#define FM4_ECC_CAPTURE_AVAILABLE                 1
#define FM_ECC_CAPTURE_AVAILABLE                  1
#define FM4_ETHERNET_CONTROL_AVAILABLE            1
#define FM_ETHERNET_CONTROL_AVAILABLE             1
#define FM4_ETHERNET_MAC_AVAILABLE                1
#define FM_ETHERNET_MAC_AVAILABLE                 1
#define FM4_EXBUS_AVAILABLE                       1
#define FM_EXBUS_AVAILABLE                        1
#define FM4_EXTI_AVAILABLE                        1
#define FM_EXTI_AVAILABLE                         1
#define FM4_FLASH_IF_AVAILABLE                    1
#define FM_FLASH_IF_AVAILABLE                     1
#define FM4_GPIO_AVAILABLE                        1
#define FM_GPIO_AVAILABLE                         1
#define FM4_HSSPI_AVAILABLE                       1
#define FM_HSSPI_AVAILABLE                        1
#define FM4_HWWDT_AVAILABLE                       1
#define FM_HWWDT_AVAILABLE                        1
#define FM4_I2S_AVAILABLE                         1
#define FM_I2S_AVAILABLE                          1
#define FM4_I2SPRE_AVAILABLE                      1
#define FM_I2SPRE_AVAILABLE                       1
#define FM4_INTREQ_AVAILABLE                      1
#define FM_INTREQ_AVAILABLE                       1
#define FM4_LSCRP_AVAILABLE                       1
#define FM_LSCRP_AVAILABLE                        1
#define FM4_LVD_AVAILABLE                         1
#define FM_LVD_AVAILABLE                          1
#define FM4_MFS_AVAILABLE                         1
#define FM_MFS_AVAILABLE                          1
#define FM4_MFS_CSIO_AVAILABLE                    1
#define FM_MFS_CSIO_AVAILABLE                     1
#define FM4_MFS_I2C_AVAILABLE                     1
#define FM_MFS_I2C_AVAILABLE                      1
#define FM4_MFS_LIN_AVAILABLE                     1
#define FM_MFS_LIN_AVAILABLE                      1
#define FM4_MFS_UART_AVAILABLE                    1
#define FM_MFS_UART_AVAILABLE                     1
#define FM4_MFT_AVAILABLE                         1
#define FM_MFT_AVAILABLE                          1
#define FM4_MFT_ADCMP_AVAILABLE                   1
#define FM_MFT_ADCMP_AVAILABLE                    1
#define FM4_MFT_FRT_AVAILABLE                     1
#define FM_MFT_FRT_AVAILABLE                      1
#define FM4_MFT_ICU_AVAILABLE                     1
#define FM_MFT_ICU_AVAILABLE                      1
#define FM4_MFT_OCU_AVAILABLE                     1
#define FM_MFT_OCU_AVAILABLE                      1
#define FM4_MFT_PPG_AVAILABLE                     1
#define FM_MFT_PPG_AVAILABLE                      1
#define FM4_MFT_WFG_AVAILABLE                     1
#define FM_MFT_WFG_AVAILABLE                      1
#define FM4_PCRC_AVAILABLE                        1
#define FM_PCRC_AVAILABLE                         1
#define FM4_QPRC_AVAILABLE                        1
#define FM_QPRC_AVAILABLE                         1
#define FM4_QPRC_NF_AVAILABLE                     1
#define FM_QPRC_NF_AVAILABLE                      1
#define FM4_RTC_AVAILABLE                         1
#define FM_RTC_AVAILABLE                          1
#define FM4_SBSSR_AVAILABLE                       1
#define FM_SBSSR_AVAILABLE                        1
#define FM4_SDIF_AVAILABLE                        1
#define FM_SDIF_AVAILABLE                         1
#define FM4_SWWDT_AVAILABLE                       1
#define FM_SWWDT_AVAILABLE                        1
#define FM4_UNIQUE_ID_AVAILABLE                   1
#define FM_UNIQUE_ID_AVAILABLE                    1
#define FM4_USB_AVAILABLE                         1
#define FM_USB_AVAILABLE                          1
#define FM4_USBETHERCLK_AVAILABLE                 1
#define FM_USBETHERCLK_AVAILABLE                  1
#define FM4_WC_AVAILABLE                          1
#define FM_WC_AVAILABLE                           1

/*******************************************************************************
* \brief Interrupt number definition for all type MCUs
*******************************************************************************/
#define FM_INTERRUPT_TYPE                         0x400Bu

#define IRQ_NMI_AVAILABLE                         1
#define IRQ_HARDFAULT_AVAILABLE                   1
#define IRQ_MEMMANAGE_AVAILABLE                   1
#define IRQ_BUSFAULT_AVAILABLE                    1
#define IRQ_USAGEFAULT_AVAILABLE                  1
#define IRQ_SVC_AVAILABLE                         1
#define IRQ_DEBUGMONITOR_AVAILABLE                1
#define IRQ_PENDSV_AVAILABLE                      1
#define IRQ_SYSTICK_AVAILABLE                     1

#define IRQ_CSV_AVAILABLE                         1
#define IRQ_SWDT_AVAILABLE                        1
#define IRQ_LVD_AVAILABLE                         1
#define IRQ_IRQ003SEL_AVAILABLE                   1
#define IRQ_IRQ004SEL_AVAILABLE                   1
#define IRQ_IRQ005SEL_AVAILABLE                   1
#define IRQ_IRQ006SEL_AVAILABLE                   1
#define IRQ_IRQ007SEL_AVAILABLE                   1
#define IRQ_IRQ008SEL_AVAILABLE                   1
#define IRQ_IRQ009SEL_AVAILABLE                   1
#define IRQ_IRQ010SEL_AVAILABLE                   1
#define IRQ_EXINT0_AVAILABLE                      1
#define IRQ_EXINT1_AVAILABLE                      1
#define IRQ_EXINT2_AVAILABLE                      1
#define IRQ_EXINT3_AVAILABLE                      1
#define IRQ_EXINT4_AVAILABLE                      1
#define IRQ_EXINT5_AVAILABLE                      1
#define IRQ_EXINT6_AVAILABLE                      1
#define IRQ_EXINT7_AVAILABLE                      1
#define IRQ_QPRC0_AVAILABLE                       1
#define IRQ_QPRC1_AVAILABLE                       1
#define IRQ_MFT0_WFG_DTIF_AVAILABLE               1
#define IRQ_MFT1_WFG_DTIF_AVAILABLE               1
#define IRQ_MFT2_WFG_DTIF_AVAILABLE               1
#define IRQ_MFT0_FRT_PEAK_AVAILABLE               1
#define IRQ_MFT0_FRT_ZERO_AVAILABLE               1
#define IRQ_MFT0_ICU_AVAILABLE                    1
#define IRQ_MFT0_OCU_AVAILABLE                    1
#define IRQ_MFT1_FRT_PEAK_AVAILABLE               1
#define IRQ_MFT1_FRT_ZERO_AVAILABLE               1
#define IRQ_MFT1_ICU_AVAILABLE                    1
#define IRQ_MFT1_OCU_AVAILABLE                    1
#define IRQ_MFT2_FRT_PEAK_AVAILABLE               1
#define IRQ_MFT2_FRT_ZERO_AVAILABLE               1
#define IRQ_MFT2_ICU_AVAILABLE                    1
#define IRQ_MFT2_OCU_AVAILABLE                    1
#define IRQ_PPG00_02_04_AVAILABLE                 1
#define IRQ_PPG08_10_12_AVAILABLE                 1
#define IRQ_PPG16_18_20_AVAILABLE                 1
#define IRQ_BT0_AVAILABLE                         1
#define IRQ_BT1_AVAILABLE                         1
#define IRQ_BT2_AVAILABLE                         1
#define IRQ_BT3_AVAILABLE                         1
#define IRQ_BT4_AVAILABLE                         1
#define IRQ_BT5_AVAILABLE                         1
#define IRQ_BT6_AVAILABLE                         1
#define IRQ_BT7_AVAILABLE                         1
#define IRQ_DT_AVAILABLE                          1
#define IRQ_WC_AVAILABLE                          1
#define IRQ_EXTBUS_ERR_AVAILABLE                  1
#define IRQ_RTC_AVAILABLE                         1
#define IRQ_EXINT8_AVAILABLE                      1
#define IRQ_EXINT9_AVAILABLE                      1
#define IRQ_EXINT10_AVAILABLE                     1
#define IRQ_EXINT11_AVAILABLE                     1
#define IRQ_EXINT12_AVAILABLE                     1
#define IRQ_EXINT13_AVAILABLE                     1
#define IRQ_EXINT14_AVAILABLE                     1
#define IRQ_EXINT15_AVAILABLE                     1
#define IRQ_TIM_AVAILABLE                         1
#define IRQ_MFS0_RX_AVAILABLE                     1
#define IRQ_MFS0_TX_AVAILABLE                     1
#define IRQ_MFS1_RX_AVAILABLE                     1
#define IRQ_MFS1_TX_AVAILABLE                     1
#define IRQ_MFS2_RX_AVAILABLE                     1
#define IRQ_MFS2_TX_AVAILABLE                     1
#define IRQ_MFS3_RX_AVAILABLE                     1
#define IRQ_MFS3_TX_AVAILABLE                     1
#define IRQ_MFS4_RX_AVAILABLE                     1
#define IRQ_MFS4_TX_AVAILABLE                     1
#define IRQ_MFS5_RX_AVAILABLE                     1
#define IRQ_MFS5_TX_AVAILABLE                     1
#define IRQ_MFS6_RX_AVAILABLE                     1
#define IRQ_MFS6_TX_AVAILABLE                     1
#define IRQ_MFS7_RX_AVAILABLE                     1
#define IRQ_MFS7_TX_AVAILABLE                     1
#define IRQ_ADC0_AVAILABLE                        1
#define IRQ_ADC1_AVAILABLE                        1
#define IRQ_USB0_F_AVAILABLE                      1
#define IRQ_USB0_H_F_AVAILABLE                    1
#define IRQ_CAN0_AVAILABLE                        1
#define IRQ_CAN1_CANFD0_AVAILABLE                 1
#define IRQ_ETHER0_AVAILABLE                      1
#define IRQ_DMAC0_AVAILABLE                       1
#define IRQ_DMAC1_AVAILABLE                       1
#define IRQ_DMAC2_AVAILABLE                       1
#define IRQ_DMAC3_AVAILABLE                       1
#define IRQ_DMAC4_AVAILABLE                       1
#define IRQ_DMAC5_AVAILABLE                       1
#define IRQ_DMAC6_AVAILABLE                       1
#define IRQ_DMAC7_AVAILABLE                       1
#define IRQ_DSTC_AVAILABLE                        1
#define IRQ_EXINT16_19_AVAILABLE                  1
#define IRQ_EXINT20_23_AVAILABLE                  1
#define IRQ_EXINT24_27_AVAILABLE                  1
#define IRQ_EXINT28_31_AVAILABLE                  1
#define IRQ_QPRC2_AVAILABLE                       1
#define IRQ_QPRC3_AVAILABLE                       1
#define IRQ_BT8_AVAILABLE                         1
#define IRQ_BT9_AVAILABLE                         1
#define IRQ_BT10_AVAILABLE                        1
#define IRQ_BT11_AVAILABLE                        1
#define IRQ_BT12_15_AVAILABLE                     1
#define IRQ_MFS8_RX_AVAILABLE                     1
#define IRQ_MFS8_TX_AVAILABLE                     1
#define IRQ_MFS9_RX_AVAILABLE                     1
#define IRQ_MFS9_TX_AVAILABLE                     1
#define IRQ_MFS10_RX_AVAILABLE                    1
#define IRQ_MFS10_TX_AVAILABLE                    1
#define IRQ_MFS11_RX_AVAILABLE                    1
#define IRQ_MFS11_TX_AVAILABLE                    1
#define IRQ_ADC2_AVAILABLE                        1
#define IRQ_DSTC_HW_AVAILABLE                     1
#define IRQ_USB1_F_AVAILABLE                      1
#define IRQ_USB1_H_F_AVAILABLE                    1
#define IRQ_HSSPI_AVAILABLE                       1
#define IRQ_PCRC_I2S0_1_AVAILABLE                 1
#define IRQ_SD_AVAILABLE                          1
#define IRQ_FLASHIF_AVAILABLE                     1
#define IRQ_MFS12_RX_AVAILABLE                    1
#define IRQ_MFS12_TX_AVAILABLE                    1
#define IRQ_MFS13_RX_AVAILABLE                    1
#define IRQ_MFS13_TX_AVAILABLE                    1
#define IRQ_MFS14_RX_AVAILABLE                    1
#define IRQ_MFS14_TX_AVAILABLE                    1
#define IRQ_MFS15_RX_AVAILABLE                    1
#define IRQ_MFS15_TX_AVAILABLE                    1


typedef enum IRQn
{
    NMI_IRQn                                      =  -14, /* Non Maskable Interrupt NMI */
    HardFault_IRQn                                =  -13, /* HardFault HardFault */
    MemManage_IRQn                                =  -12, /* Memory Management MemManage */
    BusFault_IRQn                                 =  -11, /* Bus Fault BusFault */
    UsageFault_IRQn                               =  -10, /* Usage Fault UsageFault */
    SVC_IRQn                                      =   -5, /* SV Call SVC */
    DebugMonitor_IRQn                             =   -4, /* Debug Monitor DebugMonitor */
    PendSV_IRQn                                   =   -2, /* Pend SV PendSV */
    SysTick_IRQn                                  =   -1, /* System Tick SysTick */

    CSV_IRQn                                      =    0, /* CSV_IRQ */
    SWDT_IRQn                                     =    1, /* SWDT_IRQ */
    LVD_IRQn                                      =    2, /* LVD_IRQ */
    IRQ003SEL_IRQn                                =    3, /* IRQ003SEL_IRQ */
    IRQ004SEL_IRQn                                =    4, /* IRQ004SEL_IRQ */
    IRQ005SEL_IRQn                                =    5, /* IRQ005SEL_IRQ */
    IRQ006SEL_IRQn                                =    6, /* IRQ006SEL_IRQ */
    IRQ007SEL_IRQn                                =    7, /* IRQ007SEL_IRQ */
    IRQ008SEL_IRQn                                =    8, /* IRQ008SEL_IRQ */
    IRQ009SEL_IRQn                                =    9, /* IRQ009SEL_IRQ */
    IRQ010SEL_IRQn                                =   10, /* IRQ010SEL_IRQ */
    EXINT0_IRQn                                   =   11, /* EXINT0_IRQ */
    EXINT1_IRQn                                   =   12, /* EXINT1_IRQ */
    EXINT2_IRQn                                   =   13, /* EXINT2_IRQ */
    EXINT3_IRQn                                   =   14, /* EXINT3_IRQ */
    EXINT4_IRQn                                   =   15, /* EXINT4_IRQ */
    EXINT5_IRQn                                   =   16, /* EXINT5_IRQ */
    EXINT6_IRQn                                   =   17, /* EXINT6_IRQ */
    EXINT7_IRQn                                   =   18, /* EXINT7_IRQ */
    QPRC0_IRQn                                    =   19, /* QPRC0_IRQ */
    QPRC1_IRQn                                    =   20, /* QPRC1_IRQ */
    MFT0_WFG_DTIF_IRQn                            =   21, /* MFT0_WFG_DTIF_IRQ */
    MFT1_WFG_DTIF_IRQn                            =   22, /* MFT1_WFG_DTIF_IRQ */
    MFT2_WFG_DTIF_IRQn                            =   23, /* MFT2_WFG_DTIF_IRQ */
    MFT0_FRT_PEAK_IRQn                            =   24, /* MFT0_FRT_PEAK_IRQ */
    MFT0_FRT_ZERO_IRQn                            =   25, /* MFT0_FRT_ZERO_IRQ */
    MFT0_ICU_IRQn                                 =   26, /* MFT0_ICU_IRQ */
    MFT0_OCU_IRQn                                 =   27, /* MFT0_OCU_IRQ */
    MFT1_FRT_PEAK_IRQn                            =   28, /* MFT1_FRT_PEAK_IRQ */
    MFT1_FRT_ZERO_IRQn                            =   29, /* MFT1_FRT_ZERO_IRQ */
    MFT1_ICU_IRQn                                 =   30, /* MFT1_ICU_IRQ */
    MFT1_OCU_IRQn                                 =   31, /* MFT1_OCU_IRQ */
    MFT2_FRT_PEAK_IRQn                            =   32, /* MFT2_FRT_PEAK_IRQ */
    MFT2_FRT_ZERO_IRQn                            =   33, /* MFT2_FRT_ZERO_IRQ */
    MFT2_ICU_IRQn                                 =   34, /* MFT2_ICU_IRQ */
    MFT2_OCU_IRQn                                 =   35, /* MFT2_OCU_IRQ */
    PPG00_02_04_IRQn                              =   36, /* PPG00_02_04_IRQ */
    PPG08_10_12_IRQn                              =   37, /* PPG08_10_12_IRQ */
    PPG16_18_20_IRQn                              =   38, /* PPG16_18_20_IRQ */
    BT0_IRQn                                      =   39, /* BT0_IRQ */
    BT1_IRQn                                      =   40, /* BT1_IRQ */
    BT2_IRQn                                      =   41, /* BT2_IRQ */
    BT3_IRQn                                      =   42, /* BT3_IRQ */
    BT4_IRQn                                      =   43, /* BT4_IRQ */
    BT5_IRQn                                      =   44, /* BT5_IRQ */
    BT6_IRQn                                      =   45, /* BT6_IRQ */
    BT7_IRQn                                      =   46, /* BT7_IRQ */
    DT_IRQn                                       =   47, /* DT_IRQ */
    WC_IRQn                                       =   48, /* WC_IRQ */
    EXTBUS_ERR_IRQn                               =   49, /* EXTBUS_ERR_IRQ */
    RTC_IRQn                                      =   50, /* RTC_IRQ */
    EXINT8_IRQn                                   =   51, /* EXINT8_IRQ */
    EXINT9_IRQn                                   =   52, /* EXINT9_IRQ */
    EXINT10_IRQn                                  =   53, /* EXINT10_IRQ */
    EXINT11_IRQn                                  =   54, /* EXINT11_IRQ */
    EXINT12_IRQn                                  =   55, /* EXINT12_IRQ */
    EXINT13_IRQn                                  =   56, /* EXINT13_IRQ */
    EXINT14_IRQn                                  =   57, /* EXINT14_IRQ */
    EXINT15_IRQn                                  =   58, /* EXINT15_IRQ */
    TIM_IRQn                                      =   59, /* TIM_IRQ */
    MFS0_RX_IRQn                                  =   60, /* MFS0_RX_IRQ */
    MFS0_TX_IRQn                                  =   61, /* MFS0_TX_IRQ */
    MFS1_RX_IRQn                                  =   62, /* MFS1_RX_IRQ */
    MFS1_TX_IRQn                                  =   63, /* MFS1_TX_IRQ */
    MFS2_RX_IRQn                                  =   64, /* MFS2_RX_IRQ */
    MFS2_TX_IRQn                                  =   65, /* MFS2_TX_IRQ */
    MFS3_RX_IRQn                                  =   66, /* MFS3_RX_IRQ */
    MFS3_TX_IRQn                                  =   67, /* MFS3_TX_IRQ */
    MFS4_RX_IRQn                                  =   68, /* MFS4_RX_IRQ */
    MFS4_TX_IRQn                                  =   69, /* MFS4_TX_IRQ */
    MFS5_RX_IRQn                                  =   70, /* MFS5_RX_IRQ */
    MFS5_TX_IRQn                                  =   71, /* MFS5_TX_IRQ */
    MFS6_RX_IRQn                                  =   72, /* MFS6_RX_IRQ */
    MFS6_TX_IRQn                                  =   73, /* MFS6_TX_IRQ */
    MFS7_RX_IRQn                                  =   74, /* MFS7_RX_IRQ */
    MFS7_TX_IRQn                                  =   75, /* MFS7_TX_IRQ */
    ADC0_IRQn                                     =   76, /* ADC0_IRQ */
    ADC1_IRQn                                     =   77, /* ADC1_IRQ */
    USB0_F_IRQn                                   =   78, /* USB0_F_IRQ */
    USB0_H_F_IRQn                                 =   79, /* USB0_H_F_IRQ */
    CAN0_IRQn                                     =   80, /* CAN0_IRQ */
    CAN1_CANFD0_IRQn                              =   81, /* CAN1_CANFD0_IRQ */
    ETHER0_IRQn                                   =   82, /* ETHER0_IRQ */
    DMAC0_IRQn                                    =   83, /* DMAC0_IRQ */
    DMAC1_IRQn                                    =   84, /* DMAC1_IRQ */
    DMAC2_IRQn                                    =   85, /* DMAC2_IRQ */
    DMAC3_IRQn                                    =   86, /* DMAC3_IRQ */
    DMAC4_IRQn                                    =   87, /* DMAC4_IRQ */
    DMAC5_IRQn                                    =   88, /* DMAC5_IRQ */
    DMAC6_IRQn                                    =   89, /* DMAC6_IRQ */
    DMAC7_IRQn                                    =   90, /* DMAC7_IRQ */
    DSTC_IRQn                                     =   91, /* DSTC_IRQ */
    EXINT16_19_IRQn                               =   92, /* EXINT16_19_IRQ */
    EXINT20_23_IRQn                               =   93, /* EXINT20_23_IRQ */
    EXINT24_27_IRQn                               =   94, /* EXINT24_27_IRQ */
    EXINT28_31_IRQn                               =   95, /* EXINT28_31_IRQ */
    QPRC2_IRQn                                    =   96, /* QPRC2_IRQ */
    QPRC3_IRQn                                    =   97, /* QPRC3_IRQ */
    BT8_IRQn                                      =   98, /* BT8_IRQ */
    BT9_IRQn                                      =   99, /* BT9_IRQ */
    BT10_IRQn                                     =  100, /* BT10_IRQ */
    BT11_IRQn                                     =  101, /* BT11_IRQ */
    BT12_15_IRQn                                  =  102, /* BT12_15_IRQ */
    MFS8_RX_IRQn                                  =  103, /* MFS8_RX_IRQ */
    MFS8_TX_IRQn                                  =  104, /* MFS8_TX_IRQ */
    MFS9_RX_IRQn                                  =  105, /* MFS9_RX_IRQ */
    MFS9_TX_IRQn                                  =  106, /* MFS9_TX_IRQ */
    MFS10_RX_IRQn                                 =  107, /* MFS10_RX_IRQ */
    MFS10_TX_IRQn                                 =  108, /* MFS10_TX_IRQ */
    MFS11_RX_IRQn                                 =  109, /* MFS11_RX_IRQ */
    MFS11_TX_IRQn                                 =  110, /* MFS11_TX_IRQ */
    ADC2_IRQn                                     =  111, /* ADC2_IRQ */
    DSTC_HW_IRQn                                  =  112, /* DSTC_HW_IRQ */
    USB1_F_IRQn                                   =  113, /* USB1_F_IRQ */
    USB1_H_F_IRQn                                 =  114, /* USB1_H_F_IRQ */
    HSSPI_IRQn                                    =  115, /* HSSPI_IRQ */
    PCRC_I2S0_1_IRQn                              =  117, /* PCRC_I2S0_1_IRQ */
    SD_IRQn                                       =  118, /* SD_IRQ */
    FLASHIF_IRQn                                  =  119, /* FLASHIF_IRQ */
    MFS12_RX_IRQn                                 =  120, /* MFS12_RX_IRQ */
    MFS12_TX_IRQn                                 =  121, /* MFS12_TX_IRQ */
    MFS13_RX_IRQn                                 =  122, /* MFS13_RX_IRQ */
    MFS13_TX_IRQn                                 =  123, /* MFS13_TX_IRQ */
    MFS14_RX_IRQn                                 =  124, /* MFS14_RX_IRQ */
    MFS14_TX_IRQn                                 =  125, /* MFS14_TX_IRQ */
    MFS15_RX_IRQn                                 =  126, /* MFS15_RX_IRQ */
    MFS15_TX_IRQn                                 =  127, /* MFS15_TX_IRQ */
} IRQn_Type;

#include "core_cm4.h"
#include <stdint.h>

/*******************************************************************************
* Device Specific Peripheral Registers structures
*******************************************************************************/
#if defined ( __CC_ARM   )
#pragma anon_unions
#endif

/*******************************************************************************
* ADC_MODULE
*******************************************************************************/
typedef struct stc_adc_adsr_field
{
        __IO   uint8_t  SCS                      :1;
        __IO   uint8_t  PCS                      :1;
        __IO   uint8_t  PCNS                     :1;
        __IO   uint8_t  RESERVED0                :3;
        __IO   uint8_t  FDAS                     :1;
        __IO   uint8_t  ADSTP                    :1;
} stc_adc_adsr_field_t;

typedef struct stc_adc_adcr_field
{
        __IO   uint8_t  OVRIE                    :1;
        __IO   uint8_t  CMPIE                    :1;
        __IO   uint8_t  PCIE                     :1;
        __IO   uint8_t  SCIE                     :1;
        __IO   uint8_t  RESERVED0                :1;
        __IO   uint8_t  CMPIF                    :1;
        __IO   uint8_t  PCIF                     :1;
        __IO   uint8_t  SCIF                     :1;
} stc_adc_adcr_field_t;

typedef struct stc_adc_sfns_field
{
    union {
        struct {
            __IO   uint8_t  SFS                  :4;
            __IO   uint8_t  RESERVED0            :4;
        };
        struct {
            __IO   uint8_t  SFS0                 :1;
            __IO   uint8_t  SFS1                 :1;
            __IO   uint8_t  SFS2                 :1;
            __IO   uint8_t  SFS3                 :1;
            __IO   uint8_t  RESERVED1            :4;
        };
    };
} stc_adc_sfns_field_t;

typedef struct stc_adc_sccr_field
{
        __IO   uint8_t  SSTR                     :1;
        __IO   uint8_t  SHEN                     :1;
        __IO   uint8_t  RPT                      :1;
        __IO   uint8_t  RESERVED0                :1;
        __IO   uint8_t  SFCLR                    :1;
        __IO   uint8_t  SOVR                     :1;
        __IO   uint8_t  SFUL                     :1;
        __IO   uint8_t  SEMP                     :1;
} stc_adc_sccr_field_t;

typedef struct stc_adc_scfd_fdas1_field
{
    union {
        struct {
            __IO  uint32_t  SC                   :5;
            __IO  uint32_t  RESERVED0            :3;
            __IO  uint32_t  RS                   :2;
            __IO  uint32_t  RESERVED2            :2;
            __IO  uint32_t  INVL                 :1;
            __IO  uint32_t  RESERVED3            :3;
            __IO  uint32_t  SD                   :12;
            __IO  uint32_t  RESERVED5            :4;
        };
        struct {
            __IO  uint32_t  SC0                  :1;
            __IO  uint32_t  SC1                  :1;
            __IO  uint32_t  SC2                  :1;
            __IO  uint32_t  SC3                  :1;
            __IO  uint32_t  SC4                  :1;
            __IO  uint32_t  RESERVED1            :3;
            __IO  uint32_t  RS0                  :1;
            __IO  uint32_t  RS1                  :1;
            __IO  uint32_t  RESERVED4            :6;
            __IO  uint32_t  SD0                  :1;
            __IO  uint32_t  SD1                  :1;
            __IO  uint32_t  SD2                  :1;
            __IO  uint32_t  SD3                  :1;
            __IO  uint32_t  SD4                  :1;
            __IO  uint32_t  SD5                  :1;
            __IO  uint32_t  SD6                  :1;
            __IO  uint32_t  SD7                  :1;
            __IO  uint32_t  SD8                  :1;
            __IO  uint32_t  SD9                  :1;
            __IO  uint32_t  SD10                 :1;
            __IO  uint32_t  SD11                 :1;
            __IO  uint32_t  RESERVED6            :4;
        };
    };
} stc_adc_scfd_fdas1_field_t;

typedef struct stc_adc_scfd_field
{
    union {
        struct {
            __IO  uint32_t  SC                   :5;
            __IO  uint32_t  RESERVED0            :3;
            __IO  uint32_t  RS                   :2;
            __IO  uint32_t  RESERVED2            :2;
            __IO  uint32_t  INVL                 :1;
            __IO  uint32_t  RESERVED3            :7;
            __IO  uint32_t  SD                   :12;
        };
        struct {
            __IO  uint32_t  SC0                  :1;
            __IO  uint32_t  SC1                  :1;
            __IO  uint32_t  SC2                  :1;
            __IO  uint32_t  SC3                  :1;
            __IO  uint32_t  SC4                  :1;
            __IO  uint32_t  RESERVED1            :3;
            __IO  uint32_t  RS0                  :1;
            __IO  uint32_t  RS1                  :1;
            __IO  uint32_t  RESERVED4            :10;
            __IO  uint32_t  SD0                  :1;
            __IO  uint32_t  SD1                  :1;
            __IO  uint32_t  SD2                  :1;
            __IO  uint32_t  SD3                  :1;
            __IO  uint32_t  SD4                  :1;
            __IO  uint32_t  SD5                  :1;
            __IO  uint32_t  SD6                  :1;
            __IO  uint32_t  SD7                  :1;
            __IO  uint32_t  SD8                  :1;
            __IO  uint32_t  SD9                  :1;
            __IO  uint32_t  SD10                 :1;
            __IO  uint32_t  SD11                 :1;
        };
    };
} stc_adc_scfd_field_t;

typedef struct stc_adc_scis23_field
{
        __IO  uint16_t  AN16                     :1;
        __IO  uint16_t  AN17                     :1;
        __IO  uint16_t  AN18                     :1;
        __IO  uint16_t  AN19                     :1;
        __IO  uint16_t  AN20                     :1;
        __IO  uint16_t  AN21                     :1;
        __IO  uint16_t  AN22                     :1;
        __IO  uint16_t  AN23                     :1;
        __IO  uint16_t  AN24                     :1;
        __IO  uint16_t  AN25                     :1;
        __IO  uint16_t  AN26                     :1;
        __IO  uint16_t  AN27                     :1;
        __IO  uint16_t  AN28                     :1;
        __IO  uint16_t  AN29                     :1;
        __IO  uint16_t  AN30                     :1;
        __IO  uint16_t  AN31                     :1;
} stc_adc_scis23_field_t;

typedef struct stc_adc_scis01_field
{
        __IO  uint16_t  AN0                      :1;
        __IO  uint16_t  AN1                      :1;
        __IO  uint16_t  AN2                      :1;
        __IO  uint16_t  AN3                      :1;
        __IO  uint16_t  AN4                      :1;
        __IO  uint16_t  AN5                      :1;
        __IO  uint16_t  AN6                      :1;
        __IO  uint16_t  AN7                      :1;
        __IO  uint16_t  AN8                      :1;
        __IO  uint16_t  AN9                      :1;
        __IO  uint16_t  AN10                     :1;
        __IO  uint16_t  AN11                     :1;
        __IO  uint16_t  AN12                     :1;
        __IO  uint16_t  AN13                     :1;
        __IO  uint16_t  AN14                     :1;
        __IO  uint16_t  AN15                     :1;
} stc_adc_scis01_field_t;

typedef struct stc_adc_pfns_field
{
    union {
        struct {
            __IO   uint8_t  PFS                  :2;
            __IO   uint8_t  RESERVED0            :2;
            __IO   uint8_t  TEST                 :2;
            __IO   uint8_t  RESERVED2            :2;
        };
        struct {
            __IO   uint8_t  PFS0                 :1;
            __IO   uint8_t  PFS1                 :1;
            __IO   uint8_t  RESERVED1            :2;
            __IO   uint8_t  TEST0                :1;
            __IO   uint8_t  TEST1                :1;
            __IO   uint8_t  RESERVED3            :2;
        };
    };
} stc_adc_pfns_field_t;

typedef struct stc_adc_pccr_field
{
        __IO   uint8_t  PSTR                     :1;
        __IO   uint8_t  PHEN                     :1;
        __IO   uint8_t  PEEN                     :1;
        __IO   uint8_t  ESCE                     :1;
        __IO   uint8_t  PFCLR                    :1;
        __IO   uint8_t  POVR                     :1;
        __IO   uint8_t  PFUL                     :1;
        __IO   uint8_t  PEMP                     :1;
} stc_adc_pccr_field_t;

typedef struct stc_adc_pcfd_fdas1_field
{
    union {
        struct {
            __IO  uint32_t  PC                   :5;
            __IO  uint32_t  RESERVED0            :3;
            __IO  uint32_t  RS                   :3;
            __IO  uint32_t  RESERVED2            :1;
            __IO  uint32_t  INVL                 :1;
            __IO  uint32_t  RESERVED3            :3;
            __IO  uint32_t  PD                   :12;
            __IO  uint32_t  RESERVED5            :4;
        };
        struct {
            __IO  uint32_t  PC0                  :1;
            __IO  uint32_t  PC1                  :1;
            __IO  uint32_t  PC2                  :1;
            __IO  uint32_t  PC3                  :1;
            __IO  uint32_t  PC4                  :1;
            __IO  uint32_t  RESERVED1            :3;
            __IO  uint32_t  RS0                  :1;
            __IO  uint32_t  RS1                  :1;
            __IO  uint32_t  RS2                  :1;
            __IO  uint32_t  RESERVED4            :5;
            __IO  uint32_t  PD0                  :1;
            __IO  uint32_t  PD1                  :1;
            __IO  uint32_t  PD2                  :1;
            __IO  uint32_t  PD3                  :1;
            __IO  uint32_t  PD4                  :1;
            __IO  uint32_t  PD5                  :1;
            __IO  uint32_t  PD6                  :1;
            __IO  uint32_t  PD7                  :1;
            __IO  uint32_t  PD8                  :1;
            __IO  uint32_t  PD9                  :1;
            __IO  uint32_t  PD10                 :1;
            __IO  uint32_t  PD11                 :1;
            __IO  uint32_t  RESERVED6            :4;
        };
    };
} stc_adc_pcfd_fdas1_field_t;

typedef struct stc_adc_pcfd_field
{
    union {
        struct {
            __IO  uint32_t  PC                   :5;
            __IO  uint32_t  RESERVED0            :3;
            __IO  uint32_t  RS                   :3;
            __IO  uint32_t  RESERVED2            :1;
            __IO  uint32_t  INVL                 :1;
            __IO  uint32_t  RESERVED3            :7;
            __IO  uint32_t  PD                   :12;
        };
        struct {
            __IO  uint32_t  PC0                  :1;
            __IO  uint32_t  PC1                  :1;
            __IO  uint32_t  PC2                  :1;
            __IO  uint32_t  PC3                  :1;
            __IO  uint32_t  PC4                  :1;
            __IO  uint32_t  RESERVED1            :3;
            __IO  uint32_t  RS0                  :1;
            __IO  uint32_t  RS1                  :1;
            __IO  uint32_t  RS2                  :1;
            __IO  uint32_t  RESERVED4            :9;
            __IO  uint32_t  PD0                  :1;
            __IO  uint32_t  PD1                  :1;
            __IO  uint32_t  PD2                  :1;
            __IO  uint32_t  PD3                  :1;
            __IO  uint32_t  PD4                  :1;
            __IO  uint32_t  PD5                  :1;
            __IO  uint32_t  PD6                  :1;
            __IO  uint32_t  PD7                  :1;
            __IO  uint32_t  PD8                  :1;
            __IO  uint32_t  PD9                  :1;
            __IO  uint32_t  PD10                 :1;
            __IO  uint32_t  PD11                 :1;
        };
    };
} stc_adc_pcfd_field_t;

typedef struct stc_adc_pcis_field
{
    union {
        struct {
            __IO   uint8_t  P1A                  :3;
            __IO   uint8_t  P2A                  :5;
        };
        struct {
            __IO   uint8_t  P1A0                 :1;
            __IO   uint8_t  P1A1                 :1;
            __IO   uint8_t  P1A2                 :1;
            __IO   uint8_t  P2A0                 :1;
            __IO   uint8_t  P2A1                 :1;
            __IO   uint8_t  P2A2                 :1;
            __IO   uint8_t  P2A3                 :1;
            __IO   uint8_t  P2A4                 :1;
        };
    };
} stc_adc_pcis_field_t;

typedef struct stc_adc_cmpcr_field
{
    union {
        struct {
            __IO   uint8_t  CCH                  :5;
            __IO   uint8_t  CMD0                 :1;
            __IO   uint8_t  CMD1                 :1;
            __IO   uint8_t  CMPEN                :1;
        };
        struct {
            __IO   uint8_t  CCH0                 :1;
            __IO   uint8_t  CCH1                 :1;
            __IO   uint8_t  CCH2                 :1;
            __IO   uint8_t  CCH3                 :1;
            __IO   uint8_t  CCH4                 :1;
            __IO   uint8_t  RESERVED0            :3;
        };
    };
} stc_adc_cmpcr_field_t;

typedef struct stc_adc_cmpd_field
{
    union {
        struct {
            __IO  uint16_t  RESERVED0            :6;
            __IO  uint16_t  CMAD                 :10;
        };
        struct {
            __IO  uint16_t  RESERVED1            :6;
            __IO  uint16_t  CMAD0                :1;
            __IO  uint16_t  CMAD1                :1;
            __IO  uint16_t  CMAD2                :1;
            __IO  uint16_t  CMAD3                :1;
            __IO  uint16_t  CMAD4                :1;
            __IO  uint16_t  CMAD5                :1;
            __IO  uint16_t  CMAD6                :1;
            __IO  uint16_t  CMAD7                :1;
            __IO  uint16_t  CMAD8                :1;
            __IO  uint16_t  CMAD9                :1;
        };
    };
} stc_adc_cmpd_field_t;

typedef struct stc_adc_adss23_field
{
        __IO  uint16_t  TS16                     :1;
        __IO  uint16_t  TS17                     :1;
        __IO  uint16_t  TS18                     :1;
        __IO  uint16_t  TS19                     :1;
        __IO  uint16_t  TS20                     :1;
        __IO  uint16_t  TS21                     :1;
        __IO  uint16_t  TS22                     :1;
        __IO  uint16_t  TS23                     :1;
        __IO  uint16_t  TS24                     :1;
        __IO  uint16_t  TS25                     :1;
        __IO  uint16_t  TS26                     :1;
        __IO  uint16_t  TS27                     :1;
        __IO  uint16_t  TS28                     :1;
        __IO  uint16_t  TS29                     :1;
        __IO  uint16_t  TS30                     :1;
        __IO  uint16_t  TS31                     :1;
} stc_adc_adss23_field_t;

typedef struct stc_adc_adss01_field
{
        __IO  uint16_t  TS0                      :1;
        __IO  uint16_t  TS1                      :1;
        __IO  uint16_t  TS2                      :1;
        __IO  uint16_t  TS3                      :1;
        __IO  uint16_t  TS4                      :1;
        __IO  uint16_t  TS5                      :1;
        __IO  uint16_t  TS6                      :1;
        __IO  uint16_t  TS7                      :1;
        __IO  uint16_t  TS8                      :1;
        __IO  uint16_t  TS9                      :1;
        __IO  uint16_t  TS10                     :1;
        __IO  uint16_t  TS11                     :1;
        __IO  uint16_t  TS12                     :1;
        __IO  uint16_t  TS13                     :1;
        __IO  uint16_t  TS14                     :1;
        __IO  uint16_t  TS15                     :1;
} stc_adc_adss01_field_t;

typedef struct stc_adc_adst01_field
{
    union {
        struct {
            __IO  uint16_t  ST1                  :5;
            __IO  uint16_t  STX1                 :3;
            __IO  uint16_t  ST0                  :5;
            __IO  uint16_t  STX0                 :3;
        };
        struct {
            __IO  uint16_t  ST10                 :1;
            __IO  uint16_t  ST11                 :1;
            __IO  uint16_t  ST12                 :1;
            __IO  uint16_t  ST13                 :1;
            __IO  uint16_t  ST14                 :1;
            __IO  uint16_t  STX10                :1;
            __IO  uint16_t  STX11                :1;
            __IO  uint16_t  STX12                :1;
            __IO  uint16_t  ST00                 :1;
            __IO  uint16_t  ST01                 :1;
            __IO  uint16_t  ST02                 :1;
            __IO  uint16_t  ST03                 :1;
            __IO  uint16_t  ST04                 :1;
            __IO  uint16_t  STX00                :1;
            __IO  uint16_t  STX01                :1;
            __IO  uint16_t  STX02                :1;
        };
    };
} stc_adc_adst01_field_t;

typedef struct stc_adc_adct_field
{
    union {
        struct {
            __IO   uint8_t  CT                   :8;
        };
        struct {
            __IO   uint8_t  CT0                  :1;
            __IO   uint8_t  CT1                  :1;
            __IO   uint8_t  CT2                  :1;
            __IO   uint8_t  CT3                  :1;
            __IO   uint8_t  CT4                  :1;
            __IO   uint8_t  CT5                  :1;
            __IO   uint8_t  CT6                  :1;
            __IO   uint8_t  CT7                  :1;
        };
    };
} stc_adc_adct_field_t;

typedef struct stc_adc_prtsl_field
{
    union {
        struct {
            __IO   uint8_t  PRTSL                :4;
            __IO   uint8_t  RESERVED0            :4;
        };
        struct {
            __IO   uint8_t  PRTSL0               :1;
            __IO   uint8_t  PRTSL1               :1;
            __IO   uint8_t  PRTSL2               :1;
            __IO   uint8_t  PRTSL3               :1;
            __IO   uint8_t  RESERVED1            :4;
        };
    };
} stc_adc_prtsl_field_t;

typedef struct stc_adc_sctsl_field
{
    union {
        struct {
            __IO   uint8_t  SCTSL                :4;
            __IO   uint8_t  RESERVED0            :4;
        };
        struct {
            __IO   uint8_t  SCTSL0               :1;
            __IO   uint8_t  SCTSL1               :1;
            __IO   uint8_t  SCTSL2               :1;
            __IO   uint8_t  SCTSL3               :1;
            __IO   uint8_t  RESERVED1            :4;
        };
    };
} stc_adc_sctsl_field_t;

typedef struct stc_adc_adcen_field
{
    union {
        struct {
            __IO  uint16_t  ENBL                 :1;
            __IO  uint16_t  READY                :1;
            __IO  uint16_t  RESERVED0            :6;
            __IO  uint16_t  ENBLTIME             :8;
        };
        struct {
            __IO  uint16_t  RESERVED1            :8;
            __IO  uint16_t  ENBLTIME0            :1;
            __IO  uint16_t  ENBLTIME1            :1;
            __IO  uint16_t  ENBLTIME2            :1;
            __IO  uint16_t  ENBLTIME3            :1;
            __IO  uint16_t  ENBLTIME4            :1;
            __IO  uint16_t  ENBLTIME5            :1;
            __IO  uint16_t  ENBLTIME6            :1;
            __IO  uint16_t  ENBLTIME7            :1;
        };
    };
} stc_adc_adcen_field_t;

typedef struct stc_adc_calsr_field
{
    union {
        struct {
            __IO  uint32_t  OFST                 :8;
            __IO  uint32_t  CLBEN                :1;
            __IO  uint32_t  RESERVED0            :23;
        };
        struct {
            __IO  uint32_t  OFST0                :1;
            __IO  uint32_t  OFST1                :1;
            __IO  uint32_t  OFST2                :1;
            __IO  uint32_t  OFST3                :1;
            __IO  uint32_t  OFST4                :1;
            __IO  uint32_t  OFST5                :1;
            __IO  uint32_t  OFST6                :1;
            __IO  uint32_t  OFST7                :1;
            __IO  uint32_t  RESERVED1            :24;
        };
    };
} stc_adc_calsr_field_t;

typedef struct stc_adc_wcmrcot_field
{
        __IO   uint8_t  RCOOF                    :1;
        __IO   uint8_t  RESERVED0                :7;
} stc_adc_wcmrcot_field_t;

typedef struct stc_adc_wcmrcif_field
{
        __IO   uint8_t  RCINT                    :1;
        __IO   uint8_t  RESERVED0                :7;
} stc_adc_wcmrcif_field_t;

typedef struct stc_adc_wcmpcr_field
{
    union {
        struct {
            __IO   uint8_t  RESERVED0            :2;
            __IO   uint8_t  RCOE                 :1;
            __IO   uint8_t  RCOIE                :1;
            __IO   uint8_t  RCOIRS               :1;
            __IO   uint8_t  RCOCD                :3;
        };
        struct {
            __IO   uint8_t  RESERVED1            :5;
            __IO   uint8_t  RCOCD0               :1;
            __IO   uint8_t  RCOCD1               :1;
            __IO   uint8_t  RCOCD2               :1;
        };
    };
} stc_adc_wcmpcr_field_t;

typedef struct stc_adc_wcmpsr_field
{
    union {
        struct {
            __IO   uint8_t  WCCH                 :5;
            __IO   uint8_t  WCMD                 :1;
            __IO   uint8_t  RESERVED0            :2;
        };
        struct {
            __IO   uint8_t  WCCH0                :1;
            __IO   uint8_t  WCCH1                :1;
            __IO   uint8_t  WCCH2                :1;
            __IO   uint8_t  WCCH3                :1;
            __IO   uint8_t  WCCH4                :1;
            __IO   uint8_t  RESERVED1            :3;
        };
    };
} stc_adc_wcmpsr_field_t;

typedef struct stc_adc_wcmpdl_field
{
    union {
        struct {
            __IO  uint16_t  RESERVED0            :6;
            __IO  uint16_t  CMLD                 :10;
        };
        struct {
            __IO  uint16_t  RESERVED1            :6;
            __IO  uint16_t  CMLD0                :1;
            __IO  uint16_t  CMLD1                :1;
            __IO  uint16_t  CMLD2                :1;
            __IO  uint16_t  CMLD3                :1;
            __IO  uint16_t  CMLD4                :1;
            __IO  uint16_t  CMLD5                :1;
            __IO  uint16_t  CMLD6                :1;
            __IO  uint16_t  CMLD7                :1;
            __IO  uint16_t  CMLD8                :1;
            __IO  uint16_t  CMLD9                :1;
        };
    };
} stc_adc_wcmpdl_field_t;

typedef struct stc_adc_wcmpdh_field
{
    union {
        struct {
            __IO  uint16_t  RESERVED0            :6;
            __IO  uint16_t  CMHD                 :10;
        };
        struct {
            __IO  uint16_t  RESERVED1            :6;
            __IO  uint16_t  CMHD0                :1;
            __IO  uint16_t  CMHD1                :1;
            __IO  uint16_t  CMHD2                :1;
            __IO  uint16_t  CMHD3                :1;
            __IO  uint16_t  CMHD4                :1;
            __IO  uint16_t  CMHD5                :1;
            __IO  uint16_t  CMHD6                :1;
            __IO  uint16_t  CMHD7                :1;
            __IO  uint16_t  CMHD8                :1;
            __IO  uint16_t  CMHD9                :1;
        };
    };
} stc_adc_wcmpdh_field_t;

/*******************************************************************************
* BT_MODULE
*******************************************************************************/
typedef struct stc_bt_tmcr_field
{
    union {
        union {
            struct {
                __IO  uint16_t  STRG             :1;
                __IO  uint16_t  CTEN             :1;
                __IO  uint16_t  MDSE             :1;
                __IO  uint16_t  OSEL             :1;
                __IO  uint16_t  FMD              :3;
                __IO  uint16_t  RESERVED1        :1;
                __IO  uint16_t  EGS              :2;
                __IO  uint16_t  PMSK             :1;
                __IO  uint16_t  RTGEN            :1;
                __IO  uint16_t  CKS              :3;
                __IO  uint16_t  RESERVED4        :1;
            };
            struct {
                __IO  uint16_t  RESERVED0        :4;
                __IO  uint16_t  FMD0             :1;
                __IO  uint16_t  FMD1             :1;
                __IO  uint16_t  FMD2             :1;
                __IO  uint16_t  RESERVED2        :1;
                __IO  uint16_t  EGS0             :1;
                __IO  uint16_t  EGS1             :1;
                __IO  uint16_t  RESERVED3        :2;
                __IO  uint16_t  CKS0             :1;
                __IO  uint16_t  CKS1             :1;
                __IO  uint16_t  CKS2             :1;
                __IO  uint16_t  RESERVED5        :1;
            };
        };
        union {
            struct {
                __IO  uint16_t  RESERVED6        :7;
                __IO  uint16_t  T32              :1;
                __IO  uint16_t  RESERVED7        :8;
            };
            struct {
                __IO  uint16_t  RESERVED8        :16;
            };
        };
    };
} stc_bt_tmcr_field_t;

typedef struct stc_bt_stc_field
{
    union {
        struct {
            __IO   uint8_t  UDIR                 :1;
            __IO   uint8_t  RESERVED0            :1;
            __IO   uint8_t  TGIR                 :1;
            __IO   uint8_t  RESERVED1            :1;
            __IO   uint8_t  UDIE                 :1;
            __IO   uint8_t  RESERVED2            :1;
            __IO   uint8_t  TGIE                 :1;
            __IO   uint8_t  RESERVED3            :1;
        };
        struct {
            __IO   uint8_t  OVIR                 :1;
            __IO   uint8_t  RESERVED5            :1;
            __IO   uint8_t  EDIR                 :1;
            __IO   uint8_t  RESERVED6            :1;
            __IO   uint8_t  OVIE                 :1;
            __IO   uint8_t  RESERVED7            :1;
            __IO   uint8_t  EDIE                 :1;
            __IO   uint8_t  ERR                  :1;
        };
        struct {
            __IO   uint8_t  RESERVED9            :1;
            __IO   uint8_t  DTIR                 :1;
            __IO   uint8_t  RESERVED10           :3;
            __IO   uint8_t  DTIE                 :1;
            __IO   uint8_t  RESERVED11           :2;
        };
    };
} stc_bt_stc_field_t;

typedef struct stc_bt_tmcr2_field
{
    union {
        struct {
            __IO   uint8_t  CKS3                 :1;
            __IO   uint8_t  RESERVED0            :7;
        };
        struct {
            __IO   uint8_t  RESERVED6            :7;
            __IO   uint8_t  GATE                 :1;
        };
    };
} stc_bt_tmcr2_field_t;

typedef struct stc_bt_ppg_tmcr_field
{
    union {
        struct {
            __IO  uint16_t  STRG                 :1;
            __IO  uint16_t  CTEN                 :1;
            __IO  uint16_t  MDSE                 :1;
            __IO  uint16_t  OSEL                 :1;
            __IO  uint16_t  FMD                  :3;
            __IO  uint16_t  RESERVED1            :1;
            __IO  uint16_t  EGS                  :2;
            __IO  uint16_t  PMSK                 :1;
            __IO  uint16_t  RTGEN                :1;
            __IO  uint16_t  CKS                  :3;
            __IO  uint16_t  RESERVED4            :1;
        };
        struct {
            __IO  uint16_t  RESERVED0            :4;
            __IO  uint16_t  FMD0                 :1;
            __IO  uint16_t  FMD1                 :1;
            __IO  uint16_t  FMD2                 :1;
            __IO  uint16_t  RESERVED2            :1;
            __IO  uint16_t  EGS0                 :1;
            __IO  uint16_t  EGS1                 :1;
            __IO  uint16_t  RESERVED3            :2;
            __IO  uint16_t  CKS0                 :1;
            __IO  uint16_t  CKS1                 :1;
            __IO  uint16_t  CKS2                 :1;
            __IO  uint16_t  RESERVED5            :1;
        };
    };
} stc_bt_ppg_tmcr_field_t;

typedef struct stc_bt_pwc_tmcr_field
{
    union {
        struct {
            __IO  uint16_t  RESERVED6            :1;
            __IO  uint16_t  CTEN                 :1;
            __IO  uint16_t  MDSE                 :1;
            __IO  uint16_t  RESERVED7            :1;
            __IO  uint16_t  FMD                  :3;
            __IO  uint16_t  T32                  :1;
            __IO  uint16_t  EGS                  :3;
            __IO  uint16_t  RESERVED10           :1;
            __IO  uint16_t  CKS                  :3;
            __IO  uint16_t  RESERVED12           :1;
        };
        struct {
            __IO  uint16_t  RESERVED8            :4;
            __IO  uint16_t  FMD0                 :1;
            __IO  uint16_t  FMD1                 :1;
            __IO  uint16_t  FMD2                 :1;
            __IO  uint16_t  RESERVED9            :1;
            __IO  uint16_t  EGS0                 :1;
            __IO  uint16_t  EGS1                 :1;
            __IO  uint16_t  EGS2                 :1;
            __IO  uint16_t  RESERVED11           :1;
            __IO  uint16_t  CKS0                 :1;
            __IO  uint16_t  CKS1                 :1;
            __IO  uint16_t  CKS2                 :1;
            __IO  uint16_t  RESERVED13           :1;
        };
    };
} stc_bt_pwc_tmcr_field_t;

typedef struct stc_bt_pwm_tmcr_field
{
    union {
        struct {
            __IO  uint16_t  STRG                 :1;
            __IO  uint16_t  CTEN                 :1;
            __IO  uint16_t  MDSE                 :1;
            __IO  uint16_t  OSEL                 :1;
            __IO  uint16_t  FMD                  :3;
            __IO  uint16_t  RESERVED15           :1;
            __IO  uint16_t  EGS                  :2;
            __IO  uint16_t  PMSK                 :1;
            __IO  uint16_t  RTGEN                :1;
            __IO  uint16_t  CKS                  :3;
            __IO  uint16_t  RESERVED18           :1;
        };
        struct {
            __IO  uint16_t  RESERVED14           :4;
            __IO  uint16_t  FMD0                 :1;
            __IO  uint16_t  FMD1                 :1;
            __IO  uint16_t  FMD2                 :1;
            __IO  uint16_t  RESERVED16           :1;
            __IO  uint16_t  EGS0                 :1;
            __IO  uint16_t  EGS1                 :1;
            __IO  uint16_t  RESERVED17           :2;
            __IO  uint16_t  CKS0                 :1;
            __IO  uint16_t  CKS1                 :1;
            __IO  uint16_t  CKS2                 :1;
            __IO  uint16_t  RESERVED19           :1;
        };
    };
} stc_bt_pwm_tmcr_field_t;

typedef struct stc_bt_rt_tmcr_field
{
    union {
        struct {
            __IO  uint16_t  STRG                 :1;
            __IO  uint16_t  CTEN                 :1;
            __IO  uint16_t  MDSE                 :1;
            __IO  uint16_t  OSEL                 :1;
            __IO  uint16_t  FMD                  :3;
            __IO  uint16_t  T32                  :1;
            __IO  uint16_t  EGS                  :2;
            __IO  uint16_t  RESERVED22           :2;
            __IO  uint16_t  CKS                  :3;
            __IO  uint16_t  RESERVED24           :1;
        };
        struct {
            __IO  uint16_t  RESERVED20           :4;
            __IO  uint16_t  FMD0                 :1;
            __IO  uint16_t  FMD1                 :1;
            __IO  uint16_t  FMD2                 :1;
            __IO  uint16_t  RESERVED21           :1;
            __IO  uint16_t  EGS0                 :1;
            __IO  uint16_t  EGS1                 :1;
            __IO  uint16_t  RESERVED23           :2;
            __IO  uint16_t  CKS0                 :1;
            __IO  uint16_t  CKS1                 :1;
            __IO  uint16_t  CKS2                 :1;
            __IO  uint16_t  RESERVED25           :1;
        };
    };
} stc_bt_rt_tmcr_field_t;

typedef struct stc_bt_ppg_stc_field
{
        __IO   uint8_t  UDIR                     :1;
        __IO   uint8_t  RESERVED0                :1;
        __IO   uint8_t  TGIR                     :1;
        __IO   uint8_t  RESERVED1                :1;
        __IO   uint8_t  UDIE                     :1;
        __IO   uint8_t  RESERVED2                :1;
        __IO   uint8_t  TGIE                     :1;
        __IO   uint8_t  RESERVED3                :1;
} stc_bt_ppg_stc_field_t;

typedef struct stc_bt_pwc_stc_field
{
        __IO   uint8_t  OVIR                     :1;
        __IO   uint8_t  RESERVED5                :1;
        __IO   uint8_t  EDIR                     :1;
        __IO   uint8_t  RESERVED6                :1;
        __IO   uint8_t  OVIE                     :1;
        __IO   uint8_t  RESERVED7                :1;
        __IO   uint8_t  EDIE                     :1;
        __IO   uint8_t  ERR                      :1;
} stc_bt_pwc_stc_field_t;

typedef struct stc_bt_pwm_stc_field
{
        __IO   uint8_t  UDIR                     :1;
        __IO   uint8_t  DTIR                     :1;
        __IO   uint8_t  TGIR                     :1;
        __IO   uint8_t  RESERVED9                :1;
        __IO   uint8_t  UDIE                     :1;
        __IO   uint8_t  DTIE                     :1;
        __IO   uint8_t  TGIE                     :1;
        __IO   uint8_t  RESERVED10               :1;
} stc_bt_pwm_stc_field_t;

typedef struct stc_bt_rt_stc_field
{
        __IO   uint8_t  UDIR                     :1;
        __IO   uint8_t  RESERVED12               :1;
        __IO   uint8_t  TGIR                     :1;
        __IO   uint8_t  RESERVED13               :1;
        __IO   uint8_t  UDIE                     :1;
        __IO   uint8_t  RESERVED14               :1;
        __IO   uint8_t  TGIE                     :1;
        __IO   uint8_t  RESERVED15               :1;
} stc_bt_rt_stc_field_t;

typedef struct stc_bt_ppg_tmcr2_field
{
        __IO   uint8_t  CKS3                     :1;
        __IO   uint8_t  RESERVED0                :7;
} stc_bt_ppg_tmcr2_field_t;

typedef struct stc_bt_pwc_tmcr2_field
{
        __IO   uint8_t  CKS3                     :1;
        __IO   uint8_t  RESERVED2                :7;
} stc_bt_pwc_tmcr2_field_t;

typedef struct stc_bt_pwm_tmcr2_field
{
        __IO   uint8_t  CKS3                     :1;
        __IO   uint8_t  RESERVED4                :7;
} stc_bt_pwm_tmcr2_field_t;

typedef struct stc_bt_rt_tmcr2_field
{
        __IO   uint8_t  CKS3                     :1;
        __IO   uint8_t  RESERVED6                :6;
        __IO   uint8_t  GATE                     :1;
} stc_bt_rt_tmcr2_field_t;

/*******************************************************************************
* BTIOSEL03_MODULE
*******************************************************************************/
typedef struct stc_btiosel03_btsel0123_field
{
    union {
        struct {
            __IO   uint8_t  SEL01                :4;
            __IO   uint8_t  SEL23                :4;
        };
        struct {
            __IO   uint8_t  SEL010               :1;
            __IO   uint8_t  SEL011               :1;
            __IO   uint8_t  SEL012               :1;
            __IO   uint8_t  SEL013               :1;
            __IO   uint8_t  SEL230               :1;
            __IO   uint8_t  SEL231               :1;
            __IO   uint8_t  SEL232               :1;
            __IO   uint8_t  SEL233               :1;
        };
    };
} stc_btiosel03_btsel0123_field_t;

/*******************************************************************************
* BTIOSEL47_MODULE
*******************************************************************************/
typedef struct stc_btiosel47_btsel4567_field
{
    union {
        struct {
            __IO   uint8_t  SEL45                :4;
            __IO   uint8_t  SEL67                :4;
        };
        struct {
            __IO   uint8_t  SEL450               :1;
            __IO   uint8_t  SEL451               :1;
            __IO   uint8_t  SEL452               :1;
            __IO   uint8_t  SEL453               :1;
            __IO   uint8_t  SEL670               :1;
            __IO   uint8_t  SEL671               :1;
            __IO   uint8_t  SEL672               :1;
            __IO   uint8_t  SEL673               :1;
        };
    };
} stc_btiosel47_btsel4567_field_t;

/*******************************************************************************
* BTIOSEL8B_MODULE
*******************************************************************************/
typedef struct stc_btiosel8b_btsel89ab_field
{
    union {
        struct {
            __IO   uint8_t  SEL89                :4;
            __IO   uint8_t  SELAB                :4;
        };
        struct {
            __IO   uint8_t  SEL890               :1;
            __IO   uint8_t  SEL891               :1;
            __IO   uint8_t  SEL892               :1;
            __IO   uint8_t  SEL893               :1;
            __IO   uint8_t  SELAB0               :1;
            __IO   uint8_t  SELAB1               :1;
            __IO   uint8_t  SELAB2               :1;
            __IO   uint8_t  SELAB3               :1;
        };
    };
} stc_btiosel8b_btsel89ab_field_t;

/*******************************************************************************
* BTIOSELCF_MODULE
*******************************************************************************/
typedef struct stc_btioselcf_btselcdef_field
{
    union {
        struct {
            __IO   uint8_t  SELCD                :4;
            __IO   uint8_t  SELEF                :4;
        };
        struct {
            __IO   uint8_t  SELCD0               :1;
            __IO   uint8_t  SELCD1               :1;
            __IO   uint8_t  SELCD2               :1;
            __IO   uint8_t  SELCD3               :1;
            __IO   uint8_t  SELEF0               :1;
            __IO   uint8_t  SELEF1               :1;
            __IO   uint8_t  SELEF2               :1;
            __IO   uint8_t  SELEF3               :1;
        };
    };
} stc_btioselcf_btselcdef_field_t;

/*******************************************************************************
* CAN_MODULE
*******************************************************************************/
typedef struct stc_can_ctrlr_field
{
        __IO  uint16_t  INIT                     :1;
        __IO  uint16_t  IE                       :1;
        __IO  uint16_t  SIE                      :1;
        __IO  uint16_t  EIE                      :1;
        __IO  uint16_t  RESERVED0                :1;
        __IO  uint16_t  DAR                      :1;
        __IO  uint16_t  CCE                      :1;
        __IO  uint16_t  TEST                     :1;
        __IO  uint16_t  RESERVED1                :8;
} stc_can_ctrlr_field_t;

typedef struct stc_can_statr_field
{
    union {
        struct {
            __IO  uint16_t  LEC                  :3;
            __IO  uint16_t  TXOK                 :1;
            __IO  uint16_t  RXOK                 :1;
            __IO  uint16_t  EPASS                :1;
            __IO  uint16_t  EWARN                :1;
            __IO  uint16_t  BOFF                 :1;
            __IO  uint16_t  RESERVED0            :8;
        };
        struct {
            __IO  uint16_t  LEC0                 :1;
            __IO  uint16_t  LEC1                 :1;
            __IO  uint16_t  LEC2                 :1;
            __IO  uint16_t  RESERVED1            :13;
        };
    };
} stc_can_statr_field_t;

typedef struct stc_can_errcnt_field
{
    union {
        struct {
            __IO  uint16_t  TEC                  :8;
            __IO  uint16_t  REC                  :7;
            __IO  uint16_t  RP                   :1;
        };
        struct {
            __IO  uint16_t  TEC0                 :1;
            __IO  uint16_t  TEC1                 :1;
            __IO  uint16_t  TEC2                 :1;
            __IO  uint16_t  TEC3                 :1;
            __IO  uint16_t  TEC4                 :1;
            __IO  uint16_t  TEC5                 :1;
            __IO  uint16_t  TEC6                 :1;
            __IO  uint16_t  TEC7                 :1;
            __IO  uint16_t  REC0                 :1;
            __IO  uint16_t  REC1                 :1;
            __IO  uint16_t  REC2                 :1;
            __IO  uint16_t  REC3                 :1;
            __IO  uint16_t  REC4                 :1;
            __IO  uint16_t  REC5                 :1;
            __IO  uint16_t  REC6                 :1;
            __IO  uint16_t  RESERVED0            :1;
        };
    };
} stc_can_errcnt_field_t;

typedef struct stc_can_btr_field
{
    union {
        struct {
            __IO  uint16_t  BRP                  :6;
            __IO  uint16_t  SJW                  :2;
            __IO  uint16_t  TSEG1                :4;
            __IO  uint16_t  TSEG2                :3;
            __IO  uint16_t  RESERVED0            :1;
        };
        struct {
            __IO  uint16_t  BRP0                 :1;
            __IO  uint16_t  BRP1                 :1;
            __IO  uint16_t  BRP2                 :1;
            __IO  uint16_t  BRP3                 :1;
            __IO  uint16_t  BRP4                 :1;
            __IO  uint16_t  BRP5                 :1;
            __IO  uint16_t  SJW0                 :1;
            __IO  uint16_t  SJW1                 :1;
            __IO  uint16_t  TSEG10               :1;
            __IO  uint16_t  TSEG11               :1;
            __IO  uint16_t  TSEG12               :1;
            __IO  uint16_t  TSEG13               :1;
            __IO  uint16_t  TSEG20               :1;
            __IO  uint16_t  TSEG21               :1;
            __IO  uint16_t  TSEG22               :1;
            __IO  uint16_t  RESERVED1            :1;
        };
    };
} stc_can_btr_field_t;

typedef struct stc_can_intr_field
{
    union {
        struct {
            __IO  uint16_t  INTID                :16;
        };
        struct {
            __IO  uint16_t  INTID0               :1;
            __IO  uint16_t  INTID1               :1;
            __IO  uint16_t  INTID2               :1;
            __IO  uint16_t  INTID3               :1;
            __IO  uint16_t  INTID4               :1;
            __IO  uint16_t  INTID5               :1;
            __IO  uint16_t  INTID6               :1;
            __IO  uint16_t  INTID7               :1;
            __IO  uint16_t  INTID8               :1;
            __IO  uint16_t  INTID9               :1;
            __IO  uint16_t  INTID10              :1;
            __IO  uint16_t  INTID11              :1;
            __IO  uint16_t  INTID12              :1;
            __IO  uint16_t  INTID13              :1;
            __IO  uint16_t  INTID14              :1;
            __IO  uint16_t  INTID15              :1;
        };
    };
} stc_can_intr_field_t;

typedef struct stc_can_testr_field
{
    union {
        struct {
            __IO  uint16_t  RESERVED0            :2;
            __IO  uint16_t  BASIC                :1;
            __IO  uint16_t  SILENT               :1;
            __IO  uint16_t  LBACK                :1;
            __IO  uint16_t  TX                   :2;
            __IO  uint16_t  RX                   :1;
            __IO  uint16_t  RESERVED2            :8;
        };
        struct {
            __IO  uint16_t  RESERVED1            :5;
            __IO  uint16_t  TX0                  :1;
            __IO  uint16_t  TX1                  :1;
            __IO  uint16_t  RESERVED3            :9;
        };
    };
} stc_can_testr_field_t;

typedef struct stc_can_brper_field
{
    union {
        struct {
            __IO  uint16_t  BRPE                 :4;
            __IO  uint16_t  RESERVED0            :12;
        };
        struct {
            __IO  uint16_t  BRPE0                :1;
            __IO  uint16_t  BRPE1                :1;
            __IO  uint16_t  BRPE2                :1;
            __IO  uint16_t  BRPE3                :1;
            __IO  uint16_t  RESERVED1            :12;
        };
    };
} stc_can_brper_field_t;

typedef struct stc_can_if1creq_field
{
    union {
        struct {
            __IO  uint16_t  MESSAGENUMBER        :8;
            __IO  uint16_t  RESERVED0            :7;
            __IO  uint16_t  BUSY                 :1;
        };
        struct {
            __IO  uint16_t  MESSAGENUMBER0       :1;
            __IO  uint16_t  MESSAGENUMBER1       :1;
            __IO  uint16_t  MESSAGENUMBER2       :1;
            __IO  uint16_t  MESSAGENUMBER3       :1;
            __IO  uint16_t  MESSAGENUMBER4       :1;
            __IO  uint16_t  MESSAGENUMBER5       :1;
            __IO  uint16_t  MESSAGENUMBER6       :1;
            __IO  uint16_t  MESSAGENUMBER7       :1;
            __IO  uint16_t  RESERVED1            :8;
        };
    };
} stc_can_if1creq_field_t;

typedef struct stc_can_if1cmsk_field
{
        __IO  uint16_t  DATAB                    :1;
        __IO  uint16_t  DATAA                    :1;
        __IO  uint16_t  NEWDAT                   :1;
        __IO  uint16_t  CIP                      :1;
        __IO  uint16_t  CONTROL                  :1;
        __IO  uint16_t  ARB                      :1;
        __IO  uint16_t  MASK                     :1;
        __IO  uint16_t  WR_RD                    :1;
        __IO  uint16_t  RESERVED0                :8;
} stc_can_if1cmsk_field_t;

typedef struct stc_can_if1msk_field
{
    union {
        struct {
            __IO  uint32_t  MSK                  :29;
            __IO  uint32_t  RESERVED0            :1;
            __IO  uint32_t  MDIR                 :1;
            __IO  uint32_t  MXTD                 :1;
        };
        struct {
            __IO  uint32_t  MSK0                 :1;
            __IO  uint32_t  MSK1                 :1;
            __IO  uint32_t  MSK2                 :1;
            __IO  uint32_t  MSK3                 :1;
            __IO  uint32_t  MSK4                 :1;
            __IO  uint32_t  MSK5                 :1;
            __IO  uint32_t  MSK6                 :1;
            __IO  uint32_t  MSK7                 :1;
            __IO  uint32_t  MSK8                 :1;
            __IO  uint32_t  MSK9                 :1;
            __IO  uint32_t  MSK10                :1;
            __IO  uint32_t  MSK11                :1;
            __IO  uint32_t  MSK12                :1;
            __IO  uint32_t  MSK13                :1;
            __IO  uint32_t  MSK14                :1;
            __IO  uint32_t  MSK15                :1;
            __IO  uint32_t  MSK16                :1;
            __IO  uint32_t  MSK17                :1;
            __IO  uint32_t  MSK18                :1;
            __IO  uint32_t  MSK19                :1;
            __IO  uint32_t  MSK20                :1;
            __IO  uint32_t  MSK21                :1;
            __IO  uint32_t  MSK22                :1;
            __IO  uint32_t  MSK23                :1;
            __IO  uint32_t  MSK24                :1;
            __IO  uint32_t  MSK25                :1;
            __IO  uint32_t  MSK26                :1;
            __IO  uint32_t  MSK27                :1;
            __IO  uint32_t  MSK28                :1;
            __IO  uint32_t  RESERVED1            :3;
        };
    };
} stc_can_if1msk_field_t;

typedef struct stc_can_if1arb_field
{
    union {
        struct {
            __IO  uint32_t  ID                   :29;
            __IO  uint32_t  DIR                  :1;
            __IO  uint32_t  XTD                  :1;
            __IO  uint32_t  MSGVAL               :1;
        };
        struct {
            __IO  uint32_t  ID0                  :1;
            __IO  uint32_t  ID1                  :1;
            __IO  uint32_t  ID2                  :1;
            __IO  uint32_t  ID3                  :1;
            __IO  uint32_t  ID4                  :1;
            __IO  uint32_t  ID5                  :1;
            __IO  uint32_t  ID6                  :1;
            __IO  uint32_t  ID7                  :1;
            __IO  uint32_t  ID8                  :1;
            __IO  uint32_t  ID9                  :1;
            __IO  uint32_t  ID10                 :1;
            __IO  uint32_t  ID11                 :1;
            __IO  uint32_t  ID12                 :1;
            __IO  uint32_t  ID13                 :1;
            __IO  uint32_t  ID14                 :1;
            __IO  uint32_t  ID15                 :1;
            __IO  uint32_t  ID16                 :1;
            __IO  uint32_t  ID17                 :1;
            __IO  uint32_t  ID18                 :1;
            __IO  uint32_t  ID19                 :1;
            __IO  uint32_t  ID20                 :1;
            __IO  uint32_t  ID21                 :1;
            __IO  uint32_t  ID22                 :1;
            __IO  uint32_t  ID23                 :1;
            __IO  uint32_t  ID24                 :1;
            __IO  uint32_t  ID25                 :1;
            __IO  uint32_t  ID26                 :1;
            __IO  uint32_t  ID27                 :1;
            __IO  uint32_t  ID28                 :1;
            __IO  uint32_t  RESERVED0            :3;
        };
    };
} stc_can_if1arb_field_t;

typedef struct stc_can_if1mctr_field
{
    union {
        struct {
            __IO  uint16_t  DLC                  :4;
            __IO  uint16_t  RESERVED0            :3;
            __IO  uint16_t  EOB                  :1;
            __IO  uint16_t  TXRQST               :1;
            __IO  uint16_t  RMTEN                :1;
            __IO  uint16_t  RXIE                 :1;
            __IO  uint16_t  TXIE                 :1;
            __IO  uint16_t  UMASK                :1;
            __IO  uint16_t  INTPND               :1;
            __IO  uint16_t  MSGLST               :1;
            __IO  uint16_t  NEWDAT               :1;
        };
        struct {
            __IO  uint16_t  DLC0                 :1;
            __IO  uint16_t  DLC1                 :1;
            __IO  uint16_t  DLC2                 :1;
            __IO  uint16_t  DLC3                 :1;
            __IO  uint16_t  RESERVED1            :12;
        };
    };
} stc_can_if1mctr_field_t;

typedef struct stc_can_if1dta_l_field
{
    union {
        struct {
            __IO  uint32_t  DATA0                :8;
            __IO  uint32_t  DATA1                :8;
            __IO  uint32_t  DATA2                :8;
            __IO  uint32_t  DATA3                :8;
        };
        struct {
            __IO  uint32_t  DATA00               :1;
            __IO  uint32_t  DATA01               :1;
            __IO  uint32_t  DATA02               :1;
            __IO  uint32_t  DATA03               :1;
            __IO  uint32_t  DATA04               :1;
            __IO  uint32_t  DATA05               :1;
            __IO  uint32_t  DATA06               :1;
            __IO  uint32_t  DATA07               :1;
            __IO  uint32_t  DATA10               :1;
            __IO  uint32_t  DATA11               :1;
            __IO  uint32_t  DATA12               :1;
            __IO  uint32_t  DATA13               :1;
            __IO  uint32_t  DATA14               :1;
            __IO  uint32_t  DATA15               :1;
            __IO  uint32_t  DATA16               :1;
            __IO  uint32_t  DATA17               :1;
            __IO  uint32_t  DATA20               :1;
            __IO  uint32_t  DATA21               :1;
            __IO  uint32_t  DATA22               :1;
            __IO  uint32_t  DATA23               :1;
            __IO  uint32_t  DATA24               :1;
            __IO  uint32_t  DATA25               :1;
            __IO  uint32_t  DATA26               :1;
            __IO  uint32_t  DATA27               :1;
            __IO  uint32_t  DATA30               :1;
            __IO  uint32_t  DATA31               :1;
            __IO  uint32_t  DATA32               :1;
            __IO  uint32_t  DATA33               :1;
            __IO  uint32_t  DATA34               :1;
            __IO  uint32_t  DATA35               :1;
            __IO  uint32_t  DATA36               :1;
            __IO  uint32_t  DATA37               :1;
        };
    };
} stc_can_if1dta_l_field_t;

typedef struct stc_can_if1dtb_l_field
{
    union {
        struct {
            __IO  uint32_t  DATA4                :8;
            __IO  uint32_t  DATA5                :8;
            __IO  uint32_t  DATA6                :8;
            __IO  uint32_t  DATA7                :8;
        };
        struct {
            __IO  uint32_t  DATA40               :1;
            __IO  uint32_t  DATA41               :1;
            __IO  uint32_t  DATA42               :1;
            __IO  uint32_t  DATA43               :1;
            __IO  uint32_t  DATA44               :1;
            __IO  uint32_t  DATA45               :1;
            __IO  uint32_t  DATA46               :1;
            __IO  uint32_t  DATA47               :1;
            __IO  uint32_t  DATA50               :1;
            __IO  uint32_t  DATA51               :1;
            __IO  uint32_t  DATA52               :1;
            __IO  uint32_t  DATA53               :1;
            __IO  uint32_t  DATA54               :1;
            __IO  uint32_t  DATA55               :1;
            __IO  uint32_t  DATA56               :1;
            __IO  uint32_t  DATA57               :1;
            __IO  uint32_t  DATA60               :1;
            __IO  uint32_t  DATA61               :1;
            __IO  uint32_t  DATA62               :1;
            __IO  uint32_t  DATA63               :1;
            __IO  uint32_t  DATA64               :1;
            __IO  uint32_t  DATA65               :1;
            __IO  uint32_t  DATA66               :1;
            __IO  uint32_t  DATA67               :1;
            __IO  uint32_t  DATA70               :1;
            __IO  uint32_t  DATA71               :1;
            __IO  uint32_t  DATA72               :1;
            __IO  uint32_t  DATA73               :1;
            __IO  uint32_t  DATA74               :1;
            __IO  uint32_t  DATA75               :1;
            __IO  uint32_t  DATA76               :1;
            __IO  uint32_t  DATA77               :1;
        };
    };
} stc_can_if1dtb_l_field_t;

typedef struct stc_can_if1dta_b_field
{
    union {
        struct {
            __IO  uint32_t  DATA3                :8;
            __IO  uint32_t  DATA2                :8;
            __IO  uint32_t  DATA1                :8;
            __IO  uint32_t  DATA0                :8;
        };
        struct {
            __IO  uint32_t  DATA30               :1;
            __IO  uint32_t  DATA31               :1;
            __IO  uint32_t  DATA32               :1;
            __IO  uint32_t  DATA33               :1;
            __IO  uint32_t  DATA34               :1;
            __IO  uint32_t  DATA35               :1;
            __IO  uint32_t  DATA36               :1;
            __IO  uint32_t  DATA37               :1;
            __IO  uint32_t  DATA20               :1;
            __IO  uint32_t  DATA21               :1;
            __IO  uint32_t  DATA22               :1;
            __IO  uint32_t  DATA23               :1;
            __IO  uint32_t  DATA24               :1;
            __IO  uint32_t  DATA25               :1;
            __IO  uint32_t  DATA26               :1;
            __IO  uint32_t  DATA27               :1;
            __IO  uint32_t  DATA10               :1;
            __IO  uint32_t  DATA11               :1;
            __IO  uint32_t  DATA12               :1;
            __IO  uint32_t  DATA13               :1;
            __IO  uint32_t  DATA14               :1;
            __IO  uint32_t  DATA15               :1;
            __IO  uint32_t  DATA16               :1;
            __IO  uint32_t  DATA17               :1;
            __IO  uint32_t  DATA00               :1;
            __IO  uint32_t  DATA01               :1;
            __IO  uint32_t  DATA02               :1;
            __IO  uint32_t  DATA03               :1;
            __IO  uint32_t  DATA04               :1;
            __IO  uint32_t  DATA05               :1;
            __IO  uint32_t  DATA06               :1;
            __IO  uint32_t  DATA07               :1;
        };
    };
} stc_can_if1dta_b_field_t;

typedef struct stc_can_if1dtb_b_field
{
    union {
        struct {
            __IO  uint32_t  DATA7                :8;
            __IO  uint32_t  DATA6                :8;
            __IO  uint32_t  DATA5                :8;
            __IO  uint32_t  DATA4                :8;
        };
        struct {
            __IO  uint32_t  DATA70               :1;
            __IO  uint32_t  DATA71               :1;
            __IO  uint32_t  DATA72               :1;
            __IO  uint32_t  DATA73               :1;
            __IO  uint32_t  DATA74               :1;
            __IO  uint32_t  DATA75               :1;
            __IO  uint32_t  DATA76               :1;
            __IO  uint32_t  DATA77               :1;
            __IO  uint32_t  DATA60               :1;
            __IO  uint32_t  DATA61               :1;
            __IO  uint32_t  DATA62               :1;
            __IO  uint32_t  DATA63               :1;
            __IO  uint32_t  DATA64               :1;
            __IO  uint32_t  DATA65               :1;
            __IO  uint32_t  DATA66               :1;
            __IO  uint32_t  DATA67               :1;
            __IO  uint32_t  DATA50               :1;
            __IO  uint32_t  DATA51               :1;
            __IO  uint32_t  DATA52               :1;
            __IO  uint32_t  DATA53               :1;
            __IO  uint32_t  DATA54               :1;
            __IO  uint32_t  DATA55               :1;
            __IO  uint32_t  DATA56               :1;
            __IO  uint32_t  DATA57               :1;
            __IO  uint32_t  DATA40               :1;
            __IO  uint32_t  DATA41               :1;
            __IO  uint32_t  DATA42               :1;
            __IO  uint32_t  DATA43               :1;
            __IO  uint32_t  DATA44               :1;
            __IO  uint32_t  DATA45               :1;
            __IO  uint32_t  DATA46               :1;
            __IO  uint32_t  DATA47               :1;
        };
    };
} stc_can_if1dtb_b_field_t;

typedef struct stc_can_if2creq_field
{
    union {
        struct {
            __IO  uint16_t  MESSAGENUMBER        :8;
            __IO  uint16_t  RESERVED0            :7;
            __IO  uint16_t  BUSY                 :1;
        };
        struct {
            __IO  uint16_t  MESSAGENUMBER0       :1;
            __IO  uint16_t  MESSAGENUMBER1       :1;
            __IO  uint16_t  MESSAGENUMBER2       :1;
            __IO  uint16_t  MESSAGENUMBER3       :1;
            __IO  uint16_t  MESSAGENUMBER4       :1;
            __IO  uint16_t  MESSAGENUMBER5       :1;
            __IO  uint16_t  MESSAGENUMBER6       :1;
            __IO  uint16_t  MESSAGENUMBER7       :1;
            __IO  uint16_t  RESERVED1            :8;
        };
    };
} stc_can_if2creq_field_t;

typedef struct stc_can_if2cmsk_field
{
        __IO  uint16_t  DATAB                    :1;
        __IO  uint16_t  DATAA                    :1;
        __IO  uint16_t  NEWDAT                   :1;
        __IO  uint16_t  CIP                      :1;
        __IO  uint16_t  CONTROL                  :1;
        __IO  uint16_t  ARB                      :1;
        __IO  uint16_t  MASK                     :1;
        __IO  uint16_t  WR_RD                    :1;
        __IO  uint16_t  RESERVED0                :8;
} stc_can_if2cmsk_field_t;

typedef struct stc_can_if2msk_field
{
    union {
        struct {
            __IO  uint32_t  MSK                  :29;
            __IO  uint32_t  RESERVED0            :1;
            __IO  uint32_t  MDIR                 :1;
            __IO  uint32_t  MXTD                 :1;
        };
        struct {
            __IO  uint32_t  MSK0                 :1;
            __IO  uint32_t  MSK1                 :1;
            __IO  uint32_t  MSK2                 :1;
            __IO  uint32_t  MSK3                 :1;
            __IO  uint32_t  MSK4                 :1;
            __IO  uint32_t  MSK5                 :1;
            __IO  uint32_t  MSK6                 :1;
            __IO  uint32_t  MSK7                 :1;
            __IO  uint32_t  MSK8                 :1;
            __IO  uint32_t  MSK9                 :1;
            __IO  uint32_t  MSK10                :1;
            __IO  uint32_t  MSK11                :1;
            __IO  uint32_t  MSK12                :1;
            __IO  uint32_t  MSK13                :1;
            __IO  uint32_t  MSK14                :1;
            __IO  uint32_t  MSK15                :1;
            __IO  uint32_t  MSK16                :1;
            __IO  uint32_t  MSK17                :1;
            __IO  uint32_t  MSK18                :1;
            __IO  uint32_t  MSK19                :1;
            __IO  uint32_t  MSK20                :1;
            __IO  uint32_t  MSK21                :1;
            __IO  uint32_t  MSK22                :1;
            __IO  uint32_t  MSK23                :1;
            __IO  uint32_t  MSK24                :1;
            __IO  uint32_t  MSK25                :1;
            __IO  uint32_t  MSK26                :1;
            __IO  uint32_t  MSK27                :1;
            __IO  uint32_t  MSK28                :1;
            __IO  uint32_t  RESERVED1            :3;
        };
    };
} stc_can_if2msk_field_t;

typedef struct stc_can_if2arb_field
{
    union {
        struct {
            __IO  uint32_t  ID                   :29;
            __IO  uint32_t  DIR                  :1;
            __IO  uint32_t  XTD                  :1;
            __IO  uint32_t  MSGVAL               :1;
        };
        struct {
            __IO  uint32_t  ID0                  :1;
            __IO  uint32_t  ID1                  :1;
            __IO  uint32_t  ID2                  :1;
            __IO  uint32_t  ID3                  :1;
            __IO  uint32_t  ID4                  :1;
            __IO  uint32_t  ID5                  :1;
            __IO  uint32_t  ID6                  :1;
            __IO  uint32_t  ID7                  :1;
            __IO  uint32_t  ID8                  :1;
            __IO  uint32_t  ID9                  :1;
            __IO  uint32_t  ID10                 :1;
            __IO  uint32_t  ID11                 :1;
            __IO  uint32_t  ID12                 :1;
            __IO  uint32_t  ID13                 :1;
            __IO  uint32_t  ID14                 :1;
            __IO  uint32_t  ID15                 :1;
            __IO  uint32_t  ID16                 :1;
            __IO  uint32_t  ID17                 :1;
            __IO  uint32_t  ID18                 :1;
            __IO  uint32_t  ID19                 :1;
            __IO  uint32_t  ID20                 :1;
            __IO  uint32_t  ID21                 :1;
            __IO  uint32_t  ID22                 :1;
            __IO  uint32_t  ID23                 :1;
            __IO  uint32_t  ID24                 :1;
            __IO  uint32_t  ID25                 :1;
            __IO  uint32_t  ID26                 :1;
            __IO  uint32_t  ID27                 :1;
            __IO  uint32_t  ID28                 :1;
            __IO  uint32_t  RESERVED0            :3;
        };
    };
} stc_can_if2arb_field_t;

typedef struct stc_can_if2mctr_field
{
    union {
        struct {
            __IO  uint16_t  DLC                  :4;
            __IO  uint16_t  RESERVED0            :3;
            __IO  uint16_t  EOB                  :1;
            __IO  uint16_t  TXRQST               :1;
            __IO  uint16_t  RMTEN                :1;
            __IO  uint16_t  RXIE                 :1;
            __IO  uint16_t  TXIE                 :1;
            __IO  uint16_t  UMASK                :1;
            __IO  uint16_t  INTPND               :1;
            __IO  uint16_t  MSGLST               :1;
            __IO  uint16_t  NEWDAT               :1;
        };
        struct {
            __IO  uint16_t  DLC0                 :1;
            __IO  uint16_t  DLC1                 :1;
            __IO  uint16_t  DLC2                 :1;
            __IO  uint16_t  DLC3                 :1;
            __IO  uint16_t  RESERVED1            :12;
        };
    };
} stc_can_if2mctr_field_t;

typedef struct stc_can_if2dta_l_field
{
    union {
        struct {
            __IO  uint32_t  DATA0                :8;
            __IO  uint32_t  DATA1                :8;
            __IO  uint32_t  DATA2                :8;
            __IO  uint32_t  DATA3                :8;
        };
        struct {
            __IO  uint32_t  DATA00               :1;
            __IO  uint32_t  DATA01               :1;
            __IO  uint32_t  DATA02               :1;
            __IO  uint32_t  DATA03               :1;
            __IO  uint32_t  DATA04               :1;
            __IO  uint32_t  DATA05               :1;
            __IO  uint32_t  DATA06               :1;
            __IO  uint32_t  DATA07               :1;
            __IO  uint32_t  DATA10               :1;
            __IO  uint32_t  DATA11               :1;
            __IO  uint32_t  DATA12               :1;
            __IO  uint32_t  DATA13               :1;
            __IO  uint32_t  DATA14               :1;
            __IO  uint32_t  DATA15               :1;
            __IO  uint32_t  DATA16               :1;
            __IO  uint32_t  DATA17               :1;
            __IO  uint32_t  DATA20               :1;
            __IO  uint32_t  DATA21               :1;
            __IO  uint32_t  DATA22               :1;
            __IO  uint32_t  DATA23               :1;
            __IO  uint32_t  DATA24               :1;
            __IO  uint32_t  DATA25               :1;
            __IO  uint32_t  DATA26               :1;
            __IO  uint32_t  DATA27               :1;
            __IO  uint32_t  DATA30               :1;
            __IO  uint32_t  DATA31               :1;
            __IO  uint32_t  DATA32               :1;
            __IO  uint32_t  DATA33               :1;
            __IO  uint32_t  DATA34               :1;
            __IO  uint32_t  DATA35               :1;
            __IO  uint32_t  DATA36               :1;
            __IO  uint32_t  DATA37               :1;
        };
    };
} stc_can_if2dta_l_field_t;

typedef struct stc_can_if2dtb_l_field
{
    union {
        struct {
            __IO  uint32_t  DATA4                :8;
            __IO  uint32_t  DATA5                :8;
            __IO  uint32_t  DATA6                :8;
            __IO  uint32_t  DATA7                :8;
        };
        struct {
            __IO  uint32_t  DATA40               :1;
            __IO  uint32_t  DATA41               :1;
            __IO  uint32_t  DATA42               :1;
            __IO  uint32_t  DATA43               :1;
            __IO  uint32_t  DATA44               :1;
            __IO  uint32_t  DATA45               :1;
            __IO  uint32_t  DATA46               :1;
            __IO  uint32_t  DATA47               :1;
            __IO  uint32_t  DATA50               :1;
            __IO  uint32_t  DATA51               :1;
            __IO  uint32_t  DATA52               :1;
            __IO  uint32_t  DATA53               :1;
            __IO  uint32_t  DATA54               :1;
            __IO  uint32_t  DATA55               :1;
            __IO  uint32_t  DATA56               :1;
            __IO  uint32_t  DATA57               :1;
            __IO  uint32_t  DATA60               :1;
            __IO  uint32_t  DATA61               :1;
            __IO  uint32_t  DATA62               :1;
            __IO  uint32_t  DATA63               :1;
            __IO  uint32_t  DATA64               :1;
            __IO  uint32_t  DATA65               :1;
            __IO  uint32_t  DATA66               :1;
            __IO  uint32_t  DATA67               :1;
            __IO  uint32_t  DATA70               :1;
            __IO  uint32_t  DATA71               :1;
            __IO  uint32_t  DATA72               :1;
            __IO  uint32_t  DATA73               :1;
            __IO  uint32_t  DATA74               :1;
            __IO  uint32_t  DATA75               :1;
            __IO  uint32_t  DATA76               :1;
            __IO  uint32_t  DATA77               :1;
        };
    };
} stc_can_if2dtb_l_field_t;

typedef struct stc_can_if2dta_b_field
{
    union {
        struct {
            __IO  uint32_t  DATA3                :8;
            __IO  uint32_t  DATA2                :8;
            __IO  uint32_t  DATA1                :8;
            __IO  uint32_t  DATA0                :8;
        };
        struct {
            __IO  uint32_t  DATA30               :1;
            __IO  uint32_t  DATA31               :1;
            __IO  uint32_t  DATA32               :1;
            __IO  uint32_t  DATA33               :1;
            __IO  uint32_t  DATA34               :1;
            __IO  uint32_t  DATA35               :1;
            __IO  uint32_t  DATA36               :1;
            __IO  uint32_t  DATA37               :1;
            __IO  uint32_t  DATA20               :1;
            __IO  uint32_t  DATA21               :1;
            __IO  uint32_t  DATA22               :1;
            __IO  uint32_t  DATA23               :1;
            __IO  uint32_t  DATA24               :1;
            __IO  uint32_t  DATA25               :1;
            __IO  uint32_t  DATA26               :1;
            __IO  uint32_t  DATA27               :1;
            __IO  uint32_t  DATA10               :1;
            __IO  uint32_t  DATA11               :1;
            __IO  uint32_t  DATA12               :1;
            __IO  uint32_t  DATA13               :1;
            __IO  uint32_t  DATA14               :1;
            __IO  uint32_t  DATA15               :1;
            __IO  uint32_t  DATA16               :1;
            __IO  uint32_t  DATA17               :1;
            __IO  uint32_t  DATA00               :1;
            __IO  uint32_t  DATA01               :1;
            __IO  uint32_t  DATA02               :1;
            __IO  uint32_t  DATA03               :1;
            __IO  uint32_t  DATA04               :1;
            __IO  uint32_t  DATA05               :1;
            __IO  uint32_t  DATA06               :1;
            __IO  uint32_t  DATA07               :1;
        };
    };
} stc_can_if2dta_b_field_t;

typedef struct stc_can_if2dtb_b_field
{
    union {
        struct {
            __IO  uint32_t  DATA7                :8;
            __IO  uint32_t  DATA6                :8;
            __IO  uint32_t  DATA5                :8;
            __IO  uint32_t  DATA4                :8;
        };
        struct {
            __IO  uint32_t  DATA70               :1;
            __IO  uint32_t  DATA71               :1;
            __IO  uint32_t  DATA72               :1;
            __IO  uint32_t  DATA73               :1;
            __IO  uint32_t  DATA74               :1;
            __IO  uint32_t  DATA75               :1;
            __IO  uint32_t  DATA76               :1;
            __IO  uint32_t  DATA77               :1;
            __IO  uint32_t  DATA60               :1;
            __IO  uint32_t  DATA61               :1;
            __IO  uint32_t  DATA62               :1;
            __IO  uint32_t  DATA63               :1;
            __IO  uint32_t  DATA64               :1;
            __IO  uint32_t  DATA65               :1;
            __IO  uint32_t  DATA66               :1;
            __IO  uint32_t  DATA67               :1;
            __IO  uint32_t  DATA50               :1;
            __IO  uint32_t  DATA51               :1;
            __IO  uint32_t  DATA52               :1;
            __IO  uint32_t  DATA53               :1;
            __IO  uint32_t  DATA54               :1;
            __IO  uint32_t  DATA55               :1;
            __IO  uint32_t  DATA56               :1;
            __IO  uint32_t  DATA57               :1;
            __IO  uint32_t  DATA40               :1;
            __IO  uint32_t  DATA41               :1;
            __IO  uint32_t  DATA42               :1;
            __IO  uint32_t  DATA43               :1;
            __IO  uint32_t  DATA44               :1;
            __IO  uint32_t  DATA45               :1;
            __IO  uint32_t  DATA46               :1;
            __IO  uint32_t  DATA47               :1;
        };
    };
} stc_can_if2dtb_b_field_t;

typedef struct stc_can_treqr_field
{
        __IO  uint32_t  TXRQST1                  :1;
        __IO  uint32_t  TXRQST2                  :1;
        __IO  uint32_t  TXRQST3                  :1;
        __IO  uint32_t  TXRQST4                  :1;
        __IO  uint32_t  TXRQST5                  :1;
        __IO  uint32_t  TXRQST6                  :1;
        __IO  uint32_t  TXRQST7                  :1;
        __IO  uint32_t  TXRQST8                  :1;
        __IO  uint32_t  TXRQST9                  :1;
        __IO  uint32_t  TXRQST10                 :1;
        __IO  uint32_t  TXRQST11                 :1;
        __IO  uint32_t  TXRQST12                 :1;
        __IO  uint32_t  TXRQST13                 :1;
        __IO  uint32_t  TXRQST14                 :1;
        __IO  uint32_t  TXRQST15                 :1;
        __IO  uint32_t  TXRQST16                 :1;
        __IO  uint32_t  TXRQST17                 :1;
        __IO  uint32_t  TXRQST18                 :1;
        __IO  uint32_t  TXRQST19                 :1;
        __IO  uint32_t  TXRQST20                 :1;
        __IO  uint32_t  TXRQST21                 :1;
        __IO  uint32_t  TXRQST22                 :1;
        __IO  uint32_t  TXRQST23                 :1;
        __IO  uint32_t  TXRQST24                 :1;
        __IO  uint32_t  TXRQST25                 :1;
        __IO  uint32_t  TXRQST26                 :1;
        __IO  uint32_t  TXRQST27                 :1;
        __IO  uint32_t  TXRQST28                 :1;
        __IO  uint32_t  TXRQST29                 :1;
        __IO  uint32_t  TXRQST30                 :1;
        __IO  uint32_t  TXRQST31                 :1;
        __IO  uint32_t  TXRQST32                 :1;
} stc_can_treqr_field_t;

typedef struct stc_can_newdt_field
{
        __IO  uint32_t  NEWDAT1                  :1;
        __IO  uint32_t  NEWDAT2                  :1;
        __IO  uint32_t  NEWDAT3                  :1;
        __IO  uint32_t  NEWDAT4                  :1;
        __IO  uint32_t  NEWDAT5                  :1;
        __IO  uint32_t  NEWDAT6                  :1;
        __IO  uint32_t  NEWDAT7                  :1;
        __IO  uint32_t  NEWDAT8                  :1;
        __IO  uint32_t  NEWDAT9                  :1;
        __IO  uint32_t  NEWDAT10                 :1;
        __IO  uint32_t  NEWDAT11                 :1;
        __IO  uint32_t  NEWDAT12                 :1;
        __IO  uint32_t  NEWDAT13                 :1;
        __IO  uint32_t  NEWDAT14                 :1;
        __IO  uint32_t  NEWDAT15                 :1;
        __IO  uint32_t  NEWDAT16                 :1;
        __IO  uint32_t  NEWDAT17                 :1;
        __IO  uint32_t  NEWDAT18                 :1;
        __IO  uint32_t  NEWDAT19                 :1;
        __IO  uint32_t  NEWDAT20                 :1;
        __IO  uint32_t  NEWDAT21                 :1;
        __IO  uint32_t  NEWDAT22                 :1;
        __IO  uint32_t  NEWDAT23                 :1;
        __IO  uint32_t  NEWDAT24                 :1;
        __IO  uint32_t  NEWDAT25                 :1;
        __IO  uint32_t  NEWDAT26                 :1;
        __IO  uint32_t  NEWDAT27                 :1;
        __IO  uint32_t  NEWDAT28                 :1;
        __IO  uint32_t  NEWDAT29                 :1;
        __IO  uint32_t  NEWDAT30                 :1;
        __IO  uint32_t  NEWDAT31                 :1;
        __IO  uint32_t  NEWDAT32                 :1;
} stc_can_newdt_field_t;

typedef struct stc_can_intpnd_field
{
        __IO  uint32_t  INTPND1                  :1;
        __IO  uint32_t  INTPND2                  :1;
        __IO  uint32_t  INTPND3                  :1;
        __IO  uint32_t  INTPND4                  :1;
        __IO  uint32_t  INTPND5                  :1;
        __IO  uint32_t  INTPND6                  :1;
        __IO  uint32_t  INTPND7                  :1;
        __IO  uint32_t  INTPND8                  :1;
        __IO  uint32_t  INTPND9                  :1;
        __IO  uint32_t  INTPND10                 :1;
        __IO  uint32_t  INTPND11                 :1;
        __IO  uint32_t  INTPND12                 :1;
        __IO  uint32_t  INTPND13                 :1;
        __IO  uint32_t  INTPND14                 :1;
        __IO  uint32_t  INTPND15                 :1;
        __IO  uint32_t  INTPND16                 :1;
        __IO  uint32_t  INTPND17                 :1;
        __IO  uint32_t  INTPND18                 :1;
        __IO  uint32_t  INTPND19                 :1;
        __IO  uint32_t  INTPND20                 :1;
        __IO  uint32_t  INTPND21                 :1;
        __IO  uint32_t  INTPND22                 :1;
        __IO  uint32_t  INTPND23                 :1;
        __IO  uint32_t  INTPND24                 :1;
        __IO  uint32_t  INTPND25                 :1;
        __IO  uint32_t  INTPND26                 :1;
        __IO  uint32_t  INTPND27                 :1;
        __IO  uint32_t  INTPND28                 :1;
        __IO  uint32_t  INTPND29                 :1;
        __IO  uint32_t  INTPND30                 :1;
        __IO  uint32_t  INTPND31                 :1;
        __IO  uint32_t  INTPND32                 :1;
} stc_can_intpnd_field_t;

typedef struct stc_can_msgval_field
{
        __IO  uint32_t  MSGVAL1                  :1;
        __IO  uint32_t  MSGVAL2                  :1;
        __IO  uint32_t  MSGVAL3                  :1;
        __IO  uint32_t  MSGVAL4                  :1;
        __IO  uint32_t  MSGVAL5                  :1;
        __IO  uint32_t  MSGVAL6                  :1;
        __IO  uint32_t  MSGVAL7                  :1;
        __IO  uint32_t  MSGVAL8                  :1;
        __IO  uint32_t  MSGVAL9                  :1;
        __IO  uint32_t  MSGVAL10                 :1;
        __IO  uint32_t  MSGVAL11                 :1;
        __IO  uint32_t  MSGVAL12                 :1;
        __IO  uint32_t  MSGVAL13                 :1;
        __IO  uint32_t  MSGVAL14                 :1;
        __IO  uint32_t  MSGVAL15                 :1;
        __IO  uint32_t  MSGVAL16                 :1;
        __IO  uint32_t  MSGVAL17                 :1;
        __IO  uint32_t  MSGVAL18                 :1;
        __IO  uint32_t  MSGVAL19                 :1;
        __IO  uint32_t  MSGVAL20                 :1;
        __IO  uint32_t  MSGVAL21                 :1;
        __IO  uint32_t  MSGVAL22                 :1;
        __IO  uint32_t  MSGVAL23                 :1;
        __IO  uint32_t  MSGVAL24                 :1;
        __IO  uint32_t  MSGVAL25                 :1;
        __IO  uint32_t  MSGVAL26                 :1;
        __IO  uint32_t  MSGVAL27                 :1;
        __IO  uint32_t  MSGVAL28                 :1;
        __IO  uint32_t  MSGVAL29                 :1;
        __IO  uint32_t  MSGVAL30                 :1;
        __IO  uint32_t  MSGVAL31                 :1;
        __IO  uint32_t  MSGVAL32                 :1;
} stc_can_msgval_field_t;

/*******************************************************************************
* CANFD_MODULE
*******************************************************************************/
typedef struct stc_canfd_crel_field
{
    union {
        struct {
            __IO  uint32_t  DAY                  :8;
            __IO  uint32_t  MON                  :8;
            __IO  uint32_t  YEAR                 :4;
            __IO  uint32_t  SUBSTEP              :4;
            __IO  uint32_t  STEP                 :4;
            __IO  uint32_t  REL                  :4;
        };
        struct {
            __IO  uint32_t  DAY0                 :1;
            __IO  uint32_t  DAY1                 :1;
            __IO  uint32_t  DAY2                 :1;
            __IO  uint32_t  DAY3                 :1;
            __IO  uint32_t  DAY4                 :1;
            __IO  uint32_t  DAY5                 :1;
            __IO  uint32_t  DAY6                 :1;
            __IO  uint32_t  DAY7                 :1;
            __IO  uint32_t  MON0                 :1;
            __IO  uint32_t  MON1                 :1;
            __IO  uint32_t  MON2                 :1;
            __IO  uint32_t  MON3                 :1;
            __IO  uint32_t  MON4                 :1;
            __IO  uint32_t  MON5                 :1;
            __IO  uint32_t  MON6                 :1;
            __IO  uint32_t  MON7                 :1;
            __IO  uint32_t  YEAR0                :1;
            __IO  uint32_t  YEAR1                :1;
            __IO  uint32_t  YEAR2                :1;
            __IO  uint32_t  YEAR3                :1;
            __IO  uint32_t  SUBSTEP0             :1;
            __IO  uint32_t  SUBSTEP1             :1;
            __IO  uint32_t  SUBSTEP2             :1;
            __IO  uint32_t  SUBSTEP3             :1;
            __IO  uint32_t  STEP0                :1;
            __IO  uint32_t  STEP1                :1;
            __IO  uint32_t  STEP2                :1;
            __IO  uint32_t  STEP3                :1;
            __IO  uint32_t  REL0                 :1;
            __IO  uint32_t  REL1                 :1;
            __IO  uint32_t  REL2                 :1;
            __IO  uint32_t  REL3                 :1;
        };
    };
} stc_canfd_crel_field_t;

typedef struct stc_canfd_endn_field
{
    union {
        struct {
            __IO  uint32_t  ETV                  :32;
        };
        struct {
            __IO  uint32_t  ETV0                 :1;
            __IO  uint32_t  ETV1                 :1;
            __IO  uint32_t  ETV2                 :1;
            __IO  uint32_t  ETV3                 :1;
            __IO  uint32_t  ETV4                 :1;
            __IO  uint32_t  ETV5                 :1;
            __IO  uint32_t  ETV6                 :1;
            __IO  uint32_t  ETV7                 :1;
            __IO  uint32_t  ETV8                 :1;
            __IO  uint32_t  ETV9                 :1;
            __IO  uint32_t  ETV10                :1;
            __IO  uint32_t  ETV11                :1;
            __IO  uint32_t  ETV12                :1;
            __IO  uint32_t  ETV13                :1;
            __IO  uint32_t  ETV14                :1;
            __IO  uint32_t  ETV15                :1;
            __IO  uint32_t  ETV16                :1;
            __IO  uint32_t  ETV17                :1;
            __IO  uint32_t  ETV18                :1;
            __IO  uint32_t  ETV19                :1;
            __IO  uint32_t  ETV20                :1;
            __IO  uint32_t  ETV21                :1;
            __IO  uint32_t  ETV22                :1;
            __IO  uint32_t  ETV23                :1;
            __IO  uint32_t  ETV24                :1;
            __IO  uint32_t  ETV25                :1;
            __IO  uint32_t  ETV26                :1;
            __IO  uint32_t  ETV27                :1;
            __IO  uint32_t  ETV28                :1;
            __IO  uint32_t  ETV29                :1;
            __IO  uint32_t  ETV30                :1;
            __IO  uint32_t  ETV31                :1;
        };
    };
} stc_canfd_endn_field_t;

typedef struct stc_canfd_fbtp_field
{
    union {
        struct {
            __IO  uint32_t  FSJW                 :2;
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  FTSEG2               :3;
            __IO  uint32_t  RESERVED2            :1;
            __IO  uint32_t  FTSEG1               :4;
            __IO  uint32_t  RESERVED4            :4;
            __IO  uint32_t  FBRP                 :5;
            __IO  uint32_t  RESERVED6            :2;
            __IO  uint32_t  TDC                  :1;
            __IO  uint32_t  TDCO                 :5;
            __IO  uint32_t  RESERVED8            :3;
        };
        struct {
            __IO  uint32_t  FSJW0                :1;
            __IO  uint32_t  FSJW1                :1;
            __IO  uint32_t  RESERVED1            :2;
            __IO  uint32_t  FTSEG20              :1;
            __IO  uint32_t  FTSEG21              :1;
            __IO  uint32_t  FTSEG22              :1;
            __IO  uint32_t  RESERVED3            :1;
            __IO  uint32_t  FTSEG10              :1;
            __IO  uint32_t  FTSEG11              :1;
            __IO  uint32_t  FTSEG12              :1;
            __IO  uint32_t  FTSEG13              :1;
            __IO  uint32_t  RESERVED5            :4;
            __IO  uint32_t  FBRP0                :1;
            __IO  uint32_t  FBRP1                :1;
            __IO  uint32_t  FBRP2                :1;
            __IO  uint32_t  FBRP3                :1;
            __IO  uint32_t  FBRP4                :1;
            __IO  uint32_t  RESERVED7            :3;
            __IO  uint32_t  TDCO0                :1;
            __IO  uint32_t  TDCO1                :1;
            __IO  uint32_t  TDCO2                :1;
            __IO  uint32_t  TDCO3                :1;
            __IO  uint32_t  TDCO4                :1;
            __IO  uint32_t  RESERVED9            :3;
        };
    };
} stc_canfd_fbtp_field_t;

typedef struct stc_canfd_test_field
{
    union {
        struct {
            __IO  uint32_t  RESERVED0            :4;
            __IO  uint32_t  LBCK                 :1;
            __IO  uint32_t  TX                   :2;
            __IO  uint32_t  RX                   :1;
            __IO  uint32_t  TDCV                 :6;
            __IO  uint32_t  RESERVED3            :18;
        };
        struct {
            __IO  uint32_t  RESERVED1            :5;
            __IO  uint32_t  TX0                  :1;
            __IO  uint32_t  TX1                  :1;
            __IO  uint32_t  RESERVED2            :1;
            __IO  uint32_t  TDCV0                :1;
            __IO  uint32_t  TDCV1                :1;
            __IO  uint32_t  TDCV2                :1;
            __IO  uint32_t  TDCV3                :1;
            __IO  uint32_t  TDCV4                :1;
            __IO  uint32_t  TDCV5                :1;
            __IO  uint32_t  RESERVED4            :18;
        };
    };
} stc_canfd_test_field_t;

typedef struct stc_canfd_rwd_field
{
    union {
        struct {
            __IO  uint32_t  WDC                  :8;
            __IO  uint32_t  WDV                  :8;
            __IO  uint32_t  RESERVED0            :16;
        };
        struct {
            __IO  uint32_t  WDC0                 :1;
            __IO  uint32_t  WDC1                 :1;
            __IO  uint32_t  WDC2                 :1;
            __IO  uint32_t  WDC3                 :1;
            __IO  uint32_t  WDC4                 :1;
            __IO  uint32_t  WDC5                 :1;
            __IO  uint32_t  WDC6                 :1;
            __IO  uint32_t  WDC7                 :1;
            __IO  uint32_t  WDV0                 :1;
            __IO  uint32_t  WDV1                 :1;
            __IO  uint32_t  WDV2                 :1;
            __IO  uint32_t  WDV3                 :1;
            __IO  uint32_t  WDV4                 :1;
            __IO  uint32_t  WDV5                 :1;
            __IO  uint32_t  WDV6                 :1;
            __IO  uint32_t  WDV7                 :1;
            __IO  uint32_t  RESERVED1            :16;
        };
    };
} stc_canfd_rwd_field_t;

typedef struct stc_canfd_cccr_field
{
    union {
        struct {
            __IO  uint32_t  INIT                 :1;
            __IO  uint32_t  CCE                  :1;
            __IO  uint32_t  ASM                  :1;
            __IO  uint32_t  CSA                  :1;
            __IO  uint32_t  CSR                  :1;
            __IO  uint32_t  MON                  :1;
            __IO  uint32_t  DAR                  :1;
            __IO  uint32_t  TEST                 :1;
            __IO  uint32_t  CME                  :2;
            __IO  uint32_t  CMR                  :2;
            __IO  uint32_t  FDO                  :1;
            __IO  uint32_t  FDBS                 :1;
            __IO  uint32_t  TXP                  :1;
            __IO  uint32_t  RESERVED1            :17;
        };
        struct {
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  CME0                 :1;
            __IO  uint32_t  CME1                 :1;
            __IO  uint32_t  CMR0                 :1;
            __IO  uint32_t  CMR1                 :1;
            __IO  uint32_t  RESERVED2            :20;
        };
    };
} stc_canfd_cccr_field_t;

typedef struct stc_canfd_btp_field
{
    union {
        struct {
            __IO  uint32_t  SJW                  :4;
            __IO  uint32_t  TSEG2                :4;
            __IO  uint32_t  TSEG1                :6;
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  BRP                  :10;
            __IO  uint32_t  RESERVED2            :6;
        };
        struct {
            __IO  uint32_t  SJW0                 :1;
            __IO  uint32_t  SJW1                 :1;
            __IO  uint32_t  SJW2                 :1;
            __IO  uint32_t  SJW3                 :1;
            __IO  uint32_t  TSEG20               :1;
            __IO  uint32_t  TSEG21               :1;
            __IO  uint32_t  TSEG22               :1;
            __IO  uint32_t  TSEG23               :1;
            __IO  uint32_t  TSEG10               :1;
            __IO  uint32_t  TSEG11               :1;
            __IO  uint32_t  TSEG12               :1;
            __IO  uint32_t  TSEG13               :1;
            __IO  uint32_t  TSEG14               :1;
            __IO  uint32_t  TSEG15               :1;
            __IO  uint32_t  RESERVED1            :2;
            __IO  uint32_t  BRP0                 :1;
            __IO  uint32_t  BRP1                 :1;
            __IO  uint32_t  BRP2                 :1;
            __IO  uint32_t  BRP3                 :1;
            __IO  uint32_t  BRP4                 :1;
            __IO  uint32_t  BRP5                 :1;
            __IO  uint32_t  BRP6                 :1;
            __IO  uint32_t  BRP7                 :1;
            __IO  uint32_t  BRP8                 :1;
            __IO  uint32_t  BRP9                 :1;
            __IO  uint32_t  RESERVED3            :6;
        };
    };
} stc_canfd_btp_field_t;

typedef struct stc_canfd_tscc_field
{
    union {
        struct {
            __IO  uint32_t  TSS                  :2;
            __IO  uint32_t  RESERVED0            :14;
            __IO  uint32_t  TCP                  :4;
            __IO  uint32_t  RESERVED2            :12;
        };
        struct {
            __IO  uint32_t  TSS0                 :1;
            __IO  uint32_t  TSS1                 :1;
            __IO  uint32_t  RESERVED1            :14;
            __IO  uint32_t  TCP0                 :1;
            __IO  uint32_t  TCP1                 :1;
            __IO  uint32_t  TCP2                 :1;
            __IO  uint32_t  TCP3                 :1;
            __IO  uint32_t  RESERVED3            :12;
        };
    };
} stc_canfd_tscc_field_t;

typedef struct stc_canfd_tscv_field
{
    union {
        struct {
            __IO  uint32_t  TSC                  :16;
            __IO  uint32_t  RESERVED0            :16;
        };
        struct {
            __IO  uint32_t  TSC0                 :1;
            __IO  uint32_t  TSC1                 :1;
            __IO  uint32_t  TSC2                 :1;
            __IO  uint32_t  TSC3                 :1;
            __IO  uint32_t  TSC4                 :1;
            __IO  uint32_t  TSC5                 :1;
            __IO  uint32_t  TSC6                 :1;
            __IO  uint32_t  TSC7                 :1;
            __IO  uint32_t  TSC8                 :1;
            __IO  uint32_t  TSC9                 :1;
            __IO  uint32_t  TSC10                :1;
            __IO  uint32_t  TSC11                :1;
            __IO  uint32_t  TSC12                :1;
            __IO  uint32_t  TSC13                :1;
            __IO  uint32_t  TSC14                :1;
            __IO  uint32_t  TSC15                :1;
            __IO  uint32_t  RESERVED1            :16;
        };
    };
} stc_canfd_tscv_field_t;

typedef struct stc_canfd_tocc_field
{
    union {
        struct {
            __IO  uint32_t  ETOC                 :1;
            __IO  uint32_t  TOS                  :2;
            __IO  uint32_t  RESERVED1            :13;
            __IO  uint32_t  TOP                  :16;
        };
        struct {
            __IO  uint32_t  RESERVED0            :1;
            __IO  uint32_t  TOS0                 :1;
            __IO  uint32_t  TOS1                 :1;
            __IO  uint32_t  RESERVED2            :13;
            __IO  uint32_t  TOP0                 :1;
            __IO  uint32_t  TOP1                 :1;
            __IO  uint32_t  TOP2                 :1;
            __IO  uint32_t  TOP3                 :1;
            __IO  uint32_t  TOP4                 :1;
            __IO  uint32_t  TOP5                 :1;
            __IO  uint32_t  TOP6                 :1;
            __IO  uint32_t  TOP7                 :1;
            __IO  uint32_t  TOP8                 :1;
            __IO  uint32_t  TOP9                 :1;
            __IO  uint32_t  TOP10                :1;
            __IO  uint32_t  TOP11                :1;
            __IO  uint32_t  TOP12                :1;
            __IO  uint32_t  TOP13                :1;
            __IO  uint32_t  TOP14                :1;
            __IO  uint32_t  TOP15                :1;
        };
    };
} stc_canfd_tocc_field_t;

typedef struct stc_canfd_tocv_field
{
    union {
        struct {
            __IO  uint32_t  TOC                  :16;
            __IO  uint32_t  RESERVED0            :16;
        };
        struct {
            __IO  uint32_t  TOC0                 :1;
            __IO  uint32_t  TOC1                 :1;
            __IO  uint32_t  TOC2                 :1;
            __IO  uint32_t  TOC3                 :1;
            __IO  uint32_t  TOC4                 :1;
            __IO  uint32_t  TOC5                 :1;
            __IO  uint32_t  TOC6                 :1;
            __IO  uint32_t  TOC7                 :1;
            __IO  uint32_t  TOC8                 :1;
            __IO  uint32_t  TOC9                 :1;
            __IO  uint32_t  TOC10                :1;
            __IO  uint32_t  TOC11                :1;
            __IO  uint32_t  TOC12                :1;
            __IO  uint32_t  TOC13                :1;
            __IO  uint32_t  TOC14                :1;
            __IO  uint32_t  TOC15                :1;
            __IO  uint32_t  RESERVED1            :16;
        };
    };
} stc_canfd_tocv_field_t;

typedef struct stc_canfd_ecr_field
{
    union {
        struct {
            __IO  uint32_t  TEC                  :8;
            __IO  uint32_t  REC                  :7;
            __IO  uint32_t  RP                   :1;
            __IO  uint32_t  CEL                  :8;
            __IO  uint32_t  RESERVED1            :8;
        };
        struct {
            __IO  uint32_t  TEC0                 :1;
            __IO  uint32_t  TEC1                 :1;
            __IO  uint32_t  TEC2                 :1;
            __IO  uint32_t  TEC3                 :1;
            __IO  uint32_t  TEC4                 :1;
            __IO  uint32_t  TEC5                 :1;
            __IO  uint32_t  TEC6                 :1;
            __IO  uint32_t  TEC7                 :1;
            __IO  uint32_t  REC0                 :1;
            __IO  uint32_t  REC1                 :1;
            __IO  uint32_t  REC2                 :1;
            __IO  uint32_t  REC3                 :1;
            __IO  uint32_t  REC4                 :1;
            __IO  uint32_t  REC5                 :1;
            __IO  uint32_t  REC6                 :1;
            __IO  uint32_t  RESERVED0            :1;
            __IO  uint32_t  CEL0                 :1;
            __IO  uint32_t  CEL1                 :1;
            __IO  uint32_t  CEL2                 :1;
            __IO  uint32_t  CEL3                 :1;
            __IO  uint32_t  CEL4                 :1;
            __IO  uint32_t  CEL5                 :1;
            __IO  uint32_t  CEL6                 :1;
            __IO  uint32_t  CEL7                 :1;
            __IO  uint32_t  RESERVED2            :8;
        };
    };
} stc_canfd_ecr_field_t;

typedef struct stc_canfd_psr_field
{
    union {
        struct {
            __IO  uint32_t  LEC                  :3;
            __IO  uint32_t  ACT                  :2;
            __IO  uint32_t  EP                   :1;
            __IO  uint32_t  EW                   :1;
            __IO  uint32_t  BO                   :1;
            __IO  uint32_t  FLEC                 :3;
            __IO  uint32_t  RESI                 :1;
            __IO  uint32_t  RBRS                 :1;
            __IO  uint32_t  REDL                 :1;
            __IO  uint32_t  RESERVED1            :18;
        };
        struct {
            __IO  uint32_t  LEC0                 :1;
            __IO  uint32_t  LEC1                 :1;
            __IO  uint32_t  LEC2                 :1;
            __IO  uint32_t  ACT0                 :1;
            __IO  uint32_t  ACT1                 :1;
            __IO  uint32_t  RESERVED0            :3;
            __IO  uint32_t  FLEC0                :1;
            __IO  uint32_t  FLEC1                :1;
            __IO  uint32_t  FLEC2                :1;
            __IO  uint32_t  RESERVED2            :21;
        };
    };
} stc_canfd_psr_field_t;

typedef struct stc_canfd_ir_field
{
        __IO  uint32_t  RF0N                     :1;
        __IO  uint32_t  RF0W                     :1;
        __IO  uint32_t  RF0F                     :1;
        __IO  uint32_t  RF0L                     :1;
        __IO  uint32_t  RF1N                     :1;
        __IO  uint32_t  RF1W                     :1;
        __IO  uint32_t  RF1F                     :1;
        __IO  uint32_t  RF1L                     :1;
        __IO  uint32_t  HPM                      :1;
        __IO  uint32_t  TC                       :1;
        __IO  uint32_t  TCF                      :1;
        __IO  uint32_t  TFE                      :1;
        __IO  uint32_t  TEFN                     :1;
        __IO  uint32_t  TEFW                     :1;
        __IO  uint32_t  TEFF                     :1;
        __IO  uint32_t  TEFL                     :1;
        __IO  uint32_t  TSW                      :1;
        __IO  uint32_t  MRAF                     :1;
        __IO  uint32_t  TOO                      :1;
        __IO  uint32_t  DRX                      :1;
        __IO  uint32_t  BEC                      :1;
        __IO  uint32_t  BEU                      :1;
        __IO  uint32_t  ELO                      :1;
        __IO  uint32_t  EP                       :1;
        __IO  uint32_t  EW                       :1;
        __IO  uint32_t  BO                       :1;
        __IO  uint32_t  WDI                      :1;
        __IO  uint32_t  CRCE                     :1;
        __IO  uint32_t  BE                       :1;
        __IO  uint32_t  ACKE                     :1;
        __IO  uint32_t  FOE                      :1;
        __IO  uint32_t  STE                      :1;
} stc_canfd_ir_field_t;

typedef struct stc_canfd_ie_field
{
        __IO  uint32_t  RF0NE                    :1;
        __IO  uint32_t  RF0WE                    :1;
        __IO  uint32_t  RF0FE                    :1;
        __IO  uint32_t  RF0LE                    :1;
        __IO  uint32_t  RF1NE                    :1;
        __IO  uint32_t  RF1WE                    :1;
        __IO  uint32_t  RF1FE                    :1;
        __IO  uint32_t  RF1LE                    :1;
        __IO  uint32_t  HPME                     :1;
        __IO  uint32_t  TCE                      :1;
        __IO  uint32_t  TCFE                     :1;
        __IO  uint32_t  TFEE                     :1;
        __IO  uint32_t  TEFNE                    :1;
        __IO  uint32_t  TEFWE                    :1;
        __IO  uint32_t  TEFFE                    :1;
        __IO  uint32_t  TEFLE                    :1;
        __IO  uint32_t  TSWE                     :1;
        __IO  uint32_t  MRAFE                    :1;
        __IO  uint32_t  TOOE                     :1;
        __IO  uint32_t  DRXE                     :1;
        __IO  uint32_t  BECE                     :1;
        __IO  uint32_t  BEUE                     :1;
        __IO  uint32_t  ELOE                     :1;
        __IO  uint32_t  EPE                      :1;
        __IO  uint32_t  EWE                      :1;
        __IO  uint32_t  BOE                      :1;
        __IO  uint32_t  WDIE                     :1;
        __IO  uint32_t  CRCEE                    :1;
        __IO  uint32_t  BEE                      :1;
        __IO  uint32_t  ACKEE                    :1;
        __IO  uint32_t  FOEE                     :1;
        __IO  uint32_t  STEE                     :1;
} stc_canfd_ie_field_t;

typedef struct stc_canfd_ils_field
{
        __IO  uint32_t  RF0NL                    :1;
        __IO  uint32_t  RF0WL                    :1;
        __IO  uint32_t  RF0FL                    :1;
        __IO  uint32_t  RF0LL                    :1;
        __IO  uint32_t  RF1NL                    :1;
        __IO  uint32_t  RF1WL                    :1;
        __IO  uint32_t  RF1FL                    :1;
        __IO  uint32_t  RF1LL                    :1;
        __IO  uint32_t  HPML                     :1;
        __IO  uint32_t  TCL                      :1;
        __IO  uint32_t  TCFL                     :1;
        __IO  uint32_t  TFEL                     :1;
        __IO  uint32_t  TEFNL                    :1;
        __IO  uint32_t  TEFWL                    :1;
        __IO  uint32_t  TEFFL                    :1;
        __IO  uint32_t  TEFLL                    :1;
        __IO  uint32_t  TSWL                     :1;
        __IO  uint32_t  MRAFL                    :1;
        __IO  uint32_t  TOOL                     :1;
        __IO  uint32_t  DRXL                     :1;
        __IO  uint32_t  BECL                     :1;
        __IO  uint32_t  BEUL                     :1;
        __IO  uint32_t  ELOL                     :1;
        __IO  uint32_t  EPL                      :1;
        __IO  uint32_t  EWL                      :1;
        __IO  uint32_t  BOL                      :1;
        __IO  uint32_t  WDIL                     :1;
        __IO  uint32_t  CRCEL                    :1;
        __IO  uint32_t  BEL                      :1;
        __IO  uint32_t  ACKEL                    :1;
        __IO  uint32_t  FOEL                     :1;
        __IO  uint32_t  STEL                     :1;
} stc_canfd_ils_field_t;

typedef struct stc_canfd_ile_field
{
        __IO  uint32_t  EINT0                    :1;
        __IO  uint32_t  EINT1                    :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_canfd_ile_field_t;

typedef struct stc_canfd_gfc_field
{
    union {
        struct {
            __IO  uint32_t  RRFE                 :1;
            __IO  uint32_t  RRFS                 :1;
            __IO  uint32_t  ANFE                 :2;
            __IO  uint32_t  ANFS                 :2;
            __IO  uint32_t  RESERVED1            :26;
        };
        struct {
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  ANFE0                :1;
            __IO  uint32_t  ANFE1                :1;
            __IO  uint32_t  ANFS0                :1;
            __IO  uint32_t  ANFS1                :1;
            __IO  uint32_t  RESERVED2            :26;
        };
    };
} stc_canfd_gfc_field_t;

typedef struct stc_canfd_sidfc_field
{
    union {
        struct {
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  FLSSA                :14;
            __IO  uint32_t  LSS                  :8;
            __IO  uint32_t  RESERVED2            :8;
        };
        struct {
            __IO  uint32_t  RESERVED1            :2;
            __IO  uint32_t  FLSSA0               :1;
            __IO  uint32_t  FLSSA1               :1;
            __IO  uint32_t  FLSSA2               :1;
            __IO  uint32_t  FLSSA3               :1;
            __IO  uint32_t  FLSSA4               :1;
            __IO  uint32_t  FLSSA5               :1;
            __IO  uint32_t  FLSSA6               :1;
            __IO  uint32_t  FLSSA7               :1;
            __IO  uint32_t  FLSSA8               :1;
            __IO  uint32_t  FLSSA9               :1;
            __IO  uint32_t  FLSSA10              :1;
            __IO  uint32_t  FLSSA11              :1;
            __IO  uint32_t  FLSSA12              :1;
            __IO  uint32_t  FLSSA13              :1;
            __IO  uint32_t  LSS0                 :1;
            __IO  uint32_t  LSS1                 :1;
            __IO  uint32_t  LSS2                 :1;
            __IO  uint32_t  LSS3                 :1;
            __IO  uint32_t  LSS4                 :1;
            __IO  uint32_t  LSS5                 :1;
            __IO  uint32_t  LSS6                 :1;
            __IO  uint32_t  LSS7                 :1;
            __IO  uint32_t  RESERVED3            :8;
        };
    };
} stc_canfd_sidfc_field_t;

typedef struct stc_canfd_xidfc_field
{
    union {
        struct {
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  FLESA                :14;
            __IO  uint32_t  LSE                  :7;
            __IO  uint32_t  RESERVED2            :9;
        };
        struct {
            __IO  uint32_t  RESERVED1            :2;
            __IO  uint32_t  FLESA0               :1;
            __IO  uint32_t  FLESA1               :1;
            __IO  uint32_t  FLESA2               :1;
            __IO  uint32_t  FLESA3               :1;
            __IO  uint32_t  FLESA4               :1;
            __IO  uint32_t  FLESA5               :1;
            __IO  uint32_t  FLESA6               :1;
            __IO  uint32_t  FLESA7               :1;
            __IO  uint32_t  FLESA8               :1;
            __IO  uint32_t  FLESA9               :1;
            __IO  uint32_t  FLESA10              :1;
            __IO  uint32_t  FLESA11              :1;
            __IO  uint32_t  FLESA12              :1;
            __IO  uint32_t  FLESA13              :1;
            __IO  uint32_t  LSE0                 :1;
            __IO  uint32_t  LSE1                 :1;
            __IO  uint32_t  LSE2                 :1;
            __IO  uint32_t  LSE3                 :1;
            __IO  uint32_t  LSE4                 :1;
            __IO  uint32_t  LSE5                 :1;
            __IO  uint32_t  LSE6                 :1;
            __IO  uint32_t  RESERVED3            :9;
        };
    };
} stc_canfd_xidfc_field_t;

typedef struct stc_canfd_xidam_field
{
    union {
        struct {
            __IO  uint32_t  EIDM                 :29;
            __IO  uint32_t  RESERVED0            :3;
        };
        struct {
            __IO  uint32_t  EIDM0                :1;
            __IO  uint32_t  EIDM1                :1;
            __IO  uint32_t  EIDM2                :1;
            __IO  uint32_t  EIDM3                :1;
            __IO  uint32_t  EIDM4                :1;
            __IO  uint32_t  EIDM5                :1;
            __IO  uint32_t  EIDM6                :1;
            __IO  uint32_t  EIDM7                :1;
            __IO  uint32_t  EIDM8                :1;
            __IO  uint32_t  EIDM9                :1;
            __IO  uint32_t  EIDM10               :1;
            __IO  uint32_t  EIDM11               :1;
            __IO  uint32_t  EIDM12               :1;
            __IO  uint32_t  EIDM13               :1;
            __IO  uint32_t  EIDM14               :1;
            __IO  uint32_t  EIDM15               :1;
            __IO  uint32_t  EIDM16               :1;
            __IO  uint32_t  EIDM17               :1;
            __IO  uint32_t  EIDM18               :1;
            __IO  uint32_t  EIDM19               :1;
            __IO  uint32_t  EIDM20               :1;
            __IO  uint32_t  EIDM21               :1;
            __IO  uint32_t  EIDM22               :1;
            __IO  uint32_t  EIDM23               :1;
            __IO  uint32_t  EIDM24               :1;
            __IO  uint32_t  EIDM25               :1;
            __IO  uint32_t  EIDM26               :1;
            __IO  uint32_t  EIDM27               :1;
            __IO  uint32_t  EIDM28               :1;
            __IO  uint32_t  RESERVED1            :3;
        };
    };
} stc_canfd_xidam_field_t;

typedef struct stc_canfd_hpms_field
{
    union {
        struct {
            __IO  uint32_t  BIDX                 :6;
            __IO  uint32_t  MSI                  :2;
            __IO  uint32_t  FIDX                 :7;
            __IO  uint32_t  FLST                 :1;
            __IO  uint32_t  RESERVED0            :16;
        };
        struct {
            __IO  uint32_t  BIDX0                :1;
            __IO  uint32_t  BIDX1                :1;
            __IO  uint32_t  BIDX2                :1;
            __IO  uint32_t  BIDX3                :1;
            __IO  uint32_t  BIDX4                :1;
            __IO  uint32_t  BIDX5                :1;
            __IO  uint32_t  MSI0                 :1;
            __IO  uint32_t  MSI1                 :1;
            __IO  uint32_t  FIDX0                :1;
            __IO  uint32_t  FIDX1                :1;
            __IO  uint32_t  FIDX2                :1;
            __IO  uint32_t  FIDX3                :1;
            __IO  uint32_t  FIDX4                :1;
            __IO  uint32_t  FIDX5                :1;
            __IO  uint32_t  FIDX6                :1;
            __IO  uint32_t  RESERVED1            :17;
        };
    };
} stc_canfd_hpms_field_t;

typedef struct stc_canfd_ndat1_field
{
        __IO  uint32_t  ND0                      :1;
        __IO  uint32_t  ND1                      :1;
        __IO  uint32_t  ND2                      :1;
        __IO  uint32_t  ND3                      :1;
        __IO  uint32_t  ND4                      :1;
        __IO  uint32_t  ND5                      :1;
        __IO  uint32_t  ND6                      :1;
        __IO  uint32_t  ND7                      :1;
        __IO  uint32_t  ND8                      :1;
        __IO  uint32_t  ND9                      :1;
        __IO  uint32_t  ND10                     :1;
        __IO  uint32_t  ND11                     :1;
        __IO  uint32_t  ND12                     :1;
        __IO  uint32_t  ND13                     :1;
        __IO  uint32_t  ND14                     :1;
        __IO  uint32_t  ND15                     :1;
        __IO  uint32_t  ND16                     :1;
        __IO  uint32_t  ND17                     :1;
        __IO  uint32_t  ND18                     :1;
        __IO  uint32_t  ND19                     :1;
        __IO  uint32_t  ND20                     :1;
        __IO  uint32_t  ND21                     :1;
        __IO  uint32_t  ND22                     :1;
        __IO  uint32_t  ND23                     :1;
        __IO  uint32_t  ND24                     :1;
        __IO  uint32_t  ND25                     :1;
        __IO  uint32_t  ND26                     :1;
        __IO  uint32_t  ND27                     :1;
        __IO  uint32_t  ND28                     :1;
        __IO  uint32_t  ND29                     :1;
        __IO  uint32_t  ND30                     :1;
        __IO  uint32_t  ND31                     :1;
} stc_canfd_ndat1_field_t;

typedef struct stc_canfd_ndat2_field
{
        __IO  uint32_t  ND32                     :1;
        __IO  uint32_t  ND33                     :1;
        __IO  uint32_t  ND34                     :1;
        __IO  uint32_t  ND35                     :1;
        __IO  uint32_t  ND36                     :1;
        __IO  uint32_t  ND37                     :1;
        __IO  uint32_t  ND38                     :1;
        __IO  uint32_t  ND39                     :1;
        __IO  uint32_t  ND40                     :1;
        __IO  uint32_t  ND41                     :1;
        __IO  uint32_t  ND42                     :1;
        __IO  uint32_t  ND43                     :1;
        __IO  uint32_t  ND44                     :1;
        __IO  uint32_t  ND45                     :1;
        __IO  uint32_t  ND46                     :1;
        __IO  uint32_t  ND47                     :1;
        __IO  uint32_t  ND48                     :1;
        __IO  uint32_t  ND49                     :1;
        __IO  uint32_t  ND50                     :1;
        __IO  uint32_t  ND51                     :1;
        __IO  uint32_t  ND52                     :1;
        __IO  uint32_t  ND53                     :1;
        __IO  uint32_t  ND54                     :1;
        __IO  uint32_t  ND55                     :1;
        __IO  uint32_t  ND56                     :1;
        __IO  uint32_t  ND57                     :1;
        __IO  uint32_t  ND58                     :1;
        __IO  uint32_t  ND59                     :1;
        __IO  uint32_t  ND60                     :1;
        __IO  uint32_t  ND61                     :1;
        __IO  uint32_t  ND62                     :1;
        __IO  uint32_t  ND63                     :1;
} stc_canfd_ndat2_field_t;

typedef struct stc_canfd_rxf0c_field
{
    union {
        struct {
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  F0SA                 :14;
            __IO  uint32_t  F0S                  :7;
            __IO  uint32_t  RESERVED2            :1;
            __IO  uint32_t  F0WM                 :7;
            __IO  uint32_t  F0OM                 :1;
        };
        struct {
            __IO  uint32_t  RESERVED1            :2;
            __IO  uint32_t  F0SA0                :1;
            __IO  uint32_t  F0SA1                :1;
            __IO  uint32_t  F0SA2                :1;
            __IO  uint32_t  F0SA3                :1;
            __IO  uint32_t  F0SA4                :1;
            __IO  uint32_t  F0SA5                :1;
            __IO  uint32_t  F0SA6                :1;
            __IO  uint32_t  F0SA7                :1;
            __IO  uint32_t  F0SA8                :1;
            __IO  uint32_t  F0SA9                :1;
            __IO  uint32_t  F0SA10               :1;
            __IO  uint32_t  F0SA11               :1;
            __IO  uint32_t  F0SA12               :1;
            __IO  uint32_t  F0SA13               :1;
            __IO  uint32_t  F0S0                 :1;
            __IO  uint32_t  F0S1                 :1;
            __IO  uint32_t  F0S2                 :1;
            __IO  uint32_t  F0S3                 :1;
            __IO  uint32_t  F0S4                 :1;
            __IO  uint32_t  F0S5                 :1;
            __IO  uint32_t  F0S6                 :1;
            __IO  uint32_t  RESERVED3            :1;
            __IO  uint32_t  F0WM0                :1;
            __IO  uint32_t  F0WM1                :1;
            __IO  uint32_t  F0WM2                :1;
            __IO  uint32_t  F0WM3                :1;
            __IO  uint32_t  F0WM4                :1;
            __IO  uint32_t  F0WM5                :1;
            __IO  uint32_t  F0WM6                :1;
            __IO  uint32_t  RESERVED4            :1;
        };
    };
} stc_canfd_rxf0c_field_t;

typedef struct stc_canfd_rxf0s_field
{
    union {
        struct {
            __IO  uint32_t  F0FL                 :7;
            __IO  uint32_t  RESERVED0            :1;
            __IO  uint32_t  F0GI                 :6;
            __IO  uint32_t  RESERVED2            :2;
            __IO  uint32_t  F0PI                 :6;
            __IO  uint32_t  RESERVED4            :2;
            __IO  uint32_t  F0F                  :1;
            __IO  uint32_t  RF0L                 :1;
            __IO  uint32_t  RESERVED5            :6;
        };
        struct {
            __IO  uint32_t  F0FL0                :1;
            __IO  uint32_t  F0FL1                :1;
            __IO  uint32_t  F0FL2                :1;
            __IO  uint32_t  F0FL3                :1;
            __IO  uint32_t  F0FL4                :1;
            __IO  uint32_t  F0FL5                :1;
            __IO  uint32_t  F0FL6                :1;
            __IO  uint32_t  RESERVED1            :1;
            __IO  uint32_t  F0GI0                :1;
            __IO  uint32_t  F0GI1                :1;
            __IO  uint32_t  F0GI2                :1;
            __IO  uint32_t  F0GI3                :1;
            __IO  uint32_t  F0GI4                :1;
            __IO  uint32_t  F0GI5                :1;
            __IO  uint32_t  RESERVED3            :2;
            __IO  uint32_t  F0PI0                :1;
            __IO  uint32_t  F0PI1                :1;
            __IO  uint32_t  F0PI2                :1;
            __IO  uint32_t  F0PI3                :1;
            __IO  uint32_t  F0PI4                :1;
            __IO  uint32_t  F0PI5                :1;
            __IO  uint32_t  RESERVED6            :10;
        };
    };
} stc_canfd_rxf0s_field_t;

typedef struct stc_canfd_rxf0a_field
{
    union {
        struct {
            __IO  uint32_t  F0AI                 :6;
            __IO  uint32_t  RESERVED0            :26;
        };
        struct {
            __IO  uint32_t  F0AI0                :1;
            __IO  uint32_t  F0AI1                :1;
            __IO  uint32_t  F0AI2                :1;
            __IO  uint32_t  F0AI3                :1;
            __IO  uint32_t  F0AI4                :1;
            __IO  uint32_t  F0AI5                :1;
            __IO  uint32_t  RESERVED1            :26;
        };
    };
} stc_canfd_rxf0a_field_t;

typedef struct stc_canfd_rxbc_field
{
    union {
        struct {
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  RBSA                 :14;
            __IO  uint32_t  RESERVED2            :16;
        };
        struct {
            __IO  uint32_t  RESERVED1            :2;
            __IO  uint32_t  RBSA0                :1;
            __IO  uint32_t  RBSA1                :1;
            __IO  uint32_t  RBSA2                :1;
            __IO  uint32_t  RBSA3                :1;
            __IO  uint32_t  RBSA4                :1;
            __IO  uint32_t  RBSA5                :1;
            __IO  uint32_t  RBSA6                :1;
            __IO  uint32_t  RBSA7                :1;
            __IO  uint32_t  RBSA8                :1;
            __IO  uint32_t  RBSA9                :1;
            __IO  uint32_t  RBSA10               :1;
            __IO  uint32_t  RBSA11               :1;
            __IO  uint32_t  RBSA12               :1;
            __IO  uint32_t  RBSA13               :1;
            __IO  uint32_t  RESERVED3            :16;
        };
    };
} stc_canfd_rxbc_field_t;

typedef struct stc_canfd_rxf1c_field
{
    union {
        struct {
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  F1SA                 :14;
            __IO  uint32_t  F1S                  :7;
            __IO  uint32_t  RESERVED2            :1;
            __IO  uint32_t  F1WM                 :7;
            __IO  uint32_t  F1OM                 :1;
        };
        struct {
            __IO  uint32_t  RESERVED1            :2;
            __IO  uint32_t  F1SA0                :1;
            __IO  uint32_t  F1SA1                :1;
            __IO  uint32_t  F1SA2                :1;
            __IO  uint32_t  F1SA3                :1;
            __IO  uint32_t  F1SA4                :1;
            __IO  uint32_t  F1SA5                :1;
            __IO  uint32_t  F1SA6                :1;
            __IO  uint32_t  F1SA7                :1;
            __IO  uint32_t  F1SA8                :1;
            __IO  uint32_t  F1SA9                :1;
            __IO  uint32_t  F1SA10               :1;
            __IO  uint32_t  F1SA11               :1;
            __IO  uint32_t  F1SA12               :1;
            __IO  uint32_t  F1SA13               :1;
            __IO  uint32_t  F1S0                 :1;
            __IO  uint32_t  F1S1                 :1;
            __IO  uint32_t  F1S2                 :1;
            __IO  uint32_t  F1S3                 :1;
            __IO  uint32_t  F1S4                 :1;
            __IO  uint32_t  F1S5                 :1;
            __IO  uint32_t  F1S6                 :1;
            __IO  uint32_t  RESERVED3            :1;
            __IO  uint32_t  F1WM0                :1;
            __IO  uint32_t  F1WM1                :1;
            __IO  uint32_t  F1WM2                :1;
            __IO  uint32_t  F1WM3                :1;
            __IO  uint32_t  F1WM4                :1;
            __IO  uint32_t  F1WM5                :1;
            __IO  uint32_t  F1WM6                :1;
            __IO  uint32_t  RESERVED4            :1;
        };
    };
} stc_canfd_rxf1c_field_t;

typedef struct stc_canfd_rxf1s_field
{
    union {
        struct {
            __IO  uint32_t  F1FL                 :7;
            __IO  uint32_t  RESERVED0            :1;
            __IO  uint32_t  F1GI                 :6;
            __IO  uint32_t  RESERVED2            :2;
            __IO  uint32_t  F1PI                 :6;
            __IO  uint32_t  RESERVED4            :2;
            __IO  uint32_t  F1F                  :1;
            __IO  uint32_t  RF1L                 :1;
            __IO  uint32_t  RESERVED5            :4;
            __IO  uint32_t  DMS                  :2;
        };
        struct {
            __IO  uint32_t  F1FL0                :1;
            __IO  uint32_t  F1FL1                :1;
            __IO  uint32_t  F1FL2                :1;
            __IO  uint32_t  F1FL3                :1;
            __IO  uint32_t  F1FL4                :1;
            __IO  uint32_t  F1FL5                :1;
            __IO  uint32_t  F1FL6                :1;
            __IO  uint32_t  RESERVED1            :1;
            __IO  uint32_t  F1GI0                :1;
            __IO  uint32_t  F1GI1                :1;
            __IO  uint32_t  F1GI2                :1;
            __IO  uint32_t  F1GI3                :1;
            __IO  uint32_t  F1GI4                :1;
            __IO  uint32_t  F1GI5                :1;
            __IO  uint32_t  RESERVED3            :2;
            __IO  uint32_t  F1PI0                :1;
            __IO  uint32_t  F1PI1                :1;
            __IO  uint32_t  F1PI2                :1;
            __IO  uint32_t  F1PI3                :1;
            __IO  uint32_t  F1PI4                :1;
            __IO  uint32_t  F1PI5                :1;
            __IO  uint32_t  RESERVED6            :8;
            __IO  uint32_t  DMS0                 :1;
            __IO  uint32_t  DMS1                 :1;
        };
    };
} stc_canfd_rxf1s_field_t;

typedef struct stc_canfd_rxf1a_field
{
    union {
        struct {
            __IO  uint32_t  F1AI                 :6;
            __IO  uint32_t  RESERVED0            :26;
        };
        struct {
            __IO  uint32_t  F1AI0                :1;
            __IO  uint32_t  F1AI1                :1;
            __IO  uint32_t  F1AI2                :1;
            __IO  uint32_t  F1AI3                :1;
            __IO  uint32_t  F1AI4                :1;
            __IO  uint32_t  F1AI5                :1;
            __IO  uint32_t  RESERVED1            :26;
        };
    };
} stc_canfd_rxf1a_field_t;

typedef struct stc_canfd_rxesc_field
{
    union {
        struct {
            __IO  uint32_t  F0DS                 :3;
            __IO  uint32_t  RESERVED0            :1;
            __IO  uint32_t  F1DS                 :3;
            __IO  uint32_t  RESERVED2            :1;
            __IO  uint32_t  RBDS                 :3;
            __IO  uint32_t  RESERVED4            :21;
        };
        struct {
            __IO  uint32_t  F0DS0                :1;
            __IO  uint32_t  F0DS1                :1;
            __IO  uint32_t  F0DS2                :1;
            __IO  uint32_t  RESERVED1            :1;
            __IO  uint32_t  F1DS0                :1;
            __IO  uint32_t  F1DS1                :1;
            __IO  uint32_t  F1DS2                :1;
            __IO  uint32_t  RESERVED3            :1;
            __IO  uint32_t  RBDS0                :1;
            __IO  uint32_t  RBDS1                :1;
            __IO  uint32_t  RBDS2                :1;
            __IO  uint32_t  RESERVED5            :21;
        };
    };
} stc_canfd_rxesc_field_t;

typedef struct stc_canfd_txbc_field
{
    union {
        struct {
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  TBSA                 :14;
            __IO  uint32_t  NDTB                 :6;
            __IO  uint32_t  RESERVED2            :2;
            __IO  uint32_t  TFQS                 :6;
            __IO  uint32_t  TFQM                 :1;
            __IO  uint32_t  RESERVED4            :1;
        };
        struct {
            __IO  uint32_t  RESERVED1            :2;
            __IO  uint32_t  TBSA0                :1;
            __IO  uint32_t  TBSA1                :1;
            __IO  uint32_t  TBSA2                :1;
            __IO  uint32_t  TBSA3                :1;
            __IO  uint32_t  TBSA4                :1;
            __IO  uint32_t  TBSA5                :1;
            __IO  uint32_t  TBSA6                :1;
            __IO  uint32_t  TBSA7                :1;
            __IO  uint32_t  TBSA8                :1;
            __IO  uint32_t  TBSA9                :1;
            __IO  uint32_t  TBSA10               :1;
            __IO  uint32_t  TBSA11               :1;
            __IO  uint32_t  TBSA12               :1;
            __IO  uint32_t  TBSA13               :1;
            __IO  uint32_t  NDTB0                :1;
            __IO  uint32_t  NDTB1                :1;
            __IO  uint32_t  NDTB2                :1;
            __IO  uint32_t  NDTB3                :1;
            __IO  uint32_t  NDTB4                :1;
            __IO  uint32_t  NDTB5                :1;
            __IO  uint32_t  RESERVED3            :2;
            __IO  uint32_t  TFQS0                :1;
            __IO  uint32_t  TFQS1                :1;
            __IO  uint32_t  TFQS2                :1;
            __IO  uint32_t  TFQS3                :1;
            __IO  uint32_t  TFQS4                :1;
            __IO  uint32_t  TFQS5                :1;
            __IO  uint32_t  RESERVED5            :2;
        };
    };
} stc_canfd_txbc_field_t;

typedef struct stc_canfd_txfqs_field
{
    union {
        struct {
            __IO  uint32_t  TFFL                 :6;
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  TFGI                 :5;
            __IO  uint32_t  RESERVED2            :3;
            __IO  uint32_t  TFQPI                :5;
            __IO  uint32_t  TFQF                 :1;
            __IO  uint32_t  RESERVED4            :10;
        };
        struct {
            __IO  uint32_t  TFFL0                :1;
            __IO  uint32_t  TFFL1                :1;
            __IO  uint32_t  TFFL2                :1;
            __IO  uint32_t  TFFL3                :1;
            __IO  uint32_t  TFFL4                :1;
            __IO  uint32_t  TFFL5                :1;
            __IO  uint32_t  RESERVED1            :2;
            __IO  uint32_t  TFGI0                :1;
            __IO  uint32_t  TFGI1                :1;
            __IO  uint32_t  TFGI2                :1;
            __IO  uint32_t  TFGI3                :1;
            __IO  uint32_t  TFGI4                :1;
            __IO  uint32_t  RESERVED3            :3;
            __IO  uint32_t  TFQPI0               :1;
            __IO  uint32_t  TFQPI1               :1;
            __IO  uint32_t  TFQPI2               :1;
            __IO  uint32_t  TFQPI3               :1;
            __IO  uint32_t  TFQPI4               :1;
            __IO  uint32_t  RESERVED5            :11;
        };
    };
} stc_canfd_txfqs_field_t;

typedef struct stc_canfd_txesc_field
{
    union {
        struct {
            __IO  uint32_t  TBDS                 :3;
            __IO  uint32_t  RESERVED0            :29;
        };
        struct {
            __IO  uint32_t  TBDS0                :1;
            __IO  uint32_t  TBDS1                :1;
            __IO  uint32_t  TBDS2                :1;
            __IO  uint32_t  RESERVED1            :29;
        };
    };
} stc_canfd_txesc_field_t;

typedef struct stc_canfd_txbrp_field
{
        __IO  uint32_t  TRP0                     :1;
        __IO  uint32_t  TRP1                     :1;
        __IO  uint32_t  TRP2                     :1;
        __IO  uint32_t  TRP3                     :1;
        __IO  uint32_t  TRP4                     :1;
        __IO  uint32_t  TRP5                     :1;
        __IO  uint32_t  TRP6                     :1;
        __IO  uint32_t  TRP7                     :1;
        __IO  uint32_t  TRP8                     :1;
        __IO  uint32_t  TRP9                     :1;
        __IO  uint32_t  TRP10                    :1;
        __IO  uint32_t  TRP11                    :1;
        __IO  uint32_t  TRP12                    :1;
        __IO  uint32_t  TRP13                    :1;
        __IO  uint32_t  TRP14                    :1;
        __IO  uint32_t  TRP15                    :1;
        __IO  uint32_t  TRP16                    :1;
        __IO  uint32_t  TRP17                    :1;
        __IO  uint32_t  TRP18                    :1;
        __IO  uint32_t  TRP19                    :1;
        __IO  uint32_t  TRP20                    :1;
        __IO  uint32_t  TRP21                    :1;
        __IO  uint32_t  TRP22                    :1;
        __IO  uint32_t  TRP23                    :1;
        __IO  uint32_t  TRP24                    :1;
        __IO  uint32_t  TRP25                    :1;
        __IO  uint32_t  TRP26                    :1;
        __IO  uint32_t  TRP27                    :1;
        __IO  uint32_t  TRP28                    :1;
        __IO  uint32_t  TRP29                    :1;
        __IO  uint32_t  TRP30                    :1;
        __IO  uint32_t  TRP31                    :1;
} stc_canfd_txbrp_field_t;

typedef struct stc_canfd_txbar_field
{
        __IO  uint32_t  AR0                      :1;
        __IO  uint32_t  AR1                      :1;
        __IO  uint32_t  AR2                      :1;
        __IO  uint32_t  AR3                      :1;
        __IO  uint32_t  AR4                      :1;
        __IO  uint32_t  AR5                      :1;
        __IO  uint32_t  AR6                      :1;
        __IO  uint32_t  AR7                      :1;
        __IO  uint32_t  AR8                      :1;
        __IO  uint32_t  AR9                      :1;
        __IO  uint32_t  AR10                     :1;
        __IO  uint32_t  AR11                     :1;
        __IO  uint32_t  AR12                     :1;
        __IO  uint32_t  AR13                     :1;
        __IO  uint32_t  AR14                     :1;
        __IO  uint32_t  AR15                     :1;
        __IO  uint32_t  AR16                     :1;
        __IO  uint32_t  AR17                     :1;
        __IO  uint32_t  AR18                     :1;
        __IO  uint32_t  AR19                     :1;
        __IO  uint32_t  AR20                     :1;
        __IO  uint32_t  AR21                     :1;
        __IO  uint32_t  AR22                     :1;
        __IO  uint32_t  AR23                     :1;
        __IO  uint32_t  AR24                     :1;
        __IO  uint32_t  AR25                     :1;
        __IO  uint32_t  AR26                     :1;
        __IO  uint32_t  AR27                     :1;
        __IO  uint32_t  AR28                     :1;
        __IO  uint32_t  AR29                     :1;
        __IO  uint32_t  AR30                     :1;
        __IO  uint32_t  AR31                     :1;
} stc_canfd_txbar_field_t;

typedef struct stc_canfd_txbcr_field
{
        __IO  uint32_t  CR0                      :1;
        __IO  uint32_t  CR1                      :1;
        __IO  uint32_t  CR2                      :1;
        __IO  uint32_t  CR3                      :1;
        __IO  uint32_t  CR4                      :1;
        __IO  uint32_t  CR5                      :1;
        __IO  uint32_t  CR6                      :1;
        __IO  uint32_t  CR7                      :1;
        __IO  uint32_t  CR8                      :1;
        __IO  uint32_t  CR9                      :1;
        __IO  uint32_t  CR10                     :1;
        __IO  uint32_t  CR11                     :1;
        __IO  uint32_t  CR12                     :1;
        __IO  uint32_t  CR13                     :1;
        __IO  uint32_t  CR14                     :1;
        __IO  uint32_t  CR15                     :1;
        __IO  uint32_t  CR16                     :1;
        __IO  uint32_t  CR17                     :1;
        __IO  uint32_t  CR18                     :1;
        __IO  uint32_t  CR19                     :1;
        __IO  uint32_t  CR20                     :1;
        __IO  uint32_t  CR21                     :1;
        __IO  uint32_t  CR22                     :1;
        __IO  uint32_t  CR23                     :1;
        __IO  uint32_t  CR24                     :1;
        __IO  uint32_t  CR25                     :1;
        __IO  uint32_t  CR26                     :1;
        __IO  uint32_t  CR27                     :1;
        __IO  uint32_t  CR28                     :1;
        __IO  uint32_t  CR29                     :1;
        __IO  uint32_t  CR30                     :1;
        __IO  uint32_t  CR31                     :1;
} stc_canfd_txbcr_field_t;

typedef struct stc_canfd_txbto_field
{
        __IO  uint32_t  TO0                      :1;
        __IO  uint32_t  TO1                      :1;
        __IO  uint32_t  TO2                      :1;
        __IO  uint32_t  TO3                      :1;
        __IO  uint32_t  TO4                      :1;
        __IO  uint32_t  TO5                      :1;
        __IO  uint32_t  TO6                      :1;
        __IO  uint32_t  TO7                      :1;
        __IO  uint32_t  TO8                      :1;
        __IO  uint32_t  TO9                      :1;
        __IO  uint32_t  TO10                     :1;
        __IO  uint32_t  TO11                     :1;
        __IO  uint32_t  TO12                     :1;
        __IO  uint32_t  TO13                     :1;
        __IO  uint32_t  TO14                     :1;
        __IO  uint32_t  TO15                     :1;
        __IO  uint32_t  TO16                     :1;
        __IO  uint32_t  TO17                     :1;
        __IO  uint32_t  TO18                     :1;
        __IO  uint32_t  TO19                     :1;
        __IO  uint32_t  TO20                     :1;
        __IO  uint32_t  TO21                     :1;
        __IO  uint32_t  TO22                     :1;
        __IO  uint32_t  TO23                     :1;
        __IO  uint32_t  TO24                     :1;
        __IO  uint32_t  TO25                     :1;
        __IO  uint32_t  TO26                     :1;
        __IO  uint32_t  TO27                     :1;
        __IO  uint32_t  TO28                     :1;
        __IO  uint32_t  TO29                     :1;
        __IO  uint32_t  TO30                     :1;
        __IO  uint32_t  TO31                     :1;
} stc_canfd_txbto_field_t;

typedef struct stc_canfd_txbcf_field
{
        __IO  uint32_t  CF0                      :1;
        __IO  uint32_t  CF1                      :1;
        __IO  uint32_t  CF2                      :1;
        __IO  uint32_t  CF3                      :1;
        __IO  uint32_t  CF4                      :1;
        __IO  uint32_t  CF5                      :1;
        __IO  uint32_t  CF6                      :1;
        __IO  uint32_t  CF7                      :1;
        __IO  uint32_t  CF8                      :1;
        __IO  uint32_t  CF9                      :1;
        __IO  uint32_t  CF10                     :1;
        __IO  uint32_t  CF11                     :1;
        __IO  uint32_t  CF12                     :1;
        __IO  uint32_t  CF13                     :1;
        __IO  uint32_t  CF14                     :1;
        __IO  uint32_t  CF15                     :1;
        __IO  uint32_t  CF16                     :1;
        __IO  uint32_t  CF17                     :1;
        __IO  uint32_t  CF18                     :1;
        __IO  uint32_t  CF19                     :1;
        __IO  uint32_t  CF20                     :1;
        __IO  uint32_t  CF21                     :1;
        __IO  uint32_t  CF22                     :1;
        __IO  uint32_t  CF23                     :1;
        __IO  uint32_t  CF24                     :1;
        __IO  uint32_t  CF25                     :1;
        __IO  uint32_t  CF26                     :1;
        __IO  uint32_t  CF27                     :1;
        __IO  uint32_t  CF28                     :1;
        __IO  uint32_t  CF29                     :1;
        __IO  uint32_t  CF30                     :1;
        __IO  uint32_t  CF31                     :1;
} stc_canfd_txbcf_field_t;

typedef struct stc_canfd_txbtie_field
{
        __IO  uint32_t  TIE0                     :1;
        __IO  uint32_t  TIE1                     :1;
        __IO  uint32_t  TIE2                     :1;
        __IO  uint32_t  TIE3                     :1;
        __IO  uint32_t  TIE4                     :1;
        __IO  uint32_t  TIE5                     :1;
        __IO  uint32_t  TIE6                     :1;
        __IO  uint32_t  TIE7                     :1;
        __IO  uint32_t  TIE8                     :1;
        __IO  uint32_t  TIE9                     :1;
        __IO  uint32_t  TIE10                    :1;
        __IO  uint32_t  TIE11                    :1;
        __IO  uint32_t  TIE12                    :1;
        __IO  uint32_t  TIE13                    :1;
        __IO  uint32_t  TIE14                    :1;
        __IO  uint32_t  TIE15                    :1;
        __IO  uint32_t  TIE16                    :1;
        __IO  uint32_t  TIE17                    :1;
        __IO  uint32_t  TIE18                    :1;
        __IO  uint32_t  TIE19                    :1;
        __IO  uint32_t  TIE20                    :1;
        __IO  uint32_t  TIE21                    :1;
        __IO  uint32_t  TIE22                    :1;
        __IO  uint32_t  TIE23                    :1;
        __IO  uint32_t  TIE24                    :1;
        __IO  uint32_t  TIE25                    :1;
        __IO  uint32_t  TIE26                    :1;
        __IO  uint32_t  TIE27                    :1;
        __IO  uint32_t  TIE28                    :1;
        __IO  uint32_t  TIE29                    :1;
        __IO  uint32_t  TIE30                    :1;
        __IO  uint32_t  TIE31                    :1;
} stc_canfd_txbtie_field_t;

typedef struct stc_canfd_txbcie_field
{
        __IO  uint32_t  CFIE0                    :1;
        __IO  uint32_t  CFIE1                    :1;
        __IO  uint32_t  CFIE2                    :1;
        __IO  uint32_t  CFIE3                    :1;
        __IO  uint32_t  CFIE4                    :1;
        __IO  uint32_t  CFIE5                    :1;
        __IO  uint32_t  CFIE6                    :1;
        __IO  uint32_t  CFIE7                    :1;
        __IO  uint32_t  CFIE8                    :1;
        __IO  uint32_t  CFIE9                    :1;
        __IO  uint32_t  CFIE10                   :1;
        __IO  uint32_t  CFIE11                   :1;
        __IO  uint32_t  CFIE12                   :1;
        __IO  uint32_t  CFIE13                   :1;
        __IO  uint32_t  CFIE14                   :1;
        __IO  uint32_t  CFIE15                   :1;
        __IO  uint32_t  CFIE16                   :1;
        __IO  uint32_t  CFIE17                   :1;
        __IO  uint32_t  CFIE18                   :1;
        __IO  uint32_t  CFIE19                   :1;
        __IO  uint32_t  CFIE20                   :1;
        __IO  uint32_t  CFIE21                   :1;
        __IO  uint32_t  CFIE22                   :1;
        __IO  uint32_t  CFIE23                   :1;
        __IO  uint32_t  CFIE24                   :1;
        __IO  uint32_t  CFIE25                   :1;
        __IO  uint32_t  CFIE26                   :1;
        __IO  uint32_t  CFIE27                   :1;
        __IO  uint32_t  CFIE28                   :1;
        __IO  uint32_t  CFIE29                   :1;
        __IO  uint32_t  CFIE30                   :1;
        __IO  uint32_t  CFIE31                   :1;
} stc_canfd_txbcie_field_t;

typedef struct stc_canfd_txefc_field
{
    union {
        struct {
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  EFSA                 :14;
            __IO  uint32_t  EFS                  :6;
            __IO  uint32_t  RESERVED2            :2;
            __IO  uint32_t  EFWM                 :6;
            __IO  uint32_t  RESERVED4            :2;
        };
        struct {
            __IO  uint32_t  RESERVED1            :2;
            __IO  uint32_t  EFSA0                :1;
            __IO  uint32_t  EFSA1                :1;
            __IO  uint32_t  EFSA2                :1;
            __IO  uint32_t  EFSA3                :1;
            __IO  uint32_t  EFSA4                :1;
            __IO  uint32_t  EFSA5                :1;
            __IO  uint32_t  EFSA6                :1;
            __IO  uint32_t  EFSA7                :1;
            __IO  uint32_t  EFSA8                :1;
            __IO  uint32_t  EFSA9                :1;
            __IO  uint32_t  EFSA10               :1;
            __IO  uint32_t  EFSA11               :1;
            __IO  uint32_t  EFSA12               :1;
            __IO  uint32_t  EFSA13               :1;
            __IO  uint32_t  EFS0                 :1;
            __IO  uint32_t  EFS1                 :1;
            __IO  uint32_t  EFS2                 :1;
            __IO  uint32_t  EFS3                 :1;
            __IO  uint32_t  EFS4                 :1;
            __IO  uint32_t  EFS5                 :1;
            __IO  uint32_t  RESERVED3            :2;
            __IO  uint32_t  EFWM0                :1;
            __IO  uint32_t  EFWM1                :1;
            __IO  uint32_t  EFWM2                :1;
            __IO  uint32_t  EFWM3                :1;
            __IO  uint32_t  EFWM4                :1;
            __IO  uint32_t  EFWM5                :1;
            __IO  uint32_t  RESERVED5            :2;
        };
    };
} stc_canfd_txefc_field_t;

typedef struct stc_canfd_txfs_field
{
    union {
        struct {
            __IO  uint32_t  EFFL                 :6;
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  EFGI                 :5;
            __IO  uint32_t  RESERVED2            :3;
            __IO  uint32_t  EFPI                 :5;
            __IO  uint32_t  RESERVED4            :3;
            __IO  uint32_t  EFF                  :1;
            __IO  uint32_t  TEFL                 :1;
            __IO  uint32_t  RESERVED5            :6;
        };
        struct {
            __IO  uint32_t  EFFL0                :1;
            __IO  uint32_t  EFFL1                :1;
            __IO  uint32_t  EFFL2                :1;
            __IO  uint32_t  EFFL3                :1;
            __IO  uint32_t  EFFL4                :1;
            __IO  uint32_t  EFFL5                :1;
            __IO  uint32_t  RESERVED1            :2;
            __IO  uint32_t  EFGI0                :1;
            __IO  uint32_t  EFGI1                :1;
            __IO  uint32_t  EFGI2                :1;
            __IO  uint32_t  EFGI3                :1;
            __IO  uint32_t  EFGI4                :1;
            __IO  uint32_t  RESERVED3            :3;
            __IO  uint32_t  EFPI0                :1;
            __IO  uint32_t  EFPI1                :1;
            __IO  uint32_t  EFPI2                :1;
            __IO  uint32_t  EFPI3                :1;
            __IO  uint32_t  EFPI4                :1;
            __IO  uint32_t  RESERVED6            :11;
        };
    };
} stc_canfd_txfs_field_t;

typedef struct stc_canfd_txfa_field
{
    union {
        struct {
            __IO  uint32_t  EFAI                 :5;
            __IO  uint32_t  RESERVED0            :27;
        };
        struct {
            __IO  uint32_t  EFAI0                :1;
            __IO  uint32_t  EFAI1                :1;
            __IO  uint32_t  EFAI2                :1;
            __IO  uint32_t  EFAI3                :1;
            __IO  uint32_t  EFAI4                :1;
            __IO  uint32_t  RESERVED1            :27;
        };
    };
} stc_canfd_txfa_field_t;

typedef struct stc_canfd_fdecr_field
{
        __IO   uint8_t  SEIE                     :1;
        __IO   uint8_t  DEIE                     :1;
        __IO   uint8_t  CEREN                    :1;
        __IO   uint8_t  CEIV                     :1;
        __IO   uint8_t  RESERVED0                :4;
} stc_canfd_fdecr_field_t;

typedef struct stc_canfd_fdesr_field
{
        __IO   uint8_t  SEI                      :1;
        __IO   uint8_t  DEI                      :1;
        __IO   uint8_t  RESERVED0                :6;
} stc_canfd_fdesr_field_t;

typedef struct stc_canfd_fdsear_field
{
    union {
        struct {
            __IO  uint16_t  SRA                  :16;
        };
        struct {
            __IO  uint16_t  SRA0                 :1;
            __IO  uint16_t  SRA1                 :1;
            __IO  uint16_t  SRA2                 :1;
            __IO  uint16_t  SRA3                 :1;
            __IO  uint16_t  SRA4                 :1;
            __IO  uint16_t  SRA5                 :1;
            __IO  uint16_t  SRA6                 :1;
            __IO  uint16_t  SRA7                 :1;
            __IO  uint16_t  SRA8                 :1;
            __IO  uint16_t  SRA9                 :1;
            __IO  uint16_t  SRA10                :1;
            __IO  uint16_t  SRA11                :1;
            __IO  uint16_t  SRA12                :1;
            __IO  uint16_t  SRA13                :1;
            __IO  uint16_t  SRA14                :1;
            __IO  uint16_t  SRA15                :1;
        };
    };
} stc_canfd_fdsear_field_t;

typedef struct stc_canfd_fdescr_field
{
        __IO   uint8_t  SEIC                     :1;
        __IO   uint8_t  DEIC                     :1;
        __IO   uint8_t  RESERVED0                :6;
} stc_canfd_fdescr_field_t;

typedef struct stc_canfd_fddear_field
{
    union {
        struct {
            __IO  uint16_t  DRA                  :16;
        };
        struct {
            __IO  uint16_t  DRA0                 :1;
            __IO  uint16_t  DRA1                 :1;
            __IO  uint16_t  DRA2                 :1;
            __IO  uint16_t  DRA3                 :1;
            __IO  uint16_t  DRA4                 :1;
            __IO  uint16_t  DRA5                 :1;
            __IO  uint16_t  DRA6                 :1;
            __IO  uint16_t  DRA7                 :1;
            __IO  uint16_t  DRA8                 :1;
            __IO  uint16_t  DRA9                 :1;
            __IO  uint16_t  DRA10                :1;
            __IO  uint16_t  DRA11                :1;
            __IO  uint16_t  DRA12                :1;
            __IO  uint16_t  DRA13                :1;
            __IO  uint16_t  DRA14                :1;
            __IO  uint16_t  DRA15                :1;
        };
    };
} stc_canfd_fddear_field_t;

typedef struct stc_canfd_tscntr_field
{
        __IO  uint16_t  CCLR                     :1;
        __IO  uint16_t  RESERVED0                :15;
} stc_canfd_tscntr_field_t;

typedef struct stc_canfd_tsmdr_field
{
        __IO  uint16_t  CNTEN                    :1;
        __IO  uint16_t  RESERVED0                :15;
} stc_canfd_tsmdr_field_t;

typedef struct stc_canfd_tsdivr_field
{
    union {
        struct {
            __IO  uint32_t  CDIV                 :16;
            __IO  uint32_t  RESERVED0            :16;
        };
        struct {
            __IO  uint32_t  CDIV0                :1;
            __IO  uint32_t  CDIV1                :1;
            __IO  uint32_t  CDIV2                :1;
            __IO  uint32_t  CDIV3                :1;
            __IO  uint32_t  CDIV4                :1;
            __IO  uint32_t  CDIV5                :1;
            __IO  uint32_t  CDIV6                :1;
            __IO  uint32_t  CDIV7                :1;
            __IO  uint32_t  CDIV8                :1;
            __IO  uint32_t  CDIV9                :1;
            __IO  uint32_t  CDIV10               :1;
            __IO  uint32_t  CDIV11               :1;
            __IO  uint32_t  CDIV12               :1;
            __IO  uint32_t  CDIV13               :1;
            __IO  uint32_t  CDIV14               :1;
            __IO  uint32_t  CDIV15               :1;
            __IO  uint32_t  RESERVED1            :16;
        };
    };
} stc_canfd_tsdivr_field_t;

typedef struct stc_canfd_tscdtr_field
{
    union {
        struct {
            __IO  uint16_t  CNT                  :16;
        };
        struct {
            __IO  uint16_t  CNT0                 :1;
            __IO  uint16_t  CNT1                 :1;
            __IO  uint16_t  CNT2                 :1;
            __IO  uint16_t  CNT3                 :1;
            __IO  uint16_t  CNT4                 :1;
            __IO  uint16_t  CNT5                 :1;
            __IO  uint16_t  CNT6                 :1;
            __IO  uint16_t  CNT7                 :1;
            __IO  uint16_t  CNT8                 :1;
            __IO  uint16_t  CNT9                 :1;
            __IO  uint16_t  CNT10                :1;
            __IO  uint16_t  CNT11                :1;
            __IO  uint16_t  CNT12                :1;
            __IO  uint16_t  CNT13                :1;
            __IO  uint16_t  CNT14                :1;
            __IO  uint16_t  CNT15                :1;
        };
    };
} stc_canfd_tscdtr_field_t;

typedef struct stc_canfd_tscpclr_field
{
    union {
        struct {
            __IO  uint16_t  CMP                  :16;
        };
        struct {
            __IO  uint16_t  CMP0                 :1;
            __IO  uint16_t  CMP1                 :1;
            __IO  uint16_t  CMP2                 :1;
            __IO  uint16_t  CMP3                 :1;
            __IO  uint16_t  CMP4                 :1;
            __IO  uint16_t  CMP5                 :1;
            __IO  uint16_t  CMP6                 :1;
            __IO  uint16_t  CMP7                 :1;
            __IO  uint16_t  CMP8                 :1;
            __IO  uint16_t  CMP9                 :1;
            __IO  uint16_t  CMP10                :1;
            __IO  uint16_t  CMP11                :1;
            __IO  uint16_t  CMP12                :1;
            __IO  uint16_t  CMP13                :1;
            __IO  uint16_t  CMP14                :1;
            __IO  uint16_t  CMP15                :1;
        };
    };
} stc_canfd_tscpclr_field_t;

/*******************************************************************************
* CANPRES_MODULE
*******************************************************************************/
typedef struct stc_canpres_canpre_field
{
    union {
        struct {
            __IO   uint8_t  CANPRE               :4;
            __IO   uint8_t  RESERVED0            :4;
        };
        struct {
            __IO   uint8_t  CANPRE0              :1;
            __IO   uint8_t  CANPRE1              :1;
            __IO   uint8_t  CANPRE2              :1;
            __IO   uint8_t  CANPRE3              :1;
            __IO   uint8_t  RESERVED1            :4;
        };
    };
} stc_canpres_canpre_field_t;

/*******************************************************************************
* CLK_GATING_MODULE
*******************************************************************************/
typedef struct stc_clk_gating_cken0_field
{
        __IO  uint32_t  MFSCK0                   :1;
        __IO  uint32_t  MFSCK1                   :1;
        __IO  uint32_t  MFSCK2                   :1;
        __IO  uint32_t  MFSCK3                   :1;
        __IO  uint32_t  MFSCK4                   :1;
        __IO  uint32_t  MFSCK5                   :1;
        __IO  uint32_t  MFSCK6                   :1;
        __IO  uint32_t  MFSCK7                   :1;
        __IO  uint32_t  MFSCK8                   :1;
        __IO  uint32_t  MFSCK9                   :1;
        __IO  uint32_t  MFSCK10                  :1;
        __IO  uint32_t  MFSCK11                  :1;
        __IO  uint32_t  MFSCK12                  :1;
        __IO  uint32_t  MFSCK13                  :1;
        __IO  uint32_t  MFSCK14                  :1;
        __IO  uint32_t  MFSCK15                  :1;
        __IO  uint32_t  ADCCK0                   :1;
        __IO  uint32_t  ADCCK1                   :1;
        __IO  uint32_t  ADCCK2                   :1;
        __IO  uint32_t  ADCCK3                   :1;
        __IO  uint32_t  RESERVED0                :4;
        __IO  uint32_t  DMACK                    :1;
        __IO  uint32_t  RESERVED1                :1;
        __IO  uint32_t  EXBCK                    :1;
        __IO  uint32_t  RESERVED2                :1;
        __IO  uint32_t  GIOCK                    :1;
        __IO  uint32_t  RESERVED3                :3;
} stc_clk_gating_cken0_field_t;

typedef struct stc_clk_gating_mrst0_field
{
        __IO  uint32_t  MFSRST0                  :1;
        __IO  uint32_t  MFSRST1                  :1;
        __IO  uint32_t  MFSRST2                  :1;
        __IO  uint32_t  MFSRST3                  :1;
        __IO  uint32_t  MFSRST4                  :1;
        __IO  uint32_t  MFSRST5                  :1;
        __IO  uint32_t  MFSRST6                  :1;
        __IO  uint32_t  MFSRST7                  :1;
        __IO  uint32_t  MFSRST8                  :1;
        __IO  uint32_t  MFSRST9                  :1;
        __IO  uint32_t  MFSRST10                 :1;
        __IO  uint32_t  MFSRST11                 :1;
        __IO  uint32_t  MFSRST12                 :1;
        __IO  uint32_t  MFSRST13                 :1;
        __IO  uint32_t  MFSRST14                 :1;
        __IO  uint32_t  MFSRST15                 :1;
        __IO  uint32_t  ADCRST0                  :1;
        __IO  uint32_t  ADCRST1                  :1;
        __IO  uint32_t  ADCRST2                  :1;
        __IO  uint32_t  ADCRST3                  :1;
        __IO  uint32_t  RESERVED0                :4;
        __IO  uint32_t  DMARST                   :1;
        __IO  uint32_t  RESERVED1                :1;
        __IO  uint32_t  EXBRST                   :1;
        __IO  uint32_t  RESERVED2                :5;
} stc_clk_gating_mrst0_field_t;

typedef struct stc_clk_gating_cken1_field
{
        __IO  uint32_t  BTMCK0                   :1;
        __IO  uint32_t  BTMCK1                   :1;
        __IO  uint32_t  BTMCK2                   :1;
        __IO  uint32_t  BTMCK3                   :1;
        __IO  uint32_t  RESERVED0                :4;
        __IO  uint32_t  MFTCK0                   :1;
        __IO  uint32_t  MFTCK1                   :1;
        __IO  uint32_t  MFTCK2                   :1;
        __IO  uint32_t  MFTCK3                   :1;
        __IO  uint32_t  RESERVED1                :4;
        __IO  uint32_t  QDUCK0                   :1;
        __IO  uint32_t  QDUCK1                   :1;
        __IO  uint32_t  QDUCK2                   :1;
        __IO  uint32_t  QDUCK3                   :1;
        __IO  uint32_t  RESERVED2                :12;
} stc_clk_gating_cken1_field_t;

typedef struct stc_clk_gating_mrst1_field
{
        __IO  uint32_t  BTMRST0                  :1;
        __IO  uint32_t  BTMRST1                  :1;
        __IO  uint32_t  BTMRST2                  :1;
        __IO  uint32_t  BTMRST3                  :1;
        __IO  uint32_t  RESERVED0                :4;
        __IO  uint32_t  MFTRST0                  :1;
        __IO  uint32_t  MFTRST1                  :1;
        __IO  uint32_t  MFTRST2                  :1;
        __IO  uint32_t  MFTRST3                  :1;
        __IO  uint32_t  RESERVED1                :4;
        __IO  uint32_t  QDURST0                  :1;
        __IO  uint32_t  QDURST1                  :1;
        __IO  uint32_t  QDURST2                  :1;
        __IO  uint32_t  QDURST3                  :1;
        __IO  uint32_t  RESERVED2                :12;
} stc_clk_gating_mrst1_field_t;

typedef struct stc_clk_gating_cken2_field
{
        __IO  uint32_t  USBCK0                   :1;
        __IO  uint32_t  USBCK1                   :1;
        __IO  uint32_t  RESERVED0                :2;
        __IO  uint32_t  CANCK0                   :1;
        __IO  uint32_t  CANCK1                   :1;
        __IO  uint32_t  CANCK2                   :1;
        __IO  uint32_t  RESERVED1                :1;
        __IO  uint32_t  SDCCK                    :1;
        __IO  uint32_t  RESERVED2                :7;
        __IO  uint32_t  I2SCK0                   :1;
        __IO  uint32_t  I2SCK1                   :1;
        __IO  uint32_t  RESERVED3                :2;
        __IO  uint32_t  PCRCCK                   :1;
        __IO  uint32_t  RESERVED4                :3;
        __IO  uint32_t  CECCK0                   :1;
        __IO  uint32_t  CECCK1                   :1;
        __IO  uint32_t  RESERVED5                :2;
        __IO  uint32_t  HSSPICK                  :1;
        __IO  uint32_t  RESERVED6                :3;
} stc_clk_gating_cken2_field_t;

typedef struct stc_clk_gating_mrst2_field
{
        __IO  uint32_t  USBRST0                  :1;
        __IO  uint32_t  USBRST1                  :1;
        __IO  uint32_t  RESERVED0                :2;
        __IO  uint32_t  CANRST0                  :1;
        __IO  uint32_t  CANRST1                  :1;
        __IO  uint32_t  CANRST2                  :1;
        __IO  uint32_t  RESERVED1                :1;
        __IO  uint32_t  SDCRST                   :1;
        __IO  uint32_t  RESERVED2                :7;
        __IO  uint32_t  I2SRST0                  :1;
        __IO  uint32_t  I2SRST1                  :1;
        __IO  uint32_t  RESERVED3                :2;
        __IO  uint32_t  PCRCRST                  :1;
        __IO  uint32_t  RESERVED4                :3;
        __IO  uint32_t  CECRST0                  :1;
        __IO  uint32_t  CECRST1                  :1;
        __IO  uint32_t  RESERVED5                :2;
        __IO  uint32_t  HSSPIRST                 :1;
        __IO  uint32_t  RESERVED6                :3;
} stc_clk_gating_mrst2_field_t;

/*******************************************************************************
* CRC_MODULE
*******************************************************************************/
typedef struct stc_crc_crccr_field
{
        __IO   uint8_t  INIT                     :1;
        __IO   uint8_t  CRC32                    :1;
        __IO   uint8_t  LTLEND                   :1;
        __IO   uint8_t  LSBFST                   :1;
        __IO   uint8_t  CRCLTE                   :1;
        __IO   uint8_t  CRCLSF                   :1;
        __IO   uint8_t  FXOR                     :1;
        __IO   uint8_t  RESERVED0                :1;
} stc_crc_crccr_field_t;

typedef struct stc_crc_crcinit_field
{
    union {
        struct {
            __IO  uint32_t  D                    :32;
        };
        struct {
            __IO  uint32_t  D0                   :1;
            __IO  uint32_t  D1                   :1;
            __IO  uint32_t  D2                   :1;
            __IO  uint32_t  D3                   :1;
            __IO  uint32_t  D4                   :1;
            __IO  uint32_t  D5                   :1;
            __IO  uint32_t  D6                   :1;
            __IO  uint32_t  D7                   :1;
            __IO  uint32_t  D8                   :1;
            __IO  uint32_t  D9                   :1;
            __IO  uint32_t  D10                  :1;
            __IO  uint32_t  D11                  :1;
            __IO  uint32_t  D12                  :1;
            __IO  uint32_t  D13                  :1;
            __IO  uint32_t  D14                  :1;
            __IO  uint32_t  D15                  :1;
            __IO  uint32_t  D16                  :1;
            __IO  uint32_t  D17                  :1;
            __IO  uint32_t  D18                  :1;
            __IO  uint32_t  D19                  :1;
            __IO  uint32_t  D20                  :1;
            __IO  uint32_t  D21                  :1;
            __IO  uint32_t  D22                  :1;
            __IO  uint32_t  D23                  :1;
            __IO  uint32_t  D24                  :1;
            __IO  uint32_t  D25                  :1;
            __IO  uint32_t  D26                  :1;
            __IO  uint32_t  D27                  :1;
            __IO  uint32_t  D28                  :1;
            __IO  uint32_t  D29                  :1;
            __IO  uint32_t  D30                  :1;
            __IO  uint32_t  D31                  :1;
        };
    };
} stc_crc_crcinit_field_t;

typedef struct stc_crc_crcin_field
{
    union {
        struct {
            __IO  uint32_t  D                    :32;
        };
        struct {
            __IO  uint32_t  D0                   :1;
            __IO  uint32_t  D1                   :1;
            __IO  uint32_t  D2                   :1;
            __IO  uint32_t  D3                   :1;
            __IO  uint32_t  D4                   :1;
            __IO  uint32_t  D5                   :1;
            __IO  uint32_t  D6                   :1;
            __IO  uint32_t  D7                   :1;
            __IO  uint32_t  D8                   :1;
            __IO  uint32_t  D9                   :1;
            __IO  uint32_t  D10                  :1;
            __IO  uint32_t  D11                  :1;
            __IO  uint32_t  D12                  :1;
            __IO  uint32_t  D13                  :1;
            __IO  uint32_t  D14                  :1;
            __IO  uint32_t  D15                  :1;
            __IO  uint32_t  D16                  :1;
            __IO  uint32_t  D17                  :1;
            __IO  uint32_t  D18                  :1;
            __IO  uint32_t  D19                  :1;
            __IO  uint32_t  D20                  :1;
            __IO  uint32_t  D21                  :1;
            __IO  uint32_t  D22                  :1;
            __IO  uint32_t  D23                  :1;
            __IO  uint32_t  D24                  :1;
            __IO  uint32_t  D25                  :1;
            __IO  uint32_t  D26                  :1;
            __IO  uint32_t  D27                  :1;
            __IO  uint32_t  D28                  :1;
            __IO  uint32_t  D29                  :1;
            __IO  uint32_t  D30                  :1;
            __IO  uint32_t  D31                  :1;
        };
    };
} stc_crc_crcin_field_t;

typedef struct stc_crc_crcr_field
{
    union {
        struct {
            __IO  uint32_t  D                    :32;
        };
        struct {
            __IO  uint32_t  D0                   :1;
            __IO  uint32_t  D1                   :1;
            __IO  uint32_t  D2                   :1;
            __IO  uint32_t  D3                   :1;
            __IO  uint32_t  D4                   :1;
            __IO  uint32_t  D5                   :1;
            __IO  uint32_t  D6                   :1;
            __IO  uint32_t  D7                   :1;
            __IO  uint32_t  D8                   :1;
            __IO  uint32_t  D9                   :1;
            __IO  uint32_t  D10                  :1;
            __IO  uint32_t  D11                  :1;
            __IO  uint32_t  D12                  :1;
            __IO  uint32_t  D13                  :1;
            __IO  uint32_t  D14                  :1;
            __IO  uint32_t  D15                  :1;
            __IO  uint32_t  D16                  :1;
            __IO  uint32_t  D17                  :1;
            __IO  uint32_t  D18                  :1;
            __IO  uint32_t  D19                  :1;
            __IO  uint32_t  D20                  :1;
            __IO  uint32_t  D21                  :1;
            __IO  uint32_t  D22                  :1;
            __IO  uint32_t  D23                  :1;
            __IO  uint32_t  D24                  :1;
            __IO  uint32_t  D25                  :1;
            __IO  uint32_t  D26                  :1;
            __IO  uint32_t  D27                  :1;
            __IO  uint32_t  D28                  :1;
            __IO  uint32_t  D29                  :1;
            __IO  uint32_t  D30                  :1;
            __IO  uint32_t  D31                  :1;
        };
    };
} stc_crc_crcr_field_t;

/*******************************************************************************
* CRG_MODULE
*******************************************************************************/
typedef struct stc_crg_scm_ctl_field
{
    union {
        struct {
            __IO  uint32_t  RESERVED0            :1;
            __IO  uint32_t  MOSCE                :1;
            __IO  uint32_t  RESERVED1            :1;
            __IO  uint32_t  SOSCE                :1;
            __IO  uint32_t  PLLE                 :1;
            __IO  uint32_t  RCS                  :3;
            __IO  uint32_t  RESERVED3            :24;
        };
        struct {
            __IO  uint32_t  RESERVED2            :5;
            __IO  uint32_t  RCS0                 :1;
            __IO  uint32_t  RCS1                 :1;
            __IO  uint32_t  RCS2                 :1;
            __IO  uint32_t  RESERVED4            :24;
        };
    };
} stc_crg_scm_ctl_field_t;

typedef struct stc_crg_scm_str_field
{
    union {
        struct {
            __IO  uint32_t  RESERVED0            :1;
            __IO  uint32_t  MORDY                :1;
            __IO  uint32_t  RESERVED1            :1;
            __IO  uint32_t  SORDY                :1;
            __IO  uint32_t  PLRDY                :1;
            __IO  uint32_t  RCM                  :3;
            __IO  uint32_t  RESERVED3            :24;
        };
        struct {
            __IO  uint32_t  RESERVED2            :5;
            __IO  uint32_t  RCM0                 :1;
            __IO  uint32_t  RCM1                 :1;
            __IO  uint32_t  RCM2                 :1;
            __IO  uint32_t  RESERVED4            :24;
        };
    };
} stc_crg_scm_str_field_t;

typedef struct stc_crg_stb_ctl_field
{
    union {
        struct {
            __IO  uint32_t  STM                  :2;
            __IO  uint32_t  DSTM                 :1;
            __IO  uint32_t  RESERVED0            :1;
            __IO  uint32_t  SPL                  :1;
            __IO  uint32_t  RESERVED1            :11;
            __IO  uint32_t  KEY                  :16;
        };
        struct {
            __IO  uint32_t  STM0                 :1;
            __IO  uint32_t  STM1                 :1;
            __IO  uint32_t  RESERVED2            :14;
            __IO  uint32_t  KEY0                 :1;
            __IO  uint32_t  KEY1                 :1;
            __IO  uint32_t  KEY2                 :1;
            __IO  uint32_t  KEY3                 :1;
            __IO  uint32_t  KEY4                 :1;
            __IO  uint32_t  KEY5                 :1;
            __IO  uint32_t  KEY6                 :1;
            __IO  uint32_t  KEY7                 :1;
            __IO  uint32_t  KEY8                 :1;
            __IO  uint32_t  KEY9                 :1;
            __IO  uint32_t  KEY10                :1;
            __IO  uint32_t  KEY11                :1;
            __IO  uint32_t  KEY12                :1;
            __IO  uint32_t  KEY13                :1;
            __IO  uint32_t  KEY14                :1;
            __IO  uint32_t  KEY15                :1;
        };
    };
} stc_crg_stb_ctl_field_t;

typedef struct stc_crg_rst_str_field
{
        __IO  uint32_t  PONR                     :1;
        __IO  uint32_t  INITX                    :1;
        __IO  uint32_t  RESERVED0                :2;
        __IO  uint32_t  SWDT                     :1;
        __IO  uint32_t  HWDT                     :1;
        __IO  uint32_t  CSVR                     :1;
        __IO  uint32_t  FCSR                     :1;
        __IO  uint32_t  SRST                     :1;
        __IO  uint32_t  RESERVED1                :23;
} stc_crg_rst_str_field_t;

typedef struct stc_crg_bsc_psr_field
{
    union {
        struct {
            __IO  uint32_t  BSR                  :3;
            __IO  uint32_t  RESERVED0            :29;
        };
        struct {
            __IO  uint32_t  BSR0                 :1;
            __IO  uint32_t  BSR1                 :1;
            __IO  uint32_t  BSR2                 :1;
            __IO  uint32_t  RESERVED1            :29;
        };
    };
} stc_crg_bsc_psr_field_t;

typedef struct stc_crg_apbc0_psr_field
{
    union {
        struct {
            __IO  uint32_t  APBC0                :2;
            __IO  uint32_t  RESERVED0            :30;
        };
        struct {
            __IO  uint32_t  APBC00               :1;
            __IO  uint32_t  APBC01               :1;
            __IO  uint32_t  RESERVED1            :30;
        };
    };
} stc_crg_apbc0_psr_field_t;

typedef struct stc_crg_apbc1_psr_field
{
    union {
        struct {
            __IO  uint32_t  APBC1                :2;
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  APBC1RST             :1;
            __IO  uint32_t  RESERVED1            :2;
            __IO  uint32_t  APBC1EN              :1;
            __IO  uint32_t  RESERVED2            :24;
        };
        struct {
            __IO  uint32_t  APBC10               :1;
            __IO  uint32_t  APBC11               :1;
            __IO  uint32_t  RESERVED3            :30;
        };
    };
} stc_crg_apbc1_psr_field_t;

typedef struct stc_crg_apbc2_psr_field
{
    union {
        struct {
            __IO  uint32_t  APBC2                :2;
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  APBC2RST             :1;
            __IO  uint32_t  RESERVED1            :2;
            __IO  uint32_t  APBC2EN              :1;
            __IO  uint32_t  RESERVED2            :24;
        };
        struct {
            __IO  uint32_t  APBC20               :1;
            __IO  uint32_t  APBC21               :1;
            __IO  uint32_t  RESERVED3            :30;
        };
    };
} stc_crg_apbc2_psr_field_t;

typedef struct stc_crg_swc_psr_field
{
    union {
        struct {
            __IO  uint32_t  SWDS                 :2;
            __IO  uint32_t  RESERVED0            :30;
        };
        struct {
            __IO  uint32_t  SWDS0                :1;
            __IO  uint32_t  SWDS1                :1;
            __IO  uint32_t  RESERVED1            :30;
        };
    };
} stc_crg_swc_psr_field_t;

typedef struct stc_crg_ttc_psr_field
{
    union {
        struct {
            __IO  uint32_t  TTC                  :2;
            __IO  uint32_t  RESERVED0            :30;
        };
        struct {
            __IO  uint32_t  TTC0                 :1;
            __IO  uint32_t  TTC1                 :1;
            __IO  uint32_t  RESERVED1            :30;
        };
    };
} stc_crg_ttc_psr_field_t;

typedef struct stc_crg_csw_tmr_field
{
    union {
        struct {
            __IO  uint32_t  MOWT                 :4;
            __IO  uint32_t  SOWT                 :4;
            __IO  uint32_t  RESERVED0            :24;
        };
        struct {
            __IO  uint32_t  MOWT0                :1;
            __IO  uint32_t  MOWT1                :1;
            __IO  uint32_t  MOWT2                :1;
            __IO  uint32_t  MOWT3                :1;
            __IO  uint32_t  SOWT0                :1;
            __IO  uint32_t  SOWT1                :1;
            __IO  uint32_t  SOWT2                :1;
            __IO  uint32_t  SOWT3                :1;
            __IO  uint32_t  RESERVED1            :24;
        };
    };
} stc_crg_csw_tmr_field_t;

typedef struct stc_crg_psw_tmr_field
{
    union {
        struct {
            __IO  uint32_t  POWT                 :3;
            __IO  uint32_t  RESERVED0            :1;
            __IO  uint32_t  PINC                 :1;
            __IO  uint32_t  RESERVED1            :27;
        };
        struct {
            __IO  uint32_t  POWT0                :1;
            __IO  uint32_t  POWT1                :1;
            __IO  uint32_t  POWT2                :1;
            __IO  uint32_t  RESERVED2            :29;
        };
    };
} stc_crg_psw_tmr_field_t;

typedef struct stc_crg_pll_ctl1_field
{
    union {
        struct {
            __IO  uint32_t  PLLM                 :4;
            __IO  uint32_t  PLLK                 :4;
            __IO  uint32_t  RESERVED0            :24;
        };
        struct {
            __IO  uint32_t  PLLM0                :1;
            __IO  uint32_t  PLLM1                :1;
            __IO  uint32_t  PLLM2                :1;
            __IO  uint32_t  PLLM3                :1;
            __IO  uint32_t  PLLK0                :1;
            __IO  uint32_t  PLLK1                :1;
            __IO  uint32_t  PLLK2                :1;
            __IO  uint32_t  PLLK3                :1;
            __IO  uint32_t  RESERVED1            :24;
        };
    };
} stc_crg_pll_ctl1_field_t;

typedef struct stc_crg_pll_ctl2_field
{
    union {
        struct {
            __IO  uint32_t  PLLN                 :6;
            __IO  uint32_t  RESERVED0            :26;
        };
        struct {
            __IO  uint32_t  PLLN0                :1;
            __IO  uint32_t  PLLN1                :1;
            __IO  uint32_t  PLLN2                :1;
            __IO  uint32_t  PLLN3                :1;
            __IO  uint32_t  PLLN4                :1;
            __IO  uint32_t  PLLN5                :1;
            __IO  uint32_t  RESERVED1            :26;
        };
    };
} stc_crg_pll_ctl2_field_t;

typedef struct stc_crg_csv_ctl_field
{
    union {
        struct {
            __IO  uint32_t  MCSVE                :1;
            __IO  uint32_t  SCSVE                :1;
            __IO  uint32_t  RESERVED0            :6;
            __IO  uint32_t  FCSDE                :1;
            __IO  uint32_t  FCSRE                :1;
            __IO  uint32_t  RESERVED1            :2;
            __IO  uint32_t  FCD                  :3;
            __IO  uint32_t  RESERVED3            :17;
        };
        struct {
            __IO  uint32_t  RESERVED2            :12;
            __IO  uint32_t  FCD0                 :1;
            __IO  uint32_t  FCD1                 :1;
            __IO  uint32_t  FCD2                 :1;
            __IO  uint32_t  RESERVED4            :17;
        };
    };
} stc_crg_csv_ctl_field_t;

typedef struct stc_crg_csv_str_field
{
        __IO  uint32_t  MCMF                     :1;
        __IO  uint32_t  SCMF                     :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_crg_csv_str_field_t;

typedef struct stc_crg_fcswh_ctl_field
{
    union {
        struct {
            __IO  uint32_t  FWH                  :16;
            __IO  uint32_t  RESERVED0            :16;
        };
        struct {
            __IO  uint32_t  FWH0                 :1;
            __IO  uint32_t  FWH1                 :1;
            __IO  uint32_t  FWH2                 :1;
            __IO  uint32_t  FWH3                 :1;
            __IO  uint32_t  FWH4                 :1;
            __IO  uint32_t  FWH5                 :1;
            __IO  uint32_t  FWH6                 :1;
            __IO  uint32_t  FWH7                 :1;
            __IO  uint32_t  FWH8                 :1;
            __IO  uint32_t  FWH9                 :1;
            __IO  uint32_t  FWH10                :1;
            __IO  uint32_t  FWH11                :1;
            __IO  uint32_t  FWH12                :1;
            __IO  uint32_t  FWH13                :1;
            __IO  uint32_t  FWH14                :1;
            __IO  uint32_t  FWH15                :1;
            __IO  uint32_t  RESERVED1            :16;
        };
    };
} stc_crg_fcswh_ctl_field_t;

typedef struct stc_crg_fcswl_ctl_field
{
    union {
        struct {
            __IO  uint32_t  FWL                  :16;
            __IO  uint32_t  RESERVED0            :16;
        };
        struct {
            __IO  uint32_t  FWL0                 :1;
            __IO  uint32_t  FWL1                 :1;
            __IO  uint32_t  FWL2                 :1;
            __IO  uint32_t  FWL3                 :1;
            __IO  uint32_t  FWL4                 :1;
            __IO  uint32_t  FWL5                 :1;
            __IO  uint32_t  FWL6                 :1;
            __IO  uint32_t  FWL7                 :1;
            __IO  uint32_t  FWL8                 :1;
            __IO  uint32_t  FWL9                 :1;
            __IO  uint32_t  FWL10                :1;
            __IO  uint32_t  FWL11                :1;
            __IO  uint32_t  FWL12                :1;
            __IO  uint32_t  FWL13                :1;
            __IO  uint32_t  FWL14                :1;
            __IO  uint32_t  FWL15                :1;
            __IO  uint32_t  RESERVED1            :16;
        };
    };
} stc_crg_fcswl_ctl_field_t;

typedef struct stc_crg_fcswd_ctl_field
{
    union {
        struct {
            __IO  uint32_t  FWD                  :16;
            __IO  uint32_t  RESERVED0            :16;
        };
        struct {
            __IO  uint32_t  FWD0                 :1;
            __IO  uint32_t  FWD1                 :1;
            __IO  uint32_t  FWD2                 :1;
            __IO  uint32_t  FWD3                 :1;
            __IO  uint32_t  FWD4                 :1;
            __IO  uint32_t  FWD5                 :1;
            __IO  uint32_t  FWD6                 :1;
            __IO  uint32_t  FWD7                 :1;
            __IO  uint32_t  FWD8                 :1;
            __IO  uint32_t  FWD9                 :1;
            __IO  uint32_t  FWD10                :1;
            __IO  uint32_t  FWD11                :1;
            __IO  uint32_t  FWD12                :1;
            __IO  uint32_t  FWD13                :1;
            __IO  uint32_t  FWD14                :1;
            __IO  uint32_t  FWD15                :1;
            __IO  uint32_t  RESERVED1            :16;
        };
    };
} stc_crg_fcswd_ctl_field_t;

typedef struct stc_crg_dbwdt_ctl_field
{
        __IO  uint32_t  RESERVED0                :5;
        __IO  uint32_t  DPSWBE                   :1;
        __IO  uint32_t  RESERVED1                :1;
        __IO  uint32_t  DPHWBE                   :1;
        __IO  uint32_t  RESERVED2                :24;
} stc_crg_dbwdt_ctl_field_t;

typedef struct stc_crg_int_enr_field
{
        __IO  uint32_t  MCSE                     :1;
        __IO  uint32_t  SCSE                     :1;
        __IO  uint32_t  PCSE                     :1;
        __IO  uint32_t  RESERVED0                :2;
        __IO  uint32_t  FCSE                     :1;
        __IO  uint32_t  RESERVED1                :26;
} stc_crg_int_enr_field_t;

typedef struct stc_crg_int_str_field
{
        __IO  uint32_t  MCSI                     :1;
        __IO  uint32_t  SCSI                     :1;
        __IO  uint32_t  PCSI                     :1;
        __IO  uint32_t  RESERVED0                :2;
        __IO  uint32_t  FCSI                     :1;
        __IO  uint32_t  RESERVED1                :26;
} stc_crg_int_str_field_t;

typedef struct stc_crg_int_clr_field
{
        __IO  uint32_t  MCSC                     :1;
        __IO  uint32_t  SCSC                     :1;
        __IO  uint32_t  PCSC                     :1;
        __IO  uint32_t  RESERVED0                :2;
        __IO  uint32_t  FCSC                     :1;
        __IO  uint32_t  RESERVED1                :26;
} stc_crg_int_clr_field_t;

typedef struct stc_crg_pllcg_ctl_field
{
    union {
        struct {
            __IO  uint32_t  PLLCGEN              :1;
            __IO  uint32_t  PLLCGSTR             :1;
            __IO  uint32_t  RESERVED0            :4;
            __IO  uint32_t  PLLCGSTS             :2;
            __IO  uint32_t  PLLCGSSN             :6;
            __IO  uint32_t  PLLCGSTP             :2;
            __IO  uint32_t  PLLCGLP              :8;
            __IO  uint32_t  RESERVED2            :8;
        };
        struct {
            __IO  uint32_t  RESERVED1            :6;
            __IO  uint32_t  PLLCGSTS0            :1;
            __IO  uint32_t  PLLCGSTS1            :1;
            __IO  uint32_t  PLLCGSSN0            :1;
            __IO  uint32_t  PLLCGSSN1            :1;
            __IO  uint32_t  PLLCGSSN2            :1;
            __IO  uint32_t  PLLCGSSN3            :1;
            __IO  uint32_t  PLLCGSSN4            :1;
            __IO  uint32_t  PLLCGSSN5            :1;
            __IO  uint32_t  PLLCGSTP0            :1;
            __IO  uint32_t  PLLCGSTP1            :1;
            __IO  uint32_t  PLLCGLP0             :1;
            __IO  uint32_t  PLLCGLP1             :1;
            __IO  uint32_t  PLLCGLP2             :1;
            __IO  uint32_t  PLLCGLP3             :1;
            __IO  uint32_t  PLLCGLP4             :1;
            __IO  uint32_t  PLLCGLP5             :1;
            __IO  uint32_t  PLLCGLP6             :1;
            __IO  uint32_t  PLLCGLP7             :1;
            __IO  uint32_t  RESERVED3            :8;
        };
    };
} stc_crg_pllcg_ctl_field_t;

/*******************************************************************************
* CRTRIM_MODULE
*******************************************************************************/
typedef struct stc_crtrim_mcr_psr_field
{
    union {
        struct {
            __IO   uint8_t  CSR                  :3;
            __IO   uint8_t  RESERVED0            :5;
        };
        struct {
            __IO   uint8_t  CSR0                 :1;
            __IO   uint8_t  CSR1                 :1;
            __IO   uint8_t  CSR2                 :1;
            __IO   uint8_t  RESERVED1            :5;
        };
    };
} stc_crtrim_mcr_psr_field_t;

typedef struct stc_crtrim_mcr_ftrm_field
{
    union {
        struct {
            __IO  uint32_t  TRD                  :10;
            __IO  uint32_t  RESERVED0            :22;
        };
        struct {
            __IO  uint32_t  TRD0                 :1;
            __IO  uint32_t  TRD1                 :1;
            __IO  uint32_t  TRD2                 :1;
            __IO  uint32_t  TRD3                 :1;
            __IO  uint32_t  TRD4                 :1;
            __IO  uint32_t  TRD5                 :1;
            __IO  uint32_t  TRD6                 :1;
            __IO  uint32_t  TRD7                 :1;
            __IO  uint32_t  TRD8                 :1;
            __IO  uint32_t  TRD9                 :1;
            __IO  uint32_t  RESERVED1            :22;
        };
    };
} stc_crtrim_mcr_ftrm_field_t;

typedef struct stc_crtrim_mcr_ttrm_field
{
    union {
        struct {
            __IO  uint32_t  TRT                  :5;
            __IO  uint32_t  RESERVED0            :27;
        };
        struct {
            __IO  uint32_t  TRT0                 :1;
            __IO  uint32_t  TRT1                 :1;
            __IO  uint32_t  TRT2                 :1;
            __IO  uint32_t  TRT3                 :1;
            __IO  uint32_t  TRT4                 :1;
            __IO  uint32_t  RESERVED1            :27;
        };
    };
} stc_crtrim_mcr_ttrm_field_t;

typedef struct stc_crtrim_mcr_rlr_field
{
    union {
        struct {
            __IO  uint32_t  TRMLCK               :32;
        };
        struct {
            __IO  uint32_t  TRMLCK0              :1;
            __IO  uint32_t  TRMLCK1              :1;
            __IO  uint32_t  TRMLCK2              :1;
            __IO  uint32_t  TRMLCK3              :1;
            __IO  uint32_t  TRMLCK4              :1;
            __IO  uint32_t  TRMLCK5              :1;
            __IO  uint32_t  TRMLCK6              :1;
            __IO  uint32_t  TRMLCK7              :1;
            __IO  uint32_t  TRMLCK8              :1;
            __IO  uint32_t  TRMLCK9              :1;
            __IO  uint32_t  TRMLCK10             :1;
            __IO  uint32_t  TRMLCK11             :1;
            __IO  uint32_t  TRMLCK12             :1;
            __IO  uint32_t  TRMLCK13             :1;
            __IO  uint32_t  TRMLCK14             :1;
            __IO  uint32_t  TRMLCK15             :1;
            __IO  uint32_t  TRMLCK16             :1;
            __IO  uint32_t  TRMLCK17             :1;
            __IO  uint32_t  TRMLCK18             :1;
            __IO  uint32_t  TRMLCK19             :1;
            __IO  uint32_t  TRMLCK20             :1;
            __IO  uint32_t  TRMLCK21             :1;
            __IO  uint32_t  TRMLCK22             :1;
            __IO  uint32_t  TRMLCK23             :1;
            __IO  uint32_t  TRMLCK24             :1;
            __IO  uint32_t  TRMLCK25             :1;
            __IO  uint32_t  TRMLCK26             :1;
            __IO  uint32_t  TRMLCK27             :1;
            __IO  uint32_t  TRMLCK28             :1;
            __IO  uint32_t  TRMLCK29             :1;
            __IO  uint32_t  TRMLCK30             :1;
            __IO  uint32_t  TRMLCK31             :1;
        };
    };
} stc_crtrim_mcr_rlr_field_t;

/*******************************************************************************
* DAC_MODULE
*******************************************************************************/
typedef struct stc_dac_dacr_field
{
        __IO   uint8_t  DAE                      :1;
        __IO   uint8_t  DRDY                     :1;
        __IO   uint8_t  RESERVED0                :2;
        __IO   uint8_t  DAC10                    :1;
        __IO   uint8_t  DDAS                     :1;
        __IO   uint8_t  RESERVED1                :2;
} stc_dac_dacr_field_t;

typedef struct stc_dac_dadr_field
{
    union {
        struct {
            __IO  uint16_t  DA                   :12;
            __IO  uint16_t  RESERVED0            :4;
        };
        struct {
            __IO  uint16_t  DA0                  :1;
            __IO  uint16_t  DA1                  :1;
            __IO  uint16_t  DA2                  :1;
            __IO  uint16_t  DA3                  :1;
            __IO  uint16_t  DA4                  :1;
            __IO  uint16_t  DA5                  :1;
            __IO  uint16_t  DA6                  :1;
            __IO  uint16_t  DA7                  :1;
            __IO  uint16_t  DA8                  :1;
            __IO  uint16_t  DA9                  :1;
            __IO  uint16_t  DA10                 :1;
            __IO  uint16_t  DA11                 :1;
            __IO  uint16_t  RESERVED1            :4;
        };
    };
} stc_dac_dadr_field_t;

/*******************************************************************************
* DMAC_MODULE
*******************************************************************************/
typedef struct stc_dmac_dmacr_field
{
    union {
        struct {
            __IO  uint32_t  RESERVED0            :24;
            __IO  uint32_t  DH                   :4;
            __IO  uint32_t  PR                   :1;
            __IO  uint32_t  RESERVED2            :1;
            __IO  uint32_t  DS                   :1;
            __IO  uint32_t  DE                   :1;
        };
        struct {
            __IO  uint32_t  RESERVED1            :24;
            __IO  uint32_t  DH0                  :1;
            __IO  uint32_t  DH1                  :1;
            __IO  uint32_t  DH2                  :1;
            __IO  uint32_t  DH3                  :1;
            __IO  uint32_t  RESERVED3            :4;
        };
    };
} stc_dmac_dmacr_field_t;

typedef struct stc_dmac_dmaca0_field
{
    union {
        struct {
            __IO  uint32_t  TC                   :16;
            __IO  uint32_t  BC                   :4;
            __IO  uint32_t  RESERVED0            :3;
            __IO  uint32_t  IS                   :6;
            __IO  uint32_t  ST                   :1;
            __IO  uint32_t  PB                   :1;
            __IO  uint32_t  EB                   :1;
        };
        struct {
            __IO  uint32_t  TC0                  :1;
            __IO  uint32_t  TC1                  :1;
            __IO  uint32_t  TC2                  :1;
            __IO  uint32_t  TC3                  :1;
            __IO  uint32_t  TC4                  :1;
            __IO  uint32_t  TC5                  :1;
            __IO  uint32_t  TC6                  :1;
            __IO  uint32_t  TC7                  :1;
            __IO  uint32_t  TC8                  :1;
            __IO  uint32_t  TC9                  :1;
            __IO  uint32_t  TC10                 :1;
            __IO  uint32_t  TC11                 :1;
            __IO  uint32_t  TC12                 :1;
            __IO  uint32_t  TC13                 :1;
            __IO  uint32_t  TC14                 :1;
            __IO  uint32_t  TC15                 :1;
            __IO  uint32_t  BC0                  :1;
            __IO  uint32_t  BC1                  :1;
            __IO  uint32_t  BC2                  :1;
            __IO  uint32_t  BC3                  :1;
            __IO  uint32_t  RESERVED1            :3;
            __IO  uint32_t  IS0                  :1;
            __IO  uint32_t  IS1                  :1;
            __IO  uint32_t  IS2                  :1;
            __IO  uint32_t  IS3                  :1;
            __IO  uint32_t  IS4                  :1;
            __IO  uint32_t  IS5                  :1;
            __IO  uint32_t  RESERVED2            :3;
        };
    };
} stc_dmac_dmaca0_field_t;

typedef struct stc_dmac_dmacb0_field
{
    union {
        struct {
            __IO  uint32_t  EM                   :1;
            __IO  uint32_t  RESERVED0            :15;
            __IO  uint32_t  SS                   :3;
            __IO  uint32_t  CI                   :1;
            __IO  uint32_t  EI                   :1;
            __IO  uint32_t  RD                   :1;
            __IO  uint32_t  RS                   :1;
            __IO  uint32_t  RC                   :1;
            __IO  uint32_t  FD                   :1;
            __IO  uint32_t  FS                   :1;
            __IO  uint32_t  TW                   :2;
            __IO  uint32_t  MS                   :2;
            __IO  uint32_t  RESERVED3            :2;
        };
        struct {
            __IO  uint32_t  RESERVED1            :16;
            __IO  uint32_t  SS0                  :1;
            __IO  uint32_t  SS1                  :1;
            __IO  uint32_t  SS2                  :1;
            __IO  uint32_t  RESERVED2            :7;
            __IO  uint32_t  TW0                  :1;
            __IO  uint32_t  TW1                  :1;
            __IO  uint32_t  MS0                  :1;
            __IO  uint32_t  MS1                  :1;
            __IO  uint32_t  RESERVED4            :2;
        };
    };
} stc_dmac_dmacb0_field_t;

typedef struct stc_dmac_dmaca1_field
{
    union {
        struct {
            __IO  uint32_t  TC                   :16;
            __IO  uint32_t  BC                   :4;
            __IO  uint32_t  RESERVED0            :3;
            __IO  uint32_t  IS                   :6;
            __IO  uint32_t  ST                   :1;
            __IO  uint32_t  PB                   :1;
            __IO  uint32_t  EB                   :1;
        };
        struct {
            __IO  uint32_t  TC0                  :1;
            __IO  uint32_t  TC1                  :1;
            __IO  uint32_t  TC2                  :1;
            __IO  uint32_t  TC3                  :1;
            __IO  uint32_t  TC4                  :1;
            __IO  uint32_t  TC5                  :1;
            __IO  uint32_t  TC6                  :1;
            __IO  uint32_t  TC7                  :1;
            __IO  uint32_t  TC8                  :1;
            __IO  uint32_t  TC9                  :1;
            __IO  uint32_t  TC10                 :1;
            __IO  uint32_t  TC11                 :1;
            __IO  uint32_t  TC12                 :1;
            __IO  uint32_t  TC13                 :1;
            __IO  uint32_t  TC14                 :1;
            __IO  uint32_t  TC15                 :1;
            __IO  uint32_t  BC0                  :1;
            __IO  uint32_t  BC1                  :1;
            __IO  uint32_t  BC2                  :1;
            __IO  uint32_t  BC3                  :1;
            __IO  uint32_t  RESERVED1            :3;
            __IO  uint32_t  IS0                  :1;
            __IO  uint32_t  IS1                  :1;
            __IO  uint32_t  IS2                  :1;
            __IO  uint32_t  IS3                  :1;
            __IO  uint32_t  IS4                  :1;
            __IO  uint32_t  IS5                  :1;
            __IO  uint32_t  RESERVED2            :3;
        };
    };
} stc_dmac_dmaca1_field_t;

typedef struct stc_dmac_dmacb1_field
{
    union {
        struct {
            __IO  uint32_t  EM                   :1;
            __IO  uint32_t  RESERVED0            :15;
            __IO  uint32_t  SS                   :3;
            __IO  uint32_t  CI                   :1;
            __IO  uint32_t  EI                   :1;
            __IO  uint32_t  RD                   :1;
            __IO  uint32_t  RS                   :1;
            __IO  uint32_t  RC                   :1;
            __IO  uint32_t  FD                   :1;
            __IO  uint32_t  FS                   :1;
            __IO  uint32_t  TW                   :2;
            __IO  uint32_t  MS                   :2;
            __IO  uint32_t  RESERVED3            :2;
        };
        struct {
            __IO  uint32_t  RESERVED1            :16;
            __IO  uint32_t  SS0                  :1;
            __IO  uint32_t  SS1                  :1;
            __IO  uint32_t  SS2                  :1;
            __IO  uint32_t  RESERVED2            :7;
            __IO  uint32_t  TW0                  :1;
            __IO  uint32_t  TW1                  :1;
            __IO  uint32_t  MS0                  :1;
            __IO  uint32_t  MS1                  :1;
            __IO  uint32_t  RESERVED4            :2;
        };
    };
} stc_dmac_dmacb1_field_t;

typedef struct stc_dmac_dmaca2_field
{
    union {
        struct {
            __IO  uint32_t  TC                   :16;
            __IO  uint32_t  BC                   :4;
            __IO  uint32_t  RESERVED0            :3;
            __IO  uint32_t  IS                   :6;
            __IO  uint32_t  ST                   :1;
            __IO  uint32_t  PB                   :1;
            __IO  uint32_t  EB                   :1;
        };
        struct {
            __IO  uint32_t  TC0                  :1;
            __IO  uint32_t  TC1                  :1;
            __IO  uint32_t  TC2                  :1;
            __IO  uint32_t  TC3                  :1;
            __IO  uint32_t  TC4                  :1;
            __IO  uint32_t  TC5                  :1;
            __IO  uint32_t  TC6                  :1;
            __IO  uint32_t  TC7                  :1;
            __IO  uint32_t  TC8                  :1;
            __IO  uint32_t  TC9                  :1;
            __IO  uint32_t  TC10                 :1;
            __IO  uint32_t  TC11                 :1;
            __IO  uint32_t  TC12                 :1;
            __IO  uint32_t  TC13                 :1;
            __IO  uint32_t  TC14                 :1;
            __IO  uint32_t  TC15                 :1;
            __IO  uint32_t  BC0                  :1;
            __IO  uint32_t  BC1                  :1;
            __IO  uint32_t  BC2                  :1;
            __IO  uint32_t  BC3                  :1;
            __IO  uint32_t  RESERVED1            :3;
            __IO  uint32_t  IS0                  :1;
            __IO  uint32_t  IS1                  :1;
            __IO  uint32_t  IS2                  :1;
            __IO  uint32_t  IS3                  :1;
            __IO  uint32_t  IS4                  :1;
            __IO  uint32_t  IS5                  :1;
            __IO  uint32_t  RESERVED2            :3;
        };
    };
} stc_dmac_dmaca2_field_t;

typedef struct stc_dmac_dmacb2_field
{
    union {
        struct {
            __IO  uint32_t  EM                   :1;
            __IO  uint32_t  RESERVED0            :15;
            __IO  uint32_t  SS                   :3;
            __IO  uint32_t  CI                   :1;
            __IO  uint32_t  EI                   :1;
            __IO  uint32_t  RD                   :1;
            __IO  uint32_t  RS                   :1;
            __IO  uint32_t  RC                   :1;
            __IO  uint32_t  FD                   :1;
            __IO  uint32_t  FS                   :1;
            __IO  uint32_t  TW                   :2;
            __IO  uint32_t  MS                   :2;
            __IO  uint32_t  RESERVED3            :2;
        };
        struct {
            __IO  uint32_t  RESERVED1            :16;
            __IO  uint32_t  SS0                  :1;
            __IO  uint32_t  SS1                  :1;
            __IO  uint32_t  SS2                  :1;
            __IO  uint32_t  RESERVED2            :7;
            __IO  uint32_t  TW0                  :1;
            __IO  uint32_t  TW1                  :1;
            __IO  uint32_t  MS0                  :1;
            __IO  uint32_t  MS1                  :1;
            __IO  uint32_t  RESERVED4            :2;
        };
    };
} stc_dmac_dmacb2_field_t;

typedef struct stc_dmac_dmaca3_field
{
    union {
        struct {
            __IO  uint32_t  TC                   :16;
            __IO  uint32_t  BC                   :4;
            __IO  uint32_t  RESERVED0            :3;
            __IO  uint32_t  IS                   :6;
            __IO  uint32_t  ST                   :1;
            __IO  uint32_t  PB                   :1;
            __IO  uint32_t  EB                   :1;
        };
        struct {
            __IO  uint32_t  TC0                  :1;
            __IO  uint32_t  TC1                  :1;
            __IO  uint32_t  TC2                  :1;
            __IO  uint32_t  TC3                  :1;
            __IO  uint32_t  TC4                  :1;
            __IO  uint32_t  TC5                  :1;
            __IO  uint32_t  TC6                  :1;
            __IO  uint32_t  TC7                  :1;
            __IO  uint32_t  TC8                  :1;
            __IO  uint32_t  TC9                  :1;
            __IO  uint32_t  TC10                 :1;
            __IO  uint32_t  TC11                 :1;
            __IO  uint32_t  TC12                 :1;
            __IO  uint32_t  TC13                 :1;
            __IO  uint32_t  TC14                 :1;
            __IO  uint32_t  TC15                 :1;
            __IO  uint32_t  BC0                  :1;
            __IO  uint32_t  BC1                  :1;
            __IO  uint32_t  BC2                  :1;
            __IO  uint32_t  BC3                  :1;
            __IO  uint32_t  RESERVED1            :3;
            __IO  uint32_t  IS0                  :1;
            __IO  uint32_t  IS1                  :1;
            __IO  uint32_t  IS2                  :1;
            __IO  uint32_t  IS3                  :1;
            __IO  uint32_t  IS4                  :1;
            __IO  uint32_t  IS5                  :1;
            __IO  uint32_t  RESERVED2            :3;
        };
    };
} stc_dmac_dmaca3_field_t;

typedef struct stc_dmac_dmacb3_field
{
    union {
        struct {
            __IO  uint32_t  EM                   :1;
            __IO  uint32_t  RESERVED0            :15;
            __IO  uint32_t  SS                   :3;
            __IO  uint32_t  CI                   :1;
            __IO  uint32_t  EI                   :1;
            __IO  uint32_t  RD                   :1;
            __IO  uint32_t  RS                   :1;
            __IO  uint32_t  RC                   :1;
            __IO  uint32_t  FD                   :1;
            __IO  uint32_t  FS                   :1;
            __IO  uint32_t  TW                   :2;
            __IO  uint32_t  MS                   :2;
            __IO  uint32_t  RESERVED3            :2;
        };
        struct {
            __IO  uint32_t  RESERVED1            :16;
            __IO  uint32_t  SS0                  :1;
            __IO  uint32_t  SS1                  :1;
            __IO  uint32_t  SS2                  :1;
            __IO  uint32_t  RESERVED2            :7;
            __IO  uint32_t  TW0                  :1;
            __IO  uint32_t  TW1                  :1;
            __IO  uint32_t  MS0                  :1;
            __IO  uint32_t  MS1                  :1;
            __IO  uint32_t  RESERVED4            :2;
        };
    };
} stc_dmac_dmacb3_field_t;

typedef struct stc_dmac_dmaca4_field
{
    union {
        struct {
            __IO  uint32_t  TC                   :16;
            __IO  uint32_t  BC                   :4;
            __IO  uint32_t  RESERVED0            :3;
            __IO  uint32_t  IS                   :6;
            __IO  uint32_t  ST                   :1;
            __IO  uint32_t  PB                   :1;
            __IO  uint32_t  EB                   :1;
        };
        struct {
            __IO  uint32_t  TC0                  :1;
            __IO  uint32_t  TC1                  :1;
            __IO  uint32_t  TC2                  :1;
            __IO  uint32_t  TC3                  :1;
            __IO  uint32_t  TC4                  :1;
            __IO  uint32_t  TC5                  :1;
            __IO  uint32_t  TC6                  :1;
            __IO  uint32_t  TC7                  :1;
            __IO  uint32_t  TC8                  :1;
            __IO  uint32_t  TC9                  :1;
            __IO  uint32_t  TC10                 :1;
            __IO  uint32_t  TC11                 :1;
            __IO  uint32_t  TC12                 :1;
            __IO  uint32_t  TC13                 :1;
            __IO  uint32_t  TC14                 :1;
            __IO  uint32_t  TC15                 :1;
            __IO  uint32_t  BC0                  :1;
            __IO  uint32_t  BC1                  :1;
            __IO  uint32_t  BC2                  :1;
            __IO  uint32_t  BC3                  :1;
            __IO  uint32_t  RESERVED1            :3;
            __IO  uint32_t  IS0                  :1;
            __IO  uint32_t  IS1                  :1;
            __IO  uint32_t  IS2                  :1;
            __IO  uint32_t  IS3                  :1;
            __IO  uint32_t  IS4                  :1;
            __IO  uint32_t  IS5                  :1;
            __IO  uint32_t  RESERVED2            :3;
        };
    };
} stc_dmac_dmaca4_field_t;

typedef struct stc_dmac_dmacb4_field
{
    union {
        struct {
            __IO  uint32_t  EM                   :1;
            __IO  uint32_t  RESERVED0            :15;
            __IO  uint32_t  SS                   :3;
            __IO  uint32_t  CI                   :1;
            __IO  uint32_t  EI                   :1;
            __IO  uint32_t  RD                   :1;
            __IO  uint32_t  RS                   :1;
            __IO  uint32_t  RC                   :1;
            __IO  uint32_t  FD                   :1;
            __IO  uint32_t  FS                   :1;
            __IO  uint32_t  TW                   :2;
            __IO  uint32_t  MS                   :2;
            __IO  uint32_t  RESERVED3            :2;
        };
        struct {
            __IO  uint32_t  RESERVED1            :16;
            __IO  uint32_t  SS0                  :1;
            __IO  uint32_t  SS1                  :1;
            __IO  uint32_t  SS2                  :1;
            __IO  uint32_t  RESERVED2            :7;
            __IO  uint32_t  TW0                  :1;
            __IO  uint32_t  TW1                  :1;
            __IO  uint32_t  MS0                  :1;
            __IO  uint32_t  MS1                  :1;
            __IO  uint32_t  RESERVED4            :2;
        };
    };
} stc_dmac_dmacb4_field_t;

typedef struct stc_dmac_dmaca5_field
{
    union {
        struct {
            __IO  uint32_t  TC                   :16;
            __IO  uint32_t  BC                   :4;
            __IO  uint32_t  RESERVED0            :3;
            __IO  uint32_t  IS                   :6;
            __IO  uint32_t  ST                   :1;
            __IO  uint32_t  PB                   :1;
            __IO  uint32_t  EB                   :1;
        };
        struct {
            __IO  uint32_t  TC0                  :1;
            __IO  uint32_t  TC1                  :1;
            __IO  uint32_t  TC2                  :1;
            __IO  uint32_t  TC3                  :1;
            __IO  uint32_t  TC4                  :1;
            __IO  uint32_t  TC5                  :1;
            __IO  uint32_t  TC6                  :1;
            __IO  uint32_t  TC7                  :1;
            __IO  uint32_t  TC8                  :1;
            __IO  uint32_t  TC9                  :1;
            __IO  uint32_t  TC10                 :1;
            __IO  uint32_t  TC11                 :1;
            __IO  uint32_t  TC12                 :1;
            __IO  uint32_t  TC13                 :1;
            __IO  uint32_t  TC14                 :1;
            __IO  uint32_t  TC15                 :1;
            __IO  uint32_t  BC0                  :1;
            __IO  uint32_t  BC1                  :1;
            __IO  uint32_t  BC2                  :1;
            __IO  uint32_t  BC3                  :1;
            __IO  uint32_t  RESERVED1            :3;
            __IO  uint32_t  IS0                  :1;
            __IO  uint32_t  IS1                  :1;
            __IO  uint32_t  IS2                  :1;
            __IO  uint32_t  IS3                  :1;
            __IO  uint32_t  IS4                  :1;
            __IO  uint32_t  IS5                  :1;
            __IO  uint32_t  RESERVED2            :3;
        };
    };
} stc_dmac_dmaca5_field_t;

typedef struct stc_dmac_dmacb5_field
{
    union {
        struct {
            __IO  uint32_t  EM                   :1;
            __IO  uint32_t  RESERVED0            :15;
            __IO  uint32_t  SS                   :3;
            __IO  uint32_t  CI                   :1;
            __IO  uint32_t  EI                   :1;
            __IO  uint32_t  RD                   :1;
            __IO  uint32_t  RS                   :1;
            __IO  uint32_t  RC                   :1;
            __IO  uint32_t  FD                   :1;
            __IO  uint32_t  FS                   :1;
            __IO  uint32_t  TW                   :2;
            __IO  uint32_t  MS                   :2;
            __IO  uint32_t  RESERVED3            :2;
        };
        struct {
            __IO  uint32_t  RESERVED1            :16;
            __IO  uint32_t  SS0                  :1;
            __IO  uint32_t  SS1                  :1;
            __IO  uint32_t  SS2                  :1;
            __IO  uint32_t  RESERVED2            :7;
            __IO  uint32_t  TW0                  :1;
            __IO  uint32_t  TW1                  :1;
            __IO  uint32_t  MS0                  :1;
            __IO  uint32_t  MS1                  :1;
            __IO  uint32_t  RESERVED4            :2;
        };
    };
} stc_dmac_dmacb5_field_t;

typedef struct stc_dmac_dmaca6_field
{
    union {
        struct {
            __IO  uint32_t  TC                   :16;
            __IO  uint32_t  BC                   :4;
            __IO  uint32_t  RESERVED0            :3;
            __IO  uint32_t  IS                   :6;
            __IO  uint32_t  ST                   :1;
            __IO  uint32_t  PB                   :1;
            __IO  uint32_t  EB                   :1;
        };
        struct {
            __IO  uint32_t  TC0                  :1;
            __IO  uint32_t  TC1                  :1;
            __IO  uint32_t  TC2                  :1;
            __IO  uint32_t  TC3                  :1;
            __IO  uint32_t  TC4                  :1;
            __IO  uint32_t  TC5                  :1;
            __IO  uint32_t  TC6                  :1;
            __IO  uint32_t  TC7                  :1;
            __IO  uint32_t  TC8                  :1;
            __IO  uint32_t  TC9                  :1;
            __IO  uint32_t  TC10                 :1;
            __IO  uint32_t  TC11                 :1;
            __IO  uint32_t  TC12                 :1;
            __IO  uint32_t  TC13                 :1;
            __IO  uint32_t  TC14                 :1;
            __IO  uint32_t  TC15                 :1;
            __IO  uint32_t  BC0                  :1;
            __IO  uint32_t  BC1                  :1;
            __IO  uint32_t  BC2                  :1;
            __IO  uint32_t  BC3                  :1;
            __IO  uint32_t  RESERVED1            :3;
            __IO  uint32_t  IS0                  :1;
            __IO  uint32_t  IS1                  :1;
            __IO  uint32_t  IS2                  :1;
            __IO  uint32_t  IS3                  :1;
            __IO  uint32_t  IS4                  :1;
            __IO  uint32_t  IS5                  :1;
            __IO  uint32_t  RESERVED2            :3;
        };
    };
} stc_dmac_dmaca6_field_t;

typedef struct stc_dmac_dmacb6_field
{
    union {
        struct {
            __IO  uint32_t  EM                   :1;
            __IO  uint32_t  RESERVED0            :15;
            __IO  uint32_t  SS                   :3;
            __IO  uint32_t  CI                   :1;
            __IO  uint32_t  EI                   :1;
            __IO  uint32_t  RD                   :1;
            __IO  uint32_t  RS                   :1;
            __IO  uint32_t  RC                   :1;
            __IO  uint32_t  FD                   :1;
            __IO  uint32_t  FS                   :1;
            __IO  uint32_t  TW                   :2;
            __IO  uint32_t  MS                   :2;
            __IO  uint32_t  RESERVED3            :2;
        };
        struct {
            __IO  uint32_t  RESERVED1            :16;
            __IO  uint32_t  SS0                  :1;
            __IO  uint32_t  SS1                  :1;
            __IO  uint32_t  SS2                  :1;
            __IO  uint32_t  RESERVED2            :7;
            __IO  uint32_t  TW0                  :1;
            __IO  uint32_t  TW1                  :1;
            __IO  uint32_t  MS0                  :1;
            __IO  uint32_t  MS1                  :1;
            __IO  uint32_t  RESERVED4            :2;
        };
    };
} stc_dmac_dmacb6_field_t;

typedef struct stc_dmac_dmaca7_field
{
    union {
        struct {
            __IO  uint32_t  TC                   :16;
            __IO  uint32_t  BC                   :4;
            __IO  uint32_t  RESERVED0            :3;
            __IO  uint32_t  IS                   :6;
            __IO  uint32_t  ST                   :1;
            __IO  uint32_t  PB                   :1;
            __IO  uint32_t  EB                   :1;
        };
        struct {
            __IO  uint32_t  TC0                  :1;
            __IO  uint32_t  TC1                  :1;
            __IO  uint32_t  TC2                  :1;
            __IO  uint32_t  TC3                  :1;
            __IO  uint32_t  TC4                  :1;
            __IO  uint32_t  TC5                  :1;
            __IO  uint32_t  TC6                  :1;
            __IO  uint32_t  TC7                  :1;
            __IO  uint32_t  TC8                  :1;
            __IO  uint32_t  TC9                  :1;
            __IO  uint32_t  TC10                 :1;
            __IO  uint32_t  TC11                 :1;
            __IO  uint32_t  TC12                 :1;
            __IO  uint32_t  TC13                 :1;
            __IO  uint32_t  TC14                 :1;
            __IO  uint32_t  TC15                 :1;
            __IO  uint32_t  BC0                  :1;
            __IO  uint32_t  BC1                  :1;
            __IO  uint32_t  BC2                  :1;
            __IO  uint32_t  BC3                  :1;
            __IO  uint32_t  RESERVED1            :3;
            __IO  uint32_t  IS0                  :1;
            __IO  uint32_t  IS1                  :1;
            __IO  uint32_t  IS2                  :1;
            __IO  uint32_t  IS3                  :1;
            __IO  uint32_t  IS4                  :1;
            __IO  uint32_t  IS5                  :1;
            __IO  uint32_t  RESERVED2            :3;
        };
    };
} stc_dmac_dmaca7_field_t;

typedef struct stc_dmac_dmacb7_field
{
    union {
        struct {
            __IO  uint32_t  EM                   :1;
            __IO  uint32_t  RESERVED0            :15;
            __IO  uint32_t  SS                   :3;
            __IO  uint32_t  CI                   :1;
            __IO  uint32_t  EI                   :1;
            __IO  uint32_t  RD                   :1;
            __IO  uint32_t  RS                   :1;
            __IO  uint32_t  RC                   :1;
            __IO  uint32_t  FD                   :1;
            __IO  uint32_t  FS                   :1;
            __IO  uint32_t  TW                   :2;
            __IO  uint32_t  MS                   :2;
            __IO  uint32_t  RESERVED3            :2;
        };
        struct {
            __IO  uint32_t  RESERVED1            :16;
            __IO  uint32_t  SS0                  :1;
            __IO  uint32_t  SS1                  :1;
            __IO  uint32_t  SS2                  :1;
            __IO  uint32_t  RESERVED2            :7;
            __IO  uint32_t  TW0                  :1;
            __IO  uint32_t  TW1                  :1;
            __IO  uint32_t  MS0                  :1;
            __IO  uint32_t  MS1                  :1;
            __IO  uint32_t  RESERVED4            :2;
        };
    };
} stc_dmac_dmacb7_field_t;

/*******************************************************************************
* DS_MODULE
*******************************************************************************/
typedef struct stc_ds_rck_ctl_field
{
        __IO   uint8_t  RTCCKE                   :1;
        __IO   uint8_t  CECCKE                   :1;
        __IO   uint8_t  RESERVED0                :6;
} stc_ds_rck_ctl_field_t;

typedef struct stc_ds_pmd_ctl_field
{
        __IO   uint8_t  RTCE                     :1;
        __IO   uint8_t  RESERVED0                :7;
} stc_ds_pmd_ctl_field_t;

typedef struct stc_ds_wrfsr_field
{
        __IO   uint8_t  WINITX                   :1;
        __IO   uint8_t  WLVDH                    :1;
        __IO   uint8_t  RESERVED0                :6;
} stc_ds_wrfsr_field_t;

typedef struct stc_ds_wifsr_field
{
        __IO  uint16_t  WRTCI                    :1;
        __IO  uint16_t  WLVDI                    :1;
        __IO  uint16_t  WUI0                     :1;
        __IO  uint16_t  WUI1                     :1;
        __IO  uint16_t  WUI2                     :1;
        __IO  uint16_t  WUI3                     :1;
        __IO  uint16_t  WUI4                     :1;
        __IO  uint16_t  WUI5                     :1;
        __IO  uint16_t  RESERVED0                :8;
} stc_ds_wifsr_field_t;

typedef struct stc_ds_wier_field
{
        __IO  uint16_t  WRTCE                    :1;
        __IO  uint16_t  WLVDE                    :1;
        __IO  uint16_t  RESERVED0                :1;
        __IO  uint16_t  WUI1E                    :1;
        __IO  uint16_t  WUI2E                    :1;
        __IO  uint16_t  WUI3E                    :1;
        __IO  uint16_t  WUI4E                    :1;
        __IO  uint16_t  WUI5E                    :1;
        __IO  uint16_t  RESERVED1                :8;
} stc_ds_wier_field_t;

typedef struct stc_ds_wilvr_field
{
        __IO   uint8_t  WUI1LV                   :1;
        __IO   uint8_t  WUI2LV                   :1;
        __IO   uint8_t  WUI3LV                   :1;
        __IO   uint8_t  WUI4LV                   :1;
        __IO   uint8_t  WUI5LV                   :1;
        __IO   uint8_t  RESERVED0                :3;
} stc_ds_wilvr_field_t;

typedef struct stc_ds_dsramr_field
{
    union {
        struct {
            __IO   uint8_t  SRAMR                :2;
            __IO   uint8_t  RESERVED0            :6;
        };
        struct {
            __IO   uint8_t  SRAMR0               :1;
            __IO   uint8_t  SRAMR1               :1;
            __IO   uint8_t  RESERVED1            :6;
        };
    };
} stc_ds_dsramr_field_t;

/*******************************************************************************
* DSTC_MODULE
*******************************************************************************/
typedef struct stc_dstc_hwdesp_field
{
    union {
        struct {
            __IO  uint32_t  CHANNEL              :8;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  HWDESP               :14;
            __IO  uint32_t  RESERVED2            :2;
        };
        struct {
            __IO  uint32_t  CHANNEL0             :1;
            __IO  uint32_t  CHANNEL1             :1;
            __IO  uint32_t  CHANNEL2             :1;
            __IO  uint32_t  CHANNEL3             :1;
            __IO  uint32_t  CHANNEL4             :1;
            __IO  uint32_t  CHANNEL5             :1;
            __IO  uint32_t  CHANNEL6             :1;
            __IO  uint32_t  CHANNEL7             :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  HWDESP0              :1;
            __IO  uint32_t  HWDESP1              :1;
            __IO  uint32_t  HWDESP2              :1;
            __IO  uint32_t  HWDESP3              :1;
            __IO  uint32_t  HWDESP4              :1;
            __IO  uint32_t  HWDESP5              :1;
            __IO  uint32_t  HWDESP6              :1;
            __IO  uint32_t  HWDESP7              :1;
            __IO  uint32_t  HWDESP8              :1;
            __IO  uint32_t  HWDESP9              :1;
            __IO  uint32_t  HWDESP10             :1;
            __IO  uint32_t  HWDESP11             :1;
            __IO  uint32_t  HWDESP12             :1;
            __IO  uint32_t  HWDESP13             :1;
            __IO  uint32_t  RESERVED3            :2;
        };
    };
} stc_dstc_hwdesp_field_t;

typedef struct stc_dstc_cfg_field
{
    union {
        struct {
            __IO   uint8_t  SWINTE               :1;
            __IO   uint8_t  ERINTE               :1;
            __IO   uint8_t  RBDIS                :1;
            __IO   uint8_t  ESTE                 :1;
            __IO   uint8_t  SWPR                 :3;
            __IO   uint8_t  RESERVED1            :1;
        };
        struct {
            __IO   uint8_t  RESERVED0            :4;
            __IO   uint8_t  SWPR0                :1;
            __IO   uint8_t  SWPR1                :1;
            __IO   uint8_t  SWPR2                :1;
            __IO   uint8_t  RESERVED2            :1;
        };
    };
} stc_dstc_cfg_field_t;

typedef struct stc_dstc_swtr_field
{
    union {
        struct {
            __IO  uint16_t  SWDESP               :14;
            __IO  uint16_t  SWREQ                :1;
            __IO  uint16_t  SWST                 :1;
        };
        struct {
            __IO  uint16_t  SWDESP0              :1;
            __IO  uint16_t  SWDESP1              :1;
            __IO  uint16_t  SWDESP2              :1;
            __IO  uint16_t  SWDESP3              :1;
            __IO  uint16_t  SWDESP4              :1;
            __IO  uint16_t  SWDESP5              :1;
            __IO  uint16_t  SWDESP6              :1;
            __IO  uint16_t  SWDESP7              :1;
            __IO  uint16_t  SWDESP8              :1;
            __IO  uint16_t  SWDESP9              :1;
            __IO  uint16_t  SWDESP10             :1;
            __IO  uint16_t  SWDESP11             :1;
            __IO  uint16_t  SWDESP12             :1;
            __IO  uint16_t  SWDESP13             :1;
            __IO  uint16_t  RESERVED0            :2;
        };
    };
} stc_dstc_swtr_field_t;

typedef struct stc_dstc_moners_field
{
    union {
        struct {
            __IO  uint32_t  EST                  :3;
            __IO  uint32_t  DER                  :1;
            __IO  uint32_t  ESTOP                :1;
            __IO  uint32_t  RESERVED0            :1;
            __IO  uint32_t  EHS                  :1;
            __IO  uint32_t  RESERVED1            :1;
            __IO  uint32_t  ECH                  :8;
            __IO  uint32_t  EDESP                :14;
            __IO  uint32_t  RESERVED3            :2;
        };
        struct {
            __IO  uint32_t  EST0                 :1;
            __IO  uint32_t  EST1                 :1;
            __IO  uint32_t  EST2                 :1;
            __IO  uint32_t  RESERVED2            :5;
            __IO  uint32_t  ECH0                 :1;
            __IO  uint32_t  ECH1                 :1;
            __IO  uint32_t  ECH2                 :1;
            __IO  uint32_t  ECH3                 :1;
            __IO  uint32_t  ECH4                 :1;
            __IO  uint32_t  ECH5                 :1;
            __IO  uint32_t  ECH6                 :1;
            __IO  uint32_t  ECH7                 :1;
            __IO  uint32_t  EDESP0               :1;
            __IO  uint32_t  EDESP1               :1;
            __IO  uint32_t  EDESP2               :1;
            __IO  uint32_t  EDESP3               :1;
            __IO  uint32_t  EDESP4               :1;
            __IO  uint32_t  EDESP5               :1;
            __IO  uint32_t  EDESP6               :1;
            __IO  uint32_t  EDESP7               :1;
            __IO  uint32_t  EDESP8               :1;
            __IO  uint32_t  EDESP9               :1;
            __IO  uint32_t  EDESP10              :1;
            __IO  uint32_t  EDESP11              :1;
            __IO  uint32_t  EDESP12              :1;
            __IO  uint32_t  EDESP13              :1;
            __IO  uint32_t  RESERVED4            :2;
        };
    };
} stc_dstc_moners_field_t;

/*******************************************************************************
* DT_MODULE
*******************************************************************************/
typedef struct stc_dt_timer1control_field
{
    union {
        struct {
            __IO  uint32_t  ONESHOT              :1;
            __IO  uint32_t  TIMERSIZE            :1;
            __IO  uint32_t  TIMERPRE             :2;
            __IO  uint32_t  RESERVED1            :1;
            __IO  uint32_t  INTENABLE            :1;
            __IO  uint32_t  TIMERMODE            :1;
            __IO  uint32_t  TIMEREN              :1;
            __IO  uint32_t  RESERVED2            :24;
        };
        struct {
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  TIMERPRE0            :1;
            __IO  uint32_t  TIMERPRE1            :1;
            __IO  uint32_t  RESERVED3            :28;
        };
    };
} stc_dt_timer1control_field_t;

typedef struct stc_dt_timer1ris_field
{
        __IO  uint32_t  TIMER1RIS                :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_dt_timer1ris_field_t;

typedef struct stc_dt_timer1mis_field
{
        __IO  uint32_t  TIMER1MIS                :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_dt_timer1mis_field_t;

typedef struct stc_dt_timer2control_field
{
    union {
        struct {
            __IO  uint32_t  ONESHOT              :1;
            __IO  uint32_t  TIMERSIZE            :1;
            __IO  uint32_t  TIMERPRE             :2;
            __IO  uint32_t  RESERVED1            :1;
            __IO  uint32_t  INTENABLE            :1;
            __IO  uint32_t  TIMERMODE            :1;
            __IO  uint32_t  TIMEREN              :1;
            __IO  uint32_t  RESERVED2            :24;
        };
        struct {
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  TIMERPRE0            :1;
            __IO  uint32_t  TIMERPRE1            :1;
            __IO  uint32_t  RESERVED3            :28;
        };
    };
} stc_dt_timer2control_field_t;

typedef struct stc_dt_timer2ris_field
{
        __IO  uint32_t  TIMER2RIS                :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_dt_timer2ris_field_t;

typedef struct stc_dt_timer2mis_field
{
        __IO  uint32_t  TIMER2MIS                :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_dt_timer2mis_field_t;

/*******************************************************************************
* DUALFLASH_IF_MODULE
*******************************************************************************/
typedef struct stc_dualflash_if_dfaszr_field
{
    union {
        struct {
            __IO  uint32_t  DASZ                 :2;
            __IO  uint32_t  RESERVED0            :30;
        };
        struct {
            __IO  uint32_t  DASZ0                :1;
            __IO  uint32_t  DASZ1                :1;
            __IO  uint32_t  RESERVED1            :30;
        };
    };
} stc_dualflash_if_dfaszr_field_t;

typedef struct stc_dualflash_if_dfrwtr_field
{
    union {
        struct {
            __IO  uint32_t  DRWT                 :2;
            __IO  uint32_t  RESERVED0            :30;
        };
        struct {
            __IO  uint32_t  DRWT0                :1;
            __IO  uint32_t  DRWT1                :1;
            __IO  uint32_t  RESERVED1            :30;
        };
    };
} stc_dualflash_if_dfrwtr_field_t;

typedef struct stc_dualflash_if_dfstr_field
{
        __IO  uint32_t  DFRDY                    :1;
        __IO  uint32_t  DFHNG                    :1;
        __IO  uint32_t  DFERR                    :1;
        __IO  uint32_t  RESERVED0                :29;
} stc_dualflash_if_dfstr_field_t;

/*******************************************************************************
* ECC_CAPTURE_MODULE
*******************************************************************************/
typedef struct stc_ecc_capture_ferrad_field
{
    union {
        struct {
            __IO  uint32_t  ERRAD                :23;
            __IO  uint32_t  RESERVED0            :9;
        };
        struct {
            __IO  uint32_t  ERRAD0               :1;
            __IO  uint32_t  ERRAD1               :1;
            __IO  uint32_t  ERRAD2               :1;
            __IO  uint32_t  ERRAD3               :1;
            __IO  uint32_t  ERRAD4               :1;
            __IO  uint32_t  ERRAD5               :1;
            __IO  uint32_t  ERRAD6               :1;
            __IO  uint32_t  ERRAD7               :1;
            __IO  uint32_t  ERRAD8               :1;
            __IO  uint32_t  ERRAD9               :1;
            __IO  uint32_t  ERRAD10              :1;
            __IO  uint32_t  ERRAD11              :1;
            __IO  uint32_t  ERRAD12              :1;
            __IO  uint32_t  ERRAD13              :1;
            __IO  uint32_t  ERRAD14              :1;
            __IO  uint32_t  ERRAD15              :1;
            __IO  uint32_t  ERRAD16              :1;
            __IO  uint32_t  ERRAD17              :1;
            __IO  uint32_t  ERRAD18              :1;
            __IO  uint32_t  ERRAD19              :1;
            __IO  uint32_t  ERRAD20              :1;
            __IO  uint32_t  ERRAD21              :1;
            __IO  uint32_t  ERRAD22              :1;
            __IO  uint32_t  RESERVED1            :9;
        };
    };
} stc_ecc_capture_ferrad_field_t;

/*******************************************************************************
* ETHERNET_CONTROL_MODULE
*******************************************************************************/
typedef struct stc_ethernet_control_eth_mode_field
{
        __IO  uint32_t  IFMODE                   :1;
        __IO  uint32_t  RESERVED0                :7;
        __IO  uint32_t  RST0                     :1;
        __IO  uint32_t  RST1                     :1;
        __IO  uint32_t  RESERVED1                :18;
        __IO  uint32_t  PPSSEL                   :1;
        __IO  uint32_t  RESERVED2                :3;
} stc_ethernet_control_eth_mode_field_t;

typedef struct stc_ethernet_control_eth_clkg_field
{
    union {
        struct {
            __IO  uint32_t  MACEN                :2;
            __IO  uint32_t  RESERVED0            :30;
        };
        struct {
            __IO  uint32_t  MACEN0               :1;
            __IO  uint32_t  MACEN1               :1;
            __IO  uint32_t  RESERVED1            :30;
        };
    };
} stc_ethernet_control_eth_clkg_field_t;

/*******************************************************************************
* ETHERNET_MAC_MODULE
*******************************************************************************/
typedef struct stc_ethernet_mac_mcr_field
{
    union {
        struct {
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  RE                   :1;
            __IO  uint32_t  TE                   :1;
            __IO  uint32_t  DC                   :1;
            __IO  uint32_t  BL                   :2;
            __IO  uint32_t  ACS                  :1;
            __IO  uint32_t  LUD                  :1;
            __IO  uint32_t  DR                   :1;
            __IO  uint32_t  IPC                  :1;
            __IO  uint32_t  DM                   :1;
            __IO  uint32_t  LM                   :1;
            __IO  uint32_t  DO                   :1;
            __IO  uint32_t  FES                  :1;
            __IO  uint32_t  PS                   :1;
            __IO  uint32_t  DCRS                 :1;
            __IO  uint32_t  IFG                  :3;
            __IO  uint32_t  JE                   :1;
            __IO  uint32_t  BE                   :1;
            __IO  uint32_t  JD                   :1;
            __IO  uint32_t  WD                   :1;
            __IO  uint32_t  TC                   :1;
            __IO  uint32_t  CST                  :1;
            __IO  uint32_t  RESERVED3            :6;
        };
        struct {
            __IO  uint32_t  RESERVED1            :5;
            __IO  uint32_t  BL0                  :1;
            __IO  uint32_t  BL1                  :1;
            __IO  uint32_t  RESERVED2            :10;
            __IO  uint32_t  IFG0                 :1;
            __IO  uint32_t  IFG1                 :1;
            __IO  uint32_t  IFG2                 :1;
            __IO  uint32_t  RESERVED4            :12;
        };
    };
} stc_ethernet_mac_mcr_field_t;

typedef struct stc_ethernet_mac_mffr_field
{
    union {
        struct {
            __IO  uint32_t  PR                   :1;
            __IO  uint32_t  HUC                  :1;
            __IO  uint32_t  HMC                  :1;
            __IO  uint32_t  DAIF                 :1;
            __IO  uint32_t  PM                   :1;
            __IO  uint32_t  DB                   :1;
            __IO  uint32_t  PCF                  :2;
            __IO  uint32_t  SAIF                 :1;
            __IO  uint32_t  SAF                  :1;
            __IO  uint32_t  HPF                  :1;
            __IO  uint32_t  RESERVED1            :20;
            __IO  uint32_t  RA                   :1;
        };
        struct {
            __IO  uint32_t  RESERVED0            :6;
            __IO  uint32_t  PCF0                 :1;
            __IO  uint32_t  PCF1                 :1;
            __IO  uint32_t  RESERVED2            :24;
        };
    };
} stc_ethernet_mac_mffr_field_t;

typedef struct stc_ethernet_mac_mhtrh_field
{
    union {
        struct {
            __IO  uint32_t  HTH                  :32;
        };
        struct {
            __IO  uint32_t  HTH0                 :1;
            __IO  uint32_t  HTH1                 :1;
            __IO  uint32_t  HTH2                 :1;
            __IO  uint32_t  HTH3                 :1;
            __IO  uint32_t  HTH4                 :1;
            __IO  uint32_t  HTH5                 :1;
            __IO  uint32_t  HTH6                 :1;
            __IO  uint32_t  HTH7                 :1;
            __IO  uint32_t  HTH8                 :1;
            __IO  uint32_t  HTH9                 :1;
            __IO  uint32_t  HTH10                :1;
            __IO  uint32_t  HTH11                :1;
            __IO  uint32_t  HTH12                :1;
            __IO  uint32_t  HTH13                :1;
            __IO  uint32_t  HTH14                :1;
            __IO  uint32_t  HTH15                :1;
            __IO  uint32_t  HTH16                :1;
            __IO  uint32_t  HTH17                :1;
            __IO  uint32_t  HTH18                :1;
            __IO  uint32_t  HTH19                :1;
            __IO  uint32_t  HTH20                :1;
            __IO  uint32_t  HTH21                :1;
            __IO  uint32_t  HTH22                :1;
            __IO  uint32_t  HTH23                :1;
            __IO  uint32_t  HTH24                :1;
            __IO  uint32_t  HTH25                :1;
            __IO  uint32_t  HTH26                :1;
            __IO  uint32_t  HTH27                :1;
            __IO  uint32_t  HTH28                :1;
            __IO  uint32_t  HTH29                :1;
            __IO  uint32_t  HTH30                :1;
            __IO  uint32_t  HTH31                :1;
        };
    };
} stc_ethernet_mac_mhtrh_field_t;

typedef struct stc_ethernet_mac_mhtrl_field
{
    union {
        struct {
            __IO  uint32_t  HTL                  :32;
        };
        struct {
            __IO  uint32_t  HTL0                 :1;
            __IO  uint32_t  HTL1                 :1;
            __IO  uint32_t  HTL2                 :1;
            __IO  uint32_t  HTL3                 :1;
            __IO  uint32_t  HTL4                 :1;
            __IO  uint32_t  HTL5                 :1;
            __IO  uint32_t  HTL6                 :1;
            __IO  uint32_t  HTL7                 :1;
            __IO  uint32_t  HTL8                 :1;
            __IO  uint32_t  HTL9                 :1;
            __IO  uint32_t  HTL10                :1;
            __IO  uint32_t  HTL11                :1;
            __IO  uint32_t  HTL12                :1;
            __IO  uint32_t  HTL13                :1;
            __IO  uint32_t  HTL14                :1;
            __IO  uint32_t  HTL15                :1;
            __IO  uint32_t  HTL16                :1;
            __IO  uint32_t  HTL17                :1;
            __IO  uint32_t  HTL18                :1;
            __IO  uint32_t  HTL19                :1;
            __IO  uint32_t  HTL20                :1;
            __IO  uint32_t  HTL21                :1;
            __IO  uint32_t  HTL22                :1;
            __IO  uint32_t  HTL23                :1;
            __IO  uint32_t  HTL24                :1;
            __IO  uint32_t  HTL25                :1;
            __IO  uint32_t  HTL26                :1;
            __IO  uint32_t  HTL27                :1;
            __IO  uint32_t  HTL28                :1;
            __IO  uint32_t  HTL29                :1;
            __IO  uint32_t  HTL30                :1;
            __IO  uint32_t  HTL31                :1;
        };
    };
} stc_ethernet_mac_mhtrl_field_t;

typedef struct stc_ethernet_mac_gar_field
{
    union {
        struct {
            __IO  uint32_t  GB                   :1;
            __IO  uint32_t  GW                   :1;
            __IO  uint32_t  CR                   :4;
            __IO  uint32_t  GR                   :5;
            __IO  uint32_t  PA                   :5;
            __IO  uint32_t  RESERVED1            :16;
        };
        struct {
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  CR0                  :1;
            __IO  uint32_t  CR1                  :1;
            __IO  uint32_t  CR2                  :1;
            __IO  uint32_t  CR3                  :1;
            __IO  uint32_t  GR0                  :1;
            __IO  uint32_t  GR1                  :1;
            __IO  uint32_t  GR2                  :1;
            __IO  uint32_t  GR3                  :1;
            __IO  uint32_t  GR4                  :1;
            __IO  uint32_t  PA0                  :1;
            __IO  uint32_t  PA1                  :1;
            __IO  uint32_t  PA2                  :1;
            __IO  uint32_t  PA3                  :1;
            __IO  uint32_t  PA4                  :1;
            __IO  uint32_t  RESERVED2            :16;
        };
    };
} stc_ethernet_mac_gar_field_t;

typedef struct stc_ethernet_mac_gdr_field
{
    union {
        struct {
            __IO  uint32_t  GD                   :16;
            __IO  uint32_t  RESERVED0            :16;
        };
        struct {
            __IO  uint32_t  GD0                  :1;
            __IO  uint32_t  GD1                  :1;
            __IO  uint32_t  GD2                  :1;
            __IO  uint32_t  GD3                  :1;
            __IO  uint32_t  GD4                  :1;
            __IO  uint32_t  GD5                  :1;
            __IO  uint32_t  GD6                  :1;
            __IO  uint32_t  GD7                  :1;
            __IO  uint32_t  GD8                  :1;
            __IO  uint32_t  GD9                  :1;
            __IO  uint32_t  GD10                 :1;
            __IO  uint32_t  GD11                 :1;
            __IO  uint32_t  GD12                 :1;
            __IO  uint32_t  GD13                 :1;
            __IO  uint32_t  GD14                 :1;
            __IO  uint32_t  GD15                 :1;
            __IO  uint32_t  RESERVED1            :16;
        };
    };
} stc_ethernet_mac_gdr_field_t;

typedef struct stc_ethernet_mac_fcr_field
{
    union {
        struct {
            __IO  uint32_t  FCB_BPA              :1;
            __IO  uint32_t  TFE                  :1;
            __IO  uint32_t  RFE                  :1;
            __IO  uint32_t  UP                   :1;
            __IO  uint32_t  PLT                  :2;
            __IO  uint32_t  RESERVED1            :1;
            __IO  uint32_t  DZPQ                 :1;
            __IO  uint32_t  RESERVED2            :8;
            __IO  uint32_t  PT                   :16;
        };
        struct {
            __IO  uint32_t  RESERVED0            :4;
            __IO  uint32_t  PLT0                 :1;
            __IO  uint32_t  PLT1                 :1;
            __IO  uint32_t  RESERVED3            :10;
            __IO  uint32_t  PT0                  :1;
            __IO  uint32_t  PT1                  :1;
            __IO  uint32_t  PT2                  :1;
            __IO  uint32_t  PT3                  :1;
            __IO  uint32_t  PT4                  :1;
            __IO  uint32_t  PT5                  :1;
            __IO  uint32_t  PT6                  :1;
            __IO  uint32_t  PT7                  :1;
            __IO  uint32_t  PT8                  :1;
            __IO  uint32_t  PT9                  :1;
            __IO  uint32_t  PT10                 :1;
            __IO  uint32_t  PT11                 :1;
            __IO  uint32_t  PT12                 :1;
            __IO  uint32_t  PT13                 :1;
            __IO  uint32_t  PT14                 :1;
            __IO  uint32_t  PT15                 :1;
        };
    };
} stc_ethernet_mac_fcr_field_t;

typedef struct stc_ethernet_mac_vtr_field
{
    union {
        struct {
            __IO  uint32_t  VL                   :16;
            __IO  uint32_t  ETV                  :1;
            __IO  uint32_t  RESERVED0            :15;
        };
        struct {
            __IO  uint32_t  VL0                  :1;
            __IO  uint32_t  VL1                  :1;
            __IO  uint32_t  VL2                  :1;
            __IO  uint32_t  VL3                  :1;
            __IO  uint32_t  VL4                  :1;
            __IO  uint32_t  VL5                  :1;
            __IO  uint32_t  VL6                  :1;
            __IO  uint32_t  VL7                  :1;
            __IO  uint32_t  VL8                  :1;
            __IO  uint32_t  VL9                  :1;
            __IO  uint32_t  VL10                 :1;
            __IO  uint32_t  VL11                 :1;
            __IO  uint32_t  VL12                 :1;
            __IO  uint32_t  VL13                 :1;
            __IO  uint32_t  VL14                 :1;
            __IO  uint32_t  VL15                 :1;
            __IO  uint32_t  RESERVED1            :16;
        };
    };
} stc_ethernet_mac_vtr_field_t;

typedef struct stc_ethernet_mac_rwffr_field
{
    union {
        struct {
            __IO  uint32_t  RWFFR                :32;
        };
        struct {
            __IO  uint32_t  RWFFR0               :1;
            __IO  uint32_t  RWFFR1               :1;
            __IO  uint32_t  RWFFR2               :1;
            __IO  uint32_t  RWFFR3               :1;
            __IO  uint32_t  RWFFR4               :1;
            __IO  uint32_t  RWFFR5               :1;
            __IO  uint32_t  RWFFR6               :1;
            __IO  uint32_t  RWFFR7               :1;
            __IO  uint32_t  RWFFR8               :1;
            __IO  uint32_t  RWFFR9               :1;
            __IO  uint32_t  RWFFR10              :1;
            __IO  uint32_t  RWFFR11              :1;
            __IO  uint32_t  RWFFR12              :1;
            __IO  uint32_t  RWFFR13              :1;
            __IO  uint32_t  RWFFR14              :1;
            __IO  uint32_t  RWFFR15              :1;
            __IO  uint32_t  RWFFR16              :1;
            __IO  uint32_t  RWFFR17              :1;
            __IO  uint32_t  RWFFR18              :1;
            __IO  uint32_t  RWFFR19              :1;
            __IO  uint32_t  RWFFR20              :1;
            __IO  uint32_t  RWFFR21              :1;
            __IO  uint32_t  RWFFR22              :1;
            __IO  uint32_t  RWFFR23              :1;
            __IO  uint32_t  RWFFR24              :1;
            __IO  uint32_t  RWFFR25              :1;
            __IO  uint32_t  RWFFR26              :1;
            __IO  uint32_t  RWFFR27              :1;
            __IO  uint32_t  RWFFR28              :1;
            __IO  uint32_t  RWFFR29              :1;
            __IO  uint32_t  RWFFR30              :1;
            __IO  uint32_t  RWFFR31              :1;
        };
    };
} stc_ethernet_mac_rwffr_field_t;

typedef struct stc_ethernet_mac_pmtr_field
{
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  MPE                      :1;
        __IO  uint32_t  WFE                      :1;
        __IO  uint32_t  RESERVED0                :2;
        __IO  uint32_t  MPR                      :1;
        __IO  uint32_t  WPR                      :1;
        __IO  uint32_t  RESERVED1                :2;
        __IO  uint32_t  GU                       :1;
        __IO  uint32_t  RESERVED2                :21;
        __IO  uint32_t  RWFFRPR                  :1;
} stc_ethernet_mac_pmtr_field_t;

typedef struct stc_ethernet_mac_lpicsr_field
{
        __IO  uint32_t  TLPIEN                   :1;
        __IO  uint32_t  TLPIEX                   :1;
        __IO  uint32_t  RLPIEN                   :1;
        __IO  uint32_t  RLPIEX                   :1;
        __IO  uint32_t  RESERVED0                :4;
        __IO  uint32_t  TLPIST                   :1;
        __IO  uint32_t  RLPIST                   :1;
        __IO  uint32_t  RESERVED1                :6;
        __IO  uint32_t  LPIEN                    :1;
        __IO  uint32_t  PLS                      :1;
        __IO  uint32_t  PLSEN                    :1;
        __IO  uint32_t  LPITXA                   :1;
        __IO  uint32_t  RESERVED2                :12;
} stc_ethernet_mac_lpicsr_field_t;

typedef struct stc_ethernet_mac_lpitcr_field
{
    union {
        struct {
            __IO  uint32_t  TWT                  :16;
            __IO  uint32_t  LIT                  :10;
            __IO  uint32_t  RESERVED0            :6;
        };
        struct {
            __IO  uint32_t  TWT0                 :1;
            __IO  uint32_t  TWT1                 :1;
            __IO  uint32_t  TWT2                 :1;
            __IO  uint32_t  TWT3                 :1;
            __IO  uint32_t  TWT4                 :1;
            __IO  uint32_t  TWT5                 :1;
            __IO  uint32_t  TWT6                 :1;
            __IO  uint32_t  TWT7                 :1;
            __IO  uint32_t  TWT8                 :1;
            __IO  uint32_t  TWT9                 :1;
            __IO  uint32_t  TWT10                :1;
            __IO  uint32_t  TWT11                :1;
            __IO  uint32_t  TWT12                :1;
            __IO  uint32_t  TWT13                :1;
            __IO  uint32_t  TWT14                :1;
            __IO  uint32_t  TWT15                :1;
            __IO  uint32_t  LIT0                 :1;
            __IO  uint32_t  LIT1                 :1;
            __IO  uint32_t  LIT2                 :1;
            __IO  uint32_t  LIT3                 :1;
            __IO  uint32_t  LIT4                 :1;
            __IO  uint32_t  LIT5                 :1;
            __IO  uint32_t  LIT6                 :1;
            __IO  uint32_t  LIT7                 :1;
            __IO  uint32_t  LIT8                 :1;
            __IO  uint32_t  LIT9                 :1;
            __IO  uint32_t  RESERVED1            :6;
        };
    };
} stc_ethernet_mac_lpitcr_field_t;

typedef struct stc_ethernet_mac_isr_field
{
        __IO  uint32_t  RGIS                     :1;
        __IO  uint32_t  RESERVED0                :2;
        __IO  uint32_t  PIS                      :1;
        __IO  uint32_t  MIS                      :1;
        __IO  uint32_t  RIS                      :1;
        __IO  uint32_t  TIS                      :1;
        __IO  uint32_t  COIS                     :1;
        __IO  uint32_t  RESERVED1                :1;
        __IO  uint32_t  TSIS                     :1;
        __IO  uint32_t  LPIIS                    :1;
        __IO  uint32_t  RESERVED2                :21;
} stc_ethernet_mac_isr_field_t;

typedef struct stc_ethernet_mac_imr_field
{
        __IO  uint32_t  RGIM                     :1;
        __IO  uint32_t  RESERVED0                :2;
        __IO  uint32_t  PIM                      :1;
        __IO  uint32_t  RESERVED1                :5;
        __IO  uint32_t  TSIM                     :1;
        __IO  uint32_t  LPIIM                    :1;
        __IO  uint32_t  RESERVED2                :21;
} stc_ethernet_mac_imr_field_t;

typedef struct stc_ethernet_mac_mar0h_field
{
    union {
        struct {
            __IO  uint32_t  A0                   :16;
            __IO  uint32_t  RESERVED0            :15;
            __IO  uint32_t  MO                   :1;
        };
        struct {
            __IO  uint32_t  A00                  :1;
            __IO  uint32_t  A01                  :1;
            __IO  uint32_t  A02                  :1;
            __IO  uint32_t  A03                  :1;
            __IO  uint32_t  A04                  :1;
            __IO  uint32_t  A05                  :1;
            __IO  uint32_t  A06                  :1;
            __IO  uint32_t  A07                  :1;
            __IO  uint32_t  A08                  :1;
            __IO  uint32_t  A09                  :1;
            __IO  uint32_t  A010                 :1;
            __IO  uint32_t  A011                 :1;
            __IO  uint32_t  A012                 :1;
            __IO  uint32_t  A013                 :1;
            __IO  uint32_t  A014                 :1;
            __IO  uint32_t  A015                 :1;
            __IO  uint32_t  RESERVED1            :16;
        };
    };
} stc_ethernet_mac_mar0h_field_t;

typedef struct stc_ethernet_mac_mar0l_field
{
    union {
        struct {
            __IO  uint32_t  A0                   :32;
        };
        struct {
            __IO  uint32_t  A00                  :1;
            __IO  uint32_t  A01                  :1;
            __IO  uint32_t  A02                  :1;
            __IO  uint32_t  A03                  :1;
            __IO  uint32_t  A04                  :1;
            __IO  uint32_t  A05                  :1;
            __IO  uint32_t  A06                  :1;
            __IO  uint32_t  A07                  :1;
            __IO  uint32_t  A08                  :1;
            __IO  uint32_t  A09                  :1;
            __IO  uint32_t  A010                 :1;
            __IO  uint32_t  A011                 :1;
            __IO  uint32_t  A012                 :1;
            __IO  uint32_t  A013                 :1;
            __IO  uint32_t  A014                 :1;
            __IO  uint32_t  A015                 :1;
            __IO  uint32_t  A016                 :1;
            __IO  uint32_t  A017                 :1;
            __IO  uint32_t  A018                 :1;
            __IO  uint32_t  A019                 :1;
            __IO  uint32_t  A020                 :1;
            __IO  uint32_t  A021                 :1;
            __IO  uint32_t  A022                 :1;
            __IO  uint32_t  A023                 :1;
            __IO  uint32_t  A024                 :1;
            __IO  uint32_t  A025                 :1;
            __IO  uint32_t  A026                 :1;
            __IO  uint32_t  A027                 :1;
            __IO  uint32_t  A028                 :1;
            __IO  uint32_t  A029                 :1;
            __IO  uint32_t  A030                 :1;
            __IO  uint32_t  A031                 :1;
        };
    };
} stc_ethernet_mac_mar0l_field_t;

typedef struct stc_ethernet_mac_mar1h_field
{
    union {
        struct {
            __IO  uint32_t  A                    :16;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MBC                  :6;
            __IO  uint32_t  SA                   :1;
            __IO  uint32_t  AE                   :1;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MBC0                 :1;
            __IO  uint32_t  MBC1                 :1;
            __IO  uint32_t  MBC2                 :1;
            __IO  uint32_t  MBC3                 :1;
            __IO  uint32_t  MBC4                 :1;
            __IO  uint32_t  MBC5                 :1;
            __IO  uint32_t  RESERVED2            :2;
        };
    };
} stc_ethernet_mac_mar1h_field_t;

typedef struct stc_ethernet_mac_mar1l_field
{
    union {
        struct {
            __IO  uint32_t  A                    :32;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  A16                  :1;
            __IO  uint32_t  A17                  :1;
            __IO  uint32_t  A18                  :1;
            __IO  uint32_t  A19                  :1;
            __IO  uint32_t  A20                  :1;
            __IO  uint32_t  A21                  :1;
            __IO  uint32_t  A22                  :1;
            __IO  uint32_t  A23                  :1;
            __IO  uint32_t  A24                  :1;
            __IO  uint32_t  A25                  :1;
            __IO  uint32_t  A26                  :1;
            __IO  uint32_t  A27                  :1;
            __IO  uint32_t  A28                  :1;
            __IO  uint32_t  A29                  :1;
            __IO  uint32_t  A30                  :1;
            __IO  uint32_t  A31                  :1;
        };
    };
} stc_ethernet_mac_mar1l_field_t;

typedef struct stc_ethernet_mac_mar2h_field
{
    union {
        struct {
            __IO  uint32_t  A                    :16;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MBC                  :6;
            __IO  uint32_t  SA                   :1;
            __IO  uint32_t  AE                   :1;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MBC0                 :1;
            __IO  uint32_t  MBC1                 :1;
            __IO  uint32_t  MBC2                 :1;
            __IO  uint32_t  MBC3                 :1;
            __IO  uint32_t  MBC4                 :1;
            __IO  uint32_t  MBC5                 :1;
            __IO  uint32_t  RESERVED2            :2;
        };
    };
} stc_ethernet_mac_mar2h_field_t;

typedef struct stc_ethernet_mac_mar2l_field
{
    union {
        struct {
            __IO  uint32_t  A                    :32;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  A16                  :1;
            __IO  uint32_t  A17                  :1;
            __IO  uint32_t  A18                  :1;
            __IO  uint32_t  A19                  :1;
            __IO  uint32_t  A20                  :1;
            __IO  uint32_t  A21                  :1;
            __IO  uint32_t  A22                  :1;
            __IO  uint32_t  A23                  :1;
            __IO  uint32_t  A24                  :1;
            __IO  uint32_t  A25                  :1;
            __IO  uint32_t  A26                  :1;
            __IO  uint32_t  A27                  :1;
            __IO  uint32_t  A28                  :1;
            __IO  uint32_t  A29                  :1;
            __IO  uint32_t  A30                  :1;
            __IO  uint32_t  A31                  :1;
        };
    };
} stc_ethernet_mac_mar2l_field_t;

typedef struct stc_ethernet_mac_mar3h_field
{
    union {
        struct {
            __IO  uint32_t  A                    :16;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MBC                  :6;
            __IO  uint32_t  SA                   :1;
            __IO  uint32_t  AE                   :1;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MBC0                 :1;
            __IO  uint32_t  MBC1                 :1;
            __IO  uint32_t  MBC2                 :1;
            __IO  uint32_t  MBC3                 :1;
            __IO  uint32_t  MBC4                 :1;
            __IO  uint32_t  MBC5                 :1;
            __IO  uint32_t  RESERVED2            :2;
        };
    };
} stc_ethernet_mac_mar3h_field_t;

typedef struct stc_ethernet_mac_mar3l_field
{
    union {
        struct {
            __IO  uint32_t  A                    :32;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  A16                  :1;
            __IO  uint32_t  A17                  :1;
            __IO  uint32_t  A18                  :1;
            __IO  uint32_t  A19                  :1;
            __IO  uint32_t  A20                  :1;
            __IO  uint32_t  A21                  :1;
            __IO  uint32_t  A22                  :1;
            __IO  uint32_t  A23                  :1;
            __IO  uint32_t  A24                  :1;
            __IO  uint32_t  A25                  :1;
            __IO  uint32_t  A26                  :1;
            __IO  uint32_t  A27                  :1;
            __IO  uint32_t  A28                  :1;
            __IO  uint32_t  A29                  :1;
            __IO  uint32_t  A30                  :1;
            __IO  uint32_t  A31                  :1;
        };
    };
} stc_ethernet_mac_mar3l_field_t;

typedef struct stc_ethernet_mac_mar4h_field
{
    union {
        struct {
            __IO  uint32_t  A                    :16;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MBC                  :6;
            __IO  uint32_t  SA                   :1;
            __IO  uint32_t  AE                   :1;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MBC0                 :1;
            __IO  uint32_t  MBC1                 :1;
            __IO  uint32_t  MBC2                 :1;
            __IO  uint32_t  MBC3                 :1;
            __IO  uint32_t  MBC4                 :1;
            __IO  uint32_t  MBC5                 :1;
            __IO  uint32_t  RESERVED2            :2;
        };
    };
} stc_ethernet_mac_mar4h_field_t;

typedef struct stc_ethernet_mac_mar4l_field
{
    union {
        struct {
            __IO  uint32_t  A                    :32;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  A16                  :1;
            __IO  uint32_t  A17                  :1;
            __IO  uint32_t  A18                  :1;
            __IO  uint32_t  A19                  :1;
            __IO  uint32_t  A20                  :1;
            __IO  uint32_t  A21                  :1;
            __IO  uint32_t  A22                  :1;
            __IO  uint32_t  A23                  :1;
            __IO  uint32_t  A24                  :1;
            __IO  uint32_t  A25                  :1;
            __IO  uint32_t  A26                  :1;
            __IO  uint32_t  A27                  :1;
            __IO  uint32_t  A28                  :1;
            __IO  uint32_t  A29                  :1;
            __IO  uint32_t  A30                  :1;
            __IO  uint32_t  A31                  :1;
        };
    };
} stc_ethernet_mac_mar4l_field_t;

typedef struct stc_ethernet_mac_mar5h_field
{
    union {
        struct {
            __IO  uint32_t  A                    :16;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MBC                  :6;
            __IO  uint32_t  SA                   :1;
            __IO  uint32_t  AE                   :1;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MBC0                 :1;
            __IO  uint32_t  MBC1                 :1;
            __IO  uint32_t  MBC2                 :1;
            __IO  uint32_t  MBC3                 :1;
            __IO  uint32_t  MBC4                 :1;
            __IO  uint32_t  MBC5                 :1;
            __IO  uint32_t  RESERVED2            :2;
        };
    };
} stc_ethernet_mac_mar5h_field_t;

typedef struct stc_ethernet_mac_mar5l_field
{
    union {
        struct {
            __IO  uint32_t  A                    :32;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  A16                  :1;
            __IO  uint32_t  A17                  :1;
            __IO  uint32_t  A18                  :1;
            __IO  uint32_t  A19                  :1;
            __IO  uint32_t  A20                  :1;
            __IO  uint32_t  A21                  :1;
            __IO  uint32_t  A22                  :1;
            __IO  uint32_t  A23                  :1;
            __IO  uint32_t  A24                  :1;
            __IO  uint32_t  A25                  :1;
            __IO  uint32_t  A26                  :1;
            __IO  uint32_t  A27                  :1;
            __IO  uint32_t  A28                  :1;
            __IO  uint32_t  A29                  :1;
            __IO  uint32_t  A30                  :1;
            __IO  uint32_t  A31                  :1;
        };
    };
} stc_ethernet_mac_mar5l_field_t;

typedef struct stc_ethernet_mac_mar6h_field
{
    union {
        struct {
            __IO  uint32_t  A                    :16;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MBC                  :6;
            __IO  uint32_t  SA                   :1;
            __IO  uint32_t  AE                   :1;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MBC0                 :1;
            __IO  uint32_t  MBC1                 :1;
            __IO  uint32_t  MBC2                 :1;
            __IO  uint32_t  MBC3                 :1;
            __IO  uint32_t  MBC4                 :1;
            __IO  uint32_t  MBC5                 :1;
            __IO  uint32_t  RESERVED2            :2;
        };
    };
} stc_ethernet_mac_mar6h_field_t;

typedef struct stc_ethernet_mac_mar6l_field
{
    union {
        struct {
            __IO  uint32_t  A                    :32;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  A16                  :1;
            __IO  uint32_t  A17                  :1;
            __IO  uint32_t  A18                  :1;
            __IO  uint32_t  A19                  :1;
            __IO  uint32_t  A20                  :1;
            __IO  uint32_t  A21                  :1;
            __IO  uint32_t  A22                  :1;
            __IO  uint32_t  A23                  :1;
            __IO  uint32_t  A24                  :1;
            __IO  uint32_t  A25                  :1;
            __IO  uint32_t  A26                  :1;
            __IO  uint32_t  A27                  :1;
            __IO  uint32_t  A28                  :1;
            __IO  uint32_t  A29                  :1;
            __IO  uint32_t  A30                  :1;
            __IO  uint32_t  A31                  :1;
        };
    };
} stc_ethernet_mac_mar6l_field_t;

typedef struct stc_ethernet_mac_mar7h_field
{
    union {
        struct {
            __IO  uint32_t  A                    :16;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MBC                  :6;
            __IO  uint32_t  SA                   :1;
            __IO  uint32_t  AE                   :1;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MBC0                 :1;
            __IO  uint32_t  MBC1                 :1;
            __IO  uint32_t  MBC2                 :1;
            __IO  uint32_t  MBC3                 :1;
            __IO  uint32_t  MBC4                 :1;
            __IO  uint32_t  MBC5                 :1;
            __IO  uint32_t  RESERVED2            :2;
        };
    };
} stc_ethernet_mac_mar7h_field_t;

typedef struct stc_ethernet_mac_mar7l_field
{
    union {
        struct {
            __IO  uint32_t  A                    :32;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  A16                  :1;
            __IO  uint32_t  A17                  :1;
            __IO  uint32_t  A18                  :1;
            __IO  uint32_t  A19                  :1;
            __IO  uint32_t  A20                  :1;
            __IO  uint32_t  A21                  :1;
            __IO  uint32_t  A22                  :1;
            __IO  uint32_t  A23                  :1;
            __IO  uint32_t  A24                  :1;
            __IO  uint32_t  A25                  :1;
            __IO  uint32_t  A26                  :1;
            __IO  uint32_t  A27                  :1;
            __IO  uint32_t  A28                  :1;
            __IO  uint32_t  A29                  :1;
            __IO  uint32_t  A30                  :1;
            __IO  uint32_t  A31                  :1;
        };
    };
} stc_ethernet_mac_mar7l_field_t;

typedef struct stc_ethernet_mac_mar8h_field
{
    union {
        struct {
            __IO  uint32_t  A                    :16;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MBC                  :6;
            __IO  uint32_t  SA                   :1;
            __IO  uint32_t  AE                   :1;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MBC0                 :1;
            __IO  uint32_t  MBC1                 :1;
            __IO  uint32_t  MBC2                 :1;
            __IO  uint32_t  MBC3                 :1;
            __IO  uint32_t  MBC4                 :1;
            __IO  uint32_t  MBC5                 :1;
            __IO  uint32_t  RESERVED2            :2;
        };
    };
} stc_ethernet_mac_mar8h_field_t;

typedef struct stc_ethernet_mac_mar8l_field
{
    union {
        struct {
            __IO  uint32_t  A                    :32;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  A16                  :1;
            __IO  uint32_t  A17                  :1;
            __IO  uint32_t  A18                  :1;
            __IO  uint32_t  A19                  :1;
            __IO  uint32_t  A20                  :1;
            __IO  uint32_t  A21                  :1;
            __IO  uint32_t  A22                  :1;
            __IO  uint32_t  A23                  :1;
            __IO  uint32_t  A24                  :1;
            __IO  uint32_t  A25                  :1;
            __IO  uint32_t  A26                  :1;
            __IO  uint32_t  A27                  :1;
            __IO  uint32_t  A28                  :1;
            __IO  uint32_t  A29                  :1;
            __IO  uint32_t  A30                  :1;
            __IO  uint32_t  A31                  :1;
        };
    };
} stc_ethernet_mac_mar8l_field_t;

typedef struct stc_ethernet_mac_mar9h_field
{
    union {
        struct {
            __IO  uint32_t  A                    :16;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MBC                  :6;
            __IO  uint32_t  SA                   :1;
            __IO  uint32_t  AE                   :1;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MBC0                 :1;
            __IO  uint32_t  MBC1                 :1;
            __IO  uint32_t  MBC2                 :1;
            __IO  uint32_t  MBC3                 :1;
            __IO  uint32_t  MBC4                 :1;
            __IO  uint32_t  MBC5                 :1;
            __IO  uint32_t  RESERVED2            :2;
        };
    };
} stc_ethernet_mac_mar9h_field_t;

typedef struct stc_ethernet_mac_mar9l_field
{
    union {
        struct {
            __IO  uint32_t  A                    :32;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  A16                  :1;
            __IO  uint32_t  A17                  :1;
            __IO  uint32_t  A18                  :1;
            __IO  uint32_t  A19                  :1;
            __IO  uint32_t  A20                  :1;
            __IO  uint32_t  A21                  :1;
            __IO  uint32_t  A22                  :1;
            __IO  uint32_t  A23                  :1;
            __IO  uint32_t  A24                  :1;
            __IO  uint32_t  A25                  :1;
            __IO  uint32_t  A26                  :1;
            __IO  uint32_t  A27                  :1;
            __IO  uint32_t  A28                  :1;
            __IO  uint32_t  A29                  :1;
            __IO  uint32_t  A30                  :1;
            __IO  uint32_t  A31                  :1;
        };
    };
} stc_ethernet_mac_mar9l_field_t;

typedef struct stc_ethernet_mac_mar10h_field
{
    union {
        struct {
            __IO  uint32_t  A                    :16;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MBC                  :6;
            __IO  uint32_t  SA                   :1;
            __IO  uint32_t  AE                   :1;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MBC0                 :1;
            __IO  uint32_t  MBC1                 :1;
            __IO  uint32_t  MBC2                 :1;
            __IO  uint32_t  MBC3                 :1;
            __IO  uint32_t  MBC4                 :1;
            __IO  uint32_t  MBC5                 :1;
            __IO  uint32_t  RESERVED2            :2;
        };
    };
} stc_ethernet_mac_mar10h_field_t;

typedef struct stc_ethernet_mac_mar10l_field
{
    union {
        struct {
            __IO  uint32_t  A                    :32;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  A16                  :1;
            __IO  uint32_t  A17                  :1;
            __IO  uint32_t  A18                  :1;
            __IO  uint32_t  A19                  :1;
            __IO  uint32_t  A20                  :1;
            __IO  uint32_t  A21                  :1;
            __IO  uint32_t  A22                  :1;
            __IO  uint32_t  A23                  :1;
            __IO  uint32_t  A24                  :1;
            __IO  uint32_t  A25                  :1;
            __IO  uint32_t  A26                  :1;
            __IO  uint32_t  A27                  :1;
            __IO  uint32_t  A28                  :1;
            __IO  uint32_t  A29                  :1;
            __IO  uint32_t  A30                  :1;
            __IO  uint32_t  A31                  :1;
        };
    };
} stc_ethernet_mac_mar10l_field_t;

typedef struct stc_ethernet_mac_mar11h_field
{
    union {
        struct {
            __IO  uint32_t  A                    :16;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MBC                  :6;
            __IO  uint32_t  SA                   :1;
            __IO  uint32_t  AE                   :1;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MBC0                 :1;
            __IO  uint32_t  MBC1                 :1;
            __IO  uint32_t  MBC2                 :1;
            __IO  uint32_t  MBC3                 :1;
            __IO  uint32_t  MBC4                 :1;
            __IO  uint32_t  MBC5                 :1;
            __IO  uint32_t  RESERVED2            :2;
        };
    };
} stc_ethernet_mac_mar11h_field_t;

typedef struct stc_ethernet_mac_mar11l_field
{
    union {
        struct {
            __IO  uint32_t  A                    :32;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  A16                  :1;
            __IO  uint32_t  A17                  :1;
            __IO  uint32_t  A18                  :1;
            __IO  uint32_t  A19                  :1;
            __IO  uint32_t  A20                  :1;
            __IO  uint32_t  A21                  :1;
            __IO  uint32_t  A22                  :1;
            __IO  uint32_t  A23                  :1;
            __IO  uint32_t  A24                  :1;
            __IO  uint32_t  A25                  :1;
            __IO  uint32_t  A26                  :1;
            __IO  uint32_t  A27                  :1;
            __IO  uint32_t  A28                  :1;
            __IO  uint32_t  A29                  :1;
            __IO  uint32_t  A30                  :1;
            __IO  uint32_t  A31                  :1;
        };
    };
} stc_ethernet_mac_mar11l_field_t;

typedef struct stc_ethernet_mac_mar12h_field
{
    union {
        struct {
            __IO  uint32_t  A                    :16;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MBC                  :6;
            __IO  uint32_t  SA                   :1;
            __IO  uint32_t  AE                   :1;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MBC0                 :1;
            __IO  uint32_t  MBC1                 :1;
            __IO  uint32_t  MBC2                 :1;
            __IO  uint32_t  MBC3                 :1;
            __IO  uint32_t  MBC4                 :1;
            __IO  uint32_t  MBC5                 :1;
            __IO  uint32_t  RESERVED2            :2;
        };
    };
} stc_ethernet_mac_mar12h_field_t;

typedef struct stc_ethernet_mac_mar12l_field
{
    union {
        struct {
            __IO  uint32_t  A                    :32;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  A16                  :1;
            __IO  uint32_t  A17                  :1;
            __IO  uint32_t  A18                  :1;
            __IO  uint32_t  A19                  :1;
            __IO  uint32_t  A20                  :1;
            __IO  uint32_t  A21                  :1;
            __IO  uint32_t  A22                  :1;
            __IO  uint32_t  A23                  :1;
            __IO  uint32_t  A24                  :1;
            __IO  uint32_t  A25                  :1;
            __IO  uint32_t  A26                  :1;
            __IO  uint32_t  A27                  :1;
            __IO  uint32_t  A28                  :1;
            __IO  uint32_t  A29                  :1;
            __IO  uint32_t  A30                  :1;
            __IO  uint32_t  A31                  :1;
        };
    };
} stc_ethernet_mac_mar12l_field_t;

typedef struct stc_ethernet_mac_mar13h_field
{
    union {
        struct {
            __IO  uint32_t  A                    :16;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MBC                  :6;
            __IO  uint32_t  SA                   :1;
            __IO  uint32_t  AE                   :1;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MBC0                 :1;
            __IO  uint32_t  MBC1                 :1;
            __IO  uint32_t  MBC2                 :1;
            __IO  uint32_t  MBC3                 :1;
            __IO  uint32_t  MBC4                 :1;
            __IO  uint32_t  MBC5                 :1;
            __IO  uint32_t  RESERVED2            :2;
        };
    };
} stc_ethernet_mac_mar13h_field_t;

typedef struct stc_ethernet_mac_mar13l_field
{
    union {
        struct {
            __IO  uint32_t  A                    :32;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  A16                  :1;
            __IO  uint32_t  A17                  :1;
            __IO  uint32_t  A18                  :1;
            __IO  uint32_t  A19                  :1;
            __IO  uint32_t  A20                  :1;
            __IO  uint32_t  A21                  :1;
            __IO  uint32_t  A22                  :1;
            __IO  uint32_t  A23                  :1;
            __IO  uint32_t  A24                  :1;
            __IO  uint32_t  A25                  :1;
            __IO  uint32_t  A26                  :1;
            __IO  uint32_t  A27                  :1;
            __IO  uint32_t  A28                  :1;
            __IO  uint32_t  A29                  :1;
            __IO  uint32_t  A30                  :1;
            __IO  uint32_t  A31                  :1;
        };
    };
} stc_ethernet_mac_mar13l_field_t;

typedef struct stc_ethernet_mac_mar14h_field
{
    union {
        struct {
            __IO  uint32_t  A                    :16;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MBC                  :6;
            __IO  uint32_t  SA                   :1;
            __IO  uint32_t  AE                   :1;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MBC0                 :1;
            __IO  uint32_t  MBC1                 :1;
            __IO  uint32_t  MBC2                 :1;
            __IO  uint32_t  MBC3                 :1;
            __IO  uint32_t  MBC4                 :1;
            __IO  uint32_t  MBC5                 :1;
            __IO  uint32_t  RESERVED2            :2;
        };
    };
} stc_ethernet_mac_mar14h_field_t;

typedef struct stc_ethernet_mac_mar14l_field
{
    union {
        struct {
            __IO  uint32_t  A                    :32;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  A16                  :1;
            __IO  uint32_t  A17                  :1;
            __IO  uint32_t  A18                  :1;
            __IO  uint32_t  A19                  :1;
            __IO  uint32_t  A20                  :1;
            __IO  uint32_t  A21                  :1;
            __IO  uint32_t  A22                  :1;
            __IO  uint32_t  A23                  :1;
            __IO  uint32_t  A24                  :1;
            __IO  uint32_t  A25                  :1;
            __IO  uint32_t  A26                  :1;
            __IO  uint32_t  A27                  :1;
            __IO  uint32_t  A28                  :1;
            __IO  uint32_t  A29                  :1;
            __IO  uint32_t  A30                  :1;
            __IO  uint32_t  A31                  :1;
        };
    };
} stc_ethernet_mac_mar14l_field_t;

typedef struct stc_ethernet_mac_mar15h_field
{
    union {
        struct {
            __IO  uint32_t  A                    :16;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MBC                  :6;
            __IO  uint32_t  SA                   :1;
            __IO  uint32_t  AE                   :1;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MBC0                 :1;
            __IO  uint32_t  MBC1                 :1;
            __IO  uint32_t  MBC2                 :1;
            __IO  uint32_t  MBC3                 :1;
            __IO  uint32_t  MBC4                 :1;
            __IO  uint32_t  MBC5                 :1;
            __IO  uint32_t  RESERVED2            :2;
        };
    };
} stc_ethernet_mac_mar15h_field_t;

typedef struct stc_ethernet_mac_mar15l_field
{
    union {
        struct {
            __IO  uint32_t  A                    :32;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  A16                  :1;
            __IO  uint32_t  A17                  :1;
            __IO  uint32_t  A18                  :1;
            __IO  uint32_t  A19                  :1;
            __IO  uint32_t  A20                  :1;
            __IO  uint32_t  A21                  :1;
            __IO  uint32_t  A22                  :1;
            __IO  uint32_t  A23                  :1;
            __IO  uint32_t  A24                  :1;
            __IO  uint32_t  A25                  :1;
            __IO  uint32_t  A26                  :1;
            __IO  uint32_t  A27                  :1;
            __IO  uint32_t  A28                  :1;
            __IO  uint32_t  A29                  :1;
            __IO  uint32_t  A30                  :1;
            __IO  uint32_t  A31                  :1;
        };
    };
} stc_ethernet_mac_mar15l_field_t;

typedef struct stc_ethernet_mac_rgsr_field
{
    union {
        struct {
            __IO  uint32_t  LM                   :1;
            __IO  uint32_t  LSP                  :2;
            __IO  uint32_t  LS                   :1;
            __IO  uint32_t  RESERVED1            :28;
        };
        struct {
            __IO  uint32_t  RESERVED0            :1;
            __IO  uint32_t  LSP0                 :1;
            __IO  uint32_t  LSP1                 :1;
            __IO  uint32_t  RESERVED2            :29;
        };
    };
} stc_ethernet_mac_rgsr_field_t;

typedef struct stc_ethernet_mac_mmc_cntl_field
{
    union {
        struct {
            __IO  uint32_t  B                    :6;
            __IO  uint32_t  RESERVED0            :26;
        };
        struct {
            __IO  uint32_t  B0                   :1;
            __IO  uint32_t  B1                   :1;
            __IO  uint32_t  B2                   :1;
            __IO  uint32_t  B3                   :1;
            __IO  uint32_t  B4                   :1;
            __IO  uint32_t  B5                   :1;
            __IO  uint32_t  RESERVED1            :26;
        };
    };
} stc_ethernet_mac_mmc_cntl_field_t;

typedef struct stc_ethernet_mac_mmc_intr_rx_field
{
    union {
        struct {
            __IO  uint32_t  B                    :24;
            __IO  uint32_t  RESERVED0            :8;
        };
        struct {
            __IO  uint32_t  B0                   :1;
            __IO  uint32_t  B1                   :1;
            __IO  uint32_t  B2                   :1;
            __IO  uint32_t  B3                   :1;
            __IO  uint32_t  B4                   :1;
            __IO  uint32_t  B5                   :1;
            __IO  uint32_t  B6                   :1;
            __IO  uint32_t  B7                   :1;
            __IO  uint32_t  B8                   :1;
            __IO  uint32_t  B9                   :1;
            __IO  uint32_t  B10                  :1;
            __IO  uint32_t  B11                  :1;
            __IO  uint32_t  B12                  :1;
            __IO  uint32_t  B13                  :1;
            __IO  uint32_t  B14                  :1;
            __IO  uint32_t  B15                  :1;
            __IO  uint32_t  B16                  :1;
            __IO  uint32_t  B17                  :1;
            __IO  uint32_t  B18                  :1;
            __IO  uint32_t  B19                  :1;
            __IO  uint32_t  B20                  :1;
            __IO  uint32_t  B21                  :1;
            __IO  uint32_t  B22                  :1;
            __IO  uint32_t  B23                  :1;
            __IO  uint32_t  RESERVED1            :8;
        };
    };
} stc_ethernet_mac_mmc_intr_rx_field_t;

typedef struct stc_ethernet_mac_mmc_intr_tx_field
{
    union {
        struct {
            __IO  uint32_t  B                    :25;
            __IO  uint32_t  RESERVED0            :7;
        };
        struct {
            __IO  uint32_t  B0                   :1;
            __IO  uint32_t  B1                   :1;
            __IO  uint32_t  B2                   :1;
            __IO  uint32_t  B3                   :1;
            __IO  uint32_t  B4                   :1;
            __IO  uint32_t  B5                   :1;
            __IO  uint32_t  B6                   :1;
            __IO  uint32_t  B7                   :1;
            __IO  uint32_t  B8                   :1;
            __IO  uint32_t  B9                   :1;
            __IO  uint32_t  B10                  :1;
            __IO  uint32_t  B11                  :1;
            __IO  uint32_t  B12                  :1;
            __IO  uint32_t  B13                  :1;
            __IO  uint32_t  B14                  :1;
            __IO  uint32_t  B15                  :1;
            __IO  uint32_t  B16                  :1;
            __IO  uint32_t  B17                  :1;
            __IO  uint32_t  B18                  :1;
            __IO  uint32_t  B19                  :1;
            __IO  uint32_t  B20                  :1;
            __IO  uint32_t  B21                  :1;
            __IO  uint32_t  B22                  :1;
            __IO  uint32_t  B23                  :1;
            __IO  uint32_t  B24                  :1;
            __IO  uint32_t  RESERVED1            :7;
        };
    };
} stc_ethernet_mac_mmc_intr_tx_field_t;

typedef struct stc_ethernet_mac_mmc_intr_mask_rx_field
{
    union {
        struct {
            __IO  uint32_t  B                    :24;
            __IO  uint32_t  RESERVED0            :8;
        };
        struct {
            __IO  uint32_t  B0                   :1;
            __IO  uint32_t  B1                   :1;
            __IO  uint32_t  B2                   :1;
            __IO  uint32_t  B3                   :1;
            __IO  uint32_t  B4                   :1;
            __IO  uint32_t  B5                   :1;
            __IO  uint32_t  B6                   :1;
            __IO  uint32_t  B7                   :1;
            __IO  uint32_t  B8                   :1;
            __IO  uint32_t  B9                   :1;
            __IO  uint32_t  B10                  :1;
            __IO  uint32_t  B11                  :1;
            __IO  uint32_t  B12                  :1;
            __IO  uint32_t  B13                  :1;
            __IO  uint32_t  B14                  :1;
            __IO  uint32_t  B15                  :1;
            __IO  uint32_t  B16                  :1;
            __IO  uint32_t  B17                  :1;
            __IO  uint32_t  B18                  :1;
            __IO  uint32_t  B19                  :1;
            __IO  uint32_t  B20                  :1;
            __IO  uint32_t  B21                  :1;
            __IO  uint32_t  B22                  :1;
            __IO  uint32_t  B23                  :1;
            __IO  uint32_t  RESERVED1            :8;
        };
    };
} stc_ethernet_mac_mmc_intr_mask_rx_field_t;

typedef struct stc_ethernet_mac_mmc_intr_mask_tx_field
{
    union {
        struct {
            __IO  uint32_t  B                    :25;
            __IO  uint32_t  RESERVED0            :7;
        };
        struct {
            __IO  uint32_t  B0                   :1;
            __IO  uint32_t  B1                   :1;
            __IO  uint32_t  B2                   :1;
            __IO  uint32_t  B3                   :1;
            __IO  uint32_t  B4                   :1;
            __IO  uint32_t  B5                   :1;
            __IO  uint32_t  B6                   :1;
            __IO  uint32_t  B7                   :1;
            __IO  uint32_t  B8                   :1;
            __IO  uint32_t  B9                   :1;
            __IO  uint32_t  B10                  :1;
            __IO  uint32_t  B11                  :1;
            __IO  uint32_t  B12                  :1;
            __IO  uint32_t  B13                  :1;
            __IO  uint32_t  B14                  :1;
            __IO  uint32_t  B15                  :1;
            __IO  uint32_t  B16                  :1;
            __IO  uint32_t  B17                  :1;
            __IO  uint32_t  B18                  :1;
            __IO  uint32_t  B19                  :1;
            __IO  uint32_t  B20                  :1;
            __IO  uint32_t  B21                  :1;
            __IO  uint32_t  B22                  :1;
            __IO  uint32_t  B23                  :1;
            __IO  uint32_t  B24                  :1;
            __IO  uint32_t  RESERVED1            :7;
        };
    };
} stc_ethernet_mac_mmc_intr_mask_tx_field_t;

typedef struct stc_ethernet_mac_mmc_ipc_intr_mask_rx_field
{
    union {
        struct {
            __IO  uint32_t  BL                   :14;
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  BH                   :14;
            __IO  uint32_t  RESERVED2            :2;
        };
        struct {
            __IO  uint32_t  BL0                  :1;
            __IO  uint32_t  BL1                  :1;
            __IO  uint32_t  BL2                  :1;
            __IO  uint32_t  BL3                  :1;
            __IO  uint32_t  BL4                  :1;
            __IO  uint32_t  BL5                  :1;
            __IO  uint32_t  BL6                  :1;
            __IO  uint32_t  BL7                  :1;
            __IO  uint32_t  BL8                  :1;
            __IO  uint32_t  BL9                  :1;
            __IO  uint32_t  BL10                 :1;
            __IO  uint32_t  BL11                 :1;
            __IO  uint32_t  BL12                 :1;
            __IO  uint32_t  BL13                 :1;
            __IO  uint32_t  RESERVED1            :2;
            __IO  uint32_t  BH0                  :1;
            __IO  uint32_t  BH1                  :1;
            __IO  uint32_t  BH2                  :1;
            __IO  uint32_t  BH3                  :1;
            __IO  uint32_t  BH4                  :1;
            __IO  uint32_t  BH5                  :1;
            __IO  uint32_t  BH6                  :1;
            __IO  uint32_t  BH7                  :1;
            __IO  uint32_t  BH8                  :1;
            __IO  uint32_t  BH9                  :1;
            __IO  uint32_t  BH10                 :1;
            __IO  uint32_t  BH11                 :1;
            __IO  uint32_t  BH12                 :1;
            __IO  uint32_t  BH13                 :1;
            __IO  uint32_t  RESERVED3            :2;
        };
    };
} stc_ethernet_mac_mmc_ipc_intr_mask_rx_field_t;

typedef struct stc_ethernet_mac_mmc_ipc_intr_rx_field
{
    union {
        struct {
            __IO  uint32_t  BL                   :14;
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  BH                   :14;
            __IO  uint32_t  RESERVED2            :2;
        };
        struct {
            __IO  uint32_t  BL0                  :1;
            __IO  uint32_t  BL1                  :1;
            __IO  uint32_t  BL2                  :1;
            __IO  uint32_t  BL3                  :1;
            __IO  uint32_t  BL4                  :1;
            __IO  uint32_t  BL5                  :1;
            __IO  uint32_t  BL6                  :1;
            __IO  uint32_t  BL7                  :1;
            __IO  uint32_t  BL8                  :1;
            __IO  uint32_t  BL9                  :1;
            __IO  uint32_t  BL10                 :1;
            __IO  uint32_t  BL11                 :1;
            __IO  uint32_t  BL12                 :1;
            __IO  uint32_t  BL13                 :1;
            __IO  uint32_t  RESERVED1            :2;
            __IO  uint32_t  BH0                  :1;
            __IO  uint32_t  BH1                  :1;
            __IO  uint32_t  BH2                  :1;
            __IO  uint32_t  BH3                  :1;
            __IO  uint32_t  BH4                  :1;
            __IO  uint32_t  BH5                  :1;
            __IO  uint32_t  BH6                  :1;
            __IO  uint32_t  BH7                  :1;
            __IO  uint32_t  BH8                  :1;
            __IO  uint32_t  BH9                  :1;
            __IO  uint32_t  BH10                 :1;
            __IO  uint32_t  BH11                 :1;
            __IO  uint32_t  BH12                 :1;
            __IO  uint32_t  BH13                 :1;
            __IO  uint32_t  RESERVED3            :2;
        };
    };
} stc_ethernet_mac_mmc_ipc_intr_rx_field_t;

typedef struct stc_ethernet_mac_tscr_field
{
    union {
        struct {
            __IO  uint32_t  TSE                  :1;
            __IO  uint32_t  TFCU                 :1;
            __IO  uint32_t  TSI                  :1;
            __IO  uint32_t  TSU                  :1;
            __IO  uint32_t  TITE                 :1;
            __IO  uint32_t  TARU                 :1;
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  TSEA                 :1;
            __IO  uint32_t  TSDB                 :1;
            __IO  uint32_t  TSV2E                :1;
            __IO  uint32_t  TETSP                :1;
            __IO  uint32_t  TSIP6E               :1;
            __IO  uint32_t  TSIP4E               :1;
            __IO  uint32_t  TETSEM               :1;
            __IO  uint32_t  TSMRM                :1;
            __IO  uint32_t  TSPS                 :2;
            __IO  uint32_t  TSENMF               :1;
            __IO  uint32_t  RESERVED2            :5;
            __IO  uint32_t  ATSFC                :1;
            __IO  uint32_t  RESERVED3            :7;
        };
        struct {
            __IO  uint32_t  RESERVED1            :16;
            __IO  uint32_t  TSPS0                :1;
            __IO  uint32_t  TSPS1                :1;
            __IO  uint32_t  RESERVED4            :14;
        };
    };
} stc_ethernet_mac_tscr_field_t;

typedef struct stc_ethernet_mac_ssir_field
{
    union {
        struct {
            __IO  uint32_t  SSINC                :8;
            __IO  uint32_t  RESERVED0            :24;
        };
        struct {
            __IO  uint32_t  SSINC0               :1;
            __IO  uint32_t  SSINC1               :1;
            __IO  uint32_t  SSINC2               :1;
            __IO  uint32_t  SSINC3               :1;
            __IO  uint32_t  SSINC4               :1;
            __IO  uint32_t  SSINC5               :1;
            __IO  uint32_t  SSINC6               :1;
            __IO  uint32_t  SSINC7               :1;
            __IO  uint32_t  RESERVED1            :24;
        };
    };
} stc_ethernet_mac_ssir_field_t;

typedef struct stc_ethernet_mac_stsr_field
{
    union {
        struct {
            __IO  uint32_t  TSS                  :32;
        };
        struct {
            __IO  uint32_t  TSS0                 :1;
            __IO  uint32_t  TSS1                 :1;
            __IO  uint32_t  TSS2                 :1;
            __IO  uint32_t  TSS3                 :1;
            __IO  uint32_t  TSS4                 :1;
            __IO  uint32_t  TSS5                 :1;
            __IO  uint32_t  TSS6                 :1;
            __IO  uint32_t  TSS7                 :1;
            __IO  uint32_t  TSS8                 :1;
            __IO  uint32_t  TSS9                 :1;
            __IO  uint32_t  TSS10                :1;
            __IO  uint32_t  TSS11                :1;
            __IO  uint32_t  TSS12                :1;
            __IO  uint32_t  TSS13                :1;
            __IO  uint32_t  TSS14                :1;
            __IO  uint32_t  TSS15                :1;
            __IO  uint32_t  TSS16                :1;
            __IO  uint32_t  TSS17                :1;
            __IO  uint32_t  TSS18                :1;
            __IO  uint32_t  TSS19                :1;
            __IO  uint32_t  TSS20                :1;
            __IO  uint32_t  TSS21                :1;
            __IO  uint32_t  TSS22                :1;
            __IO  uint32_t  TSS23                :1;
            __IO  uint32_t  TSS24                :1;
            __IO  uint32_t  TSS25                :1;
            __IO  uint32_t  TSS26                :1;
            __IO  uint32_t  TSS27                :1;
            __IO  uint32_t  TSS28                :1;
            __IO  uint32_t  TSS29                :1;
            __IO  uint32_t  TSS30                :1;
            __IO  uint32_t  TSS31                :1;
        };
    };
} stc_ethernet_mac_stsr_field_t;

typedef struct stc_ethernet_mac_stnr_field
{
    union {
        struct {
            __IO  uint32_t  TSSS                 :31;
            __IO  uint32_t  RESERVED0            :1;
        };
        struct {
            __IO  uint32_t  TSSS0                :1;
            __IO  uint32_t  TSSS1                :1;
            __IO  uint32_t  TSSS2                :1;
            __IO  uint32_t  TSSS3                :1;
            __IO  uint32_t  TSSS4                :1;
            __IO  uint32_t  TSSS5                :1;
            __IO  uint32_t  TSSS6                :1;
            __IO  uint32_t  TSSS7                :1;
            __IO  uint32_t  TSSS8                :1;
            __IO  uint32_t  TSSS9                :1;
            __IO  uint32_t  TSSS10               :1;
            __IO  uint32_t  TSSS11               :1;
            __IO  uint32_t  TSSS12               :1;
            __IO  uint32_t  TSSS13               :1;
            __IO  uint32_t  TSSS14               :1;
            __IO  uint32_t  TSSS15               :1;
            __IO  uint32_t  TSSS16               :1;
            __IO  uint32_t  TSSS17               :1;
            __IO  uint32_t  TSSS18               :1;
            __IO  uint32_t  TSSS19               :1;
            __IO  uint32_t  TSSS20               :1;
            __IO  uint32_t  TSSS21               :1;
            __IO  uint32_t  TSSS22               :1;
            __IO  uint32_t  TSSS23               :1;
            __IO  uint32_t  TSSS24               :1;
            __IO  uint32_t  TSSS25               :1;
            __IO  uint32_t  TSSS26               :1;
            __IO  uint32_t  TSSS27               :1;
            __IO  uint32_t  TSSS28               :1;
            __IO  uint32_t  TSSS29               :1;
            __IO  uint32_t  TSSS30               :1;
            __IO  uint32_t  RESERVED1            :1;
        };
    };
} stc_ethernet_mac_stnr_field_t;

typedef struct stc_ethernet_mac_stsur_field
{
    union {
        struct {
            __IO  uint32_t  TSS                  :32;
        };
        struct {
            __IO  uint32_t  TSS0                 :1;
            __IO  uint32_t  TSS1                 :1;
            __IO  uint32_t  TSS2                 :1;
            __IO  uint32_t  TSS3                 :1;
            __IO  uint32_t  TSS4                 :1;
            __IO  uint32_t  TSS5                 :1;
            __IO  uint32_t  TSS6                 :1;
            __IO  uint32_t  TSS7                 :1;
            __IO  uint32_t  TSS8                 :1;
            __IO  uint32_t  TSS9                 :1;
            __IO  uint32_t  TSS10                :1;
            __IO  uint32_t  TSS11                :1;
            __IO  uint32_t  TSS12                :1;
            __IO  uint32_t  TSS13                :1;
            __IO  uint32_t  TSS14                :1;
            __IO  uint32_t  TSS15                :1;
            __IO  uint32_t  TSS16                :1;
            __IO  uint32_t  TSS17                :1;
            __IO  uint32_t  TSS18                :1;
            __IO  uint32_t  TSS19                :1;
            __IO  uint32_t  TSS20                :1;
            __IO  uint32_t  TSS21                :1;
            __IO  uint32_t  TSS22                :1;
            __IO  uint32_t  TSS23                :1;
            __IO  uint32_t  TSS24                :1;
            __IO  uint32_t  TSS25                :1;
            __IO  uint32_t  TSS26                :1;
            __IO  uint32_t  TSS27                :1;
            __IO  uint32_t  TSS28                :1;
            __IO  uint32_t  TSS29                :1;
            __IO  uint32_t  TSS30                :1;
            __IO  uint32_t  TSS31                :1;
        };
    };
} stc_ethernet_mac_stsur_field_t;

typedef struct stc_ethernet_mac_stnur_field
{
    union {
        struct {
            __IO  uint32_t  TSSS                 :31;
            __IO  uint32_t  ADDSUB               :1;
        };
        struct {
            __IO  uint32_t  TSSS0                :1;
            __IO  uint32_t  TSSS1                :1;
            __IO  uint32_t  TSSS2                :1;
            __IO  uint32_t  TSSS3                :1;
            __IO  uint32_t  TSSS4                :1;
            __IO  uint32_t  TSSS5                :1;
            __IO  uint32_t  TSSS6                :1;
            __IO  uint32_t  TSSS7                :1;
            __IO  uint32_t  TSSS8                :1;
            __IO  uint32_t  TSSS9                :1;
            __IO  uint32_t  TSSS10               :1;
            __IO  uint32_t  TSSS11               :1;
            __IO  uint32_t  TSSS12               :1;
            __IO  uint32_t  TSSS13               :1;
            __IO  uint32_t  TSSS14               :1;
            __IO  uint32_t  TSSS15               :1;
            __IO  uint32_t  TSSS16               :1;
            __IO  uint32_t  TSSS17               :1;
            __IO  uint32_t  TSSS18               :1;
            __IO  uint32_t  TSSS19               :1;
            __IO  uint32_t  TSSS20               :1;
            __IO  uint32_t  TSSS21               :1;
            __IO  uint32_t  TSSS22               :1;
            __IO  uint32_t  TSSS23               :1;
            __IO  uint32_t  TSSS24               :1;
            __IO  uint32_t  TSSS25               :1;
            __IO  uint32_t  TSSS26               :1;
            __IO  uint32_t  TSSS27               :1;
            __IO  uint32_t  TSSS28               :1;
            __IO  uint32_t  TSSS29               :1;
            __IO  uint32_t  TSSS30               :1;
            __IO  uint32_t  RESERVED0            :1;
        };
    };
} stc_ethernet_mac_stnur_field_t;

typedef struct stc_ethernet_mac_tsar_field
{
    union {
        struct {
            __IO  uint32_t  TSAR                 :32;
        };
        struct {
            __IO  uint32_t  TSAR0                :1;
            __IO  uint32_t  TSAR1                :1;
            __IO  uint32_t  TSAR2                :1;
            __IO  uint32_t  TSAR3                :1;
            __IO  uint32_t  TSAR4                :1;
            __IO  uint32_t  TSAR5                :1;
            __IO  uint32_t  TSAR6                :1;
            __IO  uint32_t  TSAR7                :1;
            __IO  uint32_t  TSAR8                :1;
            __IO  uint32_t  TSAR9                :1;
            __IO  uint32_t  TSAR10               :1;
            __IO  uint32_t  TSAR11               :1;
            __IO  uint32_t  TSAR12               :1;
            __IO  uint32_t  TSAR13               :1;
            __IO  uint32_t  TSAR14               :1;
            __IO  uint32_t  TSAR15               :1;
            __IO  uint32_t  TSAR16               :1;
            __IO  uint32_t  TSAR17               :1;
            __IO  uint32_t  TSAR18               :1;
            __IO  uint32_t  TSAR19               :1;
            __IO  uint32_t  TSAR20               :1;
            __IO  uint32_t  TSAR21               :1;
            __IO  uint32_t  TSAR22               :1;
            __IO  uint32_t  TSAR23               :1;
            __IO  uint32_t  TSAR24               :1;
            __IO  uint32_t  TSAR25               :1;
            __IO  uint32_t  TSAR26               :1;
            __IO  uint32_t  TSAR27               :1;
            __IO  uint32_t  TSAR28               :1;
            __IO  uint32_t  TSAR29               :1;
            __IO  uint32_t  TSAR30               :1;
            __IO  uint32_t  TSAR31               :1;
        };
    };
} stc_ethernet_mac_tsar_field_t;

typedef struct stc_ethernet_mac_ttsr_field
{
    union {
        struct {
            __IO  uint32_t  TSTR                 :32;
        };
        struct {
            __IO  uint32_t  TSTR0                :1;
            __IO  uint32_t  TSTR1                :1;
            __IO  uint32_t  TSTR2                :1;
            __IO  uint32_t  TSTR3                :1;
            __IO  uint32_t  TSTR4                :1;
            __IO  uint32_t  TSTR5                :1;
            __IO  uint32_t  TSTR6                :1;
            __IO  uint32_t  TSTR7                :1;
            __IO  uint32_t  TSTR8                :1;
            __IO  uint32_t  TSTR9                :1;
            __IO  uint32_t  TSTR10               :1;
            __IO  uint32_t  TSTR11               :1;
            __IO  uint32_t  TSTR12               :1;
            __IO  uint32_t  TSTR13               :1;
            __IO  uint32_t  TSTR14               :1;
            __IO  uint32_t  TSTR15               :1;
            __IO  uint32_t  TSTR16               :1;
            __IO  uint32_t  TSTR17               :1;
            __IO  uint32_t  TSTR18               :1;
            __IO  uint32_t  TSTR19               :1;
            __IO  uint32_t  TSTR20               :1;
            __IO  uint32_t  TSTR21               :1;
            __IO  uint32_t  TSTR22               :1;
            __IO  uint32_t  TSTR23               :1;
            __IO  uint32_t  TSTR24               :1;
            __IO  uint32_t  TSTR25               :1;
            __IO  uint32_t  TSTR26               :1;
            __IO  uint32_t  TSTR27               :1;
            __IO  uint32_t  TSTR28               :1;
            __IO  uint32_t  TSTR29               :1;
            __IO  uint32_t  TSTR30               :1;
            __IO  uint32_t  TSTR31               :1;
        };
    };
} stc_ethernet_mac_ttsr_field_t;

typedef struct stc_ethernet_mac_ttnr_field
{
    union {
        struct {
            __IO  uint32_t  TSTR                 :31;
            __IO  uint32_t  RESERVED0            :1;
        };
        struct {
            __IO  uint32_t  TSTR0                :1;
            __IO  uint32_t  TSTR1                :1;
            __IO  uint32_t  TSTR2                :1;
            __IO  uint32_t  TSTR3                :1;
            __IO  uint32_t  TSTR4                :1;
            __IO  uint32_t  TSTR5                :1;
            __IO  uint32_t  TSTR6                :1;
            __IO  uint32_t  TSTR7                :1;
            __IO  uint32_t  TSTR8                :1;
            __IO  uint32_t  TSTR9                :1;
            __IO  uint32_t  TSTR10               :1;
            __IO  uint32_t  TSTR11               :1;
            __IO  uint32_t  TSTR12               :1;
            __IO  uint32_t  TSTR13               :1;
            __IO  uint32_t  TSTR14               :1;
            __IO  uint32_t  TSTR15               :1;
            __IO  uint32_t  TSTR16               :1;
            __IO  uint32_t  TSTR17               :1;
            __IO  uint32_t  TSTR18               :1;
            __IO  uint32_t  TSTR19               :1;
            __IO  uint32_t  TSTR20               :1;
            __IO  uint32_t  TSTR21               :1;
            __IO  uint32_t  TSTR22               :1;
            __IO  uint32_t  TSTR23               :1;
            __IO  uint32_t  TSTR24               :1;
            __IO  uint32_t  TSTR25               :1;
            __IO  uint32_t  TSTR26               :1;
            __IO  uint32_t  TSTR27               :1;
            __IO  uint32_t  TSTR28               :1;
            __IO  uint32_t  TSTR29               :1;
            __IO  uint32_t  TSTR30               :1;
            __IO  uint32_t  RESERVED1            :1;
        };
    };
} stc_ethernet_mac_ttnr_field_t;

typedef struct stc_ethernet_mac_sthwsr_field
{
    union {
        struct {
            __IO  uint32_t  TSHWR                :16;
            __IO  uint32_t  RESERVED0            :16;
        };
        struct {
            __IO  uint32_t  TSHWR0               :1;
            __IO  uint32_t  TSHWR1               :1;
            __IO  uint32_t  TSHWR2               :1;
            __IO  uint32_t  TSHWR3               :1;
            __IO  uint32_t  TSHWR4               :1;
            __IO  uint32_t  TSHWR5               :1;
            __IO  uint32_t  TSHWR6               :1;
            __IO  uint32_t  TSHWR7               :1;
            __IO  uint32_t  TSHWR8               :1;
            __IO  uint32_t  TSHWR9               :1;
            __IO  uint32_t  TSHWR10              :1;
            __IO  uint32_t  TSHWR11              :1;
            __IO  uint32_t  TSHWR12              :1;
            __IO  uint32_t  TSHWR13              :1;
            __IO  uint32_t  TSHWR14              :1;
            __IO  uint32_t  TSHWR15              :1;
            __IO  uint32_t  RESERVED1            :16;
        };
    };
} stc_ethernet_mac_sthwsr_field_t;

typedef struct stc_ethernet_mac_tsr_field
{
    union {
        struct {
            __IO  uint32_t  TSSOVF               :1;
            __IO  uint32_t  TSTART               :1;
            __IO  uint32_t  ATSTS                :1;
            __IO  uint32_t  TRGTER               :1;
            __IO  uint32_t  RESERVED0            :20;
            __IO  uint32_t  ATSSTM               :1;
            __IO  uint32_t  ATSNS                :3;
            __IO  uint32_t  RESERVED2            :4;
        };
        struct {
            __IO  uint32_t  RESERVED1            :25;
            __IO  uint32_t  ATSNS0               :1;
            __IO  uint32_t  ATSNS1               :1;
            __IO  uint32_t  ATSNS2               :1;
            __IO  uint32_t  RESERVED3            :4;
        };
    };
} stc_ethernet_mac_tsr_field_t;

typedef struct stc_ethernet_mac_ppscr_field
{
    union {
        struct {
            __IO  uint32_t  PPSCTRL              :4;
            __IO  uint32_t  RESERVED0            :28;
        };
        struct {
            __IO  uint32_t  PPSCTRL0             :1;
            __IO  uint32_t  PPSCTRL1             :1;
            __IO  uint32_t  PPSCTRL2             :1;
            __IO  uint32_t  PPSCTRL3             :1;
            __IO  uint32_t  RESERVED1            :28;
        };
    };
} stc_ethernet_mac_ppscr_field_t;

typedef struct stc_ethernet_mac_atnr_field
{
    union {
        struct {
            __IO  uint32_t  ATN                  :31;
            __IO  uint32_t  RESERVED0            :1;
        };
        struct {
            __IO  uint32_t  ATN0                 :1;
            __IO  uint32_t  ATN1                 :1;
            __IO  uint32_t  ATN2                 :1;
            __IO  uint32_t  ATN3                 :1;
            __IO  uint32_t  ATN4                 :1;
            __IO  uint32_t  ATN5                 :1;
            __IO  uint32_t  ATN6                 :1;
            __IO  uint32_t  ATN7                 :1;
            __IO  uint32_t  ATN8                 :1;
            __IO  uint32_t  ATN9                 :1;
            __IO  uint32_t  ATN10                :1;
            __IO  uint32_t  ATN11                :1;
            __IO  uint32_t  ATN12                :1;
            __IO  uint32_t  ATN13                :1;
            __IO  uint32_t  ATN14                :1;
            __IO  uint32_t  ATN15                :1;
            __IO  uint32_t  ATN16                :1;
            __IO  uint32_t  ATN17                :1;
            __IO  uint32_t  ATN18                :1;
            __IO  uint32_t  ATN19                :1;
            __IO  uint32_t  ATN20                :1;
            __IO  uint32_t  ATN21                :1;
            __IO  uint32_t  ATN22                :1;
            __IO  uint32_t  ATN23                :1;
            __IO  uint32_t  ATN24                :1;
            __IO  uint32_t  ATN25                :1;
            __IO  uint32_t  ATN26                :1;
            __IO  uint32_t  ATN27                :1;
            __IO  uint32_t  ATN28                :1;
            __IO  uint32_t  ATN29                :1;
            __IO  uint32_t  ATN30                :1;
            __IO  uint32_t  RESERVED1            :1;
        };
    };
} stc_ethernet_mac_atnr_field_t;

typedef struct stc_ethernet_mac_atsr_field
{
    union {
        struct {
            __IO  uint32_t  ATS                  :32;
        };
        struct {
            __IO  uint32_t  ATS0                 :1;
            __IO  uint32_t  ATS1                 :1;
            __IO  uint32_t  ATS2                 :1;
            __IO  uint32_t  ATS3                 :1;
            __IO  uint32_t  ATS4                 :1;
            __IO  uint32_t  ATS5                 :1;
            __IO  uint32_t  ATS6                 :1;
            __IO  uint32_t  ATS7                 :1;
            __IO  uint32_t  ATS8                 :1;
            __IO  uint32_t  ATS9                 :1;
            __IO  uint32_t  ATS10                :1;
            __IO  uint32_t  ATS11                :1;
            __IO  uint32_t  ATS12                :1;
            __IO  uint32_t  ATS13                :1;
            __IO  uint32_t  ATS14                :1;
            __IO  uint32_t  ATS15                :1;
            __IO  uint32_t  ATS16                :1;
            __IO  uint32_t  ATS17                :1;
            __IO  uint32_t  ATS18                :1;
            __IO  uint32_t  ATS19                :1;
            __IO  uint32_t  ATS20                :1;
            __IO  uint32_t  ATS21                :1;
            __IO  uint32_t  ATS22                :1;
            __IO  uint32_t  ATS23                :1;
            __IO  uint32_t  ATS24                :1;
            __IO  uint32_t  ATS25                :1;
            __IO  uint32_t  ATS26                :1;
            __IO  uint32_t  ATS27                :1;
            __IO  uint32_t  ATS28                :1;
            __IO  uint32_t  ATS29                :1;
            __IO  uint32_t  ATS30                :1;
            __IO  uint32_t  ATS31                :1;
        };
    };
} stc_ethernet_mac_atsr_field_t;

typedef struct stc_ethernet_mac_mar16h_field
{
    union {
        struct {
            __IO  uint32_t  A                    :16;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MBC                  :6;
            __IO  uint32_t  SA                   :1;
            __IO  uint32_t  AE                   :1;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MBC0                 :1;
            __IO  uint32_t  MBC1                 :1;
            __IO  uint32_t  MBC2                 :1;
            __IO  uint32_t  MBC3                 :1;
            __IO  uint32_t  MBC4                 :1;
            __IO  uint32_t  MBC5                 :1;
            __IO  uint32_t  RESERVED2            :2;
        };
    };
} stc_ethernet_mac_mar16h_field_t;

typedef struct stc_ethernet_mac_mar16l_field
{
    union {
        struct {
            __IO  uint32_t  A                    :32;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  A16                  :1;
            __IO  uint32_t  A17                  :1;
            __IO  uint32_t  A18                  :1;
            __IO  uint32_t  A19                  :1;
            __IO  uint32_t  A20                  :1;
            __IO  uint32_t  A21                  :1;
            __IO  uint32_t  A22                  :1;
            __IO  uint32_t  A23                  :1;
            __IO  uint32_t  A24                  :1;
            __IO  uint32_t  A25                  :1;
            __IO  uint32_t  A26                  :1;
            __IO  uint32_t  A27                  :1;
            __IO  uint32_t  A28                  :1;
            __IO  uint32_t  A29                  :1;
            __IO  uint32_t  A30                  :1;
            __IO  uint32_t  A31                  :1;
        };
    };
} stc_ethernet_mac_mar16l_field_t;

typedef struct stc_ethernet_mac_mar17h_field
{
    union {
        struct {
            __IO  uint32_t  A                    :16;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MBC                  :6;
            __IO  uint32_t  SA                   :1;
            __IO  uint32_t  AE                   :1;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MBC0                 :1;
            __IO  uint32_t  MBC1                 :1;
            __IO  uint32_t  MBC2                 :1;
            __IO  uint32_t  MBC3                 :1;
            __IO  uint32_t  MBC4                 :1;
            __IO  uint32_t  MBC5                 :1;
            __IO  uint32_t  RESERVED2            :2;
        };
    };
} stc_ethernet_mac_mar17h_field_t;

typedef struct stc_ethernet_mac_mar17l_field
{
    union {
        struct {
            __IO  uint32_t  A                    :32;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  A16                  :1;
            __IO  uint32_t  A17                  :1;
            __IO  uint32_t  A18                  :1;
            __IO  uint32_t  A19                  :1;
            __IO  uint32_t  A20                  :1;
            __IO  uint32_t  A21                  :1;
            __IO  uint32_t  A22                  :1;
            __IO  uint32_t  A23                  :1;
            __IO  uint32_t  A24                  :1;
            __IO  uint32_t  A25                  :1;
            __IO  uint32_t  A26                  :1;
            __IO  uint32_t  A27                  :1;
            __IO  uint32_t  A28                  :1;
            __IO  uint32_t  A29                  :1;
            __IO  uint32_t  A30                  :1;
            __IO  uint32_t  A31                  :1;
        };
    };
} stc_ethernet_mac_mar17l_field_t;

typedef struct stc_ethernet_mac_mar18h_field
{
    union {
        struct {
            __IO  uint32_t  A                    :16;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MBC                  :6;
            __IO  uint32_t  SA                   :1;
            __IO  uint32_t  AE                   :1;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MBC0                 :1;
            __IO  uint32_t  MBC1                 :1;
            __IO  uint32_t  MBC2                 :1;
            __IO  uint32_t  MBC3                 :1;
            __IO  uint32_t  MBC4                 :1;
            __IO  uint32_t  MBC5                 :1;
            __IO  uint32_t  RESERVED2            :2;
        };
    };
} stc_ethernet_mac_mar18h_field_t;

typedef struct stc_ethernet_mac_mar18l_field
{
    union {
        struct {
            __IO  uint32_t  A                    :32;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  A16                  :1;
            __IO  uint32_t  A17                  :1;
            __IO  uint32_t  A18                  :1;
            __IO  uint32_t  A19                  :1;
            __IO  uint32_t  A20                  :1;
            __IO  uint32_t  A21                  :1;
            __IO  uint32_t  A22                  :1;
            __IO  uint32_t  A23                  :1;
            __IO  uint32_t  A24                  :1;
            __IO  uint32_t  A25                  :1;
            __IO  uint32_t  A26                  :1;
            __IO  uint32_t  A27                  :1;
            __IO  uint32_t  A28                  :1;
            __IO  uint32_t  A29                  :1;
            __IO  uint32_t  A30                  :1;
            __IO  uint32_t  A31                  :1;
        };
    };
} stc_ethernet_mac_mar18l_field_t;

typedef struct stc_ethernet_mac_mar19h_field
{
    union {
        struct {
            __IO  uint32_t  A                    :16;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MBC                  :6;
            __IO  uint32_t  SA                   :1;
            __IO  uint32_t  AE                   :1;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MBC0                 :1;
            __IO  uint32_t  MBC1                 :1;
            __IO  uint32_t  MBC2                 :1;
            __IO  uint32_t  MBC3                 :1;
            __IO  uint32_t  MBC4                 :1;
            __IO  uint32_t  MBC5                 :1;
            __IO  uint32_t  RESERVED2            :2;
        };
    };
} stc_ethernet_mac_mar19h_field_t;

typedef struct stc_ethernet_mac_mar19l_field
{
    union {
        struct {
            __IO  uint32_t  A                    :32;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  A16                  :1;
            __IO  uint32_t  A17                  :1;
            __IO  uint32_t  A18                  :1;
            __IO  uint32_t  A19                  :1;
            __IO  uint32_t  A20                  :1;
            __IO  uint32_t  A21                  :1;
            __IO  uint32_t  A22                  :1;
            __IO  uint32_t  A23                  :1;
            __IO  uint32_t  A24                  :1;
            __IO  uint32_t  A25                  :1;
            __IO  uint32_t  A26                  :1;
            __IO  uint32_t  A27                  :1;
            __IO  uint32_t  A28                  :1;
            __IO  uint32_t  A29                  :1;
            __IO  uint32_t  A30                  :1;
            __IO  uint32_t  A31                  :1;
        };
    };
} stc_ethernet_mac_mar19l_field_t;

typedef struct stc_ethernet_mac_mar20h_field
{
    union {
        struct {
            __IO  uint32_t  A                    :16;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MBC                  :6;
            __IO  uint32_t  SA                   :1;
            __IO  uint32_t  AE                   :1;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MBC0                 :1;
            __IO  uint32_t  MBC1                 :1;
            __IO  uint32_t  MBC2                 :1;
            __IO  uint32_t  MBC3                 :1;
            __IO  uint32_t  MBC4                 :1;
            __IO  uint32_t  MBC5                 :1;
            __IO  uint32_t  RESERVED2            :2;
        };
    };
} stc_ethernet_mac_mar20h_field_t;

typedef struct stc_ethernet_mac_mar20l_field
{
    union {
        struct {
            __IO  uint32_t  A                    :32;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  A16                  :1;
            __IO  uint32_t  A17                  :1;
            __IO  uint32_t  A18                  :1;
            __IO  uint32_t  A19                  :1;
            __IO  uint32_t  A20                  :1;
            __IO  uint32_t  A21                  :1;
            __IO  uint32_t  A22                  :1;
            __IO  uint32_t  A23                  :1;
            __IO  uint32_t  A24                  :1;
            __IO  uint32_t  A25                  :1;
            __IO  uint32_t  A26                  :1;
            __IO  uint32_t  A27                  :1;
            __IO  uint32_t  A28                  :1;
            __IO  uint32_t  A29                  :1;
            __IO  uint32_t  A30                  :1;
            __IO  uint32_t  A31                  :1;
        };
    };
} stc_ethernet_mac_mar20l_field_t;

typedef struct stc_ethernet_mac_mar21h_field
{
    union {
        struct {
            __IO  uint32_t  A                    :16;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MBC                  :6;
            __IO  uint32_t  SA                   :1;
            __IO  uint32_t  AE                   :1;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MBC0                 :1;
            __IO  uint32_t  MBC1                 :1;
            __IO  uint32_t  MBC2                 :1;
            __IO  uint32_t  MBC3                 :1;
            __IO  uint32_t  MBC4                 :1;
            __IO  uint32_t  MBC5                 :1;
            __IO  uint32_t  RESERVED2            :2;
        };
    };
} stc_ethernet_mac_mar21h_field_t;

typedef struct stc_ethernet_mac_mar21l_field
{
    union {
        struct {
            __IO  uint32_t  A                    :32;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  A16                  :1;
            __IO  uint32_t  A17                  :1;
            __IO  uint32_t  A18                  :1;
            __IO  uint32_t  A19                  :1;
            __IO  uint32_t  A20                  :1;
            __IO  uint32_t  A21                  :1;
            __IO  uint32_t  A22                  :1;
            __IO  uint32_t  A23                  :1;
            __IO  uint32_t  A24                  :1;
            __IO  uint32_t  A25                  :1;
            __IO  uint32_t  A26                  :1;
            __IO  uint32_t  A27                  :1;
            __IO  uint32_t  A28                  :1;
            __IO  uint32_t  A29                  :1;
            __IO  uint32_t  A30                  :1;
            __IO  uint32_t  A31                  :1;
        };
    };
} stc_ethernet_mac_mar21l_field_t;

typedef struct stc_ethernet_mac_mar22h_field
{
    union {
        struct {
            __IO  uint32_t  A                    :16;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MBC                  :6;
            __IO  uint32_t  SA                   :1;
            __IO  uint32_t  AE                   :1;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MBC0                 :1;
            __IO  uint32_t  MBC1                 :1;
            __IO  uint32_t  MBC2                 :1;
            __IO  uint32_t  MBC3                 :1;
            __IO  uint32_t  MBC4                 :1;
            __IO  uint32_t  MBC5                 :1;
            __IO  uint32_t  RESERVED2            :2;
        };
    };
} stc_ethernet_mac_mar22h_field_t;

typedef struct stc_ethernet_mac_mar22l_field
{
    union {
        struct {
            __IO  uint32_t  A                    :32;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  A16                  :1;
            __IO  uint32_t  A17                  :1;
            __IO  uint32_t  A18                  :1;
            __IO  uint32_t  A19                  :1;
            __IO  uint32_t  A20                  :1;
            __IO  uint32_t  A21                  :1;
            __IO  uint32_t  A22                  :1;
            __IO  uint32_t  A23                  :1;
            __IO  uint32_t  A24                  :1;
            __IO  uint32_t  A25                  :1;
            __IO  uint32_t  A26                  :1;
            __IO  uint32_t  A27                  :1;
            __IO  uint32_t  A28                  :1;
            __IO  uint32_t  A29                  :1;
            __IO  uint32_t  A30                  :1;
            __IO  uint32_t  A31                  :1;
        };
    };
} stc_ethernet_mac_mar22l_field_t;

typedef struct stc_ethernet_mac_mar23h_field
{
    union {
        struct {
            __IO  uint32_t  A                    :16;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MBC                  :6;
            __IO  uint32_t  SA                   :1;
            __IO  uint32_t  AE                   :1;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MBC0                 :1;
            __IO  uint32_t  MBC1                 :1;
            __IO  uint32_t  MBC2                 :1;
            __IO  uint32_t  MBC3                 :1;
            __IO  uint32_t  MBC4                 :1;
            __IO  uint32_t  MBC5                 :1;
            __IO  uint32_t  RESERVED2            :2;
        };
    };
} stc_ethernet_mac_mar23h_field_t;

typedef struct stc_ethernet_mac_mar23l_field
{
    union {
        struct {
            __IO  uint32_t  A                    :32;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  A16                  :1;
            __IO  uint32_t  A17                  :1;
            __IO  uint32_t  A18                  :1;
            __IO  uint32_t  A19                  :1;
            __IO  uint32_t  A20                  :1;
            __IO  uint32_t  A21                  :1;
            __IO  uint32_t  A22                  :1;
            __IO  uint32_t  A23                  :1;
            __IO  uint32_t  A24                  :1;
            __IO  uint32_t  A25                  :1;
            __IO  uint32_t  A26                  :1;
            __IO  uint32_t  A27                  :1;
            __IO  uint32_t  A28                  :1;
            __IO  uint32_t  A29                  :1;
            __IO  uint32_t  A30                  :1;
            __IO  uint32_t  A31                  :1;
        };
    };
} stc_ethernet_mac_mar23l_field_t;

typedef struct stc_ethernet_mac_mar24h_field
{
    union {
        struct {
            __IO  uint32_t  A                    :16;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MBC                  :6;
            __IO  uint32_t  SA                   :1;
            __IO  uint32_t  AE                   :1;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MBC0                 :1;
            __IO  uint32_t  MBC1                 :1;
            __IO  uint32_t  MBC2                 :1;
            __IO  uint32_t  MBC3                 :1;
            __IO  uint32_t  MBC4                 :1;
            __IO  uint32_t  MBC5                 :1;
            __IO  uint32_t  RESERVED2            :2;
        };
    };
} stc_ethernet_mac_mar24h_field_t;

typedef struct stc_ethernet_mac_mar24l_field
{
    union {
        struct {
            __IO  uint32_t  A                    :32;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  A16                  :1;
            __IO  uint32_t  A17                  :1;
            __IO  uint32_t  A18                  :1;
            __IO  uint32_t  A19                  :1;
            __IO  uint32_t  A20                  :1;
            __IO  uint32_t  A21                  :1;
            __IO  uint32_t  A22                  :1;
            __IO  uint32_t  A23                  :1;
            __IO  uint32_t  A24                  :1;
            __IO  uint32_t  A25                  :1;
            __IO  uint32_t  A26                  :1;
            __IO  uint32_t  A27                  :1;
            __IO  uint32_t  A28                  :1;
            __IO  uint32_t  A29                  :1;
            __IO  uint32_t  A30                  :1;
            __IO  uint32_t  A31                  :1;
        };
    };
} stc_ethernet_mac_mar24l_field_t;

typedef struct stc_ethernet_mac_mar25h_field
{
    union {
        struct {
            __IO  uint32_t  A                    :16;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MBC                  :6;
            __IO  uint32_t  SA                   :1;
            __IO  uint32_t  AE                   :1;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MBC0                 :1;
            __IO  uint32_t  MBC1                 :1;
            __IO  uint32_t  MBC2                 :1;
            __IO  uint32_t  MBC3                 :1;
            __IO  uint32_t  MBC4                 :1;
            __IO  uint32_t  MBC5                 :1;
            __IO  uint32_t  RESERVED2            :2;
        };
    };
} stc_ethernet_mac_mar25h_field_t;

typedef struct stc_ethernet_mac_mar25l_field
{
    union {
        struct {
            __IO  uint32_t  A                    :32;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  A16                  :1;
            __IO  uint32_t  A17                  :1;
            __IO  uint32_t  A18                  :1;
            __IO  uint32_t  A19                  :1;
            __IO  uint32_t  A20                  :1;
            __IO  uint32_t  A21                  :1;
            __IO  uint32_t  A22                  :1;
            __IO  uint32_t  A23                  :1;
            __IO  uint32_t  A24                  :1;
            __IO  uint32_t  A25                  :1;
            __IO  uint32_t  A26                  :1;
            __IO  uint32_t  A27                  :1;
            __IO  uint32_t  A28                  :1;
            __IO  uint32_t  A29                  :1;
            __IO  uint32_t  A30                  :1;
            __IO  uint32_t  A31                  :1;
        };
    };
} stc_ethernet_mac_mar25l_field_t;

typedef struct stc_ethernet_mac_mar26h_field
{
    union {
        struct {
            __IO  uint32_t  A                    :16;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MBC                  :6;
            __IO  uint32_t  SA                   :1;
            __IO  uint32_t  AE                   :1;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MBC0                 :1;
            __IO  uint32_t  MBC1                 :1;
            __IO  uint32_t  MBC2                 :1;
            __IO  uint32_t  MBC3                 :1;
            __IO  uint32_t  MBC4                 :1;
            __IO  uint32_t  MBC5                 :1;
            __IO  uint32_t  RESERVED2            :2;
        };
    };
} stc_ethernet_mac_mar26h_field_t;

typedef struct stc_ethernet_mac_mar26l_field
{
    union {
        struct {
            __IO  uint32_t  A                    :32;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  A16                  :1;
            __IO  uint32_t  A17                  :1;
            __IO  uint32_t  A18                  :1;
            __IO  uint32_t  A19                  :1;
            __IO  uint32_t  A20                  :1;
            __IO  uint32_t  A21                  :1;
            __IO  uint32_t  A22                  :1;
            __IO  uint32_t  A23                  :1;
            __IO  uint32_t  A24                  :1;
            __IO  uint32_t  A25                  :1;
            __IO  uint32_t  A26                  :1;
            __IO  uint32_t  A27                  :1;
            __IO  uint32_t  A28                  :1;
            __IO  uint32_t  A29                  :1;
            __IO  uint32_t  A30                  :1;
            __IO  uint32_t  A31                  :1;
        };
    };
} stc_ethernet_mac_mar26l_field_t;

typedef struct stc_ethernet_mac_mar27h_field
{
    union {
        struct {
            __IO  uint32_t  A                    :16;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MBC                  :6;
            __IO  uint32_t  SA                   :1;
            __IO  uint32_t  AE                   :1;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MBC0                 :1;
            __IO  uint32_t  MBC1                 :1;
            __IO  uint32_t  MBC2                 :1;
            __IO  uint32_t  MBC3                 :1;
            __IO  uint32_t  MBC4                 :1;
            __IO  uint32_t  MBC5                 :1;
            __IO  uint32_t  RESERVED2            :2;
        };
    };
} stc_ethernet_mac_mar27h_field_t;

typedef struct stc_ethernet_mac_mar27l_field
{
    union {
        struct {
            __IO  uint32_t  A                    :32;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  A16                  :1;
            __IO  uint32_t  A17                  :1;
            __IO  uint32_t  A18                  :1;
            __IO  uint32_t  A19                  :1;
            __IO  uint32_t  A20                  :1;
            __IO  uint32_t  A21                  :1;
            __IO  uint32_t  A22                  :1;
            __IO  uint32_t  A23                  :1;
            __IO  uint32_t  A24                  :1;
            __IO  uint32_t  A25                  :1;
            __IO  uint32_t  A26                  :1;
            __IO  uint32_t  A27                  :1;
            __IO  uint32_t  A28                  :1;
            __IO  uint32_t  A29                  :1;
            __IO  uint32_t  A30                  :1;
            __IO  uint32_t  A31                  :1;
        };
    };
} stc_ethernet_mac_mar27l_field_t;

typedef struct stc_ethernet_mac_mar28h_field
{
    union {
        struct {
            __IO  uint32_t  A                    :16;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MBC                  :6;
            __IO  uint32_t  SA                   :1;
            __IO  uint32_t  AE                   :1;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MBC0                 :1;
            __IO  uint32_t  MBC1                 :1;
            __IO  uint32_t  MBC2                 :1;
            __IO  uint32_t  MBC3                 :1;
            __IO  uint32_t  MBC4                 :1;
            __IO  uint32_t  MBC5                 :1;
            __IO  uint32_t  RESERVED2            :2;
        };
    };
} stc_ethernet_mac_mar28h_field_t;

typedef struct stc_ethernet_mac_mar28l_field
{
    union {
        struct {
            __IO  uint32_t  A                    :32;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  A16                  :1;
            __IO  uint32_t  A17                  :1;
            __IO  uint32_t  A18                  :1;
            __IO  uint32_t  A19                  :1;
            __IO  uint32_t  A20                  :1;
            __IO  uint32_t  A21                  :1;
            __IO  uint32_t  A22                  :1;
            __IO  uint32_t  A23                  :1;
            __IO  uint32_t  A24                  :1;
            __IO  uint32_t  A25                  :1;
            __IO  uint32_t  A26                  :1;
            __IO  uint32_t  A27                  :1;
            __IO  uint32_t  A28                  :1;
            __IO  uint32_t  A29                  :1;
            __IO  uint32_t  A30                  :1;
            __IO  uint32_t  A31                  :1;
        };
    };
} stc_ethernet_mac_mar28l_field_t;

typedef struct stc_ethernet_mac_mar29h_field
{
    union {
        struct {
            __IO  uint32_t  A                    :16;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MBC                  :6;
            __IO  uint32_t  SA                   :1;
            __IO  uint32_t  AE                   :1;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MBC0                 :1;
            __IO  uint32_t  MBC1                 :1;
            __IO  uint32_t  MBC2                 :1;
            __IO  uint32_t  MBC3                 :1;
            __IO  uint32_t  MBC4                 :1;
            __IO  uint32_t  MBC5                 :1;
            __IO  uint32_t  RESERVED2            :2;
        };
    };
} stc_ethernet_mac_mar29h_field_t;

typedef struct stc_ethernet_mac_mar29l_field
{
    union {
        struct {
            __IO  uint32_t  A                    :32;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  A16                  :1;
            __IO  uint32_t  A17                  :1;
            __IO  uint32_t  A18                  :1;
            __IO  uint32_t  A19                  :1;
            __IO  uint32_t  A20                  :1;
            __IO  uint32_t  A21                  :1;
            __IO  uint32_t  A22                  :1;
            __IO  uint32_t  A23                  :1;
            __IO  uint32_t  A24                  :1;
            __IO  uint32_t  A25                  :1;
            __IO  uint32_t  A26                  :1;
            __IO  uint32_t  A27                  :1;
            __IO  uint32_t  A28                  :1;
            __IO  uint32_t  A29                  :1;
            __IO  uint32_t  A30                  :1;
            __IO  uint32_t  A31                  :1;
        };
    };
} stc_ethernet_mac_mar29l_field_t;

typedef struct stc_ethernet_mac_mar30h_field
{
    union {
        struct {
            __IO  uint32_t  A                    :16;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MBC                  :6;
            __IO  uint32_t  SA                   :1;
            __IO  uint32_t  AE                   :1;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MBC0                 :1;
            __IO  uint32_t  MBC1                 :1;
            __IO  uint32_t  MBC2                 :1;
            __IO  uint32_t  MBC3                 :1;
            __IO  uint32_t  MBC4                 :1;
            __IO  uint32_t  MBC5                 :1;
            __IO  uint32_t  RESERVED2            :2;
        };
    };
} stc_ethernet_mac_mar30h_field_t;

typedef struct stc_ethernet_mac_mar30l_field
{
    union {
        struct {
            __IO  uint32_t  A                    :32;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  A16                  :1;
            __IO  uint32_t  A17                  :1;
            __IO  uint32_t  A18                  :1;
            __IO  uint32_t  A19                  :1;
            __IO  uint32_t  A20                  :1;
            __IO  uint32_t  A21                  :1;
            __IO  uint32_t  A22                  :1;
            __IO  uint32_t  A23                  :1;
            __IO  uint32_t  A24                  :1;
            __IO  uint32_t  A25                  :1;
            __IO  uint32_t  A26                  :1;
            __IO  uint32_t  A27                  :1;
            __IO  uint32_t  A28                  :1;
            __IO  uint32_t  A29                  :1;
            __IO  uint32_t  A30                  :1;
            __IO  uint32_t  A31                  :1;
        };
    };
} stc_ethernet_mac_mar30l_field_t;

typedef struct stc_ethernet_mac_mar31h_field
{
    union {
        struct {
            __IO  uint32_t  A                    :16;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MBC                  :6;
            __IO  uint32_t  SA                   :1;
            __IO  uint32_t  AE                   :1;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MBC0                 :1;
            __IO  uint32_t  MBC1                 :1;
            __IO  uint32_t  MBC2                 :1;
            __IO  uint32_t  MBC3                 :1;
            __IO  uint32_t  MBC4                 :1;
            __IO  uint32_t  MBC5                 :1;
            __IO  uint32_t  RESERVED2            :2;
        };
    };
} stc_ethernet_mac_mar31h_field_t;

typedef struct stc_ethernet_mac_mar31l_field
{
    union {
        struct {
            __IO  uint32_t  A                    :32;
        };
        struct {
            __IO  uint32_t  A0                   :1;
            __IO  uint32_t  A1                   :1;
            __IO  uint32_t  A2                   :1;
            __IO  uint32_t  A3                   :1;
            __IO  uint32_t  A4                   :1;
            __IO  uint32_t  A5                   :1;
            __IO  uint32_t  A6                   :1;
            __IO  uint32_t  A7                   :1;
            __IO  uint32_t  A8                   :1;
            __IO  uint32_t  A9                   :1;
            __IO  uint32_t  A10                  :1;
            __IO  uint32_t  A11                  :1;
            __IO  uint32_t  A12                  :1;
            __IO  uint32_t  A13                  :1;
            __IO  uint32_t  A14                  :1;
            __IO  uint32_t  A15                  :1;
            __IO  uint32_t  A16                  :1;
            __IO  uint32_t  A17                  :1;
            __IO  uint32_t  A18                  :1;
            __IO  uint32_t  A19                  :1;
            __IO  uint32_t  A20                  :1;
            __IO  uint32_t  A21                  :1;
            __IO  uint32_t  A22                  :1;
            __IO  uint32_t  A23                  :1;
            __IO  uint32_t  A24                  :1;
            __IO  uint32_t  A25                  :1;
            __IO  uint32_t  A26                  :1;
            __IO  uint32_t  A27                  :1;
            __IO  uint32_t  A28                  :1;
            __IO  uint32_t  A29                  :1;
            __IO  uint32_t  A30                  :1;
            __IO  uint32_t  A31                  :1;
        };
    };
} stc_ethernet_mac_mar31l_field_t;

typedef struct stc_ethernet_mac_bmr_field
{
    union {
        struct {
            __IO  uint32_t  SWR                  :1;
            __IO  uint32_t  DA                   :1;
            __IO  uint32_t  DSL                  :5;
            __IO  uint32_t  ATDS                 :1;
            __IO  uint32_t  PBL                  :6;
            __IO  uint32_t  PR                   :2;
            __IO  uint32_t  FB                   :1;
            __IO  uint32_t  RPBL                 :6;
            __IO  uint32_t  USP                  :1;
            __IO  uint32_t  _8XPBL               :1;
            __IO  uint32_t  AAL                  :1;
            __IO  uint32_t  MB                   :1;
            __IO  uint32_t  TXPR                 :1;
            __IO  uint32_t  RESERVED3            :4;
        };
        struct {
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  DSL0                 :1;
            __IO  uint32_t  DSL1                 :1;
            __IO  uint32_t  DSL2                 :1;
            __IO  uint32_t  DSL3                 :1;
            __IO  uint32_t  DSL4                 :1;
            __IO  uint32_t  RESERVED1            :1;
            __IO  uint32_t  PBL0                 :1;
            __IO  uint32_t  PBL1                 :1;
            __IO  uint32_t  PBL2                 :1;
            __IO  uint32_t  PBL3                 :1;
            __IO  uint32_t  PBL4                 :1;
            __IO  uint32_t  PBL5                 :1;
            __IO  uint32_t  PR0                  :1;
            __IO  uint32_t  PR1                  :1;
            __IO  uint32_t  RESERVED2            :1;
            __IO  uint32_t  RPBL0                :1;
            __IO  uint32_t  RPBL1                :1;
            __IO  uint32_t  RPBL2                :1;
            __IO  uint32_t  RPBL3                :1;
            __IO  uint32_t  RPBL4                :1;
            __IO  uint32_t  RPBL5                :1;
            __IO  uint32_t  RESERVED4            :9;
        };
    };
} stc_ethernet_mac_bmr_field_t;

typedef struct stc_ethernet_mac_tpdr_field
{
    union {
        struct {
            __IO  uint32_t  TPD                  :32;
        };
        struct {
            __IO  uint32_t  TPD0                 :1;
            __IO  uint32_t  TPD1                 :1;
            __IO  uint32_t  TPD2                 :1;
            __IO  uint32_t  TPD3                 :1;
            __IO  uint32_t  TPD4                 :1;
            __IO  uint32_t  TPD5                 :1;
            __IO  uint32_t  TPD6                 :1;
            __IO  uint32_t  TPD7                 :1;
            __IO  uint32_t  TPD8                 :1;
            __IO  uint32_t  TPD9                 :1;
            __IO  uint32_t  TPD10                :1;
            __IO  uint32_t  TPD11                :1;
            __IO  uint32_t  TPD12                :1;
            __IO  uint32_t  TPD13                :1;
            __IO  uint32_t  TPD14                :1;
            __IO  uint32_t  TPD15                :1;
            __IO  uint32_t  TPD16                :1;
            __IO  uint32_t  TPD17                :1;
            __IO  uint32_t  TPD18                :1;
            __IO  uint32_t  TPD19                :1;
            __IO  uint32_t  TPD20                :1;
            __IO  uint32_t  TPD21                :1;
            __IO  uint32_t  TPD22                :1;
            __IO  uint32_t  TPD23                :1;
            __IO  uint32_t  TPD24                :1;
            __IO  uint32_t  TPD25                :1;
            __IO  uint32_t  TPD26                :1;
            __IO  uint32_t  TPD27                :1;
            __IO  uint32_t  TPD28                :1;
            __IO  uint32_t  TPD29                :1;
            __IO  uint32_t  TPD30                :1;
            __IO  uint32_t  TPD31                :1;
        };
    };
} stc_ethernet_mac_tpdr_field_t;

typedef struct stc_ethernet_mac_rpdr_field
{
    union {
        struct {
            __IO  uint32_t  RPD                  :32;
        };
        struct {
            __IO  uint32_t  RPD0                 :1;
            __IO  uint32_t  RPD1                 :1;
            __IO  uint32_t  RPD2                 :1;
            __IO  uint32_t  RPD3                 :1;
            __IO  uint32_t  RPD4                 :1;
            __IO  uint32_t  RPD5                 :1;
            __IO  uint32_t  RPD6                 :1;
            __IO  uint32_t  RPD7                 :1;
            __IO  uint32_t  RPD8                 :1;
            __IO  uint32_t  RPD9                 :1;
            __IO  uint32_t  RPD10                :1;
            __IO  uint32_t  RPD11                :1;
            __IO  uint32_t  RPD12                :1;
            __IO  uint32_t  RPD13                :1;
            __IO  uint32_t  RPD14                :1;
            __IO  uint32_t  RPD15                :1;
            __IO  uint32_t  RPD16                :1;
            __IO  uint32_t  RPD17                :1;
            __IO  uint32_t  RPD18                :1;
            __IO  uint32_t  RPD19                :1;
            __IO  uint32_t  RPD20                :1;
            __IO  uint32_t  RPD21                :1;
            __IO  uint32_t  RPD22                :1;
            __IO  uint32_t  RPD23                :1;
            __IO  uint32_t  RPD24                :1;
            __IO  uint32_t  RPD25                :1;
            __IO  uint32_t  RPD26                :1;
            __IO  uint32_t  RPD27                :1;
            __IO  uint32_t  RPD28                :1;
            __IO  uint32_t  RPD29                :1;
            __IO  uint32_t  RPD30                :1;
            __IO  uint32_t  RPD31                :1;
        };
    };
} stc_ethernet_mac_rpdr_field_t;

typedef struct stc_ethernet_mac_rdlar_field
{
    union {
        struct {
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  SRL                  :30;
        };
        struct {
            __IO  uint32_t  RESERVED1            :2;
            __IO  uint32_t  SRL0                 :1;
            __IO  uint32_t  SRL1                 :1;
            __IO  uint32_t  SRL2                 :1;
            __IO  uint32_t  SRL3                 :1;
            __IO  uint32_t  SRL4                 :1;
            __IO  uint32_t  SRL5                 :1;
            __IO  uint32_t  SRL6                 :1;
            __IO  uint32_t  SRL7                 :1;
            __IO  uint32_t  SRL8                 :1;
            __IO  uint32_t  SRL9                 :1;
            __IO  uint32_t  SRL10                :1;
            __IO  uint32_t  SRL11                :1;
            __IO  uint32_t  SRL12                :1;
            __IO  uint32_t  SRL13                :1;
            __IO  uint32_t  SRL14                :1;
            __IO  uint32_t  SRL15                :1;
            __IO  uint32_t  SRL16                :1;
            __IO  uint32_t  SRL17                :1;
            __IO  uint32_t  SRL18                :1;
            __IO  uint32_t  SRL19                :1;
            __IO  uint32_t  SRL20                :1;
            __IO  uint32_t  SRL21                :1;
            __IO  uint32_t  SRL22                :1;
            __IO  uint32_t  SRL23                :1;
            __IO  uint32_t  SRL24                :1;
            __IO  uint32_t  SRL25                :1;
            __IO  uint32_t  SRL26                :1;
            __IO  uint32_t  SRL27                :1;
            __IO  uint32_t  SRL28                :1;
            __IO  uint32_t  SRL29                :1;
        };
    };
} stc_ethernet_mac_rdlar_field_t;

typedef struct stc_ethernet_mac_tdlar_field
{
    union {
        struct {
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  STL                  :30;
        };
        struct {
            __IO  uint32_t  RESERVED1            :2;
            __IO  uint32_t  STL0                 :1;
            __IO  uint32_t  STL1                 :1;
            __IO  uint32_t  STL2                 :1;
            __IO  uint32_t  STL3                 :1;
            __IO  uint32_t  STL4                 :1;
            __IO  uint32_t  STL5                 :1;
            __IO  uint32_t  STL6                 :1;
            __IO  uint32_t  STL7                 :1;
            __IO  uint32_t  STL8                 :1;
            __IO  uint32_t  STL9                 :1;
            __IO  uint32_t  STL10                :1;
            __IO  uint32_t  STL11                :1;
            __IO  uint32_t  STL12                :1;
            __IO  uint32_t  STL13                :1;
            __IO  uint32_t  STL14                :1;
            __IO  uint32_t  STL15                :1;
            __IO  uint32_t  STL16                :1;
            __IO  uint32_t  STL17                :1;
            __IO  uint32_t  STL18                :1;
            __IO  uint32_t  STL19                :1;
            __IO  uint32_t  STL20                :1;
            __IO  uint32_t  STL21                :1;
            __IO  uint32_t  STL22                :1;
            __IO  uint32_t  STL23                :1;
            __IO  uint32_t  STL24                :1;
            __IO  uint32_t  STL25                :1;
            __IO  uint32_t  STL26                :1;
            __IO  uint32_t  STL27                :1;
            __IO  uint32_t  STL28                :1;
            __IO  uint32_t  STL29                :1;
        };
    };
} stc_ethernet_mac_tdlar_field_t;

typedef struct stc_ethernet_mac_sr_field
{
    union {
        struct {
            __IO  uint32_t  TI                   :1;
            __IO  uint32_t  TPS                  :1;
            __IO  uint32_t  TU                   :1;
            __IO  uint32_t  TJT                  :1;
            __IO  uint32_t  OVF                  :1;
            __IO  uint32_t  UNF                  :1;
            __IO  uint32_t  RI                   :1;
            __IO  uint32_t  RU                   :1;
            __IO  uint32_t  RPS                  :1;
            __IO  uint32_t  RWT                  :1;
            __IO  uint32_t  ETI                  :1;
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  FBI                  :1;
            __IO  uint32_t  ERI                  :1;
            __IO  uint32_t  AIS                  :1;
            __IO  uint32_t  NIS                  :1;
            __IO  uint32_t  RS                   :3;
            __IO  uint32_t  TS                   :3;
            __IO  uint32_t  EB                   :3;
            __IO  uint32_t  GLI                  :1;
            __IO  uint32_t  GMI                  :1;
            __IO  uint32_t  GPI                  :1;
            __IO  uint32_t  TTI                  :1;
            __IO  uint32_t  GLPII                :1;
            __IO  uint32_t  RESERVED2            :1;
        };
        struct {
            __IO  uint32_t  RESERVED1            :17;
            __IO  uint32_t  RS0                  :1;
            __IO  uint32_t  RS1                  :1;
            __IO  uint32_t  RS2                  :1;
            __IO  uint32_t  TS0                  :1;
            __IO  uint32_t  TS1                  :1;
            __IO  uint32_t  TS2                  :1;
            __IO  uint32_t  EB0                  :1;
            __IO  uint32_t  EB1                  :1;
            __IO  uint32_t  EB2                  :1;
            __IO  uint32_t  RESERVED3            :6;
        };
    };
} stc_ethernet_mac_sr_field_t;

typedef struct stc_ethernet_mac_omr_field
{
    union {
        struct {
            __IO  uint32_t  RESERVED0            :1;
            __IO  uint32_t  SR                   :1;
            __IO  uint32_t  OSF                  :1;
            __IO  uint32_t  RTC                  :2;
            __IO  uint32_t  RESERVED2            :1;
            __IO  uint32_t  FUF                  :1;
            __IO  uint32_t  FEF                  :1;
            __IO  uint32_t  RESERVED3            :5;
            __IO  uint32_t  ST                   :1;
            __IO  uint32_t  TTC                  :3;
            __IO  uint32_t  RESERVED5            :3;
            __IO  uint32_t  FTF                  :1;
            __IO  uint32_t  TSF                  :1;
            __IO  uint32_t  RESERVED6            :2;
            __IO  uint32_t  DFF                  :1;
            __IO  uint32_t  RSF                  :1;
            __IO  uint32_t  DT                   :1;
            __IO  uint32_t  RESERVED7            :5;
        };
        struct {
            __IO  uint32_t  RESERVED1            :3;
            __IO  uint32_t  RTC0                 :1;
            __IO  uint32_t  RTC1                 :1;
            __IO  uint32_t  RESERVED4            :9;
            __IO  uint32_t  TTC0                 :1;
            __IO  uint32_t  TTC1                 :1;
            __IO  uint32_t  TTC2                 :1;
            __IO  uint32_t  RESERVED8            :15;
        };
    };
} stc_ethernet_mac_omr_field_t;

typedef struct stc_ethernet_mac_ier_field
{
        __IO  uint32_t  TIE                      :1;
        __IO  uint32_t  TSE                      :1;
        __IO  uint32_t  TUE                      :1;
        __IO  uint32_t  TJE                      :1;
        __IO  uint32_t  OVE                      :1;
        __IO  uint32_t  UNE                      :1;
        __IO  uint32_t  RIE                      :1;
        __IO  uint32_t  RUE                      :1;
        __IO  uint32_t  RSE                      :1;
        __IO  uint32_t  RWE                      :1;
        __IO  uint32_t  ETE                      :1;
        __IO  uint32_t  RESERVED0                :2;
        __IO  uint32_t  FBE                      :1;
        __IO  uint32_t  ERE                      :1;
        __IO  uint32_t  AIE                      :1;
        __IO  uint32_t  NIE                      :1;
        __IO  uint32_t  RESERVED1                :15;
} stc_ethernet_mac_ier_field_t;

typedef struct stc_ethernet_mac_mfbocr_field
{
    union {
        struct {
            __IO  uint32_t  NMFH                 :16;
            __IO  uint32_t  ONMFH                :1;
            __IO  uint32_t  NMFF                 :11;
            __IO  uint32_t  ONMFF                :1;
            __IO  uint32_t  RESERVED1            :3;
        };
        struct {
            __IO  uint32_t  NMFH0                :1;
            __IO  uint32_t  NMFH1                :1;
            __IO  uint32_t  NMFH2                :1;
            __IO  uint32_t  NMFH3                :1;
            __IO  uint32_t  NMFH4                :1;
            __IO  uint32_t  NMFH5                :1;
            __IO  uint32_t  NMFH6                :1;
            __IO  uint32_t  NMFH7                :1;
            __IO  uint32_t  NMFH8                :1;
            __IO  uint32_t  NMFH9                :1;
            __IO  uint32_t  NMFH10               :1;
            __IO  uint32_t  NMFH11               :1;
            __IO  uint32_t  NMFH12               :1;
            __IO  uint32_t  NMFH13               :1;
            __IO  uint32_t  NMFH14               :1;
            __IO  uint32_t  NMFH15               :1;
            __IO  uint32_t  RESERVED0            :1;
            __IO  uint32_t  NMFF0                :1;
            __IO  uint32_t  NMFF1                :1;
            __IO  uint32_t  NMFF2                :1;
            __IO  uint32_t  NMFF3                :1;
            __IO  uint32_t  NMFF4                :1;
            __IO  uint32_t  NMFF5                :1;
            __IO  uint32_t  NMFF6                :1;
            __IO  uint32_t  NMFF7                :1;
            __IO  uint32_t  NMFF8                :1;
            __IO  uint32_t  NMFF9                :1;
            __IO  uint32_t  NMFF10               :1;
            __IO  uint32_t  RESERVED2            :4;
        };
    };
} stc_ethernet_mac_mfbocr_field_t;

typedef struct stc_ethernet_mac_riwtr_field
{
    union {
        struct {
            __IO  uint32_t  RIWT                 :8;
            __IO  uint32_t  RESERVED0            :24;
        };
        struct {
            __IO  uint32_t  RIWT0                :1;
            __IO  uint32_t  RIWT1                :1;
            __IO  uint32_t  RIWT2                :1;
            __IO  uint32_t  RIWT3                :1;
            __IO  uint32_t  RIWT4                :1;
            __IO  uint32_t  RIWT5                :1;
            __IO  uint32_t  RIWT6                :1;
            __IO  uint32_t  RIWT7                :1;
            __IO  uint32_t  RESERVED1            :24;
        };
    };
} stc_ethernet_mac_riwtr_field_t;

typedef struct stc_ethernet_mac_ahbsr_field
{
        __IO  uint32_t  AHBS                     :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_ethernet_mac_ahbsr_field_t;

typedef struct stc_ethernet_mac_chtdr_field
{
    union {
        struct {
            __IO  uint32_t  HTDAP                :32;
        };
        struct {
            __IO  uint32_t  HTDAP0               :1;
            __IO  uint32_t  HTDAP1               :1;
            __IO  uint32_t  HTDAP2               :1;
            __IO  uint32_t  HTDAP3               :1;
            __IO  uint32_t  HTDAP4               :1;
            __IO  uint32_t  HTDAP5               :1;
            __IO  uint32_t  HTDAP6               :1;
            __IO  uint32_t  HTDAP7               :1;
            __IO  uint32_t  HTDAP8               :1;
            __IO  uint32_t  HTDAP9               :1;
            __IO  uint32_t  HTDAP10              :1;
            __IO  uint32_t  HTDAP11              :1;
            __IO  uint32_t  HTDAP12              :1;
            __IO  uint32_t  HTDAP13              :1;
            __IO  uint32_t  HTDAP14              :1;
            __IO  uint32_t  HTDAP15              :1;
            __IO  uint32_t  HTDAP16              :1;
            __IO  uint32_t  HTDAP17              :1;
            __IO  uint32_t  HTDAP18              :1;
            __IO  uint32_t  HTDAP19              :1;
            __IO  uint32_t  HTDAP20              :1;
            __IO  uint32_t  HTDAP21              :1;
            __IO  uint32_t  HTDAP22              :1;
            __IO  uint32_t  HTDAP23              :1;
            __IO  uint32_t  HTDAP24              :1;
            __IO  uint32_t  HTDAP25              :1;
            __IO  uint32_t  HTDAP26              :1;
            __IO  uint32_t  HTDAP27              :1;
            __IO  uint32_t  HTDAP28              :1;
            __IO  uint32_t  HTDAP29              :1;
            __IO  uint32_t  HTDAP30              :1;
            __IO  uint32_t  HTDAP31              :1;
        };
    };
} stc_ethernet_mac_chtdr_field_t;

typedef struct stc_ethernet_mac_chrdr_field
{
    union {
        struct {
            __IO  uint32_t  HRDAP                :32;
        };
        struct {
            __IO  uint32_t  HRDAP0               :1;
            __IO  uint32_t  HRDAP1               :1;
            __IO  uint32_t  HRDAP2               :1;
            __IO  uint32_t  HRDAP3               :1;
            __IO  uint32_t  HRDAP4               :1;
            __IO  uint32_t  HRDAP5               :1;
            __IO  uint32_t  HRDAP6               :1;
            __IO  uint32_t  HRDAP7               :1;
            __IO  uint32_t  HRDAP8               :1;
            __IO  uint32_t  HRDAP9               :1;
            __IO  uint32_t  HRDAP10              :1;
            __IO  uint32_t  HRDAP11              :1;
            __IO  uint32_t  HRDAP12              :1;
            __IO  uint32_t  HRDAP13              :1;
            __IO  uint32_t  HRDAP14              :1;
            __IO  uint32_t  HRDAP15              :1;
            __IO  uint32_t  HRDAP16              :1;
            __IO  uint32_t  HRDAP17              :1;
            __IO  uint32_t  HRDAP18              :1;
            __IO  uint32_t  HRDAP19              :1;
            __IO  uint32_t  HRDAP20              :1;
            __IO  uint32_t  HRDAP21              :1;
            __IO  uint32_t  HRDAP22              :1;
            __IO  uint32_t  HRDAP23              :1;
            __IO  uint32_t  HRDAP24              :1;
            __IO  uint32_t  HRDAP25              :1;
            __IO  uint32_t  HRDAP26              :1;
            __IO  uint32_t  HRDAP27              :1;
            __IO  uint32_t  HRDAP28              :1;
            __IO  uint32_t  HRDAP29              :1;
            __IO  uint32_t  HRDAP30              :1;
            __IO  uint32_t  HRDAP31              :1;
        };
    };
} stc_ethernet_mac_chrdr_field_t;

typedef struct stc_ethernet_mac_chtbar_field
{
    union {
        struct {
            __IO  uint32_t  HTBAR                :32;
        };
        struct {
            __IO  uint32_t  HTBAR0               :1;
            __IO  uint32_t  HTBAR1               :1;
            __IO  uint32_t  HTBAR2               :1;
            __IO  uint32_t  HTBAR3               :1;
            __IO  uint32_t  HTBAR4               :1;
            __IO  uint32_t  HTBAR5               :1;
            __IO  uint32_t  HTBAR6               :1;
            __IO  uint32_t  HTBAR7               :1;
            __IO  uint32_t  HTBAR8               :1;
            __IO  uint32_t  HTBAR9               :1;
            __IO  uint32_t  HTBAR10              :1;
            __IO  uint32_t  HTBAR11              :1;
            __IO  uint32_t  HTBAR12              :1;
            __IO  uint32_t  HTBAR13              :1;
            __IO  uint32_t  HTBAR14              :1;
            __IO  uint32_t  HTBAR15              :1;
            __IO  uint32_t  HTBAR16              :1;
            __IO  uint32_t  HTBAR17              :1;
            __IO  uint32_t  HTBAR18              :1;
            __IO  uint32_t  HTBAR19              :1;
            __IO  uint32_t  HTBAR20              :1;
            __IO  uint32_t  HTBAR21              :1;
            __IO  uint32_t  HTBAR22              :1;
            __IO  uint32_t  HTBAR23              :1;
            __IO  uint32_t  HTBAR24              :1;
            __IO  uint32_t  HTBAR25              :1;
            __IO  uint32_t  HTBAR26              :1;
            __IO  uint32_t  HTBAR27              :1;
            __IO  uint32_t  HTBAR28              :1;
            __IO  uint32_t  HTBAR29              :1;
            __IO  uint32_t  HTBAR30              :1;
            __IO  uint32_t  HTBAR31              :1;
        };
    };
} stc_ethernet_mac_chtbar_field_t;

typedef struct stc_ethernet_mac_chrbar_field
{
    union {
        struct {
            __IO  uint32_t  HRBAR                :32;
        };
        struct {
            __IO  uint32_t  HRBAR0               :1;
            __IO  uint32_t  HRBAR1               :1;
            __IO  uint32_t  HRBAR2               :1;
            __IO  uint32_t  HRBAR3               :1;
            __IO  uint32_t  HRBAR4               :1;
            __IO  uint32_t  HRBAR5               :1;
            __IO  uint32_t  HRBAR6               :1;
            __IO  uint32_t  HRBAR7               :1;
            __IO  uint32_t  HRBAR8               :1;
            __IO  uint32_t  HRBAR9               :1;
            __IO  uint32_t  HRBAR10              :1;
            __IO  uint32_t  HRBAR11              :1;
            __IO  uint32_t  HRBAR12              :1;
            __IO  uint32_t  HRBAR13              :1;
            __IO  uint32_t  HRBAR14              :1;
            __IO  uint32_t  HRBAR15              :1;
            __IO  uint32_t  HRBAR16              :1;
            __IO  uint32_t  HRBAR17              :1;
            __IO  uint32_t  HRBAR18              :1;
            __IO  uint32_t  HRBAR19              :1;
            __IO  uint32_t  HRBAR20              :1;
            __IO  uint32_t  HRBAR21              :1;
            __IO  uint32_t  HRBAR22              :1;
            __IO  uint32_t  HRBAR23              :1;
            __IO  uint32_t  HRBAR24              :1;
            __IO  uint32_t  HRBAR25              :1;
            __IO  uint32_t  HRBAR26              :1;
            __IO  uint32_t  HRBAR27              :1;
            __IO  uint32_t  HRBAR28              :1;
            __IO  uint32_t  HRBAR29              :1;
            __IO  uint32_t  HRBAR30              :1;
            __IO  uint32_t  HRBAR31              :1;
        };
    };
} stc_ethernet_mac_chrbar_field_t;

/*******************************************************************************
* EXBUS_MODULE
*******************************************************************************/
typedef struct stc_exbus_mode0_field
{
    union {
        struct {
            __IO  uint32_t  WDTH                 :2;
            __IO  uint32_t  RBMON                :1;
            __IO  uint32_t  WEOFF                :1;
            __IO  uint32_t  NAND                 :1;
            __IO  uint32_t  PAGE                 :1;
            __IO  uint32_t  RDY                  :1;
            __IO  uint32_t  SHRTDOUT             :1;
            __IO  uint32_t  MPXMODE              :1;
            __IO  uint32_t  ALEINV               :1;
            __IO  uint32_t  RESERVED0            :1;
            __IO  uint32_t  MPXDOFF              :1;
            __IO  uint32_t  MPXCSOF              :1;
            __IO  uint32_t  MOEXEUP              :1;
            __IO  uint32_t  RESERVED1            :18;
        };
        struct {
            __IO  uint32_t  WDTH0                :1;
            __IO  uint32_t  WDTH1                :1;
            __IO  uint32_t  RESERVED2            :30;
        };
    };
} stc_exbus_mode0_field_t;

typedef struct stc_exbus_mode1_field
{
    union {
        struct {
            __IO  uint32_t  WDTH                 :2;
            __IO  uint32_t  RBMON                :1;
            __IO  uint32_t  WEOFF                :1;
            __IO  uint32_t  NAND                 :1;
            __IO  uint32_t  PAGE                 :1;
            __IO  uint32_t  RDY                  :1;
            __IO  uint32_t  SHRTDOUT             :1;
            __IO  uint32_t  MPXMODE              :1;
            __IO  uint32_t  ALEINV               :1;
            __IO  uint32_t  RESERVED0            :1;
            __IO  uint32_t  MPXDOFF              :1;
            __IO  uint32_t  MPXCSOF              :1;
            __IO  uint32_t  MOEXEUP              :1;
            __IO  uint32_t  RESERVED1            :18;
        };
        struct {
            __IO  uint32_t  WDTH0                :1;
            __IO  uint32_t  WDTH1                :1;
            __IO  uint32_t  RESERVED2            :30;
        };
    };
} stc_exbus_mode1_field_t;

typedef struct stc_exbus_mode2_field
{
    union {
        struct {
            __IO  uint32_t  WDTH                 :2;
            __IO  uint32_t  RBMON                :1;
            __IO  uint32_t  WEOFF                :1;
            __IO  uint32_t  NAND                 :1;
            __IO  uint32_t  PAGE                 :1;
            __IO  uint32_t  RDY                  :1;
            __IO  uint32_t  SHRTDOUT             :1;
            __IO  uint32_t  MPXMODE              :1;
            __IO  uint32_t  ALEINV               :1;
            __IO  uint32_t  RESERVED0            :1;
            __IO  uint32_t  MPXDOFF              :1;
            __IO  uint32_t  MPXCSOF              :1;
            __IO  uint32_t  MOEXEUP              :1;
            __IO  uint32_t  RESERVED1            :18;
        };
        struct {
            __IO  uint32_t  WDTH0                :1;
            __IO  uint32_t  WDTH1                :1;
            __IO  uint32_t  RESERVED2            :30;
        };
    };
} stc_exbus_mode2_field_t;

typedef struct stc_exbus_mode3_field
{
    union {
        struct {
            __IO  uint32_t  WDTH                 :2;
            __IO  uint32_t  RBMON                :1;
            __IO  uint32_t  WEOFF                :1;
            __IO  uint32_t  NAND                 :1;
            __IO  uint32_t  PAGE                 :1;
            __IO  uint32_t  RDY                  :1;
            __IO  uint32_t  SHRTDOUT             :1;
            __IO  uint32_t  MPXMODE              :1;
            __IO  uint32_t  ALEINV               :1;
            __IO  uint32_t  RESERVED0            :1;
            __IO  uint32_t  MPXDOFF              :1;
            __IO  uint32_t  MPXCSOF              :1;
            __IO  uint32_t  MOEXEUP              :1;
            __IO  uint32_t  RESERVED1            :18;
        };
        struct {
            __IO  uint32_t  WDTH0                :1;
            __IO  uint32_t  WDTH1                :1;
            __IO  uint32_t  RESERVED2            :30;
        };
    };
} stc_exbus_mode3_field_t;

typedef struct stc_exbus_mode4_field
{
    union {
        struct {
            __IO  uint32_t  WDTH                 :2;
            __IO  uint32_t  RBMON                :1;
            __IO  uint32_t  WEOFF                :1;
            __IO  uint32_t  NAND                 :1;
            __IO  uint32_t  PAGE                 :1;
            __IO  uint32_t  RDY                  :1;
            __IO  uint32_t  SHRTDOUT             :1;
            __IO  uint32_t  MPXMODE              :1;
            __IO  uint32_t  ALEINV               :1;
            __IO  uint32_t  RESERVED0            :1;
            __IO  uint32_t  MPXDOFF              :1;
            __IO  uint32_t  MPXCSOF              :1;
            __IO  uint32_t  MOEXEUP              :1;
            __IO  uint32_t  RESERVED1            :18;
        };
        struct {
            __IO  uint32_t  WDTH0                :1;
            __IO  uint32_t  WDTH1                :1;
            __IO  uint32_t  RESERVED2            :30;
        };
    };
} stc_exbus_mode4_field_t;

typedef struct stc_exbus_mode5_field
{
    union {
        struct {
            __IO  uint32_t  WDTH                 :2;
            __IO  uint32_t  RBMON                :1;
            __IO  uint32_t  WEOFF                :1;
            __IO  uint32_t  NAND                 :1;
            __IO  uint32_t  PAGE                 :1;
            __IO  uint32_t  RDY                  :1;
            __IO  uint32_t  SHRTDOUT             :1;
            __IO  uint32_t  MPXMODE              :1;
            __IO  uint32_t  ALEINV               :1;
            __IO  uint32_t  RESERVED0            :1;
            __IO  uint32_t  MPXDOFF              :1;
            __IO  uint32_t  MPXCSOF              :1;
            __IO  uint32_t  MOEXEUP              :1;
            __IO  uint32_t  RESERVED1            :18;
        };
        struct {
            __IO  uint32_t  WDTH0                :1;
            __IO  uint32_t  WDTH1                :1;
            __IO  uint32_t  RESERVED2            :30;
        };
    };
} stc_exbus_mode5_field_t;

typedef struct stc_exbus_mode6_field
{
    union {
        struct {
            __IO  uint32_t  WDTH                 :2;
            __IO  uint32_t  RBMON                :1;
            __IO  uint32_t  WEOFF                :1;
            __IO  uint32_t  NAND                 :1;
            __IO  uint32_t  PAGE                 :1;
            __IO  uint32_t  RDY                  :1;
            __IO  uint32_t  SHRTDOUT             :1;
            __IO  uint32_t  MPXMODE              :1;
            __IO  uint32_t  ALEINV               :1;
            __IO  uint32_t  RESERVED0            :1;
            __IO  uint32_t  MPXDOFF              :1;
            __IO  uint32_t  MPXCSOF              :1;
            __IO  uint32_t  MOEXEUP              :1;
            __IO  uint32_t  RESERVED1            :18;
        };
        struct {
            __IO  uint32_t  WDTH0                :1;
            __IO  uint32_t  WDTH1                :1;
            __IO  uint32_t  RESERVED2            :30;
        };
    };
} stc_exbus_mode6_field_t;

typedef struct stc_exbus_mode7_field
{
    union {
        struct {
            __IO  uint32_t  WDTH                 :2;
            __IO  uint32_t  RBMON                :1;
            __IO  uint32_t  WEOFF                :1;
            __IO  uint32_t  NAND                 :1;
            __IO  uint32_t  PAGE                 :1;
            __IO  uint32_t  RDY                  :1;
            __IO  uint32_t  SHRTDOUT             :1;
            __IO  uint32_t  MPXMODE              :1;
            __IO  uint32_t  ALEINV               :1;
            __IO  uint32_t  RESERVED0            :1;
            __IO  uint32_t  MPXDOFF              :1;
            __IO  uint32_t  MPXCSOF              :1;
            __IO  uint32_t  MOEXEUP              :1;
            __IO  uint32_t  RESERVED1            :18;
        };
        struct {
            __IO  uint32_t  WDTH0                :1;
            __IO  uint32_t  WDTH1                :1;
            __IO  uint32_t  RESERVED2            :30;
        };
    };
} stc_exbus_mode7_field_t;

typedef struct stc_exbus_tim0_field
{
    union {
        struct {
            __IO  uint32_t  RACC                 :4;
            __IO  uint32_t  RADC                 :4;
            __IO  uint32_t  FRADC                :4;
            __IO  uint32_t  RIDLC                :4;
            __IO  uint32_t  WACC                 :4;
            __IO  uint32_t  WADC                 :4;
            __IO  uint32_t  WWEC                 :4;
            __IO  uint32_t  WIDLC                :4;
        };
        struct {
            __IO  uint32_t  RACC0                :1;
            __IO  uint32_t  RACC1                :1;
            __IO  uint32_t  RACC2                :1;
            __IO  uint32_t  RACC3                :1;
            __IO  uint32_t  RADC0                :1;
            __IO  uint32_t  RADC1                :1;
            __IO  uint32_t  RADC2                :1;
            __IO  uint32_t  RADC3                :1;
            __IO  uint32_t  FRADC0               :1;
            __IO  uint32_t  FRADC1               :1;
            __IO  uint32_t  FRADC2               :1;
            __IO  uint32_t  FRADC3               :1;
            __IO  uint32_t  RIDLC0               :1;
            __IO  uint32_t  RIDLC1               :1;
            __IO  uint32_t  RIDLC2               :1;
            __IO  uint32_t  RIDLC3               :1;
            __IO  uint32_t  WACC0                :1;
            __IO  uint32_t  WACC1                :1;
            __IO  uint32_t  WACC2                :1;
            __IO  uint32_t  WACC3                :1;
            __IO  uint32_t  WADC0                :1;
            __IO  uint32_t  WADC1                :1;
            __IO  uint32_t  WADC2                :1;
            __IO  uint32_t  WADC3                :1;
            __IO  uint32_t  WWEC0                :1;
            __IO  uint32_t  WWEC1                :1;
            __IO  uint32_t  WWEC2                :1;
            __IO  uint32_t  WWEC3                :1;
            __IO  uint32_t  WIDLC0               :1;
            __IO  uint32_t  WIDLC1               :1;
            __IO  uint32_t  WIDLC2               :1;
            __IO  uint32_t  WIDLC3               :1;
        };
    };
} stc_exbus_tim0_field_t;

typedef struct stc_exbus_tim1_field
{
    union {
        struct {
            __IO  uint32_t  RACC                 :4;
            __IO  uint32_t  RADC                 :4;
            __IO  uint32_t  FRADC                :4;
            __IO  uint32_t  RIDLC                :4;
            __IO  uint32_t  WACC                 :4;
            __IO  uint32_t  WADC                 :4;
            __IO  uint32_t  WWEC                 :4;
            __IO  uint32_t  WIDLC                :4;
        };
        struct {
            __IO  uint32_t  RACC0                :1;
            __IO  uint32_t  RACC1                :1;
            __IO  uint32_t  RACC2                :1;
            __IO  uint32_t  RACC3                :1;
            __IO  uint32_t  RADC0                :1;
            __IO  uint32_t  RADC1                :1;
            __IO  uint32_t  RADC2                :1;
            __IO  uint32_t  RADC3                :1;
            __IO  uint32_t  FRADC0               :1;
            __IO  uint32_t  FRADC1               :1;
            __IO  uint32_t  FRADC2               :1;
            __IO  uint32_t  FRADC3               :1;
            __IO  uint32_t  RIDLC0               :1;
            __IO  uint32_t  RIDLC1               :1;
            __IO  uint32_t  RIDLC2               :1;
            __IO  uint32_t  RIDLC3               :1;
            __IO  uint32_t  WACC0                :1;
            __IO  uint32_t  WACC1                :1;
            __IO  uint32_t  WACC2                :1;
            __IO  uint32_t  WACC3                :1;
            __IO  uint32_t  WADC0                :1;
            __IO  uint32_t  WADC1                :1;
            __IO  uint32_t  WADC2                :1;
            __IO  uint32_t  WADC3                :1;
            __IO  uint32_t  WWEC0                :1;
            __IO  uint32_t  WWEC1                :1;
            __IO  uint32_t  WWEC2                :1;
            __IO  uint32_t  WWEC3                :1;
            __IO  uint32_t  WIDLC0               :1;
            __IO  uint32_t  WIDLC1               :1;
            __IO  uint32_t  WIDLC2               :1;
            __IO  uint32_t  WIDLC3               :1;
        };
    };
} stc_exbus_tim1_field_t;

typedef struct stc_exbus_tim2_field
{
    union {
        struct {
            __IO  uint32_t  RACC                 :4;
            __IO  uint32_t  RADC                 :4;
            __IO  uint32_t  FRADC                :4;
            __IO  uint32_t  RIDLC                :4;
            __IO  uint32_t  WACC                 :4;
            __IO  uint32_t  WADC                 :4;
            __IO  uint32_t  WWEC                 :4;
            __IO  uint32_t  WIDLC                :4;
        };
        struct {
            __IO  uint32_t  RACC0                :1;
            __IO  uint32_t  RACC1                :1;
            __IO  uint32_t  RACC2                :1;
            __IO  uint32_t  RACC3                :1;
            __IO  uint32_t  RADC0                :1;
            __IO  uint32_t  RADC1                :1;
            __IO  uint32_t  RADC2                :1;
            __IO  uint32_t  RADC3                :1;
            __IO  uint32_t  FRADC0               :1;
            __IO  uint32_t  FRADC1               :1;
            __IO  uint32_t  FRADC2               :1;
            __IO  uint32_t  FRADC3               :1;
            __IO  uint32_t  RIDLC0               :1;
            __IO  uint32_t  RIDLC1               :1;
            __IO  uint32_t  RIDLC2               :1;
            __IO  uint32_t  RIDLC3               :1;
            __IO  uint32_t  WACC0                :1;
            __IO  uint32_t  WACC1                :1;
            __IO  uint32_t  WACC2                :1;
            __IO  uint32_t  WACC3                :1;
            __IO  uint32_t  WADC0                :1;
            __IO  uint32_t  WADC1                :1;
            __IO  uint32_t  WADC2                :1;
            __IO  uint32_t  WADC3                :1;
            __IO  uint32_t  WWEC0                :1;
            __IO  uint32_t  WWEC1                :1;
            __IO  uint32_t  WWEC2                :1;
            __IO  uint32_t  WWEC3                :1;
            __IO  uint32_t  WIDLC0               :1;
            __IO  uint32_t  WIDLC1               :1;
            __IO  uint32_t  WIDLC2               :1;
            __IO  uint32_t  WIDLC3               :1;
        };
    };
} stc_exbus_tim2_field_t;

typedef struct stc_exbus_tim3_field
{
    union {
        struct {
            __IO  uint32_t  RACC                 :4;
            __IO  uint32_t  RADC                 :4;
            __IO  uint32_t  FRADC                :4;
            __IO  uint32_t  RIDLC                :4;
            __IO  uint32_t  WACC                 :4;
            __IO  uint32_t  WADC                 :4;
            __IO  uint32_t  WWEC                 :4;
            __IO  uint32_t  WIDLC                :4;
        };
        struct {
            __IO  uint32_t  RACC0                :1;
            __IO  uint32_t  RACC1                :1;
            __IO  uint32_t  RACC2                :1;
            __IO  uint32_t  RACC3                :1;
            __IO  uint32_t  RADC0                :1;
            __IO  uint32_t  RADC1                :1;
            __IO  uint32_t  RADC2                :1;
            __IO  uint32_t  RADC3                :1;
            __IO  uint32_t  FRADC0               :1;
            __IO  uint32_t  FRADC1               :1;
            __IO  uint32_t  FRADC2               :1;
            __IO  uint32_t  FRADC3               :1;
            __IO  uint32_t  RIDLC0               :1;
            __IO  uint32_t  RIDLC1               :1;
            __IO  uint32_t  RIDLC2               :1;
            __IO  uint32_t  RIDLC3               :1;
            __IO  uint32_t  WACC0                :1;
            __IO  uint32_t  WACC1                :1;
            __IO  uint32_t  WACC2                :1;
            __IO  uint32_t  WACC3                :1;
            __IO  uint32_t  WADC0                :1;
            __IO  uint32_t  WADC1                :1;
            __IO  uint32_t  WADC2                :1;
            __IO  uint32_t  WADC3                :1;
            __IO  uint32_t  WWEC0                :1;
            __IO  uint32_t  WWEC1                :1;
            __IO  uint32_t  WWEC2                :1;
            __IO  uint32_t  WWEC3                :1;
            __IO  uint32_t  WIDLC0               :1;
            __IO  uint32_t  WIDLC1               :1;
            __IO  uint32_t  WIDLC2               :1;
            __IO  uint32_t  WIDLC3               :1;
        };
    };
} stc_exbus_tim3_field_t;

typedef struct stc_exbus_tim4_field
{
    union {
        struct {
            __IO  uint32_t  RACC                 :4;
            __IO  uint32_t  RADC                 :4;
            __IO  uint32_t  FRADC                :4;
            __IO  uint32_t  RIDLC                :4;
            __IO  uint32_t  WACC                 :4;
            __IO  uint32_t  WADC                 :4;
            __IO  uint32_t  WWEC                 :4;
            __IO  uint32_t  WIDLC                :4;
        };
        struct {
            __IO  uint32_t  RACC0                :1;
            __IO  uint32_t  RACC1                :1;
            __IO  uint32_t  RACC2                :1;
            __IO  uint32_t  RACC3                :1;
            __IO  uint32_t  RADC0                :1;
            __IO  uint32_t  RADC1                :1;
            __IO  uint32_t  RADC2                :1;
            __IO  uint32_t  RADC3                :1;
            __IO  uint32_t  FRADC0               :1;
            __IO  uint32_t  FRADC1               :1;
            __IO  uint32_t  FRADC2               :1;
            __IO  uint32_t  FRADC3               :1;
            __IO  uint32_t  RIDLC0               :1;
            __IO  uint32_t  RIDLC1               :1;
            __IO  uint32_t  RIDLC2               :1;
            __IO  uint32_t  RIDLC3               :1;
            __IO  uint32_t  WACC0                :1;
            __IO  uint32_t  WACC1                :1;
            __IO  uint32_t  WACC2                :1;
            __IO  uint32_t  WACC3                :1;
            __IO  uint32_t  WADC0                :1;
            __IO  uint32_t  WADC1                :1;
            __IO  uint32_t  WADC2                :1;
            __IO  uint32_t  WADC3                :1;
            __IO  uint32_t  WWEC0                :1;
            __IO  uint32_t  WWEC1                :1;
            __IO  uint32_t  WWEC2                :1;
            __IO  uint32_t  WWEC3                :1;
            __IO  uint32_t  WIDLC0               :1;
            __IO  uint32_t  WIDLC1               :1;
            __IO  uint32_t  WIDLC2               :1;
            __IO  uint32_t  WIDLC3               :1;
        };
    };
} stc_exbus_tim4_field_t;

typedef struct stc_exbus_tim5_field
{
    union {
        struct {
            __IO  uint32_t  RACC                 :4;
            __IO  uint32_t  RADC                 :4;
            __IO  uint32_t  FRADC                :4;
            __IO  uint32_t  RIDLC                :4;
            __IO  uint32_t  WACC                 :4;
            __IO  uint32_t  WADC                 :4;
            __IO  uint32_t  WWEC                 :4;
            __IO  uint32_t  WIDLC                :4;
        };
        struct {
            __IO  uint32_t  RACC0                :1;
            __IO  uint32_t  RACC1                :1;
            __IO  uint32_t  RACC2                :1;
            __IO  uint32_t  RACC3                :1;
            __IO  uint32_t  RADC0                :1;
            __IO  uint32_t  RADC1                :1;
            __IO  uint32_t  RADC2                :1;
            __IO  uint32_t  RADC3                :1;
            __IO  uint32_t  FRADC0               :1;
            __IO  uint32_t  FRADC1               :1;
            __IO  uint32_t  FRADC2               :1;
            __IO  uint32_t  FRADC3               :1;
            __IO  uint32_t  RIDLC0               :1;
            __IO  uint32_t  RIDLC1               :1;
            __IO  uint32_t  RIDLC2               :1;
            __IO  uint32_t  RIDLC3               :1;
            __IO  uint32_t  WACC0                :1;
            __IO  uint32_t  WACC1                :1;
            __IO  uint32_t  WACC2                :1;
            __IO  uint32_t  WACC3                :1;
            __IO  uint32_t  WADC0                :1;
            __IO  uint32_t  WADC1                :1;
            __IO  uint32_t  WADC2                :1;
            __IO  uint32_t  WADC3                :1;
            __IO  uint32_t  WWEC0                :1;
            __IO  uint32_t  WWEC1                :1;
            __IO  uint32_t  WWEC2                :1;
            __IO  uint32_t  WWEC3                :1;
            __IO  uint32_t  WIDLC0               :1;
            __IO  uint32_t  WIDLC1               :1;
            __IO  uint32_t  WIDLC2               :1;
            __IO  uint32_t  WIDLC3               :1;
        };
    };
} stc_exbus_tim5_field_t;

typedef struct stc_exbus_tim6_field
{
    union {
        struct {
            __IO  uint32_t  RACC                 :4;
            __IO  uint32_t  RADC                 :4;
            __IO  uint32_t  FRADC                :4;
            __IO  uint32_t  RIDLC                :4;
            __IO  uint32_t  WACC                 :4;
            __IO  uint32_t  WADC                 :4;
            __IO  uint32_t  WWEC                 :4;
            __IO  uint32_t  WIDLC                :4;
        };
        struct {
            __IO  uint32_t  RACC0                :1;
            __IO  uint32_t  RACC1                :1;
            __IO  uint32_t  RACC2                :1;
            __IO  uint32_t  RACC3                :1;
            __IO  uint32_t  RADC0                :1;
            __IO  uint32_t  RADC1                :1;
            __IO  uint32_t  RADC2                :1;
            __IO  uint32_t  RADC3                :1;
            __IO  uint32_t  FRADC0               :1;
            __IO  uint32_t  FRADC1               :1;
            __IO  uint32_t  FRADC2               :1;
            __IO  uint32_t  FRADC3               :1;
            __IO  uint32_t  RIDLC0               :1;
            __IO  uint32_t  RIDLC1               :1;
            __IO  uint32_t  RIDLC2               :1;
            __IO  uint32_t  RIDLC3               :1;
            __IO  uint32_t  WACC0                :1;
            __IO  uint32_t  WACC1                :1;
            __IO  uint32_t  WACC2                :1;
            __IO  uint32_t  WACC3                :1;
            __IO  uint32_t  WADC0                :1;
            __IO  uint32_t  WADC1                :1;
            __IO  uint32_t  WADC2                :1;
            __IO  uint32_t  WADC3                :1;
            __IO  uint32_t  WWEC0                :1;
            __IO  uint32_t  WWEC1                :1;
            __IO  uint32_t  WWEC2                :1;
            __IO  uint32_t  WWEC3                :1;
            __IO  uint32_t  WIDLC0               :1;
            __IO  uint32_t  WIDLC1               :1;
            __IO  uint32_t  WIDLC2               :1;
            __IO  uint32_t  WIDLC3               :1;
        };
    };
} stc_exbus_tim6_field_t;

typedef struct stc_exbus_tim7_field
{
    union {
        struct {
            __IO  uint32_t  RACC                 :4;
            __IO  uint32_t  RADC                 :4;
            __IO  uint32_t  FRADC                :4;
            __IO  uint32_t  RIDLC                :4;
            __IO  uint32_t  WACC                 :4;
            __IO  uint32_t  WADC                 :4;
            __IO  uint32_t  WWEC                 :4;
            __IO  uint32_t  WIDLC                :4;
        };
        struct {
            __IO  uint32_t  RACC0                :1;
            __IO  uint32_t  RACC1                :1;
            __IO  uint32_t  RACC2                :1;
            __IO  uint32_t  RACC3                :1;
            __IO  uint32_t  RADC0                :1;
            __IO  uint32_t  RADC1                :1;
            __IO  uint32_t  RADC2                :1;
            __IO  uint32_t  RADC3                :1;
            __IO  uint32_t  FRADC0               :1;
            __IO  uint32_t  FRADC1               :1;
            __IO  uint32_t  FRADC2               :1;
            __IO  uint32_t  FRADC3               :1;
            __IO  uint32_t  RIDLC0               :1;
            __IO  uint32_t  RIDLC1               :1;
            __IO  uint32_t  RIDLC2               :1;
            __IO  uint32_t  RIDLC3               :1;
            __IO  uint32_t  WACC0                :1;
            __IO  uint32_t  WACC1                :1;
            __IO  uint32_t  WACC2                :1;
            __IO  uint32_t  WACC3                :1;
            __IO  uint32_t  WADC0                :1;
            __IO  uint32_t  WADC1                :1;
            __IO  uint32_t  WADC2                :1;
            __IO  uint32_t  WADC3                :1;
            __IO  uint32_t  WWEC0                :1;
            __IO  uint32_t  WWEC1                :1;
            __IO  uint32_t  WWEC2                :1;
            __IO  uint32_t  WWEC3                :1;
            __IO  uint32_t  WIDLC0               :1;
            __IO  uint32_t  WIDLC1               :1;
            __IO  uint32_t  WIDLC2               :1;
            __IO  uint32_t  WIDLC3               :1;
        };
    };
} stc_exbus_tim7_field_t;

typedef struct stc_exbus_area0_field
{
    union {
        struct {
            __IO  uint32_t  ADDR                 :8;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MASK                 :7;
            __IO  uint32_t  RESERVED2            :9;
        };
        struct {
            __IO  uint32_t  ADDR0                :1;
            __IO  uint32_t  ADDR1                :1;
            __IO  uint32_t  ADDR2                :1;
            __IO  uint32_t  ADDR3                :1;
            __IO  uint32_t  ADDR4                :1;
            __IO  uint32_t  ADDR5                :1;
            __IO  uint32_t  ADDR6                :1;
            __IO  uint32_t  ADDR7                :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MASK0                :1;
            __IO  uint32_t  MASK1                :1;
            __IO  uint32_t  MASK2                :1;
            __IO  uint32_t  MASK3                :1;
            __IO  uint32_t  MASK4                :1;
            __IO  uint32_t  MASK5                :1;
            __IO  uint32_t  MASK6                :1;
            __IO  uint32_t  RESERVED3            :9;
        };
    };
} stc_exbus_area0_field_t;

typedef struct stc_exbus_area1_field
{
    union {
        struct {
            __IO  uint32_t  ADDR                 :8;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MASK                 :7;
            __IO  uint32_t  RESERVED2            :9;
        };
        struct {
            __IO  uint32_t  ADDR0                :1;
            __IO  uint32_t  ADDR1                :1;
            __IO  uint32_t  ADDR2                :1;
            __IO  uint32_t  ADDR3                :1;
            __IO  uint32_t  ADDR4                :1;
            __IO  uint32_t  ADDR5                :1;
            __IO  uint32_t  ADDR6                :1;
            __IO  uint32_t  ADDR7                :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MASK0                :1;
            __IO  uint32_t  MASK1                :1;
            __IO  uint32_t  MASK2                :1;
            __IO  uint32_t  MASK3                :1;
            __IO  uint32_t  MASK4                :1;
            __IO  uint32_t  MASK5                :1;
            __IO  uint32_t  MASK6                :1;
            __IO  uint32_t  RESERVED3            :9;
        };
    };
} stc_exbus_area1_field_t;

typedef struct stc_exbus_area2_field
{
    union {
        struct {
            __IO  uint32_t  ADDR                 :8;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MASK                 :7;
            __IO  uint32_t  RESERVED2            :9;
        };
        struct {
            __IO  uint32_t  ADDR0                :1;
            __IO  uint32_t  ADDR1                :1;
            __IO  uint32_t  ADDR2                :1;
            __IO  uint32_t  ADDR3                :1;
            __IO  uint32_t  ADDR4                :1;
            __IO  uint32_t  ADDR5                :1;
            __IO  uint32_t  ADDR6                :1;
            __IO  uint32_t  ADDR7                :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MASK0                :1;
            __IO  uint32_t  MASK1                :1;
            __IO  uint32_t  MASK2                :1;
            __IO  uint32_t  MASK3                :1;
            __IO  uint32_t  MASK4                :1;
            __IO  uint32_t  MASK5                :1;
            __IO  uint32_t  MASK6                :1;
            __IO  uint32_t  RESERVED3            :9;
        };
    };
} stc_exbus_area2_field_t;

typedef struct stc_exbus_area3_field
{
    union {
        struct {
            __IO  uint32_t  ADDR                 :8;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MASK                 :7;
            __IO  uint32_t  RESERVED2            :9;
        };
        struct {
            __IO  uint32_t  ADDR0                :1;
            __IO  uint32_t  ADDR1                :1;
            __IO  uint32_t  ADDR2                :1;
            __IO  uint32_t  ADDR3                :1;
            __IO  uint32_t  ADDR4                :1;
            __IO  uint32_t  ADDR5                :1;
            __IO  uint32_t  ADDR6                :1;
            __IO  uint32_t  ADDR7                :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MASK0                :1;
            __IO  uint32_t  MASK1                :1;
            __IO  uint32_t  MASK2                :1;
            __IO  uint32_t  MASK3                :1;
            __IO  uint32_t  MASK4                :1;
            __IO  uint32_t  MASK5                :1;
            __IO  uint32_t  MASK6                :1;
            __IO  uint32_t  RESERVED3            :9;
        };
    };
} stc_exbus_area3_field_t;

typedef struct stc_exbus_area4_field
{
    union {
        struct {
            __IO  uint32_t  ADDR                 :8;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MASK                 :7;
            __IO  uint32_t  RESERVED2            :9;
        };
        struct {
            __IO  uint32_t  ADDR0                :1;
            __IO  uint32_t  ADDR1                :1;
            __IO  uint32_t  ADDR2                :1;
            __IO  uint32_t  ADDR3                :1;
            __IO  uint32_t  ADDR4                :1;
            __IO  uint32_t  ADDR5                :1;
            __IO  uint32_t  ADDR6                :1;
            __IO  uint32_t  ADDR7                :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MASK0                :1;
            __IO  uint32_t  MASK1                :1;
            __IO  uint32_t  MASK2                :1;
            __IO  uint32_t  MASK3                :1;
            __IO  uint32_t  MASK4                :1;
            __IO  uint32_t  MASK5                :1;
            __IO  uint32_t  MASK6                :1;
            __IO  uint32_t  RESERVED3            :9;
        };
    };
} stc_exbus_area4_field_t;

typedef struct stc_exbus_area5_field
{
    union {
        struct {
            __IO  uint32_t  ADDR                 :8;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MASK                 :7;
            __IO  uint32_t  RESERVED2            :9;
        };
        struct {
            __IO  uint32_t  ADDR0                :1;
            __IO  uint32_t  ADDR1                :1;
            __IO  uint32_t  ADDR2                :1;
            __IO  uint32_t  ADDR3                :1;
            __IO  uint32_t  ADDR4                :1;
            __IO  uint32_t  ADDR5                :1;
            __IO  uint32_t  ADDR6                :1;
            __IO  uint32_t  ADDR7                :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MASK0                :1;
            __IO  uint32_t  MASK1                :1;
            __IO  uint32_t  MASK2                :1;
            __IO  uint32_t  MASK3                :1;
            __IO  uint32_t  MASK4                :1;
            __IO  uint32_t  MASK5                :1;
            __IO  uint32_t  MASK6                :1;
            __IO  uint32_t  RESERVED3            :9;
        };
    };
} stc_exbus_area5_field_t;

typedef struct stc_exbus_area6_field
{
    union {
        struct {
            __IO  uint32_t  ADDR                 :8;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MASK                 :7;
            __IO  uint32_t  RESERVED2            :9;
        };
        struct {
            __IO  uint32_t  ADDR0                :1;
            __IO  uint32_t  ADDR1                :1;
            __IO  uint32_t  ADDR2                :1;
            __IO  uint32_t  ADDR3                :1;
            __IO  uint32_t  ADDR4                :1;
            __IO  uint32_t  ADDR5                :1;
            __IO  uint32_t  ADDR6                :1;
            __IO  uint32_t  ADDR7                :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MASK0                :1;
            __IO  uint32_t  MASK1                :1;
            __IO  uint32_t  MASK2                :1;
            __IO  uint32_t  MASK3                :1;
            __IO  uint32_t  MASK4                :1;
            __IO  uint32_t  MASK5                :1;
            __IO  uint32_t  MASK6                :1;
            __IO  uint32_t  RESERVED3            :9;
        };
    };
} stc_exbus_area6_field_t;

typedef struct stc_exbus_area7_field
{
    union {
        struct {
            __IO  uint32_t  ADDR                 :8;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  MASK                 :7;
            __IO  uint32_t  RESERVED2            :9;
        };
        struct {
            __IO  uint32_t  ADDR0                :1;
            __IO  uint32_t  ADDR1                :1;
            __IO  uint32_t  ADDR2                :1;
            __IO  uint32_t  ADDR3                :1;
            __IO  uint32_t  ADDR4                :1;
            __IO  uint32_t  ADDR5                :1;
            __IO  uint32_t  ADDR6                :1;
            __IO  uint32_t  ADDR7                :1;
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  MASK0                :1;
            __IO  uint32_t  MASK1                :1;
            __IO  uint32_t  MASK2                :1;
            __IO  uint32_t  MASK3                :1;
            __IO  uint32_t  MASK4                :1;
            __IO  uint32_t  MASK5                :1;
            __IO  uint32_t  MASK6                :1;
            __IO  uint32_t  RESERVED3            :9;
        };
    };
} stc_exbus_area7_field_t;

typedef struct stc_exbus_atim0_field
{
    union {
        struct {
            __IO  uint32_t  ALC                  :4;
            __IO  uint32_t  ALES                 :4;
            __IO  uint32_t  ALEW                 :4;
            __IO  uint32_t  RESERVED0            :20;
        };
        struct {
            __IO  uint32_t  ALC0                 :1;
            __IO  uint32_t  ALC1                 :1;
            __IO  uint32_t  ALC2                 :1;
            __IO  uint32_t  ALC3                 :1;
            __IO  uint32_t  ALES0                :1;
            __IO  uint32_t  ALES1                :1;
            __IO  uint32_t  ALES2                :1;
            __IO  uint32_t  ALES3                :1;
            __IO  uint32_t  ALEW0                :1;
            __IO  uint32_t  ALEW1                :1;
            __IO  uint32_t  ALEW2                :1;
            __IO  uint32_t  ALEW3                :1;
            __IO  uint32_t  RESERVED1            :20;
        };
    };
} stc_exbus_atim0_field_t;

typedef struct stc_exbus_atim1_field
{
    union {
        struct {
            __IO  uint32_t  ALC                  :4;
            __IO  uint32_t  ALES                 :4;
            __IO  uint32_t  ALEW                 :4;
            __IO  uint32_t  RESERVED0            :20;
        };
        struct {
            __IO  uint32_t  ALC0                 :1;
            __IO  uint32_t  ALC1                 :1;
            __IO  uint32_t  ALC2                 :1;
            __IO  uint32_t  ALC3                 :1;
            __IO  uint32_t  ALES0                :1;
            __IO  uint32_t  ALES1                :1;
            __IO  uint32_t  ALES2                :1;
            __IO  uint32_t  ALES3                :1;
            __IO  uint32_t  ALEW0                :1;
            __IO  uint32_t  ALEW1                :1;
            __IO  uint32_t  ALEW2                :1;
            __IO  uint32_t  ALEW3                :1;
            __IO  uint32_t  RESERVED1            :20;
        };
    };
} stc_exbus_atim1_field_t;

typedef struct stc_exbus_atim2_field
{
    union {
        struct {
            __IO  uint32_t  ALC                  :4;
            __IO  uint32_t  ALES                 :4;
            __IO  uint32_t  ALEW                 :4;
            __IO  uint32_t  RESERVED0            :20;
        };
        struct {
            __IO  uint32_t  ALC0                 :1;
            __IO  uint32_t  ALC1                 :1;
            __IO  uint32_t  ALC2                 :1;
            __IO  uint32_t  ALC3                 :1;
            __IO  uint32_t  ALES0                :1;
            __IO  uint32_t  ALES1                :1;
            __IO  uint32_t  ALES2                :1;
            __IO  uint32_t  ALES3                :1;
            __IO  uint32_t  ALEW0                :1;
            __IO  uint32_t  ALEW1                :1;
            __IO  uint32_t  ALEW2                :1;
            __IO  uint32_t  ALEW3                :1;
            __IO  uint32_t  RESERVED1            :20;
        };
    };
} stc_exbus_atim2_field_t;

typedef struct stc_exbus_atim3_field
{
    union {
        struct {
            __IO  uint32_t  ALC                  :4;
            __IO  uint32_t  ALES                 :4;
            __IO  uint32_t  ALEW                 :4;
            __IO  uint32_t  RESERVED0            :20;
        };
        struct {
            __IO  uint32_t  ALC0                 :1;
            __IO  uint32_t  ALC1                 :1;
            __IO  uint32_t  ALC2                 :1;
            __IO  uint32_t  ALC3                 :1;
            __IO  uint32_t  ALES0                :1;
            __IO  uint32_t  ALES1                :1;
            __IO  uint32_t  ALES2                :1;
            __IO  uint32_t  ALES3                :1;
            __IO  uint32_t  ALEW0                :1;
            __IO  uint32_t  ALEW1                :1;
            __IO  uint32_t  ALEW2                :1;
            __IO  uint32_t  ALEW3                :1;
            __IO  uint32_t  RESERVED1            :20;
        };
    };
} stc_exbus_atim3_field_t;

typedef struct stc_exbus_atim4_field
{
    union {
        struct {
            __IO  uint32_t  ALC                  :4;
            __IO  uint32_t  ALES                 :4;
            __IO  uint32_t  ALEW                 :4;
            __IO  uint32_t  RESERVED0            :20;
        };
        struct {
            __IO  uint32_t  ALC0                 :1;
            __IO  uint32_t  ALC1                 :1;
            __IO  uint32_t  ALC2                 :1;
            __IO  uint32_t  ALC3                 :1;
            __IO  uint32_t  ALES0                :1;
            __IO  uint32_t  ALES1                :1;
            __IO  uint32_t  ALES2                :1;
            __IO  uint32_t  ALES3                :1;
            __IO  uint32_t  ALEW0                :1;
            __IO  uint32_t  ALEW1                :1;
            __IO  uint32_t  ALEW2                :1;
            __IO  uint32_t  ALEW3                :1;
            __IO  uint32_t  RESERVED1            :20;
        };
    };
} stc_exbus_atim4_field_t;

typedef struct stc_exbus_atim5_field
{
    union {
        struct {
            __IO  uint32_t  ALC                  :4;
            __IO  uint32_t  ALES                 :4;
            __IO  uint32_t  ALEW                 :4;
            __IO  uint32_t  RESERVED0            :20;
        };
        struct {
            __IO  uint32_t  ALC0                 :1;
            __IO  uint32_t  ALC1                 :1;
            __IO  uint32_t  ALC2                 :1;
            __IO  uint32_t  ALC3                 :1;
            __IO  uint32_t  ALES0                :1;
            __IO  uint32_t  ALES1                :1;
            __IO  uint32_t  ALES2                :1;
            __IO  uint32_t  ALES3                :1;
            __IO  uint32_t  ALEW0                :1;
            __IO  uint32_t  ALEW1                :1;
            __IO  uint32_t  ALEW2                :1;
            __IO  uint32_t  ALEW3                :1;
            __IO  uint32_t  RESERVED1            :20;
        };
    };
} stc_exbus_atim5_field_t;

typedef struct stc_exbus_atim6_field
{
    union {
        struct {
            __IO  uint32_t  ALC                  :4;
            __IO  uint32_t  ALES                 :4;
            __IO  uint32_t  ALEW                 :4;
            __IO  uint32_t  RESERVED0            :20;
        };
        struct {
            __IO  uint32_t  ALC0                 :1;
            __IO  uint32_t  ALC1                 :1;
            __IO  uint32_t  ALC2                 :1;
            __IO  uint32_t  ALC3                 :1;
            __IO  uint32_t  ALES0                :1;
            __IO  uint32_t  ALES1                :1;
            __IO  uint32_t  ALES2                :1;
            __IO  uint32_t  ALES3                :1;
            __IO  uint32_t  ALEW0                :1;
            __IO  uint32_t  ALEW1                :1;
            __IO  uint32_t  ALEW2                :1;
            __IO  uint32_t  ALEW3                :1;
            __IO  uint32_t  RESERVED1            :20;
        };
    };
} stc_exbus_atim6_field_t;

typedef struct stc_exbus_atim7_field
{
    union {
        struct {
            __IO  uint32_t  ALC                  :4;
            __IO  uint32_t  ALES                 :4;
            __IO  uint32_t  ALEW                 :4;
            __IO  uint32_t  RESERVED0            :20;
        };
        struct {
            __IO  uint32_t  ALC0                 :1;
            __IO  uint32_t  ALC1                 :1;
            __IO  uint32_t  ALC2                 :1;
            __IO  uint32_t  ALC3                 :1;
            __IO  uint32_t  ALES0                :1;
            __IO  uint32_t  ALES1                :1;
            __IO  uint32_t  ALES2                :1;
            __IO  uint32_t  ALES3                :1;
            __IO  uint32_t  ALEW0                :1;
            __IO  uint32_t  ALEW1                :1;
            __IO  uint32_t  ALEW2                :1;
            __IO  uint32_t  ALEW3                :1;
            __IO  uint32_t  RESERVED1            :20;
        };
    };
} stc_exbus_atim7_field_t;

typedef struct stc_exbus_sdmode_field
{
    union {
        struct {
            __IO  uint32_t  SDON                 :1;
            __IO  uint32_t  PDON                 :1;
            __IO  uint32_t  ROFF                 :1;
            __IO  uint32_t  RESERVED0            :1;
            __IO  uint32_t  CASEL                :2;
            __IO  uint32_t  RESERVED2            :2;
            __IO  uint32_t  RASEL                :4;
            __IO  uint32_t  BASEL                :4;
            __IO  uint32_t  MSDCLKOFF            :1;
            __IO  uint32_t  RESERVED4            :15;
        };
        struct {
            __IO  uint32_t  RESERVED1            :4;
            __IO  uint32_t  CASEL0               :1;
            __IO  uint32_t  CASEL1               :1;
            __IO  uint32_t  RESERVED3            :2;
            __IO  uint32_t  RASEL0               :1;
            __IO  uint32_t  RASEL1               :1;
            __IO  uint32_t  RASEL2               :1;
            __IO  uint32_t  RASEL3               :1;
            __IO  uint32_t  BASEL0               :1;
            __IO  uint32_t  BASEL1               :1;
            __IO  uint32_t  BASEL2               :1;
            __IO  uint32_t  BASEL3               :1;
            __IO  uint32_t  RESERVED5            :16;
        };
    };
} stc_exbus_sdmode_field_t;

typedef struct stc_exbus_reftim_field
{
    union {
        struct {
            __IO  uint32_t  REFC                 :16;
            __IO  uint32_t  NREF                 :8;
            __IO  uint32_t  PREF                 :1;
            __IO  uint32_t  RESERVED0            :7;
        };
        struct {
            __IO  uint32_t  REFC0                :1;
            __IO  uint32_t  REFC1                :1;
            __IO  uint32_t  REFC2                :1;
            __IO  uint32_t  REFC3                :1;
            __IO  uint32_t  REFC4                :1;
            __IO  uint32_t  REFC5                :1;
            __IO  uint32_t  REFC6                :1;
            __IO  uint32_t  REFC7                :1;
            __IO  uint32_t  REFC8                :1;
            __IO  uint32_t  REFC9                :1;
            __IO  uint32_t  REFC10               :1;
            __IO  uint32_t  REFC11               :1;
            __IO  uint32_t  REFC12               :1;
            __IO  uint32_t  REFC13               :1;
            __IO  uint32_t  REFC14               :1;
            __IO  uint32_t  REFC15               :1;
            __IO  uint32_t  NREF0                :1;
            __IO  uint32_t  NREF1                :1;
            __IO  uint32_t  NREF2                :1;
            __IO  uint32_t  NREF3                :1;
            __IO  uint32_t  NREF4                :1;
            __IO  uint32_t  NREF5                :1;
            __IO  uint32_t  NREF6                :1;
            __IO  uint32_t  NREF7                :1;
            __IO  uint32_t  RESERVED1            :8;
        };
    };
} stc_exbus_reftim_field_t;

typedef struct stc_exbus_pwrdwn_field
{
    union {
        struct {
            __IO  uint32_t  PDC                  :16;
            __IO  uint32_t  RESERVED0            :16;
        };
        struct {
            __IO  uint32_t  PDC0                 :1;
            __IO  uint32_t  PDC1                 :1;
            __IO  uint32_t  PDC2                 :1;
            __IO  uint32_t  PDC3                 :1;
            __IO  uint32_t  PDC4                 :1;
            __IO  uint32_t  PDC5                 :1;
            __IO  uint32_t  PDC6                 :1;
            __IO  uint32_t  PDC7                 :1;
            __IO  uint32_t  PDC8                 :1;
            __IO  uint32_t  PDC9                 :1;
            __IO  uint32_t  PDC10                :1;
            __IO  uint32_t  PDC11                :1;
            __IO  uint32_t  PDC12                :1;
            __IO  uint32_t  PDC13                :1;
            __IO  uint32_t  PDC14                :1;
            __IO  uint32_t  PDC15                :1;
            __IO  uint32_t  RESERVED1            :16;
        };
    };
} stc_exbus_pwrdwn_field_t;

typedef struct stc_exbus_sdtim_field
{
    union {
        struct {
            __IO  uint32_t  CL                   :2;
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  TRC                  :4;
            __IO  uint32_t  TRP                  :4;
            __IO  uint32_t  TRCD                 :4;
            __IO  uint32_t  TRAS                 :4;
            __IO  uint32_t  TREFC                :4;
            __IO  uint32_t  TDPL                 :2;
            __IO  uint32_t  RESERVED2            :5;
            __IO  uint32_t  BOFF                 :1;
        };
        struct {
            __IO  uint32_t  CL0                  :1;
            __IO  uint32_t  CL1                  :1;
            __IO  uint32_t  RESERVED1            :2;
            __IO  uint32_t  TRC0                 :1;
            __IO  uint32_t  TRC1                 :1;
            __IO  uint32_t  TRC2                 :1;
            __IO  uint32_t  TRC3                 :1;
            __IO  uint32_t  TRP0                 :1;
            __IO  uint32_t  TRP1                 :1;
            __IO  uint32_t  TRP2                 :1;
            __IO  uint32_t  TRP3                 :1;
            __IO  uint32_t  TRCD0                :1;
            __IO  uint32_t  TRCD1                :1;
            __IO  uint32_t  TRCD2                :1;
            __IO  uint32_t  TRCD3                :1;
            __IO  uint32_t  TRAS0                :1;
            __IO  uint32_t  TRAS1                :1;
            __IO  uint32_t  TRAS2                :1;
            __IO  uint32_t  TRAS3                :1;
            __IO  uint32_t  TREFC0               :1;
            __IO  uint32_t  TREFC1               :1;
            __IO  uint32_t  TREFC2               :1;
            __IO  uint32_t  TREFC3               :1;
            __IO  uint32_t  TDPL0                :1;
            __IO  uint32_t  TDPL1                :1;
            __IO  uint32_t  RESERVED3            :6;
        };
    };
} stc_exbus_sdtim_field_t;

typedef struct stc_exbus_sdcmd_field
{
    union {
        struct {
            __IO  uint32_t  SDAD                 :16;
            __IO  uint32_t  SDWE                 :1;
            __IO  uint32_t  SDCAS                :1;
            __IO  uint32_t  SDRAS                :1;
            __IO  uint32_t  SDCS                 :1;
            __IO  uint32_t  SDCKE                :1;
            __IO  uint32_t  RESERVED0            :10;
            __IO  uint32_t  PEND                 :1;
        };
        struct {
            __IO  uint32_t  SDAD0                :1;
            __IO  uint32_t  SDAD1                :1;
            __IO  uint32_t  SDAD2                :1;
            __IO  uint32_t  SDAD3                :1;
            __IO  uint32_t  SDAD4                :1;
            __IO  uint32_t  SDAD5                :1;
            __IO  uint32_t  SDAD6                :1;
            __IO  uint32_t  SDAD7                :1;
            __IO  uint32_t  SDAD8                :1;
            __IO  uint32_t  SDAD9                :1;
            __IO  uint32_t  SDAD10               :1;
            __IO  uint32_t  SDAD11               :1;
            __IO  uint32_t  SDAD12               :1;
            __IO  uint32_t  SDAD13               :1;
            __IO  uint32_t  SDAD14               :1;
            __IO  uint32_t  SDAD15               :1;
            __IO  uint32_t  RESERVED1            :16;
        };
    };
} stc_exbus_sdcmd_field_t;

typedef struct stc_exbus_memcerr_field
{
        __IO  uint32_t  SFER                     :1;
        __IO  uint32_t  SDER                     :1;
        __IO  uint32_t  SFION                    :1;
        __IO  uint32_t  SDION                    :1;
        __IO  uint32_t  RESERVED0                :28;
} stc_exbus_memcerr_field_t;

typedef struct stc_exbus_dclkr_field
{
    union {
        struct {
            __IO  uint32_t  MDIV                 :4;
            __IO  uint32_t  MCLKON               :1;
            __IO  uint32_t  RESERVED0            :27;
        };
        struct {
            __IO  uint32_t  MDIV0                :1;
            __IO  uint32_t  MDIV1                :1;
            __IO  uint32_t  MDIV2                :1;
            __IO  uint32_t  MDIV3                :1;
            __IO  uint32_t  RESERVED1            :28;
        };
    };
} stc_exbus_dclkr_field_t;

typedef struct stc_exbus_est_field
{
        __IO  uint32_t  WERR                     :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_exbus_est_field_t;

typedef struct stc_exbus_wead_field
{
    union {
        struct {
            __IO  uint32_t  ADDR                 :32;
        };
        struct {
            __IO  uint32_t  ADDR0                :1;
            __IO  uint32_t  ADDR1                :1;
            __IO  uint32_t  ADDR2                :1;
            __IO  uint32_t  ADDR3                :1;
            __IO  uint32_t  ADDR4                :1;
            __IO  uint32_t  ADDR5                :1;
            __IO  uint32_t  ADDR6                :1;
            __IO  uint32_t  ADDR7                :1;
            __IO  uint32_t  ADDR8                :1;
            __IO  uint32_t  ADDR9                :1;
            __IO  uint32_t  ADDR10               :1;
            __IO  uint32_t  ADDR11               :1;
            __IO  uint32_t  ADDR12               :1;
            __IO  uint32_t  ADDR13               :1;
            __IO  uint32_t  ADDR14               :1;
            __IO  uint32_t  ADDR15               :1;
            __IO  uint32_t  ADDR16               :1;
            __IO  uint32_t  ADDR17               :1;
            __IO  uint32_t  ADDR18               :1;
            __IO  uint32_t  ADDR19               :1;
            __IO  uint32_t  ADDR20               :1;
            __IO  uint32_t  ADDR21               :1;
            __IO  uint32_t  ADDR22               :1;
            __IO  uint32_t  ADDR23               :1;
            __IO  uint32_t  ADDR24               :1;
            __IO  uint32_t  ADDR25               :1;
            __IO  uint32_t  ADDR26               :1;
            __IO  uint32_t  ADDR27               :1;
            __IO  uint32_t  ADDR28               :1;
            __IO  uint32_t  ADDR29               :1;
            __IO  uint32_t  ADDR30               :1;
            __IO  uint32_t  ADDR31               :1;
        };
    };
} stc_exbus_wead_field_t;

typedef struct stc_exbus_esclr_field
{
        __IO  uint32_t  WERRCLR                  :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_exbus_esclr_field_t;

typedef struct stc_exbus_amode_field
{
        __IO  uint32_t  WAEN                     :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_exbus_amode_field_t;

/*******************************************************************************
* EXTI_MODULE
*******************************************************************************/
typedef struct stc_exti_enir_field
{
        __IO  uint32_t  EN0                      :1;
        __IO  uint32_t  EN1                      :1;
        __IO  uint32_t  EN2                      :1;
        __IO  uint32_t  EN3                      :1;
        __IO  uint32_t  EN4                      :1;
        __IO  uint32_t  EN5                      :1;
        __IO  uint32_t  EN6                      :1;
        __IO  uint32_t  EN7                      :1;
        __IO  uint32_t  EN8                      :1;
        __IO  uint32_t  EN9                      :1;
        __IO  uint32_t  EN10                     :1;
        __IO  uint32_t  EN11                     :1;
        __IO  uint32_t  EN12                     :1;
        __IO  uint32_t  EN13                     :1;
        __IO  uint32_t  EN14                     :1;
        __IO  uint32_t  EN15                     :1;
        __IO  uint32_t  EN16                     :1;
        __IO  uint32_t  EN17                     :1;
        __IO  uint32_t  EN18                     :1;
        __IO  uint32_t  EN19                     :1;
        __IO  uint32_t  EN20                     :1;
        __IO  uint32_t  EN21                     :1;
        __IO  uint32_t  EN22                     :1;
        __IO  uint32_t  EN23                     :1;
        __IO  uint32_t  EN24                     :1;
        __IO  uint32_t  EN25                     :1;
        __IO  uint32_t  EN26                     :1;
        __IO  uint32_t  EN27                     :1;
        __IO  uint32_t  EN28                     :1;
        __IO  uint32_t  EN29                     :1;
        __IO  uint32_t  EN30                     :1;
        __IO  uint32_t  EN31                     :1;
} stc_exti_enir_field_t;

typedef struct stc_exti_eirr_field
{
        __IO  uint32_t  ER0                      :1;
        __IO  uint32_t  ER1                      :1;
        __IO  uint32_t  ER2                      :1;
        __IO  uint32_t  ER3                      :1;
        __IO  uint32_t  ER4                      :1;
        __IO  uint32_t  ER5                      :1;
        __IO  uint32_t  ER6                      :1;
        __IO  uint32_t  ER7                      :1;
        __IO  uint32_t  ER8                      :1;
        __IO  uint32_t  ER9                      :1;
        __IO  uint32_t  ER10                     :1;
        __IO  uint32_t  ER11                     :1;
        __IO  uint32_t  ER12                     :1;
        __IO  uint32_t  ER13                     :1;
        __IO  uint32_t  ER14                     :1;
        __IO  uint32_t  ER15                     :1;
        __IO  uint32_t  ER16                     :1;
        __IO  uint32_t  ER17                     :1;
        __IO  uint32_t  ER18                     :1;
        __IO  uint32_t  ER19                     :1;
        __IO  uint32_t  ER20                     :1;
        __IO  uint32_t  ER21                     :1;
        __IO  uint32_t  ER22                     :1;
        __IO  uint32_t  ER23                     :1;
        __IO  uint32_t  ER24                     :1;
        __IO  uint32_t  ER25                     :1;
        __IO  uint32_t  ER26                     :1;
        __IO  uint32_t  ER27                     :1;
        __IO  uint32_t  ER28                     :1;
        __IO  uint32_t  ER29                     :1;
        __IO  uint32_t  ER30                     :1;
        __IO  uint32_t  ER31                     :1;
} stc_exti_eirr_field_t;

typedef struct stc_exti_eicl_field
{
        __IO  uint32_t  ECL0                     :1;
        __IO  uint32_t  ECL1                     :1;
        __IO  uint32_t  ECL2                     :1;
        __IO  uint32_t  ECL3                     :1;
        __IO  uint32_t  ECL4                     :1;
        __IO  uint32_t  ECL5                     :1;
        __IO  uint32_t  ECL6                     :1;
        __IO  uint32_t  ECL7                     :1;
        __IO  uint32_t  ECL8                     :1;
        __IO  uint32_t  ECL9                     :1;
        __IO  uint32_t  ECL10                    :1;
        __IO  uint32_t  ECL11                    :1;
        __IO  uint32_t  ECL12                    :1;
        __IO  uint32_t  ECL13                    :1;
        __IO  uint32_t  ECL14                    :1;
        __IO  uint32_t  ECL15                    :1;
        __IO  uint32_t  ECL16                    :1;
        __IO  uint32_t  ECL17                    :1;
        __IO  uint32_t  ECL18                    :1;
        __IO  uint32_t  ECL19                    :1;
        __IO  uint32_t  ECL20                    :1;
        __IO  uint32_t  ECL21                    :1;
        __IO  uint32_t  ECL22                    :1;
        __IO  uint32_t  ECL23                    :1;
        __IO  uint32_t  ECL24                    :1;
        __IO  uint32_t  ECL25                    :1;
        __IO  uint32_t  ECL26                    :1;
        __IO  uint32_t  ECL27                    :1;
        __IO  uint32_t  ECL28                    :1;
        __IO  uint32_t  ECL29                    :1;
        __IO  uint32_t  ECL30                    :1;
        __IO  uint32_t  ECL31                    :1;
} stc_exti_eicl_field_t;

typedef struct stc_exti_elvr_field
{
        __IO  uint32_t  LA0                      :1;
        __IO  uint32_t  LB0                      :1;
        __IO  uint32_t  LA1                      :1;
        __IO  uint32_t  LB1                      :1;
        __IO  uint32_t  LA2                      :1;
        __IO  uint32_t  LB2                      :1;
        __IO  uint32_t  LA3                      :1;
        __IO  uint32_t  LB3                      :1;
        __IO  uint32_t  LA4                      :1;
        __IO  uint32_t  LB4                      :1;
        __IO  uint32_t  LA5                      :1;
        __IO  uint32_t  LB5                      :1;
        __IO  uint32_t  LA6                      :1;
        __IO  uint32_t  LB6                      :1;
        __IO  uint32_t  LA7                      :1;
        __IO  uint32_t  LB7                      :1;
        __IO  uint32_t  LA8                      :1;
        __IO  uint32_t  LB8                      :1;
        __IO  uint32_t  LA9                      :1;
        __IO  uint32_t  LB9                      :1;
        __IO  uint32_t  LA10                     :1;
        __IO  uint32_t  LB10                     :1;
        __IO  uint32_t  LA11                     :1;
        __IO  uint32_t  LB11                     :1;
        __IO  uint32_t  LA12                     :1;
        __IO  uint32_t  LB12                     :1;
        __IO  uint32_t  LA13                     :1;
        __IO  uint32_t  LB13                     :1;
        __IO  uint32_t  LA14                     :1;
        __IO  uint32_t  LB14                     :1;
        __IO  uint32_t  LA15                     :1;
        __IO  uint32_t  LB15                     :1;
} stc_exti_elvr_field_t;

typedef struct stc_exti_elvr1_field
{
        __IO  uint32_t  LA16                     :1;
        __IO  uint32_t  LB16                     :1;
        __IO  uint32_t  LA17                     :1;
        __IO  uint32_t  LB17                     :1;
        __IO  uint32_t  LA18                     :1;
        __IO  uint32_t  LB18                     :1;
        __IO  uint32_t  LA19                     :1;
        __IO  uint32_t  LB19                     :1;
        __IO  uint32_t  LA20                     :1;
        __IO  uint32_t  LB20                     :1;
        __IO  uint32_t  LA21                     :1;
        __IO  uint32_t  LB21                     :1;
        __IO  uint32_t  LA22                     :1;
        __IO  uint32_t  LB22                     :1;
        __IO  uint32_t  LA23                     :1;
        __IO  uint32_t  LB23                     :1;
        __IO  uint32_t  LA24                     :1;
        __IO  uint32_t  LB24                     :1;
        __IO  uint32_t  LA25                     :1;
        __IO  uint32_t  LB25                     :1;
        __IO  uint32_t  LA26                     :1;
        __IO  uint32_t  LB26                     :1;
        __IO  uint32_t  LA27                     :1;
        __IO  uint32_t  LB27                     :1;
        __IO  uint32_t  LA28                     :1;
        __IO  uint32_t  LB28                     :1;
        __IO  uint32_t  LA29                     :1;
        __IO  uint32_t  LB29                     :1;
        __IO  uint32_t  LA30                     :1;
        __IO  uint32_t  LB30                     :1;
        __IO  uint32_t  LA31                     :1;
        __IO  uint32_t  LB31                     :1;
} stc_exti_elvr1_field_t;

typedef struct stc_exti_nmirr_field
{
        __IO  uint16_t  NR                       :1;
        __IO  uint16_t  RESERVED0                :15;
} stc_exti_nmirr_field_t;

typedef struct stc_exti_nmicl_field
{
        __IO  uint16_t  NCL                      :1;
        __IO  uint16_t  RESERVED0                :15;
} stc_exti_nmicl_field_t;

/*******************************************************************************
* FLASH_IF_MODULE
*******************************************************************************/
typedef struct stc_flash_if_faszr_field
{
    union {
        struct {
            __IO  uint32_t  ASZ                  :2;
            __IO  uint32_t  RESERVED0            :30;
        };
        struct {
            __IO  uint32_t  ASZ0                 :1;
            __IO  uint32_t  ASZ1                 :1;
            __IO  uint32_t  RESERVED1            :30;
        };
    };
} stc_flash_if_faszr_field_t;

typedef struct stc_flash_if_frwtr_field
{
    union {
        struct {
            __IO  uint32_t  RWT                  :2;
            __IO  uint32_t  RESERVED0            :30;
        };
        struct {
            __IO  uint32_t  RWT0                 :1;
            __IO  uint32_t  RWT1                 :1;
            __IO  uint32_t  RESERVED1            :30;
        };
    };
} stc_flash_if_frwtr_field_t;

typedef struct stc_flash_if_fstr_field
{
        __IO  uint32_t  RDY                      :1;
        __IO  uint32_t  HNG                      :1;
        __IO  uint32_t  ERR                      :1;
        __IO  uint32_t  RESERVED0                :29;
} stc_flash_if_fstr_field_t;

typedef struct stc_flash_if_fsyndn_field
{
    union {
        struct {
            __IO  uint32_t  SD                   :3;
            __IO  uint32_t  RESERVED0            :29;
        };
        struct {
            __IO  uint32_t  SD0                  :1;
            __IO  uint32_t  SD1                  :1;
            __IO  uint32_t  SD2                  :1;
            __IO  uint32_t  RESERVED1            :29;
        };
    };
} stc_flash_if_fsyndn_field_t;

typedef struct stc_flash_if_fbfcr_field
{
        __IO  uint32_t  BE                       :1;
        __IO  uint32_t  BS                       :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_flash_if_fbfcr_field_t;

typedef struct stc_flash_if_ficr_field
{
        __IO  uint32_t  RDYIE                    :1;
        __IO  uint32_t  HNGIE                    :1;
        __IO  uint32_t  ERRIE                    :1;
        __IO  uint32_t  RESERVED0                :29;
} stc_flash_if_ficr_field_t;

typedef struct stc_flash_if_fisr_field
{
        __IO  uint32_t  RDYIF                    :1;
        __IO  uint32_t  HNGIF                    :1;
        __IO  uint32_t  ERRIF                    :1;
        __IO  uint32_t  RESERVED0                :29;
} stc_flash_if_fisr_field_t;

typedef struct stc_flash_if_ficlr_field
{
        __IO  uint32_t  RDYIC                    :1;
        __IO  uint32_t  HNGIC                    :1;
        __IO  uint32_t  ERRIC                    :1;
        __IO  uint32_t  RESERVED0                :29;
} stc_flash_if_ficlr_field_t;

typedef struct stc_flash_if_dfctrlr_field
{
    union {
        struct {
            __IO  uint32_t  DFE                  :1;
            __IO  uint32_t  RME                  :1;
            __IO  uint32_t  RESERVED0            :14;
            __IO  uint32_t  WKEY                 :16;
        };
        struct {
            __IO  uint32_t  RESERVED1            :16;
            __IO  uint32_t  WKEY0                :1;
            __IO  uint32_t  WKEY1                :1;
            __IO  uint32_t  WKEY2                :1;
            __IO  uint32_t  WKEY3                :1;
            __IO  uint32_t  WKEY4                :1;
            __IO  uint32_t  WKEY5                :1;
            __IO  uint32_t  WKEY6                :1;
            __IO  uint32_t  WKEY7                :1;
            __IO  uint32_t  WKEY8                :1;
            __IO  uint32_t  WKEY9                :1;
            __IO  uint32_t  WKEY10               :1;
            __IO  uint32_t  WKEY11               :1;
            __IO  uint32_t  WKEY12               :1;
            __IO  uint32_t  WKEY13               :1;
            __IO  uint32_t  WKEY14               :1;
            __IO  uint32_t  WKEY15               :1;
        };
    };
} stc_flash_if_dfctrlr_field_t;

typedef struct stc_flash_if_crtrmm_field
{
    union {
        struct {
            __IO  uint32_t  TRMM                 :10;
            __IO  uint32_t  RESERVED0            :6;
            __IO  uint32_t  TTRMM                :5;
            __IO  uint32_t  RESERVED2            :11;
        };
        struct {
            __IO  uint32_t  TRMM0                :1;
            __IO  uint32_t  TRMM1                :1;
            __IO  uint32_t  TRMM2                :1;
            __IO  uint32_t  TRMM3                :1;
            __IO  uint32_t  TRMM4                :1;
            __IO  uint32_t  TRMM5                :1;
            __IO  uint32_t  TRMM6                :1;
            __IO  uint32_t  TRMM7                :1;
            __IO  uint32_t  TRMM8                :1;
            __IO  uint32_t  TRMM9                :1;
            __IO  uint32_t  RESERVED1            :6;
            __IO  uint32_t  TTRMM0               :1;
            __IO  uint32_t  TTRMM1               :1;
            __IO  uint32_t  TTRMM2               :1;
            __IO  uint32_t  TTRMM3               :1;
            __IO  uint32_t  TTRMM4               :1;
            __IO  uint32_t  RESERVED3            :11;
        };
    };
} stc_flash_if_crtrmm_field_t;

typedef struct stc_flash_if_fgpdm1_field
{
    union {
        struct {
            __IO  uint32_t  GPD1                 :32;
        };
        struct {
            __IO  uint32_t  GPD10                :1;
            __IO  uint32_t  GPD11                :1;
            __IO  uint32_t  GPD12                :1;
            __IO  uint32_t  GPD13                :1;
            __IO  uint32_t  GPD14                :1;
            __IO  uint32_t  GPD15                :1;
            __IO  uint32_t  GPD16                :1;
            __IO  uint32_t  GPD17                :1;
            __IO  uint32_t  GPD18                :1;
            __IO  uint32_t  GPD19                :1;
            __IO  uint32_t  GPD110               :1;
            __IO  uint32_t  GPD111               :1;
            __IO  uint32_t  GPD112               :1;
            __IO  uint32_t  GPD113               :1;
            __IO  uint32_t  GPD114               :1;
            __IO  uint32_t  GPD115               :1;
            __IO  uint32_t  GPD116               :1;
            __IO  uint32_t  GPD117               :1;
            __IO  uint32_t  GPD118               :1;
            __IO  uint32_t  GPD119               :1;
            __IO  uint32_t  GPD120               :1;
            __IO  uint32_t  GPD121               :1;
            __IO  uint32_t  GPD122               :1;
            __IO  uint32_t  GPD123               :1;
            __IO  uint32_t  GPD124               :1;
            __IO  uint32_t  GPD125               :1;
            __IO  uint32_t  GPD126               :1;
            __IO  uint32_t  GPD127               :1;
            __IO  uint32_t  GPD128               :1;
            __IO  uint32_t  GPD129               :1;
            __IO  uint32_t  GPD130               :1;
            __IO  uint32_t  GPD131               :1;
        };
    };
} stc_flash_if_fgpdm1_field_t;

typedef struct stc_flash_if_fgpdm2_field
{
    union {
        struct {
            __IO  uint32_t  GPD2                 :32;
        };
        struct {
            __IO  uint32_t  GPD20                :1;
            __IO  uint32_t  GPD21                :1;
            __IO  uint32_t  GPD22                :1;
            __IO  uint32_t  GPD23                :1;
            __IO  uint32_t  GPD24                :1;
            __IO  uint32_t  GPD25                :1;
            __IO  uint32_t  GPD26                :1;
            __IO  uint32_t  GPD27                :1;
            __IO  uint32_t  GPD28                :1;
            __IO  uint32_t  GPD29                :1;
            __IO  uint32_t  GPD210               :1;
            __IO  uint32_t  GPD211               :1;
            __IO  uint32_t  GPD212               :1;
            __IO  uint32_t  GPD213               :1;
            __IO  uint32_t  GPD214               :1;
            __IO  uint32_t  GPD215               :1;
            __IO  uint32_t  GPD216               :1;
            __IO  uint32_t  GPD217               :1;
            __IO  uint32_t  GPD218               :1;
            __IO  uint32_t  GPD219               :1;
            __IO  uint32_t  GPD220               :1;
            __IO  uint32_t  GPD221               :1;
            __IO  uint32_t  GPD222               :1;
            __IO  uint32_t  GPD223               :1;
            __IO  uint32_t  GPD224               :1;
            __IO  uint32_t  GPD225               :1;
            __IO  uint32_t  GPD226               :1;
            __IO  uint32_t  GPD227               :1;
            __IO  uint32_t  GPD228               :1;
            __IO  uint32_t  GPD229               :1;
            __IO  uint32_t  GPD230               :1;
            __IO  uint32_t  GPD231               :1;
        };
    };
} stc_flash_if_fgpdm2_field_t;

typedef struct stc_flash_if_fgpdm3_field
{
    union {
        struct {
            __IO  uint32_t  GPD3                 :32;
        };
        struct {
            __IO  uint32_t  GPD30                :1;
            __IO  uint32_t  GPD31                :1;
            __IO  uint32_t  GPD32                :1;
            __IO  uint32_t  GPD33                :1;
            __IO  uint32_t  GPD34                :1;
            __IO  uint32_t  GPD35                :1;
            __IO  uint32_t  GPD36                :1;
            __IO  uint32_t  GPD37                :1;
            __IO  uint32_t  GPD38                :1;
            __IO  uint32_t  GPD39                :1;
            __IO  uint32_t  GPD310               :1;
            __IO  uint32_t  GPD311               :1;
            __IO  uint32_t  GPD312               :1;
            __IO  uint32_t  GPD313               :1;
            __IO  uint32_t  GPD314               :1;
            __IO  uint32_t  GPD315               :1;
            __IO  uint32_t  GPD316               :1;
            __IO  uint32_t  GPD317               :1;
            __IO  uint32_t  GPD318               :1;
            __IO  uint32_t  GPD319               :1;
            __IO  uint32_t  GPD320               :1;
            __IO  uint32_t  GPD321               :1;
            __IO  uint32_t  GPD322               :1;
            __IO  uint32_t  GPD323               :1;
            __IO  uint32_t  GPD324               :1;
            __IO  uint32_t  GPD325               :1;
            __IO  uint32_t  GPD326               :1;
            __IO  uint32_t  GPD327               :1;
            __IO  uint32_t  GPD328               :1;
            __IO  uint32_t  GPD329               :1;
            __IO  uint32_t  GPD330               :1;
            __IO  uint32_t  GPD331               :1;
        };
    };
} stc_flash_if_fgpdm3_field_t;

typedef struct stc_flash_if_fgpdm4_field
{
    union {
        struct {
            __IO  uint32_t  GPD4                 :32;
        };
        struct {
            __IO  uint32_t  GPD40                :1;
            __IO  uint32_t  GPD41                :1;
            __IO  uint32_t  GPD42                :1;
            __IO  uint32_t  GPD43                :1;
            __IO  uint32_t  GPD44                :1;
            __IO  uint32_t  GPD45                :1;
            __IO  uint32_t  GPD46                :1;
            __IO  uint32_t  GPD47                :1;
            __IO  uint32_t  GPD48                :1;
            __IO  uint32_t  GPD49                :1;
            __IO  uint32_t  GPD410               :1;
            __IO  uint32_t  GPD411               :1;
            __IO  uint32_t  GPD412               :1;
            __IO  uint32_t  GPD413               :1;
            __IO  uint32_t  GPD414               :1;
            __IO  uint32_t  GPD415               :1;
            __IO  uint32_t  GPD416               :1;
            __IO  uint32_t  GPD417               :1;
            __IO  uint32_t  GPD418               :1;
            __IO  uint32_t  GPD419               :1;
            __IO  uint32_t  GPD420               :1;
            __IO  uint32_t  GPD421               :1;
            __IO  uint32_t  GPD422               :1;
            __IO  uint32_t  GPD423               :1;
            __IO  uint32_t  GPD424               :1;
            __IO  uint32_t  GPD425               :1;
            __IO  uint32_t  GPD426               :1;
            __IO  uint32_t  GPD427               :1;
            __IO  uint32_t  GPD428               :1;
            __IO  uint32_t  GPD429               :1;
            __IO  uint32_t  GPD430               :1;
            __IO  uint32_t  GPD431               :1;
        };
    };
} stc_flash_if_fgpdm4_field_t;

/*******************************************************************************
* GPIO_MODULE
*******************************************************************************/
typedef struct stc_gpio_pfr0_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  RESERVED0                :3;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  RESERVED1                :21;
} stc_gpio_pfr0_field_t;

typedef struct stc_gpio_pfr1_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  PF                       :1;
        __IO  uint32_t  RESERVED0                :16;
} stc_gpio_pfr1_field_t;

typedef struct stc_gpio_pfr2_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  RESERVED0                :21;
} stc_gpio_pfr2_field_t;

typedef struct stc_gpio_pfr3_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  RESERVED0                :17;
} stc_gpio_pfr3_field_t;

typedef struct stc_gpio_pfr4_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  RESERVED0                :22;
} stc_gpio_pfr4_field_t;

typedef struct stc_gpio_pfr5_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  RESERVED0                :10;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  PF                       :1;
        __IO  uint32_t  RESERVED1                :16;
} stc_gpio_pfr5_field_t;

typedef struct stc_gpio_pfr6_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  RESERVED0                :8;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  RESERVED1                :17;
} stc_gpio_pfr6_field_t;

typedef struct stc_gpio_pfr7_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  RESERVED0                :17;
} stc_gpio_pfr7_field_t;

typedef struct stc_gpio_pfr8_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  RESERVED0                :28;
} stc_gpio_pfr8_field_t;

typedef struct stc_gpio_pfr9_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  RESERVED0                :26;
} stc_gpio_pfr9_field_t;

typedef struct stc_gpio_pfra_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  PF                       :1;
        __IO  uint32_t  RESERVED0                :16;
} stc_gpio_pfra_field_t;

typedef struct stc_gpio_pfrb_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  RESERVED0                :24;
} stc_gpio_pfrb_field_t;

typedef struct stc_gpio_pfrc_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  PF                       :1;
        __IO  uint32_t  RESERVED0                :16;
} stc_gpio_pfrc_field_t;

typedef struct stc_gpio_pfrd_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  RESERVED0                :29;
} stc_gpio_pfrd_field_t;

typedef struct stc_gpio_pfre_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  RESERVED0                :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  RESERVED1                :28;
} stc_gpio_pfre_field_t;

typedef struct stc_gpio_pfrf_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  RESERVED0                :24;
} stc_gpio_pfrf_field_t;

typedef struct stc_gpio_pcr0_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  RESERVED0                :3;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  RESERVED1                :21;
} stc_gpio_pcr0_field_t;

typedef struct stc_gpio_pcr1_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  PF                       :1;
        __IO  uint32_t  RESERVED0                :16;
} stc_gpio_pcr1_field_t;

typedef struct stc_gpio_pcr2_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  RESERVED0                :21;
} stc_gpio_pcr2_field_t;

typedef struct stc_gpio_pcr3_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  RESERVED0                :17;
} stc_gpio_pcr3_field_t;

typedef struct stc_gpio_pcr4_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  RESERVED0                :22;
} stc_gpio_pcr4_field_t;

typedef struct stc_gpio_pcr5_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  RESERVED0                :10;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  PF                       :1;
        __IO  uint32_t  RESERVED1                :16;
} stc_gpio_pcr5_field_t;

typedef struct stc_gpio_pcr6_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  RESERVED0                :8;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  RESERVED1                :17;
} stc_gpio_pcr6_field_t;

typedef struct stc_gpio_pcr7_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  RESERVED0                :17;
} stc_gpio_pcr7_field_t;

typedef struct stc_gpio_pcr9_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  RESERVED0                :26;
} stc_gpio_pcr9_field_t;

typedef struct stc_gpio_pcra_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  PF                       :1;
        __IO  uint32_t  RESERVED0                :16;
} stc_gpio_pcra_field_t;

typedef struct stc_gpio_pcrb_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  RESERVED0                :24;
} stc_gpio_pcrb_field_t;

typedef struct stc_gpio_pcrc_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  PF                       :1;
        __IO  uint32_t  RESERVED0                :16;
} stc_gpio_pcrc_field_t;

typedef struct stc_gpio_pcrd_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  RESERVED0                :29;
} stc_gpio_pcrd_field_t;

typedef struct stc_gpio_pcre_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  RESERVED0                :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  RESERVED1                :28;
} stc_gpio_pcre_field_t;

typedef struct stc_gpio_pcrf_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  RESERVED0                :24;
} stc_gpio_pcrf_field_t;

typedef struct stc_gpio_ddr0_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  RESERVED0                :3;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  RESERVED1                :21;
} stc_gpio_ddr0_field_t;

typedef struct stc_gpio_ddr1_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  PF                       :1;
        __IO  uint32_t  RESERVED0                :16;
} stc_gpio_ddr1_field_t;

typedef struct stc_gpio_ddr2_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  RESERVED0                :21;
} stc_gpio_ddr2_field_t;

typedef struct stc_gpio_ddr3_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  RESERVED0                :17;
} stc_gpio_ddr3_field_t;

typedef struct stc_gpio_ddr4_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  RESERVED0                :22;
} stc_gpio_ddr4_field_t;

typedef struct stc_gpio_ddr5_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  RESERVED0                :10;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  PF                       :1;
        __IO  uint32_t  RESERVED1                :16;
} stc_gpio_ddr5_field_t;

typedef struct stc_gpio_ddr6_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  RESERVED0                :8;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  RESERVED1                :17;
} stc_gpio_ddr6_field_t;

typedef struct stc_gpio_ddr7_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  RESERVED0                :17;
} stc_gpio_ddr7_field_t;

typedef struct stc_gpio_ddr8_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  RESERVED0                :28;
} stc_gpio_ddr8_field_t;

typedef struct stc_gpio_ddr9_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  RESERVED0                :26;
} stc_gpio_ddr9_field_t;

typedef struct stc_gpio_ddra_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  PF                       :1;
        __IO  uint32_t  RESERVED0                :16;
} stc_gpio_ddra_field_t;

typedef struct stc_gpio_ddrb_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  RESERVED0                :24;
} stc_gpio_ddrb_field_t;

typedef struct stc_gpio_ddrc_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  PF                       :1;
        __IO  uint32_t  RESERVED0                :16;
} stc_gpio_ddrc_field_t;

typedef struct stc_gpio_ddrd_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  RESERVED0                :29;
} stc_gpio_ddrd_field_t;

typedef struct stc_gpio_ddre_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  RESERVED0                :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  RESERVED1                :28;
} stc_gpio_ddre_field_t;

typedef struct stc_gpio_ddrf_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  RESERVED0                :24;
} stc_gpio_ddrf_field_t;

typedef struct stc_gpio_pdir0_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  RESERVED0                :3;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  RESERVED1                :21;
} stc_gpio_pdir0_field_t;

typedef struct stc_gpio_pdir1_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  PF                       :1;
        __IO  uint32_t  RESERVED0                :16;
} stc_gpio_pdir1_field_t;

typedef struct stc_gpio_pdir2_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  RESERVED0                :21;
} stc_gpio_pdir2_field_t;

typedef struct stc_gpio_pdir3_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  RESERVED0                :17;
} stc_gpio_pdir3_field_t;

typedef struct stc_gpio_pdir4_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  RESERVED0                :22;
} stc_gpio_pdir4_field_t;

typedef struct stc_gpio_pdir5_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  RESERVED0                :10;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  PF                       :1;
        __IO  uint32_t  RESERVED1                :16;
} stc_gpio_pdir5_field_t;

typedef struct stc_gpio_pdir6_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  RESERVED0                :8;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  RESERVED1                :17;
} stc_gpio_pdir6_field_t;

typedef struct stc_gpio_pdir7_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  RESERVED0                :17;
} stc_gpio_pdir7_field_t;

typedef struct stc_gpio_pdir8_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  RESERVED0                :28;
} stc_gpio_pdir8_field_t;

typedef struct stc_gpio_pdir9_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  RESERVED0                :26;
} stc_gpio_pdir9_field_t;

typedef struct stc_gpio_pdira_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  PF                       :1;
        __IO  uint32_t  RESERVED0                :16;
} stc_gpio_pdira_field_t;

typedef struct stc_gpio_pdirb_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  RESERVED0                :24;
} stc_gpio_pdirb_field_t;

typedef struct stc_gpio_pdirc_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  PF                       :1;
        __IO  uint32_t  RESERVED0                :16;
} stc_gpio_pdirc_field_t;

typedef struct stc_gpio_pdird_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  RESERVED0                :29;
} stc_gpio_pdird_field_t;

typedef struct stc_gpio_pdire_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  RESERVED0                :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  RESERVED1                :28;
} stc_gpio_pdire_field_t;

typedef struct stc_gpio_pdirf_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  RESERVED0                :24;
} stc_gpio_pdirf_field_t;

typedef struct stc_gpio_pdor0_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  RESERVED0                :3;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  RESERVED1                :21;
} stc_gpio_pdor0_field_t;

typedef struct stc_gpio_pdor1_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  PF                       :1;
        __IO  uint32_t  RESERVED0                :16;
} stc_gpio_pdor1_field_t;

typedef struct stc_gpio_pdor2_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  RESERVED0                :21;
} stc_gpio_pdor2_field_t;

typedef struct stc_gpio_pdor3_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  RESERVED0                :17;
} stc_gpio_pdor3_field_t;

typedef struct stc_gpio_pdor4_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  RESERVED0                :22;
} stc_gpio_pdor4_field_t;

typedef struct stc_gpio_pdor5_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  RESERVED0                :10;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  PF                       :1;
        __IO  uint32_t  RESERVED1                :16;
} stc_gpio_pdor5_field_t;

typedef struct stc_gpio_pdor6_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  RESERVED0                :8;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  RESERVED1                :17;
} stc_gpio_pdor6_field_t;

typedef struct stc_gpio_pdor7_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  RESERVED0                :17;
} stc_gpio_pdor7_field_t;

typedef struct stc_gpio_pdor8_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  RESERVED0                :28;
} stc_gpio_pdor8_field_t;

typedef struct stc_gpio_pdor9_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  RESERVED0                :26;
} stc_gpio_pdor9_field_t;

typedef struct stc_gpio_pdora_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  PF                       :1;
        __IO  uint32_t  RESERVED0                :16;
} stc_gpio_pdora_field_t;

typedef struct stc_gpio_pdorb_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  RESERVED0                :24;
} stc_gpio_pdorb_field_t;

typedef struct stc_gpio_pdorc_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  PF                       :1;
        __IO  uint32_t  RESERVED0                :16;
} stc_gpio_pdorc_field_t;

typedef struct stc_gpio_pdord_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  RESERVED0                :29;
} stc_gpio_pdord_field_t;

typedef struct stc_gpio_pdore_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  RESERVED0                :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  RESERVED1                :28;
} stc_gpio_pdore_field_t;

typedef struct stc_gpio_pdorf_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  RESERVED0                :24;
} stc_gpio_pdorf_field_t;

typedef struct stc_gpio_ade_field
{
        __IO  uint32_t  AN00                     :1;
        __IO  uint32_t  AN01                     :1;
        __IO  uint32_t  AN02                     :1;
        __IO  uint32_t  AN03                     :1;
        __IO  uint32_t  AN04                     :1;
        __IO  uint32_t  AN05                     :1;
        __IO  uint32_t  AN06                     :1;
        __IO  uint32_t  AN07                     :1;
        __IO  uint32_t  AN08                     :1;
        __IO  uint32_t  AN09                     :1;
        __IO  uint32_t  AN10                     :1;
        __IO  uint32_t  AN11                     :1;
        __IO  uint32_t  AN12                     :1;
        __IO  uint32_t  AN13                     :1;
        __IO  uint32_t  AN14                     :1;
        __IO  uint32_t  AN15                     :1;
        __IO  uint32_t  AN16                     :1;
        __IO  uint32_t  AN17                     :1;
        __IO  uint32_t  AN18                     :1;
        __IO  uint32_t  AN19                     :1;
        __IO  uint32_t  AN20                     :1;
        __IO  uint32_t  AN21                     :1;
        __IO  uint32_t  AN22                     :1;
        __IO  uint32_t  AN23                     :1;
        __IO  uint32_t  AN24                     :1;
        __IO  uint32_t  AN25                     :1;
        __IO  uint32_t  AN26                     :1;
        __IO  uint32_t  AN27                     :1;
        __IO  uint32_t  AN28                     :1;
        __IO  uint32_t  AN29                     :1;
        __IO  uint32_t  AN30                     :1;
        __IO  uint32_t  AN31                     :1;
} stc_gpio_ade_field_t;

typedef struct stc_gpio_spsr_field
{
    union {
        struct {
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  MAINXC               :2;
            __IO  uint32_t  USB0C                :1;
            __IO  uint32_t  USB1C                :1;
            __IO  uint32_t  RESERVED2            :26;
        };
        struct {
            __IO  uint32_t  RESERVED1            :2;
            __IO  uint32_t  MAINXC0              :1;
            __IO  uint32_t  MAINXC1              :1;
            __IO  uint32_t  RESERVED3            :28;
        };
    };
} stc_gpio_spsr_field_t;

typedef struct stc_gpio_epfr00_field
{
    union {
        struct {
            __IO  uint32_t  NMIS                 :1;
            __IO  uint32_t  CROUTE               :2;
            __IO  uint32_t  RESERVED1            :1;
            __IO  uint32_t  RTCCOE               :2;
            __IO  uint32_t  SUBOUTE              :2;
            __IO  uint32_t  RESERVED3            :1;
            __IO  uint32_t  USBP0E               :1;
            __IO  uint32_t  RESERVED4            :3;
            __IO  uint32_t  USBP1E               :1;
            __IO  uint32_t  RESERVED5            :2;
            __IO  uint32_t  JTAGEN0B             :1;
            __IO  uint32_t  JTAGEN1S             :1;
            __IO  uint32_t  RESERVED6            :6;
            __IO  uint32_t  TRC0E                :1;
            __IO  uint32_t  TRC1E                :1;
            __IO  uint32_t  TRC2E                :1;
            __IO  uint32_t  TRC3E                :1;
            __IO  uint32_t  RESERVED7            :4;
        };
        struct {
            __IO  uint32_t  RESERVED0            :1;
            __IO  uint32_t  CROUTE0              :1;
            __IO  uint32_t  CROUTE1              :1;
            __IO  uint32_t  RESERVED2            :1;
            __IO  uint32_t  RTCCOE0              :1;
            __IO  uint32_t  RTCCOE1              :1;
            __IO  uint32_t  SUBOUTE0             :1;
            __IO  uint32_t  SUBOUTE1             :1;
            __IO  uint32_t  RESERVED8            :24;
        };
    };
} stc_gpio_epfr00_field_t;

typedef struct stc_gpio_epfr01_field
{
    union {
        struct {
            __IO  uint32_t  RTO00E               :2;
            __IO  uint32_t  RTO01E               :2;
            __IO  uint32_t  RTO02E               :2;
            __IO  uint32_t  RTO03E               :2;
            __IO  uint32_t  RTO04E               :2;
            __IO  uint32_t  RTO05E               :2;
            __IO  uint32_t  DTTI0C               :1;
            __IO  uint32_t  RESERVED0            :3;
            __IO  uint32_t  DTTI0S               :2;
            __IO  uint32_t  FRCK0S               :2;
            __IO  uint32_t  IC00S                :3;
            __IO  uint32_t  IC01S                :3;
            __IO  uint32_t  IC02S                :3;
            __IO  uint32_t  IC03S                :3;
        };
        struct {
            __IO  uint32_t  RTO00E0              :1;
            __IO  uint32_t  RTO00E1              :1;
            __IO  uint32_t  RTO01E0              :1;
            __IO  uint32_t  RTO01E1              :1;
            __IO  uint32_t  RTO02E0              :1;
            __IO  uint32_t  RTO02E1              :1;
            __IO  uint32_t  RTO03E0              :1;
            __IO  uint32_t  RTO03E1              :1;
            __IO  uint32_t  RTO04E0              :1;
            __IO  uint32_t  RTO04E1              :1;
            __IO  uint32_t  RTO05E0              :1;
            __IO  uint32_t  RTO05E1              :1;
            __IO  uint32_t  RESERVED1            :4;
            __IO  uint32_t  DTTI0S0              :1;
            __IO  uint32_t  DTTI0S1              :1;
            __IO  uint32_t  FRCK0S0              :1;
            __IO  uint32_t  FRCK0S1              :1;
            __IO  uint32_t  IC00S0               :1;
            __IO  uint32_t  IC00S1               :1;
            __IO  uint32_t  IC00S2               :1;
            __IO  uint32_t  IC01S0               :1;
            __IO  uint32_t  IC01S1               :1;
            __IO  uint32_t  IC01S2               :1;
            __IO  uint32_t  IC02S0               :1;
            __IO  uint32_t  IC02S1               :1;
            __IO  uint32_t  IC02S2               :1;
            __IO  uint32_t  IC03S0               :1;
            __IO  uint32_t  IC03S1               :1;
            __IO  uint32_t  IC03S2               :1;
        };
    };
} stc_gpio_epfr01_field_t;

typedef struct stc_gpio_epfr02_field
{
    union {
        struct {
            __IO  uint32_t  RTO10E               :2;
            __IO  uint32_t  RTO11E               :2;
            __IO  uint32_t  RTO12E               :2;
            __IO  uint32_t  RTO13E               :2;
            __IO  uint32_t  RTO14E               :2;
            __IO  uint32_t  RTO15E               :2;
            __IO  uint32_t  DTTI1C               :1;
            __IO  uint32_t  RESERVED0            :3;
            __IO  uint32_t  DTTI1S               :2;
            __IO  uint32_t  FRCK1S               :2;
            __IO  uint32_t  IC10S                :3;
            __IO  uint32_t  IC11S                :3;
            __IO  uint32_t  IC12S                :3;
            __IO  uint32_t  IC13S                :3;
        };
        struct {
            __IO  uint32_t  RTO10E0              :1;
            __IO  uint32_t  RTO10E1              :1;
            __IO  uint32_t  RTO11E0              :1;
            __IO  uint32_t  RTO11E1              :1;
            __IO  uint32_t  RTO12E0              :1;
            __IO  uint32_t  RTO12E1              :1;
            __IO  uint32_t  RTO13E0              :1;
            __IO  uint32_t  RTO13E1              :1;
            __IO  uint32_t  RTO14E0              :1;
            __IO  uint32_t  RTO14E1              :1;
            __IO  uint32_t  RTO15E0              :1;
            __IO  uint32_t  RTO15E1              :1;
            __IO  uint32_t  RESERVED1            :4;
            __IO  uint32_t  DTTI1S0              :1;
            __IO  uint32_t  DTTI1S1              :1;
            __IO  uint32_t  FRCK1S0              :1;
            __IO  uint32_t  FRCK1S1              :1;
            __IO  uint32_t  IC10S0               :1;
            __IO  uint32_t  IC10S1               :1;
            __IO  uint32_t  IC10S2               :1;
            __IO  uint32_t  IC11S0               :1;
            __IO  uint32_t  IC11S1               :1;
            __IO  uint32_t  IC11S2               :1;
            __IO  uint32_t  IC12S0               :1;
            __IO  uint32_t  IC12S1               :1;
            __IO  uint32_t  IC12S2               :1;
            __IO  uint32_t  IC13S0               :1;
            __IO  uint32_t  IC13S1               :1;
            __IO  uint32_t  IC13S2               :1;
        };
    };
} stc_gpio_epfr02_field_t;

typedef struct stc_gpio_epfr03_field
{
    union {
        struct {
            __IO  uint32_t  RTO20E               :2;
            __IO  uint32_t  RTO21E               :2;
            __IO  uint32_t  RTO22E               :2;
            __IO  uint32_t  RTO23E               :2;
            __IO  uint32_t  RTO24E               :2;
            __IO  uint32_t  RTO25E               :2;
            __IO  uint32_t  DTTI2C               :1;
            __IO  uint32_t  RESERVED0            :3;
            __IO  uint32_t  DTTI2S               :2;
            __IO  uint32_t  FRCK2S               :2;
            __IO  uint32_t  IC20S                :3;
            __IO  uint32_t  IC21S                :3;
            __IO  uint32_t  IC22S                :3;
            __IO  uint32_t  IC23S                :3;
        };
        struct {
            __IO  uint32_t  RTO20E0              :1;
            __IO  uint32_t  RTO20E1              :1;
            __IO  uint32_t  RTO21E0              :1;
            __IO  uint32_t  RTO21E1              :1;
            __IO  uint32_t  RTO22E0              :1;
            __IO  uint32_t  RTO22E1              :1;
            __IO  uint32_t  RTO23E0              :1;
            __IO  uint32_t  RTO23E1              :1;
            __IO  uint32_t  RTO24E0              :1;
            __IO  uint32_t  RTO24E1              :1;
            __IO  uint32_t  RTO25E0              :1;
            __IO  uint32_t  RTO25E1              :1;
            __IO  uint32_t  RESERVED1            :4;
            __IO  uint32_t  DTTI2S0              :1;
            __IO  uint32_t  DTTI2S1              :1;
            __IO  uint32_t  FRCK2S0              :1;
            __IO  uint32_t  FRCK2S1              :1;
            __IO  uint32_t  IC20S0               :1;
            __IO  uint32_t  IC20S1               :1;
            __IO  uint32_t  IC20S2               :1;
            __IO  uint32_t  IC21S0               :1;
            __IO  uint32_t  IC21S1               :1;
            __IO  uint32_t  IC21S2               :1;
            __IO  uint32_t  IC22S0               :1;
            __IO  uint32_t  IC22S1               :1;
            __IO  uint32_t  IC22S2               :1;
            __IO  uint32_t  IC23S0               :1;
            __IO  uint32_t  IC23S1               :1;
            __IO  uint32_t  IC23S2               :1;
        };
    };
} stc_gpio_epfr03_field_t;

typedef struct stc_gpio_epfr04_field
{
    union {
        struct {
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  TIOA0E               :2;
            __IO  uint32_t  TIOB0S               :3;
            __IO  uint32_t  RESERVED2            :1;
            __IO  uint32_t  TIOA1S               :2;
            __IO  uint32_t  TIOA1E               :2;
            __IO  uint32_t  TIOB1S               :2;
            __IO  uint32_t  RESERVED4            :4;
            __IO  uint32_t  TIOA2E               :2;
            __IO  uint32_t  TIOB2S               :2;
            __IO  uint32_t  RESERVED6            :2;
            __IO  uint32_t  TIOA3S               :2;
            __IO  uint32_t  TIOA3E               :2;
            __IO  uint32_t  TIOB3S               :2;
            __IO  uint32_t  RESERVED8            :2;
        };
        struct {
            __IO  uint32_t  RESERVED1            :2;
            __IO  uint32_t  TIOA0E0              :1;
            __IO  uint32_t  TIOA0E1              :1;
            __IO  uint32_t  TIOB0S0              :1;
            __IO  uint32_t  TIOB0S1              :1;
            __IO  uint32_t  TIOB0S2              :1;
            __IO  uint32_t  RESERVED3            :1;
            __IO  uint32_t  TIOA1S0              :1;
            __IO  uint32_t  TIOA1S1              :1;
            __IO  uint32_t  TIOA1E0              :1;
            __IO  uint32_t  TIOA1E1              :1;
            __IO  uint32_t  TIOB1S0              :1;
            __IO  uint32_t  TIOB1S1              :1;
            __IO  uint32_t  RESERVED5            :4;
            __IO  uint32_t  TIOA2E0              :1;
            __IO  uint32_t  TIOA2E1              :1;
            __IO  uint32_t  TIOB2S0              :1;
            __IO  uint32_t  TIOB2S1              :1;
            __IO  uint32_t  RESERVED7            :2;
            __IO  uint32_t  TIOA3S0              :1;
            __IO  uint32_t  TIOA3S1              :1;
            __IO  uint32_t  TIOA3E0              :1;
            __IO  uint32_t  TIOA3E1              :1;
            __IO  uint32_t  TIOB3S0              :1;
            __IO  uint32_t  TIOB3S1              :1;
            __IO  uint32_t  RESERVED9            :2;
        };
    };
} stc_gpio_epfr04_field_t;

typedef struct stc_gpio_epfr05_field
{
    union {
        struct {
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  TIOA4E               :2;
            __IO  uint32_t  TIOB4S               :2;
            __IO  uint32_t  RESERVED2            :2;
            __IO  uint32_t  TIOA5S               :2;
            __IO  uint32_t  TIOA5E               :2;
            __IO  uint32_t  TIOB5S               :2;
            __IO  uint32_t  RESERVED4            :4;
            __IO  uint32_t  TIOA6E               :2;
            __IO  uint32_t  TIOB6S               :2;
            __IO  uint32_t  RESERVED6            :2;
            __IO  uint32_t  TIOA7S               :2;
            __IO  uint32_t  TIOA7E               :2;
            __IO  uint32_t  TIOB7S               :2;
            __IO  uint32_t  RESERVED8            :2;
        };
        struct {
            __IO  uint32_t  RESERVED1            :2;
            __IO  uint32_t  TIOA4E0              :1;
            __IO  uint32_t  TIOA4E1              :1;
            __IO  uint32_t  TIOB4S0              :1;
            __IO  uint32_t  TIOB4S1              :1;
            __IO  uint32_t  RESERVED3            :2;
            __IO  uint32_t  TIOA5S0              :1;
            __IO  uint32_t  TIOA5S1              :1;
            __IO  uint32_t  TIOA5E0              :1;
            __IO  uint32_t  TIOA5E1              :1;
            __IO  uint32_t  TIOB5S0              :1;
            __IO  uint32_t  TIOB5S1              :1;
            __IO  uint32_t  RESERVED5            :4;
            __IO  uint32_t  TIOA6E0              :1;
            __IO  uint32_t  TIOA6E1              :1;
            __IO  uint32_t  TIOB6S0              :1;
            __IO  uint32_t  TIOB6S1              :1;
            __IO  uint32_t  RESERVED7            :2;
            __IO  uint32_t  TIOA7S0              :1;
            __IO  uint32_t  TIOA7S1              :1;
            __IO  uint32_t  TIOA7E0              :1;
            __IO  uint32_t  TIOA7E1              :1;
            __IO  uint32_t  TIOB7S0              :1;
            __IO  uint32_t  TIOB7S1              :1;
            __IO  uint32_t  RESERVED9            :2;
        };
    };
} stc_gpio_epfr05_field_t;

typedef struct stc_gpio_epfr06_field
{
    union {
        struct {
            __IO  uint32_t  EINT00S              :2;
            __IO  uint32_t  EINT01S              :2;
            __IO  uint32_t  EINT02S              :2;
            __IO  uint32_t  EINT03S              :2;
            __IO  uint32_t  EINT04S              :2;
            __IO  uint32_t  EINT05S              :2;
            __IO  uint32_t  EINT06S              :2;
            __IO  uint32_t  EINT07S              :2;
            __IO  uint32_t  EINT08S              :2;
            __IO  uint32_t  EINT09S              :2;
            __IO  uint32_t  EINT10S              :2;
            __IO  uint32_t  EINT11S              :2;
            __IO  uint32_t  EINT12S              :2;
            __IO  uint32_t  EINT13S              :2;
            __IO  uint32_t  EINT14S              :2;
            __IO  uint32_t  EINT15S              :2;
        };
        struct {
            __IO  uint32_t  EINT00S0             :1;
            __IO  uint32_t  EINT00S1             :1;
            __IO  uint32_t  EINT01S0             :1;
            __IO  uint32_t  EINT01S1             :1;
            __IO  uint32_t  EINT02S0             :1;
            __IO  uint32_t  EINT02S1             :1;
            __IO  uint32_t  EINT03S0             :1;
            __IO  uint32_t  EINT03S1             :1;
            __IO  uint32_t  EINT04S0             :1;
            __IO  uint32_t  EINT04S1             :1;
            __IO  uint32_t  EINT05S0             :1;
            __IO  uint32_t  EINT05S1             :1;
            __IO  uint32_t  EINT06S0             :1;
            __IO  uint32_t  EINT06S1             :1;
            __IO  uint32_t  EINT07S0             :1;
            __IO  uint32_t  EINT07S1             :1;
            __IO  uint32_t  EINT08S0             :1;
            __IO  uint32_t  EINT08S1             :1;
            __IO  uint32_t  EINT09S0             :1;
            __IO  uint32_t  EINT09S1             :1;
            __IO  uint32_t  EINT10S0             :1;
            __IO  uint32_t  EINT10S1             :1;
            __IO  uint32_t  EINT11S0             :1;
            __IO  uint32_t  EINT11S1             :1;
            __IO  uint32_t  EINT12S0             :1;
            __IO  uint32_t  EINT12S1             :1;
            __IO  uint32_t  EINT13S0             :1;
            __IO  uint32_t  EINT13S1             :1;
            __IO  uint32_t  EINT14S0             :1;
            __IO  uint32_t  EINT14S1             :1;
            __IO  uint32_t  EINT15S0             :1;
            __IO  uint32_t  EINT15S1             :1;
        };
    };
} stc_gpio_epfr06_field_t;

typedef struct stc_gpio_epfr07_field
{
    union {
        struct {
            __IO  uint32_t  RESERVED0            :4;
            __IO  uint32_t  SIN0S                :2;
            __IO  uint32_t  SOT0B                :2;
            __IO  uint32_t  SCK0B                :2;
            __IO  uint32_t  SIN1S                :2;
            __IO  uint32_t  SOT1B                :2;
            __IO  uint32_t  SCK1B                :2;
            __IO  uint32_t  SIN2S                :2;
            __IO  uint32_t  SOT2B                :2;
            __IO  uint32_t  SCK2B                :2;
            __IO  uint32_t  SIN3S                :2;
            __IO  uint32_t  SOT3B                :2;
            __IO  uint32_t  SCK3B                :2;
            __IO  uint32_t  RESERVED2            :4;
        };
        struct {
            __IO  uint32_t  RESERVED1            :4;
            __IO  uint32_t  SIN0S0               :1;
            __IO  uint32_t  SIN0S1               :1;
            __IO  uint32_t  SOT0B0               :1;
            __IO  uint32_t  SOT0B1               :1;
            __IO  uint32_t  SCK0B0               :1;
            __IO  uint32_t  SCK0B1               :1;
            __IO  uint32_t  SIN1S0               :1;
            __IO  uint32_t  SIN1S1               :1;
            __IO  uint32_t  SOT1B0               :1;
            __IO  uint32_t  SOT1B1               :1;
            __IO  uint32_t  SCK1B0               :1;
            __IO  uint32_t  SCK1B1               :1;
            __IO  uint32_t  SIN2S0               :1;
            __IO  uint32_t  SIN2S1               :1;
            __IO  uint32_t  SOT2B0               :1;
            __IO  uint32_t  SOT2B1               :1;
            __IO  uint32_t  SCK2B0               :1;
            __IO  uint32_t  SCK2B1               :1;
            __IO  uint32_t  SIN3S0               :1;
            __IO  uint32_t  SIN3S1               :1;
            __IO  uint32_t  SOT3B0               :1;
            __IO  uint32_t  SOT3B1               :1;
            __IO  uint32_t  SCK3B0               :1;
            __IO  uint32_t  SCK3B1               :1;
            __IO  uint32_t  RESERVED3            :4;
        };
    };
} stc_gpio_epfr07_field_t;

typedef struct stc_gpio_epfr08_field
{
    union {
        struct {
            __IO  uint32_t  RTS4E                :2;
            __IO  uint32_t  CTS4S                :2;
            __IO  uint32_t  SIN4S                :2;
            __IO  uint32_t  SOT4B                :2;
            __IO  uint32_t  SCK4B                :2;
            __IO  uint32_t  SIN5S                :2;
            __IO  uint32_t  SOT5B                :2;
            __IO  uint32_t  SCK5B                :2;
            __IO  uint32_t  SIN6S                :2;
            __IO  uint32_t  SOT6B                :2;
            __IO  uint32_t  SCK6B                :2;
            __IO  uint32_t  SIN7S                :2;
            __IO  uint32_t  SOT7B                :2;
            __IO  uint32_t  SCK7B                :2;
            __IO  uint32_t  RTS5E                :2;
            __IO  uint32_t  CTS5S                :2;
        };
        struct {
            __IO  uint32_t  RTS4E0               :1;
            __IO  uint32_t  RTS4E1               :1;
            __IO  uint32_t  CTS4S0               :1;
            __IO  uint32_t  CTS4S1               :1;
            __IO  uint32_t  SIN4S0               :1;
            __IO  uint32_t  SIN4S1               :1;
            __IO  uint32_t  SOT4B0               :1;
            __IO  uint32_t  SOT4B1               :1;
            __IO  uint32_t  SCK4B0               :1;
            __IO  uint32_t  SCK4B1               :1;
            __IO  uint32_t  SIN5S0               :1;
            __IO  uint32_t  SIN5S1               :1;
            __IO  uint32_t  SOT5B0               :1;
            __IO  uint32_t  SOT5B1               :1;
            __IO  uint32_t  SCK5B0               :1;
            __IO  uint32_t  SCK5B1               :1;
            __IO  uint32_t  SIN6S0               :1;
            __IO  uint32_t  SIN6S1               :1;
            __IO  uint32_t  SOT6B0               :1;
            __IO  uint32_t  SOT6B1               :1;
            __IO  uint32_t  SCK6B0               :1;
            __IO  uint32_t  SCK6B1               :1;
            __IO  uint32_t  SIN7S0               :1;
            __IO  uint32_t  SIN7S1               :1;
            __IO  uint32_t  SOT7B0               :1;
            __IO  uint32_t  SOT7B1               :1;
            __IO  uint32_t  SCK7B0               :1;
            __IO  uint32_t  SCK7B1               :1;
            __IO  uint32_t  RTS5E0               :1;
            __IO  uint32_t  RTS5E1               :1;
            __IO  uint32_t  CTS5S0               :1;
            __IO  uint32_t  CTS5S1               :1;
        };
    };
} stc_gpio_epfr08_field_t;

typedef struct stc_gpio_epfr09_field
{
    union {
        struct {
            __IO  uint32_t  QAIN0S               :2;
            __IO  uint32_t  QBIN0S               :2;
            __IO  uint32_t  QZIN0S               :2;
            __IO  uint32_t  QAIN1S               :2;
            __IO  uint32_t  QBIN1S               :2;
            __IO  uint32_t  QZIN1S               :2;
            __IO  uint32_t  ADTRG0S              :4;
            __IO  uint32_t  ADTRG1S              :4;
            __IO  uint32_t  ADTRG2S              :4;
            __IO  uint32_t  CRX0S                :2;
            __IO  uint32_t  CTX0E                :2;
            __IO  uint32_t  CRX1S                :2;
            __IO  uint32_t  CTX1E                :2;
        };
        struct {
            __IO  uint32_t  QAIN0S0              :1;
            __IO  uint32_t  QAIN0S1              :1;
            __IO  uint32_t  QBIN0S0              :1;
            __IO  uint32_t  QBIN0S1              :1;
            __IO  uint32_t  QZIN0S0              :1;
            __IO  uint32_t  QZIN0S1              :1;
            __IO  uint32_t  QAIN1S0              :1;
            __IO  uint32_t  QAIN1S1              :1;
            __IO  uint32_t  QBIN1S0              :1;
            __IO  uint32_t  QBIN1S1              :1;
            __IO  uint32_t  QZIN1S0              :1;
            __IO  uint32_t  QZIN1S1              :1;
            __IO  uint32_t  ADTRG0S0             :1;
            __IO  uint32_t  ADTRG0S1             :1;
            __IO  uint32_t  ADTRG0S2             :1;
            __IO  uint32_t  ADTRG0S3             :1;
            __IO  uint32_t  ADTRG1S0             :1;
            __IO  uint32_t  ADTRG1S1             :1;
            __IO  uint32_t  ADTRG1S2             :1;
            __IO  uint32_t  ADTRG1S3             :1;
            __IO  uint32_t  ADTRG2S0             :1;
            __IO  uint32_t  ADTRG2S1             :1;
            __IO  uint32_t  ADTRG2S2             :1;
            __IO  uint32_t  ADTRG2S3             :1;
            __IO  uint32_t  CRX0S0               :1;
            __IO  uint32_t  CRX0S1               :1;
            __IO  uint32_t  CTX0E0               :1;
            __IO  uint32_t  CTX0E1               :1;
            __IO  uint32_t  CRX1S0               :1;
            __IO  uint32_t  CRX1S1               :1;
            __IO  uint32_t  CTX1E0               :1;
            __IO  uint32_t  CTX1E1               :1;
        };
    };
} stc_gpio_epfr09_field_t;

typedef struct stc_gpio_epfr10_field
{
        __IO  uint32_t  UEDEFB                   :1;
        __IO  uint32_t  UEDTHB                   :1;
        __IO  uint32_t  UECLKE                   :1;
        __IO  uint32_t  UEWEXE                   :1;
        __IO  uint32_t  UEDQME                   :1;
        __IO  uint32_t  UEOEXE                   :1;
        __IO  uint32_t  UEFLSE                   :1;
        __IO  uint32_t  UECS1E                   :1;
        __IO  uint32_t  UECS2E                   :1;
        __IO  uint32_t  UECS3E                   :1;
        __IO  uint32_t  UECS4E                   :1;
        __IO  uint32_t  UECS5E                   :1;
        __IO  uint32_t  UECS6E                   :1;
        __IO  uint32_t  UECS7E                   :1;
        __IO  uint32_t  UEAOOE                   :1;
        __IO  uint32_t  UEA08E                   :1;
        __IO  uint32_t  UEA09E                   :1;
        __IO  uint32_t  UEA10E                   :1;
        __IO  uint32_t  UEA11E                   :1;
        __IO  uint32_t  UEA12E                   :1;
        __IO  uint32_t  UEA13E                   :1;
        __IO  uint32_t  UEA14E                   :1;
        __IO  uint32_t  UEA15E                   :1;
        __IO  uint32_t  UEA16E                   :1;
        __IO  uint32_t  UEA17E                   :1;
        __IO  uint32_t  UEA18E                   :1;
        __IO  uint32_t  UEA19E                   :1;
        __IO  uint32_t  UEA20E                   :1;
        __IO  uint32_t  UEA21E                   :1;
        __IO  uint32_t  UEA22E                   :1;
        __IO  uint32_t  UEA23E                   :1;
        __IO  uint32_t  UEA24E                   :1;
} stc_gpio_epfr10_field_t;

typedef struct stc_gpio_epfr11_field
{
        __IO  uint32_t  UEALEE                   :1;
        __IO  uint32_t  UECS0E                   :1;
        __IO  uint32_t  UEA01E                   :1;
        __IO  uint32_t  UEA02E                   :1;
        __IO  uint32_t  UEA03E                   :1;
        __IO  uint32_t  UEA04E                   :1;
        __IO  uint32_t  UEA05E                   :1;
        __IO  uint32_t  UEA06E                   :1;
        __IO  uint32_t  UEA07E                   :1;
        __IO  uint32_t  UED00B                   :1;
        __IO  uint32_t  UED01B                   :1;
        __IO  uint32_t  UED02B                   :1;
        __IO  uint32_t  UED03B                   :1;
        __IO  uint32_t  UED04B                   :1;
        __IO  uint32_t  UED05B                   :1;
        __IO  uint32_t  UED06B                   :1;
        __IO  uint32_t  UED07B                   :1;
        __IO  uint32_t  UED08B                   :1;
        __IO  uint32_t  UED09B                   :1;
        __IO  uint32_t  UED10B                   :1;
        __IO  uint32_t  UED11B                   :1;
        __IO  uint32_t  UED12B                   :1;
        __IO  uint32_t  UED13B                   :1;
        __IO  uint32_t  UED14B                   :1;
        __IO  uint32_t  UED15B                   :1;
        __IO  uint32_t  UERLC                    :1;
        __IO  uint32_t  RESERVED0                :6;
} stc_gpio_epfr11_field_t;

typedef struct stc_gpio_epfr12_field
{
    union {
        struct {
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  TIOA8E               :2;
            __IO  uint32_t  TIOB8S               :2;
            __IO  uint32_t  RESERVED2            :2;
            __IO  uint32_t  TIOA9S               :2;
            __IO  uint32_t  TIOA9E               :2;
            __IO  uint32_t  TIOB9S               :2;
            __IO  uint32_t  RESERVED4            :4;
            __IO  uint32_t  TIOA10E              :2;
            __IO  uint32_t  TIOB10S              :2;
            __IO  uint32_t  RESERVED6            :2;
            __IO  uint32_t  TIOA11S              :2;
            __IO  uint32_t  TIOA11E              :2;
            __IO  uint32_t  TIOB11S              :2;
            __IO  uint32_t  RESERVED8            :2;
        };
        struct {
            __IO  uint32_t  RESERVED1            :2;
            __IO  uint32_t  TIOA8E0              :1;
            __IO  uint32_t  TIOA8E1              :1;
            __IO  uint32_t  TIOB8S0              :1;
            __IO  uint32_t  TIOB8S1              :1;
            __IO  uint32_t  RESERVED3            :2;
            __IO  uint32_t  TIOA9S0              :1;
            __IO  uint32_t  TIOA9S1              :1;
            __IO  uint32_t  TIOA9E0              :1;
            __IO  uint32_t  TIOA9E1              :1;
            __IO  uint32_t  TIOB9S0              :1;
            __IO  uint32_t  TIOB9S1              :1;
            __IO  uint32_t  RESERVED5            :4;
            __IO  uint32_t  TIOA10E0             :1;
            __IO  uint32_t  TIOA10E1             :1;
            __IO  uint32_t  TIOB10S0             :1;
            __IO  uint32_t  TIOB10S1             :1;
            __IO  uint32_t  RESERVED7            :2;
            __IO  uint32_t  TIOA11S0             :1;
            __IO  uint32_t  TIOA11S1             :1;
            __IO  uint32_t  TIOA11E0             :1;
            __IO  uint32_t  TIOA11E1             :1;
            __IO  uint32_t  TIOB11S0             :1;
            __IO  uint32_t  TIOB11S1             :1;
            __IO  uint32_t  RESERVED9            :2;
        };
    };
} stc_gpio_epfr12_field_t;

typedef struct stc_gpio_epfr13_field
{
    union {
        struct {
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  TIOA12E              :2;
            __IO  uint32_t  TIOB12S              :2;
            __IO  uint32_t  RESERVED2            :2;
            __IO  uint32_t  TIOA13S              :2;
            __IO  uint32_t  TIOA13E              :2;
            __IO  uint32_t  TIOB13S              :2;
            __IO  uint32_t  RESERVED4            :4;
            __IO  uint32_t  TIOA14E              :2;
            __IO  uint32_t  TIOB14S              :2;
            __IO  uint32_t  RESERVED6            :2;
            __IO  uint32_t  TIOA15S              :2;
            __IO  uint32_t  TIOA15E              :2;
            __IO  uint32_t  TIOB15S              :2;
            __IO  uint32_t  RESERVED8            :2;
        };
        struct {
            __IO  uint32_t  RESERVED1            :2;
            __IO  uint32_t  TIOA12E0             :1;
            __IO  uint32_t  TIOA12E1             :1;
            __IO  uint32_t  TIOB12S0             :1;
            __IO  uint32_t  TIOB12S1             :1;
            __IO  uint32_t  RESERVED3            :2;
            __IO  uint32_t  TIOA13S0             :1;
            __IO  uint32_t  TIOA13S1             :1;
            __IO  uint32_t  TIOA13E0             :1;
            __IO  uint32_t  TIOA13E1             :1;
            __IO  uint32_t  TIOB13S0             :1;
            __IO  uint32_t  TIOB13S1             :1;
            __IO  uint32_t  RESERVED5            :4;
            __IO  uint32_t  TIOA14E0             :1;
            __IO  uint32_t  TIOA14E1             :1;
            __IO  uint32_t  TIOB14S0             :1;
            __IO  uint32_t  TIOB14S1             :1;
            __IO  uint32_t  RESERVED7            :2;
            __IO  uint32_t  TIOA15S0             :1;
            __IO  uint32_t  TIOA15S1             :1;
            __IO  uint32_t  TIOA15E0             :1;
            __IO  uint32_t  TIOA15E1             :1;
            __IO  uint32_t  TIOB15S0             :1;
            __IO  uint32_t  TIOB15S1             :1;
            __IO  uint32_t  RESERVED9            :2;
        };
    };
} stc_gpio_epfr13_field_t;

typedef struct stc_gpio_epfr14_field
{
    union {
        struct {
            __IO  uint32_t  QAIN2S               :2;
            __IO  uint32_t  QBIN2S               :2;
            __IO  uint32_t  QZIN2S               :2;
            __IO  uint32_t  RESERVED0            :12;
            __IO  uint32_t  E_TD0E               :1;
            __IO  uint32_t  E_TD1E               :1;
            __IO  uint32_t  E_TE0E               :1;
            __IO  uint32_t  E_TE1E               :1;
            __IO  uint32_t  E_MC0E               :1;
            __IO  uint32_t  E_MC1B               :1;
            __IO  uint32_t  E_MD0B               :1;
            __IO  uint32_t  E_MD1B               :1;
            __IO  uint32_t  E_CKE                :1;
            __IO  uint32_t  E_PSE                :1;
            __IO  uint32_t  E_SPLC               :2;
            __IO  uint32_t  RESERVED2            :2;
        };
        struct {
            __IO  uint32_t  QAIN2S0              :1;
            __IO  uint32_t  QAIN2S1              :1;
            __IO  uint32_t  QBIN2S0              :1;
            __IO  uint32_t  QBIN2S1              :1;
            __IO  uint32_t  QZIN2S0              :1;
            __IO  uint32_t  QZIN2S1              :1;
            __IO  uint32_t  RESERVED1            :22;
            __IO  uint32_t  E_SPLC0              :1;
            __IO  uint32_t  E_SPLC1              :1;
            __IO  uint32_t  RESERVED3            :2;
        };
    };
} stc_gpio_epfr14_field_t;

typedef struct stc_gpio_epfr15_field
{
    union {
        struct {
            __IO  uint32_t  EINT16S              :2;
            __IO  uint32_t  EINT17S              :2;
            __IO  uint32_t  EINT18S              :2;
            __IO  uint32_t  EINT19S              :2;
            __IO  uint32_t  EINT20S              :2;
            __IO  uint32_t  EINT21S              :2;
            __IO  uint32_t  EINT22S              :2;
            __IO  uint32_t  EINT23S              :2;
            __IO  uint32_t  EINT24S              :2;
            __IO  uint32_t  EINT25S              :2;
            __IO  uint32_t  EINT26S              :2;
            __IO  uint32_t  EINT27S              :2;
            __IO  uint32_t  EINT28S              :2;
            __IO  uint32_t  EINT29S              :2;
            __IO  uint32_t  EINT30S              :2;
            __IO  uint32_t  EINT31S              :2;
        };
        struct {
            __IO  uint32_t  EINT16S0             :1;
            __IO  uint32_t  EINT16S1             :1;
            __IO  uint32_t  EINT17S0             :1;
            __IO  uint32_t  EINT17S1             :1;
            __IO  uint32_t  EINT18S0             :1;
            __IO  uint32_t  EINT18S1             :1;
            __IO  uint32_t  EINT19S0             :1;
            __IO  uint32_t  EINT19S1             :1;
            __IO  uint32_t  EINT20S0             :1;
            __IO  uint32_t  EINT20S1             :1;
            __IO  uint32_t  EINT21S0             :1;
            __IO  uint32_t  EINT21S1             :1;
            __IO  uint32_t  EINT22S0             :1;
            __IO  uint32_t  EINT22S1             :1;
            __IO  uint32_t  EINT23S0             :1;
            __IO  uint32_t  EINT23S1             :1;
            __IO  uint32_t  EINT24S0             :1;
            __IO  uint32_t  EINT24S1             :1;
            __IO  uint32_t  EINT25S0             :1;
            __IO  uint32_t  EINT25S1             :1;
            __IO  uint32_t  EINT26S0             :1;
            __IO  uint32_t  EINT26S1             :1;
            __IO  uint32_t  EINT27S0             :1;
            __IO  uint32_t  EINT27S1             :1;
            __IO  uint32_t  EINT28S0             :1;
            __IO  uint32_t  EINT28S1             :1;
            __IO  uint32_t  EINT29S0             :1;
            __IO  uint32_t  EINT29S1             :1;
            __IO  uint32_t  EINT30S0             :1;
            __IO  uint32_t  EINT30S1             :1;
            __IO  uint32_t  EINT31S0             :1;
            __IO  uint32_t  EINT31S1             :1;
        };
    };
} stc_gpio_epfr15_field_t;

typedef struct stc_gpio_epfr16_field
{
    union {
        struct {
            __IO  uint32_t  SCS6B                :2;
            __IO  uint32_t  SCS7B                :2;
            __IO  uint32_t  SIN8S                :2;
            __IO  uint32_t  SOT8B                :2;
            __IO  uint32_t  SCK8B                :2;
            __IO  uint32_t  SIN9S                :2;
            __IO  uint32_t  SOT9B                :2;
            __IO  uint32_t  SCK9B                :2;
            __IO  uint32_t  SIN10S               :2;
            __IO  uint32_t  SOT10B               :2;
            __IO  uint32_t  SCK10B               :2;
            __IO  uint32_t  SIN11S               :2;
            __IO  uint32_t  SOT11B               :2;
            __IO  uint32_t  SCK11B               :2;
            __IO  uint32_t  SFMPAC               :1;
            __IO  uint32_t  SFMPBC               :1;
            __IO  uint32_t  RESERVED0            :2;
        };
        struct {
            __IO  uint32_t  SCS6B0               :1;
            __IO  uint32_t  SCS6B1               :1;
            __IO  uint32_t  SCS7B0               :1;
            __IO  uint32_t  SCS7B1               :1;
            __IO  uint32_t  SIN8S0               :1;
            __IO  uint32_t  SIN8S1               :1;
            __IO  uint32_t  SOT8B0               :1;
            __IO  uint32_t  SOT8B1               :1;
            __IO  uint32_t  SCK8B0               :1;
            __IO  uint32_t  SCK8B1               :1;
            __IO  uint32_t  SIN9S0               :1;
            __IO  uint32_t  SIN9S1               :1;
            __IO  uint32_t  SOT9B0               :1;
            __IO  uint32_t  SOT9B1               :1;
            __IO  uint32_t  SCK9B0               :1;
            __IO  uint32_t  SCK9B1               :1;
            __IO  uint32_t  SIN10S0              :1;
            __IO  uint32_t  SIN10S1              :1;
            __IO  uint32_t  SOT10B0              :1;
            __IO  uint32_t  SOT10B1              :1;
            __IO  uint32_t  SCK10B0              :1;
            __IO  uint32_t  SCK10B1              :1;
            __IO  uint32_t  SIN11S0              :1;
            __IO  uint32_t  SIN11S1              :1;
            __IO  uint32_t  SOT11B0              :1;
            __IO  uint32_t  SOT11B1              :1;
            __IO  uint32_t  SCK11B0              :1;
            __IO  uint32_t  SCK11B1              :1;
            __IO  uint32_t  RESERVED1            :4;
        };
    };
} stc_gpio_epfr16_field_t;

typedef struct stc_gpio_epfr17_field
{
    union {
        struct {
            __IO  uint32_t  RESERVED0            :4;
            __IO  uint32_t  SIN12S               :2;
            __IO  uint32_t  SOT12B               :2;
            __IO  uint32_t  SCK12B               :2;
            __IO  uint32_t  SIN13S               :2;
            __IO  uint32_t  SOT13B               :2;
            __IO  uint32_t  SCK13B               :2;
            __IO  uint32_t  SIN14S               :2;
            __IO  uint32_t  SOT14B               :2;
            __IO  uint32_t  SCK14B               :2;
            __IO  uint32_t  SIN15S               :2;
            __IO  uint32_t  SOT15B               :2;
            __IO  uint32_t  SCK15B               :2;
            __IO  uint32_t  RESERVED2            :4;
        };
        struct {
            __IO  uint32_t  RESERVED1            :4;
            __IO  uint32_t  SIN12S0              :1;
            __IO  uint32_t  SIN12S1              :1;
            __IO  uint32_t  SOT12B0              :1;
            __IO  uint32_t  SOT12B1              :1;
            __IO  uint32_t  SCK12B0              :1;
            __IO  uint32_t  SCK12B1              :1;
            __IO  uint32_t  SIN13S0              :1;
            __IO  uint32_t  SIN13S1              :1;
            __IO  uint32_t  SOT13B0              :1;
            __IO  uint32_t  SOT13B1              :1;
            __IO  uint32_t  SCK13B0              :1;
            __IO  uint32_t  SCK13B1              :1;
            __IO  uint32_t  SIN14S0              :1;
            __IO  uint32_t  SIN14S1              :1;
            __IO  uint32_t  SOT14B0              :1;
            __IO  uint32_t  SOT14B1              :1;
            __IO  uint32_t  SCK14B0              :1;
            __IO  uint32_t  SCK14B1              :1;
            __IO  uint32_t  SIN15S0              :1;
            __IO  uint32_t  SIN15S1              :1;
            __IO  uint32_t  SOT15B0              :1;
            __IO  uint32_t  SOT15B1              :1;
            __IO  uint32_t  SCK15B0              :1;
            __IO  uint32_t  SCK15B1              :1;
            __IO  uint32_t  RESERVED3            :4;
        };
    };
} stc_gpio_epfr17_field_t;

typedef struct stc_gpio_epfr18_field
{
    union {
        struct {
            __IO  uint32_t  RESERVED0            :4;
            __IO  uint32_t  QAIN3S               :2;
            __IO  uint32_t  QBIN3S               :2;
            __IO  uint32_t  QZIN3S               :2;
            __IO  uint32_t  RESERVED2            :4;
            __IO  uint32_t  SDCLKE               :2;
            __IO  uint32_t  SDCMDB               :2;
            __IO  uint32_t  SDDATA0B             :2;
            __IO  uint32_t  SDDATA1B             :2;
            __IO  uint32_t  SDDATA2B             :2;
            __IO  uint32_t  SDDATA3B             :2;
            __IO  uint32_t  SDCDS                :2;
            __IO  uint32_t  SDWPS                :2;
            __IO  uint32_t  RESERVED4            :2;
        };
        struct {
            __IO  uint32_t  RESERVED1            :4;
            __IO  uint32_t  QAIN3S0              :1;
            __IO  uint32_t  QAIN3S1              :1;
            __IO  uint32_t  QBIN3S0              :1;
            __IO  uint32_t  QBIN3S1              :1;
            __IO  uint32_t  QZIN3S0              :1;
            __IO  uint32_t  QZIN3S1              :1;
            __IO  uint32_t  RESERVED3            :4;
            __IO  uint32_t  SDCLKE0              :1;
            __IO  uint32_t  SDCLKE1              :1;
            __IO  uint32_t  SDCMDB0              :1;
            __IO  uint32_t  SDCMDB1              :1;
            __IO  uint32_t  SDDATA0B0            :1;
            __IO  uint32_t  SDDATA0B1            :1;
            __IO  uint32_t  SDDATA1B0            :1;
            __IO  uint32_t  SDDATA1B1            :1;
            __IO  uint32_t  SDDATA2B0            :1;
            __IO  uint32_t  SDDATA2B1            :1;
            __IO  uint32_t  SDDATA3B0            :1;
            __IO  uint32_t  SDDATA3B1            :1;
            __IO  uint32_t  SDCDS0               :1;
            __IO  uint32_t  SDCDS1               :1;
            __IO  uint32_t  SDWPS0               :1;
            __IO  uint32_t  SDWPS1               :1;
            __IO  uint32_t  RESERVED5            :2;
        };
    };
} stc_gpio_epfr18_field_t;

typedef struct stc_gpio_epfr20_field
{
        __IO  uint32_t  UESMCKE                  :1;
        __IO  uint32_t  UESMCEE                  :1;
        __IO  uint32_t  UERASE                   :1;
        __IO  uint32_t  UECASE                   :1;
        __IO  uint32_t  UEDWEXE                  :1;
        __IO  uint32_t  UECSXE                   :1;
        __IO  uint32_t  UEDQM2E                  :1;
        __IO  uint32_t  UEDQM3E                  :1;
        __IO  uint32_t  UEDTHHB                  :1;
        __IO  uint32_t  UED16B                   :1;
        __IO  uint32_t  UED17B                   :1;
        __IO  uint32_t  UED18B                   :1;
        __IO  uint32_t  UED19B                   :1;
        __IO  uint32_t  UED20B                   :1;
        __IO  uint32_t  UED21B                   :1;
        __IO  uint32_t  UED22B                   :1;
        __IO  uint32_t  UED23B                   :1;
        __IO  uint32_t  UED24B                   :1;
        __IO  uint32_t  UED25B                   :1;
        __IO  uint32_t  UED26B                   :1;
        __IO  uint32_t  UED27B                   :1;
        __IO  uint32_t  UED28B                   :1;
        __IO  uint32_t  UED29B                   :1;
        __IO  uint32_t  UED30B                   :1;
        __IO  uint32_t  UED31B                   :1;
        __IO  uint32_t  RESERVED0                :7;
} stc_gpio_epfr20_field_t;

typedef struct stc_gpio_epfr23_field
{
    union {
        struct {
            __IO  uint32_t  SCS60E               :2;
            __IO  uint32_t  SCS61E               :2;
            __IO  uint32_t  SCS62E               :2;
            __IO  uint32_t  SCS63E               :2;
            __IO  uint32_t  SCS70E               :2;
            __IO  uint32_t  SCS71E               :2;
            __IO  uint32_t  SCS72E               :2;
            __IO  uint32_t  SCS73E               :2;
            __IO  uint32_t  RESERVED0            :16;
        };
        struct {
            __IO  uint32_t  SCS60E0              :1;
            __IO  uint32_t  SCS60E1              :1;
            __IO  uint32_t  SCS61E0              :1;
            __IO  uint32_t  SCS61E1              :1;
            __IO  uint32_t  SCS62E0              :1;
            __IO  uint32_t  SCS62E1              :1;
            __IO  uint32_t  SCS63E0              :1;
            __IO  uint32_t  SCS63E1              :1;
            __IO  uint32_t  SCS70E0              :1;
            __IO  uint32_t  SCS70E1              :1;
            __IO  uint32_t  SCS71E0              :1;
            __IO  uint32_t  SCS71E1              :1;
            __IO  uint32_t  SCS72E0              :1;
            __IO  uint32_t  SCS72E1              :1;
            __IO  uint32_t  SCS73E0              :1;
            __IO  uint32_t  SCS73E1              :1;
            __IO  uint32_t  RESERVED1            :16;
        };
    };
} stc_gpio_epfr23_field_t;

typedef struct stc_gpio_epfr24_field
{
    union {
        struct {
            __IO  uint32_t  I2SM4_MCLK0S         :2;
            __IO  uint32_t  I2SM4_MCLK0E         :2;
            __IO  uint32_t  I2SM4_SCK0B          :2;
            __IO  uint32_t  I2SM4_WS0B           :2;
            __IO  uint32_t  I2SM4_SDI0S          :2;
            __IO  uint32_t  I2SM4_SDO0E          :2;
            __IO  uint32_t  RESERVED0            :4;
            __IO  uint32_t  I2SM4_MCLK1S         :2;
            __IO  uint32_t  I2SM4_MCLK1E         :2;
            __IO  uint32_t  I2SM4_SCK1B          :2;
            __IO  uint32_t  I2SM4_WS1B           :2;
            __IO  uint32_t  I2SM4_SDI1S          :2;
            __IO  uint32_t  I2SM4_SDO1E          :2;
            __IO  uint32_t  RESERVED2            :4;
        };
        struct {
            __IO  uint32_t  I2SM4_MCLK0S0        :1;
            __IO  uint32_t  I2SM4_MCLK0S1        :1;
            __IO  uint32_t  I2SM4_MCLK0E0        :1;
            __IO  uint32_t  I2SM4_MCLK0E1        :1;
            __IO  uint32_t  I2SM4_SCK0B0         :1;
            __IO  uint32_t  I2SM4_SCK0B1         :1;
            __IO  uint32_t  I2SM4_WS0B0          :1;
            __IO  uint32_t  I2SM4_WS0B1          :1;
            __IO  uint32_t  I2SM4_SDI0S0         :1;
            __IO  uint32_t  I2SM4_SDI0S1         :1;
            __IO  uint32_t  I2SM4_SDO0E0         :1;
            __IO  uint32_t  I2SM4_SDO0E1         :1;
            __IO  uint32_t  RESERVED1            :4;
            __IO  uint32_t  I2SM4_MCLK1S0        :1;
            __IO  uint32_t  I2SM4_MCLK1S1        :1;
            __IO  uint32_t  I2SM4_MCLK1E0        :1;
            __IO  uint32_t  I2SM4_MCLK1E1        :1;
            __IO  uint32_t  I2SM4_SCK1B0         :1;
            __IO  uint32_t  I2SM4_SCK1B1         :1;
            __IO  uint32_t  I2SM4_WS1B0          :1;
            __IO  uint32_t  I2SM4_WS1B1          :1;
            __IO  uint32_t  I2SM4_SDI1S0         :1;
            __IO  uint32_t  I2SM4_SDI1S1         :1;
            __IO  uint32_t  I2SM4_SDO1E0         :1;
            __IO  uint32_t  I2SM4_SDO1E1         :1;
            __IO  uint32_t  RESERVED3            :4;
        };
    };
} stc_gpio_epfr24_field_t;

typedef struct stc_gpio_epfr25_field
{
    union {
        struct {
            __IO  uint32_t  MCRX2S               :2;
            __IO  uint32_t  MCTX2E               :2;
            __IO  uint32_t  RESERVED0            :28;
        };
        struct {
            __IO  uint32_t  MCRX2S0              :1;
            __IO  uint32_t  MCRX2S1              :1;
            __IO  uint32_t  MCTX2E0              :1;
            __IO  uint32_t  MCTX2E1              :1;
            __IO  uint32_t  RESERVED1            :28;
        };
    };
} stc_gpio_epfr25_field_t;

typedef struct stc_gpio_epfr26_field
{
    union {
        struct {
            __IO  uint32_t  Q_SCKB               :2;
            __IO  uint32_t  Q_CS0E               :2;
            __IO  uint32_t  Q_CS1E               :2;
            __IO  uint32_t  Q_CS2E               :2;
            __IO  uint32_t  Q_CS3E               :2;
            __IO  uint32_t  Q_IO0B               :2;
            __IO  uint32_t  Q_IO1B               :2;
            __IO  uint32_t  Q_IO2B               :2;
            __IO  uint32_t  Q_IO3B               :2;
            __IO  uint32_t  RESERVED0            :14;
        };
        struct {
            __IO  uint32_t  Q_SCKB0              :1;
            __IO  uint32_t  Q_SCKB1              :1;
            __IO  uint32_t  Q_CS0E0              :1;
            __IO  uint32_t  Q_CS0E1              :1;
            __IO  uint32_t  Q_CS1E0              :1;
            __IO  uint32_t  Q_CS1E1              :1;
            __IO  uint32_t  Q_CS2E0              :1;
            __IO  uint32_t  Q_CS2E1              :1;
            __IO  uint32_t  Q_CS3E0              :1;
            __IO  uint32_t  Q_CS3E1              :1;
            __IO  uint32_t  Q_IO0B0              :1;
            __IO  uint32_t  Q_IO0B1              :1;
            __IO  uint32_t  Q_IO1B0              :1;
            __IO  uint32_t  Q_IO1B1              :1;
            __IO  uint32_t  Q_IO2B0              :1;
            __IO  uint32_t  Q_IO2B1              :1;
            __IO  uint32_t  Q_IO3B0              :1;
            __IO  uint32_t  Q_IO3B1              :1;
            __IO  uint32_t  RESERVED1            :14;
        };
    };
} stc_gpio_epfr26_field_t;

typedef struct stc_gpio_pzr0_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  RESERVED0                :3;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  RESERVED1                :21;
} stc_gpio_pzr0_field_t;

typedef struct stc_gpio_pzr1_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  PF                       :1;
        __IO  uint32_t  RESERVED0                :16;
} stc_gpio_pzr1_field_t;

typedef struct stc_gpio_pzr2_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  RESERVED0                :21;
} stc_gpio_pzr2_field_t;

typedef struct stc_gpio_pzr3_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  RESERVED0                :17;
} stc_gpio_pzr3_field_t;

typedef struct stc_gpio_pzr4_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  RESERVED0                :22;
} stc_gpio_pzr4_field_t;

typedef struct stc_gpio_pzr5_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  RESERVED0                :10;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  PF                       :1;
        __IO  uint32_t  RESERVED1                :16;
} stc_gpio_pzr5_field_t;

typedef struct stc_gpio_pzr6_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  RESERVED0                :8;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  RESERVED1                :17;
} stc_gpio_pzr6_field_t;

typedef struct stc_gpio_pzr7_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  RESERVED0                :17;
} stc_gpio_pzr7_field_t;

typedef struct stc_gpio_pzr8_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  RESERVED0                :28;
} stc_gpio_pzr8_field_t;

typedef struct stc_gpio_pzr9_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  RESERVED0                :26;
} stc_gpio_pzr9_field_t;

typedef struct stc_gpio_pzra_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  PF                       :1;
        __IO  uint32_t  RESERVED0                :16;
} stc_gpio_pzra_field_t;

typedef struct stc_gpio_pzrb_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  RESERVED0                :24;
} stc_gpio_pzrb_field_t;

typedef struct stc_gpio_pzrc_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  PF                       :1;
        __IO  uint32_t  RESERVED0                :16;
} stc_gpio_pzrc_field_t;

typedef struct stc_gpio_pzrd_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  RESERVED0                :29;
} stc_gpio_pzrd_field_t;

typedef struct stc_gpio_pzre_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  RESERVED0                :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  RESERVED1                :28;
} stc_gpio_pzre_field_t;

typedef struct stc_gpio_pzrf_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  RESERVED0                :24;
} stc_gpio_pzrf_field_t;

typedef struct stc_gpio_pdsr0_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  RESERVED0                :3;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  RESERVED1                :21;
} stc_gpio_pdsr0_field_t;

typedef struct stc_gpio_pdsr1_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  PF                       :1;
        __IO  uint32_t  RESERVED0                :16;
} stc_gpio_pdsr1_field_t;

typedef struct stc_gpio_pdsr2_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  RESERVED0                :21;
} stc_gpio_pdsr2_field_t;

typedef struct stc_gpio_pdsr3_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  RESERVED0                :17;
} stc_gpio_pdsr3_field_t;

typedef struct stc_gpio_pdsr4_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  RESERVED0                :22;
} stc_gpio_pdsr4_field_t;

typedef struct stc_gpio_pdsr5_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  RESERVED0                :10;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  PF                       :1;
        __IO  uint32_t  RESERVED1                :16;
} stc_gpio_pdsr5_field_t;

typedef struct stc_gpio_pdsr6_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  RESERVED0                :8;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  RESERVED1                :17;
} stc_gpio_pdsr6_field_t;

typedef struct stc_gpio_pdsr7_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  RESERVED0                :17;
} stc_gpio_pdsr7_field_t;

typedef struct stc_gpio_pdsr8_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  RESERVED0                :28;
} stc_gpio_pdsr8_field_t;

typedef struct stc_gpio_pdsr9_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  RESERVED0                :26;
} stc_gpio_pdsr9_field_t;

typedef struct stc_gpio_pdsra_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  PF                       :1;
        __IO  uint32_t  RESERVED0                :16;
} stc_gpio_pdsra_field_t;

typedef struct stc_gpio_pdsrb_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  RESERVED0                :24;
} stc_gpio_pdsrb_field_t;

typedef struct stc_gpio_pdsrc_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  P8                       :1;
        __IO  uint32_t  P9                       :1;
        __IO  uint32_t  PA                       :1;
        __IO  uint32_t  PB                       :1;
        __IO  uint32_t  PC                       :1;
        __IO  uint32_t  PD                       :1;
        __IO  uint32_t  PE                       :1;
        __IO  uint32_t  PF                       :1;
        __IO  uint32_t  RESERVED0                :16;
} stc_gpio_pdsrc_field_t;

typedef struct stc_gpio_pdsrd_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  RESERVED0                :29;
} stc_gpio_pdsrd_field_t;

typedef struct stc_gpio_pdsre_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  RESERVED0                :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  RESERVED1                :28;
} stc_gpio_pdsre_field_t;

typedef struct stc_gpio_pdsrf_field
{
        __IO  uint32_t  P0                       :1;
        __IO  uint32_t  P1                       :1;
        __IO  uint32_t  P2                       :1;
        __IO  uint32_t  P3                       :1;
        __IO  uint32_t  P4                       :1;
        __IO  uint32_t  P5                       :1;
        __IO  uint32_t  P6                       :1;
        __IO  uint32_t  P7                       :1;
        __IO  uint32_t  RESERVED0                :24;
} stc_gpio_pdsrf_field_t;

/*******************************************************************************
* HSSPI_MODULE
*******************************************************************************/
typedef struct stc_hsspi_mctrl_field
{
        __IO  uint32_t  MEN                      :1;
        __IO  uint32_t  CSEN                     :1;
        __IO  uint32_t  RESERVED0                :2;
        __IO  uint32_t  MES                      :1;
        __IO  uint32_t  SYNCON                   :1;
        __IO  uint32_t  RESERVED1                :26;
} stc_hsspi_mctrl_field_t;

typedef struct stc_hsspi_pcc0_field
{
    union {
        struct {
            __IO  uint32_t  CPHA                 :1;
            __IO  uint32_t  CPOL                 :1;
            __IO  uint32_t  ACES                 :1;
            __IO  uint32_t  RTM                  :1;
            __IO  uint32_t  SSPOL                :1;
            __IO  uint32_t  SS2CD                :2;
            __IO  uint32_t  SDIR                 :1;
            __IO  uint32_t  SENDIAN              :1;
            __IO  uint32_t  CDRS                 :7;
            __IO  uint32_t  SAFESYNC             :1;
            __IO  uint32_t  WRDSEL               :4;
            __IO  uint32_t  RDDSEL               :2;
            __IO  uint32_t  RESERVED3            :9;
        };
        struct {
            __IO  uint32_t  RESERVED0            :5;
            __IO  uint32_t  SS2CD0               :1;
            __IO  uint32_t  SS2CD1               :1;
            __IO  uint32_t  RESERVED1            :2;
            __IO  uint32_t  CDRS0                :1;
            __IO  uint32_t  CDRS1                :1;
            __IO  uint32_t  CDRS2                :1;
            __IO  uint32_t  CDRS3                :1;
            __IO  uint32_t  CDRS4                :1;
            __IO  uint32_t  CDRS5                :1;
            __IO  uint32_t  CDRS6                :1;
            __IO  uint32_t  RESERVED2            :1;
            __IO  uint32_t  WRDSEL0              :1;
            __IO  uint32_t  WRDSEL1              :1;
            __IO  uint32_t  WRDSEL2              :1;
            __IO  uint32_t  WRDSEL3              :1;
            __IO  uint32_t  RDDSEL0              :1;
            __IO  uint32_t  RDDSEL1              :1;
            __IO  uint32_t  RESERVED4            :9;
        };
    };
} stc_hsspi_pcc0_field_t;

typedef struct stc_hsspi_pcc1_field
{
    union {
        struct {
            __IO  uint32_t  CPHA                 :1;
            __IO  uint32_t  CPOL                 :1;
            __IO  uint32_t  ACES                 :1;
            __IO  uint32_t  RTM                  :1;
            __IO  uint32_t  SSPOL                :1;
            __IO  uint32_t  SS2CD                :2;
            __IO  uint32_t  SDIR                 :1;
            __IO  uint32_t  SENDIAN              :1;
            __IO  uint32_t  CDRS                 :7;
            __IO  uint32_t  SAFESYNC             :1;
            __IO  uint32_t  WRDSEL               :4;
            __IO  uint32_t  RDDSEL               :2;
            __IO  uint32_t  RESERVED3            :9;
        };
        struct {
            __IO  uint32_t  RESERVED0            :5;
            __IO  uint32_t  SS2CD0               :1;
            __IO  uint32_t  SS2CD1               :1;
            __IO  uint32_t  RESERVED1            :2;
            __IO  uint32_t  CDRS0                :1;
            __IO  uint32_t  CDRS1                :1;
            __IO  uint32_t  CDRS2                :1;
            __IO  uint32_t  CDRS3                :1;
            __IO  uint32_t  CDRS4                :1;
            __IO  uint32_t  CDRS5                :1;
            __IO  uint32_t  CDRS6                :1;
            __IO  uint32_t  RESERVED2            :1;
            __IO  uint32_t  WRDSEL0              :1;
            __IO  uint32_t  WRDSEL1              :1;
            __IO  uint32_t  WRDSEL2              :1;
            __IO  uint32_t  WRDSEL3              :1;
            __IO  uint32_t  RDDSEL0              :1;
            __IO  uint32_t  RDDSEL1              :1;
            __IO  uint32_t  RESERVED4            :9;
        };
    };
} stc_hsspi_pcc1_field_t;

typedef struct stc_hsspi_pcc2_field
{
    union {
        struct {
            __IO  uint32_t  CPHA                 :1;
            __IO  uint32_t  CPOL                 :1;
            __IO  uint32_t  ACES                 :1;
            __IO  uint32_t  RTM                  :1;
            __IO  uint32_t  SSPOL                :1;
            __IO  uint32_t  SS2CD                :2;
            __IO  uint32_t  SDIR                 :1;
            __IO  uint32_t  SENDIAN              :1;
            __IO  uint32_t  CDRS                 :7;
            __IO  uint32_t  SAFESYNC             :1;
            __IO  uint32_t  WRDSEL               :4;
            __IO  uint32_t  RDDSEL               :2;
            __IO  uint32_t  RESERVED3            :9;
        };
        struct {
            __IO  uint32_t  RESERVED0            :5;
            __IO  uint32_t  SS2CD0               :1;
            __IO  uint32_t  SS2CD1               :1;
            __IO  uint32_t  RESERVED1            :2;
            __IO  uint32_t  CDRS0                :1;
            __IO  uint32_t  CDRS1                :1;
            __IO  uint32_t  CDRS2                :1;
            __IO  uint32_t  CDRS3                :1;
            __IO  uint32_t  CDRS4                :1;
            __IO  uint32_t  CDRS5                :1;
            __IO  uint32_t  CDRS6                :1;
            __IO  uint32_t  RESERVED2            :1;
            __IO  uint32_t  WRDSEL0              :1;
            __IO  uint32_t  WRDSEL1              :1;
            __IO  uint32_t  WRDSEL2              :1;
            __IO  uint32_t  WRDSEL3              :1;
            __IO  uint32_t  RDDSEL0              :1;
            __IO  uint32_t  RDDSEL1              :1;
            __IO  uint32_t  RESERVED4            :9;
        };
    };
} stc_hsspi_pcc2_field_t;

typedef struct stc_hsspi_pcc3_field
{
    union {
        struct {
            __IO  uint32_t  CPHA                 :1;
            __IO  uint32_t  CPOL                 :1;
            __IO  uint32_t  ACES                 :1;
            __IO  uint32_t  RTM                  :1;
            __IO  uint32_t  SSPOL                :1;
            __IO  uint32_t  SS2CD                :2;
            __IO  uint32_t  SDIR                 :1;
            __IO  uint32_t  SENDIAN              :1;
            __IO  uint32_t  CDRS                 :7;
            __IO  uint32_t  SAFESYNC             :1;
            __IO  uint32_t  WRDSEL               :4;
            __IO  uint32_t  RDDSEL               :2;
            __IO  uint32_t  RESERVED3            :9;
        };
        struct {
            __IO  uint32_t  RESERVED0            :5;
            __IO  uint32_t  SS2CD0               :1;
            __IO  uint32_t  SS2CD1               :1;
            __IO  uint32_t  RESERVED1            :2;
            __IO  uint32_t  CDRS0                :1;
            __IO  uint32_t  CDRS1                :1;
            __IO  uint32_t  CDRS2                :1;
            __IO  uint32_t  CDRS3                :1;
            __IO  uint32_t  CDRS4                :1;
            __IO  uint32_t  CDRS5                :1;
            __IO  uint32_t  CDRS6                :1;
            __IO  uint32_t  RESERVED2            :1;
            __IO  uint32_t  WRDSEL0              :1;
            __IO  uint32_t  WRDSEL1              :1;
            __IO  uint32_t  WRDSEL2              :1;
            __IO  uint32_t  WRDSEL3              :1;
            __IO  uint32_t  RDDSEL0              :1;
            __IO  uint32_t  RDDSEL1              :1;
            __IO  uint32_t  RESERVED4            :9;
        };
    };
} stc_hsspi_pcc3_field_t;

typedef struct stc_hsspi_txf_field
{
        __IO  uint32_t  TFFS                     :1;
        __IO  uint32_t  TFES                     :1;
        __IO  uint32_t  TFOS                     :1;
        __IO  uint32_t  TFUS                     :1;
        __IO  uint32_t  TFLETS                   :1;
        __IO  uint32_t  TFMTS                    :1;
        __IO  uint32_t  TSSRS                    :1;
        __IO  uint32_t  RESERVED0                :25;
} stc_hsspi_txf_field_t;

typedef struct stc_hsspi_txe_field
{
        __IO  uint32_t  TFFE                     :1;
        __IO  uint32_t  TFEE                     :1;
        __IO  uint32_t  TFOE                     :1;
        __IO  uint32_t  TFUE                     :1;
        __IO  uint32_t  TFLETE                   :1;
        __IO  uint32_t  TFMTE                    :1;
        __IO  uint32_t  TSSRE                    :1;
        __IO  uint32_t  RESERVED0                :25;
} stc_hsspi_txe_field_t;

typedef struct stc_hsspi_txc_field
{
        __IO  uint32_t  TFFC                     :1;
        __IO  uint32_t  TFEC                     :1;
        __IO  uint32_t  TFOC                     :1;
        __IO  uint32_t  TFUC                     :1;
        __IO  uint32_t  TFLETC                   :1;
        __IO  uint32_t  TFMTC                    :1;
        __IO  uint32_t  TSSRC                    :1;
        __IO  uint32_t  RESERVED0                :25;
} stc_hsspi_txc_field_t;

typedef struct stc_hsspi_rxf_field
{
        __IO  uint32_t  RFFS                     :1;
        __IO  uint32_t  RFES                     :1;
        __IO  uint32_t  RFOS                     :1;
        __IO  uint32_t  RFUS                     :1;
        __IO  uint32_t  RFLETS                   :1;
        __IO  uint32_t  RFMTS                    :1;
        __IO  uint32_t  RSSRS                    :1;
        __IO  uint32_t  RESERVED0                :25;
} stc_hsspi_rxf_field_t;

typedef struct stc_hsspi_rxe_field
{
        __IO  uint32_t  RFFE                     :1;
        __IO  uint32_t  RFEE                     :1;
        __IO  uint32_t  RFOE                     :1;
        __IO  uint32_t  RFUE                     :1;
        __IO  uint32_t  RFLETE                   :1;
        __IO  uint32_t  RFMTE                    :1;
        __IO  uint32_t  RSSRE                    :1;
        __IO  uint32_t  RESERVED0                :25;
} stc_hsspi_rxe_field_t;

typedef struct stc_hsspi_rxc_field
{
        __IO  uint32_t  RFFC                     :1;
        __IO  uint32_t  RFEC                     :1;
        __IO  uint32_t  RFOC                     :1;
        __IO  uint32_t  RFUC                     :1;
        __IO  uint32_t  RFLETC                   :1;
        __IO  uint32_t  RFMTC                    :1;
        __IO  uint32_t  RSSRC                    :1;
        __IO  uint32_t  RESERVED0                :25;
} stc_hsspi_rxc_field_t;

typedef struct stc_hsspi_faultf_field
{
        __IO  uint32_t  UMAFS                    :1;
        __IO  uint32_t  WAFS                     :1;
        __IO  uint32_t  PVFS                     :1;
        __IO  uint32_t  DWCBSFS                  :1;
        __IO  uint32_t  DRCBSFS                  :1;
        __IO  uint32_t  RESERVED0                :27;
} stc_hsspi_faultf_field_t;

typedef struct stc_hsspi_faultc_field
{
        __IO  uint32_t  UMAFC                    :1;
        __IO  uint32_t  WAFC                     :1;
        __IO  uint32_t  PVFC                     :1;
        __IO  uint32_t  DWCBSFC                  :1;
        __IO  uint32_t  DRCBSFC                  :1;
        __IO  uint32_t  RESERVED0                :27;
} stc_hsspi_faultc_field_t;

typedef struct stc_hsspi_dmcfg_field
{
        __IO   uint8_t  RESERVED0                :1;
        __IO   uint8_t  SSDC                     :1;
        __IO   uint8_t  RESERVED1                :6;
} stc_hsspi_dmcfg_field_t;

typedef struct stc_hsspi_dmdmaen_field
{
        __IO   uint8_t  RXDMAEN                  :1;
        __IO   uint8_t  TXDMAEN                  :1;
        __IO   uint8_t  RESERVED0                :6;
} stc_hsspi_dmdmaen_field_t;

typedef struct stc_hsspi_dmstart_field
{
        __IO   uint8_t  START                    :1;
        __IO   uint8_t  RESERVED0                :7;
} stc_hsspi_dmstart_field_t;

typedef struct stc_hsspi_dmstop_field
{
        __IO   uint8_t  STOP                     :1;
        __IO   uint8_t  RESERVED0                :7;
} stc_hsspi_dmstop_field_t;

typedef struct stc_hsspi_dmpsel_field
{
    union {
        struct {
            __IO   uint8_t  PSEL                 :2;
            __IO   uint8_t  RESERVED0            :6;
        };
        struct {
            __IO   uint8_t  PSEL0                :1;
            __IO   uint8_t  PSEL1                :1;
            __IO   uint8_t  RESERVED1            :6;
        };
    };
} stc_hsspi_dmpsel_field_t;

typedef struct stc_hsspi_dmtrp_field
{
    union {
        struct {
            __IO   uint8_t  TRP                  :4;
            __IO   uint8_t  RESERVED0            :4;
        };
        struct {
            __IO   uint8_t  TRP0                 :1;
            __IO   uint8_t  TRP1                 :1;
            __IO   uint8_t  TRP2                 :1;
            __IO   uint8_t  TRP3                 :1;
            __IO   uint8_t  RESERVED1            :4;
        };
    };
} stc_hsspi_dmtrp_field_t;

typedef struct stc_hsspi_dmbcc_field
{
    union {
        struct {
            __IO  uint16_t  BCC                  :16;
        };
        struct {
            __IO  uint16_t  BCC0                 :1;
            __IO  uint16_t  BCC1                 :1;
            __IO  uint16_t  BCC2                 :1;
            __IO  uint16_t  BCC3                 :1;
            __IO  uint16_t  BCC4                 :1;
            __IO  uint16_t  BCC5                 :1;
            __IO  uint16_t  BCC6                 :1;
            __IO  uint16_t  BCC7                 :1;
            __IO  uint16_t  BCC8                 :1;
            __IO  uint16_t  BCC9                 :1;
            __IO  uint16_t  BCC10                :1;
            __IO  uint16_t  BCC11                :1;
            __IO  uint16_t  BCC12                :1;
            __IO  uint16_t  BCC13                :1;
            __IO  uint16_t  BCC14                :1;
            __IO  uint16_t  BCC15                :1;
        };
    };
} stc_hsspi_dmbcc_field_t;

typedef struct stc_hsspi_dmbcs_field
{
    union {
        struct {
            __IO  uint16_t  BCS                  :16;
        };
        struct {
            __IO  uint16_t  BCS0                 :1;
            __IO  uint16_t  BCS1                 :1;
            __IO  uint16_t  BCS2                 :1;
            __IO  uint16_t  BCS3                 :1;
            __IO  uint16_t  BCS4                 :1;
            __IO  uint16_t  BCS5                 :1;
            __IO  uint16_t  BCS6                 :1;
            __IO  uint16_t  BCS7                 :1;
            __IO  uint16_t  BCS8                 :1;
            __IO  uint16_t  BCS9                 :1;
            __IO  uint16_t  BCS10                :1;
            __IO  uint16_t  BCS11                :1;
            __IO  uint16_t  BCS12                :1;
            __IO  uint16_t  BCS13                :1;
            __IO  uint16_t  BCS14                :1;
            __IO  uint16_t  BCS15                :1;
        };
    };
} stc_hsspi_dmbcs_field_t;

typedef struct stc_hsspi_dmstatus_field
{
    union {
        struct {
            __IO  uint32_t  RXACTIVE             :1;
            __IO  uint32_t  TXACTIVE             :1;
            __IO  uint32_t  RESERVED0            :6;
            __IO  uint32_t  RXFLEVEL             :5;
            __IO  uint32_t  RESERVED2            :3;
            __IO  uint32_t  TXFLEVEL             :5;
            __IO  uint32_t  RESERVED4            :11;
        };
        struct {
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  RXFLEVEL0            :1;
            __IO  uint32_t  RXFLEVEL1            :1;
            __IO  uint32_t  RXFLEVEL2            :1;
            __IO  uint32_t  RXFLEVEL3            :1;
            __IO  uint32_t  RXFLEVEL4            :1;
            __IO  uint32_t  RESERVED3            :3;
            __IO  uint32_t  TXFLEVEL0            :1;
            __IO  uint32_t  TXFLEVEL1            :1;
            __IO  uint32_t  TXFLEVEL2            :1;
            __IO  uint32_t  TXFLEVEL3            :1;
            __IO  uint32_t  TXFLEVEL4            :1;
            __IO  uint32_t  RESERVED5            :11;
        };
    };
} stc_hsspi_dmstatus_field_t;

typedef struct stc_hsspi_fifocfg_field
{
    union {
        struct {
            __IO  uint32_t  RXFTH                :4;
            __IO  uint32_t  TXFTH                :4;
            __IO  uint32_t  FWIDTH               :2;
            __IO  uint32_t  TXCTRL               :1;
            __IO  uint32_t  RXFLSH               :1;
            __IO  uint32_t  TXFLSH               :1;
            __IO  uint32_t  RESERVED0            :19;
        };
        struct {
            __IO  uint32_t  RXFTH0               :1;
            __IO  uint32_t  RXFTH1               :1;
            __IO  uint32_t  RXFTH2               :1;
            __IO  uint32_t  RXFTH3               :1;
            __IO  uint32_t  TXFTH0               :1;
            __IO  uint32_t  TXFTH1               :1;
            __IO  uint32_t  TXFTH2               :1;
            __IO  uint32_t  TXFTH3               :1;
            __IO  uint32_t  FWIDTH0              :1;
            __IO  uint32_t  FWIDTH1              :1;
            __IO  uint32_t  RESERVED1            :22;
        };
    };
} stc_hsspi_fifocfg_field_t;

typedef struct stc_hsspi_txfifo0_field
{
    union {
        struct {
            __IO  uint32_t  TXDATA               :32;
        };
        struct {
            __IO  uint32_t  TXDATA0              :1;
            __IO  uint32_t  TXDATA1              :1;
            __IO  uint32_t  TXDATA2              :1;
            __IO  uint32_t  TXDATA3              :1;
            __IO  uint32_t  TXDATA4              :1;
            __IO  uint32_t  TXDATA5              :1;
            __IO  uint32_t  TXDATA6              :1;
            __IO  uint32_t  TXDATA7              :1;
            __IO  uint32_t  TXDATA8              :1;
            __IO  uint32_t  TXDATA9              :1;
            __IO  uint32_t  TXDATA10             :1;
            __IO  uint32_t  TXDATA11             :1;
            __IO  uint32_t  TXDATA12             :1;
            __IO  uint32_t  TXDATA13             :1;
            __IO  uint32_t  TXDATA14             :1;
            __IO  uint32_t  TXDATA15             :1;
            __IO  uint32_t  TXDATA16             :1;
            __IO  uint32_t  TXDATA17             :1;
            __IO  uint32_t  TXDATA18             :1;
            __IO  uint32_t  TXDATA19             :1;
            __IO  uint32_t  TXDATA20             :1;
            __IO  uint32_t  TXDATA21             :1;
            __IO  uint32_t  TXDATA22             :1;
            __IO  uint32_t  TXDATA23             :1;
            __IO  uint32_t  TXDATA24             :1;
            __IO  uint32_t  TXDATA25             :1;
            __IO  uint32_t  TXDATA26             :1;
            __IO  uint32_t  TXDATA27             :1;
            __IO  uint32_t  TXDATA28             :1;
            __IO  uint32_t  TXDATA29             :1;
            __IO  uint32_t  TXDATA30             :1;
            __IO  uint32_t  TXDATA31             :1;
        };
    };
} stc_hsspi_txfifo0_field_t;

typedef struct stc_hsspi_txfifo1_field
{
    union {
        struct {
            __IO  uint32_t  TXDATA               :32;
        };
        struct {
            __IO  uint32_t  TXDATA0              :1;
            __IO  uint32_t  TXDATA1              :1;
            __IO  uint32_t  TXDATA2              :1;
            __IO  uint32_t  TXDATA3              :1;
            __IO  uint32_t  TXDATA4              :1;
            __IO  uint32_t  TXDATA5              :1;
            __IO  uint32_t  TXDATA6              :1;
            __IO  uint32_t  TXDATA7              :1;
            __IO  uint32_t  TXDATA8              :1;
            __IO  uint32_t  TXDATA9              :1;
            __IO  uint32_t  TXDATA10             :1;
            __IO  uint32_t  TXDATA11             :1;
            __IO  uint32_t  TXDATA12             :1;
            __IO  uint32_t  TXDATA13             :1;
            __IO  uint32_t  TXDATA14             :1;
            __IO  uint32_t  TXDATA15             :1;
            __IO  uint32_t  TXDATA16             :1;
            __IO  uint32_t  TXDATA17             :1;
            __IO  uint32_t  TXDATA18             :1;
            __IO  uint32_t  TXDATA19             :1;
            __IO  uint32_t  TXDATA20             :1;
            __IO  uint32_t  TXDATA21             :1;
            __IO  uint32_t  TXDATA22             :1;
            __IO  uint32_t  TXDATA23             :1;
            __IO  uint32_t  TXDATA24             :1;
            __IO  uint32_t  TXDATA25             :1;
            __IO  uint32_t  TXDATA26             :1;
            __IO  uint32_t  TXDATA27             :1;
            __IO  uint32_t  TXDATA28             :1;
            __IO  uint32_t  TXDATA29             :1;
            __IO  uint32_t  TXDATA30             :1;
            __IO  uint32_t  TXDATA31             :1;
        };
    };
} stc_hsspi_txfifo1_field_t;

typedef struct stc_hsspi_txfifo2_field
{
    union {
        struct {
            __IO  uint32_t  TXDATA               :32;
        };
        struct {
            __IO  uint32_t  TXDATA0              :1;
            __IO  uint32_t  TXDATA1              :1;
            __IO  uint32_t  TXDATA2              :1;
            __IO  uint32_t  TXDATA3              :1;
            __IO  uint32_t  TXDATA4              :1;
            __IO  uint32_t  TXDATA5              :1;
            __IO  uint32_t  TXDATA6              :1;
            __IO  uint32_t  TXDATA7              :1;
            __IO  uint32_t  TXDATA8              :1;
            __IO  uint32_t  TXDATA9              :1;
            __IO  uint32_t  TXDATA10             :1;
            __IO  uint32_t  TXDATA11             :1;
            __IO  uint32_t  TXDATA12             :1;
            __IO  uint32_t  TXDATA13             :1;
            __IO  uint32_t  TXDATA14             :1;
            __IO  uint32_t  TXDATA15             :1;
            __IO  uint32_t  TXDATA16             :1;
            __IO  uint32_t  TXDATA17             :1;
            __IO  uint32_t  TXDATA18             :1;
            __IO  uint32_t  TXDATA19             :1;
            __IO  uint32_t  TXDATA20             :1;
            __IO  uint32_t  TXDATA21             :1;
            __IO  uint32_t  TXDATA22             :1;
            __IO  uint32_t  TXDATA23             :1;
            __IO  uint32_t  TXDATA24             :1;
            __IO  uint32_t  TXDATA25             :1;
            __IO  uint32_t  TXDATA26             :1;
            __IO  uint32_t  TXDATA27             :1;
            __IO  uint32_t  TXDATA28             :1;
            __IO  uint32_t  TXDATA29             :1;
            __IO  uint32_t  TXDATA30             :1;
            __IO  uint32_t  TXDATA31             :1;
        };
    };
} stc_hsspi_txfifo2_field_t;

typedef struct stc_hsspi_txfifo3_field
{
    union {
        struct {
            __IO  uint32_t  TXDATA               :32;
        };
        struct {
            __IO  uint32_t  TXDATA0              :1;
            __IO  uint32_t  TXDATA1              :1;
            __IO  uint32_t  TXDATA2              :1;
            __IO  uint32_t  TXDATA3              :1;
            __IO  uint32_t  TXDATA4              :1;
            __IO  uint32_t  TXDATA5              :1;
            __IO  uint32_t  TXDATA6              :1;
            __IO  uint32_t  TXDATA7              :1;
            __IO  uint32_t  TXDATA8              :1;
            __IO  uint32_t  TXDATA9              :1;
            __IO  uint32_t  TXDATA10             :1;
            __IO  uint32_t  TXDATA11             :1;
            __IO  uint32_t  TXDATA12             :1;
            __IO  uint32_t  TXDATA13             :1;
            __IO  uint32_t  TXDATA14             :1;
            __IO  uint32_t  TXDATA15             :1;
            __IO  uint32_t  TXDATA16             :1;
            __IO  uint32_t  TXDATA17             :1;
            __IO  uint32_t  TXDATA18             :1;
            __IO  uint32_t  TXDATA19             :1;
            __IO  uint32_t  TXDATA20             :1;
            __IO  uint32_t  TXDATA21             :1;
            __IO  uint32_t  TXDATA22             :1;
            __IO  uint32_t  TXDATA23             :1;
            __IO  uint32_t  TXDATA24             :1;
            __IO  uint32_t  TXDATA25             :1;
            __IO  uint32_t  TXDATA26             :1;
            __IO  uint32_t  TXDATA27             :1;
            __IO  uint32_t  TXDATA28             :1;
            __IO  uint32_t  TXDATA29             :1;
            __IO  uint32_t  TXDATA30             :1;
            __IO  uint32_t  TXDATA31             :1;
        };
    };
} stc_hsspi_txfifo3_field_t;

typedef struct stc_hsspi_txfifo4_field
{
    union {
        struct {
            __IO  uint32_t  TXDATA               :32;
        };
        struct {
            __IO  uint32_t  TXDATA0              :1;
            __IO  uint32_t  TXDATA1              :1;
            __IO  uint32_t  TXDATA2              :1;
            __IO  uint32_t  TXDATA3              :1;
            __IO  uint32_t  TXDATA4              :1;
            __IO  uint32_t  TXDATA5              :1;
            __IO  uint32_t  TXDATA6              :1;
            __IO  uint32_t  TXDATA7              :1;
            __IO  uint32_t  TXDATA8              :1;
            __IO  uint32_t  TXDATA9              :1;
            __IO  uint32_t  TXDATA10             :1;
            __IO  uint32_t  TXDATA11             :1;
            __IO  uint32_t  TXDATA12             :1;
            __IO  uint32_t  TXDATA13             :1;
            __IO  uint32_t  TXDATA14             :1;
            __IO  uint32_t  TXDATA15             :1;
            __IO  uint32_t  TXDATA16             :1;
            __IO  uint32_t  TXDATA17             :1;
            __IO  uint32_t  TXDATA18             :1;
            __IO  uint32_t  TXDATA19             :1;
            __IO  uint32_t  TXDATA20             :1;
            __IO  uint32_t  TXDATA21             :1;
            __IO  uint32_t  TXDATA22             :1;
            __IO  uint32_t  TXDATA23             :1;
            __IO  uint32_t  TXDATA24             :1;
            __IO  uint32_t  TXDATA25             :1;
            __IO  uint32_t  TXDATA26             :1;
            __IO  uint32_t  TXDATA27             :1;
            __IO  uint32_t  TXDATA28             :1;
            __IO  uint32_t  TXDATA29             :1;
            __IO  uint32_t  TXDATA30             :1;
            __IO  uint32_t  TXDATA31             :1;
        };
    };
} stc_hsspi_txfifo4_field_t;

typedef struct stc_hsspi_txfifo5_field
{
    union {
        struct {
            __IO  uint32_t  TXDATA               :32;
        };
        struct {
            __IO  uint32_t  TXDATA0              :1;
            __IO  uint32_t  TXDATA1              :1;
            __IO  uint32_t  TXDATA2              :1;
            __IO  uint32_t  TXDATA3              :1;
            __IO  uint32_t  TXDATA4              :1;
            __IO  uint32_t  TXDATA5              :1;
            __IO  uint32_t  TXDATA6              :1;
            __IO  uint32_t  TXDATA7              :1;
            __IO  uint32_t  TXDATA8              :1;
            __IO  uint32_t  TXDATA9              :1;
            __IO  uint32_t  TXDATA10             :1;
            __IO  uint32_t  TXDATA11             :1;
            __IO  uint32_t  TXDATA12             :1;
            __IO  uint32_t  TXDATA13             :1;
            __IO  uint32_t  TXDATA14             :1;
            __IO  uint32_t  TXDATA15             :1;
            __IO  uint32_t  TXDATA16             :1;
            __IO  uint32_t  TXDATA17             :1;
            __IO  uint32_t  TXDATA18             :1;
            __IO  uint32_t  TXDATA19             :1;
            __IO  uint32_t  TXDATA20             :1;
            __IO  uint32_t  TXDATA21             :1;
            __IO  uint32_t  TXDATA22             :1;
            __IO  uint32_t  TXDATA23             :1;
            __IO  uint32_t  TXDATA24             :1;
            __IO  uint32_t  TXDATA25             :1;
            __IO  uint32_t  TXDATA26             :1;
            __IO  uint32_t  TXDATA27             :1;
            __IO  uint32_t  TXDATA28             :1;
            __IO  uint32_t  TXDATA29             :1;
            __IO  uint32_t  TXDATA30             :1;
            __IO  uint32_t  TXDATA31             :1;
        };
    };
} stc_hsspi_txfifo5_field_t;

typedef struct stc_hsspi_txfifo6_field
{
    union {
        struct {
            __IO  uint32_t  TXDATA               :32;
        };
        struct {
            __IO  uint32_t  TXDATA0              :1;
            __IO  uint32_t  TXDATA1              :1;
            __IO  uint32_t  TXDATA2              :1;
            __IO  uint32_t  TXDATA3              :1;
            __IO  uint32_t  TXDATA4              :1;
            __IO  uint32_t  TXDATA5              :1;
            __IO  uint32_t  TXDATA6              :1;
            __IO  uint32_t  TXDATA7              :1;
            __IO  uint32_t  TXDATA8              :1;
            __IO  uint32_t  TXDATA9              :1;
            __IO  uint32_t  TXDATA10             :1;
            __IO  uint32_t  TXDATA11             :1;
            __IO  uint32_t  TXDATA12             :1;
            __IO  uint32_t  TXDATA13             :1;
            __IO  uint32_t  TXDATA14             :1;
            __IO  uint32_t  TXDATA15             :1;
            __IO  uint32_t  TXDATA16             :1;
            __IO  uint32_t  TXDATA17             :1;
            __IO  uint32_t  TXDATA18             :1;
            __IO  uint32_t  TXDATA19             :1;
            __IO  uint32_t  TXDATA20             :1;
            __IO  uint32_t  TXDATA21             :1;
            __IO  uint32_t  TXDATA22             :1;
            __IO  uint32_t  TXDATA23             :1;
            __IO  uint32_t  TXDATA24             :1;
            __IO  uint32_t  TXDATA25             :1;
            __IO  uint32_t  TXDATA26             :1;
            __IO  uint32_t  TXDATA27             :1;
            __IO  uint32_t  TXDATA28             :1;
            __IO  uint32_t  TXDATA29             :1;
            __IO  uint32_t  TXDATA30             :1;
            __IO  uint32_t  TXDATA31             :1;
        };
    };
} stc_hsspi_txfifo6_field_t;

typedef struct stc_hsspi_txfifo7_field
{
    union {
        struct {
            __IO  uint32_t  TXDATA               :32;
        };
        struct {
            __IO  uint32_t  TXDATA0              :1;
            __IO  uint32_t  TXDATA1              :1;
            __IO  uint32_t  TXDATA2              :1;
            __IO  uint32_t  TXDATA3              :1;
            __IO  uint32_t  TXDATA4              :1;
            __IO  uint32_t  TXDATA5              :1;
            __IO  uint32_t  TXDATA6              :1;
            __IO  uint32_t  TXDATA7              :1;
            __IO  uint32_t  TXDATA8              :1;
            __IO  uint32_t  TXDATA9              :1;
            __IO  uint32_t  TXDATA10             :1;
            __IO  uint32_t  TXDATA11             :1;
            __IO  uint32_t  TXDATA12             :1;
            __IO  uint32_t  TXDATA13             :1;
            __IO  uint32_t  TXDATA14             :1;
            __IO  uint32_t  TXDATA15             :1;
            __IO  uint32_t  TXDATA16             :1;
            __IO  uint32_t  TXDATA17             :1;
            __IO  uint32_t  TXDATA18             :1;
            __IO  uint32_t  TXDATA19             :1;
            __IO  uint32_t  TXDATA20             :1;
            __IO  uint32_t  TXDATA21             :1;
            __IO  uint32_t  TXDATA22             :1;
            __IO  uint32_t  TXDATA23             :1;
            __IO  uint32_t  TXDATA24             :1;
            __IO  uint32_t  TXDATA25             :1;
            __IO  uint32_t  TXDATA26             :1;
            __IO  uint32_t  TXDATA27             :1;
            __IO  uint32_t  TXDATA28             :1;
            __IO  uint32_t  TXDATA29             :1;
            __IO  uint32_t  TXDATA30             :1;
            __IO  uint32_t  TXDATA31             :1;
        };
    };
} stc_hsspi_txfifo7_field_t;

typedef struct stc_hsspi_txfifo8_field
{
    union {
        struct {
            __IO  uint32_t  TXDATA               :32;
        };
        struct {
            __IO  uint32_t  TXDATA0              :1;
            __IO  uint32_t  TXDATA1              :1;
            __IO  uint32_t  TXDATA2              :1;
            __IO  uint32_t  TXDATA3              :1;
            __IO  uint32_t  TXDATA4              :1;
            __IO  uint32_t  TXDATA5              :1;
            __IO  uint32_t  TXDATA6              :1;
            __IO  uint32_t  TXDATA7              :1;
            __IO  uint32_t  TXDATA8              :1;
            __IO  uint32_t  TXDATA9              :1;
            __IO  uint32_t  TXDATA10             :1;
            __IO  uint32_t  TXDATA11             :1;
            __IO  uint32_t  TXDATA12             :1;
            __IO  uint32_t  TXDATA13             :1;
            __IO  uint32_t  TXDATA14             :1;
            __IO  uint32_t  TXDATA15             :1;
            __IO  uint32_t  TXDATA16             :1;
            __IO  uint32_t  TXDATA17             :1;
            __IO  uint32_t  TXDATA18             :1;
            __IO  uint32_t  TXDATA19             :1;
            __IO  uint32_t  TXDATA20             :1;
            __IO  uint32_t  TXDATA21             :1;
            __IO  uint32_t  TXDATA22             :1;
            __IO  uint32_t  TXDATA23             :1;
            __IO  uint32_t  TXDATA24             :1;
            __IO  uint32_t  TXDATA25             :1;
            __IO  uint32_t  TXDATA26             :1;
            __IO  uint32_t  TXDATA27             :1;
            __IO  uint32_t  TXDATA28             :1;
            __IO  uint32_t  TXDATA29             :1;
            __IO  uint32_t  TXDATA30             :1;
            __IO  uint32_t  TXDATA31             :1;
        };
    };
} stc_hsspi_txfifo8_field_t;

typedef struct stc_hsspi_txfifo9_field
{
    union {
        struct {
            __IO  uint32_t  TXDATA               :32;
        };
        struct {
            __IO  uint32_t  TXDATA0              :1;
            __IO  uint32_t  TXDATA1              :1;
            __IO  uint32_t  TXDATA2              :1;
            __IO  uint32_t  TXDATA3              :1;
            __IO  uint32_t  TXDATA4              :1;
            __IO  uint32_t  TXDATA5              :1;
            __IO  uint32_t  TXDATA6              :1;
            __IO  uint32_t  TXDATA7              :1;
            __IO  uint32_t  TXDATA8              :1;
            __IO  uint32_t  TXDATA9              :1;
            __IO  uint32_t  TXDATA10             :1;
            __IO  uint32_t  TXDATA11             :1;
            __IO  uint32_t  TXDATA12             :1;
            __IO  uint32_t  TXDATA13             :1;
            __IO  uint32_t  TXDATA14             :1;
            __IO  uint32_t  TXDATA15             :1;
            __IO  uint32_t  TXDATA16             :1;
            __IO  uint32_t  TXDATA17             :1;
            __IO  uint32_t  TXDATA18             :1;
            __IO  uint32_t  TXDATA19             :1;
            __IO  uint32_t  TXDATA20             :1;
            __IO  uint32_t  TXDATA21             :1;
            __IO  uint32_t  TXDATA22             :1;
            __IO  uint32_t  TXDATA23             :1;
            __IO  uint32_t  TXDATA24             :1;
            __IO  uint32_t  TXDATA25             :1;
            __IO  uint32_t  TXDATA26             :1;
            __IO  uint32_t  TXDATA27             :1;
            __IO  uint32_t  TXDATA28             :1;
            __IO  uint32_t  TXDATA29             :1;
            __IO  uint32_t  TXDATA30             :1;
            __IO  uint32_t  TXDATA31             :1;
        };
    };
} stc_hsspi_txfifo9_field_t;

typedef struct stc_hsspi_txfifo10_field
{
    union {
        struct {
            __IO  uint32_t  TXDATA               :32;
        };
        struct {
            __IO  uint32_t  TXDATA0              :1;
            __IO  uint32_t  TXDATA1              :1;
            __IO  uint32_t  TXDATA2              :1;
            __IO  uint32_t  TXDATA3              :1;
            __IO  uint32_t  TXDATA4              :1;
            __IO  uint32_t  TXDATA5              :1;
            __IO  uint32_t  TXDATA6              :1;
            __IO  uint32_t  TXDATA7              :1;
            __IO  uint32_t  TXDATA8              :1;
            __IO  uint32_t  TXDATA9              :1;
            __IO  uint32_t  TXDATA10             :1;
            __IO  uint32_t  TXDATA11             :1;
            __IO  uint32_t  TXDATA12             :1;
            __IO  uint32_t  TXDATA13             :1;
            __IO  uint32_t  TXDATA14             :1;
            __IO  uint32_t  TXDATA15             :1;
            __IO  uint32_t  TXDATA16             :1;
            __IO  uint32_t  TXDATA17             :1;
            __IO  uint32_t  TXDATA18             :1;
            __IO  uint32_t  TXDATA19             :1;
            __IO  uint32_t  TXDATA20             :1;
            __IO  uint32_t  TXDATA21             :1;
            __IO  uint32_t  TXDATA22             :1;
            __IO  uint32_t  TXDATA23             :1;
            __IO  uint32_t  TXDATA24             :1;
            __IO  uint32_t  TXDATA25             :1;
            __IO  uint32_t  TXDATA26             :1;
            __IO  uint32_t  TXDATA27             :1;
            __IO  uint32_t  TXDATA28             :1;
            __IO  uint32_t  TXDATA29             :1;
            __IO  uint32_t  TXDATA30             :1;
            __IO  uint32_t  TXDATA31             :1;
        };
    };
} stc_hsspi_txfifo10_field_t;

typedef struct stc_hsspi_txfifo11_field
{
    union {
        struct {
            __IO  uint32_t  TXDATA               :32;
        };
        struct {
            __IO  uint32_t  TXDATA0              :1;
            __IO  uint32_t  TXDATA1              :1;
            __IO  uint32_t  TXDATA2              :1;
            __IO  uint32_t  TXDATA3              :1;
            __IO  uint32_t  TXDATA4              :1;
            __IO  uint32_t  TXDATA5              :1;
            __IO  uint32_t  TXDATA6              :1;
            __IO  uint32_t  TXDATA7              :1;
            __IO  uint32_t  TXDATA8              :1;
            __IO  uint32_t  TXDATA9              :1;
            __IO  uint32_t  TXDATA10             :1;
            __IO  uint32_t  TXDATA11             :1;
            __IO  uint32_t  TXDATA12             :1;
            __IO  uint32_t  TXDATA13             :1;
            __IO  uint32_t  TXDATA14             :1;
            __IO  uint32_t  TXDATA15             :1;
            __IO  uint32_t  TXDATA16             :1;
            __IO  uint32_t  TXDATA17             :1;
            __IO  uint32_t  TXDATA18             :1;
            __IO  uint32_t  TXDATA19             :1;
            __IO  uint32_t  TXDATA20             :1;
            __IO  uint32_t  TXDATA21             :1;
            __IO  uint32_t  TXDATA22             :1;
            __IO  uint32_t  TXDATA23             :1;
            __IO  uint32_t  TXDATA24             :1;
            __IO  uint32_t  TXDATA25             :1;
            __IO  uint32_t  TXDATA26             :1;
            __IO  uint32_t  TXDATA27             :1;
            __IO  uint32_t  TXDATA28             :1;
            __IO  uint32_t  TXDATA29             :1;
            __IO  uint32_t  TXDATA30             :1;
            __IO  uint32_t  TXDATA31             :1;
        };
    };
} stc_hsspi_txfifo11_field_t;

typedef struct stc_hsspi_txfifo12_field
{
    union {
        struct {
            __IO  uint32_t  TXDATA               :32;
        };
        struct {
            __IO  uint32_t  TXDATA0              :1;
            __IO  uint32_t  TXDATA1              :1;
            __IO  uint32_t  TXDATA2              :1;
            __IO  uint32_t  TXDATA3              :1;
            __IO  uint32_t  TXDATA4              :1;
            __IO  uint32_t  TXDATA5              :1;
            __IO  uint32_t  TXDATA6              :1;
            __IO  uint32_t  TXDATA7              :1;
            __IO  uint32_t  TXDATA8              :1;
            __IO  uint32_t  TXDATA9              :1;
            __IO  uint32_t  TXDATA10             :1;
            __IO  uint32_t  TXDATA11             :1;
            __IO  uint32_t  TXDATA12             :1;
            __IO  uint32_t  TXDATA13             :1;
            __IO  uint32_t  TXDATA14             :1;
            __IO  uint32_t  TXDATA15             :1;
            __IO  uint32_t  TXDATA16             :1;
            __IO  uint32_t  TXDATA17             :1;
            __IO  uint32_t  TXDATA18             :1;
            __IO  uint32_t  TXDATA19             :1;
            __IO  uint32_t  TXDATA20             :1;
            __IO  uint32_t  TXDATA21             :1;
            __IO  uint32_t  TXDATA22             :1;
            __IO  uint32_t  TXDATA23             :1;
            __IO  uint32_t  TXDATA24             :1;
            __IO  uint32_t  TXDATA25             :1;
            __IO  uint32_t  TXDATA26             :1;
            __IO  uint32_t  TXDATA27             :1;
            __IO  uint32_t  TXDATA28             :1;
            __IO  uint32_t  TXDATA29             :1;
            __IO  uint32_t  TXDATA30             :1;
            __IO  uint32_t  TXDATA31             :1;
        };
    };
} stc_hsspi_txfifo12_field_t;

typedef struct stc_hsspi_txfifo13_field
{
    union {
        struct {
            __IO  uint32_t  TXDATA               :32;
        };
        struct {
            __IO  uint32_t  TXDATA0              :1;
            __IO  uint32_t  TXDATA1              :1;
            __IO  uint32_t  TXDATA2              :1;
            __IO  uint32_t  TXDATA3              :1;
            __IO  uint32_t  TXDATA4              :1;
            __IO  uint32_t  TXDATA5              :1;
            __IO  uint32_t  TXDATA6              :1;
            __IO  uint32_t  TXDATA7              :1;
            __IO  uint32_t  TXDATA8              :1;
            __IO  uint32_t  TXDATA9              :1;
            __IO  uint32_t  TXDATA10             :1;
            __IO  uint32_t  TXDATA11             :1;
            __IO  uint32_t  TXDATA12             :1;
            __IO  uint32_t  TXDATA13             :1;
            __IO  uint32_t  TXDATA14             :1;
            __IO  uint32_t  TXDATA15             :1;
            __IO  uint32_t  TXDATA16             :1;
            __IO  uint32_t  TXDATA17             :1;
            __IO  uint32_t  TXDATA18             :1;
            __IO  uint32_t  TXDATA19             :1;
            __IO  uint32_t  TXDATA20             :1;
            __IO  uint32_t  TXDATA21             :1;
            __IO  uint32_t  TXDATA22             :1;
            __IO  uint32_t  TXDATA23             :1;
            __IO  uint32_t  TXDATA24             :1;
            __IO  uint32_t  TXDATA25             :1;
            __IO  uint32_t  TXDATA26             :1;
            __IO  uint32_t  TXDATA27             :1;
            __IO  uint32_t  TXDATA28             :1;
            __IO  uint32_t  TXDATA29             :1;
            __IO  uint32_t  TXDATA30             :1;
            __IO  uint32_t  TXDATA31             :1;
        };
    };
} stc_hsspi_txfifo13_field_t;

typedef struct stc_hsspi_txfifo14_field
{
    union {
        struct {
            __IO  uint32_t  TXDATA               :32;
        };
        struct {
            __IO  uint32_t  TXDATA0              :1;
            __IO  uint32_t  TXDATA1              :1;
            __IO  uint32_t  TXDATA2              :1;
            __IO  uint32_t  TXDATA3              :1;
            __IO  uint32_t  TXDATA4              :1;
            __IO  uint32_t  TXDATA5              :1;
            __IO  uint32_t  TXDATA6              :1;
            __IO  uint32_t  TXDATA7              :1;
            __IO  uint32_t  TXDATA8              :1;
            __IO  uint32_t  TXDATA9              :1;
            __IO  uint32_t  TXDATA10             :1;
            __IO  uint32_t  TXDATA11             :1;
            __IO  uint32_t  TXDATA12             :1;
            __IO  uint32_t  TXDATA13             :1;
            __IO  uint32_t  TXDATA14             :1;
            __IO  uint32_t  TXDATA15             :1;
            __IO  uint32_t  TXDATA16             :1;
            __IO  uint32_t  TXDATA17             :1;
            __IO  uint32_t  TXDATA18             :1;
            __IO  uint32_t  TXDATA19             :1;
            __IO  uint32_t  TXDATA20             :1;
            __IO  uint32_t  TXDATA21             :1;
            __IO  uint32_t  TXDATA22             :1;
            __IO  uint32_t  TXDATA23             :1;
            __IO  uint32_t  TXDATA24             :1;
            __IO  uint32_t  TXDATA25             :1;
            __IO  uint32_t  TXDATA26             :1;
            __IO  uint32_t  TXDATA27             :1;
            __IO  uint32_t  TXDATA28             :1;
            __IO  uint32_t  TXDATA29             :1;
            __IO  uint32_t  TXDATA30             :1;
            __IO  uint32_t  TXDATA31             :1;
        };
    };
} stc_hsspi_txfifo14_field_t;

typedef struct stc_hsspi_txfifo15_field
{
    union {
        struct {
            __IO  uint32_t  TXDATA               :32;
        };
        struct {
            __IO  uint32_t  TXDATA0              :1;
            __IO  uint32_t  TXDATA1              :1;
            __IO  uint32_t  TXDATA2              :1;
            __IO  uint32_t  TXDATA3              :1;
            __IO  uint32_t  TXDATA4              :1;
            __IO  uint32_t  TXDATA5              :1;
            __IO  uint32_t  TXDATA6              :1;
            __IO  uint32_t  TXDATA7              :1;
            __IO  uint32_t  TXDATA8              :1;
            __IO  uint32_t  TXDATA9              :1;
            __IO  uint32_t  TXDATA10             :1;
            __IO  uint32_t  TXDATA11             :1;
            __IO  uint32_t  TXDATA12             :1;
            __IO  uint32_t  TXDATA13             :1;
            __IO  uint32_t  TXDATA14             :1;
            __IO  uint32_t  TXDATA15             :1;
            __IO  uint32_t  TXDATA16             :1;
            __IO  uint32_t  TXDATA17             :1;
            __IO  uint32_t  TXDATA18             :1;
            __IO  uint32_t  TXDATA19             :1;
            __IO  uint32_t  TXDATA20             :1;
            __IO  uint32_t  TXDATA21             :1;
            __IO  uint32_t  TXDATA22             :1;
            __IO  uint32_t  TXDATA23             :1;
            __IO  uint32_t  TXDATA24             :1;
            __IO  uint32_t  TXDATA25             :1;
            __IO  uint32_t  TXDATA26             :1;
            __IO  uint32_t  TXDATA27             :1;
            __IO  uint32_t  TXDATA28             :1;
            __IO  uint32_t  TXDATA29             :1;
            __IO  uint32_t  TXDATA30             :1;
            __IO  uint32_t  TXDATA31             :1;
        };
    };
} stc_hsspi_txfifo15_field_t;

typedef struct stc_hsspi_rxfifo0_field
{
    union {
        struct {
            __IO  uint32_t  RXDATA               :32;
        };
        struct {
            __IO  uint32_t  RXDATA0              :1;
            __IO  uint32_t  RXDATA1              :1;
            __IO  uint32_t  RXDATA2              :1;
            __IO  uint32_t  RXDATA3              :1;
            __IO  uint32_t  RXDATA4              :1;
            __IO  uint32_t  RXDATA5              :1;
            __IO  uint32_t  RXDATA6              :1;
            __IO  uint32_t  RXDATA7              :1;
            __IO  uint32_t  RXDATA8              :1;
            __IO  uint32_t  RXDATA9              :1;
            __IO  uint32_t  RXDATA10             :1;
            __IO  uint32_t  RXDATA11             :1;
            __IO  uint32_t  RXDATA12             :1;
            __IO  uint32_t  RXDATA13             :1;
            __IO  uint32_t  RXDATA14             :1;
            __IO  uint32_t  RXDATA15             :1;
            __IO  uint32_t  RXDATA16             :1;
            __IO  uint32_t  RXDATA17             :1;
            __IO  uint32_t  RXDATA18             :1;
            __IO  uint32_t  RXDATA19             :1;
            __IO  uint32_t  RXDATA20             :1;
            __IO  uint32_t  RXDATA21             :1;
            __IO  uint32_t  RXDATA22             :1;
            __IO  uint32_t  RXDATA23             :1;
            __IO  uint32_t  RXDATA24             :1;
            __IO  uint32_t  RXDATA25             :1;
            __IO  uint32_t  RXDATA26             :1;
            __IO  uint32_t  RXDATA27             :1;
            __IO  uint32_t  RXDATA28             :1;
            __IO  uint32_t  RXDATA29             :1;
            __IO  uint32_t  RXDATA30             :1;
            __IO  uint32_t  RXDATA31             :1;
        };
    };
} stc_hsspi_rxfifo0_field_t;

typedef struct stc_hsspi_rxfifo1_field
{
    union {
        struct {
            __IO  uint32_t  RXDATA               :32;
        };
        struct {
            __IO  uint32_t  RXDATA0              :1;
            __IO  uint32_t  RXDATA1              :1;
            __IO  uint32_t  RXDATA2              :1;
            __IO  uint32_t  RXDATA3              :1;
            __IO  uint32_t  RXDATA4              :1;
            __IO  uint32_t  RXDATA5              :1;
            __IO  uint32_t  RXDATA6              :1;
            __IO  uint32_t  RXDATA7              :1;
            __IO  uint32_t  RXDATA8              :1;
            __IO  uint32_t  RXDATA9              :1;
            __IO  uint32_t  RXDATA10             :1;
            __IO  uint32_t  RXDATA11             :1;
            __IO  uint32_t  RXDATA12             :1;
            __IO  uint32_t  RXDATA13             :1;
            __IO  uint32_t  RXDATA14             :1;
            __IO  uint32_t  RXDATA15             :1;
            __IO  uint32_t  RXDATA16             :1;
            __IO  uint32_t  RXDATA17             :1;
            __IO  uint32_t  RXDATA18             :1;
            __IO  uint32_t  RXDATA19             :1;
            __IO  uint32_t  RXDATA20             :1;
            __IO  uint32_t  RXDATA21             :1;
            __IO  uint32_t  RXDATA22             :1;
            __IO  uint32_t  RXDATA23             :1;
            __IO  uint32_t  RXDATA24             :1;
            __IO  uint32_t  RXDATA25             :1;
            __IO  uint32_t  RXDATA26             :1;
            __IO  uint32_t  RXDATA27             :1;
            __IO  uint32_t  RXDATA28             :1;
            __IO  uint32_t  RXDATA29             :1;
            __IO  uint32_t  RXDATA30             :1;
            __IO  uint32_t  RXDATA31             :1;
        };
    };
} stc_hsspi_rxfifo1_field_t;

typedef struct stc_hsspi_rxfifo2_field
{
    union {
        struct {
            __IO  uint32_t  RXDATA               :32;
        };
        struct {
            __IO  uint32_t  RXDATA0              :1;
            __IO  uint32_t  RXDATA1              :1;
            __IO  uint32_t  RXDATA2              :1;
            __IO  uint32_t  RXDATA3              :1;
            __IO  uint32_t  RXDATA4              :1;
            __IO  uint32_t  RXDATA5              :1;
            __IO  uint32_t  RXDATA6              :1;
            __IO  uint32_t  RXDATA7              :1;
            __IO  uint32_t  RXDATA8              :1;
            __IO  uint32_t  RXDATA9              :1;
            __IO  uint32_t  RXDATA10             :1;
            __IO  uint32_t  RXDATA11             :1;
            __IO  uint32_t  RXDATA12             :1;
            __IO  uint32_t  RXDATA13             :1;
            __IO  uint32_t  RXDATA14             :1;
            __IO  uint32_t  RXDATA15             :1;
            __IO  uint32_t  RXDATA16             :1;
            __IO  uint32_t  RXDATA17             :1;
            __IO  uint32_t  RXDATA18             :1;
            __IO  uint32_t  RXDATA19             :1;
            __IO  uint32_t  RXDATA20             :1;
            __IO  uint32_t  RXDATA21             :1;
            __IO  uint32_t  RXDATA22             :1;
            __IO  uint32_t  RXDATA23             :1;
            __IO  uint32_t  RXDATA24             :1;
            __IO  uint32_t  RXDATA25             :1;
            __IO  uint32_t  RXDATA26             :1;
            __IO  uint32_t  RXDATA27             :1;
            __IO  uint32_t  RXDATA28             :1;
            __IO  uint32_t  RXDATA29             :1;
            __IO  uint32_t  RXDATA30             :1;
            __IO  uint32_t  RXDATA31             :1;
        };
    };
} stc_hsspi_rxfifo2_field_t;

typedef struct stc_hsspi_rxfifo3_field
{
    union {
        struct {
            __IO  uint32_t  RXDATA               :32;
        };
        struct {
            __IO  uint32_t  RXDATA0              :1;
            __IO  uint32_t  RXDATA1              :1;
            __IO  uint32_t  RXDATA2              :1;
            __IO  uint32_t  RXDATA3              :1;
            __IO  uint32_t  RXDATA4              :1;
            __IO  uint32_t  RXDATA5              :1;
            __IO  uint32_t  RXDATA6              :1;
            __IO  uint32_t  RXDATA7              :1;
            __IO  uint32_t  RXDATA8              :1;
            __IO  uint32_t  RXDATA9              :1;
            __IO  uint32_t  RXDATA10             :1;
            __IO  uint32_t  RXDATA11             :1;
            __IO  uint32_t  RXDATA12             :1;
            __IO  uint32_t  RXDATA13             :1;
            __IO  uint32_t  RXDATA14             :1;
            __IO  uint32_t  RXDATA15             :1;
            __IO  uint32_t  RXDATA16             :1;
            __IO  uint32_t  RXDATA17             :1;
            __IO  uint32_t  RXDATA18             :1;
            __IO  uint32_t  RXDATA19             :1;
            __IO  uint32_t  RXDATA20             :1;
            __IO  uint32_t  RXDATA21             :1;
            __IO  uint32_t  RXDATA22             :1;
            __IO  uint32_t  RXDATA23             :1;
            __IO  uint32_t  RXDATA24             :1;
            __IO  uint32_t  RXDATA25             :1;
            __IO  uint32_t  RXDATA26             :1;
            __IO  uint32_t  RXDATA27             :1;
            __IO  uint32_t  RXDATA28             :1;
            __IO  uint32_t  RXDATA29             :1;
            __IO  uint32_t  RXDATA30             :1;
            __IO  uint32_t  RXDATA31             :1;
        };
    };
} stc_hsspi_rxfifo3_field_t;

typedef struct stc_hsspi_rxfifo4_field
{
    union {
        struct {
            __IO  uint32_t  RXDATA               :32;
        };
        struct {
            __IO  uint32_t  RXDATA0              :1;
            __IO  uint32_t  RXDATA1              :1;
            __IO  uint32_t  RXDATA2              :1;
            __IO  uint32_t  RXDATA3              :1;
            __IO  uint32_t  RXDATA4              :1;
            __IO  uint32_t  RXDATA5              :1;
            __IO  uint32_t  RXDATA6              :1;
            __IO  uint32_t  RXDATA7              :1;
            __IO  uint32_t  RXDATA8              :1;
            __IO  uint32_t  RXDATA9              :1;
            __IO  uint32_t  RXDATA10             :1;
            __IO  uint32_t  RXDATA11             :1;
            __IO  uint32_t  RXDATA12             :1;
            __IO  uint32_t  RXDATA13             :1;
            __IO  uint32_t  RXDATA14             :1;
            __IO  uint32_t  RXDATA15             :1;
            __IO  uint32_t  RXDATA16             :1;
            __IO  uint32_t  RXDATA17             :1;
            __IO  uint32_t  RXDATA18             :1;
            __IO  uint32_t  RXDATA19             :1;
            __IO  uint32_t  RXDATA20             :1;
            __IO  uint32_t  RXDATA21             :1;
            __IO  uint32_t  RXDATA22             :1;
            __IO  uint32_t  RXDATA23             :1;
            __IO  uint32_t  RXDATA24             :1;
            __IO  uint32_t  RXDATA25             :1;
            __IO  uint32_t  RXDATA26             :1;
            __IO  uint32_t  RXDATA27             :1;
            __IO  uint32_t  RXDATA28             :1;
            __IO  uint32_t  RXDATA29             :1;
            __IO  uint32_t  RXDATA30             :1;
            __IO  uint32_t  RXDATA31             :1;
        };
    };
} stc_hsspi_rxfifo4_field_t;

typedef struct stc_hsspi_rxfifo5_field
{
    union {
        struct {
            __IO  uint32_t  RXDATA               :32;
        };
        struct {
            __IO  uint32_t  RXDATA0              :1;
            __IO  uint32_t  RXDATA1              :1;
            __IO  uint32_t  RXDATA2              :1;
            __IO  uint32_t  RXDATA3              :1;
            __IO  uint32_t  RXDATA4              :1;
            __IO  uint32_t  RXDATA5              :1;
            __IO  uint32_t  RXDATA6              :1;
            __IO  uint32_t  RXDATA7              :1;
            __IO  uint32_t  RXDATA8              :1;
            __IO  uint32_t  RXDATA9              :1;
            __IO  uint32_t  RXDATA10             :1;
            __IO  uint32_t  RXDATA11             :1;
            __IO  uint32_t  RXDATA12             :1;
            __IO  uint32_t  RXDATA13             :1;
            __IO  uint32_t  RXDATA14             :1;
            __IO  uint32_t  RXDATA15             :1;
            __IO  uint32_t  RXDATA16             :1;
            __IO  uint32_t  RXDATA17             :1;
            __IO  uint32_t  RXDATA18             :1;
            __IO  uint32_t  RXDATA19             :1;
            __IO  uint32_t  RXDATA20             :1;
            __IO  uint32_t  RXDATA21             :1;
            __IO  uint32_t  RXDATA22             :1;
            __IO  uint32_t  RXDATA23             :1;
            __IO  uint32_t  RXDATA24             :1;
            __IO  uint32_t  RXDATA25             :1;
            __IO  uint32_t  RXDATA26             :1;
            __IO  uint32_t  RXDATA27             :1;
            __IO  uint32_t  RXDATA28             :1;
            __IO  uint32_t  RXDATA29             :1;
            __IO  uint32_t  RXDATA30             :1;
            __IO  uint32_t  RXDATA31             :1;
        };
    };
} stc_hsspi_rxfifo5_field_t;

typedef struct stc_hsspi_rxfifo6_field
{
    union {
        struct {
            __IO  uint32_t  RXDATA               :32;
        };
        struct {
            __IO  uint32_t  RXDATA0              :1;
            __IO  uint32_t  RXDATA1              :1;
            __IO  uint32_t  RXDATA2              :1;
            __IO  uint32_t  RXDATA3              :1;
            __IO  uint32_t  RXDATA4              :1;
            __IO  uint32_t  RXDATA5              :1;
            __IO  uint32_t  RXDATA6              :1;
            __IO  uint32_t  RXDATA7              :1;
            __IO  uint32_t  RXDATA8              :1;
            __IO  uint32_t  RXDATA9              :1;
            __IO  uint32_t  RXDATA10             :1;
            __IO  uint32_t  RXDATA11             :1;
            __IO  uint32_t  RXDATA12             :1;
            __IO  uint32_t  RXDATA13             :1;
            __IO  uint32_t  RXDATA14             :1;
            __IO  uint32_t  RXDATA15             :1;
            __IO  uint32_t  RXDATA16             :1;
            __IO  uint32_t  RXDATA17             :1;
            __IO  uint32_t  RXDATA18             :1;
            __IO  uint32_t  RXDATA19             :1;
            __IO  uint32_t  RXDATA20             :1;
            __IO  uint32_t  RXDATA21             :1;
            __IO  uint32_t  RXDATA22             :1;
            __IO  uint32_t  RXDATA23             :1;
            __IO  uint32_t  RXDATA24             :1;
            __IO  uint32_t  RXDATA25             :1;
            __IO  uint32_t  RXDATA26             :1;
            __IO  uint32_t  RXDATA27             :1;
            __IO  uint32_t  RXDATA28             :1;
            __IO  uint32_t  RXDATA29             :1;
            __IO  uint32_t  RXDATA30             :1;
            __IO  uint32_t  RXDATA31             :1;
        };
    };
} stc_hsspi_rxfifo6_field_t;

typedef struct stc_hsspi_rxfifo7_field
{
    union {
        struct {
            __IO  uint32_t  RXDATA               :32;
        };
        struct {
            __IO  uint32_t  RXDATA0              :1;
            __IO  uint32_t  RXDATA1              :1;
            __IO  uint32_t  RXDATA2              :1;
            __IO  uint32_t  RXDATA3              :1;
            __IO  uint32_t  RXDATA4              :1;
            __IO  uint32_t  RXDATA5              :1;
            __IO  uint32_t  RXDATA6              :1;
            __IO  uint32_t  RXDATA7              :1;
            __IO  uint32_t  RXDATA8              :1;
            __IO  uint32_t  RXDATA9              :1;
            __IO  uint32_t  RXDATA10             :1;
            __IO  uint32_t  RXDATA11             :1;
            __IO  uint32_t  RXDATA12             :1;
            __IO  uint32_t  RXDATA13             :1;
            __IO  uint32_t  RXDATA14             :1;
            __IO  uint32_t  RXDATA15             :1;
            __IO  uint32_t  RXDATA16             :1;
            __IO  uint32_t  RXDATA17             :1;
            __IO  uint32_t  RXDATA18             :1;
            __IO  uint32_t  RXDATA19             :1;
            __IO  uint32_t  RXDATA20             :1;
            __IO  uint32_t  RXDATA21             :1;
            __IO  uint32_t  RXDATA22             :1;
            __IO  uint32_t  RXDATA23             :1;
            __IO  uint32_t  RXDATA24             :1;
            __IO  uint32_t  RXDATA25             :1;
            __IO  uint32_t  RXDATA26             :1;
            __IO  uint32_t  RXDATA27             :1;
            __IO  uint32_t  RXDATA28             :1;
            __IO  uint32_t  RXDATA29             :1;
            __IO  uint32_t  RXDATA30             :1;
            __IO  uint32_t  RXDATA31             :1;
        };
    };
} stc_hsspi_rxfifo7_field_t;

typedef struct stc_hsspi_rxfifo8_field
{
    union {
        struct {
            __IO  uint32_t  RXDATA               :32;
        };
        struct {
            __IO  uint32_t  RXDATA0              :1;
            __IO  uint32_t  RXDATA1              :1;
            __IO  uint32_t  RXDATA2              :1;
            __IO  uint32_t  RXDATA3              :1;
            __IO  uint32_t  RXDATA4              :1;
            __IO  uint32_t  RXDATA5              :1;
            __IO  uint32_t  RXDATA6              :1;
            __IO  uint32_t  RXDATA7              :1;
            __IO  uint32_t  RXDATA8              :1;
            __IO  uint32_t  RXDATA9              :1;
            __IO  uint32_t  RXDATA10             :1;
            __IO  uint32_t  RXDATA11             :1;
            __IO  uint32_t  RXDATA12             :1;
            __IO  uint32_t  RXDATA13             :1;
            __IO  uint32_t  RXDATA14             :1;
            __IO  uint32_t  RXDATA15             :1;
            __IO  uint32_t  RXDATA16             :1;
            __IO  uint32_t  RXDATA17             :1;
            __IO  uint32_t  RXDATA18             :1;
            __IO  uint32_t  RXDATA19             :1;
            __IO  uint32_t  RXDATA20             :1;
            __IO  uint32_t  RXDATA21             :1;
            __IO  uint32_t  RXDATA22             :1;
            __IO  uint32_t  RXDATA23             :1;
            __IO  uint32_t  RXDATA24             :1;
            __IO  uint32_t  RXDATA25             :1;
            __IO  uint32_t  RXDATA26             :1;
            __IO  uint32_t  RXDATA27             :1;
            __IO  uint32_t  RXDATA28             :1;
            __IO  uint32_t  RXDATA29             :1;
            __IO  uint32_t  RXDATA30             :1;
            __IO  uint32_t  RXDATA31             :1;
        };
    };
} stc_hsspi_rxfifo8_field_t;

typedef struct stc_hsspi_rxfifo9_field
{
    union {
        struct {
            __IO  uint32_t  RXDATA               :32;
        };
        struct {
            __IO  uint32_t  RXDATA0              :1;
            __IO  uint32_t  RXDATA1              :1;
            __IO  uint32_t  RXDATA2              :1;
            __IO  uint32_t  RXDATA3              :1;
            __IO  uint32_t  RXDATA4              :1;
            __IO  uint32_t  RXDATA5              :1;
            __IO  uint32_t  RXDATA6              :1;
            __IO  uint32_t  RXDATA7              :1;
            __IO  uint32_t  RXDATA8              :1;
            __IO  uint32_t  RXDATA9              :1;
            __IO  uint32_t  RXDATA10             :1;
            __IO  uint32_t  RXDATA11             :1;
            __IO  uint32_t  RXDATA12             :1;
            __IO  uint32_t  RXDATA13             :1;
            __IO  uint32_t  RXDATA14             :1;
            __IO  uint32_t  RXDATA15             :1;
            __IO  uint32_t  RXDATA16             :1;
            __IO  uint32_t  RXDATA17             :1;
            __IO  uint32_t  RXDATA18             :1;
            __IO  uint32_t  RXDATA19             :1;
            __IO  uint32_t  RXDATA20             :1;
            __IO  uint32_t  RXDATA21             :1;
            __IO  uint32_t  RXDATA22             :1;
            __IO  uint32_t  RXDATA23             :1;
            __IO  uint32_t  RXDATA24             :1;
            __IO  uint32_t  RXDATA25             :1;
            __IO  uint32_t  RXDATA26             :1;
            __IO  uint32_t  RXDATA27             :1;
            __IO  uint32_t  RXDATA28             :1;
            __IO  uint32_t  RXDATA29             :1;
            __IO  uint32_t  RXDATA30             :1;
            __IO  uint32_t  RXDATA31             :1;
        };
    };
} stc_hsspi_rxfifo9_field_t;

typedef struct stc_hsspi_rxfifo10_field
{
    union {
        struct {
            __IO  uint32_t  RXDATA               :32;
        };
        struct {
            __IO  uint32_t  RXDATA0              :1;
            __IO  uint32_t  RXDATA1              :1;
            __IO  uint32_t  RXDATA2              :1;
            __IO  uint32_t  RXDATA3              :1;
            __IO  uint32_t  RXDATA4              :1;
            __IO  uint32_t  RXDATA5              :1;
            __IO  uint32_t  RXDATA6              :1;
            __IO  uint32_t  RXDATA7              :1;
            __IO  uint32_t  RXDATA8              :1;
            __IO  uint32_t  RXDATA9              :1;
            __IO  uint32_t  RXDATA10             :1;
            __IO  uint32_t  RXDATA11             :1;
            __IO  uint32_t  RXDATA12             :1;
            __IO  uint32_t  RXDATA13             :1;
            __IO  uint32_t  RXDATA14             :1;
            __IO  uint32_t  RXDATA15             :1;
            __IO  uint32_t  RXDATA16             :1;
            __IO  uint32_t  RXDATA17             :1;
            __IO  uint32_t  RXDATA18             :1;
            __IO  uint32_t  RXDATA19             :1;
            __IO  uint32_t  RXDATA20             :1;
            __IO  uint32_t  RXDATA21             :1;
            __IO  uint32_t  RXDATA22             :1;
            __IO  uint32_t  RXDATA23             :1;
            __IO  uint32_t  RXDATA24             :1;
            __IO  uint32_t  RXDATA25             :1;
            __IO  uint32_t  RXDATA26             :1;
            __IO  uint32_t  RXDATA27             :1;
            __IO  uint32_t  RXDATA28             :1;
            __IO  uint32_t  RXDATA29             :1;
            __IO  uint32_t  RXDATA30             :1;
            __IO  uint32_t  RXDATA31             :1;
        };
    };
} stc_hsspi_rxfifo10_field_t;

typedef struct stc_hsspi_rxfifo11_field
{
    union {
        struct {
            __IO  uint32_t  RXDATA               :32;
        };
        struct {
            __IO  uint32_t  RXDATA0              :1;
            __IO  uint32_t  RXDATA1              :1;
            __IO  uint32_t  RXDATA2              :1;
            __IO  uint32_t  RXDATA3              :1;
            __IO  uint32_t  RXDATA4              :1;
            __IO  uint32_t  RXDATA5              :1;
            __IO  uint32_t  RXDATA6              :1;
            __IO  uint32_t  RXDATA7              :1;
            __IO  uint32_t  RXDATA8              :1;
            __IO  uint32_t  RXDATA9              :1;
            __IO  uint32_t  RXDATA10             :1;
            __IO  uint32_t  RXDATA11             :1;
            __IO  uint32_t  RXDATA12             :1;
            __IO  uint32_t  RXDATA13             :1;
            __IO  uint32_t  RXDATA14             :1;
            __IO  uint32_t  RXDATA15             :1;
            __IO  uint32_t  RXDATA16             :1;
            __IO  uint32_t  RXDATA17             :1;
            __IO  uint32_t  RXDATA18             :1;
            __IO  uint32_t  RXDATA19             :1;
            __IO  uint32_t  RXDATA20             :1;
            __IO  uint32_t  RXDATA21             :1;
            __IO  uint32_t  RXDATA22             :1;
            __IO  uint32_t  RXDATA23             :1;
            __IO  uint32_t  RXDATA24             :1;
            __IO  uint32_t  RXDATA25             :1;
            __IO  uint32_t  RXDATA26             :1;
            __IO  uint32_t  RXDATA27             :1;
            __IO  uint32_t  RXDATA28             :1;
            __IO  uint32_t  RXDATA29             :1;
            __IO  uint32_t  RXDATA30             :1;
            __IO  uint32_t  RXDATA31             :1;
        };
    };
} stc_hsspi_rxfifo11_field_t;

typedef struct stc_hsspi_rxfifo12_field
{
    union {
        struct {
            __IO  uint32_t  RXDATA               :32;
        };
        struct {
            __IO  uint32_t  RXDATA0              :1;
            __IO  uint32_t  RXDATA1              :1;
            __IO  uint32_t  RXDATA2              :1;
            __IO  uint32_t  RXDATA3              :1;
            __IO  uint32_t  RXDATA4              :1;
            __IO  uint32_t  RXDATA5              :1;
            __IO  uint32_t  RXDATA6              :1;
            __IO  uint32_t  RXDATA7              :1;
            __IO  uint32_t  RXDATA8              :1;
            __IO  uint32_t  RXDATA9              :1;
            __IO  uint32_t  RXDATA10             :1;
            __IO  uint32_t  RXDATA11             :1;
            __IO  uint32_t  RXDATA12             :1;
            __IO  uint32_t  RXDATA13             :1;
            __IO  uint32_t  RXDATA14             :1;
            __IO  uint32_t  RXDATA15             :1;
            __IO  uint32_t  RXDATA16             :1;
            __IO  uint32_t  RXDATA17             :1;
            __IO  uint32_t  RXDATA18             :1;
            __IO  uint32_t  RXDATA19             :1;
            __IO  uint32_t  RXDATA20             :1;
            __IO  uint32_t  RXDATA21             :1;
            __IO  uint32_t  RXDATA22             :1;
            __IO  uint32_t  RXDATA23             :1;
            __IO  uint32_t  RXDATA24             :1;
            __IO  uint32_t  RXDATA25             :1;
            __IO  uint32_t  RXDATA26             :1;
            __IO  uint32_t  RXDATA27             :1;
            __IO  uint32_t  RXDATA28             :1;
            __IO  uint32_t  RXDATA29             :1;
            __IO  uint32_t  RXDATA30             :1;
            __IO  uint32_t  RXDATA31             :1;
        };
    };
} stc_hsspi_rxfifo12_field_t;

typedef struct stc_hsspi_rxfifo13_field
{
    union {
        struct {
            __IO  uint32_t  RXDATA               :32;
        };
        struct {
            __IO  uint32_t  RXDATA0              :1;
            __IO  uint32_t  RXDATA1              :1;
            __IO  uint32_t  RXDATA2              :1;
            __IO  uint32_t  RXDATA3              :1;
            __IO  uint32_t  RXDATA4              :1;
            __IO  uint32_t  RXDATA5              :1;
            __IO  uint32_t  RXDATA6              :1;
            __IO  uint32_t  RXDATA7              :1;
            __IO  uint32_t  RXDATA8              :1;
            __IO  uint32_t  RXDATA9              :1;
            __IO  uint32_t  RXDATA10             :1;
            __IO  uint32_t  RXDATA11             :1;
            __IO  uint32_t  RXDATA12             :1;
            __IO  uint32_t  RXDATA13             :1;
            __IO  uint32_t  RXDATA14             :1;
            __IO  uint32_t  RXDATA15             :1;
            __IO  uint32_t  RXDATA16             :1;
            __IO  uint32_t  RXDATA17             :1;
            __IO  uint32_t  RXDATA18             :1;
            __IO  uint32_t  RXDATA19             :1;
            __IO  uint32_t  RXDATA20             :1;
            __IO  uint32_t  RXDATA21             :1;
            __IO  uint32_t  RXDATA22             :1;
            __IO  uint32_t  RXDATA23             :1;
            __IO  uint32_t  RXDATA24             :1;
            __IO  uint32_t  RXDATA25             :1;
            __IO  uint32_t  RXDATA26             :1;
            __IO  uint32_t  RXDATA27             :1;
            __IO  uint32_t  RXDATA28             :1;
            __IO  uint32_t  RXDATA29             :1;
            __IO  uint32_t  RXDATA30             :1;
            __IO  uint32_t  RXDATA31             :1;
        };
    };
} stc_hsspi_rxfifo13_field_t;

typedef struct stc_hsspi_rxfifo14_field
{
    union {
        struct {
            __IO  uint32_t  RXDATA               :32;
        };
        struct {
            __IO  uint32_t  RXDATA0              :1;
            __IO  uint32_t  RXDATA1              :1;
            __IO  uint32_t  RXDATA2              :1;
            __IO  uint32_t  RXDATA3              :1;
            __IO  uint32_t  RXDATA4              :1;
            __IO  uint32_t  RXDATA5              :1;
            __IO  uint32_t  RXDATA6              :1;
            __IO  uint32_t  RXDATA7              :1;
            __IO  uint32_t  RXDATA8              :1;
            __IO  uint32_t  RXDATA9              :1;
            __IO  uint32_t  RXDATA10             :1;
            __IO  uint32_t  RXDATA11             :1;
            __IO  uint32_t  RXDATA12             :1;
            __IO  uint32_t  RXDATA13             :1;
            __IO  uint32_t  RXDATA14             :1;
            __IO  uint32_t  RXDATA15             :1;
            __IO  uint32_t  RXDATA16             :1;
            __IO  uint32_t  RXDATA17             :1;
            __IO  uint32_t  RXDATA18             :1;
            __IO  uint32_t  RXDATA19             :1;
            __IO  uint32_t  RXDATA20             :1;
            __IO  uint32_t  RXDATA21             :1;
            __IO  uint32_t  RXDATA22             :1;
            __IO  uint32_t  RXDATA23             :1;
            __IO  uint32_t  RXDATA24             :1;
            __IO  uint32_t  RXDATA25             :1;
            __IO  uint32_t  RXDATA26             :1;
            __IO  uint32_t  RXDATA27             :1;
            __IO  uint32_t  RXDATA28             :1;
            __IO  uint32_t  RXDATA29             :1;
            __IO  uint32_t  RXDATA30             :1;
            __IO  uint32_t  RXDATA31             :1;
        };
    };
} stc_hsspi_rxfifo14_field_t;

typedef struct stc_hsspi_rxfifo15_field
{
    union {
        struct {
            __IO  uint32_t  RXDATA               :32;
        };
        struct {
            __IO  uint32_t  RXDATA0              :1;
            __IO  uint32_t  RXDATA1              :1;
            __IO  uint32_t  RXDATA2              :1;
            __IO  uint32_t  RXDATA3              :1;
            __IO  uint32_t  RXDATA4              :1;
            __IO  uint32_t  RXDATA5              :1;
            __IO  uint32_t  RXDATA6              :1;
            __IO  uint32_t  RXDATA7              :1;
            __IO  uint32_t  RXDATA8              :1;
            __IO  uint32_t  RXDATA9              :1;
            __IO  uint32_t  RXDATA10             :1;
            __IO  uint32_t  RXDATA11             :1;
            __IO  uint32_t  RXDATA12             :1;
            __IO  uint32_t  RXDATA13             :1;
            __IO  uint32_t  RXDATA14             :1;
            __IO  uint32_t  RXDATA15             :1;
            __IO  uint32_t  RXDATA16             :1;
            __IO  uint32_t  RXDATA17             :1;
            __IO  uint32_t  RXDATA18             :1;
            __IO  uint32_t  RXDATA19             :1;
            __IO  uint32_t  RXDATA20             :1;
            __IO  uint32_t  RXDATA21             :1;
            __IO  uint32_t  RXDATA22             :1;
            __IO  uint32_t  RXDATA23             :1;
            __IO  uint32_t  RXDATA24             :1;
            __IO  uint32_t  RXDATA25             :1;
            __IO  uint32_t  RXDATA26             :1;
            __IO  uint32_t  RXDATA27             :1;
            __IO  uint32_t  RXDATA28             :1;
            __IO  uint32_t  RXDATA29             :1;
            __IO  uint32_t  RXDATA30             :1;
            __IO  uint32_t  RXDATA31             :1;
        };
    };
} stc_hsspi_rxfifo15_field_t;

typedef struct stc_hsspi_cscfg_field
{
    union {
        struct {
            __IO  uint32_t  SRAM                 :1;
            __IO  uint32_t  MBM                  :2;
            __IO  uint32_t  RESERVED1            :5;
            __IO  uint32_t  SSEL0EN              :1;
            __IO  uint32_t  SSEL1EN              :1;
            __IO  uint32_t  SSEL2EN              :1;
            __IO  uint32_t  SSEL3EN              :1;
            __IO  uint32_t  RESERVED2            :4;
            __IO  uint32_t  MSEL                 :4;
            __IO  uint32_t  RESERVED4            :12;
        };
        struct {
            __IO  uint32_t  RESERVED0            :1;
            __IO  uint32_t  MBM0                 :1;
            __IO  uint32_t  MBM1                 :1;
            __IO  uint32_t  RESERVED3            :13;
            __IO  uint32_t  MSEL0                :1;
            __IO  uint32_t  MSEL1                :1;
            __IO  uint32_t  MSEL2                :1;
            __IO  uint32_t  MSEL3                :1;
            __IO  uint32_t  RESERVED5            :12;
        };
    };
} stc_hsspi_cscfg_field_t;

typedef struct stc_hsspi_csitime_field
{
    union {
        struct {
            __IO  uint32_t  ITIME                :16;
            __IO  uint32_t  RESERVED0            :16;
        };
        struct {
            __IO  uint32_t  ITIME0               :1;
            __IO  uint32_t  ITIME1               :1;
            __IO  uint32_t  ITIME2               :1;
            __IO  uint32_t  ITIME3               :1;
            __IO  uint32_t  ITIME4               :1;
            __IO  uint32_t  ITIME5               :1;
            __IO  uint32_t  ITIME6               :1;
            __IO  uint32_t  ITIME7               :1;
            __IO  uint32_t  ITIME8               :1;
            __IO  uint32_t  ITIME9               :1;
            __IO  uint32_t  ITIME10              :1;
            __IO  uint32_t  ITIME11              :1;
            __IO  uint32_t  ITIME12              :1;
            __IO  uint32_t  ITIME13              :1;
            __IO  uint32_t  ITIME14              :1;
            __IO  uint32_t  ITIME15              :1;
            __IO  uint32_t  RESERVED1            :16;
        };
    };
} stc_hsspi_csitime_field_t;

typedef struct stc_hsspi_csaext_field
{
    union {
        struct {
            __IO  uint32_t  RESERVED0            :13;
            __IO  uint32_t  AEXT                 :19;
        };
        struct {
            __IO  uint32_t  RESERVED1            :13;
            __IO  uint32_t  AEXT0                :1;
            __IO  uint32_t  AEXT1                :1;
            __IO  uint32_t  AEXT2                :1;
            __IO  uint32_t  AEXT3                :1;
            __IO  uint32_t  AEXT4                :1;
            __IO  uint32_t  AEXT5                :1;
            __IO  uint32_t  AEXT6                :1;
            __IO  uint32_t  AEXT7                :1;
            __IO  uint32_t  AEXT8                :1;
            __IO  uint32_t  AEXT9                :1;
            __IO  uint32_t  AEXT10               :1;
            __IO  uint32_t  AEXT11               :1;
            __IO  uint32_t  AEXT12               :1;
            __IO  uint32_t  AEXT13               :1;
            __IO  uint32_t  AEXT14               :1;
            __IO  uint32_t  AEXT15               :1;
            __IO  uint32_t  AEXT16               :1;
            __IO  uint32_t  AEXT17               :1;
            __IO  uint32_t  AEXT18               :1;
        };
    };
} stc_hsspi_csaext_field_t;

typedef struct stc_hsspi_rdcsdc0_field
{
    union {
        struct {
            __IO  uint16_t  DEC                  :1;
            __IO  uint16_t  TRP                  :2;
            __IO  uint16_t  CONT                 :1;
            __IO  uint16_t  RESERVED1            :4;
            __IO  uint16_t  RDCSDATA             :8;
        };
        struct {
            __IO  uint16_t  RESERVED0            :1;
            __IO  uint16_t  TRP0                 :1;
            __IO  uint16_t  TRP1                 :1;
            __IO  uint16_t  RESERVED2            :5;
            __IO  uint16_t  RDCSDATA0            :1;
            __IO  uint16_t  RDCSDATA1            :1;
            __IO  uint16_t  RDCSDATA2            :1;
            __IO  uint16_t  RDCSDATA3            :1;
            __IO  uint16_t  RDCSDATA4            :1;
            __IO  uint16_t  RDCSDATA5            :1;
            __IO  uint16_t  RDCSDATA6            :1;
            __IO  uint16_t  RDCSDATA7            :1;
        };
    };
} stc_hsspi_rdcsdc0_field_t;

typedef struct stc_hsspi_rdcsdc1_field
{
    union {
        struct {
            __IO  uint16_t  DEC                  :1;
            __IO  uint16_t  TRP                  :2;
            __IO  uint16_t  CONT                 :1;
            __IO  uint16_t  RESERVED1            :4;
            __IO  uint16_t  RDCSDATA             :8;
        };
        struct {
            __IO  uint16_t  RESERVED0            :1;
            __IO  uint16_t  TRP0                 :1;
            __IO  uint16_t  TRP1                 :1;
            __IO  uint16_t  RESERVED2            :5;
            __IO  uint16_t  RDCSDATA0            :1;
            __IO  uint16_t  RDCSDATA1            :1;
            __IO  uint16_t  RDCSDATA2            :1;
            __IO  uint16_t  RDCSDATA3            :1;
            __IO  uint16_t  RDCSDATA4            :1;
            __IO  uint16_t  RDCSDATA5            :1;
            __IO  uint16_t  RDCSDATA6            :1;
            __IO  uint16_t  RDCSDATA7            :1;
        };
    };
} stc_hsspi_rdcsdc1_field_t;

typedef struct stc_hsspi_rdcsdc2_field
{
    union {
        struct {
            __IO  uint16_t  DEC                  :1;
            __IO  uint16_t  TRP                  :2;
            __IO  uint16_t  CONT                 :1;
            __IO  uint16_t  RESERVED1            :4;
            __IO  uint16_t  RDCSDATA             :8;
        };
        struct {
            __IO  uint16_t  RESERVED0            :1;
            __IO  uint16_t  TRP0                 :1;
            __IO  uint16_t  TRP1                 :1;
            __IO  uint16_t  RESERVED2            :5;
            __IO  uint16_t  RDCSDATA0            :1;
            __IO  uint16_t  RDCSDATA1            :1;
            __IO  uint16_t  RDCSDATA2            :1;
            __IO  uint16_t  RDCSDATA3            :1;
            __IO  uint16_t  RDCSDATA4            :1;
            __IO  uint16_t  RDCSDATA5            :1;
            __IO  uint16_t  RDCSDATA6            :1;
            __IO  uint16_t  RDCSDATA7            :1;
        };
    };
} stc_hsspi_rdcsdc2_field_t;

typedef struct stc_hsspi_rdcsdc3_field
{
    union {
        struct {
            __IO  uint16_t  DEC                  :1;
            __IO  uint16_t  TRP                  :2;
            __IO  uint16_t  CONT                 :1;
            __IO  uint16_t  RESERVED1            :4;
            __IO  uint16_t  RDCSDATA             :8;
        };
        struct {
            __IO  uint16_t  RESERVED0            :1;
            __IO  uint16_t  TRP0                 :1;
            __IO  uint16_t  TRP1                 :1;
            __IO  uint16_t  RESERVED2            :5;
            __IO  uint16_t  RDCSDATA0            :1;
            __IO  uint16_t  RDCSDATA1            :1;
            __IO  uint16_t  RDCSDATA2            :1;
            __IO  uint16_t  RDCSDATA3            :1;
            __IO  uint16_t  RDCSDATA4            :1;
            __IO  uint16_t  RDCSDATA5            :1;
            __IO  uint16_t  RDCSDATA6            :1;
            __IO  uint16_t  RDCSDATA7            :1;
        };
    };
} stc_hsspi_rdcsdc3_field_t;

typedef struct stc_hsspi_rdcsdc4_field
{
    union {
        struct {
            __IO  uint16_t  DEC                  :1;
            __IO  uint16_t  TRP                  :2;
            __IO  uint16_t  CONT                 :1;
            __IO  uint16_t  RESERVED1            :4;
            __IO  uint16_t  RDCSDATA             :8;
        };
        struct {
            __IO  uint16_t  RESERVED0            :1;
            __IO  uint16_t  TRP0                 :1;
            __IO  uint16_t  TRP1                 :1;
            __IO  uint16_t  RESERVED2            :5;
            __IO  uint16_t  RDCSDATA0            :1;
            __IO  uint16_t  RDCSDATA1            :1;
            __IO  uint16_t  RDCSDATA2            :1;
            __IO  uint16_t  RDCSDATA3            :1;
            __IO  uint16_t  RDCSDATA4            :1;
            __IO  uint16_t  RDCSDATA5            :1;
            __IO  uint16_t  RDCSDATA6            :1;
            __IO  uint16_t  RDCSDATA7            :1;
        };
    };
} stc_hsspi_rdcsdc4_field_t;

typedef struct stc_hsspi_rdcsdc5_field
{
    union {
        struct {
            __IO  uint16_t  DEC                  :1;
            __IO  uint16_t  TRP                  :2;
            __IO  uint16_t  CONT                 :1;
            __IO  uint16_t  RESERVED1            :4;
            __IO  uint16_t  RDCSDATA             :8;
        };
        struct {
            __IO  uint16_t  RESERVED0            :1;
            __IO  uint16_t  TRP0                 :1;
            __IO  uint16_t  TRP1                 :1;
            __IO  uint16_t  RESERVED2            :5;
            __IO  uint16_t  RDCSDATA0            :1;
            __IO  uint16_t  RDCSDATA1            :1;
            __IO  uint16_t  RDCSDATA2            :1;
            __IO  uint16_t  RDCSDATA3            :1;
            __IO  uint16_t  RDCSDATA4            :1;
            __IO  uint16_t  RDCSDATA5            :1;
            __IO  uint16_t  RDCSDATA6            :1;
            __IO  uint16_t  RDCSDATA7            :1;
        };
    };
} stc_hsspi_rdcsdc5_field_t;

typedef struct stc_hsspi_rdcsdc6_field
{
    union {
        struct {
            __IO  uint16_t  DEC                  :1;
            __IO  uint16_t  TRP                  :2;
            __IO  uint16_t  CONT                 :1;
            __IO  uint16_t  RESERVED1            :4;
            __IO  uint16_t  RDCSDATA             :8;
        };
        struct {
            __IO  uint16_t  RESERVED0            :1;
            __IO  uint16_t  TRP0                 :1;
            __IO  uint16_t  TRP1                 :1;
            __IO  uint16_t  RESERVED2            :5;
            __IO  uint16_t  RDCSDATA0            :1;
            __IO  uint16_t  RDCSDATA1            :1;
            __IO  uint16_t  RDCSDATA2            :1;
            __IO  uint16_t  RDCSDATA3            :1;
            __IO  uint16_t  RDCSDATA4            :1;
            __IO  uint16_t  RDCSDATA5            :1;
            __IO  uint16_t  RDCSDATA6            :1;
            __IO  uint16_t  RDCSDATA7            :1;
        };
    };
} stc_hsspi_rdcsdc6_field_t;

typedef struct stc_hsspi_rdcsdc7_field
{
    union {
        struct {
            __IO  uint16_t  DEC                  :1;
            __IO  uint16_t  TRP                  :2;
            __IO  uint16_t  CONT                 :1;
            __IO  uint16_t  RESERVED1            :4;
            __IO  uint16_t  RDCSDATA             :8;
        };
        struct {
            __IO  uint16_t  RESERVED0            :1;
            __IO  uint16_t  TRP0                 :1;
            __IO  uint16_t  TRP1                 :1;
            __IO  uint16_t  RESERVED2            :5;
            __IO  uint16_t  RDCSDATA0            :1;
            __IO  uint16_t  RDCSDATA1            :1;
            __IO  uint16_t  RDCSDATA2            :1;
            __IO  uint16_t  RDCSDATA3            :1;
            __IO  uint16_t  RDCSDATA4            :1;
            __IO  uint16_t  RDCSDATA5            :1;
            __IO  uint16_t  RDCSDATA6            :1;
            __IO  uint16_t  RDCSDATA7            :1;
        };
    };
} stc_hsspi_rdcsdc7_field_t;

typedef struct stc_hsspi_wrcsdc0_field
{
    union {
        struct {
            __IO  uint16_t  DEC                  :1;
            __IO  uint16_t  TRP                  :2;
            __IO  uint16_t  CONT                 :1;
            __IO  uint16_t  RESERVED1            :4;
            __IO  uint16_t  WRCSDATA             :8;
        };
        struct {
            __IO  uint16_t  RESERVED0            :1;
            __IO  uint16_t  TRP0                 :1;
            __IO  uint16_t  TRP1                 :1;
            __IO  uint16_t  RESERVED2            :5;
            __IO  uint16_t  WRCSDATA0            :1;
            __IO  uint16_t  WRCSDATA1            :1;
            __IO  uint16_t  WRCSDATA2            :1;
            __IO  uint16_t  WRCSDATA3            :1;
            __IO  uint16_t  WRCSDATA4            :1;
            __IO  uint16_t  WRCSDATA5            :1;
            __IO  uint16_t  WRCSDATA6            :1;
            __IO  uint16_t  WRCSDATA7            :1;
        };
    };
} stc_hsspi_wrcsdc0_field_t;

typedef struct stc_hsspi_wrcsdc1_field
{
    union {
        struct {
            __IO  uint16_t  DEC                  :1;
            __IO  uint16_t  TRP                  :2;
            __IO  uint16_t  CONT                 :1;
            __IO  uint16_t  RESERVED1            :4;
            __IO  uint16_t  WRCSDATA             :8;
        };
        struct {
            __IO  uint16_t  RESERVED0            :1;
            __IO  uint16_t  TRP0                 :1;
            __IO  uint16_t  TRP1                 :1;
            __IO  uint16_t  RESERVED2            :5;
            __IO  uint16_t  WRCSDATA0            :1;
            __IO  uint16_t  WRCSDATA1            :1;
            __IO  uint16_t  WRCSDATA2            :1;
            __IO  uint16_t  WRCSDATA3            :1;
            __IO  uint16_t  WRCSDATA4            :1;
            __IO  uint16_t  WRCSDATA5            :1;
            __IO  uint16_t  WRCSDATA6            :1;
            __IO  uint16_t  WRCSDATA7            :1;
        };
    };
} stc_hsspi_wrcsdc1_field_t;

typedef struct stc_hsspi_wrcsdc2_field
{
    union {
        struct {
            __IO  uint16_t  DEC                  :1;
            __IO  uint16_t  TRP                  :2;
            __IO  uint16_t  CONT                 :1;
            __IO  uint16_t  RESERVED1            :4;
            __IO  uint16_t  WRCSDATA             :8;
        };
        struct {
            __IO  uint16_t  RESERVED0            :1;
            __IO  uint16_t  TRP0                 :1;
            __IO  uint16_t  TRP1                 :1;
            __IO  uint16_t  RESERVED2            :5;
            __IO  uint16_t  WRCSDATA0            :1;
            __IO  uint16_t  WRCSDATA1            :1;
            __IO  uint16_t  WRCSDATA2            :1;
            __IO  uint16_t  WRCSDATA3            :1;
            __IO  uint16_t  WRCSDATA4            :1;
            __IO  uint16_t  WRCSDATA5            :1;
            __IO  uint16_t  WRCSDATA6            :1;
            __IO  uint16_t  WRCSDATA7            :1;
        };
    };
} stc_hsspi_wrcsdc2_field_t;

typedef struct stc_hsspi_wrcsdc3_field
{
    union {
        struct {
            __IO  uint16_t  DEC                  :1;
            __IO  uint16_t  TRP                  :2;
            __IO  uint16_t  CONT                 :1;
            __IO  uint16_t  RESERVED1            :4;
            __IO  uint16_t  WRCSDATA             :8;
        };
        struct {
            __IO  uint16_t  RESERVED0            :1;
            __IO  uint16_t  TRP0                 :1;
            __IO  uint16_t  TRP1                 :1;
            __IO  uint16_t  RESERVED2            :5;
            __IO  uint16_t  WRCSDATA0            :1;
            __IO  uint16_t  WRCSDATA1            :1;
            __IO  uint16_t  WRCSDATA2            :1;
            __IO  uint16_t  WRCSDATA3            :1;
            __IO  uint16_t  WRCSDATA4            :1;
            __IO  uint16_t  WRCSDATA5            :1;
            __IO  uint16_t  WRCSDATA6            :1;
            __IO  uint16_t  WRCSDATA7            :1;
        };
    };
} stc_hsspi_wrcsdc3_field_t;

typedef struct stc_hsspi_wrcsdc4_field
{
    union {
        struct {
            __IO  uint16_t  DEC                  :1;
            __IO  uint16_t  TRP                  :2;
            __IO  uint16_t  CONT                 :1;
            __IO  uint16_t  RESERVED1            :4;
            __IO  uint16_t  WRCSDATA             :8;
        };
        struct {
            __IO  uint16_t  RESERVED0            :1;
            __IO  uint16_t  TRP0                 :1;
            __IO  uint16_t  TRP1                 :1;
            __IO  uint16_t  RESERVED2            :5;
            __IO  uint16_t  WRCSDATA0            :1;
            __IO  uint16_t  WRCSDATA1            :1;
            __IO  uint16_t  WRCSDATA2            :1;
            __IO  uint16_t  WRCSDATA3            :1;
            __IO  uint16_t  WRCSDATA4            :1;
            __IO  uint16_t  WRCSDATA5            :1;
            __IO  uint16_t  WRCSDATA6            :1;
            __IO  uint16_t  WRCSDATA7            :1;
        };
    };
} stc_hsspi_wrcsdc4_field_t;

typedef struct stc_hsspi_wrcsdc5_field
{
    union {
        struct {
            __IO  uint16_t  DEC                  :1;
            __IO  uint16_t  TRP                  :2;
            __IO  uint16_t  CONT                 :1;
            __IO  uint16_t  RESERVED1            :4;
            __IO  uint16_t  WRCSDATA             :8;
        };
        struct {
            __IO  uint16_t  RESERVED0            :1;
            __IO  uint16_t  TRP0                 :1;
            __IO  uint16_t  TRP1                 :1;
            __IO  uint16_t  RESERVED2            :5;
            __IO  uint16_t  WRCSDATA0            :1;
            __IO  uint16_t  WRCSDATA1            :1;
            __IO  uint16_t  WRCSDATA2            :1;
            __IO  uint16_t  WRCSDATA3            :1;
            __IO  uint16_t  WRCSDATA4            :1;
            __IO  uint16_t  WRCSDATA5            :1;
            __IO  uint16_t  WRCSDATA6            :1;
            __IO  uint16_t  WRCSDATA7            :1;
        };
    };
} stc_hsspi_wrcsdc5_field_t;

typedef struct stc_hsspi_wrcsdc6_field
{
    union {
        struct {
            __IO  uint16_t  DEC                  :1;
            __IO  uint16_t  TRP                  :2;
            __IO  uint16_t  CONT                 :1;
            __IO  uint16_t  RESERVED1            :4;
            __IO  uint16_t  WRCSDATA             :8;
        };
        struct {
            __IO  uint16_t  RESERVED0            :1;
            __IO  uint16_t  TRP0                 :1;
            __IO  uint16_t  TRP1                 :1;
            __IO  uint16_t  RESERVED2            :5;
            __IO  uint16_t  WRCSDATA0            :1;
            __IO  uint16_t  WRCSDATA1            :1;
            __IO  uint16_t  WRCSDATA2            :1;
            __IO  uint16_t  WRCSDATA3            :1;
            __IO  uint16_t  WRCSDATA4            :1;
            __IO  uint16_t  WRCSDATA5            :1;
            __IO  uint16_t  WRCSDATA6            :1;
            __IO  uint16_t  WRCSDATA7            :1;
        };
    };
} stc_hsspi_wrcsdc6_field_t;

typedef struct stc_hsspi_wrcsdc7_field
{
    union {
        struct {
            __IO  uint16_t  DEC                  :1;
            __IO  uint16_t  TRP                  :2;
            __IO  uint16_t  CONT                 :1;
            __IO  uint16_t  RESERVED1            :4;
            __IO  uint16_t  WRCSDATA             :8;
        };
        struct {
            __IO  uint16_t  RESERVED0            :1;
            __IO  uint16_t  TRP0                 :1;
            __IO  uint16_t  TRP1                 :1;
            __IO  uint16_t  RESERVED2            :5;
            __IO  uint16_t  WRCSDATA0            :1;
            __IO  uint16_t  WRCSDATA1            :1;
            __IO  uint16_t  WRCSDATA2            :1;
            __IO  uint16_t  WRCSDATA3            :1;
            __IO  uint16_t  WRCSDATA4            :1;
            __IO  uint16_t  WRCSDATA5            :1;
            __IO  uint16_t  WRCSDATA6            :1;
            __IO  uint16_t  WRCSDATA7            :1;
        };
    };
} stc_hsspi_wrcsdc7_field_t;

typedef struct stc_hsspi_mid_field
{
    union {
        struct {
            __IO  uint32_t  MID                  :32;
        };
        struct {
            __IO  uint32_t  MID0                 :1;
            __IO  uint32_t  MID1                 :1;
            __IO  uint32_t  MID2                 :1;
            __IO  uint32_t  MID3                 :1;
            __IO  uint32_t  MID4                 :1;
            __IO  uint32_t  MID5                 :1;
            __IO  uint32_t  MID6                 :1;
            __IO  uint32_t  MID7                 :1;
            __IO  uint32_t  MID8                 :1;
            __IO  uint32_t  MID9                 :1;
            __IO  uint32_t  MID10                :1;
            __IO  uint32_t  MID11                :1;
            __IO  uint32_t  MID12                :1;
            __IO  uint32_t  MID13                :1;
            __IO  uint32_t  MID14                :1;
            __IO  uint32_t  MID15                :1;
            __IO  uint32_t  MID16                :1;
            __IO  uint32_t  MID17                :1;
            __IO  uint32_t  MID18                :1;
            __IO  uint32_t  MID19                :1;
            __IO  uint32_t  MID20                :1;
            __IO  uint32_t  MID21                :1;
            __IO  uint32_t  MID22                :1;
            __IO  uint32_t  MID23                :1;
            __IO  uint32_t  MID24                :1;
            __IO  uint32_t  MID25                :1;
            __IO  uint32_t  MID26                :1;
            __IO  uint32_t  MID27                :1;
            __IO  uint32_t  MID28                :1;
            __IO  uint32_t  MID29                :1;
            __IO  uint32_t  MID30                :1;
            __IO  uint32_t  MID31                :1;
        };
    };
} stc_hsspi_mid_field_t;

typedef struct stc_hsspi_qdclkr_field
{
    union {
        struct {
            __IO   uint8_t  QHDIV                :4;
            __IO   uint8_t  RESERVED0            :4;
        };
        struct {
            __IO   uint8_t  QHDIV0               :1;
            __IO   uint8_t  QHDIV1               :1;
            __IO   uint8_t  QHDIV2               :1;
            __IO   uint8_t  QHDIV3               :1;
            __IO   uint8_t  RESERVED1            :4;
        };
    };
} stc_hsspi_qdclkr_field_t;

typedef struct stc_hsspi_dbcnt_field
{
        __IO   uint8_t  RXDBEN                   :1;
        __IO   uint8_t  TXDBEN                   :1;
        __IO   uint8_t  RESERVED0                :6;
} stc_hsspi_dbcnt_field_t;

/*******************************************************************************
* HWWDT_MODULE
*******************************************************************************/
typedef struct stc_hwwdt_wdg_ctl_field
{
        __IO  uint32_t  INTEN                    :1;
        __IO  uint32_t  RESEN                    :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_hwwdt_wdg_ctl_field_t;

typedef struct stc_hwwdt_wdg_ris_field
{
        __IO  uint32_t  RIS                      :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_hwwdt_wdg_ris_field_t;

/*******************************************************************************
* I2S_MODULE
*******************************************************************************/
typedef struct stc_i2s_rxfdat_field
{
    union {
        struct {
            __IO  uint32_t  RXDATA               :32;
        };
        struct {
            __IO  uint32_t  RXDATA0              :1;
            __IO  uint32_t  RXDATA1              :1;
            __IO  uint32_t  RXDATA2              :1;
            __IO  uint32_t  RXDATA3              :1;
            __IO  uint32_t  RXDATA4              :1;
            __IO  uint32_t  RXDATA5              :1;
            __IO  uint32_t  RXDATA6              :1;
            __IO  uint32_t  RXDATA7              :1;
            __IO  uint32_t  RXDATA8              :1;
            __IO  uint32_t  RXDATA9              :1;
            __IO  uint32_t  RXDATA10             :1;
            __IO  uint32_t  RXDATA11             :1;
            __IO  uint32_t  RXDATA12             :1;
            __IO  uint32_t  RXDATA13             :1;
            __IO  uint32_t  RXDATA14             :1;
            __IO  uint32_t  RXDATA15             :1;
            __IO  uint32_t  RXDATA16             :1;
            __IO  uint32_t  RXDATA17             :1;
            __IO  uint32_t  RXDATA18             :1;
            __IO  uint32_t  RXDATA19             :1;
            __IO  uint32_t  RXDATA20             :1;
            __IO  uint32_t  RXDATA21             :1;
            __IO  uint32_t  RXDATA22             :1;
            __IO  uint32_t  RXDATA23             :1;
            __IO  uint32_t  RXDATA24             :1;
            __IO  uint32_t  RXDATA25             :1;
            __IO  uint32_t  RXDATA26             :1;
            __IO  uint32_t  RXDATA27             :1;
            __IO  uint32_t  RXDATA28             :1;
            __IO  uint32_t  RXDATA29             :1;
            __IO  uint32_t  RXDATA30             :1;
            __IO  uint32_t  RXDATA31             :1;
        };
    };
} stc_i2s_rxfdat_field_t;

typedef struct stc_i2s_txfdat_field
{
    union {
        struct {
            __IO  uint32_t  TXDATA               :32;
        };
        struct {
            __IO  uint32_t  TXDATA0              :1;
            __IO  uint32_t  TXDATA1              :1;
            __IO  uint32_t  TXDATA2              :1;
            __IO  uint32_t  TXDATA3              :1;
            __IO  uint32_t  TXDATA4              :1;
            __IO  uint32_t  TXDATA5              :1;
            __IO  uint32_t  TXDATA6              :1;
            __IO  uint32_t  TXDATA7              :1;
            __IO  uint32_t  TXDATA8              :1;
            __IO  uint32_t  TXDATA9              :1;
            __IO  uint32_t  TXDATA10             :1;
            __IO  uint32_t  TXDATA11             :1;
            __IO  uint32_t  TXDATA12             :1;
            __IO  uint32_t  TXDATA13             :1;
            __IO  uint32_t  TXDATA14             :1;
            __IO  uint32_t  TXDATA15             :1;
            __IO  uint32_t  TXDATA16             :1;
            __IO  uint32_t  TXDATA17             :1;
            __IO  uint32_t  TXDATA18             :1;
            __IO  uint32_t  TXDATA19             :1;
            __IO  uint32_t  TXDATA20             :1;
            __IO  uint32_t  TXDATA21             :1;
            __IO  uint32_t  TXDATA22             :1;
            __IO  uint32_t  TXDATA23             :1;
            __IO  uint32_t  TXDATA24             :1;
            __IO  uint32_t  TXDATA25             :1;
            __IO  uint32_t  TXDATA26             :1;
            __IO  uint32_t  TXDATA27             :1;
            __IO  uint32_t  TXDATA28             :1;
            __IO  uint32_t  TXDATA29             :1;
            __IO  uint32_t  TXDATA30             :1;
            __IO  uint32_t  TXDATA31             :1;
        };
    };
} stc_i2s_txfdat_field_t;

typedef struct stc_i2s_cntreg_field
{
    union {
        struct {
            __IO  uint32_t  FSPL                 :1;
            __IO  uint32_t  FSLN                 :1;
            __IO  uint32_t  FSPH                 :1;
            __IO  uint32_t  CPOL                 :1;
            __IO  uint32_t  SMPL                 :1;
            __IO  uint32_t  RXDIS                :1;
            __IO  uint32_t  TXDIS                :1;
            __IO  uint32_t  MLSB                 :1;
            __IO  uint32_t  FRUN                 :1;
            __IO  uint32_t  BEXT                 :1;
            __IO  uint32_t  ECKM                 :1;
            __IO  uint32_t  RHLL                 :1;
            __IO  uint32_t  SBFN                 :1;
            __IO  uint32_t  MSMD                 :1;
            __IO  uint32_t  MSKB                 :1;
            __IO  uint32_t  RESERVED0            :1;
            __IO  uint32_t  OVHD                 :10;
            __IO  uint32_t  CKRT                 :6;
        };
        struct {
            __IO  uint32_t  RESERVED1            :16;
            __IO  uint32_t  OVHD0                :1;
            __IO  uint32_t  OVHD1                :1;
            __IO  uint32_t  OVHD2                :1;
            __IO  uint32_t  OVHD3                :1;
            __IO  uint32_t  OVHD4                :1;
            __IO  uint32_t  OVHD5                :1;
            __IO  uint32_t  OVHD6                :1;
            __IO  uint32_t  OVHD7                :1;
            __IO  uint32_t  OVHD8                :1;
            __IO  uint32_t  OVHD9                :1;
            __IO  uint32_t  CKRT0                :1;
            __IO  uint32_t  CKRT1                :1;
            __IO  uint32_t  CKRT2                :1;
            __IO  uint32_t  CKRT3                :1;
            __IO  uint32_t  CKRT4                :1;
            __IO  uint32_t  CKRT5                :1;
        };
    };
} stc_i2s_cntreg_field_t;

typedef struct stc_i2s_mcr0reg_field
{
    union {
        struct {
            __IO  uint32_t  S0WDL                :5;
            __IO  uint32_t  S0CHL                :5;
            __IO  uint32_t  S0CHN                :5;
            __IO  uint32_t  RESERVED0            :1;
            __IO  uint32_t  S1WDL                :5;
            __IO  uint32_t  S1CHL                :5;
            __IO  uint32_t  S1CHN                :5;
            __IO  uint32_t  RESERVED2            :1;
        };
        struct {
            __IO  uint32_t  S0WDL0               :1;
            __IO  uint32_t  S0WDL1               :1;
            __IO  uint32_t  S0WDL2               :1;
            __IO  uint32_t  S0WDL3               :1;
            __IO  uint32_t  S0WDL4               :1;
            __IO  uint32_t  S0CHL0               :1;
            __IO  uint32_t  S0CHL1               :1;
            __IO  uint32_t  S0CHL2               :1;
            __IO  uint32_t  S0CHL3               :1;
            __IO  uint32_t  S0CHL4               :1;
            __IO  uint32_t  S0CHN0               :1;
            __IO  uint32_t  S0CHN1               :1;
            __IO  uint32_t  S0CHN2               :1;
            __IO  uint32_t  S0CHN3               :1;
            __IO  uint32_t  S0CHN4               :1;
            __IO  uint32_t  RESERVED1            :1;
            __IO  uint32_t  S1WDL0               :1;
            __IO  uint32_t  S1WDL1               :1;
            __IO  uint32_t  S1WDL2               :1;
            __IO  uint32_t  S1WDL3               :1;
            __IO  uint32_t  S1WDL4               :1;
            __IO  uint32_t  S1CHL0               :1;
            __IO  uint32_t  S1CHL1               :1;
            __IO  uint32_t  S1CHL2               :1;
            __IO  uint32_t  S1CHL3               :1;
            __IO  uint32_t  S1CHL4               :1;
            __IO  uint32_t  S1CHN0               :1;
            __IO  uint32_t  S1CHN1               :1;
            __IO  uint32_t  S1CHN2               :1;
            __IO  uint32_t  S1CHN3               :1;
            __IO  uint32_t  S1CHN4               :1;
            __IO  uint32_t  RESERVED3            :1;
        };
    };
} stc_i2s_mcr0reg_field_t;

typedef struct stc_i2s_mcr1reg_field
{
        __IO  uint32_t  S0CH00                   :1;
        __IO  uint32_t  S0CH01                   :1;
        __IO  uint32_t  S0CH02                   :1;
        __IO  uint32_t  S0CH03                   :1;
        __IO  uint32_t  S0CH04                   :1;
        __IO  uint32_t  S0CH05                   :1;
        __IO  uint32_t  S0CH06                   :1;
        __IO  uint32_t  S0CH07                   :1;
        __IO  uint32_t  S0CH08                   :1;
        __IO  uint32_t  S0CH09                   :1;
        __IO  uint32_t  S0CH10                   :1;
        __IO  uint32_t  S0CH11                   :1;
        __IO  uint32_t  S0CH12                   :1;
        __IO  uint32_t  S0CH13                   :1;
        __IO  uint32_t  S0CH14                   :1;
        __IO  uint32_t  S0CH15                   :1;
        __IO  uint32_t  S0CH16                   :1;
        __IO  uint32_t  S0CH17                   :1;
        __IO  uint32_t  S0CH18                   :1;
        __IO  uint32_t  S0CH19                   :1;
        __IO  uint32_t  S0CH20                   :1;
        __IO  uint32_t  S0CH21                   :1;
        __IO  uint32_t  S0CH22                   :1;
        __IO  uint32_t  S0CH23                   :1;
        __IO  uint32_t  S0CH24                   :1;
        __IO  uint32_t  S0CH25                   :1;
        __IO  uint32_t  S0CH26                   :1;
        __IO  uint32_t  S0CH27                   :1;
        __IO  uint32_t  S0CH28                   :1;
        __IO  uint32_t  S0CH29                   :1;
        __IO  uint32_t  S0CH30                   :1;
        __IO  uint32_t  S0CH31                   :1;
} stc_i2s_mcr1reg_field_t;

typedef struct stc_i2s_mcr2reg_field
{
        __IO  uint32_t  S1CH00                   :1;
        __IO  uint32_t  S1CH01                   :1;
        __IO  uint32_t  S1CH02                   :1;
        __IO  uint32_t  S1CH03                   :1;
        __IO  uint32_t  S1CH04                   :1;
        __IO  uint32_t  S1CH05                   :1;
        __IO  uint32_t  S1CH06                   :1;
        __IO  uint32_t  S1CH07                   :1;
        __IO  uint32_t  S1CH08                   :1;
        __IO  uint32_t  S1CH09                   :1;
        __IO  uint32_t  S1CH10                   :1;
        __IO  uint32_t  S1CH11                   :1;
        __IO  uint32_t  S1CH12                   :1;
        __IO  uint32_t  S1CH13                   :1;
        __IO  uint32_t  S1CH14                   :1;
        __IO  uint32_t  S1CH15                   :1;
        __IO  uint32_t  S1CH16                   :1;
        __IO  uint32_t  S1CH17                   :1;
        __IO  uint32_t  S1CH18                   :1;
        __IO  uint32_t  S1CH19                   :1;
        __IO  uint32_t  S1CH20                   :1;
        __IO  uint32_t  S1CH21                   :1;
        __IO  uint32_t  S1CH22                   :1;
        __IO  uint32_t  S1CH23                   :1;
        __IO  uint32_t  S1CH24                   :1;
        __IO  uint32_t  S1CH25                   :1;
        __IO  uint32_t  S1CH26                   :1;
        __IO  uint32_t  S1CH27                   :1;
        __IO  uint32_t  S1CH28                   :1;
        __IO  uint32_t  S1CH29                   :1;
        __IO  uint32_t  S1CH30                   :1;
        __IO  uint32_t  S1CH31                   :1;
} stc_i2s_mcr2reg_field_t;

typedef struct stc_i2s_oprreg_field
{
        __IO  uint32_t  START                    :1;
        __IO  uint32_t  RESERVED0                :15;
        __IO  uint32_t  TXENB                    :1;
        __IO  uint32_t  RESERVED1                :7;
        __IO  uint32_t  RXENB                    :1;
        __IO  uint32_t  RESERVED2                :7;
} stc_i2s_oprreg_field_t;

typedef struct stc_i2s_srst_field
{
        __IO  uint32_t  SRST                     :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_i2s_srst_field_t;

typedef struct stc_i2s_intcnt_field
{
    union {
        struct {
            __IO  uint32_t  RFTH                 :4;
            __IO  uint32_t  RPTMR                :2;
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  TFTH                 :4;
            __IO  uint32_t  RESERVED2            :4;
            __IO  uint32_t  RXFIM                :1;
            __IO  uint32_t  RXFDM                :1;
            __IO  uint32_t  EOPM                 :1;
            __IO  uint32_t  RXOVM                :1;
            __IO  uint32_t  RXUDM                :1;
            __IO  uint32_t  RBERM                :1;
            __IO  uint32_t  RESERVED3            :2;
            __IO  uint32_t  TXFIM                :1;
            __IO  uint32_t  TXFDM                :1;
            __IO  uint32_t  TXOVM                :1;
            __IO  uint32_t  TXUD0M               :1;
            __IO  uint32_t  FERRM                :1;
            __IO  uint32_t  TBERM                :1;
            __IO  uint32_t  TXUD1M               :1;
            __IO  uint32_t  RESERVED4            :1;
        };
        struct {
            __IO  uint32_t  RFTH0                :1;
            __IO  uint32_t  RFTH1                :1;
            __IO  uint32_t  RFTH2                :1;
            __IO  uint32_t  RFTH3                :1;
            __IO  uint32_t  RPTMR0               :1;
            __IO  uint32_t  RPTMR1               :1;
            __IO  uint32_t  RESERVED1            :2;
            __IO  uint32_t  TFTH0                :1;
            __IO  uint32_t  TFTH1                :1;
            __IO  uint32_t  TFTH2                :1;
            __IO  uint32_t  TFTH3                :1;
            __IO  uint32_t  RESERVED5            :20;
        };
    };
} stc_i2s_intcnt_field_t;

typedef struct stc_i2s_status_field
{
    union {
        struct {
            __IO  uint32_t  RXNUM                :8;
            __IO  uint32_t  TXNUM                :8;
            __IO  uint32_t  RXFI                 :1;
            __IO  uint32_t  TXFI                 :1;
            __IO  uint32_t  BSY                  :1;
            __IO  uint32_t  EOPI                 :1;
            __IO  uint32_t  RESERVED0            :4;
            __IO  uint32_t  RXOVR                :1;
            __IO  uint32_t  RXUDR                :1;
            __IO  uint32_t  TXOVR                :1;
            __IO  uint32_t  TXUDR0               :1;
            __IO  uint32_t  TXUDR1               :1;
            __IO  uint32_t  FERR                 :1;
            __IO  uint32_t  RBERR                :1;
            __IO  uint32_t  TBERR                :1;
        };
        struct {
            __IO  uint32_t  RXNUM0               :1;
            __IO  uint32_t  RXNUM1               :1;
            __IO  uint32_t  RXNUM2               :1;
            __IO  uint32_t  RXNUM3               :1;
            __IO  uint32_t  RXNUM4               :1;
            __IO  uint32_t  RXNUM5               :1;
            __IO  uint32_t  RXNUM6               :1;
            __IO  uint32_t  RXNUM7               :1;
            __IO  uint32_t  TXNUM0               :1;
            __IO  uint32_t  TXNUM1               :1;
            __IO  uint32_t  TXNUM2               :1;
            __IO  uint32_t  TXNUM3               :1;
            __IO  uint32_t  TXNUM4               :1;
            __IO  uint32_t  TXNUM5               :1;
            __IO  uint32_t  TXNUM6               :1;
            __IO  uint32_t  TXNUM7               :1;
            __IO  uint32_t  RESERVED1            :16;
        };
    };
} stc_i2s_status_field_t;

typedef struct stc_i2s_dmaact_field
{
        __IO  uint32_t  RDMACT                   :1;
        __IO  uint32_t  RESERVED0                :7;
        __IO  uint32_t  RL1E0                    :1;
        __IO  uint32_t  RESERVED1                :7;
        __IO  uint32_t  TDMACT                   :1;
        __IO  uint32_t  RESERVED2                :7;
        __IO  uint32_t  TL1E0                    :1;
        __IO  uint32_t  RESERVED3                :7;
} stc_i2s_dmaact_field_t;

typedef struct stc_i2s_tstreg_field
{
        __IO  uint32_t  LBMD                     :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_i2s_tstreg_field_t;

/*******************************************************************************
* I2SPRE_MODULE
*******************************************************************************/
typedef struct stc_i2spre_iccr_field
{
        __IO  uint32_t  I2SEN                    :1;
        __IO  uint32_t  ICSEL                    :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_i2spre_iccr_field_t;

typedef struct stc_i2spre_ipcr1_field
{
        __IO  uint32_t  IPLLEN                   :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_i2spre_ipcr1_field_t;

typedef struct stc_i2spre_ipcr2_field
{
    union {
        struct {
            __IO  uint32_t  IPOWT                :3;
            __IO  uint32_t  RESERVED0            :29;
        };
        struct {
            __IO  uint32_t  IPOWT0               :1;
            __IO  uint32_t  IPOWT1               :1;
            __IO  uint32_t  IPOWT2               :1;
            __IO  uint32_t  RESERVED1            :29;
        };
    };
} stc_i2spre_ipcr2_field_t;

typedef struct stc_i2spre_ipcr3_field
{
    union {
        struct {
            __IO  uint32_t  IPLLK                :5;
            __IO  uint32_t  RESERVED0            :27;
        };
        struct {
            __IO  uint32_t  IPLLK0               :1;
            __IO  uint32_t  IPLLK1               :1;
            __IO  uint32_t  IPLLK2               :1;
            __IO  uint32_t  IPLLK3               :1;
            __IO  uint32_t  IPLLK4               :1;
            __IO  uint32_t  RESERVED1            :27;
        };
    };
} stc_i2spre_ipcr3_field_t;

typedef struct stc_i2spre_ipcr4_field
{
    union {
        struct {
            __IO  uint32_t  IPLLN                :7;
            __IO  uint32_t  RESERVED0            :25;
        };
        struct {
            __IO  uint32_t  IPLLN0               :1;
            __IO  uint32_t  IPLLN1               :1;
            __IO  uint32_t  IPLLN2               :1;
            __IO  uint32_t  IPLLN3               :1;
            __IO  uint32_t  IPLLN4               :1;
            __IO  uint32_t  IPLLN5               :1;
            __IO  uint32_t  IPLLN6               :1;
            __IO  uint32_t  RESERVED1            :25;
        };
    };
} stc_i2spre_ipcr4_field_t;

typedef struct stc_i2spre_ip_str_field
{
        __IO  uint32_t  IPRDY                    :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_i2spre_ip_str_field_t;

typedef struct stc_i2spre_ipint_enr_field
{
        __IO  uint32_t  IPCSE                    :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_i2spre_ipint_enr_field_t;

typedef struct stc_i2spre_ipint_clr_field
{
        __IO  uint32_t  IPCSC                    :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_i2spre_ipint_clr_field_t;

typedef struct stc_i2spre_ipint_str_field
{
        __IO  uint32_t  IPCSI                    :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_i2spre_ipint_str_field_t;

typedef struct stc_i2spre_ipcr5_field
{
    union {
        struct {
            __IO  uint32_t  IPLLM                :7;
            __IO  uint32_t  RESERVED0            :25;
        };
        struct {
            __IO  uint32_t  IPLLM0               :1;
            __IO  uint32_t  IPLLM1               :1;
            __IO  uint32_t  IPLLM2               :1;
            __IO  uint32_t  IPLLM3               :1;
            __IO  uint32_t  IPLLM4               :1;
            __IO  uint32_t  IPLLM5               :1;
            __IO  uint32_t  IPLLM6               :1;
            __IO  uint32_t  RESERVED1            :25;
        };
    };
} stc_i2spre_ipcr5_field_t;

/*******************************************************************************
* INTREQ_MODULE
*******************************************************************************/
typedef struct stc_intreq_drqsel_field
{
        __IO  uint32_t  USBEP1                   :1;
        __IO  uint32_t  USBEP2                   :1;
        __IO  uint32_t  USBEP3                   :1;
        __IO  uint32_t  USBEP4                   :1;
        __IO  uint32_t  USBEP5                   :1;
        __IO  uint32_t  ADCSCAN0                 :1;
        __IO  uint32_t  ADCSCAN1                 :1;
        __IO  uint32_t  ADCSCAN2                 :1;
        __IO  uint32_t  IRQ0BT0                  :1;
        __IO  uint32_t  IRQ0BT2                  :1;
        __IO  uint32_t  IRQ0BT4                  :1;
        __IO  uint32_t  IRQ0BT6                  :1;
        __IO  uint32_t  MFS0RX                   :1;
        __IO  uint32_t  MFS0TX                   :1;
        __IO  uint32_t  MFS1RX                   :1;
        __IO  uint32_t  MFS1TX                   :1;
        __IO  uint32_t  MFS2RX                   :1;
        __IO  uint32_t  MFS2TX                   :1;
        __IO  uint32_t  MFS3RX                   :1;
        __IO  uint32_t  MFS3TX                   :1;
        __IO  uint32_t  MFS4RX                   :1;
        __IO  uint32_t  MFS4TX                   :1;
        __IO  uint32_t  MFS5RX                   :1;
        __IO  uint32_t  MFS5TX                   :1;
        __IO  uint32_t  MFS6RX                   :1;
        __IO  uint32_t  MFS6TX                   :1;
        __IO  uint32_t  MFS7RX                   :1;
        __IO  uint32_t  MFS7TX                   :1;
        __IO  uint32_t  EXINT0                   :1;
        __IO  uint32_t  EXINT1                   :1;
        __IO  uint32_t  EXINT2                   :1;
        __IO  uint32_t  EXINT3                   :1;
} stc_intreq_drqsel_field_t;

typedef struct stc_intreq_oddpks_field
{
        __IO   uint8_t  ODDPKS0                  :1;
        __IO   uint8_t  ODDPKS1                  :1;
        __IO   uint8_t  ODDPKS2                  :1;
        __IO   uint8_t  ODDPKS3                  :1;
        __IO   uint8_t  ODDPKS4                  :1;
        __IO   uint8_t  RESERVED0                :3;
} stc_intreq_oddpks_field_t;

typedef struct stc_intreq_oddpks1_field
{
        __IO   uint8_t  ODDPKS10                 :1;
        __IO   uint8_t  ODDPKS11                 :1;
        __IO   uint8_t  ODDPKS12                 :1;
        __IO   uint8_t  ODDPKS13                 :1;
        __IO   uint8_t  ODDPKS14                 :1;
        __IO   uint8_t  RESERVED0                :3;
} stc_intreq_oddpks1_field_t;

typedef struct stc_intreq_irq003sel_field
{
    union {
        struct {
            __IO  uint32_t  SELIRQ               :8;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  SELBIT0              :1;
            __IO  uint32_t  SELBIT1              :1;
            __IO  uint32_t  SELBIT2              :1;
            __IO  uint32_t  SELBIT3              :1;
            __IO  uint32_t  SELBIT4              :1;
            __IO  uint32_t  SELBIT5              :1;
            __IO  uint32_t  SELBIT6              :1;
            __IO  uint32_t  SELBIT7              :1;
            __IO  uint32_t  SELBIT8              :1;
            __IO  uint32_t  SELBIT9              :1;
            __IO  uint32_t  SELBIT10             :1;
            __IO  uint32_t  SELBIT11             :1;
            __IO  uint32_t  SELBIT12             :1;
            __IO  uint32_t  SELBIT13             :1;
            __IO  uint32_t  SELBIT14             :1;
            __IO  uint32_t  SELBIT15             :1;
        };
        struct {
            __IO  uint32_t  SELIRQ0              :1;
            __IO  uint32_t  SELIRQ1              :1;
            __IO  uint32_t  SELIRQ2              :1;
            __IO  uint32_t  SELIRQ3              :1;
            __IO  uint32_t  SELIRQ4              :1;
            __IO  uint32_t  SELIRQ5              :1;
            __IO  uint32_t  SELIRQ6              :1;
            __IO  uint32_t  SELIRQ7              :1;
            __IO  uint32_t  RESERVED1            :24;
        };
    };
} stc_intreq_irq003sel_field_t;

typedef struct stc_intreq_irq004sel_field
{
    union {
        struct {
            __IO  uint32_t  SELIRQ               :8;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  SELBIT0              :1;
            __IO  uint32_t  SELBIT1              :1;
            __IO  uint32_t  SELBIT2              :1;
            __IO  uint32_t  SELBIT3              :1;
            __IO  uint32_t  SELBIT4              :1;
            __IO  uint32_t  SELBIT5              :1;
            __IO  uint32_t  SELBIT6              :1;
            __IO  uint32_t  SELBIT7              :1;
            __IO  uint32_t  SELBIT8              :1;
            __IO  uint32_t  SELBIT9              :1;
            __IO  uint32_t  SELBIT10             :1;
            __IO  uint32_t  SELBIT11             :1;
            __IO  uint32_t  SELBIT12             :1;
            __IO  uint32_t  SELBIT13             :1;
            __IO  uint32_t  SELBIT14             :1;
            __IO  uint32_t  SELBIT15             :1;
        };
        struct {
            __IO  uint32_t  SELIRQ0              :1;
            __IO  uint32_t  SELIRQ1              :1;
            __IO  uint32_t  SELIRQ2              :1;
            __IO  uint32_t  SELIRQ3              :1;
            __IO  uint32_t  SELIRQ4              :1;
            __IO  uint32_t  SELIRQ5              :1;
            __IO  uint32_t  SELIRQ6              :1;
            __IO  uint32_t  SELIRQ7              :1;
            __IO  uint32_t  RESERVED1            :24;
        };
    };
} stc_intreq_irq004sel_field_t;

typedef struct stc_intreq_irq005sel_field
{
    union {
        struct {
            __IO  uint32_t  SELIRQ               :8;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  SELBIT0              :1;
            __IO  uint32_t  SELBIT1              :1;
            __IO  uint32_t  SELBIT2              :1;
            __IO  uint32_t  SELBIT3              :1;
            __IO  uint32_t  SELBIT4              :1;
            __IO  uint32_t  SELBIT5              :1;
            __IO  uint32_t  SELBIT6              :1;
            __IO  uint32_t  SELBIT7              :1;
            __IO  uint32_t  SELBIT8              :1;
            __IO  uint32_t  SELBIT9              :1;
            __IO  uint32_t  SELBIT10             :1;
            __IO  uint32_t  SELBIT11             :1;
            __IO  uint32_t  SELBIT12             :1;
            __IO  uint32_t  SELBIT13             :1;
            __IO  uint32_t  SELBIT14             :1;
            __IO  uint32_t  SELBIT15             :1;
        };
        struct {
            __IO  uint32_t  SELIRQ0              :1;
            __IO  uint32_t  SELIRQ1              :1;
            __IO  uint32_t  SELIRQ2              :1;
            __IO  uint32_t  SELIRQ3              :1;
            __IO  uint32_t  SELIRQ4              :1;
            __IO  uint32_t  SELIRQ5              :1;
            __IO  uint32_t  SELIRQ6              :1;
            __IO  uint32_t  SELIRQ7              :1;
            __IO  uint32_t  RESERVED1            :24;
        };
    };
} stc_intreq_irq005sel_field_t;

typedef struct stc_intreq_irq006sel_field
{
    union {
        struct {
            __IO  uint32_t  SELIRQ               :8;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  SELBIT0              :1;
            __IO  uint32_t  SELBIT1              :1;
            __IO  uint32_t  SELBIT2              :1;
            __IO  uint32_t  SELBIT3              :1;
            __IO  uint32_t  SELBIT4              :1;
            __IO  uint32_t  SELBIT5              :1;
            __IO  uint32_t  SELBIT6              :1;
            __IO  uint32_t  SELBIT7              :1;
            __IO  uint32_t  SELBIT8              :1;
            __IO  uint32_t  SELBIT9              :1;
            __IO  uint32_t  SELBIT10             :1;
            __IO  uint32_t  SELBIT11             :1;
            __IO  uint32_t  SELBIT12             :1;
            __IO  uint32_t  SELBIT13             :1;
            __IO  uint32_t  SELBIT14             :1;
            __IO  uint32_t  SELBIT15             :1;
        };
        struct {
            __IO  uint32_t  SELIRQ0              :1;
            __IO  uint32_t  SELIRQ1              :1;
            __IO  uint32_t  SELIRQ2              :1;
            __IO  uint32_t  SELIRQ3              :1;
            __IO  uint32_t  SELIRQ4              :1;
            __IO  uint32_t  SELIRQ5              :1;
            __IO  uint32_t  SELIRQ6              :1;
            __IO  uint32_t  SELIRQ7              :1;
            __IO  uint32_t  RESERVED1            :24;
        };
    };
} stc_intreq_irq006sel_field_t;

typedef struct stc_intreq_irq007sel_field
{
    union {
        struct {
            __IO  uint32_t  SELIRQ               :8;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  SELBIT0              :1;
            __IO  uint32_t  SELBIT1              :1;
            __IO  uint32_t  SELBIT2              :1;
            __IO  uint32_t  SELBIT3              :1;
            __IO  uint32_t  SELBIT4              :1;
            __IO  uint32_t  SELBIT5              :1;
            __IO  uint32_t  SELBIT6              :1;
            __IO  uint32_t  SELBIT7              :1;
            __IO  uint32_t  SELBIT8              :1;
            __IO  uint32_t  SELBIT9              :1;
            __IO  uint32_t  SELBIT10             :1;
            __IO  uint32_t  SELBIT11             :1;
            __IO  uint32_t  SELBIT12             :1;
            __IO  uint32_t  SELBIT13             :1;
            __IO  uint32_t  SELBIT14             :1;
            __IO  uint32_t  SELBIT15             :1;
        };
        struct {
            __IO  uint32_t  SELIRQ0              :1;
            __IO  uint32_t  SELIRQ1              :1;
            __IO  uint32_t  SELIRQ2              :1;
            __IO  uint32_t  SELIRQ3              :1;
            __IO  uint32_t  SELIRQ4              :1;
            __IO  uint32_t  SELIRQ5              :1;
            __IO  uint32_t  SELIRQ6              :1;
            __IO  uint32_t  SELIRQ7              :1;
            __IO  uint32_t  RESERVED1            :24;
        };
    };
} stc_intreq_irq007sel_field_t;

typedef struct stc_intreq_irq008sel_field
{
    union {
        struct {
            __IO  uint32_t  SELIRQ               :8;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  SELBIT0              :1;
            __IO  uint32_t  SELBIT1              :1;
            __IO  uint32_t  SELBIT2              :1;
            __IO  uint32_t  SELBIT3              :1;
            __IO  uint32_t  SELBIT4              :1;
            __IO  uint32_t  SELBIT5              :1;
            __IO  uint32_t  SELBIT6              :1;
            __IO  uint32_t  SELBIT7              :1;
            __IO  uint32_t  SELBIT8              :1;
            __IO  uint32_t  SELBIT9              :1;
            __IO  uint32_t  SELBIT10             :1;
            __IO  uint32_t  SELBIT11             :1;
            __IO  uint32_t  SELBIT12             :1;
            __IO  uint32_t  SELBIT13             :1;
            __IO  uint32_t  SELBIT14             :1;
            __IO  uint32_t  SELBIT15             :1;
        };
        struct {
            __IO  uint32_t  SELIRQ0              :1;
            __IO  uint32_t  SELIRQ1              :1;
            __IO  uint32_t  SELIRQ2              :1;
            __IO  uint32_t  SELIRQ3              :1;
            __IO  uint32_t  SELIRQ4              :1;
            __IO  uint32_t  SELIRQ5              :1;
            __IO  uint32_t  SELIRQ6              :1;
            __IO  uint32_t  SELIRQ7              :1;
            __IO  uint32_t  RESERVED1            :24;
        };
    };
} stc_intreq_irq008sel_field_t;

typedef struct stc_intreq_irq009sel_field
{
    union {
        struct {
            __IO  uint32_t  SELIRQ               :8;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  SELBIT0              :1;
            __IO  uint32_t  SELBIT1              :1;
            __IO  uint32_t  SELBIT2              :1;
            __IO  uint32_t  SELBIT3              :1;
            __IO  uint32_t  SELBIT4              :1;
            __IO  uint32_t  SELBIT5              :1;
            __IO  uint32_t  SELBIT6              :1;
            __IO  uint32_t  SELBIT7              :1;
            __IO  uint32_t  SELBIT8              :1;
            __IO  uint32_t  SELBIT9              :1;
            __IO  uint32_t  SELBIT10             :1;
            __IO  uint32_t  SELBIT11             :1;
            __IO  uint32_t  SELBIT12             :1;
            __IO  uint32_t  SELBIT13             :1;
            __IO  uint32_t  SELBIT14             :1;
            __IO  uint32_t  SELBIT15             :1;
        };
        struct {
            __IO  uint32_t  SELIRQ0              :1;
            __IO  uint32_t  SELIRQ1              :1;
            __IO  uint32_t  SELIRQ2              :1;
            __IO  uint32_t  SELIRQ3              :1;
            __IO  uint32_t  SELIRQ4              :1;
            __IO  uint32_t  SELIRQ5              :1;
            __IO  uint32_t  SELIRQ6              :1;
            __IO  uint32_t  SELIRQ7              :1;
            __IO  uint32_t  RESERVED1            :24;
        };
    };
} stc_intreq_irq009sel_field_t;

typedef struct stc_intreq_irq010sel_field
{
    union {
        struct {
            __IO  uint32_t  SELIRQ               :8;
            __IO  uint32_t  RESERVED0            :8;
            __IO  uint32_t  SELBIT0              :1;
            __IO  uint32_t  SELBIT1              :1;
            __IO  uint32_t  SELBIT2              :1;
            __IO  uint32_t  SELBIT3              :1;
            __IO  uint32_t  SELBIT4              :1;
            __IO  uint32_t  SELBIT5              :1;
            __IO  uint32_t  SELBIT6              :1;
            __IO  uint32_t  SELBIT7              :1;
            __IO  uint32_t  SELBIT8              :1;
            __IO  uint32_t  SELBIT9              :1;
            __IO  uint32_t  SELBIT10             :1;
            __IO  uint32_t  SELBIT11             :1;
            __IO  uint32_t  SELBIT12             :1;
            __IO  uint32_t  SELBIT13             :1;
            __IO  uint32_t  SELBIT14             :1;
            __IO  uint32_t  SELBIT15             :1;
        };
        struct {
            __IO  uint32_t  SELIRQ0              :1;
            __IO  uint32_t  SELIRQ1              :1;
            __IO  uint32_t  SELIRQ2              :1;
            __IO  uint32_t  SELIRQ3              :1;
            __IO  uint32_t  SELIRQ4              :1;
            __IO  uint32_t  SELIRQ5              :1;
            __IO  uint32_t  SELIRQ6              :1;
            __IO  uint32_t  SELIRQ7              :1;
            __IO  uint32_t  RESERVED1            :24;
        };
    };
} stc_intreq_irq010sel_field_t;

typedef struct stc_intreq_exc02mon_field
{
        __IO  uint32_t  NMI                      :1;
        __IO  uint32_t  HWINT                    :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_exc02mon_field_t;

typedef struct stc_intreq_irq000mon_field
{
        __IO  uint32_t  FCSINT                   :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq000mon_field_t;

typedef struct stc_intreq_irq001mon_field
{
        __IO  uint32_t  SWWDTINT                 :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq001mon_field_t;

typedef struct stc_intreq_irq002mon_field
{
        __IO  uint32_t  LVDINT                   :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq002mon_field_t;

typedef struct stc_intreq_irq003mon_field
{
        __IO  uint32_t  IRQBIT0                  :1;
        __IO  uint32_t  IRQBIT1                  :1;
        __IO  uint32_t  IRQBIT2                  :1;
        __IO  uint32_t  IRQBIT3                  :1;
        __IO  uint32_t  IRQBIT4                  :1;
        __IO  uint32_t  IRQBIT5                  :1;
        __IO  uint32_t  IRQBIT6                  :1;
        __IO  uint32_t  IRQBIT7                  :1;
        __IO  uint32_t  RESERVED0                :24;
} stc_intreq_irq003mon_field_t;

typedef struct stc_intreq_irq004mon_field
{
        __IO  uint32_t  IRQBIT0                  :1;
        __IO  uint32_t  IRQBIT1                  :1;
        __IO  uint32_t  IRQBIT2                  :1;
        __IO  uint32_t  IRQBIT3                  :1;
        __IO  uint32_t  IRQBIT4                  :1;
        __IO  uint32_t  IRQBIT5                  :1;
        __IO  uint32_t  IRQBIT6                  :1;
        __IO  uint32_t  IRQBIT7                  :1;
        __IO  uint32_t  RESERVED0                :24;
} stc_intreq_irq004mon_field_t;

typedef struct stc_intreq_irq005mon_field
{
        __IO  uint32_t  IRQBIT0                  :1;
        __IO  uint32_t  IRQBIT1                  :1;
        __IO  uint32_t  IRQBIT2                  :1;
        __IO  uint32_t  IRQBIT3                  :1;
        __IO  uint32_t  IRQBIT4                  :1;
        __IO  uint32_t  IRQBIT5                  :1;
        __IO  uint32_t  IRQBIT6                  :1;
        __IO  uint32_t  IRQBIT7                  :1;
        __IO  uint32_t  RESERVED0                :24;
} stc_intreq_irq005mon_field_t;

typedef struct stc_intreq_irq006mon_field
{
        __IO  uint32_t  IRQBIT0                  :1;
        __IO  uint32_t  IRQBIT1                  :1;
        __IO  uint32_t  IRQBIT2                  :1;
        __IO  uint32_t  IRQBIT3                  :1;
        __IO  uint32_t  IRQBIT4                  :1;
        __IO  uint32_t  IRQBIT5                  :1;
        __IO  uint32_t  IRQBIT6                  :1;
        __IO  uint32_t  IRQBIT7                  :1;
        __IO  uint32_t  RESERVED0                :24;
} stc_intreq_irq006mon_field_t;

typedef struct stc_intreq_irq007mon_field
{
        __IO  uint32_t  IRQBIT0                  :1;
        __IO  uint32_t  IRQBIT1                  :1;
        __IO  uint32_t  IRQBIT2                  :1;
        __IO  uint32_t  IRQBIT3                  :1;
        __IO  uint32_t  IRQBIT4                  :1;
        __IO  uint32_t  IRQBIT5                  :1;
        __IO  uint32_t  IRQBIT6                  :1;
        __IO  uint32_t  IRQBIT7                  :1;
        __IO  uint32_t  RESERVED0                :24;
} stc_intreq_irq007mon_field_t;

typedef struct stc_intreq_irq008mon_field
{
        __IO  uint32_t  IRQBIT0                  :1;
        __IO  uint32_t  IRQBIT1                  :1;
        __IO  uint32_t  IRQBIT2                  :1;
        __IO  uint32_t  IRQBIT3                  :1;
        __IO  uint32_t  IRQBIT4                  :1;
        __IO  uint32_t  IRQBIT5                  :1;
        __IO  uint32_t  IRQBIT6                  :1;
        __IO  uint32_t  IRQBIT7                  :1;
        __IO  uint32_t  RESERVED0                :24;
} stc_intreq_irq008mon_field_t;

typedef struct stc_intreq_irq009mon_field
{
        __IO  uint32_t  IRQBIT0                  :1;
        __IO  uint32_t  IRQBIT1                  :1;
        __IO  uint32_t  IRQBIT2                  :1;
        __IO  uint32_t  IRQBIT3                  :1;
        __IO  uint32_t  IRQBIT4                  :1;
        __IO  uint32_t  IRQBIT5                  :1;
        __IO  uint32_t  IRQBIT6                  :1;
        __IO  uint32_t  IRQBIT7                  :1;
        __IO  uint32_t  RESERVED0                :24;
} stc_intreq_irq009mon_field_t;

typedef struct stc_intreq_irq010mon_field
{
        __IO  uint32_t  IRQBIT0                  :1;
        __IO  uint32_t  IRQBIT1                  :1;
        __IO  uint32_t  IRQBIT2                  :1;
        __IO  uint32_t  IRQBIT3                  :1;
        __IO  uint32_t  IRQBIT4                  :1;
        __IO  uint32_t  IRQBIT5                  :1;
        __IO  uint32_t  IRQBIT6                  :1;
        __IO  uint32_t  IRQBIT7                  :1;
        __IO  uint32_t  RESERVED0                :24;
} stc_intreq_irq010mon_field_t;

typedef struct stc_intreq_irq011mon_field
{
        __IO  uint32_t  EXTINT                   :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq011mon_field_t;

typedef struct stc_intreq_irq012mon_field
{
        __IO  uint32_t  EXTINT                   :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq012mon_field_t;

typedef struct stc_intreq_irq013mon_field
{
        __IO  uint32_t  EXTINT                   :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq013mon_field_t;

typedef struct stc_intreq_irq014mon_field
{
        __IO  uint32_t  EXTINT                   :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq014mon_field_t;

typedef struct stc_intreq_irq015mon_field
{
        __IO  uint32_t  EXTINT                   :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq015mon_field_t;

typedef struct stc_intreq_irq016mon_field
{
        __IO  uint32_t  EXTINT                   :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq016mon_field_t;

typedef struct stc_intreq_irq017mon_field
{
        __IO  uint32_t  EXTINT                   :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq017mon_field_t;

typedef struct stc_intreq_irq018mon_field
{
        __IO  uint32_t  EXTINT                   :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq018mon_field_t;

typedef struct stc_intreq_irq019mon_field
{
        __IO  uint32_t  QPRCINT0                 :1;
        __IO  uint32_t  QPRCINT1                 :1;
        __IO  uint32_t  QPRCINT2                 :1;
        __IO  uint32_t  QPRCINT3                 :1;
        __IO  uint32_t  QPRCINT4                 :1;
        __IO  uint32_t  QPRCINT5                 :1;
        __IO  uint32_t  RESERVED0                :26;
} stc_intreq_irq019mon_field_t;

typedef struct stc_intreq_irq020mon_field
{
        __IO  uint32_t  QPRCINT0                 :1;
        __IO  uint32_t  QPRCINT1                 :1;
        __IO  uint32_t  QPRCINT2                 :1;
        __IO  uint32_t  QPRCINT3                 :1;
        __IO  uint32_t  QPRCINT4                 :1;
        __IO  uint32_t  QPRCINT5                 :1;
        __IO  uint32_t  RESERVED0                :26;
} stc_intreq_irq020mon_field_t;

typedef struct stc_intreq_irq021mon_field
{
        __IO  uint32_t  WAVEINT0                 :1;
        __IO  uint32_t  WAVEINT1                 :1;
        __IO  uint32_t  WAVEINT2                 :1;
        __IO  uint32_t  WAVEINT3                 :1;
        __IO  uint32_t  RESERVED0                :28;
} stc_intreq_irq021mon_field_t;

typedef struct stc_intreq_irq022mon_field
{
        __IO  uint32_t  WAVEINT0                 :1;
        __IO  uint32_t  WAVEINT1                 :1;
        __IO  uint32_t  WAVEINT2                 :1;
        __IO  uint32_t  WAVEINT3                 :1;
        __IO  uint32_t  RESERVED0                :28;
} stc_intreq_irq022mon_field_t;

typedef struct stc_intreq_irq023mon_field
{
        __IO  uint32_t  WAVEINT0                 :1;
        __IO  uint32_t  WAVEINT1                 :1;
        __IO  uint32_t  WAVEINT2                 :1;
        __IO  uint32_t  WAVEINT3                 :1;
        __IO  uint32_t  RESERVED0                :28;
} stc_intreq_irq023mon_field_t;

typedef struct stc_intreq_irq024mon_field
{
        __IO  uint32_t  FRT_PEAK_INT0            :1;
        __IO  uint32_t  FRT_PEAK_INT1            :1;
        __IO  uint32_t  FRT_PEAK_INT2            :1;
        __IO  uint32_t  RESERVED0                :29;
} stc_intreq_irq024mon_field_t;

typedef struct stc_intreq_irq025mon_field
{
        __IO  uint32_t  FRT_ZERO_INT0            :1;
        __IO  uint32_t  FRT_ZERO_INT1            :1;
        __IO  uint32_t  FRT_ZERO_INT2            :1;
        __IO  uint32_t  RESERVED0                :29;
} stc_intreq_irq025mon_field_t;

typedef struct stc_intreq_irq026mon_field
{
        __IO  uint32_t  ICUINT0                  :1;
        __IO  uint32_t  ICUINT1                  :1;
        __IO  uint32_t  ICUINT2                  :1;
        __IO  uint32_t  ICUINT3                  :1;
        __IO  uint32_t  RESERVED0                :28;
} stc_intreq_irq026mon_field_t;

typedef struct stc_intreq_irq027mon_field
{
        __IO  uint32_t  OCUINT0                  :1;
        __IO  uint32_t  OCUINT1                  :1;
        __IO  uint32_t  OCUINT2                  :1;
        __IO  uint32_t  OCUINT3                  :1;
        __IO  uint32_t  OCUINT4                  :1;
        __IO  uint32_t  OCUINT5                  :1;
        __IO  uint32_t  RESERVED0                :26;
} stc_intreq_irq027mon_field_t;

typedef struct stc_intreq_irq028mon_field
{
        __IO  uint32_t  FRT_PEAK_INT0            :1;
        __IO  uint32_t  FRT_PEAK_INT1            :1;
        __IO  uint32_t  FRT_PEAK_INT2            :1;
        __IO  uint32_t  RESERVED0                :29;
} stc_intreq_irq028mon_field_t;

typedef struct stc_intreq_irq029mon_field
{
        __IO  uint32_t  FRT_ZERO_INT0            :1;
        __IO  uint32_t  FRT_ZERO_INT1            :1;
        __IO  uint32_t  FRT_ZERO_INT2            :1;
        __IO  uint32_t  RESERVED0                :29;
} stc_intreq_irq029mon_field_t;

typedef struct stc_intreq_irq030mon_field
{
        __IO  uint32_t  ICUINT0                  :1;
        __IO  uint32_t  ICUINT1                  :1;
        __IO  uint32_t  ICUINT2                  :1;
        __IO  uint32_t  ICUINT3                  :1;
        __IO  uint32_t  RESERVED0                :28;
} stc_intreq_irq030mon_field_t;

typedef struct stc_intreq_irq031mon_field
{
        __IO  uint32_t  OCUINT0                  :1;
        __IO  uint32_t  OCUINT1                  :1;
        __IO  uint32_t  OCUINT2                  :1;
        __IO  uint32_t  OCUINT3                  :1;
        __IO  uint32_t  OCUINT4                  :1;
        __IO  uint32_t  OCUINT5                  :1;
        __IO  uint32_t  RESERVED0                :26;
} stc_intreq_irq031mon_field_t;

typedef struct stc_intreq_irq032mon_field
{
        __IO  uint32_t  FRT_PEAK_INT0            :1;
        __IO  uint32_t  FRT_PEAK_INT1            :1;
        __IO  uint32_t  FRT_PEAK_INT2            :1;
        __IO  uint32_t  RESERVED0                :29;
} stc_intreq_irq032mon_field_t;

typedef struct stc_intreq_irq033mon_field
{
        __IO  uint32_t  FRT_ZERO_INT0            :1;
        __IO  uint32_t  FRT_ZERO_INT1            :1;
        __IO  uint32_t  FRT_ZERO_INT2            :1;
        __IO  uint32_t  RESERVED0                :29;
} stc_intreq_irq033mon_field_t;

typedef struct stc_intreq_irq034mon_field
{
        __IO  uint32_t  ICUINT0                  :1;
        __IO  uint32_t  ICUINT1                  :1;
        __IO  uint32_t  ICUINT2                  :1;
        __IO  uint32_t  ICUINT3                  :1;
        __IO  uint32_t  RESERVED0                :28;
} stc_intreq_irq034mon_field_t;

typedef struct stc_intreq_irq035mon_field
{
        __IO  uint32_t  OCUINT0                  :1;
        __IO  uint32_t  OCUINT1                  :1;
        __IO  uint32_t  OCUINT2                  :1;
        __IO  uint32_t  OCUINT3                  :1;
        __IO  uint32_t  OCUINT4                  :1;
        __IO  uint32_t  OCUINT5                  :1;
        __IO  uint32_t  RESERVED0                :26;
} stc_intreq_irq035mon_field_t;

typedef struct stc_intreq_irq036mon_field
{
        __IO  uint32_t  PPGINT0                  :1;
        __IO  uint32_t  PPGINT1                  :1;
        __IO  uint32_t  PPGINT2                  :1;
        __IO  uint32_t  RESERVED0                :29;
} stc_intreq_irq036mon_field_t;

typedef struct stc_intreq_irq037mon_field
{
        __IO  uint32_t  PPGINT0                  :1;
        __IO  uint32_t  PPGINT1                  :1;
        __IO  uint32_t  PPGINT2                  :1;
        __IO  uint32_t  RESERVED0                :29;
} stc_intreq_irq037mon_field_t;

typedef struct stc_intreq_irq038mon_field
{
        __IO  uint32_t  PPGINT0                  :1;
        __IO  uint32_t  PPGINT1                  :1;
        __IO  uint32_t  PPGINT2                  :1;
        __IO  uint32_t  RESERVED0                :29;
} stc_intreq_irq038mon_field_t;

typedef struct stc_intreq_irq039mon_field
{
        __IO  uint32_t  BTINT0                   :1;
        __IO  uint32_t  BTINT1                   :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_irq039mon_field_t;

typedef struct stc_intreq_irq040mon_field
{
        __IO  uint32_t  BTINT0                   :1;
        __IO  uint32_t  BTINT1                   :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_irq040mon_field_t;

typedef struct stc_intreq_irq041mon_field
{
        __IO  uint32_t  BTINT0                   :1;
        __IO  uint32_t  BTINT1                   :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_irq041mon_field_t;

typedef struct stc_intreq_irq042mon_field
{
        __IO  uint32_t  BTINT0                   :1;
        __IO  uint32_t  BTINT1                   :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_irq042mon_field_t;

typedef struct stc_intreq_irq043mon_field
{
        __IO  uint32_t  BTINT0                   :1;
        __IO  uint32_t  BTINT1                   :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_irq043mon_field_t;

typedef struct stc_intreq_irq044mon_field
{
        __IO  uint32_t  BTINT0                   :1;
        __IO  uint32_t  BTINT1                   :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_irq044mon_field_t;

typedef struct stc_intreq_irq045mon_field
{
        __IO  uint32_t  BTINT0                   :1;
        __IO  uint32_t  BTINT1                   :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_irq045mon_field_t;

typedef struct stc_intreq_irq046mon_field
{
        __IO  uint32_t  BTINT0                   :1;
        __IO  uint32_t  BTINT1                   :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_irq046mon_field_t;

typedef struct stc_intreq_irq047mon_field
{
        __IO  uint32_t  TIMINT1                  :1;
        __IO  uint32_t  TIMINT2                  :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_irq047mon_field_t;

typedef struct stc_intreq_irq048mon_field
{
        __IO  uint32_t  WCINT                    :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq048mon_field_t;

typedef struct stc_intreq_irq049mon_field
{
        __IO  uint32_t  BMEMCS                   :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq049mon_field_t;

typedef struct stc_intreq_irq050mon_field
{
        __IO  uint32_t  RTCINT                   :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq050mon_field_t;

typedef struct stc_intreq_irq051mon_field
{
        __IO  uint32_t  EXTINT                   :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq051mon_field_t;

typedef struct stc_intreq_irq052mon_field
{
        __IO  uint32_t  EXTINT                   :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq052mon_field_t;

typedef struct stc_intreq_irq053mon_field
{
        __IO  uint32_t  EXTINT                   :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq053mon_field_t;

typedef struct stc_intreq_irq054mon_field
{
        __IO  uint32_t  EXTINT                   :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq054mon_field_t;

typedef struct stc_intreq_irq055mon_field
{
        __IO  uint32_t  EXTINT                   :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq055mon_field_t;

typedef struct stc_intreq_irq056mon_field
{
        __IO  uint32_t  EXTINT                   :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq056mon_field_t;

typedef struct stc_intreq_irq057mon_field
{
        __IO  uint32_t  EXTINT                   :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq057mon_field_t;

typedef struct stc_intreq_irq058mon_field
{
        __IO  uint32_t  EXTINT                   :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq058mon_field_t;

typedef struct stc_intreq_irq059mon_field
{
        __IO  uint32_t  MOSCINT                  :1;
        __IO  uint32_t  SOSCINT                  :1;
        __IO  uint32_t  MPLLINT                  :1;
        __IO  uint32_t  UPLLINT                  :1;
        __IO  uint32_t  IPLLINT                  :1;
        __IO  uint32_t  RESERVED0                :27;
} stc_intreq_irq059mon_field_t;

typedef struct stc_intreq_irq060mon_field
{
        __IO  uint32_t  MFSINT0_RX               :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq060mon_field_t;

typedef struct stc_intreq_irq061mon_field
{
        __IO  uint32_t  MFSINT0_TX               :1;
        __IO  uint32_t  MFSINT0_STATUS           :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_irq061mon_field_t;

typedef struct stc_intreq_irq062mon_field
{
        __IO  uint32_t  MFSINT1_RX               :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq062mon_field_t;

typedef struct stc_intreq_irq063mon_field
{
        __IO  uint32_t  MFSINT1_TX               :1;
        __IO  uint32_t  MFSINT1_STATUS           :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_irq063mon_field_t;

typedef struct stc_intreq_irq064mon_field
{
        __IO  uint32_t  MFSINT2_RX               :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq064mon_field_t;

typedef struct stc_intreq_irq065mon_field
{
        __IO  uint32_t  MFSINT2_TX               :1;
        __IO  uint32_t  MFSINT2_STATUS           :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_irq065mon_field_t;

typedef struct stc_intreq_irq066mon_field
{
        __IO  uint32_t  MFSINT3_RX               :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq066mon_field_t;

typedef struct stc_intreq_irq067mon_field
{
        __IO  uint32_t  MFSINT3_TX               :1;
        __IO  uint32_t  MFSINT3_STATUS           :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_irq067mon_field_t;

typedef struct stc_intreq_irq068mon_field
{
        __IO  uint32_t  MFSINT4_RX               :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq068mon_field_t;

typedef struct stc_intreq_irq069mon_field
{
        __IO  uint32_t  MFSINT4_TX               :1;
        __IO  uint32_t  MFSINT4_STATUS           :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_irq069mon_field_t;

typedef struct stc_intreq_irq070mon_field
{
        __IO  uint32_t  MFSINT5_RX               :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq070mon_field_t;

typedef struct stc_intreq_irq071mon_field
{
        __IO  uint32_t  MFSINT5_TX               :1;
        __IO  uint32_t  MFSINT5_STATUS           :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_irq071mon_field_t;

typedef struct stc_intreq_irq072mon_field
{
        __IO  uint32_t  MFSINT6_RX               :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq072mon_field_t;

typedef struct stc_intreq_irq073mon_field
{
        __IO  uint32_t  MFSINT6_TX               :1;
        __IO  uint32_t  MFSINT6_STATUS           :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_irq073mon_field_t;

typedef struct stc_intreq_irq074mon_field
{
        __IO  uint32_t  MFSINT7_RX               :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq074mon_field_t;

typedef struct stc_intreq_irq075mon_field
{
        __IO  uint32_t  MFSINT7_TX               :1;
        __IO  uint32_t  MFSINT7_STATUS           :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_irq075mon_field_t;

typedef struct stc_intreq_irq076mon_field
{
        __IO  uint32_t  ADCINT0                  :1;
        __IO  uint32_t  ADCINT1                  :1;
        __IO  uint32_t  ADCINT2                  :1;
        __IO  uint32_t  ADCINT3                  :1;
        __IO  uint32_t  ADCINT4                  :1;
        __IO  uint32_t  RESERVED0                :27;
} stc_intreq_irq076mon_field_t;

typedef struct stc_intreq_irq077mon_field
{
        __IO  uint32_t  ADCINT0                  :1;
        __IO  uint32_t  ADCINT1                  :1;
        __IO  uint32_t  ADCINT2                  :1;
        __IO  uint32_t  ADCINT3                  :1;
        __IO  uint32_t  ADCINT4                  :1;
        __IO  uint32_t  RESERVED0                :27;
} stc_intreq_irq077mon_field_t;

typedef struct stc_intreq_irq078mon_field
{
        __IO  uint32_t  USB_DRQ_INT0             :1;
        __IO  uint32_t  USB_DRQ_INT1             :1;
        __IO  uint32_t  USB_DRQ_INT2             :1;
        __IO  uint32_t  USB_DRQ_INT3             :1;
        __IO  uint32_t  USB_DRQ_INT4             :1;
        __IO  uint32_t  RESERVED0                :27;
} stc_intreq_irq078mon_field_t;

typedef struct stc_intreq_irq079mon_field
{
        __IO  uint32_t  USB_INT0                 :1;
        __IO  uint32_t  USB_INT1                 :1;
        __IO  uint32_t  USB_INT2                 :1;
        __IO  uint32_t  USB_INT3                 :1;
        __IO  uint32_t  USB_INT4                 :1;
        __IO  uint32_t  USB_INT5                 :1;
        __IO  uint32_t  RESERVED0                :26;
} stc_intreq_irq079mon_field_t;

typedef struct stc_intreq_irq080mon_field
{
        __IO  uint32_t  CANINT                   :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq080mon_field_t;

typedef struct stc_intreq_irq081mon_field
{
        __IO  uint32_t  CANINT                   :1;
        __IO  uint32_t  CANDEINT                 :1;
        __IO  uint32_t  CANSEINT                 :1;
        __IO  uint32_t  CAN0INT                  :1;
        __IO  uint32_t  CAN1INT                  :1;
        __IO  uint32_t  RESERVED0                :27;
} stc_intreq_irq081mon_field_t;

typedef struct stc_intreq_irq082mon_field
{
        __IO  uint32_t  MACSBD                   :1;
        __IO  uint32_t  MACPMT                   :1;
        __IO  uint32_t  MACLPI                   :1;
        __IO  uint32_t  RESERVED0                :29;
} stc_intreq_irq082mon_field_t;

typedef struct stc_intreq_irq083mon_field
{
        __IO  uint32_t  DMACINT                  :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq083mon_field_t;

typedef struct stc_intreq_irq084mon_field
{
        __IO  uint32_t  DMACINT                  :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq084mon_field_t;

typedef struct stc_intreq_irq085mon_field
{
        __IO  uint32_t  DMACINT                  :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq085mon_field_t;

typedef struct stc_intreq_irq086mon_field
{
        __IO  uint32_t  DMACINT                  :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq086mon_field_t;

typedef struct stc_intreq_irq087mon_field
{
        __IO  uint32_t  DMACINT                  :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq087mon_field_t;

typedef struct stc_intreq_irq088mon_field
{
        __IO  uint32_t  DMACINT                  :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq088mon_field_t;

typedef struct stc_intreq_irq089mon_field
{
        __IO  uint32_t  DMACINT                  :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq089mon_field_t;

typedef struct stc_intreq_irq090mon_field
{
        __IO  uint32_t  DMACINT                  :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq090mon_field_t;

typedef struct stc_intreq_irq091mon_field
{
        __IO  uint32_t  DSTCINT0                 :1;
        __IO  uint32_t  DSTCINT1                 :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_irq091mon_field_t;

typedef struct stc_intreq_irq092mon_field
{
        __IO  uint32_t  EXTINT0                  :1;
        __IO  uint32_t  EXTINT1                  :1;
        __IO  uint32_t  EXTINT2                  :1;
        __IO  uint32_t  EXTINT3                  :1;
        __IO  uint32_t  RESERVED0                :28;
} stc_intreq_irq092mon_field_t;

typedef struct stc_intreq_irq093mon_field
{
        __IO  uint32_t  EXTINT0                  :1;
        __IO  uint32_t  EXTINT1                  :1;
        __IO  uint32_t  EXTINT2                  :1;
        __IO  uint32_t  EXTINT3                  :1;
        __IO  uint32_t  RESERVED0                :28;
} stc_intreq_irq093mon_field_t;

typedef struct stc_intreq_irq094mon_field
{
        __IO  uint32_t  EXTINT0                  :1;
        __IO  uint32_t  EXTINT1                  :1;
        __IO  uint32_t  EXTINT2                  :1;
        __IO  uint32_t  EXTINT3                  :1;
        __IO  uint32_t  RESERVED0                :28;
} stc_intreq_irq094mon_field_t;

typedef struct stc_intreq_irq095mon_field
{
        __IO  uint32_t  EXTINT0                  :1;
        __IO  uint32_t  EXTINT1                  :1;
        __IO  uint32_t  EXTINT2                  :1;
        __IO  uint32_t  EXTINT3                  :1;
        __IO  uint32_t  RESERVED0                :28;
} stc_intreq_irq095mon_field_t;

typedef struct stc_intreq_irq096mon_field
{
        __IO  uint32_t  QPRCINT0                 :1;
        __IO  uint32_t  QPRCINT1                 :1;
        __IO  uint32_t  QPRCINT2                 :1;
        __IO  uint32_t  QPRCINT3                 :1;
        __IO  uint32_t  QPRCINT4                 :1;
        __IO  uint32_t  QPRCINT5                 :1;
        __IO  uint32_t  RESERVED0                :26;
} stc_intreq_irq096mon_field_t;

typedef struct stc_intreq_irq097mon_field
{
        __IO  uint32_t  QPRCINT0                 :1;
        __IO  uint32_t  QPRCINT1                 :1;
        __IO  uint32_t  QPRCINT2                 :1;
        __IO  uint32_t  QPRCINT3                 :1;
        __IO  uint32_t  QPRCINT4                 :1;
        __IO  uint32_t  QPRCINT5                 :1;
        __IO  uint32_t  RESERVED0                :26;
} stc_intreq_irq097mon_field_t;

typedef struct stc_intreq_irq098mon_field
{
        __IO  uint32_t  BTINT0                   :1;
        __IO  uint32_t  BTINT1                   :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_irq098mon_field_t;

typedef struct stc_intreq_irq099mon_field
{
        __IO  uint32_t  BTINT0                   :1;
        __IO  uint32_t  BTINT1                   :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_irq099mon_field_t;

typedef struct stc_intreq_irq100mon_field
{
        __IO  uint32_t  BTINT0                   :1;
        __IO  uint32_t  BTINT1                   :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_irq100mon_field_t;

typedef struct stc_intreq_irq101mon_field
{
        __IO  uint32_t  BTINT0                   :1;
        __IO  uint32_t  BTINT1                   :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_irq101mon_field_t;

typedef struct stc_intreq_irq102mon_field
{
        __IO  uint32_t  BTINT0                   :1;
        __IO  uint32_t  BTINT1                   :1;
        __IO  uint32_t  BTINT2                   :1;
        __IO  uint32_t  BTINT3                   :1;
        __IO  uint32_t  BTINT4                   :1;
        __IO  uint32_t  BTINT5                   :1;
        __IO  uint32_t  BTINT6                   :1;
        __IO  uint32_t  BTINT7                   :1;
        __IO  uint32_t  RESERVED0                :24;
} stc_intreq_irq102mon_field_t;

typedef struct stc_intreq_irq103mon_field
{
        __IO  uint32_t  MFSINT8_RX               :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq103mon_field_t;

typedef struct stc_intreq_irq104mon_field
{
        __IO  uint32_t  MFSINT8_TX               :1;
        __IO  uint32_t  MFSINT8_STATUS           :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_irq104mon_field_t;

typedef struct stc_intreq_irq105mon_field
{
        __IO  uint32_t  MFSINT9_RX               :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq105mon_field_t;

typedef struct stc_intreq_irq106mon_field
{
        __IO  uint32_t  MFSINT9_TX               :1;
        __IO  uint32_t  MFSINT9_STATUS           :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_irq106mon_field_t;

typedef struct stc_intreq_irq107mon_field
{
        __IO  uint32_t  MFSINT10_RX              :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq107mon_field_t;

typedef struct stc_intreq_irq108mon_field
{
        __IO  uint32_t  MFSINT10_TX              :1;
        __IO  uint32_t  MFSINT10_STATUS          :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_irq108mon_field_t;

typedef struct stc_intreq_irq109mon_field
{
        __IO  uint32_t  MFSINT11_RX              :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq109mon_field_t;

typedef struct stc_intreq_irq110mon_field
{
        __IO  uint32_t  MFSINT11_TX              :1;
        __IO  uint32_t  MFSINT11_STATUS          :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_irq110mon_field_t;

typedef struct stc_intreq_irq111mon_field
{
        __IO  uint32_t  ADCINT0                  :1;
        __IO  uint32_t  ADCINT1                  :1;
        __IO  uint32_t  ADCINT2                  :1;
        __IO  uint32_t  ADCINT3                  :1;
        __IO  uint32_t  ADCINT4                  :1;
        __IO  uint32_t  RESERVED0                :27;
} stc_intreq_irq111mon_field_t;

typedef struct stc_intreq_irq112mon_field
{
        __IO  uint32_t  I2SDINT0                 :1;
        __IO  uint32_t  I2SDINT1                 :1;
        __IO  uint32_t  HSSPIDINT0               :1;
        __IO  uint32_t  HSSPIDINT1               :1;
        __IO  uint32_t  PCRCDINT                 :1;
        __IO  uint32_t  CANDINT                  :1;
        __IO  uint32_t  RESERVED0                :26;
} stc_intreq_irq112mon_field_t;

typedef struct stc_intreq_irq113mon_field
{
        __IO  uint32_t  USB_DRQ_INT0             :1;
        __IO  uint32_t  USB_DRQ_INT1             :1;
        __IO  uint32_t  USB_DRQ_INT2             :1;
        __IO  uint32_t  USB_DRQ_INT3             :1;
        __IO  uint32_t  USB_DRQ_INT4             :1;
        __IO  uint32_t  RCEC0INT                 :1;
        __IO  uint32_t  RESERVED0                :26;
} stc_intreq_irq113mon_field_t;

typedef struct stc_intreq_irq114mon_field
{
        __IO  uint32_t  USB_INT0                 :1;
        __IO  uint32_t  USB_INT1                 :1;
        __IO  uint32_t  USB_INT2                 :1;
        __IO  uint32_t  USB_INT3                 :1;
        __IO  uint32_t  USB_INT4                 :1;
        __IO  uint32_t  USB_INT5                 :1;
        __IO  uint32_t  RCEC1INT                 :1;
        __IO  uint32_t  RESERVED0                :25;
} stc_intreq_irq114mon_field_t;

typedef struct stc_intreq_irq115mon_field
{
        __IO  uint32_t  HSSPIINT0                :1;
        __IO  uint32_t  HSSPIINT1                :1;
        __IO  uint32_t  HSSPIINT2                :1;
        __IO  uint32_t  RESERVED0                :29;
} stc_intreq_irq115mon_field_t;

typedef struct stc_intreq_irq117mon_field
{
        __IO  uint32_t  I2SINT                   :1;
        __IO  uint32_t  PCRC                     :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_irq117mon_field_t;

typedef struct stc_intreq_irq118mon_field
{
        __IO  uint32_t  SDINT0                   :1;
        __IO  uint32_t  SDINT1                   :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_irq118mon_field_t;

typedef struct stc_intreq_irq119mon_field
{
        __IO  uint32_t  FLINT                    :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq119mon_field_t;

typedef struct stc_intreq_irq120mon_field
{
        __IO  uint32_t  MFSINT12_RX              :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq120mon_field_t;

typedef struct stc_intreq_irq121mon_field
{
        __IO  uint32_t  MFSINT12_TX              :1;
        __IO  uint32_t  MFSINT12_STATUS          :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_irq121mon_field_t;

typedef struct stc_intreq_irq122mon_field
{
        __IO  uint32_t  MFSINT13_RX              :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq122mon_field_t;

typedef struct stc_intreq_irq123mon_field
{
        __IO  uint32_t  MFSINT13_TX              :1;
        __IO  uint32_t  MFSINT13_STATUS          :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_irq123mon_field_t;

typedef struct stc_intreq_irq124mon_field
{
        __IO  uint32_t  MFSINT14_RX              :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq124mon_field_t;

typedef struct stc_intreq_irq125mon_field
{
        __IO  uint32_t  MFSINT14_TX              :1;
        __IO  uint32_t  MFSINT14_STATUS          :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_irq125mon_field_t;

typedef struct stc_intreq_irq126mon_field
{
        __IO  uint32_t  MFSINT15_RX              :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_intreq_irq126mon_field_t;

typedef struct stc_intreq_irq127mon_field
{
        __IO  uint32_t  MFSINT15_TX              :1;
        __IO  uint32_t  MFSINT15_STATUS          :1;
        __IO  uint32_t  RESERVED0                :30;
} stc_intreq_irq127mon_field_t;

/*******************************************************************************
* LSCRP_MODULE
*******************************************************************************/
typedef struct stc_lscrp_lcr_prsld_field
{
    union {
        struct {
            __IO   uint8_t  LCR_PRSLD            :6;
            __IO   uint8_t  RESERVED0            :2;
        };
        struct {
            __IO   uint8_t  LCR_PRSLD0           :1;
            __IO   uint8_t  LCR_PRSLD1           :1;
            __IO   uint8_t  LCR_PRSLD2           :1;
            __IO   uint8_t  LCR_PRSLD3           :1;
            __IO   uint8_t  LCR_PRSLD4           :1;
            __IO   uint8_t  LCR_PRSLD5           :1;
            __IO   uint8_t  RESERVED1            :2;
        };
    };
} stc_lscrp_lcr_prsld_field_t;

/*******************************************************************************
* LVD_MODULE
*******************************************************************************/
typedef struct stc_lvd_lvd_ctl_field
{
    union {
        struct {
            __IO   uint8_t  RESERVED0            :2;
            __IO   uint8_t  SVHI                 :5;
            __IO   uint8_t  LVDIE                :1;
        };
        struct {
            __IO   uint8_t  RESERVED1            :2;
            __IO   uint8_t  SVHI0                :1;
            __IO   uint8_t  SVHI1                :1;
            __IO   uint8_t  SVHI2                :1;
            __IO   uint8_t  SVHI3                :1;
            __IO   uint8_t  SVHI4                :1;
            __IO   uint8_t  RESERVED2            :1;
        };
    };
} stc_lvd_lvd_ctl_field_t;

typedef struct stc_lvd_lvd_str_field
{
        __IO   uint8_t  RESERVED0                :7;
        __IO   uint8_t  LVDIR                    :1;
} stc_lvd_lvd_str_field_t;

typedef struct stc_lvd_lvd_clr_field
{
        __IO   uint8_t  RESERVED0                :7;
        __IO   uint8_t  LVDCL                    :1;
} stc_lvd_lvd_clr_field_t;

typedef struct stc_lvd_lvd_rlr_field
{
    union {
        struct {
            __IO  uint32_t  LVDLCK               :32;
        };
        struct {
            __IO  uint32_t  LVDLCK0              :1;
            __IO  uint32_t  LVDLCK1              :1;
            __IO  uint32_t  LVDLCK2              :1;
            __IO  uint32_t  LVDLCK3              :1;
            __IO  uint32_t  LVDLCK4              :1;
            __IO  uint32_t  LVDLCK5              :1;
            __IO  uint32_t  LVDLCK6              :1;
            __IO  uint32_t  LVDLCK7              :1;
            __IO  uint32_t  LVDLCK8              :1;
            __IO  uint32_t  LVDLCK9              :1;
            __IO  uint32_t  LVDLCK10             :1;
            __IO  uint32_t  LVDLCK11             :1;
            __IO  uint32_t  LVDLCK12             :1;
            __IO  uint32_t  LVDLCK13             :1;
            __IO  uint32_t  LVDLCK14             :1;
            __IO  uint32_t  LVDLCK15             :1;
            __IO  uint32_t  LVDLCK16             :1;
            __IO  uint32_t  LVDLCK17             :1;
            __IO  uint32_t  LVDLCK18             :1;
            __IO  uint32_t  LVDLCK19             :1;
            __IO  uint32_t  LVDLCK20             :1;
            __IO  uint32_t  LVDLCK21             :1;
            __IO  uint32_t  LVDLCK22             :1;
            __IO  uint32_t  LVDLCK23             :1;
            __IO  uint32_t  LVDLCK24             :1;
            __IO  uint32_t  LVDLCK25             :1;
            __IO  uint32_t  LVDLCK26             :1;
            __IO  uint32_t  LVDLCK27             :1;
            __IO  uint32_t  LVDLCK28             :1;
            __IO  uint32_t  LVDLCK29             :1;
            __IO  uint32_t  LVDLCK30             :1;
            __IO  uint32_t  LVDLCK31             :1;
        };
    };
} stc_lvd_lvd_rlr_field_t;

typedef struct stc_lvd_lvd_str2_field
{
        __IO   uint8_t  RESERVED0                :7;
        __IO   uint8_t  LVDIRDY                  :1;
} stc_lvd_lvd_str2_field_t;

/*******************************************************************************
* MFS_MODULE
*******************************************************************************/
typedef struct stc_mfs_smr_field
{
    union {
        union {
            struct {
                __IO   uint8_t  SOE              :1;
                __IO   uint8_t  SCKE             :1;
                __IO   uint8_t  BDS              :1;
                __IO   uint8_t  SCINV            :1;
                __IO   uint8_t  RESERVED0        :1;
                __IO   uint8_t  MD               :3;
            };
            struct {
                __IO   uint8_t  RESERVED1        :5;
                __IO   uint8_t  MD0              :1;
                __IO   uint8_t  MD1              :1;
                __IO   uint8_t  MD2              :1;
            };
        };
        union {
            struct {
                __IO   uint8_t  RESERVED2        :2;
                __IO   uint8_t  TIE              :1;
                __IO   uint8_t  RIE              :1;
                __IO   uint8_t  RESERVED3        :4;
            };
            struct {
                __IO   uint8_t  RESERVED4        :8;
            };
        };
        union {
            struct {
                __IO   uint8_t  RESERVED5        :3;
                __IO   uint8_t  SBL              :1;
                __IO   uint8_t  WUCR             :1;
                __IO   uint8_t  RESERVED6        :3;
            };
            struct {
                __IO   uint8_t  RESERVED7        :8;
            };
        };
    };
} stc_mfs_smr_field_t;

typedef struct stc_mfs_ibcr_field
{
    union {
        struct {
            __IO   uint8_t  TXE                  :1;
            __IO   uint8_t  RXE                  :1;
            __IO   uint8_t  TBIE                 :1;
            __IO   uint8_t  TIE                  :1;
            __IO   uint8_t  RIE                  :1;
            __IO   uint8_t  SPI                  :1;
            __IO   uint8_t  MS                   :1;
            __IO   uint8_t  UPCL                 :1;
        };
        struct {
            __IO   uint8_t  INT                  :1;
            __IO   uint8_t  BER                  :1;
            __IO   uint8_t  INTE                 :1;
            __IO   uint8_t  CNDE                 :1;
            __IO   uint8_t  WSEL                 :1;
            __IO   uint8_t  ACKE                 :1;
            __IO   uint8_t  ACT_SCC              :1;
            __IO   uint8_t  MSS                  :1;
        };
        struct {
            __IO   uint8_t  RESERVED2            :5;
            __IO   uint8_t  LBR                  :1;
            __IO   uint8_t  RESERVED3            :2;
        };
    };
} stc_mfs_ibcr_field_t;

typedef struct stc_mfs_scr_field
{
    union {
        struct {
            __IO   uint8_t  TXE                  :1;
            __IO   uint8_t  RXE                  :1;
            __IO   uint8_t  TBIE                 :1;
            __IO   uint8_t  TIE                  :1;
            __IO   uint8_t  RIE                  :1;
            __IO   uint8_t  SPI                  :1;
            __IO   uint8_t  MS                   :1;
            __IO   uint8_t  UPCL                 :1;
        };
        struct {
            __IO   uint8_t  INT                  :1;
            __IO   uint8_t  BER                  :1;
            __IO   uint8_t  INTE                 :1;
            __IO   uint8_t  CNDE                 :1;
            __IO   uint8_t  WSEL                 :1;
            __IO   uint8_t  ACKE                 :1;
            __IO   uint8_t  ACT_SCC              :1;
            __IO   uint8_t  MSS                  :1;
        };
        struct {
            __IO   uint8_t  RESERVED2            :5;
            __IO   uint8_t  LBR                  :1;
            __IO   uint8_t  RESERVED3            :2;
        };
    };
} stc_mfs_scr_field_t;

typedef struct stc_mfs_escr_field
{
    union {
        union {
            struct {
                __IO   uint8_t  L                :3;
                __IO   uint8_t  WT               :2;
                __IO   uint8_t  CSFE             :1;
                __IO   uint8_t  L3               :1;
                __IO   uint8_t  SOP              :1;
            };
            struct {
                __IO   uint8_t  L0               :1;
                __IO   uint8_t  L1               :1;
                __IO   uint8_t  L2               :1;
                __IO   uint8_t  WT0              :1;
                __IO   uint8_t  WT1              :1;
                __IO   uint8_t  RESERVED0        :3;
            };
        };
        struct {
            __IO   uint8_t  BB                   :1;
            __IO   uint8_t  SPC                  :1;
            __IO   uint8_t  RSC                  :1;
            __IO   uint8_t  AL                   :1;
            __IO   uint8_t  TRX                  :1;
            __IO   uint8_t  RSA                  :1;
            __IO   uint8_t  RACK                 :1;
            __IO   uint8_t  FBT                  :1;
        };
        union {
            struct {
                __IO   uint8_t  DEL              :2;
                __IO   uint8_t  LBL              :2;
                __IO   uint8_t  LBIE             :1;
                __IO   uint8_t  RESERVED2        :1;
                __IO   uint8_t  ESBL             :1;
                __IO   uint8_t  RESERVED3        :1;
            };
            struct {
                __IO   uint8_t  DEL0             :1;
                __IO   uint8_t  DEL1             :1;
                __IO   uint8_t  LBL0             :1;
                __IO   uint8_t  LBL1             :1;
                __IO   uint8_t  RESERVED4        :4;
            };
        };
        union {
            struct {
                __IO   uint8_t  RESERVED5        :3;
                __IO   uint8_t  P                :1;
                __IO   uint8_t  PEN              :1;
                __IO   uint8_t  INV              :1;
                __IO   uint8_t  RESERVED6        :1;
                __IO   uint8_t  FLWEN            :1;
            };
            struct {
                __IO   uint8_t  RESERVED7        :8;
            };
        };
    };
} stc_mfs_escr_field_t;

typedef struct stc_mfs_ibsr_field
{
    union {
        union {
            struct {
                __IO   uint8_t  L                :3;
                __IO   uint8_t  WT               :2;
                __IO   uint8_t  CSFE             :1;
                __IO   uint8_t  L3               :1;
                __IO   uint8_t  SOP              :1;
            };
            struct {
                __IO   uint8_t  L0               :1;
                __IO   uint8_t  L1               :1;
                __IO   uint8_t  L2               :1;
                __IO   uint8_t  WT0              :1;
                __IO   uint8_t  WT1              :1;
                __IO   uint8_t  RESERVED0        :3;
            };
        };
        struct {
            __IO   uint8_t  BB                   :1;
            __IO   uint8_t  SPC                  :1;
            __IO   uint8_t  RSC                  :1;
            __IO   uint8_t  AL                   :1;
            __IO   uint8_t  TRX                  :1;
            __IO   uint8_t  RSA                  :1;
            __IO   uint8_t  RACK                 :1;
            __IO   uint8_t  FBT                  :1;
        };
        union {
            struct {
                __IO   uint8_t  DEL              :2;
                __IO   uint8_t  LBL              :2;
                __IO   uint8_t  LBIE             :1;
                __IO   uint8_t  RESERVED2        :1;
                __IO   uint8_t  ESBL             :1;
                __IO   uint8_t  RESERVED3        :1;
            };
            struct {
                __IO   uint8_t  DEL0             :1;
                __IO   uint8_t  DEL1             :1;
                __IO   uint8_t  LBL0             :1;
                __IO   uint8_t  LBL1             :1;
                __IO   uint8_t  RESERVED4        :4;
            };
        };
        union {
            struct {
                __IO   uint8_t  RESERVED5        :3;
                __IO   uint8_t  P                :1;
                __IO   uint8_t  PEN              :1;
                __IO   uint8_t  INV              :1;
                __IO   uint8_t  RESERVED6        :1;
                __IO   uint8_t  FLWEN            :1;
            };
            struct {
                __IO   uint8_t  RESERVED7        :8;
            };
        };
    };
} stc_mfs_ibsr_field_t;

typedef struct stc_mfs_ssr_field
{
    union {
        struct {
            __IO   uint8_t  TBI                  :1;
            __IO   uint8_t  TDRE                 :1;
            __IO   uint8_t  RDRF                 :1;
            __IO   uint8_t  ORE                  :1;
            __IO   uint8_t  AWC                  :1;
            __IO   uint8_t  RESERVED0            :2;
            __IO   uint8_t  REC                  :1;
        };
        struct {
            __IO   uint8_t  RESERVED2            :4;
            __IO   uint8_t  TBIE                 :1;
            __IO   uint8_t  DMA                  :1;
            __IO   uint8_t  TSET                 :1;
            __IO   uint8_t  RESERVED3            :1;
        };
        struct {
            __IO   uint8_t  RESERVED5            :4;
            __IO   uint8_t  FRE                  :1;
            __IO   uint8_t  LBD                  :1;
            __IO   uint8_t  RESERVED6            :2;
        };
        struct {
            __IO   uint8_t  RESERVED8            :5;
            __IO   uint8_t  PE                   :1;
            __IO   uint8_t  RESERVED9            :2;
        };
    };
} stc_mfs_ssr_field_t;

typedef struct stc_mfs_rdr_field
{
    union {
        union {
            struct {
                __IO  uint16_t  D                :16;
            };
            struct {
                __IO  uint16_t  D0               :1;
                __IO  uint16_t  D1               :1;
                __IO  uint16_t  D2               :1;
                __IO  uint16_t  D3               :1;
                __IO  uint16_t  D4               :1;
                __IO  uint16_t  D5               :1;
                __IO  uint16_t  D6               :1;
                __IO  uint16_t  D7               :1;
                __IO  uint16_t  D8               :1;
                __IO  uint16_t  D9               :1;
                __IO  uint16_t  D10              :1;
                __IO  uint16_t  D11              :1;
                __IO  uint16_t  D12              :1;
                __IO  uint16_t  D13              :1;
                __IO  uint16_t  D14              :1;
                __IO  uint16_t  D15              :1;
            };
        };
    };
} stc_mfs_rdr_field_t;

typedef struct stc_mfs_tdr_field
{
    union {
        union {
            struct {
                __IO  uint16_t  D                :16;
            };
            struct {
                __IO  uint16_t  D0               :1;
                __IO  uint16_t  D1               :1;
                __IO  uint16_t  D2               :1;
                __IO  uint16_t  D3               :1;
                __IO  uint16_t  D4               :1;
                __IO  uint16_t  D5               :1;
                __IO  uint16_t  D6               :1;
                __IO  uint16_t  D7               :1;
                __IO  uint16_t  D8               :1;
                __IO  uint16_t  D9               :1;
                __IO  uint16_t  D10              :1;
                __IO  uint16_t  D11              :1;
                __IO  uint16_t  D12              :1;
                __IO  uint16_t  D13              :1;
                __IO  uint16_t  D14              :1;
                __IO  uint16_t  D15              :1;
            };
        };
    };
} stc_mfs_tdr_field_t;

typedef struct stc_mfs_bgr_field
{
    union {
        union {
            struct {
                __IO  uint16_t  BGR              :15;
                __IO  uint16_t  RESERVED0        :1;
            };
            struct {
                __IO  uint16_t  BGR0             :1;
                __IO  uint16_t  BGR1             :1;
                __IO  uint16_t  BGR2             :1;
                __IO  uint16_t  BGR3             :1;
                __IO  uint16_t  BGR4             :1;
                __IO  uint16_t  BGR5             :1;
                __IO  uint16_t  BGR6             :1;
                __IO  uint16_t  BGR7             :1;
                __IO  uint16_t  BGR8             :1;
                __IO  uint16_t  BGR9             :1;
                __IO  uint16_t  BGR10            :1;
                __IO  uint16_t  BGR11            :1;
                __IO  uint16_t  BGR12            :1;
                __IO  uint16_t  BGR13            :1;
                __IO  uint16_t  BGR14            :1;
                __IO  uint16_t  RESERVED1        :1;
            };
        };
        union {
            struct {
                __IO  uint16_t  RESERVED4        :15;
                __IO  uint16_t  EXT              :1;
            };
            struct {
                __IO  uint16_t  RESERVED5        :16;
            };
        };
    };
} stc_mfs_bgr_field_t;

typedef struct stc_mfs_isba_field
{
    union {
        struct {
            __IO   uint8_t  SA                   :7;
            __IO   uint8_t  SAEN                 :1;
        };
        struct {
            __IO   uint8_t  SA0                  :1;
            __IO   uint8_t  SA1                  :1;
            __IO   uint8_t  SA2                  :1;
            __IO   uint8_t  SA3                  :1;
            __IO   uint8_t  SA4                  :1;
            __IO   uint8_t  SA5                  :1;
            __IO   uint8_t  SA6                  :1;
            __IO   uint8_t  RESERVED0            :1;
        };
    };
} stc_mfs_isba_field_t;

typedef struct stc_mfs_ismk_field
{
    union {
        struct {
            __IO   uint8_t  SM                   :7;
            __IO   uint8_t  EN                   :1;
        };
        struct {
            __IO   uint8_t  SM0                  :1;
            __IO   uint8_t  SM1                  :1;
            __IO   uint8_t  SM2                  :1;
            __IO   uint8_t  SM3                  :1;
            __IO   uint8_t  SM4                  :1;
            __IO   uint8_t  SM5                  :1;
            __IO   uint8_t  SM6                  :1;
            __IO   uint8_t  RESERVED0            :1;
        };
    };
} stc_mfs_ismk_field_t;

typedef struct stc_mfs_fcr_field
{
    union {
        struct {
            __IO  uint16_t  FE1                  :1;
            __IO  uint16_t  FE2                  :1;
            __IO  uint16_t  FCL1                 :1;
            __IO  uint16_t  FCL2                 :1;
            __IO  uint16_t  FSET                 :1;
            __IO  uint16_t  FLD                  :1;
            __IO  uint16_t  FLST                 :1;
            __IO  uint16_t  RESERVED0            :1;
            __IO  uint16_t  FSEL                 :1;
            __IO  uint16_t  FTIE                 :1;
            __IO  uint16_t  FDRQ                 :1;
            __IO  uint16_t  FRIIE                :1;
            __IO  uint16_t  FLSTE                :1;
            __IO  uint16_t  RESERVED1            :3;
        };
    };
} stc_mfs_fcr_field_t;

typedef struct stc_mfs_fbyte1_field
{
    union {
        union {
            struct {
                __IO   uint8_t  FD               :8;
            };
            struct {
                __IO   uint8_t  FD0              :1;
                __IO   uint8_t  FD1              :1;
                __IO   uint8_t  FD2              :1;
                __IO   uint8_t  FD3              :1;
                __IO   uint8_t  FD4              :1;
                __IO   uint8_t  FD5              :1;
                __IO   uint8_t  FD6              :1;
                __IO   uint8_t  FD7              :1;
            };
        };
    };
} stc_mfs_fbyte1_field_t;

typedef struct stc_mfs_fbyte2_field
{
    union {
        union {
            struct {
                __IO   uint8_t  FD               :8;
            };
            struct {
                __IO   uint8_t  FD0              :1;
                __IO   uint8_t  FD1              :1;
                __IO   uint8_t  FD2              :1;
                __IO   uint8_t  FD3              :1;
                __IO   uint8_t  FD4              :1;
                __IO   uint8_t  FD5              :1;
                __IO   uint8_t  FD6              :1;
                __IO   uint8_t  FD7              :1;
            };
        };
    };
} stc_mfs_fbyte2_field_t;

typedef struct stc_mfs_nfcr_field
{
    union {
        union {
            struct {
                __IO   uint8_t  CSHD             :8;
            };
            struct {
                __IO   uint8_t  CSHD0            :1;
                __IO   uint8_t  CSHD1            :1;
                __IO   uint8_t  CSHD2            :1;
                __IO   uint8_t  CSHD3            :1;
                __IO   uint8_t  CSHD4            :1;
                __IO   uint8_t  CSHD5            :1;
                __IO   uint8_t  CSHD6            :1;
                __IO   uint8_t  CSHD7            :1;
            };
        };
        union {
            struct {
                __IO   uint8_t  NFT              :5;
                __IO   uint8_t  RESERVED0        :3;
            };
            struct {
                __IO   uint8_t  NFT0             :1;
                __IO   uint8_t  NFT1             :1;
                __IO   uint8_t  NFT2             :1;
                __IO   uint8_t  NFT3             :1;
                __IO   uint8_t  NFT4             :1;
                __IO   uint8_t  RESERVED1        :3;
            };
        };
    };
} stc_mfs_nfcr_field_t;

typedef struct stc_mfs_scstr0_field
{
    union {
        union {
            struct {
                __IO   uint8_t  CSHD             :8;
            };
            struct {
                __IO   uint8_t  CSHD0            :1;
                __IO   uint8_t  CSHD1            :1;
                __IO   uint8_t  CSHD2            :1;
                __IO   uint8_t  CSHD3            :1;
                __IO   uint8_t  CSHD4            :1;
                __IO   uint8_t  CSHD5            :1;
                __IO   uint8_t  CSHD6            :1;
                __IO   uint8_t  CSHD7            :1;
            };
        };
        union {
            struct {
                __IO   uint8_t  NFT              :5;
                __IO   uint8_t  RESERVED0        :3;
            };
            struct {
                __IO   uint8_t  NFT0             :1;
                __IO   uint8_t  NFT1             :1;
                __IO   uint8_t  NFT2             :1;
                __IO   uint8_t  NFT3             :1;
                __IO   uint8_t  NFT4             :1;
                __IO   uint8_t  RESERVED1        :3;
            };
        };
    };
} stc_mfs_scstr0_field_t;

typedef struct stc_mfs_eibcr_field
{
    union {
        union {
            struct {
                __IO   uint8_t  CSSU             :8;
            };
            struct {
                __IO   uint8_t  CSSU0            :1;
                __IO   uint8_t  CSSU1            :1;
                __IO   uint8_t  CSSU2            :1;
                __IO   uint8_t  CSSU3            :1;
                __IO   uint8_t  CSSU4            :1;
                __IO   uint8_t  CSSU5            :1;
                __IO   uint8_t  CSSU6            :1;
                __IO   uint8_t  CSSU7            :1;
            };
        };
        struct {
            __IO   uint8_t  BEC                  :1;
            __IO   uint8_t  SOCE                 :1;
            __IO   uint8_t  SCLC                 :1;
            __IO   uint8_t  SDAC                 :1;
            __IO   uint8_t  SCLS                 :1;
            __IO   uint8_t  SDAS                 :1;
            __IO   uint8_t  RESERVED0            :2;
        };
    };
} stc_mfs_eibcr_field_t;

typedef struct stc_mfs_scstr1_field
{
    union {
        union {
            struct {
                __IO   uint8_t  CSSU             :8;
            };
            struct {
                __IO   uint8_t  CSSU0            :1;
                __IO   uint8_t  CSSU1            :1;
                __IO   uint8_t  CSSU2            :1;
                __IO   uint8_t  CSSU3            :1;
                __IO   uint8_t  CSSU4            :1;
                __IO   uint8_t  CSSU5            :1;
                __IO   uint8_t  CSSU6            :1;
                __IO   uint8_t  CSSU7            :1;
            };
        };
        struct {
            __IO   uint8_t  BEC                  :1;
            __IO   uint8_t  SOCE                 :1;
            __IO   uint8_t  SCLC                 :1;
            __IO   uint8_t  SDAC                 :1;
            __IO   uint8_t  SCLS                 :1;
            __IO   uint8_t  SDAS                 :1;
            __IO   uint8_t  RESERVED0            :2;
        };
    };
} stc_mfs_scstr1_field_t;

typedef struct stc_mfs_scstr32_field
{
    union {
        struct {
            __IO  uint16_t  CSDS                 :16;
        };
        struct {
            __IO  uint16_t  CSDS0                :1;
            __IO  uint16_t  CSDS1                :1;
            __IO  uint16_t  CSDS2                :1;
            __IO  uint16_t  CSDS3                :1;
            __IO  uint16_t  CSDS4                :1;
            __IO  uint16_t  CSDS5                :1;
            __IO  uint16_t  CSDS6                :1;
            __IO  uint16_t  CSDS7                :1;
            __IO  uint16_t  CSDS8                :1;
            __IO  uint16_t  CSDS9                :1;
            __IO  uint16_t  CSDS10               :1;
            __IO  uint16_t  CSDS11               :1;
            __IO  uint16_t  CSDS12               :1;
            __IO  uint16_t  CSDS13               :1;
            __IO  uint16_t  CSDS14               :1;
            __IO  uint16_t  CSDS15               :1;
        };
    };
} stc_mfs_scstr32_field_t;

typedef struct stc_mfs_sacsr_field
{
    union {
        struct {
            __IO  uint16_t  TMRE                 :1;
            __IO  uint16_t  TDIV                 :4;
            __IO  uint16_t  RESERVED1            :1;
            __IO  uint16_t  TSYNE                :1;
            __IO  uint16_t  TINTE                :1;
            __IO  uint16_t  TINT                 :1;
            __IO  uint16_t  RESERVED2            :2;
            __IO  uint16_t  CSE                  :1;
            __IO  uint16_t  CSEIE                :1;
            __IO  uint16_t  TBEEN                :1;
            __IO  uint16_t  RESERVED3            :2;
        };
        struct {
            __IO  uint16_t  RESERVED0            :1;
            __IO  uint16_t  TDIV0                :1;
            __IO  uint16_t  TDIV1                :1;
            __IO  uint16_t  TDIV2                :1;
            __IO  uint16_t  TDIV3                :1;
            __IO  uint16_t  RESERVED4            :11;
        };
    };
} stc_mfs_sacsr_field_t;

typedef struct stc_mfs_stmr_field
{
    union {
        struct {
            __IO  uint16_t  TM                   :16;
        };
        struct {
            __IO  uint16_t  TM0                  :1;
            __IO  uint16_t  TM1                  :1;
            __IO  uint16_t  TM2                  :1;
            __IO  uint16_t  TM3                  :1;
            __IO  uint16_t  TM4                  :1;
            __IO  uint16_t  TM5                  :1;
            __IO  uint16_t  TM6                  :1;
            __IO  uint16_t  TM7                  :1;
            __IO  uint16_t  TM8                  :1;
            __IO  uint16_t  TM9                  :1;
            __IO  uint16_t  TM10                 :1;
            __IO  uint16_t  TM11                 :1;
            __IO  uint16_t  TM12                 :1;
            __IO  uint16_t  TM13                 :1;
            __IO  uint16_t  TM14                 :1;
            __IO  uint16_t  TM15                 :1;
        };
    };
} stc_mfs_stmr_field_t;

typedef struct stc_mfs_stmcr_field
{
    union {
        struct {
            __IO  uint16_t  TC                   :16;
        };
        struct {
            __IO  uint16_t  TC0                  :1;
            __IO  uint16_t  TC1                  :1;
            __IO  uint16_t  TC2                  :1;
            __IO  uint16_t  TC3                  :1;
            __IO  uint16_t  TC4                  :1;
            __IO  uint16_t  TC5                  :1;
            __IO  uint16_t  TC6                  :1;
            __IO  uint16_t  TC7                  :1;
            __IO  uint16_t  TC8                  :1;
            __IO  uint16_t  TC9                  :1;
            __IO  uint16_t  TC10                 :1;
            __IO  uint16_t  TC11                 :1;
            __IO  uint16_t  TC12                 :1;
            __IO  uint16_t  TC13                 :1;
            __IO  uint16_t  TC14                 :1;
            __IO  uint16_t  TC15                 :1;
        };
    };
} stc_mfs_stmcr_field_t;

typedef struct stc_mfs_scscr_field
{
    union {
        struct {
            __IO  uint16_t  CSOE                 :1;
            __IO  uint16_t  CSEN0                :1;
            __IO  uint16_t  CSEN1                :1;
            __IO  uint16_t  CSEN2                :1;
            __IO  uint16_t  CSEN3                :1;
            __IO  uint16_t  CSLVL                :1;
            __IO  uint16_t  CDIV                 :3;
            __IO  uint16_t  SCAM                 :1;
            __IO  uint16_t  SCD                  :2;
            __IO  uint16_t  SED                  :2;
            __IO  uint16_t  SST                  :2;
        };
        struct {
            __IO  uint16_t  RESERVED0            :6;
            __IO  uint16_t  CDIV0                :1;
            __IO  uint16_t  CDIV1                :1;
            __IO  uint16_t  CDIV2                :1;
            __IO  uint16_t  RESERVED1            :1;
            __IO  uint16_t  SCD0                 :1;
            __IO  uint16_t  SCD1                 :1;
            __IO  uint16_t  SED0                 :1;
            __IO  uint16_t  SED1                 :1;
            __IO  uint16_t  SST0                 :1;
            __IO  uint16_t  SST1                 :1;
        };
    };
} stc_mfs_scscr_field_t;

typedef struct stc_mfs_scsfr0_field
{
    union {
        struct {
            __IO   uint8_t  CS1L                 :5;
            __IO   uint8_t  CS1SPI               :1;
            __IO   uint8_t  CS1SCINV             :1;
            __IO   uint8_t  CS1CSLVL             :1;
        };
        struct {
            __IO   uint8_t  CS1L0                :1;
            __IO   uint8_t  CS1L1                :1;
            __IO   uint8_t  CS1L2                :1;
            __IO   uint8_t  CS1L3                :1;
            __IO   uint8_t  CS1L4                :1;
            __IO   uint8_t  RESERVED0            :3;
        };
    };
} stc_mfs_scsfr0_field_t;

typedef struct stc_mfs_scsfr1_field
{
    union {
        struct {
            __IO   uint8_t  CS2L                 :5;
            __IO   uint8_t  CS2SPI               :1;
            __IO   uint8_t  CS2SCINV             :1;
            __IO   uint8_t  CS2CSLVL             :1;
        };
        struct {
            __IO   uint8_t  CS2L0                :1;
            __IO   uint8_t  CS2L1                :1;
            __IO   uint8_t  CS2L2                :1;
            __IO   uint8_t  CS2L3                :1;
            __IO   uint8_t  CS2L4                :1;
            __IO   uint8_t  RESERVED0            :3;
        };
    };
} stc_mfs_scsfr1_field_t;

typedef struct stc_mfs_scsfr2_field
{
    union {
        struct {
            __IO   uint8_t  CS3L                 :5;
            __IO   uint8_t  CS3SPI               :1;
            __IO   uint8_t  CS3SCINV             :1;
            __IO   uint8_t  CS3CSLVL             :1;
        };
        struct {
            __IO   uint8_t  CS3L0                :1;
            __IO   uint8_t  CS3L1                :1;
            __IO   uint8_t  CS3L2                :1;
            __IO   uint8_t  CS3L3                :1;
            __IO   uint8_t  CS3L4                :1;
            __IO   uint8_t  RESERVED0            :3;
        };
    };
} stc_mfs_scsfr2_field_t;

typedef struct stc_mfs_csio_smr_field
{
    union {
        struct {
            __IO   uint8_t  SOE                  :1;
            __IO   uint8_t  SCKE                 :1;
            __IO   uint8_t  BDS                  :1;
            __IO   uint8_t  SCINV                :1;
            __IO   uint8_t  RESERVED0            :1;
            __IO   uint8_t  MD                   :3;
        };
        struct {
            __IO   uint8_t  RESERVED1            :5;
            __IO   uint8_t  MD0                  :1;
            __IO   uint8_t  MD1                  :1;
            __IO   uint8_t  MD2                  :1;
        };
    };
} stc_mfs_csio_smr_field_t;

typedef struct stc_mfs_i2c_smr_field
{
    union {
        struct {
            __IO   uint8_t  RESERVED2            :2;
            __IO   uint8_t  TIE                  :1;
            __IO   uint8_t  RIE                  :1;
            __IO   uint8_t  RESERVED3            :1;
            __IO   uint8_t  MD                   :3;
        };
        struct {
            __IO   uint8_t  RESERVED4            :5;
            __IO   uint8_t  MD0                  :1;
            __IO   uint8_t  MD1                  :1;
            __IO   uint8_t  MD2                  :1;
        };
    };
} stc_mfs_i2c_smr_field_t;

typedef struct stc_mfs_lin_smr_field
{
    union {
        struct {
            __IO   uint8_t  SOE                  :1;
            __IO   uint8_t  RESERVED5            :2;
            __IO   uint8_t  SBL                  :1;
            __IO   uint8_t  WUCR                 :1;
            __IO   uint8_t  MD                   :3;
        };
        struct {
            __IO   uint8_t  RESERVED6            :5;
            __IO   uint8_t  MD0                  :1;
            __IO   uint8_t  MD1                  :1;
            __IO   uint8_t  MD2                  :1;
        };
    };
} stc_mfs_lin_smr_field_t;

typedef struct stc_mfs_uart_smr_field
{
    union {
        struct {
            __IO   uint8_t  SOE                  :1;
            __IO   uint8_t  RESERVED7            :1;
            __IO   uint8_t  BDS                  :1;
            __IO   uint8_t  SBL                  :1;
            __IO   uint8_t  RESERVED8            :1;
            __IO   uint8_t  MD                   :3;
        };
        struct {
            __IO   uint8_t  RESERVED9            :5;
            __IO   uint8_t  MD0                  :1;
            __IO   uint8_t  MD1                  :1;
            __IO   uint8_t  MD2                  :1;
        };
    };
} stc_mfs_uart_smr_field_t;

typedef struct stc_mfs_csio_scr_field
{
        __IO   uint8_t  TXE                      :1;
        __IO   uint8_t  RXE                      :1;
        __IO   uint8_t  TBIE                     :1;
        __IO   uint8_t  TIE                      :1;
        __IO   uint8_t  RIE                      :1;
        __IO   uint8_t  SPI                      :1;
        __IO   uint8_t  MS                       :1;
        __IO   uint8_t  UPCL                     :1;
} stc_mfs_csio_scr_field_t;

typedef struct stc_mfs_i2c_ibcr_field
{
        __IO   uint8_t  INT                      :1;
        __IO   uint8_t  BER                      :1;
        __IO   uint8_t  INTE                     :1;
        __IO   uint8_t  CNDE                     :1;
        __IO   uint8_t  WSEL                     :1;
        __IO   uint8_t  ACKE                     :1;
        __IO   uint8_t  ACT_SCC                  :1;
        __IO   uint8_t  MSS                      :1;
} stc_mfs_i2c_ibcr_field_t;

typedef struct stc_mfs_lin_scr_field
{
        __IO   uint8_t  TXE                      :1;
        __IO   uint8_t  RXE                      :1;
        __IO   uint8_t  TBIE                     :1;
        __IO   uint8_t  TIE                      :1;
        __IO   uint8_t  RIE                      :1;
        __IO   uint8_t  LBR                      :1;
        __IO   uint8_t  MS                       :1;
        __IO   uint8_t  UPCL                     :1;
} stc_mfs_lin_scr_field_t;

typedef struct stc_mfs_uart_scr_field
{
        __IO   uint8_t  TXE                      :1;
        __IO   uint8_t  RXE                      :1;
        __IO   uint8_t  TBIE                     :1;
        __IO   uint8_t  TIE                      :1;
        __IO   uint8_t  RIE                      :1;
        __IO   uint8_t  RESERVED3                :2;
        __IO   uint8_t  UPCL                     :1;
} stc_mfs_uart_scr_field_t;

typedef struct stc_mfs_csio_escr_field
{
    union {
        struct {
            __IO   uint8_t  L                    :3;
            __IO   uint8_t  WT                   :2;
            __IO   uint8_t  CSFE                 :1;
            __IO   uint8_t  L3                   :1;
            __IO   uint8_t  SOP                  :1;
        };
        struct {
            __IO   uint8_t  L0                   :1;
            __IO   uint8_t  L1                   :1;
            __IO   uint8_t  L2                   :1;
            __IO   uint8_t  WT0                  :1;
            __IO   uint8_t  WT1                  :1;
            __IO   uint8_t  RESERVED0            :3;
        };
    };
} stc_mfs_csio_escr_field_t;

typedef struct stc_mfs_i2c_ibsr_field
{
        __IO   uint8_t  BB                       :1;
        __IO   uint8_t  SPC                      :1;
        __IO   uint8_t  RSC                      :1;
        __IO   uint8_t  AL                       :1;
        __IO   uint8_t  TRX                      :1;
        __IO   uint8_t  RSA                      :1;
        __IO   uint8_t  RACK                     :1;
        __IO   uint8_t  FBT                      :1;
} stc_mfs_i2c_ibsr_field_t;

typedef struct stc_mfs_lin_escr_field
{
    union {
        struct {
            __IO   uint8_t  DEL                  :2;
            __IO   uint8_t  LBL                  :2;
            __IO   uint8_t  LBIE                 :1;
            __IO   uint8_t  RESERVED2            :1;
            __IO   uint8_t  ESBL                 :1;
            __IO   uint8_t  RESERVED3            :1;
        };
        struct {
            __IO   uint8_t  DEL0                 :1;
            __IO   uint8_t  DEL1                 :1;
            __IO   uint8_t  LBL0                 :1;
            __IO   uint8_t  LBL1                 :1;
            __IO   uint8_t  RESERVED4            :4;
        };
    };
} stc_mfs_lin_escr_field_t;

typedef struct stc_mfs_uart_escr_field
{
    union {
        struct {
            __IO   uint8_t  L                    :3;
            __IO   uint8_t  P                    :1;
            __IO   uint8_t  PEN                  :1;
            __IO   uint8_t  INV                  :1;
            __IO   uint8_t  ESBL                 :1;
            __IO   uint8_t  FLWEN                :1;
        };
        struct {
            __IO   uint8_t  L0                   :1;
            __IO   uint8_t  L1                   :1;
            __IO   uint8_t  L2                   :1;
            __IO   uint8_t  RESERVED5            :5;
        };
    };
} stc_mfs_uart_escr_field_t;

typedef struct stc_mfs_csio_ssr_field
{
        __IO   uint8_t  TBI                      :1;
        __IO   uint8_t  TDRE                     :1;
        __IO   uint8_t  RDRF                     :1;
        __IO   uint8_t  ORE                      :1;
        __IO   uint8_t  AWC                      :1;
        __IO   uint8_t  RESERVED0                :2;
        __IO   uint8_t  REC                      :1;
} stc_mfs_csio_ssr_field_t;

typedef struct stc_mfs_i2c_ssr_field
{
        __IO   uint8_t  TBI                      :1;
        __IO   uint8_t  TDRE                     :1;
        __IO   uint8_t  RDRF                     :1;
        __IO   uint8_t  ORE                      :1;
        __IO   uint8_t  TBIE                     :1;
        __IO   uint8_t  DMA                      :1;
        __IO   uint8_t  TSET                     :1;
        __IO   uint8_t  REC                      :1;
} stc_mfs_i2c_ssr_field_t;

typedef struct stc_mfs_lin_ssr_field
{
        __IO   uint8_t  TBI                      :1;
        __IO   uint8_t  TDRE                     :1;
        __IO   uint8_t  RDRF                     :1;
        __IO   uint8_t  ORE                      :1;
        __IO   uint8_t  FRE                      :1;
        __IO   uint8_t  LBD                      :1;
        __IO   uint8_t  RESERVED3                :1;
        __IO   uint8_t  REC                      :1;
} stc_mfs_lin_ssr_field_t;

typedef struct stc_mfs_uart_ssr_field
{
        __IO   uint8_t  TBI                      :1;
        __IO   uint8_t  TDRE                     :1;
        __IO   uint8_t  RDRF                     :1;
        __IO   uint8_t  ORE                      :1;
        __IO   uint8_t  FRE                      :1;
        __IO   uint8_t  PE                       :1;
        __IO   uint8_t  RESERVED5                :1;
        __IO   uint8_t  REC                      :1;
} stc_mfs_uart_ssr_field_t;

typedef struct stc_mfs_csio_rdr_field
{
    union {
        struct {
            __IO  uint16_t  D                    :16;
        };
        struct {
            __IO  uint16_t  D0                   :1;
            __IO  uint16_t  D1                   :1;
            __IO  uint16_t  D2                   :1;
            __IO  uint16_t  D3                   :1;
            __IO  uint16_t  D4                   :1;
            __IO  uint16_t  D5                   :1;
            __IO  uint16_t  D6                   :1;
            __IO  uint16_t  D7                   :1;
            __IO  uint16_t  D8                   :1;
            __IO  uint16_t  D9                   :1;
            __IO  uint16_t  D10                  :1;
            __IO  uint16_t  D11                  :1;
            __IO  uint16_t  D12                  :1;
            __IO  uint16_t  D13                  :1;
            __IO  uint16_t  D14                  :1;
            __IO  uint16_t  D15                  :1;
        };
    };
} stc_mfs_csio_rdr_field_t;

typedef struct stc_mfs_csio_tdr_field
{
    union {
        struct {
            __IO  uint16_t  D                    :16;
        };
        struct {
            __IO  uint16_t  D0                   :1;
            __IO  uint16_t  D1                   :1;
            __IO  uint16_t  D2                   :1;
            __IO  uint16_t  D3                   :1;
            __IO  uint16_t  D4                   :1;
            __IO  uint16_t  D5                   :1;
            __IO  uint16_t  D6                   :1;
            __IO  uint16_t  D7                   :1;
            __IO  uint16_t  D8                   :1;
            __IO  uint16_t  D9                   :1;
            __IO  uint16_t  D10                  :1;
            __IO  uint16_t  D11                  :1;
            __IO  uint16_t  D12                  :1;
            __IO  uint16_t  D13                  :1;
            __IO  uint16_t  D14                  :1;
            __IO  uint16_t  D15                  :1;
        };
    };
} stc_mfs_csio_tdr_field_t;

typedef struct stc_mfs_i2c_rdr_field
{
    union {
        struct {
            __IO  uint16_t  D                    :8;
            __IO  uint16_t  RESERVED0            :8;
        };
        struct {
            __IO  uint16_t  D0                   :1;
            __IO  uint16_t  D1                   :1;
            __IO  uint16_t  D2                   :1;
            __IO  uint16_t  D3                   :1;
            __IO  uint16_t  D4                   :1;
            __IO  uint16_t  D5                   :1;
            __IO  uint16_t  D6                   :1;
            __IO  uint16_t  D7                   :1;
            __IO  uint16_t  RESERVED1            :8;
        };
    };
} stc_mfs_i2c_rdr_field_t;

typedef struct stc_mfs_i2c_tdr_field
{
    union {
        struct {
            __IO  uint16_t  D                    :8;
            __IO  uint16_t  RESERVED2            :8;
        };
        struct {
            __IO  uint16_t  D0                   :1;
            __IO  uint16_t  D1                   :1;
            __IO  uint16_t  D2                   :1;
            __IO  uint16_t  D3                   :1;
            __IO  uint16_t  D4                   :1;
            __IO  uint16_t  D5                   :1;
            __IO  uint16_t  D6                   :1;
            __IO  uint16_t  D7                   :1;
            __IO  uint16_t  RESERVED3            :8;
        };
    };
} stc_mfs_i2c_tdr_field_t;

typedef struct stc_mfs_lin_rdr_field
{
    union {
        struct {
            __IO  uint16_t  D                    :8;
            __IO  uint16_t  RESERVED4            :8;
        };
        struct {
            __IO  uint16_t  D0                   :1;
            __IO  uint16_t  D1                   :1;
            __IO  uint16_t  D2                   :1;
            __IO  uint16_t  D3                   :1;
            __IO  uint16_t  D4                   :1;
            __IO  uint16_t  D5                   :1;
            __IO  uint16_t  D6                   :1;
            __IO  uint16_t  D7                   :1;
            __IO  uint16_t  RESERVED5            :8;
        };
    };
} stc_mfs_lin_rdr_field_t;

typedef struct stc_mfs_lin_tdr_field
{
    union {
        struct {
            __IO  uint16_t  D                    :8;
            __IO  uint16_t  RESERVED6            :8;
        };
        struct {
            __IO  uint16_t  D0                   :1;
            __IO  uint16_t  D1                   :1;
            __IO  uint16_t  D2                   :1;
            __IO  uint16_t  D3                   :1;
            __IO  uint16_t  D4                   :1;
            __IO  uint16_t  D5                   :1;
            __IO  uint16_t  D6                   :1;
            __IO  uint16_t  D7                   :1;
            __IO  uint16_t  RESERVED7            :8;
        };
    };
} stc_mfs_lin_tdr_field_t;

typedef struct stc_mfs_uart_rdr_field
{
    union {
        struct {
            __IO  uint16_t  D                    :9;
            __IO  uint16_t  RESERVED8            :7;
        };
        struct {
            __IO  uint16_t  D0                   :1;
            __IO  uint16_t  D1                   :1;
            __IO  uint16_t  D2                   :1;
            __IO  uint16_t  D3                   :1;
            __IO  uint16_t  D4                   :1;
            __IO  uint16_t  D5                   :1;
            __IO  uint16_t  D6                   :1;
            __IO  uint16_t  D7                   :1;
            __IO  uint16_t  D8                   :1;
            __IO  uint16_t  RESERVED9            :7;
        };
    };
} stc_mfs_uart_rdr_field_t;

typedef struct stc_mfs_uart_tdr_field
{
    union {
        struct {
            __IO  uint16_t  D                    :9;
            __IO  uint16_t  RESERVED10           :7;
        };
        struct {
            __IO  uint16_t  D0                   :1;
            __IO  uint16_t  D1                   :1;
            __IO  uint16_t  D2                   :1;
            __IO  uint16_t  D3                   :1;
            __IO  uint16_t  D4                   :1;
            __IO  uint16_t  D5                   :1;
            __IO  uint16_t  D6                   :1;
            __IO  uint16_t  D7                   :1;
            __IO  uint16_t  D8                   :1;
            __IO  uint16_t  RESERVED11           :7;
        };
    };
} stc_mfs_uart_tdr_field_t;

typedef struct stc_mfs_csio_bgr_field
{
    union {
        struct {
            __IO  uint16_t  BGR                  :15;
            __IO  uint16_t  RESERVED0            :1;
        };
        struct {
            __IO  uint16_t  BGR0                 :1;
            __IO  uint16_t  BGR1                 :1;
            __IO  uint16_t  BGR2                 :1;
            __IO  uint16_t  BGR3                 :1;
            __IO  uint16_t  BGR4                 :1;
            __IO  uint16_t  BGR5                 :1;
            __IO  uint16_t  BGR6                 :1;
            __IO  uint16_t  BGR7                 :1;
            __IO  uint16_t  BGR8                 :1;
            __IO  uint16_t  BGR9                 :1;
            __IO  uint16_t  BGR10                :1;
            __IO  uint16_t  BGR11                :1;
            __IO  uint16_t  BGR12                :1;
            __IO  uint16_t  BGR13                :1;
            __IO  uint16_t  BGR14                :1;
            __IO  uint16_t  RESERVED1            :1;
        };
    };
} stc_mfs_csio_bgr_field_t;

typedef struct stc_mfs_i2c_bgr_field
{
    union {
        struct {
            __IO  uint16_t  BGR                  :15;
            __IO  uint16_t  RESERVED2            :1;
        };
        struct {
            __IO  uint16_t  BGR0                 :1;
            __IO  uint16_t  BGR1                 :1;
            __IO  uint16_t  BGR2                 :1;
            __IO  uint16_t  BGR3                 :1;
            __IO  uint16_t  BGR4                 :1;
            __IO  uint16_t  BGR5                 :1;
            __IO  uint16_t  BGR6                 :1;
            __IO  uint16_t  BGR7                 :1;
            __IO  uint16_t  BGR8                 :1;
            __IO  uint16_t  BGR9                 :1;
            __IO  uint16_t  BGR10                :1;
            __IO  uint16_t  BGR11                :1;
            __IO  uint16_t  BGR12                :1;
            __IO  uint16_t  BGR13                :1;
            __IO  uint16_t  BGR14                :1;
            __IO  uint16_t  RESERVED3            :1;
        };
    };
} stc_mfs_i2c_bgr_field_t;

typedef struct stc_mfs_lin_bgr_field
{
    union {
        struct {
            __IO  uint16_t  BGR                  :15;
            __IO  uint16_t  EXT                  :1;
        };
        struct {
            __IO  uint16_t  BGR0                 :1;
            __IO  uint16_t  BGR1                 :1;
            __IO  uint16_t  BGR2                 :1;
            __IO  uint16_t  BGR3                 :1;
            __IO  uint16_t  BGR4                 :1;
            __IO  uint16_t  BGR5                 :1;
            __IO  uint16_t  BGR6                 :1;
            __IO  uint16_t  BGR7                 :1;
            __IO  uint16_t  BGR8                 :1;
            __IO  uint16_t  BGR9                 :1;
            __IO  uint16_t  BGR10                :1;
            __IO  uint16_t  BGR11                :1;
            __IO  uint16_t  BGR12                :1;
            __IO  uint16_t  BGR13                :1;
            __IO  uint16_t  BGR14                :1;
            __IO  uint16_t  RESERVED4            :1;
        };
    };
} stc_mfs_lin_bgr_field_t;

typedef struct stc_mfs_uart_bgr_field
{
    union {
        struct {
            __IO  uint16_t  BGR                  :15;
            __IO  uint16_t  EXT                  :1;
        };
        struct {
            __IO  uint16_t  BGR0                 :1;
            __IO  uint16_t  BGR1                 :1;
            __IO  uint16_t  BGR2                 :1;
            __IO  uint16_t  BGR3                 :1;
            __IO  uint16_t  BGR4                 :1;
            __IO  uint16_t  BGR5                 :1;
            __IO  uint16_t  BGR6                 :1;
            __IO  uint16_t  BGR7                 :1;
            __IO  uint16_t  BGR8                 :1;
            __IO  uint16_t  BGR9                 :1;
            __IO  uint16_t  BGR10                :1;
            __IO  uint16_t  BGR11                :1;
            __IO  uint16_t  BGR12                :1;
            __IO  uint16_t  BGR13                :1;
            __IO  uint16_t  BGR14                :1;
            __IO  uint16_t  RESERVED5            :1;
        };
    };
} stc_mfs_uart_bgr_field_t;

typedef struct stc_mfs_i2c_isba_field
{
    union {
        struct {
            __IO   uint8_t  SA                   :7;
            __IO   uint8_t  SAEN                 :1;
        };
        struct {
            __IO   uint8_t  SA0                  :1;
            __IO   uint8_t  SA1                  :1;
            __IO   uint8_t  SA2                  :1;
            __IO   uint8_t  SA3                  :1;
            __IO   uint8_t  SA4                  :1;
            __IO   uint8_t  SA5                  :1;
            __IO   uint8_t  SA6                  :1;
            __IO   uint8_t  RESERVED0            :1;
        };
    };
} stc_mfs_i2c_isba_field_t;

typedef struct stc_mfs_i2c_ismk_field
{
    union {
        struct {
            __IO   uint8_t  SM                   :7;
            __IO   uint8_t  EN                   :1;
        };
        struct {
            __IO   uint8_t  SM0                  :1;
            __IO   uint8_t  SM1                  :1;
            __IO   uint8_t  SM2                  :1;
            __IO   uint8_t  SM3                  :1;
            __IO   uint8_t  SM4                  :1;
            __IO   uint8_t  SM5                  :1;
            __IO   uint8_t  SM6                  :1;
            __IO   uint8_t  RESERVED0            :1;
        };
    };
} stc_mfs_i2c_ismk_field_t;

typedef struct stc_mfs_csio_fcr_field
{
        __IO  uint16_t  FE1                      :1;
        __IO  uint16_t  FE2                      :1;
        __IO  uint16_t  FCL1                     :1;
        __IO  uint16_t  FCL2                     :1;
        __IO  uint16_t  FSET                     :1;
        __IO  uint16_t  FLD                      :1;
        __IO  uint16_t  FLST                     :1;
        __IO  uint16_t  RESERVED0                :1;
        __IO  uint16_t  FSEL                     :1;
        __IO  uint16_t  FTIE                     :1;
        __IO  uint16_t  FDRQ                     :1;
        __IO  uint16_t  FRIIE                    :1;
        __IO  uint16_t  FLSTE                    :1;
        __IO  uint16_t  RESERVED1                :3;
} stc_mfs_csio_fcr_field_t;

typedef struct stc_mfs_i2c_fcr_field
{
        __IO  uint16_t  FE1                      :1;
        __IO  uint16_t  FE2                      :1;
        __IO  uint16_t  FCL1                     :1;
        __IO  uint16_t  FCL2                     :1;
        __IO  uint16_t  FSET                     :1;
        __IO  uint16_t  FLD                      :1;
        __IO  uint16_t  FLST                     :1;
        __IO  uint16_t  RESERVED3                :1;
        __IO  uint16_t  FSEL                     :1;
        __IO  uint16_t  FTIE                     :1;
        __IO  uint16_t  FDRQ                     :1;
        __IO  uint16_t  FRIIE                    :1;
        __IO  uint16_t  FLSTE                    :1;
        __IO  uint16_t  RESERVED4                :3;
} stc_mfs_i2c_fcr_field_t;

typedef struct stc_mfs_lin_fcr_field
{
        __IO  uint16_t  FE1                      :1;
        __IO  uint16_t  FE2                      :1;
        __IO  uint16_t  FCL1                     :1;
        __IO  uint16_t  FCL2                     :1;
        __IO  uint16_t  FSET                     :1;
        __IO  uint16_t  FLD                      :1;
        __IO  uint16_t  FLST                     :1;
        __IO  uint16_t  RESERVED6                :1;
        __IO  uint16_t  FSEL                     :1;
        __IO  uint16_t  FTIE                     :1;
        __IO  uint16_t  FDRQ                     :1;
        __IO  uint16_t  FRIIE                    :1;
        __IO  uint16_t  FLSTE                    :1;
        __IO  uint16_t  RESERVED7                :3;
} stc_mfs_lin_fcr_field_t;

typedef struct stc_mfs_uart_fcr_field
{
        __IO  uint16_t  FE1                      :1;
        __IO  uint16_t  FE2                      :1;
        __IO  uint16_t  FCL1                     :1;
        __IO  uint16_t  FCL2                     :1;
        __IO  uint16_t  FSET                     :1;
        __IO  uint16_t  FLD                      :1;
        __IO  uint16_t  FLST                     :1;
        __IO  uint16_t  RESERVED9                :1;
        __IO  uint16_t  FSEL                     :1;
        __IO  uint16_t  FTIE                     :1;
        __IO  uint16_t  FDRQ                     :1;
        __IO  uint16_t  FRIIE                    :1;
        __IO  uint16_t  FLSTE                    :1;
        __IO  uint16_t  RESERVED10               :3;
} stc_mfs_uart_fcr_field_t;

typedef struct stc_mfs_csio_fbyte1_field
{
    union {
        struct {
            __IO   uint8_t  FD                   :8;
        };
        struct {
            __IO   uint8_t  FD0                  :1;
            __IO   uint8_t  FD1                  :1;
            __IO   uint8_t  FD2                  :1;
            __IO   uint8_t  FD3                  :1;
            __IO   uint8_t  FD4                  :1;
            __IO   uint8_t  FD5                  :1;
            __IO   uint8_t  FD6                  :1;
            __IO   uint8_t  FD7                  :1;
        };
    };
} stc_mfs_csio_fbyte1_field_t;

typedef struct stc_mfs_i2c_fbyte1_field
{
    union {
        struct {
            __IO   uint8_t  FD                   :8;
        };
        struct {
            __IO   uint8_t  FD0                  :1;
            __IO   uint8_t  FD1                  :1;
            __IO   uint8_t  FD2                  :1;
            __IO   uint8_t  FD3                  :1;
            __IO   uint8_t  FD4                  :1;
            __IO   uint8_t  FD5                  :1;
            __IO   uint8_t  FD6                  :1;
            __IO   uint8_t  FD7                  :1;
        };
    };
} stc_mfs_i2c_fbyte1_field_t;

typedef struct stc_mfs_lin_fbyte1_field
{
    union {
        struct {
            __IO   uint8_t  FD                   :8;
        };
        struct {
            __IO   uint8_t  FD0                  :1;
            __IO   uint8_t  FD1                  :1;
            __IO   uint8_t  FD2                  :1;
            __IO   uint8_t  FD3                  :1;
            __IO   uint8_t  FD4                  :1;
            __IO   uint8_t  FD5                  :1;
            __IO   uint8_t  FD6                  :1;
            __IO   uint8_t  FD7                  :1;
        };
    };
} stc_mfs_lin_fbyte1_field_t;

typedef struct stc_mfs_uart_fbyte1_field
{
    union {
        struct {
            __IO   uint8_t  FD                   :8;
        };
        struct {
            __IO   uint8_t  FD0                  :1;
            __IO   uint8_t  FD1                  :1;
            __IO   uint8_t  FD2                  :1;
            __IO   uint8_t  FD3                  :1;
            __IO   uint8_t  FD4                  :1;
            __IO   uint8_t  FD5                  :1;
            __IO   uint8_t  FD6                  :1;
            __IO   uint8_t  FD7                  :1;
        };
    };
} stc_mfs_uart_fbyte1_field_t;

typedef struct stc_mfs_csio_fbyte2_field
{
    union {
        struct {
            __IO   uint8_t  FD                   :8;
        };
        struct {
            __IO   uint8_t  FD0                  :1;
            __IO   uint8_t  FD1                  :1;
            __IO   uint8_t  FD2                  :1;
            __IO   uint8_t  FD3                  :1;
            __IO   uint8_t  FD4                  :1;
            __IO   uint8_t  FD5                  :1;
            __IO   uint8_t  FD6                  :1;
            __IO   uint8_t  FD7                  :1;
        };
    };
} stc_mfs_csio_fbyte2_field_t;

typedef struct stc_mfs_i2c_fbyte2_field
{
    union {
        struct {
            __IO   uint8_t  FD                   :8;
        };
        struct {
            __IO   uint8_t  FD0                  :1;
            __IO   uint8_t  FD1                  :1;
            __IO   uint8_t  FD2                  :1;
            __IO   uint8_t  FD3                  :1;
            __IO   uint8_t  FD4                  :1;
            __IO   uint8_t  FD5                  :1;
            __IO   uint8_t  FD6                  :1;
            __IO   uint8_t  FD7                  :1;
        };
    };
} stc_mfs_i2c_fbyte2_field_t;

typedef struct stc_mfs_lin_fbyte2_field
{
    union {
        struct {
            __IO   uint8_t  FD                   :8;
        };
        struct {
            __IO   uint8_t  FD0                  :1;
            __IO   uint8_t  FD1                  :1;
            __IO   uint8_t  FD2                  :1;
            __IO   uint8_t  FD3                  :1;
            __IO   uint8_t  FD4                  :1;
            __IO   uint8_t  FD5                  :1;
            __IO   uint8_t  FD6                  :1;
            __IO   uint8_t  FD7                  :1;
        };
    };
} stc_mfs_lin_fbyte2_field_t;

typedef struct stc_mfs_uart_fbyte2_field
{
    union {
        struct {
            __IO   uint8_t  FD                   :8;
        };
        struct {
            __IO   uint8_t  FD0                  :1;
            __IO   uint8_t  FD1                  :1;
            __IO   uint8_t  FD2                  :1;
            __IO   uint8_t  FD3                  :1;
            __IO   uint8_t  FD4                  :1;
            __IO   uint8_t  FD5                  :1;
            __IO   uint8_t  FD6                  :1;
            __IO   uint8_t  FD7                  :1;
        };
    };
} stc_mfs_uart_fbyte2_field_t;

typedef struct stc_mfs_csio_scstr0_field
{
    union {
        struct {
            __IO   uint8_t  CSHD                 :8;
        };
        struct {
            __IO   uint8_t  CSHD0                :1;
            __IO   uint8_t  CSHD1                :1;
            __IO   uint8_t  CSHD2                :1;
            __IO   uint8_t  CSHD3                :1;
            __IO   uint8_t  CSHD4                :1;
            __IO   uint8_t  CSHD5                :1;
            __IO   uint8_t  CSHD6                :1;
            __IO   uint8_t  CSHD7                :1;
        };
    };
} stc_mfs_csio_scstr0_field_t;

typedef struct stc_mfs_i2c_nfcr_field
{
    union {
        struct {
            __IO   uint8_t  NFT                  :5;
            __IO   uint8_t  RESERVED0            :3;
        };
        struct {
            __IO   uint8_t  NFT0                 :1;
            __IO   uint8_t  NFT1                 :1;
            __IO   uint8_t  NFT2                 :1;
            __IO   uint8_t  NFT3                 :1;
            __IO   uint8_t  NFT4                 :1;
            __IO   uint8_t  RESERVED1            :3;
        };
    };
} stc_mfs_i2c_nfcr_field_t;

typedef struct stc_mfs_csio_scstr1_field
{
    union {
        struct {
            __IO   uint8_t  CSSU                 :8;
        };
        struct {
            __IO   uint8_t  CSSU0                :1;
            __IO   uint8_t  CSSU1                :1;
            __IO   uint8_t  CSSU2                :1;
            __IO   uint8_t  CSSU3                :1;
            __IO   uint8_t  CSSU4                :1;
            __IO   uint8_t  CSSU5                :1;
            __IO   uint8_t  CSSU6                :1;
            __IO   uint8_t  CSSU7                :1;
        };
    };
} stc_mfs_csio_scstr1_field_t;

typedef struct stc_mfs_i2c_eibcr_field
{
        __IO   uint8_t  BEC                      :1;
        __IO   uint8_t  SOCE                     :1;
        __IO   uint8_t  SCLC                     :1;
        __IO   uint8_t  SDAC                     :1;
        __IO   uint8_t  SCLS                     :1;
        __IO   uint8_t  SDAS                     :1;
        __IO   uint8_t  RESERVED0                :2;
} stc_mfs_i2c_eibcr_field_t;

typedef struct stc_mfs_csio_scstr32_field
{
    union {
        struct {
            __IO  uint16_t  CSDS                 :16;
        };
        struct {
            __IO  uint16_t  CSDS0                :1;
            __IO  uint16_t  CSDS1                :1;
            __IO  uint16_t  CSDS2                :1;
            __IO  uint16_t  CSDS3                :1;
            __IO  uint16_t  CSDS4                :1;
            __IO  uint16_t  CSDS5                :1;
            __IO  uint16_t  CSDS6                :1;
            __IO  uint16_t  CSDS7                :1;
            __IO  uint16_t  CSDS8                :1;
            __IO  uint16_t  CSDS9                :1;
            __IO  uint16_t  CSDS10               :1;
            __IO  uint16_t  CSDS11               :1;
            __IO  uint16_t  CSDS12               :1;
            __IO  uint16_t  CSDS13               :1;
            __IO  uint16_t  CSDS14               :1;
            __IO  uint16_t  CSDS15               :1;
        };
    };
} stc_mfs_csio_scstr32_field_t;

typedef struct stc_mfs_csio_sacsr_field
{
    union {
        struct {
            __IO  uint16_t  TMRE                 :1;
            __IO  uint16_t  TDIV                 :4;
            __IO  uint16_t  RESERVED1            :1;
            __IO  uint16_t  TSYNE                :1;
            __IO  uint16_t  TINTE                :1;
            __IO  uint16_t  TINT                 :1;
            __IO  uint16_t  RESERVED2            :2;
            __IO  uint16_t  CSE                  :1;
            __IO  uint16_t  CSEIE                :1;
            __IO  uint16_t  TBEEN                :1;
            __IO  uint16_t  RESERVED3            :2;
        };
        struct {
            __IO  uint16_t  RESERVED0            :1;
            __IO  uint16_t  TDIV0                :1;
            __IO  uint16_t  TDIV1                :1;
            __IO  uint16_t  TDIV2                :1;
            __IO  uint16_t  TDIV3                :1;
            __IO  uint16_t  RESERVED4            :11;
        };
    };
} stc_mfs_csio_sacsr_field_t;

typedef struct stc_mfs_csio_stmr_field
{
    union {
        struct {
            __IO  uint16_t  TM                   :16;
        };
        struct {
            __IO  uint16_t  TM0                  :1;
            __IO  uint16_t  TM1                  :1;
            __IO  uint16_t  TM2                  :1;
            __IO  uint16_t  TM3                  :1;
            __IO  uint16_t  TM4                  :1;
            __IO  uint16_t  TM5                  :1;
            __IO  uint16_t  TM6                  :1;
            __IO  uint16_t  TM7                  :1;
            __IO  uint16_t  TM8                  :1;
            __IO  uint16_t  TM9                  :1;
            __IO  uint16_t  TM10                 :1;
            __IO  uint16_t  TM11                 :1;
            __IO  uint16_t  TM12                 :1;
            __IO  uint16_t  TM13                 :1;
            __IO  uint16_t  TM14                 :1;
            __IO  uint16_t  TM15                 :1;
        };
    };
} stc_mfs_csio_stmr_field_t;

typedef struct stc_mfs_csio_stmcr_field
{
    union {
        struct {
            __IO  uint16_t  TC                   :16;
        };
        struct {
            __IO  uint16_t  TC0                  :1;
            __IO  uint16_t  TC1                  :1;
            __IO  uint16_t  TC2                  :1;
            __IO  uint16_t  TC3                  :1;
            __IO  uint16_t  TC4                  :1;
            __IO  uint16_t  TC5                  :1;
            __IO  uint16_t  TC6                  :1;
            __IO  uint16_t  TC7                  :1;
            __IO  uint16_t  TC8                  :1;
            __IO  uint16_t  TC9                  :1;
            __IO  uint16_t  TC10                 :1;
            __IO  uint16_t  TC11                 :1;
            __IO  uint16_t  TC12                 :1;
            __IO  uint16_t  TC13                 :1;
            __IO  uint16_t  TC14                 :1;
            __IO  uint16_t  TC15                 :1;
        };
    };
} stc_mfs_csio_stmcr_field_t;

typedef struct stc_mfs_csio_scscr_field
{
    union {
        struct {
            __IO  uint16_t  CSOE                 :1;
            __IO  uint16_t  CSEN0                :1;
            __IO  uint16_t  CSEN1                :1;
            __IO  uint16_t  CSEN2                :1;
            __IO  uint16_t  CSEN3                :1;
            __IO  uint16_t  CSLVL                :1;
            __IO  uint16_t  CDIV                 :3;
            __IO  uint16_t  SCAM                 :1;
            __IO  uint16_t  SCD                  :2;
            __IO  uint16_t  SED                  :2;
            __IO  uint16_t  SST                  :2;
        };
        struct {
            __IO  uint16_t  RESERVED0            :6;
            __IO  uint16_t  CDIV0                :1;
            __IO  uint16_t  CDIV1                :1;
            __IO  uint16_t  CDIV2                :1;
            __IO  uint16_t  RESERVED1            :1;
            __IO  uint16_t  SCD0                 :1;
            __IO  uint16_t  SCD1                 :1;
            __IO  uint16_t  SED0                 :1;
            __IO  uint16_t  SED1                 :1;
            __IO  uint16_t  SST0                 :1;
            __IO  uint16_t  SST1                 :1;
        };
    };
} stc_mfs_csio_scscr_field_t;

typedef struct stc_mfs_csio_scsfr0_field
{
    union {
        struct {
            __IO   uint8_t  CS1L                 :5;
            __IO   uint8_t  CS1SPI               :1;
            __IO   uint8_t  CS1SCINV             :1;
            __IO   uint8_t  CS1CSLVL             :1;
        };
        struct {
            __IO   uint8_t  CS1L0                :1;
            __IO   uint8_t  CS1L1                :1;
            __IO   uint8_t  CS1L2                :1;
            __IO   uint8_t  CS1L3                :1;
            __IO   uint8_t  CS1L4                :1;
            __IO   uint8_t  RESERVED0            :3;
        };
    };
} stc_mfs_csio_scsfr0_field_t;

typedef struct stc_mfs_csio_scsfr1_field
{
    union {
        struct {
            __IO   uint8_t  CS2L                 :5;
            __IO   uint8_t  CS2SPI               :1;
            __IO   uint8_t  CS2SCINV             :1;
            __IO   uint8_t  CS2CSLVL             :1;
        };
        struct {
            __IO   uint8_t  CS2L0                :1;
            __IO   uint8_t  CS2L1                :1;
            __IO   uint8_t  CS2L2                :1;
            __IO   uint8_t  CS2L3                :1;
            __IO   uint8_t  CS2L4                :1;
            __IO   uint8_t  RESERVED0            :3;
        };
    };
} stc_mfs_csio_scsfr1_field_t;

typedef struct stc_mfs_csio_scsfr2_field
{
    union {
        struct {
            __IO   uint8_t  CS3L                 :5;
            __IO   uint8_t  CS3SPI               :1;
            __IO   uint8_t  CS3SCINV             :1;
            __IO   uint8_t  CS3CSLVL             :1;
        };
        struct {
            __IO   uint8_t  CS3L0                :1;
            __IO   uint8_t  CS3L1                :1;
            __IO   uint8_t  CS3L2                :1;
            __IO   uint8_t  CS3L3                :1;
            __IO   uint8_t  CS3L4                :1;
            __IO   uint8_t  RESERVED0            :3;
        };
    };
} stc_mfs_csio_scsfr2_field_t;

/*******************************************************************************
* MFT_MODULE
*******************************************************************************/
typedef struct stc_mft_ocsa10_field
{
        __IO   uint8_t  CST0                     :1;
        __IO   uint8_t  CST1                     :1;
        __IO   uint8_t  RESERVED0                :2;
        __IO   uint8_t  IOE0                     :1;
        __IO   uint8_t  IOE1                     :1;
        __IO   uint8_t  IOP0                     :1;
        __IO   uint8_t  IOP1                     :1;
} stc_mft_ocsa10_field_t;

typedef struct stc_mft_ocsb10_field
{
        __IO   uint8_t  OTD0                     :1;
        __IO   uint8_t  OTD1                     :1;
        __IO   uint8_t  RESERVED0                :2;
        __IO   uint8_t  CMOD                     :1;
        __IO   uint8_t  RESERVED1                :2;
        __IO   uint8_t  FM4                      :1;
} stc_mft_ocsb10_field_t;

typedef struct stc_mft_ocsd10_field
{
    union {
        struct {
            __IO  uint16_t  OCCP0BUFE            :2;
            __IO  uint16_t  OCCP1BUFE            :2;
            __IO  uint16_t  OCSE0BUFE            :2;
            __IO  uint16_t  OCSE1BUFE            :2;
            __IO  uint16_t  OPBM0                :1;
            __IO  uint16_t  OPBM1                :1;
            __IO  uint16_t  OEBM0                :1;
            __IO  uint16_t  OEBM1                :1;
            __IO  uint16_t  OFEX0                :1;
            __IO  uint16_t  OFEX1                :1;
            __IO  uint16_t  RESERVED0            :2;
        };
        struct {
            __IO  uint16_t  OCCP0BUFE0           :1;
            __IO  uint16_t  OCCP0BUFE1           :1;
            __IO  uint16_t  OCCP1BUFE0           :1;
            __IO  uint16_t  OCCP1BUFE1           :1;
            __IO  uint16_t  OCSE0BUFE0           :1;
            __IO  uint16_t  OCSE0BUFE1           :1;
            __IO  uint16_t  OCSE1BUFE0           :1;
            __IO  uint16_t  OCSE1BUFE1           :1;
            __IO  uint16_t  RESERVED1            :8;
        };
    };
} stc_mft_ocsd10_field_t;

typedef struct stc_mft_ocsa32_field
{
        __IO   uint8_t  CST2                     :1;
        __IO   uint8_t  CST3                     :1;
        __IO   uint8_t  RESERVED0                :2;
        __IO   uint8_t  IOE2                     :1;
        __IO   uint8_t  IOE3                     :1;
        __IO   uint8_t  IOP2                     :1;
        __IO   uint8_t  IOP3                     :1;
} stc_mft_ocsa32_field_t;

typedef struct stc_mft_ocsb32_field
{
        __IO   uint8_t  OTD2                     :1;
        __IO   uint8_t  OTD3                     :1;
        __IO   uint8_t  RESERVED0                :2;
        __IO   uint8_t  CMOD                     :1;
        __IO   uint8_t  RESERVED1                :2;
        __IO   uint8_t  FM4                      :1;
} stc_mft_ocsb32_field_t;

typedef struct stc_mft_ocsd32_field
{
    union {
        struct {
            __IO  uint16_t  OCCP2BUFE            :2;
            __IO  uint16_t  OCCP3BUFE            :2;
            __IO  uint16_t  OCSE2BUFE            :2;
            __IO  uint16_t  OCSE3BUFE            :2;
            __IO  uint16_t  OPBM2                :1;
            __IO  uint16_t  OPBM3                :1;
            __IO  uint16_t  OEBM2                :1;
            __IO  uint16_t  OEBM3                :1;
            __IO  uint16_t  OFEX2                :1;
            __IO  uint16_t  OFEX3                :1;
            __IO  uint16_t  RESERVED0            :2;
        };
        struct {
            __IO  uint16_t  OCCP2BUFE0           :1;
            __IO  uint16_t  OCCP2BUFE1           :1;
            __IO  uint16_t  OCCP3BUFE0           :1;
            __IO  uint16_t  OCCP3BUFE1           :1;
            __IO  uint16_t  OCSE2BUFE0           :1;
            __IO  uint16_t  OCSE2BUFE1           :1;
            __IO  uint16_t  OCSE3BUFE0           :1;
            __IO  uint16_t  OCSE3BUFE1           :1;
            __IO  uint16_t  RESERVED1            :8;
        };
    };
} stc_mft_ocsd32_field_t;

typedef struct stc_mft_ocsa54_field
{
        __IO   uint8_t  CST4                     :1;
        __IO   uint8_t  CST5                     :1;
        __IO   uint8_t  RESERVED0                :2;
        __IO   uint8_t  IOE4                     :1;
        __IO   uint8_t  IOE5                     :1;
        __IO   uint8_t  IOP4                     :1;
        __IO   uint8_t  IOP5                     :1;
} stc_mft_ocsa54_field_t;

typedef struct stc_mft_ocsb54_field
{
        __IO   uint8_t  OTD4                     :1;
        __IO   uint8_t  OTD5                     :1;
        __IO   uint8_t  RESERVED0                :2;
        __IO   uint8_t  CMOD                     :1;
        __IO   uint8_t  RESERVED1                :2;
        __IO   uint8_t  FM4                      :1;
} stc_mft_ocsb54_field_t;

typedef struct stc_mft_ocsd54_field
{
    union {
        struct {
            __IO  uint16_t  OCCP4BUFE            :2;
            __IO  uint16_t  OCCP5BUFE            :2;
            __IO  uint16_t  OCSE4BUFE            :2;
            __IO  uint16_t  OCSE5BUFE            :2;
            __IO  uint16_t  OPBM4                :1;
            __IO  uint16_t  OPBM5                :1;
            __IO  uint16_t  OEBM4                :1;
            __IO  uint16_t  OEBM5                :1;
            __IO  uint16_t  OFEX4                :1;
            __IO  uint16_t  OFEX5                :1;
            __IO  uint16_t  RESERVED0            :2;
        };
        struct {
            __IO  uint16_t  OCCP4BUFE0           :1;
            __IO  uint16_t  OCCP4BUFE1           :1;
            __IO  uint16_t  OCCP5BUFE0           :1;
            __IO  uint16_t  OCCP5BUFE1           :1;
            __IO  uint16_t  OCSE4BUFE0           :1;
            __IO  uint16_t  OCSE4BUFE1           :1;
            __IO  uint16_t  OCSE5BUFE0           :1;
            __IO  uint16_t  OCSE5BUFE1           :1;
            __IO  uint16_t  RESERVED1            :8;
        };
    };
} stc_mft_ocsd54_field_t;

typedef struct stc_mft_ocsc_field
{
        __IO   uint8_t  MOD0                     :1;
        __IO   uint8_t  MOD1                     :1;
        __IO   uint8_t  MOD2                     :1;
        __IO   uint8_t  MOD3                     :1;
        __IO   uint8_t  MOD4                     :1;
        __IO   uint8_t  MOD5                     :1;
        __IO   uint8_t  RESERVED0                :2;
} stc_mft_ocsc_field_t;

typedef struct stc_mft_ocse0_field
{
    union {
        struct {
            __IO  uint16_t  OCSE                 :16;
        };
        struct {
            __IO  uint16_t  OCSE0                :1;
            __IO  uint16_t  OCSE1                :1;
            __IO  uint16_t  OCSE2                :1;
            __IO  uint16_t  OCSE3                :1;
            __IO  uint16_t  OCSE4                :1;
            __IO  uint16_t  OCSE5                :1;
            __IO  uint16_t  OCSE6                :1;
            __IO  uint16_t  OCSE7                :1;
            __IO  uint16_t  OCSE8                :1;
            __IO  uint16_t  OCSE9                :1;
            __IO  uint16_t  OCSE10               :1;
            __IO  uint16_t  OCSE11               :1;
            __IO  uint16_t  OCSE12               :1;
            __IO  uint16_t  OCSE13               :1;
            __IO  uint16_t  OCSE14               :1;
            __IO  uint16_t  OCSE15               :1;
        };
    };
} stc_mft_ocse0_field_t;

typedef struct stc_mft_ocse1_field
{
    union {
        struct {
            __IO  uint32_t  OCSE                 :32;
        };
        struct {
            __IO  uint32_t  OCSE0                :1;
            __IO  uint32_t  OCSE1                :1;
            __IO  uint32_t  OCSE2                :1;
            __IO  uint32_t  OCSE3                :1;
            __IO  uint32_t  OCSE4                :1;
            __IO  uint32_t  OCSE5                :1;
            __IO  uint32_t  OCSE6                :1;
            __IO  uint32_t  OCSE7                :1;
            __IO  uint32_t  OCSE8                :1;
            __IO  uint32_t  OCSE9                :1;
            __IO  uint32_t  OCSE10               :1;
            __IO  uint32_t  OCSE11               :1;
            __IO  uint32_t  OCSE12               :1;
            __IO  uint32_t  OCSE13               :1;
            __IO  uint32_t  OCSE14               :1;
            __IO  uint32_t  OCSE15               :1;
            __IO  uint32_t  OCSE16               :1;
            __IO  uint32_t  OCSE17               :1;
            __IO  uint32_t  OCSE18               :1;
            __IO  uint32_t  OCSE19               :1;
            __IO  uint32_t  OCSE20               :1;
            __IO  uint32_t  OCSE21               :1;
            __IO  uint32_t  OCSE22               :1;
            __IO  uint32_t  OCSE23               :1;
            __IO  uint32_t  OCSE24               :1;
            __IO  uint32_t  OCSE25               :1;
            __IO  uint32_t  OCSE26               :1;
            __IO  uint32_t  OCSE27               :1;
            __IO  uint32_t  OCSE28               :1;
            __IO  uint32_t  OCSE29               :1;
            __IO  uint32_t  OCSE30               :1;
            __IO  uint32_t  OCSE31               :1;
        };
    };
} stc_mft_ocse1_field_t;

typedef struct stc_mft_ocse2_field
{
    union {
        struct {
            __IO  uint16_t  OCSE                 :16;
        };
        struct {
            __IO  uint16_t  OCSE0                :1;
            __IO  uint16_t  OCSE1                :1;
            __IO  uint16_t  OCSE2                :1;
            __IO  uint16_t  OCSE3                :1;
            __IO  uint16_t  OCSE4                :1;
            __IO  uint16_t  OCSE5                :1;
            __IO  uint16_t  OCSE6                :1;
            __IO  uint16_t  OCSE7                :1;
            __IO  uint16_t  OCSE8                :1;
            __IO  uint16_t  OCSE9                :1;
            __IO  uint16_t  OCSE10               :1;
            __IO  uint16_t  OCSE11               :1;
            __IO  uint16_t  OCSE12               :1;
            __IO  uint16_t  OCSE13               :1;
            __IO  uint16_t  OCSE14               :1;
            __IO  uint16_t  OCSE15               :1;
        };
    };
} stc_mft_ocse2_field_t;

typedef struct stc_mft_ocse3_field
{
    union {
        struct {
            __IO  uint32_t  OCSE                 :32;
        };
        struct {
            __IO  uint32_t  OCSE0                :1;
            __IO  uint32_t  OCSE1                :1;
            __IO  uint32_t  OCSE2                :1;
            __IO  uint32_t  OCSE3                :1;
            __IO  uint32_t  OCSE4                :1;
            __IO  uint32_t  OCSE5                :1;
            __IO  uint32_t  OCSE6                :1;
            __IO  uint32_t  OCSE7                :1;
            __IO  uint32_t  OCSE8                :1;
            __IO  uint32_t  OCSE9                :1;
            __IO  uint32_t  OCSE10               :1;
            __IO  uint32_t  OCSE11               :1;
            __IO  uint32_t  OCSE12               :1;
            __IO  uint32_t  OCSE13               :1;
            __IO  uint32_t  OCSE14               :1;
            __IO  uint32_t  OCSE15               :1;
            __IO  uint32_t  OCSE16               :1;
            __IO  uint32_t  OCSE17               :1;
            __IO  uint32_t  OCSE18               :1;
            __IO  uint32_t  OCSE19               :1;
            __IO  uint32_t  OCSE20               :1;
            __IO  uint32_t  OCSE21               :1;
            __IO  uint32_t  OCSE22               :1;
            __IO  uint32_t  OCSE23               :1;
            __IO  uint32_t  OCSE24               :1;
            __IO  uint32_t  OCSE25               :1;
            __IO  uint32_t  OCSE26               :1;
            __IO  uint32_t  OCSE27               :1;
            __IO  uint32_t  OCSE28               :1;
            __IO  uint32_t  OCSE29               :1;
            __IO  uint32_t  OCSE30               :1;
            __IO  uint32_t  OCSE31               :1;
        };
    };
} stc_mft_ocse3_field_t;

typedef struct stc_mft_ocse4_field
{
    union {
        struct {
            __IO  uint16_t  OCSE                 :16;
        };
        struct {
            __IO  uint16_t  OCSE0                :1;
            __IO  uint16_t  OCSE1                :1;
            __IO  uint16_t  OCSE2                :1;
            __IO  uint16_t  OCSE3                :1;
            __IO  uint16_t  OCSE4                :1;
            __IO  uint16_t  OCSE5                :1;
            __IO  uint16_t  OCSE6                :1;
            __IO  uint16_t  OCSE7                :1;
            __IO  uint16_t  OCSE8                :1;
            __IO  uint16_t  OCSE9                :1;
            __IO  uint16_t  OCSE10               :1;
            __IO  uint16_t  OCSE11               :1;
            __IO  uint16_t  OCSE12               :1;
            __IO  uint16_t  OCSE13               :1;
            __IO  uint16_t  OCSE14               :1;
            __IO  uint16_t  OCSE15               :1;
        };
    };
} stc_mft_ocse4_field_t;

typedef struct stc_mft_ocse5_field
{
    union {
        struct {
            __IO  uint32_t  OCSE                 :32;
        };
        struct {
            __IO  uint32_t  OCSE0                :1;
            __IO  uint32_t  OCSE1                :1;
            __IO  uint32_t  OCSE2                :1;
            __IO  uint32_t  OCSE3                :1;
            __IO  uint32_t  OCSE4                :1;
            __IO  uint32_t  OCSE5                :1;
            __IO  uint32_t  OCSE6                :1;
            __IO  uint32_t  OCSE7                :1;
            __IO  uint32_t  OCSE8                :1;
            __IO  uint32_t  OCSE9                :1;
            __IO  uint32_t  OCSE10               :1;
            __IO  uint32_t  OCSE11               :1;
            __IO  uint32_t  OCSE12               :1;
            __IO  uint32_t  OCSE13               :1;
            __IO  uint32_t  OCSE14               :1;
            __IO  uint32_t  OCSE15               :1;
            __IO  uint32_t  OCSE16               :1;
            __IO  uint32_t  OCSE17               :1;
            __IO  uint32_t  OCSE18               :1;
            __IO  uint32_t  OCSE19               :1;
            __IO  uint32_t  OCSE20               :1;
            __IO  uint32_t  OCSE21               :1;
            __IO  uint32_t  OCSE22               :1;
            __IO  uint32_t  OCSE23               :1;
            __IO  uint32_t  OCSE24               :1;
            __IO  uint32_t  OCSE25               :1;
            __IO  uint32_t  OCSE26               :1;
            __IO  uint32_t  OCSE27               :1;
            __IO  uint32_t  OCSE28               :1;
            __IO  uint32_t  OCSE29               :1;
            __IO  uint32_t  OCSE30               :1;
            __IO  uint32_t  OCSE31               :1;
        };
    };
} stc_mft_ocse5_field_t;

typedef struct stc_mft_tccp0_field
{
    union {
        struct {
            __IO  uint16_t  TCCP                 :16;
        };
        struct {
            __IO  uint16_t  TCCP0                :1;
            __IO  uint16_t  TCCP1                :1;
            __IO  uint16_t  TCCP2                :1;
            __IO  uint16_t  TCCP3                :1;
            __IO  uint16_t  TCCP4                :1;
            __IO  uint16_t  TCCP5                :1;
            __IO  uint16_t  TCCP6                :1;
            __IO  uint16_t  TCCP7                :1;
            __IO  uint16_t  TCCP8                :1;
            __IO  uint16_t  TCCP9                :1;
            __IO  uint16_t  TCCP10               :1;
            __IO  uint16_t  TCCP11               :1;
            __IO  uint16_t  TCCP12               :1;
            __IO  uint16_t  TCCP13               :1;
            __IO  uint16_t  TCCP14               :1;
            __IO  uint16_t  TCCP15               :1;
        };
    };
} stc_mft_tccp0_field_t;

typedef struct stc_mft_tcsa0_field
{
    union {
        struct {
            __IO  uint16_t  CLK                  :4;
            __IO  uint16_t  SCLR                 :1;
            __IO  uint16_t  MODE                 :1;
            __IO  uint16_t  STOP                 :1;
            __IO  uint16_t  BFE                  :1;
            __IO  uint16_t  ICRE                 :1;
            __IO  uint16_t  ICLR                 :1;
            __IO  uint16_t  RESERVED0            :3;
            __IO  uint16_t  IRQZE                :1;
            __IO  uint16_t  IRQZF                :1;
            __IO  uint16_t  ECKE                 :1;
        };
        struct {
            __IO  uint16_t  CLK0                 :1;
            __IO  uint16_t  CLK1                 :1;
            __IO  uint16_t  CLK2                 :1;
            __IO  uint16_t  CLK3                 :1;
            __IO  uint16_t  RESERVED1            :12;
        };
    };
} stc_mft_tcsa0_field_t;

typedef struct stc_mft_tcsc0_field
{
    union {
        struct {
            __IO  uint16_t  MSZI                 :4;
            __IO  uint16_t  MSPI                 :4;
            __IO  uint16_t  MSZC                 :4;
            __IO  uint16_t  MSPC                 :4;
        };
        struct {
            __IO  uint16_t  MSZI0                :1;
            __IO  uint16_t  MSZI1                :1;
            __IO  uint16_t  MSZI2                :1;
            __IO  uint16_t  MSZI3                :1;
            __IO  uint16_t  MSPI0                :1;
            __IO  uint16_t  MSPI1                :1;
            __IO  uint16_t  MSPI2                :1;
            __IO  uint16_t  MSPI3                :1;
            __IO  uint16_t  MSZC0                :1;
            __IO  uint16_t  MSZC1                :1;
            __IO  uint16_t  MSZC2                :1;
            __IO  uint16_t  MSZC3                :1;
            __IO  uint16_t  MSPC0                :1;
            __IO  uint16_t  MSPC1                :1;
            __IO  uint16_t  MSPC2                :1;
            __IO  uint16_t  MSPC3                :1;
        };
    };
} stc_mft_tcsc0_field_t;

typedef struct stc_mft_tccp1_field
{
    union {
        struct {
            __IO  uint16_t  TCCP                 :16;
        };
        struct {
            __IO  uint16_t  TCCP0                :1;
            __IO  uint16_t  TCCP1                :1;
            __IO  uint16_t  TCCP2                :1;
            __IO  uint16_t  TCCP3                :1;
            __IO  uint16_t  TCCP4                :1;
            __IO  uint16_t  TCCP5                :1;
            __IO  uint16_t  TCCP6                :1;
            __IO  uint16_t  TCCP7                :1;
            __IO  uint16_t  TCCP8                :1;
            __IO  uint16_t  TCCP9                :1;
            __IO  uint16_t  TCCP10               :1;
            __IO  uint16_t  TCCP11               :1;
            __IO  uint16_t  TCCP12               :1;
            __IO  uint16_t  TCCP13               :1;
            __IO  uint16_t  TCCP14               :1;
            __IO  uint16_t  TCCP15               :1;
        };
    };
} stc_mft_tccp1_field_t;

typedef struct stc_mft_tcsa1_field
{
    union {
        struct {
            __IO  uint16_t  CLK                  :4;
            __IO  uint16_t  SCLR                 :1;
            __IO  uint16_t  MODE                 :1;
            __IO  uint16_t  STOP                 :1;
            __IO  uint16_t  BFE                  :1;
            __IO  uint16_t  ICRE                 :1;
            __IO  uint16_t  ICLR                 :1;
            __IO  uint16_t  RESERVED0            :3;
            __IO  uint16_t  IRQZE                :1;
            __IO  uint16_t  IRQZF                :1;
            __IO  uint16_t  ECKE                 :1;
        };
        struct {
            __IO  uint16_t  CLK0                 :1;
            __IO  uint16_t  CLK1                 :1;
            __IO  uint16_t  CLK2                 :1;
            __IO  uint16_t  CLK3                 :1;
            __IO  uint16_t  RESERVED1            :12;
        };
    };
} stc_mft_tcsa1_field_t;

typedef struct stc_mft_tcsc1_field
{
    union {
        struct {
            __IO  uint16_t  MSZI                 :4;
            __IO  uint16_t  MSPI                 :4;
            __IO  uint16_t  MSZC                 :4;
            __IO  uint16_t  MSPC                 :4;
        };
        struct {
            __IO  uint16_t  MSZI0                :1;
            __IO  uint16_t  MSZI1                :1;
            __IO  uint16_t  MSZI2                :1;
            __IO  uint16_t  MSZI3                :1;
            __IO  uint16_t  MSPI0                :1;
            __IO  uint16_t  MSPI1                :1;
            __IO  uint16_t  MSPI2                :1;
            __IO  uint16_t  MSPI3                :1;
            __IO  uint16_t  MSZC0                :1;
            __IO  uint16_t  MSZC1                :1;
            __IO  uint16_t  MSZC2                :1;
            __IO  uint16_t  MSZC3                :1;
            __IO  uint16_t  MSPC0                :1;
            __IO  uint16_t  MSPC1                :1;
            __IO  uint16_t  MSPC2                :1;
            __IO  uint16_t  MSPC3                :1;
        };
    };
} stc_mft_tcsc1_field_t;

typedef struct stc_mft_tccp2_field
{
    union {
        struct {
            __IO  uint16_t  TCCP                 :16;
        };
        struct {
            __IO  uint16_t  TCCP0                :1;
            __IO  uint16_t  TCCP1                :1;
            __IO  uint16_t  TCCP2                :1;
            __IO  uint16_t  TCCP3                :1;
            __IO  uint16_t  TCCP4                :1;
            __IO  uint16_t  TCCP5                :1;
            __IO  uint16_t  TCCP6                :1;
            __IO  uint16_t  TCCP7                :1;
            __IO  uint16_t  TCCP8                :1;
            __IO  uint16_t  TCCP9                :1;
            __IO  uint16_t  TCCP10               :1;
            __IO  uint16_t  TCCP11               :1;
            __IO  uint16_t  TCCP12               :1;
            __IO  uint16_t  TCCP13               :1;
            __IO  uint16_t  TCCP14               :1;
            __IO  uint16_t  TCCP15               :1;
        };
    };
} stc_mft_tccp2_field_t;

typedef struct stc_mft_tcsa2_field
{
    union {
        struct {
            __IO  uint16_t  CLK                  :4;
            __IO  uint16_t  SCLR                 :1;
            __IO  uint16_t  MODE                 :1;
            __IO  uint16_t  STOP                 :1;
            __IO  uint16_t  BFE                  :1;
            __IO  uint16_t  ICRE                 :1;
            __IO  uint16_t  ICLR                 :1;
            __IO  uint16_t  RESERVED0            :3;
            __IO  uint16_t  IRQZE                :1;
            __IO  uint16_t  IRQZF                :1;
            __IO  uint16_t  ECKE                 :1;
        };
        struct {
            __IO  uint16_t  CLK0                 :1;
            __IO  uint16_t  CLK1                 :1;
            __IO  uint16_t  CLK2                 :1;
            __IO  uint16_t  CLK3                 :1;
            __IO  uint16_t  RESERVED1            :12;
        };
    };
} stc_mft_tcsa2_field_t;

typedef struct stc_mft_tcsc2_field
{
    union {
        struct {
            __IO  uint16_t  MSZI                 :4;
            __IO  uint16_t  MSPI                 :4;
            __IO  uint16_t  MSZC                 :4;
            __IO  uint16_t  MSPC                 :4;
        };
        struct {
            __IO  uint16_t  MSZI0                :1;
            __IO  uint16_t  MSZI1                :1;
            __IO  uint16_t  MSZI2                :1;
            __IO  uint16_t  MSZI3                :1;
            __IO  uint16_t  MSPI0                :1;
            __IO  uint16_t  MSPI1                :1;
            __IO  uint16_t  MSPI2                :1;
            __IO  uint16_t  MSPI3                :1;
            __IO  uint16_t  MSZC0                :1;
            __IO  uint16_t  MSZC1                :1;
            __IO  uint16_t  MSZC2                :1;
            __IO  uint16_t  MSZC3                :1;
            __IO  uint16_t  MSPC0                :1;
            __IO  uint16_t  MSPC1                :1;
            __IO  uint16_t  MSPC2                :1;
            __IO  uint16_t  MSPC3                :1;
        };
    };
} stc_mft_tcsc2_field_t;

typedef struct stc_mft_tcal_field
{
        __IO  uint32_t  STOP00                   :1;
        __IO  uint32_t  STOP01                   :1;
        __IO  uint32_t  STOP02                   :1;
        __IO  uint32_t  STOP10                   :1;
        __IO  uint32_t  STOP11                   :1;
        __IO  uint32_t  STOP12                   :1;
        __IO  uint32_t  STOP20                   :1;
        __IO  uint32_t  STOP21                   :1;
        __IO  uint32_t  STOP22                   :1;
        __IO  uint32_t  RESERVED0                :7;
        __IO  uint32_t  SCLR00                   :1;
        __IO  uint32_t  SCLR01                   :1;
        __IO  uint32_t  SCLR02                   :1;
        __IO  uint32_t  SCLR10                   :1;
        __IO  uint32_t  SCLR11                   :1;
        __IO  uint32_t  SCLR12                   :1;
        __IO  uint32_t  SCLR20                   :1;
        __IO  uint32_t  SCLR21                   :1;
        __IO  uint32_t  SCLR22                   :1;
        __IO  uint32_t  RESERVED1                :7;
} stc_mft_tcal_field_t;

typedef struct stc_mft_ocfs10_field
{
    union {
        struct {
            __IO   uint8_t  FSO0                 :4;
            __IO   uint8_t  FSO1                 :4;
        };
        struct {
            __IO   uint8_t  FSO00                :1;
            __IO   uint8_t  FSO01                :1;
            __IO   uint8_t  FSO02                :1;
            __IO   uint8_t  FSO03                :1;
            __IO   uint8_t  FSO10                :1;
            __IO   uint8_t  FSO11                :1;
            __IO   uint8_t  FSO12                :1;
            __IO   uint8_t  FSO13                :1;
        };
    };
} stc_mft_ocfs10_field_t;

typedef struct stc_mft_ocfs32_field
{
    union {
        struct {
            __IO   uint8_t  FSO2                 :4;
            __IO   uint8_t  FSO3                 :4;
        };
        struct {
            __IO   uint8_t  FSO20                :1;
            __IO   uint8_t  FSO21                :1;
            __IO   uint8_t  FSO22                :1;
            __IO   uint8_t  FSO23                :1;
            __IO   uint8_t  FSO30                :1;
            __IO   uint8_t  FSO31                :1;
            __IO   uint8_t  FSO32                :1;
            __IO   uint8_t  FSO33                :1;
        };
    };
} stc_mft_ocfs32_field_t;

typedef struct stc_mft_ocfs54_field
{
    union {
        struct {
            __IO   uint8_t  FSO4                 :4;
            __IO   uint8_t  FSO5                 :4;
        };
        struct {
            __IO   uint8_t  FSO40                :1;
            __IO   uint8_t  FSO41                :1;
            __IO   uint8_t  FSO42                :1;
            __IO   uint8_t  FSO43                :1;
            __IO   uint8_t  FSO50                :1;
            __IO   uint8_t  FSO51                :1;
            __IO   uint8_t  FSO52                :1;
            __IO   uint8_t  FSO53                :1;
        };
    };
} stc_mft_ocfs54_field_t;

typedef struct stc_mft_icfs10_field
{
    union {
        struct {
            __IO   uint8_t  FSI0                 :4;
            __IO   uint8_t  FSI1                 :4;
        };
        struct {
            __IO   uint8_t  FSI00                :1;
            __IO   uint8_t  FSI01                :1;
            __IO   uint8_t  FSI02                :1;
            __IO   uint8_t  FSI03                :1;
            __IO   uint8_t  FSI10                :1;
            __IO   uint8_t  FSI11                :1;
            __IO   uint8_t  FSI12                :1;
            __IO   uint8_t  FSI13                :1;
        };
    };
} stc_mft_icfs10_field_t;

typedef struct stc_mft_icfs32_field
{
    union {
        struct {
            __IO   uint8_t  FSI2                 :4;
            __IO   uint8_t  FSI3                 :4;
        };
        struct {
            __IO   uint8_t  FSI20                :1;
            __IO   uint8_t  FSI21                :1;
            __IO   uint8_t  FSI22                :1;
            __IO   uint8_t  FSI23                :1;
            __IO   uint8_t  FSI30                :1;
            __IO   uint8_t  FSI31                :1;
            __IO   uint8_t  FSI32                :1;
            __IO   uint8_t  FSI33                :1;
        };
    };
} stc_mft_icfs32_field_t;

typedef struct stc_mft_acfs10_field
{
    union {
        struct {
            __IO   uint8_t  FSA0                 :4;
            __IO   uint8_t  FSA1                 :4;
        };
        struct {
            __IO   uint8_t  FSA00                :1;
            __IO   uint8_t  FSA01                :1;
            __IO   uint8_t  FSA02                :1;
            __IO   uint8_t  FSA03                :1;
            __IO   uint8_t  FSA10                :1;
            __IO   uint8_t  FSA11                :1;
            __IO   uint8_t  FSA12                :1;
            __IO   uint8_t  FSA13                :1;
        };
    };
} stc_mft_acfs10_field_t;

typedef struct stc_mft_acfs32_field
{
    union {
        struct {
            __IO   uint8_t  FSA2                 :4;
            __IO   uint8_t  FSA3                 :4;
        };
        struct {
            __IO   uint8_t  FSA20                :1;
            __IO   uint8_t  FSA21                :1;
            __IO   uint8_t  FSA22                :1;
            __IO   uint8_t  FSA23                :1;
            __IO   uint8_t  FSA30                :1;
            __IO   uint8_t  FSA31                :1;
            __IO   uint8_t  FSA32                :1;
            __IO   uint8_t  FSA33                :1;
        };
    };
} stc_mft_acfs32_field_t;

typedef struct stc_mft_acfs54_field
{
    union {
        struct {
            __IO   uint8_t  FSA4                 :4;
            __IO   uint8_t  FSA5                 :4;
        };
        struct {
            __IO   uint8_t  FSA40                :1;
            __IO   uint8_t  FSA41                :1;
            __IO   uint8_t  FSA42                :1;
            __IO   uint8_t  FSA43                :1;
            __IO   uint8_t  FSA50                :1;
            __IO   uint8_t  FSA51                :1;
            __IO   uint8_t  FSA52                :1;
            __IO   uint8_t  FSA53                :1;
        };
    };
} stc_mft_acfs54_field_t;

typedef struct stc_mft_icsa10_field
{
    union {
        struct {
            __IO   uint8_t  EG0                  :2;
            __IO   uint8_t  EG1                  :2;
            __IO   uint8_t  ICE0                 :1;
            __IO   uint8_t  ICE1                 :1;
            __IO   uint8_t  ICP0                 :1;
            __IO   uint8_t  ICP1                 :1;
        };
        struct {
            __IO   uint8_t  EG00                 :1;
            __IO   uint8_t  EG01                 :1;
            __IO   uint8_t  EG10                 :1;
            __IO   uint8_t  EG11                 :1;
            __IO   uint8_t  RESERVED0            :4;
        };
    };
} stc_mft_icsa10_field_t;

typedef struct stc_mft_icsb10_field
{
        __IO   uint8_t  IEI0                     :1;
        __IO   uint8_t  IEI1                     :1;
        __IO   uint8_t  RESERVED0                :6;
} stc_mft_icsb10_field_t;

typedef struct stc_mft_icsa32_field
{
    union {
        struct {
            __IO   uint8_t  EG2                  :2;
            __IO   uint8_t  EG3                  :2;
            __IO   uint8_t  ICE2                 :1;
            __IO   uint8_t  ICE3                 :1;
            __IO   uint8_t  ICP2                 :1;
            __IO   uint8_t  ICP3                 :1;
        };
        struct {
            __IO   uint8_t  EG20                 :1;
            __IO   uint8_t  EG21                 :1;
            __IO   uint8_t  EG30                 :1;
            __IO   uint8_t  EG31                 :1;
            __IO   uint8_t  RESERVED0            :4;
        };
    };
} stc_mft_icsa32_field_t;

typedef struct stc_mft_icsb32_field
{
        __IO   uint8_t  IEI2                     :1;
        __IO   uint8_t  IEI3                     :1;
        __IO   uint8_t  RESERVED0                :6;
} stc_mft_icsb32_field_t;

typedef struct stc_mft_wfsa10_field
{
    union {
        struct {
            __IO  uint16_t  DCK                  :3;
            __IO  uint16_t  TMD                  :3;
            __IO  uint16_t  GTEN                 :2;
            __IO  uint16_t  PSEL                 :2;
            __IO  uint16_t  PGEN                 :2;
            __IO  uint16_t  DMOD                 :2;
            __IO  uint16_t  RESERVED0            :2;
        };
        struct {
            __IO  uint16_t  DCK0                 :1;
            __IO  uint16_t  DCK1                 :1;
            __IO  uint16_t  DCK2                 :1;
            __IO  uint16_t  TMD0                 :1;
            __IO  uint16_t  TMD1                 :1;
            __IO  uint16_t  TMD2                 :1;
            __IO  uint16_t  GTEN0                :1;
            __IO  uint16_t  GTEN1                :1;
            __IO  uint16_t  PSEL0                :1;
            __IO  uint16_t  PSEL1                :1;
            __IO  uint16_t  PGEN0                :1;
            __IO  uint16_t  PGEN1                :1;
            __IO  uint16_t  DMOD0                :1;
            __IO  uint16_t  DMOD1                :1;
            __IO  uint16_t  RESERVED1            :2;
        };
    };
} stc_mft_wfsa10_field_t;

typedef struct stc_mft_wfsa32_field
{
    union {
        struct {
            __IO  uint16_t  DCK                  :3;
            __IO  uint16_t  TMD                  :3;
            __IO  uint16_t  GTEN                 :2;
            __IO  uint16_t  PSEL                 :2;
            __IO  uint16_t  PGEN                 :2;
            __IO  uint16_t  DMOD                 :2;
            __IO  uint16_t  RESERVED0            :2;
        };
        struct {
            __IO  uint16_t  DCK0                 :1;
            __IO  uint16_t  DCK1                 :1;
            __IO  uint16_t  DCK2                 :1;
            __IO  uint16_t  TMD0                 :1;
            __IO  uint16_t  TMD1                 :1;
            __IO  uint16_t  TMD2                 :1;
            __IO  uint16_t  GTEN0                :1;
            __IO  uint16_t  GTEN1                :1;
            __IO  uint16_t  PSEL0                :1;
            __IO  uint16_t  PSEL1                :1;
            __IO  uint16_t  PGEN0                :1;
            __IO  uint16_t  PGEN1                :1;
            __IO  uint16_t  DMOD0                :1;
            __IO  uint16_t  DMOD1                :1;
            __IO  uint16_t  RESERVED1            :2;
        };
    };
} stc_mft_wfsa32_field_t;

typedef struct stc_mft_wfsa54_field
{
    union {
        struct {
            __IO  uint16_t  DCK                  :3;
            __IO  uint16_t  TMD                  :3;
            __IO  uint16_t  GTEN                 :2;
            __IO  uint16_t  PSEL                 :2;
            __IO  uint16_t  PGEN                 :2;
            __IO  uint16_t  DMOD                 :2;
            __IO  uint16_t  RESERVED0            :2;
        };
        struct {
            __IO  uint16_t  DCK0                 :1;
            __IO  uint16_t  DCK1                 :1;
            __IO  uint16_t  DCK2                 :1;
            __IO  uint16_t  TMD0                 :1;
            __IO  uint16_t  TMD1                 :1;
            __IO  uint16_t  TMD2                 :1;
            __IO  uint16_t  GTEN0                :1;
            __IO  uint16_t  GTEN1                :1;
            __IO  uint16_t  PSEL0                :1;
            __IO  uint16_t  PSEL1                :1;
            __IO  uint16_t  PGEN0                :1;
            __IO  uint16_t  PGEN1                :1;
            __IO  uint16_t  DMOD0                :1;
            __IO  uint16_t  DMOD1                :1;
            __IO  uint16_t  RESERVED1            :2;
        };
    };
} stc_mft_wfsa54_field_t;

typedef struct stc_mft_wfir_field
{
        __IO  uint16_t  DTIFA                    :1;
        __IO  uint16_t  DTICA                    :1;
        __IO  uint16_t  DTIFB                    :1;
        __IO  uint16_t  DTICB                    :1;
        __IO  uint16_t  TMIF10                   :1;
        __IO  uint16_t  TMIC10                   :1;
        __IO  uint16_t  TMIE10                   :1;
        __IO  uint16_t  TMIS10                   :1;
        __IO  uint16_t  TMIF32                   :1;
        __IO  uint16_t  TMIC32                   :1;
        __IO  uint16_t  TMIE32                   :1;
        __IO  uint16_t  TMIS32                   :1;
        __IO  uint16_t  TMIF54                   :1;
        __IO  uint16_t  TMIC54                   :1;
        __IO  uint16_t  TMIE54                   :1;
        __IO  uint16_t  TMIS54                   :1;
} stc_mft_wfir_field_t;

typedef struct stc_mft_nzcl_field
{
    union {
        struct {
            __IO  uint16_t  DTIEA                :1;
            __IO  uint16_t  NWS                  :3;
            __IO  uint16_t  SDTI                 :1;
            __IO  uint16_t  DTIEB                :1;
            __IO  uint16_t  RESERVED1            :1;
            __IO  uint16_t  DHOLD                :1;
            __IO  uint16_t  DIMA                 :1;
            __IO  uint16_t  DIMB                 :1;
            __IO  uint16_t  RESERVED2            :2;
            __IO  uint16_t  WIM10                :1;
            __IO  uint16_t  WIM32                :1;
            __IO  uint16_t  WIM54                :1;
            __IO  uint16_t  RESERVED3            :1;
        };
        struct {
            __IO  uint16_t  RESERVED0            :1;
            __IO  uint16_t  NWS0                 :1;
            __IO  uint16_t  NWS1                 :1;
            __IO  uint16_t  NWS2                 :1;
            __IO  uint16_t  RESERVED4            :12;
        };
    };
} stc_mft_nzcl_field_t;

typedef struct stc_mft_acmp0_field
{
    union {
        struct {
            __IO  uint16_t  ACMP                 :16;
        };
        struct {
            __IO  uint16_t  ACMP0                :1;
            __IO  uint16_t  ACMP1                :1;
            __IO  uint16_t  ACMP2                :1;
            __IO  uint16_t  ACMP3                :1;
            __IO  uint16_t  ACMP4                :1;
            __IO  uint16_t  ACMP5                :1;
            __IO  uint16_t  ACMP6                :1;
            __IO  uint16_t  ACMP7                :1;
            __IO  uint16_t  ACMP8                :1;
            __IO  uint16_t  ACMP9                :1;
            __IO  uint16_t  ACMP10               :1;
            __IO  uint16_t  ACMP11               :1;
            __IO  uint16_t  ACMP12               :1;
            __IO  uint16_t  ACMP13               :1;
            __IO  uint16_t  ACMP14               :1;
            __IO  uint16_t  ACMP15               :1;
        };
    };
} stc_mft_acmp0_field_t;

typedef struct stc_mft_acmp1_field
{
    union {
        struct {
            __IO  uint16_t  ACMP                 :16;
        };
        struct {
            __IO  uint16_t  ACMP0                :1;
            __IO  uint16_t  ACMP1                :1;
            __IO  uint16_t  ACMP2                :1;
            __IO  uint16_t  ACMP3                :1;
            __IO  uint16_t  ACMP4                :1;
            __IO  uint16_t  ACMP5                :1;
            __IO  uint16_t  ACMP6                :1;
            __IO  uint16_t  ACMP7                :1;
            __IO  uint16_t  ACMP8                :1;
            __IO  uint16_t  ACMP9                :1;
            __IO  uint16_t  ACMP10               :1;
            __IO  uint16_t  ACMP11               :1;
            __IO  uint16_t  ACMP12               :1;
            __IO  uint16_t  ACMP13               :1;
            __IO  uint16_t  ACMP14               :1;
            __IO  uint16_t  ACMP15               :1;
        };
    };
} stc_mft_acmp1_field_t;

typedef struct stc_mft_acmp2_field
{
    union {
        struct {
            __IO  uint16_t  ACMP                 :16;
        };
        struct {
            __IO  uint16_t  ACMP0                :1;
            __IO  uint16_t  ACMP1                :1;
            __IO  uint16_t  ACMP2                :1;
            __IO  uint16_t  ACMP3                :1;
            __IO  uint16_t  ACMP4                :1;
            __IO  uint16_t  ACMP5                :1;
            __IO  uint16_t  ACMP6                :1;
            __IO  uint16_t  ACMP7                :1;
            __IO  uint16_t  ACMP8                :1;
            __IO  uint16_t  ACMP9                :1;
            __IO  uint16_t  ACMP10               :1;
            __IO  uint16_t  ACMP11               :1;
            __IO  uint16_t  ACMP12               :1;
            __IO  uint16_t  ACMP13               :1;
            __IO  uint16_t  ACMP14               :1;
            __IO  uint16_t  ACMP15               :1;
        };
    };
} stc_mft_acmp2_field_t;

typedef struct stc_mft_acmp3_field
{
    union {
        struct {
            __IO  uint16_t  ACMP                 :16;
        };
        struct {
            __IO  uint16_t  ACMP0                :1;
            __IO  uint16_t  ACMP1                :1;
            __IO  uint16_t  ACMP2                :1;
            __IO  uint16_t  ACMP3                :1;
            __IO  uint16_t  ACMP4                :1;
            __IO  uint16_t  ACMP5                :1;
            __IO  uint16_t  ACMP6                :1;
            __IO  uint16_t  ACMP7                :1;
            __IO  uint16_t  ACMP8                :1;
            __IO  uint16_t  ACMP9                :1;
            __IO  uint16_t  ACMP10               :1;
            __IO  uint16_t  ACMP11               :1;
            __IO  uint16_t  ACMP12               :1;
            __IO  uint16_t  ACMP13               :1;
            __IO  uint16_t  ACMP14               :1;
            __IO  uint16_t  ACMP15               :1;
        };
    };
} stc_mft_acmp3_field_t;

typedef struct stc_mft_acmp4_field
{
    union {
        struct {
            __IO  uint16_t  ACMP                 :16;
        };
        struct {
            __IO  uint16_t  ACMP0                :1;
            __IO  uint16_t  ACMP1                :1;
            __IO  uint16_t  ACMP2                :1;
            __IO  uint16_t  ACMP3                :1;
            __IO  uint16_t  ACMP4                :1;
            __IO  uint16_t  ACMP5                :1;
            __IO  uint16_t  ACMP6                :1;
            __IO  uint16_t  ACMP7                :1;
            __IO  uint16_t  ACMP8                :1;
            __IO  uint16_t  ACMP9                :1;
            __IO  uint16_t  ACMP10               :1;
            __IO  uint16_t  ACMP11               :1;
            __IO  uint16_t  ACMP12               :1;
            __IO  uint16_t  ACMP13               :1;
            __IO  uint16_t  ACMP14               :1;
            __IO  uint16_t  ACMP15               :1;
        };
    };
} stc_mft_acmp4_field_t;

typedef struct stc_mft_acmp5_field
{
    union {
        struct {
            __IO  uint16_t  ACMP                 :16;
        };
        struct {
            __IO  uint16_t  ACMP0                :1;
            __IO  uint16_t  ACMP1                :1;
            __IO  uint16_t  ACMP2                :1;
            __IO  uint16_t  ACMP3                :1;
            __IO  uint16_t  ACMP4                :1;
            __IO  uint16_t  ACMP5                :1;
            __IO  uint16_t  ACMP6                :1;
            __IO  uint16_t  ACMP7                :1;
            __IO  uint16_t  ACMP8                :1;
            __IO  uint16_t  ACMP9                :1;
            __IO  uint16_t  ACMP10               :1;
            __IO  uint16_t  ACMP11               :1;
            __IO  uint16_t  ACMP12               :1;
            __IO  uint16_t  ACMP13               :1;
            __IO  uint16_t  ACMP14               :1;
            __IO  uint16_t  ACMP15               :1;
        };
    };
} stc_mft_acmp5_field_t;

typedef struct stc_mft_acsa_field
{
    union {
        struct {
            __IO  uint16_t  CE10                 :2;
            __IO  uint16_t  CE32                 :2;
            __IO  uint16_t  CE54                 :2;
            __IO  uint16_t  RESERVED0            :2;
            __IO  uint16_t  SEL10                :2;
            __IO  uint16_t  SEL32                :2;
            __IO  uint16_t  SEL54                :2;
            __IO  uint16_t  RESERVED2            :2;
        };
        struct {
            __IO  uint16_t  CE100                :1;
            __IO  uint16_t  CE101                :1;
            __IO  uint16_t  CE320                :1;
            __IO  uint16_t  CE321                :1;
            __IO  uint16_t  CE540                :1;
            __IO  uint16_t  CE541                :1;
            __IO  uint16_t  RESERVED1            :2;
            __IO  uint16_t  SEL100               :1;
            __IO  uint16_t  SEL101               :1;
            __IO  uint16_t  SEL320               :1;
            __IO  uint16_t  SEL321               :1;
            __IO  uint16_t  SEL540               :1;
            __IO  uint16_t  SEL541               :1;
            __IO  uint16_t  RESERVED3            :2;
        };
    };
} stc_mft_acsa_field_t;

typedef struct stc_mft_acsc0_field
{
    union {
        struct {
            __IO   uint8_t  BUFE                 :2;
            __IO   uint8_t  ADSEL                :3;
            __IO   uint8_t  APBM                 :1;
            __IO   uint8_t  RESERVED0            :2;
        };
        struct {
            __IO   uint8_t  BUFE0                :1;
            __IO   uint8_t  BUFE1                :1;
            __IO   uint8_t  ADSEL0               :1;
            __IO   uint8_t  ADSEL1               :1;
            __IO   uint8_t  ADSEL2               :1;
            __IO   uint8_t  RESERVED1            :3;
        };
    };
} stc_mft_acsc0_field_t;

typedef struct stc_mft_acsd0_field
{
        __IO   uint8_t  AMOD                     :1;
        __IO   uint8_t  OCUS                     :1;
        __IO   uint8_t  RESERVED0                :2;
        __IO   uint8_t  DE                       :1;
        __IO   uint8_t  PE                       :1;
        __IO   uint8_t  UE                       :1;
        __IO   uint8_t  ZE                       :1;
} stc_mft_acsd0_field_t;

typedef struct stc_mft_acmc0_field
{
    union {
        struct {
            __IO   uint8_t  AMC                  :4;
            __IO   uint8_t  RESERVED0            :2;
            __IO   uint8_t  MZCE                 :1;
            __IO   uint8_t  MPCE                 :1;
        };
        struct {
            __IO   uint8_t  AMC0                 :1;
            __IO   uint8_t  AMC1                 :1;
            __IO   uint8_t  AMC2                 :1;
            __IO   uint8_t  AMC3                 :1;
            __IO   uint8_t  RESERVED1            :4;
        };
    };
} stc_mft_acmc0_field_t;

typedef struct stc_mft_acsc1_field
{
    union {
        struct {
            __IO   uint8_t  BUFE                 :2;
            __IO   uint8_t  ADSEL                :3;
            __IO   uint8_t  APBM                 :1;
            __IO   uint8_t  RESERVED0            :2;
        };
        struct {
            __IO   uint8_t  BUFE0                :1;
            __IO   uint8_t  BUFE1                :1;
            __IO   uint8_t  ADSEL0               :1;
            __IO   uint8_t  ADSEL1               :1;
            __IO   uint8_t  ADSEL2               :1;
            __IO   uint8_t  RESERVED1            :3;
        };
    };
} stc_mft_acsc1_field_t;

typedef struct stc_mft_acsd1_field
{
        __IO   uint8_t  AMOD                     :1;
        __IO   uint8_t  OCUS                     :1;
        __IO   uint8_t  RESERVED0                :2;
        __IO   uint8_t  DE                       :1;
        __IO   uint8_t  PE                       :1;
        __IO   uint8_t  UE                       :1;
        __IO   uint8_t  ZE                       :1;
} stc_mft_acsd1_field_t;

typedef struct stc_mft_acmc1_field
{
    union {
        struct {
            __IO   uint8_t  AMC                  :4;
            __IO   uint8_t  RESERVED0            :2;
            __IO   uint8_t  MZCE                 :1;
            __IO   uint8_t  MPCE                 :1;
        };
        struct {
            __IO   uint8_t  AMC0                 :1;
            __IO   uint8_t  AMC1                 :1;
            __IO   uint8_t  AMC2                 :1;
            __IO   uint8_t  AMC3                 :1;
            __IO   uint8_t  RESERVED1            :4;
        };
    };
} stc_mft_acmc1_field_t;

typedef struct stc_mft_acsc2_field
{
    union {
        struct {
            __IO   uint8_t  BUFE                 :2;
            __IO   uint8_t  ADSEL                :3;
            __IO   uint8_t  APBM                 :1;
            __IO   uint8_t  RESERVED0            :2;
        };
        struct {
            __IO   uint8_t  BUFE0                :1;
            __IO   uint8_t  BUFE1                :1;
            __IO   uint8_t  ADSEL0               :1;
            __IO   uint8_t  ADSEL1               :1;
            __IO   uint8_t  ADSEL2               :1;
            __IO   uint8_t  RESERVED1            :3;
        };
    };
} stc_mft_acsc2_field_t;

typedef struct stc_mft_acsd2_field
{
        __IO   uint8_t  AMOD                     :1;
        __IO   uint8_t  OCUS                     :1;
        __IO   uint8_t  RESERVED0                :2;
        __IO   uint8_t  DE                       :1;
        __IO   uint8_t  PE                       :1;
        __IO   uint8_t  UE                       :1;
        __IO   uint8_t  ZE                       :1;
} stc_mft_acsd2_field_t;

typedef struct stc_mft_acmc2_field
{
    union {
        struct {
            __IO   uint8_t  AMC                  :4;
            __IO   uint8_t  RESERVED0            :2;
            __IO   uint8_t  MZCE                 :1;
            __IO   uint8_t  MPCE                 :1;
        };
        struct {
            __IO   uint8_t  AMC0                 :1;
            __IO   uint8_t  AMC1                 :1;
            __IO   uint8_t  AMC2                 :1;
            __IO   uint8_t  AMC3                 :1;
            __IO   uint8_t  RESERVED1            :4;
        };
    };
} stc_mft_acmc2_field_t;

typedef struct stc_mft_acsc3_field
{
    union {
        struct {
            __IO   uint8_t  BUFE                 :2;
            __IO   uint8_t  ADSEL                :3;
            __IO   uint8_t  APBM                 :1;
            __IO   uint8_t  RESERVED0            :2;
        };
        struct {
            __IO   uint8_t  BUFE0                :1;
            __IO   uint8_t  BUFE1                :1;
            __IO   uint8_t  ADSEL0               :1;
            __IO   uint8_t  ADSEL1               :1;
            __IO   uint8_t  ADSEL2               :1;
            __IO   uint8_t  RESERVED1            :3;
        };
    };
} stc_mft_acsc3_field_t;

typedef struct stc_mft_acsd3_field
{
        __IO   uint8_t  AMOD                     :1;
        __IO   uint8_t  OCUS                     :1;
        __IO   uint8_t  RESERVED0                :2;
        __IO   uint8_t  DE                       :1;
        __IO   uint8_t  PE                       :1;
        __IO   uint8_t  UE                       :1;
        __IO   uint8_t  ZE                       :1;
} stc_mft_acsd3_field_t;

typedef struct stc_mft_acmc3_field
{
    union {
        struct {
            __IO   uint8_t  AMC                  :4;
            __IO   uint8_t  RESERVED0            :2;
            __IO   uint8_t  MZCE                 :1;
            __IO   uint8_t  MPCE                 :1;
        };
        struct {
            __IO   uint8_t  AMC0                 :1;
            __IO   uint8_t  AMC1                 :1;
            __IO   uint8_t  AMC2                 :1;
            __IO   uint8_t  AMC3                 :1;
            __IO   uint8_t  RESERVED1            :4;
        };
    };
} stc_mft_acmc3_field_t;

typedef struct stc_mft_acsc4_field
{
    union {
        struct {
            __IO   uint8_t  BUFE                 :2;
            __IO   uint8_t  ADSEL                :3;
            __IO   uint8_t  APBM                 :1;
            __IO   uint8_t  RESERVED0            :2;
        };
        struct {
            __IO   uint8_t  BUFE0                :1;
            __IO   uint8_t  BUFE1                :1;
            __IO   uint8_t  ADSEL0               :1;
            __IO   uint8_t  ADSEL1               :1;
            __IO   uint8_t  ADSEL2               :1;
            __IO   uint8_t  RESERVED1            :3;
        };
    };
} stc_mft_acsc4_field_t;

typedef struct stc_mft_acsd4_field
{
        __IO   uint8_t  AMOD                     :1;
        __IO   uint8_t  OCUS                     :1;
        __IO   uint8_t  RESERVED0                :2;
        __IO   uint8_t  DE                       :1;
        __IO   uint8_t  PE                       :1;
        __IO   uint8_t  UE                       :1;
        __IO   uint8_t  ZE                       :1;
} stc_mft_acsd4_field_t;

typedef struct stc_mft_acmc4_field
{
    union {
        struct {
            __IO   uint8_t  AMC                  :4;
            __IO   uint8_t  RESERVED0            :2;
            __IO   uint8_t  MZCE                 :1;
            __IO   uint8_t  MPCE                 :1;
        };
        struct {
            __IO   uint8_t  AMC0                 :1;
            __IO   uint8_t  AMC1                 :1;
            __IO   uint8_t  AMC2                 :1;
            __IO   uint8_t  AMC3                 :1;
            __IO   uint8_t  RESERVED1            :4;
        };
    };
} stc_mft_acmc4_field_t;

typedef struct stc_mft_acsc5_field
{
    union {
        struct {
            __IO   uint8_t  BUFE                 :2;
            __IO   uint8_t  ADSEL                :3;
            __IO   uint8_t  APBM                 :1;
            __IO   uint8_t  RESERVED0            :2;
        };
        struct {
            __IO   uint8_t  BUFE0                :1;
            __IO   uint8_t  BUFE1                :1;
            __IO   uint8_t  ADSEL0               :1;
            __IO   uint8_t  ADSEL1               :1;
            __IO   uint8_t  ADSEL2               :1;
            __IO   uint8_t  RESERVED1            :3;
        };
    };
} stc_mft_acsc5_field_t;

typedef struct stc_mft_acsd5_field
{
        __IO   uint8_t  AMOD                     :1;
        __IO   uint8_t  OCUS                     :1;
        __IO   uint8_t  RESERVED0                :2;
        __IO   uint8_t  DE                       :1;
        __IO   uint8_t  PE                       :1;
        __IO   uint8_t  UE                       :1;
        __IO   uint8_t  ZE                       :1;
} stc_mft_acsd5_field_t;

typedef struct stc_mft_acmc5_field
{
    union {
        struct {
            __IO   uint8_t  AMC                  :4;
            __IO   uint8_t  RESERVED0            :2;
            __IO   uint8_t  MZCE                 :1;
            __IO   uint8_t  MPCE                 :1;
        };
        struct {
            __IO   uint8_t  AMC0                 :1;
            __IO   uint8_t  AMC1                 :1;
            __IO   uint8_t  AMC2                 :1;
            __IO   uint8_t  AMC3                 :1;
            __IO   uint8_t  RESERVED1            :4;
        };
    };
} stc_mft_acmc5_field_t;

typedef struct stc_mft_tcsd_field
{
        __IO   uint8_t  OFMD1                    :1;
        __IO   uint8_t  OFMD2                    :1;
        __IO   uint8_t  RESERVED0                :6;
} stc_mft_tcsd_field_t;

typedef struct stc_mft_ocu_ocsa10_field
{
        __IO   uint8_t  CST0                     :1;
        __IO   uint8_t  CST1                     :1;
        __IO   uint8_t  RESERVED0                :2;
        __IO   uint8_t  IOE0                     :1;
        __IO   uint8_t  IOE1                     :1;
        __IO   uint8_t  IOP0                     :1;
        __IO   uint8_t  IOP1                     :1;
} stc_mft_ocu_ocsa10_field_t;

typedef struct stc_mft_ocu_ocsb10_field
{
        __IO   uint8_t  OTD0                     :1;
        __IO   uint8_t  OTD1                     :1;
        __IO   uint8_t  RESERVED0                :2;
        __IO   uint8_t  CMOD                     :1;
        __IO   uint8_t  RESERVED1                :2;
        __IO   uint8_t  FM4                      :1;
} stc_mft_ocu_ocsb10_field_t;

typedef struct stc_mft_ocu_ocsd10_field
{
    union {
        struct {
            __IO  uint16_t  OCCP0BUFE            :2;
            __IO  uint16_t  OCCP1BUFE            :2;
            __IO  uint16_t  OCSE0BUFE            :2;
            __IO  uint16_t  OCSE1BUFE            :2;
            __IO  uint16_t  OPBM0                :1;
            __IO  uint16_t  OPBM1                :1;
            __IO  uint16_t  OEBM0                :1;
            __IO  uint16_t  OEBM1                :1;
            __IO  uint16_t  OFEX0                :1;
            __IO  uint16_t  OFEX1                :1;
            __IO  uint16_t  RESERVED0            :2;
        };
        struct {
            __IO  uint16_t  OCCP0BUFE0           :1;
            __IO  uint16_t  OCCP0BUFE1           :1;
            __IO  uint16_t  OCCP1BUFE0           :1;
            __IO  uint16_t  OCCP1BUFE1           :1;
            __IO  uint16_t  OCSE0BUFE0           :1;
            __IO  uint16_t  OCSE0BUFE1           :1;
            __IO  uint16_t  OCSE1BUFE0           :1;
            __IO  uint16_t  OCSE1BUFE1           :1;
            __IO  uint16_t  RESERVED1            :8;
        };
    };
} stc_mft_ocu_ocsd10_field_t;

typedef struct stc_mft_ocu_ocsa32_field
{
        __IO   uint8_t  CST2                     :1;
        __IO   uint8_t  CST3                     :1;
        __IO   uint8_t  RESERVED0                :2;
        __IO   uint8_t  IOE2                     :1;
        __IO   uint8_t  IOE3                     :1;
        __IO   uint8_t  IOP2                     :1;
        __IO   uint8_t  IOP3                     :1;
} stc_mft_ocu_ocsa32_field_t;

typedef struct stc_mft_ocu_ocsb32_field
{
        __IO   uint8_t  OTD2                     :1;
        __IO   uint8_t  OTD3                     :1;
        __IO   uint8_t  RESERVED0                :2;
        __IO   uint8_t  CMOD                     :1;
        __IO   uint8_t  RESERVED1                :2;
        __IO   uint8_t  FM4                      :1;
} stc_mft_ocu_ocsb32_field_t;

typedef struct stc_mft_ocu_ocsd32_field
{
    union {
        struct {
            __IO  uint16_t  OCCP2BUFE            :2;
            __IO  uint16_t  OCCP3BUFE            :2;
            __IO  uint16_t  OCSE2BUFE            :2;
            __IO  uint16_t  OCSE3BUFE            :2;
            __IO  uint16_t  OPBM2                :1;
            __IO  uint16_t  OPBM3                :1;
            __IO  uint16_t  OEBM2                :1;
            __IO  uint16_t  OEBM3                :1;
            __IO  uint16_t  OFEX2                :1;
            __IO  uint16_t  OFEX3                :1;
            __IO  uint16_t  RESERVED0            :2;
        };
        struct {
            __IO  uint16_t  OCCP2BUFE0           :1;
            __IO  uint16_t  OCCP2BUFE1           :1;
            __IO  uint16_t  OCCP3BUFE0           :1;
            __IO  uint16_t  OCCP3BUFE1           :1;
            __IO  uint16_t  OCSE2BUFE0           :1;
            __IO  uint16_t  OCSE2BUFE1           :1;
            __IO  uint16_t  OCSE3BUFE0           :1;
            __IO  uint16_t  OCSE3BUFE1           :1;
            __IO  uint16_t  RESERVED1            :8;
        };
    };
} stc_mft_ocu_ocsd32_field_t;

typedef struct stc_mft_ocu_ocsa54_field
{
        __IO   uint8_t  CST4                     :1;
        __IO   uint8_t  CST5                     :1;
        __IO   uint8_t  RESERVED0                :2;
        __IO   uint8_t  IOE4                     :1;
        __IO   uint8_t  IOE5                     :1;
        __IO   uint8_t  IOP4                     :1;
        __IO   uint8_t  IOP5                     :1;
} stc_mft_ocu_ocsa54_field_t;

typedef struct stc_mft_ocu_ocsb54_field
{
        __IO   uint8_t  OTD4                     :1;
        __IO   uint8_t  OTD5                     :1;
        __IO   uint8_t  RESERVED0                :2;
        __IO   uint8_t  CMOD                     :1;
        __IO   uint8_t  RESERVED1                :2;
        __IO   uint8_t  FM4                      :1;
} stc_mft_ocu_ocsb54_field_t;

typedef struct stc_mft_ocu_ocsd54_field
{
    union {
        struct {
            __IO  uint16_t  OCCP4BUFE            :2;
            __IO  uint16_t  OCCP5BUFE            :2;
            __IO  uint16_t  OCSE4BUFE            :2;
            __IO  uint16_t  OCSE5BUFE            :2;
            __IO  uint16_t  OPBM4                :1;
            __IO  uint16_t  OPBM5                :1;
            __IO  uint16_t  OEBM4                :1;
            __IO  uint16_t  OEBM5                :1;
            __IO  uint16_t  OFEX4                :1;
            __IO  uint16_t  OFEX5                :1;
            __IO  uint16_t  RESERVED0            :2;
        };
        struct {
            __IO  uint16_t  OCCP4BUFE0           :1;
            __IO  uint16_t  OCCP4BUFE1           :1;
            __IO  uint16_t  OCCP5BUFE0           :1;
            __IO  uint16_t  OCCP5BUFE1           :1;
            __IO  uint16_t  OCSE4BUFE0           :1;
            __IO  uint16_t  OCSE4BUFE1           :1;
            __IO  uint16_t  OCSE5BUFE0           :1;
            __IO  uint16_t  OCSE5BUFE1           :1;
            __IO  uint16_t  RESERVED1            :8;
        };
    };
} stc_mft_ocu_ocsd54_field_t;

typedef struct stc_mft_ocu_ocsc_field
{
        __IO   uint8_t  MOD0                     :1;
        __IO   uint8_t  MOD1                     :1;
        __IO   uint8_t  MOD2                     :1;
        __IO   uint8_t  MOD3                     :1;
        __IO   uint8_t  MOD4                     :1;
        __IO   uint8_t  MOD5                     :1;
        __IO   uint8_t  RESERVED0                :2;
} stc_mft_ocu_ocsc_field_t;

typedef struct stc_mft_ocu_ocse0_field
{
    union {
        struct {
            __IO  uint16_t  OCSE                 :16;
        };
        struct {
            __IO  uint16_t  OCSE0                :1;
            __IO  uint16_t  OCSE1                :1;
            __IO  uint16_t  OCSE2                :1;
            __IO  uint16_t  OCSE3                :1;
            __IO  uint16_t  OCSE4                :1;
            __IO  uint16_t  OCSE5                :1;
            __IO  uint16_t  OCSE6                :1;
            __IO  uint16_t  OCSE7                :1;
            __IO  uint16_t  OCSE8                :1;
            __IO  uint16_t  OCSE9                :1;
            __IO  uint16_t  OCSE10               :1;
            __IO  uint16_t  OCSE11               :1;
            __IO  uint16_t  OCSE12               :1;
            __IO  uint16_t  OCSE13               :1;
            __IO  uint16_t  OCSE14               :1;
            __IO  uint16_t  OCSE15               :1;
        };
    };
} stc_mft_ocu_ocse0_field_t;

typedef struct stc_mft_ocu_ocse1_field
{
    union {
        struct {
            __IO  uint32_t  OCSE                 :32;
        };
        struct {
            __IO  uint32_t  OCSE0                :1;
            __IO  uint32_t  OCSE1                :1;
            __IO  uint32_t  OCSE2                :1;
            __IO  uint32_t  OCSE3                :1;
            __IO  uint32_t  OCSE4                :1;
            __IO  uint32_t  OCSE5                :1;
            __IO  uint32_t  OCSE6                :1;
            __IO  uint32_t  OCSE7                :1;
            __IO  uint32_t  OCSE8                :1;
            __IO  uint32_t  OCSE9                :1;
            __IO  uint32_t  OCSE10               :1;
            __IO  uint32_t  OCSE11               :1;
            __IO  uint32_t  OCSE12               :1;
            __IO  uint32_t  OCSE13               :1;
            __IO  uint32_t  OCSE14               :1;
            __IO  uint32_t  OCSE15               :1;
            __IO  uint32_t  OCSE16               :1;
            __IO  uint32_t  OCSE17               :1;
            __IO  uint32_t  OCSE18               :1;
            __IO  uint32_t  OCSE19               :1;
            __IO  uint32_t  OCSE20               :1;
            __IO  uint32_t  OCSE21               :1;
            __IO  uint32_t  OCSE22               :1;
            __IO  uint32_t  OCSE23               :1;
            __IO  uint32_t  OCSE24               :1;
            __IO  uint32_t  OCSE25               :1;
            __IO  uint32_t  OCSE26               :1;
            __IO  uint32_t  OCSE27               :1;
            __IO  uint32_t  OCSE28               :1;
            __IO  uint32_t  OCSE29               :1;
            __IO  uint32_t  OCSE30               :1;
            __IO  uint32_t  OCSE31               :1;
        };
    };
} stc_mft_ocu_ocse1_field_t;

typedef struct stc_mft_ocu_ocse2_field
{
    union {
        struct {
            __IO  uint16_t  OCSE                 :16;
        };
        struct {
            __IO  uint16_t  OCSE0                :1;
            __IO  uint16_t  OCSE1                :1;
            __IO  uint16_t  OCSE2                :1;
            __IO  uint16_t  OCSE3                :1;
            __IO  uint16_t  OCSE4                :1;
            __IO  uint16_t  OCSE5                :1;
            __IO  uint16_t  OCSE6                :1;
            __IO  uint16_t  OCSE7                :1;
            __IO  uint16_t  OCSE8                :1;
            __IO  uint16_t  OCSE9                :1;
            __IO  uint16_t  OCSE10               :1;
            __IO  uint16_t  OCSE11               :1;
            __IO  uint16_t  OCSE12               :1;
            __IO  uint16_t  OCSE13               :1;
            __IO  uint16_t  OCSE14               :1;
            __IO  uint16_t  OCSE15               :1;
        };
    };
} stc_mft_ocu_ocse2_field_t;

typedef struct stc_mft_ocu_ocse3_field
{
    union {
        struct {
            __IO  uint32_t  OCSE                 :32;
        };
        struct {
            __IO  uint32_t  OCSE0                :1;
            __IO  uint32_t  OCSE1                :1;
            __IO  uint32_t  OCSE2                :1;
            __IO  uint32_t  OCSE3                :1;
            __IO  uint32_t  OCSE4                :1;
            __IO  uint32_t  OCSE5                :1;
            __IO  uint32_t  OCSE6                :1;
            __IO  uint32_t  OCSE7                :1;
            __IO  uint32_t  OCSE8                :1;
            __IO  uint32_t  OCSE9                :1;
            __IO  uint32_t  OCSE10               :1;
            __IO  uint32_t  OCSE11               :1;
            __IO  uint32_t  OCSE12               :1;
            __IO  uint32_t  OCSE13               :1;
            __IO  uint32_t  OCSE14               :1;
            __IO  uint32_t  OCSE15               :1;
            __IO  uint32_t  OCSE16               :1;
            __IO  uint32_t  OCSE17               :1;
            __IO  uint32_t  OCSE18               :1;
            __IO  uint32_t  OCSE19               :1;
            __IO  uint32_t  OCSE20               :1;
            __IO  uint32_t  OCSE21               :1;
            __IO  uint32_t  OCSE22               :1;
            __IO  uint32_t  OCSE23               :1;
            __IO  uint32_t  OCSE24               :1;
            __IO  uint32_t  OCSE25               :1;
            __IO  uint32_t  OCSE26               :1;
            __IO  uint32_t  OCSE27               :1;
            __IO  uint32_t  OCSE28               :1;
            __IO  uint32_t  OCSE29               :1;
            __IO  uint32_t  OCSE30               :1;
            __IO  uint32_t  OCSE31               :1;
        };
    };
} stc_mft_ocu_ocse3_field_t;

typedef struct stc_mft_ocu_ocse4_field
{
    union {
        struct {
            __IO  uint16_t  OCSE                 :16;
        };
        struct {
            __IO  uint16_t  OCSE0                :1;
            __IO  uint16_t  OCSE1                :1;
            __IO  uint16_t  OCSE2                :1;
            __IO  uint16_t  OCSE3                :1;
            __IO  uint16_t  OCSE4                :1;
            __IO  uint16_t  OCSE5                :1;
            __IO  uint16_t  OCSE6                :1;
            __IO  uint16_t  OCSE7                :1;
            __IO  uint16_t  OCSE8                :1;
            __IO  uint16_t  OCSE9                :1;
            __IO  uint16_t  OCSE10               :1;
            __IO  uint16_t  OCSE11               :1;
            __IO  uint16_t  OCSE12               :1;
            __IO  uint16_t  OCSE13               :1;
            __IO  uint16_t  OCSE14               :1;
            __IO  uint16_t  OCSE15               :1;
        };
    };
} stc_mft_ocu_ocse4_field_t;

typedef struct stc_mft_ocu_ocse5_field
{
    union {
        struct {
            __IO  uint32_t  OCSE                 :32;
        };
        struct {
            __IO  uint32_t  OCSE0                :1;
            __IO  uint32_t  OCSE1                :1;
            __IO  uint32_t  OCSE2                :1;
            __IO  uint32_t  OCSE3                :1;
            __IO  uint32_t  OCSE4                :1;
            __IO  uint32_t  OCSE5                :1;
            __IO  uint32_t  OCSE6                :1;
            __IO  uint32_t  OCSE7                :1;
            __IO  uint32_t  OCSE8                :1;
            __IO  uint32_t  OCSE9                :1;
            __IO  uint32_t  OCSE10               :1;
            __IO  uint32_t  OCSE11               :1;
            __IO  uint32_t  OCSE12               :1;
            __IO  uint32_t  OCSE13               :1;
            __IO  uint32_t  OCSE14               :1;
            __IO  uint32_t  OCSE15               :1;
            __IO  uint32_t  OCSE16               :1;
            __IO  uint32_t  OCSE17               :1;
            __IO  uint32_t  OCSE18               :1;
            __IO  uint32_t  OCSE19               :1;
            __IO  uint32_t  OCSE20               :1;
            __IO  uint32_t  OCSE21               :1;
            __IO  uint32_t  OCSE22               :1;
            __IO  uint32_t  OCSE23               :1;
            __IO  uint32_t  OCSE24               :1;
            __IO  uint32_t  OCSE25               :1;
            __IO  uint32_t  OCSE26               :1;
            __IO  uint32_t  OCSE27               :1;
            __IO  uint32_t  OCSE28               :1;
            __IO  uint32_t  OCSE29               :1;
            __IO  uint32_t  OCSE30               :1;
            __IO  uint32_t  OCSE31               :1;
        };
    };
} stc_mft_ocu_ocse5_field_t;

typedef struct stc_mft_frt_tccp0_field
{
    union {
        struct {
            __IO  uint16_t  TCCP                 :16;
        };
        struct {
            __IO  uint16_t  TCCP0                :1;
            __IO  uint16_t  TCCP1                :1;
            __IO  uint16_t  TCCP2                :1;
            __IO  uint16_t  TCCP3                :1;
            __IO  uint16_t  TCCP4                :1;
            __IO  uint16_t  TCCP5                :1;
            __IO  uint16_t  TCCP6                :1;
            __IO  uint16_t  TCCP7                :1;
            __IO  uint16_t  TCCP8                :1;
            __IO  uint16_t  TCCP9                :1;
            __IO  uint16_t  TCCP10               :1;
            __IO  uint16_t  TCCP11               :1;
            __IO  uint16_t  TCCP12               :1;
            __IO  uint16_t  TCCP13               :1;
            __IO  uint16_t  TCCP14               :1;
            __IO  uint16_t  TCCP15               :1;
        };
    };
} stc_mft_frt_tccp0_field_t;

typedef struct stc_mft_frt_tcsa0_field
{
    union {
        struct {
            __IO  uint16_t  CLK                  :4;
            __IO  uint16_t  SCLR                 :1;
            __IO  uint16_t  MODE                 :1;
            __IO  uint16_t  STOP                 :1;
            __IO  uint16_t  BFE                  :1;
            __IO  uint16_t  ICRE                 :1;
            __IO  uint16_t  ICLR                 :1;
            __IO  uint16_t  RESERVED0            :3;
            __IO  uint16_t  IRQZE                :1;
            __IO  uint16_t  IRQZF                :1;
            __IO  uint16_t  ECKE                 :1;
        };
        struct {
            __IO  uint16_t  CLK0                 :1;
            __IO  uint16_t  CLK1                 :1;
            __IO  uint16_t  CLK2                 :1;
            __IO  uint16_t  CLK3                 :1;
            __IO  uint16_t  RESERVED1            :12;
        };
    };
} stc_mft_frt_tcsa0_field_t;

typedef struct stc_mft_frt_tcsc0_field
{
    union {
        struct {
            __IO  uint16_t  MSZI                 :4;
            __IO  uint16_t  MSPI                 :4;
            __IO  uint16_t  MSZC                 :4;
            __IO  uint16_t  MSPC                 :4;
        };
        struct {
            __IO  uint16_t  MSZI0                :1;
            __IO  uint16_t  MSZI1                :1;
            __IO  uint16_t  MSZI2                :1;
            __IO  uint16_t  MSZI3                :1;
            __IO  uint16_t  MSPI0                :1;
            __IO  uint16_t  MSPI1                :1;
            __IO  uint16_t  MSPI2                :1;
            __IO  uint16_t  MSPI3                :1;
            __IO  uint16_t  MSZC0                :1;
            __IO  uint16_t  MSZC1                :1;
            __IO  uint16_t  MSZC2                :1;
            __IO  uint16_t  MSZC3                :1;
            __IO  uint16_t  MSPC0                :1;
            __IO  uint16_t  MSPC1                :1;
            __IO  uint16_t  MSPC2                :1;
            __IO  uint16_t  MSPC3                :1;
        };
    };
} stc_mft_frt_tcsc0_field_t;

typedef struct stc_mft_frt_tccp1_field
{
    union {
        struct {
            __IO  uint16_t  TCCP                 :16;
        };
        struct {
            __IO  uint16_t  TCCP0                :1;
            __IO  uint16_t  TCCP1                :1;
            __IO  uint16_t  TCCP2                :1;
            __IO  uint16_t  TCCP3                :1;
            __IO  uint16_t  TCCP4                :1;
            __IO  uint16_t  TCCP5                :1;
            __IO  uint16_t  TCCP6                :1;
            __IO  uint16_t  TCCP7                :1;
            __IO  uint16_t  TCCP8                :1;
            __IO  uint16_t  TCCP9                :1;
            __IO  uint16_t  TCCP10               :1;
            __IO  uint16_t  TCCP11               :1;
            __IO  uint16_t  TCCP12               :1;
            __IO  uint16_t  TCCP13               :1;
            __IO  uint16_t  TCCP14               :1;
            __IO  uint16_t  TCCP15               :1;
        };
    };
} stc_mft_frt_tccp1_field_t;

typedef struct stc_mft_frt_tcsa1_field
{
    union {
        struct {
            __IO  uint16_t  CLK                  :4;
            __IO  uint16_t  SCLR                 :1;
            __IO  uint16_t  MODE                 :1;
            __IO  uint16_t  STOP                 :1;
            __IO  uint16_t  BFE                  :1;
            __IO  uint16_t  ICRE                 :1;
            __IO  uint16_t  ICLR                 :1;
            __IO  uint16_t  RESERVED0            :3;
            __IO  uint16_t  IRQZE                :1;
            __IO  uint16_t  IRQZF                :1;
            __IO  uint16_t  ECKE                 :1;
        };
        struct {
            __IO  uint16_t  CLK0                 :1;
            __IO  uint16_t  CLK1                 :1;
            __IO  uint16_t  CLK2                 :1;
            __IO  uint16_t  CLK3                 :1;
            __IO  uint16_t  RESERVED1            :12;
        };
    };
} stc_mft_frt_tcsa1_field_t;

typedef struct stc_mft_frt_tcsc1_field
{
    union {
        struct {
            __IO  uint16_t  MSZI                 :4;
            __IO  uint16_t  MSPI                 :4;
            __IO  uint16_t  MSZC                 :4;
            __IO  uint16_t  MSPC                 :4;
        };
        struct {
            __IO  uint16_t  MSZI0                :1;
            __IO  uint16_t  MSZI1                :1;
            __IO  uint16_t  MSZI2                :1;
            __IO  uint16_t  MSZI3                :1;
            __IO  uint16_t  MSPI0                :1;
            __IO  uint16_t  MSPI1                :1;
            __IO  uint16_t  MSPI2                :1;
            __IO  uint16_t  MSPI3                :1;
            __IO  uint16_t  MSZC0                :1;
            __IO  uint16_t  MSZC1                :1;
            __IO  uint16_t  MSZC2                :1;
            __IO  uint16_t  MSZC3                :1;
            __IO  uint16_t  MSPC0                :1;
            __IO  uint16_t  MSPC1                :1;
            __IO  uint16_t  MSPC2                :1;
            __IO  uint16_t  MSPC3                :1;
        };
    };
} stc_mft_frt_tcsc1_field_t;

typedef struct stc_mft_frt_tccp2_field
{
    union {
        struct {
            __IO  uint16_t  TCCP                 :16;
        };
        struct {
            __IO  uint16_t  TCCP0                :1;
            __IO  uint16_t  TCCP1                :1;
            __IO  uint16_t  TCCP2                :1;
            __IO  uint16_t  TCCP3                :1;
            __IO  uint16_t  TCCP4                :1;
            __IO  uint16_t  TCCP5                :1;
            __IO  uint16_t  TCCP6                :1;
            __IO  uint16_t  TCCP7                :1;
            __IO  uint16_t  TCCP8                :1;
            __IO  uint16_t  TCCP9                :1;
            __IO  uint16_t  TCCP10               :1;
            __IO  uint16_t  TCCP11               :1;
            __IO  uint16_t  TCCP12               :1;
            __IO  uint16_t  TCCP13               :1;
            __IO  uint16_t  TCCP14               :1;
            __IO  uint16_t  TCCP15               :1;
        };
    };
} stc_mft_frt_tccp2_field_t;

typedef struct stc_mft_frt_tcsa2_field
{
    union {
        struct {
            __IO  uint16_t  CLK                  :4;
            __IO  uint16_t  SCLR                 :1;
            __IO  uint16_t  MODE                 :1;
            __IO  uint16_t  STOP                 :1;
            __IO  uint16_t  BFE                  :1;
            __IO  uint16_t  ICRE                 :1;
            __IO  uint16_t  ICLR                 :1;
            __IO  uint16_t  RESERVED0            :3;
            __IO  uint16_t  IRQZE                :1;
            __IO  uint16_t  IRQZF                :1;
            __IO  uint16_t  ECKE                 :1;
        };
        struct {
            __IO  uint16_t  CLK0                 :1;
            __IO  uint16_t  CLK1                 :1;
            __IO  uint16_t  CLK2                 :1;
            __IO  uint16_t  CLK3                 :1;
            __IO  uint16_t  RESERVED1            :12;
        };
    };
} stc_mft_frt_tcsa2_field_t;

typedef struct stc_mft_frt_tcsc2_field
{
    union {
        struct {
            __IO  uint16_t  MSZI                 :4;
            __IO  uint16_t  MSPI                 :4;
            __IO  uint16_t  MSZC                 :4;
            __IO  uint16_t  MSPC                 :4;
        };
        struct {
            __IO  uint16_t  MSZI0                :1;
            __IO  uint16_t  MSZI1                :1;
            __IO  uint16_t  MSZI2                :1;
            __IO  uint16_t  MSZI3                :1;
            __IO  uint16_t  MSPI0                :1;
            __IO  uint16_t  MSPI1                :1;
            __IO  uint16_t  MSPI2                :1;
            __IO  uint16_t  MSPI3                :1;
            __IO  uint16_t  MSZC0                :1;
            __IO  uint16_t  MSZC1                :1;
            __IO  uint16_t  MSZC2                :1;
            __IO  uint16_t  MSZC3                :1;
            __IO  uint16_t  MSPC0                :1;
            __IO  uint16_t  MSPC1                :1;
            __IO  uint16_t  MSPC2                :1;
            __IO  uint16_t  MSPC3                :1;
        };
    };
} stc_mft_frt_tcsc2_field_t;

typedef struct stc_mft_frt_tcal_field
{
        __IO  uint32_t  STOP00                   :1;
        __IO  uint32_t  STOP01                   :1;
        __IO  uint32_t  STOP02                   :1;
        __IO  uint32_t  STOP10                   :1;
        __IO  uint32_t  STOP11                   :1;
        __IO  uint32_t  STOP12                   :1;
        __IO  uint32_t  STOP20                   :1;
        __IO  uint32_t  STOP21                   :1;
        __IO  uint32_t  STOP22                   :1;
        __IO  uint32_t  RESERVED0                :7;
        __IO  uint32_t  SCLR00                   :1;
        __IO  uint32_t  SCLR01                   :1;
        __IO  uint32_t  SCLR02                   :1;
        __IO  uint32_t  SCLR10                   :1;
        __IO  uint32_t  SCLR11                   :1;
        __IO  uint32_t  SCLR12                   :1;
        __IO  uint32_t  SCLR20                   :1;
        __IO  uint32_t  SCLR21                   :1;
        __IO  uint32_t  SCLR22                   :1;
        __IO  uint32_t  RESERVED1                :7;
} stc_mft_frt_tcal_field_t;

typedef struct stc_mft_ocu_ocfs10_field
{
    union {
        struct {
            __IO   uint8_t  FSO0                 :4;
            __IO   uint8_t  FSO1                 :4;
        };
        struct {
            __IO   uint8_t  FSO00                :1;
            __IO   uint8_t  FSO01                :1;
            __IO   uint8_t  FSO02                :1;
            __IO   uint8_t  FSO03                :1;
            __IO   uint8_t  FSO10                :1;
            __IO   uint8_t  FSO11                :1;
            __IO   uint8_t  FSO12                :1;
            __IO   uint8_t  FSO13                :1;
        };
    };
} stc_mft_ocu_ocfs10_field_t;

typedef struct stc_mft_ocu_ocfs32_field
{
    union {
        struct {
            __IO   uint8_t  FSO2                 :4;
            __IO   uint8_t  FSO3                 :4;
        };
        struct {
            __IO   uint8_t  FSO20                :1;
            __IO   uint8_t  FSO21                :1;
            __IO   uint8_t  FSO22                :1;
            __IO   uint8_t  FSO23                :1;
            __IO   uint8_t  FSO30                :1;
            __IO   uint8_t  FSO31                :1;
            __IO   uint8_t  FSO32                :1;
            __IO   uint8_t  FSO33                :1;
        };
    };
} stc_mft_ocu_ocfs32_field_t;

typedef struct stc_mft_ocu_ocfs54_field
{
    union {
        struct {
            __IO   uint8_t  FSO4                 :4;
            __IO   uint8_t  FSO5                 :4;
        };
        struct {
            __IO   uint8_t  FSO40                :1;
            __IO   uint8_t  FSO41                :1;
            __IO   uint8_t  FSO42                :1;
            __IO   uint8_t  FSO43                :1;
            __IO   uint8_t  FSO50                :1;
            __IO   uint8_t  FSO51                :1;
            __IO   uint8_t  FSO52                :1;
            __IO   uint8_t  FSO53                :1;
        };
    };
} stc_mft_ocu_ocfs54_field_t;

typedef struct stc_mft_icu_icfs10_field
{
    union {
        struct {
            __IO   uint8_t  FSI0                 :4;
            __IO   uint8_t  FSI1                 :4;
        };
        struct {
            __IO   uint8_t  FSI00                :1;
            __IO   uint8_t  FSI01                :1;
            __IO   uint8_t  FSI02                :1;
            __IO   uint8_t  FSI03                :1;
            __IO   uint8_t  FSI10                :1;
            __IO   uint8_t  FSI11                :1;
            __IO   uint8_t  FSI12                :1;
            __IO   uint8_t  FSI13                :1;
        };
    };
} stc_mft_icu_icfs10_field_t;

typedef struct stc_mft_icu_icfs32_field
{
    union {
        struct {
            __IO   uint8_t  FSI2                 :4;
            __IO   uint8_t  FSI3                 :4;
        };
        struct {
            __IO   uint8_t  FSI20                :1;
            __IO   uint8_t  FSI21                :1;
            __IO   uint8_t  FSI22                :1;
            __IO   uint8_t  FSI23                :1;
            __IO   uint8_t  FSI30                :1;
            __IO   uint8_t  FSI31                :1;
            __IO   uint8_t  FSI32                :1;
            __IO   uint8_t  FSI33                :1;
        };
    };
} stc_mft_icu_icfs32_field_t;

typedef struct stc_mft_adcmp_acfs10_field
{
    union {
        struct {
            __IO   uint8_t  FSA0                 :4;
            __IO   uint8_t  FSA1                 :4;
        };
        struct {
            __IO   uint8_t  FSA00                :1;
            __IO   uint8_t  FSA01                :1;
            __IO   uint8_t  FSA02                :1;
            __IO   uint8_t  FSA03                :1;
            __IO   uint8_t  FSA10                :1;
            __IO   uint8_t  FSA11                :1;
            __IO   uint8_t  FSA12                :1;
            __IO   uint8_t  FSA13                :1;
        };
    };
} stc_mft_adcmp_acfs10_field_t;

typedef struct stc_mft_adcmp_acfs32_field
{
    union {
        struct {
            __IO   uint8_t  FSA2                 :4;
            __IO   uint8_t  FSA3                 :4;
        };
        struct {
            __IO   uint8_t  FSA20                :1;
            __IO   uint8_t  FSA21                :1;
            __IO   uint8_t  FSA22                :1;
            __IO   uint8_t  FSA23                :1;
            __IO   uint8_t  FSA30                :1;
            __IO   uint8_t  FSA31                :1;
            __IO   uint8_t  FSA32                :1;
            __IO   uint8_t  FSA33                :1;
        };
    };
} stc_mft_adcmp_acfs32_field_t;

typedef struct stc_mft_adcmp_acfs54_field
{
    union {
        struct {
            __IO   uint8_t  FSA4                 :4;
            __IO   uint8_t  FSA5                 :4;
        };
        struct {
            __IO   uint8_t  FSA40                :1;
            __IO   uint8_t  FSA41                :1;
            __IO   uint8_t  FSA42                :1;
            __IO   uint8_t  FSA43                :1;
            __IO   uint8_t  FSA50                :1;
            __IO   uint8_t  FSA51                :1;
            __IO   uint8_t  FSA52                :1;
            __IO   uint8_t  FSA53                :1;
        };
    };
} stc_mft_adcmp_acfs54_field_t;

typedef struct stc_mft_icu_icsa10_field
{
    union {
        struct {
            __IO   uint8_t  EG0                  :2;
            __IO   uint8_t  EG1                  :2;
            __IO   uint8_t  ICE0                 :1;
            __IO   uint8_t  ICE1                 :1;
            __IO   uint8_t  ICP0                 :1;
            __IO   uint8_t  ICP1                 :1;
        };
        struct {
            __IO   uint8_t  EG00                 :1;
            __IO   uint8_t  EG01                 :1;
            __IO   uint8_t  EG10                 :1;
            __IO   uint8_t  EG11                 :1;
            __IO   uint8_t  RESERVED0            :4;
        };
    };
} stc_mft_icu_icsa10_field_t;

typedef struct stc_mft_icu_icsb10_field
{
        __IO   uint8_t  IEI0                     :1;
        __IO   uint8_t  IEI1                     :1;
        __IO   uint8_t  RESERVED0                :6;
} stc_mft_icu_icsb10_field_t;

typedef struct stc_mft_icu_icsa32_field
{
    union {
        struct {
            __IO   uint8_t  EG2                  :2;
            __IO   uint8_t  EG3                  :2;
            __IO   uint8_t  ICE2                 :1;
            __IO   uint8_t  ICE3                 :1;
            __IO   uint8_t  ICP2                 :1;
            __IO   uint8_t  ICP3                 :1;
        };
        struct {
            __IO   uint8_t  EG20                 :1;
            __IO   uint8_t  EG21                 :1;
            __IO   uint8_t  EG30                 :1;
            __IO   uint8_t  EG31                 :1;
            __IO   uint8_t  RESERVED0            :4;
        };
    };
} stc_mft_icu_icsa32_field_t;

typedef struct stc_mft_icu_icsb32_field
{
        __IO   uint8_t  IEI2                     :1;
        __IO   uint8_t  IEI3                     :1;
        __IO   uint8_t  RESERVED0                :6;
} stc_mft_icu_icsb32_field_t;

typedef struct stc_mft_wfg_wfsa10_field
{
    union {
        struct {
            __IO  uint16_t  DCK                  :3;
            __IO  uint16_t  TMD                  :3;
            __IO  uint16_t  GTEN                 :2;
            __IO  uint16_t  PSEL                 :2;
            __IO  uint16_t  PGEN                 :2;
            __IO  uint16_t  DMOD                 :2;
            __IO  uint16_t  RESERVED0            :2;
        };
        struct {
            __IO  uint16_t  DCK0                 :1;
            __IO  uint16_t  DCK1                 :1;
            __IO  uint16_t  DCK2                 :1;
            __IO  uint16_t  TMD0                 :1;
            __IO  uint16_t  TMD1                 :1;
            __IO  uint16_t  TMD2                 :1;
            __IO  uint16_t  GTEN0                :1;
            __IO  uint16_t  GTEN1                :1;
            __IO  uint16_t  PSEL0                :1;
            __IO  uint16_t  PSEL1                :1;
            __IO  uint16_t  PGEN0                :1;
            __IO  uint16_t  PGEN1                :1;
            __IO  uint16_t  DMOD0                :1;
            __IO  uint16_t  DMOD1                :1;
            __IO  uint16_t  RESERVED1            :2;
        };
    };
} stc_mft_wfg_wfsa10_field_t;

typedef struct stc_mft_wfg_wfsa32_field
{
    union {
        struct {
            __IO  uint16_t  DCK                  :3;
            __IO  uint16_t  TMD                  :3;
            __IO  uint16_t  GTEN                 :2;
            __IO  uint16_t  PSEL                 :2;
            __IO  uint16_t  PGEN                 :2;
            __IO  uint16_t  DMOD                 :2;
            __IO  uint16_t  RESERVED0            :2;
        };
        struct {
            __IO  uint16_t  DCK0                 :1;
            __IO  uint16_t  DCK1                 :1;
            __IO  uint16_t  DCK2                 :1;
            __IO  uint16_t  TMD0                 :1;
            __IO  uint16_t  TMD1                 :1;
            __IO  uint16_t  TMD2                 :1;
            __IO  uint16_t  GTEN0                :1;
            __IO  uint16_t  GTEN1                :1;
            __IO  uint16_t  PSEL0                :1;
            __IO  uint16_t  PSEL1                :1;
            __IO  uint16_t  PGEN0                :1;
            __IO  uint16_t  PGEN1                :1;
            __IO  uint16_t  DMOD0                :1;
            __IO  uint16_t  DMOD1                :1;
            __IO  uint16_t  RESERVED1            :2;
        };
    };
} stc_mft_wfg_wfsa32_field_t;

typedef struct stc_mft_wfg_wfsa54_field
{
    union {
        struct {
            __IO  uint16_t  DCK                  :3;
            __IO  uint16_t  TMD                  :3;
            __IO  uint16_t  GTEN                 :2;
            __IO  uint16_t  PSEL                 :2;
            __IO  uint16_t  PGEN                 :2;
            __IO  uint16_t  DMOD                 :2;
            __IO  uint16_t  RESERVED0            :2;
        };
        struct {
            __IO  uint16_t  DCK0                 :1;
            __IO  uint16_t  DCK1                 :1;
            __IO  uint16_t  DCK2                 :1;
            __IO  uint16_t  TMD0                 :1;
            __IO  uint16_t  TMD1                 :1;
            __IO  uint16_t  TMD2                 :1;
            __IO  uint16_t  GTEN0                :1;
            __IO  uint16_t  GTEN1                :1;
            __IO  uint16_t  PSEL0                :1;
            __IO  uint16_t  PSEL1                :1;
            __IO  uint16_t  PGEN0                :1;
            __IO  uint16_t  PGEN1                :1;
            __IO  uint16_t  DMOD0                :1;
            __IO  uint16_t  DMOD1                :1;
            __IO  uint16_t  RESERVED1            :2;
        };
    };
} stc_mft_wfg_wfsa54_field_t;

typedef struct stc_mft_wfg_wfir_field
{
        __IO  uint16_t  DTIFA                    :1;
        __IO  uint16_t  DTICA                    :1;
        __IO  uint16_t  DTIFB                    :1;
        __IO  uint16_t  DTICB                    :1;
        __IO  uint16_t  TMIF10                   :1;
        __IO  uint16_t  TMIC10                   :1;
        __IO  uint16_t  TMIE10                   :1;
        __IO  uint16_t  TMIS10                   :1;
        __IO  uint16_t  TMIF32                   :1;
        __IO  uint16_t  TMIC32                   :1;
        __IO  uint16_t  TMIE32                   :1;
        __IO  uint16_t  TMIS32                   :1;
        __IO  uint16_t  TMIF54                   :1;
        __IO  uint16_t  TMIC54                   :1;
        __IO  uint16_t  TMIE54                   :1;
        __IO  uint16_t  TMIS54                   :1;
} stc_mft_wfg_wfir_field_t;

typedef struct stc_mft_wfg_nzcl_field
{
    union {
        struct {
            __IO  uint16_t  DTIEA                :1;
            __IO  uint16_t  NWS                  :3;
            __IO  uint16_t  SDTI                 :1;
            __IO  uint16_t  DTIEB                :1;
            __IO  uint16_t  RESERVED1            :1;
            __IO  uint16_t  DHOLD                :1;
            __IO  uint16_t  DIMA                 :1;
            __IO  uint16_t  DIMB                 :1;
            __IO  uint16_t  RESERVED2            :2;
            __IO  uint16_t  WIM10                :1;
            __IO  uint16_t  WIM32                :1;
            __IO  uint16_t  WIM54                :1;
            __IO  uint16_t  RESERVED3            :1;
        };
        struct {
            __IO  uint16_t  RESERVED0            :1;
            __IO  uint16_t  NWS0                 :1;
            __IO  uint16_t  NWS1                 :1;
            __IO  uint16_t  NWS2                 :1;
            __IO  uint16_t  RESERVED4            :12;
        };
    };
} stc_mft_wfg_nzcl_field_t;

typedef struct stc_mft_adcmp_acmp0_field
{
    union {
        struct {
            __IO  uint16_t  ACMP                 :16;
        };
        struct {
            __IO  uint16_t  ACMP0                :1;
            __IO  uint16_t  ACMP1                :1;
            __IO  uint16_t  ACMP2                :1;
            __IO  uint16_t  ACMP3                :1;
            __IO  uint16_t  ACMP4                :1;
            __IO  uint16_t  ACMP5                :1;
            __IO  uint16_t  ACMP6                :1;
            __IO  uint16_t  ACMP7                :1;
            __IO  uint16_t  ACMP8                :1;
            __IO  uint16_t  ACMP9                :1;
            __IO  uint16_t  ACMP10               :1;
            __IO  uint16_t  ACMP11               :1;
            __IO  uint16_t  ACMP12               :1;
            __IO  uint16_t  ACMP13               :1;
            __IO  uint16_t  ACMP14               :1;
            __IO  uint16_t  ACMP15               :1;
        };
    };
} stc_mft_adcmp_acmp0_field_t;

typedef struct stc_mft_adcmp_acmp1_field
{
    union {
        struct {
            __IO  uint16_t  ACMP                 :16;
        };
        struct {
            __IO  uint16_t  ACMP0                :1;
            __IO  uint16_t  ACMP1                :1;
            __IO  uint16_t  ACMP2                :1;
            __IO  uint16_t  ACMP3                :1;
            __IO  uint16_t  ACMP4                :1;
            __IO  uint16_t  ACMP5                :1;
            __IO  uint16_t  ACMP6                :1;
            __IO  uint16_t  ACMP7                :1;
            __IO  uint16_t  ACMP8                :1;
            __IO  uint16_t  ACMP9                :1;
            __IO  uint16_t  ACMP10               :1;
            __IO  uint16_t  ACMP11               :1;
            __IO  uint16_t  ACMP12               :1;
            __IO  uint16_t  ACMP13               :1;
            __IO  uint16_t  ACMP14               :1;
            __IO  uint16_t  ACMP15               :1;
        };
    };
} stc_mft_adcmp_acmp1_field_t;

typedef struct stc_mft_adcmp_acmp2_field
{
    union {
        struct {
            __IO  uint16_t  ACMP                 :16;
        };
        struct {
            __IO  uint16_t  ACMP0                :1;
            __IO  uint16_t  ACMP1                :1;
            __IO  uint16_t  ACMP2                :1;
            __IO  uint16_t  ACMP3                :1;
            __IO  uint16_t  ACMP4                :1;
            __IO  uint16_t  ACMP5                :1;
            __IO  uint16_t  ACMP6                :1;
            __IO  uint16_t  ACMP7                :1;
            __IO  uint16_t  ACMP8                :1;
            __IO  uint16_t  ACMP9                :1;
            __IO  uint16_t  ACMP10               :1;
            __IO  uint16_t  ACMP11               :1;
            __IO  uint16_t  ACMP12               :1;
            __IO  uint16_t  ACMP13               :1;
            __IO  uint16_t  ACMP14               :1;
            __IO  uint16_t  ACMP15               :1;
        };
    };
} stc_mft_adcmp_acmp2_field_t;

typedef struct stc_mft_adcmp_acmp3_field
{
    union {
        struct {
            __IO  uint16_t  ACMP                 :16;
        };
        struct {
            __IO  uint16_t  ACMP0                :1;
            __IO  uint16_t  ACMP1                :1;
            __IO  uint16_t  ACMP2                :1;
            __IO  uint16_t  ACMP3                :1;
            __IO  uint16_t  ACMP4                :1;
            __IO  uint16_t  ACMP5                :1;
            __IO  uint16_t  ACMP6                :1;
            __IO  uint16_t  ACMP7                :1;
            __IO  uint16_t  ACMP8                :1;
            __IO  uint16_t  ACMP9                :1;
            __IO  uint16_t  ACMP10               :1;
            __IO  uint16_t  ACMP11               :1;
            __IO  uint16_t  ACMP12               :1;
            __IO  uint16_t  ACMP13               :1;
            __IO  uint16_t  ACMP14               :1;
            __IO  uint16_t  ACMP15               :1;
        };
    };
} stc_mft_adcmp_acmp3_field_t;

typedef struct stc_mft_adcmp_acmp4_field
{
    union {
        struct {
            __IO  uint16_t  ACMP                 :16;
        };
        struct {
            __IO  uint16_t  ACMP0                :1;
            __IO  uint16_t  ACMP1                :1;
            __IO  uint16_t  ACMP2                :1;
            __IO  uint16_t  ACMP3                :1;
            __IO  uint16_t  ACMP4                :1;
            __IO  uint16_t  ACMP5                :1;
            __IO  uint16_t  ACMP6                :1;
            __IO  uint16_t  ACMP7                :1;
            __IO  uint16_t  ACMP8                :1;
            __IO  uint16_t  ACMP9                :1;
            __IO  uint16_t  ACMP10               :1;
            __IO  uint16_t  ACMP11               :1;
            __IO  uint16_t  ACMP12               :1;
            __IO  uint16_t  ACMP13               :1;
            __IO  uint16_t  ACMP14               :1;
            __IO  uint16_t  ACMP15               :1;
        };
    };
} stc_mft_adcmp_acmp4_field_t;

typedef struct stc_mft_adcmp_acmp5_field
{
    union {
        struct {
            __IO  uint16_t  ACMP                 :16;
        };
        struct {
            __IO  uint16_t  ACMP0                :1;
            __IO  uint16_t  ACMP1                :1;
            __IO  uint16_t  ACMP2                :1;
            __IO  uint16_t  ACMP3                :1;
            __IO  uint16_t  ACMP4                :1;
            __IO  uint16_t  ACMP5                :1;
            __IO  uint16_t  ACMP6                :1;
            __IO  uint16_t  ACMP7                :1;
            __IO  uint16_t  ACMP8                :1;
            __IO  uint16_t  ACMP9                :1;
            __IO  uint16_t  ACMP10               :1;
            __IO  uint16_t  ACMP11               :1;
            __IO  uint16_t  ACMP12               :1;
            __IO  uint16_t  ACMP13               :1;
            __IO  uint16_t  ACMP14               :1;
            __IO  uint16_t  ACMP15               :1;
        };
    };
} stc_mft_adcmp_acmp5_field_t;

typedef struct stc_mft_adcmp_acsa_field
{
    union {
        struct {
            __IO  uint16_t  CE10                 :2;
            __IO  uint16_t  CE32                 :2;
            __IO  uint16_t  CE54                 :2;
            __IO  uint16_t  RESERVED0            :2;
            __IO  uint16_t  SEL10                :2;
            __IO  uint16_t  SEL32                :2;
            __IO  uint16_t  SEL54                :2;
            __IO  uint16_t  RESERVED2            :2;
        };
        struct {
            __IO  uint16_t  CE100                :1;
            __IO  uint16_t  CE101                :1;
            __IO  uint16_t  CE320                :1;
            __IO  uint16_t  CE321                :1;
            __IO  uint16_t  CE540                :1;
            __IO  uint16_t  CE541                :1;
            __IO  uint16_t  RESERVED1            :2;
            __IO  uint16_t  SEL100               :1;
            __IO  uint16_t  SEL101               :1;
            __IO  uint16_t  SEL320               :1;
            __IO  uint16_t  SEL321               :1;
            __IO  uint16_t  SEL540               :1;
            __IO  uint16_t  SEL541               :1;
            __IO  uint16_t  RESERVED3            :2;
        };
    };
} stc_mft_adcmp_acsa_field_t;

typedef struct stc_mft_adcmp_acsc0_field
{
    union {
        struct {
            __IO   uint8_t  BUFE                 :2;
            __IO   uint8_t  ADSEL                :3;
            __IO   uint8_t  APBM                 :1;
            __IO   uint8_t  RESERVED0            :2;
        };
        struct {
            __IO   uint8_t  BUFE0                :1;
            __IO   uint8_t  BUFE1                :1;
            __IO   uint8_t  ADSEL0               :1;
            __IO   uint8_t  ADSEL1               :1;
            __IO   uint8_t  ADSEL2               :1;
            __IO   uint8_t  RESERVED1            :3;
        };
    };
} stc_mft_adcmp_acsc0_field_t;

typedef struct stc_mft_adcmp_acsd0_field
{
        __IO   uint8_t  AMOD                     :1;
        __IO   uint8_t  OCUS                     :1;
        __IO   uint8_t  RESERVED0                :2;
        __IO   uint8_t  DE                       :1;
        __IO   uint8_t  PE                       :1;
        __IO   uint8_t  UE                       :1;
        __IO   uint8_t  ZE                       :1;
} stc_mft_adcmp_acsd0_field_t;

typedef struct stc_mft_adcmp_acmc0_field
{
    union {
        struct {
            __IO   uint8_t  AMC                  :4;
            __IO   uint8_t  RESERVED0            :2;
            __IO   uint8_t  MZCE                 :1;
            __IO   uint8_t  MPCE                 :1;
        };
        struct {
            __IO   uint8_t  AMC0                 :1;
            __IO   uint8_t  AMC1                 :1;
            __IO   uint8_t  AMC2                 :1;
            __IO   uint8_t  AMC3                 :1;
            __IO   uint8_t  RESERVED1            :4;
        };
    };
} stc_mft_adcmp_acmc0_field_t;

typedef struct stc_mft_adcmp_acsc1_field
{
    union {
        struct {
            __IO   uint8_t  BUFE                 :2;
            __IO   uint8_t  ADSEL                :3;
            __IO   uint8_t  APBM                 :1;
            __IO   uint8_t  RESERVED0            :2;
        };
        struct {
            __IO   uint8_t  BUFE0                :1;
            __IO   uint8_t  BUFE1                :1;
            __IO   uint8_t  ADSEL0               :1;
            __IO   uint8_t  ADSEL1               :1;
            __IO   uint8_t  ADSEL2               :1;
            __IO   uint8_t  RESERVED1            :3;
        };
    };
} stc_mft_adcmp_acsc1_field_t;

typedef struct stc_mft_adcmp_acsd1_field
{
        __IO   uint8_t  AMOD                     :1;
        __IO   uint8_t  OCUS                     :1;
        __IO   uint8_t  RESERVED0                :2;
        __IO   uint8_t  DE                       :1;
        __IO   uint8_t  PE                       :1;
        __IO   uint8_t  UE                       :1;
        __IO   uint8_t  ZE                       :1;
} stc_mft_adcmp_acsd1_field_t;

typedef struct stc_mft_adcmp_acmc1_field
{
    union {
        struct {
            __IO   uint8_t  AMC                  :4;
            __IO   uint8_t  RESERVED0            :2;
            __IO   uint8_t  MZCE                 :1;
            __IO   uint8_t  MPCE                 :1;
        };
        struct {
            __IO   uint8_t  AMC0                 :1;
            __IO   uint8_t  AMC1                 :1;
            __IO   uint8_t  AMC2                 :1;
            __IO   uint8_t  AMC3                 :1;
            __IO   uint8_t  RESERVED1            :4;
        };
    };
} stc_mft_adcmp_acmc1_field_t;

typedef struct stc_mft_adcmp_acsc2_field
{
    union {
        struct {
            __IO   uint8_t  BUFE                 :2;
            __IO   uint8_t  ADSEL                :3;
            __IO   uint8_t  APBM                 :1;
            __IO   uint8_t  RESERVED0            :2;
        };
        struct {
            __IO   uint8_t  BUFE0                :1;
            __IO   uint8_t  BUFE1                :1;
            __IO   uint8_t  ADSEL0               :1;
            __IO   uint8_t  ADSEL1               :1;
            __IO   uint8_t  ADSEL2               :1;
            __IO   uint8_t  RESERVED1            :3;
        };
    };
} stc_mft_adcmp_acsc2_field_t;

typedef struct stc_mft_adcmp_acsd2_field
{
        __IO   uint8_t  AMOD                     :1;
        __IO   uint8_t  OCUS                     :1;
        __IO   uint8_t  RESERVED0                :2;
        __IO   uint8_t  DE                       :1;
        __IO   uint8_t  PE                       :1;
        __IO   uint8_t  UE                       :1;
        __IO   uint8_t  ZE                       :1;
} stc_mft_adcmp_acsd2_field_t;

typedef struct stc_mft_adcmp_acmc2_field
{
    union {
        struct {
            __IO   uint8_t  AMC                  :4;
            __IO   uint8_t  RESERVED0            :2;
            __IO   uint8_t  MZCE                 :1;
            __IO   uint8_t  MPCE                 :1;
        };
        struct {
            __IO   uint8_t  AMC0                 :1;
            __IO   uint8_t  AMC1                 :1;
            __IO   uint8_t  AMC2                 :1;
            __IO   uint8_t  AMC3                 :1;
            __IO   uint8_t  RESERVED1            :4;
        };
    };
} stc_mft_adcmp_acmc2_field_t;

typedef struct stc_mft_adcmp_acsc3_field
{
    union {
        struct {
            __IO   uint8_t  BUFE                 :2;
            __IO   uint8_t  ADSEL                :3;
            __IO   uint8_t  APBM                 :1;
            __IO   uint8_t  RESERVED0            :2;
        };
        struct {
            __IO   uint8_t  BUFE0                :1;
            __IO   uint8_t  BUFE1                :1;
            __IO   uint8_t  ADSEL0               :1;
            __IO   uint8_t  ADSEL1               :1;
            __IO   uint8_t  ADSEL2               :1;
            __IO   uint8_t  RESERVED1            :3;
        };
    };
} stc_mft_adcmp_acsc3_field_t;

typedef struct stc_mft_adcmp_acsd3_field
{
        __IO   uint8_t  AMOD                     :1;
        __IO   uint8_t  OCUS                     :1;
        __IO   uint8_t  RESERVED0                :2;
        __IO   uint8_t  DE                       :1;
        __IO   uint8_t  PE                       :1;
        __IO   uint8_t  UE                       :1;
        __IO   uint8_t  ZE                       :1;
} stc_mft_adcmp_acsd3_field_t;

typedef struct stc_mft_adcmp_acmc3_field
{
    union {
        struct {
            __IO   uint8_t  AMC                  :4;
            __IO   uint8_t  RESERVED0            :2;
            __IO   uint8_t  MZCE                 :1;
            __IO   uint8_t  MPCE                 :1;
        };
        struct {
            __IO   uint8_t  AMC0                 :1;
            __IO   uint8_t  AMC1                 :1;
            __IO   uint8_t  AMC2                 :1;
            __IO   uint8_t  AMC3                 :1;
            __IO   uint8_t  RESERVED1            :4;
        };
    };
} stc_mft_adcmp_acmc3_field_t;

typedef struct stc_mft_adcmp_acsc4_field
{
    union {
        struct {
            __IO   uint8_t  BUFE                 :2;
            __IO   uint8_t  ADSEL                :3;
            __IO   uint8_t  APBM                 :1;
            __IO   uint8_t  RESERVED0            :2;
        };
        struct {
            __IO   uint8_t  BUFE0                :1;
            __IO   uint8_t  BUFE1                :1;
            __IO   uint8_t  ADSEL0               :1;
            __IO   uint8_t  ADSEL1               :1;
            __IO   uint8_t  ADSEL2               :1;
            __IO   uint8_t  RESERVED1            :3;
        };
    };
} stc_mft_adcmp_acsc4_field_t;

typedef struct stc_mft_adcmp_acsd4_field
{
        __IO   uint8_t  AMOD                     :1;
        __IO   uint8_t  OCUS                     :1;
        __IO   uint8_t  RESERVED0                :2;
        __IO   uint8_t  DE                       :1;
        __IO   uint8_t  PE                       :1;
        __IO   uint8_t  UE                       :1;
        __IO   uint8_t  ZE                       :1;
} stc_mft_adcmp_acsd4_field_t;

typedef struct stc_mft_adcmp_acmc4_field
{
    union {
        struct {
            __IO   uint8_t  AMC                  :4;
            __IO   uint8_t  RESERVED0            :2;
            __IO   uint8_t  MZCE                 :1;
            __IO   uint8_t  MPCE                 :1;
        };
        struct {
            __IO   uint8_t  AMC0                 :1;
            __IO   uint8_t  AMC1                 :1;
            __IO   uint8_t  AMC2                 :1;
            __IO   uint8_t  AMC3                 :1;
            __IO   uint8_t  RESERVED1            :4;
        };
    };
} stc_mft_adcmp_acmc4_field_t;

typedef struct stc_mft_adcmp_acsc5_field
{
    union {
        struct {
            __IO   uint8_t  BUFE                 :2;
            __IO   uint8_t  ADSEL                :3;
            __IO   uint8_t  APBM                 :1;
            __IO   uint8_t  RESERVED0            :2;
        };
        struct {
            __IO   uint8_t  BUFE0                :1;
            __IO   uint8_t  BUFE1                :1;
            __IO   uint8_t  ADSEL0               :1;
            __IO   uint8_t  ADSEL1               :1;
            __IO   uint8_t  ADSEL2               :1;
            __IO   uint8_t  RESERVED1            :3;
        };
    };
} stc_mft_adcmp_acsc5_field_t;

typedef struct stc_mft_adcmp_acsd5_field
{
        __IO   uint8_t  AMOD                     :1;
        __IO   uint8_t  OCUS                     :1;
        __IO   uint8_t  RESERVED0                :2;
        __IO   uint8_t  DE                       :1;
        __IO   uint8_t  PE                       :1;
        __IO   uint8_t  UE                       :1;
        __IO   uint8_t  ZE                       :1;
} stc_mft_adcmp_acsd5_field_t;

typedef struct stc_mft_adcmp_acmc5_field
{
    union {
        struct {
            __IO   uint8_t  AMC                  :4;
            __IO   uint8_t  RESERVED0            :2;
            __IO   uint8_t  MZCE                 :1;
            __IO   uint8_t  MPCE                 :1;
        };
        struct {
            __IO   uint8_t  AMC0                 :1;
            __IO   uint8_t  AMC1                 :1;
            __IO   uint8_t  AMC2                 :1;
            __IO   uint8_t  AMC3                 :1;
            __IO   uint8_t  RESERVED1            :4;
        };
    };
} stc_mft_adcmp_acmc5_field_t;

typedef struct stc_mft_frt_tcsd_field
{
        __IO   uint8_t  OFMD1                    :1;
        __IO   uint8_t  OFMD2                    :1;
        __IO   uint8_t  RESERVED0                :6;
} stc_mft_frt_tcsd_field_t;

/*******************************************************************************
* MFT_PPG_MODULE
*******************************************************************************/
typedef struct stc_mft_ppg_ttcr0_field
{
    union {
        struct {
            __IO   uint8_t  STR0                 :1;
            __IO   uint8_t  MONI0                :1;
            __IO   uint8_t  CS0                  :2;
            __IO   uint8_t  TRG0O                :1;
            __IO   uint8_t  TRG2O                :1;
            __IO   uint8_t  TRG4O                :1;
            __IO   uint8_t  TRG6O                :1;
        };
        struct {
            __IO   uint8_t  RESERVED0            :2;
            __IO   uint8_t  CS00                 :1;
            __IO   uint8_t  CS01                 :1;
            __IO   uint8_t  RESERVED1            :4;
        };
    };
} stc_mft_ppg_ttcr0_field_t;

typedef struct stc_mft_ppg_ttcr1_field
{
    union {
        struct {
            __IO   uint8_t  STR1                 :1;
            __IO   uint8_t  MONI1                :1;
            __IO   uint8_t  CS1                  :2;
            __IO   uint8_t  TRG1O                :1;
            __IO   uint8_t  TRG3O                :1;
            __IO   uint8_t  TRG5O                :1;
            __IO   uint8_t  TRG7O                :1;
        };
        struct {
            __IO   uint8_t  RESERVED0            :2;
            __IO   uint8_t  CS10                 :1;
            __IO   uint8_t  CS11                 :1;
            __IO   uint8_t  RESERVED1            :4;
        };
    };
} stc_mft_ppg_ttcr1_field_t;

typedef struct stc_mft_ppg_ttcr2_field
{
    union {
        struct {
            __IO   uint8_t  STR2                 :1;
            __IO   uint8_t  MONI2                :1;
            __IO   uint8_t  CS2                  :2;
            __IO   uint8_t  TRG16O               :1;
            __IO   uint8_t  TRG18O               :1;
            __IO   uint8_t  TRG20O               :1;
            __IO   uint8_t  TRG22O               :1;
        };
        struct {
            __IO   uint8_t  RESERVED0            :2;
            __IO   uint8_t  CS20                 :1;
            __IO   uint8_t  CS21                 :1;
            __IO   uint8_t  RESERVED1            :4;
        };
    };
} stc_mft_ppg_ttcr2_field_t;

typedef struct stc_mft_ppg_trg0_field
{
        __IO  uint16_t  PEN00                    :1;
        __IO  uint16_t  PEN01                    :1;
        __IO  uint16_t  PEN02                    :1;
        __IO  uint16_t  PEN03                    :1;
        __IO  uint16_t  PEN04                    :1;
        __IO  uint16_t  PEN05                    :1;
        __IO  uint16_t  PEN06                    :1;
        __IO  uint16_t  PEN07                    :1;
        __IO  uint16_t  PEN08                    :1;
        __IO  uint16_t  PEN09                    :1;
        __IO  uint16_t  PEN10                    :1;
        __IO  uint16_t  PEN11                    :1;
        __IO  uint16_t  PEN12                    :1;
        __IO  uint16_t  PEN13                    :1;
        __IO  uint16_t  PEN14                    :1;
        __IO  uint16_t  PEN15                    :1;
} stc_mft_ppg_trg0_field_t;

typedef struct stc_mft_ppg_revc0_field
{
        __IO  uint16_t  REV00                    :1;
        __IO  uint16_t  REV01                    :1;
        __IO  uint16_t  REV02                    :1;
        __IO  uint16_t  REV03                    :1;
        __IO  uint16_t  REV04                    :1;
        __IO  uint16_t  REV05                    :1;
        __IO  uint16_t  REV06                    :1;
        __IO  uint16_t  REV07                    :1;
        __IO  uint16_t  REV08                    :1;
        __IO  uint16_t  REV09                    :1;
        __IO  uint16_t  REV10                    :1;
        __IO  uint16_t  REV11                    :1;
        __IO  uint16_t  REV12                    :1;
        __IO  uint16_t  REV13                    :1;
        __IO  uint16_t  REV14                    :1;
        __IO  uint16_t  REV15                    :1;
} stc_mft_ppg_revc0_field_t;

typedef struct stc_mft_ppg_trg1_field
{
        __IO  uint16_t  PEN16                    :1;
        __IO  uint16_t  PEN17                    :1;
        __IO  uint16_t  PEN18                    :1;
        __IO  uint16_t  PEN19                    :1;
        __IO  uint16_t  PEN20                    :1;
        __IO  uint16_t  PEN21                    :1;
        __IO  uint16_t  PEN22                    :1;
        __IO  uint16_t  PEN23                    :1;
        __IO  uint16_t  RESERVED0                :8;
} stc_mft_ppg_trg1_field_t;

typedef struct stc_mft_ppg_revc1_field
{
        __IO  uint16_t  REV16                    :1;
        __IO  uint16_t  REV17                    :1;
        __IO  uint16_t  REV18                    :1;
        __IO  uint16_t  REV19                    :1;
        __IO  uint16_t  REV20                    :1;
        __IO  uint16_t  REV21                    :1;
        __IO  uint16_t  REV22                    :1;
        __IO  uint16_t  REV23                    :1;
        __IO  uint16_t  RESERVED0                :8;
} stc_mft_ppg_revc1_field_t;

typedef struct stc_mft_ppg_ppgc1_field
{
    union {
        struct {
            __IO   uint8_t  RESERVED0            :3;
            __IO   uint8_t  PCS                  :2;
            __IO   uint8_t  INTM                 :1;
            __IO   uint8_t  PUF                  :1;
            __IO   uint8_t  PIE                  :1;
        };
        struct {
            __IO   uint8_t  RESERVED1            :3;
            __IO   uint8_t  PCS0                 :1;
            __IO   uint8_t  PCS1                 :1;
            __IO   uint8_t  RESERVED2            :3;
        };
    };
} stc_mft_ppg_ppgc1_field_t;

typedef struct stc_mft_ppg_ppgc0_field
{
    union {
        struct {
            __IO   uint8_t  TTRG                 :1;
            __IO   uint8_t  MD                   :2;
            __IO   uint8_t  PCS                  :2;
            __IO   uint8_t  INTM                 :1;
            __IO   uint8_t  PUF                  :1;
            __IO   uint8_t  PIE                  :1;
        };
        struct {
            __IO   uint8_t  RESERVED0            :1;
            __IO   uint8_t  MD0                  :1;
            __IO   uint8_t  MD1                  :1;
            __IO   uint8_t  PCS0                 :1;
            __IO   uint8_t  PCS1                 :1;
            __IO   uint8_t  RESERVED1            :3;
        };
    };
} stc_mft_ppg_ppgc0_field_t;

typedef struct stc_mft_ppg_ppgc3_field
{
    union {
        struct {
            __IO   uint8_t  RESERVED0            :3;
            __IO   uint8_t  PCS                  :2;
            __IO   uint8_t  INTM                 :1;
            __IO   uint8_t  PUF                  :1;
            __IO   uint8_t  PIE                  :1;
        };
        struct {
            __IO   uint8_t  RESERVED1            :3;
            __IO   uint8_t  PCS0                 :1;
            __IO   uint8_t  PCS1                 :1;
            __IO   uint8_t  RESERVED2            :3;
        };
    };
} stc_mft_ppg_ppgc3_field_t;

typedef struct stc_mft_ppg_ppgc2_field
{
    union {
        struct {
            __IO   uint8_t  TTRG                 :1;
            __IO   uint8_t  MD                   :2;
            __IO   uint8_t  PCS                  :2;
            __IO   uint8_t  INTM                 :1;
            __IO   uint8_t  PUF                  :1;
            __IO   uint8_t  PIE                  :1;
        };
        struct {
            __IO   uint8_t  RESERVED0            :1;
            __IO   uint8_t  MD0                  :1;
            __IO   uint8_t  MD1                  :1;
            __IO   uint8_t  PCS0                 :1;
            __IO   uint8_t  PCS1                 :1;
            __IO   uint8_t  RESERVED1            :3;
        };
    };
} stc_mft_ppg_ppgc2_field_t;

typedef struct stc_mft_ppg_prll0_field
{
    union {
        struct {
            __IO   uint8_t  PRLL                 :8;
        };
        struct {
            __IO   uint8_t  PRLL0                :1;
            __IO   uint8_t  PRLL1                :1;
            __IO   uint8_t  PRLL2                :1;
            __IO   uint8_t  PRLL3                :1;
            __IO   uint8_t  PRLL4                :1;
            __IO   uint8_t  PRLL5                :1;
            __IO   uint8_t  PRLL6                :1;
            __IO   uint8_t  PRLL7                :1;
        };
    };
} stc_mft_ppg_prll0_field_t;

typedef struct stc_mft_ppg_prlh0_field
{
    union {
        struct {
            __IO   uint8_t  PRLH                 :8;
        };
        struct {
            __IO   uint8_t  PRLH0                :1;
            __IO   uint8_t  PRLH1                :1;
            __IO   uint8_t  PRLH2                :1;
            __IO   uint8_t  PRLH3                :1;
            __IO   uint8_t  PRLH4                :1;
            __IO   uint8_t  PRLH5                :1;
            __IO   uint8_t  PRLH6                :1;
            __IO   uint8_t  PRLH7                :1;
        };
    };
} stc_mft_ppg_prlh0_field_t;

typedef struct stc_mft_ppg_prll1_field
{
    union {
        struct {
            __IO   uint8_t  PRLL                 :8;
        };
        struct {
            __IO   uint8_t  PRLL0                :1;
            __IO   uint8_t  PRLL1                :1;
            __IO   uint8_t  PRLL2                :1;
            __IO   uint8_t  PRLL3                :1;
            __IO   uint8_t  PRLL4                :1;
            __IO   uint8_t  PRLL5                :1;
            __IO   uint8_t  PRLL6                :1;
            __IO   uint8_t  PRLL7                :1;
        };
    };
} stc_mft_ppg_prll1_field_t;

typedef struct stc_mft_ppg_prlh1_field
{
    union {
        struct {
            __IO   uint8_t  PRLH                 :8;
        };
        struct {
            __IO   uint8_t  PRLH0                :1;
            __IO   uint8_t  PRLH1                :1;
            __IO   uint8_t  PRLH2                :1;
            __IO   uint8_t  PRLH3                :1;
            __IO   uint8_t  PRLH4                :1;
            __IO   uint8_t  PRLH5                :1;
            __IO   uint8_t  PRLH6                :1;
            __IO   uint8_t  PRLH7                :1;
        };
    };
} stc_mft_ppg_prlh1_field_t;

typedef struct stc_mft_ppg_prll2_field
{
    union {
        struct {
            __IO   uint8_t  PRLL                 :8;
        };
        struct {
            __IO   uint8_t  PRLL0                :1;
            __IO   uint8_t  PRLL1                :1;
            __IO   uint8_t  PRLL2                :1;
            __IO   uint8_t  PRLL3                :1;
            __IO   uint8_t  PRLL4                :1;
            __IO   uint8_t  PRLL5                :1;
            __IO   uint8_t  PRLL6                :1;
            __IO   uint8_t  PRLL7                :1;
        };
    };
} stc_mft_ppg_prll2_field_t;

typedef struct stc_mft_ppg_prlh2_field
{
    union {
        struct {
            __IO   uint8_t  PRLH                 :8;
        };
        struct {
            __IO   uint8_t  PRLH0                :1;
            __IO   uint8_t  PRLH1                :1;
            __IO   uint8_t  PRLH2                :1;
            __IO   uint8_t  PRLH3                :1;
            __IO   uint8_t  PRLH4                :1;
            __IO   uint8_t  PRLH5                :1;
            __IO   uint8_t  PRLH6                :1;
            __IO   uint8_t  PRLH7                :1;
        };
    };
} stc_mft_ppg_prlh2_field_t;

typedef struct stc_mft_ppg_prll3_field
{
    union {
        struct {
            __IO   uint8_t  PRLL                 :8;
        };
        struct {
            __IO   uint8_t  PRLL0                :1;
            __IO   uint8_t  PRLL1                :1;
            __IO   uint8_t  PRLL2                :1;
            __IO   uint8_t  PRLL3                :1;
            __IO   uint8_t  PRLL4                :1;
            __IO   uint8_t  PRLL5                :1;
            __IO   uint8_t  PRLL6                :1;
            __IO   uint8_t  PRLL7                :1;
        };
    };
} stc_mft_ppg_prll3_field_t;

typedef struct stc_mft_ppg_prlh3_field
{
    union {
        struct {
            __IO   uint8_t  PRLH                 :8;
        };
        struct {
            __IO   uint8_t  PRLH0                :1;
            __IO   uint8_t  PRLH1                :1;
            __IO   uint8_t  PRLH2                :1;
            __IO   uint8_t  PRLH3                :1;
            __IO   uint8_t  PRLH4                :1;
            __IO   uint8_t  PRLH5                :1;
            __IO   uint8_t  PRLH6                :1;
            __IO   uint8_t  PRLH7                :1;
        };
    };
} stc_mft_ppg_prlh3_field_t;

typedef struct stc_mft_ppg_gatec0_field
{
        __IO   uint8_t  EDGE0                    :1;
        __IO   uint8_t  STRG0                    :1;
        __IO   uint8_t  RESERVED0                :2;
        __IO   uint8_t  EDGE2                    :1;
        __IO   uint8_t  STRG2                    :1;
        __IO   uint8_t  RESERVED1                :2;
} stc_mft_ppg_gatec0_field_t;

typedef struct stc_mft_ppg_ppgc5_field
{
    union {
        struct {
            __IO   uint8_t  RESERVED0            :3;
            __IO   uint8_t  PCS                  :2;
            __IO   uint8_t  INTM                 :1;
            __IO   uint8_t  PUF                  :1;
            __IO   uint8_t  PIE                  :1;
        };
        struct {
            __IO   uint8_t  RESERVED1            :3;
            __IO   uint8_t  PCS0                 :1;
            __IO   uint8_t  PCS1                 :1;
            __IO   uint8_t  RESERVED2            :3;
        };
    };
} stc_mft_ppg_ppgc5_field_t;

typedef struct stc_mft_ppg_ppgc4_field
{
    union {
        struct {
            __IO   uint8_t  TTRG                 :1;
            __IO   uint8_t  MD                   :2;
            __IO   uint8_t  PCS                  :2;
            __IO   uint8_t  INTM                 :1;
            __IO   uint8_t  PUF                  :1;
            __IO   uint8_t  PIE                  :1;
        };
        struct {
            __IO   uint8_t  RESERVED0            :1;
            __IO   uint8_t  MD0                  :1;
            __IO   uint8_t  MD1                  :1;
            __IO   uint8_t  PCS0                 :1;
            __IO   uint8_t  PCS1                 :1;
            __IO   uint8_t  RESERVED1            :3;
        };
    };
} stc_mft_ppg_ppgc4_field_t;

typedef struct stc_mft_ppg_ppgc7_field
{
    union {
        struct {
            __IO   uint8_t  RESERVED0            :3;
            __IO   uint8_t  PCS                  :2;
            __IO   uint8_t  INTM                 :1;
            __IO   uint8_t  PUF                  :1;
            __IO   uint8_t  PIE                  :1;
        };
        struct {
            __IO   uint8_t  RESERVED1            :3;
            __IO   uint8_t  PCS0                 :1;
            __IO   uint8_t  PCS1                 :1;
            __IO   uint8_t  RESERVED2            :3;
        };
    };
} stc_mft_ppg_ppgc7_field_t;

typedef struct stc_mft_ppg_ppgc6_field
{
    union {
        struct {
            __IO   uint8_t  TTRG                 :1;
            __IO   uint8_t  MD                   :2;
            __IO   uint8_t  PCS                  :2;
            __IO   uint8_t  INTM                 :1;
            __IO   uint8_t  PUF                  :1;
            __IO   uint8_t  PIE                  :1;
        };
        struct {
            __IO   uint8_t  RESERVED0            :1;
            __IO   uint8_t  MD0                  :1;
            __IO   uint8_t  MD1                  :1;
            __IO   uint8_t  PCS0                 :1;
            __IO   uint8_t  PCS1                 :1;
            __IO   uint8_t  RESERVED1            :3;
        };
    };
} stc_mft_ppg_ppgc6_field_t;

typedef struct stc_mft_ppg_prll4_field
{
    union {
        struct {
            __IO   uint8_t  PRLL                 :8;
        };
        struct {
            __IO   uint8_t  PRLL0                :1;
            __IO   uint8_t  PRLL1                :1;
            __IO   uint8_t  PRLL2                :1;
            __IO   uint8_t  PRLL3                :1;
            __IO   uint8_t  PRLL4                :1;
            __IO   uint8_t  PRLL5                :1;
            __IO   uint8_t  PRLL6                :1;
            __IO   uint8_t  PRLL7                :1;
        };
    };
} stc_mft_ppg_prll4_field_t;

typedef struct stc_mft_ppg_prlh4_field
{
    union {
        struct {
            __IO   uint8_t  PRLH                 :8;
        };
        struct {
            __IO   uint8_t  PRLH0                :1;
            __IO   uint8_t  PRLH1                :1;
            __IO   uint8_t  PRLH2                :1;
            __IO   uint8_t  PRLH3                :1;
            __IO   uint8_t  PRLH4                :1;
            __IO   uint8_t  PRLH5                :1;
            __IO   uint8_t  PRLH6                :1;
            __IO   uint8_t  PRLH7                :1;
        };
    };
} stc_mft_ppg_prlh4_field_t;

typedef struct stc_mft_ppg_prll5_field
{
    union {
        struct {
            __IO   uint8_t  PRLL                 :8;
        };
        struct {
            __IO   uint8_t  PRLL0                :1;
            __IO   uint8_t  PRLL1                :1;
            __IO   uint8_t  PRLL2                :1;
            __IO   uint8_t  PRLL3                :1;
            __IO   uint8_t  PRLL4                :1;
            __IO   uint8_t  PRLL5                :1;
            __IO   uint8_t  PRLL6                :1;
            __IO   uint8_t  PRLL7                :1;
        };
    };
} stc_mft_ppg_prll5_field_t;

typedef struct stc_mft_ppg_prlh5_field
{
    union {
        struct {
            __IO   uint8_t  PRLH                 :8;
        };
        struct {
            __IO   uint8_t  PRLH0                :1;
            __IO   uint8_t  PRLH1                :1;
            __IO   uint8_t  PRLH2                :1;
            __IO   uint8_t  PRLH3                :1;
            __IO   uint8_t  PRLH4                :1;
            __IO   uint8_t  PRLH5                :1;
            __IO   uint8_t  PRLH6                :1;
            __IO   uint8_t  PRLH7                :1;
        };
    };
} stc_mft_ppg_prlh5_field_t;

typedef struct stc_mft_ppg_prll6_field
{
    union {
        struct {
            __IO   uint8_t  PRLL                 :8;
        };
        struct {
            __IO   uint8_t  PRLL0                :1;
            __IO   uint8_t  PRLL1                :1;
            __IO   uint8_t  PRLL2                :1;
            __IO   uint8_t  PRLL3                :1;
            __IO   uint8_t  PRLL4                :1;
            __IO   uint8_t  PRLL5                :1;
            __IO   uint8_t  PRLL6                :1;
            __IO   uint8_t  PRLL7                :1;
        };
    };
} stc_mft_ppg_prll6_field_t;

typedef struct stc_mft_ppg_prlh6_field
{
    union {
        struct {
            __IO   uint8_t  PRLH                 :8;
        };
        struct {
            __IO   uint8_t  PRLH0                :1;
            __IO   uint8_t  PRLH1                :1;
            __IO   uint8_t  PRLH2                :1;
            __IO   uint8_t  PRLH3                :1;
            __IO   uint8_t  PRLH4                :1;
            __IO   uint8_t  PRLH5                :1;
            __IO   uint8_t  PRLH6                :1;
            __IO   uint8_t  PRLH7                :1;
        };
    };
} stc_mft_ppg_prlh6_field_t;

typedef struct stc_mft_ppg_prll7_field
{
    union {
        struct {
            __IO   uint8_t  PRLL                 :8;
        };
        struct {
            __IO   uint8_t  PRLL0                :1;
            __IO   uint8_t  PRLL1                :1;
            __IO   uint8_t  PRLL2                :1;
            __IO   uint8_t  PRLL3                :1;
            __IO   uint8_t  PRLL4                :1;
            __IO   uint8_t  PRLL5                :1;
            __IO   uint8_t  PRLL6                :1;
            __IO   uint8_t  PRLL7                :1;
        };
    };
} stc_mft_ppg_prll7_field_t;

typedef struct stc_mft_ppg_prlh7_field
{
    union {
        struct {
            __IO   uint8_t  PRLH                 :8;
        };
        struct {
            __IO   uint8_t  PRLH0                :1;
            __IO   uint8_t  PRLH1                :1;
            __IO   uint8_t  PRLH2                :1;
            __IO   uint8_t  PRLH3                :1;
            __IO   uint8_t  PRLH4                :1;
            __IO   uint8_t  PRLH5                :1;
            __IO   uint8_t  PRLH6                :1;
            __IO   uint8_t  PRLH7                :1;
        };
    };
} stc_mft_ppg_prlh7_field_t;

typedef struct stc_mft_ppg_gatec4_field
{
        __IO   uint8_t  EDGE4                    :1;
        __IO   uint8_t  STRG4                    :1;
        __IO   uint8_t  RESERVED0                :2;
        __IO   uint8_t  EDGE6                    :1;
        __IO   uint8_t  STRG6                    :1;
        __IO   uint8_t  RESERVED1                :2;
} stc_mft_ppg_gatec4_field_t;

typedef struct stc_mft_ppg_ppgc9_field
{
    union {
        struct {
            __IO   uint8_t  RESERVED0            :3;
            __IO   uint8_t  PCS                  :2;
            __IO   uint8_t  INTM                 :1;
            __IO   uint8_t  PUF                  :1;
            __IO   uint8_t  PIE                  :1;
        };
        struct {
            __IO   uint8_t  RESERVED1            :3;
            __IO   uint8_t  PCS0                 :1;
            __IO   uint8_t  PCS1                 :1;
            __IO   uint8_t  RESERVED2            :3;
        };
    };
} stc_mft_ppg_ppgc9_field_t;

typedef struct stc_mft_ppg_ppgc8_field
{
    union {
        struct {
            __IO   uint8_t  TTRG                 :1;
            __IO   uint8_t  MD                   :2;
            __IO   uint8_t  PCS                  :2;
            __IO   uint8_t  INTM                 :1;
            __IO   uint8_t  PUF                  :1;
            __IO   uint8_t  PIE                  :1;
        };
        struct {
            __IO   uint8_t  RESERVED0            :1;
            __IO   uint8_t  MD0                  :1;
            __IO   uint8_t  MD1                  :1;
            __IO   uint8_t  PCS0                 :1;
            __IO   uint8_t  PCS1                 :1;
            __IO   uint8_t  RESERVED1            :3;
        };
    };
} stc_mft_ppg_ppgc8_field_t;

typedef struct stc_mft_ppg_ppgc11_field
{
    union {
        struct {
            __IO   uint8_t  RESERVED0            :3;
            __IO   uint8_t  PCS                  :2;
            __IO   uint8_t  INTM                 :1;
            __IO   uint8_t  PUF                  :1;
            __IO   uint8_t  PIE                  :1;
        };
        struct {
            __IO   uint8_t  RESERVED1            :3;
            __IO   uint8_t  PCS0                 :1;
            __IO   uint8_t  PCS1                 :1;
            __IO   uint8_t  RESERVED2            :3;
        };
    };
} stc_mft_ppg_ppgc11_field_t;

typedef struct stc_mft_ppg_ppgc10_field
{
    union {
        struct {
            __IO   uint8_t  TTRG                 :1;
            __IO   uint8_t  MD                   :2;
            __IO   uint8_t  PCS                  :2;
            __IO   uint8_t  INTM                 :1;
            __IO   uint8_t  PUF                  :1;
            __IO   uint8_t  PIE                  :1;
        };
        struct {
            __IO   uint8_t  RESERVED0            :1;
            __IO   uint8_t  MD0                  :1;
            __IO   uint8_t  MD1                  :1;
            __IO   uint8_t  PCS0                 :1;
            __IO   uint8_t  PCS1                 :1;
            __IO   uint8_t  RESERVED1            :3;
        };
    };
} stc_mft_ppg_ppgc10_field_t;

typedef struct stc_mft_ppg_prll8_field
{
    union {
        struct {
            __IO   uint8_t  PRLL                 :8;
        };
        struct {
            __IO   uint8_t  PRLL0                :1;
            __IO   uint8_t  PRLL1                :1;
            __IO   uint8_t  PRLL2                :1;
            __IO   uint8_t  PRLL3                :1;
            __IO   uint8_t  PRLL4                :1;
            __IO   uint8_t  PRLL5                :1;
            __IO   uint8_t  PRLL6                :1;
            __IO   uint8_t  PRLL7                :1;
        };
    };
} stc_mft_ppg_prll8_field_t;

typedef struct stc_mft_ppg_prlh8_field
{
    union {
        struct {
            __IO   uint8_t  PRLH                 :8;
        };
        struct {
            __IO   uint8_t  PRLH0                :1;
            __IO   uint8_t  PRLH1                :1;
            __IO   uint8_t  PRLH2                :1;
            __IO   uint8_t  PRLH3                :1;
            __IO   uint8_t  PRLH4                :1;
            __IO   uint8_t  PRLH5                :1;
            __IO   uint8_t  PRLH6                :1;
            __IO   uint8_t  PRLH7                :1;
        };
    };
} stc_mft_ppg_prlh8_field_t;

typedef struct stc_mft_ppg_prll9_field
{
    union {
        struct {
            __IO   uint8_t  PRLL                 :8;
        };
        struct {
            __IO   uint8_t  PRLL0                :1;
            __IO   uint8_t  PRLL1                :1;
            __IO   uint8_t  PRLL2                :1;
            __IO   uint8_t  PRLL3                :1;
            __IO   uint8_t  PRLL4                :1;
            __IO   uint8_t  PRLL5                :1;
            __IO   uint8_t  PRLL6                :1;
            __IO   uint8_t  PRLL7                :1;
        };
    };
} stc_mft_ppg_prll9_field_t;

typedef struct stc_mft_ppg_prlh9_field
{
    union {
        struct {
            __IO   uint8_t  PRLH                 :8;
        };
        struct {
            __IO   uint8_t  PRLH0                :1;
            __IO   uint8_t  PRLH1                :1;
            __IO   uint8_t  PRLH2                :1;
            __IO   uint8_t  PRLH3                :1;
            __IO   uint8_t  PRLH4                :1;
            __IO   uint8_t  PRLH5                :1;
            __IO   uint8_t  PRLH6                :1;
            __IO   uint8_t  PRLH7                :1;
        };
    };
} stc_mft_ppg_prlh9_field_t;

typedef struct stc_mft_ppg_prll10_field
{
    union {
        struct {
            __IO   uint8_t  PRLL                 :8;
        };
        struct {
            __IO   uint8_t  PRLL0                :1;
            __IO   uint8_t  PRLL1                :1;
            __IO   uint8_t  PRLL2                :1;
            __IO   uint8_t  PRLL3                :1;
            __IO   uint8_t  PRLL4                :1;
            __IO   uint8_t  PRLL5                :1;
            __IO   uint8_t  PRLL6                :1;
            __IO   uint8_t  PRLL7                :1;
        };
    };
} stc_mft_ppg_prll10_field_t;

typedef struct stc_mft_ppg_prlh10_field
{
    union {
        struct {
            __IO   uint8_t  PRLH                 :8;
        };
        struct {
            __IO   uint8_t  PRLH0                :1;
            __IO   uint8_t  PRLH1                :1;
            __IO   uint8_t  PRLH2                :1;
            __IO   uint8_t  PRLH3                :1;
            __IO   uint8_t  PRLH4                :1;
            __IO   uint8_t  PRLH5                :1;
            __IO   uint8_t  PRLH6                :1;
            __IO   uint8_t  PRLH7                :1;
        };
    };
} stc_mft_ppg_prlh10_field_t;

typedef struct stc_mft_ppg_prll11_field
{
    union {
        struct {
            __IO   uint8_t  PRLL                 :8;
        };
        struct {
            __IO   uint8_t  PRLL0                :1;
            __IO   uint8_t  PRLL1                :1;
            __IO   uint8_t  PRLL2                :1;
            __IO   uint8_t  PRLL3                :1;
            __IO   uint8_t  PRLL4                :1;
            __IO   uint8_t  PRLL5                :1;
            __IO   uint8_t  PRLL6                :1;
            __IO   uint8_t  PRLL7                :1;
        };
    };
} stc_mft_ppg_prll11_field_t;

typedef struct stc_mft_ppg_prlh11_field
{
    union {
        struct {
            __IO   uint8_t  PRLH                 :8;
        };
        struct {
            __IO   uint8_t  PRLH0                :1;
            __IO   uint8_t  PRLH1                :1;
            __IO   uint8_t  PRLH2                :1;
            __IO   uint8_t  PRLH3                :1;
            __IO   uint8_t  PRLH4                :1;
            __IO   uint8_t  PRLH5                :1;
            __IO   uint8_t  PRLH6                :1;
            __IO   uint8_t  PRLH7                :1;
        };
    };
} stc_mft_ppg_prlh11_field_t;

typedef struct stc_mft_ppg_gatec8_field
{
        __IO   uint8_t  EDGE8                    :1;
        __IO   uint8_t  STRG8                    :1;
        __IO   uint8_t  RESERVED0                :2;
        __IO   uint8_t  EDGE10                   :1;
        __IO   uint8_t  STRG10                   :1;
        __IO   uint8_t  RESERVED1                :2;
} stc_mft_ppg_gatec8_field_t;

typedef struct stc_mft_ppg_ppgc13_field
{
    union {
        struct {
            __IO   uint8_t  RESERVED0            :3;
            __IO   uint8_t  PCS                  :2;
            __IO   uint8_t  INTM                 :1;
            __IO   uint8_t  PUF                  :1;
            __IO   uint8_t  PIE                  :1;
        };
        struct {
            __IO   uint8_t  RESERVED1            :3;
            __IO   uint8_t  PCS0                 :1;
            __IO   uint8_t  PCS1                 :1;
            __IO   uint8_t  RESERVED2            :3;
        };
    };
} stc_mft_ppg_ppgc13_field_t;

typedef struct stc_mft_ppg_ppgc12_field
{
    union {
        struct {
            __IO   uint8_t  TTRG                 :1;
            __IO   uint8_t  MD                   :2;
            __IO   uint8_t  PCS                  :2;
            __IO   uint8_t  INTM                 :1;
            __IO   uint8_t  PUF                  :1;
            __IO   uint8_t  PIE                  :1;
        };
        struct {
            __IO   uint8_t  RESERVED0            :1;
            __IO   uint8_t  MD0                  :1;
            __IO   uint8_t  MD1                  :1;
            __IO   uint8_t  PCS0                 :1;
            __IO   uint8_t  PCS1                 :1;
            __IO   uint8_t  RESERVED1            :3;
        };
    };
} stc_mft_ppg_ppgc12_field_t;

typedef struct stc_mft_ppg_ppgc15_field
{
    union {
        struct {
            __IO   uint8_t  RESERVED0            :3;
            __IO   uint8_t  PCS                  :2;
            __IO   uint8_t  INTM                 :1;
            __IO   uint8_t  PUF                  :1;
            __IO   uint8_t  PIE                  :1;
        };
        struct {
            __IO   uint8_t  RESERVED1            :3;
            __IO   uint8_t  PCS0                 :1;
            __IO   uint8_t  PCS1                 :1;
            __IO   uint8_t  RESERVED2            :3;
        };
    };
} stc_mft_ppg_ppgc15_field_t;

typedef struct stc_mft_ppg_ppgc14_field
{
    union {
        struct {
            __IO   uint8_t  TTRG                 :1;
            __IO   uint8_t  MD                   :2;
            __IO   uint8_t  PCS                  :2;
            __IO   uint8_t  INTM                 :1;
            __IO   uint8_t  PUF                  :1;
            __IO   uint8_t  PIE                  :1;
        };
        struct {
            __IO   uint8_t  RESERVED0            :1;
            __IO   uint8_t  MD0                  :1;
            __IO   uint8_t  MD1                  :1;
            __IO   uint8_t  PCS0                 :1;
            __IO   uint8_t  PCS1                 :1;
            __IO   uint8_t  RESERVED1            :3;
        };
    };
} stc_mft_ppg_ppgc14_field_t;

typedef struct stc_mft_ppg_prll12_field
{
    union {
        struct {
            __IO   uint8_t  PRLL                 :8;
        };
        struct {
            __IO   uint8_t  PRLL0                :1;
            __IO   uint8_t  PRLL1                :1;
            __IO   uint8_t  PRLL2                :1;
            __IO   uint8_t  PRLL3                :1;
            __IO   uint8_t  PRLL4                :1;
            __IO   uint8_t  PRLL5                :1;
            __IO   uint8_t  PRLL6                :1;
            __IO   uint8_t  PRLL7                :1;
        };
    };
} stc_mft_ppg_prll12_field_t;

typedef struct stc_mft_ppg_prlh12_field
{
    union {
        struct {
            __IO   uint8_t  PRLH                 :8;
        };
        struct {
            __IO   uint8_t  PRLH0                :1;
            __IO   uint8_t  PRLH1                :1;
            __IO   uint8_t  PRLH2                :1;
            __IO   uint8_t  PRLH3                :1;
            __IO   uint8_t  PRLH4                :1;
            __IO   uint8_t  PRLH5                :1;
            __IO   uint8_t  PRLH6                :1;
            __IO   uint8_t  PRLH7                :1;
        };
    };
} stc_mft_ppg_prlh12_field_t;

typedef struct stc_mft_ppg_prll13_field
{
    union {
        struct {
            __IO   uint8_t  PRLL                 :8;
        };
        struct {
            __IO   uint8_t  PRLL0                :1;
            __IO   uint8_t  PRLL1                :1;
            __IO   uint8_t  PRLL2                :1;
            __IO   uint8_t  PRLL3                :1;
            __IO   uint8_t  PRLL4                :1;
            __IO   uint8_t  PRLL5                :1;
            __IO   uint8_t  PRLL6                :1;
            __IO   uint8_t  PRLL7                :1;
        };
    };
} stc_mft_ppg_prll13_field_t;

typedef struct stc_mft_ppg_prlh13_field
{
    union {
        struct {
            __IO   uint8_t  PRLH                 :8;
        };
        struct {
            __IO   uint8_t  PRLH0                :1;
            __IO   uint8_t  PRLH1                :1;
            __IO   uint8_t  PRLH2                :1;
            __IO   uint8_t  PRLH3                :1;
            __IO   uint8_t  PRLH4                :1;
            __IO   uint8_t  PRLH5                :1;
            __IO   uint8_t  PRLH6                :1;
            __IO   uint8_t  PRLH7                :1;
        };
    };
} stc_mft_ppg_prlh13_field_t;

typedef struct stc_mft_ppg_prll14_field
{
    union {
        struct {
            __IO   uint8_t  PRLL                 :8;
        };
        struct {
            __IO   uint8_t  PRLL0                :1;
            __IO   uint8_t  PRLL1                :1;
            __IO   uint8_t  PRLL2                :1;
            __IO   uint8_t  PRLL3                :1;
            __IO   uint8_t  PRLL4                :1;
            __IO   uint8_t  PRLL5                :1;
            __IO   uint8_t  PRLL6                :1;
            __IO   uint8_t  PRLL7                :1;
        };
    };
} stc_mft_ppg_prll14_field_t;

typedef struct stc_mft_ppg_prlh14_field
{
    union {
        struct {
            __IO   uint8_t  PRLH                 :8;
        };
        struct {
            __IO   uint8_t  PRLH0                :1;
            __IO   uint8_t  PRLH1                :1;
            __IO   uint8_t  PRLH2                :1;
            __IO   uint8_t  PRLH3                :1;
            __IO   uint8_t  PRLH4                :1;
            __IO   uint8_t  PRLH5                :1;
            __IO   uint8_t  PRLH6                :1;
            __IO   uint8_t  PRLH7                :1;
        };
    };
} stc_mft_ppg_prlh14_field_t;

typedef struct stc_mft_ppg_prll15_field
{
    union {
        struct {
            __IO   uint8_t  PRLL                 :8;
        };
        struct {
            __IO   uint8_t  PRLL0                :1;
            __IO   uint8_t  PRLL1                :1;
            __IO   uint8_t  PRLL2                :1;
            __IO   uint8_t  PRLL3                :1;
            __IO   uint8_t  PRLL4                :1;
            __IO   uint8_t  PRLL5                :1;
            __IO   uint8_t  PRLL6                :1;
            __IO   uint8_t  PRLL7                :1;
        };
    };
} stc_mft_ppg_prll15_field_t;

typedef struct stc_mft_ppg_prlh15_field
{
    union {
        struct {
            __IO   uint8_t  PRLH                 :8;
        };
        struct {
            __IO   uint8_t  PRLH0                :1;
            __IO   uint8_t  PRLH1                :1;
            __IO   uint8_t  PRLH2                :1;
            __IO   uint8_t  PRLH3                :1;
            __IO   uint8_t  PRLH4                :1;
            __IO   uint8_t  PRLH5                :1;
            __IO   uint8_t  PRLH6                :1;
            __IO   uint8_t  PRLH7                :1;
        };
    };
} stc_mft_ppg_prlh15_field_t;

typedef struct stc_mft_ppg_gatec12_field
{
        __IO   uint8_t  EDGE12                   :1;
        __IO   uint8_t  STRG12                   :1;
        __IO   uint8_t  RESERVED0                :2;
        __IO   uint8_t  EDGE14                   :1;
        __IO   uint8_t  STRG14                   :1;
        __IO   uint8_t  RESERVED1                :2;
} stc_mft_ppg_gatec12_field_t;

typedef struct stc_mft_ppg_ppgc17_field
{
    union {
        struct {
            __IO   uint8_t  RESERVED0            :3;
            __IO   uint8_t  PCS                  :2;
            __IO   uint8_t  INTM                 :1;
            __IO   uint8_t  PUF                  :1;
            __IO   uint8_t  PIE                  :1;
        };
        struct {
            __IO   uint8_t  RESERVED1            :3;
            __IO   uint8_t  PCS0                 :1;
            __IO   uint8_t  PCS1                 :1;
            __IO   uint8_t  RESERVED2            :3;
        };
    };
} stc_mft_ppg_ppgc17_field_t;

typedef struct stc_mft_ppg_ppgc16_field
{
    union {
        struct {
            __IO   uint8_t  TTRG                 :1;
            __IO   uint8_t  MD                   :2;
            __IO   uint8_t  PCS                  :2;
            __IO   uint8_t  INTM                 :1;
            __IO   uint8_t  PUF                  :1;
            __IO   uint8_t  PIE                  :1;
        };
        struct {
            __IO   uint8_t  RESERVED0            :1;
            __IO   uint8_t  MD0                  :1;
            __IO   uint8_t  MD1                  :1;
            __IO   uint8_t  PCS0                 :1;
            __IO   uint8_t  PCS1                 :1;
            __IO   uint8_t  RESERVED1            :3;
        };
    };
} stc_mft_ppg_ppgc16_field_t;

typedef struct stc_mft_ppg_ppgc19_field
{
    union {
        struct {
            __IO   uint8_t  RESERVED0            :3;
            __IO   uint8_t  PCS                  :2;
            __IO   uint8_t  INTM                 :1;
            __IO   uint8_t  PUF                  :1;
            __IO   uint8_t  PIE                  :1;
        };
        struct {
            __IO   uint8_t  RESERVED1            :3;
            __IO   uint8_t  PCS0                 :1;
            __IO   uint8_t  PCS1                 :1;
            __IO   uint8_t  RESERVED2            :3;
        };
    };
} stc_mft_ppg_ppgc19_field_t;

typedef struct stc_mft_ppg_ppgc18_field
{
    union {
        struct {
            __IO   uint8_t  TTRG                 :1;
            __IO   uint8_t  MD                   :2;
            __IO   uint8_t  PCS                  :2;
            __IO   uint8_t  INTM                 :1;
            __IO   uint8_t  PUF                  :1;
            __IO   uint8_t  PIE                  :1;
        };
        struct {
            __IO   uint8_t  RESERVED0            :1;
            __IO   uint8_t  MD0                  :1;
            __IO   uint8_t  MD1                  :1;
            __IO   uint8_t  PCS0                 :1;
            __IO   uint8_t  PCS1                 :1;
            __IO   uint8_t  RESERVED1            :3;
        };
    };
} stc_mft_ppg_ppgc18_field_t;

typedef struct stc_mft_ppg_prll16_field
{
    union {
        struct {
            __IO   uint8_t  PRLL                 :8;
        };
        struct {
            __IO   uint8_t  PRLL0                :1;
            __IO   uint8_t  PRLL1                :1;
            __IO   uint8_t  PRLL2                :1;
            __IO   uint8_t  PRLL3                :1;
            __IO   uint8_t  PRLL4                :1;
            __IO   uint8_t  PRLL5                :1;
            __IO   uint8_t  PRLL6                :1;
            __IO   uint8_t  PRLL7                :1;
        };
    };
} stc_mft_ppg_prll16_field_t;

typedef struct stc_mft_ppg_prlh16_field
{
    union {
        struct {
            __IO   uint8_t  PRLH                 :8;
        };
        struct {
            __IO   uint8_t  PRLH0                :1;
            __IO   uint8_t  PRLH1                :1;
            __IO   uint8_t  PRLH2                :1;
            __IO   uint8_t  PRLH3                :1;
            __IO   uint8_t  PRLH4                :1;
            __IO   uint8_t  PRLH5                :1;
            __IO   uint8_t  PRLH6                :1;
            __IO   uint8_t  PRLH7                :1;
        };
    };
} stc_mft_ppg_prlh16_field_t;

typedef struct stc_mft_ppg_prll17_field
{
    union {
        struct {
            __IO   uint8_t  PRLL                 :8;
        };
        struct {
            __IO   uint8_t  PRLL0                :1;
            __IO   uint8_t  PRLL1                :1;
            __IO   uint8_t  PRLL2                :1;
            __IO   uint8_t  PRLL3                :1;
            __IO   uint8_t  PRLL4                :1;
            __IO   uint8_t  PRLL5                :1;
            __IO   uint8_t  PRLL6                :1;
            __IO   uint8_t  PRLL7                :1;
        };
    };
} stc_mft_ppg_prll17_field_t;

typedef struct stc_mft_ppg_prlh17_field
{
    union {
        struct {
            __IO   uint8_t  PRLH                 :8;
        };
        struct {
            __IO   uint8_t  PRLH0                :1;
            __IO   uint8_t  PRLH1                :1;
            __IO   uint8_t  PRLH2                :1;
            __IO   uint8_t  PRLH3                :1;
            __IO   uint8_t  PRLH4                :1;
            __IO   uint8_t  PRLH5                :1;
            __IO   uint8_t  PRLH6                :1;
            __IO   uint8_t  PRLH7                :1;
        };
    };
} stc_mft_ppg_prlh17_field_t;

typedef struct stc_mft_ppg_prll18_field
{
    union {
        struct {
            __IO   uint8_t  PRLL                 :8;
        };
        struct {
            __IO   uint8_t  PRLL0                :1;
            __IO   uint8_t  PRLL1                :1;
            __IO   uint8_t  PRLL2                :1;
            __IO   uint8_t  PRLL3                :1;
            __IO   uint8_t  PRLL4                :1;
            __IO   uint8_t  PRLL5                :1;
            __IO   uint8_t  PRLL6                :1;
            __IO   uint8_t  PRLL7                :1;
        };
    };
} stc_mft_ppg_prll18_field_t;

typedef struct stc_mft_ppg_prlh18_field
{
    union {
        struct {
            __IO   uint8_t  PRLH                 :8;
        };
        struct {
            __IO   uint8_t  PRLH0                :1;
            __IO   uint8_t  PRLH1                :1;
            __IO   uint8_t  PRLH2                :1;
            __IO   uint8_t  PRLH3                :1;
            __IO   uint8_t  PRLH4                :1;
            __IO   uint8_t  PRLH5                :1;
            __IO   uint8_t  PRLH6                :1;
            __IO   uint8_t  PRLH7                :1;
        };
    };
} stc_mft_ppg_prlh18_field_t;

typedef struct stc_mft_ppg_prll19_field
{
    union {
        struct {
            __IO   uint8_t  PRLL                 :8;
        };
        struct {
            __IO   uint8_t  PRLL0                :1;
            __IO   uint8_t  PRLL1                :1;
            __IO   uint8_t  PRLL2                :1;
            __IO   uint8_t  PRLL3                :1;
            __IO   uint8_t  PRLL4                :1;
            __IO   uint8_t  PRLL5                :1;
            __IO   uint8_t  PRLL6                :1;
            __IO   uint8_t  PRLL7                :1;
        };
    };
} stc_mft_ppg_prll19_field_t;

typedef struct stc_mft_ppg_prlh19_field
{
    union {
        struct {
            __IO   uint8_t  PRLH                 :8;
        };
        struct {
            __IO   uint8_t  PRLH0                :1;
            __IO   uint8_t  PRLH1                :1;
            __IO   uint8_t  PRLH2                :1;
            __IO   uint8_t  PRLH3                :1;
            __IO   uint8_t  PRLH4                :1;
            __IO   uint8_t  PRLH5                :1;
            __IO   uint8_t  PRLH6                :1;
            __IO   uint8_t  PRLH7                :1;
        };
    };
} stc_mft_ppg_prlh19_field_t;

typedef struct stc_mft_ppg_gatec16_field
{
        __IO   uint8_t  EDGE16                   :1;
        __IO   uint8_t  STRG16                   :1;
        __IO   uint8_t  RESERVED0                :2;
        __IO   uint8_t  EDGE18                   :1;
        __IO   uint8_t  STRG18                   :1;
        __IO   uint8_t  RESERVED1                :2;
} stc_mft_ppg_gatec16_field_t;

typedef struct stc_mft_ppg_ppgc21_field
{
    union {
        struct {
            __IO   uint8_t  RESERVED0            :3;
            __IO   uint8_t  PCS                  :2;
            __IO   uint8_t  INTM                 :1;
            __IO   uint8_t  PUF                  :1;
            __IO   uint8_t  PIE                  :1;
        };
        struct {
            __IO   uint8_t  RESERVED1            :3;
            __IO   uint8_t  PCS0                 :1;
            __IO   uint8_t  PCS1                 :1;
            __IO   uint8_t  RESERVED2            :3;
        };
    };
} stc_mft_ppg_ppgc21_field_t;

typedef struct stc_mft_ppg_ppgc20_field
{
    union {
        struct {
            __IO   uint8_t  TTRG                 :1;
            __IO   uint8_t  MD                   :2;
            __IO   uint8_t  PCS                  :2;
            __IO   uint8_t  INTM                 :1;
            __IO   uint8_t  PUF                  :1;
            __IO   uint8_t  PIE                  :1;
        };
        struct {
            __IO   uint8_t  RESERVED0            :1;
            __IO   uint8_t  MD0                  :1;
            __IO   uint8_t  MD1                  :1;
            __IO   uint8_t  PCS0                 :1;
            __IO   uint8_t  PCS1                 :1;
            __IO   uint8_t  RESERVED1            :3;
        };
    };
} stc_mft_ppg_ppgc20_field_t;

typedef struct stc_mft_ppg_ppgc23_field
{
    union {
        struct {
            __IO   uint8_t  RESERVED0            :3;
            __IO   uint8_t  PCS                  :2;
            __IO   uint8_t  INTM                 :1;
            __IO   uint8_t  PUF                  :1;
            __IO   uint8_t  PIE                  :1;
        };
        struct {
            __IO   uint8_t  RESERVED1            :3;
            __IO   uint8_t  PCS0                 :1;
            __IO   uint8_t  PCS1                 :1;
            __IO   uint8_t  RESERVED2            :3;
        };
    };
} stc_mft_ppg_ppgc23_field_t;

typedef struct stc_mft_ppg_ppgc22_field
{
    union {
        struct {
            __IO   uint8_t  TTRG                 :1;
            __IO   uint8_t  MD                   :2;
            __IO   uint8_t  PCS                  :2;
            __IO   uint8_t  INTM                 :1;
            __IO   uint8_t  PUF                  :1;
            __IO   uint8_t  PIE                  :1;
        };
        struct {
            __IO   uint8_t  RESERVED0            :1;
            __IO   uint8_t  MD0                  :1;
            __IO   uint8_t  MD1                  :1;
            __IO   uint8_t  PCS0                 :1;
            __IO   uint8_t  PCS1                 :1;
            __IO   uint8_t  RESERVED1            :3;
        };
    };
} stc_mft_ppg_ppgc22_field_t;

typedef struct stc_mft_ppg_prll20_field
{
    union {
        struct {
            __IO   uint8_t  PRLL                 :8;
        };
        struct {
            __IO   uint8_t  PRLL0                :1;
            __IO   uint8_t  PRLL1                :1;
            __IO   uint8_t  PRLL2                :1;
            __IO   uint8_t  PRLL3                :1;
            __IO   uint8_t  PRLL4                :1;
            __IO   uint8_t  PRLL5                :1;
            __IO   uint8_t  PRLL6                :1;
            __IO   uint8_t  PRLL7                :1;
        };
    };
} stc_mft_ppg_prll20_field_t;

typedef struct stc_mft_ppg_prlh20_field
{
    union {
        struct {
            __IO   uint8_t  PRLH                 :8;
        };
        struct {
            __IO   uint8_t  PRLH0                :1;
            __IO   uint8_t  PRLH1                :1;
            __IO   uint8_t  PRLH2                :1;
            __IO   uint8_t  PRLH3                :1;
            __IO   uint8_t  PRLH4                :1;
            __IO   uint8_t  PRLH5                :1;
            __IO   uint8_t  PRLH6                :1;
            __IO   uint8_t  PRLH7                :1;
        };
    };
} stc_mft_ppg_prlh20_field_t;

typedef struct stc_mft_ppg_prll21_field
{
    union {
        struct {
            __IO   uint8_t  PRLL                 :8;
        };
        struct {
            __IO   uint8_t  PRLL0                :1;
            __IO   uint8_t  PRLL1                :1;
            __IO   uint8_t  PRLL2                :1;
            __IO   uint8_t  PRLL3                :1;
            __IO   uint8_t  PRLL4                :1;
            __IO   uint8_t  PRLL5                :1;
            __IO   uint8_t  PRLL6                :1;
            __IO   uint8_t  PRLL7                :1;
        };
    };
} stc_mft_ppg_prll21_field_t;

typedef struct stc_mft_ppg_prlh21_field
{
    union {
        struct {
            __IO   uint8_t  PRLH                 :8;
        };
        struct {
            __IO   uint8_t  PRLH0                :1;
            __IO   uint8_t  PRLH1                :1;
            __IO   uint8_t  PRLH2                :1;
            __IO   uint8_t  PRLH3                :1;
            __IO   uint8_t  PRLH4                :1;
            __IO   uint8_t  PRLH5                :1;
            __IO   uint8_t  PRLH6                :1;
            __IO   uint8_t  PRLH7                :1;
        };
    };
} stc_mft_ppg_prlh21_field_t;

typedef struct stc_mft_ppg_prll22_field
{
    union {
        struct {
            __IO   uint8_t  PRLL                 :8;
        };
        struct {
            __IO   uint8_t  PRLL0                :1;
            __IO   uint8_t  PRLL1                :1;
            __IO   uint8_t  PRLL2                :1;
            __IO   uint8_t  PRLL3                :1;
            __IO   uint8_t  PRLL4                :1;
            __IO   uint8_t  PRLL5                :1;
            __IO   uint8_t  PRLL6                :1;
            __IO   uint8_t  PRLL7                :1;
        };
    };
} stc_mft_ppg_prll22_field_t;

typedef struct stc_mft_ppg_prlh22_field
{
    union {
        struct {
            __IO   uint8_t  PRLH                 :8;
        };
        struct {
            __IO   uint8_t  PRLH0                :1;
            __IO   uint8_t  PRLH1                :1;
            __IO   uint8_t  PRLH2                :1;
            __IO   uint8_t  PRLH3                :1;
            __IO   uint8_t  PRLH4                :1;
            __IO   uint8_t  PRLH5                :1;
            __IO   uint8_t  PRLH6                :1;
            __IO   uint8_t  PRLH7                :1;
        };
    };
} stc_mft_ppg_prlh22_field_t;

typedef struct stc_mft_ppg_prll23_field
{
    union {
        struct {
            __IO   uint8_t  PRLL                 :8;
        };
        struct {
            __IO   uint8_t  PRLL0                :1;
            __IO   uint8_t  PRLL1                :1;
            __IO   uint8_t  PRLL2                :1;
            __IO   uint8_t  PRLL3                :1;
            __IO   uint8_t  PRLL4                :1;
            __IO   uint8_t  PRLL5                :1;
            __IO   uint8_t  PRLL6                :1;
            __IO   uint8_t  PRLL7                :1;
        };
    };
} stc_mft_ppg_prll23_field_t;

typedef struct stc_mft_ppg_prlh23_field
{
    union {
        struct {
            __IO   uint8_t  PRLH                 :8;
        };
        struct {
            __IO   uint8_t  PRLH0                :1;
            __IO   uint8_t  PRLH1                :1;
            __IO   uint8_t  PRLH2                :1;
            __IO   uint8_t  PRLH3                :1;
            __IO   uint8_t  PRLH4                :1;
            __IO   uint8_t  PRLH5                :1;
            __IO   uint8_t  PRLH6                :1;
            __IO   uint8_t  PRLH7                :1;
        };
    };
} stc_mft_ppg_prlh23_field_t;

typedef struct stc_mft_ppg_gatec20_field
{
        __IO   uint8_t  EDGE20                   :1;
        __IO   uint8_t  STRG20                   :1;
        __IO   uint8_t  RESERVED0                :2;
        __IO   uint8_t  EDGE22                   :1;
        __IO   uint8_t  STRG22                   :1;
        __IO   uint8_t  RESERVED1                :2;
} stc_mft_ppg_gatec20_field_t;

/*******************************************************************************
* PCRC_MODULE
*******************************************************************************/
typedef struct stc_pcrc_pcrc_cfg_field
{
    union {
        struct {
            __IO  uint32_t  CIRQCLR              :1;
            __IO  uint32_t  RESERVED0            :7;
            __IO  uint32_t  FO                   :2;
            __IO  uint32_t  FI                   :2;
            __IO  uint32_t  RESERVED2            :4;
            __IO  uint32_t  TEST                 :6;
            __IO  uint32_t  SZ                   :2;
            __IO  uint32_t  CIRQ                 :1;
            __IO  uint32_t  CIEN                 :1;
            __IO  uint32_t  CDEN                 :1;
            __IO  uint32_t  RESERVED4            :1;
            __IO  uint32_t  LOCK                 :1;
            __IO  uint32_t  RESERVED5            :3;
        };
        struct {
            __IO  uint32_t  RESERVED1            :8;
            __IO  uint32_t  FO0                  :1;
            __IO  uint32_t  FO1                  :1;
            __IO  uint32_t  FI0                  :1;
            __IO  uint32_t  FI1                  :1;
            __IO  uint32_t  RESERVED3            :4;
            __IO  uint32_t  TEST0                :1;
            __IO  uint32_t  TEST1                :1;
            __IO  uint32_t  TEST2                :1;
            __IO  uint32_t  TEST3                :1;
            __IO  uint32_t  TEST4                :1;
            __IO  uint32_t  TEST5                :1;
            __IO  uint32_t  SZ0                  :1;
            __IO  uint32_t  SZ1                  :1;
            __IO  uint32_t  RESERVED6            :8;
        };
    };
} stc_pcrc_pcrc_cfg_field_t;

/*******************************************************************************
* QPRC_MODULE
*******************************************************************************/
typedef struct stc_qprc_qicrl_field
{
        __IO   uint8_t  QPCMIE                   :1;
        __IO   uint8_t  QPCMF                    :1;
        __IO   uint8_t  QPRCMIE                  :1;
        __IO   uint8_t  QPRCMF                   :1;
        __IO   uint8_t  OUZIE                    :1;
        __IO   uint8_t  UFDF                     :1;
        __IO   uint8_t  OFDF                     :1;
        __IO   uint8_t  ZIIF                     :1;
} stc_qprc_qicrl_field_t;

typedef struct stc_qprc_qicrh_field
{
        __IO   uint8_t  CDCIE                    :1;
        __IO   uint8_t  CDCF                     :1;
        __IO   uint8_t  DIRPC                    :1;
        __IO   uint8_t  DIROU                    :1;
        __IO   uint8_t  QPCNRCMIE                :1;
        __IO   uint8_t  QPCNRCMF                 :1;
        __IO   uint8_t  RESERVED0                :2;
} stc_qprc_qicrh_field_t;

typedef struct stc_qprc_qcr_field
{
    union {
        struct {
            __IO  uint16_t  PCM                  :2;
            __IO  uint16_t  RCM                  :2;
            __IO  uint16_t  PSTP                 :1;
            __IO  uint16_t  CGSC                 :1;
            __IO  uint16_t  RSEL                 :1;
            __IO  uint16_t  SWAP                 :1;
            __IO  uint16_t  PCRM                 :2;
            __IO  uint16_t  AES                  :2;
            __IO  uint16_t  BES                  :2;
            __IO  uint16_t  CGE                  :2;
        };
        struct {
            __IO  uint16_t  PCM0                 :1;
            __IO  uint16_t  PCM1                 :1;
            __IO  uint16_t  RCM0                 :1;
            __IO  uint16_t  RCM1                 :1;
            __IO  uint16_t  RESERVED0            :4;
            __IO  uint16_t  PCRM0                :1;
            __IO  uint16_t  PCRM1                :1;
            __IO  uint16_t  AES0                 :1;
            __IO  uint16_t  AES1                 :1;
            __IO  uint16_t  BES0                 :1;
            __IO  uint16_t  BES1                 :1;
            __IO  uint16_t  CGE0                 :1;
            __IO  uint16_t  CGE1                 :1;
        };
    };
} stc_qprc_qcr_field_t;

typedef struct stc_qprc_qecr_field
{
        __IO  uint16_t  ORNGMD                   :1;
        __IO  uint16_t  ORNGF                    :1;
        __IO  uint16_t  ORNGIE                   :1;
        __IO  uint16_t  PEC                      :1;
        __IO  uint16_t  RESERVED0                :12;
} stc_qprc_qecr_field_t;

typedef struct stc_qprc_qprcrr_field
{
    union {
        struct {
            __IO  uint32_t  QPCRR                :16;
            __IO  uint32_t  QRCRR                :16;
        };
        struct {
            __IO  uint32_t  QPCRR0               :1;
            __IO  uint32_t  QPCRR1               :1;
            __IO  uint32_t  QPCRR2               :1;
            __IO  uint32_t  QPCRR3               :1;
            __IO  uint32_t  QPCRR4               :1;
            __IO  uint32_t  QPCRR5               :1;
            __IO  uint32_t  QPCRR6               :1;
            __IO  uint32_t  QPCRR7               :1;
            __IO  uint32_t  QPCRR8               :1;
            __IO  uint32_t  QPCRR9               :1;
            __IO  uint32_t  QPCRR10              :1;
            __IO  uint32_t  QPCRR11              :1;
            __IO  uint32_t  QPCRR12              :1;
            __IO  uint32_t  QPCRR13              :1;
            __IO  uint32_t  QPCRR14              :1;
            __IO  uint32_t  QPCRR15              :1;
            __IO  uint32_t  QRCRR0               :1;
            __IO  uint32_t  QRCRR1               :1;
            __IO  uint32_t  QRCRR2               :1;
            __IO  uint32_t  QRCRR3               :1;
            __IO  uint32_t  QRCRR4               :1;
            __IO  uint32_t  QRCRR5               :1;
            __IO  uint32_t  QRCRR6               :1;
            __IO  uint32_t  QRCRR7               :1;
            __IO  uint32_t  QRCRR8               :1;
            __IO  uint32_t  QRCRR9               :1;
            __IO  uint32_t  QRCRR10              :1;
            __IO  uint32_t  QRCRR11              :1;
            __IO  uint32_t  QRCRR12              :1;
            __IO  uint32_t  QRCRR13              :1;
            __IO  uint32_t  QRCRR14              :1;
            __IO  uint32_t  QRCRR15              :1;
        };
    };
} stc_qprc_qprcrr_field_t;

/*******************************************************************************
* QPRC_NF_MODULE
*******************************************************************************/
typedef struct stc_qprc_nf_nfctla_field
{
    union {
        struct {
            __IO   uint8_t  AINNWS               :3;
            __IO   uint8_t  RESERVED0            :1;
            __IO   uint8_t  AINLV                :1;
            __IO   uint8_t  AINMD                :1;
            __IO   uint8_t  RESERVED1            :2;
        };
        struct {
            __IO   uint8_t  AINNWS0              :1;
            __IO   uint8_t  AINNWS1              :1;
            __IO   uint8_t  AINNWS2              :1;
            __IO   uint8_t  RESERVED2            :5;
        };
    };
} stc_qprc_nf_nfctla_field_t;

typedef struct stc_qprc_nf_nfctlb_field
{
    union {
        struct {
            __IO   uint8_t  BINNWS               :3;
            __IO   uint8_t  RESERVED0            :1;
            __IO   uint8_t  BINLV                :1;
            __IO   uint8_t  BINMD                :1;
            __IO   uint8_t  RESERVED1            :2;
        };
        struct {
            __IO   uint8_t  BINNWS0              :1;
            __IO   uint8_t  BINNWS1              :1;
            __IO   uint8_t  BINNWS2              :1;
            __IO   uint8_t  RESERVED2            :5;
        };
    };
} stc_qprc_nf_nfctlb_field_t;

typedef struct stc_qprc_nf_nfctlz_field
{
    union {
        struct {
            __IO   uint8_t  ZINNWS               :3;
            __IO   uint8_t  RESERVED0            :1;
            __IO   uint8_t  ZINLV                :1;
            __IO   uint8_t  ZINMD                :1;
            __IO   uint8_t  RESERVED1            :2;
        };
        struct {
            __IO   uint8_t  ZINNWS0              :1;
            __IO   uint8_t  ZINNWS1              :1;
            __IO   uint8_t  ZINNWS2              :1;
            __IO   uint8_t  RESERVED2            :5;
        };
    };
} stc_qprc_nf_nfctlz_field_t;

/*******************************************************************************
* RTC_MODULE
*******************************************************************************/
typedef struct stc_rtc_wtcr10_field
{
        __IO   uint8_t  ST                       :1;
        __IO   uint8_t  RESERVED0                :1;
        __IO   uint8_t  RUN                      :1;
        __IO   uint8_t  SRST                     :1;
        __IO   uint8_t  SCST                     :1;
        __IO   uint8_t  SCRST                    :1;
        __IO   uint8_t  BUSY                     :1;
        __IO   uint8_t  TRANS                    :1;
} stc_rtc_wtcr10_field_t;

typedef struct stc_rtc_wtcr11_field
{
        __IO   uint8_t  MIEN                     :1;
        __IO   uint8_t  HEN                      :1;
        __IO   uint8_t  DEN                      :1;
        __IO   uint8_t  MOEN                     :1;
        __IO   uint8_t  YEN                      :1;
        __IO   uint8_t  RESERVED0                :3;
} stc_rtc_wtcr11_field_t;

typedef struct stc_rtc_wtcr12_field
{
        __IO   uint8_t  INTSSI                   :1;
        __IO   uint8_t  INTSI                    :1;
        __IO   uint8_t  INTMI                    :1;
        __IO   uint8_t  INTHI                    :1;
        __IO   uint8_t  INTTMI                   :1;
        __IO   uint8_t  INTALI                   :1;
        __IO   uint8_t  INTERI                   :1;
        __IO   uint8_t  INTCRI                   :1;
} stc_rtc_wtcr12_field_t;

typedef struct stc_rtc_wtcr13_field
{
        __IO   uint8_t  INTSSIE                  :1;
        __IO   uint8_t  INTSIE                   :1;
        __IO   uint8_t  INTMIE                   :1;
        __IO   uint8_t  INTHIE                   :1;
        __IO   uint8_t  INTTMIE                  :1;
        __IO   uint8_t  INTALIE                  :1;
        __IO   uint8_t  INTERIE                  :1;
        __IO   uint8_t  INTCRIE                  :1;
} stc_rtc_wtcr13_field_t;

typedef struct stc_rtc_wtcr20_field
{
        __IO   uint8_t  CREAD                    :1;
        __IO   uint8_t  CWRITE                   :1;
        __IO   uint8_t  BREAD                    :1;
        __IO   uint8_t  BWRITE                   :1;
        __IO   uint8_t  PREAD                    :1;
        __IO   uint8_t  PWRITE                   :1;
        __IO   uint8_t  RESERVED0                :2;
} stc_rtc_wtcr20_field_t;

typedef struct stc_rtc_wtcr21_field
{
        __IO   uint8_t  TMST                     :1;
        __IO   uint8_t  TMEN                     :1;
        __IO   uint8_t  TMRUN                    :1;
        __IO   uint8_t  RESERVED0                :5;
} stc_rtc_wtcr21_field_t;

typedef struct stc_rtc_wtsr_field
{
    union {
        struct {
            __IO   uint8_t  S                    :4;
            __IO   uint8_t  TS                   :3;
            __IO   uint8_t  RESERVED0            :1;
        };
        struct {
            __IO   uint8_t  S0                   :1;
            __IO   uint8_t  S1                   :1;
            __IO   uint8_t  S2                   :1;
            __IO   uint8_t  S3                   :1;
            __IO   uint8_t  TS0                  :1;
            __IO   uint8_t  TS1                  :1;
            __IO   uint8_t  TS2                  :1;
            __IO   uint8_t  RESERVED1            :1;
        };
    };
} stc_rtc_wtsr_field_t;

typedef struct stc_rtc_wtmir_field
{
    union {
        struct {
            __IO   uint8_t  MI                   :4;
            __IO   uint8_t  TMI                  :3;
            __IO   uint8_t  RESERVED0            :1;
        };
        struct {
            __IO   uint8_t  MI0                  :1;
            __IO   uint8_t  MI1                  :1;
            __IO   uint8_t  MI2                  :1;
            __IO   uint8_t  MI3                  :1;
            __IO   uint8_t  TMI0                 :1;
            __IO   uint8_t  TMI1                 :1;
            __IO   uint8_t  TMI2                 :1;
            __IO   uint8_t  RESERVED1            :1;
        };
    };
} stc_rtc_wtmir_field_t;

typedef struct stc_rtc_wthr_field
{
    union {
        struct {
            __IO   uint8_t  H                    :4;
            __IO   uint8_t  TH                   :2;
            __IO   uint8_t  RESERVED0            :2;
        };
        struct {
            __IO   uint8_t  H0                   :1;
            __IO   uint8_t  H1                   :1;
            __IO   uint8_t  H2                   :1;
            __IO   uint8_t  H3                   :1;
            __IO   uint8_t  TH0                  :1;
            __IO   uint8_t  TH1                  :1;
            __IO   uint8_t  RESERVED1            :2;
        };
    };
} stc_rtc_wthr_field_t;

typedef struct stc_rtc_wtdr_field
{
    union {
        struct {
            __IO   uint8_t  D                    :4;
            __IO   uint8_t  TD                   :2;
            __IO   uint8_t  RESERVED0            :2;
        };
        struct {
            __IO   uint8_t  D0                   :1;
            __IO   uint8_t  D1                   :1;
            __IO   uint8_t  D2                   :1;
            __IO   uint8_t  D3                   :1;
            __IO   uint8_t  TD0                  :1;
            __IO   uint8_t  TD1                  :1;
            __IO   uint8_t  RESERVED1            :2;
        };
    };
} stc_rtc_wtdr_field_t;

typedef struct stc_rtc_wtdw_field
{
    union {
        struct {
            __IO   uint8_t  DW                   :3;
            __IO   uint8_t  RESERVED0            :5;
        };
        struct {
            __IO   uint8_t  DW0                  :1;
            __IO   uint8_t  DW1                  :1;
            __IO   uint8_t  DW2                  :1;
            __IO   uint8_t  RESERVED1            :5;
        };
    };
} stc_rtc_wtdw_field_t;

typedef struct stc_rtc_wtmor_field
{
    union {
        struct {
            __IO   uint8_t  MO                   :4;
            __IO   uint8_t  TMO                  :1;
            __IO   uint8_t  RESERVED0            :3;
        };
        struct {
            __IO   uint8_t  MO0                  :1;
            __IO   uint8_t  MO1                  :1;
            __IO   uint8_t  MO2                  :1;
            __IO   uint8_t  MO3                  :1;
            __IO   uint8_t  RESERVED1            :4;
        };
    };
} stc_rtc_wtmor_field_t;

typedef struct stc_rtc_wtyr_field
{
    union {
        struct {
            __IO   uint8_t  Y                    :4;
            __IO   uint8_t  TY                   :4;
        };
        struct {
            __IO   uint8_t  Y0                   :1;
            __IO   uint8_t  Y1                   :1;
            __IO   uint8_t  Y2                   :1;
            __IO   uint8_t  Y3                   :1;
            __IO   uint8_t  TY0                  :1;
            __IO   uint8_t  TY1                  :1;
            __IO   uint8_t  TY2                  :1;
            __IO   uint8_t  TY3                  :1;
        };
    };
} stc_rtc_wtyr_field_t;

typedef struct stc_rtc_almir_field
{
    union {
        struct {
            __IO   uint8_t  AMI                  :4;
            __IO   uint8_t  TAMI                 :3;
            __IO   uint8_t  RESERVED0            :1;
        };
        struct {
            __IO   uint8_t  AMI0                 :1;
            __IO   uint8_t  AMI1                 :1;
            __IO   uint8_t  AMI2                 :1;
            __IO   uint8_t  AMI3                 :1;
            __IO   uint8_t  TAMI0                :1;
            __IO   uint8_t  TAMI1                :1;
            __IO   uint8_t  TAMI2                :1;
            __IO   uint8_t  RESERVED1            :1;
        };
    };
} stc_rtc_almir_field_t;

typedef struct stc_rtc_alhr_field
{
    union {
        struct {
            __IO   uint8_t  AH                   :4;
            __IO   uint8_t  TAH                  :2;
            __IO   uint8_t  RESERVED0            :2;
        };
        struct {
            __IO   uint8_t  AH0                  :1;
            __IO   uint8_t  AH1                  :1;
            __IO   uint8_t  AH2                  :1;
            __IO   uint8_t  AH3                  :1;
            __IO   uint8_t  TAH0                 :1;
            __IO   uint8_t  TAH1                 :1;
            __IO   uint8_t  RESERVED1            :2;
        };
    };
} stc_rtc_alhr_field_t;

typedef struct stc_rtc_aldr_field
{
    union {
        struct {
            __IO   uint8_t  AD                   :4;
            __IO   uint8_t  TAD                  :2;
            __IO   uint8_t  RESERVED0            :2;
        };
        struct {
            __IO   uint8_t  AD0                  :1;
            __IO   uint8_t  AD1                  :1;
            __IO   uint8_t  AD2                  :1;
            __IO   uint8_t  AD3                  :1;
            __IO   uint8_t  TAD0                 :1;
            __IO   uint8_t  TAD1                 :1;
            __IO   uint8_t  RESERVED1            :2;
        };
    };
} stc_rtc_aldr_field_t;

typedef struct stc_rtc_almor_field
{
    union {
        struct {
            __IO   uint8_t  AMO                  :4;
            __IO   uint8_t  TAMO                 :1;
            __IO   uint8_t  RESERVED0            :3;
        };
        struct {
            __IO   uint8_t  AMO0                 :1;
            __IO   uint8_t  AMO1                 :1;
            __IO   uint8_t  AMO2                 :1;
            __IO   uint8_t  AMO3                 :1;
            __IO   uint8_t  RESERVED1            :4;
        };
    };
} stc_rtc_almor_field_t;

typedef struct stc_rtc_alyr_field
{
    union {
        struct {
            __IO   uint8_t  AY                   :4;
            __IO   uint8_t  TAY                  :4;
        };
        struct {
            __IO   uint8_t  AY0                  :1;
            __IO   uint8_t  AY1                  :1;
            __IO   uint8_t  AY2                  :1;
            __IO   uint8_t  AY3                  :1;
            __IO   uint8_t  TAY0                 :1;
            __IO   uint8_t  TAY1                 :1;
            __IO   uint8_t  TAY2                 :1;
            __IO   uint8_t  TAY3                 :1;
        };
    };
} stc_rtc_alyr_field_t;

typedef struct stc_rtc_wttr0_field
{
    union {
        struct {
            __IO   uint8_t  TM                   :8;
        };
        struct {
            __IO   uint8_t  TM0                  :1;
            __IO   uint8_t  TM1                  :1;
            __IO   uint8_t  TM2                  :1;
            __IO   uint8_t  TM3                  :1;
            __IO   uint8_t  TM4                  :1;
            __IO   uint8_t  TM5                  :1;
            __IO   uint8_t  TM6                  :1;
            __IO   uint8_t  TM7                  :1;
        };
    };
} stc_rtc_wttr0_field_t;

typedef struct stc_rtc_wttr1_field
{
    union {
        struct {
            __IO   uint8_t  TM                   :8;
        };
        struct {
            __IO   uint8_t  TM0                  :1;
            __IO   uint8_t  TM1                  :1;
            __IO   uint8_t  TM2                  :1;
            __IO   uint8_t  TM3                  :1;
            __IO   uint8_t  TM4                  :1;
            __IO   uint8_t  TM5                  :1;
            __IO   uint8_t  TM6                  :1;
            __IO   uint8_t  TM7                  :1;
        };
    };
} stc_rtc_wttr1_field_t;

typedef struct stc_rtc_wttr2_field
{
    union {
        struct {
            __IO   uint8_t  TM                   :2;
            __IO   uint8_t  RESERVED0            :6;
        };
        struct {
            __IO   uint8_t  TM0                  :1;
            __IO   uint8_t  TM1                  :1;
            __IO   uint8_t  RESERVED1            :6;
        };
    };
} stc_rtc_wttr2_field_t;

typedef struct stc_rtc_wtcal0_field
{
    union {
        struct {
            __IO   uint8_t  WTCAL0               :8;
        };
        struct {
            __IO   uint8_t  WTCAL00              :1;
            __IO   uint8_t  WTCAL01              :1;
            __IO   uint8_t  WTCAL02              :1;
            __IO   uint8_t  WTCAL03              :1;
            __IO   uint8_t  WTCAL04              :1;
            __IO   uint8_t  WTCAL05              :1;
            __IO   uint8_t  WTCAL06              :1;
            __IO   uint8_t  WTCAL07              :1;
        };
    };
} stc_rtc_wtcal0_field_t;

typedef struct stc_rtc_wtcal1_field
{
    union {
        struct {
            __IO   uint8_t  WTCAL1               :2;
            __IO   uint8_t  RESERVED0            :6;
        };
        struct {
            __IO   uint8_t  WTCAL10              :1;
            __IO   uint8_t  WTCAL11              :1;
            __IO   uint8_t  RESERVED1            :6;
        };
    };
} stc_rtc_wtcal1_field_t;

typedef struct stc_rtc_wtcalen_field
{
        __IO   uint8_t  WTCALEN                  :1;
        __IO   uint8_t  RESERVED0                :7;
} stc_rtc_wtcalen_field_t;

typedef struct stc_rtc_wtdiv_field
{
    union {
        struct {
            __IO   uint8_t  WTDIV                :4;
            __IO   uint8_t  RESERVED0            :4;
        };
        struct {
            __IO   uint8_t  WTDIV0               :1;
            __IO   uint8_t  WTDIV1               :1;
            __IO   uint8_t  WTDIV2               :1;
            __IO   uint8_t  WTDIV3               :1;
            __IO   uint8_t  RESERVED1            :4;
        };
    };
} stc_rtc_wtdiv_field_t;

typedef struct stc_rtc_wtdiven_field
{
        __IO   uint8_t  WTDIVEN                  :1;
        __IO   uint8_t  WTDIVRDY                 :1;
        __IO   uint8_t  RESERVED0                :6;
} stc_rtc_wtdiven_field_t;

typedef struct stc_rtc_wtcalprd_field
{
    union {
        struct {
            __IO   uint8_t  WTCALPRD             :6;
            __IO   uint8_t  RESERVED0            :2;
        };
        struct {
            __IO   uint8_t  WTCALPRD0            :1;
            __IO   uint8_t  WTCALPRD1            :1;
            __IO   uint8_t  WTCALPRD2            :1;
            __IO   uint8_t  WTCALPRD3            :1;
            __IO   uint8_t  WTCALPRD4            :1;
            __IO   uint8_t  WTCALPRD5            :1;
            __IO   uint8_t  RESERVED1            :2;
        };
    };
} stc_rtc_wtcalprd_field_t;

typedef struct stc_rtc_wtcosel_field
{
        __IO   uint8_t  WTCOSEL                  :1;
        __IO   uint8_t  RESERVED0                :7;
} stc_rtc_wtcosel_field_t;

typedef struct stc_rtc_vb_clkdiv_field
{
    union {
        struct {
            __IO   uint8_t  DIV                  :8;
        };
        struct {
            __IO   uint8_t  DIV0                 :1;
            __IO   uint8_t  DIV1                 :1;
            __IO   uint8_t  DIV2                 :1;
            __IO   uint8_t  DIV3                 :1;
            __IO   uint8_t  DIV4                 :1;
            __IO   uint8_t  DIV5                 :1;
            __IO   uint8_t  DIV6                 :1;
            __IO   uint8_t  DIV7                 :1;
        };
    };
} stc_rtc_vb_clkdiv_field_t;

typedef struct stc_rtc_wtosccnt_field
{
        __IO   uint8_t  SOSCEX                   :1;
        __IO   uint8_t  SOSCNTL                  :1;
        __IO   uint8_t  RESERVED0                :6;
} stc_rtc_wtosccnt_field_t;

typedef struct stc_rtc_ccs_field
{
    union {
        struct {
            __IO   uint8_t  CCS                  :8;
        };
        struct {
            __IO   uint8_t  CCS0                 :1;
            __IO   uint8_t  CCS1                 :1;
            __IO   uint8_t  CCS2                 :1;
            __IO   uint8_t  CCS3                 :1;
            __IO   uint8_t  CCS4                 :1;
            __IO   uint8_t  CCS5                 :1;
            __IO   uint8_t  CCS6                 :1;
            __IO   uint8_t  CCS7                 :1;
        };
    };
} stc_rtc_ccs_field_t;

typedef struct stc_rtc_ccb_field
{
    union {
        struct {
            __IO   uint8_t  CCB                  :8;
        };
        struct {
            __IO   uint8_t  CCB0                 :1;
            __IO   uint8_t  CCB1                 :1;
            __IO   uint8_t  CCB2                 :1;
            __IO   uint8_t  CCB3                 :1;
            __IO   uint8_t  CCB4                 :1;
            __IO   uint8_t  CCB5                 :1;
            __IO   uint8_t  CCB6                 :1;
            __IO   uint8_t  CCB7                 :1;
        };
    };
} stc_rtc_ccb_field_t;

typedef struct stc_rtc_boost_field
{
    union {
        struct {
            __IO   uint8_t  BOOST                :2;
            __IO   uint8_t  RESERVED0            :6;
        };
        struct {
            __IO   uint8_t  BOOST0               :1;
            __IO   uint8_t  BOOST1               :1;
            __IO   uint8_t  RESERVED1            :6;
        };
    };
} stc_rtc_boost_field_t;

typedef struct stc_rtc_ewkup_field
{
        __IO   uint8_t  WUP0                     :1;
        __IO   uint8_t  RESERVED0                :7;
} stc_rtc_ewkup_field_t;

typedef struct stc_rtc_vdet_field
{
        __IO   uint8_t  RESERVED0                :7;
        __IO   uint8_t  PON                      :1;
} stc_rtc_vdet_field_t;

typedef struct stc_rtc_hibrst_field
{
        __IO   uint8_t  HIBRST                   :1;
        __IO   uint8_t  RESERVED0                :7;
} stc_rtc_hibrst_field_t;

typedef struct stc_rtc_vbpfr_field
{
    union {
        struct {
            __IO   uint8_t  VPFR0                :1;
            __IO   uint8_t  VPFR1                :1;
            __IO   uint8_t  VPFR2                :1;
            __IO   uint8_t  VPFR3                :1;
            __IO   uint8_t  SPSR                 :2;
            __IO   uint8_t  RESERVED1            :2;
        };
        struct {
            __IO   uint8_t  RESERVED0            :4;
            __IO   uint8_t  SPSR0                :1;
            __IO   uint8_t  SPSR1                :1;
            __IO   uint8_t  RESERVED2            :2;
        };
    };
} stc_rtc_vbpfr_field_t;

typedef struct stc_rtc_vbpcr_field
{
        __IO   uint8_t  VPCR0                    :1;
        __IO   uint8_t  VPCR1                    :1;
        __IO   uint8_t  VPCR2                    :1;
        __IO   uint8_t  VPCR3                    :1;
        __IO   uint8_t  RESERVED0                :4;
} stc_rtc_vbpcr_field_t;

typedef struct stc_rtc_vbddr_field
{
        __IO   uint8_t  VDDR0                    :1;
        __IO   uint8_t  VDDR1                    :1;
        __IO   uint8_t  VDDR2                    :1;
        __IO   uint8_t  VDDR3                    :1;
        __IO   uint8_t  RESERVED0                :4;
} stc_rtc_vbddr_field_t;

typedef struct stc_rtc_vbdir_field
{
        __IO   uint8_t  VDIR0                    :1;
        __IO   uint8_t  VDIR1                    :1;
        __IO   uint8_t  VDIR2                    :1;
        __IO   uint8_t  VDIR3                    :1;
        __IO   uint8_t  RESERVED0                :4;
} stc_rtc_vbdir_field_t;

typedef struct stc_rtc_vbdor_field
{
        __IO   uint8_t  VDOR0                    :1;
        __IO   uint8_t  VDOR1                    :1;
        __IO   uint8_t  VDOR2                    :1;
        __IO   uint8_t  VDOR3                    :1;
        __IO   uint8_t  RESERVED0                :4;
} stc_rtc_vbdor_field_t;

typedef struct stc_rtc_vbpzr_field
{
        __IO   uint8_t  VPZR0                    :1;
        __IO   uint8_t  VPZR1                    :1;
        __IO   uint8_t  RESERVED0                :6;
} stc_rtc_vbpzr_field_t;

/*******************************************************************************
* SBSSR_MODULE
*******************************************************************************/
typedef struct stc_sbssr_btsssr_field
{
        __IO  uint16_t  SSSR0                    :1;
        __IO  uint16_t  SSSR1                    :1;
        __IO  uint16_t  SSSR2                    :1;
        __IO  uint16_t  SSSR3                    :1;
        __IO  uint16_t  SSSR4                    :1;
        __IO  uint16_t  SSSR5                    :1;
        __IO  uint16_t  SSSR6                    :1;
        __IO  uint16_t  SSSR7                    :1;
        __IO  uint16_t  SSSR8                    :1;
        __IO  uint16_t  SSSR9                    :1;
        __IO  uint16_t  SSSR10                   :1;
        __IO  uint16_t  SSSR11                   :1;
        __IO  uint16_t  SSSR12                   :1;
        __IO  uint16_t  SSSR13                   :1;
        __IO  uint16_t  SSSR14                   :1;
        __IO  uint16_t  SSSR15                   :1;
} stc_sbssr_btsssr_field_t;

/*******************************************************************************
* SDIF_MODULE
*******************************************************************************/
typedef struct stc_sdif_sbsize_field
{
    union {
        struct {
            __IO  uint16_t  TRSFBLCKSZ           :12;
            __IO  uint16_t  HSDMABUFBD           :3;
            __IO  uint16_t  RESERVED0            :1;
        };
        struct {
            __IO  uint16_t  TRSFBLCKSZ0          :1;
            __IO  uint16_t  TRSFBLCKSZ1          :1;
            __IO  uint16_t  TRSFBLCKSZ2          :1;
            __IO  uint16_t  TRSFBLCKSZ3          :1;
            __IO  uint16_t  TRSFBLCKSZ4          :1;
            __IO  uint16_t  TRSFBLCKSZ5          :1;
            __IO  uint16_t  TRSFBLCKSZ6          :1;
            __IO  uint16_t  TRSFBLCKSZ7          :1;
            __IO  uint16_t  TRSFBLCKSZ8          :1;
            __IO  uint16_t  TRSFBLCKSZ9          :1;
            __IO  uint16_t  TRSFBLCKSZ10         :1;
            __IO  uint16_t  TRSFBLCKSZ11         :1;
            __IO  uint16_t  HSDMABUFBD0          :1;
            __IO  uint16_t  HSDMABUFBD1          :1;
            __IO  uint16_t  HSDMABUFBD2          :1;
            __IO  uint16_t  RESERVED1            :1;
        };
    };
} stc_sdif_sbsize_field_t;

typedef struct stc_sdif_strsfmd_field
{
    union {
        struct {
            __IO  uint16_t  DMAEN                :1;
            __IO  uint16_t  BLCKCNTEN            :1;
            __IO  uint16_t  AUTOCMDEN            :2;
            __IO  uint16_t  DTTRSFDIR            :1;
            __IO  uint16_t  BLCKCNTSEL           :1;
            __IO  uint16_t  RESERVED1            :10;
        };
        struct {
            __IO  uint16_t  RESERVED0            :2;
            __IO  uint16_t  AUTOCMDEN0           :1;
            __IO  uint16_t  AUTOCMDEN1           :1;
            __IO  uint16_t  RESERVED2            :12;
        };
    };
} stc_sdif_strsfmd_field_t;

typedef struct stc_sdif_scmmd_field
{
    union {
        struct {
            __IO  uint16_t  RESPTYPE             :2;
            __IO  uint16_t  RESERVED0            :1;
            __IO  uint16_t  CMDCRCCHKE           :1;
            __IO  uint16_t  CMDIDXCHKE           :1;
            __IO  uint16_t  DATPRESSEL           :1;
            __IO  uint16_t  CMDTYPE              :2;
            __IO  uint16_t  CMDINDEX             :6;
            __IO  uint16_t  RESERVED2            :2;
        };
        struct {
            __IO  uint16_t  RESPTYPE0            :1;
            __IO  uint16_t  RESPTYPE1            :1;
            __IO  uint16_t  RESERVED1            :4;
            __IO  uint16_t  CMDTYPE0             :1;
            __IO  uint16_t  CMDTYPE1             :1;
            __IO  uint16_t  CMDINDEX0            :1;
            __IO  uint16_t  CMDINDEX1            :1;
            __IO  uint16_t  CMDINDEX2            :1;
            __IO  uint16_t  CMDINDEX3            :1;
            __IO  uint16_t  CMDINDEX4            :1;
            __IO  uint16_t  CMDINDEX5            :1;
            __IO  uint16_t  RESERVED3            :2;
        };
    };
} stc_sdif_scmmd_field_t;

typedef struct stc_sdif_sprstat_field
{
    union {
        struct {
            __IO  uint32_t  CMDINH               :1;
            __IO  uint32_t  CMDDATINH            :1;
            __IO  uint32_t  DATLNACT             :1;
            __IO  uint32_t  RETUNEREQ            :1;
            __IO  uint32_t  RESERVED0            :4;
            __IO  uint32_t  WRTRSFACT            :1;
            __IO  uint32_t  RDTRSFACT            :1;
            __IO  uint32_t  BUFWREN              :1;
            __IO  uint32_t  BUFRDEN              :1;
            __IO  uint32_t  RESERVED1            :4;
            __IO  uint32_t  CARDINS              :1;
            __IO  uint32_t  CARDSTB              :1;
            __IO  uint32_t  CARDDET              :1;
            __IO  uint32_t  WPPINLVL             :1;
            __IO  uint32_t  LNSGNLVL             :4;
            __IO  uint32_t  CMDLNSGN             :1;
            __IO  uint32_t  RESERVED3            :7;
        };
        struct {
            __IO  uint32_t  RESERVED2            :20;
            __IO  uint32_t  LNSGNLVL0            :1;
            __IO  uint32_t  LNSGNLVL1            :1;
            __IO  uint32_t  LNSGNLVL2            :1;
            __IO  uint32_t  LNSGNLVL3            :1;
            __IO  uint32_t  RESERVED4            :8;
        };
    };
} stc_sdif_sprstat_field_t;

typedef struct stc_sdif_shctl1_field
{
    union {
        struct {
            __IO   uint8_t  LEDCTRL              :1;
            __IO   uint8_t  DATAWIDTH            :1;
            __IO   uint8_t  HIGHSPDEN            :1;
            __IO   uint8_t  DMASEL               :2;
            __IO   uint8_t  EXTDTWIDTH           :1;
            __IO   uint8_t  CDTSTLVL             :1;
            __IO   uint8_t  CDSGNSEL             :1;
        };
        struct {
            __IO   uint8_t  RESERVED0            :3;
            __IO   uint8_t  DMASEL0              :1;
            __IO   uint8_t  DMASEL1              :1;
            __IO   uint8_t  RESERVED1            :3;
        };
    };
} stc_sdif_shctl1_field_t;

typedef struct stc_sdif_spwrctl_field
{
    union {
        struct {
            __IO   uint8_t  SDBUSPWR             :1;
            __IO   uint8_t  SDBUSVLSEL           :3;
            __IO   uint8_t  RESERVED1            :4;
        };
        struct {
            __IO   uint8_t  RESERVED0            :1;
            __IO   uint8_t  SDBUSVLSEL0          :1;
            __IO   uint8_t  SDBUSVLSEL1          :1;
            __IO   uint8_t  SDBUSVLSEL2          :1;
            __IO   uint8_t  RESERVED2            :4;
        };
    };
} stc_sdif_spwrctl_field_t;

typedef struct stc_sdif_sblkgpctl_field
{
        __IO   uint8_t  BLCKGSTPREQ              :1;
        __IO   uint8_t  CONTREQ                  :1;
        __IO   uint8_t  RDWAITCTL                :1;
        __IO   uint8_t  BLCKGAPINT               :1;
        __IO   uint8_t  RESERVED0                :4;
} stc_sdif_sblkgpctl_field_t;

typedef struct stc_sdif_swkupctl_field
{
        __IO   uint8_t  WKUPEVNTEN0              :1;
        __IO   uint8_t  WKUPEVNTEN1              :1;
        __IO   uint8_t  WKUPEVNTEN2              :1;
        __IO   uint8_t  RESERVED0                :5;
} stc_sdif_swkupctl_field_t;

typedef struct stc_sdif_sclkctl_field
{
    union {
        struct {
            __IO  uint16_t  INTLCLCKEN           :1;
            __IO  uint16_t  INTLCLCKST           :1;
            __IO  uint16_t  SDCLCKEN             :1;
            __IO  uint16_t  RESERVED0            :2;
            __IO  uint16_t  CLCKGENSEL           :1;
            __IO  uint16_t  UPSDCLKSEL           :2;
            __IO  uint16_t  SDCLKSEL             :8;
        };
        struct {
            __IO  uint16_t  RESERVED1            :6;
            __IO  uint16_t  UPSDCLKSEL0          :1;
            __IO  uint16_t  UPSDCLKSEL1          :1;
            __IO  uint16_t  SDCLKSEL0            :1;
            __IO  uint16_t  SDCLKSEL1            :1;
            __IO  uint16_t  SDCLKSEL2            :1;
            __IO  uint16_t  SDCLKSEL3            :1;
            __IO  uint16_t  SDCLKSEL4            :1;
            __IO  uint16_t  SDCLKSEL5            :1;
            __IO  uint16_t  SDCLKSEL6            :1;
            __IO  uint16_t  SDCLKSEL7            :1;
        };
    };
} stc_sdif_sclkctl_field_t;

typedef struct stc_sdif_stoctl_field
{
    union {
        struct {
            __IO   uint8_t  DTTMOUTVAL           :4;
            __IO   uint8_t  RESERVED0            :4;
        };
        struct {
            __IO   uint8_t  DTTMOUTVAL0          :1;
            __IO   uint8_t  DTTMOUTVAL1          :1;
            __IO   uint8_t  DTTMOUTVAL2          :1;
            __IO   uint8_t  DTTMOUTVAL3          :1;
            __IO   uint8_t  RESERVED1            :4;
        };
    };
} stc_sdif_stoctl_field_t;

typedef struct stc_sdif_ssrst_field
{
        __IO   uint8_t  SWRSTALL                 :1;
        __IO   uint8_t  SWRSTCMDLN               :1;
        __IO   uint8_t  SWRSTDATLN               :1;
        __IO   uint8_t  RESERVED0                :5;
} stc_sdif_ssrst_field_t;

typedef struct stc_sdif_snintst_field
{
        __IO  uint16_t  CMDCMPLT                 :1;
        __IO  uint16_t  TRSFCMPLT                :1;
        __IO  uint16_t  BLCKGEVNT                :1;
        __IO  uint16_t  DMAINT                   :1;
        __IO  uint16_t  BUFWRRDY                 :1;
        __IO  uint16_t  BUFRDRDY                 :1;
        __IO  uint16_t  CARDINS                  :1;
        __IO  uint16_t  CARDRMV                  :1;
        __IO  uint16_t  CARDINT                  :1;
        __IO  uint16_t  INT_A                    :1;
        __IO  uint16_t  INT_B                    :1;
        __IO  uint16_t  INT_C                    :1;
        __IO  uint16_t  RETUNEEVT                :1;
        __IO  uint16_t  RESERVED0                :2;
        __IO  uint16_t  ERRORINT                 :1;
} stc_sdif_snintst_field_t;

typedef struct stc_sdif_seintst_field
{
        __IO  uint16_t  CMDTOERR                 :1;
        __IO  uint16_t  CMDCRCERR                :1;
        __IO  uint16_t  CMDEBERR                 :1;
        __IO  uint16_t  CMDIDXERR                :1;
        __IO  uint16_t  DTTOERR                  :1;
        __IO  uint16_t  DTCRCERR                 :1;
        __IO  uint16_t  DTEBERR                  :1;
        __IO  uint16_t  CRTLMTERR                :1;
        __IO  uint16_t  ACMD12ERR                :1;
        __IO  uint16_t  ADMAERR                  :1;
        __IO  uint16_t  TUNINGERR                :1;
        __IO  uint16_t  RESERVED0                :1;
        __IO  uint16_t  BTACKERR                 :1;
        __IO  uint16_t  ACMD19ERR                :1;
        __IO  uint16_t  AHBMSTERR                :1;
        __IO  uint16_t  RESERVED1                :1;
} stc_sdif_seintst_field_t;

typedef struct stc_sdif_snintste_field
{
        __IO  uint16_t  CMDCMPLTS                :1;
        __IO  uint16_t  TRSFCMPLTS               :1;
        __IO  uint16_t  BLCKGEVNTS               :1;
        __IO  uint16_t  DMAINTS                  :1;
        __IO  uint16_t  BUFWRRDYS                :1;
        __IO  uint16_t  BUFRDRDYS                :1;
        __IO  uint16_t  CARDINSS                 :1;
        __IO  uint16_t  CARDRMVS                 :1;
        __IO  uint16_t  CARDINTS                 :1;
        __IO  uint16_t  INT_AS                   :1;
        __IO  uint16_t  INT_BS                   :1;
        __IO  uint16_t  INT_CS                   :1;
        __IO  uint16_t  RETUNEEVTS               :1;
        __IO  uint16_t  RESERVED0                :3;
} stc_sdif_snintste_field_t;

typedef struct stc_sdif_seintste_field
{
        __IO  uint16_t  CMDTOERRS                :1;
        __IO  uint16_t  CMDCRCERRS               :1;
        __IO  uint16_t  CMDEBERRS                :1;
        __IO  uint16_t  CMDIDXERRS               :1;
        __IO  uint16_t  DTTOERRS                 :1;
        __IO  uint16_t  DTCRCERRS                :1;
        __IO  uint16_t  DTEBERRS                 :1;
        __IO  uint16_t  CRTLMTERRS               :1;
        __IO  uint16_t  ACMD12ERRS               :1;
        __IO  uint16_t  ADMAERRS                 :1;
        __IO  uint16_t  TUNINGERRS               :1;
        __IO  uint16_t  RESERVED0                :1;
        __IO  uint16_t  BTACKERRS                :1;
        __IO  uint16_t  ACMD19ERRS               :1;
        __IO  uint16_t  AHBMSTERRS               :1;
        __IO  uint16_t  RESERVED1                :1;
} stc_sdif_seintste_field_t;

typedef struct stc_sdif_snintsge_field
{
        __IO  uint16_t  CMDCMPLTG                :1;
        __IO  uint16_t  TRSFCMPLTG               :1;
        __IO  uint16_t  BLCKGEVNTG               :1;
        __IO  uint16_t  DMAINTG                  :1;
        __IO  uint16_t  BUFWRRDYG                :1;
        __IO  uint16_t  BUFRDRDYG                :1;
        __IO  uint16_t  CARDINSG                 :1;
        __IO  uint16_t  CARDRMVG                 :1;
        __IO  uint16_t  CARDINTG                 :1;
        __IO  uint16_t  INT_AG                   :1;
        __IO  uint16_t  INT_BG                   :1;
        __IO  uint16_t  INT_CG                   :1;
        __IO  uint16_t  RETUNEEVTG               :1;
        __IO  uint16_t  RESERVED0                :3;
} stc_sdif_snintsge_field_t;

typedef struct stc_sdif_seintsge_field
{
        __IO  uint16_t  CMDTOERRG                :1;
        __IO  uint16_t  CMDCRCERRG               :1;
        __IO  uint16_t  CMDEBERRG                :1;
        __IO  uint16_t  CMDIDXERRG               :1;
        __IO  uint16_t  DTTOERRG                 :1;
        __IO  uint16_t  DTCRCERRG                :1;
        __IO  uint16_t  DTEBERRG                 :1;
        __IO  uint16_t  CRTLMTERRG               :1;
        __IO  uint16_t  ACMD12ERRG               :1;
        __IO  uint16_t  ADMAERRG                 :1;
        __IO  uint16_t  TUNINGERRG               :1;
        __IO  uint16_t  RESERVED0                :1;
        __IO  uint16_t  BTACKERRG                :1;
        __IO  uint16_t  ACMD19ERRG               :1;
        __IO  uint16_t  AHBMSTERRG               :1;
        __IO  uint16_t  RESERVED1                :1;
} stc_sdif_seintsge_field_t;

typedef struct stc_sdif_sacmdest_field
{
        __IO  uint16_t  ACMD12NOEX               :1;
        __IO  uint16_t  ACMDTOERR                :1;
        __IO  uint16_t  ACMDCRCERR               :1;
        __IO  uint16_t  ACMDEBERR                :1;
        __IO  uint16_t  ACMDIDXERR               :1;
        __IO  uint16_t  RESERVED0                :2;
        __IO  uint16_t  CMDND12ERR               :1;
        __IO  uint16_t  RESERVED1                :8;
} stc_sdif_sacmdest_field_t;

typedef struct stc_sdif_shctl2_field
{
    union {
        struct {
            __IO  uint16_t  UHSMDSEL             :3;
            __IO  uint16_t  V18SGNEN             :1;
            __IO  uint16_t  DRVSEL               :2;
            __IO  uint16_t  DOTUING              :1;
            __IO  uint16_t  SMPCLKSEL            :1;
            __IO  uint16_t  RESERVED1            :6;
            __IO  uint16_t  ASYINTEN             :1;
            __IO  uint16_t  PREVALEN             :1;
        };
        struct {
            __IO  uint16_t  UHSMDSEL0            :1;
            __IO  uint16_t  UHSMDSEL1            :1;
            __IO  uint16_t  UHSMDSEL2            :1;
            __IO  uint16_t  RESERVED0            :1;
            __IO  uint16_t  DRVSEL0              :1;
            __IO  uint16_t  DRVSEL1              :1;
            __IO  uint16_t  RESERVED2            :10;
        };
    };
} stc_sdif_shctl2_field_t;

typedef struct stc_sdif_capblty0_field
{
    union {
        struct {
            __IO  uint16_t  TOCLKFREQ            :6;
            __IO  uint16_t  RESERVED0            :1;
            __IO  uint16_t  TOCLKUNIT            :1;
            __IO  uint16_t  SDBASECLK            :8;
        };
        struct {
            __IO  uint16_t  TOCLKFREQ0           :1;
            __IO  uint16_t  TOCLKFREQ1           :1;
            __IO  uint16_t  TOCLKFREQ2           :1;
            __IO  uint16_t  TOCLKFREQ3           :1;
            __IO  uint16_t  TOCLKFREQ4           :1;
            __IO  uint16_t  TOCLKFREQ5           :1;
            __IO  uint16_t  RESERVED1            :2;
            __IO  uint16_t  SDBASECLK0           :1;
            __IO  uint16_t  SDBASECLK1           :1;
            __IO  uint16_t  SDBASECLK2           :1;
            __IO  uint16_t  SDBASECLK3           :1;
            __IO  uint16_t  SDBASECLK4           :1;
            __IO  uint16_t  SDBASECLK5           :1;
            __IO  uint16_t  SDBASECLK6           :1;
            __IO  uint16_t  SDBASECLK7           :1;
        };
    };
} stc_sdif_capblty0_field_t;

typedef struct stc_sdif_capblty1_field
{
    union {
        struct {
            __IO  uint16_t  MAXBLCKLEN           :2;
            __IO  uint16_t  EMBD8BIT             :1;
            __IO  uint16_t  ADMA2SPT             :1;
            __IO  uint16_t  RESERVED0            :1;
            __IO  uint16_t  HGHSPDSPT            :1;
            __IO  uint16_t  SDMASPT              :1;
            __IO  uint16_t  LWPWRSPT             :1;
            __IO  uint16_t  V33SPT               :1;
            __IO  uint16_t  V30SPT               :1;
            __IO  uint16_t  V18SPT               :1;
            __IO  uint16_t  RESERVED1            :1;
            __IO  uint16_t  BUS64SPT             :1;
            __IO  uint16_t  ASYINTSPT            :1;
            __IO  uint16_t  STOPTYPE             :2;
        };
        struct {
            __IO  uint16_t  MAXBLCKLEN0          :1;
            __IO  uint16_t  MAXBLCKLEN1          :1;
            __IO  uint16_t  RESERVED2            :12;
            __IO  uint16_t  STOPTYPE0            :1;
            __IO  uint16_t  STOPTYPE1            :1;
        };
    };
} stc_sdif_capblty1_field_t;

typedef struct stc_sdif_capblty2_field
{
    union {
        struct {
            __IO  uint16_t  SDR50SPT             :1;
            __IO  uint16_t  SDR104SPT            :1;
            __IO  uint16_t  DDR50SPT             :1;
            __IO  uint16_t  RESERVED0            :1;
            __IO  uint16_t  DRVTPASPT            :1;
            __IO  uint16_t  DRVTPCSPT            :1;
            __IO  uint16_t  DRVTPDSPT            :1;
            __IO  uint16_t  RESERVED1            :1;
            __IO  uint16_t  TMCNTRETN            :4;
            __IO  uint16_t  RESERVED3            :1;
            __IO  uint16_t  USETNSDR50           :1;
            __IO  uint16_t  RETNMODE             :2;
        };
        struct {
            __IO  uint16_t  RESERVED2            :8;
            __IO  uint16_t  TMCNTRETN0           :1;
            __IO  uint16_t  TMCNTRETN1           :1;
            __IO  uint16_t  TMCNTRETN2           :1;
            __IO  uint16_t  TMCNTRETN3           :1;
            __IO  uint16_t  RESERVED4            :2;
            __IO  uint16_t  RETNMODE0            :1;
            __IO  uint16_t  RETNMODE1            :1;
        };
    };
} stc_sdif_capblty2_field_t;

typedef struct stc_sdif_capblty3_field
{
    union {
        struct {
            __IO  uint16_t  CLKMULTPL            :8;
            __IO  uint16_t  RESERVED0            :8;
        };
        struct {
            __IO  uint16_t  CLKMULTPL0           :1;
            __IO  uint16_t  CLKMULTPL1           :1;
            __IO  uint16_t  CLKMULTPL2           :1;
            __IO  uint16_t  CLKMULTPL3           :1;
            __IO  uint16_t  CLKMULTPL4           :1;
            __IO  uint16_t  CLKMULTPL5           :1;
            __IO  uint16_t  CLKMULTPL6           :1;
            __IO  uint16_t  CLKMULTPL7           :1;
            __IO  uint16_t  RESERVED1            :8;
        };
    };
} stc_sdif_capblty3_field_t;

typedef struct stc_sdif_mxccapy0_field
{
    union {
        struct {
            __IO  uint16_t  V33MAXCUR            :8;
            __IO  uint16_t  V30MAXCUR            :8;
        };
        struct {
            __IO  uint16_t  V33MAXCUR0           :1;
            __IO  uint16_t  V33MAXCUR1           :1;
            __IO  uint16_t  V33MAXCUR2           :1;
            __IO  uint16_t  V33MAXCUR3           :1;
            __IO  uint16_t  V33MAXCUR4           :1;
            __IO  uint16_t  V33MAXCUR5           :1;
            __IO  uint16_t  V33MAXCUR6           :1;
            __IO  uint16_t  V33MAXCUR7           :1;
            __IO  uint16_t  V30MAXCUR0           :1;
            __IO  uint16_t  V30MAXCUR1           :1;
            __IO  uint16_t  V30MAXCUR2           :1;
            __IO  uint16_t  V30MAXCUR3           :1;
            __IO  uint16_t  V30MAXCUR4           :1;
            __IO  uint16_t  V30MAXCUR5           :1;
            __IO  uint16_t  V30MAXCUR6           :1;
            __IO  uint16_t  V30MAXCUR7           :1;
        };
    };
} stc_sdif_mxccapy0_field_t;

typedef struct stc_sdif_mxccapy1_field
{
    union {
        struct {
            __IO  uint16_t  V18MAXCUR            :8;
            __IO  uint16_t  RESERVED0            :8;
        };
        struct {
            __IO  uint16_t  V18MAXCUR0           :1;
            __IO  uint16_t  V18MAXCUR1           :1;
            __IO  uint16_t  V18MAXCUR2           :1;
            __IO  uint16_t  V18MAXCUR3           :1;
            __IO  uint16_t  V18MAXCUR4           :1;
            __IO  uint16_t  V18MAXCUR5           :1;
            __IO  uint16_t  V18MAXCUR6           :1;
            __IO  uint16_t  V18MAXCUR7           :1;
            __IO  uint16_t  RESERVED1            :8;
        };
    };
} stc_sdif_mxccapy1_field_t;

typedef struct stc_sdif_feacest_field
{
        __IO  uint16_t  FEVNT12ND                :1;
        __IO  uint16_t  FEVNTTO                  :1;
        __IO  uint16_t  FEVNTCRC                 :1;
        __IO  uint16_t  FEVNTEB                  :1;
        __IO  uint16_t  FEVNTIDX                 :1;
        __IO  uint16_t  RESERVED0                :2;
        __IO  uint16_t  FEVNTCMD12               :1;
        __IO  uint16_t  RESERVED1                :8;
} stc_sdif_feacest_field_t;

typedef struct stc_sdif_sfeeist_field
{
        __IO  uint16_t  FETOERR                  :1;
        __IO  uint16_t  FECRCERR                 :1;
        __IO  uint16_t  FEEBERR                  :1;
        __IO  uint16_t  FEIDXERR                 :1;
        __IO  uint16_t  FEDTOTERR                :1;
        __IO  uint16_t  FEDTCRCERR               :1;
        __IO  uint16_t  FEDTEBERR                :1;
        __IO  uint16_t  FECRLTERR                :1;
        __IO  uint16_t  FEA12ERR                 :1;
        __IO  uint16_t  FEADMAERR                :1;
        __IO  uint16_t  FETUNEERR                :1;
        __IO  uint16_t  RESERVED0                :1;
        __IO  uint16_t  FEACKERR                 :1;
        __IO  uint16_t  FEA19ERR                 :1;
        __IO  uint16_t  FEAHBMSERR               :1;
        __IO  uint16_t  RESERVED1                :1;
} stc_sdif_sfeeist_field_t;

typedef struct stc_sdif_admaest_field
{
    union {
        struct {
            __IO   uint8_t  ADMAERRS             :2;
            __IO   uint8_t  ADMALENME            :1;
            __IO   uint8_t  RESERVED0            :5;
        };
        struct {
            __IO   uint8_t  ADMAERRS0            :1;
            __IO   uint8_t  ADMAERRS1            :1;
            __IO   uint8_t  RESERVED1            :6;
        };
    };
} stc_sdif_admaest_field_t;

typedef struct stc_sdif_sadsa0_field
{
    union {
        struct {
            __IO  uint16_t  ADR1500              :16;
        };
        struct {
            __IO  uint16_t  ADR15000             :1;
            __IO  uint16_t  ADR15001             :1;
            __IO  uint16_t  ADR15002             :1;
            __IO  uint16_t  ADR15003             :1;
            __IO  uint16_t  ADR15004             :1;
            __IO  uint16_t  ADR15005             :1;
            __IO  uint16_t  ADR15006             :1;
            __IO  uint16_t  ADR15007             :1;
            __IO  uint16_t  ADR15008             :1;
            __IO  uint16_t  ADR15009             :1;
            __IO  uint16_t  ADR150010            :1;
            __IO  uint16_t  ADR150011            :1;
            __IO  uint16_t  ADR150012            :1;
            __IO  uint16_t  ADR150013            :1;
            __IO  uint16_t  ADR150014            :1;
            __IO  uint16_t  ADR150015            :1;
        };
    };
} stc_sdif_sadsa0_field_t;

typedef struct stc_sdif_sadsa1_field
{
    union {
        struct {
            __IO  uint16_t  ADR3116              :16;
        };
        struct {
            __IO  uint16_t  ADR31160             :1;
            __IO  uint16_t  ADR31161             :1;
            __IO  uint16_t  ADR31162             :1;
            __IO  uint16_t  ADR31163             :1;
            __IO  uint16_t  ADR31164             :1;
            __IO  uint16_t  ADR31165             :1;
            __IO  uint16_t  ADR31166             :1;
            __IO  uint16_t  ADR31167             :1;
            __IO  uint16_t  ADR31168             :1;
            __IO  uint16_t  ADR31169             :1;
            __IO  uint16_t  ADR311610            :1;
            __IO  uint16_t  ADR311611            :1;
            __IO  uint16_t  ADR311612            :1;
            __IO  uint16_t  ADR311613            :1;
            __IO  uint16_t  ADR311614            :1;
            __IO  uint16_t  ADR311615            :1;
        };
    };
} stc_sdif_sadsa1_field_t;

typedef struct stc_sdif_sadsa2_field
{
    union {
        struct {
            __IO  uint16_t  ADR4732              :16;
        };
        struct {
            __IO  uint16_t  ADR47320             :1;
            __IO  uint16_t  ADR47321             :1;
            __IO  uint16_t  ADR47322             :1;
            __IO  uint16_t  ADR47323             :1;
            __IO  uint16_t  ADR47324             :1;
            __IO  uint16_t  ADR47325             :1;
            __IO  uint16_t  ADR47326             :1;
            __IO  uint16_t  ADR47327             :1;
            __IO  uint16_t  ADR47328             :1;
            __IO  uint16_t  ADR47329             :1;
            __IO  uint16_t  ADR473210            :1;
            __IO  uint16_t  ADR473211            :1;
            __IO  uint16_t  ADR473212            :1;
            __IO  uint16_t  ADR473213            :1;
            __IO  uint16_t  ADR473214            :1;
            __IO  uint16_t  ADR473215            :1;
        };
    };
} stc_sdif_sadsa2_field_t;

typedef struct stc_sdif_sadsa3_field
{
    union {
        struct {
            __IO  uint16_t  ADR6348              :16;
        };
        struct {
            __IO  uint16_t  ADR63480             :1;
            __IO  uint16_t  ADR63481             :1;
            __IO  uint16_t  ADR63482             :1;
            __IO  uint16_t  ADR63483             :1;
            __IO  uint16_t  ADR63484             :1;
            __IO  uint16_t  ADR63485             :1;
            __IO  uint16_t  ADR63486             :1;
            __IO  uint16_t  ADR63487             :1;
            __IO  uint16_t  ADR63488             :1;
            __IO  uint16_t  ADR63489             :1;
            __IO  uint16_t  ADR634810            :1;
            __IO  uint16_t  ADR634811            :1;
            __IO  uint16_t  ADR634812            :1;
            __IO  uint16_t  ADR634813            :1;
            __IO  uint16_t  ADR634814            :1;
            __IO  uint16_t  ADR634815            :1;
        };
    };
} stc_sdif_sadsa3_field_t;

typedef struct stc_sdif_sprval0_field
{
    union {
        struct {
            __IO  uint16_t  SCFSELVAL            :10;
            __IO  uint16_t  CGSELVAL             :1;
            __IO  uint16_t  RESERVED0            :3;
            __IO  uint16_t  DSSELVAL             :2;
        };
        struct {
            __IO  uint16_t  SCFSELVAL0           :1;
            __IO  uint16_t  SCFSELVAL1           :1;
            __IO  uint16_t  SCFSELVAL2           :1;
            __IO  uint16_t  SCFSELVAL3           :1;
            __IO  uint16_t  SCFSELVAL4           :1;
            __IO  uint16_t  SCFSELVAL5           :1;
            __IO  uint16_t  SCFSELVAL6           :1;
            __IO  uint16_t  SCFSELVAL7           :1;
            __IO  uint16_t  SCFSELVAL8           :1;
            __IO  uint16_t  SCFSELVAL9           :1;
            __IO  uint16_t  RESERVED1            :4;
            __IO  uint16_t  DSSELVAL0            :1;
            __IO  uint16_t  DSSELVAL1            :1;
        };
    };
} stc_sdif_sprval0_field_t;

typedef struct stc_sdif_sprval1_field
{
    union {
        struct {
            __IO  uint16_t  SCFSELVAL            :10;
            __IO  uint16_t  CGSELVAL             :1;
            __IO  uint16_t  RESERVED0            :3;
            __IO  uint16_t  DSSELVAL             :2;
        };
        struct {
            __IO  uint16_t  SCFSELVAL0           :1;
            __IO  uint16_t  SCFSELVAL1           :1;
            __IO  uint16_t  SCFSELVAL2           :1;
            __IO  uint16_t  SCFSELVAL3           :1;
            __IO  uint16_t  SCFSELVAL4           :1;
            __IO  uint16_t  SCFSELVAL5           :1;
            __IO  uint16_t  SCFSELVAL6           :1;
            __IO  uint16_t  SCFSELVAL7           :1;
            __IO  uint16_t  SCFSELVAL8           :1;
            __IO  uint16_t  SCFSELVAL9           :1;
            __IO  uint16_t  RESERVED1            :4;
            __IO  uint16_t  DSSELVAL0            :1;
            __IO  uint16_t  DSSELVAL1            :1;
        };
    };
} stc_sdif_sprval1_field_t;

typedef struct stc_sdif_sprval2_field
{
    union {
        struct {
            __IO  uint16_t  SCFSELVAL            :10;
            __IO  uint16_t  CGSELVAL             :1;
            __IO  uint16_t  RESERVED0            :3;
            __IO  uint16_t  DSSELVAL             :2;
        };
        struct {
            __IO  uint16_t  SCFSELVAL0           :1;
            __IO  uint16_t  SCFSELVAL1           :1;
            __IO  uint16_t  SCFSELVAL2           :1;
            __IO  uint16_t  SCFSELVAL3           :1;
            __IO  uint16_t  SCFSELVAL4           :1;
            __IO  uint16_t  SCFSELVAL5           :1;
            __IO  uint16_t  SCFSELVAL6           :1;
            __IO  uint16_t  SCFSELVAL7           :1;
            __IO  uint16_t  SCFSELVAL8           :1;
            __IO  uint16_t  SCFSELVAL9           :1;
            __IO  uint16_t  RESERVED1            :4;
            __IO  uint16_t  DSSELVAL0            :1;
            __IO  uint16_t  DSSELVAL1            :1;
        };
    };
} stc_sdif_sprval2_field_t;

typedef struct stc_sdif_sprval3_field
{
    union {
        struct {
            __IO  uint16_t  SCFSELVAL            :10;
            __IO  uint16_t  CGSELVAL             :1;
            __IO  uint16_t  RESERVED0            :3;
            __IO  uint16_t  DSSELVAL             :2;
        };
        struct {
            __IO  uint16_t  SCFSELVAL0           :1;
            __IO  uint16_t  SCFSELVAL1           :1;
            __IO  uint16_t  SCFSELVAL2           :1;
            __IO  uint16_t  SCFSELVAL3           :1;
            __IO  uint16_t  SCFSELVAL4           :1;
            __IO  uint16_t  SCFSELVAL5           :1;
            __IO  uint16_t  SCFSELVAL6           :1;
            __IO  uint16_t  SCFSELVAL7           :1;
            __IO  uint16_t  SCFSELVAL8           :1;
            __IO  uint16_t  SCFSELVAL9           :1;
            __IO  uint16_t  RESERVED1            :4;
            __IO  uint16_t  DSSELVAL0            :1;
            __IO  uint16_t  DSSELVAL1            :1;
        };
    };
} stc_sdif_sprval3_field_t;

typedef struct stc_sdif_sprval4_field
{
    union {
        struct {
            __IO  uint16_t  SCFSELVAL            :10;
            __IO  uint16_t  CGSELVAL             :1;
            __IO  uint16_t  RESERVED0            :3;
            __IO  uint16_t  DSSELVAL             :2;
        };
        struct {
            __IO  uint16_t  SCFSELVAL0           :1;
            __IO  uint16_t  SCFSELVAL1           :1;
            __IO  uint16_t  SCFSELVAL2           :1;
            __IO  uint16_t  SCFSELVAL3           :1;
            __IO  uint16_t  SCFSELVAL4           :1;
            __IO  uint16_t  SCFSELVAL5           :1;
            __IO  uint16_t  SCFSELVAL6           :1;
            __IO  uint16_t  SCFSELVAL7           :1;
            __IO  uint16_t  SCFSELVAL8           :1;
            __IO  uint16_t  SCFSELVAL9           :1;
            __IO  uint16_t  RESERVED1            :4;
            __IO  uint16_t  DSSELVAL0            :1;
            __IO  uint16_t  DSSELVAL1            :1;
        };
    };
} stc_sdif_sprval4_field_t;

typedef struct stc_sdif_sprval5_field
{
    union {
        struct {
            __IO  uint16_t  SCFSELVAL            :10;
            __IO  uint16_t  CGSELVAL             :1;
            __IO  uint16_t  RESERVED0            :3;
            __IO  uint16_t  DSSELVAL             :2;
        };
        struct {
            __IO  uint16_t  SCFSELVAL0           :1;
            __IO  uint16_t  SCFSELVAL1           :1;
            __IO  uint16_t  SCFSELVAL2           :1;
            __IO  uint16_t  SCFSELVAL3           :1;
            __IO  uint16_t  SCFSELVAL4           :1;
            __IO  uint16_t  SCFSELVAL5           :1;
            __IO  uint16_t  SCFSELVAL6           :1;
            __IO  uint16_t  SCFSELVAL7           :1;
            __IO  uint16_t  SCFSELVAL8           :1;
            __IO  uint16_t  SCFSELVAL9           :1;
            __IO  uint16_t  RESERVED1            :4;
            __IO  uint16_t  DSSELVAL0            :1;
            __IO  uint16_t  DSSELVAL1            :1;
        };
    };
} stc_sdif_sprval5_field_t;

typedef struct stc_sdif_sprval6_field
{
    union {
        struct {
            __IO  uint16_t  SCFSELVAL            :10;
            __IO  uint16_t  CGSELVAL             :1;
            __IO  uint16_t  RESERVED0            :3;
            __IO  uint16_t  DSSELVAL             :2;
        };
        struct {
            __IO  uint16_t  SCFSELVAL0           :1;
            __IO  uint16_t  SCFSELVAL1           :1;
            __IO  uint16_t  SCFSELVAL2           :1;
            __IO  uint16_t  SCFSELVAL3           :1;
            __IO  uint16_t  SCFSELVAL4           :1;
            __IO  uint16_t  SCFSELVAL5           :1;
            __IO  uint16_t  SCFSELVAL6           :1;
            __IO  uint16_t  SCFSELVAL7           :1;
            __IO  uint16_t  SCFSELVAL8           :1;
            __IO  uint16_t  SCFSELVAL9           :1;
            __IO  uint16_t  RESERVED1            :4;
            __IO  uint16_t  DSSELVAL0            :1;
            __IO  uint16_t  DSSELVAL1            :1;
        };
    };
} stc_sdif_sprval6_field_t;

typedef struct stc_sdif_sprval7_field
{
    union {
        struct {
            __IO  uint16_t  SCFSELVAL            :10;
            __IO  uint16_t  CGSELVAL             :1;
            __IO  uint16_t  RESERVED0            :3;
            __IO  uint16_t  DSSELVAL             :2;
        };
        struct {
            __IO  uint16_t  SCFSELVAL0           :1;
            __IO  uint16_t  SCFSELVAL1           :1;
            __IO  uint16_t  SCFSELVAL2           :1;
            __IO  uint16_t  SCFSELVAL3           :1;
            __IO  uint16_t  SCFSELVAL4           :1;
            __IO  uint16_t  SCFSELVAL5           :1;
            __IO  uint16_t  SCFSELVAL6           :1;
            __IO  uint16_t  SCFSELVAL7           :1;
            __IO  uint16_t  SCFSELVAL8           :1;
            __IO  uint16_t  SCFSELVAL9           :1;
            __IO  uint16_t  RESERVED1            :4;
            __IO  uint16_t  DSSELVAL0            :1;
            __IO  uint16_t  DSSELVAL1            :1;
        };
    };
} stc_sdif_sprval7_field_t;

typedef struct stc_sdif_sshbctll_field
{
    union {
        struct {
            __IO  uint16_t  CLCKPIN              :3;
            __IO  uint16_t  RESERVED0            :1;
            __IO  uint16_t  INTINPIN             :2;
            __IO  uint16_t  RESERVED2            :2;
            __IO  uint16_t  BUSWDPRST            :7;
            __IO  uint16_t  RESERVED4            :1;
        };
        struct {
            __IO  uint16_t  CLCKPIN0             :1;
            __IO  uint16_t  CLCKPIN1             :1;
            __IO  uint16_t  CLCKPIN2             :1;
            __IO  uint16_t  RESERVED1            :1;
            __IO  uint16_t  INTINPIN0            :1;
            __IO  uint16_t  INTINPIN1            :1;
            __IO  uint16_t  RESERVED3            :2;
            __IO  uint16_t  BUSWDPRST0           :1;
            __IO  uint16_t  BUSWDPRST1           :1;
            __IO  uint16_t  BUSWDPRST2           :1;
            __IO  uint16_t  BUSWDPRST3           :1;
            __IO  uint16_t  BUSWDPRST4           :1;
            __IO  uint16_t  BUSWDPRST5           :1;
            __IO  uint16_t  BUSWDPRST6           :1;
            __IO  uint16_t  RESERVED5            :1;
        };
    };
} stc_sdif_sshbctll_field_t;

typedef struct stc_sdif_sshbctlh_field
{
    union {
        struct {
            __IO  uint16_t  CLCKPINSEL           :3;
            __IO  uint16_t  RESERVED0            :1;
            __IO  uint16_t  INTPINSEL            :3;
            __IO  uint16_t  RESERVED2            :1;
            __IO  uint16_t  BEPWRCTL             :7;
            __IO  uint16_t  RESERVED4            :1;
        };
        struct {
            __IO  uint16_t  CLCKPINSEL0          :1;
            __IO  uint16_t  CLCKPINSEL1          :1;
            __IO  uint16_t  CLCKPINSEL2          :1;
            __IO  uint16_t  RESERVED1            :1;
            __IO  uint16_t  INTPINSEL0           :1;
            __IO  uint16_t  INTPINSEL1           :1;
            __IO  uint16_t  INTPINSEL2           :1;
            __IO  uint16_t  RESERVED3            :1;
            __IO  uint16_t  BEPWRCTL0            :1;
            __IO  uint16_t  BEPWRCTL1            :1;
            __IO  uint16_t  BEPWRCTL2            :1;
            __IO  uint16_t  BEPWRCTL3            :1;
            __IO  uint16_t  BEPWRCTL4            :1;
            __IO  uint16_t  BEPWRCTL5            :1;
            __IO  uint16_t  BEPWRCTL6            :1;
            __IO  uint16_t  RESERVED5            :1;
        };
    };
} stc_sdif_sshbctlh_field_t;

typedef struct stc_sdif_sslist_field
{
    union {
        struct {
            __IO  uint16_t  SLOTINTSGN           :8;
            __IO  uint16_t  RESERVED0            :8;
        };
        struct {
            __IO  uint16_t  SLOTINTSGN0          :1;
            __IO  uint16_t  SLOTINTSGN1          :1;
            __IO  uint16_t  SLOTINTSGN2          :1;
            __IO  uint16_t  SLOTINTSGN3          :1;
            __IO  uint16_t  SLOTINTSGN4          :1;
            __IO  uint16_t  SLOTINTSGN5          :1;
            __IO  uint16_t  SLOTINTSGN6          :1;
            __IO  uint16_t  SLOTINTSGN7          :1;
            __IO  uint16_t  RESERVED1            :8;
        };
    };
} stc_sdif_sslist_field_t;

typedef struct stc_sdif_shctlv_field
{
    union {
        struct {
            __IO  uint16_t  SPECVERNUM           :8;
            __IO  uint16_t  VNDVERNUM            :8;
        };
        struct {
            __IO  uint16_t  SPECVERNUM0          :1;
            __IO  uint16_t  SPECVERNUM1          :1;
            __IO  uint16_t  SPECVERNUM2          :1;
            __IO  uint16_t  SPECVERNUM3          :1;
            __IO  uint16_t  SPECVERNUM4          :1;
            __IO  uint16_t  SPECVERNUM5          :1;
            __IO  uint16_t  SPECVERNUM6          :1;
            __IO  uint16_t  SPECVERNUM7          :1;
            __IO  uint16_t  VNDVERNUM0           :1;
            __IO  uint16_t  VNDVERNUM1           :1;
            __IO  uint16_t  VNDVERNUM2           :1;
            __IO  uint16_t  VNDVERNUM3           :1;
            __IO  uint16_t  VNDVERNUM4           :1;
            __IO  uint16_t  VNDVERNUM5           :1;
            __IO  uint16_t  VNDVERNUM6           :1;
            __IO  uint16_t  VNDVERNUM7           :1;
        };
    };
} stc_sdif_shctlv_field_t;

typedef struct stc_sdif_ahbcfgl_field
{
    union {
        struct {
            __IO  uint16_t  INCRSEL              :3;
            __IO  uint16_t  SINEN                :1;
            __IO  uint16_t  BSLOCK               :1;
            __IO  uint16_t  BSLOCKSEL            :1;
            __IO  uint16_t  ENDIANSEL            :1;
            __IO  uint16_t  RESERVED0            :9;
        };
        struct {
            __IO  uint16_t  INCRSEL0             :1;
            __IO  uint16_t  INCRSEL1             :1;
            __IO  uint16_t  INCRSEL2             :1;
            __IO  uint16_t  RESERVED1            :13;
        };
    };
} stc_sdif_ahbcfgl_field_t;

typedef struct stc_sdif_spwswcl_field
{
        __IO  uint16_t  ATPWRSWEN                :1;
        __IO  uint16_t  IOREGSEL                 :1;
        __IO  uint16_t  RESERVED0                :14;
} stc_sdif_spwswcl_field_t;

typedef struct stc_sdif_stunsetl_field
{
    union {
        struct {
            __IO  uint16_t  TNPTSEL              :8;
            __IO  uint16_t  TNPHSELEN            :1;
            __IO  uint16_t  TNERRBDSEL           :1;
            __IO  uint16_t  RETNTAPSEL           :1;
            __IO  uint16_t  RETNRNGSEL           :2;
            __IO  uint16_t  RESERVED1            :3;
        };
        struct {
            __IO  uint16_t  TNPTSEL0             :1;
            __IO  uint16_t  TNPTSEL1             :1;
            __IO  uint16_t  TNPTSEL2             :1;
            __IO  uint16_t  TNPTSEL3             :1;
            __IO  uint16_t  TNPTSEL4             :1;
            __IO  uint16_t  TNPTSEL5             :1;
            __IO  uint16_t  TNPTSEL6             :1;
            __IO  uint16_t  TNPTSEL7             :1;
            __IO  uint16_t  RESERVED0            :3;
            __IO  uint16_t  RETNRNGSEL0          :1;
            __IO  uint16_t  RETNRNGSEL1          :1;
            __IO  uint16_t  RESERVED2            :3;
        };
    };
} stc_sdif_stunsetl_field_t;

typedef struct stc_sdif_stunseth_field
{
    union {
        struct {
            __IO  uint16_t  CMDCFCHKDS           :1;
            __IO  uint16_t  RESERVED0            :7;
            __IO  uint16_t  DTOTCNTVAL           :4;
            __IO  uint16_t  RESERVED2            :4;
        };
        struct {
            __IO  uint16_t  RESERVED1            :8;
            __IO  uint16_t  DTOTCNTVAL0          :1;
            __IO  uint16_t  DTOTCNTVAL1          :1;
            __IO  uint16_t  DTOTCNTVAL2          :1;
            __IO  uint16_t  DTOTCNTVAL3          :1;
            __IO  uint16_t  RESERVED3            :4;
        };
    };
} stc_sdif_stunseth_field_t;

typedef struct stc_sdif_stunstl_field
{
    union {
        struct {
            __IO  uint16_t  REP8TNRSLT           :8;
            __IO  uint16_t  REP3TNRSLT           :3;
            __IO  uint16_t  RESERVED0            :5;
        };
        struct {
            __IO  uint16_t  REP8TNRSLT0          :1;
            __IO  uint16_t  REP8TNRSLT1          :1;
            __IO  uint16_t  REP8TNRSLT2          :1;
            __IO  uint16_t  REP8TNRSLT3          :1;
            __IO  uint16_t  REP8TNRSLT4          :1;
            __IO  uint16_t  REP8TNRSLT5          :1;
            __IO  uint16_t  REP8TNRSLT6          :1;
            __IO  uint16_t  REP8TNRSLT7          :1;
            __IO  uint16_t  REP3TNRSLT0          :1;
            __IO  uint16_t  REP3TNRSLT1          :1;
            __IO  uint16_t  REP3TNRSLT2          :1;
            __IO  uint16_t  RESERVED1            :5;
        };
    };
} stc_sdif_stunstl_field_t;

typedef struct stc_sdif_stunsth_field
{
    union {
        struct {
            __IO  uint16_t  PRSTTNPNT            :8;
            __IO  uint16_t  RESERVED0            :8;
        };
        struct {
            __IO  uint16_t  PRSTTNPNT0           :1;
            __IO  uint16_t  PRSTTNPNT1           :1;
            __IO  uint16_t  PRSTTNPNT2           :1;
            __IO  uint16_t  PRSTTNPNT3           :1;
            __IO  uint16_t  PRSTTNPNT4           :1;
            __IO  uint16_t  PRSTTNPNT5           :1;
            __IO  uint16_t  PRSTTNPNT6           :1;
            __IO  uint16_t  PRSTTNPNT7           :1;
            __IO  uint16_t  RESERVED1            :8;
        };
    };
} stc_sdif_stunsth_field_t;

typedef struct stc_sdif_pswistl_field
{
        __IO  uint16_t  INT5MS                   :1;
        __IO  uint16_t  INT1MS                   :1;
        __IO  uint16_t  RESERVED0                :14;
} stc_sdif_pswistl_field_t;

typedef struct stc_sdif_pswistel_field
{
        __IO  uint16_t  INT5MSSTS                :1;
        __IO  uint16_t  INT1MSSTS                :1;
        __IO  uint16_t  RESERVED0                :14;
} stc_sdif_pswistel_field_t;

typedef struct stc_sdif_pswisgel_field
{
        __IO  uint16_t  INT5MSSGEN               :1;
        __IO  uint16_t  INT1MSSGEN               :1;
        __IO  uint16_t  RESERVED0                :14;
} stc_sdif_pswisgel_field_t;

typedef struct stc_sdif_mmcsdcl_field
{
        __IO  uint16_t  LCKRSTESD                :1;
        __IO  uint16_t  RSTMMC                   :1;
        __IO  uint16_t  VCCCTLMMC                :1;
        __IO  uint16_t  VCCQCTLMMC               :1;
        __IO  uint16_t  RESERVED0                :4;
        __IO  uint16_t  MMCDDRSEL                :1;
        __IO  uint16_t  CMDDATDLY                :1;
        __IO  uint16_t  RESERVED1                :6;
} stc_sdif_mmcsdcl_field_t;

typedef struct stc_sdif_mmcsdch_field
{
        __IO  uint16_t  BTACKENMMC               :1;
        __IO  uint16_t  BTABTENMMC               :1;
        __IO  uint16_t  BTMDENMMC                :1;
        __IO  uint16_t  RESERVED0                :13;
} stc_sdif_mmcsdch_field_t;

typedef struct stc_sdif_mcwirqc0_field
{
        __IO  uint16_t  WTIRQEN                  :1;
        __IO  uint16_t  WTIRQST                  :1;
        __IO  uint16_t  RESERVED0                :14;
} stc_sdif_mcwirqc0_field_t;

typedef struct stc_sdif_mcwirqc1_field
{
    union {
        struct {
            __IO  uint16_t  WTIRQCNCLR           :16;
        };
        struct {
            __IO  uint16_t  WTIRQCNCLR0          :1;
            __IO  uint16_t  WTIRQCNCLR1          :1;
            __IO  uint16_t  WTIRQCNCLR2          :1;
            __IO  uint16_t  WTIRQCNCLR3          :1;
            __IO  uint16_t  WTIRQCNCLR4          :1;
            __IO  uint16_t  WTIRQCNCLR5          :1;
            __IO  uint16_t  WTIRQCNCLR6          :1;
            __IO  uint16_t  WTIRQCNCLR7          :1;
            __IO  uint16_t  WTIRQCNCLR8          :1;
            __IO  uint16_t  WTIRQCNCLR9          :1;
            __IO  uint16_t  WTIRQCNCLR10         :1;
            __IO  uint16_t  WTIRQCNCLR11         :1;
            __IO  uint16_t  WTIRQCNCLR12         :1;
            __IO  uint16_t  WTIRQCNCLR13         :1;
            __IO  uint16_t  WTIRQCNCLR14         :1;
            __IO  uint16_t  WTIRQCNCLR15         :1;
        };
    };
} stc_sdif_mcwirqc1_field_t;

typedef struct stc_sdif_mcwirqc2_field
{
    union {
        struct {
            __IO  uint16_t  WTIRQCNCLR           :16;
        };
        struct {
            __IO  uint16_t  WTIRQCNCLR0          :1;
            __IO  uint16_t  WTIRQCNCLR1          :1;
            __IO  uint16_t  WTIRQCNCLR2          :1;
            __IO  uint16_t  WTIRQCNCLR3          :1;
            __IO  uint16_t  WTIRQCNCLR4          :1;
            __IO  uint16_t  WTIRQCNCLR5          :1;
            __IO  uint16_t  WTIRQCNCLR6          :1;
            __IO  uint16_t  WTIRQCNCLR7          :1;
            __IO  uint16_t  WTIRQCNCLR8          :1;
            __IO  uint16_t  WTIRQCNCLR9          :1;
            __IO  uint16_t  WTIRQCNCLR10         :1;
            __IO  uint16_t  WTIRQCNCLR11         :1;
            __IO  uint16_t  WTIRQCNCLR12         :1;
            __IO  uint16_t  WTIRQCNCLR13         :1;
            __IO  uint16_t  WTIRQCNCLR14         :1;
            __IO  uint16_t  WTIRQCNCLR15         :1;
        };
    };
} stc_sdif_mcwirqc2_field_t;

typedef struct stc_sdif_mcwirqc3_field
{
    union {
        struct {
            __IO  uint16_t  WTIRQCNCLR           :16;
        };
        struct {
            __IO  uint16_t  WTIRQCNCLR0          :1;
            __IO  uint16_t  WTIRQCNCLR1          :1;
            __IO  uint16_t  WTIRQCNCLR2          :1;
            __IO  uint16_t  WTIRQCNCLR3          :1;
            __IO  uint16_t  WTIRQCNCLR4          :1;
            __IO  uint16_t  WTIRQCNCLR5          :1;
            __IO  uint16_t  WTIRQCNCLR6          :1;
            __IO  uint16_t  WTIRQCNCLR7          :1;
            __IO  uint16_t  WTIRQCNCLR8          :1;
            __IO  uint16_t  WTIRQCNCLR9          :1;
            __IO  uint16_t  WTIRQCNCLR10         :1;
            __IO  uint16_t  WTIRQCNCLR11         :1;
            __IO  uint16_t  WTIRQCNCLR12         :1;
            __IO  uint16_t  WTIRQCNCLR13         :1;
            __IO  uint16_t  WTIRQCNCLR14         :1;
            __IO  uint16_t  WTIRQCNCLR15         :1;
        };
    };
} stc_sdif_mcwirqc3_field_t;

typedef struct stc_sdif_mcrpckbl_field
{
    union {
        struct {
            __IO  uint16_t  CHECKBIT1            :7;
            __IO  uint16_t  CHECKBIT2            :6;
            __IO  uint16_t  RESERVED0            :3;
        };
        struct {
            __IO  uint16_t  CHECKBIT10           :1;
            __IO  uint16_t  CHECKBIT11           :1;
            __IO  uint16_t  CHECKBIT12           :1;
            __IO  uint16_t  CHECKBIT13           :1;
            __IO  uint16_t  CHECKBIT14           :1;
            __IO  uint16_t  CHECKBIT15           :1;
            __IO  uint16_t  CHECKBIT16           :1;
            __IO  uint16_t  CHECKBIT20           :1;
            __IO  uint16_t  CHECKBIT21           :1;
            __IO  uint16_t  CHECKBIT22           :1;
            __IO  uint16_t  CHECKBIT23           :1;
            __IO  uint16_t  CHECKBIT24           :1;
            __IO  uint16_t  CHECKBIT25           :1;
            __IO  uint16_t  RESERVED1            :3;
        };
    };
} stc_sdif_mcrpckbl_field_t;

typedef struct stc_sdif_scdetecs_field
{
    union {
        struct {
            __IO  uint16_t  RESERVED0            :8;
            __IO  uint16_t  CDDEBTCVAL           :4;
            __IO  uint16_t  RESERVED2            :4;
        };
        struct {
            __IO  uint16_t  RESERVED1            :8;
            __IO  uint16_t  CDDEBTCVAL0          :1;
            __IO  uint16_t  CDDEBTCVAL1          :1;
            __IO  uint16_t  CDDEBTCVAL2          :1;
            __IO  uint16_t  CDDEBTCVAL3          :1;
            __IO  uint16_t  RESERVED3            :4;
        };
    };
} stc_sdif_scdetecs_field_t;

/*******************************************************************************
* SWWDT_MODULE
*******************************************************************************/
typedef struct stc_swwdt_wdogcontrol_field
{
    union {
        struct {
            __IO  uint32_t  INTEN                :1;
            __IO  uint32_t  RESEN                :1;
            __IO  uint32_t  TWD                  :2;
            __IO  uint32_t  SPM                  :1;
            __IO  uint32_t  RESERVED1            :27;
        };
        struct {
            __IO  uint32_t  RESERVED0            :2;
            __IO  uint32_t  TWD0                 :1;
            __IO  uint32_t  TWD1                 :1;
            __IO  uint32_t  RESERVED2            :28;
        };
    };
} stc_swwdt_wdogcontrol_field_t;

typedef struct stc_swwdt_wdogris_field
{
        __IO  uint32_t  RIS                      :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_swwdt_wdogris_field_t;

typedef struct stc_swwdt_wdogspmc_field
{
        __IO  uint32_t  TGR                      :1;
        __IO  uint32_t  RESERVED0                :31;
} stc_swwdt_wdogspmc_field_t;

/*******************************************************************************
* UNIQUE_ID_MODULE
*******************************************************************************/
typedef struct stc_unique_id_uidr0_field
{
    union {
        struct {
            __IO  uint32_t  RESERVED0            :4;
            __IO  uint32_t  UID                  :28;
        };
        struct {
            __IO  uint32_t  RESERVED1            :4;
            __IO  uint32_t  UID0                 :1;
            __IO  uint32_t  UID1                 :1;
            __IO  uint32_t  UID2                 :1;
            __IO  uint32_t  UID3                 :1;
            __IO  uint32_t  UID4                 :1;
            __IO  uint32_t  UID5                 :1;
            __IO  uint32_t  UID6                 :1;
            __IO  uint32_t  UID7                 :1;
            __IO  uint32_t  UID8                 :1;
            __IO  uint32_t  UID9                 :1;
            __IO  uint32_t  UID10                :1;
            __IO  uint32_t  UID11                :1;
            __IO  uint32_t  UID12                :1;
            __IO  uint32_t  UID13                :1;
            __IO  uint32_t  UID14                :1;
            __IO  uint32_t  UID15                :1;
            __IO  uint32_t  UID16                :1;
            __IO  uint32_t  UID17                :1;
            __IO  uint32_t  UID18                :1;
            __IO  uint32_t  UID19                :1;
            __IO  uint32_t  UID20                :1;
            __IO  uint32_t  UID21                :1;
            __IO  uint32_t  UID22                :1;
            __IO  uint32_t  UID23                :1;
            __IO  uint32_t  UID24                :1;
            __IO  uint32_t  UID25                :1;
            __IO  uint32_t  UID26                :1;
            __IO  uint32_t  UID27                :1;
        };
    };
} stc_unique_id_uidr0_field_t;

typedef struct stc_unique_id_uidr1_field
{
    union {
        struct {
            __IO  uint32_t  UID                  :13;
            __IO  uint32_t  RESERVED0            :19;
        };
        struct {
            __IO  uint32_t  UID0                 :1;
            __IO  uint32_t  UID1                 :1;
            __IO  uint32_t  UID2                 :1;
            __IO  uint32_t  UID3                 :1;
            __IO  uint32_t  UID4                 :1;
            __IO  uint32_t  UID5                 :1;
            __IO  uint32_t  UID6                 :1;
            __IO  uint32_t  UID7                 :1;
            __IO  uint32_t  UID8                 :1;
            __IO  uint32_t  UID9                 :1;
            __IO  uint32_t  UID10                :1;
            __IO  uint32_t  UID11                :1;
            __IO  uint32_t  UID12                :1;
            __IO  uint32_t  RESERVED1            :19;
        };
    };
} stc_unique_id_uidr1_field_t;

/*******************************************************************************
* USB_MODULE
*******************************************************************************/
typedef struct stc_usb_hcnt_field
{
        __IO  uint16_t  HOST                     :1;
        __IO  uint16_t  URST                     :1;
        __IO  uint16_t  SOFIRE                   :1;
        __IO  uint16_t  DIRE                     :1;
        __IO  uint16_t  CNNIRE                   :1;
        __IO  uint16_t  CMPIRE                   :1;
        __IO  uint16_t  URIRE                    :1;
        __IO  uint16_t  RWKIRE                   :1;
        __IO  uint16_t  RETRY                    :1;
        __IO  uint16_t  CANCEL                   :1;
        __IO  uint16_t  SOFSTEP                  :1;
        __IO  uint16_t  RESERVED0                :5;
} stc_usb_hcnt_field_t;

typedef struct stc_usb_hirq_field
{
        __IO   uint8_t  SOFIRQ                   :1;
        __IO   uint8_t  DIRQ                     :1;
        __IO   uint8_t  CNNIRQ                   :1;
        __IO   uint8_t  CMPIRQ                   :1;
        __IO   uint8_t  URIRQ                    :1;
        __IO   uint8_t  RWKIRQ                   :1;
        __IO   uint8_t  RESERVED0                :1;
        __IO   uint8_t  TCAN                     :1;
} stc_usb_hirq_field_t;

typedef struct stc_usb_herr_field
{
    union {
        struct {
            __IO   uint8_t  HS                   :2;
            __IO   uint8_t  STUFF                :1;
            __IO   uint8_t  TGERR                :1;
            __IO   uint8_t  CRC                  :1;
            __IO   uint8_t  TOUT                 :1;
            __IO   uint8_t  RERR                 :1;
            __IO   uint8_t  LSTSOF               :1;
        };
        struct {
            __IO   uint8_t  HS0                  :1;
            __IO   uint8_t  HS1                  :1;
            __IO   uint8_t  RESERVED0            :6;
        };
    };
} stc_usb_herr_field_t;

typedef struct stc_usb_hstate_field
{
        __IO   uint8_t  CSTAT                    :1;
        __IO   uint8_t  TMODE                    :1;
        __IO   uint8_t  SUSP                     :1;
        __IO   uint8_t  SOFBUSY                  :1;
        __IO   uint8_t  CLKSEL                   :1;
        __IO   uint8_t  ALIVE                    :1;
        __IO   uint8_t  RESERVED0                :2;
} stc_usb_hstate_field_t;

typedef struct stc_usb_hfcomp_field
{
    union {
        struct {
            __IO   uint8_t  FRAMECOMP            :8;
        };
        struct {
            __IO   uint8_t  FRAMECOMP0           :1;
            __IO   uint8_t  FRAMECOMP1           :1;
            __IO   uint8_t  FRAMECOMP2           :1;
            __IO   uint8_t  FRAMECOMP3           :1;
            __IO   uint8_t  FRAMECOMP4           :1;
            __IO   uint8_t  FRAMECOMP5           :1;
            __IO   uint8_t  FRAMECOMP6           :1;
            __IO   uint8_t  FRAMECOMP7           :1;
        };
    };
} stc_usb_hfcomp_field_t;

typedef struct stc_usb_hrtimer_field
{
    union {
        struct {
            __IO  uint16_t  RTIMER               :16;
        };
        struct {
            __IO  uint16_t  RTIMER0              :1;
            __IO  uint16_t  RTIMER1              :1;
            __IO  uint16_t  RTIMER2              :1;
            __IO  uint16_t  RTIMER3              :1;
            __IO  uint16_t  RTIMER4              :1;
            __IO  uint16_t  RTIMER5              :1;
            __IO  uint16_t  RTIMER6              :1;
            __IO  uint16_t  RTIMER7              :1;
            __IO  uint16_t  RTIMER8              :1;
            __IO  uint16_t  RTIMER9              :1;
            __IO  uint16_t  RTIMER10             :1;
            __IO  uint16_t  RTIMER11             :1;
            __IO  uint16_t  RTIMER12             :1;
            __IO  uint16_t  RTIMER13             :1;
            __IO  uint16_t  RTIMER14             :1;
            __IO  uint16_t  RTIMER15             :1;
        };
    };
} stc_usb_hrtimer_field_t;

typedef struct stc_usb_hrtimer2_field
{
    union {
        struct {
            __IO   uint8_t  RTIMER2              :2;
            __IO   uint8_t  RESERVED0            :6;
        };
        struct {
            __IO   uint8_t  RTIMER20             :1;
            __IO   uint8_t  RTIMER21             :1;
            __IO   uint8_t  RESERVED1            :6;
        };
    };
} stc_usb_hrtimer2_field_t;

typedef struct stc_usb_hadr_field
{
    union {
        struct {
            __IO   uint8_t  ADDRESS              :7;
            __IO   uint8_t  RESERVED0            :1;
        };
        struct {
            __IO   uint8_t  ADDRESS0             :1;
            __IO   uint8_t  ADDRESS1             :1;
            __IO   uint8_t  ADDRESS2             :1;
            __IO   uint8_t  ADDRESS3             :1;
            __IO   uint8_t  ADDRESS4             :1;
            __IO   uint8_t  ADDRESS5             :1;
            __IO   uint8_t  ADDRESS6             :1;
            __IO   uint8_t  RESERVED1            :1;
        };
    };
} stc_usb_hadr_field_t;

typedef struct stc_usb_heof_field
{
    union {
        struct {
            __IO  uint16_t  HEOF                 :14;
            __IO  uint16_t  RESERVED0            :2;
        };
        struct {
            __IO  uint16_t  HEOF0                :1;
            __IO  uint16_t  HEOF1                :1;
            __IO  uint16_t  HEOF2                :1;
            __IO  uint16_t  HEOF3                :1;
            __IO  uint16_t  HEOF4                :1;
            __IO  uint16_t  HEOF5                :1;
            __IO  uint16_t  HEOF6                :1;
            __IO  uint16_t  HEOF7                :1;
            __IO  uint16_t  HEOF8                :1;
            __IO  uint16_t  HEOF9                :1;
            __IO  uint16_t  HEOF10               :1;
            __IO  uint16_t  HEOF11               :1;
            __IO  uint16_t  HEOF12               :1;
            __IO  uint16_t  HEOF13               :1;
            __IO  uint16_t  RESERVED1            :2;
        };
    };
} stc_usb_heof_field_t;

typedef struct stc_usb_hframe_field
{
    union {
        struct {
            __IO  uint16_t  FRAME                :11;
            __IO  uint16_t  RESERVED0            :5;
        };
        struct {
            __IO  uint16_t  FRAME0               :1;
            __IO  uint16_t  FRAME1               :1;
            __IO  uint16_t  FRAME2               :1;
            __IO  uint16_t  FRAME3               :1;
            __IO  uint16_t  FRAME4               :1;
            __IO  uint16_t  FRAME5               :1;
            __IO  uint16_t  FRAME6               :1;
            __IO  uint16_t  FRAME7               :1;
            __IO  uint16_t  FRAME8               :1;
            __IO  uint16_t  FRAME9               :1;
            __IO  uint16_t  FRAME10              :1;
            __IO  uint16_t  RESERVED1            :5;
        };
    };
} stc_usb_hframe_field_t;

typedef struct stc_usb_htoken_field
{
    union {
        struct {
            __IO   uint8_t  ENDPT                :4;
            __IO   uint8_t  TKNEN                :3;
            __IO   uint8_t  TGGL                 :1;
        };
        struct {
            __IO   uint8_t  ENDPT0               :1;
            __IO   uint8_t  ENDPT1               :1;
            __IO   uint8_t  ENDPT2               :1;
            __IO   uint8_t  ENDPT3               :1;
            __IO   uint8_t  TKNEN0               :1;
            __IO   uint8_t  TKNEN1               :1;
            __IO   uint8_t  TKNEN2               :1;
            __IO   uint8_t  RESERVED0            :1;
        };
    };
} stc_usb_htoken_field_t;

typedef struct stc_usb_udcc_field
{
        __IO  uint16_t  PWC                      :1;
        __IO  uint16_t  RFBK                     :1;
        __IO  uint16_t  RESERVED0                :1;
        __IO  uint16_t  STALCLREN                :1;
        __IO  uint16_t  USTP                     :1;
        __IO  uint16_t  HCONX                    :1;
        __IO  uint16_t  RESUM                    :1;
        __IO  uint16_t  RST                      :1;
        __IO  uint16_t  RESERVED1                :8;
} stc_usb_udcc_field_t;

typedef struct stc_usb_ep0c_field
{
    union {
        struct {
            __IO  uint16_t  PKS                  :7;
            __IO  uint16_t  RESERVED0            :2;
            __IO  uint16_t  STAL                 :1;
            __IO  uint16_t  RESERVED1            :6;
        };
        struct {
            __IO  uint16_t  PKS0                 :1;
            __IO  uint16_t  PKS1                 :1;
            __IO  uint16_t  PKS2                 :1;
            __IO  uint16_t  PKS3                 :1;
            __IO  uint16_t  PKS4                 :1;
            __IO  uint16_t  PKS5                 :1;
            __IO  uint16_t  PKS6                 :1;
            __IO  uint16_t  RESERVED2            :9;
        };
    };
} stc_usb_ep0c_field_t;

typedef struct stc_usb_ep1c_field
{
    union {
        struct {
            __IO  uint16_t  PKS                  :9;
            __IO  uint16_t  STAL                 :1;
            __IO  uint16_t  NULE                 :1;
            __IO  uint16_t  DMAE                 :1;
            __IO  uint16_t  DIR                  :1;
            __IO  uint16_t  TYPE                 :2;
            __IO  uint16_t  EPEN                 :1;
        };
        struct {
            __IO  uint16_t  PKS0                 :1;
            __IO  uint16_t  PKS1                 :1;
            __IO  uint16_t  PKS2                 :1;
            __IO  uint16_t  PKS3                 :1;
            __IO  uint16_t  PKS4                 :1;
            __IO  uint16_t  PKS5                 :1;
            __IO  uint16_t  PKS6                 :1;
            __IO  uint16_t  PKS7                 :1;
            __IO  uint16_t  PKS8                 :1;
            __IO  uint16_t  RESERVED0            :4;
            __IO  uint16_t  TYPE0                :1;
            __IO  uint16_t  TYPE1                :1;
            __IO  uint16_t  RESERVED1            :1;
        };
    };
} stc_usb_ep1c_field_t;

typedef struct stc_usb_ep2c_field
{
    union {
        struct {
            __IO  uint16_t  PKS                  :7;
            __IO  uint16_t  RESERVED0            :2;
            __IO  uint16_t  STAL                 :1;
            __IO  uint16_t  NULE                 :1;
            __IO  uint16_t  DMAE                 :1;
            __IO  uint16_t  DIR                  :1;
            __IO  uint16_t  TYPE                 :2;
            __IO  uint16_t  EPEN                 :1;
        };
        struct {
            __IO  uint16_t  PKS0                 :1;
            __IO  uint16_t  PKS1                 :1;
            __IO  uint16_t  PKS2                 :1;
            __IO  uint16_t  PKS3                 :1;
            __IO  uint16_t  PKS4                 :1;
            __IO  uint16_t  PKS5                 :1;
            __IO  uint16_t  PKS6                 :1;
            __IO  uint16_t  RESERVED1            :6;
            __IO  uint16_t  TYPE0                :1;
            __IO  uint16_t  TYPE1                :1;
            __IO  uint16_t  RESERVED2            :1;
        };
    };
} stc_usb_ep2c_field_t;

typedef struct stc_usb_ep3c_field
{
    union {
        struct {
            __IO  uint16_t  PKS                  :7;
            __IO  uint16_t  RESERVED0            :2;
            __IO  uint16_t  STAL                 :1;
            __IO  uint16_t  NULE                 :1;
            __IO  uint16_t  DMAE                 :1;
            __IO  uint16_t  DIR                  :1;
            __IO  uint16_t  TYPE                 :2;
            __IO  uint16_t  EPEN                 :1;
        };
        struct {
            __IO  uint16_t  PKS0                 :1;
            __IO  uint16_t  PKS1                 :1;
            __IO  uint16_t  PKS2                 :1;
            __IO  uint16_t  PKS3                 :1;
            __IO  uint16_t  PKS4                 :1;
            __IO  uint16_t  PKS5                 :1;
            __IO  uint16_t  PKS6                 :1;
            __IO  uint16_t  RESERVED1            :6;
            __IO  uint16_t  TYPE0                :1;
            __IO  uint16_t  TYPE1                :1;
            __IO  uint16_t  RESERVED2            :1;
        };
    };
} stc_usb_ep3c_field_t;

typedef struct stc_usb_ep4c_field
{
    union {
        struct {
            __IO  uint16_t  PKS                  :7;
            __IO  uint16_t  RESERVED0            :2;
            __IO  uint16_t  STAL                 :1;
            __IO  uint16_t  NULE                 :1;
            __IO  uint16_t  DMAE                 :1;
            __IO  uint16_t  DIR                  :1;
            __IO  uint16_t  TYPE                 :2;
            __IO  uint16_t  EPEN                 :1;
        };
        struct {
            __IO  uint16_t  PKS0                 :1;
            __IO  uint16_t  PKS1                 :1;
            __IO  uint16_t  PKS2                 :1;
            __IO  uint16_t  PKS3                 :1;
            __IO  uint16_t  PKS4                 :1;
            __IO  uint16_t  PKS5                 :1;
            __IO  uint16_t  PKS6                 :1;
            __IO  uint16_t  RESERVED1            :6;
            __IO  uint16_t  TYPE0                :1;
            __IO  uint16_t  TYPE1                :1;
            __IO  uint16_t  RESERVED2            :1;
        };
    };
} stc_usb_ep4c_field_t;

typedef struct stc_usb_ep5c_field
{
    union {
        struct {
            __IO  uint16_t  PKS                  :7;
            __IO  uint16_t  RESERVED0            :2;
            __IO  uint16_t  STAL                 :1;
            __IO  uint16_t  NULE                 :1;
            __IO  uint16_t  DMAE                 :1;
            __IO  uint16_t  DIR                  :1;
            __IO  uint16_t  TYPE                 :2;
            __IO  uint16_t  EPEN                 :1;
        };
        struct {
            __IO  uint16_t  PKS0                 :1;
            __IO  uint16_t  PKS1                 :1;
            __IO  uint16_t  PKS2                 :1;
            __IO  uint16_t  PKS3                 :1;
            __IO  uint16_t  PKS4                 :1;
            __IO  uint16_t  PKS5                 :1;
            __IO  uint16_t  PKS6                 :1;
            __IO  uint16_t  RESERVED1            :6;
            __IO  uint16_t  TYPE0                :1;
            __IO  uint16_t  TYPE1                :1;
            __IO  uint16_t  RESERVED2            :1;
        };
    };
} stc_usb_ep5c_field_t;

typedef struct stc_usb_tmsp_field
{
    union {
        struct {
            __IO  uint16_t  TMSP                 :11;
            __IO  uint16_t  RESERVED0            :5;
        };
        struct {
            __IO  uint16_t  TMSP0                :1;
            __IO  uint16_t  TMSP1                :1;
            __IO  uint16_t  TMSP2                :1;
            __IO  uint16_t  TMSP3                :1;
            __IO  uint16_t  TMSP4                :1;
            __IO  uint16_t  TMSP5                :1;
            __IO  uint16_t  TMSP6                :1;
            __IO  uint16_t  TMSP7                :1;
            __IO  uint16_t  TMSP8                :1;
            __IO  uint16_t  TMSP9                :1;
            __IO  uint16_t  TMSP10               :1;
            __IO  uint16_t  RESERVED1            :5;
        };
    };
} stc_usb_tmsp_field_t;

typedef struct stc_usb_udcs_field
{
        __IO   uint8_t  CONF                     :1;
        __IO   uint8_t  SETP                     :1;
        __IO   uint8_t  WKUP                     :1;
        __IO   uint8_t  BRST                     :1;
        __IO   uint8_t  SOF                      :1;
        __IO   uint8_t  SUSP                     :1;
        __IO   uint8_t  RESERVED0                :2;
} stc_usb_udcs_field_t;

typedef struct stc_usb_udcie_field
{
        __IO   uint8_t  CONFIE                   :1;
        __IO   uint8_t  CONFN                    :1;
        __IO   uint8_t  WKUPIE                   :1;
        __IO   uint8_t  BRSTIE                   :1;
        __IO   uint8_t  SOFIE                    :1;
        __IO   uint8_t  SUSPIE                   :1;
        __IO   uint8_t  RESERVED0                :2;
} stc_usb_udcie_field_t;

typedef struct stc_usb_ep0is_field
{
        __IO  uint16_t  RESERVED0                :10;
        __IO  uint16_t  DRQI                     :1;
        __IO  uint16_t  RESERVED1                :3;
        __IO  uint16_t  DRQIIE                   :1;
        __IO  uint16_t  BFINI                    :1;
} stc_usb_ep0is_field_t;

typedef struct stc_usb_ep0os_field
{
    union {
        struct {
            __IO  uint16_t  SIZE                 :7;
            __IO  uint16_t  RESERVED0            :2;
            __IO  uint16_t  SPK                  :1;
            __IO  uint16_t  DRQO                 :1;
            __IO  uint16_t  RESERVED1            :2;
            __IO  uint16_t  SPKIE                :1;
            __IO  uint16_t  DRQOIE               :1;
            __IO  uint16_t  BFINI                :1;
        };
        struct {
            __IO  uint16_t  SIZE0                :1;
            __IO  uint16_t  SIZE1                :1;
            __IO  uint16_t  SIZE2                :1;
            __IO  uint16_t  SIZE3                :1;
            __IO  uint16_t  SIZE4                :1;
            __IO  uint16_t  SIZE5                :1;
            __IO  uint16_t  SIZE6                :1;
            __IO  uint16_t  RESERVED2            :9;
        };
    };
} stc_usb_ep0os_field_t;

typedef struct stc_usb_ep1s_field
{
    union {
        struct {
            __IO  uint16_t  SIZE                 :9;
            __IO  uint16_t  SPK                  :1;
            __IO  uint16_t  DRQ                  :1;
            __IO  uint16_t  BUSY                 :1;
            __IO  uint16_t  RESERVED0            :1;
            __IO  uint16_t  SPKIE                :1;
            __IO  uint16_t  DRQIE                :1;
            __IO  uint16_t  BFINI                :1;
        };
        struct {
            __IO  uint16_t  SIZE0                :1;
            __IO  uint16_t  SIZE1                :1;
            __IO  uint16_t  SIZE2                :1;
            __IO  uint16_t  SIZE3                :1;
            __IO  uint16_t  SIZE4                :1;
            __IO  uint16_t  SIZE5                :1;
            __IO  uint16_t  SIZE6                :1;
            __IO  uint16_t  SIZE7                :1;
            __IO  uint16_t  SIZE8                :1;
            __IO  uint16_t  RESERVED1            :7;
        };
    };
} stc_usb_ep1s_field_t;

typedef struct stc_usb_ep2s_field
{
    union {
        struct {
            __IO  uint16_t  SIZE                 :7;
            __IO  uint16_t  RESERVED0            :2;
            __IO  uint16_t  SPK                  :1;
            __IO  uint16_t  DRQ                  :1;
            __IO  uint16_t  BUSY                 :1;
            __IO  uint16_t  RESERVED1            :1;
            __IO  uint16_t  SPKIE                :1;
            __IO  uint16_t  DRQIE                :1;
            __IO  uint16_t  BFINI                :1;
        };
        struct {
            __IO  uint16_t  SIZE0                :1;
            __IO  uint16_t  SIZE1                :1;
            __IO  uint16_t  SIZE2                :1;
            __IO  uint16_t  SIZE3                :1;
            __IO  uint16_t  SIZE4                :1;
            __IO  uint16_t  SIZE5                :1;
            __IO  uint16_t  SIZE6                :1;
            __IO  uint16_t  RESERVED2            :9;
        };
    };
} stc_usb_ep2s_field_t;

typedef struct stc_usb_ep3s_field
{
    union {
        struct {
            __IO  uint16_t  SIZE                 :7;
            __IO  uint16_t  RESERVED0            :2;
            __IO  uint16_t  SPK                  :1;
            __IO  uint16_t  DRQ                  :1;
            __IO  uint16_t  BUSY                 :1;
            __IO  uint16_t  RESERVED1            :1;
            __IO  uint16_t  SPKIE                :1;
            __IO  uint16_t  DRQIE                :1;
            __IO  uint16_t  BFINI                :1;
        };
        struct {
            __IO  uint16_t  SIZE0                :1;
            __IO  uint16_t  SIZE1                :1;
            __IO  uint16_t  SIZE2                :1;
            __IO  uint16_t  SIZE3                :1;
            __IO  uint16_t  SIZE4                :1;
            __IO  uint16_t  SIZE5                :1;
            __IO  uint16_t  SIZE6                :1;
            __IO  uint16_t  RESERVED2            :9;
        };
    };
} stc_usb_ep3s_field_t;

typedef struct stc_usb_ep4s_field
{
    union {
        struct {
            __IO  uint16_t  SIZE                 :7;
            __IO  uint16_t  RESERVED0            :2;
            __IO  uint16_t  SPK                  :1;
            __IO  uint16_t  DRQ                  :1;
            __IO  uint16_t  BUSY                 :1;
            __IO  uint16_t  RESERVED1            :1;
            __IO  uint16_t  SPKIE                :1;
            __IO  uint16_t  DRQIE                :1;
            __IO  uint16_t  BFINI                :1;
        };
        struct {
            __IO  uint16_t  SIZE0                :1;
            __IO  uint16_t  SIZE1                :1;
            __IO  uint16_t  SIZE2                :1;
            __IO  uint16_t  SIZE3                :1;
            __IO  uint16_t  SIZE4                :1;
            __IO  uint16_t  SIZE5                :1;
            __IO  uint16_t  SIZE6                :1;
            __IO  uint16_t  RESERVED2            :9;
        };
    };
} stc_usb_ep4s_field_t;

typedef struct stc_usb_ep5s_field
{
    union {
        struct {
            __IO  uint16_t  SIZE                 :7;
            __IO  uint16_t  RESERVED0            :2;
            __IO  uint16_t  SPK                  :1;
            __IO  uint16_t  DRQ                  :1;
            __IO  uint16_t  BUSY                 :1;
            __IO  uint16_t  RESERVED1            :1;
            __IO  uint16_t  SPKIE                :1;
            __IO  uint16_t  DRQIE                :1;
            __IO  uint16_t  BFINI                :1;
        };
        struct {
            __IO  uint16_t  SIZE0                :1;
            __IO  uint16_t  SIZE1                :1;
            __IO  uint16_t  SIZE2                :1;
            __IO  uint16_t  SIZE3                :1;
            __IO  uint16_t  SIZE4                :1;
            __IO  uint16_t  SIZE5                :1;
            __IO  uint16_t  SIZE6                :1;
            __IO  uint16_t  RESERVED2            :9;
        };
    };
} stc_usb_ep5s_field_t;

typedef struct stc_usb_ep0dt_field
{
    union {
        struct {
            __IO  uint16_t  BFDT                 :16;
        };
        struct {
            __IO  uint16_t  BFDT0                :1;
            __IO  uint16_t  BFDT1                :1;
            __IO  uint16_t  BFDT2                :1;
            __IO  uint16_t  BFDT3                :1;
            __IO  uint16_t  BFDT4                :1;
            __IO  uint16_t  BFDT5                :1;
            __IO  uint16_t  BFDT6                :1;
            __IO  uint16_t  BFDT7                :1;
            __IO  uint16_t  BFDT8                :1;
            __IO  uint16_t  BFDT9                :1;
            __IO  uint16_t  BFDT10               :1;
            __IO  uint16_t  BFDT11               :1;
            __IO  uint16_t  BFDT12               :1;
            __IO  uint16_t  BFDT13               :1;
            __IO  uint16_t  BFDT14               :1;
            __IO  uint16_t  BFDT15               :1;
        };
    };
} stc_usb_ep0dt_field_t;

typedef struct stc_usb_ep1dt_field
{
    union {
        struct {
            __IO  uint16_t  BFDT                 :16;
        };
        struct {
            __IO  uint16_t  BFDT0                :1;
            __IO  uint16_t  BFDT1                :1;
            __IO  uint16_t  BFDT2                :1;
            __IO  uint16_t  BFDT3                :1;
            __IO  uint16_t  BFDT4                :1;
            __IO  uint16_t  BFDT5                :1;
            __IO  uint16_t  BFDT6                :1;
            __IO  uint16_t  BFDT7                :1;
            __IO  uint16_t  BFDT8                :1;
            __IO  uint16_t  BFDT9                :1;
            __IO  uint16_t  BFDT10               :1;
            __IO  uint16_t  BFDT11               :1;
            __IO  uint16_t  BFDT12               :1;
            __IO  uint16_t  BFDT13               :1;
            __IO  uint16_t  BFDT14               :1;
            __IO  uint16_t  BFDT15               :1;
        };
    };
} stc_usb_ep1dt_field_t;

typedef struct stc_usb_ep2dt_field
{
    union {
        struct {
            __IO  uint16_t  BFDT                 :16;
        };
        struct {
            __IO  uint16_t  BFDT0                :1;
            __IO  uint16_t  BFDT1                :1;
            __IO  uint16_t  BFDT2                :1;
            __IO  uint16_t  BFDT3                :1;
            __IO  uint16_t  BFDT4                :1;
            __IO  uint16_t  BFDT5                :1;
            __IO  uint16_t  BFDT6                :1;
            __IO  uint16_t  BFDT7                :1;
            __IO  uint16_t  BFDT8                :1;
            __IO  uint16_t  BFDT9                :1;
            __IO  uint16_t  BFDT10               :1;
            __IO  uint16_t  BFDT11               :1;
            __IO  uint16_t  BFDT12               :1;
            __IO  uint16_t  BFDT13               :1;
            __IO  uint16_t  BFDT14               :1;
            __IO  uint16_t  BFDT15               :1;
        };
    };
} stc_usb_ep2dt_field_t;

typedef struct stc_usb_ep3dt_field
{
    union {
        struct {
            __IO  uint16_t  BFDT                 :16;
        };
        struct {
            __IO  uint16_t  BFDT0                :1;
            __IO  uint16_t  BFDT1                :1;
            __IO  uint16_t  BFDT2                :1;
            __IO  uint16_t  BFDT3                :1;
            __IO  uint16_t  BFDT4                :1;
            __IO  uint16_t  BFDT5                :1;
            __IO  uint16_t  BFDT6                :1;
            __IO  uint16_t  BFDT7                :1;
            __IO  uint16_t  BFDT8                :1;
            __IO  uint16_t  BFDT9                :1;
            __IO  uint16_t  BFDT10               :1;
            __IO  uint16_t  BFDT11               :1;
            __IO  uint16_t  BFDT12               :1;
            __IO  uint16_t  BFDT13               :1;
            __IO  uint16_t  BFDT14               :1;
            __IO  uint16_t  BFDT15               :1;
        };
    };
} stc_usb_ep3dt_field_t;

typedef struct stc_usb_ep4dt_field
{
    union {
        struct {
            __IO  uint16_t  BFDT                 :16;
        };
        struct {
            __IO  uint16_t  BFDT0                :1;
            __IO  uint16_t  BFDT1                :1;
            __IO  uint16_t  BFDT2                :1;
            __IO  uint16_t  BFDT3                :1;
            __IO  uint16_t  BFDT4                :1;
            __IO  uint16_t  BFDT5                :1;
            __IO  uint16_t  BFDT6                :1;
            __IO  uint16_t  BFDT7                :1;
            __IO  uint16_t  BFDT8                :1;
            __IO  uint16_t  BFDT9                :1;
            __IO  uint16_t  BFDT10               :1;
            __IO  uint16_t  BFDT11               :1;
            __IO  uint16_t  BFDT12               :1;
            __IO  uint16_t  BFDT13               :1;
            __IO  uint16_t  BFDT14               :1;
            __IO  uint16_t  BFDT15               :1;
        };
    };
} stc_usb_ep4dt_field_t;

typedef struct stc_usb_ep5dt_field
{
    union {
        struct {
            __IO  uint16_t  BFDT                 :16;
        };
        struct {
            __IO  uint16_t  BFDT0                :1;
            __IO  uint16_t  BFDT1                :1;
            __IO  uint16_t  BFDT2                :1;
            __IO  uint16_t  BFDT3                :1;
            __IO  uint16_t  BFDT4                :1;
            __IO  uint16_t  BFDT5                :1;
            __IO  uint16_t  BFDT6                :1;
            __IO  uint16_t  BFDT7                :1;
            __IO  uint16_t  BFDT8                :1;
            __IO  uint16_t  BFDT9                :1;
            __IO  uint16_t  BFDT10               :1;
            __IO  uint16_t  BFDT11               :1;
            __IO  uint16_t  BFDT12               :1;
            __IO  uint16_t  BFDT13               :1;
            __IO  uint16_t  BFDT14               :1;
            __IO  uint16_t  BFDT15               :1;
        };
    };
} stc_usb_ep5dt_field_t;

/*******************************************************************************
* USBETHERCLK_MODULE
*******************************************************************************/
typedef struct stc_usbetherclk_uccr_field
{
    union {
        struct {
            __IO   uint8_t  UCEN0                :1;
            __IO   uint8_t  UCSEL                :2;
            __IO   uint8_t  UCEN1                :1;
            __IO   uint8_t  ECEN                 :1;
            __IO   uint8_t  ECSEL                :2;
            __IO   uint8_t  RESERVED2            :1;
        };
        struct {
            __IO   uint8_t  RESERVED0            :1;
            __IO   uint8_t  UCSEL0               :1;
            __IO   uint8_t  UCSEL1               :1;
            __IO   uint8_t  RESERVED1            :2;
            __IO   uint8_t  ECSEL0               :1;
            __IO   uint8_t  ECSEL1               :1;
            __IO   uint8_t  RESERVED3            :1;
        };
    };
} stc_usbetherclk_uccr_field_t;

typedef struct stc_usbetherclk_upcr1_field
{
        __IO   uint8_t  UPLLEN                   :1;
        __IO   uint8_t  UPINC                    :1;
        __IO   uint8_t  RESERVED0                :6;
} stc_usbetherclk_upcr1_field_t;

typedef struct stc_usbetherclk_upcr2_field
{
    union {
        struct {
            __IO   uint8_t  UPOWT                :3;
            __IO   uint8_t  RESERVED0            :5;
        };
        struct {
            __IO   uint8_t  UPOWT0               :1;
            __IO   uint8_t  UPOWT1               :1;
            __IO   uint8_t  UPOWT2               :1;
            __IO   uint8_t  RESERVED1            :5;
        };
    };
} stc_usbetherclk_upcr2_field_t;

typedef struct stc_usbetherclk_upcr3_field
{
    union {
        struct {
            __IO   uint8_t  UPLLK                :5;
            __IO   uint8_t  RESERVED0            :3;
        };
        struct {
            __IO   uint8_t  UPLLK0               :1;
            __IO   uint8_t  UPLLK1               :1;
            __IO   uint8_t  UPLLK2               :1;
            __IO   uint8_t  UPLLK3               :1;
            __IO   uint8_t  UPLLK4               :1;
            __IO   uint8_t  RESERVED1            :3;
        };
    };
} stc_usbetherclk_upcr3_field_t;

typedef struct stc_usbetherclk_upcr4_field
{
    union {
        struct {
            __IO   uint8_t  UPLLN                :7;
            __IO   uint8_t  RESERVED0            :1;
        };
        struct {
            __IO   uint8_t  UPLLN0               :1;
            __IO   uint8_t  UPLLN1               :1;
            __IO   uint8_t  UPLLN2               :1;
            __IO   uint8_t  UPLLN3               :1;
            __IO   uint8_t  UPLLN4               :1;
            __IO   uint8_t  UPLLN5               :1;
            __IO   uint8_t  UPLLN6               :1;
            __IO   uint8_t  RESERVED1            :1;
        };
    };
} stc_usbetherclk_upcr4_field_t;

typedef struct stc_usbetherclk_up_str_field
{
        __IO   uint8_t  UPRDY                    :1;
        __IO   uint8_t  RESERVED0                :7;
} stc_usbetherclk_up_str_field_t;

typedef struct stc_usbetherclk_upint_enr_field
{
        __IO   uint8_t  UPCSE                    :1;
        __IO   uint8_t  RESERVED0                :7;
} stc_usbetherclk_upint_enr_field_t;

typedef struct stc_usbetherclk_upint_clr_field
{
        __IO   uint8_t  UPCSC                    :1;
        __IO   uint8_t  RESERVED0                :7;
} stc_usbetherclk_upint_clr_field_t;

typedef struct stc_usbetherclk_upint_str_field
{
        __IO   uint8_t  UPCSI                    :1;
        __IO   uint8_t  RESERVED0                :7;
} stc_usbetherclk_upint_str_field_t;

typedef struct stc_usbetherclk_upcr5_field
{
    union {
        struct {
            __IO   uint8_t  UPLLM                :4;
            __IO   uint8_t  RESERVED0            :4;
        };
        struct {
            __IO   uint8_t  UPLLM0               :1;
            __IO   uint8_t  UPLLM1               :1;
            __IO   uint8_t  UPLLM2               :1;
            __IO   uint8_t  UPLLM3               :1;
            __IO   uint8_t  RESERVED1            :4;
        };
    };
} stc_usbetherclk_upcr5_field_t;

typedef struct stc_usbetherclk_upcr6_field
{
    union {
        struct {
            __IO   uint8_t  UBSR                 :4;
            __IO   uint8_t  RESERVED0            :4;
        };
        struct {
            __IO   uint8_t  UBSR0                :1;
            __IO   uint8_t  UBSR1                :1;
            __IO   uint8_t  UBSR2                :1;
            __IO   uint8_t  UBSR3                :1;
            __IO   uint8_t  RESERVED1            :4;
        };
    };
} stc_usbetherclk_upcr6_field_t;

typedef struct stc_usbetherclk_upcr7_field
{
        __IO   uint8_t  EPLLEN                   :1;
        __IO   uint8_t  RESERVED0                :7;
} stc_usbetherclk_upcr7_field_t;

typedef struct stc_usbetherclk_usben0_field
{
        __IO   uint8_t  USBEN0                   :1;
        __IO   uint8_t  RESERVED0                :7;
} stc_usbetherclk_usben0_field_t;

typedef struct stc_usbetherclk_usben1_field
{
        __IO   uint8_t  USBEN1                   :1;
        __IO   uint8_t  RESERVED0                :7;
} stc_usbetherclk_usben1_field_t;

/*******************************************************************************
* WC_MODULE
*******************************************************************************/
typedef struct stc_wc_wcrd_field
{
    union {
        struct {
            __IO   uint8_t  CTR                  :6;
            __IO   uint8_t  RESERVED0            :2;
        };
        struct {
            __IO   uint8_t  CTR0                 :1;
            __IO   uint8_t  CTR1                 :1;
            __IO   uint8_t  CTR2                 :1;
            __IO   uint8_t  CTR3                 :1;
            __IO   uint8_t  CTR4                 :1;
            __IO   uint8_t  CTR5                 :1;
            __IO   uint8_t  RESERVED1            :2;
        };
    };
} stc_wc_wcrd_field_t;

typedef struct stc_wc_wcrl_field
{
    union {
        struct {
            __IO   uint8_t  RLC                  :6;
            __IO   uint8_t  RESERVED0            :2;
        };
        struct {
            __IO   uint8_t  RLC0                 :1;
            __IO   uint8_t  RLC1                 :1;
            __IO   uint8_t  RLC2                 :1;
            __IO   uint8_t  RLC3                 :1;
            __IO   uint8_t  RLC4                 :1;
            __IO   uint8_t  RLC5                 :1;
            __IO   uint8_t  RESERVED1            :2;
        };
    };
} stc_wc_wcrl_field_t;

typedef struct stc_wc_wccr_field
{
    union {
        struct {
            __IO   uint8_t  WCIF                 :1;
            __IO   uint8_t  WCIE                 :1;
            __IO   uint8_t  CS                   :2;
            __IO   uint8_t  RESERVED1            :2;
            __IO   uint8_t  WCOP                 :1;
            __IO   uint8_t  WCEN                 :1;
        };
        struct {
            __IO   uint8_t  RESERVED0            :2;
            __IO   uint8_t  CS0                  :1;
            __IO   uint8_t  CS1                  :1;
            __IO   uint8_t  RESERVED2            :4;
        };
    };
} stc_wc_wccr_field_t;

typedef struct stc_wc_clk_sel_field
{
    union {
        struct {
            __IO  uint16_t  SEL_IN               :2;
            __IO  uint16_t  RESERVED0            :6;
            __IO  uint16_t  SEL_OUT              :3;
            __IO  uint16_t  RESERVED2            :5;
        };
        struct {
            __IO  uint16_t  SEL_IN0              :1;
            __IO  uint16_t  SEL_IN1              :1;
            __IO  uint16_t  RESERVED1            :6;
            __IO  uint16_t  SEL_OUT0             :1;
            __IO  uint16_t  SEL_OUT1             :1;
            __IO  uint16_t  SEL_OUT2             :1;
            __IO  uint16_t  RESERVED3            :5;
        };
    };
} stc_wc_clk_sel_field_t;

typedef struct stc_wc_clk_en_field
{
        __IO   uint8_t  CLK_EN                   :1;
        __IO   uint8_t  CLK_EN_R                 :1;
        __IO   uint8_t  RESERVED0                :6;
} stc_wc_clk_en_field_t;

/*******************************************************************************
* Peripheral register structures
*******************************************************************************/

/*******************************************************************************
* ADC_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO  uint8_t ADSR;
        stc_adc_adsr_field_t ADSR_f;
    };
    union {
        __IO  uint8_t ADCR;
        stc_adc_adcr_field_t ADCR_f;
    };
        __IO  uint8_t RESERVED0[6];
    union {
        __IO  uint8_t SFNS;
        stc_adc_sfns_field_t SFNS_f;
    };
    union {
        __IO  uint8_t SCCR;
        stc_adc_sccr_field_t SCCR_f;
    };
        __IO  uint8_t RESERVED1[2];
    union {
        __IO uint32_t SCFD;
        stc_adc_scfd_field_t SCFD_f;
        struct {
          union {
            __IO uint16_t SCFDL;
            struct {
              __IO uint8_t SCFDLL;
              __IO uint8_t SCFDLH;
            };
          };
          union {
            __IO uint16_t SCFDH;
            struct {
              __IO uint8_t SCFDHL;
              __IO uint8_t SCFDHH;
            };
          };
        };
        __IO uint32_t SCFD_FDAS1;
        stc_adc_scfd_fdas1_field_t SCFD_FDAS1_f;
        struct {
          union {
            __IO uint16_t SCFD_FDAS1L;
            struct {
              __IO uint8_t SCFD_FDAS1LL;
              __IO uint8_t SCFD_FDAS1LH;
            };
          };
          union {
            __IO uint16_t SCFD_FDAS1H;
            struct {
              __IO uint8_t SCFD_FDAS1HL;
              __IO uint8_t SCFD_FDAS1HH;
            };
          };
        };
    };
    union {
        __IO uint16_t SCIS23;
        stc_adc_scis23_field_t SCIS23_f;
        struct {
            __IO  uint8_t SCIS23L;
            __IO  uint8_t SCIS23H;
        };
    };
        __IO  uint8_t RESERVED2[2];
    union {
        __IO uint16_t SCIS01;
        stc_adc_scis01_field_t SCIS01_f;
        struct {
            __IO  uint8_t SCIS01L;
            __IO  uint8_t SCIS01H;
        };
    };
        __IO  uint8_t RESERVED3[2];
    union {
        __IO  uint8_t PFNS;
        stc_adc_pfns_field_t PFNS_f;
    };
    union {
        __IO  uint8_t PCCR;
        stc_adc_pccr_field_t PCCR_f;
    };
        __IO  uint8_t RESERVED4[2];
    union {
        __IO uint32_t PCFD;
        stc_adc_pcfd_field_t PCFD_f;
        struct {
          union {
            __IO uint16_t PCFDL;
            struct {
              __IO uint8_t PCFDLL;
              __IO uint8_t PCFDLH;
            };
          };
          union {
            __IO uint16_t PCFDH;
            struct {
              __IO uint8_t PCFDHL;
              __IO uint8_t PCFDHH;
            };
          };
        };
        __IO uint32_t PCFD_FDAS1;
        stc_adc_pcfd_fdas1_field_t PCFD_FDAS1_f;
        struct {
          union {
            __IO uint16_t PCFD_FDAS1L;
            struct {
              __IO uint8_t PCFD_FDAS1LL;
              __IO uint8_t PCFD_FDAS1LH;
            };
          };
          union {
            __IO uint16_t PCFD_FDAS1H;
            struct {
              __IO uint8_t PCFD_FDAS1HL;
              __IO uint8_t PCFD_FDAS1HH;
            };
          };
        };
    };
    union {
        __IO  uint8_t PCIS;
        stc_adc_pcis_field_t PCIS_f;
    };
        __IO  uint8_t RESERVED5[3];
    union {
        __IO  uint8_t CMPCR;
        stc_adc_cmpcr_field_t CMPCR_f;
    };
        __IO  uint8_t RESERVED6[1];
    union {
        __IO uint16_t CMPD;
        stc_adc_cmpd_field_t CMPD_f;
        struct {
            __IO  uint8_t CMPDL;
            __IO  uint8_t CMPDH;
        };
    };
    union {
        __IO uint16_t ADSS23;
        stc_adc_adss23_field_t ADSS23_f;
        struct {
            __IO  uint8_t ADSS23L;
            __IO  uint8_t ADSS23H;
        };
    };
        __IO  uint8_t RESERVED7[2];
    union {
        __IO uint16_t ADSS01;
        stc_adc_adss01_field_t ADSS01_f;
        struct {
            __IO  uint8_t ADSS01L;
            __IO  uint8_t ADSS01H;
        };
    };
        __IO  uint8_t RESERVED8[2];
    union {
        __IO uint16_t ADST01;
        stc_adc_adst01_field_t ADST01_f;
        struct {
            __IO  uint8_t ADST01L;
            __IO  uint8_t ADST01H;
        };
    };
        __IO  uint8_t RESERVED9[2];
    union {
        __IO  uint8_t ADCT;
        stc_adc_adct_field_t ADCT_f;
    };
        __IO  uint8_t RESERVED10[3];
    union {
        __IO  uint8_t PRTSL;
        stc_adc_prtsl_field_t PRTSL_f;
    };
    union {
        __IO  uint8_t SCTSL;
        stc_adc_sctsl_field_t SCTSL_f;
    };
        __IO  uint8_t RESERVED11[2];
    union {
        __IO uint16_t ADCEN;
        stc_adc_adcen_field_t ADCEN_f;
        struct {
            __IO  uint8_t ADCENL;
            __IO  uint8_t ADCENH;
        };
    };
        __IO  uint8_t RESERVED12[2];
    union {
        __IO uint32_t CALSR;
        stc_adc_calsr_field_t CALSR_f;
        struct {
          union {
            __IO uint16_t CALSRL;
            struct {
              __IO uint8_t CALSRLL;
              __IO uint8_t CALSRLH;
            };
          };
          union {
            __IO uint16_t CALSRH;
            struct {
              __IO uint8_t CALSRHL;
              __IO uint8_t CALSRHH;
            };
          };
        };
    };
    union {
        __IO  uint8_t WCMRCOT;
        stc_adc_wcmrcot_field_t WCMRCOT_f;
    };
        __IO  uint8_t RESERVED13[3];
    union {
        __IO  uint8_t WCMRCIF;
        stc_adc_wcmrcif_field_t WCMRCIF_f;
    };
        __IO  uint8_t RESERVED14[3];
    union {
        __IO  uint8_t WCMPCR;
        stc_adc_wcmpcr_field_t WCMPCR_f;
    };
    union {
        __IO  uint8_t WCMPSR;
        stc_adc_wcmpsr_field_t WCMPSR_f;
    };
        __IO  uint8_t RESERVED15[2];
    union {
        __IO uint16_t WCMPDL;
        stc_adc_wcmpdl_field_t WCMPDL_f;
        struct {
            __IO  uint8_t WCMPDLL;
            __IO  uint8_t WCMPDLH;
        };
    };
    union {
        __IO uint16_t WCMPDH;
        stc_adc_wcmpdh_field_t WCMPDH_f;
        struct {
            __IO  uint8_t WCMPDHL;
            __IO  uint8_t WCMPDHH;
        };
    };
} FM_ADC_TypeDef, FM4_ADC_TypeDef;

/*******************************************************************************
* BT_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO uint16_t PRLL;
        struct {
            __IO  uint8_t PRLLL;
            __IO  uint8_t PRLLH;
        };
        __IO uint16_t PPG_PRLL;
        struct {
            __IO  uint8_t PPG_PRLLL;
            __IO  uint8_t PPG_PRLLH;
        };
        __IO uint16_t PCSR;
        struct {
            __IO  uint8_t PCSRL;
            __IO  uint8_t PCSRH;
        };
        __IO uint16_t PWM_PCSR;
        struct {
            __IO  uint8_t PWM_PCSRL;
            __IO  uint8_t PWM_PCSRH;
        };
        __IO uint16_t RT_PCSR;
        struct {
            __IO  uint8_t RT_PCSRL;
            __IO  uint8_t RT_PCSRH;
        };
    };
        __IO  uint8_t RESERVED0[2];
    union {
        __IO uint16_t PRLH;
        struct {
            __IO  uint8_t PRLHL;
            __IO  uint8_t PRLHH;
        };
        __IO uint16_t PPG_PRLH;
        struct {
            __IO  uint8_t PPG_PRLHL;
            __IO  uint8_t PPG_PRLHH;
        };
        __IO uint16_t DTBF;
        struct {
            __IO  uint8_t DTBFL;
            __IO  uint8_t DTBFH;
        };
        __IO uint16_t PWC_DTBF;
        struct {
            __IO  uint8_t PWC_DTBFL;
            __IO  uint8_t PWC_DTBFH;
        };
        __IO uint16_t PDUT;
        struct {
            __IO  uint8_t PDUTL;
            __IO  uint8_t PDUTH;
        };
        __IO uint16_t PWM_PDUT;
        struct {
            __IO  uint8_t PWM_PDUTL;
            __IO  uint8_t PWM_PDUTH;
        };
    };
        __IO  uint8_t RESERVED1[2];
    union {
        __IO uint16_t TMR;
        struct {
            __IO  uint8_t TMRL;
            __IO  uint8_t TMRH;
        };
        __IO uint16_t PPG_TMR;
        struct {
            __IO  uint8_t PPG_TMRL;
            __IO  uint8_t PPG_TMRH;
        };
        __IO uint16_t PWM_TMR;
        struct {
            __IO  uint8_t PWM_TMRL;
            __IO  uint8_t PWM_TMRH;
        };
        __IO uint16_t RT_TMR;
        struct {
            __IO  uint8_t RT_TMRL;
            __IO  uint8_t RT_TMRH;
        };
    };
        __IO  uint8_t RESERVED2[2];
    union {
        __IO uint16_t TMCR;
        stc_bt_tmcr_field_t TMCR_f;
        struct {
            __IO  uint8_t TMCRL;
            __IO  uint8_t TMCRH;
        };
        __IO uint16_t PPG_TMCR;
        stc_bt_ppg_tmcr_field_t PPG_TMCR_f;
        struct {
            __IO  uint8_t PPG_TMCRL;
            __IO  uint8_t PPG_TMCRH;
        };
        __IO uint16_t PWC_TMCR;
        stc_bt_pwc_tmcr_field_t PWC_TMCR_f;
        struct {
            __IO  uint8_t PWC_TMCRL;
            __IO  uint8_t PWC_TMCRH;
        };
        __IO uint16_t PWM_TMCR;
        stc_bt_pwm_tmcr_field_t PWM_TMCR_f;
        struct {
            __IO  uint8_t PWM_TMCRL;
            __IO  uint8_t PWM_TMCRH;
        };
        __IO uint16_t RT_TMCR;
        stc_bt_rt_tmcr_field_t RT_TMCR_f;
        struct {
            __IO  uint8_t RT_TMCRL;
            __IO  uint8_t RT_TMCRH;
        };
    };
        __IO  uint8_t RESERVED3[2];
    union {
        __IO  uint8_t STC;
        stc_bt_stc_field_t STC_f;
        __IO  uint8_t PPG_STC;
        stc_bt_ppg_stc_field_t PPG_STC_f;
        __IO  uint8_t PWC_STC;
        stc_bt_pwc_stc_field_t PWC_STC_f;
        __IO  uint8_t PWM_STC;
        stc_bt_pwm_stc_field_t PWM_STC_f;
        __IO  uint8_t RT_STC;
        stc_bt_rt_stc_field_t RT_STC_f;
    };
    union {
        __IO  uint8_t TMCR2;
        stc_bt_tmcr2_field_t TMCR2_f;
        __IO  uint8_t PPG_TMCR2;
        stc_bt_ppg_tmcr2_field_t PPG_TMCR2_f;
        __IO  uint8_t PWC_TMCR2;
        stc_bt_pwc_tmcr2_field_t PWC_TMCR2_f;
        __IO  uint8_t PWM_TMCR2;
        stc_bt_pwm_tmcr2_field_t PWM_TMCR2_f;
        __IO  uint8_t RT_TMCR2;
        stc_bt_rt_tmcr2_field_t RT_TMCR2_f;
    };
} FM_BT_TypeDef, FM4_BT_TypeDef;

/*******************************************************************************
* BT_PPG_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO uint16_t PRLL;
        struct {
            __IO  uint8_t PRLLL;
            __IO  uint8_t PRLLH;
        };
    };
        __IO  uint8_t RESERVED4[2];
    union {
        __IO uint16_t PRLH;
        struct {
            __IO  uint8_t PRLHL;
            __IO  uint8_t PRLHH;
        };
    };
        __IO  uint8_t RESERVED5[2];
    union {
        __IO uint16_t TMR;
        struct {
            __IO  uint8_t TMRL;
            __IO  uint8_t TMRH;
        };
    };
        __IO  uint8_t RESERVED6[2];
    union {
        __IO uint16_t TMCR;
        stc_bt_ppg_tmcr_field_t TMCR_f;
        struct {
            __IO  uint8_t TMCRL;
            __IO  uint8_t TMCRH;
        };
    };
        __IO  uint8_t RESERVED7[2];
    union {
        __IO  uint8_t STC;
        stc_bt_ppg_stc_field_t STC_f;
    };
    union {
        __IO  uint8_t TMCR2;
        stc_bt_ppg_tmcr2_field_t TMCR2_f;
    };
} FM_BT_PPG_TypeDef, FM4_BT_PPG_TypeDef;

/*******************************************************************************
* BT_PWC_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
        __IO  uint8_t RESERVED8[4];
    union {
        __IO uint16_t DTBF;
        struct {
            __IO  uint8_t DTBFL;
            __IO  uint8_t DTBFH;
        };
    };
        __IO  uint8_t RESERVED9[6];
    union {
        __IO uint16_t TMCR;
        stc_bt_pwc_tmcr_field_t TMCR_f;
        struct {
            __IO  uint8_t TMCRL;
            __IO  uint8_t TMCRH;
        };
    };
        __IO  uint8_t RESERVED10[2];
    union {
        __IO  uint8_t STC;
        stc_bt_pwc_stc_field_t STC_f;
    };
    union {
        __IO  uint8_t TMCR2;
        stc_bt_pwc_tmcr2_field_t TMCR2_f;
    };
} FM_BT_PWC_TypeDef, FM4_BT_PWC_TypeDef;

/*******************************************************************************
* BT_PWM_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO uint16_t PCSR;
        struct {
            __IO  uint8_t PCSRL;
            __IO  uint8_t PCSRH;
        };
    };
        __IO  uint8_t RESERVED11[2];
    union {
        __IO uint16_t PDUT;
        struct {
            __IO  uint8_t PDUTL;
            __IO  uint8_t PDUTH;
        };
    };
        __IO  uint8_t RESERVED12[2];
    union {
        __IO uint16_t TMR;
        struct {
            __IO  uint8_t TMRL;
            __IO  uint8_t TMRH;
        };
    };
        __IO  uint8_t RESERVED13[2];
    union {
        __IO uint16_t TMCR;
        stc_bt_pwm_tmcr_field_t TMCR_f;
        struct {
            __IO  uint8_t TMCRL;
            __IO  uint8_t TMCRH;
        };
    };
        __IO  uint8_t RESERVED14[2];
    union {
        __IO  uint8_t STC;
        stc_bt_pwm_stc_field_t STC_f;
    };
    union {
        __IO  uint8_t TMCR2;
        stc_bt_pwm_tmcr2_field_t TMCR2_f;
    };
} FM_BT_PWM_TypeDef, FM4_BT_PWM_TypeDef;

/*******************************************************************************
* BT_RT_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO uint16_t PCSR;
        struct {
            __IO  uint8_t PCSRL;
            __IO  uint8_t PCSRH;
        };
    };
        __IO  uint8_t RESERVED15[6];
    union {
        __IO uint16_t TMR;
        struct {
            __IO  uint8_t TMRL;
            __IO  uint8_t TMRH;
        };
    };
        __IO  uint8_t RESERVED16[2];
    union {
        __IO uint16_t TMCR;
        stc_bt_rt_tmcr_field_t TMCR_f;
        struct {
            __IO  uint8_t TMCRL;
            __IO  uint8_t TMCRH;
        };
    };
        __IO  uint8_t RESERVED17[2];
    union {
        __IO  uint8_t STC;
        stc_bt_rt_stc_field_t STC_f;
    };
    union {
        __IO  uint8_t TMCR2;
        stc_bt_rt_tmcr2_field_t TMCR2_f;
    };
} FM_BT_RT_TypeDef, FM4_BT_RT_TypeDef;

/*******************************************************************************
* BTIOSEL03_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
        __IO  uint8_t RESERVED0[1];
    union {
        __IO  uint8_t BTSEL0123;
        stc_btiosel03_btsel0123_field_t BTSEL0123_f;
    };
} FM_BTIOSEL03_TypeDef, FM4_BTIOSEL03_TypeDef;

/*******************************************************************************
* BTIOSEL47_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
        __IO  uint8_t RESERVED0[1];
    union {
        __IO  uint8_t BTSEL4567;
        stc_btiosel47_btsel4567_field_t BTSEL4567_f;
    };
} FM_BTIOSEL47_TypeDef, FM4_BTIOSEL47_TypeDef;

/*******************************************************************************
* BTIOSEL8B_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
        __IO  uint8_t RESERVED0[1];
    union {
        __IO  uint8_t BTSEL89AB;
        stc_btiosel8b_btsel89ab_field_t BTSEL89AB_f;
    };
} FM_BTIOSEL8B_TypeDef, FM4_BTIOSEL8B_TypeDef;

/*******************************************************************************
* BTIOSELCF_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
        __IO  uint8_t RESERVED0[1];
    union {
        __IO  uint8_t BTSELCDEF;
        stc_btioselcf_btselcdef_field_t BTSELCDEF_f;
    };
} FM_BTIOSELCF_TypeDef, FM4_BTIOSELCF_TypeDef;

/*******************************************************************************
* CAN_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO uint16_t CTRLR;
        stc_can_ctrlr_field_t CTRLR_f;
        struct {
            __IO  uint8_t CTRLRL;
            __IO  uint8_t CTRLRH;
        };
    };
    union {
        __IO uint16_t STATR;
        stc_can_statr_field_t STATR_f;
        struct {
            __IO  uint8_t STATRL;
            __IO  uint8_t STATRH;
        };
    };
    union {
        __IO uint16_t ERRCNT;
        stc_can_errcnt_field_t ERRCNT_f;
        struct {
            __IO  uint8_t ERRCNTL;
            __IO  uint8_t ERRCNTH;
        };
    };
    union {
        __IO uint16_t BTR;
        stc_can_btr_field_t BTR_f;
        struct {
            __IO  uint8_t BTRL;
            __IO  uint8_t BTRH;
        };
    };
    union {
        __IO uint16_t INTR;
        stc_can_intr_field_t INTR_f;
        struct {
            __IO  uint8_t INTRL;
            __IO  uint8_t INTRH;
        };
    };
    union {
        __IO uint16_t TESTR;
        stc_can_testr_field_t TESTR_f;
        struct {
            __IO  uint8_t TESTRL;
            __IO  uint8_t TESTRH;
        };
    };
    union {
        __IO uint16_t BRPER;
        stc_can_brper_field_t BRPER_f;
        struct {
            __IO  uint8_t BRPERL;
            __IO  uint8_t BRPERH;
        };
    };
        __IO  uint8_t RESERVED0[2];
    union {
        __IO uint16_t IF1CREQ;
        stc_can_if1creq_field_t IF1CREQ_f;
        struct {
            __IO  uint8_t IF1CREQL;
            __IO  uint8_t IF1CREQH;
        };
    };
    union {
        __IO uint16_t IF1CMSK;
        stc_can_if1cmsk_field_t IF1CMSK_f;
        struct {
            __IO  uint8_t IF1CMSKL;
            __IO  uint8_t IF1CMSKH;
        };
    };
    union {
        __IO uint32_t IF1MSK;
        stc_can_if1msk_field_t IF1MSK_f;
        struct {
          union {
            __IO uint16_t IF1MSKL;
            struct {
              __IO uint8_t IF1MSKLL;
              __IO uint8_t IF1MSKLH;
            };
          };
          union {
            __IO uint16_t IF1MSKH;
            struct {
              __IO uint8_t IF1MSKHL;
              __IO uint8_t IF1MSKHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IF1ARB;
        stc_can_if1arb_field_t IF1ARB_f;
        struct {
          union {
            __IO uint16_t IF1ARBL;
            struct {
              __IO uint8_t IF1ARBLL;
              __IO uint8_t IF1ARBLH;
            };
          };
          union {
            __IO uint16_t IF1ARBH;
            struct {
              __IO uint8_t IF1ARBHL;
              __IO uint8_t IF1ARBHH;
            };
          };
        };
    };
    union {
        __IO uint16_t IF1MCTR;
        stc_can_if1mctr_field_t IF1MCTR_f;
        struct {
            __IO  uint8_t IF1MCTRL;
            __IO  uint8_t IF1MCTRH;
        };
    };
        __IO  uint8_t RESERVED1[2];
    union {
        __IO uint32_t IF1DTA_L;
        stc_can_if1dta_l_field_t IF1DTA_L_f;
        struct {
          union {
            __IO uint16_t IF1DTA_LL;
            struct {
              __IO uint8_t IF1DTA_LLL;
              __IO uint8_t IF1DTA_LLH;
            };
          };
          union {
            __IO uint16_t IF1DTA_LH;
            struct {
              __IO uint8_t IF1DTA_LHL;
              __IO uint8_t IF1DTA_LHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IF1DTB_L;
        stc_can_if1dtb_l_field_t IF1DTB_L_f;
        struct {
          union {
            __IO uint16_t IF1DTB_LL;
            struct {
              __IO uint8_t IF1DTB_LLL;
              __IO uint8_t IF1DTB_LLH;
            };
          };
          union {
            __IO uint16_t IF1DTB_LH;
            struct {
              __IO uint8_t IF1DTB_LHL;
              __IO uint8_t IF1DTB_LHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED2[8];
    union {
        __IO uint32_t IF1DTA_B;
        stc_can_if1dta_b_field_t IF1DTA_B_f;
        struct {
          union {
            __IO uint16_t IF1DTA_BL;
            struct {
              __IO uint8_t IF1DTA_BLL;
              __IO uint8_t IF1DTA_BLH;
            };
          };
          union {
            __IO uint16_t IF1DTA_BH;
            struct {
              __IO uint8_t IF1DTA_BHL;
              __IO uint8_t IF1DTA_BHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IF1DTB_B;
        stc_can_if1dtb_b_field_t IF1DTB_B_f;
        struct {
          union {
            __IO uint16_t IF1DTB_BL;
            struct {
              __IO uint8_t IF1DTB_BLL;
              __IO uint8_t IF1DTB_BLH;
            };
          };
          union {
            __IO uint16_t IF1DTB_BH;
            struct {
              __IO uint8_t IF1DTB_BHL;
              __IO uint8_t IF1DTB_BHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED3[8];
    union {
        __IO uint16_t IF2CREQ;
        stc_can_if2creq_field_t IF2CREQ_f;
        struct {
            __IO  uint8_t IF2CREQL;
            __IO  uint8_t IF2CREQH;
        };
    };
    union {
        __IO uint16_t IF2CMSK;
        stc_can_if2cmsk_field_t IF2CMSK_f;
        struct {
            __IO  uint8_t IF2CMSKL;
            __IO  uint8_t IF2CMSKH;
        };
    };
    union {
        __IO uint32_t IF2MSK;
        stc_can_if2msk_field_t IF2MSK_f;
        struct {
          union {
            __IO uint16_t IF2MSKL;
            struct {
              __IO uint8_t IF2MSKLL;
              __IO uint8_t IF2MSKLH;
            };
          };
          union {
            __IO uint16_t IF2MSKH;
            struct {
              __IO uint8_t IF2MSKHL;
              __IO uint8_t IF2MSKHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IF2ARB;
        stc_can_if2arb_field_t IF2ARB_f;
        struct {
          union {
            __IO uint16_t IF2ARBL;
            struct {
              __IO uint8_t IF2ARBLL;
              __IO uint8_t IF2ARBLH;
            };
          };
          union {
            __IO uint16_t IF2ARBH;
            struct {
              __IO uint8_t IF2ARBHL;
              __IO uint8_t IF2ARBHH;
            };
          };
        };
    };
    union {
        __IO uint16_t IF2MCTR;
        stc_can_if2mctr_field_t IF2MCTR_f;
        struct {
            __IO  uint8_t IF2MCTRL;
            __IO  uint8_t IF2MCTRH;
        };
    };
        __IO  uint8_t RESERVED4[2];
    union {
        __IO uint32_t IF2DTA_L;
        stc_can_if2dta_l_field_t IF2DTA_L_f;
        struct {
          union {
            __IO uint16_t IF2DTA_LL;
            struct {
              __IO uint8_t IF2DTA_LLL;
              __IO uint8_t IF2DTA_LLH;
            };
          };
          union {
            __IO uint16_t IF2DTA_LH;
            struct {
              __IO uint8_t IF2DTA_LHL;
              __IO uint8_t IF2DTA_LHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IF2DTB_L;
        stc_can_if2dtb_l_field_t IF2DTB_L_f;
        struct {
          union {
            __IO uint16_t IF2DTB_LL;
            struct {
              __IO uint8_t IF2DTB_LLL;
              __IO uint8_t IF2DTB_LLH;
            };
          };
          union {
            __IO uint16_t IF2DTB_LH;
            struct {
              __IO uint8_t IF2DTB_LHL;
              __IO uint8_t IF2DTB_LHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED5[8];
    union {
        __IO uint32_t IF2DTA_B;
        stc_can_if2dta_b_field_t IF2DTA_B_f;
        struct {
          union {
            __IO uint16_t IF2DTA_BL;
            struct {
              __IO uint8_t IF2DTA_BLL;
              __IO uint8_t IF2DTA_BLH;
            };
          };
          union {
            __IO uint16_t IF2DTA_BH;
            struct {
              __IO uint8_t IF2DTA_BHL;
              __IO uint8_t IF2DTA_BHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IF2DTB_B;
        stc_can_if2dtb_b_field_t IF2DTB_B_f;
        struct {
          union {
            __IO uint16_t IF2DTB_BL;
            struct {
              __IO uint8_t IF2DTB_BLL;
              __IO uint8_t IF2DTB_BLH;
            };
          };
          union {
            __IO uint16_t IF2DTB_BH;
            struct {
              __IO uint8_t IF2DTB_BHL;
              __IO uint8_t IF2DTB_BHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED6[24];
    union {
        __IO uint32_t TREQR;
        stc_can_treqr_field_t TREQR_f;
        struct {
          union {
            __IO uint16_t TREQRL;
            struct {
              __IO uint8_t TREQRLL;
              __IO uint8_t TREQRLH;
            };
          };
          union {
            __IO uint16_t TREQRH;
            struct {
              __IO uint8_t TREQRHL;
              __IO uint8_t TREQRHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED7[12];
    union {
        __IO uint32_t NEWDT;
        stc_can_newdt_field_t NEWDT_f;
        struct {
          union {
            __IO uint16_t NEWDTL;
            struct {
              __IO uint8_t NEWDTLL;
              __IO uint8_t NEWDTLH;
            };
          };
          union {
            __IO uint16_t NEWDTH;
            struct {
              __IO uint8_t NEWDTHL;
              __IO uint8_t NEWDTHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED8[12];
    union {
        __IO uint32_t INTPND;
        stc_can_intpnd_field_t INTPND_f;
        struct {
          union {
            __IO uint16_t INTPNDL;
            struct {
              __IO uint8_t INTPNDLL;
              __IO uint8_t INTPNDLH;
            };
          };
          union {
            __IO uint16_t INTPNDH;
            struct {
              __IO uint8_t INTPNDHL;
              __IO uint8_t INTPNDHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED9[12];
    union {
        __IO uint32_t MSGVAL;
        stc_can_msgval_field_t MSGVAL_f;
        struct {
          union {
            __IO uint16_t MSGVALL;
            struct {
              __IO uint8_t MSGVALLL;
              __IO uint8_t MSGVALLH;
            };
          };
          union {
            __IO uint16_t MSGVALH;
            struct {
              __IO uint8_t MSGVALHL;
              __IO uint8_t MSGVALHH;
            };
          };
        };
    };
} FM_CAN_TypeDef, FM4_CAN_TypeDef;

/*******************************************************************************
* CANFD_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO uint32_t CREL;
        stc_canfd_crel_field_t CREL_f;
        struct {
          union {
            __IO uint16_t CRELL;
            struct {
              __IO uint8_t CRELLL;
              __IO uint8_t CRELLH;
            };
          };
          union {
            __IO uint16_t CRELH;
            struct {
              __IO uint8_t CRELHL;
              __IO uint8_t CRELHH;
            };
          };
        };
    };
    union {
        __IO uint32_t ENDN;
        stc_canfd_endn_field_t ENDN_f;
        struct {
          union {
            __IO uint16_t ENDNL;
            struct {
              __IO uint8_t ENDNLL;
              __IO uint8_t ENDNLH;
            };
          };
          union {
            __IO uint16_t ENDNH;
            struct {
              __IO uint8_t ENDNHL;
              __IO uint8_t ENDNHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED0[4];
    union {
        __IO uint32_t FBTP;
        stc_canfd_fbtp_field_t FBTP_f;
        struct {
          union {
            __IO uint16_t FBTPL;
            struct {
              __IO uint8_t FBTPLL;
              __IO uint8_t FBTPLH;
            };
          };
          union {
            __IO uint16_t FBTPH;
            struct {
              __IO uint8_t FBTPHL;
              __IO uint8_t FBTPHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TEST;
        stc_canfd_test_field_t TEST_f;
        struct {
          union {
            __IO uint16_t TESTL;
            struct {
              __IO uint8_t TESTLL;
              __IO uint8_t TESTLH;
            };
          };
          union {
            __IO uint16_t TESTH;
            struct {
              __IO uint8_t TESTHL;
              __IO uint8_t TESTHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RWD;
        stc_canfd_rwd_field_t RWD_f;
        struct {
          union {
            __IO uint16_t RWDL;
            struct {
              __IO uint8_t RWDLL;
              __IO uint8_t RWDLH;
            };
          };
          union {
            __IO uint16_t RWDH;
            struct {
              __IO uint8_t RWDHL;
              __IO uint8_t RWDHH;
            };
          };
        };
    };
    union {
        __IO uint32_t CCCR;
        stc_canfd_cccr_field_t CCCR_f;
        struct {
          union {
            __IO uint16_t CCCRL;
            struct {
              __IO uint8_t CCCRLL;
              __IO uint8_t CCCRLH;
            };
          };
          union {
            __IO uint16_t CCCRH;
            struct {
              __IO uint8_t CCCRHL;
              __IO uint8_t CCCRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t BTP;
        stc_canfd_btp_field_t BTP_f;
        struct {
          union {
            __IO uint16_t BTPL;
            struct {
              __IO uint8_t BTPLL;
              __IO uint8_t BTPLH;
            };
          };
          union {
            __IO uint16_t BTPH;
            struct {
              __IO uint8_t BTPHL;
              __IO uint8_t BTPHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TSCC;
        stc_canfd_tscc_field_t TSCC_f;
        struct {
          union {
            __IO uint16_t TSCCL;
            struct {
              __IO uint8_t TSCCLL;
              __IO uint8_t TSCCLH;
            };
          };
          union {
            __IO uint16_t TSCCH;
            struct {
              __IO uint8_t TSCCHL;
              __IO uint8_t TSCCHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TSCV;
        stc_canfd_tscv_field_t TSCV_f;
        struct {
          union {
            __IO uint16_t TSCVL;
            struct {
              __IO uint8_t TSCVLL;
              __IO uint8_t TSCVLH;
            };
          };
          union {
            __IO uint16_t TSCVH;
            struct {
              __IO uint8_t TSCVHL;
              __IO uint8_t TSCVHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TOCC;
        stc_canfd_tocc_field_t TOCC_f;
        struct {
          union {
            __IO uint16_t TOCCL;
            struct {
              __IO uint8_t TOCCLL;
              __IO uint8_t TOCCLH;
            };
          };
          union {
            __IO uint16_t TOCCH;
            struct {
              __IO uint8_t TOCCHL;
              __IO uint8_t TOCCHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TOCV;
        stc_canfd_tocv_field_t TOCV_f;
        struct {
          union {
            __IO uint16_t TOCVL;
            struct {
              __IO uint8_t TOCVLL;
              __IO uint8_t TOCVLH;
            };
          };
          union {
            __IO uint16_t TOCVH;
            struct {
              __IO uint8_t TOCVHL;
              __IO uint8_t TOCVHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED1[16];
    union {
        __IO uint32_t ECR;
        stc_canfd_ecr_field_t ECR_f;
        struct {
          union {
            __IO uint16_t ECRL;
            struct {
              __IO uint8_t ECRLL;
              __IO uint8_t ECRLH;
            };
          };
          union {
            __IO uint16_t ECRH;
            struct {
              __IO uint8_t ECRHL;
              __IO uint8_t ECRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PSR;
        stc_canfd_psr_field_t PSR_f;
        struct {
          union {
            __IO uint16_t PSRL;
            struct {
              __IO uint8_t PSRLL;
              __IO uint8_t PSRLH;
            };
          };
          union {
            __IO uint16_t PSRH;
            struct {
              __IO uint8_t PSRHL;
              __IO uint8_t PSRHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED2[8];
    union {
        __IO uint32_t IR;
        stc_canfd_ir_field_t IR_f;
        struct {
          union {
            __IO uint16_t IRL;
            struct {
              __IO uint8_t IRLL;
              __IO uint8_t IRLH;
            };
          };
          union {
            __IO uint16_t IRH;
            struct {
              __IO uint8_t IRHL;
              __IO uint8_t IRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IE;
        stc_canfd_ie_field_t IE_f;
        struct {
          union {
            __IO uint16_t IEL;
            struct {
              __IO uint8_t IELL;
              __IO uint8_t IELH;
            };
          };
          union {
            __IO uint16_t IEH;
            struct {
              __IO uint8_t IEHL;
              __IO uint8_t IEHH;
            };
          };
        };
    };
    union {
        __IO uint32_t ILS;
        stc_canfd_ils_field_t ILS_f;
        struct {
          union {
            __IO uint16_t ILSL;
            struct {
              __IO uint8_t ILSLL;
              __IO uint8_t ILSLH;
            };
          };
          union {
            __IO uint16_t ILSH;
            struct {
              __IO uint8_t ILSHL;
              __IO uint8_t ILSHH;
            };
          };
        };
    };
    union {
        __IO uint32_t ILE;
        stc_canfd_ile_field_t ILE_f;
        struct {
          union {
            __IO uint16_t ILEL;
            struct {
              __IO uint8_t ILELL;
              __IO uint8_t ILELH;
            };
          };
          union {
            __IO uint16_t ILEH;
            struct {
              __IO uint8_t ILEHL;
              __IO uint8_t ILEHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED3[32];
    union {
        __IO uint32_t GFC;
        stc_canfd_gfc_field_t GFC_f;
        struct {
          union {
            __IO uint16_t GFCL;
            struct {
              __IO uint8_t GFCLL;
              __IO uint8_t GFCLH;
            };
          };
          union {
            __IO uint16_t GFCH;
            struct {
              __IO uint8_t GFCHL;
              __IO uint8_t GFCHH;
            };
          };
        };
    };
    union {
        __IO uint32_t SIDFC;
        stc_canfd_sidfc_field_t SIDFC_f;
        struct {
          union {
            __IO uint16_t SIDFCL;
            struct {
              __IO uint8_t SIDFCLL;
              __IO uint8_t SIDFCLH;
            };
          };
          union {
            __IO uint16_t SIDFCH;
            struct {
              __IO uint8_t SIDFCHL;
              __IO uint8_t SIDFCHH;
            };
          };
        };
    };
    union {
        __IO uint32_t XIDFC;
        stc_canfd_xidfc_field_t XIDFC_f;
        struct {
          union {
            __IO uint16_t XIDFCL;
            struct {
              __IO uint8_t XIDFCLL;
              __IO uint8_t XIDFCLH;
            };
          };
          union {
            __IO uint16_t XIDFCH;
            struct {
              __IO uint8_t XIDFCHL;
              __IO uint8_t XIDFCHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED4[4];
    union {
        __IO uint32_t XIDAM;
        stc_canfd_xidam_field_t XIDAM_f;
        struct {
          union {
            __IO uint16_t XIDAML;
            struct {
              __IO uint8_t XIDAMLL;
              __IO uint8_t XIDAMLH;
            };
          };
          union {
            __IO uint16_t XIDAMH;
            struct {
              __IO uint8_t XIDAMHL;
              __IO uint8_t XIDAMHH;
            };
          };
        };
    };
    union {
        __IO uint32_t HPMS;
        stc_canfd_hpms_field_t HPMS_f;
        struct {
          union {
            __IO uint16_t HPMSL;
            struct {
              __IO uint8_t HPMSLL;
              __IO uint8_t HPMSLH;
            };
          };
          union {
            __IO uint16_t HPMSH;
            struct {
              __IO uint8_t HPMSHL;
              __IO uint8_t HPMSHH;
            };
          };
        };
    };
    union {
        __IO uint32_t NDAT1;
        stc_canfd_ndat1_field_t NDAT1_f;
        struct {
          union {
            __IO uint16_t NDAT1L;
            struct {
              __IO uint8_t NDAT1LL;
              __IO uint8_t NDAT1LH;
            };
          };
          union {
            __IO uint16_t NDAT1H;
            struct {
              __IO uint8_t NDAT1HL;
              __IO uint8_t NDAT1HH;
            };
          };
        };
    };
    union {
        __IO uint32_t NDAT2;
        stc_canfd_ndat2_field_t NDAT2_f;
        struct {
          union {
            __IO uint16_t NDAT2L;
            struct {
              __IO uint8_t NDAT2LL;
              __IO uint8_t NDAT2LH;
            };
          };
          union {
            __IO uint16_t NDAT2H;
            struct {
              __IO uint8_t NDAT2HL;
              __IO uint8_t NDAT2HH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXF0C;
        stc_canfd_rxf0c_field_t RXF0C_f;
        struct {
          union {
            __IO uint16_t RXF0CL;
            struct {
              __IO uint8_t RXF0CLL;
              __IO uint8_t RXF0CLH;
            };
          };
          union {
            __IO uint16_t RXF0CH;
            struct {
              __IO uint8_t RXF0CHL;
              __IO uint8_t RXF0CHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXF0S;
        stc_canfd_rxf0s_field_t RXF0S_f;
        struct {
          union {
            __IO uint16_t RXF0SL;
            struct {
              __IO uint8_t RXF0SLL;
              __IO uint8_t RXF0SLH;
            };
          };
          union {
            __IO uint16_t RXF0SH;
            struct {
              __IO uint8_t RXF0SHL;
              __IO uint8_t RXF0SHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXF0A;
        stc_canfd_rxf0a_field_t RXF0A_f;
        struct {
          union {
            __IO uint16_t RXF0AL;
            struct {
              __IO uint8_t RXF0ALL;
              __IO uint8_t RXF0ALH;
            };
          };
          union {
            __IO uint16_t RXF0AH;
            struct {
              __IO uint8_t RXF0AHL;
              __IO uint8_t RXF0AHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXBC;
        stc_canfd_rxbc_field_t RXBC_f;
        struct {
          union {
            __IO uint16_t RXBCL;
            struct {
              __IO uint8_t RXBCLL;
              __IO uint8_t RXBCLH;
            };
          };
          union {
            __IO uint16_t RXBCH;
            struct {
              __IO uint8_t RXBCHL;
              __IO uint8_t RXBCHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXF1C;
        stc_canfd_rxf1c_field_t RXF1C_f;
        struct {
          union {
            __IO uint16_t RXF1CL;
            struct {
              __IO uint8_t RXF1CLL;
              __IO uint8_t RXF1CLH;
            };
          };
          union {
            __IO uint16_t RXF1CH;
            struct {
              __IO uint8_t RXF1CHL;
              __IO uint8_t RXF1CHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXF1S;
        stc_canfd_rxf1s_field_t RXF1S_f;
        struct {
          union {
            __IO uint16_t RXF1SL;
            struct {
              __IO uint8_t RXF1SLL;
              __IO uint8_t RXF1SLH;
            };
          };
          union {
            __IO uint16_t RXF1SH;
            struct {
              __IO uint8_t RXF1SHL;
              __IO uint8_t RXF1SHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXF1A;
        stc_canfd_rxf1a_field_t RXF1A_f;
        struct {
          union {
            __IO uint16_t RXF1AL;
            struct {
              __IO uint8_t RXF1ALL;
              __IO uint8_t RXF1ALH;
            };
          };
          union {
            __IO uint16_t RXF1AH;
            struct {
              __IO uint8_t RXF1AHL;
              __IO uint8_t RXF1AHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXESC;
        stc_canfd_rxesc_field_t RXESC_f;
        struct {
          union {
            __IO uint16_t RXESCL;
            struct {
              __IO uint8_t RXESCLL;
              __IO uint8_t RXESCLH;
            };
          };
          union {
            __IO uint16_t RXESCH;
            struct {
              __IO uint8_t RXESCHL;
              __IO uint8_t RXESCHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXBC;
        stc_canfd_txbc_field_t TXBC_f;
        struct {
          union {
            __IO uint16_t TXBCL;
            struct {
              __IO uint8_t TXBCLL;
              __IO uint8_t TXBCLH;
            };
          };
          union {
            __IO uint16_t TXBCH;
            struct {
              __IO uint8_t TXBCHL;
              __IO uint8_t TXBCHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXFQS;
        stc_canfd_txfqs_field_t TXFQS_f;
        struct {
          union {
            __IO uint16_t TXFQSL;
            struct {
              __IO uint8_t TXFQSLL;
              __IO uint8_t TXFQSLH;
            };
          };
          union {
            __IO uint16_t TXFQSH;
            struct {
              __IO uint8_t TXFQSHL;
              __IO uint8_t TXFQSHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXESC;
        stc_canfd_txesc_field_t TXESC_f;
        struct {
          union {
            __IO uint16_t TXESCL;
            struct {
              __IO uint8_t TXESCLL;
              __IO uint8_t TXESCLH;
            };
          };
          union {
            __IO uint16_t TXESCH;
            struct {
              __IO uint8_t TXESCHL;
              __IO uint8_t TXESCHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXBRP;
        stc_canfd_txbrp_field_t TXBRP_f;
        struct {
          union {
            __IO uint16_t TXBRPL;
            struct {
              __IO uint8_t TXBRPLL;
              __IO uint8_t TXBRPLH;
            };
          };
          union {
            __IO uint16_t TXBRPH;
            struct {
              __IO uint8_t TXBRPHL;
              __IO uint8_t TXBRPHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXBAR;
        stc_canfd_txbar_field_t TXBAR_f;
        struct {
          union {
            __IO uint16_t TXBARL;
            struct {
              __IO uint8_t TXBARLL;
              __IO uint8_t TXBARLH;
            };
          };
          union {
            __IO uint16_t TXBARH;
            struct {
              __IO uint8_t TXBARHL;
              __IO uint8_t TXBARHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXBCR;
        stc_canfd_txbcr_field_t TXBCR_f;
        struct {
          union {
            __IO uint16_t TXBCRL;
            struct {
              __IO uint8_t TXBCRLL;
              __IO uint8_t TXBCRLH;
            };
          };
          union {
            __IO uint16_t TXBCRH;
            struct {
              __IO uint8_t TXBCRHL;
              __IO uint8_t TXBCRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXBTO;
        stc_canfd_txbto_field_t TXBTO_f;
        struct {
          union {
            __IO uint16_t TXBTOL;
            struct {
              __IO uint8_t TXBTOLL;
              __IO uint8_t TXBTOLH;
            };
          };
          union {
            __IO uint16_t TXBTOH;
            struct {
              __IO uint8_t TXBTOHL;
              __IO uint8_t TXBTOHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXBCF;
        stc_canfd_txbcf_field_t TXBCF_f;
        struct {
          union {
            __IO uint16_t TXBCFL;
            struct {
              __IO uint8_t TXBCFLL;
              __IO uint8_t TXBCFLH;
            };
          };
          union {
            __IO uint16_t TXBCFH;
            struct {
              __IO uint8_t TXBCFHL;
              __IO uint8_t TXBCFHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXBTIE;
        stc_canfd_txbtie_field_t TXBTIE_f;
        struct {
          union {
            __IO uint16_t TXBTIEL;
            struct {
              __IO uint8_t TXBTIELL;
              __IO uint8_t TXBTIELH;
            };
          };
          union {
            __IO uint16_t TXBTIEH;
            struct {
              __IO uint8_t TXBTIEHL;
              __IO uint8_t TXBTIEHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXBCIE;
        stc_canfd_txbcie_field_t TXBCIE_f;
        struct {
          union {
            __IO uint16_t TXBCIEL;
            struct {
              __IO uint8_t TXBCIELL;
              __IO uint8_t TXBCIELH;
            };
          };
          union {
            __IO uint16_t TXBCIEH;
            struct {
              __IO uint8_t TXBCIEHL;
              __IO uint8_t TXBCIEHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED5[8];
    union {
        __IO uint32_t TXEFC;
        stc_canfd_txefc_field_t TXEFC_f;
        struct {
          union {
            __IO uint16_t TXEFCL;
            struct {
              __IO uint8_t TXEFCLL;
              __IO uint8_t TXEFCLH;
            };
          };
          union {
            __IO uint16_t TXEFCH;
            struct {
              __IO uint8_t TXEFCHL;
              __IO uint8_t TXEFCHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXFS;
        stc_canfd_txfs_field_t TXFS_f;
        struct {
          union {
            __IO uint16_t TXFSL;
            struct {
              __IO uint8_t TXFSLL;
              __IO uint8_t TXFSLH;
            };
          };
          union {
            __IO uint16_t TXFSH;
            struct {
              __IO uint8_t TXFSHL;
              __IO uint8_t TXFSHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXFA;
        stc_canfd_txfa_field_t TXFA_f;
        struct {
          union {
            __IO uint16_t TXFAL;
            struct {
              __IO uint8_t TXFALL;
              __IO uint8_t TXFALH;
            };
          };
          union {
            __IO uint16_t TXFAH;
            struct {
              __IO uint8_t TXFAHL;
              __IO uint8_t TXFAHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED6[260];
    union {
        __IO  uint8_t FDECR;
        stc_canfd_fdecr_field_t FDECR_f;
    };
    union {
        __IO  uint8_t FDESR;
        stc_canfd_fdesr_field_t FDESR_f;
    };
    union {
        __IO uint16_t FDSEAR;
        stc_canfd_fdsear_field_t FDSEAR_f;
        struct {
            __IO  uint8_t FDSEARL;
            __IO  uint8_t FDSEARH;
        };
    };
        __IO  uint8_t RESERVED7[1];
    union {
        __IO  uint8_t FDESCR;
        stc_canfd_fdescr_field_t FDESCR_f;
    };
    union {
        __IO uint16_t FDDEAR;
        stc_canfd_fddear_field_t FDDEAR_f;
        struct {
            __IO  uint8_t FDDEARL;
            __IO  uint8_t FDDEARH;
        };
    };
        __IO  uint8_t RESERVED8[8];
    union {
        __IO uint16_t TSCNTR;
        stc_canfd_tscntr_field_t TSCNTR_f;
        struct {
            __IO  uint8_t TSCNTRL;
            __IO  uint8_t TSCNTRH;
        };
    };
    union {
        __IO uint16_t TSMDR;
        stc_canfd_tsmdr_field_t TSMDR_f;
        struct {
            __IO  uint8_t TSMDRL;
            __IO  uint8_t TSMDRH;
        };
    };
    union {
        __IO uint32_t TSDIVR;
        stc_canfd_tsdivr_field_t TSDIVR_f;
        struct {
          union {
            __IO uint16_t TSDIVRL;
            struct {
              __IO uint8_t TSDIVRLL;
              __IO uint8_t TSDIVRLH;
            };
          };
          union {
            __IO uint16_t TSDIVRH;
            struct {
              __IO uint8_t TSDIVRHL;
              __IO uint8_t TSDIVRHH;
            };
          };
        };
    };
    union {
        __IO uint16_t TSCDTR;
        stc_canfd_tscdtr_field_t TSCDTR_f;
        struct {
            __IO  uint8_t TSCDTRL;
            __IO  uint8_t TSCDTRH;
        };
    };
    union {
        __IO uint16_t TSCPCLR;
        stc_canfd_tscpclr_field_t TSCPCLR_f;
        struct {
            __IO  uint8_t TSCPCLRL;
            __IO  uint8_t TSCPCLRH;
        };
    };
} FM_CANFD_TypeDef, FM4_CANFD_TypeDef;

/*******************************************************************************
* CANPRES_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO  uint8_t CANPRE;
        stc_canpres_canpre_field_t CANPRE_f;
    };
} FM_CANPRES_TypeDef, FM4_CANPRES_TypeDef;

/*******************************************************************************
* CLK_GATING_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO uint32_t CKEN0;
        stc_clk_gating_cken0_field_t CKEN0_f;
        struct {
          union {
            __IO uint16_t CKEN0L;
            struct {
              __IO uint8_t CKEN0LL;
              __IO uint8_t CKEN0LH;
            };
          };
          union {
            __IO uint16_t CKEN0H;
            struct {
              __IO uint8_t CKEN0HL;
              __IO uint8_t CKEN0HH;
            };
          };
        };
    };
    union {
        __IO uint32_t MRST0;
        stc_clk_gating_mrst0_field_t MRST0_f;
        struct {
          union {
            __IO uint16_t MRST0L;
            struct {
              __IO uint8_t MRST0LL;
              __IO uint8_t MRST0LH;
            };
          };
          union {
            __IO uint16_t MRST0H;
            struct {
              __IO uint8_t MRST0HL;
              __IO uint8_t MRST0HH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED0[8];
    union {
        __IO uint32_t CKEN1;
        stc_clk_gating_cken1_field_t CKEN1_f;
        struct {
          union {
            __IO uint16_t CKEN1L;
            struct {
              __IO uint8_t CKEN1LL;
              __IO uint8_t CKEN1LH;
            };
          };
          union {
            __IO uint16_t CKEN1H;
            struct {
              __IO uint8_t CKEN1HL;
              __IO uint8_t CKEN1HH;
            };
          };
        };
    };
    union {
        __IO uint32_t MRST1;
        stc_clk_gating_mrst1_field_t MRST1_f;
        struct {
          union {
            __IO uint16_t MRST1L;
            struct {
              __IO uint8_t MRST1LL;
              __IO uint8_t MRST1LH;
            };
          };
          union {
            __IO uint16_t MRST1H;
            struct {
              __IO uint8_t MRST1HL;
              __IO uint8_t MRST1HH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED1[8];
    union {
        __IO uint32_t CKEN2;
        stc_clk_gating_cken2_field_t CKEN2_f;
        struct {
          union {
            __IO uint16_t CKEN2L;
            struct {
              __IO uint8_t CKEN2LL;
              __IO uint8_t CKEN2LH;
            };
          };
          union {
            __IO uint16_t CKEN2H;
            struct {
              __IO uint8_t CKEN2HL;
              __IO uint8_t CKEN2HH;
            };
          };
        };
    };
    union {
        __IO uint32_t MRST2;
        stc_clk_gating_mrst2_field_t MRST2_f;
        struct {
          union {
            __IO uint16_t MRST2L;
            struct {
              __IO uint8_t MRST2LL;
              __IO uint8_t MRST2LH;
            };
          };
          union {
            __IO uint16_t MRST2H;
            struct {
              __IO uint8_t MRST2HL;
              __IO uint8_t MRST2HH;
            };
          };
        };
    };
} FM_CLK_GATING_TypeDef, FM4_CLK_GATING_TypeDef;

/*******************************************************************************
* CRC_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO  uint8_t CRCCR;
        stc_crc_crccr_field_t CRCCR_f;
    };
        __IO  uint8_t RESERVED0[3];
    union {
        __IO uint32_t CRCINIT;
        stc_crc_crcinit_field_t CRCINIT_f;
        struct {
          union {
            __IO uint16_t CRCINITL;
            struct {
              __IO uint8_t CRCINITLL;
              __IO uint8_t CRCINITLH;
            };
          };
          union {
            __IO uint16_t CRCINITH;
            struct {
              __IO uint8_t CRCINITHL;
              __IO uint8_t CRCINITHH;
            };
          };
        };
    };
    union {
        __IO uint32_t CRCIN;
        stc_crc_crcin_field_t CRCIN_f;
        struct {
          union {
            __IO uint16_t CRCINL;
            struct {
              __IO uint8_t CRCINLL;
              __IO uint8_t CRCINLH;
            };
          };
          union {
            __IO uint16_t CRCINH;
            struct {
              __IO uint8_t CRCINHL;
              __IO uint8_t CRCINHH;
            };
          };
        };
    };
    union {
        __IO uint32_t CRCR;
        stc_crc_crcr_field_t CRCR_f;
        struct {
          union {
            __IO uint16_t CRCRL;
            struct {
              __IO uint8_t CRCRLL;
              __IO uint8_t CRCRLH;
            };
          };
          union {
            __IO uint16_t CRCRH;
            struct {
              __IO uint8_t CRCRHL;
              __IO uint8_t CRCRHH;
            };
          };
        };
    };
} FM_CRC_TypeDef, FM4_CRC_TypeDef;

/*******************************************************************************
* CRG_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO uint32_t SCM_CTL;
        stc_crg_scm_ctl_field_t SCM_CTL_f;
        struct {
          union {
            __IO uint16_t SCM_CTLL;
            struct {
              __IO uint8_t SCM_CTLLL;
              __IO uint8_t SCM_CTLLH;
            };
          };
          union {
            __IO uint16_t SCM_CTLH;
            struct {
              __IO uint8_t SCM_CTLHL;
              __IO uint8_t SCM_CTLHH;
            };
          };
        };
    };
    union {
        __IO uint32_t SCM_STR;
        stc_crg_scm_str_field_t SCM_STR_f;
        struct {
          union {
            __IO uint16_t SCM_STRL;
            struct {
              __IO uint8_t SCM_STRLL;
              __IO uint8_t SCM_STRLH;
            };
          };
          union {
            __IO uint16_t SCM_STRH;
            struct {
              __IO uint8_t SCM_STRHL;
              __IO uint8_t SCM_STRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t STB_CTL;
        stc_crg_stb_ctl_field_t STB_CTL_f;
        struct {
          union {
            __IO uint16_t STB_CTLL;
            struct {
              __IO uint8_t STB_CTLLL;
              __IO uint8_t STB_CTLLH;
            };
          };
          union {
            __IO uint16_t STB_CTLH;
            struct {
              __IO uint8_t STB_CTLHL;
              __IO uint8_t STB_CTLHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RST_STR;
        stc_crg_rst_str_field_t RST_STR_f;
        struct {
          union {
            __IO uint16_t RST_STRL;
            struct {
              __IO uint8_t RST_STRLL;
              __IO uint8_t RST_STRLH;
            };
          };
          union {
            __IO uint16_t RST_STRH;
            struct {
              __IO uint8_t RST_STRHL;
              __IO uint8_t RST_STRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t BSC_PSR;
        stc_crg_bsc_psr_field_t BSC_PSR_f;
        struct {
          union {
            __IO uint16_t BSC_PSRL;
            struct {
              __IO uint8_t BSC_PSRLL;
              __IO uint8_t BSC_PSRLH;
            };
          };
          union {
            __IO uint16_t BSC_PSRH;
            struct {
              __IO uint8_t BSC_PSRHL;
              __IO uint8_t BSC_PSRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t APBC0_PSR;
        stc_crg_apbc0_psr_field_t APBC0_PSR_f;
        struct {
          union {
            __IO uint16_t APBC0_PSRL;
            struct {
              __IO uint8_t APBC0_PSRLL;
              __IO uint8_t APBC0_PSRLH;
            };
          };
          union {
            __IO uint16_t APBC0_PSRH;
            struct {
              __IO uint8_t APBC0_PSRHL;
              __IO uint8_t APBC0_PSRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t APBC1_PSR;
        stc_crg_apbc1_psr_field_t APBC1_PSR_f;
        struct {
          union {
            __IO uint16_t APBC1_PSRL;
            struct {
              __IO uint8_t APBC1_PSRLL;
              __IO uint8_t APBC1_PSRLH;
            };
          };
          union {
            __IO uint16_t APBC1_PSRH;
            struct {
              __IO uint8_t APBC1_PSRHL;
              __IO uint8_t APBC1_PSRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t APBC2_PSR;
        stc_crg_apbc2_psr_field_t APBC2_PSR_f;
        struct {
          union {
            __IO uint16_t APBC2_PSRL;
            struct {
              __IO uint8_t APBC2_PSRLL;
              __IO uint8_t APBC2_PSRLH;
            };
          };
          union {
            __IO uint16_t APBC2_PSRH;
            struct {
              __IO uint8_t APBC2_PSRHL;
              __IO uint8_t APBC2_PSRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t SWC_PSR;
        stc_crg_swc_psr_field_t SWC_PSR_f;
        struct {
          union {
            __IO uint16_t SWC_PSRL;
            struct {
              __IO uint8_t SWC_PSRLL;
              __IO uint8_t SWC_PSRLH;
            };
          };
          union {
            __IO uint16_t SWC_PSRH;
            struct {
              __IO uint8_t SWC_PSRHL;
              __IO uint8_t SWC_PSRHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED0[4];
    union {
        __IO uint32_t TTC_PSR;
        stc_crg_ttc_psr_field_t TTC_PSR_f;
        struct {
          union {
            __IO uint16_t TTC_PSRL;
            struct {
              __IO uint8_t TTC_PSRLL;
              __IO uint8_t TTC_PSRLH;
            };
          };
          union {
            __IO uint16_t TTC_PSRH;
            struct {
              __IO uint8_t TTC_PSRHL;
              __IO uint8_t TTC_PSRHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED1[4];
    union {
        __IO uint32_t CSW_TMR;
        stc_crg_csw_tmr_field_t CSW_TMR_f;
        struct {
          union {
            __IO uint16_t CSW_TMRL;
            struct {
              __IO uint8_t CSW_TMRLL;
              __IO uint8_t CSW_TMRLH;
            };
          };
          union {
            __IO uint16_t CSW_TMRH;
            struct {
              __IO uint8_t CSW_TMRHL;
              __IO uint8_t CSW_TMRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PSW_TMR;
        stc_crg_psw_tmr_field_t PSW_TMR_f;
        struct {
          union {
            __IO uint16_t PSW_TMRL;
            struct {
              __IO uint8_t PSW_TMRLL;
              __IO uint8_t PSW_TMRLH;
            };
          };
          union {
            __IO uint16_t PSW_TMRH;
            struct {
              __IO uint8_t PSW_TMRHL;
              __IO uint8_t PSW_TMRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PLL_CTL1;
        stc_crg_pll_ctl1_field_t PLL_CTL1_f;
        struct {
          union {
            __IO uint16_t PLL_CTL1L;
            struct {
              __IO uint8_t PLL_CTL1LL;
              __IO uint8_t PLL_CTL1LH;
            };
          };
          union {
            __IO uint16_t PLL_CTL1H;
            struct {
              __IO uint8_t PLL_CTL1HL;
              __IO uint8_t PLL_CTL1HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PLL_CTL2;
        stc_crg_pll_ctl2_field_t PLL_CTL2_f;
        struct {
          union {
            __IO uint16_t PLL_CTL2L;
            struct {
              __IO uint8_t PLL_CTL2LL;
              __IO uint8_t PLL_CTL2LH;
            };
          };
          union {
            __IO uint16_t PLL_CTL2H;
            struct {
              __IO uint8_t PLL_CTL2HL;
              __IO uint8_t PLL_CTL2HH;
            };
          };
        };
    };
    union {
        __IO uint32_t CSV_CTL;
        stc_crg_csv_ctl_field_t CSV_CTL_f;
        struct {
          union {
            __IO uint16_t CSV_CTLL;
            struct {
              __IO uint8_t CSV_CTLLL;
              __IO uint8_t CSV_CTLLH;
            };
          };
          union {
            __IO uint16_t CSV_CTLH;
            struct {
              __IO uint8_t CSV_CTLHL;
              __IO uint8_t CSV_CTLHH;
            };
          };
        };
    };
    union {
        __IO uint32_t CSV_STR;
        stc_crg_csv_str_field_t CSV_STR_f;
        struct {
          union {
            __IO uint16_t CSV_STRL;
            struct {
              __IO uint8_t CSV_STRLL;
              __IO uint8_t CSV_STRLH;
            };
          };
          union {
            __IO uint16_t CSV_STRH;
            struct {
              __IO uint8_t CSV_STRHL;
              __IO uint8_t CSV_STRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t FCSWH_CTL;
        stc_crg_fcswh_ctl_field_t FCSWH_CTL_f;
        struct {
          union {
            __IO uint16_t FCSWH_CTLL;
            struct {
              __IO uint8_t FCSWH_CTLLL;
              __IO uint8_t FCSWH_CTLLH;
            };
          };
          union {
            __IO uint16_t FCSWH_CTLH;
            struct {
              __IO uint8_t FCSWH_CTLHL;
              __IO uint8_t FCSWH_CTLHH;
            };
          };
        };
    };
    union {
        __IO uint32_t FCSWL_CTL;
        stc_crg_fcswl_ctl_field_t FCSWL_CTL_f;
        struct {
          union {
            __IO uint16_t FCSWL_CTLL;
            struct {
              __IO uint8_t FCSWL_CTLLL;
              __IO uint8_t FCSWL_CTLLH;
            };
          };
          union {
            __IO uint16_t FCSWL_CTLH;
            struct {
              __IO uint8_t FCSWL_CTLHL;
              __IO uint8_t FCSWL_CTLHH;
            };
          };
        };
    };
    union {
        __IO uint32_t FCSWD_CTL;
        stc_crg_fcswd_ctl_field_t FCSWD_CTL_f;
        struct {
          union {
            __IO uint16_t FCSWD_CTLL;
            struct {
              __IO uint8_t FCSWD_CTLLL;
              __IO uint8_t FCSWD_CTLLH;
            };
          };
          union {
            __IO uint16_t FCSWD_CTLH;
            struct {
              __IO uint8_t FCSWD_CTLHL;
              __IO uint8_t FCSWD_CTLHH;
            };
          };
        };
    };
    union {
        __IO uint32_t DBWDT_CTL;
        stc_crg_dbwdt_ctl_field_t DBWDT_CTL_f;
        struct {
          union {
            __IO uint16_t DBWDT_CTLL;
            struct {
              __IO uint8_t DBWDT_CTLLL;
              __IO uint8_t DBWDT_CTLLH;
            };
          };
          union {
            __IO uint16_t DBWDT_CTLH;
            struct {
              __IO uint8_t DBWDT_CTLHL;
              __IO uint8_t DBWDT_CTLHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED2[8];
    union {
        __IO uint32_t INT_ENR;
        stc_crg_int_enr_field_t INT_ENR_f;
        struct {
          union {
            __IO uint16_t INT_ENRL;
            struct {
              __IO uint8_t INT_ENRLL;
              __IO uint8_t INT_ENRLH;
            };
          };
          union {
            __IO uint16_t INT_ENRH;
            struct {
              __IO uint8_t INT_ENRHL;
              __IO uint8_t INT_ENRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t INT_STR;
        stc_crg_int_str_field_t INT_STR_f;
        struct {
          union {
            __IO uint16_t INT_STRL;
            struct {
              __IO uint8_t INT_STRLL;
              __IO uint8_t INT_STRLH;
            };
          };
          union {
            __IO uint16_t INT_STRH;
            struct {
              __IO uint8_t INT_STRHL;
              __IO uint8_t INT_STRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t INT_CLR;
        stc_crg_int_clr_field_t INT_CLR_f;
        struct {
          union {
            __IO uint16_t INT_CLRL;
            struct {
              __IO uint8_t INT_CLRLL;
              __IO uint8_t INT_CLRLH;
            };
          };
          union {
            __IO uint16_t INT_CLRH;
            struct {
              __IO uint8_t INT_CLRHL;
              __IO uint8_t INT_CLRHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED3[8];
    union {
        __IO uint32_t PLLCG_CTL;
        stc_crg_pllcg_ctl_field_t PLLCG_CTL_f;
        struct {
          union {
            __IO uint16_t PLLCG_CTLL;
            struct {
              __IO uint8_t PLLCG_CTLLL;
              __IO uint8_t PLLCG_CTLLH;
            };
          };
          union {
            __IO uint16_t PLLCG_CTLH;
            struct {
              __IO uint8_t PLLCG_CTLHL;
              __IO uint8_t PLLCG_CTLHH;
            };
          };
        };
    };
} FM_CRG_TypeDef, FM4_CRG_TypeDef;

/*******************************************************************************
* CRTRIM_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO  uint8_t MCR_PSR;
        stc_crtrim_mcr_psr_field_t MCR_PSR_f;
    };
        __IO  uint8_t RESERVED0[3];
    union {
        __IO uint32_t MCR_FTRM;
        stc_crtrim_mcr_ftrm_field_t MCR_FTRM_f;
        struct {
          union {
            __IO uint16_t MCR_FTRML;
            struct {
              __IO uint8_t MCR_FTRMLL;
              __IO uint8_t MCR_FTRMLH;
            };
          };
          union {
            __IO uint16_t MCR_FTRMH;
            struct {
              __IO uint8_t MCR_FTRMHL;
              __IO uint8_t MCR_FTRMHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MCR_TTRM;
        stc_crtrim_mcr_ttrm_field_t MCR_TTRM_f;
        struct {
          union {
            __IO uint16_t MCR_TTRML;
            struct {
              __IO uint8_t MCR_TTRMLL;
              __IO uint8_t MCR_TTRMLH;
            };
          };
          union {
            __IO uint16_t MCR_TTRMH;
            struct {
              __IO uint8_t MCR_TTRMHL;
              __IO uint8_t MCR_TTRMHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MCR_RLR;
        stc_crtrim_mcr_rlr_field_t MCR_RLR_f;
        struct {
          union {
            __IO uint16_t MCR_RLRL;
            struct {
              __IO uint8_t MCR_RLRLL;
              __IO uint8_t MCR_RLRLH;
            };
          };
          union {
            __IO uint16_t MCR_RLRH;
            struct {
              __IO uint8_t MCR_RLRHL;
              __IO uint8_t MCR_RLRHH;
            };
          };
        };
    };
} FM_CRTRIM_TypeDef, FM4_CRTRIM_TypeDef;

/*******************************************************************************
* DAC_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO  uint8_t DACR;
        stc_dac_dacr_field_t DACR_f;
    };
        __IO  uint8_t RESERVED0[3];
    union {
        __IO uint16_t DADR;
        stc_dac_dadr_field_t DADR_f;
        struct {
            __IO  uint8_t DADRL;
            __IO  uint8_t DADRH;
        };
    };
} FM_DAC_TypeDef, FM4_DAC_TypeDef;

/*******************************************************************************
* DMAC_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO uint32_t DMACR;
        stc_dmac_dmacr_field_t DMACR_f;
        struct {
          union {
            __IO uint16_t DMACRL;
            struct {
              __IO uint8_t DMACRLL;
              __IO uint8_t DMACRLH;
            };
          };
          union {
            __IO uint16_t DMACRH;
            struct {
              __IO uint8_t DMACRHL;
              __IO uint8_t DMACRHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED0[12];
    union {
        __IO uint32_t DMACA0;
        stc_dmac_dmaca0_field_t DMACA0_f;
        struct {
          union {
            __IO uint16_t DMACA0L;
            struct {
              __IO uint8_t DMACA0LL;
              __IO uint8_t DMACA0LH;
            };
          };
          union {
            __IO uint16_t DMACA0H;
            struct {
              __IO uint8_t DMACA0HL;
              __IO uint8_t DMACA0HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DMACB0;
        stc_dmac_dmacb0_field_t DMACB0_f;
        struct {
          union {
            __IO uint16_t DMACB0L;
            struct {
              __IO uint8_t DMACB0LL;
              __IO uint8_t DMACB0LH;
            };
          };
          union {
            __IO uint16_t DMACB0H;
            struct {
              __IO uint8_t DMACB0HL;
              __IO uint8_t DMACB0HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DMACSA0;
        struct {
          union {
            __IO uint16_t DMACSA0L;
            struct {
              __IO uint8_t DMACSA0LL;
              __IO uint8_t DMACSA0LH;
            };
          };
          union {
            __IO uint16_t DMACSA0H;
            struct {
              __IO uint8_t DMACSA0HL;
              __IO uint8_t DMACSA0HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DMACDA0;
        struct {
          union {
            __IO uint16_t DMACDA0L;
            struct {
              __IO uint8_t DMACDA0LL;
              __IO uint8_t DMACDA0LH;
            };
          };
          union {
            __IO uint16_t DMACDA0H;
            struct {
              __IO uint8_t DMACDA0HL;
              __IO uint8_t DMACDA0HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DMACA1;
        stc_dmac_dmaca1_field_t DMACA1_f;
        struct {
          union {
            __IO uint16_t DMACA1L;
            struct {
              __IO uint8_t DMACA1LL;
              __IO uint8_t DMACA1LH;
            };
          };
          union {
            __IO uint16_t DMACA1H;
            struct {
              __IO uint8_t DMACA1HL;
              __IO uint8_t DMACA1HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DMACB1;
        stc_dmac_dmacb1_field_t DMACB1_f;
        struct {
          union {
            __IO uint16_t DMACB1L;
            struct {
              __IO uint8_t DMACB1LL;
              __IO uint8_t DMACB1LH;
            };
          };
          union {
            __IO uint16_t DMACB1H;
            struct {
              __IO uint8_t DMACB1HL;
              __IO uint8_t DMACB1HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DMACSA1;
        struct {
          union {
            __IO uint16_t DMACSA1L;
            struct {
              __IO uint8_t DMACSA1LL;
              __IO uint8_t DMACSA1LH;
            };
          };
          union {
            __IO uint16_t DMACSA1H;
            struct {
              __IO uint8_t DMACSA1HL;
              __IO uint8_t DMACSA1HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DMACDA1;
        struct {
          union {
            __IO uint16_t DMACDA1L;
            struct {
              __IO uint8_t DMACDA1LL;
              __IO uint8_t DMACDA1LH;
            };
          };
          union {
            __IO uint16_t DMACDA1H;
            struct {
              __IO uint8_t DMACDA1HL;
              __IO uint8_t DMACDA1HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DMACA2;
        stc_dmac_dmaca2_field_t DMACA2_f;
        struct {
          union {
            __IO uint16_t DMACA2L;
            struct {
              __IO uint8_t DMACA2LL;
              __IO uint8_t DMACA2LH;
            };
          };
          union {
            __IO uint16_t DMACA2H;
            struct {
              __IO uint8_t DMACA2HL;
              __IO uint8_t DMACA2HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DMACB2;
        stc_dmac_dmacb2_field_t DMACB2_f;
        struct {
          union {
            __IO uint16_t DMACB2L;
            struct {
              __IO uint8_t DMACB2LL;
              __IO uint8_t DMACB2LH;
            };
          };
          union {
            __IO uint16_t DMACB2H;
            struct {
              __IO uint8_t DMACB2HL;
              __IO uint8_t DMACB2HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DMACSA2;
        struct {
          union {
            __IO uint16_t DMACSA2L;
            struct {
              __IO uint8_t DMACSA2LL;
              __IO uint8_t DMACSA2LH;
            };
          };
          union {
            __IO uint16_t DMACSA2H;
            struct {
              __IO uint8_t DMACSA2HL;
              __IO uint8_t DMACSA2HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DMACDA2;
        struct {
          union {
            __IO uint16_t DMACDA2L;
            struct {
              __IO uint8_t DMACDA2LL;
              __IO uint8_t DMACDA2LH;
            };
          };
          union {
            __IO uint16_t DMACDA2H;
            struct {
              __IO uint8_t DMACDA2HL;
              __IO uint8_t DMACDA2HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DMACA3;
        stc_dmac_dmaca3_field_t DMACA3_f;
        struct {
          union {
            __IO uint16_t DMACA3L;
            struct {
              __IO uint8_t DMACA3LL;
              __IO uint8_t DMACA3LH;
            };
          };
          union {
            __IO uint16_t DMACA3H;
            struct {
              __IO uint8_t DMACA3HL;
              __IO uint8_t DMACA3HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DMACB3;
        stc_dmac_dmacb3_field_t DMACB3_f;
        struct {
          union {
            __IO uint16_t DMACB3L;
            struct {
              __IO uint8_t DMACB3LL;
              __IO uint8_t DMACB3LH;
            };
          };
          union {
            __IO uint16_t DMACB3H;
            struct {
              __IO uint8_t DMACB3HL;
              __IO uint8_t DMACB3HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DMACSA3;
        struct {
          union {
            __IO uint16_t DMACSA3L;
            struct {
              __IO uint8_t DMACSA3LL;
              __IO uint8_t DMACSA3LH;
            };
          };
          union {
            __IO uint16_t DMACSA3H;
            struct {
              __IO uint8_t DMACSA3HL;
              __IO uint8_t DMACSA3HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DMACDA3;
        struct {
          union {
            __IO uint16_t DMACDA3L;
            struct {
              __IO uint8_t DMACDA3LL;
              __IO uint8_t DMACDA3LH;
            };
          };
          union {
            __IO uint16_t DMACDA3H;
            struct {
              __IO uint8_t DMACDA3HL;
              __IO uint8_t DMACDA3HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DMACA4;
        stc_dmac_dmaca4_field_t DMACA4_f;
        struct {
          union {
            __IO uint16_t DMACA4L;
            struct {
              __IO uint8_t DMACA4LL;
              __IO uint8_t DMACA4LH;
            };
          };
          union {
            __IO uint16_t DMACA4H;
            struct {
              __IO uint8_t DMACA4HL;
              __IO uint8_t DMACA4HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DMACB4;
        stc_dmac_dmacb4_field_t DMACB4_f;
        struct {
          union {
            __IO uint16_t DMACB4L;
            struct {
              __IO uint8_t DMACB4LL;
              __IO uint8_t DMACB4LH;
            };
          };
          union {
            __IO uint16_t DMACB4H;
            struct {
              __IO uint8_t DMACB4HL;
              __IO uint8_t DMACB4HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DMACSA4;
        struct {
          union {
            __IO uint16_t DMACSA4L;
            struct {
              __IO uint8_t DMACSA4LL;
              __IO uint8_t DMACSA4LH;
            };
          };
          union {
            __IO uint16_t DMACSA4H;
            struct {
              __IO uint8_t DMACSA4HL;
              __IO uint8_t DMACSA4HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DMACDA4;
        struct {
          union {
            __IO uint16_t DMACDA4L;
            struct {
              __IO uint8_t DMACDA4LL;
              __IO uint8_t DMACDA4LH;
            };
          };
          union {
            __IO uint16_t DMACDA4H;
            struct {
              __IO uint8_t DMACDA4HL;
              __IO uint8_t DMACDA4HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DMACA5;
        stc_dmac_dmaca5_field_t DMACA5_f;
        struct {
          union {
            __IO uint16_t DMACA5L;
            struct {
              __IO uint8_t DMACA5LL;
              __IO uint8_t DMACA5LH;
            };
          };
          union {
            __IO uint16_t DMACA5H;
            struct {
              __IO uint8_t DMACA5HL;
              __IO uint8_t DMACA5HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DMACB5;
        stc_dmac_dmacb5_field_t DMACB5_f;
        struct {
          union {
            __IO uint16_t DMACB5L;
            struct {
              __IO uint8_t DMACB5LL;
              __IO uint8_t DMACB5LH;
            };
          };
          union {
            __IO uint16_t DMACB5H;
            struct {
              __IO uint8_t DMACB5HL;
              __IO uint8_t DMACB5HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DMACSA5;
        struct {
          union {
            __IO uint16_t DMACSA5L;
            struct {
              __IO uint8_t DMACSA5LL;
              __IO uint8_t DMACSA5LH;
            };
          };
          union {
            __IO uint16_t DMACSA5H;
            struct {
              __IO uint8_t DMACSA5HL;
              __IO uint8_t DMACSA5HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DMACDA5;
        struct {
          union {
            __IO uint16_t DMACDA5L;
            struct {
              __IO uint8_t DMACDA5LL;
              __IO uint8_t DMACDA5LH;
            };
          };
          union {
            __IO uint16_t DMACDA5H;
            struct {
              __IO uint8_t DMACDA5HL;
              __IO uint8_t DMACDA5HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DMACA6;
        stc_dmac_dmaca6_field_t DMACA6_f;
        struct {
          union {
            __IO uint16_t DMACA6L;
            struct {
              __IO uint8_t DMACA6LL;
              __IO uint8_t DMACA6LH;
            };
          };
          union {
            __IO uint16_t DMACA6H;
            struct {
              __IO uint8_t DMACA6HL;
              __IO uint8_t DMACA6HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DMACB6;
        stc_dmac_dmacb6_field_t DMACB6_f;
        struct {
          union {
            __IO uint16_t DMACB6L;
            struct {
              __IO uint8_t DMACB6LL;
              __IO uint8_t DMACB6LH;
            };
          };
          union {
            __IO uint16_t DMACB6H;
            struct {
              __IO uint8_t DMACB6HL;
              __IO uint8_t DMACB6HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DMACSA6;
        struct {
          union {
            __IO uint16_t DMACSA6L;
            struct {
              __IO uint8_t DMACSA6LL;
              __IO uint8_t DMACSA6LH;
            };
          };
          union {
            __IO uint16_t DMACSA6H;
            struct {
              __IO uint8_t DMACSA6HL;
              __IO uint8_t DMACSA6HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DMACDA6;
        struct {
          union {
            __IO uint16_t DMACDA6L;
            struct {
              __IO uint8_t DMACDA6LL;
              __IO uint8_t DMACDA6LH;
            };
          };
          union {
            __IO uint16_t DMACDA6H;
            struct {
              __IO uint8_t DMACDA6HL;
              __IO uint8_t DMACDA6HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DMACA7;
        stc_dmac_dmaca7_field_t DMACA7_f;
        struct {
          union {
            __IO uint16_t DMACA7L;
            struct {
              __IO uint8_t DMACA7LL;
              __IO uint8_t DMACA7LH;
            };
          };
          union {
            __IO uint16_t DMACA7H;
            struct {
              __IO uint8_t DMACA7HL;
              __IO uint8_t DMACA7HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DMACB7;
        stc_dmac_dmacb7_field_t DMACB7_f;
        struct {
          union {
            __IO uint16_t DMACB7L;
            struct {
              __IO uint8_t DMACB7LL;
              __IO uint8_t DMACB7LH;
            };
          };
          union {
            __IO uint16_t DMACB7H;
            struct {
              __IO uint8_t DMACB7HL;
              __IO uint8_t DMACB7HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DMACSA7;
        struct {
          union {
            __IO uint16_t DMACSA7L;
            struct {
              __IO uint8_t DMACSA7LL;
              __IO uint8_t DMACSA7LH;
            };
          };
          union {
            __IO uint16_t DMACSA7H;
            struct {
              __IO uint8_t DMACSA7HL;
              __IO uint8_t DMACSA7HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DMACDA7;
        struct {
          union {
            __IO uint16_t DMACDA7L;
            struct {
              __IO uint8_t DMACDA7LL;
              __IO uint8_t DMACDA7LH;
            };
          };
          union {
            __IO uint16_t DMACDA7H;
            struct {
              __IO uint8_t DMACDA7HL;
              __IO uint8_t DMACDA7HH;
            };
          };
        };
    };
} FM_DMAC_TypeDef, FM4_DMAC_TypeDef;

/*******************************************************************************
* DS_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
        __IO  uint8_t RESERVED0[4];
    union {
        __IO  uint8_t RCK_CTL;
        stc_ds_rck_ctl_field_t RCK_CTL_f;
    };
        __IO  uint8_t RESERVED1[1787];
    union {
        __IO  uint8_t PMD_CTL;
        stc_ds_pmd_ctl_field_t PMD_CTL_f;
    };
        __IO  uint8_t RESERVED2[3];
    union {
        __IO  uint8_t WRFSR;
        stc_ds_wrfsr_field_t WRFSR_f;
    };
        __IO  uint8_t RESERVED3[3];
    union {
        __IO uint16_t WIFSR;
        stc_ds_wifsr_field_t WIFSR_f;
        struct {
            __IO  uint8_t WIFSRL;
            __IO  uint8_t WIFSRH;
        };
    };
        __IO  uint8_t RESERVED4[2];
    union {
        __IO uint16_t WIER;
        stc_ds_wier_field_t WIER_f;
        struct {
            __IO  uint8_t WIERL;
            __IO  uint8_t WIERH;
        };
    };
        __IO  uint8_t RESERVED5[2];
    union {
        __IO  uint8_t WILVR;
        stc_ds_wilvr_field_t WILVR_f;
    };
        __IO  uint8_t RESERVED6[3];
    union {
        __IO  uint8_t DSRAMR;
        stc_ds_dsramr_field_t DSRAMR_f;
    };
        __IO  uint8_t RESERVED7[235];
        __IO  uint8_t BUR01;
        __IO  uint8_t BUR02;
        __IO  uint8_t BUR03;
        __IO  uint8_t BUR04;
        __IO  uint8_t BUR05;
        __IO  uint8_t BUR06;
        __IO  uint8_t BUR07;
        __IO  uint8_t BUR08;
        __IO  uint8_t BUR09;
        __IO  uint8_t BUR10;
        __IO  uint8_t BUR11;
        __IO  uint8_t BUR12;
        __IO  uint8_t BUR13;
        __IO  uint8_t BUR14;
        __IO  uint8_t BUR15;
        __IO  uint8_t BUR16;
} FM_DS_TypeDef, FM4_DS_TypeDef;

/*******************************************************************************
* DSTC_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO uint32_t DESTP;
        struct {
          union {
            __IO uint16_t DESTPL;
            struct {
              __IO uint8_t DESTPLL;
              __IO uint8_t DESTPLH;
            };
          };
          union {
            __IO uint16_t DESTPH;
            struct {
              __IO uint8_t DESTPHL;
              __IO uint8_t DESTPHH;
            };
          };
        };
    };
    union {
        __IO uint32_t HWDESP;
        stc_dstc_hwdesp_field_t HWDESP_f;
        struct {
          union {
            __IO uint16_t HWDESPL;
            struct {
              __IO uint8_t HWDESPLL;
              __IO uint8_t HWDESPLH;
            };
          };
          union {
            __IO uint16_t HWDESPH;
            struct {
              __IO uint8_t HWDESPHL;
              __IO uint8_t HWDESPHH;
            };
          };
        };
    };
        __IO  uint8_t CMD;
    union {
        __IO  uint8_t CFG;
        stc_dstc_cfg_field_t CFG_f;
    };
    union {
        __IO uint16_t SWTR;
        stc_dstc_swtr_field_t SWTR_f;
        struct {
            __IO  uint8_t SWTRL;
            __IO  uint8_t SWTRH;
        };
    };
    union {
        __IO uint32_t MONERS;
        stc_dstc_moners_field_t MONERS_f;
        struct {
          union {
            __IO uint16_t MONERSL;
            struct {
              __IO uint8_t MONERSLL;
              __IO uint8_t MONERSLH;
            };
          };
          union {
            __IO uint16_t MONERSH;
            struct {
              __IO uint8_t MONERSHL;
              __IO uint8_t MONERSHH;
            };
          };
        };
    };
    union {
        __IO uint32_t DREQENB0;
        struct {
          union {
            __IO uint16_t DREQENB0L;
            struct {
              __IO uint8_t DREQENB0LL;
              __IO uint8_t DREQENB0LH;
            };
          };
          union {
            __IO uint16_t DREQENB0H;
            struct {
              __IO uint8_t DREQENB0HL;
              __IO uint8_t DREQENB0HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DREQENB1;
        struct {
          union {
            __IO uint16_t DREQENB1L;
            struct {
              __IO uint8_t DREQENB1LL;
              __IO uint8_t DREQENB1LH;
            };
          };
          union {
            __IO uint16_t DREQENB1H;
            struct {
              __IO uint8_t DREQENB1HL;
              __IO uint8_t DREQENB1HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DREQENB2;
        struct {
          union {
            __IO uint16_t DREQENB2L;
            struct {
              __IO uint8_t DREQENB2LL;
              __IO uint8_t DREQENB2LH;
            };
          };
          union {
            __IO uint16_t DREQENB2H;
            struct {
              __IO uint8_t DREQENB2HL;
              __IO uint8_t DREQENB2HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DREQENB3;
        struct {
          union {
            __IO uint16_t DREQENB3L;
            struct {
              __IO uint8_t DREQENB3LL;
              __IO uint8_t DREQENB3LH;
            };
          };
          union {
            __IO uint16_t DREQENB3H;
            struct {
              __IO uint8_t DREQENB3HL;
              __IO uint8_t DREQENB3HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DREQENB4;
        struct {
          union {
            __IO uint16_t DREQENB4L;
            struct {
              __IO uint8_t DREQENB4LL;
              __IO uint8_t DREQENB4LH;
            };
          };
          union {
            __IO uint16_t DREQENB4H;
            struct {
              __IO uint8_t DREQENB4HL;
              __IO uint8_t DREQENB4HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DREQENB5;
        struct {
          union {
            __IO uint16_t DREQENB5L;
            struct {
              __IO uint8_t DREQENB5LL;
              __IO uint8_t DREQENB5LH;
            };
          };
          union {
            __IO uint16_t DREQENB5H;
            struct {
              __IO uint8_t DREQENB5HL;
              __IO uint8_t DREQENB5HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DREQENB6;
        struct {
          union {
            __IO uint16_t DREQENB6L;
            struct {
              __IO uint8_t DREQENB6LL;
              __IO uint8_t DREQENB6LH;
            };
          };
          union {
            __IO uint16_t DREQENB6H;
            struct {
              __IO uint8_t DREQENB6HL;
              __IO uint8_t DREQENB6HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DREQENB7;
        struct {
          union {
            __IO uint16_t DREQENB7L;
            struct {
              __IO uint8_t DREQENB7LL;
              __IO uint8_t DREQENB7LH;
            };
          };
          union {
            __IO uint16_t DREQENB7H;
            struct {
              __IO uint8_t DREQENB7HL;
              __IO uint8_t DREQENB7HH;
            };
          };
        };
    };
    union {
        __IO uint32_t HWINT0;
        struct {
          union {
            __IO uint16_t HWINT0L;
            struct {
              __IO uint8_t HWINT0LL;
              __IO uint8_t HWINT0LH;
            };
          };
          union {
            __IO uint16_t HWINT0H;
            struct {
              __IO uint8_t HWINT0HL;
              __IO uint8_t HWINT0HH;
            };
          };
        };
    };
    union {
        __IO uint32_t HWINT1;
        struct {
          union {
            __IO uint16_t HWINT1L;
            struct {
              __IO uint8_t HWINT1LL;
              __IO uint8_t HWINT1LH;
            };
          };
          union {
            __IO uint16_t HWINT1H;
            struct {
              __IO uint8_t HWINT1HL;
              __IO uint8_t HWINT1HH;
            };
          };
        };
    };
    union {
        __IO uint32_t HWINT2;
        struct {
          union {
            __IO uint16_t HWINT2L;
            struct {
              __IO uint8_t HWINT2LL;
              __IO uint8_t HWINT2LH;
            };
          };
          union {
            __IO uint16_t HWINT2H;
            struct {
              __IO uint8_t HWINT2HL;
              __IO uint8_t HWINT2HH;
            };
          };
        };
    };
    union {
        __IO uint32_t HWINT3;
        struct {
          union {
            __IO uint16_t HWINT3L;
            struct {
              __IO uint8_t HWINT3LL;
              __IO uint8_t HWINT3LH;
            };
          };
          union {
            __IO uint16_t HWINT3H;
            struct {
              __IO uint8_t HWINT3HL;
              __IO uint8_t HWINT3HH;
            };
          };
        };
    };
    union {
        __IO uint32_t HWINT4;
        struct {
          union {
            __IO uint16_t HWINT4L;
            struct {
              __IO uint8_t HWINT4LL;
              __IO uint8_t HWINT4LH;
            };
          };
          union {
            __IO uint16_t HWINT4H;
            struct {
              __IO uint8_t HWINT4HL;
              __IO uint8_t HWINT4HH;
            };
          };
        };
    };
    union {
        __IO uint32_t HWINT5;
        struct {
          union {
            __IO uint16_t HWINT5L;
            struct {
              __IO uint8_t HWINT5LL;
              __IO uint8_t HWINT5LH;
            };
          };
          union {
            __IO uint16_t HWINT5H;
            struct {
              __IO uint8_t HWINT5HL;
              __IO uint8_t HWINT5HH;
            };
          };
        };
    };
    union {
        __IO uint32_t HWINT6;
        struct {
          union {
            __IO uint16_t HWINT6L;
            struct {
              __IO uint8_t HWINT6LL;
              __IO uint8_t HWINT6LH;
            };
          };
          union {
            __IO uint16_t HWINT6H;
            struct {
              __IO uint8_t HWINT6HL;
              __IO uint8_t HWINT6HH;
            };
          };
        };
    };
    union {
        __IO uint32_t HWINT7;
        struct {
          union {
            __IO uint16_t HWINT7L;
            struct {
              __IO uint8_t HWINT7LL;
              __IO uint8_t HWINT7LH;
            };
          };
          union {
            __IO uint16_t HWINT7H;
            struct {
              __IO uint8_t HWINT7HL;
              __IO uint8_t HWINT7HH;
            };
          };
        };
    };
    union {
        __IO uint32_t HWINTCLR0;
        struct {
          union {
            __IO uint16_t HWINTCLR0L;
            struct {
              __IO uint8_t HWINTCLR0LL;
              __IO uint8_t HWINTCLR0LH;
            };
          };
          union {
            __IO uint16_t HWINTCLR0H;
            struct {
              __IO uint8_t HWINTCLR0HL;
              __IO uint8_t HWINTCLR0HH;
            };
          };
        };
    };
    union {
        __IO uint32_t HWINTCLR1;
        struct {
          union {
            __IO uint16_t HWINTCLR1L;
            struct {
              __IO uint8_t HWINTCLR1LL;
              __IO uint8_t HWINTCLR1LH;
            };
          };
          union {
            __IO uint16_t HWINTCLR1H;
            struct {
              __IO uint8_t HWINTCLR1HL;
              __IO uint8_t HWINTCLR1HH;
            };
          };
        };
    };
    union {
        __IO uint32_t HWINTCLR2;
        struct {
          union {
            __IO uint16_t HWINTCLR2L;
            struct {
              __IO uint8_t HWINTCLR2LL;
              __IO uint8_t HWINTCLR2LH;
            };
          };
          union {
            __IO uint16_t HWINTCLR2H;
            struct {
              __IO uint8_t HWINTCLR2HL;
              __IO uint8_t HWINTCLR2HH;
            };
          };
        };
    };
    union {
        __IO uint32_t HWINTCLR3;
        struct {
          union {
            __IO uint16_t HWINTCLR3L;
            struct {
              __IO uint8_t HWINTCLR3LL;
              __IO uint8_t HWINTCLR3LH;
            };
          };
          union {
            __IO uint16_t HWINTCLR3H;
            struct {
              __IO uint8_t HWINTCLR3HL;
              __IO uint8_t HWINTCLR3HH;
            };
          };
        };
    };
    union {
        __IO uint32_t HWINTCLR4;
        struct {
          union {
            __IO uint16_t HWINTCLR4L;
            struct {
              __IO uint8_t HWINTCLR4LL;
              __IO uint8_t HWINTCLR4LH;
            };
          };
          union {
            __IO uint16_t HWINTCLR4H;
            struct {
              __IO uint8_t HWINTCLR4HL;
              __IO uint8_t HWINTCLR4HH;
            };
          };
        };
    };
    union {
        __IO uint32_t HWINTCLR5;
        struct {
          union {
            __IO uint16_t HWINTCLR5L;
            struct {
              __IO uint8_t HWINTCLR5LL;
              __IO uint8_t HWINTCLR5LH;
            };
          };
          union {
            __IO uint16_t HWINTCLR5H;
            struct {
              __IO uint8_t HWINTCLR5HL;
              __IO uint8_t HWINTCLR5HH;
            };
          };
        };
    };
    union {
        __IO uint32_t HWINTCLR6;
        struct {
          union {
            __IO uint16_t HWINTCLR6L;
            struct {
              __IO uint8_t HWINTCLR6LL;
              __IO uint8_t HWINTCLR6LH;
            };
          };
          union {
            __IO uint16_t HWINTCLR6H;
            struct {
              __IO uint8_t HWINTCLR6HL;
              __IO uint8_t HWINTCLR6HH;
            };
          };
        };
    };
    union {
        __IO uint32_t HWINTCLR7;
        struct {
          union {
            __IO uint16_t HWINTCLR7L;
            struct {
              __IO uint8_t HWINTCLR7LL;
              __IO uint8_t HWINTCLR7LH;
            };
          };
          union {
            __IO uint16_t HWINTCLR7H;
            struct {
              __IO uint8_t HWINTCLR7HL;
              __IO uint8_t HWINTCLR7HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DQMSK0;
        struct {
          union {
            __IO uint16_t DQMSK0L;
            struct {
              __IO uint8_t DQMSK0LL;
              __IO uint8_t DQMSK0LH;
            };
          };
          union {
            __IO uint16_t DQMSK0H;
            struct {
              __IO uint8_t DQMSK0HL;
              __IO uint8_t DQMSK0HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DQMSK1;
        struct {
          union {
            __IO uint16_t DQMSK1L;
            struct {
              __IO uint8_t DQMSK1LL;
              __IO uint8_t DQMSK1LH;
            };
          };
          union {
            __IO uint16_t DQMSK1H;
            struct {
              __IO uint8_t DQMSK1HL;
              __IO uint8_t DQMSK1HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DQMSK2;
        struct {
          union {
            __IO uint16_t DQMSK2L;
            struct {
              __IO uint8_t DQMSK2LL;
              __IO uint8_t DQMSK2LH;
            };
          };
          union {
            __IO uint16_t DQMSK2H;
            struct {
              __IO uint8_t DQMSK2HL;
              __IO uint8_t DQMSK2HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DQMSK3;
        struct {
          union {
            __IO uint16_t DQMSK3L;
            struct {
              __IO uint8_t DQMSK3LL;
              __IO uint8_t DQMSK3LH;
            };
          };
          union {
            __IO uint16_t DQMSK3H;
            struct {
              __IO uint8_t DQMSK3HL;
              __IO uint8_t DQMSK3HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DQMSK4;
        struct {
          union {
            __IO uint16_t DQMSK4L;
            struct {
              __IO uint8_t DQMSK4LL;
              __IO uint8_t DQMSK4LH;
            };
          };
          union {
            __IO uint16_t DQMSK4H;
            struct {
              __IO uint8_t DQMSK4HL;
              __IO uint8_t DQMSK4HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DQMSK5;
        struct {
          union {
            __IO uint16_t DQMSK5L;
            struct {
              __IO uint8_t DQMSK5LL;
              __IO uint8_t DQMSK5LH;
            };
          };
          union {
            __IO uint16_t DQMSK5H;
            struct {
              __IO uint8_t DQMSK5HL;
              __IO uint8_t DQMSK5HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DQMSK6;
        struct {
          union {
            __IO uint16_t DQMSK6L;
            struct {
              __IO uint8_t DQMSK6LL;
              __IO uint8_t DQMSK6LH;
            };
          };
          union {
            __IO uint16_t DQMSK6H;
            struct {
              __IO uint8_t DQMSK6HL;
              __IO uint8_t DQMSK6HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DQMSK7;
        struct {
          union {
            __IO uint16_t DQMSK7L;
            struct {
              __IO uint8_t DQMSK7LL;
              __IO uint8_t DQMSK7LH;
            };
          };
          union {
            __IO uint16_t DQMSK7H;
            struct {
              __IO uint8_t DQMSK7HL;
              __IO uint8_t DQMSK7HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DQMSKCLR0;
        struct {
          union {
            __IO uint16_t DQMSKCLR0L;
            struct {
              __IO uint8_t DQMSKCLR0LL;
              __IO uint8_t DQMSKCLR0LH;
            };
          };
          union {
            __IO uint16_t DQMSKCLR0H;
            struct {
              __IO uint8_t DQMSKCLR0HL;
              __IO uint8_t DQMSKCLR0HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DQMSKCLR1;
        struct {
          union {
            __IO uint16_t DQMSKCLR1L;
            struct {
              __IO uint8_t DQMSKCLR1LL;
              __IO uint8_t DQMSKCLR1LH;
            };
          };
          union {
            __IO uint16_t DQMSKCLR1H;
            struct {
              __IO uint8_t DQMSKCLR1HL;
              __IO uint8_t DQMSKCLR1HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DQMSKCLR2;
        struct {
          union {
            __IO uint16_t DQMSKCLR2L;
            struct {
              __IO uint8_t DQMSKCLR2LL;
              __IO uint8_t DQMSKCLR2LH;
            };
          };
          union {
            __IO uint16_t DQMSKCLR2H;
            struct {
              __IO uint8_t DQMSKCLR2HL;
              __IO uint8_t DQMSKCLR2HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DQMSKCLR3;
        struct {
          union {
            __IO uint16_t DQMSKCLR3L;
            struct {
              __IO uint8_t DQMSKCLR3LL;
              __IO uint8_t DQMSKCLR3LH;
            };
          };
          union {
            __IO uint16_t DQMSKCLR3H;
            struct {
              __IO uint8_t DQMSKCLR3HL;
              __IO uint8_t DQMSKCLR3HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DQMSKCLR4;
        struct {
          union {
            __IO uint16_t DQMSKCLR4L;
            struct {
              __IO uint8_t DQMSKCLR4LL;
              __IO uint8_t DQMSKCLR4LH;
            };
          };
          union {
            __IO uint16_t DQMSKCLR4H;
            struct {
              __IO uint8_t DQMSKCLR4HL;
              __IO uint8_t DQMSKCLR4HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DQMSKCLR5;
        struct {
          union {
            __IO uint16_t DQMSKCLR5L;
            struct {
              __IO uint8_t DQMSKCLR5LL;
              __IO uint8_t DQMSKCLR5LH;
            };
          };
          union {
            __IO uint16_t DQMSKCLR5H;
            struct {
              __IO uint8_t DQMSKCLR5HL;
              __IO uint8_t DQMSKCLR5HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DQMSKCLR6;
        struct {
          union {
            __IO uint16_t DQMSKCLR6L;
            struct {
              __IO uint8_t DQMSKCLR6LL;
              __IO uint8_t DQMSKCLR6LH;
            };
          };
          union {
            __IO uint16_t DQMSKCLR6H;
            struct {
              __IO uint8_t DQMSKCLR6HL;
              __IO uint8_t DQMSKCLR6HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DQMSKCLR7;
        struct {
          union {
            __IO uint16_t DQMSKCLR7L;
            struct {
              __IO uint8_t DQMSKCLR7LL;
              __IO uint8_t DQMSKCLR7LH;
            };
          };
          union {
            __IO uint16_t DQMSKCLR7H;
            struct {
              __IO uint8_t DQMSKCLR7HL;
              __IO uint8_t DQMSKCLR7HH;
            };
          };
        };
    };
} FM_DSTC_TypeDef, FM4_DSTC_TypeDef;

/*******************************************************************************
* DT_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO uint32_t TIMER1LOAD;
        struct {
          union {
            __IO uint16_t TIMER1LOADL;
            struct {
              __IO uint8_t TIMER1LOADLL;
              __IO uint8_t TIMER1LOADLH;
            };
          };
          union {
            __IO uint16_t TIMER1LOADH;
            struct {
              __IO uint8_t TIMER1LOADHL;
              __IO uint8_t TIMER1LOADHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TIMER1VALUE;
        struct {
          union {
            __IO uint16_t TIMER1VALUEL;
            struct {
              __IO uint8_t TIMER1VALUELL;
              __IO uint8_t TIMER1VALUELH;
            };
          };
          union {
            __IO uint16_t TIMER1VALUEH;
            struct {
              __IO uint8_t TIMER1VALUEHL;
              __IO uint8_t TIMER1VALUEHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TIMER1CONTROL;
        stc_dt_timer1control_field_t TIMER1CONTROL_f;
        struct {
          union {
            __IO uint16_t TIMER1CONTROLL;
            struct {
              __IO uint8_t TIMER1CONTROLLL;
              __IO uint8_t TIMER1CONTROLLH;
            };
          };
          union {
            __IO uint16_t TIMER1CONTROLH;
            struct {
              __IO uint8_t TIMER1CONTROLHL;
              __IO uint8_t TIMER1CONTROLHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TIMER1INTCLR;
        struct {
          union {
            __IO uint16_t TIMER1INTCLRL;
            struct {
              __IO uint8_t TIMER1INTCLRLL;
              __IO uint8_t TIMER1INTCLRLH;
            };
          };
          union {
            __IO uint16_t TIMER1INTCLRH;
            struct {
              __IO uint8_t TIMER1INTCLRHL;
              __IO uint8_t TIMER1INTCLRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TIMER1RIS;
        stc_dt_timer1ris_field_t TIMER1RIS_f;
        struct {
          union {
            __IO uint16_t TIMER1RISL;
            struct {
              __IO uint8_t TIMER1RISLL;
              __IO uint8_t TIMER1RISLH;
            };
          };
          union {
            __IO uint16_t TIMER1RISH;
            struct {
              __IO uint8_t TIMER1RISHL;
              __IO uint8_t TIMER1RISHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TIMER1MIS;
        stc_dt_timer1mis_field_t TIMER1MIS_f;
        struct {
          union {
            __IO uint16_t TIMER1MISL;
            struct {
              __IO uint8_t TIMER1MISLL;
              __IO uint8_t TIMER1MISLH;
            };
          };
          union {
            __IO uint16_t TIMER1MISH;
            struct {
              __IO uint8_t TIMER1MISHL;
              __IO uint8_t TIMER1MISHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TIMER1BGLOAD;
        struct {
          union {
            __IO uint16_t TIMER1BGLOADL;
            struct {
              __IO uint8_t TIMER1BGLOADLL;
              __IO uint8_t TIMER1BGLOADLH;
            };
          };
          union {
            __IO uint16_t TIMER1BGLOADH;
            struct {
              __IO uint8_t TIMER1BGLOADHL;
              __IO uint8_t TIMER1BGLOADHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED0[4];
    union {
        __IO uint32_t TIMER2LOAD;
        struct {
          union {
            __IO uint16_t TIMER2LOADL;
            struct {
              __IO uint8_t TIMER2LOADLL;
              __IO uint8_t TIMER2LOADLH;
            };
          };
          union {
            __IO uint16_t TIMER2LOADH;
            struct {
              __IO uint8_t TIMER2LOADHL;
              __IO uint8_t TIMER2LOADHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TIMER2VALUE;
        struct {
          union {
            __IO uint16_t TIMER2VALUEL;
            struct {
              __IO uint8_t TIMER2VALUELL;
              __IO uint8_t TIMER2VALUELH;
            };
          };
          union {
            __IO uint16_t TIMER2VALUEH;
            struct {
              __IO uint8_t TIMER2VALUEHL;
              __IO uint8_t TIMER2VALUEHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TIMER2CONTROL;
        stc_dt_timer2control_field_t TIMER2CONTROL_f;
        struct {
          union {
            __IO uint16_t TIMER2CONTROLL;
            struct {
              __IO uint8_t TIMER2CONTROLLL;
              __IO uint8_t TIMER2CONTROLLH;
            };
          };
          union {
            __IO uint16_t TIMER2CONTROLH;
            struct {
              __IO uint8_t TIMER2CONTROLHL;
              __IO uint8_t TIMER2CONTROLHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TIMER2INTCLR;
        struct {
          union {
            __IO uint16_t TIMER2INTCLRL;
            struct {
              __IO uint8_t TIMER2INTCLRLL;
              __IO uint8_t TIMER2INTCLRLH;
            };
          };
          union {
            __IO uint16_t TIMER2INTCLRH;
            struct {
              __IO uint8_t TIMER2INTCLRHL;
              __IO uint8_t TIMER2INTCLRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TIMER2RIS;
        stc_dt_timer2ris_field_t TIMER2RIS_f;
        struct {
          union {
            __IO uint16_t TIMER2RISL;
            struct {
              __IO uint8_t TIMER2RISLL;
              __IO uint8_t TIMER2RISLH;
            };
          };
          union {
            __IO uint16_t TIMER2RISH;
            struct {
              __IO uint8_t TIMER2RISHL;
              __IO uint8_t TIMER2RISHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TIMER2MIS;
        stc_dt_timer2mis_field_t TIMER2MIS_f;
        struct {
          union {
            __IO uint16_t TIMER2MISL;
            struct {
              __IO uint8_t TIMER2MISLL;
              __IO uint8_t TIMER2MISLH;
            };
          };
          union {
            __IO uint16_t TIMER2MISH;
            struct {
              __IO uint8_t TIMER2MISHL;
              __IO uint8_t TIMER2MISHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TIMER2BGLOAD;
        struct {
          union {
            __IO uint16_t TIMER2BGLOADL;
            struct {
              __IO uint8_t TIMER2BGLOADLL;
              __IO uint8_t TIMER2BGLOADLH;
            };
          };
          union {
            __IO uint16_t TIMER2BGLOADH;
            struct {
              __IO uint8_t TIMER2BGLOADHL;
              __IO uint8_t TIMER2BGLOADHH;
            };
          };
        };
    };
} FM_DT_TypeDef, FM4_DT_TypeDef;

/*******************************************************************************
* DUALFLASH_IF_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO uint32_t DFASZR;
        stc_dualflash_if_dfaszr_field_t DFASZR_f;
        struct {
          union {
            __IO uint16_t DFASZRL;
            struct {
              __IO uint8_t DFASZRLL;
              __IO uint8_t DFASZRLH;
            };
          };
          union {
            __IO uint16_t DFASZRH;
            struct {
              __IO uint8_t DFASZRHL;
              __IO uint8_t DFASZRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t DFRWTR;
        stc_dualflash_if_dfrwtr_field_t DFRWTR_f;
        struct {
          union {
            __IO uint16_t DFRWTRL;
            struct {
              __IO uint8_t DFRWTRLL;
              __IO uint8_t DFRWTRLH;
            };
          };
          union {
            __IO uint16_t DFRWTRH;
            struct {
              __IO uint8_t DFRWTRHL;
              __IO uint8_t DFRWTRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t DFSTR;
        stc_dualflash_if_dfstr_field_t DFSTR_f;
        struct {
          union {
            __IO uint16_t DFSTRL;
            struct {
              __IO uint8_t DFSTRLL;
              __IO uint8_t DFSTRLH;
            };
          };
          union {
            __IO uint16_t DFSTRH;
            struct {
              __IO uint8_t DFSTRHL;
              __IO uint8_t DFSTRHH;
            };
          };
        };
    };
} FM_DUALFLASH_IF_TypeDef, FM4_DUALFLASH_IF_TypeDef;

/*******************************************************************************
* ECC_CAPTURE_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO uint32_t FERRAD;
        stc_ecc_capture_ferrad_field_t FERRAD_f;
        struct {
          union {
            __IO uint16_t FERRADL;
            struct {
              __IO uint8_t FERRADLL;
              __IO uint8_t FERRADLH;
            };
          };
          union {
            __IO uint16_t FERRADH;
            struct {
              __IO uint8_t FERRADHL;
              __IO uint8_t FERRADHH;
            };
          };
        };
    };
} FM_ECC_CAPTURE_TypeDef, FM4_ECC_CAPTURE_TypeDef;

/*******************************************************************************
* ETHERNET_CONTROL_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO uint32_t ETH_MODE;
        stc_ethernet_control_eth_mode_field_t ETH_MODE_f;
        struct {
          union {
            __IO uint16_t ETH_MODEL;
            struct {
              __IO uint8_t ETH_MODELL;
              __IO uint8_t ETH_MODELH;
            };
          };
          union {
            __IO uint16_t ETH_MODEH;
            struct {
              __IO uint8_t ETH_MODEHL;
              __IO uint8_t ETH_MODEHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED0[4];
    union {
        __IO uint32_t ETH_CLKG;
        stc_ethernet_control_eth_clkg_field_t ETH_CLKG_f;
        struct {
          union {
            __IO uint16_t ETH_CLKGL;
            struct {
              __IO uint8_t ETH_CLKGLL;
              __IO uint8_t ETH_CLKGLH;
            };
          };
          union {
            __IO uint16_t ETH_CLKGH;
            struct {
              __IO uint8_t ETH_CLKGHL;
              __IO uint8_t ETH_CLKGHH;
            };
          };
        };
    };
} FM_ETHERNET_CONTROL_TypeDef, FM4_ETHERNET_CONTROL_TypeDef;

/*******************************************************************************
* ETHERNET_MAC_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO uint32_t MCR;
        stc_ethernet_mac_mcr_field_t MCR_f;
        struct {
          union {
            __IO uint16_t MCRL;
            struct {
              __IO uint8_t MCRLL;
              __IO uint8_t MCRLH;
            };
          };
          union {
            __IO uint16_t MCRH;
            struct {
              __IO uint8_t MCRHL;
              __IO uint8_t MCRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MFFR;
        stc_ethernet_mac_mffr_field_t MFFR_f;
        struct {
          union {
            __IO uint16_t MFFRL;
            struct {
              __IO uint8_t MFFRLL;
              __IO uint8_t MFFRLH;
            };
          };
          union {
            __IO uint16_t MFFRH;
            struct {
              __IO uint8_t MFFRHL;
              __IO uint8_t MFFRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MHTRH;
        stc_ethernet_mac_mhtrh_field_t MHTRH_f;
        struct {
          union {
            __IO uint16_t MHTRHL;
            struct {
              __IO uint8_t MHTRHLL;
              __IO uint8_t MHTRHLH;
            };
          };
          union {
            __IO uint16_t MHTRHH;
            struct {
              __IO uint8_t MHTRHHL;
              __IO uint8_t MHTRHHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MHTRL;
        stc_ethernet_mac_mhtrl_field_t MHTRL_f;
        struct {
          union {
            __IO uint16_t MHTRLL;
            struct {
              __IO uint8_t MHTRLLL;
              __IO uint8_t MHTRLLH;
            };
          };
          union {
            __IO uint16_t MHTRLH;
            struct {
              __IO uint8_t MHTRLHL;
              __IO uint8_t MHTRLHH;
            };
          };
        };
    };
    union {
        __IO uint32_t GAR;
        stc_ethernet_mac_gar_field_t GAR_f;
        struct {
          union {
            __IO uint16_t GARL;
            struct {
              __IO uint8_t GARLL;
              __IO uint8_t GARLH;
            };
          };
          union {
            __IO uint16_t GARH;
            struct {
              __IO uint8_t GARHL;
              __IO uint8_t GARHH;
            };
          };
        };
    };
    union {
        __IO uint32_t GDR;
        stc_ethernet_mac_gdr_field_t GDR_f;
        struct {
          union {
            __IO uint16_t GDRL;
            struct {
              __IO uint8_t GDRLL;
              __IO uint8_t GDRLH;
            };
          };
          union {
            __IO uint16_t GDRH;
            struct {
              __IO uint8_t GDRHL;
              __IO uint8_t GDRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t FCR;
        stc_ethernet_mac_fcr_field_t FCR_f;
        struct {
          union {
            __IO uint16_t FCRL;
            struct {
              __IO uint8_t FCRLL;
              __IO uint8_t FCRLH;
            };
          };
          union {
            __IO uint16_t FCRH;
            struct {
              __IO uint8_t FCRHL;
              __IO uint8_t FCRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t VTR;
        stc_ethernet_mac_vtr_field_t VTR_f;
        struct {
          union {
            __IO uint16_t VTRL;
            struct {
              __IO uint8_t VTRLL;
              __IO uint8_t VTRLH;
            };
          };
          union {
            __IO uint16_t VTRH;
            struct {
              __IO uint8_t VTRHL;
              __IO uint8_t VTRHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED0[8];
    union {
        __IO uint32_t RWFFR;
        stc_ethernet_mac_rwffr_field_t RWFFR_f;
        struct {
          union {
            __IO uint16_t RWFFRL;
            struct {
              __IO uint8_t RWFFRLL;
              __IO uint8_t RWFFRLH;
            };
          };
          union {
            __IO uint16_t RWFFRH;
            struct {
              __IO uint8_t RWFFRHL;
              __IO uint8_t RWFFRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PMTR;
        stc_ethernet_mac_pmtr_field_t PMTR_f;
        struct {
          union {
            __IO uint16_t PMTRL;
            struct {
              __IO uint8_t PMTRLL;
              __IO uint8_t PMTRLH;
            };
          };
          union {
            __IO uint16_t PMTRH;
            struct {
              __IO uint8_t PMTRHL;
              __IO uint8_t PMTRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t LPICSR;
        stc_ethernet_mac_lpicsr_field_t LPICSR_f;
        struct {
          union {
            __IO uint16_t LPICSRL;
            struct {
              __IO uint8_t LPICSRLL;
              __IO uint8_t LPICSRLH;
            };
          };
          union {
            __IO uint16_t LPICSRH;
            struct {
              __IO uint8_t LPICSRHL;
              __IO uint8_t LPICSRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t LPITCR;
        stc_ethernet_mac_lpitcr_field_t LPITCR_f;
        struct {
          union {
            __IO uint16_t LPITCRL;
            struct {
              __IO uint8_t LPITCRLL;
              __IO uint8_t LPITCRLH;
            };
          };
          union {
            __IO uint16_t LPITCRH;
            struct {
              __IO uint8_t LPITCRHL;
              __IO uint8_t LPITCRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t ISR;
        stc_ethernet_mac_isr_field_t ISR_f;
        struct {
          union {
            __IO uint16_t ISRL;
            struct {
              __IO uint8_t ISRLL;
              __IO uint8_t ISRLH;
            };
          };
          union {
            __IO uint16_t ISRH;
            struct {
              __IO uint8_t ISRHL;
              __IO uint8_t ISRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IMR;
        stc_ethernet_mac_imr_field_t IMR_f;
        struct {
          union {
            __IO uint16_t IMRL;
            struct {
              __IO uint8_t IMRLL;
              __IO uint8_t IMRLH;
            };
          };
          union {
            __IO uint16_t IMRH;
            struct {
              __IO uint8_t IMRHL;
              __IO uint8_t IMRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR0H;
        stc_ethernet_mac_mar0h_field_t MAR0H_f;
        struct {
          union {
            __IO uint16_t MAR0HL;
            struct {
              __IO uint8_t MAR0HLL;
              __IO uint8_t MAR0HLH;
            };
          };
          union {
            __IO uint16_t MAR0HH;
            struct {
              __IO uint8_t MAR0HHL;
              __IO uint8_t MAR0HHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR0L;
        stc_ethernet_mac_mar0l_field_t MAR0L_f;
        struct {
          union {
            __IO uint16_t MAR0LL;
            struct {
              __IO uint8_t MAR0LLL;
              __IO uint8_t MAR0LLH;
            };
          };
          union {
            __IO uint16_t MAR0LH;
            struct {
              __IO uint8_t MAR0LHL;
              __IO uint8_t MAR0LHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR1H;
        stc_ethernet_mac_mar1h_field_t MAR1H_f;
        struct {
          union {
            __IO uint16_t MAR1HL;
            struct {
              __IO uint8_t MAR1HLL;
              __IO uint8_t MAR1HLH;
            };
          };
          union {
            __IO uint16_t MAR1HH;
            struct {
              __IO uint8_t MAR1HHL;
              __IO uint8_t MAR1HHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR1L;
        stc_ethernet_mac_mar1l_field_t MAR1L_f;
        struct {
          union {
            __IO uint16_t MAR1LL;
            struct {
              __IO uint8_t MAR1LLL;
              __IO uint8_t MAR1LLH;
            };
          };
          union {
            __IO uint16_t MAR1LH;
            struct {
              __IO uint8_t MAR1LHL;
              __IO uint8_t MAR1LHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR2H;
        stc_ethernet_mac_mar2h_field_t MAR2H_f;
        struct {
          union {
            __IO uint16_t MAR2HL;
            struct {
              __IO uint8_t MAR2HLL;
              __IO uint8_t MAR2HLH;
            };
          };
          union {
            __IO uint16_t MAR2HH;
            struct {
              __IO uint8_t MAR2HHL;
              __IO uint8_t MAR2HHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR2L;
        stc_ethernet_mac_mar2l_field_t MAR2L_f;
        struct {
          union {
            __IO uint16_t MAR2LL;
            struct {
              __IO uint8_t MAR2LLL;
              __IO uint8_t MAR2LLH;
            };
          };
          union {
            __IO uint16_t MAR2LH;
            struct {
              __IO uint8_t MAR2LHL;
              __IO uint8_t MAR2LHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR3H;
        stc_ethernet_mac_mar3h_field_t MAR3H_f;
        struct {
          union {
            __IO uint16_t MAR3HL;
            struct {
              __IO uint8_t MAR3HLL;
              __IO uint8_t MAR3HLH;
            };
          };
          union {
            __IO uint16_t MAR3HH;
            struct {
              __IO uint8_t MAR3HHL;
              __IO uint8_t MAR3HHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR3L;
        stc_ethernet_mac_mar3l_field_t MAR3L_f;
        struct {
          union {
            __IO uint16_t MAR3LL;
            struct {
              __IO uint8_t MAR3LLL;
              __IO uint8_t MAR3LLH;
            };
          };
          union {
            __IO uint16_t MAR3LH;
            struct {
              __IO uint8_t MAR3LHL;
              __IO uint8_t MAR3LHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR4H;
        stc_ethernet_mac_mar4h_field_t MAR4H_f;
        struct {
          union {
            __IO uint16_t MAR4HL;
            struct {
              __IO uint8_t MAR4HLL;
              __IO uint8_t MAR4HLH;
            };
          };
          union {
            __IO uint16_t MAR4HH;
            struct {
              __IO uint8_t MAR4HHL;
              __IO uint8_t MAR4HHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR4L;
        stc_ethernet_mac_mar4l_field_t MAR4L_f;
        struct {
          union {
            __IO uint16_t MAR4LL;
            struct {
              __IO uint8_t MAR4LLL;
              __IO uint8_t MAR4LLH;
            };
          };
          union {
            __IO uint16_t MAR4LH;
            struct {
              __IO uint8_t MAR4LHL;
              __IO uint8_t MAR4LHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR5H;
        stc_ethernet_mac_mar5h_field_t MAR5H_f;
        struct {
          union {
            __IO uint16_t MAR5HL;
            struct {
              __IO uint8_t MAR5HLL;
              __IO uint8_t MAR5HLH;
            };
          };
          union {
            __IO uint16_t MAR5HH;
            struct {
              __IO uint8_t MAR5HHL;
              __IO uint8_t MAR5HHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR5L;
        stc_ethernet_mac_mar5l_field_t MAR5L_f;
        struct {
          union {
            __IO uint16_t MAR5LL;
            struct {
              __IO uint8_t MAR5LLL;
              __IO uint8_t MAR5LLH;
            };
          };
          union {
            __IO uint16_t MAR5LH;
            struct {
              __IO uint8_t MAR5LHL;
              __IO uint8_t MAR5LHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR6H;
        stc_ethernet_mac_mar6h_field_t MAR6H_f;
        struct {
          union {
            __IO uint16_t MAR6HL;
            struct {
              __IO uint8_t MAR6HLL;
              __IO uint8_t MAR6HLH;
            };
          };
          union {
            __IO uint16_t MAR6HH;
            struct {
              __IO uint8_t MAR6HHL;
              __IO uint8_t MAR6HHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR6L;
        stc_ethernet_mac_mar6l_field_t MAR6L_f;
        struct {
          union {
            __IO uint16_t MAR6LL;
            struct {
              __IO uint8_t MAR6LLL;
              __IO uint8_t MAR6LLH;
            };
          };
          union {
            __IO uint16_t MAR6LH;
            struct {
              __IO uint8_t MAR6LHL;
              __IO uint8_t MAR6LHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR7H;
        stc_ethernet_mac_mar7h_field_t MAR7H_f;
        struct {
          union {
            __IO uint16_t MAR7HL;
            struct {
              __IO uint8_t MAR7HLL;
              __IO uint8_t MAR7HLH;
            };
          };
          union {
            __IO uint16_t MAR7HH;
            struct {
              __IO uint8_t MAR7HHL;
              __IO uint8_t MAR7HHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR7L;
        stc_ethernet_mac_mar7l_field_t MAR7L_f;
        struct {
          union {
            __IO uint16_t MAR7LL;
            struct {
              __IO uint8_t MAR7LLL;
              __IO uint8_t MAR7LLH;
            };
          };
          union {
            __IO uint16_t MAR7LH;
            struct {
              __IO uint8_t MAR7LHL;
              __IO uint8_t MAR7LHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR8H;
        stc_ethernet_mac_mar8h_field_t MAR8H_f;
        struct {
          union {
            __IO uint16_t MAR8HL;
            struct {
              __IO uint8_t MAR8HLL;
              __IO uint8_t MAR8HLH;
            };
          };
          union {
            __IO uint16_t MAR8HH;
            struct {
              __IO uint8_t MAR8HHL;
              __IO uint8_t MAR8HHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR8L;
        stc_ethernet_mac_mar8l_field_t MAR8L_f;
        struct {
          union {
            __IO uint16_t MAR8LL;
            struct {
              __IO uint8_t MAR8LLL;
              __IO uint8_t MAR8LLH;
            };
          };
          union {
            __IO uint16_t MAR8LH;
            struct {
              __IO uint8_t MAR8LHL;
              __IO uint8_t MAR8LHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR9H;
        stc_ethernet_mac_mar9h_field_t MAR9H_f;
        struct {
          union {
            __IO uint16_t MAR9HL;
            struct {
              __IO uint8_t MAR9HLL;
              __IO uint8_t MAR9HLH;
            };
          };
          union {
            __IO uint16_t MAR9HH;
            struct {
              __IO uint8_t MAR9HHL;
              __IO uint8_t MAR9HHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR9L;
        stc_ethernet_mac_mar9l_field_t MAR9L_f;
        struct {
          union {
            __IO uint16_t MAR9LL;
            struct {
              __IO uint8_t MAR9LLL;
              __IO uint8_t MAR9LLH;
            };
          };
          union {
            __IO uint16_t MAR9LH;
            struct {
              __IO uint8_t MAR9LHL;
              __IO uint8_t MAR9LHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR10H;
        stc_ethernet_mac_mar10h_field_t MAR10H_f;
        struct {
          union {
            __IO uint16_t MAR10HL;
            struct {
              __IO uint8_t MAR10HLL;
              __IO uint8_t MAR10HLH;
            };
          };
          union {
            __IO uint16_t MAR10HH;
            struct {
              __IO uint8_t MAR10HHL;
              __IO uint8_t MAR10HHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR10L;
        stc_ethernet_mac_mar10l_field_t MAR10L_f;
        struct {
          union {
            __IO uint16_t MAR10LL;
            struct {
              __IO uint8_t MAR10LLL;
              __IO uint8_t MAR10LLH;
            };
          };
          union {
            __IO uint16_t MAR10LH;
            struct {
              __IO uint8_t MAR10LHL;
              __IO uint8_t MAR10LHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR11H;
        stc_ethernet_mac_mar11h_field_t MAR11H_f;
        struct {
          union {
            __IO uint16_t MAR11HL;
            struct {
              __IO uint8_t MAR11HLL;
              __IO uint8_t MAR11HLH;
            };
          };
          union {
            __IO uint16_t MAR11HH;
            struct {
              __IO uint8_t MAR11HHL;
              __IO uint8_t MAR11HHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR11L;
        stc_ethernet_mac_mar11l_field_t MAR11L_f;
        struct {
          union {
            __IO uint16_t MAR11LL;
            struct {
              __IO uint8_t MAR11LLL;
              __IO uint8_t MAR11LLH;
            };
          };
          union {
            __IO uint16_t MAR11LH;
            struct {
              __IO uint8_t MAR11LHL;
              __IO uint8_t MAR11LHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR12H;
        stc_ethernet_mac_mar12h_field_t MAR12H_f;
        struct {
          union {
            __IO uint16_t MAR12HL;
            struct {
              __IO uint8_t MAR12HLL;
              __IO uint8_t MAR12HLH;
            };
          };
          union {
            __IO uint16_t MAR12HH;
            struct {
              __IO uint8_t MAR12HHL;
              __IO uint8_t MAR12HHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR12L;
        stc_ethernet_mac_mar12l_field_t MAR12L_f;
        struct {
          union {
            __IO uint16_t MAR12LL;
            struct {
              __IO uint8_t MAR12LLL;
              __IO uint8_t MAR12LLH;
            };
          };
          union {
            __IO uint16_t MAR12LH;
            struct {
              __IO uint8_t MAR12LHL;
              __IO uint8_t MAR12LHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR13H;
        stc_ethernet_mac_mar13h_field_t MAR13H_f;
        struct {
          union {
            __IO uint16_t MAR13HL;
            struct {
              __IO uint8_t MAR13HLL;
              __IO uint8_t MAR13HLH;
            };
          };
          union {
            __IO uint16_t MAR13HH;
            struct {
              __IO uint8_t MAR13HHL;
              __IO uint8_t MAR13HHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR13L;
        stc_ethernet_mac_mar13l_field_t MAR13L_f;
        struct {
          union {
            __IO uint16_t MAR13LL;
            struct {
              __IO uint8_t MAR13LLL;
              __IO uint8_t MAR13LLH;
            };
          };
          union {
            __IO uint16_t MAR13LH;
            struct {
              __IO uint8_t MAR13LHL;
              __IO uint8_t MAR13LHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR14H;
        stc_ethernet_mac_mar14h_field_t MAR14H_f;
        struct {
          union {
            __IO uint16_t MAR14HL;
            struct {
              __IO uint8_t MAR14HLL;
              __IO uint8_t MAR14HLH;
            };
          };
          union {
            __IO uint16_t MAR14HH;
            struct {
              __IO uint8_t MAR14HHL;
              __IO uint8_t MAR14HHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR14L;
        stc_ethernet_mac_mar14l_field_t MAR14L_f;
        struct {
          union {
            __IO uint16_t MAR14LL;
            struct {
              __IO uint8_t MAR14LLL;
              __IO uint8_t MAR14LLH;
            };
          };
          union {
            __IO uint16_t MAR14LH;
            struct {
              __IO uint8_t MAR14LHL;
              __IO uint8_t MAR14LHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR15H;
        stc_ethernet_mac_mar15h_field_t MAR15H_f;
        struct {
          union {
            __IO uint16_t MAR15HL;
            struct {
              __IO uint8_t MAR15HLL;
              __IO uint8_t MAR15HLH;
            };
          };
          union {
            __IO uint16_t MAR15HH;
            struct {
              __IO uint8_t MAR15HHL;
              __IO uint8_t MAR15HHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR15L;
        stc_ethernet_mac_mar15l_field_t MAR15L_f;
        struct {
          union {
            __IO uint16_t MAR15LL;
            struct {
              __IO uint8_t MAR15LLL;
              __IO uint8_t MAR15LLH;
            };
          };
          union {
            __IO uint16_t MAR15LH;
            struct {
              __IO uint8_t MAR15LHL;
              __IO uint8_t MAR15LHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED1[24];
    union {
        __IO uint32_t RGSR;
        stc_ethernet_mac_rgsr_field_t RGSR_f;
        struct {
          union {
            __IO uint16_t RGSRL;
            struct {
              __IO uint8_t RGSRLL;
              __IO uint8_t RGSRLH;
            };
          };
          union {
            __IO uint16_t RGSRH;
            struct {
              __IO uint8_t RGSRHL;
              __IO uint8_t RGSRHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED2[36];
    union {
        __IO uint32_t MMC_CNTL;
        stc_ethernet_mac_mmc_cntl_field_t MMC_CNTL_f;
        struct {
          union {
            __IO uint16_t MMC_CNTLL;
            struct {
              __IO uint8_t MMC_CNTLLL;
              __IO uint8_t MMC_CNTLLH;
            };
          };
          union {
            __IO uint16_t MMC_CNTLH;
            struct {
              __IO uint8_t MMC_CNTLHL;
              __IO uint8_t MMC_CNTLHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MMC_INTR_RX;
        stc_ethernet_mac_mmc_intr_rx_field_t MMC_INTR_RX_f;
        struct {
          union {
            __IO uint16_t MMC_INTR_RXL;
            struct {
              __IO uint8_t MMC_INTR_RXLL;
              __IO uint8_t MMC_INTR_RXLH;
            };
          };
          union {
            __IO uint16_t MMC_INTR_RXH;
            struct {
              __IO uint8_t MMC_INTR_RXHL;
              __IO uint8_t MMC_INTR_RXHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MMC_INTR_TX;
        stc_ethernet_mac_mmc_intr_tx_field_t MMC_INTR_TX_f;
        struct {
          union {
            __IO uint16_t MMC_INTR_TXL;
            struct {
              __IO uint8_t MMC_INTR_TXLL;
              __IO uint8_t MMC_INTR_TXLH;
            };
          };
          union {
            __IO uint16_t MMC_INTR_TXH;
            struct {
              __IO uint8_t MMC_INTR_TXHL;
              __IO uint8_t MMC_INTR_TXHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MMC_INTR_MASK_RX;
        stc_ethernet_mac_mmc_intr_mask_rx_field_t MMC_INTR_MASK_RX_f;
        struct {
          union {
            __IO uint16_t MMC_INTR_MASK_RXL;
            struct {
              __IO uint8_t MMC_INTR_MASK_RXLL;
              __IO uint8_t MMC_INTR_MASK_RXLH;
            };
          };
          union {
            __IO uint16_t MMC_INTR_MASK_RXH;
            struct {
              __IO uint8_t MMC_INTR_MASK_RXHL;
              __IO uint8_t MMC_INTR_MASK_RXHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MMC_INTR_MASK_TX;
        stc_ethernet_mac_mmc_intr_mask_tx_field_t MMC_INTR_MASK_TX_f;
        struct {
          union {
            __IO uint16_t MMC_INTR_MASK_TXL;
            struct {
              __IO uint8_t MMC_INTR_MASK_TXLL;
              __IO uint8_t MMC_INTR_MASK_TXLH;
            };
          };
          union {
            __IO uint16_t MMC_INTR_MASK_TXH;
            struct {
              __IO uint8_t MMC_INTR_MASK_TXHL;
              __IO uint8_t MMC_INTR_MASK_TXHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXOCTETCOUNT_GB;
        struct {
          union {
            __IO uint16_t TXOCTETCOUNT_GBL;
            struct {
              __IO uint8_t TXOCTETCOUNT_GBLL;
              __IO uint8_t TXOCTETCOUNT_GBLH;
            };
          };
          union {
            __IO uint16_t TXOCTETCOUNT_GBH;
            struct {
              __IO uint8_t TXOCTETCOUNT_GBHL;
              __IO uint8_t TXOCTETCOUNT_GBHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXFRAMECOUNT_GB;
        struct {
          union {
            __IO uint16_t TXFRAMECOUNT_GBL;
            struct {
              __IO uint8_t TXFRAMECOUNT_GBLL;
              __IO uint8_t TXFRAMECOUNT_GBLH;
            };
          };
          union {
            __IO uint16_t TXFRAMECOUNT_GBH;
            struct {
              __IO uint8_t TXFRAMECOUNT_GBHL;
              __IO uint8_t TXFRAMECOUNT_GBHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXBROADCASTFRAMES_G;
        struct {
          union {
            __IO uint16_t TXBROADCASTFRAMES_GL;
            struct {
              __IO uint8_t TXBROADCASTFRAMES_GLL;
              __IO uint8_t TXBROADCASTFRAMES_GLH;
            };
          };
          union {
            __IO uint16_t TXBROADCASTFRAMES_GH;
            struct {
              __IO uint8_t TXBROADCASTFRAMES_GHL;
              __IO uint8_t TXBROADCASTFRAMES_GHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXMULTICASTFRAMES_G;
        struct {
          union {
            __IO uint16_t TXMULTICASTFRAMES_GL;
            struct {
              __IO uint8_t TXMULTICASTFRAMES_GLL;
              __IO uint8_t TXMULTICASTFRAMES_GLH;
            };
          };
          union {
            __IO uint16_t TXMULTICASTFRAMES_GH;
            struct {
              __IO uint8_t TXMULTICASTFRAMES_GHL;
              __IO uint8_t TXMULTICASTFRAMES_GHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TX64OCTETS_GB;
        struct {
          union {
            __IO uint16_t TX64OCTETS_GBL;
            struct {
              __IO uint8_t TX64OCTETS_GBLL;
              __IO uint8_t TX64OCTETS_GBLH;
            };
          };
          union {
            __IO uint16_t TX64OCTETS_GBH;
            struct {
              __IO uint8_t TX64OCTETS_GBHL;
              __IO uint8_t TX64OCTETS_GBHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TX65TO127OCTETS_GB;
        struct {
          union {
            __IO uint16_t TX65TO127OCTETS_GBL;
            struct {
              __IO uint8_t TX65TO127OCTETS_GBLL;
              __IO uint8_t TX65TO127OCTETS_GBLH;
            };
          };
          union {
            __IO uint16_t TX65TO127OCTETS_GBH;
            struct {
              __IO uint8_t TX65TO127OCTETS_GBHL;
              __IO uint8_t TX65TO127OCTETS_GBHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TX128TO255OCTETS_GB;
        struct {
          union {
            __IO uint16_t TX128TO255OCTETS_GBL;
            struct {
              __IO uint8_t TX128TO255OCTETS_GBLL;
              __IO uint8_t TX128TO255OCTETS_GBLH;
            };
          };
          union {
            __IO uint16_t TX128TO255OCTETS_GBH;
            struct {
              __IO uint8_t TX128TO255OCTETS_GBHL;
              __IO uint8_t TX128TO255OCTETS_GBHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TX256TO511OCTETS_GB;
        struct {
          union {
            __IO uint16_t TX256TO511OCTETS_GBL;
            struct {
              __IO uint8_t TX256TO511OCTETS_GBLL;
              __IO uint8_t TX256TO511OCTETS_GBLH;
            };
          };
          union {
            __IO uint16_t TX256TO511OCTETS_GBH;
            struct {
              __IO uint8_t TX256TO511OCTETS_GBHL;
              __IO uint8_t TX256TO511OCTETS_GBHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TX512TO1023OCTETS_GB;
        struct {
          union {
            __IO uint16_t TX512TO1023OCTETS_GBL;
            struct {
              __IO uint8_t TX512TO1023OCTETS_GBLL;
              __IO uint8_t TX512TO1023OCTETS_GBLH;
            };
          };
          union {
            __IO uint16_t TX512TO1023OCTETS_GBH;
            struct {
              __IO uint8_t TX512TO1023OCTETS_GBHL;
              __IO uint8_t TX512TO1023OCTETS_GBHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TX1024TOMAXOCTETS_GB;
        struct {
          union {
            __IO uint16_t TX1024TOMAXOCTETS_GBL;
            struct {
              __IO uint8_t TX1024TOMAXOCTETS_GBLL;
              __IO uint8_t TX1024TOMAXOCTETS_GBLH;
            };
          };
          union {
            __IO uint16_t TX1024TOMAXOCTETS_GBH;
            struct {
              __IO uint8_t TX1024TOMAXOCTETS_GBHL;
              __IO uint8_t TX1024TOMAXOCTETS_GBHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXUNICASTFRAMES_GB;
        struct {
          union {
            __IO uint16_t TXUNICASTFRAMES_GBL;
            struct {
              __IO uint8_t TXUNICASTFRAMES_GBLL;
              __IO uint8_t TXUNICASTFRAMES_GBLH;
            };
          };
          union {
            __IO uint16_t TXUNICASTFRAMES_GBH;
            struct {
              __IO uint8_t TXUNICASTFRAMES_GBHL;
              __IO uint8_t TXUNICASTFRAMES_GBHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXMULTICASTFRAMES_GB;
        struct {
          union {
            __IO uint16_t TXMULTICASTFRAMES_GBL;
            struct {
              __IO uint8_t TXMULTICASTFRAMES_GBLL;
              __IO uint8_t TXMULTICASTFRAMES_GBLH;
            };
          };
          union {
            __IO uint16_t TXMULTICASTFRAMES_GBH;
            struct {
              __IO uint8_t TXMULTICASTFRAMES_GBHL;
              __IO uint8_t TXMULTICASTFRAMES_GBHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXBROADCASTFRAMES_GB;
        struct {
          union {
            __IO uint16_t TXBROADCASTFRAMES_GBL;
            struct {
              __IO uint8_t TXBROADCASTFRAMES_GBLL;
              __IO uint8_t TXBROADCASTFRAMES_GBLH;
            };
          };
          union {
            __IO uint16_t TXBROADCASTFRAMES_GBH;
            struct {
              __IO uint8_t TXBROADCASTFRAMES_GBHL;
              __IO uint8_t TXBROADCASTFRAMES_GBHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXUNDERFLOWERROR;
        struct {
          union {
            __IO uint16_t TXUNDERFLOWERRORL;
            struct {
              __IO uint8_t TXUNDERFLOWERRORLL;
              __IO uint8_t TXUNDERFLOWERRORLH;
            };
          };
          union {
            __IO uint16_t TXUNDERFLOWERRORH;
            struct {
              __IO uint8_t TXUNDERFLOWERRORHL;
              __IO uint8_t TXUNDERFLOWERRORHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXSINGLECOL_G;
        struct {
          union {
            __IO uint16_t TXSINGLECOL_GL;
            struct {
              __IO uint8_t TXSINGLECOL_GLL;
              __IO uint8_t TXSINGLECOL_GLH;
            };
          };
          union {
            __IO uint16_t TXSINGLECOL_GH;
            struct {
              __IO uint8_t TXSINGLECOL_GHL;
              __IO uint8_t TXSINGLECOL_GHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXMULTICOL_G;
        struct {
          union {
            __IO uint16_t TXMULTICOL_GL;
            struct {
              __IO uint8_t TXMULTICOL_GLL;
              __IO uint8_t TXMULTICOL_GLH;
            };
          };
          union {
            __IO uint16_t TXMULTICOL_GH;
            struct {
              __IO uint8_t TXMULTICOL_GHL;
              __IO uint8_t TXMULTICOL_GHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXDEFERRED;
        struct {
          union {
            __IO uint16_t TXDEFERREDL;
            struct {
              __IO uint8_t TXDEFERREDLL;
              __IO uint8_t TXDEFERREDLH;
            };
          };
          union {
            __IO uint16_t TXDEFERREDH;
            struct {
              __IO uint8_t TXDEFERREDHL;
              __IO uint8_t TXDEFERREDHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXLATECOL;
        struct {
          union {
            __IO uint16_t TXLATECOLL;
            struct {
              __IO uint8_t TXLATECOLLL;
              __IO uint8_t TXLATECOLLH;
            };
          };
          union {
            __IO uint16_t TXLATECOLH;
            struct {
              __IO uint8_t TXLATECOLHL;
              __IO uint8_t TXLATECOLHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXEXESSCOL;
        struct {
          union {
            __IO uint16_t TXEXESSCOLL;
            struct {
              __IO uint8_t TXEXESSCOLLL;
              __IO uint8_t TXEXESSCOLLH;
            };
          };
          union {
            __IO uint16_t TXEXESSCOLH;
            struct {
              __IO uint8_t TXEXESSCOLHL;
              __IO uint8_t TXEXESSCOLHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXCARRIERERROR;
        struct {
          union {
            __IO uint16_t TXCARRIERERRORL;
            struct {
              __IO uint8_t TXCARRIERERRORLL;
              __IO uint8_t TXCARRIERERRORLH;
            };
          };
          union {
            __IO uint16_t TXCARRIERERRORH;
            struct {
              __IO uint8_t TXCARRIERERRORHL;
              __IO uint8_t TXCARRIERERRORHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXOCTETCOUNT_G;
        struct {
          union {
            __IO uint16_t TXOCTETCOUNT_GL;
            struct {
              __IO uint8_t TXOCTETCOUNT_GLL;
              __IO uint8_t TXOCTETCOUNT_GLH;
            };
          };
          union {
            __IO uint16_t TXOCTETCOUNT_GH;
            struct {
              __IO uint8_t TXOCTETCOUNT_GHL;
              __IO uint8_t TXOCTETCOUNT_GHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXFRAMECOUNT_G;
        struct {
          union {
            __IO uint16_t TXFRAMECOUNT_GL;
            struct {
              __IO uint8_t TXFRAMECOUNT_GLL;
              __IO uint8_t TXFRAMECOUNT_GLH;
            };
          };
          union {
            __IO uint16_t TXFRAMECOUNT_GH;
            struct {
              __IO uint8_t TXFRAMECOUNT_GHL;
              __IO uint8_t TXFRAMECOUNT_GHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXEXECESSDEF_G;
        struct {
          union {
            __IO uint16_t TXEXECESSDEF_GL;
            struct {
              __IO uint8_t TXEXECESSDEF_GLL;
              __IO uint8_t TXEXECESSDEF_GLH;
            };
          };
          union {
            __IO uint16_t TXEXECESSDEF_GH;
            struct {
              __IO uint8_t TXEXECESSDEF_GHL;
              __IO uint8_t TXEXECESSDEF_GHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXPAUSEFRAMES;
        struct {
          union {
            __IO uint16_t TXPAUSEFRAMESL;
            struct {
              __IO uint8_t TXPAUSEFRAMESLL;
              __IO uint8_t TXPAUSEFRAMESLH;
            };
          };
          union {
            __IO uint16_t TXPAUSEFRAMESH;
            struct {
              __IO uint8_t TXPAUSEFRAMESHL;
              __IO uint8_t TXPAUSEFRAMESHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXVLANFRAMES_G;
        struct {
          union {
            __IO uint16_t TXVLANFRAMES_GL;
            struct {
              __IO uint8_t TXVLANFRAMES_GLL;
              __IO uint8_t TXVLANFRAMES_GLH;
            };
          };
          union {
            __IO uint16_t TXVLANFRAMES_GH;
            struct {
              __IO uint8_t TXVLANFRAMES_GHL;
              __IO uint8_t TXVLANFRAMES_GHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED3[8];
    union {
        __IO uint32_t RXFRAMECOUNT_GB;
        struct {
          union {
            __IO uint16_t RXFRAMECOUNT_GBL;
            struct {
              __IO uint8_t RXFRAMECOUNT_GBLL;
              __IO uint8_t RXFRAMECOUNT_GBLH;
            };
          };
          union {
            __IO uint16_t RXFRAMECOUNT_GBH;
            struct {
              __IO uint8_t RXFRAMECOUNT_GBHL;
              __IO uint8_t RXFRAMECOUNT_GBHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXOCTETCOUNT_GB;
        struct {
          union {
            __IO uint16_t RXOCTETCOUNT_GBL;
            struct {
              __IO uint8_t RXOCTETCOUNT_GBLL;
              __IO uint8_t RXOCTETCOUNT_GBLH;
            };
          };
          union {
            __IO uint16_t RXOCTETCOUNT_GBH;
            struct {
              __IO uint8_t RXOCTETCOUNT_GBHL;
              __IO uint8_t RXOCTETCOUNT_GBHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXOCTETCOUNT_G;
        struct {
          union {
            __IO uint16_t RXOCTETCOUNT_GL;
            struct {
              __IO uint8_t RXOCTETCOUNT_GLL;
              __IO uint8_t RXOCTETCOUNT_GLH;
            };
          };
          union {
            __IO uint16_t RXOCTETCOUNT_GH;
            struct {
              __IO uint8_t RXOCTETCOUNT_GHL;
              __IO uint8_t RXOCTETCOUNT_GHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXBROADCASTFRAMES_G;
        struct {
          union {
            __IO uint16_t RXBROADCASTFRAMES_GL;
            struct {
              __IO uint8_t RXBROADCASTFRAMES_GLL;
              __IO uint8_t RXBROADCASTFRAMES_GLH;
            };
          };
          union {
            __IO uint16_t RXBROADCASTFRAMES_GH;
            struct {
              __IO uint8_t RXBROADCASTFRAMES_GHL;
              __IO uint8_t RXBROADCASTFRAMES_GHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXMULTICASTFRAMES_G;
        struct {
          union {
            __IO uint16_t RXMULTICASTFRAMES_GL;
            struct {
              __IO uint8_t RXMULTICASTFRAMES_GLL;
              __IO uint8_t RXMULTICASTFRAMES_GLH;
            };
          };
          union {
            __IO uint16_t RXMULTICASTFRAMES_GH;
            struct {
              __IO uint8_t RXMULTICASTFRAMES_GHL;
              __IO uint8_t RXMULTICASTFRAMES_GHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXCRCERROR;
        struct {
          union {
            __IO uint16_t RXCRCERRORL;
            struct {
              __IO uint8_t RXCRCERRORLL;
              __IO uint8_t RXCRCERRORLH;
            };
          };
          union {
            __IO uint16_t RXCRCERRORH;
            struct {
              __IO uint8_t RXCRCERRORHL;
              __IO uint8_t RXCRCERRORHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXALLIGNMENTERROR;
        struct {
          union {
            __IO uint16_t RXALLIGNMENTERRORL;
            struct {
              __IO uint8_t RXALLIGNMENTERRORLL;
              __IO uint8_t RXALLIGNMENTERRORLH;
            };
          };
          union {
            __IO uint16_t RXALLIGNMENTERRORH;
            struct {
              __IO uint8_t RXALLIGNMENTERRORHL;
              __IO uint8_t RXALLIGNMENTERRORHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXRUNTERROR;
        struct {
          union {
            __IO uint16_t RXRUNTERRORL;
            struct {
              __IO uint8_t RXRUNTERRORLL;
              __IO uint8_t RXRUNTERRORLH;
            };
          };
          union {
            __IO uint16_t RXRUNTERRORH;
            struct {
              __IO uint8_t RXRUNTERRORHL;
              __IO uint8_t RXRUNTERRORHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXJABBERERROR;
        struct {
          union {
            __IO uint16_t RXJABBERERRORL;
            struct {
              __IO uint8_t RXJABBERERRORLL;
              __IO uint8_t RXJABBERERRORLH;
            };
          };
          union {
            __IO uint16_t RXJABBERERRORH;
            struct {
              __IO uint8_t RXJABBERERRORHL;
              __IO uint8_t RXJABBERERRORHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXUNDERSIZE_G;
        struct {
          union {
            __IO uint16_t RXUNDERSIZE_GL;
            struct {
              __IO uint8_t RXUNDERSIZE_GLL;
              __IO uint8_t RXUNDERSIZE_GLH;
            };
          };
          union {
            __IO uint16_t RXUNDERSIZE_GH;
            struct {
              __IO uint8_t RXUNDERSIZE_GHL;
              __IO uint8_t RXUNDERSIZE_GHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXOVERSIZE_G;
        struct {
          union {
            __IO uint16_t RXOVERSIZE_GL;
            struct {
              __IO uint8_t RXOVERSIZE_GLL;
              __IO uint8_t RXOVERSIZE_GLH;
            };
          };
          union {
            __IO uint16_t RXOVERSIZE_GH;
            struct {
              __IO uint8_t RXOVERSIZE_GHL;
              __IO uint8_t RXOVERSIZE_GHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RX64OCTETS_GB;
        struct {
          union {
            __IO uint16_t RX64OCTETS_GBL;
            struct {
              __IO uint8_t RX64OCTETS_GBLL;
              __IO uint8_t RX64OCTETS_GBLH;
            };
          };
          union {
            __IO uint16_t RX64OCTETS_GBH;
            struct {
              __IO uint8_t RX64OCTETS_GBHL;
              __IO uint8_t RX64OCTETS_GBHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RX65TO127OCTETS_GB;
        struct {
          union {
            __IO uint16_t RX65TO127OCTETS_GBL;
            struct {
              __IO uint8_t RX65TO127OCTETS_GBLL;
              __IO uint8_t RX65TO127OCTETS_GBLH;
            };
          };
          union {
            __IO uint16_t RX65TO127OCTETS_GBH;
            struct {
              __IO uint8_t RX65TO127OCTETS_GBHL;
              __IO uint8_t RX65TO127OCTETS_GBHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RX128TO255OCTETS_GB;
        struct {
          union {
            __IO uint16_t RX128TO255OCTETS_GBL;
            struct {
              __IO uint8_t RX128TO255OCTETS_GBLL;
              __IO uint8_t RX128TO255OCTETS_GBLH;
            };
          };
          union {
            __IO uint16_t RX128TO255OCTETS_GBH;
            struct {
              __IO uint8_t RX128TO255OCTETS_GBHL;
              __IO uint8_t RX128TO255OCTETS_GBHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RX256TO511OCTETS_GB;
        struct {
          union {
            __IO uint16_t RX256TO511OCTETS_GBL;
            struct {
              __IO uint8_t RX256TO511OCTETS_GBLL;
              __IO uint8_t RX256TO511OCTETS_GBLH;
            };
          };
          union {
            __IO uint16_t RX256TO511OCTETS_GBH;
            struct {
              __IO uint8_t RX256TO511OCTETS_GBHL;
              __IO uint8_t RX256TO511OCTETS_GBHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RX512TO1023OCTETS_GB;
        struct {
          union {
            __IO uint16_t RX512TO1023OCTETS_GBL;
            struct {
              __IO uint8_t RX512TO1023OCTETS_GBLL;
              __IO uint8_t RX512TO1023OCTETS_GBLH;
            };
          };
          union {
            __IO uint16_t RX512TO1023OCTETS_GBH;
            struct {
              __IO uint8_t RX512TO1023OCTETS_GBHL;
              __IO uint8_t RX512TO1023OCTETS_GBHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RX1024TOMAXOCTETS_GB;
        struct {
          union {
            __IO uint16_t RX1024TOMAXOCTETS_GBL;
            struct {
              __IO uint8_t RX1024TOMAXOCTETS_GBLL;
              __IO uint8_t RX1024TOMAXOCTETS_GBLH;
            };
          };
          union {
            __IO uint16_t RX1024TOMAXOCTETS_GBH;
            struct {
              __IO uint8_t RX1024TOMAXOCTETS_GBHL;
              __IO uint8_t RX1024TOMAXOCTETS_GBHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXUNICASTFRAMES_G;
        struct {
          union {
            __IO uint16_t RXUNICASTFRAMES_GL;
            struct {
              __IO uint8_t RXUNICASTFRAMES_GLL;
              __IO uint8_t RXUNICASTFRAMES_GLH;
            };
          };
          union {
            __IO uint16_t RXUNICASTFRAMES_GH;
            struct {
              __IO uint8_t RXUNICASTFRAMES_GHL;
              __IO uint8_t RXUNICASTFRAMES_GHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXLENGTHERROR;
        struct {
          union {
            __IO uint16_t RXLENGTHERRORL;
            struct {
              __IO uint8_t RXLENGTHERRORLL;
              __IO uint8_t RXLENGTHERRORLH;
            };
          };
          union {
            __IO uint16_t RXLENGTHERRORH;
            struct {
              __IO uint8_t RXLENGTHERRORHL;
              __IO uint8_t RXLENGTHERRORHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXOUTOFRANGETYPE;
        struct {
          union {
            __IO uint16_t RXOUTOFRANGETYPEL;
            struct {
              __IO uint8_t RXOUTOFRANGETYPELL;
              __IO uint8_t RXOUTOFRANGETYPELH;
            };
          };
          union {
            __IO uint16_t RXOUTOFRANGETYPEH;
            struct {
              __IO uint8_t RXOUTOFRANGETYPEHL;
              __IO uint8_t RXOUTOFRANGETYPEHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXPAUSEFRAMES;
        struct {
          union {
            __IO uint16_t RXPAUSEFRAMESL;
            struct {
              __IO uint8_t RXPAUSEFRAMESLL;
              __IO uint8_t RXPAUSEFRAMESLH;
            };
          };
          union {
            __IO uint16_t RXPAUSEFRAMESH;
            struct {
              __IO uint8_t RXPAUSEFRAMESHL;
              __IO uint8_t RXPAUSEFRAMESHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXFIFOOVERFLOW;
        struct {
          union {
            __IO uint16_t RXFIFOOVERFLOWL;
            struct {
              __IO uint8_t RXFIFOOVERFLOWLL;
              __IO uint8_t RXFIFOOVERFLOWLH;
            };
          };
          union {
            __IO uint16_t RXFIFOOVERFLOWH;
            struct {
              __IO uint8_t RXFIFOOVERFLOWHL;
              __IO uint8_t RXFIFOOVERFLOWHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXVLANFRAMES_GB;
        struct {
          union {
            __IO uint16_t RXVLANFRAMES_GBL;
            struct {
              __IO uint8_t RXVLANFRAMES_GBLL;
              __IO uint8_t RXVLANFRAMES_GBLH;
            };
          };
          union {
            __IO uint16_t RXVLANFRAMES_GBH;
            struct {
              __IO uint8_t RXVLANFRAMES_GBHL;
              __IO uint8_t RXVLANFRAMES_GBHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXWATCHDOGERROR;
        struct {
          union {
            __IO uint16_t RXWATCHDOGERRORL;
            struct {
              __IO uint8_t RXWATCHDOGERRORLL;
              __IO uint8_t RXWATCHDOGERRORLH;
            };
          };
          union {
            __IO uint16_t RXWATCHDOGERRORH;
            struct {
              __IO uint8_t RXWATCHDOGERRORHL;
              __IO uint8_t RXWATCHDOGERRORHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED4[32];
    union {
        __IO uint32_t MMC_IPC_INTR_MASK_RX;
        stc_ethernet_mac_mmc_ipc_intr_mask_rx_field_t MMC_IPC_INTR_MASK_RX_f;
        struct {
          union {
            __IO uint16_t MMC_IPC_INTR_MASK_RXL;
            struct {
              __IO uint8_t MMC_IPC_INTR_MASK_RXLL;
              __IO uint8_t MMC_IPC_INTR_MASK_RXLH;
            };
          };
          union {
            __IO uint16_t MMC_IPC_INTR_MASK_RXH;
            struct {
              __IO uint8_t MMC_IPC_INTR_MASK_RXHL;
              __IO uint8_t MMC_IPC_INTR_MASK_RXHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED5[4];
    union {
        __IO uint32_t MMC_IPC_INTR_RX;
        stc_ethernet_mac_mmc_ipc_intr_rx_field_t MMC_IPC_INTR_RX_f;
        struct {
          union {
            __IO uint16_t MMC_IPC_INTR_RXL;
            struct {
              __IO uint8_t MMC_IPC_INTR_RXLL;
              __IO uint8_t MMC_IPC_INTR_RXLH;
            };
          };
          union {
            __IO uint16_t MMC_IPC_INTR_RXH;
            struct {
              __IO uint8_t MMC_IPC_INTR_RXHL;
              __IO uint8_t MMC_IPC_INTR_RXHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED6[4];
    union {
        __IO uint32_t RXIPV4_GD_FRMS;
        struct {
          union {
            __IO uint16_t RXIPV4_GD_FRMSL;
            struct {
              __IO uint8_t RXIPV4_GD_FRMSLL;
              __IO uint8_t RXIPV4_GD_FRMSLH;
            };
          };
          union {
            __IO uint16_t RXIPV4_GD_FRMSH;
            struct {
              __IO uint8_t RXIPV4_GD_FRMSHL;
              __IO uint8_t RXIPV4_GD_FRMSHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXIPV4_HDRERR_FRMS;
        struct {
          union {
            __IO uint16_t RXIPV4_HDRERR_FRMSL;
            struct {
              __IO uint8_t RXIPV4_HDRERR_FRMSLL;
              __IO uint8_t RXIPV4_HDRERR_FRMSLH;
            };
          };
          union {
            __IO uint16_t RXIPV4_HDRERR_FRMSH;
            struct {
              __IO uint8_t RXIPV4_HDRERR_FRMSHL;
              __IO uint8_t RXIPV4_HDRERR_FRMSHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXIPV4_NOPAY_FRMS;
        struct {
          union {
            __IO uint16_t RXIPV4_NOPAY_FRMSL;
            struct {
              __IO uint8_t RXIPV4_NOPAY_FRMSLL;
              __IO uint8_t RXIPV4_NOPAY_FRMSLH;
            };
          };
          union {
            __IO uint16_t RXIPV4_NOPAY_FRMSH;
            struct {
              __IO uint8_t RXIPV4_NOPAY_FRMSHL;
              __IO uint8_t RXIPV4_NOPAY_FRMSHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXIPV4_FRAG_FRMS;
        struct {
          union {
            __IO uint16_t RXIPV4_FRAG_FRMSL;
            struct {
              __IO uint8_t RXIPV4_FRAG_FRMSLL;
              __IO uint8_t RXIPV4_FRAG_FRMSLH;
            };
          };
          union {
            __IO uint16_t RXIPV4_FRAG_FRMSH;
            struct {
              __IO uint8_t RXIPV4_FRAG_FRMSHL;
              __IO uint8_t RXIPV4_FRAG_FRMSHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXIPV4_UDSBL_FRMS;
        struct {
          union {
            __IO uint16_t RXIPV4_UDSBL_FRMSL;
            struct {
              __IO uint8_t RXIPV4_UDSBL_FRMSLL;
              __IO uint8_t RXIPV4_UDSBL_FRMSLH;
            };
          };
          union {
            __IO uint16_t RXIPV4_UDSBL_FRMSH;
            struct {
              __IO uint8_t RXIPV4_UDSBL_FRMSHL;
              __IO uint8_t RXIPV4_UDSBL_FRMSHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXIPV6_GD_FRMS;
        struct {
          union {
            __IO uint16_t RXIPV6_GD_FRMSL;
            struct {
              __IO uint8_t RXIPV6_GD_FRMSLL;
              __IO uint8_t RXIPV6_GD_FRMSLH;
            };
          };
          union {
            __IO uint16_t RXIPV6_GD_FRMSH;
            struct {
              __IO uint8_t RXIPV6_GD_FRMSHL;
              __IO uint8_t RXIPV6_GD_FRMSHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXIPV6_HDRERR_FRMS;
        struct {
          union {
            __IO uint16_t RXIPV6_HDRERR_FRMSL;
            struct {
              __IO uint8_t RXIPV6_HDRERR_FRMSLL;
              __IO uint8_t RXIPV6_HDRERR_FRMSLH;
            };
          };
          union {
            __IO uint16_t RXIPV6_HDRERR_FRMSH;
            struct {
              __IO uint8_t RXIPV6_HDRERR_FRMSHL;
              __IO uint8_t RXIPV6_HDRERR_FRMSHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXIPV6_NOPAY_FRMS;
        struct {
          union {
            __IO uint16_t RXIPV6_NOPAY_FRMSL;
            struct {
              __IO uint8_t RXIPV6_NOPAY_FRMSLL;
              __IO uint8_t RXIPV6_NOPAY_FRMSLH;
            };
          };
          union {
            __IO uint16_t RXIPV6_NOPAY_FRMSH;
            struct {
              __IO uint8_t RXIPV6_NOPAY_FRMSHL;
              __IO uint8_t RXIPV6_NOPAY_FRMSHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXUDP_GD_FRMS;
        struct {
          union {
            __IO uint16_t RXUDP_GD_FRMSL;
            struct {
              __IO uint8_t RXUDP_GD_FRMSLL;
              __IO uint8_t RXUDP_GD_FRMSLH;
            };
          };
          union {
            __IO uint16_t RXUDP_GD_FRMSH;
            struct {
              __IO uint8_t RXUDP_GD_FRMSHL;
              __IO uint8_t RXUDP_GD_FRMSHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXUDP_ERR_FRMS;
        struct {
          union {
            __IO uint16_t RXUDP_ERR_FRMSL;
            struct {
              __IO uint8_t RXUDP_ERR_FRMSLL;
              __IO uint8_t RXUDP_ERR_FRMSLH;
            };
          };
          union {
            __IO uint16_t RXUDP_ERR_FRMSH;
            struct {
              __IO uint8_t RXUDP_ERR_FRMSHL;
              __IO uint8_t RXUDP_ERR_FRMSHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXTCP_GD_FRMS;
        struct {
          union {
            __IO uint16_t RXTCP_GD_FRMSL;
            struct {
              __IO uint8_t RXTCP_GD_FRMSLL;
              __IO uint8_t RXTCP_GD_FRMSLH;
            };
          };
          union {
            __IO uint16_t RXTCP_GD_FRMSH;
            struct {
              __IO uint8_t RXTCP_GD_FRMSHL;
              __IO uint8_t RXTCP_GD_FRMSHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXTCP_ERR_FRMS;
        struct {
          union {
            __IO uint16_t RXTCP_ERR_FRMSL;
            struct {
              __IO uint8_t RXTCP_ERR_FRMSLL;
              __IO uint8_t RXTCP_ERR_FRMSLH;
            };
          };
          union {
            __IO uint16_t RXTCP_ERR_FRMSH;
            struct {
              __IO uint8_t RXTCP_ERR_FRMSHL;
              __IO uint8_t RXTCP_ERR_FRMSHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXICMP_GD_FRMS;
        struct {
          union {
            __IO uint16_t RXICMP_GD_FRMSL;
            struct {
              __IO uint8_t RXICMP_GD_FRMSLL;
              __IO uint8_t RXICMP_GD_FRMSLH;
            };
          };
          union {
            __IO uint16_t RXICMP_GD_FRMSH;
            struct {
              __IO uint8_t RXICMP_GD_FRMSHL;
              __IO uint8_t RXICMP_GD_FRMSHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXICMP_ERR_FRMS;
        struct {
          union {
            __IO uint16_t RXICMP_ERR_FRMSL;
            struct {
              __IO uint8_t RXICMP_ERR_FRMSLL;
              __IO uint8_t RXICMP_ERR_FRMSLH;
            };
          };
          union {
            __IO uint16_t RXICMP_ERR_FRMSH;
            struct {
              __IO uint8_t RXICMP_ERR_FRMSHL;
              __IO uint8_t RXICMP_ERR_FRMSHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED7[8];
    union {
        __IO uint32_t RXIPV4_GD_OCTETS;
        struct {
          union {
            __IO uint16_t RXIPV4_GD_OCTETSL;
            struct {
              __IO uint8_t RXIPV4_GD_OCTETSLL;
              __IO uint8_t RXIPV4_GD_OCTETSLH;
            };
          };
          union {
            __IO uint16_t RXIPV4_GD_OCTETSH;
            struct {
              __IO uint8_t RXIPV4_GD_OCTETSHL;
              __IO uint8_t RXIPV4_GD_OCTETSHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXIPV4_HDRERR_OCTETS;
        struct {
          union {
            __IO uint16_t RXIPV4_HDRERR_OCTETSL;
            struct {
              __IO uint8_t RXIPV4_HDRERR_OCTETSLL;
              __IO uint8_t RXIPV4_HDRERR_OCTETSLH;
            };
          };
          union {
            __IO uint16_t RXIPV4_HDRERR_OCTETSH;
            struct {
              __IO uint8_t RXIPV4_HDRERR_OCTETSHL;
              __IO uint8_t RXIPV4_HDRERR_OCTETSHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXIPV4_NOPAY_OCTETS;
        struct {
          union {
            __IO uint16_t RXIPV4_NOPAY_OCTETSL;
            struct {
              __IO uint8_t RXIPV4_NOPAY_OCTETSLL;
              __IO uint8_t RXIPV4_NOPAY_OCTETSLH;
            };
          };
          union {
            __IO uint16_t RXIPV4_NOPAY_OCTETSH;
            struct {
              __IO uint8_t RXIPV4_NOPAY_OCTETSHL;
              __IO uint8_t RXIPV4_NOPAY_OCTETSHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXIPV4_FRAG_OCTETS;
        struct {
          union {
            __IO uint16_t RXIPV4_FRAG_OCTETSL;
            struct {
              __IO uint8_t RXIPV4_FRAG_OCTETSLL;
              __IO uint8_t RXIPV4_FRAG_OCTETSLH;
            };
          };
          union {
            __IO uint16_t RXIPV4_FRAG_OCTETSH;
            struct {
              __IO uint8_t RXIPV4_FRAG_OCTETSHL;
              __IO uint8_t RXIPV4_FRAG_OCTETSHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXIPV4_UDSBL_OCTETS;
        struct {
          union {
            __IO uint16_t RXIPV4_UDSBL_OCTETSL;
            struct {
              __IO uint8_t RXIPV4_UDSBL_OCTETSLL;
              __IO uint8_t RXIPV4_UDSBL_OCTETSLH;
            };
          };
          union {
            __IO uint16_t RXIPV4_UDSBL_OCTETSH;
            struct {
              __IO uint8_t RXIPV4_UDSBL_OCTETSHL;
              __IO uint8_t RXIPV4_UDSBL_OCTETSHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXIPV6_GD_OCTETS;
        struct {
          union {
            __IO uint16_t RXIPV6_GD_OCTETSL;
            struct {
              __IO uint8_t RXIPV6_GD_OCTETSLL;
              __IO uint8_t RXIPV6_GD_OCTETSLH;
            };
          };
          union {
            __IO uint16_t RXIPV6_GD_OCTETSH;
            struct {
              __IO uint8_t RXIPV6_GD_OCTETSHL;
              __IO uint8_t RXIPV6_GD_OCTETSHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXIPV6_HDRERR_OCTETS;
        struct {
          union {
            __IO uint16_t RXIPV6_HDRERR_OCTETSL;
            struct {
              __IO uint8_t RXIPV6_HDRERR_OCTETSLL;
              __IO uint8_t RXIPV6_HDRERR_OCTETSLH;
            };
          };
          union {
            __IO uint16_t RXIPV6_HDRERR_OCTETSH;
            struct {
              __IO uint8_t RXIPV6_HDRERR_OCTETSHL;
              __IO uint8_t RXIPV6_HDRERR_OCTETSHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXIPV6_NOPAY_OCTETS;
        struct {
          union {
            __IO uint16_t RXIPV6_NOPAY_OCTETSL;
            struct {
              __IO uint8_t RXIPV6_NOPAY_OCTETSLL;
              __IO uint8_t RXIPV6_NOPAY_OCTETSLH;
            };
          };
          union {
            __IO uint16_t RXIPV6_NOPAY_OCTETSH;
            struct {
              __IO uint8_t RXIPV6_NOPAY_OCTETSHL;
              __IO uint8_t RXIPV6_NOPAY_OCTETSHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXUDP_GD_OCTETS;
        struct {
          union {
            __IO uint16_t RXUDP_GD_OCTETSL;
            struct {
              __IO uint8_t RXUDP_GD_OCTETSLL;
              __IO uint8_t RXUDP_GD_OCTETSLH;
            };
          };
          union {
            __IO uint16_t RXUDP_GD_OCTETSH;
            struct {
              __IO uint8_t RXUDP_GD_OCTETSHL;
              __IO uint8_t RXUDP_GD_OCTETSHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXUDP_ERR_OCTETS;
        struct {
          union {
            __IO uint16_t RXUDP_ERR_OCTETSL;
            struct {
              __IO uint8_t RXUDP_ERR_OCTETSLL;
              __IO uint8_t RXUDP_ERR_OCTETSLH;
            };
          };
          union {
            __IO uint16_t RXUDP_ERR_OCTETSH;
            struct {
              __IO uint8_t RXUDP_ERR_OCTETSHL;
              __IO uint8_t RXUDP_ERR_OCTETSHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXTCP_GD_OCTETS;
        struct {
          union {
            __IO uint16_t RXTCP_GD_OCTETSL;
            struct {
              __IO uint8_t RXTCP_GD_OCTETSLL;
              __IO uint8_t RXTCP_GD_OCTETSLH;
            };
          };
          union {
            __IO uint16_t RXTCP_GD_OCTETSH;
            struct {
              __IO uint8_t RXTCP_GD_OCTETSHL;
              __IO uint8_t RXTCP_GD_OCTETSHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXTCP_ERR_OCTETS;
        struct {
          union {
            __IO uint16_t RXTCP_ERR_OCTETSL;
            struct {
              __IO uint8_t RXTCP_ERR_OCTETSLL;
              __IO uint8_t RXTCP_ERR_OCTETSLH;
            };
          };
          union {
            __IO uint16_t RXTCP_ERR_OCTETSH;
            struct {
              __IO uint8_t RXTCP_ERR_OCTETSHL;
              __IO uint8_t RXTCP_ERR_OCTETSHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXICMP_GD_OCTETS;
        struct {
          union {
            __IO uint16_t RXICMP_GD_OCTETSL;
            struct {
              __IO uint8_t RXICMP_GD_OCTETSLL;
              __IO uint8_t RXICMP_GD_OCTETSLH;
            };
          };
          union {
            __IO uint16_t RXICMP_GD_OCTETSH;
            struct {
              __IO uint8_t RXICMP_GD_OCTETSHL;
              __IO uint8_t RXICMP_GD_OCTETSHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXICMP_ERR_OCTETS;
        struct {
          union {
            __IO uint16_t RXICMP_ERR_OCTETSL;
            struct {
              __IO uint8_t RXICMP_ERR_OCTETSLL;
              __IO uint8_t RXICMP_ERR_OCTETSLH;
            };
          };
          union {
            __IO uint16_t RXICMP_ERR_OCTETSH;
            struct {
              __IO uint8_t RXICMP_ERR_OCTETSHL;
              __IO uint8_t RXICMP_ERR_OCTETSHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED8[1144];
    union {
        __IO uint32_t TSCR;
        stc_ethernet_mac_tscr_field_t TSCR_f;
        struct {
          union {
            __IO uint16_t TSCRL;
            struct {
              __IO uint8_t TSCRLL;
              __IO uint8_t TSCRLH;
            };
          };
          union {
            __IO uint16_t TSCRH;
            struct {
              __IO uint8_t TSCRHL;
              __IO uint8_t TSCRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t SSIR;
        stc_ethernet_mac_ssir_field_t SSIR_f;
        struct {
          union {
            __IO uint16_t SSIRL;
            struct {
              __IO uint8_t SSIRLL;
              __IO uint8_t SSIRLH;
            };
          };
          union {
            __IO uint16_t SSIRH;
            struct {
              __IO uint8_t SSIRHL;
              __IO uint8_t SSIRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t STSR;
        stc_ethernet_mac_stsr_field_t STSR_f;
        struct {
          union {
            __IO uint16_t STSRL;
            struct {
              __IO uint8_t STSRLL;
              __IO uint8_t STSRLH;
            };
          };
          union {
            __IO uint16_t STSRH;
            struct {
              __IO uint8_t STSRHL;
              __IO uint8_t STSRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t STNR;
        stc_ethernet_mac_stnr_field_t STNR_f;
        struct {
          union {
            __IO uint16_t STNRL;
            struct {
              __IO uint8_t STNRLL;
              __IO uint8_t STNRLH;
            };
          };
          union {
            __IO uint16_t STNRH;
            struct {
              __IO uint8_t STNRHL;
              __IO uint8_t STNRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t STSUR;
        stc_ethernet_mac_stsur_field_t STSUR_f;
        struct {
          union {
            __IO uint16_t STSURL;
            struct {
              __IO uint8_t STSURLL;
              __IO uint8_t STSURLH;
            };
          };
          union {
            __IO uint16_t STSURH;
            struct {
              __IO uint8_t STSURHL;
              __IO uint8_t STSURHH;
            };
          };
        };
    };
    union {
        __IO uint32_t STNUR;
        stc_ethernet_mac_stnur_field_t STNUR_f;
        struct {
          union {
            __IO uint16_t STNURL;
            struct {
              __IO uint8_t STNURLL;
              __IO uint8_t STNURLH;
            };
          };
          union {
            __IO uint16_t STNURH;
            struct {
              __IO uint8_t STNURHL;
              __IO uint8_t STNURHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TSAR;
        stc_ethernet_mac_tsar_field_t TSAR_f;
        struct {
          union {
            __IO uint16_t TSARL;
            struct {
              __IO uint8_t TSARLL;
              __IO uint8_t TSARLH;
            };
          };
          union {
            __IO uint16_t TSARH;
            struct {
              __IO uint8_t TSARHL;
              __IO uint8_t TSARHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TTSR;
        stc_ethernet_mac_ttsr_field_t TTSR_f;
        struct {
          union {
            __IO uint16_t TTSRL;
            struct {
              __IO uint8_t TTSRLL;
              __IO uint8_t TTSRLH;
            };
          };
          union {
            __IO uint16_t TTSRH;
            struct {
              __IO uint8_t TTSRHL;
              __IO uint8_t TTSRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TTNR;
        stc_ethernet_mac_ttnr_field_t TTNR_f;
        struct {
          union {
            __IO uint16_t TTNRL;
            struct {
              __IO uint8_t TTNRLL;
              __IO uint8_t TTNRLH;
            };
          };
          union {
            __IO uint16_t TTNRH;
            struct {
              __IO uint8_t TTNRHL;
              __IO uint8_t TTNRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t STHWSR;
        stc_ethernet_mac_sthwsr_field_t STHWSR_f;
        struct {
          union {
            __IO uint16_t STHWSRL;
            struct {
              __IO uint8_t STHWSRLL;
              __IO uint8_t STHWSRLH;
            };
          };
          union {
            __IO uint16_t STHWSRH;
            struct {
              __IO uint8_t STHWSRHL;
              __IO uint8_t STHWSRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TSR;
        stc_ethernet_mac_tsr_field_t TSR_f;
        struct {
          union {
            __IO uint16_t TSRL;
            struct {
              __IO uint8_t TSRLL;
              __IO uint8_t TSRLH;
            };
          };
          union {
            __IO uint16_t TSRH;
            struct {
              __IO uint8_t TSRHL;
              __IO uint8_t TSRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PPSCR;
        stc_ethernet_mac_ppscr_field_t PPSCR_f;
        struct {
          union {
            __IO uint16_t PPSCRL;
            struct {
              __IO uint8_t PPSCRLL;
              __IO uint8_t PPSCRLH;
            };
          };
          union {
            __IO uint16_t PPSCRH;
            struct {
              __IO uint8_t PPSCRHL;
              __IO uint8_t PPSCRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t ATNR;
        stc_ethernet_mac_atnr_field_t ATNR_f;
        struct {
          union {
            __IO uint16_t ATNRL;
            struct {
              __IO uint8_t ATNRLL;
              __IO uint8_t ATNRLH;
            };
          };
          union {
            __IO uint16_t ATNRH;
            struct {
              __IO uint8_t ATNRHL;
              __IO uint8_t ATNRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t ATSR;
        stc_ethernet_mac_atsr_field_t ATSR_f;
        struct {
          union {
            __IO uint16_t ATSRL;
            struct {
              __IO uint8_t ATSRLL;
              __IO uint8_t ATSRLH;
            };
          };
          union {
            __IO uint16_t ATSRH;
            struct {
              __IO uint8_t ATSRHL;
              __IO uint8_t ATSRHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED9[200];
    union {
        __IO uint32_t MAR16H;
        stc_ethernet_mac_mar16h_field_t MAR16H_f;
        struct {
          union {
            __IO uint16_t MAR16HL;
            struct {
              __IO uint8_t MAR16HLL;
              __IO uint8_t MAR16HLH;
            };
          };
          union {
            __IO uint16_t MAR16HH;
            struct {
              __IO uint8_t MAR16HHL;
              __IO uint8_t MAR16HHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR16L;
        stc_ethernet_mac_mar16l_field_t MAR16L_f;
        struct {
          union {
            __IO uint16_t MAR16LL;
            struct {
              __IO uint8_t MAR16LLL;
              __IO uint8_t MAR16LLH;
            };
          };
          union {
            __IO uint16_t MAR16LH;
            struct {
              __IO uint8_t MAR16LHL;
              __IO uint8_t MAR16LHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR17H;
        stc_ethernet_mac_mar17h_field_t MAR17H_f;
        struct {
          union {
            __IO uint16_t MAR17HL;
            struct {
              __IO uint8_t MAR17HLL;
              __IO uint8_t MAR17HLH;
            };
          };
          union {
            __IO uint16_t MAR17HH;
            struct {
              __IO uint8_t MAR17HHL;
              __IO uint8_t MAR17HHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR17L;
        stc_ethernet_mac_mar17l_field_t MAR17L_f;
        struct {
          union {
            __IO uint16_t MAR17LL;
            struct {
              __IO uint8_t MAR17LLL;
              __IO uint8_t MAR17LLH;
            };
          };
          union {
            __IO uint16_t MAR17LH;
            struct {
              __IO uint8_t MAR17LHL;
              __IO uint8_t MAR17LHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR18H;
        stc_ethernet_mac_mar18h_field_t MAR18H_f;
        struct {
          union {
            __IO uint16_t MAR18HL;
            struct {
              __IO uint8_t MAR18HLL;
              __IO uint8_t MAR18HLH;
            };
          };
          union {
            __IO uint16_t MAR18HH;
            struct {
              __IO uint8_t MAR18HHL;
              __IO uint8_t MAR18HHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR18L;
        stc_ethernet_mac_mar18l_field_t MAR18L_f;
        struct {
          union {
            __IO uint16_t MAR18LL;
            struct {
              __IO uint8_t MAR18LLL;
              __IO uint8_t MAR18LLH;
            };
          };
          union {
            __IO uint16_t MAR18LH;
            struct {
              __IO uint8_t MAR18LHL;
              __IO uint8_t MAR18LHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR19H;
        stc_ethernet_mac_mar19h_field_t MAR19H_f;
        struct {
          union {
            __IO uint16_t MAR19HL;
            struct {
              __IO uint8_t MAR19HLL;
              __IO uint8_t MAR19HLH;
            };
          };
          union {
            __IO uint16_t MAR19HH;
            struct {
              __IO uint8_t MAR19HHL;
              __IO uint8_t MAR19HHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR19L;
        stc_ethernet_mac_mar19l_field_t MAR19L_f;
        struct {
          union {
            __IO uint16_t MAR19LL;
            struct {
              __IO uint8_t MAR19LLL;
              __IO uint8_t MAR19LLH;
            };
          };
          union {
            __IO uint16_t MAR19LH;
            struct {
              __IO uint8_t MAR19LHL;
              __IO uint8_t MAR19LHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR20H;
        stc_ethernet_mac_mar20h_field_t MAR20H_f;
        struct {
          union {
            __IO uint16_t MAR20HL;
            struct {
              __IO uint8_t MAR20HLL;
              __IO uint8_t MAR20HLH;
            };
          };
          union {
            __IO uint16_t MAR20HH;
            struct {
              __IO uint8_t MAR20HHL;
              __IO uint8_t MAR20HHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR20L;
        stc_ethernet_mac_mar20l_field_t MAR20L_f;
        struct {
          union {
            __IO uint16_t MAR20LL;
            struct {
              __IO uint8_t MAR20LLL;
              __IO uint8_t MAR20LLH;
            };
          };
          union {
            __IO uint16_t MAR20LH;
            struct {
              __IO uint8_t MAR20LHL;
              __IO uint8_t MAR20LHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR21H;
        stc_ethernet_mac_mar21h_field_t MAR21H_f;
        struct {
          union {
            __IO uint16_t MAR21HL;
            struct {
              __IO uint8_t MAR21HLL;
              __IO uint8_t MAR21HLH;
            };
          };
          union {
            __IO uint16_t MAR21HH;
            struct {
              __IO uint8_t MAR21HHL;
              __IO uint8_t MAR21HHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR21L;
        stc_ethernet_mac_mar21l_field_t MAR21L_f;
        struct {
          union {
            __IO uint16_t MAR21LL;
            struct {
              __IO uint8_t MAR21LLL;
              __IO uint8_t MAR21LLH;
            };
          };
          union {
            __IO uint16_t MAR21LH;
            struct {
              __IO uint8_t MAR21LHL;
              __IO uint8_t MAR21LHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR22H;
        stc_ethernet_mac_mar22h_field_t MAR22H_f;
        struct {
          union {
            __IO uint16_t MAR22HL;
            struct {
              __IO uint8_t MAR22HLL;
              __IO uint8_t MAR22HLH;
            };
          };
          union {
            __IO uint16_t MAR22HH;
            struct {
              __IO uint8_t MAR22HHL;
              __IO uint8_t MAR22HHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR22L;
        stc_ethernet_mac_mar22l_field_t MAR22L_f;
        struct {
          union {
            __IO uint16_t MAR22LL;
            struct {
              __IO uint8_t MAR22LLL;
              __IO uint8_t MAR22LLH;
            };
          };
          union {
            __IO uint16_t MAR22LH;
            struct {
              __IO uint8_t MAR22LHL;
              __IO uint8_t MAR22LHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR23H;
        stc_ethernet_mac_mar23h_field_t MAR23H_f;
        struct {
          union {
            __IO uint16_t MAR23HL;
            struct {
              __IO uint8_t MAR23HLL;
              __IO uint8_t MAR23HLH;
            };
          };
          union {
            __IO uint16_t MAR23HH;
            struct {
              __IO uint8_t MAR23HHL;
              __IO uint8_t MAR23HHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR23L;
        stc_ethernet_mac_mar23l_field_t MAR23L_f;
        struct {
          union {
            __IO uint16_t MAR23LL;
            struct {
              __IO uint8_t MAR23LLL;
              __IO uint8_t MAR23LLH;
            };
          };
          union {
            __IO uint16_t MAR23LH;
            struct {
              __IO uint8_t MAR23LHL;
              __IO uint8_t MAR23LHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR24H;
        stc_ethernet_mac_mar24h_field_t MAR24H_f;
        struct {
          union {
            __IO uint16_t MAR24HL;
            struct {
              __IO uint8_t MAR24HLL;
              __IO uint8_t MAR24HLH;
            };
          };
          union {
            __IO uint16_t MAR24HH;
            struct {
              __IO uint8_t MAR24HHL;
              __IO uint8_t MAR24HHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR24L;
        stc_ethernet_mac_mar24l_field_t MAR24L_f;
        struct {
          union {
            __IO uint16_t MAR24LL;
            struct {
              __IO uint8_t MAR24LLL;
              __IO uint8_t MAR24LLH;
            };
          };
          union {
            __IO uint16_t MAR24LH;
            struct {
              __IO uint8_t MAR24LHL;
              __IO uint8_t MAR24LHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR25H;
        stc_ethernet_mac_mar25h_field_t MAR25H_f;
        struct {
          union {
            __IO uint16_t MAR25HL;
            struct {
              __IO uint8_t MAR25HLL;
              __IO uint8_t MAR25HLH;
            };
          };
          union {
            __IO uint16_t MAR25HH;
            struct {
              __IO uint8_t MAR25HHL;
              __IO uint8_t MAR25HHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR25L;
        stc_ethernet_mac_mar25l_field_t MAR25L_f;
        struct {
          union {
            __IO uint16_t MAR25LL;
            struct {
              __IO uint8_t MAR25LLL;
              __IO uint8_t MAR25LLH;
            };
          };
          union {
            __IO uint16_t MAR25LH;
            struct {
              __IO uint8_t MAR25LHL;
              __IO uint8_t MAR25LHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR26H;
        stc_ethernet_mac_mar26h_field_t MAR26H_f;
        struct {
          union {
            __IO uint16_t MAR26HL;
            struct {
              __IO uint8_t MAR26HLL;
              __IO uint8_t MAR26HLH;
            };
          };
          union {
            __IO uint16_t MAR26HH;
            struct {
              __IO uint8_t MAR26HHL;
              __IO uint8_t MAR26HHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR26L;
        stc_ethernet_mac_mar26l_field_t MAR26L_f;
        struct {
          union {
            __IO uint16_t MAR26LL;
            struct {
              __IO uint8_t MAR26LLL;
              __IO uint8_t MAR26LLH;
            };
          };
          union {
            __IO uint16_t MAR26LH;
            struct {
              __IO uint8_t MAR26LHL;
              __IO uint8_t MAR26LHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR27H;
        stc_ethernet_mac_mar27h_field_t MAR27H_f;
        struct {
          union {
            __IO uint16_t MAR27HL;
            struct {
              __IO uint8_t MAR27HLL;
              __IO uint8_t MAR27HLH;
            };
          };
          union {
            __IO uint16_t MAR27HH;
            struct {
              __IO uint8_t MAR27HHL;
              __IO uint8_t MAR27HHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR27L;
        stc_ethernet_mac_mar27l_field_t MAR27L_f;
        struct {
          union {
            __IO uint16_t MAR27LL;
            struct {
              __IO uint8_t MAR27LLL;
              __IO uint8_t MAR27LLH;
            };
          };
          union {
            __IO uint16_t MAR27LH;
            struct {
              __IO uint8_t MAR27LHL;
              __IO uint8_t MAR27LHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR28H;
        stc_ethernet_mac_mar28h_field_t MAR28H_f;
        struct {
          union {
            __IO uint16_t MAR28HL;
            struct {
              __IO uint8_t MAR28HLL;
              __IO uint8_t MAR28HLH;
            };
          };
          union {
            __IO uint16_t MAR28HH;
            struct {
              __IO uint8_t MAR28HHL;
              __IO uint8_t MAR28HHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR28L;
        stc_ethernet_mac_mar28l_field_t MAR28L_f;
        struct {
          union {
            __IO uint16_t MAR28LL;
            struct {
              __IO uint8_t MAR28LLL;
              __IO uint8_t MAR28LLH;
            };
          };
          union {
            __IO uint16_t MAR28LH;
            struct {
              __IO uint8_t MAR28LHL;
              __IO uint8_t MAR28LHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR29H;
        stc_ethernet_mac_mar29h_field_t MAR29H_f;
        struct {
          union {
            __IO uint16_t MAR29HL;
            struct {
              __IO uint8_t MAR29HLL;
              __IO uint8_t MAR29HLH;
            };
          };
          union {
            __IO uint16_t MAR29HH;
            struct {
              __IO uint8_t MAR29HHL;
              __IO uint8_t MAR29HHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR29L;
        stc_ethernet_mac_mar29l_field_t MAR29L_f;
        struct {
          union {
            __IO uint16_t MAR29LL;
            struct {
              __IO uint8_t MAR29LLL;
              __IO uint8_t MAR29LLH;
            };
          };
          union {
            __IO uint16_t MAR29LH;
            struct {
              __IO uint8_t MAR29LHL;
              __IO uint8_t MAR29LHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR30H;
        stc_ethernet_mac_mar30h_field_t MAR30H_f;
        struct {
          union {
            __IO uint16_t MAR30HL;
            struct {
              __IO uint8_t MAR30HLL;
              __IO uint8_t MAR30HLH;
            };
          };
          union {
            __IO uint16_t MAR30HH;
            struct {
              __IO uint8_t MAR30HHL;
              __IO uint8_t MAR30HHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR30L;
        stc_ethernet_mac_mar30l_field_t MAR30L_f;
        struct {
          union {
            __IO uint16_t MAR30LL;
            struct {
              __IO uint8_t MAR30LLL;
              __IO uint8_t MAR30LLH;
            };
          };
          union {
            __IO uint16_t MAR30LH;
            struct {
              __IO uint8_t MAR30LHL;
              __IO uint8_t MAR30LHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR31H;
        stc_ethernet_mac_mar31h_field_t MAR31H_f;
        struct {
          union {
            __IO uint16_t MAR31HL;
            struct {
              __IO uint8_t MAR31HLL;
              __IO uint8_t MAR31HLH;
            };
          };
          union {
            __IO uint16_t MAR31HH;
            struct {
              __IO uint8_t MAR31HHL;
              __IO uint8_t MAR31HHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MAR31L;
        stc_ethernet_mac_mar31l_field_t MAR31L_f;
        struct {
          union {
            __IO uint16_t MAR31LL;
            struct {
              __IO uint8_t MAR31LLL;
              __IO uint8_t MAR31LLH;
            };
          };
          union {
            __IO uint16_t MAR31LH;
            struct {
              __IO uint8_t MAR31LHL;
              __IO uint8_t MAR31LHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED10[1920];
    union {
        __IO uint32_t BMR;
        stc_ethernet_mac_bmr_field_t BMR_f;
        struct {
          union {
            __IO uint16_t BMRL;
            struct {
              __IO uint8_t BMRLL;
              __IO uint8_t BMRLH;
            };
          };
          union {
            __IO uint16_t BMRH;
            struct {
              __IO uint8_t BMRHL;
              __IO uint8_t BMRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TPDR;
        stc_ethernet_mac_tpdr_field_t TPDR_f;
        struct {
          union {
            __IO uint16_t TPDRL;
            struct {
              __IO uint8_t TPDRLL;
              __IO uint8_t TPDRLH;
            };
          };
          union {
            __IO uint16_t TPDRH;
            struct {
              __IO uint8_t TPDRHL;
              __IO uint8_t TPDRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RPDR;
        stc_ethernet_mac_rpdr_field_t RPDR_f;
        struct {
          union {
            __IO uint16_t RPDRL;
            struct {
              __IO uint8_t RPDRLL;
              __IO uint8_t RPDRLH;
            };
          };
          union {
            __IO uint16_t RPDRH;
            struct {
              __IO uint8_t RPDRHL;
              __IO uint8_t RPDRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RDLAR;
        stc_ethernet_mac_rdlar_field_t RDLAR_f;
        struct {
          union {
            __IO uint16_t RDLARL;
            struct {
              __IO uint8_t RDLARLL;
              __IO uint8_t RDLARLH;
            };
          };
          union {
            __IO uint16_t RDLARH;
            struct {
              __IO uint8_t RDLARHL;
              __IO uint8_t RDLARHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TDLAR;
        stc_ethernet_mac_tdlar_field_t TDLAR_f;
        struct {
          union {
            __IO uint16_t TDLARL;
            struct {
              __IO uint8_t TDLARLL;
              __IO uint8_t TDLARLH;
            };
          };
          union {
            __IO uint16_t TDLARH;
            struct {
              __IO uint8_t TDLARHL;
              __IO uint8_t TDLARHH;
            };
          };
        };
    };
    union {
        __IO uint32_t SR;
        stc_ethernet_mac_sr_field_t SR_f;
        struct {
          union {
            __IO uint16_t SRL;
            struct {
              __IO uint8_t SRLL;
              __IO uint8_t SRLH;
            };
          };
          union {
            __IO uint16_t SRH;
            struct {
              __IO uint8_t SRHL;
              __IO uint8_t SRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t OMR;
        stc_ethernet_mac_omr_field_t OMR_f;
        struct {
          union {
            __IO uint16_t OMRL;
            struct {
              __IO uint8_t OMRLL;
              __IO uint8_t OMRLH;
            };
          };
          union {
            __IO uint16_t OMRH;
            struct {
              __IO uint8_t OMRHL;
              __IO uint8_t OMRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IER;
        stc_ethernet_mac_ier_field_t IER_f;
        struct {
          union {
            __IO uint16_t IERL;
            struct {
              __IO uint8_t IERLL;
              __IO uint8_t IERLH;
            };
          };
          union {
            __IO uint16_t IERH;
            struct {
              __IO uint8_t IERHL;
              __IO uint8_t IERHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MFBOCR;
        stc_ethernet_mac_mfbocr_field_t MFBOCR_f;
        struct {
          union {
            __IO uint16_t MFBOCRL;
            struct {
              __IO uint8_t MFBOCRLL;
              __IO uint8_t MFBOCRLH;
            };
          };
          union {
            __IO uint16_t MFBOCRH;
            struct {
              __IO uint8_t MFBOCRHL;
              __IO uint8_t MFBOCRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RIWTR;
        stc_ethernet_mac_riwtr_field_t RIWTR_f;
        struct {
          union {
            __IO uint16_t RIWTRL;
            struct {
              __IO uint8_t RIWTRLL;
              __IO uint8_t RIWTRLH;
            };
          };
          union {
            __IO uint16_t RIWTRH;
            struct {
              __IO uint8_t RIWTRHL;
              __IO uint8_t RIWTRHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED11[4];
    union {
        __IO uint32_t AHBSR;
        stc_ethernet_mac_ahbsr_field_t AHBSR_f;
        struct {
          union {
            __IO uint16_t AHBSRL;
            struct {
              __IO uint8_t AHBSRLL;
              __IO uint8_t AHBSRLH;
            };
          };
          union {
            __IO uint16_t AHBSRH;
            struct {
              __IO uint8_t AHBSRHL;
              __IO uint8_t AHBSRHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED12[24];
    union {
        __IO uint32_t CHTDR;
        stc_ethernet_mac_chtdr_field_t CHTDR_f;
        struct {
          union {
            __IO uint16_t CHTDRL;
            struct {
              __IO uint8_t CHTDRLL;
              __IO uint8_t CHTDRLH;
            };
          };
          union {
            __IO uint16_t CHTDRH;
            struct {
              __IO uint8_t CHTDRHL;
              __IO uint8_t CHTDRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t CHRDR;
        stc_ethernet_mac_chrdr_field_t CHRDR_f;
        struct {
          union {
            __IO uint16_t CHRDRL;
            struct {
              __IO uint8_t CHRDRLL;
              __IO uint8_t CHRDRLH;
            };
          };
          union {
            __IO uint16_t CHRDRH;
            struct {
              __IO uint8_t CHRDRHL;
              __IO uint8_t CHRDRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t CHTBAR;
        stc_ethernet_mac_chtbar_field_t CHTBAR_f;
        struct {
          union {
            __IO uint16_t CHTBARL;
            struct {
              __IO uint8_t CHTBARLL;
              __IO uint8_t CHTBARLH;
            };
          };
          union {
            __IO uint16_t CHTBARH;
            struct {
              __IO uint8_t CHTBARHL;
              __IO uint8_t CHTBARHH;
            };
          };
        };
    };
    union {
        __IO uint32_t CHRBAR;
        stc_ethernet_mac_chrbar_field_t CHRBAR_f;
        struct {
          union {
            __IO uint16_t CHRBARL;
            struct {
              __IO uint8_t CHRBARLL;
              __IO uint8_t CHRBARLH;
            };
          };
          union {
            __IO uint16_t CHRBARH;
            struct {
              __IO uint8_t CHRBARHL;
              __IO uint8_t CHRBARHH;
            };
          };
        };
    };
} FM_ETHERNET_MAC_TypeDef, FM4_ETHERNET_MAC_TypeDef;

/*******************************************************************************
* EXBUS_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO uint32_t MODE0;
        stc_exbus_mode0_field_t MODE0_f;
        struct {
          union {
            __IO uint16_t MODE0L;
            struct {
              __IO uint8_t MODE0LL;
              __IO uint8_t MODE0LH;
            };
          };
          union {
            __IO uint16_t MODE0H;
            struct {
              __IO uint8_t MODE0HL;
              __IO uint8_t MODE0HH;
            };
          };
        };
    };
    union {
        __IO uint32_t MODE1;
        stc_exbus_mode1_field_t MODE1_f;
        struct {
          union {
            __IO uint16_t MODE1L;
            struct {
              __IO uint8_t MODE1LL;
              __IO uint8_t MODE1LH;
            };
          };
          union {
            __IO uint16_t MODE1H;
            struct {
              __IO uint8_t MODE1HL;
              __IO uint8_t MODE1HH;
            };
          };
        };
    };
    union {
        __IO uint32_t MODE2;
        stc_exbus_mode2_field_t MODE2_f;
        struct {
          union {
            __IO uint16_t MODE2L;
            struct {
              __IO uint8_t MODE2LL;
              __IO uint8_t MODE2LH;
            };
          };
          union {
            __IO uint16_t MODE2H;
            struct {
              __IO uint8_t MODE2HL;
              __IO uint8_t MODE2HH;
            };
          };
        };
    };
    union {
        __IO uint32_t MODE3;
        stc_exbus_mode3_field_t MODE3_f;
        struct {
          union {
            __IO uint16_t MODE3L;
            struct {
              __IO uint8_t MODE3LL;
              __IO uint8_t MODE3LH;
            };
          };
          union {
            __IO uint16_t MODE3H;
            struct {
              __IO uint8_t MODE3HL;
              __IO uint8_t MODE3HH;
            };
          };
        };
    };
    union {
        __IO uint32_t MODE4;
        stc_exbus_mode4_field_t MODE4_f;
        struct {
          union {
            __IO uint16_t MODE4L;
            struct {
              __IO uint8_t MODE4LL;
              __IO uint8_t MODE4LH;
            };
          };
          union {
            __IO uint16_t MODE4H;
            struct {
              __IO uint8_t MODE4HL;
              __IO uint8_t MODE4HH;
            };
          };
        };
    };
    union {
        __IO uint32_t MODE5;
        stc_exbus_mode5_field_t MODE5_f;
        struct {
          union {
            __IO uint16_t MODE5L;
            struct {
              __IO uint8_t MODE5LL;
              __IO uint8_t MODE5LH;
            };
          };
          union {
            __IO uint16_t MODE5H;
            struct {
              __IO uint8_t MODE5HL;
              __IO uint8_t MODE5HH;
            };
          };
        };
    };
    union {
        __IO uint32_t MODE6;
        stc_exbus_mode6_field_t MODE6_f;
        struct {
          union {
            __IO uint16_t MODE6L;
            struct {
              __IO uint8_t MODE6LL;
              __IO uint8_t MODE6LH;
            };
          };
          union {
            __IO uint16_t MODE6H;
            struct {
              __IO uint8_t MODE6HL;
              __IO uint8_t MODE6HH;
            };
          };
        };
    };
    union {
        __IO uint32_t MODE7;
        stc_exbus_mode7_field_t MODE7_f;
        struct {
          union {
            __IO uint16_t MODE7L;
            struct {
              __IO uint8_t MODE7LL;
              __IO uint8_t MODE7LH;
            };
          };
          union {
            __IO uint16_t MODE7H;
            struct {
              __IO uint8_t MODE7HL;
              __IO uint8_t MODE7HH;
            };
          };
        };
    };
    union {
        __IO uint32_t TIM0;
        stc_exbus_tim0_field_t TIM0_f;
        struct {
          union {
            __IO uint16_t TIM0L;
            struct {
              __IO uint8_t TIM0LL;
              __IO uint8_t TIM0LH;
            };
          };
          union {
            __IO uint16_t TIM0H;
            struct {
              __IO uint8_t TIM0HL;
              __IO uint8_t TIM0HH;
            };
          };
        };
    };
    union {
        __IO uint32_t TIM1;
        stc_exbus_tim1_field_t TIM1_f;
        struct {
          union {
            __IO uint16_t TIM1L;
            struct {
              __IO uint8_t TIM1LL;
              __IO uint8_t TIM1LH;
            };
          };
          union {
            __IO uint16_t TIM1H;
            struct {
              __IO uint8_t TIM1HL;
              __IO uint8_t TIM1HH;
            };
          };
        };
    };
    union {
        __IO uint32_t TIM2;
        stc_exbus_tim2_field_t TIM2_f;
        struct {
          union {
            __IO uint16_t TIM2L;
            struct {
              __IO uint8_t TIM2LL;
              __IO uint8_t TIM2LH;
            };
          };
          union {
            __IO uint16_t TIM2H;
            struct {
              __IO uint8_t TIM2HL;
              __IO uint8_t TIM2HH;
            };
          };
        };
    };
    union {
        __IO uint32_t TIM3;
        stc_exbus_tim3_field_t TIM3_f;
        struct {
          union {
            __IO uint16_t TIM3L;
            struct {
              __IO uint8_t TIM3LL;
              __IO uint8_t TIM3LH;
            };
          };
          union {
            __IO uint16_t TIM3H;
            struct {
              __IO uint8_t TIM3HL;
              __IO uint8_t TIM3HH;
            };
          };
        };
    };
    union {
        __IO uint32_t TIM4;
        stc_exbus_tim4_field_t TIM4_f;
        struct {
          union {
            __IO uint16_t TIM4L;
            struct {
              __IO uint8_t TIM4LL;
              __IO uint8_t TIM4LH;
            };
          };
          union {
            __IO uint16_t TIM4H;
            struct {
              __IO uint8_t TIM4HL;
              __IO uint8_t TIM4HH;
            };
          };
        };
    };
    union {
        __IO uint32_t TIM5;
        stc_exbus_tim5_field_t TIM5_f;
        struct {
          union {
            __IO uint16_t TIM5L;
            struct {
              __IO uint8_t TIM5LL;
              __IO uint8_t TIM5LH;
            };
          };
          union {
            __IO uint16_t TIM5H;
            struct {
              __IO uint8_t TIM5HL;
              __IO uint8_t TIM5HH;
            };
          };
        };
    };
    union {
        __IO uint32_t TIM6;
        stc_exbus_tim6_field_t TIM6_f;
        struct {
          union {
            __IO uint16_t TIM6L;
            struct {
              __IO uint8_t TIM6LL;
              __IO uint8_t TIM6LH;
            };
          };
          union {
            __IO uint16_t TIM6H;
            struct {
              __IO uint8_t TIM6HL;
              __IO uint8_t TIM6HH;
            };
          };
        };
    };
    union {
        __IO uint32_t TIM7;
        stc_exbus_tim7_field_t TIM7_f;
        struct {
          union {
            __IO uint16_t TIM7L;
            struct {
              __IO uint8_t TIM7LL;
              __IO uint8_t TIM7LH;
            };
          };
          union {
            __IO uint16_t TIM7H;
            struct {
              __IO uint8_t TIM7HL;
              __IO uint8_t TIM7HH;
            };
          };
        };
    };
    union {
        __IO uint32_t AREA0;
        stc_exbus_area0_field_t AREA0_f;
        struct {
          union {
            __IO uint16_t AREA0L;
            struct {
              __IO uint8_t AREA0LL;
              __IO uint8_t AREA0LH;
            };
          };
          union {
            __IO uint16_t AREA0H;
            struct {
              __IO uint8_t AREA0HL;
              __IO uint8_t AREA0HH;
            };
          };
        };
    };
    union {
        __IO uint32_t AREA1;
        stc_exbus_area1_field_t AREA1_f;
        struct {
          union {
            __IO uint16_t AREA1L;
            struct {
              __IO uint8_t AREA1LL;
              __IO uint8_t AREA1LH;
            };
          };
          union {
            __IO uint16_t AREA1H;
            struct {
              __IO uint8_t AREA1HL;
              __IO uint8_t AREA1HH;
            };
          };
        };
    };
    union {
        __IO uint32_t AREA2;
        stc_exbus_area2_field_t AREA2_f;
        struct {
          union {
            __IO uint16_t AREA2L;
            struct {
              __IO uint8_t AREA2LL;
              __IO uint8_t AREA2LH;
            };
          };
          union {
            __IO uint16_t AREA2H;
            struct {
              __IO uint8_t AREA2HL;
              __IO uint8_t AREA2HH;
            };
          };
        };
    };
    union {
        __IO uint32_t AREA3;
        stc_exbus_area3_field_t AREA3_f;
        struct {
          union {
            __IO uint16_t AREA3L;
            struct {
              __IO uint8_t AREA3LL;
              __IO uint8_t AREA3LH;
            };
          };
          union {
            __IO uint16_t AREA3H;
            struct {
              __IO uint8_t AREA3HL;
              __IO uint8_t AREA3HH;
            };
          };
        };
    };
    union {
        __IO uint32_t AREA4;
        stc_exbus_area4_field_t AREA4_f;
        struct {
          union {
            __IO uint16_t AREA4L;
            struct {
              __IO uint8_t AREA4LL;
              __IO uint8_t AREA4LH;
            };
          };
          union {
            __IO uint16_t AREA4H;
            struct {
              __IO uint8_t AREA4HL;
              __IO uint8_t AREA4HH;
            };
          };
        };
    };
    union {
        __IO uint32_t AREA5;
        stc_exbus_area5_field_t AREA5_f;
        struct {
          union {
            __IO uint16_t AREA5L;
            struct {
              __IO uint8_t AREA5LL;
              __IO uint8_t AREA5LH;
            };
          };
          union {
            __IO uint16_t AREA5H;
            struct {
              __IO uint8_t AREA5HL;
              __IO uint8_t AREA5HH;
            };
          };
        };
    };
    union {
        __IO uint32_t AREA6;
        stc_exbus_area6_field_t AREA6_f;
        struct {
          union {
            __IO uint16_t AREA6L;
            struct {
              __IO uint8_t AREA6LL;
              __IO uint8_t AREA6LH;
            };
          };
          union {
            __IO uint16_t AREA6H;
            struct {
              __IO uint8_t AREA6HL;
              __IO uint8_t AREA6HH;
            };
          };
        };
    };
    union {
        __IO uint32_t AREA7;
        stc_exbus_area7_field_t AREA7_f;
        struct {
          union {
            __IO uint16_t AREA7L;
            struct {
              __IO uint8_t AREA7LL;
              __IO uint8_t AREA7LH;
            };
          };
          union {
            __IO uint16_t AREA7H;
            struct {
              __IO uint8_t AREA7HL;
              __IO uint8_t AREA7HH;
            };
          };
        };
    };
    union {
        __IO uint32_t ATIM0;
        stc_exbus_atim0_field_t ATIM0_f;
        struct {
          union {
            __IO uint16_t ATIM0L;
            struct {
              __IO uint8_t ATIM0LL;
              __IO uint8_t ATIM0LH;
            };
          };
          union {
            __IO uint16_t ATIM0H;
            struct {
              __IO uint8_t ATIM0HL;
              __IO uint8_t ATIM0HH;
            };
          };
        };
    };
    union {
        __IO uint32_t ATIM1;
        stc_exbus_atim1_field_t ATIM1_f;
        struct {
          union {
            __IO uint16_t ATIM1L;
            struct {
              __IO uint8_t ATIM1LL;
              __IO uint8_t ATIM1LH;
            };
          };
          union {
            __IO uint16_t ATIM1H;
            struct {
              __IO uint8_t ATIM1HL;
              __IO uint8_t ATIM1HH;
            };
          };
        };
    };
    union {
        __IO uint32_t ATIM2;
        stc_exbus_atim2_field_t ATIM2_f;
        struct {
          union {
            __IO uint16_t ATIM2L;
            struct {
              __IO uint8_t ATIM2LL;
              __IO uint8_t ATIM2LH;
            };
          };
          union {
            __IO uint16_t ATIM2H;
            struct {
              __IO uint8_t ATIM2HL;
              __IO uint8_t ATIM2HH;
            };
          };
        };
    };
    union {
        __IO uint32_t ATIM3;
        stc_exbus_atim3_field_t ATIM3_f;
        struct {
          union {
            __IO uint16_t ATIM3L;
            struct {
              __IO uint8_t ATIM3LL;
              __IO uint8_t ATIM3LH;
            };
          };
          union {
            __IO uint16_t ATIM3H;
            struct {
              __IO uint8_t ATIM3HL;
              __IO uint8_t ATIM3HH;
            };
          };
        };
    };
    union {
        __IO uint32_t ATIM4;
        stc_exbus_atim4_field_t ATIM4_f;
        struct {
          union {
            __IO uint16_t ATIM4L;
            struct {
              __IO uint8_t ATIM4LL;
              __IO uint8_t ATIM4LH;
            };
          };
          union {
            __IO uint16_t ATIM4H;
            struct {
              __IO uint8_t ATIM4HL;
              __IO uint8_t ATIM4HH;
            };
          };
        };
    };
    union {
        __IO uint32_t ATIM5;
        stc_exbus_atim5_field_t ATIM5_f;
        struct {
          union {
            __IO uint16_t ATIM5L;
            struct {
              __IO uint8_t ATIM5LL;
              __IO uint8_t ATIM5LH;
            };
          };
          union {
            __IO uint16_t ATIM5H;
            struct {
              __IO uint8_t ATIM5HL;
              __IO uint8_t ATIM5HH;
            };
          };
        };
    };
    union {
        __IO uint32_t ATIM6;
        stc_exbus_atim6_field_t ATIM6_f;
        struct {
          union {
            __IO uint16_t ATIM6L;
            struct {
              __IO uint8_t ATIM6LL;
              __IO uint8_t ATIM6LH;
            };
          };
          union {
            __IO uint16_t ATIM6H;
            struct {
              __IO uint8_t ATIM6HL;
              __IO uint8_t ATIM6HH;
            };
          };
        };
    };
    union {
        __IO uint32_t ATIM7;
        stc_exbus_atim7_field_t ATIM7_f;
        struct {
          union {
            __IO uint16_t ATIM7L;
            struct {
              __IO uint8_t ATIM7LL;
              __IO uint8_t ATIM7LH;
            };
          };
          union {
            __IO uint16_t ATIM7H;
            struct {
              __IO uint8_t ATIM7HL;
              __IO uint8_t ATIM7HH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED0[128];
    union {
        __IO uint32_t SDMODE;
        stc_exbus_sdmode_field_t SDMODE_f;
        struct {
          union {
            __IO uint16_t SDMODEL;
            struct {
              __IO uint8_t SDMODELL;
              __IO uint8_t SDMODELH;
            };
          };
          union {
            __IO uint16_t SDMODEH;
            struct {
              __IO uint8_t SDMODEHL;
              __IO uint8_t SDMODEHH;
            };
          };
        };
    };
    union {
        __IO uint32_t REFTIM;
        stc_exbus_reftim_field_t REFTIM_f;
        struct {
          union {
            __IO uint16_t REFTIML;
            struct {
              __IO uint8_t REFTIMLL;
              __IO uint8_t REFTIMLH;
            };
          };
          union {
            __IO uint16_t REFTIMH;
            struct {
              __IO uint8_t REFTIMHL;
              __IO uint8_t REFTIMHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PWRDWN;
        stc_exbus_pwrdwn_field_t PWRDWN_f;
        struct {
          union {
            __IO uint16_t PWRDWNL;
            struct {
              __IO uint8_t PWRDWNLL;
              __IO uint8_t PWRDWNLH;
            };
          };
          union {
            __IO uint16_t PWRDWNH;
            struct {
              __IO uint8_t PWRDWNHL;
              __IO uint8_t PWRDWNHH;
            };
          };
        };
    };
    union {
        __IO uint32_t SDTIM;
        stc_exbus_sdtim_field_t SDTIM_f;
        struct {
          union {
            __IO uint16_t SDTIML;
            struct {
              __IO uint8_t SDTIMLL;
              __IO uint8_t SDTIMLH;
            };
          };
          union {
            __IO uint16_t SDTIMH;
            struct {
              __IO uint8_t SDTIMHL;
              __IO uint8_t SDTIMHH;
            };
          };
        };
    };
    union {
        __IO uint32_t SDCMD;
        stc_exbus_sdcmd_field_t SDCMD_f;
        struct {
          union {
            __IO uint16_t SDCMDL;
            struct {
              __IO uint8_t SDCMDLL;
              __IO uint8_t SDCMDLH;
            };
          };
          union {
            __IO uint16_t SDCMDH;
            struct {
              __IO uint8_t SDCMDHL;
              __IO uint8_t SDCMDHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED1[236];
    union {
        __IO uint32_t MEMCERR;
        stc_exbus_memcerr_field_t MEMCERR_f;
        struct {
          union {
            __IO uint16_t MEMCERRL;
            struct {
              __IO uint8_t MEMCERRLL;
              __IO uint8_t MEMCERRLH;
            };
          };
          union {
            __IO uint16_t MEMCERRH;
            struct {
              __IO uint8_t MEMCERRHL;
              __IO uint8_t MEMCERRHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED2[252];
    union {
        __IO uint32_t DCLKR;
        stc_exbus_dclkr_field_t DCLKR_f;
        struct {
          union {
            __IO uint16_t DCLKRL;
            struct {
              __IO uint8_t DCLKRLL;
              __IO uint8_t DCLKRLH;
            };
          };
          union {
            __IO uint16_t DCLKRH;
            struct {
              __IO uint8_t DCLKRHL;
              __IO uint8_t DCLKRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t EST;
        stc_exbus_est_field_t EST_f;
        struct {
          union {
            __IO uint16_t ESTL;
            struct {
              __IO uint8_t ESTLL;
              __IO uint8_t ESTLH;
            };
          };
          union {
            __IO uint16_t ESTH;
            struct {
              __IO uint8_t ESTHL;
              __IO uint8_t ESTHH;
            };
          };
        };
    };
    union {
        __IO uint32_t WEAD;
        stc_exbus_wead_field_t WEAD_f;
        struct {
          union {
            __IO uint16_t WEADL;
            struct {
              __IO uint8_t WEADLL;
              __IO uint8_t WEADLH;
            };
          };
          union {
            __IO uint16_t WEADH;
            struct {
              __IO uint8_t WEADHL;
              __IO uint8_t WEADHH;
            };
          };
        };
    };
    union {
        __IO uint32_t ESCLR;
        stc_exbus_esclr_field_t ESCLR_f;
        struct {
          union {
            __IO uint16_t ESCLRL;
            struct {
              __IO uint8_t ESCLRLL;
              __IO uint8_t ESCLRLH;
            };
          };
          union {
            __IO uint16_t ESCLRH;
            struct {
              __IO uint8_t ESCLRHL;
              __IO uint8_t ESCLRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t AMODE;
        stc_exbus_amode_field_t AMODE_f;
        struct {
          union {
            __IO uint16_t AMODEL;
            struct {
              __IO uint8_t AMODELL;
              __IO uint8_t AMODELH;
            };
          };
          union {
            __IO uint16_t AMODEH;
            struct {
              __IO uint8_t AMODEHL;
              __IO uint8_t AMODEHH;
            };
          };
        };
    };
} FM_EXBUS_TypeDef, FM4_EXBUS_TypeDef;

/*******************************************************************************
* EXTI_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO uint32_t ENIR;
        stc_exti_enir_field_t ENIR_f;
        struct {
          union {
            __IO uint16_t ENIRL;
            struct {
              __IO uint8_t ENIRLL;
              __IO uint8_t ENIRLH;
            };
          };
          union {
            __IO uint16_t ENIRH;
            struct {
              __IO uint8_t ENIRHL;
              __IO uint8_t ENIRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t EIRR;
        stc_exti_eirr_field_t EIRR_f;
        struct {
          union {
            __IO uint16_t EIRRL;
            struct {
              __IO uint8_t EIRRLL;
              __IO uint8_t EIRRLH;
            };
          };
          union {
            __IO uint16_t EIRRH;
            struct {
              __IO uint8_t EIRRHL;
              __IO uint8_t EIRRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t EICL;
        stc_exti_eicl_field_t EICL_f;
        struct {
          union {
            __IO uint16_t EICLL;
            struct {
              __IO uint8_t EICLLL;
              __IO uint8_t EICLLH;
            };
          };
          union {
            __IO uint16_t EICLH;
            struct {
              __IO uint8_t EICLHL;
              __IO uint8_t EICLHH;
            };
          };
        };
    };
    union {
        __IO uint32_t ELVR;
        stc_exti_elvr_field_t ELVR_f;
        struct {
          union {
            __IO uint16_t ELVRL;
            struct {
              __IO uint8_t ELVRLL;
              __IO uint8_t ELVRLH;
            };
          };
          union {
            __IO uint16_t ELVRH;
            struct {
              __IO uint8_t ELVRHL;
              __IO uint8_t ELVRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t ELVR1;
        stc_exti_elvr1_field_t ELVR1_f;
        struct {
          union {
            __IO uint16_t ELVR1L;
            struct {
              __IO uint8_t ELVR1LL;
              __IO uint8_t ELVR1LH;
            };
          };
          union {
            __IO uint16_t ELVR1H;
            struct {
              __IO uint8_t ELVR1HL;
              __IO uint8_t ELVR1HH;
            };
          };
        };
    };
    union {
        __IO uint16_t NMIRR;
        stc_exti_nmirr_field_t NMIRR_f;
        struct {
            __IO  uint8_t NMIRRL;
            __IO  uint8_t NMIRRH;
        };
    };
        __IO  uint8_t RESERVED0[2];
    union {
        __IO uint16_t NMICL;
        stc_exti_nmicl_field_t NMICL_f;
        struct {
            __IO  uint8_t NMICLL;
            __IO  uint8_t NMICLH;
        };
    };
} FM_EXTI_TypeDef, FM4_EXTI_TypeDef;

/*******************************************************************************
* FLASH_IF_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO uint32_t FASZR;
        stc_flash_if_faszr_field_t FASZR_f;
        struct {
          union {
            __IO uint16_t FASZRL;
            struct {
              __IO uint8_t FASZRLL;
              __IO uint8_t FASZRLH;
            };
          };
          union {
            __IO uint16_t FASZRH;
            struct {
              __IO uint8_t FASZRHL;
              __IO uint8_t FASZRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t FRWTR;
        stc_flash_if_frwtr_field_t FRWTR_f;
        struct {
          union {
            __IO uint16_t FRWTRL;
            struct {
              __IO uint8_t FRWTRLL;
              __IO uint8_t FRWTRLH;
            };
          };
          union {
            __IO uint16_t FRWTRH;
            struct {
              __IO uint8_t FRWTRHL;
              __IO uint8_t FRWTRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t FSTR;
        stc_flash_if_fstr_field_t FSTR_f;
        struct {
          union {
            __IO uint16_t FSTRL;
            struct {
              __IO uint8_t FSTRLL;
              __IO uint8_t FSTRLH;
            };
          };
          union {
            __IO uint16_t FSTRH;
            struct {
              __IO uint8_t FSTRHL;
              __IO uint8_t FSTRHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED0[4];
    union {
        __IO uint32_t FSYNDN;
        stc_flash_if_fsyndn_field_t FSYNDN_f;
        struct {
          union {
            __IO uint16_t FSYNDNL;
            struct {
              __IO uint8_t FSYNDNLL;
              __IO uint8_t FSYNDNLH;
            };
          };
          union {
            __IO uint16_t FSYNDNH;
            struct {
              __IO uint8_t FSYNDNHL;
              __IO uint8_t FSYNDNHH;
            };
          };
        };
    };
    union {
        __IO uint32_t FBFCR;
        stc_flash_if_fbfcr_field_t FBFCR_f;
        struct {
          union {
            __IO uint16_t FBFCRL;
            struct {
              __IO uint8_t FBFCRLL;
              __IO uint8_t FBFCRLH;
            };
          };
          union {
            __IO uint16_t FBFCRH;
            struct {
              __IO uint8_t FBFCRHL;
              __IO uint8_t FBFCRHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED1[8];
    union {
        __IO uint32_t FICR;
        stc_flash_if_ficr_field_t FICR_f;
        struct {
          union {
            __IO uint16_t FICRL;
            struct {
              __IO uint8_t FICRLL;
              __IO uint8_t FICRLH;
            };
          };
          union {
            __IO uint16_t FICRH;
            struct {
              __IO uint8_t FICRHL;
              __IO uint8_t FICRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t FISR;
        stc_flash_if_fisr_field_t FISR_f;
        struct {
          union {
            __IO uint16_t FISRL;
            struct {
              __IO uint8_t FISRLL;
              __IO uint8_t FISRLH;
            };
          };
          union {
            __IO uint16_t FISRH;
            struct {
              __IO uint8_t FISRHL;
              __IO uint8_t FISRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t FICLR;
        stc_flash_if_ficlr_field_t FICLR_f;
        struct {
          union {
            __IO uint16_t FICLRL;
            struct {
              __IO uint8_t FICLRLL;
              __IO uint8_t FICLRLH;
            };
          };
          union {
            __IO uint16_t FICLRH;
            struct {
              __IO uint8_t FICLRHL;
              __IO uint8_t FICLRHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED2[4];
    union {
        __IO uint32_t DFCTRLR;
        stc_flash_if_dfctrlr_field_t DFCTRLR_f;
        struct {
          union {
            __IO uint16_t DFCTRLRL;
            struct {
              __IO uint8_t DFCTRLRLL;
              __IO uint8_t DFCTRLRLH;
            };
          };
          union {
            __IO uint16_t DFCTRLRH;
            struct {
              __IO uint8_t DFCTRLRHL;
              __IO uint8_t DFCTRLRHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED3[204];
    union {
        __IO uint32_t CRTRMM;
        stc_flash_if_crtrmm_field_t CRTRMM_f;
        struct {
          union {
            __IO uint16_t CRTRMML;
            struct {
              __IO uint8_t CRTRMMLL;
              __IO uint8_t CRTRMMLH;
            };
          };
          union {
            __IO uint16_t CRTRMMH;
            struct {
              __IO uint8_t CRTRMMHL;
              __IO uint8_t CRTRMMHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED4[12];
    union {
        __IO uint32_t FGPDM1;
        stc_flash_if_fgpdm1_field_t FGPDM1_f;
        struct {
          union {
            __IO uint16_t FGPDM1L;
            struct {
              __IO uint8_t FGPDM1LL;
              __IO uint8_t FGPDM1LH;
            };
          };
          union {
            __IO uint16_t FGPDM1H;
            struct {
              __IO uint8_t FGPDM1HL;
              __IO uint8_t FGPDM1HH;
            };
          };
        };
    };
    union {
        __IO uint32_t FGPDM2;
        stc_flash_if_fgpdm2_field_t FGPDM2_f;
        struct {
          union {
            __IO uint16_t FGPDM2L;
            struct {
              __IO uint8_t FGPDM2LL;
              __IO uint8_t FGPDM2LH;
            };
          };
          union {
            __IO uint16_t FGPDM2H;
            struct {
              __IO uint8_t FGPDM2HL;
              __IO uint8_t FGPDM2HH;
            };
          };
        };
    };
    union {
        __IO uint32_t FGPDM3;
        stc_flash_if_fgpdm3_field_t FGPDM3_f;
        struct {
          union {
            __IO uint16_t FGPDM3L;
            struct {
              __IO uint8_t FGPDM3LL;
              __IO uint8_t FGPDM3LH;
            };
          };
          union {
            __IO uint16_t FGPDM3H;
            struct {
              __IO uint8_t FGPDM3HL;
              __IO uint8_t FGPDM3HH;
            };
          };
        };
    };
    union {
        __IO uint32_t FGPDM4;
        stc_flash_if_fgpdm4_field_t FGPDM4_f;
        struct {
          union {
            __IO uint16_t FGPDM4L;
            struct {
              __IO uint8_t FGPDM4LL;
              __IO uint8_t FGPDM4LH;
            };
          };
          union {
            __IO uint16_t FGPDM4H;
            struct {
              __IO uint8_t FGPDM4HL;
              __IO uint8_t FGPDM4HH;
            };
          };
        };
    };
} FM_FLASH_IF_TypeDef, FM4_FLASH_IF_TypeDef;

/*******************************************************************************
* GPIO_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO uint32_t PFR0;
        stc_gpio_pfr0_field_t PFR0_f;
        struct {
          union {
            __IO uint16_t PFR0L;
            struct {
              __IO uint8_t PFR0LL;
              __IO uint8_t PFR0LH;
            };
          };
          union {
            __IO uint16_t PFR0H;
            struct {
              __IO uint8_t PFR0HL;
              __IO uint8_t PFR0HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PFR1;
        stc_gpio_pfr1_field_t PFR1_f;
        struct {
          union {
            __IO uint16_t PFR1L;
            struct {
              __IO uint8_t PFR1LL;
              __IO uint8_t PFR1LH;
            };
          };
          union {
            __IO uint16_t PFR1H;
            struct {
              __IO uint8_t PFR1HL;
              __IO uint8_t PFR1HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PFR2;
        stc_gpio_pfr2_field_t PFR2_f;
        struct {
          union {
            __IO uint16_t PFR2L;
            struct {
              __IO uint8_t PFR2LL;
              __IO uint8_t PFR2LH;
            };
          };
          union {
            __IO uint16_t PFR2H;
            struct {
              __IO uint8_t PFR2HL;
              __IO uint8_t PFR2HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PFR3;
        stc_gpio_pfr3_field_t PFR3_f;
        struct {
          union {
            __IO uint16_t PFR3L;
            struct {
              __IO uint8_t PFR3LL;
              __IO uint8_t PFR3LH;
            };
          };
          union {
            __IO uint16_t PFR3H;
            struct {
              __IO uint8_t PFR3HL;
              __IO uint8_t PFR3HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PFR4;
        stc_gpio_pfr4_field_t PFR4_f;
        struct {
          union {
            __IO uint16_t PFR4L;
            struct {
              __IO uint8_t PFR4LL;
              __IO uint8_t PFR4LH;
            };
          };
          union {
            __IO uint16_t PFR4H;
            struct {
              __IO uint8_t PFR4HL;
              __IO uint8_t PFR4HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PFR5;
        stc_gpio_pfr5_field_t PFR5_f;
        struct {
          union {
            __IO uint16_t PFR5L;
            struct {
              __IO uint8_t PFR5LL;
              __IO uint8_t PFR5LH;
            };
          };
          union {
            __IO uint16_t PFR5H;
            struct {
              __IO uint8_t PFR5HL;
              __IO uint8_t PFR5HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PFR6;
        stc_gpio_pfr6_field_t PFR6_f;
        struct {
          union {
            __IO uint16_t PFR6L;
            struct {
              __IO uint8_t PFR6LL;
              __IO uint8_t PFR6LH;
            };
          };
          union {
            __IO uint16_t PFR6H;
            struct {
              __IO uint8_t PFR6HL;
              __IO uint8_t PFR6HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PFR7;
        stc_gpio_pfr7_field_t PFR7_f;
        struct {
          union {
            __IO uint16_t PFR7L;
            struct {
              __IO uint8_t PFR7LL;
              __IO uint8_t PFR7LH;
            };
          };
          union {
            __IO uint16_t PFR7H;
            struct {
              __IO uint8_t PFR7HL;
              __IO uint8_t PFR7HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PFR8;
        stc_gpio_pfr8_field_t PFR8_f;
        struct {
          union {
            __IO uint16_t PFR8L;
            struct {
              __IO uint8_t PFR8LL;
              __IO uint8_t PFR8LH;
            };
          };
          union {
            __IO uint16_t PFR8H;
            struct {
              __IO uint8_t PFR8HL;
              __IO uint8_t PFR8HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PFR9;
        stc_gpio_pfr9_field_t PFR9_f;
        struct {
          union {
            __IO uint16_t PFR9L;
            struct {
              __IO uint8_t PFR9LL;
              __IO uint8_t PFR9LH;
            };
          };
          union {
            __IO uint16_t PFR9H;
            struct {
              __IO uint8_t PFR9HL;
              __IO uint8_t PFR9HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PFRA;
        stc_gpio_pfra_field_t PFRA_f;
        struct {
          union {
            __IO uint16_t PFRAL;
            struct {
              __IO uint8_t PFRALL;
              __IO uint8_t PFRALH;
            };
          };
          union {
            __IO uint16_t PFRAH;
            struct {
              __IO uint8_t PFRAHL;
              __IO uint8_t PFRAHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PFRB;
        stc_gpio_pfrb_field_t PFRB_f;
        struct {
          union {
            __IO uint16_t PFRBL;
            struct {
              __IO uint8_t PFRBLL;
              __IO uint8_t PFRBLH;
            };
          };
          union {
            __IO uint16_t PFRBH;
            struct {
              __IO uint8_t PFRBHL;
              __IO uint8_t PFRBHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PFRC;
        stc_gpio_pfrc_field_t PFRC_f;
        struct {
          union {
            __IO uint16_t PFRCL;
            struct {
              __IO uint8_t PFRCLL;
              __IO uint8_t PFRCLH;
            };
          };
          union {
            __IO uint16_t PFRCH;
            struct {
              __IO uint8_t PFRCHL;
              __IO uint8_t PFRCHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PFRD;
        stc_gpio_pfrd_field_t PFRD_f;
        struct {
          union {
            __IO uint16_t PFRDL;
            struct {
              __IO uint8_t PFRDLL;
              __IO uint8_t PFRDLH;
            };
          };
          union {
            __IO uint16_t PFRDH;
            struct {
              __IO uint8_t PFRDHL;
              __IO uint8_t PFRDHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PFRE;
        stc_gpio_pfre_field_t PFRE_f;
        struct {
          union {
            __IO uint16_t PFREL;
            struct {
              __IO uint8_t PFRELL;
              __IO uint8_t PFRELH;
            };
          };
          union {
            __IO uint16_t PFREH;
            struct {
              __IO uint8_t PFREHL;
              __IO uint8_t PFREHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PFRF;
        stc_gpio_pfrf_field_t PFRF_f;
        struct {
          union {
            __IO uint16_t PFRFL;
            struct {
              __IO uint8_t PFRFLL;
              __IO uint8_t PFRFLH;
            };
          };
          union {
            __IO uint16_t PFRFH;
            struct {
              __IO uint8_t PFRFHL;
              __IO uint8_t PFRFHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED0[192];
    union {
        __IO uint32_t PCR0;
        stc_gpio_pcr0_field_t PCR0_f;
        struct {
          union {
            __IO uint16_t PCR0L;
            struct {
              __IO uint8_t PCR0LL;
              __IO uint8_t PCR0LH;
            };
          };
          union {
            __IO uint16_t PCR0H;
            struct {
              __IO uint8_t PCR0HL;
              __IO uint8_t PCR0HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PCR1;
        stc_gpio_pcr1_field_t PCR1_f;
        struct {
          union {
            __IO uint16_t PCR1L;
            struct {
              __IO uint8_t PCR1LL;
              __IO uint8_t PCR1LH;
            };
          };
          union {
            __IO uint16_t PCR1H;
            struct {
              __IO uint8_t PCR1HL;
              __IO uint8_t PCR1HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PCR2;
        stc_gpio_pcr2_field_t PCR2_f;
        struct {
          union {
            __IO uint16_t PCR2L;
            struct {
              __IO uint8_t PCR2LL;
              __IO uint8_t PCR2LH;
            };
          };
          union {
            __IO uint16_t PCR2H;
            struct {
              __IO uint8_t PCR2HL;
              __IO uint8_t PCR2HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PCR3;
        stc_gpio_pcr3_field_t PCR3_f;
        struct {
          union {
            __IO uint16_t PCR3L;
            struct {
              __IO uint8_t PCR3LL;
              __IO uint8_t PCR3LH;
            };
          };
          union {
            __IO uint16_t PCR3H;
            struct {
              __IO uint8_t PCR3HL;
              __IO uint8_t PCR3HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PCR4;
        stc_gpio_pcr4_field_t PCR4_f;
        struct {
          union {
            __IO uint16_t PCR4L;
            struct {
              __IO uint8_t PCR4LL;
              __IO uint8_t PCR4LH;
            };
          };
          union {
            __IO uint16_t PCR4H;
            struct {
              __IO uint8_t PCR4HL;
              __IO uint8_t PCR4HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PCR5;
        stc_gpio_pcr5_field_t PCR5_f;
        struct {
          union {
            __IO uint16_t PCR5L;
            struct {
              __IO uint8_t PCR5LL;
              __IO uint8_t PCR5LH;
            };
          };
          union {
            __IO uint16_t PCR5H;
            struct {
              __IO uint8_t PCR5HL;
              __IO uint8_t PCR5HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PCR6;
        stc_gpio_pcr6_field_t PCR6_f;
        struct {
          union {
            __IO uint16_t PCR6L;
            struct {
              __IO uint8_t PCR6LL;
              __IO uint8_t PCR6LH;
            };
          };
          union {
            __IO uint16_t PCR6H;
            struct {
              __IO uint8_t PCR6HL;
              __IO uint8_t PCR6HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PCR7;
        stc_gpio_pcr7_field_t PCR7_f;
        struct {
          union {
            __IO uint16_t PCR7L;
            struct {
              __IO uint8_t PCR7LL;
              __IO uint8_t PCR7LH;
            };
          };
          union {
            __IO uint16_t PCR7H;
            struct {
              __IO uint8_t PCR7HL;
              __IO uint8_t PCR7HH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED1[4];
    union {
        __IO uint32_t PCR9;
        stc_gpio_pcr9_field_t PCR9_f;
        struct {
          union {
            __IO uint16_t PCR9L;
            struct {
              __IO uint8_t PCR9LL;
              __IO uint8_t PCR9LH;
            };
          };
          union {
            __IO uint16_t PCR9H;
            struct {
              __IO uint8_t PCR9HL;
              __IO uint8_t PCR9HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PCRA;
        stc_gpio_pcra_field_t PCRA_f;
        struct {
          union {
            __IO uint16_t PCRAL;
            struct {
              __IO uint8_t PCRALL;
              __IO uint8_t PCRALH;
            };
          };
          union {
            __IO uint16_t PCRAH;
            struct {
              __IO uint8_t PCRAHL;
              __IO uint8_t PCRAHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PCRB;
        stc_gpio_pcrb_field_t PCRB_f;
        struct {
          union {
            __IO uint16_t PCRBL;
            struct {
              __IO uint8_t PCRBLL;
              __IO uint8_t PCRBLH;
            };
          };
          union {
            __IO uint16_t PCRBH;
            struct {
              __IO uint8_t PCRBHL;
              __IO uint8_t PCRBHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PCRC;
        stc_gpio_pcrc_field_t PCRC_f;
        struct {
          union {
            __IO uint16_t PCRCL;
            struct {
              __IO uint8_t PCRCLL;
              __IO uint8_t PCRCLH;
            };
          };
          union {
            __IO uint16_t PCRCH;
            struct {
              __IO uint8_t PCRCHL;
              __IO uint8_t PCRCHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PCRD;
        stc_gpio_pcrd_field_t PCRD_f;
        struct {
          union {
            __IO uint16_t PCRDL;
            struct {
              __IO uint8_t PCRDLL;
              __IO uint8_t PCRDLH;
            };
          };
          union {
            __IO uint16_t PCRDH;
            struct {
              __IO uint8_t PCRDHL;
              __IO uint8_t PCRDHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PCRE;
        stc_gpio_pcre_field_t PCRE_f;
        struct {
          union {
            __IO uint16_t PCREL;
            struct {
              __IO uint8_t PCRELL;
              __IO uint8_t PCRELH;
            };
          };
          union {
            __IO uint16_t PCREH;
            struct {
              __IO uint8_t PCREHL;
              __IO uint8_t PCREHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PCRF;
        stc_gpio_pcrf_field_t PCRF_f;
        struct {
          union {
            __IO uint16_t PCRFL;
            struct {
              __IO uint8_t PCRFLL;
              __IO uint8_t PCRFLH;
            };
          };
          union {
            __IO uint16_t PCRFH;
            struct {
              __IO uint8_t PCRFHL;
              __IO uint8_t PCRFHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED2[192];
    union {
        __IO uint32_t DDR0;
        stc_gpio_ddr0_field_t DDR0_f;
        struct {
          union {
            __IO uint16_t DDR0L;
            struct {
              __IO uint8_t DDR0LL;
              __IO uint8_t DDR0LH;
            };
          };
          union {
            __IO uint16_t DDR0H;
            struct {
              __IO uint8_t DDR0HL;
              __IO uint8_t DDR0HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DDR1;
        stc_gpio_ddr1_field_t DDR1_f;
        struct {
          union {
            __IO uint16_t DDR1L;
            struct {
              __IO uint8_t DDR1LL;
              __IO uint8_t DDR1LH;
            };
          };
          union {
            __IO uint16_t DDR1H;
            struct {
              __IO uint8_t DDR1HL;
              __IO uint8_t DDR1HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DDR2;
        stc_gpio_ddr2_field_t DDR2_f;
        struct {
          union {
            __IO uint16_t DDR2L;
            struct {
              __IO uint8_t DDR2LL;
              __IO uint8_t DDR2LH;
            };
          };
          union {
            __IO uint16_t DDR2H;
            struct {
              __IO uint8_t DDR2HL;
              __IO uint8_t DDR2HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DDR3;
        stc_gpio_ddr3_field_t DDR3_f;
        struct {
          union {
            __IO uint16_t DDR3L;
            struct {
              __IO uint8_t DDR3LL;
              __IO uint8_t DDR3LH;
            };
          };
          union {
            __IO uint16_t DDR3H;
            struct {
              __IO uint8_t DDR3HL;
              __IO uint8_t DDR3HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DDR4;
        stc_gpio_ddr4_field_t DDR4_f;
        struct {
          union {
            __IO uint16_t DDR4L;
            struct {
              __IO uint8_t DDR4LL;
              __IO uint8_t DDR4LH;
            };
          };
          union {
            __IO uint16_t DDR4H;
            struct {
              __IO uint8_t DDR4HL;
              __IO uint8_t DDR4HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DDR5;
        stc_gpio_ddr5_field_t DDR5_f;
        struct {
          union {
            __IO uint16_t DDR5L;
            struct {
              __IO uint8_t DDR5LL;
              __IO uint8_t DDR5LH;
            };
          };
          union {
            __IO uint16_t DDR5H;
            struct {
              __IO uint8_t DDR5HL;
              __IO uint8_t DDR5HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DDR6;
        stc_gpio_ddr6_field_t DDR6_f;
        struct {
          union {
            __IO uint16_t DDR6L;
            struct {
              __IO uint8_t DDR6LL;
              __IO uint8_t DDR6LH;
            };
          };
          union {
            __IO uint16_t DDR6H;
            struct {
              __IO uint8_t DDR6HL;
              __IO uint8_t DDR6HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DDR7;
        stc_gpio_ddr7_field_t DDR7_f;
        struct {
          union {
            __IO uint16_t DDR7L;
            struct {
              __IO uint8_t DDR7LL;
              __IO uint8_t DDR7LH;
            };
          };
          union {
            __IO uint16_t DDR7H;
            struct {
              __IO uint8_t DDR7HL;
              __IO uint8_t DDR7HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DDR8;
        stc_gpio_ddr8_field_t DDR8_f;
        struct {
          union {
            __IO uint16_t DDR8L;
            struct {
              __IO uint8_t DDR8LL;
              __IO uint8_t DDR8LH;
            };
          };
          union {
            __IO uint16_t DDR8H;
            struct {
              __IO uint8_t DDR8HL;
              __IO uint8_t DDR8HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DDR9;
        stc_gpio_ddr9_field_t DDR9_f;
        struct {
          union {
            __IO uint16_t DDR9L;
            struct {
              __IO uint8_t DDR9LL;
              __IO uint8_t DDR9LH;
            };
          };
          union {
            __IO uint16_t DDR9H;
            struct {
              __IO uint8_t DDR9HL;
              __IO uint8_t DDR9HH;
            };
          };
        };
    };
    union {
        __IO uint32_t DDRA;
        stc_gpio_ddra_field_t DDRA_f;
        struct {
          union {
            __IO uint16_t DDRAL;
            struct {
              __IO uint8_t DDRALL;
              __IO uint8_t DDRALH;
            };
          };
          union {
            __IO uint16_t DDRAH;
            struct {
              __IO uint8_t DDRAHL;
              __IO uint8_t DDRAHH;
            };
          };
        };
    };
    union {
        __IO uint32_t DDRB;
        stc_gpio_ddrb_field_t DDRB_f;
        struct {
          union {
            __IO uint16_t DDRBL;
            struct {
              __IO uint8_t DDRBLL;
              __IO uint8_t DDRBLH;
            };
          };
          union {
            __IO uint16_t DDRBH;
            struct {
              __IO uint8_t DDRBHL;
              __IO uint8_t DDRBHH;
            };
          };
        };
    };
    union {
        __IO uint32_t DDRC;
        stc_gpio_ddrc_field_t DDRC_f;
        struct {
          union {
            __IO uint16_t DDRCL;
            struct {
              __IO uint8_t DDRCLL;
              __IO uint8_t DDRCLH;
            };
          };
          union {
            __IO uint16_t DDRCH;
            struct {
              __IO uint8_t DDRCHL;
              __IO uint8_t DDRCHH;
            };
          };
        };
    };
    union {
        __IO uint32_t DDRD;
        stc_gpio_ddrd_field_t DDRD_f;
        struct {
          union {
            __IO uint16_t DDRDL;
            struct {
              __IO uint8_t DDRDLL;
              __IO uint8_t DDRDLH;
            };
          };
          union {
            __IO uint16_t DDRDH;
            struct {
              __IO uint8_t DDRDHL;
              __IO uint8_t DDRDHH;
            };
          };
        };
    };
    union {
        __IO uint32_t DDRE;
        stc_gpio_ddre_field_t DDRE_f;
        struct {
          union {
            __IO uint16_t DDREL;
            struct {
              __IO uint8_t DDRELL;
              __IO uint8_t DDRELH;
            };
          };
          union {
            __IO uint16_t DDREH;
            struct {
              __IO uint8_t DDREHL;
              __IO uint8_t DDREHH;
            };
          };
        };
    };
    union {
        __IO uint32_t DDRF;
        stc_gpio_ddrf_field_t DDRF_f;
        struct {
          union {
            __IO uint16_t DDRFL;
            struct {
              __IO uint8_t DDRFLL;
              __IO uint8_t DDRFLH;
            };
          };
          union {
            __IO uint16_t DDRFH;
            struct {
              __IO uint8_t DDRFHL;
              __IO uint8_t DDRFHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED3[192];
    union {
        __IO uint32_t PDIR0;
        stc_gpio_pdir0_field_t PDIR0_f;
        struct {
          union {
            __IO uint16_t PDIR0L;
            struct {
              __IO uint8_t PDIR0LL;
              __IO uint8_t PDIR0LH;
            };
          };
          union {
            __IO uint16_t PDIR0H;
            struct {
              __IO uint8_t PDIR0HL;
              __IO uint8_t PDIR0HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDIR1;
        stc_gpio_pdir1_field_t PDIR1_f;
        struct {
          union {
            __IO uint16_t PDIR1L;
            struct {
              __IO uint8_t PDIR1LL;
              __IO uint8_t PDIR1LH;
            };
          };
          union {
            __IO uint16_t PDIR1H;
            struct {
              __IO uint8_t PDIR1HL;
              __IO uint8_t PDIR1HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDIR2;
        stc_gpio_pdir2_field_t PDIR2_f;
        struct {
          union {
            __IO uint16_t PDIR2L;
            struct {
              __IO uint8_t PDIR2LL;
              __IO uint8_t PDIR2LH;
            };
          };
          union {
            __IO uint16_t PDIR2H;
            struct {
              __IO uint8_t PDIR2HL;
              __IO uint8_t PDIR2HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDIR3;
        stc_gpio_pdir3_field_t PDIR3_f;
        struct {
          union {
            __IO uint16_t PDIR3L;
            struct {
              __IO uint8_t PDIR3LL;
              __IO uint8_t PDIR3LH;
            };
          };
          union {
            __IO uint16_t PDIR3H;
            struct {
              __IO uint8_t PDIR3HL;
              __IO uint8_t PDIR3HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDIR4;
        stc_gpio_pdir4_field_t PDIR4_f;
        struct {
          union {
            __IO uint16_t PDIR4L;
            struct {
              __IO uint8_t PDIR4LL;
              __IO uint8_t PDIR4LH;
            };
          };
          union {
            __IO uint16_t PDIR4H;
            struct {
              __IO uint8_t PDIR4HL;
              __IO uint8_t PDIR4HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDIR5;
        stc_gpio_pdir5_field_t PDIR5_f;
        struct {
          union {
            __IO uint16_t PDIR5L;
            struct {
              __IO uint8_t PDIR5LL;
              __IO uint8_t PDIR5LH;
            };
          };
          union {
            __IO uint16_t PDIR5H;
            struct {
              __IO uint8_t PDIR5HL;
              __IO uint8_t PDIR5HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDIR6;
        stc_gpio_pdir6_field_t PDIR6_f;
        struct {
          union {
            __IO uint16_t PDIR6L;
            struct {
              __IO uint8_t PDIR6LL;
              __IO uint8_t PDIR6LH;
            };
          };
          union {
            __IO uint16_t PDIR6H;
            struct {
              __IO uint8_t PDIR6HL;
              __IO uint8_t PDIR6HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDIR7;
        stc_gpio_pdir7_field_t PDIR7_f;
        struct {
          union {
            __IO uint16_t PDIR7L;
            struct {
              __IO uint8_t PDIR7LL;
              __IO uint8_t PDIR7LH;
            };
          };
          union {
            __IO uint16_t PDIR7H;
            struct {
              __IO uint8_t PDIR7HL;
              __IO uint8_t PDIR7HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDIR8;
        stc_gpio_pdir8_field_t PDIR8_f;
        struct {
          union {
            __IO uint16_t PDIR8L;
            struct {
              __IO uint8_t PDIR8LL;
              __IO uint8_t PDIR8LH;
            };
          };
          union {
            __IO uint16_t PDIR8H;
            struct {
              __IO uint8_t PDIR8HL;
              __IO uint8_t PDIR8HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDIR9;
        stc_gpio_pdir9_field_t PDIR9_f;
        struct {
          union {
            __IO uint16_t PDIR9L;
            struct {
              __IO uint8_t PDIR9LL;
              __IO uint8_t PDIR9LH;
            };
          };
          union {
            __IO uint16_t PDIR9H;
            struct {
              __IO uint8_t PDIR9HL;
              __IO uint8_t PDIR9HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDIRA;
        stc_gpio_pdira_field_t PDIRA_f;
        struct {
          union {
            __IO uint16_t PDIRAL;
            struct {
              __IO uint8_t PDIRALL;
              __IO uint8_t PDIRALH;
            };
          };
          union {
            __IO uint16_t PDIRAH;
            struct {
              __IO uint8_t PDIRAHL;
              __IO uint8_t PDIRAHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDIRB;
        stc_gpio_pdirb_field_t PDIRB_f;
        struct {
          union {
            __IO uint16_t PDIRBL;
            struct {
              __IO uint8_t PDIRBLL;
              __IO uint8_t PDIRBLH;
            };
          };
          union {
            __IO uint16_t PDIRBH;
            struct {
              __IO uint8_t PDIRBHL;
              __IO uint8_t PDIRBHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDIRC;
        stc_gpio_pdirc_field_t PDIRC_f;
        struct {
          union {
            __IO uint16_t PDIRCL;
            struct {
              __IO uint8_t PDIRCLL;
              __IO uint8_t PDIRCLH;
            };
          };
          union {
            __IO uint16_t PDIRCH;
            struct {
              __IO uint8_t PDIRCHL;
              __IO uint8_t PDIRCHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDIRD;
        stc_gpio_pdird_field_t PDIRD_f;
        struct {
          union {
            __IO uint16_t PDIRDL;
            struct {
              __IO uint8_t PDIRDLL;
              __IO uint8_t PDIRDLH;
            };
          };
          union {
            __IO uint16_t PDIRDH;
            struct {
              __IO uint8_t PDIRDHL;
              __IO uint8_t PDIRDHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDIRE;
        stc_gpio_pdire_field_t PDIRE_f;
        struct {
          union {
            __IO uint16_t PDIREL;
            struct {
              __IO uint8_t PDIRELL;
              __IO uint8_t PDIRELH;
            };
          };
          union {
            __IO uint16_t PDIREH;
            struct {
              __IO uint8_t PDIREHL;
              __IO uint8_t PDIREHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDIRF;
        stc_gpio_pdirf_field_t PDIRF_f;
        struct {
          union {
            __IO uint16_t PDIRFL;
            struct {
              __IO uint8_t PDIRFLL;
              __IO uint8_t PDIRFLH;
            };
          };
          union {
            __IO uint16_t PDIRFH;
            struct {
              __IO uint8_t PDIRFHL;
              __IO uint8_t PDIRFHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED4[192];
    union {
        __IO uint32_t PDOR0;
        stc_gpio_pdor0_field_t PDOR0_f;
        struct {
          union {
            __IO uint16_t PDOR0L;
            struct {
              __IO uint8_t PDOR0LL;
              __IO uint8_t PDOR0LH;
            };
          };
          union {
            __IO uint16_t PDOR0H;
            struct {
              __IO uint8_t PDOR0HL;
              __IO uint8_t PDOR0HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDOR1;
        stc_gpio_pdor1_field_t PDOR1_f;
        struct {
          union {
            __IO uint16_t PDOR1L;
            struct {
              __IO uint8_t PDOR1LL;
              __IO uint8_t PDOR1LH;
            };
          };
          union {
            __IO uint16_t PDOR1H;
            struct {
              __IO uint8_t PDOR1HL;
              __IO uint8_t PDOR1HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDOR2;
        stc_gpio_pdor2_field_t PDOR2_f;
        struct {
          union {
            __IO uint16_t PDOR2L;
            struct {
              __IO uint8_t PDOR2LL;
              __IO uint8_t PDOR2LH;
            };
          };
          union {
            __IO uint16_t PDOR2H;
            struct {
              __IO uint8_t PDOR2HL;
              __IO uint8_t PDOR2HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDOR3;
        stc_gpio_pdor3_field_t PDOR3_f;
        struct {
          union {
            __IO uint16_t PDOR3L;
            struct {
              __IO uint8_t PDOR3LL;
              __IO uint8_t PDOR3LH;
            };
          };
          union {
            __IO uint16_t PDOR3H;
            struct {
              __IO uint8_t PDOR3HL;
              __IO uint8_t PDOR3HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDOR4;
        stc_gpio_pdor4_field_t PDOR4_f;
        struct {
          union {
            __IO uint16_t PDOR4L;
            struct {
              __IO uint8_t PDOR4LL;
              __IO uint8_t PDOR4LH;
            };
          };
          union {
            __IO uint16_t PDOR4H;
            struct {
              __IO uint8_t PDOR4HL;
              __IO uint8_t PDOR4HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDOR5;
        stc_gpio_pdor5_field_t PDOR5_f;
        struct {
          union {
            __IO uint16_t PDOR5L;
            struct {
              __IO uint8_t PDOR5LL;
              __IO uint8_t PDOR5LH;
            };
          };
          union {
            __IO uint16_t PDOR5H;
            struct {
              __IO uint8_t PDOR5HL;
              __IO uint8_t PDOR5HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDOR6;
        stc_gpio_pdor6_field_t PDOR6_f;
        struct {
          union {
            __IO uint16_t PDOR6L;
            struct {
              __IO uint8_t PDOR6LL;
              __IO uint8_t PDOR6LH;
            };
          };
          union {
            __IO uint16_t PDOR6H;
            struct {
              __IO uint8_t PDOR6HL;
              __IO uint8_t PDOR6HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDOR7;
        stc_gpio_pdor7_field_t PDOR7_f;
        struct {
          union {
            __IO uint16_t PDOR7L;
            struct {
              __IO uint8_t PDOR7LL;
              __IO uint8_t PDOR7LH;
            };
          };
          union {
            __IO uint16_t PDOR7H;
            struct {
              __IO uint8_t PDOR7HL;
              __IO uint8_t PDOR7HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDOR8;
        stc_gpio_pdor8_field_t PDOR8_f;
        struct {
          union {
            __IO uint16_t PDOR8L;
            struct {
              __IO uint8_t PDOR8LL;
              __IO uint8_t PDOR8LH;
            };
          };
          union {
            __IO uint16_t PDOR8H;
            struct {
              __IO uint8_t PDOR8HL;
              __IO uint8_t PDOR8HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDOR9;
        stc_gpio_pdor9_field_t PDOR9_f;
        struct {
          union {
            __IO uint16_t PDOR9L;
            struct {
              __IO uint8_t PDOR9LL;
              __IO uint8_t PDOR9LH;
            };
          };
          union {
            __IO uint16_t PDOR9H;
            struct {
              __IO uint8_t PDOR9HL;
              __IO uint8_t PDOR9HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDORA;
        stc_gpio_pdora_field_t PDORA_f;
        struct {
          union {
            __IO uint16_t PDORAL;
            struct {
              __IO uint8_t PDORALL;
              __IO uint8_t PDORALH;
            };
          };
          union {
            __IO uint16_t PDORAH;
            struct {
              __IO uint8_t PDORAHL;
              __IO uint8_t PDORAHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDORB;
        stc_gpio_pdorb_field_t PDORB_f;
        struct {
          union {
            __IO uint16_t PDORBL;
            struct {
              __IO uint8_t PDORBLL;
              __IO uint8_t PDORBLH;
            };
          };
          union {
            __IO uint16_t PDORBH;
            struct {
              __IO uint8_t PDORBHL;
              __IO uint8_t PDORBHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDORC;
        stc_gpio_pdorc_field_t PDORC_f;
        struct {
          union {
            __IO uint16_t PDORCL;
            struct {
              __IO uint8_t PDORCLL;
              __IO uint8_t PDORCLH;
            };
          };
          union {
            __IO uint16_t PDORCH;
            struct {
              __IO uint8_t PDORCHL;
              __IO uint8_t PDORCHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDORD;
        stc_gpio_pdord_field_t PDORD_f;
        struct {
          union {
            __IO uint16_t PDORDL;
            struct {
              __IO uint8_t PDORDLL;
              __IO uint8_t PDORDLH;
            };
          };
          union {
            __IO uint16_t PDORDH;
            struct {
              __IO uint8_t PDORDHL;
              __IO uint8_t PDORDHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDORE;
        stc_gpio_pdore_field_t PDORE_f;
        struct {
          union {
            __IO uint16_t PDOREL;
            struct {
              __IO uint8_t PDORELL;
              __IO uint8_t PDORELH;
            };
          };
          union {
            __IO uint16_t PDOREH;
            struct {
              __IO uint8_t PDOREHL;
              __IO uint8_t PDOREHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDORF;
        stc_gpio_pdorf_field_t PDORF_f;
        struct {
          union {
            __IO uint16_t PDORFL;
            struct {
              __IO uint8_t PDORFLL;
              __IO uint8_t PDORFLH;
            };
          };
          union {
            __IO uint16_t PDORFH;
            struct {
              __IO uint8_t PDORFHL;
              __IO uint8_t PDORFHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED5[192];
    union {
        __IO uint32_t ADE;
        stc_gpio_ade_field_t ADE_f;
        struct {
          union {
            __IO uint16_t ADEL;
            struct {
              __IO uint8_t ADELL;
              __IO uint8_t ADELH;
            };
          };
          union {
            __IO uint16_t ADEH;
            struct {
              __IO uint8_t ADEHL;
              __IO uint8_t ADEHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED6[124];
    union {
        __IO uint32_t SPSR;
        stc_gpio_spsr_field_t SPSR_f;
        struct {
          union {
            __IO uint16_t SPSRL;
            struct {
              __IO uint8_t SPSRLL;
              __IO uint8_t SPSRLH;
            };
          };
          union {
            __IO uint16_t SPSRH;
            struct {
              __IO uint8_t SPSRHL;
              __IO uint8_t SPSRHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED7[124];
    union {
        __IO uint32_t EPFR00;
        stc_gpio_epfr00_field_t EPFR00_f;
        struct {
          union {
            __IO uint16_t EPFR00L;
            struct {
              __IO uint8_t EPFR00LL;
              __IO uint8_t EPFR00LH;
            };
          };
          union {
            __IO uint16_t EPFR00H;
            struct {
              __IO uint8_t EPFR00HL;
              __IO uint8_t EPFR00HH;
            };
          };
        };
    };
    union {
        __IO uint32_t EPFR01;
        stc_gpio_epfr01_field_t EPFR01_f;
        struct {
          union {
            __IO uint16_t EPFR01L;
            struct {
              __IO uint8_t EPFR01LL;
              __IO uint8_t EPFR01LH;
            };
          };
          union {
            __IO uint16_t EPFR01H;
            struct {
              __IO uint8_t EPFR01HL;
              __IO uint8_t EPFR01HH;
            };
          };
        };
    };
    union {
        __IO uint32_t EPFR02;
        stc_gpio_epfr02_field_t EPFR02_f;
        struct {
          union {
            __IO uint16_t EPFR02L;
            struct {
              __IO uint8_t EPFR02LL;
              __IO uint8_t EPFR02LH;
            };
          };
          union {
            __IO uint16_t EPFR02H;
            struct {
              __IO uint8_t EPFR02HL;
              __IO uint8_t EPFR02HH;
            };
          };
        };
    };
    union {
        __IO uint32_t EPFR03;
        stc_gpio_epfr03_field_t EPFR03_f;
        struct {
          union {
            __IO uint16_t EPFR03L;
            struct {
              __IO uint8_t EPFR03LL;
              __IO uint8_t EPFR03LH;
            };
          };
          union {
            __IO uint16_t EPFR03H;
            struct {
              __IO uint8_t EPFR03HL;
              __IO uint8_t EPFR03HH;
            };
          };
        };
    };
    union {
        __IO uint32_t EPFR04;
        stc_gpio_epfr04_field_t EPFR04_f;
        struct {
          union {
            __IO uint16_t EPFR04L;
            struct {
              __IO uint8_t EPFR04LL;
              __IO uint8_t EPFR04LH;
            };
          };
          union {
            __IO uint16_t EPFR04H;
            struct {
              __IO uint8_t EPFR04HL;
              __IO uint8_t EPFR04HH;
            };
          };
        };
    };
    union {
        __IO uint32_t EPFR05;
        stc_gpio_epfr05_field_t EPFR05_f;
        struct {
          union {
            __IO uint16_t EPFR05L;
            struct {
              __IO uint8_t EPFR05LL;
              __IO uint8_t EPFR05LH;
            };
          };
          union {
            __IO uint16_t EPFR05H;
            struct {
              __IO uint8_t EPFR05HL;
              __IO uint8_t EPFR05HH;
            };
          };
        };
    };
    union {
        __IO uint32_t EPFR06;
        stc_gpio_epfr06_field_t EPFR06_f;
        struct {
          union {
            __IO uint16_t EPFR06L;
            struct {
              __IO uint8_t EPFR06LL;
              __IO uint8_t EPFR06LH;
            };
          };
          union {
            __IO uint16_t EPFR06H;
            struct {
              __IO uint8_t EPFR06HL;
              __IO uint8_t EPFR06HH;
            };
          };
        };
    };
    union {
        __IO uint32_t EPFR07;
        stc_gpio_epfr07_field_t EPFR07_f;
        struct {
          union {
            __IO uint16_t EPFR07L;
            struct {
              __IO uint8_t EPFR07LL;
              __IO uint8_t EPFR07LH;
            };
          };
          union {
            __IO uint16_t EPFR07H;
            struct {
              __IO uint8_t EPFR07HL;
              __IO uint8_t EPFR07HH;
            };
          };
        };
    };
    union {
        __IO uint32_t EPFR08;
        stc_gpio_epfr08_field_t EPFR08_f;
        struct {
          union {
            __IO uint16_t EPFR08L;
            struct {
              __IO uint8_t EPFR08LL;
              __IO uint8_t EPFR08LH;
            };
          };
          union {
            __IO uint16_t EPFR08H;
            struct {
              __IO uint8_t EPFR08HL;
              __IO uint8_t EPFR08HH;
            };
          };
        };
    };
    union {
        __IO uint32_t EPFR09;
        stc_gpio_epfr09_field_t EPFR09_f;
        struct {
          union {
            __IO uint16_t EPFR09L;
            struct {
              __IO uint8_t EPFR09LL;
              __IO uint8_t EPFR09LH;
            };
          };
          union {
            __IO uint16_t EPFR09H;
            struct {
              __IO uint8_t EPFR09HL;
              __IO uint8_t EPFR09HH;
            };
          };
        };
    };
    union {
        __IO uint32_t EPFR10;
        stc_gpio_epfr10_field_t EPFR10_f;
        struct {
          union {
            __IO uint16_t EPFR10L;
            struct {
              __IO uint8_t EPFR10LL;
              __IO uint8_t EPFR10LH;
            };
          };
          union {
            __IO uint16_t EPFR10H;
            struct {
              __IO uint8_t EPFR10HL;
              __IO uint8_t EPFR10HH;
            };
          };
        };
    };
    union {
        __IO uint32_t EPFR11;
        stc_gpio_epfr11_field_t EPFR11_f;
        struct {
          union {
            __IO uint16_t EPFR11L;
            struct {
              __IO uint8_t EPFR11LL;
              __IO uint8_t EPFR11LH;
            };
          };
          union {
            __IO uint16_t EPFR11H;
            struct {
              __IO uint8_t EPFR11HL;
              __IO uint8_t EPFR11HH;
            };
          };
        };
    };
    union {
        __IO uint32_t EPFR12;
        stc_gpio_epfr12_field_t EPFR12_f;
        struct {
          union {
            __IO uint16_t EPFR12L;
            struct {
              __IO uint8_t EPFR12LL;
              __IO uint8_t EPFR12LH;
            };
          };
          union {
            __IO uint16_t EPFR12H;
            struct {
              __IO uint8_t EPFR12HL;
              __IO uint8_t EPFR12HH;
            };
          };
        };
    };
    union {
        __IO uint32_t EPFR13;
        stc_gpio_epfr13_field_t EPFR13_f;
        struct {
          union {
            __IO uint16_t EPFR13L;
            struct {
              __IO uint8_t EPFR13LL;
              __IO uint8_t EPFR13LH;
            };
          };
          union {
            __IO uint16_t EPFR13H;
            struct {
              __IO uint8_t EPFR13HL;
              __IO uint8_t EPFR13HH;
            };
          };
        };
    };
    union {
        __IO uint32_t EPFR14;
        stc_gpio_epfr14_field_t EPFR14_f;
        struct {
          union {
            __IO uint16_t EPFR14L;
            struct {
              __IO uint8_t EPFR14LL;
              __IO uint8_t EPFR14LH;
            };
          };
          union {
            __IO uint16_t EPFR14H;
            struct {
              __IO uint8_t EPFR14HL;
              __IO uint8_t EPFR14HH;
            };
          };
        };
    };
    union {
        __IO uint32_t EPFR15;
        stc_gpio_epfr15_field_t EPFR15_f;
        struct {
          union {
            __IO uint16_t EPFR15L;
            struct {
              __IO uint8_t EPFR15LL;
              __IO uint8_t EPFR15LH;
            };
          };
          union {
            __IO uint16_t EPFR15H;
            struct {
              __IO uint8_t EPFR15HL;
              __IO uint8_t EPFR15HH;
            };
          };
        };
    };
    union {
        __IO uint32_t EPFR16;
        stc_gpio_epfr16_field_t EPFR16_f;
        struct {
          union {
            __IO uint16_t EPFR16L;
            struct {
              __IO uint8_t EPFR16LL;
              __IO uint8_t EPFR16LH;
            };
          };
          union {
            __IO uint16_t EPFR16H;
            struct {
              __IO uint8_t EPFR16HL;
              __IO uint8_t EPFR16HH;
            };
          };
        };
    };
    union {
        __IO uint32_t EPFR17;
        stc_gpio_epfr17_field_t EPFR17_f;
        struct {
          union {
            __IO uint16_t EPFR17L;
            struct {
              __IO uint8_t EPFR17LL;
              __IO uint8_t EPFR17LH;
            };
          };
          union {
            __IO uint16_t EPFR17H;
            struct {
              __IO uint8_t EPFR17HL;
              __IO uint8_t EPFR17HH;
            };
          };
        };
    };
    union {
        __IO uint32_t EPFR18;
        stc_gpio_epfr18_field_t EPFR18_f;
        struct {
          union {
            __IO uint16_t EPFR18L;
            struct {
              __IO uint8_t EPFR18LL;
              __IO uint8_t EPFR18LH;
            };
          };
          union {
            __IO uint16_t EPFR18H;
            struct {
              __IO uint8_t EPFR18HL;
              __IO uint8_t EPFR18HH;
            };
          };
        };
    };
    union {
        __IO uint32_t EPFR19;
        struct {
          union {
            __IO uint16_t EPFR19L;
            struct {
              __IO uint8_t EPFR19LL;
              __IO uint8_t EPFR19LH;
            };
          };
          union {
            __IO uint16_t EPFR19H;
            struct {
              __IO uint8_t EPFR19HL;
              __IO uint8_t EPFR19HH;
            };
          };
        };
    };
    union {
        __IO uint32_t EPFR20;
        stc_gpio_epfr20_field_t EPFR20_f;
        struct {
          union {
            __IO uint16_t EPFR20L;
            struct {
              __IO uint8_t EPFR20LL;
              __IO uint8_t EPFR20LH;
            };
          };
          union {
            __IO uint16_t EPFR20H;
            struct {
              __IO uint8_t EPFR20HL;
              __IO uint8_t EPFR20HH;
            };
          };
        };
    };
    union {
        __IO uint32_t EPFR21;
        struct {
          union {
            __IO uint16_t EPFR21L;
            struct {
              __IO uint8_t EPFR21LL;
              __IO uint8_t EPFR21LH;
            };
          };
          union {
            __IO uint16_t EPFR21H;
            struct {
              __IO uint8_t EPFR21HL;
              __IO uint8_t EPFR21HH;
            };
          };
        };
    };
    union {
        __IO uint32_t EPFR22;
        struct {
          union {
            __IO uint16_t EPFR22L;
            struct {
              __IO uint8_t EPFR22LL;
              __IO uint8_t EPFR22LH;
            };
          };
          union {
            __IO uint16_t EPFR22H;
            struct {
              __IO uint8_t EPFR22HL;
              __IO uint8_t EPFR22HH;
            };
          };
        };
    };
    union {
        __IO uint32_t EPFR23;
        stc_gpio_epfr23_field_t EPFR23_f;
        struct {
          union {
            __IO uint16_t EPFR23L;
            struct {
              __IO uint8_t EPFR23LL;
              __IO uint8_t EPFR23LH;
            };
          };
          union {
            __IO uint16_t EPFR23H;
            struct {
              __IO uint8_t EPFR23HL;
              __IO uint8_t EPFR23HH;
            };
          };
        };
    };
    union {
        __IO uint32_t EPFR24;
        stc_gpio_epfr24_field_t EPFR24_f;
        struct {
          union {
            __IO uint16_t EPFR24L;
            struct {
              __IO uint8_t EPFR24LL;
              __IO uint8_t EPFR24LH;
            };
          };
          union {
            __IO uint16_t EPFR24H;
            struct {
              __IO uint8_t EPFR24HL;
              __IO uint8_t EPFR24HH;
            };
          };
        };
    };
    union {
        __IO uint32_t EPFR25;
        stc_gpio_epfr25_field_t EPFR25_f;
        struct {
          union {
            __IO uint16_t EPFR25L;
            struct {
              __IO uint8_t EPFR25LL;
              __IO uint8_t EPFR25LH;
            };
          };
          union {
            __IO uint16_t EPFR25H;
            struct {
              __IO uint8_t EPFR25HL;
              __IO uint8_t EPFR25HH;
            };
          };
        };
    };
    union {
        __IO uint32_t EPFR26;
        stc_gpio_epfr26_field_t EPFR26_f;
        struct {
          union {
            __IO uint16_t EPFR26L;
            struct {
              __IO uint8_t EPFR26LL;
              __IO uint8_t EPFR26LH;
            };
          };
          union {
            __IO uint16_t EPFR26H;
            struct {
              __IO uint8_t EPFR26HL;
              __IO uint8_t EPFR26HH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED8[148];
    union {
        __IO uint32_t PZR0;
        stc_gpio_pzr0_field_t PZR0_f;
        struct {
          union {
            __IO uint16_t PZR0L;
            struct {
              __IO uint8_t PZR0LL;
              __IO uint8_t PZR0LH;
            };
          };
          union {
            __IO uint16_t PZR0H;
            struct {
              __IO uint8_t PZR0HL;
              __IO uint8_t PZR0HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PZR1;
        stc_gpio_pzr1_field_t PZR1_f;
        struct {
          union {
            __IO uint16_t PZR1L;
            struct {
              __IO uint8_t PZR1LL;
              __IO uint8_t PZR1LH;
            };
          };
          union {
            __IO uint16_t PZR1H;
            struct {
              __IO uint8_t PZR1HL;
              __IO uint8_t PZR1HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PZR2;
        stc_gpio_pzr2_field_t PZR2_f;
        struct {
          union {
            __IO uint16_t PZR2L;
            struct {
              __IO uint8_t PZR2LL;
              __IO uint8_t PZR2LH;
            };
          };
          union {
            __IO uint16_t PZR2H;
            struct {
              __IO uint8_t PZR2HL;
              __IO uint8_t PZR2HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PZR3;
        stc_gpio_pzr3_field_t PZR3_f;
        struct {
          union {
            __IO uint16_t PZR3L;
            struct {
              __IO uint8_t PZR3LL;
              __IO uint8_t PZR3LH;
            };
          };
          union {
            __IO uint16_t PZR3H;
            struct {
              __IO uint8_t PZR3HL;
              __IO uint8_t PZR3HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PZR4;
        stc_gpio_pzr4_field_t PZR4_f;
        struct {
          union {
            __IO uint16_t PZR4L;
            struct {
              __IO uint8_t PZR4LL;
              __IO uint8_t PZR4LH;
            };
          };
          union {
            __IO uint16_t PZR4H;
            struct {
              __IO uint8_t PZR4HL;
              __IO uint8_t PZR4HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PZR5;
        stc_gpio_pzr5_field_t PZR5_f;
        struct {
          union {
            __IO uint16_t PZR5L;
            struct {
              __IO uint8_t PZR5LL;
              __IO uint8_t PZR5LH;
            };
          };
          union {
            __IO uint16_t PZR5H;
            struct {
              __IO uint8_t PZR5HL;
              __IO uint8_t PZR5HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PZR6;
        stc_gpio_pzr6_field_t PZR6_f;
        struct {
          union {
            __IO uint16_t PZR6L;
            struct {
              __IO uint8_t PZR6LL;
              __IO uint8_t PZR6LH;
            };
          };
          union {
            __IO uint16_t PZR6H;
            struct {
              __IO uint8_t PZR6HL;
              __IO uint8_t PZR6HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PZR7;
        stc_gpio_pzr7_field_t PZR7_f;
        struct {
          union {
            __IO uint16_t PZR7L;
            struct {
              __IO uint8_t PZR7LL;
              __IO uint8_t PZR7LH;
            };
          };
          union {
            __IO uint16_t PZR7H;
            struct {
              __IO uint8_t PZR7HL;
              __IO uint8_t PZR7HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PZR8;
        stc_gpio_pzr8_field_t PZR8_f;
        struct {
          union {
            __IO uint16_t PZR8L;
            struct {
              __IO uint8_t PZR8LL;
              __IO uint8_t PZR8LH;
            };
          };
          union {
            __IO uint16_t PZR8H;
            struct {
              __IO uint8_t PZR8HL;
              __IO uint8_t PZR8HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PZR9;
        stc_gpio_pzr9_field_t PZR9_f;
        struct {
          union {
            __IO uint16_t PZR9L;
            struct {
              __IO uint8_t PZR9LL;
              __IO uint8_t PZR9LH;
            };
          };
          union {
            __IO uint16_t PZR9H;
            struct {
              __IO uint8_t PZR9HL;
              __IO uint8_t PZR9HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PZRA;
        stc_gpio_pzra_field_t PZRA_f;
        struct {
          union {
            __IO uint16_t PZRAL;
            struct {
              __IO uint8_t PZRALL;
              __IO uint8_t PZRALH;
            };
          };
          union {
            __IO uint16_t PZRAH;
            struct {
              __IO uint8_t PZRAHL;
              __IO uint8_t PZRAHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PZRB;
        stc_gpio_pzrb_field_t PZRB_f;
        struct {
          union {
            __IO uint16_t PZRBL;
            struct {
              __IO uint8_t PZRBLL;
              __IO uint8_t PZRBLH;
            };
          };
          union {
            __IO uint16_t PZRBH;
            struct {
              __IO uint8_t PZRBHL;
              __IO uint8_t PZRBHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PZRC;
        stc_gpio_pzrc_field_t PZRC_f;
        struct {
          union {
            __IO uint16_t PZRCL;
            struct {
              __IO uint8_t PZRCLL;
              __IO uint8_t PZRCLH;
            };
          };
          union {
            __IO uint16_t PZRCH;
            struct {
              __IO uint8_t PZRCHL;
              __IO uint8_t PZRCHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PZRD;
        stc_gpio_pzrd_field_t PZRD_f;
        struct {
          union {
            __IO uint16_t PZRDL;
            struct {
              __IO uint8_t PZRDLL;
              __IO uint8_t PZRDLH;
            };
          };
          union {
            __IO uint16_t PZRDH;
            struct {
              __IO uint8_t PZRDHL;
              __IO uint8_t PZRDHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PZRE;
        stc_gpio_pzre_field_t PZRE_f;
        struct {
          union {
            __IO uint16_t PZREL;
            struct {
              __IO uint8_t PZRELL;
              __IO uint8_t PZRELH;
            };
          };
          union {
            __IO uint16_t PZREH;
            struct {
              __IO uint8_t PZREHL;
              __IO uint8_t PZREHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PZRF;
        stc_gpio_pzrf_field_t PZRF_f;
        struct {
          union {
            __IO uint16_t PZRFL;
            struct {
              __IO uint8_t PZRFLL;
              __IO uint8_t PZRFLH;
            };
          };
          union {
            __IO uint16_t PZRFH;
            struct {
              __IO uint8_t PZRFHL;
              __IO uint8_t PZRFHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDSR0;
        stc_gpio_pdsr0_field_t PDSR0_f;
        struct {
          union {
            __IO uint16_t PDSR0L;
            struct {
              __IO uint8_t PDSR0LL;
              __IO uint8_t PDSR0LH;
            };
          };
          union {
            __IO uint16_t PDSR0H;
            struct {
              __IO uint8_t PDSR0HL;
              __IO uint8_t PDSR0HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDSR1;
        stc_gpio_pdsr1_field_t PDSR1_f;
        struct {
          union {
            __IO uint16_t PDSR1L;
            struct {
              __IO uint8_t PDSR1LL;
              __IO uint8_t PDSR1LH;
            };
          };
          union {
            __IO uint16_t PDSR1H;
            struct {
              __IO uint8_t PDSR1HL;
              __IO uint8_t PDSR1HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDSR2;
        stc_gpio_pdsr2_field_t PDSR2_f;
        struct {
          union {
            __IO uint16_t PDSR2L;
            struct {
              __IO uint8_t PDSR2LL;
              __IO uint8_t PDSR2LH;
            };
          };
          union {
            __IO uint16_t PDSR2H;
            struct {
              __IO uint8_t PDSR2HL;
              __IO uint8_t PDSR2HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDSR3;
        stc_gpio_pdsr3_field_t PDSR3_f;
        struct {
          union {
            __IO uint16_t PDSR3L;
            struct {
              __IO uint8_t PDSR3LL;
              __IO uint8_t PDSR3LH;
            };
          };
          union {
            __IO uint16_t PDSR3H;
            struct {
              __IO uint8_t PDSR3HL;
              __IO uint8_t PDSR3HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDSR4;
        stc_gpio_pdsr4_field_t PDSR4_f;
        struct {
          union {
            __IO uint16_t PDSR4L;
            struct {
              __IO uint8_t PDSR4LL;
              __IO uint8_t PDSR4LH;
            };
          };
          union {
            __IO uint16_t PDSR4H;
            struct {
              __IO uint8_t PDSR4HL;
              __IO uint8_t PDSR4HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDSR5;
        stc_gpio_pdsr5_field_t PDSR5_f;
        struct {
          union {
            __IO uint16_t PDSR5L;
            struct {
              __IO uint8_t PDSR5LL;
              __IO uint8_t PDSR5LH;
            };
          };
          union {
            __IO uint16_t PDSR5H;
            struct {
              __IO uint8_t PDSR5HL;
              __IO uint8_t PDSR5HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDSR6;
        stc_gpio_pdsr6_field_t PDSR6_f;
        struct {
          union {
            __IO uint16_t PDSR6L;
            struct {
              __IO uint8_t PDSR6LL;
              __IO uint8_t PDSR6LH;
            };
          };
          union {
            __IO uint16_t PDSR6H;
            struct {
              __IO uint8_t PDSR6HL;
              __IO uint8_t PDSR6HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDSR7;
        stc_gpio_pdsr7_field_t PDSR7_f;
        struct {
          union {
            __IO uint16_t PDSR7L;
            struct {
              __IO uint8_t PDSR7LL;
              __IO uint8_t PDSR7LH;
            };
          };
          union {
            __IO uint16_t PDSR7H;
            struct {
              __IO uint8_t PDSR7HL;
              __IO uint8_t PDSR7HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDSR8;
        stc_gpio_pdsr8_field_t PDSR8_f;
        struct {
          union {
            __IO uint16_t PDSR8L;
            struct {
              __IO uint8_t PDSR8LL;
              __IO uint8_t PDSR8LH;
            };
          };
          union {
            __IO uint16_t PDSR8H;
            struct {
              __IO uint8_t PDSR8HL;
              __IO uint8_t PDSR8HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDSR9;
        stc_gpio_pdsr9_field_t PDSR9_f;
        struct {
          union {
            __IO uint16_t PDSR9L;
            struct {
              __IO uint8_t PDSR9LL;
              __IO uint8_t PDSR9LH;
            };
          };
          union {
            __IO uint16_t PDSR9H;
            struct {
              __IO uint8_t PDSR9HL;
              __IO uint8_t PDSR9HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDSRA;
        stc_gpio_pdsra_field_t PDSRA_f;
        struct {
          union {
            __IO uint16_t PDSRAL;
            struct {
              __IO uint8_t PDSRALL;
              __IO uint8_t PDSRALH;
            };
          };
          union {
            __IO uint16_t PDSRAH;
            struct {
              __IO uint8_t PDSRAHL;
              __IO uint8_t PDSRAHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDSRB;
        stc_gpio_pdsrb_field_t PDSRB_f;
        struct {
          union {
            __IO uint16_t PDSRBL;
            struct {
              __IO uint8_t PDSRBLL;
              __IO uint8_t PDSRBLH;
            };
          };
          union {
            __IO uint16_t PDSRBH;
            struct {
              __IO uint8_t PDSRBHL;
              __IO uint8_t PDSRBHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDSRC;
        stc_gpio_pdsrc_field_t PDSRC_f;
        struct {
          union {
            __IO uint16_t PDSRCL;
            struct {
              __IO uint8_t PDSRCLL;
              __IO uint8_t PDSRCLH;
            };
          };
          union {
            __IO uint16_t PDSRCH;
            struct {
              __IO uint8_t PDSRCHL;
              __IO uint8_t PDSRCHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDSRD;
        stc_gpio_pdsrd_field_t PDSRD_f;
        struct {
          union {
            __IO uint16_t PDSRDL;
            struct {
              __IO uint8_t PDSRDLL;
              __IO uint8_t PDSRDLH;
            };
          };
          union {
            __IO uint16_t PDSRDH;
            struct {
              __IO uint8_t PDSRDHL;
              __IO uint8_t PDSRDHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDSRE;
        stc_gpio_pdsre_field_t PDSRE_f;
        struct {
          union {
            __IO uint16_t PDSREL;
            struct {
              __IO uint8_t PDSRELL;
              __IO uint8_t PDSRELH;
            };
          };
          union {
            __IO uint16_t PDSREH;
            struct {
              __IO uint8_t PDSREHL;
              __IO uint8_t PDSREHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PDSRF;
        stc_gpio_pdsrf_field_t PDSRF_f;
        struct {
          union {
            __IO uint16_t PDSRFL;
            struct {
              __IO uint8_t PDSRFLL;
              __IO uint8_t PDSRFLH;
            };
          };
          union {
            __IO uint16_t PDSRFH;
            struct {
              __IO uint8_t PDSRFHL;
              __IO uint8_t PDSRFHH;
            };
          };
        };
    };
} FM_GPIO_TypeDef, FM4_GPIO_TypeDef;

/*******************************************************************************
* HSSPI_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO uint32_t MCTRL;
        stc_hsspi_mctrl_field_t MCTRL_f;
        struct {
          union {
            __IO uint16_t MCTRLL;
            struct {
              __IO uint8_t MCTRLLL;
              __IO uint8_t MCTRLLH;
            };
          };
          union {
            __IO uint16_t MCTRLH;
            struct {
              __IO uint8_t MCTRLHL;
              __IO uint8_t MCTRLHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PCC0;
        stc_hsspi_pcc0_field_t PCC0_f;
        struct {
          union {
            __IO uint16_t PCC0L;
            struct {
              __IO uint8_t PCC0LL;
              __IO uint8_t PCC0LH;
            };
          };
          union {
            __IO uint16_t PCC0H;
            struct {
              __IO uint8_t PCC0HL;
              __IO uint8_t PCC0HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PCC1;
        stc_hsspi_pcc1_field_t PCC1_f;
        struct {
          union {
            __IO uint16_t PCC1L;
            struct {
              __IO uint8_t PCC1LL;
              __IO uint8_t PCC1LH;
            };
          };
          union {
            __IO uint16_t PCC1H;
            struct {
              __IO uint8_t PCC1HL;
              __IO uint8_t PCC1HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PCC2;
        stc_hsspi_pcc2_field_t PCC2_f;
        struct {
          union {
            __IO uint16_t PCC2L;
            struct {
              __IO uint8_t PCC2LL;
              __IO uint8_t PCC2LH;
            };
          };
          union {
            __IO uint16_t PCC2H;
            struct {
              __IO uint8_t PCC2HL;
              __IO uint8_t PCC2HH;
            };
          };
        };
    };
    union {
        __IO uint32_t PCC3;
        stc_hsspi_pcc3_field_t PCC3_f;
        struct {
          union {
            __IO uint16_t PCC3L;
            struct {
              __IO uint8_t PCC3LL;
              __IO uint8_t PCC3LH;
            };
          };
          union {
            __IO uint16_t PCC3H;
            struct {
              __IO uint8_t PCC3HL;
              __IO uint8_t PCC3HH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXF;
        stc_hsspi_txf_field_t TXF_f;
        struct {
          union {
            __IO uint16_t TXFL;
            struct {
              __IO uint8_t TXFLL;
              __IO uint8_t TXFLH;
            };
          };
          union {
            __IO uint16_t TXFH;
            struct {
              __IO uint8_t TXFHL;
              __IO uint8_t TXFHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXE;
        stc_hsspi_txe_field_t TXE_f;
        struct {
          union {
            __IO uint16_t TXEL;
            struct {
              __IO uint8_t TXELL;
              __IO uint8_t TXELH;
            };
          };
          union {
            __IO uint16_t TXEH;
            struct {
              __IO uint8_t TXEHL;
              __IO uint8_t TXEHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXC;
        stc_hsspi_txc_field_t TXC_f;
        struct {
          union {
            __IO uint16_t TXCL;
            struct {
              __IO uint8_t TXCLL;
              __IO uint8_t TXCLH;
            };
          };
          union {
            __IO uint16_t TXCH;
            struct {
              __IO uint8_t TXCHL;
              __IO uint8_t TXCHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXF;
        stc_hsspi_rxf_field_t RXF_f;
        struct {
          union {
            __IO uint16_t RXFL;
            struct {
              __IO uint8_t RXFLL;
              __IO uint8_t RXFLH;
            };
          };
          union {
            __IO uint16_t RXFH;
            struct {
              __IO uint8_t RXFHL;
              __IO uint8_t RXFHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXE;
        stc_hsspi_rxe_field_t RXE_f;
        struct {
          union {
            __IO uint16_t RXEL;
            struct {
              __IO uint8_t RXELL;
              __IO uint8_t RXELH;
            };
          };
          union {
            __IO uint16_t RXEH;
            struct {
              __IO uint8_t RXEHL;
              __IO uint8_t RXEHH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXC;
        stc_hsspi_rxc_field_t RXC_f;
        struct {
          union {
            __IO uint16_t RXCL;
            struct {
              __IO uint8_t RXCLL;
              __IO uint8_t RXCLH;
            };
          };
          union {
            __IO uint16_t RXCH;
            struct {
              __IO uint8_t RXCHL;
              __IO uint8_t RXCHH;
            };
          };
        };
    };
    union {
        __IO uint32_t FAULTF;
        stc_hsspi_faultf_field_t FAULTF_f;
        struct {
          union {
            __IO uint16_t FAULTFL;
            struct {
              __IO uint8_t FAULTFLL;
              __IO uint8_t FAULTFLH;
            };
          };
          union {
            __IO uint16_t FAULTFH;
            struct {
              __IO uint8_t FAULTFHL;
              __IO uint8_t FAULTFHH;
            };
          };
        };
    };
    union {
        __IO uint32_t FAULTC;
        stc_hsspi_faultc_field_t FAULTC_f;
        struct {
          union {
            __IO uint16_t FAULTCL;
            struct {
              __IO uint8_t FAULTCLL;
              __IO uint8_t FAULTCLH;
            };
          };
          union {
            __IO uint16_t FAULTCH;
            struct {
              __IO uint8_t FAULTCHL;
              __IO uint8_t FAULTCHH;
            };
          };
        };
    };
    union {
        __IO  uint8_t DMCFG;
        stc_hsspi_dmcfg_field_t DMCFG_f;
    };
    union {
        __IO  uint8_t DMDMAEN;
        stc_hsspi_dmdmaen_field_t DMDMAEN_f;
    };
        __IO  uint8_t RESERVED0[2];
    union {
        __IO  uint8_t DMSTART;
        stc_hsspi_dmstart_field_t DMSTART_f;
    };
    union {
        __IO  uint8_t DMSTOP;
        stc_hsspi_dmstop_field_t DMSTOP_f;
    };
    union {
        __IO  uint8_t DMPSEL;
        stc_hsspi_dmpsel_field_t DMPSEL_f;
    };
    union {
        __IO  uint8_t DMTRP;
        stc_hsspi_dmtrp_field_t DMTRP_f;
    };
    union {
        __IO uint16_t DMBCC;
        stc_hsspi_dmbcc_field_t DMBCC_f;
        struct {
            __IO  uint8_t DMBCCL;
            __IO  uint8_t DMBCCH;
        };
    };
    union {
        __IO uint16_t DMBCS;
        stc_hsspi_dmbcs_field_t DMBCS_f;
        struct {
            __IO  uint8_t DMBCSL;
            __IO  uint8_t DMBCSH;
        };
    };
    union {
        __IO uint32_t DMSTATUS;
        stc_hsspi_dmstatus_field_t DMSTATUS_f;
        struct {
          union {
            __IO uint16_t DMSTATUSL;
            struct {
              __IO uint8_t DMSTATUSLL;
              __IO uint8_t DMSTATUSLH;
            };
          };
          union {
            __IO uint16_t DMSTATUSH;
            struct {
              __IO uint8_t DMSTATUSHL;
              __IO uint8_t DMSTATUSHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED1[8];
    union {
        __IO uint32_t FIFOCFG;
        stc_hsspi_fifocfg_field_t FIFOCFG_f;
        struct {
          union {
            __IO uint16_t FIFOCFGL;
            struct {
              __IO uint8_t FIFOCFGLL;
              __IO uint8_t FIFOCFGLH;
            };
          };
          union {
            __IO uint16_t FIFOCFGH;
            struct {
              __IO uint8_t FIFOCFGHL;
              __IO uint8_t FIFOCFGHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXFIFO0;
        stc_hsspi_txfifo0_field_t TXFIFO0_f;
        struct {
          union {
            __IO uint16_t TXFIFO0L;
            struct {
              __IO uint8_t TXFIFO0LL;
              __IO uint8_t TXFIFO0LH;
            };
          };
          union {
            __IO uint16_t TXFIFO0H;
            struct {
              __IO uint8_t TXFIFO0HL;
              __IO uint8_t TXFIFO0HH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXFIFO1;
        stc_hsspi_txfifo1_field_t TXFIFO1_f;
        struct {
          union {
            __IO uint16_t TXFIFO1L;
            struct {
              __IO uint8_t TXFIFO1LL;
              __IO uint8_t TXFIFO1LH;
            };
          };
          union {
            __IO uint16_t TXFIFO1H;
            struct {
              __IO uint8_t TXFIFO1HL;
              __IO uint8_t TXFIFO1HH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXFIFO2;
        stc_hsspi_txfifo2_field_t TXFIFO2_f;
        struct {
          union {
            __IO uint16_t TXFIFO2L;
            struct {
              __IO uint8_t TXFIFO2LL;
              __IO uint8_t TXFIFO2LH;
            };
          };
          union {
            __IO uint16_t TXFIFO2H;
            struct {
              __IO uint8_t TXFIFO2HL;
              __IO uint8_t TXFIFO2HH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXFIFO3;
        stc_hsspi_txfifo3_field_t TXFIFO3_f;
        struct {
          union {
            __IO uint16_t TXFIFO3L;
            struct {
              __IO uint8_t TXFIFO3LL;
              __IO uint8_t TXFIFO3LH;
            };
          };
          union {
            __IO uint16_t TXFIFO3H;
            struct {
              __IO uint8_t TXFIFO3HL;
              __IO uint8_t TXFIFO3HH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXFIFO4;
        stc_hsspi_txfifo4_field_t TXFIFO4_f;
        struct {
          union {
            __IO uint16_t TXFIFO4L;
            struct {
              __IO uint8_t TXFIFO4LL;
              __IO uint8_t TXFIFO4LH;
            };
          };
          union {
            __IO uint16_t TXFIFO4H;
            struct {
              __IO uint8_t TXFIFO4HL;
              __IO uint8_t TXFIFO4HH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXFIFO5;
        stc_hsspi_txfifo5_field_t TXFIFO5_f;
        struct {
          union {
            __IO uint16_t TXFIFO5L;
            struct {
              __IO uint8_t TXFIFO5LL;
              __IO uint8_t TXFIFO5LH;
            };
          };
          union {
            __IO uint16_t TXFIFO5H;
            struct {
              __IO uint8_t TXFIFO5HL;
              __IO uint8_t TXFIFO5HH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXFIFO6;
        stc_hsspi_txfifo6_field_t TXFIFO6_f;
        struct {
          union {
            __IO uint16_t TXFIFO6L;
            struct {
              __IO uint8_t TXFIFO6LL;
              __IO uint8_t TXFIFO6LH;
            };
          };
          union {
            __IO uint16_t TXFIFO6H;
            struct {
              __IO uint8_t TXFIFO6HL;
              __IO uint8_t TXFIFO6HH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXFIFO7;
        stc_hsspi_txfifo7_field_t TXFIFO7_f;
        struct {
          union {
            __IO uint16_t TXFIFO7L;
            struct {
              __IO uint8_t TXFIFO7LL;
              __IO uint8_t TXFIFO7LH;
            };
          };
          union {
            __IO uint16_t TXFIFO7H;
            struct {
              __IO uint8_t TXFIFO7HL;
              __IO uint8_t TXFIFO7HH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXFIFO8;
        stc_hsspi_txfifo8_field_t TXFIFO8_f;
        struct {
          union {
            __IO uint16_t TXFIFO8L;
            struct {
              __IO uint8_t TXFIFO8LL;
              __IO uint8_t TXFIFO8LH;
            };
          };
          union {
            __IO uint16_t TXFIFO8H;
            struct {
              __IO uint8_t TXFIFO8HL;
              __IO uint8_t TXFIFO8HH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXFIFO9;
        stc_hsspi_txfifo9_field_t TXFIFO9_f;
        struct {
          union {
            __IO uint16_t TXFIFO9L;
            struct {
              __IO uint8_t TXFIFO9LL;
              __IO uint8_t TXFIFO9LH;
            };
          };
          union {
            __IO uint16_t TXFIFO9H;
            struct {
              __IO uint8_t TXFIFO9HL;
              __IO uint8_t TXFIFO9HH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXFIFO10;
        stc_hsspi_txfifo10_field_t TXFIFO10_f;
        struct {
          union {
            __IO uint16_t TXFIFO10L;
            struct {
              __IO uint8_t TXFIFO10LL;
              __IO uint8_t TXFIFO10LH;
            };
          };
          union {
            __IO uint16_t TXFIFO10H;
            struct {
              __IO uint8_t TXFIFO10HL;
              __IO uint8_t TXFIFO10HH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXFIFO11;
        stc_hsspi_txfifo11_field_t TXFIFO11_f;
        struct {
          union {
            __IO uint16_t TXFIFO11L;
            struct {
              __IO uint8_t TXFIFO11LL;
              __IO uint8_t TXFIFO11LH;
            };
          };
          union {
            __IO uint16_t TXFIFO11H;
            struct {
              __IO uint8_t TXFIFO11HL;
              __IO uint8_t TXFIFO11HH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXFIFO12;
        stc_hsspi_txfifo12_field_t TXFIFO12_f;
        struct {
          union {
            __IO uint16_t TXFIFO12L;
            struct {
              __IO uint8_t TXFIFO12LL;
              __IO uint8_t TXFIFO12LH;
            };
          };
          union {
            __IO uint16_t TXFIFO12H;
            struct {
              __IO uint8_t TXFIFO12HL;
              __IO uint8_t TXFIFO12HH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXFIFO13;
        stc_hsspi_txfifo13_field_t TXFIFO13_f;
        struct {
          union {
            __IO uint16_t TXFIFO13L;
            struct {
              __IO uint8_t TXFIFO13LL;
              __IO uint8_t TXFIFO13LH;
            };
          };
          union {
            __IO uint16_t TXFIFO13H;
            struct {
              __IO uint8_t TXFIFO13HL;
              __IO uint8_t TXFIFO13HH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXFIFO14;
        stc_hsspi_txfifo14_field_t TXFIFO14_f;
        struct {
          union {
            __IO uint16_t TXFIFO14L;
            struct {
              __IO uint8_t TXFIFO14LL;
              __IO uint8_t TXFIFO14LH;
            };
          };
          union {
            __IO uint16_t TXFIFO14H;
            struct {
              __IO uint8_t TXFIFO14HL;
              __IO uint8_t TXFIFO14HH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXFIFO15;
        stc_hsspi_txfifo15_field_t TXFIFO15_f;
        struct {
          union {
            __IO uint16_t TXFIFO15L;
            struct {
              __IO uint8_t TXFIFO15LL;
              __IO uint8_t TXFIFO15LH;
            };
          };
          union {
            __IO uint16_t TXFIFO15H;
            struct {
              __IO uint8_t TXFIFO15HL;
              __IO uint8_t TXFIFO15HH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXFIFO0;
        stc_hsspi_rxfifo0_field_t RXFIFO0_f;
        struct {
          union {
            __IO uint16_t RXFIFO0L;
            struct {
              __IO uint8_t RXFIFO0LL;
              __IO uint8_t RXFIFO0LH;
            };
          };
          union {
            __IO uint16_t RXFIFO0H;
            struct {
              __IO uint8_t RXFIFO0HL;
              __IO uint8_t RXFIFO0HH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXFIFO1;
        stc_hsspi_rxfifo1_field_t RXFIFO1_f;
        struct {
          union {
            __IO uint16_t RXFIFO1L;
            struct {
              __IO uint8_t RXFIFO1LL;
              __IO uint8_t RXFIFO1LH;
            };
          };
          union {
            __IO uint16_t RXFIFO1H;
            struct {
              __IO uint8_t RXFIFO1HL;
              __IO uint8_t RXFIFO1HH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXFIFO2;
        stc_hsspi_rxfifo2_field_t RXFIFO2_f;
        struct {
          union {
            __IO uint16_t RXFIFO2L;
            struct {
              __IO uint8_t RXFIFO2LL;
              __IO uint8_t RXFIFO2LH;
            };
          };
          union {
            __IO uint16_t RXFIFO2H;
            struct {
              __IO uint8_t RXFIFO2HL;
              __IO uint8_t RXFIFO2HH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXFIFO3;
        stc_hsspi_rxfifo3_field_t RXFIFO3_f;
        struct {
          union {
            __IO uint16_t RXFIFO3L;
            struct {
              __IO uint8_t RXFIFO3LL;
              __IO uint8_t RXFIFO3LH;
            };
          };
          union {
            __IO uint16_t RXFIFO3H;
            struct {
              __IO uint8_t RXFIFO3HL;
              __IO uint8_t RXFIFO3HH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXFIFO4;
        stc_hsspi_rxfifo4_field_t RXFIFO4_f;
        struct {
          union {
            __IO uint16_t RXFIFO4L;
            struct {
              __IO uint8_t RXFIFO4LL;
              __IO uint8_t RXFIFO4LH;
            };
          };
          union {
            __IO uint16_t RXFIFO4H;
            struct {
              __IO uint8_t RXFIFO4HL;
              __IO uint8_t RXFIFO4HH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXFIFO5;
        stc_hsspi_rxfifo5_field_t RXFIFO5_f;
        struct {
          union {
            __IO uint16_t RXFIFO5L;
            struct {
              __IO uint8_t RXFIFO5LL;
              __IO uint8_t RXFIFO5LH;
            };
          };
          union {
            __IO uint16_t RXFIFO5H;
            struct {
              __IO uint8_t RXFIFO5HL;
              __IO uint8_t RXFIFO5HH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXFIFO6;
        stc_hsspi_rxfifo6_field_t RXFIFO6_f;
        struct {
          union {
            __IO uint16_t RXFIFO6L;
            struct {
              __IO uint8_t RXFIFO6LL;
              __IO uint8_t RXFIFO6LH;
            };
          };
          union {
            __IO uint16_t RXFIFO6H;
            struct {
              __IO uint8_t RXFIFO6HL;
              __IO uint8_t RXFIFO6HH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXFIFO7;
        stc_hsspi_rxfifo7_field_t RXFIFO7_f;
        struct {
          union {
            __IO uint16_t RXFIFO7L;
            struct {
              __IO uint8_t RXFIFO7LL;
              __IO uint8_t RXFIFO7LH;
            };
          };
          union {
            __IO uint16_t RXFIFO7H;
            struct {
              __IO uint8_t RXFIFO7HL;
              __IO uint8_t RXFIFO7HH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXFIFO8;
        stc_hsspi_rxfifo8_field_t RXFIFO8_f;
        struct {
          union {
            __IO uint16_t RXFIFO8L;
            struct {
              __IO uint8_t RXFIFO8LL;
              __IO uint8_t RXFIFO8LH;
            };
          };
          union {
            __IO uint16_t RXFIFO8H;
            struct {
              __IO uint8_t RXFIFO8HL;
              __IO uint8_t RXFIFO8HH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXFIFO9;
        stc_hsspi_rxfifo9_field_t RXFIFO9_f;
        struct {
          union {
            __IO uint16_t RXFIFO9L;
            struct {
              __IO uint8_t RXFIFO9LL;
              __IO uint8_t RXFIFO9LH;
            };
          };
          union {
            __IO uint16_t RXFIFO9H;
            struct {
              __IO uint8_t RXFIFO9HL;
              __IO uint8_t RXFIFO9HH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXFIFO10;
        stc_hsspi_rxfifo10_field_t RXFIFO10_f;
        struct {
          union {
            __IO uint16_t RXFIFO10L;
            struct {
              __IO uint8_t RXFIFO10LL;
              __IO uint8_t RXFIFO10LH;
            };
          };
          union {
            __IO uint16_t RXFIFO10H;
            struct {
              __IO uint8_t RXFIFO10HL;
              __IO uint8_t RXFIFO10HH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXFIFO11;
        stc_hsspi_rxfifo11_field_t RXFIFO11_f;
        struct {
          union {
            __IO uint16_t RXFIFO11L;
            struct {
              __IO uint8_t RXFIFO11LL;
              __IO uint8_t RXFIFO11LH;
            };
          };
          union {
            __IO uint16_t RXFIFO11H;
            struct {
              __IO uint8_t RXFIFO11HL;
              __IO uint8_t RXFIFO11HH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXFIFO12;
        stc_hsspi_rxfifo12_field_t RXFIFO12_f;
        struct {
          union {
            __IO uint16_t RXFIFO12L;
            struct {
              __IO uint8_t RXFIFO12LL;
              __IO uint8_t RXFIFO12LH;
            };
          };
          union {
            __IO uint16_t RXFIFO12H;
            struct {
              __IO uint8_t RXFIFO12HL;
              __IO uint8_t RXFIFO12HH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXFIFO13;
        stc_hsspi_rxfifo13_field_t RXFIFO13_f;
        struct {
          union {
            __IO uint16_t RXFIFO13L;
            struct {
              __IO uint8_t RXFIFO13LL;
              __IO uint8_t RXFIFO13LH;
            };
          };
          union {
            __IO uint16_t RXFIFO13H;
            struct {
              __IO uint8_t RXFIFO13HL;
              __IO uint8_t RXFIFO13HH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXFIFO14;
        stc_hsspi_rxfifo14_field_t RXFIFO14_f;
        struct {
          union {
            __IO uint16_t RXFIFO14L;
            struct {
              __IO uint8_t RXFIFO14LL;
              __IO uint8_t RXFIFO14LH;
            };
          };
          union {
            __IO uint16_t RXFIFO14H;
            struct {
              __IO uint8_t RXFIFO14HL;
              __IO uint8_t RXFIFO14HH;
            };
          };
        };
    };
    union {
        __IO uint32_t RXFIFO15;
        stc_hsspi_rxfifo15_field_t RXFIFO15_f;
        struct {
          union {
            __IO uint16_t RXFIFO15L;
            struct {
              __IO uint8_t RXFIFO15LL;
              __IO uint8_t RXFIFO15LH;
            };
          };
          union {
            __IO uint16_t RXFIFO15H;
            struct {
              __IO uint8_t RXFIFO15HL;
              __IO uint8_t RXFIFO15HH;
            };
          };
        };
    };
    union {
        __IO uint32_t CSCFG;
        stc_hsspi_cscfg_field_t CSCFG_f;
        struct {
          union {
            __IO uint16_t CSCFGL;
            struct {
              __IO uint8_t CSCFGLL;
              __IO uint8_t CSCFGLH;
            };
          };
          union {
            __IO uint16_t CSCFGH;
            struct {
              __IO uint8_t CSCFGHL;
              __IO uint8_t CSCFGHH;
            };
          };
        };
    };
    union {
        __IO uint32_t CSITIME;
        stc_hsspi_csitime_field_t CSITIME_f;
        struct {
          union {
            __IO uint16_t CSITIMEL;
            struct {
              __IO uint8_t CSITIMELL;
              __IO uint8_t CSITIMELH;
            };
          };
          union {
            __IO uint16_t CSITIMEH;
            struct {
              __IO uint8_t CSITIMEHL;
              __IO uint8_t CSITIMEHH;
            };
          };
        };
    };
    union {
        __IO uint32_t CSAEXT;
        stc_hsspi_csaext_field_t CSAEXT_f;
        struct {
          union {
            __IO uint16_t CSAEXTL;
            struct {
              __IO uint8_t CSAEXTLL;
              __IO uint8_t CSAEXTLH;
            };
          };
          union {
            __IO uint16_t CSAEXTH;
            struct {
              __IO uint8_t CSAEXTHL;
              __IO uint8_t CSAEXTHH;
            };
          };
        };
    };
    union {
        __IO uint16_t RDCSDC0;
        stc_hsspi_rdcsdc0_field_t RDCSDC0_f;
        struct {
            __IO  uint8_t RDCSDC0L;
            __IO  uint8_t RDCSDC0H;
        };
    };
    union {
        __IO uint16_t RDCSDC1;
        stc_hsspi_rdcsdc1_field_t RDCSDC1_f;
        struct {
            __IO  uint8_t RDCSDC1L;
            __IO  uint8_t RDCSDC1H;
        };
    };
    union {
        __IO uint16_t RDCSDC2;
        stc_hsspi_rdcsdc2_field_t RDCSDC2_f;
        struct {
            __IO  uint8_t RDCSDC2L;
            __IO  uint8_t RDCSDC2H;
        };
    };
    union {
        __IO uint16_t RDCSDC3;
        stc_hsspi_rdcsdc3_field_t RDCSDC3_f;
        struct {
            __IO  uint8_t RDCSDC3L;
            __IO  uint8_t RDCSDC3H;
        };
    };
    union {
        __IO uint16_t RDCSDC4;
        stc_hsspi_rdcsdc4_field_t RDCSDC4_f;
        struct {
            __IO  uint8_t RDCSDC4L;
            __IO  uint8_t RDCSDC4H;
        };
    };
    union {
        __IO uint16_t RDCSDC5;
        stc_hsspi_rdcsdc5_field_t RDCSDC5_f;
        struct {
            __IO  uint8_t RDCSDC5L;
            __IO  uint8_t RDCSDC5H;
        };
    };
    union {
        __IO uint16_t RDCSDC6;
        stc_hsspi_rdcsdc6_field_t RDCSDC6_f;
        struct {
            __IO  uint8_t RDCSDC6L;
            __IO  uint8_t RDCSDC6H;
        };
    };
    union {
        __IO uint16_t RDCSDC7;
        stc_hsspi_rdcsdc7_field_t RDCSDC7_f;
        struct {
            __IO  uint8_t RDCSDC7L;
            __IO  uint8_t RDCSDC7H;
        };
    };
    union {
        __IO uint16_t WRCSDC0;
        stc_hsspi_wrcsdc0_field_t WRCSDC0_f;
        struct {
            __IO  uint8_t WRCSDC0L;
            __IO  uint8_t WRCSDC0H;
        };
    };
    union {
        __IO uint16_t WRCSDC1;
        stc_hsspi_wrcsdc1_field_t WRCSDC1_f;
        struct {
            __IO  uint8_t WRCSDC1L;
            __IO  uint8_t WRCSDC1H;
        };
    };
    union {
        __IO uint16_t WRCSDC2;
        stc_hsspi_wrcsdc2_field_t WRCSDC2_f;
        struct {
            __IO  uint8_t WRCSDC2L;
            __IO  uint8_t WRCSDC2H;
        };
    };
    union {
        __IO uint16_t WRCSDC3;
        stc_hsspi_wrcsdc3_field_t WRCSDC3_f;
        struct {
            __IO  uint8_t WRCSDC3L;
            __IO  uint8_t WRCSDC3H;
        };
    };
    union {
        __IO uint16_t WRCSDC4;
        stc_hsspi_wrcsdc4_field_t WRCSDC4_f;
        struct {
            __IO  uint8_t WRCSDC4L;
            __IO  uint8_t WRCSDC4H;
        };
    };
    union {
        __IO uint16_t WRCSDC5;
        stc_hsspi_wrcsdc5_field_t WRCSDC5_f;
        struct {
            __IO  uint8_t WRCSDC5L;
            __IO  uint8_t WRCSDC5H;
        };
    };
    union {
        __IO uint16_t WRCSDC6;
        stc_hsspi_wrcsdc6_field_t WRCSDC6_f;
        struct {
            __IO  uint8_t WRCSDC6L;
            __IO  uint8_t WRCSDC6H;
        };
    };
    union {
        __IO uint16_t WRCSDC7;
        stc_hsspi_wrcsdc7_field_t WRCSDC7_f;
        struct {
            __IO  uint8_t WRCSDC7L;
            __IO  uint8_t WRCSDC7H;
        };
    };
    union {
        __IO uint32_t MID;
        stc_hsspi_mid_field_t MID_f;
        struct {
          union {
            __IO uint16_t MIDL;
            struct {
              __IO uint8_t MIDLL;
              __IO uint8_t MIDLH;
            };
          };
          union {
            __IO uint16_t MIDH;
            struct {
              __IO uint8_t MIDHL;
              __IO uint8_t MIDHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED2[768];
    union {
        __IO  uint8_t QDCLKR;
        stc_hsspi_qdclkr_field_t QDCLKR_f;
    };
        __IO  uint8_t RESERVED3[3];
    union {
        __IO  uint8_t DBCNT;
        stc_hsspi_dbcnt_field_t DBCNT_f;
    };
} FM_HSSPI_TypeDef, FM4_HSSPI_TypeDef;

/*******************************************************************************
* HWWDT_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO uint32_t WDG_LDR;
        struct {
          union {
            __IO uint16_t WDG_LDRL;
            struct {
              __IO uint8_t WDG_LDRLL;
              __IO uint8_t WDG_LDRLH;
            };
          };
          union {
            __IO uint16_t WDG_LDRH;
            struct {
              __IO uint8_t WDG_LDRHL;
              __IO uint8_t WDG_LDRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t WDG_VLR;
        struct {
          union {
            __IO uint16_t WDG_VLRL;
            struct {
              __IO uint8_t WDG_VLRLL;
              __IO uint8_t WDG_VLRLH;
            };
          };
          union {
            __IO uint16_t WDG_VLRH;
            struct {
              __IO uint8_t WDG_VLRHL;
              __IO uint8_t WDG_VLRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t WDG_CTL;
        stc_hwwdt_wdg_ctl_field_t WDG_CTL_f;
        struct {
          union {
            __IO uint16_t WDG_CTLL;
            struct {
              __IO uint8_t WDG_CTLLL;
              __IO uint8_t WDG_CTLLH;
            };
          };
          union {
            __IO uint16_t WDG_CTLH;
            struct {
              __IO uint8_t WDG_CTLHL;
              __IO uint8_t WDG_CTLHH;
            };
          };
        };
    };
    union {
        __IO uint32_t WDG_ICL;
        struct {
          union {
            __IO uint16_t WDG_ICLL;
            struct {
              __IO uint8_t WDG_ICLLL;
              __IO uint8_t WDG_ICLLH;
            };
          };
          union {
            __IO uint16_t WDG_ICLH;
            struct {
              __IO uint8_t WDG_ICLHL;
              __IO uint8_t WDG_ICLHH;
            };
          };
        };
    };
    union {
        __IO uint32_t WDG_RIS;
        stc_hwwdt_wdg_ris_field_t WDG_RIS_f;
        struct {
          union {
            __IO uint16_t WDG_RISL;
            struct {
              __IO uint8_t WDG_RISLL;
              __IO uint8_t WDG_RISLH;
            };
          };
          union {
            __IO uint16_t WDG_RISH;
            struct {
              __IO uint8_t WDG_RISHL;
              __IO uint8_t WDG_RISHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED0[3052];
    union {
        __IO uint32_t WDG_LCK;
        struct {
          union {
            __IO uint16_t WDG_LCKL;
            struct {
              __IO uint8_t WDG_LCKLL;
              __IO uint8_t WDG_LCKLH;
            };
          };
          union {
            __IO uint16_t WDG_LCKH;
            struct {
              __IO uint8_t WDG_LCKHL;
              __IO uint8_t WDG_LCKHH;
            };
          };
        };
    };
} FM_HWWDT_TypeDef, FM4_HWWDT_TypeDef;

/*******************************************************************************
* I2S_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO uint32_t RXFDAT;
        stc_i2s_rxfdat_field_t RXFDAT_f;
        struct {
          union {
            __IO uint16_t RXFDATL;
            struct {
              __IO uint8_t RXFDATLL;
              __IO uint8_t RXFDATLH;
            };
          };
          union {
            __IO uint16_t RXFDATH;
            struct {
              __IO uint8_t RXFDATHL;
              __IO uint8_t RXFDATHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TXFDAT;
        stc_i2s_txfdat_field_t TXFDAT_f;
        struct {
          union {
            __IO uint16_t TXFDATL;
            struct {
              __IO uint8_t TXFDATLL;
              __IO uint8_t TXFDATLH;
            };
          };
          union {
            __IO uint16_t TXFDATH;
            struct {
              __IO uint8_t TXFDATHL;
              __IO uint8_t TXFDATHH;
            };
          };
        };
    };
    union {
        __IO uint32_t CNTREG;
        stc_i2s_cntreg_field_t CNTREG_f;
        struct {
          union {
            __IO uint16_t CNTREGL;
            struct {
              __IO uint8_t CNTREGLL;
              __IO uint8_t CNTREGLH;
            };
          };
          union {
            __IO uint16_t CNTREGH;
            struct {
              __IO uint8_t CNTREGHL;
              __IO uint8_t CNTREGHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MCR0REG;
        stc_i2s_mcr0reg_field_t MCR0REG_f;
        struct {
          union {
            __IO uint16_t MCR0REGL;
            struct {
              __IO uint8_t MCR0REGLL;
              __IO uint8_t MCR0REGLH;
            };
          };
          union {
            __IO uint16_t MCR0REGH;
            struct {
              __IO uint8_t MCR0REGHL;
              __IO uint8_t MCR0REGHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MCR1REG;
        stc_i2s_mcr1reg_field_t MCR1REG_f;
        struct {
          union {
            __IO uint16_t MCR1REGL;
            struct {
              __IO uint8_t MCR1REGLL;
              __IO uint8_t MCR1REGLH;
            };
          };
          union {
            __IO uint16_t MCR1REGH;
            struct {
              __IO uint8_t MCR1REGHL;
              __IO uint8_t MCR1REGHH;
            };
          };
        };
    };
    union {
        __IO uint32_t MCR2REG;
        stc_i2s_mcr2reg_field_t MCR2REG_f;
        struct {
          union {
            __IO uint16_t MCR2REGL;
            struct {
              __IO uint8_t MCR2REGLL;
              __IO uint8_t MCR2REGLH;
            };
          };
          union {
            __IO uint16_t MCR2REGH;
            struct {
              __IO uint8_t MCR2REGHL;
              __IO uint8_t MCR2REGHH;
            };
          };
        };
    };
    union {
        __IO uint32_t OPRREG;
        stc_i2s_oprreg_field_t OPRREG_f;
        struct {
          union {
            __IO uint16_t OPRREGL;
            struct {
              __IO uint8_t OPRREGLL;
              __IO uint8_t OPRREGLH;
            };
          };
          union {
            __IO uint16_t OPRREGH;
            struct {
              __IO uint8_t OPRREGHL;
              __IO uint8_t OPRREGHH;
            };
          };
        };
    };
    union {
        __IO uint32_t SRST;
        stc_i2s_srst_field_t SRST_f;
        struct {
          union {
            __IO uint16_t SRSTL;
            struct {
              __IO uint8_t SRSTLL;
              __IO uint8_t SRSTLH;
            };
          };
          union {
            __IO uint16_t SRSTH;
            struct {
              __IO uint8_t SRSTHL;
              __IO uint8_t SRSTHH;
            };
          };
        };
    };
    union {
        __IO uint32_t INTCNT;
        stc_i2s_intcnt_field_t INTCNT_f;
        struct {
          union {
            __IO uint16_t INTCNTL;
            struct {
              __IO uint8_t INTCNTLL;
              __IO uint8_t INTCNTLH;
            };
          };
          union {
            __IO uint16_t INTCNTH;
            struct {
              __IO uint8_t INTCNTHL;
              __IO uint8_t INTCNTHH;
            };
          };
        };
    };
    union {
        __IO uint32_t STATUS;
        stc_i2s_status_field_t STATUS_f;
        struct {
          union {
            __IO uint16_t STATUSL;
            struct {
              __IO uint8_t STATUSLL;
              __IO uint8_t STATUSLH;
            };
          };
          union {
            __IO uint16_t STATUSH;
            struct {
              __IO uint8_t STATUSHL;
              __IO uint8_t STATUSHH;
            };
          };
        };
    };
    union {
        __IO uint32_t DMAACT;
        stc_i2s_dmaact_field_t DMAACT_f;
        struct {
          union {
            __IO uint16_t DMAACTL;
            struct {
              __IO uint8_t DMAACTLL;
              __IO uint8_t DMAACTLH;
            };
          };
          union {
            __IO uint16_t DMAACTH;
            struct {
              __IO uint8_t DMAACTHL;
              __IO uint8_t DMAACTHH;
            };
          };
        };
    };
    union {
        __IO uint32_t TSTREG;
        stc_i2s_tstreg_field_t TSTREG_f;
        struct {
          union {
            __IO uint16_t TSTREGL;
            struct {
              __IO uint8_t TSTREGLL;
              __IO uint8_t TSTREGLH;
            };
          };
          union {
            __IO uint16_t TSTREGH;
            struct {
              __IO uint8_t TSTREGHL;
              __IO uint8_t TSTREGHH;
            };
          };
        };
    };
} FM_I2S_TypeDef, FM4_I2S_TypeDef;

/*******************************************************************************
* I2SPRE_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO uint32_t ICCR;
        stc_i2spre_iccr_field_t ICCR_f;
        struct {
          union {
            __IO uint16_t ICCRL;
            struct {
              __IO uint8_t ICCRLL;
              __IO uint8_t ICCRLH;
            };
          };
          union {
            __IO uint16_t ICCRH;
            struct {
              __IO uint8_t ICCRHL;
              __IO uint8_t ICCRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IPCR1;
        stc_i2spre_ipcr1_field_t IPCR1_f;
        struct {
          union {
            __IO uint16_t IPCR1L;
            struct {
              __IO uint8_t IPCR1LL;
              __IO uint8_t IPCR1LH;
            };
          };
          union {
            __IO uint16_t IPCR1H;
            struct {
              __IO uint8_t IPCR1HL;
              __IO uint8_t IPCR1HH;
            };
          };
        };
    };
    union {
        __IO uint32_t IPCR2;
        stc_i2spre_ipcr2_field_t IPCR2_f;
        struct {
          union {
            __IO uint16_t IPCR2L;
            struct {
              __IO uint8_t IPCR2LL;
              __IO uint8_t IPCR2LH;
            };
          };
          union {
            __IO uint16_t IPCR2H;
            struct {
              __IO uint8_t IPCR2HL;
              __IO uint8_t IPCR2HH;
            };
          };
        };
    };
    union {
        __IO uint32_t IPCR3;
        stc_i2spre_ipcr3_field_t IPCR3_f;
        struct {
          union {
            __IO uint16_t IPCR3L;
            struct {
              __IO uint8_t IPCR3LL;
              __IO uint8_t IPCR3LH;
            };
          };
          union {
            __IO uint16_t IPCR3H;
            struct {
              __IO uint8_t IPCR3HL;
              __IO uint8_t IPCR3HH;
            };
          };
        };
    };
    union {
        __IO uint32_t IPCR4;
        stc_i2spre_ipcr4_field_t IPCR4_f;
        struct {
          union {
            __IO uint16_t IPCR4L;
            struct {
              __IO uint8_t IPCR4LL;
              __IO uint8_t IPCR4LH;
            };
          };
          union {
            __IO uint16_t IPCR4H;
            struct {
              __IO uint8_t IPCR4HL;
              __IO uint8_t IPCR4HH;
            };
          };
        };
    };
    union {
        __IO uint32_t IP_STR;
        stc_i2spre_ip_str_field_t IP_STR_f;
        struct {
          union {
            __IO uint16_t IP_STRL;
            struct {
              __IO uint8_t IP_STRLL;
              __IO uint8_t IP_STRLH;
            };
          };
          union {
            __IO uint16_t IP_STRH;
            struct {
              __IO uint8_t IP_STRHL;
              __IO uint8_t IP_STRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IPINT_ENR;
        stc_i2spre_ipint_enr_field_t IPINT_ENR_f;
        struct {
          union {
            __IO uint16_t IPINT_ENRL;
            struct {
              __IO uint8_t IPINT_ENRLL;
              __IO uint8_t IPINT_ENRLH;
            };
          };
          union {
            __IO uint16_t IPINT_ENRH;
            struct {
              __IO uint8_t IPINT_ENRHL;
              __IO uint8_t IPINT_ENRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IPINT_CLR;
        stc_i2spre_ipint_clr_field_t IPINT_CLR_f;
        struct {
          union {
            __IO uint16_t IPINT_CLRL;
            struct {
              __IO uint8_t IPINT_CLRLL;
              __IO uint8_t IPINT_CLRLH;
            };
          };
          union {
            __IO uint16_t IPINT_CLRH;
            struct {
              __IO uint8_t IPINT_CLRHL;
              __IO uint8_t IPINT_CLRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IPINT_STR;
        stc_i2spre_ipint_str_field_t IPINT_STR_f;
        struct {
          union {
            __IO uint16_t IPINT_STRL;
            struct {
              __IO uint8_t IPINT_STRLL;
              __IO uint8_t IPINT_STRLH;
            };
          };
          union {
            __IO uint16_t IPINT_STRH;
            struct {
              __IO uint8_t IPINT_STRHL;
              __IO uint8_t IPINT_STRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IPCR5;
        stc_i2spre_ipcr5_field_t IPCR5_f;
        struct {
          union {
            __IO uint16_t IPCR5L;
            struct {
              __IO uint8_t IPCR5LL;
              __IO uint8_t IPCR5LH;
            };
          };
          union {
            __IO uint16_t IPCR5H;
            struct {
              __IO uint8_t IPCR5HL;
              __IO uint8_t IPCR5HH;
            };
          };
        };
    };
} FM_I2SPRE_TypeDef, FM4_I2SPRE_TypeDef;

/*******************************************************************************
* INTREQ_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO uint32_t DRQSEL;
        stc_intreq_drqsel_field_t DRQSEL_f;
        struct {
          union {
            __IO uint16_t DRQSELL;
            struct {
              __IO uint8_t DRQSELLL;
              __IO uint8_t DRQSELLH;
            };
          };
          union {
            __IO uint16_t DRQSELH;
            struct {
              __IO uint8_t DRQSELHL;
              __IO uint8_t DRQSELHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED0[12];
    union {
        __IO  uint8_t ODDPKS;
        stc_intreq_oddpks_field_t ODDPKS_f;
    };
        __IO  uint8_t RESERVED1[3];
    union {
        __IO  uint8_t ODDPKS1;
        stc_intreq_oddpks1_field_t ODDPKS1_f;
    };
        __IO  uint8_t RESERVED2[251];
    union {
        __IO uint32_t IRQ003SEL;
        stc_intreq_irq003sel_field_t IRQ003SEL_f;
        struct {
          union {
            __IO uint16_t IRQ003SELL;
            struct {
              __IO uint8_t IRQ003SELLL;
              __IO uint8_t IRQ003SELLH;
            };
          };
          union {
            __IO uint16_t IRQ003SELH;
            struct {
              __IO uint8_t IRQ003SELHL;
              __IO uint8_t IRQ003SELHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ004SEL;
        stc_intreq_irq004sel_field_t IRQ004SEL_f;
        struct {
          union {
            __IO uint16_t IRQ004SELL;
            struct {
              __IO uint8_t IRQ004SELLL;
              __IO uint8_t IRQ004SELLH;
            };
          };
          union {
            __IO uint16_t IRQ004SELH;
            struct {
              __IO uint8_t IRQ004SELHL;
              __IO uint8_t IRQ004SELHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ005SEL;
        stc_intreq_irq005sel_field_t IRQ005SEL_f;
        struct {
          union {
            __IO uint16_t IRQ005SELL;
            struct {
              __IO uint8_t IRQ005SELLL;
              __IO uint8_t IRQ005SELLH;
            };
          };
          union {
            __IO uint16_t IRQ005SELH;
            struct {
              __IO uint8_t IRQ005SELHL;
              __IO uint8_t IRQ005SELHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ006SEL;
        stc_intreq_irq006sel_field_t IRQ006SEL_f;
        struct {
          union {
            __IO uint16_t IRQ006SELL;
            struct {
              __IO uint8_t IRQ006SELLL;
              __IO uint8_t IRQ006SELLH;
            };
          };
          union {
            __IO uint16_t IRQ006SELH;
            struct {
              __IO uint8_t IRQ006SELHL;
              __IO uint8_t IRQ006SELHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ007SEL;
        stc_intreq_irq007sel_field_t IRQ007SEL_f;
        struct {
          union {
            __IO uint16_t IRQ007SELL;
            struct {
              __IO uint8_t IRQ007SELLL;
              __IO uint8_t IRQ007SELLH;
            };
          };
          union {
            __IO uint16_t IRQ007SELH;
            struct {
              __IO uint8_t IRQ007SELHL;
              __IO uint8_t IRQ007SELHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ008SEL;
        stc_intreq_irq008sel_field_t IRQ008SEL_f;
        struct {
          union {
            __IO uint16_t IRQ008SELL;
            struct {
              __IO uint8_t IRQ008SELLL;
              __IO uint8_t IRQ008SELLH;
            };
          };
          union {
            __IO uint16_t IRQ008SELH;
            struct {
              __IO uint8_t IRQ008SELHL;
              __IO uint8_t IRQ008SELHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ009SEL;
        stc_intreq_irq009sel_field_t IRQ009SEL_f;
        struct {
          union {
            __IO uint16_t IRQ009SELL;
            struct {
              __IO uint8_t IRQ009SELLL;
              __IO uint8_t IRQ009SELLH;
            };
          };
          union {
            __IO uint16_t IRQ009SELH;
            struct {
              __IO uint8_t IRQ009SELHL;
              __IO uint8_t IRQ009SELHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ010SEL;
        stc_intreq_irq010sel_field_t IRQ010SEL_f;
        struct {
          union {
            __IO uint16_t IRQ010SELL;
            struct {
              __IO uint8_t IRQ010SELLL;
              __IO uint8_t IRQ010SELLH;
            };
          };
          union {
            __IO uint16_t IRQ010SELH;
            struct {
              __IO uint8_t IRQ010SELHL;
              __IO uint8_t IRQ010SELHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED3[208];
    union {
        __IO uint32_t EXC02MON;
        stc_intreq_exc02mon_field_t EXC02MON_f;
        struct {
          union {
            __IO uint16_t EXC02MONL;
            struct {
              __IO uint8_t EXC02MONLL;
              __IO uint8_t EXC02MONLH;
            };
          };
          union {
            __IO uint16_t EXC02MONH;
            struct {
              __IO uint8_t EXC02MONHL;
              __IO uint8_t EXC02MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ000MON;
        stc_intreq_irq000mon_field_t IRQ000MON_f;
        struct {
          union {
            __IO uint16_t IRQ000MONL;
            struct {
              __IO uint8_t IRQ000MONLL;
              __IO uint8_t IRQ000MONLH;
            };
          };
          union {
            __IO uint16_t IRQ000MONH;
            struct {
              __IO uint8_t IRQ000MONHL;
              __IO uint8_t IRQ000MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ001MON;
        stc_intreq_irq001mon_field_t IRQ001MON_f;
        struct {
          union {
            __IO uint16_t IRQ001MONL;
            struct {
              __IO uint8_t IRQ001MONLL;
              __IO uint8_t IRQ001MONLH;
            };
          };
          union {
            __IO uint16_t IRQ001MONH;
            struct {
              __IO uint8_t IRQ001MONHL;
              __IO uint8_t IRQ001MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ002MON;
        stc_intreq_irq002mon_field_t IRQ002MON_f;
        struct {
          union {
            __IO uint16_t IRQ002MONL;
            struct {
              __IO uint8_t IRQ002MONLL;
              __IO uint8_t IRQ002MONLH;
            };
          };
          union {
            __IO uint16_t IRQ002MONH;
            struct {
              __IO uint8_t IRQ002MONHL;
              __IO uint8_t IRQ002MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ003MON;
        stc_intreq_irq003mon_field_t IRQ003MON_f;
        struct {
          union {
            __IO uint16_t IRQ003MONL;
            struct {
              __IO uint8_t IRQ003MONLL;
              __IO uint8_t IRQ003MONLH;
            };
          };
          union {
            __IO uint16_t IRQ003MONH;
            struct {
              __IO uint8_t IRQ003MONHL;
              __IO uint8_t IRQ003MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ004MON;
        stc_intreq_irq004mon_field_t IRQ004MON_f;
        struct {
          union {
            __IO uint16_t IRQ004MONL;
            struct {
              __IO uint8_t IRQ004MONLL;
              __IO uint8_t IRQ004MONLH;
            };
          };
          union {
            __IO uint16_t IRQ004MONH;
            struct {
              __IO uint8_t IRQ004MONHL;
              __IO uint8_t IRQ004MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ005MON;
        stc_intreq_irq005mon_field_t IRQ005MON_f;
        struct {
          union {
            __IO uint16_t IRQ005MONL;
            struct {
              __IO uint8_t IRQ005MONLL;
              __IO uint8_t IRQ005MONLH;
            };
          };
          union {
            __IO uint16_t IRQ005MONH;
            struct {
              __IO uint8_t IRQ005MONHL;
              __IO uint8_t IRQ005MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ006MON;
        stc_intreq_irq006mon_field_t IRQ006MON_f;
        struct {
          union {
            __IO uint16_t IRQ006MONL;
            struct {
              __IO uint8_t IRQ006MONLL;
              __IO uint8_t IRQ006MONLH;
            };
          };
          union {
            __IO uint16_t IRQ006MONH;
            struct {
              __IO uint8_t IRQ006MONHL;
              __IO uint8_t IRQ006MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ007MON;
        stc_intreq_irq007mon_field_t IRQ007MON_f;
        struct {
          union {
            __IO uint16_t IRQ007MONL;
            struct {
              __IO uint8_t IRQ007MONLL;
              __IO uint8_t IRQ007MONLH;
            };
          };
          union {
            __IO uint16_t IRQ007MONH;
            struct {
              __IO uint8_t IRQ007MONHL;
              __IO uint8_t IRQ007MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ008MON;
        stc_intreq_irq008mon_field_t IRQ008MON_f;
        struct {
          union {
            __IO uint16_t IRQ008MONL;
            struct {
              __IO uint8_t IRQ008MONLL;
              __IO uint8_t IRQ008MONLH;
            };
          };
          union {
            __IO uint16_t IRQ008MONH;
            struct {
              __IO uint8_t IRQ008MONHL;
              __IO uint8_t IRQ008MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ009MON;
        stc_intreq_irq009mon_field_t IRQ009MON_f;
        struct {
          union {
            __IO uint16_t IRQ009MONL;
            struct {
              __IO uint8_t IRQ009MONLL;
              __IO uint8_t IRQ009MONLH;
            };
          };
          union {
            __IO uint16_t IRQ009MONH;
            struct {
              __IO uint8_t IRQ009MONHL;
              __IO uint8_t IRQ009MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ010MON;
        stc_intreq_irq010mon_field_t IRQ010MON_f;
        struct {
          union {
            __IO uint16_t IRQ010MONL;
            struct {
              __IO uint8_t IRQ010MONLL;
              __IO uint8_t IRQ010MONLH;
            };
          };
          union {
            __IO uint16_t IRQ010MONH;
            struct {
              __IO uint8_t IRQ010MONHL;
              __IO uint8_t IRQ010MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ011MON;
        stc_intreq_irq011mon_field_t IRQ011MON_f;
        struct {
          union {
            __IO uint16_t IRQ011MONL;
            struct {
              __IO uint8_t IRQ011MONLL;
              __IO uint8_t IRQ011MONLH;
            };
          };
          union {
            __IO uint16_t IRQ011MONH;
            struct {
              __IO uint8_t IRQ011MONHL;
              __IO uint8_t IRQ011MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ012MON;
        stc_intreq_irq012mon_field_t IRQ012MON_f;
        struct {
          union {
            __IO uint16_t IRQ012MONL;
            struct {
              __IO uint8_t IRQ012MONLL;
              __IO uint8_t IRQ012MONLH;
            };
          };
          union {
            __IO uint16_t IRQ012MONH;
            struct {
              __IO uint8_t IRQ012MONHL;
              __IO uint8_t IRQ012MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ013MON;
        stc_intreq_irq013mon_field_t IRQ013MON_f;
        struct {
          union {
            __IO uint16_t IRQ013MONL;
            struct {
              __IO uint8_t IRQ013MONLL;
              __IO uint8_t IRQ013MONLH;
            };
          };
          union {
            __IO uint16_t IRQ013MONH;
            struct {
              __IO uint8_t IRQ013MONHL;
              __IO uint8_t IRQ013MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ014MON;
        stc_intreq_irq014mon_field_t IRQ014MON_f;
        struct {
          union {
            __IO uint16_t IRQ014MONL;
            struct {
              __IO uint8_t IRQ014MONLL;
              __IO uint8_t IRQ014MONLH;
            };
          };
          union {
            __IO uint16_t IRQ014MONH;
            struct {
              __IO uint8_t IRQ014MONHL;
              __IO uint8_t IRQ014MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ015MON;
        stc_intreq_irq015mon_field_t IRQ015MON_f;
        struct {
          union {
            __IO uint16_t IRQ015MONL;
            struct {
              __IO uint8_t IRQ015MONLL;
              __IO uint8_t IRQ015MONLH;
            };
          };
          union {
            __IO uint16_t IRQ015MONH;
            struct {
              __IO uint8_t IRQ015MONHL;
              __IO uint8_t IRQ015MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ016MON;
        stc_intreq_irq016mon_field_t IRQ016MON_f;
        struct {
          union {
            __IO uint16_t IRQ016MONL;
            struct {
              __IO uint8_t IRQ016MONLL;
              __IO uint8_t IRQ016MONLH;
            };
          };
          union {
            __IO uint16_t IRQ016MONH;
            struct {
              __IO uint8_t IRQ016MONHL;
              __IO uint8_t IRQ016MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ017MON;
        stc_intreq_irq017mon_field_t IRQ017MON_f;
        struct {
          union {
            __IO uint16_t IRQ017MONL;
            struct {
              __IO uint8_t IRQ017MONLL;
              __IO uint8_t IRQ017MONLH;
            };
          };
          union {
            __IO uint16_t IRQ017MONH;
            struct {
              __IO uint8_t IRQ017MONHL;
              __IO uint8_t IRQ017MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ018MON;
        stc_intreq_irq018mon_field_t IRQ018MON_f;
        struct {
          union {
            __IO uint16_t IRQ018MONL;
            struct {
              __IO uint8_t IRQ018MONLL;
              __IO uint8_t IRQ018MONLH;
            };
          };
          union {
            __IO uint16_t IRQ018MONH;
            struct {
              __IO uint8_t IRQ018MONHL;
              __IO uint8_t IRQ018MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ019MON;
        stc_intreq_irq019mon_field_t IRQ019MON_f;
        struct {
          union {
            __IO uint16_t IRQ019MONL;
            struct {
              __IO uint8_t IRQ019MONLL;
              __IO uint8_t IRQ019MONLH;
            };
          };
          union {
            __IO uint16_t IRQ019MONH;
            struct {
              __IO uint8_t IRQ019MONHL;
              __IO uint8_t IRQ019MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ020MON;
        stc_intreq_irq020mon_field_t IRQ020MON_f;
        struct {
          union {
            __IO uint16_t IRQ020MONL;
            struct {
              __IO uint8_t IRQ020MONLL;
              __IO uint8_t IRQ020MONLH;
            };
          };
          union {
            __IO uint16_t IRQ020MONH;
            struct {
              __IO uint8_t IRQ020MONHL;
              __IO uint8_t IRQ020MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ021MON;
        stc_intreq_irq021mon_field_t IRQ021MON_f;
        struct {
          union {
            __IO uint16_t IRQ021MONL;
            struct {
              __IO uint8_t IRQ021MONLL;
              __IO uint8_t IRQ021MONLH;
            };
          };
          union {
            __IO uint16_t IRQ021MONH;
            struct {
              __IO uint8_t IRQ021MONHL;
              __IO uint8_t IRQ021MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ022MON;
        stc_intreq_irq022mon_field_t IRQ022MON_f;
        struct {
          union {
            __IO uint16_t IRQ022MONL;
            struct {
              __IO uint8_t IRQ022MONLL;
              __IO uint8_t IRQ022MONLH;
            };
          };
          union {
            __IO uint16_t IRQ022MONH;
            struct {
              __IO uint8_t IRQ022MONHL;
              __IO uint8_t IRQ022MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ023MON;
        stc_intreq_irq023mon_field_t IRQ023MON_f;
        struct {
          union {
            __IO uint16_t IRQ023MONL;
            struct {
              __IO uint8_t IRQ023MONLL;
              __IO uint8_t IRQ023MONLH;
            };
          };
          union {
            __IO uint16_t IRQ023MONH;
            struct {
              __IO uint8_t IRQ023MONHL;
              __IO uint8_t IRQ023MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ024MON;
        stc_intreq_irq024mon_field_t IRQ024MON_f;
        struct {
          union {
            __IO uint16_t IRQ024MONL;
            struct {
              __IO uint8_t IRQ024MONLL;
              __IO uint8_t IRQ024MONLH;
            };
          };
          union {
            __IO uint16_t IRQ024MONH;
            struct {
              __IO uint8_t IRQ024MONHL;
              __IO uint8_t IRQ024MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ025MON;
        stc_intreq_irq025mon_field_t IRQ025MON_f;
        struct {
          union {
            __IO uint16_t IRQ025MONL;
            struct {
              __IO uint8_t IRQ025MONLL;
              __IO uint8_t IRQ025MONLH;
            };
          };
          union {
            __IO uint16_t IRQ025MONH;
            struct {
              __IO uint8_t IRQ025MONHL;
              __IO uint8_t IRQ025MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ026MON;
        stc_intreq_irq026mon_field_t IRQ026MON_f;
        struct {
          union {
            __IO uint16_t IRQ026MONL;
            struct {
              __IO uint8_t IRQ026MONLL;
              __IO uint8_t IRQ026MONLH;
            };
          };
          union {
            __IO uint16_t IRQ026MONH;
            struct {
              __IO uint8_t IRQ026MONHL;
              __IO uint8_t IRQ026MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ027MON;
        stc_intreq_irq027mon_field_t IRQ027MON_f;
        struct {
          union {
            __IO uint16_t IRQ027MONL;
            struct {
              __IO uint8_t IRQ027MONLL;
              __IO uint8_t IRQ027MONLH;
            };
          };
          union {
            __IO uint16_t IRQ027MONH;
            struct {
              __IO uint8_t IRQ027MONHL;
              __IO uint8_t IRQ027MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ028MON;
        stc_intreq_irq028mon_field_t IRQ028MON_f;
        struct {
          union {
            __IO uint16_t IRQ028MONL;
            struct {
              __IO uint8_t IRQ028MONLL;
              __IO uint8_t IRQ028MONLH;
            };
          };
          union {
            __IO uint16_t IRQ028MONH;
            struct {
              __IO uint8_t IRQ028MONHL;
              __IO uint8_t IRQ028MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ029MON;
        stc_intreq_irq029mon_field_t IRQ029MON_f;
        struct {
          union {
            __IO uint16_t IRQ029MONL;
            struct {
              __IO uint8_t IRQ029MONLL;
              __IO uint8_t IRQ029MONLH;
            };
          };
          union {
            __IO uint16_t IRQ029MONH;
            struct {
              __IO uint8_t IRQ029MONHL;
              __IO uint8_t IRQ029MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ030MON;
        stc_intreq_irq030mon_field_t IRQ030MON_f;
        struct {
          union {
            __IO uint16_t IRQ030MONL;
            struct {
              __IO uint8_t IRQ030MONLL;
              __IO uint8_t IRQ030MONLH;
            };
          };
          union {
            __IO uint16_t IRQ030MONH;
            struct {
              __IO uint8_t IRQ030MONHL;
              __IO uint8_t IRQ030MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ031MON;
        stc_intreq_irq031mon_field_t IRQ031MON_f;
        struct {
          union {
            __IO uint16_t IRQ031MONL;
            struct {
              __IO uint8_t IRQ031MONLL;
              __IO uint8_t IRQ031MONLH;
            };
          };
          union {
            __IO uint16_t IRQ031MONH;
            struct {
              __IO uint8_t IRQ031MONHL;
              __IO uint8_t IRQ031MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ032MON;
        stc_intreq_irq032mon_field_t IRQ032MON_f;
        struct {
          union {
            __IO uint16_t IRQ032MONL;
            struct {
              __IO uint8_t IRQ032MONLL;
              __IO uint8_t IRQ032MONLH;
            };
          };
          union {
            __IO uint16_t IRQ032MONH;
            struct {
              __IO uint8_t IRQ032MONHL;
              __IO uint8_t IRQ032MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ033MON;
        stc_intreq_irq033mon_field_t IRQ033MON_f;
        struct {
          union {
            __IO uint16_t IRQ033MONL;
            struct {
              __IO uint8_t IRQ033MONLL;
              __IO uint8_t IRQ033MONLH;
            };
          };
          union {
            __IO uint16_t IRQ033MONH;
            struct {
              __IO uint8_t IRQ033MONHL;
              __IO uint8_t IRQ033MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ034MON;
        stc_intreq_irq034mon_field_t IRQ034MON_f;
        struct {
          union {
            __IO uint16_t IRQ034MONL;
            struct {
              __IO uint8_t IRQ034MONLL;
              __IO uint8_t IRQ034MONLH;
            };
          };
          union {
            __IO uint16_t IRQ034MONH;
            struct {
              __IO uint8_t IRQ034MONHL;
              __IO uint8_t IRQ034MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ035MON;
        stc_intreq_irq035mon_field_t IRQ035MON_f;
        struct {
          union {
            __IO uint16_t IRQ035MONL;
            struct {
              __IO uint8_t IRQ035MONLL;
              __IO uint8_t IRQ035MONLH;
            };
          };
          union {
            __IO uint16_t IRQ035MONH;
            struct {
              __IO uint8_t IRQ035MONHL;
              __IO uint8_t IRQ035MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ036MON;
        stc_intreq_irq036mon_field_t IRQ036MON_f;
        struct {
          union {
            __IO uint16_t IRQ036MONL;
            struct {
              __IO uint8_t IRQ036MONLL;
              __IO uint8_t IRQ036MONLH;
            };
          };
          union {
            __IO uint16_t IRQ036MONH;
            struct {
              __IO uint8_t IRQ036MONHL;
              __IO uint8_t IRQ036MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ037MON;
        stc_intreq_irq037mon_field_t IRQ037MON_f;
        struct {
          union {
            __IO uint16_t IRQ037MONL;
            struct {
              __IO uint8_t IRQ037MONLL;
              __IO uint8_t IRQ037MONLH;
            };
          };
          union {
            __IO uint16_t IRQ037MONH;
            struct {
              __IO uint8_t IRQ037MONHL;
              __IO uint8_t IRQ037MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ038MON;
        stc_intreq_irq038mon_field_t IRQ038MON_f;
        struct {
          union {
            __IO uint16_t IRQ038MONL;
            struct {
              __IO uint8_t IRQ038MONLL;
              __IO uint8_t IRQ038MONLH;
            };
          };
          union {
            __IO uint16_t IRQ038MONH;
            struct {
              __IO uint8_t IRQ038MONHL;
              __IO uint8_t IRQ038MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ039MON;
        stc_intreq_irq039mon_field_t IRQ039MON_f;
        struct {
          union {
            __IO uint16_t IRQ039MONL;
            struct {
              __IO uint8_t IRQ039MONLL;
              __IO uint8_t IRQ039MONLH;
            };
          };
          union {
            __IO uint16_t IRQ039MONH;
            struct {
              __IO uint8_t IRQ039MONHL;
              __IO uint8_t IRQ039MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ040MON;
        stc_intreq_irq040mon_field_t IRQ040MON_f;
        struct {
          union {
            __IO uint16_t IRQ040MONL;
            struct {
              __IO uint8_t IRQ040MONLL;
              __IO uint8_t IRQ040MONLH;
            };
          };
          union {
            __IO uint16_t IRQ040MONH;
            struct {
              __IO uint8_t IRQ040MONHL;
              __IO uint8_t IRQ040MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ041MON;
        stc_intreq_irq041mon_field_t IRQ041MON_f;
        struct {
          union {
            __IO uint16_t IRQ041MONL;
            struct {
              __IO uint8_t IRQ041MONLL;
              __IO uint8_t IRQ041MONLH;
            };
          };
          union {
            __IO uint16_t IRQ041MONH;
            struct {
              __IO uint8_t IRQ041MONHL;
              __IO uint8_t IRQ041MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ042MON;
        stc_intreq_irq042mon_field_t IRQ042MON_f;
        struct {
          union {
            __IO uint16_t IRQ042MONL;
            struct {
              __IO uint8_t IRQ042MONLL;
              __IO uint8_t IRQ042MONLH;
            };
          };
          union {
            __IO uint16_t IRQ042MONH;
            struct {
              __IO uint8_t IRQ042MONHL;
              __IO uint8_t IRQ042MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ043MON;
        stc_intreq_irq043mon_field_t IRQ043MON_f;
        struct {
          union {
            __IO uint16_t IRQ043MONL;
            struct {
              __IO uint8_t IRQ043MONLL;
              __IO uint8_t IRQ043MONLH;
            };
          };
          union {
            __IO uint16_t IRQ043MONH;
            struct {
              __IO uint8_t IRQ043MONHL;
              __IO uint8_t IRQ043MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ044MON;
        stc_intreq_irq044mon_field_t IRQ044MON_f;
        struct {
          union {
            __IO uint16_t IRQ044MONL;
            struct {
              __IO uint8_t IRQ044MONLL;
              __IO uint8_t IRQ044MONLH;
            };
          };
          union {
            __IO uint16_t IRQ044MONH;
            struct {
              __IO uint8_t IRQ044MONHL;
              __IO uint8_t IRQ044MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ045MON;
        stc_intreq_irq045mon_field_t IRQ045MON_f;
        struct {
          union {
            __IO uint16_t IRQ045MONL;
            struct {
              __IO uint8_t IRQ045MONLL;
              __IO uint8_t IRQ045MONLH;
            };
          };
          union {
            __IO uint16_t IRQ045MONH;
            struct {
              __IO uint8_t IRQ045MONHL;
              __IO uint8_t IRQ045MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ046MON;
        stc_intreq_irq046mon_field_t IRQ046MON_f;
        struct {
          union {
            __IO uint16_t IRQ046MONL;
            struct {
              __IO uint8_t IRQ046MONLL;
              __IO uint8_t IRQ046MONLH;
            };
          };
          union {
            __IO uint16_t IRQ046MONH;
            struct {
              __IO uint8_t IRQ046MONHL;
              __IO uint8_t IRQ046MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ047MON;
        stc_intreq_irq047mon_field_t IRQ047MON_f;
        struct {
          union {
            __IO uint16_t IRQ047MONL;
            struct {
              __IO uint8_t IRQ047MONLL;
              __IO uint8_t IRQ047MONLH;
            };
          };
          union {
            __IO uint16_t IRQ047MONH;
            struct {
              __IO uint8_t IRQ047MONHL;
              __IO uint8_t IRQ047MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ048MON;
        stc_intreq_irq048mon_field_t IRQ048MON_f;
        struct {
          union {
            __IO uint16_t IRQ048MONL;
            struct {
              __IO uint8_t IRQ048MONLL;
              __IO uint8_t IRQ048MONLH;
            };
          };
          union {
            __IO uint16_t IRQ048MONH;
            struct {
              __IO uint8_t IRQ048MONHL;
              __IO uint8_t IRQ048MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ049MON;
        stc_intreq_irq049mon_field_t IRQ049MON_f;
        struct {
          union {
            __IO uint16_t IRQ049MONL;
            struct {
              __IO uint8_t IRQ049MONLL;
              __IO uint8_t IRQ049MONLH;
            };
          };
          union {
            __IO uint16_t IRQ049MONH;
            struct {
              __IO uint8_t IRQ049MONHL;
              __IO uint8_t IRQ049MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ050MON;
        stc_intreq_irq050mon_field_t IRQ050MON_f;
        struct {
          union {
            __IO uint16_t IRQ050MONL;
            struct {
              __IO uint8_t IRQ050MONLL;
              __IO uint8_t IRQ050MONLH;
            };
          };
          union {
            __IO uint16_t IRQ050MONH;
            struct {
              __IO uint8_t IRQ050MONHL;
              __IO uint8_t IRQ050MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ051MON;
        stc_intreq_irq051mon_field_t IRQ051MON_f;
        struct {
          union {
            __IO uint16_t IRQ051MONL;
            struct {
              __IO uint8_t IRQ051MONLL;
              __IO uint8_t IRQ051MONLH;
            };
          };
          union {
            __IO uint16_t IRQ051MONH;
            struct {
              __IO uint8_t IRQ051MONHL;
              __IO uint8_t IRQ051MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ052MON;
        stc_intreq_irq052mon_field_t IRQ052MON_f;
        struct {
          union {
            __IO uint16_t IRQ052MONL;
            struct {
              __IO uint8_t IRQ052MONLL;
              __IO uint8_t IRQ052MONLH;
            };
          };
          union {
            __IO uint16_t IRQ052MONH;
            struct {
              __IO uint8_t IRQ052MONHL;
              __IO uint8_t IRQ052MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ053MON;
        stc_intreq_irq053mon_field_t IRQ053MON_f;
        struct {
          union {
            __IO uint16_t IRQ053MONL;
            struct {
              __IO uint8_t IRQ053MONLL;
              __IO uint8_t IRQ053MONLH;
            };
          };
          union {
            __IO uint16_t IRQ053MONH;
            struct {
              __IO uint8_t IRQ053MONHL;
              __IO uint8_t IRQ053MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ054MON;
        stc_intreq_irq054mon_field_t IRQ054MON_f;
        struct {
          union {
            __IO uint16_t IRQ054MONL;
            struct {
              __IO uint8_t IRQ054MONLL;
              __IO uint8_t IRQ054MONLH;
            };
          };
          union {
            __IO uint16_t IRQ054MONH;
            struct {
              __IO uint8_t IRQ054MONHL;
              __IO uint8_t IRQ054MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ055MON;
        stc_intreq_irq055mon_field_t IRQ055MON_f;
        struct {
          union {
            __IO uint16_t IRQ055MONL;
            struct {
              __IO uint8_t IRQ055MONLL;
              __IO uint8_t IRQ055MONLH;
            };
          };
          union {
            __IO uint16_t IRQ055MONH;
            struct {
              __IO uint8_t IRQ055MONHL;
              __IO uint8_t IRQ055MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ056MON;
        stc_intreq_irq056mon_field_t IRQ056MON_f;
        struct {
          union {
            __IO uint16_t IRQ056MONL;
            struct {
              __IO uint8_t IRQ056MONLL;
              __IO uint8_t IRQ056MONLH;
            };
          };
          union {
            __IO uint16_t IRQ056MONH;
            struct {
              __IO uint8_t IRQ056MONHL;
              __IO uint8_t IRQ056MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ057MON;
        stc_intreq_irq057mon_field_t IRQ057MON_f;
        struct {
          union {
            __IO uint16_t IRQ057MONL;
            struct {
              __IO uint8_t IRQ057MONLL;
              __IO uint8_t IRQ057MONLH;
            };
          };
          union {
            __IO uint16_t IRQ057MONH;
            struct {
              __IO uint8_t IRQ057MONHL;
              __IO uint8_t IRQ057MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ058MON;
        stc_intreq_irq058mon_field_t IRQ058MON_f;
        struct {
          union {
            __IO uint16_t IRQ058MONL;
            struct {
              __IO uint8_t IRQ058MONLL;
              __IO uint8_t IRQ058MONLH;
            };
          };
          union {
            __IO uint16_t IRQ058MONH;
            struct {
              __IO uint8_t IRQ058MONHL;
              __IO uint8_t IRQ058MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ059MON;
        stc_intreq_irq059mon_field_t IRQ059MON_f;
        struct {
          union {
            __IO uint16_t IRQ059MONL;
            struct {
              __IO uint8_t IRQ059MONLL;
              __IO uint8_t IRQ059MONLH;
            };
          };
          union {
            __IO uint16_t IRQ059MONH;
            struct {
              __IO uint8_t IRQ059MONHL;
              __IO uint8_t IRQ059MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ060MON;
        stc_intreq_irq060mon_field_t IRQ060MON_f;
        struct {
          union {
            __IO uint16_t IRQ060MONL;
            struct {
              __IO uint8_t IRQ060MONLL;
              __IO uint8_t IRQ060MONLH;
            };
          };
          union {
            __IO uint16_t IRQ060MONH;
            struct {
              __IO uint8_t IRQ060MONHL;
              __IO uint8_t IRQ060MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ061MON;
        stc_intreq_irq061mon_field_t IRQ061MON_f;
        struct {
          union {
            __IO uint16_t IRQ061MONL;
            struct {
              __IO uint8_t IRQ061MONLL;
              __IO uint8_t IRQ061MONLH;
            };
          };
          union {
            __IO uint16_t IRQ061MONH;
            struct {
              __IO uint8_t IRQ061MONHL;
              __IO uint8_t IRQ061MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ062MON;
        stc_intreq_irq062mon_field_t IRQ062MON_f;
        struct {
          union {
            __IO uint16_t IRQ062MONL;
            struct {
              __IO uint8_t IRQ062MONLL;
              __IO uint8_t IRQ062MONLH;
            };
          };
          union {
            __IO uint16_t IRQ062MONH;
            struct {
              __IO uint8_t IRQ062MONHL;
              __IO uint8_t IRQ062MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ063MON;
        stc_intreq_irq063mon_field_t IRQ063MON_f;
        struct {
          union {
            __IO uint16_t IRQ063MONL;
            struct {
              __IO uint8_t IRQ063MONLL;
              __IO uint8_t IRQ063MONLH;
            };
          };
          union {
            __IO uint16_t IRQ063MONH;
            struct {
              __IO uint8_t IRQ063MONHL;
              __IO uint8_t IRQ063MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ064MON;
        stc_intreq_irq064mon_field_t IRQ064MON_f;
        struct {
          union {
            __IO uint16_t IRQ064MONL;
            struct {
              __IO uint8_t IRQ064MONLL;
              __IO uint8_t IRQ064MONLH;
            };
          };
          union {
            __IO uint16_t IRQ064MONH;
            struct {
              __IO uint8_t IRQ064MONHL;
              __IO uint8_t IRQ064MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ065MON;
        stc_intreq_irq065mon_field_t IRQ065MON_f;
        struct {
          union {
            __IO uint16_t IRQ065MONL;
            struct {
              __IO uint8_t IRQ065MONLL;
              __IO uint8_t IRQ065MONLH;
            };
          };
          union {
            __IO uint16_t IRQ065MONH;
            struct {
              __IO uint8_t IRQ065MONHL;
              __IO uint8_t IRQ065MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ066MON;
        stc_intreq_irq066mon_field_t IRQ066MON_f;
        struct {
          union {
            __IO uint16_t IRQ066MONL;
            struct {
              __IO uint8_t IRQ066MONLL;
              __IO uint8_t IRQ066MONLH;
            };
          };
          union {
            __IO uint16_t IRQ066MONH;
            struct {
              __IO uint8_t IRQ066MONHL;
              __IO uint8_t IRQ066MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ067MON;
        stc_intreq_irq067mon_field_t IRQ067MON_f;
        struct {
          union {
            __IO uint16_t IRQ067MONL;
            struct {
              __IO uint8_t IRQ067MONLL;
              __IO uint8_t IRQ067MONLH;
            };
          };
          union {
            __IO uint16_t IRQ067MONH;
            struct {
              __IO uint8_t IRQ067MONHL;
              __IO uint8_t IRQ067MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ068MON;
        stc_intreq_irq068mon_field_t IRQ068MON_f;
        struct {
          union {
            __IO uint16_t IRQ068MONL;
            struct {
              __IO uint8_t IRQ068MONLL;
              __IO uint8_t IRQ068MONLH;
            };
          };
          union {
            __IO uint16_t IRQ068MONH;
            struct {
              __IO uint8_t IRQ068MONHL;
              __IO uint8_t IRQ068MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ069MON;
        stc_intreq_irq069mon_field_t IRQ069MON_f;
        struct {
          union {
            __IO uint16_t IRQ069MONL;
            struct {
              __IO uint8_t IRQ069MONLL;
              __IO uint8_t IRQ069MONLH;
            };
          };
          union {
            __IO uint16_t IRQ069MONH;
            struct {
              __IO uint8_t IRQ069MONHL;
              __IO uint8_t IRQ069MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ070MON;
        stc_intreq_irq070mon_field_t IRQ070MON_f;
        struct {
          union {
            __IO uint16_t IRQ070MONL;
            struct {
              __IO uint8_t IRQ070MONLL;
              __IO uint8_t IRQ070MONLH;
            };
          };
          union {
            __IO uint16_t IRQ070MONH;
            struct {
              __IO uint8_t IRQ070MONHL;
              __IO uint8_t IRQ070MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ071MON;
        stc_intreq_irq071mon_field_t IRQ071MON_f;
        struct {
          union {
            __IO uint16_t IRQ071MONL;
            struct {
              __IO uint8_t IRQ071MONLL;
              __IO uint8_t IRQ071MONLH;
            };
          };
          union {
            __IO uint16_t IRQ071MONH;
            struct {
              __IO uint8_t IRQ071MONHL;
              __IO uint8_t IRQ071MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ072MON;
        stc_intreq_irq072mon_field_t IRQ072MON_f;
        struct {
          union {
            __IO uint16_t IRQ072MONL;
            struct {
              __IO uint8_t IRQ072MONLL;
              __IO uint8_t IRQ072MONLH;
            };
          };
          union {
            __IO uint16_t IRQ072MONH;
            struct {
              __IO uint8_t IRQ072MONHL;
              __IO uint8_t IRQ072MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ073MON;
        stc_intreq_irq073mon_field_t IRQ073MON_f;
        struct {
          union {
            __IO uint16_t IRQ073MONL;
            struct {
              __IO uint8_t IRQ073MONLL;
              __IO uint8_t IRQ073MONLH;
            };
          };
          union {
            __IO uint16_t IRQ073MONH;
            struct {
              __IO uint8_t IRQ073MONHL;
              __IO uint8_t IRQ073MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ074MON;
        stc_intreq_irq074mon_field_t IRQ074MON_f;
        struct {
          union {
            __IO uint16_t IRQ074MONL;
            struct {
              __IO uint8_t IRQ074MONLL;
              __IO uint8_t IRQ074MONLH;
            };
          };
          union {
            __IO uint16_t IRQ074MONH;
            struct {
              __IO uint8_t IRQ074MONHL;
              __IO uint8_t IRQ074MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ075MON;
        stc_intreq_irq075mon_field_t IRQ075MON_f;
        struct {
          union {
            __IO uint16_t IRQ075MONL;
            struct {
              __IO uint8_t IRQ075MONLL;
              __IO uint8_t IRQ075MONLH;
            };
          };
          union {
            __IO uint16_t IRQ075MONH;
            struct {
              __IO uint8_t IRQ075MONHL;
              __IO uint8_t IRQ075MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ076MON;
        stc_intreq_irq076mon_field_t IRQ076MON_f;
        struct {
          union {
            __IO uint16_t IRQ076MONL;
            struct {
              __IO uint8_t IRQ076MONLL;
              __IO uint8_t IRQ076MONLH;
            };
          };
          union {
            __IO uint16_t IRQ076MONH;
            struct {
              __IO uint8_t IRQ076MONHL;
              __IO uint8_t IRQ076MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ077MON;
        stc_intreq_irq077mon_field_t IRQ077MON_f;
        struct {
          union {
            __IO uint16_t IRQ077MONL;
            struct {
              __IO uint8_t IRQ077MONLL;
              __IO uint8_t IRQ077MONLH;
            };
          };
          union {
            __IO uint16_t IRQ077MONH;
            struct {
              __IO uint8_t IRQ077MONHL;
              __IO uint8_t IRQ077MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ078MON;
        stc_intreq_irq078mon_field_t IRQ078MON_f;
        struct {
          union {
            __IO uint16_t IRQ078MONL;
            struct {
              __IO uint8_t IRQ078MONLL;
              __IO uint8_t IRQ078MONLH;
            };
          };
          union {
            __IO uint16_t IRQ078MONH;
            struct {
              __IO uint8_t IRQ078MONHL;
              __IO uint8_t IRQ078MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ079MON;
        stc_intreq_irq079mon_field_t IRQ079MON_f;
        struct {
          union {
            __IO uint16_t IRQ079MONL;
            struct {
              __IO uint8_t IRQ079MONLL;
              __IO uint8_t IRQ079MONLH;
            };
          };
          union {
            __IO uint16_t IRQ079MONH;
            struct {
              __IO uint8_t IRQ079MONHL;
              __IO uint8_t IRQ079MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ080MON;
        stc_intreq_irq080mon_field_t IRQ080MON_f;
        struct {
          union {
            __IO uint16_t IRQ080MONL;
            struct {
              __IO uint8_t IRQ080MONLL;
              __IO uint8_t IRQ080MONLH;
            };
          };
          union {
            __IO uint16_t IRQ080MONH;
            struct {
              __IO uint8_t IRQ080MONHL;
              __IO uint8_t IRQ080MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ081MON;
        stc_intreq_irq081mon_field_t IRQ081MON_f;
        struct {
          union {
            __IO uint16_t IRQ081MONL;
            struct {
              __IO uint8_t IRQ081MONLL;
              __IO uint8_t IRQ081MONLH;
            };
          };
          union {
            __IO uint16_t IRQ081MONH;
            struct {
              __IO uint8_t IRQ081MONHL;
              __IO uint8_t IRQ081MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ082MON;
        stc_intreq_irq082mon_field_t IRQ082MON_f;
        struct {
          union {
            __IO uint16_t IRQ082MONL;
            struct {
              __IO uint8_t IRQ082MONLL;
              __IO uint8_t IRQ082MONLH;
            };
          };
          union {
            __IO uint16_t IRQ082MONH;
            struct {
              __IO uint8_t IRQ082MONHL;
              __IO uint8_t IRQ082MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ083MON;
        stc_intreq_irq083mon_field_t IRQ083MON_f;
        struct {
          union {
            __IO uint16_t IRQ083MONL;
            struct {
              __IO uint8_t IRQ083MONLL;
              __IO uint8_t IRQ083MONLH;
            };
          };
          union {
            __IO uint16_t IRQ083MONH;
            struct {
              __IO uint8_t IRQ083MONHL;
              __IO uint8_t IRQ083MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ084MON;
        stc_intreq_irq084mon_field_t IRQ084MON_f;
        struct {
          union {
            __IO uint16_t IRQ084MONL;
            struct {
              __IO uint8_t IRQ084MONLL;
              __IO uint8_t IRQ084MONLH;
            };
          };
          union {
            __IO uint16_t IRQ084MONH;
            struct {
              __IO uint8_t IRQ084MONHL;
              __IO uint8_t IRQ084MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ085MON;
        stc_intreq_irq085mon_field_t IRQ085MON_f;
        struct {
          union {
            __IO uint16_t IRQ085MONL;
            struct {
              __IO uint8_t IRQ085MONLL;
              __IO uint8_t IRQ085MONLH;
            };
          };
          union {
            __IO uint16_t IRQ085MONH;
            struct {
              __IO uint8_t IRQ085MONHL;
              __IO uint8_t IRQ085MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ086MON;
        stc_intreq_irq086mon_field_t IRQ086MON_f;
        struct {
          union {
            __IO uint16_t IRQ086MONL;
            struct {
              __IO uint8_t IRQ086MONLL;
              __IO uint8_t IRQ086MONLH;
            };
          };
          union {
            __IO uint16_t IRQ086MONH;
            struct {
              __IO uint8_t IRQ086MONHL;
              __IO uint8_t IRQ086MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ087MON;
        stc_intreq_irq087mon_field_t IRQ087MON_f;
        struct {
          union {
            __IO uint16_t IRQ087MONL;
            struct {
              __IO uint8_t IRQ087MONLL;
              __IO uint8_t IRQ087MONLH;
            };
          };
          union {
            __IO uint16_t IRQ087MONH;
            struct {
              __IO uint8_t IRQ087MONHL;
              __IO uint8_t IRQ087MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ088MON;
        stc_intreq_irq088mon_field_t IRQ088MON_f;
        struct {
          union {
            __IO uint16_t IRQ088MONL;
            struct {
              __IO uint8_t IRQ088MONLL;
              __IO uint8_t IRQ088MONLH;
            };
          };
          union {
            __IO uint16_t IRQ088MONH;
            struct {
              __IO uint8_t IRQ088MONHL;
              __IO uint8_t IRQ088MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ089MON;
        stc_intreq_irq089mon_field_t IRQ089MON_f;
        struct {
          union {
            __IO uint16_t IRQ089MONL;
            struct {
              __IO uint8_t IRQ089MONLL;
              __IO uint8_t IRQ089MONLH;
            };
          };
          union {
            __IO uint16_t IRQ089MONH;
            struct {
              __IO uint8_t IRQ089MONHL;
              __IO uint8_t IRQ089MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ090MON;
        stc_intreq_irq090mon_field_t IRQ090MON_f;
        struct {
          union {
            __IO uint16_t IRQ090MONL;
            struct {
              __IO uint8_t IRQ090MONLL;
              __IO uint8_t IRQ090MONLH;
            };
          };
          union {
            __IO uint16_t IRQ090MONH;
            struct {
              __IO uint8_t IRQ090MONHL;
              __IO uint8_t IRQ090MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ091MON;
        stc_intreq_irq091mon_field_t IRQ091MON_f;
        struct {
          union {
            __IO uint16_t IRQ091MONL;
            struct {
              __IO uint8_t IRQ091MONLL;
              __IO uint8_t IRQ091MONLH;
            };
          };
          union {
            __IO uint16_t IRQ091MONH;
            struct {
              __IO uint8_t IRQ091MONHL;
              __IO uint8_t IRQ091MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ092MON;
        stc_intreq_irq092mon_field_t IRQ092MON_f;
        struct {
          union {
            __IO uint16_t IRQ092MONL;
            struct {
              __IO uint8_t IRQ092MONLL;
              __IO uint8_t IRQ092MONLH;
            };
          };
          union {
            __IO uint16_t IRQ092MONH;
            struct {
              __IO uint8_t IRQ092MONHL;
              __IO uint8_t IRQ092MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ093MON;
        stc_intreq_irq093mon_field_t IRQ093MON_f;
        struct {
          union {
            __IO uint16_t IRQ093MONL;
            struct {
              __IO uint8_t IRQ093MONLL;
              __IO uint8_t IRQ093MONLH;
            };
          };
          union {
            __IO uint16_t IRQ093MONH;
            struct {
              __IO uint8_t IRQ093MONHL;
              __IO uint8_t IRQ093MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ094MON;
        stc_intreq_irq094mon_field_t IRQ094MON_f;
        struct {
          union {
            __IO uint16_t IRQ094MONL;
            struct {
              __IO uint8_t IRQ094MONLL;
              __IO uint8_t IRQ094MONLH;
            };
          };
          union {
            __IO uint16_t IRQ094MONH;
            struct {
              __IO uint8_t IRQ094MONHL;
              __IO uint8_t IRQ094MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ095MON;
        stc_intreq_irq095mon_field_t IRQ095MON_f;
        struct {
          union {
            __IO uint16_t IRQ095MONL;
            struct {
              __IO uint8_t IRQ095MONLL;
              __IO uint8_t IRQ095MONLH;
            };
          };
          union {
            __IO uint16_t IRQ095MONH;
            struct {
              __IO uint8_t IRQ095MONHL;
              __IO uint8_t IRQ095MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ096MON;
        stc_intreq_irq096mon_field_t IRQ096MON_f;
        struct {
          union {
            __IO uint16_t IRQ096MONL;
            struct {
              __IO uint8_t IRQ096MONLL;
              __IO uint8_t IRQ096MONLH;
            };
          };
          union {
            __IO uint16_t IRQ096MONH;
            struct {
              __IO uint8_t IRQ096MONHL;
              __IO uint8_t IRQ096MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ097MON;
        stc_intreq_irq097mon_field_t IRQ097MON_f;
        struct {
          union {
            __IO uint16_t IRQ097MONL;
            struct {
              __IO uint8_t IRQ097MONLL;
              __IO uint8_t IRQ097MONLH;
            };
          };
          union {
            __IO uint16_t IRQ097MONH;
            struct {
              __IO uint8_t IRQ097MONHL;
              __IO uint8_t IRQ097MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ098MON;
        stc_intreq_irq098mon_field_t IRQ098MON_f;
        struct {
          union {
            __IO uint16_t IRQ098MONL;
            struct {
              __IO uint8_t IRQ098MONLL;
              __IO uint8_t IRQ098MONLH;
            };
          };
          union {
            __IO uint16_t IRQ098MONH;
            struct {
              __IO uint8_t IRQ098MONHL;
              __IO uint8_t IRQ098MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ099MON;
        stc_intreq_irq099mon_field_t IRQ099MON_f;
        struct {
          union {
            __IO uint16_t IRQ099MONL;
            struct {
              __IO uint8_t IRQ099MONLL;
              __IO uint8_t IRQ099MONLH;
            };
          };
          union {
            __IO uint16_t IRQ099MONH;
            struct {
              __IO uint8_t IRQ099MONHL;
              __IO uint8_t IRQ099MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ100MON;
        stc_intreq_irq100mon_field_t IRQ100MON_f;
        struct {
          union {
            __IO uint16_t IRQ100MONL;
            struct {
              __IO uint8_t IRQ100MONLL;
              __IO uint8_t IRQ100MONLH;
            };
          };
          union {
            __IO uint16_t IRQ100MONH;
            struct {
              __IO uint8_t IRQ100MONHL;
              __IO uint8_t IRQ100MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ101MON;
        stc_intreq_irq101mon_field_t IRQ101MON_f;
        struct {
          union {
            __IO uint16_t IRQ101MONL;
            struct {
              __IO uint8_t IRQ101MONLL;
              __IO uint8_t IRQ101MONLH;
            };
          };
          union {
            __IO uint16_t IRQ101MONH;
            struct {
              __IO uint8_t IRQ101MONHL;
              __IO uint8_t IRQ101MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ102MON;
        stc_intreq_irq102mon_field_t IRQ102MON_f;
        struct {
          union {
            __IO uint16_t IRQ102MONL;
            struct {
              __IO uint8_t IRQ102MONLL;
              __IO uint8_t IRQ102MONLH;
            };
          };
          union {
            __IO uint16_t IRQ102MONH;
            struct {
              __IO uint8_t IRQ102MONHL;
              __IO uint8_t IRQ102MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ103MON;
        stc_intreq_irq103mon_field_t IRQ103MON_f;
        struct {
          union {
            __IO uint16_t IRQ103MONL;
            struct {
              __IO uint8_t IRQ103MONLL;
              __IO uint8_t IRQ103MONLH;
            };
          };
          union {
            __IO uint16_t IRQ103MONH;
            struct {
              __IO uint8_t IRQ103MONHL;
              __IO uint8_t IRQ103MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ104MON;
        stc_intreq_irq104mon_field_t IRQ104MON_f;
        struct {
          union {
            __IO uint16_t IRQ104MONL;
            struct {
              __IO uint8_t IRQ104MONLL;
              __IO uint8_t IRQ104MONLH;
            };
          };
          union {
            __IO uint16_t IRQ104MONH;
            struct {
              __IO uint8_t IRQ104MONHL;
              __IO uint8_t IRQ104MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ105MON;
        stc_intreq_irq105mon_field_t IRQ105MON_f;
        struct {
          union {
            __IO uint16_t IRQ105MONL;
            struct {
              __IO uint8_t IRQ105MONLL;
              __IO uint8_t IRQ105MONLH;
            };
          };
          union {
            __IO uint16_t IRQ105MONH;
            struct {
              __IO uint8_t IRQ105MONHL;
              __IO uint8_t IRQ105MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ106MON;
        stc_intreq_irq106mon_field_t IRQ106MON_f;
        struct {
          union {
            __IO uint16_t IRQ106MONL;
            struct {
              __IO uint8_t IRQ106MONLL;
              __IO uint8_t IRQ106MONLH;
            };
          };
          union {
            __IO uint16_t IRQ106MONH;
            struct {
              __IO uint8_t IRQ106MONHL;
              __IO uint8_t IRQ106MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ107MON;
        stc_intreq_irq107mon_field_t IRQ107MON_f;
        struct {
          union {
            __IO uint16_t IRQ107MONL;
            struct {
              __IO uint8_t IRQ107MONLL;
              __IO uint8_t IRQ107MONLH;
            };
          };
          union {
            __IO uint16_t IRQ107MONH;
            struct {
              __IO uint8_t IRQ107MONHL;
              __IO uint8_t IRQ107MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ108MON;
        stc_intreq_irq108mon_field_t IRQ108MON_f;
        struct {
          union {
            __IO uint16_t IRQ108MONL;
            struct {
              __IO uint8_t IRQ108MONLL;
              __IO uint8_t IRQ108MONLH;
            };
          };
          union {
            __IO uint16_t IRQ108MONH;
            struct {
              __IO uint8_t IRQ108MONHL;
              __IO uint8_t IRQ108MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ109MON;
        stc_intreq_irq109mon_field_t IRQ109MON_f;
        struct {
          union {
            __IO uint16_t IRQ109MONL;
            struct {
              __IO uint8_t IRQ109MONLL;
              __IO uint8_t IRQ109MONLH;
            };
          };
          union {
            __IO uint16_t IRQ109MONH;
            struct {
              __IO uint8_t IRQ109MONHL;
              __IO uint8_t IRQ109MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ110MON;
        stc_intreq_irq110mon_field_t IRQ110MON_f;
        struct {
          union {
            __IO uint16_t IRQ110MONL;
            struct {
              __IO uint8_t IRQ110MONLL;
              __IO uint8_t IRQ110MONLH;
            };
          };
          union {
            __IO uint16_t IRQ110MONH;
            struct {
              __IO uint8_t IRQ110MONHL;
              __IO uint8_t IRQ110MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ111MON;
        stc_intreq_irq111mon_field_t IRQ111MON_f;
        struct {
          union {
            __IO uint16_t IRQ111MONL;
            struct {
              __IO uint8_t IRQ111MONLL;
              __IO uint8_t IRQ111MONLH;
            };
          };
          union {
            __IO uint16_t IRQ111MONH;
            struct {
              __IO uint8_t IRQ111MONHL;
              __IO uint8_t IRQ111MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ112MON;
        stc_intreq_irq112mon_field_t IRQ112MON_f;
        struct {
          union {
            __IO uint16_t IRQ112MONL;
            struct {
              __IO uint8_t IRQ112MONLL;
              __IO uint8_t IRQ112MONLH;
            };
          };
          union {
            __IO uint16_t IRQ112MONH;
            struct {
              __IO uint8_t IRQ112MONHL;
              __IO uint8_t IRQ112MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ113MON;
        stc_intreq_irq113mon_field_t IRQ113MON_f;
        struct {
          union {
            __IO uint16_t IRQ113MONL;
            struct {
              __IO uint8_t IRQ113MONLL;
              __IO uint8_t IRQ113MONLH;
            };
          };
          union {
            __IO uint16_t IRQ113MONH;
            struct {
              __IO uint8_t IRQ113MONHL;
              __IO uint8_t IRQ113MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ114MON;
        stc_intreq_irq114mon_field_t IRQ114MON_f;
        struct {
          union {
            __IO uint16_t IRQ114MONL;
            struct {
              __IO uint8_t IRQ114MONLL;
              __IO uint8_t IRQ114MONLH;
            };
          };
          union {
            __IO uint16_t IRQ114MONH;
            struct {
              __IO uint8_t IRQ114MONHL;
              __IO uint8_t IRQ114MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ115MON;
        stc_intreq_irq115mon_field_t IRQ115MON_f;
        struct {
          union {
            __IO uint16_t IRQ115MONL;
            struct {
              __IO uint8_t IRQ115MONLL;
              __IO uint8_t IRQ115MONLH;
            };
          };
          union {
            __IO uint16_t IRQ115MONH;
            struct {
              __IO uint8_t IRQ115MONHL;
              __IO uint8_t IRQ115MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ116MON;
        struct {
          union {
            __IO uint16_t IRQ116MONL;
            struct {
              __IO uint8_t IRQ116MONLL;
              __IO uint8_t IRQ116MONLH;
            };
          };
          union {
            __IO uint16_t IRQ116MONH;
            struct {
              __IO uint8_t IRQ116MONHL;
              __IO uint8_t IRQ116MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ117MON;
        stc_intreq_irq117mon_field_t IRQ117MON_f;
        struct {
          union {
            __IO uint16_t IRQ117MONL;
            struct {
              __IO uint8_t IRQ117MONLL;
              __IO uint8_t IRQ117MONLH;
            };
          };
          union {
            __IO uint16_t IRQ117MONH;
            struct {
              __IO uint8_t IRQ117MONHL;
              __IO uint8_t IRQ117MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ118MON;
        stc_intreq_irq118mon_field_t IRQ118MON_f;
        struct {
          union {
            __IO uint16_t IRQ118MONL;
            struct {
              __IO uint8_t IRQ118MONLL;
              __IO uint8_t IRQ118MONLH;
            };
          };
          union {
            __IO uint16_t IRQ118MONH;
            struct {
              __IO uint8_t IRQ118MONHL;
              __IO uint8_t IRQ118MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ119MON;
        stc_intreq_irq119mon_field_t IRQ119MON_f;
        struct {
          union {
            __IO uint16_t IRQ119MONL;
            struct {
              __IO uint8_t IRQ119MONLL;
              __IO uint8_t IRQ119MONLH;
            };
          };
          union {
            __IO uint16_t IRQ119MONH;
            struct {
              __IO uint8_t IRQ119MONHL;
              __IO uint8_t IRQ119MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ120MON;
        stc_intreq_irq120mon_field_t IRQ120MON_f;
        struct {
          union {
            __IO uint16_t IRQ120MONL;
            struct {
              __IO uint8_t IRQ120MONLL;
              __IO uint8_t IRQ120MONLH;
            };
          };
          union {
            __IO uint16_t IRQ120MONH;
            struct {
              __IO uint8_t IRQ120MONHL;
              __IO uint8_t IRQ120MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ121MON;
        stc_intreq_irq121mon_field_t IRQ121MON_f;
        struct {
          union {
            __IO uint16_t IRQ121MONL;
            struct {
              __IO uint8_t IRQ121MONLL;
              __IO uint8_t IRQ121MONLH;
            };
          };
          union {
            __IO uint16_t IRQ121MONH;
            struct {
              __IO uint8_t IRQ121MONHL;
              __IO uint8_t IRQ121MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ122MON;
        stc_intreq_irq122mon_field_t IRQ122MON_f;
        struct {
          union {
            __IO uint16_t IRQ122MONL;
            struct {
              __IO uint8_t IRQ122MONLL;
              __IO uint8_t IRQ122MONLH;
            };
          };
          union {
            __IO uint16_t IRQ122MONH;
            struct {
              __IO uint8_t IRQ122MONHL;
              __IO uint8_t IRQ122MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ123MON;
        stc_intreq_irq123mon_field_t IRQ123MON_f;
        struct {
          union {
            __IO uint16_t IRQ123MONL;
            struct {
              __IO uint8_t IRQ123MONLL;
              __IO uint8_t IRQ123MONLH;
            };
          };
          union {
            __IO uint16_t IRQ123MONH;
            struct {
              __IO uint8_t IRQ123MONHL;
              __IO uint8_t IRQ123MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ124MON;
        stc_intreq_irq124mon_field_t IRQ124MON_f;
        struct {
          union {
            __IO uint16_t IRQ124MONL;
            struct {
              __IO uint8_t IRQ124MONLL;
              __IO uint8_t IRQ124MONLH;
            };
          };
          union {
            __IO uint16_t IRQ124MONH;
            struct {
              __IO uint8_t IRQ124MONHL;
              __IO uint8_t IRQ124MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ125MON;
        stc_intreq_irq125mon_field_t IRQ125MON_f;
        struct {
          union {
            __IO uint16_t IRQ125MONL;
            struct {
              __IO uint8_t IRQ125MONLL;
              __IO uint8_t IRQ125MONLH;
            };
          };
          union {
            __IO uint16_t IRQ125MONH;
            struct {
              __IO uint8_t IRQ125MONHL;
              __IO uint8_t IRQ125MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ126MON;
        stc_intreq_irq126mon_field_t IRQ126MON_f;
        struct {
          union {
            __IO uint16_t IRQ126MONL;
            struct {
              __IO uint8_t IRQ126MONLL;
              __IO uint8_t IRQ126MONLH;
            };
          };
          union {
            __IO uint16_t IRQ126MONH;
            struct {
              __IO uint8_t IRQ126MONHL;
              __IO uint8_t IRQ126MONHH;
            };
          };
        };
    };
    union {
        __IO uint32_t IRQ127MON;
        stc_intreq_irq127mon_field_t IRQ127MON_f;
        struct {
          union {
            __IO uint16_t IRQ127MONL;
            struct {
              __IO uint8_t IRQ127MONLL;
              __IO uint8_t IRQ127MONLH;
            };
          };
          union {
            __IO uint16_t IRQ127MONH;
            struct {
              __IO uint8_t IRQ127MONHL;
              __IO uint8_t IRQ127MONHH;
            };
          };
        };
    };
} FM_INTREQ_TypeDef, FM4_INTREQ_TypeDef;

/*******************************************************************************
* LSCRP_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO  uint8_t LCR_PRSLD;
        stc_lscrp_lcr_prsld_field_t LCR_PRSLD_f;
    };
} FM_LSCRP_TypeDef, FM4_LSCRP_TypeDef;

/*******************************************************************************
* LVD_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO  uint8_t LVD_CTL;
        stc_lvd_lvd_ctl_field_t LVD_CTL_f;
    };
        __IO  uint8_t RESERVED0[3];
    union {
        __IO  uint8_t LVD_STR;
        stc_lvd_lvd_str_field_t LVD_STR_f;
    };
        __IO  uint8_t RESERVED1[3];
    union {
        __IO  uint8_t LVD_CLR;
        stc_lvd_lvd_clr_field_t LVD_CLR_f;
    };
        __IO  uint8_t RESERVED2[3];
    union {
        __IO uint32_t LVD_RLR;
        stc_lvd_lvd_rlr_field_t LVD_RLR_f;
        struct {
          union {
            __IO uint16_t LVD_RLRL;
            struct {
              __IO uint8_t LVD_RLRLL;
              __IO uint8_t LVD_RLRLH;
            };
          };
          union {
            __IO uint16_t LVD_RLRH;
            struct {
              __IO uint8_t LVD_RLRHL;
              __IO uint8_t LVD_RLRHH;
            };
          };
        };
    };
    union {
        __IO  uint8_t LVD_STR2;
        stc_lvd_lvd_str2_field_t LVD_STR2_f;
    };
} FM_LVD_TypeDef, FM4_LVD_TypeDef;

/*******************************************************************************
* MFS_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO  uint8_t SMR;
        stc_mfs_smr_field_t SMR_f;
        __IO  uint8_t CSIO_SMR;
        stc_mfs_csio_smr_field_t CSIO_SMR_f;
        __IO  uint8_t I2C_SMR;
        stc_mfs_i2c_smr_field_t I2C_SMR_f;
        __IO  uint8_t LIN_SMR;
        stc_mfs_lin_smr_field_t LIN_SMR_f;
        __IO  uint8_t UART_SMR;
        stc_mfs_uart_smr_field_t UART_SMR_f;
    };
    union {
        __IO  uint8_t SCR;
        stc_mfs_scr_field_t SCR_f;
        __IO  uint8_t CSIO_SCR;
        stc_mfs_csio_scr_field_t CSIO_SCR_f;
        __IO  uint8_t IBCR;
        stc_mfs_ibcr_field_t IBCR_f;
        __IO  uint8_t I2C_IBCR;
        stc_mfs_i2c_ibcr_field_t I2C_IBCR_f;
        __IO  uint8_t LIN_SCR;
        stc_mfs_lin_scr_field_t LIN_SCR_f;
        __IO  uint8_t UART_SCR;
        stc_mfs_uart_scr_field_t UART_SCR_f;
    };
        __IO  uint8_t RESERVED0[2];
    union {
        __IO  uint8_t ESCR;
        stc_mfs_escr_field_t ESCR_f;
        __IO  uint8_t CSIO_ESCR;
        stc_mfs_csio_escr_field_t CSIO_ESCR_f;
        __IO  uint8_t IBSR;
        stc_mfs_ibsr_field_t IBSR_f;
        __IO  uint8_t I2C_IBSR;
        stc_mfs_i2c_ibsr_field_t I2C_IBSR_f;
        __IO  uint8_t LIN_ESCR;
        stc_mfs_lin_escr_field_t LIN_ESCR_f;
        __IO  uint8_t UART_ESCR;
        stc_mfs_uart_escr_field_t UART_ESCR_f;
    };
    union {
        __IO  uint8_t SSR;
        stc_mfs_ssr_field_t SSR_f;
        __IO  uint8_t CSIO_SSR;
        stc_mfs_csio_ssr_field_t CSIO_SSR_f;
        __IO  uint8_t I2C_SSR;
        stc_mfs_i2c_ssr_field_t I2C_SSR_f;
        __IO  uint8_t LIN_SSR;
        stc_mfs_lin_ssr_field_t LIN_SSR_f;
        __IO  uint8_t UART_SSR;
        stc_mfs_uart_ssr_field_t UART_SSR_f;
    };
        __IO  uint8_t RESERVED1[2];
    union {
        __IO uint16_t RDR;
        stc_mfs_rdr_field_t RDR_f;
        struct {
            __IO  uint8_t RDRL;
            __IO  uint8_t RDRH;
        };
        __IO uint16_t CSIO_RDR;
        stc_mfs_csio_rdr_field_t CSIO_RDR_f;
        struct {
            __IO  uint8_t CSIO_RDRL;
            __IO  uint8_t CSIO_RDRH;
        };
        __IO uint16_t TDR;
        stc_mfs_tdr_field_t TDR_f;
        struct {
            __IO  uint8_t TDRL;
            __IO  uint8_t TDRH;
        };
        __IO uint16_t CSIO_TDR;
        stc_mfs_csio_tdr_field_t CSIO_TDR_f;
        struct {
            __IO  uint8_t CSIO_TDRL;
            __IO  uint8_t CSIO_TDRH;
        };
        __IO uint16_t I2C_RDR;
        stc_mfs_i2c_rdr_field_t I2C_RDR_f;
        struct {
            __IO  uint8_t I2C_RDRL;
            __IO  uint8_t I2C_RDRH;
        };
        __IO uint16_t I2C_TDR;
        stc_mfs_i2c_tdr_field_t I2C_TDR_f;
        struct {
            __IO  uint8_t I2C_TDRL;
            __IO  uint8_t I2C_TDRH;
        };
        __IO uint16_t LIN_RDR;
        stc_mfs_lin_rdr_field_t LIN_RDR_f;
        struct {
            __IO  uint8_t LIN_RDRL;
            __IO  uint8_t LIN_RDRH;
        };
        __IO uint16_t LIN_TDR;
        stc_mfs_lin_tdr_field_t LIN_TDR_f;
        struct {
            __IO  uint8_t LIN_TDRL;
            __IO  uint8_t LIN_TDRH;
        };
        __IO uint16_t UART_RDR;
        stc_mfs_uart_rdr_field_t UART_RDR_f;
        struct {
            __IO  uint8_t UART_RDRL;
            __IO  uint8_t UART_RDRH;
        };
        __IO uint16_t UART_TDR;
        stc_mfs_uart_tdr_field_t UART_TDR_f;
        struct {
            __IO  uint8_t UART_TDRL;
            __IO  uint8_t UART_TDRH;
        };
    };
        __IO  uint8_t RESERVED2[2];
    union {
        __IO uint16_t BGR;
        stc_mfs_bgr_field_t BGR_f;
        struct {
            __IO  uint8_t BGRL;
            __IO  uint8_t BGRH;
        };
        __IO uint16_t CSIO_BGR;
        stc_mfs_csio_bgr_field_t CSIO_BGR_f;
        struct {
            __IO  uint8_t CSIO_BGRL;
            __IO  uint8_t CSIO_BGRH;
        };
        __IO uint16_t I2C_BGR;
        stc_mfs_i2c_bgr_field_t I2C_BGR_f;
        struct {
            __IO  uint8_t I2C_BGRL;
            __IO  uint8_t I2C_BGRH;
        };
        __IO uint16_t LIN_BGR;
        stc_mfs_lin_bgr_field_t LIN_BGR_f;
        struct {
            __IO  uint8_t LIN_BGRL;
            __IO  uint8_t LIN_BGRH;
        };
        __IO uint16_t UART_BGR;
        stc_mfs_uart_bgr_field_t UART_BGR_f;
        struct {
            __IO  uint8_t UART_BGRL;
            __IO  uint8_t UART_BGRH;
        };
    };
        __IO  uint8_t RESERVED3[2];
    union {
        __IO  uint8_t ISBA;
        stc_mfs_isba_field_t ISBA_f;
        __IO  uint8_t I2C_ISBA;
        stc_mfs_i2c_isba_field_t I2C_ISBA_f;
    };
    union {
        __IO  uint8_t ISMK;
        stc_mfs_ismk_field_t ISMK_f;
        __IO  uint8_t I2C_ISMK;
        stc_mfs_i2c_ismk_field_t I2C_ISMK_f;
    };
        __IO  uint8_t RESERVED4[2];
    union {
        __IO uint16_t FCR;
        stc_mfs_fcr_field_t FCR_f;
        struct {
            __IO  uint8_t FCRL;
            __IO  uint8_t FCRH;
        };
        __IO uint16_t CSIO_FCR;
        stc_mfs_csio_fcr_field_t CSIO_FCR_f;
        struct {
            __IO  uint8_t CSIO_FCRL;
            __IO  uint8_t CSIO_FCRH;
        };
        __IO uint16_t I2C_FCR;
        stc_mfs_i2c_fcr_field_t I2C_FCR_f;
        struct {
            __IO  uint8_t I2C_FCRL;
            __IO  uint8_t I2C_FCRH;
        };
        __IO uint16_t LIN_FCR;
        stc_mfs_lin_fcr_field_t LIN_FCR_f;
        struct {
            __IO  uint8_t LIN_FCRL;
            __IO  uint8_t LIN_FCRH;
        };
        __IO uint16_t UART_FCR;
        stc_mfs_uart_fcr_field_t UART_FCR_f;
        struct {
            __IO  uint8_t UART_FCRL;
            __IO  uint8_t UART_FCRH;
        };
    };
        __IO  uint8_t RESERVED5[2];
    union {
        __IO  uint8_t FBYTE1;
        stc_mfs_fbyte1_field_t FBYTE1_f;
        __IO  uint8_t CSIO_FBYTE1;
        stc_mfs_csio_fbyte1_field_t CSIO_FBYTE1_f;
        __IO  uint8_t I2C_FBYTE1;
        stc_mfs_i2c_fbyte1_field_t I2C_FBYTE1_f;
        __IO  uint8_t LIN_FBYTE1;
        stc_mfs_lin_fbyte1_field_t LIN_FBYTE1_f;
        __IO  uint8_t UART_FBYTE1;
        stc_mfs_uart_fbyte1_field_t UART_FBYTE1_f;
    };
    union {
        __IO  uint8_t FBYTE2;
        stc_mfs_fbyte2_field_t FBYTE2_f;
        __IO  uint8_t CSIO_FBYTE2;
        stc_mfs_csio_fbyte2_field_t CSIO_FBYTE2_f;
        __IO  uint8_t I2C_FBYTE2;
        stc_mfs_i2c_fbyte2_field_t I2C_FBYTE2_f;
        __IO  uint8_t LIN_FBYTE2;
        stc_mfs_lin_fbyte2_field_t LIN_FBYTE2_f;
        __IO  uint8_t UART_FBYTE2;
        stc_mfs_uart_fbyte2_field_t UART_FBYTE2_f;
    };
        __IO  uint8_t RESERVED6[2];
    union {
        __IO  uint8_t SCSTR0;
        stc_mfs_scstr0_field_t SCSTR0_f;
        __IO  uint8_t CSIO_SCSTR0;
        stc_mfs_csio_scstr0_field_t CSIO_SCSTR0_f;
        __IO  uint8_t NFCR;
        stc_mfs_nfcr_field_t NFCR_f;
        __IO  uint8_t I2C_NFCR;
        stc_mfs_i2c_nfcr_field_t I2C_NFCR_f;
    };
    union {
        __IO  uint8_t SCSTR1;
        stc_mfs_scstr1_field_t SCSTR1_f;
        __IO  uint8_t CSIO_SCSTR1;
        stc_mfs_csio_scstr1_field_t CSIO_SCSTR1_f;
        __IO  uint8_t EIBCR;
        stc_mfs_eibcr_field_t EIBCR_f;
        __IO  uint8_t I2C_EIBCR;
        stc_mfs_i2c_eibcr_field_t I2C_EIBCR_f;
    };
        __IO  uint8_t RESERVED7[2];
    union {
        __IO uint16_t SCSTR32;
        stc_mfs_scstr32_field_t SCSTR32_f;
        struct {
            __IO  uint8_t SCSTR32L;
            __IO  uint8_t SCSTR32H;
        };
        __IO uint16_t CSIO_SCSTR32;
        stc_mfs_csio_scstr32_field_t CSIO_SCSTR32_f;
        struct {
            __IO  uint8_t CSIO_SCSTR32L;
            __IO  uint8_t CSIO_SCSTR32H;
        };
    };
        __IO  uint8_t RESERVED8[2];
    union {
        __IO uint16_t SACSR;
        stc_mfs_sacsr_field_t SACSR_f;
        struct {
            __IO  uint8_t SACSRL;
            __IO  uint8_t SACSRH;
        };
        __IO uint16_t CSIO_SACSR;
        stc_mfs_csio_sacsr_field_t CSIO_SACSR_f;
        struct {
            __IO  uint8_t CSIO_SACSRL;
            __IO  uint8_t CSIO_SACSRH;
        };
    };
        __IO  uint8_t RESERVED9[2];
    union {
        __IO uint16_t STMR;
        stc_mfs_stmr_field_t STMR_f;
        struct {
            __IO  uint8_t STMRL;
            __IO  uint8_t STMRH;
        };
        __IO uint16_t CSIO_STMR;
        stc_mfs_csio_stmr_field_t CSIO_STMR_f;
        struct {
            __IO  uint8_t CSIO_STMRL;
            __IO  uint8_t CSIO_STMRH;
        };
    };
        __IO  uint8_t RESERVED10[2];
    union {
        __IO uint16_t STMCR;
        stc_mfs_stmcr_field_t STMCR_f;
        struct {
            __IO  uint8_t STMCRL;
            __IO  uint8_t STMCRH;
        };
        __IO uint16_t CSIO_STMCR;
        stc_mfs_csio_stmcr_field_t CSIO_STMCR_f;
        struct {
            __IO  uint8_t CSIO_STMCRL;
            __IO  uint8_t CSIO_STMCRH;
        };
    };
        __IO  uint8_t RESERVED11[2];
    union {
        __IO uint16_t SCSCR;
        stc_mfs_scscr_field_t SCSCR_f;
        struct {
            __IO  uint8_t SCSCRL;
            __IO  uint8_t SCSCRH;
        };
        __IO uint16_t CSIO_SCSCR;
        stc_mfs_csio_scscr_field_t CSIO_SCSCR_f;
        struct {
            __IO  uint8_t CSIO_SCSCRL;
            __IO  uint8_t CSIO_SCSCRH;
        };
    };
        __IO  uint8_t RESERVED12[2];
    union {
        __IO  uint8_t SCSFR0;
        stc_mfs_scsfr0_field_t SCSFR0_f;
        __IO  uint8_t CSIO_SCSFR0;
        stc_mfs_csio_scsfr0_field_t CSIO_SCSFR0_f;
    };
    union {
        __IO  uint8_t SCSFR1;
        stc_mfs_scsfr1_field_t SCSFR1_f;
        __IO  uint8_t CSIO_SCSFR1;
        stc_mfs_csio_scsfr1_field_t CSIO_SCSFR1_f;
    };
        __IO  uint8_t RESERVED13[2];
    union {
        __IO  uint8_t SCSFR2;
        stc_mfs_scsfr2_field_t SCSFR2_f;
        __IO  uint8_t CSIO_SCSFR2;
        stc_mfs_csio_scsfr2_field_t CSIO_SCSFR2_f;
    };
        __IO  uint8_t RESERVED14[3];
    union {
        __IO  uint8_t TBYTE0;
        __IO  uint8_t CSIO_TBYTE0;
    };
    union {
        __IO  uint8_t TBYTE1;
        __IO  uint8_t CSIO_TBYTE1;
    };
        __IO  uint8_t RESERVED15[2];
    union {
        __IO  uint8_t TBYTE2;
        __IO  uint8_t CSIO_TBYTE2;
    };
    union {
        __IO  uint8_t TBYTE3;
        __IO  uint8_t CSIO_TBYTE3;
    };
} FM_MFS_TypeDef, FM4_MFS_TypeDef;

/*******************************************************************************
* MFS_CSIO_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO  uint8_t SMR;
        stc_mfs_csio_smr_field_t SMR_f;
    };
    union {
        __IO  uint8_t SCR;
        stc_mfs_csio_scr_field_t SCR_f;
    };
        __IO  uint8_t RESERVED16[2];
    union {
        __IO  uint8_t ESCR;
        stc_mfs_csio_escr_field_t ESCR_f;
    };
    union {
        __IO  uint8_t SSR;
        stc_mfs_csio_ssr_field_t SSR_f;
    };
        __IO  uint8_t RESERVED17[2];
    union {
        __IO uint16_t RDR;
        stc_mfs_csio_rdr_field_t RDR_f;
        struct {
            __IO  uint8_t RDRL;
            __IO  uint8_t RDRH;
        };
        __IO uint16_t TDR;
        stc_mfs_csio_tdr_field_t TDR_f;
        struct {
            __IO  uint8_t TDRL;
            __IO  uint8_t TDRH;
        };
    };
        __IO  uint8_t RESERVED18[2];
    union {
        __IO uint16_t BGR;
        stc_mfs_csio_bgr_field_t BGR_f;
        struct {
            __IO  uint8_t BGRL;
            __IO  uint8_t BGRH;
        };
    };
        __IO  uint8_t RESERVED19[6];
    union {
        __IO uint16_t FCR;
        stc_mfs_csio_fcr_field_t FCR_f;
        struct {
            __IO  uint8_t FCRL;
            __IO  uint8_t FCRH;
        };
    };
        __IO  uint8_t RESERVED20[2];
    union {
        __IO  uint8_t FBYTE1;
        stc_mfs_csio_fbyte1_field_t FBYTE1_f;
    };
    union {
        __IO  uint8_t FBYTE2;
        stc_mfs_csio_fbyte2_field_t FBYTE2_f;
    };
        __IO  uint8_t RESERVED21[2];
    union {
        __IO  uint8_t SCSTR0;
        stc_mfs_csio_scstr0_field_t SCSTR0_f;
    };
    union {
        __IO  uint8_t SCSTR1;
        stc_mfs_csio_scstr1_field_t SCSTR1_f;
    };
        __IO  uint8_t RESERVED22[2];
    union {
        __IO uint16_t SCSTR32;
        stc_mfs_csio_scstr32_field_t SCSTR32_f;
        struct {
            __IO  uint8_t SCSTR32L;
            __IO  uint8_t SCSTR32H;
        };
    };
        __IO  uint8_t RESERVED23[2];
    union {
        __IO uint16_t SACSR;
        stc_mfs_csio_sacsr_field_t SACSR_f;
        struct {
            __IO  uint8_t SACSRL;
            __IO  uint8_t SACSRH;
        };
    };
        __IO  uint8_t RESERVED24[2];
    union {
        __IO uint16_t STMR;
        stc_mfs_csio_stmr_field_t STMR_f;
        struct {
            __IO  uint8_t STMRL;
            __IO  uint8_t STMRH;
        };
    };
        __IO  uint8_t RESERVED25[2];
    union {
        __IO uint16_t STMCR;
        stc_mfs_csio_stmcr_field_t STMCR_f;
        struct {
            __IO  uint8_t STMCRL;
            __IO  uint8_t STMCRH;
        };
    };
        __IO  uint8_t RESERVED26[2];
    union {
        __IO uint16_t SCSCR;
        stc_mfs_csio_scscr_field_t SCSCR_f;
        struct {
            __IO  uint8_t SCSCRL;
            __IO  uint8_t SCSCRH;
        };
    };
        __IO  uint8_t RESERVED27[2];
    union {
        __IO  uint8_t SCSFR0;
        stc_mfs_csio_scsfr0_field_t SCSFR0_f;
    };
    union {
        __IO  uint8_t SCSFR1;
        stc_mfs_csio_scsfr1_field_t SCSFR1_f;
    };
        __IO  uint8_t RESERVED28[2];
    union {
        __IO  uint8_t SCSFR2;
        stc_mfs_csio_scsfr2_field_t SCSFR2_f;
    };
        __IO  uint8_t RESERVED29[3];
        __IO  uint8_t TBYTE0;
        __IO  uint8_t TBYTE1;
        __IO  uint8_t RESERVED30[2];
        __IO  uint8_t TBYTE2;
        __IO  uint8_t TBYTE3;
} FM_MFS_CSIO_TypeDef, FM4_MFS_CSIO_TypeDef;

/*******************************************************************************
* MFS_I2C_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO  uint8_t SMR;
        stc_mfs_i2c_smr_field_t SMR_f;
    };
    union {
        __IO  uint8_t IBCR;
        stc_mfs_i2c_ibcr_field_t IBCR_f;
    };
        __IO  uint8_t RESERVED31[2];
    union {
        __IO  uint8_t IBSR;
        stc_mfs_i2c_ibsr_field_t IBSR_f;
    };
    union {
        __IO  uint8_t SSR;
        stc_mfs_i2c_ssr_field_t SSR_f;
    };
        __IO  uint8_t RESERVED32[2];
    union {
        __IO uint16_t RDR;
        stc_mfs_i2c_rdr_field_t RDR_f;
        struct {
            __IO  uint8_t RDRL;
            __IO  uint8_t RDRH;
        };
        __IO uint16_t TDR;
        stc_mfs_i2c_tdr_field_t TDR_f;
        struct {
            __IO  uint8_t TDRL;
            __IO  uint8_t TDRH;
        };
    };
        __IO  uint8_t RESERVED33[2];
    union {
        __IO uint16_t BGR;
        stc_mfs_i2c_bgr_field_t BGR_f;
        struct {
            __IO  uint8_t BGRL;
            __IO  uint8_t BGRH;
        };
    };
        __IO  uint8_t RESERVED34[2];
    union {
        __IO  uint8_t ISBA;
        stc_mfs_i2c_isba_field_t ISBA_f;
    };
    union {
        __IO  uint8_t ISMK;
        stc_mfs_i2c_ismk_field_t ISMK_f;
    };
        __IO  uint8_t RESERVED35[2];
    union {
        __IO uint16_t FCR;
        stc_mfs_i2c_fcr_field_t FCR_f;
        struct {
            __IO  uint8_t FCRL;
            __IO  uint8_t FCRH;
        };
    };
        __IO  uint8_t RESERVED36[2];
    union {
        __IO  uint8_t FBYTE1;
        stc_mfs_i2c_fbyte1_field_t FBYTE1_f;
    };
    union {
        __IO  uint8_t FBYTE2;
        stc_mfs_i2c_fbyte2_field_t FBYTE2_f;
    };
        __IO  uint8_t RESERVED37[2];
    union {
        __IO  uint8_t NFCR;
        stc_mfs_i2c_nfcr_field_t NFCR_f;
    };
    union {
        __IO  uint8_t EIBCR;
        stc_mfs_i2c_eibcr_field_t EIBCR_f;
    };
} FM_MFS_I2C_TypeDef, FM4_MFS_I2C_TypeDef;

/*******************************************************************************
* MFS_LIN_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO  uint8_t SMR;
        stc_mfs_lin_smr_field_t SMR_f;
    };
    union {
        __IO  uint8_t SCR;
        stc_mfs_lin_scr_field_t SCR_f;
    };
        __IO  uint8_t RESERVED38[2];
    union {
        __IO  uint8_t ESCR;
        stc_mfs_lin_escr_field_t ESCR_f;
    };
    union {
        __IO  uint8_t SSR;
        stc_mfs_lin_ssr_field_t SSR_f;
    };
        __IO  uint8_t RESERVED39[2];
    union {
        __IO uint16_t RDR;
        stc_mfs_lin_rdr_field_t RDR_f;
        struct {
            __IO  uint8_t RDRL;
            __IO  uint8_t RDRH;
        };
        __IO uint16_t TDR;
        stc_mfs_lin_tdr_field_t TDR_f;
        struct {
            __IO  uint8_t TDRL;
            __IO  uint8_t TDRH;
        };
    };
        __IO  uint8_t RESERVED40[2];
    union {
        __IO uint16_t BGR;
        stc_mfs_lin_bgr_field_t BGR_f;
        struct {
            __IO  uint8_t BGRL;
            __IO  uint8_t BGRH;
        };
    };
        __IO  uint8_t RESERVED41[6];
    union {
        __IO uint16_t FCR;
        stc_mfs_lin_fcr_field_t FCR_f;
        struct {
            __IO  uint8_t FCRL;
            __IO  uint8_t FCRH;
        };
    };
        __IO  uint8_t RESERVED42[2];
    union {
        __IO  uint8_t FBYTE1;
        stc_mfs_lin_fbyte1_field_t FBYTE1_f;
    };
    union {
        __IO  uint8_t FBYTE2;
        stc_mfs_lin_fbyte2_field_t FBYTE2_f;
    };
} FM_MFS_LIN_TypeDef, FM4_MFS_LIN_TypeDef;

/*******************************************************************************
* MFS_UART_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO  uint8_t SMR;
        stc_mfs_uart_smr_field_t SMR_f;
    };
    union {
        __IO  uint8_t SCR;
        stc_mfs_uart_scr_field_t SCR_f;
    };
        __IO  uint8_t RESERVED43[2];
    union {
        __IO  uint8_t ESCR;
        stc_mfs_uart_escr_field_t ESCR_f;
    };
    union {
        __IO  uint8_t SSR;
        stc_mfs_uart_ssr_field_t SSR_f;
    };
        __IO  uint8_t RESERVED44[2];
    union {
        __IO uint16_t RDR;
        stc_mfs_uart_rdr_field_t RDR_f;
        struct {
            __IO  uint8_t RDRL;
            __IO  uint8_t RDRH;
        };
        __IO uint16_t TDR;
        stc_mfs_uart_tdr_field_t TDR_f;
        struct {
            __IO  uint8_t TDRL;
            __IO  uint8_t TDRH;
        };
    };
        __IO  uint8_t RESERVED45[2];
    union {
        __IO uint16_t BGR;
        stc_mfs_uart_bgr_field_t BGR_f;
        struct {
            __IO  uint8_t BGRL;
            __IO  uint8_t BGRH;
        };
    };
        __IO  uint8_t RESERVED46[6];
    union {
        __IO uint16_t FCR;
        stc_mfs_uart_fcr_field_t FCR_f;
        struct {
            __IO  uint8_t FCRL;
            __IO  uint8_t FCRH;
        };
    };
        __IO  uint8_t RESERVED47[2];
    union {
        __IO  uint8_t FBYTE1;
        stc_mfs_uart_fbyte1_field_t FBYTE1_f;
    };
    union {
        __IO  uint8_t FBYTE2;
        stc_mfs_uart_fbyte2_field_t FBYTE2_f;
    };
} FM_MFS_UART_TypeDef, FM4_MFS_UART_TypeDef;

/*******************************************************************************
* MFT_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
        __IO  uint8_t RESERVED0[258];
    union {
        __IO uint16_t OCCP0;
        struct {
            __IO  uint8_t OCCP0L;
            __IO  uint8_t OCCP0H;
        };
        __IO uint16_t OCU_OCCP0;
        struct {
            __IO  uint8_t OCU_OCCP0L;
            __IO  uint8_t OCU_OCCP0H;
        };
    };
        __IO  uint8_t RESERVED1[2];
    union {
        __IO uint16_t OCCP1;
        struct {
            __IO  uint8_t OCCP1L;
            __IO  uint8_t OCCP1H;
        };
        __IO uint16_t OCU_OCCP1;
        struct {
            __IO  uint8_t OCU_OCCP1L;
            __IO  uint8_t OCU_OCCP1H;
        };
    };
        __IO  uint8_t RESERVED2[2];
    union {
        __IO uint16_t OCCP2;
        struct {
            __IO  uint8_t OCCP2L;
            __IO  uint8_t OCCP2H;
        };
        __IO uint16_t OCU_OCCP2;
        struct {
            __IO  uint8_t OCU_OCCP2L;
            __IO  uint8_t OCU_OCCP2H;
        };
    };
        __IO  uint8_t RESERVED3[2];
    union {
        __IO uint16_t OCCP3;
        struct {
            __IO  uint8_t OCCP3L;
            __IO  uint8_t OCCP3H;
        };
        __IO uint16_t OCU_OCCP3;
        struct {
            __IO  uint8_t OCU_OCCP3L;
            __IO  uint8_t OCU_OCCP3H;
        };
    };
        __IO  uint8_t RESERVED4[2];
    union {
        __IO uint16_t OCCP4;
        struct {
            __IO  uint8_t OCCP4L;
            __IO  uint8_t OCCP4H;
        };
        __IO uint16_t OCU_OCCP4;
        struct {
            __IO  uint8_t OCU_OCCP4L;
            __IO  uint8_t OCU_OCCP4H;
        };
    };
        __IO  uint8_t RESERVED5[2];
    union {
        __IO uint16_t OCCP5;
        struct {
            __IO  uint8_t OCCP5L;
            __IO  uint8_t OCCP5H;
        };
        __IO uint16_t OCU_OCCP5;
        struct {
            __IO  uint8_t OCU_OCCP5L;
            __IO  uint8_t OCU_OCCP5H;
        };
    };
    union {
        __IO  uint8_t OCSA10;
        stc_mft_ocsa10_field_t OCSA10_f;
        __IO  uint8_t OCU_OCSA10;
        stc_mft_ocu_ocsa10_field_t OCU_OCSA10_f;
    };
    union {
        __IO  uint8_t OCSB10;
        stc_mft_ocsb10_field_t OCSB10_f;
        __IO  uint8_t OCU_OCSB10;
        stc_mft_ocu_ocsb10_field_t OCU_OCSB10_f;
    };
    union {
        __IO uint16_t OCSD10;
        stc_mft_ocsd10_field_t OCSD10_f;
        struct {
            __IO  uint8_t OCSD10L;
            __IO  uint8_t OCSD10H;
        };
        __IO uint16_t OCU_OCSD10;
        stc_mft_ocu_ocsd10_field_t OCU_OCSD10_f;
        struct {
            __IO  uint8_t OCU_OCSD10L;
            __IO  uint8_t OCU_OCSD10H;
        };
    };
    union {
        __IO  uint8_t OCSA32;
        stc_mft_ocsa32_field_t OCSA32_f;
        __IO  uint8_t OCU_OCSA32;
        stc_mft_ocu_ocsa32_field_t OCU_OCSA32_f;
    };
    union {
        __IO  uint8_t OCSB32;
        stc_mft_ocsb32_field_t OCSB32_f;
        __IO  uint8_t OCU_OCSB32;
        stc_mft_ocu_ocsb32_field_t OCU_OCSB32_f;
    };
    union {
        __IO uint16_t OCSD32;
        stc_mft_ocsd32_field_t OCSD32_f;
        struct {
            __IO  uint8_t OCSD32L;
            __IO  uint8_t OCSD32H;
        };
        __IO uint16_t OCU_OCSD32;
        stc_mft_ocu_ocsd32_field_t OCU_OCSD32_f;
        struct {
            __IO  uint8_t OCU_OCSD32L;
            __IO  uint8_t OCU_OCSD32H;
        };
    };
    union {
        __IO  uint8_t OCSA54;
        stc_mft_ocsa54_field_t OCSA54_f;
        __IO  uint8_t OCU_OCSA54;
        stc_mft_ocu_ocsa54_field_t OCU_OCSA54_f;
    };
    union {
        __IO  uint8_t OCSB54;
        stc_mft_ocsb54_field_t OCSB54_f;
        __IO  uint8_t OCU_OCSB54;
        stc_mft_ocu_ocsb54_field_t OCU_OCSB54_f;
    };
    union {
        __IO uint16_t OCSD54;
        stc_mft_ocsd54_field_t OCSD54_f;
        struct {
            __IO  uint8_t OCSD54L;
            __IO  uint8_t OCSD54H;
        };
        __IO uint16_t OCU_OCSD54;
        stc_mft_ocu_ocsd54_field_t OCU_OCSD54_f;
        struct {
            __IO  uint8_t OCU_OCSD54L;
            __IO  uint8_t OCU_OCSD54H;
        };
    };
        __IO  uint8_t RESERVED6[1];
    union {
        __IO  uint8_t OCSC;
        stc_mft_ocsc_field_t OCSC_f;
        __IO  uint8_t OCU_OCSC;
        stc_mft_ocu_ocsc_field_t OCU_OCSC_f;
    };
        __IO  uint8_t RESERVED7[2];
    union {
        __IO uint16_t OCSE0;
        stc_mft_ocse0_field_t OCSE0_f;
        struct {
            __IO  uint8_t OCSE0L;
            __IO  uint8_t OCSE0H;
        };
        __IO uint16_t OCU_OCSE0;
        stc_mft_ocu_ocse0_field_t OCU_OCSE0_f;
        struct {
            __IO  uint8_t OCU_OCSE0L;
            __IO  uint8_t OCU_OCSE0H;
        };
    };
        __IO  uint8_t RESERVED8[2];
    union {
        __IO uint32_t OCSE1;
        stc_mft_ocse1_field_t OCSE1_f;
        struct {
          union {
            __IO uint16_t OCSE1L;
            struct {
              __IO uint8_t OCSE1LL;
              __IO uint8_t OCSE1LH;
            };
          };
          union {
            __IO uint16_t OCSE1H;
            struct {
              __IO uint8_t OCSE1HL;
              __IO uint8_t OCSE1HH;
            };
          };
        };
        __IO uint32_t OCU_OCSE1;
        stc_mft_ocu_ocse1_field_t OCU_OCSE1_f;
        struct {
          union {
            __IO uint16_t OCU_OCSE1L;
            struct {
              __IO uint8_t OCU_OCSE1LL;
              __IO uint8_t OCU_OCSE1LH;
            };
          };
          union {
            __IO uint16_t OCU_OCSE1H;
            struct {
              __IO uint8_t OCU_OCSE1HL;
              __IO uint8_t OCU_OCSE1HH;
            };
          };
        };
    };
    union {
        __IO uint16_t OCSE2;
        stc_mft_ocse2_field_t OCSE2_f;
        struct {
            __IO  uint8_t OCSE2L;
            __IO  uint8_t OCSE2H;
        };
        __IO uint16_t OCU_OCSE2;
        stc_mft_ocu_ocse2_field_t OCU_OCSE2_f;
        struct {
            __IO  uint8_t OCU_OCSE2L;
            __IO  uint8_t OCU_OCSE2H;
        };
    };
        __IO  uint8_t RESERVED9[2];
    union {
        __IO uint32_t OCSE3;
        stc_mft_ocse3_field_t OCSE3_f;
        struct {
          union {
            __IO uint16_t OCSE3L;
            struct {
              __IO uint8_t OCSE3LL;
              __IO uint8_t OCSE3LH;
            };
          };
          union {
            __IO uint16_t OCSE3H;
            struct {
              __IO uint8_t OCSE3HL;
              __IO uint8_t OCSE3HH;
            };
          };
        };
        __IO uint32_t OCU_OCSE3;
        stc_mft_ocu_ocse3_field_t OCU_OCSE3_f;
        struct {
          union {
            __IO uint16_t OCU_OCSE3L;
            struct {
              __IO uint8_t OCU_OCSE3LL;
              __IO uint8_t OCU_OCSE3LH;
            };
          };
          union {
            __IO uint16_t OCU_OCSE3H;
            struct {
              __IO uint8_t OCU_OCSE3HL;
              __IO uint8_t OCU_OCSE3HH;
            };
          };
        };
    };
    union {
        __IO uint16_t OCSE4;
        stc_mft_ocse4_field_t OCSE4_f;
        struct {
            __IO  uint8_t OCSE4L;
            __IO  uint8_t OCSE4H;
        };
        __IO uint16_t OCU_OCSE4;
        stc_mft_ocu_ocse4_field_t OCU_OCSE4_f;
        struct {
            __IO  uint8_t OCU_OCSE4L;
            __IO  uint8_t OCU_OCSE4H;
        };
    };
        __IO  uint8_t RESERVED10[2];
    union {
        __IO uint32_t OCSE5;
        stc_mft_ocse5_field_t OCSE5_f;
        struct {
          union {
            __IO uint16_t OCSE5L;
            struct {
              __IO uint8_t OCSE5LL;
              __IO uint8_t OCSE5LH;
            };
          };
          union {
            __IO uint16_t OCSE5H;
            struct {
              __IO uint8_t OCSE5HL;
              __IO uint8_t OCSE5HH;
            };
          };
        };
        __IO uint32_t OCU_OCSE5;
        stc_mft_ocu_ocse5_field_t OCU_OCSE5_f;
        struct {
          union {
            __IO uint16_t OCU_OCSE5L;
            struct {
              __IO uint8_t OCU_OCSE5LL;
              __IO uint8_t OCU_OCSE5LH;
            };
          };
          union {
            __IO uint16_t OCU_OCSE5H;
            struct {
              __IO uint8_t OCU_OCSE5HL;
              __IO uint8_t OCU_OCSE5HH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED11[2];
    union {
        __IO uint16_t TCCP0;
        stc_mft_tccp0_field_t TCCP0_f;
        struct {
            __IO  uint8_t TCCP0L;
            __IO  uint8_t TCCP0H;
        };
        __IO uint16_t FRT_TCCP0;
        stc_mft_frt_tccp0_field_t FRT_TCCP0_f;
        struct {
            __IO  uint8_t FRT_TCCP0L;
            __IO  uint8_t FRT_TCCP0H;
        };
    };
        __IO  uint8_t RESERVED12[2];
    union {
        __IO uint16_t TCDT0;
        struct {
            __IO  uint8_t TCDT0L;
            __IO  uint8_t TCDT0H;
        };
        __IO uint16_t FRT_TCDT0;
        struct {
            __IO  uint8_t FRT_TCDT0L;
            __IO  uint8_t FRT_TCDT0H;
        };
    };
    union {
        __IO uint16_t TCSA0;
        stc_mft_tcsa0_field_t TCSA0_f;
        struct {
            __IO  uint8_t TCSA0L;
            __IO  uint8_t TCSA0H;
        };
        __IO uint16_t FRT_TCSA0;
        stc_mft_frt_tcsa0_field_t FRT_TCSA0_f;
        struct {
            __IO  uint8_t FRT_TCSA0L;
            __IO  uint8_t FRT_TCSA0H;
        };
    };
    union {
        __IO uint16_t TCSC0;
        stc_mft_tcsc0_field_t TCSC0_f;
        struct {
            __IO  uint8_t TCSC0L;
            __IO  uint8_t TCSC0H;
        };
        __IO uint16_t FRT_TCSC0;
        stc_mft_frt_tcsc0_field_t FRT_TCSC0_f;
        struct {
            __IO  uint8_t FRT_TCSC0L;
            __IO  uint8_t FRT_TCSC0H;
        };
    };
        __IO  uint8_t RESERVED13[2];
    union {
        __IO uint16_t TCCP1;
        stc_mft_tccp1_field_t TCCP1_f;
        struct {
            __IO  uint8_t TCCP1L;
            __IO  uint8_t TCCP1H;
        };
        __IO uint16_t FRT_TCCP1;
        stc_mft_frt_tccp1_field_t FRT_TCCP1_f;
        struct {
            __IO  uint8_t FRT_TCCP1L;
            __IO  uint8_t FRT_TCCP1H;
        };
    };
        __IO  uint8_t RESERVED14[2];
    union {
        __IO uint16_t TCDT1;
        struct {
            __IO  uint8_t TCDT1L;
            __IO  uint8_t TCDT1H;
        };
        __IO uint16_t FRT_TCDT1;
        struct {
            __IO  uint8_t FRT_TCDT1L;
            __IO  uint8_t FRT_TCDT1H;
        };
    };
    union {
        __IO uint16_t TCSA1;
        stc_mft_tcsa1_field_t TCSA1_f;
        struct {
            __IO  uint8_t TCSA1L;
            __IO  uint8_t TCSA1H;
        };
        __IO uint16_t FRT_TCSA1;
        stc_mft_frt_tcsa1_field_t FRT_TCSA1_f;
        struct {
            __IO  uint8_t FRT_TCSA1L;
            __IO  uint8_t FRT_TCSA1H;
        };
    };
    union {
        __IO uint16_t TCSC1;
        stc_mft_tcsc1_field_t TCSC1_f;
        struct {
            __IO  uint8_t TCSC1L;
            __IO  uint8_t TCSC1H;
        };
        __IO uint16_t FRT_TCSC1;
        stc_mft_frt_tcsc1_field_t FRT_TCSC1_f;
        struct {
            __IO  uint8_t FRT_TCSC1L;
            __IO  uint8_t FRT_TCSC1H;
        };
    };
        __IO  uint8_t RESERVED15[2];
    union {
        __IO uint16_t TCCP2;
        stc_mft_tccp2_field_t TCCP2_f;
        struct {
            __IO  uint8_t TCCP2L;
            __IO  uint8_t TCCP2H;
        };
        __IO uint16_t FRT_TCCP2;
        stc_mft_frt_tccp2_field_t FRT_TCCP2_f;
        struct {
            __IO  uint8_t FRT_TCCP2L;
            __IO  uint8_t FRT_TCCP2H;
        };
    };
        __IO  uint8_t RESERVED16[2];
    union {
        __IO uint16_t TCDT2;
        struct {
            __IO  uint8_t TCDT2L;
            __IO  uint8_t TCDT2H;
        };
        __IO uint16_t FRT_TCDT2;
        struct {
            __IO  uint8_t FRT_TCDT2L;
            __IO  uint8_t FRT_TCDT2H;
        };
    };
    union {
        __IO uint16_t TCSA2;
        stc_mft_tcsa2_field_t TCSA2_f;
        struct {
            __IO  uint8_t TCSA2L;
            __IO  uint8_t TCSA2H;
        };
        __IO uint16_t FRT_TCSA2;
        stc_mft_frt_tcsa2_field_t FRT_TCSA2_f;
        struct {
            __IO  uint8_t FRT_TCSA2L;
            __IO  uint8_t FRT_TCSA2H;
        };
    };
    union {
        __IO uint16_t TCSC2;
        stc_mft_tcsc2_field_t TCSC2_f;
        struct {
            __IO  uint8_t TCSC2L;
            __IO  uint8_t TCSC2H;
        };
        __IO uint16_t FRT_TCSC2;
        stc_mft_frt_tcsc2_field_t FRT_TCSC2_f;
        struct {
            __IO  uint8_t FRT_TCSC2L;
            __IO  uint8_t FRT_TCSC2H;
        };
    };
    union {
        __IO uint32_t TCAL;
        stc_mft_tcal_field_t TCAL_f;
        struct {
          union {
            __IO uint16_t TCALL;
            struct {
              __IO uint8_t TCALLL;
              __IO uint8_t TCALLH;
            };
          };
          union {
            __IO uint16_t TCALH;
            struct {
              __IO uint8_t TCALHL;
              __IO uint8_t TCALHH;
            };
          };
        };
        __IO uint32_t FRT_TCAL;
        stc_mft_frt_tcal_field_t FRT_TCAL_f;
        struct {
          union {
            __IO uint16_t FRT_TCALL;
            struct {
              __IO uint8_t FRT_TCALLL;
              __IO uint8_t FRT_TCALLH;
            };
          };
          union {
            __IO uint16_t FRT_TCALH;
            struct {
              __IO uint8_t FRT_TCALHL;
              __IO uint8_t FRT_TCALHH;
            };
          };
        };
    };
    union {
        __IO  uint8_t OCFS10;
        stc_mft_ocfs10_field_t OCFS10_f;
        __IO  uint8_t OCU_OCFS10;
        stc_mft_ocu_ocfs10_field_t OCU_OCFS10_f;
    };
    union {
        __IO  uint8_t OCFS32;
        stc_mft_ocfs32_field_t OCFS32_f;
        __IO  uint8_t OCU_OCFS32;
        stc_mft_ocu_ocfs32_field_t OCU_OCFS32_f;
    };
    union {
        __IO  uint8_t OCFS54;
        stc_mft_ocfs54_field_t OCFS54_f;
        __IO  uint8_t OCU_OCFS54;
        stc_mft_ocu_ocfs54_field_t OCU_OCFS54_f;
    };
        __IO  uint8_t RESERVED17[1];
    union {
        __IO  uint8_t ICFS10;
        stc_mft_icfs10_field_t ICFS10_f;
        __IO  uint8_t ICU_ICFS10;
        stc_mft_icu_icfs10_field_t ICU_ICFS10_f;
    };
    union {
        __IO  uint8_t ICFS32;
        stc_mft_icfs32_field_t ICFS32_f;
        __IO  uint8_t ICU_ICFS32;
        stc_mft_icu_icfs32_field_t ICU_ICFS32_f;
    };
        __IO  uint8_t RESERVED18[2];
    union {
        __IO  uint8_t ACFS10;
        stc_mft_acfs10_field_t ACFS10_f;
        __IO  uint8_t ADCMP_ACFS10;
        stc_mft_adcmp_acfs10_field_t ADCMP_ACFS10_f;
    };
    union {
        __IO  uint8_t ACFS32;
        stc_mft_acfs32_field_t ACFS32_f;
        __IO  uint8_t ADCMP_ACFS32;
        stc_mft_adcmp_acfs32_field_t ADCMP_ACFS32_f;
    };
    union {
        __IO  uint8_t ACFS54;
        stc_mft_acfs54_field_t ACFS54_f;
        __IO  uint8_t ADCMP_ACFS54;
        stc_mft_adcmp_acfs54_field_t ADCMP_ACFS54_f;
    };
        __IO  uint8_t RESERVED19[3];
    union {
        __IO uint16_t ICCP0;
        struct {
            __IO  uint8_t ICCP0L;
            __IO  uint8_t ICCP0H;
        };
        __IO uint16_t ICU_ICCP0;
        struct {
            __IO  uint8_t ICU_ICCP0L;
            __IO  uint8_t ICU_ICCP0H;
        };
    };
        __IO  uint8_t RESERVED20[2];
    union {
        __IO uint16_t ICCP1;
        struct {
            __IO  uint8_t ICCP1L;
            __IO  uint8_t ICCP1H;
        };
        __IO uint16_t ICU_ICCP1;
        struct {
            __IO  uint8_t ICU_ICCP1L;
            __IO  uint8_t ICU_ICCP1H;
        };
    };
        __IO  uint8_t RESERVED21[2];
    union {
        __IO uint16_t ICCP2;
        struct {
            __IO  uint8_t ICCP2L;
            __IO  uint8_t ICCP2H;
        };
        __IO uint16_t ICU_ICCP2;
        struct {
            __IO  uint8_t ICU_ICCP2L;
            __IO  uint8_t ICU_ICCP2H;
        };
    };
        __IO  uint8_t RESERVED22[2];
    union {
        __IO uint16_t ICCP3;
        struct {
            __IO  uint8_t ICCP3L;
            __IO  uint8_t ICCP3H;
        };
        __IO uint16_t ICU_ICCP3;
        struct {
            __IO  uint8_t ICU_ICCP3L;
            __IO  uint8_t ICU_ICCP3H;
        };
    };
    union {
        __IO  uint8_t ICSA10;
        stc_mft_icsa10_field_t ICSA10_f;
        __IO  uint8_t ICU_ICSA10;
        stc_mft_icu_icsa10_field_t ICU_ICSA10_f;
    };
    union {
        __IO  uint8_t ICSB10;
        stc_mft_icsb10_field_t ICSB10_f;
        __IO  uint8_t ICU_ICSB10;
        stc_mft_icu_icsb10_field_t ICU_ICSB10_f;
    };
        __IO  uint8_t RESERVED23[2];
    union {
        __IO  uint8_t ICSA32;
        stc_mft_icsa32_field_t ICSA32_f;
        __IO  uint8_t ICU_ICSA32;
        stc_mft_icu_icsa32_field_t ICU_ICSA32_f;
    };
    union {
        __IO  uint8_t ICSB32;
        stc_mft_icsb32_field_t ICSB32_f;
        __IO  uint8_t ICU_ICSB32;
        stc_mft_icu_icsb32_field_t ICU_ICSB32_f;
    };
        __IO  uint8_t RESERVED24[4];
    union {
        __IO uint16_t WFTF10;
        struct {
            __IO  uint8_t WFTF10L;
            __IO  uint8_t WFTF10H;
        };
        __IO uint16_t WFG_WFTF10;
        struct {
            __IO  uint8_t WFG_WFTF10L;
            __IO  uint8_t WFG_WFTF10H;
        };
    };
    union {
        __IO uint16_t WFTA10;
        struct {
            __IO  uint8_t WFTA10L;
            __IO  uint8_t WFTA10H;
        };
        __IO uint16_t WFG_WFTA10;
        struct {
            __IO  uint8_t WFG_WFTA10L;
            __IO  uint8_t WFG_WFTA10H;
        };
    };
    union {
        __IO uint16_t WFTB10;
        struct {
            __IO  uint8_t WFTB10L;
            __IO  uint8_t WFTB10H;
        };
        __IO uint16_t WFG_WFTB10;
        struct {
            __IO  uint8_t WFG_WFTB10L;
            __IO  uint8_t WFG_WFTB10H;
        };
    };
        __IO  uint8_t RESERVED25[2];
    union {
        __IO uint16_t WFTF32;
        struct {
            __IO  uint8_t WFTF32L;
            __IO  uint8_t WFTF32H;
        };
        __IO uint16_t WFG_WFTF32;
        struct {
            __IO  uint8_t WFG_WFTF32L;
            __IO  uint8_t WFG_WFTF32H;
        };
    };
    union {
        __IO uint16_t WFTA32;
        struct {
            __IO  uint8_t WFTA32L;
            __IO  uint8_t WFTA32H;
        };
        __IO uint16_t WFG_WFTA32;
        struct {
            __IO  uint8_t WFG_WFTA32L;
            __IO  uint8_t WFG_WFTA32H;
        };
    };
    union {
        __IO uint16_t WFTB32;
        struct {
            __IO  uint8_t WFTB32L;
            __IO  uint8_t WFTB32H;
        };
        __IO uint16_t WFG_WFTB32;
        struct {
            __IO  uint8_t WFG_WFTB32L;
            __IO  uint8_t WFG_WFTB32H;
        };
    };
        __IO  uint8_t RESERVED26[2];
    union {
        __IO uint16_t WFTF54;
        struct {
            __IO  uint8_t WFTF54L;
            __IO  uint8_t WFTF54H;
        };
        __IO uint16_t WFG_WFTF54;
        struct {
            __IO  uint8_t WFG_WFTF54L;
            __IO  uint8_t WFG_WFTF54H;
        };
    };
    union {
        __IO uint16_t WFTA54;
        struct {
            __IO  uint8_t WFTA54L;
            __IO  uint8_t WFTA54H;
        };
        __IO uint16_t WFG_WFTA54;
        struct {
            __IO  uint8_t WFG_WFTA54L;
            __IO  uint8_t WFG_WFTA54H;
        };
    };
    union {
        __IO uint16_t WFTB54;
        struct {
            __IO  uint8_t WFTB54L;
            __IO  uint8_t WFTB54H;
        };
        __IO uint16_t WFG_WFTB54;
        struct {
            __IO  uint8_t WFG_WFTB54L;
            __IO  uint8_t WFG_WFTB54H;
        };
    };
    union {
        __IO uint16_t WFSA10;
        stc_mft_wfsa10_field_t WFSA10_f;
        struct {
            __IO  uint8_t WFSA10L;
            __IO  uint8_t WFSA10H;
        };
        __IO uint16_t WFG_WFSA10;
        stc_mft_wfg_wfsa10_field_t WFG_WFSA10_f;
        struct {
            __IO  uint8_t WFG_WFSA10L;
            __IO  uint8_t WFG_WFSA10H;
        };
    };
        __IO  uint8_t RESERVED27[2];
    union {
        __IO uint16_t WFSA32;
        stc_mft_wfsa32_field_t WFSA32_f;
        struct {
            __IO  uint8_t WFSA32L;
            __IO  uint8_t WFSA32H;
        };
        __IO uint16_t WFG_WFSA32;
        stc_mft_wfg_wfsa32_field_t WFG_WFSA32_f;
        struct {
            __IO  uint8_t WFG_WFSA32L;
            __IO  uint8_t WFG_WFSA32H;
        };
    };
        __IO  uint8_t RESERVED28[2];
    union {
        __IO uint16_t WFSA54;
        stc_mft_wfsa54_field_t WFSA54_f;
        struct {
            __IO  uint8_t WFSA54L;
            __IO  uint8_t WFSA54H;
        };
        __IO uint16_t WFG_WFSA54;
        stc_mft_wfg_wfsa54_field_t WFG_WFSA54_f;
        struct {
            __IO  uint8_t WFG_WFSA54L;
            __IO  uint8_t WFG_WFSA54H;
        };
    };
        __IO  uint8_t RESERVED29[2];
    union {
        __IO uint16_t WFIR;
        stc_mft_wfir_field_t WFIR_f;
        struct {
            __IO  uint8_t WFIRL;
            __IO  uint8_t WFIRH;
        };
        __IO uint16_t WFG_WFIR;
        stc_mft_wfg_wfir_field_t WFG_WFIR_f;
        struct {
            __IO  uint8_t WFG_WFIRL;
            __IO  uint8_t WFG_WFIRH;
        };
    };
        __IO  uint8_t RESERVED30[2];
    union {
        __IO uint16_t NZCL;
        stc_mft_nzcl_field_t NZCL_f;
        struct {
            __IO  uint8_t NZCLL;
            __IO  uint8_t NZCLH;
        };
        __IO uint16_t WFG_NZCL;
        stc_mft_wfg_nzcl_field_t WFG_NZCL_f;
        struct {
            __IO  uint8_t WFG_NZCLL;
            __IO  uint8_t WFG_NZCLH;
        };
    };
        __IO  uint8_t RESERVED31[4];
    union {
        __IO uint16_t ACMP0;
        stc_mft_acmp0_field_t ACMP0_f;
        struct {
            __IO  uint8_t ACMP0L;
            __IO  uint8_t ACMP0H;
        };
        __IO uint16_t ADCMP_ACMP0;
        stc_mft_adcmp_acmp0_field_t ADCMP_ACMP0_f;
        struct {
            __IO  uint8_t ADCMP_ACMP0L;
            __IO  uint8_t ADCMP_ACMP0H;
        };
    };
        __IO  uint8_t RESERVED32[2];
    union {
        __IO uint16_t ACMP1;
        stc_mft_acmp1_field_t ACMP1_f;
        struct {
            __IO  uint8_t ACMP1L;
            __IO  uint8_t ACMP1H;
        };
        __IO uint16_t ADCMP_ACMP1;
        stc_mft_adcmp_acmp1_field_t ADCMP_ACMP1_f;
        struct {
            __IO  uint8_t ADCMP_ACMP1L;
            __IO  uint8_t ADCMP_ACMP1H;
        };
    };
        __IO  uint8_t RESERVED33[2];
    union {
        __IO uint16_t ACMP2;
        stc_mft_acmp2_field_t ACMP2_f;
        struct {
            __IO  uint8_t ACMP2L;
            __IO  uint8_t ACMP2H;
        };
        __IO uint16_t ADCMP_ACMP2;
        stc_mft_adcmp_acmp2_field_t ADCMP_ACMP2_f;
        struct {
            __IO  uint8_t ADCMP_ACMP2L;
            __IO  uint8_t ADCMP_ACMP2H;
        };
    };
        __IO  uint8_t RESERVED34[2];
    union {
        __IO uint16_t ACMP3;
        stc_mft_acmp3_field_t ACMP3_f;
        struct {
            __IO  uint8_t ACMP3L;
            __IO  uint8_t ACMP3H;
        };
        __IO uint16_t ADCMP_ACMP3;
        stc_mft_adcmp_acmp3_field_t ADCMP_ACMP3_f;
        struct {
            __IO  uint8_t ADCMP_ACMP3L;
            __IO  uint8_t ADCMP_ACMP3H;
        };
    };
        __IO  uint8_t RESERVED35[2];
    union {
        __IO uint16_t ACMP4;
        stc_mft_acmp4_field_t ACMP4_f;
        struct {
            __IO  uint8_t ACMP4L;
            __IO  uint8_t ACMP4H;
        };
        __IO uint16_t ADCMP_ACMP4;
        stc_mft_adcmp_acmp4_field_t ADCMP_ACMP4_f;
        struct {
            __IO  uint8_t ADCMP_ACMP4L;
            __IO  uint8_t ADCMP_ACMP4H;
        };
    };
        __IO  uint8_t RESERVED36[2];
    union {
        __IO uint16_t ACMP5;
        stc_mft_acmp5_field_t ACMP5_f;
        struct {
            __IO  uint8_t ACMP5L;
            __IO  uint8_t ACMP5H;
        };
        __IO uint16_t ADCMP_ACMP5;
        stc_mft_adcmp_acmp5_field_t ADCMP_ACMP5_f;
        struct {
            __IO  uint8_t ADCMP_ACMP5L;
            __IO  uint8_t ADCMP_ACMP5H;
        };
    };
    union {
        __IO uint16_t ACSA;
        stc_mft_acsa_field_t ACSA_f;
        struct {
            __IO  uint8_t ACSAL;
            __IO  uint8_t ACSAH;
        };
        __IO uint16_t ADCMP_ACSA;
        stc_mft_adcmp_acsa_field_t ADCMP_ACSA_f;
        struct {
            __IO  uint8_t ADCMP_ACSAL;
            __IO  uint8_t ADCMP_ACSAH;
        };
    };
        __IO  uint8_t RESERVED37[2];
    union {
        __IO  uint8_t ACSC0;
        stc_mft_acsc0_field_t ACSC0_f;
        __IO  uint8_t ADCMP_ACSC0;
        stc_mft_adcmp_acsc0_field_t ADCMP_ACSC0_f;
    };
    union {
        __IO  uint8_t ACSD0;
        stc_mft_acsd0_field_t ACSD0_f;
        __IO  uint8_t ADCMP_ACSD0;
        stc_mft_adcmp_acsd0_field_t ADCMP_ACSD0_f;
    };
    union {
        __IO  uint8_t ACMC0;
        stc_mft_acmc0_field_t ACMC0_f;
        __IO  uint8_t ADCMP_ACMC0;
        stc_mft_adcmp_acmc0_field_t ADCMP_ACMC0_f;
    };
        __IO  uint8_t RESERVED38[1];
    union {
        __IO  uint8_t ACSC1;
        stc_mft_acsc1_field_t ACSC1_f;
        __IO  uint8_t ADCMP_ACSC1;
        stc_mft_adcmp_acsc1_field_t ADCMP_ACSC1_f;
    };
    union {
        __IO  uint8_t ACSD1;
        stc_mft_acsd1_field_t ACSD1_f;
        __IO  uint8_t ADCMP_ACSD1;
        stc_mft_adcmp_acsd1_field_t ADCMP_ACSD1_f;
    };
    union {
        __IO  uint8_t ACMC1;
        stc_mft_acmc1_field_t ACMC1_f;
        __IO  uint8_t ADCMP_ACMC1;
        stc_mft_adcmp_acmc1_field_t ADCMP_ACMC1_f;
    };
        __IO  uint8_t RESERVED39[1];
    union {
        __IO  uint8_t ACSC2;
        stc_mft_acsc2_field_t ACSC2_f;
        __IO  uint8_t ADCMP_ACSC2;
        stc_mft_adcmp_acsc2_field_t ADCMP_ACSC2_f;
    };
    union {
        __IO  uint8_t ACSD2;
        stc_mft_acsd2_field_t ACSD2_f;
        __IO  uint8_t ADCMP_ACSD2;
        stc_mft_adcmp_acsd2_field_t ADCMP_ACSD2_f;
    };
    union {
        __IO  uint8_t ACMC2;
        stc_mft_acmc2_field_t ACMC2_f;
        __IO  uint8_t ADCMP_ACMC2;
        stc_mft_adcmp_acmc2_field_t ADCMP_ACMC2_f;
    };
        __IO  uint8_t RESERVED40[1];
    union {
        __IO  uint8_t ACSC3;
        stc_mft_acsc3_field_t ACSC3_f;
        __IO  uint8_t ADCMP_ACSC3;
        stc_mft_adcmp_acsc3_field_t ADCMP_ACSC3_f;
    };
    union {
        __IO  uint8_t ACSD3;
        stc_mft_acsd3_field_t ACSD3_f;
        __IO  uint8_t ADCMP_ACSD3;
        stc_mft_adcmp_acsd3_field_t ADCMP_ACSD3_f;
    };
    union {
        __IO  uint8_t ACMC3;
        stc_mft_acmc3_field_t ACMC3_f;
        __IO  uint8_t ADCMP_ACMC3;
        stc_mft_adcmp_acmc3_field_t ADCMP_ACMC3_f;
    };
        __IO  uint8_t RESERVED41[1];
    union {
        __IO  uint8_t ACSC4;
        stc_mft_acsc4_field_t ACSC4_f;
        __IO  uint8_t ADCMP_ACSC4;
        stc_mft_adcmp_acsc4_field_t ADCMP_ACSC4_f;
    };
    union {
        __IO  uint8_t ACSD4;
        stc_mft_acsd4_field_t ACSD4_f;
        __IO  uint8_t ADCMP_ACSD4;
        stc_mft_adcmp_acsd4_field_t ADCMP_ACSD4_f;
    };
    union {
        __IO  uint8_t ACMC4;
        stc_mft_acmc4_field_t ACMC4_f;
        __IO  uint8_t ADCMP_ACMC4;
        stc_mft_adcmp_acmc4_field_t ADCMP_ACMC4_f;
    };
        __IO  uint8_t RESERVED42[1];
    union {
        __IO  uint8_t ACSC5;
        stc_mft_acsc5_field_t ACSC5_f;
        __IO  uint8_t ADCMP_ACSC5;
        stc_mft_adcmp_acsc5_field_t ADCMP_ACSC5_f;
    };
    union {
        __IO  uint8_t ACSD5;
        stc_mft_acsd5_field_t ACSD5_f;
        __IO  uint8_t ADCMP_ACSD5;
        stc_mft_adcmp_acsd5_field_t ADCMP_ACSD5_f;
    };
    union {
        __IO  uint8_t ACMC5;
        stc_mft_acmc5_field_t ACMC5_f;
        __IO  uint8_t ADCMP_ACMC5;
        stc_mft_adcmp_acmc5_field_t ADCMP_ACMC5_f;
    };
        __IO  uint8_t RESERVED43[1];
    union {
        __IO  uint8_t TCSD;
        stc_mft_tcsd_field_t TCSD_f;
        __IO  uint8_t FRT_TCSD;
        stc_mft_frt_tcsd_field_t FRT_TCSD_f;
    };
} FM_MFT_TypeDef, FM4_MFT_TypeDef;

/*******************************************************************************
* MFT_ADCMP_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
        __IO  uint8_t RESERVED44[368];
    union {
        __IO  uint8_t ACFS10;
        stc_mft_adcmp_acfs10_field_t ACFS10_f;
    };
    union {
        __IO  uint8_t ACFS32;
        stc_mft_adcmp_acfs32_field_t ACFS32_f;
    };
    union {
        __IO  uint8_t ACFS54;
        stc_mft_adcmp_acfs54_field_t ACFS54_f;
    };
        __IO  uint8_t RESERVED45[71];
    union {
        __IO uint16_t ACMP0;
        stc_mft_adcmp_acmp0_field_t ACMP0_f;
        struct {
            __IO  uint8_t ACMP0L;
            __IO  uint8_t ACMP0H;
        };
    };
        __IO  uint8_t RESERVED46[2];
    union {
        __IO uint16_t ACMP1;
        stc_mft_adcmp_acmp1_field_t ACMP1_f;
        struct {
            __IO  uint8_t ACMP1L;
            __IO  uint8_t ACMP1H;
        };
    };
        __IO  uint8_t RESERVED47[2];
    union {
        __IO uint16_t ACMP2;
        stc_mft_adcmp_acmp2_field_t ACMP2_f;
        struct {
            __IO  uint8_t ACMP2L;
            __IO  uint8_t ACMP2H;
        };
    };
        __IO  uint8_t RESERVED48[2];
    union {
        __IO uint16_t ACMP3;
        stc_mft_adcmp_acmp3_field_t ACMP3_f;
        struct {
            __IO  uint8_t ACMP3L;
            __IO  uint8_t ACMP3H;
        };
    };
        __IO  uint8_t RESERVED49[2];
    union {
        __IO uint16_t ACMP4;
        stc_mft_adcmp_acmp4_field_t ACMP4_f;
        struct {
            __IO  uint8_t ACMP4L;
            __IO  uint8_t ACMP4H;
        };
    };
        __IO  uint8_t RESERVED50[2];
    union {
        __IO uint16_t ACMP5;
        stc_mft_adcmp_acmp5_field_t ACMP5_f;
        struct {
            __IO  uint8_t ACMP5L;
            __IO  uint8_t ACMP5H;
        };
    };
    union {
        __IO uint16_t ACSA;
        stc_mft_adcmp_acsa_field_t ACSA_f;
        struct {
            __IO  uint8_t ACSAL;
            __IO  uint8_t ACSAH;
        };
    };
        __IO  uint8_t RESERVED51[2];
    union {
        __IO  uint8_t ACSC0;
        stc_mft_adcmp_acsc0_field_t ACSC0_f;
    };
    union {
        __IO  uint8_t ACSD0;
        stc_mft_adcmp_acsd0_field_t ACSD0_f;
    };
    union {
        __IO  uint8_t ACMC0;
        stc_mft_adcmp_acmc0_field_t ACMC0_f;
    };
        __IO  uint8_t RESERVED52[1];
    union {
        __IO  uint8_t ACSC1;
        stc_mft_adcmp_acsc1_field_t ACSC1_f;
    };
    union {
        __IO  uint8_t ACSD1;
        stc_mft_adcmp_acsd1_field_t ACSD1_f;
    };
    union {
        __IO  uint8_t ACMC1;
        stc_mft_adcmp_acmc1_field_t ACMC1_f;
    };
        __IO  uint8_t RESERVED53[1];
    union {
        __IO  uint8_t ACSC2;
        stc_mft_adcmp_acsc2_field_t ACSC2_f;
    };
    union {
        __IO  uint8_t ACSD2;
        stc_mft_adcmp_acsd2_field_t ACSD2_f;
    };
    union {
        __IO  uint8_t ACMC2;
        stc_mft_adcmp_acmc2_field_t ACMC2_f;
    };
        __IO  uint8_t RESERVED54[1];
    union {
        __IO  uint8_t ACSC3;
        stc_mft_adcmp_acsc3_field_t ACSC3_f;
    };
    union {
        __IO  uint8_t ACSD3;
        stc_mft_adcmp_acsd3_field_t ACSD3_f;
    };
    union {
        __IO  uint8_t ACMC3;
        stc_mft_adcmp_acmc3_field_t ACMC3_f;
    };
        __IO  uint8_t RESERVED55[1];
    union {
        __IO  uint8_t ACSC4;
        stc_mft_adcmp_acsc4_field_t ACSC4_f;
    };
    union {
        __IO  uint8_t ACSD4;
        stc_mft_adcmp_acsd4_field_t ACSD4_f;
    };
    union {
        __IO  uint8_t ACMC4;
        stc_mft_adcmp_acmc4_field_t ACMC4_f;
    };
        __IO  uint8_t RESERVED56[1];
    union {
        __IO  uint8_t ACSC5;
        stc_mft_adcmp_acsc5_field_t ACSC5_f;
    };
    union {
        __IO  uint8_t ACSD5;
        stc_mft_adcmp_acsd5_field_t ACSD5_f;
    };
    union {
        __IO  uint8_t ACMC5;
        stc_mft_adcmp_acmc5_field_t ACMC5_f;
    };
} FM_MFT_ADCMP_TypeDef, FM4_MFT_ADCMP_TypeDef;

/*******************************************************************************
* MFT_FRT_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
        __IO  uint8_t RESERVED57[322];
    union {
        __IO uint16_t TCCP0;
        stc_mft_frt_tccp0_field_t TCCP0_f;
        struct {
            __IO  uint8_t TCCP0L;
            __IO  uint8_t TCCP0H;
        };
    };
        __IO  uint8_t RESERVED58[2];
    union {
        __IO uint16_t TCDT0;
        struct {
            __IO  uint8_t TCDT0L;
            __IO  uint8_t TCDT0H;
        };
    };
    union {
        __IO uint16_t TCSA0;
        stc_mft_frt_tcsa0_field_t TCSA0_f;
        struct {
            __IO  uint8_t TCSA0L;
            __IO  uint8_t TCSA0H;
        };
    };
    union {
        __IO uint16_t TCSC0;
        stc_mft_frt_tcsc0_field_t TCSC0_f;
        struct {
            __IO  uint8_t TCSC0L;
            __IO  uint8_t TCSC0H;
        };
    };
        __IO  uint8_t RESERVED59[2];
    union {
        __IO uint16_t TCCP1;
        stc_mft_frt_tccp1_field_t TCCP1_f;
        struct {
            __IO  uint8_t TCCP1L;
            __IO  uint8_t TCCP1H;
        };
    };
        __IO  uint8_t RESERVED60[2];
    union {
        __IO uint16_t TCDT1;
        struct {
            __IO  uint8_t TCDT1L;
            __IO  uint8_t TCDT1H;
        };
    };
    union {
        __IO uint16_t TCSA1;
        stc_mft_frt_tcsa1_field_t TCSA1_f;
        struct {
            __IO  uint8_t TCSA1L;
            __IO  uint8_t TCSA1H;
        };
    };
    union {
        __IO uint16_t TCSC1;
        stc_mft_frt_tcsc1_field_t TCSC1_f;
        struct {
            __IO  uint8_t TCSC1L;
            __IO  uint8_t TCSC1H;
        };
    };
        __IO  uint8_t RESERVED61[2];
    union {
        __IO uint16_t TCCP2;
        stc_mft_frt_tccp2_field_t TCCP2_f;
        struct {
            __IO  uint8_t TCCP2L;
            __IO  uint8_t TCCP2H;
        };
    };
        __IO  uint8_t RESERVED62[2];
    union {
        __IO uint16_t TCDT2;
        struct {
            __IO  uint8_t TCDT2L;
            __IO  uint8_t TCDT2H;
        };
    };
    union {
        __IO uint16_t TCSA2;
        stc_mft_frt_tcsa2_field_t TCSA2_f;
        struct {
            __IO  uint8_t TCSA2L;
            __IO  uint8_t TCSA2H;
        };
    };
    union {
        __IO uint16_t TCSC2;
        stc_mft_frt_tcsc2_field_t TCSC2_f;
        struct {
            __IO  uint8_t TCSC2L;
            __IO  uint8_t TCSC2H;
        };
    };
    union {
        __IO uint32_t TCAL;
        stc_mft_frt_tcal_field_t TCAL_f;
        struct {
          union {
            __IO uint16_t TCALL;
            struct {
              __IO uint8_t TCALLL;
              __IO uint8_t TCALLH;
            };
          };
          union {
            __IO uint16_t TCALH;
            struct {
              __IO uint8_t TCALHL;
              __IO uint8_t TCALHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED63[132];
    union {
        __IO  uint8_t TCSD;
        stc_mft_frt_tcsd_field_t TCSD_f;
    };
} FM_MFT_FRT_TypeDef, FM4_MFT_FRT_TypeDef;

/*******************************************************************************
* MFT_ICU_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
        __IO  uint8_t RESERVED64[364];
    union {
        __IO  uint8_t ICFS10;
        stc_mft_icu_icfs10_field_t ICFS10_f;
    };
    union {
        __IO  uint8_t ICFS32;
        stc_mft_icu_icfs32_field_t ICFS32_f;
    };
        __IO  uint8_t RESERVED65[8];
    union {
        __IO uint16_t ICCP0;
        struct {
            __IO  uint8_t ICCP0L;
            __IO  uint8_t ICCP0H;
        };
    };
        __IO  uint8_t RESERVED66[2];
    union {
        __IO uint16_t ICCP1;
        struct {
            __IO  uint8_t ICCP1L;
            __IO  uint8_t ICCP1H;
        };
    };
        __IO  uint8_t RESERVED67[2];
    union {
        __IO uint16_t ICCP2;
        struct {
            __IO  uint8_t ICCP2L;
            __IO  uint8_t ICCP2H;
        };
    };
        __IO  uint8_t RESERVED68[2];
    union {
        __IO uint16_t ICCP3;
        struct {
            __IO  uint8_t ICCP3L;
            __IO  uint8_t ICCP3H;
        };
    };
    union {
        __IO  uint8_t ICSA10;
        stc_mft_icu_icsa10_field_t ICSA10_f;
    };
    union {
        __IO  uint8_t ICSB10;
        stc_mft_icu_icsb10_field_t ICSB10_f;
    };
        __IO  uint8_t RESERVED69[2];
    union {
        __IO  uint8_t ICSA32;
        stc_mft_icu_icsa32_field_t ICSA32_f;
    };
    union {
        __IO  uint8_t ICSB32;
        stc_mft_icu_icsb32_field_t ICSB32_f;
    };
} FM_MFT_ICU_TypeDef, FM4_MFT_ICU_TypeDef;

/*******************************************************************************
* MFT_OCU_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
        __IO  uint8_t RESERVED70[258];
    union {
        __IO uint16_t OCCP0;
        struct {
            __IO  uint8_t OCCP0L;
            __IO  uint8_t OCCP0H;
        };
    };
        __IO  uint8_t RESERVED71[2];
    union {
        __IO uint16_t OCCP1;
        struct {
            __IO  uint8_t OCCP1L;
            __IO  uint8_t OCCP1H;
        };
    };
        __IO  uint8_t RESERVED72[2];
    union {
        __IO uint16_t OCCP2;
        struct {
            __IO  uint8_t OCCP2L;
            __IO  uint8_t OCCP2H;
        };
    };
        __IO  uint8_t RESERVED73[2];
    union {
        __IO uint16_t OCCP3;
        struct {
            __IO  uint8_t OCCP3L;
            __IO  uint8_t OCCP3H;
        };
    };
        __IO  uint8_t RESERVED74[2];
    union {
        __IO uint16_t OCCP4;
        struct {
            __IO  uint8_t OCCP4L;
            __IO  uint8_t OCCP4H;
        };
    };
        __IO  uint8_t RESERVED75[2];
    union {
        __IO uint16_t OCCP5;
        struct {
            __IO  uint8_t OCCP5L;
            __IO  uint8_t OCCP5H;
        };
    };
    union {
        __IO  uint8_t OCSA10;
        stc_mft_ocu_ocsa10_field_t OCSA10_f;
    };
    union {
        __IO  uint8_t OCSB10;
        stc_mft_ocu_ocsb10_field_t OCSB10_f;
    };
    union {
        __IO uint16_t OCSD10;
        stc_mft_ocu_ocsd10_field_t OCSD10_f;
        struct {
            __IO  uint8_t OCSD10L;
            __IO  uint8_t OCSD10H;
        };
    };
    union {
        __IO  uint8_t OCSA32;
        stc_mft_ocu_ocsa32_field_t OCSA32_f;
    };
    union {
        __IO  uint8_t OCSB32;
        stc_mft_ocu_ocsb32_field_t OCSB32_f;
    };
    union {
        __IO uint16_t OCSD32;
        stc_mft_ocu_ocsd32_field_t OCSD32_f;
        struct {
            __IO  uint8_t OCSD32L;
            __IO  uint8_t OCSD32H;
        };
    };
    union {
        __IO  uint8_t OCSA54;
        stc_mft_ocu_ocsa54_field_t OCSA54_f;
    };
    union {
        __IO  uint8_t OCSB54;
        stc_mft_ocu_ocsb54_field_t OCSB54_f;
    };
    union {
        __IO uint16_t OCSD54;
        stc_mft_ocu_ocsd54_field_t OCSD54_f;
        struct {
            __IO  uint8_t OCSD54L;
            __IO  uint8_t OCSD54H;
        };
    };
        __IO  uint8_t RESERVED76[1];
    union {
        __IO  uint8_t OCSC;
        stc_mft_ocu_ocsc_field_t OCSC_f;
    };
        __IO  uint8_t RESERVED77[2];
    union {
        __IO uint16_t OCSE0;
        stc_mft_ocu_ocse0_field_t OCSE0_f;
        struct {
            __IO  uint8_t OCSE0L;
            __IO  uint8_t OCSE0H;
        };
    };
        __IO  uint8_t RESERVED78[2];
    union {
        __IO uint32_t OCSE1;
        stc_mft_ocu_ocse1_field_t OCSE1_f;
        struct {
          union {
            __IO uint16_t OCSE1L;
            struct {
              __IO uint8_t OCSE1LL;
              __IO uint8_t OCSE1LH;
            };
          };
          union {
            __IO uint16_t OCSE1H;
            struct {
              __IO uint8_t OCSE1HL;
              __IO uint8_t OCSE1HH;
            };
          };
        };
    };
    union {
        __IO uint16_t OCSE2;
        stc_mft_ocu_ocse2_field_t OCSE2_f;
        struct {
            __IO  uint8_t OCSE2L;
            __IO  uint8_t OCSE2H;
        };
    };
        __IO  uint8_t RESERVED79[2];
    union {
        __IO uint32_t OCSE3;
        stc_mft_ocu_ocse3_field_t OCSE3_f;
        struct {
          union {
            __IO uint16_t OCSE3L;
            struct {
              __IO uint8_t OCSE3LL;
              __IO uint8_t OCSE3LH;
            };
          };
          union {
            __IO uint16_t OCSE3H;
            struct {
              __IO uint8_t OCSE3HL;
              __IO uint8_t OCSE3HH;
            };
          };
        };
    };
    union {
        __IO uint16_t OCSE4;
        stc_mft_ocu_ocse4_field_t OCSE4_f;
        struct {
            __IO  uint8_t OCSE4L;
            __IO  uint8_t OCSE4H;
        };
    };
        __IO  uint8_t RESERVED80[2];
    union {
        __IO uint32_t OCSE5;
        stc_mft_ocu_ocse5_field_t OCSE5_f;
        struct {
          union {
            __IO uint16_t OCSE5L;
            struct {
              __IO uint8_t OCSE5LL;
              __IO uint8_t OCSE5LH;
            };
          };
          union {
            __IO uint16_t OCSE5H;
            struct {
              __IO uint8_t OCSE5HL;
              __IO uint8_t OCSE5HH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED81[40];
    union {
        __IO  uint8_t OCFS10;
        stc_mft_ocu_ocfs10_field_t OCFS10_f;
    };
    union {
        __IO  uint8_t OCFS32;
        stc_mft_ocu_ocfs32_field_t OCFS32_f;
    };
    union {
        __IO  uint8_t OCFS54;
        stc_mft_ocu_ocfs54_field_t OCFS54_f;
    };
} FM_MFT_OCU_TypeDef, FM4_MFT_OCU_TypeDef;

/*******************************************************************************
* MFT_WFG_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
        __IO  uint8_t RESERVED82[398];
    union {
        __IO uint16_t WFTF10;
        struct {
            __IO  uint8_t WFTF10L;
            __IO  uint8_t WFTF10H;
        };
    };
    union {
        __IO uint16_t WFTA10;
        struct {
            __IO  uint8_t WFTA10L;
            __IO  uint8_t WFTA10H;
        };
    };
    union {
        __IO uint16_t WFTB10;
        struct {
            __IO  uint8_t WFTB10L;
            __IO  uint8_t WFTB10H;
        };
    };
        __IO  uint8_t RESERVED83[2];
    union {
        __IO uint16_t WFTF32;
        struct {
            __IO  uint8_t WFTF32L;
            __IO  uint8_t WFTF32H;
        };
    };
    union {
        __IO uint16_t WFTA32;
        struct {
            __IO  uint8_t WFTA32L;
            __IO  uint8_t WFTA32H;
        };
    };
    union {
        __IO uint16_t WFTB32;
        struct {
            __IO  uint8_t WFTB32L;
            __IO  uint8_t WFTB32H;
        };
    };
        __IO  uint8_t RESERVED84[2];
    union {
        __IO uint16_t WFTF54;
        struct {
            __IO  uint8_t WFTF54L;
            __IO  uint8_t WFTF54H;
        };
    };
    union {
        __IO uint16_t WFTA54;
        struct {
            __IO  uint8_t WFTA54L;
            __IO  uint8_t WFTA54H;
        };
    };
    union {
        __IO uint16_t WFTB54;
        struct {
            __IO  uint8_t WFTB54L;
            __IO  uint8_t WFTB54H;
        };
    };
    union {
        __IO uint16_t WFSA10;
        stc_mft_wfg_wfsa10_field_t WFSA10_f;
        struct {
            __IO  uint8_t WFSA10L;
            __IO  uint8_t WFSA10H;
        };
    };
        __IO  uint8_t RESERVED85[2];
    union {
        __IO uint16_t WFSA32;
        stc_mft_wfg_wfsa32_field_t WFSA32_f;
        struct {
            __IO  uint8_t WFSA32L;
            __IO  uint8_t WFSA32H;
        };
    };
        __IO  uint8_t RESERVED86[2];
    union {
        __IO uint16_t WFSA54;
        stc_mft_wfg_wfsa54_field_t WFSA54_f;
        struct {
            __IO  uint8_t WFSA54L;
            __IO  uint8_t WFSA54H;
        };
    };
        __IO  uint8_t RESERVED87[2];
    union {
        __IO uint16_t WFIR;
        stc_mft_wfg_wfir_field_t WFIR_f;
        struct {
            __IO  uint8_t WFIRL;
            __IO  uint8_t WFIRH;
        };
    };
        __IO  uint8_t RESERVED88[2];
    union {
        __IO uint16_t NZCL;
        stc_mft_wfg_nzcl_field_t NZCL_f;
        struct {
            __IO  uint8_t NZCLL;
            __IO  uint8_t NZCLH;
        };
    };
} FM_MFT_WFG_TypeDef, FM4_MFT_WFG_TypeDef;

/*******************************************************************************
* MFT_PPG_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
        __IO  uint8_t RESERVED0[1];
    union {
        __IO  uint8_t TTCR0;
        stc_mft_ppg_ttcr0_field_t TTCR0_f;
    };
        __IO  uint8_t RESERVED1[7];
        __IO  uint8_t COMP0;
        __IO  uint8_t RESERVED2[2];
        __IO  uint8_t COMP2;
        __IO  uint8_t RESERVED3[4];
        __IO  uint8_t COMP4;
        __IO  uint8_t RESERVED4[2];
        __IO  uint8_t COMP6;
        __IO  uint8_t RESERVED5[12];
    union {
        __IO  uint8_t TTCR1;
        stc_mft_ppg_ttcr1_field_t TTCR1_f;
    };
        __IO  uint8_t RESERVED6[7];
        __IO  uint8_t COMP1;
        __IO  uint8_t RESERVED7[2];
        __IO  uint8_t COMP3;
        __IO  uint8_t RESERVED8[4];
        __IO  uint8_t COMP5;
        __IO  uint8_t RESERVED9[2];
        __IO  uint8_t COMP7;
        __IO  uint8_t RESERVED10[12];
    union {
        __IO  uint8_t TTCR2;
        stc_mft_ppg_ttcr2_field_t TTCR2_f;
    };
        __IO  uint8_t RESERVED11[7];
        __IO  uint8_t COMP8;
        __IO  uint8_t RESERVED12[2];
        __IO  uint8_t COMP10;
        __IO  uint8_t RESERVED13[4];
        __IO  uint8_t COMP12;
        __IO  uint8_t RESERVED14[2];
        __IO  uint8_t COMP14;
        __IO  uint8_t RESERVED15[171];
    union {
        __IO uint16_t TRG0;
        stc_mft_ppg_trg0_field_t TRG0_f;
        struct {
            __IO  uint8_t TRG0L;
            __IO  uint8_t TRG0H;
        };
    };
        __IO  uint8_t RESERVED16[2];
    union {
        __IO uint16_t REVC0;
        stc_mft_ppg_revc0_field_t REVC0_f;
        struct {
            __IO  uint8_t REVC0L;
            __IO  uint8_t REVC0H;
        };
    };
        __IO  uint8_t RESERVED17[58];
    union {
        __IO uint16_t TRG1;
        stc_mft_ppg_trg1_field_t TRG1_f;
        struct {
            __IO  uint8_t TRG1L;
            __IO  uint8_t TRG1H;
        };
    };
        __IO  uint8_t RESERVED18[2];
    union {
        __IO uint16_t REVC1;
        stc_mft_ppg_revc1_field_t REVC1_f;
        struct {
            __IO  uint8_t REVC1L;
            __IO  uint8_t REVC1H;
        };
    };
        __IO  uint8_t RESERVED19[186];
    union {
        __IO  uint8_t PPGC1;
        stc_mft_ppg_ppgc1_field_t PPGC1_f;
    };
    union {
        __IO  uint8_t PPGC0;
        stc_mft_ppg_ppgc0_field_t PPGC0_f;
    };
        __IO  uint8_t RESERVED20[2];
    union {
        __IO  uint8_t PPGC3;
        stc_mft_ppg_ppgc3_field_t PPGC3_f;
    };
    union {
        __IO  uint8_t PPGC2;
        stc_mft_ppg_ppgc2_field_t PPGC2_f;
    };
        __IO  uint8_t RESERVED21[2];
    union {
        __IO  uint8_t PRLL0;
        stc_mft_ppg_prll0_field_t PRLL0_f;
    };
    union {
        __IO  uint8_t PRLH0;
        stc_mft_ppg_prlh0_field_t PRLH0_f;
    };
        __IO  uint8_t RESERVED22[2];
    union {
        __IO  uint8_t PRLL1;
        stc_mft_ppg_prll1_field_t PRLL1_f;
    };
    union {
        __IO  uint8_t PRLH1;
        stc_mft_ppg_prlh1_field_t PRLH1_f;
    };
        __IO  uint8_t RESERVED23[2];
    union {
        __IO  uint8_t PRLL2;
        stc_mft_ppg_prll2_field_t PRLL2_f;
    };
    union {
        __IO  uint8_t PRLH2;
        stc_mft_ppg_prlh2_field_t PRLH2_f;
    };
        __IO  uint8_t RESERVED24[2];
    union {
        __IO  uint8_t PRLL3;
        stc_mft_ppg_prll3_field_t PRLL3_f;
    };
    union {
        __IO  uint8_t PRLH3;
        stc_mft_ppg_prlh3_field_t PRLH3_f;
    };
        __IO  uint8_t RESERVED25[2];
    union {
        __IO  uint8_t GATEC0;
        stc_mft_ppg_gatec0_field_t GATEC0_f;
    };
        __IO  uint8_t RESERVED26[39];
    union {
        __IO  uint8_t PPGC5;
        stc_mft_ppg_ppgc5_field_t PPGC5_f;
    };
    union {
        __IO  uint8_t PPGC4;
        stc_mft_ppg_ppgc4_field_t PPGC4_f;
    };
        __IO  uint8_t RESERVED27[2];
    union {
        __IO  uint8_t PPGC7;
        stc_mft_ppg_ppgc7_field_t PPGC7_f;
    };
    union {
        __IO  uint8_t PPGC6;
        stc_mft_ppg_ppgc6_field_t PPGC6_f;
    };
        __IO  uint8_t RESERVED28[2];
    union {
        __IO  uint8_t PRLL4;
        stc_mft_ppg_prll4_field_t PRLL4_f;
    };
    union {
        __IO  uint8_t PRLH4;
        stc_mft_ppg_prlh4_field_t PRLH4_f;
    };
        __IO  uint8_t RESERVED29[2];
    union {
        __IO  uint8_t PRLL5;
        stc_mft_ppg_prll5_field_t PRLL5_f;
    };
    union {
        __IO  uint8_t PRLH5;
        stc_mft_ppg_prlh5_field_t PRLH5_f;
    };
        __IO  uint8_t RESERVED30[2];
    union {
        __IO  uint8_t PRLL6;
        stc_mft_ppg_prll6_field_t PRLL6_f;
    };
    union {
        __IO  uint8_t PRLH6;
        stc_mft_ppg_prlh6_field_t PRLH6_f;
    };
        __IO  uint8_t RESERVED31[2];
    union {
        __IO  uint8_t PRLL7;
        stc_mft_ppg_prll7_field_t PRLL7_f;
    };
    union {
        __IO  uint8_t PRLH7;
        stc_mft_ppg_prlh7_field_t PRLH7_f;
    };
        __IO  uint8_t RESERVED32[2];
    union {
        __IO  uint8_t GATEC4;
        stc_mft_ppg_gatec4_field_t GATEC4_f;
    };
        __IO  uint8_t RESERVED33[39];
    union {
        __IO  uint8_t PPGC9;
        stc_mft_ppg_ppgc9_field_t PPGC9_f;
    };
    union {
        __IO  uint8_t PPGC8;
        stc_mft_ppg_ppgc8_field_t PPGC8_f;
    };
        __IO  uint8_t RESERVED34[2];
    union {
        __IO  uint8_t PPGC11;
        stc_mft_ppg_ppgc11_field_t PPGC11_f;
    };
    union {
        __IO  uint8_t PPGC10;
        stc_mft_ppg_ppgc10_field_t PPGC10_f;
    };
        __IO  uint8_t RESERVED35[2];
    union {
        __IO  uint8_t PRLL8;
        stc_mft_ppg_prll8_field_t PRLL8_f;
    };
    union {
        __IO  uint8_t PRLH8;
        stc_mft_ppg_prlh8_field_t PRLH8_f;
    };
        __IO  uint8_t RESERVED36[2];
    union {
        __IO  uint8_t PRLL9;
        stc_mft_ppg_prll9_field_t PRLL9_f;
    };
    union {
        __IO  uint8_t PRLH9;
        stc_mft_ppg_prlh9_field_t PRLH9_f;
    };
        __IO  uint8_t RESERVED37[2];
    union {
        __IO  uint8_t PRLL10;
        stc_mft_ppg_prll10_field_t PRLL10_f;
    };
    union {
        __IO  uint8_t PRLH10;
        stc_mft_ppg_prlh10_field_t PRLH10_f;
    };
        __IO  uint8_t RESERVED38[2];
    union {
        __IO  uint8_t PRLL11;
        stc_mft_ppg_prll11_field_t PRLL11_f;
    };
    union {
        __IO  uint8_t PRLH11;
        stc_mft_ppg_prlh11_field_t PRLH11_f;
    };
        __IO  uint8_t RESERVED39[2];
    union {
        __IO  uint8_t GATEC8;
        stc_mft_ppg_gatec8_field_t GATEC8_f;
    };
        __IO  uint8_t RESERVED40[39];
    union {
        __IO  uint8_t PPGC13;
        stc_mft_ppg_ppgc13_field_t PPGC13_f;
    };
    union {
        __IO  uint8_t PPGC12;
        stc_mft_ppg_ppgc12_field_t PPGC12_f;
    };
        __IO  uint8_t RESERVED41[2];
    union {
        __IO  uint8_t PPGC15;
        stc_mft_ppg_ppgc15_field_t PPGC15_f;
    };
    union {
        __IO  uint8_t PPGC14;
        stc_mft_ppg_ppgc14_field_t PPGC14_f;
    };
        __IO  uint8_t RESERVED42[2];
    union {
        __IO  uint8_t PRLL12;
        stc_mft_ppg_prll12_field_t PRLL12_f;
    };
    union {
        __IO  uint8_t PRLH12;
        stc_mft_ppg_prlh12_field_t PRLH12_f;
    };
        __IO  uint8_t RESERVED43[2];
    union {
        __IO  uint8_t PRLL13;
        stc_mft_ppg_prll13_field_t PRLL13_f;
    };
    union {
        __IO  uint8_t PRLH13;
        stc_mft_ppg_prlh13_field_t PRLH13_f;
    };
        __IO  uint8_t RESERVED44[2];
    union {
        __IO  uint8_t PRLL14;
        stc_mft_ppg_prll14_field_t PRLL14_f;
    };
    union {
        __IO  uint8_t PRLH14;
        stc_mft_ppg_prlh14_field_t PRLH14_f;
    };
        __IO  uint8_t RESERVED45[2];
    union {
        __IO  uint8_t PRLL15;
        stc_mft_ppg_prll15_field_t PRLL15_f;
    };
    union {
        __IO  uint8_t PRLH15;
        stc_mft_ppg_prlh15_field_t PRLH15_f;
    };
        __IO  uint8_t RESERVED46[2];
    union {
        __IO  uint8_t GATEC12;
        stc_mft_ppg_gatec12_field_t GATEC12_f;
    };
        __IO  uint8_t RESERVED47[39];
    union {
        __IO  uint8_t PPGC17;
        stc_mft_ppg_ppgc17_field_t PPGC17_f;
    };
    union {
        __IO  uint8_t PPGC16;
        stc_mft_ppg_ppgc16_field_t PPGC16_f;
    };
        __IO  uint8_t RESERVED48[2];
    union {
        __IO  uint8_t PPGC19;
        stc_mft_ppg_ppgc19_field_t PPGC19_f;
    };
    union {
        __IO  uint8_t PPGC18;
        stc_mft_ppg_ppgc18_field_t PPGC18_f;
    };
        __IO  uint8_t RESERVED49[2];
    union {
        __IO  uint8_t PRLL16;
        stc_mft_ppg_prll16_field_t PRLL16_f;
    };
    union {
        __IO  uint8_t PRLH16;
        stc_mft_ppg_prlh16_field_t PRLH16_f;
    };
        __IO  uint8_t RESERVED50[2];
    union {
        __IO  uint8_t PRLL17;
        stc_mft_ppg_prll17_field_t PRLL17_f;
    };
    union {
        __IO  uint8_t PRLH17;
        stc_mft_ppg_prlh17_field_t PRLH17_f;
    };
        __IO  uint8_t RESERVED51[2];
    union {
        __IO  uint8_t PRLL18;
        stc_mft_ppg_prll18_field_t PRLL18_f;
    };
    union {
        __IO  uint8_t PRLH18;
        stc_mft_ppg_prlh18_field_t PRLH18_f;
    };
        __IO  uint8_t RESERVED52[2];
    union {
        __IO  uint8_t PRLL19;
        stc_mft_ppg_prll19_field_t PRLL19_f;
    };
    union {
        __IO  uint8_t PRLH19;
        stc_mft_ppg_prlh19_field_t PRLH19_f;
    };
        __IO  uint8_t RESERVED53[2];
    union {
        __IO  uint8_t GATEC16;
        stc_mft_ppg_gatec16_field_t GATEC16_f;
    };
        __IO  uint8_t RESERVED54[39];
    union {
        __IO  uint8_t PPGC21;
        stc_mft_ppg_ppgc21_field_t PPGC21_f;
    };
    union {
        __IO  uint8_t PPGC20;
        stc_mft_ppg_ppgc20_field_t PPGC20_f;
    };
        __IO  uint8_t RESERVED55[2];
    union {
        __IO  uint8_t PPGC23;
        stc_mft_ppg_ppgc23_field_t PPGC23_f;
    };
    union {
        __IO  uint8_t PPGC22;
        stc_mft_ppg_ppgc22_field_t PPGC22_f;
    };
        __IO  uint8_t RESERVED56[2];
    union {
        __IO  uint8_t PRLL20;
        stc_mft_ppg_prll20_field_t PRLL20_f;
    };
    union {
        __IO  uint8_t PRLH20;
        stc_mft_ppg_prlh20_field_t PRLH20_f;
    };
        __IO  uint8_t RESERVED57[2];
    union {
        __IO  uint8_t PRLL21;
        stc_mft_ppg_prll21_field_t PRLL21_f;
    };
    union {
        __IO  uint8_t PRLH21;
        stc_mft_ppg_prlh21_field_t PRLH21_f;
    };
        __IO  uint8_t RESERVED58[2];
    union {
        __IO  uint8_t PRLL22;
        stc_mft_ppg_prll22_field_t PRLL22_f;
    };
    union {
        __IO  uint8_t PRLH22;
        stc_mft_ppg_prlh22_field_t PRLH22_f;
    };
        __IO  uint8_t RESERVED59[2];
    union {
        __IO  uint8_t PRLL23;
        stc_mft_ppg_prll23_field_t PRLL23_f;
    };
    union {
        __IO  uint8_t PRLH23;
        stc_mft_ppg_prlh23_field_t PRLH23_f;
    };
        __IO  uint8_t RESERVED60[2];
    union {
        __IO  uint8_t GATEC20;
        stc_mft_ppg_gatec20_field_t GATEC20_f;
    };
} FM_MFT_PPG_TypeDef, FM4_MFT_PPG_TypeDef;

/*******************************************************************************
* PCRC_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO uint32_t PCRC_POLY;
        struct {
          union {
            __IO uint16_t PCRC_POLYL;
            struct {
              __IO uint8_t PCRC_POLYLL;
              __IO uint8_t PCRC_POLYLH;
            };
          };
          union {
            __IO uint16_t PCRC_POLYH;
            struct {
              __IO uint8_t PCRC_POLYHL;
              __IO uint8_t PCRC_POLYHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PCRC_SEED;
        struct {
          union {
            __IO uint16_t PCRC_SEEDL;
            struct {
              __IO uint8_t PCRC_SEEDLL;
              __IO uint8_t PCRC_SEEDLH;
            };
          };
          union {
            __IO uint16_t PCRC_SEEDH;
            struct {
              __IO uint8_t PCRC_SEEDHL;
              __IO uint8_t PCRC_SEEDHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PCRC_FXOR;
        struct {
          union {
            __IO uint16_t PCRC_FXORL;
            struct {
              __IO uint8_t PCRC_FXORLL;
              __IO uint8_t PCRC_FXORLH;
            };
          };
          union {
            __IO uint16_t PCRC_FXORH;
            struct {
              __IO uint8_t PCRC_FXORHL;
              __IO uint8_t PCRC_FXORHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PCRC_CFG;
        stc_pcrc_pcrc_cfg_field_t PCRC_CFG_f;
        struct {
          union {
            __IO uint16_t PCRC_CFGL;
            struct {
              __IO uint8_t PCRC_CFGLL;
              __IO uint8_t PCRC_CFGLH;
            };
          };
          union {
            __IO uint16_t PCRC_CFGH;
            struct {
              __IO uint8_t PCRC_CFGHL;
              __IO uint8_t PCRC_CFGHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PCRC_WR;
        struct {
          union {
            __IO uint16_t PCRC_WRL;
            struct {
              __IO uint8_t PCRC_WRLL;
              __IO uint8_t PCRC_WRLH;
            };
          };
          union {
            __IO uint16_t PCRC_WRH;
            struct {
              __IO uint8_t PCRC_WRHL;
              __IO uint8_t PCRC_WRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t PCRC_RD;
        struct {
          union {
            __IO uint16_t PCRC_RDL;
            struct {
              __IO uint8_t PCRC_RDLL;
              __IO uint8_t PCRC_RDLH;
            };
          };
          union {
            __IO uint16_t PCRC_RDH;
            struct {
              __IO uint8_t PCRC_RDHL;
              __IO uint8_t PCRC_RDHH;
            };
          };
        };
    };
} FM_PCRC_TypeDef, FM4_PCRC_TypeDef;

/*******************************************************************************
* QPRC_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO uint16_t QPCR;
        struct {
            __IO  uint8_t QPCRL;
            __IO  uint8_t QPCRH;
        };
    };
        __IO  uint8_t RESERVED0[2];
    union {
        __IO uint16_t QRCR;
        struct {
            __IO  uint8_t QRCRL;
            __IO  uint8_t QRCRH;
        };
    };
        __IO  uint8_t RESERVED1[2];
    union {
        __IO uint16_t QPCCR;
        struct {
            __IO  uint8_t QPCCRL;
            __IO  uint8_t QPCCRH;
        };
    };
        __IO  uint8_t RESERVED2[2];
    union {
        __IO uint16_t QPRCR;
        struct {
            __IO  uint8_t QPRCRL;
            __IO  uint8_t QPRCRH;
        };
    };
        __IO  uint8_t RESERVED3[2];
    union {
        __IO uint16_t QMPR;
        struct {
            __IO  uint8_t QMPRL;
            __IO  uint8_t QMPRH;
        };
    };
        __IO  uint8_t RESERVED4[2];
    union {
        __IO  uint8_t QICRL;
        stc_qprc_qicrl_field_t QICRL_f;
    };
    union {
        __IO  uint8_t QICRH;
        stc_qprc_qicrh_field_t QICRH_f;
    };
        __IO  uint8_t RESERVED5[2];
    union {
        __IO uint16_t QCR;
        stc_qprc_qcr_field_t QCR_f;
        struct {
            __IO  uint8_t QCRL;
            __IO  uint8_t QCRH;
        };
    };
        __IO  uint8_t RESERVED6[2];
    union {
        __IO uint16_t QECR;
        stc_qprc_qecr_field_t QECR_f;
        struct {
            __IO  uint8_t QECRL;
            __IO  uint8_t QECRH;
        };
    };
        __IO  uint8_t RESERVED7[30];
    union {
        __IO uint32_t QPRCRR;
        stc_qprc_qprcrr_field_t QPRCRR_f;
        struct {
          union {
            __IO uint16_t QPRCRRL;
            struct {
              __IO uint8_t QPRCRRLL;
              __IO uint8_t QPRCRRLH;
            };
          };
          union {
            __IO uint16_t QPRCRRH;
            struct {
              __IO uint8_t QPRCRRHL;
              __IO uint8_t QPRCRRHH;
            };
          };
        };
    };
} FM_QPRC_TypeDef, FM4_QPRC_TypeDef;

/*******************************************************************************
* QPRC_NF_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO  uint8_t NFCTLA;
        stc_qprc_nf_nfctla_field_t NFCTLA_f;
    };
        __IO  uint8_t RESERVED0[3];
    union {
        __IO  uint8_t NFCTLB;
        stc_qprc_nf_nfctlb_field_t NFCTLB_f;
    };
        __IO  uint8_t RESERVED1[3];
    union {
        __IO  uint8_t NFCTLZ;
        stc_qprc_nf_nfctlz_field_t NFCTLZ_f;
    };
} FM_QPRC_NF_TypeDef, FM4_QPRC_NF_TypeDef;

/*******************************************************************************
* RTC_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO  uint8_t WTCR10;
        stc_rtc_wtcr10_field_t WTCR10_f;
    };
        __IO  uint8_t RESERVED0[3];
    union {
        __IO  uint8_t WTCR11;
        stc_rtc_wtcr11_field_t WTCR11_f;
    };
        __IO  uint8_t RESERVED1[3];
    union {
        __IO  uint8_t WTCR12;
        stc_rtc_wtcr12_field_t WTCR12_f;
    };
        __IO  uint8_t RESERVED2[3];
    union {
        __IO  uint8_t WTCR13;
        stc_rtc_wtcr13_field_t WTCR13_f;
    };
        __IO  uint8_t RESERVED3[3];
    union {
        __IO  uint8_t WTCR20;
        stc_rtc_wtcr20_field_t WTCR20_f;
    };
        __IO  uint8_t RESERVED4[3];
    union {
        __IO  uint8_t WTCR21;
        stc_rtc_wtcr21_field_t WTCR21_f;
    };
        __IO  uint8_t RESERVED5[7];
    union {
        __IO  uint8_t WTSR;
        stc_rtc_wtsr_field_t WTSR_f;
    };
        __IO  uint8_t RESERVED6[3];
    union {
        __IO  uint8_t WTMIR;
        stc_rtc_wtmir_field_t WTMIR_f;
    };
        __IO  uint8_t RESERVED7[3];
    union {
        __IO  uint8_t WTHR;
        stc_rtc_wthr_field_t WTHR_f;
    };
        __IO  uint8_t RESERVED8[3];
    union {
        __IO  uint8_t WTDR;
        stc_rtc_wtdr_field_t WTDR_f;
    };
        __IO  uint8_t RESERVED9[3];
    union {
        __IO  uint8_t WTDW;
        stc_rtc_wtdw_field_t WTDW_f;
    };
        __IO  uint8_t RESERVED10[3];
    union {
        __IO  uint8_t WTMOR;
        stc_rtc_wtmor_field_t WTMOR_f;
    };
        __IO  uint8_t RESERVED11[3];
    union {
        __IO  uint8_t WTYR;
        stc_rtc_wtyr_field_t WTYR_f;
    };
        __IO  uint8_t RESERVED12[3];
    union {
        __IO  uint8_t ALMIR;
        stc_rtc_almir_field_t ALMIR_f;
    };
        __IO  uint8_t RESERVED13[3];
    union {
        __IO  uint8_t ALHR;
        stc_rtc_alhr_field_t ALHR_f;
    };
        __IO  uint8_t RESERVED14[3];
    union {
        __IO  uint8_t ALDR;
        stc_rtc_aldr_field_t ALDR_f;
    };
        __IO  uint8_t RESERVED15[3];
    union {
        __IO  uint8_t ALMOR;
        stc_rtc_almor_field_t ALMOR_f;
    };
        __IO  uint8_t RESERVED16[3];
    union {
        __IO  uint8_t ALYR;
        stc_rtc_alyr_field_t ALYR_f;
    };
        __IO  uint8_t RESERVED17[3];
    union {
        __IO  uint8_t WTTR0;
        stc_rtc_wttr0_field_t WTTR0_f;
    };
        __IO  uint8_t RESERVED18[3];
    union {
        __IO  uint8_t WTTR1;
        stc_rtc_wttr1_field_t WTTR1_f;
    };
        __IO  uint8_t RESERVED19[3];
    union {
        __IO  uint8_t WTTR2;
        stc_rtc_wttr2_field_t WTTR2_f;
    };
        __IO  uint8_t RESERVED20[3];
    union {
        __IO  uint8_t WTCAL0;
        stc_rtc_wtcal0_field_t WTCAL0_f;
    };
        __IO  uint8_t RESERVED21[3];
    union {
        __IO  uint8_t WTCAL1;
        stc_rtc_wtcal1_field_t WTCAL1_f;
    };
        __IO  uint8_t RESERVED22[3];
    union {
        __IO  uint8_t WTCALEN;
        stc_rtc_wtcalen_field_t WTCALEN_f;
    };
        __IO  uint8_t RESERVED23[3];
    union {
        __IO  uint8_t WTDIV;
        stc_rtc_wtdiv_field_t WTDIV_f;
    };
        __IO  uint8_t RESERVED24[3];
    union {
        __IO  uint8_t WTDIVEN;
        stc_rtc_wtdiven_field_t WTDIVEN_f;
    };
        __IO  uint8_t RESERVED25[3];
    union {
        __IO  uint8_t WTCALPRD;
        stc_rtc_wtcalprd_field_t WTCALPRD_f;
    };
        __IO  uint8_t RESERVED26[3];
    union {
        __IO  uint8_t WTCOSEL;
        stc_rtc_wtcosel_field_t WTCOSEL_f;
    };
        __IO  uint8_t RESERVED27[3];
    union {
        __IO  uint8_t VB_CLKDIV;
        stc_rtc_vb_clkdiv_field_t VB_CLKDIV_f;
    };
        __IO  uint8_t RESERVED28[3];
    union {
        __IO  uint8_t WTOSCCNT;
        stc_rtc_wtosccnt_field_t WTOSCCNT_f;
    };
        __IO  uint8_t RESERVED29[3];
    union {
        __IO  uint8_t CCS;
        stc_rtc_ccs_field_t CCS_f;
    };
        __IO  uint8_t RESERVED30[3];
    union {
        __IO  uint8_t CCB;
        stc_rtc_ccb_field_t CCB_f;
    };
        __IO  uint8_t RESERVED31[7];
    union {
        __IO  uint8_t BOOST;
        stc_rtc_boost_field_t BOOST_f;
    };
        __IO  uint8_t RESERVED32[3];
    union {
        __IO  uint8_t EWKUP;
        stc_rtc_ewkup_field_t EWKUP_f;
    };
        __IO  uint8_t RESERVED33[3];
    union {
        __IO  uint8_t VDET;
        stc_rtc_vdet_field_t VDET_f;
    };
        __IO  uint8_t RESERVED34[7];
    union {
        __IO  uint8_t HIBRST;
        stc_rtc_hibrst_field_t HIBRST_f;
    };
        __IO  uint8_t RESERVED35[3];
    union {
        __IO  uint8_t VBPFR;
        stc_rtc_vbpfr_field_t VBPFR_f;
    };
        __IO  uint8_t RESERVED36[3];
    union {
        __IO  uint8_t VBPCR;
        stc_rtc_vbpcr_field_t VBPCR_f;
    };
        __IO  uint8_t RESERVED37[3];
    union {
        __IO  uint8_t VBDDR;
        stc_rtc_vbddr_field_t VBDDR_f;
    };
        __IO  uint8_t RESERVED38[3];
    union {
        __IO  uint8_t VBDIR;
        stc_rtc_vbdir_field_t VBDIR_f;
    };
        __IO  uint8_t RESERVED39[3];
    union {
        __IO  uint8_t VBDOR;
        stc_rtc_vbdor_field_t VBDOR_f;
    };
        __IO  uint8_t RESERVED40[3];
    union {
        __IO  uint8_t VBPZR;
        stc_rtc_vbpzr_field_t VBPZR_f;
    };
        __IO  uint8_t RESERVED41[79];
        __IO  uint8_t BREG00;
        __IO  uint8_t BREG01;
        __IO  uint8_t BREG02;
        __IO  uint8_t BREG03;
        __IO  uint8_t BREG04;
        __IO  uint8_t BREG05;
        __IO  uint8_t BREG06;
        __IO  uint8_t BREG07;
        __IO  uint8_t BREG08;
        __IO  uint8_t BREG09;
        __IO  uint8_t BREG0A;
        __IO  uint8_t BREG0B;
        __IO  uint8_t BREG0C;
        __IO  uint8_t BREG0D;
        __IO  uint8_t BREG0E;
        __IO  uint8_t BREG0F;
        __IO  uint8_t BREG10;
        __IO  uint8_t BREG11;
        __IO  uint8_t BREG12;
        __IO  uint8_t BREG13;
        __IO  uint8_t BREG14;
        __IO  uint8_t BREG15;
        __IO  uint8_t BREG16;
        __IO  uint8_t BREG17;
        __IO  uint8_t BREG18;
        __IO  uint8_t BREG19;
        __IO  uint8_t BREG1A;
        __IO  uint8_t BREG1B;
        __IO  uint8_t BREG1C;
        __IO  uint8_t BREG1D;
        __IO  uint8_t BREG1E;
        __IO  uint8_t BREG1F;
        __IO  uint8_t BREG20;
        __IO  uint8_t BREG21;
        __IO  uint8_t BREG22;
        __IO  uint8_t BREG23;
        __IO  uint8_t BREG24;
        __IO  uint8_t BREG25;
        __IO  uint8_t BREG26;
        __IO  uint8_t BREG27;
        __IO  uint8_t BREG28;
        __IO  uint8_t BREG29;
        __IO  uint8_t BREG2A;
        __IO  uint8_t BREG2B;
        __IO  uint8_t BREG2C;
        __IO  uint8_t BREG2D;
        __IO  uint8_t BREG2E;
        __IO  uint8_t BREG2F;
        __IO  uint8_t BREG30;
        __IO  uint8_t BREG31;
        __IO  uint8_t BREG32;
        __IO  uint8_t BREG33;
        __IO  uint8_t BREG34;
        __IO  uint8_t BREG35;
        __IO  uint8_t BREG36;
        __IO  uint8_t BREG37;
        __IO  uint8_t BREG38;
        __IO  uint8_t BREG39;
        __IO  uint8_t BREG3A;
        __IO  uint8_t BREG3B;
        __IO  uint8_t BREG3C;
        __IO  uint8_t BREG3D;
        __IO  uint8_t BREG3E;
        __IO  uint8_t BREG3F;
        __IO  uint8_t BREG40;
        __IO  uint8_t BREG41;
        __IO  uint8_t BREG42;
        __IO  uint8_t BREG43;
        __IO  uint8_t BREG44;
        __IO  uint8_t BREG45;
        __IO  uint8_t BREG46;
        __IO  uint8_t BREG47;
        __IO  uint8_t BREG48;
        __IO  uint8_t BREG49;
        __IO  uint8_t BREG4A;
        __IO  uint8_t BREG4B;
        __IO  uint8_t BREG4C;
        __IO  uint8_t BREG4D;
        __IO  uint8_t BREG4E;
        __IO  uint8_t BREG4F;
        __IO  uint8_t BREG50;
        __IO  uint8_t BREG51;
        __IO  uint8_t BREG52;
        __IO  uint8_t BREG53;
        __IO  uint8_t BREG54;
        __IO  uint8_t BREG55;
        __IO  uint8_t BREG56;
        __IO  uint8_t BREG57;
        __IO  uint8_t BREG58;
        __IO  uint8_t BREG59;
        __IO  uint8_t BREG5A;
        __IO  uint8_t BREG5B;
        __IO  uint8_t BREG5C;
        __IO  uint8_t BREG5D;
        __IO  uint8_t BREG5E;
        __IO  uint8_t BREG5F;
        __IO  uint8_t BREG60;
        __IO  uint8_t BREG61;
        __IO  uint8_t BREG62;
        __IO  uint8_t BREG63;
        __IO  uint8_t BREG64;
        __IO  uint8_t BREG65;
        __IO  uint8_t BREG66;
        __IO  uint8_t BREG67;
        __IO  uint8_t BREG68;
        __IO  uint8_t BREG69;
        __IO  uint8_t BREG6A;
        __IO  uint8_t BREG6B;
        __IO  uint8_t BREG6C;
        __IO  uint8_t BREG6D;
        __IO  uint8_t BREG6E;
        __IO  uint8_t BREG6F;
        __IO  uint8_t BREG70;
        __IO  uint8_t BREG71;
        __IO  uint8_t BREG72;
        __IO  uint8_t BREG73;
        __IO  uint8_t BREG74;
        __IO  uint8_t BREG75;
        __IO  uint8_t BREG76;
        __IO  uint8_t BREG77;
        __IO  uint8_t BREG78;
        __IO  uint8_t BREG79;
        __IO  uint8_t BREG7A;
        __IO  uint8_t BREG7B;
        __IO  uint8_t BREG7C;
        __IO  uint8_t BREG7D;
        __IO  uint8_t BREG7E;
        __IO  uint8_t BREG7F;
} FM_RTC_TypeDef, FM4_RTC_TypeDef;

/*******************************************************************************
* SBSSR_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
        __IO  uint8_t RESERVED0[252];
    union {
        __IO uint16_t BTSSSR;
        stc_sbssr_btsssr_field_t BTSSSR_f;
        struct {
            __IO  uint8_t BTSSSRL;
            __IO  uint8_t BTSSSRH;
        };
    };
} FM_SBSSR_TypeDef, FM4_SBSSR_TypeDef;

/*******************************************************************************
* SDIF_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO uint32_t SSA2;
        struct {
          union {
            __IO uint16_t SSA2L;
            struct {
              __IO uint8_t SSA2LL;
              __IO uint8_t SSA2LH;
            };
          };
          union {
            __IO uint16_t SSA2H;
            struct {
              __IO uint8_t SSA2HL;
              __IO uint8_t SSA2HH;
            };
          };
        };
    };
    union {
        __IO uint16_t SBSIZE;
        stc_sdif_sbsize_field_t SBSIZE_f;
        struct {
            __IO  uint8_t SBSIZEL;
            __IO  uint8_t SBSIZEH;
        };
    };
    union {
        __IO uint16_t SBLCNT;
        struct {
            __IO  uint8_t SBLCNTL;
            __IO  uint8_t SBLCNTH;
        };
    };
    union {
        __IO uint32_t SSA1;
        struct {
          union {
            __IO uint16_t SSA1L;
            struct {
              __IO uint8_t SSA1LL;
              __IO uint8_t SSA1LH;
            };
          };
          union {
            __IO uint16_t SSA1H;
            struct {
              __IO uint8_t SSA1HL;
              __IO uint8_t SSA1HH;
            };
          };
        };
    };
    union {
        __IO uint16_t STRSFMD;
        stc_sdif_strsfmd_field_t STRSFMD_f;
        struct {
            __IO  uint8_t STRSFMDL;
            __IO  uint8_t STRSFMDH;
        };
    };
    union {
        __IO uint16_t SCMMD;
        stc_sdif_scmmd_field_t SCMMD_f;
        struct {
            __IO  uint8_t SCMMDL;
            __IO  uint8_t SCMMDH;
        };
    };
    union {
        __IO uint16_t SRESP0;
        struct {
            __IO  uint8_t SRESP0L;
            __IO  uint8_t SRESP0H;
        };
    };
    union {
        __IO uint16_t SRESP1;
        struct {
            __IO  uint8_t SRESP1L;
            __IO  uint8_t SRESP1H;
        };
    };
    union {
        __IO uint16_t SRESP2;
        struct {
            __IO  uint8_t SRESP2L;
            __IO  uint8_t SRESP2H;
        };
    };
    union {
        __IO uint16_t SRESP3;
        struct {
            __IO  uint8_t SRESP3L;
            __IO  uint8_t SRESP3H;
        };
    };
    union {
        __IO uint16_t SRESP4;
        struct {
            __IO  uint8_t SRESP4L;
            __IO  uint8_t SRESP4H;
        };
    };
    union {
        __IO uint16_t SRESP5;
        struct {
            __IO  uint8_t SRESP5L;
            __IO  uint8_t SRESP5H;
        };
    };
    union {
        __IO uint16_t SRESP6;
        struct {
            __IO  uint8_t SRESP6L;
            __IO  uint8_t SRESP6H;
        };
    };
    union {
        __IO uint16_t SRESP7;
        struct {
            __IO  uint8_t SRESP7L;
            __IO  uint8_t SRESP7H;
        };
    };
    union {
        __IO uint32_t SBUFDP;
        struct {
          union {
            __IO uint16_t SBUFDPL;
            struct {
              __IO uint8_t SBUFDPLL;
              __IO uint8_t SBUFDPLH;
            };
          };
          union {
            __IO uint16_t SBUFDPH;
            struct {
              __IO uint8_t SBUFDPHL;
              __IO uint8_t SBUFDPHH;
            };
          };
        };
    };
    union {
        __IO uint32_t SPRSTAT;
        stc_sdif_sprstat_field_t SPRSTAT_f;
        struct {
          union {
            __IO uint16_t SPRSTATL;
            struct {
              __IO uint8_t SPRSTATLL;
              __IO uint8_t SPRSTATLH;
            };
          };
          union {
            __IO uint16_t SPRSTATH;
            struct {
              __IO uint8_t SPRSTATHL;
              __IO uint8_t SPRSTATHH;
            };
          };
        };
    };
    union {
        __IO  uint8_t SHCTL1;
        stc_sdif_shctl1_field_t SHCTL1_f;
    };
    union {
        __IO  uint8_t SPWRCTL;
        stc_sdif_spwrctl_field_t SPWRCTL_f;
    };
    union {
        __IO  uint8_t SBLKGPCTL;
        stc_sdif_sblkgpctl_field_t SBLKGPCTL_f;
    };
    union {
        __IO  uint8_t SWKUPCTL;
        stc_sdif_swkupctl_field_t SWKUPCTL_f;
    };
    union {
        __IO uint16_t SCLKCTL;
        stc_sdif_sclkctl_field_t SCLKCTL_f;
        struct {
            __IO  uint8_t SCLKCTLL;
            __IO  uint8_t SCLKCTLH;
        };
    };
    union {
        __IO  uint8_t STOCTL;
        stc_sdif_stoctl_field_t STOCTL_f;
    };
    union {
        __IO  uint8_t SSRST;
        stc_sdif_ssrst_field_t SSRST_f;
    };
    union {
        __IO uint16_t SNINTST;
        stc_sdif_snintst_field_t SNINTST_f;
        struct {
            __IO  uint8_t SNINTSTL;
            __IO  uint8_t SNINTSTH;
        };
    };
    union {
        __IO uint16_t SEINTST;
        stc_sdif_seintst_field_t SEINTST_f;
        struct {
            __IO  uint8_t SEINTSTL;
            __IO  uint8_t SEINTSTH;
        };
    };
    union {
        __IO uint16_t SNINTSTE;
        stc_sdif_snintste_field_t SNINTSTE_f;
        struct {
            __IO  uint8_t SNINTSTEL;
            __IO  uint8_t SNINTSTEH;
        };
    };
    union {
        __IO uint16_t SEINTSTE;
        stc_sdif_seintste_field_t SEINTSTE_f;
        struct {
            __IO  uint8_t SEINTSTEL;
            __IO  uint8_t SEINTSTEH;
        };
    };
    union {
        __IO uint16_t SNINTSGE;
        stc_sdif_snintsge_field_t SNINTSGE_f;
        struct {
            __IO  uint8_t SNINTSGEL;
            __IO  uint8_t SNINTSGEH;
        };
    };
    union {
        __IO uint16_t SEINTSGE;
        stc_sdif_seintsge_field_t SEINTSGE_f;
        struct {
            __IO  uint8_t SEINTSGEL;
            __IO  uint8_t SEINTSGEH;
        };
    };
    union {
        __IO uint16_t SACMDEST;
        stc_sdif_sacmdest_field_t SACMDEST_f;
        struct {
            __IO  uint8_t SACMDESTL;
            __IO  uint8_t SACMDESTH;
        };
    };
    union {
        __IO uint16_t SHCTL2;
        stc_sdif_shctl2_field_t SHCTL2_f;
        struct {
            __IO  uint8_t SHCTL2L;
            __IO  uint8_t SHCTL2H;
        };
    };
    union {
        __IO uint16_t CAPBLTY0;
        stc_sdif_capblty0_field_t CAPBLTY0_f;
        struct {
            __IO  uint8_t CAPBLTY0L;
            __IO  uint8_t CAPBLTY0H;
        };
    };
    union {
        __IO uint16_t CAPBLTY1;
        stc_sdif_capblty1_field_t CAPBLTY1_f;
        struct {
            __IO  uint8_t CAPBLTY1L;
            __IO  uint8_t CAPBLTY1H;
        };
    };
    union {
        __IO uint16_t CAPBLTY2;
        stc_sdif_capblty2_field_t CAPBLTY2_f;
        struct {
            __IO  uint8_t CAPBLTY2L;
            __IO  uint8_t CAPBLTY2H;
        };
    };
    union {
        __IO uint16_t CAPBLTY3;
        stc_sdif_capblty3_field_t CAPBLTY3_f;
        struct {
            __IO  uint8_t CAPBLTY3L;
            __IO  uint8_t CAPBLTY3H;
        };
    };
    union {
        __IO uint16_t MXCCAPY0;
        stc_sdif_mxccapy0_field_t MXCCAPY0_f;
        struct {
            __IO  uint8_t MXCCAPY0L;
            __IO  uint8_t MXCCAPY0H;
        };
    };
    union {
        __IO uint16_t MXCCAPY1;
        stc_sdif_mxccapy1_field_t MXCCAPY1_f;
        struct {
            __IO  uint8_t MXCCAPY1L;
            __IO  uint8_t MXCCAPY1H;
        };
    };
    union {
        __IO uint16_t MXCCAPY2;
        struct {
            __IO  uint8_t MXCCAPY2L;
            __IO  uint8_t MXCCAPY2H;
        };
    };
    union {
        __IO uint16_t MXCCAPY3;
        struct {
            __IO  uint8_t MXCCAPY3L;
            __IO  uint8_t MXCCAPY3H;
        };
    };
    union {
        __IO uint16_t FEACEST;
        stc_sdif_feacest_field_t FEACEST_f;
        struct {
            __IO  uint8_t FEACESTL;
            __IO  uint8_t FEACESTH;
        };
    };
    union {
        __IO uint16_t SFEEIST;
        stc_sdif_sfeeist_field_t SFEEIST_f;
        struct {
            __IO  uint8_t SFEEISTL;
            __IO  uint8_t SFEEISTH;
        };
    };
    union {
        __IO  uint8_t ADMAEST;
        stc_sdif_admaest_field_t ADMAEST_f;
    };
        __IO  uint8_t RESERVED0[3];
    union {
        __IO uint16_t SADSA0;
        stc_sdif_sadsa0_field_t SADSA0_f;
        struct {
            __IO  uint8_t SADSA0L;
            __IO  uint8_t SADSA0H;
        };
    };
    union {
        __IO uint16_t SADSA1;
        stc_sdif_sadsa1_field_t SADSA1_f;
        struct {
            __IO  uint8_t SADSA1L;
            __IO  uint8_t SADSA1H;
        };
    };
    union {
        __IO uint16_t SADSA2;
        stc_sdif_sadsa2_field_t SADSA2_f;
        struct {
            __IO  uint8_t SADSA2L;
            __IO  uint8_t SADSA2H;
        };
    };
    union {
        __IO uint16_t SADSA3;
        stc_sdif_sadsa3_field_t SADSA3_f;
        struct {
            __IO  uint8_t SADSA3L;
            __IO  uint8_t SADSA3H;
        };
    };
    union {
        __IO uint16_t SPRVAL0;
        stc_sdif_sprval0_field_t SPRVAL0_f;
        struct {
            __IO  uint8_t SPRVAL0L;
            __IO  uint8_t SPRVAL0H;
        };
    };
    union {
        __IO uint16_t SPRVAL1;
        stc_sdif_sprval1_field_t SPRVAL1_f;
        struct {
            __IO  uint8_t SPRVAL1L;
            __IO  uint8_t SPRVAL1H;
        };
    };
    union {
        __IO uint16_t SPRVAL2;
        stc_sdif_sprval2_field_t SPRVAL2_f;
        struct {
            __IO  uint8_t SPRVAL2L;
            __IO  uint8_t SPRVAL2H;
        };
    };
    union {
        __IO uint16_t SPRVAL3;
        stc_sdif_sprval3_field_t SPRVAL3_f;
        struct {
            __IO  uint8_t SPRVAL3L;
            __IO  uint8_t SPRVAL3H;
        };
    };
    union {
        __IO uint16_t SPRVAL4;
        stc_sdif_sprval4_field_t SPRVAL4_f;
        struct {
            __IO  uint8_t SPRVAL4L;
            __IO  uint8_t SPRVAL4H;
        };
    };
    union {
        __IO uint16_t SPRVAL5;
        stc_sdif_sprval5_field_t SPRVAL5_f;
        struct {
            __IO  uint8_t SPRVAL5L;
            __IO  uint8_t SPRVAL5H;
        };
    };
    union {
        __IO uint16_t SPRVAL6;
        stc_sdif_sprval6_field_t SPRVAL6_f;
        struct {
            __IO  uint8_t SPRVAL6L;
            __IO  uint8_t SPRVAL6H;
        };
    };
    union {
        __IO uint16_t SPRVAL7;
        stc_sdif_sprval7_field_t SPRVAL7_f;
        struct {
            __IO  uint8_t SPRVAL7L;
            __IO  uint8_t SPRVAL7H;
        };
    };
        __IO  uint8_t RESERVED1[112];
    union {
        __IO uint16_t SSHBCTLL;
        stc_sdif_sshbctll_field_t SSHBCTLL_f;
        struct {
            __IO  uint8_t SSHBCTLLL;
            __IO  uint8_t SSHBCTLLH;
        };
    };
    union {
        __IO uint16_t SSHBCTLH;
        stc_sdif_sshbctlh_field_t SSHBCTLH_f;
        struct {
            __IO  uint8_t SSHBCTLHL;
            __IO  uint8_t SSHBCTLHH;
        };
    };
        __IO  uint8_t RESERVED2[24];
    union {
        __IO uint16_t SSLIST;
        stc_sdif_sslist_field_t SSLIST_f;
        struct {
            __IO  uint8_t SSLISTL;
            __IO  uint8_t SSLISTH;
        };
    };
    union {
        __IO uint16_t SHCTLV;
        stc_sdif_shctlv_field_t SHCTLV_f;
        struct {
            __IO  uint8_t SHCTLVL;
            __IO  uint8_t SHCTLVH;
        };
    };
    union {
        __IO uint16_t AHBCFGL;
        stc_sdif_ahbcfgl_field_t AHBCFGL_f;
        struct {
            __IO  uint8_t AHBCFGLL;
            __IO  uint8_t AHBCFGLH;
        };
    };
    union {
        __IO uint16_t AHBCFGH;
        struct {
            __IO  uint8_t AHBCFGHL;
            __IO  uint8_t AHBCFGHH;
        };
    };
    union {
        __IO uint16_t SPWSWCL;
        stc_sdif_spwswcl_field_t SPWSWCL_f;
        struct {
            __IO  uint8_t SPWSWCLL;
            __IO  uint8_t SPWSWCLH;
        };
    };
    union {
        __IO uint16_t SPWSWCH;
        struct {
            __IO  uint8_t SPWSWCHL;
            __IO  uint8_t SPWSWCHH;
        };
    };
    union {
        __IO uint16_t STUNSETL;
        stc_sdif_stunsetl_field_t STUNSETL_f;
        struct {
            __IO  uint8_t STUNSETLL;
            __IO  uint8_t STUNSETLH;
        };
    };
    union {
        __IO uint16_t STUNSETH;
        stc_sdif_stunseth_field_t STUNSETH_f;
        struct {
            __IO  uint8_t STUNSETHL;
            __IO  uint8_t STUNSETHH;
        };
    };
    union {
        __IO uint16_t STUNSTL;
        stc_sdif_stunstl_field_t STUNSTL_f;
        struct {
            __IO  uint8_t STUNSTLL;
            __IO  uint8_t STUNSTLH;
        };
    };
    union {
        __IO uint16_t STUNSTH;
        stc_sdif_stunsth_field_t STUNSTH_f;
        struct {
            __IO  uint8_t STUNSTHL;
            __IO  uint8_t STUNSTHH;
        };
    };
        __IO  uint8_t RESERVED3[8];
    union {
        __IO uint16_t PSWISTL;
        stc_sdif_pswistl_field_t PSWISTL_f;
        struct {
            __IO  uint8_t PSWISTLL;
            __IO  uint8_t PSWISTLH;
        };
    };
    union {
        __IO uint16_t PSWISTH;
        struct {
            __IO  uint8_t PSWISTHL;
            __IO  uint8_t PSWISTHH;
        };
    };
    union {
        __IO uint16_t PSWISTEL;
        stc_sdif_pswistel_field_t PSWISTEL_f;
        struct {
            __IO  uint8_t PSWISTELL;
            __IO  uint8_t PSWISTELH;
        };
    };
    union {
        __IO uint16_t PSWISTEH;
        struct {
            __IO  uint8_t PSWISTEHL;
            __IO  uint8_t PSWISTEHH;
        };
    };
    union {
        __IO uint16_t PSWISGEL;
        stc_sdif_pswisgel_field_t PSWISGEL_f;
        struct {
            __IO  uint8_t PSWISGELL;
            __IO  uint8_t PSWISGELH;
        };
    };
    union {
        __IO uint16_t PSWISGEH;
        struct {
            __IO  uint8_t PSWISGEHL;
            __IO  uint8_t PSWISGEHH;
        };
    };
    union {
        __IO uint16_t MMCSDCL;
        stc_sdif_mmcsdcl_field_t MMCSDCL_f;
        struct {
            __IO  uint8_t MMCSDCLL;
            __IO  uint8_t MMCSDCLH;
        };
    };
    union {
        __IO uint16_t MMCSDCH;
        stc_sdif_mmcsdch_field_t MMCSDCH_f;
        struct {
            __IO  uint8_t MMCSDCHL;
            __IO  uint8_t MMCSDCHH;
        };
    };
    union {
        __IO uint16_t MCWIRQC0;
        stc_sdif_mcwirqc0_field_t MCWIRQC0_f;
        struct {
            __IO  uint8_t MCWIRQC0L;
            __IO  uint8_t MCWIRQC0H;
        };
    };
    union {
        __IO uint16_t MCWIRQC1;
        stc_sdif_mcwirqc1_field_t MCWIRQC1_f;
        struct {
            __IO  uint8_t MCWIRQC1L;
            __IO  uint8_t MCWIRQC1H;
        };
    };
    union {
        __IO uint16_t MCWIRQC2;
        stc_sdif_mcwirqc2_field_t MCWIRQC2_f;
        struct {
            __IO  uint8_t MCWIRQC2L;
            __IO  uint8_t MCWIRQC2H;
        };
    };
    union {
        __IO uint16_t MCWIRQC3;
        stc_sdif_mcwirqc3_field_t MCWIRQC3_f;
        struct {
            __IO  uint8_t MCWIRQC3L;
            __IO  uint8_t MCWIRQC3H;
        };
    };
    union {
        __IO uint16_t MCRPCKBL;
        stc_sdif_mcrpckbl_field_t MCRPCKBL_f;
        struct {
            __IO  uint8_t MCRPCKBLL;
            __IO  uint8_t MCRPCKBLH;
        };
    };
    union {
        __IO uint16_t MCRPCKBH;
        struct {
            __IO  uint8_t MCRPCKBHL;
            __IO  uint8_t MCRPCKBHH;
        };
    };
        __IO  uint8_t RESERVED4[32];
    union {
        __IO uint16_t SCDETECS;
        stc_sdif_scdetecs_field_t SCDETECS_f;
        struct {
            __IO  uint8_t SCDETECSL;
            __IO  uint8_t SCDETECSH;
        };
    };
} FM_SDIF_TypeDef, FM4_SDIF_TypeDef;

/*******************************************************************************
* SWWDT_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO uint32_t WDOGLOAD;
        struct {
          union {
            __IO uint16_t WDOGLOADL;
            struct {
              __IO uint8_t WDOGLOADLL;
              __IO uint8_t WDOGLOADLH;
            };
          };
          union {
            __IO uint16_t WDOGLOADH;
            struct {
              __IO uint8_t WDOGLOADHL;
              __IO uint8_t WDOGLOADHH;
            };
          };
        };
    };
    union {
        __IO uint32_t WDOGVALUE;
        struct {
          union {
            __IO uint16_t WDOGVALUEL;
            struct {
              __IO uint8_t WDOGVALUELL;
              __IO uint8_t WDOGVALUELH;
            };
          };
          union {
            __IO uint16_t WDOGVALUEH;
            struct {
              __IO uint8_t WDOGVALUEHL;
              __IO uint8_t WDOGVALUEHH;
            };
          };
        };
    };
    union {
        __IO uint32_t WDOGCONTROL;
        stc_swwdt_wdogcontrol_field_t WDOGCONTROL_f;
        struct {
          union {
            __IO uint16_t WDOGCONTROLL;
            struct {
              __IO uint8_t WDOGCONTROLLL;
              __IO uint8_t WDOGCONTROLLH;
            };
          };
          union {
            __IO uint16_t WDOGCONTROLH;
            struct {
              __IO uint8_t WDOGCONTROLHL;
              __IO uint8_t WDOGCONTROLHH;
            };
          };
        };
    };
    union {
        __IO uint32_t WDOGINTCLR;
        struct {
          union {
            __IO uint16_t WDOGINTCLRL;
            struct {
              __IO uint8_t WDOGINTCLRLL;
              __IO uint8_t WDOGINTCLRLH;
            };
          };
          union {
            __IO uint16_t WDOGINTCLRH;
            struct {
              __IO uint8_t WDOGINTCLRHL;
              __IO uint8_t WDOGINTCLRHH;
            };
          };
        };
    };
    union {
        __IO uint32_t WDOGRIS;
        stc_swwdt_wdogris_field_t WDOGRIS_f;
        struct {
          union {
            __IO uint16_t WDOGRISL;
            struct {
              __IO uint8_t WDOGRISLL;
              __IO uint8_t WDOGRISLH;
            };
          };
          union {
            __IO uint16_t WDOGRISH;
            struct {
              __IO uint8_t WDOGRISHL;
              __IO uint8_t WDOGRISHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED0[4];
    union {
        __IO uint32_t WDOGSPMC;
        stc_swwdt_wdogspmc_field_t WDOGSPMC_f;
        struct {
          union {
            __IO uint16_t WDOGSPMCL;
            struct {
              __IO uint8_t WDOGSPMCLL;
              __IO uint8_t WDOGSPMCLH;
            };
          };
          union {
            __IO uint16_t WDOGSPMCH;
            struct {
              __IO uint8_t WDOGSPMCHL;
              __IO uint8_t WDOGSPMCHH;
            };
          };
        };
    };
        __IO  uint8_t RESERVED1[3044];
    union {
        __IO uint32_t WDOGLOCK;
        struct {
          union {
            __IO uint16_t WDOGLOCKL;
            struct {
              __IO uint8_t WDOGLOCKLL;
              __IO uint8_t WDOGLOCKLH;
            };
          };
          union {
            __IO uint16_t WDOGLOCKH;
            struct {
              __IO uint8_t WDOGLOCKHL;
              __IO uint8_t WDOGLOCKHH;
            };
          };
        };
    };
} FM_SWWDT_TypeDef, FM4_SWWDT_TypeDef;

/*******************************************************************************
* UNIQUE_ID_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO uint32_t UIDR0;
        stc_unique_id_uidr0_field_t UIDR0_f;
        struct {
          union {
            __IO uint16_t UIDR0L;
            struct {
              __IO uint8_t UIDR0LL;
              __IO uint8_t UIDR0LH;
            };
          };
          union {
            __IO uint16_t UIDR0H;
            struct {
              __IO uint8_t UIDR0HL;
              __IO uint8_t UIDR0HH;
            };
          };
        };
    };
    union {
        __IO uint32_t UIDR1;
        stc_unique_id_uidr1_field_t UIDR1_f;
        struct {
          union {
            __IO uint16_t UIDR1L;
            struct {
              __IO uint8_t UIDR1LL;
              __IO uint8_t UIDR1LH;
            };
          };
          union {
            __IO uint16_t UIDR1H;
            struct {
              __IO uint8_t UIDR1HL;
              __IO uint8_t UIDR1HH;
            };
          };
        };
    };
} FM_UNIQUE_ID_TypeDef, FM4_UNIQUE_ID_TypeDef;

/*******************************************************************************
* USB_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
        __IO  uint8_t RESERVED0[8448];
    union {
        __IO uint16_t HCNT;
        stc_usb_hcnt_field_t HCNT_f;
        struct {
            __IO  uint8_t HCNTL;
            __IO  uint8_t HCNTH;
        };
    };
        __IO  uint8_t RESERVED1[2];
    union {
        __IO  uint8_t HIRQ;
        stc_usb_hirq_field_t HIRQ_f;
    };
    union {
        __IO  uint8_t HERR;
        stc_usb_herr_field_t HERR_f;
    };
        __IO  uint8_t RESERVED2[2];
    union {
        __IO  uint8_t HSTATE;
        stc_usb_hstate_field_t HSTATE_f;
    };
    union {
        __IO  uint8_t HFCOMP;
        stc_usb_hfcomp_field_t HFCOMP_f;
    };
        __IO  uint8_t RESERVED3[2];
    union {
        __IO uint16_t HRTIMER;
        stc_usb_hrtimer_field_t HRTIMER_f;
        struct {
            __IO  uint8_t HRTIMERL;
            __IO  uint8_t HRTIMERH;
        };
    };
        __IO  uint8_t RESERVED4[2];
    union {
        __IO  uint8_t HRTIMER2;
        stc_usb_hrtimer2_field_t HRTIMER2_f;
    };
    union {
        __IO  uint8_t HADR;
        stc_usb_hadr_field_t HADR_f;
    };
        __IO  uint8_t RESERVED5[2];
    union {
        __IO uint16_t HEOF;
        stc_usb_heof_field_t HEOF_f;
        struct {
            __IO  uint8_t HEOFL;
            __IO  uint8_t HEOFH;
        };
    };
        __IO  uint8_t RESERVED6[2];
    union {
        __IO uint16_t HFRAME;
        stc_usb_hframe_field_t HFRAME_f;
        struct {
            __IO  uint8_t HFRAMEL;
            __IO  uint8_t HFRAMEH;
        };
    };
        __IO  uint8_t RESERVED7[2];
    union {
        __IO  uint8_t HTOKEN;
        stc_usb_htoken_field_t HTOKEN_f;
    };
        __IO  uint8_t RESERVED8[3];
    union {
        __IO uint16_t UDCC;
        stc_usb_udcc_field_t UDCC_f;
        struct {
            __IO  uint8_t UDCCL;
            __IO  uint8_t UDCCH;
        };
    };
        __IO  uint8_t RESERVED9[2];
    union {
        __IO uint16_t EP0C;
        stc_usb_ep0c_field_t EP0C_f;
        struct {
            __IO  uint8_t EP0CL;
            __IO  uint8_t EP0CH;
        };
    };
        __IO  uint8_t RESERVED10[2];
    union {
        __IO uint16_t EP1C;
        stc_usb_ep1c_field_t EP1C_f;
        struct {
            __IO  uint8_t EP1CL;
            __IO  uint8_t EP1CH;
        };
    };
        __IO  uint8_t RESERVED11[2];
    union {
        __IO uint16_t EP2C;
        stc_usb_ep2c_field_t EP2C_f;
        struct {
            __IO  uint8_t EP2CL;
            __IO  uint8_t EP2CH;
        };
    };
        __IO  uint8_t RESERVED12[2];
    union {
        __IO uint16_t EP3C;
        stc_usb_ep3c_field_t EP3C_f;
        struct {
            __IO  uint8_t EP3CL;
            __IO  uint8_t EP3CH;
        };
    };
        __IO  uint8_t RESERVED13[2];
    union {
        __IO uint16_t EP4C;
        stc_usb_ep4c_field_t EP4C_f;
        struct {
            __IO  uint8_t EP4CL;
            __IO  uint8_t EP4CH;
        };
    };
        __IO  uint8_t RESERVED14[2];
    union {
        __IO uint16_t EP5C;
        stc_usb_ep5c_field_t EP5C_f;
        struct {
            __IO  uint8_t EP5CL;
            __IO  uint8_t EP5CH;
        };
    };
        __IO  uint8_t RESERVED15[2];
    union {
        __IO uint16_t TMSP;
        stc_usb_tmsp_field_t TMSP_f;
        struct {
            __IO  uint8_t TMSPL;
            __IO  uint8_t TMSPH;
        };
    };
        __IO  uint8_t RESERVED16[2];
    union {
        __IO  uint8_t UDCS;
        stc_usb_udcs_field_t UDCS_f;
    };
    union {
        __IO  uint8_t UDCIE;
        stc_usb_udcie_field_t UDCIE_f;
    };
        __IO  uint8_t RESERVED17[2];
    union {
        __IO uint16_t EP0IS;
        stc_usb_ep0is_field_t EP0IS_f;
        struct {
            __IO  uint8_t EP0ISL;
            __IO  uint8_t EP0ISH;
        };
    };
        __IO  uint8_t RESERVED18[2];
    union {
        __IO uint16_t EP0OS;
        stc_usb_ep0os_field_t EP0OS_f;
        struct {
            __IO  uint8_t EP0OSL;
            __IO  uint8_t EP0OSH;
        };
    };
        __IO  uint8_t RESERVED19[2];
    union {
        __IO uint16_t EP1S;
        stc_usb_ep1s_field_t EP1S_f;
        struct {
            __IO  uint8_t EP1SL;
            __IO  uint8_t EP1SH;
        };
    };
        __IO  uint8_t RESERVED20[2];
    union {
        __IO uint16_t EP2S;
        stc_usb_ep2s_field_t EP2S_f;
        struct {
            __IO  uint8_t EP2SL;
            __IO  uint8_t EP2SH;
        };
    };
        __IO  uint8_t RESERVED21[2];
    union {
        __IO uint16_t EP3S;
        stc_usb_ep3s_field_t EP3S_f;
        struct {
            __IO  uint8_t EP3SL;
            __IO  uint8_t EP3SH;
        };
    };
        __IO  uint8_t RESERVED22[2];
    union {
        __IO uint16_t EP4S;
        stc_usb_ep4s_field_t EP4S_f;
        struct {
            __IO  uint8_t EP4SL;
            __IO  uint8_t EP4SH;
        };
    };
        __IO  uint8_t RESERVED23[2];
    union {
        __IO uint16_t EP5S;
        stc_usb_ep5s_field_t EP5S_f;
        struct {
            __IO  uint8_t EP5SL;
            __IO  uint8_t EP5SH;
        };
    };
        __IO  uint8_t RESERVED24[2];
    union {
        __IO uint16_t EP0DT;
        stc_usb_ep0dt_field_t EP0DT_f;
        struct {
            __IO  uint8_t EP0DTL;
            __IO  uint8_t EP0DTH;
        };
    };
        __IO  uint8_t RESERVED25[2];
    union {
        __IO uint16_t EP1DT;
        stc_usb_ep1dt_field_t EP1DT_f;
        struct {
            __IO  uint8_t EP1DTL;
            __IO  uint8_t EP1DTH;
        };
    };
        __IO  uint8_t RESERVED26[2];
    union {
        __IO uint16_t EP2DT;
        stc_usb_ep2dt_field_t EP2DT_f;
        struct {
            __IO  uint8_t EP2DTL;
            __IO  uint8_t EP2DTH;
        };
    };
        __IO  uint8_t RESERVED27[2];
    union {
        __IO uint16_t EP3DT;
        stc_usb_ep3dt_field_t EP3DT_f;
        struct {
            __IO  uint8_t EP3DTL;
            __IO  uint8_t EP3DTH;
        };
    };
        __IO  uint8_t RESERVED28[2];
    union {
        __IO uint16_t EP4DT;
        stc_usb_ep4dt_field_t EP4DT_f;
        struct {
            __IO  uint8_t EP4DTL;
            __IO  uint8_t EP4DTH;
        };
    };
        __IO  uint8_t RESERVED29[2];
    union {
        __IO uint16_t EP5DT;
        stc_usb_ep5dt_field_t EP5DT_f;
        struct {
            __IO  uint8_t EP5DTL;
            __IO  uint8_t EP5DTH;
        };
    };
} FM_USB_TypeDef, FM4_USB_TypeDef;

/*******************************************************************************
* USBETHERCLK_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO  uint8_t UCCR;
        stc_usbetherclk_uccr_field_t UCCR_f;
    };
        __IO  uint8_t RESERVED0[3];
    union {
        __IO  uint8_t UPCR1;
        stc_usbetherclk_upcr1_field_t UPCR1_f;
    };
        __IO  uint8_t RESERVED1[3];
    union {
        __IO  uint8_t UPCR2;
        stc_usbetherclk_upcr2_field_t UPCR2_f;
    };
        __IO  uint8_t RESERVED2[3];
    union {
        __IO  uint8_t UPCR3;
        stc_usbetherclk_upcr3_field_t UPCR3_f;
    };
        __IO  uint8_t RESERVED3[3];
    union {
        __IO  uint8_t UPCR4;
        stc_usbetherclk_upcr4_field_t UPCR4_f;
    };
        __IO  uint8_t RESERVED4[3];
    union {
        __IO  uint8_t UP_STR;
        stc_usbetherclk_up_str_field_t UP_STR_f;
    };
        __IO  uint8_t RESERVED5[3];
    union {
        __IO  uint8_t UPINT_ENR;
        stc_usbetherclk_upint_enr_field_t UPINT_ENR_f;
    };
        __IO  uint8_t RESERVED6[3];
    union {
        __IO  uint8_t UPINT_CLR;
        stc_usbetherclk_upint_clr_field_t UPINT_CLR_f;
    };
        __IO  uint8_t RESERVED7[3];
    union {
        __IO  uint8_t UPINT_STR;
        stc_usbetherclk_upint_str_field_t UPINT_STR_f;
    };
        __IO  uint8_t RESERVED8[3];
    union {
        __IO  uint8_t UPCR5;
        stc_usbetherclk_upcr5_field_t UPCR5_f;
    };
        __IO  uint8_t RESERVED9[3];
    union {
        __IO  uint8_t UPCR6;
        stc_usbetherclk_upcr6_field_t UPCR6_f;
    };
        __IO  uint8_t RESERVED10[3];
    union {
        __IO  uint8_t UPCR7;
        stc_usbetherclk_upcr7_field_t UPCR7_f;
    };
        __IO  uint8_t RESERVED11[3];
    union {
        __IO  uint8_t USBEN0;
        stc_usbetherclk_usben0_field_t USBEN0_f;
    };
        __IO  uint8_t RESERVED12[3];
    union {
        __IO  uint8_t USBEN1;
        stc_usbetherclk_usben1_field_t USBEN1_f;
    };
} FM_USBETHERCLK_TypeDef, FM4_USBETHERCLK_TypeDef;

/*******************************************************************************
* WC_MODULE
*   register structur
*******************************************************************************/
typedef struct
{
    union {
        __IO  uint8_t WCRD;
        stc_wc_wcrd_field_t WCRD_f;
    };
    union {
        __IO  uint8_t WCRL;
        stc_wc_wcrl_field_t WCRL_f;
    };
    union {
        __IO  uint8_t WCCR;
        stc_wc_wccr_field_t WCCR_f;
    };
        __IO  uint8_t RESERVED0[13];
    union {
        __IO uint16_t CLK_SEL;
        stc_wc_clk_sel_field_t CLK_SEL_f;
        struct {
            __IO  uint8_t CLK_SELL;
            __IO  uint8_t CLK_SELH;
        };
    };
        __IO  uint8_t RESERVED1[2];
    union {
        __IO  uint8_t CLK_EN;
        stc_wc_clk_en_field_t CLK_EN_f;
    };
} FM_WC_TypeDef, FM4_WC_TypeDef;

/*******************************************************************************
* Peripheral Memory Map
*******************************************************************************/
#define FM_FLASH_BASE                             (0x00000000UL) /* Flash Base Address */
#define FM4_FLASH_BASE                            (0x00000000UL) /* Flash Base Address */
#define FM_PERIPH_BASE                            (0x40000000UL) /* Peripheral Base Address */
#define FM4_PERIPH_BASE                           (0x40000000UL) /* Peripheral Base Address */
#define FM_CM4_BASE                               (0xE0100000UL) /* CM4 Private */
#define FM4_CM4_BASE                              (0xE0100000UL) /* CM4 Private  */

#define FM_ADC0_BASE                              (0x40027000UL) /* ADC0 Base Address */
#define FM4_ADC0_BASE                             (0x40027000UL) /* ADC0 Base Address */
#define FM_ADC1_BASE                              (0x40027100UL) /* ADC1 Base Address */
#define FM4_ADC1_BASE                             (0x40027100UL) /* ADC1 Base Address */
#define FM_ADC2_BASE                              (0x40027200UL) /* ADC2 Base Address */
#define FM4_ADC2_BASE                             (0x40027200UL) /* ADC2 Base Address */
#define FM_BT0_BASE                               (0x40025000UL) /* BT0 Base Address */
#define FM4_BT0_BASE                              (0x40025000UL) /* BT0 Base Address */
#define FM_BT0_PPG_BASE                           (0x40025000UL) /* BT0 Base Address */
#define FM4_BT0_PPG_BASE                          (0x40025000UL) /* BT0 Base Address */
#define FM_BT0_PWC_BASE                           (0x40025000UL) /* BT0 Base Address */
#define FM4_BT0_PWC_BASE                          (0x40025000UL) /* BT0 Base Address */
#define FM_BT0_PWM_BASE                           (0x40025000UL) /* BT0 Base Address */
#define FM4_BT0_PWM_BASE                          (0x40025000UL) /* BT0 Base Address */
#define FM_BT0_RT_BASE                            (0x40025000UL) /* BT0 Base Address */
#define FM4_BT0_RT_BASE                           (0x40025000UL) /* BT0 Base Address */
#define FM_BT1_BASE                               (0x40025040UL) /* BT1 Base Address */
#define FM4_BT1_BASE                              (0x40025040UL) /* BT1 Base Address */
#define FM_BT1_PPG_BASE                           (0x40025040UL) /* BT1 Base Address */
#define FM4_BT1_PPG_BASE                          (0x40025040UL) /* BT1 Base Address */
#define FM_BT1_PWC_BASE                           (0x40025040UL) /* BT1 Base Address */
#define FM4_BT1_PWC_BASE                          (0x40025040UL) /* BT1 Base Address */
#define FM_BT1_PWM_BASE                           (0x40025040UL) /* BT1 Base Address */
#define FM4_BT1_PWM_BASE                          (0x40025040UL) /* BT1 Base Address */
#define FM_BT1_RT_BASE                            (0x40025040UL) /* BT1 Base Address */
#define FM4_BT1_RT_BASE                           (0x40025040UL) /* BT1 Base Address */
#define FM_BT10_BASE                              (0x40025480UL) /* BT10 Base Address */
#define FM4_BT10_BASE                             (0x40025480UL) /* BT10 Base Address */
#define FM_BT10_PPG_BASE                          (0x40025480UL) /* BT10 Base Address */
#define FM4_BT10_PPG_BASE                         (0x40025480UL) /* BT10 Base Address */
#define FM_BT10_PWC_BASE                          (0x40025480UL) /* BT10 Base Address */
#define FM4_BT10_PWC_BASE                         (0x40025480UL) /* BT10 Base Address */
#define FM_BT10_PWM_BASE                          (0x40025480UL) /* BT10 Base Address */
#define FM4_BT10_PWM_BASE                         (0x40025480UL) /* BT10 Base Address */
#define FM_BT10_RT_BASE                           (0x40025480UL) /* BT10 Base Address */
#define FM4_BT10_RT_BASE                          (0x40025480UL) /* BT10 Base Address */
#define FM_BT11_BASE                              (0x400254C0UL) /* BT11 Base Address */
#define FM4_BT11_BASE                             (0x400254C0UL) /* BT11 Base Address */
#define FM_BT11_PPG_BASE                          (0x400254C0UL) /* BT11 Base Address */
#define FM4_BT11_PPG_BASE                         (0x400254C0UL) /* BT11 Base Address */
#define FM_BT11_PWC_BASE                          (0x400254C0UL) /* BT11 Base Address */
#define FM4_BT11_PWC_BASE                         (0x400254C0UL) /* BT11 Base Address */
#define FM_BT11_PWM_BASE                          (0x400254C0UL) /* BT11 Base Address */
#define FM4_BT11_PWM_BASE                         (0x400254C0UL) /* BT11 Base Address */
#define FM_BT11_RT_BASE                           (0x400254C0UL) /* BT11 Base Address */
#define FM4_BT11_RT_BASE                          (0x400254C0UL) /* BT11 Base Address */
#define FM_BT12_BASE                              (0x40025600UL) /* BT12 Base Address */
#define FM4_BT12_BASE                             (0x40025600UL) /* BT12 Base Address */
#define FM_BT12_PPG_BASE                          (0x40025600UL) /* BT12 Base Address */
#define FM4_BT12_PPG_BASE                         (0x40025600UL) /* BT12 Base Address */
#define FM_BT12_PWC_BASE                          (0x40025600UL) /* BT12 Base Address */
#define FM4_BT12_PWC_BASE                         (0x40025600UL) /* BT12 Base Address */
#define FM_BT12_PWM_BASE                          (0x40025600UL) /* BT12 Base Address */
#define FM4_BT12_PWM_BASE                         (0x40025600UL) /* BT12 Base Address */
#define FM_BT12_RT_BASE                           (0x40025600UL) /* BT12 Base Address */
#define FM4_BT12_RT_BASE                          (0x40025600UL) /* BT12 Base Address */
#define FM_BT13_BASE                              (0x40025640UL) /* BT13 Base Address */
#define FM4_BT13_BASE                             (0x40025640UL) /* BT13 Base Address */
#define FM_BT13_PPG_BASE                          (0x40025640UL) /* BT13 Base Address */
#define FM4_BT13_PPG_BASE                         (0x40025640UL) /* BT13 Base Address */
#define FM_BT13_PWC_BASE                          (0x40025640UL) /* BT13 Base Address */
#define FM4_BT13_PWC_BASE                         (0x40025640UL) /* BT13 Base Address */
#define FM_BT13_PWM_BASE                          (0x40025640UL) /* BT13 Base Address */
#define FM4_BT13_PWM_BASE                         (0x40025640UL) /* BT13 Base Address */
#define FM_BT13_RT_BASE                           (0x40025640UL) /* BT13 Base Address */
#define FM4_BT13_RT_BASE                          (0x40025640UL) /* BT13 Base Address */
#define FM_BT14_BASE                              (0x40025680UL) /* BT14 Base Address */
#define FM4_BT14_BASE                             (0x40025680UL) /* BT14 Base Address */
#define FM_BT14_PPG_BASE                          (0x40025680UL) /* BT14 Base Address */
#define FM4_BT14_PPG_BASE                         (0x40025680UL) /* BT14 Base Address */
#define FM_BT14_PWC_BASE                          (0x40025680UL) /* BT14 Base Address */
#define FM4_BT14_PWC_BASE                         (0x40025680UL) /* BT14 Base Address */
#define FM_BT14_PWM_BASE                          (0x40025680UL) /* BT14 Base Address */
#define FM4_BT14_PWM_BASE                         (0x40025680UL) /* BT14 Base Address */
#define FM_BT14_RT_BASE                           (0x40025680UL) /* BT14 Base Address */
#define FM4_BT14_RT_BASE                          (0x40025680UL) /* BT14 Base Address */
#define FM_BT15_BASE                              (0x400256C0UL) /* BT15 Base Address */
#define FM4_BT15_BASE                             (0x400256C0UL) /* BT15 Base Address */
#define FM_BT15_PPG_BASE                          (0x400256C0UL) /* BT15 Base Address */
#define FM4_BT15_PPG_BASE                         (0x400256C0UL) /* BT15 Base Address */
#define FM_BT15_PWC_BASE                          (0x400256C0UL) /* BT15 Base Address */
#define FM4_BT15_PWC_BASE                         (0x400256C0UL) /* BT15 Base Address */
#define FM_BT15_PWM_BASE                          (0x400256C0UL) /* BT15 Base Address */
#define FM4_BT15_PWM_BASE                         (0x400256C0UL) /* BT15 Base Address */
#define FM_BT15_RT_BASE                           (0x400256C0UL) /* BT15 Base Address */
#define FM4_BT15_RT_BASE                          (0x400256C0UL) /* BT15 Base Address */
#define FM_BT2_BASE                               (0x40025080UL) /* BT2 Base Address */
#define FM4_BT2_BASE                              (0x40025080UL) /* BT2 Base Address */
#define FM_BT2_PPG_BASE                           (0x40025080UL) /* BT2 Base Address */
#define FM4_BT2_PPG_BASE                          (0x40025080UL) /* BT2 Base Address */
#define FM_BT2_PWC_BASE                           (0x40025080UL) /* BT2 Base Address */
#define FM4_BT2_PWC_BASE                          (0x40025080UL) /* BT2 Base Address */
#define FM_BT2_PWM_BASE                           (0x40025080UL) /* BT2 Base Address */
#define FM4_BT2_PWM_BASE                          (0x40025080UL) /* BT2 Base Address */
#define FM_BT2_RT_BASE                            (0x40025080UL) /* BT2 Base Address */
#define FM4_BT2_RT_BASE                           (0x40025080UL) /* BT2 Base Address */
#define FM_BT3_BASE                               (0x400250C0UL) /* BT3 Base Address */
#define FM4_BT3_BASE                              (0x400250C0UL) /* BT3 Base Address */
#define FM_BT3_PPG_BASE                           (0x400250C0UL) /* BT3 Base Address */
#define FM4_BT3_PPG_BASE                          (0x400250C0UL) /* BT3 Base Address */
#define FM_BT3_PWC_BASE                           (0x400250C0UL) /* BT3 Base Address */
#define FM4_BT3_PWC_BASE                          (0x400250C0UL) /* BT3 Base Address */
#define FM_BT3_PWM_BASE                           (0x400250C0UL) /* BT3 Base Address */
#define FM4_BT3_PWM_BASE                          (0x400250C0UL) /* BT3 Base Address */
#define FM_BT3_RT_BASE                            (0x400250C0UL) /* BT3 Base Address */
#define FM4_BT3_RT_BASE                           (0x400250C0UL) /* BT3 Base Address */
#define FM_BT4_BASE                               (0x40025200UL) /* BT4 Base Address */
#define FM4_BT4_BASE                              (0x40025200UL) /* BT4 Base Address */
#define FM_BT4_PPG_BASE                           (0x40025200UL) /* BT4 Base Address */
#define FM4_BT4_PPG_BASE                          (0x40025200UL) /* BT4 Base Address */
#define FM_BT4_PWC_BASE                           (0x40025200UL) /* BT4 Base Address */
#define FM4_BT4_PWC_BASE                          (0x40025200UL) /* BT4 Base Address */
#define FM_BT4_PWM_BASE                           (0x40025200UL) /* BT4 Base Address */
#define FM4_BT4_PWM_BASE                          (0x40025200UL) /* BT4 Base Address */
#define FM_BT4_RT_BASE                            (0x40025200UL) /* BT4 Base Address */
#define FM4_BT4_RT_BASE                           (0x40025200UL) /* BT4 Base Address */
#define FM_BT5_BASE                               (0x40025240UL) /* BT5 Base Address */
#define FM4_BT5_BASE                              (0x40025240UL) /* BT5 Base Address */
#define FM_BT5_PPG_BASE                           (0x40025240UL) /* BT5 Base Address */
#define FM4_BT5_PPG_BASE                          (0x40025240UL) /* BT5 Base Address */
#define FM_BT5_PWC_BASE                           (0x40025240UL) /* BT5 Base Address */
#define FM4_BT5_PWC_BASE                          (0x40025240UL) /* BT5 Base Address */
#define FM_BT5_PWM_BASE                           (0x40025240UL) /* BT5 Base Address */
#define FM4_BT5_PWM_BASE                          (0x40025240UL) /* BT5 Base Address */
#define FM_BT5_RT_BASE                            (0x40025240UL) /* BT5 Base Address */
#define FM4_BT5_RT_BASE                           (0x40025240UL) /* BT5 Base Address */
#define FM_BT6_BASE                               (0x40025280UL) /* BT6 Base Address */
#define FM4_BT6_BASE                              (0x40025280UL) /* BT6 Base Address */
#define FM_BT6_PPG_BASE                           (0x40025280UL) /* BT6 Base Address */
#define FM4_BT6_PPG_BASE                          (0x40025280UL) /* BT6 Base Address */
#define FM_BT6_PWC_BASE                           (0x40025280UL) /* BT6 Base Address */
#define FM4_BT6_PWC_BASE                          (0x40025280UL) /* BT6 Base Address */
#define FM_BT6_PWM_BASE                           (0x40025280UL) /* BT6 Base Address */
#define FM4_BT6_PWM_BASE                          (0x40025280UL) /* BT6 Base Address */
#define FM_BT6_RT_BASE                            (0x40025280UL) /* BT6 Base Address */
#define FM4_BT6_RT_BASE                           (0x40025280UL) /* BT6 Base Address */
#define FM_BT7_BASE                               (0x400252C0UL) /* BT7 Base Address */
#define FM4_BT7_BASE                              (0x400252C0UL) /* BT7 Base Address */
#define FM_BT7_PPG_BASE                           (0x400252C0UL) /* BT7 Base Address */
#define FM4_BT7_PPG_BASE                          (0x400252C0UL) /* BT7 Base Address */
#define FM_BT7_PWC_BASE                           (0x400252C0UL) /* BT7 Base Address */
#define FM4_BT7_PWC_BASE                          (0x400252C0UL) /* BT7 Base Address */
#define FM_BT7_PWM_BASE                           (0x400252C0UL) /* BT7 Base Address */
#define FM4_BT7_PWM_BASE                          (0x400252C0UL) /* BT7 Base Address */
#define FM_BT7_RT_BASE                            (0x400252C0UL) /* BT7 Base Address */
#define FM4_BT7_RT_BASE                           (0x400252C0UL) /* BT7 Base Address */
#define FM_BT8_BASE                               (0x40025400UL) /* BT8 Base Address */
#define FM4_BT8_BASE                              (0x40025400UL) /* BT8 Base Address */
#define FM_BT8_PPG_BASE                           (0x40025400UL) /* BT8 Base Address */
#define FM4_BT8_PPG_BASE                          (0x40025400UL) /* BT8 Base Address */
#define FM_BT8_PWC_BASE                           (0x40025400UL) /* BT8 Base Address */
#define FM4_BT8_PWC_BASE                          (0x40025400UL) /* BT8 Base Address */
#define FM_BT8_PWM_BASE                           (0x40025400UL) /* BT8 Base Address */
#define FM4_BT8_PWM_BASE                          (0x40025400UL) /* BT8 Base Address */
#define FM_BT8_RT_BASE                            (0x40025400UL) /* BT8 Base Address */
#define FM4_BT8_RT_BASE                           (0x40025400UL) /* BT8 Base Address */
#define FM_BT9_BASE                               (0x40025440UL) /* BT9 Base Address */
#define FM4_BT9_BASE                              (0x40025440UL) /* BT9 Base Address */
#define FM_BT9_PPG_BASE                           (0x40025440UL) /* BT9 Base Address */
#define FM4_BT9_PPG_BASE                          (0x40025440UL) /* BT9 Base Address */
#define FM_BT9_PWC_BASE                           (0x40025440UL) /* BT9 Base Address */
#define FM4_BT9_PWC_BASE                          (0x40025440UL) /* BT9 Base Address */
#define FM_BT9_PWM_BASE                           (0x40025440UL) /* BT9 Base Address */
#define FM4_BT9_PWM_BASE                          (0x40025440UL) /* BT9 Base Address */
#define FM_BT9_RT_BASE                            (0x40025440UL) /* BT9 Base Address */
#define FM4_BT9_RT_BASE                           (0x40025440UL) /* BT9 Base Address */
#define FM_BTIOSEL03_BASE                         (0x40025100UL) /* BTIOSEL03 Base Address */
#define FM4_BTIOSEL03_BASE                        (0x40025100UL) /* BTIOSEL03 Base Address */
#define FM_BTIOSEL47_BASE                         (0x40025300UL) /* BTIOSEL47 Base Address */
#define FM4_BTIOSEL47_BASE                        (0x40025300UL) /* BTIOSEL47 Base Address */
#define FM_BTIOSEL8B_BASE                         (0x40025500UL) /* BTIOSEL8B Base Address */
#define FM4_BTIOSEL8B_BASE                        (0x40025500UL) /* BTIOSEL8B Base Address */
#define FM_BTIOSELCF_BASE                         (0x40025700UL) /* BTIOSELCF Base Address */
#define FM4_BTIOSELCF_BASE                        (0x40025700UL) /* BTIOSELCF Base Address */
#define FM_CAN0_BASE                              (0x40062000UL) /* CAN0 Base Address */
#define FM4_CAN0_BASE                             (0x40062000UL) /* CAN0 Base Address */
#define FM_CAN1_BASE                              (0x40063000UL) /* CAN1 Base Address */
#define FM4_CAN1_BASE                             (0x40063000UL) /* CAN1 Base Address */
#define FM_CANFD0_BASE                            (0x40070000UL) /* CANFD0 Base Address */
#define FM4_CANFD0_BASE                           (0x40070000UL) /* CANFD0 Base Address */
#define FM_CANPRES_BASE                           (0x40037000UL) /* CANPRES Base Address */
#define FM4_CANPRES_BASE                          (0x40037000UL) /* CANPRES Base Address */
#define FM_CLK_GATING_BASE                        (0x4003C100UL) /* CLK_GATING Base Address */
#define FM4_CLK_GATING_BASE                       (0x4003C100UL) /* CLK_GATING Base Address */
#define FM_CRC_BASE                               (0x40039000UL) /* CRC Base Address */
#define FM4_CRC_BASE                              (0x40039000UL) /* CRC Base Address */
#define FM_CRG_BASE                               (0x40010000UL) /* CRG Base Address */
#define FM4_CRG_BASE                              (0x40010000UL) /* CRG Base Address */
#define FM_CRTRIM_BASE                            (0x4002E000UL) /* CRTRIM Base Address */
#define FM4_CRTRIM_BASE                           (0x4002E000UL) /* CRTRIM Base Address */
#define FM_DAC0_BASE                              (0x40033000UL) /* DAC0 Base Address */
#define FM4_DAC0_BASE                             (0x40033000UL) /* DAC0 Base Address */
#define FM_DAC1_BASE                              (0x40033008UL) /* DAC1 Base Address */
#define FM4_DAC1_BASE                             (0x40033008UL) /* DAC1 Base Address */
#define FM_DMAC_BASE                              (0x40060000UL) /* DMAC Base Address */
#define FM4_DMAC_BASE                             (0x40060000UL) /* DMAC Base Address */
#define FM_DS_BASE                                (0x40035100UL) /* DS Base Address */
#define FM4_DS_BASE                               (0x40035100UL) /* DS Base Address */
#define FM_DSTC_BASE                              (0x40061000UL) /* DSTC Base Address */
#define FM4_DSTC_BASE                             (0x40061000UL) /* DSTC Base Address */
#define FM_DT_BASE                                (0x40015000UL) /* DT Base Address */
#define FM4_DT_BASE                               (0x40015000UL) /* DT Base Address */
#define FM_DUALFLASH_IF_BASE                      (0x40000400UL) /* DUALFLASH_IF Base Address */
#define FM4_DUALFLASH_IF_BASE                     (0x40000400UL) /* DUALFLASH_IF Base Address */
#define FM_ECC_CAPTURE_BASE                       (0x40000300UL) /* ECC_CAPTURE Base Address */
#define FM4_ECC_CAPTURE_BASE                      (0x40000300UL) /* ECC_CAPTURE Base Address */
#define FM_ETHERNET_CONTROL_BASE                  (0x40066000UL) /* ETHERNET_CONTROL Base Address */
#define FM4_ETHERNET_CONTROL_BASE                 (0x40066000UL) /* ETHERNET_CONTROL Base Address */
#define FM_ETHERNET_MAC0_BASE                     (0x40064000UL) /* ETHERNET_MAC0 Base Address */
#define FM4_ETHERNET_MAC0_BASE                    (0x40064000UL) /* ETHERNET_MAC0 Base Address */
#define FM_EXBUS_BASE                             (0x4003F000UL) /* EXBUS Base Address */
#define FM4_EXBUS_BASE                            (0x4003F000UL) /* EXBUS Base Address */
#define FM_EXTI_BASE                              (0x40030000UL) /* EXTI Base Address */
#define FM4_EXTI_BASE                             (0x40030000UL) /* EXTI Base Address */
#define FM_FLASH_IF_BASE                          (0x40000000UL) /* FLASH_IF Base Address */
#define FM4_FLASH_IF_BASE                         (0x40000000UL) /* FLASH_IF Base Address */
#define FM_GPIO_BASE                              (0x4006F000UL) /* GPIO Base Address */
#define FM4_GPIO_BASE                             (0x4006F000UL) /* GPIO Base Address */
#define FM_HSSPI_BASE                             (0xD0000000UL) /* HSSPI Base Address */
#define FM4_HSSPI_BASE                            (0xD0000000UL) /* HSSPI Base Address */
#define FM_HWWDT_BASE                             (0x40011000UL) /* HWWDT Base Address */
#define FM4_HWWDT_BASE                            (0x40011000UL) /* HWWDT Base Address */
#define FM_I2S0_BASE                              (0x4006C000UL) /* I2S0 Base Address */
#define FM4_I2S0_BASE                             (0x4006C000UL) /* I2S0 Base Address */
#define FM_I2SPRE_BASE                            (0x4003D000UL) /* I2SPRE Base Address */
#define FM4_I2SPRE_BASE                           (0x4003D000UL) /* I2SPRE Base Address */
#define FM_INTREQ_BASE                            (0x40031000UL) /* INTREQ Base Address */
#define FM4_INTREQ_BASE                           (0x40031000UL) /* INTREQ Base Address */
#define FM_LSCRP_BASE                             (0x4003C000UL) /* LSCRP Base Address */
#define FM4_LSCRP_BASE                            (0x4003C000UL) /* LSCRP Base Address */
#define FM_LVD_BASE                               (0x40035000UL) /* LVD Base Address */
#define FM4_LVD_BASE                              (0x40035000UL) /* LVD Base Address */
#define FM_MFS0_BASE                              (0x40038000UL) /* MFS0 Base Address */
#define FM4_MFS0_BASE                             (0x40038000UL) /* MFS0 Base Address */
#define FM_MFS0_CSIO_BASE                         (0x40038000UL) /* MFS0 Base Address */
#define FM4_MFS0_CSIO_BASE                        (0x40038000UL) /* MFS0 Base Address */
#define FM_MFS0_I2C_BASE                          (0x40038000UL) /* MFS0 Base Address */
#define FM4_MFS0_I2C_BASE                         (0x40038000UL) /* MFS0 Base Address */
#define FM_MFS0_LIN_BASE                          (0x40038000UL) /* MFS0 Base Address */
#define FM4_MFS0_LIN_BASE                         (0x40038000UL) /* MFS0 Base Address */
#define FM_MFS0_UART_BASE                         (0x40038000UL) /* MFS0 Base Address */
#define FM4_MFS0_UART_BASE                        (0x40038000UL) /* MFS0 Base Address */
#define FM_MFS1_BASE                              (0x40038100UL) /* MFS1 Base Address */
#define FM4_MFS1_BASE                             (0x40038100UL) /* MFS1 Base Address */
#define FM_MFS1_CSIO_BASE                         (0x40038100UL) /* MFS1 Base Address */
#define FM4_MFS1_CSIO_BASE                        (0x40038100UL) /* MFS1 Base Address */
#define FM_MFS1_I2C_BASE                          (0x40038100UL) /* MFS1 Base Address */
#define FM4_MFS1_I2C_BASE                         (0x40038100UL) /* MFS1 Base Address */
#define FM_MFS1_LIN_BASE                          (0x40038100UL) /* MFS1 Base Address */
#define FM4_MFS1_LIN_BASE                         (0x40038100UL) /* MFS1 Base Address */
#define FM_MFS1_UART_BASE                         (0x40038100UL) /* MFS1 Base Address */
#define FM4_MFS1_UART_BASE                        (0x40038100UL) /* MFS1 Base Address */
#define FM_MFS10_BASE                             (0x40038A00UL) /* MFS10 Base Address */
#define FM4_MFS10_BASE                            (0x40038A00UL) /* MFS10 Base Address */
#define FM_MFS10_CSIO_BASE                        (0x40038A00UL) /* MFS10 Base Address */
#define FM4_MFS10_CSIO_BASE                       (0x40038A00UL) /* MFS10 Base Address */
#define FM_MFS10_I2C_BASE                         (0x40038A00UL) /* MFS10 Base Address */
#define FM4_MFS10_I2C_BASE                        (0x40038A00UL) /* MFS10 Base Address */
#define FM_MFS10_LIN_BASE                         (0x40038A00UL) /* MFS10 Base Address */
#define FM4_MFS10_LIN_BASE                        (0x40038A00UL) /* MFS10 Base Address */
#define FM_MFS10_UART_BASE                        (0x40038A00UL) /* MFS10 Base Address */
#define FM4_MFS10_UART_BASE                       (0x40038A00UL) /* MFS10 Base Address */
#define FM_MFS11_BASE                             (0x40038B00UL) /* MFS11 Base Address */
#define FM4_MFS11_BASE                            (0x40038B00UL) /* MFS11 Base Address */
#define FM_MFS11_CSIO_BASE                        (0x40038B00UL) /* MFS11 Base Address */
#define FM4_MFS11_CSIO_BASE                       (0x40038B00UL) /* MFS11 Base Address */
#define FM_MFS11_I2C_BASE                         (0x40038B00UL) /* MFS11 Base Address */
#define FM4_MFS11_I2C_BASE                        (0x40038B00UL) /* MFS11 Base Address */
#define FM_MFS11_LIN_BASE                         (0x40038B00UL) /* MFS11 Base Address */
#define FM4_MFS11_LIN_BASE                        (0x40038B00UL) /* MFS11 Base Address */
#define FM_MFS11_UART_BASE                        (0x40038B00UL) /* MFS11 Base Address */
#define FM4_MFS11_UART_BASE                       (0x40038B00UL) /* MFS11 Base Address */
#define FM_MFS12_BASE                             (0x40038C00UL) /* MFS12 Base Address */
#define FM4_MFS12_BASE                            (0x40038C00UL) /* MFS12 Base Address */
#define FM_MFS12_CSIO_BASE                        (0x40038C00UL) /* MFS12 Base Address */
#define FM4_MFS12_CSIO_BASE                       (0x40038C00UL) /* MFS12 Base Address */
#define FM_MFS12_I2C_BASE                         (0x40038C00UL) /* MFS12 Base Address */
#define FM4_MFS12_I2C_BASE                        (0x40038C00UL) /* MFS12 Base Address */
#define FM_MFS12_LIN_BASE                         (0x40038C00UL) /* MFS12 Base Address */
#define FM4_MFS12_LIN_BASE                        (0x40038C00UL) /* MFS12 Base Address */
#define FM_MFS12_UART_BASE                        (0x40038C00UL) /* MFS12 Base Address */
#define FM4_MFS12_UART_BASE                       (0x40038C00UL) /* MFS12 Base Address */
#define FM_MFS13_BASE                             (0x40038D00UL) /* MFS13 Base Address */
#define FM4_MFS13_BASE                            (0x40038D00UL) /* MFS13 Base Address */
#define FM_MFS13_CSIO_BASE                        (0x40038D00UL) /* MFS13 Base Address */
#define FM4_MFS13_CSIO_BASE                       (0x40038D00UL) /* MFS13 Base Address */
#define FM_MFS13_I2C_BASE                         (0x40038D00UL) /* MFS13 Base Address */
#define FM4_MFS13_I2C_BASE                        (0x40038D00UL) /* MFS13 Base Address */
#define FM_MFS13_LIN_BASE                         (0x40038D00UL) /* MFS13 Base Address */
#define FM4_MFS13_LIN_BASE                        (0x40038D00UL) /* MFS13 Base Address */
#define FM_MFS13_UART_BASE                        (0x40038D00UL) /* MFS13 Base Address */
#define FM4_MFS13_UART_BASE                       (0x40038D00UL) /* MFS13 Base Address */
#define FM_MFS14_BASE                             (0x40038E00UL) /* MFS14 Base Address */
#define FM4_MFS14_BASE                            (0x40038E00UL) /* MFS14 Base Address */
#define FM_MFS14_CSIO_BASE                        (0x40038E00UL) /* MFS14 Base Address */
#define FM4_MFS14_CSIO_BASE                       (0x40038E00UL) /* MFS14 Base Address */
#define FM_MFS14_I2C_BASE                         (0x40038E00UL) /* MFS14 Base Address */
#define FM4_MFS14_I2C_BASE                        (0x40038E00UL) /* MFS14 Base Address */
#define FM_MFS14_LIN_BASE                         (0x40038E00UL) /* MFS14 Base Address */
#define FM4_MFS14_LIN_BASE                        (0x40038E00UL) /* MFS14 Base Address */
#define FM_MFS14_UART_BASE                        (0x40038E00UL) /* MFS14 Base Address */
#define FM4_MFS14_UART_BASE                       (0x40038E00UL) /* MFS14 Base Address */
#define FM_MFS15_BASE                             (0x40038F00UL) /* MFS15 Base Address */
#define FM4_MFS15_BASE                            (0x40038F00UL) /* MFS15 Base Address */
#define FM_MFS15_CSIO_BASE                        (0x40038F00UL) /* MFS15 Base Address */
#define FM4_MFS15_CSIO_BASE                       (0x40038F00UL) /* MFS15 Base Address */
#define FM_MFS15_I2C_BASE                         (0x40038F00UL) /* MFS15 Base Address */
#define FM4_MFS15_I2C_BASE                        (0x40038F00UL) /* MFS15 Base Address */
#define FM_MFS15_LIN_BASE                         (0x40038F00UL) /* MFS15 Base Address */
#define FM4_MFS15_LIN_BASE                        (0x40038F00UL) /* MFS15 Base Address */
#define FM_MFS15_UART_BASE                        (0x40038F00UL) /* MFS15 Base Address */
#define FM4_MFS15_UART_BASE                       (0x40038F00UL) /* MFS15 Base Address */
#define FM_MFS2_BASE                              (0x40038200UL) /* MFS2 Base Address */
#define FM4_MFS2_BASE                             (0x40038200UL) /* MFS2 Base Address */
#define FM_MFS2_CSIO_BASE                         (0x40038200UL) /* MFS2 Base Address */
#define FM4_MFS2_CSIO_BASE                        (0x40038200UL) /* MFS2 Base Address */
#define FM_MFS2_I2C_BASE                          (0x40038200UL) /* MFS2 Base Address */
#define FM4_MFS2_I2C_BASE                         (0x40038200UL) /* MFS2 Base Address */
#define FM_MFS2_LIN_BASE                          (0x40038200UL) /* MFS2 Base Address */
#define FM4_MFS2_LIN_BASE                         (0x40038200UL) /* MFS2 Base Address */
#define FM_MFS2_UART_BASE                         (0x40038200UL) /* MFS2 Base Address */
#define FM4_MFS2_UART_BASE                        (0x40038200UL) /* MFS2 Base Address */
#define FM_MFS3_BASE                              (0x40038300UL) /* MFS3 Base Address */
#define FM4_MFS3_BASE                             (0x40038300UL) /* MFS3 Base Address */
#define FM_MFS3_CSIO_BASE                         (0x40038300UL) /* MFS3 Base Address */
#define FM4_MFS3_CSIO_BASE                        (0x40038300UL) /* MFS3 Base Address */
#define FM_MFS3_I2C_BASE                          (0x40038300UL) /* MFS3 Base Address */
#define FM4_MFS3_I2C_BASE                         (0x40038300UL) /* MFS3 Base Address */
#define FM_MFS3_LIN_BASE                          (0x40038300UL) /* MFS3 Base Address */
#define FM4_MFS3_LIN_BASE                         (0x40038300UL) /* MFS3 Base Address */
#define FM_MFS3_UART_BASE                         (0x40038300UL) /* MFS3 Base Address */
#define FM4_MFS3_UART_BASE                        (0x40038300UL) /* MFS3 Base Address */
#define FM_MFS4_BASE                              (0x40038400UL) /* MFS4 Base Address */
#define FM4_MFS4_BASE                             (0x40038400UL) /* MFS4 Base Address */
#define FM_MFS4_CSIO_BASE                         (0x40038400UL) /* MFS4 Base Address */
#define FM4_MFS4_CSIO_BASE                        (0x40038400UL) /* MFS4 Base Address */
#define FM_MFS4_I2C_BASE                          (0x40038400UL) /* MFS4 Base Address */
#define FM4_MFS4_I2C_BASE                         (0x40038400UL) /* MFS4 Base Address */
#define FM_MFS4_LIN_BASE                          (0x40038400UL) /* MFS4 Base Address */
#define FM4_MFS4_LIN_BASE                         (0x40038400UL) /* MFS4 Base Address */
#define FM_MFS4_UART_BASE                         (0x40038400UL) /* MFS4 Base Address */
#define FM4_MFS4_UART_BASE                        (0x40038400UL) /* MFS4 Base Address */
#define FM_MFS5_BASE                              (0x40038500UL) /* MFS5 Base Address */
#define FM4_MFS5_BASE                             (0x40038500UL) /* MFS5 Base Address */
#define FM_MFS5_CSIO_BASE                         (0x40038500UL) /* MFS5 Base Address */
#define FM4_MFS5_CSIO_BASE                        (0x40038500UL) /* MFS5 Base Address */
#define FM_MFS5_I2C_BASE                          (0x40038500UL) /* MFS5 Base Address */
#define FM4_MFS5_I2C_BASE                         (0x40038500UL) /* MFS5 Base Address */
#define FM_MFS5_LIN_BASE                          (0x40038500UL) /* MFS5 Base Address */
#define FM4_MFS5_LIN_BASE                         (0x40038500UL) /* MFS5 Base Address */
#define FM_MFS5_UART_BASE                         (0x40038500UL) /* MFS5 Base Address */
#define FM4_MFS5_UART_BASE                        (0x40038500UL) /* MFS5 Base Address */
#define FM_MFS6_BASE                              (0x40038600UL) /* MFS6 Base Address */
#define FM4_MFS6_BASE                             (0x40038600UL) /* MFS6 Base Address */
#define FM_MFS6_CSIO_BASE                         (0x40038600UL) /* MFS6 Base Address */
#define FM4_MFS6_CSIO_BASE                        (0x40038600UL) /* MFS6 Base Address */
#define FM_MFS6_I2C_BASE                          (0x40038600UL) /* MFS6 Base Address */
#define FM4_MFS6_I2C_BASE                         (0x40038600UL) /* MFS6 Base Address */
#define FM_MFS6_LIN_BASE                          (0x40038600UL) /* MFS6 Base Address */
#define FM4_MFS6_LIN_BASE                         (0x40038600UL) /* MFS6 Base Address */
#define FM_MFS6_UART_BASE                         (0x40038600UL) /* MFS6 Base Address */
#define FM4_MFS6_UART_BASE                        (0x40038600UL) /* MFS6 Base Address */
#define FM_MFS7_BASE                              (0x40038700UL) /* MFS7 Base Address */
#define FM4_MFS7_BASE                             (0x40038700UL) /* MFS7 Base Address */
#define FM_MFS7_CSIO_BASE                         (0x40038700UL) /* MFS7 Base Address */
#define FM4_MFS7_CSIO_BASE                        (0x40038700UL) /* MFS7 Base Address */
#define FM_MFS7_I2C_BASE                          (0x40038700UL) /* MFS7 Base Address */
#define FM4_MFS7_I2C_BASE                         (0x40038700UL) /* MFS7 Base Address */
#define FM_MFS7_LIN_BASE                          (0x40038700UL) /* MFS7 Base Address */
#define FM4_MFS7_LIN_BASE                         (0x40038700UL) /* MFS7 Base Address */
#define FM_MFS7_UART_BASE                         (0x40038700UL) /* MFS7 Base Address */
#define FM4_MFS7_UART_BASE                        (0x40038700UL) /* MFS7 Base Address */
#define FM_MFS8_BASE                              (0x40038800UL) /* MFS8 Base Address */
#define FM4_MFS8_BASE                             (0x40038800UL) /* MFS8 Base Address */
#define FM_MFS8_CSIO_BASE                         (0x40038800UL) /* MFS8 Base Address */
#define FM4_MFS8_CSIO_BASE                        (0x40038800UL) /* MFS8 Base Address */
#define FM_MFS8_I2C_BASE                          (0x40038800UL) /* MFS8 Base Address */
#define FM4_MFS8_I2C_BASE                         (0x40038800UL) /* MFS8 Base Address */
#define FM_MFS8_LIN_BASE                          (0x40038800UL) /* MFS8 Base Address */
#define FM4_MFS8_LIN_BASE                         (0x40038800UL) /* MFS8 Base Address */
#define FM_MFS8_UART_BASE                         (0x40038800UL) /* MFS8 Base Address */
#define FM4_MFS8_UART_BASE                        (0x40038800UL) /* MFS8 Base Address */
#define FM_MFS9_BASE                              (0x40038900UL) /* MFS9 Base Address */
#define FM4_MFS9_BASE                             (0x40038900UL) /* MFS9 Base Address */
#define FM_MFS9_CSIO_BASE                         (0x40038900UL) /* MFS9 Base Address */
#define FM4_MFS9_CSIO_BASE                        (0x40038900UL) /* MFS9 Base Address */
#define FM_MFS9_I2C_BASE                          (0x40038900UL) /* MFS9 Base Address */
#define FM4_MFS9_I2C_BASE                         (0x40038900UL) /* MFS9 Base Address */
#define FM_MFS9_LIN_BASE                          (0x40038900UL) /* MFS9 Base Address */
#define FM4_MFS9_LIN_BASE                         (0x40038900UL) /* MFS9 Base Address */
#define FM_MFS9_UART_BASE                         (0x40038900UL) /* MFS9 Base Address */
#define FM4_MFS9_UART_BASE                        (0x40038900UL) /* MFS9 Base Address */
#define FM_MFT_PPG_BASE                           (0x40024000UL) /* MFT_PPG Base Address */
#define FM4_MFT_PPG_BASE                          (0x40024000UL) /* MFT_PPG Base Address */
#define FM_MFT0_BASE                              (0x40020000UL) /* MFT0 Base Address */
#define FM4_MFT0_BASE                             (0x40020000UL) /* MFT0 Base Address */
#define FM_MFT0_ADCMP_BASE                        (0x40020000UL) /* MFT0 Base Address */
#define FM4_MFT0_ADCMP_BASE                       (0x40020000UL) /* MFT0 Base Address */
#define FM_MFT0_FRT_BASE                          (0x40020000UL) /* MFT0 Base Address */
#define FM4_MFT0_FRT_BASE                         (0x40020000UL) /* MFT0 Base Address */
#define FM_MFT0_ICU_BASE                          (0x40020000UL) /* MFT0 Base Address */
#define FM4_MFT0_ICU_BASE                         (0x40020000UL) /* MFT0 Base Address */
#define FM_MFT0_OCU_BASE                          (0x40020000UL) /* MFT0 Base Address */
#define FM4_MFT0_OCU_BASE                         (0x40020000UL) /* MFT0 Base Address */
#define FM_MFT0_WFG_BASE                          (0x40020000UL) /* MFT0 Base Address */
#define FM4_MFT0_WFG_BASE                         (0x40020000UL) /* MFT0 Base Address */
#define FM_MFT1_BASE                              (0x40021000UL) /* MFT1 Base Address */
#define FM4_MFT1_BASE                             (0x40021000UL) /* MFT1 Base Address */
#define FM_MFT1_ADCMP_BASE                        (0x40021000UL) /* MFT1 Base Address */
#define FM4_MFT1_ADCMP_BASE                       (0x40021000UL) /* MFT1 Base Address */
#define FM_MFT1_FRT_BASE                          (0x40021000UL) /* MFT1 Base Address */
#define FM4_MFT1_FRT_BASE                         (0x40021000UL) /* MFT1 Base Address */
#define FM_MFT1_ICU_BASE                          (0x40021000UL) /* MFT1 Base Address */
#define FM4_MFT1_ICU_BASE                         (0x40021000UL) /* MFT1 Base Address */
#define FM_MFT1_OCU_BASE                          (0x40021000UL) /* MFT1 Base Address */
#define FM4_MFT1_OCU_BASE                         (0x40021000UL) /* MFT1 Base Address */
#define FM_MFT1_WFG_BASE                          (0x40021000UL) /* MFT1 Base Address */
#define FM4_MFT1_WFG_BASE                         (0x40021000UL) /* MFT1 Base Address */
#define FM_MFT2_BASE                              (0x40022000UL) /* MFT2 Base Address */
#define FM4_MFT2_BASE                             (0x40022000UL) /* MFT2 Base Address */
#define FM_MFT2_ADCMP_BASE                        (0x40022000UL) /* MFT2 Base Address */
#define FM4_MFT2_ADCMP_BASE                       (0x40022000UL) /* MFT2 Base Address */
#define FM_MFT2_FRT_BASE                          (0x40022000UL) /* MFT2 Base Address */
#define FM4_MFT2_FRT_BASE                         (0x40022000UL) /* MFT2 Base Address */
#define FM_MFT2_ICU_BASE                          (0x40022000UL) /* MFT2 Base Address */
#define FM4_MFT2_ICU_BASE                         (0x40022000UL) /* MFT2 Base Address */
#define FM_MFT2_OCU_BASE                          (0x40022000UL) /* MFT2 Base Address */
#define FM4_MFT2_OCU_BASE                         (0x40022000UL) /* MFT2 Base Address */
#define FM_MFT2_WFG_BASE                          (0x40022000UL) /* MFT2 Base Address */
#define FM4_MFT2_WFG_BASE                         (0x40022000UL) /* MFT2 Base Address */
#define FM_PCRC_BASE                              (0x40080000UL) /* PCRC Base Address */
#define FM4_PCRC_BASE                             (0x40080000UL) /* PCRC Base Address */
#define FM_QPRC0_BASE                             (0x40026000UL) /* QPRC0 Base Address */
#define FM4_QPRC0_BASE                            (0x40026000UL) /* QPRC0 Base Address */
#define FM_QPRC0_NF_BASE                          (0x40026100UL) /* QPRC0_NF Base Address */
#define FM4_QPRC0_NF_BASE                         (0x40026100UL) /* QPRC0_NF Base Address */
#define FM_QPRC1_BASE                             (0x40026040UL) /* QPRC1 Base Address */
#define FM4_QPRC1_BASE                            (0x40026040UL) /* QPRC1 Base Address */
#define FM_QPRC1_NF_BASE                          (0x40026110UL) /* QPRC1_NF Base Address */
#define FM4_QPRC1_NF_BASE                         (0x40026110UL) /* QPRC1_NF Base Address */
#define FM_QPRC2_BASE                             (0x40026080UL) /* QPRC2 Base Address */
#define FM4_QPRC2_BASE                            (0x40026080UL) /* QPRC2 Base Address */
#define FM_QPRC2_NF_BASE                          (0x40026120UL) /* QPRC2_NF Base Address */
#define FM4_QPRC2_NF_BASE                         (0x40026120UL) /* QPRC2_NF Base Address */
#define FM_QPRC3_BASE                             (0x400260C0UL) /* QPRC3 Base Address */
#define FM4_QPRC3_BASE                            (0x400260C0UL) /* QPRC3 Base Address */
#define FM_QPRC3_NF_BASE                          (0x40026130UL) /* QPRC3_NF Base Address */
#define FM4_QPRC3_NF_BASE                         (0x40026130UL) /* QPRC3_NF Base Address */
#define FM_RTC_BASE                               (0x4003B100UL) /* RTC Base Address */
#define FM4_RTC_BASE                              (0x4003B100UL) /* RTC Base Address */
#define FM_SBSSR_BASE                             (0x40025F00UL) /* SBSSR Base Address */
#define FM4_SBSSR_BASE                            (0x40025F00UL) /* SBSSR Base Address */
#define FM_SDIF_BASE                              (0x4006E000UL) /* SDIF Base Address */
#define FM4_SDIF_BASE                             (0x4006E000UL) /* SDIF Base Address */
#define FM_SWWDT_BASE                             (0x40012000UL) /* SWWDT Base Address */
#define FM4_SWWDT_BASE                            (0x40012000UL) /* SWWDT Base Address */
#define FM_UNIQUE_ID_BASE                         (0x40000200UL) /* UNIQUE_ID Base Address */
#define FM4_UNIQUE_ID_BASE                        (0x40000200UL) /* UNIQUE_ID Base Address */
#define FM_USB0_BASE                              (0x40040000UL) /* USB0 Base Address */
#define FM4_USB0_BASE                             (0x40040000UL) /* USB0 Base Address */
#define FM_USB1_BASE                              (0x40052100UL) /* USB1 Base Address */
#define FM4_USB1_BASE                             (0x40052100UL) /* USB1 Base Address */
#define FM_USBETHERCLK_BASE                       (0x40036000UL) /* USBETHERCLK Base Address */
#define FM4_USBETHERCLK_BASE                      (0x40036000UL) /* USBETHERCLK Base Address */
#define FM_WC_BASE                                (0x4003A000UL) /* WC Base Address */
#define FM4_WC_BASE                               (0x4003A000UL) /* WC Base Address */
/*******************************************************************************
* Peripheral declaration
*******************************************************************************/
#define FM4_ADC0                                  ((FM_ADC_TypeDef *)FM4_ADC0_BASE)
#define FM_ADC0                                   ((FM_ADC_TypeDef *)FM4_ADC0_BASE)
#define FM4_ADC1                                  ((FM_ADC_TypeDef *)FM4_ADC1_BASE)
#define FM_ADC1                                   ((FM_ADC_TypeDef *)FM4_ADC1_BASE)
#define FM4_ADC2                                  ((FM_ADC_TypeDef *)FM4_ADC2_BASE)
#define FM_ADC2                                   ((FM_ADC_TypeDef *)FM4_ADC2_BASE)
#define FM4_BT0                                   ((FM_BT_TypeDef *)FM4_BT0_BASE)
#define FM_BT0                                    ((FM_BT_TypeDef *)FM4_BT0_BASE)
#define FM4_BT0_PPG                               ((FM_BT_PPG_TypeDef *)FM4_BT0_BASE)
#define FM_BT0_PPG                                ((FM_BT_PPG_TypeDef *)FM4_BT0_BASE)
#define FM4_BT0_PWC                               ((FM_BT_PWC_TypeDef *)FM4_BT0_BASE)
#define FM_BT0_PWC                                ((FM_BT_PWC_TypeDef *)FM4_BT0_BASE)
#define FM4_BT0_PWM                               ((FM_BT_PWM_TypeDef *)FM4_BT0_BASE)
#define FM_BT0_PWM                                ((FM_BT_PWM_TypeDef *)FM4_BT0_BASE)
#define FM4_BT0_RT                                ((FM_BT_RT_TypeDef *)FM4_BT0_BASE)
#define FM_BT0_RT                                 ((FM_BT_RT_TypeDef *)FM4_BT0_BASE)
#define FM4_BT1                                   ((FM_BT_TypeDef *)FM4_BT1_BASE)
#define FM_BT1                                    ((FM_BT_TypeDef *)FM4_BT1_BASE)
#define FM4_BT1_PPG                               ((FM_BT_PPG_TypeDef *)FM4_BT1_BASE)
#define FM_BT1_PPG                                ((FM_BT_PPG_TypeDef *)FM4_BT1_BASE)
#define FM4_BT1_PWC                               ((FM_BT_PWC_TypeDef *)FM4_BT1_BASE)
#define FM_BT1_PWC                                ((FM_BT_PWC_TypeDef *)FM4_BT1_BASE)
#define FM4_BT1_PWM                               ((FM_BT_PWM_TypeDef *)FM4_BT1_BASE)
#define FM_BT1_PWM                                ((FM_BT_PWM_TypeDef *)FM4_BT1_BASE)
#define FM4_BT1_RT                                ((FM_BT_RT_TypeDef *)FM4_BT1_BASE)
#define FM_BT1_RT                                 ((FM_BT_RT_TypeDef *)FM4_BT1_BASE)
#define FM4_BT10                                  ((FM_BT_TypeDef *)FM4_BT10_BASE)
#define FM_BT10                                   ((FM_BT_TypeDef *)FM4_BT10_BASE)
#define FM4_BT10_PPG                              ((FM_BT_PPG_TypeDef *)FM4_BT10_BASE)
#define FM_BT10_PPG                               ((FM_BT_PPG_TypeDef *)FM4_BT10_BASE)
#define FM4_BT10_PWC                              ((FM_BT_PWC_TypeDef *)FM4_BT10_BASE)
#define FM_BT10_PWC                               ((FM_BT_PWC_TypeDef *)FM4_BT10_BASE)
#define FM4_BT10_PWM                              ((FM_BT_PWM_TypeDef *)FM4_BT10_BASE)
#define FM_BT10_PWM                               ((FM_BT_PWM_TypeDef *)FM4_BT10_BASE)
#define FM4_BT10_RT                               ((FM_BT_RT_TypeDef *)FM4_BT10_BASE)
#define FM_BT10_RT                                ((FM_BT_RT_TypeDef *)FM4_BT10_BASE)
#define FM4_BT11                                  ((FM_BT_TypeDef *)FM4_BT11_BASE)
#define FM_BT11                                   ((FM_BT_TypeDef *)FM4_BT11_BASE)
#define FM4_BT11_PPG                              ((FM_BT_PPG_TypeDef *)FM4_BT11_BASE)
#define FM_BT11_PPG                               ((FM_BT_PPG_TypeDef *)FM4_BT11_BASE)
#define FM4_BT11_PWC                              ((FM_BT_PWC_TypeDef *)FM4_BT11_BASE)
#define FM_BT11_PWC                               ((FM_BT_PWC_TypeDef *)FM4_BT11_BASE)
#define FM4_BT11_PWM                              ((FM_BT_PWM_TypeDef *)FM4_BT11_BASE)
#define FM_BT11_PWM                               ((FM_BT_PWM_TypeDef *)FM4_BT11_BASE)
#define FM4_BT11_RT                               ((FM_BT_RT_TypeDef *)FM4_BT11_BASE)
#define FM_BT11_RT                                ((FM_BT_RT_TypeDef *)FM4_BT11_BASE)
#define FM4_BT12                                  ((FM_BT_TypeDef *)FM4_BT12_BASE)
#define FM_BT12                                   ((FM_BT_TypeDef *)FM4_BT12_BASE)
#define FM4_BT12_PPG                              ((FM_BT_PPG_TypeDef *)FM4_BT12_BASE)
#define FM_BT12_PPG                               ((FM_BT_PPG_TypeDef *)FM4_BT12_BASE)
#define FM4_BT12_PWC                              ((FM_BT_PWC_TypeDef *)FM4_BT12_BASE)
#define FM_BT12_PWC                               ((FM_BT_PWC_TypeDef *)FM4_BT12_BASE)
#define FM4_BT12_PWM                              ((FM_BT_PWM_TypeDef *)FM4_BT12_BASE)
#define FM_BT12_PWM                               ((FM_BT_PWM_TypeDef *)FM4_BT12_BASE)
#define FM4_BT12_RT                               ((FM_BT_RT_TypeDef *)FM4_BT12_BASE)
#define FM_BT12_RT                                ((FM_BT_RT_TypeDef *)FM4_BT12_BASE)
#define FM4_BT13                                  ((FM_BT_TypeDef *)FM4_BT13_BASE)
#define FM_BT13                                   ((FM_BT_TypeDef *)FM4_BT13_BASE)
#define FM4_BT13_PPG                              ((FM_BT_PPG_TypeDef *)FM4_BT13_BASE)
#define FM_BT13_PPG                               ((FM_BT_PPG_TypeDef *)FM4_BT13_BASE)
#define FM4_BT13_PWC                              ((FM_BT_PWC_TypeDef *)FM4_BT13_BASE)
#define FM_BT13_PWC                               ((FM_BT_PWC_TypeDef *)FM4_BT13_BASE)
#define FM4_BT13_PWM                              ((FM_BT_PWM_TypeDef *)FM4_BT13_BASE)
#define FM_BT13_PWM                               ((FM_BT_PWM_TypeDef *)FM4_BT13_BASE)
#define FM4_BT13_RT                               ((FM_BT_RT_TypeDef *)FM4_BT13_BASE)
#define FM_BT13_RT                                ((FM_BT_RT_TypeDef *)FM4_BT13_BASE)
#define FM4_BT14                                  ((FM_BT_TypeDef *)FM4_BT14_BASE)
#define FM_BT14                                   ((FM_BT_TypeDef *)FM4_BT14_BASE)
#define FM4_BT14_PPG                              ((FM_BT_PPG_TypeDef *)FM4_BT14_BASE)
#define FM_BT14_PPG                               ((FM_BT_PPG_TypeDef *)FM4_BT14_BASE)
#define FM4_BT14_PWC                              ((FM_BT_PWC_TypeDef *)FM4_BT14_BASE)
#define FM_BT14_PWC                               ((FM_BT_PWC_TypeDef *)FM4_BT14_BASE)
#define FM4_BT14_PWM                              ((FM_BT_PWM_TypeDef *)FM4_BT14_BASE)
#define FM_BT14_PWM                               ((FM_BT_PWM_TypeDef *)FM4_BT14_BASE)
#define FM4_BT14_RT                               ((FM_BT_RT_TypeDef *)FM4_BT14_BASE)
#define FM_BT14_RT                                ((FM_BT_RT_TypeDef *)FM4_BT14_BASE)
#define FM4_BT15                                  ((FM_BT_TypeDef *)FM4_BT15_BASE)
#define FM_BT15                                   ((FM_BT_TypeDef *)FM4_BT15_BASE)
#define FM4_BT15_PPG                              ((FM_BT_PPG_TypeDef *)FM4_BT15_BASE)
#define FM_BT15_PPG                               ((FM_BT_PPG_TypeDef *)FM4_BT15_BASE)
#define FM4_BT15_PWC                              ((FM_BT_PWC_TypeDef *)FM4_BT15_BASE)
#define FM_BT15_PWC                               ((FM_BT_PWC_TypeDef *)FM4_BT15_BASE)
#define FM4_BT15_PWM                              ((FM_BT_PWM_TypeDef *)FM4_BT15_BASE)
#define FM_BT15_PWM                               ((FM_BT_PWM_TypeDef *)FM4_BT15_BASE)
#define FM4_BT15_RT                               ((FM_BT_RT_TypeDef *)FM4_BT15_BASE)
#define FM_BT15_RT                                ((FM_BT_RT_TypeDef *)FM4_BT15_BASE)
#define FM4_BT2                                   ((FM_BT_TypeDef *)FM4_BT2_BASE)
#define FM_BT2                                    ((FM_BT_TypeDef *)FM4_BT2_BASE)
#define FM4_BT2_PPG                               ((FM_BT_PPG_TypeDef *)FM4_BT2_BASE)
#define FM_BT2_PPG                                ((FM_BT_PPG_TypeDef *)FM4_BT2_BASE)
#define FM4_BT2_PWC                               ((FM_BT_PWC_TypeDef *)FM4_BT2_BASE)
#define FM_BT2_PWC                                ((FM_BT_PWC_TypeDef *)FM4_BT2_BASE)
#define FM4_BT2_PWM                               ((FM_BT_PWM_TypeDef *)FM4_BT2_BASE)
#define FM_BT2_PWM                                ((FM_BT_PWM_TypeDef *)FM4_BT2_BASE)
#define FM4_BT2_RT                                ((FM_BT_RT_TypeDef *)FM4_BT2_BASE)
#define FM_BT2_RT                                 ((FM_BT_RT_TypeDef *)FM4_BT2_BASE)
#define FM4_BT3                                   ((FM_BT_TypeDef *)FM4_BT3_BASE)
#define FM_BT3                                    ((FM_BT_TypeDef *)FM4_BT3_BASE)
#define FM4_BT3_PPG                               ((FM_BT_PPG_TypeDef *)FM4_BT3_BASE)
#define FM_BT3_PPG                                ((FM_BT_PPG_TypeDef *)FM4_BT3_BASE)
#define FM4_BT3_PWC                               ((FM_BT_PWC_TypeDef *)FM4_BT3_BASE)
#define FM_BT3_PWC                                ((FM_BT_PWC_TypeDef *)FM4_BT3_BASE)
#define FM4_BT3_PWM                               ((FM_BT_PWM_TypeDef *)FM4_BT3_BASE)
#define FM_BT3_PWM                                ((FM_BT_PWM_TypeDef *)FM4_BT3_BASE)
#define FM4_BT3_RT                                ((FM_BT_RT_TypeDef *)FM4_BT3_BASE)
#define FM_BT3_RT                                 ((FM_BT_RT_TypeDef *)FM4_BT3_BASE)
#define FM4_BT4                                   ((FM_BT_TypeDef *)FM4_BT4_BASE)
#define FM_BT4                                    ((FM_BT_TypeDef *)FM4_BT4_BASE)
#define FM4_BT4_PPG                               ((FM_BT_PPG_TypeDef *)FM4_BT4_BASE)
#define FM_BT4_PPG                                ((FM_BT_PPG_TypeDef *)FM4_BT4_BASE)
#define FM4_BT4_PWC                               ((FM_BT_PWC_TypeDef *)FM4_BT4_BASE)
#define FM_BT4_PWC                                ((FM_BT_PWC_TypeDef *)FM4_BT4_BASE)
#define FM4_BT4_PWM                               ((FM_BT_PWM_TypeDef *)FM4_BT4_BASE)
#define FM_BT4_PWM                                ((FM_BT_PWM_TypeDef *)FM4_BT4_BASE)
#define FM4_BT4_RT                                ((FM_BT_RT_TypeDef *)FM4_BT4_BASE)
#define FM_BT4_RT                                 ((FM_BT_RT_TypeDef *)FM4_BT4_BASE)
#define FM4_BT5                                   ((FM_BT_TypeDef *)FM4_BT5_BASE)
#define FM_BT5                                    ((FM_BT_TypeDef *)FM4_BT5_BASE)
#define FM4_BT5_PPG                               ((FM_BT_PPG_TypeDef *)FM4_BT5_BASE)
#define FM_BT5_PPG                                ((FM_BT_PPG_TypeDef *)FM4_BT5_BASE)
#define FM4_BT5_PWC                               ((FM_BT_PWC_TypeDef *)FM4_BT5_BASE)
#define FM_BT5_PWC                                ((FM_BT_PWC_TypeDef *)FM4_BT5_BASE)
#define FM4_BT5_PWM                               ((FM_BT_PWM_TypeDef *)FM4_BT5_BASE)
#define FM_BT5_PWM                                ((FM_BT_PWM_TypeDef *)FM4_BT5_BASE)
#define FM4_BT5_RT                                ((FM_BT_RT_TypeDef *)FM4_BT5_BASE)
#define FM_BT5_RT                                 ((FM_BT_RT_TypeDef *)FM4_BT5_BASE)
#define FM4_BT6                                   ((FM_BT_TypeDef *)FM4_BT6_BASE)
#define FM_BT6                                    ((FM_BT_TypeDef *)FM4_BT6_BASE)
#define FM4_BT6_PPG                               ((FM_BT_PPG_TypeDef *)FM4_BT6_BASE)
#define FM_BT6_PPG                                ((FM_BT_PPG_TypeDef *)FM4_BT6_BASE)
#define FM4_BT6_PWC                               ((FM_BT_PWC_TypeDef *)FM4_BT6_BASE)
#define FM_BT6_PWC                                ((FM_BT_PWC_TypeDef *)FM4_BT6_BASE)
#define FM4_BT6_PWM                               ((FM_BT_PWM_TypeDef *)FM4_BT6_BASE)
#define FM_BT6_PWM                                ((FM_BT_PWM_TypeDef *)FM4_BT6_BASE)
#define FM4_BT6_RT                                ((FM_BT_RT_TypeDef *)FM4_BT6_BASE)
#define FM_BT6_RT                                 ((FM_BT_RT_TypeDef *)FM4_BT6_BASE)
#define FM4_BT7                                   ((FM_BT_TypeDef *)FM4_BT7_BASE)
#define FM_BT7                                    ((FM_BT_TypeDef *)FM4_BT7_BASE)
#define FM4_BT7_PPG                               ((FM_BT_PPG_TypeDef *)FM4_BT7_BASE)
#define FM_BT7_PPG                                ((FM_BT_PPG_TypeDef *)FM4_BT7_BASE)
#define FM4_BT7_PWC                               ((FM_BT_PWC_TypeDef *)FM4_BT7_BASE)
#define FM_BT7_PWC                                ((FM_BT_PWC_TypeDef *)FM4_BT7_BASE)
#define FM4_BT7_PWM                               ((FM_BT_PWM_TypeDef *)FM4_BT7_BASE)
#define FM_BT7_PWM                                ((FM_BT_PWM_TypeDef *)FM4_BT7_BASE)
#define FM4_BT7_RT                                ((FM_BT_RT_TypeDef *)FM4_BT7_BASE)
#define FM_BT7_RT                                 ((FM_BT_RT_TypeDef *)FM4_BT7_BASE)
#define FM4_BT8                                   ((FM_BT_TypeDef *)FM4_BT8_BASE)
#define FM_BT8                                    ((FM_BT_TypeDef *)FM4_BT8_BASE)
#define FM4_BT8_PPG                               ((FM_BT_PPG_TypeDef *)FM4_BT8_BASE)
#define FM_BT8_PPG                                ((FM_BT_PPG_TypeDef *)FM4_BT8_BASE)
#define FM4_BT8_PWC                               ((FM_BT_PWC_TypeDef *)FM4_BT8_BASE)
#define FM_BT8_PWC                                ((FM_BT_PWC_TypeDef *)FM4_BT8_BASE)
#define FM4_BT8_PWM                               ((FM_BT_PWM_TypeDef *)FM4_BT8_BASE)
#define FM_BT8_PWM                                ((FM_BT_PWM_TypeDef *)FM4_BT8_BASE)
#define FM4_BT8_RT                                ((FM_BT_RT_TypeDef *)FM4_BT8_BASE)
#define FM_BT8_RT                                 ((FM_BT_RT_TypeDef *)FM4_BT8_BASE)
#define FM4_BT9                                   ((FM_BT_TypeDef *)FM4_BT9_BASE)
#define FM_BT9                                    ((FM_BT_TypeDef *)FM4_BT9_BASE)
#define FM4_BT9_PPG                               ((FM_BT_PPG_TypeDef *)FM4_BT9_BASE)
#define FM_BT9_PPG                                ((FM_BT_PPG_TypeDef *)FM4_BT9_BASE)
#define FM4_BT9_PWC                               ((FM_BT_PWC_TypeDef *)FM4_BT9_BASE)
#define FM_BT9_PWC                                ((FM_BT_PWC_TypeDef *)FM4_BT9_BASE)
#define FM4_BT9_PWM                               ((FM_BT_PWM_TypeDef *)FM4_BT9_BASE)
#define FM_BT9_PWM                                ((FM_BT_PWM_TypeDef *)FM4_BT9_BASE)
#define FM4_BT9_RT                                ((FM_BT_RT_TypeDef *)FM4_BT9_BASE)
#define FM_BT9_RT                                 ((FM_BT_RT_TypeDef *)FM4_BT9_BASE)
#define FM4_BTIOSEL03                             ((FM_BTIOSEL03_TypeDef *)FM4_BTIOSEL03_BASE)
#define FM_BTIOSEL03                              ((FM_BTIOSEL03_TypeDef *)FM4_BTIOSEL03_BASE)
#define FM4_BTIOSEL47                             ((FM_BTIOSEL47_TypeDef *)FM4_BTIOSEL47_BASE)
#define FM_BTIOSEL47                              ((FM_BTIOSEL47_TypeDef *)FM4_BTIOSEL47_BASE)
#define FM4_BTIOSEL8B                             ((FM_BTIOSEL8B_TypeDef *)FM4_BTIOSEL8B_BASE)
#define FM_BTIOSEL8B                              ((FM_BTIOSEL8B_TypeDef *)FM4_BTIOSEL8B_BASE)
#define FM4_BTIOSELCF                             ((FM_BTIOSELCF_TypeDef *)FM4_BTIOSELCF_BASE)
#define FM_BTIOSELCF                              ((FM_BTIOSELCF_TypeDef *)FM4_BTIOSELCF_BASE)
#define FM4_CAN0                                  ((FM_CAN_TypeDef *)FM4_CAN0_BASE)
#define FM_CAN0                                   ((FM_CAN_TypeDef *)FM4_CAN0_BASE)
#define FM4_CAN1                                  ((FM_CAN_TypeDef *)FM4_CAN1_BASE)
#define FM_CAN1                                   ((FM_CAN_TypeDef *)FM4_CAN1_BASE)
#define FM4_CANFD0                                ((FM_CANFD_TypeDef *)FM4_CANFD0_BASE)
#define FM_CANFD0                                 ((FM_CANFD_TypeDef *)FM4_CANFD0_BASE)
#define FM4_CANPRES                               ((FM_CANPRES_TypeDef *)FM4_CANPRES_BASE)
#define FM_CANPRES                                ((FM_CANPRES_TypeDef *)FM4_CANPRES_BASE)
#define FM4_CLK_GATING                            ((FM_CLK_GATING_TypeDef *)FM4_CLK_GATING_BASE)
#define FM_CLK_GATING                             ((FM_CLK_GATING_TypeDef *)FM4_CLK_GATING_BASE)
#define FM4_CRC                                   ((FM_CRC_TypeDef *)FM4_CRC_BASE)
#define FM_CRC                                    ((FM_CRC_TypeDef *)FM4_CRC_BASE)
#define FM4_CRG                                   ((FM_CRG_TypeDef *)FM4_CRG_BASE)
#define FM_CRG                                    ((FM_CRG_TypeDef *)FM4_CRG_BASE)
#define FM4_CRTRIM                                ((FM_CRTRIM_TypeDef *)FM4_CRTRIM_BASE)
#define FM_CRTRIM                                 ((FM_CRTRIM_TypeDef *)FM4_CRTRIM_BASE)
#define FM4_DAC0                                  ((FM_DAC_TypeDef *)FM4_DAC0_BASE)
#define FM_DAC0                                   ((FM_DAC_TypeDef *)FM4_DAC0_BASE)
#define FM4_DAC1                                  ((FM_DAC_TypeDef *)FM4_DAC1_BASE)
#define FM_DAC1                                   ((FM_DAC_TypeDef *)FM4_DAC1_BASE)
#define FM4_DMAC                                  ((FM_DMAC_TypeDef *)FM4_DMAC_BASE)
#define FM_DMAC                                   ((FM_DMAC_TypeDef *)FM4_DMAC_BASE)
#define FM4_DS                                    ((FM_DS_TypeDef *)FM4_DS_BASE)
#define FM_DS                                     ((FM_DS_TypeDef *)FM4_DS_BASE)
#define FM4_DSTC                                  ((FM_DSTC_TypeDef *)FM4_DSTC_BASE)
#define FM_DSTC                                   ((FM_DSTC_TypeDef *)FM4_DSTC_BASE)
#define FM4_DT                                    ((FM_DT_TypeDef *)FM4_DT_BASE)
#define FM_DT                                     ((FM_DT_TypeDef *)FM4_DT_BASE)
#define FM4_DUALFLASH_IF                          ((FM_DUALFLASH_IF_TypeDef *)FM4_DUALFLASH_IF_BASE)
#define FM_DUALFLASH_IF                           ((FM_DUALFLASH_IF_TypeDef *)FM4_DUALFLASH_IF_BASE)
#define FM4_ECC_CAPTURE                           ((FM_ECC_CAPTURE_TypeDef *)FM4_ECC_CAPTURE_BASE)
#define FM_ECC_CAPTURE                            ((FM_ECC_CAPTURE_TypeDef *)FM4_ECC_CAPTURE_BASE)
#define FM4_ETHERNET_CONTROL                      ((FM_ETHERNET_CONTROL_TypeDef *)FM4_ETHERNET_CONTROL_BASE)
#define FM_ETHERNET_CONTROL                       ((FM_ETHERNET_CONTROL_TypeDef *)FM4_ETHERNET_CONTROL_BASE)
#define FM4_ETHERNET_MAC0                         ((FM_ETHERNET_MAC_TypeDef *)FM4_ETHERNET_MAC0_BASE)
#define FM_ETHERNET_MAC0                          ((FM_ETHERNET_MAC_TypeDef *)FM4_ETHERNET_MAC0_BASE)
#define FM4_EXBUS                                 ((FM_EXBUS_TypeDef *)FM4_EXBUS_BASE)
#define FM_EXBUS                                  ((FM_EXBUS_TypeDef *)FM4_EXBUS_BASE)
#define FM4_EXTI                                  ((FM_EXTI_TypeDef *)FM4_EXTI_BASE)
#define FM_EXTI                                   ((FM_EXTI_TypeDef *)FM4_EXTI_BASE)
#define FM4_FLASH_IF                              ((FM_FLASH_IF_TypeDef *)FM4_FLASH_IF_BASE)
#define FM_FLASH_IF                               ((FM_FLASH_IF_TypeDef *)FM4_FLASH_IF_BASE)
#define FM4_GPIO                                  ((FM_GPIO_TypeDef *)FM4_GPIO_BASE)
#define FM_GPIO                                   ((FM_GPIO_TypeDef *)FM4_GPIO_BASE)
#define FM4_HSSPI                                 ((FM_HSSPI_TypeDef *)FM4_HSSPI_BASE)
#define FM_HSSPI                                  ((FM_HSSPI_TypeDef *)FM4_HSSPI_BASE)
#define FM4_HWWDT                                 ((FM_HWWDT_TypeDef *)FM4_HWWDT_BASE)
#define FM_HWWDT                                  ((FM_HWWDT_TypeDef *)FM4_HWWDT_BASE)
#define FM4_I2S0                                  ((FM_I2S_TypeDef *)FM4_I2S0_BASE)
#define FM_I2S0                                   ((FM_I2S_TypeDef *)FM4_I2S0_BASE)
#define FM4_I2SPRE                                ((FM_I2SPRE_TypeDef *)FM4_I2SPRE_BASE)
#define FM_I2SPRE                                 ((FM_I2SPRE_TypeDef *)FM4_I2SPRE_BASE)
#define FM4_INTREQ                                ((FM_INTREQ_TypeDef *)FM4_INTREQ_BASE)
#define FM_INTREQ                                 ((FM_INTREQ_TypeDef *)FM4_INTREQ_BASE)
#define FM4_LSCRP                                 ((FM_LSCRP_TypeDef *)FM4_LSCRP_BASE)
#define FM_LSCRP                                  ((FM_LSCRP_TypeDef *)FM4_LSCRP_BASE)
#define FM4_LVD                                   ((FM_LVD_TypeDef *)FM4_LVD_BASE)
#define FM_LVD                                    ((FM_LVD_TypeDef *)FM4_LVD_BASE)
#define FM4_MFS0                                  ((FM_MFS_TypeDef *)FM4_MFS0_BASE)
#define FM_MFS0                                   ((FM_MFS_TypeDef *)FM4_MFS0_BASE)
#define FM4_MFS0_CSIO                             ((FM_MFS_CSIO_TypeDef *)FM4_MFS0_BASE)
#define FM_MFS0_CSIO                              ((FM_MFS_CSIO_TypeDef *)FM4_MFS0_BASE)
#define FM4_MFS0_I2C                              ((FM_MFS_I2C_TypeDef *)FM4_MFS0_BASE)
#define FM_MFS0_I2C                               ((FM_MFS_I2C_TypeDef *)FM4_MFS0_BASE)
#define FM4_MFS0_LIN                              ((FM_MFS_LIN_TypeDef *)FM4_MFS0_BASE)
#define FM_MFS0_LIN                               ((FM_MFS_LIN_TypeDef *)FM4_MFS0_BASE)
#define FM4_MFS0_UART                             ((FM_MFS_UART_TypeDef *)FM4_MFS0_BASE)
#define FM_MFS0_UART                              ((FM_MFS_UART_TypeDef *)FM4_MFS0_BASE)
#define FM4_MFS1                                  ((FM_MFS_TypeDef *)FM4_MFS1_BASE)
#define FM_MFS1                                   ((FM_MFS_TypeDef *)FM4_MFS1_BASE)
#define FM4_MFS1_CSIO                             ((FM_MFS_CSIO_TypeDef *)FM4_MFS1_BASE)
#define FM_MFS1_CSIO                              ((FM_MFS_CSIO_TypeDef *)FM4_MFS1_BASE)
#define FM4_MFS1_I2C                              ((FM_MFS_I2C_TypeDef *)FM4_MFS1_BASE)
#define FM_MFS1_I2C                               ((FM_MFS_I2C_TypeDef *)FM4_MFS1_BASE)
#define FM4_MFS1_LIN                              ((FM_MFS_LIN_TypeDef *)FM4_MFS1_BASE)
#define FM_MFS1_LIN                               ((FM_MFS_LIN_TypeDef *)FM4_MFS1_BASE)
#define FM4_MFS1_UART                             ((FM_MFS_UART_TypeDef *)FM4_MFS1_BASE)
#define FM_MFS1_UART                              ((FM_MFS_UART_TypeDef *)FM4_MFS1_BASE)
#define FM4_MFS10                                 ((FM_MFS_TypeDef *)FM4_MFS10_BASE)
#define FM_MFS10                                  ((FM_MFS_TypeDef *)FM4_MFS10_BASE)
#define FM4_MFS10_CSIO                            ((FM_MFS_CSIO_TypeDef *)FM4_MFS10_BASE)
#define FM_MFS10_CSIO                             ((FM_MFS_CSIO_TypeDef *)FM4_MFS10_BASE)
#define FM4_MFS10_I2C                             ((FM_MFS_I2C_TypeDef *)FM4_MFS10_BASE)
#define FM_MFS10_I2C                              ((FM_MFS_I2C_TypeDef *)FM4_MFS10_BASE)
#define FM4_MFS10_LIN                             ((FM_MFS_LIN_TypeDef *)FM4_MFS10_BASE)
#define FM_MFS10_LIN                              ((FM_MFS_LIN_TypeDef *)FM4_MFS10_BASE)
#define FM4_MFS10_UART                            ((FM_MFS_UART_TypeDef *)FM4_MFS10_BASE)
#define FM_MFS10_UART                             ((FM_MFS_UART_TypeDef *)FM4_MFS10_BASE)
#define FM4_MFS11                                 ((FM_MFS_TypeDef *)FM4_MFS11_BASE)
#define FM_MFS11                                  ((FM_MFS_TypeDef *)FM4_MFS11_BASE)
#define FM4_MFS11_CSIO                            ((FM_MFS_CSIO_TypeDef *)FM4_MFS11_BASE)
#define FM_MFS11_CSIO                             ((FM_MFS_CSIO_TypeDef *)FM4_MFS11_BASE)
#define FM4_MFS11_I2C                             ((FM_MFS_I2C_TypeDef *)FM4_MFS11_BASE)
#define FM_MFS11_I2C                              ((FM_MFS_I2C_TypeDef *)FM4_MFS11_BASE)
#define FM4_MFS11_LIN                             ((FM_MFS_LIN_TypeDef *)FM4_MFS11_BASE)
#define FM_MFS11_LIN                              ((FM_MFS_LIN_TypeDef *)FM4_MFS11_BASE)
#define FM4_MFS11_UART                            ((FM_MFS_UART_TypeDef *)FM4_MFS11_BASE)
#define FM_MFS11_UART                             ((FM_MFS_UART_TypeDef *)FM4_MFS11_BASE)
#define FM4_MFS12                                 ((FM_MFS_TypeDef *)FM4_MFS12_BASE)
#define FM_MFS12                                  ((FM_MFS_TypeDef *)FM4_MFS12_BASE)
#define FM4_MFS12_CSIO                            ((FM_MFS_CSIO_TypeDef *)FM4_MFS12_BASE)
#define FM_MFS12_CSIO                             ((FM_MFS_CSIO_TypeDef *)FM4_MFS12_BASE)
#define FM4_MFS12_I2C                             ((FM_MFS_I2C_TypeDef *)FM4_MFS12_BASE)
#define FM_MFS12_I2C                              ((FM_MFS_I2C_TypeDef *)FM4_MFS12_BASE)
#define FM4_MFS12_LIN                             ((FM_MFS_LIN_TypeDef *)FM4_MFS12_BASE)
#define FM_MFS12_LIN                              ((FM_MFS_LIN_TypeDef *)FM4_MFS12_BASE)
#define FM4_MFS12_UART                            ((FM_MFS_UART_TypeDef *)FM4_MFS12_BASE)
#define FM_MFS12_UART                             ((FM_MFS_UART_TypeDef *)FM4_MFS12_BASE)
#define FM4_MFS13                                 ((FM_MFS_TypeDef *)FM4_MFS13_BASE)
#define FM_MFS13                                  ((FM_MFS_TypeDef *)FM4_MFS13_BASE)
#define FM4_MFS13_CSIO                            ((FM_MFS_CSIO_TypeDef *)FM4_MFS13_BASE)
#define FM_MFS13_CSIO                             ((FM_MFS_CSIO_TypeDef *)FM4_MFS13_BASE)
#define FM4_MFS13_I2C                             ((FM_MFS_I2C_TypeDef *)FM4_MFS13_BASE)
#define FM_MFS13_I2C                              ((FM_MFS_I2C_TypeDef *)FM4_MFS13_BASE)
#define FM4_MFS13_LIN                             ((FM_MFS_LIN_TypeDef *)FM4_MFS13_BASE)
#define FM_MFS13_LIN                              ((FM_MFS_LIN_TypeDef *)FM4_MFS13_BASE)
#define FM4_MFS13_UART                            ((FM_MFS_UART_TypeDef *)FM4_MFS13_BASE)
#define FM_MFS13_UART                             ((FM_MFS_UART_TypeDef *)FM4_MFS13_BASE)
#define FM4_MFS14                                 ((FM_MFS_TypeDef *)FM4_MFS14_BASE)
#define FM_MFS14                                  ((FM_MFS_TypeDef *)FM4_MFS14_BASE)
#define FM4_MFS14_CSIO                            ((FM_MFS_CSIO_TypeDef *)FM4_MFS14_BASE)
#define FM_MFS14_CSIO                             ((FM_MFS_CSIO_TypeDef *)FM4_MFS14_BASE)
#define FM4_MFS14_I2C                             ((FM_MFS_I2C_TypeDef *)FM4_MFS14_BASE)
#define FM_MFS14_I2C                              ((FM_MFS_I2C_TypeDef *)FM4_MFS14_BASE)
#define FM4_MFS14_LIN                             ((FM_MFS_LIN_TypeDef *)FM4_MFS14_BASE)
#define FM_MFS14_LIN                              ((FM_MFS_LIN_TypeDef *)FM4_MFS14_BASE)
#define FM4_MFS14_UART                            ((FM_MFS_UART_TypeDef *)FM4_MFS14_BASE)
#define FM_MFS14_UART                             ((FM_MFS_UART_TypeDef *)FM4_MFS14_BASE)
#define FM4_MFS15                                 ((FM_MFS_TypeDef *)FM4_MFS15_BASE)
#define FM_MFS15                                  ((FM_MFS_TypeDef *)FM4_MFS15_BASE)
#define FM4_MFS15_CSIO                            ((FM_MFS_CSIO_TypeDef *)FM4_MFS15_BASE)
#define FM_MFS15_CSIO                             ((FM_MFS_CSIO_TypeDef *)FM4_MFS15_BASE)
#define FM4_MFS15_I2C                             ((FM_MFS_I2C_TypeDef *)FM4_MFS15_BASE)
#define FM_MFS15_I2C                              ((FM_MFS_I2C_TypeDef *)FM4_MFS15_BASE)
#define FM4_MFS15_LIN                             ((FM_MFS_LIN_TypeDef *)FM4_MFS15_BASE)
#define FM_MFS15_LIN                              ((FM_MFS_LIN_TypeDef *)FM4_MFS15_BASE)
#define FM4_MFS15_UART                            ((FM_MFS_UART_TypeDef *)FM4_MFS15_BASE)
#define FM_MFS15_UART                             ((FM_MFS_UART_TypeDef *)FM4_MFS15_BASE)
#define FM4_MFS2                                  ((FM_MFS_TypeDef *)FM4_MFS2_BASE)
#define FM_MFS2                                   ((FM_MFS_TypeDef *)FM4_MFS2_BASE)
#define FM4_MFS2_CSIO                             ((FM_MFS_CSIO_TypeDef *)FM4_MFS2_BASE)
#define FM_MFS2_CSIO                              ((FM_MFS_CSIO_TypeDef *)FM4_MFS2_BASE)
#define FM4_MFS2_I2C                              ((FM_MFS_I2C_TypeDef *)FM4_MFS2_BASE)
#define FM_MFS2_I2C                               ((FM_MFS_I2C_TypeDef *)FM4_MFS2_BASE)
#define FM4_MFS2_LIN                              ((FM_MFS_LIN_TypeDef *)FM4_MFS2_BASE)
#define FM_MFS2_LIN                               ((FM_MFS_LIN_TypeDef *)FM4_MFS2_BASE)
#define FM4_MFS2_UART                             ((FM_MFS_UART_TypeDef *)FM4_MFS2_BASE)
#define FM_MFS2_UART                              ((FM_MFS_UART_TypeDef *)FM4_MFS2_BASE)
#define FM4_MFS3                                  ((FM_MFS_TypeDef *)FM4_MFS3_BASE)
#define FM_MFS3                                   ((FM_MFS_TypeDef *)FM4_MFS3_BASE)
#define FM4_MFS3_CSIO                             ((FM_MFS_CSIO_TypeDef *)FM4_MFS3_BASE)
#define FM_MFS3_CSIO                              ((FM_MFS_CSIO_TypeDef *)FM4_MFS3_BASE)
#define FM4_MFS3_I2C                              ((FM_MFS_I2C_TypeDef *)FM4_MFS3_BASE)
#define FM_MFS3_I2C                               ((FM_MFS_I2C_TypeDef *)FM4_MFS3_BASE)
#define FM4_MFS3_LIN                              ((FM_MFS_LIN_TypeDef *)FM4_MFS3_BASE)
#define FM_MFS3_LIN                               ((FM_MFS_LIN_TypeDef *)FM4_MFS3_BASE)
#define FM4_MFS3_UART                             ((FM_MFS_UART_TypeDef *)FM4_MFS3_BASE)
#define FM_MFS3_UART                              ((FM_MFS_UART_TypeDef *)FM4_MFS3_BASE)
#define FM4_MFS4                                  ((FM_MFS_TypeDef *)FM4_MFS4_BASE)
#define FM_MFS4                                   ((FM_MFS_TypeDef *)FM4_MFS4_BASE)
#define FM4_MFS4_CSIO                             ((FM_MFS_CSIO_TypeDef *)FM4_MFS4_BASE)
#define FM_MFS4_CSIO                              ((FM_MFS_CSIO_TypeDef *)FM4_MFS4_BASE)
#define FM4_MFS4_I2C                              ((FM_MFS_I2C_TypeDef *)FM4_MFS4_BASE)
#define FM_MFS4_I2C                               ((FM_MFS_I2C_TypeDef *)FM4_MFS4_BASE)
#define FM4_MFS4_LIN                              ((FM_MFS_LIN_TypeDef *)FM4_MFS4_BASE)
#define FM_MFS4_LIN                               ((FM_MFS_LIN_TypeDef *)FM4_MFS4_BASE)
#define FM4_MFS4_UART                             ((FM_MFS_UART_TypeDef *)FM4_MFS4_BASE)
#define FM_MFS4_UART                              ((FM_MFS_UART_TypeDef *)FM4_MFS4_BASE)
#define FM4_MFS5                                  ((FM_MFS_TypeDef *)FM4_MFS5_BASE)
#define FM_MFS5                                   ((FM_MFS_TypeDef *)FM4_MFS5_BASE)
#define FM4_MFS5_CSIO                             ((FM_MFS_CSIO_TypeDef *)FM4_MFS5_BASE)
#define FM_MFS5_CSIO                              ((FM_MFS_CSIO_TypeDef *)FM4_MFS5_BASE)
#define FM4_MFS5_I2C                              ((FM_MFS_I2C_TypeDef *)FM4_MFS5_BASE)
#define FM_MFS5_I2C                               ((FM_MFS_I2C_TypeDef *)FM4_MFS5_BASE)
#define FM4_MFS5_LIN                              ((FM_MFS_LIN_TypeDef *)FM4_MFS5_BASE)
#define FM_MFS5_LIN                               ((FM_MFS_LIN_TypeDef *)FM4_MFS5_BASE)
#define FM4_MFS5_UART                             ((FM_MFS_UART_TypeDef *)FM4_MFS5_BASE)
#define FM_MFS5_UART                              ((FM_MFS_UART_TypeDef *)FM4_MFS5_BASE)
#define FM4_MFS6                                  ((FM_MFS_TypeDef *)FM4_MFS6_BASE)
#define FM_MFS6                                   ((FM_MFS_TypeDef *)FM4_MFS6_BASE)
#define FM4_MFS6_CSIO                             ((FM_MFS_CSIO_TypeDef *)FM4_MFS6_BASE)
#define FM_MFS6_CSIO                              ((FM_MFS_CSIO_TypeDef *)FM4_MFS6_BASE)
#define FM4_MFS6_I2C                              ((FM_MFS_I2C_TypeDef *)FM4_MFS6_BASE)
#define FM_MFS6_I2C                               ((FM_MFS_I2C_TypeDef *)FM4_MFS6_BASE)
#define FM4_MFS6_LIN                              ((FM_MFS_LIN_TypeDef *)FM4_MFS6_BASE)
#define FM_MFS6_LIN                               ((FM_MFS_LIN_TypeDef *)FM4_MFS6_BASE)
#define FM4_MFS6_UART                             ((FM_MFS_UART_TypeDef *)FM4_MFS6_BASE)
#define FM_MFS6_UART                              ((FM_MFS_UART_TypeDef *)FM4_MFS6_BASE)
#define FM4_MFS7                                  ((FM_MFS_TypeDef *)FM4_MFS7_BASE)
#define FM_MFS7                                   ((FM_MFS_TypeDef *)FM4_MFS7_BASE)
#define FM4_MFS7_CSIO                             ((FM_MFS_CSIO_TypeDef *)FM4_MFS7_BASE)
#define FM_MFS7_CSIO                              ((FM_MFS_CSIO_TypeDef *)FM4_MFS7_BASE)
#define FM4_MFS7_I2C                              ((FM_MFS_I2C_TypeDef *)FM4_MFS7_BASE)
#define FM_MFS7_I2C                               ((FM_MFS_I2C_TypeDef *)FM4_MFS7_BASE)
#define FM4_MFS7_LIN                              ((FM_MFS_LIN_TypeDef *)FM4_MFS7_BASE)
#define FM_MFS7_LIN                               ((FM_MFS_LIN_TypeDef *)FM4_MFS7_BASE)
#define FM4_MFS7_UART                             ((FM_MFS_UART_TypeDef *)FM4_MFS7_BASE)
#define FM_MFS7_UART                              ((FM_MFS_UART_TypeDef *)FM4_MFS7_BASE)
#define FM4_MFS8                                  ((FM_MFS_TypeDef *)FM4_MFS8_BASE)
#define FM_MFS8                                   ((FM_MFS_TypeDef *)FM4_MFS8_BASE)
#define FM4_MFS8_CSIO                             ((FM_MFS_CSIO_TypeDef *)FM4_MFS8_BASE)
#define FM_MFS8_CSIO                              ((FM_MFS_CSIO_TypeDef *)FM4_MFS8_BASE)
#define FM4_MFS8_I2C                              ((FM_MFS_I2C_TypeDef *)FM4_MFS8_BASE)
#define FM_MFS8_I2C                               ((FM_MFS_I2C_TypeDef *)FM4_MFS8_BASE)
#define FM4_MFS8_LIN                              ((FM_MFS_LIN_TypeDef *)FM4_MFS8_BASE)
#define FM_MFS8_LIN                               ((FM_MFS_LIN_TypeDef *)FM4_MFS8_BASE)
#define FM4_MFS8_UART                             ((FM_MFS_UART_TypeDef *)FM4_MFS8_BASE)
#define FM_MFS8_UART                              ((FM_MFS_UART_TypeDef *)FM4_MFS8_BASE)
#define FM4_MFS9                                  ((FM_MFS_TypeDef *)FM4_MFS9_BASE)
#define FM_MFS9                                   ((FM_MFS_TypeDef *)FM4_MFS9_BASE)
#define FM4_MFS9_CSIO                             ((FM_MFS_CSIO_TypeDef *)FM4_MFS9_BASE)
#define FM_MFS9_CSIO                              ((FM_MFS_CSIO_TypeDef *)FM4_MFS9_BASE)
#define FM4_MFS9_I2C                              ((FM_MFS_I2C_TypeDef *)FM4_MFS9_BASE)
#define FM_MFS9_I2C                               ((FM_MFS_I2C_TypeDef *)FM4_MFS9_BASE)
#define FM4_MFS9_LIN                              ((FM_MFS_LIN_TypeDef *)FM4_MFS9_BASE)
#define FM_MFS9_LIN                               ((FM_MFS_LIN_TypeDef *)FM4_MFS9_BASE)
#define FM4_MFS9_UART                             ((FM_MFS_UART_TypeDef *)FM4_MFS9_BASE)
#define FM_MFS9_UART                              ((FM_MFS_UART_TypeDef *)FM4_MFS9_BASE)
#define FM4_MFT_PPG                               ((FM_MFT_PPG_TypeDef *)FM4_MFT_PPG_BASE)
#define FM_MFT_PPG                                ((FM_MFT_PPG_TypeDef *)FM4_MFT_PPG_BASE)
#define FM4_MFT0                                  ((FM_MFT_TypeDef *)FM4_MFT0_BASE)
#define FM_MFT0                                   ((FM_MFT_TypeDef *)FM4_MFT0_BASE)
#define FM4_MFT0_ADCMP                            ((FM_MFT_ADCMP_TypeDef *)FM4_MFT0_BASE)
#define FM_MFT0_ADCMP                             ((FM_MFT_ADCMP_TypeDef *)FM4_MFT0_BASE)
#define FM4_MFT0_FRT                              ((FM_MFT_FRT_TypeDef *)FM4_MFT0_BASE)
#define FM_MFT0_FRT                               ((FM_MFT_FRT_TypeDef *)FM4_MFT0_BASE)
#define FM4_MFT0_ICU                              ((FM_MFT_ICU_TypeDef *)FM4_MFT0_BASE)
#define FM_MFT0_ICU                               ((FM_MFT_ICU_TypeDef *)FM4_MFT0_BASE)
#define FM4_MFT0_OCU                              ((FM_MFT_OCU_TypeDef *)FM4_MFT0_BASE)
#define FM_MFT0_OCU                               ((FM_MFT_OCU_TypeDef *)FM4_MFT0_BASE)
#define FM4_MFT0_WFG                              ((FM_MFT_WFG_TypeDef *)FM4_MFT0_BASE)
#define FM_MFT0_WFG                               ((FM_MFT_WFG_TypeDef *)FM4_MFT0_BASE)
#define FM4_MFT1                                  ((FM_MFT_TypeDef *)FM4_MFT1_BASE)
#define FM_MFT1                                   ((FM_MFT_TypeDef *)FM4_MFT1_BASE)
#define FM4_MFT1_ADCMP                            ((FM_MFT_ADCMP_TypeDef *)FM4_MFT1_BASE)
#define FM_MFT1_ADCMP                             ((FM_MFT_ADCMP_TypeDef *)FM4_MFT1_BASE)
#define FM4_MFT1_FRT                              ((FM_MFT_FRT_TypeDef *)FM4_MFT1_BASE)
#define FM_MFT1_FRT                               ((FM_MFT_FRT_TypeDef *)FM4_MFT1_BASE)
#define FM4_MFT1_ICU                              ((FM_MFT_ICU_TypeDef *)FM4_MFT1_BASE)
#define FM_MFT1_ICU                               ((FM_MFT_ICU_TypeDef *)FM4_MFT1_BASE)
#define FM4_MFT1_OCU                              ((FM_MFT_OCU_TypeDef *)FM4_MFT1_BASE)
#define FM_MFT1_OCU                               ((FM_MFT_OCU_TypeDef *)FM4_MFT1_BASE)
#define FM4_MFT1_WFG                              ((FM_MFT_WFG_TypeDef *)FM4_MFT1_BASE)
#define FM_MFT1_WFG                               ((FM_MFT_WFG_TypeDef *)FM4_MFT1_BASE)
#define FM4_MFT2                                  ((FM_MFT_TypeDef *)FM4_MFT2_BASE)
#define FM_MFT2                                   ((FM_MFT_TypeDef *)FM4_MFT2_BASE)
#define FM4_MFT2_ADCMP                            ((FM_MFT_ADCMP_TypeDef *)FM4_MFT2_BASE)
#define FM_MFT2_ADCMP                             ((FM_MFT_ADCMP_TypeDef *)FM4_MFT2_BASE)
#define FM4_MFT2_FRT                              ((FM_MFT_FRT_TypeDef *)FM4_MFT2_BASE)
#define FM_MFT2_FRT                               ((FM_MFT_FRT_TypeDef *)FM4_MFT2_BASE)
#define FM4_MFT2_ICU                              ((FM_MFT_ICU_TypeDef *)FM4_MFT2_BASE)
#define FM_MFT2_ICU                               ((FM_MFT_ICU_TypeDef *)FM4_MFT2_BASE)
#define FM4_MFT2_OCU                              ((FM_MFT_OCU_TypeDef *)FM4_MFT2_BASE)
#define FM_MFT2_OCU                               ((FM_MFT_OCU_TypeDef *)FM4_MFT2_BASE)
#define FM4_MFT2_WFG                              ((FM_MFT_WFG_TypeDef *)FM4_MFT2_BASE)
#define FM_MFT2_WFG                               ((FM_MFT_WFG_TypeDef *)FM4_MFT2_BASE)
#define FM4_PCRC                                  ((FM_PCRC_TypeDef *)FM4_PCRC_BASE)
#define FM_PCRC                                   ((FM_PCRC_TypeDef *)FM4_PCRC_BASE)
#define FM4_QPRC0                                 ((FM_QPRC_TypeDef *)FM4_QPRC0_BASE)
#define FM_QPRC0                                  ((FM_QPRC_TypeDef *)FM4_QPRC0_BASE)
#define FM4_QPRC0_NF                              ((FM_QPRC_NF_TypeDef *)FM4_QPRC0_NF_BASE)
#define FM_QPRC0_NF                               ((FM_QPRC_NF_TypeDef *)FM4_QPRC0_NF_BASE)
#define FM4_QPRC1                                 ((FM_QPRC_TypeDef *)FM4_QPRC1_BASE)
#define FM_QPRC1                                  ((FM_QPRC_TypeDef *)FM4_QPRC1_BASE)
#define FM4_QPRC1_NF                              ((FM_QPRC_NF_TypeDef *)FM4_QPRC1_NF_BASE)
#define FM_QPRC1_NF                               ((FM_QPRC_NF_TypeDef *)FM4_QPRC1_NF_BASE)
#define FM4_QPRC2                                 ((FM_QPRC_TypeDef *)FM4_QPRC2_BASE)
#define FM_QPRC2                                  ((FM_QPRC_TypeDef *)FM4_QPRC2_BASE)
#define FM4_QPRC2_NF                              ((FM_QPRC_NF_TypeDef *)FM4_QPRC2_NF_BASE)
#define FM_QPRC2_NF                               ((FM_QPRC_NF_TypeDef *)FM4_QPRC2_NF_BASE)
#define FM4_QPRC3                                 ((FM_QPRC_TypeDef *)FM4_QPRC3_BASE)
#define FM_QPRC3                                  ((FM_QPRC_TypeDef *)FM4_QPRC3_BASE)
#define FM4_QPRC3_NF                              ((FM_QPRC_NF_TypeDef *)FM4_QPRC3_NF_BASE)
#define FM_QPRC3_NF                               ((FM_QPRC_NF_TypeDef *)FM4_QPRC3_NF_BASE)
#define FM4_RTC                                   ((FM_RTC_TypeDef *)FM4_RTC_BASE)
#define FM_RTC                                    ((FM_RTC_TypeDef *)FM4_RTC_BASE)
#define FM4_SBSSR                                 ((FM_SBSSR_TypeDef *)FM4_SBSSR_BASE)
#define FM_SBSSR                                  ((FM_SBSSR_TypeDef *)FM4_SBSSR_BASE)
#define FM4_SDIF                                  ((FM_SDIF_TypeDef *)FM4_SDIF_BASE)
#define FM_SDIF                                   ((FM_SDIF_TypeDef *)FM4_SDIF_BASE)
#define FM4_SWWDT                                 ((FM_SWWDT_TypeDef *)FM4_SWWDT_BASE)
#define FM_SWWDT                                  ((FM_SWWDT_TypeDef *)FM4_SWWDT_BASE)
#define FM4_UNIQUE_ID                             ((FM_UNIQUE_ID_TypeDef *)FM4_UNIQUE_ID_BASE)
#define FM_UNIQUE_ID                              ((FM_UNIQUE_ID_TypeDef *)FM4_UNIQUE_ID_BASE)
#define FM4_USB0                                  ((FM_USB_TypeDef *)FM4_USB0_BASE)
#define FM_USB0                                   ((FM_USB_TypeDef *)FM4_USB0_BASE)
#define FM4_USB1                                  ((FM_USB_TypeDef *)FM4_USB1_BASE)
#define FM_USB1                                   ((FM_USB_TypeDef *)FM4_USB1_BASE)
#define FM4_USBETHERCLK                           ((FM_USBETHERCLK_TypeDef *)FM4_USBETHERCLK_BASE)
#define FM_USBETHERCLK                            ((FM_USBETHERCLK_TypeDef *)FM4_USBETHERCLK_BASE)
#define FM4_WC                                    ((FM_WC_TypeDef *)FM4_WC_BASE)
#define FM_WC                                     ((FM_WC_TypeDef *)FM4_WC_BASE)
/*******************************************************************************
* Register Definitions
*******************************************************************************/
/*******************************************************************************
* ADC Registers ADC0
*   Register Definition
*******************************************************************************/
#define FM_ADC0_ADSR                              *((volatile  uint8_t*)(0x40027000UL))
#define FM4_ADC0_ADSR                             *((volatile  uint8_t*)(0x40027000UL))
#define FM_ADC0_ADCR                              *((volatile  uint8_t*)(0x40027001UL))
#define FM4_ADC0_ADCR                             *((volatile  uint8_t*)(0x40027001UL))
#define FM_ADC0_SFNS                              *((volatile  uint8_t*)(0x40027008UL))
#define FM4_ADC0_SFNS                             *((volatile  uint8_t*)(0x40027008UL))
#define FM_ADC0_SCCR                              *((volatile  uint8_t*)(0x40027009UL))
#define FM4_ADC0_SCCR                             *((volatile  uint8_t*)(0x40027009UL))
#define FM_ADC0_SCFD                              *((volatile uint32_t*)(0x4002700CUL))
#define FM4_ADC0_SCFD                             *((volatile uint32_t*)(0x4002700CUL))
#define FM_ADC0_SCFD_FDAS1                        *((volatile uint32_t*)(0x4002700CUL))
#define FM4_ADC0_SCFD_FDAS1                       *((volatile uint32_t*)(0x4002700CUL))
#define FM_ADC0_SCIS23                            *((volatile uint16_t*)(0x40027010UL))
#define FM4_ADC0_SCIS23                           *((volatile uint16_t*)(0x40027010UL))
#define FM_ADC0_SCIS01                            *((volatile uint16_t*)(0x40027014UL))
#define FM4_ADC0_SCIS01                           *((volatile uint16_t*)(0x40027014UL))
#define FM_ADC0_PFNS                              *((volatile  uint8_t*)(0x40027018UL))
#define FM4_ADC0_PFNS                             *((volatile  uint8_t*)(0x40027018UL))
#define FM_ADC0_PCCR                              *((volatile  uint8_t*)(0x40027019UL))
#define FM4_ADC0_PCCR                             *((volatile  uint8_t*)(0x40027019UL))
#define FM_ADC0_PCFD                              *((volatile uint32_t*)(0x4002701CUL))
#define FM4_ADC0_PCFD                             *((volatile uint32_t*)(0x4002701CUL))
#define FM_ADC0_PCFD_FDAS1                        *((volatile uint32_t*)(0x4002701CUL))
#define FM4_ADC0_PCFD_FDAS1                       *((volatile uint32_t*)(0x4002701CUL))
#define FM_ADC0_PCIS                              *((volatile  uint8_t*)(0x40027020UL))
#define FM4_ADC0_PCIS                             *((volatile  uint8_t*)(0x40027020UL))
#define FM_ADC0_CMPCR                             *((volatile  uint8_t*)(0x40027024UL))
#define FM4_ADC0_CMPCR                            *((volatile  uint8_t*)(0x40027024UL))
#define FM_ADC0_CMPD                              *((volatile uint16_t*)(0x40027026UL))
#define FM4_ADC0_CMPD                             *((volatile uint16_t*)(0x40027026UL))
#define FM_ADC0_ADSS23                            *((volatile uint16_t*)(0x40027028UL))
#define FM4_ADC0_ADSS23                           *((volatile uint16_t*)(0x40027028UL))
#define FM_ADC0_ADSS01                            *((volatile uint16_t*)(0x4002702CUL))
#define FM4_ADC0_ADSS01                           *((volatile uint16_t*)(0x4002702CUL))
#define FM_ADC0_ADST01                            *((volatile uint16_t*)(0x40027030UL))
#define FM4_ADC0_ADST01                           *((volatile uint16_t*)(0x40027030UL))
#define FM_ADC0_ADCT                              *((volatile  uint8_t*)(0x40027034UL))
#define FM4_ADC0_ADCT                             *((volatile  uint8_t*)(0x40027034UL))
#define FM_ADC0_PRTSL                             *((volatile  uint8_t*)(0x40027038UL))
#define FM4_ADC0_PRTSL                            *((volatile  uint8_t*)(0x40027038UL))
#define FM_ADC0_SCTSL                             *((volatile  uint8_t*)(0x40027039UL))
#define FM4_ADC0_SCTSL                            *((volatile  uint8_t*)(0x40027039UL))
#define FM_ADC0_ADCEN                             *((volatile uint16_t*)(0x4002703CUL))
#define FM4_ADC0_ADCEN                            *((volatile uint16_t*)(0x4002703CUL))
#define FM_ADC0_CALSR                             *((volatile uint32_t*)(0x40027040UL))
#define FM4_ADC0_CALSR                            *((volatile uint32_t*)(0x40027040UL))
#define FM_ADC0_WCMRCOT                           *((volatile  uint8_t*)(0x40027044UL))
#define FM4_ADC0_WCMRCOT                          *((volatile  uint8_t*)(0x40027044UL))
#define FM_ADC0_WCMRCIF                           *((volatile  uint8_t*)(0x40027048UL))
#define FM4_ADC0_WCMRCIF                          *((volatile  uint8_t*)(0x40027048UL))
#define FM_ADC0_WCMPCR                            *((volatile  uint8_t*)(0x4002704CUL))
#define FM4_ADC0_WCMPCR                           *((volatile  uint8_t*)(0x4002704CUL))
#define FM_ADC0_WCMPSR                            *((volatile  uint8_t*)(0x4002704DUL))
#define FM4_ADC0_WCMPSR                           *((volatile  uint8_t*)(0x4002704DUL))
#define FM_ADC0_WCMPDL                            *((volatile uint16_t*)(0x40027050UL))
#define FM4_ADC0_WCMPDL                           *((volatile uint16_t*)(0x40027050UL))
#define FM_ADC0_WCMPDH                            *((volatile uint16_t*)(0x40027052UL))
#define FM4_ADC0_WCMPDH                           *((volatile uint16_t*)(0x40027052UL))

/*******************************************************************************
* ADC Registers ADC1
*   Register Definition
*******************************************************************************/
#define FM_ADC1_ADSR                              *((volatile  uint8_t*)(0x40027100UL))
#define FM4_ADC1_ADSR                             *((volatile  uint8_t*)(0x40027100UL))
#define FM_ADC1_ADCR                              *((volatile  uint8_t*)(0x40027101UL))
#define FM4_ADC1_ADCR                             *((volatile  uint8_t*)(0x40027101UL))
#define FM_ADC1_SFNS                              *((volatile  uint8_t*)(0x40027108UL))
#define FM4_ADC1_SFNS                             *((volatile  uint8_t*)(0x40027108UL))
#define FM_ADC1_SCCR                              *((volatile  uint8_t*)(0x40027109UL))
#define FM4_ADC1_SCCR                             *((volatile  uint8_t*)(0x40027109UL))
#define FM_ADC1_SCFD                              *((volatile uint32_t*)(0x4002710CUL))
#define FM4_ADC1_SCFD                             *((volatile uint32_t*)(0x4002710CUL))
#define FM_ADC1_SCFD_FDAS1                        *((volatile uint32_t*)(0x4002710CUL))
#define FM4_ADC1_SCFD_FDAS1                       *((volatile uint32_t*)(0x4002710CUL))
#define FM_ADC1_SCIS23                            *((volatile uint16_t*)(0x40027110UL))
#define FM4_ADC1_SCIS23                           *((volatile uint16_t*)(0x40027110UL))
#define FM_ADC1_SCIS01                            *((volatile uint16_t*)(0x40027114UL))
#define FM4_ADC1_SCIS01                           *((volatile uint16_t*)(0x40027114UL))
#define FM_ADC1_PFNS                              *((volatile  uint8_t*)(0x40027118UL))
#define FM4_ADC1_PFNS                             *((volatile  uint8_t*)(0x40027118UL))
#define FM_ADC1_PCCR                              *((volatile  uint8_t*)(0x40027119UL))
#define FM4_ADC1_PCCR                             *((volatile  uint8_t*)(0x40027119UL))
#define FM_ADC1_PCFD                              *((volatile uint32_t*)(0x4002711CUL))
#define FM4_ADC1_PCFD                             *((volatile uint32_t*)(0x4002711CUL))
#define FM_ADC1_PCFD_FDAS1                        *((volatile uint32_t*)(0x4002711CUL))
#define FM4_ADC1_PCFD_FDAS1                       *((volatile uint32_t*)(0x4002711CUL))
#define FM_ADC1_PCIS                              *((volatile  uint8_t*)(0x40027120UL))
#define FM4_ADC1_PCIS                             *((volatile  uint8_t*)(0x40027120UL))
#define FM_ADC1_CMPCR                             *((volatile  uint8_t*)(0x40027124UL))
#define FM4_ADC1_CMPCR                            *((volatile  uint8_t*)(0x40027124UL))
#define FM_ADC1_CMPD                              *((volatile uint16_t*)(0x40027126UL))
#define FM4_ADC1_CMPD                             *((volatile uint16_t*)(0x40027126UL))
#define FM_ADC1_ADSS23                            *((volatile uint16_t*)(0x40027128UL))
#define FM4_ADC1_ADSS23                           *((volatile uint16_t*)(0x40027128UL))
#define FM_ADC1_ADSS01                            *((volatile uint16_t*)(0x4002712CUL))
#define FM4_ADC1_ADSS01                           *((volatile uint16_t*)(0x4002712CUL))
#define FM_ADC1_ADST01                            *((volatile uint16_t*)(0x40027130UL))
#define FM4_ADC1_ADST01                           *((volatile uint16_t*)(0x40027130UL))
#define FM_ADC1_ADCT                              *((volatile  uint8_t*)(0x40027134UL))
#define FM4_ADC1_ADCT                             *((volatile  uint8_t*)(0x40027134UL))
#define FM_ADC1_PRTSL                             *((volatile  uint8_t*)(0x40027138UL))
#define FM4_ADC1_PRTSL                            *((volatile  uint8_t*)(0x40027138UL))
#define FM_ADC1_SCTSL                             *((volatile  uint8_t*)(0x40027139UL))
#define FM4_ADC1_SCTSL                            *((volatile  uint8_t*)(0x40027139UL))
#define FM_ADC1_ADCEN                             *((volatile uint16_t*)(0x4002713CUL))
#define FM4_ADC1_ADCEN                            *((volatile uint16_t*)(0x4002713CUL))
#define FM_ADC1_CALSR                             *((volatile uint32_t*)(0x40027140UL))
#define FM4_ADC1_CALSR                            *((volatile uint32_t*)(0x40027140UL))
#define FM_ADC1_WCMRCOT                           *((volatile  uint8_t*)(0x40027144UL))
#define FM4_ADC1_WCMRCOT                          *((volatile  uint8_t*)(0x40027144UL))
#define FM_ADC1_WCMRCIF                           *((volatile  uint8_t*)(0x40027148UL))
#define FM4_ADC1_WCMRCIF                          *((volatile  uint8_t*)(0x40027148UL))
#define FM_ADC1_WCMPCR                            *((volatile  uint8_t*)(0x4002714CUL))
#define FM4_ADC1_WCMPCR                           *((volatile  uint8_t*)(0x4002714CUL))
#define FM_ADC1_WCMPSR                            *((volatile  uint8_t*)(0x4002714DUL))
#define FM4_ADC1_WCMPSR                           *((volatile  uint8_t*)(0x4002714DUL))
#define FM_ADC1_WCMPDL                            *((volatile uint16_t*)(0x40027150UL))
#define FM4_ADC1_WCMPDL                           *((volatile uint16_t*)(0x40027150UL))
#define FM_ADC1_WCMPDH                            *((volatile uint16_t*)(0x40027152UL))
#define FM4_ADC1_WCMPDH                           *((volatile uint16_t*)(0x40027152UL))

/*******************************************************************************
* ADC Registers ADC2
*   Register Definition
*******************************************************************************/
#define FM_ADC2_ADSR                              *((volatile  uint8_t*)(0x40027200UL))
#define FM4_ADC2_ADSR                             *((volatile  uint8_t*)(0x40027200UL))
#define FM_ADC2_ADCR                              *((volatile  uint8_t*)(0x40027201UL))
#define FM4_ADC2_ADCR                             *((volatile  uint8_t*)(0x40027201UL))
#define FM_ADC2_SFNS                              *((volatile  uint8_t*)(0x40027208UL))
#define FM4_ADC2_SFNS                             *((volatile  uint8_t*)(0x40027208UL))
#define FM_ADC2_SCCR                              *((volatile  uint8_t*)(0x40027209UL))
#define FM4_ADC2_SCCR                             *((volatile  uint8_t*)(0x40027209UL))
#define FM_ADC2_SCFD                              *((volatile uint32_t*)(0x4002720CUL))
#define FM4_ADC2_SCFD                             *((volatile uint32_t*)(0x4002720CUL))
#define FM_ADC2_SCFD_FDAS1                        *((volatile uint32_t*)(0x4002720CUL))
#define FM4_ADC2_SCFD_FDAS1                       *((volatile uint32_t*)(0x4002720CUL))
#define FM_ADC2_SCIS23                            *((volatile uint16_t*)(0x40027210UL))
#define FM4_ADC2_SCIS23                           *((volatile uint16_t*)(0x40027210UL))
#define FM_ADC2_SCIS01                            *((volatile uint16_t*)(0x40027214UL))
#define FM4_ADC2_SCIS01                           *((volatile uint16_t*)(0x40027214UL))
#define FM_ADC2_PFNS                              *((volatile  uint8_t*)(0x40027218UL))
#define FM4_ADC2_PFNS                             *((volatile  uint8_t*)(0x40027218UL))
#define FM_ADC2_PCCR                              *((volatile  uint8_t*)(0x40027219UL))
#define FM4_ADC2_PCCR                             *((volatile  uint8_t*)(0x40027219UL))
#define FM_ADC2_PCFD                              *((volatile uint32_t*)(0x4002721CUL))
#define FM4_ADC2_PCFD                             *((volatile uint32_t*)(0x4002721CUL))
#define FM_ADC2_PCFD_FDAS1                        *((volatile uint32_t*)(0x4002721CUL))
#define FM4_ADC2_PCFD_FDAS1                       *((volatile uint32_t*)(0x4002721CUL))
#define FM_ADC2_PCIS                              *((volatile  uint8_t*)(0x40027220UL))
#define FM4_ADC2_PCIS                             *((volatile  uint8_t*)(0x40027220UL))
#define FM_ADC2_CMPCR                             *((volatile  uint8_t*)(0x40027224UL))
#define FM4_ADC2_CMPCR                            *((volatile  uint8_t*)(0x40027224UL))
#define FM_ADC2_CMPD                              *((volatile uint16_t*)(0x40027226UL))
#define FM4_ADC2_CMPD                             *((volatile uint16_t*)(0x40027226UL))
#define FM_ADC2_ADSS23                            *((volatile uint16_t*)(0x40027228UL))
#define FM4_ADC2_ADSS23                           *((volatile uint16_t*)(0x40027228UL))
#define FM_ADC2_ADSS01                            *((volatile uint16_t*)(0x4002722CUL))
#define FM4_ADC2_ADSS01                           *((volatile uint16_t*)(0x4002722CUL))
#define FM_ADC2_ADST01                            *((volatile uint16_t*)(0x40027230UL))
#define FM4_ADC2_ADST01                           *((volatile uint16_t*)(0x40027230UL))
#define FM_ADC2_ADCT                              *((volatile  uint8_t*)(0x40027234UL))
#define FM4_ADC2_ADCT                             *((volatile  uint8_t*)(0x40027234UL))
#define FM_ADC2_PRTSL                             *((volatile  uint8_t*)(0x40027238UL))
#define FM4_ADC2_PRTSL                            *((volatile  uint8_t*)(0x40027238UL))
#define FM_ADC2_SCTSL                             *((volatile  uint8_t*)(0x40027239UL))
#define FM4_ADC2_SCTSL                            *((volatile  uint8_t*)(0x40027239UL))
#define FM_ADC2_ADCEN                             *((volatile uint16_t*)(0x4002723CUL))
#define FM4_ADC2_ADCEN                            *((volatile uint16_t*)(0x4002723CUL))
#define FM_ADC2_CALSR                             *((volatile uint32_t*)(0x40027240UL))
#define FM4_ADC2_CALSR                            *((volatile uint32_t*)(0x40027240UL))
#define FM_ADC2_WCMRCOT                           *((volatile  uint8_t*)(0x40027244UL))
#define FM4_ADC2_WCMRCOT                          *((volatile  uint8_t*)(0x40027244UL))
#define FM_ADC2_WCMRCIF                           *((volatile  uint8_t*)(0x40027248UL))
#define FM4_ADC2_WCMRCIF                          *((volatile  uint8_t*)(0x40027248UL))
#define FM_ADC2_WCMPCR                            *((volatile  uint8_t*)(0x4002724CUL))
#define FM4_ADC2_WCMPCR                           *((volatile  uint8_t*)(0x4002724CUL))
#define FM_ADC2_WCMPSR                            *((volatile  uint8_t*)(0x4002724DUL))
#define FM4_ADC2_WCMPSR                           *((volatile  uint8_t*)(0x4002724DUL))
#define FM_ADC2_WCMPDL                            *((volatile uint16_t*)(0x40027250UL))
#define FM4_ADC2_WCMPDL                           *((volatile uint16_t*)(0x40027250UL))
#define FM_ADC2_WCMPDH                            *((volatile uint16_t*)(0x40027252UL))
#define FM4_ADC2_WCMPDH                           *((volatile uint16_t*)(0x40027252UL))

/*******************************************************************************
* BT Registers BT0
*   Register Definition
*******************************************************************************/
#define FM_BT0_PPG_PRLL                           *((volatile uint16_t*)(0x40025000UL))
#define FM4_BT0_PPG_PRLL                          *((volatile uint16_t*)(0x40025000UL))
#define FM_BT0_PWM_PCSR                           *((volatile uint16_t*)(0x40025000UL))
#define FM4_BT0_PWM_PCSR                          *((volatile uint16_t*)(0x40025000UL))
#define FM_BT0_RT_PCSR                            *((volatile uint16_t*)(0x40025000UL))
#define FM4_BT0_RT_PCSR                           *((volatile uint16_t*)(0x40025000UL))
#define FM_BT0_PPG_PRLH                           *((volatile uint16_t*)(0x40025004UL))
#define FM4_BT0_PPG_PRLH                          *((volatile uint16_t*)(0x40025004UL))
#define FM_BT0_PWC_DTBF                           *((volatile uint16_t*)(0x40025004UL))
#define FM4_BT0_PWC_DTBF                          *((volatile uint16_t*)(0x40025004UL))
#define FM_BT0_PWM_PDUT                           *((volatile uint16_t*)(0x40025004UL))
#define FM4_BT0_PWM_PDUT                          *((volatile uint16_t*)(0x40025004UL))
#define FM_BT0_PPG_TMR                            *((volatile uint16_t*)(0x40025008UL))
#define FM4_BT0_PPG_TMR                           *((volatile uint16_t*)(0x40025008UL))
#define FM_BT0_PWM_TMR                            *((volatile uint16_t*)(0x40025008UL))
#define FM4_BT0_PWM_TMR                           *((volatile uint16_t*)(0x40025008UL))
#define FM_BT0_RT_TMR                             *((volatile uint16_t*)(0x40025008UL))
#define FM4_BT0_RT_TMR                            *((volatile uint16_t*)(0x40025008UL))
#define FM_BT0_PPG_TMCR                           *((volatile uint16_t*)(0x4002500CUL))
#define FM4_BT0_PPG_TMCR                          *((volatile uint16_t*)(0x4002500CUL))
#define FM_BT0_PWC_TMCR                           *((volatile uint16_t*)(0x4002500CUL))
#define FM4_BT0_PWC_TMCR                          *((volatile uint16_t*)(0x4002500CUL))
#define FM_BT0_PWM_TMCR                           *((volatile uint16_t*)(0x4002500CUL))
#define FM4_BT0_PWM_TMCR                          *((volatile uint16_t*)(0x4002500CUL))
#define FM_BT0_RT_TMCR                            *((volatile uint16_t*)(0x4002500CUL))
#define FM4_BT0_RT_TMCR                           *((volatile uint16_t*)(0x4002500CUL))
#define FM_BT0_PPG_STC                            *((volatile  uint8_t*)(0x40025010UL))
#define FM4_BT0_PPG_STC                           *((volatile  uint8_t*)(0x40025010UL))
#define FM_BT0_PWC_STC                            *((volatile  uint8_t*)(0x40025010UL))
#define FM4_BT0_PWC_STC                           *((volatile  uint8_t*)(0x40025010UL))
#define FM_BT0_PWM_STC                            *((volatile  uint8_t*)(0x40025010UL))
#define FM4_BT0_PWM_STC                           *((volatile  uint8_t*)(0x40025010UL))
#define FM_BT0_RT_STC                             *((volatile  uint8_t*)(0x40025010UL))
#define FM4_BT0_RT_STC                            *((volatile  uint8_t*)(0x40025010UL))
#define FM_BT0_PPG_TMCR2                          *((volatile  uint8_t*)(0x40025011UL))
#define FM4_BT0_PPG_TMCR2                         *((volatile  uint8_t*)(0x40025011UL))
#define FM_BT0_PWC_TMCR2                          *((volatile  uint8_t*)(0x40025011UL))
#define FM4_BT0_PWC_TMCR2                         *((volatile  uint8_t*)(0x40025011UL))
#define FM_BT0_PWM_TMCR2                          *((volatile  uint8_t*)(0x40025011UL))
#define FM4_BT0_PWM_TMCR2                         *((volatile  uint8_t*)(0x40025011UL))
#define FM_BT0_RT_TMCR2                           *((volatile  uint8_t*)(0x40025011UL))
#define FM4_BT0_RT_TMCR2                          *((volatile  uint8_t*)(0x40025011UL))

/*******************************************************************************
* BT Registers BT1
*   Register Definition
*******************************************************************************/
#define FM_BT1_PPG_PRLL                           *((volatile uint16_t*)(0x40025040UL))
#define FM4_BT1_PPG_PRLL                          *((volatile uint16_t*)(0x40025040UL))
#define FM_BT1_PWM_PCSR                           *((volatile uint16_t*)(0x40025040UL))
#define FM4_BT1_PWM_PCSR                          *((volatile uint16_t*)(0x40025040UL))
#define FM_BT1_RT_PCSR                            *((volatile uint16_t*)(0x40025040UL))
#define FM4_BT1_RT_PCSR                           *((volatile uint16_t*)(0x40025040UL))
#define FM_BT1_PPG_PRLH                           *((volatile uint16_t*)(0x40025044UL))
#define FM4_BT1_PPG_PRLH                          *((volatile uint16_t*)(0x40025044UL))
#define FM_BT1_PWC_DTBF                           *((volatile uint16_t*)(0x40025044UL))
#define FM4_BT1_PWC_DTBF                          *((volatile uint16_t*)(0x40025044UL))
#define FM_BT1_PWM_PDUT                           *((volatile uint16_t*)(0x40025044UL))
#define FM4_BT1_PWM_PDUT                          *((volatile uint16_t*)(0x40025044UL))
#define FM_BT1_PPG_TMR                            *((volatile uint16_t*)(0x40025048UL))
#define FM4_BT1_PPG_TMR                           *((volatile uint16_t*)(0x40025048UL))
#define FM_BT1_PWM_TMR                            *((volatile uint16_t*)(0x40025048UL))
#define FM4_BT1_PWM_TMR                           *((volatile uint16_t*)(0x40025048UL))
#define FM_BT1_RT_TMR                             *((volatile uint16_t*)(0x40025048UL))
#define FM4_BT1_RT_TMR                            *((volatile uint16_t*)(0x40025048UL))
#define FM_BT1_PPG_TMCR                           *((volatile uint16_t*)(0x4002504CUL))
#define FM4_BT1_PPG_TMCR                          *((volatile uint16_t*)(0x4002504CUL))
#define FM_BT1_PWC_TMCR                           *((volatile uint16_t*)(0x4002504CUL))
#define FM4_BT1_PWC_TMCR                          *((volatile uint16_t*)(0x4002504CUL))
#define FM_BT1_PWM_TMCR                           *((volatile uint16_t*)(0x4002504CUL))
#define FM4_BT1_PWM_TMCR                          *((volatile uint16_t*)(0x4002504CUL))
#define FM_BT1_RT_TMCR                            *((volatile uint16_t*)(0x4002504CUL))
#define FM4_BT1_RT_TMCR                           *((volatile uint16_t*)(0x4002504CUL))
#define FM_BT1_PPG_STC                            *((volatile  uint8_t*)(0x40025050UL))
#define FM4_BT1_PPG_STC                           *((volatile  uint8_t*)(0x40025050UL))
#define FM_BT1_PWC_STC                            *((volatile  uint8_t*)(0x40025050UL))
#define FM4_BT1_PWC_STC                           *((volatile  uint8_t*)(0x40025050UL))
#define FM_BT1_PWM_STC                            *((volatile  uint8_t*)(0x40025050UL))
#define FM4_BT1_PWM_STC                           *((volatile  uint8_t*)(0x40025050UL))
#define FM_BT1_RT_STC                             *((volatile  uint8_t*)(0x40025050UL))
#define FM4_BT1_RT_STC                            *((volatile  uint8_t*)(0x40025050UL))
#define FM_BT1_PPG_TMCR2                          *((volatile  uint8_t*)(0x40025051UL))
#define FM4_BT1_PPG_TMCR2                         *((volatile  uint8_t*)(0x40025051UL))
#define FM_BT1_PWC_TMCR2                          *((volatile  uint8_t*)(0x40025051UL))
#define FM4_BT1_PWC_TMCR2                         *((volatile  uint8_t*)(0x40025051UL))
#define FM_BT1_PWM_TMCR2                          *((volatile  uint8_t*)(0x40025051UL))
#define FM4_BT1_PWM_TMCR2                         *((volatile  uint8_t*)(0x40025051UL))
#define FM_BT1_RT_TMCR2                           *((volatile  uint8_t*)(0x40025051UL))
#define FM4_BT1_RT_TMCR2                          *((volatile  uint8_t*)(0x40025051UL))

/*******************************************************************************
* BT Registers BT10
*   Register Definition
*******************************************************************************/
#define FM_BT10_PPG_PRLL                          *((volatile uint16_t*)(0x40025480UL))
#define FM4_BT10_PPG_PRLL                         *((volatile uint16_t*)(0x40025480UL))
#define FM_BT10_PWM_PCSR                          *((volatile uint16_t*)(0x40025480UL))
#define FM4_BT10_PWM_PCSR                         *((volatile uint16_t*)(0x40025480UL))
#define FM_BT10_RT_PCSR                           *((volatile uint16_t*)(0x40025480UL))
#define FM4_BT10_RT_PCSR                          *((volatile uint16_t*)(0x40025480UL))
#define FM_BT10_PPG_PRLH                          *((volatile uint16_t*)(0x40025484UL))
#define FM4_BT10_PPG_PRLH                         *((volatile uint16_t*)(0x40025484UL))
#define FM_BT10_PWC_DTBF                          *((volatile uint16_t*)(0x40025484UL))
#define FM4_BT10_PWC_DTBF                         *((volatile uint16_t*)(0x40025484UL))
#define FM_BT10_PWM_PDUT                          *((volatile uint16_t*)(0x40025484UL))
#define FM4_BT10_PWM_PDUT                         *((volatile uint16_t*)(0x40025484UL))
#define FM_BT10_PPG_TMR                           *((volatile uint16_t*)(0x40025488UL))
#define FM4_BT10_PPG_TMR                          *((volatile uint16_t*)(0x40025488UL))
#define FM_BT10_PWM_TMR                           *((volatile uint16_t*)(0x40025488UL))
#define FM4_BT10_PWM_TMR                          *((volatile uint16_t*)(0x40025488UL))
#define FM_BT10_RT_TMR                            *((volatile uint16_t*)(0x40025488UL))
#define FM4_BT10_RT_TMR                           *((volatile uint16_t*)(0x40025488UL))
#define FM_BT10_PPG_TMCR                          *((volatile uint16_t*)(0x4002548CUL))
#define FM4_BT10_PPG_TMCR                         *((volatile uint16_t*)(0x4002548CUL))
#define FM_BT10_PWC_TMCR                          *((volatile uint16_t*)(0x4002548CUL))
#define FM4_BT10_PWC_TMCR                         *((volatile uint16_t*)(0x4002548CUL))
#define FM_BT10_PWM_TMCR                          *((volatile uint16_t*)(0x4002548CUL))
#define FM4_BT10_PWM_TMCR                         *((volatile uint16_t*)(0x4002548CUL))
#define FM_BT10_RT_TMCR                           *((volatile uint16_t*)(0x4002548CUL))
#define FM4_BT10_RT_TMCR                          *((volatile uint16_t*)(0x4002548CUL))
#define FM_BT10_PPG_STC                           *((volatile  uint8_t*)(0x40025490UL))
#define FM4_BT10_PPG_STC                          *((volatile  uint8_t*)(0x40025490UL))
#define FM_BT10_PWC_STC                           *((volatile  uint8_t*)(0x40025490UL))
#define FM4_BT10_PWC_STC                          *((volatile  uint8_t*)(0x40025490UL))
#define FM_BT10_PWM_STC                           *((volatile  uint8_t*)(0x40025490UL))
#define FM4_BT10_PWM_STC                          *((volatile  uint8_t*)(0x40025490UL))
#define FM_BT10_RT_STC                            *((volatile  uint8_t*)(0x40025490UL))
#define FM4_BT10_RT_STC                           *((volatile  uint8_t*)(0x40025490UL))
#define FM_BT10_PPG_TMCR2                         *((volatile  uint8_t*)(0x40025491UL))
#define FM4_BT10_PPG_TMCR2                        *((volatile  uint8_t*)(0x40025491UL))
#define FM_BT10_PWC_TMCR2                         *((volatile  uint8_t*)(0x40025491UL))
#define FM4_BT10_PWC_TMCR2                        *((volatile  uint8_t*)(0x40025491UL))
#define FM_BT10_PWM_TMCR2                         *((volatile  uint8_t*)(0x40025491UL))
#define FM4_BT10_PWM_TMCR2                        *((volatile  uint8_t*)(0x40025491UL))
#define FM_BT10_RT_TMCR2                          *((volatile  uint8_t*)(0x40025491UL))
#define FM4_BT10_RT_TMCR2                         *((volatile  uint8_t*)(0x40025491UL))

/*******************************************************************************
* BT Registers BT11
*   Register Definition
*******************************************************************************/
#define FM_BT11_PPG_PRLL                          *((volatile uint16_t*)(0x400254C0UL))
#define FM4_BT11_PPG_PRLL                         *((volatile uint16_t*)(0x400254C0UL))
#define FM_BT11_PWM_PCSR                          *((volatile uint16_t*)(0x400254C0UL))
#define FM4_BT11_PWM_PCSR                         *((volatile uint16_t*)(0x400254C0UL))
#define FM_BT11_RT_PCSR                           *((volatile uint16_t*)(0x400254C0UL))
#define FM4_BT11_RT_PCSR                          *((volatile uint16_t*)(0x400254C0UL))
#define FM_BT11_PPG_PRLH                          *((volatile uint16_t*)(0x400254C4UL))
#define FM4_BT11_PPG_PRLH                         *((volatile uint16_t*)(0x400254C4UL))
#define FM_BT11_PWC_DTBF                          *((volatile uint16_t*)(0x400254C4UL))
#define FM4_BT11_PWC_DTBF                         *((volatile uint16_t*)(0x400254C4UL))
#define FM_BT11_PWM_PDUT                          *((volatile uint16_t*)(0x400254C4UL))
#define FM4_BT11_PWM_PDUT                         *((volatile uint16_t*)(0x400254C4UL))
#define FM_BT11_PPG_TMR                           *((volatile uint16_t*)(0x400254C8UL))
#define FM4_BT11_PPG_TMR                          *((volatile uint16_t*)(0x400254C8UL))
#define FM_BT11_PWM_TMR                           *((volatile uint16_t*)(0x400254C8UL))
#define FM4_BT11_PWM_TMR                          *((volatile uint16_t*)(0x400254C8UL))
#define FM_BT11_RT_TMR                            *((volatile uint16_t*)(0x400254C8UL))
#define FM4_BT11_RT_TMR                           *((volatile uint16_t*)(0x400254C8UL))
#define FM_BT11_PPG_TMCR                          *((volatile uint16_t*)(0x400254CCUL))
#define FM4_BT11_PPG_TMCR                         *((volatile uint16_t*)(0x400254CCUL))
#define FM_BT11_PWC_TMCR                          *((volatile uint16_t*)(0x400254CCUL))
#define FM4_BT11_PWC_TMCR                         *((volatile uint16_t*)(0x400254CCUL))
#define FM_BT11_PWM_TMCR                          *((volatile uint16_t*)(0x400254CCUL))
#define FM4_BT11_PWM_TMCR                         *((volatile uint16_t*)(0x400254CCUL))
#define FM_BT11_RT_TMCR                           *((volatile uint16_t*)(0x400254CCUL))
#define FM4_BT11_RT_TMCR                          *((volatile uint16_t*)(0x400254CCUL))
#define FM_BT11_PPG_STC                           *((volatile  uint8_t*)(0x400254D0UL))
#define FM4_BT11_PPG_STC                          *((volatile  uint8_t*)(0x400254D0UL))
#define FM_BT11_PWC_STC                           *((volatile  uint8_t*)(0x400254D0UL))
#define FM4_BT11_PWC_STC                          *((volatile  uint8_t*)(0x400254D0UL))
#define FM_BT11_PWM_STC                           *((volatile  uint8_t*)(0x400254D0UL))
#define FM4_BT11_PWM_STC                          *((volatile  uint8_t*)(0x400254D0UL))
#define FM_BT11_RT_STC                            *((volatile  uint8_t*)(0x400254D0UL))
#define FM4_BT11_RT_STC                           *((volatile  uint8_t*)(0x400254D0UL))
#define FM_BT11_PPG_TMCR2                         *((volatile  uint8_t*)(0x400254D1UL))
#define FM4_BT11_PPG_TMCR2                        *((volatile  uint8_t*)(0x400254D1UL))
#define FM_BT11_PWC_TMCR2                         *((volatile  uint8_t*)(0x400254D1UL))
#define FM4_BT11_PWC_TMCR2                        *((volatile  uint8_t*)(0x400254D1UL))
#define FM_BT11_PWM_TMCR2                         *((volatile  uint8_t*)(0x400254D1UL))
#define FM4_BT11_PWM_TMCR2                        *((volatile  uint8_t*)(0x400254D1UL))
#define FM_BT11_RT_TMCR2                          *((volatile  uint8_t*)(0x400254D1UL))
#define FM4_BT11_RT_TMCR2                         *((volatile  uint8_t*)(0x400254D1UL))

/*******************************************************************************
* BT Registers BT12
*   Register Definition
*******************************************************************************/
#define FM_BT12_PPG_PRLL                          *((volatile uint16_t*)(0x40025600UL))
#define FM4_BT12_PPG_PRLL                         *((volatile uint16_t*)(0x40025600UL))
#define FM_BT12_PWM_PCSR                          *((volatile uint16_t*)(0x40025600UL))
#define FM4_BT12_PWM_PCSR                         *((volatile uint16_t*)(0x40025600UL))
#define FM_BT12_RT_PCSR                           *((volatile uint16_t*)(0x40025600UL))
#define FM4_BT12_RT_PCSR                          *((volatile uint16_t*)(0x40025600UL))
#define FM_BT12_PPG_PRLH                          *((volatile uint16_t*)(0x40025604UL))
#define FM4_BT12_PPG_PRLH                         *((volatile uint16_t*)(0x40025604UL))
#define FM_BT12_PWC_DTBF                          *((volatile uint16_t*)(0x40025604UL))
#define FM4_BT12_PWC_DTBF                         *((volatile uint16_t*)(0x40025604UL))
#define FM_BT12_PWM_PDUT                          *((volatile uint16_t*)(0x40025604UL))
#define FM4_BT12_PWM_PDUT                         *((volatile uint16_t*)(0x40025604UL))
#define FM_BT12_PPG_TMR                           *((volatile uint16_t*)(0x40025608UL))
#define FM4_BT12_PPG_TMR                          *((volatile uint16_t*)(0x40025608UL))
#define FM_BT12_PWM_TMR                           *((volatile uint16_t*)(0x40025608UL))
#define FM4_BT12_PWM_TMR                          *((volatile uint16_t*)(0x40025608UL))
#define FM_BT12_RT_TMR                            *((volatile uint16_t*)(0x40025608UL))
#define FM4_BT12_RT_TMR                           *((volatile uint16_t*)(0x40025608UL))
#define FM_BT12_PPG_TMCR                          *((volatile uint16_t*)(0x4002560CUL))
#define FM4_BT12_PPG_TMCR                         *((volatile uint16_t*)(0x4002560CUL))
#define FM_BT12_PWC_TMCR                          *((volatile uint16_t*)(0x4002560CUL))
#define FM4_BT12_PWC_TMCR                         *((volatile uint16_t*)(0x4002560CUL))
#define FM_BT12_PWM_TMCR                          *((volatile uint16_t*)(0x4002560CUL))
#define FM4_BT12_PWM_TMCR                         *((volatile uint16_t*)(0x4002560CUL))
#define FM_BT12_RT_TMCR                           *((volatile uint16_t*)(0x4002560CUL))
#define FM4_BT12_RT_TMCR                          *((volatile uint16_t*)(0x4002560CUL))
#define FM_BT12_PPG_STC                           *((volatile  uint8_t*)(0x40025610UL))
#define FM4_BT12_PPG_STC                          *((volatile  uint8_t*)(0x40025610UL))
#define FM_BT12_PWC_STC                           *((volatile  uint8_t*)(0x40025610UL))
#define FM4_BT12_PWC_STC                          *((volatile  uint8_t*)(0x40025610UL))
#define FM_BT12_PWM_STC                           *((volatile  uint8_t*)(0x40025610UL))
#define FM4_BT12_PWM_STC                          *((volatile  uint8_t*)(0x40025610UL))
#define FM_BT12_RT_STC                            *((volatile  uint8_t*)(0x40025610UL))
#define FM4_BT12_RT_STC                           *((volatile  uint8_t*)(0x40025610UL))
#define FM_BT12_PPG_TMCR2                         *((volatile  uint8_t*)(0x40025611UL))
#define FM4_BT12_PPG_TMCR2                        *((volatile  uint8_t*)(0x40025611UL))
#define FM_BT12_PWC_TMCR2                         *((volatile  uint8_t*)(0x40025611UL))
#define FM4_BT12_PWC_TMCR2                        *((volatile  uint8_t*)(0x40025611UL))
#define FM_BT12_PWM_TMCR2                         *((volatile  uint8_t*)(0x40025611UL))
#define FM4_BT12_PWM_TMCR2                        *((volatile  uint8_t*)(0x40025611UL))
#define FM_BT12_RT_TMCR2                          *((volatile  uint8_t*)(0x40025611UL))
#define FM4_BT12_RT_TMCR2                         *((volatile  uint8_t*)(0x40025611UL))

/*******************************************************************************
* BT Registers BT13
*   Register Definition
*******************************************************************************/
#define FM_BT13_PPG_PRLL                          *((volatile uint16_t*)(0x40025640UL))
#define FM4_BT13_PPG_PRLL                         *((volatile uint16_t*)(0x40025640UL))
#define FM_BT13_PWM_PCSR                          *((volatile uint16_t*)(0x40025640UL))
#define FM4_BT13_PWM_PCSR                         *((volatile uint16_t*)(0x40025640UL))
#define FM_BT13_RT_PCSR                           *((volatile uint16_t*)(0x40025640UL))
#define FM4_BT13_RT_PCSR                          *((volatile uint16_t*)(0x40025640UL))
#define FM_BT13_PPG_PRLH                          *((volatile uint16_t*)(0x40025644UL))
#define FM4_BT13_PPG_PRLH                         *((volatile uint16_t*)(0x40025644UL))
#define FM_BT13_PWC_DTBF                          *((volatile uint16_t*)(0x40025644UL))
#define FM4_BT13_PWC_DTBF                         *((volatile uint16_t*)(0x40025644UL))
#define FM_BT13_PWM_PDUT                          *((volatile uint16_t*)(0x40025644UL))
#define FM4_BT13_PWM_PDUT                         *((volatile uint16_t*)(0x40025644UL))
#define FM_BT13_PPG_TMR                           *((volatile uint16_t*)(0x40025648UL))
#define FM4_BT13_PPG_TMR                          *((volatile uint16_t*)(0x40025648UL))
#define FM_BT13_PWM_TMR                           *((volatile uint16_t*)(0x40025648UL))
#define FM4_BT13_PWM_TMR                          *((volatile uint16_t*)(0x40025648UL))
#define FM_BT13_RT_TMR                            *((volatile uint16_t*)(0x40025648UL))
#define FM4_BT13_RT_TMR                           *((volatile uint16_t*)(0x40025648UL))
#define FM_BT13_PPG_TMCR                          *((volatile uint16_t*)(0x4002564CUL))
#define FM4_BT13_PPG_TMCR                         *((volatile uint16_t*)(0x4002564CUL))
#define FM_BT13_PWC_TMCR                          *((volatile uint16_t*)(0x4002564CUL))
#define FM4_BT13_PWC_TMCR                         *((volatile uint16_t*)(0x4002564CUL))
#define FM_BT13_PWM_TMCR                          *((volatile uint16_t*)(0x4002564CUL))
#define FM4_BT13_PWM_TMCR                         *((volatile uint16_t*)(0x4002564CUL))
#define FM_BT13_RT_TMCR                           *((volatile uint16_t*)(0x4002564CUL))
#define FM4_BT13_RT_TMCR                          *((volatile uint16_t*)(0x4002564CUL))
#define FM_BT13_PPG_STC                           *((volatile  uint8_t*)(0x40025650UL))
#define FM4_BT13_PPG_STC                          *((volatile  uint8_t*)(0x40025650UL))
#define FM_BT13_PWC_STC                           *((volatile  uint8_t*)(0x40025650UL))
#define FM4_BT13_PWC_STC                          *((volatile  uint8_t*)(0x40025650UL))
#define FM_BT13_PWM_STC                           *((volatile  uint8_t*)(0x40025650UL))
#define FM4_BT13_PWM_STC                          *((volatile  uint8_t*)(0x40025650UL))
#define FM_BT13_RT_STC                            *((volatile  uint8_t*)(0x40025650UL))
#define FM4_BT13_RT_STC                           *((volatile  uint8_t*)(0x40025650UL))
#define FM_BT13_PPG_TMCR2                         *((volatile  uint8_t*)(0x40025651UL))
#define FM4_BT13_PPG_TMCR2                        *((volatile  uint8_t*)(0x40025651UL))
#define FM_BT13_PWC_TMCR2                         *((volatile  uint8_t*)(0x40025651UL))
#define FM4_BT13_PWC_TMCR2                        *((volatile  uint8_t*)(0x40025651UL))
#define FM_BT13_PWM_TMCR2                         *((volatile  uint8_t*)(0x40025651UL))
#define FM4_BT13_PWM_TMCR2                        *((volatile  uint8_t*)(0x40025651UL))
#define FM_BT13_RT_TMCR2                          *((volatile  uint8_t*)(0x40025651UL))
#define FM4_BT13_RT_TMCR2                         *((volatile  uint8_t*)(0x40025651UL))

/*******************************************************************************
* BT Registers BT14
*   Register Definition
*******************************************************************************/
#define FM_BT14_PPG_PRLL                          *((volatile uint16_t*)(0x40025680UL))
#define FM4_BT14_PPG_PRLL                         *((volatile uint16_t*)(0x40025680UL))
#define FM_BT14_PWM_PCSR                          *((volatile uint16_t*)(0x40025680UL))
#define FM4_BT14_PWM_PCSR                         *((volatile uint16_t*)(0x40025680UL))
#define FM_BT14_RT_PCSR                           *((volatile uint16_t*)(0x40025680UL))
#define FM4_BT14_RT_PCSR                          *((volatile uint16_t*)(0x40025680UL))
#define FM_BT14_PPG_PRLH                          *((volatile uint16_t*)(0x40025684UL))
#define FM4_BT14_PPG_PRLH                         *((volatile uint16_t*)(0x40025684UL))
#define FM_BT14_PWC_DTBF                          *((volatile uint16_t*)(0x40025684UL))
#define FM4_BT14_PWC_DTBF                         *((volatile uint16_t*)(0x40025684UL))
#define FM_BT14_PWM_PDUT                          *((volatile uint16_t*)(0x40025684UL))
#define FM4_BT14_PWM_PDUT                         *((volatile uint16_t*)(0x40025684UL))
#define FM_BT14_PPG_TMR                           *((volatile uint16_t*)(0x40025688UL))
#define FM4_BT14_PPG_TMR                          *((volatile uint16_t*)(0x40025688UL))
#define FM_BT14_PWM_TMR                           *((volatile uint16_t*)(0x40025688UL))
#define FM4_BT14_PWM_TMR                          *((volatile uint16_t*)(0x40025688UL))
#define FM_BT14_RT_TMR                            *((volatile uint16_t*)(0x40025688UL))
#define FM4_BT14_RT_TMR                           *((volatile uint16_t*)(0x40025688UL))
#define FM_BT14_PPG_TMCR                          *((volatile uint16_t*)(0x4002568CUL))
#define FM4_BT14_PPG_TMCR                         *((volatile uint16_t*)(0x4002568CUL))
#define FM_BT14_PWC_TMCR                          *((volatile uint16_t*)(0x4002568CUL))
#define FM4_BT14_PWC_TMCR                         *((volatile uint16_t*)(0x4002568CUL))
#define FM_BT14_PWM_TMCR                          *((volatile uint16_t*)(0x4002568CUL))
#define FM4_BT14_PWM_TMCR                         *((volatile uint16_t*)(0x4002568CUL))
#define FM_BT14_RT_TMCR                           *((volatile uint16_t*)(0x4002568CUL))
#define FM4_BT14_RT_TMCR                          *((volatile uint16_t*)(0x4002568CUL))
#define FM_BT14_PPG_STC                           *((volatile  uint8_t*)(0x40025690UL))
#define FM4_BT14_PPG_STC                          *((volatile  uint8_t*)(0x40025690UL))
#define FM_BT14_PWC_STC                           *((volatile  uint8_t*)(0x40025690UL))
#define FM4_BT14_PWC_STC                          *((volatile  uint8_t*)(0x40025690UL))
#define FM_BT14_PWM_STC                           *((volatile  uint8_t*)(0x40025690UL))
#define FM4_BT14_PWM_STC                          *((volatile  uint8_t*)(0x40025690UL))
#define FM_BT14_RT_STC                            *((volatile  uint8_t*)(0x40025690UL))
#define FM4_BT14_RT_STC                           *((volatile  uint8_t*)(0x40025690UL))
#define FM_BT14_PPG_TMCR2                         *((volatile  uint8_t*)(0x40025691UL))
#define FM4_BT14_PPG_TMCR2                        *((volatile  uint8_t*)(0x40025691UL))
#define FM_BT14_PWC_TMCR2                         *((volatile  uint8_t*)(0x40025691UL))
#define FM4_BT14_PWC_TMCR2                        *((volatile  uint8_t*)(0x40025691UL))
#define FM_BT14_PWM_TMCR2                         *((volatile  uint8_t*)(0x40025691UL))
#define FM4_BT14_PWM_TMCR2                        *((volatile  uint8_t*)(0x40025691UL))
#define FM_BT14_RT_TMCR2                          *((volatile  uint8_t*)(0x40025691UL))
#define FM4_BT14_RT_TMCR2                         *((volatile  uint8_t*)(0x40025691UL))

/*******************************************************************************
* BT Registers BT15
*   Register Definition
*******************************************************************************/
#define FM_BT15_PPG_PRLL                          *((volatile uint16_t*)(0x400256C0UL))
#define FM4_BT15_PPG_PRLL                         *((volatile uint16_t*)(0x400256C0UL))
#define FM_BT15_PWM_PCSR                          *((volatile uint16_t*)(0x400256C0UL))
#define FM4_BT15_PWM_PCSR                         *((volatile uint16_t*)(0x400256C0UL))
#define FM_BT15_RT_PCSR                           *((volatile uint16_t*)(0x400256C0UL))
#define FM4_BT15_RT_PCSR                          *((volatile uint16_t*)(0x400256C0UL))
#define FM_BT15_PPG_PRLH                          *((volatile uint16_t*)(0x400256C4UL))
#define FM4_BT15_PPG_PRLH                         *((volatile uint16_t*)(0x400256C4UL))
#define FM_BT15_PWC_DTBF                          *((volatile uint16_t*)(0x400256C4UL))
#define FM4_BT15_PWC_DTBF                         *((volatile uint16_t*)(0x400256C4UL))
#define FM_BT15_PWM_PDUT                          *((volatile uint16_t*)(0x400256C4UL))
#define FM4_BT15_PWM_PDUT                         *((volatile uint16_t*)(0x400256C4UL))
#define FM_BT15_PPG_TMR                           *((volatile uint16_t*)(0x400256C8UL))
#define FM4_BT15_PPG_TMR                          *((volatile uint16_t*)(0x400256C8UL))
#define FM_BT15_PWM_TMR                           *((volatile uint16_t*)(0x400256C8UL))
#define FM4_BT15_PWM_TMR                          *((volatile uint16_t*)(0x400256C8UL))
#define FM_BT15_RT_TMR                            *((volatile uint16_t*)(0x400256C8UL))
#define FM4_BT15_RT_TMR                           *((volatile uint16_t*)(0x400256C8UL))
#define FM_BT15_PPG_TMCR                          *((volatile uint16_t*)(0x400256CCUL))
#define FM4_BT15_PPG_TMCR                         *((volatile uint16_t*)(0x400256CCUL))
#define FM_BT15_PWC_TMCR                          *((volatile uint16_t*)(0x400256CCUL))
#define FM4_BT15_PWC_TMCR                         *((volatile uint16_t*)(0x400256CCUL))
#define FM_BT15_PWM_TMCR                          *((volatile uint16_t*)(0x400256CCUL))
#define FM4_BT15_PWM_TMCR                         *((volatile uint16_t*)(0x400256CCUL))
#define FM_BT15_RT_TMCR                           *((volatile uint16_t*)(0x400256CCUL))
#define FM4_BT15_RT_TMCR                          *((volatile uint16_t*)(0x400256CCUL))
#define FM_BT15_PPG_STC                           *((volatile  uint8_t*)(0x400256D0UL))
#define FM4_BT15_PPG_STC                          *((volatile  uint8_t*)(0x400256D0UL))
#define FM_BT15_PWC_STC                           *((volatile  uint8_t*)(0x400256D0UL))
#define FM4_BT15_PWC_STC                          *((volatile  uint8_t*)(0x400256D0UL))
#define FM_BT15_PWM_STC                           *((volatile  uint8_t*)(0x400256D0UL))
#define FM4_BT15_PWM_STC                          *((volatile  uint8_t*)(0x400256D0UL))
#define FM_BT15_RT_STC                            *((volatile  uint8_t*)(0x400256D0UL))
#define FM4_BT15_RT_STC                           *((volatile  uint8_t*)(0x400256D0UL))
#define FM_BT15_PPG_TMCR2                         *((volatile  uint8_t*)(0x400256D1UL))
#define FM4_BT15_PPG_TMCR2                        *((volatile  uint8_t*)(0x400256D1UL))
#define FM_BT15_PWC_TMCR2                         *((volatile  uint8_t*)(0x400256D1UL))
#define FM4_BT15_PWC_TMCR2                        *((volatile  uint8_t*)(0x400256D1UL))
#define FM_BT15_PWM_TMCR2                         *((volatile  uint8_t*)(0x400256D1UL))
#define FM4_BT15_PWM_TMCR2                        *((volatile  uint8_t*)(0x400256D1UL))
#define FM_BT15_RT_TMCR2                          *((volatile  uint8_t*)(0x400256D1UL))
#define FM4_BT15_RT_TMCR2                         *((volatile  uint8_t*)(0x400256D1UL))

/*******************************************************************************
* BT Registers BT2
*   Register Definition
*******************************************************************************/
#define FM_BT2_PPG_PRLL                           *((volatile uint16_t*)(0x40025080UL))
#define FM4_BT2_PPG_PRLL                          *((volatile uint16_t*)(0x40025080UL))
#define FM_BT2_PWM_PCSR                           *((volatile uint16_t*)(0x40025080UL))
#define FM4_BT2_PWM_PCSR                          *((volatile uint16_t*)(0x40025080UL))
#define FM_BT2_RT_PCSR                            *((volatile uint16_t*)(0x40025080UL))
#define FM4_BT2_RT_PCSR                           *((volatile uint16_t*)(0x40025080UL))
#define FM_BT2_PPG_PRLH                           *((volatile uint16_t*)(0x40025084UL))
#define FM4_BT2_PPG_PRLH                          *((volatile uint16_t*)(0x40025084UL))
#define FM_BT2_PWC_DTBF                           *((volatile uint16_t*)(0x40025084UL))
#define FM4_BT2_PWC_DTBF                          *((volatile uint16_t*)(0x40025084UL))
#define FM_BT2_PWM_PDUT                           *((volatile uint16_t*)(0x40025084UL))
#define FM4_BT2_PWM_PDUT                          *((volatile uint16_t*)(0x40025084UL))
#define FM_BT2_PPG_TMR                            *((volatile uint16_t*)(0x40025088UL))
#define FM4_BT2_PPG_TMR                           *((volatile uint16_t*)(0x40025088UL))
#define FM_BT2_PWM_TMR                            *((volatile uint16_t*)(0x40025088UL))
#define FM4_BT2_PWM_TMR                           *((volatile uint16_t*)(0x40025088UL))
#define FM_BT2_RT_TMR                             *((volatile uint16_t*)(0x40025088UL))
#define FM4_BT2_RT_TMR                            *((volatile uint16_t*)(0x40025088UL))
#define FM_BT2_PPG_TMCR                           *((volatile uint16_t*)(0x4002508CUL))
#define FM4_BT2_PPG_TMCR                          *((volatile uint16_t*)(0x4002508CUL))
#define FM_BT2_PWC_TMCR                           *((volatile uint16_t*)(0x4002508CUL))
#define FM4_BT2_PWC_TMCR                          *((volatile uint16_t*)(0x4002508CUL))
#define FM_BT2_PWM_TMCR                           *((volatile uint16_t*)(0x4002508CUL))
#define FM4_BT2_PWM_TMCR                          *((volatile uint16_t*)(0x4002508CUL))
#define FM_BT2_RT_TMCR                            *((volatile uint16_t*)(0x4002508CUL))
#define FM4_BT2_RT_TMCR                           *((volatile uint16_t*)(0x4002508CUL))
#define FM_BT2_PPG_STC                            *((volatile  uint8_t*)(0x40025090UL))
#define FM4_BT2_PPG_STC                           *((volatile  uint8_t*)(0x40025090UL))
#define FM_BT2_PWC_STC                            *((volatile  uint8_t*)(0x40025090UL))
#define FM4_BT2_PWC_STC                           *((volatile  uint8_t*)(0x40025090UL))
#define FM_BT2_PWM_STC                            *((volatile  uint8_t*)(0x40025090UL))
#define FM4_BT2_PWM_STC                           *((volatile  uint8_t*)(0x40025090UL))
#define FM_BT2_RT_STC                             *((volatile  uint8_t*)(0x40025090UL))
#define FM4_BT2_RT_STC                            *((volatile  uint8_t*)(0x40025090UL))
#define FM_BT2_PPG_TMCR2                          *((volatile  uint8_t*)(0x40025091UL))
#define FM4_BT2_PPG_TMCR2                         *((volatile  uint8_t*)(0x40025091UL))
#define FM_BT2_PWC_TMCR2                          *((volatile  uint8_t*)(0x40025091UL))
#define FM4_BT2_PWC_TMCR2                         *((volatile  uint8_t*)(0x40025091UL))
#define FM_BT2_PWM_TMCR2                          *((volatile  uint8_t*)(0x40025091UL))
#define FM4_BT2_PWM_TMCR2                         *((volatile  uint8_t*)(0x40025091UL))
#define FM_BT2_RT_TMCR2                           *((volatile  uint8_t*)(0x40025091UL))
#define FM4_BT2_RT_TMCR2                          *((volatile  uint8_t*)(0x40025091UL))

/*******************************************************************************
* BT Registers BT3
*   Register Definition
*******************************************************************************/
#define FM_BT3_PPG_PRLL                           *((volatile uint16_t*)(0x400250C0UL))
#define FM4_BT3_PPG_PRLL                          *((volatile uint16_t*)(0x400250C0UL))
#define FM_BT3_PWM_PCSR                           *((volatile uint16_t*)(0x400250C0UL))
#define FM4_BT3_PWM_PCSR                          *((volatile uint16_t*)(0x400250C0UL))
#define FM_BT3_RT_PCSR                            *((volatile uint16_t*)(0x400250C0UL))
#define FM4_BT3_RT_PCSR                           *((volatile uint16_t*)(0x400250C0UL))
#define FM_BT3_PPG_PRLH                           *((volatile uint16_t*)(0x400250C4UL))
#define FM4_BT3_PPG_PRLH                          *((volatile uint16_t*)(0x400250C4UL))
#define FM_BT3_PWC_DTBF                           *((volatile uint16_t*)(0x400250C4UL))
#define FM4_BT3_PWC_DTBF                          *((volatile uint16_t*)(0x400250C4UL))
#define FM_BT3_PWM_PDUT                           *((volatile uint16_t*)(0x400250C4UL))
#define FM4_BT3_PWM_PDUT                          *((volatile uint16_t*)(0x400250C4UL))
#define FM_BT3_PPG_TMR                            *((volatile uint16_t*)(0x400250C8UL))
#define FM4_BT3_PPG_TMR                           *((volatile uint16_t*)(0x400250C8UL))
#define FM_BT3_PWM_TMR                            *((volatile uint16_t*)(0x400250C8UL))
#define FM4_BT3_PWM_TMR                           *((volatile uint16_t*)(0x400250C8UL))
#define FM_BT3_RT_TMR                             *((volatile uint16_t*)(0x400250C8UL))
#define FM4_BT3_RT_TMR                            *((volatile uint16_t*)(0x400250C8UL))
#define FM_BT3_PPG_TMCR                           *((volatile uint16_t*)(0x400250CCUL))
#define FM4_BT3_PPG_TMCR                          *((volatile uint16_t*)(0x400250CCUL))
#define FM_BT3_PWC_TMCR                           *((volatile uint16_t*)(0x400250CCUL))
#define FM4_BT3_PWC_TMCR                          *((volatile uint16_t*)(0x400250CCUL))
#define FM_BT3_PWM_TMCR                           *((volatile uint16_t*)(0x400250CCUL))
#define FM4_BT3_PWM_TMCR                          *((volatile uint16_t*)(0x400250CCUL))
#define FM_BT3_RT_TMCR                            *((volatile uint16_t*)(0x400250CCUL))
#define FM4_BT3_RT_TMCR                           *((volatile uint16_t*)(0x400250CCUL))
#define FM_BT3_PPG_STC                            *((volatile  uint8_t*)(0x400250D0UL))
#define FM4_BT3_PPG_STC                           *((volatile  uint8_t*)(0x400250D0UL))
#define FM_BT3_PWC_STC                            *((volatile  uint8_t*)(0x400250D0UL))
#define FM4_BT3_PWC_STC                           *((volatile  uint8_t*)(0x400250D0UL))
#define FM_BT3_PWM_STC                            *((volatile  uint8_t*)(0x400250D0UL))
#define FM4_BT3_PWM_STC                           *((volatile  uint8_t*)(0x400250D0UL))
#define FM_BT3_RT_STC                             *((volatile  uint8_t*)(0x400250D0UL))
#define FM4_BT3_RT_STC                            *((volatile  uint8_t*)(0x400250D0UL))
#define FM_BT3_PPG_TMCR2                          *((volatile  uint8_t*)(0x400250D1UL))
#define FM4_BT3_PPG_TMCR2                         *((volatile  uint8_t*)(0x400250D1UL))
#define FM_BT3_PWC_TMCR2                          *((volatile  uint8_t*)(0x400250D1UL))
#define FM4_BT3_PWC_TMCR2                         *((volatile  uint8_t*)(0x400250D1UL))
#define FM_BT3_PWM_TMCR2                          *((volatile  uint8_t*)(0x400250D1UL))
#define FM4_BT3_PWM_TMCR2                         *((volatile  uint8_t*)(0x400250D1UL))
#define FM_BT3_RT_TMCR2                           *((volatile  uint8_t*)(0x400250D1UL))
#define FM4_BT3_RT_TMCR2                          *((volatile  uint8_t*)(0x400250D1UL))

/*******************************************************************************
* BT Registers BT4
*   Register Definition
*******************************************************************************/
#define FM_BT4_PPG_PRLL                           *((volatile uint16_t*)(0x40025200UL))
#define FM4_BT4_PPG_PRLL                          *((volatile uint16_t*)(0x40025200UL))
#define FM_BT4_PWM_PCSR                           *((volatile uint16_t*)(0x40025200UL))
#define FM4_BT4_PWM_PCSR                          *((volatile uint16_t*)(0x40025200UL))
#define FM_BT4_RT_PCSR                            *((volatile uint16_t*)(0x40025200UL))
#define FM4_BT4_RT_PCSR                           *((volatile uint16_t*)(0x40025200UL))
#define FM_BT4_PPG_PRLH                           *((volatile uint16_t*)(0x40025204UL))
#define FM4_BT4_PPG_PRLH                          *((volatile uint16_t*)(0x40025204UL))
#define FM_BT4_PWC_DTBF                           *((volatile uint16_t*)(0x40025204UL))
#define FM4_BT4_PWC_DTBF                          *((volatile uint16_t*)(0x40025204UL))
#define FM_BT4_PWM_PDUT                           *((volatile uint16_t*)(0x40025204UL))
#define FM4_BT4_PWM_PDUT                          *((volatile uint16_t*)(0x40025204UL))
#define FM_BT4_PPG_TMR                            *((volatile uint16_t*)(0x40025208UL))
#define FM4_BT4_PPG_TMR                           *((volatile uint16_t*)(0x40025208UL))
#define FM_BT4_PWM_TMR                            *((volatile uint16_t*)(0x40025208UL))
#define FM4_BT4_PWM_TMR                           *((volatile uint16_t*)(0x40025208UL))
#define FM_BT4_RT_TMR                             *((volatile uint16_t*)(0x40025208UL))
#define FM4_BT4_RT_TMR                            *((volatile uint16_t*)(0x40025208UL))
#define FM_BT4_PPG_TMCR                           *((volatile uint16_t*)(0x4002520CUL))
#define FM4_BT4_PPG_TMCR                          *((volatile uint16_t*)(0x4002520CUL))
#define FM_BT4_PWC_TMCR                           *((volatile uint16_t*)(0x4002520CUL))
#define FM4_BT4_PWC_TMCR                          *((volatile uint16_t*)(0x4002520CUL))
#define FM_BT4_PWM_TMCR                           *((volatile uint16_t*)(0x4002520CUL))
#define FM4_BT4_PWM_TMCR                          *((volatile uint16_t*)(0x4002520CUL))
#define FM_BT4_RT_TMCR                            *((volatile uint16_t*)(0x4002520CUL))
#define FM4_BT4_RT_TMCR                           *((volatile uint16_t*)(0x4002520CUL))
#define FM_BT4_PPG_STC                            *((volatile  uint8_t*)(0x40025210UL))
#define FM4_BT4_PPG_STC                           *((volatile  uint8_t*)(0x40025210UL))
#define FM_BT4_PWC_STC                            *((volatile  uint8_t*)(0x40025210UL))
#define FM4_BT4_PWC_STC                           *((volatile  uint8_t*)(0x40025210UL))
#define FM_BT4_PWM_STC                            *((volatile  uint8_t*)(0x40025210UL))
#define FM4_BT4_PWM_STC                           *((volatile  uint8_t*)(0x40025210UL))
#define FM_BT4_RT_STC                             *((volatile  uint8_t*)(0x40025210UL))
#define FM4_BT4_RT_STC                            *((volatile  uint8_t*)(0x40025210UL))
#define FM_BT4_PPG_TMCR2                          *((volatile  uint8_t*)(0x40025211UL))
#define FM4_BT4_PPG_TMCR2                         *((volatile  uint8_t*)(0x40025211UL))
#define FM_BT4_PWC_TMCR2                          *((volatile  uint8_t*)(0x40025211UL))
#define FM4_BT4_PWC_TMCR2                         *((volatile  uint8_t*)(0x40025211UL))
#define FM_BT4_PWM_TMCR2                          *((volatile  uint8_t*)(0x40025211UL))
#define FM4_BT4_PWM_TMCR2                         *((volatile  uint8_t*)(0x40025211UL))
#define FM_BT4_RT_TMCR2                           *((volatile  uint8_t*)(0x40025211UL))
#define FM4_BT4_RT_TMCR2                          *((volatile  uint8_t*)(0x40025211UL))

/*******************************************************************************
* BT Registers BT5
*   Register Definition
*******************************************************************************/
#define FM_BT5_PPG_PRLL                           *((volatile uint16_t*)(0x40025240UL))
#define FM4_BT5_PPG_PRLL                          *((volatile uint16_t*)(0x40025240UL))
#define FM_BT5_PWM_PCSR                           *((volatile uint16_t*)(0x40025240UL))
#define FM4_BT5_PWM_PCSR                          *((volatile uint16_t*)(0x40025240UL))
#define FM_BT5_RT_PCSR                            *((volatile uint16_t*)(0x40025240UL))
#define FM4_BT5_RT_PCSR                           *((volatile uint16_t*)(0x40025240UL))
#define FM_BT5_PPG_PRLH                           *((volatile uint16_t*)(0x40025244UL))
#define FM4_BT5_PPG_PRLH                          *((volatile uint16_t*)(0x40025244UL))
#define FM_BT5_PWC_DTBF                           *((volatile uint16_t*)(0x40025244UL))
#define FM4_BT5_PWC_DTBF                          *((volatile uint16_t*)(0x40025244UL))
#define FM_BT5_PWM_PDUT                           *((volatile uint16_t*)(0x40025244UL))
#define FM4_BT5_PWM_PDUT                          *((volatile uint16_t*)(0x40025244UL))
#define FM_BT5_PPG_TMR                            *((volatile uint16_t*)(0x40025248UL))
#define FM4_BT5_PPG_TMR                           *((volatile uint16_t*)(0x40025248UL))
#define FM_BT5_PWM_TMR                            *((volatile uint16_t*)(0x40025248UL))
#define FM4_BT5_PWM_TMR                           *((volatile uint16_t*)(0x40025248UL))
#define FM_BT5_RT_TMR                             *((volatile uint16_t*)(0x40025248UL))
#define FM4_BT5_RT_TMR                            *((volatile uint16_t*)(0x40025248UL))
#define FM_BT5_PPG_TMCR                           *((volatile uint16_t*)(0x4002524CUL))
#define FM4_BT5_PPG_TMCR                          *((volatile uint16_t*)(0x4002524CUL))
#define FM_BT5_PWC_TMCR                           *((volatile uint16_t*)(0x4002524CUL))
#define FM4_BT5_PWC_TMCR                          *((volatile uint16_t*)(0x4002524CUL))
#define FM_BT5_PWM_TMCR                           *((volatile uint16_t*)(0x4002524CUL))
#define FM4_BT5_PWM_TMCR                          *((volatile uint16_t*)(0x4002524CUL))
#define FM_BT5_RT_TMCR                            *((volatile uint16_t*)(0x4002524CUL))
#define FM4_BT5_RT_TMCR                           *((volatile uint16_t*)(0x4002524CUL))
#define FM_BT5_PPG_STC                            *((volatile  uint8_t*)(0x40025250UL))
#define FM4_BT5_PPG_STC                           *((volatile  uint8_t*)(0x40025250UL))
#define FM_BT5_PWC_STC                            *((volatile  uint8_t*)(0x40025250UL))
#define FM4_BT5_PWC_STC                           *((volatile  uint8_t*)(0x40025250UL))
#define FM_BT5_PWM_STC                            *((volatile  uint8_t*)(0x40025250UL))
#define FM4_BT5_PWM_STC                           *((volatile  uint8_t*)(0x40025250UL))
#define FM_BT5_RT_STC                             *((volatile  uint8_t*)(0x40025250UL))
#define FM4_BT5_RT_STC                            *((volatile  uint8_t*)(0x40025250UL))
#define FM_BT5_PPG_TMCR2                          *((volatile  uint8_t*)(0x40025251UL))
#define FM4_BT5_PPG_TMCR2                         *((volatile  uint8_t*)(0x40025251UL))
#define FM_BT5_PWC_TMCR2                          *((volatile  uint8_t*)(0x40025251UL))
#define FM4_BT5_PWC_TMCR2                         *((volatile  uint8_t*)(0x40025251UL))
#define FM_BT5_PWM_TMCR2                          *((volatile  uint8_t*)(0x40025251UL))
#define FM4_BT5_PWM_TMCR2                         *((volatile  uint8_t*)(0x40025251UL))
#define FM_BT5_RT_TMCR2                           *((volatile  uint8_t*)(0x40025251UL))
#define FM4_BT5_RT_TMCR2                          *((volatile  uint8_t*)(0x40025251UL))

/*******************************************************************************
* BT Registers BT6
*   Register Definition
*******************************************************************************/
#define FM_BT6_PPG_PRLL                           *((volatile uint16_t*)(0x40025280UL))
#define FM4_BT6_PPG_PRLL                          *((volatile uint16_t*)(0x40025280UL))
#define FM_BT6_PWM_PCSR                           *((volatile uint16_t*)(0x40025280UL))
#define FM4_BT6_PWM_PCSR                          *((volatile uint16_t*)(0x40025280UL))
#define FM_BT6_RT_PCSR                            *((volatile uint16_t*)(0x40025280UL))
#define FM4_BT6_RT_PCSR                           *((volatile uint16_t*)(0x40025280UL))
#define FM_BT6_PPG_PRLH                           *((volatile uint16_t*)(0x40025284UL))
#define FM4_BT6_PPG_PRLH                          *((volatile uint16_t*)(0x40025284UL))
#define FM_BT6_PWC_DTBF                           *((volatile uint16_t*)(0x40025284UL))
#define FM4_BT6_PWC_DTBF                          *((volatile uint16_t*)(0x40025284UL))
#define FM_BT6_PWM_PDUT                           *((volatile uint16_t*)(0x40025284UL))
#define FM4_BT6_PWM_PDUT                          *((volatile uint16_t*)(0x40025284UL))
#define FM_BT6_PPG_TMR                            *((volatile uint16_t*)(0x40025288UL))
#define FM4_BT6_PPG_TMR                           *((volatile uint16_t*)(0x40025288UL))
#define FM_BT6_PWM_TMR                            *((volatile uint16_t*)(0x40025288UL))
#define FM4_BT6_PWM_TMR                           *((volatile uint16_t*)(0x40025288UL))
#define FM_BT6_RT_TMR                             *((volatile uint16_t*)(0x40025288UL))
#define FM4_BT6_RT_TMR                            *((volatile uint16_t*)(0x40025288UL))
#define FM_BT6_PPG_TMCR                           *((volatile uint16_t*)(0x4002528CUL))
#define FM4_BT6_PPG_TMCR                          *((volatile uint16_t*)(0x4002528CUL))
#define FM_BT6_PWC_TMCR                           *((volatile uint16_t*)(0x4002528CUL))
#define FM4_BT6_PWC_TMCR                          *((volatile uint16_t*)(0x4002528CUL))
#define FM_BT6_PWM_TMCR                           *((volatile uint16_t*)(0x4002528CUL))
#define FM4_BT6_PWM_TMCR                          *((volatile uint16_t*)(0x4002528CUL))
#define FM_BT6_RT_TMCR                            *((volatile uint16_t*)(0x4002528CUL))
#define FM4_BT6_RT_TMCR                           *((volatile uint16_t*)(0x4002528CUL))
#define FM_BT6_PPG_STC                            *((volatile  uint8_t*)(0x40025290UL))
#define FM4_BT6_PPG_STC                           *((volatile  uint8_t*)(0x40025290UL))
#define FM_BT6_PWC_STC                            *((volatile  uint8_t*)(0x40025290UL))
#define FM4_BT6_PWC_STC                           *((volatile  uint8_t*)(0x40025290UL))
#define FM_BT6_PWM_STC                            *((volatile  uint8_t*)(0x40025290UL))
#define FM4_BT6_PWM_STC                           *((volatile  uint8_t*)(0x40025290UL))
#define FM_BT6_RT_STC                             *((volatile  uint8_t*)(0x40025290UL))
#define FM4_BT6_RT_STC                            *((volatile  uint8_t*)(0x40025290UL))
#define FM_BT6_PPG_TMCR2                          *((volatile  uint8_t*)(0x40025291UL))
#define FM4_BT6_PPG_TMCR2                         *((volatile  uint8_t*)(0x40025291UL))
#define FM_BT6_PWC_TMCR2                          *((volatile  uint8_t*)(0x40025291UL))
#define FM4_BT6_PWC_TMCR2                         *((volatile  uint8_t*)(0x40025291UL))
#define FM_BT6_PWM_TMCR2                          *((volatile  uint8_t*)(0x40025291UL))
#define FM4_BT6_PWM_TMCR2                         *((volatile  uint8_t*)(0x40025291UL))
#define FM_BT6_RT_TMCR2                           *((volatile  uint8_t*)(0x40025291UL))
#define FM4_BT6_RT_TMCR2                          *((volatile  uint8_t*)(0x40025291UL))

/*******************************************************************************
* BT Registers BT7
*   Register Definition
*******************************************************************************/
#define FM_BT7_PPG_PRLL                           *((volatile uint16_t*)(0x400252C0UL))
#define FM4_BT7_PPG_PRLL                          *((volatile uint16_t*)(0x400252C0UL))
#define FM_BT7_PWM_PCSR                           *((volatile uint16_t*)(0x400252C0UL))
#define FM4_BT7_PWM_PCSR                          *((volatile uint16_t*)(0x400252C0UL))
#define FM_BT7_RT_PCSR                            *((volatile uint16_t*)(0x400252C0UL))
#define FM4_BT7_RT_PCSR                           *((volatile uint16_t*)(0x400252C0UL))
#define FM_BT7_PPG_PRLH                           *((volatile uint16_t*)(0x400252C4UL))
#define FM4_BT7_PPG_PRLH                          *((volatile uint16_t*)(0x400252C4UL))
#define FM_BT7_PWC_DTBF                           *((volatile uint16_t*)(0x400252C4UL))
#define FM4_BT7_PWC_DTBF                          *((volatile uint16_t*)(0x400252C4UL))
#define FM_BT7_PWM_PDUT                           *((volatile uint16_t*)(0x400252C4UL))
#define FM4_BT7_PWM_PDUT                          *((volatile uint16_t*)(0x400252C4UL))
#define FM_BT7_PPG_TMR                            *((volatile uint16_t*)(0x400252C8UL))
#define FM4_BT7_PPG_TMR                           *((volatile uint16_t*)(0x400252C8UL))
#define FM_BT7_PWM_TMR                            *((volatile uint16_t*)(0x400252C8UL))
#define FM4_BT7_PWM_TMR                           *((volatile uint16_t*)(0x400252C8UL))
#define FM_BT7_RT_TMR                             *((volatile uint16_t*)(0x400252C8UL))
#define FM4_BT7_RT_TMR                            *((volatile uint16_t*)(0x400252C8UL))
#define FM_BT7_PPG_TMCR                           *((volatile uint16_t*)(0x400252CCUL))
#define FM4_BT7_PPG_TMCR                          *((volatile uint16_t*)(0x400252CCUL))
#define FM_BT7_PWC_TMCR                           *((volatile uint16_t*)(0x400252CCUL))
#define FM4_BT7_PWC_TMCR                          *((volatile uint16_t*)(0x400252CCUL))
#define FM_BT7_PWM_TMCR                           *((volatile uint16_t*)(0x400252CCUL))
#define FM4_BT7_PWM_TMCR                          *((volatile uint16_t*)(0x400252CCUL))
#define FM_BT7_RT_TMCR                            *((volatile uint16_t*)(0x400252CCUL))
#define FM4_BT7_RT_TMCR                           *((volatile uint16_t*)(0x400252CCUL))
#define FM_BT7_PPG_STC                            *((volatile  uint8_t*)(0x400252D0UL))
#define FM4_BT7_PPG_STC                           *((volatile  uint8_t*)(0x400252D0UL))
#define FM_BT7_PWC_STC                            *((volatile  uint8_t*)(0x400252D0UL))
#define FM4_BT7_PWC_STC                           *((volatile  uint8_t*)(0x400252D0UL))
#define FM_BT7_PWM_STC                            *((volatile  uint8_t*)(0x400252D0UL))
#define FM4_BT7_PWM_STC                           *((volatile  uint8_t*)(0x400252D0UL))
#define FM_BT7_RT_STC                             *((volatile  uint8_t*)(0x400252D0UL))
#define FM4_BT7_RT_STC                            *((volatile  uint8_t*)(0x400252D0UL))
#define FM_BT7_PPG_TMCR2                          *((volatile  uint8_t*)(0x400252D1UL))
#define FM4_BT7_PPG_TMCR2                         *((volatile  uint8_t*)(0x400252D1UL))
#define FM_BT7_PWC_TMCR2                          *((volatile  uint8_t*)(0x400252D1UL))
#define FM4_BT7_PWC_TMCR2                         *((volatile  uint8_t*)(0x400252D1UL))
#define FM_BT7_PWM_TMCR2                          *((volatile  uint8_t*)(0x400252D1UL))
#define FM4_BT7_PWM_TMCR2                         *((volatile  uint8_t*)(0x400252D1UL))
#define FM_BT7_RT_TMCR2                           *((volatile  uint8_t*)(0x400252D1UL))
#define FM4_BT7_RT_TMCR2                          *((volatile  uint8_t*)(0x400252D1UL))

/*******************************************************************************
* BT Registers BT8
*   Register Definition
*******************************************************************************/
#define FM_BT8_PPG_PRLL                           *((volatile uint16_t*)(0x40025400UL))
#define FM4_BT8_PPG_PRLL                          *((volatile uint16_t*)(0x40025400UL))
#define FM_BT8_PWM_PCSR                           *((volatile uint16_t*)(0x40025400UL))
#define FM4_BT8_PWM_PCSR                          *((volatile uint16_t*)(0x40025400UL))
#define FM_BT8_RT_PCSR                            *((volatile uint16_t*)(0x40025400UL))
#define FM4_BT8_RT_PCSR                           *((volatile uint16_t*)(0x40025400UL))
#define FM_BT8_PPG_PRLH                           *((volatile uint16_t*)(0x40025404UL))
#define FM4_BT8_PPG_PRLH                          *((volatile uint16_t*)(0x40025404UL))
#define FM_BT8_PWC_DTBF                           *((volatile uint16_t*)(0x40025404UL))
#define FM4_BT8_PWC_DTBF                          *((volatile uint16_t*)(0x40025404UL))
#define FM_BT8_PWM_PDUT                           *((volatile uint16_t*)(0x40025404UL))
#define FM4_BT8_PWM_PDUT                          *((volatile uint16_t*)(0x40025404UL))
#define FM_BT8_PPG_TMR                            *((volatile uint16_t*)(0x40025408UL))
#define FM4_BT8_PPG_TMR                           *((volatile uint16_t*)(0x40025408UL))
#define FM_BT8_PWM_TMR                            *((volatile uint16_t*)(0x40025408UL))
#define FM4_BT8_PWM_TMR                           *((volatile uint16_t*)(0x40025408UL))
#define FM_BT8_RT_TMR                             *((volatile uint16_t*)(0x40025408UL))
#define FM4_BT8_RT_TMR                            *((volatile uint16_t*)(0x40025408UL))
#define FM_BT8_PPG_TMCR                           *((volatile uint16_t*)(0x4002540CUL))
#define FM4_BT8_PPG_TMCR                          *((volatile uint16_t*)(0x4002540CUL))
#define FM_BT8_PWC_TMCR                           *((volatile uint16_t*)(0x4002540CUL))
#define FM4_BT8_PWC_TMCR                          *((volatile uint16_t*)(0x4002540CUL))
#define FM_BT8_PWM_TMCR                           *((volatile uint16_t*)(0x4002540CUL))
#define FM4_BT8_PWM_TMCR                          *((volatile uint16_t*)(0x4002540CUL))
#define FM_BT8_RT_TMCR                            *((volatile uint16_t*)(0x4002540CUL))
#define FM4_BT8_RT_TMCR                           *((volatile uint16_t*)(0x4002540CUL))
#define FM_BT8_PPG_STC                            *((volatile  uint8_t*)(0x40025410UL))
#define FM4_BT8_PPG_STC                           *((volatile  uint8_t*)(0x40025410UL))
#define FM_BT8_PWC_STC                            *((volatile  uint8_t*)(0x40025410UL))
#define FM4_BT8_PWC_STC                           *((volatile  uint8_t*)(0x40025410UL))
#define FM_BT8_PWM_STC                            *((volatile  uint8_t*)(0x40025410UL))
#define FM4_BT8_PWM_STC                           *((volatile  uint8_t*)(0x40025410UL))
#define FM_BT8_RT_STC                             *((volatile  uint8_t*)(0x40025410UL))
#define FM4_BT8_RT_STC                            *((volatile  uint8_t*)(0x40025410UL))
#define FM_BT8_PPG_TMCR2                          *((volatile  uint8_t*)(0x40025411UL))
#define FM4_BT8_PPG_TMCR2                         *((volatile  uint8_t*)(0x40025411UL))
#define FM_BT8_PWC_TMCR2                          *((volatile  uint8_t*)(0x40025411UL))
#define FM4_BT8_PWC_TMCR2                         *((volatile  uint8_t*)(0x40025411UL))
#define FM_BT8_PWM_TMCR2                          *((volatile  uint8_t*)(0x40025411UL))
#define FM4_BT8_PWM_TMCR2                         *((volatile  uint8_t*)(0x40025411UL))
#define FM_BT8_RT_TMCR2                           *((volatile  uint8_t*)(0x40025411UL))
#define FM4_BT8_RT_TMCR2                          *((volatile  uint8_t*)(0x40025411UL))

/*******************************************************************************
* BT Registers BT9
*   Register Definition
*******************************************************************************/
#define FM_BT9_PPG_PRLL                           *((volatile uint16_t*)(0x40025440UL))
#define FM4_BT9_PPG_PRLL                          *((volatile uint16_t*)(0x40025440UL))
#define FM_BT9_PWM_PCSR                           *((volatile uint16_t*)(0x40025440UL))
#define FM4_BT9_PWM_PCSR                          *((volatile uint16_t*)(0x40025440UL))
#define FM_BT9_RT_PCSR                            *((volatile uint16_t*)(0x40025440UL))
#define FM4_BT9_RT_PCSR                           *((volatile uint16_t*)(0x40025440UL))
#define FM_BT9_PPG_PRLH                           *((volatile uint16_t*)(0x40025444UL))
#define FM4_BT9_PPG_PRLH                          *((volatile uint16_t*)(0x40025444UL))
#define FM_BT9_PWC_DTBF                           *((volatile uint16_t*)(0x40025444UL))
#define FM4_BT9_PWC_DTBF                          *((volatile uint16_t*)(0x40025444UL))
#define FM_BT9_PWM_PDUT                           *((volatile uint16_t*)(0x40025444UL))
#define FM4_BT9_PWM_PDUT                          *((volatile uint16_t*)(0x40025444UL))
#define FM_BT9_PPG_TMR                            *((volatile uint16_t*)(0x40025448UL))
#define FM4_BT9_PPG_TMR                           *((volatile uint16_t*)(0x40025448UL))
#define FM_BT9_PWM_TMR                            *((volatile uint16_t*)(0x40025448UL))
#define FM4_BT9_PWM_TMR                           *((volatile uint16_t*)(0x40025448UL))
#define FM_BT9_RT_TMR                             *((volatile uint16_t*)(0x40025448UL))
#define FM4_BT9_RT_TMR                            *((volatile uint16_t*)(0x40025448UL))
#define FM_BT9_PPG_TMCR                           *((volatile uint16_t*)(0x4002544CUL))
#define FM4_BT9_PPG_TMCR                          *((volatile uint16_t*)(0x4002544CUL))
#define FM_BT9_PWC_TMCR                           *((volatile uint16_t*)(0x4002544CUL))
#define FM4_BT9_PWC_TMCR                          *((volatile uint16_t*)(0x4002544CUL))
#define FM_BT9_PWM_TMCR                           *((volatile uint16_t*)(0x4002544CUL))
#define FM4_BT9_PWM_TMCR                          *((volatile uint16_t*)(0x4002544CUL))
#define FM_BT9_RT_TMCR                            *((volatile uint16_t*)(0x4002544CUL))
#define FM4_BT9_RT_TMCR                           *((volatile uint16_t*)(0x4002544CUL))
#define FM_BT9_PPG_STC                            *((volatile  uint8_t*)(0x40025450UL))
#define FM4_BT9_PPG_STC                           *((volatile  uint8_t*)(0x40025450UL))
#define FM_BT9_PWC_STC                            *((volatile  uint8_t*)(0x40025450UL))
#define FM4_BT9_PWC_STC                           *((volatile  uint8_t*)(0x40025450UL))
#define FM_BT9_PWM_STC                            *((volatile  uint8_t*)(0x40025450UL))
#define FM4_BT9_PWM_STC                           *((volatile  uint8_t*)(0x40025450UL))
#define FM_BT9_RT_STC                             *((volatile  uint8_t*)(0x40025450UL))
#define FM4_BT9_RT_STC                            *((volatile  uint8_t*)(0x40025450UL))
#define FM_BT9_PPG_TMCR2                          *((volatile  uint8_t*)(0x40025451UL))
#define FM4_BT9_PPG_TMCR2                         *((volatile  uint8_t*)(0x40025451UL))
#define FM_BT9_PWC_TMCR2                          *((volatile  uint8_t*)(0x40025451UL))
#define FM4_BT9_PWC_TMCR2                         *((volatile  uint8_t*)(0x40025451UL))
#define FM_BT9_PWM_TMCR2                          *((volatile  uint8_t*)(0x40025451UL))
#define FM4_BT9_PWM_TMCR2                         *((volatile  uint8_t*)(0x40025451UL))
#define FM_BT9_RT_TMCR2                           *((volatile  uint8_t*)(0x40025451UL))
#define FM4_BT9_RT_TMCR2                          *((volatile  uint8_t*)(0x40025451UL))

/*******************************************************************************
* BTIOSEL03 Registers BTIOSEL03
*   Register Definition
*******************************************************************************/
#define FM_BTIOSEL03_BTSEL0123                    *((volatile  uint8_t*)(0x40025101UL))
#define FM4_BTIOSEL03_BTSEL0123                   *((volatile  uint8_t*)(0x40025101UL))

/*******************************************************************************
* BTIOSEL47 Registers BTIOSEL47
*   Register Definition
*******************************************************************************/
#define FM_BTIOSEL47_BTSEL4567                    *((volatile  uint8_t*)(0x40025301UL))
#define FM4_BTIOSEL47_BTSEL4567                   *((volatile  uint8_t*)(0x40025301UL))

/*******************************************************************************
* BTIOSEL8B Registers BTIOSEL8B
*   Register Definition
*******************************************************************************/
#define FM_BTIOSEL8B_BTSEL89AB                    *((volatile  uint8_t*)(0x40025501UL))
#define FM4_BTIOSEL8B_BTSEL89AB                   *((volatile  uint8_t*)(0x40025501UL))

/*******************************************************************************
* BTIOSELCF Registers BTIOSELCF
*   Register Definition
*******************************************************************************/
#define FM_BTIOSELCF_BTSELCDEF                    *((volatile  uint8_t*)(0x40025701UL))
#define FM4_BTIOSELCF_BTSELCDEF                   *((volatile  uint8_t*)(0x40025701UL))

/*******************************************************************************
* CAN Registers CAN0
*   Register Definition
*******************************************************************************/
#define FM_CAN0_CTRLR                             *((volatile uint16_t*)(0x40062000UL))
#define FM4_CAN0_CTRLR                            *((volatile uint16_t*)(0x40062000UL))
#define FM_CAN0_STATR                             *((volatile uint16_t*)(0x40062002UL))
#define FM4_CAN0_STATR                            *((volatile uint16_t*)(0x40062002UL))
#define FM_CAN0_ERRCNT                            *((volatile uint16_t*)(0x40062004UL))
#define FM4_CAN0_ERRCNT                           *((volatile uint16_t*)(0x40062004UL))
#define FM_CAN0_BTR                               *((volatile uint16_t*)(0x40062006UL))
#define FM4_CAN0_BTR                              *((volatile uint16_t*)(0x40062006UL))
#define FM_CAN0_INTR                              *((volatile uint16_t*)(0x40062008UL))
#define FM4_CAN0_INTR                             *((volatile uint16_t*)(0x40062008UL))
#define FM_CAN0_TESTR                             *((volatile uint16_t*)(0x4006200AUL))
#define FM4_CAN0_TESTR                            *((volatile uint16_t*)(0x4006200AUL))
#define FM_CAN0_BRPER                             *((volatile uint16_t*)(0x4006200CUL))
#define FM4_CAN0_BRPER                            *((volatile uint16_t*)(0x4006200CUL))
#define FM_CAN0_IF1CREQ                           *((volatile uint16_t*)(0x40062010UL))
#define FM4_CAN0_IF1CREQ                          *((volatile uint16_t*)(0x40062010UL))
#define FM_CAN0_IF1CMSK                           *((volatile uint16_t*)(0x40062012UL))
#define FM4_CAN0_IF1CMSK                          *((volatile uint16_t*)(0x40062012UL))
#define FM_CAN0_IF1MSK                            *((volatile uint32_t*)(0x40062014UL))
#define FM4_CAN0_IF1MSK                           *((volatile uint32_t*)(0x40062014UL))
#define FM_CAN0_IF1ARB                            *((volatile uint32_t*)(0x40062018UL))
#define FM4_CAN0_IF1ARB                           *((volatile uint32_t*)(0x40062018UL))
#define FM_CAN0_IF1MCTR                           *((volatile uint16_t*)(0x4006201CUL))
#define FM4_CAN0_IF1MCTR                          *((volatile uint16_t*)(0x4006201CUL))
#define FM_CAN0_IF1DTA_L                          *((volatile uint32_t*)(0x40062020UL))
#define FM4_CAN0_IF1DTA_L                         *((volatile uint32_t*)(0x40062020UL))
#define FM_CAN0_IF1DTB_L                          *((volatile uint32_t*)(0x40062024UL))
#define FM4_CAN0_IF1DTB_L                         *((volatile uint32_t*)(0x40062024UL))
#define FM_CAN0_IF1DTA_B                          *((volatile uint32_t*)(0x40062030UL))
#define FM4_CAN0_IF1DTA_B                         *((volatile uint32_t*)(0x40062030UL))
#define FM_CAN0_IF1DTB_B                          *((volatile uint32_t*)(0x40062034UL))
#define FM4_CAN0_IF1DTB_B                         *((volatile uint32_t*)(0x40062034UL))
#define FM_CAN0_IF2CREQ                           *((volatile uint16_t*)(0x40062040UL))
#define FM4_CAN0_IF2CREQ                          *((volatile uint16_t*)(0x40062040UL))
#define FM_CAN0_IF2CMSK                           *((volatile uint16_t*)(0x40062042UL))
#define FM4_CAN0_IF2CMSK                          *((volatile uint16_t*)(0x40062042UL))
#define FM_CAN0_IF2MSK                            *((volatile uint32_t*)(0x40062044UL))
#define FM4_CAN0_IF2MSK                           *((volatile uint32_t*)(0x40062044UL))
#define FM_CAN0_IF2ARB                            *((volatile uint32_t*)(0x40062048UL))
#define FM4_CAN0_IF2ARB                           *((volatile uint32_t*)(0x40062048UL))
#define FM_CAN0_IF2MCTR                           *((volatile uint16_t*)(0x4006204CUL))
#define FM4_CAN0_IF2MCTR                          *((volatile uint16_t*)(0x4006204CUL))
#define FM_CAN0_IF2DTA_L                          *((volatile uint32_t*)(0x40062050UL))
#define FM4_CAN0_IF2DTA_L                         *((volatile uint32_t*)(0x40062050UL))
#define FM_CAN0_IF2DTB_L                          *((volatile uint32_t*)(0x40062054UL))
#define FM4_CAN0_IF2DTB_L                         *((volatile uint32_t*)(0x40062054UL))
#define FM_CAN0_IF2DTA_B                          *((volatile uint32_t*)(0x40062060UL))
#define FM4_CAN0_IF2DTA_B                         *((volatile uint32_t*)(0x40062060UL))
#define FM_CAN0_IF2DTB_B                          *((volatile uint32_t*)(0x40062064UL))
#define FM4_CAN0_IF2DTB_B                         *((volatile uint32_t*)(0x40062064UL))
#define FM_CAN0_TREQR                             *((volatile uint32_t*)(0x40062080UL))
#define FM4_CAN0_TREQR                            *((volatile uint32_t*)(0x40062080UL))
#define FM_CAN0_NEWDT                             *((volatile uint32_t*)(0x40062090UL))
#define FM4_CAN0_NEWDT                            *((volatile uint32_t*)(0x40062090UL))
#define FM_CAN0_INTPND                            *((volatile uint32_t*)(0x400620A0UL))
#define FM4_CAN0_INTPND                           *((volatile uint32_t*)(0x400620A0UL))
#define FM_CAN0_MSGVAL                            *((volatile uint32_t*)(0x400620B0UL))
#define FM4_CAN0_MSGVAL                           *((volatile uint32_t*)(0x400620B0UL))

/*******************************************************************************
* CAN Registers CAN1
*   Register Definition
*******************************************************************************/
#define FM_CAN1_CTRLR                             *((volatile uint16_t*)(0x40063000UL))
#define FM4_CAN1_CTRLR                            *((volatile uint16_t*)(0x40063000UL))
#define FM_CAN1_STATR                             *((volatile uint16_t*)(0x40063002UL))
#define FM4_CAN1_STATR                            *((volatile uint16_t*)(0x40063002UL))
#define FM_CAN1_ERRCNT                            *((volatile uint16_t*)(0x40063004UL))
#define FM4_CAN1_ERRCNT                           *((volatile uint16_t*)(0x40063004UL))
#define FM_CAN1_BTR                               *((volatile uint16_t*)(0x40063006UL))
#define FM4_CAN1_BTR                              *((volatile uint16_t*)(0x40063006UL))
#define FM_CAN1_INTR                              *((volatile uint16_t*)(0x40063008UL))
#define FM4_CAN1_INTR                             *((volatile uint16_t*)(0x40063008UL))
#define FM_CAN1_TESTR                             *((volatile uint16_t*)(0x4006300AUL))
#define FM4_CAN1_TESTR                            *((volatile uint16_t*)(0x4006300AUL))
#define FM_CAN1_BRPER                             *((volatile uint16_t*)(0x4006300CUL))
#define FM4_CAN1_BRPER                            *((volatile uint16_t*)(0x4006300CUL))
#define FM_CAN1_IF1CREQ                           *((volatile uint16_t*)(0x40063010UL))
#define FM4_CAN1_IF1CREQ                          *((volatile uint16_t*)(0x40063010UL))
#define FM_CAN1_IF1CMSK                           *((volatile uint16_t*)(0x40063012UL))
#define FM4_CAN1_IF1CMSK                          *((volatile uint16_t*)(0x40063012UL))
#define FM_CAN1_IF1MSK                            *((volatile uint32_t*)(0x40063014UL))
#define FM4_CAN1_IF1MSK                           *((volatile uint32_t*)(0x40063014UL))
#define FM_CAN1_IF1ARB                            *((volatile uint32_t*)(0x40063018UL))
#define FM4_CAN1_IF1ARB                           *((volatile uint32_t*)(0x40063018UL))
#define FM_CAN1_IF1MCTR                           *((volatile uint16_t*)(0x4006301CUL))
#define FM4_CAN1_IF1MCTR                          *((volatile uint16_t*)(0x4006301CUL))
#define FM_CAN1_IF1DTA_L                          *((volatile uint32_t*)(0x40063020UL))
#define FM4_CAN1_IF1DTA_L                         *((volatile uint32_t*)(0x40063020UL))
#define FM_CAN1_IF1DTB_L                          *((volatile uint32_t*)(0x40063024UL))
#define FM4_CAN1_IF1DTB_L                         *((volatile uint32_t*)(0x40063024UL))
#define FM_CAN1_IF1DTA_B                          *((volatile uint32_t*)(0x40063030UL))
#define FM4_CAN1_IF1DTA_B                         *((volatile uint32_t*)(0x40063030UL))
#define FM_CAN1_IF1DTB_B                          *((volatile uint32_t*)(0x40063034UL))
#define FM4_CAN1_IF1DTB_B                         *((volatile uint32_t*)(0x40063034UL))
#define FM_CAN1_IF2CREQ                           *((volatile uint16_t*)(0x40063040UL))
#define FM4_CAN1_IF2CREQ                          *((volatile uint16_t*)(0x40063040UL))
#define FM_CAN1_IF2CMSK                           *((volatile uint16_t*)(0x40063042UL))
#define FM4_CAN1_IF2CMSK                          *((volatile uint16_t*)(0x40063042UL))
#define FM_CAN1_IF2MSK                            *((volatile uint32_t*)(0x40063044UL))
#define FM4_CAN1_IF2MSK                           *((volatile uint32_t*)(0x40063044UL))
#define FM_CAN1_IF2ARB                            *((volatile uint32_t*)(0x40063048UL))
#define FM4_CAN1_IF2ARB                           *((volatile uint32_t*)(0x40063048UL))
#define FM_CAN1_IF2MCTR                           *((volatile uint16_t*)(0x4006304CUL))
#define FM4_CAN1_IF2MCTR                          *((volatile uint16_t*)(0x4006304CUL))
#define FM_CAN1_IF2DTA_L                          *((volatile uint32_t*)(0x40063050UL))
#define FM4_CAN1_IF2DTA_L                         *((volatile uint32_t*)(0x40063050UL))
#define FM_CAN1_IF2DTB_L                          *((volatile uint32_t*)(0x40063054UL))
#define FM4_CAN1_IF2DTB_L                         *((volatile uint32_t*)(0x40063054UL))
#define FM_CAN1_IF2DTA_B                          *((volatile uint32_t*)(0x40063060UL))
#define FM4_CAN1_IF2DTA_B                         *((volatile uint32_t*)(0x40063060UL))
#define FM_CAN1_IF2DTB_B                          *((volatile uint32_t*)(0x40063064UL))
#define FM4_CAN1_IF2DTB_B                         *((volatile uint32_t*)(0x40063064UL))
#define FM_CAN1_TREQR                             *((volatile uint32_t*)(0x40063080UL))
#define FM4_CAN1_TREQR                            *((volatile uint32_t*)(0x40063080UL))
#define FM_CAN1_NEWDT                             *((volatile uint32_t*)(0x40063090UL))
#define FM4_CAN1_NEWDT                            *((volatile uint32_t*)(0x40063090UL))
#define FM_CAN1_INTPND                            *((volatile uint32_t*)(0x400630A0UL))
#define FM4_CAN1_INTPND                           *((volatile uint32_t*)(0x400630A0UL))
#define FM_CAN1_MSGVAL                            *((volatile uint32_t*)(0x400630B0UL))
#define FM4_CAN1_MSGVAL                           *((volatile uint32_t*)(0x400630B0UL))

/*******************************************************************************
* CANFD Registers CANFD0
*   Register Definition
*******************************************************************************/
#define FM_CANFD0_CREL                            *((volatile uint32_t*)(0x40070000UL))
#define FM4_CANFD0_CREL                           *((volatile uint32_t*)(0x40070000UL))
#define FM_CANFD0_ENDN                            *((volatile uint32_t*)(0x40070004UL))
#define FM4_CANFD0_ENDN                           *((volatile uint32_t*)(0x40070004UL))
#define FM_CANFD0_FBTP                            *((volatile uint32_t*)(0x4007000CUL))
#define FM4_CANFD0_FBTP                           *((volatile uint32_t*)(0x4007000CUL))
#define FM_CANFD0_TEST                            *((volatile uint32_t*)(0x40070010UL))
#define FM4_CANFD0_TEST                           *((volatile uint32_t*)(0x40070010UL))
#define FM_CANFD0_RWD                             *((volatile uint32_t*)(0x40070014UL))
#define FM4_CANFD0_RWD                            *((volatile uint32_t*)(0x40070014UL))
#define FM_CANFD0_CCCR                            *((volatile uint32_t*)(0x40070018UL))
#define FM4_CANFD0_CCCR                           *((volatile uint32_t*)(0x40070018UL))
#define FM_CANFD0_BTP                             *((volatile uint32_t*)(0x4007001CUL))
#define FM4_CANFD0_BTP                            *((volatile uint32_t*)(0x4007001CUL))
#define FM_CANFD0_TSCC                            *((volatile uint32_t*)(0x40070020UL))
#define FM4_CANFD0_TSCC                           *((volatile uint32_t*)(0x40070020UL))
#define FM_CANFD0_TSCV                            *((volatile uint32_t*)(0x40070024UL))
#define FM4_CANFD0_TSCV                           *((volatile uint32_t*)(0x40070024UL))
#define FM_CANFD0_TOCC                            *((volatile uint32_t*)(0x40070028UL))
#define FM4_CANFD0_TOCC                           *((volatile uint32_t*)(0x40070028UL))
#define FM_CANFD0_TOCV                            *((volatile uint32_t*)(0x4007002CUL))
#define FM4_CANFD0_TOCV                           *((volatile uint32_t*)(0x4007002CUL))
#define FM_CANFD0_ECR                             *((volatile uint32_t*)(0x40070040UL))
#define FM4_CANFD0_ECR                            *((volatile uint32_t*)(0x40070040UL))
#define FM_CANFD0_PSR                             *((volatile uint32_t*)(0x40070044UL))
#define FM4_CANFD0_PSR                            *((volatile uint32_t*)(0x40070044UL))
#define FM_CANFD0_IR                              *((volatile uint32_t*)(0x40070050UL))
#define FM4_CANFD0_IR                             *((volatile uint32_t*)(0x40070050UL))
#define FM_CANFD0_IE                              *((volatile uint32_t*)(0x40070054UL))
#define FM4_CANFD0_IE                             *((volatile uint32_t*)(0x40070054UL))
#define FM_CANFD0_ILS                             *((volatile uint32_t*)(0x40070058UL))
#define FM4_CANFD0_ILS                            *((volatile uint32_t*)(0x40070058UL))
#define FM_CANFD0_ILE                             *((volatile uint32_t*)(0x4007005CUL))
#define FM4_CANFD0_ILE                            *((volatile uint32_t*)(0x4007005CUL))
#define FM_CANFD0_GFC                             *((volatile uint32_t*)(0x40070080UL))
#define FM4_CANFD0_GFC                            *((volatile uint32_t*)(0x40070080UL))
#define FM_CANFD0_SIDFC                           *((volatile uint32_t*)(0x40070084UL))
#define FM4_CANFD0_SIDFC                          *((volatile uint32_t*)(0x40070084UL))
#define FM_CANFD0_XIDFC                           *((volatile uint32_t*)(0x40070088UL))
#define FM4_CANFD0_XIDFC                          *((volatile uint32_t*)(0x40070088UL))
#define FM_CANFD0_XIDAM                           *((volatile uint32_t*)(0x40070090UL))
#define FM4_CANFD0_XIDAM                          *((volatile uint32_t*)(0x40070090UL))
#define FM_CANFD0_HPMS                            *((volatile uint32_t*)(0x40070094UL))
#define FM4_CANFD0_HPMS                           *((volatile uint32_t*)(0x40070094UL))
#define FM_CANFD0_NDAT1                           *((volatile uint32_t*)(0x40070098UL))
#define FM4_CANFD0_NDAT1                          *((volatile uint32_t*)(0x40070098UL))
#define FM_CANFD0_NDAT2                           *((volatile uint32_t*)(0x4007009CUL))
#define FM4_CANFD0_NDAT2                          *((volatile uint32_t*)(0x4007009CUL))
#define FM_CANFD0_RXF0C                           *((volatile uint32_t*)(0x400700A0UL))
#define FM4_CANFD0_RXF0C                          *((volatile uint32_t*)(0x400700A0UL))
#define FM_CANFD0_RXF0S                           *((volatile uint32_t*)(0x400700A4UL))
#define FM4_CANFD0_RXF0S                          *((volatile uint32_t*)(0x400700A4UL))
#define FM_CANFD0_RXF0A                           *((volatile uint32_t*)(0x400700A8UL))
#define FM4_CANFD0_RXF0A                          *((volatile uint32_t*)(0x400700A8UL))
#define FM_CANFD0_RXBC                            *((volatile uint32_t*)(0x400700ACUL))
#define FM4_CANFD0_RXBC                           *((volatile uint32_t*)(0x400700ACUL))
#define FM_CANFD0_RXF1C                           *((volatile uint32_t*)(0x400700B0UL))
#define FM4_CANFD0_RXF1C                          *((volatile uint32_t*)(0x400700B0UL))
#define FM_CANFD0_RXF1S                           *((volatile uint32_t*)(0x400700B4UL))
#define FM4_CANFD0_RXF1S                          *((volatile uint32_t*)(0x400700B4UL))
#define FM_CANFD0_RXF1A                           *((volatile uint32_t*)(0x400700B8UL))
#define FM4_CANFD0_RXF1A                          *((volatile uint32_t*)(0x400700B8UL))
#define FM_CANFD0_RXESC                           *((volatile uint32_t*)(0x400700BCUL))
#define FM4_CANFD0_RXESC                          *((volatile uint32_t*)(0x400700BCUL))
#define FM_CANFD0_TXBC                            *((volatile uint32_t*)(0x400700C0UL))
#define FM4_CANFD0_TXBC                           *((volatile uint32_t*)(0x400700C0UL))
#define FM_CANFD0_TXFQS                           *((volatile uint32_t*)(0x400700C4UL))
#define FM4_CANFD0_TXFQS                          *((volatile uint32_t*)(0x400700C4UL))
#define FM_CANFD0_TXESC                           *((volatile uint32_t*)(0x400700C8UL))
#define FM4_CANFD0_TXESC                          *((volatile uint32_t*)(0x400700C8UL))
#define FM_CANFD0_TXBRP                           *((volatile uint32_t*)(0x400700CCUL))
#define FM4_CANFD0_TXBRP                          *((volatile uint32_t*)(0x400700CCUL))
#define FM_CANFD0_TXBAR                           *((volatile uint32_t*)(0x400700D0UL))
#define FM4_CANFD0_TXBAR                          *((volatile uint32_t*)(0x400700D0UL))
#define FM_CANFD0_TXBCR                           *((volatile uint32_t*)(0x400700D4UL))
#define FM4_CANFD0_TXBCR                          *((volatile uint32_t*)(0x400700D4UL))
#define FM_CANFD0_TXBTO                           *((volatile uint32_t*)(0x400700D8UL))
#define FM4_CANFD0_TXBTO                          *((volatile uint32_t*)(0x400700D8UL))
#define FM_CANFD0_TXBCF                           *((volatile uint32_t*)(0x400700DCUL))
#define FM4_CANFD0_TXBCF                          *((volatile uint32_t*)(0x400700DCUL))
#define FM_CANFD0_TXBTIE                          *((volatile uint32_t*)(0x400700E0UL))
#define FM4_CANFD0_TXBTIE                         *((volatile uint32_t*)(0x400700E0UL))
#define FM_CANFD0_TXBCIE                          *((volatile uint32_t*)(0x400700E4UL))
#define FM4_CANFD0_TXBCIE                         *((volatile uint32_t*)(0x400700E4UL))
#define FM_CANFD0_TXEFC                           *((volatile uint32_t*)(0x400700F0UL))
#define FM4_CANFD0_TXEFC                          *((volatile uint32_t*)(0x400700F0UL))
#define FM_CANFD0_TXFS                            *((volatile uint32_t*)(0x400700F4UL))
#define FM4_CANFD0_TXFS                           *((volatile uint32_t*)(0x400700F4UL))
#define FM_CANFD0_TXFA                            *((volatile uint32_t*)(0x400700F8UL))
#define FM4_CANFD0_TXFA                           *((volatile uint32_t*)(0x400700F8UL))
#define FM_CANFD0_FDECR                           *((volatile  uint8_t*)(0x40070200UL))
#define FM4_CANFD0_FDECR                          *((volatile  uint8_t*)(0x40070200UL))
#define FM_CANFD0_FDESR                           *((volatile  uint8_t*)(0x40070201UL))
#define FM4_CANFD0_FDESR                          *((volatile  uint8_t*)(0x40070201UL))
#define FM_CANFD0_FDSEAR                          *((volatile uint16_t*)(0x40070202UL))
#define FM4_CANFD0_FDSEAR                         *((volatile uint16_t*)(0x40070202UL))
#define FM_CANFD0_FDESCR                          *((volatile  uint8_t*)(0x40070205UL))
#define FM4_CANFD0_FDESCR                         *((volatile  uint8_t*)(0x40070205UL))
#define FM_CANFD0_FDDEAR                          *((volatile uint16_t*)(0x40070206UL))
#define FM4_CANFD0_FDDEAR                         *((volatile uint16_t*)(0x40070206UL))
#define FM_CANFD0_TSCNTR                          *((volatile uint16_t*)(0x40070210UL))
#define FM4_CANFD0_TSCNTR                         *((volatile uint16_t*)(0x40070210UL))
#define FM_CANFD0_TSMDR                           *((volatile uint16_t*)(0x40070212UL))
#define FM4_CANFD0_TSMDR                          *((volatile uint16_t*)(0x40070212UL))
#define FM_CANFD0_TSDIVR                          *((volatile uint32_t*)(0x40070214UL))
#define FM4_CANFD0_TSDIVR                         *((volatile uint32_t*)(0x40070214UL))
#define FM_CANFD0_TSCDTR                          *((volatile uint16_t*)(0x40070218UL))
#define FM4_CANFD0_TSCDTR                         *((volatile uint16_t*)(0x40070218UL))
#define FM_CANFD0_TSCPCLR                         *((volatile uint16_t*)(0x4007021AUL))
#define FM4_CANFD0_TSCPCLR                        *((volatile uint16_t*)(0x4007021AUL))

/*******************************************************************************
* CANPRES Registers CANPRES
*   Register Definition
*******************************************************************************/
#define FM_CANPRES_CANPRE                         *((volatile  uint8_t*)(0x40037000UL))
#define FM4_CANPRES_CANPRE                        *((volatile  uint8_t*)(0x40037000UL))

/*******************************************************************************
* CLK_GATING Registers CLK_GATING
*   Register Definition
*******************************************************************************/
#define FM_CLK_GATING_CKEN0                       *((volatile uint32_t*)(0x4003C100UL))
#define FM4_CLK_GATING_CKEN0                      *((volatile uint32_t*)(0x4003C100UL))
#define FM_CLK_GATING_MRST0                       *((volatile uint32_t*)(0x4003C104UL))
#define FM4_CLK_GATING_MRST0                      *((volatile uint32_t*)(0x4003C104UL))
#define FM_CLK_GATING_CKEN1                       *((volatile uint32_t*)(0x4003C110UL))
#define FM4_CLK_GATING_CKEN1                      *((volatile uint32_t*)(0x4003C110UL))
#define FM_CLK_GATING_MRST1                       *((volatile uint32_t*)(0x4003C114UL))
#define FM4_CLK_GATING_MRST1                      *((volatile uint32_t*)(0x4003C114UL))
#define FM_CLK_GATING_CKEN2                       *((volatile uint32_t*)(0x4003C120UL))
#define FM4_CLK_GATING_CKEN2                      *((volatile uint32_t*)(0x4003C120UL))
#define FM_CLK_GATING_MRST2                       *((volatile uint32_t*)(0x4003C124UL))
#define FM4_CLK_GATING_MRST2                      *((volatile uint32_t*)(0x4003C124UL))

/*******************************************************************************
* CRC Registers CRC
*   Register Definition
*******************************************************************************/
#define FM_CRC_CRCCR                              *((volatile  uint8_t*)(0x40039000UL))
#define FM4_CRC_CRCCR                             *((volatile  uint8_t*)(0x40039000UL))
#define FM_CRC_CRCINIT                            *((volatile uint32_t*)(0x40039004UL))
#define FM4_CRC_CRCINIT                           *((volatile uint32_t*)(0x40039004UL))
#define FM_CRC_CRCIN                              *((volatile uint32_t*)(0x40039008UL))
#define FM4_CRC_CRCIN                             *((volatile uint32_t*)(0x40039008UL))
#define FM_CRC_CRCR                               *((volatile uint32_t*)(0x4003900CUL))
#define FM4_CRC_CRCR                              *((volatile uint32_t*)(0x4003900CUL))

/*******************************************************************************
* CRG Registers CRG
*   Register Definition
*******************************************************************************/
#define FM_CRG_SCM_CTL                            *((volatile uint32_t*)(0x40010000UL))
#define FM4_CRG_SCM_CTL                           *((volatile uint32_t*)(0x40010000UL))
#define FM_CRG_SCM_STR                            *((volatile uint32_t*)(0x40010004UL))
#define FM4_CRG_SCM_STR                           *((volatile uint32_t*)(0x40010004UL))
#define FM_CRG_STB_CTL                            *((volatile uint32_t*)(0x40010008UL))
#define FM4_CRG_STB_CTL                           *((volatile uint32_t*)(0x40010008UL))
#define FM_CRG_RST_STR                            *((volatile uint32_t*)(0x4001000CUL))
#define FM4_CRG_RST_STR                           *((volatile uint32_t*)(0x4001000CUL))
#define FM_CRG_BSC_PSR                            *((volatile uint32_t*)(0x40010010UL))
#define FM4_CRG_BSC_PSR                           *((volatile uint32_t*)(0x40010010UL))
#define FM_CRG_APBC0_PSR                          *((volatile uint32_t*)(0x40010014UL))
#define FM4_CRG_APBC0_PSR                         *((volatile uint32_t*)(0x40010014UL))
#define FM_CRG_APBC1_PSR                          *((volatile uint32_t*)(0x40010018UL))
#define FM4_CRG_APBC1_PSR                         *((volatile uint32_t*)(0x40010018UL))
#define FM_CRG_APBC2_PSR                          *((volatile uint32_t*)(0x4001001CUL))
#define FM4_CRG_APBC2_PSR                         *((volatile uint32_t*)(0x4001001CUL))
#define FM_CRG_SWC_PSR                            *((volatile uint32_t*)(0x40010020UL))
#define FM4_CRG_SWC_PSR                           *((volatile uint32_t*)(0x40010020UL))
#define FM_CRG_TTC_PSR                            *((volatile uint32_t*)(0x40010028UL))
#define FM4_CRG_TTC_PSR                           *((volatile uint32_t*)(0x40010028UL))
#define FM_CRG_CSW_TMR                            *((volatile uint32_t*)(0x40010030UL))
#define FM4_CRG_CSW_TMR                           *((volatile uint32_t*)(0x40010030UL))
#define FM_CRG_PSW_TMR                            *((volatile uint32_t*)(0x40010034UL))
#define FM4_CRG_PSW_TMR                           *((volatile uint32_t*)(0x40010034UL))
#define FM_CRG_PLL_CTL1                           *((volatile uint32_t*)(0x40010038UL))
#define FM4_CRG_PLL_CTL1                          *((volatile uint32_t*)(0x40010038UL))
#define FM_CRG_PLL_CTL2                           *((volatile uint32_t*)(0x4001003CUL))
#define FM4_CRG_PLL_CTL2                          *((volatile uint32_t*)(0x4001003CUL))
#define FM_CRG_CSV_CTL                            *((volatile uint32_t*)(0x40010040UL))
#define FM4_CRG_CSV_CTL                           *((volatile uint32_t*)(0x40010040UL))
#define FM_CRG_CSV_STR                            *((volatile uint32_t*)(0x40010044UL))
#define FM4_CRG_CSV_STR                           *((volatile uint32_t*)(0x40010044UL))
#define FM_CRG_FCSWH_CTL                          *((volatile uint32_t*)(0x40010048UL))
#define FM4_CRG_FCSWH_CTL                         *((volatile uint32_t*)(0x40010048UL))
#define FM_CRG_FCSWL_CTL                          *((volatile uint32_t*)(0x4001004CUL))
#define FM4_CRG_FCSWL_CTL                         *((volatile uint32_t*)(0x4001004CUL))
#define FM_CRG_FCSWD_CTL                          *((volatile uint32_t*)(0x40010050UL))
#define FM4_CRG_FCSWD_CTL                         *((volatile uint32_t*)(0x40010050UL))
#define FM_CRG_DBWDT_CTL                          *((volatile uint32_t*)(0x40010054UL))
#define FM4_CRG_DBWDT_CTL                         *((volatile uint32_t*)(0x40010054UL))
#define FM_CRG_INT_ENR                            *((volatile uint32_t*)(0x40010060UL))
#define FM4_CRG_INT_ENR                           *((volatile uint32_t*)(0x40010060UL))
#define FM_CRG_INT_STR                            *((volatile uint32_t*)(0x40010064UL))
#define FM4_CRG_INT_STR                           *((volatile uint32_t*)(0x40010064UL))
#define FM_CRG_INT_CLR                            *((volatile uint32_t*)(0x40010068UL))
#define FM4_CRG_INT_CLR                           *((volatile uint32_t*)(0x40010068UL))
#define FM_CRG_PLLCG_CTL                          *((volatile uint32_t*)(0x40010074UL))
#define FM4_CRG_PLLCG_CTL                         *((volatile uint32_t*)(0x40010074UL))

/*******************************************************************************
* CRTRIM Registers CRTRIM
*   Register Definition
*******************************************************************************/
#define FM_CRTRIM_MCR_PSR                         *((volatile  uint8_t*)(0x4002E000UL))
#define FM4_CRTRIM_MCR_PSR                        *((volatile  uint8_t*)(0x4002E000UL))
#define FM_CRTRIM_MCR_FTRM                        *((volatile uint32_t*)(0x4002E004UL))
#define FM4_CRTRIM_MCR_FTRM                       *((volatile uint32_t*)(0x4002E004UL))
#define FM_CRTRIM_MCR_TTRM                        *((volatile uint32_t*)(0x4002E008UL))
#define FM4_CRTRIM_MCR_TTRM                       *((volatile uint32_t*)(0x4002E008UL))
#define FM_CRTRIM_MCR_RLR                         *((volatile uint32_t*)(0x4002E00CUL))
#define FM4_CRTRIM_MCR_RLR                        *((volatile uint32_t*)(0x4002E00CUL))

/*******************************************************************************
* DAC Registers DAC0
*   Register Definition
*******************************************************************************/
#define FM_DAC0_DACR                              *((volatile  uint8_t*)(0x40033000UL))
#define FM4_DAC0_DACR                             *((volatile  uint8_t*)(0x40033000UL))
#define FM_DAC0_DADR                              *((volatile uint16_t*)(0x40033004UL))
#define FM4_DAC0_DADR                             *((volatile uint16_t*)(0x40033004UL))

/*******************************************************************************
* DAC Registers DAC1
*   Register Definition
*******************************************************************************/
#define FM_DAC1_DACR                              *((volatile  uint8_t*)(0x40033008UL))
#define FM4_DAC1_DACR                             *((volatile  uint8_t*)(0x40033008UL))
#define FM_DAC1_DADR                              *((volatile uint16_t*)(0x4003300CUL))
#define FM4_DAC1_DADR                             *((volatile uint16_t*)(0x4003300CUL))

/*******************************************************************************
* DMAC Registers DMAC
*   Register Definition
*******************************************************************************/
#define FM_DMAC_DMACR                             *((volatile uint32_t*)(0x40060000UL))
#define FM4_DMAC_DMACR                            *((volatile uint32_t*)(0x40060000UL))
#define FM_DMAC_DMACA0                            *((volatile uint32_t*)(0x40060010UL))
#define FM4_DMAC_DMACA0                           *((volatile uint32_t*)(0x40060010UL))
#define FM_DMAC_DMACB0                            *((volatile uint32_t*)(0x40060014UL))
#define FM4_DMAC_DMACB0                           *((volatile uint32_t*)(0x40060014UL))
#define FM_DMAC_DMACSA0                           *((volatile uint32_t*)(0x40060018UL))
#define FM4_DMAC_DMACSA0                          *((volatile uint32_t*)(0x40060018UL))
#define FM_DMAC_DMACDA0                           *((volatile uint32_t*)(0x4006001CUL))
#define FM4_DMAC_DMACDA0                          *((volatile uint32_t*)(0x4006001CUL))
#define FM_DMAC_DMACA1                            *((volatile uint32_t*)(0x40060020UL))
#define FM4_DMAC_DMACA1                           *((volatile uint32_t*)(0x40060020UL))
#define FM_DMAC_DMACB1                            *((volatile uint32_t*)(0x40060024UL))
#define FM4_DMAC_DMACB1                           *((volatile uint32_t*)(0x40060024UL))
#define FM_DMAC_DMACSA1                           *((volatile uint32_t*)(0x40060028UL))
#define FM4_DMAC_DMACSA1                          *((volatile uint32_t*)(0x40060028UL))
#define FM_DMAC_DMACDA1                           *((volatile uint32_t*)(0x4006002CUL))
#define FM4_DMAC_DMACDA1                          *((volatile uint32_t*)(0x4006002CUL))
#define FM_DMAC_DMACA2                            *((volatile uint32_t*)(0x40060030UL))
#define FM4_DMAC_DMACA2                           *((volatile uint32_t*)(0x40060030UL))
#define FM_DMAC_DMACB2                            *((volatile uint32_t*)(0x40060034UL))
#define FM4_DMAC_DMACB2                           *((volatile uint32_t*)(0x40060034UL))
#define FM_DMAC_DMACSA2                           *((volatile uint32_t*)(0x40060038UL))
#define FM4_DMAC_DMACSA2                          *((volatile uint32_t*)(0x40060038UL))
#define FM_DMAC_DMACDA2                           *((volatile uint32_t*)(0x4006003CUL))
#define FM4_DMAC_DMACDA2                          *((volatile uint32_t*)(0x4006003CUL))
#define FM_DMAC_DMACA3                            *((volatile uint32_t*)(0x40060040UL))
#define FM4_DMAC_DMACA3                           *((volatile uint32_t*)(0x40060040UL))
#define FM_DMAC_DMACB3                            *((volatile uint32_t*)(0x40060044UL))
#define FM4_DMAC_DMACB3                           *((volatile uint32_t*)(0x40060044UL))
#define FM_DMAC_DMACSA3                           *((volatile uint32_t*)(0x40060048UL))
#define FM4_DMAC_DMACSA3                          *((volatile uint32_t*)(0x40060048UL))
#define FM_DMAC_DMACDA3                           *((volatile uint32_t*)(0x4006004CUL))
#define FM4_DMAC_DMACDA3                          *((volatile uint32_t*)(0x4006004CUL))
#define FM_DMAC_DMACA4                            *((volatile uint32_t*)(0x40060050UL))
#define FM4_DMAC_DMACA4                           *((volatile uint32_t*)(0x40060050UL))
#define FM_DMAC_DMACB4                            *((volatile uint32_t*)(0x40060054UL))
#define FM4_DMAC_DMACB4                           *((volatile uint32_t*)(0x40060054UL))
#define FM_DMAC_DMACSA4                           *((volatile uint32_t*)(0x40060058UL))
#define FM4_DMAC_DMACSA4                          *((volatile uint32_t*)(0x40060058UL))
#define FM_DMAC_DMACDA4                           *((volatile uint32_t*)(0x4006005CUL))
#define FM4_DMAC_DMACDA4                          *((volatile uint32_t*)(0x4006005CUL))
#define FM_DMAC_DMACA5                            *((volatile uint32_t*)(0x40060060UL))
#define FM4_DMAC_DMACA5                           *((volatile uint32_t*)(0x40060060UL))
#define FM_DMAC_DMACB5                            *((volatile uint32_t*)(0x40060064UL))
#define FM4_DMAC_DMACB5                           *((volatile uint32_t*)(0x40060064UL))
#define FM_DMAC_DMACSA5                           *((volatile uint32_t*)(0x40060068UL))
#define FM4_DMAC_DMACSA5                          *((volatile uint32_t*)(0x40060068UL))
#define FM_DMAC_DMACDA5                           *((volatile uint32_t*)(0x4006006CUL))
#define FM4_DMAC_DMACDA5                          *((volatile uint32_t*)(0x4006006CUL))
#define FM_DMAC_DMACA6                            *((volatile uint32_t*)(0x40060070UL))
#define FM4_DMAC_DMACA6                           *((volatile uint32_t*)(0x40060070UL))
#define FM_DMAC_DMACB6                            *((volatile uint32_t*)(0x40060074UL))
#define FM4_DMAC_DMACB6                           *((volatile uint32_t*)(0x40060074UL))
#define FM_DMAC_DMACSA6                           *((volatile uint32_t*)(0x40060078UL))
#define FM4_DMAC_DMACSA6                          *((volatile uint32_t*)(0x40060078UL))
#define FM_DMAC_DMACDA6                           *((volatile uint32_t*)(0x4006007CUL))
#define FM4_DMAC_DMACDA6                          *((volatile uint32_t*)(0x4006007CUL))
#define FM_DMAC_DMACA7                            *((volatile uint32_t*)(0x40060080UL))
#define FM4_DMAC_DMACA7                           *((volatile uint32_t*)(0x40060080UL))
#define FM_DMAC_DMACB7                            *((volatile uint32_t*)(0x40060084UL))
#define FM4_DMAC_DMACB7                           *((volatile uint32_t*)(0x40060084UL))
#define FM_DMAC_DMACSA7                           *((volatile uint32_t*)(0x40060088UL))
#define FM4_DMAC_DMACSA7                          *((volatile uint32_t*)(0x40060088UL))
#define FM_DMAC_DMACDA7                           *((volatile uint32_t*)(0x4006008CUL))
#define FM4_DMAC_DMACDA7                          *((volatile uint32_t*)(0x4006008CUL))

/*******************************************************************************
* DS Registers DS
*   Register Definition
*******************************************************************************/
#define FM_DS_RCK_CTL                             *((volatile  uint8_t*)(0x40035104UL))
#define FM4_DS_RCK_CTL                            *((volatile  uint8_t*)(0x40035104UL))
#define FM_DS_PMD_CTL                             *((volatile  uint8_t*)(0x40035800UL))
#define FM4_DS_PMD_CTL                            *((volatile  uint8_t*)(0x40035800UL))
#define FM_DS_WRFSR                               *((volatile  uint8_t*)(0x40035804UL))
#define FM4_DS_WRFSR                              *((volatile  uint8_t*)(0x40035804UL))
#define FM_DS_WIFSR                               *((volatile uint16_t*)(0x40035808UL))
#define FM4_DS_WIFSR                              *((volatile uint16_t*)(0x40035808UL))
#define FM_DS_WIER                                *((volatile uint16_t*)(0x4003580CUL))
#define FM4_DS_WIER                               *((volatile uint16_t*)(0x4003580CUL))
#define FM_DS_WILVR                               *((volatile  uint8_t*)(0x40035810UL))
#define FM4_DS_WILVR                              *((volatile  uint8_t*)(0x40035810UL))
#define FM_DS_DSRAMR                              *((volatile  uint8_t*)(0x40035814UL))
#define FM4_DS_DSRAMR                             *((volatile  uint8_t*)(0x40035814UL))
#define FM_DS_BUR01                               *((volatile  uint8_t*)(0x40035900UL))
#define FM4_DS_BUR01                              *((volatile  uint8_t*)(0x40035900UL))
#define FM_DS_BUR02                               *((volatile  uint8_t*)(0x40035901UL))
#define FM4_DS_BUR02                              *((volatile  uint8_t*)(0x40035901UL))
#define FM_DS_BUR03                               *((volatile  uint8_t*)(0x40035902UL))
#define FM4_DS_BUR03                              *((volatile  uint8_t*)(0x40035902UL))
#define FM_DS_BUR04                               *((volatile  uint8_t*)(0x40035903UL))
#define FM4_DS_BUR04                              *((volatile  uint8_t*)(0x40035903UL))
#define FM_DS_BUR05                               *((volatile  uint8_t*)(0x40035904UL))
#define FM4_DS_BUR05                              *((volatile  uint8_t*)(0x40035904UL))
#define FM_DS_BUR06                               *((volatile  uint8_t*)(0x40035905UL))
#define FM4_DS_BUR06                              *((volatile  uint8_t*)(0x40035905UL))
#define FM_DS_BUR07                               *((volatile  uint8_t*)(0x40035906UL))
#define FM4_DS_BUR07                              *((volatile  uint8_t*)(0x40035906UL))
#define FM_DS_BUR08                               *((volatile  uint8_t*)(0x40035907UL))
#define FM4_DS_BUR08                              *((volatile  uint8_t*)(0x40035907UL))
#define FM_DS_BUR09                               *((volatile  uint8_t*)(0x40035908UL))
#define FM4_DS_BUR09                              *((volatile  uint8_t*)(0x40035908UL))
#define FM_DS_BUR10                               *((volatile  uint8_t*)(0x40035909UL))
#define FM4_DS_BUR10                              *((volatile  uint8_t*)(0x40035909UL))
#define FM_DS_BUR11                               *((volatile  uint8_t*)(0x4003590AUL))
#define FM4_DS_BUR11                              *((volatile  uint8_t*)(0x4003590AUL))
#define FM_DS_BUR12                               *((volatile  uint8_t*)(0x4003590BUL))
#define FM4_DS_BUR12                              *((volatile  uint8_t*)(0x4003590BUL))
#define FM_DS_BUR13                               *((volatile  uint8_t*)(0x4003590CUL))
#define FM4_DS_BUR13                              *((volatile  uint8_t*)(0x4003590CUL))
#define FM_DS_BUR14                               *((volatile  uint8_t*)(0x4003590DUL))
#define FM4_DS_BUR14                              *((volatile  uint8_t*)(0x4003590DUL))
#define FM_DS_BUR15                               *((volatile  uint8_t*)(0x4003590EUL))
#define FM4_DS_BUR15                              *((volatile  uint8_t*)(0x4003590EUL))
#define FM_DS_BUR16                               *((volatile  uint8_t*)(0x4003590FUL))
#define FM4_DS_BUR16                              *((volatile  uint8_t*)(0x4003590FUL))

/*******************************************************************************
* DSTC Registers DSTC
*   Register Definition
*******************************************************************************/
#define FM_DSTC_DESTP                             *((volatile uint32_t*)(0x40061000UL))
#define FM4_DSTC_DESTP                            *((volatile uint32_t*)(0x40061000UL))
#define FM_DSTC_HWDESP                            *((volatile uint32_t*)(0x40061004UL))
#define FM4_DSTC_HWDESP                           *((volatile uint32_t*)(0x40061004UL))
#define FM_DSTC_CMD                               *((volatile  uint8_t*)(0x40061008UL))
#define FM4_DSTC_CMD                              *((volatile  uint8_t*)(0x40061008UL))
#define FM_DSTC_CFG                               *((volatile  uint8_t*)(0x40061009UL))
#define FM4_DSTC_CFG                              *((volatile  uint8_t*)(0x40061009UL))
#define FM_DSTC_SWTR                              *((volatile uint16_t*)(0x4006100AUL))
#define FM4_DSTC_SWTR                             *((volatile uint16_t*)(0x4006100AUL))
#define FM_DSTC_MONERS                            *((volatile uint32_t*)(0x4006100CUL))
#define FM4_DSTC_MONERS                           *((volatile uint32_t*)(0x4006100CUL))
#define FM_DSTC_DREQENB0                          *((volatile uint32_t*)(0x40061010UL))
#define FM4_DSTC_DREQENB0                         *((volatile uint32_t*)(0x40061010UL))
#define FM_DSTC_DREQENB1                          *((volatile uint32_t*)(0x40061014UL))
#define FM4_DSTC_DREQENB1                         *((volatile uint32_t*)(0x40061014UL))
#define FM_DSTC_DREQENB2                          *((volatile uint32_t*)(0x40061018UL))
#define FM4_DSTC_DREQENB2                         *((volatile uint32_t*)(0x40061018UL))
#define FM_DSTC_DREQENB3                          *((volatile uint32_t*)(0x4006101CUL))
#define FM4_DSTC_DREQENB3                         *((volatile uint32_t*)(0x4006101CUL))
#define FM_DSTC_DREQENB4                          *((volatile uint32_t*)(0x40061020UL))
#define FM4_DSTC_DREQENB4                         *((volatile uint32_t*)(0x40061020UL))
#define FM_DSTC_DREQENB5                          *((volatile uint32_t*)(0x40061024UL))
#define FM4_DSTC_DREQENB5                         *((volatile uint32_t*)(0x40061024UL))
#define FM_DSTC_DREQENB6                          *((volatile uint32_t*)(0x40061028UL))
#define FM4_DSTC_DREQENB6                         *((volatile uint32_t*)(0x40061028UL))
#define FM_DSTC_DREQENB7                          *((volatile uint32_t*)(0x4006102CUL))
#define FM4_DSTC_DREQENB7                         *((volatile uint32_t*)(0x4006102CUL))
#define FM_DSTC_HWINT0                            *((volatile uint32_t*)(0x40061030UL))
#define FM4_DSTC_HWINT0                           *((volatile uint32_t*)(0x40061030UL))
#define FM_DSTC_HWINT1                            *((volatile uint32_t*)(0x40061034UL))
#define FM4_DSTC_HWINT1                           *((volatile uint32_t*)(0x40061034UL))
#define FM_DSTC_HWINT2                            *((volatile uint32_t*)(0x40061038UL))
#define FM4_DSTC_HWINT2                           *((volatile uint32_t*)(0x40061038UL))
#define FM_DSTC_HWINT3                            *((volatile uint32_t*)(0x4006103CUL))
#define FM4_DSTC_HWINT3                           *((volatile uint32_t*)(0x4006103CUL))
#define FM_DSTC_HWINT4                            *((volatile uint32_t*)(0x40061040UL))
#define FM4_DSTC_HWINT4                           *((volatile uint32_t*)(0x40061040UL))
#define FM_DSTC_HWINT5                            *((volatile uint32_t*)(0x40061044UL))
#define FM4_DSTC_HWINT5                           *((volatile uint32_t*)(0x40061044UL))
#define FM_DSTC_HWINT6                            *((volatile uint32_t*)(0x40061048UL))
#define FM4_DSTC_HWINT6                           *((volatile uint32_t*)(0x40061048UL))
#define FM_DSTC_HWINT7                            *((volatile uint32_t*)(0x4006104CUL))
#define FM4_DSTC_HWINT7                           *((volatile uint32_t*)(0x4006104CUL))
#define FM_DSTC_HWINTCLR0                         *((volatile uint32_t*)(0x40061050UL))
#define FM4_DSTC_HWINTCLR0                        *((volatile uint32_t*)(0x40061050UL))
#define FM_DSTC_HWINTCLR1                         *((volatile uint32_t*)(0x40061054UL))
#define FM4_DSTC_HWINTCLR1                        *((volatile uint32_t*)(0x40061054UL))
#define FM_DSTC_HWINTCLR2                         *((volatile uint32_t*)(0x40061058UL))
#define FM4_DSTC_HWINTCLR2                        *((volatile uint32_t*)(0x40061058UL))
#define FM_DSTC_HWINTCLR3                         *((volatile uint32_t*)(0x4006105CUL))
#define FM4_DSTC_HWINTCLR3                        *((volatile uint32_t*)(0x4006105CUL))
#define FM_DSTC_HWINTCLR4                         *((volatile uint32_t*)(0x40061060UL))
#define FM4_DSTC_HWINTCLR4                        *((volatile uint32_t*)(0x40061060UL))
#define FM_DSTC_HWINTCLR5                         *((volatile uint32_t*)(0x40061064UL))
#define FM4_DSTC_HWINTCLR5                        *((volatile uint32_t*)(0x40061064UL))
#define FM_DSTC_HWINTCLR6                         *((volatile uint32_t*)(0x40061068UL))
#define FM4_DSTC_HWINTCLR6                        *((volatile uint32_t*)(0x40061068UL))
#define FM_DSTC_HWINTCLR7                         *((volatile uint32_t*)(0x4006106CUL))
#define FM4_DSTC_HWINTCLR7                        *((volatile uint32_t*)(0x4006106CUL))
#define FM_DSTC_DQMSK0                            *((volatile uint32_t*)(0x40061070UL))
#define FM4_DSTC_DQMSK0                           *((volatile uint32_t*)(0x40061070UL))
#define FM_DSTC_DQMSK1                            *((volatile uint32_t*)(0x40061074UL))
#define FM4_DSTC_DQMSK1                           *((volatile uint32_t*)(0x40061074UL))
#define FM_DSTC_DQMSK2                            *((volatile uint32_t*)(0x40061078UL))
#define FM4_DSTC_DQMSK2                           *((volatile uint32_t*)(0x40061078UL))
#define FM_DSTC_DQMSK3                            *((volatile uint32_t*)(0x4006107CUL))
#define FM4_DSTC_DQMSK3                           *((volatile uint32_t*)(0x4006107CUL))
#define FM_DSTC_DQMSK4                            *((volatile uint32_t*)(0x40061080UL))
#define FM4_DSTC_DQMSK4                           *((volatile uint32_t*)(0x40061080UL))
#define FM_DSTC_DQMSK5                            *((volatile uint32_t*)(0x40061084UL))
#define FM4_DSTC_DQMSK5                           *((volatile uint32_t*)(0x40061084UL))
#define FM_DSTC_DQMSK6                            *((volatile uint32_t*)(0x40061088UL))
#define FM4_DSTC_DQMSK6                           *((volatile uint32_t*)(0x40061088UL))
#define FM_DSTC_DQMSK7                            *((volatile uint32_t*)(0x4006108CUL))
#define FM4_DSTC_DQMSK7                           *((volatile uint32_t*)(0x4006108CUL))
#define FM_DSTC_DQMSKCLR0                         *((volatile uint32_t*)(0x40061090UL))
#define FM4_DSTC_DQMSKCLR0                        *((volatile uint32_t*)(0x40061090UL))
#define FM_DSTC_DQMSKCLR1                         *((volatile uint32_t*)(0x40061094UL))
#define FM4_DSTC_DQMSKCLR1                        *((volatile uint32_t*)(0x40061094UL))
#define FM_DSTC_DQMSKCLR2                         *((volatile uint32_t*)(0x40061098UL))
#define FM4_DSTC_DQMSKCLR2                        *((volatile uint32_t*)(0x40061098UL))
#define FM_DSTC_DQMSKCLR3                         *((volatile uint32_t*)(0x4006109CUL))
#define FM4_DSTC_DQMSKCLR3                        *((volatile uint32_t*)(0x4006109CUL))
#define FM_DSTC_DQMSKCLR4                         *((volatile uint32_t*)(0x400610A0UL))
#define FM4_DSTC_DQMSKCLR4                        *((volatile uint32_t*)(0x400610A0UL))
#define FM_DSTC_DQMSKCLR5                         *((volatile uint32_t*)(0x400610A4UL))
#define FM4_DSTC_DQMSKCLR5                        *((volatile uint32_t*)(0x400610A4UL))
#define FM_DSTC_DQMSKCLR6                         *((volatile uint32_t*)(0x400610A8UL))
#define FM4_DSTC_DQMSKCLR6                        *((volatile uint32_t*)(0x400610A8UL))
#define FM_DSTC_DQMSKCLR7                         *((volatile uint32_t*)(0x400610ACUL))
#define FM4_DSTC_DQMSKCLR7                        *((volatile uint32_t*)(0x400610ACUL))

/*******************************************************************************
* DT Registers DT
*   Register Definition
*******************************************************************************/
#define FM_DT_TIMER1LOAD                          *((volatile uint32_t*)(0x40015000UL))
#define FM4_DT_TIMER1LOAD                         *((volatile uint32_t*)(0x40015000UL))
#define FM_DT_TIMER1VALUE                         *((volatile uint32_t*)(0x40015004UL))
#define FM4_DT_TIMER1VALUE                        *((volatile uint32_t*)(0x40015004UL))
#define FM_DT_TIMER1CONTROL                       *((volatile uint32_t*)(0x40015008UL))
#define FM4_DT_TIMER1CONTROL                      *((volatile uint32_t*)(0x40015008UL))
#define FM_DT_TIMER1INTCLR                        *((volatile uint32_t*)(0x4001500CUL))
#define FM4_DT_TIMER1INTCLR                       *((volatile uint32_t*)(0x4001500CUL))
#define FM_DT_TIMER1RIS                           *((volatile uint32_t*)(0x40015010UL))
#define FM4_DT_TIMER1RIS                          *((volatile uint32_t*)(0x40015010UL))
#define FM_DT_TIMER1MIS                           *((volatile uint32_t*)(0x40015014UL))
#define FM4_DT_TIMER1MIS                          *((volatile uint32_t*)(0x40015014UL))
#define FM_DT_TIMER1BGLOAD                        *((volatile uint32_t*)(0x40015018UL))
#define FM4_DT_TIMER1BGLOAD                       *((volatile uint32_t*)(0x40015018UL))
#define FM_DT_TIMER2LOAD                          *((volatile uint32_t*)(0x40015020UL))
#define FM4_DT_TIMER2LOAD                         *((volatile uint32_t*)(0x40015020UL))
#define FM_DT_TIMER2VALUE                         *((volatile uint32_t*)(0x40015024UL))
#define FM4_DT_TIMER2VALUE                        *((volatile uint32_t*)(0x40015024UL))
#define FM_DT_TIMER2CONTROL                       *((volatile uint32_t*)(0x40015028UL))
#define FM4_DT_TIMER2CONTROL                      *((volatile uint32_t*)(0x40015028UL))
#define FM_DT_TIMER2INTCLR                        *((volatile uint32_t*)(0x4001502CUL))
#define FM4_DT_TIMER2INTCLR                       *((volatile uint32_t*)(0x4001502CUL))
#define FM_DT_TIMER2RIS                           *((volatile uint32_t*)(0x40015030UL))
#define FM4_DT_TIMER2RIS                          *((volatile uint32_t*)(0x40015030UL))
#define FM_DT_TIMER2MIS                           *((volatile uint32_t*)(0x40015034UL))
#define FM4_DT_TIMER2MIS                          *((volatile uint32_t*)(0x40015034UL))
#define FM_DT_TIMER2BGLOAD                        *((volatile uint32_t*)(0x40015038UL))
#define FM4_DT_TIMER2BGLOAD                       *((volatile uint32_t*)(0x40015038UL))

/*******************************************************************************
* DUALFLASH_IF Registers DUALFLASH_IF
*   Register Definition
*******************************************************************************/
#define FM_DUALFLASH_IF_DFASZR                    *((volatile uint32_t*)(0x40000400UL))
#define FM4_DUALFLASH_IF_DFASZR                   *((volatile uint32_t*)(0x40000400UL))
#define FM_DUALFLASH_IF_DFRWTR                    *((volatile uint32_t*)(0x40000404UL))
#define FM4_DUALFLASH_IF_DFRWTR                   *((volatile uint32_t*)(0x40000404UL))
#define FM_DUALFLASH_IF_DFSTR                     *((volatile uint32_t*)(0x40000408UL))
#define FM4_DUALFLASH_IF_DFSTR                    *((volatile uint32_t*)(0x40000408UL))

/*******************************************************************************
* ECC_CAPTURE Registers ECC_CAPTURE
*   Register Definition
*******************************************************************************/
#define FM_ECC_CAPTURE_FERRAD                     *((volatile uint32_t*)(0x40000300UL))
#define FM4_ECC_CAPTURE_FERRAD                    *((volatile uint32_t*)(0x40000300UL))

/*******************************************************************************
* ETHERNET_CONTROL Registers ETHERNET_CONTROL
*   Register Definition
*******************************************************************************/
#define FM_ETHERNET_CONTROL_ETH_MODE              *((volatile uint32_t*)(0x40066000UL))
#define FM4_ETHERNET_CONTROL_ETH_MODE             *((volatile uint32_t*)(0x40066000UL))
#define FM_ETHERNET_CONTROL_ETH_CLKG              *((volatile uint32_t*)(0x40066008UL))
#define FM4_ETHERNET_CONTROL_ETH_CLKG             *((volatile uint32_t*)(0x40066008UL))

/*******************************************************************************
* ETHERNET_MAC Registers ETHERNET_MAC0
*   Register Definition
*******************************************************************************/
#define FM_ETHERNET_MAC0_MCR                      *((volatile uint32_t*)(0x40064000UL))
#define FM4_ETHERNET_MAC0_MCR                     *((volatile uint32_t*)(0x40064000UL))
#define FM_ETHERNET_MAC0_MFFR                     *((volatile uint32_t*)(0x40064004UL))
#define FM4_ETHERNET_MAC0_MFFR                    *((volatile uint32_t*)(0x40064004UL))
#define FM_ETHERNET_MAC0_MHTRH                    *((volatile uint32_t*)(0x40064008UL))
#define FM4_ETHERNET_MAC0_MHTRH                   *((volatile uint32_t*)(0x40064008UL))
#define FM_ETHERNET_MAC0_MHTRL                    *((volatile uint32_t*)(0x4006400CUL))
#define FM4_ETHERNET_MAC0_MHTRL                   *((volatile uint32_t*)(0x4006400CUL))
#define FM_ETHERNET_MAC0_GAR                      *((volatile uint32_t*)(0x40064010UL))
#define FM4_ETHERNET_MAC0_GAR                     *((volatile uint32_t*)(0x40064010UL))
#define FM_ETHERNET_MAC0_GDR                      *((volatile uint32_t*)(0x40064014UL))
#define FM4_ETHERNET_MAC0_GDR                     *((volatile uint32_t*)(0x40064014UL))
#define FM_ETHERNET_MAC0_FCR                      *((volatile uint32_t*)(0x40064018UL))
#define FM4_ETHERNET_MAC0_FCR                     *((volatile uint32_t*)(0x40064018UL))
#define FM_ETHERNET_MAC0_VTR                      *((volatile uint32_t*)(0x4006401CUL))
#define FM4_ETHERNET_MAC0_VTR                     *((volatile uint32_t*)(0x4006401CUL))
#define FM_ETHERNET_MAC0_RWFFR                    *((volatile uint32_t*)(0x40064028UL))
#define FM4_ETHERNET_MAC0_RWFFR                   *((volatile uint32_t*)(0x40064028UL))
#define FM_ETHERNET_MAC0_PMTR                     *((volatile uint32_t*)(0x4006402CUL))
#define FM4_ETHERNET_MAC0_PMTR                    *((volatile uint32_t*)(0x4006402CUL))
#define FM_ETHERNET_MAC0_LPICSR                   *((volatile uint32_t*)(0x40064030UL))
#define FM4_ETHERNET_MAC0_LPICSR                  *((volatile uint32_t*)(0x40064030UL))
#define FM_ETHERNET_MAC0_LPITCR                   *((volatile uint32_t*)(0x40064034UL))
#define FM4_ETHERNET_MAC0_LPITCR                  *((volatile uint32_t*)(0x40064034UL))
#define FM_ETHERNET_MAC0_ISR                      *((volatile uint32_t*)(0x40064038UL))
#define FM4_ETHERNET_MAC0_ISR                     *((volatile uint32_t*)(0x40064038UL))
#define FM_ETHERNET_MAC0_IMR                      *((volatile uint32_t*)(0x4006403CUL))
#define FM4_ETHERNET_MAC0_IMR                     *((volatile uint32_t*)(0x4006403CUL))
#define FM_ETHERNET_MAC0_MAR0H                    *((volatile uint32_t*)(0x40064040UL))
#define FM4_ETHERNET_MAC0_MAR0H                   *((volatile uint32_t*)(0x40064040UL))
#define FM_ETHERNET_MAC0_MAR0L                    *((volatile uint32_t*)(0x40064044UL))
#define FM4_ETHERNET_MAC0_MAR0L                   *((volatile uint32_t*)(0x40064044UL))
#define FM_ETHERNET_MAC0_MAR1H                    *((volatile uint32_t*)(0x40064048UL))
#define FM4_ETHERNET_MAC0_MAR1H                   *((volatile uint32_t*)(0x40064048UL))
#define FM_ETHERNET_MAC0_MAR1L                    *((volatile uint32_t*)(0x4006404CUL))
#define FM4_ETHERNET_MAC0_MAR1L                   *((volatile uint32_t*)(0x4006404CUL))
#define FM_ETHERNET_MAC0_MAR2H                    *((volatile uint32_t*)(0x40064050UL))
#define FM4_ETHERNET_MAC0_MAR2H                   *((volatile uint32_t*)(0x40064050UL))
#define FM_ETHERNET_MAC0_MAR2L                    *((volatile uint32_t*)(0x40064054UL))
#define FM4_ETHERNET_MAC0_MAR2L                   *((volatile uint32_t*)(0x40064054UL))
#define FM_ETHERNET_MAC0_MAR3H                    *((volatile uint32_t*)(0x40064058UL))
#define FM4_ETHERNET_MAC0_MAR3H                   *((volatile uint32_t*)(0x40064058UL))
#define FM_ETHERNET_MAC0_MAR3L                    *((volatile uint32_t*)(0x4006405CUL))
#define FM4_ETHERNET_MAC0_MAR3L                   *((volatile uint32_t*)(0x4006405CUL))
#define FM_ETHERNET_MAC0_MAR4H                    *((volatile uint32_t*)(0x40064060UL))
#define FM4_ETHERNET_MAC0_MAR4H                   *((volatile uint32_t*)(0x40064060UL))
#define FM_ETHERNET_MAC0_MAR4L                    *((volatile uint32_t*)(0x40064064UL))
#define FM4_ETHERNET_MAC0_MAR4L                   *((volatile uint32_t*)(0x40064064UL))
#define FM_ETHERNET_MAC0_MAR5H                    *((volatile uint32_t*)(0x40064068UL))
#define FM4_ETHERNET_MAC0_MAR5H                   *((volatile uint32_t*)(0x40064068UL))
#define FM_ETHERNET_MAC0_MAR5L                    *((volatile uint32_t*)(0x4006406CUL))
#define FM4_ETHERNET_MAC0_MAR5L                   *((volatile uint32_t*)(0x4006406CUL))
#define FM_ETHERNET_MAC0_MAR6H                    *((volatile uint32_t*)(0x40064070UL))
#define FM4_ETHERNET_MAC0_MAR6H                   *((volatile uint32_t*)(0x40064070UL))
#define FM_ETHERNET_MAC0_MAR6L                    *((volatile uint32_t*)(0x40064074UL))
#define FM4_ETHERNET_MAC0_MAR6L                   *((volatile uint32_t*)(0x40064074UL))
#define FM_ETHERNET_MAC0_MAR7H                    *((volatile uint32_t*)(0x40064078UL))
#define FM4_ETHERNET_MAC0_MAR7H                   *((volatile uint32_t*)(0x40064078UL))
#define FM_ETHERNET_MAC0_MAR7L                    *((volatile uint32_t*)(0x4006407CUL))
#define FM4_ETHERNET_MAC0_MAR7L                   *((volatile uint32_t*)(0x4006407CUL))
#define FM_ETHERNET_MAC0_MAR8H                    *((volatile uint32_t*)(0x40064080UL))
#define FM4_ETHERNET_MAC0_MAR8H                   *((volatile uint32_t*)(0x40064080UL))
#define FM_ETHERNET_MAC0_MAR8L                    *((volatile uint32_t*)(0x40064084UL))
#define FM4_ETHERNET_MAC0_MAR8L                   *((volatile uint32_t*)(0x40064084UL))
#define FM_ETHERNET_MAC0_MAR9H                    *((volatile uint32_t*)(0x40064088UL))
#define FM4_ETHERNET_MAC0_MAR9H                   *((volatile uint32_t*)(0x40064088UL))
#define FM_ETHERNET_MAC0_MAR9L                    *((volatile uint32_t*)(0x4006408CUL))
#define FM4_ETHERNET_MAC0_MAR9L                   *((volatile uint32_t*)(0x4006408CUL))
#define FM_ETHERNET_MAC0_MAR10H                   *((volatile uint32_t*)(0x40064090UL))
#define FM4_ETHERNET_MAC0_MAR10H                  *((volatile uint32_t*)(0x40064090UL))
#define FM_ETHERNET_MAC0_MAR10L                   *((volatile uint32_t*)(0x40064094UL))
#define FM4_ETHERNET_MAC0_MAR10L                  *((volatile uint32_t*)(0x40064094UL))
#define FM_ETHERNET_MAC0_MAR11H                   *((volatile uint32_t*)(0x40064098UL))
#define FM4_ETHERNET_MAC0_MAR11H                  *((volatile uint32_t*)(0x40064098UL))
#define FM_ETHERNET_MAC0_MAR11L                   *((volatile uint32_t*)(0x4006409CUL))
#define FM4_ETHERNET_MAC0_MAR11L                  *((volatile uint32_t*)(0x4006409CUL))
#define FM_ETHERNET_MAC0_MAR12H                   *((volatile uint32_t*)(0x400640A0UL))
#define FM4_ETHERNET_MAC0_MAR12H                  *((volatile uint32_t*)(0x400640A0UL))
#define FM_ETHERNET_MAC0_MAR12L                   *((volatile uint32_t*)(0x400640A4UL))
#define FM4_ETHERNET_MAC0_MAR12L                  *((volatile uint32_t*)(0x400640A4UL))
#define FM_ETHERNET_MAC0_MAR13H                   *((volatile uint32_t*)(0x400640A8UL))
#define FM4_ETHERNET_MAC0_MAR13H                  *((volatile uint32_t*)(0x400640A8UL))
#define FM_ETHERNET_MAC0_MAR13L                   *((volatile uint32_t*)(0x400640ACUL))
#define FM4_ETHERNET_MAC0_MAR13L                  *((volatile uint32_t*)(0x400640ACUL))
#define FM_ETHERNET_MAC0_MAR14H                   *((volatile uint32_t*)(0x400640B0UL))
#define FM4_ETHERNET_MAC0_MAR14H                  *((volatile uint32_t*)(0x400640B0UL))
#define FM_ETHERNET_MAC0_MAR14L                   *((volatile uint32_t*)(0x400640B4UL))
#define FM4_ETHERNET_MAC0_MAR14L                  *((volatile uint32_t*)(0x400640B4UL))
#define FM_ETHERNET_MAC0_MAR15H                   *((volatile uint32_t*)(0x400640B8UL))
#define FM4_ETHERNET_MAC0_MAR15H                  *((volatile uint32_t*)(0x400640B8UL))
#define FM_ETHERNET_MAC0_MAR15L                   *((volatile uint32_t*)(0x400640BCUL))
#define FM4_ETHERNET_MAC0_MAR15L                  *((volatile uint32_t*)(0x400640BCUL))
#define FM_ETHERNET_MAC0_RGSR                     *((volatile uint32_t*)(0x400640D8UL))
#define FM4_ETHERNET_MAC0_RGSR                    *((volatile uint32_t*)(0x400640D8UL))
#define FM_ETHERNET_MAC0_MMC_CNTL                 *((volatile uint32_t*)(0x40064100UL))
#define FM4_ETHERNET_MAC0_MMC_CNTL                *((volatile uint32_t*)(0x40064100UL))
#define FM_ETHERNET_MAC0_MMC_INTR_RX              *((volatile uint32_t*)(0x40064104UL))
#define FM4_ETHERNET_MAC0_MMC_INTR_RX             *((volatile uint32_t*)(0x40064104UL))
#define FM_ETHERNET_MAC0_MMC_INTR_TX              *((volatile uint32_t*)(0x40064108UL))
#define FM4_ETHERNET_MAC0_MMC_INTR_TX             *((volatile uint32_t*)(0x40064108UL))
#define FM_ETHERNET_MAC0_MMC_INTR_MASK_RX         *((volatile uint32_t*)(0x4006410CUL))
#define FM4_ETHERNET_MAC0_MMC_INTR_MASK_RX        *((volatile uint32_t*)(0x4006410CUL))
#define FM_ETHERNET_MAC0_MMC_INTR_MASK_TX         *((volatile uint32_t*)(0x40064110UL))
#define FM4_ETHERNET_MAC0_MMC_INTR_MASK_TX        *((volatile uint32_t*)(0x40064110UL))
#define FM_ETHERNET_MAC0_TXOCTETCOUNT_GB          *((volatile uint32_t*)(0x40064114UL))
#define FM4_ETHERNET_MAC0_TXOCTETCOUNT_GB         *((volatile uint32_t*)(0x40064114UL))
#define FM_ETHERNET_MAC0_TXFRAMECOUNT_GB          *((volatile uint32_t*)(0x40064118UL))
#define FM4_ETHERNET_MAC0_TXFRAMECOUNT_GB         *((volatile uint32_t*)(0x40064118UL))
#define FM_ETHERNET_MAC0_TXBROADCASTFRAMES_G      *((volatile uint32_t*)(0x4006411CUL))
#define FM4_ETHERNET_MAC0_TXBROADCASTFRAMES_G     *((volatile uint32_t*)(0x4006411CUL))
#define FM_ETHERNET_MAC0_TXMULTICASTFRAMES_G      *((volatile uint32_t*)(0x40064120UL))
#define FM4_ETHERNET_MAC0_TXMULTICASTFRAMES_G     *((volatile uint32_t*)(0x40064120UL))
#define FM_ETHERNET_MAC0_TX64OCTETS_GB            *((volatile uint32_t*)(0x40064124UL))
#define FM4_ETHERNET_MAC0_TX64OCTETS_GB           *((volatile uint32_t*)(0x40064124UL))
#define FM_ETHERNET_MAC0_TX65TO127OCTETS_GB       *((volatile uint32_t*)(0x40064128UL))
#define FM4_ETHERNET_MAC0_TX65TO127OCTETS_GB      *((volatile uint32_t*)(0x40064128UL))
#define FM_ETHERNET_MAC0_TX128TO255OCTETS_GB      *((volatile uint32_t*)(0x4006412CUL))
#define FM4_ETHERNET_MAC0_TX128TO255OCTETS_GB     *((volatile uint32_t*)(0x4006412CUL))
#define FM_ETHERNET_MAC0_TX256TO511OCTETS_GB      *((volatile uint32_t*)(0x40064130UL))
#define FM4_ETHERNET_MAC0_TX256TO511OCTETS_GB     *((volatile uint32_t*)(0x40064130UL))
#define FM_ETHERNET_MAC0_TX512TO1023OCTETS_GB     *((volatile uint32_t*)(0x40064134UL))
#define FM4_ETHERNET_MAC0_TX512TO1023OCTETS_GB    *((volatile uint32_t*)(0x40064134UL))
#define FM_ETHERNET_MAC0_TX1024TOMAXOCTETS_GB     *((volatile uint32_t*)(0x40064138UL))
#define FM4_ETHERNET_MAC0_TX1024TOMAXOCTETS_GB    *((volatile uint32_t*)(0x40064138UL))
#define FM_ETHERNET_MAC0_TXUNICASTFRAMES_GB       *((volatile uint32_t*)(0x4006413CUL))
#define FM4_ETHERNET_MAC0_TXUNICASTFRAMES_GB      *((volatile uint32_t*)(0x4006413CUL))
#define FM_ETHERNET_MAC0_TXMULTICASTFRAMES_GB     *((volatile uint32_t*)(0x40064140UL))
#define FM4_ETHERNET_MAC0_TXMULTICASTFRAMES_GB    *((volatile uint32_t*)(0x40064140UL))
#define FM_ETHERNET_MAC0_TXBROADCASTFRAMES_GB     *((volatile uint32_t*)(0x40064144UL))
#define FM4_ETHERNET_MAC0_TXBROADCASTFRAMES_GB    *((volatile uint32_t*)(0x40064144UL))
#define FM_ETHERNET_MAC0_TXUNDERFLOWERROR         *((volatile uint32_t*)(0x40064148UL))
#define FM4_ETHERNET_MAC0_TXUNDERFLOWERROR        *((volatile uint32_t*)(0x40064148UL))
#define FM_ETHERNET_MAC0_TXSINGLECOL_G            *((volatile uint32_t*)(0x4006414CUL))
#define FM4_ETHERNET_MAC0_TXSINGLECOL_G           *((volatile uint32_t*)(0x4006414CUL))
#define FM_ETHERNET_MAC0_TXMULTICOL_G             *((volatile uint32_t*)(0x40064150UL))
#define FM4_ETHERNET_MAC0_TXMULTICOL_G            *((volatile uint32_t*)(0x40064150UL))
#define FM_ETHERNET_MAC0_TXDEFERRED               *((volatile uint32_t*)(0x40064154UL))
#define FM4_ETHERNET_MAC0_TXDEFERRED              *((volatile uint32_t*)(0x40064154UL))
#define FM_ETHERNET_MAC0_TXLATECOL                *((volatile uint32_t*)(0x40064158UL))
#define FM4_ETHERNET_MAC0_TXLATECOL               *((volatile uint32_t*)(0x40064158UL))
#define FM_ETHERNET_MAC0_TXEXESSCOL               *((volatile uint32_t*)(0x4006415CUL))
#define FM4_ETHERNET_MAC0_TXEXESSCOL              *((volatile uint32_t*)(0x4006415CUL))
#define FM_ETHERNET_MAC0_TXCARRIERERROR           *((volatile uint32_t*)(0x40064160UL))
#define FM4_ETHERNET_MAC0_TXCARRIERERROR          *((volatile uint32_t*)(0x40064160UL))
#define FM_ETHERNET_MAC0_TXOCTETCOUNT_G           *((volatile uint32_t*)(0x40064164UL))
#define FM4_ETHERNET_MAC0_TXOCTETCOUNT_G          *((volatile uint32_t*)(0x40064164UL))
#define FM_ETHERNET_MAC0_TXFRAMECOUNT_G           *((volatile uint32_t*)(0x40064168UL))
#define FM4_ETHERNET_MAC0_TXFRAMECOUNT_G          *((volatile uint32_t*)(0x40064168UL))
#define FM_ETHERNET_MAC0_TXEXECESSDEF_G           *((volatile uint32_t*)(0x4006416CUL))
#define FM4_ETHERNET_MAC0_TXEXECESSDEF_G          *((volatile uint32_t*)(0x4006416CUL))
#define FM_ETHERNET_MAC0_TXPAUSEFRAMES            *((volatile uint32_t*)(0x40064170UL))
#define FM4_ETHERNET_MAC0_TXPAUSEFRAMES           *((volatile uint32_t*)(0x40064170UL))
#define FM_ETHERNET_MAC0_TXVLANFRAMES_G           *((volatile uint32_t*)(0x40064174UL))
#define FM4_ETHERNET_MAC0_TXVLANFRAMES_G          *((volatile uint32_t*)(0x40064174UL))
#define FM_ETHERNET_MAC0_RXFRAMECOUNT_GB          *((volatile uint32_t*)(0x40064180UL))
#define FM4_ETHERNET_MAC0_RXFRAMECOUNT_GB         *((volatile uint32_t*)(0x40064180UL))
#define FM_ETHERNET_MAC0_RXOCTETCOUNT_GB          *((volatile uint32_t*)(0x40064184UL))
#define FM4_ETHERNET_MAC0_RXOCTETCOUNT_GB         *((volatile uint32_t*)(0x40064184UL))
#define FM_ETHERNET_MAC0_RXOCTETCOUNT_G           *((volatile uint32_t*)(0x40064188UL))
#define FM4_ETHERNET_MAC0_RXOCTETCOUNT_G          *((volatile uint32_t*)(0x40064188UL))
#define FM_ETHERNET_MAC0_RXBROADCASTFRAMES_G      *((volatile uint32_t*)(0x4006418CUL))
#define FM4_ETHERNET_MAC0_RXBROADCASTFRAMES_G     *((volatile uint32_t*)(0x4006418CUL))
#define FM_ETHERNET_MAC0_RXMULTICASTFRAMES_G      *((volatile uint32_t*)(0x40064190UL))
#define FM4_ETHERNET_MAC0_RXMULTICASTFRAMES_G     *((volatile uint32_t*)(0x40064190UL))
#define FM_ETHERNET_MAC0_RXCRCERROR               *((volatile uint32_t*)(0x40064194UL))
#define FM4_ETHERNET_MAC0_RXCRCERROR              *((volatile uint32_t*)(0x40064194UL))
#define FM_ETHERNET_MAC0_RXALLIGNMENTERROR        *((volatile uint32_t*)(0x40064198UL))
#define FM4_ETHERNET_MAC0_RXALLIGNMENTERROR       *((volatile uint32_t*)(0x40064198UL))
#define FM_ETHERNET_MAC0_RXRUNTERROR              *((volatile uint32_t*)(0x4006419CUL))
#define FM4_ETHERNET_MAC0_RXRUNTERROR             *((volatile uint32_t*)(0x4006419CUL))
#define FM_ETHERNET_MAC0_RXJABBERERROR            *((volatile uint32_t*)(0x400641A0UL))
#define FM4_ETHERNET_MAC0_RXJABBERERROR           *((volatile uint32_t*)(0x400641A0UL))
#define FM_ETHERNET_MAC0_RXUNDERSIZE_G            *((volatile uint32_t*)(0x400641A4UL))
#define FM4_ETHERNET_MAC0_RXUNDERSIZE_G           *((volatile uint32_t*)(0x400641A4UL))
#define FM_ETHERNET_MAC0_RXOVERSIZE_G             *((volatile uint32_t*)(0x400641A8UL))
#define FM4_ETHERNET_MAC0_RXOVERSIZE_G            *((volatile uint32_t*)(0x400641A8UL))
#define FM_ETHERNET_MAC0_RX64OCTETS_GB            *((volatile uint32_t*)(0x400641ACUL))
#define FM4_ETHERNET_MAC0_RX64OCTETS_GB           *((volatile uint32_t*)(0x400641ACUL))
#define FM_ETHERNET_MAC0_RX65TO127OCTETS_GB       *((volatile uint32_t*)(0x400641B0UL))
#define FM4_ETHERNET_MAC0_RX65TO127OCTETS_GB      *((volatile uint32_t*)(0x400641B0UL))
#define FM_ETHERNET_MAC0_RX128TO255OCTETS_GB      *((volatile uint32_t*)(0x400641B4UL))
#define FM4_ETHERNET_MAC0_RX128TO255OCTETS_GB     *((volatile uint32_t*)(0x400641B4UL))
#define FM_ETHERNET_MAC0_RX256TO511OCTETS_GB      *((volatile uint32_t*)(0x400641B8UL))
#define FM4_ETHERNET_MAC0_RX256TO511OCTETS_GB     *((volatile uint32_t*)(0x400641B8UL))
#define FM_ETHERNET_MAC0_RX512TO1023OCTETS_GB     *((volatile uint32_t*)(0x400641BCUL))
#define FM4_ETHERNET_MAC0_RX512TO1023OCTETS_GB    *((volatile uint32_t*)(0x400641BCUL))
#define FM_ETHERNET_MAC0_RX1024TOMAXOCTETS_GB     *((volatile uint32_t*)(0x400641C0UL))
#define FM4_ETHERNET_MAC0_RX1024TOMAXOCTETS_GB    *((volatile uint32_t*)(0x400641C0UL))
#define FM_ETHERNET_MAC0_RXUNICASTFRAMES_G        *((volatile uint32_t*)(0x400641C4UL))
#define FM4_ETHERNET_MAC0_RXUNICASTFRAMES_G       *((volatile uint32_t*)(0x400641C4UL))
#define FM_ETHERNET_MAC0_RXLENGTHERROR            *((volatile uint32_t*)(0x400641C8UL))
#define FM4_ETHERNET_MAC0_RXLENGTHERROR           *((volatile uint32_t*)(0x400641C8UL))
#define FM_ETHERNET_MAC0_RXOUTOFRANGETYPE         *((volatile uint32_t*)(0x400641CCUL))
#define FM4_ETHERNET_MAC0_RXOUTOFRANGETYPE        *((volatile uint32_t*)(0x400641CCUL))
#define FM_ETHERNET_MAC0_RXPAUSEFRAMES            *((volatile uint32_t*)(0x400641D0UL))
#define FM4_ETHERNET_MAC0_RXPAUSEFRAMES           *((volatile uint32_t*)(0x400641D0UL))
#define FM_ETHERNET_MAC0_RXFIFOOVERFLOW           *((volatile uint32_t*)(0x400641D4UL))
#define FM4_ETHERNET_MAC0_RXFIFOOVERFLOW          *((volatile uint32_t*)(0x400641D4UL))
#define FM_ETHERNET_MAC0_RXVLANFRAMES_GB          *((volatile uint32_t*)(0x400641D8UL))
#define FM4_ETHERNET_MAC0_RXVLANFRAMES_GB         *((volatile uint32_t*)(0x400641D8UL))
#define FM_ETHERNET_MAC0_RXWATCHDOGERROR          *((volatile uint32_t*)(0x400641DCUL))
#define FM4_ETHERNET_MAC0_RXWATCHDOGERROR         *((volatile uint32_t*)(0x400641DCUL))
#define FM_ETHERNET_MAC0_MMC_IPC_INTR_MASK_RX     *((volatile uint32_t*)(0x40064200UL))
#define FM4_ETHERNET_MAC0_MMC_IPC_INTR_MASK_RX    *((volatile uint32_t*)(0x40064200UL))
#define FM_ETHERNET_MAC0_MMC_IPC_INTR_RX          *((volatile uint32_t*)(0x40064208UL))
#define FM4_ETHERNET_MAC0_MMC_IPC_INTR_RX         *((volatile uint32_t*)(0x40064208UL))
#define FM_ETHERNET_MAC0_RXIPV4_GD_FRMS           *((volatile uint32_t*)(0x40064210UL))
#define FM4_ETHERNET_MAC0_RXIPV4_GD_FRMS          *((volatile uint32_t*)(0x40064210UL))
#define FM_ETHERNET_MAC0_RXIPV4_HDRERR_FRMS       *((volatile uint32_t*)(0x40064214UL))
#define FM4_ETHERNET_MAC0_RXIPV4_HDRERR_FRMS      *((volatile uint32_t*)(0x40064214UL))
#define FM_ETHERNET_MAC0_RXIPV4_NOPAY_FRMS        *((volatile uint32_t*)(0x40064218UL))
#define FM4_ETHERNET_MAC0_RXIPV4_NOPAY_FRMS       *((volatile uint32_t*)(0x40064218UL))
#define FM_ETHERNET_MAC0_RXIPV4_FRAG_FRMS         *((volatile uint32_t*)(0x4006421CUL))
#define FM4_ETHERNET_MAC0_RXIPV4_FRAG_FRMS        *((volatile uint32_t*)(0x4006421CUL))
#define FM_ETHERNET_MAC0_RXIPV4_UDSBL_FRMS        *((volatile uint32_t*)(0x40064220UL))
#define FM4_ETHERNET_MAC0_RXIPV4_UDSBL_FRMS       *((volatile uint32_t*)(0x40064220UL))
#define FM_ETHERNET_MAC0_RXIPV6_GD_FRMS           *((volatile uint32_t*)(0x40064224UL))
#define FM4_ETHERNET_MAC0_RXIPV6_GD_FRMS          *((volatile uint32_t*)(0x40064224UL))
#define FM_ETHERNET_MAC0_RXIPV6_HDRERR_FRMS       *((volatile uint32_t*)(0x40064228UL))
#define FM4_ETHERNET_MAC0_RXIPV6_HDRERR_FRMS      *((volatile uint32_t*)(0x40064228UL))
#define FM_ETHERNET_MAC0_RXIPV6_NOPAY_FRMS        *((volatile uint32_t*)(0x4006422CUL))
#define FM4_ETHERNET_MAC0_RXIPV6_NOPAY_FRMS       *((volatile uint32_t*)(0x4006422CUL))
#define FM_ETHERNET_MAC0_RXUDP_GD_FRMS            *((volatile uint32_t*)(0x40064230UL))
#define FM4_ETHERNET_MAC0_RXUDP_GD_FRMS           *((volatile uint32_t*)(0x40064230UL))
#define FM_ETHERNET_MAC0_RXUDP_ERR_FRMS           *((volatile uint32_t*)(0x40064234UL))
#define FM4_ETHERNET_MAC0_RXUDP_ERR_FRMS          *((volatile uint32_t*)(0x40064234UL))
#define FM_ETHERNET_MAC0_RXTCP_GD_FRMS            *((volatile uint32_t*)(0x40064238UL))
#define FM4_ETHERNET_MAC0_RXTCP_GD_FRMS           *((volatile uint32_t*)(0x40064238UL))
#define FM_ETHERNET_MAC0_RXTCP_ERR_FRMS           *((volatile uint32_t*)(0x4006423CUL))
#define FM4_ETHERNET_MAC0_RXTCP_ERR_FRMS          *((volatile uint32_t*)(0x4006423CUL))
#define FM_ETHERNET_MAC0_RXICMP_GD_FRMS           *((volatile uint32_t*)(0x40064240UL))
#define FM4_ETHERNET_MAC0_RXICMP_GD_FRMS          *((volatile uint32_t*)(0x40064240UL))
#define FM_ETHERNET_MAC0_RXICMP_ERR_FRMS          *((volatile uint32_t*)(0x40064244UL))
#define FM4_ETHERNET_MAC0_RXICMP_ERR_FRMS         *((volatile uint32_t*)(0x40064244UL))
#define FM_ETHERNET_MAC0_RXIPV4_GD_OCTETS         *((volatile uint32_t*)(0x40064250UL))
#define FM4_ETHERNET_MAC0_RXIPV4_GD_OCTETS        *((volatile uint32_t*)(0x40064250UL))
#define FM_ETHERNET_MAC0_RXIPV4_HDRERR_OCTETS     *((volatile uint32_t*)(0x40064254UL))
#define FM4_ETHERNET_MAC0_RXIPV4_HDRERR_OCTETS    *((volatile uint32_t*)(0x40064254UL))
#define FM_ETHERNET_MAC0_RXIPV4_NOPAY_OCTETS      *((volatile uint32_t*)(0x40064258UL))
#define FM4_ETHERNET_MAC0_RXIPV4_NOPAY_OCTETS     *((volatile uint32_t*)(0x40064258UL))
#define FM_ETHERNET_MAC0_RXIPV4_FRAG_OCTETS       *((volatile uint32_t*)(0x4006425CUL))
#define FM4_ETHERNET_MAC0_RXIPV4_FRAG_OCTETS      *((volatile uint32_t*)(0x4006425CUL))
#define FM_ETHERNET_MAC0_RXIPV4_UDSBL_OCTETS      *((volatile uint32_t*)(0x40064260UL))
#define FM4_ETHERNET_MAC0_RXIPV4_UDSBL_OCTETS     *((volatile uint32_t*)(0x40064260UL))
#define FM_ETHERNET_MAC0_RXIPV6_GD_OCTETS         *((volatile uint32_t*)(0x40064264UL))
#define FM4_ETHERNET_MAC0_RXIPV6_GD_OCTETS        *((volatile uint32_t*)(0x40064264UL))
#define FM_ETHERNET_MAC0_RXIPV6_HDRERR_OCTETS     *((volatile uint32_t*)(0x40064268UL))
#define FM4_ETHERNET_MAC0_RXIPV6_HDRERR_OCTETS    *((volatile uint32_t*)(0x40064268UL))
#define FM_ETHERNET_MAC0_RXIPV6_NOPAY_OCTETS      *((volatile uint32_t*)(0x4006426CUL))
#define FM4_ETHERNET_MAC0_RXIPV6_NOPAY_OCTETS     *((volatile uint32_t*)(0x4006426CUL))
#define FM_ETHERNET_MAC0_RXUDP_GD_OCTETS          *((volatile uint32_t*)(0x40064270UL))
#define FM4_ETHERNET_MAC0_RXUDP_GD_OCTETS         *((volatile uint32_t*)(0x40064270UL))
#define FM_ETHERNET_MAC0_RXUDP_ERR_OCTETS         *((volatile uint32_t*)(0x40064274UL))
#define FM4_ETHERNET_MAC0_RXUDP_ERR_OCTETS        *((volatile uint32_t*)(0x40064274UL))
#define FM_ETHERNET_MAC0_RXTCP_GD_OCTETS          *((volatile uint32_t*)(0x40064278UL))
#define FM4_ETHERNET_MAC0_RXTCP_GD_OCTETS         *((volatile uint32_t*)(0x40064278UL))
#define FM_ETHERNET_MAC0_RXTCP_ERR_OCTETS         *((volatile uint32_t*)(0x4006427CUL))
#define FM4_ETHERNET_MAC0_RXTCP_ERR_OCTETS        *((volatile uint32_t*)(0x4006427CUL))
#define FM_ETHERNET_MAC0_RXICMP_GD_OCTETS         *((volatile uint32_t*)(0x40064280UL))
#define FM4_ETHERNET_MAC0_RXICMP_GD_OCTETS        *((volatile uint32_t*)(0x40064280UL))
#define FM_ETHERNET_MAC0_RXICMP_ERR_OCTETS        *((volatile uint32_t*)(0x40064284UL))
#define FM4_ETHERNET_MAC0_RXICMP_ERR_OCTETS       *((volatile uint32_t*)(0x40064284UL))
#define FM_ETHERNET_MAC0_TSCR                     *((volatile uint32_t*)(0x40064700UL))
#define FM4_ETHERNET_MAC0_TSCR                    *((volatile uint32_t*)(0x40064700UL))
#define FM_ETHERNET_MAC0_SSIR                     *((volatile uint32_t*)(0x40064704UL))
#define FM4_ETHERNET_MAC0_SSIR                    *((volatile uint32_t*)(0x40064704UL))
#define FM_ETHERNET_MAC0_STSR                     *((volatile uint32_t*)(0x40064708UL))
#define FM4_ETHERNET_MAC0_STSR                    *((volatile uint32_t*)(0x40064708UL))
#define FM_ETHERNET_MAC0_STNR                     *((volatile uint32_t*)(0x4006470CUL))
#define FM4_ETHERNET_MAC0_STNR                    *((volatile uint32_t*)(0x4006470CUL))
#define FM_ETHERNET_MAC0_STSUR                    *((volatile uint32_t*)(0x40064710UL))
#define FM4_ETHERNET_MAC0_STSUR                   *((volatile uint32_t*)(0x40064710UL))
#define FM_ETHERNET_MAC0_STNUR                    *((volatile uint32_t*)(0x40064714UL))
#define FM4_ETHERNET_MAC0_STNUR                   *((volatile uint32_t*)(0x40064714UL))
#define FM_ETHERNET_MAC0_TSAR                     *((volatile uint32_t*)(0x40064718UL))
#define FM4_ETHERNET_MAC0_TSAR                    *((volatile uint32_t*)(0x40064718UL))
#define FM_ETHERNET_MAC0_TTSR                     *((volatile uint32_t*)(0x4006471CUL))
#define FM4_ETHERNET_MAC0_TTSR                    *((volatile uint32_t*)(0x4006471CUL))
#define FM_ETHERNET_MAC0_TTNR                     *((volatile uint32_t*)(0x40064720UL))
#define FM4_ETHERNET_MAC0_TTNR                    *((volatile uint32_t*)(0x40064720UL))
#define FM_ETHERNET_MAC0_STHWSR                   *((volatile uint32_t*)(0x40064724UL))
#define FM4_ETHERNET_MAC0_STHWSR                  *((volatile uint32_t*)(0x40064724UL))
#define FM_ETHERNET_MAC0_TSR                      *((volatile uint32_t*)(0x40064728UL))
#define FM4_ETHERNET_MAC0_TSR                     *((volatile uint32_t*)(0x40064728UL))
#define FM_ETHERNET_MAC0_PPSCR                    *((volatile uint32_t*)(0x4006472CUL))
#define FM4_ETHERNET_MAC0_PPSCR                   *((volatile uint32_t*)(0x4006472CUL))
#define FM_ETHERNET_MAC0_ATNR                     *((volatile uint32_t*)(0x40064730UL))
#define FM4_ETHERNET_MAC0_ATNR                    *((volatile uint32_t*)(0x40064730UL))
#define FM_ETHERNET_MAC0_ATSR                     *((volatile uint32_t*)(0x40064734UL))
#define FM4_ETHERNET_MAC0_ATSR                    *((volatile uint32_t*)(0x40064734UL))
#define FM_ETHERNET_MAC0_MAR16H                   *((volatile uint32_t*)(0x40064800UL))
#define FM4_ETHERNET_MAC0_MAR16H                  *((volatile uint32_t*)(0x40064800UL))
#define FM_ETHERNET_MAC0_MAR16L                   *((volatile uint32_t*)(0x40064804UL))
#define FM4_ETHERNET_MAC0_MAR16L                  *((volatile uint32_t*)(0x40064804UL))
#define FM_ETHERNET_MAC0_MAR17H                   *((volatile uint32_t*)(0x40064808UL))
#define FM4_ETHERNET_MAC0_MAR17H                  *((volatile uint32_t*)(0x40064808UL))
#define FM_ETHERNET_MAC0_MAR17L                   *((volatile uint32_t*)(0x4006480CUL))
#define FM4_ETHERNET_MAC0_MAR17L                  *((volatile uint32_t*)(0x4006480CUL))
#define FM_ETHERNET_MAC0_MAR18H                   *((volatile uint32_t*)(0x40064810UL))
#define FM4_ETHERNET_MAC0_MAR18H                  *((volatile uint32_t*)(0x40064810UL))
#define FM_ETHERNET_MAC0_MAR18L                   *((volatile uint32_t*)(0x40064814UL))
#define FM4_ETHERNET_MAC0_MAR18L                  *((volatile uint32_t*)(0x40064814UL))
#define FM_ETHERNET_MAC0_MAR19H                   *((volatile uint32_t*)(0x40064818UL))
#define FM4_ETHERNET_MAC0_MAR19H                  *((volatile uint32_t*)(0x40064818UL))
#define FM_ETHERNET_MAC0_MAR19L                   *((volatile uint32_t*)(0x4006481CUL))
#define FM4_ETHERNET_MAC0_MAR19L                  *((volatile uint32_t*)(0x4006481CUL))
#define FM_ETHERNET_MAC0_MAR20H                   *((volatile uint32_t*)(0x40064820UL))
#define FM4_ETHERNET_MAC0_MAR20H                  *((volatile uint32_t*)(0x40064820UL))
#define FM_ETHERNET_MAC0_MAR20L                   *((volatile uint32_t*)(0x40064824UL))
#define FM4_ETHERNET_MAC0_MAR20L                  *((volatile uint32_t*)(0x40064824UL))
#define FM_ETHERNET_MAC0_MAR21H                   *((volatile uint32_t*)(0x40064828UL))
#define FM4_ETHERNET_MAC0_MAR21H                  *((volatile uint32_t*)(0x40064828UL))
#define FM_ETHERNET_MAC0_MAR21L                   *((volatile uint32_t*)(0x4006482CUL))
#define FM4_ETHERNET_MAC0_MAR21L                  *((volatile uint32_t*)(0x4006482CUL))
#define FM_ETHERNET_MAC0_MAR22H                   *((volatile uint32_t*)(0x40064830UL))
#define FM4_ETHERNET_MAC0_MAR22H                  *((volatile uint32_t*)(0x40064830UL))
#define FM_ETHERNET_MAC0_MAR22L                   *((volatile uint32_t*)(0x40064834UL))
#define FM4_ETHERNET_MAC0_MAR22L                  *((volatile uint32_t*)(0x40064834UL))
#define FM_ETHERNET_MAC0_MAR23H                   *((volatile uint32_t*)(0x40064838UL))
#define FM4_ETHERNET_MAC0_MAR23H                  *((volatile uint32_t*)(0x40064838UL))
#define FM_ETHERNET_MAC0_MAR23L                   *((volatile uint32_t*)(0x4006483CUL))
#define FM4_ETHERNET_MAC0_MAR23L                  *((volatile uint32_t*)(0x4006483CUL))
#define FM_ETHERNET_MAC0_MAR24H                   *((volatile uint32_t*)(0x40064840UL))
#define FM4_ETHERNET_MAC0_MAR24H                  *((volatile uint32_t*)(0x40064840UL))
#define FM_ETHERNET_MAC0_MAR24L                   *((volatile uint32_t*)(0x40064844UL))
#define FM4_ETHERNET_MAC0_MAR24L                  *((volatile uint32_t*)(0x40064844UL))
#define FM_ETHERNET_MAC0_MAR25H                   *((volatile uint32_t*)(0x40064848UL))
#define FM4_ETHERNET_MAC0_MAR25H                  *((volatile uint32_t*)(0x40064848UL))
#define FM_ETHERNET_MAC0_MAR25L                   *((volatile uint32_t*)(0x4006484CUL))
#define FM4_ETHERNET_MAC0_MAR25L                  *((volatile uint32_t*)(0x4006484CUL))
#define FM_ETHERNET_MAC0_MAR26H                   *((volatile uint32_t*)(0x40064850UL))
#define FM4_ETHERNET_MAC0_MAR26H                  *((volatile uint32_t*)(0x40064850UL))
#define FM_ETHERNET_MAC0_MAR26L                   *((volatile uint32_t*)(0x40064854UL))
#define FM4_ETHERNET_MAC0_MAR26L                  *((volatile uint32_t*)(0x40064854UL))
#define FM_ETHERNET_MAC0_MAR27H                   *((volatile uint32_t*)(0x40064858UL))
#define FM4_ETHERNET_MAC0_MAR27H                  *((volatile uint32_t*)(0x40064858UL))
#define FM_ETHERNET_MAC0_MAR27L                   *((volatile uint32_t*)(0x4006485CUL))
#define FM4_ETHERNET_MAC0_MAR27L                  *((volatile uint32_t*)(0x4006485CUL))
#define FM_ETHERNET_MAC0_MAR28H                   *((volatile uint32_t*)(0x40064860UL))
#define FM4_ETHERNET_MAC0_MAR28H                  *((volatile uint32_t*)(0x40064860UL))
#define FM_ETHERNET_MAC0_MAR28L                   *((volatile uint32_t*)(0x40064864UL))
#define FM4_ETHERNET_MAC0_MAR28L                  *((volatile uint32_t*)(0x40064864UL))
#define FM_ETHERNET_MAC0_MAR29H                   *((volatile uint32_t*)(0x40064868UL))
#define FM4_ETHERNET_MAC0_MAR29H                  *((volatile uint32_t*)(0x40064868UL))
#define FM_ETHERNET_MAC0_MAR29L                   *((volatile uint32_t*)(0x4006486CUL))
#define FM4_ETHERNET_MAC0_MAR29L                  *((volatile uint32_t*)(0x4006486CUL))
#define FM_ETHERNET_MAC0_MAR30H                   *((volatile uint32_t*)(0x40064870UL))
#define FM4_ETHERNET_MAC0_MAR30H                  *((volatile uint32_t*)(0x40064870UL))
#define FM_ETHERNET_MAC0_MAR30L                   *((volatile uint32_t*)(0x40064874UL))
#define FM4_ETHERNET_MAC0_MAR30L                  *((volatile uint32_t*)(0x40064874UL))
#define FM_ETHERNET_MAC0_MAR31H                   *((volatile uint32_t*)(0x40064878UL))
#define FM4_ETHERNET_MAC0_MAR31H                  *((volatile uint32_t*)(0x40064878UL))
#define FM_ETHERNET_MAC0_MAR31L                   *((volatile uint32_t*)(0x4006487CUL))
#define FM4_ETHERNET_MAC0_MAR31L                  *((volatile uint32_t*)(0x4006487CUL))
#define FM_ETHERNET_MAC0_BMR                      *((volatile uint32_t*)(0x40065000UL))
#define FM4_ETHERNET_MAC0_BMR                     *((volatile uint32_t*)(0x40065000UL))
#define FM_ETHERNET_MAC0_TPDR                     *((volatile uint32_t*)(0x40065004UL))
#define FM4_ETHERNET_MAC0_TPDR                    *((volatile uint32_t*)(0x40065004UL))
#define FM_ETHERNET_MAC0_RPDR                     *((volatile uint32_t*)(0x40065008UL))
#define FM4_ETHERNET_MAC0_RPDR                    *((volatile uint32_t*)(0x40065008UL))
#define FM_ETHERNET_MAC0_RDLAR                    *((volatile uint32_t*)(0x4006500CUL))
#define FM4_ETHERNET_MAC0_RDLAR                   *((volatile uint32_t*)(0x4006500CUL))
#define FM_ETHERNET_MAC0_TDLAR                    *((volatile uint32_t*)(0x40065010UL))
#define FM4_ETHERNET_MAC0_TDLAR                   *((volatile uint32_t*)(0x40065010UL))
#define FM_ETHERNET_MAC0_SR                       *((volatile uint32_t*)(0x40065014UL))
#define FM4_ETHERNET_MAC0_SR                      *((volatile uint32_t*)(0x40065014UL))
#define FM_ETHERNET_MAC0_OMR                      *((volatile uint32_t*)(0x40065018UL))
#define FM4_ETHERNET_MAC0_OMR                     *((volatile uint32_t*)(0x40065018UL))
#define FM_ETHERNET_MAC0_IER                      *((volatile uint32_t*)(0x4006501CUL))
#define FM4_ETHERNET_MAC0_IER                     *((volatile uint32_t*)(0x4006501CUL))
#define FM_ETHERNET_MAC0_MFBOCR                   *((volatile uint32_t*)(0x40065020UL))
#define FM4_ETHERNET_MAC0_MFBOCR                  *((volatile uint32_t*)(0x40065020UL))
#define FM_ETHERNET_MAC0_RIWTR                    *((volatile uint32_t*)(0x40065024UL))
#define FM4_ETHERNET_MAC0_RIWTR                   *((volatile uint32_t*)(0x40065024UL))
#define FM_ETHERNET_MAC0_AHBSR                    *((volatile uint32_t*)(0x4006502CUL))
#define FM4_ETHERNET_MAC0_AHBSR                   *((volatile uint32_t*)(0x4006502CUL))
#define FM_ETHERNET_MAC0_CHTDR                    *((volatile uint32_t*)(0x40065048UL))
#define FM4_ETHERNET_MAC0_CHTDR                   *((volatile uint32_t*)(0x40065048UL))
#define FM_ETHERNET_MAC0_CHRDR                    *((volatile uint32_t*)(0x4006504CUL))
#define FM4_ETHERNET_MAC0_CHRDR                   *((volatile uint32_t*)(0x4006504CUL))
#define FM_ETHERNET_MAC0_CHTBAR                   *((volatile uint32_t*)(0x40065050UL))
#define FM4_ETHERNET_MAC0_CHTBAR                  *((volatile uint32_t*)(0x40065050UL))
#define FM_ETHERNET_MAC0_CHRBAR                   *((volatile uint32_t*)(0x40065054UL))
#define FM4_ETHERNET_MAC0_CHRBAR                  *((volatile uint32_t*)(0x40065054UL))

/*******************************************************************************
* EXBUS Registers EXBUS
*   Register Definition
*******************************************************************************/
#define FM_EXBUS_MODE0                            *((volatile uint32_t*)(0x4003F000UL))
#define FM4_EXBUS_MODE0                           *((volatile uint32_t*)(0x4003F000UL))
#define FM_EXBUS_MODE1                            *((volatile uint32_t*)(0x4003F004UL))
#define FM4_EXBUS_MODE1                           *((volatile uint32_t*)(0x4003F004UL))
#define FM_EXBUS_MODE2                            *((volatile uint32_t*)(0x4003F008UL))
#define FM4_EXBUS_MODE2                           *((volatile uint32_t*)(0x4003F008UL))
#define FM_EXBUS_MODE3                            *((volatile uint32_t*)(0x4003F00CUL))
#define FM4_EXBUS_MODE3                           *((volatile uint32_t*)(0x4003F00CUL))
#define FM_EXBUS_MODE4                            *((volatile uint32_t*)(0x4003F010UL))
#define FM4_EXBUS_MODE4                           *((volatile uint32_t*)(0x4003F010UL))
#define FM_EXBUS_MODE5                            *((volatile uint32_t*)(0x4003F014UL))
#define FM4_EXBUS_MODE5                           *((volatile uint32_t*)(0x4003F014UL))
#define FM_EXBUS_MODE6                            *((volatile uint32_t*)(0x4003F018UL))
#define FM4_EXBUS_MODE6                           *((volatile uint32_t*)(0x4003F018UL))
#define FM_EXBUS_MODE7                            *((volatile uint32_t*)(0x4003F01CUL))
#define FM4_EXBUS_MODE7                           *((volatile uint32_t*)(0x4003F01CUL))
#define FM_EXBUS_TIM0                             *((volatile uint32_t*)(0x4003F020UL))
#define FM4_EXBUS_TIM0                            *((volatile uint32_t*)(0x4003F020UL))
#define FM_EXBUS_TIM1                             *((volatile uint32_t*)(0x4003F024UL))
#define FM4_EXBUS_TIM1                            *((volatile uint32_t*)(0x4003F024UL))
#define FM_EXBUS_TIM2                             *((volatile uint32_t*)(0x4003F028UL))
#define FM4_EXBUS_TIM2                            *((volatile uint32_t*)(0x4003F028UL))
#define FM_EXBUS_TIM3                             *((volatile uint32_t*)(0x4003F02CUL))
#define FM4_EXBUS_TIM3                            *((volatile uint32_t*)(0x4003F02CUL))
#define FM_EXBUS_TIM4                             *((volatile uint32_t*)(0x4003F030UL))
#define FM4_EXBUS_TIM4                            *((volatile uint32_t*)(0x4003F030UL))
#define FM_EXBUS_TIM5                             *((volatile uint32_t*)(0x4003F034UL))
#define FM4_EXBUS_TIM5                            *((volatile uint32_t*)(0x4003F034UL))
#define FM_EXBUS_TIM6                             *((volatile uint32_t*)(0x4003F038UL))
#define FM4_EXBUS_TIM6                            *((volatile uint32_t*)(0x4003F038UL))
#define FM_EXBUS_TIM7                             *((volatile uint32_t*)(0x4003F03CUL))
#define FM4_EXBUS_TIM7                            *((volatile uint32_t*)(0x4003F03CUL))
#define FM_EXBUS_AREA0                            *((volatile uint32_t*)(0x4003F040UL))
#define FM4_EXBUS_AREA0                           *((volatile uint32_t*)(0x4003F040UL))
#define FM_EXBUS_AREA1                            *((volatile uint32_t*)(0x4003F044UL))
#define FM4_EXBUS_AREA1                           *((volatile uint32_t*)(0x4003F044UL))
#define FM_EXBUS_AREA2                            *((volatile uint32_t*)(0x4003F048UL))
#define FM4_EXBUS_AREA2                           *((volatile uint32_t*)(0x4003F048UL))
#define FM_EXBUS_AREA3                            *((volatile uint32_t*)(0x4003F04CUL))
#define FM4_EXBUS_AREA3                           *((volatile uint32_t*)(0x4003F04CUL))
#define FM_EXBUS_AREA4                            *((volatile uint32_t*)(0x4003F050UL))
#define FM4_EXBUS_AREA4                           *((volatile uint32_t*)(0x4003F050UL))
#define FM_EXBUS_AREA5                            *((volatile uint32_t*)(0x4003F054UL))
#define FM4_EXBUS_AREA5                           *((volatile uint32_t*)(0x4003F054UL))
#define FM_EXBUS_AREA6                            *((volatile uint32_t*)(0x4003F058UL))
#define FM4_EXBUS_AREA6                           *((volatile uint32_t*)(0x4003F058UL))
#define FM_EXBUS_AREA7                            *((volatile uint32_t*)(0x4003F05CUL))
#define FM4_EXBUS_AREA7                           *((volatile uint32_t*)(0x4003F05CUL))
#define FM_EXBUS_ATIM0                            *((volatile uint32_t*)(0x4003F060UL))
#define FM4_EXBUS_ATIM0                           *((volatile uint32_t*)(0x4003F060UL))
#define FM_EXBUS_ATIM1                            *((volatile uint32_t*)(0x4003F064UL))
#define FM4_EXBUS_ATIM1                           *((volatile uint32_t*)(0x4003F064UL))
#define FM_EXBUS_ATIM2                            *((volatile uint32_t*)(0x4003F068UL))
#define FM4_EXBUS_ATIM2                           *((volatile uint32_t*)(0x4003F068UL))
#define FM_EXBUS_ATIM3                            *((volatile uint32_t*)(0x4003F06CUL))
#define FM4_EXBUS_ATIM3                           *((volatile uint32_t*)(0x4003F06CUL))
#define FM_EXBUS_ATIM4                            *((volatile uint32_t*)(0x4003F070UL))
#define FM4_EXBUS_ATIM4                           *((volatile uint32_t*)(0x4003F070UL))
#define FM_EXBUS_ATIM5                            *((volatile uint32_t*)(0x4003F074UL))
#define FM4_EXBUS_ATIM5                           *((volatile uint32_t*)(0x4003F074UL))
#define FM_EXBUS_ATIM6                            *((volatile uint32_t*)(0x4003F078UL))
#define FM4_EXBUS_ATIM6                           *((volatile uint32_t*)(0x4003F078UL))
#define FM_EXBUS_ATIM7                            *((volatile uint32_t*)(0x4003F07CUL))
#define FM4_EXBUS_ATIM7                           *((volatile uint32_t*)(0x4003F07CUL))
#define FM_EXBUS_SDMODE                           *((volatile uint32_t*)(0x4003F100UL))
#define FM4_EXBUS_SDMODE                          *((volatile uint32_t*)(0x4003F100UL))
#define FM_EXBUS_REFTIM                           *((volatile uint32_t*)(0x4003F104UL))
#define FM4_EXBUS_REFTIM                          *((volatile uint32_t*)(0x4003F104UL))
#define FM_EXBUS_PWRDWN                           *((volatile uint32_t*)(0x4003F108UL))
#define FM4_EXBUS_PWRDWN                          *((volatile uint32_t*)(0x4003F108UL))
#define FM_EXBUS_SDTIM                            *((volatile uint32_t*)(0x4003F10CUL))
#define FM4_EXBUS_SDTIM                           *((volatile uint32_t*)(0x4003F10CUL))
#define FM_EXBUS_SDCMD                            *((volatile uint32_t*)(0x4003F110UL))
#define FM4_EXBUS_SDCMD                           *((volatile uint32_t*)(0x4003F110UL))
#define FM_EXBUS_MEMCERR                          *((volatile uint32_t*)(0x4003F200UL))
#define FM4_EXBUS_MEMCERR                         *((volatile uint32_t*)(0x4003F200UL))
#define FM_EXBUS_DCLKR                            *((volatile uint32_t*)(0x4003F300UL))
#define FM4_EXBUS_DCLKR                           *((volatile uint32_t*)(0x4003F300UL))
#define FM_EXBUS_EST                              *((volatile uint32_t*)(0x4003F304UL))
#define FM4_EXBUS_EST                             *((volatile uint32_t*)(0x4003F304UL))
#define FM_EXBUS_WEAD                             *((volatile uint32_t*)(0x4003F308UL))
#define FM4_EXBUS_WEAD                            *((volatile uint32_t*)(0x4003F308UL))
#define FM_EXBUS_ESCLR                            *((volatile uint32_t*)(0x4003F30CUL))
#define FM4_EXBUS_ESCLR                           *((volatile uint32_t*)(0x4003F30CUL))
#define FM_EXBUS_AMODE                            *((volatile uint32_t*)(0x4003F310UL))
#define FM4_EXBUS_AMODE                           *((volatile uint32_t*)(0x4003F310UL))

/*******************************************************************************
* EXTI Registers EXTI
*   Register Definition
*******************************************************************************/
#define FM_EXTI_ENIR                              *((volatile uint32_t*)(0x40030000UL))
#define FM4_EXTI_ENIR                             *((volatile uint32_t*)(0x40030000UL))
#define FM_EXTI_EIRR                              *((volatile uint32_t*)(0x40030004UL))
#define FM4_EXTI_EIRR                             *((volatile uint32_t*)(0x40030004UL))
#define FM_EXTI_EICL                              *((volatile uint32_t*)(0x40030008UL))
#define FM4_EXTI_EICL                             *((volatile uint32_t*)(0x40030008UL))
#define FM_EXTI_ELVR                              *((volatile uint32_t*)(0x4003000CUL))
#define FM4_EXTI_ELVR                             *((volatile uint32_t*)(0x4003000CUL))
#define FM_EXTI_ELVR1                             *((volatile uint32_t*)(0x40030010UL))
#define FM4_EXTI_ELVR1                            *((volatile uint32_t*)(0x40030010UL))
#define FM_EXTI_NMIRR                             *((volatile uint16_t*)(0x40030014UL))
#define FM4_EXTI_NMIRR                            *((volatile uint16_t*)(0x40030014UL))
#define FM_EXTI_NMICL                             *((volatile uint16_t*)(0x40030018UL))
#define FM4_EXTI_NMICL                            *((volatile uint16_t*)(0x40030018UL))

/*******************************************************************************
* FLASH_IF Registers FLASH_IF
*   Register Definition
*******************************************************************************/
#define FM_FLASH_IF_FASZR                         *((volatile uint32_t*)(0x40000000UL))
#define FM4_FLASH_IF_FASZR                        *((volatile uint32_t*)(0x40000000UL))
#define FM_FLASH_IF_FRWTR                         *((volatile uint32_t*)(0x40000004UL))
#define FM4_FLASH_IF_FRWTR                        *((volatile uint32_t*)(0x40000004UL))
#define FM_FLASH_IF_FSTR                          *((volatile uint32_t*)(0x40000008UL))
#define FM4_FLASH_IF_FSTR                         *((volatile uint32_t*)(0x40000008UL))
#define FM_FLASH_IF_FSYNDN                        *((volatile uint32_t*)(0x40000010UL))
#define FM4_FLASH_IF_FSYNDN                       *((volatile uint32_t*)(0x40000010UL))
#define FM_FLASH_IF_FBFCR                         *((volatile uint32_t*)(0x40000014UL))
#define FM4_FLASH_IF_FBFCR                        *((volatile uint32_t*)(0x40000014UL))
#define FM_FLASH_IF_FICR                          *((volatile uint32_t*)(0x40000020UL))
#define FM4_FLASH_IF_FICR                         *((volatile uint32_t*)(0x40000020UL))
#define FM_FLASH_IF_FISR                          *((volatile uint32_t*)(0x40000024UL))
#define FM4_FLASH_IF_FISR                         *((volatile uint32_t*)(0x40000024UL))
#define FM_FLASH_IF_FICLR                         *((volatile uint32_t*)(0x40000028UL))
#define FM4_FLASH_IF_FICLR                        *((volatile uint32_t*)(0x40000028UL))
#define FM_FLASH_IF_DFCTRLR                       *((volatile uint32_t*)(0x40000030UL))
#define FM4_FLASH_IF_DFCTRLR                      *((volatile uint32_t*)(0x40000030UL))
#define FM_FLASH_IF_CRTRMM                        *((volatile uint32_t*)(0x40000100UL))
#define FM4_FLASH_IF_CRTRMM                       *((volatile uint32_t*)(0x40000100UL))
#define FM_FLASH_IF_FGPDM1                        *((volatile uint32_t*)(0x40000110UL))
#define FM4_FLASH_IF_FGPDM1                       *((volatile uint32_t*)(0x40000110UL))
#define FM_FLASH_IF_FGPDM2                        *((volatile uint32_t*)(0x40000114UL))
#define FM4_FLASH_IF_FGPDM2                       *((volatile uint32_t*)(0x40000114UL))
#define FM_FLASH_IF_FGPDM3                        *((volatile uint32_t*)(0x40000118UL))
#define FM4_FLASH_IF_FGPDM3                       *((volatile uint32_t*)(0x40000118UL))
#define FM_FLASH_IF_FGPDM4                        *((volatile uint32_t*)(0x4000011CUL))
#define FM4_FLASH_IF_FGPDM4                       *((volatile uint32_t*)(0x4000011CUL))

/*******************************************************************************
* GPIO Registers GPIO
*   Register Definition
*******************************************************************************/
#define FM_GPIO_PFR0                              *((volatile uint32_t*)(0x4006F000UL))
#define FM4_GPIO_PFR0                             *((volatile uint32_t*)(0x4006F000UL))
#define FM_GPIO_PFR1                              *((volatile uint32_t*)(0x4006F004UL))
#define FM4_GPIO_PFR1                             *((volatile uint32_t*)(0x4006F004UL))
#define FM_GPIO_PFR2                              *((volatile uint32_t*)(0x4006F008UL))
#define FM4_GPIO_PFR2                             *((volatile uint32_t*)(0x4006F008UL))
#define FM_GPIO_PFR3                              *((volatile uint32_t*)(0x4006F00CUL))
#define FM4_GPIO_PFR3                             *((volatile uint32_t*)(0x4006F00CUL))
#define FM_GPIO_PFR4                              *((volatile uint32_t*)(0x4006F010UL))
#define FM4_GPIO_PFR4                             *((volatile uint32_t*)(0x4006F010UL))
#define FM_GPIO_PFR5                              *((volatile uint32_t*)(0x4006F014UL))
#define FM4_GPIO_PFR5                             *((volatile uint32_t*)(0x4006F014UL))
#define FM_GPIO_PFR6                              *((volatile uint32_t*)(0x4006F018UL))
#define FM4_GPIO_PFR6                             *((volatile uint32_t*)(0x4006F018UL))
#define FM_GPIO_PFR7                              *((volatile uint32_t*)(0x4006F01CUL))
#define FM4_GPIO_PFR7                             *((volatile uint32_t*)(0x4006F01CUL))
#define FM_GPIO_PFR8                              *((volatile uint32_t*)(0x4006F020UL))
#define FM4_GPIO_PFR8                             *((volatile uint32_t*)(0x4006F020UL))
#define FM_GPIO_PFR9                              *((volatile uint32_t*)(0x4006F024UL))
#define FM4_GPIO_PFR9                             *((volatile uint32_t*)(0x4006F024UL))
#define FM_GPIO_PFRA                              *((volatile uint32_t*)(0x4006F028UL))
#define FM4_GPIO_PFRA                             *((volatile uint32_t*)(0x4006F028UL))
#define FM_GPIO_PFRB                              *((volatile uint32_t*)(0x4006F02CUL))
#define FM4_GPIO_PFRB                             *((volatile uint32_t*)(0x4006F02CUL))
#define FM_GPIO_PFRC                              *((volatile uint32_t*)(0x4006F030UL))
#define FM4_GPIO_PFRC                             *((volatile uint32_t*)(0x4006F030UL))
#define FM_GPIO_PFRD                              *((volatile uint32_t*)(0x4006F034UL))
#define FM4_GPIO_PFRD                             *((volatile uint32_t*)(0x4006F034UL))
#define FM_GPIO_PFRE                              *((volatile uint32_t*)(0x4006F038UL))
#define FM4_GPIO_PFRE                             *((volatile uint32_t*)(0x4006F038UL))
#define FM_GPIO_PFRF                              *((volatile uint32_t*)(0x4006F03CUL))
#define FM4_GPIO_PFRF                             *((volatile uint32_t*)(0x4006F03CUL))
#define FM_GPIO_PCR0                              *((volatile uint32_t*)(0x4006F100UL))
#define FM4_GPIO_PCR0                             *((volatile uint32_t*)(0x4006F100UL))
#define FM_GPIO_PCR1                              *((volatile uint32_t*)(0x4006F104UL))
#define FM4_GPIO_PCR1                             *((volatile uint32_t*)(0x4006F104UL))
#define FM_GPIO_PCR2                              *((volatile uint32_t*)(0x4006F108UL))
#define FM4_GPIO_PCR2                             *((volatile uint32_t*)(0x4006F108UL))
#define FM_GPIO_PCR3                              *((volatile uint32_t*)(0x4006F10CUL))
#define FM4_GPIO_PCR3                             *((volatile uint32_t*)(0x4006F10CUL))
#define FM_GPIO_PCR4                              *((volatile uint32_t*)(0x4006F110UL))
#define FM4_GPIO_PCR4                             *((volatile uint32_t*)(0x4006F110UL))
#define FM_GPIO_PCR5                              *((volatile uint32_t*)(0x4006F114UL))
#define FM4_GPIO_PCR5                             *((volatile uint32_t*)(0x4006F114UL))
#define FM_GPIO_PCR6                              *((volatile uint32_t*)(0x4006F118UL))
#define FM4_GPIO_PCR6                             *((volatile uint32_t*)(0x4006F118UL))
#define FM_GPIO_PCR7                              *((volatile uint32_t*)(0x4006F11CUL))
#define FM4_GPIO_PCR7                             *((volatile uint32_t*)(0x4006F11CUL))
#define FM_GPIO_PCR9                              *((volatile uint32_t*)(0x4006F124UL))
#define FM4_GPIO_PCR9                             *((volatile uint32_t*)(0x4006F124UL))
#define FM_GPIO_PCRA                              *((volatile uint32_t*)(0x4006F128UL))
#define FM4_GPIO_PCRA                             *((volatile uint32_t*)(0x4006F128UL))
#define FM_GPIO_PCRB                              *((volatile uint32_t*)(0x4006F12CUL))
#define FM4_GPIO_PCRB                             *((volatile uint32_t*)(0x4006F12CUL))
#define FM_GPIO_PCRC                              *((volatile uint32_t*)(0x4006F130UL))
#define FM4_GPIO_PCRC                             *((volatile uint32_t*)(0x4006F130UL))
#define FM_GPIO_PCRD                              *((volatile uint32_t*)(0x4006F134UL))
#define FM4_GPIO_PCRD                             *((volatile uint32_t*)(0x4006F134UL))
#define FM_GPIO_PCRE                              *((volatile uint32_t*)(0x4006F138UL))
#define FM4_GPIO_PCRE                             *((volatile uint32_t*)(0x4006F138UL))
#define FM_GPIO_PCRF                              *((volatile uint32_t*)(0x4006F13CUL))
#define FM4_GPIO_PCRF                             *((volatile uint32_t*)(0x4006F13CUL))
#define FM_GPIO_DDR0                              *((volatile uint32_t*)(0x4006F200UL))
#define FM4_GPIO_DDR0                             *((volatile uint32_t*)(0x4006F200UL))
#define FM_GPIO_DDR1                              *((volatile uint32_t*)(0x4006F204UL))
#define FM4_GPIO_DDR1                             *((volatile uint32_t*)(0x4006F204UL))
#define FM_GPIO_DDR2                              *((volatile uint32_t*)(0x4006F208UL))
#define FM4_GPIO_DDR2                             *((volatile uint32_t*)(0x4006F208UL))
#define FM_GPIO_DDR3                              *((volatile uint32_t*)(0x4006F20CUL))
#define FM4_GPIO_DDR3                             *((volatile uint32_t*)(0x4006F20CUL))
#define FM_GPIO_DDR4                              *((volatile uint32_t*)(0x4006F210UL))
#define FM4_GPIO_DDR4                             *((volatile uint32_t*)(0x4006F210UL))
#define FM_GPIO_DDR5                              *((volatile uint32_t*)(0x4006F214UL))
#define FM4_GPIO_DDR5                             *((volatile uint32_t*)(0x4006F214UL))
#define FM_GPIO_DDR6                              *((volatile uint32_t*)(0x4006F218UL))
#define FM4_GPIO_DDR6                             *((volatile uint32_t*)(0x4006F218UL))
#define FM_GPIO_DDR7                              *((volatile uint32_t*)(0x4006F21CUL))
#define FM4_GPIO_DDR7                             *((volatile uint32_t*)(0x4006F21CUL))
#define FM_GPIO_DDR8                              *((volatile uint32_t*)(0x4006F220UL))
#define FM4_GPIO_DDR8                             *((volatile uint32_t*)(0x4006F220UL))
#define FM_GPIO_DDR9                              *((volatile uint32_t*)(0x4006F224UL))
#define FM4_GPIO_DDR9                             *((volatile uint32_t*)(0x4006F224UL))
#define FM_GPIO_DDRA                              *((volatile uint32_t*)(0x4006F228UL))
#define FM4_GPIO_DDRA                             *((volatile uint32_t*)(0x4006F228UL))
#define FM_GPIO_DDRB                              *((volatile uint32_t*)(0x4006F22CUL))
#define FM4_GPIO_DDRB                             *((volatile uint32_t*)(0x4006F22CUL))
#define FM_GPIO_DDRC                              *((volatile uint32_t*)(0x4006F230UL))
#define FM4_GPIO_DDRC                             *((volatile uint32_t*)(0x4006F230UL))
#define FM_GPIO_DDRD                              *((volatile uint32_t*)(0x4006F234UL))
#define FM4_GPIO_DDRD                             *((volatile uint32_t*)(0x4006F234UL))
#define FM_GPIO_DDRE                              *((volatile uint32_t*)(0x4006F238UL))
#define FM4_GPIO_DDRE                             *((volatile uint32_t*)(0x4006F238UL))
#define FM_GPIO_DDRF                              *((volatile uint32_t*)(0x4006F23CUL))
#define FM4_GPIO_DDRF                             *((volatile uint32_t*)(0x4006F23CUL))
#define FM_GPIO_PDIR0                             *((volatile uint32_t*)(0x4006F300UL))
#define FM4_GPIO_PDIR0                            *((volatile uint32_t*)(0x4006F300UL))
#define FM_GPIO_PDIR1                             *((volatile uint32_t*)(0x4006F304UL))
#define FM4_GPIO_PDIR1                            *((volatile uint32_t*)(0x4006F304UL))
#define FM_GPIO_PDIR2                             *((volatile uint32_t*)(0x4006F308UL))
#define FM4_GPIO_PDIR2                            *((volatile uint32_t*)(0x4006F308UL))
#define FM_GPIO_PDIR3                             *((volatile uint32_t*)(0x4006F30CUL))
#define FM4_GPIO_PDIR3                            *((volatile uint32_t*)(0x4006F30CUL))
#define FM_GPIO_PDIR4                             *((volatile uint32_t*)(0x4006F310UL))
#define FM4_GPIO_PDIR4                            *((volatile uint32_t*)(0x4006F310UL))
#define FM_GPIO_PDIR5                             *((volatile uint32_t*)(0x4006F314UL))
#define FM4_GPIO_PDIR5                            *((volatile uint32_t*)(0x4006F314UL))
#define FM_GPIO_PDIR6                             *((volatile uint32_t*)(0x4006F318UL))
#define FM4_GPIO_PDIR6                            *((volatile uint32_t*)(0x4006F318UL))
#define FM_GPIO_PDIR7                             *((volatile uint32_t*)(0x4006F31CUL))
#define FM4_GPIO_PDIR7                            *((volatile uint32_t*)(0x4006F31CUL))
#define FM_GPIO_PDIR8                             *((volatile uint32_t*)(0x4006F320UL))
#define FM4_GPIO_PDIR8                            *((volatile uint32_t*)(0x4006F320UL))
#define FM_GPIO_PDIR9                             *((volatile uint32_t*)(0x4006F324UL))
#define FM4_GPIO_PDIR9                            *((volatile uint32_t*)(0x4006F324UL))
#define FM_GPIO_PDIRA                             *((volatile uint32_t*)(0x4006F328UL))
#define FM4_GPIO_PDIRA                            *((volatile uint32_t*)(0x4006F328UL))
#define FM_GPIO_PDIRB                             *((volatile uint32_t*)(0x4006F32CUL))
#define FM4_GPIO_PDIRB                            *((volatile uint32_t*)(0x4006F32CUL))
#define FM_GPIO_PDIRC                             *((volatile uint32_t*)(0x4006F330UL))
#define FM4_GPIO_PDIRC                            *((volatile uint32_t*)(0x4006F330UL))
#define FM_GPIO_PDIRD                             *((volatile uint32_t*)(0x4006F334UL))
#define FM4_GPIO_PDIRD                            *((volatile uint32_t*)(0x4006F334UL))
#define FM_GPIO_PDIRE                             *((volatile uint32_t*)(0x4006F338UL))
#define FM4_GPIO_PDIRE                            *((volatile uint32_t*)(0x4006F338UL))
#define FM_GPIO_PDIRF                             *((volatile uint32_t*)(0x4006F33CUL))
#define FM4_GPIO_PDIRF                            *((volatile uint32_t*)(0x4006F33CUL))
#define FM_GPIO_PDOR0                             *((volatile uint32_t*)(0x4006F400UL))
#define FM4_GPIO_PDOR0                            *((volatile uint32_t*)(0x4006F400UL))
#define FM_GPIO_PDOR1                             *((volatile uint32_t*)(0x4006F404UL))
#define FM4_GPIO_PDOR1                            *((volatile uint32_t*)(0x4006F404UL))
#define FM_GPIO_PDOR2                             *((volatile uint32_t*)(0x4006F408UL))
#define FM4_GPIO_PDOR2                            *((volatile uint32_t*)(0x4006F408UL))
#define FM_GPIO_PDOR3                             *((volatile uint32_t*)(0x4006F40CUL))
#define FM4_GPIO_PDOR3                            *((volatile uint32_t*)(0x4006F40CUL))
#define FM_GPIO_PDOR4                             *((volatile uint32_t*)(0x4006F410UL))
#define FM4_GPIO_PDOR4                            *((volatile uint32_t*)(0x4006F410UL))
#define FM_GPIO_PDOR5                             *((volatile uint32_t*)(0x4006F414UL))
#define FM4_GPIO_PDOR5                            *((volatile uint32_t*)(0x4006F414UL))
#define FM_GPIO_PDOR6                             *((volatile uint32_t*)(0x4006F418UL))
#define FM4_GPIO_PDOR6                            *((volatile uint32_t*)(0x4006F418UL))
#define FM_GPIO_PDOR7                             *((volatile uint32_t*)(0x4006F41CUL))
#define FM4_GPIO_PDOR7                            *((volatile uint32_t*)(0x4006F41CUL))
#define FM_GPIO_PDOR8                             *((volatile uint32_t*)(0x4006F420UL))
#define FM4_GPIO_PDOR8                            *((volatile uint32_t*)(0x4006F420UL))
#define FM_GPIO_PDOR9                             *((volatile uint32_t*)(0x4006F424UL))
#define FM4_GPIO_PDOR9                            *((volatile uint32_t*)(0x4006F424UL))
#define FM_GPIO_PDORA                             *((volatile uint32_t*)(0x4006F428UL))
#define FM4_GPIO_PDORA                            *((volatile uint32_t*)(0x4006F428UL))
#define FM_GPIO_PDORB                             *((volatile uint32_t*)(0x4006F42CUL))
#define FM4_GPIO_PDORB                            *((volatile uint32_t*)(0x4006F42CUL))
#define FM_GPIO_PDORC                             *((volatile uint32_t*)(0x4006F430UL))
#define FM4_GPIO_PDORC                            *((volatile uint32_t*)(0x4006F430UL))
#define FM_GPIO_PDORD                             *((volatile uint32_t*)(0x4006F434UL))
#define FM4_GPIO_PDORD                            *((volatile uint32_t*)(0x4006F434UL))
#define FM_GPIO_PDORE                             *((volatile uint32_t*)(0x4006F438UL))
#define FM4_GPIO_PDORE                            *((volatile uint32_t*)(0x4006F438UL))
#define FM_GPIO_PDORF                             *((volatile uint32_t*)(0x4006F43CUL))
#define FM4_GPIO_PDORF                            *((volatile uint32_t*)(0x4006F43CUL))
#define FM_GPIO_ADE                               *((volatile uint32_t*)(0x4006F500UL))
#define FM4_GPIO_ADE                              *((volatile uint32_t*)(0x4006F500UL))
#define FM_GPIO_SPSR                              *((volatile uint32_t*)(0x4006F580UL))
#define FM4_GPIO_SPSR                             *((volatile uint32_t*)(0x4006F580UL))
#define FM_GPIO_EPFR00                            *((volatile uint32_t*)(0x4006F600UL))
#define FM4_GPIO_EPFR00                           *((volatile uint32_t*)(0x4006F600UL))
#define FM_GPIO_EPFR01                            *((volatile uint32_t*)(0x4006F604UL))
#define FM4_GPIO_EPFR01                           *((volatile uint32_t*)(0x4006F604UL))
#define FM_GPIO_EPFR02                            *((volatile uint32_t*)(0x4006F608UL))
#define FM4_GPIO_EPFR02                           *((volatile uint32_t*)(0x4006F608UL))
#define FM_GPIO_EPFR03                            *((volatile uint32_t*)(0x4006F60CUL))
#define FM4_GPIO_EPFR03                           *((volatile uint32_t*)(0x4006F60CUL))
#define FM_GPIO_EPFR04                            *((volatile uint32_t*)(0x4006F610UL))
#define FM4_GPIO_EPFR04                           *((volatile uint32_t*)(0x4006F610UL))
#define FM_GPIO_EPFR05                            *((volatile uint32_t*)(0x4006F614UL))
#define FM4_GPIO_EPFR05                           *((volatile uint32_t*)(0x4006F614UL))
#define FM_GPIO_EPFR06                            *((volatile uint32_t*)(0x4006F618UL))
#define FM4_GPIO_EPFR06                           *((volatile uint32_t*)(0x4006F618UL))
#define FM_GPIO_EPFR07                            *((volatile uint32_t*)(0x4006F61CUL))
#define FM4_GPIO_EPFR07                           *((volatile uint32_t*)(0x4006F61CUL))
#define FM_GPIO_EPFR08                            *((volatile uint32_t*)(0x4006F620UL))
#define FM4_GPIO_EPFR08                           *((volatile uint32_t*)(0x4006F620UL))
#define FM_GPIO_EPFR09                            *((volatile uint32_t*)(0x4006F624UL))
#define FM4_GPIO_EPFR09                           *((volatile uint32_t*)(0x4006F624UL))
#define FM_GPIO_EPFR10                            *((volatile uint32_t*)(0x4006F628UL))
#define FM4_GPIO_EPFR10                           *((volatile uint32_t*)(0x4006F628UL))
#define FM_GPIO_EPFR11                            *((volatile uint32_t*)(0x4006F62CUL))
#define FM4_GPIO_EPFR11                           *((volatile uint32_t*)(0x4006F62CUL))
#define FM_GPIO_EPFR12                            *((volatile uint32_t*)(0x4006F630UL))
#define FM4_GPIO_EPFR12                           *((volatile uint32_t*)(0x4006F630UL))
#define FM_GPIO_EPFR13                            *((volatile uint32_t*)(0x4006F634UL))
#define FM4_GPIO_EPFR13                           *((volatile uint32_t*)(0x4006F634UL))
#define FM_GPIO_EPFR14                            *((volatile uint32_t*)(0x4006F638UL))
#define FM4_GPIO_EPFR14                           *((volatile uint32_t*)(0x4006F638UL))
#define FM_GPIO_EPFR15                            *((volatile uint32_t*)(0x4006F63CUL))
#define FM4_GPIO_EPFR15                           *((volatile uint32_t*)(0x4006F63CUL))
#define FM_GPIO_EPFR16                            *((volatile uint32_t*)(0x4006F640UL))
#define FM4_GPIO_EPFR16                           *((volatile uint32_t*)(0x4006F640UL))
#define FM_GPIO_EPFR17                            *((volatile uint32_t*)(0x4006F644UL))
#define FM4_GPIO_EPFR17                           *((volatile uint32_t*)(0x4006F644UL))
#define FM_GPIO_EPFR18                            *((volatile uint32_t*)(0x4006F648UL))
#define FM4_GPIO_EPFR18                           *((volatile uint32_t*)(0x4006F648UL))
#define FM_GPIO_EPFR19                            *((volatile uint32_t*)(0x4006F64CUL))
#define FM4_GPIO_EPFR19                           *((volatile uint32_t*)(0x4006F64CUL))
#define FM_GPIO_EPFR20                            *((volatile uint32_t*)(0x4006F650UL))
#define FM4_GPIO_EPFR20                           *((volatile uint32_t*)(0x4006F650UL))
#define FM_GPIO_EPFR21                            *((volatile uint32_t*)(0x4006F654UL))
#define FM4_GPIO_EPFR21                           *((volatile uint32_t*)(0x4006F654UL))
#define FM_GPIO_EPFR22                            *((volatile uint32_t*)(0x4006F658UL))
#define FM4_GPIO_EPFR22                           *((volatile uint32_t*)(0x4006F658UL))
#define FM_GPIO_EPFR23                            *((volatile uint32_t*)(0x4006F65CUL))
#define FM4_GPIO_EPFR23                           *((volatile uint32_t*)(0x4006F65CUL))
#define FM_GPIO_EPFR24                            *((volatile uint32_t*)(0x4006F660UL))
#define FM4_GPIO_EPFR24                           *((volatile uint32_t*)(0x4006F660UL))
#define FM_GPIO_EPFR25                            *((volatile uint32_t*)(0x4006F664UL))
#define FM4_GPIO_EPFR25                           *((volatile uint32_t*)(0x4006F664UL))
#define FM_GPIO_EPFR26                            *((volatile uint32_t*)(0x4006F668UL))
#define FM4_GPIO_EPFR26                           *((volatile uint32_t*)(0x4006F668UL))
#define FM_GPIO_PZR0                              *((volatile uint32_t*)(0x4006F700UL))
#define FM4_GPIO_PZR0                             *((volatile uint32_t*)(0x4006F700UL))
#define FM_GPIO_PZR1                              *((volatile uint32_t*)(0x4006F704UL))
#define FM4_GPIO_PZR1                             *((volatile uint32_t*)(0x4006F704UL))
#define FM_GPIO_PZR2                              *((volatile uint32_t*)(0x4006F708UL))
#define FM4_GPIO_PZR2                             *((volatile uint32_t*)(0x4006F708UL))
#define FM_GPIO_PZR3                              *((volatile uint32_t*)(0x4006F70CUL))
#define FM4_GPIO_PZR3                             *((volatile uint32_t*)(0x4006F70CUL))
#define FM_GPIO_PZR4                              *((volatile uint32_t*)(0x4006F710UL))
#define FM4_GPIO_PZR4                             *((volatile uint32_t*)(0x4006F710UL))
#define FM_GPIO_PZR5                              *((volatile uint32_t*)(0x4006F714UL))
#define FM4_GPIO_PZR5                             *((volatile uint32_t*)(0x4006F714UL))
#define FM_GPIO_PZR6                              *((volatile uint32_t*)(0x4006F718UL))
#define FM4_GPIO_PZR6                             *((volatile uint32_t*)(0x4006F718UL))
#define FM_GPIO_PZR7                              *((volatile uint32_t*)(0x4006F71CUL))
#define FM4_GPIO_PZR7                             *((volatile uint32_t*)(0x4006F71CUL))
#define FM_GPIO_PZR8                              *((volatile uint32_t*)(0x4006F720UL))
#define FM4_GPIO_PZR8                             *((volatile uint32_t*)(0x4006F720UL))
#define FM_GPIO_PZR9                              *((volatile uint32_t*)(0x4006F724UL))
#define FM4_GPIO_PZR9                             *((volatile uint32_t*)(0x4006F724UL))
#define FM_GPIO_PZRA                              *((volatile uint32_t*)(0x4006F728UL))
#define FM4_GPIO_PZRA                             *((volatile uint32_t*)(0x4006F728UL))
#define FM_GPIO_PZRB                              *((volatile uint32_t*)(0x4006F72CUL))
#define FM4_GPIO_PZRB                             *((volatile uint32_t*)(0x4006F72CUL))
#define FM_GPIO_PZRC                              *((volatile uint32_t*)(0x4006F730UL))
#define FM4_GPIO_PZRC                             *((volatile uint32_t*)(0x4006F730UL))
#define FM_GPIO_PZRD                              *((volatile uint32_t*)(0x4006F734UL))
#define FM4_GPIO_PZRD                             *((volatile uint32_t*)(0x4006F734UL))
#define FM_GPIO_PZRE                              *((volatile uint32_t*)(0x4006F738UL))
#define FM4_GPIO_PZRE                             *((volatile uint32_t*)(0x4006F738UL))
#define FM_GPIO_PZRF                              *((volatile uint32_t*)(0x4006F73CUL))
#define FM4_GPIO_PZRF                             *((volatile uint32_t*)(0x4006F73CUL))
#define FM_GPIO_PDSR0                             *((volatile uint32_t*)(0x4006F740UL))
#define FM4_GPIO_PDSR0                            *((volatile uint32_t*)(0x4006F740UL))
#define FM_GPIO_PDSR1                             *((volatile uint32_t*)(0x4006F744UL))
#define FM4_GPIO_PDSR1                            *((volatile uint32_t*)(0x4006F744UL))
#define FM_GPIO_PDSR2                             *((volatile uint32_t*)(0x4006F748UL))
#define FM4_GPIO_PDSR2                            *((volatile uint32_t*)(0x4006F748UL))
#define FM_GPIO_PDSR3                             *((volatile uint32_t*)(0x4006F74CUL))
#define FM4_GPIO_PDSR3                            *((volatile uint32_t*)(0x4006F74CUL))
#define FM_GPIO_PDSR4                             *((volatile uint32_t*)(0x4006F750UL))
#define FM4_GPIO_PDSR4                            *((volatile uint32_t*)(0x4006F750UL))
#define FM_GPIO_PDSR5                             *((volatile uint32_t*)(0x4006F754UL))
#define FM4_GPIO_PDSR5                            *((volatile uint32_t*)(0x4006F754UL))
#define FM_GPIO_PDSR6                             *((volatile uint32_t*)(0x4006F758UL))
#define FM4_GPIO_PDSR6                            *((volatile uint32_t*)(0x4006F758UL))
#define FM_GPIO_PDSR7                             *((volatile uint32_t*)(0x4006F75CUL))
#define FM4_GPIO_PDSR7                            *((volatile uint32_t*)(0x4006F75CUL))
#define FM_GPIO_PDSR8                             *((volatile uint32_t*)(0x4006F760UL))
#define FM4_GPIO_PDSR8                            *((volatile uint32_t*)(0x4006F760UL))
#define FM_GPIO_PDSR9                             *((volatile uint32_t*)(0x4006F764UL))
#define FM4_GPIO_PDSR9                            *((volatile uint32_t*)(0x4006F764UL))
#define FM_GPIO_PDSRA                             *((volatile uint32_t*)(0x4006F768UL))
#define FM4_GPIO_PDSRA                            *((volatile uint32_t*)(0x4006F768UL))
#define FM_GPIO_PDSRB                             *((volatile uint32_t*)(0x4006F76CUL))
#define FM4_GPIO_PDSRB                            *((volatile uint32_t*)(0x4006F76CUL))
#define FM_GPIO_PDSRC                             *((volatile uint32_t*)(0x4006F770UL))
#define FM4_GPIO_PDSRC                            *((volatile uint32_t*)(0x4006F770UL))
#define FM_GPIO_PDSRD                             *((volatile uint32_t*)(0x4006F774UL))
#define FM4_GPIO_PDSRD                            *((volatile uint32_t*)(0x4006F774UL))
#define FM_GPIO_PDSRE                             *((volatile uint32_t*)(0x4006F778UL))
#define FM4_GPIO_PDSRE                            *((volatile uint32_t*)(0x4006F778UL))
#define FM_GPIO_PDSRF                             *((volatile uint32_t*)(0x4006F77CUL))
#define FM4_GPIO_PDSRF                            *((volatile uint32_t*)(0x4006F77CUL))

/*******************************************************************************
* HSSPI Registers HSSPI
*   Register Definition
*******************************************************************************/
#define FM_HSSPI_MCTRL                            *((volatile uint32_t*)(0xD0000000UL))
#define FM4_HSSPI_MCTRL                           *((volatile uint32_t*)(0xD0000000UL))
#define FM_HSSPI_PCC0                             *((volatile uint32_t*)(0xD0000004UL))
#define FM4_HSSPI_PCC0                            *((volatile uint32_t*)(0xD0000004UL))
#define FM_HSSPI_PCC1                             *((volatile uint32_t*)(0xD0000008UL))
#define FM4_HSSPI_PCC1                            *((volatile uint32_t*)(0xD0000008UL))
#define FM_HSSPI_PCC2                             *((volatile uint32_t*)(0xD000000CUL))
#define FM4_HSSPI_PCC2                            *((volatile uint32_t*)(0xD000000CUL))
#define FM_HSSPI_PCC3                             *((volatile uint32_t*)(0xD0000010UL))
#define FM4_HSSPI_PCC3                            *((volatile uint32_t*)(0xD0000010UL))
#define FM_HSSPI_TXF                              *((volatile uint32_t*)(0xD0000014UL))
#define FM4_HSSPI_TXF                             *((volatile uint32_t*)(0xD0000014UL))
#define FM_HSSPI_TXE                              *((volatile uint32_t*)(0xD0000018UL))
#define FM4_HSSPI_TXE                             *((volatile uint32_t*)(0xD0000018UL))
#define FM_HSSPI_TXC                              *((volatile uint32_t*)(0xD000001CUL))
#define FM4_HSSPI_TXC                             *((volatile uint32_t*)(0xD000001CUL))
#define FM_HSSPI_RXF                              *((volatile uint32_t*)(0xD0000020UL))
#define FM4_HSSPI_RXF                             *((volatile uint32_t*)(0xD0000020UL))
#define FM_HSSPI_RXE                              *((volatile uint32_t*)(0xD0000024UL))
#define FM4_HSSPI_RXE                             *((volatile uint32_t*)(0xD0000024UL))
#define FM_HSSPI_RXC                              *((volatile uint32_t*)(0xD0000028UL))
#define FM4_HSSPI_RXC                             *((volatile uint32_t*)(0xD0000028UL))
#define FM_HSSPI_FAULTF                           *((volatile uint32_t*)(0xD000002CUL))
#define FM4_HSSPI_FAULTF                          *((volatile uint32_t*)(0xD000002CUL))
#define FM_HSSPI_FAULTC                           *((volatile uint32_t*)(0xD0000030UL))
#define FM4_HSSPI_FAULTC                          *((volatile uint32_t*)(0xD0000030UL))
#define FM_HSSPI_DMCFG                            *((volatile  uint8_t*)(0xD0000034UL))
#define FM4_HSSPI_DMCFG                           *((volatile  uint8_t*)(0xD0000034UL))
#define FM_HSSPI_DMDMAEN                          *((volatile  uint8_t*)(0xD0000035UL))
#define FM4_HSSPI_DMDMAEN                         *((volatile  uint8_t*)(0xD0000035UL))
#define FM_HSSPI_DMSTART                          *((volatile  uint8_t*)(0xD0000038UL))
#define FM4_HSSPI_DMSTART                         *((volatile  uint8_t*)(0xD0000038UL))
#define FM_HSSPI_DMSTOP                           *((volatile  uint8_t*)(0xD0000039UL))
#define FM4_HSSPI_DMSTOP                          *((volatile  uint8_t*)(0xD0000039UL))
#define FM_HSSPI_DMPSEL                           *((volatile  uint8_t*)(0xD000003AUL))
#define FM4_HSSPI_DMPSEL                          *((volatile  uint8_t*)(0xD000003AUL))
#define FM_HSSPI_DMTRP                            *((volatile  uint8_t*)(0xD000003BUL))
#define FM4_HSSPI_DMTRP                           *((volatile  uint8_t*)(0xD000003BUL))
#define FM_HSSPI_DMBCC                            *((volatile uint16_t*)(0xD000003CUL))
#define FM4_HSSPI_DMBCC                           *((volatile uint16_t*)(0xD000003CUL))
#define FM_HSSPI_DMBCS                            *((volatile uint16_t*)(0xD000003EUL))
#define FM4_HSSPI_DMBCS                           *((volatile uint16_t*)(0xD000003EUL))
#define FM_HSSPI_DMSTATUS                         *((volatile uint32_t*)(0xD0000040UL))
#define FM4_HSSPI_DMSTATUS                        *((volatile uint32_t*)(0xD0000040UL))
#define FM_HSSPI_FIFOCFG                          *((volatile uint32_t*)(0xD000004CUL))
#define FM4_HSSPI_FIFOCFG                         *((volatile uint32_t*)(0xD000004CUL))
#define FM_HSSPI_TXFIFO0                          *((volatile uint32_t*)(0xD0000050UL))
#define FM4_HSSPI_TXFIFO0                         *((volatile uint32_t*)(0xD0000050UL))
#define FM_HSSPI_TXFIFO1                          *((volatile uint32_t*)(0xD0000054UL))
#define FM4_HSSPI_TXFIFO1                         *((volatile uint32_t*)(0xD0000054UL))
#define FM_HSSPI_TXFIFO2                          *((volatile uint32_t*)(0xD0000058UL))
#define FM4_HSSPI_TXFIFO2                         *((volatile uint32_t*)(0xD0000058UL))
#define FM_HSSPI_TXFIFO3                          *((volatile uint32_t*)(0xD000005CUL))
#define FM4_HSSPI_TXFIFO3                         *((volatile uint32_t*)(0xD000005CUL))
#define FM_HSSPI_TXFIFO4                          *((volatile uint32_t*)(0xD0000060UL))
#define FM4_HSSPI_TXFIFO4                         *((volatile uint32_t*)(0xD0000060UL))
#define FM_HSSPI_TXFIFO5                          *((volatile uint32_t*)(0xD0000064UL))
#define FM4_HSSPI_TXFIFO5                         *((volatile uint32_t*)(0xD0000064UL))
#define FM_HSSPI_TXFIFO6                          *((volatile uint32_t*)(0xD0000068UL))
#define FM4_HSSPI_TXFIFO6                         *((volatile uint32_t*)(0xD0000068UL))
#define FM_HSSPI_TXFIFO7                          *((volatile uint32_t*)(0xD000006CUL))
#define FM4_HSSPI_TXFIFO7                         *((volatile uint32_t*)(0xD000006CUL))
#define FM_HSSPI_TXFIFO8                          *((volatile uint32_t*)(0xD0000070UL))
#define FM4_HSSPI_TXFIFO8                         *((volatile uint32_t*)(0xD0000070UL))
#define FM_HSSPI_TXFIFO9                          *((volatile uint32_t*)(0xD0000074UL))
#define FM4_HSSPI_TXFIFO9                         *((volatile uint32_t*)(0xD0000074UL))
#define FM_HSSPI_TXFIFO10                         *((volatile uint32_t*)(0xD0000078UL))
#define FM4_HSSPI_TXFIFO10                        *((volatile uint32_t*)(0xD0000078UL))
#define FM_HSSPI_TXFIFO11                         *((volatile uint32_t*)(0xD000007CUL))
#define FM4_HSSPI_TXFIFO11                        *((volatile uint32_t*)(0xD000007CUL))
#define FM_HSSPI_TXFIFO12                         *((volatile uint32_t*)(0xD0000080UL))
#define FM4_HSSPI_TXFIFO12                        *((volatile uint32_t*)(0xD0000080UL))
#define FM_HSSPI_TXFIFO13                         *((volatile uint32_t*)(0xD0000084UL))
#define FM4_HSSPI_TXFIFO13                        *((volatile uint32_t*)(0xD0000084UL))
#define FM_HSSPI_TXFIFO14                         *((volatile uint32_t*)(0xD0000088UL))
#define FM4_HSSPI_TXFIFO14                        *((volatile uint32_t*)(0xD0000088UL))
#define FM_HSSPI_TXFIFO15                         *((volatile uint32_t*)(0xD000008CUL))
#define FM4_HSSPI_TXFIFO15                        *((volatile uint32_t*)(0xD000008CUL))
#define FM_HSSPI_RXFIFO0                          *((volatile uint32_t*)(0xD0000090UL))
#define FM4_HSSPI_RXFIFO0                         *((volatile uint32_t*)(0xD0000090UL))
#define FM_HSSPI_RXFIFO1                          *((volatile uint32_t*)(0xD0000094UL))
#define FM4_HSSPI_RXFIFO1                         *((volatile uint32_t*)(0xD0000094UL))
#define FM_HSSPI_RXFIFO2                          *((volatile uint32_t*)(0xD0000098UL))
#define FM4_HSSPI_RXFIFO2                         *((volatile uint32_t*)(0xD0000098UL))
#define FM_HSSPI_RXFIFO3                          *((volatile uint32_t*)(0xD000009CUL))
#define FM4_HSSPI_RXFIFO3                         *((volatile uint32_t*)(0xD000009CUL))
#define FM_HSSPI_RXFIFO4                          *((volatile uint32_t*)(0xD00000A0UL))
#define FM4_HSSPI_RXFIFO4                         *((volatile uint32_t*)(0xD00000A0UL))
#define FM_HSSPI_RXFIFO5                          *((volatile uint32_t*)(0xD00000A4UL))
#define FM4_HSSPI_RXFIFO5                         *((volatile uint32_t*)(0xD00000A4UL))
#define FM_HSSPI_RXFIFO6                          *((volatile uint32_t*)(0xD00000A8UL))
#define FM4_HSSPI_RXFIFO6                         *((volatile uint32_t*)(0xD00000A8UL))
#define FM_HSSPI_RXFIFO7                          *((volatile uint32_t*)(0xD00000ACUL))
#define FM4_HSSPI_RXFIFO7                         *((volatile uint32_t*)(0xD00000ACUL))
#define FM_HSSPI_RXFIFO8                          *((volatile uint32_t*)(0xD00000B0UL))
#define FM4_HSSPI_RXFIFO8                         *((volatile uint32_t*)(0xD00000B0UL))
#define FM_HSSPI_RXFIFO9                          *((volatile uint32_t*)(0xD00000B4UL))
#define FM4_HSSPI_RXFIFO9                         *((volatile uint32_t*)(0xD00000B4UL))
#define FM_HSSPI_RXFIFO10                         *((volatile uint32_t*)(0xD00000B8UL))
#define FM4_HSSPI_RXFIFO10                        *((volatile uint32_t*)(0xD00000B8UL))
#define FM_HSSPI_RXFIFO11                         *((volatile uint32_t*)(0xD00000BCUL))
#define FM4_HSSPI_RXFIFO11                        *((volatile uint32_t*)(0xD00000BCUL))
#define FM_HSSPI_RXFIFO12                         *((volatile uint32_t*)(0xD00000C0UL))
#define FM4_HSSPI_RXFIFO12                        *((volatile uint32_t*)(0xD00000C0UL))
#define FM_HSSPI_RXFIFO13                         *((volatile uint32_t*)(0xD00000C4UL))
#define FM4_HSSPI_RXFIFO13                        *((volatile uint32_t*)(0xD00000C4UL))
#define FM_HSSPI_RXFIFO14                         *((volatile uint32_t*)(0xD00000C8UL))
#define FM4_HSSPI_RXFIFO14                        *((volatile uint32_t*)(0xD00000C8UL))
#define FM_HSSPI_RXFIFO15                         *((volatile uint32_t*)(0xD00000CCUL))
#define FM4_HSSPI_RXFIFO15                        *((volatile uint32_t*)(0xD00000CCUL))
#define FM_HSSPI_CSCFG                            *((volatile uint32_t*)(0xD00000D0UL))
#define FM4_HSSPI_CSCFG                           *((volatile uint32_t*)(0xD00000D0UL))
#define FM_HSSPI_CSITIME                          *((volatile uint32_t*)(0xD00000D4UL))
#define FM4_HSSPI_CSITIME                         *((volatile uint32_t*)(0xD00000D4UL))
#define FM_HSSPI_CSAEXT                           *((volatile uint32_t*)(0xD00000D8UL))
#define FM4_HSSPI_CSAEXT                          *((volatile uint32_t*)(0xD00000D8UL))
#define FM_HSSPI_RDCSDC0                          *((volatile uint16_t*)(0xD00000DCUL))
#define FM4_HSSPI_RDCSDC0                         *((volatile uint16_t*)(0xD00000DCUL))
#define FM_HSSPI_RDCSDC1                          *((volatile uint16_t*)(0xD00000DEUL))
#define FM4_HSSPI_RDCSDC1                         *((volatile uint16_t*)(0xD00000DEUL))
#define FM_HSSPI_RDCSDC2                          *((volatile uint16_t*)(0xD00000E0UL))
#define FM4_HSSPI_RDCSDC2                         *((volatile uint16_t*)(0xD00000E0UL))
#define FM_HSSPI_RDCSDC3                          *((volatile uint16_t*)(0xD00000E2UL))
#define FM4_HSSPI_RDCSDC3                         *((volatile uint16_t*)(0xD00000E2UL))
#define FM_HSSPI_RDCSDC4                          *((volatile uint16_t*)(0xD00000E4UL))
#define FM4_HSSPI_RDCSDC4                         *((volatile uint16_t*)(0xD00000E4UL))
#define FM_HSSPI_RDCSDC5                          *((volatile uint16_t*)(0xD00000E6UL))
#define FM4_HSSPI_RDCSDC5                         *((volatile uint16_t*)(0xD00000E6UL))
#define FM_HSSPI_RDCSDC6                          *((volatile uint16_t*)(0xD00000E8UL))
#define FM4_HSSPI_RDCSDC6                         *((volatile uint16_t*)(0xD00000E8UL))
#define FM_HSSPI_RDCSDC7                          *((volatile uint16_t*)(0xD00000EAUL))
#define FM4_HSSPI_RDCSDC7                         *((volatile uint16_t*)(0xD00000EAUL))
#define FM_HSSPI_WRCSDC0                          *((volatile uint16_t*)(0xD00000ECUL))
#define FM4_HSSPI_WRCSDC0                         *((volatile uint16_t*)(0xD00000ECUL))
#define FM_HSSPI_WRCSDC1                          *((volatile uint16_t*)(0xD00000EEUL))
#define FM4_HSSPI_WRCSDC1                         *((volatile uint16_t*)(0xD00000EEUL))
#define FM_HSSPI_WRCSDC2                          *((volatile uint16_t*)(0xD00000F0UL))
#define FM4_HSSPI_WRCSDC2                         *((volatile uint16_t*)(0xD00000F0UL))
#define FM_HSSPI_WRCSDC3                          *((volatile uint16_t*)(0xD00000F2UL))
#define FM4_HSSPI_WRCSDC3                         *((volatile uint16_t*)(0xD00000F2UL))
#define FM_HSSPI_WRCSDC4                          *((volatile uint16_t*)(0xD00000F4UL))
#define FM4_HSSPI_WRCSDC4                         *((volatile uint16_t*)(0xD00000F4UL))
#define FM_HSSPI_WRCSDC5                          *((volatile uint16_t*)(0xD00000F6UL))
#define FM4_HSSPI_WRCSDC5                         *((volatile uint16_t*)(0xD00000F6UL))
#define FM_HSSPI_WRCSDC6                          *((volatile uint16_t*)(0xD00000F8UL))
#define FM4_HSSPI_WRCSDC6                         *((volatile uint16_t*)(0xD00000F8UL))
#define FM_HSSPI_WRCSDC7                          *((volatile uint16_t*)(0xD00000FAUL))
#define FM4_HSSPI_WRCSDC7                         *((volatile uint16_t*)(0xD00000FAUL))
#define FM_HSSPI_MID                              *((volatile uint32_t*)(0xD00000FCUL))
#define FM4_HSSPI_MID                             *((volatile uint32_t*)(0xD00000FCUL))
#define FM_HSSPI_QDCLKR                           *((volatile  uint8_t*)(0xD0000400UL))
#define FM4_HSSPI_QDCLKR                          *((volatile  uint8_t*)(0xD0000400UL))
#define FM_HSSPI_DBCNT                            *((volatile  uint8_t*)(0xD0000404UL))
#define FM4_HSSPI_DBCNT                           *((volatile  uint8_t*)(0xD0000404UL))

/*******************************************************************************
* HWWDT Registers HWWDT
*   Register Definition
*******************************************************************************/
#define FM_HWWDT_WDG_LDR                          *((volatile uint32_t*)(0x40011000UL))
#define FM4_HWWDT_WDG_LDR                         *((volatile uint32_t*)(0x40011000UL))
#define FM_HWWDT_WDG_VLR                          *((volatile uint32_t*)(0x40011004UL))
#define FM4_HWWDT_WDG_VLR                         *((volatile uint32_t*)(0x40011004UL))
#define FM_HWWDT_WDG_CTL                          *((volatile uint32_t*)(0x40011008UL))
#define FM4_HWWDT_WDG_CTL                         *((volatile uint32_t*)(0x40011008UL))
#define FM_HWWDT_WDG_ICL                          *((volatile uint32_t*)(0x4001100CUL))
#define FM4_HWWDT_WDG_ICL                         *((volatile uint32_t*)(0x4001100CUL))
#define FM_HWWDT_WDG_RIS                          *((volatile uint32_t*)(0x40011010UL))
#define FM4_HWWDT_WDG_RIS                         *((volatile uint32_t*)(0x40011010UL))
#define FM_HWWDT_WDG_LCK                          *((volatile uint32_t*)(0x40011C00UL))
#define FM4_HWWDT_WDG_LCK                         *((volatile uint32_t*)(0x40011C00UL))

/*******************************************************************************
* I2S Registers I2S0
*   Register Definition
*******************************************************************************/
#define FM_I2S0_RXFDAT                            *((volatile uint32_t*)(0x4006C000UL))
#define FM4_I2S0_RXFDAT                           *((volatile uint32_t*)(0x4006C000UL))
#define FM_I2S0_TXFDAT                            *((volatile uint32_t*)(0x4006C004UL))
#define FM4_I2S0_TXFDAT                           *((volatile uint32_t*)(0x4006C004UL))
#define FM_I2S0_CNTREG                            *((volatile uint32_t*)(0x4006C008UL))
#define FM4_I2S0_CNTREG                           *((volatile uint32_t*)(0x4006C008UL))
#define FM_I2S0_MCR0REG                           *((volatile uint32_t*)(0x4006C00CUL))
#define FM4_I2S0_MCR0REG                          *((volatile uint32_t*)(0x4006C00CUL))
#define FM_I2S0_MCR1REG                           *((volatile uint32_t*)(0x4006C010UL))
#define FM4_I2S0_MCR1REG                          *((volatile uint32_t*)(0x4006C010UL))
#define FM_I2S0_MCR2REG                           *((volatile uint32_t*)(0x4006C014UL))
#define FM4_I2S0_MCR2REG                          *((volatile uint32_t*)(0x4006C014UL))
#define FM_I2S0_OPRREG                            *((volatile uint32_t*)(0x4006C018UL))
#define FM4_I2S0_OPRREG                           *((volatile uint32_t*)(0x4006C018UL))
#define FM_I2S0_SRST                              *((volatile uint32_t*)(0x4006C01CUL))
#define FM4_I2S0_SRST                             *((volatile uint32_t*)(0x4006C01CUL))
#define FM_I2S0_INTCNT                            *((volatile uint32_t*)(0x4006C020UL))
#define FM4_I2S0_INTCNT                           *((volatile uint32_t*)(0x4006C020UL))
#define FM_I2S0_STATUS                            *((volatile uint32_t*)(0x4006C024UL))
#define FM4_I2S0_STATUS                           *((volatile uint32_t*)(0x4006C024UL))
#define FM_I2S0_DMAACT                            *((volatile uint32_t*)(0x4006C028UL))
#define FM4_I2S0_DMAACT                           *((volatile uint32_t*)(0x4006C028UL))
#define FM_I2S0_TSTREG                            *((volatile uint32_t*)(0x4006C02CUL))
#define FM4_I2S0_TSTREG                           *((volatile uint32_t*)(0x4006C02CUL))

/*******************************************************************************
* I2SPRE Registers I2SPRE
*   Register Definition
*******************************************************************************/
#define FM_I2SPRE_ICCR                            *((volatile uint32_t*)(0x4003D000UL))
#define FM4_I2SPRE_ICCR                           *((volatile uint32_t*)(0x4003D000UL))
#define FM_I2SPRE_IPCR1                           *((volatile uint32_t*)(0x4003D004UL))
#define FM4_I2SPRE_IPCR1                          *((volatile uint32_t*)(0x4003D004UL))
#define FM_I2SPRE_IPCR2                           *((volatile uint32_t*)(0x4003D008UL))
#define FM4_I2SPRE_IPCR2                          *((volatile uint32_t*)(0x4003D008UL))
#define FM_I2SPRE_IPCR3                           *((volatile uint32_t*)(0x4003D00CUL))
#define FM4_I2SPRE_IPCR3                          *((volatile uint32_t*)(0x4003D00CUL))
#define FM_I2SPRE_IPCR4                           *((volatile uint32_t*)(0x4003D010UL))
#define FM4_I2SPRE_IPCR4                          *((volatile uint32_t*)(0x4003D010UL))
#define FM_I2SPRE_IP_STR                          *((volatile uint32_t*)(0x4003D014UL))
#define FM4_I2SPRE_IP_STR                         *((volatile uint32_t*)(0x4003D014UL))
#define FM_I2SPRE_IPINT_ENR                       *((volatile uint32_t*)(0x4003D018UL))
#define FM4_I2SPRE_IPINT_ENR                      *((volatile uint32_t*)(0x4003D018UL))
#define FM_I2SPRE_IPINT_CLR                       *((volatile uint32_t*)(0x4003D01CUL))
#define FM4_I2SPRE_IPINT_CLR                      *((volatile uint32_t*)(0x4003D01CUL))
#define FM_I2SPRE_IPINT_STR                       *((volatile uint32_t*)(0x4003D020UL))
#define FM4_I2SPRE_IPINT_STR                      *((volatile uint32_t*)(0x4003D020UL))
#define FM_I2SPRE_IPCR5                           *((volatile uint32_t*)(0x4003D024UL))
#define FM4_I2SPRE_IPCR5                          *((volatile uint32_t*)(0x4003D024UL))

/*******************************************************************************
* INTREQ Registers INTREQ
*   Register Definition
*******************************************************************************/
#define FM_INTREQ_DRQSEL                          *((volatile uint32_t*)(0x40031000UL))
#define FM4_INTREQ_DRQSEL                         *((volatile uint32_t*)(0x40031000UL))
#define FM_INTREQ_ODDPKS                          *((volatile  uint8_t*)(0x40031010UL))
#define FM4_INTREQ_ODDPKS                         *((volatile  uint8_t*)(0x40031010UL))
#define FM_INTREQ_ODDPKS1                         *((volatile  uint8_t*)(0x40031014UL))
#define FM4_INTREQ_ODDPKS1                        *((volatile  uint8_t*)(0x40031014UL))
#define FM_INTREQ_IRQ003SEL                       *((volatile uint32_t*)(0x40031110UL))
#define FM4_INTREQ_IRQ003SEL                      *((volatile uint32_t*)(0x40031110UL))
#define FM_INTREQ_IRQ004SEL                       *((volatile uint32_t*)(0x40031114UL))
#define FM4_INTREQ_IRQ004SEL                      *((volatile uint32_t*)(0x40031114UL))
#define FM_INTREQ_IRQ005SEL                       *((volatile uint32_t*)(0x40031118UL))
#define FM4_INTREQ_IRQ005SEL                      *((volatile uint32_t*)(0x40031118UL))
#define FM_INTREQ_IRQ006SEL                       *((volatile uint32_t*)(0x4003111CUL))
#define FM4_INTREQ_IRQ006SEL                      *((volatile uint32_t*)(0x4003111CUL))
#define FM_INTREQ_IRQ007SEL                       *((volatile uint32_t*)(0x40031120UL))
#define FM4_INTREQ_IRQ007SEL                      *((volatile uint32_t*)(0x40031120UL))
#define FM_INTREQ_IRQ008SEL                       *((volatile uint32_t*)(0x40031124UL))
#define FM4_INTREQ_IRQ008SEL                      *((volatile uint32_t*)(0x40031124UL))
#define FM_INTREQ_IRQ009SEL                       *((volatile uint32_t*)(0x40031128UL))
#define FM4_INTREQ_IRQ009SEL                      *((volatile uint32_t*)(0x40031128UL))
#define FM_INTREQ_IRQ010SEL                       *((volatile uint32_t*)(0x4003112CUL))
#define FM4_INTREQ_IRQ010SEL                      *((volatile uint32_t*)(0x4003112CUL))
#define FM_INTREQ_EXC02MON                        *((volatile uint32_t*)(0x40031200UL))
#define FM4_INTREQ_EXC02MON                       *((volatile uint32_t*)(0x40031200UL))
#define FM_INTREQ_IRQ000MON                       *((volatile uint32_t*)(0x40031204UL))
#define FM4_INTREQ_IRQ000MON                      *((volatile uint32_t*)(0x40031204UL))
#define FM_INTREQ_IRQ001MON                       *((volatile uint32_t*)(0x40031208UL))
#define FM4_INTREQ_IRQ001MON                      *((volatile uint32_t*)(0x40031208UL))
#define FM_INTREQ_IRQ002MON                       *((volatile uint32_t*)(0x4003120CUL))
#define FM4_INTREQ_IRQ002MON                      *((volatile uint32_t*)(0x4003120CUL))
#define FM_INTREQ_IRQ003MON                       *((volatile uint32_t*)(0x40031210UL))
#define FM4_INTREQ_IRQ003MON                      *((volatile uint32_t*)(0x40031210UL))
#define FM_INTREQ_IRQ004MON                       *((volatile uint32_t*)(0x40031214UL))
#define FM4_INTREQ_IRQ004MON                      *((volatile uint32_t*)(0x40031214UL))
#define FM_INTREQ_IRQ005MON                       *((volatile uint32_t*)(0x40031218UL))
#define FM4_INTREQ_IRQ005MON                      *((volatile uint32_t*)(0x40031218UL))
#define FM_INTREQ_IRQ006MON                       *((volatile uint32_t*)(0x4003121CUL))
#define FM4_INTREQ_IRQ006MON                      *((volatile uint32_t*)(0x4003121CUL))
#define FM_INTREQ_IRQ007MON                       *((volatile uint32_t*)(0x40031220UL))
#define FM4_INTREQ_IRQ007MON                      *((volatile uint32_t*)(0x40031220UL))
#define FM_INTREQ_IRQ008MON                       *((volatile uint32_t*)(0x40031224UL))
#define FM4_INTREQ_IRQ008MON                      *((volatile uint32_t*)(0x40031224UL))
#define FM_INTREQ_IRQ009MON                       *((volatile uint32_t*)(0x40031228UL))
#define FM4_INTREQ_IRQ009MON                      *((volatile uint32_t*)(0x40031228UL))
#define FM_INTREQ_IRQ010MON                       *((volatile uint32_t*)(0x4003122CUL))
#define FM4_INTREQ_IRQ010MON                      *((volatile uint32_t*)(0x4003122CUL))
#define FM_INTREQ_IRQ011MON                       *((volatile uint32_t*)(0x40031230UL))
#define FM4_INTREQ_IRQ011MON                      *((volatile uint32_t*)(0x40031230UL))
#define FM_INTREQ_IRQ012MON                       *((volatile uint32_t*)(0x40031234UL))
#define FM4_INTREQ_IRQ012MON                      *((volatile uint32_t*)(0x40031234UL))
#define FM_INTREQ_IRQ013MON                       *((volatile uint32_t*)(0x40031238UL))
#define FM4_INTREQ_IRQ013MON                      *((volatile uint32_t*)(0x40031238UL))
#define FM_INTREQ_IRQ014MON                       *((volatile uint32_t*)(0x4003123CUL))
#define FM4_INTREQ_IRQ014MON                      *((volatile uint32_t*)(0x4003123CUL))
#define FM_INTREQ_IRQ015MON                       *((volatile uint32_t*)(0x40031240UL))
#define FM4_INTREQ_IRQ015MON                      *((volatile uint32_t*)(0x40031240UL))
#define FM_INTREQ_IRQ016MON                       *((volatile uint32_t*)(0x40031244UL))
#define FM4_INTREQ_IRQ016MON                      *((volatile uint32_t*)(0x40031244UL))
#define FM_INTREQ_IRQ017MON                       *((volatile uint32_t*)(0x40031248UL))
#define FM4_INTREQ_IRQ017MON                      *((volatile uint32_t*)(0x40031248UL))
#define FM_INTREQ_IRQ018MON                       *((volatile uint32_t*)(0x4003124CUL))
#define FM4_INTREQ_IRQ018MON                      *((volatile uint32_t*)(0x4003124CUL))
#define FM_INTREQ_IRQ019MON                       *((volatile uint32_t*)(0x40031250UL))
#define FM4_INTREQ_IRQ019MON                      *((volatile uint32_t*)(0x40031250UL))
#define FM_INTREQ_IRQ020MON                       *((volatile uint32_t*)(0x40031254UL))
#define FM4_INTREQ_IRQ020MON                      *((volatile uint32_t*)(0x40031254UL))
#define FM_INTREQ_IRQ021MON                       *((volatile uint32_t*)(0x40031258UL))
#define FM4_INTREQ_IRQ021MON                      *((volatile uint32_t*)(0x40031258UL))
#define FM_INTREQ_IRQ022MON                       *((volatile uint32_t*)(0x4003125CUL))
#define FM4_INTREQ_IRQ022MON                      *((volatile uint32_t*)(0x4003125CUL))
#define FM_INTREQ_IRQ023MON                       *((volatile uint32_t*)(0x40031260UL))
#define FM4_INTREQ_IRQ023MON                      *((volatile uint32_t*)(0x40031260UL))
#define FM_INTREQ_IRQ024MON                       *((volatile uint32_t*)(0x40031264UL))
#define FM4_INTREQ_IRQ024MON                      *((volatile uint32_t*)(0x40031264UL))
#define FM_INTREQ_IRQ025MON                       *((volatile uint32_t*)(0x40031268UL))
#define FM4_INTREQ_IRQ025MON                      *((volatile uint32_t*)(0x40031268UL))
#define FM_INTREQ_IRQ026MON                       *((volatile uint32_t*)(0x4003126CUL))
#define FM4_INTREQ_IRQ026MON                      *((volatile uint32_t*)(0x4003126CUL))
#define FM_INTREQ_IRQ027MON                       *((volatile uint32_t*)(0x40031270UL))
#define FM4_INTREQ_IRQ027MON                      *((volatile uint32_t*)(0x40031270UL))
#define FM_INTREQ_IRQ028MON                       *((volatile uint32_t*)(0x40031274UL))
#define FM4_INTREQ_IRQ028MON                      *((volatile uint32_t*)(0x40031274UL))
#define FM_INTREQ_IRQ029MON                       *((volatile uint32_t*)(0x40031278UL))
#define FM4_INTREQ_IRQ029MON                      *((volatile uint32_t*)(0x40031278UL))
#define FM_INTREQ_IRQ030MON                       *((volatile uint32_t*)(0x4003127CUL))
#define FM4_INTREQ_IRQ030MON                      *((volatile uint32_t*)(0x4003127CUL))
#define FM_INTREQ_IRQ031MON                       *((volatile uint32_t*)(0x40031280UL))
#define FM4_INTREQ_IRQ031MON                      *((volatile uint32_t*)(0x40031280UL))
#define FM_INTREQ_IRQ032MON                       *((volatile uint32_t*)(0x40031284UL))
#define FM4_INTREQ_IRQ032MON                      *((volatile uint32_t*)(0x40031284UL))
#define FM_INTREQ_IRQ033MON                       *((volatile uint32_t*)(0x40031288UL))
#define FM4_INTREQ_IRQ033MON                      *((volatile uint32_t*)(0x40031288UL))
#define FM_INTREQ_IRQ034MON                       *((volatile uint32_t*)(0x4003128CUL))
#define FM4_INTREQ_IRQ034MON                      *((volatile uint32_t*)(0x4003128CUL))
#define FM_INTREQ_IRQ035MON                       *((volatile uint32_t*)(0x40031290UL))
#define FM4_INTREQ_IRQ035MON                      *((volatile uint32_t*)(0x40031290UL))
#define FM_INTREQ_IRQ036MON                       *((volatile uint32_t*)(0x40031294UL))
#define FM4_INTREQ_IRQ036MON                      *((volatile uint32_t*)(0x40031294UL))
#define FM_INTREQ_IRQ037MON                       *((volatile uint32_t*)(0x40031298UL))
#define FM4_INTREQ_IRQ037MON                      *((volatile uint32_t*)(0x40031298UL))
#define FM_INTREQ_IRQ038MON                       *((volatile uint32_t*)(0x4003129CUL))
#define FM4_INTREQ_IRQ038MON                      *((volatile uint32_t*)(0x4003129CUL))
#define FM_INTREQ_IRQ039MON                       *((volatile uint32_t*)(0x400312A0UL))
#define FM4_INTREQ_IRQ039MON                      *((volatile uint32_t*)(0x400312A0UL))
#define FM_INTREQ_IRQ040MON                       *((volatile uint32_t*)(0x400312A4UL))
#define FM4_INTREQ_IRQ040MON                      *((volatile uint32_t*)(0x400312A4UL))
#define FM_INTREQ_IRQ041MON                       *((volatile uint32_t*)(0x400312A8UL))
#define FM4_INTREQ_IRQ041MON                      *((volatile uint32_t*)(0x400312A8UL))
#define FM_INTREQ_IRQ042MON                       *((volatile uint32_t*)(0x400312ACUL))
#define FM4_INTREQ_IRQ042MON                      *((volatile uint32_t*)(0x400312ACUL))
#define FM_INTREQ_IRQ043MON                       *((volatile uint32_t*)(0x400312B0UL))
#define FM4_INTREQ_IRQ043MON                      *((volatile uint32_t*)(0x400312B0UL))
#define FM_INTREQ_IRQ044MON                       *((volatile uint32_t*)(0x400312B4UL))
#define FM4_INTREQ_IRQ044MON                      *((volatile uint32_t*)(0x400312B4UL))
#define FM_INTREQ_IRQ045MON                       *((volatile uint32_t*)(0x400312B8UL))
#define FM4_INTREQ_IRQ045MON                      *((volatile uint32_t*)(0x400312B8UL))
#define FM_INTREQ_IRQ046MON                       *((volatile uint32_t*)(0x400312BCUL))
#define FM4_INTREQ_IRQ046MON                      *((volatile uint32_t*)(0x400312BCUL))
#define FM_INTREQ_IRQ047MON                       *((volatile uint32_t*)(0x400312C0UL))
#define FM4_INTREQ_IRQ047MON                      *((volatile uint32_t*)(0x400312C0UL))
#define FM_INTREQ_IRQ048MON                       *((volatile uint32_t*)(0x400312C4UL))
#define FM4_INTREQ_IRQ048MON                      *((volatile uint32_t*)(0x400312C4UL))
#define FM_INTREQ_IRQ049MON                       *((volatile uint32_t*)(0x400312C8UL))
#define FM4_INTREQ_IRQ049MON                      *((volatile uint32_t*)(0x400312C8UL))
#define FM_INTREQ_IRQ050MON                       *((volatile uint32_t*)(0x400312CCUL))
#define FM4_INTREQ_IRQ050MON                      *((volatile uint32_t*)(0x400312CCUL))
#define FM_INTREQ_IRQ051MON                       *((volatile uint32_t*)(0x400312D0UL))
#define FM4_INTREQ_IRQ051MON                      *((volatile uint32_t*)(0x400312D0UL))
#define FM_INTREQ_IRQ052MON                       *((volatile uint32_t*)(0x400312D4UL))
#define FM4_INTREQ_IRQ052MON                      *((volatile uint32_t*)(0x400312D4UL))
#define FM_INTREQ_IRQ053MON                       *((volatile uint32_t*)(0x400312D8UL))
#define FM4_INTREQ_IRQ053MON                      *((volatile uint32_t*)(0x400312D8UL))
#define FM_INTREQ_IRQ054MON                       *((volatile uint32_t*)(0x400312DCUL))
#define FM4_INTREQ_IRQ054MON                      *((volatile uint32_t*)(0x400312DCUL))
#define FM_INTREQ_IRQ055MON                       *((volatile uint32_t*)(0x400312E0UL))
#define FM4_INTREQ_IRQ055MON                      *((volatile uint32_t*)(0x400312E0UL))
#define FM_INTREQ_IRQ056MON                       *((volatile uint32_t*)(0x400312E4UL))
#define FM4_INTREQ_IRQ056MON                      *((volatile uint32_t*)(0x400312E4UL))
#define FM_INTREQ_IRQ057MON                       *((volatile uint32_t*)(0x400312E8UL))
#define FM4_INTREQ_IRQ057MON                      *((volatile uint32_t*)(0x400312E8UL))
#define FM_INTREQ_IRQ058MON                       *((volatile uint32_t*)(0x400312ECUL))
#define FM4_INTREQ_IRQ058MON                      *((volatile uint32_t*)(0x400312ECUL))
#define FM_INTREQ_IRQ059MON                       *((volatile uint32_t*)(0x400312F0UL))
#define FM4_INTREQ_IRQ059MON                      *((volatile uint32_t*)(0x400312F0UL))
#define FM_INTREQ_IRQ060MON                       *((volatile uint32_t*)(0x400312F4UL))
#define FM4_INTREQ_IRQ060MON                      *((volatile uint32_t*)(0x400312F4UL))
#define FM_INTREQ_IRQ061MON                       *((volatile uint32_t*)(0x400312F8UL))
#define FM4_INTREQ_IRQ061MON                      *((volatile uint32_t*)(0x400312F8UL))
#define FM_INTREQ_IRQ062MON                       *((volatile uint32_t*)(0x400312FCUL))
#define FM4_INTREQ_IRQ062MON                      *((volatile uint32_t*)(0x400312FCUL))
#define FM_INTREQ_IRQ063MON                       *((volatile uint32_t*)(0x40031300UL))
#define FM4_INTREQ_IRQ063MON                      *((volatile uint32_t*)(0x40031300UL))
#define FM_INTREQ_IRQ064MON                       *((volatile uint32_t*)(0x40031304UL))
#define FM4_INTREQ_IRQ064MON                      *((volatile uint32_t*)(0x40031304UL))
#define FM_INTREQ_IRQ065MON                       *((volatile uint32_t*)(0x40031308UL))
#define FM4_INTREQ_IRQ065MON                      *((volatile uint32_t*)(0x40031308UL))
#define FM_INTREQ_IRQ066MON                       *((volatile uint32_t*)(0x4003130CUL))
#define FM4_INTREQ_IRQ066MON                      *((volatile uint32_t*)(0x4003130CUL))
#define FM_INTREQ_IRQ067MON                       *((volatile uint32_t*)(0x40031310UL))
#define FM4_INTREQ_IRQ067MON                      *((volatile uint32_t*)(0x40031310UL))
#define FM_INTREQ_IRQ068MON                       *((volatile uint32_t*)(0x40031314UL))
#define FM4_INTREQ_IRQ068MON                      *((volatile uint32_t*)(0x40031314UL))
#define FM_INTREQ_IRQ069MON                       *((volatile uint32_t*)(0x40031318UL))
#define FM4_INTREQ_IRQ069MON                      *((volatile uint32_t*)(0x40031318UL))
#define FM_INTREQ_IRQ070MON                       *((volatile uint32_t*)(0x4003131CUL))
#define FM4_INTREQ_IRQ070MON                      *((volatile uint32_t*)(0x4003131CUL))
#define FM_INTREQ_IRQ071MON                       *((volatile uint32_t*)(0x40031320UL))
#define FM4_INTREQ_IRQ071MON                      *((volatile uint32_t*)(0x40031320UL))
#define FM_INTREQ_IRQ072MON                       *((volatile uint32_t*)(0x40031324UL))
#define FM4_INTREQ_IRQ072MON                      *((volatile uint32_t*)(0x40031324UL))
#define FM_INTREQ_IRQ073MON                       *((volatile uint32_t*)(0x40031328UL))
#define FM4_INTREQ_IRQ073MON                      *((volatile uint32_t*)(0x40031328UL))
#define FM_INTREQ_IRQ074MON                       *((volatile uint32_t*)(0x4003132CUL))
#define FM4_INTREQ_IRQ074MON                      *((volatile uint32_t*)(0x4003132CUL))
#define FM_INTREQ_IRQ075MON                       *((volatile uint32_t*)(0x40031330UL))
#define FM4_INTREQ_IRQ075MON                      *((volatile uint32_t*)(0x40031330UL))
#define FM_INTREQ_IRQ076MON                       *((volatile uint32_t*)(0x40031334UL))
#define FM4_INTREQ_IRQ076MON                      *((volatile uint32_t*)(0x40031334UL))
#define FM_INTREQ_IRQ077MON                       *((volatile uint32_t*)(0x40031338UL))
#define FM4_INTREQ_IRQ077MON                      *((volatile uint32_t*)(0x40031338UL))
#define FM_INTREQ_IRQ078MON                       *((volatile uint32_t*)(0x4003133CUL))
#define FM4_INTREQ_IRQ078MON                      *((volatile uint32_t*)(0x4003133CUL))
#define FM_INTREQ_IRQ079MON                       *((volatile uint32_t*)(0x40031340UL))
#define FM4_INTREQ_IRQ079MON                      *((volatile uint32_t*)(0x40031340UL))
#define FM_INTREQ_IRQ080MON                       *((volatile uint32_t*)(0x40031344UL))
#define FM4_INTREQ_IRQ080MON                      *((volatile uint32_t*)(0x40031344UL))
#define FM_INTREQ_IRQ081MON                       *((volatile uint32_t*)(0x40031348UL))
#define FM4_INTREQ_IRQ081MON                      *((volatile uint32_t*)(0x40031348UL))
#define FM_INTREQ_IRQ082MON                       *((volatile uint32_t*)(0x4003134CUL))
#define FM4_INTREQ_IRQ082MON                      *((volatile uint32_t*)(0x4003134CUL))
#define FM_INTREQ_IRQ083MON                       *((volatile uint32_t*)(0x40031350UL))
#define FM4_INTREQ_IRQ083MON                      *((volatile uint32_t*)(0x40031350UL))
#define FM_INTREQ_IRQ084MON                       *((volatile uint32_t*)(0x40031354UL))
#define FM4_INTREQ_IRQ084MON                      *((volatile uint32_t*)(0x40031354UL))
#define FM_INTREQ_IRQ085MON                       *((volatile uint32_t*)(0x40031358UL))
#define FM4_INTREQ_IRQ085MON                      *((volatile uint32_t*)(0x40031358UL))
#define FM_INTREQ_IRQ086MON                       *((volatile uint32_t*)(0x4003135CUL))
#define FM4_INTREQ_IRQ086MON                      *((volatile uint32_t*)(0x4003135CUL))
#define FM_INTREQ_IRQ087MON                       *((volatile uint32_t*)(0x40031360UL))
#define FM4_INTREQ_IRQ087MON                      *((volatile uint32_t*)(0x40031360UL))
#define FM_INTREQ_IRQ088MON                       *((volatile uint32_t*)(0x40031364UL))
#define FM4_INTREQ_IRQ088MON                      *((volatile uint32_t*)(0x40031364UL))
#define FM_INTREQ_IRQ089MON                       *((volatile uint32_t*)(0x40031368UL))
#define FM4_INTREQ_IRQ089MON                      *((volatile uint32_t*)(0x40031368UL))
#define FM_INTREQ_IRQ090MON                       *((volatile uint32_t*)(0x4003136CUL))
#define FM4_INTREQ_IRQ090MON                      *((volatile uint32_t*)(0x4003136CUL))
#define FM_INTREQ_IRQ091MON                       *((volatile uint32_t*)(0x40031370UL))
#define FM4_INTREQ_IRQ091MON                      *((volatile uint32_t*)(0x40031370UL))
#define FM_INTREQ_IRQ092MON                       *((volatile uint32_t*)(0x40031374UL))
#define FM4_INTREQ_IRQ092MON                      *((volatile uint32_t*)(0x40031374UL))
#define FM_INTREQ_IRQ093MON                       *((volatile uint32_t*)(0x40031378UL))
#define FM4_INTREQ_IRQ093MON                      *((volatile uint32_t*)(0x40031378UL))
#define FM_INTREQ_IRQ094MON                       *((volatile uint32_t*)(0x4003137CUL))
#define FM4_INTREQ_IRQ094MON                      *((volatile uint32_t*)(0x4003137CUL))
#define FM_INTREQ_IRQ095MON                       *((volatile uint32_t*)(0x40031380UL))
#define FM4_INTREQ_IRQ095MON                      *((volatile uint32_t*)(0x40031380UL))
#define FM_INTREQ_IRQ096MON                       *((volatile uint32_t*)(0x40031384UL))
#define FM4_INTREQ_IRQ096MON                      *((volatile uint32_t*)(0x40031384UL))
#define FM_INTREQ_IRQ097MON                       *((volatile uint32_t*)(0x40031388UL))
#define FM4_INTREQ_IRQ097MON                      *((volatile uint32_t*)(0x40031388UL))
#define FM_INTREQ_IRQ098MON                       *((volatile uint32_t*)(0x4003138CUL))
#define FM4_INTREQ_IRQ098MON                      *((volatile uint32_t*)(0x4003138CUL))
#define FM_INTREQ_IRQ099MON                       *((volatile uint32_t*)(0x40031390UL))
#define FM4_INTREQ_IRQ099MON                      *((volatile uint32_t*)(0x40031390UL))
#define FM_INTREQ_IRQ100MON                       *((volatile uint32_t*)(0x40031394UL))
#define FM4_INTREQ_IRQ100MON                      *((volatile uint32_t*)(0x40031394UL))
#define FM_INTREQ_IRQ101MON                       *((volatile uint32_t*)(0x40031398UL))
#define FM4_INTREQ_IRQ101MON                      *((volatile uint32_t*)(0x40031398UL))
#define FM_INTREQ_IRQ102MON                       *((volatile uint32_t*)(0x4003139CUL))
#define FM4_INTREQ_IRQ102MON                      *((volatile uint32_t*)(0x4003139CUL))
#define FM_INTREQ_IRQ103MON                       *((volatile uint32_t*)(0x400313A0UL))
#define FM4_INTREQ_IRQ103MON                      *((volatile uint32_t*)(0x400313A0UL))
#define FM_INTREQ_IRQ104MON                       *((volatile uint32_t*)(0x400313A4UL))
#define FM4_INTREQ_IRQ104MON                      *((volatile uint32_t*)(0x400313A4UL))
#define FM_INTREQ_IRQ105MON                       *((volatile uint32_t*)(0x400313A8UL))
#define FM4_INTREQ_IRQ105MON                      *((volatile uint32_t*)(0x400313A8UL))
#define FM_INTREQ_IRQ106MON                       *((volatile uint32_t*)(0x400313ACUL))
#define FM4_INTREQ_IRQ106MON                      *((volatile uint32_t*)(0x400313ACUL))
#define FM_INTREQ_IRQ107MON                       *((volatile uint32_t*)(0x400313B0UL))
#define FM4_INTREQ_IRQ107MON                      *((volatile uint32_t*)(0x400313B0UL))
#define FM_INTREQ_IRQ108MON                       *((volatile uint32_t*)(0x400313B4UL))
#define FM4_INTREQ_IRQ108MON                      *((volatile uint32_t*)(0x400313B4UL))
#define FM_INTREQ_IRQ109MON                       *((volatile uint32_t*)(0x400313B8UL))
#define FM4_INTREQ_IRQ109MON                      *((volatile uint32_t*)(0x400313B8UL))
#define FM_INTREQ_IRQ110MON                       *((volatile uint32_t*)(0x400313BCUL))
#define FM4_INTREQ_IRQ110MON                      *((volatile uint32_t*)(0x400313BCUL))
#define FM_INTREQ_IRQ111MON                       *((volatile uint32_t*)(0x400313C0UL))
#define FM4_INTREQ_IRQ111MON                      *((volatile uint32_t*)(0x400313C0UL))
#define FM_INTREQ_IRQ112MON                       *((volatile uint32_t*)(0x400313C4UL))
#define FM4_INTREQ_IRQ112MON                      *((volatile uint32_t*)(0x400313C4UL))
#define FM_INTREQ_IRQ113MON                       *((volatile uint32_t*)(0x400313C8UL))
#define FM4_INTREQ_IRQ113MON                      *((volatile uint32_t*)(0x400313C8UL))
#define FM_INTREQ_IRQ114MON                       *((volatile uint32_t*)(0x400313CCUL))
#define FM4_INTREQ_IRQ114MON                      *((volatile uint32_t*)(0x400313CCUL))
#define FM_INTREQ_IRQ115MON                       *((volatile uint32_t*)(0x400313D0UL))
#define FM4_INTREQ_IRQ115MON                      *((volatile uint32_t*)(0x400313D0UL))
#define FM_INTREQ_IRQ116MON                       *((volatile uint32_t*)(0x400313D4UL))
#define FM4_INTREQ_IRQ116MON                      *((volatile uint32_t*)(0x400313D4UL))
#define FM_INTREQ_IRQ117MON                       *((volatile uint32_t*)(0x400313D8UL))
#define FM4_INTREQ_IRQ117MON                      *((volatile uint32_t*)(0x400313D8UL))
#define FM_INTREQ_IRQ118MON                       *((volatile uint32_t*)(0x400313DCUL))
#define FM4_INTREQ_IRQ118MON                      *((volatile uint32_t*)(0x400313DCUL))
#define FM_INTREQ_IRQ119MON                       *((volatile uint32_t*)(0x400313E0UL))
#define FM4_INTREQ_IRQ119MON                      *((volatile uint32_t*)(0x400313E0UL))
#define FM_INTREQ_IRQ120MON                       *((volatile uint32_t*)(0x400313E4UL))
#define FM4_INTREQ_IRQ120MON                      *((volatile uint32_t*)(0x400313E4UL))
#define FM_INTREQ_IRQ121MON                       *((volatile uint32_t*)(0x400313E8UL))
#define FM4_INTREQ_IRQ121MON                      *((volatile uint32_t*)(0x400313E8UL))
#define FM_INTREQ_IRQ122MON                       *((volatile uint32_t*)(0x400313ECUL))
#define FM4_INTREQ_IRQ122MON                      *((volatile uint32_t*)(0x400313ECUL))
#define FM_INTREQ_IRQ123MON                       *((volatile uint32_t*)(0x400313F0UL))
#define FM4_INTREQ_IRQ123MON                      *((volatile uint32_t*)(0x400313F0UL))
#define FM_INTREQ_IRQ124MON                       *((volatile uint32_t*)(0x400313F4UL))
#define FM4_INTREQ_IRQ124MON                      *((volatile uint32_t*)(0x400313F4UL))
#define FM_INTREQ_IRQ125MON                       *((volatile uint32_t*)(0x400313F8UL))
#define FM4_INTREQ_IRQ125MON                      *((volatile uint32_t*)(0x400313F8UL))
#define FM_INTREQ_IRQ126MON                       *((volatile uint32_t*)(0x400313FCUL))
#define FM4_INTREQ_IRQ126MON                      *((volatile uint32_t*)(0x400313FCUL))
#define FM_INTREQ_IRQ127MON                       *((volatile uint32_t*)(0x40031400UL))
#define FM4_INTREQ_IRQ127MON                      *((volatile uint32_t*)(0x40031400UL))

/*******************************************************************************
* LSCRP Registers LSCRP
*   Register Definition
*******************************************************************************/
#define FM_LSCRP_LCR_PRSLD                        *((volatile  uint8_t*)(0x4003C000UL))
#define FM4_LSCRP_LCR_PRSLD                       *((volatile  uint8_t*)(0x4003C000UL))

/*******************************************************************************
* LVD Registers LVD
*   Register Definition
*******************************************************************************/
#define FM_LVD_LVD_CTL                            *((volatile  uint8_t*)(0x40035000UL))
#define FM4_LVD_LVD_CTL                           *((volatile  uint8_t*)(0x40035000UL))
#define FM_LVD_LVD_STR                            *((volatile  uint8_t*)(0x40035004UL))
#define FM4_LVD_LVD_STR                           *((volatile  uint8_t*)(0x40035004UL))
#define FM_LVD_LVD_CLR                            *((volatile  uint8_t*)(0x40035008UL))
#define FM4_LVD_LVD_CLR                           *((volatile  uint8_t*)(0x40035008UL))
#define FM_LVD_LVD_RLR                            *((volatile uint32_t*)(0x4003500CUL))
#define FM4_LVD_LVD_RLR                           *((volatile uint32_t*)(0x4003500CUL))
#define FM_LVD_LVD_STR2                           *((volatile  uint8_t*)(0x40035010UL))
#define FM4_LVD_LVD_STR2                          *((volatile  uint8_t*)(0x40035010UL))

/*******************************************************************************
* MFS Registers MFS0
*   Register Definition
*******************************************************************************/
#define FM_MFS0_CSIO_SMR                          *((volatile  uint8_t*)(0x40038000UL))
#define FM4_MFS0_CSIO_SMR                         *((volatile  uint8_t*)(0x40038000UL))
#define FM_MFS0_I2C_SMR                           *((volatile  uint8_t*)(0x40038000UL))
#define FM4_MFS0_I2C_SMR                          *((volatile  uint8_t*)(0x40038000UL))
#define FM_MFS0_LIN_SMR                           *((volatile  uint8_t*)(0x40038000UL))
#define FM4_MFS0_LIN_SMR                          *((volatile  uint8_t*)(0x40038000UL))
#define FM_MFS0_UART_SMR                          *((volatile  uint8_t*)(0x40038000UL))
#define FM4_MFS0_UART_SMR                         *((volatile  uint8_t*)(0x40038000UL))
#define FM_MFS0_CSIO_SCR                          *((volatile  uint8_t*)(0x40038001UL))
#define FM4_MFS0_CSIO_SCR                         *((volatile  uint8_t*)(0x40038001UL))
#define FM_MFS0_I2C_IBCR                          *((volatile  uint8_t*)(0x40038001UL))
#define FM4_MFS0_I2C_IBCR                         *((volatile  uint8_t*)(0x40038001UL))
#define FM_MFS0_LIN_SCR                           *((volatile  uint8_t*)(0x40038001UL))
#define FM4_MFS0_LIN_SCR                          *((volatile  uint8_t*)(0x40038001UL))
#define FM_MFS0_UART_SCR                          *((volatile  uint8_t*)(0x40038001UL))
#define FM4_MFS0_UART_SCR                         *((volatile  uint8_t*)(0x40038001UL))
#define FM_MFS0_CSIO_ESCR                         *((volatile  uint8_t*)(0x40038004UL))
#define FM4_MFS0_CSIO_ESCR                        *((volatile  uint8_t*)(0x40038004UL))
#define FM_MFS0_I2C_IBSR                          *((volatile  uint8_t*)(0x40038004UL))
#define FM4_MFS0_I2C_IBSR                         *((volatile  uint8_t*)(0x40038004UL))
#define FM_MFS0_LIN_ESCR                          *((volatile  uint8_t*)(0x40038004UL))
#define FM4_MFS0_LIN_ESCR                         *((volatile  uint8_t*)(0x40038004UL))
#define FM_MFS0_UART_ESCR                         *((volatile  uint8_t*)(0x40038004UL))
#define FM4_MFS0_UART_ESCR                        *((volatile  uint8_t*)(0x40038004UL))
#define FM_MFS0_CSIO_SSR                          *((volatile  uint8_t*)(0x40038005UL))
#define FM4_MFS0_CSIO_SSR                         *((volatile  uint8_t*)(0x40038005UL))
#define FM_MFS0_I2C_SSR                           *((volatile  uint8_t*)(0x40038005UL))
#define FM4_MFS0_I2C_SSR                          *((volatile  uint8_t*)(0x40038005UL))
#define FM_MFS0_LIN_SSR                           *((volatile  uint8_t*)(0x40038005UL))
#define FM4_MFS0_LIN_SSR                          *((volatile  uint8_t*)(0x40038005UL))
#define FM_MFS0_UART_SSR                          *((volatile  uint8_t*)(0x40038005UL))
#define FM4_MFS0_UART_SSR                         *((volatile  uint8_t*)(0x40038005UL))
#define FM_MFS0_CSIO_RDR                          *((volatile uint16_t*)(0x40038008UL))
#define FM4_MFS0_CSIO_RDR                         *((volatile uint16_t*)(0x40038008UL))
#define FM_MFS0_CSIO_TDR                          *((volatile uint16_t*)(0x40038008UL))
#define FM4_MFS0_CSIO_TDR                         *((volatile uint16_t*)(0x40038008UL))
#define FM_MFS0_I2C_RDR                           *((volatile uint16_t*)(0x40038008UL))
#define FM4_MFS0_I2C_RDR                          *((volatile uint16_t*)(0x40038008UL))
#define FM_MFS0_I2C_TDR                           *((volatile uint16_t*)(0x40038008UL))
#define FM4_MFS0_I2C_TDR                          *((volatile uint16_t*)(0x40038008UL))
#define FM_MFS0_LIN_RDR                           *((volatile uint16_t*)(0x40038008UL))
#define FM4_MFS0_LIN_RDR                          *((volatile uint16_t*)(0x40038008UL))
#define FM_MFS0_LIN_TDR                           *((volatile uint16_t*)(0x40038008UL))
#define FM4_MFS0_LIN_TDR                          *((volatile uint16_t*)(0x40038008UL))
#define FM_MFS0_UART_RDR                          *((volatile uint16_t*)(0x40038008UL))
#define FM4_MFS0_UART_RDR                         *((volatile uint16_t*)(0x40038008UL))
#define FM_MFS0_UART_TDR                          *((volatile uint16_t*)(0x40038008UL))
#define FM4_MFS0_UART_TDR                         *((volatile uint16_t*)(0x40038008UL))
#define FM_MFS0_CSIO_BGR                          *((volatile uint16_t*)(0x4003800CUL))
#define FM4_MFS0_CSIO_BGR                         *((volatile uint16_t*)(0x4003800CUL))
#define FM_MFS0_I2C_BGR                           *((volatile uint16_t*)(0x4003800CUL))
#define FM4_MFS0_I2C_BGR                          *((volatile uint16_t*)(0x4003800CUL))
#define FM_MFS0_LIN_BGR                           *((volatile uint16_t*)(0x4003800CUL))
#define FM4_MFS0_LIN_BGR                          *((volatile uint16_t*)(0x4003800CUL))
#define FM_MFS0_UART_BGR                          *((volatile uint16_t*)(0x4003800CUL))
#define FM4_MFS0_UART_BGR                         *((volatile uint16_t*)(0x4003800CUL))
#define FM_MFS0_I2C_ISBA                          *((volatile  uint8_t*)(0x40038010UL))
#define FM4_MFS0_I2C_ISBA                         *((volatile  uint8_t*)(0x40038010UL))
#define FM_MFS0_I2C_ISMK                          *((volatile  uint8_t*)(0x40038011UL))
#define FM4_MFS0_I2C_ISMK                         *((volatile  uint8_t*)(0x40038011UL))
#define FM_MFS0_CSIO_FCR                          *((volatile uint16_t*)(0x40038014UL))
#define FM4_MFS0_CSIO_FCR                         *((volatile uint16_t*)(0x40038014UL))
#define FM_MFS0_I2C_FCR                           *((volatile uint16_t*)(0x40038014UL))
#define FM4_MFS0_I2C_FCR                          *((volatile uint16_t*)(0x40038014UL))
#define FM_MFS0_LIN_FCR                           *((volatile uint16_t*)(0x40038014UL))
#define FM4_MFS0_LIN_FCR                          *((volatile uint16_t*)(0x40038014UL))
#define FM_MFS0_UART_FCR                          *((volatile uint16_t*)(0x40038014UL))
#define FM4_MFS0_UART_FCR                         *((volatile uint16_t*)(0x40038014UL))
#define FM_MFS0_CSIO_FBYTE1                       *((volatile  uint8_t*)(0x40038018UL))
#define FM4_MFS0_CSIO_FBYTE1                      *((volatile  uint8_t*)(0x40038018UL))
#define FM_MFS0_I2C_FBYTE1                        *((volatile  uint8_t*)(0x40038018UL))
#define FM4_MFS0_I2C_FBYTE1                       *((volatile  uint8_t*)(0x40038018UL))
#define FM_MFS0_LIN_FBYTE1                        *((volatile  uint8_t*)(0x40038018UL))
#define FM4_MFS0_LIN_FBYTE1                       *((volatile  uint8_t*)(0x40038018UL))
#define FM_MFS0_UART_FBYTE1                       *((volatile  uint8_t*)(0x40038018UL))
#define FM4_MFS0_UART_FBYTE1                      *((volatile  uint8_t*)(0x40038018UL))
#define FM_MFS0_CSIO_FBYTE2                       *((volatile  uint8_t*)(0x40038019UL))
#define FM4_MFS0_CSIO_FBYTE2                      *((volatile  uint8_t*)(0x40038019UL))
#define FM_MFS0_I2C_FBYTE2                        *((volatile  uint8_t*)(0x40038019UL))
#define FM4_MFS0_I2C_FBYTE2                       *((volatile  uint8_t*)(0x40038019UL))
#define FM_MFS0_LIN_FBYTE2                        *((volatile  uint8_t*)(0x40038019UL))
#define FM4_MFS0_LIN_FBYTE2                       *((volatile  uint8_t*)(0x40038019UL))
#define FM_MFS0_UART_FBYTE2                       *((volatile  uint8_t*)(0x40038019UL))
#define FM4_MFS0_UART_FBYTE2                      *((volatile  uint8_t*)(0x40038019UL))
#define FM_MFS0_CSIO_SCSTR0                       *((volatile  uint8_t*)(0x4003801CUL))
#define FM4_MFS0_CSIO_SCSTR0                      *((volatile  uint8_t*)(0x4003801CUL))
#define FM_MFS0_I2C_NFCR                          *((volatile  uint8_t*)(0x4003801CUL))
#define FM4_MFS0_I2C_NFCR                         *((volatile  uint8_t*)(0x4003801CUL))
#define FM_MFS0_CSIO_SCSTR1                       *((volatile  uint8_t*)(0x4003801DUL))
#define FM4_MFS0_CSIO_SCSTR1                      *((volatile  uint8_t*)(0x4003801DUL))
#define FM_MFS0_I2C_EIBCR                         *((volatile  uint8_t*)(0x4003801DUL))
#define FM4_MFS0_I2C_EIBCR                        *((volatile  uint8_t*)(0x4003801DUL))
#define FM_MFS0_CSIO_SCSTR32                      *((volatile uint16_t*)(0x40038020UL))
#define FM4_MFS0_CSIO_SCSTR32                     *((volatile uint16_t*)(0x40038020UL))
#define FM_MFS0_CSIO_SACSR                        *((volatile uint16_t*)(0x40038024UL))
#define FM4_MFS0_CSIO_SACSR                       *((volatile uint16_t*)(0x40038024UL))
#define FM_MFS0_CSIO_STMR                         *((volatile uint16_t*)(0x40038028UL))
#define FM4_MFS0_CSIO_STMR                        *((volatile uint16_t*)(0x40038028UL))
#define FM_MFS0_CSIO_STMCR                        *((volatile uint16_t*)(0x4003802CUL))
#define FM4_MFS0_CSIO_STMCR                       *((volatile uint16_t*)(0x4003802CUL))
#define FM_MFS0_CSIO_SCSCR                        *((volatile uint16_t*)(0x40038030UL))
#define FM4_MFS0_CSIO_SCSCR                       *((volatile uint16_t*)(0x40038030UL))
#define FM_MFS0_CSIO_SCSFR0                       *((volatile  uint8_t*)(0x40038034UL))
#define FM4_MFS0_CSIO_SCSFR0                      *((volatile  uint8_t*)(0x40038034UL))
#define FM_MFS0_CSIO_SCSFR1                       *((volatile  uint8_t*)(0x40038035UL))
#define FM4_MFS0_CSIO_SCSFR1                      *((volatile  uint8_t*)(0x40038035UL))
#define FM_MFS0_CSIO_SCSFR2                       *((volatile  uint8_t*)(0x40038038UL))
#define FM4_MFS0_CSIO_SCSFR2                      *((volatile  uint8_t*)(0x40038038UL))
#define FM_MFS0_CSIO_TBYTE0                       *((volatile  uint8_t*)(0x4003803CUL))
#define FM4_MFS0_CSIO_TBYTE0                      *((volatile  uint8_t*)(0x4003803CUL))
#define FM_MFS0_CSIO_TBYTE1                       *((volatile  uint8_t*)(0x4003803DUL))
#define FM4_MFS0_CSIO_TBYTE1                      *((volatile  uint8_t*)(0x4003803DUL))
#define FM_MFS0_CSIO_TBYTE2                       *((volatile  uint8_t*)(0x40038040UL))
#define FM4_MFS0_CSIO_TBYTE2                      *((volatile  uint8_t*)(0x40038040UL))
#define FM_MFS0_CSIO_TBYTE3                       *((volatile  uint8_t*)(0x40038041UL))
#define FM4_MFS0_CSIO_TBYTE3                      *((volatile  uint8_t*)(0x40038041UL))

/*******************************************************************************
* MFS Registers MFS1
*   Register Definition
*******************************************************************************/
#define FM_MFS1_CSIO_SMR                          *((volatile  uint8_t*)(0x40038100UL))
#define FM4_MFS1_CSIO_SMR                         *((volatile  uint8_t*)(0x40038100UL))
#define FM_MFS1_I2C_SMR                           *((volatile  uint8_t*)(0x40038100UL))
#define FM4_MFS1_I2C_SMR                          *((volatile  uint8_t*)(0x40038100UL))
#define FM_MFS1_LIN_SMR                           *((volatile  uint8_t*)(0x40038100UL))
#define FM4_MFS1_LIN_SMR                          *((volatile  uint8_t*)(0x40038100UL))
#define FM_MFS1_UART_SMR                          *((volatile  uint8_t*)(0x40038100UL))
#define FM4_MFS1_UART_SMR                         *((volatile  uint8_t*)(0x40038100UL))
#define FM_MFS1_CSIO_SCR                          *((volatile  uint8_t*)(0x40038101UL))
#define FM4_MFS1_CSIO_SCR                         *((volatile  uint8_t*)(0x40038101UL))
#define FM_MFS1_I2C_IBCR                          *((volatile  uint8_t*)(0x40038101UL))
#define FM4_MFS1_I2C_IBCR                         *((volatile  uint8_t*)(0x40038101UL))
#define FM_MFS1_LIN_SCR                           *((volatile  uint8_t*)(0x40038101UL))
#define FM4_MFS1_LIN_SCR                          *((volatile  uint8_t*)(0x40038101UL))
#define FM_MFS1_UART_SCR                          *((volatile  uint8_t*)(0x40038101UL))
#define FM4_MFS1_UART_SCR                         *((volatile  uint8_t*)(0x40038101UL))
#define FM_MFS1_CSIO_ESCR                         *((volatile  uint8_t*)(0x40038104UL))
#define FM4_MFS1_CSIO_ESCR                        *((volatile  uint8_t*)(0x40038104UL))
#define FM_MFS1_I2C_IBSR                          *((volatile  uint8_t*)(0x40038104UL))
#define FM4_MFS1_I2C_IBSR                         *((volatile  uint8_t*)(0x40038104UL))
#define FM_MFS1_LIN_ESCR                          *((volatile  uint8_t*)(0x40038104UL))
#define FM4_MFS1_LIN_ESCR                         *((volatile  uint8_t*)(0x40038104UL))
#define FM_MFS1_UART_ESCR                         *((volatile  uint8_t*)(0x40038104UL))
#define FM4_MFS1_UART_ESCR                        *((volatile  uint8_t*)(0x40038104UL))
#define FM_MFS1_CSIO_SSR                          *((volatile  uint8_t*)(0x40038105UL))
#define FM4_MFS1_CSIO_SSR                         *((volatile  uint8_t*)(0x40038105UL))
#define FM_MFS1_I2C_SSR                           *((volatile  uint8_t*)(0x40038105UL))
#define FM4_MFS1_I2C_SSR                          *((volatile  uint8_t*)(0x40038105UL))
#define FM_MFS1_LIN_SSR                           *((volatile  uint8_t*)(0x40038105UL))
#define FM4_MFS1_LIN_SSR                          *((volatile  uint8_t*)(0x40038105UL))
#define FM_MFS1_UART_SSR                          *((volatile  uint8_t*)(0x40038105UL))
#define FM4_MFS1_UART_SSR                         *((volatile  uint8_t*)(0x40038105UL))
#define FM_MFS1_CSIO_RDR                          *((volatile uint16_t*)(0x40038108UL))
#define FM4_MFS1_CSIO_RDR                         *((volatile uint16_t*)(0x40038108UL))
#define FM_MFS1_CSIO_TDR                          *((volatile uint16_t*)(0x40038108UL))
#define FM4_MFS1_CSIO_TDR                         *((volatile uint16_t*)(0x40038108UL))
#define FM_MFS1_I2C_RDR                           *((volatile uint16_t*)(0x40038108UL))
#define FM4_MFS1_I2C_RDR                          *((volatile uint16_t*)(0x40038108UL))
#define FM_MFS1_I2C_TDR                           *((volatile uint16_t*)(0x40038108UL))
#define FM4_MFS1_I2C_TDR                          *((volatile uint16_t*)(0x40038108UL))
#define FM_MFS1_LIN_RDR                           *((volatile uint16_t*)(0x40038108UL))
#define FM4_MFS1_LIN_RDR                          *((volatile uint16_t*)(0x40038108UL))
#define FM_MFS1_LIN_TDR                           *((volatile uint16_t*)(0x40038108UL))
#define FM4_MFS1_LIN_TDR                          *((volatile uint16_t*)(0x40038108UL))
#define FM_MFS1_UART_RDR                          *((volatile uint16_t*)(0x40038108UL))
#define FM4_MFS1_UART_RDR                         *((volatile uint16_t*)(0x40038108UL))
#define FM_MFS1_UART_TDR                          *((volatile uint16_t*)(0x40038108UL))
#define FM4_MFS1_UART_TDR                         *((volatile uint16_t*)(0x40038108UL))
#define FM_MFS1_CSIO_BGR                          *((volatile uint16_t*)(0x4003810CUL))
#define FM4_MFS1_CSIO_BGR                         *((volatile uint16_t*)(0x4003810CUL))
#define FM_MFS1_I2C_BGR                           *((volatile uint16_t*)(0x4003810CUL))
#define FM4_MFS1_I2C_BGR                          *((volatile uint16_t*)(0x4003810CUL))
#define FM_MFS1_LIN_BGR                           *((volatile uint16_t*)(0x4003810CUL))
#define FM4_MFS1_LIN_BGR                          *((volatile uint16_t*)(0x4003810CUL))
#define FM_MFS1_UART_BGR                          *((volatile uint16_t*)(0x4003810CUL))
#define FM4_MFS1_UART_BGR                         *((volatile uint16_t*)(0x4003810CUL))
#define FM_MFS1_I2C_ISBA                          *((volatile  uint8_t*)(0x40038110UL))
#define FM4_MFS1_I2C_ISBA                         *((volatile  uint8_t*)(0x40038110UL))
#define FM_MFS1_I2C_ISMK                          *((volatile  uint8_t*)(0x40038111UL))
#define FM4_MFS1_I2C_ISMK                         *((volatile  uint8_t*)(0x40038111UL))
#define FM_MFS1_CSIO_FCR                          *((volatile uint16_t*)(0x40038114UL))
#define FM4_MFS1_CSIO_FCR                         *((volatile uint16_t*)(0x40038114UL))
#define FM_MFS1_I2C_FCR                           *((volatile uint16_t*)(0x40038114UL))
#define FM4_MFS1_I2C_FCR                          *((volatile uint16_t*)(0x40038114UL))
#define FM_MFS1_LIN_FCR                           *((volatile uint16_t*)(0x40038114UL))
#define FM4_MFS1_LIN_FCR                          *((volatile uint16_t*)(0x40038114UL))
#define FM_MFS1_UART_FCR                          *((volatile uint16_t*)(0x40038114UL))
#define FM4_MFS1_UART_FCR                         *((volatile uint16_t*)(0x40038114UL))
#define FM_MFS1_CSIO_FBYTE1                       *((volatile  uint8_t*)(0x40038118UL))
#define FM4_MFS1_CSIO_FBYTE1                      *((volatile  uint8_t*)(0x40038118UL))
#define FM_MFS1_I2C_FBYTE1                        *((volatile  uint8_t*)(0x40038118UL))
#define FM4_MFS1_I2C_FBYTE1                       *((volatile  uint8_t*)(0x40038118UL))
#define FM_MFS1_LIN_FBYTE1                        *((volatile  uint8_t*)(0x40038118UL))
#define FM4_MFS1_LIN_FBYTE1                       *((volatile  uint8_t*)(0x40038118UL))
#define FM_MFS1_UART_FBYTE1                       *((volatile  uint8_t*)(0x40038118UL))
#define FM4_MFS1_UART_FBYTE1                      *((volatile  uint8_t*)(0x40038118UL))
#define FM_MFS1_CSIO_FBYTE2                       *((volatile  uint8_t*)(0x40038119UL))
#define FM4_MFS1_CSIO_FBYTE2                      *((volatile  uint8_t*)(0x40038119UL))
#define FM_MFS1_I2C_FBYTE2                        *((volatile  uint8_t*)(0x40038119UL))
#define FM4_MFS1_I2C_FBYTE2                       *((volatile  uint8_t*)(0x40038119UL))
#define FM_MFS1_LIN_FBYTE2                        *((volatile  uint8_t*)(0x40038119UL))
#define FM4_MFS1_LIN_FBYTE2                       *((volatile  uint8_t*)(0x40038119UL))
#define FM_MFS1_UART_FBYTE2                       *((volatile  uint8_t*)(0x40038119UL))
#define FM4_MFS1_UART_FBYTE2                      *((volatile  uint8_t*)(0x40038119UL))
#define FM_MFS1_CSIO_SCSTR0                       *((volatile  uint8_t*)(0x4003811CUL))
#define FM4_MFS1_CSIO_SCSTR0                      *((volatile  uint8_t*)(0x4003811CUL))
#define FM_MFS1_I2C_NFCR                          *((volatile  uint8_t*)(0x4003811CUL))
#define FM4_MFS1_I2C_NFCR                         *((volatile  uint8_t*)(0x4003811CUL))
#define FM_MFS1_CSIO_SCSTR1                       *((volatile  uint8_t*)(0x4003811DUL))
#define FM4_MFS1_CSIO_SCSTR1                      *((volatile  uint8_t*)(0x4003811DUL))
#define FM_MFS1_I2C_EIBCR                         *((volatile  uint8_t*)(0x4003811DUL))
#define FM4_MFS1_I2C_EIBCR                        *((volatile  uint8_t*)(0x4003811DUL))
#define FM_MFS1_CSIO_SCSTR32                      *((volatile uint16_t*)(0x40038120UL))
#define FM4_MFS1_CSIO_SCSTR32                     *((volatile uint16_t*)(0x40038120UL))
#define FM_MFS1_CSIO_SACSR                        *((volatile uint16_t*)(0x40038124UL))
#define FM4_MFS1_CSIO_SACSR                       *((volatile uint16_t*)(0x40038124UL))
#define FM_MFS1_CSIO_STMR                         *((volatile uint16_t*)(0x40038128UL))
#define FM4_MFS1_CSIO_STMR                        *((volatile uint16_t*)(0x40038128UL))
#define FM_MFS1_CSIO_STMCR                        *((volatile uint16_t*)(0x4003812CUL))
#define FM4_MFS1_CSIO_STMCR                       *((volatile uint16_t*)(0x4003812CUL))
#define FM_MFS1_CSIO_SCSCR                        *((volatile uint16_t*)(0x40038130UL))
#define FM4_MFS1_CSIO_SCSCR                       *((volatile uint16_t*)(0x40038130UL))
#define FM_MFS1_CSIO_SCSFR0                       *((volatile  uint8_t*)(0x40038134UL))
#define FM4_MFS1_CSIO_SCSFR0                      *((volatile  uint8_t*)(0x40038134UL))
#define FM_MFS1_CSIO_SCSFR1                       *((volatile  uint8_t*)(0x40038135UL))
#define FM4_MFS1_CSIO_SCSFR1                      *((volatile  uint8_t*)(0x40038135UL))
#define FM_MFS1_CSIO_SCSFR2                       *((volatile  uint8_t*)(0x40038138UL))
#define FM4_MFS1_CSIO_SCSFR2                      *((volatile  uint8_t*)(0x40038138UL))
#define FM_MFS1_CSIO_TBYTE0                       *((volatile  uint8_t*)(0x4003813CUL))
#define FM4_MFS1_CSIO_TBYTE0                      *((volatile  uint8_t*)(0x4003813CUL))
#define FM_MFS1_CSIO_TBYTE1                       *((volatile  uint8_t*)(0x4003813DUL))
#define FM4_MFS1_CSIO_TBYTE1                      *((volatile  uint8_t*)(0x4003813DUL))
#define FM_MFS1_CSIO_TBYTE2                       *((volatile  uint8_t*)(0x40038140UL))
#define FM4_MFS1_CSIO_TBYTE2                      *((volatile  uint8_t*)(0x40038140UL))
#define FM_MFS1_CSIO_TBYTE3                       *((volatile  uint8_t*)(0x40038141UL))
#define FM4_MFS1_CSIO_TBYTE3                      *((volatile  uint8_t*)(0x40038141UL))

/*******************************************************************************
* MFS Registers MFS10
*   Register Definition
*******************************************************************************/
#define FM_MFS10_CSIO_SMR                         *((volatile  uint8_t*)(0x40038A00UL))
#define FM4_MFS10_CSIO_SMR                        *((volatile  uint8_t*)(0x40038A00UL))
#define FM_MFS10_I2C_SMR                          *((volatile  uint8_t*)(0x40038A00UL))
#define FM4_MFS10_I2C_SMR                         *((volatile  uint8_t*)(0x40038A00UL))
#define FM_MFS10_LIN_SMR                          *((volatile  uint8_t*)(0x40038A00UL))
#define FM4_MFS10_LIN_SMR                         *((volatile  uint8_t*)(0x40038A00UL))
#define FM_MFS10_UART_SMR                         *((volatile  uint8_t*)(0x40038A00UL))
#define FM4_MFS10_UART_SMR                        *((volatile  uint8_t*)(0x40038A00UL))
#define FM_MFS10_CSIO_SCR                         *((volatile  uint8_t*)(0x40038A01UL))
#define FM4_MFS10_CSIO_SCR                        *((volatile  uint8_t*)(0x40038A01UL))
#define FM_MFS10_I2C_IBCR                         *((volatile  uint8_t*)(0x40038A01UL))
#define FM4_MFS10_I2C_IBCR                        *((volatile  uint8_t*)(0x40038A01UL))
#define FM_MFS10_LIN_SCR                          *((volatile  uint8_t*)(0x40038A01UL))
#define FM4_MFS10_LIN_SCR                         *((volatile  uint8_t*)(0x40038A01UL))
#define FM_MFS10_UART_SCR                         *((volatile  uint8_t*)(0x40038A01UL))
#define FM4_MFS10_UART_SCR                        *((volatile  uint8_t*)(0x40038A01UL))
#define FM_MFS10_CSIO_ESCR                        *((volatile  uint8_t*)(0x40038A04UL))
#define FM4_MFS10_CSIO_ESCR                       *((volatile  uint8_t*)(0x40038A04UL))
#define FM_MFS10_I2C_IBSR                         *((volatile  uint8_t*)(0x40038A04UL))
#define FM4_MFS10_I2C_IBSR                        *((volatile  uint8_t*)(0x40038A04UL))
#define FM_MFS10_LIN_ESCR                         *((volatile  uint8_t*)(0x40038A04UL))
#define FM4_MFS10_LIN_ESCR                        *((volatile  uint8_t*)(0x40038A04UL))
#define FM_MFS10_UART_ESCR                        *((volatile  uint8_t*)(0x40038A04UL))
#define FM4_MFS10_UART_ESCR                       *((volatile  uint8_t*)(0x40038A04UL))
#define FM_MFS10_CSIO_SSR                         *((volatile  uint8_t*)(0x40038A05UL))
#define FM4_MFS10_CSIO_SSR                        *((volatile  uint8_t*)(0x40038A05UL))
#define FM_MFS10_I2C_SSR                          *((volatile  uint8_t*)(0x40038A05UL))
#define FM4_MFS10_I2C_SSR                         *((volatile  uint8_t*)(0x40038A05UL))
#define FM_MFS10_LIN_SSR                          *((volatile  uint8_t*)(0x40038A05UL))
#define FM4_MFS10_LIN_SSR                         *((volatile  uint8_t*)(0x40038A05UL))
#define FM_MFS10_UART_SSR                         *((volatile  uint8_t*)(0x40038A05UL))
#define FM4_MFS10_UART_SSR                        *((volatile  uint8_t*)(0x40038A05UL))
#define FM_MFS10_CSIO_RDR                         *((volatile uint16_t*)(0x40038A08UL))
#define FM4_MFS10_CSIO_RDR                        *((volatile uint16_t*)(0x40038A08UL))
#define FM_MFS10_CSIO_TDR                         *((volatile uint16_t*)(0x40038A08UL))
#define FM4_MFS10_CSIO_TDR                        *((volatile uint16_t*)(0x40038A08UL))
#define FM_MFS10_I2C_RDR                          *((volatile uint16_t*)(0x40038A08UL))
#define FM4_MFS10_I2C_RDR                         *((volatile uint16_t*)(0x40038A08UL))
#define FM_MFS10_I2C_TDR                          *((volatile uint16_t*)(0x40038A08UL))
#define FM4_MFS10_I2C_TDR                         *((volatile uint16_t*)(0x40038A08UL))
#define FM_MFS10_LIN_RDR                          *((volatile uint16_t*)(0x40038A08UL))
#define FM4_MFS10_LIN_RDR                         *((volatile uint16_t*)(0x40038A08UL))
#define FM_MFS10_LIN_TDR                          *((volatile uint16_t*)(0x40038A08UL))
#define FM4_MFS10_LIN_TDR                         *((volatile uint16_t*)(0x40038A08UL))
#define FM_MFS10_UART_RDR                         *((volatile uint16_t*)(0x40038A08UL))
#define FM4_MFS10_UART_RDR                        *((volatile uint16_t*)(0x40038A08UL))
#define FM_MFS10_UART_TDR                         *((volatile uint16_t*)(0x40038A08UL))
#define FM4_MFS10_UART_TDR                        *((volatile uint16_t*)(0x40038A08UL))
#define FM_MFS10_CSIO_BGR                         *((volatile uint16_t*)(0x40038A0CUL))
#define FM4_MFS10_CSIO_BGR                        *((volatile uint16_t*)(0x40038A0CUL))
#define FM_MFS10_I2C_BGR                          *((volatile uint16_t*)(0x40038A0CUL))
#define FM4_MFS10_I2C_BGR                         *((volatile uint16_t*)(0x40038A0CUL))
#define FM_MFS10_LIN_BGR                          *((volatile uint16_t*)(0x40038A0CUL))
#define FM4_MFS10_LIN_BGR                         *((volatile uint16_t*)(0x40038A0CUL))
#define FM_MFS10_UART_BGR                         *((volatile uint16_t*)(0x40038A0CUL))
#define FM4_MFS10_UART_BGR                        *((volatile uint16_t*)(0x40038A0CUL))
#define FM_MFS10_I2C_ISBA                         *((volatile  uint8_t*)(0x40038A10UL))
#define FM4_MFS10_I2C_ISBA                        *((volatile  uint8_t*)(0x40038A10UL))
#define FM_MFS10_I2C_ISMK                         *((volatile  uint8_t*)(0x40038A11UL))
#define FM4_MFS10_I2C_ISMK                        *((volatile  uint8_t*)(0x40038A11UL))
#define FM_MFS10_CSIO_FCR                         *((volatile uint16_t*)(0x40038A14UL))
#define FM4_MFS10_CSIO_FCR                        *((volatile uint16_t*)(0x40038A14UL))
#define FM_MFS10_I2C_FCR                          *((volatile uint16_t*)(0x40038A14UL))
#define FM4_MFS10_I2C_FCR                         *((volatile uint16_t*)(0x40038A14UL))
#define FM_MFS10_LIN_FCR                          *((volatile uint16_t*)(0x40038A14UL))
#define FM4_MFS10_LIN_FCR                         *((volatile uint16_t*)(0x40038A14UL))
#define FM_MFS10_UART_FCR                         *((volatile uint16_t*)(0x40038A14UL))
#define FM4_MFS10_UART_FCR                        *((volatile uint16_t*)(0x40038A14UL))
#define FM_MFS10_CSIO_FBYTE1                      *((volatile  uint8_t*)(0x40038A18UL))
#define FM4_MFS10_CSIO_FBYTE1                     *((volatile  uint8_t*)(0x40038A18UL))
#define FM_MFS10_I2C_FBYTE1                       *((volatile  uint8_t*)(0x40038A18UL))
#define FM4_MFS10_I2C_FBYTE1                      *((volatile  uint8_t*)(0x40038A18UL))
#define FM_MFS10_LIN_FBYTE1                       *((volatile  uint8_t*)(0x40038A18UL))
#define FM4_MFS10_LIN_FBYTE1                      *((volatile  uint8_t*)(0x40038A18UL))
#define FM_MFS10_UART_FBYTE1                      *((volatile  uint8_t*)(0x40038A18UL))
#define FM4_MFS10_UART_FBYTE1                     *((volatile  uint8_t*)(0x40038A18UL))
#define FM_MFS10_CSIO_FBYTE2                      *((volatile  uint8_t*)(0x40038A19UL))
#define FM4_MFS10_CSIO_FBYTE2                     *((volatile  uint8_t*)(0x40038A19UL))
#define FM_MFS10_I2C_FBYTE2                       *((volatile  uint8_t*)(0x40038A19UL))
#define FM4_MFS10_I2C_FBYTE2                      *((volatile  uint8_t*)(0x40038A19UL))
#define FM_MFS10_LIN_FBYTE2                       *((volatile  uint8_t*)(0x40038A19UL))
#define FM4_MFS10_LIN_FBYTE2                      *((volatile  uint8_t*)(0x40038A19UL))
#define FM_MFS10_UART_FBYTE2                      *((volatile  uint8_t*)(0x40038A19UL))
#define FM4_MFS10_UART_FBYTE2                     *((volatile  uint8_t*)(0x40038A19UL))
#define FM_MFS10_CSIO_SCSTR0                      *((volatile  uint8_t*)(0x40038A1CUL))
#define FM4_MFS10_CSIO_SCSTR0                     *((volatile  uint8_t*)(0x40038A1CUL))
#define FM_MFS10_I2C_NFCR                         *((volatile  uint8_t*)(0x40038A1CUL))
#define FM4_MFS10_I2C_NFCR                        *((volatile  uint8_t*)(0x40038A1CUL))
#define FM_MFS10_CSIO_SCSTR1                      *((volatile  uint8_t*)(0x40038A1DUL))
#define FM4_MFS10_CSIO_SCSTR1                     *((volatile  uint8_t*)(0x40038A1DUL))
#define FM_MFS10_I2C_EIBCR                        *((volatile  uint8_t*)(0x40038A1DUL))
#define FM4_MFS10_I2C_EIBCR                       *((volatile  uint8_t*)(0x40038A1DUL))
#define FM_MFS10_CSIO_SCSTR32                     *((volatile uint16_t*)(0x40038A20UL))
#define FM4_MFS10_CSIO_SCSTR32                    *((volatile uint16_t*)(0x40038A20UL))
#define FM_MFS10_CSIO_SACSR                       *((volatile uint16_t*)(0x40038A24UL))
#define FM4_MFS10_CSIO_SACSR                      *((volatile uint16_t*)(0x40038A24UL))
#define FM_MFS10_CSIO_STMR                        *((volatile uint16_t*)(0x40038A28UL))
#define FM4_MFS10_CSIO_STMR                       *((volatile uint16_t*)(0x40038A28UL))
#define FM_MFS10_CSIO_STMCR                       *((volatile uint16_t*)(0x40038A2CUL))
#define FM4_MFS10_CSIO_STMCR                      *((volatile uint16_t*)(0x40038A2CUL))
#define FM_MFS10_CSIO_SCSCR                       *((volatile uint16_t*)(0x40038A30UL))
#define FM4_MFS10_CSIO_SCSCR                      *((volatile uint16_t*)(0x40038A30UL))
#define FM_MFS10_CSIO_SCSFR0                      *((volatile  uint8_t*)(0x40038A34UL))
#define FM4_MFS10_CSIO_SCSFR0                     *((volatile  uint8_t*)(0x40038A34UL))
#define FM_MFS10_CSIO_SCSFR1                      *((volatile  uint8_t*)(0x40038A35UL))
#define FM4_MFS10_CSIO_SCSFR1                     *((volatile  uint8_t*)(0x40038A35UL))
#define FM_MFS10_CSIO_SCSFR2                      *((volatile  uint8_t*)(0x40038A38UL))
#define FM4_MFS10_CSIO_SCSFR2                     *((volatile  uint8_t*)(0x40038A38UL))
#define FM_MFS10_CSIO_TBYTE0                      *((volatile  uint8_t*)(0x40038A3CUL))
#define FM4_MFS10_CSIO_TBYTE0                     *((volatile  uint8_t*)(0x40038A3CUL))
#define FM_MFS10_CSIO_TBYTE1                      *((volatile  uint8_t*)(0x40038A3DUL))
#define FM4_MFS10_CSIO_TBYTE1                     *((volatile  uint8_t*)(0x40038A3DUL))
#define FM_MFS10_CSIO_TBYTE2                      *((volatile  uint8_t*)(0x40038A40UL))
#define FM4_MFS10_CSIO_TBYTE2                     *((volatile  uint8_t*)(0x40038A40UL))
#define FM_MFS10_CSIO_TBYTE3                      *((volatile  uint8_t*)(0x40038A41UL))
#define FM4_MFS10_CSIO_TBYTE3                     *((volatile  uint8_t*)(0x40038A41UL))

/*******************************************************************************
* MFS Registers MFS11
*   Register Definition
*******************************************************************************/
#define FM_MFS11_CSIO_SMR                         *((volatile  uint8_t*)(0x40038B00UL))
#define FM4_MFS11_CSIO_SMR                        *((volatile  uint8_t*)(0x40038B00UL))
#define FM_MFS11_I2C_SMR                          *((volatile  uint8_t*)(0x40038B00UL))
#define FM4_MFS11_I2C_SMR                         *((volatile  uint8_t*)(0x40038B00UL))
#define FM_MFS11_LIN_SMR                          *((volatile  uint8_t*)(0x40038B00UL))
#define FM4_MFS11_LIN_SMR                         *((volatile  uint8_t*)(0x40038B00UL))
#define FM_MFS11_UART_SMR                         *((volatile  uint8_t*)(0x40038B00UL))
#define FM4_MFS11_UART_SMR                        *((volatile  uint8_t*)(0x40038B00UL))
#define FM_MFS11_CSIO_SCR                         *((volatile  uint8_t*)(0x40038B01UL))
#define FM4_MFS11_CSIO_SCR                        *((volatile  uint8_t*)(0x40038B01UL))
#define FM_MFS11_I2C_IBCR                         *((volatile  uint8_t*)(0x40038B01UL))
#define FM4_MFS11_I2C_IBCR                        *((volatile  uint8_t*)(0x40038B01UL))
#define FM_MFS11_LIN_SCR                          *((volatile  uint8_t*)(0x40038B01UL))
#define FM4_MFS11_LIN_SCR                         *((volatile  uint8_t*)(0x40038B01UL))
#define FM_MFS11_UART_SCR                         *((volatile  uint8_t*)(0x40038B01UL))
#define FM4_MFS11_UART_SCR                        *((volatile  uint8_t*)(0x40038B01UL))
#define FM_MFS11_CSIO_ESCR                        *((volatile  uint8_t*)(0x40038B04UL))
#define FM4_MFS11_CSIO_ESCR                       *((volatile  uint8_t*)(0x40038B04UL))
#define FM_MFS11_I2C_IBSR                         *((volatile  uint8_t*)(0x40038B04UL))
#define FM4_MFS11_I2C_IBSR                        *((volatile  uint8_t*)(0x40038B04UL))
#define FM_MFS11_LIN_ESCR                         *((volatile  uint8_t*)(0x40038B04UL))
#define FM4_MFS11_LIN_ESCR                        *((volatile  uint8_t*)(0x40038B04UL))
#define FM_MFS11_UART_ESCR                        *((volatile  uint8_t*)(0x40038B04UL))
#define FM4_MFS11_UART_ESCR                       *((volatile  uint8_t*)(0x40038B04UL))
#define FM_MFS11_CSIO_SSR                         *((volatile  uint8_t*)(0x40038B05UL))
#define FM4_MFS11_CSIO_SSR                        *((volatile  uint8_t*)(0x40038B05UL))
#define FM_MFS11_I2C_SSR                          *((volatile  uint8_t*)(0x40038B05UL))
#define FM4_MFS11_I2C_SSR                         *((volatile  uint8_t*)(0x40038B05UL))
#define FM_MFS11_LIN_SSR                          *((volatile  uint8_t*)(0x40038B05UL))
#define FM4_MFS11_LIN_SSR                         *((volatile  uint8_t*)(0x40038B05UL))
#define FM_MFS11_UART_SSR                         *((volatile  uint8_t*)(0x40038B05UL))
#define FM4_MFS11_UART_SSR                        *((volatile  uint8_t*)(0x40038B05UL))
#define FM_MFS11_CSIO_RDR                         *((volatile uint16_t*)(0x40038B08UL))
#define FM4_MFS11_CSIO_RDR                        *((volatile uint16_t*)(0x40038B08UL))
#define FM_MFS11_CSIO_TDR                         *((volatile uint16_t*)(0x40038B08UL))
#define FM4_MFS11_CSIO_TDR                        *((volatile uint16_t*)(0x40038B08UL))
#define FM_MFS11_I2C_RDR                          *((volatile uint16_t*)(0x40038B08UL))
#define FM4_MFS11_I2C_RDR                         *((volatile uint16_t*)(0x40038B08UL))
#define FM_MFS11_I2C_TDR                          *((volatile uint16_t*)(0x40038B08UL))
#define FM4_MFS11_I2C_TDR                         *((volatile uint16_t*)(0x40038B08UL))
#define FM_MFS11_LIN_RDR                          *((volatile uint16_t*)(0x40038B08UL))
#define FM4_MFS11_LIN_RDR                         *((volatile uint16_t*)(0x40038B08UL))
#define FM_MFS11_LIN_TDR                          *((volatile uint16_t*)(0x40038B08UL))
#define FM4_MFS11_LIN_TDR                         *((volatile uint16_t*)(0x40038B08UL))
#define FM_MFS11_UART_RDR                         *((volatile uint16_t*)(0x40038B08UL))
#define FM4_MFS11_UART_RDR                        *((volatile uint16_t*)(0x40038B08UL))
#define FM_MFS11_UART_TDR                         *((volatile uint16_t*)(0x40038B08UL))
#define FM4_MFS11_UART_TDR                        *((volatile uint16_t*)(0x40038B08UL))
#define FM_MFS11_CSIO_BGR                         *((volatile uint16_t*)(0x40038B0CUL))
#define FM4_MFS11_CSIO_BGR                        *((volatile uint16_t*)(0x40038B0CUL))
#define FM_MFS11_I2C_BGR                          *((volatile uint16_t*)(0x40038B0CUL))
#define FM4_MFS11_I2C_BGR                         *((volatile uint16_t*)(0x40038B0CUL))
#define FM_MFS11_LIN_BGR                          *((volatile uint16_t*)(0x40038B0CUL))
#define FM4_MFS11_LIN_BGR                         *((volatile uint16_t*)(0x40038B0CUL))
#define FM_MFS11_UART_BGR                         *((volatile uint16_t*)(0x40038B0CUL))
#define FM4_MFS11_UART_BGR                        *((volatile uint16_t*)(0x40038B0CUL))
#define FM_MFS11_I2C_ISBA                         *((volatile  uint8_t*)(0x40038B10UL))
#define FM4_MFS11_I2C_ISBA                        *((volatile  uint8_t*)(0x40038B10UL))
#define FM_MFS11_I2C_ISMK                         *((volatile  uint8_t*)(0x40038B11UL))
#define FM4_MFS11_I2C_ISMK                        *((volatile  uint8_t*)(0x40038B11UL))
#define FM_MFS11_CSIO_FCR                         *((volatile uint16_t*)(0x40038B14UL))
#define FM4_MFS11_CSIO_FCR                        *((volatile uint16_t*)(0x40038B14UL))
#define FM_MFS11_I2C_FCR                          *((volatile uint16_t*)(0x40038B14UL))
#define FM4_MFS11_I2C_FCR                         *((volatile uint16_t*)(0x40038B14UL))
#define FM_MFS11_LIN_FCR                          *((volatile uint16_t*)(0x40038B14UL))
#define FM4_MFS11_LIN_FCR                         *((volatile uint16_t*)(0x40038B14UL))
#define FM_MFS11_UART_FCR                         *((volatile uint16_t*)(0x40038B14UL))
#define FM4_MFS11_UART_FCR                        *((volatile uint16_t*)(0x40038B14UL))
#define FM_MFS11_CSIO_FBYTE1                      *((volatile  uint8_t*)(0x40038B18UL))
#define FM4_MFS11_CSIO_FBYTE1                     *((volatile  uint8_t*)(0x40038B18UL))
#define FM_MFS11_I2C_FBYTE1                       *((volatile  uint8_t*)(0x40038B18UL))
#define FM4_MFS11_I2C_FBYTE1                      *((volatile  uint8_t*)(0x40038B18UL))
#define FM_MFS11_LIN_FBYTE1                       *((volatile  uint8_t*)(0x40038B18UL))
#define FM4_MFS11_LIN_FBYTE1                      *((volatile  uint8_t*)(0x40038B18UL))
#define FM_MFS11_UART_FBYTE1                      *((volatile  uint8_t*)(0x40038B18UL))
#define FM4_MFS11_UART_FBYTE1                     *((volatile  uint8_t*)(0x40038B18UL))
#define FM_MFS11_CSIO_FBYTE2                      *((volatile  uint8_t*)(0x40038B19UL))
#define FM4_MFS11_CSIO_FBYTE2                     *((volatile  uint8_t*)(0x40038B19UL))
#define FM_MFS11_I2C_FBYTE2                       *((volatile  uint8_t*)(0x40038B19UL))
#define FM4_MFS11_I2C_FBYTE2                      *((volatile  uint8_t*)(0x40038B19UL))
#define FM_MFS11_LIN_FBYTE2                       *((volatile  uint8_t*)(0x40038B19UL))
#define FM4_MFS11_LIN_FBYTE2                      *((volatile  uint8_t*)(0x40038B19UL))
#define FM_MFS11_UART_FBYTE2                      *((volatile  uint8_t*)(0x40038B19UL))
#define FM4_MFS11_UART_FBYTE2                     *((volatile  uint8_t*)(0x40038B19UL))
#define FM_MFS11_CSIO_SCSTR0                      *((volatile  uint8_t*)(0x40038B1CUL))
#define FM4_MFS11_CSIO_SCSTR0                     *((volatile  uint8_t*)(0x40038B1CUL))
#define FM_MFS11_I2C_NFCR                         *((volatile  uint8_t*)(0x40038B1CUL))
#define FM4_MFS11_I2C_NFCR                        *((volatile  uint8_t*)(0x40038B1CUL))
#define FM_MFS11_CSIO_SCSTR1                      *((volatile  uint8_t*)(0x40038B1DUL))
#define FM4_MFS11_CSIO_SCSTR1                     *((volatile  uint8_t*)(0x40038B1DUL))
#define FM_MFS11_I2C_EIBCR                        *((volatile  uint8_t*)(0x40038B1DUL))
#define FM4_MFS11_I2C_EIBCR                       *((volatile  uint8_t*)(0x40038B1DUL))
#define FM_MFS11_CSIO_SCSTR32                     *((volatile uint16_t*)(0x40038B20UL))
#define FM4_MFS11_CSIO_SCSTR32                    *((volatile uint16_t*)(0x40038B20UL))
#define FM_MFS11_CSIO_SACSR                       *((volatile uint16_t*)(0x40038B24UL))
#define FM4_MFS11_CSIO_SACSR                      *((volatile uint16_t*)(0x40038B24UL))
#define FM_MFS11_CSIO_STMR                        *((volatile uint16_t*)(0x40038B28UL))
#define FM4_MFS11_CSIO_STMR                       *((volatile uint16_t*)(0x40038B28UL))
#define FM_MFS11_CSIO_STMCR                       *((volatile uint16_t*)(0x40038B2CUL))
#define FM4_MFS11_CSIO_STMCR                      *((volatile uint16_t*)(0x40038B2CUL))
#define FM_MFS11_CSIO_SCSCR                       *((volatile uint16_t*)(0x40038B30UL))
#define FM4_MFS11_CSIO_SCSCR                      *((volatile uint16_t*)(0x40038B30UL))
#define FM_MFS11_CSIO_SCSFR0                      *((volatile  uint8_t*)(0x40038B34UL))
#define FM4_MFS11_CSIO_SCSFR0                     *((volatile  uint8_t*)(0x40038B34UL))
#define FM_MFS11_CSIO_SCSFR1                      *((volatile  uint8_t*)(0x40038B35UL))
#define FM4_MFS11_CSIO_SCSFR1                     *((volatile  uint8_t*)(0x40038B35UL))
#define FM_MFS11_CSIO_SCSFR2                      *((volatile  uint8_t*)(0x40038B38UL))
#define FM4_MFS11_CSIO_SCSFR2                     *((volatile  uint8_t*)(0x40038B38UL))
#define FM_MFS11_CSIO_TBYTE0                      *((volatile  uint8_t*)(0x40038B3CUL))
#define FM4_MFS11_CSIO_TBYTE0                     *((volatile  uint8_t*)(0x40038B3CUL))
#define FM_MFS11_CSIO_TBYTE1                      *((volatile  uint8_t*)(0x40038B3DUL))
#define FM4_MFS11_CSIO_TBYTE1                     *((volatile  uint8_t*)(0x40038B3DUL))
#define FM_MFS11_CSIO_TBYTE2                      *((volatile  uint8_t*)(0x40038B40UL))
#define FM4_MFS11_CSIO_TBYTE2                     *((volatile  uint8_t*)(0x40038B40UL))
#define FM_MFS11_CSIO_TBYTE3                      *((volatile  uint8_t*)(0x40038B41UL))
#define FM4_MFS11_CSIO_TBYTE3                     *((volatile  uint8_t*)(0x40038B41UL))

/*******************************************************************************
* MFS Registers MFS12
*   Register Definition
*******************************************************************************/
#define FM_MFS12_CSIO_SMR                         *((volatile  uint8_t*)(0x40038C00UL))
#define FM4_MFS12_CSIO_SMR                        *((volatile  uint8_t*)(0x40038C00UL))
#define FM_MFS12_I2C_SMR                          *((volatile  uint8_t*)(0x40038C00UL))
#define FM4_MFS12_I2C_SMR                         *((volatile  uint8_t*)(0x40038C00UL))
#define FM_MFS12_LIN_SMR                          *((volatile  uint8_t*)(0x40038C00UL))
#define FM4_MFS12_LIN_SMR                         *((volatile  uint8_t*)(0x40038C00UL))
#define FM_MFS12_UART_SMR                         *((volatile  uint8_t*)(0x40038C00UL))
#define FM4_MFS12_UART_SMR                        *((volatile  uint8_t*)(0x40038C00UL))
#define FM_MFS12_CSIO_SCR                         *((volatile  uint8_t*)(0x40038C01UL))
#define FM4_MFS12_CSIO_SCR                        *((volatile  uint8_t*)(0x40038C01UL))
#define FM_MFS12_I2C_IBCR                         *((volatile  uint8_t*)(0x40038C01UL))
#define FM4_MFS12_I2C_IBCR                        *((volatile  uint8_t*)(0x40038C01UL))
#define FM_MFS12_LIN_SCR                          *((volatile  uint8_t*)(0x40038C01UL))
#define FM4_MFS12_LIN_SCR                         *((volatile  uint8_t*)(0x40038C01UL))
#define FM_MFS12_UART_SCR                         *((volatile  uint8_t*)(0x40038C01UL))
#define FM4_MFS12_UART_SCR                        *((volatile  uint8_t*)(0x40038C01UL))
#define FM_MFS12_CSIO_ESCR                        *((volatile  uint8_t*)(0x40038C04UL))
#define FM4_MFS12_CSIO_ESCR                       *((volatile  uint8_t*)(0x40038C04UL))
#define FM_MFS12_I2C_IBSR                         *((volatile  uint8_t*)(0x40038C04UL))
#define FM4_MFS12_I2C_IBSR                        *((volatile  uint8_t*)(0x40038C04UL))
#define FM_MFS12_LIN_ESCR                         *((volatile  uint8_t*)(0x40038C04UL))
#define FM4_MFS12_LIN_ESCR                        *((volatile  uint8_t*)(0x40038C04UL))
#define FM_MFS12_UART_ESCR                        *((volatile  uint8_t*)(0x40038C04UL))
#define FM4_MFS12_UART_ESCR                       *((volatile  uint8_t*)(0x40038C04UL))
#define FM_MFS12_CSIO_SSR                         *((volatile  uint8_t*)(0x40038C05UL))
#define FM4_MFS12_CSIO_SSR                        *((volatile  uint8_t*)(0x40038C05UL))
#define FM_MFS12_I2C_SSR                          *((volatile  uint8_t*)(0x40038C05UL))
#define FM4_MFS12_I2C_SSR                         *((volatile  uint8_t*)(0x40038C05UL))
#define FM_MFS12_LIN_SSR                          *((volatile  uint8_t*)(0x40038C05UL))
#define FM4_MFS12_LIN_SSR                         *((volatile  uint8_t*)(0x40038C05UL))
#define FM_MFS12_UART_SSR                         *((volatile  uint8_t*)(0x40038C05UL))
#define FM4_MFS12_UART_SSR                        *((volatile  uint8_t*)(0x40038C05UL))
#define FM_MFS12_CSIO_RDR                         *((volatile uint16_t*)(0x40038C08UL))
#define FM4_MFS12_CSIO_RDR                        *((volatile uint16_t*)(0x40038C08UL))
#define FM_MFS12_CSIO_TDR                         *((volatile uint16_t*)(0x40038C08UL))
#define FM4_MFS12_CSIO_TDR                        *((volatile uint16_t*)(0x40038C08UL))
#define FM_MFS12_I2C_RDR                          *((volatile uint16_t*)(0x40038C08UL))
#define FM4_MFS12_I2C_RDR                         *((volatile uint16_t*)(0x40038C08UL))
#define FM_MFS12_I2C_TDR                          *((volatile uint16_t*)(0x40038C08UL))
#define FM4_MFS12_I2C_TDR                         *((volatile uint16_t*)(0x40038C08UL))
#define FM_MFS12_LIN_RDR                          *((volatile uint16_t*)(0x40038C08UL))
#define FM4_MFS12_LIN_RDR                         *((volatile uint16_t*)(0x40038C08UL))
#define FM_MFS12_LIN_TDR                          *((volatile uint16_t*)(0x40038C08UL))
#define FM4_MFS12_LIN_TDR                         *((volatile uint16_t*)(0x40038C08UL))
#define FM_MFS12_UART_RDR                         *((volatile uint16_t*)(0x40038C08UL))
#define FM4_MFS12_UART_RDR                        *((volatile uint16_t*)(0x40038C08UL))
#define FM_MFS12_UART_TDR                         *((volatile uint16_t*)(0x40038C08UL))
#define FM4_MFS12_UART_TDR                        *((volatile uint16_t*)(0x40038C08UL))
#define FM_MFS12_CSIO_BGR                         *((volatile uint16_t*)(0x40038C0CUL))
#define FM4_MFS12_CSIO_BGR                        *((volatile uint16_t*)(0x40038C0CUL))
#define FM_MFS12_I2C_BGR                          *((volatile uint16_t*)(0x40038C0CUL))
#define FM4_MFS12_I2C_BGR                         *((volatile uint16_t*)(0x40038C0CUL))
#define FM_MFS12_LIN_BGR                          *((volatile uint16_t*)(0x40038C0CUL))
#define FM4_MFS12_LIN_BGR                         *((volatile uint16_t*)(0x40038C0CUL))
#define FM_MFS12_UART_BGR                         *((volatile uint16_t*)(0x40038C0CUL))
#define FM4_MFS12_UART_BGR                        *((volatile uint16_t*)(0x40038C0CUL))
#define FM_MFS12_I2C_ISBA                         *((volatile  uint8_t*)(0x40038C10UL))
#define FM4_MFS12_I2C_ISBA                        *((volatile  uint8_t*)(0x40038C10UL))
#define FM_MFS12_I2C_ISMK                         *((volatile  uint8_t*)(0x40038C11UL))
#define FM4_MFS12_I2C_ISMK                        *((volatile  uint8_t*)(0x40038C11UL))
#define FM_MFS12_CSIO_FCR                         *((volatile uint16_t*)(0x40038C14UL))
#define FM4_MFS12_CSIO_FCR                        *((volatile uint16_t*)(0x40038C14UL))
#define FM_MFS12_I2C_FCR                          *((volatile uint16_t*)(0x40038C14UL))
#define FM4_MFS12_I2C_FCR                         *((volatile uint16_t*)(0x40038C14UL))
#define FM_MFS12_LIN_FCR                          *((volatile uint16_t*)(0x40038C14UL))
#define FM4_MFS12_LIN_FCR                         *((volatile uint16_t*)(0x40038C14UL))
#define FM_MFS12_UART_FCR                         *((volatile uint16_t*)(0x40038C14UL))
#define FM4_MFS12_UART_FCR                        *((volatile uint16_t*)(0x40038C14UL))
#define FM_MFS12_CSIO_FBYTE1                      *((volatile  uint8_t*)(0x40038C18UL))
#define FM4_MFS12_CSIO_FBYTE1                     *((volatile  uint8_t*)(0x40038C18UL))
#define FM_MFS12_I2C_FBYTE1                       *((volatile  uint8_t*)(0x40038C18UL))
#define FM4_MFS12_I2C_FBYTE1                      *((volatile  uint8_t*)(0x40038C18UL))
#define FM_MFS12_LIN_FBYTE1                       *((volatile  uint8_t*)(0x40038C18UL))
#define FM4_MFS12_LIN_FBYTE1                      *((volatile  uint8_t*)(0x40038C18UL))
#define FM_MFS12_UART_FBYTE1                      *((volatile  uint8_t*)(0x40038C18UL))
#define FM4_MFS12_UART_FBYTE1                     *((volatile  uint8_t*)(0x40038C18UL))
#define FM_MFS12_CSIO_FBYTE2                      *((volatile  uint8_t*)(0x40038C19UL))
#define FM4_MFS12_CSIO_FBYTE2                     *((volatile  uint8_t*)(0x40038C19UL))
#define FM_MFS12_I2C_FBYTE2                       *((volatile  uint8_t*)(0x40038C19UL))
#define FM4_MFS12_I2C_FBYTE2                      *((volatile  uint8_t*)(0x40038C19UL))
#define FM_MFS12_LIN_FBYTE2                       *((volatile  uint8_t*)(0x40038C19UL))
#define FM4_MFS12_LIN_FBYTE2                      *((volatile  uint8_t*)(0x40038C19UL))
#define FM_MFS12_UART_FBYTE2                      *((volatile  uint8_t*)(0x40038C19UL))
#define FM4_MFS12_UART_FBYTE2                     *((volatile  uint8_t*)(0x40038C19UL))
#define FM_MFS12_CSIO_SCSTR0                      *((volatile  uint8_t*)(0x40038C1CUL))
#define FM4_MFS12_CSIO_SCSTR0                     *((volatile  uint8_t*)(0x40038C1CUL))
#define FM_MFS12_I2C_NFCR                         *((volatile  uint8_t*)(0x40038C1CUL))
#define FM4_MFS12_I2C_NFCR                        *((volatile  uint8_t*)(0x40038C1CUL))
#define FM_MFS12_CSIO_SCSTR1                      *((volatile  uint8_t*)(0x40038C1DUL))
#define FM4_MFS12_CSIO_SCSTR1                     *((volatile  uint8_t*)(0x40038C1DUL))
#define FM_MFS12_I2C_EIBCR                        *((volatile  uint8_t*)(0x40038C1DUL))
#define FM4_MFS12_I2C_EIBCR                       *((volatile  uint8_t*)(0x40038C1DUL))
#define FM_MFS12_CSIO_SCSTR32                     *((volatile uint16_t*)(0x40038C20UL))
#define FM4_MFS12_CSIO_SCSTR32                    *((volatile uint16_t*)(0x40038C20UL))
#define FM_MFS12_CSIO_SACSR                       *((volatile uint16_t*)(0x40038C24UL))
#define FM4_MFS12_CSIO_SACSR                      *((volatile uint16_t*)(0x40038C24UL))
#define FM_MFS12_CSIO_STMR                        *((volatile uint16_t*)(0x40038C28UL))
#define FM4_MFS12_CSIO_STMR                       *((volatile uint16_t*)(0x40038C28UL))
#define FM_MFS12_CSIO_STMCR                       *((volatile uint16_t*)(0x40038C2CUL))
#define FM4_MFS12_CSIO_STMCR                      *((volatile uint16_t*)(0x40038C2CUL))
#define FM_MFS12_CSIO_SCSCR                       *((volatile uint16_t*)(0x40038C30UL))
#define FM4_MFS12_CSIO_SCSCR                      *((volatile uint16_t*)(0x40038C30UL))
#define FM_MFS12_CSIO_SCSFR0                      *((volatile  uint8_t*)(0x40038C34UL))
#define FM4_MFS12_CSIO_SCSFR0                     *((volatile  uint8_t*)(0x40038C34UL))
#define FM_MFS12_CSIO_SCSFR1                      *((volatile  uint8_t*)(0x40038C35UL))
#define FM4_MFS12_CSIO_SCSFR1                     *((volatile  uint8_t*)(0x40038C35UL))
#define FM_MFS12_CSIO_SCSFR2                      *((volatile  uint8_t*)(0x40038C38UL))
#define FM4_MFS12_CSIO_SCSFR2                     *((volatile  uint8_t*)(0x40038C38UL))
#define FM_MFS12_CSIO_TBYTE0                      *((volatile  uint8_t*)(0x40038C3CUL))
#define FM4_MFS12_CSIO_TBYTE0                     *((volatile  uint8_t*)(0x40038C3CUL))
#define FM_MFS12_CSIO_TBYTE1                      *((volatile  uint8_t*)(0x40038C3DUL))
#define FM4_MFS12_CSIO_TBYTE1                     *((volatile  uint8_t*)(0x40038C3DUL))
#define FM_MFS12_CSIO_TBYTE2                      *((volatile  uint8_t*)(0x40038C40UL))
#define FM4_MFS12_CSIO_TBYTE2                     *((volatile  uint8_t*)(0x40038C40UL))
#define FM_MFS12_CSIO_TBYTE3                      *((volatile  uint8_t*)(0x40038C41UL))
#define FM4_MFS12_CSIO_TBYTE3                     *((volatile  uint8_t*)(0x40038C41UL))

/*******************************************************************************
* MFS Registers MFS13
*   Register Definition
*******************************************************************************/
#define FM_MFS13_CSIO_SMR                         *((volatile  uint8_t*)(0x40038D00UL))
#define FM4_MFS13_CSIO_SMR                        *((volatile  uint8_t*)(0x40038D00UL))
#define FM_MFS13_I2C_SMR                          *((volatile  uint8_t*)(0x40038D00UL))
#define FM4_MFS13_I2C_SMR                         *((volatile  uint8_t*)(0x40038D00UL))
#define FM_MFS13_LIN_SMR                          *((volatile  uint8_t*)(0x40038D00UL))
#define FM4_MFS13_LIN_SMR                         *((volatile  uint8_t*)(0x40038D00UL))
#define FM_MFS13_UART_SMR                         *((volatile  uint8_t*)(0x40038D00UL))
#define FM4_MFS13_UART_SMR                        *((volatile  uint8_t*)(0x40038D00UL))
#define FM_MFS13_CSIO_SCR                         *((volatile  uint8_t*)(0x40038D01UL))
#define FM4_MFS13_CSIO_SCR                        *((volatile  uint8_t*)(0x40038D01UL))
#define FM_MFS13_I2C_IBCR                         *((volatile  uint8_t*)(0x40038D01UL))
#define FM4_MFS13_I2C_IBCR                        *((volatile  uint8_t*)(0x40038D01UL))
#define FM_MFS13_LIN_SCR                          *((volatile  uint8_t*)(0x40038D01UL))
#define FM4_MFS13_LIN_SCR                         *((volatile  uint8_t*)(0x40038D01UL))
#define FM_MFS13_UART_SCR                         *((volatile  uint8_t*)(0x40038D01UL))
#define FM4_MFS13_UART_SCR                        *((volatile  uint8_t*)(0x40038D01UL))
#define FM_MFS13_CSIO_ESCR                        *((volatile  uint8_t*)(0x40038D04UL))
#define FM4_MFS13_CSIO_ESCR                       *((volatile  uint8_t*)(0x40038D04UL))
#define FM_MFS13_I2C_IBSR                         *((volatile  uint8_t*)(0x40038D04UL))
#define FM4_MFS13_I2C_IBSR                        *((volatile  uint8_t*)(0x40038D04UL))
#define FM_MFS13_LIN_ESCR                         *((volatile  uint8_t*)(0x40038D04UL))
#define FM4_MFS13_LIN_ESCR                        *((volatile  uint8_t*)(0x40038D04UL))
#define FM_MFS13_UART_ESCR                        *((volatile  uint8_t*)(0x40038D04UL))
#define FM4_MFS13_UART_ESCR                       *((volatile  uint8_t*)(0x40038D04UL))
#define FM_MFS13_CSIO_SSR                         *((volatile  uint8_t*)(0x40038D05UL))
#define FM4_MFS13_CSIO_SSR                        *((volatile  uint8_t*)(0x40038D05UL))
#define FM_MFS13_I2C_SSR                          *((volatile  uint8_t*)(0x40038D05UL))
#define FM4_MFS13_I2C_SSR                         *((volatile  uint8_t*)(0x40038D05UL))
#define FM_MFS13_LIN_SSR                          *((volatile  uint8_t*)(0x40038D05UL))
#define FM4_MFS13_LIN_SSR                         *((volatile  uint8_t*)(0x40038D05UL))
#define FM_MFS13_UART_SSR                         *((volatile  uint8_t*)(0x40038D05UL))
#define FM4_MFS13_UART_SSR                        *((volatile  uint8_t*)(0x40038D05UL))
#define FM_MFS13_CSIO_RDR                         *((volatile uint16_t*)(0x40038D08UL))
#define FM4_MFS13_CSIO_RDR                        *((volatile uint16_t*)(0x40038D08UL))
#define FM_MFS13_CSIO_TDR                         *((volatile uint16_t*)(0x40038D08UL))
#define FM4_MFS13_CSIO_TDR                        *((volatile uint16_t*)(0x40038D08UL))
#define FM_MFS13_I2C_RDR                          *((volatile uint16_t*)(0x40038D08UL))
#define FM4_MFS13_I2C_RDR                         *((volatile uint16_t*)(0x40038D08UL))
#define FM_MFS13_I2C_TDR                          *((volatile uint16_t*)(0x40038D08UL))
#define FM4_MFS13_I2C_TDR                         *((volatile uint16_t*)(0x40038D08UL))
#define FM_MFS13_LIN_RDR                          *((volatile uint16_t*)(0x40038D08UL))
#define FM4_MFS13_LIN_RDR                         *((volatile uint16_t*)(0x40038D08UL))
#define FM_MFS13_LIN_TDR                          *((volatile uint16_t*)(0x40038D08UL))
#define FM4_MFS13_LIN_TDR                         *((volatile uint16_t*)(0x40038D08UL))
#define FM_MFS13_UART_RDR                         *((volatile uint16_t*)(0x40038D08UL))
#define FM4_MFS13_UART_RDR                        *((volatile uint16_t*)(0x40038D08UL))
#define FM_MFS13_UART_TDR                         *((volatile uint16_t*)(0x40038D08UL))
#define FM4_MFS13_UART_TDR                        *((volatile uint16_t*)(0x40038D08UL))
#define FM_MFS13_CSIO_BGR                         *((volatile uint16_t*)(0x40038D0CUL))
#define FM4_MFS13_CSIO_BGR                        *((volatile uint16_t*)(0x40038D0CUL))
#define FM_MFS13_I2C_BGR                          *((volatile uint16_t*)(0x40038D0CUL))
#define FM4_MFS13_I2C_BGR                         *((volatile uint16_t*)(0x40038D0CUL))
#define FM_MFS13_LIN_BGR                          *((volatile uint16_t*)(0x40038D0CUL))
#define FM4_MFS13_LIN_BGR                         *((volatile uint16_t*)(0x40038D0CUL))
#define FM_MFS13_UART_BGR                         *((volatile uint16_t*)(0x40038D0CUL))
#define FM4_MFS13_UART_BGR                        *((volatile uint16_t*)(0x40038D0CUL))
#define FM_MFS13_I2C_ISBA                         *((volatile  uint8_t*)(0x40038D10UL))
#define FM4_MFS13_I2C_ISBA                        *((volatile  uint8_t*)(0x40038D10UL))
#define FM_MFS13_I2C_ISMK                         *((volatile  uint8_t*)(0x40038D11UL))
#define FM4_MFS13_I2C_ISMK                        *((volatile  uint8_t*)(0x40038D11UL))
#define FM_MFS13_CSIO_FCR                         *((volatile uint16_t*)(0x40038D14UL))
#define FM4_MFS13_CSIO_FCR                        *((volatile uint16_t*)(0x40038D14UL))
#define FM_MFS13_I2C_FCR                          *((volatile uint16_t*)(0x40038D14UL))
#define FM4_MFS13_I2C_FCR                         *((volatile uint16_t*)(0x40038D14UL))
#define FM_MFS13_LIN_FCR                          *((volatile uint16_t*)(0x40038D14UL))
#define FM4_MFS13_LIN_FCR                         *((volatile uint16_t*)(0x40038D14UL))
#define FM_MFS13_UART_FCR                         *((volatile uint16_t*)(0x40038D14UL))
#define FM4_MFS13_UART_FCR                        *((volatile uint16_t*)(0x40038D14UL))
#define FM_MFS13_CSIO_FBYTE1                      *((volatile  uint8_t*)(0x40038D18UL))
#define FM4_MFS13_CSIO_FBYTE1                     *((volatile  uint8_t*)(0x40038D18UL))
#define FM_MFS13_I2C_FBYTE1                       *((volatile  uint8_t*)(0x40038D18UL))
#define FM4_MFS13_I2C_FBYTE1                      *((volatile  uint8_t*)(0x40038D18UL))
#define FM_MFS13_LIN_FBYTE1                       *((volatile  uint8_t*)(0x40038D18UL))
#define FM4_MFS13_LIN_FBYTE1                      *((volatile  uint8_t*)(0x40038D18UL))
#define FM_MFS13_UART_FBYTE1                      *((volatile  uint8_t*)(0x40038D18UL))
#define FM4_MFS13_UART_FBYTE1                     *((volatile  uint8_t*)(0x40038D18UL))
#define FM_MFS13_CSIO_FBYTE2                      *((volatile  uint8_t*)(0x40038D19UL))
#define FM4_MFS13_CSIO_FBYTE2                     *((volatile  uint8_t*)(0x40038D19UL))
#define FM_MFS13_I2C_FBYTE2                       *((volatile  uint8_t*)(0x40038D19UL))
#define FM4_MFS13_I2C_FBYTE2                      *((volatile  uint8_t*)(0x40038D19UL))
#define FM_MFS13_LIN_FBYTE2                       *((volatile  uint8_t*)(0x40038D19UL))
#define FM4_MFS13_LIN_FBYTE2                      *((volatile  uint8_t*)(0x40038D19UL))
#define FM_MFS13_UART_FBYTE2                      *((volatile  uint8_t*)(0x40038D19UL))
#define FM4_MFS13_UART_FBYTE2                     *((volatile  uint8_t*)(0x40038D19UL))
#define FM_MFS13_CSIO_SCSTR0                      *((volatile  uint8_t*)(0x40038D1CUL))
#define FM4_MFS13_CSIO_SCSTR0                     *((volatile  uint8_t*)(0x40038D1CUL))
#define FM_MFS13_I2C_NFCR                         *((volatile  uint8_t*)(0x40038D1CUL))
#define FM4_MFS13_I2C_NFCR                        *((volatile  uint8_t*)(0x40038D1CUL))
#define FM_MFS13_CSIO_SCSTR1                      *((volatile  uint8_t*)(0x40038D1DUL))
#define FM4_MFS13_CSIO_SCSTR1                     *((volatile  uint8_t*)(0x40038D1DUL))
#define FM_MFS13_I2C_EIBCR                        *((volatile  uint8_t*)(0x40038D1DUL))
#define FM4_MFS13_I2C_EIBCR                       *((volatile  uint8_t*)(0x40038D1DUL))
#define FM_MFS13_CSIO_SCSTR32                     *((volatile uint16_t*)(0x40038D20UL))
#define FM4_MFS13_CSIO_SCSTR32                    *((volatile uint16_t*)(0x40038D20UL))
#define FM_MFS13_CSIO_SACSR                       *((volatile uint16_t*)(0x40038D24UL))
#define FM4_MFS13_CSIO_SACSR                      *((volatile uint16_t*)(0x40038D24UL))
#define FM_MFS13_CSIO_STMR                        *((volatile uint16_t*)(0x40038D28UL))
#define FM4_MFS13_CSIO_STMR                       *((volatile uint16_t*)(0x40038D28UL))
#define FM_MFS13_CSIO_STMCR                       *((volatile uint16_t*)(0x40038D2CUL))
#define FM4_MFS13_CSIO_STMCR                      *((volatile uint16_t*)(0x40038D2CUL))
#define FM_MFS13_CSIO_SCSCR                       *((volatile uint16_t*)(0x40038D30UL))
#define FM4_MFS13_CSIO_SCSCR                      *((volatile uint16_t*)(0x40038D30UL))
#define FM_MFS13_CSIO_SCSFR0                      *((volatile  uint8_t*)(0x40038D34UL))
#define FM4_MFS13_CSIO_SCSFR0                     *((volatile  uint8_t*)(0x40038D34UL))
#define FM_MFS13_CSIO_SCSFR1                      *((volatile  uint8_t*)(0x40038D35UL))
#define FM4_MFS13_CSIO_SCSFR1                     *((volatile  uint8_t*)(0x40038D35UL))
#define FM_MFS13_CSIO_SCSFR2                      *((volatile  uint8_t*)(0x40038D38UL))
#define FM4_MFS13_CSIO_SCSFR2                     *((volatile  uint8_t*)(0x40038D38UL))
#define FM_MFS13_CSIO_TBYTE0                      *((volatile  uint8_t*)(0x40038D3CUL))
#define FM4_MFS13_CSIO_TBYTE0                     *((volatile  uint8_t*)(0x40038D3CUL))
#define FM_MFS13_CSIO_TBYTE1                      *((volatile  uint8_t*)(0x40038D3DUL))
#define FM4_MFS13_CSIO_TBYTE1                     *((volatile  uint8_t*)(0x40038D3DUL))
#define FM_MFS13_CSIO_TBYTE2                      *((volatile  uint8_t*)(0x40038D40UL))
#define FM4_MFS13_CSIO_TBYTE2                     *((volatile  uint8_t*)(0x40038D40UL))
#define FM_MFS13_CSIO_TBYTE3                      *((volatile  uint8_t*)(0x40038D41UL))
#define FM4_MFS13_CSIO_TBYTE3                     *((volatile  uint8_t*)(0x40038D41UL))

/*******************************************************************************
* MFS Registers MFS14
*   Register Definition
*******************************************************************************/
#define FM_MFS14_CSIO_SMR                         *((volatile  uint8_t*)(0x40038E00UL))
#define FM4_MFS14_CSIO_SMR                        *((volatile  uint8_t*)(0x40038E00UL))
#define FM_MFS14_I2C_SMR                          *((volatile  uint8_t*)(0x40038E00UL))
#define FM4_MFS14_I2C_SMR                         *((volatile  uint8_t*)(0x40038E00UL))
#define FM_MFS14_LIN_SMR                          *((volatile  uint8_t*)(0x40038E00UL))
#define FM4_MFS14_LIN_SMR                         *((volatile  uint8_t*)(0x40038E00UL))
#define FM_MFS14_UART_SMR                         *((volatile  uint8_t*)(0x40038E00UL))
#define FM4_MFS14_UART_SMR                        *((volatile  uint8_t*)(0x40038E00UL))
#define FM_MFS14_CSIO_SCR                         *((volatile  uint8_t*)(0x40038E01UL))
#define FM4_MFS14_CSIO_SCR                        *((volatile  uint8_t*)(0x40038E01UL))
#define FM_MFS14_I2C_IBCR                         *((volatile  uint8_t*)(0x40038E01UL))
#define FM4_MFS14_I2C_IBCR                        *((volatile  uint8_t*)(0x40038E01UL))
#define FM_MFS14_LIN_SCR                          *((volatile  uint8_t*)(0x40038E01UL))
#define FM4_MFS14_LIN_SCR                         *((volatile  uint8_t*)(0x40038E01UL))
#define FM_MFS14_UART_SCR                         *((volatile  uint8_t*)(0x40038E01UL))
#define FM4_MFS14_UART_SCR                        *((volatile  uint8_t*)(0x40038E01UL))
#define FM_MFS14_CSIO_ESCR                        *((volatile  uint8_t*)(0x40038E04UL))
#define FM4_MFS14_CSIO_ESCR                       *((volatile  uint8_t*)(0x40038E04UL))
#define FM_MFS14_I2C_IBSR                         *((volatile  uint8_t*)(0x40038E04UL))
#define FM4_MFS14_I2C_IBSR                        *((volatile  uint8_t*)(0x40038E04UL))
#define FM_MFS14_LIN_ESCR                         *((volatile  uint8_t*)(0x40038E04UL))
#define FM4_MFS14_LIN_ESCR                        *((volatile  uint8_t*)(0x40038E04UL))
#define FM_MFS14_UART_ESCR                        *((volatile  uint8_t*)(0x40038E04UL))
#define FM4_MFS14_UART_ESCR                       *((volatile  uint8_t*)(0x40038E04UL))
#define FM_MFS14_CSIO_SSR                         *((volatile  uint8_t*)(0x40038E05UL))
#define FM4_MFS14_CSIO_SSR                        *((volatile  uint8_t*)(0x40038E05UL))
#define FM_MFS14_I2C_SSR                          *((volatile  uint8_t*)(0x40038E05UL))
#define FM4_MFS14_I2C_SSR                         *((volatile  uint8_t*)(0x40038E05UL))
#define FM_MFS14_LIN_SSR                          *((volatile  uint8_t*)(0x40038E05UL))
#define FM4_MFS14_LIN_SSR                         *((volatile  uint8_t*)(0x40038E05UL))
#define FM_MFS14_UART_SSR                         *((volatile  uint8_t*)(0x40038E05UL))
#define FM4_MFS14_UART_SSR                        *((volatile  uint8_t*)(0x40038E05UL))
#define FM_MFS14_CSIO_RDR                         *((volatile uint16_t*)(0x40038E08UL))
#define FM4_MFS14_CSIO_RDR                        *((volatile uint16_t*)(0x40038E08UL))
#define FM_MFS14_CSIO_TDR                         *((volatile uint16_t*)(0x40038E08UL))
#define FM4_MFS14_CSIO_TDR                        *((volatile uint16_t*)(0x40038E08UL))
#define FM_MFS14_I2C_RDR                          *((volatile uint16_t*)(0x40038E08UL))
#define FM4_MFS14_I2C_RDR                         *((volatile uint16_t*)(0x40038E08UL))
#define FM_MFS14_I2C_TDR                          *((volatile uint16_t*)(0x40038E08UL))
#define FM4_MFS14_I2C_TDR                         *((volatile uint16_t*)(0x40038E08UL))
#define FM_MFS14_LIN_RDR                          *((volatile uint16_t*)(0x40038E08UL))
#define FM4_MFS14_LIN_RDR                         *((volatile uint16_t*)(0x40038E08UL))
#define FM_MFS14_LIN_TDR                          *((volatile uint16_t*)(0x40038E08UL))
#define FM4_MFS14_LIN_TDR                         *((volatile uint16_t*)(0x40038E08UL))
#define FM_MFS14_UART_RDR                         *((volatile uint16_t*)(0x40038E08UL))
#define FM4_MFS14_UART_RDR                        *((volatile uint16_t*)(0x40038E08UL))
#define FM_MFS14_UART_TDR                         *((volatile uint16_t*)(0x40038E08UL))
#define FM4_MFS14_UART_TDR                        *((volatile uint16_t*)(0x40038E08UL))
#define FM_MFS14_CSIO_BGR                         *((volatile uint16_t*)(0x40038E0CUL))
#define FM4_MFS14_CSIO_BGR                        *((volatile uint16_t*)(0x40038E0CUL))
#define FM_MFS14_I2C_BGR                          *((volatile uint16_t*)(0x40038E0CUL))
#define FM4_MFS14_I2C_BGR                         *((volatile uint16_t*)(0x40038E0CUL))
#define FM_MFS14_LIN_BGR                          *((volatile uint16_t*)(0x40038E0CUL))
#define FM4_MFS14_LIN_BGR                         *((volatile uint16_t*)(0x40038E0CUL))
#define FM_MFS14_UART_BGR                         *((volatile uint16_t*)(0x40038E0CUL))
#define FM4_MFS14_UART_BGR                        *((volatile uint16_t*)(0x40038E0CUL))
#define FM_MFS14_I2C_ISBA                         *((volatile  uint8_t*)(0x40038E10UL))
#define FM4_MFS14_I2C_ISBA                        *((volatile  uint8_t*)(0x40038E10UL))
#define FM_MFS14_I2C_ISMK                         *((volatile  uint8_t*)(0x40038E11UL))
#define FM4_MFS14_I2C_ISMK                        *((volatile  uint8_t*)(0x40038E11UL))
#define FM_MFS14_CSIO_FCR                         *((volatile uint16_t*)(0x40038E14UL))
#define FM4_MFS14_CSIO_FCR                        *((volatile uint16_t*)(0x40038E14UL))
#define FM_MFS14_I2C_FCR                          *((volatile uint16_t*)(0x40038E14UL))
#define FM4_MFS14_I2C_FCR                         *((volatile uint16_t*)(0x40038E14UL))
#define FM_MFS14_LIN_FCR                          *((volatile uint16_t*)(0x40038E14UL))
#define FM4_MFS14_LIN_FCR                         *((volatile uint16_t*)(0x40038E14UL))
#define FM_MFS14_UART_FCR                         *((volatile uint16_t*)(0x40038E14UL))
#define FM4_MFS14_UART_FCR                        *((volatile uint16_t*)(0x40038E14UL))
#define FM_MFS14_CSIO_FBYTE1                      *((volatile  uint8_t*)(0x40038E18UL))
#define FM4_MFS14_CSIO_FBYTE1                     *((volatile  uint8_t*)(0x40038E18UL))
#define FM_MFS14_I2C_FBYTE1                       *((volatile  uint8_t*)(0x40038E18UL))
#define FM4_MFS14_I2C_FBYTE1                      *((volatile  uint8_t*)(0x40038E18UL))
#define FM_MFS14_LIN_FBYTE1                       *((volatile  uint8_t*)(0x40038E18UL))
#define FM4_MFS14_LIN_FBYTE1                      *((volatile  uint8_t*)(0x40038E18UL))
#define FM_MFS14_UART_FBYTE1                      *((volatile  uint8_t*)(0x40038E18UL))
#define FM4_MFS14_UART_FBYTE1                     *((volatile  uint8_t*)(0x40038E18UL))
#define FM_MFS14_CSIO_FBYTE2                      *((volatile  uint8_t*)(0x40038E19UL))
#define FM4_MFS14_CSIO_FBYTE2                     *((volatile  uint8_t*)(0x40038E19UL))
#define FM_MFS14_I2C_FBYTE2                       *((volatile  uint8_t*)(0x40038E19UL))
#define FM4_MFS14_I2C_FBYTE2                      *((volatile  uint8_t*)(0x40038E19UL))
#define FM_MFS14_LIN_FBYTE2                       *((volatile  uint8_t*)(0x40038E19UL))
#define FM4_MFS14_LIN_FBYTE2                      *((volatile  uint8_t*)(0x40038E19UL))
#define FM_MFS14_UART_FBYTE2                      *((volatile  uint8_t*)(0x40038E19UL))
#define FM4_MFS14_UART_FBYTE2                     *((volatile  uint8_t*)(0x40038E19UL))
#define FM_MFS14_CSIO_SCSTR0                      *((volatile  uint8_t*)(0x40038E1CUL))
#define FM4_MFS14_CSIO_SCSTR0                     *((volatile  uint8_t*)(0x40038E1CUL))
#define FM_MFS14_I2C_NFCR                         *((volatile  uint8_t*)(0x40038E1CUL))
#define FM4_MFS14_I2C_NFCR                        *((volatile  uint8_t*)(0x40038E1CUL))
#define FM_MFS14_CSIO_SCSTR1                      *((volatile  uint8_t*)(0x40038E1DUL))
#define FM4_MFS14_CSIO_SCSTR1                     *((volatile  uint8_t*)(0x40038E1DUL))
#define FM_MFS14_I2C_EIBCR                        *((volatile  uint8_t*)(0x40038E1DUL))
#define FM4_MFS14_I2C_EIBCR                       *((volatile  uint8_t*)(0x40038E1DUL))
#define FM_MFS14_CSIO_SCSTR32                     *((volatile uint16_t*)(0x40038E20UL))
#define FM4_MFS14_CSIO_SCSTR32                    *((volatile uint16_t*)(0x40038E20UL))
#define FM_MFS14_CSIO_SACSR                       *((volatile uint16_t*)(0x40038E24UL))
#define FM4_MFS14_CSIO_SACSR                      *((volatile uint16_t*)(0x40038E24UL))
#define FM_MFS14_CSIO_STMR                        *((volatile uint16_t*)(0x40038E28UL))
#define FM4_MFS14_CSIO_STMR                       *((volatile uint16_t*)(0x40038E28UL))
#define FM_MFS14_CSIO_STMCR                       *((volatile uint16_t*)(0x40038E2CUL))
#define FM4_MFS14_CSIO_STMCR                      *((volatile uint16_t*)(0x40038E2CUL))
#define FM_MFS14_CSIO_SCSCR                       *((volatile uint16_t*)(0x40038E30UL))
#define FM4_MFS14_CSIO_SCSCR                      *((volatile uint16_t*)(0x40038E30UL))
#define FM_MFS14_CSIO_SCSFR0                      *((volatile  uint8_t*)(0x40038E34UL))
#define FM4_MFS14_CSIO_SCSFR0                     *((volatile  uint8_t*)(0x40038E34UL))
#define FM_MFS14_CSIO_SCSFR1                      *((volatile  uint8_t*)(0x40038E35UL))
#define FM4_MFS14_CSIO_SCSFR1                     *((volatile  uint8_t*)(0x40038E35UL))
#define FM_MFS14_CSIO_SCSFR2                      *((volatile  uint8_t*)(0x40038E38UL))
#define FM4_MFS14_CSIO_SCSFR2                     *((volatile  uint8_t*)(0x40038E38UL))
#define FM_MFS14_CSIO_TBYTE0                      *((volatile  uint8_t*)(0x40038E3CUL))
#define FM4_MFS14_CSIO_TBYTE0                     *((volatile  uint8_t*)(0x40038E3CUL))
#define FM_MFS14_CSIO_TBYTE1                      *((volatile  uint8_t*)(0x40038E3DUL))
#define FM4_MFS14_CSIO_TBYTE1                     *((volatile  uint8_t*)(0x40038E3DUL))
#define FM_MFS14_CSIO_TBYTE2                      *((volatile  uint8_t*)(0x40038E40UL))
#define FM4_MFS14_CSIO_TBYTE2                     *((volatile  uint8_t*)(0x40038E40UL))
#define FM_MFS14_CSIO_TBYTE3                      *((volatile  uint8_t*)(0x40038E41UL))
#define FM4_MFS14_CSIO_TBYTE3                     *((volatile  uint8_t*)(0x40038E41UL))

/*******************************************************************************
* MFS Registers MFS15
*   Register Definition
*******************************************************************************/
#define FM_MFS15_CSIO_SMR                         *((volatile  uint8_t*)(0x40038F00UL))
#define FM4_MFS15_CSIO_SMR                        *((volatile  uint8_t*)(0x40038F00UL))
#define FM_MFS15_I2C_SMR                          *((volatile  uint8_t*)(0x40038F00UL))
#define FM4_MFS15_I2C_SMR                         *((volatile  uint8_t*)(0x40038F00UL))
#define FM_MFS15_LIN_SMR                          *((volatile  uint8_t*)(0x40038F00UL))
#define FM4_MFS15_LIN_SMR                         *((volatile  uint8_t*)(0x40038F00UL))
#define FM_MFS15_UART_SMR                         *((volatile  uint8_t*)(0x40038F00UL))
#define FM4_MFS15_UART_SMR                        *((volatile  uint8_t*)(0x40038F00UL))
#define FM_MFS15_CSIO_SCR                         *((volatile  uint8_t*)(0x40038F01UL))
#define FM4_MFS15_CSIO_SCR                        *((volatile  uint8_t*)(0x40038F01UL))
#define FM_MFS15_I2C_IBCR                         *((volatile  uint8_t*)(0x40038F01UL))
#define FM4_MFS15_I2C_IBCR                        *((volatile  uint8_t*)(0x40038F01UL))
#define FM_MFS15_LIN_SCR                          *((volatile  uint8_t*)(0x40038F01UL))
#define FM4_MFS15_LIN_SCR                         *((volatile  uint8_t*)(0x40038F01UL))
#define FM_MFS15_UART_SCR                         *((volatile  uint8_t*)(0x40038F01UL))
#define FM4_MFS15_UART_SCR                        *((volatile  uint8_t*)(0x40038F01UL))
#define FM_MFS15_CSIO_ESCR                        *((volatile  uint8_t*)(0x40038F04UL))
#define FM4_MFS15_CSIO_ESCR                       *((volatile  uint8_t*)(0x40038F04UL))
#define FM_MFS15_I2C_IBSR                         *((volatile  uint8_t*)(0x40038F04UL))
#define FM4_MFS15_I2C_IBSR                        *((volatile  uint8_t*)(0x40038F04UL))
#define FM_MFS15_LIN_ESCR                         *((volatile  uint8_t*)(0x40038F04UL))
#define FM4_MFS15_LIN_ESCR                        *((volatile  uint8_t*)(0x40038F04UL))
#define FM_MFS15_UART_ESCR                        *((volatile  uint8_t*)(0x40038F04UL))
#define FM4_MFS15_UART_ESCR                       *((volatile  uint8_t*)(0x40038F04UL))
#define FM_MFS15_CSIO_SSR                         *((volatile  uint8_t*)(0x40038F05UL))
#define FM4_MFS15_CSIO_SSR                        *((volatile  uint8_t*)(0x40038F05UL))
#define FM_MFS15_I2C_SSR                          *((volatile  uint8_t*)(0x40038F05UL))
#define FM4_MFS15_I2C_SSR                         *((volatile  uint8_t*)(0x40038F05UL))
#define FM_MFS15_LIN_SSR                          *((volatile  uint8_t*)(0x40038F05UL))
#define FM4_MFS15_LIN_SSR                         *((volatile  uint8_t*)(0x40038F05UL))
#define FM_MFS15_UART_SSR                         *((volatile  uint8_t*)(0x40038F05UL))
#define FM4_MFS15_UART_SSR                        *((volatile  uint8_t*)(0x40038F05UL))
#define FM_MFS15_CSIO_RDR                         *((volatile uint16_t*)(0x40038F08UL))
#define FM4_MFS15_CSIO_RDR                        *((volatile uint16_t*)(0x40038F08UL))
#define FM_MFS15_CSIO_TDR                         *((volatile uint16_t*)(0x40038F08UL))
#define FM4_MFS15_CSIO_TDR                        *((volatile uint16_t*)(0x40038F08UL))
#define FM_MFS15_I2C_RDR                          *((volatile uint16_t*)(0x40038F08UL))
#define FM4_MFS15_I2C_RDR                         *((volatile uint16_t*)(0x40038F08UL))
#define FM_MFS15_I2C_TDR                          *((volatile uint16_t*)(0x40038F08UL))
#define FM4_MFS15_I2C_TDR                         *((volatile uint16_t*)(0x40038F08UL))
#define FM_MFS15_LIN_RDR                          *((volatile uint16_t*)(0x40038F08UL))
#define FM4_MFS15_LIN_RDR                         *((volatile uint16_t*)(0x40038F08UL))
#define FM_MFS15_LIN_TDR                          *((volatile uint16_t*)(0x40038F08UL))
#define FM4_MFS15_LIN_TDR                         *((volatile uint16_t*)(0x40038F08UL))
#define FM_MFS15_UART_RDR                         *((volatile uint16_t*)(0x40038F08UL))
#define FM4_MFS15_UART_RDR                        *((volatile uint16_t*)(0x40038F08UL))
#define FM_MFS15_UART_TDR                         *((volatile uint16_t*)(0x40038F08UL))
#define FM4_MFS15_UART_TDR                        *((volatile uint16_t*)(0x40038F08UL))
#define FM_MFS15_CSIO_BGR                         *((volatile uint16_t*)(0x40038F0CUL))
#define FM4_MFS15_CSIO_BGR                        *((volatile uint16_t*)(0x40038F0CUL))
#define FM_MFS15_I2C_BGR                          *((volatile uint16_t*)(0x40038F0CUL))
#define FM4_MFS15_I2C_BGR                         *((volatile uint16_t*)(0x40038F0CUL))
#define FM_MFS15_LIN_BGR                          *((volatile uint16_t*)(0x40038F0CUL))
#define FM4_MFS15_LIN_BGR                         *((volatile uint16_t*)(0x40038F0CUL))
#define FM_MFS15_UART_BGR                         *((volatile uint16_t*)(0x40038F0CUL))
#define FM4_MFS15_UART_BGR                        *((volatile uint16_t*)(0x40038F0CUL))
#define FM_MFS15_I2C_ISBA                         *((volatile  uint8_t*)(0x40038F10UL))
#define FM4_MFS15_I2C_ISBA                        *((volatile  uint8_t*)(0x40038F10UL))
#define FM_MFS15_I2C_ISMK                         *((volatile  uint8_t*)(0x40038F11UL))
#define FM4_MFS15_I2C_ISMK                        *((volatile  uint8_t*)(0x40038F11UL))
#define FM_MFS15_CSIO_FCR                         *((volatile uint16_t*)(0x40038F14UL))
#define FM4_MFS15_CSIO_FCR                        *((volatile uint16_t*)(0x40038F14UL))
#define FM_MFS15_I2C_FCR                          *((volatile uint16_t*)(0x40038F14UL))
#define FM4_MFS15_I2C_FCR                         *((volatile uint16_t*)(0x40038F14UL))
#define FM_MFS15_LIN_FCR                          *((volatile uint16_t*)(0x40038F14UL))
#define FM4_MFS15_LIN_FCR                         *((volatile uint16_t*)(0x40038F14UL))
#define FM_MFS15_UART_FCR                         *((volatile uint16_t*)(0x40038F14UL))
#define FM4_MFS15_UART_FCR                        *((volatile uint16_t*)(0x40038F14UL))
#define FM_MFS15_CSIO_FBYTE1                      *((volatile  uint8_t*)(0x40038F18UL))
#define FM4_MFS15_CSIO_FBYTE1                     *((volatile  uint8_t*)(0x40038F18UL))
#define FM_MFS15_I2C_FBYTE1                       *((volatile  uint8_t*)(0x40038F18UL))
#define FM4_MFS15_I2C_FBYTE1                      *((volatile  uint8_t*)(0x40038F18UL))
#define FM_MFS15_LIN_FBYTE1                       *((volatile  uint8_t*)(0x40038F18UL))
#define FM4_MFS15_LIN_FBYTE1                      *((volatile  uint8_t*)(0x40038F18UL))
#define FM_MFS15_UART_FBYTE1                      *((volatile  uint8_t*)(0x40038F18UL))
#define FM4_MFS15_UART_FBYTE1                     *((volatile  uint8_t*)(0x40038F18UL))
#define FM_MFS15_CSIO_FBYTE2                      *((volatile  uint8_t*)(0x40038F19UL))
#define FM4_MFS15_CSIO_FBYTE2                     *((volatile  uint8_t*)(0x40038F19UL))
#define FM_MFS15_I2C_FBYTE2                       *((volatile  uint8_t*)(0x40038F19UL))
#define FM4_MFS15_I2C_FBYTE2                      *((volatile  uint8_t*)(0x40038F19UL))
#define FM_MFS15_LIN_FBYTE2                       *((volatile  uint8_t*)(0x40038F19UL))
#define FM4_MFS15_LIN_FBYTE2                      *((volatile  uint8_t*)(0x40038F19UL))
#define FM_MFS15_UART_FBYTE2                      *((volatile  uint8_t*)(0x40038F19UL))
#define FM4_MFS15_UART_FBYTE2                     *((volatile  uint8_t*)(0x40038F19UL))
#define FM_MFS15_CSIO_SCSTR0                      *((volatile  uint8_t*)(0x40038F1CUL))
#define FM4_MFS15_CSIO_SCSTR0                     *((volatile  uint8_t*)(0x40038F1CUL))
#define FM_MFS15_I2C_NFCR                         *((volatile  uint8_t*)(0x40038F1CUL))
#define FM4_MFS15_I2C_NFCR                        *((volatile  uint8_t*)(0x40038F1CUL))
#define FM_MFS15_CSIO_SCSTR1                      *((volatile  uint8_t*)(0x40038F1DUL))
#define FM4_MFS15_CSIO_SCSTR1                     *((volatile  uint8_t*)(0x40038F1DUL))
#define FM_MFS15_I2C_EIBCR                        *((volatile  uint8_t*)(0x40038F1DUL))
#define FM4_MFS15_I2C_EIBCR                       *((volatile  uint8_t*)(0x40038F1DUL))
#define FM_MFS15_CSIO_SCSTR32                     *((volatile uint16_t*)(0x40038F20UL))
#define FM4_MFS15_CSIO_SCSTR32                    *((volatile uint16_t*)(0x40038F20UL))
#define FM_MFS15_CSIO_SACSR                       *((volatile uint16_t*)(0x40038F24UL))
#define FM4_MFS15_CSIO_SACSR                      *((volatile uint16_t*)(0x40038F24UL))
#define FM_MFS15_CSIO_STMR                        *((volatile uint16_t*)(0x40038F28UL))
#define FM4_MFS15_CSIO_STMR                       *((volatile uint16_t*)(0x40038F28UL))
#define FM_MFS15_CSIO_STMCR                       *((volatile uint16_t*)(0x40038F2CUL))
#define FM4_MFS15_CSIO_STMCR                      *((volatile uint16_t*)(0x40038F2CUL))
#define FM_MFS15_CSIO_SCSCR                       *((volatile uint16_t*)(0x40038F30UL))
#define FM4_MFS15_CSIO_SCSCR                      *((volatile uint16_t*)(0x40038F30UL))
#define FM_MFS15_CSIO_SCSFR0                      *((volatile  uint8_t*)(0x40038F34UL))
#define FM4_MFS15_CSIO_SCSFR0                     *((volatile  uint8_t*)(0x40038F34UL))
#define FM_MFS15_CSIO_SCSFR1                      *((volatile  uint8_t*)(0x40038F35UL))
#define FM4_MFS15_CSIO_SCSFR1                     *((volatile  uint8_t*)(0x40038F35UL))
#define FM_MFS15_CSIO_SCSFR2                      *((volatile  uint8_t*)(0x40038F38UL))
#define FM4_MFS15_CSIO_SCSFR2                     *((volatile  uint8_t*)(0x40038F38UL))
#define FM_MFS15_CSIO_TBYTE0                      *((volatile  uint8_t*)(0x40038F3CUL))
#define FM4_MFS15_CSIO_TBYTE0                     *((volatile  uint8_t*)(0x40038F3CUL))
#define FM_MFS15_CSIO_TBYTE1                      *((volatile  uint8_t*)(0x40038F3DUL))
#define FM4_MFS15_CSIO_TBYTE1                     *((volatile  uint8_t*)(0x40038F3DUL))
#define FM_MFS15_CSIO_TBYTE2                      *((volatile  uint8_t*)(0x40038F40UL))
#define FM4_MFS15_CSIO_TBYTE2                     *((volatile  uint8_t*)(0x40038F40UL))
#define FM_MFS15_CSIO_TBYTE3                      *((volatile  uint8_t*)(0x40038F41UL))
#define FM4_MFS15_CSIO_TBYTE3                     *((volatile  uint8_t*)(0x40038F41UL))

/*******************************************************************************
* MFS Registers MFS2
*   Register Definition
*******************************************************************************/
#define FM_MFS2_CSIO_SMR                          *((volatile  uint8_t*)(0x40038200UL))
#define FM4_MFS2_CSIO_SMR                         *((volatile  uint8_t*)(0x40038200UL))
#define FM_MFS2_I2C_SMR                           *((volatile  uint8_t*)(0x40038200UL))
#define FM4_MFS2_I2C_SMR                          *((volatile  uint8_t*)(0x40038200UL))
#define FM_MFS2_LIN_SMR                           *((volatile  uint8_t*)(0x40038200UL))
#define FM4_MFS2_LIN_SMR                          *((volatile  uint8_t*)(0x40038200UL))
#define FM_MFS2_UART_SMR                          *((volatile  uint8_t*)(0x40038200UL))
#define FM4_MFS2_UART_SMR                         *((volatile  uint8_t*)(0x40038200UL))
#define FM_MFS2_CSIO_SCR                          *((volatile  uint8_t*)(0x40038201UL))
#define FM4_MFS2_CSIO_SCR                         *((volatile  uint8_t*)(0x40038201UL))
#define FM_MFS2_I2C_IBCR                          *((volatile  uint8_t*)(0x40038201UL))
#define FM4_MFS2_I2C_IBCR                         *((volatile  uint8_t*)(0x40038201UL))
#define FM_MFS2_LIN_SCR                           *((volatile  uint8_t*)(0x40038201UL))
#define FM4_MFS2_LIN_SCR                          *((volatile  uint8_t*)(0x40038201UL))
#define FM_MFS2_UART_SCR                          *((volatile  uint8_t*)(0x40038201UL))
#define FM4_MFS2_UART_SCR                         *((volatile  uint8_t*)(0x40038201UL))
#define FM_MFS2_CSIO_ESCR                         *((volatile  uint8_t*)(0x40038204UL))
#define FM4_MFS2_CSIO_ESCR                        *((volatile  uint8_t*)(0x40038204UL))
#define FM_MFS2_I2C_IBSR                          *((volatile  uint8_t*)(0x40038204UL))
#define FM4_MFS2_I2C_IBSR                         *((volatile  uint8_t*)(0x40038204UL))
#define FM_MFS2_LIN_ESCR                          *((volatile  uint8_t*)(0x40038204UL))
#define FM4_MFS2_LIN_ESCR                         *((volatile  uint8_t*)(0x40038204UL))
#define FM_MFS2_UART_ESCR                         *((volatile  uint8_t*)(0x40038204UL))
#define FM4_MFS2_UART_ESCR                        *((volatile  uint8_t*)(0x40038204UL))
#define FM_MFS2_CSIO_SSR                          *((volatile  uint8_t*)(0x40038205UL))
#define FM4_MFS2_CSIO_SSR                         *((volatile  uint8_t*)(0x40038205UL))
#define FM_MFS2_I2C_SSR                           *((volatile  uint8_t*)(0x40038205UL))
#define FM4_MFS2_I2C_SSR                          *((volatile  uint8_t*)(0x40038205UL))
#define FM_MFS2_LIN_SSR                           *((volatile  uint8_t*)(0x40038205UL))
#define FM4_MFS2_LIN_SSR                          *((volatile  uint8_t*)(0x40038205UL))
#define FM_MFS2_UART_SSR                          *((volatile  uint8_t*)(0x40038205UL))
#define FM4_MFS2_UART_SSR                         *((volatile  uint8_t*)(0x40038205UL))
#define FM_MFS2_CSIO_RDR                          *((volatile uint16_t*)(0x40038208UL))
#define FM4_MFS2_CSIO_RDR                         *((volatile uint16_t*)(0x40038208UL))
#define FM_MFS2_CSIO_TDR                          *((volatile uint16_t*)(0x40038208UL))
#define FM4_MFS2_CSIO_TDR                         *((volatile uint16_t*)(0x40038208UL))
#define FM_MFS2_I2C_RDR                           *((volatile uint16_t*)(0x40038208UL))
#define FM4_MFS2_I2C_RDR                          *((volatile uint16_t*)(0x40038208UL))
#define FM_MFS2_I2C_TDR                           *((volatile uint16_t*)(0x40038208UL))
#define FM4_MFS2_I2C_TDR                          *((volatile uint16_t*)(0x40038208UL))
#define FM_MFS2_LIN_RDR                           *((volatile uint16_t*)(0x40038208UL))
#define FM4_MFS2_LIN_RDR                          *((volatile uint16_t*)(0x40038208UL))
#define FM_MFS2_LIN_TDR                           *((volatile uint16_t*)(0x40038208UL))
#define FM4_MFS2_LIN_TDR                          *((volatile uint16_t*)(0x40038208UL))
#define FM_MFS2_UART_RDR                          *((volatile uint16_t*)(0x40038208UL))
#define FM4_MFS2_UART_RDR                         *((volatile uint16_t*)(0x40038208UL))
#define FM_MFS2_UART_TDR                          *((volatile uint16_t*)(0x40038208UL))
#define FM4_MFS2_UART_TDR                         *((volatile uint16_t*)(0x40038208UL))
#define FM_MFS2_CSIO_BGR                          *((volatile uint16_t*)(0x4003820CUL))
#define FM4_MFS2_CSIO_BGR                         *((volatile uint16_t*)(0x4003820CUL))
#define FM_MFS2_I2C_BGR                           *((volatile uint16_t*)(0x4003820CUL))
#define FM4_MFS2_I2C_BGR                          *((volatile uint16_t*)(0x4003820CUL))
#define FM_MFS2_LIN_BGR                           *((volatile uint16_t*)(0x4003820CUL))
#define FM4_MFS2_LIN_BGR                          *((volatile uint16_t*)(0x4003820CUL))
#define FM_MFS2_UART_BGR                          *((volatile uint16_t*)(0x4003820CUL))
#define FM4_MFS2_UART_BGR                         *((volatile uint16_t*)(0x4003820CUL))
#define FM_MFS2_I2C_ISBA                          *((volatile  uint8_t*)(0x40038210UL))
#define FM4_MFS2_I2C_ISBA                         *((volatile  uint8_t*)(0x40038210UL))
#define FM_MFS2_I2C_ISMK                          *((volatile  uint8_t*)(0x40038211UL))
#define FM4_MFS2_I2C_ISMK                         *((volatile  uint8_t*)(0x40038211UL))
#define FM_MFS2_CSIO_FCR                          *((volatile uint16_t*)(0x40038214UL))
#define FM4_MFS2_CSIO_FCR                         *((volatile uint16_t*)(0x40038214UL))
#define FM_MFS2_I2C_FCR                           *((volatile uint16_t*)(0x40038214UL))
#define FM4_MFS2_I2C_FCR                          *((volatile uint16_t*)(0x40038214UL))
#define FM_MFS2_LIN_FCR                           *((volatile uint16_t*)(0x40038214UL))
#define FM4_MFS2_LIN_FCR                          *((volatile uint16_t*)(0x40038214UL))
#define FM_MFS2_UART_FCR                          *((volatile uint16_t*)(0x40038214UL))
#define FM4_MFS2_UART_FCR                         *((volatile uint16_t*)(0x40038214UL))
#define FM_MFS2_CSIO_FBYTE1                       *((volatile  uint8_t*)(0x40038218UL))
#define FM4_MFS2_CSIO_FBYTE1                      *((volatile  uint8_t*)(0x40038218UL))
#define FM_MFS2_I2C_FBYTE1                        *((volatile  uint8_t*)(0x40038218UL))
#define FM4_MFS2_I2C_FBYTE1                       *((volatile  uint8_t*)(0x40038218UL))
#define FM_MFS2_LIN_FBYTE1                        *((volatile  uint8_t*)(0x40038218UL))
#define FM4_MFS2_LIN_FBYTE1                       *((volatile  uint8_t*)(0x40038218UL))
#define FM_MFS2_UART_FBYTE1                       *((volatile  uint8_t*)(0x40038218UL))
#define FM4_MFS2_UART_FBYTE1                      *((volatile  uint8_t*)(0x40038218UL))
#define FM_MFS2_CSIO_FBYTE2                       *((volatile  uint8_t*)(0x40038219UL))
#define FM4_MFS2_CSIO_FBYTE2                      *((volatile  uint8_t*)(0x40038219UL))
#define FM_MFS2_I2C_FBYTE2                        *((volatile  uint8_t*)(0x40038219UL))
#define FM4_MFS2_I2C_FBYTE2                       *((volatile  uint8_t*)(0x40038219UL))
#define FM_MFS2_LIN_FBYTE2                        *((volatile  uint8_t*)(0x40038219UL))
#define FM4_MFS2_LIN_FBYTE2                       *((volatile  uint8_t*)(0x40038219UL))
#define FM_MFS2_UART_FBYTE2                       *((volatile  uint8_t*)(0x40038219UL))
#define FM4_MFS2_UART_FBYTE2                      *((volatile  uint8_t*)(0x40038219UL))
#define FM_MFS2_CSIO_SCSTR0                       *((volatile  uint8_t*)(0x4003821CUL))
#define FM4_MFS2_CSIO_SCSTR0                      *((volatile  uint8_t*)(0x4003821CUL))
#define FM_MFS2_I2C_NFCR                          *((volatile  uint8_t*)(0x4003821CUL))
#define FM4_MFS2_I2C_NFCR                         *((volatile  uint8_t*)(0x4003821CUL))
#define FM_MFS2_CSIO_SCSTR1                       *((volatile  uint8_t*)(0x4003821DUL))
#define FM4_MFS2_CSIO_SCSTR1                      *((volatile  uint8_t*)(0x4003821DUL))
#define FM_MFS2_I2C_EIBCR                         *((volatile  uint8_t*)(0x4003821DUL))
#define FM4_MFS2_I2C_EIBCR                        *((volatile  uint8_t*)(0x4003821DUL))
#define FM_MFS2_CSIO_SCSTR32                      *((volatile uint16_t*)(0x40038220UL))
#define FM4_MFS2_CSIO_SCSTR32                     *((volatile uint16_t*)(0x40038220UL))
#define FM_MFS2_CSIO_SACSR                        *((volatile uint16_t*)(0x40038224UL))
#define FM4_MFS2_CSIO_SACSR                       *((volatile uint16_t*)(0x40038224UL))
#define FM_MFS2_CSIO_STMR                         *((volatile uint16_t*)(0x40038228UL))
#define FM4_MFS2_CSIO_STMR                        *((volatile uint16_t*)(0x40038228UL))
#define FM_MFS2_CSIO_STMCR                        *((volatile uint16_t*)(0x4003822CUL))
#define FM4_MFS2_CSIO_STMCR                       *((volatile uint16_t*)(0x4003822CUL))
#define FM_MFS2_CSIO_SCSCR                        *((volatile uint16_t*)(0x40038230UL))
#define FM4_MFS2_CSIO_SCSCR                       *((volatile uint16_t*)(0x40038230UL))
#define FM_MFS2_CSIO_SCSFR0                       *((volatile  uint8_t*)(0x40038234UL))
#define FM4_MFS2_CSIO_SCSFR0                      *((volatile  uint8_t*)(0x40038234UL))
#define FM_MFS2_CSIO_SCSFR1                       *((volatile  uint8_t*)(0x40038235UL))
#define FM4_MFS2_CSIO_SCSFR1                      *((volatile  uint8_t*)(0x40038235UL))
#define FM_MFS2_CSIO_SCSFR2                       *((volatile  uint8_t*)(0x40038238UL))
#define FM4_MFS2_CSIO_SCSFR2                      *((volatile  uint8_t*)(0x40038238UL))
#define FM_MFS2_CSIO_TBYTE0                       *((volatile  uint8_t*)(0x4003823CUL))
#define FM4_MFS2_CSIO_TBYTE0                      *((volatile  uint8_t*)(0x4003823CUL))
#define FM_MFS2_CSIO_TBYTE1                       *((volatile  uint8_t*)(0x4003823DUL))
#define FM4_MFS2_CSIO_TBYTE1                      *((volatile  uint8_t*)(0x4003823DUL))
#define FM_MFS2_CSIO_TBYTE2                       *((volatile  uint8_t*)(0x40038240UL))
#define FM4_MFS2_CSIO_TBYTE2                      *((volatile  uint8_t*)(0x40038240UL))
#define FM_MFS2_CSIO_TBYTE3                       *((volatile  uint8_t*)(0x40038241UL))
#define FM4_MFS2_CSIO_TBYTE3                      *((volatile  uint8_t*)(0x40038241UL))

/*******************************************************************************
* MFS Registers MFS3
*   Register Definition
*******************************************************************************/
#define FM_MFS3_CSIO_SMR                          *((volatile  uint8_t*)(0x40038300UL))
#define FM4_MFS3_CSIO_SMR                         *((volatile  uint8_t*)(0x40038300UL))
#define FM_MFS3_I2C_SMR                           *((volatile  uint8_t*)(0x40038300UL))
#define FM4_MFS3_I2C_SMR                          *((volatile  uint8_t*)(0x40038300UL))
#define FM_MFS3_LIN_SMR                           *((volatile  uint8_t*)(0x40038300UL))
#define FM4_MFS3_LIN_SMR                          *((volatile  uint8_t*)(0x40038300UL))
#define FM_MFS3_UART_SMR                          *((volatile  uint8_t*)(0x40038300UL))
#define FM4_MFS3_UART_SMR                         *((volatile  uint8_t*)(0x40038300UL))
#define FM_MFS3_CSIO_SCR                          *((volatile  uint8_t*)(0x40038301UL))
#define FM4_MFS3_CSIO_SCR                         *((volatile  uint8_t*)(0x40038301UL))
#define FM_MFS3_I2C_IBCR                          *((volatile  uint8_t*)(0x40038301UL))
#define FM4_MFS3_I2C_IBCR                         *((volatile  uint8_t*)(0x40038301UL))
#define FM_MFS3_LIN_SCR                           *((volatile  uint8_t*)(0x40038301UL))
#define FM4_MFS3_LIN_SCR                          *((volatile  uint8_t*)(0x40038301UL))
#define FM_MFS3_UART_SCR                          *((volatile  uint8_t*)(0x40038301UL))
#define FM4_MFS3_UART_SCR                         *((volatile  uint8_t*)(0x40038301UL))
#define FM_MFS3_CSIO_ESCR                         *((volatile  uint8_t*)(0x40038304UL))
#define FM4_MFS3_CSIO_ESCR                        *((volatile  uint8_t*)(0x40038304UL))
#define FM_MFS3_I2C_IBSR                          *((volatile  uint8_t*)(0x40038304UL))
#define FM4_MFS3_I2C_IBSR                         *((volatile  uint8_t*)(0x40038304UL))
#define FM_MFS3_LIN_ESCR                          *((volatile  uint8_t*)(0x40038304UL))
#define FM4_MFS3_LIN_ESCR                         *((volatile  uint8_t*)(0x40038304UL))
#define FM_MFS3_UART_ESCR                         *((volatile  uint8_t*)(0x40038304UL))
#define FM4_MFS3_UART_ESCR                        *((volatile  uint8_t*)(0x40038304UL))
#define FM_MFS3_CSIO_SSR                          *((volatile  uint8_t*)(0x40038305UL))
#define FM4_MFS3_CSIO_SSR                         *((volatile  uint8_t*)(0x40038305UL))
#define FM_MFS3_I2C_SSR                           *((volatile  uint8_t*)(0x40038305UL))
#define FM4_MFS3_I2C_SSR                          *((volatile  uint8_t*)(0x40038305UL))
#define FM_MFS3_LIN_SSR                           *((volatile  uint8_t*)(0x40038305UL))
#define FM4_MFS3_LIN_SSR                          *((volatile  uint8_t*)(0x40038305UL))
#define FM_MFS3_UART_SSR                          *((volatile  uint8_t*)(0x40038305UL))
#define FM4_MFS3_UART_SSR                         *((volatile  uint8_t*)(0x40038305UL))
#define FM_MFS3_CSIO_RDR                          *((volatile uint16_t*)(0x40038308UL))
#define FM4_MFS3_CSIO_RDR                         *((volatile uint16_t*)(0x40038308UL))
#define FM_MFS3_CSIO_TDR                          *((volatile uint16_t*)(0x40038308UL))
#define FM4_MFS3_CSIO_TDR                         *((volatile uint16_t*)(0x40038308UL))
#define FM_MFS3_I2C_RDR                           *((volatile uint16_t*)(0x40038308UL))
#define FM4_MFS3_I2C_RDR                          *((volatile uint16_t*)(0x40038308UL))
#define FM_MFS3_I2C_TDR                           *((volatile uint16_t*)(0x40038308UL))
#define FM4_MFS3_I2C_TDR                          *((volatile uint16_t*)(0x40038308UL))
#define FM_MFS3_LIN_RDR                           *((volatile uint16_t*)(0x40038308UL))
#define FM4_MFS3_LIN_RDR                          *((volatile uint16_t*)(0x40038308UL))
#define FM_MFS3_LIN_TDR                           *((volatile uint16_t*)(0x40038308UL))
#define FM4_MFS3_LIN_TDR                          *((volatile uint16_t*)(0x40038308UL))
#define FM_MFS3_UART_RDR                          *((volatile uint16_t*)(0x40038308UL))
#define FM4_MFS3_UART_RDR                         *((volatile uint16_t*)(0x40038308UL))
#define FM_MFS3_UART_TDR                          *((volatile uint16_t*)(0x40038308UL))
#define FM4_MFS3_UART_TDR                         *((volatile uint16_t*)(0x40038308UL))
#define FM_MFS3_CSIO_BGR                          *((volatile uint16_t*)(0x4003830CUL))
#define FM4_MFS3_CSIO_BGR                         *((volatile uint16_t*)(0x4003830CUL))
#define FM_MFS3_I2C_BGR                           *((volatile uint16_t*)(0x4003830CUL))
#define FM4_MFS3_I2C_BGR                          *((volatile uint16_t*)(0x4003830CUL))
#define FM_MFS3_LIN_BGR                           *((volatile uint16_t*)(0x4003830CUL))
#define FM4_MFS3_LIN_BGR                          *((volatile uint16_t*)(0x4003830CUL))
#define FM_MFS3_UART_BGR                          *((volatile uint16_t*)(0x4003830CUL))
#define FM4_MFS3_UART_BGR                         *((volatile uint16_t*)(0x4003830CUL))
#define FM_MFS3_I2C_ISBA                          *((volatile  uint8_t*)(0x40038310UL))
#define FM4_MFS3_I2C_ISBA                         *((volatile  uint8_t*)(0x40038310UL))
#define FM_MFS3_I2C_ISMK                          *((volatile  uint8_t*)(0x40038311UL))
#define FM4_MFS3_I2C_ISMK                         *((volatile  uint8_t*)(0x40038311UL))
#define FM_MFS3_CSIO_FCR                          *((volatile uint16_t*)(0x40038314UL))
#define FM4_MFS3_CSIO_FCR                         *((volatile uint16_t*)(0x40038314UL))
#define FM_MFS3_I2C_FCR                           *((volatile uint16_t*)(0x40038314UL))
#define FM4_MFS3_I2C_FCR                          *((volatile uint16_t*)(0x40038314UL))
#define FM_MFS3_LIN_FCR                           *((volatile uint16_t*)(0x40038314UL))
#define FM4_MFS3_LIN_FCR                          *((volatile uint16_t*)(0x40038314UL))
#define FM_MFS3_UART_FCR                          *((volatile uint16_t*)(0x40038314UL))
#define FM4_MFS3_UART_FCR                         *((volatile uint16_t*)(0x40038314UL))
#define FM_MFS3_CSIO_FBYTE1                       *((volatile  uint8_t*)(0x40038318UL))
#define FM4_MFS3_CSIO_FBYTE1                      *((volatile  uint8_t*)(0x40038318UL))
#define FM_MFS3_I2C_FBYTE1                        *((volatile  uint8_t*)(0x40038318UL))
#define FM4_MFS3_I2C_FBYTE1                       *((volatile  uint8_t*)(0x40038318UL))
#define FM_MFS3_LIN_FBYTE1                        *((volatile  uint8_t*)(0x40038318UL))
#define FM4_MFS3_LIN_FBYTE1                       *((volatile  uint8_t*)(0x40038318UL))
#define FM_MFS3_UART_FBYTE1                       *((volatile  uint8_t*)(0x40038318UL))
#define FM4_MFS3_UART_FBYTE1                      *((volatile  uint8_t*)(0x40038318UL))
#define FM_MFS3_CSIO_FBYTE2                       *((volatile  uint8_t*)(0x40038319UL))
#define FM4_MFS3_CSIO_FBYTE2                      *((volatile  uint8_t*)(0x40038319UL))
#define FM_MFS3_I2C_FBYTE2                        *((volatile  uint8_t*)(0x40038319UL))
#define FM4_MFS3_I2C_FBYTE2                       *((volatile  uint8_t*)(0x40038319UL))
#define FM_MFS3_LIN_FBYTE2                        *((volatile  uint8_t*)(0x40038319UL))
#define FM4_MFS3_LIN_FBYTE2                       *((volatile  uint8_t*)(0x40038319UL))
#define FM_MFS3_UART_FBYTE2                       *((volatile  uint8_t*)(0x40038319UL))
#define FM4_MFS3_UART_FBYTE2                      *((volatile  uint8_t*)(0x40038319UL))
#define FM_MFS3_CSIO_SCSTR0                       *((volatile  uint8_t*)(0x4003831CUL))
#define FM4_MFS3_CSIO_SCSTR0                      *((volatile  uint8_t*)(0x4003831CUL))
#define FM_MFS3_I2C_NFCR                          *((volatile  uint8_t*)(0x4003831CUL))
#define FM4_MFS3_I2C_NFCR                         *((volatile  uint8_t*)(0x4003831CUL))
#define FM_MFS3_CSIO_SCSTR1                       *((volatile  uint8_t*)(0x4003831DUL))
#define FM4_MFS3_CSIO_SCSTR1                      *((volatile  uint8_t*)(0x4003831DUL))
#define FM_MFS3_I2C_EIBCR                         *((volatile  uint8_t*)(0x4003831DUL))
#define FM4_MFS3_I2C_EIBCR                        *((volatile  uint8_t*)(0x4003831DUL))
#define FM_MFS3_CSIO_SCSTR32                      *((volatile uint16_t*)(0x40038320UL))
#define FM4_MFS3_CSIO_SCSTR32                     *((volatile uint16_t*)(0x40038320UL))
#define FM_MFS3_CSIO_SACSR                        *((volatile uint16_t*)(0x40038324UL))
#define FM4_MFS3_CSIO_SACSR                       *((volatile uint16_t*)(0x40038324UL))
#define FM_MFS3_CSIO_STMR                         *((volatile uint16_t*)(0x40038328UL))
#define FM4_MFS3_CSIO_STMR                        *((volatile uint16_t*)(0x40038328UL))
#define FM_MFS3_CSIO_STMCR                        *((volatile uint16_t*)(0x4003832CUL))
#define FM4_MFS3_CSIO_STMCR                       *((volatile uint16_t*)(0x4003832CUL))
#define FM_MFS3_CSIO_SCSCR                        *((volatile uint16_t*)(0x40038330UL))
#define FM4_MFS3_CSIO_SCSCR                       *((volatile uint16_t*)(0x40038330UL))
#define FM_MFS3_CSIO_SCSFR0                       *((volatile  uint8_t*)(0x40038334UL))
#define FM4_MFS3_CSIO_SCSFR0                      *((volatile  uint8_t*)(0x40038334UL))
#define FM_MFS3_CSIO_SCSFR1                       *((volatile  uint8_t*)(0x40038335UL))
#define FM4_MFS3_CSIO_SCSFR1                      *((volatile  uint8_t*)(0x40038335UL))
#define FM_MFS3_CSIO_SCSFR2                       *((volatile  uint8_t*)(0x40038338UL))
#define FM4_MFS3_CSIO_SCSFR2                      *((volatile  uint8_t*)(0x40038338UL))
#define FM_MFS3_CSIO_TBYTE0                       *((volatile  uint8_t*)(0x4003833CUL))
#define FM4_MFS3_CSIO_TBYTE0                      *((volatile  uint8_t*)(0x4003833CUL))
#define FM_MFS3_CSIO_TBYTE1                       *((volatile  uint8_t*)(0x4003833DUL))
#define FM4_MFS3_CSIO_TBYTE1                      *((volatile  uint8_t*)(0x4003833DUL))
#define FM_MFS3_CSIO_TBYTE2                       *((volatile  uint8_t*)(0x40038340UL))
#define FM4_MFS3_CSIO_TBYTE2                      *((volatile  uint8_t*)(0x40038340UL))
#define FM_MFS3_CSIO_TBYTE3                       *((volatile  uint8_t*)(0x40038341UL))
#define FM4_MFS3_CSIO_TBYTE3                      *((volatile  uint8_t*)(0x40038341UL))

/*******************************************************************************
* MFS Registers MFS4
*   Register Definition
*******************************************************************************/
#define FM_MFS4_CSIO_SMR                          *((volatile  uint8_t*)(0x40038400UL))
#define FM4_MFS4_CSIO_SMR                         *((volatile  uint8_t*)(0x40038400UL))
#define FM_MFS4_I2C_SMR                           *((volatile  uint8_t*)(0x40038400UL))
#define FM4_MFS4_I2C_SMR                          *((volatile  uint8_t*)(0x40038400UL))
#define FM_MFS4_LIN_SMR                           *((volatile  uint8_t*)(0x40038400UL))
#define FM4_MFS4_LIN_SMR                          *((volatile  uint8_t*)(0x40038400UL))
#define FM_MFS4_UART_SMR                          *((volatile  uint8_t*)(0x40038400UL))
#define FM4_MFS4_UART_SMR                         *((volatile  uint8_t*)(0x40038400UL))
#define FM_MFS4_CSIO_SCR                          *((volatile  uint8_t*)(0x40038401UL))
#define FM4_MFS4_CSIO_SCR                         *((volatile  uint8_t*)(0x40038401UL))
#define FM_MFS4_I2C_IBCR                          *((volatile  uint8_t*)(0x40038401UL))
#define FM4_MFS4_I2C_IBCR                         *((volatile  uint8_t*)(0x40038401UL))
#define FM_MFS4_LIN_SCR                           *((volatile  uint8_t*)(0x40038401UL))
#define FM4_MFS4_LIN_SCR                          *((volatile  uint8_t*)(0x40038401UL))
#define FM_MFS4_UART_SCR                          *((volatile  uint8_t*)(0x40038401UL))
#define FM4_MFS4_UART_SCR                         *((volatile  uint8_t*)(0x40038401UL))
#define FM_MFS4_CSIO_ESCR                         *((volatile  uint8_t*)(0x40038404UL))
#define FM4_MFS4_CSIO_ESCR                        *((volatile  uint8_t*)(0x40038404UL))
#define FM_MFS4_I2C_IBSR                          *((volatile  uint8_t*)(0x40038404UL))
#define FM4_MFS4_I2C_IBSR                         *((volatile  uint8_t*)(0x40038404UL))
#define FM_MFS4_LIN_ESCR                          *((volatile  uint8_t*)(0x40038404UL))
#define FM4_MFS4_LIN_ESCR                         *((volatile  uint8_t*)(0x40038404UL))
#define FM_MFS4_UART_ESCR                         *((volatile  uint8_t*)(0x40038404UL))
#define FM4_MFS4_UART_ESCR                        *((volatile  uint8_t*)(0x40038404UL))
#define FM_MFS4_CSIO_SSR                          *((volatile  uint8_t*)(0x40038405UL))
#define FM4_MFS4_CSIO_SSR                         *((volatile  uint8_t*)(0x40038405UL))
#define FM_MFS4_I2C_SSR                           *((volatile  uint8_t*)(0x40038405UL))
#define FM4_MFS4_I2C_SSR                          *((volatile  uint8_t*)(0x40038405UL))
#define FM_MFS4_LIN_SSR                           *((volatile  uint8_t*)(0x40038405UL))
#define FM4_MFS4_LIN_SSR                          *((volatile  uint8_t*)(0x40038405UL))
#define FM_MFS4_UART_SSR                          *((volatile  uint8_t*)(0x40038405UL))
#define FM4_MFS4_UART_SSR                         *((volatile  uint8_t*)(0x40038405UL))
#define FM_MFS4_CSIO_RDR                          *((volatile uint16_t*)(0x40038408UL))
#define FM4_MFS4_CSIO_RDR                         *((volatile uint16_t*)(0x40038408UL))
#define FM_MFS4_CSIO_TDR                          *((volatile uint16_t*)(0x40038408UL))
#define FM4_MFS4_CSIO_TDR                         *((volatile uint16_t*)(0x40038408UL))
#define FM_MFS4_I2C_RDR                           *((volatile uint16_t*)(0x40038408UL))
#define FM4_MFS4_I2C_RDR                          *((volatile uint16_t*)(0x40038408UL))
#define FM_MFS4_I2C_TDR                           *((volatile uint16_t*)(0x40038408UL))
#define FM4_MFS4_I2C_TDR                          *((volatile uint16_t*)(0x40038408UL))
#define FM_MFS4_LIN_RDR                           *((volatile uint16_t*)(0x40038408UL))
#define FM4_MFS4_LIN_RDR                          *((volatile uint16_t*)(0x40038408UL))
#define FM_MFS4_LIN_TDR                           *((volatile uint16_t*)(0x40038408UL))
#define FM4_MFS4_LIN_TDR                          *((volatile uint16_t*)(0x40038408UL))
#define FM_MFS4_UART_RDR                          *((volatile uint16_t*)(0x40038408UL))
#define FM4_MFS4_UART_RDR                         *((volatile uint16_t*)(0x40038408UL))
#define FM_MFS4_UART_TDR                          *((volatile uint16_t*)(0x40038408UL))
#define FM4_MFS4_UART_TDR                         *((volatile uint16_t*)(0x40038408UL))
#define FM_MFS4_CSIO_BGR                          *((volatile uint16_t*)(0x4003840CUL))
#define FM4_MFS4_CSIO_BGR                         *((volatile uint16_t*)(0x4003840CUL))
#define FM_MFS4_I2C_BGR                           *((volatile uint16_t*)(0x4003840CUL))
#define FM4_MFS4_I2C_BGR                          *((volatile uint16_t*)(0x4003840CUL))
#define FM_MFS4_LIN_BGR                           *((volatile uint16_t*)(0x4003840CUL))
#define FM4_MFS4_LIN_BGR                          *((volatile uint16_t*)(0x4003840CUL))
#define FM_MFS4_UART_BGR                          *((volatile uint16_t*)(0x4003840CUL))
#define FM4_MFS4_UART_BGR                         *((volatile uint16_t*)(0x4003840CUL))
#define FM_MFS4_I2C_ISBA                          *((volatile  uint8_t*)(0x40038410UL))
#define FM4_MFS4_I2C_ISBA                         *((volatile  uint8_t*)(0x40038410UL))
#define FM_MFS4_I2C_ISMK                          *((volatile  uint8_t*)(0x40038411UL))
#define FM4_MFS4_I2C_ISMK                         *((volatile  uint8_t*)(0x40038411UL))
#define FM_MFS4_CSIO_FCR                          *((volatile uint16_t*)(0x40038414UL))
#define FM4_MFS4_CSIO_FCR                         *((volatile uint16_t*)(0x40038414UL))
#define FM_MFS4_I2C_FCR                           *((volatile uint16_t*)(0x40038414UL))
#define FM4_MFS4_I2C_FCR                          *((volatile uint16_t*)(0x40038414UL))
#define FM_MFS4_LIN_FCR                           *((volatile uint16_t*)(0x40038414UL))
#define FM4_MFS4_LIN_FCR                          *((volatile uint16_t*)(0x40038414UL))
#define FM_MFS4_UART_FCR                          *((volatile uint16_t*)(0x40038414UL))
#define FM4_MFS4_UART_FCR                         *((volatile uint16_t*)(0x40038414UL))
#define FM_MFS4_CSIO_FBYTE1                       *((volatile  uint8_t*)(0x40038418UL))
#define FM4_MFS4_CSIO_FBYTE1                      *((volatile  uint8_t*)(0x40038418UL))
#define FM_MFS4_I2C_FBYTE1                        *((volatile  uint8_t*)(0x40038418UL))
#define FM4_MFS4_I2C_FBYTE1                       *((volatile  uint8_t*)(0x40038418UL))
#define FM_MFS4_LIN_FBYTE1                        *((volatile  uint8_t*)(0x40038418UL))
#define FM4_MFS4_LIN_FBYTE1                       *((volatile  uint8_t*)(0x40038418UL))
#define FM_MFS4_UART_FBYTE1                       *((volatile  uint8_t*)(0x40038418UL))
#define FM4_MFS4_UART_FBYTE1                      *((volatile  uint8_t*)(0x40038418UL))
#define FM_MFS4_CSIO_FBYTE2                       *((volatile  uint8_t*)(0x40038419UL))
#define FM4_MFS4_CSIO_FBYTE2                      *((volatile  uint8_t*)(0x40038419UL))
#define FM_MFS4_I2C_FBYTE2                        *((volatile  uint8_t*)(0x40038419UL))
#define FM4_MFS4_I2C_FBYTE2                       *((volatile  uint8_t*)(0x40038419UL))
#define FM_MFS4_LIN_FBYTE2                        *((volatile  uint8_t*)(0x40038419UL))
#define FM4_MFS4_LIN_FBYTE2                       *((volatile  uint8_t*)(0x40038419UL))
#define FM_MFS4_UART_FBYTE2                       *((volatile  uint8_t*)(0x40038419UL))
#define FM4_MFS4_UART_FBYTE2                      *((volatile  uint8_t*)(0x40038419UL))
#define FM_MFS4_CSIO_SCSTR0                       *((volatile  uint8_t*)(0x4003841CUL))
#define FM4_MFS4_CSIO_SCSTR0                      *((volatile  uint8_t*)(0x4003841CUL))
#define FM_MFS4_I2C_NFCR                          *((volatile  uint8_t*)(0x4003841CUL))
#define FM4_MFS4_I2C_NFCR                         *((volatile  uint8_t*)(0x4003841CUL))
#define FM_MFS4_CSIO_SCSTR1                       *((volatile  uint8_t*)(0x4003841DUL))
#define FM4_MFS4_CSIO_SCSTR1                      *((volatile  uint8_t*)(0x4003841DUL))
#define FM_MFS4_I2C_EIBCR                         *((volatile  uint8_t*)(0x4003841DUL))
#define FM4_MFS4_I2C_EIBCR                        *((volatile  uint8_t*)(0x4003841DUL))
#define FM_MFS4_CSIO_SCSTR32                      *((volatile uint16_t*)(0x40038420UL))
#define FM4_MFS4_CSIO_SCSTR32                     *((volatile uint16_t*)(0x40038420UL))
#define FM_MFS4_CSIO_SACSR                        *((volatile uint16_t*)(0x40038424UL))
#define FM4_MFS4_CSIO_SACSR                       *((volatile uint16_t*)(0x40038424UL))
#define FM_MFS4_CSIO_STMR                         *((volatile uint16_t*)(0x40038428UL))
#define FM4_MFS4_CSIO_STMR                        *((volatile uint16_t*)(0x40038428UL))
#define FM_MFS4_CSIO_STMCR                        *((volatile uint16_t*)(0x4003842CUL))
#define FM4_MFS4_CSIO_STMCR                       *((volatile uint16_t*)(0x4003842CUL))
#define FM_MFS4_CSIO_SCSCR                        *((volatile uint16_t*)(0x40038430UL))
#define FM4_MFS4_CSIO_SCSCR                       *((volatile uint16_t*)(0x40038430UL))
#define FM_MFS4_CSIO_SCSFR0                       *((volatile  uint8_t*)(0x40038434UL))
#define FM4_MFS4_CSIO_SCSFR0                      *((volatile  uint8_t*)(0x40038434UL))
#define FM_MFS4_CSIO_SCSFR1                       *((volatile  uint8_t*)(0x40038435UL))
#define FM4_MFS4_CSIO_SCSFR1                      *((volatile  uint8_t*)(0x40038435UL))
#define FM_MFS4_CSIO_SCSFR2                       *((volatile  uint8_t*)(0x40038438UL))
#define FM4_MFS4_CSIO_SCSFR2                      *((volatile  uint8_t*)(0x40038438UL))
#define FM_MFS4_CSIO_TBYTE0                       *((volatile  uint8_t*)(0x4003843CUL))
#define FM4_MFS4_CSIO_TBYTE0                      *((volatile  uint8_t*)(0x4003843CUL))
#define FM_MFS4_CSIO_TBYTE1                       *((volatile  uint8_t*)(0x4003843DUL))
#define FM4_MFS4_CSIO_TBYTE1                      *((volatile  uint8_t*)(0x4003843DUL))
#define FM_MFS4_CSIO_TBYTE2                       *((volatile  uint8_t*)(0x40038440UL))
#define FM4_MFS4_CSIO_TBYTE2                      *((volatile  uint8_t*)(0x40038440UL))
#define FM_MFS4_CSIO_TBYTE3                       *((volatile  uint8_t*)(0x40038441UL))
#define FM4_MFS4_CSIO_TBYTE3                      *((volatile  uint8_t*)(0x40038441UL))

/*******************************************************************************
* MFS Registers MFS5
*   Register Definition
*******************************************************************************/
#define FM_MFS5_CSIO_SMR                          *((volatile  uint8_t*)(0x40038500UL))
#define FM4_MFS5_CSIO_SMR                         *((volatile  uint8_t*)(0x40038500UL))
#define FM_MFS5_I2C_SMR                           *((volatile  uint8_t*)(0x40038500UL))
#define FM4_MFS5_I2C_SMR                          *((volatile  uint8_t*)(0x40038500UL))
#define FM_MFS5_LIN_SMR                           *((volatile  uint8_t*)(0x40038500UL))
#define FM4_MFS5_LIN_SMR                          *((volatile  uint8_t*)(0x40038500UL))
#define FM_MFS5_UART_SMR                          *((volatile  uint8_t*)(0x40038500UL))
#define FM4_MFS5_UART_SMR                         *((volatile  uint8_t*)(0x40038500UL))
#define FM_MFS5_CSIO_SCR                          *((volatile  uint8_t*)(0x40038501UL))
#define FM4_MFS5_CSIO_SCR                         *((volatile  uint8_t*)(0x40038501UL))
#define FM_MFS5_I2C_IBCR                          *((volatile  uint8_t*)(0x40038501UL))
#define FM4_MFS5_I2C_IBCR                         *((volatile  uint8_t*)(0x40038501UL))
#define FM_MFS5_LIN_SCR                           *((volatile  uint8_t*)(0x40038501UL))
#define FM4_MFS5_LIN_SCR                          *((volatile  uint8_t*)(0x40038501UL))
#define FM_MFS5_UART_SCR                          *((volatile  uint8_t*)(0x40038501UL))
#define FM4_MFS5_UART_SCR                         *((volatile  uint8_t*)(0x40038501UL))
#define FM_MFS5_CSIO_ESCR                         *((volatile  uint8_t*)(0x40038504UL))
#define FM4_MFS5_CSIO_ESCR                        *((volatile  uint8_t*)(0x40038504UL))
#define FM_MFS5_I2C_IBSR                          *((volatile  uint8_t*)(0x40038504UL))
#define FM4_MFS5_I2C_IBSR                         *((volatile  uint8_t*)(0x40038504UL))
#define FM_MFS5_LIN_ESCR                          *((volatile  uint8_t*)(0x40038504UL))
#define FM4_MFS5_LIN_ESCR                         *((volatile  uint8_t*)(0x40038504UL))
#define FM_MFS5_UART_ESCR                         *((volatile  uint8_t*)(0x40038504UL))
#define FM4_MFS5_UART_ESCR                        *((volatile  uint8_t*)(0x40038504UL))
#define FM_MFS5_CSIO_SSR                          *((volatile  uint8_t*)(0x40038505UL))
#define FM4_MFS5_CSIO_SSR                         *((volatile  uint8_t*)(0x40038505UL))
#define FM_MFS5_I2C_SSR                           *((volatile  uint8_t*)(0x40038505UL))
#define FM4_MFS5_I2C_SSR                          *((volatile  uint8_t*)(0x40038505UL))
#define FM_MFS5_LIN_SSR                           *((volatile  uint8_t*)(0x40038505UL))
#define FM4_MFS5_LIN_SSR                          *((volatile  uint8_t*)(0x40038505UL))
#define FM_MFS5_UART_SSR                          *((volatile  uint8_t*)(0x40038505UL))
#define FM4_MFS5_UART_SSR                         *((volatile  uint8_t*)(0x40038505UL))
#define FM_MFS5_CSIO_RDR                          *((volatile uint16_t*)(0x40038508UL))
#define FM4_MFS5_CSIO_RDR                         *((volatile uint16_t*)(0x40038508UL))
#define FM_MFS5_CSIO_TDR                          *((volatile uint16_t*)(0x40038508UL))
#define FM4_MFS5_CSIO_TDR                         *((volatile uint16_t*)(0x40038508UL))
#define FM_MFS5_I2C_RDR                           *((volatile uint16_t*)(0x40038508UL))
#define FM4_MFS5_I2C_RDR                          *((volatile uint16_t*)(0x40038508UL))
#define FM_MFS5_I2C_TDR                           *((volatile uint16_t*)(0x40038508UL))
#define FM4_MFS5_I2C_TDR                          *((volatile uint16_t*)(0x40038508UL))
#define FM_MFS5_LIN_RDR                           *((volatile uint16_t*)(0x40038508UL))
#define FM4_MFS5_LIN_RDR                          *((volatile uint16_t*)(0x40038508UL))
#define FM_MFS5_LIN_TDR                           *((volatile uint16_t*)(0x40038508UL))
#define FM4_MFS5_LIN_TDR                          *((volatile uint16_t*)(0x40038508UL))
#define FM_MFS5_UART_RDR                          *((volatile uint16_t*)(0x40038508UL))
#define FM4_MFS5_UART_RDR                         *((volatile uint16_t*)(0x40038508UL))
#define FM_MFS5_UART_TDR                          *((volatile uint16_t*)(0x40038508UL))
#define FM4_MFS5_UART_TDR                         *((volatile uint16_t*)(0x40038508UL))
#define FM_MFS5_CSIO_BGR                          *((volatile uint16_t*)(0x4003850CUL))
#define FM4_MFS5_CSIO_BGR                         *((volatile uint16_t*)(0x4003850CUL))
#define FM_MFS5_I2C_BGR                           *((volatile uint16_t*)(0x4003850CUL))
#define FM4_MFS5_I2C_BGR                          *((volatile uint16_t*)(0x4003850CUL))
#define FM_MFS5_LIN_BGR                           *((volatile uint16_t*)(0x4003850CUL))
#define FM4_MFS5_LIN_BGR                          *((volatile uint16_t*)(0x4003850CUL))
#define FM_MFS5_UART_BGR                          *((volatile uint16_t*)(0x4003850CUL))
#define FM4_MFS5_UART_BGR                         *((volatile uint16_t*)(0x4003850CUL))
#define FM_MFS5_I2C_ISBA                          *((volatile  uint8_t*)(0x40038510UL))
#define FM4_MFS5_I2C_ISBA                         *((volatile  uint8_t*)(0x40038510UL))
#define FM_MFS5_I2C_ISMK                          *((volatile  uint8_t*)(0x40038511UL))
#define FM4_MFS5_I2C_ISMK                         *((volatile  uint8_t*)(0x40038511UL))
#define FM_MFS5_CSIO_FCR                          *((volatile uint16_t*)(0x40038514UL))
#define FM4_MFS5_CSIO_FCR                         *((volatile uint16_t*)(0x40038514UL))
#define FM_MFS5_I2C_FCR                           *((volatile uint16_t*)(0x40038514UL))
#define FM4_MFS5_I2C_FCR                          *((volatile uint16_t*)(0x40038514UL))
#define FM_MFS5_LIN_FCR                           *((volatile uint16_t*)(0x40038514UL))
#define FM4_MFS5_LIN_FCR                          *((volatile uint16_t*)(0x40038514UL))
#define FM_MFS5_UART_FCR                          *((volatile uint16_t*)(0x40038514UL))
#define FM4_MFS5_UART_FCR                         *((volatile uint16_t*)(0x40038514UL))
#define FM_MFS5_CSIO_FBYTE1                       *((volatile  uint8_t*)(0x40038518UL))
#define FM4_MFS5_CSIO_FBYTE1                      *((volatile  uint8_t*)(0x40038518UL))
#define FM_MFS5_I2C_FBYTE1                        *((volatile  uint8_t*)(0x40038518UL))
#define FM4_MFS5_I2C_FBYTE1                       *((volatile  uint8_t*)(0x40038518UL))
#define FM_MFS5_LIN_FBYTE1                        *((volatile  uint8_t*)(0x40038518UL))
#define FM4_MFS5_LIN_FBYTE1                       *((volatile  uint8_t*)(0x40038518UL))
#define FM_MFS5_UART_FBYTE1                       *((volatile  uint8_t*)(0x40038518UL))
#define FM4_MFS5_UART_FBYTE1                      *((volatile  uint8_t*)(0x40038518UL))
#define FM_MFS5_CSIO_FBYTE2                       *((volatile  uint8_t*)(0x40038519UL))
#define FM4_MFS5_CSIO_FBYTE2                      *((volatile  uint8_t*)(0x40038519UL))
#define FM_MFS5_I2C_FBYTE2                        *((volatile  uint8_t*)(0x40038519UL))
#define FM4_MFS5_I2C_FBYTE2                       *((volatile  uint8_t*)(0x40038519UL))
#define FM_MFS5_LIN_FBYTE2                        *((volatile  uint8_t*)(0x40038519UL))
#define FM4_MFS5_LIN_FBYTE2                       *((volatile  uint8_t*)(0x40038519UL))
#define FM_MFS5_UART_FBYTE2                       *((volatile  uint8_t*)(0x40038519UL))
#define FM4_MFS5_UART_FBYTE2                      *((volatile  uint8_t*)(0x40038519UL))
#define FM_MFS5_CSIO_SCSTR0                       *((volatile  uint8_t*)(0x4003851CUL))
#define FM4_MFS5_CSIO_SCSTR0                      *((volatile  uint8_t*)(0x4003851CUL))
#define FM_MFS5_I2C_NFCR                          *((volatile  uint8_t*)(0x4003851CUL))
#define FM4_MFS5_I2C_NFCR                         *((volatile  uint8_t*)(0x4003851CUL))
#define FM_MFS5_CSIO_SCSTR1                       *((volatile  uint8_t*)(0x4003851DUL))
#define FM4_MFS5_CSIO_SCSTR1                      *((volatile  uint8_t*)(0x4003851DUL))
#define FM_MFS5_I2C_EIBCR                         *((volatile  uint8_t*)(0x4003851DUL))
#define FM4_MFS5_I2C_EIBCR                        *((volatile  uint8_t*)(0x4003851DUL))
#define FM_MFS5_CSIO_SCSTR32                      *((volatile uint16_t*)(0x40038520UL))
#define FM4_MFS5_CSIO_SCSTR32                     *((volatile uint16_t*)(0x40038520UL))
#define FM_MFS5_CSIO_SACSR                        *((volatile uint16_t*)(0x40038524UL))
#define FM4_MFS5_CSIO_SACSR                       *((volatile uint16_t*)(0x40038524UL))
#define FM_MFS5_CSIO_STMR                         *((volatile uint16_t*)(0x40038528UL))
#define FM4_MFS5_CSIO_STMR                        *((volatile uint16_t*)(0x40038528UL))
#define FM_MFS5_CSIO_STMCR                        *((volatile uint16_t*)(0x4003852CUL))
#define FM4_MFS5_CSIO_STMCR                       *((volatile uint16_t*)(0x4003852CUL))
#define FM_MFS5_CSIO_SCSCR                        *((volatile uint16_t*)(0x40038530UL))
#define FM4_MFS5_CSIO_SCSCR                       *((volatile uint16_t*)(0x40038530UL))
#define FM_MFS5_CSIO_SCSFR0                       *((volatile  uint8_t*)(0x40038534UL))
#define FM4_MFS5_CSIO_SCSFR0                      *((volatile  uint8_t*)(0x40038534UL))
#define FM_MFS5_CSIO_SCSFR1                       *((volatile  uint8_t*)(0x40038535UL))
#define FM4_MFS5_CSIO_SCSFR1                      *((volatile  uint8_t*)(0x40038535UL))
#define FM_MFS5_CSIO_SCSFR2                       *((volatile  uint8_t*)(0x40038538UL))
#define FM4_MFS5_CSIO_SCSFR2                      *((volatile  uint8_t*)(0x40038538UL))
#define FM_MFS5_CSIO_TBYTE0                       *((volatile  uint8_t*)(0x4003853CUL))
#define FM4_MFS5_CSIO_TBYTE0                      *((volatile  uint8_t*)(0x4003853CUL))
#define FM_MFS5_CSIO_TBYTE1                       *((volatile  uint8_t*)(0x4003853DUL))
#define FM4_MFS5_CSIO_TBYTE1                      *((volatile  uint8_t*)(0x4003853DUL))
#define FM_MFS5_CSIO_TBYTE2                       *((volatile  uint8_t*)(0x40038540UL))
#define FM4_MFS5_CSIO_TBYTE2                      *((volatile  uint8_t*)(0x40038540UL))
#define FM_MFS5_CSIO_TBYTE3                       *((volatile  uint8_t*)(0x40038541UL))
#define FM4_MFS5_CSIO_TBYTE3                      *((volatile  uint8_t*)(0x40038541UL))

/*******************************************************************************
* MFS Registers MFS6
*   Register Definition
*******************************************************************************/
#define FM_MFS6_CSIO_SMR                          *((volatile  uint8_t*)(0x40038600UL))
#define FM4_MFS6_CSIO_SMR                         *((volatile  uint8_t*)(0x40038600UL))
#define FM_MFS6_I2C_SMR                           *((volatile  uint8_t*)(0x40038600UL))
#define FM4_MFS6_I2C_SMR                          *((volatile  uint8_t*)(0x40038600UL))
#define FM_MFS6_LIN_SMR                           *((volatile  uint8_t*)(0x40038600UL))
#define FM4_MFS6_LIN_SMR                          *((volatile  uint8_t*)(0x40038600UL))
#define FM_MFS6_UART_SMR                          *((volatile  uint8_t*)(0x40038600UL))
#define FM4_MFS6_UART_SMR                         *((volatile  uint8_t*)(0x40038600UL))
#define FM_MFS6_CSIO_SCR                          *((volatile  uint8_t*)(0x40038601UL))
#define FM4_MFS6_CSIO_SCR                         *((volatile  uint8_t*)(0x40038601UL))
#define FM_MFS6_I2C_IBCR                          *((volatile  uint8_t*)(0x40038601UL))
#define FM4_MFS6_I2C_IBCR                         *((volatile  uint8_t*)(0x40038601UL))
#define FM_MFS6_LIN_SCR                           *((volatile  uint8_t*)(0x40038601UL))
#define FM4_MFS6_LIN_SCR                          *((volatile  uint8_t*)(0x40038601UL))
#define FM_MFS6_UART_SCR                          *((volatile  uint8_t*)(0x40038601UL))
#define FM4_MFS6_UART_SCR                         *((volatile  uint8_t*)(0x40038601UL))
#define FM_MFS6_CSIO_ESCR                         *((volatile  uint8_t*)(0x40038604UL))
#define FM4_MFS6_CSIO_ESCR                        *((volatile  uint8_t*)(0x40038604UL))
#define FM_MFS6_I2C_IBSR                          *((volatile  uint8_t*)(0x40038604UL))
#define FM4_MFS6_I2C_IBSR                         *((volatile  uint8_t*)(0x40038604UL))
#define FM_MFS6_LIN_ESCR                          *((volatile  uint8_t*)(0x40038604UL))
#define FM4_MFS6_LIN_ESCR                         *((volatile  uint8_t*)(0x40038604UL))
#define FM_MFS6_UART_ESCR                         *((volatile  uint8_t*)(0x40038604UL))
#define FM4_MFS6_UART_ESCR                        *((volatile  uint8_t*)(0x40038604UL))
#define FM_MFS6_CSIO_SSR                          *((volatile  uint8_t*)(0x40038605UL))
#define FM4_MFS6_CSIO_SSR                         *((volatile  uint8_t*)(0x40038605UL))
#define FM_MFS6_I2C_SSR                           *((volatile  uint8_t*)(0x40038605UL))
#define FM4_MFS6_I2C_SSR                          *((volatile  uint8_t*)(0x40038605UL))
#define FM_MFS6_LIN_SSR                           *((volatile  uint8_t*)(0x40038605UL))
#define FM4_MFS6_LIN_SSR                          *((volatile  uint8_t*)(0x40038605UL))
#define FM_MFS6_UART_SSR                          *((volatile  uint8_t*)(0x40038605UL))
#define FM4_MFS6_UART_SSR                         *((volatile  uint8_t*)(0x40038605UL))
#define FM_MFS6_CSIO_RDR                          *((volatile uint16_t*)(0x40038608UL))
#define FM4_MFS6_CSIO_RDR                         *((volatile uint16_t*)(0x40038608UL))
#define FM_MFS6_CSIO_TDR                          *((volatile uint16_t*)(0x40038608UL))
#define FM4_MFS6_CSIO_TDR                         *((volatile uint16_t*)(0x40038608UL))
#define FM_MFS6_I2C_RDR                           *((volatile uint16_t*)(0x40038608UL))
#define FM4_MFS6_I2C_RDR                          *((volatile uint16_t*)(0x40038608UL))
#define FM_MFS6_I2C_TDR                           *((volatile uint16_t*)(0x40038608UL))
#define FM4_MFS6_I2C_TDR                          *((volatile uint16_t*)(0x40038608UL))
#define FM_MFS6_LIN_RDR                           *((volatile uint16_t*)(0x40038608UL))
#define FM4_MFS6_LIN_RDR                          *((volatile uint16_t*)(0x40038608UL))
#define FM_MFS6_LIN_TDR                           *((volatile uint16_t*)(0x40038608UL))
#define FM4_MFS6_LIN_TDR                          *((volatile uint16_t*)(0x40038608UL))
#define FM_MFS6_UART_RDR                          *((volatile uint16_t*)(0x40038608UL))
#define FM4_MFS6_UART_RDR                         *((volatile uint16_t*)(0x40038608UL))
#define FM_MFS6_UART_TDR                          *((volatile uint16_t*)(0x40038608UL))
#define FM4_MFS6_UART_TDR                         *((volatile uint16_t*)(0x40038608UL))
#define FM_MFS6_CSIO_BGR                          *((volatile uint16_t*)(0x4003860CUL))
#define FM4_MFS6_CSIO_BGR                         *((volatile uint16_t*)(0x4003860CUL))
#define FM_MFS6_I2C_BGR                           *((volatile uint16_t*)(0x4003860CUL))
#define FM4_MFS6_I2C_BGR                          *((volatile uint16_t*)(0x4003860CUL))
#define FM_MFS6_LIN_BGR                           *((volatile uint16_t*)(0x4003860CUL))
#define FM4_MFS6_LIN_BGR                          *((volatile uint16_t*)(0x4003860CUL))
#define FM_MFS6_UART_BGR                          *((volatile uint16_t*)(0x4003860CUL))
#define FM4_MFS6_UART_BGR                         *((volatile uint16_t*)(0x4003860CUL))
#define FM_MFS6_I2C_ISBA                          *((volatile  uint8_t*)(0x40038610UL))
#define FM4_MFS6_I2C_ISBA                         *((volatile  uint8_t*)(0x40038610UL))
#define FM_MFS6_I2C_ISMK                          *((volatile  uint8_t*)(0x40038611UL))
#define FM4_MFS6_I2C_ISMK                         *((volatile  uint8_t*)(0x40038611UL))
#define FM_MFS6_CSIO_FCR                          *((volatile uint16_t*)(0x40038614UL))
#define FM4_MFS6_CSIO_FCR                         *((volatile uint16_t*)(0x40038614UL))
#define FM_MFS6_I2C_FCR                           *((volatile uint16_t*)(0x40038614UL))
#define FM4_MFS6_I2C_FCR                          *((volatile uint16_t*)(0x40038614UL))
#define FM_MFS6_LIN_FCR                           *((volatile uint16_t*)(0x40038614UL))
#define FM4_MFS6_LIN_FCR                          *((volatile uint16_t*)(0x40038614UL))
#define FM_MFS6_UART_FCR                          *((volatile uint16_t*)(0x40038614UL))
#define FM4_MFS6_UART_FCR                         *((volatile uint16_t*)(0x40038614UL))
#define FM_MFS6_CSIO_FBYTE1                       *((volatile  uint8_t*)(0x40038618UL))
#define FM4_MFS6_CSIO_FBYTE1                      *((volatile  uint8_t*)(0x40038618UL))
#define FM_MFS6_I2C_FBYTE1                        *((volatile  uint8_t*)(0x40038618UL))
#define FM4_MFS6_I2C_FBYTE1                       *((volatile  uint8_t*)(0x40038618UL))
#define FM_MFS6_LIN_FBYTE1                        *((volatile  uint8_t*)(0x40038618UL))
#define FM4_MFS6_LIN_FBYTE1                       *((volatile  uint8_t*)(0x40038618UL))
#define FM_MFS6_UART_FBYTE1                       *((volatile  uint8_t*)(0x40038618UL))
#define FM4_MFS6_UART_FBYTE1                      *((volatile  uint8_t*)(0x40038618UL))
#define FM_MFS6_CSIO_FBYTE2                       *((volatile  uint8_t*)(0x40038619UL))
#define FM4_MFS6_CSIO_FBYTE2                      *((volatile  uint8_t*)(0x40038619UL))
#define FM_MFS6_I2C_FBYTE2                        *((volatile  uint8_t*)(0x40038619UL))
#define FM4_MFS6_I2C_FBYTE2                       *((volatile  uint8_t*)(0x40038619UL))
#define FM_MFS6_LIN_FBYTE2                        *((volatile  uint8_t*)(0x40038619UL))
#define FM4_MFS6_LIN_FBYTE2                       *((volatile  uint8_t*)(0x40038619UL))
#define FM_MFS6_UART_FBYTE2                       *((volatile  uint8_t*)(0x40038619UL))
#define FM4_MFS6_UART_FBYTE2                      *((volatile  uint8_t*)(0x40038619UL))
#define FM_MFS6_CSIO_SCSTR0                       *((volatile  uint8_t*)(0x4003861CUL))
#define FM4_MFS6_CSIO_SCSTR0                      *((volatile  uint8_t*)(0x4003861CUL))
#define FM_MFS6_I2C_NFCR                          *((volatile  uint8_t*)(0x4003861CUL))
#define FM4_MFS6_I2C_NFCR                         *((volatile  uint8_t*)(0x4003861CUL))
#define FM_MFS6_CSIO_SCSTR1                       *((volatile  uint8_t*)(0x4003861DUL))
#define FM4_MFS6_CSIO_SCSTR1                      *((volatile  uint8_t*)(0x4003861DUL))
#define FM_MFS6_I2C_EIBCR                         *((volatile  uint8_t*)(0x4003861DUL))
#define FM4_MFS6_I2C_EIBCR                        *((volatile  uint8_t*)(0x4003861DUL))
#define FM_MFS6_CSIO_SCSTR32                      *((volatile uint16_t*)(0x40038620UL))
#define FM4_MFS6_CSIO_SCSTR32                     *((volatile uint16_t*)(0x40038620UL))
#define FM_MFS6_CSIO_SACSR                        *((volatile uint16_t*)(0x40038624UL))
#define FM4_MFS6_CSIO_SACSR                       *((volatile uint16_t*)(0x40038624UL))
#define FM_MFS6_CSIO_STMR                         *((volatile uint16_t*)(0x40038628UL))
#define FM4_MFS6_CSIO_STMR                        *((volatile uint16_t*)(0x40038628UL))
#define FM_MFS6_CSIO_STMCR                        *((volatile uint16_t*)(0x4003862CUL))
#define FM4_MFS6_CSIO_STMCR                       *((volatile uint16_t*)(0x4003862CUL))
#define FM_MFS6_CSIO_SCSCR                        *((volatile uint16_t*)(0x40038630UL))
#define FM4_MFS6_CSIO_SCSCR                       *((volatile uint16_t*)(0x40038630UL))
#define FM_MFS6_CSIO_SCSFR0                       *((volatile  uint8_t*)(0x40038634UL))
#define FM4_MFS6_CSIO_SCSFR0                      *((volatile  uint8_t*)(0x40038634UL))
#define FM_MFS6_CSIO_SCSFR1                       *((volatile  uint8_t*)(0x40038635UL))
#define FM4_MFS6_CSIO_SCSFR1                      *((volatile  uint8_t*)(0x40038635UL))
#define FM_MFS6_CSIO_SCSFR2                       *((volatile  uint8_t*)(0x40038638UL))
#define FM4_MFS6_CSIO_SCSFR2                      *((volatile  uint8_t*)(0x40038638UL))
#define FM_MFS6_CSIO_TBYTE0                       *((volatile  uint8_t*)(0x4003863CUL))
#define FM4_MFS6_CSIO_TBYTE0                      *((volatile  uint8_t*)(0x4003863CUL))
#define FM_MFS6_CSIO_TBYTE1                       *((volatile  uint8_t*)(0x4003863DUL))
#define FM4_MFS6_CSIO_TBYTE1                      *((volatile  uint8_t*)(0x4003863DUL))
#define FM_MFS6_CSIO_TBYTE2                       *((volatile  uint8_t*)(0x40038640UL))
#define FM4_MFS6_CSIO_TBYTE2                      *((volatile  uint8_t*)(0x40038640UL))
#define FM_MFS6_CSIO_TBYTE3                       *((volatile  uint8_t*)(0x40038641UL))
#define FM4_MFS6_CSIO_TBYTE3                      *((volatile  uint8_t*)(0x40038641UL))

/*******************************************************************************
* MFS Registers MFS7
*   Register Definition
*******************************************************************************/
#define FM_MFS7_CSIO_SMR                          *((volatile  uint8_t*)(0x40038700UL))
#define FM4_MFS7_CSIO_SMR                         *((volatile  uint8_t*)(0x40038700UL))
#define FM_MFS7_I2C_SMR                           *((volatile  uint8_t*)(0x40038700UL))
#define FM4_MFS7_I2C_SMR                          *((volatile  uint8_t*)(0x40038700UL))
#define FM_MFS7_LIN_SMR                           *((volatile  uint8_t*)(0x40038700UL))
#define FM4_MFS7_LIN_SMR                          *((volatile  uint8_t*)(0x40038700UL))
#define FM_MFS7_UART_SMR                          *((volatile  uint8_t*)(0x40038700UL))
#define FM4_MFS7_UART_SMR                         *((volatile  uint8_t*)(0x40038700UL))
#define FM_MFS7_CSIO_SCR                          *((volatile  uint8_t*)(0x40038701UL))
#define FM4_MFS7_CSIO_SCR                         *((volatile  uint8_t*)(0x40038701UL))
#define FM_MFS7_I2C_IBCR                          *((volatile  uint8_t*)(0x40038701UL))
#define FM4_MFS7_I2C_IBCR                         *((volatile  uint8_t*)(0x40038701UL))
#define FM_MFS7_LIN_SCR                           *((volatile  uint8_t*)(0x40038701UL))
#define FM4_MFS7_LIN_SCR                          *((volatile  uint8_t*)(0x40038701UL))
#define FM_MFS7_UART_SCR                          *((volatile  uint8_t*)(0x40038701UL))
#define FM4_MFS7_UART_SCR                         *((volatile  uint8_t*)(0x40038701UL))
#define FM_MFS7_CSIO_ESCR                         *((volatile  uint8_t*)(0x40038704UL))
#define FM4_MFS7_CSIO_ESCR                        *((volatile  uint8_t*)(0x40038704UL))
#define FM_MFS7_I2C_IBSR                          *((volatile  uint8_t*)(0x40038704UL))
#define FM4_MFS7_I2C_IBSR                         *((volatile  uint8_t*)(0x40038704UL))
#define FM_MFS7_LIN_ESCR                          *((volatile  uint8_t*)(0x40038704UL))
#define FM4_MFS7_LIN_ESCR                         *((volatile  uint8_t*)(0x40038704UL))
#define FM_MFS7_UART_ESCR                         *((volatile  uint8_t*)(0x40038704UL))
#define FM4_MFS7_UART_ESCR                        *((volatile  uint8_t*)(0x40038704UL))
#define FM_MFS7_CSIO_SSR                          *((volatile  uint8_t*)(0x40038705UL))
#define FM4_MFS7_CSIO_SSR                         *((volatile  uint8_t*)(0x40038705UL))
#define FM_MFS7_I2C_SSR                           *((volatile  uint8_t*)(0x40038705UL))
#define FM4_MFS7_I2C_SSR                          *((volatile  uint8_t*)(0x40038705UL))
#define FM_MFS7_LIN_SSR                           *((volatile  uint8_t*)(0x40038705UL))
#define FM4_MFS7_LIN_SSR                          *((volatile  uint8_t*)(0x40038705UL))
#define FM_MFS7_UART_SSR                          *((volatile  uint8_t*)(0x40038705UL))
#define FM4_MFS7_UART_SSR                         *((volatile  uint8_t*)(0x40038705UL))
#define FM_MFS7_CSIO_RDR                          *((volatile uint16_t*)(0x40038708UL))
#define FM4_MFS7_CSIO_RDR                         *((volatile uint16_t*)(0x40038708UL))
#define FM_MFS7_CSIO_TDR                          *((volatile uint16_t*)(0x40038708UL))
#define FM4_MFS7_CSIO_TDR                         *((volatile uint16_t*)(0x40038708UL))
#define FM_MFS7_I2C_RDR                           *((volatile uint16_t*)(0x40038708UL))
#define FM4_MFS7_I2C_RDR                          *((volatile uint16_t*)(0x40038708UL))
#define FM_MFS7_I2C_TDR                           *((volatile uint16_t*)(0x40038708UL))
#define FM4_MFS7_I2C_TDR                          *((volatile uint16_t*)(0x40038708UL))
#define FM_MFS7_LIN_RDR                           *((volatile uint16_t*)(0x40038708UL))
#define FM4_MFS7_LIN_RDR                          *((volatile uint16_t*)(0x40038708UL))
#define FM_MFS7_LIN_TDR                           *((volatile uint16_t*)(0x40038708UL))
#define FM4_MFS7_LIN_TDR                          *((volatile uint16_t*)(0x40038708UL))
#define FM_MFS7_UART_RDR                          *((volatile uint16_t*)(0x40038708UL))
#define FM4_MFS7_UART_RDR                         *((volatile uint16_t*)(0x40038708UL))
#define FM_MFS7_UART_TDR                          *((volatile uint16_t*)(0x40038708UL))
#define FM4_MFS7_UART_TDR                         *((volatile uint16_t*)(0x40038708UL))
#define FM_MFS7_CSIO_BGR                          *((volatile uint16_t*)(0x4003870CUL))
#define FM4_MFS7_CSIO_BGR                         *((volatile uint16_t*)(0x4003870CUL))
#define FM_MFS7_I2C_BGR                           *((volatile uint16_t*)(0x4003870CUL))
#define FM4_MFS7_I2C_BGR                          *((volatile uint16_t*)(0x4003870CUL))
#define FM_MFS7_LIN_BGR                           *((volatile uint16_t*)(0x4003870CUL))
#define FM4_MFS7_LIN_BGR                          *((volatile uint16_t*)(0x4003870CUL))
#define FM_MFS7_UART_BGR                          *((volatile uint16_t*)(0x4003870CUL))
#define FM4_MFS7_UART_BGR                         *((volatile uint16_t*)(0x4003870CUL))
#define FM_MFS7_I2C_ISBA                          *((volatile  uint8_t*)(0x40038710UL))
#define FM4_MFS7_I2C_ISBA                         *((volatile  uint8_t*)(0x40038710UL))
#define FM_MFS7_I2C_ISMK                          *((volatile  uint8_t*)(0x40038711UL))
#define FM4_MFS7_I2C_ISMK                         *((volatile  uint8_t*)(0x40038711UL))
#define FM_MFS7_CSIO_FCR                          *((volatile uint16_t*)(0x40038714UL))
#define FM4_MFS7_CSIO_FCR                         *((volatile uint16_t*)(0x40038714UL))
#define FM_MFS7_I2C_FCR                           *((volatile uint16_t*)(0x40038714UL))
#define FM4_MFS7_I2C_FCR                          *((volatile uint16_t*)(0x40038714UL))
#define FM_MFS7_LIN_FCR                           *((volatile uint16_t*)(0x40038714UL))
#define FM4_MFS7_LIN_FCR                          *((volatile uint16_t*)(0x40038714UL))
#define FM_MFS7_UART_FCR                          *((volatile uint16_t*)(0x40038714UL))
#define FM4_MFS7_UART_FCR                         *((volatile uint16_t*)(0x40038714UL))
#define FM_MFS7_CSIO_FBYTE1                       *((volatile  uint8_t*)(0x40038718UL))
#define FM4_MFS7_CSIO_FBYTE1                      *((volatile  uint8_t*)(0x40038718UL))
#define FM_MFS7_I2C_FBYTE1                        *((volatile  uint8_t*)(0x40038718UL))
#define FM4_MFS7_I2C_FBYTE1                       *((volatile  uint8_t*)(0x40038718UL))
#define FM_MFS7_LIN_FBYTE1                        *((volatile  uint8_t*)(0x40038718UL))
#define FM4_MFS7_LIN_FBYTE1                       *((volatile  uint8_t*)(0x40038718UL))
#define FM_MFS7_UART_FBYTE1                       *((volatile  uint8_t*)(0x40038718UL))
#define FM4_MFS7_UART_FBYTE1                      *((volatile  uint8_t*)(0x40038718UL))
#define FM_MFS7_CSIO_FBYTE2                       *((volatile  uint8_t*)(0x40038719UL))
#define FM4_MFS7_CSIO_FBYTE2                      *((volatile  uint8_t*)(0x40038719UL))
#define FM_MFS7_I2C_FBYTE2                        *((volatile  uint8_t*)(0x40038719UL))
#define FM4_MFS7_I2C_FBYTE2                       *((volatile  uint8_t*)(0x40038719UL))
#define FM_MFS7_LIN_FBYTE2                        *((volatile  uint8_t*)(0x40038719UL))
#define FM4_MFS7_LIN_FBYTE2                       *((volatile  uint8_t*)(0x40038719UL))
#define FM_MFS7_UART_FBYTE2                       *((volatile  uint8_t*)(0x40038719UL))
#define FM4_MFS7_UART_FBYTE2                      *((volatile  uint8_t*)(0x40038719UL))
#define FM_MFS7_CSIO_SCSTR0                       *((volatile  uint8_t*)(0x4003871CUL))
#define FM4_MFS7_CSIO_SCSTR0                      *((volatile  uint8_t*)(0x4003871CUL))
#define FM_MFS7_I2C_NFCR                          *((volatile  uint8_t*)(0x4003871CUL))
#define FM4_MFS7_I2C_NFCR                         *((volatile  uint8_t*)(0x4003871CUL))
#define FM_MFS7_CSIO_SCSTR1                       *((volatile  uint8_t*)(0x4003871DUL))
#define FM4_MFS7_CSIO_SCSTR1                      *((volatile  uint8_t*)(0x4003871DUL))
#define FM_MFS7_I2C_EIBCR                         *((volatile  uint8_t*)(0x4003871DUL))
#define FM4_MFS7_I2C_EIBCR                        *((volatile  uint8_t*)(0x4003871DUL))
#define FM_MFS7_CSIO_SCSTR32                      *((volatile uint16_t*)(0x40038720UL))
#define FM4_MFS7_CSIO_SCSTR32                     *((volatile uint16_t*)(0x40038720UL))
#define FM_MFS7_CSIO_SACSR                        *((volatile uint16_t*)(0x40038724UL))
#define FM4_MFS7_CSIO_SACSR                       *((volatile uint16_t*)(0x40038724UL))
#define FM_MFS7_CSIO_STMR                         *((volatile uint16_t*)(0x40038728UL))
#define FM4_MFS7_CSIO_STMR                        *((volatile uint16_t*)(0x40038728UL))
#define FM_MFS7_CSIO_STMCR                        *((volatile uint16_t*)(0x4003872CUL))
#define FM4_MFS7_CSIO_STMCR                       *((volatile uint16_t*)(0x4003872CUL))
#define FM_MFS7_CSIO_SCSCR                        *((volatile uint16_t*)(0x40038730UL))
#define FM4_MFS7_CSIO_SCSCR                       *((volatile uint16_t*)(0x40038730UL))
#define FM_MFS7_CSIO_SCSFR0                       *((volatile  uint8_t*)(0x40038734UL))
#define FM4_MFS7_CSIO_SCSFR0                      *((volatile  uint8_t*)(0x40038734UL))
#define FM_MFS7_CSIO_SCSFR1                       *((volatile  uint8_t*)(0x40038735UL))
#define FM4_MFS7_CSIO_SCSFR1                      *((volatile  uint8_t*)(0x40038735UL))
#define FM_MFS7_CSIO_SCSFR2                       *((volatile  uint8_t*)(0x40038738UL))
#define FM4_MFS7_CSIO_SCSFR2                      *((volatile  uint8_t*)(0x40038738UL))
#define FM_MFS7_CSIO_TBYTE0                       *((volatile  uint8_t*)(0x4003873CUL))
#define FM4_MFS7_CSIO_TBYTE0                      *((volatile  uint8_t*)(0x4003873CUL))
#define FM_MFS7_CSIO_TBYTE1                       *((volatile  uint8_t*)(0x4003873DUL))
#define FM4_MFS7_CSIO_TBYTE1                      *((volatile  uint8_t*)(0x4003873DUL))
#define FM_MFS7_CSIO_TBYTE2                       *((volatile  uint8_t*)(0x40038740UL))
#define FM4_MFS7_CSIO_TBYTE2                      *((volatile  uint8_t*)(0x40038740UL))
#define FM_MFS7_CSIO_TBYTE3                       *((volatile  uint8_t*)(0x40038741UL))
#define FM4_MFS7_CSIO_TBYTE3                      *((volatile  uint8_t*)(0x40038741UL))

/*******************************************************************************
* MFS Registers MFS8
*   Register Definition
*******************************************************************************/
#define FM_MFS8_CSIO_SMR                          *((volatile  uint8_t*)(0x40038800UL))
#define FM4_MFS8_CSIO_SMR                         *((volatile  uint8_t*)(0x40038800UL))
#define FM_MFS8_I2C_SMR                           *((volatile  uint8_t*)(0x40038800UL))
#define FM4_MFS8_I2C_SMR                          *((volatile  uint8_t*)(0x40038800UL))
#define FM_MFS8_LIN_SMR                           *((volatile  uint8_t*)(0x40038800UL))
#define FM4_MFS8_LIN_SMR                          *((volatile  uint8_t*)(0x40038800UL))
#define FM_MFS8_UART_SMR                          *((volatile  uint8_t*)(0x40038800UL))
#define FM4_MFS8_UART_SMR                         *((volatile  uint8_t*)(0x40038800UL))
#define FM_MFS8_CSIO_SCR                          *((volatile  uint8_t*)(0x40038801UL))
#define FM4_MFS8_CSIO_SCR                         *((volatile  uint8_t*)(0x40038801UL))
#define FM_MFS8_I2C_IBCR                          *((volatile  uint8_t*)(0x40038801UL))
#define FM4_MFS8_I2C_IBCR                         *((volatile  uint8_t*)(0x40038801UL))
#define FM_MFS8_LIN_SCR                           *((volatile  uint8_t*)(0x40038801UL))
#define FM4_MFS8_LIN_SCR                          *((volatile  uint8_t*)(0x40038801UL))
#define FM_MFS8_UART_SCR                          *((volatile  uint8_t*)(0x40038801UL))
#define FM4_MFS8_UART_SCR                         *((volatile  uint8_t*)(0x40038801UL))
#define FM_MFS8_CSIO_ESCR                         *((volatile  uint8_t*)(0x40038804UL))
#define FM4_MFS8_CSIO_ESCR                        *((volatile  uint8_t*)(0x40038804UL))
#define FM_MFS8_I2C_IBSR                          *((volatile  uint8_t*)(0x40038804UL))
#define FM4_MFS8_I2C_IBSR                         *((volatile  uint8_t*)(0x40038804UL))
#define FM_MFS8_LIN_ESCR                          *((volatile  uint8_t*)(0x40038804UL))
#define FM4_MFS8_LIN_ESCR                         *((volatile  uint8_t*)(0x40038804UL))
#define FM_MFS8_UART_ESCR                         *((volatile  uint8_t*)(0x40038804UL))
#define FM4_MFS8_UART_ESCR                        *((volatile  uint8_t*)(0x40038804UL))
#define FM_MFS8_CSIO_SSR                          *((volatile  uint8_t*)(0x40038805UL))
#define FM4_MFS8_CSIO_SSR                         *((volatile  uint8_t*)(0x40038805UL))
#define FM_MFS8_I2C_SSR                           *((volatile  uint8_t*)(0x40038805UL))
#define FM4_MFS8_I2C_SSR                          *((volatile  uint8_t*)(0x40038805UL))
#define FM_MFS8_LIN_SSR                           *((volatile  uint8_t*)(0x40038805UL))
#define FM4_MFS8_LIN_SSR                          *((volatile  uint8_t*)(0x40038805UL))
#define FM_MFS8_UART_SSR                          *((volatile  uint8_t*)(0x40038805UL))
#define FM4_MFS8_UART_SSR                         *((volatile  uint8_t*)(0x40038805UL))
#define FM_MFS8_CSIO_RDR                          *((volatile uint16_t*)(0x40038808UL))
#define FM4_MFS8_CSIO_RDR                         *((volatile uint16_t*)(0x40038808UL))
#define FM_MFS8_CSIO_TDR                          *((volatile uint16_t*)(0x40038808UL))
#define FM4_MFS8_CSIO_TDR                         *((volatile uint16_t*)(0x40038808UL))
#define FM_MFS8_I2C_RDR                           *((volatile uint16_t*)(0x40038808UL))
#define FM4_MFS8_I2C_RDR                          *((volatile uint16_t*)(0x40038808UL))
#define FM_MFS8_I2C_TDR                           *((volatile uint16_t*)(0x40038808UL))
#define FM4_MFS8_I2C_TDR                          *((volatile uint16_t*)(0x40038808UL))
#define FM_MFS8_LIN_RDR                           *((volatile uint16_t*)(0x40038808UL))
#define FM4_MFS8_LIN_RDR                          *((volatile uint16_t*)(0x40038808UL))
#define FM_MFS8_LIN_TDR                           *((volatile uint16_t*)(0x40038808UL))
#define FM4_MFS8_LIN_TDR                          *((volatile uint16_t*)(0x40038808UL))
#define FM_MFS8_UART_RDR                          *((volatile uint16_t*)(0x40038808UL))
#define FM4_MFS8_UART_RDR                         *((volatile uint16_t*)(0x40038808UL))
#define FM_MFS8_UART_TDR                          *((volatile uint16_t*)(0x40038808UL))
#define FM4_MFS8_UART_TDR                         *((volatile uint16_t*)(0x40038808UL))
#define FM_MFS8_CSIO_BGR                          *((volatile uint16_t*)(0x4003880CUL))
#define FM4_MFS8_CSIO_BGR                         *((volatile uint16_t*)(0x4003880CUL))
#define FM_MFS8_I2C_BGR                           *((volatile uint16_t*)(0x4003880CUL))
#define FM4_MFS8_I2C_BGR                          *((volatile uint16_t*)(0x4003880CUL))
#define FM_MFS8_LIN_BGR                           *((volatile uint16_t*)(0x4003880CUL))
#define FM4_MFS8_LIN_BGR                          *((volatile uint16_t*)(0x4003880CUL))
#define FM_MFS8_UART_BGR                          *((volatile uint16_t*)(0x4003880CUL))
#define FM4_MFS8_UART_BGR                         *((volatile uint16_t*)(0x4003880CUL))
#define FM_MFS8_I2C_ISBA                          *((volatile  uint8_t*)(0x40038810UL))
#define FM4_MFS8_I2C_ISBA                         *((volatile  uint8_t*)(0x40038810UL))
#define FM_MFS8_I2C_ISMK                          *((volatile  uint8_t*)(0x40038811UL))
#define FM4_MFS8_I2C_ISMK                         *((volatile  uint8_t*)(0x40038811UL))
#define FM_MFS8_CSIO_FCR                          *((volatile uint16_t*)(0x40038814UL))
#define FM4_MFS8_CSIO_FCR                         *((volatile uint16_t*)(0x40038814UL))
#define FM_MFS8_I2C_FCR                           *((volatile uint16_t*)(0x40038814UL))
#define FM4_MFS8_I2C_FCR                          *((volatile uint16_t*)(0x40038814UL))
#define FM_MFS8_LIN_FCR                           *((volatile uint16_t*)(0x40038814UL))
#define FM4_MFS8_LIN_FCR                          *((volatile uint16_t*)(0x40038814UL))
#define FM_MFS8_UART_FCR                          *((volatile uint16_t*)(0x40038814UL))
#define FM4_MFS8_UART_FCR                         *((volatile uint16_t*)(0x40038814UL))
#define FM_MFS8_CSIO_FBYTE1                       *((volatile  uint8_t*)(0x40038818UL))
#define FM4_MFS8_CSIO_FBYTE1                      *((volatile  uint8_t*)(0x40038818UL))
#define FM_MFS8_I2C_FBYTE1                        *((volatile  uint8_t*)(0x40038818UL))
#define FM4_MFS8_I2C_FBYTE1                       *((volatile  uint8_t*)(0x40038818UL))
#define FM_MFS8_LIN_FBYTE1                        *((volatile  uint8_t*)(0x40038818UL))
#define FM4_MFS8_LIN_FBYTE1                       *((volatile  uint8_t*)(0x40038818UL))
#define FM_MFS8_UART_FBYTE1                       *((volatile  uint8_t*)(0x40038818UL))
#define FM4_MFS8_UART_FBYTE1                      *((volatile  uint8_t*)(0x40038818UL))
#define FM_MFS8_CSIO_FBYTE2                       *((volatile  uint8_t*)(0x40038819UL))
#define FM4_MFS8_CSIO_FBYTE2                      *((volatile  uint8_t*)(0x40038819UL))
#define FM_MFS8_I2C_FBYTE2                        *((volatile  uint8_t*)(0x40038819UL))
#define FM4_MFS8_I2C_FBYTE2                       *((volatile  uint8_t*)(0x40038819UL))
#define FM_MFS8_LIN_FBYTE2                        *((volatile  uint8_t*)(0x40038819UL))
#define FM4_MFS8_LIN_FBYTE2                       *((volatile  uint8_t*)(0x40038819UL))
#define FM_MFS8_UART_FBYTE2                       *((volatile  uint8_t*)(0x40038819UL))
#define FM4_MFS8_UART_FBYTE2                      *((volatile  uint8_t*)(0x40038819UL))
#define FM_MFS8_CSIO_SCSTR0                       *((volatile  uint8_t*)(0x4003881CUL))
#define FM4_MFS8_CSIO_SCSTR0                      *((volatile  uint8_t*)(0x4003881CUL))
#define FM_MFS8_I2C_NFCR                          *((volatile  uint8_t*)(0x4003881CUL))
#define FM4_MFS8_I2C_NFCR                         *((volatile  uint8_t*)(0x4003881CUL))
#define FM_MFS8_CSIO_SCSTR1                       *((volatile  uint8_t*)(0x4003881DUL))
#define FM4_MFS8_CSIO_SCSTR1                      *((volatile  uint8_t*)(0x4003881DUL))
#define FM_MFS8_I2C_EIBCR                         *((volatile  uint8_t*)(0x4003881DUL))
#define FM4_MFS8_I2C_EIBCR                        *((volatile  uint8_t*)(0x4003881DUL))
#define FM_MFS8_CSIO_SCSTR32                      *((volatile uint16_t*)(0x40038820UL))
#define FM4_MFS8_CSIO_SCSTR32                     *((volatile uint16_t*)(0x40038820UL))
#define FM_MFS8_CSIO_SACSR                        *((volatile uint16_t*)(0x40038824UL))
#define FM4_MFS8_CSIO_SACSR                       *((volatile uint16_t*)(0x40038824UL))
#define FM_MFS8_CSIO_STMR                         *((volatile uint16_t*)(0x40038828UL))
#define FM4_MFS8_CSIO_STMR                        *((volatile uint16_t*)(0x40038828UL))
#define FM_MFS8_CSIO_STMCR                        *((volatile uint16_t*)(0x4003882CUL))
#define FM4_MFS8_CSIO_STMCR                       *((volatile uint16_t*)(0x4003882CUL))
#define FM_MFS8_CSIO_SCSCR                        *((volatile uint16_t*)(0x40038830UL))
#define FM4_MFS8_CSIO_SCSCR                       *((volatile uint16_t*)(0x40038830UL))
#define FM_MFS8_CSIO_SCSFR0                       *((volatile  uint8_t*)(0x40038834UL))
#define FM4_MFS8_CSIO_SCSFR0                      *((volatile  uint8_t*)(0x40038834UL))
#define FM_MFS8_CSIO_SCSFR1                       *((volatile  uint8_t*)(0x40038835UL))
#define FM4_MFS8_CSIO_SCSFR1                      *((volatile  uint8_t*)(0x40038835UL))
#define FM_MFS8_CSIO_SCSFR2                       *((volatile  uint8_t*)(0x40038838UL))
#define FM4_MFS8_CSIO_SCSFR2                      *((volatile  uint8_t*)(0x40038838UL))
#define FM_MFS8_CSIO_TBYTE0                       *((volatile  uint8_t*)(0x4003883CUL))
#define FM4_MFS8_CSIO_TBYTE0                      *((volatile  uint8_t*)(0x4003883CUL))
#define FM_MFS8_CSIO_TBYTE1                       *((volatile  uint8_t*)(0x4003883DUL))
#define FM4_MFS8_CSIO_TBYTE1                      *((volatile  uint8_t*)(0x4003883DUL))
#define FM_MFS8_CSIO_TBYTE2                       *((volatile  uint8_t*)(0x40038840UL))
#define FM4_MFS8_CSIO_TBYTE2                      *((volatile  uint8_t*)(0x40038840UL))
#define FM_MFS8_CSIO_TBYTE3                       *((volatile  uint8_t*)(0x40038841UL))
#define FM4_MFS8_CSIO_TBYTE3                      *((volatile  uint8_t*)(0x40038841UL))

/*******************************************************************************
* MFS Registers MFS9
*   Register Definition
*******************************************************************************/
#define FM_MFS9_CSIO_SMR                          *((volatile  uint8_t*)(0x40038900UL))
#define FM4_MFS9_CSIO_SMR                         *((volatile  uint8_t*)(0x40038900UL))
#define FM_MFS9_I2C_SMR                           *((volatile  uint8_t*)(0x40038900UL))
#define FM4_MFS9_I2C_SMR                          *((volatile  uint8_t*)(0x40038900UL))
#define FM_MFS9_LIN_SMR                           *((volatile  uint8_t*)(0x40038900UL))
#define FM4_MFS9_LIN_SMR                          *((volatile  uint8_t*)(0x40038900UL))
#define FM_MFS9_UART_SMR                          *((volatile  uint8_t*)(0x40038900UL))
#define FM4_MFS9_UART_SMR                         *((volatile  uint8_t*)(0x40038900UL))
#define FM_MFS9_CSIO_SCR                          *((volatile  uint8_t*)(0x40038901UL))
#define FM4_MFS9_CSIO_SCR                         *((volatile  uint8_t*)(0x40038901UL))
#define FM_MFS9_I2C_IBCR                          *((volatile  uint8_t*)(0x40038901UL))
#define FM4_MFS9_I2C_IBCR                         *((volatile  uint8_t*)(0x40038901UL))
#define FM_MFS9_LIN_SCR                           *((volatile  uint8_t*)(0x40038901UL))
#define FM4_MFS9_LIN_SCR                          *((volatile  uint8_t*)(0x40038901UL))
#define FM_MFS9_UART_SCR                          *((volatile  uint8_t*)(0x40038901UL))
#define FM4_MFS9_UART_SCR                         *((volatile  uint8_t*)(0x40038901UL))
#define FM_MFS9_CSIO_ESCR                         *((volatile  uint8_t*)(0x40038904UL))
#define FM4_MFS9_CSIO_ESCR                        *((volatile  uint8_t*)(0x40038904UL))
#define FM_MFS9_I2C_IBSR                          *((volatile  uint8_t*)(0x40038904UL))
#define FM4_MFS9_I2C_IBSR                         *((volatile  uint8_t*)(0x40038904UL))
#define FM_MFS9_LIN_ESCR                          *((volatile  uint8_t*)(0x40038904UL))
#define FM4_MFS9_LIN_ESCR                         *((volatile  uint8_t*)(0x40038904UL))
#define FM_MFS9_UART_ESCR                         *((volatile  uint8_t*)(0x40038904UL))
#define FM4_MFS9_UART_ESCR                        *((volatile  uint8_t*)(0x40038904UL))
#define FM_MFS9_CSIO_SSR                          *((volatile  uint8_t*)(0x40038905UL))
#define FM4_MFS9_CSIO_SSR                         *((volatile  uint8_t*)(0x40038905UL))
#define FM_MFS9_I2C_SSR                           *((volatile  uint8_t*)(0x40038905UL))
#define FM4_MFS9_I2C_SSR                          *((volatile  uint8_t*)(0x40038905UL))
#define FM_MFS9_LIN_SSR                           *((volatile  uint8_t*)(0x40038905UL))
#define FM4_MFS9_LIN_SSR                          *((volatile  uint8_t*)(0x40038905UL))
#define FM_MFS9_UART_SSR                          *((volatile  uint8_t*)(0x40038905UL))
#define FM4_MFS9_UART_SSR                         *((volatile  uint8_t*)(0x40038905UL))
#define FM_MFS9_CSIO_RDR                          *((volatile uint16_t*)(0x40038908UL))
#define FM4_MFS9_CSIO_RDR                         *((volatile uint16_t*)(0x40038908UL))
#define FM_MFS9_CSIO_TDR                          *((volatile uint16_t*)(0x40038908UL))
#define FM4_MFS9_CSIO_TDR                         *((volatile uint16_t*)(0x40038908UL))
#define FM_MFS9_I2C_RDR                           *((volatile uint16_t*)(0x40038908UL))
#define FM4_MFS9_I2C_RDR                          *((volatile uint16_t*)(0x40038908UL))
#define FM_MFS9_I2C_TDR                           *((volatile uint16_t*)(0x40038908UL))
#define FM4_MFS9_I2C_TDR                          *((volatile uint16_t*)(0x40038908UL))
#define FM_MFS9_LIN_RDR                           *((volatile uint16_t*)(0x40038908UL))
#define FM4_MFS9_LIN_RDR                          *((volatile uint16_t*)(0x40038908UL))
#define FM_MFS9_LIN_TDR                           *((volatile uint16_t*)(0x40038908UL))
#define FM4_MFS9_LIN_TDR                          *((volatile uint16_t*)(0x40038908UL))
#define FM_MFS9_UART_RDR                          *((volatile uint16_t*)(0x40038908UL))
#define FM4_MFS9_UART_RDR                         *((volatile uint16_t*)(0x40038908UL))
#define FM_MFS9_UART_TDR                          *((volatile uint16_t*)(0x40038908UL))
#define FM4_MFS9_UART_TDR                         *((volatile uint16_t*)(0x40038908UL))
#define FM_MFS9_CSIO_BGR                          *((volatile uint16_t*)(0x4003890CUL))
#define FM4_MFS9_CSIO_BGR                         *((volatile uint16_t*)(0x4003890CUL))
#define FM_MFS9_I2C_BGR                           *((volatile uint16_t*)(0x4003890CUL))
#define FM4_MFS9_I2C_BGR                          *((volatile uint16_t*)(0x4003890CUL))
#define FM_MFS9_LIN_BGR                           *((volatile uint16_t*)(0x4003890CUL))
#define FM4_MFS9_LIN_BGR                          *((volatile uint16_t*)(0x4003890CUL))
#define FM_MFS9_UART_BGR                          *((volatile uint16_t*)(0x4003890CUL))
#define FM4_MFS9_UART_BGR                         *((volatile uint16_t*)(0x4003890CUL))
#define FM_MFS9_I2C_ISBA                          *((volatile  uint8_t*)(0x40038910UL))
#define FM4_MFS9_I2C_ISBA                         *((volatile  uint8_t*)(0x40038910UL))
#define FM_MFS9_I2C_ISMK                          *((volatile  uint8_t*)(0x40038911UL))
#define FM4_MFS9_I2C_ISMK                         *((volatile  uint8_t*)(0x40038911UL))
#define FM_MFS9_CSIO_FCR                          *((volatile uint16_t*)(0x40038914UL))
#define FM4_MFS9_CSIO_FCR                         *((volatile uint16_t*)(0x40038914UL))
#define FM_MFS9_I2C_FCR                           *((volatile uint16_t*)(0x40038914UL))
#define FM4_MFS9_I2C_FCR                          *((volatile uint16_t*)(0x40038914UL))
#define FM_MFS9_LIN_FCR                           *((volatile uint16_t*)(0x40038914UL))
#define FM4_MFS9_LIN_FCR                          *((volatile uint16_t*)(0x40038914UL))
#define FM_MFS9_UART_FCR                          *((volatile uint16_t*)(0x40038914UL))
#define FM4_MFS9_UART_FCR                         *((volatile uint16_t*)(0x40038914UL))
#define FM_MFS9_CSIO_FBYTE1                       *((volatile  uint8_t*)(0x40038918UL))
#define FM4_MFS9_CSIO_FBYTE1                      *((volatile  uint8_t*)(0x40038918UL))
#define FM_MFS9_I2C_FBYTE1                        *((volatile  uint8_t*)(0x40038918UL))
#define FM4_MFS9_I2C_FBYTE1                       *((volatile  uint8_t*)(0x40038918UL))
#define FM_MFS9_LIN_FBYTE1                        *((volatile  uint8_t*)(0x40038918UL))
#define FM4_MFS9_LIN_FBYTE1                       *((volatile  uint8_t*)(0x40038918UL))
#define FM_MFS9_UART_FBYTE1                       *((volatile  uint8_t*)(0x40038918UL))
#define FM4_MFS9_UART_FBYTE1                      *((volatile  uint8_t*)(0x40038918UL))
#define FM_MFS9_CSIO_FBYTE2                       *((volatile  uint8_t*)(0x40038919UL))
#define FM4_MFS9_CSIO_FBYTE2                      *((volatile  uint8_t*)(0x40038919UL))
#define FM_MFS9_I2C_FBYTE2                        *((volatile  uint8_t*)(0x40038919UL))
#define FM4_MFS9_I2C_FBYTE2                       *((volatile  uint8_t*)(0x40038919UL))
#define FM_MFS9_LIN_FBYTE2                        *((volatile  uint8_t*)(0x40038919UL))
#define FM4_MFS9_LIN_FBYTE2                       *((volatile  uint8_t*)(0x40038919UL))
#define FM_MFS9_UART_FBYTE2                       *((volatile  uint8_t*)(0x40038919UL))
#define FM4_MFS9_UART_FBYTE2                      *((volatile  uint8_t*)(0x40038919UL))
#define FM_MFS9_CSIO_SCSTR0                       *((volatile  uint8_t*)(0x4003891CUL))
#define FM4_MFS9_CSIO_SCSTR0                      *((volatile  uint8_t*)(0x4003891CUL))
#define FM_MFS9_I2C_NFCR                          *((volatile  uint8_t*)(0x4003891CUL))
#define FM4_MFS9_I2C_NFCR                         *((volatile  uint8_t*)(0x4003891CUL))
#define FM_MFS9_CSIO_SCSTR1                       *((volatile  uint8_t*)(0x4003891DUL))
#define FM4_MFS9_CSIO_SCSTR1                      *((volatile  uint8_t*)(0x4003891DUL))
#define FM_MFS9_I2C_EIBCR                         *((volatile  uint8_t*)(0x4003891DUL))
#define FM4_MFS9_I2C_EIBCR                        *((volatile  uint8_t*)(0x4003891DUL))
#define FM_MFS9_CSIO_SCSTR32                      *((volatile uint16_t*)(0x40038920UL))
#define FM4_MFS9_CSIO_SCSTR32                     *((volatile uint16_t*)(0x40038920UL))
#define FM_MFS9_CSIO_SACSR                        *((volatile uint16_t*)(0x40038924UL))
#define FM4_MFS9_CSIO_SACSR                       *((volatile uint16_t*)(0x40038924UL))
#define FM_MFS9_CSIO_STMR                         *((volatile uint16_t*)(0x40038928UL))
#define FM4_MFS9_CSIO_STMR                        *((volatile uint16_t*)(0x40038928UL))
#define FM_MFS9_CSIO_STMCR                        *((volatile uint16_t*)(0x4003892CUL))
#define FM4_MFS9_CSIO_STMCR                       *((volatile uint16_t*)(0x4003892CUL))
#define FM_MFS9_CSIO_SCSCR                        *((volatile uint16_t*)(0x40038930UL))
#define FM4_MFS9_CSIO_SCSCR                       *((volatile uint16_t*)(0x40038930UL))
#define FM_MFS9_CSIO_SCSFR0                       *((volatile  uint8_t*)(0x40038934UL))
#define FM4_MFS9_CSIO_SCSFR0                      *((volatile  uint8_t*)(0x40038934UL))
#define FM_MFS9_CSIO_SCSFR1                       *((volatile  uint8_t*)(0x40038935UL))
#define FM4_MFS9_CSIO_SCSFR1                      *((volatile  uint8_t*)(0x40038935UL))
#define FM_MFS9_CSIO_SCSFR2                       *((volatile  uint8_t*)(0x40038938UL))
#define FM4_MFS9_CSIO_SCSFR2                      *((volatile  uint8_t*)(0x40038938UL))
#define FM_MFS9_CSIO_TBYTE0                       *((volatile  uint8_t*)(0x4003893CUL))
#define FM4_MFS9_CSIO_TBYTE0                      *((volatile  uint8_t*)(0x4003893CUL))
#define FM_MFS9_CSIO_TBYTE1                       *((volatile  uint8_t*)(0x4003893DUL))
#define FM4_MFS9_CSIO_TBYTE1                      *((volatile  uint8_t*)(0x4003893DUL))
#define FM_MFS9_CSIO_TBYTE2                       *((volatile  uint8_t*)(0x40038940UL))
#define FM4_MFS9_CSIO_TBYTE2                      *((volatile  uint8_t*)(0x40038940UL))
#define FM_MFS9_CSIO_TBYTE3                       *((volatile  uint8_t*)(0x40038941UL))
#define FM4_MFS9_CSIO_TBYTE3                      *((volatile  uint8_t*)(0x40038941UL))

/*******************************************************************************
* MFT_PPG Registers MFT_PPG
*   Register Definition
*******************************************************************************/
#define FM_MFT_PPG_TTCR0                          *((volatile  uint8_t*)(0x40024001UL))
#define FM4_MFT_PPG_TTCR0                         *((volatile  uint8_t*)(0x40024001UL))
#define FM_MFT_PPG_COMP0                          *((volatile  uint8_t*)(0x40024009UL))
#define FM4_MFT_PPG_COMP0                         *((volatile  uint8_t*)(0x40024009UL))
#define FM_MFT_PPG_COMP2                          *((volatile  uint8_t*)(0x4002400CUL))
#define FM4_MFT_PPG_COMP2                         *((volatile  uint8_t*)(0x4002400CUL))
#define FM_MFT_PPG_COMP4                          *((volatile  uint8_t*)(0x40024011UL))
#define FM4_MFT_PPG_COMP4                         *((volatile  uint8_t*)(0x40024011UL))
#define FM_MFT_PPG_COMP6                          *((volatile  uint8_t*)(0x40024014UL))
#define FM4_MFT_PPG_COMP6                         *((volatile  uint8_t*)(0x40024014UL))
#define FM_MFT_PPG_TTCR1                          *((volatile  uint8_t*)(0x40024021UL))
#define FM4_MFT_PPG_TTCR1                         *((volatile  uint8_t*)(0x40024021UL))
#define FM_MFT_PPG_COMP1                          *((volatile  uint8_t*)(0x40024029UL))
#define FM4_MFT_PPG_COMP1                         *((volatile  uint8_t*)(0x40024029UL))
#define FM_MFT_PPG_COMP3                          *((volatile  uint8_t*)(0x4002402CUL))
#define FM4_MFT_PPG_COMP3                         *((volatile  uint8_t*)(0x4002402CUL))
#define FM_MFT_PPG_COMP5                          *((volatile  uint8_t*)(0x40024031UL))
#define FM4_MFT_PPG_COMP5                         *((volatile  uint8_t*)(0x40024031UL))
#define FM_MFT_PPG_COMP7                          *((volatile  uint8_t*)(0x40024034UL))
#define FM4_MFT_PPG_COMP7                         *((volatile  uint8_t*)(0x40024034UL))
#define FM_MFT_PPG_TTCR2                          *((volatile  uint8_t*)(0x40024041UL))
#define FM4_MFT_PPG_TTCR2                         *((volatile  uint8_t*)(0x40024041UL))
#define FM_MFT_PPG_COMP8                          *((volatile  uint8_t*)(0x40024049UL))
#define FM4_MFT_PPG_COMP8                         *((volatile  uint8_t*)(0x40024049UL))
#define FM_MFT_PPG_COMP10                         *((volatile  uint8_t*)(0x4002404CUL))
#define FM4_MFT_PPG_COMP10                        *((volatile  uint8_t*)(0x4002404CUL))
#define FM_MFT_PPG_COMP12                         *((volatile  uint8_t*)(0x40024051UL))
#define FM4_MFT_PPG_COMP12                        *((volatile  uint8_t*)(0x40024051UL))
#define FM_MFT_PPG_COMP14                         *((volatile  uint8_t*)(0x40024054UL))
#define FM4_MFT_PPG_COMP14                        *((volatile  uint8_t*)(0x40024054UL))
#define FM_MFT_PPG_TRG0                           *((volatile uint16_t*)(0x40024100UL))
#define FM4_MFT_PPG_TRG0                          *((volatile uint16_t*)(0x40024100UL))
#define FM_MFT_PPG_REVC0                          *((volatile uint16_t*)(0x40024104UL))
#define FM4_MFT_PPG_REVC0                         *((volatile uint16_t*)(0x40024104UL))
#define FM_MFT_PPG_TRG1                           *((volatile uint16_t*)(0x40024140UL))
#define FM4_MFT_PPG_TRG1                          *((volatile uint16_t*)(0x40024140UL))
#define FM_MFT_PPG_REVC1                          *((volatile uint16_t*)(0x40024144UL))
#define FM4_MFT_PPG_REVC1                         *((volatile uint16_t*)(0x40024144UL))
#define FM_MFT_PPG_PPGC1                          *((volatile  uint8_t*)(0x40024200UL))
#define FM4_MFT_PPG_PPGC1                         *((volatile  uint8_t*)(0x40024200UL))
#define FM_MFT_PPG_PPGC0                          *((volatile  uint8_t*)(0x40024201UL))
#define FM4_MFT_PPG_PPGC0                         *((volatile  uint8_t*)(0x40024201UL))
#define FM_MFT_PPG_PPGC3                          *((volatile  uint8_t*)(0x40024204UL))
#define FM4_MFT_PPG_PPGC3                         *((volatile  uint8_t*)(0x40024204UL))
#define FM_MFT_PPG_PPGC2                          *((volatile  uint8_t*)(0x40024205UL))
#define FM4_MFT_PPG_PPGC2                         *((volatile  uint8_t*)(0x40024205UL))
#define FM_MFT_PPG_PRLL0                          *((volatile  uint8_t*)(0x40024208UL))
#define FM4_MFT_PPG_PRLL0                         *((volatile  uint8_t*)(0x40024208UL))
#define FM_MFT_PPG_PRLH0                          *((volatile  uint8_t*)(0x40024209UL))
#define FM4_MFT_PPG_PRLH0                         *((volatile  uint8_t*)(0x40024209UL))
#define FM_MFT_PPG_PRLL1                          *((volatile  uint8_t*)(0x4002420CUL))
#define FM4_MFT_PPG_PRLL1                         *((volatile  uint8_t*)(0x4002420CUL))
#define FM_MFT_PPG_PRLH1                          *((volatile  uint8_t*)(0x4002420DUL))
#define FM4_MFT_PPG_PRLH1                         *((volatile  uint8_t*)(0x4002420DUL))
#define FM_MFT_PPG_PRLL2                          *((volatile  uint8_t*)(0x40024210UL))
#define FM4_MFT_PPG_PRLL2                         *((volatile  uint8_t*)(0x40024210UL))
#define FM_MFT_PPG_PRLH2                          *((volatile  uint8_t*)(0x40024211UL))
#define FM4_MFT_PPG_PRLH2                         *((volatile  uint8_t*)(0x40024211UL))
#define FM_MFT_PPG_PRLL3                          *((volatile  uint8_t*)(0x40024214UL))
#define FM4_MFT_PPG_PRLL3                         *((volatile  uint8_t*)(0x40024214UL))
#define FM_MFT_PPG_PRLH3                          *((volatile  uint8_t*)(0x40024215UL))
#define FM4_MFT_PPG_PRLH3                         *((volatile  uint8_t*)(0x40024215UL))
#define FM_MFT_PPG_GATEC0                         *((volatile  uint8_t*)(0x40024218UL))
#define FM4_MFT_PPG_GATEC0                        *((volatile  uint8_t*)(0x40024218UL))
#define FM_MFT_PPG_PPGC5                          *((volatile  uint8_t*)(0x40024240UL))
#define FM4_MFT_PPG_PPGC5                         *((volatile  uint8_t*)(0x40024240UL))
#define FM_MFT_PPG_PPGC4                          *((volatile  uint8_t*)(0x40024241UL))
#define FM4_MFT_PPG_PPGC4                         *((volatile  uint8_t*)(0x40024241UL))
#define FM_MFT_PPG_PPGC7                          *((volatile  uint8_t*)(0x40024244UL))
#define FM4_MFT_PPG_PPGC7                         *((volatile  uint8_t*)(0x40024244UL))
#define FM_MFT_PPG_PPGC6                          *((volatile  uint8_t*)(0x40024245UL))
#define FM4_MFT_PPG_PPGC6                         *((volatile  uint8_t*)(0x40024245UL))
#define FM_MFT_PPG_PRLL4                          *((volatile  uint8_t*)(0x40024248UL))
#define FM4_MFT_PPG_PRLL4                         *((volatile  uint8_t*)(0x40024248UL))
#define FM_MFT_PPG_PRLH4                          *((volatile  uint8_t*)(0x40024249UL))
#define FM4_MFT_PPG_PRLH4                         *((volatile  uint8_t*)(0x40024249UL))
#define FM_MFT_PPG_PRLL5                          *((volatile  uint8_t*)(0x4002424CUL))
#define FM4_MFT_PPG_PRLL5                         *((volatile  uint8_t*)(0x4002424CUL))
#define FM_MFT_PPG_PRLH5                          *((volatile  uint8_t*)(0x4002424DUL))
#define FM4_MFT_PPG_PRLH5                         *((volatile  uint8_t*)(0x4002424DUL))
#define FM_MFT_PPG_PRLL6                          *((volatile  uint8_t*)(0x40024250UL))
#define FM4_MFT_PPG_PRLL6                         *((volatile  uint8_t*)(0x40024250UL))
#define FM_MFT_PPG_PRLH6                          *((volatile  uint8_t*)(0x40024251UL))
#define FM4_MFT_PPG_PRLH6                         *((volatile  uint8_t*)(0x40024251UL))
#define FM_MFT_PPG_PRLL7                          *((volatile  uint8_t*)(0x40024254UL))
#define FM4_MFT_PPG_PRLL7                         *((volatile  uint8_t*)(0x40024254UL))
#define FM_MFT_PPG_PRLH7                          *((volatile  uint8_t*)(0x40024255UL))
#define FM4_MFT_PPG_PRLH7                         *((volatile  uint8_t*)(0x40024255UL))
#define FM_MFT_PPG_GATEC4                         *((volatile  uint8_t*)(0x40024258UL))
#define FM4_MFT_PPG_GATEC4                        *((volatile  uint8_t*)(0x40024258UL))
#define FM_MFT_PPG_PPGC9                          *((volatile  uint8_t*)(0x40024280UL))
#define FM4_MFT_PPG_PPGC9                         *((volatile  uint8_t*)(0x40024280UL))
#define FM_MFT_PPG_PPGC8                          *((volatile  uint8_t*)(0x40024281UL))
#define FM4_MFT_PPG_PPGC8                         *((volatile  uint8_t*)(0x40024281UL))
#define FM_MFT_PPG_PPGC11                         *((volatile  uint8_t*)(0x40024284UL))
#define FM4_MFT_PPG_PPGC11                        *((volatile  uint8_t*)(0x40024284UL))
#define FM_MFT_PPG_PPGC10                         *((volatile  uint8_t*)(0x40024285UL))
#define FM4_MFT_PPG_PPGC10                        *((volatile  uint8_t*)(0x40024285UL))
#define FM_MFT_PPG_PRLL8                          *((volatile  uint8_t*)(0x40024288UL))
#define FM4_MFT_PPG_PRLL8                         *((volatile  uint8_t*)(0x40024288UL))
#define FM_MFT_PPG_PRLH8                          *((volatile  uint8_t*)(0x40024289UL))
#define FM4_MFT_PPG_PRLH8                         *((volatile  uint8_t*)(0x40024289UL))
#define FM_MFT_PPG_PRLL9                          *((volatile  uint8_t*)(0x4002428CUL))
#define FM4_MFT_PPG_PRLL9                         *((volatile  uint8_t*)(0x4002428CUL))
#define FM_MFT_PPG_PRLH9                          *((volatile  uint8_t*)(0x4002428DUL))
#define FM4_MFT_PPG_PRLH9                         *((volatile  uint8_t*)(0x4002428DUL))
#define FM_MFT_PPG_PRLL10                         *((volatile  uint8_t*)(0x40024290UL))
#define FM4_MFT_PPG_PRLL10                        *((volatile  uint8_t*)(0x40024290UL))
#define FM_MFT_PPG_PRLH10                         *((volatile  uint8_t*)(0x40024291UL))
#define FM4_MFT_PPG_PRLH10                        *((volatile  uint8_t*)(0x40024291UL))
#define FM_MFT_PPG_PRLL11                         *((volatile  uint8_t*)(0x40024294UL))
#define FM4_MFT_PPG_PRLL11                        *((volatile  uint8_t*)(0x40024294UL))
#define FM_MFT_PPG_PRLH11                         *((volatile  uint8_t*)(0x40024295UL))
#define FM4_MFT_PPG_PRLH11                        *((volatile  uint8_t*)(0x40024295UL))
#define FM_MFT_PPG_GATEC8                         *((volatile  uint8_t*)(0x40024298UL))
#define FM4_MFT_PPG_GATEC8                        *((volatile  uint8_t*)(0x40024298UL))
#define FM_MFT_PPG_PPGC13                         *((volatile  uint8_t*)(0x400242C0UL))
#define FM4_MFT_PPG_PPGC13                        *((volatile  uint8_t*)(0x400242C0UL))
#define FM_MFT_PPG_PPGC12                         *((volatile  uint8_t*)(0x400242C1UL))
#define FM4_MFT_PPG_PPGC12                        *((volatile  uint8_t*)(0x400242C1UL))
#define FM_MFT_PPG_PPGC15                         *((volatile  uint8_t*)(0x400242C4UL))
#define FM4_MFT_PPG_PPGC15                        *((volatile  uint8_t*)(0x400242C4UL))
#define FM_MFT_PPG_PPGC14                         *((volatile  uint8_t*)(0x400242C5UL))
#define FM4_MFT_PPG_PPGC14                        *((volatile  uint8_t*)(0x400242C5UL))
#define FM_MFT_PPG_PRLL12                         *((volatile  uint8_t*)(0x400242C8UL))
#define FM4_MFT_PPG_PRLL12                        *((volatile  uint8_t*)(0x400242C8UL))
#define FM_MFT_PPG_PRLH12                         *((volatile  uint8_t*)(0x400242C9UL))
#define FM4_MFT_PPG_PRLH12                        *((volatile  uint8_t*)(0x400242C9UL))
#define FM_MFT_PPG_PRLL13                         *((volatile  uint8_t*)(0x400242CCUL))
#define FM4_MFT_PPG_PRLL13                        *((volatile  uint8_t*)(0x400242CCUL))
#define FM_MFT_PPG_PRLH13                         *((volatile  uint8_t*)(0x400242CDUL))
#define FM4_MFT_PPG_PRLH13                        *((volatile  uint8_t*)(0x400242CDUL))
#define FM_MFT_PPG_PRLL14                         *((volatile  uint8_t*)(0x400242D0UL))
#define FM4_MFT_PPG_PRLL14                        *((volatile  uint8_t*)(0x400242D0UL))
#define FM_MFT_PPG_PRLH14                         *((volatile  uint8_t*)(0x400242D1UL))
#define FM4_MFT_PPG_PRLH14                        *((volatile  uint8_t*)(0x400242D1UL))
#define FM_MFT_PPG_PRLL15                         *((volatile  uint8_t*)(0x400242D4UL))
#define FM4_MFT_PPG_PRLL15                        *((volatile  uint8_t*)(0x400242D4UL))
#define FM_MFT_PPG_PRLH15                         *((volatile  uint8_t*)(0x400242D5UL))
#define FM4_MFT_PPG_PRLH15                        *((volatile  uint8_t*)(0x400242D5UL))
#define FM_MFT_PPG_GATEC12                        *((volatile  uint8_t*)(0x400242D8UL))
#define FM4_MFT_PPG_GATEC12                       *((volatile  uint8_t*)(0x400242D8UL))
#define FM_MFT_PPG_PPGC17                         *((volatile  uint8_t*)(0x40024300UL))
#define FM4_MFT_PPG_PPGC17                        *((volatile  uint8_t*)(0x40024300UL))
#define FM_MFT_PPG_PPGC16                         *((volatile  uint8_t*)(0x40024301UL))
#define FM4_MFT_PPG_PPGC16                        *((volatile  uint8_t*)(0x40024301UL))
#define FM_MFT_PPG_PPGC19                         *((volatile  uint8_t*)(0x40024304UL))
#define FM4_MFT_PPG_PPGC19                        *((volatile  uint8_t*)(0x40024304UL))
#define FM_MFT_PPG_PPGC18                         *((volatile  uint8_t*)(0x40024305UL))
#define FM4_MFT_PPG_PPGC18                        *((volatile  uint8_t*)(0x40024305UL))
#define FM_MFT_PPG_PRLL16                         *((volatile  uint8_t*)(0x40024308UL))
#define FM4_MFT_PPG_PRLL16                        *((volatile  uint8_t*)(0x40024308UL))
#define FM_MFT_PPG_PRLH16                         *((volatile  uint8_t*)(0x40024309UL))
#define FM4_MFT_PPG_PRLH16                        *((volatile  uint8_t*)(0x40024309UL))
#define FM_MFT_PPG_PRLL17                         *((volatile  uint8_t*)(0x4002430CUL))
#define FM4_MFT_PPG_PRLL17                        *((volatile  uint8_t*)(0x4002430CUL))
#define FM_MFT_PPG_PRLH17                         *((volatile  uint8_t*)(0x4002430DUL))
#define FM4_MFT_PPG_PRLH17                        *((volatile  uint8_t*)(0x4002430DUL))
#define FM_MFT_PPG_PRLL18                         *((volatile  uint8_t*)(0x40024310UL))
#define FM4_MFT_PPG_PRLL18                        *((volatile  uint8_t*)(0x40024310UL))
#define FM_MFT_PPG_PRLH18                         *((volatile  uint8_t*)(0x40024311UL))
#define FM4_MFT_PPG_PRLH18                        *((volatile  uint8_t*)(0x40024311UL))
#define FM_MFT_PPG_PRLL19                         *((volatile  uint8_t*)(0x40024314UL))
#define FM4_MFT_PPG_PRLL19                        *((volatile  uint8_t*)(0x40024314UL))
#define FM_MFT_PPG_PRLH19                         *((volatile  uint8_t*)(0x40024315UL))
#define FM4_MFT_PPG_PRLH19                        *((volatile  uint8_t*)(0x40024315UL))
#define FM_MFT_PPG_GATEC16                        *((volatile  uint8_t*)(0x40024318UL))
#define FM4_MFT_PPG_GATEC16                       *((volatile  uint8_t*)(0x40024318UL))
#define FM_MFT_PPG_PPGC21                         *((volatile  uint8_t*)(0x40024340UL))
#define FM4_MFT_PPG_PPGC21                        *((volatile  uint8_t*)(0x40024340UL))
#define FM_MFT_PPG_PPGC20                         *((volatile  uint8_t*)(0x40024341UL))
#define FM4_MFT_PPG_PPGC20                        *((volatile  uint8_t*)(0x40024341UL))
#define FM_MFT_PPG_PPGC23                         *((volatile  uint8_t*)(0x40024344UL))
#define FM4_MFT_PPG_PPGC23                        *((volatile  uint8_t*)(0x40024344UL))
#define FM_MFT_PPG_PPGC22                         *((volatile  uint8_t*)(0x40024345UL))
#define FM4_MFT_PPG_PPGC22                        *((volatile  uint8_t*)(0x40024345UL))
#define FM_MFT_PPG_PRLL20                         *((volatile  uint8_t*)(0x40024348UL))
#define FM4_MFT_PPG_PRLL20                        *((volatile  uint8_t*)(0x40024348UL))
#define FM_MFT_PPG_PRLH20                         *((volatile  uint8_t*)(0x40024349UL))
#define FM4_MFT_PPG_PRLH20                        *((volatile  uint8_t*)(0x40024349UL))
#define FM_MFT_PPG_PRLL21                         *((volatile  uint8_t*)(0x4002434CUL))
#define FM4_MFT_PPG_PRLL21                        *((volatile  uint8_t*)(0x4002434CUL))
#define FM_MFT_PPG_PRLH21                         *((volatile  uint8_t*)(0x4002434DUL))
#define FM4_MFT_PPG_PRLH21                        *((volatile  uint8_t*)(0x4002434DUL))
#define FM_MFT_PPG_PRLL22                         *((volatile  uint8_t*)(0x40024350UL))
#define FM4_MFT_PPG_PRLL22                        *((volatile  uint8_t*)(0x40024350UL))
#define FM_MFT_PPG_PRLH22                         *((volatile  uint8_t*)(0x40024351UL))
#define FM4_MFT_PPG_PRLH22                        *((volatile  uint8_t*)(0x40024351UL))
#define FM_MFT_PPG_PRLL23                         *((volatile  uint8_t*)(0x40024354UL))
#define FM4_MFT_PPG_PRLL23                        *((volatile  uint8_t*)(0x40024354UL))
#define FM_MFT_PPG_PRLH23                         *((volatile  uint8_t*)(0x40024355UL))
#define FM4_MFT_PPG_PRLH23                        *((volatile  uint8_t*)(0x40024355UL))
#define FM_MFT_PPG_GATEC20                        *((volatile  uint8_t*)(0x40024358UL))
#define FM4_MFT_PPG_GATEC20                       *((volatile  uint8_t*)(0x40024358UL))

/*******************************************************************************
* MFT Registers MFT0
*   Register Definition
*******************************************************************************/
#define FM_MFT0_OCU_OCCP0                         *((volatile uint16_t*)(0x40020102UL))
#define FM4_MFT0_OCU_OCCP0                        *((volatile uint16_t*)(0x40020102UL))
#define FM_MFT0_OCU_OCCP1                         *((volatile uint16_t*)(0x40020106UL))
#define FM4_MFT0_OCU_OCCP1                        *((volatile uint16_t*)(0x40020106UL))
#define FM_MFT0_OCU_OCCP2                         *((volatile uint16_t*)(0x4002010AUL))
#define FM4_MFT0_OCU_OCCP2                        *((volatile uint16_t*)(0x4002010AUL))
#define FM_MFT0_OCU_OCCP3                         *((volatile uint16_t*)(0x4002010EUL))
#define FM4_MFT0_OCU_OCCP3                        *((volatile uint16_t*)(0x4002010EUL))
#define FM_MFT0_OCU_OCCP4                         *((volatile uint16_t*)(0x40020112UL))
#define FM4_MFT0_OCU_OCCP4                        *((volatile uint16_t*)(0x40020112UL))
#define FM_MFT0_OCU_OCCP5                         *((volatile uint16_t*)(0x40020116UL))
#define FM4_MFT0_OCU_OCCP5                        *((volatile uint16_t*)(0x40020116UL))
#define FM_MFT0_OCU_OCSA10                        *((volatile  uint8_t*)(0x40020118UL))
#define FM4_MFT0_OCU_OCSA10                       *((volatile  uint8_t*)(0x40020118UL))
#define FM_MFT0_OCU_OCSB10                        *((volatile  uint8_t*)(0x40020119UL))
#define FM4_MFT0_OCU_OCSB10                       *((volatile  uint8_t*)(0x40020119UL))
#define FM_MFT0_OCU_OCSD10                        *((volatile uint16_t*)(0x4002011AUL))
#define FM4_MFT0_OCU_OCSD10                       *((volatile uint16_t*)(0x4002011AUL))
#define FM_MFT0_OCU_OCSA32                        *((volatile  uint8_t*)(0x4002011CUL))
#define FM4_MFT0_OCU_OCSA32                       *((volatile  uint8_t*)(0x4002011CUL))
#define FM_MFT0_OCU_OCSB32                        *((volatile  uint8_t*)(0x4002011DUL))
#define FM4_MFT0_OCU_OCSB32                       *((volatile  uint8_t*)(0x4002011DUL))
#define FM_MFT0_OCU_OCSD32                        *((volatile uint16_t*)(0x4002011EUL))
#define FM4_MFT0_OCU_OCSD32                       *((volatile uint16_t*)(0x4002011EUL))
#define FM_MFT0_OCU_OCSA54                        *((volatile  uint8_t*)(0x40020120UL))
#define FM4_MFT0_OCU_OCSA54                       *((volatile  uint8_t*)(0x40020120UL))
#define FM_MFT0_OCU_OCSB54                        *((volatile  uint8_t*)(0x40020121UL))
#define FM4_MFT0_OCU_OCSB54                       *((volatile  uint8_t*)(0x40020121UL))
#define FM_MFT0_OCU_OCSD54                        *((volatile uint16_t*)(0x40020122UL))
#define FM4_MFT0_OCU_OCSD54                       *((volatile uint16_t*)(0x40020122UL))
#define FM_MFT0_OCU_OCSC                          *((volatile  uint8_t*)(0x40020125UL))
#define FM4_MFT0_OCU_OCSC                         *((volatile  uint8_t*)(0x40020125UL))
#define FM_MFT0_OCU_OCSE0                         *((volatile uint16_t*)(0x40020128UL))
#define FM4_MFT0_OCU_OCSE0                        *((volatile uint16_t*)(0x40020128UL))
#define FM_MFT0_OCU_OCSE1                         *((volatile uint32_t*)(0x4002012CUL))
#define FM4_MFT0_OCU_OCSE1                        *((volatile uint32_t*)(0x4002012CUL))
#define FM_MFT0_OCU_OCSE2                         *((volatile uint16_t*)(0x40020130UL))
#define FM4_MFT0_OCU_OCSE2                        *((volatile uint16_t*)(0x40020130UL))
#define FM_MFT0_OCU_OCSE3                         *((volatile uint32_t*)(0x40020134UL))
#define FM4_MFT0_OCU_OCSE3                        *((volatile uint32_t*)(0x40020134UL))
#define FM_MFT0_OCU_OCSE4                         *((volatile uint16_t*)(0x40020138UL))
#define FM4_MFT0_OCU_OCSE4                        *((volatile uint16_t*)(0x40020138UL))
#define FM_MFT0_OCU_OCSE5                         *((volatile uint32_t*)(0x4002013CUL))
#define FM4_MFT0_OCU_OCSE5                        *((volatile uint32_t*)(0x4002013CUL))
#define FM_MFT0_FRT_TCCP0                         *((volatile uint16_t*)(0x40020142UL))
#define FM4_MFT0_FRT_TCCP0                        *((volatile uint16_t*)(0x40020142UL))
#define FM_MFT0_FRT_TCDT0                         *((volatile uint16_t*)(0x40020146UL))
#define FM4_MFT0_FRT_TCDT0                        *((volatile uint16_t*)(0x40020146UL))
#define FM_MFT0_FRT_TCSA0                         *((volatile uint16_t*)(0x40020148UL))
#define FM4_MFT0_FRT_TCSA0                        *((volatile uint16_t*)(0x40020148UL))
#define FM_MFT0_FRT_TCSC0                         *((volatile uint16_t*)(0x4002014AUL))
#define FM4_MFT0_FRT_TCSC0                        *((volatile uint16_t*)(0x4002014AUL))
#define FM_MFT0_FRT_TCCP1                         *((volatile uint16_t*)(0x4002014EUL))
#define FM4_MFT0_FRT_TCCP1                        *((volatile uint16_t*)(0x4002014EUL))
#define FM_MFT0_FRT_TCDT1                         *((volatile uint16_t*)(0x40020152UL))
#define FM4_MFT0_FRT_TCDT1                        *((volatile uint16_t*)(0x40020152UL))
#define FM_MFT0_FRT_TCSA1                         *((volatile uint16_t*)(0x40020154UL))
#define FM4_MFT0_FRT_TCSA1                        *((volatile uint16_t*)(0x40020154UL))
#define FM_MFT0_FRT_TCSC1                         *((volatile uint16_t*)(0x40020156UL))
#define FM4_MFT0_FRT_TCSC1                        *((volatile uint16_t*)(0x40020156UL))
#define FM_MFT0_FRT_TCCP2                         *((volatile uint16_t*)(0x4002015AUL))
#define FM4_MFT0_FRT_TCCP2                        *((volatile uint16_t*)(0x4002015AUL))
#define FM_MFT0_FRT_TCDT2                         *((volatile uint16_t*)(0x4002015EUL))
#define FM4_MFT0_FRT_TCDT2                        *((volatile uint16_t*)(0x4002015EUL))
#define FM_MFT0_FRT_TCSA2                         *((volatile uint16_t*)(0x40020160UL))
#define FM4_MFT0_FRT_TCSA2                        *((volatile uint16_t*)(0x40020160UL))
#define FM_MFT0_FRT_TCSC2                         *((volatile uint16_t*)(0x40020162UL))
#define FM4_MFT0_FRT_TCSC2                        *((volatile uint16_t*)(0x40020162UL))
#define FM_MFT0_FRT_TCAL                          *((volatile uint32_t*)(0x40020164UL))
#define FM4_MFT0_FRT_TCAL                         *((volatile uint32_t*)(0x40020164UL))
#define FM_MFT0_OCU_OCFS10                        *((volatile  uint8_t*)(0x40020168UL))
#define FM4_MFT0_OCU_OCFS10                       *((volatile  uint8_t*)(0x40020168UL))
#define FM_MFT0_OCU_OCFS32                        *((volatile  uint8_t*)(0x40020169UL))
#define FM4_MFT0_OCU_OCFS32                       *((volatile  uint8_t*)(0x40020169UL))
#define FM_MFT0_OCU_OCFS54                        *((volatile  uint8_t*)(0x4002016AUL))
#define FM4_MFT0_OCU_OCFS54                       *((volatile  uint8_t*)(0x4002016AUL))
#define FM_MFT0_ICU_ICFS10                        *((volatile  uint8_t*)(0x4002016CUL))
#define FM4_MFT0_ICU_ICFS10                       *((volatile  uint8_t*)(0x4002016CUL))
#define FM_MFT0_ICU_ICFS32                        *((volatile  uint8_t*)(0x4002016DUL))
#define FM4_MFT0_ICU_ICFS32                       *((volatile  uint8_t*)(0x4002016DUL))
#define FM_MFT0_ADCMP_ACFS10                      *((volatile  uint8_t*)(0x40020170UL))
#define FM4_MFT0_ADCMP_ACFS10                     *((volatile  uint8_t*)(0x40020170UL))
#define FM_MFT0_ADCMP_ACFS32                      *((volatile  uint8_t*)(0x40020171UL))
#define FM4_MFT0_ADCMP_ACFS32                     *((volatile  uint8_t*)(0x40020171UL))
#define FM_MFT0_ADCMP_ACFS54                      *((volatile  uint8_t*)(0x40020172UL))
#define FM4_MFT0_ADCMP_ACFS54                     *((volatile  uint8_t*)(0x40020172UL))
#define FM_MFT0_ICU_ICCP0                         *((volatile uint16_t*)(0x40020176UL))
#define FM4_MFT0_ICU_ICCP0                        *((volatile uint16_t*)(0x40020176UL))
#define FM_MFT0_ICU_ICCP1                         *((volatile uint16_t*)(0x4002017AUL))
#define FM4_MFT0_ICU_ICCP1                        *((volatile uint16_t*)(0x4002017AUL))
#define FM_MFT0_ICU_ICCP2                         *((volatile uint16_t*)(0x4002017EUL))
#define FM4_MFT0_ICU_ICCP2                        *((volatile uint16_t*)(0x4002017EUL))
#define FM_MFT0_ICU_ICCP3                         *((volatile uint16_t*)(0x40020182UL))
#define FM4_MFT0_ICU_ICCP3                        *((volatile uint16_t*)(0x40020182UL))
#define FM_MFT0_ICU_ICSA10                        *((volatile  uint8_t*)(0x40020184UL))
#define FM4_MFT0_ICU_ICSA10                       *((volatile  uint8_t*)(0x40020184UL))
#define FM_MFT0_ICU_ICSB10                        *((volatile  uint8_t*)(0x40020185UL))
#define FM4_MFT0_ICU_ICSB10                       *((volatile  uint8_t*)(0x40020185UL))
#define FM_MFT0_ICU_ICSA32                        *((volatile  uint8_t*)(0x40020188UL))
#define FM4_MFT0_ICU_ICSA32                       *((volatile  uint8_t*)(0x40020188UL))
#define FM_MFT0_ICU_ICSB32                        *((volatile  uint8_t*)(0x40020189UL))
#define FM4_MFT0_ICU_ICSB32                       *((volatile  uint8_t*)(0x40020189UL))
#define FM_MFT0_WFG_WFTF10                        *((volatile uint16_t*)(0x4002018EUL))
#define FM4_MFT0_WFG_WFTF10                       *((volatile uint16_t*)(0x4002018EUL))
#define FM_MFT0_WFG_WFTA10                        *((volatile uint16_t*)(0x40020190UL))
#define FM4_MFT0_WFG_WFTA10                       *((volatile uint16_t*)(0x40020190UL))
#define FM_MFT0_WFG_WFTB10                        *((volatile uint16_t*)(0x40020192UL))
#define FM4_MFT0_WFG_WFTB10                       *((volatile uint16_t*)(0x40020192UL))
#define FM_MFT0_WFG_WFTF32                        *((volatile uint16_t*)(0x40020196UL))
#define FM4_MFT0_WFG_WFTF32                       *((volatile uint16_t*)(0x40020196UL))
#define FM_MFT0_WFG_WFTA32                        *((volatile uint16_t*)(0x40020198UL))
#define FM4_MFT0_WFG_WFTA32                       *((volatile uint16_t*)(0x40020198UL))
#define FM_MFT0_WFG_WFTB32                        *((volatile uint16_t*)(0x4002019AUL))
#define FM4_MFT0_WFG_WFTB32                       *((volatile uint16_t*)(0x4002019AUL))
#define FM_MFT0_WFG_WFTF54                        *((volatile uint16_t*)(0x4002019EUL))
#define FM4_MFT0_WFG_WFTF54                       *((volatile uint16_t*)(0x4002019EUL))
#define FM_MFT0_WFG_WFTA54                        *((volatile uint16_t*)(0x400201A0UL))
#define FM4_MFT0_WFG_WFTA54                       *((volatile uint16_t*)(0x400201A0UL))
#define FM_MFT0_WFG_WFTB54                        *((volatile uint16_t*)(0x400201A2UL))
#define FM4_MFT0_WFG_WFTB54                       *((volatile uint16_t*)(0x400201A2UL))
#define FM_MFT0_WFG_WFSA10                        *((volatile uint16_t*)(0x400201A4UL))
#define FM4_MFT0_WFG_WFSA10                       *((volatile uint16_t*)(0x400201A4UL))
#define FM_MFT0_WFG_WFSA32                        *((volatile uint16_t*)(0x400201A8UL))
#define FM4_MFT0_WFG_WFSA32                       *((volatile uint16_t*)(0x400201A8UL))
#define FM_MFT0_WFG_WFSA54                        *((volatile uint16_t*)(0x400201ACUL))
#define FM4_MFT0_WFG_WFSA54                       *((volatile uint16_t*)(0x400201ACUL))
#define FM_MFT0_WFG_WFIR                          *((volatile uint16_t*)(0x400201B0UL))
#define FM4_MFT0_WFG_WFIR                         *((volatile uint16_t*)(0x400201B0UL))
#define FM_MFT0_WFG_NZCL                          *((volatile uint16_t*)(0x400201B4UL))
#define FM4_MFT0_WFG_NZCL                         *((volatile uint16_t*)(0x400201B4UL))
#define FM_MFT0_ADCMP_ACMP0                       *((volatile uint16_t*)(0x400201BAUL))
#define FM4_MFT0_ADCMP_ACMP0                      *((volatile uint16_t*)(0x400201BAUL))
#define FM_MFT0_ADCMP_ACMP1                       *((volatile uint16_t*)(0x400201BEUL))
#define FM4_MFT0_ADCMP_ACMP1                      *((volatile uint16_t*)(0x400201BEUL))
#define FM_MFT0_ADCMP_ACMP2                       *((volatile uint16_t*)(0x400201C2UL))
#define FM4_MFT0_ADCMP_ACMP2                      *((volatile uint16_t*)(0x400201C2UL))
#define FM_MFT0_ADCMP_ACMP3                       *((volatile uint16_t*)(0x400201C6UL))
#define FM4_MFT0_ADCMP_ACMP3                      *((volatile uint16_t*)(0x400201C6UL))
#define FM_MFT0_ADCMP_ACMP4                       *((volatile uint16_t*)(0x400201CAUL))
#define FM4_MFT0_ADCMP_ACMP4                      *((volatile uint16_t*)(0x400201CAUL))
#define FM_MFT0_ADCMP_ACMP5                       *((volatile uint16_t*)(0x400201CEUL))
#define FM4_MFT0_ADCMP_ACMP5                      *((volatile uint16_t*)(0x400201CEUL))
#define FM_MFT0_ADCMP_ACSA                        *((volatile uint16_t*)(0x400201D0UL))
#define FM4_MFT0_ADCMP_ACSA                       *((volatile uint16_t*)(0x400201D0UL))
#define FM_MFT0_ADCMP_ACSC0                       *((volatile  uint8_t*)(0x400201D4UL))
#define FM4_MFT0_ADCMP_ACSC0                      *((volatile  uint8_t*)(0x400201D4UL))
#define FM_MFT0_ADCMP_ACSD0                       *((volatile  uint8_t*)(0x400201D5UL))
#define FM4_MFT0_ADCMP_ACSD0                      *((volatile  uint8_t*)(0x400201D5UL))
#define FM_MFT0_ADCMP_ACMC0                       *((volatile  uint8_t*)(0x400201D6UL))
#define FM4_MFT0_ADCMP_ACMC0                      *((volatile  uint8_t*)(0x400201D6UL))
#define FM_MFT0_ADCMP_ACSC1                       *((volatile  uint8_t*)(0x400201D8UL))
#define FM4_MFT0_ADCMP_ACSC1                      *((volatile  uint8_t*)(0x400201D8UL))
#define FM_MFT0_ADCMP_ACSD1                       *((volatile  uint8_t*)(0x400201D9UL))
#define FM4_MFT0_ADCMP_ACSD1                      *((volatile  uint8_t*)(0x400201D9UL))
#define FM_MFT0_ADCMP_ACMC1                       *((volatile  uint8_t*)(0x400201DAUL))
#define FM4_MFT0_ADCMP_ACMC1                      *((volatile  uint8_t*)(0x400201DAUL))
#define FM_MFT0_ADCMP_ACSC2                       *((volatile  uint8_t*)(0x400201DCUL))
#define FM4_MFT0_ADCMP_ACSC2                      *((volatile  uint8_t*)(0x400201DCUL))
#define FM_MFT0_ADCMP_ACSD2                       *((volatile  uint8_t*)(0x400201DDUL))
#define FM4_MFT0_ADCMP_ACSD2                      *((volatile  uint8_t*)(0x400201DDUL))
#define FM_MFT0_ADCMP_ACMC2                       *((volatile  uint8_t*)(0x400201DEUL))
#define FM4_MFT0_ADCMP_ACMC2                      *((volatile  uint8_t*)(0x400201DEUL))
#define FM_MFT0_ADCMP_ACSC3                       *((volatile  uint8_t*)(0x400201E0UL))
#define FM4_MFT0_ADCMP_ACSC3                      *((volatile  uint8_t*)(0x400201E0UL))
#define FM_MFT0_ADCMP_ACSD3                       *((volatile  uint8_t*)(0x400201E1UL))
#define FM4_MFT0_ADCMP_ACSD3                      *((volatile  uint8_t*)(0x400201E1UL))
#define FM_MFT0_ADCMP_ACMC3                       *((volatile  uint8_t*)(0x400201E2UL))
#define FM4_MFT0_ADCMP_ACMC3                      *((volatile  uint8_t*)(0x400201E2UL))
#define FM_MFT0_ADCMP_ACSC4                       *((volatile  uint8_t*)(0x400201E4UL))
#define FM4_MFT0_ADCMP_ACSC4                      *((volatile  uint8_t*)(0x400201E4UL))
#define FM_MFT0_ADCMP_ACSD4                       *((volatile  uint8_t*)(0x400201E5UL))
#define FM4_MFT0_ADCMP_ACSD4                      *((volatile  uint8_t*)(0x400201E5UL))
#define FM_MFT0_ADCMP_ACMC4                       *((volatile  uint8_t*)(0x400201E6UL))
#define FM4_MFT0_ADCMP_ACMC4                      *((volatile  uint8_t*)(0x400201E6UL))
#define FM_MFT0_ADCMP_ACSC5                       *((volatile  uint8_t*)(0x400201E8UL))
#define FM4_MFT0_ADCMP_ACSC5                      *((volatile  uint8_t*)(0x400201E8UL))
#define FM_MFT0_ADCMP_ACSD5                       *((volatile  uint8_t*)(0x400201E9UL))
#define FM4_MFT0_ADCMP_ACSD5                      *((volatile  uint8_t*)(0x400201E9UL))
#define FM_MFT0_ADCMP_ACMC5                       *((volatile  uint8_t*)(0x400201EAUL))
#define FM4_MFT0_ADCMP_ACMC5                      *((volatile  uint8_t*)(0x400201EAUL))
#define FM_MFT0_FRT_TCSD                          *((volatile  uint8_t*)(0x400201ECUL))
#define FM4_MFT0_FRT_TCSD                         *((volatile  uint8_t*)(0x400201ECUL))

/*******************************************************************************
* MFT Registers MFT1
*   Register Definition
*******************************************************************************/
#define FM_MFT1_OCU_OCCP0                         *((volatile uint16_t*)(0x40021102UL))
#define FM4_MFT1_OCU_OCCP0                        *((volatile uint16_t*)(0x40021102UL))
#define FM_MFT1_OCU_OCCP1                         *((volatile uint16_t*)(0x40021106UL))
#define FM4_MFT1_OCU_OCCP1                        *((volatile uint16_t*)(0x40021106UL))
#define FM_MFT1_OCU_OCCP2                         *((volatile uint16_t*)(0x4002110AUL))
#define FM4_MFT1_OCU_OCCP2                        *((volatile uint16_t*)(0x4002110AUL))
#define FM_MFT1_OCU_OCCP3                         *((volatile uint16_t*)(0x4002110EUL))
#define FM4_MFT1_OCU_OCCP3                        *((volatile uint16_t*)(0x4002110EUL))
#define FM_MFT1_OCU_OCCP4                         *((volatile uint16_t*)(0x40021112UL))
#define FM4_MFT1_OCU_OCCP4                        *((volatile uint16_t*)(0x40021112UL))
#define FM_MFT1_OCU_OCCP5                         *((volatile uint16_t*)(0x40021116UL))
#define FM4_MFT1_OCU_OCCP5                        *((volatile uint16_t*)(0x40021116UL))
#define FM_MFT1_OCU_OCSA10                        *((volatile  uint8_t*)(0x40021118UL))
#define FM4_MFT1_OCU_OCSA10                       *((volatile  uint8_t*)(0x40021118UL))
#define FM_MFT1_OCU_OCSB10                        *((volatile  uint8_t*)(0x40021119UL))
#define FM4_MFT1_OCU_OCSB10                       *((volatile  uint8_t*)(0x40021119UL))
#define FM_MFT1_OCU_OCSD10                        *((volatile uint16_t*)(0x4002111AUL))
#define FM4_MFT1_OCU_OCSD10                       *((volatile uint16_t*)(0x4002111AUL))
#define FM_MFT1_OCU_OCSA32                        *((volatile  uint8_t*)(0x4002111CUL))
#define FM4_MFT1_OCU_OCSA32                       *((volatile  uint8_t*)(0x4002111CUL))
#define FM_MFT1_OCU_OCSB32                        *((volatile  uint8_t*)(0x4002111DUL))
#define FM4_MFT1_OCU_OCSB32                       *((volatile  uint8_t*)(0x4002111DUL))
#define FM_MFT1_OCU_OCSD32                        *((volatile uint16_t*)(0x4002111EUL))
#define FM4_MFT1_OCU_OCSD32                       *((volatile uint16_t*)(0x4002111EUL))
#define FM_MFT1_OCU_OCSA54                        *((volatile  uint8_t*)(0x40021120UL))
#define FM4_MFT1_OCU_OCSA54                       *((volatile  uint8_t*)(0x40021120UL))
#define FM_MFT1_OCU_OCSB54                        *((volatile  uint8_t*)(0x40021121UL))
#define FM4_MFT1_OCU_OCSB54                       *((volatile  uint8_t*)(0x40021121UL))
#define FM_MFT1_OCU_OCSD54                        *((volatile uint16_t*)(0x40021122UL))
#define FM4_MFT1_OCU_OCSD54                       *((volatile uint16_t*)(0x40021122UL))
#define FM_MFT1_OCU_OCSC                          *((volatile  uint8_t*)(0x40021125UL))
#define FM4_MFT1_OCU_OCSC                         *((volatile  uint8_t*)(0x40021125UL))
#define FM_MFT1_OCU_OCSE0                         *((volatile uint16_t*)(0x40021128UL))
#define FM4_MFT1_OCU_OCSE0                        *((volatile uint16_t*)(0x40021128UL))
#define FM_MFT1_OCU_OCSE1                         *((volatile uint32_t*)(0x4002112CUL))
#define FM4_MFT1_OCU_OCSE1                        *((volatile uint32_t*)(0x4002112CUL))
#define FM_MFT1_OCU_OCSE2                         *((volatile uint16_t*)(0x40021130UL))
#define FM4_MFT1_OCU_OCSE2                        *((volatile uint16_t*)(0x40021130UL))
#define FM_MFT1_OCU_OCSE3                         *((volatile uint32_t*)(0x40021134UL))
#define FM4_MFT1_OCU_OCSE3                        *((volatile uint32_t*)(0x40021134UL))
#define FM_MFT1_OCU_OCSE4                         *((volatile uint16_t*)(0x40021138UL))
#define FM4_MFT1_OCU_OCSE4                        *((volatile uint16_t*)(0x40021138UL))
#define FM_MFT1_OCU_OCSE5                         *((volatile uint32_t*)(0x4002113CUL))
#define FM4_MFT1_OCU_OCSE5                        *((volatile uint32_t*)(0x4002113CUL))
#define FM_MFT1_FRT_TCCP0                         *((volatile uint16_t*)(0x40021142UL))
#define FM4_MFT1_FRT_TCCP0                        *((volatile uint16_t*)(0x40021142UL))
#define FM_MFT1_FRT_TCDT0                         *((volatile uint16_t*)(0x40021146UL))
#define FM4_MFT1_FRT_TCDT0                        *((volatile uint16_t*)(0x40021146UL))
#define FM_MFT1_FRT_TCSA0                         *((volatile uint16_t*)(0x40021148UL))
#define FM4_MFT1_FRT_TCSA0                        *((volatile uint16_t*)(0x40021148UL))
#define FM_MFT1_FRT_TCSC0                         *((volatile uint16_t*)(0x4002114AUL))
#define FM4_MFT1_FRT_TCSC0                        *((volatile uint16_t*)(0x4002114AUL))
#define FM_MFT1_FRT_TCCP1                         *((volatile uint16_t*)(0x4002114EUL))
#define FM4_MFT1_FRT_TCCP1                        *((volatile uint16_t*)(0x4002114EUL))
#define FM_MFT1_FRT_TCDT1                         *((volatile uint16_t*)(0x40021152UL))
#define FM4_MFT1_FRT_TCDT1                        *((volatile uint16_t*)(0x40021152UL))
#define FM_MFT1_FRT_TCSA1                         *((volatile uint16_t*)(0x40021154UL))
#define FM4_MFT1_FRT_TCSA1                        *((volatile uint16_t*)(0x40021154UL))
#define FM_MFT1_FRT_TCSC1                         *((volatile uint16_t*)(0x40021156UL))
#define FM4_MFT1_FRT_TCSC1                        *((volatile uint16_t*)(0x40021156UL))
#define FM_MFT1_FRT_TCCP2                         *((volatile uint16_t*)(0x4002115AUL))
#define FM4_MFT1_FRT_TCCP2                        *((volatile uint16_t*)(0x4002115AUL))
#define FM_MFT1_FRT_TCDT2                         *((volatile uint16_t*)(0x4002115EUL))
#define FM4_MFT1_FRT_TCDT2                        *((volatile uint16_t*)(0x4002115EUL))
#define FM_MFT1_FRT_TCSA2                         *((volatile uint16_t*)(0x40021160UL))
#define FM4_MFT1_FRT_TCSA2                        *((volatile uint16_t*)(0x40021160UL))
#define FM_MFT1_FRT_TCSC2                         *((volatile uint16_t*)(0x40021162UL))
#define FM4_MFT1_FRT_TCSC2                        *((volatile uint16_t*)(0x40021162UL))
#define FM_MFT1_FRT_TCAL                          *((volatile uint32_t*)(0x40021164UL))
#define FM4_MFT1_FRT_TCAL                         *((volatile uint32_t*)(0x40021164UL))
#define FM_MFT1_OCU_OCFS10                        *((volatile  uint8_t*)(0x40021168UL))
#define FM4_MFT1_OCU_OCFS10                       *((volatile  uint8_t*)(0x40021168UL))
#define FM_MFT1_OCU_OCFS32                        *((volatile  uint8_t*)(0x40021169UL))
#define FM4_MFT1_OCU_OCFS32                       *((volatile  uint8_t*)(0x40021169UL))
#define FM_MFT1_OCU_OCFS54                        *((volatile  uint8_t*)(0x4002116AUL))
#define FM4_MFT1_OCU_OCFS54                       *((volatile  uint8_t*)(0x4002116AUL))
#define FM_MFT1_ICU_ICFS10                        *((volatile  uint8_t*)(0x4002116CUL))
#define FM4_MFT1_ICU_ICFS10                       *((volatile  uint8_t*)(0x4002116CUL))
#define FM_MFT1_ICU_ICFS32                        *((volatile  uint8_t*)(0x4002116DUL))
#define FM4_MFT1_ICU_ICFS32                       *((volatile  uint8_t*)(0x4002116DUL))
#define FM_MFT1_ADCMP_ACFS10                      *((volatile  uint8_t*)(0x40021170UL))
#define FM4_MFT1_ADCMP_ACFS10                     *((volatile  uint8_t*)(0x40021170UL))
#define FM_MFT1_ADCMP_ACFS32                      *((volatile  uint8_t*)(0x40021171UL))
#define FM4_MFT1_ADCMP_ACFS32                     *((volatile  uint8_t*)(0x40021171UL))
#define FM_MFT1_ADCMP_ACFS54                      *((volatile  uint8_t*)(0x40021172UL))
#define FM4_MFT1_ADCMP_ACFS54                     *((volatile  uint8_t*)(0x40021172UL))
#define FM_MFT1_ICU_ICCP0                         *((volatile uint16_t*)(0x40021176UL))
#define FM4_MFT1_ICU_ICCP0                        *((volatile uint16_t*)(0x40021176UL))
#define FM_MFT1_ICU_ICCP1                         *((volatile uint16_t*)(0x4002117AUL))
#define FM4_MFT1_ICU_ICCP1                        *((volatile uint16_t*)(0x4002117AUL))
#define FM_MFT1_ICU_ICCP2                         *((volatile uint16_t*)(0x4002117EUL))
#define FM4_MFT1_ICU_ICCP2                        *((volatile uint16_t*)(0x4002117EUL))
#define FM_MFT1_ICU_ICCP3                         *((volatile uint16_t*)(0x40021182UL))
#define FM4_MFT1_ICU_ICCP3                        *((volatile uint16_t*)(0x40021182UL))
#define FM_MFT1_ICU_ICSA10                        *((volatile  uint8_t*)(0x40021184UL))
#define FM4_MFT1_ICU_ICSA10                       *((volatile  uint8_t*)(0x40021184UL))
#define FM_MFT1_ICU_ICSB10                        *((volatile  uint8_t*)(0x40021185UL))
#define FM4_MFT1_ICU_ICSB10                       *((volatile  uint8_t*)(0x40021185UL))
#define FM_MFT1_ICU_ICSA32                        *((volatile  uint8_t*)(0x40021188UL))
#define FM4_MFT1_ICU_ICSA32                       *((volatile  uint8_t*)(0x40021188UL))
#define FM_MFT1_ICU_ICSB32                        *((volatile  uint8_t*)(0x40021189UL))
#define FM4_MFT1_ICU_ICSB32                       *((volatile  uint8_t*)(0x40021189UL))
#define FM_MFT1_WFG_WFTF10                        *((volatile uint16_t*)(0x4002118EUL))
#define FM4_MFT1_WFG_WFTF10                       *((volatile uint16_t*)(0x4002118EUL))
#define FM_MFT1_WFG_WFTA10                        *((volatile uint16_t*)(0x40021190UL))
#define FM4_MFT1_WFG_WFTA10                       *((volatile uint16_t*)(0x40021190UL))
#define FM_MFT1_WFG_WFTB10                        *((volatile uint16_t*)(0x40021192UL))
#define FM4_MFT1_WFG_WFTB10                       *((volatile uint16_t*)(0x40021192UL))
#define FM_MFT1_WFG_WFTF32                        *((volatile uint16_t*)(0x40021196UL))
#define FM4_MFT1_WFG_WFTF32                       *((volatile uint16_t*)(0x40021196UL))
#define FM_MFT1_WFG_WFTA32                        *((volatile uint16_t*)(0x40021198UL))
#define FM4_MFT1_WFG_WFTA32                       *((volatile uint16_t*)(0x40021198UL))
#define FM_MFT1_WFG_WFTB32                        *((volatile uint16_t*)(0x4002119AUL))
#define FM4_MFT1_WFG_WFTB32                       *((volatile uint16_t*)(0x4002119AUL))
#define FM_MFT1_WFG_WFTF54                        *((volatile uint16_t*)(0x4002119EUL))
#define FM4_MFT1_WFG_WFTF54                       *((volatile uint16_t*)(0x4002119EUL))
#define FM_MFT1_WFG_WFTA54                        *((volatile uint16_t*)(0x400211A0UL))
#define FM4_MFT1_WFG_WFTA54                       *((volatile uint16_t*)(0x400211A0UL))
#define FM_MFT1_WFG_WFTB54                        *((volatile uint16_t*)(0x400211A2UL))
#define FM4_MFT1_WFG_WFTB54                       *((volatile uint16_t*)(0x400211A2UL))
#define FM_MFT1_WFG_WFSA10                        *((volatile uint16_t*)(0x400211A4UL))
#define FM4_MFT1_WFG_WFSA10                       *((volatile uint16_t*)(0x400211A4UL))
#define FM_MFT1_WFG_WFSA32                        *((volatile uint16_t*)(0x400211A8UL))
#define FM4_MFT1_WFG_WFSA32                       *((volatile uint16_t*)(0x400211A8UL))
#define FM_MFT1_WFG_WFSA54                        *((volatile uint16_t*)(0x400211ACUL))
#define FM4_MFT1_WFG_WFSA54                       *((volatile uint16_t*)(0x400211ACUL))
#define FM_MFT1_WFG_WFIR                          *((volatile uint16_t*)(0x400211B0UL))
#define FM4_MFT1_WFG_WFIR                         *((volatile uint16_t*)(0x400211B0UL))
#define FM_MFT1_WFG_NZCL                          *((volatile uint16_t*)(0x400211B4UL))
#define FM4_MFT1_WFG_NZCL                         *((volatile uint16_t*)(0x400211B4UL))
#define FM_MFT1_ADCMP_ACMP0                       *((volatile uint16_t*)(0x400211BAUL))
#define FM4_MFT1_ADCMP_ACMP0                      *((volatile uint16_t*)(0x400211BAUL))
#define FM_MFT1_ADCMP_ACMP1                       *((volatile uint16_t*)(0x400211BEUL))
#define FM4_MFT1_ADCMP_ACMP1                      *((volatile uint16_t*)(0x400211BEUL))
#define FM_MFT1_ADCMP_ACMP2                       *((volatile uint16_t*)(0x400211C2UL))
#define FM4_MFT1_ADCMP_ACMP2                      *((volatile uint16_t*)(0x400211C2UL))
#define FM_MFT1_ADCMP_ACMP3                       *((volatile uint16_t*)(0x400211C6UL))
#define FM4_MFT1_ADCMP_ACMP3                      *((volatile uint16_t*)(0x400211C6UL))
#define FM_MFT1_ADCMP_ACMP4                       *((volatile uint16_t*)(0x400211CAUL))
#define FM4_MFT1_ADCMP_ACMP4                      *((volatile uint16_t*)(0x400211CAUL))
#define FM_MFT1_ADCMP_ACMP5                       *((volatile uint16_t*)(0x400211CEUL))
#define FM4_MFT1_ADCMP_ACMP5                      *((volatile uint16_t*)(0x400211CEUL))
#define FM_MFT1_ADCMP_ACSA                        *((volatile uint16_t*)(0x400211D0UL))
#define FM4_MFT1_ADCMP_ACSA                       *((volatile uint16_t*)(0x400211D0UL))
#define FM_MFT1_ADCMP_ACSC0                       *((volatile  uint8_t*)(0x400211D4UL))
#define FM4_MFT1_ADCMP_ACSC0                      *((volatile  uint8_t*)(0x400211D4UL))
#define FM_MFT1_ADCMP_ACSD0                       *((volatile  uint8_t*)(0x400211D5UL))
#define FM4_MFT1_ADCMP_ACSD0                      *((volatile  uint8_t*)(0x400211D5UL))
#define FM_MFT1_ADCMP_ACMC0                       *((volatile  uint8_t*)(0x400211D6UL))
#define FM4_MFT1_ADCMP_ACMC0                      *((volatile  uint8_t*)(0x400211D6UL))
#define FM_MFT1_ADCMP_ACSC1                       *((volatile  uint8_t*)(0x400211D8UL))
#define FM4_MFT1_ADCMP_ACSC1                      *((volatile  uint8_t*)(0x400211D8UL))
#define FM_MFT1_ADCMP_ACSD1                       *((volatile  uint8_t*)(0x400211D9UL))
#define FM4_MFT1_ADCMP_ACSD1                      *((volatile  uint8_t*)(0x400211D9UL))
#define FM_MFT1_ADCMP_ACMC1                       *((volatile  uint8_t*)(0x400211DAUL))
#define FM4_MFT1_ADCMP_ACMC1                      *((volatile  uint8_t*)(0x400211DAUL))
#define FM_MFT1_ADCMP_ACSC2                       *((volatile  uint8_t*)(0x400211DCUL))
#define FM4_MFT1_ADCMP_ACSC2                      *((volatile  uint8_t*)(0x400211DCUL))
#define FM_MFT1_ADCMP_ACSD2                       *((volatile  uint8_t*)(0x400211DDUL))
#define FM4_MFT1_ADCMP_ACSD2                      *((volatile  uint8_t*)(0x400211DDUL))
#define FM_MFT1_ADCMP_ACMC2                       *((volatile  uint8_t*)(0x400211DEUL))
#define FM4_MFT1_ADCMP_ACMC2                      *((volatile  uint8_t*)(0x400211DEUL))
#define FM_MFT1_ADCMP_ACSC3                       *((volatile  uint8_t*)(0x400211E0UL))
#define FM4_MFT1_ADCMP_ACSC3                      *((volatile  uint8_t*)(0x400211E0UL))
#define FM_MFT1_ADCMP_ACSD3                       *((volatile  uint8_t*)(0x400211E1UL))
#define FM4_MFT1_ADCMP_ACSD3                      *((volatile  uint8_t*)(0x400211E1UL))
#define FM_MFT1_ADCMP_ACMC3                       *((volatile  uint8_t*)(0x400211E2UL))
#define FM4_MFT1_ADCMP_ACMC3                      *((volatile  uint8_t*)(0x400211E2UL))
#define FM_MFT1_ADCMP_ACSC4                       *((volatile  uint8_t*)(0x400211E4UL))
#define FM4_MFT1_ADCMP_ACSC4                      *((volatile  uint8_t*)(0x400211E4UL))
#define FM_MFT1_ADCMP_ACSD4                       *((volatile  uint8_t*)(0x400211E5UL))
#define FM4_MFT1_ADCMP_ACSD4                      *((volatile  uint8_t*)(0x400211E5UL))
#define FM_MFT1_ADCMP_ACMC4                       *((volatile  uint8_t*)(0x400211E6UL))
#define FM4_MFT1_ADCMP_ACMC4                      *((volatile  uint8_t*)(0x400211E6UL))
#define FM_MFT1_ADCMP_ACSC5                       *((volatile  uint8_t*)(0x400211E8UL))
#define FM4_MFT1_ADCMP_ACSC5                      *((volatile  uint8_t*)(0x400211E8UL))
#define FM_MFT1_ADCMP_ACSD5                       *((volatile  uint8_t*)(0x400211E9UL))
#define FM4_MFT1_ADCMP_ACSD5                      *((volatile  uint8_t*)(0x400211E9UL))
#define FM_MFT1_ADCMP_ACMC5                       *((volatile  uint8_t*)(0x400211EAUL))
#define FM4_MFT1_ADCMP_ACMC5                      *((volatile  uint8_t*)(0x400211EAUL))
#define FM_MFT1_FRT_TCSD                          *((volatile  uint8_t*)(0x400211ECUL))
#define FM4_MFT1_FRT_TCSD                         *((volatile  uint8_t*)(0x400211ECUL))

/*******************************************************************************
* MFT Registers MFT2
*   Register Definition
*******************************************************************************/
#define FM_MFT2_OCU_OCCP0                         *((volatile uint16_t*)(0x40022102UL))
#define FM4_MFT2_OCU_OCCP0                        *((volatile uint16_t*)(0x40022102UL))
#define FM_MFT2_OCU_OCCP1                         *((volatile uint16_t*)(0x40022106UL))
#define FM4_MFT2_OCU_OCCP1                        *((volatile uint16_t*)(0x40022106UL))
#define FM_MFT2_OCU_OCCP2                         *((volatile uint16_t*)(0x4002210AUL))
#define FM4_MFT2_OCU_OCCP2                        *((volatile uint16_t*)(0x4002210AUL))
#define FM_MFT2_OCU_OCCP3                         *((volatile uint16_t*)(0x4002210EUL))
#define FM4_MFT2_OCU_OCCP3                        *((volatile uint16_t*)(0x4002210EUL))
#define FM_MFT2_OCU_OCCP4                         *((volatile uint16_t*)(0x40022112UL))
#define FM4_MFT2_OCU_OCCP4                        *((volatile uint16_t*)(0x40022112UL))
#define FM_MFT2_OCU_OCCP5                         *((volatile uint16_t*)(0x40022116UL))
#define FM4_MFT2_OCU_OCCP5                        *((volatile uint16_t*)(0x40022116UL))
#define FM_MFT2_OCU_OCSA10                        *((volatile  uint8_t*)(0x40022118UL))
#define FM4_MFT2_OCU_OCSA10                       *((volatile  uint8_t*)(0x40022118UL))
#define FM_MFT2_OCU_OCSB10                        *((volatile  uint8_t*)(0x40022119UL))
#define FM4_MFT2_OCU_OCSB10                       *((volatile  uint8_t*)(0x40022119UL))
#define FM_MFT2_OCU_OCSD10                        *((volatile uint16_t*)(0x4002211AUL))
#define FM4_MFT2_OCU_OCSD10                       *((volatile uint16_t*)(0x4002211AUL))
#define FM_MFT2_OCU_OCSA32                        *((volatile  uint8_t*)(0x4002211CUL))
#define FM4_MFT2_OCU_OCSA32                       *((volatile  uint8_t*)(0x4002211CUL))
#define FM_MFT2_OCU_OCSB32                        *((volatile  uint8_t*)(0x4002211DUL))
#define FM4_MFT2_OCU_OCSB32                       *((volatile  uint8_t*)(0x4002211DUL))
#define FM_MFT2_OCU_OCSD32                        *((volatile uint16_t*)(0x4002211EUL))
#define FM4_MFT2_OCU_OCSD32                       *((volatile uint16_t*)(0x4002211EUL))
#define FM_MFT2_OCU_OCSA54                        *((volatile  uint8_t*)(0x40022120UL))
#define FM4_MFT2_OCU_OCSA54                       *((volatile  uint8_t*)(0x40022120UL))
#define FM_MFT2_OCU_OCSB54                        *((volatile  uint8_t*)(0x40022121UL))
#define FM4_MFT2_OCU_OCSB54                       *((volatile  uint8_t*)(0x40022121UL))
#define FM_MFT2_OCU_OCSD54                        *((volatile uint16_t*)(0x40022122UL))
#define FM4_MFT2_OCU_OCSD54                       *((volatile uint16_t*)(0x40022122UL))
#define FM_MFT2_OCU_OCSC                          *((volatile  uint8_t*)(0x40022125UL))
#define FM4_MFT2_OCU_OCSC                         *((volatile  uint8_t*)(0x40022125UL))
#define FM_MFT2_OCU_OCSE0                         *((volatile uint16_t*)(0x40022128UL))
#define FM4_MFT2_OCU_OCSE0                        *((volatile uint16_t*)(0x40022128UL))
#define FM_MFT2_OCU_OCSE1                         *((volatile uint32_t*)(0x4002212CUL))
#define FM4_MFT2_OCU_OCSE1                        *((volatile uint32_t*)(0x4002212CUL))
#define FM_MFT2_OCU_OCSE2                         *((volatile uint16_t*)(0x40022130UL))
#define FM4_MFT2_OCU_OCSE2                        *((volatile uint16_t*)(0x40022130UL))
#define FM_MFT2_OCU_OCSE3                         *((volatile uint32_t*)(0x40022134UL))
#define FM4_MFT2_OCU_OCSE3                        *((volatile uint32_t*)(0x40022134UL))
#define FM_MFT2_OCU_OCSE4                         *((volatile uint16_t*)(0x40022138UL))
#define FM4_MFT2_OCU_OCSE4                        *((volatile uint16_t*)(0x40022138UL))
#define FM_MFT2_OCU_OCSE5                         *((volatile uint32_t*)(0x4002213CUL))
#define FM4_MFT2_OCU_OCSE5                        *((volatile uint32_t*)(0x4002213CUL))
#define FM_MFT2_FRT_TCCP0                         *((volatile uint16_t*)(0x40022142UL))
#define FM4_MFT2_FRT_TCCP0                        *((volatile uint16_t*)(0x40022142UL))
#define FM_MFT2_FRT_TCDT0                         *((volatile uint16_t*)(0x40022146UL))
#define FM4_MFT2_FRT_TCDT0                        *((volatile uint16_t*)(0x40022146UL))
#define FM_MFT2_FRT_TCSA0                         *((volatile uint16_t*)(0x40022148UL))
#define FM4_MFT2_FRT_TCSA0                        *((volatile uint16_t*)(0x40022148UL))
#define FM_MFT2_FRT_TCSC0                         *((volatile uint16_t*)(0x4002214AUL))
#define FM4_MFT2_FRT_TCSC0                        *((volatile uint16_t*)(0x4002214AUL))
#define FM_MFT2_FRT_TCCP1                         *((volatile uint16_t*)(0x4002214EUL))
#define FM4_MFT2_FRT_TCCP1                        *((volatile uint16_t*)(0x4002214EUL))
#define FM_MFT2_FRT_TCDT1                         *((volatile uint16_t*)(0x40022152UL))
#define FM4_MFT2_FRT_TCDT1                        *((volatile uint16_t*)(0x40022152UL))
#define FM_MFT2_FRT_TCSA1                         *((volatile uint16_t*)(0x40022154UL))
#define FM4_MFT2_FRT_TCSA1                        *((volatile uint16_t*)(0x40022154UL))
#define FM_MFT2_FRT_TCSC1                         *((volatile uint16_t*)(0x40022156UL))
#define FM4_MFT2_FRT_TCSC1                        *((volatile uint16_t*)(0x40022156UL))
#define FM_MFT2_FRT_TCCP2                         *((volatile uint16_t*)(0x4002215AUL))
#define FM4_MFT2_FRT_TCCP2                        *((volatile uint16_t*)(0x4002215AUL))
#define FM_MFT2_FRT_TCDT2                         *((volatile uint16_t*)(0x4002215EUL))
#define FM4_MFT2_FRT_TCDT2                        *((volatile uint16_t*)(0x4002215EUL))
#define FM_MFT2_FRT_TCSA2                         *((volatile uint16_t*)(0x40022160UL))
#define FM4_MFT2_FRT_TCSA2                        *((volatile uint16_t*)(0x40022160UL))
#define FM_MFT2_FRT_TCSC2                         *((volatile uint16_t*)(0x40022162UL))
#define FM4_MFT2_FRT_TCSC2                        *((volatile uint16_t*)(0x40022162UL))
#define FM_MFT2_FRT_TCAL                          *((volatile uint32_t*)(0x40022164UL))
#define FM4_MFT2_FRT_TCAL                         *((volatile uint32_t*)(0x40022164UL))
#define FM_MFT2_OCU_OCFS10                        *((volatile  uint8_t*)(0x40022168UL))
#define FM4_MFT2_OCU_OCFS10                       *((volatile  uint8_t*)(0x40022168UL))
#define FM_MFT2_OCU_OCFS32                        *((volatile  uint8_t*)(0x40022169UL))
#define FM4_MFT2_OCU_OCFS32                       *((volatile  uint8_t*)(0x40022169UL))
#define FM_MFT2_OCU_OCFS54                        *((volatile  uint8_t*)(0x4002216AUL))
#define FM4_MFT2_OCU_OCFS54                       *((volatile  uint8_t*)(0x4002216AUL))
#define FM_MFT2_ICU_ICFS10                        *((volatile  uint8_t*)(0x4002216CUL))
#define FM4_MFT2_ICU_ICFS10                       *((volatile  uint8_t*)(0x4002216CUL))
#define FM_MFT2_ICU_ICFS32                        *((volatile  uint8_t*)(0x4002216DUL))
#define FM4_MFT2_ICU_ICFS32                       *((volatile  uint8_t*)(0x4002216DUL))
#define FM_MFT2_ADCMP_ACFS10                      *((volatile  uint8_t*)(0x40022170UL))
#define FM4_MFT2_ADCMP_ACFS10                     *((volatile  uint8_t*)(0x40022170UL))
#define FM_MFT2_ADCMP_ACFS32                      *((volatile  uint8_t*)(0x40022171UL))
#define FM4_MFT2_ADCMP_ACFS32                     *((volatile  uint8_t*)(0x40022171UL))
#define FM_MFT2_ADCMP_ACFS54                      *((volatile  uint8_t*)(0x40022172UL))
#define FM4_MFT2_ADCMP_ACFS54                     *((volatile  uint8_t*)(0x40022172UL))
#define FM_MFT2_ICU_ICCP0                         *((volatile uint16_t*)(0x40022176UL))
#define FM4_MFT2_ICU_ICCP0                        *((volatile uint16_t*)(0x40022176UL))
#define FM_MFT2_ICU_ICCP1                         *((volatile uint16_t*)(0x4002217AUL))
#define FM4_MFT2_ICU_ICCP1                        *((volatile uint16_t*)(0x4002217AUL))
#define FM_MFT2_ICU_ICCP2                         *((volatile uint16_t*)(0x4002217EUL))
#define FM4_MFT2_ICU_ICCP2                        *((volatile uint16_t*)(0x4002217EUL))
#define FM_MFT2_ICU_ICCP3                         *((volatile uint16_t*)(0x40022182UL))
#define FM4_MFT2_ICU_ICCP3                        *((volatile uint16_t*)(0x40022182UL))
#define FM_MFT2_ICU_ICSA10                        *((volatile  uint8_t*)(0x40022184UL))
#define FM4_MFT2_ICU_ICSA10                       *((volatile  uint8_t*)(0x40022184UL))
#define FM_MFT2_ICU_ICSB10                        *((volatile  uint8_t*)(0x40022185UL))
#define FM4_MFT2_ICU_ICSB10                       *((volatile  uint8_t*)(0x40022185UL))
#define FM_MFT2_ICU_ICSA32                        *((volatile  uint8_t*)(0x40022188UL))
#define FM4_MFT2_ICU_ICSA32                       *((volatile  uint8_t*)(0x40022188UL))
#define FM_MFT2_ICU_ICSB32                        *((volatile  uint8_t*)(0x40022189UL))
#define FM4_MFT2_ICU_ICSB32                       *((volatile  uint8_t*)(0x40022189UL))
#define FM_MFT2_WFG_WFTF10                        *((volatile uint16_t*)(0x4002218EUL))
#define FM4_MFT2_WFG_WFTF10                       *((volatile uint16_t*)(0x4002218EUL))
#define FM_MFT2_WFG_WFTA10                        *((volatile uint16_t*)(0x40022190UL))
#define FM4_MFT2_WFG_WFTA10                       *((volatile uint16_t*)(0x40022190UL))
#define FM_MFT2_WFG_WFTB10                        *((volatile uint16_t*)(0x40022192UL))
#define FM4_MFT2_WFG_WFTB10                       *((volatile uint16_t*)(0x40022192UL))
#define FM_MFT2_WFG_WFTF32                        *((volatile uint16_t*)(0x40022196UL))
#define FM4_MFT2_WFG_WFTF32                       *((volatile uint16_t*)(0x40022196UL))
#define FM_MFT2_WFG_WFTA32                        *((volatile uint16_t*)(0x40022198UL))
#define FM4_MFT2_WFG_WFTA32                       *((volatile uint16_t*)(0x40022198UL))
#define FM_MFT2_WFG_WFTB32                        *((volatile uint16_t*)(0x4002219AUL))
#define FM4_MFT2_WFG_WFTB32                       *((volatile uint16_t*)(0x4002219AUL))
#define FM_MFT2_WFG_WFTF54                        *((volatile uint16_t*)(0x4002219EUL))
#define FM4_MFT2_WFG_WFTF54                       *((volatile uint16_t*)(0x4002219EUL))
#define FM_MFT2_WFG_WFTA54                        *((volatile uint16_t*)(0x400221A0UL))
#define FM4_MFT2_WFG_WFTA54                       *((volatile uint16_t*)(0x400221A0UL))
#define FM_MFT2_WFG_WFTB54                        *((volatile uint16_t*)(0x400221A2UL))
#define FM4_MFT2_WFG_WFTB54                       *((volatile uint16_t*)(0x400221A2UL))
#define FM_MFT2_WFG_WFSA10                        *((volatile uint16_t*)(0x400221A4UL))
#define FM4_MFT2_WFG_WFSA10                       *((volatile uint16_t*)(0x400221A4UL))
#define FM_MFT2_WFG_WFSA32                        *((volatile uint16_t*)(0x400221A8UL))
#define FM4_MFT2_WFG_WFSA32                       *((volatile uint16_t*)(0x400221A8UL))
#define FM_MFT2_WFG_WFSA54                        *((volatile uint16_t*)(0x400221ACUL))
#define FM4_MFT2_WFG_WFSA54                       *((volatile uint16_t*)(0x400221ACUL))
#define FM_MFT2_WFG_WFIR                          *((volatile uint16_t*)(0x400221B0UL))
#define FM4_MFT2_WFG_WFIR                         *((volatile uint16_t*)(0x400221B0UL))
#define FM_MFT2_WFG_NZCL                          *((volatile uint16_t*)(0x400221B4UL))
#define FM4_MFT2_WFG_NZCL                         *((volatile uint16_t*)(0x400221B4UL))
#define FM_MFT2_ADCMP_ACMP0                       *((volatile uint16_t*)(0x400221BAUL))
#define FM4_MFT2_ADCMP_ACMP0                      *((volatile uint16_t*)(0x400221BAUL))
#define FM_MFT2_ADCMP_ACMP1                       *((volatile uint16_t*)(0x400221BEUL))
#define FM4_MFT2_ADCMP_ACMP1                      *((volatile uint16_t*)(0x400221BEUL))
#define FM_MFT2_ADCMP_ACMP2                       *((volatile uint16_t*)(0x400221C2UL))
#define FM4_MFT2_ADCMP_ACMP2                      *((volatile uint16_t*)(0x400221C2UL))
#define FM_MFT2_ADCMP_ACMP3                       *((volatile uint16_t*)(0x400221C6UL))
#define FM4_MFT2_ADCMP_ACMP3                      *((volatile uint16_t*)(0x400221C6UL))
#define FM_MFT2_ADCMP_ACMP4                       *((volatile uint16_t*)(0x400221CAUL))
#define FM4_MFT2_ADCMP_ACMP4                      *((volatile uint16_t*)(0x400221CAUL))
#define FM_MFT2_ADCMP_ACMP5                       *((volatile uint16_t*)(0x400221CEUL))
#define FM4_MFT2_ADCMP_ACMP5                      *((volatile uint16_t*)(0x400221CEUL))
#define FM_MFT2_ADCMP_ACSA                        *((volatile uint16_t*)(0x400221D0UL))
#define FM4_MFT2_ADCMP_ACSA                       *((volatile uint16_t*)(0x400221D0UL))
#define FM_MFT2_ADCMP_ACSC0                       *((volatile  uint8_t*)(0x400221D4UL))
#define FM4_MFT2_ADCMP_ACSC0                      *((volatile  uint8_t*)(0x400221D4UL))
#define FM_MFT2_ADCMP_ACSD0                       *((volatile  uint8_t*)(0x400221D5UL))
#define FM4_MFT2_ADCMP_ACSD0                      *((volatile  uint8_t*)(0x400221D5UL))
#define FM_MFT2_ADCMP_ACMC0                       *((volatile  uint8_t*)(0x400221D6UL))
#define FM4_MFT2_ADCMP_ACMC0                      *((volatile  uint8_t*)(0x400221D6UL))
#define FM_MFT2_ADCMP_ACSC1                       *((volatile  uint8_t*)(0x400221D8UL))
#define FM4_MFT2_ADCMP_ACSC1                      *((volatile  uint8_t*)(0x400221D8UL))
#define FM_MFT2_ADCMP_ACSD1                       *((volatile  uint8_t*)(0x400221D9UL))
#define FM4_MFT2_ADCMP_ACSD1                      *((volatile  uint8_t*)(0x400221D9UL))
#define FM_MFT2_ADCMP_ACMC1                       *((volatile  uint8_t*)(0x400221DAUL))
#define FM4_MFT2_ADCMP_ACMC1                      *((volatile  uint8_t*)(0x400221DAUL))
#define FM_MFT2_ADCMP_ACSC2                       *((volatile  uint8_t*)(0x400221DCUL))
#define FM4_MFT2_ADCMP_ACSC2                      *((volatile  uint8_t*)(0x400221DCUL))
#define FM_MFT2_ADCMP_ACSD2                       *((volatile  uint8_t*)(0x400221DDUL))
#define FM4_MFT2_ADCMP_ACSD2                      *((volatile  uint8_t*)(0x400221DDUL))
#define FM_MFT2_ADCMP_ACMC2                       *((volatile  uint8_t*)(0x400221DEUL))
#define FM4_MFT2_ADCMP_ACMC2                      *((volatile  uint8_t*)(0x400221DEUL))
#define FM_MFT2_ADCMP_ACSC3                       *((volatile  uint8_t*)(0x400221E0UL))
#define FM4_MFT2_ADCMP_ACSC3                      *((volatile  uint8_t*)(0x400221E0UL))
#define FM_MFT2_ADCMP_ACSD3                       *((volatile  uint8_t*)(0x400221E1UL))
#define FM4_MFT2_ADCMP_ACSD3                      *((volatile  uint8_t*)(0x400221E1UL))
#define FM_MFT2_ADCMP_ACMC3                       *((volatile  uint8_t*)(0x400221E2UL))
#define FM4_MFT2_ADCMP_ACMC3                      *((volatile  uint8_t*)(0x400221E2UL))
#define FM_MFT2_ADCMP_ACSC4                       *((volatile  uint8_t*)(0x400221E4UL))
#define FM4_MFT2_ADCMP_ACSC4                      *((volatile  uint8_t*)(0x400221E4UL))
#define FM_MFT2_ADCMP_ACSD4                       *((volatile  uint8_t*)(0x400221E5UL))
#define FM4_MFT2_ADCMP_ACSD4                      *((volatile  uint8_t*)(0x400221E5UL))
#define FM_MFT2_ADCMP_ACMC4                       *((volatile  uint8_t*)(0x400221E6UL))
#define FM4_MFT2_ADCMP_ACMC4                      *((volatile  uint8_t*)(0x400221E6UL))
#define FM_MFT2_ADCMP_ACSC5                       *((volatile  uint8_t*)(0x400221E8UL))
#define FM4_MFT2_ADCMP_ACSC5                      *((volatile  uint8_t*)(0x400221E8UL))
#define FM_MFT2_ADCMP_ACSD5                       *((volatile  uint8_t*)(0x400221E9UL))
#define FM4_MFT2_ADCMP_ACSD5                      *((volatile  uint8_t*)(0x400221E9UL))
#define FM_MFT2_ADCMP_ACMC5                       *((volatile  uint8_t*)(0x400221EAUL))
#define FM4_MFT2_ADCMP_ACMC5                      *((volatile  uint8_t*)(0x400221EAUL))
#define FM_MFT2_FRT_TCSD                          *((volatile  uint8_t*)(0x400221ECUL))
#define FM4_MFT2_FRT_TCSD                         *((volatile  uint8_t*)(0x400221ECUL))

/*******************************************************************************
* PCRC Registers PCRC
*   Register Definition
*******************************************************************************/
#define FM_PCRC_PCRC_POLY                         *((volatile uint32_t*)(0x40080000UL))
#define FM4_PCRC_PCRC_POLY                        *((volatile uint32_t*)(0x40080000UL))
#define FM_PCRC_PCRC_SEED                         *((volatile uint32_t*)(0x40080004UL))
#define FM4_PCRC_PCRC_SEED                        *((volatile uint32_t*)(0x40080004UL))
#define FM_PCRC_PCRC_FXOR                         *((volatile uint32_t*)(0x40080008UL))
#define FM4_PCRC_PCRC_FXOR                        *((volatile uint32_t*)(0x40080008UL))
#define FM_PCRC_PCRC_CFG                          *((volatile uint32_t*)(0x4008000CUL))
#define FM4_PCRC_PCRC_CFG                         *((volatile uint32_t*)(0x4008000CUL))
#define FM_PCRC_PCRC_WR                           *((volatile uint32_t*)(0x40080010UL))
#define FM4_PCRC_PCRC_WR                          *((volatile uint32_t*)(0x40080010UL))
#define FM_PCRC_PCRC_RD                           *((volatile uint32_t*)(0x40080014UL))
#define FM4_PCRC_PCRC_RD                          *((volatile uint32_t*)(0x40080014UL))

/*******************************************************************************
* QPRC Registers QPRC0
*   Register Definition
*******************************************************************************/
#define FM_QPRC0_QPCR                             *((volatile uint16_t*)(0x40026000UL))
#define FM4_QPRC0_QPCR                            *((volatile uint16_t*)(0x40026000UL))
#define FM_QPRC0_QRCR                             *((volatile uint16_t*)(0x40026004UL))
#define FM4_QPRC0_QRCR                            *((volatile uint16_t*)(0x40026004UL))
#define FM_QPRC0_QPCCR                            *((volatile uint16_t*)(0x40026008UL))
#define FM4_QPRC0_QPCCR                           *((volatile uint16_t*)(0x40026008UL))
#define FM_QPRC0_QPRCR                            *((volatile uint16_t*)(0x4002600CUL))
#define FM4_QPRC0_QPRCR                           *((volatile uint16_t*)(0x4002600CUL))
#define FM_QPRC0_QMPR                             *((volatile uint16_t*)(0x40026010UL))
#define FM4_QPRC0_QMPR                            *((volatile uint16_t*)(0x40026010UL))
#define FM_QPRC0_QICRL                            *((volatile  uint8_t*)(0x40026014UL))
#define FM4_QPRC0_QICRL                           *((volatile  uint8_t*)(0x40026014UL))
#define FM_QPRC0_QICRH                            *((volatile  uint8_t*)(0x40026015UL))
#define FM4_QPRC0_QICRH                           *((volatile  uint8_t*)(0x40026015UL))
#define FM_QPRC0_QCR                              *((volatile uint16_t*)(0x40026018UL))
#define FM4_QPRC0_QCR                             *((volatile uint16_t*)(0x40026018UL))
#define FM_QPRC0_QECR                             *((volatile uint16_t*)(0x4002601CUL))
#define FM4_QPRC0_QECR                            *((volatile uint16_t*)(0x4002601CUL))
#define FM_QPRC0_QPRCRR                           *((volatile uint32_t*)(0x4002603CUL))
#define FM4_QPRC0_QPRCRR                          *((volatile uint32_t*)(0x4002603CUL))

/*******************************************************************************
* QPRC_NF Registers QPRC0_NF
*   Register Definition
*******************************************************************************/
#define FM_QPRC0_NF_NFCTLA                        *((volatile  uint8_t*)(0x40026100UL))
#define FM4_QPRC0_NF_NFCTLA                       *((volatile  uint8_t*)(0x40026100UL))
#define FM_QPRC0_NF_NFCTLB                        *((volatile  uint8_t*)(0x40026104UL))
#define FM4_QPRC0_NF_NFCTLB                       *((volatile  uint8_t*)(0x40026104UL))
#define FM_QPRC0_NF_NFCTLZ                        *((volatile  uint8_t*)(0x40026108UL))
#define FM4_QPRC0_NF_NFCTLZ                       *((volatile  uint8_t*)(0x40026108UL))

/*******************************************************************************
* QPRC Registers QPRC1
*   Register Definition
*******************************************************************************/
#define FM_QPRC1_QPCR                             *((volatile uint16_t*)(0x40026040UL))
#define FM4_QPRC1_QPCR                            *((volatile uint16_t*)(0x40026040UL))
#define FM_QPRC1_QRCR                             *((volatile uint16_t*)(0x40026044UL))
#define FM4_QPRC1_QRCR                            *((volatile uint16_t*)(0x40026044UL))
#define FM_QPRC1_QPCCR                            *((volatile uint16_t*)(0x40026048UL))
#define FM4_QPRC1_QPCCR                           *((volatile uint16_t*)(0x40026048UL))
#define FM_QPRC1_QPRCR                            *((volatile uint16_t*)(0x4002604CUL))
#define FM4_QPRC1_QPRCR                           *((volatile uint16_t*)(0x4002604CUL))
#define FM_QPRC1_QMPR                             *((volatile uint16_t*)(0x40026050UL))
#define FM4_QPRC1_QMPR                            *((volatile uint16_t*)(0x40026050UL))
#define FM_QPRC1_QICRL                            *((volatile  uint8_t*)(0x40026054UL))
#define FM4_QPRC1_QICRL                           *((volatile  uint8_t*)(0x40026054UL))
#define FM_QPRC1_QICRH                            *((volatile  uint8_t*)(0x40026055UL))
#define FM4_QPRC1_QICRH                           *((volatile  uint8_t*)(0x40026055UL))
#define FM_QPRC1_QCR                              *((volatile uint16_t*)(0x40026058UL))
#define FM4_QPRC1_QCR                             *((volatile uint16_t*)(0x40026058UL))
#define FM_QPRC1_QECR                             *((volatile uint16_t*)(0x4002605CUL))
#define FM4_QPRC1_QECR                            *((volatile uint16_t*)(0x4002605CUL))
#define FM_QPRC1_QPRCRR                           *((volatile uint32_t*)(0x4002607CUL))
#define FM4_QPRC1_QPRCRR                          *((volatile uint32_t*)(0x4002607CUL))

/*******************************************************************************
* QPRC_NF Registers QPRC1_NF
*   Register Definition
*******************************************************************************/
#define FM_QPRC1_NF_NFCTLA                        *((volatile  uint8_t*)(0x40026110UL))
#define FM4_QPRC1_NF_NFCTLA                       *((volatile  uint8_t*)(0x40026110UL))
#define FM_QPRC1_NF_NFCTLB                        *((volatile  uint8_t*)(0x40026114UL))
#define FM4_QPRC1_NF_NFCTLB                       *((volatile  uint8_t*)(0x40026114UL))
#define FM_QPRC1_NF_NFCTLZ                        *((volatile  uint8_t*)(0x40026118UL))
#define FM4_QPRC1_NF_NFCTLZ                       *((volatile  uint8_t*)(0x40026118UL))

/*******************************************************************************
* QPRC Registers QPRC2
*   Register Definition
*******************************************************************************/
#define FM_QPRC2_QPCR                             *((volatile uint16_t*)(0x40026080UL))
#define FM4_QPRC2_QPCR                            *((volatile uint16_t*)(0x40026080UL))
#define FM_QPRC2_QRCR                             *((volatile uint16_t*)(0x40026084UL))
#define FM4_QPRC2_QRCR                            *((volatile uint16_t*)(0x40026084UL))
#define FM_QPRC2_QPCCR                            *((volatile uint16_t*)(0x40026088UL))
#define FM4_QPRC2_QPCCR                           *((volatile uint16_t*)(0x40026088UL))
#define FM_QPRC2_QPRCR                            *((volatile uint16_t*)(0x4002608CUL))
#define FM4_QPRC2_QPRCR                           *((volatile uint16_t*)(0x4002608CUL))
#define FM_QPRC2_QMPR                             *((volatile uint16_t*)(0x40026090UL))
#define FM4_QPRC2_QMPR                            *((volatile uint16_t*)(0x40026090UL))
#define FM_QPRC2_QICRL                            *((volatile  uint8_t*)(0x40026094UL))
#define FM4_QPRC2_QICRL                           *((volatile  uint8_t*)(0x40026094UL))
#define FM_QPRC2_QICRH                            *((volatile  uint8_t*)(0x40026095UL))
#define FM4_QPRC2_QICRH                           *((volatile  uint8_t*)(0x40026095UL))
#define FM_QPRC2_QCR                              *((volatile uint16_t*)(0x40026098UL))
#define FM4_QPRC2_QCR                             *((volatile uint16_t*)(0x40026098UL))
#define FM_QPRC2_QECR                             *((volatile uint16_t*)(0x4002609CUL))
#define FM4_QPRC2_QECR                            *((volatile uint16_t*)(0x4002609CUL))
#define FM_QPRC2_QPRCRR                           *((volatile uint32_t*)(0x400260BCUL))
#define FM4_QPRC2_QPRCRR                          *((volatile uint32_t*)(0x400260BCUL))

/*******************************************************************************
* QPRC_NF Registers QPRC2_NF
*   Register Definition
*******************************************************************************/
#define FM_QPRC2_NF_NFCTLA                        *((volatile  uint8_t*)(0x40026120UL))
#define FM4_QPRC2_NF_NFCTLA                       *((volatile  uint8_t*)(0x40026120UL))
#define FM_QPRC2_NF_NFCTLB                        *((volatile  uint8_t*)(0x40026124UL))
#define FM4_QPRC2_NF_NFCTLB                       *((volatile  uint8_t*)(0x40026124UL))
#define FM_QPRC2_NF_NFCTLZ                        *((volatile  uint8_t*)(0x40026128UL))
#define FM4_QPRC2_NF_NFCTLZ                       *((volatile  uint8_t*)(0x40026128UL))

/*******************************************************************************
* QPRC Registers QPRC3
*   Register Definition
*******************************************************************************/
#define FM_QPRC3_QPCR                             *((volatile uint16_t*)(0x400260C0UL))
#define FM4_QPRC3_QPCR                            *((volatile uint16_t*)(0x400260C0UL))
#define FM_QPRC3_QRCR                             *((volatile uint16_t*)(0x400260C4UL))
#define FM4_QPRC3_QRCR                            *((volatile uint16_t*)(0x400260C4UL))
#define FM_QPRC3_QPCCR                            *((volatile uint16_t*)(0x400260C8UL))
#define FM4_QPRC3_QPCCR                           *((volatile uint16_t*)(0x400260C8UL))
#define FM_QPRC3_QPRCR                            *((volatile uint16_t*)(0x400260CCUL))
#define FM4_QPRC3_QPRCR                           *((volatile uint16_t*)(0x400260CCUL))
#define FM_QPRC3_QMPR                             *((volatile uint16_t*)(0x400260D0UL))
#define FM4_QPRC3_QMPR                            *((volatile uint16_t*)(0x400260D0UL))
#define FM_QPRC3_QICRL                            *((volatile  uint8_t*)(0x400260D4UL))
#define FM4_QPRC3_QICRL                           *((volatile  uint8_t*)(0x400260D4UL))
#define FM_QPRC3_QICRH                            *((volatile  uint8_t*)(0x400260D5UL))
#define FM4_QPRC3_QICRH                           *((volatile  uint8_t*)(0x400260D5UL))
#define FM_QPRC3_QCR                              *((volatile uint16_t*)(0x400260D8UL))
#define FM4_QPRC3_QCR                             *((volatile uint16_t*)(0x400260D8UL))
#define FM_QPRC3_QECR                             *((volatile uint16_t*)(0x400260DCUL))
#define FM4_QPRC3_QECR                            *((volatile uint16_t*)(0x400260DCUL))
#define FM_QPRC3_QPRCRR                           *((volatile uint32_t*)(0x400260FCUL))
#define FM4_QPRC3_QPRCRR                          *((volatile uint32_t*)(0x400260FCUL))

/*******************************************************************************
* QPRC_NF Registers QPRC3_NF
*   Register Definition
*******************************************************************************/
#define FM_QPRC3_NF_NFCTLA                        *((volatile  uint8_t*)(0x40026130UL))
#define FM4_QPRC3_NF_NFCTLA                       *((volatile  uint8_t*)(0x40026130UL))
#define FM_QPRC3_NF_NFCTLB                        *((volatile  uint8_t*)(0x40026134UL))
#define FM4_QPRC3_NF_NFCTLB                       *((volatile  uint8_t*)(0x40026134UL))
#define FM_QPRC3_NF_NFCTLZ                        *((volatile  uint8_t*)(0x40026138UL))
#define FM4_QPRC3_NF_NFCTLZ                       *((volatile  uint8_t*)(0x40026138UL))

/*******************************************************************************
* RTC Registers RTC
*   Register Definition
*******************************************************************************/
#define FM_RTC_WTCR10                             *((volatile  uint8_t*)(0x4003B100UL))
#define FM4_RTC_WTCR10                            *((volatile  uint8_t*)(0x4003B100UL))
#define FM_RTC_WTCR11                             *((volatile  uint8_t*)(0x4003B104UL))
#define FM4_RTC_WTCR11                            *((volatile  uint8_t*)(0x4003B104UL))
#define FM_RTC_WTCR12                             *((volatile  uint8_t*)(0x4003B108UL))
#define FM4_RTC_WTCR12                            *((volatile  uint8_t*)(0x4003B108UL))
#define FM_RTC_WTCR13                             *((volatile  uint8_t*)(0x4003B10CUL))
#define FM4_RTC_WTCR13                            *((volatile  uint8_t*)(0x4003B10CUL))
#define FM_RTC_WTCR20                             *((volatile  uint8_t*)(0x4003B110UL))
#define FM4_RTC_WTCR20                            *((volatile  uint8_t*)(0x4003B110UL))
#define FM_RTC_WTCR21                             *((volatile  uint8_t*)(0x4003B114UL))
#define FM4_RTC_WTCR21                            *((volatile  uint8_t*)(0x4003B114UL))
#define FM_RTC_WTSR                               *((volatile  uint8_t*)(0x4003B11CUL))
#define FM4_RTC_WTSR                              *((volatile  uint8_t*)(0x4003B11CUL))
#define FM_RTC_WTMIR                              *((volatile  uint8_t*)(0x4003B120UL))
#define FM4_RTC_WTMIR                             *((volatile  uint8_t*)(0x4003B120UL))
#define FM_RTC_WTHR                               *((volatile  uint8_t*)(0x4003B124UL))
#define FM4_RTC_WTHR                              *((volatile  uint8_t*)(0x4003B124UL))
#define FM_RTC_WTDR                               *((volatile  uint8_t*)(0x4003B128UL))
#define FM4_RTC_WTDR                              *((volatile  uint8_t*)(0x4003B128UL))
#define FM_RTC_WTDW                               *((volatile  uint8_t*)(0x4003B12CUL))
#define FM4_RTC_WTDW                              *((volatile  uint8_t*)(0x4003B12CUL))
#define FM_RTC_WTMOR                              *((volatile  uint8_t*)(0x4003B130UL))
#define FM4_RTC_WTMOR                             *((volatile  uint8_t*)(0x4003B130UL))
#define FM_RTC_WTYR                               *((volatile  uint8_t*)(0x4003B134UL))
#define FM4_RTC_WTYR                              *((volatile  uint8_t*)(0x4003B134UL))
#define FM_RTC_ALMIR                              *((volatile  uint8_t*)(0x4003B138UL))
#define FM4_RTC_ALMIR                             *((volatile  uint8_t*)(0x4003B138UL))
#define FM_RTC_ALHR                               *((volatile  uint8_t*)(0x4003B13CUL))
#define FM4_RTC_ALHR                              *((volatile  uint8_t*)(0x4003B13CUL))
#define FM_RTC_ALDR                               *((volatile  uint8_t*)(0x4003B140UL))
#define FM4_RTC_ALDR                              *((volatile  uint8_t*)(0x4003B140UL))
#define FM_RTC_ALMOR                              *((volatile  uint8_t*)(0x4003B144UL))
#define FM4_RTC_ALMOR                             *((volatile  uint8_t*)(0x4003B144UL))
#define FM_RTC_ALYR                               *((volatile  uint8_t*)(0x4003B148UL))
#define FM4_RTC_ALYR                              *((volatile  uint8_t*)(0x4003B148UL))
#define FM_RTC_WTTR0                              *((volatile  uint8_t*)(0x4003B14CUL))
#define FM4_RTC_WTTR0                             *((volatile  uint8_t*)(0x4003B14CUL))
#define FM_RTC_WTTR1                              *((volatile  uint8_t*)(0x4003B150UL))
#define FM4_RTC_WTTR1                             *((volatile  uint8_t*)(0x4003B150UL))
#define FM_RTC_WTTR2                              *((volatile  uint8_t*)(0x4003B154UL))
#define FM4_RTC_WTTR2                             *((volatile  uint8_t*)(0x4003B154UL))
#define FM_RTC_WTCAL0                             *((volatile  uint8_t*)(0x4003B158UL))
#define FM4_RTC_WTCAL0                            *((volatile  uint8_t*)(0x4003B158UL))
#define FM_RTC_WTCAL1                             *((volatile  uint8_t*)(0x4003B15CUL))
#define FM4_RTC_WTCAL1                            *((volatile  uint8_t*)(0x4003B15CUL))
#define FM_RTC_WTCALEN                            *((volatile  uint8_t*)(0x4003B160UL))
#define FM4_RTC_WTCALEN                           *((volatile  uint8_t*)(0x4003B160UL))
#define FM_RTC_WTDIV                              *((volatile  uint8_t*)(0x4003B164UL))
#define FM4_RTC_WTDIV                             *((volatile  uint8_t*)(0x4003B164UL))
#define FM_RTC_WTDIVEN                            *((volatile  uint8_t*)(0x4003B168UL))
#define FM4_RTC_WTDIVEN                           *((volatile  uint8_t*)(0x4003B168UL))
#define FM_RTC_WTCALPRD                           *((volatile  uint8_t*)(0x4003B16CUL))
#define FM4_RTC_WTCALPRD                          *((volatile  uint8_t*)(0x4003B16CUL))
#define FM_RTC_WTCOSEL                            *((volatile  uint8_t*)(0x4003B170UL))
#define FM4_RTC_WTCOSEL                           *((volatile  uint8_t*)(0x4003B170UL))
#define FM_RTC_VB_CLKDIV                          *((volatile  uint8_t*)(0x4003B174UL))
#define FM4_RTC_VB_CLKDIV                         *((volatile  uint8_t*)(0x4003B174UL))
#define FM_RTC_WTOSCCNT                           *((volatile  uint8_t*)(0x4003B178UL))
#define FM4_RTC_WTOSCCNT                          *((volatile  uint8_t*)(0x4003B178UL))
#define FM_RTC_CCS                                *((volatile  uint8_t*)(0x4003B17CUL))
#define FM4_RTC_CCS                               *((volatile  uint8_t*)(0x4003B17CUL))
#define FM_RTC_CCB                                *((volatile  uint8_t*)(0x4003B180UL))
#define FM4_RTC_CCB                               *((volatile  uint8_t*)(0x4003B180UL))
#define FM_RTC_BOOST                              *((volatile  uint8_t*)(0x4003B188UL))
#define FM4_RTC_BOOST                             *((volatile  uint8_t*)(0x4003B188UL))
#define FM_RTC_EWKUP                              *((volatile  uint8_t*)(0x4003B18CUL))
#define FM4_RTC_EWKUP                             *((volatile  uint8_t*)(0x4003B18CUL))
#define FM_RTC_VDET                               *((volatile  uint8_t*)(0x4003B190UL))
#define FM4_RTC_VDET                              *((volatile  uint8_t*)(0x4003B190UL))
#define FM_RTC_HIBRST                             *((volatile  uint8_t*)(0x4003B198UL))
#define FM4_RTC_HIBRST                            *((volatile  uint8_t*)(0x4003B198UL))
#define FM_RTC_VBPFR                              *((volatile  uint8_t*)(0x4003B19CUL))
#define FM4_RTC_VBPFR                             *((volatile  uint8_t*)(0x4003B19CUL))
#define FM_RTC_VBPCR                              *((volatile  uint8_t*)(0x4003B1A0UL))
#define FM4_RTC_VBPCR                             *((volatile  uint8_t*)(0x4003B1A0UL))
#define FM_RTC_VBDDR                              *((volatile  uint8_t*)(0x4003B1A4UL))
#define FM4_RTC_VBDDR                             *((volatile  uint8_t*)(0x4003B1A4UL))
#define FM_RTC_VBDIR                              *((volatile  uint8_t*)(0x4003B1A8UL))
#define FM4_RTC_VBDIR                             *((volatile  uint8_t*)(0x4003B1A8UL))
#define FM_RTC_VBDOR                              *((volatile  uint8_t*)(0x4003B1ACUL))
#define FM4_RTC_VBDOR                             *((volatile  uint8_t*)(0x4003B1ACUL))
#define FM_RTC_VBPZR                              *((volatile  uint8_t*)(0x4003B1B0UL))
#define FM4_RTC_VBPZR                             *((volatile  uint8_t*)(0x4003B1B0UL))
#define FM_RTC_BREG00                             *((volatile  uint8_t*)(0x4003B200UL))
#define FM4_RTC_BREG00                            *((volatile  uint8_t*)(0x4003B200UL))
#define FM_RTC_BREG01                             *((volatile  uint8_t*)(0x4003B201UL))
#define FM4_RTC_BREG01                            *((volatile  uint8_t*)(0x4003B201UL))
#define FM_RTC_BREG02                             *((volatile  uint8_t*)(0x4003B202UL))
#define FM4_RTC_BREG02                            *((volatile  uint8_t*)(0x4003B202UL))
#define FM_RTC_BREG03                             *((volatile  uint8_t*)(0x4003B203UL))
#define FM4_RTC_BREG03                            *((volatile  uint8_t*)(0x4003B203UL))
#define FM_RTC_BREG04                             *((volatile  uint8_t*)(0x4003B204UL))
#define FM4_RTC_BREG04                            *((volatile  uint8_t*)(0x4003B204UL))
#define FM_RTC_BREG05                             *((volatile  uint8_t*)(0x4003B205UL))
#define FM4_RTC_BREG05                            *((volatile  uint8_t*)(0x4003B205UL))
#define FM_RTC_BREG06                             *((volatile  uint8_t*)(0x4003B206UL))
#define FM4_RTC_BREG06                            *((volatile  uint8_t*)(0x4003B206UL))
#define FM_RTC_BREG07                             *((volatile  uint8_t*)(0x4003B207UL))
#define FM4_RTC_BREG07                            *((volatile  uint8_t*)(0x4003B207UL))
#define FM_RTC_BREG08                             *((volatile  uint8_t*)(0x4003B208UL))
#define FM4_RTC_BREG08                            *((volatile  uint8_t*)(0x4003B208UL))
#define FM_RTC_BREG09                             *((volatile  uint8_t*)(0x4003B209UL))
#define FM4_RTC_BREG09                            *((volatile  uint8_t*)(0x4003B209UL))
#define FM_RTC_BREG0A                             *((volatile  uint8_t*)(0x4003B20AUL))
#define FM4_RTC_BREG0A                            *((volatile  uint8_t*)(0x4003B20AUL))
#define FM_RTC_BREG0B                             *((volatile  uint8_t*)(0x4003B20BUL))
#define FM4_RTC_BREG0B                            *((volatile  uint8_t*)(0x4003B20BUL))
#define FM_RTC_BREG0C                             *((volatile  uint8_t*)(0x4003B20CUL))
#define FM4_RTC_BREG0C                            *((volatile  uint8_t*)(0x4003B20CUL))
#define FM_RTC_BREG0D                             *((volatile  uint8_t*)(0x4003B20DUL))
#define FM4_RTC_BREG0D                            *((volatile  uint8_t*)(0x4003B20DUL))
#define FM_RTC_BREG0E                             *((volatile  uint8_t*)(0x4003B20EUL))
#define FM4_RTC_BREG0E                            *((volatile  uint8_t*)(0x4003B20EUL))
#define FM_RTC_BREG0F                             *((volatile  uint8_t*)(0x4003B20FUL))
#define FM4_RTC_BREG0F                            *((volatile  uint8_t*)(0x4003B20FUL))
#define FM_RTC_BREG10                             *((volatile  uint8_t*)(0x4003B210UL))
#define FM4_RTC_BREG10                            *((volatile  uint8_t*)(0x4003B210UL))
#define FM_RTC_BREG11                             *((volatile  uint8_t*)(0x4003B211UL))
#define FM4_RTC_BREG11                            *((volatile  uint8_t*)(0x4003B211UL))
#define FM_RTC_BREG12                             *((volatile  uint8_t*)(0x4003B212UL))
#define FM4_RTC_BREG12                            *((volatile  uint8_t*)(0x4003B212UL))
#define FM_RTC_BREG13                             *((volatile  uint8_t*)(0x4003B213UL))
#define FM4_RTC_BREG13                            *((volatile  uint8_t*)(0x4003B213UL))
#define FM_RTC_BREG14                             *((volatile  uint8_t*)(0x4003B214UL))
#define FM4_RTC_BREG14                            *((volatile  uint8_t*)(0x4003B214UL))
#define FM_RTC_BREG15                             *((volatile  uint8_t*)(0x4003B215UL))
#define FM4_RTC_BREG15                            *((volatile  uint8_t*)(0x4003B215UL))
#define FM_RTC_BREG16                             *((volatile  uint8_t*)(0x4003B216UL))
#define FM4_RTC_BREG16                            *((volatile  uint8_t*)(0x4003B216UL))
#define FM_RTC_BREG17                             *((volatile  uint8_t*)(0x4003B217UL))
#define FM4_RTC_BREG17                            *((volatile  uint8_t*)(0x4003B217UL))
#define FM_RTC_BREG18                             *((volatile  uint8_t*)(0x4003B218UL))
#define FM4_RTC_BREG18                            *((volatile  uint8_t*)(0x4003B218UL))
#define FM_RTC_BREG19                             *((volatile  uint8_t*)(0x4003B219UL))
#define FM4_RTC_BREG19                            *((volatile  uint8_t*)(0x4003B219UL))
#define FM_RTC_BREG1A                             *((volatile  uint8_t*)(0x4003B21AUL))
#define FM4_RTC_BREG1A                            *((volatile  uint8_t*)(0x4003B21AUL))
#define FM_RTC_BREG1B                             *((volatile  uint8_t*)(0x4003B21BUL))
#define FM4_RTC_BREG1B                            *((volatile  uint8_t*)(0x4003B21BUL))
#define FM_RTC_BREG1C                             *((volatile  uint8_t*)(0x4003B21CUL))
#define FM4_RTC_BREG1C                            *((volatile  uint8_t*)(0x4003B21CUL))
#define FM_RTC_BREG1D                             *((volatile  uint8_t*)(0x4003B21DUL))
#define FM4_RTC_BREG1D                            *((volatile  uint8_t*)(0x4003B21DUL))
#define FM_RTC_BREG1E                             *((volatile  uint8_t*)(0x4003B21EUL))
#define FM4_RTC_BREG1E                            *((volatile  uint8_t*)(0x4003B21EUL))
#define FM_RTC_BREG1F                             *((volatile  uint8_t*)(0x4003B21FUL))
#define FM4_RTC_BREG1F                            *((volatile  uint8_t*)(0x4003B21FUL))
#define FM_RTC_BREG20                             *((volatile  uint8_t*)(0x4003B220UL))
#define FM4_RTC_BREG20                            *((volatile  uint8_t*)(0x4003B220UL))
#define FM_RTC_BREG21                             *((volatile  uint8_t*)(0x4003B221UL))
#define FM4_RTC_BREG21                            *((volatile  uint8_t*)(0x4003B221UL))
#define FM_RTC_BREG22                             *((volatile  uint8_t*)(0x4003B222UL))
#define FM4_RTC_BREG22                            *((volatile  uint8_t*)(0x4003B222UL))
#define FM_RTC_BREG23                             *((volatile  uint8_t*)(0x4003B223UL))
#define FM4_RTC_BREG23                            *((volatile  uint8_t*)(0x4003B223UL))
#define FM_RTC_BREG24                             *((volatile  uint8_t*)(0x4003B224UL))
#define FM4_RTC_BREG24                            *((volatile  uint8_t*)(0x4003B224UL))
#define FM_RTC_BREG25                             *((volatile  uint8_t*)(0x4003B225UL))
#define FM4_RTC_BREG25                            *((volatile  uint8_t*)(0x4003B225UL))
#define FM_RTC_BREG26                             *((volatile  uint8_t*)(0x4003B226UL))
#define FM4_RTC_BREG26                            *((volatile  uint8_t*)(0x4003B226UL))
#define FM_RTC_BREG27                             *((volatile  uint8_t*)(0x4003B227UL))
#define FM4_RTC_BREG27                            *((volatile  uint8_t*)(0x4003B227UL))
#define FM_RTC_BREG28                             *((volatile  uint8_t*)(0x4003B228UL))
#define FM4_RTC_BREG28                            *((volatile  uint8_t*)(0x4003B228UL))
#define FM_RTC_BREG29                             *((volatile  uint8_t*)(0x4003B229UL))
#define FM4_RTC_BREG29                            *((volatile  uint8_t*)(0x4003B229UL))
#define FM_RTC_BREG2A                             *((volatile  uint8_t*)(0x4003B22AUL))
#define FM4_RTC_BREG2A                            *((volatile  uint8_t*)(0x4003B22AUL))
#define FM_RTC_BREG2B                             *((volatile  uint8_t*)(0x4003B22BUL))
#define FM4_RTC_BREG2B                            *((volatile  uint8_t*)(0x4003B22BUL))
#define FM_RTC_BREG2C                             *((volatile  uint8_t*)(0x4003B22CUL))
#define FM4_RTC_BREG2C                            *((volatile  uint8_t*)(0x4003B22CUL))
#define FM_RTC_BREG2D                             *((volatile  uint8_t*)(0x4003B22DUL))
#define FM4_RTC_BREG2D                            *((volatile  uint8_t*)(0x4003B22DUL))
#define FM_RTC_BREG2E                             *((volatile  uint8_t*)(0x4003B22EUL))
#define FM4_RTC_BREG2E                            *((volatile  uint8_t*)(0x4003B22EUL))
#define FM_RTC_BREG2F                             *((volatile  uint8_t*)(0x4003B22FUL))
#define FM4_RTC_BREG2F                            *((volatile  uint8_t*)(0x4003B22FUL))
#define FM_RTC_BREG30                             *((volatile  uint8_t*)(0x4003B230UL))
#define FM4_RTC_BREG30                            *((volatile  uint8_t*)(0x4003B230UL))
#define FM_RTC_BREG31                             *((volatile  uint8_t*)(0x4003B231UL))
#define FM4_RTC_BREG31                            *((volatile  uint8_t*)(0x4003B231UL))
#define FM_RTC_BREG32                             *((volatile  uint8_t*)(0x4003B232UL))
#define FM4_RTC_BREG32                            *((volatile  uint8_t*)(0x4003B232UL))
#define FM_RTC_BREG33                             *((volatile  uint8_t*)(0x4003B233UL))
#define FM4_RTC_BREG33                            *((volatile  uint8_t*)(0x4003B233UL))
#define FM_RTC_BREG34                             *((volatile  uint8_t*)(0x4003B234UL))
#define FM4_RTC_BREG34                            *((volatile  uint8_t*)(0x4003B234UL))
#define FM_RTC_BREG35                             *((volatile  uint8_t*)(0x4003B235UL))
#define FM4_RTC_BREG35                            *((volatile  uint8_t*)(0x4003B235UL))
#define FM_RTC_BREG36                             *((volatile  uint8_t*)(0x4003B236UL))
#define FM4_RTC_BREG36                            *((volatile  uint8_t*)(0x4003B236UL))
#define FM_RTC_BREG37                             *((volatile  uint8_t*)(0x4003B237UL))
#define FM4_RTC_BREG37                            *((volatile  uint8_t*)(0x4003B237UL))
#define FM_RTC_BREG38                             *((volatile  uint8_t*)(0x4003B238UL))
#define FM4_RTC_BREG38                            *((volatile  uint8_t*)(0x4003B238UL))
#define FM_RTC_BREG39                             *((volatile  uint8_t*)(0x4003B239UL))
#define FM4_RTC_BREG39                            *((volatile  uint8_t*)(0x4003B239UL))
#define FM_RTC_BREG3A                             *((volatile  uint8_t*)(0x4003B23AUL))
#define FM4_RTC_BREG3A                            *((volatile  uint8_t*)(0x4003B23AUL))
#define FM_RTC_BREG3B                             *((volatile  uint8_t*)(0x4003B23BUL))
#define FM4_RTC_BREG3B                            *((volatile  uint8_t*)(0x4003B23BUL))
#define FM_RTC_BREG3C                             *((volatile  uint8_t*)(0x4003B23CUL))
#define FM4_RTC_BREG3C                            *((volatile  uint8_t*)(0x4003B23CUL))
#define FM_RTC_BREG3D                             *((volatile  uint8_t*)(0x4003B23DUL))
#define FM4_RTC_BREG3D                            *((volatile  uint8_t*)(0x4003B23DUL))
#define FM_RTC_BREG3E                             *((volatile  uint8_t*)(0x4003B23EUL))
#define FM4_RTC_BREG3E                            *((volatile  uint8_t*)(0x4003B23EUL))
#define FM_RTC_BREG3F                             *((volatile  uint8_t*)(0x4003B23FUL))
#define FM4_RTC_BREG3F                            *((volatile  uint8_t*)(0x4003B23FUL))
#define FM_RTC_BREG40                             *((volatile  uint8_t*)(0x4003B240UL))
#define FM4_RTC_BREG40                            *((volatile  uint8_t*)(0x4003B240UL))
#define FM_RTC_BREG41                             *((volatile  uint8_t*)(0x4003B241UL))
#define FM4_RTC_BREG41                            *((volatile  uint8_t*)(0x4003B241UL))
#define FM_RTC_BREG42                             *((volatile  uint8_t*)(0x4003B242UL))
#define FM4_RTC_BREG42                            *((volatile  uint8_t*)(0x4003B242UL))
#define FM_RTC_BREG43                             *((volatile  uint8_t*)(0x4003B243UL))
#define FM4_RTC_BREG43                            *((volatile  uint8_t*)(0x4003B243UL))
#define FM_RTC_BREG44                             *((volatile  uint8_t*)(0x4003B244UL))
#define FM4_RTC_BREG44                            *((volatile  uint8_t*)(0x4003B244UL))
#define FM_RTC_BREG45                             *((volatile  uint8_t*)(0x4003B245UL))
#define FM4_RTC_BREG45                            *((volatile  uint8_t*)(0x4003B245UL))
#define FM_RTC_BREG46                             *((volatile  uint8_t*)(0x4003B246UL))
#define FM4_RTC_BREG46                            *((volatile  uint8_t*)(0x4003B246UL))
#define FM_RTC_BREG47                             *((volatile  uint8_t*)(0x4003B247UL))
#define FM4_RTC_BREG47                            *((volatile  uint8_t*)(0x4003B247UL))
#define FM_RTC_BREG48                             *((volatile  uint8_t*)(0x4003B248UL))
#define FM4_RTC_BREG48                            *((volatile  uint8_t*)(0x4003B248UL))
#define FM_RTC_BREG49                             *((volatile  uint8_t*)(0x4003B249UL))
#define FM4_RTC_BREG49                            *((volatile  uint8_t*)(0x4003B249UL))
#define FM_RTC_BREG4A                             *((volatile  uint8_t*)(0x4003B24AUL))
#define FM4_RTC_BREG4A                            *((volatile  uint8_t*)(0x4003B24AUL))
#define FM_RTC_BREG4B                             *((volatile  uint8_t*)(0x4003B24BUL))
#define FM4_RTC_BREG4B                            *((volatile  uint8_t*)(0x4003B24BUL))
#define FM_RTC_BREG4C                             *((volatile  uint8_t*)(0x4003B24CUL))
#define FM4_RTC_BREG4C                            *((volatile  uint8_t*)(0x4003B24CUL))
#define FM_RTC_BREG4D                             *((volatile  uint8_t*)(0x4003B24DUL))
#define FM4_RTC_BREG4D                            *((volatile  uint8_t*)(0x4003B24DUL))
#define FM_RTC_BREG4E                             *((volatile  uint8_t*)(0x4003B24EUL))
#define FM4_RTC_BREG4E                            *((volatile  uint8_t*)(0x4003B24EUL))
#define FM_RTC_BREG4F                             *((volatile  uint8_t*)(0x4003B24FUL))
#define FM4_RTC_BREG4F                            *((volatile  uint8_t*)(0x4003B24FUL))
#define FM_RTC_BREG50                             *((volatile  uint8_t*)(0x4003B250UL))
#define FM4_RTC_BREG50                            *((volatile  uint8_t*)(0x4003B250UL))
#define FM_RTC_BREG51                             *((volatile  uint8_t*)(0x4003B251UL))
#define FM4_RTC_BREG51                            *((volatile  uint8_t*)(0x4003B251UL))
#define FM_RTC_BREG52                             *((volatile  uint8_t*)(0x4003B252UL))
#define FM4_RTC_BREG52                            *((volatile  uint8_t*)(0x4003B252UL))
#define FM_RTC_BREG53                             *((volatile  uint8_t*)(0x4003B253UL))
#define FM4_RTC_BREG53                            *((volatile  uint8_t*)(0x4003B253UL))
#define FM_RTC_BREG54                             *((volatile  uint8_t*)(0x4003B254UL))
#define FM4_RTC_BREG54                            *((volatile  uint8_t*)(0x4003B254UL))
#define FM_RTC_BREG55                             *((volatile  uint8_t*)(0x4003B255UL))
#define FM4_RTC_BREG55                            *((volatile  uint8_t*)(0x4003B255UL))
#define FM_RTC_BREG56                             *((volatile  uint8_t*)(0x4003B256UL))
#define FM4_RTC_BREG56                            *((volatile  uint8_t*)(0x4003B256UL))
#define FM_RTC_BREG57                             *((volatile  uint8_t*)(0x4003B257UL))
#define FM4_RTC_BREG57                            *((volatile  uint8_t*)(0x4003B257UL))
#define FM_RTC_BREG58                             *((volatile  uint8_t*)(0x4003B258UL))
#define FM4_RTC_BREG58                            *((volatile  uint8_t*)(0x4003B258UL))
#define FM_RTC_BREG59                             *((volatile  uint8_t*)(0x4003B259UL))
#define FM4_RTC_BREG59                            *((volatile  uint8_t*)(0x4003B259UL))
#define FM_RTC_BREG5A                             *((volatile  uint8_t*)(0x4003B25AUL))
#define FM4_RTC_BREG5A                            *((volatile  uint8_t*)(0x4003B25AUL))
#define FM_RTC_BREG5B                             *((volatile  uint8_t*)(0x4003B25BUL))
#define FM4_RTC_BREG5B                            *((volatile  uint8_t*)(0x4003B25BUL))
#define FM_RTC_BREG5C                             *((volatile  uint8_t*)(0x4003B25CUL))
#define FM4_RTC_BREG5C                            *((volatile  uint8_t*)(0x4003B25CUL))
#define FM_RTC_BREG5D                             *((volatile  uint8_t*)(0x4003B25DUL))
#define FM4_RTC_BREG5D                            *((volatile  uint8_t*)(0x4003B25DUL))
#define FM_RTC_BREG5E                             *((volatile  uint8_t*)(0x4003B25EUL))
#define FM4_RTC_BREG5E                            *((volatile  uint8_t*)(0x4003B25EUL))
#define FM_RTC_BREG5F                             *((volatile  uint8_t*)(0x4003B25FUL))
#define FM4_RTC_BREG5F                            *((volatile  uint8_t*)(0x4003B25FUL))
#define FM_RTC_BREG60                             *((volatile  uint8_t*)(0x4003B260UL))
#define FM4_RTC_BREG60                            *((volatile  uint8_t*)(0x4003B260UL))
#define FM_RTC_BREG61                             *((volatile  uint8_t*)(0x4003B261UL))
#define FM4_RTC_BREG61                            *((volatile  uint8_t*)(0x4003B261UL))
#define FM_RTC_BREG62                             *((volatile  uint8_t*)(0x4003B262UL))
#define FM4_RTC_BREG62                            *((volatile  uint8_t*)(0x4003B262UL))
#define FM_RTC_BREG63                             *((volatile  uint8_t*)(0x4003B263UL))
#define FM4_RTC_BREG63                            *((volatile  uint8_t*)(0x4003B263UL))
#define FM_RTC_BREG64                             *((volatile  uint8_t*)(0x4003B264UL))
#define FM4_RTC_BREG64                            *((volatile  uint8_t*)(0x4003B264UL))
#define FM_RTC_BREG65                             *((volatile  uint8_t*)(0x4003B265UL))
#define FM4_RTC_BREG65                            *((volatile  uint8_t*)(0x4003B265UL))
#define FM_RTC_BREG66                             *((volatile  uint8_t*)(0x4003B266UL))
#define FM4_RTC_BREG66                            *((volatile  uint8_t*)(0x4003B266UL))
#define FM_RTC_BREG67                             *((volatile  uint8_t*)(0x4003B267UL))
#define FM4_RTC_BREG67                            *((volatile  uint8_t*)(0x4003B267UL))
#define FM_RTC_BREG68                             *((volatile  uint8_t*)(0x4003B268UL))
#define FM4_RTC_BREG68                            *((volatile  uint8_t*)(0x4003B268UL))
#define FM_RTC_BREG69                             *((volatile  uint8_t*)(0x4003B269UL))
#define FM4_RTC_BREG69                            *((volatile  uint8_t*)(0x4003B269UL))
#define FM_RTC_BREG6A                             *((volatile  uint8_t*)(0x4003B26AUL))
#define FM4_RTC_BREG6A                            *((volatile  uint8_t*)(0x4003B26AUL))
#define FM_RTC_BREG6B                             *((volatile  uint8_t*)(0x4003B26BUL))
#define FM4_RTC_BREG6B                            *((volatile  uint8_t*)(0x4003B26BUL))
#define FM_RTC_BREG6C                             *((volatile  uint8_t*)(0x4003B26CUL))
#define FM4_RTC_BREG6C                            *((volatile  uint8_t*)(0x4003B26CUL))
#define FM_RTC_BREG6D                             *((volatile  uint8_t*)(0x4003B26DUL))
#define FM4_RTC_BREG6D                            *((volatile  uint8_t*)(0x4003B26DUL))
#define FM_RTC_BREG6E                             *((volatile  uint8_t*)(0x4003B26EUL))
#define FM4_RTC_BREG6E                            *((volatile  uint8_t*)(0x4003B26EUL))
#define FM_RTC_BREG6F                             *((volatile  uint8_t*)(0x4003B26FUL))
#define FM4_RTC_BREG6F                            *((volatile  uint8_t*)(0x4003B26FUL))
#define FM_RTC_BREG70                             *((volatile  uint8_t*)(0x4003B270UL))
#define FM4_RTC_BREG70                            *((volatile  uint8_t*)(0x4003B270UL))
#define FM_RTC_BREG71                             *((volatile  uint8_t*)(0x4003B271UL))
#define FM4_RTC_BREG71                            *((volatile  uint8_t*)(0x4003B271UL))
#define FM_RTC_BREG72                             *((volatile  uint8_t*)(0x4003B272UL))
#define FM4_RTC_BREG72                            *((volatile  uint8_t*)(0x4003B272UL))
#define FM_RTC_BREG73                             *((volatile  uint8_t*)(0x4003B273UL))
#define FM4_RTC_BREG73                            *((volatile  uint8_t*)(0x4003B273UL))
#define FM_RTC_BREG74                             *((volatile  uint8_t*)(0x4003B274UL))
#define FM4_RTC_BREG74                            *((volatile  uint8_t*)(0x4003B274UL))
#define FM_RTC_BREG75                             *((volatile  uint8_t*)(0x4003B275UL))
#define FM4_RTC_BREG75                            *((volatile  uint8_t*)(0x4003B275UL))
#define FM_RTC_BREG76                             *((volatile  uint8_t*)(0x4003B276UL))
#define FM4_RTC_BREG76                            *((volatile  uint8_t*)(0x4003B276UL))
#define FM_RTC_BREG77                             *((volatile  uint8_t*)(0x4003B277UL))
#define FM4_RTC_BREG77                            *((volatile  uint8_t*)(0x4003B277UL))
#define FM_RTC_BREG78                             *((volatile  uint8_t*)(0x4003B278UL))
#define FM4_RTC_BREG78                            *((volatile  uint8_t*)(0x4003B278UL))
#define FM_RTC_BREG79                             *((volatile  uint8_t*)(0x4003B279UL))
#define FM4_RTC_BREG79                            *((volatile  uint8_t*)(0x4003B279UL))
#define FM_RTC_BREG7A                             *((volatile  uint8_t*)(0x4003B27AUL))
#define FM4_RTC_BREG7A                            *((volatile  uint8_t*)(0x4003B27AUL))
#define FM_RTC_BREG7B                             *((volatile  uint8_t*)(0x4003B27BUL))
#define FM4_RTC_BREG7B                            *((volatile  uint8_t*)(0x4003B27BUL))
#define FM_RTC_BREG7C                             *((volatile  uint8_t*)(0x4003B27CUL))
#define FM4_RTC_BREG7C                            *((volatile  uint8_t*)(0x4003B27CUL))
#define FM_RTC_BREG7D                             *((volatile  uint8_t*)(0x4003B27DUL))
#define FM4_RTC_BREG7D                            *((volatile  uint8_t*)(0x4003B27DUL))
#define FM_RTC_BREG7E                             *((volatile  uint8_t*)(0x4003B27EUL))
#define FM4_RTC_BREG7E                            *((volatile  uint8_t*)(0x4003B27EUL))
#define FM_RTC_BREG7F                             *((volatile  uint8_t*)(0x4003B27FUL))
#define FM4_RTC_BREG7F                            *((volatile  uint8_t*)(0x4003B27FUL))

/*******************************************************************************
* SBSSR Registers SBSSR
*   Register Definition
*******************************************************************************/
#define FM_SBSSR_BTSSSR                           *((volatile uint16_t*)(0x40025FFCUL))
#define FM4_SBSSR_BTSSSR                          *((volatile uint16_t*)(0x40025FFCUL))

/*******************************************************************************
* SDIF Registers SDIF
*   Register Definition
*******************************************************************************/
#define FM_SDIF_SSA2                              *((volatile uint32_t*)(0x4006E000UL))
#define FM4_SDIF_SSA2                             *((volatile uint32_t*)(0x4006E000UL))
#define FM_SDIF_SBSIZE                            *((volatile uint16_t*)(0x4006E004UL))
#define FM4_SDIF_SBSIZE                           *((volatile uint16_t*)(0x4006E004UL))
#define FM_SDIF_SBLCNT                            *((volatile uint16_t*)(0x4006E006UL))
#define FM4_SDIF_SBLCNT                           *((volatile uint16_t*)(0x4006E006UL))
#define FM_SDIF_SSA1                              *((volatile uint32_t*)(0x4006E008UL))
#define FM4_SDIF_SSA1                             *((volatile uint32_t*)(0x4006E008UL))
#define FM_SDIF_STRSFMD                           *((volatile uint16_t*)(0x4006E00CUL))
#define FM4_SDIF_STRSFMD                          *((volatile uint16_t*)(0x4006E00CUL))
#define FM_SDIF_SCMMD                             *((volatile uint16_t*)(0x4006E00EUL))
#define FM4_SDIF_SCMMD                            *((volatile uint16_t*)(0x4006E00EUL))
#define FM_SDIF_SRESP0                            *((volatile uint16_t*)(0x4006E010UL))
#define FM4_SDIF_SRESP0                           *((volatile uint16_t*)(0x4006E010UL))
#define FM_SDIF_SRESP1                            *((volatile uint16_t*)(0x4006E012UL))
#define FM4_SDIF_SRESP1                           *((volatile uint16_t*)(0x4006E012UL))
#define FM_SDIF_SRESP2                            *((volatile uint16_t*)(0x4006E014UL))
#define FM4_SDIF_SRESP2                           *((volatile uint16_t*)(0x4006E014UL))
#define FM_SDIF_SRESP3                            *((volatile uint16_t*)(0x4006E016UL))
#define FM4_SDIF_SRESP3                           *((volatile uint16_t*)(0x4006E016UL))
#define FM_SDIF_SRESP4                            *((volatile uint16_t*)(0x4006E018UL))
#define FM4_SDIF_SRESP4                           *((volatile uint16_t*)(0x4006E018UL))
#define FM_SDIF_SRESP5                            *((volatile uint16_t*)(0x4006E01AUL))
#define FM4_SDIF_SRESP5                           *((volatile uint16_t*)(0x4006E01AUL))
#define FM_SDIF_SRESP6                            *((volatile uint16_t*)(0x4006E01CUL))
#define FM4_SDIF_SRESP6                           *((volatile uint16_t*)(0x4006E01CUL))
#define FM_SDIF_SRESP7                            *((volatile uint16_t*)(0x4006E01EUL))
#define FM4_SDIF_SRESP7                           *((volatile uint16_t*)(0x4006E01EUL))
#define FM_SDIF_SBUFDP                            *((volatile uint32_t*)(0x4006E020UL))
#define FM4_SDIF_SBUFDP                           *((volatile uint32_t*)(0x4006E020UL))
#define FM_SDIF_SPRSTAT                           *((volatile uint32_t*)(0x4006E024UL))
#define FM4_SDIF_SPRSTAT                          *((volatile uint32_t*)(0x4006E024UL))
#define FM_SDIF_SHCTL1                            *((volatile  uint8_t*)(0x4006E028UL))
#define FM4_SDIF_SHCTL1                           *((volatile  uint8_t*)(0x4006E028UL))
#define FM_SDIF_SPWRCTL                           *((volatile  uint8_t*)(0x4006E029UL))
#define FM4_SDIF_SPWRCTL                          *((volatile  uint8_t*)(0x4006E029UL))
#define FM_SDIF_SBLKGPCTL                         *((volatile  uint8_t*)(0x4006E02AUL))
#define FM4_SDIF_SBLKGPCTL                        *((volatile  uint8_t*)(0x4006E02AUL))
#define FM_SDIF_SWKUPCTL                          *((volatile  uint8_t*)(0x4006E02BUL))
#define FM4_SDIF_SWKUPCTL                         *((volatile  uint8_t*)(0x4006E02BUL))
#define FM_SDIF_SCLKCTL                           *((volatile uint16_t*)(0x4006E02CUL))
#define FM4_SDIF_SCLKCTL                          *((volatile uint16_t*)(0x4006E02CUL))
#define FM_SDIF_STOCTL                            *((volatile  uint8_t*)(0x4006E02EUL))
#define FM4_SDIF_STOCTL                           *((volatile  uint8_t*)(0x4006E02EUL))
#define FM_SDIF_SSRST                             *((volatile  uint8_t*)(0x4006E02FUL))
#define FM4_SDIF_SSRST                            *((volatile  uint8_t*)(0x4006E02FUL))
#define FM_SDIF_SNINTST                           *((volatile uint16_t*)(0x4006E030UL))
#define FM4_SDIF_SNINTST                          *((volatile uint16_t*)(0x4006E030UL))
#define FM_SDIF_SEINTST                           *((volatile uint16_t*)(0x4006E032UL))
#define FM4_SDIF_SEINTST                          *((volatile uint16_t*)(0x4006E032UL))
#define FM_SDIF_SNINTSTE                          *((volatile uint16_t*)(0x4006E034UL))
#define FM4_SDIF_SNINTSTE                         *((volatile uint16_t*)(0x4006E034UL))
#define FM_SDIF_SEINTSTE                          *((volatile uint16_t*)(0x4006E036UL))
#define FM4_SDIF_SEINTSTE                         *((volatile uint16_t*)(0x4006E036UL))
#define FM_SDIF_SNINTSGE                          *((volatile uint16_t*)(0x4006E038UL))
#define FM4_SDIF_SNINTSGE                         *((volatile uint16_t*)(0x4006E038UL))
#define FM_SDIF_SEINTSGE                          *((volatile uint16_t*)(0x4006E03AUL))
#define FM4_SDIF_SEINTSGE                         *((volatile uint16_t*)(0x4006E03AUL))
#define FM_SDIF_SACMDEST                          *((volatile uint16_t*)(0x4006E03CUL))
#define FM4_SDIF_SACMDEST                         *((volatile uint16_t*)(0x4006E03CUL))
#define FM_SDIF_SHCTL2                            *((volatile uint16_t*)(0x4006E03EUL))
#define FM4_SDIF_SHCTL2                           *((volatile uint16_t*)(0x4006E03EUL))
#define FM_SDIF_CAPBLTY0                          *((volatile uint16_t*)(0x4006E040UL))
#define FM4_SDIF_CAPBLTY0                         *((volatile uint16_t*)(0x4006E040UL))
#define FM_SDIF_CAPBLTY1                          *((volatile uint16_t*)(0x4006E042UL))
#define FM4_SDIF_CAPBLTY1                         *((volatile uint16_t*)(0x4006E042UL))
#define FM_SDIF_CAPBLTY2                          *((volatile uint16_t*)(0x4006E044UL))
#define FM4_SDIF_CAPBLTY2                         *((volatile uint16_t*)(0x4006E044UL))
#define FM_SDIF_CAPBLTY3                          *((volatile uint16_t*)(0x4006E046UL))
#define FM4_SDIF_CAPBLTY3                         *((volatile uint16_t*)(0x4006E046UL))
#define FM_SDIF_MXCCAPY0                          *((volatile uint16_t*)(0x4006E048UL))
#define FM4_SDIF_MXCCAPY0                         *((volatile uint16_t*)(0x4006E048UL))
#define FM_SDIF_MXCCAPY1                          *((volatile uint16_t*)(0x4006E04AUL))
#define FM4_SDIF_MXCCAPY1                         *((volatile uint16_t*)(0x4006E04AUL))
#define FM_SDIF_MXCCAPY2                          *((volatile uint16_t*)(0x4006E04CUL))
#define FM4_SDIF_MXCCAPY2                         *((volatile uint16_t*)(0x4006E04CUL))
#define FM_SDIF_MXCCAPY3                          *((volatile uint16_t*)(0x4006E04EUL))
#define FM4_SDIF_MXCCAPY3                         *((volatile uint16_t*)(0x4006E04EUL))
#define FM_SDIF_FEACEST                           *((volatile uint16_t*)(0x4006E050UL))
#define FM4_SDIF_FEACEST                          *((volatile uint16_t*)(0x4006E050UL))
#define FM_SDIF_SFEEIST                           *((volatile uint16_t*)(0x4006E052UL))
#define FM4_SDIF_SFEEIST                          *((volatile uint16_t*)(0x4006E052UL))
#define FM_SDIF_ADMAEST                           *((volatile  uint8_t*)(0x4006E054UL))
#define FM4_SDIF_ADMAEST                          *((volatile  uint8_t*)(0x4006E054UL))
#define FM_SDIF_SADSA0                            *((volatile uint16_t*)(0x4006E058UL))
#define FM4_SDIF_SADSA0                           *((volatile uint16_t*)(0x4006E058UL))
#define FM_SDIF_SADSA1                            *((volatile uint16_t*)(0x4006E05AUL))
#define FM4_SDIF_SADSA1                           *((volatile uint16_t*)(0x4006E05AUL))
#define FM_SDIF_SADSA2                            *((volatile uint16_t*)(0x4006E05CUL))
#define FM4_SDIF_SADSA2                           *((volatile uint16_t*)(0x4006E05CUL))
#define FM_SDIF_SADSA3                            *((volatile uint16_t*)(0x4006E05EUL))
#define FM4_SDIF_SADSA3                           *((volatile uint16_t*)(0x4006E05EUL))
#define FM_SDIF_SPRVAL0                           *((volatile uint16_t*)(0x4006E060UL))
#define FM4_SDIF_SPRVAL0                          *((volatile uint16_t*)(0x4006E060UL))
#define FM_SDIF_SPRVAL1                           *((volatile uint16_t*)(0x4006E062UL))
#define FM4_SDIF_SPRVAL1                          *((volatile uint16_t*)(0x4006E062UL))
#define FM_SDIF_SPRVAL2                           *((volatile uint16_t*)(0x4006E064UL))
#define FM4_SDIF_SPRVAL2                          *((volatile uint16_t*)(0x4006E064UL))
#define FM_SDIF_SPRVAL3                           *((volatile uint16_t*)(0x4006E066UL))
#define FM4_SDIF_SPRVAL3                          *((volatile uint16_t*)(0x4006E066UL))
#define FM_SDIF_SPRVAL4                           *((volatile uint16_t*)(0x4006E068UL))
#define FM4_SDIF_SPRVAL4                          *((volatile uint16_t*)(0x4006E068UL))
#define FM_SDIF_SPRVAL5                           *((volatile uint16_t*)(0x4006E06AUL))
#define FM4_SDIF_SPRVAL5                          *((volatile uint16_t*)(0x4006E06AUL))
#define FM_SDIF_SPRVAL6                           *((volatile uint16_t*)(0x4006E06CUL))
#define FM4_SDIF_SPRVAL6                          *((volatile uint16_t*)(0x4006E06CUL))
#define FM_SDIF_SPRVAL7                           *((volatile uint16_t*)(0x4006E06EUL))
#define FM4_SDIF_SPRVAL7                          *((volatile uint16_t*)(0x4006E06EUL))
#define FM_SDIF_SSHBCTLL                          *((volatile uint16_t*)(0x4006E0E0UL))
#define FM4_SDIF_SSHBCTLL                         *((volatile uint16_t*)(0x4006E0E0UL))
#define FM_SDIF_SSHBCTLH                          *((volatile uint16_t*)(0x4006E0E2UL))
#define FM4_SDIF_SSHBCTLH                         *((volatile uint16_t*)(0x4006E0E2UL))
#define FM_SDIF_SSLIST                            *((volatile uint16_t*)(0x4006E0FCUL))
#define FM4_SDIF_SSLIST                           *((volatile uint16_t*)(0x4006E0FCUL))
#define FM_SDIF_SHCTLV                            *((volatile uint16_t*)(0x4006E0FEUL))
#define FM4_SDIF_SHCTLV                           *((volatile uint16_t*)(0x4006E0FEUL))
#define FM_SDIF_AHBCFGL                           *((volatile uint16_t*)(0x4006E100UL))
#define FM4_SDIF_AHBCFGL                          *((volatile uint16_t*)(0x4006E100UL))
#define FM_SDIF_AHBCFGH                           *((volatile uint16_t*)(0x4006E102UL))
#define FM4_SDIF_AHBCFGH                          *((volatile uint16_t*)(0x4006E102UL))
#define FM_SDIF_SPWSWCL                           *((volatile uint16_t*)(0x4006E104UL))
#define FM4_SDIF_SPWSWCL                          *((volatile uint16_t*)(0x4006E104UL))
#define FM_SDIF_SPWSWCH                           *((volatile uint16_t*)(0x4006E106UL))
#define FM4_SDIF_SPWSWCH                          *((volatile uint16_t*)(0x4006E106UL))
#define FM_SDIF_STUNSETL                          *((volatile uint16_t*)(0x4006E108UL))
#define FM4_SDIF_STUNSETL                         *((volatile uint16_t*)(0x4006E108UL))
#define FM_SDIF_STUNSETH                          *((volatile uint16_t*)(0x4006E10AUL))
#define FM4_SDIF_STUNSETH                         *((volatile uint16_t*)(0x4006E10AUL))
#define FM_SDIF_STUNSTL                           *((volatile uint16_t*)(0x4006E10CUL))
#define FM4_SDIF_STUNSTL                          *((volatile uint16_t*)(0x4006E10CUL))
#define FM_SDIF_STUNSTH                           *((volatile uint16_t*)(0x4006E10EUL))
#define FM4_SDIF_STUNSTH                          *((volatile uint16_t*)(0x4006E10EUL))
#define FM_SDIF_PSWISTL                           *((volatile uint16_t*)(0x4006E118UL))
#define FM4_SDIF_PSWISTL                          *((volatile uint16_t*)(0x4006E118UL))
#define FM_SDIF_PSWISTH                           *((volatile uint16_t*)(0x4006E11AUL))
#define FM4_SDIF_PSWISTH                          *((volatile uint16_t*)(0x4006E11AUL))
#define FM_SDIF_PSWISTEL                          *((volatile uint16_t*)(0x4006E11CUL))
#define FM4_SDIF_PSWISTEL                         *((volatile uint16_t*)(0x4006E11CUL))
#define FM_SDIF_PSWISTEH                          *((volatile uint16_t*)(0x4006E11EUL))
#define FM4_SDIF_PSWISTEH                         *((volatile uint16_t*)(0x4006E11EUL))
#define FM_SDIF_PSWISGEL                          *((volatile uint16_t*)(0x4006E120UL))
#define FM4_SDIF_PSWISGEL                         *((volatile uint16_t*)(0x4006E120UL))
#define FM_SDIF_PSWISGEH                          *((volatile uint16_t*)(0x4006E122UL))
#define FM4_SDIF_PSWISGEH                         *((volatile uint16_t*)(0x4006E122UL))
#define FM_SDIF_MMCSDCL                           *((volatile uint16_t*)(0x4006E124UL))
#define FM4_SDIF_MMCSDCL                          *((volatile uint16_t*)(0x4006E124UL))
#define FM_SDIF_MMCSDCH                           *((volatile uint16_t*)(0x4006E126UL))
#define FM4_SDIF_MMCSDCH                          *((volatile uint16_t*)(0x4006E126UL))
#define FM_SDIF_MCWIRQC0                          *((volatile uint16_t*)(0x4006E128UL))
#define FM4_SDIF_MCWIRQC0                         *((volatile uint16_t*)(0x4006E128UL))
#define FM_SDIF_MCWIRQC1                          *((volatile uint16_t*)(0x4006E12AUL))
#define FM4_SDIF_MCWIRQC1                         *((volatile uint16_t*)(0x4006E12AUL))
#define FM_SDIF_MCWIRQC2                          *((volatile uint16_t*)(0x4006E12CUL))
#define FM4_SDIF_MCWIRQC2                         *((volatile uint16_t*)(0x4006E12CUL))
#define FM_SDIF_MCWIRQC3                          *((volatile uint16_t*)(0x4006E12EUL))
#define FM4_SDIF_MCWIRQC3                         *((volatile uint16_t*)(0x4006E12EUL))
#define FM_SDIF_MCRPCKBL                          *((volatile uint16_t*)(0x4006E130UL))
#define FM4_SDIF_MCRPCKBL                         *((volatile uint16_t*)(0x4006E130UL))
#define FM_SDIF_MCRPCKBH                          *((volatile uint16_t*)(0x4006E132UL))
#define FM4_SDIF_MCRPCKBH                         *((volatile uint16_t*)(0x4006E132UL))
#define FM_SDIF_SCDETECS                          *((volatile uint16_t*)(0x4006E154UL))
#define FM4_SDIF_SCDETECS                         *((volatile uint16_t*)(0x4006E154UL))

/*******************************************************************************
* SWWDT Registers SWWDT
*   Register Definition
*******************************************************************************/
#define FM_SWWDT_WDOGLOAD                         *((volatile uint32_t*)(0x40012000UL))
#define FM4_SWWDT_WDOGLOAD                        *((volatile uint32_t*)(0x40012000UL))
#define FM_SWWDT_WDOGVALUE                        *((volatile uint32_t*)(0x40012004UL))
#define FM4_SWWDT_WDOGVALUE                       *((volatile uint32_t*)(0x40012004UL))
#define FM_SWWDT_WDOGCONTROL                      *((volatile uint32_t*)(0x40012008UL))
#define FM4_SWWDT_WDOGCONTROL                     *((volatile uint32_t*)(0x40012008UL))
#define FM_SWWDT_WDOGINTCLR                       *((volatile uint32_t*)(0x4001200CUL))
#define FM4_SWWDT_WDOGINTCLR                      *((volatile uint32_t*)(0x4001200CUL))
#define FM_SWWDT_WDOGRIS                          *((volatile uint32_t*)(0x40012010UL))
#define FM4_SWWDT_WDOGRIS                         *((volatile uint32_t*)(0x40012010UL))
#define FM_SWWDT_WDOGSPMC                         *((volatile uint32_t*)(0x40012018UL))
#define FM4_SWWDT_WDOGSPMC                        *((volatile uint32_t*)(0x40012018UL))
#define FM_SWWDT_WDOGLOCK                         *((volatile uint32_t*)(0x40012C00UL))
#define FM4_SWWDT_WDOGLOCK                        *((volatile uint32_t*)(0x40012C00UL))

/*******************************************************************************
* UNIQUE_ID Registers UNIQUE_ID
*   Register Definition
*******************************************************************************/
#define FM_UNIQUE_ID_UIDR0                        *((volatile uint32_t*)(0x40000200UL))
#define FM4_UNIQUE_ID_UIDR0                       *((volatile uint32_t*)(0x40000200UL))
#define FM_UNIQUE_ID_UIDR1                        *((volatile uint32_t*)(0x40000204UL))
#define FM4_UNIQUE_ID_UIDR1                       *((volatile uint32_t*)(0x40000204UL))

/*******************************************************************************
* USB Registers USB0
*   Register Definition
*******************************************************************************/
#define FM_USB0_HCNT                              *((volatile uint16_t*)(0x40042100UL))
#define FM4_USB0_HCNT                             *((volatile uint16_t*)(0x40042100UL))
#define FM_USB0_HIRQ                              *((volatile  uint8_t*)(0x40042104UL))
#define FM4_USB0_HIRQ                             *((volatile  uint8_t*)(0x40042104UL))
#define FM_USB0_HERR                              *((volatile  uint8_t*)(0x40042105UL))
#define FM4_USB0_HERR                             *((volatile  uint8_t*)(0x40042105UL))
#define FM_USB0_HSTATE                            *((volatile  uint8_t*)(0x40042108UL))
#define FM4_USB0_HSTATE                           *((volatile  uint8_t*)(0x40042108UL))
#define FM_USB0_HFCOMP                            *((volatile  uint8_t*)(0x40042109UL))
#define FM4_USB0_HFCOMP                           *((volatile  uint8_t*)(0x40042109UL))
#define FM_USB0_HRTIMER                           *((volatile uint16_t*)(0x4004210CUL))
#define FM4_USB0_HRTIMER                          *((volatile uint16_t*)(0x4004210CUL))
#define FM_USB0_HRTIMER2                          *((volatile  uint8_t*)(0x40042110UL))
#define FM4_USB0_HRTIMER2                         *((volatile  uint8_t*)(0x40042110UL))
#define FM_USB0_HADR                              *((volatile  uint8_t*)(0x40042111UL))
#define FM4_USB0_HADR                             *((volatile  uint8_t*)(0x40042111UL))
#define FM_USB0_HEOF                              *((volatile uint16_t*)(0x40042114UL))
#define FM4_USB0_HEOF                             *((volatile uint16_t*)(0x40042114UL))
#define FM_USB0_HFRAME                            *((volatile uint16_t*)(0x40042118UL))
#define FM4_USB0_HFRAME                           *((volatile uint16_t*)(0x40042118UL))
#define FM_USB0_HTOKEN                            *((volatile  uint8_t*)(0x4004211CUL))
#define FM4_USB0_HTOKEN                           *((volatile  uint8_t*)(0x4004211CUL))
#define FM_USB0_UDCC                              *((volatile uint16_t*)(0x40042120UL))
#define FM4_USB0_UDCC                             *((volatile uint16_t*)(0x40042120UL))
#define FM_USB0_EP0C                              *((volatile uint16_t*)(0x40042124UL))
#define FM4_USB0_EP0C                             *((volatile uint16_t*)(0x40042124UL))
#define FM_USB0_EP1C                              *((volatile uint16_t*)(0x40042128UL))
#define FM4_USB0_EP1C                             *((volatile uint16_t*)(0x40042128UL))
#define FM_USB0_EP2C                              *((volatile uint16_t*)(0x4004212CUL))
#define FM4_USB0_EP2C                             *((volatile uint16_t*)(0x4004212CUL))
#define FM_USB0_EP3C                              *((volatile uint16_t*)(0x40042130UL))
#define FM4_USB0_EP3C                             *((volatile uint16_t*)(0x40042130UL))
#define FM_USB0_EP4C                              *((volatile uint16_t*)(0x40042134UL))
#define FM4_USB0_EP4C                             *((volatile uint16_t*)(0x40042134UL))
#define FM_USB0_EP5C                              *((volatile uint16_t*)(0x40042138UL))
#define FM4_USB0_EP5C                             *((volatile uint16_t*)(0x40042138UL))
#define FM_USB0_TMSP                              *((volatile uint16_t*)(0x4004213CUL))
#define FM4_USB0_TMSP                             *((volatile uint16_t*)(0x4004213CUL))
#define FM_USB0_UDCS                              *((volatile  uint8_t*)(0x40042140UL))
#define FM4_USB0_UDCS                             *((volatile  uint8_t*)(0x40042140UL))
#define FM_USB0_UDCIE                             *((volatile  uint8_t*)(0x40042141UL))
#define FM4_USB0_UDCIE                            *((volatile  uint8_t*)(0x40042141UL))
#define FM_USB0_EP0IS                             *((volatile uint16_t*)(0x40042144UL))
#define FM4_USB0_EP0IS                            *((volatile uint16_t*)(0x40042144UL))
#define FM_USB0_EP0OS                             *((volatile uint16_t*)(0x40042148UL))
#define FM4_USB0_EP0OS                            *((volatile uint16_t*)(0x40042148UL))
#define FM_USB0_EP1S                              *((volatile uint16_t*)(0x4004214CUL))
#define FM4_USB0_EP1S                             *((volatile uint16_t*)(0x4004214CUL))
#define FM_USB0_EP2S                              *((volatile uint16_t*)(0x40042150UL))
#define FM4_USB0_EP2S                             *((volatile uint16_t*)(0x40042150UL))
#define FM_USB0_EP3S                              *((volatile uint16_t*)(0x40042154UL))
#define FM4_USB0_EP3S                             *((volatile uint16_t*)(0x40042154UL))
#define FM_USB0_EP4S                              *((volatile uint16_t*)(0x40042158UL))
#define FM4_USB0_EP4S                             *((volatile uint16_t*)(0x40042158UL))
#define FM_USB0_EP5S                              *((volatile uint16_t*)(0x4004215CUL))
#define FM4_USB0_EP5S                             *((volatile uint16_t*)(0x4004215CUL))
#define FM_USB0_EP0DT                             *((volatile uint16_t*)(0x40042160UL))
#define FM4_USB0_EP0DT                            *((volatile uint16_t*)(0x40042160UL))
#define FM_USB0_EP1DT                             *((volatile uint16_t*)(0x40042164UL))
#define FM4_USB0_EP1DT                            *((volatile uint16_t*)(0x40042164UL))
#define FM_USB0_EP2DT                             *((volatile uint16_t*)(0x40042168UL))
#define FM4_USB0_EP2DT                            *((volatile uint16_t*)(0x40042168UL))
#define FM_USB0_EP3DT                             *((volatile uint16_t*)(0x4004216CUL))
#define FM4_USB0_EP3DT                            *((volatile uint16_t*)(0x4004216CUL))
#define FM_USB0_EP4DT                             *((volatile uint16_t*)(0x40042170UL))
#define FM4_USB0_EP4DT                            *((volatile uint16_t*)(0x40042170UL))
#define FM_USB0_EP5DT                             *((volatile uint16_t*)(0x40042174UL))
#define FM4_USB0_EP5DT                            *((volatile uint16_t*)(0x40042174UL))

/*******************************************************************************
* USB Registers USB1
*   Register Definition
*******************************************************************************/
#define FM_USB1_HCNT                              *((volatile uint16_t*)(0x40054200UL))
#define FM4_USB1_HCNT                             *((volatile uint16_t*)(0x40054200UL))
#define FM_USB1_HIRQ                              *((volatile  uint8_t*)(0x40054204UL))
#define FM4_USB1_HIRQ                             *((volatile  uint8_t*)(0x40054204UL))
#define FM_USB1_HERR                              *((volatile  uint8_t*)(0x40054205UL))
#define FM4_USB1_HERR                             *((volatile  uint8_t*)(0x40054205UL))
#define FM_USB1_HSTATE                            *((volatile  uint8_t*)(0x40054208UL))
#define FM4_USB1_HSTATE                           *((volatile  uint8_t*)(0x40054208UL))
#define FM_USB1_HFCOMP                            *((volatile  uint8_t*)(0x40054209UL))
#define FM4_USB1_HFCOMP                           *((volatile  uint8_t*)(0x40054209UL))
#define FM_USB1_HRTIMER                           *((volatile uint16_t*)(0x4005420CUL))
#define FM4_USB1_HRTIMER                          *((volatile uint16_t*)(0x4005420CUL))
#define FM_USB1_HRTIMER2                          *((volatile  uint8_t*)(0x40054210UL))
#define FM4_USB1_HRTIMER2                         *((volatile  uint8_t*)(0x40054210UL))
#define FM_USB1_HADR                              *((volatile  uint8_t*)(0x40054211UL))
#define FM4_USB1_HADR                             *((volatile  uint8_t*)(0x40054211UL))
#define FM_USB1_HEOF                              *((volatile uint16_t*)(0x40054214UL))
#define FM4_USB1_HEOF                             *((volatile uint16_t*)(0x40054214UL))
#define FM_USB1_HFRAME                            *((volatile uint16_t*)(0x40054218UL))
#define FM4_USB1_HFRAME                           *((volatile uint16_t*)(0x40054218UL))
#define FM_USB1_HTOKEN                            *((volatile  uint8_t*)(0x4005421CUL))
#define FM4_USB1_HTOKEN                           *((volatile  uint8_t*)(0x4005421CUL))
#define FM_USB1_UDCC                              *((volatile uint16_t*)(0x40054220UL))
#define FM4_USB1_UDCC                             *((volatile uint16_t*)(0x40054220UL))
#define FM_USB1_EP0C                              *((volatile uint16_t*)(0x40054224UL))
#define FM4_USB1_EP0C                             *((volatile uint16_t*)(0x40054224UL))
#define FM_USB1_EP1C                              *((volatile uint16_t*)(0x40054228UL))
#define FM4_USB1_EP1C                             *((volatile uint16_t*)(0x40054228UL))
#define FM_USB1_EP2C                              *((volatile uint16_t*)(0x4005422CUL))
#define FM4_USB1_EP2C                             *((volatile uint16_t*)(0x4005422CUL))
#define FM_USB1_EP3C                              *((volatile uint16_t*)(0x40054230UL))
#define FM4_USB1_EP3C                             *((volatile uint16_t*)(0x40054230UL))
#define FM_USB1_EP4C                              *((volatile uint16_t*)(0x40054234UL))
#define FM4_USB1_EP4C                             *((volatile uint16_t*)(0x40054234UL))
#define FM_USB1_EP5C                              *((volatile uint16_t*)(0x40054238UL))
#define FM4_USB1_EP5C                             *((volatile uint16_t*)(0x40054238UL))
#define FM_USB1_TMSP                              *((volatile uint16_t*)(0x4005423CUL))
#define FM4_USB1_TMSP                             *((volatile uint16_t*)(0x4005423CUL))
#define FM_USB1_UDCS                              *((volatile  uint8_t*)(0x40054240UL))
#define FM4_USB1_UDCS                             *((volatile  uint8_t*)(0x40054240UL))
#define FM_USB1_UDCIE                             *((volatile  uint8_t*)(0x40054241UL))
#define FM4_USB1_UDCIE                            *((volatile  uint8_t*)(0x40054241UL))
#define FM_USB1_EP0IS                             *((volatile uint16_t*)(0x40054244UL))
#define FM4_USB1_EP0IS                            *((volatile uint16_t*)(0x40054244UL))
#define FM_USB1_EP0OS                             *((volatile uint16_t*)(0x40054248UL))
#define FM4_USB1_EP0OS                            *((volatile uint16_t*)(0x40054248UL))
#define FM_USB1_EP1S                              *((volatile uint16_t*)(0x4005424CUL))
#define FM4_USB1_EP1S                             *((volatile uint16_t*)(0x4005424CUL))
#define FM_USB1_EP2S                              *((volatile uint16_t*)(0x40054250UL))
#define FM4_USB1_EP2S                             *((volatile uint16_t*)(0x40054250UL))
#define FM_USB1_EP3S                              *((volatile uint16_t*)(0x40054254UL))
#define FM4_USB1_EP3S                             *((volatile uint16_t*)(0x40054254UL))
#define FM_USB1_EP4S                              *((volatile uint16_t*)(0x40054258UL))
#define FM4_USB1_EP4S                             *((volatile uint16_t*)(0x40054258UL))
#define FM_USB1_EP5S                              *((volatile uint16_t*)(0x4005425CUL))
#define FM4_USB1_EP5S                             *((volatile uint16_t*)(0x4005425CUL))
#define FM_USB1_EP0DT                             *((volatile uint16_t*)(0x40054260UL))
#define FM4_USB1_EP0DT                            *((volatile uint16_t*)(0x40054260UL))
#define FM_USB1_EP1DT                             *((volatile uint16_t*)(0x40054264UL))
#define FM4_USB1_EP1DT                            *((volatile uint16_t*)(0x40054264UL))
#define FM_USB1_EP2DT                             *((volatile uint16_t*)(0x40054268UL))
#define FM4_USB1_EP2DT                            *((volatile uint16_t*)(0x40054268UL))
#define FM_USB1_EP3DT                             *((volatile uint16_t*)(0x4005426CUL))
#define FM4_USB1_EP3DT                            *((volatile uint16_t*)(0x4005426CUL))
#define FM_USB1_EP4DT                             *((volatile uint16_t*)(0x40054270UL))
#define FM4_USB1_EP4DT                            *((volatile uint16_t*)(0x40054270UL))
#define FM_USB1_EP5DT                             *((volatile uint16_t*)(0x40054274UL))
#define FM4_USB1_EP5DT                            *((volatile uint16_t*)(0x40054274UL))

/*******************************************************************************
* USBETHERCLK Registers USBETHERCLK
*   Register Definition
*******************************************************************************/
#define FM_USBETHERCLK_UCCR                       *((volatile  uint8_t*)(0x40036000UL))
#define FM4_USBETHERCLK_UCCR                      *((volatile  uint8_t*)(0x40036000UL))
#define FM_USBETHERCLK_UPCR1                      *((volatile  uint8_t*)(0x40036004UL))
#define FM4_USBETHERCLK_UPCR1                     *((volatile  uint8_t*)(0x40036004UL))
#define FM_USBETHERCLK_UPCR2                      *((volatile  uint8_t*)(0x40036008UL))
#define FM4_USBETHERCLK_UPCR2                     *((volatile  uint8_t*)(0x40036008UL))
#define FM_USBETHERCLK_UPCR3                      *((volatile  uint8_t*)(0x4003600CUL))
#define FM4_USBETHERCLK_UPCR3                     *((volatile  uint8_t*)(0x4003600CUL))
#define FM_USBETHERCLK_UPCR4                      *((volatile  uint8_t*)(0x40036010UL))
#define FM4_USBETHERCLK_UPCR4                     *((volatile  uint8_t*)(0x40036010UL))
#define FM_USBETHERCLK_UP_STR                     *((volatile  uint8_t*)(0x40036014UL))
#define FM4_USBETHERCLK_UP_STR                    *((volatile  uint8_t*)(0x40036014UL))
#define FM_USBETHERCLK_UPINT_ENR                  *((volatile  uint8_t*)(0x40036018UL))
#define FM4_USBETHERCLK_UPINT_ENR                 *((volatile  uint8_t*)(0x40036018UL))
#define FM_USBETHERCLK_UPINT_CLR                  *((volatile  uint8_t*)(0x4003601CUL))
#define FM4_USBETHERCLK_UPINT_CLR                 *((volatile  uint8_t*)(0x4003601CUL))
#define FM_USBETHERCLK_UPINT_STR                  *((volatile  uint8_t*)(0x40036020UL))
#define FM4_USBETHERCLK_UPINT_STR                 *((volatile  uint8_t*)(0x40036020UL))
#define FM_USBETHERCLK_UPCR5                      *((volatile  uint8_t*)(0x40036024UL))
#define FM4_USBETHERCLK_UPCR5                     *((volatile  uint8_t*)(0x40036024UL))
#define FM_USBETHERCLK_UPCR6                      *((volatile  uint8_t*)(0x40036028UL))
#define FM4_USBETHERCLK_UPCR6                     *((volatile  uint8_t*)(0x40036028UL))
#define FM_USBETHERCLK_UPCR7                      *((volatile  uint8_t*)(0x4003602CUL))
#define FM4_USBETHERCLK_UPCR7                     *((volatile  uint8_t*)(0x4003602CUL))
#define FM_USBETHERCLK_USBEN0                     *((volatile  uint8_t*)(0x40036030UL))
#define FM4_USBETHERCLK_USBEN0                    *((volatile  uint8_t*)(0x40036030UL))
#define FM_USBETHERCLK_USBEN1                     *((volatile  uint8_t*)(0x40036034UL))
#define FM4_USBETHERCLK_USBEN1                    *((volatile  uint8_t*)(0x40036034UL))

/*******************************************************************************
* WC Registers WC
*   Register Definition
*******************************************************************************/
#define FM_WC_WCRD                                *((volatile  uint8_t*)(0x4003A000UL))
#define FM4_WC_WCRD                               *((volatile  uint8_t*)(0x4003A000UL))
#define FM_WC_WCRL                                *((volatile  uint8_t*)(0x4003A001UL))
#define FM4_WC_WCRL                               *((volatile  uint8_t*)(0x4003A001UL))
#define FM_WC_WCCR                                *((volatile  uint8_t*)(0x4003A002UL))
#define FM4_WC_WCCR                               *((volatile  uint8_t*)(0x4003A002UL))
#define FM_WC_CLK_SEL                             *((volatile uint16_t*)(0x4003A010UL))
#define FM4_WC_CLK_SEL                            *((volatile uint16_t*)(0x4003A010UL))
#define FM_WC_CLK_EN                              *((volatile  uint8_t*)(0x4003A014UL))
#define FM4_WC_CLK_EN                             *((volatile  uint8_t*)(0x4003A014UL))

/*******************************************************************************
* Available Registers
*******************************************************************************/
/*******************************************************************************
* ADC0
*******************************************************************************/
#define FM4_ADC_ADCEN_AVAILABLE                   1
#define FM_ADC_ADCEN_AVAILABLE                    1
#define FM4_ADC_ADCR_AVAILABLE                    1
#define FM_ADC_ADCR_AVAILABLE                     1
#define FM4_ADC_ADCT_AVAILABLE                    1
#define FM_ADC_ADCT_AVAILABLE                     1
#define FM4_ADC_ADSR_AVAILABLE                    1
#define FM_ADC_ADSR_AVAILABLE                     1
#define FM4_ADC_ADSS01_AVAILABLE                  1
#define FM_ADC_ADSS01_AVAILABLE                   1
#define FM4_ADC_ADSS23_AVAILABLE                  1
#define FM_ADC_ADSS23_AVAILABLE                   1
#define FM4_ADC_ADST01_AVAILABLE                  1
#define FM_ADC_ADST01_AVAILABLE                   1
#define FM4_ADC_CALSR_AVAILABLE                   1
#define FM_ADC_CALSR_AVAILABLE                    1
#define FM4_ADC_CMPCR_AVAILABLE                   1
#define FM_ADC_CMPCR_AVAILABLE                    1
#define FM4_ADC_CMPD_AVAILABLE                    1
#define FM_ADC_CMPD_AVAILABLE                     1
#define FM4_ADC_PCCR_AVAILABLE                    1
#define FM_ADC_PCCR_AVAILABLE                     1
#define FM4_ADC_PCFD_AVAILABLE                    1
#define FM_ADC_PCFD_AVAILABLE                     1
#define FM4_ADC_PCFD_FDAS1_AVAILABLE              1
#define FM_ADC_PCFD_FDAS1_AVAILABLE               1
#define FM4_ADC_PCIS_AVAILABLE                    1
#define FM_ADC_PCIS_AVAILABLE                     1
#define FM4_ADC_PFNS_AVAILABLE                    1
#define FM_ADC_PFNS_AVAILABLE                     1
#define FM4_ADC_PRTSL_AVAILABLE                   1
#define FM_ADC_PRTSL_AVAILABLE                    1
#define FM4_ADC_SCCR_AVAILABLE                    1
#define FM_ADC_SCCR_AVAILABLE                     1
#define FM4_ADC_SCFD_AVAILABLE                    1
#define FM_ADC_SCFD_AVAILABLE                     1
#define FM4_ADC_SCFD_FDAS1_AVAILABLE              1
#define FM_ADC_SCFD_FDAS1_AVAILABLE               1
#define FM4_ADC_SCIS01_AVAILABLE                  1
#define FM_ADC_SCIS01_AVAILABLE                   1
#define FM4_ADC_SCIS23_AVAILABLE                  1
#define FM_ADC_SCIS23_AVAILABLE                   1
#define FM4_ADC_SCTSL_AVAILABLE                   1
#define FM_ADC_SCTSL_AVAILABLE                    1
#define FM4_ADC_SFNS_AVAILABLE                    1
#define FM_ADC_SFNS_AVAILABLE                     1
#define FM4_ADC_WCMPCR_AVAILABLE                  1
#define FM_ADC_WCMPCR_AVAILABLE                   1
#define FM4_ADC_WCMPDH_AVAILABLE                  1
#define FM_ADC_WCMPDH_AVAILABLE                   1
#define FM4_ADC_WCMPDL_AVAILABLE                  1
#define FM_ADC_WCMPDL_AVAILABLE                   1
#define FM4_ADC_WCMPSR_AVAILABLE                  1
#define FM_ADC_WCMPSR_AVAILABLE                   1
#define FM4_ADC_WCMRCIF_AVAILABLE                 1
#define FM_ADC_WCMRCIF_AVAILABLE                  1
#define FM4_ADC_WCMRCOT_AVAILABLE                 1
#define FM_ADC_WCMRCOT_AVAILABLE                  1
/*******************************************************************************
* BT0
*******************************************************************************/
#define FM4_BT_PPG_PRLH_AVAILABLE                 1
#define FM_BT_PPG_PRLH_AVAILABLE                  1
#define FM4_BT_PPG_PRLL_AVAILABLE                 1
#define FM_BT_PPG_PRLL_AVAILABLE                  1
#define FM4_BT_PPG_STC_AVAILABLE                  1
#define FM_BT_PPG_STC_AVAILABLE                   1
#define FM4_BT_PPG_TMCR_AVAILABLE                 1
#define FM_BT_PPG_TMCR_AVAILABLE                  1
#define FM4_BT_PPG_TMCR2_AVAILABLE                1
#define FM_BT_PPG_TMCR2_AVAILABLE                 1
#define FM4_BT_PPG_TMR_AVAILABLE                  1
#define FM_BT_PPG_TMR_AVAILABLE                   1
#define FM4_BT_PWC_DTBF_AVAILABLE                 1
#define FM_BT_PWC_DTBF_AVAILABLE                  1
#define FM4_BT_PWC_STC_AVAILABLE                  1
#define FM_BT_PWC_STC_AVAILABLE                   1
#define FM4_BT_PWC_TMCR_AVAILABLE                 1
#define FM_BT_PWC_TMCR_AVAILABLE                  1
#define FM4_BT_PWC_TMCR2_AVAILABLE                1
#define FM_BT_PWC_TMCR2_AVAILABLE                 1
#define FM4_BT_PWM_PCSR_AVAILABLE                 1
#define FM_BT_PWM_PCSR_AVAILABLE                  1
#define FM4_BT_PWM_PDUT_AVAILABLE                 1
#define FM_BT_PWM_PDUT_AVAILABLE                  1
#define FM4_BT_PWM_STC_AVAILABLE                  1
#define FM_BT_PWM_STC_AVAILABLE                   1
#define FM4_BT_PWM_TMCR_AVAILABLE                 1
#define FM_BT_PWM_TMCR_AVAILABLE                  1
#define FM4_BT_PWM_TMCR2_AVAILABLE                1
#define FM_BT_PWM_TMCR2_AVAILABLE                 1
#define FM4_BT_PWM_TMR_AVAILABLE                  1
#define FM_BT_PWM_TMR_AVAILABLE                   1
#define FM4_BT_RT_PCSR_AVAILABLE                  1
#define FM_BT_RT_PCSR_AVAILABLE                   1
#define FM4_BT_RT_STC_AVAILABLE                   1
#define FM_BT_RT_STC_AVAILABLE                    1
#define FM4_BT_RT_TMCR_AVAILABLE                  1
#define FM_BT_RT_TMCR_AVAILABLE                   1
#define FM4_BT_RT_TMCR2_AVAILABLE                 1
#define FM_BT_RT_TMCR2_AVAILABLE                  1
#define FM4_BT_RT_TMR_AVAILABLE                   1
#define FM_BT_RT_TMR_AVAILABLE                    1
/*******************************************************************************
* BTIOSEL03
*******************************************************************************/
#define FM4_BTIOSEL03_BTSEL0123_AVAILABLE         1
#define FM_BTIOSEL03_BTSEL0123_AVAILABLE          1
/*******************************************************************************
* BTIOSEL47
*******************************************************************************/
#define FM4_BTIOSEL47_BTSEL4567_AVAILABLE         1
#define FM_BTIOSEL47_BTSEL4567_AVAILABLE          1
/*******************************************************************************
* BTIOSEL8B
*******************************************************************************/
#define FM4_BTIOSEL8B_BTSEL89AB_AVAILABLE         1
#define FM_BTIOSEL8B_BTSEL89AB_AVAILABLE          1
/*******************************************************************************
* BTIOSELCF
*******************************************************************************/
#define FM4_BTIOSELCF_BTSELCDEF_AVAILABLE         1
#define FM_BTIOSELCF_BTSELCDEF_AVAILABLE          1
/*******************************************************************************
* CAN0
*******************************************************************************/
#define FM4_CAN_BRPER_AVAILABLE                   1
#define FM_CAN_BRPER_AVAILABLE                    1
#define FM4_CAN_BTR_AVAILABLE                     1
#define FM_CAN_BTR_AVAILABLE                      1
#define FM4_CAN_CTRLR_AVAILABLE                   1
#define FM_CAN_CTRLR_AVAILABLE                    1
#define FM4_CAN_ERRCNT_AVAILABLE                  1
#define FM_CAN_ERRCNT_AVAILABLE                   1
#define FM4_CAN_IF1ARB_AVAILABLE                  1
#define FM_CAN_IF1ARB_AVAILABLE                   1
#define FM4_CAN_IF1CMSK_AVAILABLE                 1
#define FM_CAN_IF1CMSK_AVAILABLE                  1
#define FM4_CAN_IF1CREQ_AVAILABLE                 1
#define FM_CAN_IF1CREQ_AVAILABLE                  1
#define FM4_CAN_IF1DTA_B_AVAILABLE                1
#define FM_CAN_IF1DTA_B_AVAILABLE                 1
#define FM4_CAN_IF1DTA_L_AVAILABLE                1
#define FM_CAN_IF1DTA_L_AVAILABLE                 1
#define FM4_CAN_IF1DTB_B_AVAILABLE                1
#define FM_CAN_IF1DTB_B_AVAILABLE                 1
#define FM4_CAN_IF1DTB_L_AVAILABLE                1
#define FM_CAN_IF1DTB_L_AVAILABLE                 1
#define FM4_CAN_IF1MCTR_AVAILABLE                 1
#define FM_CAN_IF1MCTR_AVAILABLE                  1
#define FM4_CAN_IF1MSK_AVAILABLE                  1
#define FM_CAN_IF1MSK_AVAILABLE                   1
#define FM4_CAN_IF2ARB_AVAILABLE                  1
#define FM_CAN_IF2ARB_AVAILABLE                   1
#define FM4_CAN_IF2CMSK_AVAILABLE                 1
#define FM_CAN_IF2CMSK_AVAILABLE                  1
#define FM4_CAN_IF2CREQ_AVAILABLE                 1
#define FM_CAN_IF2CREQ_AVAILABLE                  1
#define FM4_CAN_IF2DTA_B_AVAILABLE                1
#define FM_CAN_IF2DTA_B_AVAILABLE                 1
#define FM4_CAN_IF2DTA_L_AVAILABLE                1
#define FM_CAN_IF2DTA_L_AVAILABLE                 1
#define FM4_CAN_IF2DTB_B_AVAILABLE                1
#define FM_CAN_IF2DTB_B_AVAILABLE                 1
#define FM4_CAN_IF2DTB_L_AVAILABLE                1
#define FM_CAN_IF2DTB_L_AVAILABLE                 1
#define FM4_CAN_IF2MCTR_AVAILABLE                 1
#define FM_CAN_IF2MCTR_AVAILABLE                  1
#define FM4_CAN_IF2MSK_AVAILABLE                  1
#define FM_CAN_IF2MSK_AVAILABLE                   1
#define FM4_CAN_INTPND_AVAILABLE                  1
#define FM_CAN_INTPND_AVAILABLE                   1
#define FM4_CAN_INTR_AVAILABLE                    1
#define FM_CAN_INTR_AVAILABLE                     1
#define FM4_CAN_MSGVAL_AVAILABLE                  1
#define FM_CAN_MSGVAL_AVAILABLE                   1
#define FM4_CAN_NEWDT_AVAILABLE                   1
#define FM_CAN_NEWDT_AVAILABLE                    1
#define FM4_CAN_STATR_AVAILABLE                   1
#define FM_CAN_STATR_AVAILABLE                    1
#define FM4_CAN_TESTR_AVAILABLE                   1
#define FM_CAN_TESTR_AVAILABLE                    1
#define FM4_CAN_TREQR_AVAILABLE                   1
#define FM_CAN_TREQR_AVAILABLE                    1
/*******************************************************************************
* CANFD0
*******************************************************************************/
#define FM4_CANFD_BTP_AVAILABLE                   1
#define FM_CANFD_BTP_AVAILABLE                    1
#define FM4_CANFD_CCCR_AVAILABLE                  1
#define FM_CANFD_CCCR_AVAILABLE                   1
#define FM4_CANFD_CREL_AVAILABLE                  1
#define FM_CANFD_CREL_AVAILABLE                   1
#define FM4_CANFD_ECR_AVAILABLE                   1
#define FM_CANFD_ECR_AVAILABLE                    1
#define FM4_CANFD_ENDN_AVAILABLE                  1
#define FM_CANFD_ENDN_AVAILABLE                   1
#define FM4_CANFD_FBTP_AVAILABLE                  1
#define FM_CANFD_FBTP_AVAILABLE                   1
#define FM4_CANFD_FDDEAR_AVAILABLE                1
#define FM_CANFD_FDDEAR_AVAILABLE                 1
#define FM4_CANFD_FDECR_AVAILABLE                 1
#define FM_CANFD_FDECR_AVAILABLE                  1
#define FM4_CANFD_FDESCR_AVAILABLE                1
#define FM_CANFD_FDESCR_AVAILABLE                 1
#define FM4_CANFD_FDESR_AVAILABLE                 1
#define FM_CANFD_FDESR_AVAILABLE                  1
#define FM4_CANFD_FDSEAR_AVAILABLE                1
#define FM_CANFD_FDSEAR_AVAILABLE                 1
#define FM4_CANFD_GFC_AVAILABLE                   1
#define FM_CANFD_GFC_AVAILABLE                    1
#define FM4_CANFD_HPMS_AVAILABLE                  1
#define FM_CANFD_HPMS_AVAILABLE                   1
#define FM4_CANFD_IE_AVAILABLE                    1
#define FM_CANFD_IE_AVAILABLE                     1
#define FM4_CANFD_ILE_AVAILABLE                   1
#define FM_CANFD_ILE_AVAILABLE                    1
#define FM4_CANFD_ILS_AVAILABLE                   1
#define FM_CANFD_ILS_AVAILABLE                    1
#define FM4_CANFD_IR_AVAILABLE                    1
#define FM_CANFD_IR_AVAILABLE                     1
#define FM4_CANFD_NDAT1_AVAILABLE                 1
#define FM_CANFD_NDAT1_AVAILABLE                  1
#define FM4_CANFD_NDAT2_AVAILABLE                 1
#define FM_CANFD_NDAT2_AVAILABLE                  1
#define FM4_CANFD_PSR_AVAILABLE                   1
#define FM_CANFD_PSR_AVAILABLE                    1
#define FM4_CANFD_RWD_AVAILABLE                   1
#define FM_CANFD_RWD_AVAILABLE                    1
#define FM4_CANFD_RXBC_AVAILABLE                  1
#define FM_CANFD_RXBC_AVAILABLE                   1
#define FM4_CANFD_RXESC_AVAILABLE                 1
#define FM_CANFD_RXESC_AVAILABLE                  1
#define FM4_CANFD_RXF0A_AVAILABLE                 1
#define FM_CANFD_RXF0A_AVAILABLE                  1
#define FM4_CANFD_RXF0C_AVAILABLE                 1
#define FM_CANFD_RXF0C_AVAILABLE                  1
#define FM4_CANFD_RXF0S_AVAILABLE                 1
#define FM_CANFD_RXF0S_AVAILABLE                  1
#define FM4_CANFD_RXF1A_AVAILABLE                 1
#define FM_CANFD_RXF1A_AVAILABLE                  1
#define FM4_CANFD_RXF1C_AVAILABLE                 1
#define FM_CANFD_RXF1C_AVAILABLE                  1
#define FM4_CANFD_RXF1S_AVAILABLE                 1
#define FM_CANFD_RXF1S_AVAILABLE                  1
#define FM4_CANFD_SIDFC_AVAILABLE                 1
#define FM_CANFD_SIDFC_AVAILABLE                  1
#define FM4_CANFD_TEST_AVAILABLE                  1
#define FM_CANFD_TEST_AVAILABLE                   1
#define FM4_CANFD_TOCC_AVAILABLE                  1
#define FM_CANFD_TOCC_AVAILABLE                   1
#define FM4_CANFD_TOCV_AVAILABLE                  1
#define FM_CANFD_TOCV_AVAILABLE                   1
#define FM4_CANFD_TSCC_AVAILABLE                  1
#define FM_CANFD_TSCC_AVAILABLE                   1
#define FM4_CANFD_TSCDTR_AVAILABLE                1
#define FM_CANFD_TSCDTR_AVAILABLE                 1
#define FM4_CANFD_TSCNTR_AVAILABLE                1
#define FM_CANFD_TSCNTR_AVAILABLE                 1
#define FM4_CANFD_TSCPCLR_AVAILABLE               1
#define FM_CANFD_TSCPCLR_AVAILABLE                1
#define FM4_CANFD_TSCV_AVAILABLE                  1
#define FM_CANFD_TSCV_AVAILABLE                   1
#define FM4_CANFD_TSDIVR_AVAILABLE                1
#define FM_CANFD_TSDIVR_AVAILABLE                 1
#define FM4_CANFD_TSMDR_AVAILABLE                 1
#define FM_CANFD_TSMDR_AVAILABLE                  1
#define FM4_CANFD_TXBAR_AVAILABLE                 1
#define FM_CANFD_TXBAR_AVAILABLE                  1
#define FM4_CANFD_TXBC_AVAILABLE                  1
#define FM_CANFD_TXBC_AVAILABLE                   1
#define FM4_CANFD_TXBCF_AVAILABLE                 1
#define FM_CANFD_TXBCF_AVAILABLE                  1
#define FM4_CANFD_TXBCIE_AVAILABLE                1
#define FM_CANFD_TXBCIE_AVAILABLE                 1
#define FM4_CANFD_TXBCR_AVAILABLE                 1
#define FM_CANFD_TXBCR_AVAILABLE                  1
#define FM4_CANFD_TXBRP_AVAILABLE                 1
#define FM_CANFD_TXBRP_AVAILABLE                  1
#define FM4_CANFD_TXBTIE_AVAILABLE                1
#define FM_CANFD_TXBTIE_AVAILABLE                 1
#define FM4_CANFD_TXBTO_AVAILABLE                 1
#define FM_CANFD_TXBTO_AVAILABLE                  1
#define FM4_CANFD_TXEFC_AVAILABLE                 1
#define FM_CANFD_TXEFC_AVAILABLE                  1
#define FM4_CANFD_TXESC_AVAILABLE                 1
#define FM_CANFD_TXESC_AVAILABLE                  1
#define FM4_CANFD_TXFA_AVAILABLE                  1
#define FM_CANFD_TXFA_AVAILABLE                   1
#define FM4_CANFD_TXFQS_AVAILABLE                 1
#define FM_CANFD_TXFQS_AVAILABLE                  1
#define FM4_CANFD_TXFS_AVAILABLE                  1
#define FM_CANFD_TXFS_AVAILABLE                   1
#define FM4_CANFD_XIDAM_AVAILABLE                 1
#define FM_CANFD_XIDAM_AVAILABLE                  1
#define FM4_CANFD_XIDFC_AVAILABLE                 1
#define FM_CANFD_XIDFC_AVAILABLE                  1
/*******************************************************************************
* CANPRES
*******************************************************************************/
#define FM4_CANPRES_CANPRE_AVAILABLE              1
#define FM_CANPRES_CANPRE_AVAILABLE               1
/*******************************************************************************
* CLK_GATING
*******************************************************************************/
#define FM4_CLK_GATING_CKEN0_AVAILABLE            1
#define FM_CLK_GATING_CKEN0_AVAILABLE             1
#define FM4_CLK_GATING_CKEN1_AVAILABLE            1
#define FM_CLK_GATING_CKEN1_AVAILABLE             1
#define FM4_CLK_GATING_CKEN2_AVAILABLE            1
#define FM_CLK_GATING_CKEN2_AVAILABLE             1
#define FM4_CLK_GATING_MRST0_AVAILABLE            1
#define FM_CLK_GATING_MRST0_AVAILABLE             1
#define FM4_CLK_GATING_MRST1_AVAILABLE            1
#define FM_CLK_GATING_MRST1_AVAILABLE             1
#define FM4_CLK_GATING_MRST2_AVAILABLE            1
#define FM_CLK_GATING_MRST2_AVAILABLE             1
/*******************************************************************************
* CRC
*******************************************************************************/
#define FM4_CRC_CRCCR_AVAILABLE                   1
#define FM_CRC_CRCCR_AVAILABLE                    1
#define FM4_CRC_CRCIN_AVAILABLE                   1
#define FM_CRC_CRCIN_AVAILABLE                    1
#define FM4_CRC_CRCINIT_AVAILABLE                 1
#define FM_CRC_CRCINIT_AVAILABLE                  1
#define FM4_CRC_CRCR_AVAILABLE                    1
#define FM_CRC_CRCR_AVAILABLE                     1
/*******************************************************************************
* CRG
*******************************************************************************/
#define FM4_CRG_APBC0_PSR_AVAILABLE               1
#define FM_CRG_APBC0_PSR_AVAILABLE                1
#define FM4_CRG_APBC1_PSR_AVAILABLE               1
#define FM_CRG_APBC1_PSR_AVAILABLE                1
#define FM4_CRG_APBC2_PSR_AVAILABLE               1
#define FM_CRG_APBC2_PSR_AVAILABLE                1
#define FM4_CRG_BSC_PSR_AVAILABLE                 1
#define FM_CRG_BSC_PSR_AVAILABLE                  1
#define FM4_CRG_CSV_CTL_AVAILABLE                 1
#define FM_CRG_CSV_CTL_AVAILABLE                  1
#define FM4_CRG_CSV_STR_AVAILABLE                 1
#define FM_CRG_CSV_STR_AVAILABLE                  1
#define FM4_CRG_CSW_TMR_AVAILABLE                 1
#define FM_CRG_CSW_TMR_AVAILABLE                  1
#define FM4_CRG_DBWDT_CTL_AVAILABLE               1
#define FM_CRG_DBWDT_CTL_AVAILABLE                1
#define FM4_CRG_FCSWD_CTL_AVAILABLE               1
#define FM_CRG_FCSWD_CTL_AVAILABLE                1
#define FM4_CRG_FCSWH_CTL_AVAILABLE               1
#define FM_CRG_FCSWH_CTL_AVAILABLE                1
#define FM4_CRG_FCSWL_CTL_AVAILABLE               1
#define FM_CRG_FCSWL_CTL_AVAILABLE                1
#define FM4_CRG_INT_CLR_AVAILABLE                 1
#define FM_CRG_INT_CLR_AVAILABLE                  1
#define FM4_CRG_INT_ENR_AVAILABLE                 1
#define FM_CRG_INT_ENR_AVAILABLE                  1
#define FM4_CRG_INT_STR_AVAILABLE                 1
#define FM_CRG_INT_STR_AVAILABLE                  1
#define FM4_CRG_PLL_CTL1_AVAILABLE                1
#define FM_CRG_PLL_CTL1_AVAILABLE                 1
#define FM4_CRG_PLL_CTL2_AVAILABLE                1
#define FM_CRG_PLL_CTL2_AVAILABLE                 1
#define FM4_CRG_PLLCG_CTL_AVAILABLE               1
#define FM_CRG_PLLCG_CTL_AVAILABLE                1
#define FM4_CRG_PSW_TMR_AVAILABLE                 1
#define FM_CRG_PSW_TMR_AVAILABLE                  1
#define FM4_CRG_RST_STR_AVAILABLE                 1
#define FM_CRG_RST_STR_AVAILABLE                  1
#define FM4_CRG_SCM_CTL_AVAILABLE                 1
#define FM_CRG_SCM_CTL_AVAILABLE                  1
#define FM4_CRG_SCM_STR_AVAILABLE                 1
#define FM_CRG_SCM_STR_AVAILABLE                  1
#define FM4_CRG_STB_CTL_AVAILABLE                 1
#define FM_CRG_STB_CTL_AVAILABLE                  1
#define FM4_CRG_SWC_PSR_AVAILABLE                 1
#define FM_CRG_SWC_PSR_AVAILABLE                  1
#define FM4_CRG_TTC_PSR_AVAILABLE                 1
#define FM_CRG_TTC_PSR_AVAILABLE                  1
/*******************************************************************************
* CRTRIM
*******************************************************************************/
#define FM4_CRTRIM_MCR_FTRM_AVAILABLE             1
#define FM_CRTRIM_MCR_FTRM_AVAILABLE              1
#define FM4_CRTRIM_MCR_PSR_AVAILABLE              1
#define FM_CRTRIM_MCR_PSR_AVAILABLE               1
#define FM4_CRTRIM_MCR_RLR_AVAILABLE              1
#define FM_CRTRIM_MCR_RLR_AVAILABLE               1
#define FM4_CRTRIM_MCR_TTRM_AVAILABLE             1
#define FM_CRTRIM_MCR_TTRM_AVAILABLE              1
/*******************************************************************************
* DAC0
*******************************************************************************/
#define FM4_DAC_DACR_AVAILABLE                    1
#define FM_DAC_DACR_AVAILABLE                     1
#define FM4_DAC_DADR_AVAILABLE                    1
#define FM_DAC_DADR_AVAILABLE                     1
/*******************************************************************************
* DMAC
*******************************************************************************/
#define FM4_DMAC_DMACA0_AVAILABLE                 1
#define FM_DMAC_DMACA0_AVAILABLE                  1
#define FM4_DMAC_DMACA1_AVAILABLE                 1
#define FM_DMAC_DMACA1_AVAILABLE                  1
#define FM4_DMAC_DMACA2_AVAILABLE                 1
#define FM_DMAC_DMACA2_AVAILABLE                  1
#define FM4_DMAC_DMACA3_AVAILABLE                 1
#define FM_DMAC_DMACA3_AVAILABLE                  1
#define FM4_DMAC_DMACA4_AVAILABLE                 1
#define FM_DMAC_DMACA4_AVAILABLE                  1
#define FM4_DMAC_DMACA5_AVAILABLE                 1
#define FM_DMAC_DMACA5_AVAILABLE                  1
#define FM4_DMAC_DMACA6_AVAILABLE                 1
#define FM_DMAC_DMACA6_AVAILABLE                  1
#define FM4_DMAC_DMACA7_AVAILABLE                 1
#define FM_DMAC_DMACA7_AVAILABLE                  1
#define FM4_DMAC_DMACB0_AVAILABLE                 1
#define FM_DMAC_DMACB0_AVAILABLE                  1
#define FM4_DMAC_DMACB1_AVAILABLE                 1
#define FM_DMAC_DMACB1_AVAILABLE                  1
#define FM4_DMAC_DMACB2_AVAILABLE                 1
#define FM_DMAC_DMACB2_AVAILABLE                  1
#define FM4_DMAC_DMACB3_AVAILABLE                 1
#define FM_DMAC_DMACB3_AVAILABLE                  1
#define FM4_DMAC_DMACB4_AVAILABLE                 1
#define FM_DMAC_DMACB4_AVAILABLE                  1
#define FM4_DMAC_DMACB5_AVAILABLE                 1
#define FM_DMAC_DMACB5_AVAILABLE                  1
#define FM4_DMAC_DMACB6_AVAILABLE                 1
#define FM_DMAC_DMACB6_AVAILABLE                  1
#define FM4_DMAC_DMACB7_AVAILABLE                 1
#define FM_DMAC_DMACB7_AVAILABLE                  1
#define FM4_DMAC_DMACDA0_AVAILABLE                1
#define FM_DMAC_DMACDA0_AVAILABLE                 1
#define FM4_DMAC_DMACDA1_AVAILABLE                1
#define FM_DMAC_DMACDA1_AVAILABLE                 1
#define FM4_DMAC_DMACDA2_AVAILABLE                1
#define FM_DMAC_DMACDA2_AVAILABLE                 1
#define FM4_DMAC_DMACDA3_AVAILABLE                1
#define FM_DMAC_DMACDA3_AVAILABLE                 1
#define FM4_DMAC_DMACDA4_AVAILABLE                1
#define FM_DMAC_DMACDA4_AVAILABLE                 1
#define FM4_DMAC_DMACDA5_AVAILABLE                1
#define FM_DMAC_DMACDA5_AVAILABLE                 1
#define FM4_DMAC_DMACDA6_AVAILABLE                1
#define FM_DMAC_DMACDA6_AVAILABLE                 1
#define FM4_DMAC_DMACDA7_AVAILABLE                1
#define FM_DMAC_DMACDA7_AVAILABLE                 1
#define FM4_DMAC_DMACR_AVAILABLE                  1
#define FM_DMAC_DMACR_AVAILABLE                   1
#define FM4_DMAC_DMACSA0_AVAILABLE                1
#define FM_DMAC_DMACSA0_AVAILABLE                 1
#define FM4_DMAC_DMACSA1_AVAILABLE                1
#define FM_DMAC_DMACSA1_AVAILABLE                 1
#define FM4_DMAC_DMACSA2_AVAILABLE                1
#define FM_DMAC_DMACSA2_AVAILABLE                 1
#define FM4_DMAC_DMACSA3_AVAILABLE                1
#define FM_DMAC_DMACSA3_AVAILABLE                 1
#define FM4_DMAC_DMACSA4_AVAILABLE                1
#define FM_DMAC_DMACSA4_AVAILABLE                 1
#define FM4_DMAC_DMACSA5_AVAILABLE                1
#define FM_DMAC_DMACSA5_AVAILABLE                 1
#define FM4_DMAC_DMACSA6_AVAILABLE                1
#define FM_DMAC_DMACSA6_AVAILABLE                 1
#define FM4_DMAC_DMACSA7_AVAILABLE                1
#define FM_DMAC_DMACSA7_AVAILABLE                 1
/*******************************************************************************
* DS
*******************************************************************************/
#define FM4_DS_BUR01_AVAILABLE                    1
#define FM_DS_BUR01_AVAILABLE                     1
#define FM4_DS_BUR02_AVAILABLE                    1
#define FM_DS_BUR02_AVAILABLE                     1
#define FM4_DS_BUR03_AVAILABLE                    1
#define FM_DS_BUR03_AVAILABLE                     1
#define FM4_DS_BUR04_AVAILABLE                    1
#define FM_DS_BUR04_AVAILABLE                     1
#define FM4_DS_BUR05_AVAILABLE                    1
#define FM_DS_BUR05_AVAILABLE                     1
#define FM4_DS_BUR06_AVAILABLE                    1
#define FM_DS_BUR06_AVAILABLE                     1
#define FM4_DS_BUR07_AVAILABLE                    1
#define FM_DS_BUR07_AVAILABLE                     1
#define FM4_DS_BUR08_AVAILABLE                    1
#define FM_DS_BUR08_AVAILABLE                     1
#define FM4_DS_BUR09_AVAILABLE                    1
#define FM_DS_BUR09_AVAILABLE                     1
#define FM4_DS_BUR10_AVAILABLE                    1
#define FM_DS_BUR10_AVAILABLE                     1
#define FM4_DS_BUR11_AVAILABLE                    1
#define FM_DS_BUR11_AVAILABLE                     1
#define FM4_DS_BUR12_AVAILABLE                    1
#define FM_DS_BUR12_AVAILABLE                     1
#define FM4_DS_BUR13_AVAILABLE                    1
#define FM_DS_BUR13_AVAILABLE                     1
#define FM4_DS_BUR14_AVAILABLE                    1
#define FM_DS_BUR14_AVAILABLE                     1
#define FM4_DS_BUR15_AVAILABLE                    1
#define FM_DS_BUR15_AVAILABLE                     1
#define FM4_DS_BUR16_AVAILABLE                    1
#define FM_DS_BUR16_AVAILABLE                     1
#define FM4_DS_DSRAMR_AVAILABLE                   1
#define FM_DS_DSRAMR_AVAILABLE                    1
#define FM4_DS_PMD_CTL_AVAILABLE                  1
#define FM_DS_PMD_CTL_AVAILABLE                   1
#define FM4_DS_RCK_CTL_AVAILABLE                  1
#define FM_DS_RCK_CTL_AVAILABLE                   1
#define FM4_DS_WIER_AVAILABLE                     1
#define FM_DS_WIER_AVAILABLE                      1
#define FM4_DS_WIFSR_AVAILABLE                    1
#define FM_DS_WIFSR_AVAILABLE                     1
#define FM4_DS_WILVR_AVAILABLE                    1
#define FM_DS_WILVR_AVAILABLE                     1
#define FM4_DS_WRFSR_AVAILABLE                    1
#define FM_DS_WRFSR_AVAILABLE                     1
/*******************************************************************************
* DSTC
*******************************************************************************/
#define FM4_DSTC_CFG_AVAILABLE                    1
#define FM_DSTC_CFG_AVAILABLE                     1
#define FM4_DSTC_CMD_AVAILABLE                    1
#define FM_DSTC_CMD_AVAILABLE                     1
#define FM4_DSTC_DESTP_AVAILABLE                  1
#define FM_DSTC_DESTP_AVAILABLE                   1
#define FM4_DSTC_DQMSK0_AVAILABLE                 1
#define FM_DSTC_DQMSK0_AVAILABLE                  1
#define FM4_DSTC_DQMSK1_AVAILABLE                 1
#define FM_DSTC_DQMSK1_AVAILABLE                  1
#define FM4_DSTC_DQMSK2_AVAILABLE                 1
#define FM_DSTC_DQMSK2_AVAILABLE                  1
#define FM4_DSTC_DQMSK3_AVAILABLE                 1
#define FM_DSTC_DQMSK3_AVAILABLE                  1
#define FM4_DSTC_DQMSK4_AVAILABLE                 1
#define FM_DSTC_DQMSK4_AVAILABLE                  1
#define FM4_DSTC_DQMSK5_AVAILABLE                 1
#define FM_DSTC_DQMSK5_AVAILABLE                  1
#define FM4_DSTC_DQMSK6_AVAILABLE                 1
#define FM_DSTC_DQMSK6_AVAILABLE                  1
#define FM4_DSTC_DQMSK7_AVAILABLE                 1
#define FM_DSTC_DQMSK7_AVAILABLE                  1
#define FM4_DSTC_DQMSKCLR0_AVAILABLE              1
#define FM_DSTC_DQMSKCLR0_AVAILABLE               1
#define FM4_DSTC_DQMSKCLR1_AVAILABLE              1
#define FM_DSTC_DQMSKCLR1_AVAILABLE               1
#define FM4_DSTC_DQMSKCLR2_AVAILABLE              1
#define FM_DSTC_DQMSKCLR2_AVAILABLE               1
#define FM4_DSTC_DQMSKCLR3_AVAILABLE              1
#define FM_DSTC_DQMSKCLR3_AVAILABLE               1
#define FM4_DSTC_DQMSKCLR4_AVAILABLE              1
#define FM_DSTC_DQMSKCLR4_AVAILABLE               1
#define FM4_DSTC_DQMSKCLR5_AVAILABLE              1
#define FM_DSTC_DQMSKCLR5_AVAILABLE               1
#define FM4_DSTC_DQMSKCLR6_AVAILABLE              1
#define FM_DSTC_DQMSKCLR6_AVAILABLE               1
#define FM4_DSTC_DQMSKCLR7_AVAILABLE              1
#define FM_DSTC_DQMSKCLR7_AVAILABLE               1
#define FM4_DSTC_DREQENB0_AVAILABLE               1
#define FM_DSTC_DREQENB0_AVAILABLE                1
#define FM4_DSTC_DREQENB1_AVAILABLE               1
#define FM_DSTC_DREQENB1_AVAILABLE                1
#define FM4_DSTC_DREQENB2_AVAILABLE               1
#define FM_DSTC_DREQENB2_AVAILABLE                1
#define FM4_DSTC_DREQENB3_AVAILABLE               1
#define FM_DSTC_DREQENB3_AVAILABLE                1
#define FM4_DSTC_DREQENB4_AVAILABLE               1
#define FM_DSTC_DREQENB4_AVAILABLE                1
#define FM4_DSTC_DREQENB5_AVAILABLE               1
#define FM_DSTC_DREQENB5_AVAILABLE                1
#define FM4_DSTC_DREQENB6_AVAILABLE               1
#define FM_DSTC_DREQENB6_AVAILABLE                1
#define FM4_DSTC_DREQENB7_AVAILABLE               1
#define FM_DSTC_DREQENB7_AVAILABLE                1
#define FM4_DSTC_HWDESP_AVAILABLE                 1
#define FM_DSTC_HWDESP_AVAILABLE                  1
#define FM4_DSTC_HWINT0_AVAILABLE                 1
#define FM_DSTC_HWINT0_AVAILABLE                  1
#define FM4_DSTC_HWINT1_AVAILABLE                 1
#define FM_DSTC_HWINT1_AVAILABLE                  1
#define FM4_DSTC_HWINT2_AVAILABLE                 1
#define FM_DSTC_HWINT2_AVAILABLE                  1
#define FM4_DSTC_HWINT3_AVAILABLE                 1
#define FM_DSTC_HWINT3_AVAILABLE                  1
#define FM4_DSTC_HWINT4_AVAILABLE                 1
#define FM_DSTC_HWINT4_AVAILABLE                  1
#define FM4_DSTC_HWINT5_AVAILABLE                 1
#define FM_DSTC_HWINT5_AVAILABLE                  1
#define FM4_DSTC_HWINT6_AVAILABLE                 1
#define FM_DSTC_HWINT6_AVAILABLE                  1
#define FM4_DSTC_HWINT7_AVAILABLE                 1
#define FM_DSTC_HWINT7_AVAILABLE                  1
#define FM4_DSTC_HWINTCLR0_AVAILABLE              1
#define FM_DSTC_HWINTCLR0_AVAILABLE               1
#define FM4_DSTC_HWINTCLR1_AVAILABLE              1
#define FM_DSTC_HWINTCLR1_AVAILABLE               1
#define FM4_DSTC_HWINTCLR2_AVAILABLE              1
#define FM_DSTC_HWINTCLR2_AVAILABLE               1
#define FM4_DSTC_HWINTCLR3_AVAILABLE              1
#define FM_DSTC_HWINTCLR3_AVAILABLE               1
#define FM4_DSTC_HWINTCLR4_AVAILABLE              1
#define FM_DSTC_HWINTCLR4_AVAILABLE               1
#define FM4_DSTC_HWINTCLR5_AVAILABLE              1
#define FM_DSTC_HWINTCLR5_AVAILABLE               1
#define FM4_DSTC_HWINTCLR6_AVAILABLE              1
#define FM_DSTC_HWINTCLR6_AVAILABLE               1
#define FM4_DSTC_HWINTCLR7_AVAILABLE              1
#define FM_DSTC_HWINTCLR7_AVAILABLE               1
#define FM4_DSTC_MONERS_AVAILABLE                 1
#define FM_DSTC_MONERS_AVAILABLE                  1
#define FM4_DSTC_SWTR_AVAILABLE                   1
#define FM_DSTC_SWTR_AVAILABLE                    1
/*******************************************************************************
* DT
*******************************************************************************/
#define FM4_DT_TIMER1BGLOAD_AVAILABLE             1
#define FM_DT_TIMER1BGLOAD_AVAILABLE              1
#define FM4_DT_TIMER1CONTROL_AVAILABLE            1
#define FM_DT_TIMER1CONTROL_AVAILABLE             1
#define FM4_DT_TIMER1INTCLR_AVAILABLE             1
#define FM_DT_TIMER1INTCLR_AVAILABLE              1
#define FM4_DT_TIMER1LOAD_AVAILABLE               1
#define FM_DT_TIMER1LOAD_AVAILABLE                1
#define FM4_DT_TIMER1MIS_AVAILABLE                1
#define FM_DT_TIMER1MIS_AVAILABLE                 1
#define FM4_DT_TIMER1RIS_AVAILABLE                1
#define FM_DT_TIMER1RIS_AVAILABLE                 1
#define FM4_DT_TIMER1VALUE_AVAILABLE              1
#define FM_DT_TIMER1VALUE_AVAILABLE               1
#define FM4_DT_TIMER2BGLOAD_AVAILABLE             1
#define FM_DT_TIMER2BGLOAD_AVAILABLE              1
#define FM4_DT_TIMER2CONTROL_AVAILABLE            1
#define FM_DT_TIMER2CONTROL_AVAILABLE             1
#define FM4_DT_TIMER2INTCLR_AVAILABLE             1
#define FM_DT_TIMER2INTCLR_AVAILABLE              1
#define FM4_DT_TIMER2LOAD_AVAILABLE               1
#define FM_DT_TIMER2LOAD_AVAILABLE                1
#define FM4_DT_TIMER2MIS_AVAILABLE                1
#define FM_DT_TIMER2MIS_AVAILABLE                 1
#define FM4_DT_TIMER2RIS_AVAILABLE                1
#define FM_DT_TIMER2RIS_AVAILABLE                 1
#define FM4_DT_TIMER2VALUE_AVAILABLE              1
#define FM_DT_TIMER2VALUE_AVAILABLE               1
/*******************************************************************************
* DUALFLASH_IF
*******************************************************************************/
#define FM4_DUALFLASH_IF_DFASZR_AVAILABLE         1
#define FM_DUALFLASH_IF_DFASZR_AVAILABLE          1
#define FM4_DUALFLASH_IF_DFRWTR_AVAILABLE         1
#define FM_DUALFLASH_IF_DFRWTR_AVAILABLE          1
#define FM4_DUALFLASH_IF_DFSTR_AVAILABLE          1
#define FM_DUALFLASH_IF_DFSTR_AVAILABLE           1
/*******************************************************************************
* ECC_CAPTURE
*******************************************************************************/
#define FM4_ECC_CAPTURE_FERRAD_AVAILABLE          1
#define FM_ECC_CAPTURE_FERRAD_AVAILABLE           1
/*******************************************************************************
* ETHERNET_CONTROL
*******************************************************************************/
#define FM4_ETHERNET_CONTROL_ETH_CLKG_AVAILABLE   1
#define FM_ETHERNET_CONTROL_ETH_CLKG_AVAILABLE    1
#define FM4_ETHERNET_CONTROL_ETH_MODE_AVAILABLE   1
#define FM_ETHERNET_CONTROL_ETH_MODE_AVAILABLE    1
/*******************************************************************************
* ETHERNET_MAC0
*******************************************************************************/
#define FM4_ETHERNET_MAC_AHBSR_AVAILABLE          1
#define FM_ETHERNET_MAC_AHBSR_AVAILABLE           1
#define FM4_ETHERNET_MAC_ATNR_AVAILABLE           1
#define FM_ETHERNET_MAC_ATNR_AVAILABLE            1
#define FM4_ETHERNET_MAC_ATSR_AVAILABLE           1
#define FM_ETHERNET_MAC_ATSR_AVAILABLE            1
#define FM4_ETHERNET_MAC_BMR_AVAILABLE            1
#define FM_ETHERNET_MAC_BMR_AVAILABLE             1
#define FM4_ETHERNET_MAC_CHRBAR_AVAILABLE         1
#define FM_ETHERNET_MAC_CHRBAR_AVAILABLE          1
#define FM4_ETHERNET_MAC_CHRDR_AVAILABLE          1
#define FM_ETHERNET_MAC_CHRDR_AVAILABLE           1
#define FM4_ETHERNET_MAC_CHTBAR_AVAILABLE         1
#define FM_ETHERNET_MAC_CHTBAR_AVAILABLE          1
#define FM4_ETHERNET_MAC_CHTDR_AVAILABLE          1
#define FM_ETHERNET_MAC_CHTDR_AVAILABLE           1
#define FM4_ETHERNET_MAC_FCR_AVAILABLE            1
#define FM_ETHERNET_MAC_FCR_AVAILABLE             1
#define FM4_ETHERNET_MAC_GAR_AVAILABLE            1
#define FM_ETHERNET_MAC_GAR_AVAILABLE             1
#define FM4_ETHERNET_MAC_GDR_AVAILABLE            1
#define FM_ETHERNET_MAC_GDR_AVAILABLE             1
#define FM4_ETHERNET_MAC_IER_AVAILABLE            1
#define FM_ETHERNET_MAC_IER_AVAILABLE             1
#define FM4_ETHERNET_MAC_IMR_AVAILABLE            1
#define FM_ETHERNET_MAC_IMR_AVAILABLE             1
#define FM4_ETHERNET_MAC_ISR_AVAILABLE            1
#define FM_ETHERNET_MAC_ISR_AVAILABLE             1
#define FM4_ETHERNET_MAC_LPICSR_AVAILABLE         1
#define FM_ETHERNET_MAC_LPICSR_AVAILABLE          1
#define FM4_ETHERNET_MAC_LPITCR_AVAILABLE         1
#define FM_ETHERNET_MAC_LPITCR_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR0H_AVAILABLE          1
#define FM_ETHERNET_MAC_MAR0H_AVAILABLE           1
#define FM4_ETHERNET_MAC_MAR0L_AVAILABLE          1
#define FM_ETHERNET_MAC_MAR0L_AVAILABLE           1
#define FM4_ETHERNET_MAC_MAR10H_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR10H_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR10L_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR10L_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR11H_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR11H_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR11L_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR11L_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR12H_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR12H_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR12L_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR12L_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR13H_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR13H_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR13L_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR13L_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR14H_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR14H_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR14L_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR14L_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR15H_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR15H_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR15L_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR15L_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR16H_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR16H_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR16L_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR16L_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR17H_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR17H_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR17L_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR17L_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR18H_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR18H_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR18L_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR18L_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR19H_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR19H_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR19L_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR19L_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR1H_AVAILABLE          1
#define FM_ETHERNET_MAC_MAR1H_AVAILABLE           1
#define FM4_ETHERNET_MAC_MAR1L_AVAILABLE          1
#define FM_ETHERNET_MAC_MAR1L_AVAILABLE           1
#define FM4_ETHERNET_MAC_MAR20H_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR20H_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR20L_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR20L_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR21H_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR21H_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR21L_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR21L_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR22H_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR22H_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR22L_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR22L_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR23H_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR23H_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR23L_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR23L_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR24H_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR24H_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR24L_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR24L_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR25H_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR25H_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR25L_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR25L_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR26H_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR26H_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR26L_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR26L_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR27H_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR27H_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR27L_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR27L_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR28H_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR28H_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR28L_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR28L_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR29H_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR29H_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR29L_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR29L_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR2H_AVAILABLE          1
#define FM_ETHERNET_MAC_MAR2H_AVAILABLE           1
#define FM4_ETHERNET_MAC_MAR2L_AVAILABLE          1
#define FM_ETHERNET_MAC_MAR2L_AVAILABLE           1
#define FM4_ETHERNET_MAC_MAR30H_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR30H_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR30L_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR30L_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR31H_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR31H_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR31L_AVAILABLE         1
#define FM_ETHERNET_MAC_MAR31L_AVAILABLE          1
#define FM4_ETHERNET_MAC_MAR3H_AVAILABLE          1
#define FM_ETHERNET_MAC_MAR3H_AVAILABLE           1
#define FM4_ETHERNET_MAC_MAR3L_AVAILABLE          1
#define FM_ETHERNET_MAC_MAR3L_AVAILABLE           1
#define FM4_ETHERNET_MAC_MAR4H_AVAILABLE          1
#define FM_ETHERNET_MAC_MAR4H_AVAILABLE           1
#define FM4_ETHERNET_MAC_MAR4L_AVAILABLE          1
#define FM_ETHERNET_MAC_MAR4L_AVAILABLE           1
#define FM4_ETHERNET_MAC_MAR5H_AVAILABLE          1
#define FM_ETHERNET_MAC_MAR5H_AVAILABLE           1
#define FM4_ETHERNET_MAC_MAR5L_AVAILABLE          1
#define FM_ETHERNET_MAC_MAR5L_AVAILABLE           1
#define FM4_ETHERNET_MAC_MAR6H_AVAILABLE          1
#define FM_ETHERNET_MAC_MAR6H_AVAILABLE           1
#define FM4_ETHERNET_MAC_MAR6L_AVAILABLE          1
#define FM_ETHERNET_MAC_MAR6L_AVAILABLE           1
#define FM4_ETHERNET_MAC_MAR7H_AVAILABLE          1
#define FM_ETHERNET_MAC_MAR7H_AVAILABLE           1
#define FM4_ETHERNET_MAC_MAR7L_AVAILABLE          1
#define FM_ETHERNET_MAC_MAR7L_AVAILABLE           1
#define FM4_ETHERNET_MAC_MAR8H_AVAILABLE          1
#define FM_ETHERNET_MAC_MAR8H_AVAILABLE           1
#define FM4_ETHERNET_MAC_MAR8L_AVAILABLE          1
#define FM_ETHERNET_MAC_MAR8L_AVAILABLE           1
#define FM4_ETHERNET_MAC_MAR9H_AVAILABLE          1
#define FM_ETHERNET_MAC_MAR9H_AVAILABLE           1
#define FM4_ETHERNET_MAC_MAR9L_AVAILABLE          1
#define FM_ETHERNET_MAC_MAR9L_AVAILABLE           1
#define FM4_ETHERNET_MAC_MCR_AVAILABLE            1
#define FM_ETHERNET_MAC_MCR_AVAILABLE             1
#define FM4_ETHERNET_MAC_MFBOCR_AVAILABLE         1
#define FM_ETHERNET_MAC_MFBOCR_AVAILABLE          1
#define FM4_ETHERNET_MAC_MFFR_AVAILABLE           1
#define FM_ETHERNET_MAC_MFFR_AVAILABLE            1
#define FM4_ETHERNET_MAC_MHTRH_AVAILABLE          1
#define FM_ETHERNET_MAC_MHTRH_AVAILABLE           1
#define FM4_ETHERNET_MAC_MHTRL_AVAILABLE          1
#define FM_ETHERNET_MAC_MHTRL_AVAILABLE           1
#define FM4_ETHERNET_MAC_MMC_CNTL_AVAILABLE       1
#define FM_ETHERNET_MAC_MMC_CNTL_AVAILABLE        1
#define FM4_ETHERNET_MAC_MMC_INTR_MASK_RX_AVAILABLE 1
#define FM_ETHERNET_MAC_MMC_INTR_MASK_RX_AVAILABLE 1
#define FM4_ETHERNET_MAC_MMC_INTR_MASK_TX_AVAILABLE 1
#define FM_ETHERNET_MAC_MMC_INTR_MASK_TX_AVAILABLE 1
#define FM4_ETHERNET_MAC_MMC_INTR_RX_AVAILABLE    1
#define FM_ETHERNET_MAC_MMC_INTR_RX_AVAILABLE     1
#define FM4_ETHERNET_MAC_MMC_INTR_TX_AVAILABLE    1
#define FM_ETHERNET_MAC_MMC_INTR_TX_AVAILABLE     1
#define FM4_ETHERNET_MAC_MMC_IPC_INTR_MASK_RX_AVAILABLE 1
#define FM_ETHERNET_MAC_MMC_IPC_INTR_MASK_RX_AVAILABLE 1
#define FM4_ETHERNET_MAC_MMC_IPC_INTR_RX_AVAILABLE 1
#define FM_ETHERNET_MAC_MMC_IPC_INTR_RX_AVAILABLE 1
#define FM4_ETHERNET_MAC_OMR_AVAILABLE            1
#define FM_ETHERNET_MAC_OMR_AVAILABLE             1
#define FM4_ETHERNET_MAC_PMTR_AVAILABLE           1
#define FM_ETHERNET_MAC_PMTR_AVAILABLE            1
#define FM4_ETHERNET_MAC_PPSCR_AVAILABLE          1
#define FM_ETHERNET_MAC_PPSCR_AVAILABLE           1
#define FM4_ETHERNET_MAC_RDLAR_AVAILABLE          1
#define FM_ETHERNET_MAC_RDLAR_AVAILABLE           1
#define FM4_ETHERNET_MAC_RGSR_AVAILABLE           1
#define FM_ETHERNET_MAC_RGSR_AVAILABLE            1
#define FM4_ETHERNET_MAC_RIWTR_AVAILABLE          1
#define FM_ETHERNET_MAC_RIWTR_AVAILABLE           1
#define FM4_ETHERNET_MAC_RPDR_AVAILABLE           1
#define FM_ETHERNET_MAC_RPDR_AVAILABLE            1
#define FM4_ETHERNET_MAC_RWFFR_AVAILABLE          1
#define FM_ETHERNET_MAC_RWFFR_AVAILABLE           1
#define FM4_ETHERNET_MAC_RX1024TOMAXOCTETS_GB_AVAILABLE 1
#define FM_ETHERNET_MAC_RX1024TOMAXOCTETS_GB_AVAILABLE 1
#define FM4_ETHERNET_MAC_RX128TO255OCTETS_GB_AVAILABLE 1
#define FM_ETHERNET_MAC_RX128TO255OCTETS_GB_AVAILABLE 1
#define FM4_ETHERNET_MAC_RX256TO511OCTETS_GB_AVAILABLE 1
#define FM_ETHERNET_MAC_RX256TO511OCTETS_GB_AVAILABLE 1
#define FM4_ETHERNET_MAC_RX512TO1023OCTETS_GB_AVAILABLE 1
#define FM_ETHERNET_MAC_RX512TO1023OCTETS_GB_AVAILABLE 1
#define FM4_ETHERNET_MAC_RX64OCTETS_GB_AVAILABLE  1
#define FM_ETHERNET_MAC_RX64OCTETS_GB_AVAILABLE   1
#define FM4_ETHERNET_MAC_RX65TO127OCTETS_GB_AVAILABLE 1
#define FM_ETHERNET_MAC_RX65TO127OCTETS_GB_AVAILABLE 1
#define FM4_ETHERNET_MAC_RXALLIGNMENTERROR_AVAILABLE 1
#define FM_ETHERNET_MAC_RXALLIGNMENTERROR_AVAILABLE 1
#define FM4_ETHERNET_MAC_RXBROADCASTFRAMES_G_AVAILABLE 1
#define FM_ETHERNET_MAC_RXBROADCASTFRAMES_G_AVAILABLE 1
#define FM4_ETHERNET_MAC_RXCRCERROR_AVAILABLE     1
#define FM_ETHERNET_MAC_RXCRCERROR_AVAILABLE      1
#define FM4_ETHERNET_MAC_RXFIFOOVERFLOW_AVAILABLE 1
#define FM_ETHERNET_MAC_RXFIFOOVERFLOW_AVAILABLE  1
#define FM4_ETHERNET_MAC_RXFRAMECOUNT_GB_AVAILABLE 1
#define FM_ETHERNET_MAC_RXFRAMECOUNT_GB_AVAILABLE 1
#define FM4_ETHERNET_MAC_RXICMP_ERR_FRMS_AVAILABLE 1
#define FM_ETHERNET_MAC_RXICMP_ERR_FRMS_AVAILABLE 1
#define FM4_ETHERNET_MAC_RXICMP_ERR_OCTETS_AVAILABLE 1
#define FM_ETHERNET_MAC_RXICMP_ERR_OCTETS_AVAILABLE 1
#define FM4_ETHERNET_MAC_RXICMP_GD_FRMS_AVAILABLE 1
#define FM_ETHERNET_MAC_RXICMP_GD_FRMS_AVAILABLE  1
#define FM4_ETHERNET_MAC_RXICMP_GD_OCTETS_AVAILABLE 1
#define FM_ETHERNET_MAC_RXICMP_GD_OCTETS_AVAILABLE 1
#define FM4_ETHERNET_MAC_RXIPV4_FRAG_FRMS_AVAILABLE 1
#define FM_ETHERNET_MAC_RXIPV4_FRAG_FRMS_AVAILABLE 1
#define FM4_ETHERNET_MAC_RXIPV4_FRAG_OCTETS_AVAILABLE 1
#define FM_ETHERNET_MAC_RXIPV4_FRAG_OCTETS_AVAILABLE 1
#define FM4_ETHERNET_MAC_RXIPV4_GD_FRMS_AVAILABLE 1
#define FM_ETHERNET_MAC_RXIPV4_GD_FRMS_AVAILABLE  1
#define FM4_ETHERNET_MAC_RXIPV4_GD_OCTETS_AVAILABLE 1
#define FM_ETHERNET_MAC_RXIPV4_GD_OCTETS_AVAILABLE 1
#define FM4_ETHERNET_MAC_RXIPV4_HDRERR_FRMS_AVAILABLE 1
#define FM_ETHERNET_MAC_RXIPV4_HDRERR_FRMS_AVAILABLE 1
#define FM4_ETHERNET_MAC_RXIPV4_HDRERR_OCTETS_AVAILABLE 1
#define FM_ETHERNET_MAC_RXIPV4_HDRERR_OCTETS_AVAILABLE 1
#define FM4_ETHERNET_MAC_RXIPV4_NOPAY_FRMS_AVAILABLE 1
#define FM_ETHERNET_MAC_RXIPV4_NOPAY_FRMS_AVAILABLE 1
#define FM4_ETHERNET_MAC_RXIPV4_NOPAY_OCTETS_AVAILABLE 1
#define FM_ETHERNET_MAC_RXIPV4_NOPAY_OCTETS_AVAILABLE 1
#define FM4_ETHERNET_MAC_RXIPV4_UDSBL_FRMS_AVAILABLE 1
#define FM_ETHERNET_MAC_RXIPV4_UDSBL_FRMS_AVAILABLE 1
#define FM4_ETHERNET_MAC_RXIPV4_UDSBL_OCTETS_AVAILABLE 1
#define FM_ETHERNET_MAC_RXIPV4_UDSBL_OCTETS_AVAILABLE 1
#define FM4_ETHERNET_MAC_RXIPV6_GD_FRMS_AVAILABLE 1
#define FM_ETHERNET_MAC_RXIPV6_GD_FRMS_AVAILABLE  1
#define FM4_ETHERNET_MAC_RXIPV6_GD_OCTETS_AVAILABLE 1
#define FM_ETHERNET_MAC_RXIPV6_GD_OCTETS_AVAILABLE 1
#define FM4_ETHERNET_MAC_RXIPV6_HDRERR_FRMS_AVAILABLE 1
#define FM_ETHERNET_MAC_RXIPV6_HDRERR_FRMS_AVAILABLE 1
#define FM4_ETHERNET_MAC_RXIPV6_HDRERR_OCTETS_AVAILABLE 1
#define FM_ETHERNET_MAC_RXIPV6_HDRERR_OCTETS_AVAILABLE 1
#define FM4_ETHERNET_MAC_RXIPV6_NOPAY_FRMS_AVAILABLE 1
#define FM_ETHERNET_MAC_RXIPV6_NOPAY_FRMS_AVAILABLE 1
#define FM4_ETHERNET_MAC_RXIPV6_NOPAY_OCTETS_AVAILABLE 1
#define FM_ETHERNET_MAC_RXIPV6_NOPAY_OCTETS_AVAILABLE 1
#define FM4_ETHERNET_MAC_RXJABBERERROR_AVAILABLE  1
#define FM_ETHERNET_MAC_RXJABBERERROR_AVAILABLE   1
#define FM4_ETHERNET_MAC_RXLENGTHERROR_AVAILABLE  1
#define FM_ETHERNET_MAC_RXLENGTHERROR_AVAILABLE   1
#define FM4_ETHERNET_MAC_RXMULTICASTFRAMES_G_AVAILABLE 1
#define FM_ETHERNET_MAC_RXMULTICASTFRAMES_G_AVAILABLE 1
#define FM4_ETHERNET_MAC_RXOCTETCOUNT_G_AVAILABLE 1
#define FM_ETHERNET_MAC_RXOCTETCOUNT_G_AVAILABLE  1
#define FM4_ETHERNET_MAC_RXOCTETCOUNT_GB_AVAILABLE 1
#define FM_ETHERNET_MAC_RXOCTETCOUNT_GB_AVAILABLE 1
#define FM4_ETHERNET_MAC_RXOUTOFRANGETYPE_AVAILABLE 1
#define FM_ETHERNET_MAC_RXOUTOFRANGETYPE_AVAILABLE 1
#define FM4_ETHERNET_MAC_RXOVERSIZE_G_AVAILABLE   1
#define FM_ETHERNET_MAC_RXOVERSIZE_G_AVAILABLE    1
#define FM4_ETHERNET_MAC_RXPAUSEFRAMES_AVAILABLE  1
#define FM_ETHERNET_MAC_RXPAUSEFRAMES_AVAILABLE   1
#define FM4_ETHERNET_MAC_RXRUNTERROR_AVAILABLE    1
#define FM_ETHERNET_MAC_RXRUNTERROR_AVAILABLE     1
#define FM4_ETHERNET_MAC_RXTCP_ERR_FRMS_AVAILABLE 1
#define FM_ETHERNET_MAC_RXTCP_ERR_FRMS_AVAILABLE  1
#define FM4_ETHERNET_MAC_RXTCP_ERR_OCTETS_AVAILABLE 1
#define FM_ETHERNET_MAC_RXTCP_ERR_OCTETS_AVAILABLE 1
#define FM4_ETHERNET_MAC_RXTCP_GD_FRMS_AVAILABLE  1
#define FM_ETHERNET_MAC_RXTCP_GD_FRMS_AVAILABLE   1
#define FM4_ETHERNET_MAC_RXTCP_GD_OCTETS_AVAILABLE 1
#define FM_ETHERNET_MAC_RXTCP_GD_OCTETS_AVAILABLE 1
#define FM4_ETHERNET_MAC_RXUDP_ERR_FRMS_AVAILABLE 1
#define FM_ETHERNET_MAC_RXUDP_ERR_FRMS_AVAILABLE  1
#define FM4_ETHERNET_MAC_RXUDP_ERR_OCTETS_AVAILABLE 1
#define FM_ETHERNET_MAC_RXUDP_ERR_OCTETS_AVAILABLE 1
#define FM4_ETHERNET_MAC_RXUDP_GD_FRMS_AVAILABLE  1
#define FM_ETHERNET_MAC_RXUDP_GD_FRMS_AVAILABLE   1
#define FM4_ETHERNET_MAC_RXUDP_GD_OCTETS_AVAILABLE 1
#define FM_ETHERNET_MAC_RXUDP_GD_OCTETS_AVAILABLE 1
#define FM4_ETHERNET_MAC_RXUNDERSIZE_G_AVAILABLE  1
#define FM_ETHERNET_MAC_RXUNDERSIZE_G_AVAILABLE   1
#define FM4_ETHERNET_MAC_RXUNICASTFRAMES_G_AVAILABLE 1
#define FM_ETHERNET_MAC_RXUNICASTFRAMES_G_AVAILABLE 1
#define FM4_ETHERNET_MAC_RXVLANFRAMES_GB_AVAILABLE 1
#define FM_ETHERNET_MAC_RXVLANFRAMES_GB_AVAILABLE 1
#define FM4_ETHERNET_MAC_RXWATCHDOGERROR_AVAILABLE 1
#define FM_ETHERNET_MAC_RXWATCHDOGERROR_AVAILABLE 1
#define FM4_ETHERNET_MAC_SR_AVAILABLE             1
#define FM_ETHERNET_MAC_SR_AVAILABLE              1
#define FM4_ETHERNET_MAC_SSIR_AVAILABLE           1
#define FM_ETHERNET_MAC_SSIR_AVAILABLE            1
#define FM4_ETHERNET_MAC_STHWSR_AVAILABLE         1
#define FM_ETHERNET_MAC_STHWSR_AVAILABLE          1
#define FM4_ETHERNET_MAC_STNR_AVAILABLE           1
#define FM_ETHERNET_MAC_STNR_AVAILABLE            1
#define FM4_ETHERNET_MAC_STNUR_AVAILABLE          1
#define FM_ETHERNET_MAC_STNUR_AVAILABLE           1
#define FM4_ETHERNET_MAC_STSR_AVAILABLE           1
#define FM_ETHERNET_MAC_STSR_AVAILABLE            1
#define FM4_ETHERNET_MAC_STSUR_AVAILABLE          1
#define FM_ETHERNET_MAC_STSUR_AVAILABLE           1
#define FM4_ETHERNET_MAC_TDLAR_AVAILABLE          1
#define FM_ETHERNET_MAC_TDLAR_AVAILABLE           1
#define FM4_ETHERNET_MAC_TPDR_AVAILABLE           1
#define FM_ETHERNET_MAC_TPDR_AVAILABLE            1
#define FM4_ETHERNET_MAC_TSAR_AVAILABLE           1
#define FM_ETHERNET_MAC_TSAR_AVAILABLE            1
#define FM4_ETHERNET_MAC_TSCR_AVAILABLE           1
#define FM_ETHERNET_MAC_TSCR_AVAILABLE            1
#define FM4_ETHERNET_MAC_TSR_AVAILABLE            1
#define FM_ETHERNET_MAC_TSR_AVAILABLE             1
#define FM4_ETHERNET_MAC_TTNR_AVAILABLE           1
#define FM_ETHERNET_MAC_TTNR_AVAILABLE            1
#define FM4_ETHERNET_MAC_TTSR_AVAILABLE           1
#define FM_ETHERNET_MAC_TTSR_AVAILABLE            1
#define FM4_ETHERNET_MAC_TX1024TOMAXOCTETS_GB_AVAILABLE 1
#define FM_ETHERNET_MAC_TX1024TOMAXOCTETS_GB_AVAILABLE 1
#define FM4_ETHERNET_MAC_TX128TO255OCTETS_GB_AVAILABLE 1
#define FM_ETHERNET_MAC_TX128TO255OCTETS_GB_AVAILABLE 1
#define FM4_ETHERNET_MAC_TX256TO511OCTETS_GB_AVAILABLE 1
#define FM_ETHERNET_MAC_TX256TO511OCTETS_GB_AVAILABLE 1
#define FM4_ETHERNET_MAC_TX512TO1023OCTETS_GB_AVAILABLE 1
#define FM_ETHERNET_MAC_TX512TO1023OCTETS_GB_AVAILABLE 1
#define FM4_ETHERNET_MAC_TX64OCTETS_GB_AVAILABLE  1
#define FM_ETHERNET_MAC_TX64OCTETS_GB_AVAILABLE   1
#define FM4_ETHERNET_MAC_TX65TO127OCTETS_GB_AVAILABLE 1
#define FM_ETHERNET_MAC_TX65TO127OCTETS_GB_AVAILABLE 1
#define FM4_ETHERNET_MAC_TXBROADCASTFRAMES_G_AVAILABLE 1
#define FM_ETHERNET_MAC_TXBROADCASTFRAMES_G_AVAILABLE 1
#define FM4_ETHERNET_MAC_TXBROADCASTFRAMES_GB_AVAILABLE 1
#define FM_ETHERNET_MAC_TXBROADCASTFRAMES_GB_AVAILABLE 1
#define FM4_ETHERNET_MAC_TXCARRIERERROR_AVAILABLE 1
#define FM_ETHERNET_MAC_TXCARRIERERROR_AVAILABLE  1
#define FM4_ETHERNET_MAC_TXDEFERRED_AVAILABLE     1
#define FM_ETHERNET_MAC_TXDEFERRED_AVAILABLE      1
#define FM4_ETHERNET_MAC_TXEXECESSDEF_G_AVAILABLE 1
#define FM_ETHERNET_MAC_TXEXECESSDEF_G_AVAILABLE  1
#define FM4_ETHERNET_MAC_TXEXESSCOL_AVAILABLE     1
#define FM_ETHERNET_MAC_TXEXESSCOL_AVAILABLE      1
#define FM4_ETHERNET_MAC_TXFRAMECOUNT_G_AVAILABLE 1
#define FM_ETHERNET_MAC_TXFRAMECOUNT_G_AVAILABLE  1
#define FM4_ETHERNET_MAC_TXFRAMECOUNT_GB_AVAILABLE 1
#define FM_ETHERNET_MAC_TXFRAMECOUNT_GB_AVAILABLE 1
#define FM4_ETHERNET_MAC_TXLATECOL_AVAILABLE      1
#define FM_ETHERNET_MAC_TXLATECOL_AVAILABLE       1
#define FM4_ETHERNET_MAC_TXMULTICASTFRAMES_G_AVAILABLE 1
#define FM_ETHERNET_MAC_TXMULTICASTFRAMES_G_AVAILABLE 1
#define FM4_ETHERNET_MAC_TXMULTICASTFRAMES_GB_AVAILABLE 1
#define FM_ETHERNET_MAC_TXMULTICASTFRAMES_GB_AVAILABLE 1
#define FM4_ETHERNET_MAC_TXMULTICOL_G_AVAILABLE   1
#define FM_ETHERNET_MAC_TXMULTICOL_G_AVAILABLE    1
#define FM4_ETHERNET_MAC_TXOCTETCOUNT_G_AVAILABLE 1
#define FM_ETHERNET_MAC_TXOCTETCOUNT_G_AVAILABLE  1
#define FM4_ETHERNET_MAC_TXOCTETCOUNT_GB_AVAILABLE 1
#define FM_ETHERNET_MAC_TXOCTETCOUNT_GB_AVAILABLE 1
#define FM4_ETHERNET_MAC_TXPAUSEFRAMES_AVAILABLE  1
#define FM_ETHERNET_MAC_TXPAUSEFRAMES_AVAILABLE   1
#define FM4_ETHERNET_MAC_TXSINGLECOL_G_AVAILABLE  1
#define FM_ETHERNET_MAC_TXSINGLECOL_G_AVAILABLE   1
#define FM4_ETHERNET_MAC_TXUNDERFLOWERROR_AVAILABLE 1
#define FM_ETHERNET_MAC_TXUNDERFLOWERROR_AVAILABLE 1
#define FM4_ETHERNET_MAC_TXUNICASTFRAMES_GB_AVAILABLE 1
#define FM_ETHERNET_MAC_TXUNICASTFRAMES_GB_AVAILABLE 1
#define FM4_ETHERNET_MAC_TXVLANFRAMES_G_AVAILABLE 1
#define FM_ETHERNET_MAC_TXVLANFRAMES_G_AVAILABLE  1
#define FM4_ETHERNET_MAC_VTR_AVAILABLE            1
#define FM_ETHERNET_MAC_VTR_AVAILABLE             1
/*******************************************************************************
* EXBUS
*******************************************************************************/
#define FM4_EXBUS_AMODE_AVAILABLE                 1
#define FM_EXBUS_AMODE_AVAILABLE                  1
#define FM4_EXBUS_AREA0_AVAILABLE                 1
#define FM_EXBUS_AREA0_AVAILABLE                  1
#define FM4_EXBUS_AREA1_AVAILABLE                 1
#define FM_EXBUS_AREA1_AVAILABLE                  1
#define FM4_EXBUS_AREA2_AVAILABLE                 1
#define FM_EXBUS_AREA2_AVAILABLE                  1
#define FM4_EXBUS_AREA3_AVAILABLE                 1
#define FM_EXBUS_AREA3_AVAILABLE                  1
#define FM4_EXBUS_AREA4_AVAILABLE                 1
#define FM_EXBUS_AREA4_AVAILABLE                  1
#define FM4_EXBUS_AREA5_AVAILABLE                 1
#define FM_EXBUS_AREA5_AVAILABLE                  1
#define FM4_EXBUS_AREA6_AVAILABLE                 1
#define FM_EXBUS_AREA6_AVAILABLE                  1
#define FM4_EXBUS_AREA7_AVAILABLE                 1
#define FM_EXBUS_AREA7_AVAILABLE                  1
#define FM4_EXBUS_ATIM0_AVAILABLE                 1
#define FM_EXBUS_ATIM0_AVAILABLE                  1
#define FM4_EXBUS_ATIM1_AVAILABLE                 1
#define FM_EXBUS_ATIM1_AVAILABLE                  1
#define FM4_EXBUS_ATIM2_AVAILABLE                 1
#define FM_EXBUS_ATIM2_AVAILABLE                  1
#define FM4_EXBUS_ATIM3_AVAILABLE                 1
#define FM_EXBUS_ATIM3_AVAILABLE                  1
#define FM4_EXBUS_ATIM4_AVAILABLE                 1
#define FM_EXBUS_ATIM4_AVAILABLE                  1
#define FM4_EXBUS_ATIM5_AVAILABLE                 1
#define FM_EXBUS_ATIM5_AVAILABLE                  1
#define FM4_EXBUS_ATIM6_AVAILABLE                 1
#define FM_EXBUS_ATIM6_AVAILABLE                  1
#define FM4_EXBUS_ATIM7_AVAILABLE                 1
#define FM_EXBUS_ATIM7_AVAILABLE                  1
#define FM4_EXBUS_DCLKR_AVAILABLE                 1
#define FM_EXBUS_DCLKR_AVAILABLE                  1
#define FM4_EXBUS_ESCLR_AVAILABLE                 1
#define FM_EXBUS_ESCLR_AVAILABLE                  1
#define FM4_EXBUS_EST_AVAILABLE                   1
#define FM_EXBUS_EST_AVAILABLE                    1
#define FM4_EXBUS_MEMCERR_AVAILABLE               1
#define FM_EXBUS_MEMCERR_AVAILABLE                1
#define FM4_EXBUS_MODE0_AVAILABLE                 1
#define FM_EXBUS_MODE0_AVAILABLE                  1
#define FM4_EXBUS_MODE1_AVAILABLE                 1
#define FM_EXBUS_MODE1_AVAILABLE                  1
#define FM4_EXBUS_MODE2_AVAILABLE                 1
#define FM_EXBUS_MODE2_AVAILABLE                  1
#define FM4_EXBUS_MODE3_AVAILABLE                 1
#define FM_EXBUS_MODE3_AVAILABLE                  1
#define FM4_EXBUS_MODE4_AVAILABLE                 1
#define FM_EXBUS_MODE4_AVAILABLE                  1
#define FM4_EXBUS_MODE5_AVAILABLE                 1
#define FM_EXBUS_MODE5_AVAILABLE                  1
#define FM4_EXBUS_MODE6_AVAILABLE                 1
#define FM_EXBUS_MODE6_AVAILABLE                  1
#define FM4_EXBUS_MODE7_AVAILABLE                 1
#define FM_EXBUS_MODE7_AVAILABLE                  1
#define FM4_EXBUS_PWRDWN_AVAILABLE                1
#define FM_EXBUS_PWRDWN_AVAILABLE                 1
#define FM4_EXBUS_REFTIM_AVAILABLE                1
#define FM_EXBUS_REFTIM_AVAILABLE                 1
#define FM4_EXBUS_SDCMD_AVAILABLE                 1
#define FM_EXBUS_SDCMD_AVAILABLE                  1
#define FM4_EXBUS_SDMODE_AVAILABLE                1
#define FM_EXBUS_SDMODE_AVAILABLE                 1
#define FM4_EXBUS_SDTIM_AVAILABLE                 1
#define FM_EXBUS_SDTIM_AVAILABLE                  1
#define FM4_EXBUS_TIM0_AVAILABLE                  1
#define FM_EXBUS_TIM0_AVAILABLE                   1
#define FM4_EXBUS_TIM1_AVAILABLE                  1
#define FM_EXBUS_TIM1_AVAILABLE                   1
#define FM4_EXBUS_TIM2_AVAILABLE                  1
#define FM_EXBUS_TIM2_AVAILABLE                   1
#define FM4_EXBUS_TIM3_AVAILABLE                  1
#define FM_EXBUS_TIM3_AVAILABLE                   1
#define FM4_EXBUS_TIM4_AVAILABLE                  1
#define FM_EXBUS_TIM4_AVAILABLE                   1
#define FM4_EXBUS_TIM5_AVAILABLE                  1
#define FM_EXBUS_TIM5_AVAILABLE                   1
#define FM4_EXBUS_TIM6_AVAILABLE                  1
#define FM_EXBUS_TIM6_AVAILABLE                   1
#define FM4_EXBUS_TIM7_AVAILABLE                  1
#define FM_EXBUS_TIM7_AVAILABLE                   1
#define FM4_EXBUS_WEAD_AVAILABLE                  1
#define FM_EXBUS_WEAD_AVAILABLE                   1
/*******************************************************************************
* EXTI
*******************************************************************************/
#define FM4_EXTI_EICL_AVAILABLE                   1
#define FM_EXTI_EICL_AVAILABLE                    1
#define FM4_EXTI_EIRR_AVAILABLE                   1
#define FM_EXTI_EIRR_AVAILABLE                    1
#define FM4_EXTI_ELVR_AVAILABLE                   1
#define FM_EXTI_ELVR_AVAILABLE                    1
#define FM4_EXTI_ELVR1_AVAILABLE                  1
#define FM_EXTI_ELVR1_AVAILABLE                   1
#define FM4_EXTI_ENIR_AVAILABLE                   1
#define FM_EXTI_ENIR_AVAILABLE                    1
#define FM4_EXTI_NMICL_AVAILABLE                  1
#define FM_EXTI_NMICL_AVAILABLE                   1
#define FM4_EXTI_NMIRR_AVAILABLE                  1
#define FM_EXTI_NMIRR_AVAILABLE                   1
/*******************************************************************************
* FLASH_IF
*******************************************************************************/
#define FM4_FLASH_IF_CRTRMM_AVAILABLE             1
#define FM_FLASH_IF_CRTRMM_AVAILABLE              1
#define FM4_FLASH_IF_DFCTRLR_AVAILABLE            1
#define FM_FLASH_IF_DFCTRLR_AVAILABLE             1
#define FM4_FLASH_IF_FASZR_AVAILABLE              1
#define FM_FLASH_IF_FASZR_AVAILABLE               1
#define FM4_FLASH_IF_FBFCR_AVAILABLE              1
#define FM_FLASH_IF_FBFCR_AVAILABLE               1
#define FM4_FLASH_IF_FGPDM1_AVAILABLE             1
#define FM_FLASH_IF_FGPDM1_AVAILABLE              1
#define FM4_FLASH_IF_FGPDM2_AVAILABLE             1
#define FM_FLASH_IF_FGPDM2_AVAILABLE              1
#define FM4_FLASH_IF_FGPDM3_AVAILABLE             1
#define FM_FLASH_IF_FGPDM3_AVAILABLE              1
#define FM4_FLASH_IF_FGPDM4_AVAILABLE             1
#define FM_FLASH_IF_FGPDM4_AVAILABLE              1
#define FM4_FLASH_IF_FICLR_AVAILABLE              1
#define FM_FLASH_IF_FICLR_AVAILABLE               1
#define FM4_FLASH_IF_FICR_AVAILABLE               1
#define FM_FLASH_IF_FICR_AVAILABLE                1
#define FM4_FLASH_IF_FISR_AVAILABLE               1
#define FM_FLASH_IF_FISR_AVAILABLE                1
#define FM4_FLASH_IF_FRWTR_AVAILABLE              1
#define FM_FLASH_IF_FRWTR_AVAILABLE               1
#define FM4_FLASH_IF_FSTR_AVAILABLE               1
#define FM_FLASH_IF_FSTR_AVAILABLE                1
#define FM4_FLASH_IF_FSYNDN_AVAILABLE             1
#define FM_FLASH_IF_FSYNDN_AVAILABLE              1
/*******************************************************************************
* GPIO
*******************************************************************************/
#define FM4_GPIO_ADE_AVAILABLE                    1
#define FM_GPIO_ADE_AVAILABLE                     1
#define FM4_GPIO_DDR0_AVAILABLE                   1
#define FM_GPIO_DDR0_AVAILABLE                    1
#define FM4_GPIO_DDR1_AVAILABLE                   1
#define FM_GPIO_DDR1_AVAILABLE                    1
#define FM4_GPIO_DDR2_AVAILABLE                   1
#define FM_GPIO_DDR2_AVAILABLE                    1
#define FM4_GPIO_DDR3_AVAILABLE                   1
#define FM_GPIO_DDR3_AVAILABLE                    1
#define FM4_GPIO_DDR4_AVAILABLE                   1
#define FM_GPIO_DDR4_AVAILABLE                    1
#define FM4_GPIO_DDR5_AVAILABLE                   1
#define FM_GPIO_DDR5_AVAILABLE                    1
#define FM4_GPIO_DDR6_AVAILABLE                   1
#define FM_GPIO_DDR6_AVAILABLE                    1
#define FM4_GPIO_DDR7_AVAILABLE                   1
#define FM_GPIO_DDR7_AVAILABLE                    1
#define FM4_GPIO_DDR8_AVAILABLE                   1
#define FM_GPIO_DDR8_AVAILABLE                    1
#define FM4_GPIO_DDR9_AVAILABLE                   1
#define FM_GPIO_DDR9_AVAILABLE                    1
#define FM4_GPIO_DDRA_AVAILABLE                   1
#define FM_GPIO_DDRA_AVAILABLE                    1
#define FM4_GPIO_DDRB_AVAILABLE                   1
#define FM_GPIO_DDRB_AVAILABLE                    1
#define FM4_GPIO_DDRC_AVAILABLE                   1
#define FM_GPIO_DDRC_AVAILABLE                    1
#define FM4_GPIO_DDRD_AVAILABLE                   1
#define FM_GPIO_DDRD_AVAILABLE                    1
#define FM4_GPIO_DDRE_AVAILABLE                   1
#define FM_GPIO_DDRE_AVAILABLE                    1
#define FM4_GPIO_DDRF_AVAILABLE                   1
#define FM_GPIO_DDRF_AVAILABLE                    1
#define FM4_GPIO_EPFR00_AVAILABLE                 1
#define FM_GPIO_EPFR00_AVAILABLE                  1
#define FM4_GPIO_EPFR01_AVAILABLE                 1
#define FM_GPIO_EPFR01_AVAILABLE                  1
#define FM4_GPIO_EPFR02_AVAILABLE                 1
#define FM_GPIO_EPFR02_AVAILABLE                  1
#define FM4_GPIO_EPFR03_AVAILABLE                 1
#define FM_GPIO_EPFR03_AVAILABLE                  1
#define FM4_GPIO_EPFR04_AVAILABLE                 1
#define FM_GPIO_EPFR04_AVAILABLE                  1
#define FM4_GPIO_EPFR05_AVAILABLE                 1
#define FM_GPIO_EPFR05_AVAILABLE                  1
#define FM4_GPIO_EPFR06_AVAILABLE                 1
#define FM_GPIO_EPFR06_AVAILABLE                  1
#define FM4_GPIO_EPFR07_AVAILABLE                 1
#define FM_GPIO_EPFR07_AVAILABLE                  1
#define FM4_GPIO_EPFR08_AVAILABLE                 1
#define FM_GPIO_EPFR08_AVAILABLE                  1
#define FM4_GPIO_EPFR09_AVAILABLE                 1
#define FM_GPIO_EPFR09_AVAILABLE                  1
#define FM4_GPIO_EPFR10_AVAILABLE                 1
#define FM_GPIO_EPFR10_AVAILABLE                  1
#define FM4_GPIO_EPFR11_AVAILABLE                 1
#define FM_GPIO_EPFR11_AVAILABLE                  1
#define FM4_GPIO_EPFR12_AVAILABLE                 1
#define FM_GPIO_EPFR12_AVAILABLE                  1
#define FM4_GPIO_EPFR13_AVAILABLE                 1
#define FM_GPIO_EPFR13_AVAILABLE                  1
#define FM4_GPIO_EPFR14_AVAILABLE                 1
#define FM_GPIO_EPFR14_AVAILABLE                  1
#define FM4_GPIO_EPFR15_AVAILABLE                 1
#define FM_GPIO_EPFR15_AVAILABLE                  1
#define FM4_GPIO_EPFR16_AVAILABLE                 1
#define FM_GPIO_EPFR16_AVAILABLE                  1
#define FM4_GPIO_EPFR17_AVAILABLE                 1
#define FM_GPIO_EPFR17_AVAILABLE                  1
#define FM4_GPIO_EPFR18_AVAILABLE                 1
#define FM_GPIO_EPFR18_AVAILABLE                  1
#define FM4_GPIO_EPFR19_AVAILABLE                 1
#define FM_GPIO_EPFR19_AVAILABLE                  1
#define FM4_GPIO_EPFR20_AVAILABLE                 1
#define FM_GPIO_EPFR20_AVAILABLE                  1
#define FM4_GPIO_EPFR21_AVAILABLE                 1
#define FM_GPIO_EPFR21_AVAILABLE                  1
#define FM4_GPIO_EPFR22_AVAILABLE                 1
#define FM_GPIO_EPFR22_AVAILABLE                  1
#define FM4_GPIO_EPFR23_AVAILABLE                 1
#define FM_GPIO_EPFR23_AVAILABLE                  1
#define FM4_GPIO_EPFR24_AVAILABLE                 1
#define FM_GPIO_EPFR24_AVAILABLE                  1
#define FM4_GPIO_EPFR25_AVAILABLE                 1
#define FM_GPIO_EPFR25_AVAILABLE                  1
#define FM4_GPIO_EPFR26_AVAILABLE                 1
#define FM_GPIO_EPFR26_AVAILABLE                  1
#define FM4_GPIO_PCR0_AVAILABLE                   1
#define FM_GPIO_PCR0_AVAILABLE                    1
#define FM4_GPIO_PCR1_AVAILABLE                   1
#define FM_GPIO_PCR1_AVAILABLE                    1
#define FM4_GPIO_PCR2_AVAILABLE                   1
#define FM_GPIO_PCR2_AVAILABLE                    1
#define FM4_GPIO_PCR3_AVAILABLE                   1
#define FM_GPIO_PCR3_AVAILABLE                    1
#define FM4_GPIO_PCR4_AVAILABLE                   1
#define FM_GPIO_PCR4_AVAILABLE                    1
#define FM4_GPIO_PCR5_AVAILABLE                   1
#define FM_GPIO_PCR5_AVAILABLE                    1
#define FM4_GPIO_PCR6_AVAILABLE                   1
#define FM_GPIO_PCR6_AVAILABLE                    1
#define FM4_GPIO_PCR7_AVAILABLE                   1
#define FM_GPIO_PCR7_AVAILABLE                    1
#define FM4_GPIO_PCR9_AVAILABLE                   1
#define FM_GPIO_PCR9_AVAILABLE                    1
#define FM4_GPIO_PCRA_AVAILABLE                   1
#define FM_GPIO_PCRA_AVAILABLE                    1
#define FM4_GPIO_PCRB_AVAILABLE                   1
#define FM_GPIO_PCRB_AVAILABLE                    1
#define FM4_GPIO_PCRC_AVAILABLE                   1
#define FM_GPIO_PCRC_AVAILABLE                    1
#define FM4_GPIO_PCRD_AVAILABLE                   1
#define FM_GPIO_PCRD_AVAILABLE                    1
#define FM4_GPIO_PCRE_AVAILABLE                   1
#define FM_GPIO_PCRE_AVAILABLE                    1
#define FM4_GPIO_PCRF_AVAILABLE                   1
#define FM_GPIO_PCRF_AVAILABLE                    1
#define FM4_GPIO_PDIR0_AVAILABLE                  1
#define FM_GPIO_PDIR0_AVAILABLE                   1
#define FM4_GPIO_PDIR1_AVAILABLE                  1
#define FM_GPIO_PDIR1_AVAILABLE                   1
#define FM4_GPIO_PDIR2_AVAILABLE                  1
#define FM_GPIO_PDIR2_AVAILABLE                   1
#define FM4_GPIO_PDIR3_AVAILABLE                  1
#define FM_GPIO_PDIR3_AVAILABLE                   1
#define FM4_GPIO_PDIR4_AVAILABLE                  1
#define FM_GPIO_PDIR4_AVAILABLE                   1
#define FM4_GPIO_PDIR5_AVAILABLE                  1
#define FM_GPIO_PDIR5_AVAILABLE                   1
#define FM4_GPIO_PDIR6_AVAILABLE                  1
#define FM_GPIO_PDIR6_AVAILABLE                   1
#define FM4_GPIO_PDIR7_AVAILABLE                  1
#define FM_GPIO_PDIR7_AVAILABLE                   1
#define FM4_GPIO_PDIR8_AVAILABLE                  1
#define FM_GPIO_PDIR8_AVAILABLE                   1
#define FM4_GPIO_PDIR9_AVAILABLE                  1
#define FM_GPIO_PDIR9_AVAILABLE                   1
#define FM4_GPIO_PDIRA_AVAILABLE                  1
#define FM_GPIO_PDIRA_AVAILABLE                   1
#define FM4_GPIO_PDIRB_AVAILABLE                  1
#define FM_GPIO_PDIRB_AVAILABLE                   1
#define FM4_GPIO_PDIRC_AVAILABLE                  1
#define FM_GPIO_PDIRC_AVAILABLE                   1
#define FM4_GPIO_PDIRD_AVAILABLE                  1
#define FM_GPIO_PDIRD_AVAILABLE                   1
#define FM4_GPIO_PDIRE_AVAILABLE                  1
#define FM_GPIO_PDIRE_AVAILABLE                   1
#define FM4_GPIO_PDIRF_AVAILABLE                  1
#define FM_GPIO_PDIRF_AVAILABLE                   1
#define FM4_GPIO_PDOR0_AVAILABLE                  1
#define FM_GPIO_PDOR0_AVAILABLE                   1
#define FM4_GPIO_PDOR1_AVAILABLE                  1
#define FM_GPIO_PDOR1_AVAILABLE                   1
#define FM4_GPIO_PDOR2_AVAILABLE                  1
#define FM_GPIO_PDOR2_AVAILABLE                   1
#define FM4_GPIO_PDOR3_AVAILABLE                  1
#define FM_GPIO_PDOR3_AVAILABLE                   1
#define FM4_GPIO_PDOR4_AVAILABLE                  1
#define FM_GPIO_PDOR4_AVAILABLE                   1
#define FM4_GPIO_PDOR5_AVAILABLE                  1
#define FM_GPIO_PDOR5_AVAILABLE                   1
#define FM4_GPIO_PDOR6_AVAILABLE                  1
#define FM_GPIO_PDOR6_AVAILABLE                   1
#define FM4_GPIO_PDOR7_AVAILABLE                  1
#define FM_GPIO_PDOR7_AVAILABLE                   1
#define FM4_GPIO_PDOR8_AVAILABLE                  1
#define FM_GPIO_PDOR8_AVAILABLE                   1
#define FM4_GPIO_PDOR9_AVAILABLE                  1
#define FM_GPIO_PDOR9_AVAILABLE                   1
#define FM4_GPIO_PDORA_AVAILABLE                  1
#define FM_GPIO_PDORA_AVAILABLE                   1
#define FM4_GPIO_PDORB_AVAILABLE                  1
#define FM_GPIO_PDORB_AVAILABLE                   1
#define FM4_GPIO_PDORC_AVAILABLE                  1
#define FM_GPIO_PDORC_AVAILABLE                   1
#define FM4_GPIO_PDORD_AVAILABLE                  1
#define FM_GPIO_PDORD_AVAILABLE                   1
#define FM4_GPIO_PDORE_AVAILABLE                  1
#define FM_GPIO_PDORE_AVAILABLE                   1
#define FM4_GPIO_PDORF_AVAILABLE                  1
#define FM_GPIO_PDORF_AVAILABLE                   1
#define FM4_GPIO_PDSR0_AVAILABLE                  1
#define FM_GPIO_PDSR0_AVAILABLE                   1
#define FM4_GPIO_PDSR1_AVAILABLE                  1
#define FM_GPIO_PDSR1_AVAILABLE                   1
#define FM4_GPIO_PDSR2_AVAILABLE                  1
#define FM_GPIO_PDSR2_AVAILABLE                   1
#define FM4_GPIO_PDSR3_AVAILABLE                  1
#define FM_GPIO_PDSR3_AVAILABLE                   1
#define FM4_GPIO_PDSR4_AVAILABLE                  1
#define FM_GPIO_PDSR4_AVAILABLE                   1
#define FM4_GPIO_PDSR5_AVAILABLE                  1
#define FM_GPIO_PDSR5_AVAILABLE                   1
#define FM4_GPIO_PDSR6_AVAILABLE                  1
#define FM_GPIO_PDSR6_AVAILABLE                   1
#define FM4_GPIO_PDSR7_AVAILABLE                  1
#define FM_GPIO_PDSR7_AVAILABLE                   1
#define FM4_GPIO_PDSR8_AVAILABLE                  1
#define FM_GPIO_PDSR8_AVAILABLE                   1
#define FM4_GPIO_PDSR9_AVAILABLE                  1
#define FM_GPIO_PDSR9_AVAILABLE                   1
#define FM4_GPIO_PDSRA_AVAILABLE                  1
#define FM_GPIO_PDSRA_AVAILABLE                   1
#define FM4_GPIO_PDSRB_AVAILABLE                  1
#define FM_GPIO_PDSRB_AVAILABLE                   1
#define FM4_GPIO_PDSRC_AVAILABLE                  1
#define FM_GPIO_PDSRC_AVAILABLE                   1
#define FM4_GPIO_PDSRD_AVAILABLE                  1
#define FM_GPIO_PDSRD_AVAILABLE                   1
#define FM4_GPIO_PDSRE_AVAILABLE                  1
#define FM_GPIO_PDSRE_AVAILABLE                   1
#define FM4_GPIO_PDSRF_AVAILABLE                  1
#define FM_GPIO_PDSRF_AVAILABLE                   1
#define FM4_GPIO_PFR0_AVAILABLE                   1
#define FM_GPIO_PFR0_AVAILABLE                    1
#define FM4_GPIO_PFR1_AVAILABLE                   1
#define FM_GPIO_PFR1_AVAILABLE                    1
#define FM4_GPIO_PFR2_AVAILABLE                   1
#define FM_GPIO_PFR2_AVAILABLE                    1
#define FM4_GPIO_PFR3_AVAILABLE                   1
#define FM_GPIO_PFR3_AVAILABLE                    1
#define FM4_GPIO_PFR4_AVAILABLE                   1
#define FM_GPIO_PFR4_AVAILABLE                    1
#define FM4_GPIO_PFR5_AVAILABLE                   1
#define FM_GPIO_PFR5_AVAILABLE                    1
#define FM4_GPIO_PFR6_AVAILABLE                   1
#define FM_GPIO_PFR6_AVAILABLE                    1
#define FM4_GPIO_PFR7_AVAILABLE                   1
#define FM_GPIO_PFR7_AVAILABLE                    1
#define FM4_GPIO_PFR8_AVAILABLE                   1
#define FM_GPIO_PFR8_AVAILABLE                    1
#define FM4_GPIO_PFR9_AVAILABLE                   1
#define FM_GPIO_PFR9_AVAILABLE                    1
#define FM4_GPIO_PFRA_AVAILABLE                   1
#define FM_GPIO_PFRA_AVAILABLE                    1
#define FM4_GPIO_PFRB_AVAILABLE                   1
#define FM_GPIO_PFRB_AVAILABLE                    1
#define FM4_GPIO_PFRC_AVAILABLE                   1
#define FM_GPIO_PFRC_AVAILABLE                    1
#define FM4_GPIO_PFRD_AVAILABLE                   1
#define FM_GPIO_PFRD_AVAILABLE                    1
#define FM4_GPIO_PFRE_AVAILABLE                   1
#define FM_GPIO_PFRE_AVAILABLE                    1
#define FM4_GPIO_PFRF_AVAILABLE                   1
#define FM_GPIO_PFRF_AVAILABLE                    1
#define FM4_GPIO_PZR0_AVAILABLE                   1
#define FM_GPIO_PZR0_AVAILABLE                    1
#define FM4_GPIO_PZR1_AVAILABLE                   1
#define FM_GPIO_PZR1_AVAILABLE                    1
#define FM4_GPIO_PZR2_AVAILABLE                   1
#define FM_GPIO_PZR2_AVAILABLE                    1
#define FM4_GPIO_PZR3_AVAILABLE                   1
#define FM_GPIO_PZR3_AVAILABLE                    1
#define FM4_GPIO_PZR4_AVAILABLE                   1
#define FM_GPIO_PZR4_AVAILABLE                    1
#define FM4_GPIO_PZR5_AVAILABLE                   1
#define FM_GPIO_PZR5_AVAILABLE                    1
#define FM4_GPIO_PZR6_AVAILABLE                   1
#define FM_GPIO_PZR6_AVAILABLE                    1
#define FM4_GPIO_PZR7_AVAILABLE                   1
#define FM_GPIO_PZR7_AVAILABLE                    1
#define FM4_GPIO_PZR8_AVAILABLE                   1
#define FM_GPIO_PZR8_AVAILABLE                    1
#define FM4_GPIO_PZR9_AVAILABLE                   1
#define FM_GPIO_PZR9_AVAILABLE                    1
#define FM4_GPIO_PZRA_AVAILABLE                   1
#define FM_GPIO_PZRA_AVAILABLE                    1
#define FM4_GPIO_PZRB_AVAILABLE                   1
#define FM_GPIO_PZRB_AVAILABLE                    1
#define FM4_GPIO_PZRC_AVAILABLE                   1
#define FM_GPIO_PZRC_AVAILABLE                    1
#define FM4_GPIO_PZRD_AVAILABLE                   1
#define FM_GPIO_PZRD_AVAILABLE                    1
#define FM4_GPIO_PZRE_AVAILABLE                   1
#define FM_GPIO_PZRE_AVAILABLE                    1
#define FM4_GPIO_PZRF_AVAILABLE                   1
#define FM_GPIO_PZRF_AVAILABLE                    1
#define FM4_GPIO_SPSR_AVAILABLE                   1
#define FM_GPIO_SPSR_AVAILABLE                    1
/*******************************************************************************
* HSSPI
*******************************************************************************/
#define FM4_HSSPI_CSAEXT_AVAILABLE                1
#define FM_HSSPI_CSAEXT_AVAILABLE                 1
#define FM4_HSSPI_CSCFG_AVAILABLE                 1
#define FM_HSSPI_CSCFG_AVAILABLE                  1
#define FM4_HSSPI_CSITIME_AVAILABLE               1
#define FM_HSSPI_CSITIME_AVAILABLE                1
#define FM4_HSSPI_DBCNT_AVAILABLE                 1
#define FM_HSSPI_DBCNT_AVAILABLE                  1
#define FM4_HSSPI_DMBCC_AVAILABLE                 1
#define FM_HSSPI_DMBCC_AVAILABLE                  1
#define FM4_HSSPI_DMBCS_AVAILABLE                 1
#define FM_HSSPI_DMBCS_AVAILABLE                  1
#define FM4_HSSPI_DMCFG_AVAILABLE                 1
#define FM_HSSPI_DMCFG_AVAILABLE                  1
#define FM4_HSSPI_DMDMAEN_AVAILABLE               1
#define FM_HSSPI_DMDMAEN_AVAILABLE                1
#define FM4_HSSPI_DMPSEL_AVAILABLE                1
#define FM_HSSPI_DMPSEL_AVAILABLE                 1
#define FM4_HSSPI_DMSTART_AVAILABLE               1
#define FM_HSSPI_DMSTART_AVAILABLE                1
#define FM4_HSSPI_DMSTATUS_AVAILABLE              1
#define FM_HSSPI_DMSTATUS_AVAILABLE               1
#define FM4_HSSPI_DMSTOP_AVAILABLE                1
#define FM_HSSPI_DMSTOP_AVAILABLE                 1
#define FM4_HSSPI_DMTRP_AVAILABLE                 1
#define FM_HSSPI_DMTRP_AVAILABLE                  1
#define FM4_HSSPI_FAULTC_AVAILABLE                1
#define FM_HSSPI_FAULTC_AVAILABLE                 1
#define FM4_HSSPI_FAULTF_AVAILABLE                1
#define FM_HSSPI_FAULTF_AVAILABLE                 1
#define FM4_HSSPI_FIFOCFG_AVAILABLE               1
#define FM_HSSPI_FIFOCFG_AVAILABLE                1
#define FM4_HSSPI_MCTRL_AVAILABLE                 1
#define FM_HSSPI_MCTRL_AVAILABLE                  1
#define FM4_HSSPI_MID_AVAILABLE                   1
#define FM_HSSPI_MID_AVAILABLE                    1
#define FM4_HSSPI_PCC0_AVAILABLE                  1
#define FM_HSSPI_PCC0_AVAILABLE                   1
#define FM4_HSSPI_PCC1_AVAILABLE                  1
#define FM_HSSPI_PCC1_AVAILABLE                   1
#define FM4_HSSPI_PCC2_AVAILABLE                  1
#define FM_HSSPI_PCC2_AVAILABLE                   1
#define FM4_HSSPI_PCC3_AVAILABLE                  1
#define FM_HSSPI_PCC3_AVAILABLE                   1
#define FM4_HSSPI_QDCLKR_AVAILABLE                1
#define FM_HSSPI_QDCLKR_AVAILABLE                 1
#define FM4_HSSPI_RDCSDC0_AVAILABLE               1
#define FM_HSSPI_RDCSDC0_AVAILABLE                1
#define FM4_HSSPI_RDCSDC1_AVAILABLE               1
#define FM_HSSPI_RDCSDC1_AVAILABLE                1
#define FM4_HSSPI_RDCSDC2_AVAILABLE               1
#define FM_HSSPI_RDCSDC2_AVAILABLE                1
#define FM4_HSSPI_RDCSDC3_AVAILABLE               1
#define FM_HSSPI_RDCSDC3_AVAILABLE                1
#define FM4_HSSPI_RDCSDC4_AVAILABLE               1
#define FM_HSSPI_RDCSDC4_AVAILABLE                1
#define FM4_HSSPI_RDCSDC5_AVAILABLE               1
#define FM_HSSPI_RDCSDC5_AVAILABLE                1
#define FM4_HSSPI_RDCSDC6_AVAILABLE               1
#define FM_HSSPI_RDCSDC6_AVAILABLE                1
#define FM4_HSSPI_RDCSDC7_AVAILABLE               1
#define FM_HSSPI_RDCSDC7_AVAILABLE                1
#define FM4_HSSPI_RXC_AVAILABLE                   1
#define FM_HSSPI_RXC_AVAILABLE                    1
#define FM4_HSSPI_RXE_AVAILABLE                   1
#define FM_HSSPI_RXE_AVAILABLE                    1
#define FM4_HSSPI_RXF_AVAILABLE                   1
#define FM_HSSPI_RXF_AVAILABLE                    1
#define FM4_HSSPI_RXFIFO0_AVAILABLE               1
#define FM_HSSPI_RXFIFO0_AVAILABLE                1
#define FM4_HSSPI_RXFIFO1_AVAILABLE               1
#define FM_HSSPI_RXFIFO1_AVAILABLE                1
#define FM4_HSSPI_RXFIFO10_AVAILABLE              1
#define FM_HSSPI_RXFIFO10_AVAILABLE               1
#define FM4_HSSPI_RXFIFO11_AVAILABLE              1
#define FM_HSSPI_RXFIFO11_AVAILABLE               1
#define FM4_HSSPI_RXFIFO12_AVAILABLE              1
#define FM_HSSPI_RXFIFO12_AVAILABLE               1
#define FM4_HSSPI_RXFIFO13_AVAILABLE              1
#define FM_HSSPI_RXFIFO13_AVAILABLE               1
#define FM4_HSSPI_RXFIFO14_AVAILABLE              1
#define FM_HSSPI_RXFIFO14_AVAILABLE               1
#define FM4_HSSPI_RXFIFO15_AVAILABLE              1
#define FM_HSSPI_RXFIFO15_AVAILABLE               1
#define FM4_HSSPI_RXFIFO2_AVAILABLE               1
#define FM_HSSPI_RXFIFO2_AVAILABLE                1
#define FM4_HSSPI_RXFIFO3_AVAILABLE               1
#define FM_HSSPI_RXFIFO3_AVAILABLE                1
#define FM4_HSSPI_RXFIFO4_AVAILABLE               1
#define FM_HSSPI_RXFIFO4_AVAILABLE                1
#define FM4_HSSPI_RXFIFO5_AVAILABLE               1
#define FM_HSSPI_RXFIFO5_AVAILABLE                1
#define FM4_HSSPI_RXFIFO6_AVAILABLE               1
#define FM_HSSPI_RXFIFO6_AVAILABLE                1
#define FM4_HSSPI_RXFIFO7_AVAILABLE               1
#define FM_HSSPI_RXFIFO7_AVAILABLE                1
#define FM4_HSSPI_RXFIFO8_AVAILABLE               1
#define FM_HSSPI_RXFIFO8_AVAILABLE                1
#define FM4_HSSPI_RXFIFO9_AVAILABLE               1
#define FM_HSSPI_RXFIFO9_AVAILABLE                1
#define FM4_HSSPI_TXC_AVAILABLE                   1
#define FM_HSSPI_TXC_AVAILABLE                    1
#define FM4_HSSPI_TXE_AVAILABLE                   1
#define FM_HSSPI_TXE_AVAILABLE                    1
#define FM4_HSSPI_TXF_AVAILABLE                   1
#define FM_HSSPI_TXF_AVAILABLE                    1
#define FM4_HSSPI_TXFIFO0_AVAILABLE               1
#define FM_HSSPI_TXFIFO0_AVAILABLE                1
#define FM4_HSSPI_TXFIFO1_AVAILABLE               1
#define FM_HSSPI_TXFIFO1_AVAILABLE                1
#define FM4_HSSPI_TXFIFO10_AVAILABLE              1
#define FM_HSSPI_TXFIFO10_AVAILABLE               1
#define FM4_HSSPI_TXFIFO11_AVAILABLE              1
#define FM_HSSPI_TXFIFO11_AVAILABLE               1
#define FM4_HSSPI_TXFIFO12_AVAILABLE              1
#define FM_HSSPI_TXFIFO12_AVAILABLE               1
#define FM4_HSSPI_TXFIFO13_AVAILABLE              1
#define FM_HSSPI_TXFIFO13_AVAILABLE               1
#define FM4_HSSPI_TXFIFO14_AVAILABLE              1
#define FM_HSSPI_TXFIFO14_AVAILABLE               1
#define FM4_HSSPI_TXFIFO15_AVAILABLE              1
#define FM_HSSPI_TXFIFO15_AVAILABLE               1
#define FM4_HSSPI_TXFIFO2_AVAILABLE               1
#define FM_HSSPI_TXFIFO2_AVAILABLE                1
#define FM4_HSSPI_TXFIFO3_AVAILABLE               1
#define FM_HSSPI_TXFIFO3_AVAILABLE                1
#define FM4_HSSPI_TXFIFO4_AVAILABLE               1
#define FM_HSSPI_TXFIFO4_AVAILABLE                1
#define FM4_HSSPI_TXFIFO5_AVAILABLE               1
#define FM_HSSPI_TXFIFO5_AVAILABLE                1
#define FM4_HSSPI_TXFIFO6_AVAILABLE               1
#define FM_HSSPI_TXFIFO6_AVAILABLE                1
#define FM4_HSSPI_TXFIFO7_AVAILABLE               1
#define FM_HSSPI_TXFIFO7_AVAILABLE                1
#define FM4_HSSPI_TXFIFO8_AVAILABLE               1
#define FM_HSSPI_TXFIFO8_AVAILABLE                1
#define FM4_HSSPI_TXFIFO9_AVAILABLE               1
#define FM_HSSPI_TXFIFO9_AVAILABLE                1
#define FM4_HSSPI_WRCSDC0_AVAILABLE               1
#define FM_HSSPI_WRCSDC0_AVAILABLE                1
#define FM4_HSSPI_WRCSDC1_AVAILABLE               1
#define FM_HSSPI_WRCSDC1_AVAILABLE                1
#define FM4_HSSPI_WRCSDC2_AVAILABLE               1
#define FM_HSSPI_WRCSDC2_AVAILABLE                1
#define FM4_HSSPI_WRCSDC3_AVAILABLE               1
#define FM_HSSPI_WRCSDC3_AVAILABLE                1
#define FM4_HSSPI_WRCSDC4_AVAILABLE               1
#define FM_HSSPI_WRCSDC4_AVAILABLE                1
#define FM4_HSSPI_WRCSDC5_AVAILABLE               1
#define FM_HSSPI_WRCSDC5_AVAILABLE                1
#define FM4_HSSPI_WRCSDC6_AVAILABLE               1
#define FM_HSSPI_WRCSDC6_AVAILABLE                1
#define FM4_HSSPI_WRCSDC7_AVAILABLE               1
#define FM_HSSPI_WRCSDC7_AVAILABLE                1
/*******************************************************************************
* HWWDT
*******************************************************************************/
#define FM4_HWWDT_WDG_CTL_AVAILABLE               1
#define FM_HWWDT_WDG_CTL_AVAILABLE                1
#define FM4_HWWDT_WDG_ICL_AVAILABLE               1
#define FM_HWWDT_WDG_ICL_AVAILABLE                1
#define FM4_HWWDT_WDG_LCK_AVAILABLE               1
#define FM_HWWDT_WDG_LCK_AVAILABLE                1
#define FM4_HWWDT_WDG_LDR_AVAILABLE               1
#define FM_HWWDT_WDG_LDR_AVAILABLE                1
#define FM4_HWWDT_WDG_RIS_AVAILABLE               1
#define FM_HWWDT_WDG_RIS_AVAILABLE                1
#define FM4_HWWDT_WDG_VLR_AVAILABLE               1
#define FM_HWWDT_WDG_VLR_AVAILABLE                1
/*******************************************************************************
* I2S0
*******************************************************************************/
#define FM4_I2S_CNTREG_AVAILABLE                  1
#define FM_I2S_CNTREG_AVAILABLE                   1
#define FM4_I2S_DMAACT_AVAILABLE                  1
#define FM_I2S_DMAACT_AVAILABLE                   1
#define FM4_I2S_INTCNT_AVAILABLE                  1
#define FM_I2S_INTCNT_AVAILABLE                   1
#define FM4_I2S_MCR0REG_AVAILABLE                 1
#define FM_I2S_MCR0REG_AVAILABLE                  1
#define FM4_I2S_MCR1REG_AVAILABLE                 1
#define FM_I2S_MCR1REG_AVAILABLE                  1
#define FM4_I2S_MCR2REG_AVAILABLE                 1
#define FM_I2S_MCR2REG_AVAILABLE                  1
#define FM4_I2S_OPRREG_AVAILABLE                  1
#define FM_I2S_OPRREG_AVAILABLE                   1
#define FM4_I2S_RXFDAT_AVAILABLE                  1
#define FM_I2S_RXFDAT_AVAILABLE                   1
#define FM4_I2S_SRST_AVAILABLE                    1
#define FM_I2S_SRST_AVAILABLE                     1
#define FM4_I2S_STATUS_AVAILABLE                  1
#define FM_I2S_STATUS_AVAILABLE                   1
#define FM4_I2S_TSTREG_AVAILABLE                  1
#define FM_I2S_TSTREG_AVAILABLE                   1
#define FM4_I2S_TXFDAT_AVAILABLE                  1
#define FM_I2S_TXFDAT_AVAILABLE                   1
/*******************************************************************************
* I2SPRE
*******************************************************************************/
#define FM4_I2SPRE_ICCR_AVAILABLE                 1
#define FM_I2SPRE_ICCR_AVAILABLE                  1
#define FM4_I2SPRE_IP_STR_AVAILABLE               1
#define FM_I2SPRE_IP_STR_AVAILABLE                1
#define FM4_I2SPRE_IPCR1_AVAILABLE                1
#define FM_I2SPRE_IPCR1_AVAILABLE                 1
#define FM4_I2SPRE_IPCR2_AVAILABLE                1
#define FM_I2SPRE_IPCR2_AVAILABLE                 1
#define FM4_I2SPRE_IPCR3_AVAILABLE                1
#define FM_I2SPRE_IPCR3_AVAILABLE                 1
#define FM4_I2SPRE_IPCR4_AVAILABLE                1
#define FM_I2SPRE_IPCR4_AVAILABLE                 1
#define FM4_I2SPRE_IPCR5_AVAILABLE                1
#define FM_I2SPRE_IPCR5_AVAILABLE                 1
#define FM4_I2SPRE_IPINT_CLR_AVAILABLE            1
#define FM_I2SPRE_IPINT_CLR_AVAILABLE             1
#define FM4_I2SPRE_IPINT_ENR_AVAILABLE            1
#define FM_I2SPRE_IPINT_ENR_AVAILABLE             1
#define FM4_I2SPRE_IPINT_STR_AVAILABLE            1
#define FM_I2SPRE_IPINT_STR_AVAILABLE             1
/*******************************************************************************
* INTREQ
*******************************************************************************/
#define FM4_INTREQ_DRQSEL_AVAILABLE               1
#define FM_INTREQ_DRQSEL_AVAILABLE                1
#define FM4_INTREQ_EXC02MON_AVAILABLE             1
#define FM_INTREQ_EXC02MON_AVAILABLE              1
#define FM4_INTREQ_IRQ000MON_AVAILABLE            1
#define FM_INTREQ_IRQ000MON_AVAILABLE             1
#define FM4_INTREQ_IRQ001MON_AVAILABLE            1
#define FM_INTREQ_IRQ001MON_AVAILABLE             1
#define FM4_INTREQ_IRQ002MON_AVAILABLE            1
#define FM_INTREQ_IRQ002MON_AVAILABLE             1
#define FM4_INTREQ_IRQ003MON_AVAILABLE            1
#define FM_INTREQ_IRQ003MON_AVAILABLE             1
#define FM4_INTREQ_IRQ003SEL_AVAILABLE            1
#define FM_INTREQ_IRQ003SEL_AVAILABLE             1
#define FM4_INTREQ_IRQ004MON_AVAILABLE            1
#define FM_INTREQ_IRQ004MON_AVAILABLE             1
#define FM4_INTREQ_IRQ004SEL_AVAILABLE            1
#define FM_INTREQ_IRQ004SEL_AVAILABLE             1
#define FM4_INTREQ_IRQ005MON_AVAILABLE            1
#define FM_INTREQ_IRQ005MON_AVAILABLE             1
#define FM4_INTREQ_IRQ005SEL_AVAILABLE            1
#define FM_INTREQ_IRQ005SEL_AVAILABLE             1
#define FM4_INTREQ_IRQ006MON_AVAILABLE            1
#define FM_INTREQ_IRQ006MON_AVAILABLE             1
#define FM4_INTREQ_IRQ006SEL_AVAILABLE            1
#define FM_INTREQ_IRQ006SEL_AVAILABLE             1
#define FM4_INTREQ_IRQ007MON_AVAILABLE            1
#define FM_INTREQ_IRQ007MON_AVAILABLE             1
#define FM4_INTREQ_IRQ007SEL_AVAILABLE            1
#define FM_INTREQ_IRQ007SEL_AVAILABLE             1
#define FM4_INTREQ_IRQ008MON_AVAILABLE            1
#define FM_INTREQ_IRQ008MON_AVAILABLE             1
#define FM4_INTREQ_IRQ008SEL_AVAILABLE            1
#define FM_INTREQ_IRQ008SEL_AVAILABLE             1
#define FM4_INTREQ_IRQ009MON_AVAILABLE            1
#define FM_INTREQ_IRQ009MON_AVAILABLE             1
#define FM4_INTREQ_IRQ009SEL_AVAILABLE            1
#define FM_INTREQ_IRQ009SEL_AVAILABLE             1
#define FM4_INTREQ_IRQ010MON_AVAILABLE            1
#define FM_INTREQ_IRQ010MON_AVAILABLE             1
#define FM4_INTREQ_IRQ010SEL_AVAILABLE            1
#define FM_INTREQ_IRQ010SEL_AVAILABLE             1
#define FM4_INTREQ_IRQ011MON_AVAILABLE            1
#define FM_INTREQ_IRQ011MON_AVAILABLE             1
#define FM4_INTREQ_IRQ012MON_AVAILABLE            1
#define FM_INTREQ_IRQ012MON_AVAILABLE             1
#define FM4_INTREQ_IRQ013MON_AVAILABLE            1
#define FM_INTREQ_IRQ013MON_AVAILABLE             1
#define FM4_INTREQ_IRQ014MON_AVAILABLE            1
#define FM_INTREQ_IRQ014MON_AVAILABLE             1
#define FM4_INTREQ_IRQ015MON_AVAILABLE            1
#define FM_INTREQ_IRQ015MON_AVAILABLE             1
#define FM4_INTREQ_IRQ016MON_AVAILABLE            1
#define FM_INTREQ_IRQ016MON_AVAILABLE             1
#define FM4_INTREQ_IRQ017MON_AVAILABLE            1
#define FM_INTREQ_IRQ017MON_AVAILABLE             1
#define FM4_INTREQ_IRQ018MON_AVAILABLE            1
#define FM_INTREQ_IRQ018MON_AVAILABLE             1
#define FM4_INTREQ_IRQ019MON_AVAILABLE            1
#define FM_INTREQ_IRQ019MON_AVAILABLE             1
#define FM4_INTREQ_IRQ020MON_AVAILABLE            1
#define FM_INTREQ_IRQ020MON_AVAILABLE             1
#define FM4_INTREQ_IRQ021MON_AVAILABLE            1
#define FM_INTREQ_IRQ021MON_AVAILABLE             1
#define FM4_INTREQ_IRQ022MON_AVAILABLE            1
#define FM_INTREQ_IRQ022MON_AVAILABLE             1
#define FM4_INTREQ_IRQ023MON_AVAILABLE            1
#define FM_INTREQ_IRQ023MON_AVAILABLE             1
#define FM4_INTREQ_IRQ024MON_AVAILABLE            1
#define FM_INTREQ_IRQ024MON_AVAILABLE             1
#define FM4_INTREQ_IRQ025MON_AVAILABLE            1
#define FM_INTREQ_IRQ025MON_AVAILABLE             1
#define FM4_INTREQ_IRQ026MON_AVAILABLE            1
#define FM_INTREQ_IRQ026MON_AVAILABLE             1
#define FM4_INTREQ_IRQ027MON_AVAILABLE            1
#define FM_INTREQ_IRQ027MON_AVAILABLE             1
#define FM4_INTREQ_IRQ028MON_AVAILABLE            1
#define FM_INTREQ_IRQ028MON_AVAILABLE             1
#define FM4_INTREQ_IRQ029MON_AVAILABLE            1
#define FM_INTREQ_IRQ029MON_AVAILABLE             1
#define FM4_INTREQ_IRQ030MON_AVAILABLE            1
#define FM_INTREQ_IRQ030MON_AVAILABLE             1
#define FM4_INTREQ_IRQ031MON_AVAILABLE            1
#define FM_INTREQ_IRQ031MON_AVAILABLE             1
#define FM4_INTREQ_IRQ032MON_AVAILABLE            1
#define FM_INTREQ_IRQ032MON_AVAILABLE             1
#define FM4_INTREQ_IRQ033MON_AVAILABLE            1
#define FM_INTREQ_IRQ033MON_AVAILABLE             1
#define FM4_INTREQ_IRQ034MON_AVAILABLE            1
#define FM_INTREQ_IRQ034MON_AVAILABLE             1
#define FM4_INTREQ_IRQ035MON_AVAILABLE            1
#define FM_INTREQ_IRQ035MON_AVAILABLE             1
#define FM4_INTREQ_IRQ036MON_AVAILABLE            1
#define FM_INTREQ_IRQ036MON_AVAILABLE             1
#define FM4_INTREQ_IRQ037MON_AVAILABLE            1
#define FM_INTREQ_IRQ037MON_AVAILABLE             1
#define FM4_INTREQ_IRQ038MON_AVAILABLE            1
#define FM_INTREQ_IRQ038MON_AVAILABLE             1
#define FM4_INTREQ_IRQ039MON_AVAILABLE            1
#define FM_INTREQ_IRQ039MON_AVAILABLE             1
#define FM4_INTREQ_IRQ040MON_AVAILABLE            1
#define FM_INTREQ_IRQ040MON_AVAILABLE             1
#define FM4_INTREQ_IRQ041MON_AVAILABLE            1
#define FM_INTREQ_IRQ041MON_AVAILABLE             1
#define FM4_INTREQ_IRQ042MON_AVAILABLE            1
#define FM_INTREQ_IRQ042MON_AVAILABLE             1
#define FM4_INTREQ_IRQ043MON_AVAILABLE            1
#define FM_INTREQ_IRQ043MON_AVAILABLE             1
#define FM4_INTREQ_IRQ044MON_AVAILABLE            1
#define FM_INTREQ_IRQ044MON_AVAILABLE             1
#define FM4_INTREQ_IRQ045MON_AVAILABLE            1
#define FM_INTREQ_IRQ045MON_AVAILABLE             1
#define FM4_INTREQ_IRQ046MON_AVAILABLE            1
#define FM_INTREQ_IRQ046MON_AVAILABLE             1
#define FM4_INTREQ_IRQ047MON_AVAILABLE            1
#define FM_INTREQ_IRQ047MON_AVAILABLE             1
#define FM4_INTREQ_IRQ048MON_AVAILABLE            1
#define FM_INTREQ_IRQ048MON_AVAILABLE             1
#define FM4_INTREQ_IRQ049MON_AVAILABLE            1
#define FM_INTREQ_IRQ049MON_AVAILABLE             1
#define FM4_INTREQ_IRQ050MON_AVAILABLE            1
#define FM_INTREQ_IRQ050MON_AVAILABLE             1
#define FM4_INTREQ_IRQ051MON_AVAILABLE            1
#define FM_INTREQ_IRQ051MON_AVAILABLE             1
#define FM4_INTREQ_IRQ052MON_AVAILABLE            1
#define FM_INTREQ_IRQ052MON_AVAILABLE             1
#define FM4_INTREQ_IRQ053MON_AVAILABLE            1
#define FM_INTREQ_IRQ053MON_AVAILABLE             1
#define FM4_INTREQ_IRQ054MON_AVAILABLE            1
#define FM_INTREQ_IRQ054MON_AVAILABLE             1
#define FM4_INTREQ_IRQ055MON_AVAILABLE            1
#define FM_INTREQ_IRQ055MON_AVAILABLE             1
#define FM4_INTREQ_IRQ056MON_AVAILABLE            1
#define FM_INTREQ_IRQ056MON_AVAILABLE             1
#define FM4_INTREQ_IRQ057MON_AVAILABLE            1
#define FM_INTREQ_IRQ057MON_AVAILABLE             1
#define FM4_INTREQ_IRQ058MON_AVAILABLE            1
#define FM_INTREQ_IRQ058MON_AVAILABLE             1
#define FM4_INTREQ_IRQ059MON_AVAILABLE            1
#define FM_INTREQ_IRQ059MON_AVAILABLE             1
#define FM4_INTREQ_IRQ060MON_AVAILABLE            1
#define FM_INTREQ_IRQ060MON_AVAILABLE             1
#define FM4_INTREQ_IRQ061MON_AVAILABLE            1
#define FM_INTREQ_IRQ061MON_AVAILABLE             1
#define FM4_INTREQ_IRQ062MON_AVAILABLE            1
#define FM_INTREQ_IRQ062MON_AVAILABLE             1
#define FM4_INTREQ_IRQ063MON_AVAILABLE            1
#define FM_INTREQ_IRQ063MON_AVAILABLE             1
#define FM4_INTREQ_IRQ064MON_AVAILABLE            1
#define FM_INTREQ_IRQ064MON_AVAILABLE             1
#define FM4_INTREQ_IRQ065MON_AVAILABLE            1
#define FM_INTREQ_IRQ065MON_AVAILABLE             1
#define FM4_INTREQ_IRQ066MON_AVAILABLE            1
#define FM_INTREQ_IRQ066MON_AVAILABLE             1
#define FM4_INTREQ_IRQ067MON_AVAILABLE            1
#define FM_INTREQ_IRQ067MON_AVAILABLE             1
#define FM4_INTREQ_IRQ068MON_AVAILABLE            1
#define FM_INTREQ_IRQ068MON_AVAILABLE             1
#define FM4_INTREQ_IRQ069MON_AVAILABLE            1
#define FM_INTREQ_IRQ069MON_AVAILABLE             1
#define FM4_INTREQ_IRQ070MON_AVAILABLE            1
#define FM_INTREQ_IRQ070MON_AVAILABLE             1
#define FM4_INTREQ_IRQ071MON_AVAILABLE            1
#define FM_INTREQ_IRQ071MON_AVAILABLE             1
#define FM4_INTREQ_IRQ072MON_AVAILABLE            1
#define FM_INTREQ_IRQ072MON_AVAILABLE             1
#define FM4_INTREQ_IRQ073MON_AVAILABLE            1
#define FM_INTREQ_IRQ073MON_AVAILABLE             1
#define FM4_INTREQ_IRQ074MON_AVAILABLE            1
#define FM_INTREQ_IRQ074MON_AVAILABLE             1
#define FM4_INTREQ_IRQ075MON_AVAILABLE            1
#define FM_INTREQ_IRQ075MON_AVAILABLE             1
#define FM4_INTREQ_IRQ076MON_AVAILABLE            1
#define FM_INTREQ_IRQ076MON_AVAILABLE             1
#define FM4_INTREQ_IRQ077MON_AVAILABLE            1
#define FM_INTREQ_IRQ077MON_AVAILABLE             1
#define FM4_INTREQ_IRQ078MON_AVAILABLE            1
#define FM_INTREQ_IRQ078MON_AVAILABLE             1
#define FM4_INTREQ_IRQ079MON_AVAILABLE            1
#define FM_INTREQ_IRQ079MON_AVAILABLE             1
#define FM4_INTREQ_IRQ080MON_AVAILABLE            1
#define FM_INTREQ_IRQ080MON_AVAILABLE             1
#define FM4_INTREQ_IRQ081MON_AVAILABLE            1
#define FM_INTREQ_IRQ081MON_AVAILABLE             1
#define FM4_INTREQ_IRQ082MON_AVAILABLE            1
#define FM_INTREQ_IRQ082MON_AVAILABLE             1
#define FM4_INTREQ_IRQ083MON_AVAILABLE            1
#define FM_INTREQ_IRQ083MON_AVAILABLE             1
#define FM4_INTREQ_IRQ084MON_AVAILABLE            1
#define FM_INTREQ_IRQ084MON_AVAILABLE             1
#define FM4_INTREQ_IRQ085MON_AVAILABLE            1
#define FM_INTREQ_IRQ085MON_AVAILABLE             1
#define FM4_INTREQ_IRQ086MON_AVAILABLE            1
#define FM_INTREQ_IRQ086MON_AVAILABLE             1
#define FM4_INTREQ_IRQ087MON_AVAILABLE            1
#define FM_INTREQ_IRQ087MON_AVAILABLE             1
#define FM4_INTREQ_IRQ088MON_AVAILABLE            1
#define FM_INTREQ_IRQ088MON_AVAILABLE             1
#define FM4_INTREQ_IRQ089MON_AVAILABLE            1
#define FM_INTREQ_IRQ089MON_AVAILABLE             1
#define FM4_INTREQ_IRQ090MON_AVAILABLE            1
#define FM_INTREQ_IRQ090MON_AVAILABLE             1
#define FM4_INTREQ_IRQ091MON_AVAILABLE            1
#define FM_INTREQ_IRQ091MON_AVAILABLE             1
#define FM4_INTREQ_IRQ092MON_AVAILABLE            1
#define FM_INTREQ_IRQ092MON_AVAILABLE             1
#define FM4_INTREQ_IRQ093MON_AVAILABLE            1
#define FM_INTREQ_IRQ093MON_AVAILABLE             1
#define FM4_INTREQ_IRQ094MON_AVAILABLE            1
#define FM_INTREQ_IRQ094MON_AVAILABLE             1
#define FM4_INTREQ_IRQ095MON_AVAILABLE            1
#define FM_INTREQ_IRQ095MON_AVAILABLE             1
#define FM4_INTREQ_IRQ096MON_AVAILABLE            1
#define FM_INTREQ_IRQ096MON_AVAILABLE             1
#define FM4_INTREQ_IRQ097MON_AVAILABLE            1
#define FM_INTREQ_IRQ097MON_AVAILABLE             1
#define FM4_INTREQ_IRQ098MON_AVAILABLE            1
#define FM_INTREQ_IRQ098MON_AVAILABLE             1
#define FM4_INTREQ_IRQ099MON_AVAILABLE            1
#define FM_INTREQ_IRQ099MON_AVAILABLE             1
#define FM4_INTREQ_IRQ100MON_AVAILABLE            1
#define FM_INTREQ_IRQ100MON_AVAILABLE             1
#define FM4_INTREQ_IRQ101MON_AVAILABLE            1
#define FM_INTREQ_IRQ101MON_AVAILABLE             1
#define FM4_INTREQ_IRQ102MON_AVAILABLE            1
#define FM_INTREQ_IRQ102MON_AVAILABLE             1
#define FM4_INTREQ_IRQ103MON_AVAILABLE            1
#define FM_INTREQ_IRQ103MON_AVAILABLE             1
#define FM4_INTREQ_IRQ104MON_AVAILABLE            1
#define FM_INTREQ_IRQ104MON_AVAILABLE             1
#define FM4_INTREQ_IRQ105MON_AVAILABLE            1
#define FM_INTREQ_IRQ105MON_AVAILABLE             1
#define FM4_INTREQ_IRQ106MON_AVAILABLE            1
#define FM_INTREQ_IRQ106MON_AVAILABLE             1
#define FM4_INTREQ_IRQ107MON_AVAILABLE            1
#define FM_INTREQ_IRQ107MON_AVAILABLE             1
#define FM4_INTREQ_IRQ108MON_AVAILABLE            1
#define FM_INTREQ_IRQ108MON_AVAILABLE             1
#define FM4_INTREQ_IRQ109MON_AVAILABLE            1
#define FM_INTREQ_IRQ109MON_AVAILABLE             1
#define FM4_INTREQ_IRQ110MON_AVAILABLE            1
#define FM_INTREQ_IRQ110MON_AVAILABLE             1
#define FM4_INTREQ_IRQ111MON_AVAILABLE            1
#define FM_INTREQ_IRQ111MON_AVAILABLE             1
#define FM4_INTREQ_IRQ112MON_AVAILABLE            1
#define FM_INTREQ_IRQ112MON_AVAILABLE             1
#define FM4_INTREQ_IRQ113MON_AVAILABLE            1
#define FM_INTREQ_IRQ113MON_AVAILABLE             1
#define FM4_INTREQ_IRQ114MON_AVAILABLE            1
#define FM_INTREQ_IRQ114MON_AVAILABLE             1
#define FM4_INTREQ_IRQ115MON_AVAILABLE            1
#define FM_INTREQ_IRQ115MON_AVAILABLE             1
#define FM4_INTREQ_IRQ116MON_AVAILABLE            1
#define FM_INTREQ_IRQ116MON_AVAILABLE             1
#define FM4_INTREQ_IRQ117MON_AVAILABLE            1
#define FM_INTREQ_IRQ117MON_AVAILABLE             1
#define FM4_INTREQ_IRQ118MON_AVAILABLE            1
#define FM_INTREQ_IRQ118MON_AVAILABLE             1
#define FM4_INTREQ_IRQ119MON_AVAILABLE            1
#define FM_INTREQ_IRQ119MON_AVAILABLE             1
#define FM4_INTREQ_IRQ120MON_AVAILABLE            1
#define FM_INTREQ_IRQ120MON_AVAILABLE             1
#define FM4_INTREQ_IRQ121MON_AVAILABLE            1
#define FM_INTREQ_IRQ121MON_AVAILABLE             1
#define FM4_INTREQ_IRQ122MON_AVAILABLE            1
#define FM_INTREQ_IRQ122MON_AVAILABLE             1
#define FM4_INTREQ_IRQ123MON_AVAILABLE            1
#define FM_INTREQ_IRQ123MON_AVAILABLE             1
#define FM4_INTREQ_IRQ124MON_AVAILABLE            1
#define FM_INTREQ_IRQ124MON_AVAILABLE             1
#define FM4_INTREQ_IRQ125MON_AVAILABLE            1
#define FM_INTREQ_IRQ125MON_AVAILABLE             1
#define FM4_INTREQ_IRQ126MON_AVAILABLE            1
#define FM_INTREQ_IRQ126MON_AVAILABLE             1
#define FM4_INTREQ_IRQ127MON_AVAILABLE            1
#define FM_INTREQ_IRQ127MON_AVAILABLE             1
#define FM4_INTREQ_ODDPKS_AVAILABLE               1
#define FM_INTREQ_ODDPKS_AVAILABLE                1
#define FM4_INTREQ_ODDPKS1_AVAILABLE              1
#define FM_INTREQ_ODDPKS1_AVAILABLE               1
/*******************************************************************************
* LSCRP
*******************************************************************************/
#define FM4_LSCRP_LCR_PRSLD_AVAILABLE             1
#define FM_LSCRP_LCR_PRSLD_AVAILABLE              1
/*******************************************************************************
* LVD
*******************************************************************************/
#define FM4_LVD_LVD_CLR_AVAILABLE                 1
#define FM_LVD_LVD_CLR_AVAILABLE                  1
#define FM4_LVD_LVD_CTL_AVAILABLE                 1
#define FM_LVD_LVD_CTL_AVAILABLE                  1
#define FM4_LVD_LVD_RLR_AVAILABLE                 1
#define FM_LVD_LVD_RLR_AVAILABLE                  1
#define FM4_LVD_LVD_STR_AVAILABLE                 1
#define FM_LVD_LVD_STR_AVAILABLE                  1
#define FM4_LVD_LVD_STR2_AVAILABLE                1
#define FM_LVD_LVD_STR2_AVAILABLE                 1
/*******************************************************************************
* MFS0
*******************************************************************************/
#define FM4_MFS_CSIO_BGR_AVAILABLE                1
#define FM_MFS_CSIO_BGR_AVAILABLE                 1
#define FM4_MFS_CSIO_ESCR_AVAILABLE               1
#define FM_MFS_CSIO_ESCR_AVAILABLE                1
#define FM4_MFS_CSIO_FBYTE1_AVAILABLE             1
#define FM_MFS_CSIO_FBYTE1_AVAILABLE              1
#define FM4_MFS_CSIO_FBYTE2_AVAILABLE             1
#define FM_MFS_CSIO_FBYTE2_AVAILABLE              1
#define FM4_MFS_CSIO_FCR_AVAILABLE                1
#define FM_MFS_CSIO_FCR_AVAILABLE                 1
#define FM4_MFS_CSIO_RDR_AVAILABLE                1
#define FM_MFS_CSIO_RDR_AVAILABLE                 1
#define FM4_MFS_CSIO_SACSR_AVAILABLE              1
#define FM_MFS_CSIO_SACSR_AVAILABLE               1
#define FM4_MFS_CSIO_SCR_AVAILABLE                1
#define FM_MFS_CSIO_SCR_AVAILABLE                 1
#define FM4_MFS_CSIO_SCSCR_AVAILABLE              1
#define FM_MFS_CSIO_SCSCR_AVAILABLE               1
#define FM4_MFS_CSIO_SCSFR0_AVAILABLE             1
#define FM_MFS_CSIO_SCSFR0_AVAILABLE              1
#define FM4_MFS_CSIO_SCSFR1_AVAILABLE             1
#define FM_MFS_CSIO_SCSFR1_AVAILABLE              1
#define FM4_MFS_CSIO_SCSFR2_AVAILABLE             1
#define FM_MFS_CSIO_SCSFR2_AVAILABLE              1
#define FM4_MFS_CSIO_SCSTR0_AVAILABLE             1
#define FM_MFS_CSIO_SCSTR0_AVAILABLE              1
#define FM4_MFS_CSIO_SCSTR1_AVAILABLE             1
#define FM_MFS_CSIO_SCSTR1_AVAILABLE              1
#define FM4_MFS_CSIO_SCSTR32_AVAILABLE            1
#define FM_MFS_CSIO_SCSTR32_AVAILABLE             1
#define FM4_MFS_CSIO_SMR_AVAILABLE                1
#define FM_MFS_CSIO_SMR_AVAILABLE                 1
#define FM4_MFS_CSIO_SSR_AVAILABLE                1
#define FM_MFS_CSIO_SSR_AVAILABLE                 1
#define FM4_MFS_CSIO_STMCR_AVAILABLE              1
#define FM_MFS_CSIO_STMCR_AVAILABLE               1
#define FM4_MFS_CSIO_STMR_AVAILABLE               1
#define FM_MFS_CSIO_STMR_AVAILABLE                1
#define FM4_MFS_CSIO_TBYTE0_AVAILABLE             1
#define FM_MFS_CSIO_TBYTE0_AVAILABLE              1
#define FM4_MFS_CSIO_TBYTE1_AVAILABLE             1
#define FM_MFS_CSIO_TBYTE1_AVAILABLE              1
#define FM4_MFS_CSIO_TBYTE2_AVAILABLE             1
#define FM_MFS_CSIO_TBYTE2_AVAILABLE              1
#define FM4_MFS_CSIO_TBYTE3_AVAILABLE             1
#define FM_MFS_CSIO_TBYTE3_AVAILABLE              1
#define FM4_MFS_CSIO_TDR_AVAILABLE                1
#define FM_MFS_CSIO_TDR_AVAILABLE                 1
#define FM4_MFS_I2C_BGR_AVAILABLE                 1
#define FM_MFS_I2C_BGR_AVAILABLE                  1
#define FM4_MFS_I2C_EIBCR_AVAILABLE               1
#define FM_MFS_I2C_EIBCR_AVAILABLE                1
#define FM4_MFS_I2C_FBYTE1_AVAILABLE              1
#define FM_MFS_I2C_FBYTE1_AVAILABLE               1
#define FM4_MFS_I2C_FBYTE2_AVAILABLE              1
#define FM_MFS_I2C_FBYTE2_AVAILABLE               1
#define FM4_MFS_I2C_FCR_AVAILABLE                 1
#define FM_MFS_I2C_FCR_AVAILABLE                  1
#define FM4_MFS_I2C_IBCR_AVAILABLE                1
#define FM_MFS_I2C_IBCR_AVAILABLE                 1
#define FM4_MFS_I2C_IBSR_AVAILABLE                1
#define FM_MFS_I2C_IBSR_AVAILABLE                 1
#define FM4_MFS_I2C_ISBA_AVAILABLE                1
#define FM_MFS_I2C_ISBA_AVAILABLE                 1
#define FM4_MFS_I2C_ISMK_AVAILABLE                1
#define FM_MFS_I2C_ISMK_AVAILABLE                 1
#define FM4_MFS_I2C_NFCR_AVAILABLE                1
#define FM_MFS_I2C_NFCR_AVAILABLE                 1
#define FM4_MFS_I2C_RDR_AVAILABLE                 1
#define FM_MFS_I2C_RDR_AVAILABLE                  1
#define FM4_MFS_I2C_SMR_AVAILABLE                 1
#define FM_MFS_I2C_SMR_AVAILABLE                  1
#define FM4_MFS_I2C_SSR_AVAILABLE                 1
#define FM_MFS_I2C_SSR_AVAILABLE                  1
#define FM4_MFS_I2C_TDR_AVAILABLE                 1
#define FM_MFS_I2C_TDR_AVAILABLE                  1
#define FM4_MFS_LIN_BGR_AVAILABLE                 1
#define FM_MFS_LIN_BGR_AVAILABLE                  1
#define FM4_MFS_LIN_ESCR_AVAILABLE                1
#define FM_MFS_LIN_ESCR_AVAILABLE                 1
#define FM4_MFS_LIN_FBYTE1_AVAILABLE              1
#define FM_MFS_LIN_FBYTE1_AVAILABLE               1
#define FM4_MFS_LIN_FBYTE2_AVAILABLE              1
#define FM_MFS_LIN_FBYTE2_AVAILABLE               1
#define FM4_MFS_LIN_FCR_AVAILABLE                 1
#define FM_MFS_LIN_FCR_AVAILABLE                  1
#define FM4_MFS_LIN_RDR_AVAILABLE                 1
#define FM_MFS_LIN_RDR_AVAILABLE                  1
#define FM4_MFS_LIN_SCR_AVAILABLE                 1
#define FM_MFS_LIN_SCR_AVAILABLE                  1
#define FM4_MFS_LIN_SMR_AVAILABLE                 1
#define FM_MFS_LIN_SMR_AVAILABLE                  1
#define FM4_MFS_LIN_SSR_AVAILABLE                 1
#define FM_MFS_LIN_SSR_AVAILABLE                  1
#define FM4_MFS_LIN_TDR_AVAILABLE                 1
#define FM_MFS_LIN_TDR_AVAILABLE                  1
#define FM4_MFS_UART_BGR_AVAILABLE                1
#define FM_MFS_UART_BGR_AVAILABLE                 1
#define FM4_MFS_UART_ESCR_AVAILABLE               1
#define FM_MFS_UART_ESCR_AVAILABLE                1
#define FM4_MFS_UART_FBYTE1_AVAILABLE             1
#define FM_MFS_UART_FBYTE1_AVAILABLE              1
#define FM4_MFS_UART_FBYTE2_AVAILABLE             1
#define FM_MFS_UART_FBYTE2_AVAILABLE              1
#define FM4_MFS_UART_FCR_AVAILABLE                1
#define FM_MFS_UART_FCR_AVAILABLE                 1
#define FM4_MFS_UART_RDR_AVAILABLE                1
#define FM_MFS_UART_RDR_AVAILABLE                 1
#define FM4_MFS_UART_SCR_AVAILABLE                1
#define FM_MFS_UART_SCR_AVAILABLE                 1
#define FM4_MFS_UART_SMR_AVAILABLE                1
#define FM_MFS_UART_SMR_AVAILABLE                 1
#define FM4_MFS_UART_SSR_AVAILABLE                1
#define FM_MFS_UART_SSR_AVAILABLE                 1
#define FM4_MFS_UART_TDR_AVAILABLE                1
#define FM_MFS_UART_TDR_AVAILABLE                 1
/*******************************************************************************
* MFT0
*******************************************************************************/
#define FM4_MFT_ADCMP_ACFS10_AVAILABLE            1
#define FM_MFT_ADCMP_ACFS10_AVAILABLE             1
#define FM4_MFT_ADCMP_ACFS32_AVAILABLE            1
#define FM_MFT_ADCMP_ACFS32_AVAILABLE             1
#define FM4_MFT_ADCMP_ACFS54_AVAILABLE            1
#define FM_MFT_ADCMP_ACFS54_AVAILABLE             1
#define FM4_MFT_ADCMP_ACMC0_AVAILABLE             1
#define FM_MFT_ADCMP_ACMC0_AVAILABLE              1
#define FM4_MFT_ADCMP_ACMC1_AVAILABLE             1
#define FM_MFT_ADCMP_ACMC1_AVAILABLE              1
#define FM4_MFT_ADCMP_ACMC2_AVAILABLE             1
#define FM_MFT_ADCMP_ACMC2_AVAILABLE              1
#define FM4_MFT_ADCMP_ACMC3_AVAILABLE             1
#define FM_MFT_ADCMP_ACMC3_AVAILABLE              1
#define FM4_MFT_ADCMP_ACMC4_AVAILABLE             1
#define FM_MFT_ADCMP_ACMC4_AVAILABLE              1
#define FM4_MFT_ADCMP_ACMC5_AVAILABLE             1
#define FM_MFT_ADCMP_ACMC5_AVAILABLE              1
#define FM4_MFT_ADCMP_ACMP0_AVAILABLE             1
#define FM_MFT_ADCMP_ACMP0_AVAILABLE              1
#define FM4_MFT_ADCMP_ACMP1_AVAILABLE             1
#define FM_MFT_ADCMP_ACMP1_AVAILABLE              1
#define FM4_MFT_ADCMP_ACMP2_AVAILABLE             1
#define FM_MFT_ADCMP_ACMP2_AVAILABLE              1
#define FM4_MFT_ADCMP_ACMP3_AVAILABLE             1
#define FM_MFT_ADCMP_ACMP3_AVAILABLE              1
#define FM4_MFT_ADCMP_ACMP4_AVAILABLE             1
#define FM_MFT_ADCMP_ACMP4_AVAILABLE              1
#define FM4_MFT_ADCMP_ACMP5_AVAILABLE             1
#define FM_MFT_ADCMP_ACMP5_AVAILABLE              1
#define FM4_MFT_ADCMP_ACSA_AVAILABLE              1
#define FM_MFT_ADCMP_ACSA_AVAILABLE               1
#define FM4_MFT_ADCMP_ACSC0_AVAILABLE             1
#define FM_MFT_ADCMP_ACSC0_AVAILABLE              1
#define FM4_MFT_ADCMP_ACSC1_AVAILABLE             1
#define FM_MFT_ADCMP_ACSC1_AVAILABLE              1
#define FM4_MFT_ADCMP_ACSC2_AVAILABLE             1
#define FM_MFT_ADCMP_ACSC2_AVAILABLE              1
#define FM4_MFT_ADCMP_ACSC3_AVAILABLE             1
#define FM_MFT_ADCMP_ACSC3_AVAILABLE              1
#define FM4_MFT_ADCMP_ACSC4_AVAILABLE             1
#define FM_MFT_ADCMP_ACSC4_AVAILABLE              1
#define FM4_MFT_ADCMP_ACSC5_AVAILABLE             1
#define FM_MFT_ADCMP_ACSC5_AVAILABLE              1
#define FM4_MFT_ADCMP_ACSD0_AVAILABLE             1
#define FM_MFT_ADCMP_ACSD0_AVAILABLE              1
#define FM4_MFT_ADCMP_ACSD1_AVAILABLE             1
#define FM_MFT_ADCMP_ACSD1_AVAILABLE              1
#define FM4_MFT_ADCMP_ACSD2_AVAILABLE             1
#define FM_MFT_ADCMP_ACSD2_AVAILABLE              1
#define FM4_MFT_ADCMP_ACSD3_AVAILABLE             1
#define FM_MFT_ADCMP_ACSD3_AVAILABLE              1
#define FM4_MFT_ADCMP_ACSD4_AVAILABLE             1
#define FM_MFT_ADCMP_ACSD4_AVAILABLE              1
#define FM4_MFT_ADCMP_ACSD5_AVAILABLE             1
#define FM_MFT_ADCMP_ACSD5_AVAILABLE              1
#define FM4_MFT_FRT_TCAL_AVAILABLE                1
#define FM_MFT_FRT_TCAL_AVAILABLE                 1
#define FM4_MFT_FRT_TCCP0_AVAILABLE               1
#define FM_MFT_FRT_TCCP0_AVAILABLE                1
#define FM4_MFT_FRT_TCCP1_AVAILABLE               1
#define FM_MFT_FRT_TCCP1_AVAILABLE                1
#define FM4_MFT_FRT_TCCP2_AVAILABLE               1
#define FM_MFT_FRT_TCCP2_AVAILABLE                1
#define FM4_MFT_FRT_TCDT0_AVAILABLE               1
#define FM_MFT_FRT_TCDT0_AVAILABLE                1
#define FM4_MFT_FRT_TCDT1_AVAILABLE               1
#define FM_MFT_FRT_TCDT1_AVAILABLE                1
#define FM4_MFT_FRT_TCDT2_AVAILABLE               1
#define FM_MFT_FRT_TCDT2_AVAILABLE                1
#define FM4_MFT_FRT_TCSA0_AVAILABLE               1
#define FM_MFT_FRT_TCSA0_AVAILABLE                1
#define FM4_MFT_FRT_TCSA1_AVAILABLE               1
#define FM_MFT_FRT_TCSA1_AVAILABLE                1
#define FM4_MFT_FRT_TCSA2_AVAILABLE               1
#define FM_MFT_FRT_TCSA2_AVAILABLE                1
#define FM4_MFT_FRT_TCSC0_AVAILABLE               1
#define FM_MFT_FRT_TCSC0_AVAILABLE                1
#define FM4_MFT_FRT_TCSC1_AVAILABLE               1
#define FM_MFT_FRT_TCSC1_AVAILABLE                1
#define FM4_MFT_FRT_TCSC2_AVAILABLE               1
#define FM_MFT_FRT_TCSC2_AVAILABLE                1
#define FM4_MFT_FRT_TCSD_AVAILABLE                1
#define FM_MFT_FRT_TCSD_AVAILABLE                 1
#define FM4_MFT_ICU_ICCP0_AVAILABLE               1
#define FM_MFT_ICU_ICCP0_AVAILABLE                1
#define FM4_MFT_ICU_ICCP1_AVAILABLE               1
#define FM_MFT_ICU_ICCP1_AVAILABLE                1
#define FM4_MFT_ICU_ICCP2_AVAILABLE               1
#define FM_MFT_ICU_ICCP2_AVAILABLE                1
#define FM4_MFT_ICU_ICCP3_AVAILABLE               1
#define FM_MFT_ICU_ICCP3_AVAILABLE                1
#define FM4_MFT_ICU_ICFS10_AVAILABLE              1
#define FM_MFT_ICU_ICFS10_AVAILABLE               1
#define FM4_MFT_ICU_ICFS32_AVAILABLE              1
#define FM_MFT_ICU_ICFS32_AVAILABLE               1
#define FM4_MFT_ICU_ICSA10_AVAILABLE              1
#define FM_MFT_ICU_ICSA10_AVAILABLE               1
#define FM4_MFT_ICU_ICSA32_AVAILABLE              1
#define FM_MFT_ICU_ICSA32_AVAILABLE               1
#define FM4_MFT_ICU_ICSB10_AVAILABLE              1
#define FM_MFT_ICU_ICSB10_AVAILABLE               1
#define FM4_MFT_ICU_ICSB32_AVAILABLE              1
#define FM_MFT_ICU_ICSB32_AVAILABLE               1
#define FM4_MFT_OCU_OCCP0_AVAILABLE               1
#define FM_MFT_OCU_OCCP0_AVAILABLE                1
#define FM4_MFT_OCU_OCCP1_AVAILABLE               1
#define FM_MFT_OCU_OCCP1_AVAILABLE                1
#define FM4_MFT_OCU_OCCP2_AVAILABLE               1
#define FM_MFT_OCU_OCCP2_AVAILABLE                1
#define FM4_MFT_OCU_OCCP3_AVAILABLE               1
#define FM_MFT_OCU_OCCP3_AVAILABLE                1
#define FM4_MFT_OCU_OCCP4_AVAILABLE               1
#define FM_MFT_OCU_OCCP4_AVAILABLE                1
#define FM4_MFT_OCU_OCCP5_AVAILABLE               1
#define FM_MFT_OCU_OCCP5_AVAILABLE                1
#define FM4_MFT_OCU_OCFS10_AVAILABLE              1
#define FM_MFT_OCU_OCFS10_AVAILABLE               1
#define FM4_MFT_OCU_OCFS32_AVAILABLE              1
#define FM_MFT_OCU_OCFS32_AVAILABLE               1
#define FM4_MFT_OCU_OCFS54_AVAILABLE              1
#define FM_MFT_OCU_OCFS54_AVAILABLE               1
#define FM4_MFT_OCU_OCSA10_AVAILABLE              1
#define FM_MFT_OCU_OCSA10_AVAILABLE               1
#define FM4_MFT_OCU_OCSA32_AVAILABLE              1
#define FM_MFT_OCU_OCSA32_AVAILABLE               1
#define FM4_MFT_OCU_OCSA54_AVAILABLE              1
#define FM_MFT_OCU_OCSA54_AVAILABLE               1
#define FM4_MFT_OCU_OCSB10_AVAILABLE              1
#define FM_MFT_OCU_OCSB10_AVAILABLE               1
#define FM4_MFT_OCU_OCSB32_AVAILABLE              1
#define FM_MFT_OCU_OCSB32_AVAILABLE               1
#define FM4_MFT_OCU_OCSB54_AVAILABLE              1
#define FM_MFT_OCU_OCSB54_AVAILABLE               1
#define FM4_MFT_OCU_OCSC_AVAILABLE                1
#define FM_MFT_OCU_OCSC_AVAILABLE                 1
#define FM4_MFT_OCU_OCSD10_AVAILABLE              1
#define FM_MFT_OCU_OCSD10_AVAILABLE               1
#define FM4_MFT_OCU_OCSD32_AVAILABLE              1
#define FM_MFT_OCU_OCSD32_AVAILABLE               1
#define FM4_MFT_OCU_OCSD54_AVAILABLE              1
#define FM_MFT_OCU_OCSD54_AVAILABLE               1
#define FM4_MFT_OCU_OCSE0_AVAILABLE               1
#define FM_MFT_OCU_OCSE0_AVAILABLE                1
#define FM4_MFT_OCU_OCSE1_AVAILABLE               1
#define FM_MFT_OCU_OCSE1_AVAILABLE                1
#define FM4_MFT_OCU_OCSE2_AVAILABLE               1
#define FM_MFT_OCU_OCSE2_AVAILABLE                1
#define FM4_MFT_OCU_OCSE3_AVAILABLE               1
#define FM_MFT_OCU_OCSE3_AVAILABLE                1
#define FM4_MFT_OCU_OCSE4_AVAILABLE               1
#define FM_MFT_OCU_OCSE4_AVAILABLE                1
#define FM4_MFT_OCU_OCSE5_AVAILABLE               1
#define FM_MFT_OCU_OCSE5_AVAILABLE                1
#define FM4_MFT_WFG_NZCL_AVAILABLE                1
#define FM_MFT_WFG_NZCL_AVAILABLE                 1
#define FM4_MFT_WFG_WFIR_AVAILABLE                1
#define FM_MFT_WFG_WFIR_AVAILABLE                 1
#define FM4_MFT_WFG_WFSA10_AVAILABLE              1
#define FM_MFT_WFG_WFSA10_AVAILABLE               1
#define FM4_MFT_WFG_WFSA32_AVAILABLE              1
#define FM_MFT_WFG_WFSA32_AVAILABLE               1
#define FM4_MFT_WFG_WFSA54_AVAILABLE              1
#define FM_MFT_WFG_WFSA54_AVAILABLE               1
#define FM4_MFT_WFG_WFTA10_AVAILABLE              1
#define FM_MFT_WFG_WFTA10_AVAILABLE               1
#define FM4_MFT_WFG_WFTA32_AVAILABLE              1
#define FM_MFT_WFG_WFTA32_AVAILABLE               1
#define FM4_MFT_WFG_WFTA54_AVAILABLE              1
#define FM_MFT_WFG_WFTA54_AVAILABLE               1
#define FM4_MFT_WFG_WFTB10_AVAILABLE              1
#define FM_MFT_WFG_WFTB10_AVAILABLE               1
#define FM4_MFT_WFG_WFTB32_AVAILABLE              1
#define FM_MFT_WFG_WFTB32_AVAILABLE               1
#define FM4_MFT_WFG_WFTB54_AVAILABLE              1
#define FM_MFT_WFG_WFTB54_AVAILABLE               1
#define FM4_MFT_WFG_WFTF10_AVAILABLE              1
#define FM_MFT_WFG_WFTF10_AVAILABLE               1
#define FM4_MFT_WFG_WFTF32_AVAILABLE              1
#define FM_MFT_WFG_WFTF32_AVAILABLE               1
#define FM4_MFT_WFG_WFTF54_AVAILABLE              1
#define FM_MFT_WFG_WFTF54_AVAILABLE               1
/*******************************************************************************
* MFT_PPG
*******************************************************************************/
#define FM4_MFT_PPG_COMP0_AVAILABLE               1
#define FM_MFT_PPG_COMP0_AVAILABLE                1
#define FM4_MFT_PPG_COMP1_AVAILABLE               1
#define FM_MFT_PPG_COMP1_AVAILABLE                1
#define FM4_MFT_PPG_COMP10_AVAILABLE              1
#define FM_MFT_PPG_COMP10_AVAILABLE               1
#define FM4_MFT_PPG_COMP12_AVAILABLE              1
#define FM_MFT_PPG_COMP12_AVAILABLE               1
#define FM4_MFT_PPG_COMP14_AVAILABLE              1
#define FM_MFT_PPG_COMP14_AVAILABLE               1
#define FM4_MFT_PPG_COMP2_AVAILABLE               1
#define FM_MFT_PPG_COMP2_AVAILABLE                1
#define FM4_MFT_PPG_COMP3_AVAILABLE               1
#define FM_MFT_PPG_COMP3_AVAILABLE                1
#define FM4_MFT_PPG_COMP4_AVAILABLE               1
#define FM_MFT_PPG_COMP4_AVAILABLE                1
#define FM4_MFT_PPG_COMP5_AVAILABLE               1
#define FM_MFT_PPG_COMP5_AVAILABLE                1
#define FM4_MFT_PPG_COMP6_AVAILABLE               1
#define FM_MFT_PPG_COMP6_AVAILABLE                1
#define FM4_MFT_PPG_COMP7_AVAILABLE               1
#define FM_MFT_PPG_COMP7_AVAILABLE                1
#define FM4_MFT_PPG_COMP8_AVAILABLE               1
#define FM_MFT_PPG_COMP8_AVAILABLE                1
#define FM4_MFT_PPG_GATEC0_AVAILABLE              1
#define FM_MFT_PPG_GATEC0_AVAILABLE               1
#define FM4_MFT_PPG_GATEC12_AVAILABLE             1
#define FM_MFT_PPG_GATEC12_AVAILABLE              1
#define FM4_MFT_PPG_GATEC16_AVAILABLE             1
#define FM_MFT_PPG_GATEC16_AVAILABLE              1
#define FM4_MFT_PPG_GATEC20_AVAILABLE             1
#define FM_MFT_PPG_GATEC20_AVAILABLE              1
#define FM4_MFT_PPG_GATEC4_AVAILABLE              1
#define FM_MFT_PPG_GATEC4_AVAILABLE               1
#define FM4_MFT_PPG_GATEC8_AVAILABLE              1
#define FM_MFT_PPG_GATEC8_AVAILABLE               1
#define FM4_MFT_PPG_PPGC0_AVAILABLE               1
#define FM_MFT_PPG_PPGC0_AVAILABLE                1
#define FM4_MFT_PPG_PPGC1_AVAILABLE               1
#define FM_MFT_PPG_PPGC1_AVAILABLE                1
#define FM4_MFT_PPG_PPGC10_AVAILABLE              1
#define FM_MFT_PPG_PPGC10_AVAILABLE               1
#define FM4_MFT_PPG_PPGC11_AVAILABLE              1
#define FM_MFT_PPG_PPGC11_AVAILABLE               1
#define FM4_MFT_PPG_PPGC12_AVAILABLE              1
#define FM_MFT_PPG_PPGC12_AVAILABLE               1
#define FM4_MFT_PPG_PPGC13_AVAILABLE              1
#define FM_MFT_PPG_PPGC13_AVAILABLE               1
#define FM4_MFT_PPG_PPGC14_AVAILABLE              1
#define FM_MFT_PPG_PPGC14_AVAILABLE               1
#define FM4_MFT_PPG_PPGC15_AVAILABLE              1
#define FM_MFT_PPG_PPGC15_AVAILABLE               1
#define FM4_MFT_PPG_PPGC16_AVAILABLE              1
#define FM_MFT_PPG_PPGC16_AVAILABLE               1
#define FM4_MFT_PPG_PPGC17_AVAILABLE              1
#define FM_MFT_PPG_PPGC17_AVAILABLE               1
#define FM4_MFT_PPG_PPGC18_AVAILABLE              1
#define FM_MFT_PPG_PPGC18_AVAILABLE               1
#define FM4_MFT_PPG_PPGC19_AVAILABLE              1
#define FM_MFT_PPG_PPGC19_AVAILABLE               1
#define FM4_MFT_PPG_PPGC2_AVAILABLE               1
#define FM_MFT_PPG_PPGC2_AVAILABLE                1
#define FM4_MFT_PPG_PPGC20_AVAILABLE              1
#define FM_MFT_PPG_PPGC20_AVAILABLE               1
#define FM4_MFT_PPG_PPGC21_AVAILABLE              1
#define FM_MFT_PPG_PPGC21_AVAILABLE               1
#define FM4_MFT_PPG_PPGC22_AVAILABLE              1
#define FM_MFT_PPG_PPGC22_AVAILABLE               1
#define FM4_MFT_PPG_PPGC23_AVAILABLE              1
#define FM_MFT_PPG_PPGC23_AVAILABLE               1
#define FM4_MFT_PPG_PPGC3_AVAILABLE               1
#define FM_MFT_PPG_PPGC3_AVAILABLE                1
#define FM4_MFT_PPG_PPGC4_AVAILABLE               1
#define FM_MFT_PPG_PPGC4_AVAILABLE                1
#define FM4_MFT_PPG_PPGC5_AVAILABLE               1
#define FM_MFT_PPG_PPGC5_AVAILABLE                1
#define FM4_MFT_PPG_PPGC6_AVAILABLE               1
#define FM_MFT_PPG_PPGC6_AVAILABLE                1
#define FM4_MFT_PPG_PPGC7_AVAILABLE               1
#define FM_MFT_PPG_PPGC7_AVAILABLE                1
#define FM4_MFT_PPG_PPGC8_AVAILABLE               1
#define FM_MFT_PPG_PPGC8_AVAILABLE                1
#define FM4_MFT_PPG_PPGC9_AVAILABLE               1
#define FM_MFT_PPG_PPGC9_AVAILABLE                1
#define FM4_MFT_PPG_PRLH0_AVAILABLE               1
#define FM_MFT_PPG_PRLH0_AVAILABLE                1
#define FM4_MFT_PPG_PRLH1_AVAILABLE               1
#define FM_MFT_PPG_PRLH1_AVAILABLE                1
#define FM4_MFT_PPG_PRLH10_AVAILABLE              1
#define FM_MFT_PPG_PRLH10_AVAILABLE               1
#define FM4_MFT_PPG_PRLH11_AVAILABLE              1
#define FM_MFT_PPG_PRLH11_AVAILABLE               1
#define FM4_MFT_PPG_PRLH12_AVAILABLE              1
#define FM_MFT_PPG_PRLH12_AVAILABLE               1
#define FM4_MFT_PPG_PRLH13_AVAILABLE              1
#define FM_MFT_PPG_PRLH13_AVAILABLE               1
#define FM4_MFT_PPG_PRLH14_AVAILABLE              1
#define FM_MFT_PPG_PRLH14_AVAILABLE               1
#define FM4_MFT_PPG_PRLH15_AVAILABLE              1
#define FM_MFT_PPG_PRLH15_AVAILABLE               1
#define FM4_MFT_PPG_PRLH16_AVAILABLE              1
#define FM_MFT_PPG_PRLH16_AVAILABLE               1
#define FM4_MFT_PPG_PRLH17_AVAILABLE              1
#define FM_MFT_PPG_PRLH17_AVAILABLE               1
#define FM4_MFT_PPG_PRLH18_AVAILABLE              1
#define FM_MFT_PPG_PRLH18_AVAILABLE               1
#define FM4_MFT_PPG_PRLH19_AVAILABLE              1
#define FM_MFT_PPG_PRLH19_AVAILABLE               1
#define FM4_MFT_PPG_PRLH2_AVAILABLE               1
#define FM_MFT_PPG_PRLH2_AVAILABLE                1
#define FM4_MFT_PPG_PRLH20_AVAILABLE              1
#define FM_MFT_PPG_PRLH20_AVAILABLE               1
#define FM4_MFT_PPG_PRLH21_AVAILABLE              1
#define FM_MFT_PPG_PRLH21_AVAILABLE               1
#define FM4_MFT_PPG_PRLH22_AVAILABLE              1
#define FM_MFT_PPG_PRLH22_AVAILABLE               1
#define FM4_MFT_PPG_PRLH23_AVAILABLE              1
#define FM_MFT_PPG_PRLH23_AVAILABLE               1
#define FM4_MFT_PPG_PRLH3_AVAILABLE               1
#define FM_MFT_PPG_PRLH3_AVAILABLE                1
#define FM4_MFT_PPG_PRLH4_AVAILABLE               1
#define FM_MFT_PPG_PRLH4_AVAILABLE                1
#define FM4_MFT_PPG_PRLH5_AVAILABLE               1
#define FM_MFT_PPG_PRLH5_AVAILABLE                1
#define FM4_MFT_PPG_PRLH6_AVAILABLE               1
#define FM_MFT_PPG_PRLH6_AVAILABLE                1
#define FM4_MFT_PPG_PRLH7_AVAILABLE               1
#define FM_MFT_PPG_PRLH7_AVAILABLE                1
#define FM4_MFT_PPG_PRLH8_AVAILABLE               1
#define FM_MFT_PPG_PRLH8_AVAILABLE                1
#define FM4_MFT_PPG_PRLH9_AVAILABLE               1
#define FM_MFT_PPG_PRLH9_AVAILABLE                1
#define FM4_MFT_PPG_PRLL0_AVAILABLE               1
#define FM_MFT_PPG_PRLL0_AVAILABLE                1
#define FM4_MFT_PPG_PRLL1_AVAILABLE               1
#define FM_MFT_PPG_PRLL1_AVAILABLE                1
#define FM4_MFT_PPG_PRLL10_AVAILABLE              1
#define FM_MFT_PPG_PRLL10_AVAILABLE               1
#define FM4_MFT_PPG_PRLL11_AVAILABLE              1
#define FM_MFT_PPG_PRLL11_AVAILABLE               1
#define FM4_MFT_PPG_PRLL12_AVAILABLE              1
#define FM_MFT_PPG_PRLL12_AVAILABLE               1
#define FM4_MFT_PPG_PRLL13_AVAILABLE              1
#define FM_MFT_PPG_PRLL13_AVAILABLE               1
#define FM4_MFT_PPG_PRLL14_AVAILABLE              1
#define FM_MFT_PPG_PRLL14_AVAILABLE               1
#define FM4_MFT_PPG_PRLL15_AVAILABLE              1
#define FM_MFT_PPG_PRLL15_AVAILABLE               1
#define FM4_MFT_PPG_PRLL16_AVAILABLE              1
#define FM_MFT_PPG_PRLL16_AVAILABLE               1
#define FM4_MFT_PPG_PRLL17_AVAILABLE              1
#define FM_MFT_PPG_PRLL17_AVAILABLE               1
#define FM4_MFT_PPG_PRLL18_AVAILABLE              1
#define FM_MFT_PPG_PRLL18_AVAILABLE               1
#define FM4_MFT_PPG_PRLL19_AVAILABLE              1
#define FM_MFT_PPG_PRLL19_AVAILABLE               1
#define FM4_MFT_PPG_PRLL2_AVAILABLE               1
#define FM_MFT_PPG_PRLL2_AVAILABLE                1
#define FM4_MFT_PPG_PRLL20_AVAILABLE              1
#define FM_MFT_PPG_PRLL20_AVAILABLE               1
#define FM4_MFT_PPG_PRLL21_AVAILABLE              1
#define FM_MFT_PPG_PRLL21_AVAILABLE               1
#define FM4_MFT_PPG_PRLL22_AVAILABLE              1
#define FM_MFT_PPG_PRLL22_AVAILABLE               1
#define FM4_MFT_PPG_PRLL23_AVAILABLE              1
#define FM_MFT_PPG_PRLL23_AVAILABLE               1
#define FM4_MFT_PPG_PRLL3_AVAILABLE               1
#define FM_MFT_PPG_PRLL3_AVAILABLE                1
#define FM4_MFT_PPG_PRLL4_AVAILABLE               1
#define FM_MFT_PPG_PRLL4_AVAILABLE                1
#define FM4_MFT_PPG_PRLL5_AVAILABLE               1
#define FM_MFT_PPG_PRLL5_AVAILABLE                1
#define FM4_MFT_PPG_PRLL6_AVAILABLE               1
#define FM_MFT_PPG_PRLL6_AVAILABLE                1
#define FM4_MFT_PPG_PRLL7_AVAILABLE               1
#define FM_MFT_PPG_PRLL7_AVAILABLE                1
#define FM4_MFT_PPG_PRLL8_AVAILABLE               1
#define FM_MFT_PPG_PRLL8_AVAILABLE                1
#define FM4_MFT_PPG_PRLL9_AVAILABLE               1
#define FM_MFT_PPG_PRLL9_AVAILABLE                1
#define FM4_MFT_PPG_REVC0_AVAILABLE               1
#define FM_MFT_PPG_REVC0_AVAILABLE                1
#define FM4_MFT_PPG_REVC1_AVAILABLE               1
#define FM_MFT_PPG_REVC1_AVAILABLE                1
#define FM4_MFT_PPG_TRG0_AVAILABLE                1
#define FM_MFT_PPG_TRG0_AVAILABLE                 1
#define FM4_MFT_PPG_TRG1_AVAILABLE                1
#define FM_MFT_PPG_TRG1_AVAILABLE                 1
#define FM4_MFT_PPG_TTCR0_AVAILABLE               1
#define FM_MFT_PPG_TTCR0_AVAILABLE                1
#define FM4_MFT_PPG_TTCR1_AVAILABLE               1
#define FM_MFT_PPG_TTCR1_AVAILABLE                1
#define FM4_MFT_PPG_TTCR2_AVAILABLE               1
#define FM_MFT_PPG_TTCR2_AVAILABLE                1
/*******************************************************************************
* PCRC
*******************************************************************************/
#define FM4_PCRC_PCRC_CFG_AVAILABLE               1
#define FM_PCRC_PCRC_CFG_AVAILABLE                1
#define FM4_PCRC_PCRC_FXOR_AVAILABLE              1
#define FM_PCRC_PCRC_FXOR_AVAILABLE               1
#define FM4_PCRC_PCRC_POLY_AVAILABLE              1
#define FM_PCRC_PCRC_POLY_AVAILABLE               1
#define FM4_PCRC_PCRC_RD_AVAILABLE                1
#define FM_PCRC_PCRC_RD_AVAILABLE                 1
#define FM4_PCRC_PCRC_SEED_AVAILABLE              1
#define FM_PCRC_PCRC_SEED_AVAILABLE               1
#define FM4_PCRC_PCRC_WR_AVAILABLE                1
#define FM_PCRC_PCRC_WR_AVAILABLE                 1
/*******************************************************************************
* QPRC0
*******************************************************************************/
#define FM4_QPRC_QCR_AVAILABLE                    1
#define FM_QPRC_QCR_AVAILABLE                     1
#define FM4_QPRC_QECR_AVAILABLE                   1
#define FM_QPRC_QECR_AVAILABLE                    1
#define FM4_QPRC_QICRH_AVAILABLE                  1
#define FM_QPRC_QICRH_AVAILABLE                   1
#define FM4_QPRC_QICRL_AVAILABLE                  1
#define FM_QPRC_QICRL_AVAILABLE                   1
#define FM4_QPRC_QMPR_AVAILABLE                   1
#define FM_QPRC_QMPR_AVAILABLE                    1
#define FM4_QPRC_QPCCR_AVAILABLE                  1
#define FM_QPRC_QPCCR_AVAILABLE                   1
#define FM4_QPRC_QPCR_AVAILABLE                   1
#define FM_QPRC_QPCR_AVAILABLE                    1
#define FM4_QPRC_QPRCR_AVAILABLE                  1
#define FM_QPRC_QPRCR_AVAILABLE                   1
#define FM4_QPRC_QPRCRR_AVAILABLE                 1
#define FM_QPRC_QPRCRR_AVAILABLE                  1
#define FM4_QPRC_QRCR_AVAILABLE                   1
#define FM_QPRC_QRCR_AVAILABLE                    1
/*******************************************************************************
* QPRC0_NF
*******************************************************************************/
#define FM4_QPRC_NF_NFCTLA_AVAILABLE              1
#define FM_QPRC_NF_NFCTLA_AVAILABLE               1
#define FM4_QPRC_NF_NFCTLB_AVAILABLE              1
#define FM_QPRC_NF_NFCTLB_AVAILABLE               1
#define FM4_QPRC_NF_NFCTLZ_AVAILABLE              1
#define FM_QPRC_NF_NFCTLZ_AVAILABLE               1
/*******************************************************************************
* RTC
*******************************************************************************/
#define FM4_RTC_ALDR_AVAILABLE                    1
#define FM_RTC_ALDR_AVAILABLE                     1
#define FM4_RTC_ALHR_AVAILABLE                    1
#define FM_RTC_ALHR_AVAILABLE                     1
#define FM4_RTC_ALMIR_AVAILABLE                   1
#define FM_RTC_ALMIR_AVAILABLE                    1
#define FM4_RTC_ALMOR_AVAILABLE                   1
#define FM_RTC_ALMOR_AVAILABLE                    1
#define FM4_RTC_ALYR_AVAILABLE                    1
#define FM_RTC_ALYR_AVAILABLE                     1
#define FM4_RTC_BOOST_AVAILABLE                   1
#define FM_RTC_BOOST_AVAILABLE                    1
#define FM4_RTC_BREG00_AVAILABLE                  1
#define FM_RTC_BREG00_AVAILABLE                   1
#define FM4_RTC_BREG01_AVAILABLE                  1
#define FM_RTC_BREG01_AVAILABLE                   1
#define FM4_RTC_BREG02_AVAILABLE                  1
#define FM_RTC_BREG02_AVAILABLE                   1
#define FM4_RTC_BREG03_AVAILABLE                  1
#define FM_RTC_BREG03_AVAILABLE                   1
#define FM4_RTC_BREG04_AVAILABLE                  1
#define FM_RTC_BREG04_AVAILABLE                   1
#define FM4_RTC_BREG05_AVAILABLE                  1
#define FM_RTC_BREG05_AVAILABLE                   1
#define FM4_RTC_BREG06_AVAILABLE                  1
#define FM_RTC_BREG06_AVAILABLE                   1
#define FM4_RTC_BREG07_AVAILABLE                  1
#define FM_RTC_BREG07_AVAILABLE                   1
#define FM4_RTC_BREG08_AVAILABLE                  1
#define FM_RTC_BREG08_AVAILABLE                   1
#define FM4_RTC_BREG09_AVAILABLE                  1
#define FM_RTC_BREG09_AVAILABLE                   1
#define FM4_RTC_BREG0A_AVAILABLE                  1
#define FM_RTC_BREG0A_AVAILABLE                   1
#define FM4_RTC_BREG0B_AVAILABLE                  1
#define FM_RTC_BREG0B_AVAILABLE                   1
#define FM4_RTC_BREG0C_AVAILABLE                  1
#define FM_RTC_BREG0C_AVAILABLE                   1
#define FM4_RTC_BREG0D_AVAILABLE                  1
#define FM_RTC_BREG0D_AVAILABLE                   1
#define FM4_RTC_BREG0E_AVAILABLE                  1
#define FM_RTC_BREG0E_AVAILABLE                   1
#define FM4_RTC_BREG0F_AVAILABLE                  1
#define FM_RTC_BREG0F_AVAILABLE                   1
#define FM4_RTC_BREG10_AVAILABLE                  1
#define FM_RTC_BREG10_AVAILABLE                   1
#define FM4_RTC_BREG11_AVAILABLE                  1
#define FM_RTC_BREG11_AVAILABLE                   1
#define FM4_RTC_BREG12_AVAILABLE                  1
#define FM_RTC_BREG12_AVAILABLE                   1
#define FM4_RTC_BREG13_AVAILABLE                  1
#define FM_RTC_BREG13_AVAILABLE                   1
#define FM4_RTC_BREG14_AVAILABLE                  1
#define FM_RTC_BREG14_AVAILABLE                   1
#define FM4_RTC_BREG15_AVAILABLE                  1
#define FM_RTC_BREG15_AVAILABLE                   1
#define FM4_RTC_BREG16_AVAILABLE                  1
#define FM_RTC_BREG16_AVAILABLE                   1
#define FM4_RTC_BREG17_AVAILABLE                  1
#define FM_RTC_BREG17_AVAILABLE                   1
#define FM4_RTC_BREG18_AVAILABLE                  1
#define FM_RTC_BREG18_AVAILABLE                   1
#define FM4_RTC_BREG19_AVAILABLE                  1
#define FM_RTC_BREG19_AVAILABLE                   1
#define FM4_RTC_BREG1A_AVAILABLE                  1
#define FM_RTC_BREG1A_AVAILABLE                   1
#define FM4_RTC_BREG1B_AVAILABLE                  1
#define FM_RTC_BREG1B_AVAILABLE                   1
#define FM4_RTC_BREG1C_AVAILABLE                  1
#define FM_RTC_BREG1C_AVAILABLE                   1
#define FM4_RTC_BREG1D_AVAILABLE                  1
#define FM_RTC_BREG1D_AVAILABLE                   1
#define FM4_RTC_BREG1E_AVAILABLE                  1
#define FM_RTC_BREG1E_AVAILABLE                   1
#define FM4_RTC_BREG1F_AVAILABLE                  1
#define FM_RTC_BREG1F_AVAILABLE                   1
#define FM4_RTC_BREG20_AVAILABLE                  1
#define FM_RTC_BREG20_AVAILABLE                   1
#define FM4_RTC_BREG21_AVAILABLE                  1
#define FM_RTC_BREG21_AVAILABLE                   1
#define FM4_RTC_BREG22_AVAILABLE                  1
#define FM_RTC_BREG22_AVAILABLE                   1
#define FM4_RTC_BREG23_AVAILABLE                  1
#define FM_RTC_BREG23_AVAILABLE                   1
#define FM4_RTC_BREG24_AVAILABLE                  1
#define FM_RTC_BREG24_AVAILABLE                   1
#define FM4_RTC_BREG25_AVAILABLE                  1
#define FM_RTC_BREG25_AVAILABLE                   1
#define FM4_RTC_BREG26_AVAILABLE                  1
#define FM_RTC_BREG26_AVAILABLE                   1
#define FM4_RTC_BREG27_AVAILABLE                  1
#define FM_RTC_BREG27_AVAILABLE                   1
#define FM4_RTC_BREG28_AVAILABLE                  1
#define FM_RTC_BREG28_AVAILABLE                   1
#define FM4_RTC_BREG29_AVAILABLE                  1
#define FM_RTC_BREG29_AVAILABLE                   1
#define FM4_RTC_BREG2A_AVAILABLE                  1
#define FM_RTC_BREG2A_AVAILABLE                   1
#define FM4_RTC_BREG2B_AVAILABLE                  1
#define FM_RTC_BREG2B_AVAILABLE                   1
#define FM4_RTC_BREG2C_AVAILABLE                  1
#define FM_RTC_BREG2C_AVAILABLE                   1
#define FM4_RTC_BREG2D_AVAILABLE                  1
#define FM_RTC_BREG2D_AVAILABLE                   1
#define FM4_RTC_BREG2E_AVAILABLE                  1
#define FM_RTC_BREG2E_AVAILABLE                   1
#define FM4_RTC_BREG2F_AVAILABLE                  1
#define FM_RTC_BREG2F_AVAILABLE                   1
#define FM4_RTC_BREG30_AVAILABLE                  1
#define FM_RTC_BREG30_AVAILABLE                   1
#define FM4_RTC_BREG31_AVAILABLE                  1
#define FM_RTC_BREG31_AVAILABLE                   1
#define FM4_RTC_BREG32_AVAILABLE                  1
#define FM_RTC_BREG32_AVAILABLE                   1
#define FM4_RTC_BREG33_AVAILABLE                  1
#define FM_RTC_BREG33_AVAILABLE                   1
#define FM4_RTC_BREG34_AVAILABLE                  1
#define FM_RTC_BREG34_AVAILABLE                   1
#define FM4_RTC_BREG35_AVAILABLE                  1
#define FM_RTC_BREG35_AVAILABLE                   1
#define FM4_RTC_BREG36_AVAILABLE                  1
#define FM_RTC_BREG36_AVAILABLE                   1
#define FM4_RTC_BREG37_AVAILABLE                  1
#define FM_RTC_BREG37_AVAILABLE                   1
#define FM4_RTC_BREG38_AVAILABLE                  1
#define FM_RTC_BREG38_AVAILABLE                   1
#define FM4_RTC_BREG39_AVAILABLE                  1
#define FM_RTC_BREG39_AVAILABLE                   1
#define FM4_RTC_BREG3A_AVAILABLE                  1
#define FM_RTC_BREG3A_AVAILABLE                   1
#define FM4_RTC_BREG3B_AVAILABLE                  1
#define FM_RTC_BREG3B_AVAILABLE                   1
#define FM4_RTC_BREG3C_AVAILABLE                  1
#define FM_RTC_BREG3C_AVAILABLE                   1
#define FM4_RTC_BREG3D_AVAILABLE                  1
#define FM_RTC_BREG3D_AVAILABLE                   1
#define FM4_RTC_BREG3E_AVAILABLE                  1
#define FM_RTC_BREG3E_AVAILABLE                   1
#define FM4_RTC_BREG3F_AVAILABLE                  1
#define FM_RTC_BREG3F_AVAILABLE                   1
#define FM4_RTC_BREG40_AVAILABLE                  1
#define FM_RTC_BREG40_AVAILABLE                   1
#define FM4_RTC_BREG41_AVAILABLE                  1
#define FM_RTC_BREG41_AVAILABLE                   1
#define FM4_RTC_BREG42_AVAILABLE                  1
#define FM_RTC_BREG42_AVAILABLE                   1
#define FM4_RTC_BREG43_AVAILABLE                  1
#define FM_RTC_BREG43_AVAILABLE                   1
#define FM4_RTC_BREG44_AVAILABLE                  1
#define FM_RTC_BREG44_AVAILABLE                   1
#define FM4_RTC_BREG45_AVAILABLE                  1
#define FM_RTC_BREG45_AVAILABLE                   1
#define FM4_RTC_BREG46_AVAILABLE                  1
#define FM_RTC_BREG46_AVAILABLE                   1
#define FM4_RTC_BREG47_AVAILABLE                  1
#define FM_RTC_BREG47_AVAILABLE                   1
#define FM4_RTC_BREG48_AVAILABLE                  1
#define FM_RTC_BREG48_AVAILABLE                   1
#define FM4_RTC_BREG49_AVAILABLE                  1
#define FM_RTC_BREG49_AVAILABLE                   1
#define FM4_RTC_BREG4A_AVAILABLE                  1
#define FM_RTC_BREG4A_AVAILABLE                   1
#define FM4_RTC_BREG4B_AVAILABLE                  1
#define FM_RTC_BREG4B_AVAILABLE                   1
#define FM4_RTC_BREG4C_AVAILABLE                  1
#define FM_RTC_BREG4C_AVAILABLE                   1
#define FM4_RTC_BREG4D_AVAILABLE                  1
#define FM_RTC_BREG4D_AVAILABLE                   1
#define FM4_RTC_BREG4E_AVAILABLE                  1
#define FM_RTC_BREG4E_AVAILABLE                   1
#define FM4_RTC_BREG4F_AVAILABLE                  1
#define FM_RTC_BREG4F_AVAILABLE                   1
#define FM4_RTC_BREG50_AVAILABLE                  1
#define FM_RTC_BREG50_AVAILABLE                   1
#define FM4_RTC_BREG51_AVAILABLE                  1
#define FM_RTC_BREG51_AVAILABLE                   1
#define FM4_RTC_BREG52_AVAILABLE                  1
#define FM_RTC_BREG52_AVAILABLE                   1
#define FM4_RTC_BREG53_AVAILABLE                  1
#define FM_RTC_BREG53_AVAILABLE                   1
#define FM4_RTC_BREG54_AVAILABLE                  1
#define FM_RTC_BREG54_AVAILABLE                   1
#define FM4_RTC_BREG55_AVAILABLE                  1
#define FM_RTC_BREG55_AVAILABLE                   1
#define FM4_RTC_BREG56_AVAILABLE                  1
#define FM_RTC_BREG56_AVAILABLE                   1
#define FM4_RTC_BREG57_AVAILABLE                  1
#define FM_RTC_BREG57_AVAILABLE                   1
#define FM4_RTC_BREG58_AVAILABLE                  1
#define FM_RTC_BREG58_AVAILABLE                   1
#define FM4_RTC_BREG59_AVAILABLE                  1
#define FM_RTC_BREG59_AVAILABLE                   1
#define FM4_RTC_BREG5A_AVAILABLE                  1
#define FM_RTC_BREG5A_AVAILABLE                   1
#define FM4_RTC_BREG5B_AVAILABLE                  1
#define FM_RTC_BREG5B_AVAILABLE                   1
#define FM4_RTC_BREG5C_AVAILABLE                  1
#define FM_RTC_BREG5C_AVAILABLE                   1
#define FM4_RTC_BREG5D_AVAILABLE                  1
#define FM_RTC_BREG5D_AVAILABLE                   1
#define FM4_RTC_BREG5E_AVAILABLE                  1
#define FM_RTC_BREG5E_AVAILABLE                   1
#define FM4_RTC_BREG5F_AVAILABLE                  1
#define FM_RTC_BREG5F_AVAILABLE                   1
#define FM4_RTC_BREG60_AVAILABLE                  1
#define FM_RTC_BREG60_AVAILABLE                   1
#define FM4_RTC_BREG61_AVAILABLE                  1
#define FM_RTC_BREG61_AVAILABLE                   1
#define FM4_RTC_BREG62_AVAILABLE                  1
#define FM_RTC_BREG62_AVAILABLE                   1
#define FM4_RTC_BREG63_AVAILABLE                  1
#define FM_RTC_BREG63_AVAILABLE                   1
#define FM4_RTC_BREG64_AVAILABLE                  1
#define FM_RTC_BREG64_AVAILABLE                   1
#define FM4_RTC_BREG65_AVAILABLE                  1
#define FM_RTC_BREG65_AVAILABLE                   1
#define FM4_RTC_BREG66_AVAILABLE                  1
#define FM_RTC_BREG66_AVAILABLE                   1
#define FM4_RTC_BREG67_AVAILABLE                  1
#define FM_RTC_BREG67_AVAILABLE                   1
#define FM4_RTC_BREG68_AVAILABLE                  1
#define FM_RTC_BREG68_AVAILABLE                   1
#define FM4_RTC_BREG69_AVAILABLE                  1
#define FM_RTC_BREG69_AVAILABLE                   1
#define FM4_RTC_BREG6A_AVAILABLE                  1
#define FM_RTC_BREG6A_AVAILABLE                   1
#define FM4_RTC_BREG6B_AVAILABLE                  1
#define FM_RTC_BREG6B_AVAILABLE                   1
#define FM4_RTC_BREG6C_AVAILABLE                  1
#define FM_RTC_BREG6C_AVAILABLE                   1
#define FM4_RTC_BREG6D_AVAILABLE                  1
#define FM_RTC_BREG6D_AVAILABLE                   1
#define FM4_RTC_BREG6E_AVAILABLE                  1
#define FM_RTC_BREG6E_AVAILABLE                   1
#define FM4_RTC_BREG6F_AVAILABLE                  1
#define FM_RTC_BREG6F_AVAILABLE                   1
#define FM4_RTC_BREG70_AVAILABLE                  1
#define FM_RTC_BREG70_AVAILABLE                   1
#define FM4_RTC_BREG71_AVAILABLE                  1
#define FM_RTC_BREG71_AVAILABLE                   1
#define FM4_RTC_BREG72_AVAILABLE                  1
#define FM_RTC_BREG72_AVAILABLE                   1
#define FM4_RTC_BREG73_AVAILABLE                  1
#define FM_RTC_BREG73_AVAILABLE                   1
#define FM4_RTC_BREG74_AVAILABLE                  1
#define FM_RTC_BREG74_AVAILABLE                   1
#define FM4_RTC_BREG75_AVAILABLE                  1
#define FM_RTC_BREG75_AVAILABLE                   1
#define FM4_RTC_BREG76_AVAILABLE                  1
#define FM_RTC_BREG76_AVAILABLE                   1
#define FM4_RTC_BREG77_AVAILABLE                  1
#define FM_RTC_BREG77_AVAILABLE                   1
#define FM4_RTC_BREG78_AVAILABLE                  1
#define FM_RTC_BREG78_AVAILABLE                   1
#define FM4_RTC_BREG79_AVAILABLE                  1
#define FM_RTC_BREG79_AVAILABLE                   1
#define FM4_RTC_BREG7A_AVAILABLE                  1
#define FM_RTC_BREG7A_AVAILABLE                   1
#define FM4_RTC_BREG7B_AVAILABLE                  1
#define FM_RTC_BREG7B_AVAILABLE                   1
#define FM4_RTC_BREG7C_AVAILABLE                  1
#define FM_RTC_BREG7C_AVAILABLE                   1
#define FM4_RTC_BREG7D_AVAILABLE                  1
#define FM_RTC_BREG7D_AVAILABLE                   1
#define FM4_RTC_BREG7E_AVAILABLE                  1
#define FM_RTC_BREG7E_AVAILABLE                   1
#define FM4_RTC_BREG7F_AVAILABLE                  1
#define FM_RTC_BREG7F_AVAILABLE                   1
#define FM4_RTC_CCB_AVAILABLE                     1
#define FM_RTC_CCB_AVAILABLE                      1
#define FM4_RTC_CCS_AVAILABLE                     1
#define FM_RTC_CCS_AVAILABLE                      1
#define FM4_RTC_EWKUP_AVAILABLE                   1
#define FM_RTC_EWKUP_AVAILABLE                    1
#define FM4_RTC_HIBRST_AVAILABLE                  1
#define FM_RTC_HIBRST_AVAILABLE                   1
#define FM4_RTC_VB_CLKDIV_AVAILABLE               1
#define FM_RTC_VB_CLKDIV_AVAILABLE                1
#define FM4_RTC_VBDDR_AVAILABLE                   1
#define FM_RTC_VBDDR_AVAILABLE                    1
#define FM4_RTC_VBDIR_AVAILABLE                   1
#define FM_RTC_VBDIR_AVAILABLE                    1
#define FM4_RTC_VBDOR_AVAILABLE                   1
#define FM_RTC_VBDOR_AVAILABLE                    1
#define FM4_RTC_VBPCR_AVAILABLE                   1
#define FM_RTC_VBPCR_AVAILABLE                    1
#define FM4_RTC_VBPFR_AVAILABLE                   1
#define FM_RTC_VBPFR_AVAILABLE                    1
#define FM4_RTC_VBPZR_AVAILABLE                   1
#define FM_RTC_VBPZR_AVAILABLE                    1
#define FM4_RTC_VDET_AVAILABLE                    1
#define FM_RTC_VDET_AVAILABLE                     1
#define FM4_RTC_WTCAL0_AVAILABLE                  1
#define FM_RTC_WTCAL0_AVAILABLE                   1
#define FM4_RTC_WTCAL1_AVAILABLE                  1
#define FM_RTC_WTCAL1_AVAILABLE                   1
#define FM4_RTC_WTCALEN_AVAILABLE                 1
#define FM_RTC_WTCALEN_AVAILABLE                  1
#define FM4_RTC_WTCALPRD_AVAILABLE                1
#define FM_RTC_WTCALPRD_AVAILABLE                 1
#define FM4_RTC_WTCOSEL_AVAILABLE                 1
#define FM_RTC_WTCOSEL_AVAILABLE                  1
#define FM4_RTC_WTCR10_AVAILABLE                  1
#define FM_RTC_WTCR10_AVAILABLE                   1
#define FM4_RTC_WTCR11_AVAILABLE                  1
#define FM_RTC_WTCR11_AVAILABLE                   1
#define FM4_RTC_WTCR12_AVAILABLE                  1
#define FM_RTC_WTCR12_AVAILABLE                   1
#define FM4_RTC_WTCR13_AVAILABLE                  1
#define FM_RTC_WTCR13_AVAILABLE                   1
#define FM4_RTC_WTCR20_AVAILABLE                  1
#define FM_RTC_WTCR20_AVAILABLE                   1
#define FM4_RTC_WTCR21_AVAILABLE                  1
#define FM_RTC_WTCR21_AVAILABLE                   1
#define FM4_RTC_WTDIV_AVAILABLE                   1
#define FM_RTC_WTDIV_AVAILABLE                    1
#define FM4_RTC_WTDIVEN_AVAILABLE                 1
#define FM_RTC_WTDIVEN_AVAILABLE                  1
#define FM4_RTC_WTDR_AVAILABLE                    1
#define FM_RTC_WTDR_AVAILABLE                     1
#define FM4_RTC_WTDW_AVAILABLE                    1
#define FM_RTC_WTDW_AVAILABLE                     1
#define FM4_RTC_WTHR_AVAILABLE                    1
#define FM_RTC_WTHR_AVAILABLE                     1
#define FM4_RTC_WTMIR_AVAILABLE                   1
#define FM_RTC_WTMIR_AVAILABLE                    1
#define FM4_RTC_WTMOR_AVAILABLE                   1
#define FM_RTC_WTMOR_AVAILABLE                    1
#define FM4_RTC_WTOSCCNT_AVAILABLE                1
#define FM_RTC_WTOSCCNT_AVAILABLE                 1
#define FM4_RTC_WTSR_AVAILABLE                    1
#define FM_RTC_WTSR_AVAILABLE                     1
#define FM4_RTC_WTTR0_AVAILABLE                   1
#define FM_RTC_WTTR0_AVAILABLE                    1
#define FM4_RTC_WTTR1_AVAILABLE                   1
#define FM_RTC_WTTR1_AVAILABLE                    1
#define FM4_RTC_WTTR2_AVAILABLE                   1
#define FM_RTC_WTTR2_AVAILABLE                    1
#define FM4_RTC_WTYR_AVAILABLE                    1
#define FM_RTC_WTYR_AVAILABLE                     1
/*******************************************************************************
* SBSSR
*******************************************************************************/
#define FM4_SBSSR_BTSSSR_AVAILABLE                1
#define FM_SBSSR_BTSSSR_AVAILABLE                 1
/*******************************************************************************
* SDIF
*******************************************************************************/
#define FM4_SDIF_ADMAEST_AVAILABLE                1
#define FM_SDIF_ADMAEST_AVAILABLE                 1
#define FM4_SDIF_AHBCFGH_AVAILABLE                1
#define FM_SDIF_AHBCFGH_AVAILABLE                 1
#define FM4_SDIF_AHBCFGL_AVAILABLE                1
#define FM_SDIF_AHBCFGL_AVAILABLE                 1
#define FM4_SDIF_CAPBLTY0_AVAILABLE               1
#define FM_SDIF_CAPBLTY0_AVAILABLE                1
#define FM4_SDIF_CAPBLTY1_AVAILABLE               1
#define FM_SDIF_CAPBLTY1_AVAILABLE                1
#define FM4_SDIF_CAPBLTY2_AVAILABLE               1
#define FM_SDIF_CAPBLTY2_AVAILABLE                1
#define FM4_SDIF_CAPBLTY3_AVAILABLE               1
#define FM_SDIF_CAPBLTY3_AVAILABLE                1
#define FM4_SDIF_FEACEST_AVAILABLE                1
#define FM_SDIF_FEACEST_AVAILABLE                 1
#define FM4_SDIF_MCRPCKBH_AVAILABLE               1
#define FM_SDIF_MCRPCKBH_AVAILABLE                1
#define FM4_SDIF_MCRPCKBL_AVAILABLE               1
#define FM_SDIF_MCRPCKBL_AVAILABLE                1
#define FM4_SDIF_MCWIRQC0_AVAILABLE               1
#define FM_SDIF_MCWIRQC0_AVAILABLE                1
#define FM4_SDIF_MCWIRQC1_AVAILABLE               1
#define FM_SDIF_MCWIRQC1_AVAILABLE                1
#define FM4_SDIF_MCWIRQC2_AVAILABLE               1
#define FM_SDIF_MCWIRQC2_AVAILABLE                1
#define FM4_SDIF_MCWIRQC3_AVAILABLE               1
#define FM_SDIF_MCWIRQC3_AVAILABLE                1
#define FM4_SDIF_MMCSDCH_AVAILABLE                1
#define FM_SDIF_MMCSDCH_AVAILABLE                 1
#define FM4_SDIF_MMCSDCL_AVAILABLE                1
#define FM_SDIF_MMCSDCL_AVAILABLE                 1
#define FM4_SDIF_MXCCAPY0_AVAILABLE               1
#define FM_SDIF_MXCCAPY0_AVAILABLE                1
#define FM4_SDIF_MXCCAPY1_AVAILABLE               1
#define FM_SDIF_MXCCAPY1_AVAILABLE                1
#define FM4_SDIF_MXCCAPY2_AVAILABLE               1
#define FM_SDIF_MXCCAPY2_AVAILABLE                1
#define FM4_SDIF_MXCCAPY3_AVAILABLE               1
#define FM_SDIF_MXCCAPY3_AVAILABLE                1
#define FM4_SDIF_PSWISGEH_AVAILABLE               1
#define FM_SDIF_PSWISGEH_AVAILABLE                1
#define FM4_SDIF_PSWISGEL_AVAILABLE               1
#define FM_SDIF_PSWISGEL_AVAILABLE                1
#define FM4_SDIF_PSWISTEH_AVAILABLE               1
#define FM_SDIF_PSWISTEH_AVAILABLE                1
#define FM4_SDIF_PSWISTEL_AVAILABLE               1
#define FM_SDIF_PSWISTEL_AVAILABLE                1
#define FM4_SDIF_PSWISTH_AVAILABLE                1
#define FM_SDIF_PSWISTH_AVAILABLE                 1
#define FM4_SDIF_PSWISTL_AVAILABLE                1
#define FM_SDIF_PSWISTL_AVAILABLE                 1
#define FM4_SDIF_SACMDEST_AVAILABLE               1
#define FM_SDIF_SACMDEST_AVAILABLE                1
#define FM4_SDIF_SADSA0_AVAILABLE                 1
#define FM_SDIF_SADSA0_AVAILABLE                  1
#define FM4_SDIF_SADSA1_AVAILABLE                 1
#define FM_SDIF_SADSA1_AVAILABLE                  1
#define FM4_SDIF_SADSA2_AVAILABLE                 1
#define FM_SDIF_SADSA2_AVAILABLE                  1
#define FM4_SDIF_SADSA3_AVAILABLE                 1
#define FM_SDIF_SADSA3_AVAILABLE                  1
#define FM4_SDIF_SBLCNT_AVAILABLE                 1
#define FM_SDIF_SBLCNT_AVAILABLE                  1
#define FM4_SDIF_SBLKGPCTL_AVAILABLE              1
#define FM_SDIF_SBLKGPCTL_AVAILABLE               1
#define FM4_SDIF_SBSIZE_AVAILABLE                 1
#define FM_SDIF_SBSIZE_AVAILABLE                  1
#define FM4_SDIF_SBUFDP_AVAILABLE                 1
#define FM_SDIF_SBUFDP_AVAILABLE                  1
#define FM4_SDIF_SCDETECS_AVAILABLE               1
#define FM_SDIF_SCDETECS_AVAILABLE                1
#define FM4_SDIF_SCLKCTL_AVAILABLE                1
#define FM_SDIF_SCLKCTL_AVAILABLE                 1
#define FM4_SDIF_SCMMD_AVAILABLE                  1
#define FM_SDIF_SCMMD_AVAILABLE                   1
#define FM4_SDIF_SEINTSGE_AVAILABLE               1
#define FM_SDIF_SEINTSGE_AVAILABLE                1
#define FM4_SDIF_SEINTST_AVAILABLE                1
#define FM_SDIF_SEINTST_AVAILABLE                 1
#define FM4_SDIF_SEINTSTE_AVAILABLE               1
#define FM_SDIF_SEINTSTE_AVAILABLE                1
#define FM4_SDIF_SFEEIST_AVAILABLE                1
#define FM_SDIF_SFEEIST_AVAILABLE                 1
#define FM4_SDIF_SHCTL1_AVAILABLE                 1
#define FM_SDIF_SHCTL1_AVAILABLE                  1
#define FM4_SDIF_SHCTL2_AVAILABLE                 1
#define FM_SDIF_SHCTL2_AVAILABLE                  1
#define FM4_SDIF_SHCTLV_AVAILABLE                 1
#define FM_SDIF_SHCTLV_AVAILABLE                  1
#define FM4_SDIF_SNINTSGE_AVAILABLE               1
#define FM_SDIF_SNINTSGE_AVAILABLE                1
#define FM4_SDIF_SNINTST_AVAILABLE                1
#define FM_SDIF_SNINTST_AVAILABLE                 1
#define FM4_SDIF_SNINTSTE_AVAILABLE               1
#define FM_SDIF_SNINTSTE_AVAILABLE                1
#define FM4_SDIF_SPRSTAT_AVAILABLE                1
#define FM_SDIF_SPRSTAT_AVAILABLE                 1
#define FM4_SDIF_SPRVAL0_AVAILABLE                1
#define FM_SDIF_SPRVAL0_AVAILABLE                 1
#define FM4_SDIF_SPRVAL1_AVAILABLE                1
#define FM_SDIF_SPRVAL1_AVAILABLE                 1
#define FM4_SDIF_SPRVAL2_AVAILABLE                1
#define FM_SDIF_SPRVAL2_AVAILABLE                 1
#define FM4_SDIF_SPRVAL3_AVAILABLE                1
#define FM_SDIF_SPRVAL3_AVAILABLE                 1
#define FM4_SDIF_SPRVAL4_AVAILABLE                1
#define FM_SDIF_SPRVAL4_AVAILABLE                 1
#define FM4_SDIF_SPRVAL5_AVAILABLE                1
#define FM_SDIF_SPRVAL5_AVAILABLE                 1
#define FM4_SDIF_SPRVAL6_AVAILABLE                1
#define FM_SDIF_SPRVAL6_AVAILABLE                 1
#define FM4_SDIF_SPRVAL7_AVAILABLE                1
#define FM_SDIF_SPRVAL7_AVAILABLE                 1
#define FM4_SDIF_SPWRCTL_AVAILABLE                1
#define FM_SDIF_SPWRCTL_AVAILABLE                 1
#define FM4_SDIF_SPWSWCH_AVAILABLE                1
#define FM_SDIF_SPWSWCH_AVAILABLE                 1
#define FM4_SDIF_SPWSWCL_AVAILABLE                1
#define FM_SDIF_SPWSWCL_AVAILABLE                 1
#define FM4_SDIF_SRESP0_AVAILABLE                 1
#define FM_SDIF_SRESP0_AVAILABLE                  1
#define FM4_SDIF_SRESP1_AVAILABLE                 1
#define FM_SDIF_SRESP1_AVAILABLE                  1
#define FM4_SDIF_SRESP2_AVAILABLE                 1
#define FM_SDIF_SRESP2_AVAILABLE                  1
#define FM4_SDIF_SRESP3_AVAILABLE                 1
#define FM_SDIF_SRESP3_AVAILABLE                  1
#define FM4_SDIF_SRESP4_AVAILABLE                 1
#define FM_SDIF_SRESP4_AVAILABLE                  1
#define FM4_SDIF_SRESP5_AVAILABLE                 1
#define FM_SDIF_SRESP5_AVAILABLE                  1
#define FM4_SDIF_SRESP6_AVAILABLE                 1
#define FM_SDIF_SRESP6_AVAILABLE                  1
#define FM4_SDIF_SRESP7_AVAILABLE                 1
#define FM_SDIF_SRESP7_AVAILABLE                  1
#define FM4_SDIF_SSA1_AVAILABLE                   1
#define FM_SDIF_SSA1_AVAILABLE                    1
#define FM4_SDIF_SSA2_AVAILABLE                   1
#define FM_SDIF_SSA2_AVAILABLE                    1
#define FM4_SDIF_SSHBCTLH_AVAILABLE               1
#define FM_SDIF_SSHBCTLH_AVAILABLE                1
#define FM4_SDIF_SSHBCTLL_AVAILABLE               1
#define FM_SDIF_SSHBCTLL_AVAILABLE                1
#define FM4_SDIF_SSLIST_AVAILABLE                 1
#define FM_SDIF_SSLIST_AVAILABLE                  1
#define FM4_SDIF_SSRST_AVAILABLE                  1
#define FM_SDIF_SSRST_AVAILABLE                   1
#define FM4_SDIF_STOCTL_AVAILABLE                 1
#define FM_SDIF_STOCTL_AVAILABLE                  1
#define FM4_SDIF_STRSFMD_AVAILABLE                1
#define FM_SDIF_STRSFMD_AVAILABLE                 1
#define FM4_SDIF_STUNSETH_AVAILABLE               1
#define FM_SDIF_STUNSETH_AVAILABLE                1
#define FM4_SDIF_STUNSETL_AVAILABLE               1
#define FM_SDIF_STUNSETL_AVAILABLE                1
#define FM4_SDIF_STUNSTH_AVAILABLE                1
#define FM_SDIF_STUNSTH_AVAILABLE                 1
#define FM4_SDIF_STUNSTL_AVAILABLE                1
#define FM_SDIF_STUNSTL_AVAILABLE                 1
#define FM4_SDIF_SWKUPCTL_AVAILABLE               1
#define FM_SDIF_SWKUPCTL_AVAILABLE                1
/*******************************************************************************
* SWWDT
*******************************************************************************/
#define FM4_SWWDT_WDOGCONTROL_AVAILABLE           1
#define FM_SWWDT_WDOGCONTROL_AVAILABLE            1
#define FM4_SWWDT_WDOGINTCLR_AVAILABLE            1
#define FM_SWWDT_WDOGINTCLR_AVAILABLE             1
#define FM4_SWWDT_WDOGLOAD_AVAILABLE              1
#define FM_SWWDT_WDOGLOAD_AVAILABLE               1
#define FM4_SWWDT_WDOGLOCK_AVAILABLE              1
#define FM_SWWDT_WDOGLOCK_AVAILABLE               1
#define FM4_SWWDT_WDOGRIS_AVAILABLE               1
#define FM_SWWDT_WDOGRIS_AVAILABLE                1
#define FM4_SWWDT_WDOGSPMC_AVAILABLE              1
#define FM_SWWDT_WDOGSPMC_AVAILABLE               1
#define FM4_SWWDT_WDOGVALUE_AVAILABLE             1
#define FM_SWWDT_WDOGVALUE_AVAILABLE              1
/*******************************************************************************
* UNIQUE_ID
*******************************************************************************/
#define FM4_UNIQUE_ID_UIDR0_AVAILABLE             1
#define FM_UNIQUE_ID_UIDR0_AVAILABLE              1
#define FM4_UNIQUE_ID_UIDR1_AVAILABLE             1
#define FM_UNIQUE_ID_UIDR1_AVAILABLE              1
/*******************************************************************************
* USB0
*******************************************************************************/
#define FM4_USB_EP0C_AVAILABLE                    1
#define FM_USB_EP0C_AVAILABLE                     1
#define FM4_USB_EP0DT_AVAILABLE                   1
#define FM_USB_EP0DT_AVAILABLE                    1
#define FM4_USB_EP0IS_AVAILABLE                   1
#define FM_USB_EP0IS_AVAILABLE                    1
#define FM4_USB_EP0OS_AVAILABLE                   1
#define FM_USB_EP0OS_AVAILABLE                    1
#define FM4_USB_EP1C_AVAILABLE                    1
#define FM_USB_EP1C_AVAILABLE                     1
#define FM4_USB_EP1DT_AVAILABLE                   1
#define FM_USB_EP1DT_AVAILABLE                    1
#define FM4_USB_EP1S_AVAILABLE                    1
#define FM_USB_EP1S_AVAILABLE                     1
#define FM4_USB_EP2C_AVAILABLE                    1
#define FM_USB_EP2C_AVAILABLE                     1
#define FM4_USB_EP2DT_AVAILABLE                   1
#define FM_USB_EP2DT_AVAILABLE                    1
#define FM4_USB_EP2S_AVAILABLE                    1
#define FM_USB_EP2S_AVAILABLE                     1
#define FM4_USB_EP3C_AVAILABLE                    1
#define FM_USB_EP3C_AVAILABLE                     1
#define FM4_USB_EP3DT_AVAILABLE                   1
#define FM_USB_EP3DT_AVAILABLE                    1
#define FM4_USB_EP3S_AVAILABLE                    1
#define FM_USB_EP3S_AVAILABLE                     1
#define FM4_USB_EP4C_AVAILABLE                    1
#define FM_USB_EP4C_AVAILABLE                     1
#define FM4_USB_EP4DT_AVAILABLE                   1
#define FM_USB_EP4DT_AVAILABLE                    1
#define FM4_USB_EP4S_AVAILABLE                    1
#define FM_USB_EP4S_AVAILABLE                     1
#define FM4_USB_EP5C_AVAILABLE                    1
#define FM_USB_EP5C_AVAILABLE                     1
#define FM4_USB_EP5DT_AVAILABLE                   1
#define FM_USB_EP5DT_AVAILABLE                    1
#define FM4_USB_EP5S_AVAILABLE                    1
#define FM_USB_EP5S_AVAILABLE                     1
#define FM4_USB_HADR_AVAILABLE                    1
#define FM_USB_HADR_AVAILABLE                     1
#define FM4_USB_HCNT_AVAILABLE                    1
#define FM_USB_HCNT_AVAILABLE                     1
#define FM4_USB_HEOF_AVAILABLE                    1
#define FM_USB_HEOF_AVAILABLE                     1
#define FM4_USB_HERR_AVAILABLE                    1
#define FM_USB_HERR_AVAILABLE                     1
#define FM4_USB_HFCOMP_AVAILABLE                  1
#define FM_USB_HFCOMP_AVAILABLE                   1
#define FM4_USB_HFRAME_AVAILABLE                  1
#define FM_USB_HFRAME_AVAILABLE                   1
#define FM4_USB_HIRQ_AVAILABLE                    1
#define FM_USB_HIRQ_AVAILABLE                     1
#define FM4_USB_HRTIMER_AVAILABLE                 1
#define FM_USB_HRTIMER_AVAILABLE                  1
#define FM4_USB_HRTIMER2_AVAILABLE                1
#define FM_USB_HRTIMER2_AVAILABLE                 1
#define FM4_USB_HSTATE_AVAILABLE                  1
#define FM_USB_HSTATE_AVAILABLE                   1
#define FM4_USB_HTOKEN_AVAILABLE                  1
#define FM_USB_HTOKEN_AVAILABLE                   1
#define FM4_USB_TMSP_AVAILABLE                    1
#define FM_USB_TMSP_AVAILABLE                     1
#define FM4_USB_UDCC_AVAILABLE                    1
#define FM_USB_UDCC_AVAILABLE                     1
#define FM4_USB_UDCIE_AVAILABLE                   1
#define FM_USB_UDCIE_AVAILABLE                    1
#define FM4_USB_UDCS_AVAILABLE                    1
#define FM_USB_UDCS_AVAILABLE                     1
/*******************************************************************************
* USBETHERCLK
*******************************************************************************/
#define FM4_USBETHERCLK_UCCR_AVAILABLE            1
#define FM_USBETHERCLK_UCCR_AVAILABLE             1
#define FM4_USBETHERCLK_UP_STR_AVAILABLE          1
#define FM_USBETHERCLK_UP_STR_AVAILABLE           1
#define FM4_USBETHERCLK_UPCR1_AVAILABLE           1
#define FM_USBETHERCLK_UPCR1_AVAILABLE            1
#define FM4_USBETHERCLK_UPCR2_AVAILABLE           1
#define FM_USBETHERCLK_UPCR2_AVAILABLE            1
#define FM4_USBETHERCLK_UPCR3_AVAILABLE           1
#define FM_USBETHERCLK_UPCR3_AVAILABLE            1
#define FM4_USBETHERCLK_UPCR4_AVAILABLE           1
#define FM_USBETHERCLK_UPCR4_AVAILABLE            1
#define FM4_USBETHERCLK_UPCR5_AVAILABLE           1
#define FM_USBETHERCLK_UPCR5_AVAILABLE            1
#define FM4_USBETHERCLK_UPCR6_AVAILABLE           1
#define FM_USBETHERCLK_UPCR6_AVAILABLE            1
#define FM4_USBETHERCLK_UPCR7_AVAILABLE           1
#define FM_USBETHERCLK_UPCR7_AVAILABLE            1
#define FM4_USBETHERCLK_UPINT_CLR_AVAILABLE       1
#define FM_USBETHERCLK_UPINT_CLR_AVAILABLE        1
#define FM4_USBETHERCLK_UPINT_ENR_AVAILABLE       1
#define FM_USBETHERCLK_UPINT_ENR_AVAILABLE        1
#define FM4_USBETHERCLK_UPINT_STR_AVAILABLE       1
#define FM_USBETHERCLK_UPINT_STR_AVAILABLE        1
#define FM4_USBETHERCLK_USBEN0_AVAILABLE          1
#define FM_USBETHERCLK_USBEN0_AVAILABLE           1
#define FM4_USBETHERCLK_USBEN1_AVAILABLE          1
#define FM_USBETHERCLK_USBEN1_AVAILABLE           1
/*******************************************************************************
* WC
*******************************************************************************/
#define FM4_WC_CLK_EN_AVAILABLE                   1
#define FM_WC_CLK_EN_AVAILABLE                    1
#define FM4_WC_CLK_SEL_AVAILABLE                  1
#define FM_WC_CLK_SEL_AVAILABLE                   1
#define FM4_WC_WCCR_AVAILABLE                     1
#define FM_WC_WCCR_AVAILABLE                      1
#define FM4_WC_WCRD_AVAILABLE                     1
#define FM_WC_WCRD_AVAILABLE                      1
#define FM4_WC_WCRL_AVAILABLE                     1
#define FM_WC_WCRL_AVAILABLE                      1

/*******************************************************************************
* Peripheral Bit Band Alias declaration
*******************************************************************************/
/*******************************************************************************
* ADC Registers ADC0
*   Bitband Section
*******************************************************************************/
#define bFM_ADC0_ADCEN_ENBL                       *((volatile  uint8_t *)(0x424E0780UL))
#define bFM4_ADC0_ADCEN_ENBL                      *((volatile  uint8_t *)(0x424E0780UL))
#define bFM_ADC0_ADCEN_READY                      *((volatile  uint8_t *)(0x424E0784UL))
#define bFM4_ADC0_ADCEN_READY                     *((volatile  uint8_t *)(0x424E0784UL))

#define bFM_ADC0_ADCR_OVRIE                       *((volatile  uint8_t *)(0x424E0020UL))
#define bFM4_ADC0_ADCR_OVRIE                      *((volatile  uint8_t *)(0x424E0020UL))
#define bFM_ADC0_ADCR_CMPIE                       *((volatile  uint8_t *)(0x424E0024UL))
#define bFM4_ADC0_ADCR_CMPIE                      *((volatile  uint8_t *)(0x424E0024UL))
#define bFM_ADC0_ADCR_PCIE                        *((volatile  uint8_t *)(0x424E0028UL))
#define bFM4_ADC0_ADCR_PCIE                       *((volatile  uint8_t *)(0x424E0028UL))
#define bFM_ADC0_ADCR_SCIE                        *((volatile  uint8_t *)(0x424E002CUL))
#define bFM4_ADC0_ADCR_SCIE                       *((volatile  uint8_t *)(0x424E002CUL))
#define bFM_ADC0_ADCR_CMPIF                       *((volatile  uint8_t *)(0x424E0034UL))
#define bFM4_ADC0_ADCR_CMPIF                      *((volatile  uint8_t *)(0x424E0034UL))
#define bFM_ADC0_ADCR_PCIF                        *((volatile  uint8_t *)(0x424E0038UL))
#define bFM4_ADC0_ADCR_PCIF                       *((volatile  uint8_t *)(0x424E0038UL))
#define bFM_ADC0_ADCR_SCIF                        *((volatile  uint8_t *)(0x424E003CUL))
#define bFM4_ADC0_ADCR_SCIF                       *((volatile  uint8_t *)(0x424E003CUL))

#define bFM_ADC0_ADSR_SCS                         *((volatile  uint8_t *)(0x424E0000UL))
#define bFM4_ADC0_ADSR_SCS                        *((volatile  uint8_t *)(0x424E0000UL))
#define bFM_ADC0_ADSR_PCS                         *((volatile  uint8_t *)(0x424E0004UL))
#define bFM4_ADC0_ADSR_PCS                        *((volatile  uint8_t *)(0x424E0004UL))
#define bFM_ADC0_ADSR_PCNS                        *((volatile  uint8_t *)(0x424E0008UL))
#define bFM4_ADC0_ADSR_PCNS                       *((volatile  uint8_t *)(0x424E0008UL))
#define bFM_ADC0_ADSR_FDAS                        *((volatile  uint8_t *)(0x424E0018UL))
#define bFM4_ADC0_ADSR_FDAS                       *((volatile  uint8_t *)(0x424E0018UL))
#define bFM_ADC0_ADSR_ADSTP                       *((volatile  uint8_t *)(0x424E001CUL))
#define bFM4_ADC0_ADSR_ADSTP                      *((volatile  uint8_t *)(0x424E001CUL))

#define bFM_ADC0_ADSS01_TS0                       *((volatile  uint8_t *)(0x424E0580UL))
#define bFM4_ADC0_ADSS01_TS0                      *((volatile  uint8_t *)(0x424E0580UL))
#define bFM_ADC0_ADSS01_TS1                       *((volatile  uint8_t *)(0x424E0584UL))
#define bFM4_ADC0_ADSS01_TS1                      *((volatile  uint8_t *)(0x424E0584UL))
#define bFM_ADC0_ADSS01_TS2                       *((volatile  uint8_t *)(0x424E0588UL))
#define bFM4_ADC0_ADSS01_TS2                      *((volatile  uint8_t *)(0x424E0588UL))
#define bFM_ADC0_ADSS01_TS3                       *((volatile  uint8_t *)(0x424E058CUL))
#define bFM4_ADC0_ADSS01_TS3                      *((volatile  uint8_t *)(0x424E058CUL))
#define bFM_ADC0_ADSS01_TS4                       *((volatile  uint8_t *)(0x424E0590UL))
#define bFM4_ADC0_ADSS01_TS4                      *((volatile  uint8_t *)(0x424E0590UL))
#define bFM_ADC0_ADSS01_TS5                       *((volatile  uint8_t *)(0x424E0594UL))
#define bFM4_ADC0_ADSS01_TS5                      *((volatile  uint8_t *)(0x424E0594UL))
#define bFM_ADC0_ADSS01_TS6                       *((volatile  uint8_t *)(0x424E0598UL))
#define bFM4_ADC0_ADSS01_TS6                      *((volatile  uint8_t *)(0x424E0598UL))
#define bFM_ADC0_ADSS01_TS7                       *((volatile  uint8_t *)(0x424E059CUL))
#define bFM4_ADC0_ADSS01_TS7                      *((volatile  uint8_t *)(0x424E059CUL))
#define bFM_ADC0_ADSS01_TS8                       *((volatile  uint8_t *)(0x424E05A0UL))
#define bFM4_ADC0_ADSS01_TS8                      *((volatile  uint8_t *)(0x424E05A0UL))
#define bFM_ADC0_ADSS01_TS9                       *((volatile  uint8_t *)(0x424E05A4UL))
#define bFM4_ADC0_ADSS01_TS9                      *((volatile  uint8_t *)(0x424E05A4UL))
#define bFM_ADC0_ADSS01_TS10                      *((volatile  uint8_t *)(0x424E05A8UL))
#define bFM4_ADC0_ADSS01_TS10                     *((volatile  uint8_t *)(0x424E05A8UL))
#define bFM_ADC0_ADSS01_TS11                      *((volatile  uint8_t *)(0x424E05ACUL))
#define bFM4_ADC0_ADSS01_TS11                     *((volatile  uint8_t *)(0x424E05ACUL))
#define bFM_ADC0_ADSS01_TS12                      *((volatile  uint8_t *)(0x424E05B0UL))
#define bFM4_ADC0_ADSS01_TS12                     *((volatile  uint8_t *)(0x424E05B0UL))
#define bFM_ADC0_ADSS01_TS13                      *((volatile  uint8_t *)(0x424E05B4UL))
#define bFM4_ADC0_ADSS01_TS13                     *((volatile  uint8_t *)(0x424E05B4UL))
#define bFM_ADC0_ADSS01_TS14                      *((volatile  uint8_t *)(0x424E05B8UL))
#define bFM4_ADC0_ADSS01_TS14                     *((volatile  uint8_t *)(0x424E05B8UL))
#define bFM_ADC0_ADSS01_TS15                      *((volatile  uint8_t *)(0x424E05BCUL))
#define bFM4_ADC0_ADSS01_TS15                     *((volatile  uint8_t *)(0x424E05BCUL))

#define bFM_ADC0_ADSS23_TS16                      *((volatile  uint8_t *)(0x424E0500UL))
#define bFM4_ADC0_ADSS23_TS16                     *((volatile  uint8_t *)(0x424E0500UL))
#define bFM_ADC0_ADSS23_TS17                      *((volatile  uint8_t *)(0x424E0504UL))
#define bFM4_ADC0_ADSS23_TS17                     *((volatile  uint8_t *)(0x424E0504UL))
#define bFM_ADC0_ADSS23_TS18                      *((volatile  uint8_t *)(0x424E0508UL))
#define bFM4_ADC0_ADSS23_TS18                     *((volatile  uint8_t *)(0x424E0508UL))
#define bFM_ADC0_ADSS23_TS19                      *((volatile  uint8_t *)(0x424E050CUL))
#define bFM4_ADC0_ADSS23_TS19                     *((volatile  uint8_t *)(0x424E050CUL))
#define bFM_ADC0_ADSS23_TS20                      *((volatile  uint8_t *)(0x424E0510UL))
#define bFM4_ADC0_ADSS23_TS20                     *((volatile  uint8_t *)(0x424E0510UL))
#define bFM_ADC0_ADSS23_TS21                      *((volatile  uint8_t *)(0x424E0514UL))
#define bFM4_ADC0_ADSS23_TS21                     *((volatile  uint8_t *)(0x424E0514UL))
#define bFM_ADC0_ADSS23_TS22                      *((volatile  uint8_t *)(0x424E0518UL))
#define bFM4_ADC0_ADSS23_TS22                     *((volatile  uint8_t *)(0x424E0518UL))
#define bFM_ADC0_ADSS23_TS23                      *((volatile  uint8_t *)(0x424E051CUL))
#define bFM4_ADC0_ADSS23_TS23                     *((volatile  uint8_t *)(0x424E051CUL))
#define bFM_ADC0_ADSS23_TS24                      *((volatile  uint8_t *)(0x424E0520UL))
#define bFM4_ADC0_ADSS23_TS24                     *((volatile  uint8_t *)(0x424E0520UL))
#define bFM_ADC0_ADSS23_TS25                      *((volatile  uint8_t *)(0x424E0524UL))
#define bFM4_ADC0_ADSS23_TS25                     *((volatile  uint8_t *)(0x424E0524UL))
#define bFM_ADC0_ADSS23_TS26                      *((volatile  uint8_t *)(0x424E0528UL))
#define bFM4_ADC0_ADSS23_TS26                     *((volatile  uint8_t *)(0x424E0528UL))
#define bFM_ADC0_ADSS23_TS27                      *((volatile  uint8_t *)(0x424E052CUL))
#define bFM4_ADC0_ADSS23_TS27                     *((volatile  uint8_t *)(0x424E052CUL))
#define bFM_ADC0_ADSS23_TS28                      *((volatile  uint8_t *)(0x424E0530UL))
#define bFM4_ADC0_ADSS23_TS28                     *((volatile  uint8_t *)(0x424E0530UL))
#define bFM_ADC0_ADSS23_TS29                      *((volatile  uint8_t *)(0x424E0534UL))
#define bFM4_ADC0_ADSS23_TS29                     *((volatile  uint8_t *)(0x424E0534UL))
#define bFM_ADC0_ADSS23_TS30                      *((volatile  uint8_t *)(0x424E0538UL))
#define bFM4_ADC0_ADSS23_TS30                     *((volatile  uint8_t *)(0x424E0538UL))
#define bFM_ADC0_ADSS23_TS31                      *((volatile  uint8_t *)(0x424E053CUL))
#define bFM4_ADC0_ADSS23_TS31                     *((volatile  uint8_t *)(0x424E053CUL))

#define bFM_ADC0_CALSR_CLBEN                      *((volatile  uint8_t *)(0x424E0820UL))
#define bFM4_ADC0_CALSR_CLBEN                     *((volatile  uint8_t *)(0x424E0820UL))

#define bFM_ADC0_CMPCR_CMD0                       *((volatile  uint8_t *)(0x424E0494UL))
#define bFM4_ADC0_CMPCR_CMD0                      *((volatile  uint8_t *)(0x424E0494UL))
#define bFM_ADC0_CMPCR_CMD1                       *((volatile  uint8_t *)(0x424E0498UL))
#define bFM4_ADC0_CMPCR_CMD1                      *((volatile  uint8_t *)(0x424E0498UL))
#define bFM_ADC0_CMPCR_CMPEN                      *((volatile  uint8_t *)(0x424E049CUL))
#define bFM4_ADC0_CMPCR_CMPEN                     *((volatile  uint8_t *)(0x424E049CUL))

#define bFM_ADC0_PCCR_PSTR                        *((volatile  uint8_t *)(0x424E0320UL))
#define bFM4_ADC0_PCCR_PSTR                       *((volatile  uint8_t *)(0x424E0320UL))
#define bFM_ADC0_PCCR_PHEN                        *((volatile  uint8_t *)(0x424E0324UL))
#define bFM4_ADC0_PCCR_PHEN                       *((volatile  uint8_t *)(0x424E0324UL))
#define bFM_ADC0_PCCR_PEEN                        *((volatile  uint8_t *)(0x424E0328UL))
#define bFM4_ADC0_PCCR_PEEN                       *((volatile  uint8_t *)(0x424E0328UL))
#define bFM_ADC0_PCCR_ESCE                        *((volatile  uint8_t *)(0x424E032CUL))
#define bFM4_ADC0_PCCR_ESCE                       *((volatile  uint8_t *)(0x424E032CUL))
#define bFM_ADC0_PCCR_PFCLR                       *((volatile  uint8_t *)(0x424E0330UL))
#define bFM4_ADC0_PCCR_PFCLR                      *((volatile  uint8_t *)(0x424E0330UL))
#define bFM_ADC0_PCCR_POVR                        *((volatile  uint8_t *)(0x424E0334UL))
#define bFM4_ADC0_PCCR_POVR                       *((volatile  uint8_t *)(0x424E0334UL))
#define bFM_ADC0_PCCR_PFUL                        *((volatile  uint8_t *)(0x424E0338UL))
#define bFM4_ADC0_PCCR_PFUL                       *((volatile  uint8_t *)(0x424E0338UL))
#define bFM_ADC0_PCCR_PEMP                        *((volatile  uint8_t *)(0x424E033CUL))
#define bFM4_ADC0_PCCR_PEMP                       *((volatile  uint8_t *)(0x424E033CUL))

#define bFM_ADC0_PCFD_INVL                        *((volatile  uint8_t *)(0x424E03B0UL))
#define bFM4_ADC0_PCFD_INVL                       *((volatile  uint8_t *)(0x424E03B0UL))

#define bFM_ADC0_PCFD_FDAS1_INVL                  *((volatile  uint8_t *)(0x424E03B0UL))
#define bFM4_ADC0_PCFD_FDAS1_INVL                 *((volatile  uint8_t *)(0x424E03B0UL))

#define bFM_ADC0_SCCR_SSTR                        *((volatile  uint8_t *)(0x424E0120UL))
#define bFM4_ADC0_SCCR_SSTR                       *((volatile  uint8_t *)(0x424E0120UL))
#define bFM_ADC0_SCCR_SHEN                        *((volatile  uint8_t *)(0x424E0124UL))
#define bFM4_ADC0_SCCR_SHEN                       *((volatile  uint8_t *)(0x424E0124UL))
#define bFM_ADC0_SCCR_RPT                         *((volatile  uint8_t *)(0x424E0128UL))
#define bFM4_ADC0_SCCR_RPT                        *((volatile  uint8_t *)(0x424E0128UL))
#define bFM_ADC0_SCCR_SFCLR                       *((volatile  uint8_t *)(0x424E0130UL))
#define bFM4_ADC0_SCCR_SFCLR                      *((volatile  uint8_t *)(0x424E0130UL))
#define bFM_ADC0_SCCR_SOVR                        *((volatile  uint8_t *)(0x424E0134UL))
#define bFM4_ADC0_SCCR_SOVR                       *((volatile  uint8_t *)(0x424E0134UL))
#define bFM_ADC0_SCCR_SFUL                        *((volatile  uint8_t *)(0x424E0138UL))
#define bFM4_ADC0_SCCR_SFUL                       *((volatile  uint8_t *)(0x424E0138UL))
#define bFM_ADC0_SCCR_SEMP                        *((volatile  uint8_t *)(0x424E013CUL))
#define bFM4_ADC0_SCCR_SEMP                       *((volatile  uint8_t *)(0x424E013CUL))

#define bFM_ADC0_SCFD_INVL                        *((volatile  uint8_t *)(0x424E01B0UL))
#define bFM4_ADC0_SCFD_INVL                       *((volatile  uint8_t *)(0x424E01B0UL))

#define bFM_ADC0_SCFD_FDAS1_INVL                  *((volatile  uint8_t *)(0x424E01B0UL))
#define bFM4_ADC0_SCFD_FDAS1_INVL                 *((volatile  uint8_t *)(0x424E01B0UL))

#define bFM_ADC0_SCIS01_AN0                       *((volatile  uint8_t *)(0x424E0280UL))
#define bFM4_ADC0_SCIS01_AN0                      *((volatile  uint8_t *)(0x424E0280UL))
#define bFM_ADC0_SCIS01_AN1                       *((volatile  uint8_t *)(0x424E0284UL))
#define bFM4_ADC0_SCIS01_AN1                      *((volatile  uint8_t *)(0x424E0284UL))
#define bFM_ADC0_SCIS01_AN2                       *((volatile  uint8_t *)(0x424E0288UL))
#define bFM4_ADC0_SCIS01_AN2                      *((volatile  uint8_t *)(0x424E0288UL))
#define bFM_ADC0_SCIS01_AN3                       *((volatile  uint8_t *)(0x424E028CUL))
#define bFM4_ADC0_SCIS01_AN3                      *((volatile  uint8_t *)(0x424E028CUL))
#define bFM_ADC0_SCIS01_AN4                       *((volatile  uint8_t *)(0x424E0290UL))
#define bFM4_ADC0_SCIS01_AN4                      *((volatile  uint8_t *)(0x424E0290UL))
#define bFM_ADC0_SCIS01_AN5                       *((volatile  uint8_t *)(0x424E0294UL))
#define bFM4_ADC0_SCIS01_AN5                      *((volatile  uint8_t *)(0x424E0294UL))
#define bFM_ADC0_SCIS01_AN6                       *((volatile  uint8_t *)(0x424E0298UL))
#define bFM4_ADC0_SCIS01_AN6                      *((volatile  uint8_t *)(0x424E0298UL))
#define bFM_ADC0_SCIS01_AN7                       *((volatile  uint8_t *)(0x424E029CUL))
#define bFM4_ADC0_SCIS01_AN7                      *((volatile  uint8_t *)(0x424E029CUL))
#define bFM_ADC0_SCIS01_AN8                       *((volatile  uint8_t *)(0x424E02A0UL))
#define bFM4_ADC0_SCIS01_AN8                      *((volatile  uint8_t *)(0x424E02A0UL))
#define bFM_ADC0_SCIS01_AN9                       *((volatile  uint8_t *)(0x424E02A4UL))
#define bFM4_ADC0_SCIS01_AN9                      *((volatile  uint8_t *)(0x424E02A4UL))
#define bFM_ADC0_SCIS01_AN10                      *((volatile  uint8_t *)(0x424E02A8UL))
#define bFM4_ADC0_SCIS01_AN10                     *((volatile  uint8_t *)(0x424E02A8UL))
#define bFM_ADC0_SCIS01_AN11                      *((volatile  uint8_t *)(0x424E02ACUL))
#define bFM4_ADC0_SCIS01_AN11                     *((volatile  uint8_t *)(0x424E02ACUL))
#define bFM_ADC0_SCIS01_AN12                      *((volatile  uint8_t *)(0x424E02B0UL))
#define bFM4_ADC0_SCIS01_AN12                     *((volatile  uint8_t *)(0x424E02B0UL))
#define bFM_ADC0_SCIS01_AN13                      *((volatile  uint8_t *)(0x424E02B4UL))
#define bFM4_ADC0_SCIS01_AN13                     *((volatile  uint8_t *)(0x424E02B4UL))
#define bFM_ADC0_SCIS01_AN14                      *((volatile  uint8_t *)(0x424E02B8UL))
#define bFM4_ADC0_SCIS01_AN14                     *((volatile  uint8_t *)(0x424E02B8UL))
#define bFM_ADC0_SCIS01_AN15                      *((volatile  uint8_t *)(0x424E02BCUL))
#define bFM4_ADC0_SCIS01_AN15                     *((volatile  uint8_t *)(0x424E02BCUL))

#define bFM_ADC0_SCIS23_AN16                      *((volatile  uint8_t *)(0x424E0200UL))
#define bFM4_ADC0_SCIS23_AN16                     *((volatile  uint8_t *)(0x424E0200UL))
#define bFM_ADC0_SCIS23_AN17                      *((volatile  uint8_t *)(0x424E0204UL))
#define bFM4_ADC0_SCIS23_AN17                     *((volatile  uint8_t *)(0x424E0204UL))
#define bFM_ADC0_SCIS23_AN18                      *((volatile  uint8_t *)(0x424E0208UL))
#define bFM4_ADC0_SCIS23_AN18                     *((volatile  uint8_t *)(0x424E0208UL))
#define bFM_ADC0_SCIS23_AN19                      *((volatile  uint8_t *)(0x424E020CUL))
#define bFM4_ADC0_SCIS23_AN19                     *((volatile  uint8_t *)(0x424E020CUL))
#define bFM_ADC0_SCIS23_AN20                      *((volatile  uint8_t *)(0x424E0210UL))
#define bFM4_ADC0_SCIS23_AN20                     *((volatile  uint8_t *)(0x424E0210UL))
#define bFM_ADC0_SCIS23_AN21                      *((volatile  uint8_t *)(0x424E0214UL))
#define bFM4_ADC0_SCIS23_AN21                     *((volatile  uint8_t *)(0x424E0214UL))
#define bFM_ADC0_SCIS23_AN22                      *((volatile  uint8_t *)(0x424E0218UL))
#define bFM4_ADC0_SCIS23_AN22                     *((volatile  uint8_t *)(0x424E0218UL))
#define bFM_ADC0_SCIS23_AN23                      *((volatile  uint8_t *)(0x424E021CUL))
#define bFM4_ADC0_SCIS23_AN23                     *((volatile  uint8_t *)(0x424E021CUL))
#define bFM_ADC0_SCIS23_AN24                      *((volatile  uint8_t *)(0x424E0220UL))
#define bFM4_ADC0_SCIS23_AN24                     *((volatile  uint8_t *)(0x424E0220UL))
#define bFM_ADC0_SCIS23_AN25                      *((volatile  uint8_t *)(0x424E0224UL))
#define bFM4_ADC0_SCIS23_AN25                     *((volatile  uint8_t *)(0x424E0224UL))
#define bFM_ADC0_SCIS23_AN26                      *((volatile  uint8_t *)(0x424E0228UL))
#define bFM4_ADC0_SCIS23_AN26                     *((volatile  uint8_t *)(0x424E0228UL))
#define bFM_ADC0_SCIS23_AN27                      *((volatile  uint8_t *)(0x424E022CUL))
#define bFM4_ADC0_SCIS23_AN27                     *((volatile  uint8_t *)(0x424E022CUL))
#define bFM_ADC0_SCIS23_AN28                      *((volatile  uint8_t *)(0x424E0230UL))
#define bFM4_ADC0_SCIS23_AN28                     *((volatile  uint8_t *)(0x424E0230UL))
#define bFM_ADC0_SCIS23_AN29                      *((volatile  uint8_t *)(0x424E0234UL))
#define bFM4_ADC0_SCIS23_AN29                     *((volatile  uint8_t *)(0x424E0234UL))
#define bFM_ADC0_SCIS23_AN30                      *((volatile  uint8_t *)(0x424E0238UL))
#define bFM4_ADC0_SCIS23_AN30                     *((volatile  uint8_t *)(0x424E0238UL))
#define bFM_ADC0_SCIS23_AN31                      *((volatile  uint8_t *)(0x424E023CUL))
#define bFM4_ADC0_SCIS23_AN31                     *((volatile  uint8_t *)(0x424E023CUL))

#define bFM_ADC0_WCMPCR_RCOE                      *((volatile  uint8_t *)(0x424E0988UL))
#define bFM4_ADC0_WCMPCR_RCOE                     *((volatile  uint8_t *)(0x424E0988UL))
#define bFM_ADC0_WCMPCR_RCOIE                     *((volatile  uint8_t *)(0x424E098CUL))
#define bFM4_ADC0_WCMPCR_RCOIE                    *((volatile  uint8_t *)(0x424E098CUL))
#define bFM_ADC0_WCMPCR_RCOIRS                    *((volatile  uint8_t *)(0x424E0990UL))
#define bFM4_ADC0_WCMPCR_RCOIRS                   *((volatile  uint8_t *)(0x424E0990UL))

#define bFM_ADC0_WCMPSR_WCMD                      *((volatile  uint8_t *)(0x424E09B4UL))
#define bFM4_ADC0_WCMPSR_WCMD                     *((volatile  uint8_t *)(0x424E09B4UL))

#define bFM_ADC0_WCMRCIF_RCINT                    *((volatile  uint8_t *)(0x424E0900UL))
#define bFM4_ADC0_WCMRCIF_RCINT                   *((volatile  uint8_t *)(0x424E0900UL))

#define bFM_ADC0_WCMRCOT_RCOOF                    *((volatile  uint8_t *)(0x424E0880UL))
#define bFM4_ADC0_WCMRCOT_RCOOF                   *((volatile  uint8_t *)(0x424E0880UL))


/*******************************************************************************
* ADC Registers ADC1
*   Bitband Section
*******************************************************************************/
#define bFM_ADC1_ADCEN_ENBL                       *((volatile  uint8_t *)(0x424E2780UL))
#define bFM4_ADC1_ADCEN_ENBL                      *((volatile  uint8_t *)(0x424E2780UL))
#define bFM_ADC1_ADCEN_READY                      *((volatile  uint8_t *)(0x424E2784UL))
#define bFM4_ADC1_ADCEN_READY                     *((volatile  uint8_t *)(0x424E2784UL))

#define bFM_ADC1_ADCR_OVRIE                       *((volatile  uint8_t *)(0x424E2020UL))
#define bFM4_ADC1_ADCR_OVRIE                      *((volatile  uint8_t *)(0x424E2020UL))
#define bFM_ADC1_ADCR_CMPIE                       *((volatile  uint8_t *)(0x424E2024UL))
#define bFM4_ADC1_ADCR_CMPIE                      *((volatile  uint8_t *)(0x424E2024UL))
#define bFM_ADC1_ADCR_PCIE                        *((volatile  uint8_t *)(0x424E2028UL))
#define bFM4_ADC1_ADCR_PCIE                       *((volatile  uint8_t *)(0x424E2028UL))
#define bFM_ADC1_ADCR_SCIE                        *((volatile  uint8_t *)(0x424E202CUL))
#define bFM4_ADC1_ADCR_SCIE                       *((volatile  uint8_t *)(0x424E202CUL))
#define bFM_ADC1_ADCR_CMPIF                       *((volatile  uint8_t *)(0x424E2034UL))
#define bFM4_ADC1_ADCR_CMPIF                      *((volatile  uint8_t *)(0x424E2034UL))
#define bFM_ADC1_ADCR_PCIF                        *((volatile  uint8_t *)(0x424E2038UL))
#define bFM4_ADC1_ADCR_PCIF                       *((volatile  uint8_t *)(0x424E2038UL))
#define bFM_ADC1_ADCR_SCIF                        *((volatile  uint8_t *)(0x424E203CUL))
#define bFM4_ADC1_ADCR_SCIF                       *((volatile  uint8_t *)(0x424E203CUL))

#define bFM_ADC1_ADSR_SCS                         *((volatile  uint8_t *)(0x424E2000UL))
#define bFM4_ADC1_ADSR_SCS                        *((volatile  uint8_t *)(0x424E2000UL))
#define bFM_ADC1_ADSR_PCS                         *((volatile  uint8_t *)(0x424E2004UL))
#define bFM4_ADC1_ADSR_PCS                        *((volatile  uint8_t *)(0x424E2004UL))
#define bFM_ADC1_ADSR_PCNS                        *((volatile  uint8_t *)(0x424E2008UL))
#define bFM4_ADC1_ADSR_PCNS                       *((volatile  uint8_t *)(0x424E2008UL))
#define bFM_ADC1_ADSR_FDAS                        *((volatile  uint8_t *)(0x424E2018UL))
#define bFM4_ADC1_ADSR_FDAS                       *((volatile  uint8_t *)(0x424E2018UL))
#define bFM_ADC1_ADSR_ADSTP                       *((volatile  uint8_t *)(0x424E201CUL))
#define bFM4_ADC1_ADSR_ADSTP                      *((volatile  uint8_t *)(0x424E201CUL))

#define bFM_ADC1_ADSS01_TS0                       *((volatile  uint8_t *)(0x424E2580UL))
#define bFM4_ADC1_ADSS01_TS0                      *((volatile  uint8_t *)(0x424E2580UL))
#define bFM_ADC1_ADSS01_TS1                       *((volatile  uint8_t *)(0x424E2584UL))
#define bFM4_ADC1_ADSS01_TS1                      *((volatile  uint8_t *)(0x424E2584UL))
#define bFM_ADC1_ADSS01_TS2                       *((volatile  uint8_t *)(0x424E2588UL))
#define bFM4_ADC1_ADSS01_TS2                      *((volatile  uint8_t *)(0x424E2588UL))
#define bFM_ADC1_ADSS01_TS3                       *((volatile  uint8_t *)(0x424E258CUL))
#define bFM4_ADC1_ADSS01_TS3                      *((volatile  uint8_t *)(0x424E258CUL))
#define bFM_ADC1_ADSS01_TS4                       *((volatile  uint8_t *)(0x424E2590UL))
#define bFM4_ADC1_ADSS01_TS4                      *((volatile  uint8_t *)(0x424E2590UL))
#define bFM_ADC1_ADSS01_TS5                       *((volatile  uint8_t *)(0x424E2594UL))
#define bFM4_ADC1_ADSS01_TS5                      *((volatile  uint8_t *)(0x424E2594UL))
#define bFM_ADC1_ADSS01_TS6                       *((volatile  uint8_t *)(0x424E2598UL))
#define bFM4_ADC1_ADSS01_TS6                      *((volatile  uint8_t *)(0x424E2598UL))
#define bFM_ADC1_ADSS01_TS7                       *((volatile  uint8_t *)(0x424E259CUL))
#define bFM4_ADC1_ADSS01_TS7                      *((volatile  uint8_t *)(0x424E259CUL))
#define bFM_ADC1_ADSS01_TS8                       *((volatile  uint8_t *)(0x424E25A0UL))
#define bFM4_ADC1_ADSS01_TS8                      *((volatile  uint8_t *)(0x424E25A0UL))
#define bFM_ADC1_ADSS01_TS9                       *((volatile  uint8_t *)(0x424E25A4UL))
#define bFM4_ADC1_ADSS01_TS9                      *((volatile  uint8_t *)(0x424E25A4UL))
#define bFM_ADC1_ADSS01_TS10                      *((volatile  uint8_t *)(0x424E25A8UL))
#define bFM4_ADC1_ADSS01_TS10                     *((volatile  uint8_t *)(0x424E25A8UL))
#define bFM_ADC1_ADSS01_TS11                      *((volatile  uint8_t *)(0x424E25ACUL))
#define bFM4_ADC1_ADSS01_TS11                     *((volatile  uint8_t *)(0x424E25ACUL))
#define bFM_ADC1_ADSS01_TS12                      *((volatile  uint8_t *)(0x424E25B0UL))
#define bFM4_ADC1_ADSS01_TS12                     *((volatile  uint8_t *)(0x424E25B0UL))
#define bFM_ADC1_ADSS01_TS13                      *((volatile  uint8_t *)(0x424E25B4UL))
#define bFM4_ADC1_ADSS01_TS13                     *((volatile  uint8_t *)(0x424E25B4UL))
#define bFM_ADC1_ADSS01_TS14                      *((volatile  uint8_t *)(0x424E25B8UL))
#define bFM4_ADC1_ADSS01_TS14                     *((volatile  uint8_t *)(0x424E25B8UL))
#define bFM_ADC1_ADSS01_TS15                      *((volatile  uint8_t *)(0x424E25BCUL))
#define bFM4_ADC1_ADSS01_TS15                     *((volatile  uint8_t *)(0x424E25BCUL))

#define bFM_ADC1_ADSS23_TS16                      *((volatile  uint8_t *)(0x424E2500UL))
#define bFM4_ADC1_ADSS23_TS16                     *((volatile  uint8_t *)(0x424E2500UL))
#define bFM_ADC1_ADSS23_TS17                      *((volatile  uint8_t *)(0x424E2504UL))
#define bFM4_ADC1_ADSS23_TS17                     *((volatile  uint8_t *)(0x424E2504UL))
#define bFM_ADC1_ADSS23_TS18                      *((volatile  uint8_t *)(0x424E2508UL))
#define bFM4_ADC1_ADSS23_TS18                     *((volatile  uint8_t *)(0x424E2508UL))
#define bFM_ADC1_ADSS23_TS19                      *((volatile  uint8_t *)(0x424E250CUL))
#define bFM4_ADC1_ADSS23_TS19                     *((volatile  uint8_t *)(0x424E250CUL))
#define bFM_ADC1_ADSS23_TS20                      *((volatile  uint8_t *)(0x424E2510UL))
#define bFM4_ADC1_ADSS23_TS20                     *((volatile  uint8_t *)(0x424E2510UL))
#define bFM_ADC1_ADSS23_TS21                      *((volatile  uint8_t *)(0x424E2514UL))
#define bFM4_ADC1_ADSS23_TS21                     *((volatile  uint8_t *)(0x424E2514UL))
#define bFM_ADC1_ADSS23_TS22                      *((volatile  uint8_t *)(0x424E2518UL))
#define bFM4_ADC1_ADSS23_TS22                     *((volatile  uint8_t *)(0x424E2518UL))
#define bFM_ADC1_ADSS23_TS23                      *((volatile  uint8_t *)(0x424E251CUL))
#define bFM4_ADC1_ADSS23_TS23                     *((volatile  uint8_t *)(0x424E251CUL))
#define bFM_ADC1_ADSS23_TS24                      *((volatile  uint8_t *)(0x424E2520UL))
#define bFM4_ADC1_ADSS23_TS24                     *((volatile  uint8_t *)(0x424E2520UL))
#define bFM_ADC1_ADSS23_TS25                      *((volatile  uint8_t *)(0x424E2524UL))
#define bFM4_ADC1_ADSS23_TS25                     *((volatile  uint8_t *)(0x424E2524UL))
#define bFM_ADC1_ADSS23_TS26                      *((volatile  uint8_t *)(0x424E2528UL))
#define bFM4_ADC1_ADSS23_TS26                     *((volatile  uint8_t *)(0x424E2528UL))
#define bFM_ADC1_ADSS23_TS27                      *((volatile  uint8_t *)(0x424E252CUL))
#define bFM4_ADC1_ADSS23_TS27                     *((volatile  uint8_t *)(0x424E252CUL))
#define bFM_ADC1_ADSS23_TS28                      *((volatile  uint8_t *)(0x424E2530UL))
#define bFM4_ADC1_ADSS23_TS28                     *((volatile  uint8_t *)(0x424E2530UL))
#define bFM_ADC1_ADSS23_TS29                      *((volatile  uint8_t *)(0x424E2534UL))
#define bFM4_ADC1_ADSS23_TS29                     *((volatile  uint8_t *)(0x424E2534UL))
#define bFM_ADC1_ADSS23_TS30                      *((volatile  uint8_t *)(0x424E2538UL))
#define bFM4_ADC1_ADSS23_TS30                     *((volatile  uint8_t *)(0x424E2538UL))
#define bFM_ADC1_ADSS23_TS31                      *((volatile  uint8_t *)(0x424E253CUL))
#define bFM4_ADC1_ADSS23_TS31                     *((volatile  uint8_t *)(0x424E253CUL))

#define bFM_ADC1_CALSR_CLBEN                      *((volatile  uint8_t *)(0x424E2820UL))
#define bFM4_ADC1_CALSR_CLBEN                     *((volatile  uint8_t *)(0x424E2820UL))

#define bFM_ADC1_CMPCR_CMD0                       *((volatile  uint8_t *)(0x424E2494UL))
#define bFM4_ADC1_CMPCR_CMD0                      *((volatile  uint8_t *)(0x424E2494UL))
#define bFM_ADC1_CMPCR_CMD1                       *((volatile  uint8_t *)(0x424E2498UL))
#define bFM4_ADC1_CMPCR_CMD1                      *((volatile  uint8_t *)(0x424E2498UL))
#define bFM_ADC1_CMPCR_CMPEN                      *((volatile  uint8_t *)(0x424E249CUL))
#define bFM4_ADC1_CMPCR_CMPEN                     *((volatile  uint8_t *)(0x424E249CUL))

#define bFM_ADC1_PCCR_PSTR                        *((volatile  uint8_t *)(0x424E2320UL))
#define bFM4_ADC1_PCCR_PSTR                       *((volatile  uint8_t *)(0x424E2320UL))
#define bFM_ADC1_PCCR_PHEN                        *((volatile  uint8_t *)(0x424E2324UL))
#define bFM4_ADC1_PCCR_PHEN                       *((volatile  uint8_t *)(0x424E2324UL))
#define bFM_ADC1_PCCR_PEEN                        *((volatile  uint8_t *)(0x424E2328UL))
#define bFM4_ADC1_PCCR_PEEN                       *((volatile  uint8_t *)(0x424E2328UL))
#define bFM_ADC1_PCCR_ESCE                        *((volatile  uint8_t *)(0x424E232CUL))
#define bFM4_ADC1_PCCR_ESCE                       *((volatile  uint8_t *)(0x424E232CUL))
#define bFM_ADC1_PCCR_PFCLR                       *((volatile  uint8_t *)(0x424E2330UL))
#define bFM4_ADC1_PCCR_PFCLR                      *((volatile  uint8_t *)(0x424E2330UL))
#define bFM_ADC1_PCCR_POVR                        *((volatile  uint8_t *)(0x424E2334UL))
#define bFM4_ADC1_PCCR_POVR                       *((volatile  uint8_t *)(0x424E2334UL))
#define bFM_ADC1_PCCR_PFUL                        *((volatile  uint8_t *)(0x424E2338UL))
#define bFM4_ADC1_PCCR_PFUL                       *((volatile  uint8_t *)(0x424E2338UL))
#define bFM_ADC1_PCCR_PEMP                        *((volatile  uint8_t *)(0x424E233CUL))
#define bFM4_ADC1_PCCR_PEMP                       *((volatile  uint8_t *)(0x424E233CUL))

#define bFM_ADC1_PCFD_INVL                        *((volatile  uint8_t *)(0x424E23B0UL))
#define bFM4_ADC1_PCFD_INVL                       *((volatile  uint8_t *)(0x424E23B0UL))

#define bFM_ADC1_PCFD_FDAS1_INVL                  *((volatile  uint8_t *)(0x424E23B0UL))
#define bFM4_ADC1_PCFD_FDAS1_INVL                 *((volatile  uint8_t *)(0x424E23B0UL))

#define bFM_ADC1_SCCR_SSTR                        *((volatile  uint8_t *)(0x424E2120UL))
#define bFM4_ADC1_SCCR_SSTR                       *((volatile  uint8_t *)(0x424E2120UL))
#define bFM_ADC1_SCCR_SHEN                        *((volatile  uint8_t *)(0x424E2124UL))
#define bFM4_ADC1_SCCR_SHEN                       *((volatile  uint8_t *)(0x424E2124UL))
#define bFM_ADC1_SCCR_RPT                         *((volatile  uint8_t *)(0x424E2128UL))
#define bFM4_ADC1_SCCR_RPT                        *((volatile  uint8_t *)(0x424E2128UL))
#define bFM_ADC1_SCCR_SFCLR                       *((volatile  uint8_t *)(0x424E2130UL))
#define bFM4_ADC1_SCCR_SFCLR                      *((volatile  uint8_t *)(0x424E2130UL))
#define bFM_ADC1_SCCR_SOVR                        *((volatile  uint8_t *)(0x424E2134UL))
#define bFM4_ADC1_SCCR_SOVR                       *((volatile  uint8_t *)(0x424E2134UL))
#define bFM_ADC1_SCCR_SFUL                        *((volatile  uint8_t *)(0x424E2138UL))
#define bFM4_ADC1_SCCR_SFUL                       *((volatile  uint8_t *)(0x424E2138UL))
#define bFM_ADC1_SCCR_SEMP                        *((volatile  uint8_t *)(0x424E213CUL))
#define bFM4_ADC1_SCCR_SEMP                       *((volatile  uint8_t *)(0x424E213CUL))

#define bFM_ADC1_SCFD_INVL                        *((volatile  uint8_t *)(0x424E21B0UL))
#define bFM4_ADC1_SCFD_INVL                       *((volatile  uint8_t *)(0x424E21B0UL))

#define bFM_ADC1_SCFD_FDAS1_INVL                  *((volatile  uint8_t *)(0x424E21B0UL))
#define bFM4_ADC1_SCFD_FDAS1_INVL                 *((volatile  uint8_t *)(0x424E21B0UL))

#define bFM_ADC1_SCIS01_AN0                       *((volatile  uint8_t *)(0x424E2280UL))
#define bFM4_ADC1_SCIS01_AN0                      *((volatile  uint8_t *)(0x424E2280UL))
#define bFM_ADC1_SCIS01_AN1                       *((volatile  uint8_t *)(0x424E2284UL))
#define bFM4_ADC1_SCIS01_AN1                      *((volatile  uint8_t *)(0x424E2284UL))
#define bFM_ADC1_SCIS01_AN2                       *((volatile  uint8_t *)(0x424E2288UL))
#define bFM4_ADC1_SCIS01_AN2                      *((volatile  uint8_t *)(0x424E2288UL))
#define bFM_ADC1_SCIS01_AN3                       *((volatile  uint8_t *)(0x424E228CUL))
#define bFM4_ADC1_SCIS01_AN3                      *((volatile  uint8_t *)(0x424E228CUL))
#define bFM_ADC1_SCIS01_AN4                       *((volatile  uint8_t *)(0x424E2290UL))
#define bFM4_ADC1_SCIS01_AN4                      *((volatile  uint8_t *)(0x424E2290UL))
#define bFM_ADC1_SCIS01_AN5                       *((volatile  uint8_t *)(0x424E2294UL))
#define bFM4_ADC1_SCIS01_AN5                      *((volatile  uint8_t *)(0x424E2294UL))
#define bFM_ADC1_SCIS01_AN6                       *((volatile  uint8_t *)(0x424E2298UL))
#define bFM4_ADC1_SCIS01_AN6                      *((volatile  uint8_t *)(0x424E2298UL))
#define bFM_ADC1_SCIS01_AN7                       *((volatile  uint8_t *)(0x424E229CUL))
#define bFM4_ADC1_SCIS01_AN7                      *((volatile  uint8_t *)(0x424E229CUL))
#define bFM_ADC1_SCIS01_AN8                       *((volatile  uint8_t *)(0x424E22A0UL))
#define bFM4_ADC1_SCIS01_AN8                      *((volatile  uint8_t *)(0x424E22A0UL))
#define bFM_ADC1_SCIS01_AN9                       *((volatile  uint8_t *)(0x424E22A4UL))
#define bFM4_ADC1_SCIS01_AN9                      *((volatile  uint8_t *)(0x424E22A4UL))
#define bFM_ADC1_SCIS01_AN10                      *((volatile  uint8_t *)(0x424E22A8UL))
#define bFM4_ADC1_SCIS01_AN10                     *((volatile  uint8_t *)(0x424E22A8UL))
#define bFM_ADC1_SCIS01_AN11                      *((volatile  uint8_t *)(0x424E22ACUL))
#define bFM4_ADC1_SCIS01_AN11                     *((volatile  uint8_t *)(0x424E22ACUL))
#define bFM_ADC1_SCIS01_AN12                      *((volatile  uint8_t *)(0x424E22B0UL))
#define bFM4_ADC1_SCIS01_AN12                     *((volatile  uint8_t *)(0x424E22B0UL))
#define bFM_ADC1_SCIS01_AN13                      *((volatile  uint8_t *)(0x424E22B4UL))
#define bFM4_ADC1_SCIS01_AN13                     *((volatile  uint8_t *)(0x424E22B4UL))
#define bFM_ADC1_SCIS01_AN14                      *((volatile  uint8_t *)(0x424E22B8UL))
#define bFM4_ADC1_SCIS01_AN14                     *((volatile  uint8_t *)(0x424E22B8UL))
#define bFM_ADC1_SCIS01_AN15                      *((volatile  uint8_t *)(0x424E22BCUL))
#define bFM4_ADC1_SCIS01_AN15                     *((volatile  uint8_t *)(0x424E22BCUL))

#define bFM_ADC1_SCIS23_AN16                      *((volatile  uint8_t *)(0x424E2200UL))
#define bFM4_ADC1_SCIS23_AN16                     *((volatile  uint8_t *)(0x424E2200UL))
#define bFM_ADC1_SCIS23_AN17                      *((volatile  uint8_t *)(0x424E2204UL))
#define bFM4_ADC1_SCIS23_AN17                     *((volatile  uint8_t *)(0x424E2204UL))
#define bFM_ADC1_SCIS23_AN18                      *((volatile  uint8_t *)(0x424E2208UL))
#define bFM4_ADC1_SCIS23_AN18                     *((volatile  uint8_t *)(0x424E2208UL))
#define bFM_ADC1_SCIS23_AN19                      *((volatile  uint8_t *)(0x424E220CUL))
#define bFM4_ADC1_SCIS23_AN19                     *((volatile  uint8_t *)(0x424E220CUL))
#define bFM_ADC1_SCIS23_AN20                      *((volatile  uint8_t *)(0x424E2210UL))
#define bFM4_ADC1_SCIS23_AN20                     *((volatile  uint8_t *)(0x424E2210UL))
#define bFM_ADC1_SCIS23_AN21                      *((volatile  uint8_t *)(0x424E2214UL))
#define bFM4_ADC1_SCIS23_AN21                     *((volatile  uint8_t *)(0x424E2214UL))
#define bFM_ADC1_SCIS23_AN22                      *((volatile  uint8_t *)(0x424E2218UL))
#define bFM4_ADC1_SCIS23_AN22                     *((volatile  uint8_t *)(0x424E2218UL))
#define bFM_ADC1_SCIS23_AN23                      *((volatile  uint8_t *)(0x424E221CUL))
#define bFM4_ADC1_SCIS23_AN23                     *((volatile  uint8_t *)(0x424E221CUL))
#define bFM_ADC1_SCIS23_AN24                      *((volatile  uint8_t *)(0x424E2220UL))
#define bFM4_ADC1_SCIS23_AN24                     *((volatile  uint8_t *)(0x424E2220UL))
#define bFM_ADC1_SCIS23_AN25                      *((volatile  uint8_t *)(0x424E2224UL))
#define bFM4_ADC1_SCIS23_AN25                     *((volatile  uint8_t *)(0x424E2224UL))
#define bFM_ADC1_SCIS23_AN26                      *((volatile  uint8_t *)(0x424E2228UL))
#define bFM4_ADC1_SCIS23_AN26                     *((volatile  uint8_t *)(0x424E2228UL))
#define bFM_ADC1_SCIS23_AN27                      *((volatile  uint8_t *)(0x424E222CUL))
#define bFM4_ADC1_SCIS23_AN27                     *((volatile  uint8_t *)(0x424E222CUL))
#define bFM_ADC1_SCIS23_AN28                      *((volatile  uint8_t *)(0x424E2230UL))
#define bFM4_ADC1_SCIS23_AN28                     *((volatile  uint8_t *)(0x424E2230UL))
#define bFM_ADC1_SCIS23_AN29                      *((volatile  uint8_t *)(0x424E2234UL))
#define bFM4_ADC1_SCIS23_AN29                     *((volatile  uint8_t *)(0x424E2234UL))
#define bFM_ADC1_SCIS23_AN30                      *((volatile  uint8_t *)(0x424E2238UL))
#define bFM4_ADC1_SCIS23_AN30                     *((volatile  uint8_t *)(0x424E2238UL))
#define bFM_ADC1_SCIS23_AN31                      *((volatile  uint8_t *)(0x424E223CUL))
#define bFM4_ADC1_SCIS23_AN31                     *((volatile  uint8_t *)(0x424E223CUL))

#define bFM_ADC1_WCMPCR_RCOE                      *((volatile  uint8_t *)(0x424E2988UL))
#define bFM4_ADC1_WCMPCR_RCOE                     *((volatile  uint8_t *)(0x424E2988UL))
#define bFM_ADC1_WCMPCR_RCOIE                     *((volatile  uint8_t *)(0x424E298CUL))
#define bFM4_ADC1_WCMPCR_RCOIE                    *((volatile  uint8_t *)(0x424E298CUL))
#define bFM_ADC1_WCMPCR_RCOIRS                    *((volatile  uint8_t *)(0x424E2990UL))
#define bFM4_ADC1_WCMPCR_RCOIRS                   *((volatile  uint8_t *)(0x424E2990UL))

#define bFM_ADC1_WCMPSR_WCMD                      *((volatile  uint8_t *)(0x424E29B4UL))
#define bFM4_ADC1_WCMPSR_WCMD                     *((volatile  uint8_t *)(0x424E29B4UL))

#define bFM_ADC1_WCMRCIF_RCINT                    *((volatile  uint8_t *)(0x424E2900UL))
#define bFM4_ADC1_WCMRCIF_RCINT                   *((volatile  uint8_t *)(0x424E2900UL))

#define bFM_ADC1_WCMRCOT_RCOOF                    *((volatile  uint8_t *)(0x424E2880UL))
#define bFM4_ADC1_WCMRCOT_RCOOF                   *((volatile  uint8_t *)(0x424E2880UL))


/*******************************************************************************
* ADC Registers ADC2
*   Bitband Section
*******************************************************************************/
#define bFM_ADC2_ADCEN_ENBL                       *((volatile  uint8_t *)(0x424E4780UL))
#define bFM4_ADC2_ADCEN_ENBL                      *((volatile  uint8_t *)(0x424E4780UL))
#define bFM_ADC2_ADCEN_READY                      *((volatile  uint8_t *)(0x424E4784UL))
#define bFM4_ADC2_ADCEN_READY                     *((volatile  uint8_t *)(0x424E4784UL))

#define bFM_ADC2_ADCR_OVRIE                       *((volatile  uint8_t *)(0x424E4020UL))
#define bFM4_ADC2_ADCR_OVRIE                      *((volatile  uint8_t *)(0x424E4020UL))
#define bFM_ADC2_ADCR_CMPIE                       *((volatile  uint8_t *)(0x424E4024UL))
#define bFM4_ADC2_ADCR_CMPIE                      *((volatile  uint8_t *)(0x424E4024UL))
#define bFM_ADC2_ADCR_PCIE                        *((volatile  uint8_t *)(0x424E4028UL))
#define bFM4_ADC2_ADCR_PCIE                       *((volatile  uint8_t *)(0x424E4028UL))
#define bFM_ADC2_ADCR_SCIE                        *((volatile  uint8_t *)(0x424E402CUL))
#define bFM4_ADC2_ADCR_SCIE                       *((volatile  uint8_t *)(0x424E402CUL))
#define bFM_ADC2_ADCR_CMPIF                       *((volatile  uint8_t *)(0x424E4034UL))
#define bFM4_ADC2_ADCR_CMPIF                      *((volatile  uint8_t *)(0x424E4034UL))
#define bFM_ADC2_ADCR_PCIF                        *((volatile  uint8_t *)(0x424E4038UL))
#define bFM4_ADC2_ADCR_PCIF                       *((volatile  uint8_t *)(0x424E4038UL))
#define bFM_ADC2_ADCR_SCIF                        *((volatile  uint8_t *)(0x424E403CUL))
#define bFM4_ADC2_ADCR_SCIF                       *((volatile  uint8_t *)(0x424E403CUL))

#define bFM_ADC2_ADSR_SCS                         *((volatile  uint8_t *)(0x424E4000UL))
#define bFM4_ADC2_ADSR_SCS                        *((volatile  uint8_t *)(0x424E4000UL))
#define bFM_ADC2_ADSR_PCS                         *((volatile  uint8_t *)(0x424E4004UL))
#define bFM4_ADC2_ADSR_PCS                        *((volatile  uint8_t *)(0x424E4004UL))
#define bFM_ADC2_ADSR_PCNS                        *((volatile  uint8_t *)(0x424E4008UL))
#define bFM4_ADC2_ADSR_PCNS                       *((volatile  uint8_t *)(0x424E4008UL))
#define bFM_ADC2_ADSR_FDAS                        *((volatile  uint8_t *)(0x424E4018UL))
#define bFM4_ADC2_ADSR_FDAS                       *((volatile  uint8_t *)(0x424E4018UL))
#define bFM_ADC2_ADSR_ADSTP                       *((volatile  uint8_t *)(0x424E401CUL))
#define bFM4_ADC2_ADSR_ADSTP                      *((volatile  uint8_t *)(0x424E401CUL))

#define bFM_ADC2_ADSS01_TS0                       *((volatile  uint8_t *)(0x424E4580UL))
#define bFM4_ADC2_ADSS01_TS0                      *((volatile  uint8_t *)(0x424E4580UL))
#define bFM_ADC2_ADSS01_TS1                       *((volatile  uint8_t *)(0x424E4584UL))
#define bFM4_ADC2_ADSS01_TS1                      *((volatile  uint8_t *)(0x424E4584UL))
#define bFM_ADC2_ADSS01_TS2                       *((volatile  uint8_t *)(0x424E4588UL))
#define bFM4_ADC2_ADSS01_TS2                      *((volatile  uint8_t *)(0x424E4588UL))
#define bFM_ADC2_ADSS01_TS3                       *((volatile  uint8_t *)(0x424E458CUL))
#define bFM4_ADC2_ADSS01_TS3                      *((volatile  uint8_t *)(0x424E458CUL))
#define bFM_ADC2_ADSS01_TS4                       *((volatile  uint8_t *)(0x424E4590UL))
#define bFM4_ADC2_ADSS01_TS4                      *((volatile  uint8_t *)(0x424E4590UL))
#define bFM_ADC2_ADSS01_TS5                       *((volatile  uint8_t *)(0x424E4594UL))
#define bFM4_ADC2_ADSS01_TS5                      *((volatile  uint8_t *)(0x424E4594UL))
#define bFM_ADC2_ADSS01_TS6                       *((volatile  uint8_t *)(0x424E4598UL))
#define bFM4_ADC2_ADSS01_TS6                      *((volatile  uint8_t *)(0x424E4598UL))
#define bFM_ADC2_ADSS01_TS7                       *((volatile  uint8_t *)(0x424E459CUL))
#define bFM4_ADC2_ADSS01_TS7                      *((volatile  uint8_t *)(0x424E459CUL))
#define bFM_ADC2_ADSS01_TS8                       *((volatile  uint8_t *)(0x424E45A0UL))
#define bFM4_ADC2_ADSS01_TS8                      *((volatile  uint8_t *)(0x424E45A0UL))
#define bFM_ADC2_ADSS01_TS9                       *((volatile  uint8_t *)(0x424E45A4UL))
#define bFM4_ADC2_ADSS01_TS9                      *((volatile  uint8_t *)(0x424E45A4UL))
#define bFM_ADC2_ADSS01_TS10                      *((volatile  uint8_t *)(0x424E45A8UL))
#define bFM4_ADC2_ADSS01_TS10                     *((volatile  uint8_t *)(0x424E45A8UL))
#define bFM_ADC2_ADSS01_TS11                      *((volatile  uint8_t *)(0x424E45ACUL))
#define bFM4_ADC2_ADSS01_TS11                     *((volatile  uint8_t *)(0x424E45ACUL))
#define bFM_ADC2_ADSS01_TS12                      *((volatile  uint8_t *)(0x424E45B0UL))
#define bFM4_ADC2_ADSS01_TS12                     *((volatile  uint8_t *)(0x424E45B0UL))
#define bFM_ADC2_ADSS01_TS13                      *((volatile  uint8_t *)(0x424E45B4UL))
#define bFM4_ADC2_ADSS01_TS13                     *((volatile  uint8_t *)(0x424E45B4UL))
#define bFM_ADC2_ADSS01_TS14                      *((volatile  uint8_t *)(0x424E45B8UL))
#define bFM4_ADC2_ADSS01_TS14                     *((volatile  uint8_t *)(0x424E45B8UL))
#define bFM_ADC2_ADSS01_TS15                      *((volatile  uint8_t *)(0x424E45BCUL))
#define bFM4_ADC2_ADSS01_TS15                     *((volatile  uint8_t *)(0x424E45BCUL))

#define bFM_ADC2_ADSS23_TS16                      *((volatile  uint8_t *)(0x424E4500UL))
#define bFM4_ADC2_ADSS23_TS16                     *((volatile  uint8_t *)(0x424E4500UL))
#define bFM_ADC2_ADSS23_TS17                      *((volatile  uint8_t *)(0x424E4504UL))
#define bFM4_ADC2_ADSS23_TS17                     *((volatile  uint8_t *)(0x424E4504UL))
#define bFM_ADC2_ADSS23_TS18                      *((volatile  uint8_t *)(0x424E4508UL))
#define bFM4_ADC2_ADSS23_TS18                     *((volatile  uint8_t *)(0x424E4508UL))
#define bFM_ADC2_ADSS23_TS19                      *((volatile  uint8_t *)(0x424E450CUL))
#define bFM4_ADC2_ADSS23_TS19                     *((volatile  uint8_t *)(0x424E450CUL))
#define bFM_ADC2_ADSS23_TS20                      *((volatile  uint8_t *)(0x424E4510UL))
#define bFM4_ADC2_ADSS23_TS20                     *((volatile  uint8_t *)(0x424E4510UL))
#define bFM_ADC2_ADSS23_TS21                      *((volatile  uint8_t *)(0x424E4514UL))
#define bFM4_ADC2_ADSS23_TS21                     *((volatile  uint8_t *)(0x424E4514UL))
#define bFM_ADC2_ADSS23_TS22                      *((volatile  uint8_t *)(0x424E4518UL))
#define bFM4_ADC2_ADSS23_TS22                     *((volatile  uint8_t *)(0x424E4518UL))
#define bFM_ADC2_ADSS23_TS23                      *((volatile  uint8_t *)(0x424E451CUL))
#define bFM4_ADC2_ADSS23_TS23                     *((volatile  uint8_t *)(0x424E451CUL))
#define bFM_ADC2_ADSS23_TS24                      *((volatile  uint8_t *)(0x424E4520UL))
#define bFM4_ADC2_ADSS23_TS24                     *((volatile  uint8_t *)(0x424E4520UL))
#define bFM_ADC2_ADSS23_TS25                      *((volatile  uint8_t *)(0x424E4524UL))
#define bFM4_ADC2_ADSS23_TS25                     *((volatile  uint8_t *)(0x424E4524UL))
#define bFM_ADC2_ADSS23_TS26                      *((volatile  uint8_t *)(0x424E4528UL))
#define bFM4_ADC2_ADSS23_TS26                     *((volatile  uint8_t *)(0x424E4528UL))
#define bFM_ADC2_ADSS23_TS27                      *((volatile  uint8_t *)(0x424E452CUL))
#define bFM4_ADC2_ADSS23_TS27                     *((volatile  uint8_t *)(0x424E452CUL))
#define bFM_ADC2_ADSS23_TS28                      *((volatile  uint8_t *)(0x424E4530UL))
#define bFM4_ADC2_ADSS23_TS28                     *((volatile  uint8_t *)(0x424E4530UL))
#define bFM_ADC2_ADSS23_TS29                      *((volatile  uint8_t *)(0x424E4534UL))
#define bFM4_ADC2_ADSS23_TS29                     *((volatile  uint8_t *)(0x424E4534UL))
#define bFM_ADC2_ADSS23_TS30                      *((volatile  uint8_t *)(0x424E4538UL))
#define bFM4_ADC2_ADSS23_TS30                     *((volatile  uint8_t *)(0x424E4538UL))
#define bFM_ADC2_ADSS23_TS31                      *((volatile  uint8_t *)(0x424E453CUL))
#define bFM4_ADC2_ADSS23_TS31                     *((volatile  uint8_t *)(0x424E453CUL))

#define bFM_ADC2_CALSR_CLBEN                      *((volatile  uint8_t *)(0x424E4820UL))
#define bFM4_ADC2_CALSR_CLBEN                     *((volatile  uint8_t *)(0x424E4820UL))

#define bFM_ADC2_CMPCR_CMD0                       *((volatile  uint8_t *)(0x424E4494UL))
#define bFM4_ADC2_CMPCR_CMD0                      *((volatile  uint8_t *)(0x424E4494UL))
#define bFM_ADC2_CMPCR_CMD1                       *((volatile  uint8_t *)(0x424E4498UL))
#define bFM4_ADC2_CMPCR_CMD1                      *((volatile  uint8_t *)(0x424E4498UL))
#define bFM_ADC2_CMPCR_CMPEN                      *((volatile  uint8_t *)(0x424E449CUL))
#define bFM4_ADC2_CMPCR_CMPEN                     *((volatile  uint8_t *)(0x424E449CUL))

#define bFM_ADC2_PCCR_PSTR                        *((volatile  uint8_t *)(0x424E4320UL))
#define bFM4_ADC2_PCCR_PSTR                       *((volatile  uint8_t *)(0x424E4320UL))
#define bFM_ADC2_PCCR_PHEN                        *((volatile  uint8_t *)(0x424E4324UL))
#define bFM4_ADC2_PCCR_PHEN                       *((volatile  uint8_t *)(0x424E4324UL))
#define bFM_ADC2_PCCR_PEEN                        *((volatile  uint8_t *)(0x424E4328UL))
#define bFM4_ADC2_PCCR_PEEN                       *((volatile  uint8_t *)(0x424E4328UL))
#define bFM_ADC2_PCCR_ESCE                        *((volatile  uint8_t *)(0x424E432CUL))
#define bFM4_ADC2_PCCR_ESCE                       *((volatile  uint8_t *)(0x424E432CUL))
#define bFM_ADC2_PCCR_PFCLR                       *((volatile  uint8_t *)(0x424E4330UL))
#define bFM4_ADC2_PCCR_PFCLR                      *((volatile  uint8_t *)(0x424E4330UL))
#define bFM_ADC2_PCCR_POVR                        *((volatile  uint8_t *)(0x424E4334UL))
#define bFM4_ADC2_PCCR_POVR                       *((volatile  uint8_t *)(0x424E4334UL))
#define bFM_ADC2_PCCR_PFUL                        *((volatile  uint8_t *)(0x424E4338UL))
#define bFM4_ADC2_PCCR_PFUL                       *((volatile  uint8_t *)(0x424E4338UL))
#define bFM_ADC2_PCCR_PEMP                        *((volatile  uint8_t *)(0x424E433CUL))
#define bFM4_ADC2_PCCR_PEMP                       *((volatile  uint8_t *)(0x424E433CUL))

#define bFM_ADC2_PCFD_INVL                        *((volatile  uint8_t *)(0x424E43B0UL))
#define bFM4_ADC2_PCFD_INVL                       *((volatile  uint8_t *)(0x424E43B0UL))

#define bFM_ADC2_PCFD_FDAS1_INVL                  *((volatile  uint8_t *)(0x424E43B0UL))
#define bFM4_ADC2_PCFD_FDAS1_INVL                 *((volatile  uint8_t *)(0x424E43B0UL))

#define bFM_ADC2_SCCR_SSTR                        *((volatile  uint8_t *)(0x424E4120UL))
#define bFM4_ADC2_SCCR_SSTR                       *((volatile  uint8_t *)(0x424E4120UL))
#define bFM_ADC2_SCCR_SHEN                        *((volatile  uint8_t *)(0x424E4124UL))
#define bFM4_ADC2_SCCR_SHEN                       *((volatile  uint8_t *)(0x424E4124UL))
#define bFM_ADC2_SCCR_RPT                         *((volatile  uint8_t *)(0x424E4128UL))
#define bFM4_ADC2_SCCR_RPT                        *((volatile  uint8_t *)(0x424E4128UL))
#define bFM_ADC2_SCCR_SFCLR                       *((volatile  uint8_t *)(0x424E4130UL))
#define bFM4_ADC2_SCCR_SFCLR                      *((volatile  uint8_t *)(0x424E4130UL))
#define bFM_ADC2_SCCR_SOVR                        *((volatile  uint8_t *)(0x424E4134UL))
#define bFM4_ADC2_SCCR_SOVR                       *((volatile  uint8_t *)(0x424E4134UL))
#define bFM_ADC2_SCCR_SFUL                        *((volatile  uint8_t *)(0x424E4138UL))
#define bFM4_ADC2_SCCR_SFUL                       *((volatile  uint8_t *)(0x424E4138UL))
#define bFM_ADC2_SCCR_SEMP                        *((volatile  uint8_t *)(0x424E413CUL))
#define bFM4_ADC2_SCCR_SEMP                       *((volatile  uint8_t *)(0x424E413CUL))

#define bFM_ADC2_SCFD_INVL                        *((volatile  uint8_t *)(0x424E41B0UL))
#define bFM4_ADC2_SCFD_INVL                       *((volatile  uint8_t *)(0x424E41B0UL))

#define bFM_ADC2_SCFD_FDAS1_INVL                  *((volatile  uint8_t *)(0x424E41B0UL))
#define bFM4_ADC2_SCFD_FDAS1_INVL                 *((volatile  uint8_t *)(0x424E41B0UL))

#define bFM_ADC2_SCIS01_AN0                       *((volatile  uint8_t *)(0x424E4280UL))
#define bFM4_ADC2_SCIS01_AN0                      *((volatile  uint8_t *)(0x424E4280UL))
#define bFM_ADC2_SCIS01_AN1                       *((volatile  uint8_t *)(0x424E4284UL))
#define bFM4_ADC2_SCIS01_AN1                      *((volatile  uint8_t *)(0x424E4284UL))
#define bFM_ADC2_SCIS01_AN2                       *((volatile  uint8_t *)(0x424E4288UL))
#define bFM4_ADC2_SCIS01_AN2                      *((volatile  uint8_t *)(0x424E4288UL))
#define bFM_ADC2_SCIS01_AN3                       *((volatile  uint8_t *)(0x424E428CUL))
#define bFM4_ADC2_SCIS01_AN3                      *((volatile  uint8_t *)(0x424E428CUL))
#define bFM_ADC2_SCIS01_AN4                       *((volatile  uint8_t *)(0x424E4290UL))
#define bFM4_ADC2_SCIS01_AN4                      *((volatile  uint8_t *)(0x424E4290UL))
#define bFM_ADC2_SCIS01_AN5                       *((volatile  uint8_t *)(0x424E4294UL))
#define bFM4_ADC2_SCIS01_AN5                      *((volatile  uint8_t *)(0x424E4294UL))
#define bFM_ADC2_SCIS01_AN6                       *((volatile  uint8_t *)(0x424E4298UL))
#define bFM4_ADC2_SCIS01_AN6                      *((volatile  uint8_t *)(0x424E4298UL))
#define bFM_ADC2_SCIS01_AN7                       *((volatile  uint8_t *)(0x424E429CUL))
#define bFM4_ADC2_SCIS01_AN7                      *((volatile  uint8_t *)(0x424E429CUL))
#define bFM_ADC2_SCIS01_AN8                       *((volatile  uint8_t *)(0x424E42A0UL))
#define bFM4_ADC2_SCIS01_AN8                      *((volatile  uint8_t *)(0x424E42A0UL))
#define bFM_ADC2_SCIS01_AN9                       *((volatile  uint8_t *)(0x424E42A4UL))
#define bFM4_ADC2_SCIS01_AN9                      *((volatile  uint8_t *)(0x424E42A4UL))
#define bFM_ADC2_SCIS01_AN10                      *((volatile  uint8_t *)(0x424E42A8UL))
#define bFM4_ADC2_SCIS01_AN10                     *((volatile  uint8_t *)(0x424E42A8UL))
#define bFM_ADC2_SCIS01_AN11                      *((volatile  uint8_t *)(0x424E42ACUL))
#define bFM4_ADC2_SCIS01_AN11                     *((volatile  uint8_t *)(0x424E42ACUL))
#define bFM_ADC2_SCIS01_AN12                      *((volatile  uint8_t *)(0x424E42B0UL))
#define bFM4_ADC2_SCIS01_AN12                     *((volatile  uint8_t *)(0x424E42B0UL))
#define bFM_ADC2_SCIS01_AN13                      *((volatile  uint8_t *)(0x424E42B4UL))
#define bFM4_ADC2_SCIS01_AN13                     *((volatile  uint8_t *)(0x424E42B4UL))
#define bFM_ADC2_SCIS01_AN14                      *((volatile  uint8_t *)(0x424E42B8UL))
#define bFM4_ADC2_SCIS01_AN14                     *((volatile  uint8_t *)(0x424E42B8UL))
#define bFM_ADC2_SCIS01_AN15                      *((volatile  uint8_t *)(0x424E42BCUL))
#define bFM4_ADC2_SCIS01_AN15                     *((volatile  uint8_t *)(0x424E42BCUL))

#define bFM_ADC2_SCIS23_AN16                      *((volatile  uint8_t *)(0x424E4200UL))
#define bFM4_ADC2_SCIS23_AN16                     *((volatile  uint8_t *)(0x424E4200UL))
#define bFM_ADC2_SCIS23_AN17                      *((volatile  uint8_t *)(0x424E4204UL))
#define bFM4_ADC2_SCIS23_AN17                     *((volatile  uint8_t *)(0x424E4204UL))
#define bFM_ADC2_SCIS23_AN18                      *((volatile  uint8_t *)(0x424E4208UL))
#define bFM4_ADC2_SCIS23_AN18                     *((volatile  uint8_t *)(0x424E4208UL))
#define bFM_ADC2_SCIS23_AN19                      *((volatile  uint8_t *)(0x424E420CUL))
#define bFM4_ADC2_SCIS23_AN19                     *((volatile  uint8_t *)(0x424E420CUL))
#define bFM_ADC2_SCIS23_AN20                      *((volatile  uint8_t *)(0x424E4210UL))
#define bFM4_ADC2_SCIS23_AN20                     *((volatile  uint8_t *)(0x424E4210UL))
#define bFM_ADC2_SCIS23_AN21                      *((volatile  uint8_t *)(0x424E4214UL))
#define bFM4_ADC2_SCIS23_AN21                     *((volatile  uint8_t *)(0x424E4214UL))
#define bFM_ADC2_SCIS23_AN22                      *((volatile  uint8_t *)(0x424E4218UL))
#define bFM4_ADC2_SCIS23_AN22                     *((volatile  uint8_t *)(0x424E4218UL))
#define bFM_ADC2_SCIS23_AN23                      *((volatile  uint8_t *)(0x424E421CUL))
#define bFM4_ADC2_SCIS23_AN23                     *((volatile  uint8_t *)(0x424E421CUL))
#define bFM_ADC2_SCIS23_AN24                      *((volatile  uint8_t *)(0x424E4220UL))
#define bFM4_ADC2_SCIS23_AN24                     *((volatile  uint8_t *)(0x424E4220UL))
#define bFM_ADC2_SCIS23_AN25                      *((volatile  uint8_t *)(0x424E4224UL))
#define bFM4_ADC2_SCIS23_AN25                     *((volatile  uint8_t *)(0x424E4224UL))
#define bFM_ADC2_SCIS23_AN26                      *((volatile  uint8_t *)(0x424E4228UL))
#define bFM4_ADC2_SCIS23_AN26                     *((volatile  uint8_t *)(0x424E4228UL))
#define bFM_ADC2_SCIS23_AN27                      *((volatile  uint8_t *)(0x424E422CUL))
#define bFM4_ADC2_SCIS23_AN27                     *((volatile  uint8_t *)(0x424E422CUL))
#define bFM_ADC2_SCIS23_AN28                      *((volatile  uint8_t *)(0x424E4230UL))
#define bFM4_ADC2_SCIS23_AN28                     *((volatile  uint8_t *)(0x424E4230UL))
#define bFM_ADC2_SCIS23_AN29                      *((volatile  uint8_t *)(0x424E4234UL))
#define bFM4_ADC2_SCIS23_AN29                     *((volatile  uint8_t *)(0x424E4234UL))
#define bFM_ADC2_SCIS23_AN30                      *((volatile  uint8_t *)(0x424E4238UL))
#define bFM4_ADC2_SCIS23_AN30                     *((volatile  uint8_t *)(0x424E4238UL))
#define bFM_ADC2_SCIS23_AN31                      *((volatile  uint8_t *)(0x424E423CUL))
#define bFM4_ADC2_SCIS23_AN31                     *((volatile  uint8_t *)(0x424E423CUL))

#define bFM_ADC2_WCMPCR_RCOE                      *((volatile  uint8_t *)(0x424E4988UL))
#define bFM4_ADC2_WCMPCR_RCOE                     *((volatile  uint8_t *)(0x424E4988UL))
#define bFM_ADC2_WCMPCR_RCOIE                     *((volatile  uint8_t *)(0x424E498CUL))
#define bFM4_ADC2_WCMPCR_RCOIE                    *((volatile  uint8_t *)(0x424E498CUL))
#define bFM_ADC2_WCMPCR_RCOIRS                    *((volatile  uint8_t *)(0x424E4990UL))
#define bFM4_ADC2_WCMPCR_RCOIRS                   *((volatile  uint8_t *)(0x424E4990UL))

#define bFM_ADC2_WCMPSR_WCMD                      *((volatile  uint8_t *)(0x424E49B4UL))
#define bFM4_ADC2_WCMPSR_WCMD                     *((volatile  uint8_t *)(0x424E49B4UL))

#define bFM_ADC2_WCMRCIF_RCINT                    *((volatile  uint8_t *)(0x424E4900UL))
#define bFM4_ADC2_WCMRCIF_RCINT                   *((volatile  uint8_t *)(0x424E4900UL))

#define bFM_ADC2_WCMRCOT_RCOOF                    *((volatile  uint8_t *)(0x424E4880UL))
#define bFM4_ADC2_WCMRCOT_RCOOF                   *((volatile  uint8_t *)(0x424E4880UL))


/*******************************************************************************
* BT Registers BT0
*   Bitband Section
*******************************************************************************/
#define bFM_BT0_PPG_STC_UDIR                      *((volatile  uint8_t *)(0x424A0200UL))
#define bFM4_BT0_PPG_STC_UDIR                     *((volatile  uint8_t *)(0x424A0200UL))
#define bFM_BT0_PPG_STC_TGIR                      *((volatile  uint8_t *)(0x424A0208UL))
#define bFM4_BT0_PPG_STC_TGIR                     *((volatile  uint8_t *)(0x424A0208UL))
#define bFM_BT0_PPG_STC_UDIE                      *((volatile  uint8_t *)(0x424A0210UL))
#define bFM4_BT0_PPG_STC_UDIE                     *((volatile  uint8_t *)(0x424A0210UL))
#define bFM_BT0_PPG_STC_TGIE                      *((volatile  uint8_t *)(0x424A0218UL))
#define bFM4_BT0_PPG_STC_TGIE                     *((volatile  uint8_t *)(0x424A0218UL))

#define bFM_BT0_PPG_TMCR_STRG                     *((volatile  uint8_t *)(0x424A0180UL))
#define bFM4_BT0_PPG_TMCR_STRG                    *((volatile  uint8_t *)(0x424A0180UL))
#define bFM_BT0_PPG_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A0184UL))
#define bFM4_BT0_PPG_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A0184UL))
#define bFM_BT0_PPG_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A0188UL))
#define bFM4_BT0_PPG_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A0188UL))
#define bFM_BT0_PPG_TMCR_OSEL                     *((volatile  uint8_t *)(0x424A018CUL))
#define bFM4_BT0_PPG_TMCR_OSEL                    *((volatile  uint8_t *)(0x424A018CUL))
#define bFM_BT0_PPG_TMCR_PMSK                     *((volatile  uint8_t *)(0x424A01A8UL))
#define bFM4_BT0_PPG_TMCR_PMSK                    *((volatile  uint8_t *)(0x424A01A8UL))
#define bFM_BT0_PPG_TMCR_RTGEN                    *((volatile  uint8_t *)(0x424A01ACUL))
#define bFM4_BT0_PPG_TMCR_RTGEN                   *((volatile  uint8_t *)(0x424A01ACUL))

#define bFM_BT0_PPG_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A0220UL))
#define bFM4_BT0_PPG_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A0220UL))

#define bFM_BT0_PWC_STC_OVIR                      *((volatile  uint8_t *)(0x424A0200UL))
#define bFM4_BT0_PWC_STC_OVIR                     *((volatile  uint8_t *)(0x424A0200UL))
#define bFM_BT0_PWC_STC_EDIR                      *((volatile  uint8_t *)(0x424A0208UL))
#define bFM4_BT0_PWC_STC_EDIR                     *((volatile  uint8_t *)(0x424A0208UL))
#define bFM_BT0_PWC_STC_OVIE                      *((volatile  uint8_t *)(0x424A0210UL))
#define bFM4_BT0_PWC_STC_OVIE                     *((volatile  uint8_t *)(0x424A0210UL))
#define bFM_BT0_PWC_STC_EDIE                      *((volatile  uint8_t *)(0x424A0218UL))
#define bFM4_BT0_PWC_STC_EDIE                     *((volatile  uint8_t *)(0x424A0218UL))
#define bFM_BT0_PWC_STC_ERR                       *((volatile  uint8_t *)(0x424A021CUL))
#define bFM4_BT0_PWC_STC_ERR                      *((volatile  uint8_t *)(0x424A021CUL))

#define bFM_BT0_PWC_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A0184UL))
#define bFM4_BT0_PWC_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A0184UL))
#define bFM_BT0_PWC_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A0188UL))
#define bFM4_BT0_PWC_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A0188UL))
#define bFM_BT0_PWC_TMCR_T32                      *((volatile  uint8_t *)(0x424A019CUL))
#define bFM4_BT0_PWC_TMCR_T32                     *((volatile  uint8_t *)(0x424A019CUL))

#define bFM_BT0_PWC_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A0220UL))
#define bFM4_BT0_PWC_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A0220UL))

#define bFM_BT0_PWM_STC_UDIR                      *((volatile  uint8_t *)(0x424A0200UL))
#define bFM4_BT0_PWM_STC_UDIR                     *((volatile  uint8_t *)(0x424A0200UL))
#define bFM_BT0_PWM_STC_DTIR                      *((volatile  uint8_t *)(0x424A0204UL))
#define bFM4_BT0_PWM_STC_DTIR                     *((volatile  uint8_t *)(0x424A0204UL))
#define bFM_BT0_PWM_STC_TGIR                      *((volatile  uint8_t *)(0x424A0208UL))
#define bFM4_BT0_PWM_STC_TGIR                     *((volatile  uint8_t *)(0x424A0208UL))
#define bFM_BT0_PWM_STC_UDIE                      *((volatile  uint8_t *)(0x424A0210UL))
#define bFM4_BT0_PWM_STC_UDIE                     *((volatile  uint8_t *)(0x424A0210UL))
#define bFM_BT0_PWM_STC_DTIE                      *((volatile  uint8_t *)(0x424A0214UL))
#define bFM4_BT0_PWM_STC_DTIE                     *((volatile  uint8_t *)(0x424A0214UL))
#define bFM_BT0_PWM_STC_TGIE                      *((volatile  uint8_t *)(0x424A0218UL))
#define bFM4_BT0_PWM_STC_TGIE                     *((volatile  uint8_t *)(0x424A0218UL))

#define bFM_BT0_PWM_TMCR_STRG                     *((volatile  uint8_t *)(0x424A0180UL))
#define bFM4_BT0_PWM_TMCR_STRG                    *((volatile  uint8_t *)(0x424A0180UL))
#define bFM_BT0_PWM_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A0184UL))
#define bFM4_BT0_PWM_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A0184UL))
#define bFM_BT0_PWM_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A0188UL))
#define bFM4_BT0_PWM_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A0188UL))
#define bFM_BT0_PWM_TMCR_OSEL                     *((volatile  uint8_t *)(0x424A018CUL))
#define bFM4_BT0_PWM_TMCR_OSEL                    *((volatile  uint8_t *)(0x424A018CUL))
#define bFM_BT0_PWM_TMCR_PMSK                     *((volatile  uint8_t *)(0x424A01A8UL))
#define bFM4_BT0_PWM_TMCR_PMSK                    *((volatile  uint8_t *)(0x424A01A8UL))
#define bFM_BT0_PWM_TMCR_RTGEN                    *((volatile  uint8_t *)(0x424A01ACUL))
#define bFM4_BT0_PWM_TMCR_RTGEN                   *((volatile  uint8_t *)(0x424A01ACUL))

#define bFM_BT0_PWM_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A0220UL))
#define bFM4_BT0_PWM_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A0220UL))

#define bFM_BT0_RT_STC_UDIR                       *((volatile  uint8_t *)(0x424A0200UL))
#define bFM4_BT0_RT_STC_UDIR                      *((volatile  uint8_t *)(0x424A0200UL))
#define bFM_BT0_RT_STC_TGIR                       *((volatile  uint8_t *)(0x424A0208UL))
#define bFM4_BT0_RT_STC_TGIR                      *((volatile  uint8_t *)(0x424A0208UL))
#define bFM_BT0_RT_STC_UDIE                       *((volatile  uint8_t *)(0x424A0210UL))
#define bFM4_BT0_RT_STC_UDIE                      *((volatile  uint8_t *)(0x424A0210UL))
#define bFM_BT0_RT_STC_TGIE                       *((volatile  uint8_t *)(0x424A0218UL))
#define bFM4_BT0_RT_STC_TGIE                      *((volatile  uint8_t *)(0x424A0218UL))

#define bFM_BT0_RT_TMCR_STRG                      *((volatile  uint8_t *)(0x424A0180UL))
#define bFM4_BT0_RT_TMCR_STRG                     *((volatile  uint8_t *)(0x424A0180UL))
#define bFM_BT0_RT_TMCR_CTEN                      *((volatile  uint8_t *)(0x424A0184UL))
#define bFM4_BT0_RT_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A0184UL))
#define bFM_BT0_RT_TMCR_MDSE                      *((volatile  uint8_t *)(0x424A0188UL))
#define bFM4_BT0_RT_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A0188UL))
#define bFM_BT0_RT_TMCR_OSEL                      *((volatile  uint8_t *)(0x424A018CUL))
#define bFM4_BT0_RT_TMCR_OSEL                     *((volatile  uint8_t *)(0x424A018CUL))
#define bFM_BT0_RT_TMCR_T32                       *((volatile  uint8_t *)(0x424A019CUL))
#define bFM4_BT0_RT_TMCR_T32                      *((volatile  uint8_t *)(0x424A019CUL))

#define bFM_BT0_RT_TMCR2_CKS3                     *((volatile  uint8_t *)(0x424A0220UL))
#define bFM4_BT0_RT_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A0220UL))
#define bFM_BT0_RT_TMCR2_GATE                     *((volatile  uint8_t *)(0x424A023CUL))
#define bFM4_BT0_RT_TMCR2_GATE                    *((volatile  uint8_t *)(0x424A023CUL))


/*******************************************************************************
* BT Registers BT1
*   Bitband Section
*******************************************************************************/
#define bFM_BT1_PPG_STC_UDIR                      *((volatile  uint8_t *)(0x424A0A00UL))
#define bFM4_BT1_PPG_STC_UDIR                     *((volatile  uint8_t *)(0x424A0A00UL))
#define bFM_BT1_PPG_STC_TGIR                      *((volatile  uint8_t *)(0x424A0A08UL))
#define bFM4_BT1_PPG_STC_TGIR                     *((volatile  uint8_t *)(0x424A0A08UL))
#define bFM_BT1_PPG_STC_UDIE                      *((volatile  uint8_t *)(0x424A0A10UL))
#define bFM4_BT1_PPG_STC_UDIE                     *((volatile  uint8_t *)(0x424A0A10UL))
#define bFM_BT1_PPG_STC_TGIE                      *((volatile  uint8_t *)(0x424A0A18UL))
#define bFM4_BT1_PPG_STC_TGIE                     *((volatile  uint8_t *)(0x424A0A18UL))

#define bFM_BT1_PPG_TMCR_STRG                     *((volatile  uint8_t *)(0x424A0980UL))
#define bFM4_BT1_PPG_TMCR_STRG                    *((volatile  uint8_t *)(0x424A0980UL))
#define bFM_BT1_PPG_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A0984UL))
#define bFM4_BT1_PPG_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A0984UL))
#define bFM_BT1_PPG_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A0988UL))
#define bFM4_BT1_PPG_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A0988UL))
#define bFM_BT1_PPG_TMCR_OSEL                     *((volatile  uint8_t *)(0x424A098CUL))
#define bFM4_BT1_PPG_TMCR_OSEL                    *((volatile  uint8_t *)(0x424A098CUL))
#define bFM_BT1_PPG_TMCR_PMSK                     *((volatile  uint8_t *)(0x424A09A8UL))
#define bFM4_BT1_PPG_TMCR_PMSK                    *((volatile  uint8_t *)(0x424A09A8UL))
#define bFM_BT1_PPG_TMCR_RTGEN                    *((volatile  uint8_t *)(0x424A09ACUL))
#define bFM4_BT1_PPG_TMCR_RTGEN                   *((volatile  uint8_t *)(0x424A09ACUL))

#define bFM_BT1_PPG_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A0A20UL))
#define bFM4_BT1_PPG_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A0A20UL))

#define bFM_BT1_PWC_STC_OVIR                      *((volatile  uint8_t *)(0x424A0A00UL))
#define bFM4_BT1_PWC_STC_OVIR                     *((volatile  uint8_t *)(0x424A0A00UL))
#define bFM_BT1_PWC_STC_EDIR                      *((volatile  uint8_t *)(0x424A0A08UL))
#define bFM4_BT1_PWC_STC_EDIR                     *((volatile  uint8_t *)(0x424A0A08UL))
#define bFM_BT1_PWC_STC_OVIE                      *((volatile  uint8_t *)(0x424A0A10UL))
#define bFM4_BT1_PWC_STC_OVIE                     *((volatile  uint8_t *)(0x424A0A10UL))
#define bFM_BT1_PWC_STC_EDIE                      *((volatile  uint8_t *)(0x424A0A18UL))
#define bFM4_BT1_PWC_STC_EDIE                     *((volatile  uint8_t *)(0x424A0A18UL))
#define bFM_BT1_PWC_STC_ERR                       *((volatile  uint8_t *)(0x424A0A1CUL))
#define bFM4_BT1_PWC_STC_ERR                      *((volatile  uint8_t *)(0x424A0A1CUL))

#define bFM_BT1_PWC_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A0984UL))
#define bFM4_BT1_PWC_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A0984UL))
#define bFM_BT1_PWC_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A0988UL))
#define bFM4_BT1_PWC_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A0988UL))
#define bFM_BT1_PWC_TMCR_T32                      *((volatile  uint8_t *)(0x424A099CUL))
#define bFM4_BT1_PWC_TMCR_T32                     *((volatile  uint8_t *)(0x424A099CUL))

#define bFM_BT1_PWC_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A0A20UL))
#define bFM4_BT1_PWC_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A0A20UL))

#define bFM_BT1_PWM_STC_UDIR                      *((volatile  uint8_t *)(0x424A0A00UL))
#define bFM4_BT1_PWM_STC_UDIR                     *((volatile  uint8_t *)(0x424A0A00UL))
#define bFM_BT1_PWM_STC_DTIR                      *((volatile  uint8_t *)(0x424A0A04UL))
#define bFM4_BT1_PWM_STC_DTIR                     *((volatile  uint8_t *)(0x424A0A04UL))
#define bFM_BT1_PWM_STC_TGIR                      *((volatile  uint8_t *)(0x424A0A08UL))
#define bFM4_BT1_PWM_STC_TGIR                     *((volatile  uint8_t *)(0x424A0A08UL))
#define bFM_BT1_PWM_STC_UDIE                      *((volatile  uint8_t *)(0x424A0A10UL))
#define bFM4_BT1_PWM_STC_UDIE                     *((volatile  uint8_t *)(0x424A0A10UL))
#define bFM_BT1_PWM_STC_DTIE                      *((volatile  uint8_t *)(0x424A0A14UL))
#define bFM4_BT1_PWM_STC_DTIE                     *((volatile  uint8_t *)(0x424A0A14UL))
#define bFM_BT1_PWM_STC_TGIE                      *((volatile  uint8_t *)(0x424A0A18UL))
#define bFM4_BT1_PWM_STC_TGIE                     *((volatile  uint8_t *)(0x424A0A18UL))

#define bFM_BT1_PWM_TMCR_STRG                     *((volatile  uint8_t *)(0x424A0980UL))
#define bFM4_BT1_PWM_TMCR_STRG                    *((volatile  uint8_t *)(0x424A0980UL))
#define bFM_BT1_PWM_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A0984UL))
#define bFM4_BT1_PWM_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A0984UL))
#define bFM_BT1_PWM_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A0988UL))
#define bFM4_BT1_PWM_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A0988UL))
#define bFM_BT1_PWM_TMCR_OSEL                     *((volatile  uint8_t *)(0x424A098CUL))
#define bFM4_BT1_PWM_TMCR_OSEL                    *((volatile  uint8_t *)(0x424A098CUL))
#define bFM_BT1_PWM_TMCR_PMSK                     *((volatile  uint8_t *)(0x424A09A8UL))
#define bFM4_BT1_PWM_TMCR_PMSK                    *((volatile  uint8_t *)(0x424A09A8UL))
#define bFM_BT1_PWM_TMCR_RTGEN                    *((volatile  uint8_t *)(0x424A09ACUL))
#define bFM4_BT1_PWM_TMCR_RTGEN                   *((volatile  uint8_t *)(0x424A09ACUL))

#define bFM_BT1_PWM_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A0A20UL))
#define bFM4_BT1_PWM_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A0A20UL))

#define bFM_BT1_RT_STC_UDIR                       *((volatile  uint8_t *)(0x424A0A00UL))
#define bFM4_BT1_RT_STC_UDIR                      *((volatile  uint8_t *)(0x424A0A00UL))
#define bFM_BT1_RT_STC_TGIR                       *((volatile  uint8_t *)(0x424A0A08UL))
#define bFM4_BT1_RT_STC_TGIR                      *((volatile  uint8_t *)(0x424A0A08UL))
#define bFM_BT1_RT_STC_UDIE                       *((volatile  uint8_t *)(0x424A0A10UL))
#define bFM4_BT1_RT_STC_UDIE                      *((volatile  uint8_t *)(0x424A0A10UL))
#define bFM_BT1_RT_STC_TGIE                       *((volatile  uint8_t *)(0x424A0A18UL))
#define bFM4_BT1_RT_STC_TGIE                      *((volatile  uint8_t *)(0x424A0A18UL))

#define bFM_BT1_RT_TMCR_STRG                      *((volatile  uint8_t *)(0x424A0980UL))
#define bFM4_BT1_RT_TMCR_STRG                     *((volatile  uint8_t *)(0x424A0980UL))
#define bFM_BT1_RT_TMCR_CTEN                      *((volatile  uint8_t *)(0x424A0984UL))
#define bFM4_BT1_RT_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A0984UL))
#define bFM_BT1_RT_TMCR_MDSE                      *((volatile  uint8_t *)(0x424A0988UL))
#define bFM4_BT1_RT_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A0988UL))
#define bFM_BT1_RT_TMCR_OSEL                      *((volatile  uint8_t *)(0x424A098CUL))
#define bFM4_BT1_RT_TMCR_OSEL                     *((volatile  uint8_t *)(0x424A098CUL))
#define bFM_BT1_RT_TMCR_T32                       *((volatile  uint8_t *)(0x424A099CUL))
#define bFM4_BT1_RT_TMCR_T32                      *((volatile  uint8_t *)(0x424A099CUL))

#define bFM_BT1_RT_TMCR2_CKS3                     *((volatile  uint8_t *)(0x424A0A20UL))
#define bFM4_BT1_RT_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A0A20UL))
#define bFM_BT1_RT_TMCR2_GATE                     *((volatile  uint8_t *)(0x424A0A3CUL))
#define bFM4_BT1_RT_TMCR2_GATE                    *((volatile  uint8_t *)(0x424A0A3CUL))


/*******************************************************************************
* BT Registers BT10
*   Bitband Section
*******************************************************************************/
#define bFM_BT10_PPG_STC_UDIR                     *((volatile  uint8_t *)(0x424A9200UL))
#define bFM4_BT10_PPG_STC_UDIR                    *((volatile  uint8_t *)(0x424A9200UL))
#define bFM_BT10_PPG_STC_TGIR                     *((volatile  uint8_t *)(0x424A9208UL))
#define bFM4_BT10_PPG_STC_TGIR                    *((volatile  uint8_t *)(0x424A9208UL))
#define bFM_BT10_PPG_STC_UDIE                     *((volatile  uint8_t *)(0x424A9210UL))
#define bFM4_BT10_PPG_STC_UDIE                    *((volatile  uint8_t *)(0x424A9210UL))
#define bFM_BT10_PPG_STC_TGIE                     *((volatile  uint8_t *)(0x424A9218UL))
#define bFM4_BT10_PPG_STC_TGIE                    *((volatile  uint8_t *)(0x424A9218UL))

#define bFM_BT10_PPG_TMCR_STRG                    *((volatile  uint8_t *)(0x424A9180UL))
#define bFM4_BT10_PPG_TMCR_STRG                   *((volatile  uint8_t *)(0x424A9180UL))
#define bFM_BT10_PPG_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A9184UL))
#define bFM4_BT10_PPG_TMCR_CTEN                   *((volatile  uint8_t *)(0x424A9184UL))
#define bFM_BT10_PPG_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A9188UL))
#define bFM4_BT10_PPG_TMCR_MDSE                   *((volatile  uint8_t *)(0x424A9188UL))
#define bFM_BT10_PPG_TMCR_OSEL                    *((volatile  uint8_t *)(0x424A918CUL))
#define bFM4_BT10_PPG_TMCR_OSEL                   *((volatile  uint8_t *)(0x424A918CUL))
#define bFM_BT10_PPG_TMCR_PMSK                    *((volatile  uint8_t *)(0x424A91A8UL))
#define bFM4_BT10_PPG_TMCR_PMSK                   *((volatile  uint8_t *)(0x424A91A8UL))
#define bFM_BT10_PPG_TMCR_RTGEN                   *((volatile  uint8_t *)(0x424A91ACUL))
#define bFM4_BT10_PPG_TMCR_RTGEN                  *((volatile  uint8_t *)(0x424A91ACUL))

#define bFM_BT10_PPG_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A9220UL))
#define bFM4_BT10_PPG_TMCR2_CKS3                  *((volatile  uint8_t *)(0x424A9220UL))

#define bFM_BT10_PWC_STC_OVIR                     *((volatile  uint8_t *)(0x424A9200UL))
#define bFM4_BT10_PWC_STC_OVIR                    *((volatile  uint8_t *)(0x424A9200UL))
#define bFM_BT10_PWC_STC_EDIR                     *((volatile  uint8_t *)(0x424A9208UL))
#define bFM4_BT10_PWC_STC_EDIR                    *((volatile  uint8_t *)(0x424A9208UL))
#define bFM_BT10_PWC_STC_OVIE                     *((volatile  uint8_t *)(0x424A9210UL))
#define bFM4_BT10_PWC_STC_OVIE                    *((volatile  uint8_t *)(0x424A9210UL))
#define bFM_BT10_PWC_STC_EDIE                     *((volatile  uint8_t *)(0x424A9218UL))
#define bFM4_BT10_PWC_STC_EDIE                    *((volatile  uint8_t *)(0x424A9218UL))
#define bFM_BT10_PWC_STC_ERR                      *((volatile  uint8_t *)(0x424A921CUL))
#define bFM4_BT10_PWC_STC_ERR                     *((volatile  uint8_t *)(0x424A921CUL))

#define bFM_BT10_PWC_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A9184UL))
#define bFM4_BT10_PWC_TMCR_CTEN                   *((volatile  uint8_t *)(0x424A9184UL))
#define bFM_BT10_PWC_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A9188UL))
#define bFM4_BT10_PWC_TMCR_MDSE                   *((volatile  uint8_t *)(0x424A9188UL))
#define bFM_BT10_PWC_TMCR_T32                     *((volatile  uint8_t *)(0x424A919CUL))
#define bFM4_BT10_PWC_TMCR_T32                    *((volatile  uint8_t *)(0x424A919CUL))

#define bFM_BT10_PWC_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A9220UL))
#define bFM4_BT10_PWC_TMCR2_CKS3                  *((volatile  uint8_t *)(0x424A9220UL))

#define bFM_BT10_PWM_STC_UDIR                     *((volatile  uint8_t *)(0x424A9200UL))
#define bFM4_BT10_PWM_STC_UDIR                    *((volatile  uint8_t *)(0x424A9200UL))
#define bFM_BT10_PWM_STC_DTIR                     *((volatile  uint8_t *)(0x424A9204UL))
#define bFM4_BT10_PWM_STC_DTIR                    *((volatile  uint8_t *)(0x424A9204UL))
#define bFM_BT10_PWM_STC_TGIR                     *((volatile  uint8_t *)(0x424A9208UL))
#define bFM4_BT10_PWM_STC_TGIR                    *((volatile  uint8_t *)(0x424A9208UL))
#define bFM_BT10_PWM_STC_UDIE                     *((volatile  uint8_t *)(0x424A9210UL))
#define bFM4_BT10_PWM_STC_UDIE                    *((volatile  uint8_t *)(0x424A9210UL))
#define bFM_BT10_PWM_STC_DTIE                     *((volatile  uint8_t *)(0x424A9214UL))
#define bFM4_BT10_PWM_STC_DTIE                    *((volatile  uint8_t *)(0x424A9214UL))
#define bFM_BT10_PWM_STC_TGIE                     *((volatile  uint8_t *)(0x424A9218UL))
#define bFM4_BT10_PWM_STC_TGIE                    *((volatile  uint8_t *)(0x424A9218UL))

#define bFM_BT10_PWM_TMCR_STRG                    *((volatile  uint8_t *)(0x424A9180UL))
#define bFM4_BT10_PWM_TMCR_STRG                   *((volatile  uint8_t *)(0x424A9180UL))
#define bFM_BT10_PWM_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A9184UL))
#define bFM4_BT10_PWM_TMCR_CTEN                   *((volatile  uint8_t *)(0x424A9184UL))
#define bFM_BT10_PWM_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A9188UL))
#define bFM4_BT10_PWM_TMCR_MDSE                   *((volatile  uint8_t *)(0x424A9188UL))
#define bFM_BT10_PWM_TMCR_OSEL                    *((volatile  uint8_t *)(0x424A918CUL))
#define bFM4_BT10_PWM_TMCR_OSEL                   *((volatile  uint8_t *)(0x424A918CUL))
#define bFM_BT10_PWM_TMCR_PMSK                    *((volatile  uint8_t *)(0x424A91A8UL))
#define bFM4_BT10_PWM_TMCR_PMSK                   *((volatile  uint8_t *)(0x424A91A8UL))
#define bFM_BT10_PWM_TMCR_RTGEN                   *((volatile  uint8_t *)(0x424A91ACUL))
#define bFM4_BT10_PWM_TMCR_RTGEN                  *((volatile  uint8_t *)(0x424A91ACUL))

#define bFM_BT10_PWM_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A9220UL))
#define bFM4_BT10_PWM_TMCR2_CKS3                  *((volatile  uint8_t *)(0x424A9220UL))

#define bFM_BT10_RT_STC_UDIR                      *((volatile  uint8_t *)(0x424A9200UL))
#define bFM4_BT10_RT_STC_UDIR                     *((volatile  uint8_t *)(0x424A9200UL))
#define bFM_BT10_RT_STC_TGIR                      *((volatile  uint8_t *)(0x424A9208UL))
#define bFM4_BT10_RT_STC_TGIR                     *((volatile  uint8_t *)(0x424A9208UL))
#define bFM_BT10_RT_STC_UDIE                      *((volatile  uint8_t *)(0x424A9210UL))
#define bFM4_BT10_RT_STC_UDIE                     *((volatile  uint8_t *)(0x424A9210UL))
#define bFM_BT10_RT_STC_TGIE                      *((volatile  uint8_t *)(0x424A9218UL))
#define bFM4_BT10_RT_STC_TGIE                     *((volatile  uint8_t *)(0x424A9218UL))

#define bFM_BT10_RT_TMCR_STRG                     *((volatile  uint8_t *)(0x424A9180UL))
#define bFM4_BT10_RT_TMCR_STRG                    *((volatile  uint8_t *)(0x424A9180UL))
#define bFM_BT10_RT_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A9184UL))
#define bFM4_BT10_RT_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A9184UL))
#define bFM_BT10_RT_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A9188UL))
#define bFM4_BT10_RT_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A9188UL))
#define bFM_BT10_RT_TMCR_OSEL                     *((volatile  uint8_t *)(0x424A918CUL))
#define bFM4_BT10_RT_TMCR_OSEL                    *((volatile  uint8_t *)(0x424A918CUL))
#define bFM_BT10_RT_TMCR_T32                      *((volatile  uint8_t *)(0x424A919CUL))
#define bFM4_BT10_RT_TMCR_T32                     *((volatile  uint8_t *)(0x424A919CUL))

#define bFM_BT10_RT_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A9220UL))
#define bFM4_BT10_RT_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A9220UL))
#define bFM_BT10_RT_TMCR2_GATE                    *((volatile  uint8_t *)(0x424A923CUL))
#define bFM4_BT10_RT_TMCR2_GATE                   *((volatile  uint8_t *)(0x424A923CUL))


/*******************************************************************************
* BT Registers BT11
*   Bitband Section
*******************************************************************************/
#define bFM_BT11_PPG_STC_UDIR                     *((volatile  uint8_t *)(0x424A9A00UL))
#define bFM4_BT11_PPG_STC_UDIR                    *((volatile  uint8_t *)(0x424A9A00UL))
#define bFM_BT11_PPG_STC_TGIR                     *((volatile  uint8_t *)(0x424A9A08UL))
#define bFM4_BT11_PPG_STC_TGIR                    *((volatile  uint8_t *)(0x424A9A08UL))
#define bFM_BT11_PPG_STC_UDIE                     *((volatile  uint8_t *)(0x424A9A10UL))
#define bFM4_BT11_PPG_STC_UDIE                    *((volatile  uint8_t *)(0x424A9A10UL))
#define bFM_BT11_PPG_STC_TGIE                     *((volatile  uint8_t *)(0x424A9A18UL))
#define bFM4_BT11_PPG_STC_TGIE                    *((volatile  uint8_t *)(0x424A9A18UL))

#define bFM_BT11_PPG_TMCR_STRG                    *((volatile  uint8_t *)(0x424A9980UL))
#define bFM4_BT11_PPG_TMCR_STRG                   *((volatile  uint8_t *)(0x424A9980UL))
#define bFM_BT11_PPG_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A9984UL))
#define bFM4_BT11_PPG_TMCR_CTEN                   *((volatile  uint8_t *)(0x424A9984UL))
#define bFM_BT11_PPG_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A9988UL))
#define bFM4_BT11_PPG_TMCR_MDSE                   *((volatile  uint8_t *)(0x424A9988UL))
#define bFM_BT11_PPG_TMCR_OSEL                    *((volatile  uint8_t *)(0x424A998CUL))
#define bFM4_BT11_PPG_TMCR_OSEL                   *((volatile  uint8_t *)(0x424A998CUL))
#define bFM_BT11_PPG_TMCR_PMSK                    *((volatile  uint8_t *)(0x424A99A8UL))
#define bFM4_BT11_PPG_TMCR_PMSK                   *((volatile  uint8_t *)(0x424A99A8UL))
#define bFM_BT11_PPG_TMCR_RTGEN                   *((volatile  uint8_t *)(0x424A99ACUL))
#define bFM4_BT11_PPG_TMCR_RTGEN                  *((volatile  uint8_t *)(0x424A99ACUL))

#define bFM_BT11_PPG_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A9A20UL))
#define bFM4_BT11_PPG_TMCR2_CKS3                  *((volatile  uint8_t *)(0x424A9A20UL))

#define bFM_BT11_PWC_STC_OVIR                     *((volatile  uint8_t *)(0x424A9A00UL))
#define bFM4_BT11_PWC_STC_OVIR                    *((volatile  uint8_t *)(0x424A9A00UL))
#define bFM_BT11_PWC_STC_EDIR                     *((volatile  uint8_t *)(0x424A9A08UL))
#define bFM4_BT11_PWC_STC_EDIR                    *((volatile  uint8_t *)(0x424A9A08UL))
#define bFM_BT11_PWC_STC_OVIE                     *((volatile  uint8_t *)(0x424A9A10UL))
#define bFM4_BT11_PWC_STC_OVIE                    *((volatile  uint8_t *)(0x424A9A10UL))
#define bFM_BT11_PWC_STC_EDIE                     *((volatile  uint8_t *)(0x424A9A18UL))
#define bFM4_BT11_PWC_STC_EDIE                    *((volatile  uint8_t *)(0x424A9A18UL))
#define bFM_BT11_PWC_STC_ERR                      *((volatile  uint8_t *)(0x424A9A1CUL))
#define bFM4_BT11_PWC_STC_ERR                     *((volatile  uint8_t *)(0x424A9A1CUL))

#define bFM_BT11_PWC_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A9984UL))
#define bFM4_BT11_PWC_TMCR_CTEN                   *((volatile  uint8_t *)(0x424A9984UL))
#define bFM_BT11_PWC_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A9988UL))
#define bFM4_BT11_PWC_TMCR_MDSE                   *((volatile  uint8_t *)(0x424A9988UL))
#define bFM_BT11_PWC_TMCR_T32                     *((volatile  uint8_t *)(0x424A999CUL))
#define bFM4_BT11_PWC_TMCR_T32                    *((volatile  uint8_t *)(0x424A999CUL))

#define bFM_BT11_PWC_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A9A20UL))
#define bFM4_BT11_PWC_TMCR2_CKS3                  *((volatile  uint8_t *)(0x424A9A20UL))

#define bFM_BT11_PWM_STC_UDIR                     *((volatile  uint8_t *)(0x424A9A00UL))
#define bFM4_BT11_PWM_STC_UDIR                    *((volatile  uint8_t *)(0x424A9A00UL))
#define bFM_BT11_PWM_STC_DTIR                     *((volatile  uint8_t *)(0x424A9A04UL))
#define bFM4_BT11_PWM_STC_DTIR                    *((volatile  uint8_t *)(0x424A9A04UL))
#define bFM_BT11_PWM_STC_TGIR                     *((volatile  uint8_t *)(0x424A9A08UL))
#define bFM4_BT11_PWM_STC_TGIR                    *((volatile  uint8_t *)(0x424A9A08UL))
#define bFM_BT11_PWM_STC_UDIE                     *((volatile  uint8_t *)(0x424A9A10UL))
#define bFM4_BT11_PWM_STC_UDIE                    *((volatile  uint8_t *)(0x424A9A10UL))
#define bFM_BT11_PWM_STC_DTIE                     *((volatile  uint8_t *)(0x424A9A14UL))
#define bFM4_BT11_PWM_STC_DTIE                    *((volatile  uint8_t *)(0x424A9A14UL))
#define bFM_BT11_PWM_STC_TGIE                     *((volatile  uint8_t *)(0x424A9A18UL))
#define bFM4_BT11_PWM_STC_TGIE                    *((volatile  uint8_t *)(0x424A9A18UL))

#define bFM_BT11_PWM_TMCR_STRG                    *((volatile  uint8_t *)(0x424A9980UL))
#define bFM4_BT11_PWM_TMCR_STRG                   *((volatile  uint8_t *)(0x424A9980UL))
#define bFM_BT11_PWM_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A9984UL))
#define bFM4_BT11_PWM_TMCR_CTEN                   *((volatile  uint8_t *)(0x424A9984UL))
#define bFM_BT11_PWM_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A9988UL))
#define bFM4_BT11_PWM_TMCR_MDSE                   *((volatile  uint8_t *)(0x424A9988UL))
#define bFM_BT11_PWM_TMCR_OSEL                    *((volatile  uint8_t *)(0x424A998CUL))
#define bFM4_BT11_PWM_TMCR_OSEL                   *((volatile  uint8_t *)(0x424A998CUL))
#define bFM_BT11_PWM_TMCR_PMSK                    *((volatile  uint8_t *)(0x424A99A8UL))
#define bFM4_BT11_PWM_TMCR_PMSK                   *((volatile  uint8_t *)(0x424A99A8UL))
#define bFM_BT11_PWM_TMCR_RTGEN                   *((volatile  uint8_t *)(0x424A99ACUL))
#define bFM4_BT11_PWM_TMCR_RTGEN                  *((volatile  uint8_t *)(0x424A99ACUL))

#define bFM_BT11_PWM_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A9A20UL))
#define bFM4_BT11_PWM_TMCR2_CKS3                  *((volatile  uint8_t *)(0x424A9A20UL))

#define bFM_BT11_RT_STC_UDIR                      *((volatile  uint8_t *)(0x424A9A00UL))
#define bFM4_BT11_RT_STC_UDIR                     *((volatile  uint8_t *)(0x424A9A00UL))
#define bFM_BT11_RT_STC_TGIR                      *((volatile  uint8_t *)(0x424A9A08UL))
#define bFM4_BT11_RT_STC_TGIR                     *((volatile  uint8_t *)(0x424A9A08UL))
#define bFM_BT11_RT_STC_UDIE                      *((volatile  uint8_t *)(0x424A9A10UL))
#define bFM4_BT11_RT_STC_UDIE                     *((volatile  uint8_t *)(0x424A9A10UL))
#define bFM_BT11_RT_STC_TGIE                      *((volatile  uint8_t *)(0x424A9A18UL))
#define bFM4_BT11_RT_STC_TGIE                     *((volatile  uint8_t *)(0x424A9A18UL))

#define bFM_BT11_RT_TMCR_STRG                     *((volatile  uint8_t *)(0x424A9980UL))
#define bFM4_BT11_RT_TMCR_STRG                    *((volatile  uint8_t *)(0x424A9980UL))
#define bFM_BT11_RT_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A9984UL))
#define bFM4_BT11_RT_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A9984UL))
#define bFM_BT11_RT_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A9988UL))
#define bFM4_BT11_RT_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A9988UL))
#define bFM_BT11_RT_TMCR_OSEL                     *((volatile  uint8_t *)(0x424A998CUL))
#define bFM4_BT11_RT_TMCR_OSEL                    *((volatile  uint8_t *)(0x424A998CUL))
#define bFM_BT11_RT_TMCR_T32                      *((volatile  uint8_t *)(0x424A999CUL))
#define bFM4_BT11_RT_TMCR_T32                     *((volatile  uint8_t *)(0x424A999CUL))

#define bFM_BT11_RT_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A9A20UL))
#define bFM4_BT11_RT_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A9A20UL))
#define bFM_BT11_RT_TMCR2_GATE                    *((volatile  uint8_t *)(0x424A9A3CUL))
#define bFM4_BT11_RT_TMCR2_GATE                   *((volatile  uint8_t *)(0x424A9A3CUL))


/*******************************************************************************
* BT Registers BT12
*   Bitband Section
*******************************************************************************/
#define bFM_BT12_PPG_STC_UDIR                     *((volatile  uint8_t *)(0x424AC200UL))
#define bFM4_BT12_PPG_STC_UDIR                    *((volatile  uint8_t *)(0x424AC200UL))
#define bFM_BT12_PPG_STC_TGIR                     *((volatile  uint8_t *)(0x424AC208UL))
#define bFM4_BT12_PPG_STC_TGIR                    *((volatile  uint8_t *)(0x424AC208UL))
#define bFM_BT12_PPG_STC_UDIE                     *((volatile  uint8_t *)(0x424AC210UL))
#define bFM4_BT12_PPG_STC_UDIE                    *((volatile  uint8_t *)(0x424AC210UL))
#define bFM_BT12_PPG_STC_TGIE                     *((volatile  uint8_t *)(0x424AC218UL))
#define bFM4_BT12_PPG_STC_TGIE                    *((volatile  uint8_t *)(0x424AC218UL))

#define bFM_BT12_PPG_TMCR_STRG                    *((volatile  uint8_t *)(0x424AC180UL))
#define bFM4_BT12_PPG_TMCR_STRG                   *((volatile  uint8_t *)(0x424AC180UL))
#define bFM_BT12_PPG_TMCR_CTEN                    *((volatile  uint8_t *)(0x424AC184UL))
#define bFM4_BT12_PPG_TMCR_CTEN                   *((volatile  uint8_t *)(0x424AC184UL))
#define bFM_BT12_PPG_TMCR_MDSE                    *((volatile  uint8_t *)(0x424AC188UL))
#define bFM4_BT12_PPG_TMCR_MDSE                   *((volatile  uint8_t *)(0x424AC188UL))
#define bFM_BT12_PPG_TMCR_OSEL                    *((volatile  uint8_t *)(0x424AC18CUL))
#define bFM4_BT12_PPG_TMCR_OSEL                   *((volatile  uint8_t *)(0x424AC18CUL))
#define bFM_BT12_PPG_TMCR_PMSK                    *((volatile  uint8_t *)(0x424AC1A8UL))
#define bFM4_BT12_PPG_TMCR_PMSK                   *((volatile  uint8_t *)(0x424AC1A8UL))
#define bFM_BT12_PPG_TMCR_RTGEN                   *((volatile  uint8_t *)(0x424AC1ACUL))
#define bFM4_BT12_PPG_TMCR_RTGEN                  *((volatile  uint8_t *)(0x424AC1ACUL))

#define bFM_BT12_PPG_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424AC220UL))
#define bFM4_BT12_PPG_TMCR2_CKS3                  *((volatile  uint8_t *)(0x424AC220UL))

#define bFM_BT12_PWC_STC_OVIR                     *((volatile  uint8_t *)(0x424AC200UL))
#define bFM4_BT12_PWC_STC_OVIR                    *((volatile  uint8_t *)(0x424AC200UL))
#define bFM_BT12_PWC_STC_EDIR                     *((volatile  uint8_t *)(0x424AC208UL))
#define bFM4_BT12_PWC_STC_EDIR                    *((volatile  uint8_t *)(0x424AC208UL))
#define bFM_BT12_PWC_STC_OVIE                     *((volatile  uint8_t *)(0x424AC210UL))
#define bFM4_BT12_PWC_STC_OVIE                    *((volatile  uint8_t *)(0x424AC210UL))
#define bFM_BT12_PWC_STC_EDIE                     *((volatile  uint8_t *)(0x424AC218UL))
#define bFM4_BT12_PWC_STC_EDIE                    *((volatile  uint8_t *)(0x424AC218UL))
#define bFM_BT12_PWC_STC_ERR                      *((volatile  uint8_t *)(0x424AC21CUL))
#define bFM4_BT12_PWC_STC_ERR                     *((volatile  uint8_t *)(0x424AC21CUL))

#define bFM_BT12_PWC_TMCR_CTEN                    *((volatile  uint8_t *)(0x424AC184UL))
#define bFM4_BT12_PWC_TMCR_CTEN                   *((volatile  uint8_t *)(0x424AC184UL))
#define bFM_BT12_PWC_TMCR_MDSE                    *((volatile  uint8_t *)(0x424AC188UL))
#define bFM4_BT12_PWC_TMCR_MDSE                   *((volatile  uint8_t *)(0x424AC188UL))
#define bFM_BT12_PWC_TMCR_T32                     *((volatile  uint8_t *)(0x424AC19CUL))
#define bFM4_BT12_PWC_TMCR_T32                    *((volatile  uint8_t *)(0x424AC19CUL))

#define bFM_BT12_PWC_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424AC220UL))
#define bFM4_BT12_PWC_TMCR2_CKS3                  *((volatile  uint8_t *)(0x424AC220UL))

#define bFM_BT12_PWM_STC_UDIR                     *((volatile  uint8_t *)(0x424AC200UL))
#define bFM4_BT12_PWM_STC_UDIR                    *((volatile  uint8_t *)(0x424AC200UL))
#define bFM_BT12_PWM_STC_DTIR                     *((volatile  uint8_t *)(0x424AC204UL))
#define bFM4_BT12_PWM_STC_DTIR                    *((volatile  uint8_t *)(0x424AC204UL))
#define bFM_BT12_PWM_STC_TGIR                     *((volatile  uint8_t *)(0x424AC208UL))
#define bFM4_BT12_PWM_STC_TGIR                    *((volatile  uint8_t *)(0x424AC208UL))
#define bFM_BT12_PWM_STC_UDIE                     *((volatile  uint8_t *)(0x424AC210UL))
#define bFM4_BT12_PWM_STC_UDIE                    *((volatile  uint8_t *)(0x424AC210UL))
#define bFM_BT12_PWM_STC_DTIE                     *((volatile  uint8_t *)(0x424AC214UL))
#define bFM4_BT12_PWM_STC_DTIE                    *((volatile  uint8_t *)(0x424AC214UL))
#define bFM_BT12_PWM_STC_TGIE                     *((volatile  uint8_t *)(0x424AC218UL))
#define bFM4_BT12_PWM_STC_TGIE                    *((volatile  uint8_t *)(0x424AC218UL))

#define bFM_BT12_PWM_TMCR_STRG                    *((volatile  uint8_t *)(0x424AC180UL))
#define bFM4_BT12_PWM_TMCR_STRG                   *((volatile  uint8_t *)(0x424AC180UL))
#define bFM_BT12_PWM_TMCR_CTEN                    *((volatile  uint8_t *)(0x424AC184UL))
#define bFM4_BT12_PWM_TMCR_CTEN                   *((volatile  uint8_t *)(0x424AC184UL))
#define bFM_BT12_PWM_TMCR_MDSE                    *((volatile  uint8_t *)(0x424AC188UL))
#define bFM4_BT12_PWM_TMCR_MDSE                   *((volatile  uint8_t *)(0x424AC188UL))
#define bFM_BT12_PWM_TMCR_OSEL                    *((volatile  uint8_t *)(0x424AC18CUL))
#define bFM4_BT12_PWM_TMCR_OSEL                   *((volatile  uint8_t *)(0x424AC18CUL))
#define bFM_BT12_PWM_TMCR_PMSK                    *((volatile  uint8_t *)(0x424AC1A8UL))
#define bFM4_BT12_PWM_TMCR_PMSK                   *((volatile  uint8_t *)(0x424AC1A8UL))
#define bFM_BT12_PWM_TMCR_RTGEN                   *((volatile  uint8_t *)(0x424AC1ACUL))
#define bFM4_BT12_PWM_TMCR_RTGEN                  *((volatile  uint8_t *)(0x424AC1ACUL))

#define bFM_BT12_PWM_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424AC220UL))
#define bFM4_BT12_PWM_TMCR2_CKS3                  *((volatile  uint8_t *)(0x424AC220UL))

#define bFM_BT12_RT_STC_UDIR                      *((volatile  uint8_t *)(0x424AC200UL))
#define bFM4_BT12_RT_STC_UDIR                     *((volatile  uint8_t *)(0x424AC200UL))
#define bFM_BT12_RT_STC_TGIR                      *((volatile  uint8_t *)(0x424AC208UL))
#define bFM4_BT12_RT_STC_TGIR                     *((volatile  uint8_t *)(0x424AC208UL))
#define bFM_BT12_RT_STC_UDIE                      *((volatile  uint8_t *)(0x424AC210UL))
#define bFM4_BT12_RT_STC_UDIE                     *((volatile  uint8_t *)(0x424AC210UL))
#define bFM_BT12_RT_STC_TGIE                      *((volatile  uint8_t *)(0x424AC218UL))
#define bFM4_BT12_RT_STC_TGIE                     *((volatile  uint8_t *)(0x424AC218UL))

#define bFM_BT12_RT_TMCR_STRG                     *((volatile  uint8_t *)(0x424AC180UL))
#define bFM4_BT12_RT_TMCR_STRG                    *((volatile  uint8_t *)(0x424AC180UL))
#define bFM_BT12_RT_TMCR_CTEN                     *((volatile  uint8_t *)(0x424AC184UL))
#define bFM4_BT12_RT_TMCR_CTEN                    *((volatile  uint8_t *)(0x424AC184UL))
#define bFM_BT12_RT_TMCR_MDSE                     *((volatile  uint8_t *)(0x424AC188UL))
#define bFM4_BT12_RT_TMCR_MDSE                    *((volatile  uint8_t *)(0x424AC188UL))
#define bFM_BT12_RT_TMCR_OSEL                     *((volatile  uint8_t *)(0x424AC18CUL))
#define bFM4_BT12_RT_TMCR_OSEL                    *((volatile  uint8_t *)(0x424AC18CUL))
#define bFM_BT12_RT_TMCR_T32                      *((volatile  uint8_t *)(0x424AC19CUL))
#define bFM4_BT12_RT_TMCR_T32                     *((volatile  uint8_t *)(0x424AC19CUL))

#define bFM_BT12_RT_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424AC220UL))
#define bFM4_BT12_RT_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424AC220UL))
#define bFM_BT12_RT_TMCR2_GATE                    *((volatile  uint8_t *)(0x424AC23CUL))
#define bFM4_BT12_RT_TMCR2_GATE                   *((volatile  uint8_t *)(0x424AC23CUL))


/*******************************************************************************
* BT Registers BT13
*   Bitband Section
*******************************************************************************/
#define bFM_BT13_PPG_STC_UDIR                     *((volatile  uint8_t *)(0x424ACA00UL))
#define bFM4_BT13_PPG_STC_UDIR                    *((volatile  uint8_t *)(0x424ACA00UL))
#define bFM_BT13_PPG_STC_TGIR                     *((volatile  uint8_t *)(0x424ACA08UL))
#define bFM4_BT13_PPG_STC_TGIR                    *((volatile  uint8_t *)(0x424ACA08UL))
#define bFM_BT13_PPG_STC_UDIE                     *((volatile  uint8_t *)(0x424ACA10UL))
#define bFM4_BT13_PPG_STC_UDIE                    *((volatile  uint8_t *)(0x424ACA10UL))
#define bFM_BT13_PPG_STC_TGIE                     *((volatile  uint8_t *)(0x424ACA18UL))
#define bFM4_BT13_PPG_STC_TGIE                    *((volatile  uint8_t *)(0x424ACA18UL))

#define bFM_BT13_PPG_TMCR_STRG                    *((volatile  uint8_t *)(0x424AC980UL))
#define bFM4_BT13_PPG_TMCR_STRG                   *((volatile  uint8_t *)(0x424AC980UL))
#define bFM_BT13_PPG_TMCR_CTEN                    *((volatile  uint8_t *)(0x424AC984UL))
#define bFM4_BT13_PPG_TMCR_CTEN                   *((volatile  uint8_t *)(0x424AC984UL))
#define bFM_BT13_PPG_TMCR_MDSE                    *((volatile  uint8_t *)(0x424AC988UL))
#define bFM4_BT13_PPG_TMCR_MDSE                   *((volatile  uint8_t *)(0x424AC988UL))
#define bFM_BT13_PPG_TMCR_OSEL                    *((volatile  uint8_t *)(0x424AC98CUL))
#define bFM4_BT13_PPG_TMCR_OSEL                   *((volatile  uint8_t *)(0x424AC98CUL))
#define bFM_BT13_PPG_TMCR_PMSK                    *((volatile  uint8_t *)(0x424AC9A8UL))
#define bFM4_BT13_PPG_TMCR_PMSK                   *((volatile  uint8_t *)(0x424AC9A8UL))
#define bFM_BT13_PPG_TMCR_RTGEN                   *((volatile  uint8_t *)(0x424AC9ACUL))
#define bFM4_BT13_PPG_TMCR_RTGEN                  *((volatile  uint8_t *)(0x424AC9ACUL))

#define bFM_BT13_PPG_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424ACA20UL))
#define bFM4_BT13_PPG_TMCR2_CKS3                  *((volatile  uint8_t *)(0x424ACA20UL))

#define bFM_BT13_PWC_STC_OVIR                     *((volatile  uint8_t *)(0x424ACA00UL))
#define bFM4_BT13_PWC_STC_OVIR                    *((volatile  uint8_t *)(0x424ACA00UL))
#define bFM_BT13_PWC_STC_EDIR                     *((volatile  uint8_t *)(0x424ACA08UL))
#define bFM4_BT13_PWC_STC_EDIR                    *((volatile  uint8_t *)(0x424ACA08UL))
#define bFM_BT13_PWC_STC_OVIE                     *((volatile  uint8_t *)(0x424ACA10UL))
#define bFM4_BT13_PWC_STC_OVIE                    *((volatile  uint8_t *)(0x424ACA10UL))
#define bFM_BT13_PWC_STC_EDIE                     *((volatile  uint8_t *)(0x424ACA18UL))
#define bFM4_BT13_PWC_STC_EDIE                    *((volatile  uint8_t *)(0x424ACA18UL))
#define bFM_BT13_PWC_STC_ERR                      *((volatile  uint8_t *)(0x424ACA1CUL))
#define bFM4_BT13_PWC_STC_ERR                     *((volatile  uint8_t *)(0x424ACA1CUL))

#define bFM_BT13_PWC_TMCR_CTEN                    *((volatile  uint8_t *)(0x424AC984UL))
#define bFM4_BT13_PWC_TMCR_CTEN                   *((volatile  uint8_t *)(0x424AC984UL))
#define bFM_BT13_PWC_TMCR_MDSE                    *((volatile  uint8_t *)(0x424AC988UL))
#define bFM4_BT13_PWC_TMCR_MDSE                   *((volatile  uint8_t *)(0x424AC988UL))
#define bFM_BT13_PWC_TMCR_T32                     *((volatile  uint8_t *)(0x424AC99CUL))
#define bFM4_BT13_PWC_TMCR_T32                    *((volatile  uint8_t *)(0x424AC99CUL))

#define bFM_BT13_PWC_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424ACA20UL))
#define bFM4_BT13_PWC_TMCR2_CKS3                  *((volatile  uint8_t *)(0x424ACA20UL))

#define bFM_BT13_PWM_STC_UDIR                     *((volatile  uint8_t *)(0x424ACA00UL))
#define bFM4_BT13_PWM_STC_UDIR                    *((volatile  uint8_t *)(0x424ACA00UL))
#define bFM_BT13_PWM_STC_DTIR                     *((volatile  uint8_t *)(0x424ACA04UL))
#define bFM4_BT13_PWM_STC_DTIR                    *((volatile  uint8_t *)(0x424ACA04UL))
#define bFM_BT13_PWM_STC_TGIR                     *((volatile  uint8_t *)(0x424ACA08UL))
#define bFM4_BT13_PWM_STC_TGIR                    *((volatile  uint8_t *)(0x424ACA08UL))
#define bFM_BT13_PWM_STC_UDIE                     *((volatile  uint8_t *)(0x424ACA10UL))
#define bFM4_BT13_PWM_STC_UDIE                    *((volatile  uint8_t *)(0x424ACA10UL))
#define bFM_BT13_PWM_STC_DTIE                     *((volatile  uint8_t *)(0x424ACA14UL))
#define bFM4_BT13_PWM_STC_DTIE                    *((volatile  uint8_t *)(0x424ACA14UL))
#define bFM_BT13_PWM_STC_TGIE                     *((volatile  uint8_t *)(0x424ACA18UL))
#define bFM4_BT13_PWM_STC_TGIE                    *((volatile  uint8_t *)(0x424ACA18UL))

#define bFM_BT13_PWM_TMCR_STRG                    *((volatile  uint8_t *)(0x424AC980UL))
#define bFM4_BT13_PWM_TMCR_STRG                   *((volatile  uint8_t *)(0x424AC980UL))
#define bFM_BT13_PWM_TMCR_CTEN                    *((volatile  uint8_t *)(0x424AC984UL))
#define bFM4_BT13_PWM_TMCR_CTEN                   *((volatile  uint8_t *)(0x424AC984UL))
#define bFM_BT13_PWM_TMCR_MDSE                    *((volatile  uint8_t *)(0x424AC988UL))
#define bFM4_BT13_PWM_TMCR_MDSE                   *((volatile  uint8_t *)(0x424AC988UL))
#define bFM_BT13_PWM_TMCR_OSEL                    *((volatile  uint8_t *)(0x424AC98CUL))
#define bFM4_BT13_PWM_TMCR_OSEL                   *((volatile  uint8_t *)(0x424AC98CUL))
#define bFM_BT13_PWM_TMCR_PMSK                    *((volatile  uint8_t *)(0x424AC9A8UL))
#define bFM4_BT13_PWM_TMCR_PMSK                   *((volatile  uint8_t *)(0x424AC9A8UL))
#define bFM_BT13_PWM_TMCR_RTGEN                   *((volatile  uint8_t *)(0x424AC9ACUL))
#define bFM4_BT13_PWM_TMCR_RTGEN                  *((volatile  uint8_t *)(0x424AC9ACUL))

#define bFM_BT13_PWM_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424ACA20UL))
#define bFM4_BT13_PWM_TMCR2_CKS3                  *((volatile  uint8_t *)(0x424ACA20UL))

#define bFM_BT13_RT_STC_UDIR                      *((volatile  uint8_t *)(0x424ACA00UL))
#define bFM4_BT13_RT_STC_UDIR                     *((volatile  uint8_t *)(0x424ACA00UL))
#define bFM_BT13_RT_STC_TGIR                      *((volatile  uint8_t *)(0x424ACA08UL))
#define bFM4_BT13_RT_STC_TGIR                     *((volatile  uint8_t *)(0x424ACA08UL))
#define bFM_BT13_RT_STC_UDIE                      *((volatile  uint8_t *)(0x424ACA10UL))
#define bFM4_BT13_RT_STC_UDIE                     *((volatile  uint8_t *)(0x424ACA10UL))
#define bFM_BT13_RT_STC_TGIE                      *((volatile  uint8_t *)(0x424ACA18UL))
#define bFM4_BT13_RT_STC_TGIE                     *((volatile  uint8_t *)(0x424ACA18UL))

#define bFM_BT13_RT_TMCR_STRG                     *((volatile  uint8_t *)(0x424AC980UL))
#define bFM4_BT13_RT_TMCR_STRG                    *((volatile  uint8_t *)(0x424AC980UL))
#define bFM_BT13_RT_TMCR_CTEN                     *((volatile  uint8_t *)(0x424AC984UL))
#define bFM4_BT13_RT_TMCR_CTEN                    *((volatile  uint8_t *)(0x424AC984UL))
#define bFM_BT13_RT_TMCR_MDSE                     *((volatile  uint8_t *)(0x424AC988UL))
#define bFM4_BT13_RT_TMCR_MDSE                    *((volatile  uint8_t *)(0x424AC988UL))
#define bFM_BT13_RT_TMCR_OSEL                     *((volatile  uint8_t *)(0x424AC98CUL))
#define bFM4_BT13_RT_TMCR_OSEL                    *((volatile  uint8_t *)(0x424AC98CUL))
#define bFM_BT13_RT_TMCR_T32                      *((volatile  uint8_t *)(0x424AC99CUL))
#define bFM4_BT13_RT_TMCR_T32                     *((volatile  uint8_t *)(0x424AC99CUL))

#define bFM_BT13_RT_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424ACA20UL))
#define bFM4_BT13_RT_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424ACA20UL))
#define bFM_BT13_RT_TMCR2_GATE                    *((volatile  uint8_t *)(0x424ACA3CUL))
#define bFM4_BT13_RT_TMCR2_GATE                   *((volatile  uint8_t *)(0x424ACA3CUL))


/*******************************************************************************
* BT Registers BT14
*   Bitband Section
*******************************************************************************/
#define bFM_BT14_PPG_STC_UDIR                     *((volatile  uint8_t *)(0x424AD200UL))
#define bFM4_BT14_PPG_STC_UDIR                    *((volatile  uint8_t *)(0x424AD200UL))
#define bFM_BT14_PPG_STC_TGIR                     *((volatile  uint8_t *)(0x424AD208UL))
#define bFM4_BT14_PPG_STC_TGIR                    *((volatile  uint8_t *)(0x424AD208UL))
#define bFM_BT14_PPG_STC_UDIE                     *((volatile  uint8_t *)(0x424AD210UL))
#define bFM4_BT14_PPG_STC_UDIE                    *((volatile  uint8_t *)(0x424AD210UL))
#define bFM_BT14_PPG_STC_TGIE                     *((volatile  uint8_t *)(0x424AD218UL))
#define bFM4_BT14_PPG_STC_TGIE                    *((volatile  uint8_t *)(0x424AD218UL))

#define bFM_BT14_PPG_TMCR_STRG                    *((volatile  uint8_t *)(0x424AD180UL))
#define bFM4_BT14_PPG_TMCR_STRG                   *((volatile  uint8_t *)(0x424AD180UL))
#define bFM_BT14_PPG_TMCR_CTEN                    *((volatile  uint8_t *)(0x424AD184UL))
#define bFM4_BT14_PPG_TMCR_CTEN                   *((volatile  uint8_t *)(0x424AD184UL))
#define bFM_BT14_PPG_TMCR_MDSE                    *((volatile  uint8_t *)(0x424AD188UL))
#define bFM4_BT14_PPG_TMCR_MDSE                   *((volatile  uint8_t *)(0x424AD188UL))
#define bFM_BT14_PPG_TMCR_OSEL                    *((volatile  uint8_t *)(0x424AD18CUL))
#define bFM4_BT14_PPG_TMCR_OSEL                   *((volatile  uint8_t *)(0x424AD18CUL))
#define bFM_BT14_PPG_TMCR_PMSK                    *((volatile  uint8_t *)(0x424AD1A8UL))
#define bFM4_BT14_PPG_TMCR_PMSK                   *((volatile  uint8_t *)(0x424AD1A8UL))
#define bFM_BT14_PPG_TMCR_RTGEN                   *((volatile  uint8_t *)(0x424AD1ACUL))
#define bFM4_BT14_PPG_TMCR_RTGEN                  *((volatile  uint8_t *)(0x424AD1ACUL))

#define bFM_BT14_PPG_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424AD220UL))
#define bFM4_BT14_PPG_TMCR2_CKS3                  *((volatile  uint8_t *)(0x424AD220UL))

#define bFM_BT14_PWC_STC_OVIR                     *((volatile  uint8_t *)(0x424AD200UL))
#define bFM4_BT14_PWC_STC_OVIR                    *((volatile  uint8_t *)(0x424AD200UL))
#define bFM_BT14_PWC_STC_EDIR                     *((volatile  uint8_t *)(0x424AD208UL))
#define bFM4_BT14_PWC_STC_EDIR                    *((volatile  uint8_t *)(0x424AD208UL))
#define bFM_BT14_PWC_STC_OVIE                     *((volatile  uint8_t *)(0x424AD210UL))
#define bFM4_BT14_PWC_STC_OVIE                    *((volatile  uint8_t *)(0x424AD210UL))
#define bFM_BT14_PWC_STC_EDIE                     *((volatile  uint8_t *)(0x424AD218UL))
#define bFM4_BT14_PWC_STC_EDIE                    *((volatile  uint8_t *)(0x424AD218UL))
#define bFM_BT14_PWC_STC_ERR                      *((volatile  uint8_t *)(0x424AD21CUL))
#define bFM4_BT14_PWC_STC_ERR                     *((volatile  uint8_t *)(0x424AD21CUL))

#define bFM_BT14_PWC_TMCR_CTEN                    *((volatile  uint8_t *)(0x424AD184UL))
#define bFM4_BT14_PWC_TMCR_CTEN                   *((volatile  uint8_t *)(0x424AD184UL))
#define bFM_BT14_PWC_TMCR_MDSE                    *((volatile  uint8_t *)(0x424AD188UL))
#define bFM4_BT14_PWC_TMCR_MDSE                   *((volatile  uint8_t *)(0x424AD188UL))
#define bFM_BT14_PWC_TMCR_T32                     *((volatile  uint8_t *)(0x424AD19CUL))
#define bFM4_BT14_PWC_TMCR_T32                    *((volatile  uint8_t *)(0x424AD19CUL))

#define bFM_BT14_PWC_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424AD220UL))
#define bFM4_BT14_PWC_TMCR2_CKS3                  *((volatile  uint8_t *)(0x424AD220UL))

#define bFM_BT14_PWM_STC_UDIR                     *((volatile  uint8_t *)(0x424AD200UL))
#define bFM4_BT14_PWM_STC_UDIR                    *((volatile  uint8_t *)(0x424AD200UL))
#define bFM_BT14_PWM_STC_DTIR                     *((volatile  uint8_t *)(0x424AD204UL))
#define bFM4_BT14_PWM_STC_DTIR                    *((volatile  uint8_t *)(0x424AD204UL))
#define bFM_BT14_PWM_STC_TGIR                     *((volatile  uint8_t *)(0x424AD208UL))
#define bFM4_BT14_PWM_STC_TGIR                    *((volatile  uint8_t *)(0x424AD208UL))
#define bFM_BT14_PWM_STC_UDIE                     *((volatile  uint8_t *)(0x424AD210UL))
#define bFM4_BT14_PWM_STC_UDIE                    *((volatile  uint8_t *)(0x424AD210UL))
#define bFM_BT14_PWM_STC_DTIE                     *((volatile  uint8_t *)(0x424AD214UL))
#define bFM4_BT14_PWM_STC_DTIE                    *((volatile  uint8_t *)(0x424AD214UL))
#define bFM_BT14_PWM_STC_TGIE                     *((volatile  uint8_t *)(0x424AD218UL))
#define bFM4_BT14_PWM_STC_TGIE                    *((volatile  uint8_t *)(0x424AD218UL))

#define bFM_BT14_PWM_TMCR_STRG                    *((volatile  uint8_t *)(0x424AD180UL))
#define bFM4_BT14_PWM_TMCR_STRG                   *((volatile  uint8_t *)(0x424AD180UL))
#define bFM_BT14_PWM_TMCR_CTEN                    *((volatile  uint8_t *)(0x424AD184UL))
#define bFM4_BT14_PWM_TMCR_CTEN                   *((volatile  uint8_t *)(0x424AD184UL))
#define bFM_BT14_PWM_TMCR_MDSE                    *((volatile  uint8_t *)(0x424AD188UL))
#define bFM4_BT14_PWM_TMCR_MDSE                   *((volatile  uint8_t *)(0x424AD188UL))
#define bFM_BT14_PWM_TMCR_OSEL                    *((volatile  uint8_t *)(0x424AD18CUL))
#define bFM4_BT14_PWM_TMCR_OSEL                   *((volatile  uint8_t *)(0x424AD18CUL))
#define bFM_BT14_PWM_TMCR_PMSK                    *((volatile  uint8_t *)(0x424AD1A8UL))
#define bFM4_BT14_PWM_TMCR_PMSK                   *((volatile  uint8_t *)(0x424AD1A8UL))
#define bFM_BT14_PWM_TMCR_RTGEN                   *((volatile  uint8_t *)(0x424AD1ACUL))
#define bFM4_BT14_PWM_TMCR_RTGEN                  *((volatile  uint8_t *)(0x424AD1ACUL))

#define bFM_BT14_PWM_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424AD220UL))
#define bFM4_BT14_PWM_TMCR2_CKS3                  *((volatile  uint8_t *)(0x424AD220UL))

#define bFM_BT14_RT_STC_UDIR                      *((volatile  uint8_t *)(0x424AD200UL))
#define bFM4_BT14_RT_STC_UDIR                     *((volatile  uint8_t *)(0x424AD200UL))
#define bFM_BT14_RT_STC_TGIR                      *((volatile  uint8_t *)(0x424AD208UL))
#define bFM4_BT14_RT_STC_TGIR                     *((volatile  uint8_t *)(0x424AD208UL))
#define bFM_BT14_RT_STC_UDIE                      *((volatile  uint8_t *)(0x424AD210UL))
#define bFM4_BT14_RT_STC_UDIE                     *((volatile  uint8_t *)(0x424AD210UL))
#define bFM_BT14_RT_STC_TGIE                      *((volatile  uint8_t *)(0x424AD218UL))
#define bFM4_BT14_RT_STC_TGIE                     *((volatile  uint8_t *)(0x424AD218UL))

#define bFM_BT14_RT_TMCR_STRG                     *((volatile  uint8_t *)(0x424AD180UL))
#define bFM4_BT14_RT_TMCR_STRG                    *((volatile  uint8_t *)(0x424AD180UL))
#define bFM_BT14_RT_TMCR_CTEN                     *((volatile  uint8_t *)(0x424AD184UL))
#define bFM4_BT14_RT_TMCR_CTEN                    *((volatile  uint8_t *)(0x424AD184UL))
#define bFM_BT14_RT_TMCR_MDSE                     *((volatile  uint8_t *)(0x424AD188UL))
#define bFM4_BT14_RT_TMCR_MDSE                    *((volatile  uint8_t *)(0x424AD188UL))
#define bFM_BT14_RT_TMCR_OSEL                     *((volatile  uint8_t *)(0x424AD18CUL))
#define bFM4_BT14_RT_TMCR_OSEL                    *((volatile  uint8_t *)(0x424AD18CUL))
#define bFM_BT14_RT_TMCR_T32                      *((volatile  uint8_t *)(0x424AD19CUL))
#define bFM4_BT14_RT_TMCR_T32                     *((volatile  uint8_t *)(0x424AD19CUL))

#define bFM_BT14_RT_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424AD220UL))
#define bFM4_BT14_RT_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424AD220UL))
#define bFM_BT14_RT_TMCR2_GATE                    *((volatile  uint8_t *)(0x424AD23CUL))
#define bFM4_BT14_RT_TMCR2_GATE                   *((volatile  uint8_t *)(0x424AD23CUL))


/*******************************************************************************
* BT Registers BT15
*   Bitband Section
*******************************************************************************/
#define bFM_BT15_PPG_STC_UDIR                     *((volatile  uint8_t *)(0x424ADA00UL))
#define bFM4_BT15_PPG_STC_UDIR                    *((volatile  uint8_t *)(0x424ADA00UL))
#define bFM_BT15_PPG_STC_TGIR                     *((volatile  uint8_t *)(0x424ADA08UL))
#define bFM4_BT15_PPG_STC_TGIR                    *((volatile  uint8_t *)(0x424ADA08UL))
#define bFM_BT15_PPG_STC_UDIE                     *((volatile  uint8_t *)(0x424ADA10UL))
#define bFM4_BT15_PPG_STC_UDIE                    *((volatile  uint8_t *)(0x424ADA10UL))
#define bFM_BT15_PPG_STC_TGIE                     *((volatile  uint8_t *)(0x424ADA18UL))
#define bFM4_BT15_PPG_STC_TGIE                    *((volatile  uint8_t *)(0x424ADA18UL))

#define bFM_BT15_PPG_TMCR_STRG                    *((volatile  uint8_t *)(0x424AD980UL))
#define bFM4_BT15_PPG_TMCR_STRG                   *((volatile  uint8_t *)(0x424AD980UL))
#define bFM_BT15_PPG_TMCR_CTEN                    *((volatile  uint8_t *)(0x424AD984UL))
#define bFM4_BT15_PPG_TMCR_CTEN                   *((volatile  uint8_t *)(0x424AD984UL))
#define bFM_BT15_PPG_TMCR_MDSE                    *((volatile  uint8_t *)(0x424AD988UL))
#define bFM4_BT15_PPG_TMCR_MDSE                   *((volatile  uint8_t *)(0x424AD988UL))
#define bFM_BT15_PPG_TMCR_OSEL                    *((volatile  uint8_t *)(0x424AD98CUL))
#define bFM4_BT15_PPG_TMCR_OSEL                   *((volatile  uint8_t *)(0x424AD98CUL))
#define bFM_BT15_PPG_TMCR_PMSK                    *((volatile  uint8_t *)(0x424AD9A8UL))
#define bFM4_BT15_PPG_TMCR_PMSK                   *((volatile  uint8_t *)(0x424AD9A8UL))
#define bFM_BT15_PPG_TMCR_RTGEN                   *((volatile  uint8_t *)(0x424AD9ACUL))
#define bFM4_BT15_PPG_TMCR_RTGEN                  *((volatile  uint8_t *)(0x424AD9ACUL))

#define bFM_BT15_PPG_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424ADA20UL))
#define bFM4_BT15_PPG_TMCR2_CKS3                  *((volatile  uint8_t *)(0x424ADA20UL))

#define bFM_BT15_PWC_STC_OVIR                     *((volatile  uint8_t *)(0x424ADA00UL))
#define bFM4_BT15_PWC_STC_OVIR                    *((volatile  uint8_t *)(0x424ADA00UL))
#define bFM_BT15_PWC_STC_EDIR                     *((volatile  uint8_t *)(0x424ADA08UL))
#define bFM4_BT15_PWC_STC_EDIR                    *((volatile  uint8_t *)(0x424ADA08UL))
#define bFM_BT15_PWC_STC_OVIE                     *((volatile  uint8_t *)(0x424ADA10UL))
#define bFM4_BT15_PWC_STC_OVIE                    *((volatile  uint8_t *)(0x424ADA10UL))
#define bFM_BT15_PWC_STC_EDIE                     *((volatile  uint8_t *)(0x424ADA18UL))
#define bFM4_BT15_PWC_STC_EDIE                    *((volatile  uint8_t *)(0x424ADA18UL))
#define bFM_BT15_PWC_STC_ERR                      *((volatile  uint8_t *)(0x424ADA1CUL))
#define bFM4_BT15_PWC_STC_ERR                     *((volatile  uint8_t *)(0x424ADA1CUL))

#define bFM_BT15_PWC_TMCR_CTEN                    *((volatile  uint8_t *)(0x424AD984UL))
#define bFM4_BT15_PWC_TMCR_CTEN                   *((volatile  uint8_t *)(0x424AD984UL))
#define bFM_BT15_PWC_TMCR_MDSE                    *((volatile  uint8_t *)(0x424AD988UL))
#define bFM4_BT15_PWC_TMCR_MDSE                   *((volatile  uint8_t *)(0x424AD988UL))
#define bFM_BT15_PWC_TMCR_T32                     *((volatile  uint8_t *)(0x424AD99CUL))
#define bFM4_BT15_PWC_TMCR_T32                    *((volatile  uint8_t *)(0x424AD99CUL))

#define bFM_BT15_PWC_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424ADA20UL))
#define bFM4_BT15_PWC_TMCR2_CKS3                  *((volatile  uint8_t *)(0x424ADA20UL))

#define bFM_BT15_PWM_STC_UDIR                     *((volatile  uint8_t *)(0x424ADA00UL))
#define bFM4_BT15_PWM_STC_UDIR                    *((volatile  uint8_t *)(0x424ADA00UL))
#define bFM_BT15_PWM_STC_DTIR                     *((volatile  uint8_t *)(0x424ADA04UL))
#define bFM4_BT15_PWM_STC_DTIR                    *((volatile  uint8_t *)(0x424ADA04UL))
#define bFM_BT15_PWM_STC_TGIR                     *((volatile  uint8_t *)(0x424ADA08UL))
#define bFM4_BT15_PWM_STC_TGIR                    *((volatile  uint8_t *)(0x424ADA08UL))
#define bFM_BT15_PWM_STC_UDIE                     *((volatile  uint8_t *)(0x424ADA10UL))
#define bFM4_BT15_PWM_STC_UDIE                    *((volatile  uint8_t *)(0x424ADA10UL))
#define bFM_BT15_PWM_STC_DTIE                     *((volatile  uint8_t *)(0x424ADA14UL))
#define bFM4_BT15_PWM_STC_DTIE                    *((volatile  uint8_t *)(0x424ADA14UL))
#define bFM_BT15_PWM_STC_TGIE                     *((volatile  uint8_t *)(0x424ADA18UL))
#define bFM4_BT15_PWM_STC_TGIE                    *((volatile  uint8_t *)(0x424ADA18UL))

#define bFM_BT15_PWM_TMCR_STRG                    *((volatile  uint8_t *)(0x424AD980UL))
#define bFM4_BT15_PWM_TMCR_STRG                   *((volatile  uint8_t *)(0x424AD980UL))
#define bFM_BT15_PWM_TMCR_CTEN                    *((volatile  uint8_t *)(0x424AD984UL))
#define bFM4_BT15_PWM_TMCR_CTEN                   *((volatile  uint8_t *)(0x424AD984UL))
#define bFM_BT15_PWM_TMCR_MDSE                    *((volatile  uint8_t *)(0x424AD988UL))
#define bFM4_BT15_PWM_TMCR_MDSE                   *((volatile  uint8_t *)(0x424AD988UL))
#define bFM_BT15_PWM_TMCR_OSEL                    *((volatile  uint8_t *)(0x424AD98CUL))
#define bFM4_BT15_PWM_TMCR_OSEL                   *((volatile  uint8_t *)(0x424AD98CUL))
#define bFM_BT15_PWM_TMCR_PMSK                    *((volatile  uint8_t *)(0x424AD9A8UL))
#define bFM4_BT15_PWM_TMCR_PMSK                   *((volatile  uint8_t *)(0x424AD9A8UL))
#define bFM_BT15_PWM_TMCR_RTGEN                   *((volatile  uint8_t *)(0x424AD9ACUL))
#define bFM4_BT15_PWM_TMCR_RTGEN                  *((volatile  uint8_t *)(0x424AD9ACUL))

#define bFM_BT15_PWM_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424ADA20UL))
#define bFM4_BT15_PWM_TMCR2_CKS3                  *((volatile  uint8_t *)(0x424ADA20UL))

#define bFM_BT15_RT_STC_UDIR                      *((volatile  uint8_t *)(0x424ADA00UL))
#define bFM4_BT15_RT_STC_UDIR                     *((volatile  uint8_t *)(0x424ADA00UL))
#define bFM_BT15_RT_STC_TGIR                      *((volatile  uint8_t *)(0x424ADA08UL))
#define bFM4_BT15_RT_STC_TGIR                     *((volatile  uint8_t *)(0x424ADA08UL))
#define bFM_BT15_RT_STC_UDIE                      *((volatile  uint8_t *)(0x424ADA10UL))
#define bFM4_BT15_RT_STC_UDIE                     *((volatile  uint8_t *)(0x424ADA10UL))
#define bFM_BT15_RT_STC_TGIE                      *((volatile  uint8_t *)(0x424ADA18UL))
#define bFM4_BT15_RT_STC_TGIE                     *((volatile  uint8_t *)(0x424ADA18UL))

#define bFM_BT15_RT_TMCR_STRG                     *((volatile  uint8_t *)(0x424AD980UL))
#define bFM4_BT15_RT_TMCR_STRG                    *((volatile  uint8_t *)(0x424AD980UL))
#define bFM_BT15_RT_TMCR_CTEN                     *((volatile  uint8_t *)(0x424AD984UL))
#define bFM4_BT15_RT_TMCR_CTEN                    *((volatile  uint8_t *)(0x424AD984UL))
#define bFM_BT15_RT_TMCR_MDSE                     *((volatile  uint8_t *)(0x424AD988UL))
#define bFM4_BT15_RT_TMCR_MDSE                    *((volatile  uint8_t *)(0x424AD988UL))
#define bFM_BT15_RT_TMCR_OSEL                     *((volatile  uint8_t *)(0x424AD98CUL))
#define bFM4_BT15_RT_TMCR_OSEL                    *((volatile  uint8_t *)(0x424AD98CUL))
#define bFM_BT15_RT_TMCR_T32                      *((volatile  uint8_t *)(0x424AD99CUL))
#define bFM4_BT15_RT_TMCR_T32                     *((volatile  uint8_t *)(0x424AD99CUL))

#define bFM_BT15_RT_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424ADA20UL))
#define bFM4_BT15_RT_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424ADA20UL))
#define bFM_BT15_RT_TMCR2_GATE                    *((volatile  uint8_t *)(0x424ADA3CUL))
#define bFM4_BT15_RT_TMCR2_GATE                   *((volatile  uint8_t *)(0x424ADA3CUL))


/*******************************************************************************
* BT Registers BT2
*   Bitband Section
*******************************************************************************/
#define bFM_BT2_PPG_STC_UDIR                      *((volatile  uint8_t *)(0x424A1200UL))
#define bFM4_BT2_PPG_STC_UDIR                     *((volatile  uint8_t *)(0x424A1200UL))
#define bFM_BT2_PPG_STC_TGIR                      *((volatile  uint8_t *)(0x424A1208UL))
#define bFM4_BT2_PPG_STC_TGIR                     *((volatile  uint8_t *)(0x424A1208UL))
#define bFM_BT2_PPG_STC_UDIE                      *((volatile  uint8_t *)(0x424A1210UL))
#define bFM4_BT2_PPG_STC_UDIE                     *((volatile  uint8_t *)(0x424A1210UL))
#define bFM_BT2_PPG_STC_TGIE                      *((volatile  uint8_t *)(0x424A1218UL))
#define bFM4_BT2_PPG_STC_TGIE                     *((volatile  uint8_t *)(0x424A1218UL))

#define bFM_BT2_PPG_TMCR_STRG                     *((volatile  uint8_t *)(0x424A1180UL))
#define bFM4_BT2_PPG_TMCR_STRG                    *((volatile  uint8_t *)(0x424A1180UL))
#define bFM_BT2_PPG_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A1184UL))
#define bFM4_BT2_PPG_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A1184UL))
#define bFM_BT2_PPG_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A1188UL))
#define bFM4_BT2_PPG_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A1188UL))
#define bFM_BT2_PPG_TMCR_OSEL                     *((volatile  uint8_t *)(0x424A118CUL))
#define bFM4_BT2_PPG_TMCR_OSEL                    *((volatile  uint8_t *)(0x424A118CUL))
#define bFM_BT2_PPG_TMCR_PMSK                     *((volatile  uint8_t *)(0x424A11A8UL))
#define bFM4_BT2_PPG_TMCR_PMSK                    *((volatile  uint8_t *)(0x424A11A8UL))
#define bFM_BT2_PPG_TMCR_RTGEN                    *((volatile  uint8_t *)(0x424A11ACUL))
#define bFM4_BT2_PPG_TMCR_RTGEN                   *((volatile  uint8_t *)(0x424A11ACUL))

#define bFM_BT2_PPG_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A1220UL))
#define bFM4_BT2_PPG_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A1220UL))

#define bFM_BT2_PWC_STC_OVIR                      *((volatile  uint8_t *)(0x424A1200UL))
#define bFM4_BT2_PWC_STC_OVIR                     *((volatile  uint8_t *)(0x424A1200UL))
#define bFM_BT2_PWC_STC_EDIR                      *((volatile  uint8_t *)(0x424A1208UL))
#define bFM4_BT2_PWC_STC_EDIR                     *((volatile  uint8_t *)(0x424A1208UL))
#define bFM_BT2_PWC_STC_OVIE                      *((volatile  uint8_t *)(0x424A1210UL))
#define bFM4_BT2_PWC_STC_OVIE                     *((volatile  uint8_t *)(0x424A1210UL))
#define bFM_BT2_PWC_STC_EDIE                      *((volatile  uint8_t *)(0x424A1218UL))
#define bFM4_BT2_PWC_STC_EDIE                     *((volatile  uint8_t *)(0x424A1218UL))
#define bFM_BT2_PWC_STC_ERR                       *((volatile  uint8_t *)(0x424A121CUL))
#define bFM4_BT2_PWC_STC_ERR                      *((volatile  uint8_t *)(0x424A121CUL))

#define bFM_BT2_PWC_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A1184UL))
#define bFM4_BT2_PWC_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A1184UL))
#define bFM_BT2_PWC_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A1188UL))
#define bFM4_BT2_PWC_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A1188UL))
#define bFM_BT2_PWC_TMCR_T32                      *((volatile  uint8_t *)(0x424A119CUL))
#define bFM4_BT2_PWC_TMCR_T32                     *((volatile  uint8_t *)(0x424A119CUL))

#define bFM_BT2_PWC_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A1220UL))
#define bFM4_BT2_PWC_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A1220UL))

#define bFM_BT2_PWM_STC_UDIR                      *((volatile  uint8_t *)(0x424A1200UL))
#define bFM4_BT2_PWM_STC_UDIR                     *((volatile  uint8_t *)(0x424A1200UL))
#define bFM_BT2_PWM_STC_DTIR                      *((volatile  uint8_t *)(0x424A1204UL))
#define bFM4_BT2_PWM_STC_DTIR                     *((volatile  uint8_t *)(0x424A1204UL))
#define bFM_BT2_PWM_STC_TGIR                      *((volatile  uint8_t *)(0x424A1208UL))
#define bFM4_BT2_PWM_STC_TGIR                     *((volatile  uint8_t *)(0x424A1208UL))
#define bFM_BT2_PWM_STC_UDIE                      *((volatile  uint8_t *)(0x424A1210UL))
#define bFM4_BT2_PWM_STC_UDIE                     *((volatile  uint8_t *)(0x424A1210UL))
#define bFM_BT2_PWM_STC_DTIE                      *((volatile  uint8_t *)(0x424A1214UL))
#define bFM4_BT2_PWM_STC_DTIE                     *((volatile  uint8_t *)(0x424A1214UL))
#define bFM_BT2_PWM_STC_TGIE                      *((volatile  uint8_t *)(0x424A1218UL))
#define bFM4_BT2_PWM_STC_TGIE                     *((volatile  uint8_t *)(0x424A1218UL))

#define bFM_BT2_PWM_TMCR_STRG                     *((volatile  uint8_t *)(0x424A1180UL))
#define bFM4_BT2_PWM_TMCR_STRG                    *((volatile  uint8_t *)(0x424A1180UL))
#define bFM_BT2_PWM_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A1184UL))
#define bFM4_BT2_PWM_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A1184UL))
#define bFM_BT2_PWM_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A1188UL))
#define bFM4_BT2_PWM_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A1188UL))
#define bFM_BT2_PWM_TMCR_OSEL                     *((volatile  uint8_t *)(0x424A118CUL))
#define bFM4_BT2_PWM_TMCR_OSEL                    *((volatile  uint8_t *)(0x424A118CUL))
#define bFM_BT2_PWM_TMCR_PMSK                     *((volatile  uint8_t *)(0x424A11A8UL))
#define bFM4_BT2_PWM_TMCR_PMSK                    *((volatile  uint8_t *)(0x424A11A8UL))
#define bFM_BT2_PWM_TMCR_RTGEN                    *((volatile  uint8_t *)(0x424A11ACUL))
#define bFM4_BT2_PWM_TMCR_RTGEN                   *((volatile  uint8_t *)(0x424A11ACUL))

#define bFM_BT2_PWM_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A1220UL))
#define bFM4_BT2_PWM_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A1220UL))

#define bFM_BT2_RT_STC_UDIR                       *((volatile  uint8_t *)(0x424A1200UL))
#define bFM4_BT2_RT_STC_UDIR                      *((volatile  uint8_t *)(0x424A1200UL))
#define bFM_BT2_RT_STC_TGIR                       *((volatile  uint8_t *)(0x424A1208UL))
#define bFM4_BT2_RT_STC_TGIR                      *((volatile  uint8_t *)(0x424A1208UL))
#define bFM_BT2_RT_STC_UDIE                       *((volatile  uint8_t *)(0x424A1210UL))
#define bFM4_BT2_RT_STC_UDIE                      *((volatile  uint8_t *)(0x424A1210UL))
#define bFM_BT2_RT_STC_TGIE                       *((volatile  uint8_t *)(0x424A1218UL))
#define bFM4_BT2_RT_STC_TGIE                      *((volatile  uint8_t *)(0x424A1218UL))

#define bFM_BT2_RT_TMCR_STRG                      *((volatile  uint8_t *)(0x424A1180UL))
#define bFM4_BT2_RT_TMCR_STRG                     *((volatile  uint8_t *)(0x424A1180UL))
#define bFM_BT2_RT_TMCR_CTEN                      *((volatile  uint8_t *)(0x424A1184UL))
#define bFM4_BT2_RT_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A1184UL))
#define bFM_BT2_RT_TMCR_MDSE                      *((volatile  uint8_t *)(0x424A1188UL))
#define bFM4_BT2_RT_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A1188UL))
#define bFM_BT2_RT_TMCR_OSEL                      *((volatile  uint8_t *)(0x424A118CUL))
#define bFM4_BT2_RT_TMCR_OSEL                     *((volatile  uint8_t *)(0x424A118CUL))
#define bFM_BT2_RT_TMCR_T32                       *((volatile  uint8_t *)(0x424A119CUL))
#define bFM4_BT2_RT_TMCR_T32                      *((volatile  uint8_t *)(0x424A119CUL))

#define bFM_BT2_RT_TMCR2_CKS3                     *((volatile  uint8_t *)(0x424A1220UL))
#define bFM4_BT2_RT_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A1220UL))
#define bFM_BT2_RT_TMCR2_GATE                     *((volatile  uint8_t *)(0x424A123CUL))
#define bFM4_BT2_RT_TMCR2_GATE                    *((volatile  uint8_t *)(0x424A123CUL))


/*******************************************************************************
* BT Registers BT3
*   Bitband Section
*******************************************************************************/
#define bFM_BT3_PPG_STC_UDIR                      *((volatile  uint8_t *)(0x424A1A00UL))
#define bFM4_BT3_PPG_STC_UDIR                     *((volatile  uint8_t *)(0x424A1A00UL))
#define bFM_BT3_PPG_STC_TGIR                      *((volatile  uint8_t *)(0x424A1A08UL))
#define bFM4_BT3_PPG_STC_TGIR                     *((volatile  uint8_t *)(0x424A1A08UL))
#define bFM_BT3_PPG_STC_UDIE                      *((volatile  uint8_t *)(0x424A1A10UL))
#define bFM4_BT3_PPG_STC_UDIE                     *((volatile  uint8_t *)(0x424A1A10UL))
#define bFM_BT3_PPG_STC_TGIE                      *((volatile  uint8_t *)(0x424A1A18UL))
#define bFM4_BT3_PPG_STC_TGIE                     *((volatile  uint8_t *)(0x424A1A18UL))

#define bFM_BT3_PPG_TMCR_STRG                     *((volatile  uint8_t *)(0x424A1980UL))
#define bFM4_BT3_PPG_TMCR_STRG                    *((volatile  uint8_t *)(0x424A1980UL))
#define bFM_BT3_PPG_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A1984UL))
#define bFM4_BT3_PPG_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A1984UL))
#define bFM_BT3_PPG_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A1988UL))
#define bFM4_BT3_PPG_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A1988UL))
#define bFM_BT3_PPG_TMCR_OSEL                     *((volatile  uint8_t *)(0x424A198CUL))
#define bFM4_BT3_PPG_TMCR_OSEL                    *((volatile  uint8_t *)(0x424A198CUL))
#define bFM_BT3_PPG_TMCR_PMSK                     *((volatile  uint8_t *)(0x424A19A8UL))
#define bFM4_BT3_PPG_TMCR_PMSK                    *((volatile  uint8_t *)(0x424A19A8UL))
#define bFM_BT3_PPG_TMCR_RTGEN                    *((volatile  uint8_t *)(0x424A19ACUL))
#define bFM4_BT3_PPG_TMCR_RTGEN                   *((volatile  uint8_t *)(0x424A19ACUL))

#define bFM_BT3_PPG_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A1A20UL))
#define bFM4_BT3_PPG_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A1A20UL))

#define bFM_BT3_PWC_STC_OVIR                      *((volatile  uint8_t *)(0x424A1A00UL))
#define bFM4_BT3_PWC_STC_OVIR                     *((volatile  uint8_t *)(0x424A1A00UL))
#define bFM_BT3_PWC_STC_EDIR                      *((volatile  uint8_t *)(0x424A1A08UL))
#define bFM4_BT3_PWC_STC_EDIR                     *((volatile  uint8_t *)(0x424A1A08UL))
#define bFM_BT3_PWC_STC_OVIE                      *((volatile  uint8_t *)(0x424A1A10UL))
#define bFM4_BT3_PWC_STC_OVIE                     *((volatile  uint8_t *)(0x424A1A10UL))
#define bFM_BT3_PWC_STC_EDIE                      *((volatile  uint8_t *)(0x424A1A18UL))
#define bFM4_BT3_PWC_STC_EDIE                     *((volatile  uint8_t *)(0x424A1A18UL))
#define bFM_BT3_PWC_STC_ERR                       *((volatile  uint8_t *)(0x424A1A1CUL))
#define bFM4_BT3_PWC_STC_ERR                      *((volatile  uint8_t *)(0x424A1A1CUL))

#define bFM_BT3_PWC_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A1984UL))
#define bFM4_BT3_PWC_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A1984UL))
#define bFM_BT3_PWC_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A1988UL))
#define bFM4_BT3_PWC_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A1988UL))
#define bFM_BT3_PWC_TMCR_T32                      *((volatile  uint8_t *)(0x424A199CUL))
#define bFM4_BT3_PWC_TMCR_T32                     *((volatile  uint8_t *)(0x424A199CUL))

#define bFM_BT3_PWC_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A1A20UL))
#define bFM4_BT3_PWC_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A1A20UL))

#define bFM_BT3_PWM_STC_UDIR                      *((volatile  uint8_t *)(0x424A1A00UL))
#define bFM4_BT3_PWM_STC_UDIR                     *((volatile  uint8_t *)(0x424A1A00UL))
#define bFM_BT3_PWM_STC_DTIR                      *((volatile  uint8_t *)(0x424A1A04UL))
#define bFM4_BT3_PWM_STC_DTIR                     *((volatile  uint8_t *)(0x424A1A04UL))
#define bFM_BT3_PWM_STC_TGIR                      *((volatile  uint8_t *)(0x424A1A08UL))
#define bFM4_BT3_PWM_STC_TGIR                     *((volatile  uint8_t *)(0x424A1A08UL))
#define bFM_BT3_PWM_STC_UDIE                      *((volatile  uint8_t *)(0x424A1A10UL))
#define bFM4_BT3_PWM_STC_UDIE                     *((volatile  uint8_t *)(0x424A1A10UL))
#define bFM_BT3_PWM_STC_DTIE                      *((volatile  uint8_t *)(0x424A1A14UL))
#define bFM4_BT3_PWM_STC_DTIE                     *((volatile  uint8_t *)(0x424A1A14UL))
#define bFM_BT3_PWM_STC_TGIE                      *((volatile  uint8_t *)(0x424A1A18UL))
#define bFM4_BT3_PWM_STC_TGIE                     *((volatile  uint8_t *)(0x424A1A18UL))

#define bFM_BT3_PWM_TMCR_STRG                     *((volatile  uint8_t *)(0x424A1980UL))
#define bFM4_BT3_PWM_TMCR_STRG                    *((volatile  uint8_t *)(0x424A1980UL))
#define bFM_BT3_PWM_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A1984UL))
#define bFM4_BT3_PWM_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A1984UL))
#define bFM_BT3_PWM_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A1988UL))
#define bFM4_BT3_PWM_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A1988UL))
#define bFM_BT3_PWM_TMCR_OSEL                     *((volatile  uint8_t *)(0x424A198CUL))
#define bFM4_BT3_PWM_TMCR_OSEL                    *((volatile  uint8_t *)(0x424A198CUL))
#define bFM_BT3_PWM_TMCR_PMSK                     *((volatile  uint8_t *)(0x424A19A8UL))
#define bFM4_BT3_PWM_TMCR_PMSK                    *((volatile  uint8_t *)(0x424A19A8UL))
#define bFM_BT3_PWM_TMCR_RTGEN                    *((volatile  uint8_t *)(0x424A19ACUL))
#define bFM4_BT3_PWM_TMCR_RTGEN                   *((volatile  uint8_t *)(0x424A19ACUL))

#define bFM_BT3_PWM_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A1A20UL))
#define bFM4_BT3_PWM_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A1A20UL))

#define bFM_BT3_RT_STC_UDIR                       *((volatile  uint8_t *)(0x424A1A00UL))
#define bFM4_BT3_RT_STC_UDIR                      *((volatile  uint8_t *)(0x424A1A00UL))
#define bFM_BT3_RT_STC_TGIR                       *((volatile  uint8_t *)(0x424A1A08UL))
#define bFM4_BT3_RT_STC_TGIR                      *((volatile  uint8_t *)(0x424A1A08UL))
#define bFM_BT3_RT_STC_UDIE                       *((volatile  uint8_t *)(0x424A1A10UL))
#define bFM4_BT3_RT_STC_UDIE                      *((volatile  uint8_t *)(0x424A1A10UL))
#define bFM_BT3_RT_STC_TGIE                       *((volatile  uint8_t *)(0x424A1A18UL))
#define bFM4_BT3_RT_STC_TGIE                      *((volatile  uint8_t *)(0x424A1A18UL))

#define bFM_BT3_RT_TMCR_STRG                      *((volatile  uint8_t *)(0x424A1980UL))
#define bFM4_BT3_RT_TMCR_STRG                     *((volatile  uint8_t *)(0x424A1980UL))
#define bFM_BT3_RT_TMCR_CTEN                      *((volatile  uint8_t *)(0x424A1984UL))
#define bFM4_BT3_RT_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A1984UL))
#define bFM_BT3_RT_TMCR_MDSE                      *((volatile  uint8_t *)(0x424A1988UL))
#define bFM4_BT3_RT_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A1988UL))
#define bFM_BT3_RT_TMCR_OSEL                      *((volatile  uint8_t *)(0x424A198CUL))
#define bFM4_BT3_RT_TMCR_OSEL                     *((volatile  uint8_t *)(0x424A198CUL))
#define bFM_BT3_RT_TMCR_T32                       *((volatile  uint8_t *)(0x424A199CUL))
#define bFM4_BT3_RT_TMCR_T32                      *((volatile  uint8_t *)(0x424A199CUL))

#define bFM_BT3_RT_TMCR2_CKS3                     *((volatile  uint8_t *)(0x424A1A20UL))
#define bFM4_BT3_RT_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A1A20UL))
#define bFM_BT3_RT_TMCR2_GATE                     *((volatile  uint8_t *)(0x424A1A3CUL))
#define bFM4_BT3_RT_TMCR2_GATE                    *((volatile  uint8_t *)(0x424A1A3CUL))


/*******************************************************************************
* BT Registers BT4
*   Bitband Section
*******************************************************************************/
#define bFM_BT4_PPG_STC_UDIR                      *((volatile  uint8_t *)(0x424A4200UL))
#define bFM4_BT4_PPG_STC_UDIR                     *((volatile  uint8_t *)(0x424A4200UL))
#define bFM_BT4_PPG_STC_TGIR                      *((volatile  uint8_t *)(0x424A4208UL))
#define bFM4_BT4_PPG_STC_TGIR                     *((volatile  uint8_t *)(0x424A4208UL))
#define bFM_BT4_PPG_STC_UDIE                      *((volatile  uint8_t *)(0x424A4210UL))
#define bFM4_BT4_PPG_STC_UDIE                     *((volatile  uint8_t *)(0x424A4210UL))
#define bFM_BT4_PPG_STC_TGIE                      *((volatile  uint8_t *)(0x424A4218UL))
#define bFM4_BT4_PPG_STC_TGIE                     *((volatile  uint8_t *)(0x424A4218UL))

#define bFM_BT4_PPG_TMCR_STRG                     *((volatile  uint8_t *)(0x424A4180UL))
#define bFM4_BT4_PPG_TMCR_STRG                    *((volatile  uint8_t *)(0x424A4180UL))
#define bFM_BT4_PPG_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A4184UL))
#define bFM4_BT4_PPG_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A4184UL))
#define bFM_BT4_PPG_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A4188UL))
#define bFM4_BT4_PPG_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A4188UL))
#define bFM_BT4_PPG_TMCR_OSEL                     *((volatile  uint8_t *)(0x424A418CUL))
#define bFM4_BT4_PPG_TMCR_OSEL                    *((volatile  uint8_t *)(0x424A418CUL))
#define bFM_BT4_PPG_TMCR_PMSK                     *((volatile  uint8_t *)(0x424A41A8UL))
#define bFM4_BT4_PPG_TMCR_PMSK                    *((volatile  uint8_t *)(0x424A41A8UL))
#define bFM_BT4_PPG_TMCR_RTGEN                    *((volatile  uint8_t *)(0x424A41ACUL))
#define bFM4_BT4_PPG_TMCR_RTGEN                   *((volatile  uint8_t *)(0x424A41ACUL))

#define bFM_BT4_PPG_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A4220UL))
#define bFM4_BT4_PPG_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A4220UL))

#define bFM_BT4_PWC_STC_OVIR                      *((volatile  uint8_t *)(0x424A4200UL))
#define bFM4_BT4_PWC_STC_OVIR                     *((volatile  uint8_t *)(0x424A4200UL))
#define bFM_BT4_PWC_STC_EDIR                      *((volatile  uint8_t *)(0x424A4208UL))
#define bFM4_BT4_PWC_STC_EDIR                     *((volatile  uint8_t *)(0x424A4208UL))
#define bFM_BT4_PWC_STC_OVIE                      *((volatile  uint8_t *)(0x424A4210UL))
#define bFM4_BT4_PWC_STC_OVIE                     *((volatile  uint8_t *)(0x424A4210UL))
#define bFM_BT4_PWC_STC_EDIE                      *((volatile  uint8_t *)(0x424A4218UL))
#define bFM4_BT4_PWC_STC_EDIE                     *((volatile  uint8_t *)(0x424A4218UL))
#define bFM_BT4_PWC_STC_ERR                       *((volatile  uint8_t *)(0x424A421CUL))
#define bFM4_BT4_PWC_STC_ERR                      *((volatile  uint8_t *)(0x424A421CUL))

#define bFM_BT4_PWC_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A4184UL))
#define bFM4_BT4_PWC_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A4184UL))
#define bFM_BT4_PWC_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A4188UL))
#define bFM4_BT4_PWC_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A4188UL))
#define bFM_BT4_PWC_TMCR_T32                      *((volatile  uint8_t *)(0x424A419CUL))
#define bFM4_BT4_PWC_TMCR_T32                     *((volatile  uint8_t *)(0x424A419CUL))

#define bFM_BT4_PWC_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A4220UL))
#define bFM4_BT4_PWC_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A4220UL))

#define bFM_BT4_PWM_STC_UDIR                      *((volatile  uint8_t *)(0x424A4200UL))
#define bFM4_BT4_PWM_STC_UDIR                     *((volatile  uint8_t *)(0x424A4200UL))
#define bFM_BT4_PWM_STC_DTIR                      *((volatile  uint8_t *)(0x424A4204UL))
#define bFM4_BT4_PWM_STC_DTIR                     *((volatile  uint8_t *)(0x424A4204UL))
#define bFM_BT4_PWM_STC_TGIR                      *((volatile  uint8_t *)(0x424A4208UL))
#define bFM4_BT4_PWM_STC_TGIR                     *((volatile  uint8_t *)(0x424A4208UL))
#define bFM_BT4_PWM_STC_UDIE                      *((volatile  uint8_t *)(0x424A4210UL))
#define bFM4_BT4_PWM_STC_UDIE                     *((volatile  uint8_t *)(0x424A4210UL))
#define bFM_BT4_PWM_STC_DTIE                      *((volatile  uint8_t *)(0x424A4214UL))
#define bFM4_BT4_PWM_STC_DTIE                     *((volatile  uint8_t *)(0x424A4214UL))
#define bFM_BT4_PWM_STC_TGIE                      *((volatile  uint8_t *)(0x424A4218UL))
#define bFM4_BT4_PWM_STC_TGIE                     *((volatile  uint8_t *)(0x424A4218UL))

#define bFM_BT4_PWM_TMCR_STRG                     *((volatile  uint8_t *)(0x424A4180UL))
#define bFM4_BT4_PWM_TMCR_STRG                    *((volatile  uint8_t *)(0x424A4180UL))
#define bFM_BT4_PWM_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A4184UL))
#define bFM4_BT4_PWM_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A4184UL))
#define bFM_BT4_PWM_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A4188UL))
#define bFM4_BT4_PWM_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A4188UL))
#define bFM_BT4_PWM_TMCR_OSEL                     *((volatile  uint8_t *)(0x424A418CUL))
#define bFM4_BT4_PWM_TMCR_OSEL                    *((volatile  uint8_t *)(0x424A418CUL))
#define bFM_BT4_PWM_TMCR_PMSK                     *((volatile  uint8_t *)(0x424A41A8UL))
#define bFM4_BT4_PWM_TMCR_PMSK                    *((volatile  uint8_t *)(0x424A41A8UL))
#define bFM_BT4_PWM_TMCR_RTGEN                    *((volatile  uint8_t *)(0x424A41ACUL))
#define bFM4_BT4_PWM_TMCR_RTGEN                   *((volatile  uint8_t *)(0x424A41ACUL))

#define bFM_BT4_PWM_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A4220UL))
#define bFM4_BT4_PWM_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A4220UL))

#define bFM_BT4_RT_STC_UDIR                       *((volatile  uint8_t *)(0x424A4200UL))
#define bFM4_BT4_RT_STC_UDIR                      *((volatile  uint8_t *)(0x424A4200UL))
#define bFM_BT4_RT_STC_TGIR                       *((volatile  uint8_t *)(0x424A4208UL))
#define bFM4_BT4_RT_STC_TGIR                      *((volatile  uint8_t *)(0x424A4208UL))
#define bFM_BT4_RT_STC_UDIE                       *((volatile  uint8_t *)(0x424A4210UL))
#define bFM4_BT4_RT_STC_UDIE                      *((volatile  uint8_t *)(0x424A4210UL))
#define bFM_BT4_RT_STC_TGIE                       *((volatile  uint8_t *)(0x424A4218UL))
#define bFM4_BT4_RT_STC_TGIE                      *((volatile  uint8_t *)(0x424A4218UL))

#define bFM_BT4_RT_TMCR_STRG                      *((volatile  uint8_t *)(0x424A4180UL))
#define bFM4_BT4_RT_TMCR_STRG                     *((volatile  uint8_t *)(0x424A4180UL))
#define bFM_BT4_RT_TMCR_CTEN                      *((volatile  uint8_t *)(0x424A4184UL))
#define bFM4_BT4_RT_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A4184UL))
#define bFM_BT4_RT_TMCR_MDSE                      *((volatile  uint8_t *)(0x424A4188UL))
#define bFM4_BT4_RT_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A4188UL))
#define bFM_BT4_RT_TMCR_OSEL                      *((volatile  uint8_t *)(0x424A418CUL))
#define bFM4_BT4_RT_TMCR_OSEL                     *((volatile  uint8_t *)(0x424A418CUL))
#define bFM_BT4_RT_TMCR_T32                       *((volatile  uint8_t *)(0x424A419CUL))
#define bFM4_BT4_RT_TMCR_T32                      *((volatile  uint8_t *)(0x424A419CUL))

#define bFM_BT4_RT_TMCR2_CKS3                     *((volatile  uint8_t *)(0x424A4220UL))
#define bFM4_BT4_RT_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A4220UL))
#define bFM_BT4_RT_TMCR2_GATE                     *((volatile  uint8_t *)(0x424A423CUL))
#define bFM4_BT4_RT_TMCR2_GATE                    *((volatile  uint8_t *)(0x424A423CUL))


/*******************************************************************************
* BT Registers BT5
*   Bitband Section
*******************************************************************************/
#define bFM_BT5_PPG_STC_UDIR                      *((volatile  uint8_t *)(0x424A4A00UL))
#define bFM4_BT5_PPG_STC_UDIR                     *((volatile  uint8_t *)(0x424A4A00UL))
#define bFM_BT5_PPG_STC_TGIR                      *((volatile  uint8_t *)(0x424A4A08UL))
#define bFM4_BT5_PPG_STC_TGIR                     *((volatile  uint8_t *)(0x424A4A08UL))
#define bFM_BT5_PPG_STC_UDIE                      *((volatile  uint8_t *)(0x424A4A10UL))
#define bFM4_BT5_PPG_STC_UDIE                     *((volatile  uint8_t *)(0x424A4A10UL))
#define bFM_BT5_PPG_STC_TGIE                      *((volatile  uint8_t *)(0x424A4A18UL))
#define bFM4_BT5_PPG_STC_TGIE                     *((volatile  uint8_t *)(0x424A4A18UL))

#define bFM_BT5_PPG_TMCR_STRG                     *((volatile  uint8_t *)(0x424A4980UL))
#define bFM4_BT5_PPG_TMCR_STRG                    *((volatile  uint8_t *)(0x424A4980UL))
#define bFM_BT5_PPG_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A4984UL))
#define bFM4_BT5_PPG_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A4984UL))
#define bFM_BT5_PPG_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A4988UL))
#define bFM4_BT5_PPG_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A4988UL))
#define bFM_BT5_PPG_TMCR_OSEL                     *((volatile  uint8_t *)(0x424A498CUL))
#define bFM4_BT5_PPG_TMCR_OSEL                    *((volatile  uint8_t *)(0x424A498CUL))
#define bFM_BT5_PPG_TMCR_PMSK                     *((volatile  uint8_t *)(0x424A49A8UL))
#define bFM4_BT5_PPG_TMCR_PMSK                    *((volatile  uint8_t *)(0x424A49A8UL))
#define bFM_BT5_PPG_TMCR_RTGEN                    *((volatile  uint8_t *)(0x424A49ACUL))
#define bFM4_BT5_PPG_TMCR_RTGEN                   *((volatile  uint8_t *)(0x424A49ACUL))

#define bFM_BT5_PPG_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A4A20UL))
#define bFM4_BT5_PPG_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A4A20UL))

#define bFM_BT5_PWC_STC_OVIR                      *((volatile  uint8_t *)(0x424A4A00UL))
#define bFM4_BT5_PWC_STC_OVIR                     *((volatile  uint8_t *)(0x424A4A00UL))
#define bFM_BT5_PWC_STC_EDIR                      *((volatile  uint8_t *)(0x424A4A08UL))
#define bFM4_BT5_PWC_STC_EDIR                     *((volatile  uint8_t *)(0x424A4A08UL))
#define bFM_BT5_PWC_STC_OVIE                      *((volatile  uint8_t *)(0x424A4A10UL))
#define bFM4_BT5_PWC_STC_OVIE                     *((volatile  uint8_t *)(0x424A4A10UL))
#define bFM_BT5_PWC_STC_EDIE                      *((volatile  uint8_t *)(0x424A4A18UL))
#define bFM4_BT5_PWC_STC_EDIE                     *((volatile  uint8_t *)(0x424A4A18UL))
#define bFM_BT5_PWC_STC_ERR                       *((volatile  uint8_t *)(0x424A4A1CUL))
#define bFM4_BT5_PWC_STC_ERR                      *((volatile  uint8_t *)(0x424A4A1CUL))

#define bFM_BT5_PWC_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A4984UL))
#define bFM4_BT5_PWC_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A4984UL))
#define bFM_BT5_PWC_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A4988UL))
#define bFM4_BT5_PWC_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A4988UL))
#define bFM_BT5_PWC_TMCR_T32                      *((volatile  uint8_t *)(0x424A499CUL))
#define bFM4_BT5_PWC_TMCR_T32                     *((volatile  uint8_t *)(0x424A499CUL))

#define bFM_BT5_PWC_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A4A20UL))
#define bFM4_BT5_PWC_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A4A20UL))

#define bFM_BT5_PWM_STC_UDIR                      *((volatile  uint8_t *)(0x424A4A00UL))
#define bFM4_BT5_PWM_STC_UDIR                     *((volatile  uint8_t *)(0x424A4A00UL))
#define bFM_BT5_PWM_STC_DTIR                      *((volatile  uint8_t *)(0x424A4A04UL))
#define bFM4_BT5_PWM_STC_DTIR                     *((volatile  uint8_t *)(0x424A4A04UL))
#define bFM_BT5_PWM_STC_TGIR                      *((volatile  uint8_t *)(0x424A4A08UL))
#define bFM4_BT5_PWM_STC_TGIR                     *((volatile  uint8_t *)(0x424A4A08UL))
#define bFM_BT5_PWM_STC_UDIE                      *((volatile  uint8_t *)(0x424A4A10UL))
#define bFM4_BT5_PWM_STC_UDIE                     *((volatile  uint8_t *)(0x424A4A10UL))
#define bFM_BT5_PWM_STC_DTIE                      *((volatile  uint8_t *)(0x424A4A14UL))
#define bFM4_BT5_PWM_STC_DTIE                     *((volatile  uint8_t *)(0x424A4A14UL))
#define bFM_BT5_PWM_STC_TGIE                      *((volatile  uint8_t *)(0x424A4A18UL))
#define bFM4_BT5_PWM_STC_TGIE                     *((volatile  uint8_t *)(0x424A4A18UL))

#define bFM_BT5_PWM_TMCR_STRG                     *((volatile  uint8_t *)(0x424A4980UL))
#define bFM4_BT5_PWM_TMCR_STRG                    *((volatile  uint8_t *)(0x424A4980UL))
#define bFM_BT5_PWM_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A4984UL))
#define bFM4_BT5_PWM_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A4984UL))
#define bFM_BT5_PWM_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A4988UL))
#define bFM4_BT5_PWM_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A4988UL))
#define bFM_BT5_PWM_TMCR_OSEL                     *((volatile  uint8_t *)(0x424A498CUL))
#define bFM4_BT5_PWM_TMCR_OSEL                    *((volatile  uint8_t *)(0x424A498CUL))
#define bFM_BT5_PWM_TMCR_PMSK                     *((volatile  uint8_t *)(0x424A49A8UL))
#define bFM4_BT5_PWM_TMCR_PMSK                    *((volatile  uint8_t *)(0x424A49A8UL))
#define bFM_BT5_PWM_TMCR_RTGEN                    *((volatile  uint8_t *)(0x424A49ACUL))
#define bFM4_BT5_PWM_TMCR_RTGEN                   *((volatile  uint8_t *)(0x424A49ACUL))

#define bFM_BT5_PWM_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A4A20UL))
#define bFM4_BT5_PWM_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A4A20UL))

#define bFM_BT5_RT_STC_UDIR                       *((volatile  uint8_t *)(0x424A4A00UL))
#define bFM4_BT5_RT_STC_UDIR                      *((volatile  uint8_t *)(0x424A4A00UL))
#define bFM_BT5_RT_STC_TGIR                       *((volatile  uint8_t *)(0x424A4A08UL))
#define bFM4_BT5_RT_STC_TGIR                      *((volatile  uint8_t *)(0x424A4A08UL))
#define bFM_BT5_RT_STC_UDIE                       *((volatile  uint8_t *)(0x424A4A10UL))
#define bFM4_BT5_RT_STC_UDIE                      *((volatile  uint8_t *)(0x424A4A10UL))
#define bFM_BT5_RT_STC_TGIE                       *((volatile  uint8_t *)(0x424A4A18UL))
#define bFM4_BT5_RT_STC_TGIE                      *((volatile  uint8_t *)(0x424A4A18UL))

#define bFM_BT5_RT_TMCR_STRG                      *((volatile  uint8_t *)(0x424A4980UL))
#define bFM4_BT5_RT_TMCR_STRG                     *((volatile  uint8_t *)(0x424A4980UL))
#define bFM_BT5_RT_TMCR_CTEN                      *((volatile  uint8_t *)(0x424A4984UL))
#define bFM4_BT5_RT_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A4984UL))
#define bFM_BT5_RT_TMCR_MDSE                      *((volatile  uint8_t *)(0x424A4988UL))
#define bFM4_BT5_RT_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A4988UL))
#define bFM_BT5_RT_TMCR_OSEL                      *((volatile  uint8_t *)(0x424A498CUL))
#define bFM4_BT5_RT_TMCR_OSEL                     *((volatile  uint8_t *)(0x424A498CUL))
#define bFM_BT5_RT_TMCR_T32                       *((volatile  uint8_t *)(0x424A499CUL))
#define bFM4_BT5_RT_TMCR_T32                      *((volatile  uint8_t *)(0x424A499CUL))

#define bFM_BT5_RT_TMCR2_CKS3                     *((volatile  uint8_t *)(0x424A4A20UL))
#define bFM4_BT5_RT_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A4A20UL))
#define bFM_BT5_RT_TMCR2_GATE                     *((volatile  uint8_t *)(0x424A4A3CUL))
#define bFM4_BT5_RT_TMCR2_GATE                    *((volatile  uint8_t *)(0x424A4A3CUL))


/*******************************************************************************
* BT Registers BT6
*   Bitband Section
*******************************************************************************/
#define bFM_BT6_PPG_STC_UDIR                      *((volatile  uint8_t *)(0x424A5200UL))
#define bFM4_BT6_PPG_STC_UDIR                     *((volatile  uint8_t *)(0x424A5200UL))
#define bFM_BT6_PPG_STC_TGIR                      *((volatile  uint8_t *)(0x424A5208UL))
#define bFM4_BT6_PPG_STC_TGIR                     *((volatile  uint8_t *)(0x424A5208UL))
#define bFM_BT6_PPG_STC_UDIE                      *((volatile  uint8_t *)(0x424A5210UL))
#define bFM4_BT6_PPG_STC_UDIE                     *((volatile  uint8_t *)(0x424A5210UL))
#define bFM_BT6_PPG_STC_TGIE                      *((volatile  uint8_t *)(0x424A5218UL))
#define bFM4_BT6_PPG_STC_TGIE                     *((volatile  uint8_t *)(0x424A5218UL))

#define bFM_BT6_PPG_TMCR_STRG                     *((volatile  uint8_t *)(0x424A5180UL))
#define bFM4_BT6_PPG_TMCR_STRG                    *((volatile  uint8_t *)(0x424A5180UL))
#define bFM_BT6_PPG_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A5184UL))
#define bFM4_BT6_PPG_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A5184UL))
#define bFM_BT6_PPG_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A5188UL))
#define bFM4_BT6_PPG_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A5188UL))
#define bFM_BT6_PPG_TMCR_OSEL                     *((volatile  uint8_t *)(0x424A518CUL))
#define bFM4_BT6_PPG_TMCR_OSEL                    *((volatile  uint8_t *)(0x424A518CUL))
#define bFM_BT6_PPG_TMCR_PMSK                     *((volatile  uint8_t *)(0x424A51A8UL))
#define bFM4_BT6_PPG_TMCR_PMSK                    *((volatile  uint8_t *)(0x424A51A8UL))
#define bFM_BT6_PPG_TMCR_RTGEN                    *((volatile  uint8_t *)(0x424A51ACUL))
#define bFM4_BT6_PPG_TMCR_RTGEN                   *((volatile  uint8_t *)(0x424A51ACUL))

#define bFM_BT6_PPG_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A5220UL))
#define bFM4_BT6_PPG_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A5220UL))

#define bFM_BT6_PWC_STC_OVIR                      *((volatile  uint8_t *)(0x424A5200UL))
#define bFM4_BT6_PWC_STC_OVIR                     *((volatile  uint8_t *)(0x424A5200UL))
#define bFM_BT6_PWC_STC_EDIR                      *((volatile  uint8_t *)(0x424A5208UL))
#define bFM4_BT6_PWC_STC_EDIR                     *((volatile  uint8_t *)(0x424A5208UL))
#define bFM_BT6_PWC_STC_OVIE                      *((volatile  uint8_t *)(0x424A5210UL))
#define bFM4_BT6_PWC_STC_OVIE                     *((volatile  uint8_t *)(0x424A5210UL))
#define bFM_BT6_PWC_STC_EDIE                      *((volatile  uint8_t *)(0x424A5218UL))
#define bFM4_BT6_PWC_STC_EDIE                     *((volatile  uint8_t *)(0x424A5218UL))
#define bFM_BT6_PWC_STC_ERR                       *((volatile  uint8_t *)(0x424A521CUL))
#define bFM4_BT6_PWC_STC_ERR                      *((volatile  uint8_t *)(0x424A521CUL))

#define bFM_BT6_PWC_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A5184UL))
#define bFM4_BT6_PWC_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A5184UL))
#define bFM_BT6_PWC_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A5188UL))
#define bFM4_BT6_PWC_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A5188UL))
#define bFM_BT6_PWC_TMCR_T32                      *((volatile  uint8_t *)(0x424A519CUL))
#define bFM4_BT6_PWC_TMCR_T32                     *((volatile  uint8_t *)(0x424A519CUL))

#define bFM_BT6_PWC_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A5220UL))
#define bFM4_BT6_PWC_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A5220UL))

#define bFM_BT6_PWM_STC_UDIR                      *((volatile  uint8_t *)(0x424A5200UL))
#define bFM4_BT6_PWM_STC_UDIR                     *((volatile  uint8_t *)(0x424A5200UL))
#define bFM_BT6_PWM_STC_DTIR                      *((volatile  uint8_t *)(0x424A5204UL))
#define bFM4_BT6_PWM_STC_DTIR                     *((volatile  uint8_t *)(0x424A5204UL))
#define bFM_BT6_PWM_STC_TGIR                      *((volatile  uint8_t *)(0x424A5208UL))
#define bFM4_BT6_PWM_STC_TGIR                     *((volatile  uint8_t *)(0x424A5208UL))
#define bFM_BT6_PWM_STC_UDIE                      *((volatile  uint8_t *)(0x424A5210UL))
#define bFM4_BT6_PWM_STC_UDIE                     *((volatile  uint8_t *)(0x424A5210UL))
#define bFM_BT6_PWM_STC_DTIE                      *((volatile  uint8_t *)(0x424A5214UL))
#define bFM4_BT6_PWM_STC_DTIE                     *((volatile  uint8_t *)(0x424A5214UL))
#define bFM_BT6_PWM_STC_TGIE                      *((volatile  uint8_t *)(0x424A5218UL))
#define bFM4_BT6_PWM_STC_TGIE                     *((volatile  uint8_t *)(0x424A5218UL))

#define bFM_BT6_PWM_TMCR_STRG                     *((volatile  uint8_t *)(0x424A5180UL))
#define bFM4_BT6_PWM_TMCR_STRG                    *((volatile  uint8_t *)(0x424A5180UL))
#define bFM_BT6_PWM_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A5184UL))
#define bFM4_BT6_PWM_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A5184UL))
#define bFM_BT6_PWM_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A5188UL))
#define bFM4_BT6_PWM_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A5188UL))
#define bFM_BT6_PWM_TMCR_OSEL                     *((volatile  uint8_t *)(0x424A518CUL))
#define bFM4_BT6_PWM_TMCR_OSEL                    *((volatile  uint8_t *)(0x424A518CUL))
#define bFM_BT6_PWM_TMCR_PMSK                     *((volatile  uint8_t *)(0x424A51A8UL))
#define bFM4_BT6_PWM_TMCR_PMSK                    *((volatile  uint8_t *)(0x424A51A8UL))
#define bFM_BT6_PWM_TMCR_RTGEN                    *((volatile  uint8_t *)(0x424A51ACUL))
#define bFM4_BT6_PWM_TMCR_RTGEN                   *((volatile  uint8_t *)(0x424A51ACUL))

#define bFM_BT6_PWM_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A5220UL))
#define bFM4_BT6_PWM_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A5220UL))

#define bFM_BT6_RT_STC_UDIR                       *((volatile  uint8_t *)(0x424A5200UL))
#define bFM4_BT6_RT_STC_UDIR                      *((volatile  uint8_t *)(0x424A5200UL))
#define bFM_BT6_RT_STC_TGIR                       *((volatile  uint8_t *)(0x424A5208UL))
#define bFM4_BT6_RT_STC_TGIR                      *((volatile  uint8_t *)(0x424A5208UL))
#define bFM_BT6_RT_STC_UDIE                       *((volatile  uint8_t *)(0x424A5210UL))
#define bFM4_BT6_RT_STC_UDIE                      *((volatile  uint8_t *)(0x424A5210UL))
#define bFM_BT6_RT_STC_TGIE                       *((volatile  uint8_t *)(0x424A5218UL))
#define bFM4_BT6_RT_STC_TGIE                      *((volatile  uint8_t *)(0x424A5218UL))

#define bFM_BT6_RT_TMCR_STRG                      *((volatile  uint8_t *)(0x424A5180UL))
#define bFM4_BT6_RT_TMCR_STRG                     *((volatile  uint8_t *)(0x424A5180UL))
#define bFM_BT6_RT_TMCR_CTEN                      *((volatile  uint8_t *)(0x424A5184UL))
#define bFM4_BT6_RT_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A5184UL))
#define bFM_BT6_RT_TMCR_MDSE                      *((volatile  uint8_t *)(0x424A5188UL))
#define bFM4_BT6_RT_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A5188UL))
#define bFM_BT6_RT_TMCR_OSEL                      *((volatile  uint8_t *)(0x424A518CUL))
#define bFM4_BT6_RT_TMCR_OSEL                     *((volatile  uint8_t *)(0x424A518CUL))
#define bFM_BT6_RT_TMCR_T32                       *((volatile  uint8_t *)(0x424A519CUL))
#define bFM4_BT6_RT_TMCR_T32                      *((volatile  uint8_t *)(0x424A519CUL))

#define bFM_BT6_RT_TMCR2_CKS3                     *((volatile  uint8_t *)(0x424A5220UL))
#define bFM4_BT6_RT_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A5220UL))
#define bFM_BT6_RT_TMCR2_GATE                     *((volatile  uint8_t *)(0x424A523CUL))
#define bFM4_BT6_RT_TMCR2_GATE                    *((volatile  uint8_t *)(0x424A523CUL))


/*******************************************************************************
* BT Registers BT7
*   Bitband Section
*******************************************************************************/
#define bFM_BT7_PPG_STC_UDIR                      *((volatile  uint8_t *)(0x424A5A00UL))
#define bFM4_BT7_PPG_STC_UDIR                     *((volatile  uint8_t *)(0x424A5A00UL))
#define bFM_BT7_PPG_STC_TGIR                      *((volatile  uint8_t *)(0x424A5A08UL))
#define bFM4_BT7_PPG_STC_TGIR                     *((volatile  uint8_t *)(0x424A5A08UL))
#define bFM_BT7_PPG_STC_UDIE                      *((volatile  uint8_t *)(0x424A5A10UL))
#define bFM4_BT7_PPG_STC_UDIE                     *((volatile  uint8_t *)(0x424A5A10UL))
#define bFM_BT7_PPG_STC_TGIE                      *((volatile  uint8_t *)(0x424A5A18UL))
#define bFM4_BT7_PPG_STC_TGIE                     *((volatile  uint8_t *)(0x424A5A18UL))

#define bFM_BT7_PPG_TMCR_STRG                     *((volatile  uint8_t *)(0x424A5980UL))
#define bFM4_BT7_PPG_TMCR_STRG                    *((volatile  uint8_t *)(0x424A5980UL))
#define bFM_BT7_PPG_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A5984UL))
#define bFM4_BT7_PPG_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A5984UL))
#define bFM_BT7_PPG_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A5988UL))
#define bFM4_BT7_PPG_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A5988UL))
#define bFM_BT7_PPG_TMCR_OSEL                     *((volatile  uint8_t *)(0x424A598CUL))
#define bFM4_BT7_PPG_TMCR_OSEL                    *((volatile  uint8_t *)(0x424A598CUL))
#define bFM_BT7_PPG_TMCR_PMSK                     *((volatile  uint8_t *)(0x424A59A8UL))
#define bFM4_BT7_PPG_TMCR_PMSK                    *((volatile  uint8_t *)(0x424A59A8UL))
#define bFM_BT7_PPG_TMCR_RTGEN                    *((volatile  uint8_t *)(0x424A59ACUL))
#define bFM4_BT7_PPG_TMCR_RTGEN                   *((volatile  uint8_t *)(0x424A59ACUL))

#define bFM_BT7_PPG_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A5A20UL))
#define bFM4_BT7_PPG_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A5A20UL))

#define bFM_BT7_PWC_STC_OVIR                      *((volatile  uint8_t *)(0x424A5A00UL))
#define bFM4_BT7_PWC_STC_OVIR                     *((volatile  uint8_t *)(0x424A5A00UL))
#define bFM_BT7_PWC_STC_EDIR                      *((volatile  uint8_t *)(0x424A5A08UL))
#define bFM4_BT7_PWC_STC_EDIR                     *((volatile  uint8_t *)(0x424A5A08UL))
#define bFM_BT7_PWC_STC_OVIE                      *((volatile  uint8_t *)(0x424A5A10UL))
#define bFM4_BT7_PWC_STC_OVIE                     *((volatile  uint8_t *)(0x424A5A10UL))
#define bFM_BT7_PWC_STC_EDIE                      *((volatile  uint8_t *)(0x424A5A18UL))
#define bFM4_BT7_PWC_STC_EDIE                     *((volatile  uint8_t *)(0x424A5A18UL))
#define bFM_BT7_PWC_STC_ERR                       *((volatile  uint8_t *)(0x424A5A1CUL))
#define bFM4_BT7_PWC_STC_ERR                      *((volatile  uint8_t *)(0x424A5A1CUL))

#define bFM_BT7_PWC_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A5984UL))
#define bFM4_BT7_PWC_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A5984UL))
#define bFM_BT7_PWC_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A5988UL))
#define bFM4_BT7_PWC_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A5988UL))
#define bFM_BT7_PWC_TMCR_T32                      *((volatile  uint8_t *)(0x424A599CUL))
#define bFM4_BT7_PWC_TMCR_T32                     *((volatile  uint8_t *)(0x424A599CUL))

#define bFM_BT7_PWC_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A5A20UL))
#define bFM4_BT7_PWC_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A5A20UL))

#define bFM_BT7_PWM_STC_UDIR                      *((volatile  uint8_t *)(0x424A5A00UL))
#define bFM4_BT7_PWM_STC_UDIR                     *((volatile  uint8_t *)(0x424A5A00UL))
#define bFM_BT7_PWM_STC_DTIR                      *((volatile  uint8_t *)(0x424A5A04UL))
#define bFM4_BT7_PWM_STC_DTIR                     *((volatile  uint8_t *)(0x424A5A04UL))
#define bFM_BT7_PWM_STC_TGIR                      *((volatile  uint8_t *)(0x424A5A08UL))
#define bFM4_BT7_PWM_STC_TGIR                     *((volatile  uint8_t *)(0x424A5A08UL))
#define bFM_BT7_PWM_STC_UDIE                      *((volatile  uint8_t *)(0x424A5A10UL))
#define bFM4_BT7_PWM_STC_UDIE                     *((volatile  uint8_t *)(0x424A5A10UL))
#define bFM_BT7_PWM_STC_DTIE                      *((volatile  uint8_t *)(0x424A5A14UL))
#define bFM4_BT7_PWM_STC_DTIE                     *((volatile  uint8_t *)(0x424A5A14UL))
#define bFM_BT7_PWM_STC_TGIE                      *((volatile  uint8_t *)(0x424A5A18UL))
#define bFM4_BT7_PWM_STC_TGIE                     *((volatile  uint8_t *)(0x424A5A18UL))

#define bFM_BT7_PWM_TMCR_STRG                     *((volatile  uint8_t *)(0x424A5980UL))
#define bFM4_BT7_PWM_TMCR_STRG                    *((volatile  uint8_t *)(0x424A5980UL))
#define bFM_BT7_PWM_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A5984UL))
#define bFM4_BT7_PWM_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A5984UL))
#define bFM_BT7_PWM_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A5988UL))
#define bFM4_BT7_PWM_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A5988UL))
#define bFM_BT7_PWM_TMCR_OSEL                     *((volatile  uint8_t *)(0x424A598CUL))
#define bFM4_BT7_PWM_TMCR_OSEL                    *((volatile  uint8_t *)(0x424A598CUL))
#define bFM_BT7_PWM_TMCR_PMSK                     *((volatile  uint8_t *)(0x424A59A8UL))
#define bFM4_BT7_PWM_TMCR_PMSK                    *((volatile  uint8_t *)(0x424A59A8UL))
#define bFM_BT7_PWM_TMCR_RTGEN                    *((volatile  uint8_t *)(0x424A59ACUL))
#define bFM4_BT7_PWM_TMCR_RTGEN                   *((volatile  uint8_t *)(0x424A59ACUL))

#define bFM_BT7_PWM_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A5A20UL))
#define bFM4_BT7_PWM_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A5A20UL))

#define bFM_BT7_RT_STC_UDIR                       *((volatile  uint8_t *)(0x424A5A00UL))
#define bFM4_BT7_RT_STC_UDIR                      *((volatile  uint8_t *)(0x424A5A00UL))
#define bFM_BT7_RT_STC_TGIR                       *((volatile  uint8_t *)(0x424A5A08UL))
#define bFM4_BT7_RT_STC_TGIR                      *((volatile  uint8_t *)(0x424A5A08UL))
#define bFM_BT7_RT_STC_UDIE                       *((volatile  uint8_t *)(0x424A5A10UL))
#define bFM4_BT7_RT_STC_UDIE                      *((volatile  uint8_t *)(0x424A5A10UL))
#define bFM_BT7_RT_STC_TGIE                       *((volatile  uint8_t *)(0x424A5A18UL))
#define bFM4_BT7_RT_STC_TGIE                      *((volatile  uint8_t *)(0x424A5A18UL))

#define bFM_BT7_RT_TMCR_STRG                      *((volatile  uint8_t *)(0x424A5980UL))
#define bFM4_BT7_RT_TMCR_STRG                     *((volatile  uint8_t *)(0x424A5980UL))
#define bFM_BT7_RT_TMCR_CTEN                      *((volatile  uint8_t *)(0x424A5984UL))
#define bFM4_BT7_RT_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A5984UL))
#define bFM_BT7_RT_TMCR_MDSE                      *((volatile  uint8_t *)(0x424A5988UL))
#define bFM4_BT7_RT_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A5988UL))
#define bFM_BT7_RT_TMCR_OSEL                      *((volatile  uint8_t *)(0x424A598CUL))
#define bFM4_BT7_RT_TMCR_OSEL                     *((volatile  uint8_t *)(0x424A598CUL))
#define bFM_BT7_RT_TMCR_T32                       *((volatile  uint8_t *)(0x424A599CUL))
#define bFM4_BT7_RT_TMCR_T32                      *((volatile  uint8_t *)(0x424A599CUL))

#define bFM_BT7_RT_TMCR2_CKS3                     *((volatile  uint8_t *)(0x424A5A20UL))
#define bFM4_BT7_RT_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A5A20UL))
#define bFM_BT7_RT_TMCR2_GATE                     *((volatile  uint8_t *)(0x424A5A3CUL))
#define bFM4_BT7_RT_TMCR2_GATE                    *((volatile  uint8_t *)(0x424A5A3CUL))


/*******************************************************************************
* BT Registers BT8
*   Bitband Section
*******************************************************************************/
#define bFM_BT8_PPG_STC_UDIR                      *((volatile  uint8_t *)(0x424A8200UL))
#define bFM4_BT8_PPG_STC_UDIR                     *((volatile  uint8_t *)(0x424A8200UL))
#define bFM_BT8_PPG_STC_TGIR                      *((volatile  uint8_t *)(0x424A8208UL))
#define bFM4_BT8_PPG_STC_TGIR                     *((volatile  uint8_t *)(0x424A8208UL))
#define bFM_BT8_PPG_STC_UDIE                      *((volatile  uint8_t *)(0x424A8210UL))
#define bFM4_BT8_PPG_STC_UDIE                     *((volatile  uint8_t *)(0x424A8210UL))
#define bFM_BT8_PPG_STC_TGIE                      *((volatile  uint8_t *)(0x424A8218UL))
#define bFM4_BT8_PPG_STC_TGIE                     *((volatile  uint8_t *)(0x424A8218UL))

#define bFM_BT8_PPG_TMCR_STRG                     *((volatile  uint8_t *)(0x424A8180UL))
#define bFM4_BT8_PPG_TMCR_STRG                    *((volatile  uint8_t *)(0x424A8180UL))
#define bFM_BT8_PPG_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A8184UL))
#define bFM4_BT8_PPG_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A8184UL))
#define bFM_BT8_PPG_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A8188UL))
#define bFM4_BT8_PPG_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A8188UL))
#define bFM_BT8_PPG_TMCR_OSEL                     *((volatile  uint8_t *)(0x424A818CUL))
#define bFM4_BT8_PPG_TMCR_OSEL                    *((volatile  uint8_t *)(0x424A818CUL))
#define bFM_BT8_PPG_TMCR_PMSK                     *((volatile  uint8_t *)(0x424A81A8UL))
#define bFM4_BT8_PPG_TMCR_PMSK                    *((volatile  uint8_t *)(0x424A81A8UL))
#define bFM_BT8_PPG_TMCR_RTGEN                    *((volatile  uint8_t *)(0x424A81ACUL))
#define bFM4_BT8_PPG_TMCR_RTGEN                   *((volatile  uint8_t *)(0x424A81ACUL))

#define bFM_BT8_PPG_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A8220UL))
#define bFM4_BT8_PPG_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A8220UL))

#define bFM_BT8_PWC_STC_OVIR                      *((volatile  uint8_t *)(0x424A8200UL))
#define bFM4_BT8_PWC_STC_OVIR                     *((volatile  uint8_t *)(0x424A8200UL))
#define bFM_BT8_PWC_STC_EDIR                      *((volatile  uint8_t *)(0x424A8208UL))
#define bFM4_BT8_PWC_STC_EDIR                     *((volatile  uint8_t *)(0x424A8208UL))
#define bFM_BT8_PWC_STC_OVIE                      *((volatile  uint8_t *)(0x424A8210UL))
#define bFM4_BT8_PWC_STC_OVIE                     *((volatile  uint8_t *)(0x424A8210UL))
#define bFM_BT8_PWC_STC_EDIE                      *((volatile  uint8_t *)(0x424A8218UL))
#define bFM4_BT8_PWC_STC_EDIE                     *((volatile  uint8_t *)(0x424A8218UL))
#define bFM_BT8_PWC_STC_ERR                       *((volatile  uint8_t *)(0x424A821CUL))
#define bFM4_BT8_PWC_STC_ERR                      *((volatile  uint8_t *)(0x424A821CUL))

#define bFM_BT8_PWC_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A8184UL))
#define bFM4_BT8_PWC_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A8184UL))
#define bFM_BT8_PWC_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A8188UL))
#define bFM4_BT8_PWC_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A8188UL))
#define bFM_BT8_PWC_TMCR_T32                      *((volatile  uint8_t *)(0x424A819CUL))
#define bFM4_BT8_PWC_TMCR_T32                     *((volatile  uint8_t *)(0x424A819CUL))

#define bFM_BT8_PWC_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A8220UL))
#define bFM4_BT8_PWC_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A8220UL))

#define bFM_BT8_PWM_STC_UDIR                      *((volatile  uint8_t *)(0x424A8200UL))
#define bFM4_BT8_PWM_STC_UDIR                     *((volatile  uint8_t *)(0x424A8200UL))
#define bFM_BT8_PWM_STC_DTIR                      *((volatile  uint8_t *)(0x424A8204UL))
#define bFM4_BT8_PWM_STC_DTIR                     *((volatile  uint8_t *)(0x424A8204UL))
#define bFM_BT8_PWM_STC_TGIR                      *((volatile  uint8_t *)(0x424A8208UL))
#define bFM4_BT8_PWM_STC_TGIR                     *((volatile  uint8_t *)(0x424A8208UL))
#define bFM_BT8_PWM_STC_UDIE                      *((volatile  uint8_t *)(0x424A8210UL))
#define bFM4_BT8_PWM_STC_UDIE                     *((volatile  uint8_t *)(0x424A8210UL))
#define bFM_BT8_PWM_STC_DTIE                      *((volatile  uint8_t *)(0x424A8214UL))
#define bFM4_BT8_PWM_STC_DTIE                     *((volatile  uint8_t *)(0x424A8214UL))
#define bFM_BT8_PWM_STC_TGIE                      *((volatile  uint8_t *)(0x424A8218UL))
#define bFM4_BT8_PWM_STC_TGIE                     *((volatile  uint8_t *)(0x424A8218UL))

#define bFM_BT8_PWM_TMCR_STRG                     *((volatile  uint8_t *)(0x424A8180UL))
#define bFM4_BT8_PWM_TMCR_STRG                    *((volatile  uint8_t *)(0x424A8180UL))
#define bFM_BT8_PWM_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A8184UL))
#define bFM4_BT8_PWM_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A8184UL))
#define bFM_BT8_PWM_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A8188UL))
#define bFM4_BT8_PWM_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A8188UL))
#define bFM_BT8_PWM_TMCR_OSEL                     *((volatile  uint8_t *)(0x424A818CUL))
#define bFM4_BT8_PWM_TMCR_OSEL                    *((volatile  uint8_t *)(0x424A818CUL))
#define bFM_BT8_PWM_TMCR_PMSK                     *((volatile  uint8_t *)(0x424A81A8UL))
#define bFM4_BT8_PWM_TMCR_PMSK                    *((volatile  uint8_t *)(0x424A81A8UL))
#define bFM_BT8_PWM_TMCR_RTGEN                    *((volatile  uint8_t *)(0x424A81ACUL))
#define bFM4_BT8_PWM_TMCR_RTGEN                   *((volatile  uint8_t *)(0x424A81ACUL))

#define bFM_BT8_PWM_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A8220UL))
#define bFM4_BT8_PWM_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A8220UL))

#define bFM_BT8_RT_STC_UDIR                       *((volatile  uint8_t *)(0x424A8200UL))
#define bFM4_BT8_RT_STC_UDIR                      *((volatile  uint8_t *)(0x424A8200UL))
#define bFM_BT8_RT_STC_TGIR                       *((volatile  uint8_t *)(0x424A8208UL))
#define bFM4_BT8_RT_STC_TGIR                      *((volatile  uint8_t *)(0x424A8208UL))
#define bFM_BT8_RT_STC_UDIE                       *((volatile  uint8_t *)(0x424A8210UL))
#define bFM4_BT8_RT_STC_UDIE                      *((volatile  uint8_t *)(0x424A8210UL))
#define bFM_BT8_RT_STC_TGIE                       *((volatile  uint8_t *)(0x424A8218UL))
#define bFM4_BT8_RT_STC_TGIE                      *((volatile  uint8_t *)(0x424A8218UL))

#define bFM_BT8_RT_TMCR_STRG                      *((volatile  uint8_t *)(0x424A8180UL))
#define bFM4_BT8_RT_TMCR_STRG                     *((volatile  uint8_t *)(0x424A8180UL))
#define bFM_BT8_RT_TMCR_CTEN                      *((volatile  uint8_t *)(0x424A8184UL))
#define bFM4_BT8_RT_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A8184UL))
#define bFM_BT8_RT_TMCR_MDSE                      *((volatile  uint8_t *)(0x424A8188UL))
#define bFM4_BT8_RT_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A8188UL))
#define bFM_BT8_RT_TMCR_OSEL                      *((volatile  uint8_t *)(0x424A818CUL))
#define bFM4_BT8_RT_TMCR_OSEL                     *((volatile  uint8_t *)(0x424A818CUL))
#define bFM_BT8_RT_TMCR_T32                       *((volatile  uint8_t *)(0x424A819CUL))
#define bFM4_BT8_RT_TMCR_T32                      *((volatile  uint8_t *)(0x424A819CUL))

#define bFM_BT8_RT_TMCR2_CKS3                     *((volatile  uint8_t *)(0x424A8220UL))
#define bFM4_BT8_RT_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A8220UL))
#define bFM_BT8_RT_TMCR2_GATE                     *((volatile  uint8_t *)(0x424A823CUL))
#define bFM4_BT8_RT_TMCR2_GATE                    *((volatile  uint8_t *)(0x424A823CUL))


/*******************************************************************************
* BT Registers BT9
*   Bitband Section
*******************************************************************************/
#define bFM_BT9_PPG_STC_UDIR                      *((volatile  uint8_t *)(0x424A8A00UL))
#define bFM4_BT9_PPG_STC_UDIR                     *((volatile  uint8_t *)(0x424A8A00UL))
#define bFM_BT9_PPG_STC_TGIR                      *((volatile  uint8_t *)(0x424A8A08UL))
#define bFM4_BT9_PPG_STC_TGIR                     *((volatile  uint8_t *)(0x424A8A08UL))
#define bFM_BT9_PPG_STC_UDIE                      *((volatile  uint8_t *)(0x424A8A10UL))
#define bFM4_BT9_PPG_STC_UDIE                     *((volatile  uint8_t *)(0x424A8A10UL))
#define bFM_BT9_PPG_STC_TGIE                      *((volatile  uint8_t *)(0x424A8A18UL))
#define bFM4_BT9_PPG_STC_TGIE                     *((volatile  uint8_t *)(0x424A8A18UL))

#define bFM_BT9_PPG_TMCR_STRG                     *((volatile  uint8_t *)(0x424A8980UL))
#define bFM4_BT9_PPG_TMCR_STRG                    *((volatile  uint8_t *)(0x424A8980UL))
#define bFM_BT9_PPG_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A8984UL))
#define bFM4_BT9_PPG_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A8984UL))
#define bFM_BT9_PPG_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A8988UL))
#define bFM4_BT9_PPG_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A8988UL))
#define bFM_BT9_PPG_TMCR_OSEL                     *((volatile  uint8_t *)(0x424A898CUL))
#define bFM4_BT9_PPG_TMCR_OSEL                    *((volatile  uint8_t *)(0x424A898CUL))
#define bFM_BT9_PPG_TMCR_PMSK                     *((volatile  uint8_t *)(0x424A89A8UL))
#define bFM4_BT9_PPG_TMCR_PMSK                    *((volatile  uint8_t *)(0x424A89A8UL))
#define bFM_BT9_PPG_TMCR_RTGEN                    *((volatile  uint8_t *)(0x424A89ACUL))
#define bFM4_BT9_PPG_TMCR_RTGEN                   *((volatile  uint8_t *)(0x424A89ACUL))

#define bFM_BT9_PPG_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A8A20UL))
#define bFM4_BT9_PPG_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A8A20UL))

#define bFM_BT9_PWC_STC_OVIR                      *((volatile  uint8_t *)(0x424A8A00UL))
#define bFM4_BT9_PWC_STC_OVIR                     *((volatile  uint8_t *)(0x424A8A00UL))
#define bFM_BT9_PWC_STC_EDIR                      *((volatile  uint8_t *)(0x424A8A08UL))
#define bFM4_BT9_PWC_STC_EDIR                     *((volatile  uint8_t *)(0x424A8A08UL))
#define bFM_BT9_PWC_STC_OVIE                      *((volatile  uint8_t *)(0x424A8A10UL))
#define bFM4_BT9_PWC_STC_OVIE                     *((volatile  uint8_t *)(0x424A8A10UL))
#define bFM_BT9_PWC_STC_EDIE                      *((volatile  uint8_t *)(0x424A8A18UL))
#define bFM4_BT9_PWC_STC_EDIE                     *((volatile  uint8_t *)(0x424A8A18UL))
#define bFM_BT9_PWC_STC_ERR                       *((volatile  uint8_t *)(0x424A8A1CUL))
#define bFM4_BT9_PWC_STC_ERR                      *((volatile  uint8_t *)(0x424A8A1CUL))

#define bFM_BT9_PWC_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A8984UL))
#define bFM4_BT9_PWC_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A8984UL))
#define bFM_BT9_PWC_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A8988UL))
#define bFM4_BT9_PWC_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A8988UL))
#define bFM_BT9_PWC_TMCR_T32                      *((volatile  uint8_t *)(0x424A899CUL))
#define bFM4_BT9_PWC_TMCR_T32                     *((volatile  uint8_t *)(0x424A899CUL))

#define bFM_BT9_PWC_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A8A20UL))
#define bFM4_BT9_PWC_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A8A20UL))

#define bFM_BT9_PWM_STC_UDIR                      *((volatile  uint8_t *)(0x424A8A00UL))
#define bFM4_BT9_PWM_STC_UDIR                     *((volatile  uint8_t *)(0x424A8A00UL))
#define bFM_BT9_PWM_STC_DTIR                      *((volatile  uint8_t *)(0x424A8A04UL))
#define bFM4_BT9_PWM_STC_DTIR                     *((volatile  uint8_t *)(0x424A8A04UL))
#define bFM_BT9_PWM_STC_TGIR                      *((volatile  uint8_t *)(0x424A8A08UL))
#define bFM4_BT9_PWM_STC_TGIR                     *((volatile  uint8_t *)(0x424A8A08UL))
#define bFM_BT9_PWM_STC_UDIE                      *((volatile  uint8_t *)(0x424A8A10UL))
#define bFM4_BT9_PWM_STC_UDIE                     *((volatile  uint8_t *)(0x424A8A10UL))
#define bFM_BT9_PWM_STC_DTIE                      *((volatile  uint8_t *)(0x424A8A14UL))
#define bFM4_BT9_PWM_STC_DTIE                     *((volatile  uint8_t *)(0x424A8A14UL))
#define bFM_BT9_PWM_STC_TGIE                      *((volatile  uint8_t *)(0x424A8A18UL))
#define bFM4_BT9_PWM_STC_TGIE                     *((volatile  uint8_t *)(0x424A8A18UL))

#define bFM_BT9_PWM_TMCR_STRG                     *((volatile  uint8_t *)(0x424A8980UL))
#define bFM4_BT9_PWM_TMCR_STRG                    *((volatile  uint8_t *)(0x424A8980UL))
#define bFM_BT9_PWM_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A8984UL))
#define bFM4_BT9_PWM_TMCR_CTEN                    *((volatile  uint8_t *)(0x424A8984UL))
#define bFM_BT9_PWM_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A8988UL))
#define bFM4_BT9_PWM_TMCR_MDSE                    *((volatile  uint8_t *)(0x424A8988UL))
#define bFM_BT9_PWM_TMCR_OSEL                     *((volatile  uint8_t *)(0x424A898CUL))
#define bFM4_BT9_PWM_TMCR_OSEL                    *((volatile  uint8_t *)(0x424A898CUL))
#define bFM_BT9_PWM_TMCR_PMSK                     *((volatile  uint8_t *)(0x424A89A8UL))
#define bFM4_BT9_PWM_TMCR_PMSK                    *((volatile  uint8_t *)(0x424A89A8UL))
#define bFM_BT9_PWM_TMCR_RTGEN                    *((volatile  uint8_t *)(0x424A89ACUL))
#define bFM4_BT9_PWM_TMCR_RTGEN                   *((volatile  uint8_t *)(0x424A89ACUL))

#define bFM_BT9_PWM_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A8A20UL))
#define bFM4_BT9_PWM_TMCR2_CKS3                   *((volatile  uint8_t *)(0x424A8A20UL))

#define bFM_BT9_RT_STC_UDIR                       *((volatile  uint8_t *)(0x424A8A00UL))
#define bFM4_BT9_RT_STC_UDIR                      *((volatile  uint8_t *)(0x424A8A00UL))
#define bFM_BT9_RT_STC_TGIR                       *((volatile  uint8_t *)(0x424A8A08UL))
#define bFM4_BT9_RT_STC_TGIR                      *((volatile  uint8_t *)(0x424A8A08UL))
#define bFM_BT9_RT_STC_UDIE                       *((volatile  uint8_t *)(0x424A8A10UL))
#define bFM4_BT9_RT_STC_UDIE                      *((volatile  uint8_t *)(0x424A8A10UL))
#define bFM_BT9_RT_STC_TGIE                       *((volatile  uint8_t *)(0x424A8A18UL))
#define bFM4_BT9_RT_STC_TGIE                      *((volatile  uint8_t *)(0x424A8A18UL))

#define bFM_BT9_RT_TMCR_STRG                      *((volatile  uint8_t *)(0x424A8980UL))
#define bFM4_BT9_RT_TMCR_STRG                     *((volatile  uint8_t *)(0x424A8980UL))
#define bFM_BT9_RT_TMCR_CTEN                      *((volatile  uint8_t *)(0x424A8984UL))
#define bFM4_BT9_RT_TMCR_CTEN                     *((volatile  uint8_t *)(0x424A8984UL))
#define bFM_BT9_RT_TMCR_MDSE                      *((volatile  uint8_t *)(0x424A8988UL))
#define bFM4_BT9_RT_TMCR_MDSE                     *((volatile  uint8_t *)(0x424A8988UL))
#define bFM_BT9_RT_TMCR_OSEL                      *((volatile  uint8_t *)(0x424A898CUL))
#define bFM4_BT9_RT_TMCR_OSEL                     *((volatile  uint8_t *)(0x424A898CUL))
#define bFM_BT9_RT_TMCR_T32                       *((volatile  uint8_t *)(0x424A899CUL))
#define bFM4_BT9_RT_TMCR_T32                      *((volatile  uint8_t *)(0x424A899CUL))

#define bFM_BT9_RT_TMCR2_CKS3                     *((volatile  uint8_t *)(0x424A8A20UL))
#define bFM4_BT9_RT_TMCR2_CKS3                    *((volatile  uint8_t *)(0x424A8A20UL))
#define bFM_BT9_RT_TMCR2_GATE                     *((volatile  uint8_t *)(0x424A8A3CUL))
#define bFM4_BT9_RT_TMCR2_GATE                    *((volatile  uint8_t *)(0x424A8A3CUL))


/*******************************************************************************
* BTIOSEL03 Registers BTIOSEL03
*   Bitband Section
*******************************************************************************/

/*******************************************************************************
* BTIOSEL47 Registers BTIOSEL47
*   Bitband Section
*******************************************************************************/

/*******************************************************************************
* BTIOSEL8B Registers BTIOSEL8B
*   Bitband Section
*******************************************************************************/

/*******************************************************************************
* BTIOSELCF Registers BTIOSELCF
*   Bitband Section
*******************************************************************************/

/*******************************************************************************
* CAN Registers CAN0
*   Bitband Section
*******************************************************************************/
#define bFM_CAN0_CTRLR_INIT                       *((volatile  uint8_t *)(0x42C40000UL))
#define bFM4_CAN0_CTRLR_INIT                      *((volatile  uint8_t *)(0x42C40000UL))
#define bFM_CAN0_CTRLR_IE                         *((volatile  uint8_t *)(0x42C40004UL))
#define bFM4_CAN0_CTRLR_IE                        *((volatile  uint8_t *)(0x42C40004UL))
#define bFM_CAN0_CTRLR_SIE                        *((volatile  uint8_t *)(0x42C40008UL))
#define bFM4_CAN0_CTRLR_SIE                       *((volatile  uint8_t *)(0x42C40008UL))
#define bFM_CAN0_CTRLR_EIE                        *((volatile  uint8_t *)(0x42C4000CUL))
#define bFM4_CAN0_CTRLR_EIE                       *((volatile  uint8_t *)(0x42C4000CUL))
#define bFM_CAN0_CTRLR_DAR                        *((volatile  uint8_t *)(0x42C40014UL))
#define bFM4_CAN0_CTRLR_DAR                       *((volatile  uint8_t *)(0x42C40014UL))
#define bFM_CAN0_CTRLR_CCE                        *((volatile  uint8_t *)(0x42C40018UL))
#define bFM4_CAN0_CTRLR_CCE                       *((volatile  uint8_t *)(0x42C40018UL))
#define bFM_CAN0_CTRLR_TEST                       *((volatile  uint8_t *)(0x42C4001CUL))
#define bFM4_CAN0_CTRLR_TEST                      *((volatile  uint8_t *)(0x42C4001CUL))

#define bFM_CAN0_ERRCNT_RP                        *((volatile  uint8_t *)(0x42C400BCUL))
#define bFM4_CAN0_ERRCNT_RP                       *((volatile  uint8_t *)(0x42C400BCUL))

#define bFM_CAN0_IF1ARB_DIR                       *((volatile  uint8_t *)(0x42C40374UL))
#define bFM4_CAN0_IF1ARB_DIR                      *((volatile  uint8_t *)(0x42C40374UL))
#define bFM_CAN0_IF1ARB_XTD                       *((volatile  uint8_t *)(0x42C40378UL))
#define bFM4_CAN0_IF1ARB_XTD                      *((volatile  uint8_t *)(0x42C40378UL))
#define bFM_CAN0_IF1ARB_MSGVAL                    *((volatile  uint8_t *)(0x42C4037CUL))
#define bFM4_CAN0_IF1ARB_MSGVAL                   *((volatile  uint8_t *)(0x42C4037CUL))

#define bFM_CAN0_IF1CMSK_DATAB                    *((volatile  uint8_t *)(0x42C40240UL))
#define bFM4_CAN0_IF1CMSK_DATAB                   *((volatile  uint8_t *)(0x42C40240UL))
#define bFM_CAN0_IF1CMSK_DATAA                    *((volatile  uint8_t *)(0x42C40244UL))
#define bFM4_CAN0_IF1CMSK_DATAA                   *((volatile  uint8_t *)(0x42C40244UL))
#define bFM_CAN0_IF1CMSK_NEWDAT                   *((volatile  uint8_t *)(0x42C40248UL))
#define bFM4_CAN0_IF1CMSK_NEWDAT                  *((volatile  uint8_t *)(0x42C40248UL))
#define bFM_CAN0_IF1CMSK_CIP                      *((volatile  uint8_t *)(0x42C4024CUL))
#define bFM4_CAN0_IF1CMSK_CIP                     *((volatile  uint8_t *)(0x42C4024CUL))
#define bFM_CAN0_IF1CMSK_CONTROL                  *((volatile  uint8_t *)(0x42C40250UL))
#define bFM4_CAN0_IF1CMSK_CONTROL                 *((volatile  uint8_t *)(0x42C40250UL))
#define bFM_CAN0_IF1CMSK_ARB                      *((volatile  uint8_t *)(0x42C40254UL))
#define bFM4_CAN0_IF1CMSK_ARB                     *((volatile  uint8_t *)(0x42C40254UL))
#define bFM_CAN0_IF1CMSK_MASK                     *((volatile  uint8_t *)(0x42C40258UL))
#define bFM4_CAN0_IF1CMSK_MASK                    *((volatile  uint8_t *)(0x42C40258UL))
#define bFM_CAN0_IF1CMSK_WR_RD                    *((volatile  uint8_t *)(0x42C4025CUL))
#define bFM4_CAN0_IF1CMSK_WR_RD                   *((volatile  uint8_t *)(0x42C4025CUL))

#define bFM_CAN0_IF1CREQ_BUSY                     *((volatile  uint8_t *)(0x42C4023CUL))
#define bFM4_CAN0_IF1CREQ_BUSY                    *((volatile  uint8_t *)(0x42C4023CUL))

#define bFM_CAN0_IF1MCTR_EOB                      *((volatile  uint8_t *)(0x42C4039CUL))
#define bFM4_CAN0_IF1MCTR_EOB                     *((volatile  uint8_t *)(0x42C4039CUL))
#define bFM_CAN0_IF1MCTR_TXRQST                   *((volatile  uint8_t *)(0x42C403A0UL))
#define bFM4_CAN0_IF1MCTR_TXRQST                  *((volatile  uint8_t *)(0x42C403A0UL))
#define bFM_CAN0_IF1MCTR_RMTEN                    *((volatile  uint8_t *)(0x42C403A4UL))
#define bFM4_CAN0_IF1MCTR_RMTEN                   *((volatile  uint8_t *)(0x42C403A4UL))
#define bFM_CAN0_IF1MCTR_RXIE                     *((volatile  uint8_t *)(0x42C403A8UL))
#define bFM4_CAN0_IF1MCTR_RXIE                    *((volatile  uint8_t *)(0x42C403A8UL))
#define bFM_CAN0_IF1MCTR_TXIE                     *((volatile  uint8_t *)(0x42C403ACUL))
#define bFM4_CAN0_IF1MCTR_TXIE                    *((volatile  uint8_t *)(0x42C403ACUL))
#define bFM_CAN0_IF1MCTR_UMASK                    *((volatile  uint8_t *)(0x42C403B0UL))
#define bFM4_CAN0_IF1MCTR_UMASK                   *((volatile  uint8_t *)(0x42C403B0UL))
#define bFM_CAN0_IF1MCTR_INTPND                   *((volatile  uint8_t *)(0x42C403B4UL))
#define bFM4_CAN0_IF1MCTR_INTPND                  *((volatile  uint8_t *)(0x42C403B4UL))
#define bFM_CAN0_IF1MCTR_MSGLST                   *((volatile  uint8_t *)(0x42C403B8UL))
#define bFM4_CAN0_IF1MCTR_MSGLST                  *((volatile  uint8_t *)(0x42C403B8UL))
#define bFM_CAN0_IF1MCTR_NEWDAT                   *((volatile  uint8_t *)(0x42C403BCUL))
#define bFM4_CAN0_IF1MCTR_NEWDAT                  *((volatile  uint8_t *)(0x42C403BCUL))

#define bFM_CAN0_IF1MSK_MDIR                      *((volatile  uint8_t *)(0x42C402F8UL))
#define bFM4_CAN0_IF1MSK_MDIR                     *((volatile  uint8_t *)(0x42C402F8UL))
#define bFM_CAN0_IF1MSK_MXTD                      *((volatile  uint8_t *)(0x42C402FCUL))
#define bFM4_CAN0_IF1MSK_MXTD                     *((volatile  uint8_t *)(0x42C402FCUL))

#define bFM_CAN0_IF2ARB_DIR                       *((volatile  uint8_t *)(0x42C40974UL))
#define bFM4_CAN0_IF2ARB_DIR                      *((volatile  uint8_t *)(0x42C40974UL))
#define bFM_CAN0_IF2ARB_XTD                       *((volatile  uint8_t *)(0x42C40978UL))
#define bFM4_CAN0_IF2ARB_XTD                      *((volatile  uint8_t *)(0x42C40978UL))
#define bFM_CAN0_IF2ARB_MSGVAL                    *((volatile  uint8_t *)(0x42C4097CUL))
#define bFM4_CAN0_IF2ARB_MSGVAL                   *((volatile  uint8_t *)(0x42C4097CUL))

#define bFM_CAN0_IF2CMSK_DATAB                    *((volatile  uint8_t *)(0x42C40840UL))
#define bFM4_CAN0_IF2CMSK_DATAB                   *((volatile  uint8_t *)(0x42C40840UL))
#define bFM_CAN0_IF2CMSK_DATAA                    *((volatile  uint8_t *)(0x42C40844UL))
#define bFM4_CAN0_IF2CMSK_DATAA                   *((volatile  uint8_t *)(0x42C40844UL))
#define bFM_CAN0_IF2CMSK_NEWDAT                   *((volatile  uint8_t *)(0x42C40848UL))
#define bFM4_CAN0_IF2CMSK_NEWDAT                  *((volatile  uint8_t *)(0x42C40848UL))
#define bFM_CAN0_IF2CMSK_CIP                      *((volatile  uint8_t *)(0x42C4084CUL))
#define bFM4_CAN0_IF2CMSK_CIP                     *((volatile  uint8_t *)(0x42C4084CUL))
#define bFM_CAN0_IF2CMSK_CONTROL                  *((volatile  uint8_t *)(0x42C40850UL))
#define bFM4_CAN0_IF2CMSK_CONTROL                 *((volatile  uint8_t *)(0x42C40850UL))
#define bFM_CAN0_IF2CMSK_ARB                      *((volatile  uint8_t *)(0x42C40854UL))
#define bFM4_CAN0_IF2CMSK_ARB                     *((volatile  uint8_t *)(0x42C40854UL))
#define bFM_CAN0_IF2CMSK_MASK                     *((volatile  uint8_t *)(0x42C40858UL))
#define bFM4_CAN0_IF2CMSK_MASK                    *((volatile  uint8_t *)(0x42C40858UL))
#define bFM_CAN0_IF2CMSK_WR_RD                    *((volatile  uint8_t *)(0x42C4085CUL))
#define bFM4_CAN0_IF2CMSK_WR_RD                   *((volatile  uint8_t *)(0x42C4085CUL))

#define bFM_CAN0_IF2CREQ_BUSY                     *((volatile  uint8_t *)(0x42C4083CUL))
#define bFM4_CAN0_IF2CREQ_BUSY                    *((volatile  uint8_t *)(0x42C4083CUL))

#define bFM_CAN0_IF2MCTR_EOB                      *((volatile  uint8_t *)(0x42C4099CUL))
#define bFM4_CAN0_IF2MCTR_EOB                     *((volatile  uint8_t *)(0x42C4099CUL))
#define bFM_CAN0_IF2MCTR_TXRQST                   *((volatile  uint8_t *)(0x42C409A0UL))
#define bFM4_CAN0_IF2MCTR_TXRQST                  *((volatile  uint8_t *)(0x42C409A0UL))
#define bFM_CAN0_IF2MCTR_RMTEN                    *((volatile  uint8_t *)(0x42C409A4UL))
#define bFM4_CAN0_IF2MCTR_RMTEN                   *((volatile  uint8_t *)(0x42C409A4UL))
#define bFM_CAN0_IF2MCTR_RXIE                     *((volatile  uint8_t *)(0x42C409A8UL))
#define bFM4_CAN0_IF2MCTR_RXIE                    *((volatile  uint8_t *)(0x42C409A8UL))
#define bFM_CAN0_IF2MCTR_TXIE                     *((volatile  uint8_t *)(0x42C409ACUL))
#define bFM4_CAN0_IF2MCTR_TXIE                    *((volatile  uint8_t *)(0x42C409ACUL))
#define bFM_CAN0_IF2MCTR_UMASK                    *((volatile  uint8_t *)(0x42C409B0UL))
#define bFM4_CAN0_IF2MCTR_UMASK                   *((volatile  uint8_t *)(0x42C409B0UL))
#define bFM_CAN0_IF2MCTR_INTPND                   *((volatile  uint8_t *)(0x42C409B4UL))
#define bFM4_CAN0_IF2MCTR_INTPND                  *((volatile  uint8_t *)(0x42C409B4UL))
#define bFM_CAN0_IF2MCTR_MSGLST                   *((volatile  uint8_t *)(0x42C409B8UL))
#define bFM4_CAN0_IF2MCTR_MSGLST                  *((volatile  uint8_t *)(0x42C409B8UL))
#define bFM_CAN0_IF2MCTR_NEWDAT                   *((volatile  uint8_t *)(0x42C409BCUL))
#define bFM4_CAN0_IF2MCTR_NEWDAT                  *((volatile  uint8_t *)(0x42C409BCUL))

#define bFM_CAN0_IF2MSK_MDIR                      *((volatile  uint8_t *)(0x42C408F8UL))
#define bFM4_CAN0_IF2MSK_MDIR                     *((volatile  uint8_t *)(0x42C408F8UL))
#define bFM_CAN0_IF2MSK_MXTD                      *((volatile  uint8_t *)(0x42C408FCUL))
#define bFM4_CAN0_IF2MSK_MXTD                     *((volatile  uint8_t *)(0x42C408FCUL))

#define bFM_CAN0_INTPND_INTPND1                   *((volatile  uint8_t *)(0x42C41400UL))
#define bFM4_CAN0_INTPND_INTPND1                  *((volatile  uint8_t *)(0x42C41400UL))
#define bFM_CAN0_INTPND_INTPND2                   *((volatile  uint8_t *)(0x42C41404UL))
#define bFM4_CAN0_INTPND_INTPND2                  *((volatile  uint8_t *)(0x42C41404UL))
#define bFM_CAN0_INTPND_INTPND3                   *((volatile  uint8_t *)(0x42C41408UL))
#define bFM4_CAN0_INTPND_INTPND3                  *((volatile  uint8_t *)(0x42C41408UL))
#define bFM_CAN0_INTPND_INTPND4                   *((volatile  uint8_t *)(0x42C4140CUL))
#define bFM4_CAN0_INTPND_INTPND4                  *((volatile  uint8_t *)(0x42C4140CUL))
#define bFM_CAN0_INTPND_INTPND5                   *((volatile  uint8_t *)(0x42C41410UL))
#define bFM4_CAN0_INTPND_INTPND5                  *((volatile  uint8_t *)(0x42C41410UL))
#define bFM_CAN0_INTPND_INTPND6                   *((volatile  uint8_t *)(0x42C41414UL))
#define bFM4_CAN0_INTPND_INTPND6                  *((volatile  uint8_t *)(0x42C41414UL))
#define bFM_CAN0_INTPND_INTPND7                   *((volatile  uint8_t *)(0x42C41418UL))
#define bFM4_CAN0_INTPND_INTPND7                  *((volatile  uint8_t *)(0x42C41418UL))
#define bFM_CAN0_INTPND_INTPND8                   *((volatile  uint8_t *)(0x42C4141CUL))
#define bFM4_CAN0_INTPND_INTPND8                  *((volatile  uint8_t *)(0x42C4141CUL))
#define bFM_CAN0_INTPND_INTPND9                   *((volatile  uint8_t *)(0x42C41420UL))
#define bFM4_CAN0_INTPND_INTPND9                  *((volatile  uint8_t *)(0x42C41420UL))
#define bFM_CAN0_INTPND_INTPND10                  *((volatile  uint8_t *)(0x42C41424UL))
#define bFM4_CAN0_INTPND_INTPND10                 *((volatile  uint8_t *)(0x42C41424UL))
#define bFM_CAN0_INTPND_INTPND11                  *((volatile  uint8_t *)(0x42C41428UL))
#define bFM4_CAN0_INTPND_INTPND11                 *((volatile  uint8_t *)(0x42C41428UL))
#define bFM_CAN0_INTPND_INTPND12                  *((volatile  uint8_t *)(0x42C4142CUL))
#define bFM4_CAN0_INTPND_INTPND12                 *((volatile  uint8_t *)(0x42C4142CUL))
#define bFM_CAN0_INTPND_INTPND13                  *((volatile  uint8_t *)(0x42C41430UL))
#define bFM4_CAN0_INTPND_INTPND13                 *((volatile  uint8_t *)(0x42C41430UL))
#define bFM_CAN0_INTPND_INTPND14                  *((volatile  uint8_t *)(0x42C41434UL))
#define bFM4_CAN0_INTPND_INTPND14                 *((volatile  uint8_t *)(0x42C41434UL))
#define bFM_CAN0_INTPND_INTPND15                  *((volatile  uint8_t *)(0x42C41438UL))
#define bFM4_CAN0_INTPND_INTPND15                 *((volatile  uint8_t *)(0x42C41438UL))
#define bFM_CAN0_INTPND_INTPND16                  *((volatile  uint8_t *)(0x42C4143CUL))
#define bFM4_CAN0_INTPND_INTPND16                 *((volatile  uint8_t *)(0x42C4143CUL))
#define bFM_CAN0_INTPND_INTPND17                  *((volatile  uint8_t *)(0x42C41440UL))
#define bFM4_CAN0_INTPND_INTPND17                 *((volatile  uint8_t *)(0x42C41440UL))
#define bFM_CAN0_INTPND_INTPND18                  *((volatile  uint8_t *)(0x42C41444UL))
#define bFM4_CAN0_INTPND_INTPND18                 *((volatile  uint8_t *)(0x42C41444UL))
#define bFM_CAN0_INTPND_INTPND19                  *((volatile  uint8_t *)(0x42C41448UL))
#define bFM4_CAN0_INTPND_INTPND19                 *((volatile  uint8_t *)(0x42C41448UL))
#define bFM_CAN0_INTPND_INTPND20                  *((volatile  uint8_t *)(0x42C4144CUL))
#define bFM4_CAN0_INTPND_INTPND20                 *((volatile  uint8_t *)(0x42C4144CUL))
#define bFM_CAN0_INTPND_INTPND21                  *((volatile  uint8_t *)(0x42C41450UL))
#define bFM4_CAN0_INTPND_INTPND21                 *((volatile  uint8_t *)(0x42C41450UL))
#define bFM_CAN0_INTPND_INTPND22                  *((volatile  uint8_t *)(0x42C41454UL))
#define bFM4_CAN0_INTPND_INTPND22                 *((volatile  uint8_t *)(0x42C41454UL))
#define bFM_CAN0_INTPND_INTPND23                  *((volatile  uint8_t *)(0x42C41458UL))
#define bFM4_CAN0_INTPND_INTPND23                 *((volatile  uint8_t *)(0x42C41458UL))
#define bFM_CAN0_INTPND_INTPND24                  *((volatile  uint8_t *)(0x42C4145CUL))
#define bFM4_CAN0_INTPND_INTPND24                 *((volatile  uint8_t *)(0x42C4145CUL))
#define bFM_CAN0_INTPND_INTPND25                  *((volatile  uint8_t *)(0x42C41460UL))
#define bFM4_CAN0_INTPND_INTPND25                 *((volatile  uint8_t *)(0x42C41460UL))
#define bFM_CAN0_INTPND_INTPND26                  *((volatile  uint8_t *)(0x42C41464UL))
#define bFM4_CAN0_INTPND_INTPND26                 *((volatile  uint8_t *)(0x42C41464UL))
#define bFM_CAN0_INTPND_INTPND27                  *((volatile  uint8_t *)(0x42C41468UL))
#define bFM4_CAN0_INTPND_INTPND27                 *((volatile  uint8_t *)(0x42C41468UL))
#define bFM_CAN0_INTPND_INTPND28                  *((volatile  uint8_t *)(0x42C4146CUL))
#define bFM4_CAN0_INTPND_INTPND28                 *((volatile  uint8_t *)(0x42C4146CUL))
#define bFM_CAN0_INTPND_INTPND29                  *((volatile  uint8_t *)(0x42C41470UL))
#define bFM4_CAN0_INTPND_INTPND29                 *((volatile  uint8_t *)(0x42C41470UL))
#define bFM_CAN0_INTPND_INTPND30                  *((volatile  uint8_t *)(0x42C41474UL))
#define bFM4_CAN0_INTPND_INTPND30                 *((volatile  uint8_t *)(0x42C41474UL))
#define bFM_CAN0_INTPND_INTPND31                  *((volatile  uint8_t *)(0x42C41478UL))
#define bFM4_CAN0_INTPND_INTPND31                 *((volatile  uint8_t *)(0x42C41478UL))
#define bFM_CAN0_INTPND_INTPND32                  *((volatile  uint8_t *)(0x42C4147CUL))
#define bFM4_CAN0_INTPND_INTPND32                 *((volatile  uint8_t *)(0x42C4147CUL))

#define bFM_CAN0_MSGVAL_MSGVAL1                   *((volatile  uint8_t *)(0x42C41600UL))
#define bFM4_CAN0_MSGVAL_MSGVAL1                  *((volatile  uint8_t *)(0x42C41600UL))
#define bFM_CAN0_MSGVAL_MSGVAL2                   *((volatile  uint8_t *)(0x42C41604UL))
#define bFM4_CAN0_MSGVAL_MSGVAL2                  *((volatile  uint8_t *)(0x42C41604UL))
#define bFM_CAN0_MSGVAL_MSGVAL3                   *((volatile  uint8_t *)(0x42C41608UL))
#define bFM4_CAN0_MSGVAL_MSGVAL3                  *((volatile  uint8_t *)(0x42C41608UL))
#define bFM_CAN0_MSGVAL_MSGVAL4                   *((volatile  uint8_t *)(0x42C4160CUL))
#define bFM4_CAN0_MSGVAL_MSGVAL4                  *((volatile  uint8_t *)(0x42C4160CUL))
#define bFM_CAN0_MSGVAL_MSGVAL5                   *((volatile  uint8_t *)(0x42C41610UL))
#define bFM4_CAN0_MSGVAL_MSGVAL5                  *((volatile  uint8_t *)(0x42C41610UL))
#define bFM_CAN0_MSGVAL_MSGVAL6                   *((volatile  uint8_t *)(0x42C41614UL))
#define bFM4_CAN0_MSGVAL_MSGVAL6                  *((volatile  uint8_t *)(0x42C41614UL))
#define bFM_CAN0_MSGVAL_MSGVAL7                   *((volatile  uint8_t *)(0x42C41618UL))
#define bFM4_CAN0_MSGVAL_MSGVAL7                  *((volatile  uint8_t *)(0x42C41618UL))
#define bFM_CAN0_MSGVAL_MSGVAL8                   *((volatile  uint8_t *)(0x42C4161CUL))
#define bFM4_CAN0_MSGVAL_MSGVAL8                  *((volatile  uint8_t *)(0x42C4161CUL))
#define bFM_CAN0_MSGVAL_MSGVAL9                   *((volatile  uint8_t *)(0x42C41620UL))
#define bFM4_CAN0_MSGVAL_MSGVAL9                  *((volatile  uint8_t *)(0x42C41620UL))
#define bFM_CAN0_MSGVAL_MSGVAL10                  *((volatile  uint8_t *)(0x42C41624UL))
#define bFM4_CAN0_MSGVAL_MSGVAL10                 *((volatile  uint8_t *)(0x42C41624UL))
#define bFM_CAN0_MSGVAL_MSGVAL11                  *((volatile  uint8_t *)(0x42C41628UL))
#define bFM4_CAN0_MSGVAL_MSGVAL11                 *((volatile  uint8_t *)(0x42C41628UL))
#define bFM_CAN0_MSGVAL_MSGVAL12                  *((volatile  uint8_t *)(0x42C4162CUL))
#define bFM4_CAN0_MSGVAL_MSGVAL12                 *((volatile  uint8_t *)(0x42C4162CUL))
#define bFM_CAN0_MSGVAL_MSGVAL13                  *((volatile  uint8_t *)(0x42C41630UL))
#define bFM4_CAN0_MSGVAL_MSGVAL13                 *((volatile  uint8_t *)(0x42C41630UL))
#define bFM_CAN0_MSGVAL_MSGVAL14                  *((volatile  uint8_t *)(0x42C41634UL))
#define bFM4_CAN0_MSGVAL_MSGVAL14                 *((volatile  uint8_t *)(0x42C41634UL))
#define bFM_CAN0_MSGVAL_MSGVAL15                  *((volatile  uint8_t *)(0x42C41638UL))
#define bFM4_CAN0_MSGVAL_MSGVAL15                 *((volatile  uint8_t *)(0x42C41638UL))
#define bFM_CAN0_MSGVAL_MSGVAL16                  *((volatile  uint8_t *)(0x42C4163CUL))
#define bFM4_CAN0_MSGVAL_MSGVAL16                 *((volatile  uint8_t *)(0x42C4163CUL))
#define bFM_CAN0_MSGVAL_MSGVAL17                  *((volatile  uint8_t *)(0x42C41640UL))
#define bFM4_CAN0_MSGVAL_MSGVAL17                 *((volatile  uint8_t *)(0x42C41640UL))
#define bFM_CAN0_MSGVAL_MSGVAL18                  *((volatile  uint8_t *)(0x42C41644UL))
#define bFM4_CAN0_MSGVAL_MSGVAL18                 *((volatile  uint8_t *)(0x42C41644UL))
#define bFM_CAN0_MSGVAL_MSGVAL19                  *((volatile  uint8_t *)(0x42C41648UL))
#define bFM4_CAN0_MSGVAL_MSGVAL19                 *((volatile  uint8_t *)(0x42C41648UL))
#define bFM_CAN0_MSGVAL_MSGVAL20                  *((volatile  uint8_t *)(0x42C4164CUL))
#define bFM4_CAN0_MSGVAL_MSGVAL20                 *((volatile  uint8_t *)(0x42C4164CUL))
#define bFM_CAN0_MSGVAL_MSGVAL21                  *((volatile  uint8_t *)(0x42C41650UL))
#define bFM4_CAN0_MSGVAL_MSGVAL21                 *((volatile  uint8_t *)(0x42C41650UL))
#define bFM_CAN0_MSGVAL_MSGVAL22                  *((volatile  uint8_t *)(0x42C41654UL))
#define bFM4_CAN0_MSGVAL_MSGVAL22                 *((volatile  uint8_t *)(0x42C41654UL))
#define bFM_CAN0_MSGVAL_MSGVAL23                  *((volatile  uint8_t *)(0x42C41658UL))
#define bFM4_CAN0_MSGVAL_MSGVAL23                 *((volatile  uint8_t *)(0x42C41658UL))
#define bFM_CAN0_MSGVAL_MSGVAL24                  *((volatile  uint8_t *)(0x42C4165CUL))
#define bFM4_CAN0_MSGVAL_MSGVAL24                 *((volatile  uint8_t *)(0x42C4165CUL))
#define bFM_CAN0_MSGVAL_MSGVAL25                  *((volatile  uint8_t *)(0x42C41660UL))
#define bFM4_CAN0_MSGVAL_MSGVAL25                 *((volatile  uint8_t *)(0x42C41660UL))
#define bFM_CAN0_MSGVAL_MSGVAL26                  *((volatile  uint8_t *)(0x42C41664UL))
#define bFM4_CAN0_MSGVAL_MSGVAL26                 *((volatile  uint8_t *)(0x42C41664UL))
#define bFM_CAN0_MSGVAL_MSGVAL27                  *((volatile  uint8_t *)(0x42C41668UL))
#define bFM4_CAN0_MSGVAL_MSGVAL27                 *((volatile  uint8_t *)(0x42C41668UL))
#define bFM_CAN0_MSGVAL_MSGVAL28                  *((volatile  uint8_t *)(0x42C4166CUL))
#define bFM4_CAN0_MSGVAL_MSGVAL28                 *((volatile  uint8_t *)(0x42C4166CUL))
#define bFM_CAN0_MSGVAL_MSGVAL29                  *((volatile  uint8_t *)(0x42C41670UL))
#define bFM4_CAN0_MSGVAL_MSGVAL29                 *((volatile  uint8_t *)(0x42C41670UL))
#define bFM_CAN0_MSGVAL_MSGVAL30                  *((volatile  uint8_t *)(0x42C41674UL))
#define bFM4_CAN0_MSGVAL_MSGVAL30                 *((volatile  uint8_t *)(0x42C41674UL))
#define bFM_CAN0_MSGVAL_MSGVAL31                  *((volatile  uint8_t *)(0x42C41678UL))
#define bFM4_CAN0_MSGVAL_MSGVAL31                 *((volatile  uint8_t *)(0x42C41678UL))
#define bFM_CAN0_MSGVAL_MSGVAL32                  *((volatile  uint8_t *)(0x42C4167CUL))
#define bFM4_CAN0_MSGVAL_MSGVAL32                 *((volatile  uint8_t *)(0x42C4167CUL))

#define bFM_CAN0_NEWDT_NEWDAT1                    *((volatile  uint8_t *)(0x42C41200UL))
#define bFM4_CAN0_NEWDT_NEWDAT1                   *((volatile  uint8_t *)(0x42C41200UL))
#define bFM_CAN0_NEWDT_NEWDAT2                    *((volatile  uint8_t *)(0x42C41204UL))
#define bFM4_CAN0_NEWDT_NEWDAT2                   *((volatile  uint8_t *)(0x42C41204UL))
#define bFM_CAN0_NEWDT_NEWDAT3                    *((volatile  uint8_t *)(0x42C41208UL))
#define bFM4_CAN0_NEWDT_NEWDAT3                   *((volatile  uint8_t *)(0x42C41208UL))
#define bFM_CAN0_NEWDT_NEWDAT4                    *((volatile  uint8_t *)(0x42C4120CUL))
#define bFM4_CAN0_NEWDT_NEWDAT4                   *((volatile  uint8_t *)(0x42C4120CUL))
#define bFM_CAN0_NEWDT_NEWDAT5                    *((volatile  uint8_t *)(0x42C41210UL))
#define bFM4_CAN0_NEWDT_NEWDAT5                   *((volatile  uint8_t *)(0x42C41210UL))
#define bFM_CAN0_NEWDT_NEWDAT6                    *((volatile  uint8_t *)(0x42C41214UL))
#define bFM4_CAN0_NEWDT_NEWDAT6                   *((volatile  uint8_t *)(0x42C41214UL))
#define bFM_CAN0_NEWDT_NEWDAT7                    *((volatile  uint8_t *)(0x42C41218UL))
#define bFM4_CAN0_NEWDT_NEWDAT7                   *((volatile  uint8_t *)(0x42C41218UL))
#define bFM_CAN0_NEWDT_NEWDAT8                    *((volatile  uint8_t *)(0x42C4121CUL))
#define bFM4_CAN0_NEWDT_NEWDAT8                   *((volatile  uint8_t *)(0x42C4121CUL))
#define bFM_CAN0_NEWDT_NEWDAT9                    *((volatile  uint8_t *)(0x42C41220UL))
#define bFM4_CAN0_NEWDT_NEWDAT9                   *((volatile  uint8_t *)(0x42C41220UL))
#define bFM_CAN0_NEWDT_NEWDAT10                   *((volatile  uint8_t *)(0x42C41224UL))
#define bFM4_CAN0_NEWDT_NEWDAT10                  *((volatile  uint8_t *)(0x42C41224UL))
#define bFM_CAN0_NEWDT_NEWDAT11                   *((volatile  uint8_t *)(0x42C41228UL))
#define bFM4_CAN0_NEWDT_NEWDAT11                  *((volatile  uint8_t *)(0x42C41228UL))
#define bFM_CAN0_NEWDT_NEWDAT12                   *((volatile  uint8_t *)(0x42C4122CUL))
#define bFM4_CAN0_NEWDT_NEWDAT12                  *((volatile  uint8_t *)(0x42C4122CUL))
#define bFM_CAN0_NEWDT_NEWDAT13                   *((volatile  uint8_t *)(0x42C41230UL))
#define bFM4_CAN0_NEWDT_NEWDAT13                  *((volatile  uint8_t *)(0x42C41230UL))
#define bFM_CAN0_NEWDT_NEWDAT14                   *((volatile  uint8_t *)(0x42C41234UL))
#define bFM4_CAN0_NEWDT_NEWDAT14                  *((volatile  uint8_t *)(0x42C41234UL))
#define bFM_CAN0_NEWDT_NEWDAT15                   *((volatile  uint8_t *)(0x42C41238UL))
#define bFM4_CAN0_NEWDT_NEWDAT15                  *((volatile  uint8_t *)(0x42C41238UL))
#define bFM_CAN0_NEWDT_NEWDAT16                   *((volatile  uint8_t *)(0x42C4123CUL))
#define bFM4_CAN0_NEWDT_NEWDAT16                  *((volatile  uint8_t *)(0x42C4123CUL))
#define bFM_CAN0_NEWDT_NEWDAT17                   *((volatile  uint8_t *)(0x42C41240UL))
#define bFM4_CAN0_NEWDT_NEWDAT17                  *((volatile  uint8_t *)(0x42C41240UL))
#define bFM_CAN0_NEWDT_NEWDAT18                   *((volatile  uint8_t *)(0x42C41244UL))
#define bFM4_CAN0_NEWDT_NEWDAT18                  *((volatile  uint8_t *)(0x42C41244UL))
#define bFM_CAN0_NEWDT_NEWDAT19                   *((volatile  uint8_t *)(0x42C41248UL))
#define bFM4_CAN0_NEWDT_NEWDAT19                  *((volatile  uint8_t *)(0x42C41248UL))
#define bFM_CAN0_NEWDT_NEWDAT20                   *((volatile  uint8_t *)(0x42C4124CUL))
#define bFM4_CAN0_NEWDT_NEWDAT20                  *((volatile  uint8_t *)(0x42C4124CUL))
#define bFM_CAN0_NEWDT_NEWDAT21                   *((volatile  uint8_t *)(0x42C41250UL))
#define bFM4_CAN0_NEWDT_NEWDAT21                  *((volatile  uint8_t *)(0x42C41250UL))
#define bFM_CAN0_NEWDT_NEWDAT22                   *((volatile  uint8_t *)(0x42C41254UL))
#define bFM4_CAN0_NEWDT_NEWDAT22                  *((volatile  uint8_t *)(0x42C41254UL))
#define bFM_CAN0_NEWDT_NEWDAT23                   *((volatile  uint8_t *)(0x42C41258UL))
#define bFM4_CAN0_NEWDT_NEWDAT23                  *((volatile  uint8_t *)(0x42C41258UL))
#define bFM_CAN0_NEWDT_NEWDAT24                   *((volatile  uint8_t *)(0x42C4125CUL))
#define bFM4_CAN0_NEWDT_NEWDAT24                  *((volatile  uint8_t *)(0x42C4125CUL))
#define bFM_CAN0_NEWDT_NEWDAT25                   *((volatile  uint8_t *)(0x42C41260UL))
#define bFM4_CAN0_NEWDT_NEWDAT25                  *((volatile  uint8_t *)(0x42C41260UL))
#define bFM_CAN0_NEWDT_NEWDAT26                   *((volatile  uint8_t *)(0x42C41264UL))
#define bFM4_CAN0_NEWDT_NEWDAT26                  *((volatile  uint8_t *)(0x42C41264UL))
#define bFM_CAN0_NEWDT_NEWDAT27                   *((volatile  uint8_t *)(0x42C41268UL))
#define bFM4_CAN0_NEWDT_NEWDAT27                  *((volatile  uint8_t *)(0x42C41268UL))
#define bFM_CAN0_NEWDT_NEWDAT28                   *((volatile  uint8_t *)(0x42C4126CUL))
#define bFM4_CAN0_NEWDT_NEWDAT28                  *((volatile  uint8_t *)(0x42C4126CUL))
#define bFM_CAN0_NEWDT_NEWDAT29                   *((volatile  uint8_t *)(0x42C41270UL))
#define bFM4_CAN0_NEWDT_NEWDAT29                  *((volatile  uint8_t *)(0x42C41270UL))
#define bFM_CAN0_NEWDT_NEWDAT30                   *((volatile  uint8_t *)(0x42C41274UL))
#define bFM4_CAN0_NEWDT_NEWDAT30                  *((volatile  uint8_t *)(0x42C41274UL))
#define bFM_CAN0_NEWDT_NEWDAT31                   *((volatile  uint8_t *)(0x42C41278UL))
#define bFM4_CAN0_NEWDT_NEWDAT31                  *((volatile  uint8_t *)(0x42C41278UL))
#define bFM_CAN0_NEWDT_NEWDAT32                   *((volatile  uint8_t *)(0x42C4127CUL))
#define bFM4_CAN0_NEWDT_NEWDAT32                  *((volatile  uint8_t *)(0x42C4127CUL))

#define bFM_CAN0_STATR_TXOK                       *((volatile  uint8_t *)(0x42C4004CUL))
#define bFM4_CAN0_STATR_TXOK                      *((volatile  uint8_t *)(0x42C4004CUL))
#define bFM_CAN0_STATR_RXOK                       *((volatile  uint8_t *)(0x42C40050UL))
#define bFM4_CAN0_STATR_RXOK                      *((volatile  uint8_t *)(0x42C40050UL))
#define bFM_CAN0_STATR_EPASS                      *((volatile  uint8_t *)(0x42C40054UL))
#define bFM4_CAN0_STATR_EPASS                     *((volatile  uint8_t *)(0x42C40054UL))
#define bFM_CAN0_STATR_EWARN                      *((volatile  uint8_t *)(0x42C40058UL))
#define bFM4_CAN0_STATR_EWARN                     *((volatile  uint8_t *)(0x42C40058UL))
#define bFM_CAN0_STATR_BOFF                       *((volatile  uint8_t *)(0x42C4005CUL))
#define bFM4_CAN0_STATR_BOFF                      *((volatile  uint8_t *)(0x42C4005CUL))

#define bFM_CAN0_TESTR_BASIC                      *((volatile  uint8_t *)(0x42C40148UL))
#define bFM4_CAN0_TESTR_BASIC                     *((volatile  uint8_t *)(0x42C40148UL))
#define bFM_CAN0_TESTR_SILENT                     *((volatile  uint8_t *)(0x42C4014CUL))
#define bFM4_CAN0_TESTR_SILENT                    *((volatile  uint8_t *)(0x42C4014CUL))
#define bFM_CAN0_TESTR_LBACK                      *((volatile  uint8_t *)(0x42C40150UL))
#define bFM4_CAN0_TESTR_LBACK                     *((volatile  uint8_t *)(0x42C40150UL))
#define bFM_CAN0_TESTR_RX                         *((volatile  uint8_t *)(0x42C4015CUL))
#define bFM4_CAN0_TESTR_RX                        *((volatile  uint8_t *)(0x42C4015CUL))

#define bFM_CAN0_TREQR_TXRQST1                    *((volatile  uint8_t *)(0x42C41000UL))
#define bFM4_CAN0_TREQR_TXRQST1                   *((volatile  uint8_t *)(0x42C41000UL))
#define bFM_CAN0_TREQR_TXRQST2                    *((volatile  uint8_t *)(0x42C41004UL))
#define bFM4_CAN0_TREQR_TXRQST2                   *((volatile  uint8_t *)(0x42C41004UL))
#define bFM_CAN0_TREQR_TXRQST3                    *((volatile  uint8_t *)(0x42C41008UL))
#define bFM4_CAN0_TREQR_TXRQST3                   *((volatile  uint8_t *)(0x42C41008UL))
#define bFM_CAN0_TREQR_TXRQST4                    *((volatile  uint8_t *)(0x42C4100CUL))
#define bFM4_CAN0_TREQR_TXRQST4                   *((volatile  uint8_t *)(0x42C4100CUL))
#define bFM_CAN0_TREQR_TXRQST5                    *((volatile  uint8_t *)(0x42C41010UL))
#define bFM4_CAN0_TREQR_TXRQST5                   *((volatile  uint8_t *)(0x42C41010UL))
#define bFM_CAN0_TREQR_TXRQST6                    *((volatile  uint8_t *)(0x42C41014UL))
#define bFM4_CAN0_TREQR_TXRQST6                   *((volatile  uint8_t *)(0x42C41014UL))
#define bFM_CAN0_TREQR_TXRQST7                    *((volatile  uint8_t *)(0x42C41018UL))
#define bFM4_CAN0_TREQR_TXRQST7                   *((volatile  uint8_t *)(0x42C41018UL))
#define bFM_CAN0_TREQR_TXRQST8                    *((volatile  uint8_t *)(0x42C4101CUL))
#define bFM4_CAN0_TREQR_TXRQST8                   *((volatile  uint8_t *)(0x42C4101CUL))
#define bFM_CAN0_TREQR_TXRQST9                    *((volatile  uint8_t *)(0x42C41020UL))
#define bFM4_CAN0_TREQR_TXRQST9                   *((volatile  uint8_t *)(0x42C41020UL))
#define bFM_CAN0_TREQR_TXRQST10                   *((volatile  uint8_t *)(0x42C41024UL))
#define bFM4_CAN0_TREQR_TXRQST10                  *((volatile  uint8_t *)(0x42C41024UL))
#define bFM_CAN0_TREQR_TXRQST11                   *((volatile  uint8_t *)(0x42C41028UL))
#define bFM4_CAN0_TREQR_TXRQST11                  *((volatile  uint8_t *)(0x42C41028UL))
#define bFM_CAN0_TREQR_TXRQST12                   *((volatile  uint8_t *)(0x42C4102CUL))
#define bFM4_CAN0_TREQR_TXRQST12                  *((volatile  uint8_t *)(0x42C4102CUL))
#define bFM_CAN0_TREQR_TXRQST13                   *((volatile  uint8_t *)(0x42C41030UL))
#define bFM4_CAN0_TREQR_TXRQST13                  *((volatile  uint8_t *)(0x42C41030UL))
#define bFM_CAN0_TREQR_TXRQST14                   *((volatile  uint8_t *)(0x42C41034UL))
#define bFM4_CAN0_TREQR_TXRQST14                  *((volatile  uint8_t *)(0x42C41034UL))
#define bFM_CAN0_TREQR_TXRQST15                   *((volatile  uint8_t *)(0x42C41038UL))
#define bFM4_CAN0_TREQR_TXRQST15                  *((volatile  uint8_t *)(0x42C41038UL))
#define bFM_CAN0_TREQR_TXRQST16                   *((volatile  uint8_t *)(0x42C4103CUL))
#define bFM4_CAN0_TREQR_TXRQST16                  *((volatile  uint8_t *)(0x42C4103CUL))
#define bFM_CAN0_TREQR_TXRQST17                   *((volatile  uint8_t *)(0x42C41040UL))
#define bFM4_CAN0_TREQR_TXRQST17                  *((volatile  uint8_t *)(0x42C41040UL))
#define bFM_CAN0_TREQR_TXRQST18                   *((volatile  uint8_t *)(0x42C41044UL))
#define bFM4_CAN0_TREQR_TXRQST18                  *((volatile  uint8_t *)(0x42C41044UL))
#define bFM_CAN0_TREQR_TXRQST19                   *((volatile  uint8_t *)(0x42C41048UL))
#define bFM4_CAN0_TREQR_TXRQST19                  *((volatile  uint8_t *)(0x42C41048UL))
#define bFM_CAN0_TREQR_TXRQST20                   *((volatile  uint8_t *)(0x42C4104CUL))
#define bFM4_CAN0_TREQR_TXRQST20                  *((volatile  uint8_t *)(0x42C4104CUL))
#define bFM_CAN0_TREQR_TXRQST21                   *((volatile  uint8_t *)(0x42C41050UL))
#define bFM4_CAN0_TREQR_TXRQST21                  *((volatile  uint8_t *)(0x42C41050UL))
#define bFM_CAN0_TREQR_TXRQST22                   *((volatile  uint8_t *)(0x42C41054UL))
#define bFM4_CAN0_TREQR_TXRQST22                  *((volatile  uint8_t *)(0x42C41054UL))
#define bFM_CAN0_TREQR_TXRQST23                   *((volatile  uint8_t *)(0x42C41058UL))
#define bFM4_CAN0_TREQR_TXRQST23                  *((volatile  uint8_t *)(0x42C41058UL))
#define bFM_CAN0_TREQR_TXRQST24                   *((volatile  uint8_t *)(0x42C4105CUL))
#define bFM4_CAN0_TREQR_TXRQST24                  *((volatile  uint8_t *)(0x42C4105CUL))
#define bFM_CAN0_TREQR_TXRQST25                   *((volatile  uint8_t *)(0x42C41060UL))
#define bFM4_CAN0_TREQR_TXRQST25                  *((volatile  uint8_t *)(0x42C41060UL))
#define bFM_CAN0_TREQR_TXRQST26                   *((volatile  uint8_t *)(0x42C41064UL))
#define bFM4_CAN0_TREQR_TXRQST26                  *((volatile  uint8_t *)(0x42C41064UL))
#define bFM_CAN0_TREQR_TXRQST27                   *((volatile  uint8_t *)(0x42C41068UL))
#define bFM4_CAN0_TREQR_TXRQST27                  *((volatile  uint8_t *)(0x42C41068UL))
#define bFM_CAN0_TREQR_TXRQST28                   *((volatile  uint8_t *)(0x42C4106CUL))
#define bFM4_CAN0_TREQR_TXRQST28                  *((volatile  uint8_t *)(0x42C4106CUL))
#define bFM_CAN0_TREQR_TXRQST29                   *((volatile  uint8_t *)(0x42C41070UL))
#define bFM4_CAN0_TREQR_TXRQST29                  *((volatile  uint8_t *)(0x42C41070UL))
#define bFM_CAN0_TREQR_TXRQST30                   *((volatile  uint8_t *)(0x42C41074UL))
#define bFM4_CAN0_TREQR_TXRQST30                  *((volatile  uint8_t *)(0x42C41074UL))
#define bFM_CAN0_TREQR_TXRQST31                   *((volatile  uint8_t *)(0x42C41078UL))
#define bFM4_CAN0_TREQR_TXRQST31                  *((volatile  uint8_t *)(0x42C41078UL))
#define bFM_CAN0_TREQR_TXRQST32                   *((volatile  uint8_t *)(0x42C4107CUL))
#define bFM4_CAN0_TREQR_TXRQST32                  *((volatile  uint8_t *)(0x42C4107CUL))


/*******************************************************************************
* CAN Registers CAN1
*   Bitband Section
*******************************************************************************/
#define bFM_CAN1_CTRLR_INIT                       *((volatile  uint8_t *)(0x42C60000UL))
#define bFM4_CAN1_CTRLR_INIT                      *((volatile  uint8_t *)(0x42C60000UL))
#define bFM_CAN1_CTRLR_IE                         *((volatile  uint8_t *)(0x42C60004UL))
#define bFM4_CAN1_CTRLR_IE                        *((volatile  uint8_t *)(0x42C60004UL))
#define bFM_CAN1_CTRLR_SIE                        *((volatile  uint8_t *)(0x42C60008UL))
#define bFM4_CAN1_CTRLR_SIE                       *((volatile  uint8_t *)(0x42C60008UL))
#define bFM_CAN1_CTRLR_EIE                        *((volatile  uint8_t *)(0x42C6000CUL))
#define bFM4_CAN1_CTRLR_EIE                       *((volatile  uint8_t *)(0x42C6000CUL))
#define bFM_CAN1_CTRLR_DAR                        *((volatile  uint8_t *)(0x42C60014UL))
#define bFM4_CAN1_CTRLR_DAR                       *((volatile  uint8_t *)(0x42C60014UL))
#define bFM_CAN1_CTRLR_CCE                        *((volatile  uint8_t *)(0x42C60018UL))
#define bFM4_CAN1_CTRLR_CCE                       *((volatile  uint8_t *)(0x42C60018UL))
#define bFM_CAN1_CTRLR_TEST                       *((volatile  uint8_t *)(0x42C6001CUL))
#define bFM4_CAN1_CTRLR_TEST                      *((volatile  uint8_t *)(0x42C6001CUL))

#define bFM_CAN1_ERRCNT_RP                        *((volatile  uint8_t *)(0x42C600BCUL))
#define bFM4_CAN1_ERRCNT_RP                       *((volatile  uint8_t *)(0x42C600BCUL))

#define bFM_CAN1_IF1ARB_DIR                       *((volatile  uint8_t *)(0x42C60374UL))
#define bFM4_CAN1_IF1ARB_DIR                      *((volatile  uint8_t *)(0x42C60374UL))
#define bFM_CAN1_IF1ARB_XTD                       *((volatile  uint8_t *)(0x42C60378UL))
#define bFM4_CAN1_IF1ARB_XTD                      *((volatile  uint8_t *)(0x42C60378UL))
#define bFM_CAN1_IF1ARB_MSGVAL                    *((volatile  uint8_t *)(0x42C6037CUL))
#define bFM4_CAN1_IF1ARB_MSGVAL                   *((volatile  uint8_t *)(0x42C6037CUL))

#define bFM_CAN1_IF1CMSK_DATAB                    *((volatile  uint8_t *)(0x42C60240UL))
#define bFM4_CAN1_IF1CMSK_DATAB                   *((volatile  uint8_t *)(0x42C60240UL))
#define bFM_CAN1_IF1CMSK_DATAA                    *((volatile  uint8_t *)(0x42C60244UL))
#define bFM4_CAN1_IF1CMSK_DATAA                   *((volatile  uint8_t *)(0x42C60244UL))
#define bFM_CAN1_IF1CMSK_NEWDAT                   *((volatile  uint8_t *)(0x42C60248UL))
#define bFM4_CAN1_IF1CMSK_NEWDAT                  *((volatile  uint8_t *)(0x42C60248UL))
#define bFM_CAN1_IF1CMSK_CIP                      *((volatile  uint8_t *)(0x42C6024CUL))
#define bFM4_CAN1_IF1CMSK_CIP                     *((volatile  uint8_t *)(0x42C6024CUL))
#define bFM_CAN1_IF1CMSK_CONTROL                  *((volatile  uint8_t *)(0x42C60250UL))
#define bFM4_CAN1_IF1CMSK_CONTROL                 *((volatile  uint8_t *)(0x42C60250UL))
#define bFM_CAN1_IF1CMSK_ARB                      *((volatile  uint8_t *)(0x42C60254UL))
#define bFM4_CAN1_IF1CMSK_ARB                     *((volatile  uint8_t *)(0x42C60254UL))
#define bFM_CAN1_IF1CMSK_MASK                     *((volatile  uint8_t *)(0x42C60258UL))
#define bFM4_CAN1_IF1CMSK_MASK                    *((volatile  uint8_t *)(0x42C60258UL))
#define bFM_CAN1_IF1CMSK_WR_RD                    *((volatile  uint8_t *)(0x42C6025CUL))
#define bFM4_CAN1_IF1CMSK_WR_RD                   *((volatile  uint8_t *)(0x42C6025CUL))

#define bFM_CAN1_IF1CREQ_BUSY                     *((volatile  uint8_t *)(0x42C6023CUL))
#define bFM4_CAN1_IF1CREQ_BUSY                    *((volatile  uint8_t *)(0x42C6023CUL))

#define bFM_CAN1_IF1MCTR_EOB                      *((volatile  uint8_t *)(0x42C6039CUL))
#define bFM4_CAN1_IF1MCTR_EOB                     *((volatile  uint8_t *)(0x42C6039CUL))
#define bFM_CAN1_IF1MCTR_TXRQST                   *((volatile  uint8_t *)(0x42C603A0UL))
#define bFM4_CAN1_IF1MCTR_TXRQST                  *((volatile  uint8_t *)(0x42C603A0UL))
#define bFM_CAN1_IF1MCTR_RMTEN                    *((volatile  uint8_t *)(0x42C603A4UL))
#define bFM4_CAN1_IF1MCTR_RMTEN                   *((volatile  uint8_t *)(0x42C603A4UL))
#define bFM_CAN1_IF1MCTR_RXIE                     *((volatile  uint8_t *)(0x42C603A8UL))
#define bFM4_CAN1_IF1MCTR_RXIE                    *((volatile  uint8_t *)(0x42C603A8UL))
#define bFM_CAN1_IF1MCTR_TXIE                     *((volatile  uint8_t *)(0x42C603ACUL))
#define bFM4_CAN1_IF1MCTR_TXIE                    *((volatile  uint8_t *)(0x42C603ACUL))
#define bFM_CAN1_IF1MCTR_UMASK                    *((volatile  uint8_t *)(0x42C603B0UL))
#define bFM4_CAN1_IF1MCTR_UMASK                   *((volatile  uint8_t *)(0x42C603B0UL))
#define bFM_CAN1_IF1MCTR_INTPND                   *((volatile  uint8_t *)(0x42C603B4UL))
#define bFM4_CAN1_IF1MCTR_INTPND                  *((volatile  uint8_t *)(0x42C603B4UL))
#define bFM_CAN1_IF1MCTR_MSGLST                   *((volatile  uint8_t *)(0x42C603B8UL))
#define bFM4_CAN1_IF1MCTR_MSGLST                  *((volatile  uint8_t *)(0x42C603B8UL))
#define bFM_CAN1_IF1MCTR_NEWDAT                   *((volatile  uint8_t *)(0x42C603BCUL))
#define bFM4_CAN1_IF1MCTR_NEWDAT                  *((volatile  uint8_t *)(0x42C603BCUL))

#define bFM_CAN1_IF1MSK_MDIR                      *((volatile  uint8_t *)(0x42C602F8UL))
#define bFM4_CAN1_IF1MSK_MDIR                     *((volatile  uint8_t *)(0x42C602F8UL))
#define bFM_CAN1_IF1MSK_MXTD                      *((volatile  uint8_t *)(0x42C602FCUL))
#define bFM4_CAN1_IF1MSK_MXTD                     *((volatile  uint8_t *)(0x42C602FCUL))

#define bFM_CAN1_IF2ARB_DIR                       *((volatile  uint8_t *)(0x42C60974UL))
#define bFM4_CAN1_IF2ARB_DIR                      *((volatile  uint8_t *)(0x42C60974UL))
#define bFM_CAN1_IF2ARB_XTD                       *((volatile  uint8_t *)(0x42C60978UL))
#define bFM4_CAN1_IF2ARB_XTD                      *((volatile  uint8_t *)(0x42C60978UL))
#define bFM_CAN1_IF2ARB_MSGVAL                    *((volatile  uint8_t *)(0x42C6097CUL))
#define bFM4_CAN1_IF2ARB_MSGVAL                   *((volatile  uint8_t *)(0x42C6097CUL))

#define bFM_CAN1_IF2CMSK_DATAB                    *((volatile  uint8_t *)(0x42C60840UL))
#define bFM4_CAN1_IF2CMSK_DATAB                   *((volatile  uint8_t *)(0x42C60840UL))
#define bFM_CAN1_IF2CMSK_DATAA                    *((volatile  uint8_t *)(0x42C60844UL))
#define bFM4_CAN1_IF2CMSK_DATAA                   *((volatile  uint8_t *)(0x42C60844UL))
#define bFM_CAN1_IF2CMSK_NEWDAT                   *((volatile  uint8_t *)(0x42C60848UL))
#define bFM4_CAN1_IF2CMSK_NEWDAT                  *((volatile  uint8_t *)(0x42C60848UL))
#define bFM_CAN1_IF2CMSK_CIP                      *((volatile  uint8_t *)(0x42C6084CUL))
#define bFM4_CAN1_IF2CMSK_CIP                     *((volatile  uint8_t *)(0x42C6084CUL))
#define bFM_CAN1_IF2CMSK_CONTROL                  *((volatile  uint8_t *)(0x42C60850UL))
#define bFM4_CAN1_IF2CMSK_CONTROL                 *((volatile  uint8_t *)(0x42C60850UL))
#define bFM_CAN1_IF2CMSK_ARB                      *((volatile  uint8_t *)(0x42C60854UL))
#define bFM4_CAN1_IF2CMSK_ARB                     *((volatile  uint8_t *)(0x42C60854UL))
#define bFM_CAN1_IF2CMSK_MASK                     *((volatile  uint8_t *)(0x42C60858UL))
#define bFM4_CAN1_IF2CMSK_MASK                    *((volatile  uint8_t *)(0x42C60858UL))
#define bFM_CAN1_IF2CMSK_WR_RD                    *((volatile  uint8_t *)(0x42C6085CUL))
#define bFM4_CAN1_IF2CMSK_WR_RD                   *((volatile  uint8_t *)(0x42C6085CUL))

#define bFM_CAN1_IF2CREQ_BUSY                     *((volatile  uint8_t *)(0x42C6083CUL))
#define bFM4_CAN1_IF2CREQ_BUSY                    *((volatile  uint8_t *)(0x42C6083CUL))

#define bFM_CAN1_IF2MCTR_EOB                      *((volatile  uint8_t *)(0x42C6099CUL))
#define bFM4_CAN1_IF2MCTR_EOB                     *((volatile  uint8_t *)(0x42C6099CUL))
#define bFM_CAN1_IF2MCTR_TXRQST                   *((volatile  uint8_t *)(0x42C609A0UL))
#define bFM4_CAN1_IF2MCTR_TXRQST                  *((volatile  uint8_t *)(0x42C609A0UL))
#define bFM_CAN1_IF2MCTR_RMTEN                    *((volatile  uint8_t *)(0x42C609A4UL))
#define bFM4_CAN1_IF2MCTR_RMTEN                   *((volatile  uint8_t *)(0x42C609A4UL))
#define bFM_CAN1_IF2MCTR_RXIE                     *((volatile  uint8_t *)(0x42C609A8UL))
#define bFM4_CAN1_IF2MCTR_RXIE                    *((volatile  uint8_t *)(0x42C609A8UL))
#define bFM_CAN1_IF2MCTR_TXIE                     *((volatile  uint8_t *)(0x42C609ACUL))
#define bFM4_CAN1_IF2MCTR_TXIE                    *((volatile  uint8_t *)(0x42C609ACUL))
#define bFM_CAN1_IF2MCTR_UMASK                    *((volatile  uint8_t *)(0x42C609B0UL))
#define bFM4_CAN1_IF2MCTR_UMASK                   *((volatile  uint8_t *)(0x42C609B0UL))
#define bFM_CAN1_IF2MCTR_INTPND                   *((volatile  uint8_t *)(0x42C609B4UL))
#define bFM4_CAN1_IF2MCTR_INTPND                  *((volatile  uint8_t *)(0x42C609B4UL))
#define bFM_CAN1_IF2MCTR_MSGLST                   *((volatile  uint8_t *)(0x42C609B8UL))
#define bFM4_CAN1_IF2MCTR_MSGLST                  *((volatile  uint8_t *)(0x42C609B8UL))
#define bFM_CAN1_IF2MCTR_NEWDAT                   *((volatile  uint8_t *)(0x42C609BCUL))
#define bFM4_CAN1_IF2MCTR_NEWDAT                  *((volatile  uint8_t *)(0x42C609BCUL))

#define bFM_CAN1_IF2MSK_MDIR                      *((volatile  uint8_t *)(0x42C608F8UL))
#define bFM4_CAN1_IF2MSK_MDIR                     *((volatile  uint8_t *)(0x42C608F8UL))
#define bFM_CAN1_IF2MSK_MXTD                      *((volatile  uint8_t *)(0x42C608FCUL))
#define bFM4_CAN1_IF2MSK_MXTD                     *((volatile  uint8_t *)(0x42C608FCUL))

#define bFM_CAN1_INTPND_INTPND1                   *((volatile  uint8_t *)(0x42C61400UL))
#define bFM4_CAN1_INTPND_INTPND1                  *((volatile  uint8_t *)(0x42C61400UL))
#define bFM_CAN1_INTPND_INTPND2                   *((volatile  uint8_t *)(0x42C61404UL))
#define bFM4_CAN1_INTPND_INTPND2                  *((volatile  uint8_t *)(0x42C61404UL))
#define bFM_CAN1_INTPND_INTPND3                   *((volatile  uint8_t *)(0x42C61408UL))
#define bFM4_CAN1_INTPND_INTPND3                  *((volatile  uint8_t *)(0x42C61408UL))
#define bFM_CAN1_INTPND_INTPND4                   *((volatile  uint8_t *)(0x42C6140CUL))
#define bFM4_CAN1_INTPND_INTPND4                  *((volatile  uint8_t *)(0x42C6140CUL))
#define bFM_CAN1_INTPND_INTPND5                   *((volatile  uint8_t *)(0x42C61410UL))
#define bFM4_CAN1_INTPND_INTPND5                  *((volatile  uint8_t *)(0x42C61410UL))
#define bFM_CAN1_INTPND_INTPND6                   *((volatile  uint8_t *)(0x42C61414UL))
#define bFM4_CAN1_INTPND_INTPND6                  *((volatile  uint8_t *)(0x42C61414UL))
#define bFM_CAN1_INTPND_INTPND7                   *((volatile  uint8_t *)(0x42C61418UL))
#define bFM4_CAN1_INTPND_INTPND7                  *((volatile  uint8_t *)(0x42C61418UL))
#define bFM_CAN1_INTPND_INTPND8                   *((volatile  uint8_t *)(0x42C6141CUL))
#define bFM4_CAN1_INTPND_INTPND8                  *((volatile  uint8_t *)(0x42C6141CUL))
#define bFM_CAN1_INTPND_INTPND9                   *((volatile  uint8_t *)(0x42C61420UL))
#define bFM4_CAN1_INTPND_INTPND9                  *((volatile  uint8_t *)(0x42C61420UL))
#define bFM_CAN1_INTPND_INTPND10                  *((volatile  uint8_t *)(0x42C61424UL))
#define bFM4_CAN1_INTPND_INTPND10                 *((volatile  uint8_t *)(0x42C61424UL))
#define bFM_CAN1_INTPND_INTPND11                  *((volatile  uint8_t *)(0x42C61428UL))
#define bFM4_CAN1_INTPND_INTPND11                 *((volatile  uint8_t *)(0x42C61428UL))
#define bFM_CAN1_INTPND_INTPND12                  *((volatile  uint8_t *)(0x42C6142CUL))
#define bFM4_CAN1_INTPND_INTPND12                 *((volatile  uint8_t *)(0x42C6142CUL))
#define bFM_CAN1_INTPND_INTPND13                  *((volatile  uint8_t *)(0x42C61430UL))
#define bFM4_CAN1_INTPND_INTPND13                 *((volatile  uint8_t *)(0x42C61430UL))
#define bFM_CAN1_INTPND_INTPND14                  *((volatile  uint8_t *)(0x42C61434UL))
#define bFM4_CAN1_INTPND_INTPND14                 *((volatile  uint8_t *)(0x42C61434UL))
#define bFM_CAN1_INTPND_INTPND15                  *((volatile  uint8_t *)(0x42C61438UL))
#define bFM4_CAN1_INTPND_INTPND15                 *((volatile  uint8_t *)(0x42C61438UL))
#define bFM_CAN1_INTPND_INTPND16                  *((volatile  uint8_t *)(0x42C6143CUL))
#define bFM4_CAN1_INTPND_INTPND16                 *((volatile  uint8_t *)(0x42C6143CUL))
#define bFM_CAN1_INTPND_INTPND17                  *((volatile  uint8_t *)(0x42C61440UL))
#define bFM4_CAN1_INTPND_INTPND17                 *((volatile  uint8_t *)(0x42C61440UL))
#define bFM_CAN1_INTPND_INTPND18                  *((volatile  uint8_t *)(0x42C61444UL))
#define bFM4_CAN1_INTPND_INTPND18                 *((volatile  uint8_t *)(0x42C61444UL))
#define bFM_CAN1_INTPND_INTPND19                  *((volatile  uint8_t *)(0x42C61448UL))
#define bFM4_CAN1_INTPND_INTPND19                 *((volatile  uint8_t *)(0x42C61448UL))
#define bFM_CAN1_INTPND_INTPND20                  *((volatile  uint8_t *)(0x42C6144CUL))
#define bFM4_CAN1_INTPND_INTPND20                 *((volatile  uint8_t *)(0x42C6144CUL))
#define bFM_CAN1_INTPND_INTPND21                  *((volatile  uint8_t *)(0x42C61450UL))
#define bFM4_CAN1_INTPND_INTPND21                 *((volatile  uint8_t *)(0x42C61450UL))
#define bFM_CAN1_INTPND_INTPND22                  *((volatile  uint8_t *)(0x42C61454UL))
#define bFM4_CAN1_INTPND_INTPND22                 *((volatile  uint8_t *)(0x42C61454UL))
#define bFM_CAN1_INTPND_INTPND23                  *((volatile  uint8_t *)(0x42C61458UL))
#define bFM4_CAN1_INTPND_INTPND23                 *((volatile  uint8_t *)(0x42C61458UL))
#define bFM_CAN1_INTPND_INTPND24                  *((volatile  uint8_t *)(0x42C6145CUL))
#define bFM4_CAN1_INTPND_INTPND24                 *((volatile  uint8_t *)(0x42C6145CUL))
#define bFM_CAN1_INTPND_INTPND25                  *((volatile  uint8_t *)(0x42C61460UL))
#define bFM4_CAN1_INTPND_INTPND25                 *((volatile  uint8_t *)(0x42C61460UL))
#define bFM_CAN1_INTPND_INTPND26                  *((volatile  uint8_t *)(0x42C61464UL))
#define bFM4_CAN1_INTPND_INTPND26                 *((volatile  uint8_t *)(0x42C61464UL))
#define bFM_CAN1_INTPND_INTPND27                  *((volatile  uint8_t *)(0x42C61468UL))
#define bFM4_CAN1_INTPND_INTPND27                 *((volatile  uint8_t *)(0x42C61468UL))
#define bFM_CAN1_INTPND_INTPND28                  *((volatile  uint8_t *)(0x42C6146CUL))
#define bFM4_CAN1_INTPND_INTPND28                 *((volatile  uint8_t *)(0x42C6146CUL))
#define bFM_CAN1_INTPND_INTPND29                  *((volatile  uint8_t *)(0x42C61470UL))
#define bFM4_CAN1_INTPND_INTPND29                 *((volatile  uint8_t *)(0x42C61470UL))
#define bFM_CAN1_INTPND_INTPND30                  *((volatile  uint8_t *)(0x42C61474UL))
#define bFM4_CAN1_INTPND_INTPND30                 *((volatile  uint8_t *)(0x42C61474UL))
#define bFM_CAN1_INTPND_INTPND31                  *((volatile  uint8_t *)(0x42C61478UL))
#define bFM4_CAN1_INTPND_INTPND31                 *((volatile  uint8_t *)(0x42C61478UL))
#define bFM_CAN1_INTPND_INTPND32                  *((volatile  uint8_t *)(0x42C6147CUL))
#define bFM4_CAN1_INTPND_INTPND32                 *((volatile  uint8_t *)(0x42C6147CUL))

#define bFM_CAN1_MSGVAL_MSGVAL1                   *((volatile  uint8_t *)(0x42C61600UL))
#define bFM4_CAN1_MSGVAL_MSGVAL1                  *((volatile  uint8_t *)(0x42C61600UL))
#define bFM_CAN1_MSGVAL_MSGVAL2                   *((volatile  uint8_t *)(0x42C61604UL))
#define bFM4_CAN1_MSGVAL_MSGVAL2                  *((volatile  uint8_t *)(0x42C61604UL))
#define bFM_CAN1_MSGVAL_MSGVAL3                   *((volatile  uint8_t *)(0x42C61608UL))
#define bFM4_CAN1_MSGVAL_MSGVAL3                  *((volatile  uint8_t *)(0x42C61608UL))
#define bFM_CAN1_MSGVAL_MSGVAL4                   *((volatile  uint8_t *)(0x42C6160CUL))
#define bFM4_CAN1_MSGVAL_MSGVAL4                  *((volatile  uint8_t *)(0x42C6160CUL))
#define bFM_CAN1_MSGVAL_MSGVAL5                   *((volatile  uint8_t *)(0x42C61610UL))
#define bFM4_CAN1_MSGVAL_MSGVAL5                  *((volatile  uint8_t *)(0x42C61610UL))
#define bFM_CAN1_MSGVAL_MSGVAL6                   *((volatile  uint8_t *)(0x42C61614UL))
#define bFM4_CAN1_MSGVAL_MSGVAL6                  *((volatile  uint8_t *)(0x42C61614UL))
#define bFM_CAN1_MSGVAL_MSGVAL7                   *((volatile  uint8_t *)(0x42C61618UL))
#define bFM4_CAN1_MSGVAL_MSGVAL7                  *((volatile  uint8_t *)(0x42C61618UL))
#define bFM_CAN1_MSGVAL_MSGVAL8                   *((volatile  uint8_t *)(0x42C6161CUL))
#define bFM4_CAN1_MSGVAL_MSGVAL8                  *((volatile  uint8_t *)(0x42C6161CUL))
#define bFM_CAN1_MSGVAL_MSGVAL9                   *((volatile  uint8_t *)(0x42C61620UL))
#define bFM4_CAN1_MSGVAL_MSGVAL9                  *((volatile  uint8_t *)(0x42C61620UL))
#define bFM_CAN1_MSGVAL_MSGVAL10                  *((volatile  uint8_t *)(0x42C61624UL))
#define bFM4_CAN1_MSGVAL_MSGVAL10                 *((volatile  uint8_t *)(0x42C61624UL))
#define bFM_CAN1_MSGVAL_MSGVAL11                  *((volatile  uint8_t *)(0x42C61628UL))
#define bFM4_CAN1_MSGVAL_MSGVAL11                 *((volatile  uint8_t *)(0x42C61628UL))
#define bFM_CAN1_MSGVAL_MSGVAL12                  *((volatile  uint8_t *)(0x42C6162CUL))
#define bFM4_CAN1_MSGVAL_MSGVAL12                 *((volatile  uint8_t *)(0x42C6162CUL))
#define bFM_CAN1_MSGVAL_MSGVAL13                  *((volatile  uint8_t *)(0x42C61630UL))
#define bFM4_CAN1_MSGVAL_MSGVAL13                 *((volatile  uint8_t *)(0x42C61630UL))
#define bFM_CAN1_MSGVAL_MSGVAL14                  *((volatile  uint8_t *)(0x42C61634UL))
#define bFM4_CAN1_MSGVAL_MSGVAL14                 *((volatile  uint8_t *)(0x42C61634UL))
#define bFM_CAN1_MSGVAL_MSGVAL15                  *((volatile  uint8_t *)(0x42C61638UL))
#define bFM4_CAN1_MSGVAL_MSGVAL15                 *((volatile  uint8_t *)(0x42C61638UL))
#define bFM_CAN1_MSGVAL_MSGVAL16                  *((volatile  uint8_t *)(0x42C6163CUL))
#define bFM4_CAN1_MSGVAL_MSGVAL16                 *((volatile  uint8_t *)(0x42C6163CUL))
#define bFM_CAN1_MSGVAL_MSGVAL17                  *((volatile  uint8_t *)(0x42C61640UL))
#define bFM4_CAN1_MSGVAL_MSGVAL17                 *((volatile  uint8_t *)(0x42C61640UL))
#define bFM_CAN1_MSGVAL_MSGVAL18                  *((volatile  uint8_t *)(0x42C61644UL))
#define bFM4_CAN1_MSGVAL_MSGVAL18                 *((volatile  uint8_t *)(0x42C61644UL))
#define bFM_CAN1_MSGVAL_MSGVAL19                  *((volatile  uint8_t *)(0x42C61648UL))
#define bFM4_CAN1_MSGVAL_MSGVAL19                 *((volatile  uint8_t *)(0x42C61648UL))
#define bFM_CAN1_MSGVAL_MSGVAL20                  *((volatile  uint8_t *)(0x42C6164CUL))
#define bFM4_CAN1_MSGVAL_MSGVAL20                 *((volatile  uint8_t *)(0x42C6164CUL))
#define bFM_CAN1_MSGVAL_MSGVAL21                  *((volatile  uint8_t *)(0x42C61650UL))
#define bFM4_CAN1_MSGVAL_MSGVAL21                 *((volatile  uint8_t *)(0x42C61650UL))
#define bFM_CAN1_MSGVAL_MSGVAL22                  *((volatile  uint8_t *)(0x42C61654UL))
#define bFM4_CAN1_MSGVAL_MSGVAL22                 *((volatile  uint8_t *)(0x42C61654UL))
#define bFM_CAN1_MSGVAL_MSGVAL23                  *((volatile  uint8_t *)(0x42C61658UL))
#define bFM4_CAN1_MSGVAL_MSGVAL23                 *((volatile  uint8_t *)(0x42C61658UL))
#define bFM_CAN1_MSGVAL_MSGVAL24                  *((volatile  uint8_t *)(0x42C6165CUL))
#define bFM4_CAN1_MSGVAL_MSGVAL24                 *((volatile  uint8_t *)(0x42C6165CUL))
#define bFM_CAN1_MSGVAL_MSGVAL25                  *((volatile  uint8_t *)(0x42C61660UL))
#define bFM4_CAN1_MSGVAL_MSGVAL25                 *((volatile  uint8_t *)(0x42C61660UL))
#define bFM_CAN1_MSGVAL_MSGVAL26                  *((volatile  uint8_t *)(0x42C61664UL))
#define bFM4_CAN1_MSGVAL_MSGVAL26                 *((volatile  uint8_t *)(0x42C61664UL))
#define bFM_CAN1_MSGVAL_MSGVAL27                  *((volatile  uint8_t *)(0x42C61668UL))
#define bFM4_CAN1_MSGVAL_MSGVAL27                 *((volatile  uint8_t *)(0x42C61668UL))
#define bFM_CAN1_MSGVAL_MSGVAL28                  *((volatile  uint8_t *)(0x42C6166CUL))
#define bFM4_CAN1_MSGVAL_MSGVAL28                 *((volatile  uint8_t *)(0x42C6166CUL))
#define bFM_CAN1_MSGVAL_MSGVAL29                  *((volatile  uint8_t *)(0x42C61670UL))
#define bFM4_CAN1_MSGVAL_MSGVAL29                 *((volatile  uint8_t *)(0x42C61670UL))
#define bFM_CAN1_MSGVAL_MSGVAL30                  *((volatile  uint8_t *)(0x42C61674UL))
#define bFM4_CAN1_MSGVAL_MSGVAL30                 *((volatile  uint8_t *)(0x42C61674UL))
#define bFM_CAN1_MSGVAL_MSGVAL31                  *((volatile  uint8_t *)(0x42C61678UL))
#define bFM4_CAN1_MSGVAL_MSGVAL31                 *((volatile  uint8_t *)(0x42C61678UL))
#define bFM_CAN1_MSGVAL_MSGVAL32                  *((volatile  uint8_t *)(0x42C6167CUL))
#define bFM4_CAN1_MSGVAL_MSGVAL32                 *((volatile  uint8_t *)(0x42C6167CUL))

#define bFM_CAN1_NEWDT_NEWDAT1                    *((volatile  uint8_t *)(0x42C61200UL))
#define bFM4_CAN1_NEWDT_NEWDAT1                   *((volatile  uint8_t *)(0x42C61200UL))
#define bFM_CAN1_NEWDT_NEWDAT2                    *((volatile  uint8_t *)(0x42C61204UL))
#define bFM4_CAN1_NEWDT_NEWDAT2                   *((volatile  uint8_t *)(0x42C61204UL))
#define bFM_CAN1_NEWDT_NEWDAT3                    *((volatile  uint8_t *)(0x42C61208UL))
#define bFM4_CAN1_NEWDT_NEWDAT3                   *((volatile  uint8_t *)(0x42C61208UL))
#define bFM_CAN1_NEWDT_NEWDAT4                    *((volatile  uint8_t *)(0x42C6120CUL))
#define bFM4_CAN1_NEWDT_NEWDAT4                   *((volatile  uint8_t *)(0x42C6120CUL))
#define bFM_CAN1_NEWDT_NEWDAT5                    *((volatile  uint8_t *)(0x42C61210UL))
#define bFM4_CAN1_NEWDT_NEWDAT5                   *((volatile  uint8_t *)(0x42C61210UL))
#define bFM_CAN1_NEWDT_NEWDAT6                    *((volatile  uint8_t *)(0x42C61214UL))
#define bFM4_CAN1_NEWDT_NEWDAT6                   *((volatile  uint8_t *)(0x42C61214UL))
#define bFM_CAN1_NEWDT_NEWDAT7                    *((volatile  uint8_t *)(0x42C61218UL))
#define bFM4_CAN1_NEWDT_NEWDAT7                   *((volatile  uint8_t *)(0x42C61218UL))
#define bFM_CAN1_NEWDT_NEWDAT8                    *((volatile  uint8_t *)(0x42C6121CUL))
#define bFM4_CAN1_NEWDT_NEWDAT8                   *((volatile  uint8_t *)(0x42C6121CUL))
#define bFM_CAN1_NEWDT_NEWDAT9                    *((volatile  uint8_t *)(0x42C61220UL))
#define bFM4_CAN1_NEWDT_NEWDAT9                   *((volatile  uint8_t *)(0x42C61220UL))
#define bFM_CAN1_NEWDT_NEWDAT10                   *((volatile  uint8_t *)(0x42C61224UL))
#define bFM4_CAN1_NEWDT_NEWDAT10                  *((volatile  uint8_t *)(0x42C61224UL))
#define bFM_CAN1_NEWDT_NEWDAT11                   *((volatile  uint8_t *)(0x42C61228UL))
#define bFM4_CAN1_NEWDT_NEWDAT11                  *((volatile  uint8_t *)(0x42C61228UL))
#define bFM_CAN1_NEWDT_NEWDAT12                   *((volatile  uint8_t *)(0x42C6122CUL))
#define bFM4_CAN1_NEWDT_NEWDAT12                  *((volatile  uint8_t *)(0x42C6122CUL))
#define bFM_CAN1_NEWDT_NEWDAT13                   *((volatile  uint8_t *)(0x42C61230UL))
#define bFM4_CAN1_NEWDT_NEWDAT13                  *((volatile  uint8_t *)(0x42C61230UL))
#define bFM_CAN1_NEWDT_NEWDAT14                   *((volatile  uint8_t *)(0x42C61234UL))
#define bFM4_CAN1_NEWDT_NEWDAT14                  *((volatile  uint8_t *)(0x42C61234UL))
#define bFM_CAN1_NEWDT_NEWDAT15                   *((volatile  uint8_t *)(0x42C61238UL))
#define bFM4_CAN1_NEWDT_NEWDAT15                  *((volatile  uint8_t *)(0x42C61238UL))
#define bFM_CAN1_NEWDT_NEWDAT16                   *((volatile  uint8_t *)(0x42C6123CUL))
#define bFM4_CAN1_NEWDT_NEWDAT16                  *((volatile  uint8_t *)(0x42C6123CUL))
#define bFM_CAN1_NEWDT_NEWDAT17                   *((volatile  uint8_t *)(0x42C61240UL))
#define bFM4_CAN1_NEWDT_NEWDAT17                  *((volatile  uint8_t *)(0x42C61240UL))
#define bFM_CAN1_NEWDT_NEWDAT18                   *((volatile  uint8_t *)(0x42C61244UL))
#define bFM4_CAN1_NEWDT_NEWDAT18                  *((volatile  uint8_t *)(0x42C61244UL))
#define bFM_CAN1_NEWDT_NEWDAT19                   *((volatile  uint8_t *)(0x42C61248UL))
#define bFM4_CAN1_NEWDT_NEWDAT19                  *((volatile  uint8_t *)(0x42C61248UL))
#define bFM_CAN1_NEWDT_NEWDAT20                   *((volatile  uint8_t *)(0x42C6124CUL))
#define bFM4_CAN1_NEWDT_NEWDAT20                  *((volatile  uint8_t *)(0x42C6124CUL))
#define bFM_CAN1_NEWDT_NEWDAT21                   *((volatile  uint8_t *)(0x42C61250UL))
#define bFM4_CAN1_NEWDT_NEWDAT21                  *((volatile  uint8_t *)(0x42C61250UL))
#define bFM_CAN1_NEWDT_NEWDAT22                   *((volatile  uint8_t *)(0x42C61254UL))
#define bFM4_CAN1_NEWDT_NEWDAT22                  *((volatile  uint8_t *)(0x42C61254UL))
#define bFM_CAN1_NEWDT_NEWDAT23                   *((volatile  uint8_t *)(0x42C61258UL))
#define bFM4_CAN1_NEWDT_NEWDAT23                  *((volatile  uint8_t *)(0x42C61258UL))
#define bFM_CAN1_NEWDT_NEWDAT24                   *((volatile  uint8_t *)(0x42C6125CUL))
#define bFM4_CAN1_NEWDT_NEWDAT24                  *((volatile  uint8_t *)(0x42C6125CUL))
#define bFM_CAN1_NEWDT_NEWDAT25                   *((volatile  uint8_t *)(0x42C61260UL))
#define bFM4_CAN1_NEWDT_NEWDAT25                  *((volatile  uint8_t *)(0x42C61260UL))
#define bFM_CAN1_NEWDT_NEWDAT26                   *((volatile  uint8_t *)(0x42C61264UL))
#define bFM4_CAN1_NEWDT_NEWDAT26                  *((volatile  uint8_t *)(0x42C61264UL))
#define bFM_CAN1_NEWDT_NEWDAT27                   *((volatile  uint8_t *)(0x42C61268UL))
#define bFM4_CAN1_NEWDT_NEWDAT27                  *((volatile  uint8_t *)(0x42C61268UL))
#define bFM_CAN1_NEWDT_NEWDAT28                   *((volatile  uint8_t *)(0x42C6126CUL))
#define bFM4_CAN1_NEWDT_NEWDAT28                  *((volatile  uint8_t *)(0x42C6126CUL))
#define bFM_CAN1_NEWDT_NEWDAT29                   *((volatile  uint8_t *)(0x42C61270UL))
#define bFM4_CAN1_NEWDT_NEWDAT29                  *((volatile  uint8_t *)(0x42C61270UL))
#define bFM_CAN1_NEWDT_NEWDAT30                   *((volatile  uint8_t *)(0x42C61274UL))
#define bFM4_CAN1_NEWDT_NEWDAT30                  *((volatile  uint8_t *)(0x42C61274UL))
#define bFM_CAN1_NEWDT_NEWDAT31                   *((volatile  uint8_t *)(0x42C61278UL))
#define bFM4_CAN1_NEWDT_NEWDAT31                  *((volatile  uint8_t *)(0x42C61278UL))
#define bFM_CAN1_NEWDT_NEWDAT32                   *((volatile  uint8_t *)(0x42C6127CUL))
#define bFM4_CAN1_NEWDT_NEWDAT32                  *((volatile  uint8_t *)(0x42C6127CUL))

#define bFM_CAN1_STATR_TXOK                       *((volatile  uint8_t *)(0x42C6004CUL))
#define bFM4_CAN1_STATR_TXOK                      *((volatile  uint8_t *)(0x42C6004CUL))
#define bFM_CAN1_STATR_RXOK                       *((volatile  uint8_t *)(0x42C60050UL))
#define bFM4_CAN1_STATR_RXOK                      *((volatile  uint8_t *)(0x42C60050UL))
#define bFM_CAN1_STATR_EPASS                      *((volatile  uint8_t *)(0x42C60054UL))
#define bFM4_CAN1_STATR_EPASS                     *((volatile  uint8_t *)(0x42C60054UL))
#define bFM_CAN1_STATR_EWARN                      *((volatile  uint8_t *)(0x42C60058UL))
#define bFM4_CAN1_STATR_EWARN                     *((volatile  uint8_t *)(0x42C60058UL))
#define bFM_CAN1_STATR_BOFF                       *((volatile  uint8_t *)(0x42C6005CUL))
#define bFM4_CAN1_STATR_BOFF                      *((volatile  uint8_t *)(0x42C6005CUL))

#define bFM_CAN1_TESTR_BASIC                      *((volatile  uint8_t *)(0x42C60148UL))
#define bFM4_CAN1_TESTR_BASIC                     *((volatile  uint8_t *)(0x42C60148UL))
#define bFM_CAN1_TESTR_SILENT                     *((volatile  uint8_t *)(0x42C6014CUL))
#define bFM4_CAN1_TESTR_SILENT                    *((volatile  uint8_t *)(0x42C6014CUL))
#define bFM_CAN1_TESTR_LBACK                      *((volatile  uint8_t *)(0x42C60150UL))
#define bFM4_CAN1_TESTR_LBACK                     *((volatile  uint8_t *)(0x42C60150UL))
#define bFM_CAN1_TESTR_RX                         *((volatile  uint8_t *)(0x42C6015CUL))
#define bFM4_CAN1_TESTR_RX                        *((volatile  uint8_t *)(0x42C6015CUL))

#define bFM_CAN1_TREQR_TXRQST1                    *((volatile  uint8_t *)(0x42C61000UL))
#define bFM4_CAN1_TREQR_TXRQST1                   *((volatile  uint8_t *)(0x42C61000UL))
#define bFM_CAN1_TREQR_TXRQST2                    *((volatile  uint8_t *)(0x42C61004UL))
#define bFM4_CAN1_TREQR_TXRQST2                   *((volatile  uint8_t *)(0x42C61004UL))
#define bFM_CAN1_TREQR_TXRQST3                    *((volatile  uint8_t *)(0x42C61008UL))
#define bFM4_CAN1_TREQR_TXRQST3                   *((volatile  uint8_t *)(0x42C61008UL))
#define bFM_CAN1_TREQR_TXRQST4                    *((volatile  uint8_t *)(0x42C6100CUL))
#define bFM4_CAN1_TREQR_TXRQST4                   *((volatile  uint8_t *)(0x42C6100CUL))
#define bFM_CAN1_TREQR_TXRQST5                    *((volatile  uint8_t *)(0x42C61010UL))
#define bFM4_CAN1_TREQR_TXRQST5                   *((volatile  uint8_t *)(0x42C61010UL))
#define bFM_CAN1_TREQR_TXRQST6                    *((volatile  uint8_t *)(0x42C61014UL))
#define bFM4_CAN1_TREQR_TXRQST6                   *((volatile  uint8_t *)(0x42C61014UL))
#define bFM_CAN1_TREQR_TXRQST7                    *((volatile  uint8_t *)(0x42C61018UL))
#define bFM4_CAN1_TREQR_TXRQST7                   *((volatile  uint8_t *)(0x42C61018UL))
#define bFM_CAN1_TREQR_TXRQST8                    *((volatile  uint8_t *)(0x42C6101CUL))
#define bFM4_CAN1_TREQR_TXRQST8                   *((volatile  uint8_t *)(0x42C6101CUL))
#define bFM_CAN1_TREQR_TXRQST9                    *((volatile  uint8_t *)(0x42C61020UL))
#define bFM4_CAN1_TREQR_TXRQST9                   *((volatile  uint8_t *)(0x42C61020UL))
#define bFM_CAN1_TREQR_TXRQST10                   *((volatile  uint8_t *)(0x42C61024UL))
#define bFM4_CAN1_TREQR_TXRQST10                  *((volatile  uint8_t *)(0x42C61024UL))
#define bFM_CAN1_TREQR_TXRQST11                   *((volatile  uint8_t *)(0x42C61028UL))
#define bFM4_CAN1_TREQR_TXRQST11                  *((volatile  uint8_t *)(0x42C61028UL))
#define bFM_CAN1_TREQR_TXRQST12                   *((volatile  uint8_t *)(0x42C6102CUL))
#define bFM4_CAN1_TREQR_TXRQST12                  *((volatile  uint8_t *)(0x42C6102CUL))
#define bFM_CAN1_TREQR_TXRQST13                   *((volatile  uint8_t *)(0x42C61030UL))
#define bFM4_CAN1_TREQR_TXRQST13                  *((volatile  uint8_t *)(0x42C61030UL))
#define bFM_CAN1_TREQR_TXRQST14                   *((volatile  uint8_t *)(0x42C61034UL))
#define bFM4_CAN1_TREQR_TXRQST14                  *((volatile  uint8_t *)(0x42C61034UL))
#define bFM_CAN1_TREQR_TXRQST15                   *((volatile  uint8_t *)(0x42C61038UL))
#define bFM4_CAN1_TREQR_TXRQST15                  *((volatile  uint8_t *)(0x42C61038UL))
#define bFM_CAN1_TREQR_TXRQST16                   *((volatile  uint8_t *)(0x42C6103CUL))
#define bFM4_CAN1_TREQR_TXRQST16                  *((volatile  uint8_t *)(0x42C6103CUL))
#define bFM_CAN1_TREQR_TXRQST17                   *((volatile  uint8_t *)(0x42C61040UL))
#define bFM4_CAN1_TREQR_TXRQST17                  *((volatile  uint8_t *)(0x42C61040UL))
#define bFM_CAN1_TREQR_TXRQST18                   *((volatile  uint8_t *)(0x42C61044UL))
#define bFM4_CAN1_TREQR_TXRQST18                  *((volatile  uint8_t *)(0x42C61044UL))
#define bFM_CAN1_TREQR_TXRQST19                   *((volatile  uint8_t *)(0x42C61048UL))
#define bFM4_CAN1_TREQR_TXRQST19                  *((volatile  uint8_t *)(0x42C61048UL))
#define bFM_CAN1_TREQR_TXRQST20                   *((volatile  uint8_t *)(0x42C6104CUL))
#define bFM4_CAN1_TREQR_TXRQST20                  *((volatile  uint8_t *)(0x42C6104CUL))
#define bFM_CAN1_TREQR_TXRQST21                   *((volatile  uint8_t *)(0x42C61050UL))
#define bFM4_CAN1_TREQR_TXRQST21                  *((volatile  uint8_t *)(0x42C61050UL))
#define bFM_CAN1_TREQR_TXRQST22                   *((volatile  uint8_t *)(0x42C61054UL))
#define bFM4_CAN1_TREQR_TXRQST22                  *((volatile  uint8_t *)(0x42C61054UL))
#define bFM_CAN1_TREQR_TXRQST23                   *((volatile  uint8_t *)(0x42C61058UL))
#define bFM4_CAN1_TREQR_TXRQST23                  *((volatile  uint8_t *)(0x42C61058UL))
#define bFM_CAN1_TREQR_TXRQST24                   *((volatile  uint8_t *)(0x42C6105CUL))
#define bFM4_CAN1_TREQR_TXRQST24                  *((volatile  uint8_t *)(0x42C6105CUL))
#define bFM_CAN1_TREQR_TXRQST25                   *((volatile  uint8_t *)(0x42C61060UL))
#define bFM4_CAN1_TREQR_TXRQST25                  *((volatile  uint8_t *)(0x42C61060UL))
#define bFM_CAN1_TREQR_TXRQST26                   *((volatile  uint8_t *)(0x42C61064UL))
#define bFM4_CAN1_TREQR_TXRQST26                  *((volatile  uint8_t *)(0x42C61064UL))
#define bFM_CAN1_TREQR_TXRQST27                   *((volatile  uint8_t *)(0x42C61068UL))
#define bFM4_CAN1_TREQR_TXRQST27                  *((volatile  uint8_t *)(0x42C61068UL))
#define bFM_CAN1_TREQR_TXRQST28                   *((volatile  uint8_t *)(0x42C6106CUL))
#define bFM4_CAN1_TREQR_TXRQST28                  *((volatile  uint8_t *)(0x42C6106CUL))
#define bFM_CAN1_TREQR_TXRQST29                   *((volatile  uint8_t *)(0x42C61070UL))
#define bFM4_CAN1_TREQR_TXRQST29                  *((volatile  uint8_t *)(0x42C61070UL))
#define bFM_CAN1_TREQR_TXRQST30                   *((volatile  uint8_t *)(0x42C61074UL))
#define bFM4_CAN1_TREQR_TXRQST30                  *((volatile  uint8_t *)(0x42C61074UL))
#define bFM_CAN1_TREQR_TXRQST31                   *((volatile  uint8_t *)(0x42C61078UL))
#define bFM4_CAN1_TREQR_TXRQST31                  *((volatile  uint8_t *)(0x42C61078UL))
#define bFM_CAN1_TREQR_TXRQST32                   *((volatile  uint8_t *)(0x42C6107CUL))
#define bFM4_CAN1_TREQR_TXRQST32                  *((volatile  uint8_t *)(0x42C6107CUL))


/*******************************************************************************
* CANFD Registers CANFD0
*   Bitband Section
*******************************************************************************/
#define bFM_CANFD0_CCCR_INIT                      *((volatile  uint8_t *)(0x42E00300UL))
#define bFM4_CANFD0_CCCR_INIT                     *((volatile  uint8_t *)(0x42E00300UL))
#define bFM_CANFD0_CCCR_CCE                       *((volatile  uint8_t *)(0x42E00304UL))
#define bFM4_CANFD0_CCCR_CCE                      *((volatile  uint8_t *)(0x42E00304UL))
#define bFM_CANFD0_CCCR_ASM                       *((volatile  uint8_t *)(0x42E00308UL))
#define bFM4_CANFD0_CCCR_ASM                      *((volatile  uint8_t *)(0x42E00308UL))
#define bFM_CANFD0_CCCR_CSA                       *((volatile  uint8_t *)(0x42E0030CUL))
#define bFM4_CANFD0_CCCR_CSA                      *((volatile  uint8_t *)(0x42E0030CUL))
#define bFM_CANFD0_CCCR_CSR                       *((volatile  uint8_t *)(0x42E00310UL))
#define bFM4_CANFD0_CCCR_CSR                      *((volatile  uint8_t *)(0x42E00310UL))
#define bFM_CANFD0_CCCR_MON                       *((volatile  uint8_t *)(0x42E00314UL))
#define bFM4_CANFD0_CCCR_MON                      *((volatile  uint8_t *)(0x42E00314UL))
#define bFM_CANFD0_CCCR_DAR                       *((volatile  uint8_t *)(0x42E00318UL))
#define bFM4_CANFD0_CCCR_DAR                      *((volatile  uint8_t *)(0x42E00318UL))
#define bFM_CANFD0_CCCR_TEST                      *((volatile  uint8_t *)(0x42E0031CUL))
#define bFM4_CANFD0_CCCR_TEST                     *((volatile  uint8_t *)(0x42E0031CUL))
#define bFM_CANFD0_CCCR_FDO                       *((volatile  uint8_t *)(0x42E00330UL))
#define bFM4_CANFD0_CCCR_FDO                      *((volatile  uint8_t *)(0x42E00330UL))
#define bFM_CANFD0_CCCR_FDBS                      *((volatile  uint8_t *)(0x42E00334UL))
#define bFM4_CANFD0_CCCR_FDBS                     *((volatile  uint8_t *)(0x42E00334UL))
#define bFM_CANFD0_CCCR_TXP                       *((volatile  uint8_t *)(0x42E00338UL))
#define bFM4_CANFD0_CCCR_TXP                      *((volatile  uint8_t *)(0x42E00338UL))

#define bFM_CANFD0_ECR_RP                         *((volatile  uint8_t *)(0x42E0083CUL))
#define bFM4_CANFD0_ECR_RP                        *((volatile  uint8_t *)(0x42E0083CUL))

#define bFM_CANFD0_FBTP_TDC                       *((volatile  uint8_t *)(0x42E001DCUL))
#define bFM4_CANFD0_FBTP_TDC                      *((volatile  uint8_t *)(0x42E001DCUL))

#define bFM_CANFD0_FDECR_SEIE                     *((volatile  uint8_t *)(0x42E04000UL))
#define bFM4_CANFD0_FDECR_SEIE                    *((volatile  uint8_t *)(0x42E04000UL))
#define bFM_CANFD0_FDECR_DEIE                     *((volatile  uint8_t *)(0x42E04004UL))
#define bFM4_CANFD0_FDECR_DEIE                    *((volatile  uint8_t *)(0x42E04004UL))
#define bFM_CANFD0_FDECR_CEREN                    *((volatile  uint8_t *)(0x42E04008UL))
#define bFM4_CANFD0_FDECR_CEREN                   *((volatile  uint8_t *)(0x42E04008UL))
#define bFM_CANFD0_FDECR_CEIV                     *((volatile  uint8_t *)(0x42E0400CUL))
#define bFM4_CANFD0_FDECR_CEIV                    *((volatile  uint8_t *)(0x42E0400CUL))

#define bFM_CANFD0_FDESCR_SEIC                    *((volatile  uint8_t *)(0x42E040A0UL))
#define bFM4_CANFD0_FDESCR_SEIC                   *((volatile  uint8_t *)(0x42E040A0UL))
#define bFM_CANFD0_FDESCR_DEIC                    *((volatile  uint8_t *)(0x42E040A4UL))
#define bFM4_CANFD0_FDESCR_DEIC                   *((volatile  uint8_t *)(0x42E040A4UL))

#define bFM_CANFD0_FDESR_SEI                      *((volatile  uint8_t *)(0x42E04020UL))
#define bFM4_CANFD0_FDESR_SEI                     *((volatile  uint8_t *)(0x42E04020UL))
#define bFM_CANFD0_FDESR_DEI                      *((volatile  uint8_t *)(0x42E04024UL))
#define bFM4_CANFD0_FDESR_DEI                     *((volatile  uint8_t *)(0x42E04024UL))

#define bFM_CANFD0_GFC_RRFE                       *((volatile  uint8_t *)(0x42E01000UL))
#define bFM4_CANFD0_GFC_RRFE                      *((volatile  uint8_t *)(0x42E01000UL))
#define bFM_CANFD0_GFC_RRFS                       *((volatile  uint8_t *)(0x42E01004UL))
#define bFM4_CANFD0_GFC_RRFS                      *((volatile  uint8_t *)(0x42E01004UL))

#define bFM_CANFD0_HPMS_FLST                      *((volatile  uint8_t *)(0x42E012BCUL))
#define bFM4_CANFD0_HPMS_FLST                     *((volatile  uint8_t *)(0x42E012BCUL))

#define bFM_CANFD0_IE_RF0NE                       *((volatile  uint8_t *)(0x42E00A80UL))
#define bFM4_CANFD0_IE_RF0NE                      *((volatile  uint8_t *)(0x42E00A80UL))
#define bFM_CANFD0_IE_RF0WE                       *((volatile  uint8_t *)(0x42E00A84UL))
#define bFM4_CANFD0_IE_RF0WE                      *((volatile  uint8_t *)(0x42E00A84UL))
#define bFM_CANFD0_IE_RF0FE                       *((volatile  uint8_t *)(0x42E00A88UL))
#define bFM4_CANFD0_IE_RF0FE                      *((volatile  uint8_t *)(0x42E00A88UL))
#define bFM_CANFD0_IE_RF0LE                       *((volatile  uint8_t *)(0x42E00A8CUL))
#define bFM4_CANFD0_IE_RF0LE                      *((volatile  uint8_t *)(0x42E00A8CUL))
#define bFM_CANFD0_IE_RF1NE                       *((volatile  uint8_t *)(0x42E00A90UL))
#define bFM4_CANFD0_IE_RF1NE                      *((volatile  uint8_t *)(0x42E00A90UL))
#define bFM_CANFD0_IE_RF1WE                       *((volatile  uint8_t *)(0x42E00A94UL))
#define bFM4_CANFD0_IE_RF1WE                      *((volatile  uint8_t *)(0x42E00A94UL))
#define bFM_CANFD0_IE_RF1FE                       *((volatile  uint8_t *)(0x42E00A98UL))
#define bFM4_CANFD0_IE_RF1FE                      *((volatile  uint8_t *)(0x42E00A98UL))
#define bFM_CANFD0_IE_RF1LE                       *((volatile  uint8_t *)(0x42E00A9CUL))
#define bFM4_CANFD0_IE_RF1LE                      *((volatile  uint8_t *)(0x42E00A9CUL))
#define bFM_CANFD0_IE_HPME                        *((volatile  uint8_t *)(0x42E00AA0UL))
#define bFM4_CANFD0_IE_HPME                       *((volatile  uint8_t *)(0x42E00AA0UL))
#define bFM_CANFD0_IE_TCE                         *((volatile  uint8_t *)(0x42E00AA4UL))
#define bFM4_CANFD0_IE_TCE                        *((volatile  uint8_t *)(0x42E00AA4UL))
#define bFM_CANFD0_IE_TCFE                        *((volatile  uint8_t *)(0x42E00AA8UL))
#define bFM4_CANFD0_IE_TCFE                       *((volatile  uint8_t *)(0x42E00AA8UL))
#define bFM_CANFD0_IE_TFEE                        *((volatile  uint8_t *)(0x42E00AACUL))
#define bFM4_CANFD0_IE_TFEE                       *((volatile  uint8_t *)(0x42E00AACUL))
#define bFM_CANFD0_IE_TEFNE                       *((volatile  uint8_t *)(0x42E00AB0UL))
#define bFM4_CANFD0_IE_TEFNE                      *((volatile  uint8_t *)(0x42E00AB0UL))
#define bFM_CANFD0_IE_TEFWE                       *((volatile  uint8_t *)(0x42E00AB4UL))
#define bFM4_CANFD0_IE_TEFWE                      *((volatile  uint8_t *)(0x42E00AB4UL))
#define bFM_CANFD0_IE_TEFFE                       *((volatile  uint8_t *)(0x42E00AB8UL))
#define bFM4_CANFD0_IE_TEFFE                      *((volatile  uint8_t *)(0x42E00AB8UL))
#define bFM_CANFD0_IE_TEFLE                       *((volatile  uint8_t *)(0x42E00ABCUL))
#define bFM4_CANFD0_IE_TEFLE                      *((volatile  uint8_t *)(0x42E00ABCUL))
#define bFM_CANFD0_IE_TSWE                        *((volatile  uint8_t *)(0x42E00AC0UL))
#define bFM4_CANFD0_IE_TSWE                       *((volatile  uint8_t *)(0x42E00AC0UL))
#define bFM_CANFD0_IE_MRAFE                       *((volatile  uint8_t *)(0x42E00AC4UL))
#define bFM4_CANFD0_IE_MRAFE                      *((volatile  uint8_t *)(0x42E00AC4UL))
#define bFM_CANFD0_IE_TOOE                        *((volatile  uint8_t *)(0x42E00AC8UL))
#define bFM4_CANFD0_IE_TOOE                       *((volatile  uint8_t *)(0x42E00AC8UL))
#define bFM_CANFD0_IE_DRXE                        *((volatile  uint8_t *)(0x42E00ACCUL))
#define bFM4_CANFD0_IE_DRXE                       *((volatile  uint8_t *)(0x42E00ACCUL))
#define bFM_CANFD0_IE_BECE                        *((volatile  uint8_t *)(0x42E00AD0UL))
#define bFM4_CANFD0_IE_BECE                       *((volatile  uint8_t *)(0x42E00AD0UL))
#define bFM_CANFD0_IE_BEUE                        *((volatile  uint8_t *)(0x42E00AD4UL))
#define bFM4_CANFD0_IE_BEUE                       *((volatile  uint8_t *)(0x42E00AD4UL))
#define bFM_CANFD0_IE_ELOE                        *((volatile  uint8_t *)(0x42E00AD8UL))
#define bFM4_CANFD0_IE_ELOE                       *((volatile  uint8_t *)(0x42E00AD8UL))
#define bFM_CANFD0_IE_EPE                         *((volatile  uint8_t *)(0x42E00ADCUL))
#define bFM4_CANFD0_IE_EPE                        *((volatile  uint8_t *)(0x42E00ADCUL))
#define bFM_CANFD0_IE_EWE                         *((volatile  uint8_t *)(0x42E00AE0UL))
#define bFM4_CANFD0_IE_EWE                        *((volatile  uint8_t *)(0x42E00AE0UL))
#define bFM_CANFD0_IE_BOE                         *((volatile  uint8_t *)(0x42E00AE4UL))
#define bFM4_CANFD0_IE_BOE                        *((volatile  uint8_t *)(0x42E00AE4UL))
#define bFM_CANFD0_IE_WDIE                        *((volatile  uint8_t *)(0x42E00AE8UL))
#define bFM4_CANFD0_IE_WDIE                       *((volatile  uint8_t *)(0x42E00AE8UL))
#define bFM_CANFD0_IE_CRCEE                       *((volatile  uint8_t *)(0x42E00AECUL))
#define bFM4_CANFD0_IE_CRCEE                      *((volatile  uint8_t *)(0x42E00AECUL))
#define bFM_CANFD0_IE_BEE                         *((volatile  uint8_t *)(0x42E00AF0UL))
#define bFM4_CANFD0_IE_BEE                        *((volatile  uint8_t *)(0x42E00AF0UL))
#define bFM_CANFD0_IE_ACKEE                       *((volatile  uint8_t *)(0x42E00AF4UL))
#define bFM4_CANFD0_IE_ACKEE                      *((volatile  uint8_t *)(0x42E00AF4UL))
#define bFM_CANFD0_IE_FOEE                        *((volatile  uint8_t *)(0x42E00AF8UL))
#define bFM4_CANFD0_IE_FOEE                       *((volatile  uint8_t *)(0x42E00AF8UL))
#define bFM_CANFD0_IE_STEE                        *((volatile  uint8_t *)(0x42E00AFCUL))
#define bFM4_CANFD0_IE_STEE                       *((volatile  uint8_t *)(0x42E00AFCUL))

#define bFM_CANFD0_ILE_EINT0                      *((volatile  uint8_t *)(0x42E00B80UL))
#define bFM4_CANFD0_ILE_EINT0                     *((volatile  uint8_t *)(0x42E00B80UL))
#define bFM_CANFD0_ILE_EINT1                      *((volatile  uint8_t *)(0x42E00B84UL))
#define bFM4_CANFD0_ILE_EINT1                     *((volatile  uint8_t *)(0x42E00B84UL))

#define bFM_CANFD0_ILS_RF0NL                      *((volatile  uint8_t *)(0x42E00B00UL))
#define bFM4_CANFD0_ILS_RF0NL                     *((volatile  uint8_t *)(0x42E00B00UL))
#define bFM_CANFD0_ILS_RF0WL                      *((volatile  uint8_t *)(0x42E00B04UL))
#define bFM4_CANFD0_ILS_RF0WL                     *((volatile  uint8_t *)(0x42E00B04UL))
#define bFM_CANFD0_ILS_RF0FL                      *((volatile  uint8_t *)(0x42E00B08UL))
#define bFM4_CANFD0_ILS_RF0FL                     *((volatile  uint8_t *)(0x42E00B08UL))
#define bFM_CANFD0_ILS_RF0LL                      *((volatile  uint8_t *)(0x42E00B0CUL))
#define bFM4_CANFD0_ILS_RF0LL                     *((volatile  uint8_t *)(0x42E00B0CUL))
#define bFM_CANFD0_ILS_RF1NL                      *((volatile  uint8_t *)(0x42E00B10UL))
#define bFM4_CANFD0_ILS_RF1NL                     *((volatile  uint8_t *)(0x42E00B10UL))
#define bFM_CANFD0_ILS_RF1WL                      *((volatile  uint8_t *)(0x42E00B14UL))
#define bFM4_CANFD0_ILS_RF1WL                     *((volatile  uint8_t *)(0x42E00B14UL))
#define bFM_CANFD0_ILS_RF1FL                      *((volatile  uint8_t *)(0x42E00B18UL))
#define bFM4_CANFD0_ILS_RF1FL                     *((volatile  uint8_t *)(0x42E00B18UL))
#define bFM_CANFD0_ILS_RF1LL                      *((volatile  uint8_t *)(0x42E00B1CUL))
#define bFM4_CANFD0_ILS_RF1LL                     *((volatile  uint8_t *)(0x42E00B1CUL))
#define bFM_CANFD0_ILS_HPML                       *((volatile  uint8_t *)(0x42E00B20UL))
#define bFM4_CANFD0_ILS_HPML                      *((volatile  uint8_t *)(0x42E00B20UL))
#define bFM_CANFD0_ILS_TCL                        *((volatile  uint8_t *)(0x42E00B24UL))
#define bFM4_CANFD0_ILS_TCL                       *((volatile  uint8_t *)(0x42E00B24UL))
#define bFM_CANFD0_ILS_TCFL                       *((volatile  uint8_t *)(0x42E00B28UL))
#define bFM4_CANFD0_ILS_TCFL                      *((volatile  uint8_t *)(0x42E00B28UL))
#define bFM_CANFD0_ILS_TFEL                       *((volatile  uint8_t *)(0x42E00B2CUL))
#define bFM4_CANFD0_ILS_TFEL                      *((volatile  uint8_t *)(0x42E00B2CUL))
#define bFM_CANFD0_ILS_TEFNL                      *((volatile  uint8_t *)(0x42E00B30UL))
#define bFM4_CANFD0_ILS_TEFNL                     *((volatile  uint8_t *)(0x42E00B30UL))
#define bFM_CANFD0_ILS_TEFWL                      *((volatile  uint8_t *)(0x42E00B34UL))
#define bFM4_CANFD0_ILS_TEFWL                     *((volatile  uint8_t *)(0x42E00B34UL))
#define bFM_CANFD0_ILS_TEFFL                      *((volatile  uint8_t *)(0x42E00B38UL))
#define bFM4_CANFD0_ILS_TEFFL                     *((volatile  uint8_t *)(0x42E00B38UL))
#define bFM_CANFD0_ILS_TEFLL                      *((volatile  uint8_t *)(0x42E00B3CUL))
#define bFM4_CANFD0_ILS_TEFLL                     *((volatile  uint8_t *)(0x42E00B3CUL))
#define bFM_CANFD0_ILS_TSWL                       *((volatile  uint8_t *)(0x42E00B40UL))
#define bFM4_CANFD0_ILS_TSWL                      *((volatile  uint8_t *)(0x42E00B40UL))
#define bFM_CANFD0_ILS_MRAFL                      *((volatile  uint8_t *)(0x42E00B44UL))
#define bFM4_CANFD0_ILS_MRAFL                     *((volatile  uint8_t *)(0x42E00B44UL))
#define bFM_CANFD0_ILS_TOOL                       *((volatile  uint8_t *)(0x42E00B48UL))
#define bFM4_CANFD0_ILS_TOOL                      *((volatile  uint8_t *)(0x42E00B48UL))
#define bFM_CANFD0_ILS_DRXL                       *((volatile  uint8_t *)(0x42E00B4CUL))
#define bFM4_CANFD0_ILS_DRXL                      *((volatile  uint8_t *)(0x42E00B4CUL))
#define bFM_CANFD0_ILS_BECL                       *((volatile  uint8_t *)(0x42E00B50UL))
#define bFM4_CANFD0_ILS_BECL                      *((volatile  uint8_t *)(0x42E00B50UL))
#define bFM_CANFD0_ILS_BEUL                       *((volatile  uint8_t *)(0x42E00B54UL))
#define bFM4_CANFD0_ILS_BEUL                      *((volatile  uint8_t *)(0x42E00B54UL))
#define bFM_CANFD0_ILS_ELOL                       *((volatile  uint8_t *)(0x42E00B58UL))
#define bFM4_CANFD0_ILS_ELOL                      *((volatile  uint8_t *)(0x42E00B58UL))
#define bFM_CANFD0_ILS_EPL                        *((volatile  uint8_t *)(0x42E00B5CUL))
#define bFM4_CANFD0_ILS_EPL                       *((volatile  uint8_t *)(0x42E00B5CUL))
#define bFM_CANFD0_ILS_EWL                        *((volatile  uint8_t *)(0x42E00B60UL))
#define bFM4_CANFD0_ILS_EWL                       *((volatile  uint8_t *)(0x42E00B60UL))
#define bFM_CANFD0_ILS_BOL                        *((volatile  uint8_t *)(0x42E00B64UL))
#define bFM4_CANFD0_ILS_BOL                       *((volatile  uint8_t *)(0x42E00B64UL))
#define bFM_CANFD0_ILS_WDIL                       *((volatile  uint8_t *)(0x42E00B68UL))
#define bFM4_CANFD0_ILS_WDIL                      *((volatile  uint8_t *)(0x42E00B68UL))
#define bFM_CANFD0_ILS_CRCEL                      *((volatile  uint8_t *)(0x42E00B6CUL))
#define bFM4_CANFD0_ILS_CRCEL                     *((volatile  uint8_t *)(0x42E00B6CUL))
#define bFM_CANFD0_ILS_BEL                        *((volatile  uint8_t *)(0x42E00B70UL))
#define bFM4_CANFD0_ILS_BEL                       *((volatile  uint8_t *)(0x42E00B70UL))
#define bFM_CANFD0_ILS_ACKEL                      *((volatile  uint8_t *)(0x42E00B74UL))
#define bFM4_CANFD0_ILS_ACKEL                     *((volatile  uint8_t *)(0x42E00B74UL))
#define bFM_CANFD0_ILS_FOEL                       *((volatile  uint8_t *)(0x42E00B78UL))
#define bFM4_CANFD0_ILS_FOEL                      *((volatile  uint8_t *)(0x42E00B78UL))
#define bFM_CANFD0_ILS_STEL                       *((volatile  uint8_t *)(0x42E00B7CUL))
#define bFM4_CANFD0_ILS_STEL                      *((volatile  uint8_t *)(0x42E00B7CUL))

#define bFM_CANFD0_IR_RF0N                        *((volatile  uint8_t *)(0x42E00A00UL))
#define bFM4_CANFD0_IR_RF0N                       *((volatile  uint8_t *)(0x42E00A00UL))
#define bFM_CANFD0_IR_RF0W                        *((volatile  uint8_t *)(0x42E00A04UL))
#define bFM4_CANFD0_IR_RF0W                       *((volatile  uint8_t *)(0x42E00A04UL))
#define bFM_CANFD0_IR_RF0F                        *((volatile  uint8_t *)(0x42E00A08UL))
#define bFM4_CANFD0_IR_RF0F                       *((volatile  uint8_t *)(0x42E00A08UL))
#define bFM_CANFD0_IR_RF0L                        *((volatile  uint8_t *)(0x42E00A0CUL))
#define bFM4_CANFD0_IR_RF0L                       *((volatile  uint8_t *)(0x42E00A0CUL))
#define bFM_CANFD0_IR_RF1N                        *((volatile  uint8_t *)(0x42E00A10UL))
#define bFM4_CANFD0_IR_RF1N                       *((volatile  uint8_t *)(0x42E00A10UL))
#define bFM_CANFD0_IR_RF1W                        *((volatile  uint8_t *)(0x42E00A14UL))
#define bFM4_CANFD0_IR_RF1W                       *((volatile  uint8_t *)(0x42E00A14UL))
#define bFM_CANFD0_IR_RF1F                        *((volatile  uint8_t *)(0x42E00A18UL))
#define bFM4_CANFD0_IR_RF1F                       *((volatile  uint8_t *)(0x42E00A18UL))
#define bFM_CANFD0_IR_RF1L                        *((volatile  uint8_t *)(0x42E00A1CUL))
#define bFM4_CANFD0_IR_RF1L                       *((volatile  uint8_t *)(0x42E00A1CUL))
#define bFM_CANFD0_IR_HPM                         *((volatile  uint8_t *)(0x42E00A20UL))
#define bFM4_CANFD0_IR_HPM                        *((volatile  uint8_t *)(0x42E00A20UL))
#define bFM_CANFD0_IR_TC                          *((volatile  uint8_t *)(0x42E00A24UL))
#define bFM4_CANFD0_IR_TC                         *((volatile  uint8_t *)(0x42E00A24UL))
#define bFM_CANFD0_IR_TCF                         *((volatile  uint8_t *)(0x42E00A28UL))
#define bFM4_CANFD0_IR_TCF                        *((volatile  uint8_t *)(0x42E00A28UL))
#define bFM_CANFD0_IR_TFE                         *((volatile  uint8_t *)(0x42E00A2CUL))
#define bFM4_CANFD0_IR_TFE                        *((volatile  uint8_t *)(0x42E00A2CUL))
#define bFM_CANFD0_IR_TEFN                        *((volatile  uint8_t *)(0x42E00A30UL))
#define bFM4_CANFD0_IR_TEFN                       *((volatile  uint8_t *)(0x42E00A30UL))
#define bFM_CANFD0_IR_TEFW                        *((volatile  uint8_t *)(0x42E00A34UL))
#define bFM4_CANFD0_IR_TEFW                       *((volatile  uint8_t *)(0x42E00A34UL))
#define bFM_CANFD0_IR_TEFF                        *((volatile  uint8_t *)(0x42E00A38UL))
#define bFM4_CANFD0_IR_TEFF                       *((volatile  uint8_t *)(0x42E00A38UL))
#define bFM_CANFD0_IR_TEFL                        *((volatile  uint8_t *)(0x42E00A3CUL))
#define bFM4_CANFD0_IR_TEFL                       *((volatile  uint8_t *)(0x42E00A3CUL))
#define bFM_CANFD0_IR_TSW                         *((volatile  uint8_t *)(0x42E00A40UL))
#define bFM4_CANFD0_IR_TSW                        *((volatile  uint8_t *)(0x42E00A40UL))
#define bFM_CANFD0_IR_MRAF                        *((volatile  uint8_t *)(0x42E00A44UL))
#define bFM4_CANFD0_IR_MRAF                       *((volatile  uint8_t *)(0x42E00A44UL))
#define bFM_CANFD0_IR_TOO                         *((volatile  uint8_t *)(0x42E00A48UL))
#define bFM4_CANFD0_IR_TOO                        *((volatile  uint8_t *)(0x42E00A48UL))
#define bFM_CANFD0_IR_DRX                         *((volatile  uint8_t *)(0x42E00A4CUL))
#define bFM4_CANFD0_IR_DRX                        *((volatile  uint8_t *)(0x42E00A4CUL))
#define bFM_CANFD0_IR_BEC                         *((volatile  uint8_t *)(0x42E00A50UL))
#define bFM4_CANFD0_IR_BEC                        *((volatile  uint8_t *)(0x42E00A50UL))
#define bFM_CANFD0_IR_BEU                         *((volatile  uint8_t *)(0x42E00A54UL))
#define bFM4_CANFD0_IR_BEU                        *((volatile  uint8_t *)(0x42E00A54UL))
#define bFM_CANFD0_IR_ELO                         *((volatile  uint8_t *)(0x42E00A58UL))
#define bFM4_CANFD0_IR_ELO                        *((volatile  uint8_t *)(0x42E00A58UL))
#define bFM_CANFD0_IR_EP                          *((volatile  uint8_t *)(0x42E00A5CUL))
#define bFM4_CANFD0_IR_EP                         *((volatile  uint8_t *)(0x42E00A5CUL))
#define bFM_CANFD0_IR_EW                          *((volatile  uint8_t *)(0x42E00A60UL))
#define bFM4_CANFD0_IR_EW                         *((volatile  uint8_t *)(0x42E00A60UL))
#define bFM_CANFD0_IR_BO                          *((volatile  uint8_t *)(0x42E00A64UL))
#define bFM4_CANFD0_IR_BO                         *((volatile  uint8_t *)(0x42E00A64UL))
#define bFM_CANFD0_IR_WDI                         *((volatile  uint8_t *)(0x42E00A68UL))
#define bFM4_CANFD0_IR_WDI                        *((volatile  uint8_t *)(0x42E00A68UL))
#define bFM_CANFD0_IR_CRCE                        *((volatile  uint8_t *)(0x42E00A6CUL))
#define bFM4_CANFD0_IR_CRCE                       *((volatile  uint8_t *)(0x42E00A6CUL))
#define bFM_CANFD0_IR_BE                          *((volatile  uint8_t *)(0x42E00A70UL))
#define bFM4_CANFD0_IR_BE                         *((volatile  uint8_t *)(0x42E00A70UL))
#define bFM_CANFD0_IR_ACKE                        *((volatile  uint8_t *)(0x42E00A74UL))
#define bFM4_CANFD0_IR_ACKE                       *((volatile  uint8_t *)(0x42E00A74UL))
#define bFM_CANFD0_IR_FOE                         *((volatile  uint8_t *)(0x42E00A78UL))
#define bFM4_CANFD0_IR_FOE                        *((volatile  uint8_t *)(0x42E00A78UL))
#define bFM_CANFD0_IR_STE                         *((volatile  uint8_t *)(0x42E00A7CUL))
#define bFM4_CANFD0_IR_STE                        *((volatile  uint8_t *)(0x42E00A7CUL))

#define bFM_CANFD0_NDAT1_ND0                      *((volatile  uint8_t *)(0x42E01300UL))
#define bFM4_CANFD0_NDAT1_ND0                     *((volatile  uint8_t *)(0x42E01300UL))
#define bFM_CANFD0_NDAT1_ND1                      *((volatile  uint8_t *)(0x42E01304UL))
#define bFM4_CANFD0_NDAT1_ND1                     *((volatile  uint8_t *)(0x42E01304UL))
#define bFM_CANFD0_NDAT1_ND2                      *((volatile  uint8_t *)(0x42E01308UL))
#define bFM4_CANFD0_NDAT1_ND2                     *((volatile  uint8_t *)(0x42E01308UL))
#define bFM_CANFD0_NDAT1_ND3                      *((volatile  uint8_t *)(0x42E0130CUL))
#define bFM4_CANFD0_NDAT1_ND3                     *((volatile  uint8_t *)(0x42E0130CUL))
#define bFM_CANFD0_NDAT1_ND4                      *((volatile  uint8_t *)(0x42E01310UL))
#define bFM4_CANFD0_NDAT1_ND4                     *((volatile  uint8_t *)(0x42E01310UL))
#define bFM_CANFD0_NDAT1_ND5                      *((volatile  uint8_t *)(0x42E01314UL))
#define bFM4_CANFD0_NDAT1_ND5                     *((volatile  uint8_t *)(0x42E01314UL))
#define bFM_CANFD0_NDAT1_ND6                      *((volatile  uint8_t *)(0x42E01318UL))
#define bFM4_CANFD0_NDAT1_ND6                     *((volatile  uint8_t *)(0x42E01318UL))
#define bFM_CANFD0_NDAT1_ND7                      *((volatile  uint8_t *)(0x42E0131CUL))
#define bFM4_CANFD0_NDAT1_ND7                     *((volatile  uint8_t *)(0x42E0131CUL))
#define bFM_CANFD0_NDAT1_ND8                      *((volatile  uint8_t *)(0x42E01320UL))
#define bFM4_CANFD0_NDAT1_ND8                     *((volatile  uint8_t *)(0x42E01320UL))
#define bFM_CANFD0_NDAT1_ND9                      *((volatile  uint8_t *)(0x42E01324UL))
#define bFM4_CANFD0_NDAT1_ND9                     *((volatile  uint8_t *)(0x42E01324UL))
#define bFM_CANFD0_NDAT1_ND10                     *((volatile  uint8_t *)(0x42E01328UL))
#define bFM4_CANFD0_NDAT1_ND10                    *((volatile  uint8_t *)(0x42E01328UL))
#define bFM_CANFD0_NDAT1_ND11                     *((volatile  uint8_t *)(0x42E0132CUL))
#define bFM4_CANFD0_NDAT1_ND11                    *((volatile  uint8_t *)(0x42E0132CUL))
#define bFM_CANFD0_NDAT1_ND12                     *((volatile  uint8_t *)(0x42E01330UL))
#define bFM4_CANFD0_NDAT1_ND12                    *((volatile  uint8_t *)(0x42E01330UL))
#define bFM_CANFD0_NDAT1_ND13                     *((volatile  uint8_t *)(0x42E01334UL))
#define bFM4_CANFD0_NDAT1_ND13                    *((volatile  uint8_t *)(0x42E01334UL))
#define bFM_CANFD0_NDAT1_ND14                     *((volatile  uint8_t *)(0x42E01338UL))
#define bFM4_CANFD0_NDAT1_ND14                    *((volatile  uint8_t *)(0x42E01338UL))
#define bFM_CANFD0_NDAT1_ND15                     *((volatile  uint8_t *)(0x42E0133CUL))
#define bFM4_CANFD0_NDAT1_ND15                    *((volatile  uint8_t *)(0x42E0133CUL))
#define bFM_CANFD0_NDAT1_ND16                     *((volatile  uint8_t *)(0x42E01340UL))
#define bFM4_CANFD0_NDAT1_ND16                    *((volatile  uint8_t *)(0x42E01340UL))
#define bFM_CANFD0_NDAT1_ND17                     *((volatile  uint8_t *)(0x42E01344UL))
#define bFM4_CANFD0_NDAT1_ND17                    *((volatile  uint8_t *)(0x42E01344UL))
#define bFM_CANFD0_NDAT1_ND18                     *((volatile  uint8_t *)(0x42E01348UL))
#define bFM4_CANFD0_NDAT1_ND18                    *((volatile  uint8_t *)(0x42E01348UL))
#define bFM_CANFD0_NDAT1_ND19                     *((volatile  uint8_t *)(0x42E0134CUL))
#define bFM4_CANFD0_NDAT1_ND19                    *((volatile  uint8_t *)(0x42E0134CUL))
#define bFM_CANFD0_NDAT1_ND20                     *((volatile  uint8_t *)(0x42E01350UL))
#define bFM4_CANFD0_NDAT1_ND20                    *((volatile  uint8_t *)(0x42E01350UL))
#define bFM_CANFD0_NDAT1_ND21                     *((volatile  uint8_t *)(0x42E01354UL))
#define bFM4_CANFD0_NDAT1_ND21                    *((volatile  uint8_t *)(0x42E01354UL))
#define bFM_CANFD0_NDAT1_ND22                     *((volatile  uint8_t *)(0x42E01358UL))
#define bFM4_CANFD0_NDAT1_ND22                    *((volatile  uint8_t *)(0x42E01358UL))
#define bFM_CANFD0_NDAT1_ND23                     *((volatile  uint8_t *)(0x42E0135CUL))
#define bFM4_CANFD0_NDAT1_ND23                    *((volatile  uint8_t *)(0x42E0135CUL))
#define bFM_CANFD0_NDAT1_ND24                     *((volatile  uint8_t *)(0x42E01360UL))
#define bFM4_CANFD0_NDAT1_ND24                    *((volatile  uint8_t *)(0x42E01360UL))
#define bFM_CANFD0_NDAT1_ND25                     *((volatile  uint8_t *)(0x42E01364UL))
#define bFM4_CANFD0_NDAT1_ND25                    *((volatile  uint8_t *)(0x42E01364UL))
#define bFM_CANFD0_NDAT1_ND26                     *((volatile  uint8_t *)(0x42E01368UL))
#define bFM4_CANFD0_NDAT1_ND26                    *((volatile  uint8_t *)(0x42E01368UL))
#define bFM_CANFD0_NDAT1_ND27                     *((volatile  uint8_t *)(0x42E0136CUL))
#define bFM4_CANFD0_NDAT1_ND27                    *((volatile  uint8_t *)(0x42E0136CUL))
#define bFM_CANFD0_NDAT1_ND28                     *((volatile  uint8_t *)(0x42E01370UL))
#define bFM4_CANFD0_NDAT1_ND28                    *((volatile  uint8_t *)(0x42E01370UL))
#define bFM_CANFD0_NDAT1_ND29                     *((volatile  uint8_t *)(0x42E01374UL))
#define bFM4_CANFD0_NDAT1_ND29                    *((volatile  uint8_t *)(0x42E01374UL))
#define bFM_CANFD0_NDAT1_ND30                     *((volatile  uint8_t *)(0x42E01378UL))
#define bFM4_CANFD0_NDAT1_ND30                    *((volatile  uint8_t *)(0x42E01378UL))
#define bFM_CANFD0_NDAT1_ND31                     *((volatile  uint8_t *)(0x42E0137CUL))
#define bFM4_CANFD0_NDAT1_ND31                    *((volatile  uint8_t *)(0x42E0137CUL))

#define bFM_CANFD0_NDAT2_ND32                     *((volatile  uint8_t *)(0x42E01380UL))
#define bFM4_CANFD0_NDAT2_ND32                    *((volatile  uint8_t *)(0x42E01380UL))
#define bFM_CANFD0_NDAT2_ND33                     *((volatile  uint8_t *)(0x42E01384UL))
#define bFM4_CANFD0_NDAT2_ND33                    *((volatile  uint8_t *)(0x42E01384UL))
#define bFM_CANFD0_NDAT2_ND34                     *((volatile  uint8_t *)(0x42E01388UL))
#define bFM4_CANFD0_NDAT2_ND34                    *((volatile  uint8_t *)(0x42E01388UL))
#define bFM_CANFD0_NDAT2_ND35                     *((volatile  uint8_t *)(0x42E0138CUL))
#define bFM4_CANFD0_NDAT2_ND35                    *((volatile  uint8_t *)(0x42E0138CUL))
#define bFM_CANFD0_NDAT2_ND36                     *((volatile  uint8_t *)(0x42E01390UL))
#define bFM4_CANFD0_NDAT2_ND36                    *((volatile  uint8_t *)(0x42E01390UL))
#define bFM_CANFD0_NDAT2_ND37                     *((volatile  uint8_t *)(0x42E01394UL))
#define bFM4_CANFD0_NDAT2_ND37                    *((volatile  uint8_t *)(0x42E01394UL))
#define bFM_CANFD0_NDAT2_ND38                     *((volatile  uint8_t *)(0x42E01398UL))
#define bFM4_CANFD0_NDAT2_ND38                    *((volatile  uint8_t *)(0x42E01398UL))
#define bFM_CANFD0_NDAT2_ND39                     *((volatile  uint8_t *)(0x42E0139CUL))
#define bFM4_CANFD0_NDAT2_ND39                    *((volatile  uint8_t *)(0x42E0139CUL))
#define bFM_CANFD0_NDAT2_ND40                     *((volatile  uint8_t *)(0x42E013A0UL))
#define bFM4_CANFD0_NDAT2_ND40                    *((volatile  uint8_t *)(0x42E013A0UL))
#define bFM_CANFD0_NDAT2_ND41                     *((volatile  uint8_t *)(0x42E013A4UL))
#define bFM4_CANFD0_NDAT2_ND41                    *((volatile  uint8_t *)(0x42E013A4UL))
#define bFM_CANFD0_NDAT2_ND42                     *((volatile  uint8_t *)(0x42E013A8UL))
#define bFM4_CANFD0_NDAT2_ND42                    *((volatile  uint8_t *)(0x42E013A8UL))
#define bFM_CANFD0_NDAT2_ND43                     *((volatile  uint8_t *)(0x42E013ACUL))
#define bFM4_CANFD0_NDAT2_ND43                    *((volatile  uint8_t *)(0x42E013ACUL))
#define bFM_CANFD0_NDAT2_ND44                     *((volatile  uint8_t *)(0x42E013B0UL))
#define bFM4_CANFD0_NDAT2_ND44                    *((volatile  uint8_t *)(0x42E013B0UL))
#define bFM_CANFD0_NDAT2_ND45                     *((volatile  uint8_t *)(0x42E013B4UL))
#define bFM4_CANFD0_NDAT2_ND45                    *((volatile  uint8_t *)(0x42E013B4UL))
#define bFM_CANFD0_NDAT2_ND46                     *((volatile  uint8_t *)(0x42E013B8UL))
#define bFM4_CANFD0_NDAT2_ND46                    *((volatile  uint8_t *)(0x42E013B8UL))
#define bFM_CANFD0_NDAT2_ND47                     *((volatile  uint8_t *)(0x42E013BCUL))
#define bFM4_CANFD0_NDAT2_ND47                    *((volatile  uint8_t *)(0x42E013BCUL))
#define bFM_CANFD0_NDAT2_ND48                     *((volatile  uint8_t *)(0x42E013C0UL))
#define bFM4_CANFD0_NDAT2_ND48                    *((volatile  uint8_t *)(0x42E013C0UL))
#define bFM_CANFD0_NDAT2_ND49                     *((volatile  uint8_t *)(0x42E013C4UL))
#define bFM4_CANFD0_NDAT2_ND49                    *((volatile  uint8_t *)(0x42E013C4UL))
#define bFM_CANFD0_NDAT2_ND50                     *((volatile  uint8_t *)(0x42E013C8UL))
#define bFM4_CANFD0_NDAT2_ND50                    *((volatile  uint8_t *)(0x42E013C8UL))
#define bFM_CANFD0_NDAT2_ND51                     *((volatile  uint8_t *)(0x42E013CCUL))
#define bFM4_CANFD0_NDAT2_ND51                    *((volatile  uint8_t *)(0x42E013CCUL))
#define bFM_CANFD0_NDAT2_ND52                     *((volatile  uint8_t *)(0x42E013D0UL))
#define bFM4_CANFD0_NDAT2_ND52                    *((volatile  uint8_t *)(0x42E013D0UL))
#define bFM_CANFD0_NDAT2_ND53                     *((volatile  uint8_t *)(0x42E013D4UL))
#define bFM4_CANFD0_NDAT2_ND53                    *((volatile  uint8_t *)(0x42E013D4UL))
#define bFM_CANFD0_NDAT2_ND54                     *((volatile  uint8_t *)(0x42E013D8UL))
#define bFM4_CANFD0_NDAT2_ND54                    *((volatile  uint8_t *)(0x42E013D8UL))
#define bFM_CANFD0_NDAT2_ND55                     *((volatile  uint8_t *)(0x42E013DCUL))
#define bFM4_CANFD0_NDAT2_ND55                    *((volatile  uint8_t *)(0x42E013DCUL))
#define bFM_CANFD0_NDAT2_ND56                     *((volatile  uint8_t *)(0x42E013E0UL))
#define bFM4_CANFD0_NDAT2_ND56                    *((volatile  uint8_t *)(0x42E013E0UL))
#define bFM_CANFD0_NDAT2_ND57                     *((volatile  uint8_t *)(0x42E013E4UL))
#define bFM4_CANFD0_NDAT2_ND57                    *((volatile  uint8_t *)(0x42E013E4UL))
#define bFM_CANFD0_NDAT2_ND58                     *((volatile  uint8_t *)(0x42E013E8UL))
#define bFM4_CANFD0_NDAT2_ND58                    *((volatile  uint8_t *)(0x42E013E8UL))
#define bFM_CANFD0_NDAT2_ND59                     *((volatile  uint8_t *)(0x42E013ECUL))
#define bFM4_CANFD0_NDAT2_ND59                    *((volatile  uint8_t *)(0x42E013ECUL))
#define bFM_CANFD0_NDAT2_ND60                     *((volatile  uint8_t *)(0x42E013F0UL))
#define bFM4_CANFD0_NDAT2_ND60                    *((volatile  uint8_t *)(0x42E013F0UL))
#define bFM_CANFD0_NDAT2_ND61                     *((volatile  uint8_t *)(0x42E013F4UL))
#define bFM4_CANFD0_NDAT2_ND61                    *((volatile  uint8_t *)(0x42E013F4UL))
#define bFM_CANFD0_NDAT2_ND62                     *((volatile  uint8_t *)(0x42E013F8UL))
#define bFM4_CANFD0_NDAT2_ND62                    *((volatile  uint8_t *)(0x42E013F8UL))
#define bFM_CANFD0_NDAT2_ND63                     *((volatile  uint8_t *)(0x42E013FCUL))
#define bFM4_CANFD0_NDAT2_ND63                    *((volatile  uint8_t *)(0x42E013FCUL))

#define bFM_CANFD0_PSR_EP                         *((volatile  uint8_t *)(0x42E00894UL))
#define bFM4_CANFD0_PSR_EP                        *((volatile  uint8_t *)(0x42E00894UL))
#define bFM_CANFD0_PSR_EW                         *((volatile  uint8_t *)(0x42E00898UL))
#define bFM4_CANFD0_PSR_EW                        *((volatile  uint8_t *)(0x42E00898UL))
#define bFM_CANFD0_PSR_BO                         *((volatile  uint8_t *)(0x42E0089CUL))
#define bFM4_CANFD0_PSR_BO                        *((volatile  uint8_t *)(0x42E0089CUL))
#define bFM_CANFD0_PSR_RESI                       *((volatile  uint8_t *)(0x42E008ACUL))
#define bFM4_CANFD0_PSR_RESI                      *((volatile  uint8_t *)(0x42E008ACUL))
#define bFM_CANFD0_PSR_RBRS                       *((volatile  uint8_t *)(0x42E008B0UL))
#define bFM4_CANFD0_PSR_RBRS                      *((volatile  uint8_t *)(0x42E008B0UL))
#define bFM_CANFD0_PSR_REDL                       *((volatile  uint8_t *)(0x42E008B4UL))
#define bFM4_CANFD0_PSR_REDL                      *((volatile  uint8_t *)(0x42E008B4UL))

#define bFM_CANFD0_RXF0C_F0OM                     *((volatile  uint8_t *)(0x42E0147CUL))
#define bFM4_CANFD0_RXF0C_F0OM                    *((volatile  uint8_t *)(0x42E0147CUL))

#define bFM_CANFD0_RXF0S_F0F                      *((volatile  uint8_t *)(0x42E014E0UL))
#define bFM4_CANFD0_RXF0S_F0F                     *((volatile  uint8_t *)(0x42E014E0UL))
#define bFM_CANFD0_RXF0S_RF0L                     *((volatile  uint8_t *)(0x42E014E4UL))
#define bFM4_CANFD0_RXF0S_RF0L                    *((volatile  uint8_t *)(0x42E014E4UL))

#define bFM_CANFD0_RXF1C_F1OM                     *((volatile  uint8_t *)(0x42E0167CUL))
#define bFM4_CANFD0_RXF1C_F1OM                    *((volatile  uint8_t *)(0x42E0167CUL))

#define bFM_CANFD0_RXF1S_F1F                      *((volatile  uint8_t *)(0x42E016E0UL))
#define bFM4_CANFD0_RXF1S_F1F                     *((volatile  uint8_t *)(0x42E016E0UL))
#define bFM_CANFD0_RXF1S_RF1L                     *((volatile  uint8_t *)(0x42E016E4UL))
#define bFM4_CANFD0_RXF1S_RF1L                    *((volatile  uint8_t *)(0x42E016E4UL))

#define bFM_CANFD0_TEST_LBCK                      *((volatile  uint8_t *)(0x42E00210UL))
#define bFM4_CANFD0_TEST_LBCK                     *((volatile  uint8_t *)(0x42E00210UL))
#define bFM_CANFD0_TEST_RX                        *((volatile  uint8_t *)(0x42E0021CUL))
#define bFM4_CANFD0_TEST_RX                       *((volatile  uint8_t *)(0x42E0021CUL))

#define bFM_CANFD0_TOCC_ETOC                      *((volatile  uint8_t *)(0x42E00500UL))
#define bFM4_CANFD0_TOCC_ETOC                     *((volatile  uint8_t *)(0x42E00500UL))

#define bFM_CANFD0_TSCNTR_CCLR                    *((volatile  uint8_t *)(0x42E04200UL))
#define bFM4_CANFD0_TSCNTR_CCLR                   *((volatile  uint8_t *)(0x42E04200UL))

#define bFM_CANFD0_TSMDR_CNTEN                    *((volatile  uint8_t *)(0x42E04240UL))
#define bFM4_CANFD0_TSMDR_CNTEN                   *((volatile  uint8_t *)(0x42E04240UL))

#define bFM_CANFD0_TXBAR_AR0                      *((volatile  uint8_t *)(0x42E01A00UL))
#define bFM4_CANFD0_TXBAR_AR0                     *((volatile  uint8_t *)(0x42E01A00UL))
#define bFM_CANFD0_TXBAR_AR1                      *((volatile  uint8_t *)(0x42E01A04UL))
#define bFM4_CANFD0_TXBAR_AR1                     *((volatile  uint8_t *)(0x42E01A04UL))
#define bFM_CANFD0_TXBAR_AR2                      *((volatile  uint8_t *)(0x42E01A08UL))
#define bFM4_CANFD0_TXBAR_AR2                     *((volatile  uint8_t *)(0x42E01A08UL))
#define bFM_CANFD0_TXBAR_AR3                      *((volatile  uint8_t *)(0x42E01A0CUL))
#define bFM4_CANFD0_TXBAR_AR3                     *((volatile  uint8_t *)(0x42E01A0CUL))
#define bFM_CANFD0_TXBAR_AR4                      *((volatile  uint8_t *)(0x42E01A10UL))
#define bFM4_CANFD0_TXBAR_AR4                     *((volatile  uint8_t *)(0x42E01A10UL))
#define bFM_CANFD0_TXBAR_AR5                      *((volatile  uint8_t *)(0x42E01A14UL))
#define bFM4_CANFD0_TXBAR_AR5                     *((volatile  uint8_t *)(0x42E01A14UL))
#define bFM_CANFD0_TXBAR_AR6                      *((volatile  uint8_t *)(0x42E01A18UL))
#define bFM4_CANFD0_TXBAR_AR6                     *((volatile  uint8_t *)(0x42E01A18UL))
#define bFM_CANFD0_TXBAR_AR7                      *((volatile  uint8_t *)(0x42E01A1CUL))
#define bFM4_CANFD0_TXBAR_AR7                     *((volatile  uint8_t *)(0x42E01A1CUL))
#define bFM_CANFD0_TXBAR_AR8                      *((volatile  uint8_t *)(0x42E01A20UL))
#define bFM4_CANFD0_TXBAR_AR8                     *((volatile  uint8_t *)(0x42E01A20UL))
#define bFM_CANFD0_TXBAR_AR9                      *((volatile  uint8_t *)(0x42E01A24UL))
#define bFM4_CANFD0_TXBAR_AR9                     *((volatile  uint8_t *)(0x42E01A24UL))
#define bFM_CANFD0_TXBAR_AR10                     *((volatile  uint8_t *)(0x42E01A28UL))
#define bFM4_CANFD0_TXBAR_AR10                    *((volatile  uint8_t *)(0x42E01A28UL))
#define bFM_CANFD0_TXBAR_AR11                     *((volatile  uint8_t *)(0x42E01A2CUL))
#define bFM4_CANFD0_TXBAR_AR11                    *((volatile  uint8_t *)(0x42E01A2CUL))
#define bFM_CANFD0_TXBAR_AR12                     *((volatile  uint8_t *)(0x42E01A30UL))
#define bFM4_CANFD0_TXBAR_AR12                    *((volatile  uint8_t *)(0x42E01A30UL))
#define bFM_CANFD0_TXBAR_AR13                     *((volatile  uint8_t *)(0x42E01A34UL))
#define bFM4_CANFD0_TXBAR_AR13                    *((volatile  uint8_t *)(0x42E01A34UL))
#define bFM_CANFD0_TXBAR_AR14                     *((volatile  uint8_t *)(0x42E01A38UL))
#define bFM4_CANFD0_TXBAR_AR14                    *((volatile  uint8_t *)(0x42E01A38UL))
#define bFM_CANFD0_TXBAR_AR15                     *((volatile  uint8_t *)(0x42E01A3CUL))
#define bFM4_CANFD0_TXBAR_AR15                    *((volatile  uint8_t *)(0x42E01A3CUL))
#define bFM_CANFD0_TXBAR_AR16                     *((volatile  uint8_t *)(0x42E01A40UL))
#define bFM4_CANFD0_TXBAR_AR16                    *((volatile  uint8_t *)(0x42E01A40UL))
#define bFM_CANFD0_TXBAR_AR17                     *((volatile  uint8_t *)(0x42E01A44UL))
#define bFM4_CANFD0_TXBAR_AR17                    *((volatile  uint8_t *)(0x42E01A44UL))
#define bFM_CANFD0_TXBAR_AR18                     *((volatile  uint8_t *)(0x42E01A48UL))
#define bFM4_CANFD0_TXBAR_AR18                    *((volatile  uint8_t *)(0x42E01A48UL))
#define bFM_CANFD0_TXBAR_AR19                     *((volatile  uint8_t *)(0x42E01A4CUL))
#define bFM4_CANFD0_TXBAR_AR19                    *((volatile  uint8_t *)(0x42E01A4CUL))
#define bFM_CANFD0_TXBAR_AR20                     *((volatile  uint8_t *)(0x42E01A50UL))
#define bFM4_CANFD0_TXBAR_AR20                    *((volatile  uint8_t *)(0x42E01A50UL))
#define bFM_CANFD0_TXBAR_AR21                     *((volatile  uint8_t *)(0x42E01A54UL))
#define bFM4_CANFD0_TXBAR_AR21                    *((volatile  uint8_t *)(0x42E01A54UL))
#define bFM_CANFD0_TXBAR_AR22                     *((volatile  uint8_t *)(0x42E01A58UL))
#define bFM4_CANFD0_TXBAR_AR22                    *((volatile  uint8_t *)(0x42E01A58UL))
#define bFM_CANFD0_TXBAR_AR23                     *((volatile  uint8_t *)(0x42E01A5CUL))
#define bFM4_CANFD0_TXBAR_AR23                    *((volatile  uint8_t *)(0x42E01A5CUL))
#define bFM_CANFD0_TXBAR_AR24                     *((volatile  uint8_t *)(0x42E01A60UL))
#define bFM4_CANFD0_TXBAR_AR24                    *((volatile  uint8_t *)(0x42E01A60UL))
#define bFM_CANFD0_TXBAR_AR25                     *((volatile  uint8_t *)(0x42E01A64UL))
#define bFM4_CANFD0_TXBAR_AR25                    *((volatile  uint8_t *)(0x42E01A64UL))
#define bFM_CANFD0_TXBAR_AR26                     *((volatile  uint8_t *)(0x42E01A68UL))
#define bFM4_CANFD0_TXBAR_AR26                    *((volatile  uint8_t *)(0x42E01A68UL))
#define bFM_CANFD0_TXBAR_AR27                     *((volatile  uint8_t *)(0x42E01A6CUL))
#define bFM4_CANFD0_TXBAR_AR27                    *((volatile  uint8_t *)(0x42E01A6CUL))
#define bFM_CANFD0_TXBAR_AR28                     *((volatile  uint8_t *)(0x42E01A70UL))
#define bFM4_CANFD0_TXBAR_AR28                    *((volatile  uint8_t *)(0x42E01A70UL))
#define bFM_CANFD0_TXBAR_AR29                     *((volatile  uint8_t *)(0x42E01A74UL))
#define bFM4_CANFD0_TXBAR_AR29                    *((volatile  uint8_t *)(0x42E01A74UL))
#define bFM_CANFD0_TXBAR_AR30                     *((volatile  uint8_t *)(0x42E01A78UL))
#define bFM4_CANFD0_TXBAR_AR30                    *((volatile  uint8_t *)(0x42E01A78UL))
#define bFM_CANFD0_TXBAR_AR31                     *((volatile  uint8_t *)(0x42E01A7CUL))
#define bFM4_CANFD0_TXBAR_AR31                    *((volatile  uint8_t *)(0x42E01A7CUL))

#define bFM_CANFD0_TXBC_TFQM                      *((volatile  uint8_t *)(0x42E01878UL))
#define bFM4_CANFD0_TXBC_TFQM                     *((volatile  uint8_t *)(0x42E01878UL))

#define bFM_CANFD0_TXBCF_CF0                      *((volatile  uint8_t *)(0x42E01B80UL))
#define bFM4_CANFD0_TXBCF_CF0                     *((volatile  uint8_t *)(0x42E01B80UL))
#define bFM_CANFD0_TXBCF_CF1                      *((volatile  uint8_t *)(0x42E01B84UL))
#define bFM4_CANFD0_TXBCF_CF1                     *((volatile  uint8_t *)(0x42E01B84UL))
#define bFM_CANFD0_TXBCF_CF2                      *((volatile  uint8_t *)(0x42E01B88UL))
#define bFM4_CANFD0_TXBCF_CF2                     *((volatile  uint8_t *)(0x42E01B88UL))
#define bFM_CANFD0_TXBCF_CF3                      *((volatile  uint8_t *)(0x42E01B8CUL))
#define bFM4_CANFD0_TXBCF_CF3                     *((volatile  uint8_t *)(0x42E01B8CUL))
#define bFM_CANFD0_TXBCF_CF4                      *((volatile  uint8_t *)(0x42E01B90UL))
#define bFM4_CANFD0_TXBCF_CF4                     *((volatile  uint8_t *)(0x42E01B90UL))
#define bFM_CANFD0_TXBCF_CF5                      *((volatile  uint8_t *)(0x42E01B94UL))
#define bFM4_CANFD0_TXBCF_CF5                     *((volatile  uint8_t *)(0x42E01B94UL))
#define bFM_CANFD0_TXBCF_CF6                      *((volatile  uint8_t *)(0x42E01B98UL))
#define bFM4_CANFD0_TXBCF_CF6                     *((volatile  uint8_t *)(0x42E01B98UL))
#define bFM_CANFD0_TXBCF_CF7                      *((volatile  uint8_t *)(0x42E01B9CUL))
#define bFM4_CANFD0_TXBCF_CF7                     *((volatile  uint8_t *)(0x42E01B9CUL))
#define bFM_CANFD0_TXBCF_CF8                      *((volatile  uint8_t *)(0x42E01BA0UL))
#define bFM4_CANFD0_TXBCF_CF8                     *((volatile  uint8_t *)(0x42E01BA0UL))
#define bFM_CANFD0_TXBCF_CF9                      *((volatile  uint8_t *)(0x42E01BA4UL))
#define bFM4_CANFD0_TXBCF_CF9                     *((volatile  uint8_t *)(0x42E01BA4UL))
#define bFM_CANFD0_TXBCF_CF10                     *((volatile  uint8_t *)(0x42E01BA8UL))
#define bFM4_CANFD0_TXBCF_CF10                    *((volatile  uint8_t *)(0x42E01BA8UL))
#define bFM_CANFD0_TXBCF_CF11                     *((volatile  uint8_t *)(0x42E01BACUL))
#define bFM4_CANFD0_TXBCF_CF11                    *((volatile  uint8_t *)(0x42E01BACUL))
#define bFM_CANFD0_TXBCF_CF12                     *((volatile  uint8_t *)(0x42E01BB0UL))
#define bFM4_CANFD0_TXBCF_CF12                    *((volatile  uint8_t *)(0x42E01BB0UL))
#define bFM_CANFD0_TXBCF_CF13                     *((volatile  uint8_t *)(0x42E01BB4UL))
#define bFM4_CANFD0_TXBCF_CF13                    *((volatile  uint8_t *)(0x42E01BB4UL))
#define bFM_CANFD0_TXBCF_CF14                     *((volatile  uint8_t *)(0x42E01BB8UL))
#define bFM4_CANFD0_TXBCF_CF14                    *((volatile  uint8_t *)(0x42E01BB8UL))
#define bFM_CANFD0_TXBCF_CF15                     *((volatile  uint8_t *)(0x42E01BBCUL))
#define bFM4_CANFD0_TXBCF_CF15                    *((volatile  uint8_t *)(0x42E01BBCUL))
#define bFM_CANFD0_TXBCF_CF16                     *((volatile  uint8_t *)(0x42E01BC0UL))
#define bFM4_CANFD0_TXBCF_CF16                    *((volatile  uint8_t *)(0x42E01BC0UL))
#define bFM_CANFD0_TXBCF_CF17                     *((volatile  uint8_t *)(0x42E01BC4UL))
#define bFM4_CANFD0_TXBCF_CF17                    *((volatile  uint8_t *)(0x42E01BC4UL))
#define bFM_CANFD0_TXBCF_CF18                     *((volatile  uint8_t *)(0x42E01BC8UL))
#define bFM4_CANFD0_TXBCF_CF18                    *((volatile  uint8_t *)(0x42E01BC8UL))
#define bFM_CANFD0_TXBCF_CF19                     *((volatile  uint8_t *)(0x42E01BCCUL))
#define bFM4_CANFD0_TXBCF_CF19                    *((volatile  uint8_t *)(0x42E01BCCUL))
#define bFM_CANFD0_TXBCF_CF20                     *((volatile  uint8_t *)(0x42E01BD0UL))
#define bFM4_CANFD0_TXBCF_CF20                    *((volatile  uint8_t *)(0x42E01BD0UL))
#define bFM_CANFD0_TXBCF_CF21                     *((volatile  uint8_t *)(0x42E01BD4UL))
#define bFM4_CANFD0_TXBCF_CF21                    *((volatile  uint8_t *)(0x42E01BD4UL))
#define bFM_CANFD0_TXBCF_CF22                     *((volatile  uint8_t *)(0x42E01BD8UL))
#define bFM4_CANFD0_TXBCF_CF22                    *((volatile  uint8_t *)(0x42E01BD8UL))
#define bFM_CANFD0_TXBCF_CF23                     *((volatile  uint8_t *)(0x42E01BDCUL))
#define bFM4_CANFD0_TXBCF_CF23                    *((volatile  uint8_t *)(0x42E01BDCUL))
#define bFM_CANFD0_TXBCF_CF24                     *((volatile  uint8_t *)(0x42E01BE0UL))
#define bFM4_CANFD0_TXBCF_CF24                    *((volatile  uint8_t *)(0x42E01BE0UL))
#define bFM_CANFD0_TXBCF_CF25                     *((volatile  uint8_t *)(0x42E01BE4UL))
#define bFM4_CANFD0_TXBCF_CF25                    *((volatile  uint8_t *)(0x42E01BE4UL))
#define bFM_CANFD0_TXBCF_CF26                     *((volatile  uint8_t *)(0x42E01BE8UL))
#define bFM4_CANFD0_TXBCF_CF26                    *((volatile  uint8_t *)(0x42E01BE8UL))
#define bFM_CANFD0_TXBCF_CF27                     *((volatile  uint8_t *)(0x42E01BECUL))
#define bFM4_CANFD0_TXBCF_CF27                    *((volatile  uint8_t *)(0x42E01BECUL))
#define bFM_CANFD0_TXBCF_CF28                     *((volatile  uint8_t *)(0x42E01BF0UL))
#define bFM4_CANFD0_TXBCF_CF28                    *((volatile  uint8_t *)(0x42E01BF0UL))
#define bFM_CANFD0_TXBCF_CF29                     *((volatile  uint8_t *)(0x42E01BF4UL))
#define bFM4_CANFD0_TXBCF_CF29                    *((volatile  uint8_t *)(0x42E01BF4UL))
#define bFM_CANFD0_TXBCF_CF30                     *((volatile  uint8_t *)(0x42E01BF8UL))
#define bFM4_CANFD0_TXBCF_CF30                    *((volatile  uint8_t *)(0x42E01BF8UL))
#define bFM_CANFD0_TXBCF_CF31                     *((volatile  uint8_t *)(0x42E01BFCUL))
#define bFM4_CANFD0_TXBCF_CF31                    *((volatile  uint8_t *)(0x42E01BFCUL))

#define bFM_CANFD0_TXBCIE_CFIE0                   *((volatile  uint8_t *)(0x42E01C80UL))
#define bFM4_CANFD0_TXBCIE_CFIE0                  *((volatile  uint8_t *)(0x42E01C80UL))
#define bFM_CANFD0_TXBCIE_CFIE1                   *((volatile  uint8_t *)(0x42E01C84UL))
#define bFM4_CANFD0_TXBCIE_CFIE1                  *((volatile  uint8_t *)(0x42E01C84UL))
#define bFM_CANFD0_TXBCIE_CFIE2                   *((volatile  uint8_t *)(0x42E01C88UL))
#define bFM4_CANFD0_TXBCIE_CFIE2                  *((volatile  uint8_t *)(0x42E01C88UL))
#define bFM_CANFD0_TXBCIE_CFIE3                   *((volatile  uint8_t *)(0x42E01C8CUL))
#define bFM4_CANFD0_TXBCIE_CFIE3                  *((volatile  uint8_t *)(0x42E01C8CUL))
#define bFM_CANFD0_TXBCIE_CFIE4                   *((volatile  uint8_t *)(0x42E01C90UL))
#define bFM4_CANFD0_TXBCIE_CFIE4                  *((volatile  uint8_t *)(0x42E01C90UL))
#define bFM_CANFD0_TXBCIE_CFIE5                   *((volatile  uint8_t *)(0x42E01C94UL))
#define bFM4_CANFD0_TXBCIE_CFIE5                  *((volatile  uint8_t *)(0x42E01C94UL))
#define bFM_CANFD0_TXBCIE_CFIE6                   *((volatile  uint8_t *)(0x42E01C98UL))
#define bFM4_CANFD0_TXBCIE_CFIE6                  *((volatile  uint8_t *)(0x42E01C98UL))
#define bFM_CANFD0_TXBCIE_CFIE7                   *((volatile  uint8_t *)(0x42E01C9CUL))
#define bFM4_CANFD0_TXBCIE_CFIE7                  *((volatile  uint8_t *)(0x42E01C9CUL))
#define bFM_CANFD0_TXBCIE_CFIE8                   *((volatile  uint8_t *)(0x42E01CA0UL))
#define bFM4_CANFD0_TXBCIE_CFIE8                  *((volatile  uint8_t *)(0x42E01CA0UL))
#define bFM_CANFD0_TXBCIE_CFIE9                   *((volatile  uint8_t *)(0x42E01CA4UL))
#define bFM4_CANFD0_TXBCIE_CFIE9                  *((volatile  uint8_t *)(0x42E01CA4UL))
#define bFM_CANFD0_TXBCIE_CFIE10                  *((volatile  uint8_t *)(0x42E01CA8UL))
#define bFM4_CANFD0_TXBCIE_CFIE10                 *((volatile  uint8_t *)(0x42E01CA8UL))
#define bFM_CANFD0_TXBCIE_CFIE11                  *((volatile  uint8_t *)(0x42E01CACUL))
#define bFM4_CANFD0_TXBCIE_CFIE11                 *((volatile  uint8_t *)(0x42E01CACUL))
#define bFM_CANFD0_TXBCIE_CFIE12                  *((volatile  uint8_t *)(0x42E01CB0UL))
#define bFM4_CANFD0_TXBCIE_CFIE12                 *((volatile  uint8_t *)(0x42E01CB0UL))
#define bFM_CANFD0_TXBCIE_CFIE13                  *((volatile  uint8_t *)(0x42E01CB4UL))
#define bFM4_CANFD0_TXBCIE_CFIE13                 *((volatile  uint8_t *)(0x42E01CB4UL))
#define bFM_CANFD0_TXBCIE_CFIE14                  *((volatile  uint8_t *)(0x42E01CB8UL))
#define bFM4_CANFD0_TXBCIE_CFIE14                 *((volatile  uint8_t *)(0x42E01CB8UL))
#define bFM_CANFD0_TXBCIE_CFIE15                  *((volatile  uint8_t *)(0x42E01CBCUL))
#define bFM4_CANFD0_TXBCIE_CFIE15                 *((volatile  uint8_t *)(0x42E01CBCUL))
#define bFM_CANFD0_TXBCIE_CFIE16                  *((volatile  uint8_t *)(0x42E01CC0UL))
#define bFM4_CANFD0_TXBCIE_CFIE16                 *((volatile  uint8_t *)(0x42E01CC0UL))
#define bFM_CANFD0_TXBCIE_CFIE17                  *((volatile  uint8_t *)(0x42E01CC4UL))
#define bFM4_CANFD0_TXBCIE_CFIE17                 *((volatile  uint8_t *)(0x42E01CC4UL))
#define bFM_CANFD0_TXBCIE_CFIE18                  *((volatile  uint8_t *)(0x42E01CC8UL))
#define bFM4_CANFD0_TXBCIE_CFIE18                 *((volatile  uint8_t *)(0x42E01CC8UL))
#define bFM_CANFD0_TXBCIE_CFIE19                  *((volatile  uint8_t *)(0x42E01CCCUL))
#define bFM4_CANFD0_TXBCIE_CFIE19                 *((volatile  uint8_t *)(0x42E01CCCUL))
#define bFM_CANFD0_TXBCIE_CFIE20                  *((volatile  uint8_t *)(0x42E01CD0UL))
#define bFM4_CANFD0_TXBCIE_CFIE20                 *((volatile  uint8_t *)(0x42E01CD0UL))
#define bFM_CANFD0_TXBCIE_CFIE21                  *((volatile  uint8_t *)(0x42E01CD4UL))
#define bFM4_CANFD0_TXBCIE_CFIE21                 *((volatile  uint8_t *)(0x42E01CD4UL))
#define bFM_CANFD0_TXBCIE_CFIE22                  *((volatile  uint8_t *)(0x42E01CD8UL))
#define bFM4_CANFD0_TXBCIE_CFIE22                 *((volatile  uint8_t *)(0x42E01CD8UL))
#define bFM_CANFD0_TXBCIE_CFIE23                  *((volatile  uint8_t *)(0x42E01CDCUL))
#define bFM4_CANFD0_TXBCIE_CFIE23                 *((volatile  uint8_t *)(0x42E01CDCUL))
#define bFM_CANFD0_TXBCIE_CFIE24                  *((volatile  uint8_t *)(0x42E01CE0UL))
#define bFM4_CANFD0_TXBCIE_CFIE24                 *((volatile  uint8_t *)(0x42E01CE0UL))
#define bFM_CANFD0_TXBCIE_CFIE25                  *((volatile  uint8_t *)(0x42E01CE4UL))
#define bFM4_CANFD0_TXBCIE_CFIE25                 *((volatile  uint8_t *)(0x42E01CE4UL))
#define bFM_CANFD0_TXBCIE_CFIE26                  *((volatile  uint8_t *)(0x42E01CE8UL))
#define bFM4_CANFD0_TXBCIE_CFIE26                 *((volatile  uint8_t *)(0x42E01CE8UL))
#define bFM_CANFD0_TXBCIE_CFIE27                  *((volatile  uint8_t *)(0x42E01CECUL))
#define bFM4_CANFD0_TXBCIE_CFIE27                 *((volatile  uint8_t *)(0x42E01CECUL))
#define bFM_CANFD0_TXBCIE_CFIE28                  *((volatile  uint8_t *)(0x42E01CF0UL))
#define bFM4_CANFD0_TXBCIE_CFIE28                 *((volatile  uint8_t *)(0x42E01CF0UL))
#define bFM_CANFD0_TXBCIE_CFIE29                  *((volatile  uint8_t *)(0x42E01CF4UL))
#define bFM4_CANFD0_TXBCIE_CFIE29                 *((volatile  uint8_t *)(0x42E01CF4UL))
#define bFM_CANFD0_TXBCIE_CFIE30                  *((volatile  uint8_t *)(0x42E01CF8UL))
#define bFM4_CANFD0_TXBCIE_CFIE30                 *((volatile  uint8_t *)(0x42E01CF8UL))
#define bFM_CANFD0_TXBCIE_CFIE31                  *((volatile  uint8_t *)(0x42E01CFCUL))
#define bFM4_CANFD0_TXBCIE_CFIE31                 *((volatile  uint8_t *)(0x42E01CFCUL))

#define bFM_CANFD0_TXBCR_CR0                      *((volatile  uint8_t *)(0x42E01A80UL))
#define bFM4_CANFD0_TXBCR_CR0                     *((volatile  uint8_t *)(0x42E01A80UL))
#define bFM_CANFD0_TXBCR_CR1                      *((volatile  uint8_t *)(0x42E01A84UL))
#define bFM4_CANFD0_TXBCR_CR1                     *((volatile  uint8_t *)(0x42E01A84UL))
#define bFM_CANFD0_TXBCR_CR2                      *((volatile  uint8_t *)(0x42E01A88UL))
#define bFM4_CANFD0_TXBCR_CR2                     *((volatile  uint8_t *)(0x42E01A88UL))
#define bFM_CANFD0_TXBCR_CR3                      *((volatile  uint8_t *)(0x42E01A8CUL))
#define bFM4_CANFD0_TXBCR_CR3                     *((volatile  uint8_t *)(0x42E01A8CUL))
#define bFM_CANFD0_TXBCR_CR4                      *((volatile  uint8_t *)(0x42E01A90UL))
#define bFM4_CANFD0_TXBCR_CR4                     *((volatile  uint8_t *)(0x42E01A90UL))
#define bFM_CANFD0_TXBCR_CR5                      *((volatile  uint8_t *)(0x42E01A94UL))
#define bFM4_CANFD0_TXBCR_CR5                     *((volatile  uint8_t *)(0x42E01A94UL))
#define bFM_CANFD0_TXBCR_CR6                      *((volatile  uint8_t *)(0x42E01A98UL))
#define bFM4_CANFD0_TXBCR_CR6                     *((volatile  uint8_t *)(0x42E01A98UL))
#define bFM_CANFD0_TXBCR_CR7                      *((volatile  uint8_t *)(0x42E01A9CUL))
#define bFM4_CANFD0_TXBCR_CR7                     *((volatile  uint8_t *)(0x42E01A9CUL))
#define bFM_CANFD0_TXBCR_CR8                      *((volatile  uint8_t *)(0x42E01AA0UL))
#define bFM4_CANFD0_TXBCR_CR8                     *((volatile  uint8_t *)(0x42E01AA0UL))
#define bFM_CANFD0_TXBCR_CR9                      *((volatile  uint8_t *)(0x42E01AA4UL))
#define bFM4_CANFD0_TXBCR_CR9                     *((volatile  uint8_t *)(0x42E01AA4UL))
#define bFM_CANFD0_TXBCR_CR10                     *((volatile  uint8_t *)(0x42E01AA8UL))
#define bFM4_CANFD0_TXBCR_CR10                    *((volatile  uint8_t *)(0x42E01AA8UL))
#define bFM_CANFD0_TXBCR_CR11                     *((volatile  uint8_t *)(0x42E01AACUL))
#define bFM4_CANFD0_TXBCR_CR11                    *((volatile  uint8_t *)(0x42E01AACUL))
#define bFM_CANFD0_TXBCR_CR12                     *((volatile  uint8_t *)(0x42E01AB0UL))
#define bFM4_CANFD0_TXBCR_CR12                    *((volatile  uint8_t *)(0x42E01AB0UL))
#define bFM_CANFD0_TXBCR_CR13                     *((volatile  uint8_t *)(0x42E01AB4UL))
#define bFM4_CANFD0_TXBCR_CR13                    *((volatile  uint8_t *)(0x42E01AB4UL))
#define bFM_CANFD0_TXBCR_CR14                     *((volatile  uint8_t *)(0x42E01AB8UL))
#define bFM4_CANFD0_TXBCR_CR14                    *((volatile  uint8_t *)(0x42E01AB8UL))
#define bFM_CANFD0_TXBCR_CR15                     *((volatile  uint8_t *)(0x42E01ABCUL))
#define bFM4_CANFD0_TXBCR_CR15                    *((volatile  uint8_t *)(0x42E01ABCUL))
#define bFM_CANFD0_TXBCR_CR16                     *((volatile  uint8_t *)(0x42E01AC0UL))
#define bFM4_CANFD0_TXBCR_CR16                    *((volatile  uint8_t *)(0x42E01AC0UL))
#define bFM_CANFD0_TXBCR_CR17                     *((volatile  uint8_t *)(0x42E01AC4UL))
#define bFM4_CANFD0_TXBCR_CR17                    *((volatile  uint8_t *)(0x42E01AC4UL))
#define bFM_CANFD0_TXBCR_CR18                     *((volatile  uint8_t *)(0x42E01AC8UL))
#define bFM4_CANFD0_TXBCR_CR18                    *((volatile  uint8_t *)(0x42E01AC8UL))
#define bFM_CANFD0_TXBCR_CR19                     *((volatile  uint8_t *)(0x42E01ACCUL))
#define bFM4_CANFD0_TXBCR_CR19                    *((volatile  uint8_t *)(0x42E01ACCUL))
#define bFM_CANFD0_TXBCR_CR20                     *((volatile  uint8_t *)(0x42E01AD0UL))
#define bFM4_CANFD0_TXBCR_CR20                    *((volatile  uint8_t *)(0x42E01AD0UL))
#define bFM_CANFD0_TXBCR_CR21                     *((volatile  uint8_t *)(0x42E01AD4UL))
#define bFM4_CANFD0_TXBCR_CR21                    *((volatile  uint8_t *)(0x42E01AD4UL))
#define bFM_CANFD0_TXBCR_CR22                     *((volatile  uint8_t *)(0x42E01AD8UL))
#define bFM4_CANFD0_TXBCR_CR22                    *((volatile  uint8_t *)(0x42E01AD8UL))
#define bFM_CANFD0_TXBCR_CR23                     *((volatile  uint8_t *)(0x42E01ADCUL))
#define bFM4_CANFD0_TXBCR_CR23                    *((volatile  uint8_t *)(0x42E01ADCUL))
#define bFM_CANFD0_TXBCR_CR24                     *((volatile  uint8_t *)(0x42E01AE0UL))
#define bFM4_CANFD0_TXBCR_CR24                    *((volatile  uint8_t *)(0x42E01AE0UL))
#define bFM_CANFD0_TXBCR_CR25                     *((volatile  uint8_t *)(0x42E01AE4UL))
#define bFM4_CANFD0_TXBCR_CR25                    *((volatile  uint8_t *)(0x42E01AE4UL))
#define bFM_CANFD0_TXBCR_CR26                     *((volatile  uint8_t *)(0x42E01AE8UL))
#define bFM4_CANFD0_TXBCR_CR26                    *((volatile  uint8_t *)(0x42E01AE8UL))
#define bFM_CANFD0_TXBCR_CR27                     *((volatile  uint8_t *)(0x42E01AECUL))
#define bFM4_CANFD0_TXBCR_CR27                    *((volatile  uint8_t *)(0x42E01AECUL))
#define bFM_CANFD0_TXBCR_CR28                     *((volatile  uint8_t *)(0x42E01AF0UL))
#define bFM4_CANFD0_TXBCR_CR28                    *((volatile  uint8_t *)(0x42E01AF0UL))
#define bFM_CANFD0_TXBCR_CR29                     *((volatile  uint8_t *)(0x42E01AF4UL))
#define bFM4_CANFD0_TXBCR_CR29                    *((volatile  uint8_t *)(0x42E01AF4UL))
#define bFM_CANFD0_TXBCR_CR30                     *((volatile  uint8_t *)(0x42E01AF8UL))
#define bFM4_CANFD0_TXBCR_CR30                    *((volatile  uint8_t *)(0x42E01AF8UL))
#define bFM_CANFD0_TXBCR_CR31                     *((volatile  uint8_t *)(0x42E01AFCUL))
#define bFM4_CANFD0_TXBCR_CR31                    *((volatile  uint8_t *)(0x42E01AFCUL))

#define bFM_CANFD0_TXBRP_TRP0                     *((volatile  uint8_t *)(0x42E01980UL))
#define bFM4_CANFD0_TXBRP_TRP0                    *((volatile  uint8_t *)(0x42E01980UL))
#define bFM_CANFD0_TXBRP_TRP1                     *((volatile  uint8_t *)(0x42E01984UL))
#define bFM4_CANFD0_TXBRP_TRP1                    *((volatile  uint8_t *)(0x42E01984UL))
#define bFM_CANFD0_TXBRP_TRP2                     *((volatile  uint8_t *)(0x42E01988UL))
#define bFM4_CANFD0_TXBRP_TRP2                    *((volatile  uint8_t *)(0x42E01988UL))
#define bFM_CANFD0_TXBRP_TRP3                     *((volatile  uint8_t *)(0x42E0198CUL))
#define bFM4_CANFD0_TXBRP_TRP3                    *((volatile  uint8_t *)(0x42E0198CUL))
#define bFM_CANFD0_TXBRP_TRP4                     *((volatile  uint8_t *)(0x42E01990UL))
#define bFM4_CANFD0_TXBRP_TRP4                    *((volatile  uint8_t *)(0x42E01990UL))
#define bFM_CANFD0_TXBRP_TRP5                     *((volatile  uint8_t *)(0x42E01994UL))
#define bFM4_CANFD0_TXBRP_TRP5                    *((volatile  uint8_t *)(0x42E01994UL))
#define bFM_CANFD0_TXBRP_TRP6                     *((volatile  uint8_t *)(0x42E01998UL))
#define bFM4_CANFD0_TXBRP_TRP6                    *((volatile  uint8_t *)(0x42E01998UL))
#define bFM_CANFD0_TXBRP_TRP7                     *((volatile  uint8_t *)(0x42E0199CUL))
#define bFM4_CANFD0_TXBRP_TRP7                    *((volatile  uint8_t *)(0x42E0199CUL))
#define bFM_CANFD0_TXBRP_TRP8                     *((volatile  uint8_t *)(0x42E019A0UL))
#define bFM4_CANFD0_TXBRP_TRP8                    *((volatile  uint8_t *)(0x42E019A0UL))
#define bFM_CANFD0_TXBRP_TRP9                     *((volatile  uint8_t *)(0x42E019A4UL))
#define bFM4_CANFD0_TXBRP_TRP9                    *((volatile  uint8_t *)(0x42E019A4UL))
#define bFM_CANFD0_TXBRP_TRP10                    *((volatile  uint8_t *)(0x42E019A8UL))
#define bFM4_CANFD0_TXBRP_TRP10                   *((volatile  uint8_t *)(0x42E019A8UL))
#define bFM_CANFD0_TXBRP_TRP11                    *((volatile  uint8_t *)(0x42E019ACUL))
#define bFM4_CANFD0_TXBRP_TRP11                   *((volatile  uint8_t *)(0x42E019ACUL))
#define bFM_CANFD0_TXBRP_TRP12                    *((volatile  uint8_t *)(0x42E019B0UL))
#define bFM4_CANFD0_TXBRP_TRP12                   *((volatile  uint8_t *)(0x42E019B0UL))
#define bFM_CANFD0_TXBRP_TRP13                    *((volatile  uint8_t *)(0x42E019B4UL))
#define bFM4_CANFD0_TXBRP_TRP13                   *((volatile  uint8_t *)(0x42E019B4UL))
#define bFM_CANFD0_TXBRP_TRP14                    *((volatile  uint8_t *)(0x42E019B8UL))
#define bFM4_CANFD0_TXBRP_TRP14                   *((volatile  uint8_t *)(0x42E019B8UL))
#define bFM_CANFD0_TXBRP_TRP15                    *((volatile  uint8_t *)(0x42E019BCUL))
#define bFM4_CANFD0_TXBRP_TRP15                   *((volatile  uint8_t *)(0x42E019BCUL))
#define bFM_CANFD0_TXBRP_TRP16                    *((volatile  uint8_t *)(0x42E019C0UL))
#define bFM4_CANFD0_TXBRP_TRP16                   *((volatile  uint8_t *)(0x42E019C0UL))
#define bFM_CANFD0_TXBRP_TRP17                    *((volatile  uint8_t *)(0x42E019C4UL))
#define bFM4_CANFD0_TXBRP_TRP17                   *((volatile  uint8_t *)(0x42E019C4UL))
#define bFM_CANFD0_TXBRP_TRP18                    *((volatile  uint8_t *)(0x42E019C8UL))
#define bFM4_CANFD0_TXBRP_TRP18                   *((volatile  uint8_t *)(0x42E019C8UL))
#define bFM_CANFD0_TXBRP_TRP19                    *((volatile  uint8_t *)(0x42E019CCUL))
#define bFM4_CANFD0_TXBRP_TRP19                   *((volatile  uint8_t *)(0x42E019CCUL))
#define bFM_CANFD0_TXBRP_TRP20                    *((volatile  uint8_t *)(0x42E019D0UL))
#define bFM4_CANFD0_TXBRP_TRP20                   *((volatile  uint8_t *)(0x42E019D0UL))
#define bFM_CANFD0_TXBRP_TRP21                    *((volatile  uint8_t *)(0x42E019D4UL))
#define bFM4_CANFD0_TXBRP_TRP21                   *((volatile  uint8_t *)(0x42E019D4UL))
#define bFM_CANFD0_TXBRP_TRP22                    *((volatile  uint8_t *)(0x42E019D8UL))
#define bFM4_CANFD0_TXBRP_TRP22                   *((volatile  uint8_t *)(0x42E019D8UL))
#define bFM_CANFD0_TXBRP_TRP23                    *((volatile  uint8_t *)(0x42E019DCUL))
#define bFM4_CANFD0_TXBRP_TRP23                   *((volatile  uint8_t *)(0x42E019DCUL))
#define bFM_CANFD0_TXBRP_TRP24                    *((volatile  uint8_t *)(0x42E019E0UL))
#define bFM4_CANFD0_TXBRP_TRP24                   *((volatile  uint8_t *)(0x42E019E0UL))
#define bFM_CANFD0_TXBRP_TRP25                    *((volatile  uint8_t *)(0x42E019E4UL))
#define bFM4_CANFD0_TXBRP_TRP25                   *((volatile  uint8_t *)(0x42E019E4UL))
#define bFM_CANFD0_TXBRP_TRP26                    *((volatile  uint8_t *)(0x42E019E8UL))
#define bFM4_CANFD0_TXBRP_TRP26                   *((volatile  uint8_t *)(0x42E019E8UL))
#define bFM_CANFD0_TXBRP_TRP27                    *((volatile  uint8_t *)(0x42E019ECUL))
#define bFM4_CANFD0_TXBRP_TRP27                   *((volatile  uint8_t *)(0x42E019ECUL))
#define bFM_CANFD0_TXBRP_TRP28                    *((volatile  uint8_t *)(0x42E019F0UL))
#define bFM4_CANFD0_TXBRP_TRP28                   *((volatile  uint8_t *)(0x42E019F0UL))
#define bFM_CANFD0_TXBRP_TRP29                    *((volatile  uint8_t *)(0x42E019F4UL))
#define bFM4_CANFD0_TXBRP_TRP29                   *((volatile  uint8_t *)(0x42E019F4UL))
#define bFM_CANFD0_TXBRP_TRP30                    *((volatile  uint8_t *)(0x42E019F8UL))
#define bFM4_CANFD0_TXBRP_TRP30                   *((volatile  uint8_t *)(0x42E019F8UL))
#define bFM_CANFD0_TXBRP_TRP31                    *((volatile  uint8_t *)(0x42E019FCUL))
#define bFM4_CANFD0_TXBRP_TRP31                   *((volatile  uint8_t *)(0x42E019FCUL))

#define bFM_CANFD0_TXBTIE_TIE0                    *((volatile  uint8_t *)(0x42E01C00UL))
#define bFM4_CANFD0_TXBTIE_TIE0                   *((volatile  uint8_t *)(0x42E01C00UL))
#define bFM_CANFD0_TXBTIE_TIE1                    *((volatile  uint8_t *)(0x42E01C04UL))
#define bFM4_CANFD0_TXBTIE_TIE1                   *((volatile  uint8_t *)(0x42E01C04UL))
#define bFM_CANFD0_TXBTIE_TIE2                    *((volatile  uint8_t *)(0x42E01C08UL))
#define bFM4_CANFD0_TXBTIE_TIE2                   *((volatile  uint8_t *)(0x42E01C08UL))
#define bFM_CANFD0_TXBTIE_TIE3                    *((volatile  uint8_t *)(0x42E01C0CUL))
#define bFM4_CANFD0_TXBTIE_TIE3                   *((volatile  uint8_t *)(0x42E01C0CUL))
#define bFM_CANFD0_TXBTIE_TIE4                    *((volatile  uint8_t *)(0x42E01C10UL))
#define bFM4_CANFD0_TXBTIE_TIE4                   *((volatile  uint8_t *)(0x42E01C10UL))
#define bFM_CANFD0_TXBTIE_TIE5                    *((volatile  uint8_t *)(0x42E01C14UL))
#define bFM4_CANFD0_TXBTIE_TIE5                   *((volatile  uint8_t *)(0x42E01C14UL))
#define bFM_CANFD0_TXBTIE_TIE6                    *((volatile  uint8_t *)(0x42E01C18UL))
#define bFM4_CANFD0_TXBTIE_TIE6                   *((volatile  uint8_t *)(0x42E01C18UL))
#define bFM_CANFD0_TXBTIE_TIE7                    *((volatile  uint8_t *)(0x42E01C1CUL))
#define bFM4_CANFD0_TXBTIE_TIE7                   *((volatile  uint8_t *)(0x42E01C1CUL))
#define bFM_CANFD0_TXBTIE_TIE8                    *((volatile  uint8_t *)(0x42E01C20UL))
#define bFM4_CANFD0_TXBTIE_TIE8                   *((volatile  uint8_t *)(0x42E01C20UL))
#define bFM_CANFD0_TXBTIE_TIE9                    *((volatile  uint8_t *)(0x42E01C24UL))
#define bFM4_CANFD0_TXBTIE_TIE9                   *((volatile  uint8_t *)(0x42E01C24UL))
#define bFM_CANFD0_TXBTIE_TIE10                   *((volatile  uint8_t *)(0x42E01C28UL))
#define bFM4_CANFD0_TXBTIE_TIE10                  *((volatile  uint8_t *)(0x42E01C28UL))
#define bFM_CANFD0_TXBTIE_TIE11                   *((volatile  uint8_t *)(0x42E01C2CUL))
#define bFM4_CANFD0_TXBTIE_TIE11                  *((volatile  uint8_t *)(0x42E01C2CUL))
#define bFM_CANFD0_TXBTIE_TIE12                   *((volatile  uint8_t *)(0x42E01C30UL))
#define bFM4_CANFD0_TXBTIE_TIE12                  *((volatile  uint8_t *)(0x42E01C30UL))
#define bFM_CANFD0_TXBTIE_TIE13                   *((volatile  uint8_t *)(0x42E01C34UL))
#define bFM4_CANFD0_TXBTIE_TIE13                  *((volatile  uint8_t *)(0x42E01C34UL))
#define bFM_CANFD0_TXBTIE_TIE14                   *((volatile  uint8_t *)(0x42E01C38UL))
#define bFM4_CANFD0_TXBTIE_TIE14                  *((volatile  uint8_t *)(0x42E01C38UL))
#define bFM_CANFD0_TXBTIE_TIE15                   *((volatile  uint8_t *)(0x42E01C3CUL))
#define bFM4_CANFD0_TXBTIE_TIE15                  *((volatile  uint8_t *)(0x42E01C3CUL))
#define bFM_CANFD0_TXBTIE_TIE16                   *((volatile  uint8_t *)(0x42E01C40UL))
#define bFM4_CANFD0_TXBTIE_TIE16                  *((volatile  uint8_t *)(0x42E01C40UL))
#define bFM_CANFD0_TXBTIE_TIE17                   *((volatile  uint8_t *)(0x42E01C44UL))
#define bFM4_CANFD0_TXBTIE_TIE17                  *((volatile  uint8_t *)(0x42E01C44UL))
#define bFM_CANFD0_TXBTIE_TIE18                   *((volatile  uint8_t *)(0x42E01C48UL))
#define bFM4_CANFD0_TXBTIE_TIE18                  *((volatile  uint8_t *)(0x42E01C48UL))
#define bFM_CANFD0_TXBTIE_TIE19                   *((volatile  uint8_t *)(0x42E01C4CUL))
#define bFM4_CANFD0_TXBTIE_TIE19                  *((volatile  uint8_t *)(0x42E01C4CUL))
#define bFM_CANFD0_TXBTIE_TIE20                   *((volatile  uint8_t *)(0x42E01C50UL))
#define bFM4_CANFD0_TXBTIE_TIE20                  *((volatile  uint8_t *)(0x42E01C50UL))
#define bFM_CANFD0_TXBTIE_TIE21                   *((volatile  uint8_t *)(0x42E01C54UL))
#define bFM4_CANFD0_TXBTIE_TIE21                  *((volatile  uint8_t *)(0x42E01C54UL))
#define bFM_CANFD0_TXBTIE_TIE22                   *((volatile  uint8_t *)(0x42E01C58UL))
#define bFM4_CANFD0_TXBTIE_TIE22                  *((volatile  uint8_t *)(0x42E01C58UL))
#define bFM_CANFD0_TXBTIE_TIE23                   *((volatile  uint8_t *)(0x42E01C5CUL))
#define bFM4_CANFD0_TXBTIE_TIE23                  *((volatile  uint8_t *)(0x42E01C5CUL))
#define bFM_CANFD0_TXBTIE_TIE24                   *((volatile  uint8_t *)(0x42E01C60UL))
#define bFM4_CANFD0_TXBTIE_TIE24                  *((volatile  uint8_t *)(0x42E01C60UL))
#define bFM_CANFD0_TXBTIE_TIE25                   *((volatile  uint8_t *)(0x42E01C64UL))
#define bFM4_CANFD0_TXBTIE_TIE25                  *((volatile  uint8_t *)(0x42E01C64UL))
#define bFM_CANFD0_TXBTIE_TIE26                   *((volatile  uint8_t *)(0x42E01C68UL))
#define bFM4_CANFD0_TXBTIE_TIE26                  *((volatile  uint8_t *)(0x42E01C68UL))
#define bFM_CANFD0_TXBTIE_TIE27                   *((volatile  uint8_t *)(0x42E01C6CUL))
#define bFM4_CANFD0_TXBTIE_TIE27                  *((volatile  uint8_t *)(0x42E01C6CUL))
#define bFM_CANFD0_TXBTIE_TIE28                   *((volatile  uint8_t *)(0x42E01C70UL))
#define bFM4_CANFD0_TXBTIE_TIE28                  *((volatile  uint8_t *)(0x42E01C70UL))
#define bFM_CANFD0_TXBTIE_TIE29                   *((volatile  uint8_t *)(0x42E01C74UL))
#define bFM4_CANFD0_TXBTIE_TIE29                  *((volatile  uint8_t *)(0x42E01C74UL))
#define bFM_CANFD0_TXBTIE_TIE30                   *((volatile  uint8_t *)(0x42E01C78UL))
#define bFM4_CANFD0_TXBTIE_TIE30                  *((volatile  uint8_t *)(0x42E01C78UL))
#define bFM_CANFD0_TXBTIE_TIE31                   *((volatile  uint8_t *)(0x42E01C7CUL))
#define bFM4_CANFD0_TXBTIE_TIE31                  *((volatile  uint8_t *)(0x42E01C7CUL))

#define bFM_CANFD0_TXBTO_TO0                      *((volatile  uint8_t *)(0x42E01B00UL))
#define bFM4_CANFD0_TXBTO_TO0                     *((volatile  uint8_t *)(0x42E01B00UL))
#define bFM_CANFD0_TXBTO_TO1                      *((volatile  uint8_t *)(0x42E01B04UL))
#define bFM4_CANFD0_TXBTO_TO1                     *((volatile  uint8_t *)(0x42E01B04UL))
#define bFM_CANFD0_TXBTO_TO2                      *((volatile  uint8_t *)(0x42E01B08UL))
#define bFM4_CANFD0_TXBTO_TO2                     *((volatile  uint8_t *)(0x42E01B08UL))
#define bFM_CANFD0_TXBTO_TO3                      *((volatile  uint8_t *)(0x42E01B0CUL))
#define bFM4_CANFD0_TXBTO_TO3                     *((volatile  uint8_t *)(0x42E01B0CUL))
#define bFM_CANFD0_TXBTO_TO4                      *((volatile  uint8_t *)(0x42E01B10UL))
#define bFM4_CANFD0_TXBTO_TO4                     *((volatile  uint8_t *)(0x42E01B10UL))
#define bFM_CANFD0_TXBTO_TO5                      *((volatile  uint8_t *)(0x42E01B14UL))
#define bFM4_CANFD0_TXBTO_TO5                     *((volatile  uint8_t *)(0x42E01B14UL))
#define bFM_CANFD0_TXBTO_TO6                      *((volatile  uint8_t *)(0x42E01B18UL))
#define bFM4_CANFD0_TXBTO_TO6                     *((volatile  uint8_t *)(0x42E01B18UL))
#define bFM_CANFD0_TXBTO_TO7                      *((volatile  uint8_t *)(0x42E01B1CUL))
#define bFM4_CANFD0_TXBTO_TO7                     *((volatile  uint8_t *)(0x42E01B1CUL))
#define bFM_CANFD0_TXBTO_TO8                      *((volatile  uint8_t *)(0x42E01B20UL))
#define bFM4_CANFD0_TXBTO_TO8                     *((volatile  uint8_t *)(0x42E01B20UL))
#define bFM_CANFD0_TXBTO_TO9                      *((volatile  uint8_t *)(0x42E01B24UL))
#define bFM4_CANFD0_TXBTO_TO9                     *((volatile  uint8_t *)(0x42E01B24UL))
#define bFM_CANFD0_TXBTO_TO10                     *((volatile  uint8_t *)(0x42E01B28UL))
#define bFM4_CANFD0_TXBTO_TO10                    *((volatile  uint8_t *)(0x42E01B28UL))
#define bFM_CANFD0_TXBTO_TO11                     *((volatile  uint8_t *)(0x42E01B2CUL))
#define bFM4_CANFD0_TXBTO_TO11                    *((volatile  uint8_t *)(0x42E01B2CUL))
#define bFM_CANFD0_TXBTO_TO12                     *((volatile  uint8_t *)(0x42E01B30UL))
#define bFM4_CANFD0_TXBTO_TO12                    *((volatile  uint8_t *)(0x42E01B30UL))
#define bFM_CANFD0_TXBTO_TO13                     *((volatile  uint8_t *)(0x42E01B34UL))
#define bFM4_CANFD0_TXBTO_TO13                    *((volatile  uint8_t *)(0x42E01B34UL))
#define bFM_CANFD0_TXBTO_TO14                     *((volatile  uint8_t *)(0x42E01B38UL))
#define bFM4_CANFD0_TXBTO_TO14                    *((volatile  uint8_t *)(0x42E01B38UL))
#define bFM_CANFD0_TXBTO_TO15                     *((volatile  uint8_t *)(0x42E01B3CUL))
#define bFM4_CANFD0_TXBTO_TO15                    *((volatile  uint8_t *)(0x42E01B3CUL))
#define bFM_CANFD0_TXBTO_TO16                     *((volatile  uint8_t *)(0x42E01B40UL))
#define bFM4_CANFD0_TXBTO_TO16                    *((volatile  uint8_t *)(0x42E01B40UL))
#define bFM_CANFD0_TXBTO_TO17                     *((volatile  uint8_t *)(0x42E01B44UL))
#define bFM4_CANFD0_TXBTO_TO17                    *((volatile  uint8_t *)(0x42E01B44UL))
#define bFM_CANFD0_TXBTO_TO18                     *((volatile  uint8_t *)(0x42E01B48UL))
#define bFM4_CANFD0_TXBTO_TO18                    *((volatile  uint8_t *)(0x42E01B48UL))
#define bFM_CANFD0_TXBTO_TO19                     *((volatile  uint8_t *)(0x42E01B4CUL))
#define bFM4_CANFD0_TXBTO_TO19                    *((volatile  uint8_t *)(0x42E01B4CUL))
#define bFM_CANFD0_TXBTO_TO20                     *((volatile  uint8_t *)(0x42E01B50UL))
#define bFM4_CANFD0_TXBTO_TO20                    *((volatile  uint8_t *)(0x42E01B50UL))
#define bFM_CANFD0_TXBTO_TO21                     *((volatile  uint8_t *)(0x42E01B54UL))
#define bFM4_CANFD0_TXBTO_TO21                    *((volatile  uint8_t *)(0x42E01B54UL))
#define bFM_CANFD0_TXBTO_TO22                     *((volatile  uint8_t *)(0x42E01B58UL))
#define bFM4_CANFD0_TXBTO_TO22                    *((volatile  uint8_t *)(0x42E01B58UL))
#define bFM_CANFD0_TXBTO_TO23                     *((volatile  uint8_t *)(0x42E01B5CUL))
#define bFM4_CANFD0_TXBTO_TO23                    *((volatile  uint8_t *)(0x42E01B5CUL))
#define bFM_CANFD0_TXBTO_TO24                     *((volatile  uint8_t *)(0x42E01B60UL))
#define bFM4_CANFD0_TXBTO_TO24                    *((volatile  uint8_t *)(0x42E01B60UL))
#define bFM_CANFD0_TXBTO_TO25                     *((volatile  uint8_t *)(0x42E01B64UL))
#define bFM4_CANFD0_TXBTO_TO25                    *((volatile  uint8_t *)(0x42E01B64UL))
#define bFM_CANFD0_TXBTO_TO26                     *((volatile  uint8_t *)(0x42E01B68UL))
#define bFM4_CANFD0_TXBTO_TO26                    *((volatile  uint8_t *)(0x42E01B68UL))
#define bFM_CANFD0_TXBTO_TO27                     *((volatile  uint8_t *)(0x42E01B6CUL))
#define bFM4_CANFD0_TXBTO_TO27                    *((volatile  uint8_t *)(0x42E01B6CUL))
#define bFM_CANFD0_TXBTO_TO28                     *((volatile  uint8_t *)(0x42E01B70UL))
#define bFM4_CANFD0_TXBTO_TO28                    *((volatile  uint8_t *)(0x42E01B70UL))
#define bFM_CANFD0_TXBTO_TO29                     *((volatile  uint8_t *)(0x42E01B74UL))
#define bFM4_CANFD0_TXBTO_TO29                    *((volatile  uint8_t *)(0x42E01B74UL))
#define bFM_CANFD0_TXBTO_TO30                     *((volatile  uint8_t *)(0x42E01B78UL))
#define bFM4_CANFD0_TXBTO_TO30                    *((volatile  uint8_t *)(0x42E01B78UL))
#define bFM_CANFD0_TXBTO_TO31                     *((volatile  uint8_t *)(0x42E01B7CUL))
#define bFM4_CANFD0_TXBTO_TO31                    *((volatile  uint8_t *)(0x42E01B7CUL))

#define bFM_CANFD0_TXFQS_TFQF                     *((volatile  uint8_t *)(0x42E018D4UL))
#define bFM4_CANFD0_TXFQS_TFQF                    *((volatile  uint8_t *)(0x42E018D4UL))

#define bFM_CANFD0_TXFS_EFF                       *((volatile  uint8_t *)(0x42E01EE0UL))
#define bFM4_CANFD0_TXFS_EFF                      *((volatile  uint8_t *)(0x42E01EE0UL))
#define bFM_CANFD0_TXFS_TEFL                      *((volatile  uint8_t *)(0x42E01EE4UL))
#define bFM4_CANFD0_TXFS_TEFL                     *((volatile  uint8_t *)(0x42E01EE4UL))


/*******************************************************************************
* CANPRES Registers CANPRES
*   Bitband Section
*******************************************************************************/

/*******************************************************************************
* CLK_GATING Registers CLK_GATING
*   Bitband Section
*******************************************************************************/
#define bFM_CLK_GATING_CKEN0_MFSCK0               *((volatile  uint8_t *)(0x42782000UL))
#define bFM4_CLK_GATING_CKEN0_MFSCK0              *((volatile  uint8_t *)(0x42782000UL))
#define bFM_CLK_GATING_CKEN0_MFSCK1               *((volatile  uint8_t *)(0x42782004UL))
#define bFM4_CLK_GATING_CKEN0_MFSCK1              *((volatile  uint8_t *)(0x42782004UL))
#define bFM_CLK_GATING_CKEN0_MFSCK2               *((volatile  uint8_t *)(0x42782008UL))
#define bFM4_CLK_GATING_CKEN0_MFSCK2              *((volatile  uint8_t *)(0x42782008UL))
#define bFM_CLK_GATING_CKEN0_MFSCK3               *((volatile  uint8_t *)(0x4278200CUL))
#define bFM4_CLK_GATING_CKEN0_MFSCK3              *((volatile  uint8_t *)(0x4278200CUL))
#define bFM_CLK_GATING_CKEN0_MFSCK4               *((volatile  uint8_t *)(0x42782010UL))
#define bFM4_CLK_GATING_CKEN0_MFSCK4              *((volatile  uint8_t *)(0x42782010UL))
#define bFM_CLK_GATING_CKEN0_MFSCK5               *((volatile  uint8_t *)(0x42782014UL))
#define bFM4_CLK_GATING_CKEN0_MFSCK5              *((volatile  uint8_t *)(0x42782014UL))
#define bFM_CLK_GATING_CKEN0_MFSCK6               *((volatile  uint8_t *)(0x42782018UL))
#define bFM4_CLK_GATING_CKEN0_MFSCK6              *((volatile  uint8_t *)(0x42782018UL))
#define bFM_CLK_GATING_CKEN0_MFSCK7               *((volatile  uint8_t *)(0x4278201CUL))
#define bFM4_CLK_GATING_CKEN0_MFSCK7              *((volatile  uint8_t *)(0x4278201CUL))
#define bFM_CLK_GATING_CKEN0_MFSCK8               *((volatile  uint8_t *)(0x42782020UL))
#define bFM4_CLK_GATING_CKEN0_MFSCK8              *((volatile  uint8_t *)(0x42782020UL))
#define bFM_CLK_GATING_CKEN0_MFSCK9               *((volatile  uint8_t *)(0x42782024UL))
#define bFM4_CLK_GATING_CKEN0_MFSCK9              *((volatile  uint8_t *)(0x42782024UL))
#define bFM_CLK_GATING_CKEN0_MFSCK10              *((volatile  uint8_t *)(0x42782028UL))
#define bFM4_CLK_GATING_CKEN0_MFSCK10             *((volatile  uint8_t *)(0x42782028UL))
#define bFM_CLK_GATING_CKEN0_MFSCK11              *((volatile  uint8_t *)(0x4278202CUL))
#define bFM4_CLK_GATING_CKEN0_MFSCK11             *((volatile  uint8_t *)(0x4278202CUL))
#define bFM_CLK_GATING_CKEN0_MFSCK12              *((volatile  uint8_t *)(0x42782030UL))
#define bFM4_CLK_GATING_CKEN0_MFSCK12             *((volatile  uint8_t *)(0x42782030UL))
#define bFM_CLK_GATING_CKEN0_MFSCK13              *((volatile  uint8_t *)(0x42782034UL))
#define bFM4_CLK_GATING_CKEN0_MFSCK13             *((volatile  uint8_t *)(0x42782034UL))
#define bFM_CLK_GATING_CKEN0_MFSCK14              *((volatile  uint8_t *)(0x42782038UL))
#define bFM4_CLK_GATING_CKEN0_MFSCK14             *((volatile  uint8_t *)(0x42782038UL))
#define bFM_CLK_GATING_CKEN0_MFSCK15              *((volatile  uint8_t *)(0x4278203CUL))
#define bFM4_CLK_GATING_CKEN0_MFSCK15             *((volatile  uint8_t *)(0x4278203CUL))
#define bFM_CLK_GATING_CKEN0_ADCCK0               *((volatile  uint8_t *)(0x42782040UL))
#define bFM4_CLK_GATING_CKEN0_ADCCK0              *((volatile  uint8_t *)(0x42782040UL))
#define bFM_CLK_GATING_CKEN0_ADCCK1               *((volatile  uint8_t *)(0x42782044UL))
#define bFM4_CLK_GATING_CKEN0_ADCCK1              *((volatile  uint8_t *)(0x42782044UL))
#define bFM_CLK_GATING_CKEN0_ADCCK2               *((volatile  uint8_t *)(0x42782048UL))
#define bFM4_CLK_GATING_CKEN0_ADCCK2              *((volatile  uint8_t *)(0x42782048UL))
#define bFM_CLK_GATING_CKEN0_ADCCK3               *((volatile  uint8_t *)(0x4278204CUL))
#define bFM4_CLK_GATING_CKEN0_ADCCK3              *((volatile  uint8_t *)(0x4278204CUL))
#define bFM_CLK_GATING_CKEN0_DMACK                *((volatile  uint8_t *)(0x42782060UL))
#define bFM4_CLK_GATING_CKEN0_DMACK               *((volatile  uint8_t *)(0x42782060UL))
#define bFM_CLK_GATING_CKEN0_EXBCK                *((volatile  uint8_t *)(0x42782068UL))
#define bFM4_CLK_GATING_CKEN0_EXBCK               *((volatile  uint8_t *)(0x42782068UL))
#define bFM_CLK_GATING_CKEN0_GIOCK                *((volatile  uint8_t *)(0x42782070UL))
#define bFM4_CLK_GATING_CKEN0_GIOCK               *((volatile  uint8_t *)(0x42782070UL))

#define bFM_CLK_GATING_CKEN1_BTMCK0               *((volatile  uint8_t *)(0x42782200UL))
#define bFM4_CLK_GATING_CKEN1_BTMCK0              *((volatile  uint8_t *)(0x42782200UL))
#define bFM_CLK_GATING_CKEN1_BTMCK1               *((volatile  uint8_t *)(0x42782204UL))
#define bFM4_CLK_GATING_CKEN1_BTMCK1              *((volatile  uint8_t *)(0x42782204UL))
#define bFM_CLK_GATING_CKEN1_BTMCK2               *((volatile  uint8_t *)(0x42782208UL))
#define bFM4_CLK_GATING_CKEN1_BTMCK2              *((volatile  uint8_t *)(0x42782208UL))
#define bFM_CLK_GATING_CKEN1_BTMCK3               *((volatile  uint8_t *)(0x4278220CUL))
#define bFM4_CLK_GATING_CKEN1_BTMCK3              *((volatile  uint8_t *)(0x4278220CUL))
#define bFM_CLK_GATING_CKEN1_MFTCK0               *((volatile  uint8_t *)(0x42782220UL))
#define bFM4_CLK_GATING_CKEN1_MFTCK0              *((volatile  uint8_t *)(0x42782220UL))
#define bFM_CLK_GATING_CKEN1_MFTCK1               *((volatile  uint8_t *)(0x42782224UL))
#define bFM4_CLK_GATING_CKEN1_MFTCK1              *((volatile  uint8_t *)(0x42782224UL))
#define bFM_CLK_GATING_CKEN1_MFTCK2               *((volatile  uint8_t *)(0x42782228UL))
#define bFM4_CLK_GATING_CKEN1_MFTCK2              *((volatile  uint8_t *)(0x42782228UL))
#define bFM_CLK_GATING_CKEN1_MFTCK3               *((volatile  uint8_t *)(0x4278222CUL))
#define bFM4_CLK_GATING_CKEN1_MFTCK3              *((volatile  uint8_t *)(0x4278222CUL))
#define bFM_CLK_GATING_CKEN1_QDUCK0               *((volatile  uint8_t *)(0x42782240UL))
#define bFM4_CLK_GATING_CKEN1_QDUCK0              *((volatile  uint8_t *)(0x42782240UL))
#define bFM_CLK_GATING_CKEN1_QDUCK1               *((volatile  uint8_t *)(0x42782244UL))
#define bFM4_CLK_GATING_CKEN1_QDUCK1              *((volatile  uint8_t *)(0x42782244UL))
#define bFM_CLK_GATING_CKEN1_QDUCK2               *((volatile  uint8_t *)(0x42782248UL))
#define bFM4_CLK_GATING_CKEN1_QDUCK2              *((volatile  uint8_t *)(0x42782248UL))
#define bFM_CLK_GATING_CKEN1_QDUCK3               *((volatile  uint8_t *)(0x4278224CUL))
#define bFM4_CLK_GATING_CKEN1_QDUCK3              *((volatile  uint8_t *)(0x4278224CUL))

#define bFM_CLK_GATING_CKEN2_USBCK0               *((volatile  uint8_t *)(0x42782400UL))
#define bFM4_CLK_GATING_CKEN2_USBCK0              *((volatile  uint8_t *)(0x42782400UL))
#define bFM_CLK_GATING_CKEN2_USBCK1               *((volatile  uint8_t *)(0x42782404UL))
#define bFM4_CLK_GATING_CKEN2_USBCK1              *((volatile  uint8_t *)(0x42782404UL))
#define bFM_CLK_GATING_CKEN2_CANCK0               *((volatile  uint8_t *)(0x42782410UL))
#define bFM4_CLK_GATING_CKEN2_CANCK0              *((volatile  uint8_t *)(0x42782410UL))
#define bFM_CLK_GATING_CKEN2_CANCK1               *((volatile  uint8_t *)(0x42782414UL))
#define bFM4_CLK_GATING_CKEN2_CANCK1              *((volatile  uint8_t *)(0x42782414UL))
#define bFM_CLK_GATING_CKEN2_CANCK2               *((volatile  uint8_t *)(0x42782418UL))
#define bFM4_CLK_GATING_CKEN2_CANCK2              *((volatile  uint8_t *)(0x42782418UL))
#define bFM_CLK_GATING_CKEN2_SDCCK                *((volatile  uint8_t *)(0x42782420UL))
#define bFM4_CLK_GATING_CKEN2_SDCCK               *((volatile  uint8_t *)(0x42782420UL))
#define bFM_CLK_GATING_CKEN2_I2SCK0               *((volatile  uint8_t *)(0x42782440UL))
#define bFM4_CLK_GATING_CKEN2_I2SCK0              *((volatile  uint8_t *)(0x42782440UL))
#define bFM_CLK_GATING_CKEN2_I2SCK1               *((volatile  uint8_t *)(0x42782444UL))
#define bFM4_CLK_GATING_CKEN2_I2SCK1              *((volatile  uint8_t *)(0x42782444UL))
#define bFM_CLK_GATING_CKEN2_PCRCCK               *((volatile  uint8_t *)(0x42782450UL))
#define bFM4_CLK_GATING_CKEN2_PCRCCK              *((volatile  uint8_t *)(0x42782450UL))
#define bFM_CLK_GATING_CKEN2_CECCK0               *((volatile  uint8_t *)(0x42782460UL))
#define bFM4_CLK_GATING_CKEN2_CECCK0              *((volatile  uint8_t *)(0x42782460UL))
#define bFM_CLK_GATING_CKEN2_CECCK1               *((volatile  uint8_t *)(0x42782464UL))
#define bFM4_CLK_GATING_CKEN2_CECCK1              *((volatile  uint8_t *)(0x42782464UL))
#define bFM_CLK_GATING_CKEN2_HSSPICK              *((volatile  uint8_t *)(0x42782470UL))
#define bFM4_CLK_GATING_CKEN2_HSSPICK             *((volatile  uint8_t *)(0x42782470UL))

#define bFM_CLK_GATING_MRST0_MFSRST0              *((volatile  uint8_t *)(0x42782080UL))
#define bFM4_CLK_GATING_MRST0_MFSRST0             *((volatile  uint8_t *)(0x42782080UL))
#define bFM_CLK_GATING_MRST0_MFSRST1              *((volatile  uint8_t *)(0x42782084UL))
#define bFM4_CLK_GATING_MRST0_MFSRST1             *((volatile  uint8_t *)(0x42782084UL))
#define bFM_CLK_GATING_MRST0_MFSRST2              *((volatile  uint8_t *)(0x42782088UL))
#define bFM4_CLK_GATING_MRST0_MFSRST2             *((volatile  uint8_t *)(0x42782088UL))
#define bFM_CLK_GATING_MRST0_MFSRST3              *((volatile  uint8_t *)(0x4278208CUL))
#define bFM4_CLK_GATING_MRST0_MFSRST3             *((volatile  uint8_t *)(0x4278208CUL))
#define bFM_CLK_GATING_MRST0_MFSRST4              *((volatile  uint8_t *)(0x42782090UL))
#define bFM4_CLK_GATING_MRST0_MFSRST4             *((volatile  uint8_t *)(0x42782090UL))
#define bFM_CLK_GATING_MRST0_MFSRST5              *((volatile  uint8_t *)(0x42782094UL))
#define bFM4_CLK_GATING_MRST0_MFSRST5             *((volatile  uint8_t *)(0x42782094UL))
#define bFM_CLK_GATING_MRST0_MFSRST6              *((volatile  uint8_t *)(0x42782098UL))
#define bFM4_CLK_GATING_MRST0_MFSRST6             *((volatile  uint8_t *)(0x42782098UL))
#define bFM_CLK_GATING_MRST0_MFSRST7              *((volatile  uint8_t *)(0x4278209CUL))
#define bFM4_CLK_GATING_MRST0_MFSRST7             *((volatile  uint8_t *)(0x4278209CUL))
#define bFM_CLK_GATING_MRST0_MFSRST8              *((volatile  uint8_t *)(0x427820A0UL))
#define bFM4_CLK_GATING_MRST0_MFSRST8             *((volatile  uint8_t *)(0x427820A0UL))
#define bFM_CLK_GATING_MRST0_MFSRST9              *((volatile  uint8_t *)(0x427820A4UL))
#define bFM4_CLK_GATING_MRST0_MFSRST9             *((volatile  uint8_t *)(0x427820A4UL))
#define bFM_CLK_GATING_MRST0_MFSRST10             *((volatile  uint8_t *)(0x427820A8UL))
#define bFM4_CLK_GATING_MRST0_MFSRST10            *((volatile  uint8_t *)(0x427820A8UL))
#define bFM_CLK_GATING_MRST0_MFSRST11             *((volatile  uint8_t *)(0x427820ACUL))
#define bFM4_CLK_GATING_MRST0_MFSRST11            *((volatile  uint8_t *)(0x427820ACUL))
#define bFM_CLK_GATING_MRST0_MFSRST12             *((volatile  uint8_t *)(0x427820B0UL))
#define bFM4_CLK_GATING_MRST0_MFSRST12            *((volatile  uint8_t *)(0x427820B0UL))
#define bFM_CLK_GATING_MRST0_MFSRST13             *((volatile  uint8_t *)(0x427820B4UL))
#define bFM4_CLK_GATING_MRST0_MFSRST13            *((volatile  uint8_t *)(0x427820B4UL))
#define bFM_CLK_GATING_MRST0_MFSRST14             *((volatile  uint8_t *)(0x427820B8UL))
#define bFM4_CLK_GATING_MRST0_MFSRST14            *((volatile  uint8_t *)(0x427820B8UL))
#define bFM_CLK_GATING_MRST0_MFSRST15             *((volatile  uint8_t *)(0x427820BCUL))
#define bFM4_CLK_GATING_MRST0_MFSRST15            *((volatile  uint8_t *)(0x427820BCUL))
#define bFM_CLK_GATING_MRST0_ADCRST0              *((volatile  uint8_t *)(0x427820C0UL))
#define bFM4_CLK_GATING_MRST0_ADCRST0             *((volatile  uint8_t *)(0x427820C0UL))
#define bFM_CLK_GATING_MRST0_ADCRST1              *((volatile  uint8_t *)(0x427820C4UL))
#define bFM4_CLK_GATING_MRST0_ADCRST1             *((volatile  uint8_t *)(0x427820C4UL))
#define bFM_CLK_GATING_MRST0_ADCRST2              *((volatile  uint8_t *)(0x427820C8UL))
#define bFM4_CLK_GATING_MRST0_ADCRST2             *((volatile  uint8_t *)(0x427820C8UL))
#define bFM_CLK_GATING_MRST0_ADCRST3              *((volatile  uint8_t *)(0x427820CCUL))
#define bFM4_CLK_GATING_MRST0_ADCRST3             *((volatile  uint8_t *)(0x427820CCUL))
#define bFM_CLK_GATING_MRST0_DMARST               *((volatile  uint8_t *)(0x427820E0UL))
#define bFM4_CLK_GATING_MRST0_DMARST              *((volatile  uint8_t *)(0x427820E0UL))
#define bFM_CLK_GATING_MRST0_EXBRST               *((volatile  uint8_t *)(0x427820E8UL))
#define bFM4_CLK_GATING_MRST0_EXBRST              *((volatile  uint8_t *)(0x427820E8UL))

#define bFM_CLK_GATING_MRST1_BTMRST0              *((volatile  uint8_t *)(0x42782280UL))
#define bFM4_CLK_GATING_MRST1_BTMRST0             *((volatile  uint8_t *)(0x42782280UL))
#define bFM_CLK_GATING_MRST1_BTMRST1              *((volatile  uint8_t *)(0x42782284UL))
#define bFM4_CLK_GATING_MRST1_BTMRST1             *((volatile  uint8_t *)(0x42782284UL))
#define bFM_CLK_GATING_MRST1_BTMRST2              *((volatile  uint8_t *)(0x42782288UL))
#define bFM4_CLK_GATING_MRST1_BTMRST2             *((volatile  uint8_t *)(0x42782288UL))
#define bFM_CLK_GATING_MRST1_BTMRST3              *((volatile  uint8_t *)(0x4278228CUL))
#define bFM4_CLK_GATING_MRST1_BTMRST3             *((volatile  uint8_t *)(0x4278228CUL))
#define bFM_CLK_GATING_MRST1_MFTRST0              *((volatile  uint8_t *)(0x427822A0UL))
#define bFM4_CLK_GATING_MRST1_MFTRST0             *((volatile  uint8_t *)(0x427822A0UL))
#define bFM_CLK_GATING_MRST1_MFTRST1              *((volatile  uint8_t *)(0x427822A4UL))
#define bFM4_CLK_GATING_MRST1_MFTRST1             *((volatile  uint8_t *)(0x427822A4UL))
#define bFM_CLK_GATING_MRST1_MFTRST2              *((volatile  uint8_t *)(0x427822A8UL))
#define bFM4_CLK_GATING_MRST1_MFTRST2             *((volatile  uint8_t *)(0x427822A8UL))
#define bFM_CLK_GATING_MRST1_MFTRST3              *((volatile  uint8_t *)(0x427822ACUL))
#define bFM4_CLK_GATING_MRST1_MFTRST3             *((volatile  uint8_t *)(0x427822ACUL))
#define bFM_CLK_GATING_MRST1_QDURST0              *((volatile  uint8_t *)(0x427822C0UL))
#define bFM4_CLK_GATING_MRST1_QDURST0             *((volatile  uint8_t *)(0x427822C0UL))
#define bFM_CLK_GATING_MRST1_QDURST1              *((volatile  uint8_t *)(0x427822C4UL))
#define bFM4_CLK_GATING_MRST1_QDURST1             *((volatile  uint8_t *)(0x427822C4UL))
#define bFM_CLK_GATING_MRST1_QDURST2              *((volatile  uint8_t *)(0x427822C8UL))
#define bFM4_CLK_GATING_MRST1_QDURST2             *((volatile  uint8_t *)(0x427822C8UL))
#define bFM_CLK_GATING_MRST1_QDURST3              *((volatile  uint8_t *)(0x427822CCUL))
#define bFM4_CLK_GATING_MRST1_QDURST3             *((volatile  uint8_t *)(0x427822CCUL))

#define bFM_CLK_GATING_MRST2_USBRST0              *((volatile  uint8_t *)(0x42782480UL))
#define bFM4_CLK_GATING_MRST2_USBRST0             *((volatile  uint8_t *)(0x42782480UL))
#define bFM_CLK_GATING_MRST2_USBRST1              *((volatile  uint8_t *)(0x42782484UL))
#define bFM4_CLK_GATING_MRST2_USBRST1             *((volatile  uint8_t *)(0x42782484UL))
#define bFM_CLK_GATING_MRST2_CANRST0              *((volatile  uint8_t *)(0x42782490UL))
#define bFM4_CLK_GATING_MRST2_CANRST0             *((volatile  uint8_t *)(0x42782490UL))
#define bFM_CLK_GATING_MRST2_CANRST1              *((volatile  uint8_t *)(0x42782494UL))
#define bFM4_CLK_GATING_MRST2_CANRST1             *((volatile  uint8_t *)(0x42782494UL))
#define bFM_CLK_GATING_MRST2_CANRST2              *((volatile  uint8_t *)(0x42782498UL))
#define bFM4_CLK_GATING_MRST2_CANRST2             *((volatile  uint8_t *)(0x42782498UL))
#define bFM_CLK_GATING_MRST2_SDCRST               *((volatile  uint8_t *)(0x427824A0UL))
#define bFM4_CLK_GATING_MRST2_SDCRST              *((volatile  uint8_t *)(0x427824A0UL))
#define bFM_CLK_GATING_MRST2_I2SRST0              *((volatile  uint8_t *)(0x427824C0UL))
#define bFM4_CLK_GATING_MRST2_I2SRST0             *((volatile  uint8_t *)(0x427824C0UL))
#define bFM_CLK_GATING_MRST2_I2SRST1              *((volatile  uint8_t *)(0x427824C4UL))
#define bFM4_CLK_GATING_MRST2_I2SRST1             *((volatile  uint8_t *)(0x427824C4UL))
#define bFM_CLK_GATING_MRST2_PCRCRST              *((volatile  uint8_t *)(0x427824D0UL))
#define bFM4_CLK_GATING_MRST2_PCRCRST             *((volatile  uint8_t *)(0x427824D0UL))
#define bFM_CLK_GATING_MRST2_CECRST0              *((volatile  uint8_t *)(0x427824E0UL))
#define bFM4_CLK_GATING_MRST2_CECRST0             *((volatile  uint8_t *)(0x427824E0UL))
#define bFM_CLK_GATING_MRST2_CECRST1              *((volatile  uint8_t *)(0x427824E4UL))
#define bFM4_CLK_GATING_MRST2_CECRST1             *((volatile  uint8_t *)(0x427824E4UL))
#define bFM_CLK_GATING_MRST2_HSSPIRST             *((volatile  uint8_t *)(0x427824F0UL))
#define bFM4_CLK_GATING_MRST2_HSSPIRST            *((volatile  uint8_t *)(0x427824F0UL))


/*******************************************************************************
* CRC Registers CRC
*   Bitband Section
*******************************************************************************/
#define bFM_CRC_CRCCR_INIT                        *((volatile  uint8_t *)(0x42720000UL))
#define bFM4_CRC_CRCCR_INIT                       *((volatile  uint8_t *)(0x42720000UL))
#define bFM_CRC_CRCCR_CRC32                       *((volatile  uint8_t *)(0x42720004UL))
#define bFM4_CRC_CRCCR_CRC32                      *((volatile  uint8_t *)(0x42720004UL))
#define bFM_CRC_CRCCR_LTLEND                      *((volatile  uint8_t *)(0x42720008UL))
#define bFM4_CRC_CRCCR_LTLEND                     *((volatile  uint8_t *)(0x42720008UL))
#define bFM_CRC_CRCCR_LSBFST                      *((volatile  uint8_t *)(0x4272000CUL))
#define bFM4_CRC_CRCCR_LSBFST                     *((volatile  uint8_t *)(0x4272000CUL))
#define bFM_CRC_CRCCR_CRCLTE                      *((volatile  uint8_t *)(0x42720010UL))
#define bFM4_CRC_CRCCR_CRCLTE                     *((volatile  uint8_t *)(0x42720010UL))
#define bFM_CRC_CRCCR_CRCLSF                      *((volatile  uint8_t *)(0x42720014UL))
#define bFM4_CRC_CRCCR_CRCLSF                     *((volatile  uint8_t *)(0x42720014UL))
#define bFM_CRC_CRCCR_FXOR                        *((volatile  uint8_t *)(0x42720018UL))
#define bFM4_CRC_CRCCR_FXOR                       *((volatile  uint8_t *)(0x42720018UL))


/*******************************************************************************
* CRG Registers CRG
*   Bitband Section
*******************************************************************************/
#define bFM_CRG_APBC1_PSR_APBC1RST                *((volatile  uint32_t*)(0x42200310UL))
#define bFM4_CRG_APBC1_PSR_APBC1RST               *((volatile  uint32_t*)(0x42200310UL))
#define bFM_CRG_APBC1_PSR_APBC1EN                 *((volatile  uint32_t*)(0x4220031CUL))
#define bFM4_CRG_APBC1_PSR_APBC1EN                *((volatile  uint32_t*)(0x4220031CUL))

#define bFM_CRG_APBC2_PSR_APBC2RST                *((volatile  uint32_t*)(0x42200390UL))
#define bFM4_CRG_APBC2_PSR_APBC2RST               *((volatile  uint32_t*)(0x42200390UL))
#define bFM_CRG_APBC2_PSR_APBC2EN                 *((volatile  uint32_t*)(0x4220039CUL))
#define bFM4_CRG_APBC2_PSR_APBC2EN                *((volatile  uint32_t*)(0x4220039CUL))

#define bFM_CRG_CSV_CTL_MCSVE                     *((volatile  uint32_t*)(0x42200800UL))
#define bFM4_CRG_CSV_CTL_MCSVE                    *((volatile  uint32_t*)(0x42200800UL))
#define bFM_CRG_CSV_CTL_SCSVE                     *((volatile  uint32_t*)(0x42200804UL))
#define bFM4_CRG_CSV_CTL_SCSVE                    *((volatile  uint32_t*)(0x42200804UL))
#define bFM_CRG_CSV_CTL_FCSDE                     *((volatile  uint32_t*)(0x42200820UL))
#define bFM4_CRG_CSV_CTL_FCSDE                    *((volatile  uint32_t*)(0x42200820UL))
#define bFM_CRG_CSV_CTL_FCSRE                     *((volatile  uint32_t*)(0x42200824UL))
#define bFM4_CRG_CSV_CTL_FCSRE                    *((volatile  uint32_t*)(0x42200824UL))

#define bFM_CRG_CSV_STR_MCMF                      *((volatile  uint32_t*)(0x42200880UL))
#define bFM4_CRG_CSV_STR_MCMF                     *((volatile  uint32_t*)(0x42200880UL))
#define bFM_CRG_CSV_STR_SCMF                      *((volatile  uint32_t*)(0x42200884UL))
#define bFM4_CRG_CSV_STR_SCMF                     *((volatile  uint32_t*)(0x42200884UL))

#define bFM_CRG_DBWDT_CTL_DPSWBE                  *((volatile  uint32_t*)(0x42200A94UL))
#define bFM4_CRG_DBWDT_CTL_DPSWBE                 *((volatile  uint32_t*)(0x42200A94UL))
#define bFM_CRG_DBWDT_CTL_DPHWBE                  *((volatile  uint32_t*)(0x42200A9CUL))
#define bFM4_CRG_DBWDT_CTL_DPHWBE                 *((volatile  uint32_t*)(0x42200A9CUL))

#define bFM_CRG_INT_CLR_MCSC                      *((volatile  uint32_t*)(0x42200D00UL))
#define bFM4_CRG_INT_CLR_MCSC                     *((volatile  uint32_t*)(0x42200D00UL))
#define bFM_CRG_INT_CLR_SCSC                      *((volatile  uint32_t*)(0x42200D04UL))
#define bFM4_CRG_INT_CLR_SCSC                     *((volatile  uint32_t*)(0x42200D04UL))
#define bFM_CRG_INT_CLR_PCSC                      *((volatile  uint32_t*)(0x42200D08UL))
#define bFM4_CRG_INT_CLR_PCSC                     *((volatile  uint32_t*)(0x42200D08UL))
#define bFM_CRG_INT_CLR_FCSC                      *((volatile  uint32_t*)(0x42200D14UL))
#define bFM4_CRG_INT_CLR_FCSC                     *((volatile  uint32_t*)(0x42200D14UL))

#define bFM_CRG_INT_ENR_MCSE                      *((volatile  uint32_t*)(0x42200C00UL))
#define bFM4_CRG_INT_ENR_MCSE                     *((volatile  uint32_t*)(0x42200C00UL))
#define bFM_CRG_INT_ENR_SCSE                      *((volatile  uint32_t*)(0x42200C04UL))
#define bFM4_CRG_INT_ENR_SCSE                     *((volatile  uint32_t*)(0x42200C04UL))
#define bFM_CRG_INT_ENR_PCSE                      *((volatile  uint32_t*)(0x42200C08UL))
#define bFM4_CRG_INT_ENR_PCSE                     *((volatile  uint32_t*)(0x42200C08UL))
#define bFM_CRG_INT_ENR_FCSE                      *((volatile  uint32_t*)(0x42200C14UL))
#define bFM4_CRG_INT_ENR_FCSE                     *((volatile  uint32_t*)(0x42200C14UL))

#define bFM_CRG_INT_STR_MCSI                      *((volatile  uint32_t*)(0x42200C80UL))
#define bFM4_CRG_INT_STR_MCSI                     *((volatile  uint32_t*)(0x42200C80UL))
#define bFM_CRG_INT_STR_SCSI                      *((volatile  uint32_t*)(0x42200C84UL))
#define bFM4_CRG_INT_STR_SCSI                     *((volatile  uint32_t*)(0x42200C84UL))
#define bFM_CRG_INT_STR_PCSI                      *((volatile  uint32_t*)(0x42200C88UL))
#define bFM4_CRG_INT_STR_PCSI                     *((volatile  uint32_t*)(0x42200C88UL))
#define bFM_CRG_INT_STR_FCSI                      *((volatile  uint32_t*)(0x42200C94UL))
#define bFM4_CRG_INT_STR_FCSI                     *((volatile  uint32_t*)(0x42200C94UL))

#define bFM_CRG_PLLCG_CTL_PLLCGEN                 *((volatile  uint32_t*)(0x42200E80UL))
#define bFM4_CRG_PLLCG_CTL_PLLCGEN                *((volatile  uint32_t*)(0x42200E80UL))
#define bFM_CRG_PLLCG_CTL_PLLCGSTR                *((volatile  uint32_t*)(0x42200E84UL))
#define bFM4_CRG_PLLCG_CTL_PLLCGSTR               *((volatile  uint32_t*)(0x42200E84UL))

#define bFM_CRG_PSW_TMR_PINC                      *((volatile  uint32_t*)(0x42200690UL))
#define bFM4_CRG_PSW_TMR_PINC                     *((volatile  uint32_t*)(0x42200690UL))

#define bFM_CRG_RST_STR_PONR                      *((volatile  uint32_t*)(0x42200180UL))
#define bFM4_CRG_RST_STR_PONR                     *((volatile  uint32_t*)(0x42200180UL))
#define bFM_CRG_RST_STR_INITX                     *((volatile  uint32_t*)(0x42200184UL))
#define bFM4_CRG_RST_STR_INITX                    *((volatile  uint32_t*)(0x42200184UL))
#define bFM_CRG_RST_STR_SWDT                      *((volatile  uint32_t*)(0x42200190UL))
#define bFM4_CRG_RST_STR_SWDT                     *((volatile  uint32_t*)(0x42200190UL))
#define bFM_CRG_RST_STR_HWDT                      *((volatile  uint32_t*)(0x42200194UL))
#define bFM4_CRG_RST_STR_HWDT                     *((volatile  uint32_t*)(0x42200194UL))
#define bFM_CRG_RST_STR_CSVR                      *((volatile  uint32_t*)(0x42200198UL))
#define bFM4_CRG_RST_STR_CSVR                     *((volatile  uint32_t*)(0x42200198UL))
#define bFM_CRG_RST_STR_FCSR                      *((volatile  uint32_t*)(0x4220019CUL))
#define bFM4_CRG_RST_STR_FCSR                     *((volatile  uint32_t*)(0x4220019CUL))
#define bFM_CRG_RST_STR_SRST                      *((volatile  uint32_t*)(0x422001A0UL))
#define bFM4_CRG_RST_STR_SRST                     *((volatile  uint32_t*)(0x422001A0UL))

#define bFM_CRG_SCM_CTL_MOSCE                     *((volatile  uint32_t*)(0x42200004UL))
#define bFM4_CRG_SCM_CTL_MOSCE                    *((volatile  uint32_t*)(0x42200004UL))
#define bFM_CRG_SCM_CTL_SOSCE                     *((volatile  uint32_t*)(0x4220000CUL))
#define bFM4_CRG_SCM_CTL_SOSCE                    *((volatile  uint32_t*)(0x4220000CUL))
#define bFM_CRG_SCM_CTL_PLLE                      *((volatile  uint32_t*)(0x42200010UL))
#define bFM4_CRG_SCM_CTL_PLLE                     *((volatile  uint32_t*)(0x42200010UL))

#define bFM_CRG_SCM_STR_MORDY                     *((volatile  uint32_t*)(0x42200084UL))
#define bFM4_CRG_SCM_STR_MORDY                    *((volatile  uint32_t*)(0x42200084UL))
#define bFM_CRG_SCM_STR_SORDY                     *((volatile  uint32_t*)(0x4220008CUL))
#define bFM4_CRG_SCM_STR_SORDY                    *((volatile  uint32_t*)(0x4220008CUL))
#define bFM_CRG_SCM_STR_PLRDY                     *((volatile  uint32_t*)(0x42200090UL))
#define bFM4_CRG_SCM_STR_PLRDY                    *((volatile  uint32_t*)(0x42200090UL))

#define bFM_CRG_STB_CTL_DSTM                      *((volatile  uint32_t*)(0x42200108UL))
#define bFM4_CRG_STB_CTL_DSTM                     *((volatile  uint32_t*)(0x42200108UL))
#define bFM_CRG_STB_CTL_SPL                       *((volatile  uint32_t*)(0x42200110UL))
#define bFM4_CRG_STB_CTL_SPL                      *((volatile  uint32_t*)(0x42200110UL))


/*******************************************************************************
* CRTRIM Registers CRTRIM
*   Bitband Section
*******************************************************************************/

/*******************************************************************************
* DAC Registers DAC0
*   Bitband Section
*******************************************************************************/
#define bFM_DAC0_DACR_DAE                         *((volatile  uint8_t *)(0x42660000UL))
#define bFM4_DAC0_DACR_DAE                        *((volatile  uint8_t *)(0x42660000UL))
#define bFM_DAC0_DACR_DRDY                        *((volatile  uint8_t *)(0x42660004UL))
#define bFM4_DAC0_DACR_DRDY                       *((volatile  uint8_t *)(0x42660004UL))
#define bFM_DAC0_DACR_DAC10                       *((volatile  uint8_t *)(0x42660010UL))
#define bFM4_DAC0_DACR_DAC10                      *((volatile  uint8_t *)(0x42660010UL))
#define bFM_DAC0_DACR_DDAS                        *((volatile  uint8_t *)(0x42660014UL))
#define bFM4_DAC0_DACR_DDAS                       *((volatile  uint8_t *)(0x42660014UL))


/*******************************************************************************
* DAC Registers DAC1
*   Bitband Section
*******************************************************************************/
#define bFM_DAC1_DACR_DAE                         *((volatile  uint8_t *)(0x42660100UL))
#define bFM4_DAC1_DACR_DAE                        *((volatile  uint8_t *)(0x42660100UL))
#define bFM_DAC1_DACR_DRDY                        *((volatile  uint8_t *)(0x42660104UL))
#define bFM4_DAC1_DACR_DRDY                       *((volatile  uint8_t *)(0x42660104UL))
#define bFM_DAC1_DACR_DAC10                       *((volatile  uint8_t *)(0x42660110UL))
#define bFM4_DAC1_DACR_DAC10                      *((volatile  uint8_t *)(0x42660110UL))
#define bFM_DAC1_DACR_DDAS                        *((volatile  uint8_t *)(0x42660114UL))
#define bFM4_DAC1_DACR_DDAS                       *((volatile  uint8_t *)(0x42660114UL))


/*******************************************************************************
* DMAC Registers DMAC
*   Bitband Section
*******************************************************************************/
#define bFM_DMAC_DMACA0_ST                        *((volatile  uint8_t *)(0x42C00274UL))
#define bFM4_DMAC_DMACA0_ST                       *((volatile  uint8_t *)(0x42C00274UL))
#define bFM_DMAC_DMACA0_PB                        *((volatile  uint8_t *)(0x42C00278UL))
#define bFM4_DMAC_DMACA0_PB                       *((volatile  uint8_t *)(0x42C00278UL))
#define bFM_DMAC_DMACA0_EB                        *((volatile  uint8_t *)(0x42C0027CUL))
#define bFM4_DMAC_DMACA0_EB                       *((volatile  uint8_t *)(0x42C0027CUL))

#define bFM_DMAC_DMACA1_ST                        *((volatile  uint8_t *)(0x42C00474UL))
#define bFM4_DMAC_DMACA1_ST                       *((volatile  uint8_t *)(0x42C00474UL))
#define bFM_DMAC_DMACA1_PB                        *((volatile  uint8_t *)(0x42C00478UL))
#define bFM4_DMAC_DMACA1_PB                       *((volatile  uint8_t *)(0x42C00478UL))
#define bFM_DMAC_DMACA1_EB                        *((volatile  uint8_t *)(0x42C0047CUL))
#define bFM4_DMAC_DMACA1_EB                       *((volatile  uint8_t *)(0x42C0047CUL))

#define bFM_DMAC_DMACA2_ST                        *((volatile  uint8_t *)(0x42C00674UL))
#define bFM4_DMAC_DMACA2_ST                       *((volatile  uint8_t *)(0x42C00674UL))
#define bFM_DMAC_DMACA2_PB                        *((volatile  uint8_t *)(0x42C00678UL))
#define bFM4_DMAC_DMACA2_PB                       *((volatile  uint8_t *)(0x42C00678UL))
#define bFM_DMAC_DMACA2_EB                        *((volatile  uint8_t *)(0x42C0067CUL))
#define bFM4_DMAC_DMACA2_EB                       *((volatile  uint8_t *)(0x42C0067CUL))

#define bFM_DMAC_DMACA3_ST                        *((volatile  uint8_t *)(0x42C00874UL))
#define bFM4_DMAC_DMACA3_ST                       *((volatile  uint8_t *)(0x42C00874UL))
#define bFM_DMAC_DMACA3_PB                        *((volatile  uint8_t *)(0x42C00878UL))
#define bFM4_DMAC_DMACA3_PB                       *((volatile  uint8_t *)(0x42C00878UL))
#define bFM_DMAC_DMACA3_EB                        *((volatile  uint8_t *)(0x42C0087CUL))
#define bFM4_DMAC_DMACA3_EB                       *((volatile  uint8_t *)(0x42C0087CUL))

#define bFM_DMAC_DMACA4_ST                        *((volatile  uint8_t *)(0x42C00A74UL))
#define bFM4_DMAC_DMACA4_ST                       *((volatile  uint8_t *)(0x42C00A74UL))
#define bFM_DMAC_DMACA4_PB                        *((volatile  uint8_t *)(0x42C00A78UL))
#define bFM4_DMAC_DMACA4_PB                       *((volatile  uint8_t *)(0x42C00A78UL))
#define bFM_DMAC_DMACA4_EB                        *((volatile  uint8_t *)(0x42C00A7CUL))
#define bFM4_DMAC_DMACA4_EB                       *((volatile  uint8_t *)(0x42C00A7CUL))

#define bFM_DMAC_DMACA5_ST                        *((volatile  uint8_t *)(0x42C00C74UL))
#define bFM4_DMAC_DMACA5_ST                       *((volatile  uint8_t *)(0x42C00C74UL))
#define bFM_DMAC_DMACA5_PB                        *((volatile  uint8_t *)(0x42C00C78UL))
#define bFM4_DMAC_DMACA5_PB                       *((volatile  uint8_t *)(0x42C00C78UL))
#define bFM_DMAC_DMACA5_EB                        *((volatile  uint8_t *)(0x42C00C7CUL))
#define bFM4_DMAC_DMACA5_EB                       *((volatile  uint8_t *)(0x42C00C7CUL))

#define bFM_DMAC_DMACA6_ST                        *((volatile  uint8_t *)(0x42C00E74UL))
#define bFM4_DMAC_DMACA6_ST                       *((volatile  uint8_t *)(0x42C00E74UL))
#define bFM_DMAC_DMACA6_PB                        *((volatile  uint8_t *)(0x42C00E78UL))
#define bFM4_DMAC_DMACA6_PB                       *((volatile  uint8_t *)(0x42C00E78UL))
#define bFM_DMAC_DMACA6_EB                        *((volatile  uint8_t *)(0x42C00E7CUL))
#define bFM4_DMAC_DMACA6_EB                       *((volatile  uint8_t *)(0x42C00E7CUL))

#define bFM_DMAC_DMACA7_ST                        *((volatile  uint8_t *)(0x42C01074UL))
#define bFM4_DMAC_DMACA7_ST                       *((volatile  uint8_t *)(0x42C01074UL))
#define bFM_DMAC_DMACA7_PB                        *((volatile  uint8_t *)(0x42C01078UL))
#define bFM4_DMAC_DMACA7_PB                       *((volatile  uint8_t *)(0x42C01078UL))
#define bFM_DMAC_DMACA7_EB                        *((volatile  uint8_t *)(0x42C0107CUL))
#define bFM4_DMAC_DMACA7_EB                       *((volatile  uint8_t *)(0x42C0107CUL))

#define bFM_DMAC_DMACB0_EM                        *((volatile  uint8_t *)(0x42C00280UL))
#define bFM4_DMAC_DMACB0_EM                       *((volatile  uint8_t *)(0x42C00280UL))
#define bFM_DMAC_DMACB0_CI                        *((volatile  uint8_t *)(0x42C002CCUL))
#define bFM4_DMAC_DMACB0_CI                       *((volatile  uint8_t *)(0x42C002CCUL))
#define bFM_DMAC_DMACB0_EI                        *((volatile  uint8_t *)(0x42C002D0UL))
#define bFM4_DMAC_DMACB0_EI                       *((volatile  uint8_t *)(0x42C002D0UL))
#define bFM_DMAC_DMACB0_RD                        *((volatile  uint8_t *)(0x42C002D4UL))
#define bFM4_DMAC_DMACB0_RD                       *((volatile  uint8_t *)(0x42C002D4UL))
#define bFM_DMAC_DMACB0_RS                        *((volatile  uint8_t *)(0x42C002D8UL))
#define bFM4_DMAC_DMACB0_RS                       *((volatile  uint8_t *)(0x42C002D8UL))
#define bFM_DMAC_DMACB0_RC                        *((volatile  uint8_t *)(0x42C002DCUL))
#define bFM4_DMAC_DMACB0_RC                       *((volatile  uint8_t *)(0x42C002DCUL))
#define bFM_DMAC_DMACB0_FD                        *((volatile  uint8_t *)(0x42C002E0UL))
#define bFM4_DMAC_DMACB0_FD                       *((volatile  uint8_t *)(0x42C002E0UL))
#define bFM_DMAC_DMACB0_FS                        *((volatile  uint8_t *)(0x42C002E4UL))
#define bFM4_DMAC_DMACB0_FS                       *((volatile  uint8_t *)(0x42C002E4UL))

#define bFM_DMAC_DMACB1_EM                        *((volatile  uint8_t *)(0x42C00480UL))
#define bFM4_DMAC_DMACB1_EM                       *((volatile  uint8_t *)(0x42C00480UL))
#define bFM_DMAC_DMACB1_CI                        *((volatile  uint8_t *)(0x42C004CCUL))
#define bFM4_DMAC_DMACB1_CI                       *((volatile  uint8_t *)(0x42C004CCUL))
#define bFM_DMAC_DMACB1_EI                        *((volatile  uint8_t *)(0x42C004D0UL))
#define bFM4_DMAC_DMACB1_EI                       *((volatile  uint8_t *)(0x42C004D0UL))
#define bFM_DMAC_DMACB1_RD                        *((volatile  uint8_t *)(0x42C004D4UL))
#define bFM4_DMAC_DMACB1_RD                       *((volatile  uint8_t *)(0x42C004D4UL))
#define bFM_DMAC_DMACB1_RS                        *((volatile  uint8_t *)(0x42C004D8UL))
#define bFM4_DMAC_DMACB1_RS                       *((volatile  uint8_t *)(0x42C004D8UL))
#define bFM_DMAC_DMACB1_RC                        *((volatile  uint8_t *)(0x42C004DCUL))
#define bFM4_DMAC_DMACB1_RC                       *((volatile  uint8_t *)(0x42C004DCUL))
#define bFM_DMAC_DMACB1_FD                        *((volatile  uint8_t *)(0x42C004E0UL))
#define bFM4_DMAC_DMACB1_FD                       *((volatile  uint8_t *)(0x42C004E0UL))
#define bFM_DMAC_DMACB1_FS                        *((volatile  uint8_t *)(0x42C004E4UL))
#define bFM4_DMAC_DMACB1_FS                       *((volatile  uint8_t *)(0x42C004E4UL))

#define bFM_DMAC_DMACB2_EM                        *((volatile  uint8_t *)(0x42C00680UL))
#define bFM4_DMAC_DMACB2_EM                       *((volatile  uint8_t *)(0x42C00680UL))
#define bFM_DMAC_DMACB2_CI                        *((volatile  uint8_t *)(0x42C006CCUL))
#define bFM4_DMAC_DMACB2_CI                       *((volatile  uint8_t *)(0x42C006CCUL))
#define bFM_DMAC_DMACB2_EI                        *((volatile  uint8_t *)(0x42C006D0UL))
#define bFM4_DMAC_DMACB2_EI                       *((volatile  uint8_t *)(0x42C006D0UL))
#define bFM_DMAC_DMACB2_RD                        *((volatile  uint8_t *)(0x42C006D4UL))
#define bFM4_DMAC_DMACB2_RD                       *((volatile  uint8_t *)(0x42C006D4UL))
#define bFM_DMAC_DMACB2_RS                        *((volatile  uint8_t *)(0x42C006D8UL))
#define bFM4_DMAC_DMACB2_RS                       *((volatile  uint8_t *)(0x42C006D8UL))
#define bFM_DMAC_DMACB2_RC                        *((volatile  uint8_t *)(0x42C006DCUL))
#define bFM4_DMAC_DMACB2_RC                       *((volatile  uint8_t *)(0x42C006DCUL))
#define bFM_DMAC_DMACB2_FD                        *((volatile  uint8_t *)(0x42C006E0UL))
#define bFM4_DMAC_DMACB2_FD                       *((volatile  uint8_t *)(0x42C006E0UL))
#define bFM_DMAC_DMACB2_FS                        *((volatile  uint8_t *)(0x42C006E4UL))
#define bFM4_DMAC_DMACB2_FS                       *((volatile  uint8_t *)(0x42C006E4UL))

#define bFM_DMAC_DMACB3_EM                        *((volatile  uint8_t *)(0x42C00880UL))
#define bFM4_DMAC_DMACB3_EM                       *((volatile  uint8_t *)(0x42C00880UL))
#define bFM_DMAC_DMACB3_CI                        *((volatile  uint8_t *)(0x42C008CCUL))
#define bFM4_DMAC_DMACB3_CI                       *((volatile  uint8_t *)(0x42C008CCUL))
#define bFM_DMAC_DMACB3_EI                        *((volatile  uint8_t *)(0x42C008D0UL))
#define bFM4_DMAC_DMACB3_EI                       *((volatile  uint8_t *)(0x42C008D0UL))
#define bFM_DMAC_DMACB3_RD                        *((volatile  uint8_t *)(0x42C008D4UL))
#define bFM4_DMAC_DMACB3_RD                       *((volatile  uint8_t *)(0x42C008D4UL))
#define bFM_DMAC_DMACB3_RS                        *((volatile  uint8_t *)(0x42C008D8UL))
#define bFM4_DMAC_DMACB3_RS                       *((volatile  uint8_t *)(0x42C008D8UL))
#define bFM_DMAC_DMACB3_RC                        *((volatile  uint8_t *)(0x42C008DCUL))
#define bFM4_DMAC_DMACB3_RC                       *((volatile  uint8_t *)(0x42C008DCUL))
#define bFM_DMAC_DMACB3_FD                        *((volatile  uint8_t *)(0x42C008E0UL))
#define bFM4_DMAC_DMACB3_FD                       *((volatile  uint8_t *)(0x42C008E0UL))
#define bFM_DMAC_DMACB3_FS                        *((volatile  uint8_t *)(0x42C008E4UL))
#define bFM4_DMAC_DMACB3_FS                       *((volatile  uint8_t *)(0x42C008E4UL))

#define bFM_DMAC_DMACB4_EM                        *((volatile  uint8_t *)(0x42C00A80UL))
#define bFM4_DMAC_DMACB4_EM                       *((volatile  uint8_t *)(0x42C00A80UL))
#define bFM_DMAC_DMACB4_CI                        *((volatile  uint8_t *)(0x42C00ACCUL))
#define bFM4_DMAC_DMACB4_CI                       *((volatile  uint8_t *)(0x42C00ACCUL))
#define bFM_DMAC_DMACB4_EI                        *((volatile  uint8_t *)(0x42C00AD0UL))
#define bFM4_DMAC_DMACB4_EI                       *((volatile  uint8_t *)(0x42C00AD0UL))
#define bFM_DMAC_DMACB4_RD                        *((volatile  uint8_t *)(0x42C00AD4UL))
#define bFM4_DMAC_DMACB4_RD                       *((volatile  uint8_t *)(0x42C00AD4UL))
#define bFM_DMAC_DMACB4_RS                        *((volatile  uint8_t *)(0x42C00AD8UL))
#define bFM4_DMAC_DMACB4_RS                       *((volatile  uint8_t *)(0x42C00AD8UL))
#define bFM_DMAC_DMACB4_RC                        *((volatile  uint8_t *)(0x42C00ADCUL))
#define bFM4_DMAC_DMACB4_RC                       *((volatile  uint8_t *)(0x42C00ADCUL))
#define bFM_DMAC_DMACB4_FD                        *((volatile  uint8_t *)(0x42C00AE0UL))
#define bFM4_DMAC_DMACB4_FD                       *((volatile  uint8_t *)(0x42C00AE0UL))
#define bFM_DMAC_DMACB4_FS                        *((volatile  uint8_t *)(0x42C00AE4UL))
#define bFM4_DMAC_DMACB4_FS                       *((volatile  uint8_t *)(0x42C00AE4UL))

#define bFM_DMAC_DMACB5_EM                        *((volatile  uint8_t *)(0x42C00C80UL))
#define bFM4_DMAC_DMACB5_EM                       *((volatile  uint8_t *)(0x42C00C80UL))
#define bFM_DMAC_DMACB5_CI                        *((volatile  uint8_t *)(0x42C00CCCUL))
#define bFM4_DMAC_DMACB5_CI                       *((volatile  uint8_t *)(0x42C00CCCUL))
#define bFM_DMAC_DMACB5_EI                        *((volatile  uint8_t *)(0x42C00CD0UL))
#define bFM4_DMAC_DMACB5_EI                       *((volatile  uint8_t *)(0x42C00CD0UL))
#define bFM_DMAC_DMACB5_RD                        *((volatile  uint8_t *)(0x42C00CD4UL))
#define bFM4_DMAC_DMACB5_RD                       *((volatile  uint8_t *)(0x42C00CD4UL))
#define bFM_DMAC_DMACB5_RS                        *((volatile  uint8_t *)(0x42C00CD8UL))
#define bFM4_DMAC_DMACB5_RS                       *((volatile  uint8_t *)(0x42C00CD8UL))
#define bFM_DMAC_DMACB5_RC                        *((volatile  uint8_t *)(0x42C00CDCUL))
#define bFM4_DMAC_DMACB5_RC                       *((volatile  uint8_t *)(0x42C00CDCUL))
#define bFM_DMAC_DMACB5_FD                        *((volatile  uint8_t *)(0x42C00CE0UL))
#define bFM4_DMAC_DMACB5_FD                       *((volatile  uint8_t *)(0x42C00CE0UL))
#define bFM_DMAC_DMACB5_FS                        *((volatile  uint8_t *)(0x42C00CE4UL))
#define bFM4_DMAC_DMACB5_FS                       *((volatile  uint8_t *)(0x42C00CE4UL))

#define bFM_DMAC_DMACB6_EM                        *((volatile  uint8_t *)(0x42C00E80UL))
#define bFM4_DMAC_DMACB6_EM                       *((volatile  uint8_t *)(0x42C00E80UL))
#define bFM_DMAC_DMACB6_CI                        *((volatile  uint8_t *)(0x42C00ECCUL))
#define bFM4_DMAC_DMACB6_CI                       *((volatile  uint8_t *)(0x42C00ECCUL))
#define bFM_DMAC_DMACB6_EI                        *((volatile  uint8_t *)(0x42C00ED0UL))
#define bFM4_DMAC_DMACB6_EI                       *((volatile  uint8_t *)(0x42C00ED0UL))
#define bFM_DMAC_DMACB6_RD                        *((volatile  uint8_t *)(0x42C00ED4UL))
#define bFM4_DMAC_DMACB6_RD                       *((volatile  uint8_t *)(0x42C00ED4UL))
#define bFM_DMAC_DMACB6_RS                        *((volatile  uint8_t *)(0x42C00ED8UL))
#define bFM4_DMAC_DMACB6_RS                       *((volatile  uint8_t *)(0x42C00ED8UL))
#define bFM_DMAC_DMACB6_RC                        *((volatile  uint8_t *)(0x42C00EDCUL))
#define bFM4_DMAC_DMACB6_RC                       *((volatile  uint8_t *)(0x42C00EDCUL))
#define bFM_DMAC_DMACB6_FD                        *((volatile  uint8_t *)(0x42C00EE0UL))
#define bFM4_DMAC_DMACB6_FD                       *((volatile  uint8_t *)(0x42C00EE0UL))
#define bFM_DMAC_DMACB6_FS                        *((volatile  uint8_t *)(0x42C00EE4UL))
#define bFM4_DMAC_DMACB6_FS                       *((volatile  uint8_t *)(0x42C00EE4UL))

#define bFM_DMAC_DMACB7_EM                        *((volatile  uint8_t *)(0x42C01080UL))
#define bFM4_DMAC_DMACB7_EM                       *((volatile  uint8_t *)(0x42C01080UL))
#define bFM_DMAC_DMACB7_CI                        *((volatile  uint8_t *)(0x42C010CCUL))
#define bFM4_DMAC_DMACB7_CI                       *((volatile  uint8_t *)(0x42C010CCUL))
#define bFM_DMAC_DMACB7_EI                        *((volatile  uint8_t *)(0x42C010D0UL))
#define bFM4_DMAC_DMACB7_EI                       *((volatile  uint8_t *)(0x42C010D0UL))
#define bFM_DMAC_DMACB7_RD                        *((volatile  uint8_t *)(0x42C010D4UL))
#define bFM4_DMAC_DMACB7_RD                       *((volatile  uint8_t *)(0x42C010D4UL))
#define bFM_DMAC_DMACB7_RS                        *((volatile  uint8_t *)(0x42C010D8UL))
#define bFM4_DMAC_DMACB7_RS                       *((volatile  uint8_t *)(0x42C010D8UL))
#define bFM_DMAC_DMACB7_RC                        *((volatile  uint8_t *)(0x42C010DCUL))
#define bFM4_DMAC_DMACB7_RC                       *((volatile  uint8_t *)(0x42C010DCUL))
#define bFM_DMAC_DMACB7_FD                        *((volatile  uint8_t *)(0x42C010E0UL))
#define bFM4_DMAC_DMACB7_FD                       *((volatile  uint8_t *)(0x42C010E0UL))
#define bFM_DMAC_DMACB7_FS                        *((volatile  uint8_t *)(0x42C010E4UL))
#define bFM4_DMAC_DMACB7_FS                       *((volatile  uint8_t *)(0x42C010E4UL))

#define bFM_DMAC_DMACR_PR                         *((volatile  uint8_t *)(0x42C00070UL))
#define bFM4_DMAC_DMACR_PR                        *((volatile  uint8_t *)(0x42C00070UL))
#define bFM_DMAC_DMACR_DS                         *((volatile  uint8_t *)(0x42C00078UL))
#define bFM4_DMAC_DMACR_DS                        *((volatile  uint8_t *)(0x42C00078UL))
#define bFM_DMAC_DMACR_DE                         *((volatile  uint8_t *)(0x42C0007CUL))
#define bFM4_DMAC_DMACR_DE                        *((volatile  uint8_t *)(0x42C0007CUL))


/*******************************************************************************
* DS Registers DS
*   Bitband Section
*******************************************************************************/
#define bFM_DS_PMD_CTL_RTCE                       *((volatile  uint8_t *)(0x426B0000UL))
#define bFM4_DS_PMD_CTL_RTCE                      *((volatile  uint8_t *)(0x426B0000UL))

#define bFM_DS_RCK_CTL_RTCCKE                     *((volatile  uint8_t *)(0x426A2080UL))
#define bFM4_DS_RCK_CTL_RTCCKE                    *((volatile  uint8_t *)(0x426A2080UL))
#define bFM_DS_RCK_CTL_CECCKE                     *((volatile  uint8_t *)(0x426A2084UL))
#define bFM4_DS_RCK_CTL_CECCKE                    *((volatile  uint8_t *)(0x426A2084UL))

#define bFM_DS_WIER_WRTCE                         *((volatile  uint8_t *)(0x426B0180UL))
#define bFM4_DS_WIER_WRTCE                        *((volatile  uint8_t *)(0x426B0180UL))
#define bFM_DS_WIER_WLVDE                         *((volatile  uint8_t *)(0x426B0184UL))
#define bFM4_DS_WIER_WLVDE                        *((volatile  uint8_t *)(0x426B0184UL))
#define bFM_DS_WIER_WUI1E                         *((volatile  uint8_t *)(0x426B018CUL))
#define bFM4_DS_WIER_WUI1E                        *((volatile  uint8_t *)(0x426B018CUL))
#define bFM_DS_WIER_WUI2E                         *((volatile  uint8_t *)(0x426B0190UL))
#define bFM4_DS_WIER_WUI2E                        *((volatile  uint8_t *)(0x426B0190UL))
#define bFM_DS_WIER_WUI3E                         *((volatile  uint8_t *)(0x426B0194UL))
#define bFM4_DS_WIER_WUI3E                        *((volatile  uint8_t *)(0x426B0194UL))
#define bFM_DS_WIER_WUI4E                         *((volatile  uint8_t *)(0x426B0198UL))
#define bFM4_DS_WIER_WUI4E                        *((volatile  uint8_t *)(0x426B0198UL))
#define bFM_DS_WIER_WUI5E                         *((volatile  uint8_t *)(0x426B019CUL))
#define bFM4_DS_WIER_WUI5E                        *((volatile  uint8_t *)(0x426B019CUL))

#define bFM_DS_WIFSR_WRTCI                        *((volatile  uint8_t *)(0x426B0100UL))
#define bFM4_DS_WIFSR_WRTCI                       *((volatile  uint8_t *)(0x426B0100UL))
#define bFM_DS_WIFSR_WLVDI                        *((volatile  uint8_t *)(0x426B0104UL))
#define bFM4_DS_WIFSR_WLVDI                       *((volatile  uint8_t *)(0x426B0104UL))
#define bFM_DS_WIFSR_WUI0                         *((volatile  uint8_t *)(0x426B0108UL))
#define bFM4_DS_WIFSR_WUI0                        *((volatile  uint8_t *)(0x426B0108UL))
#define bFM_DS_WIFSR_WUI1                         *((volatile  uint8_t *)(0x426B010CUL))
#define bFM4_DS_WIFSR_WUI1                        *((volatile  uint8_t *)(0x426B010CUL))
#define bFM_DS_WIFSR_WUI2                         *((volatile  uint8_t *)(0x426B0110UL))
#define bFM4_DS_WIFSR_WUI2                        *((volatile  uint8_t *)(0x426B0110UL))
#define bFM_DS_WIFSR_WUI3                         *((volatile  uint8_t *)(0x426B0114UL))
#define bFM4_DS_WIFSR_WUI3                        *((volatile  uint8_t *)(0x426B0114UL))
#define bFM_DS_WIFSR_WUI4                         *((volatile  uint8_t *)(0x426B0118UL))
#define bFM4_DS_WIFSR_WUI4                        *((volatile  uint8_t *)(0x426B0118UL))
#define bFM_DS_WIFSR_WUI5                         *((volatile  uint8_t *)(0x426B011CUL))
#define bFM4_DS_WIFSR_WUI5                        *((volatile  uint8_t *)(0x426B011CUL))

#define bFM_DS_WILVR_WUI1LV                       *((volatile  uint8_t *)(0x426B0200UL))
#define bFM4_DS_WILVR_WUI1LV                      *((volatile  uint8_t *)(0x426B0200UL))
#define bFM_DS_WILVR_WUI2LV                       *((volatile  uint8_t *)(0x426B0204UL))
#define bFM4_DS_WILVR_WUI2LV                      *((volatile  uint8_t *)(0x426B0204UL))
#define bFM_DS_WILVR_WUI3LV                       *((volatile  uint8_t *)(0x426B0208UL))
#define bFM4_DS_WILVR_WUI3LV                      *((volatile  uint8_t *)(0x426B0208UL))
#define bFM_DS_WILVR_WUI4LV                       *((volatile  uint8_t *)(0x426B020CUL))
#define bFM4_DS_WILVR_WUI4LV                      *((volatile  uint8_t *)(0x426B020CUL))
#define bFM_DS_WILVR_WUI5LV                       *((volatile  uint8_t *)(0x426B0210UL))
#define bFM4_DS_WILVR_WUI5LV                      *((volatile  uint8_t *)(0x426B0210UL))

#define bFM_DS_WRFSR_WINITX                       *((volatile  uint8_t *)(0x426B0080UL))
#define bFM4_DS_WRFSR_WINITX                      *((volatile  uint8_t *)(0x426B0080UL))
#define bFM_DS_WRFSR_WLVDH                        *((volatile  uint8_t *)(0x426B0084UL))
#define bFM4_DS_WRFSR_WLVDH                       *((volatile  uint8_t *)(0x426B0084UL))


/*******************************************************************************
* DSTC Registers DSTC
*   Bitband Section
*******************************************************************************/
#define bFM_DSTC_CFG_SWINTE                       *((volatile  uint8_t *)(0x42C20120UL))
#define bFM4_DSTC_CFG_SWINTE                      *((volatile  uint8_t *)(0x42C20120UL))
#define bFM_DSTC_CFG_ERINTE                       *((volatile  uint8_t *)(0x42C20124UL))
#define bFM4_DSTC_CFG_ERINTE                      *((volatile  uint8_t *)(0x42C20124UL))
#define bFM_DSTC_CFG_RBDIS                        *((volatile  uint8_t *)(0x42C20128UL))
#define bFM4_DSTC_CFG_RBDIS                       *((volatile  uint8_t *)(0x42C20128UL))
#define bFM_DSTC_CFG_ESTE                         *((volatile  uint8_t *)(0x42C2012CUL))
#define bFM4_DSTC_CFG_ESTE                        *((volatile  uint8_t *)(0x42C2012CUL))

#define bFM_DSTC_MONERS_DER                       *((volatile  uint8_t *)(0x42C2018CUL))
#define bFM4_DSTC_MONERS_DER                      *((volatile  uint8_t *)(0x42C2018CUL))
#define bFM_DSTC_MONERS_ESTOP                     *((volatile  uint8_t *)(0x42C20190UL))
#define bFM4_DSTC_MONERS_ESTOP                    *((volatile  uint8_t *)(0x42C20190UL))
#define bFM_DSTC_MONERS_EHS                       *((volatile  uint8_t *)(0x42C20198UL))
#define bFM4_DSTC_MONERS_EHS                      *((volatile  uint8_t *)(0x42C20198UL))

#define bFM_DSTC_SWTR_SWREQ                       *((volatile  uint16_t*)(0x42C20178UL))
#define bFM4_DSTC_SWTR_SWREQ                      *((volatile  uint16_t*)(0x42C20178UL))
#define bFM_DSTC_SWTR_SWST                        *((volatile  uint16_t*)(0x42C2017CUL))
#define bFM4_DSTC_SWTR_SWST                       *((volatile  uint16_t*)(0x42C2017CUL))


/*******************************************************************************
* DT Registers DT
*   Bitband Section
*******************************************************************************/
#define bFM_DT_TIMER1CONTROL_ONESHOT              *((volatile  uint32_t*)(0x422A0100UL))
#define bFM4_DT_TIMER1CONTROL_ONESHOT             *((volatile  uint32_t*)(0x422A0100UL))
#define bFM_DT_TIMER1CONTROL_TIMERSIZE            *((volatile  uint32_t*)(0x422A0104UL))
#define bFM4_DT_TIMER1CONTROL_TIMERSIZE           *((volatile  uint32_t*)(0x422A0104UL))
#define bFM_DT_TIMER1CONTROL_INTENABLE            *((volatile  uint32_t*)(0x422A0114UL))
#define bFM4_DT_TIMER1CONTROL_INTENABLE           *((volatile  uint32_t*)(0x422A0114UL))
#define bFM_DT_TIMER1CONTROL_TIMERMODE            *((volatile  uint32_t*)(0x422A0118UL))
#define bFM4_DT_TIMER1CONTROL_TIMERMODE           *((volatile  uint32_t*)(0x422A0118UL))
#define bFM_DT_TIMER1CONTROL_TIMEREN              *((volatile  uint32_t*)(0x422A011CUL))
#define bFM4_DT_TIMER1CONTROL_TIMEREN             *((volatile  uint32_t*)(0x422A011CUL))

#define bFM_DT_TIMER1MIS_TIMER1MIS                *((volatile  uint32_t*)(0x422A0280UL))
#define bFM4_DT_TIMER1MIS_TIMER1MIS               *((volatile  uint32_t*)(0x422A0280UL))

#define bFM_DT_TIMER1RIS_TIMER1RIS                *((volatile  uint32_t*)(0x422A0200UL))
#define bFM4_DT_TIMER1RIS_TIMER1RIS               *((volatile  uint32_t*)(0x422A0200UL))

#define bFM_DT_TIMER2CONTROL_ONESHOT              *((volatile  uint32_t*)(0x422A0500UL))
#define bFM4_DT_TIMER2CONTROL_ONESHOT             *((volatile  uint32_t*)(0x422A0500UL))
#define bFM_DT_TIMER2CONTROL_TIMERSIZE            *((volatile  uint32_t*)(0x422A0504UL))
#define bFM4_DT_TIMER2CONTROL_TIMERSIZE           *((volatile  uint32_t*)(0x422A0504UL))
#define bFM_DT_TIMER2CONTROL_INTENABLE            *((volatile  uint32_t*)(0x422A0514UL))
#define bFM4_DT_TIMER2CONTROL_INTENABLE           *((volatile  uint32_t*)(0x422A0514UL))
#define bFM_DT_TIMER2CONTROL_TIMERMODE            *((volatile  uint32_t*)(0x422A0518UL))
#define bFM4_DT_TIMER2CONTROL_TIMERMODE           *((volatile  uint32_t*)(0x422A0518UL))
#define bFM_DT_TIMER2CONTROL_TIMEREN              *((volatile  uint32_t*)(0x422A051CUL))
#define bFM4_DT_TIMER2CONTROL_TIMEREN             *((volatile  uint32_t*)(0x422A051CUL))

#define bFM_DT_TIMER2MIS_TIMER2MIS                *((volatile  uint32_t*)(0x422A0680UL))
#define bFM4_DT_TIMER2MIS_TIMER2MIS               *((volatile  uint32_t*)(0x422A0680UL))

#define bFM_DT_TIMER2RIS_TIMER2RIS                *((volatile  uint32_t*)(0x422A0600UL))
#define bFM4_DT_TIMER2RIS_TIMER2RIS               *((volatile  uint32_t*)(0x422A0600UL))


/*******************************************************************************
* DUALFLASH_IF Registers DUALFLASH_IF
*   Bitband Section
*******************************************************************************/
#define bFM_DUALFLASH_IF_DFSTR_DFRDY              *((volatile  uint8_t *)(0x42008100UL))
#define bFM4_DUALFLASH_IF_DFSTR_DFRDY             *((volatile  uint8_t *)(0x42008100UL))
#define bFM_DUALFLASH_IF_DFSTR_DFHNG              *((volatile  uint8_t *)(0x42008104UL))
#define bFM4_DUALFLASH_IF_DFSTR_DFHNG             *((volatile  uint8_t *)(0x42008104UL))
#define bFM_DUALFLASH_IF_DFSTR_DFERR              *((volatile  uint8_t *)(0x42008108UL))
#define bFM4_DUALFLASH_IF_DFSTR_DFERR             *((volatile  uint8_t *)(0x42008108UL))


/*******************************************************************************
* ECC_CAPTURE Registers ECC_CAPTURE
*   Bitband Section
*******************************************************************************/

/*******************************************************************************
* ETHERNET_CONTROL Registers ETHERNET_CONTROL
*   Bitband Section
*******************************************************************************/
#define bFM_ETHERNET_CONTROL_ETH_MODE_IFMODE      *((volatile  uint8_t *)(0x42CC0000UL))
#define bFM4_ETHERNET_CONTROL_ETH_MODE_IFMODE     *((volatile  uint8_t *)(0x42CC0000UL))
#define bFM_ETHERNET_CONTROL_ETH_MODE_RST0        *((volatile  uint8_t *)(0x42CC0020UL))
#define bFM4_ETHERNET_CONTROL_ETH_MODE_RST0       *((volatile  uint8_t *)(0x42CC0020UL))
#define bFM_ETHERNET_CONTROL_ETH_MODE_RST1        *((volatile  uint8_t *)(0x42CC0024UL))
#define bFM4_ETHERNET_CONTROL_ETH_MODE_RST1       *((volatile  uint8_t *)(0x42CC0024UL))
#define bFM_ETHERNET_CONTROL_ETH_MODE_PPSSEL      *((volatile  uint8_t *)(0x42CC0070UL))
#define bFM4_ETHERNET_CONTROL_ETH_MODE_PPSSEL     *((volatile  uint8_t *)(0x42CC0070UL))


/*******************************************************************************
* ETHERNET_MAC Registers ETHERNET_MAC0
*   Bitband Section
*******************************************************************************/
#define bFM_ETHERNET_MAC0_AHBSR_AHBS              *((volatile  uint8_t *)(0x42CA0580UL))
#define bFM4_ETHERNET_MAC0_AHBSR_AHBS             *((volatile  uint8_t *)(0x42CA0580UL))

#define bFM_ETHERNET_MAC0_BMR_SWR                 *((volatile  uint8_t *)(0x42CA0000UL))
#define bFM4_ETHERNET_MAC0_BMR_SWR                *((volatile  uint8_t *)(0x42CA0000UL))
#define bFM_ETHERNET_MAC0_BMR_DA                  *((volatile  uint8_t *)(0x42CA0004UL))
#define bFM4_ETHERNET_MAC0_BMR_DA                 *((volatile  uint8_t *)(0x42CA0004UL))
#define bFM_ETHERNET_MAC0_BMR_ATDS                *((volatile  uint8_t *)(0x42CA001CUL))
#define bFM4_ETHERNET_MAC0_BMR_ATDS               *((volatile  uint8_t *)(0x42CA001CUL))
#define bFM_ETHERNET_MAC0_BMR_FB                  *((volatile  uint8_t *)(0x42CA0040UL))
#define bFM4_ETHERNET_MAC0_BMR_FB                 *((volatile  uint8_t *)(0x42CA0040UL))
#define bFM_ETHERNET_MAC0_BMR_USP                 *((volatile  uint8_t *)(0x42CA005CUL))
#define bFM4_ETHERNET_MAC0_BMR_USP                *((volatile  uint8_t *)(0x42CA005CUL))
#define bFM_ETHERNET_MAC0_BMR__8XPBL              *((volatile  uint8_t *)(0x42CA0060UL))
#define bFM4_ETHERNET_MAC0_BMR__8XPBL             *((volatile  uint8_t *)(0x42CA0060UL))
#define bFM_ETHERNET_MAC0_BMR_AAL                 *((volatile  uint8_t *)(0x42CA0064UL))
#define bFM4_ETHERNET_MAC0_BMR_AAL                *((volatile  uint8_t *)(0x42CA0064UL))
#define bFM_ETHERNET_MAC0_BMR_MB                  *((volatile  uint8_t *)(0x42CA0068UL))
#define bFM4_ETHERNET_MAC0_BMR_MB                 *((volatile  uint8_t *)(0x42CA0068UL))
#define bFM_ETHERNET_MAC0_BMR_TXPR                *((volatile  uint8_t *)(0x42CA006CUL))
#define bFM4_ETHERNET_MAC0_BMR_TXPR               *((volatile  uint8_t *)(0x42CA006CUL))

#define bFM_ETHERNET_MAC0_FCR_FCB_BPA             *((volatile  uint8_t *)(0x42C80300UL))
#define bFM4_ETHERNET_MAC0_FCR_FCB_BPA            *((volatile  uint8_t *)(0x42C80300UL))
#define bFM_ETHERNET_MAC0_FCR_TFE                 *((volatile  uint8_t *)(0x42C80304UL))
#define bFM4_ETHERNET_MAC0_FCR_TFE                *((volatile  uint8_t *)(0x42C80304UL))
#define bFM_ETHERNET_MAC0_FCR_RFE                 *((volatile  uint8_t *)(0x42C80308UL))
#define bFM4_ETHERNET_MAC0_FCR_RFE                *((volatile  uint8_t *)(0x42C80308UL))
#define bFM_ETHERNET_MAC0_FCR_UP                  *((volatile  uint8_t *)(0x42C8030CUL))
#define bFM4_ETHERNET_MAC0_FCR_UP                 *((volatile  uint8_t *)(0x42C8030CUL))
#define bFM_ETHERNET_MAC0_FCR_DZPQ                *((volatile  uint8_t *)(0x42C8031CUL))
#define bFM4_ETHERNET_MAC0_FCR_DZPQ               *((volatile  uint8_t *)(0x42C8031CUL))

#define bFM_ETHERNET_MAC0_GAR_GB                  *((volatile  uint8_t *)(0x42C80200UL))
#define bFM4_ETHERNET_MAC0_GAR_GB                 *((volatile  uint8_t *)(0x42C80200UL))
#define bFM_ETHERNET_MAC0_GAR_GW                  *((volatile  uint8_t *)(0x42C80204UL))
#define bFM4_ETHERNET_MAC0_GAR_GW                 *((volatile  uint8_t *)(0x42C80204UL))

#define bFM_ETHERNET_MAC0_IER_TIE                 *((volatile  uint8_t *)(0x42CA0380UL))
#define bFM4_ETHERNET_MAC0_IER_TIE                *((volatile  uint8_t *)(0x42CA0380UL))
#define bFM_ETHERNET_MAC0_IER_TSE                 *((volatile  uint8_t *)(0x42CA0384UL))
#define bFM4_ETHERNET_MAC0_IER_TSE                *((volatile  uint8_t *)(0x42CA0384UL))
#define bFM_ETHERNET_MAC0_IER_TUE                 *((volatile  uint8_t *)(0x42CA0388UL))
#define bFM4_ETHERNET_MAC0_IER_TUE                *((volatile  uint8_t *)(0x42CA0388UL))
#define bFM_ETHERNET_MAC0_IER_TJE                 *((volatile  uint8_t *)(0x42CA038CUL))
#define bFM4_ETHERNET_MAC0_IER_TJE                *((volatile  uint8_t *)(0x42CA038CUL))
#define bFM_ETHERNET_MAC0_IER_OVE                 *((volatile  uint8_t *)(0x42CA0390UL))
#define bFM4_ETHERNET_MAC0_IER_OVE                *((volatile  uint8_t *)(0x42CA0390UL))
#define bFM_ETHERNET_MAC0_IER_UNE                 *((volatile  uint8_t *)(0x42CA0394UL))
#define bFM4_ETHERNET_MAC0_IER_UNE                *((volatile  uint8_t *)(0x42CA0394UL))
#define bFM_ETHERNET_MAC0_IER_RIE                 *((volatile  uint8_t *)(0x42CA0398UL))
#define bFM4_ETHERNET_MAC0_IER_RIE                *((volatile  uint8_t *)(0x42CA0398UL))
#define bFM_ETHERNET_MAC0_IER_RUE                 *((volatile  uint8_t *)(0x42CA039CUL))
#define bFM4_ETHERNET_MAC0_IER_RUE                *((volatile  uint8_t *)(0x42CA039CUL))
#define bFM_ETHERNET_MAC0_IER_RSE                 *((volatile  uint8_t *)(0x42CA03A0UL))
#define bFM4_ETHERNET_MAC0_IER_RSE                *((volatile  uint8_t *)(0x42CA03A0UL))
#define bFM_ETHERNET_MAC0_IER_RWE                 *((volatile  uint8_t *)(0x42CA03A4UL))
#define bFM4_ETHERNET_MAC0_IER_RWE                *((volatile  uint8_t *)(0x42CA03A4UL))
#define bFM_ETHERNET_MAC0_IER_ETE                 *((volatile  uint8_t *)(0x42CA03A8UL))
#define bFM4_ETHERNET_MAC0_IER_ETE                *((volatile  uint8_t *)(0x42CA03A8UL))
#define bFM_ETHERNET_MAC0_IER_FBE                 *((volatile  uint8_t *)(0x42CA03B4UL))
#define bFM4_ETHERNET_MAC0_IER_FBE                *((volatile  uint8_t *)(0x42CA03B4UL))
#define bFM_ETHERNET_MAC0_IER_ERE                 *((volatile  uint8_t *)(0x42CA03B8UL))
#define bFM4_ETHERNET_MAC0_IER_ERE                *((volatile  uint8_t *)(0x42CA03B8UL))
#define bFM_ETHERNET_MAC0_IER_AIE                 *((volatile  uint8_t *)(0x42CA03BCUL))
#define bFM4_ETHERNET_MAC0_IER_AIE                *((volatile  uint8_t *)(0x42CA03BCUL))
#define bFM_ETHERNET_MAC0_IER_NIE                 *((volatile  uint8_t *)(0x42CA03C0UL))
#define bFM4_ETHERNET_MAC0_IER_NIE                *((volatile  uint8_t *)(0x42CA03C0UL))

#define bFM_ETHERNET_MAC0_IMR_RGIM                *((volatile  uint8_t *)(0x42C80780UL))
#define bFM4_ETHERNET_MAC0_IMR_RGIM               *((volatile  uint8_t *)(0x42C80780UL))
#define bFM_ETHERNET_MAC0_IMR_PIM                 *((volatile  uint8_t *)(0x42C8078CUL))
#define bFM4_ETHERNET_MAC0_IMR_PIM                *((volatile  uint8_t *)(0x42C8078CUL))
#define bFM_ETHERNET_MAC0_IMR_TSIM                *((volatile  uint8_t *)(0x42C807A4UL))
#define bFM4_ETHERNET_MAC0_IMR_TSIM               *((volatile  uint8_t *)(0x42C807A4UL))
#define bFM_ETHERNET_MAC0_IMR_LPIIM               *((volatile  uint8_t *)(0x42C807A8UL))
#define bFM4_ETHERNET_MAC0_IMR_LPIIM              *((volatile  uint8_t *)(0x42C807A8UL))

#define bFM_ETHERNET_MAC0_ISR_RGIS                *((volatile  uint8_t *)(0x42C80700UL))
#define bFM4_ETHERNET_MAC0_ISR_RGIS               *((volatile  uint8_t *)(0x42C80700UL))
#define bFM_ETHERNET_MAC0_ISR_PIS                 *((volatile  uint8_t *)(0x42C8070CUL))
#define bFM4_ETHERNET_MAC0_ISR_PIS                *((volatile  uint8_t *)(0x42C8070CUL))
#define bFM_ETHERNET_MAC0_ISR_MIS                 *((volatile  uint8_t *)(0x42C80710UL))
#define bFM4_ETHERNET_MAC0_ISR_MIS                *((volatile  uint8_t *)(0x42C80710UL))
#define bFM_ETHERNET_MAC0_ISR_RIS                 *((volatile  uint8_t *)(0x42C80714UL))
#define bFM4_ETHERNET_MAC0_ISR_RIS                *((volatile  uint8_t *)(0x42C80714UL))
#define bFM_ETHERNET_MAC0_ISR_TIS                 *((volatile  uint8_t *)(0x42C80718UL))
#define bFM4_ETHERNET_MAC0_ISR_TIS                *((volatile  uint8_t *)(0x42C80718UL))
#define bFM_ETHERNET_MAC0_ISR_COIS                *((volatile  uint8_t *)(0x42C8071CUL))
#define bFM4_ETHERNET_MAC0_ISR_COIS               *((volatile  uint8_t *)(0x42C8071CUL))
#define bFM_ETHERNET_MAC0_ISR_TSIS                *((volatile  uint8_t *)(0x42C80724UL))
#define bFM4_ETHERNET_MAC0_ISR_TSIS               *((volatile  uint8_t *)(0x42C80724UL))
#define bFM_ETHERNET_MAC0_ISR_LPIIS               *((volatile  uint8_t *)(0x42C80728UL))
#define bFM4_ETHERNET_MAC0_ISR_LPIIS              *((volatile  uint8_t *)(0x42C80728UL))

#define bFM_ETHERNET_MAC0_LPICSR_TLPIEN           *((volatile  uint8_t *)(0x42C80600UL))
#define bFM4_ETHERNET_MAC0_LPICSR_TLPIEN          *((volatile  uint8_t *)(0x42C80600UL))
#define bFM_ETHERNET_MAC0_LPICSR_TLPIEX           *((volatile  uint8_t *)(0x42C80604UL))
#define bFM4_ETHERNET_MAC0_LPICSR_TLPIEX          *((volatile  uint8_t *)(0x42C80604UL))
#define bFM_ETHERNET_MAC0_LPICSR_RLPIEN           *((volatile  uint8_t *)(0x42C80608UL))
#define bFM4_ETHERNET_MAC0_LPICSR_RLPIEN          *((volatile  uint8_t *)(0x42C80608UL))
#define bFM_ETHERNET_MAC0_LPICSR_RLPIEX           *((volatile  uint8_t *)(0x42C8060CUL))
#define bFM4_ETHERNET_MAC0_LPICSR_RLPIEX          *((volatile  uint8_t *)(0x42C8060CUL))
#define bFM_ETHERNET_MAC0_LPICSR_TLPIST           *((volatile  uint8_t *)(0x42C80620UL))
#define bFM4_ETHERNET_MAC0_LPICSR_TLPIST          *((volatile  uint8_t *)(0x42C80620UL))
#define bFM_ETHERNET_MAC0_LPICSR_RLPIST           *((volatile  uint8_t *)(0x42C80624UL))
#define bFM4_ETHERNET_MAC0_LPICSR_RLPIST          *((volatile  uint8_t *)(0x42C80624UL))
#define bFM_ETHERNET_MAC0_LPICSR_LPIEN            *((volatile  uint8_t *)(0x42C80640UL))
#define bFM4_ETHERNET_MAC0_LPICSR_LPIEN           *((volatile  uint8_t *)(0x42C80640UL))
#define bFM_ETHERNET_MAC0_LPICSR_PLS              *((volatile  uint8_t *)(0x42C80644UL))
#define bFM4_ETHERNET_MAC0_LPICSR_PLS             *((volatile  uint8_t *)(0x42C80644UL))
#define bFM_ETHERNET_MAC0_LPICSR_PLSEN            *((volatile  uint8_t *)(0x42C80648UL))
#define bFM4_ETHERNET_MAC0_LPICSR_PLSEN           *((volatile  uint8_t *)(0x42C80648UL))
#define bFM_ETHERNET_MAC0_LPICSR_LPITXA           *((volatile  uint8_t *)(0x42C8064CUL))
#define bFM4_ETHERNET_MAC0_LPICSR_LPITXA          *((volatile  uint8_t *)(0x42C8064CUL))

#define bFM_ETHERNET_MAC0_MAR0H_MO                *((volatile  uint8_t *)(0x42C8087CUL))
#define bFM4_ETHERNET_MAC0_MAR0H_MO               *((volatile  uint8_t *)(0x42C8087CUL))

#define bFM_ETHERNET_MAC0_MAR10H_SA               *((volatile  uint8_t *)(0x42C81278UL))
#define bFM4_ETHERNET_MAC0_MAR10H_SA              *((volatile  uint8_t *)(0x42C81278UL))
#define bFM_ETHERNET_MAC0_MAR10H_AE               *((volatile  uint8_t *)(0x42C8127CUL))
#define bFM4_ETHERNET_MAC0_MAR10H_AE              *((volatile  uint8_t *)(0x42C8127CUL))

#define bFM_ETHERNET_MAC0_MAR11H_SA               *((volatile  uint8_t *)(0x42C81378UL))
#define bFM4_ETHERNET_MAC0_MAR11H_SA              *((volatile  uint8_t *)(0x42C81378UL))
#define bFM_ETHERNET_MAC0_MAR11H_AE               *((volatile  uint8_t *)(0x42C8137CUL))
#define bFM4_ETHERNET_MAC0_MAR11H_AE              *((volatile  uint8_t *)(0x42C8137CUL))

#define bFM_ETHERNET_MAC0_MAR12H_SA               *((volatile  uint8_t *)(0x42C81478UL))
#define bFM4_ETHERNET_MAC0_MAR12H_SA              *((volatile  uint8_t *)(0x42C81478UL))
#define bFM_ETHERNET_MAC0_MAR12H_AE               *((volatile  uint8_t *)(0x42C8147CUL))
#define bFM4_ETHERNET_MAC0_MAR12H_AE              *((volatile  uint8_t *)(0x42C8147CUL))

#define bFM_ETHERNET_MAC0_MAR13H_SA               *((volatile  uint8_t *)(0x42C81578UL))
#define bFM4_ETHERNET_MAC0_MAR13H_SA              *((volatile  uint8_t *)(0x42C81578UL))
#define bFM_ETHERNET_MAC0_MAR13H_AE               *((volatile  uint8_t *)(0x42C8157CUL))
#define bFM4_ETHERNET_MAC0_MAR13H_AE              *((volatile  uint8_t *)(0x42C8157CUL))

#define bFM_ETHERNET_MAC0_MAR14H_SA               *((volatile  uint8_t *)(0x42C81678UL))
#define bFM4_ETHERNET_MAC0_MAR14H_SA              *((volatile  uint8_t *)(0x42C81678UL))
#define bFM_ETHERNET_MAC0_MAR14H_AE               *((volatile  uint8_t *)(0x42C8167CUL))
#define bFM4_ETHERNET_MAC0_MAR14H_AE              *((volatile  uint8_t *)(0x42C8167CUL))

#define bFM_ETHERNET_MAC0_MAR15H_SA               *((volatile  uint8_t *)(0x42C81778UL))
#define bFM4_ETHERNET_MAC0_MAR15H_SA              *((volatile  uint8_t *)(0x42C81778UL))
#define bFM_ETHERNET_MAC0_MAR15H_AE               *((volatile  uint8_t *)(0x42C8177CUL))
#define bFM4_ETHERNET_MAC0_MAR15H_AE              *((volatile  uint8_t *)(0x42C8177CUL))

#define bFM_ETHERNET_MAC0_MAR16H_SA               *((volatile  uint8_t *)(0x42C90078UL))
#define bFM4_ETHERNET_MAC0_MAR16H_SA              *((volatile  uint8_t *)(0x42C90078UL))
#define bFM_ETHERNET_MAC0_MAR16H_AE               *((volatile  uint8_t *)(0x42C9007CUL))
#define bFM4_ETHERNET_MAC0_MAR16H_AE              *((volatile  uint8_t *)(0x42C9007CUL))

#define bFM_ETHERNET_MAC0_MAR17H_SA               *((volatile  uint8_t *)(0x42C90178UL))
#define bFM4_ETHERNET_MAC0_MAR17H_SA              *((volatile  uint8_t *)(0x42C90178UL))
#define bFM_ETHERNET_MAC0_MAR17H_AE               *((volatile  uint8_t *)(0x42C9017CUL))
#define bFM4_ETHERNET_MAC0_MAR17H_AE              *((volatile  uint8_t *)(0x42C9017CUL))

#define bFM_ETHERNET_MAC0_MAR18H_SA               *((volatile  uint8_t *)(0x42C90278UL))
#define bFM4_ETHERNET_MAC0_MAR18H_SA              *((volatile  uint8_t *)(0x42C90278UL))
#define bFM_ETHERNET_MAC0_MAR18H_AE               *((volatile  uint8_t *)(0x42C9027CUL))
#define bFM4_ETHERNET_MAC0_MAR18H_AE              *((volatile  uint8_t *)(0x42C9027CUL))

#define bFM_ETHERNET_MAC0_MAR19H_SA               *((volatile  uint8_t *)(0x42C90378UL))
#define bFM4_ETHERNET_MAC0_MAR19H_SA              *((volatile  uint8_t *)(0x42C90378UL))
#define bFM_ETHERNET_MAC0_MAR19H_AE               *((volatile  uint8_t *)(0x42C9037CUL))
#define bFM4_ETHERNET_MAC0_MAR19H_AE              *((volatile  uint8_t *)(0x42C9037CUL))

#define bFM_ETHERNET_MAC0_MAR1H_SA                *((volatile  uint8_t *)(0x42C80978UL))
#define bFM4_ETHERNET_MAC0_MAR1H_SA               *((volatile  uint8_t *)(0x42C80978UL))
#define bFM_ETHERNET_MAC0_MAR1H_AE                *((volatile  uint8_t *)(0x42C8097CUL))
#define bFM4_ETHERNET_MAC0_MAR1H_AE               *((volatile  uint8_t *)(0x42C8097CUL))

#define bFM_ETHERNET_MAC0_MAR20H_SA               *((volatile  uint8_t *)(0x42C90478UL))
#define bFM4_ETHERNET_MAC0_MAR20H_SA              *((volatile  uint8_t *)(0x42C90478UL))
#define bFM_ETHERNET_MAC0_MAR20H_AE               *((volatile  uint8_t *)(0x42C9047CUL))
#define bFM4_ETHERNET_MAC0_MAR20H_AE              *((volatile  uint8_t *)(0x42C9047CUL))

#define bFM_ETHERNET_MAC0_MAR21H_SA               *((volatile  uint8_t *)(0x42C90578UL))
#define bFM4_ETHERNET_MAC0_MAR21H_SA              *((volatile  uint8_t *)(0x42C90578UL))
#define bFM_ETHERNET_MAC0_MAR21H_AE               *((volatile  uint8_t *)(0x42C9057CUL))
#define bFM4_ETHERNET_MAC0_MAR21H_AE              *((volatile  uint8_t *)(0x42C9057CUL))

#define bFM_ETHERNET_MAC0_MAR22H_SA               *((volatile  uint8_t *)(0x42C90678UL))
#define bFM4_ETHERNET_MAC0_MAR22H_SA              *((volatile  uint8_t *)(0x42C90678UL))
#define bFM_ETHERNET_MAC0_MAR22H_AE               *((volatile  uint8_t *)(0x42C9067CUL))
#define bFM4_ETHERNET_MAC0_MAR22H_AE              *((volatile  uint8_t *)(0x42C9067CUL))

#define bFM_ETHERNET_MAC0_MAR23H_SA               *((volatile  uint8_t *)(0x42C90778UL))
#define bFM4_ETHERNET_MAC0_MAR23H_SA              *((volatile  uint8_t *)(0x42C90778UL))
#define bFM_ETHERNET_MAC0_MAR23H_AE               *((volatile  uint8_t *)(0x42C9077CUL))
#define bFM4_ETHERNET_MAC0_MAR23H_AE              *((volatile  uint8_t *)(0x42C9077CUL))

#define bFM_ETHERNET_MAC0_MAR24H_SA               *((volatile  uint8_t *)(0x42C90878UL))
#define bFM4_ETHERNET_MAC0_MAR24H_SA              *((volatile  uint8_t *)(0x42C90878UL))
#define bFM_ETHERNET_MAC0_MAR24H_AE               *((volatile  uint8_t *)(0x42C9087CUL))
#define bFM4_ETHERNET_MAC0_MAR24H_AE              *((volatile  uint8_t *)(0x42C9087CUL))

#define bFM_ETHERNET_MAC0_MAR25H_SA               *((volatile  uint8_t *)(0x42C90978UL))
#define bFM4_ETHERNET_MAC0_MAR25H_SA              *((volatile  uint8_t *)(0x42C90978UL))
#define bFM_ETHERNET_MAC0_MAR25H_AE               *((volatile  uint8_t *)(0x42C9097CUL))
#define bFM4_ETHERNET_MAC0_MAR25H_AE              *((volatile  uint8_t *)(0x42C9097CUL))

#define bFM_ETHERNET_MAC0_MAR26H_SA               *((volatile  uint8_t *)(0x42C90A78UL))
#define bFM4_ETHERNET_MAC0_MAR26H_SA              *((volatile  uint8_t *)(0x42C90A78UL))
#define bFM_ETHERNET_MAC0_MAR26H_AE               *((volatile  uint8_t *)(0x42C90A7CUL))
#define bFM4_ETHERNET_MAC0_MAR26H_AE              *((volatile  uint8_t *)(0x42C90A7CUL))

#define bFM_ETHERNET_MAC0_MAR27H_SA               *((volatile  uint8_t *)(0x42C90B78UL))
#define bFM4_ETHERNET_MAC0_MAR27H_SA              *((volatile  uint8_t *)(0x42C90B78UL))
#define bFM_ETHERNET_MAC0_MAR27H_AE               *((volatile  uint8_t *)(0x42C90B7CUL))
#define bFM4_ETHERNET_MAC0_MAR27H_AE              *((volatile  uint8_t *)(0x42C90B7CUL))

#define bFM_ETHERNET_MAC0_MAR28H_SA               *((volatile  uint8_t *)(0x42C90C78UL))
#define bFM4_ETHERNET_MAC0_MAR28H_SA              *((volatile  uint8_t *)(0x42C90C78UL))
#define bFM_ETHERNET_MAC0_MAR28H_AE               *((volatile  uint8_t *)(0x42C90C7CUL))
#define bFM4_ETHERNET_MAC0_MAR28H_AE              *((volatile  uint8_t *)(0x42C90C7CUL))

#define bFM_ETHERNET_MAC0_MAR29H_SA               *((volatile  uint8_t *)(0x42C90D78UL))
#define bFM4_ETHERNET_MAC0_MAR29H_SA              *((volatile  uint8_t *)(0x42C90D78UL))
#define bFM_ETHERNET_MAC0_MAR29H_AE               *((volatile  uint8_t *)(0x42C90D7CUL))
#define bFM4_ETHERNET_MAC0_MAR29H_AE              *((volatile  uint8_t *)(0x42C90D7CUL))

#define bFM_ETHERNET_MAC0_MAR2H_SA                *((volatile  uint8_t *)(0x42C80A78UL))
#define bFM4_ETHERNET_MAC0_MAR2H_SA               *((volatile  uint8_t *)(0x42C80A78UL))
#define bFM_ETHERNET_MAC0_MAR2H_AE                *((volatile  uint8_t *)(0x42C80A7CUL))
#define bFM4_ETHERNET_MAC0_MAR2H_AE               *((volatile  uint8_t *)(0x42C80A7CUL))

#define bFM_ETHERNET_MAC0_MAR30H_SA               *((volatile  uint8_t *)(0x42C90E78UL))
#define bFM4_ETHERNET_MAC0_MAR30H_SA              *((volatile  uint8_t *)(0x42C90E78UL))
#define bFM_ETHERNET_MAC0_MAR30H_AE               *((volatile  uint8_t *)(0x42C90E7CUL))
#define bFM4_ETHERNET_MAC0_MAR30H_AE              *((volatile  uint8_t *)(0x42C90E7CUL))

#define bFM_ETHERNET_MAC0_MAR31H_SA               *((volatile  uint8_t *)(0x42C90F78UL))
#define bFM4_ETHERNET_MAC0_MAR31H_SA              *((volatile  uint8_t *)(0x42C90F78UL))
#define bFM_ETHERNET_MAC0_MAR31H_AE               *((volatile  uint8_t *)(0x42C90F7CUL))
#define bFM4_ETHERNET_MAC0_MAR31H_AE              *((volatile  uint8_t *)(0x42C90F7CUL))

#define bFM_ETHERNET_MAC0_MAR3H_SA                *((volatile  uint8_t *)(0x42C80B78UL))
#define bFM4_ETHERNET_MAC0_MAR3H_SA               *((volatile  uint8_t *)(0x42C80B78UL))
#define bFM_ETHERNET_MAC0_MAR3H_AE                *((volatile  uint8_t *)(0x42C80B7CUL))
#define bFM4_ETHERNET_MAC0_MAR3H_AE               *((volatile  uint8_t *)(0x42C80B7CUL))

#define bFM_ETHERNET_MAC0_MAR4H_SA                *((volatile  uint8_t *)(0x42C80C78UL))
#define bFM4_ETHERNET_MAC0_MAR4H_SA               *((volatile  uint8_t *)(0x42C80C78UL))
#define bFM_ETHERNET_MAC0_MAR4H_AE                *((volatile  uint8_t *)(0x42C80C7CUL))
#define bFM4_ETHERNET_MAC0_MAR4H_AE               *((volatile  uint8_t *)(0x42C80C7CUL))

#define bFM_ETHERNET_MAC0_MAR5H_SA                *((volatile  uint8_t *)(0x42C80D78UL))
#define bFM4_ETHERNET_MAC0_MAR5H_SA               *((volatile  uint8_t *)(0x42C80D78UL))
#define bFM_ETHERNET_MAC0_MAR5H_AE                *((volatile  uint8_t *)(0x42C80D7CUL))
#define bFM4_ETHERNET_MAC0_MAR5H_AE               *((volatile  uint8_t *)(0x42C80D7CUL))

#define bFM_ETHERNET_MAC0_MAR6H_SA                *((volatile  uint8_t *)(0x42C80E78UL))
#define bFM4_ETHERNET_MAC0_MAR6H_SA               *((volatile  uint8_t *)(0x42C80E78UL))
#define bFM_ETHERNET_MAC0_MAR6H_AE                *((volatile  uint8_t *)(0x42C80E7CUL))
#define bFM4_ETHERNET_MAC0_MAR6H_AE               *((volatile  uint8_t *)(0x42C80E7CUL))

#define bFM_ETHERNET_MAC0_MAR7H_SA                *((volatile  uint8_t *)(0x42C80F78UL))
#define bFM4_ETHERNET_MAC0_MAR7H_SA               *((volatile  uint8_t *)(0x42C80F78UL))
#define bFM_ETHERNET_MAC0_MAR7H_AE                *((volatile  uint8_t *)(0x42C80F7CUL))
#define bFM4_ETHERNET_MAC0_MAR7H_AE               *((volatile  uint8_t *)(0x42C80F7CUL))

#define bFM_ETHERNET_MAC0_MAR8H_SA                *((volatile  uint8_t *)(0x42C81078UL))
#define bFM4_ETHERNET_MAC0_MAR8H_SA               *((volatile  uint8_t *)(0x42C81078UL))
#define bFM_ETHERNET_MAC0_MAR8H_AE                *((volatile  uint8_t *)(0x42C8107CUL))
#define bFM4_ETHERNET_MAC0_MAR8H_AE               *((volatile  uint8_t *)(0x42C8107CUL))

#define bFM_ETHERNET_MAC0_MAR9H_SA                *((volatile  uint8_t *)(0x42C81178UL))
#define bFM4_ETHERNET_MAC0_MAR9H_SA               *((volatile  uint8_t *)(0x42C81178UL))
#define bFM_ETHERNET_MAC0_MAR9H_AE                *((volatile  uint8_t *)(0x42C8117CUL))
#define bFM4_ETHERNET_MAC0_MAR9H_AE               *((volatile  uint8_t *)(0x42C8117CUL))

#define bFM_ETHERNET_MAC0_MCR_RE                  *((volatile  uint8_t *)(0x42C80008UL))
#define bFM4_ETHERNET_MAC0_MCR_RE                 *((volatile  uint8_t *)(0x42C80008UL))
#define bFM_ETHERNET_MAC0_MCR_TE                  *((volatile  uint8_t *)(0x42C8000CUL))
#define bFM4_ETHERNET_MAC0_MCR_TE                 *((volatile  uint8_t *)(0x42C8000CUL))
#define bFM_ETHERNET_MAC0_MCR_DC                  *((volatile  uint8_t *)(0x42C80010UL))
#define bFM4_ETHERNET_MAC0_MCR_DC                 *((volatile  uint8_t *)(0x42C80010UL))
#define bFM_ETHERNET_MAC0_MCR_ACS                 *((volatile  uint8_t *)(0x42C8001CUL))
#define bFM4_ETHERNET_MAC0_MCR_ACS                *((volatile  uint8_t *)(0x42C8001CUL))
#define bFM_ETHERNET_MAC0_MCR_LUD                 *((volatile  uint8_t *)(0x42C80020UL))
#define bFM4_ETHERNET_MAC0_MCR_LUD                *((volatile  uint8_t *)(0x42C80020UL))
#define bFM_ETHERNET_MAC0_MCR_DR                  *((volatile  uint8_t *)(0x42C80024UL))
#define bFM4_ETHERNET_MAC0_MCR_DR                 *((volatile  uint8_t *)(0x42C80024UL))
#define bFM_ETHERNET_MAC0_MCR_IPC                 *((volatile  uint8_t *)(0x42C80028UL))
#define bFM4_ETHERNET_MAC0_MCR_IPC                *((volatile  uint8_t *)(0x42C80028UL))
#define bFM_ETHERNET_MAC0_MCR_DM                  *((volatile  uint8_t *)(0x42C8002CUL))
#define bFM4_ETHERNET_MAC0_MCR_DM                 *((volatile  uint8_t *)(0x42C8002CUL))
#define bFM_ETHERNET_MAC0_MCR_LM                  *((volatile  uint8_t *)(0x42C80030UL))
#define bFM4_ETHERNET_MAC0_MCR_LM                 *((volatile  uint8_t *)(0x42C80030UL))
#define bFM_ETHERNET_MAC0_MCR_DO                  *((volatile  uint8_t *)(0x42C80034UL))
#define bFM4_ETHERNET_MAC0_MCR_DO                 *((volatile  uint8_t *)(0x42C80034UL))
#define bFM_ETHERNET_MAC0_MCR_FES                 *((volatile  uint8_t *)(0x42C80038UL))
#define bFM4_ETHERNET_MAC0_MCR_FES                *((volatile  uint8_t *)(0x42C80038UL))
#define bFM_ETHERNET_MAC0_MCR_PS                  *((volatile  uint8_t *)(0x42C8003CUL))
#define bFM4_ETHERNET_MAC0_MCR_PS                 *((volatile  uint8_t *)(0x42C8003CUL))
#define bFM_ETHERNET_MAC0_MCR_DCRS                *((volatile  uint8_t *)(0x42C80040UL))
#define bFM4_ETHERNET_MAC0_MCR_DCRS               *((volatile  uint8_t *)(0x42C80040UL))
#define bFM_ETHERNET_MAC0_MCR_JE                  *((volatile  uint8_t *)(0x42C80050UL))
#define bFM4_ETHERNET_MAC0_MCR_JE                 *((volatile  uint8_t *)(0x42C80050UL))
#define bFM_ETHERNET_MAC0_MCR_BE                  *((volatile  uint8_t *)(0x42C80054UL))
#define bFM4_ETHERNET_MAC0_MCR_BE                 *((volatile  uint8_t *)(0x42C80054UL))
#define bFM_ETHERNET_MAC0_MCR_JD                  *((volatile  uint8_t *)(0x42C80058UL))
#define bFM4_ETHERNET_MAC0_MCR_JD                 *((volatile  uint8_t *)(0x42C80058UL))
#define bFM_ETHERNET_MAC0_MCR_WD                  *((volatile  uint8_t *)(0x42C8005CUL))
#define bFM4_ETHERNET_MAC0_MCR_WD                 *((volatile  uint8_t *)(0x42C8005CUL))
#define bFM_ETHERNET_MAC0_MCR_TC                  *((volatile  uint8_t *)(0x42C80060UL))
#define bFM4_ETHERNET_MAC0_MCR_TC                 *((volatile  uint8_t *)(0x42C80060UL))
#define bFM_ETHERNET_MAC0_MCR_CST                 *((volatile  uint8_t *)(0x42C80064UL))
#define bFM4_ETHERNET_MAC0_MCR_CST                *((volatile  uint8_t *)(0x42C80064UL))

#define bFM_ETHERNET_MAC0_MFBOCR_ONMFH            *((volatile  uint8_t *)(0x42CA0440UL))
#define bFM4_ETHERNET_MAC0_MFBOCR_ONMFH           *((volatile  uint8_t *)(0x42CA0440UL))
#define bFM_ETHERNET_MAC0_MFBOCR_ONMFF            *((volatile  uint8_t *)(0x42CA0470UL))
#define bFM4_ETHERNET_MAC0_MFBOCR_ONMFF           *((volatile  uint8_t *)(0x42CA0470UL))

#define bFM_ETHERNET_MAC0_MFFR_PR                 *((volatile  uint8_t *)(0x42C80080UL))
#define bFM4_ETHERNET_MAC0_MFFR_PR                *((volatile  uint8_t *)(0x42C80080UL))
#define bFM_ETHERNET_MAC0_MFFR_HUC                *((volatile  uint8_t *)(0x42C80084UL))
#define bFM4_ETHERNET_MAC0_MFFR_HUC               *((volatile  uint8_t *)(0x42C80084UL))
#define bFM_ETHERNET_MAC0_MFFR_HMC                *((volatile  uint8_t *)(0x42C80088UL))
#define bFM4_ETHERNET_MAC0_MFFR_HMC               *((volatile  uint8_t *)(0x42C80088UL))
#define bFM_ETHERNET_MAC0_MFFR_DAIF               *((volatile  uint8_t *)(0x42C8008CUL))
#define bFM4_ETHERNET_MAC0_MFFR_DAIF              *((volatile  uint8_t *)(0x42C8008CUL))
#define bFM_ETHERNET_MAC0_MFFR_PM                 *((volatile  uint8_t *)(0x42C80090UL))
#define bFM4_ETHERNET_MAC0_MFFR_PM                *((volatile  uint8_t *)(0x42C80090UL))
#define bFM_ETHERNET_MAC0_MFFR_DB                 *((volatile  uint8_t *)(0x42C80094UL))
#define bFM4_ETHERNET_MAC0_MFFR_DB                *((volatile  uint8_t *)(0x42C80094UL))
#define bFM_ETHERNET_MAC0_MFFR_SAIF               *((volatile  uint8_t *)(0x42C800A0UL))
#define bFM4_ETHERNET_MAC0_MFFR_SAIF              *((volatile  uint8_t *)(0x42C800A0UL))
#define bFM_ETHERNET_MAC0_MFFR_SAF                *((volatile  uint8_t *)(0x42C800A4UL))
#define bFM4_ETHERNET_MAC0_MFFR_SAF               *((volatile  uint8_t *)(0x42C800A4UL))
#define bFM_ETHERNET_MAC0_MFFR_HPF                *((volatile  uint8_t *)(0x42C800A8UL))
#define bFM4_ETHERNET_MAC0_MFFR_HPF               *((volatile  uint8_t *)(0x42C800A8UL))
#define bFM_ETHERNET_MAC0_MFFR_RA                 *((volatile  uint8_t *)(0x42C800FCUL))
#define bFM4_ETHERNET_MAC0_MFFR_RA                *((volatile  uint8_t *)(0x42C800FCUL))

#define bFM_ETHERNET_MAC0_OMR_SR                  *((volatile  uint8_t *)(0x42CA0304UL))
#define bFM4_ETHERNET_MAC0_OMR_SR                 *((volatile  uint8_t *)(0x42CA0304UL))
#define bFM_ETHERNET_MAC0_OMR_OSF                 *((volatile  uint8_t *)(0x42CA0308UL))
#define bFM4_ETHERNET_MAC0_OMR_OSF                *((volatile  uint8_t *)(0x42CA0308UL))
#define bFM_ETHERNET_MAC0_OMR_FUF                 *((volatile  uint8_t *)(0x42CA0318UL))
#define bFM4_ETHERNET_MAC0_OMR_FUF                *((volatile  uint8_t *)(0x42CA0318UL))
#define bFM_ETHERNET_MAC0_OMR_FEF                 *((volatile  uint8_t *)(0x42CA031CUL))
#define bFM4_ETHERNET_MAC0_OMR_FEF                *((volatile  uint8_t *)(0x42CA031CUL))
#define bFM_ETHERNET_MAC0_OMR_ST                  *((volatile  uint8_t *)(0x42CA0334UL))
#define bFM4_ETHERNET_MAC0_OMR_ST                 *((volatile  uint8_t *)(0x42CA0334UL))
#define bFM_ETHERNET_MAC0_OMR_FTF                 *((volatile  uint8_t *)(0x42CA0350UL))
#define bFM4_ETHERNET_MAC0_OMR_FTF                *((volatile  uint8_t *)(0x42CA0350UL))
#define bFM_ETHERNET_MAC0_OMR_TSF                 *((volatile  uint8_t *)(0x42CA0354UL))
#define bFM4_ETHERNET_MAC0_OMR_TSF                *((volatile  uint8_t *)(0x42CA0354UL))
#define bFM_ETHERNET_MAC0_OMR_DFF                 *((volatile  uint8_t *)(0x42CA0360UL))
#define bFM4_ETHERNET_MAC0_OMR_DFF                *((volatile  uint8_t *)(0x42CA0360UL))
#define bFM_ETHERNET_MAC0_OMR_RSF                 *((volatile  uint8_t *)(0x42CA0364UL))
#define bFM4_ETHERNET_MAC0_OMR_RSF                *((volatile  uint8_t *)(0x42CA0364UL))
#define bFM_ETHERNET_MAC0_OMR_DT                  *((volatile  uint8_t *)(0x42CA0368UL))
#define bFM4_ETHERNET_MAC0_OMR_DT                 *((volatile  uint8_t *)(0x42CA0368UL))

#define bFM_ETHERNET_MAC0_PMTR_PD                 *((volatile  uint8_t *)(0x42C80580UL))
#define bFM4_ETHERNET_MAC0_PMTR_PD                *((volatile  uint8_t *)(0x42C80580UL))
#define bFM_ETHERNET_MAC0_PMTR_MPE                *((volatile  uint8_t *)(0x42C80584UL))
#define bFM4_ETHERNET_MAC0_PMTR_MPE               *((volatile  uint8_t *)(0x42C80584UL))
#define bFM_ETHERNET_MAC0_PMTR_WFE                *((volatile  uint8_t *)(0x42C80588UL))
#define bFM4_ETHERNET_MAC0_PMTR_WFE               *((volatile  uint8_t *)(0x42C80588UL))
#define bFM_ETHERNET_MAC0_PMTR_MPR                *((volatile  uint8_t *)(0x42C80594UL))
#define bFM4_ETHERNET_MAC0_PMTR_MPR               *((volatile  uint8_t *)(0x42C80594UL))
#define bFM_ETHERNET_MAC0_PMTR_WPR                *((volatile  uint8_t *)(0x42C80598UL))
#define bFM4_ETHERNET_MAC0_PMTR_WPR               *((volatile  uint8_t *)(0x42C80598UL))
#define bFM_ETHERNET_MAC0_PMTR_GU                 *((volatile  uint8_t *)(0x42C805A4UL))
#define bFM4_ETHERNET_MAC0_PMTR_GU                *((volatile  uint8_t *)(0x42C805A4UL))
#define bFM_ETHERNET_MAC0_PMTR_RWFFRPR            *((volatile  uint8_t *)(0x42C805FCUL))
#define bFM4_ETHERNET_MAC0_PMTR_RWFFRPR           *((volatile  uint8_t *)(0x42C805FCUL))

#define bFM_ETHERNET_MAC0_RGSR_LM                 *((volatile  uint8_t *)(0x42C81B00UL))
#define bFM4_ETHERNET_MAC0_RGSR_LM                *((volatile  uint8_t *)(0x42C81B00UL))
#define bFM_ETHERNET_MAC0_RGSR_LS                 *((volatile  uint8_t *)(0x42C81B0CUL))
#define bFM4_ETHERNET_MAC0_RGSR_LS                *((volatile  uint8_t *)(0x42C81B0CUL))

#define bFM_ETHERNET_MAC0_SR_TI                   *((volatile  uint8_t *)(0x42CA0280UL))
#define bFM4_ETHERNET_MAC0_SR_TI                  *((volatile  uint8_t *)(0x42CA0280UL))
#define bFM_ETHERNET_MAC0_SR_TPS                  *((volatile  uint8_t *)(0x42CA0284UL))
#define bFM4_ETHERNET_MAC0_SR_TPS                 *((volatile  uint8_t *)(0x42CA0284UL))
#define bFM_ETHERNET_MAC0_SR_TU                   *((volatile  uint8_t *)(0x42CA0288UL))
#define bFM4_ETHERNET_MAC0_SR_TU                  *((volatile  uint8_t *)(0x42CA0288UL))
#define bFM_ETHERNET_MAC0_SR_TJT                  *((volatile  uint8_t *)(0x42CA028CUL))
#define bFM4_ETHERNET_MAC0_SR_TJT                 *((volatile  uint8_t *)(0x42CA028CUL))
#define bFM_ETHERNET_MAC0_SR_OVF                  *((volatile  uint8_t *)(0x42CA0290UL))
#define bFM4_ETHERNET_MAC0_SR_OVF                 *((volatile  uint8_t *)(0x42CA0290UL))
#define bFM_ETHERNET_MAC0_SR_UNF                  *((volatile  uint8_t *)(0x42CA0294UL))
#define bFM4_ETHERNET_MAC0_SR_UNF                 *((volatile  uint8_t *)(0x42CA0294UL))
#define bFM_ETHERNET_MAC0_SR_RI                   *((volatile  uint8_t *)(0x42CA0298UL))
#define bFM4_ETHERNET_MAC0_SR_RI                  *((volatile  uint8_t *)(0x42CA0298UL))
#define bFM_ETHERNET_MAC0_SR_RU                   *((volatile  uint8_t *)(0x42CA029CUL))
#define bFM4_ETHERNET_MAC0_SR_RU                  *((volatile  uint8_t *)(0x42CA029CUL))
#define bFM_ETHERNET_MAC0_SR_RPS                  *((volatile  uint8_t *)(0x42CA02A0UL))
#define bFM4_ETHERNET_MAC0_SR_RPS                 *((volatile  uint8_t *)(0x42CA02A0UL))
#define bFM_ETHERNET_MAC0_SR_RWT                  *((volatile  uint8_t *)(0x42CA02A4UL))
#define bFM4_ETHERNET_MAC0_SR_RWT                 *((volatile  uint8_t *)(0x42CA02A4UL))
#define bFM_ETHERNET_MAC0_SR_ETI                  *((volatile  uint8_t *)(0x42CA02A8UL))
#define bFM4_ETHERNET_MAC0_SR_ETI                 *((volatile  uint8_t *)(0x42CA02A8UL))
#define bFM_ETHERNET_MAC0_SR_FBI                  *((volatile  uint8_t *)(0x42CA02B4UL))
#define bFM4_ETHERNET_MAC0_SR_FBI                 *((volatile  uint8_t *)(0x42CA02B4UL))
#define bFM_ETHERNET_MAC0_SR_ERI                  *((volatile  uint8_t *)(0x42CA02B8UL))
#define bFM4_ETHERNET_MAC0_SR_ERI                 *((volatile  uint8_t *)(0x42CA02B8UL))
#define bFM_ETHERNET_MAC0_SR_AIS                  *((volatile  uint8_t *)(0x42CA02BCUL))
#define bFM4_ETHERNET_MAC0_SR_AIS                 *((volatile  uint8_t *)(0x42CA02BCUL))
#define bFM_ETHERNET_MAC0_SR_NIS                  *((volatile  uint8_t *)(0x42CA02C0UL))
#define bFM4_ETHERNET_MAC0_SR_NIS                 *((volatile  uint8_t *)(0x42CA02C0UL))
#define bFM_ETHERNET_MAC0_SR_GLI                  *((volatile  uint8_t *)(0x42CA02E8UL))
#define bFM4_ETHERNET_MAC0_SR_GLI                 *((volatile  uint8_t *)(0x42CA02E8UL))
#define bFM_ETHERNET_MAC0_SR_GMI                  *((volatile  uint8_t *)(0x42CA02ECUL))
#define bFM4_ETHERNET_MAC0_SR_GMI                 *((volatile  uint8_t *)(0x42CA02ECUL))
#define bFM_ETHERNET_MAC0_SR_GPI                  *((volatile  uint8_t *)(0x42CA02F0UL))
#define bFM4_ETHERNET_MAC0_SR_GPI                 *((volatile  uint8_t *)(0x42CA02F0UL))
#define bFM_ETHERNET_MAC0_SR_TTI                  *((volatile  uint8_t *)(0x42CA02F4UL))
#define bFM4_ETHERNET_MAC0_SR_TTI                 *((volatile  uint8_t *)(0x42CA02F4UL))
#define bFM_ETHERNET_MAC0_SR_GLPII                *((volatile  uint8_t *)(0x42CA02F8UL))
#define bFM4_ETHERNET_MAC0_SR_GLPII               *((volatile  uint8_t *)(0x42CA02F8UL))

#define bFM_ETHERNET_MAC0_STNUR_ADDSUB            *((volatile  uint8_t *)(0x42C8E2FCUL))
#define bFM4_ETHERNET_MAC0_STNUR_ADDSUB           *((volatile  uint8_t *)(0x42C8E2FCUL))

#define bFM_ETHERNET_MAC0_TSCR_TSE                *((volatile  uint8_t *)(0x42C8E000UL))
#define bFM4_ETHERNET_MAC0_TSCR_TSE               *((volatile  uint8_t *)(0x42C8E000UL))
#define bFM_ETHERNET_MAC0_TSCR_TFCU               *((volatile  uint8_t *)(0x42C8E004UL))
#define bFM4_ETHERNET_MAC0_TSCR_TFCU              *((volatile  uint8_t *)(0x42C8E004UL))
#define bFM_ETHERNET_MAC0_TSCR_TSI                *((volatile  uint8_t *)(0x42C8E008UL))
#define bFM4_ETHERNET_MAC0_TSCR_TSI               *((volatile  uint8_t *)(0x42C8E008UL))
#define bFM_ETHERNET_MAC0_TSCR_TSU                *((volatile  uint8_t *)(0x42C8E00CUL))
#define bFM4_ETHERNET_MAC0_TSCR_TSU               *((volatile  uint8_t *)(0x42C8E00CUL))
#define bFM_ETHERNET_MAC0_TSCR_TITE               *((volatile  uint8_t *)(0x42C8E010UL))
#define bFM4_ETHERNET_MAC0_TSCR_TITE              *((volatile  uint8_t *)(0x42C8E010UL))
#define bFM_ETHERNET_MAC0_TSCR_TARU               *((volatile  uint8_t *)(0x42C8E014UL))
#define bFM4_ETHERNET_MAC0_TSCR_TARU              *((volatile  uint8_t *)(0x42C8E014UL))
#define bFM_ETHERNET_MAC0_TSCR_TSEA               *((volatile  uint8_t *)(0x42C8E020UL))
#define bFM4_ETHERNET_MAC0_TSCR_TSEA              *((volatile  uint8_t *)(0x42C8E020UL))
#define bFM_ETHERNET_MAC0_TSCR_TSDB               *((volatile  uint8_t *)(0x42C8E024UL))
#define bFM4_ETHERNET_MAC0_TSCR_TSDB              *((volatile  uint8_t *)(0x42C8E024UL))
#define bFM_ETHERNET_MAC0_TSCR_TSV2E              *((volatile  uint8_t *)(0x42C8E028UL))
#define bFM4_ETHERNET_MAC0_TSCR_TSV2E             *((volatile  uint8_t *)(0x42C8E028UL))
#define bFM_ETHERNET_MAC0_TSCR_TETSP              *((volatile  uint8_t *)(0x42C8E02CUL))
#define bFM4_ETHERNET_MAC0_TSCR_TETSP             *((volatile  uint8_t *)(0x42C8E02CUL))
#define bFM_ETHERNET_MAC0_TSCR_TSIP6E             *((volatile  uint8_t *)(0x42C8E030UL))
#define bFM4_ETHERNET_MAC0_TSCR_TSIP6E            *((volatile  uint8_t *)(0x42C8E030UL))
#define bFM_ETHERNET_MAC0_TSCR_TSIP4E             *((volatile  uint8_t *)(0x42C8E034UL))
#define bFM4_ETHERNET_MAC0_TSCR_TSIP4E            *((volatile  uint8_t *)(0x42C8E034UL))
#define bFM_ETHERNET_MAC0_TSCR_TETSEM             *((volatile  uint8_t *)(0x42C8E038UL))
#define bFM4_ETHERNET_MAC0_TSCR_TETSEM            *((volatile  uint8_t *)(0x42C8E038UL))
#define bFM_ETHERNET_MAC0_TSCR_TSMRM              *((volatile  uint8_t *)(0x42C8E03CUL))
#define bFM4_ETHERNET_MAC0_TSCR_TSMRM             *((volatile  uint8_t *)(0x42C8E03CUL))
#define bFM_ETHERNET_MAC0_TSCR_TSENMF             *((volatile  uint8_t *)(0x42C8E048UL))
#define bFM4_ETHERNET_MAC0_TSCR_TSENMF            *((volatile  uint8_t *)(0x42C8E048UL))
#define bFM_ETHERNET_MAC0_TSCR_ATSFC              *((volatile  uint8_t *)(0x42C8E060UL))
#define bFM4_ETHERNET_MAC0_TSCR_ATSFC             *((volatile  uint8_t *)(0x42C8E060UL))

#define bFM_ETHERNET_MAC0_TSR_TSSOVF              *((volatile  uint8_t *)(0x42C8E500UL))
#define bFM4_ETHERNET_MAC0_TSR_TSSOVF             *((volatile  uint8_t *)(0x42C8E500UL))
#define bFM_ETHERNET_MAC0_TSR_TSTART              *((volatile  uint8_t *)(0x42C8E504UL))
#define bFM4_ETHERNET_MAC0_TSR_TSTART             *((volatile  uint8_t *)(0x42C8E504UL))
#define bFM_ETHERNET_MAC0_TSR_ATSTS               *((volatile  uint8_t *)(0x42C8E508UL))
#define bFM4_ETHERNET_MAC0_TSR_ATSTS              *((volatile  uint8_t *)(0x42C8E508UL))
#define bFM_ETHERNET_MAC0_TSR_TRGTER              *((volatile  uint8_t *)(0x42C8E50CUL))
#define bFM4_ETHERNET_MAC0_TSR_TRGTER             *((volatile  uint8_t *)(0x42C8E50CUL))
#define bFM_ETHERNET_MAC0_TSR_ATSSTM              *((volatile  uint8_t *)(0x42C8E560UL))
#define bFM4_ETHERNET_MAC0_TSR_ATSSTM             *((volatile  uint8_t *)(0x42C8E560UL))

#define bFM_ETHERNET_MAC0_VTR_ETV                 *((volatile  uint8_t *)(0x42C803C0UL))
#define bFM4_ETHERNET_MAC0_VTR_ETV                *((volatile  uint8_t *)(0x42C803C0UL))


/*******************************************************************************
* EXTI Registers EXTI
*   Bitband Section
*******************************************************************************/
#define bFM_EXTI_EICL_ECL0                        *((volatile  uint8_t *)(0x42600100UL))
#define bFM4_EXTI_EICL_ECL0                       *((volatile  uint8_t *)(0x42600100UL))
#define bFM_EXTI_EICL_ECL1                        *((volatile  uint8_t *)(0x42600104UL))
#define bFM4_EXTI_EICL_ECL1                       *((volatile  uint8_t *)(0x42600104UL))
#define bFM_EXTI_EICL_ECL2                        *((volatile  uint8_t *)(0x42600108UL))
#define bFM4_EXTI_EICL_ECL2                       *((volatile  uint8_t *)(0x42600108UL))
#define bFM_EXTI_EICL_ECL3                        *((volatile  uint8_t *)(0x4260010CUL))
#define bFM4_EXTI_EICL_ECL3                       *((volatile  uint8_t *)(0x4260010CUL))
#define bFM_EXTI_EICL_ECL4                        *((volatile  uint8_t *)(0x42600110UL))
#define bFM4_EXTI_EICL_ECL4                       *((volatile  uint8_t *)(0x42600110UL))
#define bFM_EXTI_EICL_ECL5                        *((volatile  uint8_t *)(0x42600114UL))
#define bFM4_EXTI_EICL_ECL5                       *((volatile  uint8_t *)(0x42600114UL))
#define bFM_EXTI_EICL_ECL6                        *((volatile  uint8_t *)(0x42600118UL))
#define bFM4_EXTI_EICL_ECL6                       *((volatile  uint8_t *)(0x42600118UL))
#define bFM_EXTI_EICL_ECL7                        *((volatile  uint8_t *)(0x4260011CUL))
#define bFM4_EXTI_EICL_ECL7                       *((volatile  uint8_t *)(0x4260011CUL))
#define bFM_EXTI_EICL_ECL8                        *((volatile  uint8_t *)(0x42600120UL))
#define bFM4_EXTI_EICL_ECL8                       *((volatile  uint8_t *)(0x42600120UL))
#define bFM_EXTI_EICL_ECL9                        *((volatile  uint8_t *)(0x42600124UL))
#define bFM4_EXTI_EICL_ECL9                       *((volatile  uint8_t *)(0x42600124UL))
#define bFM_EXTI_EICL_ECL10                       *((volatile  uint8_t *)(0x42600128UL))
#define bFM4_EXTI_EICL_ECL10                      *((volatile  uint8_t *)(0x42600128UL))
#define bFM_EXTI_EICL_ECL11                       *((volatile  uint8_t *)(0x4260012CUL))
#define bFM4_EXTI_EICL_ECL11                      *((volatile  uint8_t *)(0x4260012CUL))
#define bFM_EXTI_EICL_ECL12                       *((volatile  uint8_t *)(0x42600130UL))
#define bFM4_EXTI_EICL_ECL12                      *((volatile  uint8_t *)(0x42600130UL))
#define bFM_EXTI_EICL_ECL13                       *((volatile  uint8_t *)(0x42600134UL))
#define bFM4_EXTI_EICL_ECL13                      *((volatile  uint8_t *)(0x42600134UL))
#define bFM_EXTI_EICL_ECL14                       *((volatile  uint8_t *)(0x42600138UL))
#define bFM4_EXTI_EICL_ECL14                      *((volatile  uint8_t *)(0x42600138UL))
#define bFM_EXTI_EICL_ECL15                       *((volatile  uint8_t *)(0x4260013CUL))
#define bFM4_EXTI_EICL_ECL15                      *((volatile  uint8_t *)(0x4260013CUL))
#define bFM_EXTI_EICL_ECL16                       *((volatile  uint8_t *)(0x42600140UL))
#define bFM4_EXTI_EICL_ECL16                      *((volatile  uint8_t *)(0x42600140UL))
#define bFM_EXTI_EICL_ECL17                       *((volatile  uint8_t *)(0x42600144UL))
#define bFM4_EXTI_EICL_ECL17                      *((volatile  uint8_t *)(0x42600144UL))
#define bFM_EXTI_EICL_ECL18                       *((volatile  uint8_t *)(0x42600148UL))
#define bFM4_EXTI_EICL_ECL18                      *((volatile  uint8_t *)(0x42600148UL))
#define bFM_EXTI_EICL_ECL19                       *((volatile  uint8_t *)(0x4260014CUL))
#define bFM4_EXTI_EICL_ECL19                      *((volatile  uint8_t *)(0x4260014CUL))
#define bFM_EXTI_EICL_ECL20                       *((volatile  uint8_t *)(0x42600150UL))
#define bFM4_EXTI_EICL_ECL20                      *((volatile  uint8_t *)(0x42600150UL))
#define bFM_EXTI_EICL_ECL21                       *((volatile  uint8_t *)(0x42600154UL))
#define bFM4_EXTI_EICL_ECL21                      *((volatile  uint8_t *)(0x42600154UL))
#define bFM_EXTI_EICL_ECL22                       *((volatile  uint8_t *)(0x42600158UL))
#define bFM4_EXTI_EICL_ECL22                      *((volatile  uint8_t *)(0x42600158UL))
#define bFM_EXTI_EICL_ECL23                       *((volatile  uint8_t *)(0x4260015CUL))
#define bFM4_EXTI_EICL_ECL23                      *((volatile  uint8_t *)(0x4260015CUL))
#define bFM_EXTI_EICL_ECL24                       *((volatile  uint8_t *)(0x42600160UL))
#define bFM4_EXTI_EICL_ECL24                      *((volatile  uint8_t *)(0x42600160UL))
#define bFM_EXTI_EICL_ECL25                       *((volatile  uint8_t *)(0x42600164UL))
#define bFM4_EXTI_EICL_ECL25                      *((volatile  uint8_t *)(0x42600164UL))
#define bFM_EXTI_EICL_ECL26                       *((volatile  uint8_t *)(0x42600168UL))
#define bFM4_EXTI_EICL_ECL26                      *((volatile  uint8_t *)(0x42600168UL))
#define bFM_EXTI_EICL_ECL27                       *((volatile  uint8_t *)(0x4260016CUL))
#define bFM4_EXTI_EICL_ECL27                      *((volatile  uint8_t *)(0x4260016CUL))
#define bFM_EXTI_EICL_ECL28                       *((volatile  uint8_t *)(0x42600170UL))
#define bFM4_EXTI_EICL_ECL28                      *((volatile  uint8_t *)(0x42600170UL))
#define bFM_EXTI_EICL_ECL29                       *((volatile  uint8_t *)(0x42600174UL))
#define bFM4_EXTI_EICL_ECL29                      *((volatile  uint8_t *)(0x42600174UL))
#define bFM_EXTI_EICL_ECL30                       *((volatile  uint8_t *)(0x42600178UL))
#define bFM4_EXTI_EICL_ECL30                      *((volatile  uint8_t *)(0x42600178UL))
#define bFM_EXTI_EICL_ECL31                       *((volatile  uint8_t *)(0x4260017CUL))
#define bFM4_EXTI_EICL_ECL31                      *((volatile  uint8_t *)(0x4260017CUL))

#define bFM_EXTI_EIRR_ER0                         *((volatile  uint8_t *)(0x42600080UL))
#define bFM4_EXTI_EIRR_ER0                        *((volatile  uint8_t *)(0x42600080UL))
#define bFM_EXTI_EIRR_ER1                         *((volatile  uint8_t *)(0x42600084UL))
#define bFM4_EXTI_EIRR_ER1                        *((volatile  uint8_t *)(0x42600084UL))
#define bFM_EXTI_EIRR_ER2                         *((volatile  uint8_t *)(0x42600088UL))
#define bFM4_EXTI_EIRR_ER2                        *((volatile  uint8_t *)(0x42600088UL))
#define bFM_EXTI_EIRR_ER3                         *((volatile  uint8_t *)(0x4260008CUL))
#define bFM4_EXTI_EIRR_ER3                        *((volatile  uint8_t *)(0x4260008CUL))
#define bFM_EXTI_EIRR_ER4                         *((volatile  uint8_t *)(0x42600090UL))
#define bFM4_EXTI_EIRR_ER4                        *((volatile  uint8_t *)(0x42600090UL))
#define bFM_EXTI_EIRR_ER5                         *((volatile  uint8_t *)(0x42600094UL))
#define bFM4_EXTI_EIRR_ER5                        *((volatile  uint8_t *)(0x42600094UL))
#define bFM_EXTI_EIRR_ER6                         *((volatile  uint8_t *)(0x42600098UL))
#define bFM4_EXTI_EIRR_ER6                        *((volatile  uint8_t *)(0x42600098UL))
#define bFM_EXTI_EIRR_ER7                         *((volatile  uint8_t *)(0x4260009CUL))
#define bFM4_EXTI_EIRR_ER7                        *((volatile  uint8_t *)(0x4260009CUL))
#define bFM_EXTI_EIRR_ER8                         *((volatile  uint8_t *)(0x426000A0UL))
#define bFM4_EXTI_EIRR_ER8                        *((volatile  uint8_t *)(0x426000A0UL))
#define bFM_EXTI_EIRR_ER9                         *((volatile  uint8_t *)(0x426000A4UL))
#define bFM4_EXTI_EIRR_ER9                        *((volatile  uint8_t *)(0x426000A4UL))
#define bFM_EXTI_EIRR_ER10                        *((volatile  uint8_t *)(0x426000A8UL))
#define bFM4_EXTI_EIRR_ER10                       *((volatile  uint8_t *)(0x426000A8UL))
#define bFM_EXTI_EIRR_ER11                        *((volatile  uint8_t *)(0x426000ACUL))
#define bFM4_EXTI_EIRR_ER11                       *((volatile  uint8_t *)(0x426000ACUL))
#define bFM_EXTI_EIRR_ER12                        *((volatile  uint8_t *)(0x426000B0UL))
#define bFM4_EXTI_EIRR_ER12                       *((volatile  uint8_t *)(0x426000B0UL))
#define bFM_EXTI_EIRR_ER13                        *((volatile  uint8_t *)(0x426000B4UL))
#define bFM4_EXTI_EIRR_ER13                       *((volatile  uint8_t *)(0x426000B4UL))
#define bFM_EXTI_EIRR_ER14                        *((volatile  uint8_t *)(0x426000B8UL))
#define bFM4_EXTI_EIRR_ER14                       *((volatile  uint8_t *)(0x426000B8UL))
#define bFM_EXTI_EIRR_ER15                        *((volatile  uint8_t *)(0x426000BCUL))
#define bFM4_EXTI_EIRR_ER15                       *((volatile  uint8_t *)(0x426000BCUL))
#define bFM_EXTI_EIRR_ER16                        *((volatile  uint8_t *)(0x426000C0UL))
#define bFM4_EXTI_EIRR_ER16                       *((volatile  uint8_t *)(0x426000C0UL))
#define bFM_EXTI_EIRR_ER17                        *((volatile  uint8_t *)(0x426000C4UL))
#define bFM4_EXTI_EIRR_ER17                       *((volatile  uint8_t *)(0x426000C4UL))
#define bFM_EXTI_EIRR_ER18                        *((volatile  uint8_t *)(0x426000C8UL))
#define bFM4_EXTI_EIRR_ER18                       *((volatile  uint8_t *)(0x426000C8UL))
#define bFM_EXTI_EIRR_ER19                        *((volatile  uint8_t *)(0x426000CCUL))
#define bFM4_EXTI_EIRR_ER19                       *((volatile  uint8_t *)(0x426000CCUL))
#define bFM_EXTI_EIRR_ER20                        *((volatile  uint8_t *)(0x426000D0UL))
#define bFM4_EXTI_EIRR_ER20                       *((volatile  uint8_t *)(0x426000D0UL))
#define bFM_EXTI_EIRR_ER21                        *((volatile  uint8_t *)(0x426000D4UL))
#define bFM4_EXTI_EIRR_ER21                       *((volatile  uint8_t *)(0x426000D4UL))
#define bFM_EXTI_EIRR_ER22                        *((volatile  uint8_t *)(0x426000D8UL))
#define bFM4_EXTI_EIRR_ER22                       *((volatile  uint8_t *)(0x426000D8UL))
#define bFM_EXTI_EIRR_ER23                        *((volatile  uint8_t *)(0x426000DCUL))
#define bFM4_EXTI_EIRR_ER23                       *((volatile  uint8_t *)(0x426000DCUL))
#define bFM_EXTI_EIRR_ER24                        *((volatile  uint8_t *)(0x426000E0UL))
#define bFM4_EXTI_EIRR_ER24                       *((volatile  uint8_t *)(0x426000E0UL))
#define bFM_EXTI_EIRR_ER25                        *((volatile  uint8_t *)(0x426000E4UL))
#define bFM4_EXTI_EIRR_ER25                       *((volatile  uint8_t *)(0x426000E4UL))
#define bFM_EXTI_EIRR_ER26                        *((volatile  uint8_t *)(0x426000E8UL))
#define bFM4_EXTI_EIRR_ER26                       *((volatile  uint8_t *)(0x426000E8UL))
#define bFM_EXTI_EIRR_ER27                        *((volatile  uint8_t *)(0x426000ECUL))
#define bFM4_EXTI_EIRR_ER27                       *((volatile  uint8_t *)(0x426000ECUL))
#define bFM_EXTI_EIRR_ER28                        *((volatile  uint8_t *)(0x426000F0UL))
#define bFM4_EXTI_EIRR_ER28                       *((volatile  uint8_t *)(0x426000F0UL))
#define bFM_EXTI_EIRR_ER29                        *((volatile  uint8_t *)(0x426000F4UL))
#define bFM4_EXTI_EIRR_ER29                       *((volatile  uint8_t *)(0x426000F4UL))
#define bFM_EXTI_EIRR_ER30                        *((volatile  uint8_t *)(0x426000F8UL))
#define bFM4_EXTI_EIRR_ER30                       *((volatile  uint8_t *)(0x426000F8UL))
#define bFM_EXTI_EIRR_ER31                        *((volatile  uint8_t *)(0x426000FCUL))
#define bFM4_EXTI_EIRR_ER31                       *((volatile  uint8_t *)(0x426000FCUL))

#define bFM_EXTI_ELVR_LA0                         *((volatile  uint8_t *)(0x42600180UL))
#define bFM4_EXTI_ELVR_LA0                        *((volatile  uint8_t *)(0x42600180UL))
#define bFM_EXTI_ELVR_LB0                         *((volatile  uint8_t *)(0x42600184UL))
#define bFM4_EXTI_ELVR_LB0                        *((volatile  uint8_t *)(0x42600184UL))
#define bFM_EXTI_ELVR_LA1                         *((volatile  uint8_t *)(0x42600188UL))
#define bFM4_EXTI_ELVR_LA1                        *((volatile  uint8_t *)(0x42600188UL))
#define bFM_EXTI_ELVR_LB1                         *((volatile  uint8_t *)(0x4260018CUL))
#define bFM4_EXTI_ELVR_LB1                        *((volatile  uint8_t *)(0x4260018CUL))
#define bFM_EXTI_ELVR_LA2                         *((volatile  uint8_t *)(0x42600190UL))
#define bFM4_EXTI_ELVR_LA2                        *((volatile  uint8_t *)(0x42600190UL))
#define bFM_EXTI_ELVR_LB2                         *((volatile  uint8_t *)(0x42600194UL))
#define bFM4_EXTI_ELVR_LB2                        *((volatile  uint8_t *)(0x42600194UL))
#define bFM_EXTI_ELVR_LA3                         *((volatile  uint8_t *)(0x42600198UL))
#define bFM4_EXTI_ELVR_LA3                        *((volatile  uint8_t *)(0x42600198UL))
#define bFM_EXTI_ELVR_LB3                         *((volatile  uint8_t *)(0x4260019CUL))
#define bFM4_EXTI_ELVR_LB3                        *((volatile  uint8_t *)(0x4260019CUL))
#define bFM_EXTI_ELVR_LA4                         *((volatile  uint8_t *)(0x426001A0UL))
#define bFM4_EXTI_ELVR_LA4                        *((volatile  uint8_t *)(0x426001A0UL))
#define bFM_EXTI_ELVR_LB4                         *((volatile  uint8_t *)(0x426001A4UL))
#define bFM4_EXTI_ELVR_LB4                        *((volatile  uint8_t *)(0x426001A4UL))
#define bFM_EXTI_ELVR_LA5                         *((volatile  uint8_t *)(0x426001A8UL))
#define bFM4_EXTI_ELVR_LA5                        *((volatile  uint8_t *)(0x426001A8UL))
#define bFM_EXTI_ELVR_LB5                         *((volatile  uint8_t *)(0x426001ACUL))
#define bFM4_EXTI_ELVR_LB5                        *((volatile  uint8_t *)(0x426001ACUL))
#define bFM_EXTI_ELVR_LA6                         *((volatile  uint8_t *)(0x426001B0UL))
#define bFM4_EXTI_ELVR_LA6                        *((volatile  uint8_t *)(0x426001B0UL))
#define bFM_EXTI_ELVR_LB6                         *((volatile  uint8_t *)(0x426001B4UL))
#define bFM4_EXTI_ELVR_LB6                        *((volatile  uint8_t *)(0x426001B4UL))
#define bFM_EXTI_ELVR_LA7                         *((volatile  uint8_t *)(0x426001B8UL))
#define bFM4_EXTI_ELVR_LA7                        *((volatile  uint8_t *)(0x426001B8UL))
#define bFM_EXTI_ELVR_LB7                         *((volatile  uint8_t *)(0x426001BCUL))
#define bFM4_EXTI_ELVR_LB7                        *((volatile  uint8_t *)(0x426001BCUL))
#define bFM_EXTI_ELVR_LA8                         *((volatile  uint8_t *)(0x426001C0UL))
#define bFM4_EXTI_ELVR_LA8                        *((volatile  uint8_t *)(0x426001C0UL))
#define bFM_EXTI_ELVR_LB8                         *((volatile  uint8_t *)(0x426001C4UL))
#define bFM4_EXTI_ELVR_LB8                        *((volatile  uint8_t *)(0x426001C4UL))
#define bFM_EXTI_ELVR_LA9                         *((volatile  uint8_t *)(0x426001C8UL))
#define bFM4_EXTI_ELVR_LA9                        *((volatile  uint8_t *)(0x426001C8UL))
#define bFM_EXTI_ELVR_LB9                         *((volatile  uint8_t *)(0x426001CCUL))
#define bFM4_EXTI_ELVR_LB9                        *((volatile  uint8_t *)(0x426001CCUL))
#define bFM_EXTI_ELVR_LA10                        *((volatile  uint8_t *)(0x426001D0UL))
#define bFM4_EXTI_ELVR_LA10                       *((volatile  uint8_t *)(0x426001D0UL))
#define bFM_EXTI_ELVR_LB10                        *((volatile  uint8_t *)(0x426001D4UL))
#define bFM4_EXTI_ELVR_LB10                       *((volatile  uint8_t *)(0x426001D4UL))
#define bFM_EXTI_ELVR_LA11                        *((volatile  uint8_t *)(0x426001D8UL))
#define bFM4_EXTI_ELVR_LA11                       *((volatile  uint8_t *)(0x426001D8UL))
#define bFM_EXTI_ELVR_LB11                        *((volatile  uint8_t *)(0x426001DCUL))
#define bFM4_EXTI_ELVR_LB11                       *((volatile  uint8_t *)(0x426001DCUL))
#define bFM_EXTI_ELVR_LA12                        *((volatile  uint8_t *)(0x426001E0UL))
#define bFM4_EXTI_ELVR_LA12                       *((volatile  uint8_t *)(0x426001E0UL))
#define bFM_EXTI_ELVR_LB12                        *((volatile  uint8_t *)(0x426001E4UL))
#define bFM4_EXTI_ELVR_LB12                       *((volatile  uint8_t *)(0x426001E4UL))
#define bFM_EXTI_ELVR_LA13                        *((volatile  uint8_t *)(0x426001E8UL))
#define bFM4_EXTI_ELVR_LA13                       *((volatile  uint8_t *)(0x426001E8UL))
#define bFM_EXTI_ELVR_LB13                        *((volatile  uint8_t *)(0x426001ECUL))
#define bFM4_EXTI_ELVR_LB13                       *((volatile  uint8_t *)(0x426001ECUL))
#define bFM_EXTI_ELVR_LA14                        *((volatile  uint8_t *)(0x426001F0UL))
#define bFM4_EXTI_ELVR_LA14                       *((volatile  uint8_t *)(0x426001F0UL))
#define bFM_EXTI_ELVR_LB14                        *((volatile  uint8_t *)(0x426001F4UL))
#define bFM4_EXTI_ELVR_LB14                       *((volatile  uint8_t *)(0x426001F4UL))
#define bFM_EXTI_ELVR_LA15                        *((volatile  uint8_t *)(0x426001F8UL))
#define bFM4_EXTI_ELVR_LA15                       *((volatile  uint8_t *)(0x426001F8UL))
#define bFM_EXTI_ELVR_LB15                        *((volatile  uint8_t *)(0x426001FCUL))
#define bFM4_EXTI_ELVR_LB15                       *((volatile  uint8_t *)(0x426001FCUL))

#define bFM_EXTI_ELVR1_LA16                       *((volatile  uint8_t *)(0x42600200UL))
#define bFM4_EXTI_ELVR1_LA16                      *((volatile  uint8_t *)(0x42600200UL))
#define bFM_EXTI_ELVR1_LB16                       *((volatile  uint8_t *)(0x42600204UL))
#define bFM4_EXTI_ELVR1_LB16                      *((volatile  uint8_t *)(0x42600204UL))
#define bFM_EXTI_ELVR1_LA17                       *((volatile  uint8_t *)(0x42600208UL))
#define bFM4_EXTI_ELVR1_LA17                      *((volatile  uint8_t *)(0x42600208UL))
#define bFM_EXTI_ELVR1_LB17                       *((volatile  uint8_t *)(0x4260020CUL))
#define bFM4_EXTI_ELVR1_LB17                      *((volatile  uint8_t *)(0x4260020CUL))
#define bFM_EXTI_ELVR1_LA18                       *((volatile  uint8_t *)(0x42600210UL))
#define bFM4_EXTI_ELVR1_LA18                      *((volatile  uint8_t *)(0x42600210UL))
#define bFM_EXTI_ELVR1_LB18                       *((volatile  uint8_t *)(0x42600214UL))
#define bFM4_EXTI_ELVR1_LB18                      *((volatile  uint8_t *)(0x42600214UL))
#define bFM_EXTI_ELVR1_LA19                       *((volatile  uint8_t *)(0x42600218UL))
#define bFM4_EXTI_ELVR1_LA19                      *((volatile  uint8_t *)(0x42600218UL))
#define bFM_EXTI_ELVR1_LB19                       *((volatile  uint8_t *)(0x4260021CUL))
#define bFM4_EXTI_ELVR1_LB19                      *((volatile  uint8_t *)(0x4260021CUL))
#define bFM_EXTI_ELVR1_LA20                       *((volatile  uint8_t *)(0x42600220UL))
#define bFM4_EXTI_ELVR1_LA20                      *((volatile  uint8_t *)(0x42600220UL))
#define bFM_EXTI_ELVR1_LB20                       *((volatile  uint8_t *)(0x42600224UL))
#define bFM4_EXTI_ELVR1_LB20                      *((volatile  uint8_t *)(0x42600224UL))
#define bFM_EXTI_ELVR1_LA21                       *((volatile  uint8_t *)(0x42600228UL))
#define bFM4_EXTI_ELVR1_LA21                      *((volatile  uint8_t *)(0x42600228UL))
#define bFM_EXTI_ELVR1_LB21                       *((volatile  uint8_t *)(0x4260022CUL))
#define bFM4_EXTI_ELVR1_LB21                      *((volatile  uint8_t *)(0x4260022CUL))
#define bFM_EXTI_ELVR1_LA22                       *((volatile  uint8_t *)(0x42600230UL))
#define bFM4_EXTI_ELVR1_LA22                      *((volatile  uint8_t *)(0x42600230UL))
#define bFM_EXTI_ELVR1_LB22                       *((volatile  uint8_t *)(0x42600234UL))
#define bFM4_EXTI_ELVR1_LB22                      *((volatile  uint8_t *)(0x42600234UL))
#define bFM_EXTI_ELVR1_LA23                       *((volatile  uint8_t *)(0x42600238UL))
#define bFM4_EXTI_ELVR1_LA23                      *((volatile  uint8_t *)(0x42600238UL))
#define bFM_EXTI_ELVR1_LB23                       *((volatile  uint8_t *)(0x4260023CUL))
#define bFM4_EXTI_ELVR1_LB23                      *((volatile  uint8_t *)(0x4260023CUL))
#define bFM_EXTI_ELVR1_LA24                       *((volatile  uint8_t *)(0x42600240UL))
#define bFM4_EXTI_ELVR1_LA24                      *((volatile  uint8_t *)(0x42600240UL))
#define bFM_EXTI_ELVR1_LB24                       *((volatile  uint8_t *)(0x42600244UL))
#define bFM4_EXTI_ELVR1_LB24                      *((volatile  uint8_t *)(0x42600244UL))
#define bFM_EXTI_ELVR1_LA25                       *((volatile  uint8_t *)(0x42600248UL))
#define bFM4_EXTI_ELVR1_LA25                      *((volatile  uint8_t *)(0x42600248UL))
#define bFM_EXTI_ELVR1_LB25                       *((volatile  uint8_t *)(0x4260024CUL))
#define bFM4_EXTI_ELVR1_LB25                      *((volatile  uint8_t *)(0x4260024CUL))
#define bFM_EXTI_ELVR1_LA26                       *((volatile  uint8_t *)(0x42600250UL))
#define bFM4_EXTI_ELVR1_LA26                      *((volatile  uint8_t *)(0x42600250UL))
#define bFM_EXTI_ELVR1_LB26                       *((volatile  uint8_t *)(0x42600254UL))
#define bFM4_EXTI_ELVR1_LB26                      *((volatile  uint8_t *)(0x42600254UL))
#define bFM_EXTI_ELVR1_LA27                       *((volatile  uint8_t *)(0x42600258UL))
#define bFM4_EXTI_ELVR1_LA27                      *((volatile  uint8_t *)(0x42600258UL))
#define bFM_EXTI_ELVR1_LB27                       *((volatile  uint8_t *)(0x4260025CUL))
#define bFM4_EXTI_ELVR1_LB27                      *((volatile  uint8_t *)(0x4260025CUL))
#define bFM_EXTI_ELVR1_LA28                       *((volatile  uint8_t *)(0x42600260UL))
#define bFM4_EXTI_ELVR1_LA28                      *((volatile  uint8_t *)(0x42600260UL))
#define bFM_EXTI_ELVR1_LB28                       *((volatile  uint8_t *)(0x42600264UL))
#define bFM4_EXTI_ELVR1_LB28                      *((volatile  uint8_t *)(0x42600264UL))
#define bFM_EXTI_ELVR1_LA29                       *((volatile  uint8_t *)(0x42600268UL))
#define bFM4_EXTI_ELVR1_LA29                      *((volatile  uint8_t *)(0x42600268UL))
#define bFM_EXTI_ELVR1_LB29                       *((volatile  uint8_t *)(0x4260026CUL))
#define bFM4_EXTI_ELVR1_LB29                      *((volatile  uint8_t *)(0x4260026CUL))
#define bFM_EXTI_ELVR1_LA30                       *((volatile  uint8_t *)(0x42600270UL))
#define bFM4_EXTI_ELVR1_LA30                      *((volatile  uint8_t *)(0x42600270UL))
#define bFM_EXTI_ELVR1_LB30                       *((volatile  uint8_t *)(0x42600274UL))
#define bFM4_EXTI_ELVR1_LB30                      *((volatile  uint8_t *)(0x42600274UL))
#define bFM_EXTI_ELVR1_LA31                       *((volatile  uint8_t *)(0x42600278UL))
#define bFM4_EXTI_ELVR1_LA31                      *((volatile  uint8_t *)(0x42600278UL))
#define bFM_EXTI_ELVR1_LB31                       *((volatile  uint8_t *)(0x4260027CUL))
#define bFM4_EXTI_ELVR1_LB31                      *((volatile  uint8_t *)(0x4260027CUL))

#define bFM_EXTI_ENIR_EN0                         *((volatile  uint8_t *)(0x42600000UL))
#define bFM4_EXTI_ENIR_EN0                        *((volatile  uint8_t *)(0x42600000UL))
#define bFM_EXTI_ENIR_EN1                         *((volatile  uint8_t *)(0x42600004UL))
#define bFM4_EXTI_ENIR_EN1                        *((volatile  uint8_t *)(0x42600004UL))
#define bFM_EXTI_ENIR_EN2                         *((volatile  uint8_t *)(0x42600008UL))
#define bFM4_EXTI_ENIR_EN2                        *((volatile  uint8_t *)(0x42600008UL))
#define bFM_EXTI_ENIR_EN3                         *((volatile  uint8_t *)(0x4260000CUL))
#define bFM4_EXTI_ENIR_EN3                        *((volatile  uint8_t *)(0x4260000CUL))
#define bFM_EXTI_ENIR_EN4                         *((volatile  uint8_t *)(0x42600010UL))
#define bFM4_EXTI_ENIR_EN4                        *((volatile  uint8_t *)(0x42600010UL))
#define bFM_EXTI_ENIR_EN5                         *((volatile  uint8_t *)(0x42600014UL))
#define bFM4_EXTI_ENIR_EN5                        *((volatile  uint8_t *)(0x42600014UL))
#define bFM_EXTI_ENIR_EN6                         *((volatile  uint8_t *)(0x42600018UL))
#define bFM4_EXTI_ENIR_EN6                        *((volatile  uint8_t *)(0x42600018UL))
#define bFM_EXTI_ENIR_EN7                         *((volatile  uint8_t *)(0x4260001CUL))
#define bFM4_EXTI_ENIR_EN7                        *((volatile  uint8_t *)(0x4260001CUL))
#define bFM_EXTI_ENIR_EN8                         *((volatile  uint8_t *)(0x42600020UL))
#define bFM4_EXTI_ENIR_EN8                        *((volatile  uint8_t *)(0x42600020UL))
#define bFM_EXTI_ENIR_EN9                         *((volatile  uint8_t *)(0x42600024UL))
#define bFM4_EXTI_ENIR_EN9                        *((volatile  uint8_t *)(0x42600024UL))
#define bFM_EXTI_ENIR_EN10                        *((volatile  uint8_t *)(0x42600028UL))
#define bFM4_EXTI_ENIR_EN10                       *((volatile  uint8_t *)(0x42600028UL))
#define bFM_EXTI_ENIR_EN11                        *((volatile  uint8_t *)(0x4260002CUL))
#define bFM4_EXTI_ENIR_EN11                       *((volatile  uint8_t *)(0x4260002CUL))
#define bFM_EXTI_ENIR_EN12                        *((volatile  uint8_t *)(0x42600030UL))
#define bFM4_EXTI_ENIR_EN12                       *((volatile  uint8_t *)(0x42600030UL))
#define bFM_EXTI_ENIR_EN13                        *((volatile  uint8_t *)(0x42600034UL))
#define bFM4_EXTI_ENIR_EN13                       *((volatile  uint8_t *)(0x42600034UL))
#define bFM_EXTI_ENIR_EN14                        *((volatile  uint8_t *)(0x42600038UL))
#define bFM4_EXTI_ENIR_EN14                       *((volatile  uint8_t *)(0x42600038UL))
#define bFM_EXTI_ENIR_EN15                        *((volatile  uint8_t *)(0x4260003CUL))
#define bFM4_EXTI_ENIR_EN15                       *((volatile  uint8_t *)(0x4260003CUL))
#define bFM_EXTI_ENIR_EN16                        *((volatile  uint8_t *)(0x42600040UL))
#define bFM4_EXTI_ENIR_EN16                       *((volatile  uint8_t *)(0x42600040UL))
#define bFM_EXTI_ENIR_EN17                        *((volatile  uint8_t *)(0x42600044UL))
#define bFM4_EXTI_ENIR_EN17                       *((volatile  uint8_t *)(0x42600044UL))
#define bFM_EXTI_ENIR_EN18                        *((volatile  uint8_t *)(0x42600048UL))
#define bFM4_EXTI_ENIR_EN18                       *((volatile  uint8_t *)(0x42600048UL))
#define bFM_EXTI_ENIR_EN19                        *((volatile  uint8_t *)(0x4260004CUL))
#define bFM4_EXTI_ENIR_EN19                       *((volatile  uint8_t *)(0x4260004CUL))
#define bFM_EXTI_ENIR_EN20                        *((volatile  uint8_t *)(0x42600050UL))
#define bFM4_EXTI_ENIR_EN20                       *((volatile  uint8_t *)(0x42600050UL))
#define bFM_EXTI_ENIR_EN21                        *((volatile  uint8_t *)(0x42600054UL))
#define bFM4_EXTI_ENIR_EN21                       *((volatile  uint8_t *)(0x42600054UL))
#define bFM_EXTI_ENIR_EN22                        *((volatile  uint8_t *)(0x42600058UL))
#define bFM4_EXTI_ENIR_EN22                       *((volatile  uint8_t *)(0x42600058UL))
#define bFM_EXTI_ENIR_EN23                        *((volatile  uint8_t *)(0x4260005CUL))
#define bFM4_EXTI_ENIR_EN23                       *((volatile  uint8_t *)(0x4260005CUL))
#define bFM_EXTI_ENIR_EN24                        *((volatile  uint8_t *)(0x42600060UL))
#define bFM4_EXTI_ENIR_EN24                       *((volatile  uint8_t *)(0x42600060UL))
#define bFM_EXTI_ENIR_EN25                        *((volatile  uint8_t *)(0x42600064UL))
#define bFM4_EXTI_ENIR_EN25                       *((volatile  uint8_t *)(0x42600064UL))
#define bFM_EXTI_ENIR_EN26                        *((volatile  uint8_t *)(0x42600068UL))
#define bFM4_EXTI_ENIR_EN26                       *((volatile  uint8_t *)(0x42600068UL))
#define bFM_EXTI_ENIR_EN27                        *((volatile  uint8_t *)(0x4260006CUL))
#define bFM4_EXTI_ENIR_EN27                       *((volatile  uint8_t *)(0x4260006CUL))
#define bFM_EXTI_ENIR_EN28                        *((volatile  uint8_t *)(0x42600070UL))
#define bFM4_EXTI_ENIR_EN28                       *((volatile  uint8_t *)(0x42600070UL))
#define bFM_EXTI_ENIR_EN29                        *((volatile  uint8_t *)(0x42600074UL))
#define bFM4_EXTI_ENIR_EN29                       *((volatile  uint8_t *)(0x42600074UL))
#define bFM_EXTI_ENIR_EN30                        *((volatile  uint8_t *)(0x42600078UL))
#define bFM4_EXTI_ENIR_EN30                       *((volatile  uint8_t *)(0x42600078UL))
#define bFM_EXTI_ENIR_EN31                        *((volatile  uint8_t *)(0x4260007CUL))
#define bFM4_EXTI_ENIR_EN31                       *((volatile  uint8_t *)(0x4260007CUL))

#define bFM_EXTI_NMICL_NCL                        *((volatile  uint8_t *)(0x42600300UL))
#define bFM4_EXTI_NMICL_NCL                       *((volatile  uint8_t *)(0x42600300UL))

#define bFM_EXTI_NMIRR_NR                         *((volatile  uint8_t *)(0x42600280UL))
#define bFM4_EXTI_NMIRR_NR                        *((volatile  uint8_t *)(0x42600280UL))


/*******************************************************************************
* FLASH_IF Registers FLASH_IF
*   Bitband Section
*******************************************************************************/
#define bFM_FLASH_IF_DFCTRLR_DFE                  *((volatile  uint32_t*)(0x42000600UL))
#define bFM4_FLASH_IF_DFCTRLR_DFE                 *((volatile  uint32_t*)(0x42000600UL))
#define bFM_FLASH_IF_DFCTRLR_RME                  *((volatile  uint32_t*)(0x42000604UL))
#define bFM4_FLASH_IF_DFCTRLR_RME                 *((volatile  uint32_t*)(0x42000604UL))

#define bFM_FLASH_IF_FBFCR_BE                     *((volatile  uint8_t *)(0x42000280UL))
#define bFM4_FLASH_IF_FBFCR_BE                    *((volatile  uint8_t *)(0x42000280UL))
#define bFM_FLASH_IF_FBFCR_BS                     *((volatile  uint8_t *)(0x42000284UL))
#define bFM4_FLASH_IF_FBFCR_BS                    *((volatile  uint8_t *)(0x42000284UL))

#define bFM_FLASH_IF_FICLR_RDYIC                  *((volatile  uint8_t *)(0x42000500UL))
#define bFM4_FLASH_IF_FICLR_RDYIC                 *((volatile  uint8_t *)(0x42000500UL))
#define bFM_FLASH_IF_FICLR_HNGIC                  *((volatile  uint8_t *)(0x42000504UL))
#define bFM4_FLASH_IF_FICLR_HNGIC                 *((volatile  uint8_t *)(0x42000504UL))
#define bFM_FLASH_IF_FICLR_ERRIC                  *((volatile  uint8_t *)(0x42000508UL))
#define bFM4_FLASH_IF_FICLR_ERRIC                 *((volatile  uint8_t *)(0x42000508UL))

#define bFM_FLASH_IF_FICR_RDYIE                   *((volatile  uint8_t *)(0x42000400UL))
#define bFM4_FLASH_IF_FICR_RDYIE                  *((volatile  uint8_t *)(0x42000400UL))
#define bFM_FLASH_IF_FICR_HNGIE                   *((volatile  uint8_t *)(0x42000404UL))
#define bFM4_FLASH_IF_FICR_HNGIE                  *((volatile  uint8_t *)(0x42000404UL))
#define bFM_FLASH_IF_FICR_ERRIE                   *((volatile  uint8_t *)(0x42000408UL))
#define bFM4_FLASH_IF_FICR_ERRIE                  *((volatile  uint8_t *)(0x42000408UL))

#define bFM_FLASH_IF_FISR_RDYIF                   *((volatile  uint8_t *)(0x42000480UL))
#define bFM4_FLASH_IF_FISR_RDYIF                  *((volatile  uint8_t *)(0x42000480UL))
#define bFM_FLASH_IF_FISR_HNGIF                   *((volatile  uint8_t *)(0x42000484UL))
#define bFM4_FLASH_IF_FISR_HNGIF                  *((volatile  uint8_t *)(0x42000484UL))
#define bFM_FLASH_IF_FISR_ERRIF                   *((volatile  uint8_t *)(0x42000488UL))
#define bFM4_FLASH_IF_FISR_ERRIF                  *((volatile  uint8_t *)(0x42000488UL))

#define bFM_FLASH_IF_FSTR_RDY                     *((volatile  uint8_t *)(0x42000100UL))
#define bFM4_FLASH_IF_FSTR_RDY                    *((volatile  uint8_t *)(0x42000100UL))
#define bFM_FLASH_IF_FSTR_HNG                     *((volatile  uint8_t *)(0x42000104UL))
#define bFM4_FLASH_IF_FSTR_HNG                    *((volatile  uint8_t *)(0x42000104UL))
#define bFM_FLASH_IF_FSTR_ERR                     *((volatile  uint8_t *)(0x42000108UL))
#define bFM4_FLASH_IF_FSTR_ERR                    *((volatile  uint8_t *)(0x42000108UL))


/*******************************************************************************
* GPIO Registers GPIO
*   Bitband Section
*******************************************************************************/
#define bFM_GPIO_ADE_AN00                         *((volatile  uint8_t *)(0x42DEA000UL))
#define bFM4_GPIO_ADE_AN00                        *((volatile  uint8_t *)(0x42DEA000UL))
#define bFM_GPIO_ADE_AN01                         *((volatile  uint8_t *)(0x42DEA004UL))
#define bFM4_GPIO_ADE_AN01                        *((volatile  uint8_t *)(0x42DEA004UL))
#define bFM_GPIO_ADE_AN02                         *((volatile  uint8_t *)(0x42DEA008UL))
#define bFM4_GPIO_ADE_AN02                        *((volatile  uint8_t *)(0x42DEA008UL))
#define bFM_GPIO_ADE_AN03                         *((volatile  uint8_t *)(0x42DEA00CUL))
#define bFM4_GPIO_ADE_AN03                        *((volatile  uint8_t *)(0x42DEA00CUL))
#define bFM_GPIO_ADE_AN04                         *((volatile  uint8_t *)(0x42DEA010UL))
#define bFM4_GPIO_ADE_AN04                        *((volatile  uint8_t *)(0x42DEA010UL))
#define bFM_GPIO_ADE_AN05                         *((volatile  uint8_t *)(0x42DEA014UL))
#define bFM4_GPIO_ADE_AN05                        *((volatile  uint8_t *)(0x42DEA014UL))
#define bFM_GPIO_ADE_AN06                         *((volatile  uint8_t *)(0x42DEA018UL))
#define bFM4_GPIO_ADE_AN06                        *((volatile  uint8_t *)(0x42DEA018UL))
#define bFM_GPIO_ADE_AN07                         *((volatile  uint8_t *)(0x42DEA01CUL))
#define bFM4_GPIO_ADE_AN07                        *((volatile  uint8_t *)(0x42DEA01CUL))
#define bFM_GPIO_ADE_AN08                         *((volatile  uint8_t *)(0x42DEA020UL))
#define bFM4_GPIO_ADE_AN08                        *((volatile  uint8_t *)(0x42DEA020UL))
#define bFM_GPIO_ADE_AN09                         *((volatile  uint8_t *)(0x42DEA024UL))
#define bFM4_GPIO_ADE_AN09                        *((volatile  uint8_t *)(0x42DEA024UL))
#define bFM_GPIO_ADE_AN10                         *((volatile  uint8_t *)(0x42DEA028UL))
#define bFM4_GPIO_ADE_AN10                        *((volatile  uint8_t *)(0x42DEA028UL))
#define bFM_GPIO_ADE_AN11                         *((volatile  uint8_t *)(0x42DEA02CUL))
#define bFM4_GPIO_ADE_AN11                        *((volatile  uint8_t *)(0x42DEA02CUL))
#define bFM_GPIO_ADE_AN12                         *((volatile  uint8_t *)(0x42DEA030UL))
#define bFM4_GPIO_ADE_AN12                        *((volatile  uint8_t *)(0x42DEA030UL))
#define bFM_GPIO_ADE_AN13                         *((volatile  uint8_t *)(0x42DEA034UL))
#define bFM4_GPIO_ADE_AN13                        *((volatile  uint8_t *)(0x42DEA034UL))
#define bFM_GPIO_ADE_AN14                         *((volatile  uint8_t *)(0x42DEA038UL))
#define bFM4_GPIO_ADE_AN14                        *((volatile  uint8_t *)(0x42DEA038UL))
#define bFM_GPIO_ADE_AN15                         *((volatile  uint8_t *)(0x42DEA03CUL))
#define bFM4_GPIO_ADE_AN15                        *((volatile  uint8_t *)(0x42DEA03CUL))
#define bFM_GPIO_ADE_AN16                         *((volatile  uint8_t *)(0x42DEA040UL))
#define bFM4_GPIO_ADE_AN16                        *((volatile  uint8_t *)(0x42DEA040UL))
#define bFM_GPIO_ADE_AN17                         *((volatile  uint8_t *)(0x42DEA044UL))
#define bFM4_GPIO_ADE_AN17                        *((volatile  uint8_t *)(0x42DEA044UL))
#define bFM_GPIO_ADE_AN18                         *((volatile  uint8_t *)(0x42DEA048UL))
#define bFM4_GPIO_ADE_AN18                        *((volatile  uint8_t *)(0x42DEA048UL))
#define bFM_GPIO_ADE_AN19                         *((volatile  uint8_t *)(0x42DEA04CUL))
#define bFM4_GPIO_ADE_AN19                        *((volatile  uint8_t *)(0x42DEA04CUL))
#define bFM_GPIO_ADE_AN20                         *((volatile  uint8_t *)(0x42DEA050UL))
#define bFM4_GPIO_ADE_AN20                        *((volatile  uint8_t *)(0x42DEA050UL))
#define bFM_GPIO_ADE_AN21                         *((volatile  uint8_t *)(0x42DEA054UL))
#define bFM4_GPIO_ADE_AN21                        *((volatile  uint8_t *)(0x42DEA054UL))
#define bFM_GPIO_ADE_AN22                         *((volatile  uint8_t *)(0x42DEA058UL))
#define bFM4_GPIO_ADE_AN22                        *((volatile  uint8_t *)(0x42DEA058UL))
#define bFM_GPIO_ADE_AN23                         *((volatile  uint8_t *)(0x42DEA05CUL))
#define bFM4_GPIO_ADE_AN23                        *((volatile  uint8_t *)(0x42DEA05CUL))
#define bFM_GPIO_ADE_AN24                         *((volatile  uint8_t *)(0x42DEA060UL))
#define bFM4_GPIO_ADE_AN24                        *((volatile  uint8_t *)(0x42DEA060UL))
#define bFM_GPIO_ADE_AN25                         *((volatile  uint8_t *)(0x42DEA064UL))
#define bFM4_GPIO_ADE_AN25                        *((volatile  uint8_t *)(0x42DEA064UL))
#define bFM_GPIO_ADE_AN26                         *((volatile  uint8_t *)(0x42DEA068UL))
#define bFM4_GPIO_ADE_AN26                        *((volatile  uint8_t *)(0x42DEA068UL))
#define bFM_GPIO_ADE_AN27                         *((volatile  uint8_t *)(0x42DEA06CUL))
#define bFM4_GPIO_ADE_AN27                        *((volatile  uint8_t *)(0x42DEA06CUL))
#define bFM_GPIO_ADE_AN28                         *((volatile  uint8_t *)(0x42DEA070UL))
#define bFM4_GPIO_ADE_AN28                        *((volatile  uint8_t *)(0x42DEA070UL))
#define bFM_GPIO_ADE_AN29                         *((volatile  uint8_t *)(0x42DEA074UL))
#define bFM4_GPIO_ADE_AN29                        *((volatile  uint8_t *)(0x42DEA074UL))
#define bFM_GPIO_ADE_AN30                         *((volatile  uint8_t *)(0x42DEA078UL))
#define bFM4_GPIO_ADE_AN30                        *((volatile  uint8_t *)(0x42DEA078UL))
#define bFM_GPIO_ADE_AN31                         *((volatile  uint8_t *)(0x42DEA07CUL))
#define bFM4_GPIO_ADE_AN31                        *((volatile  uint8_t *)(0x42DEA07CUL))

#define bFM_GPIO_DDR0_P0                          *((volatile  uint8_t *)(0x42DE4000UL))
#define bFM4_GPIO_DDR0_P0                         *((volatile  uint8_t *)(0x42DE4000UL))
#define bFM_GPIO_DDR0_P1                          *((volatile  uint8_t *)(0x42DE4004UL))
#define bFM4_GPIO_DDR0_P1                         *((volatile  uint8_t *)(0x42DE4004UL))
#define bFM_GPIO_DDR0_P2                          *((volatile  uint8_t *)(0x42DE4008UL))
#define bFM4_GPIO_DDR0_P2                         *((volatile  uint8_t *)(0x42DE4008UL))
#define bFM_GPIO_DDR0_P3                          *((volatile  uint8_t *)(0x42DE400CUL))
#define bFM4_GPIO_DDR0_P3                         *((volatile  uint8_t *)(0x42DE400CUL))
#define bFM_GPIO_DDR0_P4                          *((volatile  uint8_t *)(0x42DE4010UL))
#define bFM4_GPIO_DDR0_P4                         *((volatile  uint8_t *)(0x42DE4010UL))
#define bFM_GPIO_DDR0_P8                          *((volatile  uint8_t *)(0x42DE4020UL))
#define bFM4_GPIO_DDR0_P8                         *((volatile  uint8_t *)(0x42DE4020UL))
#define bFM_GPIO_DDR0_P9                          *((volatile  uint8_t *)(0x42DE4024UL))
#define bFM4_GPIO_DDR0_P9                         *((volatile  uint8_t *)(0x42DE4024UL))
#define bFM_GPIO_DDR0_PA                          *((volatile  uint8_t *)(0x42DE4028UL))
#define bFM4_GPIO_DDR0_PA                         *((volatile  uint8_t *)(0x42DE4028UL))

#define bFM_GPIO_DDR1_P0                          *((volatile  uint8_t *)(0x42DE4080UL))
#define bFM4_GPIO_DDR1_P0                         *((volatile  uint8_t *)(0x42DE4080UL))
#define bFM_GPIO_DDR1_P1                          *((volatile  uint8_t *)(0x42DE4084UL))
#define bFM4_GPIO_DDR1_P1                         *((volatile  uint8_t *)(0x42DE4084UL))
#define bFM_GPIO_DDR1_P2                          *((volatile  uint8_t *)(0x42DE4088UL))
#define bFM4_GPIO_DDR1_P2                         *((volatile  uint8_t *)(0x42DE4088UL))
#define bFM_GPIO_DDR1_P3                          *((volatile  uint8_t *)(0x42DE408CUL))
#define bFM4_GPIO_DDR1_P3                         *((volatile  uint8_t *)(0x42DE408CUL))
#define bFM_GPIO_DDR1_P4                          *((volatile  uint8_t *)(0x42DE4090UL))
#define bFM4_GPIO_DDR1_P4                         *((volatile  uint8_t *)(0x42DE4090UL))
#define bFM_GPIO_DDR1_P5                          *((volatile  uint8_t *)(0x42DE4094UL))
#define bFM4_GPIO_DDR1_P5                         *((volatile  uint8_t *)(0x42DE4094UL))
#define bFM_GPIO_DDR1_P6                          *((volatile  uint8_t *)(0x42DE4098UL))
#define bFM4_GPIO_DDR1_P6                         *((volatile  uint8_t *)(0x42DE4098UL))
#define bFM_GPIO_DDR1_P7                          *((volatile  uint8_t *)(0x42DE409CUL))
#define bFM4_GPIO_DDR1_P7                         *((volatile  uint8_t *)(0x42DE409CUL))
#define bFM_GPIO_DDR1_P8                          *((volatile  uint8_t *)(0x42DE40A0UL))
#define bFM4_GPIO_DDR1_P8                         *((volatile  uint8_t *)(0x42DE40A0UL))
#define bFM_GPIO_DDR1_P9                          *((volatile  uint8_t *)(0x42DE40A4UL))
#define bFM4_GPIO_DDR1_P9                         *((volatile  uint8_t *)(0x42DE40A4UL))
#define bFM_GPIO_DDR1_PA                          *((volatile  uint8_t *)(0x42DE40A8UL))
#define bFM4_GPIO_DDR1_PA                         *((volatile  uint8_t *)(0x42DE40A8UL))
#define bFM_GPIO_DDR1_PB                          *((volatile  uint8_t *)(0x42DE40ACUL))
#define bFM4_GPIO_DDR1_PB                         *((volatile  uint8_t *)(0x42DE40ACUL))
#define bFM_GPIO_DDR1_PC                          *((volatile  uint8_t *)(0x42DE40B0UL))
#define bFM4_GPIO_DDR1_PC                         *((volatile  uint8_t *)(0x42DE40B0UL))
#define bFM_GPIO_DDR1_PD                          *((volatile  uint8_t *)(0x42DE40B4UL))
#define bFM4_GPIO_DDR1_PD                         *((volatile  uint8_t *)(0x42DE40B4UL))
#define bFM_GPIO_DDR1_PE                          *((volatile  uint8_t *)(0x42DE40B8UL))
#define bFM4_GPIO_DDR1_PE                         *((volatile  uint8_t *)(0x42DE40B8UL))
#define bFM_GPIO_DDR1_PF                          *((volatile  uint8_t *)(0x42DE40BCUL))
#define bFM4_GPIO_DDR1_PF                         *((volatile  uint8_t *)(0x42DE40BCUL))

#define bFM_GPIO_DDR2_P0                          *((volatile  uint8_t *)(0x42DE4100UL))
#define bFM4_GPIO_DDR2_P0                         *((volatile  uint8_t *)(0x42DE4100UL))
#define bFM_GPIO_DDR2_P1                          *((volatile  uint8_t *)(0x42DE4104UL))
#define bFM4_GPIO_DDR2_P1                         *((volatile  uint8_t *)(0x42DE4104UL))
#define bFM_GPIO_DDR2_P2                          *((volatile  uint8_t *)(0x42DE4108UL))
#define bFM4_GPIO_DDR2_P2                         *((volatile  uint8_t *)(0x42DE4108UL))
#define bFM_GPIO_DDR2_P3                          *((volatile  uint8_t *)(0x42DE410CUL))
#define bFM4_GPIO_DDR2_P3                         *((volatile  uint8_t *)(0x42DE410CUL))
#define bFM_GPIO_DDR2_P4                          *((volatile  uint8_t *)(0x42DE4110UL))
#define bFM4_GPIO_DDR2_P4                         *((volatile  uint8_t *)(0x42DE4110UL))
#define bFM_GPIO_DDR2_P5                          *((volatile  uint8_t *)(0x42DE4114UL))
#define bFM4_GPIO_DDR2_P5                         *((volatile  uint8_t *)(0x42DE4114UL))
#define bFM_GPIO_DDR2_P6                          *((volatile  uint8_t *)(0x42DE4118UL))
#define bFM4_GPIO_DDR2_P6                         *((volatile  uint8_t *)(0x42DE4118UL))
#define bFM_GPIO_DDR2_P7                          *((volatile  uint8_t *)(0x42DE411CUL))
#define bFM4_GPIO_DDR2_P7                         *((volatile  uint8_t *)(0x42DE411CUL))
#define bFM_GPIO_DDR2_P8                          *((volatile  uint8_t *)(0x42DE4120UL))
#define bFM4_GPIO_DDR2_P8                         *((volatile  uint8_t *)(0x42DE4120UL))
#define bFM_GPIO_DDR2_P9                          *((volatile  uint8_t *)(0x42DE4124UL))
#define bFM4_GPIO_DDR2_P9                         *((volatile  uint8_t *)(0x42DE4124UL))
#define bFM_GPIO_DDR2_PA                          *((volatile  uint8_t *)(0x42DE4128UL))
#define bFM4_GPIO_DDR2_PA                         *((volatile  uint8_t *)(0x42DE4128UL))

#define bFM_GPIO_DDR3_P0                          *((volatile  uint8_t *)(0x42DE4180UL))
#define bFM4_GPIO_DDR3_P0                         *((volatile  uint8_t *)(0x42DE4180UL))
#define bFM_GPIO_DDR3_P1                          *((volatile  uint8_t *)(0x42DE4184UL))
#define bFM4_GPIO_DDR3_P1                         *((volatile  uint8_t *)(0x42DE4184UL))
#define bFM_GPIO_DDR3_P2                          *((volatile  uint8_t *)(0x42DE4188UL))
#define bFM4_GPIO_DDR3_P2                         *((volatile  uint8_t *)(0x42DE4188UL))
#define bFM_GPIO_DDR3_P3                          *((volatile  uint8_t *)(0x42DE418CUL))
#define bFM4_GPIO_DDR3_P3                         *((volatile  uint8_t *)(0x42DE418CUL))
#define bFM_GPIO_DDR3_P4                          *((volatile  uint8_t *)(0x42DE4190UL))
#define bFM4_GPIO_DDR3_P4                         *((volatile  uint8_t *)(0x42DE4190UL))
#define bFM_GPIO_DDR3_P5                          *((volatile  uint8_t *)(0x42DE4194UL))
#define bFM4_GPIO_DDR3_P5                         *((volatile  uint8_t *)(0x42DE4194UL))
#define bFM_GPIO_DDR3_P6                          *((volatile  uint8_t *)(0x42DE4198UL))
#define bFM4_GPIO_DDR3_P6                         *((volatile  uint8_t *)(0x42DE4198UL))
#define bFM_GPIO_DDR3_P7                          *((volatile  uint8_t *)(0x42DE419CUL))
#define bFM4_GPIO_DDR3_P7                         *((volatile  uint8_t *)(0x42DE419CUL))
#define bFM_GPIO_DDR3_P8                          *((volatile  uint8_t *)(0x42DE41A0UL))
#define bFM4_GPIO_DDR3_P8                         *((volatile  uint8_t *)(0x42DE41A0UL))
#define bFM_GPIO_DDR3_P9                          *((volatile  uint8_t *)(0x42DE41A4UL))
#define bFM4_GPIO_DDR3_P9                         *((volatile  uint8_t *)(0x42DE41A4UL))
#define bFM_GPIO_DDR3_PA                          *((volatile  uint8_t *)(0x42DE41A8UL))
#define bFM4_GPIO_DDR3_PA                         *((volatile  uint8_t *)(0x42DE41A8UL))
#define bFM_GPIO_DDR3_PB                          *((volatile  uint8_t *)(0x42DE41ACUL))
#define bFM4_GPIO_DDR3_PB                         *((volatile  uint8_t *)(0x42DE41ACUL))
#define bFM_GPIO_DDR3_PC                          *((volatile  uint8_t *)(0x42DE41B0UL))
#define bFM4_GPIO_DDR3_PC                         *((volatile  uint8_t *)(0x42DE41B0UL))
#define bFM_GPIO_DDR3_PD                          *((volatile  uint8_t *)(0x42DE41B4UL))
#define bFM4_GPIO_DDR3_PD                         *((volatile  uint8_t *)(0x42DE41B4UL))
#define bFM_GPIO_DDR3_PE                          *((volatile  uint8_t *)(0x42DE41B8UL))
#define bFM4_GPIO_DDR3_PE                         *((volatile  uint8_t *)(0x42DE41B8UL))

#define bFM_GPIO_DDR4_P0                          *((volatile  uint8_t *)(0x42DE4200UL))
#define bFM4_GPIO_DDR4_P0                         *((volatile  uint8_t *)(0x42DE4200UL))
#define bFM_GPIO_DDR4_P1                          *((volatile  uint8_t *)(0x42DE4204UL))
#define bFM4_GPIO_DDR4_P1                         *((volatile  uint8_t *)(0x42DE4204UL))
#define bFM_GPIO_DDR4_P2                          *((volatile  uint8_t *)(0x42DE4208UL))
#define bFM4_GPIO_DDR4_P2                         *((volatile  uint8_t *)(0x42DE4208UL))
#define bFM_GPIO_DDR4_P3                          *((volatile  uint8_t *)(0x42DE420CUL))
#define bFM4_GPIO_DDR4_P3                         *((volatile  uint8_t *)(0x42DE420CUL))
#define bFM_GPIO_DDR4_P4                          *((volatile  uint8_t *)(0x42DE4210UL))
#define bFM4_GPIO_DDR4_P4                         *((volatile  uint8_t *)(0x42DE4210UL))
#define bFM_GPIO_DDR4_P5                          *((volatile  uint8_t *)(0x42DE4214UL))
#define bFM4_GPIO_DDR4_P5                         *((volatile  uint8_t *)(0x42DE4214UL))
#define bFM_GPIO_DDR4_P6                          *((volatile  uint8_t *)(0x42DE4218UL))
#define bFM4_GPIO_DDR4_P6                         *((volatile  uint8_t *)(0x42DE4218UL))
#define bFM_GPIO_DDR4_P7                          *((volatile  uint8_t *)(0x42DE421CUL))
#define bFM4_GPIO_DDR4_P7                         *((volatile  uint8_t *)(0x42DE421CUL))
#define bFM_GPIO_DDR4_P8                          *((volatile  uint8_t *)(0x42DE4220UL))
#define bFM4_GPIO_DDR4_P8                         *((volatile  uint8_t *)(0x42DE4220UL))
#define bFM_GPIO_DDR4_P9                          *((volatile  uint8_t *)(0x42DE4224UL))
#define bFM4_GPIO_DDR4_P9                         *((volatile  uint8_t *)(0x42DE4224UL))

#define bFM_GPIO_DDR5_P0                          *((volatile  uint8_t *)(0x42DE4280UL))
#define bFM4_GPIO_DDR5_P0                         *((volatile  uint8_t *)(0x42DE4280UL))
#define bFM_GPIO_DDR5_P1                          *((volatile  uint8_t *)(0x42DE4284UL))
#define bFM4_GPIO_DDR5_P1                         *((volatile  uint8_t *)(0x42DE4284UL))
#define bFM_GPIO_DDR5_P2                          *((volatile  uint8_t *)(0x42DE4288UL))
#define bFM4_GPIO_DDR5_P2                         *((volatile  uint8_t *)(0x42DE4288UL))
#define bFM_GPIO_DDR5_PD                          *((volatile  uint8_t *)(0x42DE42B4UL))
#define bFM4_GPIO_DDR5_PD                         *((volatile  uint8_t *)(0x42DE42B4UL))
#define bFM_GPIO_DDR5_PE                          *((volatile  uint8_t *)(0x42DE42B8UL))
#define bFM4_GPIO_DDR5_PE                         *((volatile  uint8_t *)(0x42DE42B8UL))
#define bFM_GPIO_DDR5_PF                          *((volatile  uint8_t *)(0x42DE42BCUL))
#define bFM4_GPIO_DDR5_PF                         *((volatile  uint8_t *)(0x42DE42BCUL))

#define bFM_GPIO_DDR6_P0                          *((volatile  uint8_t *)(0x42DE4300UL))
#define bFM4_GPIO_DDR6_P0                         *((volatile  uint8_t *)(0x42DE4300UL))
#define bFM_GPIO_DDR6_P1                          *((volatile  uint8_t *)(0x42DE4304UL))
#define bFM4_GPIO_DDR6_P1                         *((volatile  uint8_t *)(0x42DE4304UL))
#define bFM_GPIO_DDR6_P2                          *((volatile  uint8_t *)(0x42DE4308UL))
#define bFM4_GPIO_DDR6_P2                         *((volatile  uint8_t *)(0x42DE4308UL))
#define bFM_GPIO_DDR6_P3                          *((volatile  uint8_t *)(0x42DE430CUL))
#define bFM4_GPIO_DDR6_P3                         *((volatile  uint8_t *)(0x42DE430CUL))
#define bFM_GPIO_DDR6_P4                          *((volatile  uint8_t *)(0x42DE4310UL))
#define bFM4_GPIO_DDR6_P4                         *((volatile  uint8_t *)(0x42DE4310UL))
#define bFM_GPIO_DDR6_P5                          *((volatile  uint8_t *)(0x42DE4314UL))
#define bFM4_GPIO_DDR6_P5                         *((volatile  uint8_t *)(0x42DE4314UL))
#define bFM_GPIO_DDR6_PE                          *((volatile  uint8_t *)(0x42DE4338UL))
#define bFM4_GPIO_DDR6_PE                         *((volatile  uint8_t *)(0x42DE4338UL))

#define bFM_GPIO_DDR7_P0                          *((volatile  uint8_t *)(0x42DE4380UL))
#define bFM4_GPIO_DDR7_P0                         *((volatile  uint8_t *)(0x42DE4380UL))
#define bFM_GPIO_DDR7_P1                          *((volatile  uint8_t *)(0x42DE4384UL))
#define bFM4_GPIO_DDR7_P1                         *((volatile  uint8_t *)(0x42DE4384UL))
#define bFM_GPIO_DDR7_P2                          *((volatile  uint8_t *)(0x42DE4388UL))
#define bFM4_GPIO_DDR7_P2                         *((volatile  uint8_t *)(0x42DE4388UL))
#define bFM_GPIO_DDR7_P3                          *((volatile  uint8_t *)(0x42DE438CUL))
#define bFM4_GPIO_DDR7_P3                         *((volatile  uint8_t *)(0x42DE438CUL))
#define bFM_GPIO_DDR7_P4                          *((volatile  uint8_t *)(0x42DE4390UL))
#define bFM4_GPIO_DDR7_P4                         *((volatile  uint8_t *)(0x42DE4390UL))
#define bFM_GPIO_DDR7_P5                          *((volatile  uint8_t *)(0x42DE4394UL))
#define bFM4_GPIO_DDR7_P5                         *((volatile  uint8_t *)(0x42DE4394UL))
#define bFM_GPIO_DDR7_P6                          *((volatile  uint8_t *)(0x42DE4398UL))
#define bFM4_GPIO_DDR7_P6                         *((volatile  uint8_t *)(0x42DE4398UL))
#define bFM_GPIO_DDR7_P7                          *((volatile  uint8_t *)(0x42DE439CUL))
#define bFM4_GPIO_DDR7_P7                         *((volatile  uint8_t *)(0x42DE439CUL))
#define bFM_GPIO_DDR7_P8                          *((volatile  uint8_t *)(0x42DE43A0UL))
#define bFM4_GPIO_DDR7_P8                         *((volatile  uint8_t *)(0x42DE43A0UL))
#define bFM_GPIO_DDR7_P9                          *((volatile  uint8_t *)(0x42DE43A4UL))
#define bFM4_GPIO_DDR7_P9                         *((volatile  uint8_t *)(0x42DE43A4UL))
#define bFM_GPIO_DDR7_PA                          *((volatile  uint8_t *)(0x42DE43A8UL))
#define bFM4_GPIO_DDR7_PA                         *((volatile  uint8_t *)(0x42DE43A8UL))
#define bFM_GPIO_DDR7_PB                          *((volatile  uint8_t *)(0x42DE43ACUL))
#define bFM4_GPIO_DDR7_PB                         *((volatile  uint8_t *)(0x42DE43ACUL))
#define bFM_GPIO_DDR7_PC                          *((volatile  uint8_t *)(0x42DE43B0UL))
#define bFM4_GPIO_DDR7_PC                         *((volatile  uint8_t *)(0x42DE43B0UL))
#define bFM_GPIO_DDR7_PD                          *((volatile  uint8_t *)(0x42DE43B4UL))
#define bFM4_GPIO_DDR7_PD                         *((volatile  uint8_t *)(0x42DE43B4UL))
#define bFM_GPIO_DDR7_PE                          *((volatile  uint8_t *)(0x42DE43B8UL))
#define bFM4_GPIO_DDR7_PE                         *((volatile  uint8_t *)(0x42DE43B8UL))

#define bFM_GPIO_DDR8_P0                          *((volatile  uint8_t *)(0x42DE4400UL))
#define bFM4_GPIO_DDR8_P0                         *((volatile  uint8_t *)(0x42DE4400UL))
#define bFM_GPIO_DDR8_P1                          *((volatile  uint8_t *)(0x42DE4404UL))
#define bFM4_GPIO_DDR8_P1                         *((volatile  uint8_t *)(0x42DE4404UL))
#define bFM_GPIO_DDR8_P2                          *((volatile  uint8_t *)(0x42DE4408UL))
#define bFM4_GPIO_DDR8_P2                         *((volatile  uint8_t *)(0x42DE4408UL))
#define bFM_GPIO_DDR8_P3                          *((volatile  uint8_t *)(0x42DE440CUL))
#define bFM4_GPIO_DDR8_P3                         *((volatile  uint8_t *)(0x42DE440CUL))

#define bFM_GPIO_DDR9_P0                          *((volatile  uint8_t *)(0x42DE4480UL))
#define bFM4_GPIO_DDR9_P0                         *((volatile  uint8_t *)(0x42DE4480UL))
#define bFM_GPIO_DDR9_P1                          *((volatile  uint8_t *)(0x42DE4484UL))
#define bFM4_GPIO_DDR9_P1                         *((volatile  uint8_t *)(0x42DE4484UL))
#define bFM_GPIO_DDR9_P2                          *((volatile  uint8_t *)(0x42DE4488UL))
#define bFM4_GPIO_DDR9_P2                         *((volatile  uint8_t *)(0x42DE4488UL))
#define bFM_GPIO_DDR9_P3                          *((volatile  uint8_t *)(0x42DE448CUL))
#define bFM4_GPIO_DDR9_P3                         *((volatile  uint8_t *)(0x42DE448CUL))
#define bFM_GPIO_DDR9_P4                          *((volatile  uint8_t *)(0x42DE4490UL))
#define bFM4_GPIO_DDR9_P4                         *((volatile  uint8_t *)(0x42DE4490UL))
#define bFM_GPIO_DDR9_P5                          *((volatile  uint8_t *)(0x42DE4494UL))
#define bFM4_GPIO_DDR9_P5                         *((volatile  uint8_t *)(0x42DE4494UL))

#define bFM_GPIO_DDRA_P0                          *((volatile  uint8_t *)(0x42DE4500UL))
#define bFM4_GPIO_DDRA_P0                         *((volatile  uint8_t *)(0x42DE4500UL))
#define bFM_GPIO_DDRA_P1                          *((volatile  uint8_t *)(0x42DE4504UL))
#define bFM4_GPIO_DDRA_P1                         *((volatile  uint8_t *)(0x42DE4504UL))
#define bFM_GPIO_DDRA_P2                          *((volatile  uint8_t *)(0x42DE4508UL))
#define bFM4_GPIO_DDRA_P2                         *((volatile  uint8_t *)(0x42DE4508UL))
#define bFM_GPIO_DDRA_P3                          *((volatile  uint8_t *)(0x42DE450CUL))
#define bFM4_GPIO_DDRA_P3                         *((volatile  uint8_t *)(0x42DE450CUL))
#define bFM_GPIO_DDRA_P4                          *((volatile  uint8_t *)(0x42DE4510UL))
#define bFM4_GPIO_DDRA_P4                         *((volatile  uint8_t *)(0x42DE4510UL))
#define bFM_GPIO_DDRA_P5                          *((volatile  uint8_t *)(0x42DE4514UL))
#define bFM4_GPIO_DDRA_P5                         *((volatile  uint8_t *)(0x42DE4514UL))
#define bFM_GPIO_DDRA_P6                          *((volatile  uint8_t *)(0x42DE4518UL))
#define bFM4_GPIO_DDRA_P6                         *((volatile  uint8_t *)(0x42DE4518UL))
#define bFM_GPIO_DDRA_P7                          *((volatile  uint8_t *)(0x42DE451CUL))
#define bFM4_GPIO_DDRA_P7                         *((volatile  uint8_t *)(0x42DE451CUL))
#define bFM_GPIO_DDRA_P8                          *((volatile  uint8_t *)(0x42DE4520UL))
#define bFM4_GPIO_DDRA_P8                         *((volatile  uint8_t *)(0x42DE4520UL))
#define bFM_GPIO_DDRA_P9                          *((volatile  uint8_t *)(0x42DE4524UL))
#define bFM4_GPIO_DDRA_P9                         *((volatile  uint8_t *)(0x42DE4524UL))
#define bFM_GPIO_DDRA_PA                          *((volatile  uint8_t *)(0x42DE4528UL))
#define bFM4_GPIO_DDRA_PA                         *((volatile  uint8_t *)(0x42DE4528UL))
#define bFM_GPIO_DDRA_PB                          *((volatile  uint8_t *)(0x42DE452CUL))
#define bFM4_GPIO_DDRA_PB                         *((volatile  uint8_t *)(0x42DE452CUL))
#define bFM_GPIO_DDRA_PC                          *((volatile  uint8_t *)(0x42DE4530UL))
#define bFM4_GPIO_DDRA_PC                         *((volatile  uint8_t *)(0x42DE4530UL))
#define bFM_GPIO_DDRA_PD                          *((volatile  uint8_t *)(0x42DE4534UL))
#define bFM4_GPIO_DDRA_PD                         *((volatile  uint8_t *)(0x42DE4534UL))
#define bFM_GPIO_DDRA_PE                          *((volatile  uint8_t *)(0x42DE4538UL))
#define bFM4_GPIO_DDRA_PE                         *((volatile  uint8_t *)(0x42DE4538UL))
#define bFM_GPIO_DDRA_PF                          *((volatile  uint8_t *)(0x42DE453CUL))
#define bFM4_GPIO_DDRA_PF                         *((volatile  uint8_t *)(0x42DE453CUL))

#define bFM_GPIO_DDRB_P0                          *((volatile  uint8_t *)(0x42DE4580UL))
#define bFM4_GPIO_DDRB_P0                         *((volatile  uint8_t *)(0x42DE4580UL))
#define bFM_GPIO_DDRB_P1                          *((volatile  uint8_t *)(0x42DE4584UL))
#define bFM4_GPIO_DDRB_P1                         *((volatile  uint8_t *)(0x42DE4584UL))
#define bFM_GPIO_DDRB_P2                          *((volatile  uint8_t *)(0x42DE4588UL))
#define bFM4_GPIO_DDRB_P2                         *((volatile  uint8_t *)(0x42DE4588UL))
#define bFM_GPIO_DDRB_P3                          *((volatile  uint8_t *)(0x42DE458CUL))
#define bFM4_GPIO_DDRB_P3                         *((volatile  uint8_t *)(0x42DE458CUL))
#define bFM_GPIO_DDRB_P4                          *((volatile  uint8_t *)(0x42DE4590UL))
#define bFM4_GPIO_DDRB_P4                         *((volatile  uint8_t *)(0x42DE4590UL))
#define bFM_GPIO_DDRB_P5                          *((volatile  uint8_t *)(0x42DE4594UL))
#define bFM4_GPIO_DDRB_P5                         *((volatile  uint8_t *)(0x42DE4594UL))
#define bFM_GPIO_DDRB_P6                          *((volatile  uint8_t *)(0x42DE4598UL))
#define bFM4_GPIO_DDRB_P6                         *((volatile  uint8_t *)(0x42DE4598UL))
#define bFM_GPIO_DDRB_P7                          *((volatile  uint8_t *)(0x42DE459CUL))
#define bFM4_GPIO_DDRB_P7                         *((volatile  uint8_t *)(0x42DE459CUL))

#define bFM_GPIO_DDRC_P0                          *((volatile  uint8_t *)(0x42DE4600UL))
#define bFM4_GPIO_DDRC_P0                         *((volatile  uint8_t *)(0x42DE4600UL))
#define bFM_GPIO_DDRC_P1                          *((volatile  uint8_t *)(0x42DE4604UL))
#define bFM4_GPIO_DDRC_P1                         *((volatile  uint8_t *)(0x42DE4604UL))
#define bFM_GPIO_DDRC_P2                          *((volatile  uint8_t *)(0x42DE4608UL))
#define bFM4_GPIO_DDRC_P2                         *((volatile  uint8_t *)(0x42DE4608UL))
#define bFM_GPIO_DDRC_P3                          *((volatile  uint8_t *)(0x42DE460CUL))
#define bFM4_GPIO_DDRC_P3                         *((volatile  uint8_t *)(0x42DE460CUL))
#define bFM_GPIO_DDRC_P4                          *((volatile  uint8_t *)(0x42DE4610UL))
#define bFM4_GPIO_DDRC_P4                         *((volatile  uint8_t *)(0x42DE4610UL))
#define bFM_GPIO_DDRC_P5                          *((volatile  uint8_t *)(0x42DE4614UL))
#define bFM4_GPIO_DDRC_P5                         *((volatile  uint8_t *)(0x42DE4614UL))
#define bFM_GPIO_DDRC_P6                          *((volatile  uint8_t *)(0x42DE4618UL))
#define bFM4_GPIO_DDRC_P6                         *((volatile  uint8_t *)(0x42DE4618UL))
#define bFM_GPIO_DDRC_P7                          *((volatile  uint8_t *)(0x42DE461CUL))
#define bFM4_GPIO_DDRC_P7                         *((volatile  uint8_t *)(0x42DE461CUL))
#define bFM_GPIO_DDRC_P8                          *((volatile  uint8_t *)(0x42DE4620UL))
#define bFM4_GPIO_DDRC_P8                         *((volatile  uint8_t *)(0x42DE4620UL))
#define bFM_GPIO_DDRC_P9                          *((volatile  uint8_t *)(0x42DE4624UL))
#define bFM4_GPIO_DDRC_P9                         *((volatile  uint8_t *)(0x42DE4624UL))
#define bFM_GPIO_DDRC_PA                          *((volatile  uint8_t *)(0x42DE4628UL))
#define bFM4_GPIO_DDRC_PA                         *((volatile  uint8_t *)(0x42DE4628UL))
#define bFM_GPIO_DDRC_PB                          *((volatile  uint8_t *)(0x42DE462CUL))
#define bFM4_GPIO_DDRC_PB                         *((volatile  uint8_t *)(0x42DE462CUL))
#define bFM_GPIO_DDRC_PC                          *((volatile  uint8_t *)(0x42DE4630UL))
#define bFM4_GPIO_DDRC_PC                         *((volatile  uint8_t *)(0x42DE4630UL))
#define bFM_GPIO_DDRC_PD                          *((volatile  uint8_t *)(0x42DE4634UL))
#define bFM4_GPIO_DDRC_PD                         *((volatile  uint8_t *)(0x42DE4634UL))
#define bFM_GPIO_DDRC_PE                          *((volatile  uint8_t *)(0x42DE4638UL))
#define bFM4_GPIO_DDRC_PE                         *((volatile  uint8_t *)(0x42DE4638UL))
#define bFM_GPIO_DDRC_PF                          *((volatile  uint8_t *)(0x42DE463CUL))
#define bFM4_GPIO_DDRC_PF                         *((volatile  uint8_t *)(0x42DE463CUL))

#define bFM_GPIO_DDRD_P0                          *((volatile  uint8_t *)(0x42DE4680UL))
#define bFM4_GPIO_DDRD_P0                         *((volatile  uint8_t *)(0x42DE4680UL))
#define bFM_GPIO_DDRD_P1                          *((volatile  uint8_t *)(0x42DE4684UL))
#define bFM4_GPIO_DDRD_P1                         *((volatile  uint8_t *)(0x42DE4684UL))
#define bFM_GPIO_DDRD_P2                          *((volatile  uint8_t *)(0x42DE4688UL))
#define bFM4_GPIO_DDRD_P2                         *((volatile  uint8_t *)(0x42DE4688UL))

#define bFM_GPIO_DDRE_P0                          *((volatile  uint8_t *)(0x42DE4700UL))
#define bFM4_GPIO_DDRE_P0                         *((volatile  uint8_t *)(0x42DE4700UL))
#define bFM_GPIO_DDRE_P2                          *((volatile  uint8_t *)(0x42DE4708UL))
#define bFM4_GPIO_DDRE_P2                         *((volatile  uint8_t *)(0x42DE4708UL))
#define bFM_GPIO_DDRE_P3                          *((volatile  uint8_t *)(0x42DE470CUL))
#define bFM4_GPIO_DDRE_P3                         *((volatile  uint8_t *)(0x42DE470CUL))

#define bFM_GPIO_DDRF_P0                          *((volatile  uint8_t *)(0x42DE4780UL))
#define bFM4_GPIO_DDRF_P0                         *((volatile  uint8_t *)(0x42DE4780UL))
#define bFM_GPIO_DDRF_P1                          *((volatile  uint8_t *)(0x42DE4784UL))
#define bFM4_GPIO_DDRF_P1                         *((volatile  uint8_t *)(0x42DE4784UL))
#define bFM_GPIO_DDRF_P2                          *((volatile  uint8_t *)(0x42DE4788UL))
#define bFM4_GPIO_DDRF_P2                         *((volatile  uint8_t *)(0x42DE4788UL))
#define bFM_GPIO_DDRF_P3                          *((volatile  uint8_t *)(0x42DE478CUL))
#define bFM4_GPIO_DDRF_P3                         *((volatile  uint8_t *)(0x42DE478CUL))
#define bFM_GPIO_DDRF_P4                          *((volatile  uint8_t *)(0x42DE4790UL))
#define bFM4_GPIO_DDRF_P4                         *((volatile  uint8_t *)(0x42DE4790UL))
#define bFM_GPIO_DDRF_P5                          *((volatile  uint8_t *)(0x42DE4794UL))
#define bFM4_GPIO_DDRF_P5                         *((volatile  uint8_t *)(0x42DE4794UL))
#define bFM_GPIO_DDRF_P6                          *((volatile  uint8_t *)(0x42DE4798UL))
#define bFM4_GPIO_DDRF_P6                         *((volatile  uint8_t *)(0x42DE4798UL))
#define bFM_GPIO_DDRF_P7                          *((volatile  uint8_t *)(0x42DE479CUL))
#define bFM4_GPIO_DDRF_P7                         *((volatile  uint8_t *)(0x42DE479CUL))

#define bFM_GPIO_EPFR00_NMIS                      *((volatile  uint8_t *)(0x42DEC000UL))
#define bFM4_GPIO_EPFR00_NMIS                     *((volatile  uint8_t *)(0x42DEC000UL))
#define bFM_GPIO_EPFR00_USBP0E                    *((volatile  uint8_t *)(0x42DEC024UL))
#define bFM4_GPIO_EPFR00_USBP0E                   *((volatile  uint8_t *)(0x42DEC024UL))
#define bFM_GPIO_EPFR00_USBP1E                    *((volatile  uint8_t *)(0x42DEC034UL))
#define bFM4_GPIO_EPFR00_USBP1E                   *((volatile  uint8_t *)(0x42DEC034UL))
#define bFM_GPIO_EPFR00_JTAGEN0B                  *((volatile  uint8_t *)(0x42DEC040UL))
#define bFM4_GPIO_EPFR00_JTAGEN0B                 *((volatile  uint8_t *)(0x42DEC040UL))
#define bFM_GPIO_EPFR00_JTAGEN1S                  *((volatile  uint8_t *)(0x42DEC044UL))
#define bFM4_GPIO_EPFR00_JTAGEN1S                 *((volatile  uint8_t *)(0x42DEC044UL))
#define bFM_GPIO_EPFR00_TRC0E                     *((volatile  uint8_t *)(0x42DEC060UL))
#define bFM4_GPIO_EPFR00_TRC0E                    *((volatile  uint8_t *)(0x42DEC060UL))
#define bFM_GPIO_EPFR00_TRC1E                     *((volatile  uint8_t *)(0x42DEC064UL))
#define bFM4_GPIO_EPFR00_TRC1E                    *((volatile  uint8_t *)(0x42DEC064UL))
#define bFM_GPIO_EPFR00_TRC2E                     *((volatile  uint8_t *)(0x42DEC068UL))
#define bFM4_GPIO_EPFR00_TRC2E                    *((volatile  uint8_t *)(0x42DEC068UL))
#define bFM_GPIO_EPFR00_TRC3E                     *((volatile  uint8_t *)(0x42DEC06CUL))
#define bFM4_GPIO_EPFR00_TRC3E                    *((volatile  uint8_t *)(0x42DEC06CUL))

#define bFM_GPIO_EPFR01_DTTI0C                    *((volatile  uint8_t *)(0x42DEC0B0UL))
#define bFM4_GPIO_EPFR01_DTTI0C                   *((volatile  uint8_t *)(0x42DEC0B0UL))

#define bFM_GPIO_EPFR02_DTTI1C                    *((volatile  uint8_t *)(0x42DEC130UL))
#define bFM4_GPIO_EPFR02_DTTI1C                   *((volatile  uint8_t *)(0x42DEC130UL))

#define bFM_GPIO_EPFR03_DTTI2C                    *((volatile  uint8_t *)(0x42DEC1B0UL))
#define bFM4_GPIO_EPFR03_DTTI2C                   *((volatile  uint8_t *)(0x42DEC1B0UL))

#define bFM_GPIO_EPFR10_UEDEFB                    *((volatile  uint8_t *)(0x42DEC500UL))
#define bFM4_GPIO_EPFR10_UEDEFB                   *((volatile  uint8_t *)(0x42DEC500UL))
#define bFM_GPIO_EPFR10_UEDTHB                    *((volatile  uint8_t *)(0x42DEC504UL))
#define bFM4_GPIO_EPFR10_UEDTHB                   *((volatile  uint8_t *)(0x42DEC504UL))
#define bFM_GPIO_EPFR10_UECLKE                    *((volatile  uint8_t *)(0x42DEC508UL))
#define bFM4_GPIO_EPFR10_UECLKE                   *((volatile  uint8_t *)(0x42DEC508UL))
#define bFM_GPIO_EPFR10_UEWEXE                    *((volatile  uint8_t *)(0x42DEC50CUL))
#define bFM4_GPIO_EPFR10_UEWEXE                   *((volatile  uint8_t *)(0x42DEC50CUL))
#define bFM_GPIO_EPFR10_UEDQME                    *((volatile  uint8_t *)(0x42DEC510UL))
#define bFM4_GPIO_EPFR10_UEDQME                   *((volatile  uint8_t *)(0x42DEC510UL))
#define bFM_GPIO_EPFR10_UEOEXE                    *((volatile  uint8_t *)(0x42DEC514UL))
#define bFM4_GPIO_EPFR10_UEOEXE                   *((volatile  uint8_t *)(0x42DEC514UL))
#define bFM_GPIO_EPFR10_UEFLSE                    *((volatile  uint8_t *)(0x42DEC518UL))
#define bFM4_GPIO_EPFR10_UEFLSE                   *((volatile  uint8_t *)(0x42DEC518UL))
#define bFM_GPIO_EPFR10_UECS1E                    *((volatile  uint8_t *)(0x42DEC51CUL))
#define bFM4_GPIO_EPFR10_UECS1E                   *((volatile  uint8_t *)(0x42DEC51CUL))
#define bFM_GPIO_EPFR10_UECS2E                    *((volatile  uint8_t *)(0x42DEC520UL))
#define bFM4_GPIO_EPFR10_UECS2E                   *((volatile  uint8_t *)(0x42DEC520UL))
#define bFM_GPIO_EPFR10_UECS3E                    *((volatile  uint8_t *)(0x42DEC524UL))
#define bFM4_GPIO_EPFR10_UECS3E                   *((volatile  uint8_t *)(0x42DEC524UL))
#define bFM_GPIO_EPFR10_UECS4E                    *((volatile  uint8_t *)(0x42DEC528UL))
#define bFM4_GPIO_EPFR10_UECS4E                   *((volatile  uint8_t *)(0x42DEC528UL))
#define bFM_GPIO_EPFR10_UECS5E                    *((volatile  uint8_t *)(0x42DEC52CUL))
#define bFM4_GPIO_EPFR10_UECS5E                   *((volatile  uint8_t *)(0x42DEC52CUL))
#define bFM_GPIO_EPFR10_UECS6E                    *((volatile  uint8_t *)(0x42DEC530UL))
#define bFM4_GPIO_EPFR10_UECS6E                   *((volatile  uint8_t *)(0x42DEC530UL))
#define bFM_GPIO_EPFR10_UECS7E                    *((volatile  uint8_t *)(0x42DEC534UL))
#define bFM4_GPIO_EPFR10_UECS7E                   *((volatile  uint8_t *)(0x42DEC534UL))
#define bFM_GPIO_EPFR10_UEAOOE                    *((volatile  uint8_t *)(0x42DEC538UL))
#define bFM4_GPIO_EPFR10_UEAOOE                   *((volatile  uint8_t *)(0x42DEC538UL))
#define bFM_GPIO_EPFR10_UEA08E                    *((volatile  uint8_t *)(0x42DEC53CUL))
#define bFM4_GPIO_EPFR10_UEA08E                   *((volatile  uint8_t *)(0x42DEC53CUL))
#define bFM_GPIO_EPFR10_UEA09E                    *((volatile  uint8_t *)(0x42DEC540UL))
#define bFM4_GPIO_EPFR10_UEA09E                   *((volatile  uint8_t *)(0x42DEC540UL))
#define bFM_GPIO_EPFR10_UEA10E                    *((volatile  uint8_t *)(0x42DEC544UL))
#define bFM4_GPIO_EPFR10_UEA10E                   *((volatile  uint8_t *)(0x42DEC544UL))
#define bFM_GPIO_EPFR10_UEA11E                    *((volatile  uint8_t *)(0x42DEC548UL))
#define bFM4_GPIO_EPFR10_UEA11E                   *((volatile  uint8_t *)(0x42DEC548UL))
#define bFM_GPIO_EPFR10_UEA12E                    *((volatile  uint8_t *)(0x42DEC54CUL))
#define bFM4_GPIO_EPFR10_UEA12E                   *((volatile  uint8_t *)(0x42DEC54CUL))
#define bFM_GPIO_EPFR10_UEA13E                    *((volatile  uint8_t *)(0x42DEC550UL))
#define bFM4_GPIO_EPFR10_UEA13E                   *((volatile  uint8_t *)(0x42DEC550UL))
#define bFM_GPIO_EPFR10_UEA14E                    *((volatile  uint8_t *)(0x42DEC554UL))
#define bFM4_GPIO_EPFR10_UEA14E                   *((volatile  uint8_t *)(0x42DEC554UL))
#define bFM_GPIO_EPFR10_UEA15E                    *((volatile  uint8_t *)(0x42DEC558UL))
#define bFM4_GPIO_EPFR10_UEA15E                   *((volatile  uint8_t *)(0x42DEC558UL))
#define bFM_GPIO_EPFR10_UEA16E                    *((volatile  uint8_t *)(0x42DEC55CUL))
#define bFM4_GPIO_EPFR10_UEA16E                   *((volatile  uint8_t *)(0x42DEC55CUL))
#define bFM_GPIO_EPFR10_UEA17E                    *((volatile  uint8_t *)(0x42DEC560UL))
#define bFM4_GPIO_EPFR10_UEA17E                   *((volatile  uint8_t *)(0x42DEC560UL))
#define bFM_GPIO_EPFR10_UEA18E                    *((volatile  uint8_t *)(0x42DEC564UL))
#define bFM4_GPIO_EPFR10_UEA18E                   *((volatile  uint8_t *)(0x42DEC564UL))
#define bFM_GPIO_EPFR10_UEA19E                    *((volatile  uint8_t *)(0x42DEC568UL))
#define bFM4_GPIO_EPFR10_UEA19E                   *((volatile  uint8_t *)(0x42DEC568UL))
#define bFM_GPIO_EPFR10_UEA20E                    *((volatile  uint8_t *)(0x42DEC56CUL))
#define bFM4_GPIO_EPFR10_UEA20E                   *((volatile  uint8_t *)(0x42DEC56CUL))
#define bFM_GPIO_EPFR10_UEA21E                    *((volatile  uint8_t *)(0x42DEC570UL))
#define bFM4_GPIO_EPFR10_UEA21E                   *((volatile  uint8_t *)(0x42DEC570UL))
#define bFM_GPIO_EPFR10_UEA22E                    *((volatile  uint8_t *)(0x42DEC574UL))
#define bFM4_GPIO_EPFR10_UEA22E                   *((volatile  uint8_t *)(0x42DEC574UL))
#define bFM_GPIO_EPFR10_UEA23E                    *((volatile  uint8_t *)(0x42DEC578UL))
#define bFM4_GPIO_EPFR10_UEA23E                   *((volatile  uint8_t *)(0x42DEC578UL))
#define bFM_GPIO_EPFR10_UEA24E                    *((volatile  uint8_t *)(0x42DEC57CUL))
#define bFM4_GPIO_EPFR10_UEA24E                   *((volatile  uint8_t *)(0x42DEC57CUL))

#define bFM_GPIO_EPFR11_UEALEE                    *((volatile  uint8_t *)(0x42DEC580UL))
#define bFM4_GPIO_EPFR11_UEALEE                   *((volatile  uint8_t *)(0x42DEC580UL))
#define bFM_GPIO_EPFR11_UECS0E                    *((volatile  uint8_t *)(0x42DEC584UL))
#define bFM4_GPIO_EPFR11_UECS0E                   *((volatile  uint8_t *)(0x42DEC584UL))
#define bFM_GPIO_EPFR11_UEA01E                    *((volatile  uint8_t *)(0x42DEC588UL))
#define bFM4_GPIO_EPFR11_UEA01E                   *((volatile  uint8_t *)(0x42DEC588UL))
#define bFM_GPIO_EPFR11_UEA02E                    *((volatile  uint8_t *)(0x42DEC58CUL))
#define bFM4_GPIO_EPFR11_UEA02E                   *((volatile  uint8_t *)(0x42DEC58CUL))
#define bFM_GPIO_EPFR11_UEA03E                    *((volatile  uint8_t *)(0x42DEC590UL))
#define bFM4_GPIO_EPFR11_UEA03E                   *((volatile  uint8_t *)(0x42DEC590UL))
#define bFM_GPIO_EPFR11_UEA04E                    *((volatile  uint8_t *)(0x42DEC594UL))
#define bFM4_GPIO_EPFR11_UEA04E                   *((volatile  uint8_t *)(0x42DEC594UL))
#define bFM_GPIO_EPFR11_UEA05E                    *((volatile  uint8_t *)(0x42DEC598UL))
#define bFM4_GPIO_EPFR11_UEA05E                   *((volatile  uint8_t *)(0x42DEC598UL))
#define bFM_GPIO_EPFR11_UEA06E                    *((volatile  uint8_t *)(0x42DEC59CUL))
#define bFM4_GPIO_EPFR11_UEA06E                   *((volatile  uint8_t *)(0x42DEC59CUL))
#define bFM_GPIO_EPFR11_UEA07E                    *((volatile  uint8_t *)(0x42DEC5A0UL))
#define bFM4_GPIO_EPFR11_UEA07E                   *((volatile  uint8_t *)(0x42DEC5A0UL))
#define bFM_GPIO_EPFR11_UED00B                    *((volatile  uint8_t *)(0x42DEC5A4UL))
#define bFM4_GPIO_EPFR11_UED00B                   *((volatile  uint8_t *)(0x42DEC5A4UL))
#define bFM_GPIO_EPFR11_UED01B                    *((volatile  uint8_t *)(0x42DEC5A8UL))
#define bFM4_GPIO_EPFR11_UED01B                   *((volatile  uint8_t *)(0x42DEC5A8UL))
#define bFM_GPIO_EPFR11_UED02B                    *((volatile  uint8_t *)(0x42DEC5ACUL))
#define bFM4_GPIO_EPFR11_UED02B                   *((volatile  uint8_t *)(0x42DEC5ACUL))
#define bFM_GPIO_EPFR11_UED03B                    *((volatile  uint8_t *)(0x42DEC5B0UL))
#define bFM4_GPIO_EPFR11_UED03B                   *((volatile  uint8_t *)(0x42DEC5B0UL))
#define bFM_GPIO_EPFR11_UED04B                    *((volatile  uint8_t *)(0x42DEC5B4UL))
#define bFM4_GPIO_EPFR11_UED04B                   *((volatile  uint8_t *)(0x42DEC5B4UL))
#define bFM_GPIO_EPFR11_UED05B                    *((volatile  uint8_t *)(0x42DEC5B8UL))
#define bFM4_GPIO_EPFR11_UED05B                   *((volatile  uint8_t *)(0x42DEC5B8UL))
#define bFM_GPIO_EPFR11_UED06B                    *((volatile  uint8_t *)(0x42DEC5BCUL))
#define bFM4_GPIO_EPFR11_UED06B                   *((volatile  uint8_t *)(0x42DEC5BCUL))
#define bFM_GPIO_EPFR11_UED07B                    *((volatile  uint8_t *)(0x42DEC5C0UL))
#define bFM4_GPIO_EPFR11_UED07B                   *((volatile  uint8_t *)(0x42DEC5C0UL))
#define bFM_GPIO_EPFR11_UED08B                    *((volatile  uint8_t *)(0x42DEC5C4UL))
#define bFM4_GPIO_EPFR11_UED08B                   *((volatile  uint8_t *)(0x42DEC5C4UL))
#define bFM_GPIO_EPFR11_UED09B                    *((volatile  uint8_t *)(0x42DEC5C8UL))
#define bFM4_GPIO_EPFR11_UED09B                   *((volatile  uint8_t *)(0x42DEC5C8UL))
#define bFM_GPIO_EPFR11_UED10B                    *((volatile  uint8_t *)(0x42DEC5CCUL))
#define bFM4_GPIO_EPFR11_UED10B                   *((volatile  uint8_t *)(0x42DEC5CCUL))
#define bFM_GPIO_EPFR11_UED11B                    *((volatile  uint8_t *)(0x42DEC5D0UL))
#define bFM4_GPIO_EPFR11_UED11B                   *((volatile  uint8_t *)(0x42DEC5D0UL))
#define bFM_GPIO_EPFR11_UED12B                    *((volatile  uint8_t *)(0x42DEC5D4UL))
#define bFM4_GPIO_EPFR11_UED12B                   *((volatile  uint8_t *)(0x42DEC5D4UL))
#define bFM_GPIO_EPFR11_UED13B                    *((volatile  uint8_t *)(0x42DEC5D8UL))
#define bFM4_GPIO_EPFR11_UED13B                   *((volatile  uint8_t *)(0x42DEC5D8UL))
#define bFM_GPIO_EPFR11_UED14B                    *((volatile  uint8_t *)(0x42DEC5DCUL))
#define bFM4_GPIO_EPFR11_UED14B                   *((volatile  uint8_t *)(0x42DEC5DCUL))
#define bFM_GPIO_EPFR11_UED15B                    *((volatile  uint8_t *)(0x42DEC5E0UL))
#define bFM4_GPIO_EPFR11_UED15B                   *((volatile  uint8_t *)(0x42DEC5E0UL))
#define bFM_GPIO_EPFR11_UERLC                     *((volatile  uint8_t *)(0x42DEC5E4UL))
#define bFM4_GPIO_EPFR11_UERLC                    *((volatile  uint8_t *)(0x42DEC5E4UL))

#define bFM_GPIO_EPFR14_E_TD0E                    *((volatile  uint8_t *)(0x42DEC748UL))
#define bFM4_GPIO_EPFR14_E_TD0E                   *((volatile  uint8_t *)(0x42DEC748UL))
#define bFM_GPIO_EPFR14_E_TD1E                    *((volatile  uint8_t *)(0x42DEC74CUL))
#define bFM4_GPIO_EPFR14_E_TD1E                   *((volatile  uint8_t *)(0x42DEC74CUL))
#define bFM_GPIO_EPFR14_E_TE0E                    *((volatile  uint8_t *)(0x42DEC750UL))
#define bFM4_GPIO_EPFR14_E_TE0E                   *((volatile  uint8_t *)(0x42DEC750UL))
#define bFM_GPIO_EPFR14_E_TE1E                    *((volatile  uint8_t *)(0x42DEC754UL))
#define bFM4_GPIO_EPFR14_E_TE1E                   *((volatile  uint8_t *)(0x42DEC754UL))
#define bFM_GPIO_EPFR14_E_MC0E                    *((volatile  uint8_t *)(0x42DEC758UL))
#define bFM4_GPIO_EPFR14_E_MC0E                   *((volatile  uint8_t *)(0x42DEC758UL))
#define bFM_GPIO_EPFR14_E_MC1B                    *((volatile  uint8_t *)(0x42DEC75CUL))
#define bFM4_GPIO_EPFR14_E_MC1B                   *((volatile  uint8_t *)(0x42DEC75CUL))
#define bFM_GPIO_EPFR14_E_MD0B                    *((volatile  uint8_t *)(0x42DEC760UL))
#define bFM4_GPIO_EPFR14_E_MD0B                   *((volatile  uint8_t *)(0x42DEC760UL))
#define bFM_GPIO_EPFR14_E_MD1B                    *((volatile  uint8_t *)(0x42DEC764UL))
#define bFM4_GPIO_EPFR14_E_MD1B                   *((volatile  uint8_t *)(0x42DEC764UL))
#define bFM_GPIO_EPFR14_E_CKE                     *((volatile  uint8_t *)(0x42DEC768UL))
#define bFM4_GPIO_EPFR14_E_CKE                    *((volatile  uint8_t *)(0x42DEC768UL))
#define bFM_GPIO_EPFR14_E_PSE                     *((volatile  uint8_t *)(0x42DEC76CUL))
#define bFM4_GPIO_EPFR14_E_PSE                    *((volatile  uint8_t *)(0x42DEC76CUL))

#define bFM_GPIO_EPFR16_SFMPAC                    *((volatile  uint8_t *)(0x42DEC870UL))
#define bFM4_GPIO_EPFR16_SFMPAC                   *((volatile  uint8_t *)(0x42DEC870UL))
#define bFM_GPIO_EPFR16_SFMPBC                    *((volatile  uint8_t *)(0x42DEC874UL))
#define bFM4_GPIO_EPFR16_SFMPBC                   *((volatile  uint8_t *)(0x42DEC874UL))

#define bFM_GPIO_EPFR20_UESMCKE                   *((volatile  uint8_t *)(0x42DECA00UL))
#define bFM4_GPIO_EPFR20_UESMCKE                  *((volatile  uint8_t *)(0x42DECA00UL))
#define bFM_GPIO_EPFR20_UESMCEE                   *((volatile  uint8_t *)(0x42DECA04UL))
#define bFM4_GPIO_EPFR20_UESMCEE                  *((volatile  uint8_t *)(0x42DECA04UL))
#define bFM_GPIO_EPFR20_UERASE                    *((volatile  uint8_t *)(0x42DECA08UL))
#define bFM4_GPIO_EPFR20_UERASE                   *((volatile  uint8_t *)(0x42DECA08UL))
#define bFM_GPIO_EPFR20_UECASE                    *((volatile  uint8_t *)(0x42DECA0CUL))
#define bFM4_GPIO_EPFR20_UECASE                   *((volatile  uint8_t *)(0x42DECA0CUL))
#define bFM_GPIO_EPFR20_UEDWEXE                   *((volatile  uint8_t *)(0x42DECA10UL))
#define bFM4_GPIO_EPFR20_UEDWEXE                  *((volatile  uint8_t *)(0x42DECA10UL))
#define bFM_GPIO_EPFR20_UECSXE                    *((volatile  uint8_t *)(0x42DECA14UL))
#define bFM4_GPIO_EPFR20_UECSXE                   *((volatile  uint8_t *)(0x42DECA14UL))
#define bFM_GPIO_EPFR20_UEDQM2E                   *((volatile  uint8_t *)(0x42DECA18UL))
#define bFM4_GPIO_EPFR20_UEDQM2E                  *((volatile  uint8_t *)(0x42DECA18UL))
#define bFM_GPIO_EPFR20_UEDQM3E                   *((volatile  uint8_t *)(0x42DECA1CUL))
#define bFM4_GPIO_EPFR20_UEDQM3E                  *((volatile  uint8_t *)(0x42DECA1CUL))
#define bFM_GPIO_EPFR20_UEDTHHB                   *((volatile  uint8_t *)(0x42DECA20UL))
#define bFM4_GPIO_EPFR20_UEDTHHB                  *((volatile  uint8_t *)(0x42DECA20UL))
#define bFM_GPIO_EPFR20_UED16B                    *((volatile  uint8_t *)(0x42DECA24UL))
#define bFM4_GPIO_EPFR20_UED16B                   *((volatile  uint8_t *)(0x42DECA24UL))
#define bFM_GPIO_EPFR20_UED17B                    *((volatile  uint8_t *)(0x42DECA28UL))
#define bFM4_GPIO_EPFR20_UED17B                   *((volatile  uint8_t *)(0x42DECA28UL))
#define bFM_GPIO_EPFR20_UED18B                    *((volatile  uint8_t *)(0x42DECA2CUL))
#define bFM4_GPIO_EPFR20_UED18B                   *((volatile  uint8_t *)(0x42DECA2CUL))
#define bFM_GPIO_EPFR20_UED19B                    *((volatile  uint8_t *)(0x42DECA30UL))
#define bFM4_GPIO_EPFR20_UED19B                   *((volatile  uint8_t *)(0x42DECA30UL))
#define bFM_GPIO_EPFR20_UED20B                    *((volatile  uint8_t *)(0x42DECA34UL))
#define bFM4_GPIO_EPFR20_UED20B                   *((volatile  uint8_t *)(0x42DECA34UL))
#define bFM_GPIO_EPFR20_UED21B                    *((volatile  uint8_t *)(0x42DECA38UL))
#define bFM4_GPIO_EPFR20_UED21B                   *((volatile  uint8_t *)(0x42DECA38UL))
#define bFM_GPIO_EPFR20_UED22B                    *((volatile  uint8_t *)(0x42DECA3CUL))
#define bFM4_GPIO_EPFR20_UED22B                   *((volatile  uint8_t *)(0x42DECA3CUL))
#define bFM_GPIO_EPFR20_UED23B                    *((volatile  uint8_t *)(0x42DECA40UL))
#define bFM4_GPIO_EPFR20_UED23B                   *((volatile  uint8_t *)(0x42DECA40UL))
#define bFM_GPIO_EPFR20_UED24B                    *((volatile  uint8_t *)(0x42DECA44UL))
#define bFM4_GPIO_EPFR20_UED24B                   *((volatile  uint8_t *)(0x42DECA44UL))
#define bFM_GPIO_EPFR20_UED25B                    *((volatile  uint8_t *)(0x42DECA48UL))
#define bFM4_GPIO_EPFR20_UED25B                   *((volatile  uint8_t *)(0x42DECA48UL))
#define bFM_GPIO_EPFR20_UED26B                    *((volatile  uint8_t *)(0x42DECA4CUL))
#define bFM4_GPIO_EPFR20_UED26B                   *((volatile  uint8_t *)(0x42DECA4CUL))
#define bFM_GPIO_EPFR20_UED27B                    *((volatile  uint8_t *)(0x42DECA50UL))
#define bFM4_GPIO_EPFR20_UED27B                   *((volatile  uint8_t *)(0x42DECA50UL))
#define bFM_GPIO_EPFR20_UED28B                    *((volatile  uint8_t *)(0x42DECA54UL))
#define bFM4_GPIO_EPFR20_UED28B                   *((volatile  uint8_t *)(0x42DECA54UL))
#define bFM_GPIO_EPFR20_UED29B                    *((volatile  uint8_t *)(0x42DECA58UL))
#define bFM4_GPIO_EPFR20_UED29B                   *((volatile  uint8_t *)(0x42DECA58UL))
#define bFM_GPIO_EPFR20_UED30B                    *((volatile  uint8_t *)(0x42DECA5CUL))
#define bFM4_GPIO_EPFR20_UED30B                   *((volatile  uint8_t *)(0x42DECA5CUL))
#define bFM_GPIO_EPFR20_UED31B                    *((volatile  uint8_t *)(0x42DECA60UL))
#define bFM4_GPIO_EPFR20_UED31B                   *((volatile  uint8_t *)(0x42DECA60UL))

#define bFM_GPIO_PCR0_P0                          *((volatile  uint8_t *)(0x42DE2000UL))
#define bFM4_GPIO_PCR0_P0                         *((volatile  uint8_t *)(0x42DE2000UL))
#define bFM_GPIO_PCR0_P1                          *((volatile  uint8_t *)(0x42DE2004UL))
#define bFM4_GPIO_PCR0_P1                         *((volatile  uint8_t *)(0x42DE2004UL))
#define bFM_GPIO_PCR0_P2                          *((volatile  uint8_t *)(0x42DE2008UL))
#define bFM4_GPIO_PCR0_P2                         *((volatile  uint8_t *)(0x42DE2008UL))
#define bFM_GPIO_PCR0_P3                          *((volatile  uint8_t *)(0x42DE200CUL))
#define bFM4_GPIO_PCR0_P3                         *((volatile  uint8_t *)(0x42DE200CUL))
#define bFM_GPIO_PCR0_P4                          *((volatile  uint8_t *)(0x42DE2010UL))
#define bFM4_GPIO_PCR0_P4                         *((volatile  uint8_t *)(0x42DE2010UL))
#define bFM_GPIO_PCR0_P8                          *((volatile  uint8_t *)(0x42DE2020UL))
#define bFM4_GPIO_PCR0_P8                         *((volatile  uint8_t *)(0x42DE2020UL))
#define bFM_GPIO_PCR0_P9                          *((volatile  uint8_t *)(0x42DE2024UL))
#define bFM4_GPIO_PCR0_P9                         *((volatile  uint8_t *)(0x42DE2024UL))
#define bFM_GPIO_PCR0_PA                          *((volatile  uint8_t *)(0x42DE2028UL))
#define bFM4_GPIO_PCR0_PA                         *((volatile  uint8_t *)(0x42DE2028UL))

#define bFM_GPIO_PCR1_P0                          *((volatile  uint8_t *)(0x42DE2080UL))
#define bFM4_GPIO_PCR1_P0                         *((volatile  uint8_t *)(0x42DE2080UL))
#define bFM_GPIO_PCR1_P1                          *((volatile  uint8_t *)(0x42DE2084UL))
#define bFM4_GPIO_PCR1_P1                         *((volatile  uint8_t *)(0x42DE2084UL))
#define bFM_GPIO_PCR1_P2                          *((volatile  uint8_t *)(0x42DE2088UL))
#define bFM4_GPIO_PCR1_P2                         *((volatile  uint8_t *)(0x42DE2088UL))
#define bFM_GPIO_PCR1_P3                          *((volatile  uint8_t *)(0x42DE208CUL))
#define bFM4_GPIO_PCR1_P3                         *((volatile  uint8_t *)(0x42DE208CUL))
#define bFM_GPIO_PCR1_P4                          *((volatile  uint8_t *)(0x42DE2090UL))
#define bFM4_GPIO_PCR1_P4                         *((volatile  uint8_t *)(0x42DE2090UL))
#define bFM_GPIO_PCR1_P5                          *((volatile  uint8_t *)(0x42DE2094UL))
#define bFM4_GPIO_PCR1_P5                         *((volatile  uint8_t *)(0x42DE2094UL))
#define bFM_GPIO_PCR1_P6                          *((volatile  uint8_t *)(0x42DE2098UL))
#define bFM4_GPIO_PCR1_P6                         *((volatile  uint8_t *)(0x42DE2098UL))
#define bFM_GPIO_PCR1_P7                          *((volatile  uint8_t *)(0x42DE209CUL))
#define bFM4_GPIO_PCR1_P7                         *((volatile  uint8_t *)(0x42DE209CUL))
#define bFM_GPIO_PCR1_P8                          *((volatile  uint8_t *)(0x42DE20A0UL))
#define bFM4_GPIO_PCR1_P8                         *((volatile  uint8_t *)(0x42DE20A0UL))
#define bFM_GPIO_PCR1_P9                          *((volatile  uint8_t *)(0x42DE20A4UL))
#define bFM4_GPIO_PCR1_P9                         *((volatile  uint8_t *)(0x42DE20A4UL))
#define bFM_GPIO_PCR1_PA                          *((volatile  uint8_t *)(0x42DE20A8UL))
#define bFM4_GPIO_PCR1_PA                         *((volatile  uint8_t *)(0x42DE20A8UL))
#define bFM_GPIO_PCR1_PB                          *((volatile  uint8_t *)(0x42DE20ACUL))
#define bFM4_GPIO_PCR1_PB                         *((volatile  uint8_t *)(0x42DE20ACUL))
#define bFM_GPIO_PCR1_PC                          *((volatile  uint8_t *)(0x42DE20B0UL))
#define bFM4_GPIO_PCR1_PC                         *((volatile  uint8_t *)(0x42DE20B0UL))
#define bFM_GPIO_PCR1_PD                          *((volatile  uint8_t *)(0x42DE20B4UL))
#define bFM4_GPIO_PCR1_PD                         *((volatile  uint8_t *)(0x42DE20B4UL))
#define bFM_GPIO_PCR1_PE                          *((volatile  uint8_t *)(0x42DE20B8UL))
#define bFM4_GPIO_PCR1_PE                         *((volatile  uint8_t *)(0x42DE20B8UL))
#define bFM_GPIO_PCR1_PF                          *((volatile  uint8_t *)(0x42DE20BCUL))
#define bFM4_GPIO_PCR1_PF                         *((volatile  uint8_t *)(0x42DE20BCUL))

#define bFM_GPIO_PCR2_P0                          *((volatile  uint8_t *)(0x42DE2100UL))
#define bFM4_GPIO_PCR2_P0                         *((volatile  uint8_t *)(0x42DE2100UL))
#define bFM_GPIO_PCR2_P1                          *((volatile  uint8_t *)(0x42DE2104UL))
#define bFM4_GPIO_PCR2_P1                         *((volatile  uint8_t *)(0x42DE2104UL))
#define bFM_GPIO_PCR2_P2                          *((volatile  uint8_t *)(0x42DE2108UL))
#define bFM4_GPIO_PCR2_P2                         *((volatile  uint8_t *)(0x42DE2108UL))
#define bFM_GPIO_PCR2_P3                          *((volatile  uint8_t *)(0x42DE210CUL))
#define bFM4_GPIO_PCR2_P3                         *((volatile  uint8_t *)(0x42DE210CUL))
#define bFM_GPIO_PCR2_P4                          *((volatile  uint8_t *)(0x42DE2110UL))
#define bFM4_GPIO_PCR2_P4                         *((volatile  uint8_t *)(0x42DE2110UL))
#define bFM_GPIO_PCR2_P5                          *((volatile  uint8_t *)(0x42DE2114UL))
#define bFM4_GPIO_PCR2_P5                         *((volatile  uint8_t *)(0x42DE2114UL))
#define bFM_GPIO_PCR2_P6                          *((volatile  uint8_t *)(0x42DE2118UL))
#define bFM4_GPIO_PCR2_P6                         *((volatile  uint8_t *)(0x42DE2118UL))
#define bFM_GPIO_PCR2_P7                          *((volatile  uint8_t *)(0x42DE211CUL))
#define bFM4_GPIO_PCR2_P7                         *((volatile  uint8_t *)(0x42DE211CUL))
#define bFM_GPIO_PCR2_P8                          *((volatile  uint8_t *)(0x42DE2120UL))
#define bFM4_GPIO_PCR2_P8                         *((volatile  uint8_t *)(0x42DE2120UL))
#define bFM_GPIO_PCR2_P9                          *((volatile  uint8_t *)(0x42DE2124UL))
#define bFM4_GPIO_PCR2_P9                         *((volatile  uint8_t *)(0x42DE2124UL))
#define bFM_GPIO_PCR2_PA                          *((volatile  uint8_t *)(0x42DE2128UL))
#define bFM4_GPIO_PCR2_PA                         *((volatile  uint8_t *)(0x42DE2128UL))

#define bFM_GPIO_PCR3_P0                          *((volatile  uint8_t *)(0x42DE2180UL))
#define bFM4_GPIO_PCR3_P0                         *((volatile  uint8_t *)(0x42DE2180UL))
#define bFM_GPIO_PCR3_P1                          *((volatile  uint8_t *)(0x42DE2184UL))
#define bFM4_GPIO_PCR3_P1                         *((volatile  uint8_t *)(0x42DE2184UL))
#define bFM_GPIO_PCR3_P2                          *((volatile  uint8_t *)(0x42DE2188UL))
#define bFM4_GPIO_PCR3_P2                         *((volatile  uint8_t *)(0x42DE2188UL))
#define bFM_GPIO_PCR3_P3                          *((volatile  uint8_t *)(0x42DE218CUL))
#define bFM4_GPIO_PCR3_P3                         *((volatile  uint8_t *)(0x42DE218CUL))
#define bFM_GPIO_PCR3_P4                          *((volatile  uint8_t *)(0x42DE2190UL))
#define bFM4_GPIO_PCR3_P4                         *((volatile  uint8_t *)(0x42DE2190UL))
#define bFM_GPIO_PCR3_P5                          *((volatile  uint8_t *)(0x42DE2194UL))
#define bFM4_GPIO_PCR3_P5                         *((volatile  uint8_t *)(0x42DE2194UL))
#define bFM_GPIO_PCR3_P6                          *((volatile  uint8_t *)(0x42DE2198UL))
#define bFM4_GPIO_PCR3_P6                         *((volatile  uint8_t *)(0x42DE2198UL))
#define bFM_GPIO_PCR3_P7                          *((volatile  uint8_t *)(0x42DE219CUL))
#define bFM4_GPIO_PCR3_P7                         *((volatile  uint8_t *)(0x42DE219CUL))
#define bFM_GPIO_PCR3_P8                          *((volatile  uint8_t *)(0x42DE21A0UL))
#define bFM4_GPIO_PCR3_P8                         *((volatile  uint8_t *)(0x42DE21A0UL))
#define bFM_GPIO_PCR3_P9                          *((volatile  uint8_t *)(0x42DE21A4UL))
#define bFM4_GPIO_PCR3_P9                         *((volatile  uint8_t *)(0x42DE21A4UL))
#define bFM_GPIO_PCR3_PA                          *((volatile  uint8_t *)(0x42DE21A8UL))
#define bFM4_GPIO_PCR3_PA                         *((volatile  uint8_t *)(0x42DE21A8UL))
#define bFM_GPIO_PCR3_PB                          *((volatile  uint8_t *)(0x42DE21ACUL))
#define bFM4_GPIO_PCR3_PB                         *((volatile  uint8_t *)(0x42DE21ACUL))
#define bFM_GPIO_PCR3_PC                          *((volatile  uint8_t *)(0x42DE21B0UL))
#define bFM4_GPIO_PCR3_PC                         *((volatile  uint8_t *)(0x42DE21B0UL))
#define bFM_GPIO_PCR3_PD                          *((volatile  uint8_t *)(0x42DE21B4UL))
#define bFM4_GPIO_PCR3_PD                         *((volatile  uint8_t *)(0x42DE21B4UL))
#define bFM_GPIO_PCR3_PE                          *((volatile  uint8_t *)(0x42DE21B8UL))
#define bFM4_GPIO_PCR3_PE                         *((volatile  uint8_t *)(0x42DE21B8UL))

#define bFM_GPIO_PCR4_P0                          *((volatile  uint8_t *)(0x42DE2200UL))
#define bFM4_GPIO_PCR4_P0                         *((volatile  uint8_t *)(0x42DE2200UL))
#define bFM_GPIO_PCR4_P1                          *((volatile  uint8_t *)(0x42DE2204UL))
#define bFM4_GPIO_PCR4_P1                         *((volatile  uint8_t *)(0x42DE2204UL))
#define bFM_GPIO_PCR4_P2                          *((volatile  uint8_t *)(0x42DE2208UL))
#define bFM4_GPIO_PCR4_P2                         *((volatile  uint8_t *)(0x42DE2208UL))
#define bFM_GPIO_PCR4_P3                          *((volatile  uint8_t *)(0x42DE220CUL))
#define bFM4_GPIO_PCR4_P3                         *((volatile  uint8_t *)(0x42DE220CUL))
#define bFM_GPIO_PCR4_P4                          *((volatile  uint8_t *)(0x42DE2210UL))
#define bFM4_GPIO_PCR4_P4                         *((volatile  uint8_t *)(0x42DE2210UL))
#define bFM_GPIO_PCR4_P5                          *((volatile  uint8_t *)(0x42DE2214UL))
#define bFM4_GPIO_PCR4_P5                         *((volatile  uint8_t *)(0x42DE2214UL))
#define bFM_GPIO_PCR4_P6                          *((volatile  uint8_t *)(0x42DE2218UL))
#define bFM4_GPIO_PCR4_P6                         *((volatile  uint8_t *)(0x42DE2218UL))
#define bFM_GPIO_PCR4_P7                          *((volatile  uint8_t *)(0x42DE221CUL))
#define bFM4_GPIO_PCR4_P7                         *((volatile  uint8_t *)(0x42DE221CUL))
#define bFM_GPIO_PCR4_P8                          *((volatile  uint8_t *)(0x42DE2220UL))
#define bFM4_GPIO_PCR4_P8                         *((volatile  uint8_t *)(0x42DE2220UL))
#define bFM_GPIO_PCR4_P9                          *((volatile  uint8_t *)(0x42DE2224UL))
#define bFM4_GPIO_PCR4_P9                         *((volatile  uint8_t *)(0x42DE2224UL))

#define bFM_GPIO_PCR5_P0                          *((volatile  uint8_t *)(0x42DE2280UL))
#define bFM4_GPIO_PCR5_P0                         *((volatile  uint8_t *)(0x42DE2280UL))
#define bFM_GPIO_PCR5_P1                          *((volatile  uint8_t *)(0x42DE2284UL))
#define bFM4_GPIO_PCR5_P1                         *((volatile  uint8_t *)(0x42DE2284UL))
#define bFM_GPIO_PCR5_P2                          *((volatile  uint8_t *)(0x42DE2288UL))
#define bFM4_GPIO_PCR5_P2                         *((volatile  uint8_t *)(0x42DE2288UL))
#define bFM_GPIO_PCR5_PD                          *((volatile  uint8_t *)(0x42DE22B4UL))
#define bFM4_GPIO_PCR5_PD                         *((volatile  uint8_t *)(0x42DE22B4UL))
#define bFM_GPIO_PCR5_PE                          *((volatile  uint8_t *)(0x42DE22B8UL))
#define bFM4_GPIO_PCR5_PE                         *((volatile  uint8_t *)(0x42DE22B8UL))
#define bFM_GPIO_PCR5_PF                          *((volatile  uint8_t *)(0x42DE22BCUL))
#define bFM4_GPIO_PCR5_PF                         *((volatile  uint8_t *)(0x42DE22BCUL))

#define bFM_GPIO_PCR6_P0                          *((volatile  uint8_t *)(0x42DE2300UL))
#define bFM4_GPIO_PCR6_P0                         *((volatile  uint8_t *)(0x42DE2300UL))
#define bFM_GPIO_PCR6_P1                          *((volatile  uint8_t *)(0x42DE2304UL))
#define bFM4_GPIO_PCR6_P1                         *((volatile  uint8_t *)(0x42DE2304UL))
#define bFM_GPIO_PCR6_P2                          *((volatile  uint8_t *)(0x42DE2308UL))
#define bFM4_GPIO_PCR6_P2                         *((volatile  uint8_t *)(0x42DE2308UL))
#define bFM_GPIO_PCR6_P3                          *((volatile  uint8_t *)(0x42DE230CUL))
#define bFM4_GPIO_PCR6_P3                         *((volatile  uint8_t *)(0x42DE230CUL))
#define bFM_GPIO_PCR6_P4                          *((volatile  uint8_t *)(0x42DE2310UL))
#define bFM4_GPIO_PCR6_P4                         *((volatile  uint8_t *)(0x42DE2310UL))
#define bFM_GPIO_PCR6_P5                          *((volatile  uint8_t *)(0x42DE2314UL))
#define bFM4_GPIO_PCR6_P5                         *((volatile  uint8_t *)(0x42DE2314UL))
#define bFM_GPIO_PCR6_PE                          *((volatile  uint8_t *)(0x42DE2338UL))
#define bFM4_GPIO_PCR6_PE                         *((volatile  uint8_t *)(0x42DE2338UL))

#define bFM_GPIO_PCR7_P0                          *((volatile  uint8_t *)(0x42DE2380UL))
#define bFM4_GPIO_PCR7_P0                         *((volatile  uint8_t *)(0x42DE2380UL))
#define bFM_GPIO_PCR7_P1                          *((volatile  uint8_t *)(0x42DE2384UL))
#define bFM4_GPIO_PCR7_P1                         *((volatile  uint8_t *)(0x42DE2384UL))
#define bFM_GPIO_PCR7_P2                          *((volatile  uint8_t *)(0x42DE2388UL))
#define bFM4_GPIO_PCR7_P2                         *((volatile  uint8_t *)(0x42DE2388UL))
#define bFM_GPIO_PCR7_P3                          *((volatile  uint8_t *)(0x42DE238CUL))
#define bFM4_GPIO_PCR7_P3                         *((volatile  uint8_t *)(0x42DE238CUL))
#define bFM_GPIO_PCR7_P4                          *((volatile  uint8_t *)(0x42DE2390UL))
#define bFM4_GPIO_PCR7_P4                         *((volatile  uint8_t *)(0x42DE2390UL))
#define bFM_GPIO_PCR7_P5                          *((volatile  uint8_t *)(0x42DE2394UL))
#define bFM4_GPIO_PCR7_P5                         *((volatile  uint8_t *)(0x42DE2394UL))
#define bFM_GPIO_PCR7_P6                          *((volatile  uint8_t *)(0x42DE2398UL))
#define bFM4_GPIO_PCR7_P6                         *((volatile  uint8_t *)(0x42DE2398UL))
#define bFM_GPIO_PCR7_P7                          *((volatile  uint8_t *)(0x42DE239CUL))
#define bFM4_GPIO_PCR7_P7                         *((volatile  uint8_t *)(0x42DE239CUL))
#define bFM_GPIO_PCR7_P8                          *((volatile  uint8_t *)(0x42DE23A0UL))
#define bFM4_GPIO_PCR7_P8                         *((volatile  uint8_t *)(0x42DE23A0UL))
#define bFM_GPIO_PCR7_P9                          *((volatile  uint8_t *)(0x42DE23A4UL))
#define bFM4_GPIO_PCR7_P9                         *((volatile  uint8_t *)(0x42DE23A4UL))
#define bFM_GPIO_PCR7_PA                          *((volatile  uint8_t *)(0x42DE23A8UL))
#define bFM4_GPIO_PCR7_PA                         *((volatile  uint8_t *)(0x42DE23A8UL))
#define bFM_GPIO_PCR7_PB                          *((volatile  uint8_t *)(0x42DE23ACUL))
#define bFM4_GPIO_PCR7_PB                         *((volatile  uint8_t *)(0x42DE23ACUL))
#define bFM_GPIO_PCR7_PC                          *((volatile  uint8_t *)(0x42DE23B0UL))
#define bFM4_GPIO_PCR7_PC                         *((volatile  uint8_t *)(0x42DE23B0UL))
#define bFM_GPIO_PCR7_PD                          *((volatile  uint8_t *)(0x42DE23B4UL))
#define bFM4_GPIO_PCR7_PD                         *((volatile  uint8_t *)(0x42DE23B4UL))
#define bFM_GPIO_PCR7_PE                          *((volatile  uint8_t *)(0x42DE23B8UL))
#define bFM4_GPIO_PCR7_PE                         *((volatile  uint8_t *)(0x42DE23B8UL))

#define bFM_GPIO_PCR9_P0                          *((volatile  uint8_t *)(0x42DE2480UL))
#define bFM4_GPIO_PCR9_P0                         *((volatile  uint8_t *)(0x42DE2480UL))
#define bFM_GPIO_PCR9_P1                          *((volatile  uint8_t *)(0x42DE2484UL))
#define bFM4_GPIO_PCR9_P1                         *((volatile  uint8_t *)(0x42DE2484UL))
#define bFM_GPIO_PCR9_P2                          *((volatile  uint8_t *)(0x42DE2488UL))
#define bFM4_GPIO_PCR9_P2                         *((volatile  uint8_t *)(0x42DE2488UL))
#define bFM_GPIO_PCR9_P3                          *((volatile  uint8_t *)(0x42DE248CUL))
#define bFM4_GPIO_PCR9_P3                         *((volatile  uint8_t *)(0x42DE248CUL))
#define bFM_GPIO_PCR9_P4                          *((volatile  uint8_t *)(0x42DE2490UL))
#define bFM4_GPIO_PCR9_P4                         *((volatile  uint8_t *)(0x42DE2490UL))
#define bFM_GPIO_PCR9_P5                          *((volatile  uint8_t *)(0x42DE2494UL))
#define bFM4_GPIO_PCR9_P5                         *((volatile  uint8_t *)(0x42DE2494UL))

#define bFM_GPIO_PCRA_P0                          *((volatile  uint8_t *)(0x42DE2500UL))
#define bFM4_GPIO_PCRA_P0                         *((volatile  uint8_t *)(0x42DE2500UL))
#define bFM_GPIO_PCRA_P1                          *((volatile  uint8_t *)(0x42DE2504UL))
#define bFM4_GPIO_PCRA_P1                         *((volatile  uint8_t *)(0x42DE2504UL))
#define bFM_GPIO_PCRA_P2                          *((volatile  uint8_t *)(0x42DE2508UL))
#define bFM4_GPIO_PCRA_P2                         *((volatile  uint8_t *)(0x42DE2508UL))
#define bFM_GPIO_PCRA_P3                          *((volatile  uint8_t *)(0x42DE250CUL))
#define bFM4_GPIO_PCRA_P3                         *((volatile  uint8_t *)(0x42DE250CUL))
#define bFM_GPIO_PCRA_P4                          *((volatile  uint8_t *)(0x42DE2510UL))
#define bFM4_GPIO_PCRA_P4                         *((volatile  uint8_t *)(0x42DE2510UL))
#define bFM_GPIO_PCRA_P5                          *((volatile  uint8_t *)(0x42DE2514UL))
#define bFM4_GPIO_PCRA_P5                         *((volatile  uint8_t *)(0x42DE2514UL))
#define bFM_GPIO_PCRA_P6                          *((volatile  uint8_t *)(0x42DE2518UL))
#define bFM4_GPIO_PCRA_P6                         *((volatile  uint8_t *)(0x42DE2518UL))
#define bFM_GPIO_PCRA_P7                          *((volatile  uint8_t *)(0x42DE251CUL))
#define bFM4_GPIO_PCRA_P7                         *((volatile  uint8_t *)(0x42DE251CUL))
#define bFM_GPIO_PCRA_P8                          *((volatile  uint8_t *)(0x42DE2520UL))
#define bFM4_GPIO_PCRA_P8                         *((volatile  uint8_t *)(0x42DE2520UL))
#define bFM_GPIO_PCRA_P9                          *((volatile  uint8_t *)(0x42DE2524UL))
#define bFM4_GPIO_PCRA_P9                         *((volatile  uint8_t *)(0x42DE2524UL))
#define bFM_GPIO_PCRA_PA                          *((volatile  uint8_t *)(0x42DE2528UL))
#define bFM4_GPIO_PCRA_PA                         *((volatile  uint8_t *)(0x42DE2528UL))
#define bFM_GPIO_PCRA_PB                          *((volatile  uint8_t *)(0x42DE252CUL))
#define bFM4_GPIO_PCRA_PB                         *((volatile  uint8_t *)(0x42DE252CUL))
#define bFM_GPIO_PCRA_PC                          *((volatile  uint8_t *)(0x42DE2530UL))
#define bFM4_GPIO_PCRA_PC                         *((volatile  uint8_t *)(0x42DE2530UL))
#define bFM_GPIO_PCRA_PD                          *((volatile  uint8_t *)(0x42DE2534UL))
#define bFM4_GPIO_PCRA_PD                         *((volatile  uint8_t *)(0x42DE2534UL))
#define bFM_GPIO_PCRA_PE                          *((volatile  uint8_t *)(0x42DE2538UL))
#define bFM4_GPIO_PCRA_PE                         *((volatile  uint8_t *)(0x42DE2538UL))
#define bFM_GPIO_PCRA_PF                          *((volatile  uint8_t *)(0x42DE253CUL))
#define bFM4_GPIO_PCRA_PF                         *((volatile  uint8_t *)(0x42DE253CUL))

#define bFM_GPIO_PCRB_P0                          *((volatile  uint8_t *)(0x42DE2580UL))
#define bFM4_GPIO_PCRB_P0                         *((volatile  uint8_t *)(0x42DE2580UL))
#define bFM_GPIO_PCRB_P1                          *((volatile  uint8_t *)(0x42DE2584UL))
#define bFM4_GPIO_PCRB_P1                         *((volatile  uint8_t *)(0x42DE2584UL))
#define bFM_GPIO_PCRB_P2                          *((volatile  uint8_t *)(0x42DE2588UL))
#define bFM4_GPIO_PCRB_P2                         *((volatile  uint8_t *)(0x42DE2588UL))
#define bFM_GPIO_PCRB_P3                          *((volatile  uint8_t *)(0x42DE258CUL))
#define bFM4_GPIO_PCRB_P3                         *((volatile  uint8_t *)(0x42DE258CUL))
#define bFM_GPIO_PCRB_P4                          *((volatile  uint8_t *)(0x42DE2590UL))
#define bFM4_GPIO_PCRB_P4                         *((volatile  uint8_t *)(0x42DE2590UL))
#define bFM_GPIO_PCRB_P5                          *((volatile  uint8_t *)(0x42DE2594UL))
#define bFM4_GPIO_PCRB_P5                         *((volatile  uint8_t *)(0x42DE2594UL))
#define bFM_GPIO_PCRB_P6                          *((volatile  uint8_t *)(0x42DE2598UL))
#define bFM4_GPIO_PCRB_P6                         *((volatile  uint8_t *)(0x42DE2598UL))
#define bFM_GPIO_PCRB_P7                          *((volatile  uint8_t *)(0x42DE259CUL))
#define bFM4_GPIO_PCRB_P7                         *((volatile  uint8_t *)(0x42DE259CUL))

#define bFM_GPIO_PCRC_P0                          *((volatile  uint8_t *)(0x42DE2600UL))
#define bFM4_GPIO_PCRC_P0                         *((volatile  uint8_t *)(0x42DE2600UL))
#define bFM_GPIO_PCRC_P1                          *((volatile  uint8_t *)(0x42DE2604UL))
#define bFM4_GPIO_PCRC_P1                         *((volatile  uint8_t *)(0x42DE2604UL))
#define bFM_GPIO_PCRC_P2                          *((volatile  uint8_t *)(0x42DE2608UL))
#define bFM4_GPIO_PCRC_P2                         *((volatile  uint8_t *)(0x42DE2608UL))
#define bFM_GPIO_PCRC_P3                          *((volatile  uint8_t *)(0x42DE260CUL))
#define bFM4_GPIO_PCRC_P3                         *((volatile  uint8_t *)(0x42DE260CUL))
#define bFM_GPIO_PCRC_P4                          *((volatile  uint8_t *)(0x42DE2610UL))
#define bFM4_GPIO_PCRC_P4                         *((volatile  uint8_t *)(0x42DE2610UL))
#define bFM_GPIO_PCRC_P5                          *((volatile  uint8_t *)(0x42DE2614UL))
#define bFM4_GPIO_PCRC_P5                         *((volatile  uint8_t *)(0x42DE2614UL))
#define bFM_GPIO_PCRC_P6                          *((volatile  uint8_t *)(0x42DE2618UL))
#define bFM4_GPIO_PCRC_P6                         *((volatile  uint8_t *)(0x42DE2618UL))
#define bFM_GPIO_PCRC_P7                          *((volatile  uint8_t *)(0x42DE261CUL))
#define bFM4_GPIO_PCRC_P7                         *((volatile  uint8_t *)(0x42DE261CUL))
#define bFM_GPIO_PCRC_P8                          *((volatile  uint8_t *)(0x42DE2620UL))
#define bFM4_GPIO_PCRC_P8                         *((volatile  uint8_t *)(0x42DE2620UL))
#define bFM_GPIO_PCRC_P9                          *((volatile  uint8_t *)(0x42DE2624UL))
#define bFM4_GPIO_PCRC_P9                         *((volatile  uint8_t *)(0x42DE2624UL))
#define bFM_GPIO_PCRC_PA                          *((volatile  uint8_t *)(0x42DE2628UL))
#define bFM4_GPIO_PCRC_PA                         *((volatile  uint8_t *)(0x42DE2628UL))
#define bFM_GPIO_PCRC_PB                          *((volatile  uint8_t *)(0x42DE262CUL))
#define bFM4_GPIO_PCRC_PB                         *((volatile  uint8_t *)(0x42DE262CUL))
#define bFM_GPIO_PCRC_PC                          *((volatile  uint8_t *)(0x42DE2630UL))
#define bFM4_GPIO_PCRC_PC                         *((volatile  uint8_t *)(0x42DE2630UL))
#define bFM_GPIO_PCRC_PD                          *((volatile  uint8_t *)(0x42DE2634UL))
#define bFM4_GPIO_PCRC_PD                         *((volatile  uint8_t *)(0x42DE2634UL))
#define bFM_GPIO_PCRC_PE                          *((volatile  uint8_t *)(0x42DE2638UL))
#define bFM4_GPIO_PCRC_PE                         *((volatile  uint8_t *)(0x42DE2638UL))
#define bFM_GPIO_PCRC_PF                          *((volatile  uint8_t *)(0x42DE263CUL))
#define bFM4_GPIO_PCRC_PF                         *((volatile  uint8_t *)(0x42DE263CUL))

#define bFM_GPIO_PCRD_P0                          *((volatile  uint8_t *)(0x42DE2680UL))
#define bFM4_GPIO_PCRD_P0                         *((volatile  uint8_t *)(0x42DE2680UL))
#define bFM_GPIO_PCRD_P1                          *((volatile  uint8_t *)(0x42DE2684UL))
#define bFM4_GPIO_PCRD_P1                         *((volatile  uint8_t *)(0x42DE2684UL))
#define bFM_GPIO_PCRD_P2                          *((volatile  uint8_t *)(0x42DE2688UL))
#define bFM4_GPIO_PCRD_P2                         *((volatile  uint8_t *)(0x42DE2688UL))

#define bFM_GPIO_PCRE_P0                          *((volatile  uint8_t *)(0x42DE2700UL))
#define bFM4_GPIO_PCRE_P0                         *((volatile  uint8_t *)(0x42DE2700UL))
#define bFM_GPIO_PCRE_P2                          *((volatile  uint8_t *)(0x42DE2708UL))
#define bFM4_GPIO_PCRE_P2                         *((volatile  uint8_t *)(0x42DE2708UL))
#define bFM_GPIO_PCRE_P3                          *((volatile  uint8_t *)(0x42DE270CUL))
#define bFM4_GPIO_PCRE_P3                         *((volatile  uint8_t *)(0x42DE270CUL))

#define bFM_GPIO_PCRF_P0                          *((volatile  uint8_t *)(0x42DE2780UL))
#define bFM4_GPIO_PCRF_P0                         *((volatile  uint8_t *)(0x42DE2780UL))
#define bFM_GPIO_PCRF_P1                          *((volatile  uint8_t *)(0x42DE2784UL))
#define bFM4_GPIO_PCRF_P1                         *((volatile  uint8_t *)(0x42DE2784UL))
#define bFM_GPIO_PCRF_P2                          *((volatile  uint8_t *)(0x42DE2788UL))
#define bFM4_GPIO_PCRF_P2                         *((volatile  uint8_t *)(0x42DE2788UL))
#define bFM_GPIO_PCRF_P3                          *((volatile  uint8_t *)(0x42DE278CUL))
#define bFM4_GPIO_PCRF_P3                         *((volatile  uint8_t *)(0x42DE278CUL))
#define bFM_GPIO_PCRF_P4                          *((volatile  uint8_t *)(0x42DE2790UL))
#define bFM4_GPIO_PCRF_P4                         *((volatile  uint8_t *)(0x42DE2790UL))
#define bFM_GPIO_PCRF_P5                          *((volatile  uint8_t *)(0x42DE2794UL))
#define bFM4_GPIO_PCRF_P5                         *((volatile  uint8_t *)(0x42DE2794UL))
#define bFM_GPIO_PCRF_P6                          *((volatile  uint8_t *)(0x42DE2798UL))
#define bFM4_GPIO_PCRF_P6                         *((volatile  uint8_t *)(0x42DE2798UL))
#define bFM_GPIO_PCRF_P7                          *((volatile  uint8_t *)(0x42DE279CUL))
#define bFM4_GPIO_PCRF_P7                         *((volatile  uint8_t *)(0x42DE279CUL))

#define bFM_GPIO_PDIR0_P0                         *((volatile  uint8_t *)(0x42DE6000UL))
#define bFM4_GPIO_PDIR0_P0                        *((volatile  uint8_t *)(0x42DE6000UL))
#define bFM_GPIO_PDIR0_P1                         *((volatile  uint8_t *)(0x42DE6004UL))
#define bFM4_GPIO_PDIR0_P1                        *((volatile  uint8_t *)(0x42DE6004UL))
#define bFM_GPIO_PDIR0_P2                         *((volatile  uint8_t *)(0x42DE6008UL))
#define bFM4_GPIO_PDIR0_P2                        *((volatile  uint8_t *)(0x42DE6008UL))
#define bFM_GPIO_PDIR0_P3                         *((volatile  uint8_t *)(0x42DE600CUL))
#define bFM4_GPIO_PDIR0_P3                        *((volatile  uint8_t *)(0x42DE600CUL))
#define bFM_GPIO_PDIR0_P4                         *((volatile  uint8_t *)(0x42DE6010UL))
#define bFM4_GPIO_PDIR0_P4                        *((volatile  uint8_t *)(0x42DE6010UL))
#define bFM_GPIO_PDIR0_P8                         *((volatile  uint8_t *)(0x42DE6020UL))
#define bFM4_GPIO_PDIR0_P8                        *((volatile  uint8_t *)(0x42DE6020UL))
#define bFM_GPIO_PDIR0_P9                         *((volatile  uint8_t *)(0x42DE6024UL))
#define bFM4_GPIO_PDIR0_P9                        *((volatile  uint8_t *)(0x42DE6024UL))
#define bFM_GPIO_PDIR0_PA                         *((volatile  uint8_t *)(0x42DE6028UL))
#define bFM4_GPIO_PDIR0_PA                        *((volatile  uint8_t *)(0x42DE6028UL))

#define bFM_GPIO_PDIR1_P0                         *((volatile  uint8_t *)(0x42DE6080UL))
#define bFM4_GPIO_PDIR1_P0                        *((volatile  uint8_t *)(0x42DE6080UL))
#define bFM_GPIO_PDIR1_P1                         *((volatile  uint8_t *)(0x42DE6084UL))
#define bFM4_GPIO_PDIR1_P1                        *((volatile  uint8_t *)(0x42DE6084UL))
#define bFM_GPIO_PDIR1_P2                         *((volatile  uint8_t *)(0x42DE6088UL))
#define bFM4_GPIO_PDIR1_P2                        *((volatile  uint8_t *)(0x42DE6088UL))
#define bFM_GPIO_PDIR1_P3                         *((volatile  uint8_t *)(0x42DE608CUL))
#define bFM4_GPIO_PDIR1_P3                        *((volatile  uint8_t *)(0x42DE608CUL))
#define bFM_GPIO_PDIR1_P4                         *((volatile  uint8_t *)(0x42DE6090UL))
#define bFM4_GPIO_PDIR1_P4                        *((volatile  uint8_t *)(0x42DE6090UL))
#define bFM_GPIO_PDIR1_P5                         *((volatile  uint8_t *)(0x42DE6094UL))
#define bFM4_GPIO_PDIR1_P5                        *((volatile  uint8_t *)(0x42DE6094UL))
#define bFM_GPIO_PDIR1_P6                         *((volatile  uint8_t *)(0x42DE6098UL))
#define bFM4_GPIO_PDIR1_P6                        *((volatile  uint8_t *)(0x42DE6098UL))
#define bFM_GPIO_PDIR1_P7                         *((volatile  uint8_t *)(0x42DE609CUL))
#define bFM4_GPIO_PDIR1_P7                        *((volatile  uint8_t *)(0x42DE609CUL))
#define bFM_GPIO_PDIR1_P8                         *((volatile  uint8_t *)(0x42DE60A0UL))
#define bFM4_GPIO_PDIR1_P8                        *((volatile  uint8_t *)(0x42DE60A0UL))
#define bFM_GPIO_PDIR1_P9                         *((volatile  uint8_t *)(0x42DE60A4UL))
#define bFM4_GPIO_PDIR1_P9                        *((volatile  uint8_t *)(0x42DE60A4UL))
#define bFM_GPIO_PDIR1_PA                         *((volatile  uint8_t *)(0x42DE60A8UL))
#define bFM4_GPIO_PDIR1_PA                        *((volatile  uint8_t *)(0x42DE60A8UL))
#define bFM_GPIO_PDIR1_PB                         *((volatile  uint8_t *)(0x42DE60ACUL))
#define bFM4_GPIO_PDIR1_PB                        *((volatile  uint8_t *)(0x42DE60ACUL))
#define bFM_GPIO_PDIR1_PC                         *((volatile  uint8_t *)(0x42DE60B0UL))
#define bFM4_GPIO_PDIR1_PC                        *((volatile  uint8_t *)(0x42DE60B0UL))
#define bFM_GPIO_PDIR1_PD                         *((volatile  uint8_t *)(0x42DE60B4UL))
#define bFM4_GPIO_PDIR1_PD                        *((volatile  uint8_t *)(0x42DE60B4UL))
#define bFM_GPIO_PDIR1_PE                         *((volatile  uint8_t *)(0x42DE60B8UL))
#define bFM4_GPIO_PDIR1_PE                        *((volatile  uint8_t *)(0x42DE60B8UL))
#define bFM_GPIO_PDIR1_PF                         *((volatile  uint8_t *)(0x42DE60BCUL))
#define bFM4_GPIO_PDIR1_PF                        *((volatile  uint8_t *)(0x42DE60BCUL))

#define bFM_GPIO_PDIR2_P0                         *((volatile  uint8_t *)(0x42DE6100UL))
#define bFM4_GPIO_PDIR2_P0                        *((volatile  uint8_t *)(0x42DE6100UL))
#define bFM_GPIO_PDIR2_P1                         *((volatile  uint8_t *)(0x42DE6104UL))
#define bFM4_GPIO_PDIR2_P1                        *((volatile  uint8_t *)(0x42DE6104UL))
#define bFM_GPIO_PDIR2_P2                         *((volatile  uint8_t *)(0x42DE6108UL))
#define bFM4_GPIO_PDIR2_P2                        *((volatile  uint8_t *)(0x42DE6108UL))
#define bFM_GPIO_PDIR2_P3                         *((volatile  uint8_t *)(0x42DE610CUL))
#define bFM4_GPIO_PDIR2_P3                        *((volatile  uint8_t *)(0x42DE610CUL))
#define bFM_GPIO_PDIR2_P4                         *((volatile  uint8_t *)(0x42DE6110UL))
#define bFM4_GPIO_PDIR2_P4                        *((volatile  uint8_t *)(0x42DE6110UL))
#define bFM_GPIO_PDIR2_P5                         *((volatile  uint8_t *)(0x42DE6114UL))
#define bFM4_GPIO_PDIR2_P5                        *((volatile  uint8_t *)(0x42DE6114UL))
#define bFM_GPIO_PDIR2_P6                         *((volatile  uint8_t *)(0x42DE6118UL))
#define bFM4_GPIO_PDIR2_P6                        *((volatile  uint8_t *)(0x42DE6118UL))
#define bFM_GPIO_PDIR2_P7                         *((volatile  uint8_t *)(0x42DE611CUL))
#define bFM4_GPIO_PDIR2_P7                        *((volatile  uint8_t *)(0x42DE611CUL))
#define bFM_GPIO_PDIR2_P8                         *((volatile  uint8_t *)(0x42DE6120UL))
#define bFM4_GPIO_PDIR2_P8                        *((volatile  uint8_t *)(0x42DE6120UL))
#define bFM_GPIO_PDIR2_P9                         *((volatile  uint8_t *)(0x42DE6124UL))
#define bFM4_GPIO_PDIR2_P9                        *((volatile  uint8_t *)(0x42DE6124UL))
#define bFM_GPIO_PDIR2_PA                         *((volatile  uint8_t *)(0x42DE6128UL))
#define bFM4_GPIO_PDIR2_PA                        *((volatile  uint8_t *)(0x42DE6128UL))

#define bFM_GPIO_PDIR3_P0                         *((volatile  uint8_t *)(0x42DE6180UL))
#define bFM4_GPIO_PDIR3_P0                        *((volatile  uint8_t *)(0x42DE6180UL))
#define bFM_GPIO_PDIR3_P1                         *((volatile  uint8_t *)(0x42DE6184UL))
#define bFM4_GPIO_PDIR3_P1                        *((volatile  uint8_t *)(0x42DE6184UL))
#define bFM_GPIO_PDIR3_P2                         *((volatile  uint8_t *)(0x42DE6188UL))
#define bFM4_GPIO_PDIR3_P2                        *((volatile  uint8_t *)(0x42DE6188UL))
#define bFM_GPIO_PDIR3_P3                         *((volatile  uint8_t *)(0x42DE618CUL))
#define bFM4_GPIO_PDIR3_P3                        *((volatile  uint8_t *)(0x42DE618CUL))
#define bFM_GPIO_PDIR3_P4                         *((volatile  uint8_t *)(0x42DE6190UL))
#define bFM4_GPIO_PDIR3_P4                        *((volatile  uint8_t *)(0x42DE6190UL))
#define bFM_GPIO_PDIR3_P5                         *((volatile  uint8_t *)(0x42DE6194UL))
#define bFM4_GPIO_PDIR3_P5                        *((volatile  uint8_t *)(0x42DE6194UL))
#define bFM_GPIO_PDIR3_P6                         *((volatile  uint8_t *)(0x42DE6198UL))
#define bFM4_GPIO_PDIR3_P6                        *((volatile  uint8_t *)(0x42DE6198UL))
#define bFM_GPIO_PDIR3_P7                         *((volatile  uint8_t *)(0x42DE619CUL))
#define bFM4_GPIO_PDIR3_P7                        *((volatile  uint8_t *)(0x42DE619CUL))
#define bFM_GPIO_PDIR3_P8                         *((volatile  uint8_t *)(0x42DE61A0UL))
#define bFM4_GPIO_PDIR3_P8                        *((volatile  uint8_t *)(0x42DE61A0UL))
#define bFM_GPIO_PDIR3_P9                         *((volatile  uint8_t *)(0x42DE61A4UL))
#define bFM4_GPIO_PDIR3_P9                        *((volatile  uint8_t *)(0x42DE61A4UL))
#define bFM_GPIO_PDIR3_PA                         *((volatile  uint8_t *)(0x42DE61A8UL))
#define bFM4_GPIO_PDIR3_PA                        *((volatile  uint8_t *)(0x42DE61A8UL))
#define bFM_GPIO_PDIR3_PB                         *((volatile  uint8_t *)(0x42DE61ACUL))
#define bFM4_GPIO_PDIR3_PB                        *((volatile  uint8_t *)(0x42DE61ACUL))
#define bFM_GPIO_PDIR3_PC                         *((volatile  uint8_t *)(0x42DE61B0UL))
#define bFM4_GPIO_PDIR3_PC                        *((volatile  uint8_t *)(0x42DE61B0UL))
#define bFM_GPIO_PDIR3_PD                         *((volatile  uint8_t *)(0x42DE61B4UL))
#define bFM4_GPIO_PDIR3_PD                        *((volatile  uint8_t *)(0x42DE61B4UL))
#define bFM_GPIO_PDIR3_PE                         *((volatile  uint8_t *)(0x42DE61B8UL))
#define bFM4_GPIO_PDIR3_PE                        *((volatile  uint8_t *)(0x42DE61B8UL))

#define bFM_GPIO_PDIR4_P0                         *((volatile  uint8_t *)(0x42DE6200UL))
#define bFM4_GPIO_PDIR4_P0                        *((volatile  uint8_t *)(0x42DE6200UL))
#define bFM_GPIO_PDIR4_P1                         *((volatile  uint8_t *)(0x42DE6204UL))
#define bFM4_GPIO_PDIR4_P1                        *((volatile  uint8_t *)(0x42DE6204UL))
#define bFM_GPIO_PDIR4_P2                         *((volatile  uint8_t *)(0x42DE6208UL))
#define bFM4_GPIO_PDIR4_P2                        *((volatile  uint8_t *)(0x42DE6208UL))
#define bFM_GPIO_PDIR4_P3                         *((volatile  uint8_t *)(0x42DE620CUL))
#define bFM4_GPIO_PDIR4_P3                        *((volatile  uint8_t *)(0x42DE620CUL))
#define bFM_GPIO_PDIR4_P4                         *((volatile  uint8_t *)(0x42DE6210UL))
#define bFM4_GPIO_PDIR4_P4                        *((volatile  uint8_t *)(0x42DE6210UL))
#define bFM_GPIO_PDIR4_P5                         *((volatile  uint8_t *)(0x42DE6214UL))
#define bFM4_GPIO_PDIR4_P5                        *((volatile  uint8_t *)(0x42DE6214UL))
#define bFM_GPIO_PDIR4_P6                         *((volatile  uint8_t *)(0x42DE6218UL))
#define bFM4_GPIO_PDIR4_P6                        *((volatile  uint8_t *)(0x42DE6218UL))
#define bFM_GPIO_PDIR4_P7                         *((volatile  uint8_t *)(0x42DE621CUL))
#define bFM4_GPIO_PDIR4_P7                        *((volatile  uint8_t *)(0x42DE621CUL))
#define bFM_GPIO_PDIR4_P8                         *((volatile  uint8_t *)(0x42DE6220UL))
#define bFM4_GPIO_PDIR4_P8                        *((volatile  uint8_t *)(0x42DE6220UL))
#define bFM_GPIO_PDIR4_P9                         *((volatile  uint8_t *)(0x42DE6224UL))
#define bFM4_GPIO_PDIR4_P9                        *((volatile  uint8_t *)(0x42DE6224UL))

#define bFM_GPIO_PDIR5_P0                         *((volatile  uint8_t *)(0x42DE6280UL))
#define bFM4_GPIO_PDIR5_P0                        *((volatile  uint8_t *)(0x42DE6280UL))
#define bFM_GPIO_PDIR5_P1                         *((volatile  uint8_t *)(0x42DE6284UL))
#define bFM4_GPIO_PDIR5_P1                        *((volatile  uint8_t *)(0x42DE6284UL))
#define bFM_GPIO_PDIR5_P2                         *((volatile  uint8_t *)(0x42DE6288UL))
#define bFM4_GPIO_PDIR5_P2                        *((volatile  uint8_t *)(0x42DE6288UL))
#define bFM_GPIO_PDIR5_PD                         *((volatile  uint8_t *)(0x42DE62B4UL))
#define bFM4_GPIO_PDIR5_PD                        *((volatile  uint8_t *)(0x42DE62B4UL))
#define bFM_GPIO_PDIR5_PE                         *((volatile  uint8_t *)(0x42DE62B8UL))
#define bFM4_GPIO_PDIR5_PE                        *((volatile  uint8_t *)(0x42DE62B8UL))
#define bFM_GPIO_PDIR5_PF                         *((volatile  uint8_t *)(0x42DE62BCUL))
#define bFM4_GPIO_PDIR5_PF                        *((volatile  uint8_t *)(0x42DE62BCUL))

#define bFM_GPIO_PDIR6_P0                         *((volatile  uint8_t *)(0x42DE6300UL))
#define bFM4_GPIO_PDIR6_P0                        *((volatile  uint8_t *)(0x42DE6300UL))
#define bFM_GPIO_PDIR6_P1                         *((volatile  uint8_t *)(0x42DE6304UL))
#define bFM4_GPIO_PDIR6_P1                        *((volatile  uint8_t *)(0x42DE6304UL))
#define bFM_GPIO_PDIR6_P2                         *((volatile  uint8_t *)(0x42DE6308UL))
#define bFM4_GPIO_PDIR6_P2                        *((volatile  uint8_t *)(0x42DE6308UL))
#define bFM_GPIO_PDIR6_P3                         *((volatile  uint8_t *)(0x42DE630CUL))
#define bFM4_GPIO_PDIR6_P3                        *((volatile  uint8_t *)(0x42DE630CUL))
#define bFM_GPIO_PDIR6_P4                         *((volatile  uint8_t *)(0x42DE6310UL))
#define bFM4_GPIO_PDIR6_P4                        *((volatile  uint8_t *)(0x42DE6310UL))
#define bFM_GPIO_PDIR6_P5                         *((volatile  uint8_t *)(0x42DE6314UL))
#define bFM4_GPIO_PDIR6_P5                        *((volatile  uint8_t *)(0x42DE6314UL))
#define bFM_GPIO_PDIR6_PE                         *((volatile  uint8_t *)(0x42DE6338UL))
#define bFM4_GPIO_PDIR6_PE                        *((volatile  uint8_t *)(0x42DE6338UL))

#define bFM_GPIO_PDIR7_P0                         *((volatile  uint8_t *)(0x42DE6380UL))
#define bFM4_GPIO_PDIR7_P0                        *((volatile  uint8_t *)(0x42DE6380UL))
#define bFM_GPIO_PDIR7_P1                         *((volatile  uint8_t *)(0x42DE6384UL))
#define bFM4_GPIO_PDIR7_P1                        *((volatile  uint8_t *)(0x42DE6384UL))
#define bFM_GPIO_PDIR7_P2                         *((volatile  uint8_t *)(0x42DE6388UL))
#define bFM4_GPIO_PDIR7_P2                        *((volatile  uint8_t *)(0x42DE6388UL))
#define bFM_GPIO_PDIR7_P3                         *((volatile  uint8_t *)(0x42DE638CUL))
#define bFM4_GPIO_PDIR7_P3                        *((volatile  uint8_t *)(0x42DE638CUL))
#define bFM_GPIO_PDIR7_P4                         *((volatile  uint8_t *)(0x42DE6390UL))
#define bFM4_GPIO_PDIR7_P4                        *((volatile  uint8_t *)(0x42DE6390UL))
#define bFM_GPIO_PDIR7_P5                         *((volatile  uint8_t *)(0x42DE6394UL))
#define bFM4_GPIO_PDIR7_P5                        *((volatile  uint8_t *)(0x42DE6394UL))
#define bFM_GPIO_PDIR7_P6                         *((volatile  uint8_t *)(0x42DE6398UL))
#define bFM4_GPIO_PDIR7_P6                        *((volatile  uint8_t *)(0x42DE6398UL))
#define bFM_GPIO_PDIR7_P7                         *((volatile  uint8_t *)(0x42DE639CUL))
#define bFM4_GPIO_PDIR7_P7                        *((volatile  uint8_t *)(0x42DE639CUL))
#define bFM_GPIO_PDIR7_P8                         *((volatile  uint8_t *)(0x42DE63A0UL))
#define bFM4_GPIO_PDIR7_P8                        *((volatile  uint8_t *)(0x42DE63A0UL))
#define bFM_GPIO_PDIR7_P9                         *((volatile  uint8_t *)(0x42DE63A4UL))
#define bFM4_GPIO_PDIR7_P9                        *((volatile  uint8_t *)(0x42DE63A4UL))
#define bFM_GPIO_PDIR7_PA                         *((volatile  uint8_t *)(0x42DE63A8UL))
#define bFM4_GPIO_PDIR7_PA                        *((volatile  uint8_t *)(0x42DE63A8UL))
#define bFM_GPIO_PDIR7_PB                         *((volatile  uint8_t *)(0x42DE63ACUL))
#define bFM4_GPIO_PDIR7_PB                        *((volatile  uint8_t *)(0x42DE63ACUL))
#define bFM_GPIO_PDIR7_PC                         *((volatile  uint8_t *)(0x42DE63B0UL))
#define bFM4_GPIO_PDIR7_PC                        *((volatile  uint8_t *)(0x42DE63B0UL))
#define bFM_GPIO_PDIR7_PD                         *((volatile  uint8_t *)(0x42DE63B4UL))
#define bFM4_GPIO_PDIR7_PD                        *((volatile  uint8_t *)(0x42DE63B4UL))
#define bFM_GPIO_PDIR7_PE                         *((volatile  uint8_t *)(0x42DE63B8UL))
#define bFM4_GPIO_PDIR7_PE                        *((volatile  uint8_t *)(0x42DE63B8UL))

#define bFM_GPIO_PDIR8_P0                         *((volatile  uint8_t *)(0x42DE6400UL))
#define bFM4_GPIO_PDIR8_P0                        *((volatile  uint8_t *)(0x42DE6400UL))
#define bFM_GPIO_PDIR8_P1                         *((volatile  uint8_t *)(0x42DE6404UL))
#define bFM4_GPIO_PDIR8_P1                        *((volatile  uint8_t *)(0x42DE6404UL))
#define bFM_GPIO_PDIR8_P2                         *((volatile  uint8_t *)(0x42DE6408UL))
#define bFM4_GPIO_PDIR8_P2                        *((volatile  uint8_t *)(0x42DE6408UL))
#define bFM_GPIO_PDIR8_P3                         *((volatile  uint8_t *)(0x42DE640CUL))
#define bFM4_GPIO_PDIR8_P3                        *((volatile  uint8_t *)(0x42DE640CUL))

#define bFM_GPIO_PDIR9_P0                         *((volatile  uint8_t *)(0x42DE6480UL))
#define bFM4_GPIO_PDIR9_P0                        *((volatile  uint8_t *)(0x42DE6480UL))
#define bFM_GPIO_PDIR9_P1                         *((volatile  uint8_t *)(0x42DE6484UL))
#define bFM4_GPIO_PDIR9_P1                        *((volatile  uint8_t *)(0x42DE6484UL))
#define bFM_GPIO_PDIR9_P2                         *((volatile  uint8_t *)(0x42DE6488UL))
#define bFM4_GPIO_PDIR9_P2                        *((volatile  uint8_t *)(0x42DE6488UL))
#define bFM_GPIO_PDIR9_P3                         *((volatile  uint8_t *)(0x42DE648CUL))
#define bFM4_GPIO_PDIR9_P3                        *((volatile  uint8_t *)(0x42DE648CUL))
#define bFM_GPIO_PDIR9_P4                         *((volatile  uint8_t *)(0x42DE6490UL))
#define bFM4_GPIO_PDIR9_P4                        *((volatile  uint8_t *)(0x42DE6490UL))
#define bFM_GPIO_PDIR9_P5                         *((volatile  uint8_t *)(0x42DE6494UL))
#define bFM4_GPIO_PDIR9_P5                        *((volatile  uint8_t *)(0x42DE6494UL))

#define bFM_GPIO_PDIRA_P0                         *((volatile  uint8_t *)(0x42DE6500UL))
#define bFM4_GPIO_PDIRA_P0                        *((volatile  uint8_t *)(0x42DE6500UL))
#define bFM_GPIO_PDIRA_P1                         *((volatile  uint8_t *)(0x42DE6504UL))
#define bFM4_GPIO_PDIRA_P1                        *((volatile  uint8_t *)(0x42DE6504UL))
#define bFM_GPIO_PDIRA_P2                         *((volatile  uint8_t *)(0x42DE6508UL))
#define bFM4_GPIO_PDIRA_P2                        *((volatile  uint8_t *)(0x42DE6508UL))
#define bFM_GPIO_PDIRA_P3                         *((volatile  uint8_t *)(0x42DE650CUL))
#define bFM4_GPIO_PDIRA_P3                        *((volatile  uint8_t *)(0x42DE650CUL))
#define bFM_GPIO_PDIRA_P4                         *((volatile  uint8_t *)(0x42DE6510UL))
#define bFM4_GPIO_PDIRA_P4                        *((volatile  uint8_t *)(0x42DE6510UL))
#define bFM_GPIO_PDIRA_P5                         *((volatile  uint8_t *)(0x42DE6514UL))
#define bFM4_GPIO_PDIRA_P5                        *((volatile  uint8_t *)(0x42DE6514UL))
#define bFM_GPIO_PDIRA_P6                         *((volatile  uint8_t *)(0x42DE6518UL))
#define bFM4_GPIO_PDIRA_P6                        *((volatile  uint8_t *)(0x42DE6518UL))
#define bFM_GPIO_PDIRA_P7                         *((volatile  uint8_t *)(0x42DE651CUL))
#define bFM4_GPIO_PDIRA_P7                        *((volatile  uint8_t *)(0x42DE651CUL))
#define bFM_GPIO_PDIRA_P8                         *((volatile  uint8_t *)(0x42DE6520UL))
#define bFM4_GPIO_PDIRA_P8                        *((volatile  uint8_t *)(0x42DE6520UL))
#define bFM_GPIO_PDIRA_P9                         *((volatile  uint8_t *)(0x42DE6524UL))
#define bFM4_GPIO_PDIRA_P9                        *((volatile  uint8_t *)(0x42DE6524UL))
#define bFM_GPIO_PDIRA_PA                         *((volatile  uint8_t *)(0x42DE6528UL))
#define bFM4_GPIO_PDIRA_PA                        *((volatile  uint8_t *)(0x42DE6528UL))
#define bFM_GPIO_PDIRA_PB                         *((volatile  uint8_t *)(0x42DE652CUL))
#define bFM4_GPIO_PDIRA_PB                        *((volatile  uint8_t *)(0x42DE652CUL))
#define bFM_GPIO_PDIRA_PC                         *((volatile  uint8_t *)(0x42DE6530UL))
#define bFM4_GPIO_PDIRA_PC                        *((volatile  uint8_t *)(0x42DE6530UL))
#define bFM_GPIO_PDIRA_PD                         *((volatile  uint8_t *)(0x42DE6534UL))
#define bFM4_GPIO_PDIRA_PD                        *((volatile  uint8_t *)(0x42DE6534UL))
#define bFM_GPIO_PDIRA_PE                         *((volatile  uint8_t *)(0x42DE6538UL))
#define bFM4_GPIO_PDIRA_PE                        *((volatile  uint8_t *)(0x42DE6538UL))
#define bFM_GPIO_PDIRA_PF                         *((volatile  uint8_t *)(0x42DE653CUL))
#define bFM4_GPIO_PDIRA_PF                        *((volatile  uint8_t *)(0x42DE653CUL))

#define bFM_GPIO_PDIRB_P0                         *((volatile  uint8_t *)(0x42DE6580UL))
#define bFM4_GPIO_PDIRB_P0                        *((volatile  uint8_t *)(0x42DE6580UL))
#define bFM_GPIO_PDIRB_P1                         *((volatile  uint8_t *)(0x42DE6584UL))
#define bFM4_GPIO_PDIRB_P1                        *((volatile  uint8_t *)(0x42DE6584UL))
#define bFM_GPIO_PDIRB_P2                         *((volatile  uint8_t *)(0x42DE6588UL))
#define bFM4_GPIO_PDIRB_P2                        *((volatile  uint8_t *)(0x42DE6588UL))
#define bFM_GPIO_PDIRB_P3                         *((volatile  uint8_t *)(0x42DE658CUL))
#define bFM4_GPIO_PDIRB_P3                        *((volatile  uint8_t *)(0x42DE658CUL))
#define bFM_GPIO_PDIRB_P4                         *((volatile  uint8_t *)(0x42DE6590UL))
#define bFM4_GPIO_PDIRB_P4                        *((volatile  uint8_t *)(0x42DE6590UL))
#define bFM_GPIO_PDIRB_P5                         *((volatile  uint8_t *)(0x42DE6594UL))
#define bFM4_GPIO_PDIRB_P5                        *((volatile  uint8_t *)(0x42DE6594UL))
#define bFM_GPIO_PDIRB_P6                         *((volatile  uint8_t *)(0x42DE6598UL))
#define bFM4_GPIO_PDIRB_P6                        *((volatile  uint8_t *)(0x42DE6598UL))
#define bFM_GPIO_PDIRB_P7                         *((volatile  uint8_t *)(0x42DE659CUL))
#define bFM4_GPIO_PDIRB_P7                        *((volatile  uint8_t *)(0x42DE659CUL))

#define bFM_GPIO_PDIRC_P0                         *((volatile  uint8_t *)(0x42DE6600UL))
#define bFM4_GPIO_PDIRC_P0                        *((volatile  uint8_t *)(0x42DE6600UL))
#define bFM_GPIO_PDIRC_P1                         *((volatile  uint8_t *)(0x42DE6604UL))
#define bFM4_GPIO_PDIRC_P1                        *((volatile  uint8_t *)(0x42DE6604UL))
#define bFM_GPIO_PDIRC_P2                         *((volatile  uint8_t *)(0x42DE6608UL))
#define bFM4_GPIO_PDIRC_P2                        *((volatile  uint8_t *)(0x42DE6608UL))
#define bFM_GPIO_PDIRC_P3                         *((volatile  uint8_t *)(0x42DE660CUL))
#define bFM4_GPIO_PDIRC_P3                        *((volatile  uint8_t *)(0x42DE660CUL))
#define bFM_GPIO_PDIRC_P4                         *((volatile  uint8_t *)(0x42DE6610UL))
#define bFM4_GPIO_PDIRC_P4                        *((volatile  uint8_t *)(0x42DE6610UL))
#define bFM_GPIO_PDIRC_P5                         *((volatile  uint8_t *)(0x42DE6614UL))
#define bFM4_GPIO_PDIRC_P5                        *((volatile  uint8_t *)(0x42DE6614UL))
#define bFM_GPIO_PDIRC_P6                         *((volatile  uint8_t *)(0x42DE6618UL))
#define bFM4_GPIO_PDIRC_P6                        *((volatile  uint8_t *)(0x42DE6618UL))
#define bFM_GPIO_PDIRC_P7                         *((volatile  uint8_t *)(0x42DE661CUL))
#define bFM4_GPIO_PDIRC_P7                        *((volatile  uint8_t *)(0x42DE661CUL))
#define bFM_GPIO_PDIRC_P8                         *((volatile  uint8_t *)(0x42DE6620UL))
#define bFM4_GPIO_PDIRC_P8                        *((volatile  uint8_t *)(0x42DE6620UL))
#define bFM_GPIO_PDIRC_P9                         *((volatile  uint8_t *)(0x42DE6624UL))
#define bFM4_GPIO_PDIRC_P9                        *((volatile  uint8_t *)(0x42DE6624UL))
#define bFM_GPIO_PDIRC_PA                         *((volatile  uint8_t *)(0x42DE6628UL))
#define bFM4_GPIO_PDIRC_PA                        *((volatile  uint8_t *)(0x42DE6628UL))
#define bFM_GPIO_PDIRC_PB                         *((volatile  uint8_t *)(0x42DE662CUL))
#define bFM4_GPIO_PDIRC_PB                        *((volatile  uint8_t *)(0x42DE662CUL))
#define bFM_GPIO_PDIRC_PC                         *((volatile  uint8_t *)(0x42DE6630UL))
#define bFM4_GPIO_PDIRC_PC                        *((volatile  uint8_t *)(0x42DE6630UL))
#define bFM_GPIO_PDIRC_PD                         *((volatile  uint8_t *)(0x42DE6634UL))
#define bFM4_GPIO_PDIRC_PD                        *((volatile  uint8_t *)(0x42DE6634UL))
#define bFM_GPIO_PDIRC_PE                         *((volatile  uint8_t *)(0x42DE6638UL))
#define bFM4_GPIO_PDIRC_PE                        *((volatile  uint8_t *)(0x42DE6638UL))
#define bFM_GPIO_PDIRC_PF                         *((volatile  uint8_t *)(0x42DE663CUL))
#define bFM4_GPIO_PDIRC_PF                        *((volatile  uint8_t *)(0x42DE663CUL))

#define bFM_GPIO_PDIRD_P0                         *((volatile  uint8_t *)(0x42DE6680UL))
#define bFM4_GPIO_PDIRD_P0                        *((volatile  uint8_t *)(0x42DE6680UL))
#define bFM_GPIO_PDIRD_P1                         *((volatile  uint8_t *)(0x42DE6684UL))
#define bFM4_GPIO_PDIRD_P1                        *((volatile  uint8_t *)(0x42DE6684UL))
#define bFM_GPIO_PDIRD_P2                         *((volatile  uint8_t *)(0x42DE6688UL))
#define bFM4_GPIO_PDIRD_P2                        *((volatile  uint8_t *)(0x42DE6688UL))

#define bFM_GPIO_PDIRE_P0                         *((volatile  uint8_t *)(0x42DE6700UL))
#define bFM4_GPIO_PDIRE_P0                        *((volatile  uint8_t *)(0x42DE6700UL))
#define bFM_GPIO_PDIRE_P2                         *((volatile  uint8_t *)(0x42DE6708UL))
#define bFM4_GPIO_PDIRE_P2                        *((volatile  uint8_t *)(0x42DE6708UL))
#define bFM_GPIO_PDIRE_P3                         *((volatile  uint8_t *)(0x42DE670CUL))
#define bFM4_GPIO_PDIRE_P3                        *((volatile  uint8_t *)(0x42DE670CUL))

#define bFM_GPIO_PDIRF_P0                         *((volatile  uint8_t *)(0x42DE6780UL))
#define bFM4_GPIO_PDIRF_P0                        *((volatile  uint8_t *)(0x42DE6780UL))
#define bFM_GPIO_PDIRF_P1                         *((volatile  uint8_t *)(0x42DE6784UL))
#define bFM4_GPIO_PDIRF_P1                        *((volatile  uint8_t *)(0x42DE6784UL))
#define bFM_GPIO_PDIRF_P2                         *((volatile  uint8_t *)(0x42DE6788UL))
#define bFM4_GPIO_PDIRF_P2                        *((volatile  uint8_t *)(0x42DE6788UL))
#define bFM_GPIO_PDIRF_P3                         *((volatile  uint8_t *)(0x42DE678CUL))
#define bFM4_GPIO_PDIRF_P3                        *((volatile  uint8_t *)(0x42DE678CUL))
#define bFM_GPIO_PDIRF_P4                         *((volatile  uint8_t *)(0x42DE6790UL))
#define bFM4_GPIO_PDIRF_P4                        *((volatile  uint8_t *)(0x42DE6790UL))
#define bFM_GPIO_PDIRF_P5                         *((volatile  uint8_t *)(0x42DE6794UL))
#define bFM4_GPIO_PDIRF_P5                        *((volatile  uint8_t *)(0x42DE6794UL))
#define bFM_GPIO_PDIRF_P6                         *((volatile  uint8_t *)(0x42DE6798UL))
#define bFM4_GPIO_PDIRF_P6                        *((volatile  uint8_t *)(0x42DE6798UL))
#define bFM_GPIO_PDIRF_P7                         *((volatile  uint8_t *)(0x42DE679CUL))
#define bFM4_GPIO_PDIRF_P7                        *((volatile  uint8_t *)(0x42DE679CUL))

#define bFM_GPIO_PDOR0_P0                         *((volatile  uint8_t *)(0x42DE8000UL))
#define bFM4_GPIO_PDOR0_P0                        *((volatile  uint8_t *)(0x42DE8000UL))
#define bFM_GPIO_PDOR0_P1                         *((volatile  uint8_t *)(0x42DE8004UL))
#define bFM4_GPIO_PDOR0_P1                        *((volatile  uint8_t *)(0x42DE8004UL))
#define bFM_GPIO_PDOR0_P2                         *((volatile  uint8_t *)(0x42DE8008UL))
#define bFM4_GPIO_PDOR0_P2                        *((volatile  uint8_t *)(0x42DE8008UL))
#define bFM_GPIO_PDOR0_P3                         *((volatile  uint8_t *)(0x42DE800CUL))
#define bFM4_GPIO_PDOR0_P3                        *((volatile  uint8_t *)(0x42DE800CUL))
#define bFM_GPIO_PDOR0_P4                         *((volatile  uint8_t *)(0x42DE8010UL))
#define bFM4_GPIO_PDOR0_P4                        *((volatile  uint8_t *)(0x42DE8010UL))
#define bFM_GPIO_PDOR0_P8                         *((volatile  uint8_t *)(0x42DE8020UL))
#define bFM4_GPIO_PDOR0_P8                        *((volatile  uint8_t *)(0x42DE8020UL))
#define bFM_GPIO_PDOR0_P9                         *((volatile  uint8_t *)(0x42DE8024UL))
#define bFM4_GPIO_PDOR0_P9                        *((volatile  uint8_t *)(0x42DE8024UL))
#define bFM_GPIO_PDOR0_PA                         *((volatile  uint8_t *)(0x42DE8028UL))
#define bFM4_GPIO_PDOR0_PA                        *((volatile  uint8_t *)(0x42DE8028UL))

#define bFM_GPIO_PDOR1_P0                         *((volatile  uint8_t *)(0x42DE8080UL))
#define bFM4_GPIO_PDOR1_P0                        *((volatile  uint8_t *)(0x42DE8080UL))
#define bFM_GPIO_PDOR1_P1                         *((volatile  uint8_t *)(0x42DE8084UL))
#define bFM4_GPIO_PDOR1_P1                        *((volatile  uint8_t *)(0x42DE8084UL))
#define bFM_GPIO_PDOR1_P2                         *((volatile  uint8_t *)(0x42DE8088UL))
#define bFM4_GPIO_PDOR1_P2                        *((volatile  uint8_t *)(0x42DE8088UL))
#define bFM_GPIO_PDOR1_P3                         *((volatile  uint8_t *)(0x42DE808CUL))
#define bFM4_GPIO_PDOR1_P3                        *((volatile  uint8_t *)(0x42DE808CUL))
#define bFM_GPIO_PDOR1_P4                         *((volatile  uint8_t *)(0x42DE8090UL))
#define bFM4_GPIO_PDOR1_P4                        *((volatile  uint8_t *)(0x42DE8090UL))
#define bFM_GPIO_PDOR1_P5                         *((volatile  uint8_t *)(0x42DE8094UL))
#define bFM4_GPIO_PDOR1_P5                        *((volatile  uint8_t *)(0x42DE8094UL))
#define bFM_GPIO_PDOR1_P6                         *((volatile  uint8_t *)(0x42DE8098UL))
#define bFM4_GPIO_PDOR1_P6                        *((volatile  uint8_t *)(0x42DE8098UL))
#define bFM_GPIO_PDOR1_P7                         *((volatile  uint8_t *)(0x42DE809CUL))
#define bFM4_GPIO_PDOR1_P7                        *((volatile  uint8_t *)(0x42DE809CUL))
#define bFM_GPIO_PDOR1_P8                         *((volatile  uint8_t *)(0x42DE80A0UL))
#define bFM4_GPIO_PDOR1_P8                        *((volatile  uint8_t *)(0x42DE80A0UL))
#define bFM_GPIO_PDOR1_P9                         *((volatile  uint8_t *)(0x42DE80A4UL))
#define bFM4_GPIO_PDOR1_P9                        *((volatile  uint8_t *)(0x42DE80A4UL))
#define bFM_GPIO_PDOR1_PA                         *((volatile  uint8_t *)(0x42DE80A8UL))
#define bFM4_GPIO_PDOR1_PA                        *((volatile  uint8_t *)(0x42DE80A8UL))
#define bFM_GPIO_PDOR1_PB                         *((volatile  uint8_t *)(0x42DE80ACUL))
#define bFM4_GPIO_PDOR1_PB                        *((volatile  uint8_t *)(0x42DE80ACUL))
#define bFM_GPIO_PDOR1_PC                         *((volatile  uint8_t *)(0x42DE80B0UL))
#define bFM4_GPIO_PDOR1_PC                        *((volatile  uint8_t *)(0x42DE80B0UL))
#define bFM_GPIO_PDOR1_PD                         *((volatile  uint8_t *)(0x42DE80B4UL))
#define bFM4_GPIO_PDOR1_PD                        *((volatile  uint8_t *)(0x42DE80B4UL))
#define bFM_GPIO_PDOR1_PE                         *((volatile  uint8_t *)(0x42DE80B8UL))
#define bFM4_GPIO_PDOR1_PE                        *((volatile  uint8_t *)(0x42DE80B8UL))
#define bFM_GPIO_PDOR1_PF                         *((volatile  uint8_t *)(0x42DE80BCUL))
#define bFM4_GPIO_PDOR1_PF                        *((volatile  uint8_t *)(0x42DE80BCUL))

#define bFM_GPIO_PDOR2_P0                         *((volatile  uint8_t *)(0x42DE8100UL))
#define bFM4_GPIO_PDOR2_P0                        *((volatile  uint8_t *)(0x42DE8100UL))
#define bFM_GPIO_PDOR2_P1                         *((volatile  uint8_t *)(0x42DE8104UL))
#define bFM4_GPIO_PDOR2_P1                        *((volatile  uint8_t *)(0x42DE8104UL))
#define bFM_GPIO_PDOR2_P2                         *((volatile  uint8_t *)(0x42DE8108UL))
#define bFM4_GPIO_PDOR2_P2                        *((volatile  uint8_t *)(0x42DE8108UL))
#define bFM_GPIO_PDOR2_P3                         *((volatile  uint8_t *)(0x42DE810CUL))
#define bFM4_GPIO_PDOR2_P3                        *((volatile  uint8_t *)(0x42DE810CUL))
#define bFM_GPIO_PDOR2_P4                         *((volatile  uint8_t *)(0x42DE8110UL))
#define bFM4_GPIO_PDOR2_P4                        *((volatile  uint8_t *)(0x42DE8110UL))
#define bFM_GPIO_PDOR2_P5                         *((volatile  uint8_t *)(0x42DE8114UL))
#define bFM4_GPIO_PDOR2_P5                        *((volatile  uint8_t *)(0x42DE8114UL))
#define bFM_GPIO_PDOR2_P6                         *((volatile  uint8_t *)(0x42DE8118UL))
#define bFM4_GPIO_PDOR2_P6                        *((volatile  uint8_t *)(0x42DE8118UL))
#define bFM_GPIO_PDOR2_P7                         *((volatile  uint8_t *)(0x42DE811CUL))
#define bFM4_GPIO_PDOR2_P7                        *((volatile  uint8_t *)(0x42DE811CUL))
#define bFM_GPIO_PDOR2_P8                         *((volatile  uint8_t *)(0x42DE8120UL))
#define bFM4_GPIO_PDOR2_P8                        *((volatile  uint8_t *)(0x42DE8120UL))
#define bFM_GPIO_PDOR2_P9                         *((volatile  uint8_t *)(0x42DE8124UL))
#define bFM4_GPIO_PDOR2_P9                        *((volatile  uint8_t *)(0x42DE8124UL))
#define bFM_GPIO_PDOR2_PA                         *((volatile  uint8_t *)(0x42DE8128UL))
#define bFM4_GPIO_PDOR2_PA                        *((volatile  uint8_t *)(0x42DE8128UL))

#define bFM_GPIO_PDOR3_P0                         *((volatile  uint8_t *)(0x42DE8180UL))
#define bFM4_GPIO_PDOR3_P0                        *((volatile  uint8_t *)(0x42DE8180UL))
#define bFM_GPIO_PDOR3_P1                         *((volatile  uint8_t *)(0x42DE8184UL))
#define bFM4_GPIO_PDOR3_P1                        *((volatile  uint8_t *)(0x42DE8184UL))
#define bFM_GPIO_PDOR3_P2                         *((volatile  uint8_t *)(0x42DE8188UL))
#define bFM4_GPIO_PDOR3_P2                        *((volatile  uint8_t *)(0x42DE8188UL))
#define bFM_GPIO_PDOR3_P3                         *((volatile  uint8_t *)(0x42DE818CUL))
#define bFM4_GPIO_PDOR3_P3                        *((volatile  uint8_t *)(0x42DE818CUL))
#define bFM_GPIO_PDOR3_P4                         *((volatile  uint8_t *)(0x42DE8190UL))
#define bFM4_GPIO_PDOR3_P4                        *((volatile  uint8_t *)(0x42DE8190UL))
#define bFM_GPIO_PDOR3_P5                         *((volatile  uint8_t *)(0x42DE8194UL))
#define bFM4_GPIO_PDOR3_P5                        *((volatile  uint8_t *)(0x42DE8194UL))
#define bFM_GPIO_PDOR3_P6                         *((volatile  uint8_t *)(0x42DE8198UL))
#define bFM4_GPIO_PDOR3_P6                        *((volatile  uint8_t *)(0x42DE8198UL))
#define bFM_GPIO_PDOR3_P7                         *((volatile  uint8_t *)(0x42DE819CUL))
#define bFM4_GPIO_PDOR3_P7                        *((volatile  uint8_t *)(0x42DE819CUL))
#define bFM_GPIO_PDOR3_P8                         *((volatile  uint8_t *)(0x42DE81A0UL))
#define bFM4_GPIO_PDOR3_P8                        *((volatile  uint8_t *)(0x42DE81A0UL))
#define bFM_GPIO_PDOR3_P9                         *((volatile  uint8_t *)(0x42DE81A4UL))
#define bFM4_GPIO_PDOR3_P9                        *((volatile  uint8_t *)(0x42DE81A4UL))
#define bFM_GPIO_PDOR3_PA                         *((volatile  uint8_t *)(0x42DE81A8UL))
#define bFM4_GPIO_PDOR3_PA                        *((volatile  uint8_t *)(0x42DE81A8UL))
#define bFM_GPIO_PDOR3_PB                         *((volatile  uint8_t *)(0x42DE81ACUL))
#define bFM4_GPIO_PDOR3_PB                        *((volatile  uint8_t *)(0x42DE81ACUL))
#define bFM_GPIO_PDOR3_PC                         *((volatile  uint8_t *)(0x42DE81B0UL))
#define bFM4_GPIO_PDOR3_PC                        *((volatile  uint8_t *)(0x42DE81B0UL))
#define bFM_GPIO_PDOR3_PD                         *((volatile  uint8_t *)(0x42DE81B4UL))
#define bFM4_GPIO_PDOR3_PD                        *((volatile  uint8_t *)(0x42DE81B4UL))
#define bFM_GPIO_PDOR3_PE                         *((volatile  uint8_t *)(0x42DE81B8UL))
#define bFM4_GPIO_PDOR3_PE                        *((volatile  uint8_t *)(0x42DE81B8UL))

#define bFM_GPIO_PDOR4_P0                         *((volatile  uint8_t *)(0x42DE8200UL))
#define bFM4_GPIO_PDOR4_P0                        *((volatile  uint8_t *)(0x42DE8200UL))
#define bFM_GPIO_PDOR4_P1                         *((volatile  uint8_t *)(0x42DE8204UL))
#define bFM4_GPIO_PDOR4_P1                        *((volatile  uint8_t *)(0x42DE8204UL))
#define bFM_GPIO_PDOR4_P2                         *((volatile  uint8_t *)(0x42DE8208UL))
#define bFM4_GPIO_PDOR4_P2                        *((volatile  uint8_t *)(0x42DE8208UL))
#define bFM_GPIO_PDOR4_P3                         *((volatile  uint8_t *)(0x42DE820CUL))
#define bFM4_GPIO_PDOR4_P3                        *((volatile  uint8_t *)(0x42DE820CUL))
#define bFM_GPIO_PDOR4_P4                         *((volatile  uint8_t *)(0x42DE8210UL))
#define bFM4_GPIO_PDOR4_P4                        *((volatile  uint8_t *)(0x42DE8210UL))
#define bFM_GPIO_PDOR4_P5                         *((volatile  uint8_t *)(0x42DE8214UL))
#define bFM4_GPIO_PDOR4_P5                        *((volatile  uint8_t *)(0x42DE8214UL))
#define bFM_GPIO_PDOR4_P6                         *((volatile  uint8_t *)(0x42DE8218UL))
#define bFM4_GPIO_PDOR4_P6                        *((volatile  uint8_t *)(0x42DE8218UL))
#define bFM_GPIO_PDOR4_P7                         *((volatile  uint8_t *)(0x42DE821CUL))
#define bFM4_GPIO_PDOR4_P7                        *((volatile  uint8_t *)(0x42DE821CUL))
#define bFM_GPIO_PDOR4_P8                         *((volatile  uint8_t *)(0x42DE8220UL))
#define bFM4_GPIO_PDOR4_P8                        *((volatile  uint8_t *)(0x42DE8220UL))
#define bFM_GPIO_PDOR4_P9                         *((volatile  uint8_t *)(0x42DE8224UL))
#define bFM4_GPIO_PDOR4_P9                        *((volatile  uint8_t *)(0x42DE8224UL))

#define bFM_GPIO_PDOR5_P0                         *((volatile  uint8_t *)(0x42DE8280UL))
#define bFM4_GPIO_PDOR5_P0                        *((volatile  uint8_t *)(0x42DE8280UL))
#define bFM_GPIO_PDOR5_P1                         *((volatile  uint8_t *)(0x42DE8284UL))
#define bFM4_GPIO_PDOR5_P1                        *((volatile  uint8_t *)(0x42DE8284UL))
#define bFM_GPIO_PDOR5_P2                         *((volatile  uint8_t *)(0x42DE8288UL))
#define bFM4_GPIO_PDOR5_P2                        *((volatile  uint8_t *)(0x42DE8288UL))
#define bFM_GPIO_PDOR5_PD                         *((volatile  uint8_t *)(0x42DE82B4UL))
#define bFM4_GPIO_PDOR5_PD                        *((volatile  uint8_t *)(0x42DE82B4UL))
#define bFM_GPIO_PDOR5_PE                         *((volatile  uint8_t *)(0x42DE82B8UL))
#define bFM4_GPIO_PDOR5_PE                        *((volatile  uint8_t *)(0x42DE82B8UL))
#define bFM_GPIO_PDOR5_PF                         *((volatile  uint8_t *)(0x42DE82BCUL))
#define bFM4_GPIO_PDOR5_PF                        *((volatile  uint8_t *)(0x42DE82BCUL))

#define bFM_GPIO_PDOR6_P0                         *((volatile  uint8_t *)(0x42DE8300UL))
#define bFM4_GPIO_PDOR6_P0                        *((volatile  uint8_t *)(0x42DE8300UL))
#define bFM_GPIO_PDOR6_P1                         *((volatile  uint8_t *)(0x42DE8304UL))
#define bFM4_GPIO_PDOR6_P1                        *((volatile  uint8_t *)(0x42DE8304UL))
#define bFM_GPIO_PDOR6_P2                         *((volatile  uint8_t *)(0x42DE8308UL))
#define bFM4_GPIO_PDOR6_P2                        *((volatile  uint8_t *)(0x42DE8308UL))
#define bFM_GPIO_PDOR6_P3                         *((volatile  uint8_t *)(0x42DE830CUL))
#define bFM4_GPIO_PDOR6_P3                        *((volatile  uint8_t *)(0x42DE830CUL))
#define bFM_GPIO_PDOR6_P4                         *((volatile  uint8_t *)(0x42DE8310UL))
#define bFM4_GPIO_PDOR6_P4                        *((volatile  uint8_t *)(0x42DE8310UL))
#define bFM_GPIO_PDOR6_P5                         *((volatile  uint8_t *)(0x42DE8314UL))
#define bFM4_GPIO_PDOR6_P5                        *((volatile  uint8_t *)(0x42DE8314UL))
#define bFM_GPIO_PDOR6_PE                         *((volatile  uint8_t *)(0x42DE8338UL))
#define bFM4_GPIO_PDOR6_PE                        *((volatile  uint8_t *)(0x42DE8338UL))

#define bFM_GPIO_PDOR7_P0                         *((volatile  uint8_t *)(0x42DE8380UL))
#define bFM4_GPIO_PDOR7_P0                        *((volatile  uint8_t *)(0x42DE8380UL))
#define bFM_GPIO_PDOR7_P1                         *((volatile  uint8_t *)(0x42DE8384UL))
#define bFM4_GPIO_PDOR7_P1                        *((volatile  uint8_t *)(0x42DE8384UL))
#define bFM_GPIO_PDOR7_P2                         *((volatile  uint8_t *)(0x42DE8388UL))
#define bFM4_GPIO_PDOR7_P2                        *((volatile  uint8_t *)(0x42DE8388UL))
#define bFM_GPIO_PDOR7_P3                         *((volatile  uint8_t *)(0x42DE838CUL))
#define bFM4_GPIO_PDOR7_P3                        *((volatile  uint8_t *)(0x42DE838CUL))
#define bFM_GPIO_PDOR7_P4                         *((volatile  uint8_t *)(0x42DE8390UL))
#define bFM4_GPIO_PDOR7_P4                        *((volatile  uint8_t *)(0x42DE8390UL))
#define bFM_GPIO_PDOR7_P5                         *((volatile  uint8_t *)(0x42DE8394UL))
#define bFM4_GPIO_PDOR7_P5                        *((volatile  uint8_t *)(0x42DE8394UL))
#define bFM_GPIO_PDOR7_P6                         *((volatile  uint8_t *)(0x42DE8398UL))
#define bFM4_GPIO_PDOR7_P6                        *((volatile  uint8_t *)(0x42DE8398UL))
#define bFM_GPIO_PDOR7_P7                         *((volatile  uint8_t *)(0x42DE839CUL))
#define bFM4_GPIO_PDOR7_P7                        *((volatile  uint8_t *)(0x42DE839CUL))
#define bFM_GPIO_PDOR7_P8                         *((volatile  uint8_t *)(0x42DE83A0UL))
#define bFM4_GPIO_PDOR7_P8                        *((volatile  uint8_t *)(0x42DE83A0UL))
#define bFM_GPIO_PDOR7_P9                         *((volatile  uint8_t *)(0x42DE83A4UL))
#define bFM4_GPIO_PDOR7_P9                        *((volatile  uint8_t *)(0x42DE83A4UL))
#define bFM_GPIO_PDOR7_PA                         *((volatile  uint8_t *)(0x42DE83A8UL))
#define bFM4_GPIO_PDOR7_PA                        *((volatile  uint8_t *)(0x42DE83A8UL))
#define bFM_GPIO_PDOR7_PB                         *((volatile  uint8_t *)(0x42DE83ACUL))
#define bFM4_GPIO_PDOR7_PB                        *((volatile  uint8_t *)(0x42DE83ACUL))
#define bFM_GPIO_PDOR7_PC                         *((volatile  uint8_t *)(0x42DE83B0UL))
#define bFM4_GPIO_PDOR7_PC                        *((volatile  uint8_t *)(0x42DE83B0UL))
#define bFM_GPIO_PDOR7_PD                         *((volatile  uint8_t *)(0x42DE83B4UL))
#define bFM4_GPIO_PDOR7_PD                        *((volatile  uint8_t *)(0x42DE83B4UL))
#define bFM_GPIO_PDOR7_PE                         *((volatile  uint8_t *)(0x42DE83B8UL))
#define bFM4_GPIO_PDOR7_PE                        *((volatile  uint8_t *)(0x42DE83B8UL))

#define bFM_GPIO_PDOR8_P0                         *((volatile  uint8_t *)(0x42DE8400UL))
#define bFM4_GPIO_PDOR8_P0                        *((volatile  uint8_t *)(0x42DE8400UL))
#define bFM_GPIO_PDOR8_P1                         *((volatile  uint8_t *)(0x42DE8404UL))
#define bFM4_GPIO_PDOR8_P1                        *((volatile  uint8_t *)(0x42DE8404UL))
#define bFM_GPIO_PDOR8_P2                         *((volatile  uint8_t *)(0x42DE8408UL))
#define bFM4_GPIO_PDOR8_P2                        *((volatile  uint8_t *)(0x42DE8408UL))
#define bFM_GPIO_PDOR8_P3                         *((volatile  uint8_t *)(0x42DE840CUL))
#define bFM4_GPIO_PDOR8_P3                        *((volatile  uint8_t *)(0x42DE840CUL))

#define bFM_GPIO_PDOR9_P0                         *((volatile  uint8_t *)(0x42DE8480UL))
#define bFM4_GPIO_PDOR9_P0                        *((volatile  uint8_t *)(0x42DE8480UL))
#define bFM_GPIO_PDOR9_P1                         *((volatile  uint8_t *)(0x42DE8484UL))
#define bFM4_GPIO_PDOR9_P1                        *((volatile  uint8_t *)(0x42DE8484UL))
#define bFM_GPIO_PDOR9_P2                         *((volatile  uint8_t *)(0x42DE8488UL))
#define bFM4_GPIO_PDOR9_P2                        *((volatile  uint8_t *)(0x42DE8488UL))
#define bFM_GPIO_PDOR9_P3                         *((volatile  uint8_t *)(0x42DE848CUL))
#define bFM4_GPIO_PDOR9_P3                        *((volatile  uint8_t *)(0x42DE848CUL))
#define bFM_GPIO_PDOR9_P4                         *((volatile  uint8_t *)(0x42DE8490UL))
#define bFM4_GPIO_PDOR9_P4                        *((volatile  uint8_t *)(0x42DE8490UL))
#define bFM_GPIO_PDOR9_P5                         *((volatile  uint8_t *)(0x42DE8494UL))
#define bFM4_GPIO_PDOR9_P5                        *((volatile  uint8_t *)(0x42DE8494UL))

#define bFM_GPIO_PDORA_P0                         *((volatile  uint8_t *)(0x42DE8500UL))
#define bFM4_GPIO_PDORA_P0                        *((volatile  uint8_t *)(0x42DE8500UL))
#define bFM_GPIO_PDORA_P1                         *((volatile  uint8_t *)(0x42DE8504UL))
#define bFM4_GPIO_PDORA_P1                        *((volatile  uint8_t *)(0x42DE8504UL))
#define bFM_GPIO_PDORA_P2                         *((volatile  uint8_t *)(0x42DE8508UL))
#define bFM4_GPIO_PDORA_P2                        *((volatile  uint8_t *)(0x42DE8508UL))
#define bFM_GPIO_PDORA_P3                         *((volatile  uint8_t *)(0x42DE850CUL))
#define bFM4_GPIO_PDORA_P3                        *((volatile  uint8_t *)(0x42DE850CUL))
#define bFM_GPIO_PDORA_P4                         *((volatile  uint8_t *)(0x42DE8510UL))
#define bFM4_GPIO_PDORA_P4                        *((volatile  uint8_t *)(0x42DE8510UL))
#define bFM_GPIO_PDORA_P5                         *((volatile  uint8_t *)(0x42DE8514UL))
#define bFM4_GPIO_PDORA_P5                        *((volatile  uint8_t *)(0x42DE8514UL))
#define bFM_GPIO_PDORA_P6                         *((volatile  uint8_t *)(0x42DE8518UL))
#define bFM4_GPIO_PDORA_P6                        *((volatile  uint8_t *)(0x42DE8518UL))
#define bFM_GPIO_PDORA_P7                         *((volatile  uint8_t *)(0x42DE851CUL))
#define bFM4_GPIO_PDORA_P7                        *((volatile  uint8_t *)(0x42DE851CUL))
#define bFM_GPIO_PDORA_P8                         *((volatile  uint8_t *)(0x42DE8520UL))
#define bFM4_GPIO_PDORA_P8                        *((volatile  uint8_t *)(0x42DE8520UL))
#define bFM_GPIO_PDORA_P9                         *((volatile  uint8_t *)(0x42DE8524UL))
#define bFM4_GPIO_PDORA_P9                        *((volatile  uint8_t *)(0x42DE8524UL))
#define bFM_GPIO_PDORA_PA                         *((volatile  uint8_t *)(0x42DE8528UL))
#define bFM4_GPIO_PDORA_PA                        *((volatile  uint8_t *)(0x42DE8528UL))
#define bFM_GPIO_PDORA_PB                         *((volatile  uint8_t *)(0x42DE852CUL))
#define bFM4_GPIO_PDORA_PB                        *((volatile  uint8_t *)(0x42DE852CUL))
#define bFM_GPIO_PDORA_PC                         *((volatile  uint8_t *)(0x42DE8530UL))
#define bFM4_GPIO_PDORA_PC                        *((volatile  uint8_t *)(0x42DE8530UL))
#define bFM_GPIO_PDORA_PD                         *((volatile  uint8_t *)(0x42DE8534UL))
#define bFM4_GPIO_PDORA_PD                        *((volatile  uint8_t *)(0x42DE8534UL))
#define bFM_GPIO_PDORA_PE                         *((volatile  uint8_t *)(0x42DE8538UL))
#define bFM4_GPIO_PDORA_PE                        *((volatile  uint8_t *)(0x42DE8538UL))
#define bFM_GPIO_PDORA_PF                         *((volatile  uint8_t *)(0x42DE853CUL))
#define bFM4_GPIO_PDORA_PF                        *((volatile  uint8_t *)(0x42DE853CUL))

#define bFM_GPIO_PDORB_P0                         *((volatile  uint8_t *)(0x42DE8580UL))
#define bFM4_GPIO_PDORB_P0                        *((volatile  uint8_t *)(0x42DE8580UL))
#define bFM_GPIO_PDORB_P1                         *((volatile  uint8_t *)(0x42DE8584UL))
#define bFM4_GPIO_PDORB_P1                        *((volatile  uint8_t *)(0x42DE8584UL))
#define bFM_GPIO_PDORB_P2                         *((volatile  uint8_t *)(0x42DE8588UL))
#define bFM4_GPIO_PDORB_P2                        *((volatile  uint8_t *)(0x42DE8588UL))
#define bFM_GPIO_PDORB_P3                         *((volatile  uint8_t *)(0x42DE858CUL))
#define bFM4_GPIO_PDORB_P3                        *((volatile  uint8_t *)(0x42DE858CUL))
#define bFM_GPIO_PDORB_P4                         *((volatile  uint8_t *)(0x42DE8590UL))
#define bFM4_GPIO_PDORB_P4                        *((volatile  uint8_t *)(0x42DE8590UL))
#define bFM_GPIO_PDORB_P5                         *((volatile  uint8_t *)(0x42DE8594UL))
#define bFM4_GPIO_PDORB_P5                        *((volatile  uint8_t *)(0x42DE8594UL))
#define bFM_GPIO_PDORB_P6                         *((volatile  uint8_t *)(0x42DE8598UL))
#define bFM4_GPIO_PDORB_P6                        *((volatile  uint8_t *)(0x42DE8598UL))
#define bFM_GPIO_PDORB_P7                         *((volatile  uint8_t *)(0x42DE859CUL))
#define bFM4_GPIO_PDORB_P7                        *((volatile  uint8_t *)(0x42DE859CUL))

#define bFM_GPIO_PDORC_P0                         *((volatile  uint8_t *)(0x42DE8600UL))
#define bFM4_GPIO_PDORC_P0                        *((volatile  uint8_t *)(0x42DE8600UL))
#define bFM_GPIO_PDORC_P1                         *((volatile  uint8_t *)(0x42DE8604UL))
#define bFM4_GPIO_PDORC_P1                        *((volatile  uint8_t *)(0x42DE8604UL))
#define bFM_GPIO_PDORC_P2                         *((volatile  uint8_t *)(0x42DE8608UL))
#define bFM4_GPIO_PDORC_P2                        *((volatile  uint8_t *)(0x42DE8608UL))
#define bFM_GPIO_PDORC_P3                         *((volatile  uint8_t *)(0x42DE860CUL))
#define bFM4_GPIO_PDORC_P3                        *((volatile  uint8_t *)(0x42DE860CUL))
#define bFM_GPIO_PDORC_P4                         *((volatile  uint8_t *)(0x42DE8610UL))
#define bFM4_GPIO_PDORC_P4                        *((volatile  uint8_t *)(0x42DE8610UL))
#define bFM_GPIO_PDORC_P5                         *((volatile  uint8_t *)(0x42DE8614UL))
#define bFM4_GPIO_PDORC_P5                        *((volatile  uint8_t *)(0x42DE8614UL))
#define bFM_GPIO_PDORC_P6                         *((volatile  uint8_t *)(0x42DE8618UL))
#define bFM4_GPIO_PDORC_P6                        *((volatile  uint8_t *)(0x42DE8618UL))
#define bFM_GPIO_PDORC_P7                         *((volatile  uint8_t *)(0x42DE861CUL))
#define bFM4_GPIO_PDORC_P7                        *((volatile  uint8_t *)(0x42DE861CUL))
#define bFM_GPIO_PDORC_P8                         *((volatile  uint8_t *)(0x42DE8620UL))
#define bFM4_GPIO_PDORC_P8                        *((volatile  uint8_t *)(0x42DE8620UL))
#define bFM_GPIO_PDORC_P9                         *((volatile  uint8_t *)(0x42DE8624UL))
#define bFM4_GPIO_PDORC_P9                        *((volatile  uint8_t *)(0x42DE8624UL))
#define bFM_GPIO_PDORC_PA                         *((volatile  uint8_t *)(0x42DE8628UL))
#define bFM4_GPIO_PDORC_PA                        *((volatile  uint8_t *)(0x42DE8628UL))
#define bFM_GPIO_PDORC_PB                         *((volatile  uint8_t *)(0x42DE862CUL))
#define bFM4_GPIO_PDORC_PB                        *((volatile  uint8_t *)(0x42DE862CUL))
#define bFM_GPIO_PDORC_PC                         *((volatile  uint8_t *)(0x42DE8630UL))
#define bFM4_GPIO_PDORC_PC                        *((volatile  uint8_t *)(0x42DE8630UL))
#define bFM_GPIO_PDORC_PD                         *((volatile  uint8_t *)(0x42DE8634UL))
#define bFM4_GPIO_PDORC_PD                        *((volatile  uint8_t *)(0x42DE8634UL))
#define bFM_GPIO_PDORC_PE                         *((volatile  uint8_t *)(0x42DE8638UL))
#define bFM4_GPIO_PDORC_PE                        *((volatile  uint8_t *)(0x42DE8638UL))
#define bFM_GPIO_PDORC_PF                         *((volatile  uint8_t *)(0x42DE863CUL))
#define bFM4_GPIO_PDORC_PF                        *((volatile  uint8_t *)(0x42DE863CUL))

#define bFM_GPIO_PDORD_P0                         *((volatile  uint8_t *)(0x42DE8680UL))
#define bFM4_GPIO_PDORD_P0                        *((volatile  uint8_t *)(0x42DE8680UL))
#define bFM_GPIO_PDORD_P1                         *((volatile  uint8_t *)(0x42DE8684UL))
#define bFM4_GPIO_PDORD_P1                        *((volatile  uint8_t *)(0x42DE8684UL))
#define bFM_GPIO_PDORD_P2                         *((volatile  uint8_t *)(0x42DE8688UL))
#define bFM4_GPIO_PDORD_P2                        *((volatile  uint8_t *)(0x42DE8688UL))

#define bFM_GPIO_PDORE_P0                         *((volatile  uint8_t *)(0x42DE8700UL))
#define bFM4_GPIO_PDORE_P0                        *((volatile  uint8_t *)(0x42DE8700UL))
#define bFM_GPIO_PDORE_P2                         *((volatile  uint8_t *)(0x42DE8708UL))
#define bFM4_GPIO_PDORE_P2                        *((volatile  uint8_t *)(0x42DE8708UL))
#define bFM_GPIO_PDORE_P3                         *((volatile  uint8_t *)(0x42DE870CUL))
#define bFM4_GPIO_PDORE_P3                        *((volatile  uint8_t *)(0x42DE870CUL))

#define bFM_GPIO_PDORF_P0                         *((volatile  uint8_t *)(0x42DE8780UL))
#define bFM4_GPIO_PDORF_P0                        *((volatile  uint8_t *)(0x42DE8780UL))
#define bFM_GPIO_PDORF_P1                         *((volatile  uint8_t *)(0x42DE8784UL))
#define bFM4_GPIO_PDORF_P1                        *((volatile  uint8_t *)(0x42DE8784UL))
#define bFM_GPIO_PDORF_P2                         *((volatile  uint8_t *)(0x42DE8788UL))
#define bFM4_GPIO_PDORF_P2                        *((volatile  uint8_t *)(0x42DE8788UL))
#define bFM_GPIO_PDORF_P3                         *((volatile  uint8_t *)(0x42DE878CUL))
#define bFM4_GPIO_PDORF_P3                        *((volatile  uint8_t *)(0x42DE878CUL))
#define bFM_GPIO_PDORF_P4                         *((volatile  uint8_t *)(0x42DE8790UL))
#define bFM4_GPIO_PDORF_P4                        *((volatile  uint8_t *)(0x42DE8790UL))
#define bFM_GPIO_PDORF_P5                         *((volatile  uint8_t *)(0x42DE8794UL))
#define bFM4_GPIO_PDORF_P5                        *((volatile  uint8_t *)(0x42DE8794UL))
#define bFM_GPIO_PDORF_P6                         *((volatile  uint8_t *)(0x42DE8798UL))
#define bFM4_GPIO_PDORF_P6                        *((volatile  uint8_t *)(0x42DE8798UL))
#define bFM_GPIO_PDORF_P7                         *((volatile  uint8_t *)(0x42DE879CUL))
#define bFM4_GPIO_PDORF_P7                        *((volatile  uint8_t *)(0x42DE879CUL))

#define bFM_GPIO_PDSR0_P0                         *((volatile  uint8_t *)(0x42DEE800UL))
#define bFM4_GPIO_PDSR0_P0                        *((volatile  uint8_t *)(0x42DEE800UL))
#define bFM_GPIO_PDSR0_P1                         *((volatile  uint8_t *)(0x42DEE804UL))
#define bFM4_GPIO_PDSR0_P1                        *((volatile  uint8_t *)(0x42DEE804UL))
#define bFM_GPIO_PDSR0_P2                         *((volatile  uint8_t *)(0x42DEE808UL))
#define bFM4_GPIO_PDSR0_P2                        *((volatile  uint8_t *)(0x42DEE808UL))
#define bFM_GPIO_PDSR0_P3                         *((volatile  uint8_t *)(0x42DEE80CUL))
#define bFM4_GPIO_PDSR0_P3                        *((volatile  uint8_t *)(0x42DEE80CUL))
#define bFM_GPIO_PDSR0_P4                         *((volatile  uint8_t *)(0x42DEE810UL))
#define bFM4_GPIO_PDSR0_P4                        *((volatile  uint8_t *)(0x42DEE810UL))
#define bFM_GPIO_PDSR0_P8                         *((volatile  uint8_t *)(0x42DEE820UL))
#define bFM4_GPIO_PDSR0_P8                        *((volatile  uint8_t *)(0x42DEE820UL))
#define bFM_GPIO_PDSR0_P9                         *((volatile  uint8_t *)(0x42DEE824UL))
#define bFM4_GPIO_PDSR0_P9                        *((volatile  uint8_t *)(0x42DEE824UL))
#define bFM_GPIO_PDSR0_PA                         *((volatile  uint8_t *)(0x42DEE828UL))
#define bFM4_GPIO_PDSR0_PA                        *((volatile  uint8_t *)(0x42DEE828UL))

#define bFM_GPIO_PDSR1_P0                         *((volatile  uint8_t *)(0x42DEE880UL))
#define bFM4_GPIO_PDSR1_P0                        *((volatile  uint8_t *)(0x42DEE880UL))
#define bFM_GPIO_PDSR1_P1                         *((volatile  uint8_t *)(0x42DEE884UL))
#define bFM4_GPIO_PDSR1_P1                        *((volatile  uint8_t *)(0x42DEE884UL))
#define bFM_GPIO_PDSR1_P2                         *((volatile  uint8_t *)(0x42DEE888UL))
#define bFM4_GPIO_PDSR1_P2                        *((volatile  uint8_t *)(0x42DEE888UL))
#define bFM_GPIO_PDSR1_P3                         *((volatile  uint8_t *)(0x42DEE88CUL))
#define bFM4_GPIO_PDSR1_P3                        *((volatile  uint8_t *)(0x42DEE88CUL))
#define bFM_GPIO_PDSR1_P4                         *((volatile  uint8_t *)(0x42DEE890UL))
#define bFM4_GPIO_PDSR1_P4                        *((volatile  uint8_t *)(0x42DEE890UL))
#define bFM_GPIO_PDSR1_P5                         *((volatile  uint8_t *)(0x42DEE894UL))
#define bFM4_GPIO_PDSR1_P5                        *((volatile  uint8_t *)(0x42DEE894UL))
#define bFM_GPIO_PDSR1_P6                         *((volatile  uint8_t *)(0x42DEE898UL))
#define bFM4_GPIO_PDSR1_P6                        *((volatile  uint8_t *)(0x42DEE898UL))
#define bFM_GPIO_PDSR1_P7                         *((volatile  uint8_t *)(0x42DEE89CUL))
#define bFM4_GPIO_PDSR1_P7                        *((volatile  uint8_t *)(0x42DEE89CUL))
#define bFM_GPIO_PDSR1_P8                         *((volatile  uint8_t *)(0x42DEE8A0UL))
#define bFM4_GPIO_PDSR1_P8                        *((volatile  uint8_t *)(0x42DEE8A0UL))
#define bFM_GPIO_PDSR1_P9                         *((volatile  uint8_t *)(0x42DEE8A4UL))
#define bFM4_GPIO_PDSR1_P9                        *((volatile  uint8_t *)(0x42DEE8A4UL))
#define bFM_GPIO_PDSR1_PA                         *((volatile  uint8_t *)(0x42DEE8A8UL))
#define bFM4_GPIO_PDSR1_PA                        *((volatile  uint8_t *)(0x42DEE8A8UL))
#define bFM_GPIO_PDSR1_PB                         *((volatile  uint8_t *)(0x42DEE8ACUL))
#define bFM4_GPIO_PDSR1_PB                        *((volatile  uint8_t *)(0x42DEE8ACUL))
#define bFM_GPIO_PDSR1_PC                         *((volatile  uint8_t *)(0x42DEE8B0UL))
#define bFM4_GPIO_PDSR1_PC                        *((volatile  uint8_t *)(0x42DEE8B0UL))
#define bFM_GPIO_PDSR1_PD                         *((volatile  uint8_t *)(0x42DEE8B4UL))
#define bFM4_GPIO_PDSR1_PD                        *((volatile  uint8_t *)(0x42DEE8B4UL))
#define bFM_GPIO_PDSR1_PE                         *((volatile  uint8_t *)(0x42DEE8B8UL))
#define bFM4_GPIO_PDSR1_PE                        *((volatile  uint8_t *)(0x42DEE8B8UL))
#define bFM_GPIO_PDSR1_PF                         *((volatile  uint8_t *)(0x42DEE8BCUL))
#define bFM4_GPIO_PDSR1_PF                        *((volatile  uint8_t *)(0x42DEE8BCUL))

#define bFM_GPIO_PDSR2_P0                         *((volatile  uint8_t *)(0x42DEE900UL))
#define bFM4_GPIO_PDSR2_P0                        *((volatile  uint8_t *)(0x42DEE900UL))
#define bFM_GPIO_PDSR2_P1                         *((volatile  uint8_t *)(0x42DEE904UL))
#define bFM4_GPIO_PDSR2_P1                        *((volatile  uint8_t *)(0x42DEE904UL))
#define bFM_GPIO_PDSR2_P2                         *((volatile  uint8_t *)(0x42DEE908UL))
#define bFM4_GPIO_PDSR2_P2                        *((volatile  uint8_t *)(0x42DEE908UL))
#define bFM_GPIO_PDSR2_P3                         *((volatile  uint8_t *)(0x42DEE90CUL))
#define bFM4_GPIO_PDSR2_P3                        *((volatile  uint8_t *)(0x42DEE90CUL))
#define bFM_GPIO_PDSR2_P4                         *((volatile  uint8_t *)(0x42DEE910UL))
#define bFM4_GPIO_PDSR2_P4                        *((volatile  uint8_t *)(0x42DEE910UL))
#define bFM_GPIO_PDSR2_P5                         *((volatile  uint8_t *)(0x42DEE914UL))
#define bFM4_GPIO_PDSR2_P5                        *((volatile  uint8_t *)(0x42DEE914UL))
#define bFM_GPIO_PDSR2_P6                         *((volatile  uint8_t *)(0x42DEE918UL))
#define bFM4_GPIO_PDSR2_P6                        *((volatile  uint8_t *)(0x42DEE918UL))
#define bFM_GPIO_PDSR2_P7                         *((volatile  uint8_t *)(0x42DEE91CUL))
#define bFM4_GPIO_PDSR2_P7                        *((volatile  uint8_t *)(0x42DEE91CUL))
#define bFM_GPIO_PDSR2_P8                         *((volatile  uint8_t *)(0x42DEE920UL))
#define bFM4_GPIO_PDSR2_P8                        *((volatile  uint8_t *)(0x42DEE920UL))
#define bFM_GPIO_PDSR2_P9                         *((volatile  uint8_t *)(0x42DEE924UL))
#define bFM4_GPIO_PDSR2_P9                        *((volatile  uint8_t *)(0x42DEE924UL))
#define bFM_GPIO_PDSR2_PA                         *((volatile  uint8_t *)(0x42DEE928UL))
#define bFM4_GPIO_PDSR2_PA                        *((volatile  uint8_t *)(0x42DEE928UL))

#define bFM_GPIO_PDSR3_P0                         *((volatile  uint8_t *)(0x42DEE980UL))
#define bFM4_GPIO_PDSR3_P0                        *((volatile  uint8_t *)(0x42DEE980UL))
#define bFM_GPIO_PDSR3_P1                         *((volatile  uint8_t *)(0x42DEE984UL))
#define bFM4_GPIO_PDSR3_P1                        *((volatile  uint8_t *)(0x42DEE984UL))
#define bFM_GPIO_PDSR3_P2                         *((volatile  uint8_t *)(0x42DEE988UL))
#define bFM4_GPIO_PDSR3_P2                        *((volatile  uint8_t *)(0x42DEE988UL))
#define bFM_GPIO_PDSR3_P3                         *((volatile  uint8_t *)(0x42DEE98CUL))
#define bFM4_GPIO_PDSR3_P3                        *((volatile  uint8_t *)(0x42DEE98CUL))
#define bFM_GPIO_PDSR3_P4                         *((volatile  uint8_t *)(0x42DEE990UL))
#define bFM4_GPIO_PDSR3_P4                        *((volatile  uint8_t *)(0x42DEE990UL))
#define bFM_GPIO_PDSR3_P5                         *((volatile  uint8_t *)(0x42DEE994UL))
#define bFM4_GPIO_PDSR3_P5                        *((volatile  uint8_t *)(0x42DEE994UL))
#define bFM_GPIO_PDSR3_P6                         *((volatile  uint8_t *)(0x42DEE998UL))
#define bFM4_GPIO_PDSR3_P6                        *((volatile  uint8_t *)(0x42DEE998UL))
#define bFM_GPIO_PDSR3_P7                         *((volatile  uint8_t *)(0x42DEE99CUL))
#define bFM4_GPIO_PDSR3_P7                        *((volatile  uint8_t *)(0x42DEE99CUL))
#define bFM_GPIO_PDSR3_P8                         *((volatile  uint8_t *)(0x42DEE9A0UL))
#define bFM4_GPIO_PDSR3_P8                        *((volatile  uint8_t *)(0x42DEE9A0UL))
#define bFM_GPIO_PDSR3_P9                         *((volatile  uint8_t *)(0x42DEE9A4UL))
#define bFM4_GPIO_PDSR3_P9                        *((volatile  uint8_t *)(0x42DEE9A4UL))
#define bFM_GPIO_PDSR3_PA                         *((volatile  uint8_t *)(0x42DEE9A8UL))
#define bFM4_GPIO_PDSR3_PA                        *((volatile  uint8_t *)(0x42DEE9A8UL))
#define bFM_GPIO_PDSR3_PB                         *((volatile  uint8_t *)(0x42DEE9ACUL))
#define bFM4_GPIO_PDSR3_PB                        *((volatile  uint8_t *)(0x42DEE9ACUL))
#define bFM_GPIO_PDSR3_PC                         *((volatile  uint8_t *)(0x42DEE9B0UL))
#define bFM4_GPIO_PDSR3_PC                        *((volatile  uint8_t *)(0x42DEE9B0UL))
#define bFM_GPIO_PDSR3_PD                         *((volatile  uint8_t *)(0x42DEE9B4UL))
#define bFM4_GPIO_PDSR3_PD                        *((volatile  uint8_t *)(0x42DEE9B4UL))
#define bFM_GPIO_PDSR3_PE                         *((volatile  uint8_t *)(0x42DEE9B8UL))
#define bFM4_GPIO_PDSR3_PE                        *((volatile  uint8_t *)(0x42DEE9B8UL))

#define bFM_GPIO_PDSR4_P0                         *((volatile  uint8_t *)(0x42DEEA00UL))
#define bFM4_GPIO_PDSR4_P0                        *((volatile  uint8_t *)(0x42DEEA00UL))
#define bFM_GPIO_PDSR4_P1                         *((volatile  uint8_t *)(0x42DEEA04UL))
#define bFM4_GPIO_PDSR4_P1                        *((volatile  uint8_t *)(0x42DEEA04UL))
#define bFM_GPIO_PDSR4_P2                         *((volatile  uint8_t *)(0x42DEEA08UL))
#define bFM4_GPIO_PDSR4_P2                        *((volatile  uint8_t *)(0x42DEEA08UL))
#define bFM_GPIO_PDSR4_P3                         *((volatile  uint8_t *)(0x42DEEA0CUL))
#define bFM4_GPIO_PDSR4_P3                        *((volatile  uint8_t *)(0x42DEEA0CUL))
#define bFM_GPIO_PDSR4_P4                         *((volatile  uint8_t *)(0x42DEEA10UL))
#define bFM4_GPIO_PDSR4_P4                        *((volatile  uint8_t *)(0x42DEEA10UL))
#define bFM_GPIO_PDSR4_P5                         *((volatile  uint8_t *)(0x42DEEA14UL))
#define bFM4_GPIO_PDSR4_P5                        *((volatile  uint8_t *)(0x42DEEA14UL))
#define bFM_GPIO_PDSR4_P6                         *((volatile  uint8_t *)(0x42DEEA18UL))
#define bFM4_GPIO_PDSR4_P6                        *((volatile  uint8_t *)(0x42DEEA18UL))
#define bFM_GPIO_PDSR4_P7                         *((volatile  uint8_t *)(0x42DEEA1CUL))
#define bFM4_GPIO_PDSR4_P7                        *((volatile  uint8_t *)(0x42DEEA1CUL))
#define bFM_GPIO_PDSR4_P8                         *((volatile  uint8_t *)(0x42DEEA20UL))
#define bFM4_GPIO_PDSR4_P8                        *((volatile  uint8_t *)(0x42DEEA20UL))
#define bFM_GPIO_PDSR4_P9                         *((volatile  uint8_t *)(0x42DEEA24UL))
#define bFM4_GPIO_PDSR4_P9                        *((volatile  uint8_t *)(0x42DEEA24UL))

#define bFM_GPIO_PDSR5_P0                         *((volatile  uint8_t *)(0x42DEEA80UL))
#define bFM4_GPIO_PDSR5_P0                        *((volatile  uint8_t *)(0x42DEEA80UL))
#define bFM_GPIO_PDSR5_P1                         *((volatile  uint8_t *)(0x42DEEA84UL))
#define bFM4_GPIO_PDSR5_P1                        *((volatile  uint8_t *)(0x42DEEA84UL))
#define bFM_GPIO_PDSR5_P2                         *((volatile  uint8_t *)(0x42DEEA88UL))
#define bFM4_GPIO_PDSR5_P2                        *((volatile  uint8_t *)(0x42DEEA88UL))
#define bFM_GPIO_PDSR5_PD                         *((volatile  uint8_t *)(0x42DEEAB4UL))
#define bFM4_GPIO_PDSR5_PD                        *((volatile  uint8_t *)(0x42DEEAB4UL))
#define bFM_GPIO_PDSR5_PE                         *((volatile  uint8_t *)(0x42DEEAB8UL))
#define bFM4_GPIO_PDSR5_PE                        *((volatile  uint8_t *)(0x42DEEAB8UL))
#define bFM_GPIO_PDSR5_PF                         *((volatile  uint8_t *)(0x42DEEABCUL))
#define bFM4_GPIO_PDSR5_PF                        *((volatile  uint8_t *)(0x42DEEABCUL))

#define bFM_GPIO_PDSR6_P0                         *((volatile  uint8_t *)(0x42DEEB00UL))
#define bFM4_GPIO_PDSR6_P0                        *((volatile  uint8_t *)(0x42DEEB00UL))
#define bFM_GPIO_PDSR6_P1                         *((volatile  uint8_t *)(0x42DEEB04UL))
#define bFM4_GPIO_PDSR6_P1                        *((volatile  uint8_t *)(0x42DEEB04UL))
#define bFM_GPIO_PDSR6_P2                         *((volatile  uint8_t *)(0x42DEEB08UL))
#define bFM4_GPIO_PDSR6_P2                        *((volatile  uint8_t *)(0x42DEEB08UL))
#define bFM_GPIO_PDSR6_P3                         *((volatile  uint8_t *)(0x42DEEB0CUL))
#define bFM4_GPIO_PDSR6_P3                        *((volatile  uint8_t *)(0x42DEEB0CUL))
#define bFM_GPIO_PDSR6_P4                         *((volatile  uint8_t *)(0x42DEEB10UL))
#define bFM4_GPIO_PDSR6_P4                        *((volatile  uint8_t *)(0x42DEEB10UL))
#define bFM_GPIO_PDSR6_P5                         *((volatile  uint8_t *)(0x42DEEB14UL))
#define bFM4_GPIO_PDSR6_P5                        *((volatile  uint8_t *)(0x42DEEB14UL))
#define bFM_GPIO_PDSR6_PE                         *((volatile  uint8_t *)(0x42DEEB38UL))
#define bFM4_GPIO_PDSR6_PE                        *((volatile  uint8_t *)(0x42DEEB38UL))

#define bFM_GPIO_PDSR7_P0                         *((volatile  uint8_t *)(0x42DEEB80UL))
#define bFM4_GPIO_PDSR7_P0                        *((volatile  uint8_t *)(0x42DEEB80UL))
#define bFM_GPIO_PDSR7_P1                         *((volatile  uint8_t *)(0x42DEEB84UL))
#define bFM4_GPIO_PDSR7_P1                        *((volatile  uint8_t *)(0x42DEEB84UL))
#define bFM_GPIO_PDSR7_P2                         *((volatile  uint8_t *)(0x42DEEB88UL))
#define bFM4_GPIO_PDSR7_P2                        *((volatile  uint8_t *)(0x42DEEB88UL))
#define bFM_GPIO_PDSR7_P3                         *((volatile  uint8_t *)(0x42DEEB8CUL))
#define bFM4_GPIO_PDSR7_P3                        *((volatile  uint8_t *)(0x42DEEB8CUL))
#define bFM_GPIO_PDSR7_P4                         *((volatile  uint8_t *)(0x42DEEB90UL))
#define bFM4_GPIO_PDSR7_P4                        *((volatile  uint8_t *)(0x42DEEB90UL))
#define bFM_GPIO_PDSR7_P5                         *((volatile  uint8_t *)(0x42DEEB94UL))
#define bFM4_GPIO_PDSR7_P5                        *((volatile  uint8_t *)(0x42DEEB94UL))
#define bFM_GPIO_PDSR7_P6                         *((volatile  uint8_t *)(0x42DEEB98UL))
#define bFM4_GPIO_PDSR7_P6                        *((volatile  uint8_t *)(0x42DEEB98UL))
#define bFM_GPIO_PDSR7_P7                         *((volatile  uint8_t *)(0x42DEEB9CUL))
#define bFM4_GPIO_PDSR7_P7                        *((volatile  uint8_t *)(0x42DEEB9CUL))
#define bFM_GPIO_PDSR7_P8                         *((volatile  uint8_t *)(0x42DEEBA0UL))
#define bFM4_GPIO_PDSR7_P8                        *((volatile  uint8_t *)(0x42DEEBA0UL))
#define bFM_GPIO_PDSR7_P9                         *((volatile  uint8_t *)(0x42DEEBA4UL))
#define bFM4_GPIO_PDSR7_P9                        *((volatile  uint8_t *)(0x42DEEBA4UL))
#define bFM_GPIO_PDSR7_PA                         *((volatile  uint8_t *)(0x42DEEBA8UL))
#define bFM4_GPIO_PDSR7_PA                        *((volatile  uint8_t *)(0x42DEEBA8UL))
#define bFM_GPIO_PDSR7_PB                         *((volatile  uint8_t *)(0x42DEEBACUL))
#define bFM4_GPIO_PDSR7_PB                        *((volatile  uint8_t *)(0x42DEEBACUL))
#define bFM_GPIO_PDSR7_PC                         *((volatile  uint8_t *)(0x42DEEBB0UL))
#define bFM4_GPIO_PDSR7_PC                        *((volatile  uint8_t *)(0x42DEEBB0UL))
#define bFM_GPIO_PDSR7_PD                         *((volatile  uint8_t *)(0x42DEEBB4UL))
#define bFM4_GPIO_PDSR7_PD                        *((volatile  uint8_t *)(0x42DEEBB4UL))
#define bFM_GPIO_PDSR7_PE                         *((volatile  uint8_t *)(0x42DEEBB8UL))
#define bFM4_GPIO_PDSR7_PE                        *((volatile  uint8_t *)(0x42DEEBB8UL))

#define bFM_GPIO_PDSR8_P0                         *((volatile  uint8_t *)(0x42DEEC00UL))
#define bFM4_GPIO_PDSR8_P0                        *((volatile  uint8_t *)(0x42DEEC00UL))
#define bFM_GPIO_PDSR8_P1                         *((volatile  uint8_t *)(0x42DEEC04UL))
#define bFM4_GPIO_PDSR8_P1                        *((volatile  uint8_t *)(0x42DEEC04UL))
#define bFM_GPIO_PDSR8_P2                         *((volatile  uint8_t *)(0x42DEEC08UL))
#define bFM4_GPIO_PDSR8_P2                        *((volatile  uint8_t *)(0x42DEEC08UL))
#define bFM_GPIO_PDSR8_P3                         *((volatile  uint8_t *)(0x42DEEC0CUL))
#define bFM4_GPIO_PDSR8_P3                        *((volatile  uint8_t *)(0x42DEEC0CUL))

#define bFM_GPIO_PDSR9_P0                         *((volatile  uint8_t *)(0x42DEEC80UL))
#define bFM4_GPIO_PDSR9_P0                        *((volatile  uint8_t *)(0x42DEEC80UL))
#define bFM_GPIO_PDSR9_P1                         *((volatile  uint8_t *)(0x42DEEC84UL))
#define bFM4_GPIO_PDSR9_P1                        *((volatile  uint8_t *)(0x42DEEC84UL))
#define bFM_GPIO_PDSR9_P2                         *((volatile  uint8_t *)(0x42DEEC88UL))
#define bFM4_GPIO_PDSR9_P2                        *((volatile  uint8_t *)(0x42DEEC88UL))
#define bFM_GPIO_PDSR9_P3                         *((volatile  uint8_t *)(0x42DEEC8CUL))
#define bFM4_GPIO_PDSR9_P3                        *((volatile  uint8_t *)(0x42DEEC8CUL))
#define bFM_GPIO_PDSR9_P4                         *((volatile  uint8_t *)(0x42DEEC90UL))
#define bFM4_GPIO_PDSR9_P4                        *((volatile  uint8_t *)(0x42DEEC90UL))
#define bFM_GPIO_PDSR9_P5                         *((volatile  uint8_t *)(0x42DEEC94UL))
#define bFM4_GPIO_PDSR9_P5                        *((volatile  uint8_t *)(0x42DEEC94UL))

#define bFM_GPIO_PDSRA_P0                         *((volatile  uint8_t *)(0x42DEED00UL))
#define bFM4_GPIO_PDSRA_P0                        *((volatile  uint8_t *)(0x42DEED00UL))
#define bFM_GPIO_PDSRA_P1                         *((volatile  uint8_t *)(0x42DEED04UL))
#define bFM4_GPIO_PDSRA_P1                        *((volatile  uint8_t *)(0x42DEED04UL))
#define bFM_GPIO_PDSRA_P2                         *((volatile  uint8_t *)(0x42DEED08UL))
#define bFM4_GPIO_PDSRA_P2                        *((volatile  uint8_t *)(0x42DEED08UL))
#define bFM_GPIO_PDSRA_P3                         *((volatile  uint8_t *)(0x42DEED0CUL))
#define bFM4_GPIO_PDSRA_P3                        *((volatile  uint8_t *)(0x42DEED0CUL))
#define bFM_GPIO_PDSRA_P4                         *((volatile  uint8_t *)(0x42DEED10UL))
#define bFM4_GPIO_PDSRA_P4                        *((volatile  uint8_t *)(0x42DEED10UL))
#define bFM_GPIO_PDSRA_P5                         *((volatile  uint8_t *)(0x42DEED14UL))
#define bFM4_GPIO_PDSRA_P5                        *((volatile  uint8_t *)(0x42DEED14UL))
#define bFM_GPIO_PDSRA_P6                         *((volatile  uint8_t *)(0x42DEED18UL))
#define bFM4_GPIO_PDSRA_P6                        *((volatile  uint8_t *)(0x42DEED18UL))
#define bFM_GPIO_PDSRA_P7                         *((volatile  uint8_t *)(0x42DEED1CUL))
#define bFM4_GPIO_PDSRA_P7                        *((volatile  uint8_t *)(0x42DEED1CUL))
#define bFM_GPIO_PDSRA_P8                         *((volatile  uint8_t *)(0x42DEED20UL))
#define bFM4_GPIO_PDSRA_P8                        *((volatile  uint8_t *)(0x42DEED20UL))
#define bFM_GPIO_PDSRA_P9                         *((volatile  uint8_t *)(0x42DEED24UL))
#define bFM4_GPIO_PDSRA_P9                        *((volatile  uint8_t *)(0x42DEED24UL))
#define bFM_GPIO_PDSRA_PA                         *((volatile  uint8_t *)(0x42DEED28UL))
#define bFM4_GPIO_PDSRA_PA                        *((volatile  uint8_t *)(0x42DEED28UL))
#define bFM_GPIO_PDSRA_PB                         *((volatile  uint8_t *)(0x42DEED2CUL))
#define bFM4_GPIO_PDSRA_PB                        *((volatile  uint8_t *)(0x42DEED2CUL))
#define bFM_GPIO_PDSRA_PC                         *((volatile  uint8_t *)(0x42DEED30UL))
#define bFM4_GPIO_PDSRA_PC                        *((volatile  uint8_t *)(0x42DEED30UL))
#define bFM_GPIO_PDSRA_PD                         *((volatile  uint8_t *)(0x42DEED34UL))
#define bFM4_GPIO_PDSRA_PD                        *((volatile  uint8_t *)(0x42DEED34UL))
#define bFM_GPIO_PDSRA_PE                         *((volatile  uint8_t *)(0x42DEED38UL))
#define bFM4_GPIO_PDSRA_PE                        *((volatile  uint8_t *)(0x42DEED38UL))
#define bFM_GPIO_PDSRA_PF                         *((volatile  uint8_t *)(0x42DEED3CUL))
#define bFM4_GPIO_PDSRA_PF                        *((volatile  uint8_t *)(0x42DEED3CUL))

#define bFM_GPIO_PDSRB_P0                         *((volatile  uint8_t *)(0x42DEED80UL))
#define bFM4_GPIO_PDSRB_P0                        *((volatile  uint8_t *)(0x42DEED80UL))
#define bFM_GPIO_PDSRB_P1                         *((volatile  uint8_t *)(0x42DEED84UL))
#define bFM4_GPIO_PDSRB_P1                        *((volatile  uint8_t *)(0x42DEED84UL))
#define bFM_GPIO_PDSRB_P2                         *((volatile  uint8_t *)(0x42DEED88UL))
#define bFM4_GPIO_PDSRB_P2                        *((volatile  uint8_t *)(0x42DEED88UL))
#define bFM_GPIO_PDSRB_P3                         *((volatile  uint8_t *)(0x42DEED8CUL))
#define bFM4_GPIO_PDSRB_P3                        *((volatile  uint8_t *)(0x42DEED8CUL))
#define bFM_GPIO_PDSRB_P4                         *((volatile  uint8_t *)(0x42DEED90UL))
#define bFM4_GPIO_PDSRB_P4                        *((volatile  uint8_t *)(0x42DEED90UL))
#define bFM_GPIO_PDSRB_P5                         *((volatile  uint8_t *)(0x42DEED94UL))
#define bFM4_GPIO_PDSRB_P5                        *((volatile  uint8_t *)(0x42DEED94UL))
#define bFM_GPIO_PDSRB_P6                         *((volatile  uint8_t *)(0x42DEED98UL))
#define bFM4_GPIO_PDSRB_P6                        *((volatile  uint8_t *)(0x42DEED98UL))
#define bFM_GPIO_PDSRB_P7                         *((volatile  uint8_t *)(0x42DEED9CUL))
#define bFM4_GPIO_PDSRB_P7                        *((volatile  uint8_t *)(0x42DEED9CUL))

#define bFM_GPIO_PDSRC_P0                         *((volatile  uint8_t *)(0x42DEEE00UL))
#define bFM4_GPIO_PDSRC_P0                        *((volatile  uint8_t *)(0x42DEEE00UL))
#define bFM_GPIO_PDSRC_P1                         *((volatile  uint8_t *)(0x42DEEE04UL))
#define bFM4_GPIO_PDSRC_P1                        *((volatile  uint8_t *)(0x42DEEE04UL))
#define bFM_GPIO_PDSRC_P2                         *((volatile  uint8_t *)(0x42DEEE08UL))
#define bFM4_GPIO_PDSRC_P2                        *((volatile  uint8_t *)(0x42DEEE08UL))
#define bFM_GPIO_PDSRC_P3                         *((volatile  uint8_t *)(0x42DEEE0CUL))
#define bFM4_GPIO_PDSRC_P3                        *((volatile  uint8_t *)(0x42DEEE0CUL))
#define bFM_GPIO_PDSRC_P4                         *((volatile  uint8_t *)(0x42DEEE10UL))
#define bFM4_GPIO_PDSRC_P4                        *((volatile  uint8_t *)(0x42DEEE10UL))
#define bFM_GPIO_PDSRC_P5                         *((volatile  uint8_t *)(0x42DEEE14UL))
#define bFM4_GPIO_PDSRC_P5                        *((volatile  uint8_t *)(0x42DEEE14UL))
#define bFM_GPIO_PDSRC_P6                         *((volatile  uint8_t *)(0x42DEEE18UL))
#define bFM4_GPIO_PDSRC_P6                        *((volatile  uint8_t *)(0x42DEEE18UL))
#define bFM_GPIO_PDSRC_P7                         *((volatile  uint8_t *)(0x42DEEE1CUL))
#define bFM4_GPIO_PDSRC_P7                        *((volatile  uint8_t *)(0x42DEEE1CUL))
#define bFM_GPIO_PDSRC_P8                         *((volatile  uint8_t *)(0x42DEEE20UL))
#define bFM4_GPIO_PDSRC_P8                        *((volatile  uint8_t *)(0x42DEEE20UL))
#define bFM_GPIO_PDSRC_P9                         *((volatile  uint8_t *)(0x42DEEE24UL))
#define bFM4_GPIO_PDSRC_P9                        *((volatile  uint8_t *)(0x42DEEE24UL))
#define bFM_GPIO_PDSRC_PA                         *((volatile  uint8_t *)(0x42DEEE28UL))
#define bFM4_GPIO_PDSRC_PA                        *((volatile  uint8_t *)(0x42DEEE28UL))
#define bFM_GPIO_PDSRC_PB                         *((volatile  uint8_t *)(0x42DEEE2CUL))
#define bFM4_GPIO_PDSRC_PB                        *((volatile  uint8_t *)(0x42DEEE2CUL))
#define bFM_GPIO_PDSRC_PC                         *((volatile  uint8_t *)(0x42DEEE30UL))
#define bFM4_GPIO_PDSRC_PC                        *((volatile  uint8_t *)(0x42DEEE30UL))
#define bFM_GPIO_PDSRC_PD                         *((volatile  uint8_t *)(0x42DEEE34UL))
#define bFM4_GPIO_PDSRC_PD                        *((volatile  uint8_t *)(0x42DEEE34UL))
#define bFM_GPIO_PDSRC_PE                         *((volatile  uint8_t *)(0x42DEEE38UL))
#define bFM4_GPIO_PDSRC_PE                        *((volatile  uint8_t *)(0x42DEEE38UL))
#define bFM_GPIO_PDSRC_PF                         *((volatile  uint8_t *)(0x42DEEE3CUL))
#define bFM4_GPIO_PDSRC_PF                        *((volatile  uint8_t *)(0x42DEEE3CUL))

#define bFM_GPIO_PDSRD_P0                         *((volatile  uint8_t *)(0x42DEEE80UL))
#define bFM4_GPIO_PDSRD_P0                        *((volatile  uint8_t *)(0x42DEEE80UL))
#define bFM_GPIO_PDSRD_P1                         *((volatile  uint8_t *)(0x42DEEE84UL))
#define bFM4_GPIO_PDSRD_P1                        *((volatile  uint8_t *)(0x42DEEE84UL))
#define bFM_GPIO_PDSRD_P2                         *((volatile  uint8_t *)(0x42DEEE88UL))
#define bFM4_GPIO_PDSRD_P2                        *((volatile  uint8_t *)(0x42DEEE88UL))

#define bFM_GPIO_PDSRE_P0                         *((volatile  uint8_t *)(0x42DEEF00UL))
#define bFM4_GPIO_PDSRE_P0                        *((volatile  uint8_t *)(0x42DEEF00UL))
#define bFM_GPIO_PDSRE_P2                         *((volatile  uint8_t *)(0x42DEEF08UL))
#define bFM4_GPIO_PDSRE_P2                        *((volatile  uint8_t *)(0x42DEEF08UL))
#define bFM_GPIO_PDSRE_P3                         *((volatile  uint8_t *)(0x42DEEF0CUL))
#define bFM4_GPIO_PDSRE_P3                        *((volatile  uint8_t *)(0x42DEEF0CUL))

#define bFM_GPIO_PDSRF_P0                         *((volatile  uint8_t *)(0x42DEEF80UL))
#define bFM4_GPIO_PDSRF_P0                        *((volatile  uint8_t *)(0x42DEEF80UL))
#define bFM_GPIO_PDSRF_P1                         *((volatile  uint8_t *)(0x42DEEF84UL))
#define bFM4_GPIO_PDSRF_P1                        *((volatile  uint8_t *)(0x42DEEF84UL))
#define bFM_GPIO_PDSRF_P2                         *((volatile  uint8_t *)(0x42DEEF88UL))
#define bFM4_GPIO_PDSRF_P2                        *((volatile  uint8_t *)(0x42DEEF88UL))
#define bFM_GPIO_PDSRF_P3                         *((volatile  uint8_t *)(0x42DEEF8CUL))
#define bFM4_GPIO_PDSRF_P3                        *((volatile  uint8_t *)(0x42DEEF8CUL))
#define bFM_GPIO_PDSRF_P4                         *((volatile  uint8_t *)(0x42DEEF90UL))
#define bFM4_GPIO_PDSRF_P4                        *((volatile  uint8_t *)(0x42DEEF90UL))
#define bFM_GPIO_PDSRF_P5                         *((volatile  uint8_t *)(0x42DEEF94UL))
#define bFM4_GPIO_PDSRF_P5                        *((volatile  uint8_t *)(0x42DEEF94UL))
#define bFM_GPIO_PDSRF_P6                         *((volatile  uint8_t *)(0x42DEEF98UL))
#define bFM4_GPIO_PDSRF_P6                        *((volatile  uint8_t *)(0x42DEEF98UL))
#define bFM_GPIO_PDSRF_P7                         *((volatile  uint8_t *)(0x42DEEF9CUL))
#define bFM4_GPIO_PDSRF_P7                        *((volatile  uint8_t *)(0x42DEEF9CUL))

#define bFM_GPIO_PFR0_P0                          *((volatile  uint8_t *)(0x42DE0000UL))
#define bFM4_GPIO_PFR0_P0                         *((volatile  uint8_t *)(0x42DE0000UL))
#define bFM_GPIO_PFR0_P1                          *((volatile  uint8_t *)(0x42DE0004UL))
#define bFM4_GPIO_PFR0_P1                         *((volatile  uint8_t *)(0x42DE0004UL))
#define bFM_GPIO_PFR0_P2                          *((volatile  uint8_t *)(0x42DE0008UL))
#define bFM4_GPIO_PFR0_P2                         *((volatile  uint8_t *)(0x42DE0008UL))
#define bFM_GPIO_PFR0_P3                          *((volatile  uint8_t *)(0x42DE000CUL))
#define bFM4_GPIO_PFR0_P3                         *((volatile  uint8_t *)(0x42DE000CUL))
#define bFM_GPIO_PFR0_P4                          *((volatile  uint8_t *)(0x42DE0010UL))
#define bFM4_GPIO_PFR0_P4                         *((volatile  uint8_t *)(0x42DE0010UL))
#define bFM_GPIO_PFR0_P8                          *((volatile  uint8_t *)(0x42DE0020UL))
#define bFM4_GPIO_PFR0_P8                         *((volatile  uint8_t *)(0x42DE0020UL))
#define bFM_GPIO_PFR0_P9                          *((volatile  uint8_t *)(0x42DE0024UL))
#define bFM4_GPIO_PFR0_P9                         *((volatile  uint8_t *)(0x42DE0024UL))
#define bFM_GPIO_PFR0_PA                          *((volatile  uint8_t *)(0x42DE0028UL))
#define bFM4_GPIO_PFR0_PA                         *((volatile  uint8_t *)(0x42DE0028UL))

#define bFM_GPIO_PFR1_P0                          *((volatile  uint8_t *)(0x42DE0080UL))
#define bFM4_GPIO_PFR1_P0                         *((volatile  uint8_t *)(0x42DE0080UL))
#define bFM_GPIO_PFR1_P1                          *((volatile  uint8_t *)(0x42DE0084UL))
#define bFM4_GPIO_PFR1_P1                         *((volatile  uint8_t *)(0x42DE0084UL))
#define bFM_GPIO_PFR1_P2                          *((volatile  uint8_t *)(0x42DE0088UL))
#define bFM4_GPIO_PFR1_P2                         *((volatile  uint8_t *)(0x42DE0088UL))
#define bFM_GPIO_PFR1_P3                          *((volatile  uint8_t *)(0x42DE008CUL))
#define bFM4_GPIO_PFR1_P3                         *((volatile  uint8_t *)(0x42DE008CUL))
#define bFM_GPIO_PFR1_P4                          *((volatile  uint8_t *)(0x42DE0090UL))
#define bFM4_GPIO_PFR1_P4                         *((volatile  uint8_t *)(0x42DE0090UL))
#define bFM_GPIO_PFR1_P5                          *((volatile  uint8_t *)(0x42DE0094UL))
#define bFM4_GPIO_PFR1_P5                         *((volatile  uint8_t *)(0x42DE0094UL))
#define bFM_GPIO_PFR1_P6                          *((volatile  uint8_t *)(0x42DE0098UL))
#define bFM4_GPIO_PFR1_P6                         *((volatile  uint8_t *)(0x42DE0098UL))
#define bFM_GPIO_PFR1_P7                          *((volatile  uint8_t *)(0x42DE009CUL))
#define bFM4_GPIO_PFR1_P7                         *((volatile  uint8_t *)(0x42DE009CUL))
#define bFM_GPIO_PFR1_P8                          *((volatile  uint8_t *)(0x42DE00A0UL))
#define bFM4_GPIO_PFR1_P8                         *((volatile  uint8_t *)(0x42DE00A0UL))
#define bFM_GPIO_PFR1_P9                          *((volatile  uint8_t *)(0x42DE00A4UL))
#define bFM4_GPIO_PFR1_P9                         *((volatile  uint8_t *)(0x42DE00A4UL))
#define bFM_GPIO_PFR1_PA                          *((volatile  uint8_t *)(0x42DE00A8UL))
#define bFM4_GPIO_PFR1_PA                         *((volatile  uint8_t *)(0x42DE00A8UL))
#define bFM_GPIO_PFR1_PB                          *((volatile  uint8_t *)(0x42DE00ACUL))
#define bFM4_GPIO_PFR1_PB                         *((volatile  uint8_t *)(0x42DE00ACUL))
#define bFM_GPIO_PFR1_PC                          *((volatile  uint8_t *)(0x42DE00B0UL))
#define bFM4_GPIO_PFR1_PC                         *((volatile  uint8_t *)(0x42DE00B0UL))
#define bFM_GPIO_PFR1_PD                          *((volatile  uint8_t *)(0x42DE00B4UL))
#define bFM4_GPIO_PFR1_PD                         *((volatile  uint8_t *)(0x42DE00B4UL))
#define bFM_GPIO_PFR1_PE                          *((volatile  uint8_t *)(0x42DE00B8UL))
#define bFM4_GPIO_PFR1_PE                         *((volatile  uint8_t *)(0x42DE00B8UL))
#define bFM_GPIO_PFR1_PF                          *((volatile  uint8_t *)(0x42DE00BCUL))
#define bFM4_GPIO_PFR1_PF                         *((volatile  uint8_t *)(0x42DE00BCUL))

#define bFM_GPIO_PFR2_P0                          *((volatile  uint8_t *)(0x42DE0100UL))
#define bFM4_GPIO_PFR2_P0                         *((volatile  uint8_t *)(0x42DE0100UL))
#define bFM_GPIO_PFR2_P1                          *((volatile  uint8_t *)(0x42DE0104UL))
#define bFM4_GPIO_PFR2_P1                         *((volatile  uint8_t *)(0x42DE0104UL))
#define bFM_GPIO_PFR2_P2                          *((volatile  uint8_t *)(0x42DE0108UL))
#define bFM4_GPIO_PFR2_P2                         *((volatile  uint8_t *)(0x42DE0108UL))
#define bFM_GPIO_PFR2_P3                          *((volatile  uint8_t *)(0x42DE010CUL))
#define bFM4_GPIO_PFR2_P3                         *((volatile  uint8_t *)(0x42DE010CUL))
#define bFM_GPIO_PFR2_P4                          *((volatile  uint8_t *)(0x42DE0110UL))
#define bFM4_GPIO_PFR2_P4                         *((volatile  uint8_t *)(0x42DE0110UL))
#define bFM_GPIO_PFR2_P5                          *((volatile  uint8_t *)(0x42DE0114UL))
#define bFM4_GPIO_PFR2_P5                         *((volatile  uint8_t *)(0x42DE0114UL))
#define bFM_GPIO_PFR2_P6                          *((volatile  uint8_t *)(0x42DE0118UL))
#define bFM4_GPIO_PFR2_P6                         *((volatile  uint8_t *)(0x42DE0118UL))
#define bFM_GPIO_PFR2_P7                          *((volatile  uint8_t *)(0x42DE011CUL))
#define bFM4_GPIO_PFR2_P7                         *((volatile  uint8_t *)(0x42DE011CUL))
#define bFM_GPIO_PFR2_P8                          *((volatile  uint8_t *)(0x42DE0120UL))
#define bFM4_GPIO_PFR2_P8                         *((volatile  uint8_t *)(0x42DE0120UL))
#define bFM_GPIO_PFR2_P9                          *((volatile  uint8_t *)(0x42DE0124UL))
#define bFM4_GPIO_PFR2_P9                         *((volatile  uint8_t *)(0x42DE0124UL))
#define bFM_GPIO_PFR2_PA                          *((volatile  uint8_t *)(0x42DE0128UL))
#define bFM4_GPIO_PFR2_PA                         *((volatile  uint8_t *)(0x42DE0128UL))

#define bFM_GPIO_PFR3_P0                          *((volatile  uint8_t *)(0x42DE0180UL))
#define bFM4_GPIO_PFR3_P0                         *((volatile  uint8_t *)(0x42DE0180UL))
#define bFM_GPIO_PFR3_P1                          *((volatile  uint8_t *)(0x42DE0184UL))
#define bFM4_GPIO_PFR3_P1                         *((volatile  uint8_t *)(0x42DE0184UL))
#define bFM_GPIO_PFR3_P2                          *((volatile  uint8_t *)(0x42DE0188UL))
#define bFM4_GPIO_PFR3_P2                         *((volatile  uint8_t *)(0x42DE0188UL))
#define bFM_GPIO_PFR3_P3                          *((volatile  uint8_t *)(0x42DE018CUL))
#define bFM4_GPIO_PFR3_P3                         *((volatile  uint8_t *)(0x42DE018CUL))
#define bFM_GPIO_PFR3_P4                          *((volatile  uint8_t *)(0x42DE0190UL))
#define bFM4_GPIO_PFR3_P4                         *((volatile  uint8_t *)(0x42DE0190UL))
#define bFM_GPIO_PFR3_P5                          *((volatile  uint8_t *)(0x42DE0194UL))
#define bFM4_GPIO_PFR3_P5                         *((volatile  uint8_t *)(0x42DE0194UL))
#define bFM_GPIO_PFR3_P6                          *((volatile  uint8_t *)(0x42DE0198UL))
#define bFM4_GPIO_PFR3_P6                         *((volatile  uint8_t *)(0x42DE0198UL))
#define bFM_GPIO_PFR3_P7                          *((volatile  uint8_t *)(0x42DE019CUL))
#define bFM4_GPIO_PFR3_P7                         *((volatile  uint8_t *)(0x42DE019CUL))
#define bFM_GPIO_PFR3_P8                          *((volatile  uint8_t *)(0x42DE01A0UL))
#define bFM4_GPIO_PFR3_P8                         *((volatile  uint8_t *)(0x42DE01A0UL))
#define bFM_GPIO_PFR3_P9                          *((volatile  uint8_t *)(0x42DE01A4UL))
#define bFM4_GPIO_PFR3_P9                         *((volatile  uint8_t *)(0x42DE01A4UL))
#define bFM_GPIO_PFR3_PA                          *((volatile  uint8_t *)(0x42DE01A8UL))
#define bFM4_GPIO_PFR3_PA                         *((volatile  uint8_t *)(0x42DE01A8UL))
#define bFM_GPIO_PFR3_PB                          *((volatile  uint8_t *)(0x42DE01ACUL))
#define bFM4_GPIO_PFR3_PB                         *((volatile  uint8_t *)(0x42DE01ACUL))
#define bFM_GPIO_PFR3_PC                          *((volatile  uint8_t *)(0x42DE01B0UL))
#define bFM4_GPIO_PFR3_PC                         *((volatile  uint8_t *)(0x42DE01B0UL))
#define bFM_GPIO_PFR3_PD                          *((volatile  uint8_t *)(0x42DE01B4UL))
#define bFM4_GPIO_PFR3_PD                         *((volatile  uint8_t *)(0x42DE01B4UL))
#define bFM_GPIO_PFR3_PE                          *((volatile  uint8_t *)(0x42DE01B8UL))
#define bFM4_GPIO_PFR3_PE                         *((volatile  uint8_t *)(0x42DE01B8UL))

#define bFM_GPIO_PFR4_P0                          *((volatile  uint8_t *)(0x42DE0200UL))
#define bFM4_GPIO_PFR4_P0                         *((volatile  uint8_t *)(0x42DE0200UL))
#define bFM_GPIO_PFR4_P1                          *((volatile  uint8_t *)(0x42DE0204UL))
#define bFM4_GPIO_PFR4_P1                         *((volatile  uint8_t *)(0x42DE0204UL))
#define bFM_GPIO_PFR4_P2                          *((volatile  uint8_t *)(0x42DE0208UL))
#define bFM4_GPIO_PFR4_P2                         *((volatile  uint8_t *)(0x42DE0208UL))
#define bFM_GPIO_PFR4_P3                          *((volatile  uint8_t *)(0x42DE020CUL))
#define bFM4_GPIO_PFR4_P3                         *((volatile  uint8_t *)(0x42DE020CUL))
#define bFM_GPIO_PFR4_P4                          *((volatile  uint8_t *)(0x42DE0210UL))
#define bFM4_GPIO_PFR4_P4                         *((volatile  uint8_t *)(0x42DE0210UL))
#define bFM_GPIO_PFR4_P5                          *((volatile  uint8_t *)(0x42DE0214UL))
#define bFM4_GPIO_PFR4_P5                         *((volatile  uint8_t *)(0x42DE0214UL))
#define bFM_GPIO_PFR4_P6                          *((volatile  uint8_t *)(0x42DE0218UL))
#define bFM4_GPIO_PFR4_P6                         *((volatile  uint8_t *)(0x42DE0218UL))
#define bFM_GPIO_PFR4_P7                          *((volatile  uint8_t *)(0x42DE021CUL))
#define bFM4_GPIO_PFR4_P7                         *((volatile  uint8_t *)(0x42DE021CUL))
#define bFM_GPIO_PFR4_P8                          *((volatile  uint8_t *)(0x42DE0220UL))
#define bFM4_GPIO_PFR4_P8                         *((volatile  uint8_t *)(0x42DE0220UL))
#define bFM_GPIO_PFR4_P9                          *((volatile  uint8_t *)(0x42DE0224UL))
#define bFM4_GPIO_PFR4_P9                         *((volatile  uint8_t *)(0x42DE0224UL))

#define bFM_GPIO_PFR5_P0                          *((volatile  uint8_t *)(0x42DE0280UL))
#define bFM4_GPIO_PFR5_P0                         *((volatile  uint8_t *)(0x42DE0280UL))
#define bFM_GPIO_PFR5_P1                          *((volatile  uint8_t *)(0x42DE0284UL))
#define bFM4_GPIO_PFR5_P1                         *((volatile  uint8_t *)(0x42DE0284UL))
#define bFM_GPIO_PFR5_P2                          *((volatile  uint8_t *)(0x42DE0288UL))
#define bFM4_GPIO_PFR5_P2                         *((volatile  uint8_t *)(0x42DE0288UL))
#define bFM_GPIO_PFR5_PD                          *((volatile  uint8_t *)(0x42DE02B4UL))
#define bFM4_GPIO_PFR5_PD                         *((volatile  uint8_t *)(0x42DE02B4UL))
#define bFM_GPIO_PFR5_PE                          *((volatile  uint8_t *)(0x42DE02B8UL))
#define bFM4_GPIO_PFR5_PE                         *((volatile  uint8_t *)(0x42DE02B8UL))
#define bFM_GPIO_PFR5_PF                          *((volatile  uint8_t *)(0x42DE02BCUL))
#define bFM4_GPIO_PFR5_PF                         *((volatile  uint8_t *)(0x42DE02BCUL))

#define bFM_GPIO_PFR6_P0                          *((volatile  uint8_t *)(0x42DE0300UL))
#define bFM4_GPIO_PFR6_P0                         *((volatile  uint8_t *)(0x42DE0300UL))
#define bFM_GPIO_PFR6_P1                          *((volatile  uint8_t *)(0x42DE0304UL))
#define bFM4_GPIO_PFR6_P1                         *((volatile  uint8_t *)(0x42DE0304UL))
#define bFM_GPIO_PFR6_P2                          *((volatile  uint8_t *)(0x42DE0308UL))
#define bFM4_GPIO_PFR6_P2                         *((volatile  uint8_t *)(0x42DE0308UL))
#define bFM_GPIO_PFR6_P3                          *((volatile  uint8_t *)(0x42DE030CUL))
#define bFM4_GPIO_PFR6_P3                         *((volatile  uint8_t *)(0x42DE030CUL))
#define bFM_GPIO_PFR6_P4                          *((volatile  uint8_t *)(0x42DE0310UL))
#define bFM4_GPIO_PFR6_P4                         *((volatile  uint8_t *)(0x42DE0310UL))
#define bFM_GPIO_PFR6_P5                          *((volatile  uint8_t *)(0x42DE0314UL))
#define bFM4_GPIO_PFR6_P5                         *((volatile  uint8_t *)(0x42DE0314UL))
#define bFM_GPIO_PFR6_PE                          *((volatile  uint8_t *)(0x42DE0338UL))
#define bFM4_GPIO_PFR6_PE                         *((volatile  uint8_t *)(0x42DE0338UL))

#define bFM_GPIO_PFR7_P0                          *((volatile  uint8_t *)(0x42DE0380UL))
#define bFM4_GPIO_PFR7_P0                         *((volatile  uint8_t *)(0x42DE0380UL))
#define bFM_GPIO_PFR7_P1                          *((volatile  uint8_t *)(0x42DE0384UL))
#define bFM4_GPIO_PFR7_P1                         *((volatile  uint8_t *)(0x42DE0384UL))
#define bFM_GPIO_PFR7_P2                          *((volatile  uint8_t *)(0x42DE0388UL))
#define bFM4_GPIO_PFR7_P2                         *((volatile  uint8_t *)(0x42DE0388UL))
#define bFM_GPIO_PFR7_P3                          *((volatile  uint8_t *)(0x42DE038CUL))
#define bFM4_GPIO_PFR7_P3                         *((volatile  uint8_t *)(0x42DE038CUL))
#define bFM_GPIO_PFR7_P4                          *((volatile  uint8_t *)(0x42DE0390UL))
#define bFM4_GPIO_PFR7_P4                         *((volatile  uint8_t *)(0x42DE0390UL))
#define bFM_GPIO_PFR7_P5                          *((volatile  uint8_t *)(0x42DE0394UL))
#define bFM4_GPIO_PFR7_P5                         *((volatile  uint8_t *)(0x42DE0394UL))
#define bFM_GPIO_PFR7_P6                          *((volatile  uint8_t *)(0x42DE0398UL))
#define bFM4_GPIO_PFR7_P6                         *((volatile  uint8_t *)(0x42DE0398UL))
#define bFM_GPIO_PFR7_P7                          *((volatile  uint8_t *)(0x42DE039CUL))
#define bFM4_GPIO_PFR7_P7                         *((volatile  uint8_t *)(0x42DE039CUL))
#define bFM_GPIO_PFR7_P8                          *((volatile  uint8_t *)(0x42DE03A0UL))
#define bFM4_GPIO_PFR7_P8                         *((volatile  uint8_t *)(0x42DE03A0UL))
#define bFM_GPIO_PFR7_P9                          *((volatile  uint8_t *)(0x42DE03A4UL))
#define bFM4_GPIO_PFR7_P9                         *((volatile  uint8_t *)(0x42DE03A4UL))
#define bFM_GPIO_PFR7_PA                          *((volatile  uint8_t *)(0x42DE03A8UL))
#define bFM4_GPIO_PFR7_PA                         *((volatile  uint8_t *)(0x42DE03A8UL))
#define bFM_GPIO_PFR7_PB                          *((volatile  uint8_t *)(0x42DE03ACUL))
#define bFM4_GPIO_PFR7_PB                         *((volatile  uint8_t *)(0x42DE03ACUL))
#define bFM_GPIO_PFR7_PC                          *((volatile  uint8_t *)(0x42DE03B0UL))
#define bFM4_GPIO_PFR7_PC                         *((volatile  uint8_t *)(0x42DE03B0UL))
#define bFM_GPIO_PFR7_PD                          *((volatile  uint8_t *)(0x42DE03B4UL))
#define bFM4_GPIO_PFR7_PD                         *((volatile  uint8_t *)(0x42DE03B4UL))
#define bFM_GPIO_PFR7_PE                          *((volatile  uint8_t *)(0x42DE03B8UL))
#define bFM4_GPIO_PFR7_PE                         *((volatile  uint8_t *)(0x42DE03B8UL))

#define bFM_GPIO_PFR8_P0                          *((volatile  uint8_t *)(0x42DE0400UL))
#define bFM4_GPIO_PFR8_P0                         *((volatile  uint8_t *)(0x42DE0400UL))
#define bFM_GPIO_PFR8_P1                          *((volatile  uint8_t *)(0x42DE0404UL))
#define bFM4_GPIO_PFR8_P1                         *((volatile  uint8_t *)(0x42DE0404UL))
#define bFM_GPIO_PFR8_P2                          *((volatile  uint8_t *)(0x42DE0408UL))
#define bFM4_GPIO_PFR8_P2                         *((volatile  uint8_t *)(0x42DE0408UL))
#define bFM_GPIO_PFR8_P3                          *((volatile  uint8_t *)(0x42DE040CUL))
#define bFM4_GPIO_PFR8_P3                         *((volatile  uint8_t *)(0x42DE040CUL))

#define bFM_GPIO_PFR9_P0                          *((volatile  uint8_t *)(0x42DE0480UL))
#define bFM4_GPIO_PFR9_P0                         *((volatile  uint8_t *)(0x42DE0480UL))
#define bFM_GPIO_PFR9_P1                          *((volatile  uint8_t *)(0x42DE0484UL))
#define bFM4_GPIO_PFR9_P1                         *((volatile  uint8_t *)(0x42DE0484UL))
#define bFM_GPIO_PFR9_P2                          *((volatile  uint8_t *)(0x42DE0488UL))
#define bFM4_GPIO_PFR9_P2                         *((volatile  uint8_t *)(0x42DE0488UL))
#define bFM_GPIO_PFR9_P3                          *((volatile  uint8_t *)(0x42DE048CUL))
#define bFM4_GPIO_PFR9_P3                         *((volatile  uint8_t *)(0x42DE048CUL))
#define bFM_GPIO_PFR9_P4                          *((volatile  uint8_t *)(0x42DE0490UL))
#define bFM4_GPIO_PFR9_P4                         *((volatile  uint8_t *)(0x42DE0490UL))
#define bFM_GPIO_PFR9_P5                          *((volatile  uint8_t *)(0x42DE0494UL))
#define bFM4_GPIO_PFR9_P5                         *((volatile  uint8_t *)(0x42DE0494UL))

#define bFM_GPIO_PFRA_P0                          *((volatile  uint8_t *)(0x42DE0500UL))
#define bFM4_GPIO_PFRA_P0                         *((volatile  uint8_t *)(0x42DE0500UL))
#define bFM_GPIO_PFRA_P1                          *((volatile  uint8_t *)(0x42DE0504UL))
#define bFM4_GPIO_PFRA_P1                         *((volatile  uint8_t *)(0x42DE0504UL))
#define bFM_GPIO_PFRA_P2                          *((volatile  uint8_t *)(0x42DE0508UL))
#define bFM4_GPIO_PFRA_P2                         *((volatile  uint8_t *)(0x42DE0508UL))
#define bFM_GPIO_PFRA_P3                          *((volatile  uint8_t *)(0x42DE050CUL))
#define bFM4_GPIO_PFRA_P3                         *((volatile  uint8_t *)(0x42DE050CUL))
#define bFM_GPIO_PFRA_P4                          *((volatile  uint8_t *)(0x42DE0510UL))
#define bFM4_GPIO_PFRA_P4                         *((volatile  uint8_t *)(0x42DE0510UL))
#define bFM_GPIO_PFRA_P5                          *((volatile  uint8_t *)(0x42DE0514UL))
#define bFM4_GPIO_PFRA_P5                         *((volatile  uint8_t *)(0x42DE0514UL))
#define bFM_GPIO_PFRA_P6                          *((volatile  uint8_t *)(0x42DE0518UL))
#define bFM4_GPIO_PFRA_P6                         *((volatile  uint8_t *)(0x42DE0518UL))
#define bFM_GPIO_PFRA_P7                          *((volatile  uint8_t *)(0x42DE051CUL))
#define bFM4_GPIO_PFRA_P7                         *((volatile  uint8_t *)(0x42DE051CUL))
#define bFM_GPIO_PFRA_P8                          *((volatile  uint8_t *)(0x42DE0520UL))
#define bFM4_GPIO_PFRA_P8                         *((volatile  uint8_t *)(0x42DE0520UL))
#define bFM_GPIO_PFRA_P9                          *((volatile  uint8_t *)(0x42DE0524UL))
#define bFM4_GPIO_PFRA_P9                         *((volatile  uint8_t *)(0x42DE0524UL))
#define bFM_GPIO_PFRA_PA                          *((volatile  uint8_t *)(0x42DE0528UL))
#define bFM4_GPIO_PFRA_PA                         *((volatile  uint8_t *)(0x42DE0528UL))
#define bFM_GPIO_PFRA_PB                          *((volatile  uint8_t *)(0x42DE052CUL))
#define bFM4_GPIO_PFRA_PB                         *((volatile  uint8_t *)(0x42DE052CUL))
#define bFM_GPIO_PFRA_PC                          *((volatile  uint8_t *)(0x42DE0530UL))
#define bFM4_GPIO_PFRA_PC                         *((volatile  uint8_t *)(0x42DE0530UL))
#define bFM_GPIO_PFRA_PD                          *((volatile  uint8_t *)(0x42DE0534UL))
#define bFM4_GPIO_PFRA_PD                         *((volatile  uint8_t *)(0x42DE0534UL))
#define bFM_GPIO_PFRA_PE                          *((volatile  uint8_t *)(0x42DE0538UL))
#define bFM4_GPIO_PFRA_PE                         *((volatile  uint8_t *)(0x42DE0538UL))
#define bFM_GPIO_PFRA_PF                          *((volatile  uint8_t *)(0x42DE053CUL))
#define bFM4_GPIO_PFRA_PF                         *((volatile  uint8_t *)(0x42DE053CUL))

#define bFM_GPIO_PFRB_P0                          *((volatile  uint8_t *)(0x42DE0580UL))
#define bFM4_GPIO_PFRB_P0                         *((volatile  uint8_t *)(0x42DE0580UL))
#define bFM_GPIO_PFRB_P1                          *((volatile  uint8_t *)(0x42DE0584UL))
#define bFM4_GPIO_PFRB_P1                         *((volatile  uint8_t *)(0x42DE0584UL))
#define bFM_GPIO_PFRB_P2                          *((volatile  uint8_t *)(0x42DE0588UL))
#define bFM4_GPIO_PFRB_P2                         *((volatile  uint8_t *)(0x42DE0588UL))
#define bFM_GPIO_PFRB_P3                          *((volatile  uint8_t *)(0x42DE058CUL))
#define bFM4_GPIO_PFRB_P3                         *((volatile  uint8_t *)(0x42DE058CUL))
#define bFM_GPIO_PFRB_P4                          *((volatile  uint8_t *)(0x42DE0590UL))
#define bFM4_GPIO_PFRB_P4                         *((volatile  uint8_t *)(0x42DE0590UL))
#define bFM_GPIO_PFRB_P5                          *((volatile  uint8_t *)(0x42DE0594UL))
#define bFM4_GPIO_PFRB_P5                         *((volatile  uint8_t *)(0x42DE0594UL))
#define bFM_GPIO_PFRB_P6                          *((volatile  uint8_t *)(0x42DE0598UL))
#define bFM4_GPIO_PFRB_P6                         *((volatile  uint8_t *)(0x42DE0598UL))
#define bFM_GPIO_PFRB_P7                          *((volatile  uint8_t *)(0x42DE059CUL))
#define bFM4_GPIO_PFRB_P7                         *((volatile  uint8_t *)(0x42DE059CUL))

#define bFM_GPIO_PFRC_P0                          *((volatile  uint8_t *)(0x42DE0600UL))
#define bFM4_GPIO_PFRC_P0                         *((volatile  uint8_t *)(0x42DE0600UL))
#define bFM_GPIO_PFRC_P1                          *((volatile  uint8_t *)(0x42DE0604UL))
#define bFM4_GPIO_PFRC_P1                         *((volatile  uint8_t *)(0x42DE0604UL))
#define bFM_GPIO_PFRC_P2                          *((volatile  uint8_t *)(0x42DE0608UL))
#define bFM4_GPIO_PFRC_P2                         *((volatile  uint8_t *)(0x42DE0608UL))
#define bFM_GPIO_PFRC_P3                          *((volatile  uint8_t *)(0x42DE060CUL))
#define bFM4_GPIO_PFRC_P3                         *((volatile  uint8_t *)(0x42DE060CUL))
#define bFM_GPIO_PFRC_P4                          *((volatile  uint8_t *)(0x42DE0610UL))
#define bFM4_GPIO_PFRC_P4                         *((volatile  uint8_t *)(0x42DE0610UL))
#define bFM_GPIO_PFRC_P5                          *((volatile  uint8_t *)(0x42DE0614UL))
#define bFM4_GPIO_PFRC_P5                         *((volatile  uint8_t *)(0x42DE0614UL))
#define bFM_GPIO_PFRC_P6                          *((volatile  uint8_t *)(0x42DE0618UL))
#define bFM4_GPIO_PFRC_P6                         *((volatile  uint8_t *)(0x42DE0618UL))
#define bFM_GPIO_PFRC_P7                          *((volatile  uint8_t *)(0x42DE061CUL))
#define bFM4_GPIO_PFRC_P7                         *((volatile  uint8_t *)(0x42DE061CUL))
#define bFM_GPIO_PFRC_P8                          *((volatile  uint8_t *)(0x42DE0620UL))
#define bFM4_GPIO_PFRC_P8                         *((volatile  uint8_t *)(0x42DE0620UL))
#define bFM_GPIO_PFRC_P9                          *((volatile  uint8_t *)(0x42DE0624UL))
#define bFM4_GPIO_PFRC_P9                         *((volatile  uint8_t *)(0x42DE0624UL))
#define bFM_GPIO_PFRC_PA                          *((volatile  uint8_t *)(0x42DE0628UL))
#define bFM4_GPIO_PFRC_PA                         *((volatile  uint8_t *)(0x42DE0628UL))
#define bFM_GPIO_PFRC_PB                          *((volatile  uint8_t *)(0x42DE062CUL))
#define bFM4_GPIO_PFRC_PB                         *((volatile  uint8_t *)(0x42DE062CUL))
#define bFM_GPIO_PFRC_PC                          *((volatile  uint8_t *)(0x42DE0630UL))
#define bFM4_GPIO_PFRC_PC                         *((volatile  uint8_t *)(0x42DE0630UL))
#define bFM_GPIO_PFRC_PD                          *((volatile  uint8_t *)(0x42DE0634UL))
#define bFM4_GPIO_PFRC_PD                         *((volatile  uint8_t *)(0x42DE0634UL))
#define bFM_GPIO_PFRC_PE                          *((volatile  uint8_t *)(0x42DE0638UL))
#define bFM4_GPIO_PFRC_PE                         *((volatile  uint8_t *)(0x42DE0638UL))
#define bFM_GPIO_PFRC_PF                          *((volatile  uint8_t *)(0x42DE063CUL))
#define bFM4_GPIO_PFRC_PF                         *((volatile  uint8_t *)(0x42DE063CUL))

#define bFM_GPIO_PFRD_P0                          *((volatile  uint8_t *)(0x42DE0680UL))
#define bFM4_GPIO_PFRD_P0                         *((volatile  uint8_t *)(0x42DE0680UL))
#define bFM_GPIO_PFRD_P1                          *((volatile  uint8_t *)(0x42DE0684UL))
#define bFM4_GPIO_PFRD_P1                         *((volatile  uint8_t *)(0x42DE0684UL))
#define bFM_GPIO_PFRD_P2                          *((volatile  uint8_t *)(0x42DE0688UL))
#define bFM4_GPIO_PFRD_P2                         *((volatile  uint8_t *)(0x42DE0688UL))

#define bFM_GPIO_PFRE_P0                          *((volatile  uint8_t *)(0x42DE0700UL))
#define bFM4_GPIO_PFRE_P0                         *((volatile  uint8_t *)(0x42DE0700UL))
#define bFM_GPIO_PFRE_P2                          *((volatile  uint8_t *)(0x42DE0708UL))
#define bFM4_GPIO_PFRE_P2                         *((volatile  uint8_t *)(0x42DE0708UL))
#define bFM_GPIO_PFRE_P3                          *((volatile  uint8_t *)(0x42DE070CUL))
#define bFM4_GPIO_PFRE_P3                         *((volatile  uint8_t *)(0x42DE070CUL))

#define bFM_GPIO_PFRF_P0                          *((volatile  uint8_t *)(0x42DE0780UL))
#define bFM4_GPIO_PFRF_P0                         *((volatile  uint8_t *)(0x42DE0780UL))
#define bFM_GPIO_PFRF_P1                          *((volatile  uint8_t *)(0x42DE0784UL))
#define bFM4_GPIO_PFRF_P1                         *((volatile  uint8_t *)(0x42DE0784UL))
#define bFM_GPIO_PFRF_P2                          *((volatile  uint8_t *)(0x42DE0788UL))
#define bFM4_GPIO_PFRF_P2                         *((volatile  uint8_t *)(0x42DE0788UL))
#define bFM_GPIO_PFRF_P3                          *((volatile  uint8_t *)(0x42DE078CUL))
#define bFM4_GPIO_PFRF_P3                         *((volatile  uint8_t *)(0x42DE078CUL))
#define bFM_GPIO_PFRF_P4                          *((volatile  uint8_t *)(0x42DE0790UL))
#define bFM4_GPIO_PFRF_P4                         *((volatile  uint8_t *)(0x42DE0790UL))
#define bFM_GPIO_PFRF_P5                          *((volatile  uint8_t *)(0x42DE0794UL))
#define bFM4_GPIO_PFRF_P5                         *((volatile  uint8_t *)(0x42DE0794UL))
#define bFM_GPIO_PFRF_P6                          *((volatile  uint8_t *)(0x42DE0798UL))
#define bFM4_GPIO_PFRF_P6                         *((volatile  uint8_t *)(0x42DE0798UL))
#define bFM_GPIO_PFRF_P7                          *((volatile  uint8_t *)(0x42DE079CUL))
#define bFM4_GPIO_PFRF_P7                         *((volatile  uint8_t *)(0x42DE079CUL))

#define bFM_GPIO_PZR0_P0                          *((volatile  uint8_t *)(0x42DEE000UL))
#define bFM4_GPIO_PZR0_P0                         *((volatile  uint8_t *)(0x42DEE000UL))
#define bFM_GPIO_PZR0_P1                          *((volatile  uint8_t *)(0x42DEE004UL))
#define bFM4_GPIO_PZR0_P1                         *((volatile  uint8_t *)(0x42DEE004UL))
#define bFM_GPIO_PZR0_P2                          *((volatile  uint8_t *)(0x42DEE008UL))
#define bFM4_GPIO_PZR0_P2                         *((volatile  uint8_t *)(0x42DEE008UL))
#define bFM_GPIO_PZR0_P3                          *((volatile  uint8_t *)(0x42DEE00CUL))
#define bFM4_GPIO_PZR0_P3                         *((volatile  uint8_t *)(0x42DEE00CUL))
#define bFM_GPIO_PZR0_P4                          *((volatile  uint8_t *)(0x42DEE010UL))
#define bFM4_GPIO_PZR0_P4                         *((volatile  uint8_t *)(0x42DEE010UL))
#define bFM_GPIO_PZR0_P8                          *((volatile  uint8_t *)(0x42DEE020UL))
#define bFM4_GPIO_PZR0_P8                         *((volatile  uint8_t *)(0x42DEE020UL))
#define bFM_GPIO_PZR0_P9                          *((volatile  uint8_t *)(0x42DEE024UL))
#define bFM4_GPIO_PZR0_P9                         *((volatile  uint8_t *)(0x42DEE024UL))
#define bFM_GPIO_PZR0_PA                          *((volatile  uint8_t *)(0x42DEE028UL))
#define bFM4_GPIO_PZR0_PA                         *((volatile  uint8_t *)(0x42DEE028UL))

#define bFM_GPIO_PZR1_P0                          *((volatile  uint8_t *)(0x42DEE080UL))
#define bFM4_GPIO_PZR1_P0                         *((volatile  uint8_t *)(0x42DEE080UL))
#define bFM_GPIO_PZR1_P1                          *((volatile  uint8_t *)(0x42DEE084UL))
#define bFM4_GPIO_PZR1_P1                         *((volatile  uint8_t *)(0x42DEE084UL))
#define bFM_GPIO_PZR1_P2                          *((volatile  uint8_t *)(0x42DEE088UL))
#define bFM4_GPIO_PZR1_P2                         *((volatile  uint8_t *)(0x42DEE088UL))
#define bFM_GPIO_PZR1_P3                          *((volatile  uint8_t *)(0x42DEE08CUL))
#define bFM4_GPIO_PZR1_P3                         *((volatile  uint8_t *)(0x42DEE08CUL))
#define bFM_GPIO_PZR1_P4                          *((volatile  uint8_t *)(0x42DEE090UL))
#define bFM4_GPIO_PZR1_P4                         *((volatile  uint8_t *)(0x42DEE090UL))
#define bFM_GPIO_PZR1_P5                          *((volatile  uint8_t *)(0x42DEE094UL))
#define bFM4_GPIO_PZR1_P5                         *((volatile  uint8_t *)(0x42DEE094UL))
#define bFM_GPIO_PZR1_P6                          *((volatile  uint8_t *)(0x42DEE098UL))
#define bFM4_GPIO_PZR1_P6                         *((volatile  uint8_t *)(0x42DEE098UL))
#define bFM_GPIO_PZR1_P7                          *((volatile  uint8_t *)(0x42DEE09CUL))
#define bFM4_GPIO_PZR1_P7                         *((volatile  uint8_t *)(0x42DEE09CUL))
#define bFM_GPIO_PZR1_P8                          *((volatile  uint8_t *)(0x42DEE0A0UL))
#define bFM4_GPIO_PZR1_P8                         *((volatile  uint8_t *)(0x42DEE0A0UL))
#define bFM_GPIO_PZR1_P9                          *((volatile  uint8_t *)(0x42DEE0A4UL))
#define bFM4_GPIO_PZR1_P9                         *((volatile  uint8_t *)(0x42DEE0A4UL))
#define bFM_GPIO_PZR1_PA                          *((volatile  uint8_t *)(0x42DEE0A8UL))
#define bFM4_GPIO_PZR1_PA                         *((volatile  uint8_t *)(0x42DEE0A8UL))
#define bFM_GPIO_PZR1_PB                          *((volatile  uint8_t *)(0x42DEE0ACUL))
#define bFM4_GPIO_PZR1_PB                         *((volatile  uint8_t *)(0x42DEE0ACUL))
#define bFM_GPIO_PZR1_PC                          *((volatile  uint8_t *)(0x42DEE0B0UL))
#define bFM4_GPIO_PZR1_PC                         *((volatile  uint8_t *)(0x42DEE0B0UL))
#define bFM_GPIO_PZR1_PD                          *((volatile  uint8_t *)(0x42DEE0B4UL))
#define bFM4_GPIO_PZR1_PD                         *((volatile  uint8_t *)(0x42DEE0B4UL))
#define bFM_GPIO_PZR1_PE                          *((volatile  uint8_t *)(0x42DEE0B8UL))
#define bFM4_GPIO_PZR1_PE                         *((volatile  uint8_t *)(0x42DEE0B8UL))
#define bFM_GPIO_PZR1_PF                          *((volatile  uint8_t *)(0x42DEE0BCUL))
#define bFM4_GPIO_PZR1_PF                         *((volatile  uint8_t *)(0x42DEE0BCUL))

#define bFM_GPIO_PZR2_P0                          *((volatile  uint8_t *)(0x42DEE100UL))
#define bFM4_GPIO_PZR2_P0                         *((volatile  uint8_t *)(0x42DEE100UL))
#define bFM_GPIO_PZR2_P1                          *((volatile  uint8_t *)(0x42DEE104UL))
#define bFM4_GPIO_PZR2_P1                         *((volatile  uint8_t *)(0x42DEE104UL))
#define bFM_GPIO_PZR2_P2                          *((volatile  uint8_t *)(0x42DEE108UL))
#define bFM4_GPIO_PZR2_P2                         *((volatile  uint8_t *)(0x42DEE108UL))
#define bFM_GPIO_PZR2_P3                          *((volatile  uint8_t *)(0x42DEE10CUL))
#define bFM4_GPIO_PZR2_P3                         *((volatile  uint8_t *)(0x42DEE10CUL))
#define bFM_GPIO_PZR2_P4                          *((volatile  uint8_t *)(0x42DEE110UL))
#define bFM4_GPIO_PZR2_P4                         *((volatile  uint8_t *)(0x42DEE110UL))
#define bFM_GPIO_PZR2_P5                          *((volatile  uint8_t *)(0x42DEE114UL))
#define bFM4_GPIO_PZR2_P5                         *((volatile  uint8_t *)(0x42DEE114UL))
#define bFM_GPIO_PZR2_P6                          *((volatile  uint8_t *)(0x42DEE118UL))
#define bFM4_GPIO_PZR2_P6                         *((volatile  uint8_t *)(0x42DEE118UL))
#define bFM_GPIO_PZR2_P7                          *((volatile  uint8_t *)(0x42DEE11CUL))
#define bFM4_GPIO_PZR2_P7                         *((volatile  uint8_t *)(0x42DEE11CUL))
#define bFM_GPIO_PZR2_P8                          *((volatile  uint8_t *)(0x42DEE120UL))
#define bFM4_GPIO_PZR2_P8                         *((volatile  uint8_t *)(0x42DEE120UL))
#define bFM_GPIO_PZR2_P9                          *((volatile  uint8_t *)(0x42DEE124UL))
#define bFM4_GPIO_PZR2_P9                         *((volatile  uint8_t *)(0x42DEE124UL))
#define bFM_GPIO_PZR2_PA                          *((volatile  uint8_t *)(0x42DEE128UL))
#define bFM4_GPIO_PZR2_PA                         *((volatile  uint8_t *)(0x42DEE128UL))

#define bFM_GPIO_PZR3_P0                          *((volatile  uint8_t *)(0x42DEE180UL))
#define bFM4_GPIO_PZR3_P0                         *((volatile  uint8_t *)(0x42DEE180UL))
#define bFM_GPIO_PZR3_P1                          *((volatile  uint8_t *)(0x42DEE184UL))
#define bFM4_GPIO_PZR3_P1                         *((volatile  uint8_t *)(0x42DEE184UL))
#define bFM_GPIO_PZR3_P2                          *((volatile  uint8_t *)(0x42DEE188UL))
#define bFM4_GPIO_PZR3_P2                         *((volatile  uint8_t *)(0x42DEE188UL))
#define bFM_GPIO_PZR3_P3                          *((volatile  uint8_t *)(0x42DEE18CUL))
#define bFM4_GPIO_PZR3_P3                         *((volatile  uint8_t *)(0x42DEE18CUL))
#define bFM_GPIO_PZR3_P4                          *((volatile  uint8_t *)(0x42DEE190UL))
#define bFM4_GPIO_PZR3_P4                         *((volatile  uint8_t *)(0x42DEE190UL))
#define bFM_GPIO_PZR3_P5                          *((volatile  uint8_t *)(0x42DEE194UL))
#define bFM4_GPIO_PZR3_P5                         *((volatile  uint8_t *)(0x42DEE194UL))
#define bFM_GPIO_PZR3_P6                          *((volatile  uint8_t *)(0x42DEE198UL))
#define bFM4_GPIO_PZR3_P6                         *((volatile  uint8_t *)(0x42DEE198UL))
#define bFM_GPIO_PZR3_P7                          *((volatile  uint8_t *)(0x42DEE19CUL))
#define bFM4_GPIO_PZR3_P7                         *((volatile  uint8_t *)(0x42DEE19CUL))
#define bFM_GPIO_PZR3_P8                          *((volatile  uint8_t *)(0x42DEE1A0UL))
#define bFM4_GPIO_PZR3_P8                         *((volatile  uint8_t *)(0x42DEE1A0UL))
#define bFM_GPIO_PZR3_P9                          *((volatile  uint8_t *)(0x42DEE1A4UL))
#define bFM4_GPIO_PZR3_P9                         *((volatile  uint8_t *)(0x42DEE1A4UL))
#define bFM_GPIO_PZR3_PA                          *((volatile  uint8_t *)(0x42DEE1A8UL))
#define bFM4_GPIO_PZR3_PA                         *((volatile  uint8_t *)(0x42DEE1A8UL))
#define bFM_GPIO_PZR3_PB                          *((volatile  uint8_t *)(0x42DEE1ACUL))
#define bFM4_GPIO_PZR3_PB                         *((volatile  uint8_t *)(0x42DEE1ACUL))
#define bFM_GPIO_PZR3_PC                          *((volatile  uint8_t *)(0x42DEE1B0UL))
#define bFM4_GPIO_PZR3_PC                         *((volatile  uint8_t *)(0x42DEE1B0UL))
#define bFM_GPIO_PZR3_PD                          *((volatile  uint8_t *)(0x42DEE1B4UL))
#define bFM4_GPIO_PZR3_PD                         *((volatile  uint8_t *)(0x42DEE1B4UL))
#define bFM_GPIO_PZR3_PE                          *((volatile  uint8_t *)(0x42DEE1B8UL))
#define bFM4_GPIO_PZR3_PE                         *((volatile  uint8_t *)(0x42DEE1B8UL))

#define bFM_GPIO_PZR4_P0                          *((volatile  uint8_t *)(0x42DEE200UL))
#define bFM4_GPIO_PZR4_P0                         *((volatile  uint8_t *)(0x42DEE200UL))
#define bFM_GPIO_PZR4_P1                          *((volatile  uint8_t *)(0x42DEE204UL))
#define bFM4_GPIO_PZR4_P1                         *((volatile  uint8_t *)(0x42DEE204UL))
#define bFM_GPIO_PZR4_P2                          *((volatile  uint8_t *)(0x42DEE208UL))
#define bFM4_GPIO_PZR4_P2                         *((volatile  uint8_t *)(0x42DEE208UL))
#define bFM_GPIO_PZR4_P3                          *((volatile  uint8_t *)(0x42DEE20CUL))
#define bFM4_GPIO_PZR4_P3                         *((volatile  uint8_t *)(0x42DEE20CUL))
#define bFM_GPIO_PZR4_P4                          *((volatile  uint8_t *)(0x42DEE210UL))
#define bFM4_GPIO_PZR4_P4                         *((volatile  uint8_t *)(0x42DEE210UL))
#define bFM_GPIO_PZR4_P5                          *((volatile  uint8_t *)(0x42DEE214UL))
#define bFM4_GPIO_PZR4_P5                         *((volatile  uint8_t *)(0x42DEE214UL))
#define bFM_GPIO_PZR4_P6                          *((volatile  uint8_t *)(0x42DEE218UL))
#define bFM4_GPIO_PZR4_P6                         *((volatile  uint8_t *)(0x42DEE218UL))
#define bFM_GPIO_PZR4_P7                          *((volatile  uint8_t *)(0x42DEE21CUL))
#define bFM4_GPIO_PZR4_P7                         *((volatile  uint8_t *)(0x42DEE21CUL))
#define bFM_GPIO_PZR4_P8                          *((volatile  uint8_t *)(0x42DEE220UL))
#define bFM4_GPIO_PZR4_P8                         *((volatile  uint8_t *)(0x42DEE220UL))
#define bFM_GPIO_PZR4_P9                          *((volatile  uint8_t *)(0x42DEE224UL))
#define bFM4_GPIO_PZR4_P9                         *((volatile  uint8_t *)(0x42DEE224UL))

#define bFM_GPIO_PZR5_P0                          *((volatile  uint8_t *)(0x42DEE280UL))
#define bFM4_GPIO_PZR5_P0                         *((volatile  uint8_t *)(0x42DEE280UL))
#define bFM_GPIO_PZR5_P1                          *((volatile  uint8_t *)(0x42DEE284UL))
#define bFM4_GPIO_PZR5_P1                         *((volatile  uint8_t *)(0x42DEE284UL))
#define bFM_GPIO_PZR5_P2                          *((volatile  uint8_t *)(0x42DEE288UL))
#define bFM4_GPIO_PZR5_P2                         *((volatile  uint8_t *)(0x42DEE288UL))
#define bFM_GPIO_PZR5_PD                          *((volatile  uint8_t *)(0x42DEE2B4UL))
#define bFM4_GPIO_PZR5_PD                         *((volatile  uint8_t *)(0x42DEE2B4UL))
#define bFM_GPIO_PZR5_PE                          *((volatile  uint8_t *)(0x42DEE2B8UL))
#define bFM4_GPIO_PZR5_PE                         *((volatile  uint8_t *)(0x42DEE2B8UL))
#define bFM_GPIO_PZR5_PF                          *((volatile  uint8_t *)(0x42DEE2BCUL))
#define bFM4_GPIO_PZR5_PF                         *((volatile  uint8_t *)(0x42DEE2BCUL))

#define bFM_GPIO_PZR6_P0                          *((volatile  uint8_t *)(0x42DEE300UL))
#define bFM4_GPIO_PZR6_P0                         *((volatile  uint8_t *)(0x42DEE300UL))
#define bFM_GPIO_PZR6_P1                          *((volatile  uint8_t *)(0x42DEE304UL))
#define bFM4_GPIO_PZR6_P1                         *((volatile  uint8_t *)(0x42DEE304UL))
#define bFM_GPIO_PZR6_P2                          *((volatile  uint8_t *)(0x42DEE308UL))
#define bFM4_GPIO_PZR6_P2                         *((volatile  uint8_t *)(0x42DEE308UL))
#define bFM_GPIO_PZR6_P3                          *((volatile  uint8_t *)(0x42DEE30CUL))
#define bFM4_GPIO_PZR6_P3                         *((volatile  uint8_t *)(0x42DEE30CUL))
#define bFM_GPIO_PZR6_P4                          *((volatile  uint8_t *)(0x42DEE310UL))
#define bFM4_GPIO_PZR6_P4                         *((volatile  uint8_t *)(0x42DEE310UL))
#define bFM_GPIO_PZR6_P5                          *((volatile  uint8_t *)(0x42DEE314UL))
#define bFM4_GPIO_PZR6_P5                         *((volatile  uint8_t *)(0x42DEE314UL))
#define bFM_GPIO_PZR6_PE                          *((volatile  uint8_t *)(0x42DEE338UL))
#define bFM4_GPIO_PZR6_PE                         *((volatile  uint8_t *)(0x42DEE338UL))

#define bFM_GPIO_PZR7_P0                          *((volatile  uint8_t *)(0x42DEE380UL))
#define bFM4_GPIO_PZR7_P0                         *((volatile  uint8_t *)(0x42DEE380UL))
#define bFM_GPIO_PZR7_P1                          *((volatile  uint8_t *)(0x42DEE384UL))
#define bFM4_GPIO_PZR7_P1                         *((volatile  uint8_t *)(0x42DEE384UL))
#define bFM_GPIO_PZR7_P2                          *((volatile  uint8_t *)(0x42DEE388UL))
#define bFM4_GPIO_PZR7_P2                         *((volatile  uint8_t *)(0x42DEE388UL))
#define bFM_GPIO_PZR7_P3                          *((volatile  uint8_t *)(0x42DEE38CUL))
#define bFM4_GPIO_PZR7_P3                         *((volatile  uint8_t *)(0x42DEE38CUL))
#define bFM_GPIO_PZR7_P4                          *((volatile  uint8_t *)(0x42DEE390UL))
#define bFM4_GPIO_PZR7_P4                         *((volatile  uint8_t *)(0x42DEE390UL))
#define bFM_GPIO_PZR7_P5                          *((volatile  uint8_t *)(0x42DEE394UL))
#define bFM4_GPIO_PZR7_P5                         *((volatile  uint8_t *)(0x42DEE394UL))
#define bFM_GPIO_PZR7_P6                          *((volatile  uint8_t *)(0x42DEE398UL))
#define bFM4_GPIO_PZR7_P6                         *((volatile  uint8_t *)(0x42DEE398UL))
#define bFM_GPIO_PZR7_P7                          *((volatile  uint8_t *)(0x42DEE39CUL))
#define bFM4_GPIO_PZR7_P7                         *((volatile  uint8_t *)(0x42DEE39CUL))
#define bFM_GPIO_PZR7_P8                          *((volatile  uint8_t *)(0x42DEE3A0UL))
#define bFM4_GPIO_PZR7_P8                         *((volatile  uint8_t *)(0x42DEE3A0UL))
#define bFM_GPIO_PZR7_P9                          *((volatile  uint8_t *)(0x42DEE3A4UL))
#define bFM4_GPIO_PZR7_P9                         *((volatile  uint8_t *)(0x42DEE3A4UL))
#define bFM_GPIO_PZR7_PA                          *((volatile  uint8_t *)(0x42DEE3A8UL))
#define bFM4_GPIO_PZR7_PA                         *((volatile  uint8_t *)(0x42DEE3A8UL))
#define bFM_GPIO_PZR7_PB                          *((volatile  uint8_t *)(0x42DEE3ACUL))
#define bFM4_GPIO_PZR7_PB                         *((volatile  uint8_t *)(0x42DEE3ACUL))
#define bFM_GPIO_PZR7_PC                          *((volatile  uint8_t *)(0x42DEE3B0UL))
#define bFM4_GPIO_PZR7_PC                         *((volatile  uint8_t *)(0x42DEE3B0UL))
#define bFM_GPIO_PZR7_PD                          *((volatile  uint8_t *)(0x42DEE3B4UL))
#define bFM4_GPIO_PZR7_PD                         *((volatile  uint8_t *)(0x42DEE3B4UL))
#define bFM_GPIO_PZR7_PE                          *((volatile  uint8_t *)(0x42DEE3B8UL))
#define bFM4_GPIO_PZR7_PE                         *((volatile  uint8_t *)(0x42DEE3B8UL))

#define bFM_GPIO_PZR8_P0                          *((volatile  uint8_t *)(0x42DEE400UL))
#define bFM4_GPIO_PZR8_P0                         *((volatile  uint8_t *)(0x42DEE400UL))
#define bFM_GPIO_PZR8_P1                          *((volatile  uint8_t *)(0x42DEE404UL))
#define bFM4_GPIO_PZR8_P1                         *((volatile  uint8_t *)(0x42DEE404UL))
#define bFM_GPIO_PZR8_P2                          *((volatile  uint8_t *)(0x42DEE408UL))
#define bFM4_GPIO_PZR8_P2                         *((volatile  uint8_t *)(0x42DEE408UL))
#define bFM_GPIO_PZR8_P3                          *((volatile  uint8_t *)(0x42DEE40CUL))
#define bFM4_GPIO_PZR8_P3                         *((volatile  uint8_t *)(0x42DEE40CUL))

#define bFM_GPIO_PZR9_P0                          *((volatile  uint8_t *)(0x42DEE480UL))
#define bFM4_GPIO_PZR9_P0                         *((volatile  uint8_t *)(0x42DEE480UL))
#define bFM_GPIO_PZR9_P1                          *((volatile  uint8_t *)(0x42DEE484UL))
#define bFM4_GPIO_PZR9_P1                         *((volatile  uint8_t *)(0x42DEE484UL))
#define bFM_GPIO_PZR9_P2                          *((volatile  uint8_t *)(0x42DEE488UL))
#define bFM4_GPIO_PZR9_P2                         *((volatile  uint8_t *)(0x42DEE488UL))
#define bFM_GPIO_PZR9_P3                          *((volatile  uint8_t *)(0x42DEE48CUL))
#define bFM4_GPIO_PZR9_P3                         *((volatile  uint8_t *)(0x42DEE48CUL))
#define bFM_GPIO_PZR9_P4                          *((volatile  uint8_t *)(0x42DEE490UL))
#define bFM4_GPIO_PZR9_P4                         *((volatile  uint8_t *)(0x42DEE490UL))
#define bFM_GPIO_PZR9_P5                          *((volatile  uint8_t *)(0x42DEE494UL))
#define bFM4_GPIO_PZR9_P5                         *((volatile  uint8_t *)(0x42DEE494UL))

#define bFM_GPIO_PZRA_P0                          *((volatile  uint8_t *)(0x42DEE500UL))
#define bFM4_GPIO_PZRA_P0                         *((volatile  uint8_t *)(0x42DEE500UL))
#define bFM_GPIO_PZRA_P1                          *((volatile  uint8_t *)(0x42DEE504UL))
#define bFM4_GPIO_PZRA_P1                         *((volatile  uint8_t *)(0x42DEE504UL))
#define bFM_GPIO_PZRA_P2                          *((volatile  uint8_t *)(0x42DEE508UL))
#define bFM4_GPIO_PZRA_P2                         *((volatile  uint8_t *)(0x42DEE508UL))
#define bFM_GPIO_PZRA_P3                          *((volatile  uint8_t *)(0x42DEE50CUL))
#define bFM4_GPIO_PZRA_P3                         *((volatile  uint8_t *)(0x42DEE50CUL))
#define bFM_GPIO_PZRA_P4                          *((volatile  uint8_t *)(0x42DEE510UL))
#define bFM4_GPIO_PZRA_P4                         *((volatile  uint8_t *)(0x42DEE510UL))
#define bFM_GPIO_PZRA_P5                          *((volatile  uint8_t *)(0x42DEE514UL))
#define bFM4_GPIO_PZRA_P5                         *((volatile  uint8_t *)(0x42DEE514UL))
#define bFM_GPIO_PZRA_P6                          *((volatile  uint8_t *)(0x42DEE518UL))
#define bFM4_GPIO_PZRA_P6                         *((volatile  uint8_t *)(0x42DEE518UL))
#define bFM_GPIO_PZRA_P7                          *((volatile  uint8_t *)(0x42DEE51CUL))
#define bFM4_GPIO_PZRA_P7                         *((volatile  uint8_t *)(0x42DEE51CUL))
#define bFM_GPIO_PZRA_P8                          *((volatile  uint8_t *)(0x42DEE520UL))
#define bFM4_GPIO_PZRA_P8                         *((volatile  uint8_t *)(0x42DEE520UL))
#define bFM_GPIO_PZRA_P9                          *((volatile  uint8_t *)(0x42DEE524UL))
#define bFM4_GPIO_PZRA_P9                         *((volatile  uint8_t *)(0x42DEE524UL))
#define bFM_GPIO_PZRA_PA                          *((volatile  uint8_t *)(0x42DEE528UL))
#define bFM4_GPIO_PZRA_PA                         *((volatile  uint8_t *)(0x42DEE528UL))
#define bFM_GPIO_PZRA_PB                          *((volatile  uint8_t *)(0x42DEE52CUL))
#define bFM4_GPIO_PZRA_PB                         *((volatile  uint8_t *)(0x42DEE52CUL))
#define bFM_GPIO_PZRA_PC                          *((volatile  uint8_t *)(0x42DEE530UL))
#define bFM4_GPIO_PZRA_PC                         *((volatile  uint8_t *)(0x42DEE530UL))
#define bFM_GPIO_PZRA_PD                          *((volatile  uint8_t *)(0x42DEE534UL))
#define bFM4_GPIO_PZRA_PD                         *((volatile  uint8_t *)(0x42DEE534UL))
#define bFM_GPIO_PZRA_PE                          *((volatile  uint8_t *)(0x42DEE538UL))
#define bFM4_GPIO_PZRA_PE                         *((volatile  uint8_t *)(0x42DEE538UL))
#define bFM_GPIO_PZRA_PF                          *((volatile  uint8_t *)(0x42DEE53CUL))
#define bFM4_GPIO_PZRA_PF                         *((volatile  uint8_t *)(0x42DEE53CUL))

#define bFM_GPIO_PZRB_P0                          *((volatile  uint8_t *)(0x42DEE580UL))
#define bFM4_GPIO_PZRB_P0                         *((volatile  uint8_t *)(0x42DEE580UL))
#define bFM_GPIO_PZRB_P1                          *((volatile  uint8_t *)(0x42DEE584UL))
#define bFM4_GPIO_PZRB_P1                         *((volatile  uint8_t *)(0x42DEE584UL))
#define bFM_GPIO_PZRB_P2                          *((volatile  uint8_t *)(0x42DEE588UL))
#define bFM4_GPIO_PZRB_P2                         *((volatile  uint8_t *)(0x42DEE588UL))
#define bFM_GPIO_PZRB_P3                          *((volatile  uint8_t *)(0x42DEE58CUL))
#define bFM4_GPIO_PZRB_P3                         *((volatile  uint8_t *)(0x42DEE58CUL))
#define bFM_GPIO_PZRB_P4                          *((volatile  uint8_t *)(0x42DEE590UL))
#define bFM4_GPIO_PZRB_P4                         *((volatile  uint8_t *)(0x42DEE590UL))
#define bFM_GPIO_PZRB_P5                          *((volatile  uint8_t *)(0x42DEE594UL))
#define bFM4_GPIO_PZRB_P5                         *((volatile  uint8_t *)(0x42DEE594UL))
#define bFM_GPIO_PZRB_P6                          *((volatile  uint8_t *)(0x42DEE598UL))
#define bFM4_GPIO_PZRB_P6                         *((volatile  uint8_t *)(0x42DEE598UL))
#define bFM_GPIO_PZRB_P7                          *((volatile  uint8_t *)(0x42DEE59CUL))
#define bFM4_GPIO_PZRB_P7                         *((volatile  uint8_t *)(0x42DEE59CUL))

#define bFM_GPIO_PZRC_P0                          *((volatile  uint8_t *)(0x42DEE600UL))
#define bFM4_GPIO_PZRC_P0                         *((volatile  uint8_t *)(0x42DEE600UL))
#define bFM_GPIO_PZRC_P1                          *((volatile  uint8_t *)(0x42DEE604UL))
#define bFM4_GPIO_PZRC_P1                         *((volatile  uint8_t *)(0x42DEE604UL))
#define bFM_GPIO_PZRC_P2                          *((volatile  uint8_t *)(0x42DEE608UL))
#define bFM4_GPIO_PZRC_P2                         *((volatile  uint8_t *)(0x42DEE608UL))
#define bFM_GPIO_PZRC_P3                          *((volatile  uint8_t *)(0x42DEE60CUL))
#define bFM4_GPIO_PZRC_P3                         *((volatile  uint8_t *)(0x42DEE60CUL))
#define bFM_GPIO_PZRC_P4                          *((volatile  uint8_t *)(0x42DEE610UL))
#define bFM4_GPIO_PZRC_P4                         *((volatile  uint8_t *)(0x42DEE610UL))
#define bFM_GPIO_PZRC_P5                          *((volatile  uint8_t *)(0x42DEE614UL))
#define bFM4_GPIO_PZRC_P5                         *((volatile  uint8_t *)(0x42DEE614UL))
#define bFM_GPIO_PZRC_P6                          *((volatile  uint8_t *)(0x42DEE618UL))
#define bFM4_GPIO_PZRC_P6                         *((volatile  uint8_t *)(0x42DEE618UL))
#define bFM_GPIO_PZRC_P7                          *((volatile  uint8_t *)(0x42DEE61CUL))
#define bFM4_GPIO_PZRC_P7                         *((volatile  uint8_t *)(0x42DEE61CUL))
#define bFM_GPIO_PZRC_P8                          *((volatile  uint8_t *)(0x42DEE620UL))
#define bFM4_GPIO_PZRC_P8                         *((volatile  uint8_t *)(0x42DEE620UL))
#define bFM_GPIO_PZRC_P9                          *((volatile  uint8_t *)(0x42DEE624UL))
#define bFM4_GPIO_PZRC_P9                         *((volatile  uint8_t *)(0x42DEE624UL))
#define bFM_GPIO_PZRC_PA                          *((volatile  uint8_t *)(0x42DEE628UL))
#define bFM4_GPIO_PZRC_PA                         *((volatile  uint8_t *)(0x42DEE628UL))
#define bFM_GPIO_PZRC_PB                          *((volatile  uint8_t *)(0x42DEE62CUL))
#define bFM4_GPIO_PZRC_PB                         *((volatile  uint8_t *)(0x42DEE62CUL))
#define bFM_GPIO_PZRC_PC                          *((volatile  uint8_t *)(0x42DEE630UL))
#define bFM4_GPIO_PZRC_PC                         *((volatile  uint8_t *)(0x42DEE630UL))
#define bFM_GPIO_PZRC_PD                          *((volatile  uint8_t *)(0x42DEE634UL))
#define bFM4_GPIO_PZRC_PD                         *((volatile  uint8_t *)(0x42DEE634UL))
#define bFM_GPIO_PZRC_PE                          *((volatile  uint8_t *)(0x42DEE638UL))
#define bFM4_GPIO_PZRC_PE                         *((volatile  uint8_t *)(0x42DEE638UL))
#define bFM_GPIO_PZRC_PF                          *((volatile  uint8_t *)(0x42DEE63CUL))
#define bFM4_GPIO_PZRC_PF                         *((volatile  uint8_t *)(0x42DEE63CUL))

#define bFM_GPIO_PZRD_P0                          *((volatile  uint8_t *)(0x42DEE680UL))
#define bFM4_GPIO_PZRD_P0                         *((volatile  uint8_t *)(0x42DEE680UL))
#define bFM_GPIO_PZRD_P1                          *((volatile  uint8_t *)(0x42DEE684UL))
#define bFM4_GPIO_PZRD_P1                         *((volatile  uint8_t *)(0x42DEE684UL))
#define bFM_GPIO_PZRD_P2                          *((volatile  uint8_t *)(0x42DEE688UL))
#define bFM4_GPIO_PZRD_P2                         *((volatile  uint8_t *)(0x42DEE688UL))

#define bFM_GPIO_PZRE_P0                          *((volatile  uint8_t *)(0x42DEE700UL))
#define bFM4_GPIO_PZRE_P0                         *((volatile  uint8_t *)(0x42DEE700UL))
#define bFM_GPIO_PZRE_P2                          *((volatile  uint8_t *)(0x42DEE708UL))
#define bFM4_GPIO_PZRE_P2                         *((volatile  uint8_t *)(0x42DEE708UL))
#define bFM_GPIO_PZRE_P3                          *((volatile  uint8_t *)(0x42DEE70CUL))
#define bFM4_GPIO_PZRE_P3                         *((volatile  uint8_t *)(0x42DEE70CUL))

#define bFM_GPIO_PZRF_P0                          *((volatile  uint8_t *)(0x42DEE780UL))
#define bFM4_GPIO_PZRF_P0                         *((volatile  uint8_t *)(0x42DEE780UL))
#define bFM_GPIO_PZRF_P1                          *((volatile  uint8_t *)(0x42DEE784UL))
#define bFM4_GPIO_PZRF_P1                         *((volatile  uint8_t *)(0x42DEE784UL))
#define bFM_GPIO_PZRF_P2                          *((volatile  uint8_t *)(0x42DEE788UL))
#define bFM4_GPIO_PZRF_P2                         *((volatile  uint8_t *)(0x42DEE788UL))
#define bFM_GPIO_PZRF_P3                          *((volatile  uint8_t *)(0x42DEE78CUL))
#define bFM4_GPIO_PZRF_P3                         *((volatile  uint8_t *)(0x42DEE78CUL))
#define bFM_GPIO_PZRF_P4                          *((volatile  uint8_t *)(0x42DEE790UL))
#define bFM4_GPIO_PZRF_P4                         *((volatile  uint8_t *)(0x42DEE790UL))
#define bFM_GPIO_PZRF_P5                          *((volatile  uint8_t *)(0x42DEE794UL))
#define bFM4_GPIO_PZRF_P5                         *((volatile  uint8_t *)(0x42DEE794UL))
#define bFM_GPIO_PZRF_P6                          *((volatile  uint8_t *)(0x42DEE798UL))
#define bFM4_GPIO_PZRF_P6                         *((volatile  uint8_t *)(0x42DEE798UL))
#define bFM_GPIO_PZRF_P7                          *((volatile  uint8_t *)(0x42DEE79CUL))
#define bFM4_GPIO_PZRF_P7                         *((volatile  uint8_t *)(0x42DEE79CUL))

#define bFM_GPIO_SPSR_USB0C                       *((volatile  uint8_t *)(0x42DEB010UL))
#define bFM4_GPIO_SPSR_USB0C                      *((volatile  uint8_t *)(0x42DEB010UL))
#define bFM_GPIO_SPSR_USB1C                       *((volatile  uint8_t *)(0x42DEB014UL))
#define bFM4_GPIO_SPSR_USB1C                      *((volatile  uint8_t *)(0x42DEB014UL))


/*******************************************************************************
* HSSPI Registers HSSPI
*   Bitband Section
*******************************************************************************/

/*******************************************************************************
* HWWDT Registers HWWDT
*   Bitband Section
*******************************************************************************/
#define bFM_HWWDT_WDG_CTL_INTEN                   *((volatile  uint32_t*)(0x42220100UL))
#define bFM4_HWWDT_WDG_CTL_INTEN                  *((volatile  uint32_t*)(0x42220100UL))
#define bFM_HWWDT_WDG_CTL_RESEN                   *((volatile  uint32_t*)(0x42220104UL))
#define bFM4_HWWDT_WDG_CTL_RESEN                  *((volatile  uint32_t*)(0x42220104UL))

#define bFM_HWWDT_WDG_RIS_RIS                     *((volatile  uint32_t*)(0x42220200UL))
#define bFM4_HWWDT_WDG_RIS_RIS                    *((volatile  uint32_t*)(0x42220200UL))


/*******************************************************************************
* I2S Registers I2S0
*   Bitband Section
*******************************************************************************/
#define bFM_I2S0_CNTREG_FSPL                      *((volatile  uint8_t *)(0x42D80100UL))
#define bFM4_I2S0_CNTREG_FSPL                     *((volatile  uint8_t *)(0x42D80100UL))
#define bFM_I2S0_CNTREG_FSLN                      *((volatile  uint8_t *)(0x42D80104UL))
#define bFM4_I2S0_CNTREG_FSLN                     *((volatile  uint8_t *)(0x42D80104UL))
#define bFM_I2S0_CNTREG_FSPH                      *((volatile  uint8_t *)(0x42D80108UL))
#define bFM4_I2S0_CNTREG_FSPH                     *((volatile  uint8_t *)(0x42D80108UL))
#define bFM_I2S0_CNTREG_CPOL                      *((volatile  uint8_t *)(0x42D8010CUL))
#define bFM4_I2S0_CNTREG_CPOL                     *((volatile  uint8_t *)(0x42D8010CUL))
#define bFM_I2S0_CNTREG_SMPL                      *((volatile  uint8_t *)(0x42D80110UL))
#define bFM4_I2S0_CNTREG_SMPL                     *((volatile  uint8_t *)(0x42D80110UL))
#define bFM_I2S0_CNTREG_RXDIS                     *((volatile  uint8_t *)(0x42D80114UL))
#define bFM4_I2S0_CNTREG_RXDIS                    *((volatile  uint8_t *)(0x42D80114UL))
#define bFM_I2S0_CNTREG_TXDIS                     *((volatile  uint8_t *)(0x42D80118UL))
#define bFM4_I2S0_CNTREG_TXDIS                    *((volatile  uint8_t *)(0x42D80118UL))
#define bFM_I2S0_CNTREG_MLSB                      *((volatile  uint8_t *)(0x42D8011CUL))
#define bFM4_I2S0_CNTREG_MLSB                     *((volatile  uint8_t *)(0x42D8011CUL))
#define bFM_I2S0_CNTREG_FRUN                      *((volatile  uint8_t *)(0x42D80120UL))
#define bFM4_I2S0_CNTREG_FRUN                     *((volatile  uint8_t *)(0x42D80120UL))
#define bFM_I2S0_CNTREG_BEXT                      *((volatile  uint8_t *)(0x42D80124UL))
#define bFM4_I2S0_CNTREG_BEXT                     *((volatile  uint8_t *)(0x42D80124UL))
#define bFM_I2S0_CNTREG_ECKM                      *((volatile  uint8_t *)(0x42D80128UL))
#define bFM4_I2S0_CNTREG_ECKM                     *((volatile  uint8_t *)(0x42D80128UL))
#define bFM_I2S0_CNTREG_RHLL                      *((volatile  uint8_t *)(0x42D8012CUL))
#define bFM4_I2S0_CNTREG_RHLL                     *((volatile  uint8_t *)(0x42D8012CUL))
#define bFM_I2S0_CNTREG_SBFN                      *((volatile  uint8_t *)(0x42D80130UL))
#define bFM4_I2S0_CNTREG_SBFN                     *((volatile  uint8_t *)(0x42D80130UL))
#define bFM_I2S0_CNTREG_MSMD                      *((volatile  uint8_t *)(0x42D80134UL))
#define bFM4_I2S0_CNTREG_MSMD                     *((volatile  uint8_t *)(0x42D80134UL))
#define bFM_I2S0_CNTREG_MSKB                      *((volatile  uint8_t *)(0x42D80138UL))
#define bFM4_I2S0_CNTREG_MSKB                     *((volatile  uint8_t *)(0x42D80138UL))

#define bFM_I2S0_DMAACT_RDMACT                    *((volatile  uint8_t *)(0x42D80500UL))
#define bFM4_I2S0_DMAACT_RDMACT                   *((volatile  uint8_t *)(0x42D80500UL))
#define bFM_I2S0_DMAACT_RL1E0                     *((volatile  uint8_t *)(0x42D80520UL))
#define bFM4_I2S0_DMAACT_RL1E0                    *((volatile  uint8_t *)(0x42D80520UL))
#define bFM_I2S0_DMAACT_TDMACT                    *((volatile  uint8_t *)(0x42D80540UL))
#define bFM4_I2S0_DMAACT_TDMACT                   *((volatile  uint8_t *)(0x42D80540UL))
#define bFM_I2S0_DMAACT_TL1E0                     *((volatile  uint8_t *)(0x42D80560UL))
#define bFM4_I2S0_DMAACT_TL1E0                    *((volatile  uint8_t *)(0x42D80560UL))

#define bFM_I2S0_INTCNT_RXFIM                     *((volatile  uint8_t *)(0x42D80440UL))
#define bFM4_I2S0_INTCNT_RXFIM                    *((volatile  uint8_t *)(0x42D80440UL))
#define bFM_I2S0_INTCNT_RXFDM                     *((volatile  uint8_t *)(0x42D80444UL))
#define bFM4_I2S0_INTCNT_RXFDM                    *((volatile  uint8_t *)(0x42D80444UL))
#define bFM_I2S0_INTCNT_EOPM                      *((volatile  uint8_t *)(0x42D80448UL))
#define bFM4_I2S0_INTCNT_EOPM                     *((volatile  uint8_t *)(0x42D80448UL))
#define bFM_I2S0_INTCNT_RXOVM                     *((volatile  uint8_t *)(0x42D8044CUL))
#define bFM4_I2S0_INTCNT_RXOVM                    *((volatile  uint8_t *)(0x42D8044CUL))
#define bFM_I2S0_INTCNT_RXUDM                     *((volatile  uint8_t *)(0x42D80450UL))
#define bFM4_I2S0_INTCNT_RXUDM                    *((volatile  uint8_t *)(0x42D80450UL))
#define bFM_I2S0_INTCNT_RBERM                     *((volatile  uint8_t *)(0x42D80454UL))
#define bFM4_I2S0_INTCNT_RBERM                    *((volatile  uint8_t *)(0x42D80454UL))
#define bFM_I2S0_INTCNT_TXFIM                     *((volatile  uint8_t *)(0x42D80460UL))
#define bFM4_I2S0_INTCNT_TXFIM                    *((volatile  uint8_t *)(0x42D80460UL))
#define bFM_I2S0_INTCNT_TXFDM                     *((volatile  uint8_t *)(0x42D80464UL))
#define bFM4_I2S0_INTCNT_TXFDM                    *((volatile  uint8_t *)(0x42D80464UL))
#define bFM_I2S0_INTCNT_TXOVM                     *((volatile  uint8_t *)(0x42D80468UL))
#define bFM4_I2S0_INTCNT_TXOVM                    *((volatile  uint8_t *)(0x42D80468UL))
#define bFM_I2S0_INTCNT_TXUD0M                    *((volatile  uint8_t *)(0x42D8046CUL))
#define bFM4_I2S0_INTCNT_TXUD0M                   *((volatile  uint8_t *)(0x42D8046CUL))
#define bFM_I2S0_INTCNT_FERRM                     *((volatile  uint8_t *)(0x42D80470UL))
#define bFM4_I2S0_INTCNT_FERRM                    *((volatile  uint8_t *)(0x42D80470UL))
#define bFM_I2S0_INTCNT_TBERM                     *((volatile  uint8_t *)(0x42D80474UL))
#define bFM4_I2S0_INTCNT_TBERM                    *((volatile  uint8_t *)(0x42D80474UL))
#define bFM_I2S0_INTCNT_TXUD1M                    *((volatile  uint8_t *)(0x42D80478UL))
#define bFM4_I2S0_INTCNT_TXUD1M                   *((volatile  uint8_t *)(0x42D80478UL))

#define bFM_I2S0_MCR1REG_S0CH00                   *((volatile  uint8_t *)(0x42D80200UL))
#define bFM4_I2S0_MCR1REG_S0CH00                  *((volatile  uint8_t *)(0x42D80200UL))
#define bFM_I2S0_MCR1REG_S0CH01                   *((volatile  uint8_t *)(0x42D80204UL))
#define bFM4_I2S0_MCR1REG_S0CH01                  *((volatile  uint8_t *)(0x42D80204UL))
#define bFM_I2S0_MCR1REG_S0CH02                   *((volatile  uint8_t *)(0x42D80208UL))
#define bFM4_I2S0_MCR1REG_S0CH02                  *((volatile  uint8_t *)(0x42D80208UL))
#define bFM_I2S0_MCR1REG_S0CH03                   *((volatile  uint8_t *)(0x42D8020CUL))
#define bFM4_I2S0_MCR1REG_S0CH03                  *((volatile  uint8_t *)(0x42D8020CUL))
#define bFM_I2S0_MCR1REG_S0CH04                   *((volatile  uint8_t *)(0x42D80210UL))
#define bFM4_I2S0_MCR1REG_S0CH04                  *((volatile  uint8_t *)(0x42D80210UL))
#define bFM_I2S0_MCR1REG_S0CH05                   *((volatile  uint8_t *)(0x42D80214UL))
#define bFM4_I2S0_MCR1REG_S0CH05                  *((volatile  uint8_t *)(0x42D80214UL))
#define bFM_I2S0_MCR1REG_S0CH06                   *((volatile  uint8_t *)(0x42D80218UL))
#define bFM4_I2S0_MCR1REG_S0CH06                  *((volatile  uint8_t *)(0x42D80218UL))
#define bFM_I2S0_MCR1REG_S0CH07                   *((volatile  uint8_t *)(0x42D8021CUL))
#define bFM4_I2S0_MCR1REG_S0CH07                  *((volatile  uint8_t *)(0x42D8021CUL))
#define bFM_I2S0_MCR1REG_S0CH08                   *((volatile  uint8_t *)(0x42D80220UL))
#define bFM4_I2S0_MCR1REG_S0CH08                  *((volatile  uint8_t *)(0x42D80220UL))
#define bFM_I2S0_MCR1REG_S0CH09                   *((volatile  uint8_t *)(0x42D80224UL))
#define bFM4_I2S0_MCR1REG_S0CH09                  *((volatile  uint8_t *)(0x42D80224UL))
#define bFM_I2S0_MCR1REG_S0CH10                   *((volatile  uint8_t *)(0x42D80228UL))
#define bFM4_I2S0_MCR1REG_S0CH10                  *((volatile  uint8_t *)(0x42D80228UL))
#define bFM_I2S0_MCR1REG_S0CH11                   *((volatile  uint8_t *)(0x42D8022CUL))
#define bFM4_I2S0_MCR1REG_S0CH11                  *((volatile  uint8_t *)(0x42D8022CUL))
#define bFM_I2S0_MCR1REG_S0CH12                   *((volatile  uint8_t *)(0x42D80230UL))
#define bFM4_I2S0_MCR1REG_S0CH12                  *((volatile  uint8_t *)(0x42D80230UL))
#define bFM_I2S0_MCR1REG_S0CH13                   *((volatile  uint8_t *)(0x42D80234UL))
#define bFM4_I2S0_MCR1REG_S0CH13                  *((volatile  uint8_t *)(0x42D80234UL))
#define bFM_I2S0_MCR1REG_S0CH14                   *((volatile  uint8_t *)(0x42D80238UL))
#define bFM4_I2S0_MCR1REG_S0CH14                  *((volatile  uint8_t *)(0x42D80238UL))
#define bFM_I2S0_MCR1REG_S0CH15                   *((volatile  uint8_t *)(0x42D8023CUL))
#define bFM4_I2S0_MCR1REG_S0CH15                  *((volatile  uint8_t *)(0x42D8023CUL))
#define bFM_I2S0_MCR1REG_S0CH16                   *((volatile  uint8_t *)(0x42D80240UL))
#define bFM4_I2S0_MCR1REG_S0CH16                  *((volatile  uint8_t *)(0x42D80240UL))
#define bFM_I2S0_MCR1REG_S0CH17                   *((volatile  uint8_t *)(0x42D80244UL))
#define bFM4_I2S0_MCR1REG_S0CH17                  *((volatile  uint8_t *)(0x42D80244UL))
#define bFM_I2S0_MCR1REG_S0CH18                   *((volatile  uint8_t *)(0x42D80248UL))
#define bFM4_I2S0_MCR1REG_S0CH18                  *((volatile  uint8_t *)(0x42D80248UL))
#define bFM_I2S0_MCR1REG_S0CH19                   *((volatile  uint8_t *)(0x42D8024CUL))
#define bFM4_I2S0_MCR1REG_S0CH19                  *((volatile  uint8_t *)(0x42D8024CUL))
#define bFM_I2S0_MCR1REG_S0CH20                   *((volatile  uint8_t *)(0x42D80250UL))
#define bFM4_I2S0_MCR1REG_S0CH20                  *((volatile  uint8_t *)(0x42D80250UL))
#define bFM_I2S0_MCR1REG_S0CH21                   *((volatile  uint8_t *)(0x42D80254UL))
#define bFM4_I2S0_MCR1REG_S0CH21                  *((volatile  uint8_t *)(0x42D80254UL))
#define bFM_I2S0_MCR1REG_S0CH22                   *((volatile  uint8_t *)(0x42D80258UL))
#define bFM4_I2S0_MCR1REG_S0CH22                  *((volatile  uint8_t *)(0x42D80258UL))
#define bFM_I2S0_MCR1REG_S0CH23                   *((volatile  uint8_t *)(0x42D8025CUL))
#define bFM4_I2S0_MCR1REG_S0CH23                  *((volatile  uint8_t *)(0x42D8025CUL))
#define bFM_I2S0_MCR1REG_S0CH24                   *((volatile  uint8_t *)(0x42D80260UL))
#define bFM4_I2S0_MCR1REG_S0CH24                  *((volatile  uint8_t *)(0x42D80260UL))
#define bFM_I2S0_MCR1REG_S0CH25                   *((volatile  uint8_t *)(0x42D80264UL))
#define bFM4_I2S0_MCR1REG_S0CH25                  *((volatile  uint8_t *)(0x42D80264UL))
#define bFM_I2S0_MCR1REG_S0CH26                   *((volatile  uint8_t *)(0x42D80268UL))
#define bFM4_I2S0_MCR1REG_S0CH26                  *((volatile  uint8_t *)(0x42D80268UL))
#define bFM_I2S0_MCR1REG_S0CH27                   *((volatile  uint8_t *)(0x42D8026CUL))
#define bFM4_I2S0_MCR1REG_S0CH27                  *((volatile  uint8_t *)(0x42D8026CUL))
#define bFM_I2S0_MCR1REG_S0CH28                   *((volatile  uint8_t *)(0x42D80270UL))
#define bFM4_I2S0_MCR1REG_S0CH28                  *((volatile  uint8_t *)(0x42D80270UL))
#define bFM_I2S0_MCR1REG_S0CH29                   *((volatile  uint8_t *)(0x42D80274UL))
#define bFM4_I2S0_MCR1REG_S0CH29                  *((volatile  uint8_t *)(0x42D80274UL))
#define bFM_I2S0_MCR1REG_S0CH30                   *((volatile  uint8_t *)(0x42D80278UL))
#define bFM4_I2S0_MCR1REG_S0CH30                  *((volatile  uint8_t *)(0x42D80278UL))
#define bFM_I2S0_MCR1REG_S0CH31                   *((volatile  uint8_t *)(0x42D8027CUL))
#define bFM4_I2S0_MCR1REG_S0CH31                  *((volatile  uint8_t *)(0x42D8027CUL))

#define bFM_I2S0_MCR2REG_S1CH00                   *((volatile  uint8_t *)(0x42D80280UL))
#define bFM4_I2S0_MCR2REG_S1CH00                  *((volatile  uint8_t *)(0x42D80280UL))
#define bFM_I2S0_MCR2REG_S1CH01                   *((volatile  uint8_t *)(0x42D80284UL))
#define bFM4_I2S0_MCR2REG_S1CH01                  *((volatile  uint8_t *)(0x42D80284UL))
#define bFM_I2S0_MCR2REG_S1CH02                   *((volatile  uint8_t *)(0x42D80288UL))
#define bFM4_I2S0_MCR2REG_S1CH02                  *((volatile  uint8_t *)(0x42D80288UL))
#define bFM_I2S0_MCR2REG_S1CH03                   *((volatile  uint8_t *)(0x42D8028CUL))
#define bFM4_I2S0_MCR2REG_S1CH03                  *((volatile  uint8_t *)(0x42D8028CUL))
#define bFM_I2S0_MCR2REG_S1CH04                   *((volatile  uint8_t *)(0x42D80290UL))
#define bFM4_I2S0_MCR2REG_S1CH04                  *((volatile  uint8_t *)(0x42D80290UL))
#define bFM_I2S0_MCR2REG_S1CH05                   *((volatile  uint8_t *)(0x42D80294UL))
#define bFM4_I2S0_MCR2REG_S1CH05                  *((volatile  uint8_t *)(0x42D80294UL))
#define bFM_I2S0_MCR2REG_S1CH06                   *((volatile  uint8_t *)(0x42D80298UL))
#define bFM4_I2S0_MCR2REG_S1CH06                  *((volatile  uint8_t *)(0x42D80298UL))
#define bFM_I2S0_MCR2REG_S1CH07                   *((volatile  uint8_t *)(0x42D8029CUL))
#define bFM4_I2S0_MCR2REG_S1CH07                  *((volatile  uint8_t *)(0x42D8029CUL))
#define bFM_I2S0_MCR2REG_S1CH08                   *((volatile  uint8_t *)(0x42D802A0UL))
#define bFM4_I2S0_MCR2REG_S1CH08                  *((volatile  uint8_t *)(0x42D802A0UL))
#define bFM_I2S0_MCR2REG_S1CH09                   *((volatile  uint8_t *)(0x42D802A4UL))
#define bFM4_I2S0_MCR2REG_S1CH09                  *((volatile  uint8_t *)(0x42D802A4UL))
#define bFM_I2S0_MCR2REG_S1CH10                   *((volatile  uint8_t *)(0x42D802A8UL))
#define bFM4_I2S0_MCR2REG_S1CH10                  *((volatile  uint8_t *)(0x42D802A8UL))
#define bFM_I2S0_MCR2REG_S1CH11                   *((volatile  uint8_t *)(0x42D802ACUL))
#define bFM4_I2S0_MCR2REG_S1CH11                  *((volatile  uint8_t *)(0x42D802ACUL))
#define bFM_I2S0_MCR2REG_S1CH12                   *((volatile  uint8_t *)(0x42D802B0UL))
#define bFM4_I2S0_MCR2REG_S1CH12                  *((volatile  uint8_t *)(0x42D802B0UL))
#define bFM_I2S0_MCR2REG_S1CH13                   *((volatile  uint8_t *)(0x42D802B4UL))
#define bFM4_I2S0_MCR2REG_S1CH13                  *((volatile  uint8_t *)(0x42D802B4UL))
#define bFM_I2S0_MCR2REG_S1CH14                   *((volatile  uint8_t *)(0x42D802B8UL))
#define bFM4_I2S0_MCR2REG_S1CH14                  *((volatile  uint8_t *)(0x42D802B8UL))
#define bFM_I2S0_MCR2REG_S1CH15                   *((volatile  uint8_t *)(0x42D802BCUL))
#define bFM4_I2S0_MCR2REG_S1CH15                  *((volatile  uint8_t *)(0x42D802BCUL))
#define bFM_I2S0_MCR2REG_S1CH16                   *((volatile  uint8_t *)(0x42D802C0UL))
#define bFM4_I2S0_MCR2REG_S1CH16                  *((volatile  uint8_t *)(0x42D802C0UL))
#define bFM_I2S0_MCR2REG_S1CH17                   *((volatile  uint8_t *)(0x42D802C4UL))
#define bFM4_I2S0_MCR2REG_S1CH17                  *((volatile  uint8_t *)(0x42D802C4UL))
#define bFM_I2S0_MCR2REG_S1CH18                   *((volatile  uint8_t *)(0x42D802C8UL))
#define bFM4_I2S0_MCR2REG_S1CH18                  *((volatile  uint8_t *)(0x42D802C8UL))
#define bFM_I2S0_MCR2REG_S1CH19                   *((volatile  uint8_t *)(0x42D802CCUL))
#define bFM4_I2S0_MCR2REG_S1CH19                  *((volatile  uint8_t *)(0x42D802CCUL))
#define bFM_I2S0_MCR2REG_S1CH20                   *((volatile  uint8_t *)(0x42D802D0UL))
#define bFM4_I2S0_MCR2REG_S1CH20                  *((volatile  uint8_t *)(0x42D802D0UL))
#define bFM_I2S0_MCR2REG_S1CH21                   *((volatile  uint8_t *)(0x42D802D4UL))
#define bFM4_I2S0_MCR2REG_S1CH21                  *((volatile  uint8_t *)(0x42D802D4UL))
#define bFM_I2S0_MCR2REG_S1CH22                   *((volatile  uint8_t *)(0x42D802D8UL))
#define bFM4_I2S0_MCR2REG_S1CH22                  *((volatile  uint8_t *)(0x42D802D8UL))
#define bFM_I2S0_MCR2REG_S1CH23                   *((volatile  uint8_t *)(0x42D802DCUL))
#define bFM4_I2S0_MCR2REG_S1CH23                  *((volatile  uint8_t *)(0x42D802DCUL))
#define bFM_I2S0_MCR2REG_S1CH24                   *((volatile  uint8_t *)(0x42D802E0UL))
#define bFM4_I2S0_MCR2REG_S1CH24                  *((volatile  uint8_t *)(0x42D802E0UL))
#define bFM_I2S0_MCR2REG_S1CH25                   *((volatile  uint8_t *)(0x42D802E4UL))
#define bFM4_I2S0_MCR2REG_S1CH25                  *((volatile  uint8_t *)(0x42D802E4UL))
#define bFM_I2S0_MCR2REG_S1CH26                   *((volatile  uint8_t *)(0x42D802E8UL))
#define bFM4_I2S0_MCR2REG_S1CH26                  *((volatile  uint8_t *)(0x42D802E8UL))
#define bFM_I2S0_MCR2REG_S1CH27                   *((volatile  uint8_t *)(0x42D802ECUL))
#define bFM4_I2S0_MCR2REG_S1CH27                  *((volatile  uint8_t *)(0x42D802ECUL))
#define bFM_I2S0_MCR2REG_S1CH28                   *((volatile  uint8_t *)(0x42D802F0UL))
#define bFM4_I2S0_MCR2REG_S1CH28                  *((volatile  uint8_t *)(0x42D802F0UL))
#define bFM_I2S0_MCR2REG_S1CH29                   *((volatile  uint8_t *)(0x42D802F4UL))
#define bFM4_I2S0_MCR2REG_S1CH29                  *((volatile  uint8_t *)(0x42D802F4UL))
#define bFM_I2S0_MCR2REG_S1CH30                   *((volatile  uint8_t *)(0x42D802F8UL))
#define bFM4_I2S0_MCR2REG_S1CH30                  *((volatile  uint8_t *)(0x42D802F8UL))
#define bFM_I2S0_MCR2REG_S1CH31                   *((volatile  uint8_t *)(0x42D802FCUL))
#define bFM4_I2S0_MCR2REG_S1CH31                  *((volatile  uint8_t *)(0x42D802FCUL))

#define bFM_I2S0_OPRREG_START                     *((volatile  uint8_t *)(0x42D80300UL))
#define bFM4_I2S0_OPRREG_START                    *((volatile  uint8_t *)(0x42D80300UL))
#define bFM_I2S0_OPRREG_TXENB                     *((volatile  uint8_t *)(0x42D80340UL))
#define bFM4_I2S0_OPRREG_TXENB                    *((volatile  uint8_t *)(0x42D80340UL))
#define bFM_I2S0_OPRREG_RXENB                     *((volatile  uint8_t *)(0x42D80360UL))
#define bFM4_I2S0_OPRREG_RXENB                    *((volatile  uint8_t *)(0x42D80360UL))

#define bFM_I2S0_SRST_SRST                        *((volatile  uint8_t *)(0x42D80380UL))
#define bFM4_I2S0_SRST_SRST                       *((volatile  uint8_t *)(0x42D80380UL))

#define bFM_I2S0_STATUS_RXFI                      *((volatile  uint8_t *)(0x42D804C0UL))
#define bFM4_I2S0_STATUS_RXFI                     *((volatile  uint8_t *)(0x42D804C0UL))
#define bFM_I2S0_STATUS_TXFI                      *((volatile  uint8_t *)(0x42D804C4UL))
#define bFM4_I2S0_STATUS_TXFI                     *((volatile  uint8_t *)(0x42D804C4UL))
#define bFM_I2S0_STATUS_BSY                       *((volatile  uint8_t *)(0x42D804C8UL))
#define bFM4_I2S0_STATUS_BSY                      *((volatile  uint8_t *)(0x42D804C8UL))
#define bFM_I2S0_STATUS_EOPI                      *((volatile  uint8_t *)(0x42D804CCUL))
#define bFM4_I2S0_STATUS_EOPI                     *((volatile  uint8_t *)(0x42D804CCUL))
#define bFM_I2S0_STATUS_RXOVR                     *((volatile  uint8_t *)(0x42D804E0UL))
#define bFM4_I2S0_STATUS_RXOVR                    *((volatile  uint8_t *)(0x42D804E0UL))
#define bFM_I2S0_STATUS_RXUDR                     *((volatile  uint8_t *)(0x42D804E4UL))
#define bFM4_I2S0_STATUS_RXUDR                    *((volatile  uint8_t *)(0x42D804E4UL))
#define bFM_I2S0_STATUS_TXOVR                     *((volatile  uint8_t *)(0x42D804E8UL))
#define bFM4_I2S0_STATUS_TXOVR                    *((volatile  uint8_t *)(0x42D804E8UL))
#define bFM_I2S0_STATUS_TXUDR0                    *((volatile  uint8_t *)(0x42D804ECUL))
#define bFM4_I2S0_STATUS_TXUDR0                   *((volatile  uint8_t *)(0x42D804ECUL))
#define bFM_I2S0_STATUS_TXUDR1                    *((volatile  uint8_t *)(0x42D804F0UL))
#define bFM4_I2S0_STATUS_TXUDR1                   *((volatile  uint8_t *)(0x42D804F0UL))
#define bFM_I2S0_STATUS_FERR                      *((volatile  uint8_t *)(0x42D804F4UL))
#define bFM4_I2S0_STATUS_FERR                     *((volatile  uint8_t *)(0x42D804F4UL))
#define bFM_I2S0_STATUS_RBERR                     *((volatile  uint8_t *)(0x42D804F8UL))
#define bFM4_I2S0_STATUS_RBERR                    *((volatile  uint8_t *)(0x42D804F8UL))
#define bFM_I2S0_STATUS_TBERR                     *((volatile  uint8_t *)(0x42D804FCUL))
#define bFM4_I2S0_STATUS_TBERR                    *((volatile  uint8_t *)(0x42D804FCUL))

#define bFM_I2S0_TSTREG_LBMD                      *((volatile  uint8_t *)(0x42D80580UL))
#define bFM4_I2S0_TSTREG_LBMD                     *((volatile  uint8_t *)(0x42D80580UL))


/*******************************************************************************
* I2SPRE Registers I2SPRE
*   Bitband Section
*******************************************************************************/
#define bFM_I2SPRE_ICCR_I2SEN                     *((volatile  uint8_t *)(0x427A0000UL))
#define bFM4_I2SPRE_ICCR_I2SEN                    *((volatile  uint8_t *)(0x427A0000UL))
#define bFM_I2SPRE_ICCR_ICSEL                     *((volatile  uint8_t *)(0x427A0004UL))
#define bFM4_I2SPRE_ICCR_ICSEL                    *((volatile  uint8_t *)(0x427A0004UL))

#define bFM_I2SPRE_IP_STR_IPRDY                   *((volatile  uint8_t *)(0x427A0280UL))
#define bFM4_I2SPRE_IP_STR_IPRDY                  *((volatile  uint8_t *)(0x427A0280UL))

#define bFM_I2SPRE_IPCR1_IPLLEN                   *((volatile  uint8_t *)(0x427A0080UL))
#define bFM4_I2SPRE_IPCR1_IPLLEN                  *((volatile  uint8_t *)(0x427A0080UL))

#define bFM_I2SPRE_IPINT_CLR_IPCSC                *((volatile  uint8_t *)(0x427A0380UL))
#define bFM4_I2SPRE_IPINT_CLR_IPCSC               *((volatile  uint8_t *)(0x427A0380UL))

#define bFM_I2SPRE_IPINT_ENR_IPCSE                *((volatile  uint8_t *)(0x427A0300UL))
#define bFM4_I2SPRE_IPINT_ENR_IPCSE               *((volatile  uint8_t *)(0x427A0300UL))

#define bFM_I2SPRE_IPINT_STR_IPCSI                *((volatile  uint8_t *)(0x427A0400UL))
#define bFM4_I2SPRE_IPINT_STR_IPCSI               *((volatile  uint8_t *)(0x427A0400UL))


/*******************************************************************************
* INTREQ Registers INTREQ
*   Bitband Section
*******************************************************************************/
#define bFM_INTREQ_DRQSEL_USBEP1                  *((volatile  uint8_t *)(0x42620000UL))
#define bFM4_INTREQ_DRQSEL_USBEP1                 *((volatile  uint8_t *)(0x42620000UL))
#define bFM_INTREQ_DRQSEL_USBEP2                  *((volatile  uint8_t *)(0x42620004UL))
#define bFM4_INTREQ_DRQSEL_USBEP2                 *((volatile  uint8_t *)(0x42620004UL))
#define bFM_INTREQ_DRQSEL_USBEP3                  *((volatile  uint8_t *)(0x42620008UL))
#define bFM4_INTREQ_DRQSEL_USBEP3                 *((volatile  uint8_t *)(0x42620008UL))
#define bFM_INTREQ_DRQSEL_USBEP4                  *((volatile  uint8_t *)(0x4262000CUL))
#define bFM4_INTREQ_DRQSEL_USBEP4                 *((volatile  uint8_t *)(0x4262000CUL))
#define bFM_INTREQ_DRQSEL_USBEP5                  *((volatile  uint8_t *)(0x42620010UL))
#define bFM4_INTREQ_DRQSEL_USBEP5                 *((volatile  uint8_t *)(0x42620010UL))
#define bFM_INTREQ_DRQSEL_ADCSCAN0                *((volatile  uint8_t *)(0x42620014UL))
#define bFM4_INTREQ_DRQSEL_ADCSCAN0               *((volatile  uint8_t *)(0x42620014UL))
#define bFM_INTREQ_DRQSEL_ADCSCAN1                *((volatile  uint8_t *)(0x42620018UL))
#define bFM4_INTREQ_DRQSEL_ADCSCAN1               *((volatile  uint8_t *)(0x42620018UL))
#define bFM_INTREQ_DRQSEL_ADCSCAN2                *((volatile  uint8_t *)(0x4262001CUL))
#define bFM4_INTREQ_DRQSEL_ADCSCAN2               *((volatile  uint8_t *)(0x4262001CUL))
#define bFM_INTREQ_DRQSEL_IRQ0BT0                 *((volatile  uint8_t *)(0x42620020UL))
#define bFM4_INTREQ_DRQSEL_IRQ0BT0                *((volatile  uint8_t *)(0x42620020UL))
#define bFM_INTREQ_DRQSEL_IRQ0BT2                 *((volatile  uint8_t *)(0x42620024UL))
#define bFM4_INTREQ_DRQSEL_IRQ0BT2                *((volatile  uint8_t *)(0x42620024UL))
#define bFM_INTREQ_DRQSEL_IRQ0BT4                 *((volatile  uint8_t *)(0x42620028UL))
#define bFM4_INTREQ_DRQSEL_IRQ0BT4                *((volatile  uint8_t *)(0x42620028UL))
#define bFM_INTREQ_DRQSEL_IRQ0BT6                 *((volatile  uint8_t *)(0x4262002CUL))
#define bFM4_INTREQ_DRQSEL_IRQ0BT6                *((volatile  uint8_t *)(0x4262002CUL))
#define bFM_INTREQ_DRQSEL_MFS0RX                  *((volatile  uint8_t *)(0x42620030UL))
#define bFM4_INTREQ_DRQSEL_MFS0RX                 *((volatile  uint8_t *)(0x42620030UL))
#define bFM_INTREQ_DRQSEL_MFS0TX                  *((volatile  uint8_t *)(0x42620034UL))
#define bFM4_INTREQ_DRQSEL_MFS0TX                 *((volatile  uint8_t *)(0x42620034UL))
#define bFM_INTREQ_DRQSEL_MFS1RX                  *((volatile  uint8_t *)(0x42620038UL))
#define bFM4_INTREQ_DRQSEL_MFS1RX                 *((volatile  uint8_t *)(0x42620038UL))
#define bFM_INTREQ_DRQSEL_MFS1TX                  *((volatile  uint8_t *)(0x4262003CUL))
#define bFM4_INTREQ_DRQSEL_MFS1TX                 *((volatile  uint8_t *)(0x4262003CUL))
#define bFM_INTREQ_DRQSEL_MFS2RX                  *((volatile  uint8_t *)(0x42620040UL))
#define bFM4_INTREQ_DRQSEL_MFS2RX                 *((volatile  uint8_t *)(0x42620040UL))
#define bFM_INTREQ_DRQSEL_MFS2TX                  *((volatile  uint8_t *)(0x42620044UL))
#define bFM4_INTREQ_DRQSEL_MFS2TX                 *((volatile  uint8_t *)(0x42620044UL))
#define bFM_INTREQ_DRQSEL_MFS3RX                  *((volatile  uint8_t *)(0x42620048UL))
#define bFM4_INTREQ_DRQSEL_MFS3RX                 *((volatile  uint8_t *)(0x42620048UL))
#define bFM_INTREQ_DRQSEL_MFS3TX                  *((volatile  uint8_t *)(0x4262004CUL))
#define bFM4_INTREQ_DRQSEL_MFS3TX                 *((volatile  uint8_t *)(0x4262004CUL))
#define bFM_INTREQ_DRQSEL_MFS4RX                  *((volatile  uint8_t *)(0x42620050UL))
#define bFM4_INTREQ_DRQSEL_MFS4RX                 *((volatile  uint8_t *)(0x42620050UL))
#define bFM_INTREQ_DRQSEL_MFS4TX                  *((volatile  uint8_t *)(0x42620054UL))
#define bFM4_INTREQ_DRQSEL_MFS4TX                 *((volatile  uint8_t *)(0x42620054UL))
#define bFM_INTREQ_DRQSEL_MFS5RX                  *((volatile  uint8_t *)(0x42620058UL))
#define bFM4_INTREQ_DRQSEL_MFS5RX                 *((volatile  uint8_t *)(0x42620058UL))
#define bFM_INTREQ_DRQSEL_MFS5TX                  *((volatile  uint8_t *)(0x4262005CUL))
#define bFM4_INTREQ_DRQSEL_MFS5TX                 *((volatile  uint8_t *)(0x4262005CUL))
#define bFM_INTREQ_DRQSEL_MFS6RX                  *((volatile  uint8_t *)(0x42620060UL))
#define bFM4_INTREQ_DRQSEL_MFS6RX                 *((volatile  uint8_t *)(0x42620060UL))
#define bFM_INTREQ_DRQSEL_MFS6TX                  *((volatile  uint8_t *)(0x42620064UL))
#define bFM4_INTREQ_DRQSEL_MFS6TX                 *((volatile  uint8_t *)(0x42620064UL))
#define bFM_INTREQ_DRQSEL_MFS7RX                  *((volatile  uint8_t *)(0x42620068UL))
#define bFM4_INTREQ_DRQSEL_MFS7RX                 *((volatile  uint8_t *)(0x42620068UL))
#define bFM_INTREQ_DRQSEL_MFS7TX                  *((volatile  uint8_t *)(0x4262006CUL))
#define bFM4_INTREQ_DRQSEL_MFS7TX                 *((volatile  uint8_t *)(0x4262006CUL))
#define bFM_INTREQ_DRQSEL_EXINT0                  *((volatile  uint8_t *)(0x42620070UL))
#define bFM4_INTREQ_DRQSEL_EXINT0                 *((volatile  uint8_t *)(0x42620070UL))
#define bFM_INTREQ_DRQSEL_EXINT1                  *((volatile  uint8_t *)(0x42620074UL))
#define bFM4_INTREQ_DRQSEL_EXINT1                 *((volatile  uint8_t *)(0x42620074UL))
#define bFM_INTREQ_DRQSEL_EXINT2                  *((volatile  uint8_t *)(0x42620078UL))
#define bFM4_INTREQ_DRQSEL_EXINT2                 *((volatile  uint8_t *)(0x42620078UL))
#define bFM_INTREQ_DRQSEL_EXINT3                  *((volatile  uint8_t *)(0x4262007CUL))
#define bFM4_INTREQ_DRQSEL_EXINT3                 *((volatile  uint8_t *)(0x4262007CUL))

#define bFM_INTREQ_EXC02MON_NMI                   *((volatile  uint8_t *)(0x42624000UL))
#define bFM4_INTREQ_EXC02MON_NMI                  *((volatile  uint8_t *)(0x42624000UL))
#define bFM_INTREQ_EXC02MON_HWINT                 *((volatile  uint8_t *)(0x42624004UL))
#define bFM4_INTREQ_EXC02MON_HWINT                *((volatile  uint8_t *)(0x42624004UL))

#define bFM_INTREQ_IRQ000MON_FCSINT               *((volatile  uint8_t *)(0x42624080UL))
#define bFM4_INTREQ_IRQ000MON_FCSINT              *((volatile  uint8_t *)(0x42624080UL))

#define bFM_INTREQ_IRQ001MON_SWWDTINT             *((volatile  uint8_t *)(0x42624100UL))
#define bFM4_INTREQ_IRQ001MON_SWWDTINT            *((volatile  uint8_t *)(0x42624100UL))

#define bFM_INTREQ_IRQ002MON_LVDINT               *((volatile  uint8_t *)(0x42624180UL))
#define bFM4_INTREQ_IRQ002MON_LVDINT              *((volatile  uint8_t *)(0x42624180UL))

#define bFM_INTREQ_IRQ003MON_IRQBIT0              *((volatile  uint8_t *)(0x42624200UL))
#define bFM4_INTREQ_IRQ003MON_IRQBIT0             *((volatile  uint8_t *)(0x42624200UL))
#define bFM_INTREQ_IRQ003MON_IRQBIT1              *((volatile  uint8_t *)(0x42624204UL))
#define bFM4_INTREQ_IRQ003MON_IRQBIT1             *((volatile  uint8_t *)(0x42624204UL))
#define bFM_INTREQ_IRQ003MON_IRQBIT2              *((volatile  uint8_t *)(0x42624208UL))
#define bFM4_INTREQ_IRQ003MON_IRQBIT2             *((volatile  uint8_t *)(0x42624208UL))
#define bFM_INTREQ_IRQ003MON_IRQBIT3              *((volatile  uint8_t *)(0x4262420CUL))
#define bFM4_INTREQ_IRQ003MON_IRQBIT3             *((volatile  uint8_t *)(0x4262420CUL))
#define bFM_INTREQ_IRQ003MON_IRQBIT4              *((volatile  uint8_t *)(0x42624210UL))
#define bFM4_INTREQ_IRQ003MON_IRQBIT4             *((volatile  uint8_t *)(0x42624210UL))
#define bFM_INTREQ_IRQ003MON_IRQBIT5              *((volatile  uint8_t *)(0x42624214UL))
#define bFM4_INTREQ_IRQ003MON_IRQBIT5             *((volatile  uint8_t *)(0x42624214UL))
#define bFM_INTREQ_IRQ003MON_IRQBIT6              *((volatile  uint8_t *)(0x42624218UL))
#define bFM4_INTREQ_IRQ003MON_IRQBIT6             *((volatile  uint8_t *)(0x42624218UL))
#define bFM_INTREQ_IRQ003MON_IRQBIT7              *((volatile  uint8_t *)(0x4262421CUL))
#define bFM4_INTREQ_IRQ003MON_IRQBIT7             *((volatile  uint8_t *)(0x4262421CUL))

#define bFM_INTREQ_IRQ003SEL_SELBIT0              *((volatile  uint8_t *)(0x42622240UL))
#define bFM4_INTREQ_IRQ003SEL_SELBIT0             *((volatile  uint8_t *)(0x42622240UL))
#define bFM_INTREQ_IRQ003SEL_SELBIT1              *((volatile  uint8_t *)(0x42622244UL))
#define bFM4_INTREQ_IRQ003SEL_SELBIT1             *((volatile  uint8_t *)(0x42622244UL))
#define bFM_INTREQ_IRQ003SEL_SELBIT2              *((volatile  uint8_t *)(0x42622248UL))
#define bFM4_INTREQ_IRQ003SEL_SELBIT2             *((volatile  uint8_t *)(0x42622248UL))
#define bFM_INTREQ_IRQ003SEL_SELBIT3              *((volatile  uint8_t *)(0x4262224CUL))
#define bFM4_INTREQ_IRQ003SEL_SELBIT3             *((volatile  uint8_t *)(0x4262224CUL))
#define bFM_INTREQ_IRQ003SEL_SELBIT4              *((volatile  uint8_t *)(0x42622250UL))
#define bFM4_INTREQ_IRQ003SEL_SELBIT4             *((volatile  uint8_t *)(0x42622250UL))
#define bFM_INTREQ_IRQ003SEL_SELBIT5              *((volatile  uint8_t *)(0x42622254UL))
#define bFM4_INTREQ_IRQ003SEL_SELBIT5             *((volatile  uint8_t *)(0x42622254UL))
#define bFM_INTREQ_IRQ003SEL_SELBIT6              *((volatile  uint8_t *)(0x42622258UL))
#define bFM4_INTREQ_IRQ003SEL_SELBIT6             *((volatile  uint8_t *)(0x42622258UL))
#define bFM_INTREQ_IRQ003SEL_SELBIT7              *((volatile  uint8_t *)(0x4262225CUL))
#define bFM4_INTREQ_IRQ003SEL_SELBIT7             *((volatile  uint8_t *)(0x4262225CUL))
#define bFM_INTREQ_IRQ003SEL_SELBIT8              *((volatile  uint8_t *)(0x42622260UL))
#define bFM4_INTREQ_IRQ003SEL_SELBIT8             *((volatile  uint8_t *)(0x42622260UL))
#define bFM_INTREQ_IRQ003SEL_SELBIT9              *((volatile  uint8_t *)(0x42622264UL))
#define bFM4_INTREQ_IRQ003SEL_SELBIT9             *((volatile  uint8_t *)(0x42622264UL))
#define bFM_INTREQ_IRQ003SEL_SELBIT10             *((volatile  uint8_t *)(0x42622268UL))
#define bFM4_INTREQ_IRQ003SEL_SELBIT10            *((volatile  uint8_t *)(0x42622268UL))
#define bFM_INTREQ_IRQ003SEL_SELBIT11             *((volatile  uint8_t *)(0x4262226CUL))
#define bFM4_INTREQ_IRQ003SEL_SELBIT11            *((volatile  uint8_t *)(0x4262226CUL))
#define bFM_INTREQ_IRQ003SEL_SELBIT12             *((volatile  uint8_t *)(0x42622270UL))
#define bFM4_INTREQ_IRQ003SEL_SELBIT12            *((volatile  uint8_t *)(0x42622270UL))
#define bFM_INTREQ_IRQ003SEL_SELBIT13             *((volatile  uint8_t *)(0x42622274UL))
#define bFM4_INTREQ_IRQ003SEL_SELBIT13            *((volatile  uint8_t *)(0x42622274UL))
#define bFM_INTREQ_IRQ003SEL_SELBIT14             *((volatile  uint8_t *)(0x42622278UL))
#define bFM4_INTREQ_IRQ003SEL_SELBIT14            *((volatile  uint8_t *)(0x42622278UL))
#define bFM_INTREQ_IRQ003SEL_SELBIT15             *((volatile  uint8_t *)(0x4262227CUL))
#define bFM4_INTREQ_IRQ003SEL_SELBIT15            *((volatile  uint8_t *)(0x4262227CUL))

#define bFM_INTREQ_IRQ004MON_IRQBIT0              *((volatile  uint8_t *)(0x42624280UL))
#define bFM4_INTREQ_IRQ004MON_IRQBIT0             *((volatile  uint8_t *)(0x42624280UL))
#define bFM_INTREQ_IRQ004MON_IRQBIT1              *((volatile  uint8_t *)(0x42624284UL))
#define bFM4_INTREQ_IRQ004MON_IRQBIT1             *((volatile  uint8_t *)(0x42624284UL))
#define bFM_INTREQ_IRQ004MON_IRQBIT2              *((volatile  uint8_t *)(0x42624288UL))
#define bFM4_INTREQ_IRQ004MON_IRQBIT2             *((volatile  uint8_t *)(0x42624288UL))
#define bFM_INTREQ_IRQ004MON_IRQBIT3              *((volatile  uint8_t *)(0x4262428CUL))
#define bFM4_INTREQ_IRQ004MON_IRQBIT3             *((volatile  uint8_t *)(0x4262428CUL))
#define bFM_INTREQ_IRQ004MON_IRQBIT4              *((volatile  uint8_t *)(0x42624290UL))
#define bFM4_INTREQ_IRQ004MON_IRQBIT4             *((volatile  uint8_t *)(0x42624290UL))
#define bFM_INTREQ_IRQ004MON_IRQBIT5              *((volatile  uint8_t *)(0x42624294UL))
#define bFM4_INTREQ_IRQ004MON_IRQBIT5             *((volatile  uint8_t *)(0x42624294UL))
#define bFM_INTREQ_IRQ004MON_IRQBIT6              *((volatile  uint8_t *)(0x42624298UL))
#define bFM4_INTREQ_IRQ004MON_IRQBIT6             *((volatile  uint8_t *)(0x42624298UL))
#define bFM_INTREQ_IRQ004MON_IRQBIT7              *((volatile  uint8_t *)(0x4262429CUL))
#define bFM4_INTREQ_IRQ004MON_IRQBIT7             *((volatile  uint8_t *)(0x4262429CUL))

#define bFM_INTREQ_IRQ004SEL_SELBIT0              *((volatile  uint8_t *)(0x426222C0UL))
#define bFM4_INTREQ_IRQ004SEL_SELBIT0             *((volatile  uint8_t *)(0x426222C0UL))
#define bFM_INTREQ_IRQ004SEL_SELBIT1              *((volatile  uint8_t *)(0x426222C4UL))
#define bFM4_INTREQ_IRQ004SEL_SELBIT1             *((volatile  uint8_t *)(0x426222C4UL))
#define bFM_INTREQ_IRQ004SEL_SELBIT2              *((volatile  uint8_t *)(0x426222C8UL))
#define bFM4_INTREQ_IRQ004SEL_SELBIT2             *((volatile  uint8_t *)(0x426222C8UL))
#define bFM_INTREQ_IRQ004SEL_SELBIT3              *((volatile  uint8_t *)(0x426222CCUL))
#define bFM4_INTREQ_IRQ004SEL_SELBIT3             *((volatile  uint8_t *)(0x426222CCUL))
#define bFM_INTREQ_IRQ004SEL_SELBIT4              *((volatile  uint8_t *)(0x426222D0UL))
#define bFM4_INTREQ_IRQ004SEL_SELBIT4             *((volatile  uint8_t *)(0x426222D0UL))
#define bFM_INTREQ_IRQ004SEL_SELBIT5              *((volatile  uint8_t *)(0x426222D4UL))
#define bFM4_INTREQ_IRQ004SEL_SELBIT5             *((volatile  uint8_t *)(0x426222D4UL))
#define bFM_INTREQ_IRQ004SEL_SELBIT6              *((volatile  uint8_t *)(0x426222D8UL))
#define bFM4_INTREQ_IRQ004SEL_SELBIT6             *((volatile  uint8_t *)(0x426222D8UL))
#define bFM_INTREQ_IRQ004SEL_SELBIT7              *((volatile  uint8_t *)(0x426222DCUL))
#define bFM4_INTREQ_IRQ004SEL_SELBIT7             *((volatile  uint8_t *)(0x426222DCUL))
#define bFM_INTREQ_IRQ004SEL_SELBIT8              *((volatile  uint8_t *)(0x426222E0UL))
#define bFM4_INTREQ_IRQ004SEL_SELBIT8             *((volatile  uint8_t *)(0x426222E0UL))
#define bFM_INTREQ_IRQ004SEL_SELBIT9              *((volatile  uint8_t *)(0x426222E4UL))
#define bFM4_INTREQ_IRQ004SEL_SELBIT9             *((volatile  uint8_t *)(0x426222E4UL))
#define bFM_INTREQ_IRQ004SEL_SELBIT10             *((volatile  uint8_t *)(0x426222E8UL))
#define bFM4_INTREQ_IRQ004SEL_SELBIT10            *((volatile  uint8_t *)(0x426222E8UL))
#define bFM_INTREQ_IRQ004SEL_SELBIT11             *((volatile  uint8_t *)(0x426222ECUL))
#define bFM4_INTREQ_IRQ004SEL_SELBIT11            *((volatile  uint8_t *)(0x426222ECUL))
#define bFM_INTREQ_IRQ004SEL_SELBIT12             *((volatile  uint8_t *)(0x426222F0UL))
#define bFM4_INTREQ_IRQ004SEL_SELBIT12            *((volatile  uint8_t *)(0x426222F0UL))
#define bFM_INTREQ_IRQ004SEL_SELBIT13             *((volatile  uint8_t *)(0x426222F4UL))
#define bFM4_INTREQ_IRQ004SEL_SELBIT13            *((volatile  uint8_t *)(0x426222F4UL))
#define bFM_INTREQ_IRQ004SEL_SELBIT14             *((volatile  uint8_t *)(0x426222F8UL))
#define bFM4_INTREQ_IRQ004SEL_SELBIT14            *((volatile  uint8_t *)(0x426222F8UL))
#define bFM_INTREQ_IRQ004SEL_SELBIT15             *((volatile  uint8_t *)(0x426222FCUL))
#define bFM4_INTREQ_IRQ004SEL_SELBIT15            *((volatile  uint8_t *)(0x426222FCUL))

#define bFM_INTREQ_IRQ005MON_IRQBIT0              *((volatile  uint8_t *)(0x42624300UL))
#define bFM4_INTREQ_IRQ005MON_IRQBIT0             *((volatile  uint8_t *)(0x42624300UL))
#define bFM_INTREQ_IRQ005MON_IRQBIT1              *((volatile  uint8_t *)(0x42624304UL))
#define bFM4_INTREQ_IRQ005MON_IRQBIT1             *((volatile  uint8_t *)(0x42624304UL))
#define bFM_INTREQ_IRQ005MON_IRQBIT2              *((volatile  uint8_t *)(0x42624308UL))
#define bFM4_INTREQ_IRQ005MON_IRQBIT2             *((volatile  uint8_t *)(0x42624308UL))
#define bFM_INTREQ_IRQ005MON_IRQBIT3              *((volatile  uint8_t *)(0x4262430CUL))
#define bFM4_INTREQ_IRQ005MON_IRQBIT3             *((volatile  uint8_t *)(0x4262430CUL))
#define bFM_INTREQ_IRQ005MON_IRQBIT4              *((volatile  uint8_t *)(0x42624310UL))
#define bFM4_INTREQ_IRQ005MON_IRQBIT4             *((volatile  uint8_t *)(0x42624310UL))
#define bFM_INTREQ_IRQ005MON_IRQBIT5              *((volatile  uint8_t *)(0x42624314UL))
#define bFM4_INTREQ_IRQ005MON_IRQBIT5             *((volatile  uint8_t *)(0x42624314UL))
#define bFM_INTREQ_IRQ005MON_IRQBIT6              *((volatile  uint8_t *)(0x42624318UL))
#define bFM4_INTREQ_IRQ005MON_IRQBIT6             *((volatile  uint8_t *)(0x42624318UL))
#define bFM_INTREQ_IRQ005MON_IRQBIT7              *((volatile  uint8_t *)(0x4262431CUL))
#define bFM4_INTREQ_IRQ005MON_IRQBIT7             *((volatile  uint8_t *)(0x4262431CUL))

#define bFM_INTREQ_IRQ005SEL_SELBIT0              *((volatile  uint8_t *)(0x42622340UL))
#define bFM4_INTREQ_IRQ005SEL_SELBIT0             *((volatile  uint8_t *)(0x42622340UL))
#define bFM_INTREQ_IRQ005SEL_SELBIT1              *((volatile  uint8_t *)(0x42622344UL))
#define bFM4_INTREQ_IRQ005SEL_SELBIT1             *((volatile  uint8_t *)(0x42622344UL))
#define bFM_INTREQ_IRQ005SEL_SELBIT2              *((volatile  uint8_t *)(0x42622348UL))
#define bFM4_INTREQ_IRQ005SEL_SELBIT2             *((volatile  uint8_t *)(0x42622348UL))
#define bFM_INTREQ_IRQ005SEL_SELBIT3              *((volatile  uint8_t *)(0x4262234CUL))
#define bFM4_INTREQ_IRQ005SEL_SELBIT3             *((volatile  uint8_t *)(0x4262234CUL))
#define bFM_INTREQ_IRQ005SEL_SELBIT4              *((volatile  uint8_t *)(0x42622350UL))
#define bFM4_INTREQ_IRQ005SEL_SELBIT4             *((volatile  uint8_t *)(0x42622350UL))
#define bFM_INTREQ_IRQ005SEL_SELBIT5              *((volatile  uint8_t *)(0x42622354UL))
#define bFM4_INTREQ_IRQ005SEL_SELBIT5             *((volatile  uint8_t *)(0x42622354UL))
#define bFM_INTREQ_IRQ005SEL_SELBIT6              *((volatile  uint8_t *)(0x42622358UL))
#define bFM4_INTREQ_IRQ005SEL_SELBIT6             *((volatile  uint8_t *)(0x42622358UL))
#define bFM_INTREQ_IRQ005SEL_SELBIT7              *((volatile  uint8_t *)(0x4262235CUL))
#define bFM4_INTREQ_IRQ005SEL_SELBIT7             *((volatile  uint8_t *)(0x4262235CUL))
#define bFM_INTREQ_IRQ005SEL_SELBIT8              *((volatile  uint8_t *)(0x42622360UL))
#define bFM4_INTREQ_IRQ005SEL_SELBIT8             *((volatile  uint8_t *)(0x42622360UL))
#define bFM_INTREQ_IRQ005SEL_SELBIT9              *((volatile  uint8_t *)(0x42622364UL))
#define bFM4_INTREQ_IRQ005SEL_SELBIT9             *((volatile  uint8_t *)(0x42622364UL))
#define bFM_INTREQ_IRQ005SEL_SELBIT10             *((volatile  uint8_t *)(0x42622368UL))
#define bFM4_INTREQ_IRQ005SEL_SELBIT10            *((volatile  uint8_t *)(0x42622368UL))
#define bFM_INTREQ_IRQ005SEL_SELBIT11             *((volatile  uint8_t *)(0x4262236CUL))
#define bFM4_INTREQ_IRQ005SEL_SELBIT11            *((volatile  uint8_t *)(0x4262236CUL))
#define bFM_INTREQ_IRQ005SEL_SELBIT12             *((volatile  uint8_t *)(0x42622370UL))
#define bFM4_INTREQ_IRQ005SEL_SELBIT12            *((volatile  uint8_t *)(0x42622370UL))
#define bFM_INTREQ_IRQ005SEL_SELBIT13             *((volatile  uint8_t *)(0x42622374UL))
#define bFM4_INTREQ_IRQ005SEL_SELBIT13            *((volatile  uint8_t *)(0x42622374UL))
#define bFM_INTREQ_IRQ005SEL_SELBIT14             *((volatile  uint8_t *)(0x42622378UL))
#define bFM4_INTREQ_IRQ005SEL_SELBIT14            *((volatile  uint8_t *)(0x42622378UL))
#define bFM_INTREQ_IRQ005SEL_SELBIT15             *((volatile  uint8_t *)(0x4262237CUL))
#define bFM4_INTREQ_IRQ005SEL_SELBIT15            *((volatile  uint8_t *)(0x4262237CUL))

#define bFM_INTREQ_IRQ006MON_IRQBIT0              *((volatile  uint8_t *)(0x42624380UL))
#define bFM4_INTREQ_IRQ006MON_IRQBIT0             *((volatile  uint8_t *)(0x42624380UL))
#define bFM_INTREQ_IRQ006MON_IRQBIT1              *((volatile  uint8_t *)(0x42624384UL))
#define bFM4_INTREQ_IRQ006MON_IRQBIT1             *((volatile  uint8_t *)(0x42624384UL))
#define bFM_INTREQ_IRQ006MON_IRQBIT2              *((volatile  uint8_t *)(0x42624388UL))
#define bFM4_INTREQ_IRQ006MON_IRQBIT2             *((volatile  uint8_t *)(0x42624388UL))
#define bFM_INTREQ_IRQ006MON_IRQBIT3              *((volatile  uint8_t *)(0x4262438CUL))
#define bFM4_INTREQ_IRQ006MON_IRQBIT3             *((volatile  uint8_t *)(0x4262438CUL))
#define bFM_INTREQ_IRQ006MON_IRQBIT4              *((volatile  uint8_t *)(0x42624390UL))
#define bFM4_INTREQ_IRQ006MON_IRQBIT4             *((volatile  uint8_t *)(0x42624390UL))
#define bFM_INTREQ_IRQ006MON_IRQBIT5              *((volatile  uint8_t *)(0x42624394UL))
#define bFM4_INTREQ_IRQ006MON_IRQBIT5             *((volatile  uint8_t *)(0x42624394UL))
#define bFM_INTREQ_IRQ006MON_IRQBIT6              *((volatile  uint8_t *)(0x42624398UL))
#define bFM4_INTREQ_IRQ006MON_IRQBIT6             *((volatile  uint8_t *)(0x42624398UL))
#define bFM_INTREQ_IRQ006MON_IRQBIT7              *((volatile  uint8_t *)(0x4262439CUL))
#define bFM4_INTREQ_IRQ006MON_IRQBIT7             *((volatile  uint8_t *)(0x4262439CUL))

#define bFM_INTREQ_IRQ006SEL_SELBIT0              *((volatile  uint8_t *)(0x426223C0UL))
#define bFM4_INTREQ_IRQ006SEL_SELBIT0             *((volatile  uint8_t *)(0x426223C0UL))
#define bFM_INTREQ_IRQ006SEL_SELBIT1              *((volatile  uint8_t *)(0x426223C4UL))
#define bFM4_INTREQ_IRQ006SEL_SELBIT1             *((volatile  uint8_t *)(0x426223C4UL))
#define bFM_INTREQ_IRQ006SEL_SELBIT2              *((volatile  uint8_t *)(0x426223C8UL))
#define bFM4_INTREQ_IRQ006SEL_SELBIT2             *((volatile  uint8_t *)(0x426223C8UL))
#define bFM_INTREQ_IRQ006SEL_SELBIT3              *((volatile  uint8_t *)(0x426223CCUL))
#define bFM4_INTREQ_IRQ006SEL_SELBIT3             *((volatile  uint8_t *)(0x426223CCUL))
#define bFM_INTREQ_IRQ006SEL_SELBIT4              *((volatile  uint8_t *)(0x426223D0UL))
#define bFM4_INTREQ_IRQ006SEL_SELBIT4             *((volatile  uint8_t *)(0x426223D0UL))
#define bFM_INTREQ_IRQ006SEL_SELBIT5              *((volatile  uint8_t *)(0x426223D4UL))
#define bFM4_INTREQ_IRQ006SEL_SELBIT5             *((volatile  uint8_t *)(0x426223D4UL))
#define bFM_INTREQ_IRQ006SEL_SELBIT6              *((volatile  uint8_t *)(0x426223D8UL))
#define bFM4_INTREQ_IRQ006SEL_SELBIT6             *((volatile  uint8_t *)(0x426223D8UL))
#define bFM_INTREQ_IRQ006SEL_SELBIT7              *((volatile  uint8_t *)(0x426223DCUL))
#define bFM4_INTREQ_IRQ006SEL_SELBIT7             *((volatile  uint8_t *)(0x426223DCUL))
#define bFM_INTREQ_IRQ006SEL_SELBIT8              *((volatile  uint8_t *)(0x426223E0UL))
#define bFM4_INTREQ_IRQ006SEL_SELBIT8             *((volatile  uint8_t *)(0x426223E0UL))
#define bFM_INTREQ_IRQ006SEL_SELBIT9              *((volatile  uint8_t *)(0x426223E4UL))
#define bFM4_INTREQ_IRQ006SEL_SELBIT9             *((volatile  uint8_t *)(0x426223E4UL))
#define bFM_INTREQ_IRQ006SEL_SELBIT10             *((volatile  uint8_t *)(0x426223E8UL))
#define bFM4_INTREQ_IRQ006SEL_SELBIT10            *((volatile  uint8_t *)(0x426223E8UL))
#define bFM_INTREQ_IRQ006SEL_SELBIT11             *((volatile  uint8_t *)(0x426223ECUL))
#define bFM4_INTREQ_IRQ006SEL_SELBIT11            *((volatile  uint8_t *)(0x426223ECUL))
#define bFM_INTREQ_IRQ006SEL_SELBIT12             *((volatile  uint8_t *)(0x426223F0UL))
#define bFM4_INTREQ_IRQ006SEL_SELBIT12            *((volatile  uint8_t *)(0x426223F0UL))
#define bFM_INTREQ_IRQ006SEL_SELBIT13             *((volatile  uint8_t *)(0x426223F4UL))
#define bFM4_INTREQ_IRQ006SEL_SELBIT13            *((volatile  uint8_t *)(0x426223F4UL))
#define bFM_INTREQ_IRQ006SEL_SELBIT14             *((volatile  uint8_t *)(0x426223F8UL))
#define bFM4_INTREQ_IRQ006SEL_SELBIT14            *((volatile  uint8_t *)(0x426223F8UL))
#define bFM_INTREQ_IRQ006SEL_SELBIT15             *((volatile  uint8_t *)(0x426223FCUL))
#define bFM4_INTREQ_IRQ006SEL_SELBIT15            *((volatile  uint8_t *)(0x426223FCUL))

#define bFM_INTREQ_IRQ007MON_IRQBIT0              *((volatile  uint8_t *)(0x42624400UL))
#define bFM4_INTREQ_IRQ007MON_IRQBIT0             *((volatile  uint8_t *)(0x42624400UL))
#define bFM_INTREQ_IRQ007MON_IRQBIT1              *((volatile  uint8_t *)(0x42624404UL))
#define bFM4_INTREQ_IRQ007MON_IRQBIT1             *((volatile  uint8_t *)(0x42624404UL))
#define bFM_INTREQ_IRQ007MON_IRQBIT2              *((volatile  uint8_t *)(0x42624408UL))
#define bFM4_INTREQ_IRQ007MON_IRQBIT2             *((volatile  uint8_t *)(0x42624408UL))
#define bFM_INTREQ_IRQ007MON_IRQBIT3              *((volatile  uint8_t *)(0x4262440CUL))
#define bFM4_INTREQ_IRQ007MON_IRQBIT3             *((volatile  uint8_t *)(0x4262440CUL))
#define bFM_INTREQ_IRQ007MON_IRQBIT4              *((volatile  uint8_t *)(0x42624410UL))
#define bFM4_INTREQ_IRQ007MON_IRQBIT4             *((volatile  uint8_t *)(0x42624410UL))
#define bFM_INTREQ_IRQ007MON_IRQBIT5              *((volatile  uint8_t *)(0x42624414UL))
#define bFM4_INTREQ_IRQ007MON_IRQBIT5             *((volatile  uint8_t *)(0x42624414UL))
#define bFM_INTREQ_IRQ007MON_IRQBIT6              *((volatile  uint8_t *)(0x42624418UL))
#define bFM4_INTREQ_IRQ007MON_IRQBIT6             *((volatile  uint8_t *)(0x42624418UL))
#define bFM_INTREQ_IRQ007MON_IRQBIT7              *((volatile  uint8_t *)(0x4262441CUL))
#define bFM4_INTREQ_IRQ007MON_IRQBIT7             *((volatile  uint8_t *)(0x4262441CUL))

#define bFM_INTREQ_IRQ007SEL_SELBIT0              *((volatile  uint8_t *)(0x42622440UL))
#define bFM4_INTREQ_IRQ007SEL_SELBIT0             *((volatile  uint8_t *)(0x42622440UL))
#define bFM_INTREQ_IRQ007SEL_SELBIT1              *((volatile  uint8_t *)(0x42622444UL))
#define bFM4_INTREQ_IRQ007SEL_SELBIT1             *((volatile  uint8_t *)(0x42622444UL))
#define bFM_INTREQ_IRQ007SEL_SELBIT2              *((volatile  uint8_t *)(0x42622448UL))
#define bFM4_INTREQ_IRQ007SEL_SELBIT2             *((volatile  uint8_t *)(0x42622448UL))
#define bFM_INTREQ_IRQ007SEL_SELBIT3              *((volatile  uint8_t *)(0x4262244CUL))
#define bFM4_INTREQ_IRQ007SEL_SELBIT3             *((volatile  uint8_t *)(0x4262244CUL))
#define bFM_INTREQ_IRQ007SEL_SELBIT4              *((volatile  uint8_t *)(0x42622450UL))
#define bFM4_INTREQ_IRQ007SEL_SELBIT4             *((volatile  uint8_t *)(0x42622450UL))
#define bFM_INTREQ_IRQ007SEL_SELBIT5              *((volatile  uint8_t *)(0x42622454UL))
#define bFM4_INTREQ_IRQ007SEL_SELBIT5             *((volatile  uint8_t *)(0x42622454UL))
#define bFM_INTREQ_IRQ007SEL_SELBIT6              *((volatile  uint8_t *)(0x42622458UL))
#define bFM4_INTREQ_IRQ007SEL_SELBIT6             *((volatile  uint8_t *)(0x42622458UL))
#define bFM_INTREQ_IRQ007SEL_SELBIT7              *((volatile  uint8_t *)(0x4262245CUL))
#define bFM4_INTREQ_IRQ007SEL_SELBIT7             *((volatile  uint8_t *)(0x4262245CUL))
#define bFM_INTREQ_IRQ007SEL_SELBIT8              *((volatile  uint8_t *)(0x42622460UL))
#define bFM4_INTREQ_IRQ007SEL_SELBIT8             *((volatile  uint8_t *)(0x42622460UL))
#define bFM_INTREQ_IRQ007SEL_SELBIT9              *((volatile  uint8_t *)(0x42622464UL))
#define bFM4_INTREQ_IRQ007SEL_SELBIT9             *((volatile  uint8_t *)(0x42622464UL))
#define bFM_INTREQ_IRQ007SEL_SELBIT10             *((volatile  uint8_t *)(0x42622468UL))
#define bFM4_INTREQ_IRQ007SEL_SELBIT10            *((volatile  uint8_t *)(0x42622468UL))
#define bFM_INTREQ_IRQ007SEL_SELBIT11             *((volatile  uint8_t *)(0x4262246CUL))
#define bFM4_INTREQ_IRQ007SEL_SELBIT11            *((volatile  uint8_t *)(0x4262246CUL))
#define bFM_INTREQ_IRQ007SEL_SELBIT12             *((volatile  uint8_t *)(0x42622470UL))
#define bFM4_INTREQ_IRQ007SEL_SELBIT12            *((volatile  uint8_t *)(0x42622470UL))
#define bFM_INTREQ_IRQ007SEL_SELBIT13             *((volatile  uint8_t *)(0x42622474UL))
#define bFM4_INTREQ_IRQ007SEL_SELBIT13            *((volatile  uint8_t *)(0x42622474UL))
#define bFM_INTREQ_IRQ007SEL_SELBIT14             *((volatile  uint8_t *)(0x42622478UL))
#define bFM4_INTREQ_IRQ007SEL_SELBIT14            *((volatile  uint8_t *)(0x42622478UL))
#define bFM_INTREQ_IRQ007SEL_SELBIT15             *((volatile  uint8_t *)(0x4262247CUL))
#define bFM4_INTREQ_IRQ007SEL_SELBIT15            *((volatile  uint8_t *)(0x4262247CUL))

#define bFM_INTREQ_IRQ008MON_IRQBIT0              *((volatile  uint8_t *)(0x42624480UL))
#define bFM4_INTREQ_IRQ008MON_IRQBIT0             *((volatile  uint8_t *)(0x42624480UL))
#define bFM_INTREQ_IRQ008MON_IRQBIT1              *((volatile  uint8_t *)(0x42624484UL))
#define bFM4_INTREQ_IRQ008MON_IRQBIT1             *((volatile  uint8_t *)(0x42624484UL))
#define bFM_INTREQ_IRQ008MON_IRQBIT2              *((volatile  uint8_t *)(0x42624488UL))
#define bFM4_INTREQ_IRQ008MON_IRQBIT2             *((volatile  uint8_t *)(0x42624488UL))
#define bFM_INTREQ_IRQ008MON_IRQBIT3              *((volatile  uint8_t *)(0x4262448CUL))
#define bFM4_INTREQ_IRQ008MON_IRQBIT3             *((volatile  uint8_t *)(0x4262448CUL))
#define bFM_INTREQ_IRQ008MON_IRQBIT4              *((volatile  uint8_t *)(0x42624490UL))
#define bFM4_INTREQ_IRQ008MON_IRQBIT4             *((volatile  uint8_t *)(0x42624490UL))
#define bFM_INTREQ_IRQ008MON_IRQBIT5              *((volatile  uint8_t *)(0x42624494UL))
#define bFM4_INTREQ_IRQ008MON_IRQBIT5             *((volatile  uint8_t *)(0x42624494UL))
#define bFM_INTREQ_IRQ008MON_IRQBIT6              *((volatile  uint8_t *)(0x42624498UL))
#define bFM4_INTREQ_IRQ008MON_IRQBIT6             *((volatile  uint8_t *)(0x42624498UL))
#define bFM_INTREQ_IRQ008MON_IRQBIT7              *((volatile  uint8_t *)(0x4262449CUL))
#define bFM4_INTREQ_IRQ008MON_IRQBIT7             *((volatile  uint8_t *)(0x4262449CUL))

#define bFM_INTREQ_IRQ008SEL_SELBIT0              *((volatile  uint8_t *)(0x426224C0UL))
#define bFM4_INTREQ_IRQ008SEL_SELBIT0             *((volatile  uint8_t *)(0x426224C0UL))
#define bFM_INTREQ_IRQ008SEL_SELBIT1              *((volatile  uint8_t *)(0x426224C4UL))
#define bFM4_INTREQ_IRQ008SEL_SELBIT1             *((volatile  uint8_t *)(0x426224C4UL))
#define bFM_INTREQ_IRQ008SEL_SELBIT2              *((volatile  uint8_t *)(0x426224C8UL))
#define bFM4_INTREQ_IRQ008SEL_SELBIT2             *((volatile  uint8_t *)(0x426224C8UL))
#define bFM_INTREQ_IRQ008SEL_SELBIT3              *((volatile  uint8_t *)(0x426224CCUL))
#define bFM4_INTREQ_IRQ008SEL_SELBIT3             *((volatile  uint8_t *)(0x426224CCUL))
#define bFM_INTREQ_IRQ008SEL_SELBIT4              *((volatile  uint8_t *)(0x426224D0UL))
#define bFM4_INTREQ_IRQ008SEL_SELBIT4             *((volatile  uint8_t *)(0x426224D0UL))
#define bFM_INTREQ_IRQ008SEL_SELBIT5              *((volatile  uint8_t *)(0x426224D4UL))
#define bFM4_INTREQ_IRQ008SEL_SELBIT5             *((volatile  uint8_t *)(0x426224D4UL))
#define bFM_INTREQ_IRQ008SEL_SELBIT6              *((volatile  uint8_t *)(0x426224D8UL))
#define bFM4_INTREQ_IRQ008SEL_SELBIT6             *((volatile  uint8_t *)(0x426224D8UL))
#define bFM_INTREQ_IRQ008SEL_SELBIT7              *((volatile  uint8_t *)(0x426224DCUL))
#define bFM4_INTREQ_IRQ008SEL_SELBIT7             *((volatile  uint8_t *)(0x426224DCUL))
#define bFM_INTREQ_IRQ008SEL_SELBIT8              *((volatile  uint8_t *)(0x426224E0UL))
#define bFM4_INTREQ_IRQ008SEL_SELBIT8             *((volatile  uint8_t *)(0x426224E0UL))
#define bFM_INTREQ_IRQ008SEL_SELBIT9              *((volatile  uint8_t *)(0x426224E4UL))
#define bFM4_INTREQ_IRQ008SEL_SELBIT9             *((volatile  uint8_t *)(0x426224E4UL))
#define bFM_INTREQ_IRQ008SEL_SELBIT10             *((volatile  uint8_t *)(0x426224E8UL))
#define bFM4_INTREQ_IRQ008SEL_SELBIT10            *((volatile  uint8_t *)(0x426224E8UL))
#define bFM_INTREQ_IRQ008SEL_SELBIT11             *((volatile  uint8_t *)(0x426224ECUL))
#define bFM4_INTREQ_IRQ008SEL_SELBIT11            *((volatile  uint8_t *)(0x426224ECUL))
#define bFM_INTREQ_IRQ008SEL_SELBIT12             *((volatile  uint8_t *)(0x426224F0UL))
#define bFM4_INTREQ_IRQ008SEL_SELBIT12            *((volatile  uint8_t *)(0x426224F0UL))
#define bFM_INTREQ_IRQ008SEL_SELBIT13             *((volatile  uint8_t *)(0x426224F4UL))
#define bFM4_INTREQ_IRQ008SEL_SELBIT13            *((volatile  uint8_t *)(0x426224F4UL))
#define bFM_INTREQ_IRQ008SEL_SELBIT14             *((volatile  uint8_t *)(0x426224F8UL))
#define bFM4_INTREQ_IRQ008SEL_SELBIT14            *((volatile  uint8_t *)(0x426224F8UL))
#define bFM_INTREQ_IRQ008SEL_SELBIT15             *((volatile  uint8_t *)(0x426224FCUL))
#define bFM4_INTREQ_IRQ008SEL_SELBIT15            *((volatile  uint8_t *)(0x426224FCUL))

#define bFM_INTREQ_IRQ009MON_IRQBIT0              *((volatile  uint8_t *)(0x42624500UL))
#define bFM4_INTREQ_IRQ009MON_IRQBIT0             *((volatile  uint8_t *)(0x42624500UL))
#define bFM_INTREQ_IRQ009MON_IRQBIT1              *((volatile  uint8_t *)(0x42624504UL))
#define bFM4_INTREQ_IRQ009MON_IRQBIT1             *((volatile  uint8_t *)(0x42624504UL))
#define bFM_INTREQ_IRQ009MON_IRQBIT2              *((volatile  uint8_t *)(0x42624508UL))
#define bFM4_INTREQ_IRQ009MON_IRQBIT2             *((volatile  uint8_t *)(0x42624508UL))
#define bFM_INTREQ_IRQ009MON_IRQBIT3              *((volatile  uint8_t *)(0x4262450CUL))
#define bFM4_INTREQ_IRQ009MON_IRQBIT3             *((volatile  uint8_t *)(0x4262450CUL))
#define bFM_INTREQ_IRQ009MON_IRQBIT4              *((volatile  uint8_t *)(0x42624510UL))
#define bFM4_INTREQ_IRQ009MON_IRQBIT4             *((volatile  uint8_t *)(0x42624510UL))
#define bFM_INTREQ_IRQ009MON_IRQBIT5              *((volatile  uint8_t *)(0x42624514UL))
#define bFM4_INTREQ_IRQ009MON_IRQBIT5             *((volatile  uint8_t *)(0x42624514UL))
#define bFM_INTREQ_IRQ009MON_IRQBIT6              *((volatile  uint8_t *)(0x42624518UL))
#define bFM4_INTREQ_IRQ009MON_IRQBIT6             *((volatile  uint8_t *)(0x42624518UL))
#define bFM_INTREQ_IRQ009MON_IRQBIT7              *((volatile  uint8_t *)(0x4262451CUL))
#define bFM4_INTREQ_IRQ009MON_IRQBIT7             *((volatile  uint8_t *)(0x4262451CUL))

#define bFM_INTREQ_IRQ009SEL_SELBIT0              *((volatile  uint8_t *)(0x42622540UL))
#define bFM4_INTREQ_IRQ009SEL_SELBIT0             *((volatile  uint8_t *)(0x42622540UL))
#define bFM_INTREQ_IRQ009SEL_SELBIT1              *((volatile  uint8_t *)(0x42622544UL))
#define bFM4_INTREQ_IRQ009SEL_SELBIT1             *((volatile  uint8_t *)(0x42622544UL))
#define bFM_INTREQ_IRQ009SEL_SELBIT2              *((volatile  uint8_t *)(0x42622548UL))
#define bFM4_INTREQ_IRQ009SEL_SELBIT2             *((volatile  uint8_t *)(0x42622548UL))
#define bFM_INTREQ_IRQ009SEL_SELBIT3              *((volatile  uint8_t *)(0x4262254CUL))
#define bFM4_INTREQ_IRQ009SEL_SELBIT3             *((volatile  uint8_t *)(0x4262254CUL))
#define bFM_INTREQ_IRQ009SEL_SELBIT4              *((volatile  uint8_t *)(0x42622550UL))
#define bFM4_INTREQ_IRQ009SEL_SELBIT4             *((volatile  uint8_t *)(0x42622550UL))
#define bFM_INTREQ_IRQ009SEL_SELBIT5              *((volatile  uint8_t *)(0x42622554UL))
#define bFM4_INTREQ_IRQ009SEL_SELBIT5             *((volatile  uint8_t *)(0x42622554UL))
#define bFM_INTREQ_IRQ009SEL_SELBIT6              *((volatile  uint8_t *)(0x42622558UL))
#define bFM4_INTREQ_IRQ009SEL_SELBIT6             *((volatile  uint8_t *)(0x42622558UL))
#define bFM_INTREQ_IRQ009SEL_SELBIT7              *((volatile  uint8_t *)(0x4262255CUL))
#define bFM4_INTREQ_IRQ009SEL_SELBIT7             *((volatile  uint8_t *)(0x4262255CUL))
#define bFM_INTREQ_IRQ009SEL_SELBIT8              *((volatile  uint8_t *)(0x42622560UL))
#define bFM4_INTREQ_IRQ009SEL_SELBIT8             *((volatile  uint8_t *)(0x42622560UL))
#define bFM_INTREQ_IRQ009SEL_SELBIT9              *((volatile  uint8_t *)(0x42622564UL))
#define bFM4_INTREQ_IRQ009SEL_SELBIT9             *((volatile  uint8_t *)(0x42622564UL))
#define bFM_INTREQ_IRQ009SEL_SELBIT10             *((volatile  uint8_t *)(0x42622568UL))
#define bFM4_INTREQ_IRQ009SEL_SELBIT10            *((volatile  uint8_t *)(0x42622568UL))
#define bFM_INTREQ_IRQ009SEL_SELBIT11             *((volatile  uint8_t *)(0x4262256CUL))
#define bFM4_INTREQ_IRQ009SEL_SELBIT11            *((volatile  uint8_t *)(0x4262256CUL))
#define bFM_INTREQ_IRQ009SEL_SELBIT12             *((volatile  uint8_t *)(0x42622570UL))
#define bFM4_INTREQ_IRQ009SEL_SELBIT12            *((volatile  uint8_t *)(0x42622570UL))
#define bFM_INTREQ_IRQ009SEL_SELBIT13             *((volatile  uint8_t *)(0x42622574UL))
#define bFM4_INTREQ_IRQ009SEL_SELBIT13            *((volatile  uint8_t *)(0x42622574UL))
#define bFM_INTREQ_IRQ009SEL_SELBIT14             *((volatile  uint8_t *)(0x42622578UL))
#define bFM4_INTREQ_IRQ009SEL_SELBIT14            *((volatile  uint8_t *)(0x42622578UL))
#define bFM_INTREQ_IRQ009SEL_SELBIT15             *((volatile  uint8_t *)(0x4262257CUL))
#define bFM4_INTREQ_IRQ009SEL_SELBIT15            *((volatile  uint8_t *)(0x4262257CUL))

#define bFM_INTREQ_IRQ010MON_IRQBIT0              *((volatile  uint8_t *)(0x42624580UL))
#define bFM4_INTREQ_IRQ010MON_IRQBIT0             *((volatile  uint8_t *)(0x42624580UL))
#define bFM_INTREQ_IRQ010MON_IRQBIT1              *((volatile  uint8_t *)(0x42624584UL))
#define bFM4_INTREQ_IRQ010MON_IRQBIT1             *((volatile  uint8_t *)(0x42624584UL))
#define bFM_INTREQ_IRQ010MON_IRQBIT2              *((volatile  uint8_t *)(0x42624588UL))
#define bFM4_INTREQ_IRQ010MON_IRQBIT2             *((volatile  uint8_t *)(0x42624588UL))
#define bFM_INTREQ_IRQ010MON_IRQBIT3              *((volatile  uint8_t *)(0x4262458CUL))
#define bFM4_INTREQ_IRQ010MON_IRQBIT3             *((volatile  uint8_t *)(0x4262458CUL))
#define bFM_INTREQ_IRQ010MON_IRQBIT4              *((volatile  uint8_t *)(0x42624590UL))
#define bFM4_INTREQ_IRQ010MON_IRQBIT4             *((volatile  uint8_t *)(0x42624590UL))
#define bFM_INTREQ_IRQ010MON_IRQBIT5              *((volatile  uint8_t *)(0x42624594UL))
#define bFM4_INTREQ_IRQ010MON_IRQBIT5             *((volatile  uint8_t *)(0x42624594UL))
#define bFM_INTREQ_IRQ010MON_IRQBIT6              *((volatile  uint8_t *)(0x42624598UL))
#define bFM4_INTREQ_IRQ010MON_IRQBIT6             *((volatile  uint8_t *)(0x42624598UL))
#define bFM_INTREQ_IRQ010MON_IRQBIT7              *((volatile  uint8_t *)(0x4262459CUL))
#define bFM4_INTREQ_IRQ010MON_IRQBIT7             *((volatile  uint8_t *)(0x4262459CUL))

#define bFM_INTREQ_IRQ010SEL_SELBIT0              *((volatile  uint8_t *)(0x426225C0UL))
#define bFM4_INTREQ_IRQ010SEL_SELBIT0             *((volatile  uint8_t *)(0x426225C0UL))
#define bFM_INTREQ_IRQ010SEL_SELBIT1              *((volatile  uint8_t *)(0x426225C4UL))
#define bFM4_INTREQ_IRQ010SEL_SELBIT1             *((volatile  uint8_t *)(0x426225C4UL))
#define bFM_INTREQ_IRQ010SEL_SELBIT2              *((volatile  uint8_t *)(0x426225C8UL))
#define bFM4_INTREQ_IRQ010SEL_SELBIT2             *((volatile  uint8_t *)(0x426225C8UL))
#define bFM_INTREQ_IRQ010SEL_SELBIT3              *((volatile  uint8_t *)(0x426225CCUL))
#define bFM4_INTREQ_IRQ010SEL_SELBIT3             *((volatile  uint8_t *)(0x426225CCUL))
#define bFM_INTREQ_IRQ010SEL_SELBIT4              *((volatile  uint8_t *)(0x426225D0UL))
#define bFM4_INTREQ_IRQ010SEL_SELBIT4             *((volatile  uint8_t *)(0x426225D0UL))
#define bFM_INTREQ_IRQ010SEL_SELBIT5              *((volatile  uint8_t *)(0x426225D4UL))
#define bFM4_INTREQ_IRQ010SEL_SELBIT5             *((volatile  uint8_t *)(0x426225D4UL))
#define bFM_INTREQ_IRQ010SEL_SELBIT6              *((volatile  uint8_t *)(0x426225D8UL))
#define bFM4_INTREQ_IRQ010SEL_SELBIT6             *((volatile  uint8_t *)(0x426225D8UL))
#define bFM_INTREQ_IRQ010SEL_SELBIT7              *((volatile  uint8_t *)(0x426225DCUL))
#define bFM4_INTREQ_IRQ010SEL_SELBIT7             *((volatile  uint8_t *)(0x426225DCUL))
#define bFM_INTREQ_IRQ010SEL_SELBIT8              *((volatile  uint8_t *)(0x426225E0UL))
#define bFM4_INTREQ_IRQ010SEL_SELBIT8             *((volatile  uint8_t *)(0x426225E0UL))
#define bFM_INTREQ_IRQ010SEL_SELBIT9              *((volatile  uint8_t *)(0x426225E4UL))
#define bFM4_INTREQ_IRQ010SEL_SELBIT9             *((volatile  uint8_t *)(0x426225E4UL))
#define bFM_INTREQ_IRQ010SEL_SELBIT10             *((volatile  uint8_t *)(0x426225E8UL))
#define bFM4_INTREQ_IRQ010SEL_SELBIT10            *((volatile  uint8_t *)(0x426225E8UL))
#define bFM_INTREQ_IRQ010SEL_SELBIT11             *((volatile  uint8_t *)(0x426225ECUL))
#define bFM4_INTREQ_IRQ010SEL_SELBIT11            *((volatile  uint8_t *)(0x426225ECUL))
#define bFM_INTREQ_IRQ010SEL_SELBIT12             *((volatile  uint8_t *)(0x426225F0UL))
#define bFM4_INTREQ_IRQ010SEL_SELBIT12            *((volatile  uint8_t *)(0x426225F0UL))
#define bFM_INTREQ_IRQ010SEL_SELBIT13             *((volatile  uint8_t *)(0x426225F4UL))
#define bFM4_INTREQ_IRQ010SEL_SELBIT13            *((volatile  uint8_t *)(0x426225F4UL))
#define bFM_INTREQ_IRQ010SEL_SELBIT14             *((volatile  uint8_t *)(0x426225F8UL))
#define bFM4_INTREQ_IRQ010SEL_SELBIT14            *((volatile  uint8_t *)(0x426225F8UL))
#define bFM_INTREQ_IRQ010SEL_SELBIT15             *((volatile  uint8_t *)(0x426225FCUL))
#define bFM4_INTREQ_IRQ010SEL_SELBIT15            *((volatile  uint8_t *)(0x426225FCUL))

#define bFM_INTREQ_IRQ011MON_EXTINT               *((volatile  uint8_t *)(0x42624600UL))
#define bFM4_INTREQ_IRQ011MON_EXTINT              *((volatile  uint8_t *)(0x42624600UL))

#define bFM_INTREQ_IRQ012MON_EXTINT               *((volatile  uint8_t *)(0x42624680UL))
#define bFM4_INTREQ_IRQ012MON_EXTINT              *((volatile  uint8_t *)(0x42624680UL))

#define bFM_INTREQ_IRQ013MON_EXTINT               *((volatile  uint8_t *)(0x42624700UL))
#define bFM4_INTREQ_IRQ013MON_EXTINT              *((volatile  uint8_t *)(0x42624700UL))

#define bFM_INTREQ_IRQ014MON_EXTINT               *((volatile  uint8_t *)(0x42624780UL))
#define bFM4_INTREQ_IRQ014MON_EXTINT              *((volatile  uint8_t *)(0x42624780UL))

#define bFM_INTREQ_IRQ015MON_EXTINT               *((volatile  uint8_t *)(0x42624800UL))
#define bFM4_INTREQ_IRQ015MON_EXTINT              *((volatile  uint8_t *)(0x42624800UL))

#define bFM_INTREQ_IRQ016MON_EXTINT               *((volatile  uint8_t *)(0x42624880UL))
#define bFM4_INTREQ_IRQ016MON_EXTINT              *((volatile  uint8_t *)(0x42624880UL))

#define bFM_INTREQ_IRQ017MON_EXTINT               *((volatile  uint8_t *)(0x42624900UL))
#define bFM4_INTREQ_IRQ017MON_EXTINT              *((volatile  uint8_t *)(0x42624900UL))

#define bFM_INTREQ_IRQ018MON_EXTINT               *((volatile  uint8_t *)(0x42624980UL))
#define bFM4_INTREQ_IRQ018MON_EXTINT              *((volatile  uint8_t *)(0x42624980UL))

#define bFM_INTREQ_IRQ019MON_QPRCINT0             *((volatile  uint8_t *)(0x42624A00UL))
#define bFM4_INTREQ_IRQ019MON_QPRCINT0            *((volatile  uint8_t *)(0x42624A00UL))
#define bFM_INTREQ_IRQ019MON_QPRCINT1             *((volatile  uint8_t *)(0x42624A04UL))
#define bFM4_INTREQ_IRQ019MON_QPRCINT1            *((volatile  uint8_t *)(0x42624A04UL))
#define bFM_INTREQ_IRQ019MON_QPRCINT2             *((volatile  uint8_t *)(0x42624A08UL))
#define bFM4_INTREQ_IRQ019MON_QPRCINT2            *((volatile  uint8_t *)(0x42624A08UL))
#define bFM_INTREQ_IRQ019MON_QPRCINT3             *((volatile  uint8_t *)(0x42624A0CUL))
#define bFM4_INTREQ_IRQ019MON_QPRCINT3            *((volatile  uint8_t *)(0x42624A0CUL))
#define bFM_INTREQ_IRQ019MON_QPRCINT4             *((volatile  uint8_t *)(0x42624A10UL))
#define bFM4_INTREQ_IRQ019MON_QPRCINT4            *((volatile  uint8_t *)(0x42624A10UL))
#define bFM_INTREQ_IRQ019MON_QPRCINT5             *((volatile  uint8_t *)(0x42624A14UL))
#define bFM4_INTREQ_IRQ019MON_QPRCINT5            *((volatile  uint8_t *)(0x42624A14UL))

#define bFM_INTREQ_IRQ020MON_QPRCINT0             *((volatile  uint8_t *)(0x42624A80UL))
#define bFM4_INTREQ_IRQ020MON_QPRCINT0            *((volatile  uint8_t *)(0x42624A80UL))
#define bFM_INTREQ_IRQ020MON_QPRCINT1             *((volatile  uint8_t *)(0x42624A84UL))
#define bFM4_INTREQ_IRQ020MON_QPRCINT1            *((volatile  uint8_t *)(0x42624A84UL))
#define bFM_INTREQ_IRQ020MON_QPRCINT2             *((volatile  uint8_t *)(0x42624A88UL))
#define bFM4_INTREQ_IRQ020MON_QPRCINT2            *((volatile  uint8_t *)(0x42624A88UL))
#define bFM_INTREQ_IRQ020MON_QPRCINT3             *((volatile  uint8_t *)(0x42624A8CUL))
#define bFM4_INTREQ_IRQ020MON_QPRCINT3            *((volatile  uint8_t *)(0x42624A8CUL))
#define bFM_INTREQ_IRQ020MON_QPRCINT4             *((volatile  uint8_t *)(0x42624A90UL))
#define bFM4_INTREQ_IRQ020MON_QPRCINT4            *((volatile  uint8_t *)(0x42624A90UL))
#define bFM_INTREQ_IRQ020MON_QPRCINT5             *((volatile  uint8_t *)(0x42624A94UL))
#define bFM4_INTREQ_IRQ020MON_QPRCINT5            *((volatile  uint8_t *)(0x42624A94UL))

#define bFM_INTREQ_IRQ021MON_WAVEINT0             *((volatile  uint8_t *)(0x42624B00UL))
#define bFM4_INTREQ_IRQ021MON_WAVEINT0            *((volatile  uint8_t *)(0x42624B00UL))
#define bFM_INTREQ_IRQ021MON_WAVEINT1             *((volatile  uint8_t *)(0x42624B04UL))
#define bFM4_INTREQ_IRQ021MON_WAVEINT1            *((volatile  uint8_t *)(0x42624B04UL))
#define bFM_INTREQ_IRQ021MON_WAVEINT2             *((volatile  uint8_t *)(0x42624B08UL))
#define bFM4_INTREQ_IRQ021MON_WAVEINT2            *((volatile  uint8_t *)(0x42624B08UL))
#define bFM_INTREQ_IRQ021MON_WAVEINT3             *((volatile  uint8_t *)(0x42624B0CUL))
#define bFM4_INTREQ_IRQ021MON_WAVEINT3            *((volatile  uint8_t *)(0x42624B0CUL))

#define bFM_INTREQ_IRQ022MON_WAVEINT0             *((volatile  uint8_t *)(0x42624B80UL))
#define bFM4_INTREQ_IRQ022MON_WAVEINT0            *((volatile  uint8_t *)(0x42624B80UL))
#define bFM_INTREQ_IRQ022MON_WAVEINT1             *((volatile  uint8_t *)(0x42624B84UL))
#define bFM4_INTREQ_IRQ022MON_WAVEINT1            *((volatile  uint8_t *)(0x42624B84UL))
#define bFM_INTREQ_IRQ022MON_WAVEINT2             *((volatile  uint8_t *)(0x42624B88UL))
#define bFM4_INTREQ_IRQ022MON_WAVEINT2            *((volatile  uint8_t *)(0x42624B88UL))
#define bFM_INTREQ_IRQ022MON_WAVEINT3             *((volatile  uint8_t *)(0x42624B8CUL))
#define bFM4_INTREQ_IRQ022MON_WAVEINT3            *((volatile  uint8_t *)(0x42624B8CUL))

#define bFM_INTREQ_IRQ023MON_WAVEINT0             *((volatile  uint8_t *)(0x42624C00UL))
#define bFM4_INTREQ_IRQ023MON_WAVEINT0            *((volatile  uint8_t *)(0x42624C00UL))
#define bFM_INTREQ_IRQ023MON_WAVEINT1             *((volatile  uint8_t *)(0x42624C04UL))
#define bFM4_INTREQ_IRQ023MON_WAVEINT1            *((volatile  uint8_t *)(0x42624C04UL))
#define bFM_INTREQ_IRQ023MON_WAVEINT2             *((volatile  uint8_t *)(0x42624C08UL))
#define bFM4_INTREQ_IRQ023MON_WAVEINT2            *((volatile  uint8_t *)(0x42624C08UL))
#define bFM_INTREQ_IRQ023MON_WAVEINT3             *((volatile  uint8_t *)(0x42624C0CUL))
#define bFM4_INTREQ_IRQ023MON_WAVEINT3            *((volatile  uint8_t *)(0x42624C0CUL))

#define bFM_INTREQ_IRQ024MON_FRT_PEAK_INT0        *((volatile  uint8_t *)(0x42624C80UL))
#define bFM4_INTREQ_IRQ024MON_FRT_PEAK_INT0       *((volatile  uint8_t *)(0x42624C80UL))
#define bFM_INTREQ_IRQ024MON_FRT_PEAK_INT1        *((volatile  uint8_t *)(0x42624C84UL))
#define bFM4_INTREQ_IRQ024MON_FRT_PEAK_INT1       *((volatile  uint8_t *)(0x42624C84UL))
#define bFM_INTREQ_IRQ024MON_FRT_PEAK_INT2        *((volatile  uint8_t *)(0x42624C88UL))
#define bFM4_INTREQ_IRQ024MON_FRT_PEAK_INT2       *((volatile  uint8_t *)(0x42624C88UL))

#define bFM_INTREQ_IRQ025MON_FRT_ZERO_INT0        *((volatile  uint8_t *)(0x42624D00UL))
#define bFM4_INTREQ_IRQ025MON_FRT_ZERO_INT0       *((volatile  uint8_t *)(0x42624D00UL))
#define bFM_INTREQ_IRQ025MON_FRT_ZERO_INT1        *((volatile  uint8_t *)(0x42624D04UL))
#define bFM4_INTREQ_IRQ025MON_FRT_ZERO_INT1       *((volatile  uint8_t *)(0x42624D04UL))
#define bFM_INTREQ_IRQ025MON_FRT_ZERO_INT2        *((volatile  uint8_t *)(0x42624D08UL))
#define bFM4_INTREQ_IRQ025MON_FRT_ZERO_INT2       *((volatile  uint8_t *)(0x42624D08UL))

#define bFM_INTREQ_IRQ026MON_ICUINT0              *((volatile  uint8_t *)(0x42624D80UL))
#define bFM4_INTREQ_IRQ026MON_ICUINT0             *((volatile  uint8_t *)(0x42624D80UL))
#define bFM_INTREQ_IRQ026MON_ICUINT1              *((volatile  uint8_t *)(0x42624D84UL))
#define bFM4_INTREQ_IRQ026MON_ICUINT1             *((volatile  uint8_t *)(0x42624D84UL))
#define bFM_INTREQ_IRQ026MON_ICUINT2              *((volatile  uint8_t *)(0x42624D88UL))
#define bFM4_INTREQ_IRQ026MON_ICUINT2             *((volatile  uint8_t *)(0x42624D88UL))
#define bFM_INTREQ_IRQ026MON_ICUINT3              *((volatile  uint8_t *)(0x42624D8CUL))
#define bFM4_INTREQ_IRQ026MON_ICUINT3             *((volatile  uint8_t *)(0x42624D8CUL))

#define bFM_INTREQ_IRQ027MON_OCUINT0              *((volatile  uint8_t *)(0x42624E00UL))
#define bFM4_INTREQ_IRQ027MON_OCUINT0             *((volatile  uint8_t *)(0x42624E00UL))
#define bFM_INTREQ_IRQ027MON_OCUINT1              *((volatile  uint8_t *)(0x42624E04UL))
#define bFM4_INTREQ_IRQ027MON_OCUINT1             *((volatile  uint8_t *)(0x42624E04UL))
#define bFM_INTREQ_IRQ027MON_OCUINT2              *((volatile  uint8_t *)(0x42624E08UL))
#define bFM4_INTREQ_IRQ027MON_OCUINT2             *((volatile  uint8_t *)(0x42624E08UL))
#define bFM_INTREQ_IRQ027MON_OCUINT3              *((volatile  uint8_t *)(0x42624E0CUL))
#define bFM4_INTREQ_IRQ027MON_OCUINT3             *((volatile  uint8_t *)(0x42624E0CUL))
#define bFM_INTREQ_IRQ027MON_OCUINT4              *((volatile  uint8_t *)(0x42624E10UL))
#define bFM4_INTREQ_IRQ027MON_OCUINT4             *((volatile  uint8_t *)(0x42624E10UL))
#define bFM_INTREQ_IRQ027MON_OCUINT5              *((volatile  uint8_t *)(0x42624E14UL))
#define bFM4_INTREQ_IRQ027MON_OCUINT5             *((volatile  uint8_t *)(0x42624E14UL))

#define bFM_INTREQ_IRQ028MON_FRT_PEAK_INT0        *((volatile  uint8_t *)(0x42624E80UL))
#define bFM4_INTREQ_IRQ028MON_FRT_PEAK_INT0       *((volatile  uint8_t *)(0x42624E80UL))
#define bFM_INTREQ_IRQ028MON_FRT_PEAK_INT1        *((volatile  uint8_t *)(0x42624E84UL))
#define bFM4_INTREQ_IRQ028MON_FRT_PEAK_INT1       *((volatile  uint8_t *)(0x42624E84UL))
#define bFM_INTREQ_IRQ028MON_FRT_PEAK_INT2        *((volatile  uint8_t *)(0x42624E88UL))
#define bFM4_INTREQ_IRQ028MON_FRT_PEAK_INT2       *((volatile  uint8_t *)(0x42624E88UL))

#define bFM_INTREQ_IRQ029MON_FRT_ZERO_INT0        *((volatile  uint8_t *)(0x42624F00UL))
#define bFM4_INTREQ_IRQ029MON_FRT_ZERO_INT0       *((volatile  uint8_t *)(0x42624F00UL))
#define bFM_INTREQ_IRQ029MON_FRT_ZERO_INT1        *((volatile  uint8_t *)(0x42624F04UL))
#define bFM4_INTREQ_IRQ029MON_FRT_ZERO_INT1       *((volatile  uint8_t *)(0x42624F04UL))
#define bFM_INTREQ_IRQ029MON_FRT_ZERO_INT2        *((volatile  uint8_t *)(0x42624F08UL))
#define bFM4_INTREQ_IRQ029MON_FRT_ZERO_INT2       *((volatile  uint8_t *)(0x42624F08UL))

#define bFM_INTREQ_IRQ030MON_ICUINT0              *((volatile  uint8_t *)(0x42624F80UL))
#define bFM4_INTREQ_IRQ030MON_ICUINT0             *((volatile  uint8_t *)(0x42624F80UL))
#define bFM_INTREQ_IRQ030MON_ICUINT1              *((volatile  uint8_t *)(0x42624F84UL))
#define bFM4_INTREQ_IRQ030MON_ICUINT1             *((volatile  uint8_t *)(0x42624F84UL))
#define bFM_INTREQ_IRQ030MON_ICUINT2              *((volatile  uint8_t *)(0x42624F88UL))
#define bFM4_INTREQ_IRQ030MON_ICUINT2             *((volatile  uint8_t *)(0x42624F88UL))
#define bFM_INTREQ_IRQ030MON_ICUINT3              *((volatile  uint8_t *)(0x42624F8CUL))
#define bFM4_INTREQ_IRQ030MON_ICUINT3             *((volatile  uint8_t *)(0x42624F8CUL))

#define bFM_INTREQ_IRQ031MON_OCUINT0              *((volatile  uint8_t *)(0x42625000UL))
#define bFM4_INTREQ_IRQ031MON_OCUINT0             *((volatile  uint8_t *)(0x42625000UL))
#define bFM_INTREQ_IRQ031MON_OCUINT1              *((volatile  uint8_t *)(0x42625004UL))
#define bFM4_INTREQ_IRQ031MON_OCUINT1             *((volatile  uint8_t *)(0x42625004UL))
#define bFM_INTREQ_IRQ031MON_OCUINT2              *((volatile  uint8_t *)(0x42625008UL))
#define bFM4_INTREQ_IRQ031MON_OCUINT2             *((volatile  uint8_t *)(0x42625008UL))
#define bFM_INTREQ_IRQ031MON_OCUINT3              *((volatile  uint8_t *)(0x4262500CUL))
#define bFM4_INTREQ_IRQ031MON_OCUINT3             *((volatile  uint8_t *)(0x4262500CUL))
#define bFM_INTREQ_IRQ031MON_OCUINT4              *((volatile  uint8_t *)(0x42625010UL))
#define bFM4_INTREQ_IRQ031MON_OCUINT4             *((volatile  uint8_t *)(0x42625010UL))
#define bFM_INTREQ_IRQ031MON_OCUINT5              *((volatile  uint8_t *)(0x42625014UL))
#define bFM4_INTREQ_IRQ031MON_OCUINT5             *((volatile  uint8_t *)(0x42625014UL))

#define bFM_INTREQ_IRQ032MON_FRT_PEAK_INT0        *((volatile  uint8_t *)(0x42625080UL))
#define bFM4_INTREQ_IRQ032MON_FRT_PEAK_INT0       *((volatile  uint8_t *)(0x42625080UL))
#define bFM_INTREQ_IRQ032MON_FRT_PEAK_INT1        *((volatile  uint8_t *)(0x42625084UL))
#define bFM4_INTREQ_IRQ032MON_FRT_PEAK_INT1       *((volatile  uint8_t *)(0x42625084UL))
#define bFM_INTREQ_IRQ032MON_FRT_PEAK_INT2        *((volatile  uint8_t *)(0x42625088UL))
#define bFM4_INTREQ_IRQ032MON_FRT_PEAK_INT2       *((volatile  uint8_t *)(0x42625088UL))

#define bFM_INTREQ_IRQ033MON_FRT_ZERO_INT0        *((volatile  uint8_t *)(0x42625100UL))
#define bFM4_INTREQ_IRQ033MON_FRT_ZERO_INT0       *((volatile  uint8_t *)(0x42625100UL))
#define bFM_INTREQ_IRQ033MON_FRT_ZERO_INT1        *((volatile  uint8_t *)(0x42625104UL))
#define bFM4_INTREQ_IRQ033MON_FRT_ZERO_INT1       *((volatile  uint8_t *)(0x42625104UL))
#define bFM_INTREQ_IRQ033MON_FRT_ZERO_INT2        *((volatile  uint8_t *)(0x42625108UL))
#define bFM4_INTREQ_IRQ033MON_FRT_ZERO_INT2       *((volatile  uint8_t *)(0x42625108UL))

#define bFM_INTREQ_IRQ034MON_ICUINT0              *((volatile  uint8_t *)(0x42625180UL))
#define bFM4_INTREQ_IRQ034MON_ICUINT0             *((volatile  uint8_t *)(0x42625180UL))
#define bFM_INTREQ_IRQ034MON_ICUINT1              *((volatile  uint8_t *)(0x42625184UL))
#define bFM4_INTREQ_IRQ034MON_ICUINT1             *((volatile  uint8_t *)(0x42625184UL))
#define bFM_INTREQ_IRQ034MON_ICUINT2              *((volatile  uint8_t *)(0x42625188UL))
#define bFM4_INTREQ_IRQ034MON_ICUINT2             *((volatile  uint8_t *)(0x42625188UL))
#define bFM_INTREQ_IRQ034MON_ICUINT3              *((volatile  uint8_t *)(0x4262518CUL))
#define bFM4_INTREQ_IRQ034MON_ICUINT3             *((volatile  uint8_t *)(0x4262518CUL))

#define bFM_INTREQ_IRQ035MON_OCUINT0              *((volatile  uint8_t *)(0x42625200UL))
#define bFM4_INTREQ_IRQ035MON_OCUINT0             *((volatile  uint8_t *)(0x42625200UL))
#define bFM_INTREQ_IRQ035MON_OCUINT1              *((volatile  uint8_t *)(0x42625204UL))
#define bFM4_INTREQ_IRQ035MON_OCUINT1             *((volatile  uint8_t *)(0x42625204UL))
#define bFM_INTREQ_IRQ035MON_OCUINT2              *((volatile  uint8_t *)(0x42625208UL))
#define bFM4_INTREQ_IRQ035MON_OCUINT2             *((volatile  uint8_t *)(0x42625208UL))
#define bFM_INTREQ_IRQ035MON_OCUINT3              *((volatile  uint8_t *)(0x4262520CUL))
#define bFM4_INTREQ_IRQ035MON_OCUINT3             *((volatile  uint8_t *)(0x4262520CUL))
#define bFM_INTREQ_IRQ035MON_OCUINT4              *((volatile  uint8_t *)(0x42625210UL))
#define bFM4_INTREQ_IRQ035MON_OCUINT4             *((volatile  uint8_t *)(0x42625210UL))
#define bFM_INTREQ_IRQ035MON_OCUINT5              *((volatile  uint8_t *)(0x42625214UL))
#define bFM4_INTREQ_IRQ035MON_OCUINT5             *((volatile  uint8_t *)(0x42625214UL))

#define bFM_INTREQ_IRQ036MON_PPGINT0              *((volatile  uint8_t *)(0x42625280UL))
#define bFM4_INTREQ_IRQ036MON_PPGINT0             *((volatile  uint8_t *)(0x42625280UL))
#define bFM_INTREQ_IRQ036MON_PPGINT1              *((volatile  uint8_t *)(0x42625284UL))
#define bFM4_INTREQ_IRQ036MON_PPGINT1             *((volatile  uint8_t *)(0x42625284UL))
#define bFM_INTREQ_IRQ036MON_PPGINT2              *((volatile  uint8_t *)(0x42625288UL))
#define bFM4_INTREQ_IRQ036MON_PPGINT2             *((volatile  uint8_t *)(0x42625288UL))

#define bFM_INTREQ_IRQ037MON_PPGINT0              *((volatile  uint8_t *)(0x42625300UL))
#define bFM4_INTREQ_IRQ037MON_PPGINT0             *((volatile  uint8_t *)(0x42625300UL))
#define bFM_INTREQ_IRQ037MON_PPGINT1              *((volatile  uint8_t *)(0x42625304UL))
#define bFM4_INTREQ_IRQ037MON_PPGINT1             *((volatile  uint8_t *)(0x42625304UL))
#define bFM_INTREQ_IRQ037MON_PPGINT2              *((volatile  uint8_t *)(0x42625308UL))
#define bFM4_INTREQ_IRQ037MON_PPGINT2             *((volatile  uint8_t *)(0x42625308UL))

#define bFM_INTREQ_IRQ038MON_PPGINT0              *((volatile  uint8_t *)(0x42625380UL))
#define bFM4_INTREQ_IRQ038MON_PPGINT0             *((volatile  uint8_t *)(0x42625380UL))
#define bFM_INTREQ_IRQ038MON_PPGINT1              *((volatile  uint8_t *)(0x42625384UL))
#define bFM4_INTREQ_IRQ038MON_PPGINT1             *((volatile  uint8_t *)(0x42625384UL))
#define bFM_INTREQ_IRQ038MON_PPGINT2              *((volatile  uint8_t *)(0x42625388UL))
#define bFM4_INTREQ_IRQ038MON_PPGINT2             *((volatile  uint8_t *)(0x42625388UL))

#define bFM_INTREQ_IRQ039MON_BTINT0               *((volatile  uint8_t *)(0x42625400UL))
#define bFM4_INTREQ_IRQ039MON_BTINT0              *((volatile  uint8_t *)(0x42625400UL))
#define bFM_INTREQ_IRQ039MON_BTINT1               *((volatile  uint8_t *)(0x42625404UL))
#define bFM4_INTREQ_IRQ039MON_BTINT1              *((volatile  uint8_t *)(0x42625404UL))

#define bFM_INTREQ_IRQ040MON_BTINT0               *((volatile  uint8_t *)(0x42625480UL))
#define bFM4_INTREQ_IRQ040MON_BTINT0              *((volatile  uint8_t *)(0x42625480UL))
#define bFM_INTREQ_IRQ040MON_BTINT1               *((volatile  uint8_t *)(0x42625484UL))
#define bFM4_INTREQ_IRQ040MON_BTINT1              *((volatile  uint8_t *)(0x42625484UL))

#define bFM_INTREQ_IRQ041MON_BTINT0               *((volatile  uint8_t *)(0x42625500UL))
#define bFM4_INTREQ_IRQ041MON_BTINT0              *((volatile  uint8_t *)(0x42625500UL))
#define bFM_INTREQ_IRQ041MON_BTINT1               *((volatile  uint8_t *)(0x42625504UL))
#define bFM4_INTREQ_IRQ041MON_BTINT1              *((volatile  uint8_t *)(0x42625504UL))

#define bFM_INTREQ_IRQ042MON_BTINT0               *((volatile  uint8_t *)(0x42625580UL))
#define bFM4_INTREQ_IRQ042MON_BTINT0              *((volatile  uint8_t *)(0x42625580UL))
#define bFM_INTREQ_IRQ042MON_BTINT1               *((volatile  uint8_t *)(0x42625584UL))
#define bFM4_INTREQ_IRQ042MON_BTINT1              *((volatile  uint8_t *)(0x42625584UL))

#define bFM_INTREQ_IRQ043MON_BTINT0               *((volatile  uint8_t *)(0x42625600UL))
#define bFM4_INTREQ_IRQ043MON_BTINT0              *((volatile  uint8_t *)(0x42625600UL))
#define bFM_INTREQ_IRQ043MON_BTINT1               *((volatile  uint8_t *)(0x42625604UL))
#define bFM4_INTREQ_IRQ043MON_BTINT1              *((volatile  uint8_t *)(0x42625604UL))

#define bFM_INTREQ_IRQ044MON_BTINT0               *((volatile  uint8_t *)(0x42625680UL))
#define bFM4_INTREQ_IRQ044MON_BTINT0              *((volatile  uint8_t *)(0x42625680UL))
#define bFM_INTREQ_IRQ044MON_BTINT1               *((volatile  uint8_t *)(0x42625684UL))
#define bFM4_INTREQ_IRQ044MON_BTINT1              *((volatile  uint8_t *)(0x42625684UL))

#define bFM_INTREQ_IRQ045MON_BTINT0               *((volatile  uint8_t *)(0x42625700UL))
#define bFM4_INTREQ_IRQ045MON_BTINT0              *((volatile  uint8_t *)(0x42625700UL))
#define bFM_INTREQ_IRQ045MON_BTINT1               *((volatile  uint8_t *)(0x42625704UL))
#define bFM4_INTREQ_IRQ045MON_BTINT1              *((volatile  uint8_t *)(0x42625704UL))

#define bFM_INTREQ_IRQ046MON_BTINT0               *((volatile  uint8_t *)(0x42625780UL))
#define bFM4_INTREQ_IRQ046MON_BTINT0              *((volatile  uint8_t *)(0x42625780UL))
#define bFM_INTREQ_IRQ046MON_BTINT1               *((volatile  uint8_t *)(0x42625784UL))
#define bFM4_INTREQ_IRQ046MON_BTINT1              *((volatile  uint8_t *)(0x42625784UL))

#define bFM_INTREQ_IRQ047MON_TIMINT1              *((volatile  uint8_t *)(0x42625800UL))
#define bFM4_INTREQ_IRQ047MON_TIMINT1             *((volatile  uint8_t *)(0x42625800UL))
#define bFM_INTREQ_IRQ047MON_TIMINT2              *((volatile  uint8_t *)(0x42625804UL))
#define bFM4_INTREQ_IRQ047MON_TIMINT2             *((volatile  uint8_t *)(0x42625804UL))

#define bFM_INTREQ_IRQ048MON_WCINT                *((volatile  uint8_t *)(0x42625880UL))
#define bFM4_INTREQ_IRQ048MON_WCINT               *((volatile  uint8_t *)(0x42625880UL))

#define bFM_INTREQ_IRQ049MON_BMEMCS               *((volatile  uint8_t *)(0x42625900UL))
#define bFM4_INTREQ_IRQ049MON_BMEMCS              *((volatile  uint8_t *)(0x42625900UL))

#define bFM_INTREQ_IRQ050MON_RTCINT               *((volatile  uint8_t *)(0x42625980UL))
#define bFM4_INTREQ_IRQ050MON_RTCINT              *((volatile  uint8_t *)(0x42625980UL))

#define bFM_INTREQ_IRQ051MON_EXTINT               *((volatile  uint8_t *)(0x42625A00UL))
#define bFM4_INTREQ_IRQ051MON_EXTINT              *((volatile  uint8_t *)(0x42625A00UL))

#define bFM_INTREQ_IRQ052MON_EXTINT               *((volatile  uint8_t *)(0x42625A80UL))
#define bFM4_INTREQ_IRQ052MON_EXTINT              *((volatile  uint8_t *)(0x42625A80UL))

#define bFM_INTREQ_IRQ053MON_EXTINT               *((volatile  uint8_t *)(0x42625B00UL))
#define bFM4_INTREQ_IRQ053MON_EXTINT              *((volatile  uint8_t *)(0x42625B00UL))

#define bFM_INTREQ_IRQ054MON_EXTINT               *((volatile  uint8_t *)(0x42625B80UL))
#define bFM4_INTREQ_IRQ054MON_EXTINT              *((volatile  uint8_t *)(0x42625B80UL))

#define bFM_INTREQ_IRQ055MON_EXTINT               *((volatile  uint8_t *)(0x42625C00UL))
#define bFM4_INTREQ_IRQ055MON_EXTINT              *((volatile  uint8_t *)(0x42625C00UL))

#define bFM_INTREQ_IRQ056MON_EXTINT               *((volatile  uint8_t *)(0x42625C80UL))
#define bFM4_INTREQ_IRQ056MON_EXTINT              *((volatile  uint8_t *)(0x42625C80UL))

#define bFM_INTREQ_IRQ057MON_EXTINT               *((volatile  uint8_t *)(0x42625D00UL))
#define bFM4_INTREQ_IRQ057MON_EXTINT              *((volatile  uint8_t *)(0x42625D00UL))

#define bFM_INTREQ_IRQ058MON_EXTINT               *((volatile  uint8_t *)(0x42625D80UL))
#define bFM4_INTREQ_IRQ058MON_EXTINT              *((volatile  uint8_t *)(0x42625D80UL))

#define bFM_INTREQ_IRQ059MON_MOSCINT              *((volatile  uint8_t *)(0x42625E00UL))
#define bFM4_INTREQ_IRQ059MON_MOSCINT             *((volatile  uint8_t *)(0x42625E00UL))
#define bFM_INTREQ_IRQ059MON_SOSCINT              *((volatile  uint8_t *)(0x42625E04UL))
#define bFM4_INTREQ_IRQ059MON_SOSCINT             *((volatile  uint8_t *)(0x42625E04UL))
#define bFM_INTREQ_IRQ059MON_MPLLINT              *((volatile  uint8_t *)(0x42625E08UL))
#define bFM4_INTREQ_IRQ059MON_MPLLINT             *((volatile  uint8_t *)(0x42625E08UL))
#define bFM_INTREQ_IRQ059MON_UPLLINT              *((volatile  uint8_t *)(0x42625E0CUL))
#define bFM4_INTREQ_IRQ059MON_UPLLINT             *((volatile  uint8_t *)(0x42625E0CUL))
#define bFM_INTREQ_IRQ059MON_IPLLINT              *((volatile  uint8_t *)(0x42625E10UL))
#define bFM4_INTREQ_IRQ059MON_IPLLINT             *((volatile  uint8_t *)(0x42625E10UL))

#define bFM_INTREQ_IRQ060MON_MFSINT0_RX           *((volatile  uint8_t *)(0x42625E80UL))
#define bFM4_INTREQ_IRQ060MON_MFSINT0_RX          *((volatile  uint8_t *)(0x42625E80UL))

#define bFM_INTREQ_IRQ061MON_MFSINT0_TX           *((volatile  uint8_t *)(0x42625F00UL))
#define bFM4_INTREQ_IRQ061MON_MFSINT0_TX          *((volatile  uint8_t *)(0x42625F00UL))
#define bFM_INTREQ_IRQ061MON_MFSINT0_STATUS       *((volatile  uint8_t *)(0x42625F04UL))
#define bFM4_INTREQ_IRQ061MON_MFSINT0_STATUS      *((volatile  uint8_t *)(0x42625F04UL))

#define bFM_INTREQ_IRQ062MON_MFSINT1_RX           *((volatile  uint8_t *)(0x42625F80UL))
#define bFM4_INTREQ_IRQ062MON_MFSINT1_RX          *((volatile  uint8_t *)(0x42625F80UL))

#define bFM_INTREQ_IRQ063MON_MFSINT1_TX           *((volatile  uint8_t *)(0x42626000UL))
#define bFM4_INTREQ_IRQ063MON_MFSINT1_TX          *((volatile  uint8_t *)(0x42626000UL))
#define bFM_INTREQ_IRQ063MON_MFSINT1_STATUS       *((volatile  uint8_t *)(0x42626004UL))
#define bFM4_INTREQ_IRQ063MON_MFSINT1_STATUS      *((volatile  uint8_t *)(0x42626004UL))

#define bFM_INTREQ_IRQ064MON_MFSINT2_RX           *((volatile  uint8_t *)(0x42626080UL))
#define bFM4_INTREQ_IRQ064MON_MFSINT2_RX          *((volatile  uint8_t *)(0x42626080UL))

#define bFM_INTREQ_IRQ065MON_MFSINT2_TX           *((volatile  uint8_t *)(0x42626100UL))
#define bFM4_INTREQ_IRQ065MON_MFSINT2_TX          *((volatile  uint8_t *)(0x42626100UL))
#define bFM_INTREQ_IRQ065MON_MFSINT2_STATUS       *((volatile  uint8_t *)(0x42626104UL))
#define bFM4_INTREQ_IRQ065MON_MFSINT2_STATUS      *((volatile  uint8_t *)(0x42626104UL))

#define bFM_INTREQ_IRQ066MON_MFSINT3_RX           *((volatile  uint8_t *)(0x42626180UL))
#define bFM4_INTREQ_IRQ066MON_MFSINT3_RX          *((volatile  uint8_t *)(0x42626180UL))

#define bFM_INTREQ_IRQ067MON_MFSINT3_TX           *((volatile  uint8_t *)(0x42626200UL))
#define bFM4_INTREQ_IRQ067MON_MFSINT3_TX          *((volatile  uint8_t *)(0x42626200UL))
#define bFM_INTREQ_IRQ067MON_MFSINT3_STATUS       *((volatile  uint8_t *)(0x42626204UL))
#define bFM4_INTREQ_IRQ067MON_MFSINT3_STATUS      *((volatile  uint8_t *)(0x42626204UL))

#define bFM_INTREQ_IRQ068MON_MFSINT4_RX           *((volatile  uint8_t *)(0x42626280UL))
#define bFM4_INTREQ_IRQ068MON_MFSINT4_RX          *((volatile  uint8_t *)(0x42626280UL))

#define bFM_INTREQ_IRQ069MON_MFSINT4_TX           *((volatile  uint8_t *)(0x42626300UL))
#define bFM4_INTREQ_IRQ069MON_MFSINT4_TX          *((volatile  uint8_t *)(0x42626300UL))
#define bFM_INTREQ_IRQ069MON_MFSINT4_STATUS       *((volatile  uint8_t *)(0x42626304UL))
#define bFM4_INTREQ_IRQ069MON_MFSINT4_STATUS      *((volatile  uint8_t *)(0x42626304UL))

#define bFM_INTREQ_IRQ070MON_MFSINT5_RX           *((volatile  uint8_t *)(0x42626380UL))
#define bFM4_INTREQ_IRQ070MON_MFSINT5_RX          *((volatile  uint8_t *)(0x42626380UL))

#define bFM_INTREQ_IRQ071MON_MFSINT5_TX           *((volatile  uint8_t *)(0x42626400UL))
#define bFM4_INTREQ_IRQ071MON_MFSINT5_TX          *((volatile  uint8_t *)(0x42626400UL))
#define bFM_INTREQ_IRQ071MON_MFSINT5_STATUS       *((volatile  uint8_t *)(0x42626404UL))
#define bFM4_INTREQ_IRQ071MON_MFSINT5_STATUS      *((volatile  uint8_t *)(0x42626404UL))

#define bFM_INTREQ_IRQ072MON_MFSINT6_RX           *((volatile  uint8_t *)(0x42626480UL))
#define bFM4_INTREQ_IRQ072MON_MFSINT6_RX          *((volatile  uint8_t *)(0x42626480UL))

#define bFM_INTREQ_IRQ073MON_MFSINT6_TX           *((volatile  uint8_t *)(0x42626500UL))
#define bFM4_INTREQ_IRQ073MON_MFSINT6_TX          *((volatile  uint8_t *)(0x42626500UL))
#define bFM_INTREQ_IRQ073MON_MFSINT6_STATUS       *((volatile  uint8_t *)(0x42626504UL))
#define bFM4_INTREQ_IRQ073MON_MFSINT6_STATUS      *((volatile  uint8_t *)(0x42626504UL))

#define bFM_INTREQ_IRQ074MON_MFSINT7_RX           *((volatile  uint8_t *)(0x42626580UL))
#define bFM4_INTREQ_IRQ074MON_MFSINT7_RX          *((volatile  uint8_t *)(0x42626580UL))

#define bFM_INTREQ_IRQ075MON_MFSINT7_TX           *((volatile  uint8_t *)(0x42626600UL))
#define bFM4_INTREQ_IRQ075MON_MFSINT7_TX          *((volatile  uint8_t *)(0x42626600UL))
#define bFM_INTREQ_IRQ075MON_MFSINT7_STATUS       *((volatile  uint8_t *)(0x42626604UL))
#define bFM4_INTREQ_IRQ075MON_MFSINT7_STATUS      *((volatile  uint8_t *)(0x42626604UL))

#define bFM_INTREQ_IRQ076MON_ADCINT0              *((volatile  uint8_t *)(0x42626680UL))
#define bFM4_INTREQ_IRQ076MON_ADCINT0             *((volatile  uint8_t *)(0x42626680UL))
#define bFM_INTREQ_IRQ076MON_ADCINT1              *((volatile  uint8_t *)(0x42626684UL))
#define bFM4_INTREQ_IRQ076MON_ADCINT1             *((volatile  uint8_t *)(0x42626684UL))
#define bFM_INTREQ_IRQ076MON_ADCINT2              *((volatile  uint8_t *)(0x42626688UL))
#define bFM4_INTREQ_IRQ076MON_ADCINT2             *((volatile  uint8_t *)(0x42626688UL))
#define bFM_INTREQ_IRQ076MON_ADCINT3              *((volatile  uint8_t *)(0x4262668CUL))
#define bFM4_INTREQ_IRQ076MON_ADCINT3             *((volatile  uint8_t *)(0x4262668CUL))
#define bFM_INTREQ_IRQ076MON_ADCINT4              *((volatile  uint8_t *)(0x42626690UL))
#define bFM4_INTREQ_IRQ076MON_ADCINT4             *((volatile  uint8_t *)(0x42626690UL))

#define bFM_INTREQ_IRQ077MON_ADCINT0              *((volatile  uint8_t *)(0x42626700UL))
#define bFM4_INTREQ_IRQ077MON_ADCINT0             *((volatile  uint8_t *)(0x42626700UL))
#define bFM_INTREQ_IRQ077MON_ADCINT1              *((volatile  uint8_t *)(0x42626704UL))
#define bFM4_INTREQ_IRQ077MON_ADCINT1             *((volatile  uint8_t *)(0x42626704UL))
#define bFM_INTREQ_IRQ077MON_ADCINT2              *((volatile  uint8_t *)(0x42626708UL))
#define bFM4_INTREQ_IRQ077MON_ADCINT2             *((volatile  uint8_t *)(0x42626708UL))
#define bFM_INTREQ_IRQ077MON_ADCINT3              *((volatile  uint8_t *)(0x4262670CUL))
#define bFM4_INTREQ_IRQ077MON_ADCINT3             *((volatile  uint8_t *)(0x4262670CUL))
#define bFM_INTREQ_IRQ077MON_ADCINT4              *((volatile  uint8_t *)(0x42626710UL))
#define bFM4_INTREQ_IRQ077MON_ADCINT4             *((volatile  uint8_t *)(0x42626710UL))

#define bFM_INTREQ_IRQ078MON_USB_DRQ_INT0         *((volatile  uint8_t *)(0x42626780UL))
#define bFM4_INTREQ_IRQ078MON_USB_DRQ_INT0        *((volatile  uint8_t *)(0x42626780UL))
#define bFM_INTREQ_IRQ078MON_USB_DRQ_INT1         *((volatile  uint8_t *)(0x42626784UL))
#define bFM4_INTREQ_IRQ078MON_USB_DRQ_INT1        *((volatile  uint8_t *)(0x42626784UL))
#define bFM_INTREQ_IRQ078MON_USB_DRQ_INT2         *((volatile  uint8_t *)(0x42626788UL))
#define bFM4_INTREQ_IRQ078MON_USB_DRQ_INT2        *((volatile  uint8_t *)(0x42626788UL))
#define bFM_INTREQ_IRQ078MON_USB_DRQ_INT3         *((volatile  uint8_t *)(0x4262678CUL))
#define bFM4_INTREQ_IRQ078MON_USB_DRQ_INT3        *((volatile  uint8_t *)(0x4262678CUL))
#define bFM_INTREQ_IRQ078MON_USB_DRQ_INT4         *((volatile  uint8_t *)(0x42626790UL))
#define bFM4_INTREQ_IRQ078MON_USB_DRQ_INT4        *((volatile  uint8_t *)(0x42626790UL))

#define bFM_INTREQ_IRQ079MON_USB_INT0             *((volatile  uint8_t *)(0x42626800UL))
#define bFM4_INTREQ_IRQ079MON_USB_INT0            *((volatile  uint8_t *)(0x42626800UL))
#define bFM_INTREQ_IRQ079MON_USB_INT1             *((volatile  uint8_t *)(0x42626804UL))
#define bFM4_INTREQ_IRQ079MON_USB_INT1            *((volatile  uint8_t *)(0x42626804UL))
#define bFM_INTREQ_IRQ079MON_USB_INT2             *((volatile  uint8_t *)(0x42626808UL))
#define bFM4_INTREQ_IRQ079MON_USB_INT2            *((volatile  uint8_t *)(0x42626808UL))
#define bFM_INTREQ_IRQ079MON_USB_INT3             *((volatile  uint8_t *)(0x4262680CUL))
#define bFM4_INTREQ_IRQ079MON_USB_INT3            *((volatile  uint8_t *)(0x4262680CUL))
#define bFM_INTREQ_IRQ079MON_USB_INT4             *((volatile  uint8_t *)(0x42626810UL))
#define bFM4_INTREQ_IRQ079MON_USB_INT4            *((volatile  uint8_t *)(0x42626810UL))
#define bFM_INTREQ_IRQ079MON_USB_INT5             *((volatile  uint8_t *)(0x42626814UL))
#define bFM4_INTREQ_IRQ079MON_USB_INT5            *((volatile  uint8_t *)(0x42626814UL))

#define bFM_INTREQ_IRQ080MON_CANINT               *((volatile  uint8_t *)(0x42626880UL))
#define bFM4_INTREQ_IRQ080MON_CANINT              *((volatile  uint8_t *)(0x42626880UL))

#define bFM_INTREQ_IRQ081MON_CANINT               *((volatile  uint8_t *)(0x42626900UL))
#define bFM4_INTREQ_IRQ081MON_CANINT              *((volatile  uint8_t *)(0x42626900UL))
#define bFM_INTREQ_IRQ081MON_CANDEINT             *((volatile  uint8_t *)(0x42626904UL))
#define bFM4_INTREQ_IRQ081MON_CANDEINT            *((volatile  uint8_t *)(0x42626904UL))
#define bFM_INTREQ_IRQ081MON_CANSEINT             *((volatile  uint8_t *)(0x42626908UL))
#define bFM4_INTREQ_IRQ081MON_CANSEINT            *((volatile  uint8_t *)(0x42626908UL))
#define bFM_INTREQ_IRQ081MON_CAN0INT              *((volatile  uint8_t *)(0x4262690CUL))
#define bFM4_INTREQ_IRQ081MON_CAN0INT             *((volatile  uint8_t *)(0x4262690CUL))
#define bFM_INTREQ_IRQ081MON_CAN1INT              *((volatile  uint8_t *)(0x42626910UL))
#define bFM4_INTREQ_IRQ081MON_CAN1INT             *((volatile  uint8_t *)(0x42626910UL))

#define bFM_INTREQ_IRQ082MON_MACSBD               *((volatile  uint8_t *)(0x42626980UL))
#define bFM4_INTREQ_IRQ082MON_MACSBD              *((volatile  uint8_t *)(0x42626980UL))
#define bFM_INTREQ_IRQ082MON_MACPMT               *((volatile  uint8_t *)(0x42626984UL))
#define bFM4_INTREQ_IRQ082MON_MACPMT              *((volatile  uint8_t *)(0x42626984UL))
#define bFM_INTREQ_IRQ082MON_MACLPI               *((volatile  uint8_t *)(0x42626988UL))
#define bFM4_INTREQ_IRQ082MON_MACLPI              *((volatile  uint8_t *)(0x42626988UL))

#define bFM_INTREQ_IRQ083MON_DMACINT              *((volatile  uint8_t *)(0x42626A00UL))
#define bFM4_INTREQ_IRQ083MON_DMACINT             *((volatile  uint8_t *)(0x42626A00UL))

#define bFM_INTREQ_IRQ084MON_DMACINT              *((volatile  uint8_t *)(0x42626A80UL))
#define bFM4_INTREQ_IRQ084MON_DMACINT             *((volatile  uint8_t *)(0x42626A80UL))

#define bFM_INTREQ_IRQ085MON_DMACINT              *((volatile  uint8_t *)(0x42626B00UL))
#define bFM4_INTREQ_IRQ085MON_DMACINT             *((volatile  uint8_t *)(0x42626B00UL))

#define bFM_INTREQ_IRQ086MON_DMACINT              *((volatile  uint8_t *)(0x42626B80UL))
#define bFM4_INTREQ_IRQ086MON_DMACINT             *((volatile  uint8_t *)(0x42626B80UL))

#define bFM_INTREQ_IRQ087MON_DMACINT              *((volatile  uint8_t *)(0x42626C00UL))
#define bFM4_INTREQ_IRQ087MON_DMACINT             *((volatile  uint8_t *)(0x42626C00UL))

#define bFM_INTREQ_IRQ088MON_DMACINT              *((volatile  uint8_t *)(0x42626C80UL))
#define bFM4_INTREQ_IRQ088MON_DMACINT             *((volatile  uint8_t *)(0x42626C80UL))

#define bFM_INTREQ_IRQ089MON_DMACINT              *((volatile  uint8_t *)(0x42626D00UL))
#define bFM4_INTREQ_IRQ089MON_DMACINT             *((volatile  uint8_t *)(0x42626D00UL))

#define bFM_INTREQ_IRQ090MON_DMACINT              *((volatile  uint8_t *)(0x42626D80UL))
#define bFM4_INTREQ_IRQ090MON_DMACINT             *((volatile  uint8_t *)(0x42626D80UL))

#define bFM_INTREQ_IRQ091MON_DSTCINT0             *((volatile  uint8_t *)(0x42626E00UL))
#define bFM4_INTREQ_IRQ091MON_DSTCINT0            *((volatile  uint8_t *)(0x42626E00UL))
#define bFM_INTREQ_IRQ091MON_DSTCINT1             *((volatile  uint8_t *)(0x42626E04UL))
#define bFM4_INTREQ_IRQ091MON_DSTCINT1            *((volatile  uint8_t *)(0x42626E04UL))

#define bFM_INTREQ_IRQ092MON_EXTINT0              *((volatile  uint8_t *)(0x42626E80UL))
#define bFM4_INTREQ_IRQ092MON_EXTINT0             *((volatile  uint8_t *)(0x42626E80UL))
#define bFM_INTREQ_IRQ092MON_EXTINT1              *((volatile  uint8_t *)(0x42626E84UL))
#define bFM4_INTREQ_IRQ092MON_EXTINT1             *((volatile  uint8_t *)(0x42626E84UL))
#define bFM_INTREQ_IRQ092MON_EXTINT2              *((volatile  uint8_t *)(0x42626E88UL))
#define bFM4_INTREQ_IRQ092MON_EXTINT2             *((volatile  uint8_t *)(0x42626E88UL))
#define bFM_INTREQ_IRQ092MON_EXTINT3              *((volatile  uint8_t *)(0x42626E8CUL))
#define bFM4_INTREQ_IRQ092MON_EXTINT3             *((volatile  uint8_t *)(0x42626E8CUL))

#define bFM_INTREQ_IRQ093MON_EXTINT0              *((volatile  uint8_t *)(0x42626F00UL))
#define bFM4_INTREQ_IRQ093MON_EXTINT0             *((volatile  uint8_t *)(0x42626F00UL))
#define bFM_INTREQ_IRQ093MON_EXTINT1              *((volatile  uint8_t *)(0x42626F04UL))
#define bFM4_INTREQ_IRQ093MON_EXTINT1             *((volatile  uint8_t *)(0x42626F04UL))
#define bFM_INTREQ_IRQ093MON_EXTINT2              *((volatile  uint8_t *)(0x42626F08UL))
#define bFM4_INTREQ_IRQ093MON_EXTINT2             *((volatile  uint8_t *)(0x42626F08UL))
#define bFM_INTREQ_IRQ093MON_EXTINT3              *((volatile  uint8_t *)(0x42626F0CUL))
#define bFM4_INTREQ_IRQ093MON_EXTINT3             *((volatile  uint8_t *)(0x42626F0CUL))

#define bFM_INTREQ_IRQ094MON_EXTINT0              *((volatile  uint8_t *)(0x42626F80UL))
#define bFM4_INTREQ_IRQ094MON_EXTINT0             *((volatile  uint8_t *)(0x42626F80UL))
#define bFM_INTREQ_IRQ094MON_EXTINT1              *((volatile  uint8_t *)(0x42626F84UL))
#define bFM4_INTREQ_IRQ094MON_EXTINT1             *((volatile  uint8_t *)(0x42626F84UL))
#define bFM_INTREQ_IRQ094MON_EXTINT2              *((volatile  uint8_t *)(0x42626F88UL))
#define bFM4_INTREQ_IRQ094MON_EXTINT2             *((volatile  uint8_t *)(0x42626F88UL))
#define bFM_INTREQ_IRQ094MON_EXTINT3              *((volatile  uint8_t *)(0x42626F8CUL))
#define bFM4_INTREQ_IRQ094MON_EXTINT3             *((volatile  uint8_t *)(0x42626F8CUL))

#define bFM_INTREQ_IRQ095MON_EXTINT0              *((volatile  uint8_t *)(0x42627000UL))
#define bFM4_INTREQ_IRQ095MON_EXTINT0             *((volatile  uint8_t *)(0x42627000UL))
#define bFM_INTREQ_IRQ095MON_EXTINT1              *((volatile  uint8_t *)(0x42627004UL))
#define bFM4_INTREQ_IRQ095MON_EXTINT1             *((volatile  uint8_t *)(0x42627004UL))
#define bFM_INTREQ_IRQ095MON_EXTINT2              *((volatile  uint8_t *)(0x42627008UL))
#define bFM4_INTREQ_IRQ095MON_EXTINT2             *((volatile  uint8_t *)(0x42627008UL))
#define bFM_INTREQ_IRQ095MON_EXTINT3              *((volatile  uint8_t *)(0x4262700CUL))
#define bFM4_INTREQ_IRQ095MON_EXTINT3             *((volatile  uint8_t *)(0x4262700CUL))

#define bFM_INTREQ_IRQ096MON_QPRCINT0             *((volatile  uint8_t *)(0x42627080UL))
#define bFM4_INTREQ_IRQ096MON_QPRCINT0            *((volatile  uint8_t *)(0x42627080UL))
#define bFM_INTREQ_IRQ096MON_QPRCINT1             *((volatile  uint8_t *)(0x42627084UL))
#define bFM4_INTREQ_IRQ096MON_QPRCINT1            *((volatile  uint8_t *)(0x42627084UL))
#define bFM_INTREQ_IRQ096MON_QPRCINT2             *((volatile  uint8_t *)(0x42627088UL))
#define bFM4_INTREQ_IRQ096MON_QPRCINT2            *((volatile  uint8_t *)(0x42627088UL))
#define bFM_INTREQ_IRQ096MON_QPRCINT3             *((volatile  uint8_t *)(0x4262708CUL))
#define bFM4_INTREQ_IRQ096MON_QPRCINT3            *((volatile  uint8_t *)(0x4262708CUL))
#define bFM_INTREQ_IRQ096MON_QPRCINT4             *((volatile  uint8_t *)(0x42627090UL))
#define bFM4_INTREQ_IRQ096MON_QPRCINT4            *((volatile  uint8_t *)(0x42627090UL))
#define bFM_INTREQ_IRQ096MON_QPRCINT5             *((volatile  uint8_t *)(0x42627094UL))
#define bFM4_INTREQ_IRQ096MON_QPRCINT5            *((volatile  uint8_t *)(0x42627094UL))

#define bFM_INTREQ_IRQ097MON_QPRCINT0             *((volatile  uint8_t *)(0x42627100UL))
#define bFM4_INTREQ_IRQ097MON_QPRCINT0            *((volatile  uint8_t *)(0x42627100UL))
#define bFM_INTREQ_IRQ097MON_QPRCINT1             *((volatile  uint8_t *)(0x42627104UL))
#define bFM4_INTREQ_IRQ097MON_QPRCINT1            *((volatile  uint8_t *)(0x42627104UL))
#define bFM_INTREQ_IRQ097MON_QPRCINT2             *((volatile  uint8_t *)(0x42627108UL))
#define bFM4_INTREQ_IRQ097MON_QPRCINT2            *((volatile  uint8_t *)(0x42627108UL))
#define bFM_INTREQ_IRQ097MON_QPRCINT3             *((volatile  uint8_t *)(0x4262710CUL))
#define bFM4_INTREQ_IRQ097MON_QPRCINT3            *((volatile  uint8_t *)(0x4262710CUL))
#define bFM_INTREQ_IRQ097MON_QPRCINT4             *((volatile  uint8_t *)(0x42627110UL))
#define bFM4_INTREQ_IRQ097MON_QPRCINT4            *((volatile  uint8_t *)(0x42627110UL))
#define bFM_INTREQ_IRQ097MON_QPRCINT5             *((volatile  uint8_t *)(0x42627114UL))
#define bFM4_INTREQ_IRQ097MON_QPRCINT5            *((volatile  uint8_t *)(0x42627114UL))

#define bFM_INTREQ_IRQ098MON_BTINT0               *((volatile  uint8_t *)(0x42627180UL))
#define bFM4_INTREQ_IRQ098MON_BTINT0              *((volatile  uint8_t *)(0x42627180UL))
#define bFM_INTREQ_IRQ098MON_BTINT1               *((volatile  uint8_t *)(0x42627184UL))
#define bFM4_INTREQ_IRQ098MON_BTINT1              *((volatile  uint8_t *)(0x42627184UL))

#define bFM_INTREQ_IRQ099MON_BTINT0               *((volatile  uint8_t *)(0x42627200UL))
#define bFM4_INTREQ_IRQ099MON_BTINT0              *((volatile  uint8_t *)(0x42627200UL))
#define bFM_INTREQ_IRQ099MON_BTINT1               *((volatile  uint8_t *)(0x42627204UL))
#define bFM4_INTREQ_IRQ099MON_BTINT1              *((volatile  uint8_t *)(0x42627204UL))

#define bFM_INTREQ_IRQ100MON_BTINT0               *((volatile  uint8_t *)(0x42627280UL))
#define bFM4_INTREQ_IRQ100MON_BTINT0              *((volatile  uint8_t *)(0x42627280UL))
#define bFM_INTREQ_IRQ100MON_BTINT1               *((volatile  uint8_t *)(0x42627284UL))
#define bFM4_INTREQ_IRQ100MON_BTINT1              *((volatile  uint8_t *)(0x42627284UL))

#define bFM_INTREQ_IRQ101MON_BTINT0               *((volatile  uint8_t *)(0x42627300UL))
#define bFM4_INTREQ_IRQ101MON_BTINT0              *((volatile  uint8_t *)(0x42627300UL))
#define bFM_INTREQ_IRQ101MON_BTINT1               *((volatile  uint8_t *)(0x42627304UL))
#define bFM4_INTREQ_IRQ101MON_BTINT1              *((volatile  uint8_t *)(0x42627304UL))

#define bFM_INTREQ_IRQ102MON_BTINT0               *((volatile  uint8_t *)(0x42627380UL))
#define bFM4_INTREQ_IRQ102MON_BTINT0              *((volatile  uint8_t *)(0x42627380UL))
#define bFM_INTREQ_IRQ102MON_BTINT1               *((volatile  uint8_t *)(0x42627384UL))
#define bFM4_INTREQ_IRQ102MON_BTINT1              *((volatile  uint8_t *)(0x42627384UL))
#define bFM_INTREQ_IRQ102MON_BTINT2               *((volatile  uint8_t *)(0x42627388UL))
#define bFM4_INTREQ_IRQ102MON_BTINT2              *((volatile  uint8_t *)(0x42627388UL))
#define bFM_INTREQ_IRQ102MON_BTINT3               *((volatile  uint8_t *)(0x4262738CUL))
#define bFM4_INTREQ_IRQ102MON_BTINT3              *((volatile  uint8_t *)(0x4262738CUL))
#define bFM_INTREQ_IRQ102MON_BTINT4               *((volatile  uint8_t *)(0x42627390UL))
#define bFM4_INTREQ_IRQ102MON_BTINT4              *((volatile  uint8_t *)(0x42627390UL))
#define bFM_INTREQ_IRQ102MON_BTINT5               *((volatile  uint8_t *)(0x42627394UL))
#define bFM4_INTREQ_IRQ102MON_BTINT5              *((volatile  uint8_t *)(0x42627394UL))
#define bFM_INTREQ_IRQ102MON_BTINT6               *((volatile  uint8_t *)(0x42627398UL))
#define bFM4_INTREQ_IRQ102MON_BTINT6              *((volatile  uint8_t *)(0x42627398UL))
#define bFM_INTREQ_IRQ102MON_BTINT7               *((volatile  uint8_t *)(0x4262739CUL))
#define bFM4_INTREQ_IRQ102MON_BTINT7              *((volatile  uint8_t *)(0x4262739CUL))

#define bFM_INTREQ_IRQ103MON_MFSINT8_RX           *((volatile  uint8_t *)(0x42627400UL))
#define bFM4_INTREQ_IRQ103MON_MFSINT8_RX          *((volatile  uint8_t *)(0x42627400UL))

#define bFM_INTREQ_IRQ104MON_MFSINT8_TX           *((volatile  uint8_t *)(0x42627480UL))
#define bFM4_INTREQ_IRQ104MON_MFSINT8_TX          *((volatile  uint8_t *)(0x42627480UL))
#define bFM_INTREQ_IRQ104MON_MFSINT8_STATUS       *((volatile  uint8_t *)(0x42627484UL))
#define bFM4_INTREQ_IRQ104MON_MFSINT8_STATUS      *((volatile  uint8_t *)(0x42627484UL))

#define bFM_INTREQ_IRQ105MON_MFSINT9_RX           *((volatile  uint8_t *)(0x42627500UL))
#define bFM4_INTREQ_IRQ105MON_MFSINT9_RX          *((volatile  uint8_t *)(0x42627500UL))

#define bFM_INTREQ_IRQ106MON_MFSINT9_TX           *((volatile  uint8_t *)(0x42627580UL))
#define bFM4_INTREQ_IRQ106MON_MFSINT9_TX          *((volatile  uint8_t *)(0x42627580UL))
#define bFM_INTREQ_IRQ106MON_MFSINT9_STATUS       *((volatile  uint8_t *)(0x42627584UL))
#define bFM4_INTREQ_IRQ106MON_MFSINT9_STATUS      *((volatile  uint8_t *)(0x42627584UL))

#define bFM_INTREQ_IRQ107MON_MFSINT10_RX          *((volatile  uint8_t *)(0x42627600UL))
#define bFM4_INTREQ_IRQ107MON_MFSINT10_RX         *((volatile  uint8_t *)(0x42627600UL))

#define bFM_INTREQ_IRQ108MON_MFSINT10_TX          *((volatile  uint8_t *)(0x42627680UL))
#define bFM4_INTREQ_IRQ108MON_MFSINT10_TX         *((volatile  uint8_t *)(0x42627680UL))
#define bFM_INTREQ_IRQ108MON_MFSINT10_STATUS      *((volatile  uint8_t *)(0x42627684UL))
#define bFM4_INTREQ_IRQ108MON_MFSINT10_STATUS     *((volatile  uint8_t *)(0x42627684UL))

#define bFM_INTREQ_IRQ109MON_MFSINT11_RX          *((volatile  uint8_t *)(0x42627700UL))
#define bFM4_INTREQ_IRQ109MON_MFSINT11_RX         *((volatile  uint8_t *)(0x42627700UL))

#define bFM_INTREQ_IRQ110MON_MFSINT11_TX          *((volatile  uint8_t *)(0x42627780UL))
#define bFM4_INTREQ_IRQ110MON_MFSINT11_TX         *((volatile  uint8_t *)(0x42627780UL))
#define bFM_INTREQ_IRQ110MON_MFSINT11_STATUS      *((volatile  uint8_t *)(0x42627784UL))
#define bFM4_INTREQ_IRQ110MON_MFSINT11_STATUS     *((volatile  uint8_t *)(0x42627784UL))

#define bFM_INTREQ_IRQ111MON_ADCINT0              *((volatile  uint8_t *)(0x42627800UL))
#define bFM4_INTREQ_IRQ111MON_ADCINT0             *((volatile  uint8_t *)(0x42627800UL))
#define bFM_INTREQ_IRQ111MON_ADCINT1              *((volatile  uint8_t *)(0x42627804UL))
#define bFM4_INTREQ_IRQ111MON_ADCINT1             *((volatile  uint8_t *)(0x42627804UL))
#define bFM_INTREQ_IRQ111MON_ADCINT2              *((volatile  uint8_t *)(0x42627808UL))
#define bFM4_INTREQ_IRQ111MON_ADCINT2             *((volatile  uint8_t *)(0x42627808UL))
#define bFM_INTREQ_IRQ111MON_ADCINT3              *((volatile  uint8_t *)(0x4262780CUL))
#define bFM4_INTREQ_IRQ111MON_ADCINT3             *((volatile  uint8_t *)(0x4262780CUL))
#define bFM_INTREQ_IRQ111MON_ADCINT4              *((volatile  uint8_t *)(0x42627810UL))
#define bFM4_INTREQ_IRQ111MON_ADCINT4             *((volatile  uint8_t *)(0x42627810UL))

#define bFM_INTREQ_IRQ112MON_I2SDINT0             *((volatile  uint8_t *)(0x42627880UL))
#define bFM4_INTREQ_IRQ112MON_I2SDINT0            *((volatile  uint8_t *)(0x42627880UL))
#define bFM_INTREQ_IRQ112MON_I2SDINT1             *((volatile  uint8_t *)(0x42627884UL))
#define bFM4_INTREQ_IRQ112MON_I2SDINT1            *((volatile  uint8_t *)(0x42627884UL))
#define bFM_INTREQ_IRQ112MON_HSSPIDINT0           *((volatile  uint8_t *)(0x42627888UL))
#define bFM4_INTREQ_IRQ112MON_HSSPIDINT0          *((volatile  uint8_t *)(0x42627888UL))
#define bFM_INTREQ_IRQ112MON_HSSPIDINT1           *((volatile  uint8_t *)(0x4262788CUL))
#define bFM4_INTREQ_IRQ112MON_HSSPIDINT1          *((volatile  uint8_t *)(0x4262788CUL))
#define bFM_INTREQ_IRQ112MON_PCRCDINT             *((volatile  uint8_t *)(0x42627890UL))
#define bFM4_INTREQ_IRQ112MON_PCRCDINT            *((volatile  uint8_t *)(0x42627890UL))
#define bFM_INTREQ_IRQ112MON_CANDINT              *((volatile  uint8_t *)(0x42627894UL))
#define bFM4_INTREQ_IRQ112MON_CANDINT             *((volatile  uint8_t *)(0x42627894UL))

#define bFM_INTREQ_IRQ113MON_USB_DRQ_INT0         *((volatile  uint8_t *)(0x42627900UL))
#define bFM4_INTREQ_IRQ113MON_USB_DRQ_INT0        *((volatile  uint8_t *)(0x42627900UL))
#define bFM_INTREQ_IRQ113MON_USB_DRQ_INT1         *((volatile  uint8_t *)(0x42627904UL))
#define bFM4_INTREQ_IRQ113MON_USB_DRQ_INT1        *((volatile  uint8_t *)(0x42627904UL))
#define bFM_INTREQ_IRQ113MON_USB_DRQ_INT2         *((volatile  uint8_t *)(0x42627908UL))
#define bFM4_INTREQ_IRQ113MON_USB_DRQ_INT2        *((volatile  uint8_t *)(0x42627908UL))
#define bFM_INTREQ_IRQ113MON_USB_DRQ_INT3         *((volatile  uint8_t *)(0x4262790CUL))
#define bFM4_INTREQ_IRQ113MON_USB_DRQ_INT3        *((volatile  uint8_t *)(0x4262790CUL))
#define bFM_INTREQ_IRQ113MON_USB_DRQ_INT4         *((volatile  uint8_t *)(0x42627910UL))
#define bFM4_INTREQ_IRQ113MON_USB_DRQ_INT4        *((volatile  uint8_t *)(0x42627910UL))
#define bFM_INTREQ_IRQ113MON_RCEC0INT             *((volatile  uint8_t *)(0x42627914UL))
#define bFM4_INTREQ_IRQ113MON_RCEC0INT            *((volatile  uint8_t *)(0x42627914UL))

#define bFM_INTREQ_IRQ114MON_USB_INT0             *((volatile  uint8_t *)(0x42627980UL))
#define bFM4_INTREQ_IRQ114MON_USB_INT0            *((volatile  uint8_t *)(0x42627980UL))
#define bFM_INTREQ_IRQ114MON_USB_INT1             *((volatile  uint8_t *)(0x42627984UL))
#define bFM4_INTREQ_IRQ114MON_USB_INT1            *((volatile  uint8_t *)(0x42627984UL))
#define bFM_INTREQ_IRQ114MON_USB_INT2             *((volatile  uint8_t *)(0x42627988UL))
#define bFM4_INTREQ_IRQ114MON_USB_INT2            *((volatile  uint8_t *)(0x42627988UL))
#define bFM_INTREQ_IRQ114MON_USB_INT3             *((volatile  uint8_t *)(0x4262798CUL))
#define bFM4_INTREQ_IRQ114MON_USB_INT3            *((volatile  uint8_t *)(0x4262798CUL))
#define bFM_INTREQ_IRQ114MON_USB_INT4             *((volatile  uint8_t *)(0x42627990UL))
#define bFM4_INTREQ_IRQ114MON_USB_INT4            *((volatile  uint8_t *)(0x42627990UL))
#define bFM_INTREQ_IRQ114MON_USB_INT5             *((volatile  uint8_t *)(0x42627994UL))
#define bFM4_INTREQ_IRQ114MON_USB_INT5            *((volatile  uint8_t *)(0x42627994UL))
#define bFM_INTREQ_IRQ114MON_RCEC1INT             *((volatile  uint8_t *)(0x42627998UL))
#define bFM4_INTREQ_IRQ114MON_RCEC1INT            *((volatile  uint8_t *)(0x42627998UL))

#define bFM_INTREQ_IRQ115MON_HSSPIINT0            *((volatile  uint8_t *)(0x42627A00UL))
#define bFM4_INTREQ_IRQ115MON_HSSPIINT0           *((volatile  uint8_t *)(0x42627A00UL))
#define bFM_INTREQ_IRQ115MON_HSSPIINT1            *((volatile  uint8_t *)(0x42627A04UL))
#define bFM4_INTREQ_IRQ115MON_HSSPIINT1           *((volatile  uint8_t *)(0x42627A04UL))
#define bFM_INTREQ_IRQ115MON_HSSPIINT2            *((volatile  uint8_t *)(0x42627A08UL))
#define bFM4_INTREQ_IRQ115MON_HSSPIINT2           *((volatile  uint8_t *)(0x42627A08UL))

#define bFM_INTREQ_IRQ117MON_I2SINT               *((volatile  uint8_t *)(0x42627B00UL))
#define bFM4_INTREQ_IRQ117MON_I2SINT              *((volatile  uint8_t *)(0x42627B00UL))
#define bFM_INTREQ_IRQ117MON_PCRC                 *((volatile  uint8_t *)(0x42627B04UL))
#define bFM4_INTREQ_IRQ117MON_PCRC                *((volatile  uint8_t *)(0x42627B04UL))

#define bFM_INTREQ_IRQ118MON_SDINT0               *((volatile  uint8_t *)(0x42627B80UL))
#define bFM4_INTREQ_IRQ118MON_SDINT0              *((volatile  uint8_t *)(0x42627B80UL))
#define bFM_INTREQ_IRQ118MON_SDINT1               *((volatile  uint8_t *)(0x42627B84UL))
#define bFM4_INTREQ_IRQ118MON_SDINT1              *((volatile  uint8_t *)(0x42627B84UL))

#define bFM_INTREQ_IRQ119MON_FLINT                *((volatile  uint8_t *)(0x42627C00UL))
#define bFM4_INTREQ_IRQ119MON_FLINT               *((volatile  uint8_t *)(0x42627C00UL))

#define bFM_INTREQ_IRQ120MON_MFSINT12_RX          *((volatile  uint8_t *)(0x42627C80UL))
#define bFM4_INTREQ_IRQ120MON_MFSINT12_RX         *((volatile  uint8_t *)(0x42627C80UL))

#define bFM_INTREQ_IRQ121MON_MFSINT12_TX          *((volatile  uint8_t *)(0x42627D00UL))
#define bFM4_INTREQ_IRQ121MON_MFSINT12_TX         *((volatile  uint8_t *)(0x42627D00UL))
#define bFM_INTREQ_IRQ121MON_MFSINT12_STATUS      *((volatile  uint8_t *)(0x42627D04UL))
#define bFM4_INTREQ_IRQ121MON_MFSINT12_STATUS     *((volatile  uint8_t *)(0x42627D04UL))

#define bFM_INTREQ_IRQ122MON_MFSINT13_RX          *((volatile  uint8_t *)(0x42627D80UL))
#define bFM4_INTREQ_IRQ122MON_MFSINT13_RX         *((volatile  uint8_t *)(0x42627D80UL))

#define bFM_INTREQ_IRQ123MON_MFSINT13_TX          *((volatile  uint8_t *)(0x42627E00UL))
#define bFM4_INTREQ_IRQ123MON_MFSINT13_TX         *((volatile  uint8_t *)(0x42627E00UL))
#define bFM_INTREQ_IRQ123MON_MFSINT13_STATUS      *((volatile  uint8_t *)(0x42627E04UL))
#define bFM4_INTREQ_IRQ123MON_MFSINT13_STATUS     *((volatile  uint8_t *)(0x42627E04UL))

#define bFM_INTREQ_IRQ124MON_MFSINT14_RX          *((volatile  uint8_t *)(0x42627E80UL))
#define bFM4_INTREQ_IRQ124MON_MFSINT14_RX         *((volatile  uint8_t *)(0x42627E80UL))

#define bFM_INTREQ_IRQ125MON_MFSINT14_TX          *((volatile  uint8_t *)(0x42627F00UL))
#define bFM4_INTREQ_IRQ125MON_MFSINT14_TX         *((volatile  uint8_t *)(0x42627F00UL))
#define bFM_INTREQ_IRQ125MON_MFSINT14_STATUS      *((volatile  uint8_t *)(0x42627F04UL))
#define bFM4_INTREQ_IRQ125MON_MFSINT14_STATUS     *((volatile  uint8_t *)(0x42627F04UL))

#define bFM_INTREQ_IRQ126MON_MFSINT15_RX          *((volatile  uint8_t *)(0x42627F80UL))
#define bFM4_INTREQ_IRQ126MON_MFSINT15_RX         *((volatile  uint8_t *)(0x42627F80UL))

#define bFM_INTREQ_IRQ127MON_MFSINT15_TX          *((volatile  uint8_t *)(0x42628000UL))
#define bFM4_INTREQ_IRQ127MON_MFSINT15_TX         *((volatile  uint8_t *)(0x42628000UL))
#define bFM_INTREQ_IRQ127MON_MFSINT15_STATUS      *((volatile  uint8_t *)(0x42628004UL))
#define bFM4_INTREQ_IRQ127MON_MFSINT15_STATUS     *((volatile  uint8_t *)(0x42628004UL))

#define bFM_INTREQ_ODDPKS_ODDPKS0                 *((volatile  uint8_t *)(0x42620200UL))
#define bFM4_INTREQ_ODDPKS_ODDPKS0                *((volatile  uint8_t *)(0x42620200UL))
#define bFM_INTREQ_ODDPKS_ODDPKS1                 *((volatile  uint8_t *)(0x42620204UL))
#define bFM4_INTREQ_ODDPKS_ODDPKS1                *((volatile  uint8_t *)(0x42620204UL))
#define bFM_INTREQ_ODDPKS_ODDPKS2                 *((volatile  uint8_t *)(0x42620208UL))
#define bFM4_INTREQ_ODDPKS_ODDPKS2                *((volatile  uint8_t *)(0x42620208UL))
#define bFM_INTREQ_ODDPKS_ODDPKS3                 *((volatile  uint8_t *)(0x4262020CUL))
#define bFM4_INTREQ_ODDPKS_ODDPKS3                *((volatile  uint8_t *)(0x4262020CUL))
#define bFM_INTREQ_ODDPKS_ODDPKS4                 *((volatile  uint8_t *)(0x42620210UL))
#define bFM4_INTREQ_ODDPKS_ODDPKS4                *((volatile  uint8_t *)(0x42620210UL))

#define bFM_INTREQ_ODDPKS1_ODDPKS10               *((volatile  uint8_t *)(0x42620280UL))
#define bFM4_INTREQ_ODDPKS1_ODDPKS10              *((volatile  uint8_t *)(0x42620280UL))
#define bFM_INTREQ_ODDPKS1_ODDPKS11               *((volatile  uint8_t *)(0x42620284UL))
#define bFM4_INTREQ_ODDPKS1_ODDPKS11              *((volatile  uint8_t *)(0x42620284UL))
#define bFM_INTREQ_ODDPKS1_ODDPKS12               *((volatile  uint8_t *)(0x42620288UL))
#define bFM4_INTREQ_ODDPKS1_ODDPKS12              *((volatile  uint8_t *)(0x42620288UL))
#define bFM_INTREQ_ODDPKS1_ODDPKS13               *((volatile  uint8_t *)(0x4262028CUL))
#define bFM4_INTREQ_ODDPKS1_ODDPKS13              *((volatile  uint8_t *)(0x4262028CUL))
#define bFM_INTREQ_ODDPKS1_ODDPKS14               *((volatile  uint8_t *)(0x42620290UL))
#define bFM4_INTREQ_ODDPKS1_ODDPKS14              *((volatile  uint8_t *)(0x42620290UL))


/*******************************************************************************
* LSCRP Registers LSCRP
*   Bitband Section
*******************************************************************************/

/*******************************************************************************
* LVD Registers LVD
*   Bitband Section
*******************************************************************************/
#define bFM_LVD_LVD_CLR_LVDCL                     *((volatile  uint8_t *)(0x426A011CUL))
#define bFM4_LVD_LVD_CLR_LVDCL                    *((volatile  uint8_t *)(0x426A011CUL))

#define bFM_LVD_LVD_CTL_LVDIE                     *((volatile  uint8_t *)(0x426A001CUL))
#define bFM4_LVD_LVD_CTL_LVDIE                    *((volatile  uint8_t *)(0x426A001CUL))

#define bFM_LVD_LVD_STR_LVDIR                     *((volatile  uint8_t *)(0x426A009CUL))
#define bFM4_LVD_LVD_STR_LVDIR                    *((volatile  uint8_t *)(0x426A009CUL))

#define bFM_LVD_LVD_STR2_LVDIRDY                  *((volatile  uint8_t *)(0x426A021CUL))
#define bFM4_LVD_LVD_STR2_LVDIRDY                 *((volatile  uint8_t *)(0x426A021CUL))


/*******************************************************************************
* MFS Registers MFS0
*   Bitband Section
*******************************************************************************/
#define bFM_MFS0_CSIO_ESCR_CSFE                   *((volatile  uint8_t *)(0x42700094UL))
#define bFM4_MFS0_CSIO_ESCR_CSFE                  *((volatile  uint8_t *)(0x42700094UL))
#define bFM_MFS0_CSIO_ESCR_L3                     *((volatile  uint8_t *)(0x42700098UL))
#define bFM4_MFS0_CSIO_ESCR_L3                    *((volatile  uint8_t *)(0x42700098UL))
#define bFM_MFS0_CSIO_ESCR_SOP                    *((volatile  uint8_t *)(0x4270009CUL))
#define bFM4_MFS0_CSIO_ESCR_SOP                   *((volatile  uint8_t *)(0x4270009CUL))

#define bFM_MFS0_CSIO_FCR_FE1                     *((volatile  uint8_t *)(0x42700280UL))
#define bFM4_MFS0_CSIO_FCR_FE1                    *((volatile  uint8_t *)(0x42700280UL))
#define bFM_MFS0_CSIO_FCR_FE2                     *((volatile  uint8_t *)(0x42700284UL))
#define bFM4_MFS0_CSIO_FCR_FE2                    *((volatile  uint8_t *)(0x42700284UL))
#define bFM_MFS0_CSIO_FCR_FCL1                    *((volatile  uint8_t *)(0x42700288UL))
#define bFM4_MFS0_CSIO_FCR_FCL1                   *((volatile  uint8_t *)(0x42700288UL))
#define bFM_MFS0_CSIO_FCR_FCL2                    *((volatile  uint8_t *)(0x4270028CUL))
#define bFM4_MFS0_CSIO_FCR_FCL2                   *((volatile  uint8_t *)(0x4270028CUL))
#define bFM_MFS0_CSIO_FCR_FSET                    *((volatile  uint8_t *)(0x42700290UL))
#define bFM4_MFS0_CSIO_FCR_FSET                   *((volatile  uint8_t *)(0x42700290UL))
#define bFM_MFS0_CSIO_FCR_FLD                     *((volatile  uint8_t *)(0x42700294UL))
#define bFM4_MFS0_CSIO_FCR_FLD                    *((volatile  uint8_t *)(0x42700294UL))
#define bFM_MFS0_CSIO_FCR_FLST                    *((volatile  uint8_t *)(0x42700298UL))
#define bFM4_MFS0_CSIO_FCR_FLST                   *((volatile  uint8_t *)(0x42700298UL))
#define bFM_MFS0_CSIO_FCR_FSEL                    *((volatile  uint8_t *)(0x427002A0UL))
#define bFM4_MFS0_CSIO_FCR_FSEL                   *((volatile  uint8_t *)(0x427002A0UL))
#define bFM_MFS0_CSIO_FCR_FTIE                    *((volatile  uint8_t *)(0x427002A4UL))
#define bFM4_MFS0_CSIO_FCR_FTIE                   *((volatile  uint8_t *)(0x427002A4UL))
#define bFM_MFS0_CSIO_FCR_FDRQ                    *((volatile  uint8_t *)(0x427002A8UL))
#define bFM4_MFS0_CSIO_FCR_FDRQ                   *((volatile  uint8_t *)(0x427002A8UL))
#define bFM_MFS0_CSIO_FCR_FRIIE                   *((volatile  uint8_t *)(0x427002ACUL))
#define bFM4_MFS0_CSIO_FCR_FRIIE                  *((volatile  uint8_t *)(0x427002ACUL))
#define bFM_MFS0_CSIO_FCR_FLSTE                   *((volatile  uint8_t *)(0x427002B0UL))
#define bFM4_MFS0_CSIO_FCR_FLSTE                  *((volatile  uint8_t *)(0x427002B0UL))

#define bFM_MFS0_CSIO_SACSR_TMRE                  *((volatile  uint8_t *)(0x42700480UL))
#define bFM4_MFS0_CSIO_SACSR_TMRE                 *((volatile  uint8_t *)(0x42700480UL))
#define bFM_MFS0_CSIO_SACSR_TSYNE                 *((volatile  uint8_t *)(0x42700498UL))
#define bFM4_MFS0_CSIO_SACSR_TSYNE                *((volatile  uint8_t *)(0x42700498UL))
#define bFM_MFS0_CSIO_SACSR_TINTE                 *((volatile  uint8_t *)(0x4270049CUL))
#define bFM4_MFS0_CSIO_SACSR_TINTE                *((volatile  uint8_t *)(0x4270049CUL))
#define bFM_MFS0_CSIO_SACSR_TINT                  *((volatile  uint8_t *)(0x427004A0UL))
#define bFM4_MFS0_CSIO_SACSR_TINT                 *((volatile  uint8_t *)(0x427004A0UL))
#define bFM_MFS0_CSIO_SACSR_CSE                   *((volatile  uint8_t *)(0x427004ACUL))
#define bFM4_MFS0_CSIO_SACSR_CSE                  *((volatile  uint8_t *)(0x427004ACUL))
#define bFM_MFS0_CSIO_SACSR_CSEIE                 *((volatile  uint8_t *)(0x427004B0UL))
#define bFM4_MFS0_CSIO_SACSR_CSEIE                *((volatile  uint8_t *)(0x427004B0UL))
#define bFM_MFS0_CSIO_SACSR_TBEEN                 *((volatile  uint8_t *)(0x427004B4UL))
#define bFM4_MFS0_CSIO_SACSR_TBEEN                *((volatile  uint8_t *)(0x427004B4UL))

#define bFM_MFS0_CSIO_SCR_TXE                     *((volatile  uint8_t *)(0x42700020UL))
#define bFM4_MFS0_CSIO_SCR_TXE                    *((volatile  uint8_t *)(0x42700020UL))
#define bFM_MFS0_CSIO_SCR_RXE                     *((volatile  uint8_t *)(0x42700024UL))
#define bFM4_MFS0_CSIO_SCR_RXE                    *((volatile  uint8_t *)(0x42700024UL))
#define bFM_MFS0_CSIO_SCR_TBIE                    *((volatile  uint8_t *)(0x42700028UL))
#define bFM4_MFS0_CSIO_SCR_TBIE                   *((volatile  uint8_t *)(0x42700028UL))
#define bFM_MFS0_CSIO_SCR_TIE                     *((volatile  uint8_t *)(0x4270002CUL))
#define bFM4_MFS0_CSIO_SCR_TIE                    *((volatile  uint8_t *)(0x4270002CUL))
#define bFM_MFS0_CSIO_SCR_RIE                     *((volatile  uint8_t *)(0x42700030UL))
#define bFM4_MFS0_CSIO_SCR_RIE                    *((volatile  uint8_t *)(0x42700030UL))
#define bFM_MFS0_CSIO_SCR_SPI                     *((volatile  uint8_t *)(0x42700034UL))
#define bFM4_MFS0_CSIO_SCR_SPI                    *((volatile  uint8_t *)(0x42700034UL))
#define bFM_MFS0_CSIO_SCR_MS                      *((volatile  uint8_t *)(0x42700038UL))
#define bFM4_MFS0_CSIO_SCR_MS                     *((volatile  uint8_t *)(0x42700038UL))
#define bFM_MFS0_CSIO_SCR_UPCL                    *((volatile  uint8_t *)(0x4270003CUL))
#define bFM4_MFS0_CSIO_SCR_UPCL                   *((volatile  uint8_t *)(0x4270003CUL))

#define bFM_MFS0_CSIO_SCSCR_CSOE                  *((volatile  uint8_t *)(0x42700600UL))
#define bFM4_MFS0_CSIO_SCSCR_CSOE                 *((volatile  uint8_t *)(0x42700600UL))
#define bFM_MFS0_CSIO_SCSCR_CSEN0                 *((volatile  uint8_t *)(0x42700604UL))
#define bFM4_MFS0_CSIO_SCSCR_CSEN0                *((volatile  uint8_t *)(0x42700604UL))
#define bFM_MFS0_CSIO_SCSCR_CSEN1                 *((volatile  uint8_t *)(0x42700608UL))
#define bFM4_MFS0_CSIO_SCSCR_CSEN1                *((volatile  uint8_t *)(0x42700608UL))
#define bFM_MFS0_CSIO_SCSCR_CSEN2                 *((volatile  uint8_t *)(0x4270060CUL))
#define bFM4_MFS0_CSIO_SCSCR_CSEN2                *((volatile  uint8_t *)(0x4270060CUL))
#define bFM_MFS0_CSIO_SCSCR_CSEN3                 *((volatile  uint8_t *)(0x42700610UL))
#define bFM4_MFS0_CSIO_SCSCR_CSEN3                *((volatile  uint8_t *)(0x42700610UL))
#define bFM_MFS0_CSIO_SCSCR_CSLVL                 *((volatile  uint8_t *)(0x42700614UL))
#define bFM4_MFS0_CSIO_SCSCR_CSLVL                *((volatile  uint8_t *)(0x42700614UL))
#define bFM_MFS0_CSIO_SCSCR_SCAM                  *((volatile  uint8_t *)(0x42700624UL))
#define bFM4_MFS0_CSIO_SCSCR_SCAM                 *((volatile  uint8_t *)(0x42700624UL))

#define bFM_MFS0_CSIO_SCSFR0_CS1SPI               *((volatile  uint8_t *)(0x42700694UL))
#define bFM4_MFS0_CSIO_SCSFR0_CS1SPI              *((volatile  uint8_t *)(0x42700694UL))
#define bFM_MFS0_CSIO_SCSFR0_CS1SCINV             *((volatile  uint8_t *)(0x42700698UL))
#define bFM4_MFS0_CSIO_SCSFR0_CS1SCINV            *((volatile  uint8_t *)(0x42700698UL))
#define bFM_MFS0_CSIO_SCSFR0_CS1CSLVL             *((volatile  uint8_t *)(0x4270069CUL))
#define bFM4_MFS0_CSIO_SCSFR0_CS1CSLVL            *((volatile  uint8_t *)(0x4270069CUL))

#define bFM_MFS0_CSIO_SCSFR1_CS2SPI               *((volatile  uint8_t *)(0x427006B4UL))
#define bFM4_MFS0_CSIO_SCSFR1_CS2SPI              *((volatile  uint8_t *)(0x427006B4UL))
#define bFM_MFS0_CSIO_SCSFR1_CS2SCINV             *((volatile  uint8_t *)(0x427006B8UL))
#define bFM4_MFS0_CSIO_SCSFR1_CS2SCINV            *((volatile  uint8_t *)(0x427006B8UL))
#define bFM_MFS0_CSIO_SCSFR1_CS2CSLVL             *((volatile  uint8_t *)(0x427006BCUL))
#define bFM4_MFS0_CSIO_SCSFR1_CS2CSLVL            *((volatile  uint8_t *)(0x427006BCUL))

#define bFM_MFS0_CSIO_SCSFR2_CS3SPI               *((volatile  uint8_t *)(0x42700714UL))
#define bFM4_MFS0_CSIO_SCSFR2_CS3SPI              *((volatile  uint8_t *)(0x42700714UL))
#define bFM_MFS0_CSIO_SCSFR2_CS3SCINV             *((volatile  uint8_t *)(0x42700718UL))
#define bFM4_MFS0_CSIO_SCSFR2_CS3SCINV            *((volatile  uint8_t *)(0x42700718UL))
#define bFM_MFS0_CSIO_SCSFR2_CS3CSLVL             *((volatile  uint8_t *)(0x4270071CUL))
#define bFM4_MFS0_CSIO_SCSFR2_CS3CSLVL            *((volatile  uint8_t *)(0x4270071CUL))

#define bFM_MFS0_CSIO_SMR_SOE                     *((volatile  uint8_t *)(0x42700000UL))
#define bFM4_MFS0_CSIO_SMR_SOE                    *((volatile  uint8_t *)(0x42700000UL))
#define bFM_MFS0_CSIO_SMR_SCKE                    *((volatile  uint8_t *)(0x42700004UL))
#define bFM4_MFS0_CSIO_SMR_SCKE                   *((volatile  uint8_t *)(0x42700004UL))
#define bFM_MFS0_CSIO_SMR_BDS                     *((volatile  uint8_t *)(0x42700008UL))
#define bFM4_MFS0_CSIO_SMR_BDS                    *((volatile  uint8_t *)(0x42700008UL))
#define bFM_MFS0_CSIO_SMR_SCINV                   *((volatile  uint8_t *)(0x4270000CUL))
#define bFM4_MFS0_CSIO_SMR_SCINV                  *((volatile  uint8_t *)(0x4270000CUL))

#define bFM_MFS0_CSIO_SSR_TBI                     *((volatile  uint8_t *)(0x427000A0UL))
#define bFM4_MFS0_CSIO_SSR_TBI                    *((volatile  uint8_t *)(0x427000A0UL))
#define bFM_MFS0_CSIO_SSR_TDRE                    *((volatile  uint8_t *)(0x427000A4UL))
#define bFM4_MFS0_CSIO_SSR_TDRE                   *((volatile  uint8_t *)(0x427000A4UL))
#define bFM_MFS0_CSIO_SSR_RDRF                    *((volatile  uint8_t *)(0x427000A8UL))
#define bFM4_MFS0_CSIO_SSR_RDRF                   *((volatile  uint8_t *)(0x427000A8UL))
#define bFM_MFS0_CSIO_SSR_ORE                     *((volatile  uint8_t *)(0x427000ACUL))
#define bFM4_MFS0_CSIO_SSR_ORE                    *((volatile  uint8_t *)(0x427000ACUL))
#define bFM_MFS0_CSIO_SSR_AWC                     *((volatile  uint8_t *)(0x427000B0UL))
#define bFM4_MFS0_CSIO_SSR_AWC                    *((volatile  uint8_t *)(0x427000B0UL))
#define bFM_MFS0_CSIO_SSR_REC                     *((volatile  uint8_t *)(0x427000BCUL))
#define bFM4_MFS0_CSIO_SSR_REC                    *((volatile  uint8_t *)(0x427000BCUL))

#define bFM_MFS0_I2C_EIBCR_BEC                    *((volatile  uint8_t *)(0x427003A0UL))
#define bFM4_MFS0_I2C_EIBCR_BEC                   *((volatile  uint8_t *)(0x427003A0UL))
#define bFM_MFS0_I2C_EIBCR_SOCE                   *((volatile  uint8_t *)(0x427003A4UL))
#define bFM4_MFS0_I2C_EIBCR_SOCE                  *((volatile  uint8_t *)(0x427003A4UL))
#define bFM_MFS0_I2C_EIBCR_SCLC                   *((volatile  uint8_t *)(0x427003A8UL))
#define bFM4_MFS0_I2C_EIBCR_SCLC                  *((volatile  uint8_t *)(0x427003A8UL))
#define bFM_MFS0_I2C_EIBCR_SDAC                   *((volatile  uint8_t *)(0x427003ACUL))
#define bFM4_MFS0_I2C_EIBCR_SDAC                  *((volatile  uint8_t *)(0x427003ACUL))
#define bFM_MFS0_I2C_EIBCR_SCLS                   *((volatile  uint8_t *)(0x427003B0UL))
#define bFM4_MFS0_I2C_EIBCR_SCLS                  *((volatile  uint8_t *)(0x427003B0UL))
#define bFM_MFS0_I2C_EIBCR_SDAS                   *((volatile  uint8_t *)(0x427003B4UL))
#define bFM4_MFS0_I2C_EIBCR_SDAS                  *((volatile  uint8_t *)(0x427003B4UL))

#define bFM_MFS0_I2C_FCR_FE1                      *((volatile  uint8_t *)(0x42700280UL))
#define bFM4_MFS0_I2C_FCR_FE1                     *((volatile  uint8_t *)(0x42700280UL))
#define bFM_MFS0_I2C_FCR_FE2                      *((volatile  uint8_t *)(0x42700284UL))
#define bFM4_MFS0_I2C_FCR_FE2                     *((volatile  uint8_t *)(0x42700284UL))
#define bFM_MFS0_I2C_FCR_FCL1                     *((volatile  uint8_t *)(0x42700288UL))
#define bFM4_MFS0_I2C_FCR_FCL1                    *((volatile  uint8_t *)(0x42700288UL))
#define bFM_MFS0_I2C_FCR_FCL2                     *((volatile  uint8_t *)(0x4270028CUL))
#define bFM4_MFS0_I2C_FCR_FCL2                    *((volatile  uint8_t *)(0x4270028CUL))
#define bFM_MFS0_I2C_FCR_FSET                     *((volatile  uint8_t *)(0x42700290UL))
#define bFM4_MFS0_I2C_FCR_FSET                    *((volatile  uint8_t *)(0x42700290UL))
#define bFM_MFS0_I2C_FCR_FLD                      *((volatile  uint8_t *)(0x42700294UL))
#define bFM4_MFS0_I2C_FCR_FLD                     *((volatile  uint8_t *)(0x42700294UL))
#define bFM_MFS0_I2C_FCR_FLST                     *((volatile  uint8_t *)(0x42700298UL))
#define bFM4_MFS0_I2C_FCR_FLST                    *((volatile  uint8_t *)(0x42700298UL))
#define bFM_MFS0_I2C_FCR_FSEL                     *((volatile  uint8_t *)(0x427002A0UL))
#define bFM4_MFS0_I2C_FCR_FSEL                    *((volatile  uint8_t *)(0x427002A0UL))
#define bFM_MFS0_I2C_FCR_FTIE                     *((volatile  uint8_t *)(0x427002A4UL))
#define bFM4_MFS0_I2C_FCR_FTIE                    *((volatile  uint8_t *)(0x427002A4UL))
#define bFM_MFS0_I2C_FCR_FDRQ                     *((volatile  uint8_t *)(0x427002A8UL))
#define bFM4_MFS0_I2C_FCR_FDRQ                    *((volatile  uint8_t *)(0x427002A8UL))
#define bFM_MFS0_I2C_FCR_FRIIE                    *((volatile  uint8_t *)(0x427002ACUL))
#define bFM4_MFS0_I2C_FCR_FRIIE                   *((volatile  uint8_t *)(0x427002ACUL))
#define bFM_MFS0_I2C_FCR_FLSTE                    *((volatile  uint8_t *)(0x427002B0UL))
#define bFM4_MFS0_I2C_FCR_FLSTE                   *((volatile  uint8_t *)(0x427002B0UL))

#define bFM_MFS0_I2C_IBCR_INT                     *((volatile  uint8_t *)(0x42700020UL))
#define bFM4_MFS0_I2C_IBCR_INT                    *((volatile  uint8_t *)(0x42700020UL))
#define bFM_MFS0_I2C_IBCR_BER                     *((volatile  uint8_t *)(0x42700024UL))
#define bFM4_MFS0_I2C_IBCR_BER                    *((volatile  uint8_t *)(0x42700024UL))
#define bFM_MFS0_I2C_IBCR_INTE                    *((volatile  uint8_t *)(0x42700028UL))
#define bFM4_MFS0_I2C_IBCR_INTE                   *((volatile  uint8_t *)(0x42700028UL))
#define bFM_MFS0_I2C_IBCR_CNDE                    *((volatile  uint8_t *)(0x4270002CUL))
#define bFM4_MFS0_I2C_IBCR_CNDE                   *((volatile  uint8_t *)(0x4270002CUL))
#define bFM_MFS0_I2C_IBCR_WSEL                    *((volatile  uint8_t *)(0x42700030UL))
#define bFM4_MFS0_I2C_IBCR_WSEL                   *((volatile  uint8_t *)(0x42700030UL))
#define bFM_MFS0_I2C_IBCR_ACKE                    *((volatile  uint8_t *)(0x42700034UL))
#define bFM4_MFS0_I2C_IBCR_ACKE                   *((volatile  uint8_t *)(0x42700034UL))
#define bFM_MFS0_I2C_IBCR_ACT_SCC                 *((volatile  uint8_t *)(0x42700038UL))
#define bFM4_MFS0_I2C_IBCR_ACT_SCC                *((volatile  uint8_t *)(0x42700038UL))
#define bFM_MFS0_I2C_IBCR_MSS                     *((volatile  uint8_t *)(0x4270003CUL))
#define bFM4_MFS0_I2C_IBCR_MSS                    *((volatile  uint8_t *)(0x4270003CUL))

#define bFM_MFS0_I2C_IBSR_BB                      *((volatile  uint8_t *)(0x42700080UL))
#define bFM4_MFS0_I2C_IBSR_BB                     *((volatile  uint8_t *)(0x42700080UL))
#define bFM_MFS0_I2C_IBSR_SPC                     *((volatile  uint8_t *)(0x42700084UL))
#define bFM4_MFS0_I2C_IBSR_SPC                    *((volatile  uint8_t *)(0x42700084UL))
#define bFM_MFS0_I2C_IBSR_RSC                     *((volatile  uint8_t *)(0x42700088UL))
#define bFM4_MFS0_I2C_IBSR_RSC                    *((volatile  uint8_t *)(0x42700088UL))
#define bFM_MFS0_I2C_IBSR_AL                      *((volatile  uint8_t *)(0x4270008CUL))
#define bFM4_MFS0_I2C_IBSR_AL                     *((volatile  uint8_t *)(0x4270008CUL))
#define bFM_MFS0_I2C_IBSR_TRX                     *((volatile  uint8_t *)(0x42700090UL))
#define bFM4_MFS0_I2C_IBSR_TRX                    *((volatile  uint8_t *)(0x42700090UL))
#define bFM_MFS0_I2C_IBSR_RSA                     *((volatile  uint8_t *)(0x42700094UL))
#define bFM4_MFS0_I2C_IBSR_RSA                    *((volatile  uint8_t *)(0x42700094UL))
#define bFM_MFS0_I2C_IBSR_RACK                    *((volatile  uint8_t *)(0x42700098UL))
#define bFM4_MFS0_I2C_IBSR_RACK                   *((volatile  uint8_t *)(0x42700098UL))
#define bFM_MFS0_I2C_IBSR_FBT                     *((volatile  uint8_t *)(0x4270009CUL))
#define bFM4_MFS0_I2C_IBSR_FBT                    *((volatile  uint8_t *)(0x4270009CUL))

#define bFM_MFS0_I2C_ISBA_SAEN                    *((volatile  uint8_t *)(0x4270021CUL))
#define bFM4_MFS0_I2C_ISBA_SAEN                   *((volatile  uint8_t *)(0x4270021CUL))

#define bFM_MFS0_I2C_ISMK_EN                      *((volatile  uint8_t *)(0x4270023CUL))
#define bFM4_MFS0_I2C_ISMK_EN                     *((volatile  uint8_t *)(0x4270023CUL))

#define bFM_MFS0_I2C_SMR_TIE                      *((volatile  uint8_t *)(0x42700008UL))
#define bFM4_MFS0_I2C_SMR_TIE                     *((volatile  uint8_t *)(0x42700008UL))
#define bFM_MFS0_I2C_SMR_RIE                      *((volatile  uint8_t *)(0x4270000CUL))
#define bFM4_MFS0_I2C_SMR_RIE                     *((volatile  uint8_t *)(0x4270000CUL))

#define bFM_MFS0_I2C_SSR_TBI                      *((volatile  uint8_t *)(0x427000A0UL))
#define bFM4_MFS0_I2C_SSR_TBI                     *((volatile  uint8_t *)(0x427000A0UL))
#define bFM_MFS0_I2C_SSR_TDRE                     *((volatile  uint8_t *)(0x427000A4UL))
#define bFM4_MFS0_I2C_SSR_TDRE                    *((volatile  uint8_t *)(0x427000A4UL))
#define bFM_MFS0_I2C_SSR_RDRF                     *((volatile  uint8_t *)(0x427000A8UL))
#define bFM4_MFS0_I2C_SSR_RDRF                    *((volatile  uint8_t *)(0x427000A8UL))
#define bFM_MFS0_I2C_SSR_ORE                      *((volatile  uint8_t *)(0x427000ACUL))
#define bFM4_MFS0_I2C_SSR_ORE                     *((volatile  uint8_t *)(0x427000ACUL))
#define bFM_MFS0_I2C_SSR_TBIE                     *((volatile  uint8_t *)(0x427000B0UL))
#define bFM4_MFS0_I2C_SSR_TBIE                    *((volatile  uint8_t *)(0x427000B0UL))
#define bFM_MFS0_I2C_SSR_DMA                      *((volatile  uint8_t *)(0x427000B4UL))
#define bFM4_MFS0_I2C_SSR_DMA                     *((volatile  uint8_t *)(0x427000B4UL))
#define bFM_MFS0_I2C_SSR_TSET                     *((volatile  uint8_t *)(0x427000B8UL))
#define bFM4_MFS0_I2C_SSR_TSET                    *((volatile  uint8_t *)(0x427000B8UL))
#define bFM_MFS0_I2C_SSR_REC                      *((volatile  uint8_t *)(0x427000BCUL))
#define bFM4_MFS0_I2C_SSR_REC                     *((volatile  uint8_t *)(0x427000BCUL))

#define bFM_MFS0_LIN_BGR_EXT                      *((volatile  uint8_t *)(0x427001BCUL))
#define bFM4_MFS0_LIN_BGR_EXT                     *((volatile  uint8_t *)(0x427001BCUL))

#define bFM_MFS0_LIN_ESCR_LBIE                    *((volatile  uint8_t *)(0x42700090UL))
#define bFM4_MFS0_LIN_ESCR_LBIE                   *((volatile  uint8_t *)(0x42700090UL))
#define bFM_MFS0_LIN_ESCR_ESBL                    *((volatile  uint8_t *)(0x42700098UL))
#define bFM4_MFS0_LIN_ESCR_ESBL                   *((volatile  uint8_t *)(0x42700098UL))

#define bFM_MFS0_LIN_FCR_FE1                      *((volatile  uint8_t *)(0x42700280UL))
#define bFM4_MFS0_LIN_FCR_FE1                     *((volatile  uint8_t *)(0x42700280UL))
#define bFM_MFS0_LIN_FCR_FE2                      *((volatile  uint8_t *)(0x42700284UL))
#define bFM4_MFS0_LIN_FCR_FE2                     *((volatile  uint8_t *)(0x42700284UL))
#define bFM_MFS0_LIN_FCR_FCL1                     *((volatile  uint8_t *)(0x42700288UL))
#define bFM4_MFS0_LIN_FCR_FCL1                    *((volatile  uint8_t *)(0x42700288UL))
#define bFM_MFS0_LIN_FCR_FCL2                     *((volatile  uint8_t *)(0x4270028CUL))
#define bFM4_MFS0_LIN_FCR_FCL2                    *((volatile  uint8_t *)(0x4270028CUL))
#define bFM_MFS0_LIN_FCR_FSET                     *((volatile  uint8_t *)(0x42700290UL))
#define bFM4_MFS0_LIN_FCR_FSET                    *((volatile  uint8_t *)(0x42700290UL))
#define bFM_MFS0_LIN_FCR_FLD                      *((volatile  uint8_t *)(0x42700294UL))
#define bFM4_MFS0_LIN_FCR_FLD                     *((volatile  uint8_t *)(0x42700294UL))
#define bFM_MFS0_LIN_FCR_FLST                     *((volatile  uint8_t *)(0x42700298UL))
#define bFM4_MFS0_LIN_FCR_FLST                    *((volatile  uint8_t *)(0x42700298UL))
#define bFM_MFS0_LIN_FCR_FSEL                     *((volatile  uint8_t *)(0x427002A0UL))
#define bFM4_MFS0_LIN_FCR_FSEL                    *((volatile  uint8_t *)(0x427002A0UL))
#define bFM_MFS0_LIN_FCR_FTIE                     *((volatile  uint8_t *)(0x427002A4UL))
#define bFM4_MFS0_LIN_FCR_FTIE                    *((volatile  uint8_t *)(0x427002A4UL))
#define bFM_MFS0_LIN_FCR_FDRQ                     *((volatile  uint8_t *)(0x427002A8UL))
#define bFM4_MFS0_LIN_FCR_FDRQ                    *((volatile  uint8_t *)(0x427002A8UL))
#define bFM_MFS0_LIN_FCR_FRIIE                    *((volatile  uint8_t *)(0x427002ACUL))
#define bFM4_MFS0_LIN_FCR_FRIIE                   *((volatile  uint8_t *)(0x427002ACUL))
#define bFM_MFS0_LIN_FCR_FLSTE                    *((volatile  uint8_t *)(0x427002B0UL))
#define bFM4_MFS0_LIN_FCR_FLSTE                   *((volatile  uint8_t *)(0x427002B0UL))

#define bFM_MFS0_LIN_SCR_TXE                      *((volatile  uint8_t *)(0x42700020UL))
#define bFM4_MFS0_LIN_SCR_TXE                     *((volatile  uint8_t *)(0x42700020UL))
#define bFM_MFS0_LIN_SCR_RXE                      *((volatile  uint8_t *)(0x42700024UL))
#define bFM4_MFS0_LIN_SCR_RXE                     *((volatile  uint8_t *)(0x42700024UL))
#define bFM_MFS0_LIN_SCR_TBIE                     *((volatile  uint8_t *)(0x42700028UL))
#define bFM4_MFS0_LIN_SCR_TBIE                    *((volatile  uint8_t *)(0x42700028UL))
#define bFM_MFS0_LIN_SCR_TIE                      *((volatile  uint8_t *)(0x4270002CUL))
#define bFM4_MFS0_LIN_SCR_TIE                     *((volatile  uint8_t *)(0x4270002CUL))
#define bFM_MFS0_LIN_SCR_RIE                      *((volatile  uint8_t *)(0x42700030UL))
#define bFM4_MFS0_LIN_SCR_RIE                     *((volatile  uint8_t *)(0x42700030UL))
#define bFM_MFS0_LIN_SCR_LBR                      *((volatile  uint8_t *)(0x42700034UL))
#define bFM4_MFS0_LIN_SCR_LBR                     *((volatile  uint8_t *)(0x42700034UL))
#define bFM_MFS0_LIN_SCR_MS                       *((volatile  uint8_t *)(0x42700038UL))
#define bFM4_MFS0_LIN_SCR_MS                      *((volatile  uint8_t *)(0x42700038UL))
#define bFM_MFS0_LIN_SCR_UPCL                     *((volatile  uint8_t *)(0x4270003CUL))
#define bFM4_MFS0_LIN_SCR_UPCL                    *((volatile  uint8_t *)(0x4270003CUL))

#define bFM_MFS0_LIN_SMR_SOE                      *((volatile  uint8_t *)(0x42700000UL))
#define bFM4_MFS0_LIN_SMR_SOE                     *((volatile  uint8_t *)(0x42700000UL))
#define bFM_MFS0_LIN_SMR_SBL                      *((volatile  uint8_t *)(0x4270000CUL))
#define bFM4_MFS0_LIN_SMR_SBL                     *((volatile  uint8_t *)(0x4270000CUL))
#define bFM_MFS0_LIN_SMR_WUCR                     *((volatile  uint8_t *)(0x42700010UL))
#define bFM4_MFS0_LIN_SMR_WUCR                    *((volatile  uint8_t *)(0x42700010UL))

#define bFM_MFS0_LIN_SSR_TBI                      *((volatile  uint8_t *)(0x427000A0UL))
#define bFM4_MFS0_LIN_SSR_TBI                     *((volatile  uint8_t *)(0x427000A0UL))
#define bFM_MFS0_LIN_SSR_TDRE                     *((volatile  uint8_t *)(0x427000A4UL))
#define bFM4_MFS0_LIN_SSR_TDRE                    *((volatile  uint8_t *)(0x427000A4UL))
#define bFM_MFS0_LIN_SSR_RDRF                     *((volatile  uint8_t *)(0x427000A8UL))
#define bFM4_MFS0_LIN_SSR_RDRF                    *((volatile  uint8_t *)(0x427000A8UL))
#define bFM_MFS0_LIN_SSR_ORE                      *((volatile  uint8_t *)(0x427000ACUL))
#define bFM4_MFS0_LIN_SSR_ORE                     *((volatile  uint8_t *)(0x427000ACUL))
#define bFM_MFS0_LIN_SSR_FRE                      *((volatile  uint8_t *)(0x427000B0UL))
#define bFM4_MFS0_LIN_SSR_FRE                     *((volatile  uint8_t *)(0x427000B0UL))
#define bFM_MFS0_LIN_SSR_LBD                      *((volatile  uint8_t *)(0x427000B4UL))
#define bFM4_MFS0_LIN_SSR_LBD                     *((volatile  uint8_t *)(0x427000B4UL))
#define bFM_MFS0_LIN_SSR_REC                      *((volatile  uint8_t *)(0x427000BCUL))
#define bFM4_MFS0_LIN_SSR_REC                     *((volatile  uint8_t *)(0x427000BCUL))

#define bFM_MFS0_UART_BGR_EXT                     *((volatile  uint8_t *)(0x427001BCUL))
#define bFM4_MFS0_UART_BGR_EXT                    *((volatile  uint8_t *)(0x427001BCUL))

#define bFM_MFS0_UART_ESCR_P                      *((volatile  uint8_t *)(0x4270008CUL))
#define bFM4_MFS0_UART_ESCR_P                     *((volatile  uint8_t *)(0x4270008CUL))
#define bFM_MFS0_UART_ESCR_PEN                    *((volatile  uint8_t *)(0x42700090UL))
#define bFM4_MFS0_UART_ESCR_PEN                   *((volatile  uint8_t *)(0x42700090UL))
#define bFM_MFS0_UART_ESCR_INV                    *((volatile  uint8_t *)(0x42700094UL))
#define bFM4_MFS0_UART_ESCR_INV                   *((volatile  uint8_t *)(0x42700094UL))
#define bFM_MFS0_UART_ESCR_ESBL                   *((volatile  uint8_t *)(0x42700098UL))
#define bFM4_MFS0_UART_ESCR_ESBL                  *((volatile  uint8_t *)(0x42700098UL))
#define bFM_MFS0_UART_ESCR_FLWEN                  *((volatile  uint8_t *)(0x4270009CUL))
#define bFM4_MFS0_UART_ESCR_FLWEN                 *((volatile  uint8_t *)(0x4270009CUL))

#define bFM_MFS0_UART_FCR_FE1                     *((volatile  uint8_t *)(0x42700280UL))
#define bFM4_MFS0_UART_FCR_FE1                    *((volatile  uint8_t *)(0x42700280UL))
#define bFM_MFS0_UART_FCR_FE2                     *((volatile  uint8_t *)(0x42700284UL))
#define bFM4_MFS0_UART_FCR_FE2                    *((volatile  uint8_t *)(0x42700284UL))
#define bFM_MFS0_UART_FCR_FCL1                    *((volatile  uint8_t *)(0x42700288UL))
#define bFM4_MFS0_UART_FCR_FCL1                   *((volatile  uint8_t *)(0x42700288UL))
#define bFM_MFS0_UART_FCR_FCL2                    *((volatile  uint8_t *)(0x4270028CUL))
#define bFM4_MFS0_UART_FCR_FCL2                   *((volatile  uint8_t *)(0x4270028CUL))
#define bFM_MFS0_UART_FCR_FSET                    *((volatile  uint8_t *)(0x42700290UL))
#define bFM4_MFS0_UART_FCR_FSET                   *((volatile  uint8_t *)(0x42700290UL))
#define bFM_MFS0_UART_FCR_FLD                     *((volatile  uint8_t *)(0x42700294UL))
#define bFM4_MFS0_UART_FCR_FLD                    *((volatile  uint8_t *)(0x42700294UL))
#define bFM_MFS0_UART_FCR_FLST                    *((volatile  uint8_t *)(0x42700298UL))
#define bFM4_MFS0_UART_FCR_FLST                   *((volatile  uint8_t *)(0x42700298UL))
#define bFM_MFS0_UART_FCR_FSEL                    *((volatile  uint8_t *)(0x427002A0UL))
#define bFM4_MFS0_UART_FCR_FSEL                   *((volatile  uint8_t *)(0x427002A0UL))
#define bFM_MFS0_UART_FCR_FTIE                    *((volatile  uint8_t *)(0x427002A4UL))
#define bFM4_MFS0_UART_FCR_FTIE                   *((volatile  uint8_t *)(0x427002A4UL))
#define bFM_MFS0_UART_FCR_FDRQ                    *((volatile  uint8_t *)(0x427002A8UL))
#define bFM4_MFS0_UART_FCR_FDRQ                   *((volatile  uint8_t *)(0x427002A8UL))
#define bFM_MFS0_UART_FCR_FRIIE                   *((volatile  uint8_t *)(0x427002ACUL))
#define bFM4_MFS0_UART_FCR_FRIIE                  *((volatile  uint8_t *)(0x427002ACUL))
#define bFM_MFS0_UART_FCR_FLSTE                   *((volatile  uint8_t *)(0x427002B0UL))
#define bFM4_MFS0_UART_FCR_FLSTE                  *((volatile  uint8_t *)(0x427002B0UL))

#define bFM_MFS0_UART_SCR_TXE                     *((volatile  uint8_t *)(0x42700020UL))
#define bFM4_MFS0_UART_SCR_TXE                    *((volatile  uint8_t *)(0x42700020UL))
#define bFM_MFS0_UART_SCR_RXE                     *((volatile  uint8_t *)(0x42700024UL))
#define bFM4_MFS0_UART_SCR_RXE                    *((volatile  uint8_t *)(0x42700024UL))
#define bFM_MFS0_UART_SCR_TBIE                    *((volatile  uint8_t *)(0x42700028UL))
#define bFM4_MFS0_UART_SCR_TBIE                   *((volatile  uint8_t *)(0x42700028UL))
#define bFM_MFS0_UART_SCR_TIE                     *((volatile  uint8_t *)(0x4270002CUL))
#define bFM4_MFS0_UART_SCR_TIE                    *((volatile  uint8_t *)(0x4270002CUL))
#define bFM_MFS0_UART_SCR_RIE                     *((volatile  uint8_t *)(0x42700030UL))
#define bFM4_MFS0_UART_SCR_RIE                    *((volatile  uint8_t *)(0x42700030UL))
#define bFM_MFS0_UART_SCR_UPCL                    *((volatile  uint8_t *)(0x4270003CUL))
#define bFM4_MFS0_UART_SCR_UPCL                   *((volatile  uint8_t *)(0x4270003CUL))

#define bFM_MFS0_UART_SMR_SOE                     *((volatile  uint8_t *)(0x42700000UL))
#define bFM4_MFS0_UART_SMR_SOE                    *((volatile  uint8_t *)(0x42700000UL))
#define bFM_MFS0_UART_SMR_BDS                     *((volatile  uint8_t *)(0x42700008UL))
#define bFM4_MFS0_UART_SMR_BDS                    *((volatile  uint8_t *)(0x42700008UL))
#define bFM_MFS0_UART_SMR_SBL                     *((volatile  uint8_t *)(0x4270000CUL))
#define bFM4_MFS0_UART_SMR_SBL                    *((volatile  uint8_t *)(0x4270000CUL))

#define bFM_MFS0_UART_SSR_TBI                     *((volatile  uint8_t *)(0x427000A0UL))
#define bFM4_MFS0_UART_SSR_TBI                    *((volatile  uint8_t *)(0x427000A0UL))
#define bFM_MFS0_UART_SSR_TDRE                    *((volatile  uint8_t *)(0x427000A4UL))
#define bFM4_MFS0_UART_SSR_TDRE                   *((volatile  uint8_t *)(0x427000A4UL))
#define bFM_MFS0_UART_SSR_RDRF                    *((volatile  uint8_t *)(0x427000A8UL))
#define bFM4_MFS0_UART_SSR_RDRF                   *((volatile  uint8_t *)(0x427000A8UL))
#define bFM_MFS0_UART_SSR_ORE                     *((volatile  uint8_t *)(0x427000ACUL))
#define bFM4_MFS0_UART_SSR_ORE                    *((volatile  uint8_t *)(0x427000ACUL))
#define bFM_MFS0_UART_SSR_FRE                     *((volatile  uint8_t *)(0x427000B0UL))
#define bFM4_MFS0_UART_SSR_FRE                    *((volatile  uint8_t *)(0x427000B0UL))
#define bFM_MFS0_UART_SSR_PE                      *((volatile  uint8_t *)(0x427000B4UL))
#define bFM4_MFS0_UART_SSR_PE                     *((volatile  uint8_t *)(0x427000B4UL))
#define bFM_MFS0_UART_SSR_REC                     *((volatile  uint8_t *)(0x427000BCUL))
#define bFM4_MFS0_UART_SSR_REC                    *((volatile  uint8_t *)(0x427000BCUL))


/*******************************************************************************
* MFS Registers MFS1
*   Bitband Section
*******************************************************************************/
#define bFM_MFS1_CSIO_ESCR_CSFE                   *((volatile  uint8_t *)(0x42702094UL))
#define bFM4_MFS1_CSIO_ESCR_CSFE                  *((volatile  uint8_t *)(0x42702094UL))
#define bFM_MFS1_CSIO_ESCR_L3                     *((volatile  uint8_t *)(0x42702098UL))
#define bFM4_MFS1_CSIO_ESCR_L3                    *((volatile  uint8_t *)(0x42702098UL))
#define bFM_MFS1_CSIO_ESCR_SOP                    *((volatile  uint8_t *)(0x4270209CUL))
#define bFM4_MFS1_CSIO_ESCR_SOP                   *((volatile  uint8_t *)(0x4270209CUL))

#define bFM_MFS1_CSIO_FCR_FE1                     *((volatile  uint8_t *)(0x42702280UL))
#define bFM4_MFS1_CSIO_FCR_FE1                    *((volatile  uint8_t *)(0x42702280UL))
#define bFM_MFS1_CSIO_FCR_FE2                     *((volatile  uint8_t *)(0x42702284UL))
#define bFM4_MFS1_CSIO_FCR_FE2                    *((volatile  uint8_t *)(0x42702284UL))
#define bFM_MFS1_CSIO_FCR_FCL1                    *((volatile  uint8_t *)(0x42702288UL))
#define bFM4_MFS1_CSIO_FCR_FCL1                   *((volatile  uint8_t *)(0x42702288UL))
#define bFM_MFS1_CSIO_FCR_FCL2                    *((volatile  uint8_t *)(0x4270228CUL))
#define bFM4_MFS1_CSIO_FCR_FCL2                   *((volatile  uint8_t *)(0x4270228CUL))
#define bFM_MFS1_CSIO_FCR_FSET                    *((volatile  uint8_t *)(0x42702290UL))
#define bFM4_MFS1_CSIO_FCR_FSET                   *((volatile  uint8_t *)(0x42702290UL))
#define bFM_MFS1_CSIO_FCR_FLD                     *((volatile  uint8_t *)(0x42702294UL))
#define bFM4_MFS1_CSIO_FCR_FLD                    *((volatile  uint8_t *)(0x42702294UL))
#define bFM_MFS1_CSIO_FCR_FLST                    *((volatile  uint8_t *)(0x42702298UL))
#define bFM4_MFS1_CSIO_FCR_FLST                   *((volatile  uint8_t *)(0x42702298UL))
#define bFM_MFS1_CSIO_FCR_FSEL                    *((volatile  uint8_t *)(0x427022A0UL))
#define bFM4_MFS1_CSIO_FCR_FSEL                   *((volatile  uint8_t *)(0x427022A0UL))
#define bFM_MFS1_CSIO_FCR_FTIE                    *((volatile  uint8_t *)(0x427022A4UL))
#define bFM4_MFS1_CSIO_FCR_FTIE                   *((volatile  uint8_t *)(0x427022A4UL))
#define bFM_MFS1_CSIO_FCR_FDRQ                    *((volatile  uint8_t *)(0x427022A8UL))
#define bFM4_MFS1_CSIO_FCR_FDRQ                   *((volatile  uint8_t *)(0x427022A8UL))
#define bFM_MFS1_CSIO_FCR_FRIIE                   *((volatile  uint8_t *)(0x427022ACUL))
#define bFM4_MFS1_CSIO_FCR_FRIIE                  *((volatile  uint8_t *)(0x427022ACUL))
#define bFM_MFS1_CSIO_FCR_FLSTE                   *((volatile  uint8_t *)(0x427022B0UL))
#define bFM4_MFS1_CSIO_FCR_FLSTE                  *((volatile  uint8_t *)(0x427022B0UL))

#define bFM_MFS1_CSIO_SACSR_TMRE                  *((volatile  uint8_t *)(0x42702480UL))
#define bFM4_MFS1_CSIO_SACSR_TMRE                 *((volatile  uint8_t *)(0x42702480UL))
#define bFM_MFS1_CSIO_SACSR_TSYNE                 *((volatile  uint8_t *)(0x42702498UL))
#define bFM4_MFS1_CSIO_SACSR_TSYNE                *((volatile  uint8_t *)(0x42702498UL))
#define bFM_MFS1_CSIO_SACSR_TINTE                 *((volatile  uint8_t *)(0x4270249CUL))
#define bFM4_MFS1_CSIO_SACSR_TINTE                *((volatile  uint8_t *)(0x4270249CUL))
#define bFM_MFS1_CSIO_SACSR_TINT                  *((volatile  uint8_t *)(0x427024A0UL))
#define bFM4_MFS1_CSIO_SACSR_TINT                 *((volatile  uint8_t *)(0x427024A0UL))
#define bFM_MFS1_CSIO_SACSR_CSE                   *((volatile  uint8_t *)(0x427024ACUL))
#define bFM4_MFS1_CSIO_SACSR_CSE                  *((volatile  uint8_t *)(0x427024ACUL))
#define bFM_MFS1_CSIO_SACSR_CSEIE                 *((volatile  uint8_t *)(0x427024B0UL))
#define bFM4_MFS1_CSIO_SACSR_CSEIE                *((volatile  uint8_t *)(0x427024B0UL))
#define bFM_MFS1_CSIO_SACSR_TBEEN                 *((volatile  uint8_t *)(0x427024B4UL))
#define bFM4_MFS1_CSIO_SACSR_TBEEN                *((volatile  uint8_t *)(0x427024B4UL))

#define bFM_MFS1_CSIO_SCR_TXE                     *((volatile  uint8_t *)(0x42702020UL))
#define bFM4_MFS1_CSIO_SCR_TXE                    *((volatile  uint8_t *)(0x42702020UL))
#define bFM_MFS1_CSIO_SCR_RXE                     *((volatile  uint8_t *)(0x42702024UL))
#define bFM4_MFS1_CSIO_SCR_RXE                    *((volatile  uint8_t *)(0x42702024UL))
#define bFM_MFS1_CSIO_SCR_TBIE                    *((volatile  uint8_t *)(0x42702028UL))
#define bFM4_MFS1_CSIO_SCR_TBIE                   *((volatile  uint8_t *)(0x42702028UL))
#define bFM_MFS1_CSIO_SCR_TIE                     *((volatile  uint8_t *)(0x4270202CUL))
#define bFM4_MFS1_CSIO_SCR_TIE                    *((volatile  uint8_t *)(0x4270202CUL))
#define bFM_MFS1_CSIO_SCR_RIE                     *((volatile  uint8_t *)(0x42702030UL))
#define bFM4_MFS1_CSIO_SCR_RIE                    *((volatile  uint8_t *)(0x42702030UL))
#define bFM_MFS1_CSIO_SCR_SPI                     *((volatile  uint8_t *)(0x42702034UL))
#define bFM4_MFS1_CSIO_SCR_SPI                    *((volatile  uint8_t *)(0x42702034UL))
#define bFM_MFS1_CSIO_SCR_MS                      *((volatile  uint8_t *)(0x42702038UL))
#define bFM4_MFS1_CSIO_SCR_MS                     *((volatile  uint8_t *)(0x42702038UL))
#define bFM_MFS1_CSIO_SCR_UPCL                    *((volatile  uint8_t *)(0x4270203CUL))
#define bFM4_MFS1_CSIO_SCR_UPCL                   *((volatile  uint8_t *)(0x4270203CUL))

#define bFM_MFS1_CSIO_SCSCR_CSOE                  *((volatile  uint8_t *)(0x42702600UL))
#define bFM4_MFS1_CSIO_SCSCR_CSOE                 *((volatile  uint8_t *)(0x42702600UL))
#define bFM_MFS1_CSIO_SCSCR_CSEN0                 *((volatile  uint8_t *)(0x42702604UL))
#define bFM4_MFS1_CSIO_SCSCR_CSEN0                *((volatile  uint8_t *)(0x42702604UL))
#define bFM_MFS1_CSIO_SCSCR_CSEN1                 *((volatile  uint8_t *)(0x42702608UL))
#define bFM4_MFS1_CSIO_SCSCR_CSEN1                *((volatile  uint8_t *)(0x42702608UL))
#define bFM_MFS1_CSIO_SCSCR_CSEN2                 *((volatile  uint8_t *)(0x4270260CUL))
#define bFM4_MFS1_CSIO_SCSCR_CSEN2                *((volatile  uint8_t *)(0x4270260CUL))
#define bFM_MFS1_CSIO_SCSCR_CSEN3                 *((volatile  uint8_t *)(0x42702610UL))
#define bFM4_MFS1_CSIO_SCSCR_CSEN3                *((volatile  uint8_t *)(0x42702610UL))
#define bFM_MFS1_CSIO_SCSCR_CSLVL                 *((volatile  uint8_t *)(0x42702614UL))
#define bFM4_MFS1_CSIO_SCSCR_CSLVL                *((volatile  uint8_t *)(0x42702614UL))
#define bFM_MFS1_CSIO_SCSCR_SCAM                  *((volatile  uint8_t *)(0x42702624UL))
#define bFM4_MFS1_CSIO_SCSCR_SCAM                 *((volatile  uint8_t *)(0x42702624UL))

#define bFM_MFS1_CSIO_SCSFR0_CS1SPI               *((volatile  uint8_t *)(0x42702694UL))
#define bFM4_MFS1_CSIO_SCSFR0_CS1SPI              *((volatile  uint8_t *)(0x42702694UL))
#define bFM_MFS1_CSIO_SCSFR0_CS1SCINV             *((volatile  uint8_t *)(0x42702698UL))
#define bFM4_MFS1_CSIO_SCSFR0_CS1SCINV            *((volatile  uint8_t *)(0x42702698UL))
#define bFM_MFS1_CSIO_SCSFR0_CS1CSLVL             *((volatile  uint8_t *)(0x4270269CUL))
#define bFM4_MFS1_CSIO_SCSFR0_CS1CSLVL            *((volatile  uint8_t *)(0x4270269CUL))

#define bFM_MFS1_CSIO_SCSFR1_CS2SPI               *((volatile  uint8_t *)(0x427026B4UL))
#define bFM4_MFS1_CSIO_SCSFR1_CS2SPI              *((volatile  uint8_t *)(0x427026B4UL))
#define bFM_MFS1_CSIO_SCSFR1_CS2SCINV             *((volatile  uint8_t *)(0x427026B8UL))
#define bFM4_MFS1_CSIO_SCSFR1_CS2SCINV            *((volatile  uint8_t *)(0x427026B8UL))
#define bFM_MFS1_CSIO_SCSFR1_CS2CSLVL             *((volatile  uint8_t *)(0x427026BCUL))
#define bFM4_MFS1_CSIO_SCSFR1_CS2CSLVL            *((volatile  uint8_t *)(0x427026BCUL))

#define bFM_MFS1_CSIO_SCSFR2_CS3SPI               *((volatile  uint8_t *)(0x42702714UL))
#define bFM4_MFS1_CSIO_SCSFR2_CS3SPI              *((volatile  uint8_t *)(0x42702714UL))
#define bFM_MFS1_CSIO_SCSFR2_CS3SCINV             *((volatile  uint8_t *)(0x42702718UL))
#define bFM4_MFS1_CSIO_SCSFR2_CS3SCINV            *((volatile  uint8_t *)(0x42702718UL))
#define bFM_MFS1_CSIO_SCSFR2_CS3CSLVL             *((volatile  uint8_t *)(0x4270271CUL))
#define bFM4_MFS1_CSIO_SCSFR2_CS3CSLVL            *((volatile  uint8_t *)(0x4270271CUL))

#define bFM_MFS1_CSIO_SMR_SOE                     *((volatile  uint8_t *)(0x42702000UL))
#define bFM4_MFS1_CSIO_SMR_SOE                    *((volatile  uint8_t *)(0x42702000UL))
#define bFM_MFS1_CSIO_SMR_SCKE                    *((volatile  uint8_t *)(0x42702004UL))
#define bFM4_MFS1_CSIO_SMR_SCKE                   *((volatile  uint8_t *)(0x42702004UL))
#define bFM_MFS1_CSIO_SMR_BDS                     *((volatile  uint8_t *)(0x42702008UL))
#define bFM4_MFS1_CSIO_SMR_BDS                    *((volatile  uint8_t *)(0x42702008UL))
#define bFM_MFS1_CSIO_SMR_SCINV                   *((volatile  uint8_t *)(0x4270200CUL))
#define bFM4_MFS1_CSIO_SMR_SCINV                  *((volatile  uint8_t *)(0x4270200CUL))

#define bFM_MFS1_CSIO_SSR_TBI                     *((volatile  uint8_t *)(0x427020A0UL))
#define bFM4_MFS1_CSIO_SSR_TBI                    *((volatile  uint8_t *)(0x427020A0UL))
#define bFM_MFS1_CSIO_SSR_TDRE                    *((volatile  uint8_t *)(0x427020A4UL))
#define bFM4_MFS1_CSIO_SSR_TDRE                   *((volatile  uint8_t *)(0x427020A4UL))
#define bFM_MFS1_CSIO_SSR_RDRF                    *((volatile  uint8_t *)(0x427020A8UL))
#define bFM4_MFS1_CSIO_SSR_RDRF                   *((volatile  uint8_t *)(0x427020A8UL))
#define bFM_MFS1_CSIO_SSR_ORE                     *((volatile  uint8_t *)(0x427020ACUL))
#define bFM4_MFS1_CSIO_SSR_ORE                    *((volatile  uint8_t *)(0x427020ACUL))
#define bFM_MFS1_CSIO_SSR_AWC                     *((volatile  uint8_t *)(0x427020B0UL))
#define bFM4_MFS1_CSIO_SSR_AWC                    *((volatile  uint8_t *)(0x427020B0UL))
#define bFM_MFS1_CSIO_SSR_REC                     *((volatile  uint8_t *)(0x427020BCUL))
#define bFM4_MFS1_CSIO_SSR_REC                    *((volatile  uint8_t *)(0x427020BCUL))

#define bFM_MFS1_I2C_EIBCR_BEC                    *((volatile  uint8_t *)(0x427023A0UL))
#define bFM4_MFS1_I2C_EIBCR_BEC                   *((volatile  uint8_t *)(0x427023A0UL))
#define bFM_MFS1_I2C_EIBCR_SOCE                   *((volatile  uint8_t *)(0x427023A4UL))
#define bFM4_MFS1_I2C_EIBCR_SOCE                  *((volatile  uint8_t *)(0x427023A4UL))
#define bFM_MFS1_I2C_EIBCR_SCLC                   *((volatile  uint8_t *)(0x427023A8UL))
#define bFM4_MFS1_I2C_EIBCR_SCLC                  *((volatile  uint8_t *)(0x427023A8UL))
#define bFM_MFS1_I2C_EIBCR_SDAC                   *((volatile  uint8_t *)(0x427023ACUL))
#define bFM4_MFS1_I2C_EIBCR_SDAC                  *((volatile  uint8_t *)(0x427023ACUL))
#define bFM_MFS1_I2C_EIBCR_SCLS                   *((volatile  uint8_t *)(0x427023B0UL))
#define bFM4_MFS1_I2C_EIBCR_SCLS                  *((volatile  uint8_t *)(0x427023B0UL))
#define bFM_MFS1_I2C_EIBCR_SDAS                   *((volatile  uint8_t *)(0x427023B4UL))
#define bFM4_MFS1_I2C_EIBCR_SDAS                  *((volatile  uint8_t *)(0x427023B4UL))

#define bFM_MFS1_I2C_FCR_FE1                      *((volatile  uint8_t *)(0x42702280UL))
#define bFM4_MFS1_I2C_FCR_FE1                     *((volatile  uint8_t *)(0x42702280UL))
#define bFM_MFS1_I2C_FCR_FE2                      *((volatile  uint8_t *)(0x42702284UL))
#define bFM4_MFS1_I2C_FCR_FE2                     *((volatile  uint8_t *)(0x42702284UL))
#define bFM_MFS1_I2C_FCR_FCL1                     *((volatile  uint8_t *)(0x42702288UL))
#define bFM4_MFS1_I2C_FCR_FCL1                    *((volatile  uint8_t *)(0x42702288UL))
#define bFM_MFS1_I2C_FCR_FCL2                     *((volatile  uint8_t *)(0x4270228CUL))
#define bFM4_MFS1_I2C_FCR_FCL2                    *((volatile  uint8_t *)(0x4270228CUL))
#define bFM_MFS1_I2C_FCR_FSET                     *((volatile  uint8_t *)(0x42702290UL))
#define bFM4_MFS1_I2C_FCR_FSET                    *((volatile  uint8_t *)(0x42702290UL))
#define bFM_MFS1_I2C_FCR_FLD                      *((volatile  uint8_t *)(0x42702294UL))
#define bFM4_MFS1_I2C_FCR_FLD                     *((volatile  uint8_t *)(0x42702294UL))
#define bFM_MFS1_I2C_FCR_FLST                     *((volatile  uint8_t *)(0x42702298UL))
#define bFM4_MFS1_I2C_FCR_FLST                    *((volatile  uint8_t *)(0x42702298UL))
#define bFM_MFS1_I2C_FCR_FSEL                     *((volatile  uint8_t *)(0x427022A0UL))
#define bFM4_MFS1_I2C_FCR_FSEL                    *((volatile  uint8_t *)(0x427022A0UL))
#define bFM_MFS1_I2C_FCR_FTIE                     *((volatile  uint8_t *)(0x427022A4UL))
#define bFM4_MFS1_I2C_FCR_FTIE                    *((volatile  uint8_t *)(0x427022A4UL))
#define bFM_MFS1_I2C_FCR_FDRQ                     *((volatile  uint8_t *)(0x427022A8UL))
#define bFM4_MFS1_I2C_FCR_FDRQ                    *((volatile  uint8_t *)(0x427022A8UL))
#define bFM_MFS1_I2C_FCR_FRIIE                    *((volatile  uint8_t *)(0x427022ACUL))
#define bFM4_MFS1_I2C_FCR_FRIIE                   *((volatile  uint8_t *)(0x427022ACUL))
#define bFM_MFS1_I2C_FCR_FLSTE                    *((volatile  uint8_t *)(0x427022B0UL))
#define bFM4_MFS1_I2C_FCR_FLSTE                   *((volatile  uint8_t *)(0x427022B0UL))

#define bFM_MFS1_I2C_IBCR_INT                     *((volatile  uint8_t *)(0x42702020UL))
#define bFM4_MFS1_I2C_IBCR_INT                    *((volatile  uint8_t *)(0x42702020UL))
#define bFM_MFS1_I2C_IBCR_BER                     *((volatile  uint8_t *)(0x42702024UL))
#define bFM4_MFS1_I2C_IBCR_BER                    *((volatile  uint8_t *)(0x42702024UL))
#define bFM_MFS1_I2C_IBCR_INTE                    *((volatile  uint8_t *)(0x42702028UL))
#define bFM4_MFS1_I2C_IBCR_INTE                   *((volatile  uint8_t *)(0x42702028UL))
#define bFM_MFS1_I2C_IBCR_CNDE                    *((volatile  uint8_t *)(0x4270202CUL))
#define bFM4_MFS1_I2C_IBCR_CNDE                   *((volatile  uint8_t *)(0x4270202CUL))
#define bFM_MFS1_I2C_IBCR_WSEL                    *((volatile  uint8_t *)(0x42702030UL))
#define bFM4_MFS1_I2C_IBCR_WSEL                   *((volatile  uint8_t *)(0x42702030UL))
#define bFM_MFS1_I2C_IBCR_ACKE                    *((volatile  uint8_t *)(0x42702034UL))
#define bFM4_MFS1_I2C_IBCR_ACKE                   *((volatile  uint8_t *)(0x42702034UL))
#define bFM_MFS1_I2C_IBCR_ACT_SCC                 *((volatile  uint8_t *)(0x42702038UL))
#define bFM4_MFS1_I2C_IBCR_ACT_SCC                *((volatile  uint8_t *)(0x42702038UL))
#define bFM_MFS1_I2C_IBCR_MSS                     *((volatile  uint8_t *)(0x4270203CUL))
#define bFM4_MFS1_I2C_IBCR_MSS                    *((volatile  uint8_t *)(0x4270203CUL))

#define bFM_MFS1_I2C_IBSR_BB                      *((volatile  uint8_t *)(0x42702080UL))
#define bFM4_MFS1_I2C_IBSR_BB                     *((volatile  uint8_t *)(0x42702080UL))
#define bFM_MFS1_I2C_IBSR_SPC                     *((volatile  uint8_t *)(0x42702084UL))
#define bFM4_MFS1_I2C_IBSR_SPC                    *((volatile  uint8_t *)(0x42702084UL))
#define bFM_MFS1_I2C_IBSR_RSC                     *((volatile  uint8_t *)(0x42702088UL))
#define bFM4_MFS1_I2C_IBSR_RSC                    *((volatile  uint8_t *)(0x42702088UL))
#define bFM_MFS1_I2C_IBSR_AL                      *((volatile  uint8_t *)(0x4270208CUL))
#define bFM4_MFS1_I2C_IBSR_AL                     *((volatile  uint8_t *)(0x4270208CUL))
#define bFM_MFS1_I2C_IBSR_TRX                     *((volatile  uint8_t *)(0x42702090UL))
#define bFM4_MFS1_I2C_IBSR_TRX                    *((volatile  uint8_t *)(0x42702090UL))
#define bFM_MFS1_I2C_IBSR_RSA                     *((volatile  uint8_t *)(0x42702094UL))
#define bFM4_MFS1_I2C_IBSR_RSA                    *((volatile  uint8_t *)(0x42702094UL))
#define bFM_MFS1_I2C_IBSR_RACK                    *((volatile  uint8_t *)(0x42702098UL))
#define bFM4_MFS1_I2C_IBSR_RACK                   *((volatile  uint8_t *)(0x42702098UL))
#define bFM_MFS1_I2C_IBSR_FBT                     *((volatile  uint8_t *)(0x4270209CUL))
#define bFM4_MFS1_I2C_IBSR_FBT                    *((volatile  uint8_t *)(0x4270209CUL))

#define bFM_MFS1_I2C_ISBA_SAEN                    *((volatile  uint8_t *)(0x4270221CUL))
#define bFM4_MFS1_I2C_ISBA_SAEN                   *((volatile  uint8_t *)(0x4270221CUL))

#define bFM_MFS1_I2C_ISMK_EN                      *((volatile  uint8_t *)(0x4270223CUL))
#define bFM4_MFS1_I2C_ISMK_EN                     *((volatile  uint8_t *)(0x4270223CUL))

#define bFM_MFS1_I2C_SMR_TIE                      *((volatile  uint8_t *)(0x42702008UL))
#define bFM4_MFS1_I2C_SMR_TIE                     *((volatile  uint8_t *)(0x42702008UL))
#define bFM_MFS1_I2C_SMR_RIE                      *((volatile  uint8_t *)(0x4270200CUL))
#define bFM4_MFS1_I2C_SMR_RIE                     *((volatile  uint8_t *)(0x4270200CUL))

#define bFM_MFS1_I2C_SSR_TBI                      *((volatile  uint8_t *)(0x427020A0UL))
#define bFM4_MFS1_I2C_SSR_TBI                     *((volatile  uint8_t *)(0x427020A0UL))
#define bFM_MFS1_I2C_SSR_TDRE                     *((volatile  uint8_t *)(0x427020A4UL))
#define bFM4_MFS1_I2C_SSR_TDRE                    *((volatile  uint8_t *)(0x427020A4UL))
#define bFM_MFS1_I2C_SSR_RDRF                     *((volatile  uint8_t *)(0x427020A8UL))
#define bFM4_MFS1_I2C_SSR_RDRF                    *((volatile  uint8_t *)(0x427020A8UL))
#define bFM_MFS1_I2C_SSR_ORE                      *((volatile  uint8_t *)(0x427020ACUL))
#define bFM4_MFS1_I2C_SSR_ORE                     *((volatile  uint8_t *)(0x427020ACUL))
#define bFM_MFS1_I2C_SSR_TBIE                     *((volatile  uint8_t *)(0x427020B0UL))
#define bFM4_MFS1_I2C_SSR_TBIE                    *((volatile  uint8_t *)(0x427020B0UL))
#define bFM_MFS1_I2C_SSR_DMA                      *((volatile  uint8_t *)(0x427020B4UL))
#define bFM4_MFS1_I2C_SSR_DMA                     *((volatile  uint8_t *)(0x427020B4UL))
#define bFM_MFS1_I2C_SSR_TSET                     *((volatile  uint8_t *)(0x427020B8UL))
#define bFM4_MFS1_I2C_SSR_TSET                    *((volatile  uint8_t *)(0x427020B8UL))
#define bFM_MFS1_I2C_SSR_REC                      *((volatile  uint8_t *)(0x427020BCUL))
#define bFM4_MFS1_I2C_SSR_REC                     *((volatile  uint8_t *)(0x427020BCUL))

#define bFM_MFS1_LIN_BGR_EXT                      *((volatile  uint8_t *)(0x427021BCUL))
#define bFM4_MFS1_LIN_BGR_EXT                     *((volatile  uint8_t *)(0x427021BCUL))

#define bFM_MFS1_LIN_ESCR_LBIE                    *((volatile  uint8_t *)(0x42702090UL))
#define bFM4_MFS1_LIN_ESCR_LBIE                   *((volatile  uint8_t *)(0x42702090UL))
#define bFM_MFS1_LIN_ESCR_ESBL                    *((volatile  uint8_t *)(0x42702098UL))
#define bFM4_MFS1_LIN_ESCR_ESBL                   *((volatile  uint8_t *)(0x42702098UL))

#define bFM_MFS1_LIN_FCR_FE1                      *((volatile  uint8_t *)(0x42702280UL))
#define bFM4_MFS1_LIN_FCR_FE1                     *((volatile  uint8_t *)(0x42702280UL))
#define bFM_MFS1_LIN_FCR_FE2                      *((volatile  uint8_t *)(0x42702284UL))
#define bFM4_MFS1_LIN_FCR_FE2                     *((volatile  uint8_t *)(0x42702284UL))
#define bFM_MFS1_LIN_FCR_FCL1                     *((volatile  uint8_t *)(0x42702288UL))
#define bFM4_MFS1_LIN_FCR_FCL1                    *((volatile  uint8_t *)(0x42702288UL))
#define bFM_MFS1_LIN_FCR_FCL2                     *((volatile  uint8_t *)(0x4270228CUL))
#define bFM4_MFS1_LIN_FCR_FCL2                    *((volatile  uint8_t *)(0x4270228CUL))
#define bFM_MFS1_LIN_FCR_FSET                     *((volatile  uint8_t *)(0x42702290UL))
#define bFM4_MFS1_LIN_FCR_FSET                    *((volatile  uint8_t *)(0x42702290UL))
#define bFM_MFS1_LIN_FCR_FLD                      *((volatile  uint8_t *)(0x42702294UL))
#define bFM4_MFS1_LIN_FCR_FLD                     *((volatile  uint8_t *)(0x42702294UL))
#define bFM_MFS1_LIN_FCR_FLST                     *((volatile  uint8_t *)(0x42702298UL))
#define bFM4_MFS1_LIN_FCR_FLST                    *((volatile  uint8_t *)(0x42702298UL))
#define bFM_MFS1_LIN_FCR_FSEL                     *((volatile  uint8_t *)(0x427022A0UL))
#define bFM4_MFS1_LIN_FCR_FSEL                    *((volatile  uint8_t *)(0x427022A0UL))
#define bFM_MFS1_LIN_FCR_FTIE                     *((volatile  uint8_t *)(0x427022A4UL))
#define bFM4_MFS1_LIN_FCR_FTIE                    *((volatile  uint8_t *)(0x427022A4UL))
#define bFM_MFS1_LIN_FCR_FDRQ                     *((volatile  uint8_t *)(0x427022A8UL))
#define bFM4_MFS1_LIN_FCR_FDRQ                    *((volatile  uint8_t *)(0x427022A8UL))
#define bFM_MFS1_LIN_FCR_FRIIE                    *((volatile  uint8_t *)(0x427022ACUL))
#define bFM4_MFS1_LIN_FCR_FRIIE                   *((volatile  uint8_t *)(0x427022ACUL))
#define bFM_MFS1_LIN_FCR_FLSTE                    *((volatile  uint8_t *)(0x427022B0UL))
#define bFM4_MFS1_LIN_FCR_FLSTE                   *((volatile  uint8_t *)(0x427022B0UL))

#define bFM_MFS1_LIN_SCR_TXE                      *((volatile  uint8_t *)(0x42702020UL))
#define bFM4_MFS1_LIN_SCR_TXE                     *((volatile  uint8_t *)(0x42702020UL))
#define bFM_MFS1_LIN_SCR_RXE                      *((volatile  uint8_t *)(0x42702024UL))
#define bFM4_MFS1_LIN_SCR_RXE                     *((volatile  uint8_t *)(0x42702024UL))
#define bFM_MFS1_LIN_SCR_TBIE                     *((volatile  uint8_t *)(0x42702028UL))
#define bFM4_MFS1_LIN_SCR_TBIE                    *((volatile  uint8_t *)(0x42702028UL))
#define bFM_MFS1_LIN_SCR_TIE                      *((volatile  uint8_t *)(0x4270202CUL))
#define bFM4_MFS1_LIN_SCR_TIE                     *((volatile  uint8_t *)(0x4270202CUL))
#define bFM_MFS1_LIN_SCR_RIE                      *((volatile  uint8_t *)(0x42702030UL))
#define bFM4_MFS1_LIN_SCR_RIE                     *((volatile  uint8_t *)(0x42702030UL))
#define bFM_MFS1_LIN_SCR_LBR                      *((volatile  uint8_t *)(0x42702034UL))
#define bFM4_MFS1_LIN_SCR_LBR                     *((volatile  uint8_t *)(0x42702034UL))
#define bFM_MFS1_LIN_SCR_MS                       *((volatile  uint8_t *)(0x42702038UL))
#define bFM4_MFS1_LIN_SCR_MS                      *((volatile  uint8_t *)(0x42702038UL))
#define bFM_MFS1_LIN_SCR_UPCL                     *((volatile  uint8_t *)(0x4270203CUL))
#define bFM4_MFS1_LIN_SCR_UPCL                    *((volatile  uint8_t *)(0x4270203CUL))

#define bFM_MFS1_LIN_SMR_SOE                      *((volatile  uint8_t *)(0x42702000UL))
#define bFM4_MFS1_LIN_SMR_SOE                     *((volatile  uint8_t *)(0x42702000UL))
#define bFM_MFS1_LIN_SMR_SBL                      *((volatile  uint8_t *)(0x4270200CUL))
#define bFM4_MFS1_LIN_SMR_SBL                     *((volatile  uint8_t *)(0x4270200CUL))
#define bFM_MFS1_LIN_SMR_WUCR                     *((volatile  uint8_t *)(0x42702010UL))
#define bFM4_MFS1_LIN_SMR_WUCR                    *((volatile  uint8_t *)(0x42702010UL))

#define bFM_MFS1_LIN_SSR_TBI                      *((volatile  uint8_t *)(0x427020A0UL))
#define bFM4_MFS1_LIN_SSR_TBI                     *((volatile  uint8_t *)(0x427020A0UL))
#define bFM_MFS1_LIN_SSR_TDRE                     *((volatile  uint8_t *)(0x427020A4UL))
#define bFM4_MFS1_LIN_SSR_TDRE                    *((volatile  uint8_t *)(0x427020A4UL))
#define bFM_MFS1_LIN_SSR_RDRF                     *((volatile  uint8_t *)(0x427020A8UL))
#define bFM4_MFS1_LIN_SSR_RDRF                    *((volatile  uint8_t *)(0x427020A8UL))
#define bFM_MFS1_LIN_SSR_ORE                      *((volatile  uint8_t *)(0x427020ACUL))
#define bFM4_MFS1_LIN_SSR_ORE                     *((volatile  uint8_t *)(0x427020ACUL))
#define bFM_MFS1_LIN_SSR_FRE                      *((volatile  uint8_t *)(0x427020B0UL))
#define bFM4_MFS1_LIN_SSR_FRE                     *((volatile  uint8_t *)(0x427020B0UL))
#define bFM_MFS1_LIN_SSR_LBD                      *((volatile  uint8_t *)(0x427020B4UL))
#define bFM4_MFS1_LIN_SSR_LBD                     *((volatile  uint8_t *)(0x427020B4UL))
#define bFM_MFS1_LIN_SSR_REC                      *((volatile  uint8_t *)(0x427020BCUL))
#define bFM4_MFS1_LIN_SSR_REC                     *((volatile  uint8_t *)(0x427020BCUL))

#define bFM_MFS1_UART_BGR_EXT                     *((volatile  uint8_t *)(0x427021BCUL))
#define bFM4_MFS1_UART_BGR_EXT                    *((volatile  uint8_t *)(0x427021BCUL))

#define bFM_MFS1_UART_ESCR_P                      *((volatile  uint8_t *)(0x4270208CUL))
#define bFM4_MFS1_UART_ESCR_P                     *((volatile  uint8_t *)(0x4270208CUL))
#define bFM_MFS1_UART_ESCR_PEN                    *((volatile  uint8_t *)(0x42702090UL))
#define bFM4_MFS1_UART_ESCR_PEN                   *((volatile  uint8_t *)(0x42702090UL))
#define bFM_MFS1_UART_ESCR_INV                    *((volatile  uint8_t *)(0x42702094UL))
#define bFM4_MFS1_UART_ESCR_INV                   *((volatile  uint8_t *)(0x42702094UL))
#define bFM_MFS1_UART_ESCR_ESBL                   *((volatile  uint8_t *)(0x42702098UL))
#define bFM4_MFS1_UART_ESCR_ESBL                  *((volatile  uint8_t *)(0x42702098UL))
#define bFM_MFS1_UART_ESCR_FLWEN                  *((volatile  uint8_t *)(0x4270209CUL))
#define bFM4_MFS1_UART_ESCR_FLWEN                 *((volatile  uint8_t *)(0x4270209CUL))

#define bFM_MFS1_UART_FCR_FE1                     *((volatile  uint8_t *)(0x42702280UL))
#define bFM4_MFS1_UART_FCR_FE1                    *((volatile  uint8_t *)(0x42702280UL))
#define bFM_MFS1_UART_FCR_FE2                     *((volatile  uint8_t *)(0x42702284UL))
#define bFM4_MFS1_UART_FCR_FE2                    *((volatile  uint8_t *)(0x42702284UL))
#define bFM_MFS1_UART_FCR_FCL1                    *((volatile  uint8_t *)(0x42702288UL))
#define bFM4_MFS1_UART_FCR_FCL1                   *((volatile  uint8_t *)(0x42702288UL))
#define bFM_MFS1_UART_FCR_FCL2                    *((volatile  uint8_t *)(0x4270228CUL))
#define bFM4_MFS1_UART_FCR_FCL2                   *((volatile  uint8_t *)(0x4270228CUL))
#define bFM_MFS1_UART_FCR_FSET                    *((volatile  uint8_t *)(0x42702290UL))
#define bFM4_MFS1_UART_FCR_FSET                   *((volatile  uint8_t *)(0x42702290UL))
#define bFM_MFS1_UART_FCR_FLD                     *((volatile  uint8_t *)(0x42702294UL))
#define bFM4_MFS1_UART_FCR_FLD                    *((volatile  uint8_t *)(0x42702294UL))
#define bFM_MFS1_UART_FCR_FLST                    *((volatile  uint8_t *)(0x42702298UL))
#define bFM4_MFS1_UART_FCR_FLST                   *((volatile  uint8_t *)(0x42702298UL))
#define bFM_MFS1_UART_FCR_FSEL                    *((volatile  uint8_t *)(0x427022A0UL))
#define bFM4_MFS1_UART_FCR_FSEL                   *((volatile  uint8_t *)(0x427022A0UL))
#define bFM_MFS1_UART_FCR_FTIE                    *((volatile  uint8_t *)(0x427022A4UL))
#define bFM4_MFS1_UART_FCR_FTIE                   *((volatile  uint8_t *)(0x427022A4UL))
#define bFM_MFS1_UART_FCR_FDRQ                    *((volatile  uint8_t *)(0x427022A8UL))
#define bFM4_MFS1_UART_FCR_FDRQ                   *((volatile  uint8_t *)(0x427022A8UL))
#define bFM_MFS1_UART_FCR_FRIIE                   *((volatile  uint8_t *)(0x427022ACUL))
#define bFM4_MFS1_UART_FCR_FRIIE                  *((volatile  uint8_t *)(0x427022ACUL))
#define bFM_MFS1_UART_FCR_FLSTE                   *((volatile  uint8_t *)(0x427022B0UL))
#define bFM4_MFS1_UART_FCR_FLSTE                  *((volatile  uint8_t *)(0x427022B0UL))

#define bFM_MFS1_UART_SCR_TXE                     *((volatile  uint8_t *)(0x42702020UL))
#define bFM4_MFS1_UART_SCR_TXE                    *((volatile  uint8_t *)(0x42702020UL))
#define bFM_MFS1_UART_SCR_RXE                     *((volatile  uint8_t *)(0x42702024UL))
#define bFM4_MFS1_UART_SCR_RXE                    *((volatile  uint8_t *)(0x42702024UL))
#define bFM_MFS1_UART_SCR_TBIE                    *((volatile  uint8_t *)(0x42702028UL))
#define bFM4_MFS1_UART_SCR_TBIE                   *((volatile  uint8_t *)(0x42702028UL))
#define bFM_MFS1_UART_SCR_TIE                     *((volatile  uint8_t *)(0x4270202CUL))
#define bFM4_MFS1_UART_SCR_TIE                    *((volatile  uint8_t *)(0x4270202CUL))
#define bFM_MFS1_UART_SCR_RIE                     *((volatile  uint8_t *)(0x42702030UL))
#define bFM4_MFS1_UART_SCR_RIE                    *((volatile  uint8_t *)(0x42702030UL))
#define bFM_MFS1_UART_SCR_UPCL                    *((volatile  uint8_t *)(0x4270203CUL))
#define bFM4_MFS1_UART_SCR_UPCL                   *((volatile  uint8_t *)(0x4270203CUL))

#define bFM_MFS1_UART_SMR_SOE                     *((volatile  uint8_t *)(0x42702000UL))
#define bFM4_MFS1_UART_SMR_SOE                    *((volatile  uint8_t *)(0x42702000UL))
#define bFM_MFS1_UART_SMR_BDS                     *((volatile  uint8_t *)(0x42702008UL))
#define bFM4_MFS1_UART_SMR_BDS                    *((volatile  uint8_t *)(0x42702008UL))
#define bFM_MFS1_UART_SMR_SBL                     *((volatile  uint8_t *)(0x4270200CUL))
#define bFM4_MFS1_UART_SMR_SBL                    *((volatile  uint8_t *)(0x4270200CUL))

#define bFM_MFS1_UART_SSR_TBI                     *((volatile  uint8_t *)(0x427020A0UL))
#define bFM4_MFS1_UART_SSR_TBI                    *((volatile  uint8_t *)(0x427020A0UL))
#define bFM_MFS1_UART_SSR_TDRE                    *((volatile  uint8_t *)(0x427020A4UL))
#define bFM4_MFS1_UART_SSR_TDRE                   *((volatile  uint8_t *)(0x427020A4UL))
#define bFM_MFS1_UART_SSR_RDRF                    *((volatile  uint8_t *)(0x427020A8UL))
#define bFM4_MFS1_UART_SSR_RDRF                   *((volatile  uint8_t *)(0x427020A8UL))
#define bFM_MFS1_UART_SSR_ORE                     *((volatile  uint8_t *)(0x427020ACUL))
#define bFM4_MFS1_UART_SSR_ORE                    *((volatile  uint8_t *)(0x427020ACUL))
#define bFM_MFS1_UART_SSR_FRE                     *((volatile  uint8_t *)(0x427020B0UL))
#define bFM4_MFS1_UART_SSR_FRE                    *((volatile  uint8_t *)(0x427020B0UL))
#define bFM_MFS1_UART_SSR_PE                      *((volatile  uint8_t *)(0x427020B4UL))
#define bFM4_MFS1_UART_SSR_PE                     *((volatile  uint8_t *)(0x427020B4UL))
#define bFM_MFS1_UART_SSR_REC                     *((volatile  uint8_t *)(0x427020BCUL))
#define bFM4_MFS1_UART_SSR_REC                    *((volatile  uint8_t *)(0x427020BCUL))


/*******************************************************************************
* MFS Registers MFS10
*   Bitband Section
*******************************************************************************/
#define bFM_MFS10_CSIO_ESCR_CSFE                  *((volatile  uint8_t *)(0x42714094UL))
#define bFM4_MFS10_CSIO_ESCR_CSFE                 *((volatile  uint8_t *)(0x42714094UL))
#define bFM_MFS10_CSIO_ESCR_L3                    *((volatile  uint8_t *)(0x42714098UL))
#define bFM4_MFS10_CSIO_ESCR_L3                   *((volatile  uint8_t *)(0x42714098UL))
#define bFM_MFS10_CSIO_ESCR_SOP                   *((volatile  uint8_t *)(0x4271409CUL))
#define bFM4_MFS10_CSIO_ESCR_SOP                  *((volatile  uint8_t *)(0x4271409CUL))

#define bFM_MFS10_CSIO_FCR_FE1                    *((volatile  uint8_t *)(0x42714280UL))
#define bFM4_MFS10_CSIO_FCR_FE1                   *((volatile  uint8_t *)(0x42714280UL))
#define bFM_MFS10_CSIO_FCR_FE2                    *((volatile  uint8_t *)(0x42714284UL))
#define bFM4_MFS10_CSIO_FCR_FE2                   *((volatile  uint8_t *)(0x42714284UL))
#define bFM_MFS10_CSIO_FCR_FCL1                   *((volatile  uint8_t *)(0x42714288UL))
#define bFM4_MFS10_CSIO_FCR_FCL1                  *((volatile  uint8_t *)(0x42714288UL))
#define bFM_MFS10_CSIO_FCR_FCL2                   *((volatile  uint8_t *)(0x4271428CUL))
#define bFM4_MFS10_CSIO_FCR_FCL2                  *((volatile  uint8_t *)(0x4271428CUL))
#define bFM_MFS10_CSIO_FCR_FSET                   *((volatile  uint8_t *)(0x42714290UL))
#define bFM4_MFS10_CSIO_FCR_FSET                  *((volatile  uint8_t *)(0x42714290UL))
#define bFM_MFS10_CSIO_FCR_FLD                    *((volatile  uint8_t *)(0x42714294UL))
#define bFM4_MFS10_CSIO_FCR_FLD                   *((volatile  uint8_t *)(0x42714294UL))
#define bFM_MFS10_CSIO_FCR_FLST                   *((volatile  uint8_t *)(0x42714298UL))
#define bFM4_MFS10_CSIO_FCR_FLST                  *((volatile  uint8_t *)(0x42714298UL))
#define bFM_MFS10_CSIO_FCR_FSEL                   *((volatile  uint8_t *)(0x427142A0UL))
#define bFM4_MFS10_CSIO_FCR_FSEL                  *((volatile  uint8_t *)(0x427142A0UL))
#define bFM_MFS10_CSIO_FCR_FTIE                   *((volatile  uint8_t *)(0x427142A4UL))
#define bFM4_MFS10_CSIO_FCR_FTIE                  *((volatile  uint8_t *)(0x427142A4UL))
#define bFM_MFS10_CSIO_FCR_FDRQ                   *((volatile  uint8_t *)(0x427142A8UL))
#define bFM4_MFS10_CSIO_FCR_FDRQ                  *((volatile  uint8_t *)(0x427142A8UL))
#define bFM_MFS10_CSIO_FCR_FRIIE                  *((volatile  uint8_t *)(0x427142ACUL))
#define bFM4_MFS10_CSIO_FCR_FRIIE                 *((volatile  uint8_t *)(0x427142ACUL))
#define bFM_MFS10_CSIO_FCR_FLSTE                  *((volatile  uint8_t *)(0x427142B0UL))
#define bFM4_MFS10_CSIO_FCR_FLSTE                 *((volatile  uint8_t *)(0x427142B0UL))

#define bFM_MFS10_CSIO_SACSR_TMRE                 *((volatile  uint8_t *)(0x42714480UL))
#define bFM4_MFS10_CSIO_SACSR_TMRE                *((volatile  uint8_t *)(0x42714480UL))
#define bFM_MFS10_CSIO_SACSR_TSYNE                *((volatile  uint8_t *)(0x42714498UL))
#define bFM4_MFS10_CSIO_SACSR_TSYNE               *((volatile  uint8_t *)(0x42714498UL))
#define bFM_MFS10_CSIO_SACSR_TINTE                *((volatile  uint8_t *)(0x4271449CUL))
#define bFM4_MFS10_CSIO_SACSR_TINTE               *((volatile  uint8_t *)(0x4271449CUL))
#define bFM_MFS10_CSIO_SACSR_TINT                 *((volatile  uint8_t *)(0x427144A0UL))
#define bFM4_MFS10_CSIO_SACSR_TINT                *((volatile  uint8_t *)(0x427144A0UL))
#define bFM_MFS10_CSIO_SACSR_CSE                  *((volatile  uint8_t *)(0x427144ACUL))
#define bFM4_MFS10_CSIO_SACSR_CSE                 *((volatile  uint8_t *)(0x427144ACUL))
#define bFM_MFS10_CSIO_SACSR_CSEIE                *((volatile  uint8_t *)(0x427144B0UL))
#define bFM4_MFS10_CSIO_SACSR_CSEIE               *((volatile  uint8_t *)(0x427144B0UL))
#define bFM_MFS10_CSIO_SACSR_TBEEN                *((volatile  uint8_t *)(0x427144B4UL))
#define bFM4_MFS10_CSIO_SACSR_TBEEN               *((volatile  uint8_t *)(0x427144B4UL))

#define bFM_MFS10_CSIO_SCR_TXE                    *((volatile  uint8_t *)(0x42714020UL))
#define bFM4_MFS10_CSIO_SCR_TXE                   *((volatile  uint8_t *)(0x42714020UL))
#define bFM_MFS10_CSIO_SCR_RXE                    *((volatile  uint8_t *)(0x42714024UL))
#define bFM4_MFS10_CSIO_SCR_RXE                   *((volatile  uint8_t *)(0x42714024UL))
#define bFM_MFS10_CSIO_SCR_TBIE                   *((volatile  uint8_t *)(0x42714028UL))
#define bFM4_MFS10_CSIO_SCR_TBIE                  *((volatile  uint8_t *)(0x42714028UL))
#define bFM_MFS10_CSIO_SCR_TIE                    *((volatile  uint8_t *)(0x4271402CUL))
#define bFM4_MFS10_CSIO_SCR_TIE                   *((volatile  uint8_t *)(0x4271402CUL))
#define bFM_MFS10_CSIO_SCR_RIE                    *((volatile  uint8_t *)(0x42714030UL))
#define bFM4_MFS10_CSIO_SCR_RIE                   *((volatile  uint8_t *)(0x42714030UL))
#define bFM_MFS10_CSIO_SCR_SPI                    *((volatile  uint8_t *)(0x42714034UL))
#define bFM4_MFS10_CSIO_SCR_SPI                   *((volatile  uint8_t *)(0x42714034UL))
#define bFM_MFS10_CSIO_SCR_MS                     *((volatile  uint8_t *)(0x42714038UL))
#define bFM4_MFS10_CSIO_SCR_MS                    *((volatile  uint8_t *)(0x42714038UL))
#define bFM_MFS10_CSIO_SCR_UPCL                   *((volatile  uint8_t *)(0x4271403CUL))
#define bFM4_MFS10_CSIO_SCR_UPCL                  *((volatile  uint8_t *)(0x4271403CUL))

#define bFM_MFS10_CSIO_SCSCR_CSOE                 *((volatile  uint8_t *)(0x42714600UL))
#define bFM4_MFS10_CSIO_SCSCR_CSOE                *((volatile  uint8_t *)(0x42714600UL))
#define bFM_MFS10_CSIO_SCSCR_CSEN0                *((volatile  uint8_t *)(0x42714604UL))
#define bFM4_MFS10_CSIO_SCSCR_CSEN0               *((volatile  uint8_t *)(0x42714604UL))
#define bFM_MFS10_CSIO_SCSCR_CSEN1                *((volatile  uint8_t *)(0x42714608UL))
#define bFM4_MFS10_CSIO_SCSCR_CSEN1               *((volatile  uint8_t *)(0x42714608UL))
#define bFM_MFS10_CSIO_SCSCR_CSEN2                *((volatile  uint8_t *)(0x4271460CUL))
#define bFM4_MFS10_CSIO_SCSCR_CSEN2               *((volatile  uint8_t *)(0x4271460CUL))
#define bFM_MFS10_CSIO_SCSCR_CSEN3                *((volatile  uint8_t *)(0x42714610UL))
#define bFM4_MFS10_CSIO_SCSCR_CSEN3               *((volatile  uint8_t *)(0x42714610UL))
#define bFM_MFS10_CSIO_SCSCR_CSLVL                *((volatile  uint8_t *)(0x42714614UL))
#define bFM4_MFS10_CSIO_SCSCR_CSLVL               *((volatile  uint8_t *)(0x42714614UL))
#define bFM_MFS10_CSIO_SCSCR_SCAM                 *((volatile  uint8_t *)(0x42714624UL))
#define bFM4_MFS10_CSIO_SCSCR_SCAM                *((volatile  uint8_t *)(0x42714624UL))

#define bFM_MFS10_CSIO_SCSFR0_CS1SPI              *((volatile  uint8_t *)(0x42714694UL))
#define bFM4_MFS10_CSIO_SCSFR0_CS1SPI             *((volatile  uint8_t *)(0x42714694UL))
#define bFM_MFS10_CSIO_SCSFR0_CS1SCINV            *((volatile  uint8_t *)(0x42714698UL))
#define bFM4_MFS10_CSIO_SCSFR0_CS1SCINV           *((volatile  uint8_t *)(0x42714698UL))
#define bFM_MFS10_CSIO_SCSFR0_CS1CSLVL            *((volatile  uint8_t *)(0x4271469CUL))
#define bFM4_MFS10_CSIO_SCSFR0_CS1CSLVL           *((volatile  uint8_t *)(0x4271469CUL))

#define bFM_MFS10_CSIO_SCSFR1_CS2SPI              *((volatile  uint8_t *)(0x427146B4UL))
#define bFM4_MFS10_CSIO_SCSFR1_CS2SPI             *((volatile  uint8_t *)(0x427146B4UL))
#define bFM_MFS10_CSIO_SCSFR1_CS2SCINV            *((volatile  uint8_t *)(0x427146B8UL))
#define bFM4_MFS10_CSIO_SCSFR1_CS2SCINV           *((volatile  uint8_t *)(0x427146B8UL))
#define bFM_MFS10_CSIO_SCSFR1_CS2CSLVL            *((volatile  uint8_t *)(0x427146BCUL))
#define bFM4_MFS10_CSIO_SCSFR1_CS2CSLVL           *((volatile  uint8_t *)(0x427146BCUL))

#define bFM_MFS10_CSIO_SCSFR2_CS3SPI              *((volatile  uint8_t *)(0x42714714UL))
#define bFM4_MFS10_CSIO_SCSFR2_CS3SPI             *((volatile  uint8_t *)(0x42714714UL))
#define bFM_MFS10_CSIO_SCSFR2_CS3SCINV            *((volatile  uint8_t *)(0x42714718UL))
#define bFM4_MFS10_CSIO_SCSFR2_CS3SCINV           *((volatile  uint8_t *)(0x42714718UL))
#define bFM_MFS10_CSIO_SCSFR2_CS3CSLVL            *((volatile  uint8_t *)(0x4271471CUL))
#define bFM4_MFS10_CSIO_SCSFR2_CS3CSLVL           *((volatile  uint8_t *)(0x4271471CUL))

#define bFM_MFS10_CSIO_SMR_SOE                    *((volatile  uint8_t *)(0x42714000UL))
#define bFM4_MFS10_CSIO_SMR_SOE                   *((volatile  uint8_t *)(0x42714000UL))
#define bFM_MFS10_CSIO_SMR_SCKE                   *((volatile  uint8_t *)(0x42714004UL))
#define bFM4_MFS10_CSIO_SMR_SCKE                  *((volatile  uint8_t *)(0x42714004UL))
#define bFM_MFS10_CSIO_SMR_BDS                    *((volatile  uint8_t *)(0x42714008UL))
#define bFM4_MFS10_CSIO_SMR_BDS                   *((volatile  uint8_t *)(0x42714008UL))
#define bFM_MFS10_CSIO_SMR_SCINV                  *((volatile  uint8_t *)(0x4271400CUL))
#define bFM4_MFS10_CSIO_SMR_SCINV                 *((volatile  uint8_t *)(0x4271400CUL))

#define bFM_MFS10_CSIO_SSR_TBI                    *((volatile  uint8_t *)(0x427140A0UL))
#define bFM4_MFS10_CSIO_SSR_TBI                   *((volatile  uint8_t *)(0x427140A0UL))
#define bFM_MFS10_CSIO_SSR_TDRE                   *((volatile  uint8_t *)(0x427140A4UL))
#define bFM4_MFS10_CSIO_SSR_TDRE                  *((volatile  uint8_t *)(0x427140A4UL))
#define bFM_MFS10_CSIO_SSR_RDRF                   *((volatile  uint8_t *)(0x427140A8UL))
#define bFM4_MFS10_CSIO_SSR_RDRF                  *((volatile  uint8_t *)(0x427140A8UL))
#define bFM_MFS10_CSIO_SSR_ORE                    *((volatile  uint8_t *)(0x427140ACUL))
#define bFM4_MFS10_CSIO_SSR_ORE                   *((volatile  uint8_t *)(0x427140ACUL))
#define bFM_MFS10_CSIO_SSR_AWC                    *((volatile  uint8_t *)(0x427140B0UL))
#define bFM4_MFS10_CSIO_SSR_AWC                   *((volatile  uint8_t *)(0x427140B0UL))
#define bFM_MFS10_CSIO_SSR_REC                    *((volatile  uint8_t *)(0x427140BCUL))
#define bFM4_MFS10_CSIO_SSR_REC                   *((volatile  uint8_t *)(0x427140BCUL))

#define bFM_MFS10_I2C_EIBCR_BEC                   *((volatile  uint8_t *)(0x427143A0UL))
#define bFM4_MFS10_I2C_EIBCR_BEC                  *((volatile  uint8_t *)(0x427143A0UL))
#define bFM_MFS10_I2C_EIBCR_SOCE                  *((volatile  uint8_t *)(0x427143A4UL))
#define bFM4_MFS10_I2C_EIBCR_SOCE                 *((volatile  uint8_t *)(0x427143A4UL))
#define bFM_MFS10_I2C_EIBCR_SCLC                  *((volatile  uint8_t *)(0x427143A8UL))
#define bFM4_MFS10_I2C_EIBCR_SCLC                 *((volatile  uint8_t *)(0x427143A8UL))
#define bFM_MFS10_I2C_EIBCR_SDAC                  *((volatile  uint8_t *)(0x427143ACUL))
#define bFM4_MFS10_I2C_EIBCR_SDAC                 *((volatile  uint8_t *)(0x427143ACUL))
#define bFM_MFS10_I2C_EIBCR_SCLS                  *((volatile  uint8_t *)(0x427143B0UL))
#define bFM4_MFS10_I2C_EIBCR_SCLS                 *((volatile  uint8_t *)(0x427143B0UL))
#define bFM_MFS10_I2C_EIBCR_SDAS                  *((volatile  uint8_t *)(0x427143B4UL))
#define bFM4_MFS10_I2C_EIBCR_SDAS                 *((volatile  uint8_t *)(0x427143B4UL))

#define bFM_MFS10_I2C_FCR_FE1                     *((volatile  uint8_t *)(0x42714280UL))
#define bFM4_MFS10_I2C_FCR_FE1                    *((volatile  uint8_t *)(0x42714280UL))
#define bFM_MFS10_I2C_FCR_FE2                     *((volatile  uint8_t *)(0x42714284UL))
#define bFM4_MFS10_I2C_FCR_FE2                    *((volatile  uint8_t *)(0x42714284UL))
#define bFM_MFS10_I2C_FCR_FCL1                    *((volatile  uint8_t *)(0x42714288UL))
#define bFM4_MFS10_I2C_FCR_FCL1                   *((volatile  uint8_t *)(0x42714288UL))
#define bFM_MFS10_I2C_FCR_FCL2                    *((volatile  uint8_t *)(0x4271428CUL))
#define bFM4_MFS10_I2C_FCR_FCL2                   *((volatile  uint8_t *)(0x4271428CUL))
#define bFM_MFS10_I2C_FCR_FSET                    *((volatile  uint8_t *)(0x42714290UL))
#define bFM4_MFS10_I2C_FCR_FSET                   *((volatile  uint8_t *)(0x42714290UL))
#define bFM_MFS10_I2C_FCR_FLD                     *((volatile  uint8_t *)(0x42714294UL))
#define bFM4_MFS10_I2C_FCR_FLD                    *((volatile  uint8_t *)(0x42714294UL))
#define bFM_MFS10_I2C_FCR_FLST                    *((volatile  uint8_t *)(0x42714298UL))
#define bFM4_MFS10_I2C_FCR_FLST                   *((volatile  uint8_t *)(0x42714298UL))
#define bFM_MFS10_I2C_FCR_FSEL                    *((volatile  uint8_t *)(0x427142A0UL))
#define bFM4_MFS10_I2C_FCR_FSEL                   *((volatile  uint8_t *)(0x427142A0UL))
#define bFM_MFS10_I2C_FCR_FTIE                    *((volatile  uint8_t *)(0x427142A4UL))
#define bFM4_MFS10_I2C_FCR_FTIE                   *((volatile  uint8_t *)(0x427142A4UL))
#define bFM_MFS10_I2C_FCR_FDRQ                    *((volatile  uint8_t *)(0x427142A8UL))
#define bFM4_MFS10_I2C_FCR_FDRQ                   *((volatile  uint8_t *)(0x427142A8UL))
#define bFM_MFS10_I2C_FCR_FRIIE                   *((volatile  uint8_t *)(0x427142ACUL))
#define bFM4_MFS10_I2C_FCR_FRIIE                  *((volatile  uint8_t *)(0x427142ACUL))
#define bFM_MFS10_I2C_FCR_FLSTE                   *((volatile  uint8_t *)(0x427142B0UL))
#define bFM4_MFS10_I2C_FCR_FLSTE                  *((volatile  uint8_t *)(0x427142B0UL))

#define bFM_MFS10_I2C_IBCR_INT                    *((volatile  uint8_t *)(0x42714020UL))
#define bFM4_MFS10_I2C_IBCR_INT                   *((volatile  uint8_t *)(0x42714020UL))
#define bFM_MFS10_I2C_IBCR_BER                    *((volatile  uint8_t *)(0x42714024UL))
#define bFM4_MFS10_I2C_IBCR_BER                   *((volatile  uint8_t *)(0x42714024UL))
#define bFM_MFS10_I2C_IBCR_INTE                   *((volatile  uint8_t *)(0x42714028UL))
#define bFM4_MFS10_I2C_IBCR_INTE                  *((volatile  uint8_t *)(0x42714028UL))
#define bFM_MFS10_I2C_IBCR_CNDE                   *((volatile  uint8_t *)(0x4271402CUL))
#define bFM4_MFS10_I2C_IBCR_CNDE                  *((volatile  uint8_t *)(0x4271402CUL))
#define bFM_MFS10_I2C_IBCR_WSEL                   *((volatile  uint8_t *)(0x42714030UL))
#define bFM4_MFS10_I2C_IBCR_WSEL                  *((volatile  uint8_t *)(0x42714030UL))
#define bFM_MFS10_I2C_IBCR_ACKE                   *((volatile  uint8_t *)(0x42714034UL))
#define bFM4_MFS10_I2C_IBCR_ACKE                  *((volatile  uint8_t *)(0x42714034UL))
#define bFM_MFS10_I2C_IBCR_ACT_SCC                *((volatile  uint8_t *)(0x42714038UL))
#define bFM4_MFS10_I2C_IBCR_ACT_SCC               *((volatile  uint8_t *)(0x42714038UL))
#define bFM_MFS10_I2C_IBCR_MSS                    *((volatile  uint8_t *)(0x4271403CUL))
#define bFM4_MFS10_I2C_IBCR_MSS                   *((volatile  uint8_t *)(0x4271403CUL))

#define bFM_MFS10_I2C_IBSR_BB                     *((volatile  uint8_t *)(0x42714080UL))
#define bFM4_MFS10_I2C_IBSR_BB                    *((volatile  uint8_t *)(0x42714080UL))
#define bFM_MFS10_I2C_IBSR_SPC                    *((volatile  uint8_t *)(0x42714084UL))
#define bFM4_MFS10_I2C_IBSR_SPC                   *((volatile  uint8_t *)(0x42714084UL))
#define bFM_MFS10_I2C_IBSR_RSC                    *((volatile  uint8_t *)(0x42714088UL))
#define bFM4_MFS10_I2C_IBSR_RSC                   *((volatile  uint8_t *)(0x42714088UL))
#define bFM_MFS10_I2C_IBSR_AL                     *((volatile  uint8_t *)(0x4271408CUL))
#define bFM4_MFS10_I2C_IBSR_AL                    *((volatile  uint8_t *)(0x4271408CUL))
#define bFM_MFS10_I2C_IBSR_TRX                    *((volatile  uint8_t *)(0x42714090UL))
#define bFM4_MFS10_I2C_IBSR_TRX                   *((volatile  uint8_t *)(0x42714090UL))
#define bFM_MFS10_I2C_IBSR_RSA                    *((volatile  uint8_t *)(0x42714094UL))
#define bFM4_MFS10_I2C_IBSR_RSA                   *((volatile  uint8_t *)(0x42714094UL))
#define bFM_MFS10_I2C_IBSR_RACK                   *((volatile  uint8_t *)(0x42714098UL))
#define bFM4_MFS10_I2C_IBSR_RACK                  *((volatile  uint8_t *)(0x42714098UL))
#define bFM_MFS10_I2C_IBSR_FBT                    *((volatile  uint8_t *)(0x4271409CUL))
#define bFM4_MFS10_I2C_IBSR_FBT                   *((volatile  uint8_t *)(0x4271409CUL))

#define bFM_MFS10_I2C_ISBA_SAEN                   *((volatile  uint8_t *)(0x4271421CUL))
#define bFM4_MFS10_I2C_ISBA_SAEN                  *((volatile  uint8_t *)(0x4271421CUL))

#define bFM_MFS10_I2C_ISMK_EN                     *((volatile  uint8_t *)(0x4271423CUL))
#define bFM4_MFS10_I2C_ISMK_EN                    *((volatile  uint8_t *)(0x4271423CUL))

#define bFM_MFS10_I2C_SMR_TIE                     *((volatile  uint8_t *)(0x42714008UL))
#define bFM4_MFS10_I2C_SMR_TIE                    *((volatile  uint8_t *)(0x42714008UL))
#define bFM_MFS10_I2C_SMR_RIE                     *((volatile  uint8_t *)(0x4271400CUL))
#define bFM4_MFS10_I2C_SMR_RIE                    *((volatile  uint8_t *)(0x4271400CUL))

#define bFM_MFS10_I2C_SSR_TBI                     *((volatile  uint8_t *)(0x427140A0UL))
#define bFM4_MFS10_I2C_SSR_TBI                    *((volatile  uint8_t *)(0x427140A0UL))
#define bFM_MFS10_I2C_SSR_TDRE                    *((volatile  uint8_t *)(0x427140A4UL))
#define bFM4_MFS10_I2C_SSR_TDRE                   *((volatile  uint8_t *)(0x427140A4UL))
#define bFM_MFS10_I2C_SSR_RDRF                    *((volatile  uint8_t *)(0x427140A8UL))
#define bFM4_MFS10_I2C_SSR_RDRF                   *((volatile  uint8_t *)(0x427140A8UL))
#define bFM_MFS10_I2C_SSR_ORE                     *((volatile  uint8_t *)(0x427140ACUL))
#define bFM4_MFS10_I2C_SSR_ORE                    *((volatile  uint8_t *)(0x427140ACUL))
#define bFM_MFS10_I2C_SSR_TBIE                    *((volatile  uint8_t *)(0x427140B0UL))
#define bFM4_MFS10_I2C_SSR_TBIE                   *((volatile  uint8_t *)(0x427140B0UL))
#define bFM_MFS10_I2C_SSR_DMA                     *((volatile  uint8_t *)(0x427140B4UL))
#define bFM4_MFS10_I2C_SSR_DMA                    *((volatile  uint8_t *)(0x427140B4UL))
#define bFM_MFS10_I2C_SSR_TSET                    *((volatile  uint8_t *)(0x427140B8UL))
#define bFM4_MFS10_I2C_SSR_TSET                   *((volatile  uint8_t *)(0x427140B8UL))
#define bFM_MFS10_I2C_SSR_REC                     *((volatile  uint8_t *)(0x427140BCUL))
#define bFM4_MFS10_I2C_SSR_REC                    *((volatile  uint8_t *)(0x427140BCUL))

#define bFM_MFS10_LIN_BGR_EXT                     *((volatile  uint8_t *)(0x427141BCUL))
#define bFM4_MFS10_LIN_BGR_EXT                    *((volatile  uint8_t *)(0x427141BCUL))

#define bFM_MFS10_LIN_ESCR_LBIE                   *((volatile  uint8_t *)(0x42714090UL))
#define bFM4_MFS10_LIN_ESCR_LBIE                  *((volatile  uint8_t *)(0x42714090UL))
#define bFM_MFS10_LIN_ESCR_ESBL                   *((volatile  uint8_t *)(0x42714098UL))
#define bFM4_MFS10_LIN_ESCR_ESBL                  *((volatile  uint8_t *)(0x42714098UL))

#define bFM_MFS10_LIN_FCR_FE1                     *((volatile  uint8_t *)(0x42714280UL))
#define bFM4_MFS10_LIN_FCR_FE1                    *((volatile  uint8_t *)(0x42714280UL))
#define bFM_MFS10_LIN_FCR_FE2                     *((volatile  uint8_t *)(0x42714284UL))
#define bFM4_MFS10_LIN_FCR_FE2                    *((volatile  uint8_t *)(0x42714284UL))
#define bFM_MFS10_LIN_FCR_FCL1                    *((volatile  uint8_t *)(0x42714288UL))
#define bFM4_MFS10_LIN_FCR_FCL1                   *((volatile  uint8_t *)(0x42714288UL))
#define bFM_MFS10_LIN_FCR_FCL2                    *((volatile  uint8_t *)(0x4271428CUL))
#define bFM4_MFS10_LIN_FCR_FCL2                   *((volatile  uint8_t *)(0x4271428CUL))
#define bFM_MFS10_LIN_FCR_FSET                    *((volatile  uint8_t *)(0x42714290UL))
#define bFM4_MFS10_LIN_FCR_FSET                   *((volatile  uint8_t *)(0x42714290UL))
#define bFM_MFS10_LIN_FCR_FLD                     *((volatile  uint8_t *)(0x42714294UL))
#define bFM4_MFS10_LIN_FCR_FLD                    *((volatile  uint8_t *)(0x42714294UL))
#define bFM_MFS10_LIN_FCR_FLST                    *((volatile  uint8_t *)(0x42714298UL))
#define bFM4_MFS10_LIN_FCR_FLST                   *((volatile  uint8_t *)(0x42714298UL))
#define bFM_MFS10_LIN_FCR_FSEL                    *((volatile  uint8_t *)(0x427142A0UL))
#define bFM4_MFS10_LIN_FCR_FSEL                   *((volatile  uint8_t *)(0x427142A0UL))
#define bFM_MFS10_LIN_FCR_FTIE                    *((volatile  uint8_t *)(0x427142A4UL))
#define bFM4_MFS10_LIN_FCR_FTIE                   *((volatile  uint8_t *)(0x427142A4UL))
#define bFM_MFS10_LIN_FCR_FDRQ                    *((volatile  uint8_t *)(0x427142A8UL))
#define bFM4_MFS10_LIN_FCR_FDRQ                   *((volatile  uint8_t *)(0x427142A8UL))
#define bFM_MFS10_LIN_FCR_FRIIE                   *((volatile  uint8_t *)(0x427142ACUL))
#define bFM4_MFS10_LIN_FCR_FRIIE                  *((volatile  uint8_t *)(0x427142ACUL))
#define bFM_MFS10_LIN_FCR_FLSTE                   *((volatile  uint8_t *)(0x427142B0UL))
#define bFM4_MFS10_LIN_FCR_FLSTE                  *((volatile  uint8_t *)(0x427142B0UL))

#define bFM_MFS10_LIN_SCR_TXE                     *((volatile  uint8_t *)(0x42714020UL))
#define bFM4_MFS10_LIN_SCR_TXE                    *((volatile  uint8_t *)(0x42714020UL))
#define bFM_MFS10_LIN_SCR_RXE                     *((volatile  uint8_t *)(0x42714024UL))
#define bFM4_MFS10_LIN_SCR_RXE                    *((volatile  uint8_t *)(0x42714024UL))
#define bFM_MFS10_LIN_SCR_TBIE                    *((volatile  uint8_t *)(0x42714028UL))
#define bFM4_MFS10_LIN_SCR_TBIE                   *((volatile  uint8_t *)(0x42714028UL))
#define bFM_MFS10_LIN_SCR_TIE                     *((volatile  uint8_t *)(0x4271402CUL))
#define bFM4_MFS10_LIN_SCR_TIE                    *((volatile  uint8_t *)(0x4271402CUL))
#define bFM_MFS10_LIN_SCR_RIE                     *((volatile  uint8_t *)(0x42714030UL))
#define bFM4_MFS10_LIN_SCR_RIE                    *((volatile  uint8_t *)(0x42714030UL))
#define bFM_MFS10_LIN_SCR_LBR                     *((volatile  uint8_t *)(0x42714034UL))
#define bFM4_MFS10_LIN_SCR_LBR                    *((volatile  uint8_t *)(0x42714034UL))
#define bFM_MFS10_LIN_SCR_MS                      *((volatile  uint8_t *)(0x42714038UL))
#define bFM4_MFS10_LIN_SCR_MS                     *((volatile  uint8_t *)(0x42714038UL))
#define bFM_MFS10_LIN_SCR_UPCL                    *((volatile  uint8_t *)(0x4271403CUL))
#define bFM4_MFS10_LIN_SCR_UPCL                   *((volatile  uint8_t *)(0x4271403CUL))

#define bFM_MFS10_LIN_SMR_SOE                     *((volatile  uint8_t *)(0x42714000UL))
#define bFM4_MFS10_LIN_SMR_SOE                    *((volatile  uint8_t *)(0x42714000UL))
#define bFM_MFS10_LIN_SMR_SBL                     *((volatile  uint8_t *)(0x4271400CUL))
#define bFM4_MFS10_LIN_SMR_SBL                    *((volatile  uint8_t *)(0x4271400CUL))
#define bFM_MFS10_LIN_SMR_WUCR                    *((volatile  uint8_t *)(0x42714010UL))
#define bFM4_MFS10_LIN_SMR_WUCR                   *((volatile  uint8_t *)(0x42714010UL))

#define bFM_MFS10_LIN_SSR_TBI                     *((volatile  uint8_t *)(0x427140A0UL))
#define bFM4_MFS10_LIN_SSR_TBI                    *((volatile  uint8_t *)(0x427140A0UL))
#define bFM_MFS10_LIN_SSR_TDRE                    *((volatile  uint8_t *)(0x427140A4UL))
#define bFM4_MFS10_LIN_SSR_TDRE                   *((volatile  uint8_t *)(0x427140A4UL))
#define bFM_MFS10_LIN_SSR_RDRF                    *((volatile  uint8_t *)(0x427140A8UL))
#define bFM4_MFS10_LIN_SSR_RDRF                   *((volatile  uint8_t *)(0x427140A8UL))
#define bFM_MFS10_LIN_SSR_ORE                     *((volatile  uint8_t *)(0x427140ACUL))
#define bFM4_MFS10_LIN_SSR_ORE                    *((volatile  uint8_t *)(0x427140ACUL))
#define bFM_MFS10_LIN_SSR_FRE                     *((volatile  uint8_t *)(0x427140B0UL))
#define bFM4_MFS10_LIN_SSR_FRE                    *((volatile  uint8_t *)(0x427140B0UL))
#define bFM_MFS10_LIN_SSR_LBD                     *((volatile  uint8_t *)(0x427140B4UL))
#define bFM4_MFS10_LIN_SSR_LBD                    *((volatile  uint8_t *)(0x427140B4UL))
#define bFM_MFS10_LIN_SSR_REC                     *((volatile  uint8_t *)(0x427140BCUL))
#define bFM4_MFS10_LIN_SSR_REC                    *((volatile  uint8_t *)(0x427140BCUL))

#define bFM_MFS10_UART_BGR_EXT                    *((volatile  uint8_t *)(0x427141BCUL))
#define bFM4_MFS10_UART_BGR_EXT                   *((volatile  uint8_t *)(0x427141BCUL))

#define bFM_MFS10_UART_ESCR_P                     *((volatile  uint8_t *)(0x4271408CUL))
#define bFM4_MFS10_UART_ESCR_P                    *((volatile  uint8_t *)(0x4271408CUL))
#define bFM_MFS10_UART_ESCR_PEN                   *((volatile  uint8_t *)(0x42714090UL))
#define bFM4_MFS10_UART_ESCR_PEN                  *((volatile  uint8_t *)(0x42714090UL))
#define bFM_MFS10_UART_ESCR_INV                   *((volatile  uint8_t *)(0x42714094UL))
#define bFM4_MFS10_UART_ESCR_INV                  *((volatile  uint8_t *)(0x42714094UL))
#define bFM_MFS10_UART_ESCR_ESBL                  *((volatile  uint8_t *)(0x42714098UL))
#define bFM4_MFS10_UART_ESCR_ESBL                 *((volatile  uint8_t *)(0x42714098UL))
#define bFM_MFS10_UART_ESCR_FLWEN                 *((volatile  uint8_t *)(0x4271409CUL))
#define bFM4_MFS10_UART_ESCR_FLWEN                *((volatile  uint8_t *)(0x4271409CUL))

#define bFM_MFS10_UART_FCR_FE1                    *((volatile  uint8_t *)(0x42714280UL))
#define bFM4_MFS10_UART_FCR_FE1                   *((volatile  uint8_t *)(0x42714280UL))
#define bFM_MFS10_UART_FCR_FE2                    *((volatile  uint8_t *)(0x42714284UL))
#define bFM4_MFS10_UART_FCR_FE2                   *((volatile  uint8_t *)(0x42714284UL))
#define bFM_MFS10_UART_FCR_FCL1                   *((volatile  uint8_t *)(0x42714288UL))
#define bFM4_MFS10_UART_FCR_FCL1                  *((volatile  uint8_t *)(0x42714288UL))
#define bFM_MFS10_UART_FCR_FCL2                   *((volatile  uint8_t *)(0x4271428CUL))
#define bFM4_MFS10_UART_FCR_FCL2                  *((volatile  uint8_t *)(0x4271428CUL))
#define bFM_MFS10_UART_FCR_FSET                   *((volatile  uint8_t *)(0x42714290UL))
#define bFM4_MFS10_UART_FCR_FSET                  *((volatile  uint8_t *)(0x42714290UL))
#define bFM_MFS10_UART_FCR_FLD                    *((volatile  uint8_t *)(0x42714294UL))
#define bFM4_MFS10_UART_FCR_FLD                   *((volatile  uint8_t *)(0x42714294UL))
#define bFM_MFS10_UART_FCR_FLST                   *((volatile  uint8_t *)(0x42714298UL))
#define bFM4_MFS10_UART_FCR_FLST                  *((volatile  uint8_t *)(0x42714298UL))
#define bFM_MFS10_UART_FCR_FSEL                   *((volatile  uint8_t *)(0x427142A0UL))
#define bFM4_MFS10_UART_FCR_FSEL                  *((volatile  uint8_t *)(0x427142A0UL))
#define bFM_MFS10_UART_FCR_FTIE                   *((volatile  uint8_t *)(0x427142A4UL))
#define bFM4_MFS10_UART_FCR_FTIE                  *((volatile  uint8_t *)(0x427142A4UL))
#define bFM_MFS10_UART_FCR_FDRQ                   *((volatile  uint8_t *)(0x427142A8UL))
#define bFM4_MFS10_UART_FCR_FDRQ                  *((volatile  uint8_t *)(0x427142A8UL))
#define bFM_MFS10_UART_FCR_FRIIE                  *((volatile  uint8_t *)(0x427142ACUL))
#define bFM4_MFS10_UART_FCR_FRIIE                 *((volatile  uint8_t *)(0x427142ACUL))
#define bFM_MFS10_UART_FCR_FLSTE                  *((volatile  uint8_t *)(0x427142B0UL))
#define bFM4_MFS10_UART_FCR_FLSTE                 *((volatile  uint8_t *)(0x427142B0UL))

#define bFM_MFS10_UART_SCR_TXE                    *((volatile  uint8_t *)(0x42714020UL))
#define bFM4_MFS10_UART_SCR_TXE                   *((volatile  uint8_t *)(0x42714020UL))
#define bFM_MFS10_UART_SCR_RXE                    *((volatile  uint8_t *)(0x42714024UL))
#define bFM4_MFS10_UART_SCR_RXE                   *((volatile  uint8_t *)(0x42714024UL))
#define bFM_MFS10_UART_SCR_TBIE                   *((volatile  uint8_t *)(0x42714028UL))
#define bFM4_MFS10_UART_SCR_TBIE                  *((volatile  uint8_t *)(0x42714028UL))
#define bFM_MFS10_UART_SCR_TIE                    *((volatile  uint8_t *)(0x4271402CUL))
#define bFM4_MFS10_UART_SCR_TIE                   *((volatile  uint8_t *)(0x4271402CUL))
#define bFM_MFS10_UART_SCR_RIE                    *((volatile  uint8_t *)(0x42714030UL))
#define bFM4_MFS10_UART_SCR_RIE                   *((volatile  uint8_t *)(0x42714030UL))
#define bFM_MFS10_UART_SCR_UPCL                   *((volatile  uint8_t *)(0x4271403CUL))
#define bFM4_MFS10_UART_SCR_UPCL                  *((volatile  uint8_t *)(0x4271403CUL))

#define bFM_MFS10_UART_SMR_SOE                    *((volatile  uint8_t *)(0x42714000UL))
#define bFM4_MFS10_UART_SMR_SOE                   *((volatile  uint8_t *)(0x42714000UL))
#define bFM_MFS10_UART_SMR_BDS                    *((volatile  uint8_t *)(0x42714008UL))
#define bFM4_MFS10_UART_SMR_BDS                   *((volatile  uint8_t *)(0x42714008UL))
#define bFM_MFS10_UART_SMR_SBL                    *((volatile  uint8_t *)(0x4271400CUL))
#define bFM4_MFS10_UART_SMR_SBL                   *((volatile  uint8_t *)(0x4271400CUL))

#define bFM_MFS10_UART_SSR_TBI                    *((volatile  uint8_t *)(0x427140A0UL))
#define bFM4_MFS10_UART_SSR_TBI                   *((volatile  uint8_t *)(0x427140A0UL))
#define bFM_MFS10_UART_SSR_TDRE                   *((volatile  uint8_t *)(0x427140A4UL))
#define bFM4_MFS10_UART_SSR_TDRE                  *((volatile  uint8_t *)(0x427140A4UL))
#define bFM_MFS10_UART_SSR_RDRF                   *((volatile  uint8_t *)(0x427140A8UL))
#define bFM4_MFS10_UART_SSR_RDRF                  *((volatile  uint8_t *)(0x427140A8UL))
#define bFM_MFS10_UART_SSR_ORE                    *((volatile  uint8_t *)(0x427140ACUL))
#define bFM4_MFS10_UART_SSR_ORE                   *((volatile  uint8_t *)(0x427140ACUL))
#define bFM_MFS10_UART_SSR_FRE                    *((volatile  uint8_t *)(0x427140B0UL))
#define bFM4_MFS10_UART_SSR_FRE                   *((volatile  uint8_t *)(0x427140B0UL))
#define bFM_MFS10_UART_SSR_PE                     *((volatile  uint8_t *)(0x427140B4UL))
#define bFM4_MFS10_UART_SSR_PE                    *((volatile  uint8_t *)(0x427140B4UL))
#define bFM_MFS10_UART_SSR_REC                    *((volatile  uint8_t *)(0x427140BCUL))
#define bFM4_MFS10_UART_SSR_REC                   *((volatile  uint8_t *)(0x427140BCUL))


/*******************************************************************************
* MFS Registers MFS11
*   Bitband Section
*******************************************************************************/
#define bFM_MFS11_CSIO_ESCR_CSFE                  *((volatile  uint8_t *)(0x42716094UL))
#define bFM4_MFS11_CSIO_ESCR_CSFE                 *((volatile  uint8_t *)(0x42716094UL))
#define bFM_MFS11_CSIO_ESCR_L3                    *((volatile  uint8_t *)(0x42716098UL))
#define bFM4_MFS11_CSIO_ESCR_L3                   *((volatile  uint8_t *)(0x42716098UL))
#define bFM_MFS11_CSIO_ESCR_SOP                   *((volatile  uint8_t *)(0x4271609CUL))
#define bFM4_MFS11_CSIO_ESCR_SOP                  *((volatile  uint8_t *)(0x4271609CUL))

#define bFM_MFS11_CSIO_FCR_FE1                    *((volatile  uint8_t *)(0x42716280UL))
#define bFM4_MFS11_CSIO_FCR_FE1                   *((volatile  uint8_t *)(0x42716280UL))
#define bFM_MFS11_CSIO_FCR_FE2                    *((volatile  uint8_t *)(0x42716284UL))
#define bFM4_MFS11_CSIO_FCR_FE2                   *((volatile  uint8_t *)(0x42716284UL))
#define bFM_MFS11_CSIO_FCR_FCL1                   *((volatile  uint8_t *)(0x42716288UL))
#define bFM4_MFS11_CSIO_FCR_FCL1                  *((volatile  uint8_t *)(0x42716288UL))
#define bFM_MFS11_CSIO_FCR_FCL2                   *((volatile  uint8_t *)(0x4271628CUL))
#define bFM4_MFS11_CSIO_FCR_FCL2                  *((volatile  uint8_t *)(0x4271628CUL))
#define bFM_MFS11_CSIO_FCR_FSET                   *((volatile  uint8_t *)(0x42716290UL))
#define bFM4_MFS11_CSIO_FCR_FSET                  *((volatile  uint8_t *)(0x42716290UL))
#define bFM_MFS11_CSIO_FCR_FLD                    *((volatile  uint8_t *)(0x42716294UL))
#define bFM4_MFS11_CSIO_FCR_FLD                   *((volatile  uint8_t *)(0x42716294UL))
#define bFM_MFS11_CSIO_FCR_FLST                   *((volatile  uint8_t *)(0x42716298UL))
#define bFM4_MFS11_CSIO_FCR_FLST                  *((volatile  uint8_t *)(0x42716298UL))
#define bFM_MFS11_CSIO_FCR_FSEL                   *((volatile  uint8_t *)(0x427162A0UL))
#define bFM4_MFS11_CSIO_FCR_FSEL                  *((volatile  uint8_t *)(0x427162A0UL))
#define bFM_MFS11_CSIO_FCR_FTIE                   *((volatile  uint8_t *)(0x427162A4UL))
#define bFM4_MFS11_CSIO_FCR_FTIE                  *((volatile  uint8_t *)(0x427162A4UL))
#define bFM_MFS11_CSIO_FCR_FDRQ                   *((volatile  uint8_t *)(0x427162A8UL))
#define bFM4_MFS11_CSIO_FCR_FDRQ                  *((volatile  uint8_t *)(0x427162A8UL))
#define bFM_MFS11_CSIO_FCR_FRIIE                  *((volatile  uint8_t *)(0x427162ACUL))
#define bFM4_MFS11_CSIO_FCR_FRIIE                 *((volatile  uint8_t *)(0x427162ACUL))
#define bFM_MFS11_CSIO_FCR_FLSTE                  *((volatile  uint8_t *)(0x427162B0UL))
#define bFM4_MFS11_CSIO_FCR_FLSTE                 *((volatile  uint8_t *)(0x427162B0UL))

#define bFM_MFS11_CSIO_SACSR_TMRE                 *((volatile  uint8_t *)(0x42716480UL))
#define bFM4_MFS11_CSIO_SACSR_TMRE                *((volatile  uint8_t *)(0x42716480UL))
#define bFM_MFS11_CSIO_SACSR_TSYNE                *((volatile  uint8_t *)(0x42716498UL))
#define bFM4_MFS11_CSIO_SACSR_TSYNE               *((volatile  uint8_t *)(0x42716498UL))
#define bFM_MFS11_CSIO_SACSR_TINTE                *((volatile  uint8_t *)(0x4271649CUL))
#define bFM4_MFS11_CSIO_SACSR_TINTE               *((volatile  uint8_t *)(0x4271649CUL))
#define bFM_MFS11_CSIO_SACSR_TINT                 *((volatile  uint8_t *)(0x427164A0UL))
#define bFM4_MFS11_CSIO_SACSR_TINT                *((volatile  uint8_t *)(0x427164A0UL))
#define bFM_MFS11_CSIO_SACSR_CSE                  *((volatile  uint8_t *)(0x427164ACUL))
#define bFM4_MFS11_CSIO_SACSR_CSE                 *((volatile  uint8_t *)(0x427164ACUL))
#define bFM_MFS11_CSIO_SACSR_CSEIE                *((volatile  uint8_t *)(0x427164B0UL))
#define bFM4_MFS11_CSIO_SACSR_CSEIE               *((volatile  uint8_t *)(0x427164B0UL))
#define bFM_MFS11_CSIO_SACSR_TBEEN                *((volatile  uint8_t *)(0x427164B4UL))
#define bFM4_MFS11_CSIO_SACSR_TBEEN               *((volatile  uint8_t *)(0x427164B4UL))

#define bFM_MFS11_CSIO_SCR_TXE                    *((volatile  uint8_t *)(0x42716020UL))
#define bFM4_MFS11_CSIO_SCR_TXE                   *((volatile  uint8_t *)(0x42716020UL))
#define bFM_MFS11_CSIO_SCR_RXE                    *((volatile  uint8_t *)(0x42716024UL))
#define bFM4_MFS11_CSIO_SCR_RXE                   *((volatile  uint8_t *)(0x42716024UL))
#define bFM_MFS11_CSIO_SCR_TBIE                   *((volatile  uint8_t *)(0x42716028UL))
#define bFM4_MFS11_CSIO_SCR_TBIE                  *((volatile  uint8_t *)(0x42716028UL))
#define bFM_MFS11_CSIO_SCR_TIE                    *((volatile  uint8_t *)(0x4271602CUL))
#define bFM4_MFS11_CSIO_SCR_TIE                   *((volatile  uint8_t *)(0x4271602CUL))
#define bFM_MFS11_CSIO_SCR_RIE                    *((volatile  uint8_t *)(0x42716030UL))
#define bFM4_MFS11_CSIO_SCR_RIE                   *((volatile  uint8_t *)(0x42716030UL))
#define bFM_MFS11_CSIO_SCR_SPI                    *((volatile  uint8_t *)(0x42716034UL))
#define bFM4_MFS11_CSIO_SCR_SPI                   *((volatile  uint8_t *)(0x42716034UL))
#define bFM_MFS11_CSIO_SCR_MS                     *((volatile  uint8_t *)(0x42716038UL))
#define bFM4_MFS11_CSIO_SCR_MS                    *((volatile  uint8_t *)(0x42716038UL))
#define bFM_MFS11_CSIO_SCR_UPCL                   *((volatile  uint8_t *)(0x4271603CUL))
#define bFM4_MFS11_CSIO_SCR_UPCL                  *((volatile  uint8_t *)(0x4271603CUL))

#define bFM_MFS11_CSIO_SCSCR_CSOE                 *((volatile  uint8_t *)(0x42716600UL))
#define bFM4_MFS11_CSIO_SCSCR_CSOE                *((volatile  uint8_t *)(0x42716600UL))
#define bFM_MFS11_CSIO_SCSCR_CSEN0                *((volatile  uint8_t *)(0x42716604UL))
#define bFM4_MFS11_CSIO_SCSCR_CSEN0               *((volatile  uint8_t *)(0x42716604UL))
#define bFM_MFS11_CSIO_SCSCR_CSEN1                *((volatile  uint8_t *)(0x42716608UL))
#define bFM4_MFS11_CSIO_SCSCR_CSEN1               *((volatile  uint8_t *)(0x42716608UL))
#define bFM_MFS11_CSIO_SCSCR_CSEN2                *((volatile  uint8_t *)(0x4271660CUL))
#define bFM4_MFS11_CSIO_SCSCR_CSEN2               *((volatile  uint8_t *)(0x4271660CUL))
#define bFM_MFS11_CSIO_SCSCR_CSEN3                *((volatile  uint8_t *)(0x42716610UL))
#define bFM4_MFS11_CSIO_SCSCR_CSEN3               *((volatile  uint8_t *)(0x42716610UL))
#define bFM_MFS11_CSIO_SCSCR_CSLVL                *((volatile  uint8_t *)(0x42716614UL))
#define bFM4_MFS11_CSIO_SCSCR_CSLVL               *((volatile  uint8_t *)(0x42716614UL))
#define bFM_MFS11_CSIO_SCSCR_SCAM                 *((volatile  uint8_t *)(0x42716624UL))
#define bFM4_MFS11_CSIO_SCSCR_SCAM                *((volatile  uint8_t *)(0x42716624UL))

#define bFM_MFS11_CSIO_SCSFR0_CS1SPI              *((volatile  uint8_t *)(0x42716694UL))
#define bFM4_MFS11_CSIO_SCSFR0_CS1SPI             *((volatile  uint8_t *)(0x42716694UL))
#define bFM_MFS11_CSIO_SCSFR0_CS1SCINV            *((volatile  uint8_t *)(0x42716698UL))
#define bFM4_MFS11_CSIO_SCSFR0_CS1SCINV           *((volatile  uint8_t *)(0x42716698UL))
#define bFM_MFS11_CSIO_SCSFR0_CS1CSLVL            *((volatile  uint8_t *)(0x4271669CUL))
#define bFM4_MFS11_CSIO_SCSFR0_CS1CSLVL           *((volatile  uint8_t *)(0x4271669CUL))

#define bFM_MFS11_CSIO_SCSFR1_CS2SPI              *((volatile  uint8_t *)(0x427166B4UL))
#define bFM4_MFS11_CSIO_SCSFR1_CS2SPI             *((volatile  uint8_t *)(0x427166B4UL))
#define bFM_MFS11_CSIO_SCSFR1_CS2SCINV            *((volatile  uint8_t *)(0x427166B8UL))
#define bFM4_MFS11_CSIO_SCSFR1_CS2SCINV           *((volatile  uint8_t *)(0x427166B8UL))
#define bFM_MFS11_CSIO_SCSFR1_CS2CSLVL            *((volatile  uint8_t *)(0x427166BCUL))
#define bFM4_MFS11_CSIO_SCSFR1_CS2CSLVL           *((volatile  uint8_t *)(0x427166BCUL))

#define bFM_MFS11_CSIO_SCSFR2_CS3SPI              *((volatile  uint8_t *)(0x42716714UL))
#define bFM4_MFS11_CSIO_SCSFR2_CS3SPI             *((volatile  uint8_t *)(0x42716714UL))
#define bFM_MFS11_CSIO_SCSFR2_CS3SCINV            *((volatile  uint8_t *)(0x42716718UL))
#define bFM4_MFS11_CSIO_SCSFR2_CS3SCINV           *((volatile  uint8_t *)(0x42716718UL))
#define bFM_MFS11_CSIO_SCSFR2_CS3CSLVL            *((volatile  uint8_t *)(0x4271671CUL))
#define bFM4_MFS11_CSIO_SCSFR2_CS3CSLVL           *((volatile  uint8_t *)(0x4271671CUL))

#define bFM_MFS11_CSIO_SMR_SOE                    *((volatile  uint8_t *)(0x42716000UL))
#define bFM4_MFS11_CSIO_SMR_SOE                   *((volatile  uint8_t *)(0x42716000UL))
#define bFM_MFS11_CSIO_SMR_SCKE                   *((volatile  uint8_t *)(0x42716004UL))
#define bFM4_MFS11_CSIO_SMR_SCKE                  *((volatile  uint8_t *)(0x42716004UL))
#define bFM_MFS11_CSIO_SMR_BDS                    *((volatile  uint8_t *)(0x42716008UL))
#define bFM4_MFS11_CSIO_SMR_BDS                   *((volatile  uint8_t *)(0x42716008UL))
#define bFM_MFS11_CSIO_SMR_SCINV                  *((volatile  uint8_t *)(0x4271600CUL))
#define bFM4_MFS11_CSIO_SMR_SCINV                 *((volatile  uint8_t *)(0x4271600CUL))

#define bFM_MFS11_CSIO_SSR_TBI                    *((volatile  uint8_t *)(0x427160A0UL))
#define bFM4_MFS11_CSIO_SSR_TBI                   *((volatile  uint8_t *)(0x427160A0UL))
#define bFM_MFS11_CSIO_SSR_TDRE                   *((volatile  uint8_t *)(0x427160A4UL))
#define bFM4_MFS11_CSIO_SSR_TDRE                  *((volatile  uint8_t *)(0x427160A4UL))
#define bFM_MFS11_CSIO_SSR_RDRF                   *((volatile  uint8_t *)(0x427160A8UL))
#define bFM4_MFS11_CSIO_SSR_RDRF                  *((volatile  uint8_t *)(0x427160A8UL))
#define bFM_MFS11_CSIO_SSR_ORE                    *((volatile  uint8_t *)(0x427160ACUL))
#define bFM4_MFS11_CSIO_SSR_ORE                   *((volatile  uint8_t *)(0x427160ACUL))
#define bFM_MFS11_CSIO_SSR_AWC                    *((volatile  uint8_t *)(0x427160B0UL))
#define bFM4_MFS11_CSIO_SSR_AWC                   *((volatile  uint8_t *)(0x427160B0UL))
#define bFM_MFS11_CSIO_SSR_REC                    *((volatile  uint8_t *)(0x427160BCUL))
#define bFM4_MFS11_CSIO_SSR_REC                   *((volatile  uint8_t *)(0x427160BCUL))

#define bFM_MFS11_I2C_EIBCR_BEC                   *((volatile  uint8_t *)(0x427163A0UL))
#define bFM4_MFS11_I2C_EIBCR_BEC                  *((volatile  uint8_t *)(0x427163A0UL))
#define bFM_MFS11_I2C_EIBCR_SOCE                  *((volatile  uint8_t *)(0x427163A4UL))
#define bFM4_MFS11_I2C_EIBCR_SOCE                 *((volatile  uint8_t *)(0x427163A4UL))
#define bFM_MFS11_I2C_EIBCR_SCLC                  *((volatile  uint8_t *)(0x427163A8UL))
#define bFM4_MFS11_I2C_EIBCR_SCLC                 *((volatile  uint8_t *)(0x427163A8UL))
#define bFM_MFS11_I2C_EIBCR_SDAC                  *((volatile  uint8_t *)(0x427163ACUL))
#define bFM4_MFS11_I2C_EIBCR_SDAC                 *((volatile  uint8_t *)(0x427163ACUL))
#define bFM_MFS11_I2C_EIBCR_SCLS                  *((volatile  uint8_t *)(0x427163B0UL))
#define bFM4_MFS11_I2C_EIBCR_SCLS                 *((volatile  uint8_t *)(0x427163B0UL))
#define bFM_MFS11_I2C_EIBCR_SDAS                  *((volatile  uint8_t *)(0x427163B4UL))
#define bFM4_MFS11_I2C_EIBCR_SDAS                 *((volatile  uint8_t *)(0x427163B4UL))

#define bFM_MFS11_I2C_FCR_FE1                     *((volatile  uint8_t *)(0x42716280UL))
#define bFM4_MFS11_I2C_FCR_FE1                    *((volatile  uint8_t *)(0x42716280UL))
#define bFM_MFS11_I2C_FCR_FE2                     *((volatile  uint8_t *)(0x42716284UL))
#define bFM4_MFS11_I2C_FCR_FE2                    *((volatile  uint8_t *)(0x42716284UL))
#define bFM_MFS11_I2C_FCR_FCL1                    *((volatile  uint8_t *)(0x42716288UL))
#define bFM4_MFS11_I2C_FCR_FCL1                   *((volatile  uint8_t *)(0x42716288UL))
#define bFM_MFS11_I2C_FCR_FCL2                    *((volatile  uint8_t *)(0x4271628CUL))
#define bFM4_MFS11_I2C_FCR_FCL2                   *((volatile  uint8_t *)(0x4271628CUL))
#define bFM_MFS11_I2C_FCR_FSET                    *((volatile  uint8_t *)(0x42716290UL))
#define bFM4_MFS11_I2C_FCR_FSET                   *((volatile  uint8_t *)(0x42716290UL))
#define bFM_MFS11_I2C_FCR_FLD                     *((volatile  uint8_t *)(0x42716294UL))
#define bFM4_MFS11_I2C_FCR_FLD                    *((volatile  uint8_t *)(0x42716294UL))
#define bFM_MFS11_I2C_FCR_FLST                    *((volatile  uint8_t *)(0x42716298UL))
#define bFM4_MFS11_I2C_FCR_FLST                   *((volatile  uint8_t *)(0x42716298UL))
#define bFM_MFS11_I2C_FCR_FSEL                    *((volatile  uint8_t *)(0x427162A0UL))
#define bFM4_MFS11_I2C_FCR_FSEL                   *((volatile  uint8_t *)(0x427162A0UL))
#define bFM_MFS11_I2C_FCR_FTIE                    *((volatile  uint8_t *)(0x427162A4UL))
#define bFM4_MFS11_I2C_FCR_FTIE                   *((volatile  uint8_t *)(0x427162A4UL))
#define bFM_MFS11_I2C_FCR_FDRQ                    *((volatile  uint8_t *)(0x427162A8UL))
#define bFM4_MFS11_I2C_FCR_FDRQ                   *((volatile  uint8_t *)(0x427162A8UL))
#define bFM_MFS11_I2C_FCR_FRIIE                   *((volatile  uint8_t *)(0x427162ACUL))
#define bFM4_MFS11_I2C_FCR_FRIIE                  *((volatile  uint8_t *)(0x427162ACUL))
#define bFM_MFS11_I2C_FCR_FLSTE                   *((volatile  uint8_t *)(0x427162B0UL))
#define bFM4_MFS11_I2C_FCR_FLSTE                  *((volatile  uint8_t *)(0x427162B0UL))

#define bFM_MFS11_I2C_IBCR_INT                    *((volatile  uint8_t *)(0x42716020UL))
#define bFM4_MFS11_I2C_IBCR_INT                   *((volatile  uint8_t *)(0x42716020UL))
#define bFM_MFS11_I2C_IBCR_BER                    *((volatile  uint8_t *)(0x42716024UL))
#define bFM4_MFS11_I2C_IBCR_BER                   *((volatile  uint8_t *)(0x42716024UL))
#define bFM_MFS11_I2C_IBCR_INTE                   *((volatile  uint8_t *)(0x42716028UL))
#define bFM4_MFS11_I2C_IBCR_INTE                  *((volatile  uint8_t *)(0x42716028UL))
#define bFM_MFS11_I2C_IBCR_CNDE                   *((volatile  uint8_t *)(0x4271602CUL))
#define bFM4_MFS11_I2C_IBCR_CNDE                  *((volatile  uint8_t *)(0x4271602CUL))
#define bFM_MFS11_I2C_IBCR_WSEL                   *((volatile  uint8_t *)(0x42716030UL))
#define bFM4_MFS11_I2C_IBCR_WSEL                  *((volatile  uint8_t *)(0x42716030UL))
#define bFM_MFS11_I2C_IBCR_ACKE                   *((volatile  uint8_t *)(0x42716034UL))
#define bFM4_MFS11_I2C_IBCR_ACKE                  *((volatile  uint8_t *)(0x42716034UL))
#define bFM_MFS11_I2C_IBCR_ACT_SCC                *((volatile  uint8_t *)(0x42716038UL))
#define bFM4_MFS11_I2C_IBCR_ACT_SCC               *((volatile  uint8_t *)(0x42716038UL))
#define bFM_MFS11_I2C_IBCR_MSS                    *((volatile  uint8_t *)(0x4271603CUL))
#define bFM4_MFS11_I2C_IBCR_MSS                   *((volatile  uint8_t *)(0x4271603CUL))

#define bFM_MFS11_I2C_IBSR_BB                     *((volatile  uint8_t *)(0x42716080UL))
#define bFM4_MFS11_I2C_IBSR_BB                    *((volatile  uint8_t *)(0x42716080UL))
#define bFM_MFS11_I2C_IBSR_SPC                    *((volatile  uint8_t *)(0x42716084UL))
#define bFM4_MFS11_I2C_IBSR_SPC                   *((volatile  uint8_t *)(0x42716084UL))
#define bFM_MFS11_I2C_IBSR_RSC                    *((volatile  uint8_t *)(0x42716088UL))
#define bFM4_MFS11_I2C_IBSR_RSC                   *((volatile  uint8_t *)(0x42716088UL))
#define bFM_MFS11_I2C_IBSR_AL                     *((volatile  uint8_t *)(0x4271608CUL))
#define bFM4_MFS11_I2C_IBSR_AL                    *((volatile  uint8_t *)(0x4271608CUL))
#define bFM_MFS11_I2C_IBSR_TRX                    *((volatile  uint8_t *)(0x42716090UL))
#define bFM4_MFS11_I2C_IBSR_TRX                   *((volatile  uint8_t *)(0x42716090UL))
#define bFM_MFS11_I2C_IBSR_RSA                    *((volatile  uint8_t *)(0x42716094UL))
#define bFM4_MFS11_I2C_IBSR_RSA                   *((volatile  uint8_t *)(0x42716094UL))
#define bFM_MFS11_I2C_IBSR_RACK                   *((volatile  uint8_t *)(0x42716098UL))
#define bFM4_MFS11_I2C_IBSR_RACK                  *((volatile  uint8_t *)(0x42716098UL))
#define bFM_MFS11_I2C_IBSR_FBT                    *((volatile  uint8_t *)(0x4271609CUL))
#define bFM4_MFS11_I2C_IBSR_FBT                   *((volatile  uint8_t *)(0x4271609CUL))

#define bFM_MFS11_I2C_ISBA_SAEN                   *((volatile  uint8_t *)(0x4271621CUL))
#define bFM4_MFS11_I2C_ISBA_SAEN                  *((volatile  uint8_t *)(0x4271621CUL))

#define bFM_MFS11_I2C_ISMK_EN                     *((volatile  uint8_t *)(0x4271623CUL))
#define bFM4_MFS11_I2C_ISMK_EN                    *((volatile  uint8_t *)(0x4271623CUL))

#define bFM_MFS11_I2C_SMR_TIE                     *((volatile  uint8_t *)(0x42716008UL))
#define bFM4_MFS11_I2C_SMR_TIE                    *((volatile  uint8_t *)(0x42716008UL))
#define bFM_MFS11_I2C_SMR_RIE                     *((volatile  uint8_t *)(0x4271600CUL))
#define bFM4_MFS11_I2C_SMR_RIE                    *((volatile  uint8_t *)(0x4271600CUL))

#define bFM_MFS11_I2C_SSR_TBI                     *((volatile  uint8_t *)(0x427160A0UL))
#define bFM4_MFS11_I2C_SSR_TBI                    *((volatile  uint8_t *)(0x427160A0UL))
#define bFM_MFS11_I2C_SSR_TDRE                    *((volatile  uint8_t *)(0x427160A4UL))
#define bFM4_MFS11_I2C_SSR_TDRE                   *((volatile  uint8_t *)(0x427160A4UL))
#define bFM_MFS11_I2C_SSR_RDRF                    *((volatile  uint8_t *)(0x427160A8UL))
#define bFM4_MFS11_I2C_SSR_RDRF                   *((volatile  uint8_t *)(0x427160A8UL))
#define bFM_MFS11_I2C_SSR_ORE                     *((volatile  uint8_t *)(0x427160ACUL))
#define bFM4_MFS11_I2C_SSR_ORE                    *((volatile  uint8_t *)(0x427160ACUL))
#define bFM_MFS11_I2C_SSR_TBIE                    *((volatile  uint8_t *)(0x427160B0UL))
#define bFM4_MFS11_I2C_SSR_TBIE                   *((volatile  uint8_t *)(0x427160B0UL))
#define bFM_MFS11_I2C_SSR_DMA                     *((volatile  uint8_t *)(0x427160B4UL))
#define bFM4_MFS11_I2C_SSR_DMA                    *((volatile  uint8_t *)(0x427160B4UL))
#define bFM_MFS11_I2C_SSR_TSET                    *((volatile  uint8_t *)(0x427160B8UL))
#define bFM4_MFS11_I2C_SSR_TSET                   *((volatile  uint8_t *)(0x427160B8UL))
#define bFM_MFS11_I2C_SSR_REC                     *((volatile  uint8_t *)(0x427160BCUL))
#define bFM4_MFS11_I2C_SSR_REC                    *((volatile  uint8_t *)(0x427160BCUL))

#define bFM_MFS11_LIN_BGR_EXT                     *((volatile  uint8_t *)(0x427161BCUL))
#define bFM4_MFS11_LIN_BGR_EXT                    *((volatile  uint8_t *)(0x427161BCUL))

#define bFM_MFS11_LIN_ESCR_LBIE                   *((volatile  uint8_t *)(0x42716090UL))
#define bFM4_MFS11_LIN_ESCR_LBIE                  *((volatile  uint8_t *)(0x42716090UL))
#define bFM_MFS11_LIN_ESCR_ESBL                   *((volatile  uint8_t *)(0x42716098UL))
#define bFM4_MFS11_LIN_ESCR_ESBL                  *((volatile  uint8_t *)(0x42716098UL))

#define bFM_MFS11_LIN_FCR_FE1                     *((volatile  uint8_t *)(0x42716280UL))
#define bFM4_MFS11_LIN_FCR_FE1                    *((volatile  uint8_t *)(0x42716280UL))
#define bFM_MFS11_LIN_FCR_FE2                     *((volatile  uint8_t *)(0x42716284UL))
#define bFM4_MFS11_LIN_FCR_FE2                    *((volatile  uint8_t *)(0x42716284UL))
#define bFM_MFS11_LIN_FCR_FCL1                    *((volatile  uint8_t *)(0x42716288UL))
#define bFM4_MFS11_LIN_FCR_FCL1                   *((volatile  uint8_t *)(0x42716288UL))
#define bFM_MFS11_LIN_FCR_FCL2                    *((volatile  uint8_t *)(0x4271628CUL))
#define bFM4_MFS11_LIN_FCR_FCL2                   *((volatile  uint8_t *)(0x4271628CUL))
#define bFM_MFS11_LIN_FCR_FSET                    *((volatile  uint8_t *)(0x42716290UL))
#define bFM4_MFS11_LIN_FCR_FSET                   *((volatile  uint8_t *)(0x42716290UL))
#define bFM_MFS11_LIN_FCR_FLD                     *((volatile  uint8_t *)(0x42716294UL))
#define bFM4_MFS11_LIN_FCR_FLD                    *((volatile  uint8_t *)(0x42716294UL))
#define bFM_MFS11_LIN_FCR_FLST                    *((volatile  uint8_t *)(0x42716298UL))
#define bFM4_MFS11_LIN_FCR_FLST                   *((volatile  uint8_t *)(0x42716298UL))
#define bFM_MFS11_LIN_FCR_FSEL                    *((volatile  uint8_t *)(0x427162A0UL))
#define bFM4_MFS11_LIN_FCR_FSEL                   *((volatile  uint8_t *)(0x427162A0UL))
#define bFM_MFS11_LIN_FCR_FTIE                    *((volatile  uint8_t *)(0x427162A4UL))
#define bFM4_MFS11_LIN_FCR_FTIE                   *((volatile  uint8_t *)(0x427162A4UL))
#define bFM_MFS11_LIN_FCR_FDRQ                    *((volatile  uint8_t *)(0x427162A8UL))
#define bFM4_MFS11_LIN_FCR_FDRQ                   *((volatile  uint8_t *)(0x427162A8UL))
#define bFM_MFS11_LIN_FCR_FRIIE                   *((volatile  uint8_t *)(0x427162ACUL))
#define bFM4_MFS11_LIN_FCR_FRIIE                  *((volatile  uint8_t *)(0x427162ACUL))
#define bFM_MFS11_LIN_FCR_FLSTE                   *((volatile  uint8_t *)(0x427162B0UL))
#define bFM4_MFS11_LIN_FCR_FLSTE                  *((volatile  uint8_t *)(0x427162B0UL))

#define bFM_MFS11_LIN_SCR_TXE                     *((volatile  uint8_t *)(0x42716020UL))
#define bFM4_MFS11_LIN_SCR_TXE                    *((volatile  uint8_t *)(0x42716020UL))
#define bFM_MFS11_LIN_SCR_RXE                     *((volatile  uint8_t *)(0x42716024UL))
#define bFM4_MFS11_LIN_SCR_RXE                    *((volatile  uint8_t *)(0x42716024UL))
#define bFM_MFS11_LIN_SCR_TBIE                    *((volatile  uint8_t *)(0x42716028UL))
#define bFM4_MFS11_LIN_SCR_TBIE                   *((volatile  uint8_t *)(0x42716028UL))
#define bFM_MFS11_LIN_SCR_TIE                     *((volatile  uint8_t *)(0x4271602CUL))
#define bFM4_MFS11_LIN_SCR_TIE                    *((volatile  uint8_t *)(0x4271602CUL))
#define bFM_MFS11_LIN_SCR_RIE                     *((volatile  uint8_t *)(0x42716030UL))
#define bFM4_MFS11_LIN_SCR_RIE                    *((volatile  uint8_t *)(0x42716030UL))
#define bFM_MFS11_LIN_SCR_LBR                     *((volatile  uint8_t *)(0x42716034UL))
#define bFM4_MFS11_LIN_SCR_LBR                    *((volatile  uint8_t *)(0x42716034UL))
#define bFM_MFS11_LIN_SCR_MS                      *((volatile  uint8_t *)(0x42716038UL))
#define bFM4_MFS11_LIN_SCR_MS                     *((volatile  uint8_t *)(0x42716038UL))
#define bFM_MFS11_LIN_SCR_UPCL                    *((volatile  uint8_t *)(0x4271603CUL))
#define bFM4_MFS11_LIN_SCR_UPCL                   *((volatile  uint8_t *)(0x4271603CUL))

#define bFM_MFS11_LIN_SMR_SOE                     *((volatile  uint8_t *)(0x42716000UL))
#define bFM4_MFS11_LIN_SMR_SOE                    *((volatile  uint8_t *)(0x42716000UL))
#define bFM_MFS11_LIN_SMR_SBL                     *((volatile  uint8_t *)(0x4271600CUL))
#define bFM4_MFS11_LIN_SMR_SBL                    *((volatile  uint8_t *)(0x4271600CUL))
#define bFM_MFS11_LIN_SMR_WUCR                    *((volatile  uint8_t *)(0x42716010UL))
#define bFM4_MFS11_LIN_SMR_WUCR                   *((volatile  uint8_t *)(0x42716010UL))

#define bFM_MFS11_LIN_SSR_TBI                     *((volatile  uint8_t *)(0x427160A0UL))
#define bFM4_MFS11_LIN_SSR_TBI                    *((volatile  uint8_t *)(0x427160A0UL))
#define bFM_MFS11_LIN_SSR_TDRE                    *((volatile  uint8_t *)(0x427160A4UL))
#define bFM4_MFS11_LIN_SSR_TDRE                   *((volatile  uint8_t *)(0x427160A4UL))
#define bFM_MFS11_LIN_SSR_RDRF                    *((volatile  uint8_t *)(0x427160A8UL))
#define bFM4_MFS11_LIN_SSR_RDRF                   *((volatile  uint8_t *)(0x427160A8UL))
#define bFM_MFS11_LIN_SSR_ORE                     *((volatile  uint8_t *)(0x427160ACUL))
#define bFM4_MFS11_LIN_SSR_ORE                    *((volatile  uint8_t *)(0x427160ACUL))
#define bFM_MFS11_LIN_SSR_FRE                     *((volatile  uint8_t *)(0x427160B0UL))
#define bFM4_MFS11_LIN_SSR_FRE                    *((volatile  uint8_t *)(0x427160B0UL))
#define bFM_MFS11_LIN_SSR_LBD                     *((volatile  uint8_t *)(0x427160B4UL))
#define bFM4_MFS11_LIN_SSR_LBD                    *((volatile  uint8_t *)(0x427160B4UL))
#define bFM_MFS11_LIN_SSR_REC                     *((volatile  uint8_t *)(0x427160BCUL))
#define bFM4_MFS11_LIN_SSR_REC                    *((volatile  uint8_t *)(0x427160BCUL))

#define bFM_MFS11_UART_BGR_EXT                    *((volatile  uint8_t *)(0x427161BCUL))
#define bFM4_MFS11_UART_BGR_EXT                   *((volatile  uint8_t *)(0x427161BCUL))

#define bFM_MFS11_UART_ESCR_P                     *((volatile  uint8_t *)(0x4271608CUL))
#define bFM4_MFS11_UART_ESCR_P                    *((volatile  uint8_t *)(0x4271608CUL))
#define bFM_MFS11_UART_ESCR_PEN                   *((volatile  uint8_t *)(0x42716090UL))
#define bFM4_MFS11_UART_ESCR_PEN                  *((volatile  uint8_t *)(0x42716090UL))
#define bFM_MFS11_UART_ESCR_INV                   *((volatile  uint8_t *)(0x42716094UL))
#define bFM4_MFS11_UART_ESCR_INV                  *((volatile  uint8_t *)(0x42716094UL))
#define bFM_MFS11_UART_ESCR_ESBL                  *((volatile  uint8_t *)(0x42716098UL))
#define bFM4_MFS11_UART_ESCR_ESBL                 *((volatile  uint8_t *)(0x42716098UL))
#define bFM_MFS11_UART_ESCR_FLWEN                 *((volatile  uint8_t *)(0x4271609CUL))
#define bFM4_MFS11_UART_ESCR_FLWEN                *((volatile  uint8_t *)(0x4271609CUL))

#define bFM_MFS11_UART_FCR_FE1                    *((volatile  uint8_t *)(0x42716280UL))
#define bFM4_MFS11_UART_FCR_FE1                   *((volatile  uint8_t *)(0x42716280UL))
#define bFM_MFS11_UART_FCR_FE2                    *((volatile  uint8_t *)(0x42716284UL))
#define bFM4_MFS11_UART_FCR_FE2                   *((volatile  uint8_t *)(0x42716284UL))
#define bFM_MFS11_UART_FCR_FCL1                   *((volatile  uint8_t *)(0x42716288UL))
#define bFM4_MFS11_UART_FCR_FCL1                  *((volatile  uint8_t *)(0x42716288UL))
#define bFM_MFS11_UART_FCR_FCL2                   *((volatile  uint8_t *)(0x4271628CUL))
#define bFM4_MFS11_UART_FCR_FCL2                  *((volatile  uint8_t *)(0x4271628CUL))
#define bFM_MFS11_UART_FCR_FSET                   *((volatile  uint8_t *)(0x42716290UL))
#define bFM4_MFS11_UART_FCR_FSET                  *((volatile  uint8_t *)(0x42716290UL))
#define bFM_MFS11_UART_FCR_FLD                    *((volatile  uint8_t *)(0x42716294UL))
#define bFM4_MFS11_UART_FCR_FLD                   *((volatile  uint8_t *)(0x42716294UL))
#define bFM_MFS11_UART_FCR_FLST                   *((volatile  uint8_t *)(0x42716298UL))
#define bFM4_MFS11_UART_FCR_FLST                  *((volatile  uint8_t *)(0x42716298UL))
#define bFM_MFS11_UART_FCR_FSEL                   *((volatile  uint8_t *)(0x427162A0UL))
#define bFM4_MFS11_UART_FCR_FSEL                  *((volatile  uint8_t *)(0x427162A0UL))
#define bFM_MFS11_UART_FCR_FTIE                   *((volatile  uint8_t *)(0x427162A4UL))
#define bFM4_MFS11_UART_FCR_FTIE                  *((volatile  uint8_t *)(0x427162A4UL))
#define bFM_MFS11_UART_FCR_FDRQ                   *((volatile  uint8_t *)(0x427162A8UL))
#define bFM4_MFS11_UART_FCR_FDRQ                  *((volatile  uint8_t *)(0x427162A8UL))
#define bFM_MFS11_UART_FCR_FRIIE                  *((volatile  uint8_t *)(0x427162ACUL))
#define bFM4_MFS11_UART_FCR_FRIIE                 *((volatile  uint8_t *)(0x427162ACUL))
#define bFM_MFS11_UART_FCR_FLSTE                  *((volatile  uint8_t *)(0x427162B0UL))
#define bFM4_MFS11_UART_FCR_FLSTE                 *((volatile  uint8_t *)(0x427162B0UL))

#define bFM_MFS11_UART_SCR_TXE                    *((volatile  uint8_t *)(0x42716020UL))
#define bFM4_MFS11_UART_SCR_TXE                   *((volatile  uint8_t *)(0x42716020UL))
#define bFM_MFS11_UART_SCR_RXE                    *((volatile  uint8_t *)(0x42716024UL))
#define bFM4_MFS11_UART_SCR_RXE                   *((volatile  uint8_t *)(0x42716024UL))
#define bFM_MFS11_UART_SCR_TBIE                   *((volatile  uint8_t *)(0x42716028UL))
#define bFM4_MFS11_UART_SCR_TBIE                  *((volatile  uint8_t *)(0x42716028UL))
#define bFM_MFS11_UART_SCR_TIE                    *((volatile  uint8_t *)(0x4271602CUL))
#define bFM4_MFS11_UART_SCR_TIE                   *((volatile  uint8_t *)(0x4271602CUL))
#define bFM_MFS11_UART_SCR_RIE                    *((volatile  uint8_t *)(0x42716030UL))
#define bFM4_MFS11_UART_SCR_RIE                   *((volatile  uint8_t *)(0x42716030UL))
#define bFM_MFS11_UART_SCR_UPCL                   *((volatile  uint8_t *)(0x4271603CUL))
#define bFM4_MFS11_UART_SCR_UPCL                  *((volatile  uint8_t *)(0x4271603CUL))

#define bFM_MFS11_UART_SMR_SOE                    *((volatile  uint8_t *)(0x42716000UL))
#define bFM4_MFS11_UART_SMR_SOE                   *((volatile  uint8_t *)(0x42716000UL))
#define bFM_MFS11_UART_SMR_BDS                    *((volatile  uint8_t *)(0x42716008UL))
#define bFM4_MFS11_UART_SMR_BDS                   *((volatile  uint8_t *)(0x42716008UL))
#define bFM_MFS11_UART_SMR_SBL                    *((volatile  uint8_t *)(0x4271600CUL))
#define bFM4_MFS11_UART_SMR_SBL                   *((volatile  uint8_t *)(0x4271600CUL))

#define bFM_MFS11_UART_SSR_TBI                    *((volatile  uint8_t *)(0x427160A0UL))
#define bFM4_MFS11_UART_SSR_TBI                   *((volatile  uint8_t *)(0x427160A0UL))
#define bFM_MFS11_UART_SSR_TDRE                   *((volatile  uint8_t *)(0x427160A4UL))
#define bFM4_MFS11_UART_SSR_TDRE                  *((volatile  uint8_t *)(0x427160A4UL))
#define bFM_MFS11_UART_SSR_RDRF                   *((volatile  uint8_t *)(0x427160A8UL))
#define bFM4_MFS11_UART_SSR_RDRF                  *((volatile  uint8_t *)(0x427160A8UL))
#define bFM_MFS11_UART_SSR_ORE                    *((volatile  uint8_t *)(0x427160ACUL))
#define bFM4_MFS11_UART_SSR_ORE                   *((volatile  uint8_t *)(0x427160ACUL))
#define bFM_MFS11_UART_SSR_FRE                    *((volatile  uint8_t *)(0x427160B0UL))
#define bFM4_MFS11_UART_SSR_FRE                   *((volatile  uint8_t *)(0x427160B0UL))
#define bFM_MFS11_UART_SSR_PE                     *((volatile  uint8_t *)(0x427160B4UL))
#define bFM4_MFS11_UART_SSR_PE                    *((volatile  uint8_t *)(0x427160B4UL))
#define bFM_MFS11_UART_SSR_REC                    *((volatile  uint8_t *)(0x427160BCUL))
#define bFM4_MFS11_UART_SSR_REC                   *((volatile  uint8_t *)(0x427160BCUL))


/*******************************************************************************
* MFS Registers MFS12
*   Bitband Section
*******************************************************************************/
#define bFM_MFS12_CSIO_ESCR_CSFE                  *((volatile  uint8_t *)(0x42718094UL))
#define bFM4_MFS12_CSIO_ESCR_CSFE                 *((volatile  uint8_t *)(0x42718094UL))
#define bFM_MFS12_CSIO_ESCR_L3                    *((volatile  uint8_t *)(0x42718098UL))
#define bFM4_MFS12_CSIO_ESCR_L3                   *((volatile  uint8_t *)(0x42718098UL))
#define bFM_MFS12_CSIO_ESCR_SOP                   *((volatile  uint8_t *)(0x4271809CUL))
#define bFM4_MFS12_CSIO_ESCR_SOP                  *((volatile  uint8_t *)(0x4271809CUL))

#define bFM_MFS12_CSIO_FCR_FE1                    *((volatile  uint8_t *)(0x42718280UL))
#define bFM4_MFS12_CSIO_FCR_FE1                   *((volatile  uint8_t *)(0x42718280UL))
#define bFM_MFS12_CSIO_FCR_FE2                    *((volatile  uint8_t *)(0x42718284UL))
#define bFM4_MFS12_CSIO_FCR_FE2                   *((volatile  uint8_t *)(0x42718284UL))
#define bFM_MFS12_CSIO_FCR_FCL1                   *((volatile  uint8_t *)(0x42718288UL))
#define bFM4_MFS12_CSIO_FCR_FCL1                  *((volatile  uint8_t *)(0x42718288UL))
#define bFM_MFS12_CSIO_FCR_FCL2                   *((volatile  uint8_t *)(0x4271828CUL))
#define bFM4_MFS12_CSIO_FCR_FCL2                  *((volatile  uint8_t *)(0x4271828CUL))
#define bFM_MFS12_CSIO_FCR_FSET                   *((volatile  uint8_t *)(0x42718290UL))
#define bFM4_MFS12_CSIO_FCR_FSET                  *((volatile  uint8_t *)(0x42718290UL))
#define bFM_MFS12_CSIO_FCR_FLD                    *((volatile  uint8_t *)(0x42718294UL))
#define bFM4_MFS12_CSIO_FCR_FLD                   *((volatile  uint8_t *)(0x42718294UL))
#define bFM_MFS12_CSIO_FCR_FLST                   *((volatile  uint8_t *)(0x42718298UL))
#define bFM4_MFS12_CSIO_FCR_FLST                  *((volatile  uint8_t *)(0x42718298UL))
#define bFM_MFS12_CSIO_FCR_FSEL                   *((volatile  uint8_t *)(0x427182A0UL))
#define bFM4_MFS12_CSIO_FCR_FSEL                  *((volatile  uint8_t *)(0x427182A0UL))
#define bFM_MFS12_CSIO_FCR_FTIE                   *((volatile  uint8_t *)(0x427182A4UL))
#define bFM4_MFS12_CSIO_FCR_FTIE                  *((volatile  uint8_t *)(0x427182A4UL))
#define bFM_MFS12_CSIO_FCR_FDRQ                   *((volatile  uint8_t *)(0x427182A8UL))
#define bFM4_MFS12_CSIO_FCR_FDRQ                  *((volatile  uint8_t *)(0x427182A8UL))
#define bFM_MFS12_CSIO_FCR_FRIIE                  *((volatile  uint8_t *)(0x427182ACUL))
#define bFM4_MFS12_CSIO_FCR_FRIIE                 *((volatile  uint8_t *)(0x427182ACUL))
#define bFM_MFS12_CSIO_FCR_FLSTE                  *((volatile  uint8_t *)(0x427182B0UL))
#define bFM4_MFS12_CSIO_FCR_FLSTE                 *((volatile  uint8_t *)(0x427182B0UL))

#define bFM_MFS12_CSIO_SACSR_TMRE                 *((volatile  uint8_t *)(0x42718480UL))
#define bFM4_MFS12_CSIO_SACSR_TMRE                *((volatile  uint8_t *)(0x42718480UL))
#define bFM_MFS12_CSIO_SACSR_TSYNE                *((volatile  uint8_t *)(0x42718498UL))
#define bFM4_MFS12_CSIO_SACSR_TSYNE               *((volatile  uint8_t *)(0x42718498UL))
#define bFM_MFS12_CSIO_SACSR_TINTE                *((volatile  uint8_t *)(0x4271849CUL))
#define bFM4_MFS12_CSIO_SACSR_TINTE               *((volatile  uint8_t *)(0x4271849CUL))
#define bFM_MFS12_CSIO_SACSR_TINT                 *((volatile  uint8_t *)(0x427184A0UL))
#define bFM4_MFS12_CSIO_SACSR_TINT                *((volatile  uint8_t *)(0x427184A0UL))
#define bFM_MFS12_CSIO_SACSR_CSE                  *((volatile  uint8_t *)(0x427184ACUL))
#define bFM4_MFS12_CSIO_SACSR_CSE                 *((volatile  uint8_t *)(0x427184ACUL))
#define bFM_MFS12_CSIO_SACSR_CSEIE                *((volatile  uint8_t *)(0x427184B0UL))
#define bFM4_MFS12_CSIO_SACSR_CSEIE               *((volatile  uint8_t *)(0x427184B0UL))
#define bFM_MFS12_CSIO_SACSR_TBEEN                *((volatile  uint8_t *)(0x427184B4UL))
#define bFM4_MFS12_CSIO_SACSR_TBEEN               *((volatile  uint8_t *)(0x427184B4UL))

#define bFM_MFS12_CSIO_SCR_TXE                    *((volatile  uint8_t *)(0x42718020UL))
#define bFM4_MFS12_CSIO_SCR_TXE                   *((volatile  uint8_t *)(0x42718020UL))
#define bFM_MFS12_CSIO_SCR_RXE                    *((volatile  uint8_t *)(0x42718024UL))
#define bFM4_MFS12_CSIO_SCR_RXE                   *((volatile  uint8_t *)(0x42718024UL))
#define bFM_MFS12_CSIO_SCR_TBIE                   *((volatile  uint8_t *)(0x42718028UL))
#define bFM4_MFS12_CSIO_SCR_TBIE                  *((volatile  uint8_t *)(0x42718028UL))
#define bFM_MFS12_CSIO_SCR_TIE                    *((volatile  uint8_t *)(0x4271802CUL))
#define bFM4_MFS12_CSIO_SCR_TIE                   *((volatile  uint8_t *)(0x4271802CUL))
#define bFM_MFS12_CSIO_SCR_RIE                    *((volatile  uint8_t *)(0x42718030UL))
#define bFM4_MFS12_CSIO_SCR_RIE                   *((volatile  uint8_t *)(0x42718030UL))
#define bFM_MFS12_CSIO_SCR_SPI                    *((volatile  uint8_t *)(0x42718034UL))
#define bFM4_MFS12_CSIO_SCR_SPI                   *((volatile  uint8_t *)(0x42718034UL))
#define bFM_MFS12_CSIO_SCR_MS                     *((volatile  uint8_t *)(0x42718038UL))
#define bFM4_MFS12_CSIO_SCR_MS                    *((volatile  uint8_t *)(0x42718038UL))
#define bFM_MFS12_CSIO_SCR_UPCL                   *((volatile  uint8_t *)(0x4271803CUL))
#define bFM4_MFS12_CSIO_SCR_UPCL                  *((volatile  uint8_t *)(0x4271803CUL))

#define bFM_MFS12_CSIO_SCSCR_CSOE                 *((volatile  uint8_t *)(0x42718600UL))
#define bFM4_MFS12_CSIO_SCSCR_CSOE                *((volatile  uint8_t *)(0x42718600UL))
#define bFM_MFS12_CSIO_SCSCR_CSEN0                *((volatile  uint8_t *)(0x42718604UL))
#define bFM4_MFS12_CSIO_SCSCR_CSEN0               *((volatile  uint8_t *)(0x42718604UL))
#define bFM_MFS12_CSIO_SCSCR_CSEN1                *((volatile  uint8_t *)(0x42718608UL))
#define bFM4_MFS12_CSIO_SCSCR_CSEN1               *((volatile  uint8_t *)(0x42718608UL))
#define bFM_MFS12_CSIO_SCSCR_CSEN2                *((volatile  uint8_t *)(0x4271860CUL))
#define bFM4_MFS12_CSIO_SCSCR_CSEN2               *((volatile  uint8_t *)(0x4271860CUL))
#define bFM_MFS12_CSIO_SCSCR_CSEN3                *((volatile  uint8_t *)(0x42718610UL))
#define bFM4_MFS12_CSIO_SCSCR_CSEN3               *((volatile  uint8_t *)(0x42718610UL))
#define bFM_MFS12_CSIO_SCSCR_CSLVL                *((volatile  uint8_t *)(0x42718614UL))
#define bFM4_MFS12_CSIO_SCSCR_CSLVL               *((volatile  uint8_t *)(0x42718614UL))
#define bFM_MFS12_CSIO_SCSCR_SCAM                 *((volatile  uint8_t *)(0x42718624UL))
#define bFM4_MFS12_CSIO_SCSCR_SCAM                *((volatile  uint8_t *)(0x42718624UL))

#define bFM_MFS12_CSIO_SCSFR0_CS1SPI              *((volatile  uint8_t *)(0x42718694UL))
#define bFM4_MFS12_CSIO_SCSFR0_CS1SPI             *((volatile  uint8_t *)(0x42718694UL))
#define bFM_MFS12_CSIO_SCSFR0_CS1SCINV            *((volatile  uint8_t *)(0x42718698UL))
#define bFM4_MFS12_CSIO_SCSFR0_CS1SCINV           *((volatile  uint8_t *)(0x42718698UL))
#define bFM_MFS12_CSIO_SCSFR0_CS1CSLVL            *((volatile  uint8_t *)(0x4271869CUL))
#define bFM4_MFS12_CSIO_SCSFR0_CS1CSLVL           *((volatile  uint8_t *)(0x4271869CUL))

#define bFM_MFS12_CSIO_SCSFR1_CS2SPI              *((volatile  uint8_t *)(0x427186B4UL))
#define bFM4_MFS12_CSIO_SCSFR1_CS2SPI             *((volatile  uint8_t *)(0x427186B4UL))
#define bFM_MFS12_CSIO_SCSFR1_CS2SCINV            *((volatile  uint8_t *)(0x427186B8UL))
#define bFM4_MFS12_CSIO_SCSFR1_CS2SCINV           *((volatile  uint8_t *)(0x427186B8UL))
#define bFM_MFS12_CSIO_SCSFR1_CS2CSLVL            *((volatile  uint8_t *)(0x427186BCUL))
#define bFM4_MFS12_CSIO_SCSFR1_CS2CSLVL           *((volatile  uint8_t *)(0x427186BCUL))

#define bFM_MFS12_CSIO_SCSFR2_CS3SPI              *((volatile  uint8_t *)(0x42718714UL))
#define bFM4_MFS12_CSIO_SCSFR2_CS3SPI             *((volatile  uint8_t *)(0x42718714UL))
#define bFM_MFS12_CSIO_SCSFR2_CS3SCINV            *((volatile  uint8_t *)(0x42718718UL))
#define bFM4_MFS12_CSIO_SCSFR2_CS3SCINV           *((volatile  uint8_t *)(0x42718718UL))
#define bFM_MFS12_CSIO_SCSFR2_CS3CSLVL            *((volatile  uint8_t *)(0x4271871CUL))
#define bFM4_MFS12_CSIO_SCSFR2_CS3CSLVL           *((volatile  uint8_t *)(0x4271871CUL))

#define bFM_MFS12_CSIO_SMR_SOE                    *((volatile  uint8_t *)(0x42718000UL))
#define bFM4_MFS12_CSIO_SMR_SOE                   *((volatile  uint8_t *)(0x42718000UL))
#define bFM_MFS12_CSIO_SMR_SCKE                   *((volatile  uint8_t *)(0x42718004UL))
#define bFM4_MFS12_CSIO_SMR_SCKE                  *((volatile  uint8_t *)(0x42718004UL))
#define bFM_MFS12_CSIO_SMR_BDS                    *((volatile  uint8_t *)(0x42718008UL))
#define bFM4_MFS12_CSIO_SMR_BDS                   *((volatile  uint8_t *)(0x42718008UL))
#define bFM_MFS12_CSIO_SMR_SCINV                  *((volatile  uint8_t *)(0x4271800CUL))
#define bFM4_MFS12_CSIO_SMR_SCINV                 *((volatile  uint8_t *)(0x4271800CUL))

#define bFM_MFS12_CSIO_SSR_TBI                    *((volatile  uint8_t *)(0x427180A0UL))
#define bFM4_MFS12_CSIO_SSR_TBI                   *((volatile  uint8_t *)(0x427180A0UL))
#define bFM_MFS12_CSIO_SSR_TDRE                   *((volatile  uint8_t *)(0x427180A4UL))
#define bFM4_MFS12_CSIO_SSR_TDRE                  *((volatile  uint8_t *)(0x427180A4UL))
#define bFM_MFS12_CSIO_SSR_RDRF                   *((volatile  uint8_t *)(0x427180A8UL))
#define bFM4_MFS12_CSIO_SSR_RDRF                  *((volatile  uint8_t *)(0x427180A8UL))
#define bFM_MFS12_CSIO_SSR_ORE                    *((volatile  uint8_t *)(0x427180ACUL))
#define bFM4_MFS12_CSIO_SSR_ORE                   *((volatile  uint8_t *)(0x427180ACUL))
#define bFM_MFS12_CSIO_SSR_AWC                    *((volatile  uint8_t *)(0x427180B0UL))
#define bFM4_MFS12_CSIO_SSR_AWC                   *((volatile  uint8_t *)(0x427180B0UL))
#define bFM_MFS12_CSIO_SSR_REC                    *((volatile  uint8_t *)(0x427180BCUL))
#define bFM4_MFS12_CSIO_SSR_REC                   *((volatile  uint8_t *)(0x427180BCUL))

#define bFM_MFS12_I2C_EIBCR_BEC                   *((volatile  uint8_t *)(0x427183A0UL))
#define bFM4_MFS12_I2C_EIBCR_BEC                  *((volatile  uint8_t *)(0x427183A0UL))
#define bFM_MFS12_I2C_EIBCR_SOCE                  *((volatile  uint8_t *)(0x427183A4UL))
#define bFM4_MFS12_I2C_EIBCR_SOCE                 *((volatile  uint8_t *)(0x427183A4UL))
#define bFM_MFS12_I2C_EIBCR_SCLC                  *((volatile  uint8_t *)(0x427183A8UL))
#define bFM4_MFS12_I2C_EIBCR_SCLC                 *((volatile  uint8_t *)(0x427183A8UL))
#define bFM_MFS12_I2C_EIBCR_SDAC                  *((volatile  uint8_t *)(0x427183ACUL))
#define bFM4_MFS12_I2C_EIBCR_SDAC                 *((volatile  uint8_t *)(0x427183ACUL))
#define bFM_MFS12_I2C_EIBCR_SCLS                  *((volatile  uint8_t *)(0x427183B0UL))
#define bFM4_MFS12_I2C_EIBCR_SCLS                 *((volatile  uint8_t *)(0x427183B0UL))
#define bFM_MFS12_I2C_EIBCR_SDAS                  *((volatile  uint8_t *)(0x427183B4UL))
#define bFM4_MFS12_I2C_EIBCR_SDAS                 *((volatile  uint8_t *)(0x427183B4UL))

#define bFM_MFS12_I2C_FCR_FE1                     *((volatile  uint8_t *)(0x42718280UL))
#define bFM4_MFS12_I2C_FCR_FE1                    *((volatile  uint8_t *)(0x42718280UL))
#define bFM_MFS12_I2C_FCR_FE2                     *((volatile  uint8_t *)(0x42718284UL))
#define bFM4_MFS12_I2C_FCR_FE2                    *((volatile  uint8_t *)(0x42718284UL))
#define bFM_MFS12_I2C_FCR_FCL1                    *((volatile  uint8_t *)(0x42718288UL))
#define bFM4_MFS12_I2C_FCR_FCL1                   *((volatile  uint8_t *)(0x42718288UL))
#define bFM_MFS12_I2C_FCR_FCL2                    *((volatile  uint8_t *)(0x4271828CUL))
#define bFM4_MFS12_I2C_FCR_FCL2                   *((volatile  uint8_t *)(0x4271828CUL))
#define bFM_MFS12_I2C_FCR_FSET                    *((volatile  uint8_t *)(0x42718290UL))
#define bFM4_MFS12_I2C_FCR_FSET                   *((volatile  uint8_t *)(0x42718290UL))
#define bFM_MFS12_I2C_FCR_FLD                     *((volatile  uint8_t *)(0x42718294UL))
#define bFM4_MFS12_I2C_FCR_FLD                    *((volatile  uint8_t *)(0x42718294UL))
#define bFM_MFS12_I2C_FCR_FLST                    *((volatile  uint8_t *)(0x42718298UL))
#define bFM4_MFS12_I2C_FCR_FLST                   *((volatile  uint8_t *)(0x42718298UL))
#define bFM_MFS12_I2C_FCR_FSEL                    *((volatile  uint8_t *)(0x427182A0UL))
#define bFM4_MFS12_I2C_FCR_FSEL                   *((volatile  uint8_t *)(0x427182A0UL))
#define bFM_MFS12_I2C_FCR_FTIE                    *((volatile  uint8_t *)(0x427182A4UL))
#define bFM4_MFS12_I2C_FCR_FTIE                   *((volatile  uint8_t *)(0x427182A4UL))
#define bFM_MFS12_I2C_FCR_FDRQ                    *((volatile  uint8_t *)(0x427182A8UL))
#define bFM4_MFS12_I2C_FCR_FDRQ                   *((volatile  uint8_t *)(0x427182A8UL))
#define bFM_MFS12_I2C_FCR_FRIIE                   *((volatile  uint8_t *)(0x427182ACUL))
#define bFM4_MFS12_I2C_FCR_FRIIE                  *((volatile  uint8_t *)(0x427182ACUL))
#define bFM_MFS12_I2C_FCR_FLSTE                   *((volatile  uint8_t *)(0x427182B0UL))
#define bFM4_MFS12_I2C_FCR_FLSTE                  *((volatile  uint8_t *)(0x427182B0UL))

#define bFM_MFS12_I2C_IBCR_INT                    *((volatile  uint8_t *)(0x42718020UL))
#define bFM4_MFS12_I2C_IBCR_INT                   *((volatile  uint8_t *)(0x42718020UL))
#define bFM_MFS12_I2C_IBCR_BER                    *((volatile  uint8_t *)(0x42718024UL))
#define bFM4_MFS12_I2C_IBCR_BER                   *((volatile  uint8_t *)(0x42718024UL))
#define bFM_MFS12_I2C_IBCR_INTE                   *((volatile  uint8_t *)(0x42718028UL))
#define bFM4_MFS12_I2C_IBCR_INTE                  *((volatile  uint8_t *)(0x42718028UL))
#define bFM_MFS12_I2C_IBCR_CNDE                   *((volatile  uint8_t *)(0x4271802CUL))
#define bFM4_MFS12_I2C_IBCR_CNDE                  *((volatile  uint8_t *)(0x4271802CUL))
#define bFM_MFS12_I2C_IBCR_WSEL                   *((volatile  uint8_t *)(0x42718030UL))
#define bFM4_MFS12_I2C_IBCR_WSEL                  *((volatile  uint8_t *)(0x42718030UL))
#define bFM_MFS12_I2C_IBCR_ACKE                   *((volatile  uint8_t *)(0x42718034UL))
#define bFM4_MFS12_I2C_IBCR_ACKE                  *((volatile  uint8_t *)(0x42718034UL))
#define bFM_MFS12_I2C_IBCR_ACT_SCC                *((volatile  uint8_t *)(0x42718038UL))
#define bFM4_MFS12_I2C_IBCR_ACT_SCC               *((volatile  uint8_t *)(0x42718038UL))
#define bFM_MFS12_I2C_IBCR_MSS                    *((volatile  uint8_t *)(0x4271803CUL))
#define bFM4_MFS12_I2C_IBCR_MSS                   *((volatile  uint8_t *)(0x4271803CUL))

#define bFM_MFS12_I2C_IBSR_BB                     *((volatile  uint8_t *)(0x42718080UL))
#define bFM4_MFS12_I2C_IBSR_BB                    *((volatile  uint8_t *)(0x42718080UL))
#define bFM_MFS12_I2C_IBSR_SPC                    *((volatile  uint8_t *)(0x42718084UL))
#define bFM4_MFS12_I2C_IBSR_SPC                   *((volatile  uint8_t *)(0x42718084UL))
#define bFM_MFS12_I2C_IBSR_RSC                    *((volatile  uint8_t *)(0x42718088UL))
#define bFM4_MFS12_I2C_IBSR_RSC                   *((volatile  uint8_t *)(0x42718088UL))
#define bFM_MFS12_I2C_IBSR_AL                     *((volatile  uint8_t *)(0x4271808CUL))
#define bFM4_MFS12_I2C_IBSR_AL                    *((volatile  uint8_t *)(0x4271808CUL))
#define bFM_MFS12_I2C_IBSR_TRX                    *((volatile  uint8_t *)(0x42718090UL))
#define bFM4_MFS12_I2C_IBSR_TRX                   *((volatile  uint8_t *)(0x42718090UL))
#define bFM_MFS12_I2C_IBSR_RSA                    *((volatile  uint8_t *)(0x42718094UL))
#define bFM4_MFS12_I2C_IBSR_RSA                   *((volatile  uint8_t *)(0x42718094UL))
#define bFM_MFS12_I2C_IBSR_RACK                   *((volatile  uint8_t *)(0x42718098UL))
#define bFM4_MFS12_I2C_IBSR_RACK                  *((volatile  uint8_t *)(0x42718098UL))
#define bFM_MFS12_I2C_IBSR_FBT                    *((volatile  uint8_t *)(0x4271809CUL))
#define bFM4_MFS12_I2C_IBSR_FBT                   *((volatile  uint8_t *)(0x4271809CUL))

#define bFM_MFS12_I2C_ISBA_SAEN                   *((volatile  uint8_t *)(0x4271821CUL))
#define bFM4_MFS12_I2C_ISBA_SAEN                  *((volatile  uint8_t *)(0x4271821CUL))

#define bFM_MFS12_I2C_ISMK_EN                     *((volatile  uint8_t *)(0x4271823CUL))
#define bFM4_MFS12_I2C_ISMK_EN                    *((volatile  uint8_t *)(0x4271823CUL))

#define bFM_MFS12_I2C_SMR_TIE                     *((volatile  uint8_t *)(0x42718008UL))
#define bFM4_MFS12_I2C_SMR_TIE                    *((volatile  uint8_t *)(0x42718008UL))
#define bFM_MFS12_I2C_SMR_RIE                     *((volatile  uint8_t *)(0x4271800CUL))
#define bFM4_MFS12_I2C_SMR_RIE                    *((volatile  uint8_t *)(0x4271800CUL))

#define bFM_MFS12_I2C_SSR_TBI                     *((volatile  uint8_t *)(0x427180A0UL))
#define bFM4_MFS12_I2C_SSR_TBI                    *((volatile  uint8_t *)(0x427180A0UL))
#define bFM_MFS12_I2C_SSR_TDRE                    *((volatile  uint8_t *)(0x427180A4UL))
#define bFM4_MFS12_I2C_SSR_TDRE                   *((volatile  uint8_t *)(0x427180A4UL))
#define bFM_MFS12_I2C_SSR_RDRF                    *((volatile  uint8_t *)(0x427180A8UL))
#define bFM4_MFS12_I2C_SSR_RDRF                   *((volatile  uint8_t *)(0x427180A8UL))
#define bFM_MFS12_I2C_SSR_ORE                     *((volatile  uint8_t *)(0x427180ACUL))
#define bFM4_MFS12_I2C_SSR_ORE                    *((volatile  uint8_t *)(0x427180ACUL))
#define bFM_MFS12_I2C_SSR_TBIE                    *((volatile  uint8_t *)(0x427180B0UL))
#define bFM4_MFS12_I2C_SSR_TBIE                   *((volatile  uint8_t *)(0x427180B0UL))
#define bFM_MFS12_I2C_SSR_DMA                     *((volatile  uint8_t *)(0x427180B4UL))
#define bFM4_MFS12_I2C_SSR_DMA                    *((volatile  uint8_t *)(0x427180B4UL))
#define bFM_MFS12_I2C_SSR_TSET                    *((volatile  uint8_t *)(0x427180B8UL))
#define bFM4_MFS12_I2C_SSR_TSET                   *((volatile  uint8_t *)(0x427180B8UL))
#define bFM_MFS12_I2C_SSR_REC                     *((volatile  uint8_t *)(0x427180BCUL))
#define bFM4_MFS12_I2C_SSR_REC                    *((volatile  uint8_t *)(0x427180BCUL))

#define bFM_MFS12_LIN_BGR_EXT                     *((volatile  uint8_t *)(0x427181BCUL))
#define bFM4_MFS12_LIN_BGR_EXT                    *((volatile  uint8_t *)(0x427181BCUL))

#define bFM_MFS12_LIN_ESCR_LBIE                   *((volatile  uint8_t *)(0x42718090UL))
#define bFM4_MFS12_LIN_ESCR_LBIE                  *((volatile  uint8_t *)(0x42718090UL))
#define bFM_MFS12_LIN_ESCR_ESBL                   *((volatile  uint8_t *)(0x42718098UL))
#define bFM4_MFS12_LIN_ESCR_ESBL                  *((volatile  uint8_t *)(0x42718098UL))

#define bFM_MFS12_LIN_FCR_FE1                     *((volatile  uint8_t *)(0x42718280UL))
#define bFM4_MFS12_LIN_FCR_FE1                    *((volatile  uint8_t *)(0x42718280UL))
#define bFM_MFS12_LIN_FCR_FE2                     *((volatile  uint8_t *)(0x42718284UL))
#define bFM4_MFS12_LIN_FCR_FE2                    *((volatile  uint8_t *)(0x42718284UL))
#define bFM_MFS12_LIN_FCR_FCL1                    *((volatile  uint8_t *)(0x42718288UL))
#define bFM4_MFS12_LIN_FCR_FCL1                   *((volatile  uint8_t *)(0x42718288UL))
#define bFM_MFS12_LIN_FCR_FCL2                    *((volatile  uint8_t *)(0x4271828CUL))
#define bFM4_MFS12_LIN_FCR_FCL2                   *((volatile  uint8_t *)(0x4271828CUL))
#define bFM_MFS12_LIN_FCR_FSET                    *((volatile  uint8_t *)(0x42718290UL))
#define bFM4_MFS12_LIN_FCR_FSET                   *((volatile  uint8_t *)(0x42718290UL))
#define bFM_MFS12_LIN_FCR_FLD                     *((volatile  uint8_t *)(0x42718294UL))
#define bFM4_MFS12_LIN_FCR_FLD                    *((volatile  uint8_t *)(0x42718294UL))
#define bFM_MFS12_LIN_FCR_FLST                    *((volatile  uint8_t *)(0x42718298UL))
#define bFM4_MFS12_LIN_FCR_FLST                   *((volatile  uint8_t *)(0x42718298UL))
#define bFM_MFS12_LIN_FCR_FSEL                    *((volatile  uint8_t *)(0x427182A0UL))
#define bFM4_MFS12_LIN_FCR_FSEL                   *((volatile  uint8_t *)(0x427182A0UL))
#define bFM_MFS12_LIN_FCR_FTIE                    *((volatile  uint8_t *)(0x427182A4UL))
#define bFM4_MFS12_LIN_FCR_FTIE                   *((volatile  uint8_t *)(0x427182A4UL))
#define bFM_MFS12_LIN_FCR_FDRQ                    *((volatile  uint8_t *)(0x427182A8UL))
#define bFM4_MFS12_LIN_FCR_FDRQ                   *((volatile  uint8_t *)(0x427182A8UL))
#define bFM_MFS12_LIN_FCR_FRIIE                   *((volatile  uint8_t *)(0x427182ACUL))
#define bFM4_MFS12_LIN_FCR_FRIIE                  *((volatile  uint8_t *)(0x427182ACUL))
#define bFM_MFS12_LIN_FCR_FLSTE                   *((volatile  uint8_t *)(0x427182B0UL))
#define bFM4_MFS12_LIN_FCR_FLSTE                  *((volatile  uint8_t *)(0x427182B0UL))

#define bFM_MFS12_LIN_SCR_TXE                     *((volatile  uint8_t *)(0x42718020UL))
#define bFM4_MFS12_LIN_SCR_TXE                    *((volatile  uint8_t *)(0x42718020UL))
#define bFM_MFS12_LIN_SCR_RXE                     *((volatile  uint8_t *)(0x42718024UL))
#define bFM4_MFS12_LIN_SCR_RXE                    *((volatile  uint8_t *)(0x42718024UL))
#define bFM_MFS12_LIN_SCR_TBIE                    *((volatile  uint8_t *)(0x42718028UL))
#define bFM4_MFS12_LIN_SCR_TBIE                   *((volatile  uint8_t *)(0x42718028UL))
#define bFM_MFS12_LIN_SCR_TIE                     *((volatile  uint8_t *)(0x4271802CUL))
#define bFM4_MFS12_LIN_SCR_TIE                    *((volatile  uint8_t *)(0x4271802CUL))
#define bFM_MFS12_LIN_SCR_RIE                     *((volatile  uint8_t *)(0x42718030UL))
#define bFM4_MFS12_LIN_SCR_RIE                    *((volatile  uint8_t *)(0x42718030UL))
#define bFM_MFS12_LIN_SCR_LBR                     *((volatile  uint8_t *)(0x42718034UL))
#define bFM4_MFS12_LIN_SCR_LBR                    *((volatile  uint8_t *)(0x42718034UL))
#define bFM_MFS12_LIN_SCR_MS                      *((volatile  uint8_t *)(0x42718038UL))
#define bFM4_MFS12_LIN_SCR_MS                     *((volatile  uint8_t *)(0x42718038UL))
#define bFM_MFS12_LIN_SCR_UPCL                    *((volatile  uint8_t *)(0x4271803CUL))
#define bFM4_MFS12_LIN_SCR_UPCL                   *((volatile  uint8_t *)(0x4271803CUL))

#define bFM_MFS12_LIN_SMR_SOE                     *((volatile  uint8_t *)(0x42718000UL))
#define bFM4_MFS12_LIN_SMR_SOE                    *((volatile  uint8_t *)(0x42718000UL))
#define bFM_MFS12_LIN_SMR_SBL                     *((volatile  uint8_t *)(0x4271800CUL))
#define bFM4_MFS12_LIN_SMR_SBL                    *((volatile  uint8_t *)(0x4271800CUL))
#define bFM_MFS12_LIN_SMR_WUCR                    *((volatile  uint8_t *)(0x42718010UL))
#define bFM4_MFS12_LIN_SMR_WUCR                   *((volatile  uint8_t *)(0x42718010UL))

#define bFM_MFS12_LIN_SSR_TBI                     *((volatile  uint8_t *)(0x427180A0UL))
#define bFM4_MFS12_LIN_SSR_TBI                    *((volatile  uint8_t *)(0x427180A0UL))
#define bFM_MFS12_LIN_SSR_TDRE                    *((volatile  uint8_t *)(0x427180A4UL))
#define bFM4_MFS12_LIN_SSR_TDRE                   *((volatile  uint8_t *)(0x427180A4UL))
#define bFM_MFS12_LIN_SSR_RDRF                    *((volatile  uint8_t *)(0x427180A8UL))
#define bFM4_MFS12_LIN_SSR_RDRF                   *((volatile  uint8_t *)(0x427180A8UL))
#define bFM_MFS12_LIN_SSR_ORE                     *((volatile  uint8_t *)(0x427180ACUL))
#define bFM4_MFS12_LIN_SSR_ORE                    *((volatile  uint8_t *)(0x427180ACUL))
#define bFM_MFS12_LIN_SSR_FRE                     *((volatile  uint8_t *)(0x427180B0UL))
#define bFM4_MFS12_LIN_SSR_FRE                    *((volatile  uint8_t *)(0x427180B0UL))
#define bFM_MFS12_LIN_SSR_LBD                     *((volatile  uint8_t *)(0x427180B4UL))
#define bFM4_MFS12_LIN_SSR_LBD                    *((volatile  uint8_t *)(0x427180B4UL))
#define bFM_MFS12_LIN_SSR_REC                     *((volatile  uint8_t *)(0x427180BCUL))
#define bFM4_MFS12_LIN_SSR_REC                    *((volatile  uint8_t *)(0x427180BCUL))

#define bFM_MFS12_UART_BGR_EXT                    *((volatile  uint8_t *)(0x427181BCUL))
#define bFM4_MFS12_UART_BGR_EXT                   *((volatile  uint8_t *)(0x427181BCUL))

#define bFM_MFS12_UART_ESCR_P                     *((volatile  uint8_t *)(0x4271808CUL))
#define bFM4_MFS12_UART_ESCR_P                    *((volatile  uint8_t *)(0x4271808CUL))
#define bFM_MFS12_UART_ESCR_PEN                   *((volatile  uint8_t *)(0x42718090UL))
#define bFM4_MFS12_UART_ESCR_PEN                  *((volatile  uint8_t *)(0x42718090UL))
#define bFM_MFS12_UART_ESCR_INV                   *((volatile  uint8_t *)(0x42718094UL))
#define bFM4_MFS12_UART_ESCR_INV                  *((volatile  uint8_t *)(0x42718094UL))
#define bFM_MFS12_UART_ESCR_ESBL                  *((volatile  uint8_t *)(0x42718098UL))
#define bFM4_MFS12_UART_ESCR_ESBL                 *((volatile  uint8_t *)(0x42718098UL))
#define bFM_MFS12_UART_ESCR_FLWEN                 *((volatile  uint8_t *)(0x4271809CUL))
#define bFM4_MFS12_UART_ESCR_FLWEN                *((volatile  uint8_t *)(0x4271809CUL))

#define bFM_MFS12_UART_FCR_FE1                    *((volatile  uint8_t *)(0x42718280UL))
#define bFM4_MFS12_UART_FCR_FE1                   *((volatile  uint8_t *)(0x42718280UL))
#define bFM_MFS12_UART_FCR_FE2                    *((volatile  uint8_t *)(0x42718284UL))
#define bFM4_MFS12_UART_FCR_FE2                   *((volatile  uint8_t *)(0x42718284UL))
#define bFM_MFS12_UART_FCR_FCL1                   *((volatile  uint8_t *)(0x42718288UL))
#define bFM4_MFS12_UART_FCR_FCL1                  *((volatile  uint8_t *)(0x42718288UL))
#define bFM_MFS12_UART_FCR_FCL2                   *((volatile  uint8_t *)(0x4271828CUL))
#define bFM4_MFS12_UART_FCR_FCL2                  *((volatile  uint8_t *)(0x4271828CUL))
#define bFM_MFS12_UART_FCR_FSET                   *((volatile  uint8_t *)(0x42718290UL))
#define bFM4_MFS12_UART_FCR_FSET                  *((volatile  uint8_t *)(0x42718290UL))
#define bFM_MFS12_UART_FCR_FLD                    *((volatile  uint8_t *)(0x42718294UL))
#define bFM4_MFS12_UART_FCR_FLD                   *((volatile  uint8_t *)(0x42718294UL))
#define bFM_MFS12_UART_FCR_FLST                   *((volatile  uint8_t *)(0x42718298UL))
#define bFM4_MFS12_UART_FCR_FLST                  *((volatile  uint8_t *)(0x42718298UL))
#define bFM_MFS12_UART_FCR_FSEL                   *((volatile  uint8_t *)(0x427182A0UL))
#define bFM4_MFS12_UART_FCR_FSEL                  *((volatile  uint8_t *)(0x427182A0UL))
#define bFM_MFS12_UART_FCR_FTIE                   *((volatile  uint8_t *)(0x427182A4UL))
#define bFM4_MFS12_UART_FCR_FTIE                  *((volatile  uint8_t *)(0x427182A4UL))
#define bFM_MFS12_UART_FCR_FDRQ                   *((volatile  uint8_t *)(0x427182A8UL))
#define bFM4_MFS12_UART_FCR_FDRQ                  *((volatile  uint8_t *)(0x427182A8UL))
#define bFM_MFS12_UART_FCR_FRIIE                  *((volatile  uint8_t *)(0x427182ACUL))
#define bFM4_MFS12_UART_FCR_FRIIE                 *((volatile  uint8_t *)(0x427182ACUL))
#define bFM_MFS12_UART_FCR_FLSTE                  *((volatile  uint8_t *)(0x427182B0UL))
#define bFM4_MFS12_UART_FCR_FLSTE                 *((volatile  uint8_t *)(0x427182B0UL))

#define bFM_MFS12_UART_SCR_TXE                    *((volatile  uint8_t *)(0x42718020UL))
#define bFM4_MFS12_UART_SCR_TXE                   *((volatile  uint8_t *)(0x42718020UL))
#define bFM_MFS12_UART_SCR_RXE                    *((volatile  uint8_t *)(0x42718024UL))
#define bFM4_MFS12_UART_SCR_RXE                   *((volatile  uint8_t *)(0x42718024UL))
#define bFM_MFS12_UART_SCR_TBIE                   *((volatile  uint8_t *)(0x42718028UL))
#define bFM4_MFS12_UART_SCR_TBIE                  *((volatile  uint8_t *)(0x42718028UL))
#define bFM_MFS12_UART_SCR_TIE                    *((volatile  uint8_t *)(0x4271802CUL))
#define bFM4_MFS12_UART_SCR_TIE                   *((volatile  uint8_t *)(0x4271802CUL))
#define bFM_MFS12_UART_SCR_RIE                    *((volatile  uint8_t *)(0x42718030UL))
#define bFM4_MFS12_UART_SCR_RIE                   *((volatile  uint8_t *)(0x42718030UL))
#define bFM_MFS12_UART_SCR_UPCL                   *((volatile  uint8_t *)(0x4271803CUL))
#define bFM4_MFS12_UART_SCR_UPCL                  *((volatile  uint8_t *)(0x4271803CUL))

#define bFM_MFS12_UART_SMR_SOE                    *((volatile  uint8_t *)(0x42718000UL))
#define bFM4_MFS12_UART_SMR_SOE                   *((volatile  uint8_t *)(0x42718000UL))
#define bFM_MFS12_UART_SMR_BDS                    *((volatile  uint8_t *)(0x42718008UL))
#define bFM4_MFS12_UART_SMR_BDS                   *((volatile  uint8_t *)(0x42718008UL))
#define bFM_MFS12_UART_SMR_SBL                    *((volatile  uint8_t *)(0x4271800CUL))
#define bFM4_MFS12_UART_SMR_SBL                   *((volatile  uint8_t *)(0x4271800CUL))

#define bFM_MFS12_UART_SSR_TBI                    *((volatile  uint8_t *)(0x427180A0UL))
#define bFM4_MFS12_UART_SSR_TBI                   *((volatile  uint8_t *)(0x427180A0UL))
#define bFM_MFS12_UART_SSR_TDRE                   *((volatile  uint8_t *)(0x427180A4UL))
#define bFM4_MFS12_UART_SSR_TDRE                  *((volatile  uint8_t *)(0x427180A4UL))
#define bFM_MFS12_UART_SSR_RDRF                   *((volatile  uint8_t *)(0x427180A8UL))
#define bFM4_MFS12_UART_SSR_RDRF                  *((volatile  uint8_t *)(0x427180A8UL))
#define bFM_MFS12_UART_SSR_ORE                    *((volatile  uint8_t *)(0x427180ACUL))
#define bFM4_MFS12_UART_SSR_ORE                   *((volatile  uint8_t *)(0x427180ACUL))
#define bFM_MFS12_UART_SSR_FRE                    *((volatile  uint8_t *)(0x427180B0UL))
#define bFM4_MFS12_UART_SSR_FRE                   *((volatile  uint8_t *)(0x427180B0UL))
#define bFM_MFS12_UART_SSR_PE                     *((volatile  uint8_t *)(0x427180B4UL))
#define bFM4_MFS12_UART_SSR_PE                    *((volatile  uint8_t *)(0x427180B4UL))
#define bFM_MFS12_UART_SSR_REC                    *((volatile  uint8_t *)(0x427180BCUL))
#define bFM4_MFS12_UART_SSR_REC                   *((volatile  uint8_t *)(0x427180BCUL))


/*******************************************************************************
* MFS Registers MFS13
*   Bitband Section
*******************************************************************************/
#define bFM_MFS13_CSIO_ESCR_CSFE                  *((volatile  uint8_t *)(0x4271A094UL))
#define bFM4_MFS13_CSIO_ESCR_CSFE                 *((volatile  uint8_t *)(0x4271A094UL))
#define bFM_MFS13_CSIO_ESCR_L3                    *((volatile  uint8_t *)(0x4271A098UL))
#define bFM4_MFS13_CSIO_ESCR_L3                   *((volatile  uint8_t *)(0x4271A098UL))
#define bFM_MFS13_CSIO_ESCR_SOP                   *((volatile  uint8_t *)(0x4271A09CUL))
#define bFM4_MFS13_CSIO_ESCR_SOP                  *((volatile  uint8_t *)(0x4271A09CUL))

#define bFM_MFS13_CSIO_FCR_FE1                    *((volatile  uint8_t *)(0x4271A280UL))
#define bFM4_MFS13_CSIO_FCR_FE1                   *((volatile  uint8_t *)(0x4271A280UL))
#define bFM_MFS13_CSIO_FCR_FE2                    *((volatile  uint8_t *)(0x4271A284UL))
#define bFM4_MFS13_CSIO_FCR_FE2                   *((volatile  uint8_t *)(0x4271A284UL))
#define bFM_MFS13_CSIO_FCR_FCL1                   *((volatile  uint8_t *)(0x4271A288UL))
#define bFM4_MFS13_CSIO_FCR_FCL1                  *((volatile  uint8_t *)(0x4271A288UL))
#define bFM_MFS13_CSIO_FCR_FCL2                   *((volatile  uint8_t *)(0x4271A28CUL))
#define bFM4_MFS13_CSIO_FCR_FCL2                  *((volatile  uint8_t *)(0x4271A28CUL))
#define bFM_MFS13_CSIO_FCR_FSET                   *((volatile  uint8_t *)(0x4271A290UL))
#define bFM4_MFS13_CSIO_FCR_FSET                  *((volatile  uint8_t *)(0x4271A290UL))
#define bFM_MFS13_CSIO_FCR_FLD                    *((volatile  uint8_t *)(0x4271A294UL))
#define bFM4_MFS13_CSIO_FCR_FLD                   *((volatile  uint8_t *)(0x4271A294UL))
#define bFM_MFS13_CSIO_FCR_FLST                   *((volatile  uint8_t *)(0x4271A298UL))
#define bFM4_MFS13_CSIO_FCR_FLST                  *((volatile  uint8_t *)(0x4271A298UL))
#define bFM_MFS13_CSIO_FCR_FSEL                   *((volatile  uint8_t *)(0x4271A2A0UL))
#define bFM4_MFS13_CSIO_FCR_FSEL                  *((volatile  uint8_t *)(0x4271A2A0UL))
#define bFM_MFS13_CSIO_FCR_FTIE                   *((volatile  uint8_t *)(0x4271A2A4UL))
#define bFM4_MFS13_CSIO_FCR_FTIE                  *((volatile  uint8_t *)(0x4271A2A4UL))
#define bFM_MFS13_CSIO_FCR_FDRQ                   *((volatile  uint8_t *)(0x4271A2A8UL))
#define bFM4_MFS13_CSIO_FCR_FDRQ                  *((volatile  uint8_t *)(0x4271A2A8UL))
#define bFM_MFS13_CSIO_FCR_FRIIE                  *((volatile  uint8_t *)(0x4271A2ACUL))
#define bFM4_MFS13_CSIO_FCR_FRIIE                 *((volatile  uint8_t *)(0x4271A2ACUL))
#define bFM_MFS13_CSIO_FCR_FLSTE                  *((volatile  uint8_t *)(0x4271A2B0UL))
#define bFM4_MFS13_CSIO_FCR_FLSTE                 *((volatile  uint8_t *)(0x4271A2B0UL))

#define bFM_MFS13_CSIO_SACSR_TMRE                 *((volatile  uint8_t *)(0x4271A480UL))
#define bFM4_MFS13_CSIO_SACSR_TMRE                *((volatile  uint8_t *)(0x4271A480UL))
#define bFM_MFS13_CSIO_SACSR_TSYNE                *((volatile  uint8_t *)(0x4271A498UL))
#define bFM4_MFS13_CSIO_SACSR_TSYNE               *((volatile  uint8_t *)(0x4271A498UL))
#define bFM_MFS13_CSIO_SACSR_TINTE                *((volatile  uint8_t *)(0x4271A49CUL))
#define bFM4_MFS13_CSIO_SACSR_TINTE               *((volatile  uint8_t *)(0x4271A49CUL))
#define bFM_MFS13_CSIO_SACSR_TINT                 *((volatile  uint8_t *)(0x4271A4A0UL))
#define bFM4_MFS13_CSIO_SACSR_TINT                *((volatile  uint8_t *)(0x4271A4A0UL))
#define bFM_MFS13_CSIO_SACSR_CSE                  *((volatile  uint8_t *)(0x4271A4ACUL))
#define bFM4_MFS13_CSIO_SACSR_CSE                 *((volatile  uint8_t *)(0x4271A4ACUL))
#define bFM_MFS13_CSIO_SACSR_CSEIE                *((volatile  uint8_t *)(0x4271A4B0UL))
#define bFM4_MFS13_CSIO_SACSR_CSEIE               *((volatile  uint8_t *)(0x4271A4B0UL))
#define bFM_MFS13_CSIO_SACSR_TBEEN                *((volatile  uint8_t *)(0x4271A4B4UL))
#define bFM4_MFS13_CSIO_SACSR_TBEEN               *((volatile  uint8_t *)(0x4271A4B4UL))

#define bFM_MFS13_CSIO_SCR_TXE                    *((volatile  uint8_t *)(0x4271A020UL))
#define bFM4_MFS13_CSIO_SCR_TXE                   *((volatile  uint8_t *)(0x4271A020UL))
#define bFM_MFS13_CSIO_SCR_RXE                    *((volatile  uint8_t *)(0x4271A024UL))
#define bFM4_MFS13_CSIO_SCR_RXE                   *((volatile  uint8_t *)(0x4271A024UL))
#define bFM_MFS13_CSIO_SCR_TBIE                   *((volatile  uint8_t *)(0x4271A028UL))
#define bFM4_MFS13_CSIO_SCR_TBIE                  *((volatile  uint8_t *)(0x4271A028UL))
#define bFM_MFS13_CSIO_SCR_TIE                    *((volatile  uint8_t *)(0x4271A02CUL))
#define bFM4_MFS13_CSIO_SCR_TIE                   *((volatile  uint8_t *)(0x4271A02CUL))
#define bFM_MFS13_CSIO_SCR_RIE                    *((volatile  uint8_t *)(0x4271A030UL))
#define bFM4_MFS13_CSIO_SCR_RIE                   *((volatile  uint8_t *)(0x4271A030UL))
#define bFM_MFS13_CSIO_SCR_SPI                    *((volatile  uint8_t *)(0x4271A034UL))
#define bFM4_MFS13_CSIO_SCR_SPI                   *((volatile  uint8_t *)(0x4271A034UL))
#define bFM_MFS13_CSIO_SCR_MS                     *((volatile  uint8_t *)(0x4271A038UL))
#define bFM4_MFS13_CSIO_SCR_MS                    *((volatile  uint8_t *)(0x4271A038UL))
#define bFM_MFS13_CSIO_SCR_UPCL                   *((volatile  uint8_t *)(0x4271A03CUL))
#define bFM4_MFS13_CSIO_SCR_UPCL                  *((volatile  uint8_t *)(0x4271A03CUL))

#define bFM_MFS13_CSIO_SCSCR_CSOE                 *((volatile  uint8_t *)(0x4271A600UL))
#define bFM4_MFS13_CSIO_SCSCR_CSOE                *((volatile  uint8_t *)(0x4271A600UL))
#define bFM_MFS13_CSIO_SCSCR_CSEN0                *((volatile  uint8_t *)(0x4271A604UL))
#define bFM4_MFS13_CSIO_SCSCR_CSEN0               *((volatile  uint8_t *)(0x4271A604UL))
#define bFM_MFS13_CSIO_SCSCR_CSEN1                *((volatile  uint8_t *)(0x4271A608UL))
#define bFM4_MFS13_CSIO_SCSCR_CSEN1               *((volatile  uint8_t *)(0x4271A608UL))
#define bFM_MFS13_CSIO_SCSCR_CSEN2                *((volatile  uint8_t *)(0x4271A60CUL))
#define bFM4_MFS13_CSIO_SCSCR_CSEN2               *((volatile  uint8_t *)(0x4271A60CUL))
#define bFM_MFS13_CSIO_SCSCR_CSEN3                *((volatile  uint8_t *)(0x4271A610UL))
#define bFM4_MFS13_CSIO_SCSCR_CSEN3               *((volatile  uint8_t *)(0x4271A610UL))
#define bFM_MFS13_CSIO_SCSCR_CSLVL                *((volatile  uint8_t *)(0x4271A614UL))
#define bFM4_MFS13_CSIO_SCSCR_CSLVL               *((volatile  uint8_t *)(0x4271A614UL))
#define bFM_MFS13_CSIO_SCSCR_SCAM                 *((volatile  uint8_t *)(0x4271A624UL))
#define bFM4_MFS13_CSIO_SCSCR_SCAM                *((volatile  uint8_t *)(0x4271A624UL))

#define bFM_MFS13_CSIO_SCSFR0_CS1SPI              *((volatile  uint8_t *)(0x4271A694UL))
#define bFM4_MFS13_CSIO_SCSFR0_CS1SPI             *((volatile  uint8_t *)(0x4271A694UL))
#define bFM_MFS13_CSIO_SCSFR0_CS1SCINV            *((volatile  uint8_t *)(0x4271A698UL))
#define bFM4_MFS13_CSIO_SCSFR0_CS1SCINV           *((volatile  uint8_t *)(0x4271A698UL))
#define bFM_MFS13_CSIO_SCSFR0_CS1CSLVL            *((volatile  uint8_t *)(0x4271A69CUL))
#define bFM4_MFS13_CSIO_SCSFR0_CS1CSLVL           *((volatile  uint8_t *)(0x4271A69CUL))

#define bFM_MFS13_CSIO_SCSFR1_CS2SPI              *((volatile  uint8_t *)(0x4271A6B4UL))
#define bFM4_MFS13_CSIO_SCSFR1_CS2SPI             *((volatile  uint8_t *)(0x4271A6B4UL))
#define bFM_MFS13_CSIO_SCSFR1_CS2SCINV            *((volatile  uint8_t *)(0x4271A6B8UL))
#define bFM4_MFS13_CSIO_SCSFR1_CS2SCINV           *((volatile  uint8_t *)(0x4271A6B8UL))
#define bFM_MFS13_CSIO_SCSFR1_CS2CSLVL            *((volatile  uint8_t *)(0x4271A6BCUL))
#define bFM4_MFS13_CSIO_SCSFR1_CS2CSLVL           *((volatile  uint8_t *)(0x4271A6BCUL))

#define bFM_MFS13_CSIO_SCSFR2_CS3SPI              *((volatile  uint8_t *)(0x4271A714UL))
#define bFM4_MFS13_CSIO_SCSFR2_CS3SPI             *((volatile  uint8_t *)(0x4271A714UL))
#define bFM_MFS13_CSIO_SCSFR2_CS3SCINV            *((volatile  uint8_t *)(0x4271A718UL))
#define bFM4_MFS13_CSIO_SCSFR2_CS3SCINV           *((volatile  uint8_t *)(0x4271A718UL))
#define bFM_MFS13_CSIO_SCSFR2_CS3CSLVL            *((volatile  uint8_t *)(0x4271A71CUL))
#define bFM4_MFS13_CSIO_SCSFR2_CS3CSLVL           *((volatile  uint8_t *)(0x4271A71CUL))

#define bFM_MFS13_CSIO_SMR_SOE                    *((volatile  uint8_t *)(0x4271A000UL))
#define bFM4_MFS13_CSIO_SMR_SOE                   *((volatile  uint8_t *)(0x4271A000UL))
#define bFM_MFS13_CSIO_SMR_SCKE                   *((volatile  uint8_t *)(0x4271A004UL))
#define bFM4_MFS13_CSIO_SMR_SCKE                  *((volatile  uint8_t *)(0x4271A004UL))
#define bFM_MFS13_CSIO_SMR_BDS                    *((volatile  uint8_t *)(0x4271A008UL))
#define bFM4_MFS13_CSIO_SMR_BDS                   *((volatile  uint8_t *)(0x4271A008UL))
#define bFM_MFS13_CSIO_SMR_SCINV                  *((volatile  uint8_t *)(0x4271A00CUL))
#define bFM4_MFS13_CSIO_SMR_SCINV                 *((volatile  uint8_t *)(0x4271A00CUL))

#define bFM_MFS13_CSIO_SSR_TBI                    *((volatile  uint8_t *)(0x4271A0A0UL))
#define bFM4_MFS13_CSIO_SSR_TBI                   *((volatile  uint8_t *)(0x4271A0A0UL))
#define bFM_MFS13_CSIO_SSR_TDRE                   *((volatile  uint8_t *)(0x4271A0A4UL))
#define bFM4_MFS13_CSIO_SSR_TDRE                  *((volatile  uint8_t *)(0x4271A0A4UL))
#define bFM_MFS13_CSIO_SSR_RDRF                   *((volatile  uint8_t *)(0x4271A0A8UL))
#define bFM4_MFS13_CSIO_SSR_RDRF                  *((volatile  uint8_t *)(0x4271A0A8UL))
#define bFM_MFS13_CSIO_SSR_ORE                    *((volatile  uint8_t *)(0x4271A0ACUL))
#define bFM4_MFS13_CSIO_SSR_ORE                   *((volatile  uint8_t *)(0x4271A0ACUL))
#define bFM_MFS13_CSIO_SSR_AWC                    *((volatile  uint8_t *)(0x4271A0B0UL))
#define bFM4_MFS13_CSIO_SSR_AWC                   *((volatile  uint8_t *)(0x4271A0B0UL))
#define bFM_MFS13_CSIO_SSR_REC                    *((volatile  uint8_t *)(0x4271A0BCUL))
#define bFM4_MFS13_CSIO_SSR_REC                   *((volatile  uint8_t *)(0x4271A0BCUL))

#define bFM_MFS13_I2C_EIBCR_BEC                   *((volatile  uint8_t *)(0x4271A3A0UL))
#define bFM4_MFS13_I2C_EIBCR_BEC                  *((volatile  uint8_t *)(0x4271A3A0UL))
#define bFM_MFS13_I2C_EIBCR_SOCE                  *((volatile  uint8_t *)(0x4271A3A4UL))
#define bFM4_MFS13_I2C_EIBCR_SOCE                 *((volatile  uint8_t *)(0x4271A3A4UL))
#define bFM_MFS13_I2C_EIBCR_SCLC                  *((volatile  uint8_t *)(0x4271A3A8UL))
#define bFM4_MFS13_I2C_EIBCR_SCLC                 *((volatile  uint8_t *)(0x4271A3A8UL))
#define bFM_MFS13_I2C_EIBCR_SDAC                  *((volatile  uint8_t *)(0x4271A3ACUL))
#define bFM4_MFS13_I2C_EIBCR_SDAC                 *((volatile  uint8_t *)(0x4271A3ACUL))
#define bFM_MFS13_I2C_EIBCR_SCLS                  *((volatile  uint8_t *)(0x4271A3B0UL))
#define bFM4_MFS13_I2C_EIBCR_SCLS                 *((volatile  uint8_t *)(0x4271A3B0UL))
#define bFM_MFS13_I2C_EIBCR_SDAS                  *((volatile  uint8_t *)(0x4271A3B4UL))
#define bFM4_MFS13_I2C_EIBCR_SDAS                 *((volatile  uint8_t *)(0x4271A3B4UL))

#define bFM_MFS13_I2C_FCR_FE1                     *((volatile  uint8_t *)(0x4271A280UL))
#define bFM4_MFS13_I2C_FCR_FE1                    *((volatile  uint8_t *)(0x4271A280UL))
#define bFM_MFS13_I2C_FCR_FE2                     *((volatile  uint8_t *)(0x4271A284UL))
#define bFM4_MFS13_I2C_FCR_FE2                    *((volatile  uint8_t *)(0x4271A284UL))
#define bFM_MFS13_I2C_FCR_FCL1                    *((volatile  uint8_t *)(0x4271A288UL))
#define bFM4_MFS13_I2C_FCR_FCL1                   *((volatile  uint8_t *)(0x4271A288UL))
#define bFM_MFS13_I2C_FCR_FCL2                    *((volatile  uint8_t *)(0x4271A28CUL))
#define bFM4_MFS13_I2C_FCR_FCL2                   *((volatile  uint8_t *)(0x4271A28CUL))
#define bFM_MFS13_I2C_FCR_FSET                    *((volatile  uint8_t *)(0x4271A290UL))
#define bFM4_MFS13_I2C_FCR_FSET                   *((volatile  uint8_t *)(0x4271A290UL))
#define bFM_MFS13_I2C_FCR_FLD                     *((volatile  uint8_t *)(0x4271A294UL))
#define bFM4_MFS13_I2C_FCR_FLD                    *((volatile  uint8_t *)(0x4271A294UL))
#define bFM_MFS13_I2C_FCR_FLST                    *((volatile  uint8_t *)(0x4271A298UL))
#define bFM4_MFS13_I2C_FCR_FLST                   *((volatile  uint8_t *)(0x4271A298UL))
#define bFM_MFS13_I2C_FCR_FSEL                    *((volatile  uint8_t *)(0x4271A2A0UL))
#define bFM4_MFS13_I2C_FCR_FSEL                   *((volatile  uint8_t *)(0x4271A2A0UL))
#define bFM_MFS13_I2C_FCR_FTIE                    *((volatile  uint8_t *)(0x4271A2A4UL))
#define bFM4_MFS13_I2C_FCR_FTIE                   *((volatile  uint8_t *)(0x4271A2A4UL))
#define bFM_MFS13_I2C_FCR_FDRQ                    *((volatile  uint8_t *)(0x4271A2A8UL))
#define bFM4_MFS13_I2C_FCR_FDRQ                   *((volatile  uint8_t *)(0x4271A2A8UL))
#define bFM_MFS13_I2C_FCR_FRIIE                   *((volatile  uint8_t *)(0x4271A2ACUL))
#define bFM4_MFS13_I2C_FCR_FRIIE                  *((volatile  uint8_t *)(0x4271A2ACUL))
#define bFM_MFS13_I2C_FCR_FLSTE                   *((volatile  uint8_t *)(0x4271A2B0UL))
#define bFM4_MFS13_I2C_FCR_FLSTE                  *((volatile  uint8_t *)(0x4271A2B0UL))

#define bFM_MFS13_I2C_IBCR_INT                    *((volatile  uint8_t *)(0x4271A020UL))
#define bFM4_MFS13_I2C_IBCR_INT                   *((volatile  uint8_t *)(0x4271A020UL))
#define bFM_MFS13_I2C_IBCR_BER                    *((volatile  uint8_t *)(0x4271A024UL))
#define bFM4_MFS13_I2C_IBCR_BER                   *((volatile  uint8_t *)(0x4271A024UL))
#define bFM_MFS13_I2C_IBCR_INTE                   *((volatile  uint8_t *)(0x4271A028UL))
#define bFM4_MFS13_I2C_IBCR_INTE                  *((volatile  uint8_t *)(0x4271A028UL))
#define bFM_MFS13_I2C_IBCR_CNDE                   *((volatile  uint8_t *)(0x4271A02CUL))
#define bFM4_MFS13_I2C_IBCR_CNDE                  *((volatile  uint8_t *)(0x4271A02CUL))
#define bFM_MFS13_I2C_IBCR_WSEL                   *((volatile  uint8_t *)(0x4271A030UL))
#define bFM4_MFS13_I2C_IBCR_WSEL                  *((volatile  uint8_t *)(0x4271A030UL))
#define bFM_MFS13_I2C_IBCR_ACKE                   *((volatile  uint8_t *)(0x4271A034UL))
#define bFM4_MFS13_I2C_IBCR_ACKE                  *((volatile  uint8_t *)(0x4271A034UL))
#define bFM_MFS13_I2C_IBCR_ACT_SCC                *((volatile  uint8_t *)(0x4271A038UL))
#define bFM4_MFS13_I2C_IBCR_ACT_SCC               *((volatile  uint8_t *)(0x4271A038UL))
#define bFM_MFS13_I2C_IBCR_MSS                    *((volatile  uint8_t *)(0x4271A03CUL))
#define bFM4_MFS13_I2C_IBCR_MSS                   *((volatile  uint8_t *)(0x4271A03CUL))

#define bFM_MFS13_I2C_IBSR_BB                     *((volatile  uint8_t *)(0x4271A080UL))
#define bFM4_MFS13_I2C_IBSR_BB                    *((volatile  uint8_t *)(0x4271A080UL))
#define bFM_MFS13_I2C_IBSR_SPC                    *((volatile  uint8_t *)(0x4271A084UL))
#define bFM4_MFS13_I2C_IBSR_SPC                   *((volatile  uint8_t *)(0x4271A084UL))
#define bFM_MFS13_I2C_IBSR_RSC                    *((volatile  uint8_t *)(0x4271A088UL))
#define bFM4_MFS13_I2C_IBSR_RSC                   *((volatile  uint8_t *)(0x4271A088UL))
#define bFM_MFS13_I2C_IBSR_AL                     *((volatile  uint8_t *)(0x4271A08CUL))
#define bFM4_MFS13_I2C_IBSR_AL                    *((volatile  uint8_t *)(0x4271A08CUL))
#define bFM_MFS13_I2C_IBSR_TRX                    *((volatile  uint8_t *)(0x4271A090UL))
#define bFM4_MFS13_I2C_IBSR_TRX                   *((volatile  uint8_t *)(0x4271A090UL))
#define bFM_MFS13_I2C_IBSR_RSA                    *((volatile  uint8_t *)(0x4271A094UL))
#define bFM4_MFS13_I2C_IBSR_RSA                   *((volatile  uint8_t *)(0x4271A094UL))
#define bFM_MFS13_I2C_IBSR_RACK                   *((volatile  uint8_t *)(0x4271A098UL))
#define bFM4_MFS13_I2C_IBSR_RACK                  *((volatile  uint8_t *)(0x4271A098UL))
#define bFM_MFS13_I2C_IBSR_FBT                    *((volatile  uint8_t *)(0x4271A09CUL))
#define bFM4_MFS13_I2C_IBSR_FBT                   *((volatile  uint8_t *)(0x4271A09CUL))

#define bFM_MFS13_I2C_ISBA_SAEN                   *((volatile  uint8_t *)(0x4271A21CUL))
#define bFM4_MFS13_I2C_ISBA_SAEN                  *((volatile  uint8_t *)(0x4271A21CUL))

#define bFM_MFS13_I2C_ISMK_EN                     *((volatile  uint8_t *)(0x4271A23CUL))
#define bFM4_MFS13_I2C_ISMK_EN                    *((volatile  uint8_t *)(0x4271A23CUL))

#define bFM_MFS13_I2C_SMR_TIE                     *((volatile  uint8_t *)(0x4271A008UL))
#define bFM4_MFS13_I2C_SMR_TIE                    *((volatile  uint8_t *)(0x4271A008UL))
#define bFM_MFS13_I2C_SMR_RIE                     *((volatile  uint8_t *)(0x4271A00CUL))
#define bFM4_MFS13_I2C_SMR_RIE                    *((volatile  uint8_t *)(0x4271A00CUL))

#define bFM_MFS13_I2C_SSR_TBI                     *((volatile  uint8_t *)(0x4271A0A0UL))
#define bFM4_MFS13_I2C_SSR_TBI                    *((volatile  uint8_t *)(0x4271A0A0UL))
#define bFM_MFS13_I2C_SSR_TDRE                    *((volatile  uint8_t *)(0x4271A0A4UL))
#define bFM4_MFS13_I2C_SSR_TDRE                   *((volatile  uint8_t *)(0x4271A0A4UL))
#define bFM_MFS13_I2C_SSR_RDRF                    *((volatile  uint8_t *)(0x4271A0A8UL))
#define bFM4_MFS13_I2C_SSR_RDRF                   *((volatile  uint8_t *)(0x4271A0A8UL))
#define bFM_MFS13_I2C_SSR_ORE                     *((volatile  uint8_t *)(0x4271A0ACUL))
#define bFM4_MFS13_I2C_SSR_ORE                    *((volatile  uint8_t *)(0x4271A0ACUL))
#define bFM_MFS13_I2C_SSR_TBIE                    *((volatile  uint8_t *)(0x4271A0B0UL))
#define bFM4_MFS13_I2C_SSR_TBIE                   *((volatile  uint8_t *)(0x4271A0B0UL))
#define bFM_MFS13_I2C_SSR_DMA                     *((volatile  uint8_t *)(0x4271A0B4UL))
#define bFM4_MFS13_I2C_SSR_DMA                    *((volatile  uint8_t *)(0x4271A0B4UL))
#define bFM_MFS13_I2C_SSR_TSET                    *((volatile  uint8_t *)(0x4271A0B8UL))
#define bFM4_MFS13_I2C_SSR_TSET                   *((volatile  uint8_t *)(0x4271A0B8UL))
#define bFM_MFS13_I2C_SSR_REC                     *((volatile  uint8_t *)(0x4271A0BCUL))
#define bFM4_MFS13_I2C_SSR_REC                    *((volatile  uint8_t *)(0x4271A0BCUL))

#define bFM_MFS13_LIN_BGR_EXT                     *((volatile  uint8_t *)(0x4271A1BCUL))
#define bFM4_MFS13_LIN_BGR_EXT                    *((volatile  uint8_t *)(0x4271A1BCUL))

#define bFM_MFS13_LIN_ESCR_LBIE                   *((volatile  uint8_t *)(0x4271A090UL))
#define bFM4_MFS13_LIN_ESCR_LBIE                  *((volatile  uint8_t *)(0x4271A090UL))
#define bFM_MFS13_LIN_ESCR_ESBL                   *((volatile  uint8_t *)(0x4271A098UL))
#define bFM4_MFS13_LIN_ESCR_ESBL                  *((volatile  uint8_t *)(0x4271A098UL))

#define bFM_MFS13_LIN_FCR_FE1                     *((volatile  uint8_t *)(0x4271A280UL))
#define bFM4_MFS13_LIN_FCR_FE1                    *((volatile  uint8_t *)(0x4271A280UL))
#define bFM_MFS13_LIN_FCR_FE2                     *((volatile  uint8_t *)(0x4271A284UL))
#define bFM4_MFS13_LIN_FCR_FE2                    *((volatile  uint8_t *)(0x4271A284UL))
#define bFM_MFS13_LIN_FCR_FCL1                    *((volatile  uint8_t *)(0x4271A288UL))
#define bFM4_MFS13_LIN_FCR_FCL1                   *((volatile  uint8_t *)(0x4271A288UL))
#define bFM_MFS13_LIN_FCR_FCL2                    *((volatile  uint8_t *)(0x4271A28CUL))
#define bFM4_MFS13_LIN_FCR_FCL2                   *((volatile  uint8_t *)(0x4271A28CUL))
#define bFM_MFS13_LIN_FCR_FSET                    *((volatile  uint8_t *)(0x4271A290UL))
#define bFM4_MFS13_LIN_FCR_FSET                   *((volatile  uint8_t *)(0x4271A290UL))
#define bFM_MFS13_LIN_FCR_FLD                     *((volatile  uint8_t *)(0x4271A294UL))
#define bFM4_MFS13_LIN_FCR_FLD                    *((volatile  uint8_t *)(0x4271A294UL))
#define bFM_MFS13_LIN_FCR_FLST                    *((volatile  uint8_t *)(0x4271A298UL))
#define bFM4_MFS13_LIN_FCR_FLST                   *((volatile  uint8_t *)(0x4271A298UL))
#define bFM_MFS13_LIN_FCR_FSEL                    *((volatile  uint8_t *)(0x4271A2A0UL))
#define bFM4_MFS13_LIN_FCR_FSEL                   *((volatile  uint8_t *)(0x4271A2A0UL))
#define bFM_MFS13_LIN_FCR_FTIE                    *((volatile  uint8_t *)(0x4271A2A4UL))
#define bFM4_MFS13_LIN_FCR_FTIE                   *((volatile  uint8_t *)(0x4271A2A4UL))
#define bFM_MFS13_LIN_FCR_FDRQ                    *((volatile  uint8_t *)(0x4271A2A8UL))
#define bFM4_MFS13_LIN_FCR_FDRQ                   *((volatile  uint8_t *)(0x4271A2A8UL))
#define bFM_MFS13_LIN_FCR_FRIIE                   *((volatile  uint8_t *)(0x4271A2ACUL))
#define bFM4_MFS13_LIN_FCR_FRIIE                  *((volatile  uint8_t *)(0x4271A2ACUL))
#define bFM_MFS13_LIN_FCR_FLSTE                   *((volatile  uint8_t *)(0x4271A2B0UL))
#define bFM4_MFS13_LIN_FCR_FLSTE                  *((volatile  uint8_t *)(0x4271A2B0UL))

#define bFM_MFS13_LIN_SCR_TXE                     *((volatile  uint8_t *)(0x4271A020UL))
#define bFM4_MFS13_LIN_SCR_TXE                    *((volatile  uint8_t *)(0x4271A020UL))
#define bFM_MFS13_LIN_SCR_RXE                     *((volatile  uint8_t *)(0x4271A024UL))
#define bFM4_MFS13_LIN_SCR_RXE                    *((volatile  uint8_t *)(0x4271A024UL))
#define bFM_MFS13_LIN_SCR_TBIE                    *((volatile  uint8_t *)(0x4271A028UL))
#define bFM4_MFS13_LIN_SCR_TBIE                   *((volatile  uint8_t *)(0x4271A028UL))
#define bFM_MFS13_LIN_SCR_TIE                     *((volatile  uint8_t *)(0x4271A02CUL))
#define bFM4_MFS13_LIN_SCR_TIE                    *((volatile  uint8_t *)(0x4271A02CUL))
#define bFM_MFS13_LIN_SCR_RIE                     *((volatile  uint8_t *)(0x4271A030UL))
#define bFM4_MFS13_LIN_SCR_RIE                    *((volatile  uint8_t *)(0x4271A030UL))
#define bFM_MFS13_LIN_SCR_LBR                     *((volatile  uint8_t *)(0x4271A034UL))
#define bFM4_MFS13_LIN_SCR_LBR                    *((volatile  uint8_t *)(0x4271A034UL))
#define bFM_MFS13_LIN_SCR_MS                      *((volatile  uint8_t *)(0x4271A038UL))
#define bFM4_MFS13_LIN_SCR_MS                     *((volatile  uint8_t *)(0x4271A038UL))
#define bFM_MFS13_LIN_SCR_UPCL                    *((volatile  uint8_t *)(0x4271A03CUL))
#define bFM4_MFS13_LIN_SCR_UPCL                   *((volatile  uint8_t *)(0x4271A03CUL))

#define bFM_MFS13_LIN_SMR_SOE                     *((volatile  uint8_t *)(0x4271A000UL))
#define bFM4_MFS13_LIN_SMR_SOE                    *((volatile  uint8_t *)(0x4271A000UL))
#define bFM_MFS13_LIN_SMR_SBL                     *((volatile  uint8_t *)(0x4271A00CUL))
#define bFM4_MFS13_LIN_SMR_SBL                    *((volatile  uint8_t *)(0x4271A00CUL))
#define bFM_MFS13_LIN_SMR_WUCR                    *((volatile  uint8_t *)(0x4271A010UL))
#define bFM4_MFS13_LIN_SMR_WUCR                   *((volatile  uint8_t *)(0x4271A010UL))

#define bFM_MFS13_LIN_SSR_TBI                     *((volatile  uint8_t *)(0x4271A0A0UL))
#define bFM4_MFS13_LIN_SSR_TBI                    *((volatile  uint8_t *)(0x4271A0A0UL))
#define bFM_MFS13_LIN_SSR_TDRE                    *((volatile  uint8_t *)(0x4271A0A4UL))
#define bFM4_MFS13_LIN_SSR_TDRE                   *((volatile  uint8_t *)(0x4271A0A4UL))
#define bFM_MFS13_LIN_SSR_RDRF                    *((volatile  uint8_t *)(0x4271A0A8UL))
#define bFM4_MFS13_LIN_SSR_RDRF                   *((volatile  uint8_t *)(0x4271A0A8UL))
#define bFM_MFS13_LIN_SSR_ORE                     *((volatile  uint8_t *)(0x4271A0ACUL))
#define bFM4_MFS13_LIN_SSR_ORE                    *((volatile  uint8_t *)(0x4271A0ACUL))
#define bFM_MFS13_LIN_SSR_FRE                     *((volatile  uint8_t *)(0x4271A0B0UL))
#define bFM4_MFS13_LIN_SSR_FRE                    *((volatile  uint8_t *)(0x4271A0B0UL))
#define bFM_MFS13_LIN_SSR_LBD                     *((volatile  uint8_t *)(0x4271A0B4UL))
#define bFM4_MFS13_LIN_SSR_LBD                    *((volatile  uint8_t *)(0x4271A0B4UL))
#define bFM_MFS13_LIN_SSR_REC                     *((volatile  uint8_t *)(0x4271A0BCUL))
#define bFM4_MFS13_LIN_SSR_REC                    *((volatile  uint8_t *)(0x4271A0BCUL))

#define bFM_MFS13_UART_BGR_EXT                    *((volatile  uint8_t *)(0x4271A1BCUL))
#define bFM4_MFS13_UART_BGR_EXT                   *((volatile  uint8_t *)(0x4271A1BCUL))

#define bFM_MFS13_UART_ESCR_P                     *((volatile  uint8_t *)(0x4271A08CUL))
#define bFM4_MFS13_UART_ESCR_P                    *((volatile  uint8_t *)(0x4271A08CUL))
#define bFM_MFS13_UART_ESCR_PEN                   *((volatile  uint8_t *)(0x4271A090UL))
#define bFM4_MFS13_UART_ESCR_PEN                  *((volatile  uint8_t *)(0x4271A090UL))
#define bFM_MFS13_UART_ESCR_INV                   *((volatile  uint8_t *)(0x4271A094UL))
#define bFM4_MFS13_UART_ESCR_INV                  *((volatile  uint8_t *)(0x4271A094UL))
#define bFM_MFS13_UART_ESCR_ESBL                  *((volatile  uint8_t *)(0x4271A098UL))
#define bFM4_MFS13_UART_ESCR_ESBL                 *((volatile  uint8_t *)(0x4271A098UL))
#define bFM_MFS13_UART_ESCR_FLWEN                 *((volatile  uint8_t *)(0x4271A09CUL))
#define bFM4_MFS13_UART_ESCR_FLWEN                *((volatile  uint8_t *)(0x4271A09CUL))

#define bFM_MFS13_UART_FCR_FE1                    *((volatile  uint8_t *)(0x4271A280UL))
#define bFM4_MFS13_UART_FCR_FE1                   *((volatile  uint8_t *)(0x4271A280UL))
#define bFM_MFS13_UART_FCR_FE2                    *((volatile  uint8_t *)(0x4271A284UL))
#define bFM4_MFS13_UART_FCR_FE2                   *((volatile  uint8_t *)(0x4271A284UL))
#define bFM_MFS13_UART_FCR_FCL1                   *((volatile  uint8_t *)(0x4271A288UL))
#define bFM4_MFS13_UART_FCR_FCL1                  *((volatile  uint8_t *)(0x4271A288UL))
#define bFM_MFS13_UART_FCR_FCL2                   *((volatile  uint8_t *)(0x4271A28CUL))
#define bFM4_MFS13_UART_FCR_FCL2                  *((volatile  uint8_t *)(0x4271A28CUL))
#define bFM_MFS13_UART_FCR_FSET                   *((volatile  uint8_t *)(0x4271A290UL))
#define bFM4_MFS13_UART_FCR_FSET                  *((volatile  uint8_t *)(0x4271A290UL))
#define bFM_MFS13_UART_FCR_FLD                    *((volatile  uint8_t *)(0x4271A294UL))
#define bFM4_MFS13_UART_FCR_FLD                   *((volatile  uint8_t *)(0x4271A294UL))
#define bFM_MFS13_UART_FCR_FLST                   *((volatile  uint8_t *)(0x4271A298UL))
#define bFM4_MFS13_UART_FCR_FLST                  *((volatile  uint8_t *)(0x4271A298UL))
#define bFM_MFS13_UART_FCR_FSEL                   *((volatile  uint8_t *)(0x4271A2A0UL))
#define bFM4_MFS13_UART_FCR_FSEL                  *((volatile  uint8_t *)(0x4271A2A0UL))
#define bFM_MFS13_UART_FCR_FTIE                   *((volatile  uint8_t *)(0x4271A2A4UL))
#define bFM4_MFS13_UART_FCR_FTIE                  *((volatile  uint8_t *)(0x4271A2A4UL))
#define bFM_MFS13_UART_FCR_FDRQ                   *((volatile  uint8_t *)(0x4271A2A8UL))
#define bFM4_MFS13_UART_FCR_FDRQ                  *((volatile  uint8_t *)(0x4271A2A8UL))
#define bFM_MFS13_UART_FCR_FRIIE                  *((volatile  uint8_t *)(0x4271A2ACUL))
#define bFM4_MFS13_UART_FCR_FRIIE                 *((volatile  uint8_t *)(0x4271A2ACUL))
#define bFM_MFS13_UART_FCR_FLSTE                  *((volatile  uint8_t *)(0x4271A2B0UL))
#define bFM4_MFS13_UART_FCR_FLSTE                 *((volatile  uint8_t *)(0x4271A2B0UL))

#define bFM_MFS13_UART_SCR_TXE                    *((volatile  uint8_t *)(0x4271A020UL))
#define bFM4_MFS13_UART_SCR_TXE                   *((volatile  uint8_t *)(0x4271A020UL))
#define bFM_MFS13_UART_SCR_RXE                    *((volatile  uint8_t *)(0x4271A024UL))
#define bFM4_MFS13_UART_SCR_RXE                   *((volatile  uint8_t *)(0x4271A024UL))
#define bFM_MFS13_UART_SCR_TBIE                   *((volatile  uint8_t *)(0x4271A028UL))
#define bFM4_MFS13_UART_SCR_TBIE                  *((volatile  uint8_t *)(0x4271A028UL))
#define bFM_MFS13_UART_SCR_TIE                    *((volatile  uint8_t *)(0x4271A02CUL))
#define bFM4_MFS13_UART_SCR_TIE                   *((volatile  uint8_t *)(0x4271A02CUL))
#define bFM_MFS13_UART_SCR_RIE                    *((volatile  uint8_t *)(0x4271A030UL))
#define bFM4_MFS13_UART_SCR_RIE                   *((volatile  uint8_t *)(0x4271A030UL))
#define bFM_MFS13_UART_SCR_UPCL                   *((volatile  uint8_t *)(0x4271A03CUL))
#define bFM4_MFS13_UART_SCR_UPCL                  *((volatile  uint8_t *)(0x4271A03CUL))

#define bFM_MFS13_UART_SMR_SOE                    *((volatile  uint8_t *)(0x4271A000UL))
#define bFM4_MFS13_UART_SMR_SOE                   *((volatile  uint8_t *)(0x4271A000UL))
#define bFM_MFS13_UART_SMR_BDS                    *((volatile  uint8_t *)(0x4271A008UL))
#define bFM4_MFS13_UART_SMR_BDS                   *((volatile  uint8_t *)(0x4271A008UL))
#define bFM_MFS13_UART_SMR_SBL                    *((volatile  uint8_t *)(0x4271A00CUL))
#define bFM4_MFS13_UART_SMR_SBL                   *((volatile  uint8_t *)(0x4271A00CUL))

#define bFM_MFS13_UART_SSR_TBI                    *((volatile  uint8_t *)(0x4271A0A0UL))
#define bFM4_MFS13_UART_SSR_TBI                   *((volatile  uint8_t *)(0x4271A0A0UL))
#define bFM_MFS13_UART_SSR_TDRE                   *((volatile  uint8_t *)(0x4271A0A4UL))
#define bFM4_MFS13_UART_SSR_TDRE                  *((volatile  uint8_t *)(0x4271A0A4UL))
#define bFM_MFS13_UART_SSR_RDRF                   *((volatile  uint8_t *)(0x4271A0A8UL))
#define bFM4_MFS13_UART_SSR_RDRF                  *((volatile  uint8_t *)(0x4271A0A8UL))
#define bFM_MFS13_UART_SSR_ORE                    *((volatile  uint8_t *)(0x4271A0ACUL))
#define bFM4_MFS13_UART_SSR_ORE                   *((volatile  uint8_t *)(0x4271A0ACUL))
#define bFM_MFS13_UART_SSR_FRE                    *((volatile  uint8_t *)(0x4271A0B0UL))
#define bFM4_MFS13_UART_SSR_FRE                   *((volatile  uint8_t *)(0x4271A0B0UL))
#define bFM_MFS13_UART_SSR_PE                     *((volatile  uint8_t *)(0x4271A0B4UL))
#define bFM4_MFS13_UART_SSR_PE                    *((volatile  uint8_t *)(0x4271A0B4UL))
#define bFM_MFS13_UART_SSR_REC                    *((volatile  uint8_t *)(0x4271A0BCUL))
#define bFM4_MFS13_UART_SSR_REC                   *((volatile  uint8_t *)(0x4271A0BCUL))


/*******************************************************************************
* MFS Registers MFS14
*   Bitband Section
*******************************************************************************/
#define bFM_MFS14_CSIO_ESCR_CSFE                  *((volatile  uint8_t *)(0x4271C094UL))
#define bFM4_MFS14_CSIO_ESCR_CSFE                 *((volatile  uint8_t *)(0x4271C094UL))
#define bFM_MFS14_CSIO_ESCR_L3                    *((volatile  uint8_t *)(0x4271C098UL))
#define bFM4_MFS14_CSIO_ESCR_L3                   *((volatile  uint8_t *)(0x4271C098UL))
#define bFM_MFS14_CSIO_ESCR_SOP                   *((volatile  uint8_t *)(0x4271C09CUL))
#define bFM4_MFS14_CSIO_ESCR_SOP                  *((volatile  uint8_t *)(0x4271C09CUL))

#define bFM_MFS14_CSIO_FCR_FE1                    *((volatile  uint8_t *)(0x4271C280UL))
#define bFM4_MFS14_CSIO_FCR_FE1                   *((volatile  uint8_t *)(0x4271C280UL))
#define bFM_MFS14_CSIO_FCR_FE2                    *((volatile  uint8_t *)(0x4271C284UL))
#define bFM4_MFS14_CSIO_FCR_FE2                   *((volatile  uint8_t *)(0x4271C284UL))
#define bFM_MFS14_CSIO_FCR_FCL1                   *((volatile  uint8_t *)(0x4271C288UL))
#define bFM4_MFS14_CSIO_FCR_FCL1                  *((volatile  uint8_t *)(0x4271C288UL))
#define bFM_MFS14_CSIO_FCR_FCL2                   *((volatile  uint8_t *)(0x4271C28CUL))
#define bFM4_MFS14_CSIO_FCR_FCL2                  *((volatile  uint8_t *)(0x4271C28CUL))
#define bFM_MFS14_CSIO_FCR_FSET                   *((volatile  uint8_t *)(0x4271C290UL))
#define bFM4_MFS14_CSIO_FCR_FSET                  *((volatile  uint8_t *)(0x4271C290UL))
#define bFM_MFS14_CSIO_FCR_FLD                    *((volatile  uint8_t *)(0x4271C294UL))
#define bFM4_MFS14_CSIO_FCR_FLD                   *((volatile  uint8_t *)(0x4271C294UL))
#define bFM_MFS14_CSIO_FCR_FLST                   *((volatile  uint8_t *)(0x4271C298UL))
#define bFM4_MFS14_CSIO_FCR_FLST                  *((volatile  uint8_t *)(0x4271C298UL))
#define bFM_MFS14_CSIO_FCR_FSEL                   *((volatile  uint8_t *)(0x4271C2A0UL))
#define bFM4_MFS14_CSIO_FCR_FSEL                  *((volatile  uint8_t *)(0x4271C2A0UL))
#define bFM_MFS14_CSIO_FCR_FTIE                   *((volatile  uint8_t *)(0x4271C2A4UL))
#define bFM4_MFS14_CSIO_FCR_FTIE                  *((volatile  uint8_t *)(0x4271C2A4UL))
#define bFM_MFS14_CSIO_FCR_FDRQ                   *((volatile  uint8_t *)(0x4271C2A8UL))
#define bFM4_MFS14_CSIO_FCR_FDRQ                  *((volatile  uint8_t *)(0x4271C2A8UL))
#define bFM_MFS14_CSIO_FCR_FRIIE                  *((volatile  uint8_t *)(0x4271C2ACUL))
#define bFM4_MFS14_CSIO_FCR_FRIIE                 *((volatile  uint8_t *)(0x4271C2ACUL))
#define bFM_MFS14_CSIO_FCR_FLSTE                  *((volatile  uint8_t *)(0x4271C2B0UL))
#define bFM4_MFS14_CSIO_FCR_FLSTE                 *((volatile  uint8_t *)(0x4271C2B0UL))

#define bFM_MFS14_CSIO_SACSR_TMRE                 *((volatile  uint8_t *)(0x4271C480UL))
#define bFM4_MFS14_CSIO_SACSR_TMRE                *((volatile  uint8_t *)(0x4271C480UL))
#define bFM_MFS14_CSIO_SACSR_TSYNE                *((volatile  uint8_t *)(0x4271C498UL))
#define bFM4_MFS14_CSIO_SACSR_TSYNE               *((volatile  uint8_t *)(0x4271C498UL))
#define bFM_MFS14_CSIO_SACSR_TINTE                *((volatile  uint8_t *)(0x4271C49CUL))
#define bFM4_MFS14_CSIO_SACSR_TINTE               *((volatile  uint8_t *)(0x4271C49CUL))
#define bFM_MFS14_CSIO_SACSR_TINT                 *((volatile  uint8_t *)(0x4271C4A0UL))
#define bFM4_MFS14_CSIO_SACSR_TINT                *((volatile  uint8_t *)(0x4271C4A0UL))
#define bFM_MFS14_CSIO_SACSR_CSE                  *((volatile  uint8_t *)(0x4271C4ACUL))
#define bFM4_MFS14_CSIO_SACSR_CSE                 *((volatile  uint8_t *)(0x4271C4ACUL))
#define bFM_MFS14_CSIO_SACSR_CSEIE                *((volatile  uint8_t *)(0x4271C4B0UL))
#define bFM4_MFS14_CSIO_SACSR_CSEIE               *((volatile  uint8_t *)(0x4271C4B0UL))
#define bFM_MFS14_CSIO_SACSR_TBEEN                *((volatile  uint8_t *)(0x4271C4B4UL))
#define bFM4_MFS14_CSIO_SACSR_TBEEN               *((volatile  uint8_t *)(0x4271C4B4UL))

#define bFM_MFS14_CSIO_SCR_TXE                    *((volatile  uint8_t *)(0x4271C020UL))
#define bFM4_MFS14_CSIO_SCR_TXE                   *((volatile  uint8_t *)(0x4271C020UL))
#define bFM_MFS14_CSIO_SCR_RXE                    *((volatile  uint8_t *)(0x4271C024UL))
#define bFM4_MFS14_CSIO_SCR_RXE                   *((volatile  uint8_t *)(0x4271C024UL))
#define bFM_MFS14_CSIO_SCR_TBIE                   *((volatile  uint8_t *)(0x4271C028UL))
#define bFM4_MFS14_CSIO_SCR_TBIE                  *((volatile  uint8_t *)(0x4271C028UL))
#define bFM_MFS14_CSIO_SCR_TIE                    *((volatile  uint8_t *)(0x4271C02CUL))
#define bFM4_MFS14_CSIO_SCR_TIE                   *((volatile  uint8_t *)(0x4271C02CUL))
#define bFM_MFS14_CSIO_SCR_RIE                    *((volatile  uint8_t *)(0x4271C030UL))
#define bFM4_MFS14_CSIO_SCR_RIE                   *((volatile  uint8_t *)(0x4271C030UL))
#define bFM_MFS14_CSIO_SCR_SPI                    *((volatile  uint8_t *)(0x4271C034UL))
#define bFM4_MFS14_CSIO_SCR_SPI                   *((volatile  uint8_t *)(0x4271C034UL))
#define bFM_MFS14_CSIO_SCR_MS                     *((volatile  uint8_t *)(0x4271C038UL))
#define bFM4_MFS14_CSIO_SCR_MS                    *((volatile  uint8_t *)(0x4271C038UL))
#define bFM_MFS14_CSIO_SCR_UPCL                   *((volatile  uint8_t *)(0x4271C03CUL))
#define bFM4_MFS14_CSIO_SCR_UPCL                  *((volatile  uint8_t *)(0x4271C03CUL))

#define bFM_MFS14_CSIO_SCSCR_CSOE                 *((volatile  uint8_t *)(0x4271C600UL))
#define bFM4_MFS14_CSIO_SCSCR_CSOE                *((volatile  uint8_t *)(0x4271C600UL))
#define bFM_MFS14_CSIO_SCSCR_CSEN0                *((volatile  uint8_t *)(0x4271C604UL))
#define bFM4_MFS14_CSIO_SCSCR_CSEN0               *((volatile  uint8_t *)(0x4271C604UL))
#define bFM_MFS14_CSIO_SCSCR_CSEN1                *((volatile  uint8_t *)(0x4271C608UL))
#define bFM4_MFS14_CSIO_SCSCR_CSEN1               *((volatile  uint8_t *)(0x4271C608UL))
#define bFM_MFS14_CSIO_SCSCR_CSEN2                *((volatile  uint8_t *)(0x4271C60CUL))
#define bFM4_MFS14_CSIO_SCSCR_CSEN2               *((volatile  uint8_t *)(0x4271C60CUL))
#define bFM_MFS14_CSIO_SCSCR_CSEN3                *((volatile  uint8_t *)(0x4271C610UL))
#define bFM4_MFS14_CSIO_SCSCR_CSEN3               *((volatile  uint8_t *)(0x4271C610UL))
#define bFM_MFS14_CSIO_SCSCR_CSLVL                *((volatile  uint8_t *)(0x4271C614UL))
#define bFM4_MFS14_CSIO_SCSCR_CSLVL               *((volatile  uint8_t *)(0x4271C614UL))
#define bFM_MFS14_CSIO_SCSCR_SCAM                 *((volatile  uint8_t *)(0x4271C624UL))
#define bFM4_MFS14_CSIO_SCSCR_SCAM                *((volatile  uint8_t *)(0x4271C624UL))

#define bFM_MFS14_CSIO_SCSFR0_CS1SPI              *((volatile  uint8_t *)(0x4271C694UL))
#define bFM4_MFS14_CSIO_SCSFR0_CS1SPI             *((volatile  uint8_t *)(0x4271C694UL))
#define bFM_MFS14_CSIO_SCSFR0_CS1SCINV            *((volatile  uint8_t *)(0x4271C698UL))
#define bFM4_MFS14_CSIO_SCSFR0_CS1SCINV           *((volatile  uint8_t *)(0x4271C698UL))
#define bFM_MFS14_CSIO_SCSFR0_CS1CSLVL            *((volatile  uint8_t *)(0x4271C69CUL))
#define bFM4_MFS14_CSIO_SCSFR0_CS1CSLVL           *((volatile  uint8_t *)(0x4271C69CUL))

#define bFM_MFS14_CSIO_SCSFR1_CS2SPI              *((volatile  uint8_t *)(0x4271C6B4UL))
#define bFM4_MFS14_CSIO_SCSFR1_CS2SPI             *((volatile  uint8_t *)(0x4271C6B4UL))
#define bFM_MFS14_CSIO_SCSFR1_CS2SCINV            *((volatile  uint8_t *)(0x4271C6B8UL))
#define bFM4_MFS14_CSIO_SCSFR1_CS2SCINV           *((volatile  uint8_t *)(0x4271C6B8UL))
#define bFM_MFS14_CSIO_SCSFR1_CS2CSLVL            *((volatile  uint8_t *)(0x4271C6BCUL))
#define bFM4_MFS14_CSIO_SCSFR1_CS2CSLVL           *((volatile  uint8_t *)(0x4271C6BCUL))

#define bFM_MFS14_CSIO_SCSFR2_CS3SPI              *((volatile  uint8_t *)(0x4271C714UL))
#define bFM4_MFS14_CSIO_SCSFR2_CS3SPI             *((volatile  uint8_t *)(0x4271C714UL))
#define bFM_MFS14_CSIO_SCSFR2_CS3SCINV            *((volatile  uint8_t *)(0x4271C718UL))
#define bFM4_MFS14_CSIO_SCSFR2_CS3SCINV           *((volatile  uint8_t *)(0x4271C718UL))
#define bFM_MFS14_CSIO_SCSFR2_CS3CSLVL            *((volatile  uint8_t *)(0x4271C71CUL))
#define bFM4_MFS14_CSIO_SCSFR2_CS3CSLVL           *((volatile  uint8_t *)(0x4271C71CUL))

#define bFM_MFS14_CSIO_SMR_SOE                    *((volatile  uint8_t *)(0x4271C000UL))
#define bFM4_MFS14_CSIO_SMR_SOE                   *((volatile  uint8_t *)(0x4271C000UL))
#define bFM_MFS14_CSIO_SMR_SCKE                   *((volatile  uint8_t *)(0x4271C004UL))
#define bFM4_MFS14_CSIO_SMR_SCKE                  *((volatile  uint8_t *)(0x4271C004UL))
#define bFM_MFS14_CSIO_SMR_BDS                    *((volatile  uint8_t *)(0x4271C008UL))
#define bFM4_MFS14_CSIO_SMR_BDS                   *((volatile  uint8_t *)(0x4271C008UL))
#define bFM_MFS14_CSIO_SMR_SCINV                  *((volatile  uint8_t *)(0x4271C00CUL))
#define bFM4_MFS14_CSIO_SMR_SCINV                 *((volatile  uint8_t *)(0x4271C00CUL))

#define bFM_MFS14_CSIO_SSR_TBI                    *((volatile  uint8_t *)(0x4271C0A0UL))
#define bFM4_MFS14_CSIO_SSR_TBI                   *((volatile  uint8_t *)(0x4271C0A0UL))
#define bFM_MFS14_CSIO_SSR_TDRE                   *((volatile  uint8_t *)(0x4271C0A4UL))
#define bFM4_MFS14_CSIO_SSR_TDRE                  *((volatile  uint8_t *)(0x4271C0A4UL))
#define bFM_MFS14_CSIO_SSR_RDRF                   *((volatile  uint8_t *)(0x4271C0A8UL))
#define bFM4_MFS14_CSIO_SSR_RDRF                  *((volatile  uint8_t *)(0x4271C0A8UL))
#define bFM_MFS14_CSIO_SSR_ORE                    *((volatile  uint8_t *)(0x4271C0ACUL))
#define bFM4_MFS14_CSIO_SSR_ORE                   *((volatile  uint8_t *)(0x4271C0ACUL))
#define bFM_MFS14_CSIO_SSR_AWC                    *((volatile  uint8_t *)(0x4271C0B0UL))
#define bFM4_MFS14_CSIO_SSR_AWC                   *((volatile  uint8_t *)(0x4271C0B0UL))
#define bFM_MFS14_CSIO_SSR_REC                    *((volatile  uint8_t *)(0x4271C0BCUL))
#define bFM4_MFS14_CSIO_SSR_REC                   *((volatile  uint8_t *)(0x4271C0BCUL))

#define bFM_MFS14_I2C_EIBCR_BEC                   *((volatile  uint8_t *)(0x4271C3A0UL))
#define bFM4_MFS14_I2C_EIBCR_BEC                  *((volatile  uint8_t *)(0x4271C3A0UL))
#define bFM_MFS14_I2C_EIBCR_SOCE                  *((volatile  uint8_t *)(0x4271C3A4UL))
#define bFM4_MFS14_I2C_EIBCR_SOCE                 *((volatile  uint8_t *)(0x4271C3A4UL))
#define bFM_MFS14_I2C_EIBCR_SCLC                  *((volatile  uint8_t *)(0x4271C3A8UL))
#define bFM4_MFS14_I2C_EIBCR_SCLC                 *((volatile  uint8_t *)(0x4271C3A8UL))
#define bFM_MFS14_I2C_EIBCR_SDAC                  *((volatile  uint8_t *)(0x4271C3ACUL))
#define bFM4_MFS14_I2C_EIBCR_SDAC                 *((volatile  uint8_t *)(0x4271C3ACUL))
#define bFM_MFS14_I2C_EIBCR_SCLS                  *((volatile  uint8_t *)(0x4271C3B0UL))
#define bFM4_MFS14_I2C_EIBCR_SCLS                 *((volatile  uint8_t *)(0x4271C3B0UL))
#define bFM_MFS14_I2C_EIBCR_SDAS                  *((volatile  uint8_t *)(0x4271C3B4UL))
#define bFM4_MFS14_I2C_EIBCR_SDAS                 *((volatile  uint8_t *)(0x4271C3B4UL))

#define bFM_MFS14_I2C_FCR_FE1                     *((volatile  uint8_t *)(0x4271C280UL))
#define bFM4_MFS14_I2C_FCR_FE1                    *((volatile  uint8_t *)(0x4271C280UL))
#define bFM_MFS14_I2C_FCR_FE2                     *((volatile  uint8_t *)(0x4271C284UL))
#define bFM4_MFS14_I2C_FCR_FE2                    *((volatile  uint8_t *)(0x4271C284UL))
#define bFM_MFS14_I2C_FCR_FCL1                    *((volatile  uint8_t *)(0x4271C288UL))
#define bFM4_MFS14_I2C_FCR_FCL1                   *((volatile  uint8_t *)(0x4271C288UL))
#define bFM_MFS14_I2C_FCR_FCL2                    *((volatile  uint8_t *)(0x4271C28CUL))
#define bFM4_MFS14_I2C_FCR_FCL2                   *((volatile  uint8_t *)(0x4271C28CUL))
#define bFM_MFS14_I2C_FCR_FSET                    *((volatile  uint8_t *)(0x4271C290UL))
#define bFM4_MFS14_I2C_FCR_FSET                   *((volatile  uint8_t *)(0x4271C290UL))
#define bFM_MFS14_I2C_FCR_FLD                     *((volatile  uint8_t *)(0x4271C294UL))
#define bFM4_MFS14_I2C_FCR_FLD                    *((volatile  uint8_t *)(0x4271C294UL))
#define bFM_MFS14_I2C_FCR_FLST                    *((volatile  uint8_t *)(0x4271C298UL))
#define bFM4_MFS14_I2C_FCR_FLST                   *((volatile  uint8_t *)(0x4271C298UL))
#define bFM_MFS14_I2C_FCR_FSEL                    *((volatile  uint8_t *)(0x4271C2A0UL))
#define bFM4_MFS14_I2C_FCR_FSEL                   *((volatile  uint8_t *)(0x4271C2A0UL))
#define bFM_MFS14_I2C_FCR_FTIE                    *((volatile  uint8_t *)(0x4271C2A4UL))
#define bFM4_MFS14_I2C_FCR_FTIE                   *((volatile  uint8_t *)(0x4271C2A4UL))
#define bFM_MFS14_I2C_FCR_FDRQ                    *((volatile  uint8_t *)(0x4271C2A8UL))
#define bFM4_MFS14_I2C_FCR_FDRQ                   *((volatile  uint8_t *)(0x4271C2A8UL))
#define bFM_MFS14_I2C_FCR_FRIIE                   *((volatile  uint8_t *)(0x4271C2ACUL))
#define bFM4_MFS14_I2C_FCR_FRIIE                  *((volatile  uint8_t *)(0x4271C2ACUL))
#define bFM_MFS14_I2C_FCR_FLSTE                   *((volatile  uint8_t *)(0x4271C2B0UL))
#define bFM4_MFS14_I2C_FCR_FLSTE                  *((volatile  uint8_t *)(0x4271C2B0UL))

#define bFM_MFS14_I2C_IBCR_INT                    *((volatile  uint8_t *)(0x4271C020UL))
#define bFM4_MFS14_I2C_IBCR_INT                   *((volatile  uint8_t *)(0x4271C020UL))
#define bFM_MFS14_I2C_IBCR_BER                    *((volatile  uint8_t *)(0x4271C024UL))
#define bFM4_MFS14_I2C_IBCR_BER                   *((volatile  uint8_t *)(0x4271C024UL))
#define bFM_MFS14_I2C_IBCR_INTE                   *((volatile  uint8_t *)(0x4271C028UL))
#define bFM4_MFS14_I2C_IBCR_INTE                  *((volatile  uint8_t *)(0x4271C028UL))
#define bFM_MFS14_I2C_IBCR_CNDE                   *((volatile  uint8_t *)(0x4271C02CUL))
#define bFM4_MFS14_I2C_IBCR_CNDE                  *((volatile  uint8_t *)(0x4271C02CUL))
#define bFM_MFS14_I2C_IBCR_WSEL                   *((volatile  uint8_t *)(0x4271C030UL))
#define bFM4_MFS14_I2C_IBCR_WSEL                  *((volatile  uint8_t *)(0x4271C030UL))
#define bFM_MFS14_I2C_IBCR_ACKE                   *((volatile  uint8_t *)(0x4271C034UL))
#define bFM4_MFS14_I2C_IBCR_ACKE                  *((volatile  uint8_t *)(0x4271C034UL))
#define bFM_MFS14_I2C_IBCR_ACT_SCC                *((volatile  uint8_t *)(0x4271C038UL))
#define bFM4_MFS14_I2C_IBCR_ACT_SCC               *((volatile  uint8_t *)(0x4271C038UL))
#define bFM_MFS14_I2C_IBCR_MSS                    *((volatile  uint8_t *)(0x4271C03CUL))
#define bFM4_MFS14_I2C_IBCR_MSS                   *((volatile  uint8_t *)(0x4271C03CUL))

#define bFM_MFS14_I2C_IBSR_BB                     *((volatile  uint8_t *)(0x4271C080UL))
#define bFM4_MFS14_I2C_IBSR_BB                    *((volatile  uint8_t *)(0x4271C080UL))
#define bFM_MFS14_I2C_IBSR_SPC                    *((volatile  uint8_t *)(0x4271C084UL))
#define bFM4_MFS14_I2C_IBSR_SPC                   *((volatile  uint8_t *)(0x4271C084UL))
#define bFM_MFS14_I2C_IBSR_RSC                    *((volatile  uint8_t *)(0x4271C088UL))
#define bFM4_MFS14_I2C_IBSR_RSC                   *((volatile  uint8_t *)(0x4271C088UL))
#define bFM_MFS14_I2C_IBSR_AL                     *((volatile  uint8_t *)(0x4271C08CUL))
#define bFM4_MFS14_I2C_IBSR_AL                    *((volatile  uint8_t *)(0x4271C08CUL))
#define bFM_MFS14_I2C_IBSR_TRX                    *((volatile  uint8_t *)(0x4271C090UL))
#define bFM4_MFS14_I2C_IBSR_TRX                   *((volatile  uint8_t *)(0x4271C090UL))
#define bFM_MFS14_I2C_IBSR_RSA                    *((volatile  uint8_t *)(0x4271C094UL))
#define bFM4_MFS14_I2C_IBSR_RSA                   *((volatile  uint8_t *)(0x4271C094UL))
#define bFM_MFS14_I2C_IBSR_RACK                   *((volatile  uint8_t *)(0x4271C098UL))
#define bFM4_MFS14_I2C_IBSR_RACK                  *((volatile  uint8_t *)(0x4271C098UL))
#define bFM_MFS14_I2C_IBSR_FBT                    *((volatile  uint8_t *)(0x4271C09CUL))
#define bFM4_MFS14_I2C_IBSR_FBT                   *((volatile  uint8_t *)(0x4271C09CUL))

#define bFM_MFS14_I2C_ISBA_SAEN                   *((volatile  uint8_t *)(0x4271C21CUL))
#define bFM4_MFS14_I2C_ISBA_SAEN                  *((volatile  uint8_t *)(0x4271C21CUL))

#define bFM_MFS14_I2C_ISMK_EN                     *((volatile  uint8_t *)(0x4271C23CUL))
#define bFM4_MFS14_I2C_ISMK_EN                    *((volatile  uint8_t *)(0x4271C23CUL))

#define bFM_MFS14_I2C_SMR_TIE                     *((volatile  uint8_t *)(0x4271C008UL))
#define bFM4_MFS14_I2C_SMR_TIE                    *((volatile  uint8_t *)(0x4271C008UL))
#define bFM_MFS14_I2C_SMR_RIE                     *((volatile  uint8_t *)(0x4271C00CUL))
#define bFM4_MFS14_I2C_SMR_RIE                    *((volatile  uint8_t *)(0x4271C00CUL))

#define bFM_MFS14_I2C_SSR_TBI                     *((volatile  uint8_t *)(0x4271C0A0UL))
#define bFM4_MFS14_I2C_SSR_TBI                    *((volatile  uint8_t *)(0x4271C0A0UL))
#define bFM_MFS14_I2C_SSR_TDRE                    *((volatile  uint8_t *)(0x4271C0A4UL))
#define bFM4_MFS14_I2C_SSR_TDRE                   *((volatile  uint8_t *)(0x4271C0A4UL))
#define bFM_MFS14_I2C_SSR_RDRF                    *((volatile  uint8_t *)(0x4271C0A8UL))
#define bFM4_MFS14_I2C_SSR_RDRF                   *((volatile  uint8_t *)(0x4271C0A8UL))
#define bFM_MFS14_I2C_SSR_ORE                     *((volatile  uint8_t *)(0x4271C0ACUL))
#define bFM4_MFS14_I2C_SSR_ORE                    *((volatile  uint8_t *)(0x4271C0ACUL))
#define bFM_MFS14_I2C_SSR_TBIE                    *((volatile  uint8_t *)(0x4271C0B0UL))
#define bFM4_MFS14_I2C_SSR_TBIE                   *((volatile  uint8_t *)(0x4271C0B0UL))
#define bFM_MFS14_I2C_SSR_DMA                     *((volatile  uint8_t *)(0x4271C0B4UL))
#define bFM4_MFS14_I2C_SSR_DMA                    *((volatile  uint8_t *)(0x4271C0B4UL))
#define bFM_MFS14_I2C_SSR_TSET                    *((volatile  uint8_t *)(0x4271C0B8UL))
#define bFM4_MFS14_I2C_SSR_TSET                   *((volatile  uint8_t *)(0x4271C0B8UL))
#define bFM_MFS14_I2C_SSR_REC                     *((volatile  uint8_t *)(0x4271C0BCUL))
#define bFM4_MFS14_I2C_SSR_REC                    *((volatile  uint8_t *)(0x4271C0BCUL))

#define bFM_MFS14_LIN_BGR_EXT                     *((volatile  uint8_t *)(0x4271C1BCUL))
#define bFM4_MFS14_LIN_BGR_EXT                    *((volatile  uint8_t *)(0x4271C1BCUL))

#define bFM_MFS14_LIN_ESCR_LBIE                   *((volatile  uint8_t *)(0x4271C090UL))
#define bFM4_MFS14_LIN_ESCR_LBIE                  *((volatile  uint8_t *)(0x4271C090UL))
#define bFM_MFS14_LIN_ESCR_ESBL                   *((volatile  uint8_t *)(0x4271C098UL))
#define bFM4_MFS14_LIN_ESCR_ESBL                  *((volatile  uint8_t *)(0x4271C098UL))

#define bFM_MFS14_LIN_FCR_FE1                     *((volatile  uint8_t *)(0x4271C280UL))
#define bFM4_MFS14_LIN_FCR_FE1                    *((volatile  uint8_t *)(0x4271C280UL))
#define bFM_MFS14_LIN_FCR_FE2                     *((volatile  uint8_t *)(0x4271C284UL))
#define bFM4_MFS14_LIN_FCR_FE2                    *((volatile  uint8_t *)(0x4271C284UL))
#define bFM_MFS14_LIN_FCR_FCL1                    *((volatile  uint8_t *)(0x4271C288UL))
#define bFM4_MFS14_LIN_FCR_FCL1                   *((volatile  uint8_t *)(0x4271C288UL))
#define bFM_MFS14_LIN_FCR_FCL2                    *((volatile  uint8_t *)(0x4271C28CUL))
#define bFM4_MFS14_LIN_FCR_FCL2                   *((volatile  uint8_t *)(0x4271C28CUL))
#define bFM_MFS14_LIN_FCR_FSET                    *((volatile  uint8_t *)(0x4271C290UL))
#define bFM4_MFS14_LIN_FCR_FSET                   *((volatile  uint8_t *)(0x4271C290UL))
#define bFM_MFS14_LIN_FCR_FLD                     *((volatile  uint8_t *)(0x4271C294UL))
#define bFM4_MFS14_LIN_FCR_FLD                    *((volatile  uint8_t *)(0x4271C294UL))
#define bFM_MFS14_LIN_FCR_FLST                    *((volatile  uint8_t *)(0x4271C298UL))
#define bFM4_MFS14_LIN_FCR_FLST                   *((volatile  uint8_t *)(0x4271C298UL))
#define bFM_MFS14_LIN_FCR_FSEL                    *((volatile  uint8_t *)(0x4271C2A0UL))
#define bFM4_MFS14_LIN_FCR_FSEL                   *((volatile  uint8_t *)(0x4271C2A0UL))
#define bFM_MFS14_LIN_FCR_FTIE                    *((volatile  uint8_t *)(0x4271C2A4UL))
#define bFM4_MFS14_LIN_FCR_FTIE                   *((volatile  uint8_t *)(0x4271C2A4UL))
#define bFM_MFS14_LIN_FCR_FDRQ                    *((volatile  uint8_t *)(0x4271C2A8UL))
#define bFM4_MFS14_LIN_FCR_FDRQ                   *((volatile  uint8_t *)(0x4271C2A8UL))
#define bFM_MFS14_LIN_FCR_FRIIE                   *((volatile  uint8_t *)(0x4271C2ACUL))
#define bFM4_MFS14_LIN_FCR_FRIIE                  *((volatile  uint8_t *)(0x4271C2ACUL))
#define bFM_MFS14_LIN_FCR_FLSTE                   *((volatile  uint8_t *)(0x4271C2B0UL))
#define bFM4_MFS14_LIN_FCR_FLSTE                  *((volatile  uint8_t *)(0x4271C2B0UL))

#define bFM_MFS14_LIN_SCR_TXE                     *((volatile  uint8_t *)(0x4271C020UL))
#define bFM4_MFS14_LIN_SCR_TXE                    *((volatile  uint8_t *)(0x4271C020UL))
#define bFM_MFS14_LIN_SCR_RXE                     *((volatile  uint8_t *)(0x4271C024UL))
#define bFM4_MFS14_LIN_SCR_RXE                    *((volatile  uint8_t *)(0x4271C024UL))
#define bFM_MFS14_LIN_SCR_TBIE                    *((volatile  uint8_t *)(0x4271C028UL))
#define bFM4_MFS14_LIN_SCR_TBIE                   *((volatile  uint8_t *)(0x4271C028UL))
#define bFM_MFS14_LIN_SCR_TIE                     *((volatile  uint8_t *)(0x4271C02CUL))
#define bFM4_MFS14_LIN_SCR_TIE                    *((volatile  uint8_t *)(0x4271C02CUL))
#define bFM_MFS14_LIN_SCR_RIE                     *((volatile  uint8_t *)(0x4271C030UL))
#define bFM4_MFS14_LIN_SCR_RIE                    *((volatile  uint8_t *)(0x4271C030UL))
#define bFM_MFS14_LIN_SCR_LBR                     *((volatile  uint8_t *)(0x4271C034UL))
#define bFM4_MFS14_LIN_SCR_LBR                    *((volatile  uint8_t *)(0x4271C034UL))
#define bFM_MFS14_LIN_SCR_MS                      *((volatile  uint8_t *)(0x4271C038UL))
#define bFM4_MFS14_LIN_SCR_MS                     *((volatile  uint8_t *)(0x4271C038UL))
#define bFM_MFS14_LIN_SCR_UPCL                    *((volatile  uint8_t *)(0x4271C03CUL))
#define bFM4_MFS14_LIN_SCR_UPCL                   *((volatile  uint8_t *)(0x4271C03CUL))

#define bFM_MFS14_LIN_SMR_SOE                     *((volatile  uint8_t *)(0x4271C000UL))
#define bFM4_MFS14_LIN_SMR_SOE                    *((volatile  uint8_t *)(0x4271C000UL))
#define bFM_MFS14_LIN_SMR_SBL                     *((volatile  uint8_t *)(0x4271C00CUL))
#define bFM4_MFS14_LIN_SMR_SBL                    *((volatile  uint8_t *)(0x4271C00CUL))
#define bFM_MFS14_LIN_SMR_WUCR                    *((volatile  uint8_t *)(0x4271C010UL))
#define bFM4_MFS14_LIN_SMR_WUCR                   *((volatile  uint8_t *)(0x4271C010UL))

#define bFM_MFS14_LIN_SSR_TBI                     *((volatile  uint8_t *)(0x4271C0A0UL))
#define bFM4_MFS14_LIN_SSR_TBI                    *((volatile  uint8_t *)(0x4271C0A0UL))
#define bFM_MFS14_LIN_SSR_TDRE                    *((volatile  uint8_t *)(0x4271C0A4UL))
#define bFM4_MFS14_LIN_SSR_TDRE                   *((volatile  uint8_t *)(0x4271C0A4UL))
#define bFM_MFS14_LIN_SSR_RDRF                    *((volatile  uint8_t *)(0x4271C0A8UL))
#define bFM4_MFS14_LIN_SSR_RDRF                   *((volatile  uint8_t *)(0x4271C0A8UL))
#define bFM_MFS14_LIN_SSR_ORE                     *((volatile  uint8_t *)(0x4271C0ACUL))
#define bFM4_MFS14_LIN_SSR_ORE                    *((volatile  uint8_t *)(0x4271C0ACUL))
#define bFM_MFS14_LIN_SSR_FRE                     *((volatile  uint8_t *)(0x4271C0B0UL))
#define bFM4_MFS14_LIN_SSR_FRE                    *((volatile  uint8_t *)(0x4271C0B0UL))
#define bFM_MFS14_LIN_SSR_LBD                     *((volatile  uint8_t *)(0x4271C0B4UL))
#define bFM4_MFS14_LIN_SSR_LBD                    *((volatile  uint8_t *)(0x4271C0B4UL))
#define bFM_MFS14_LIN_SSR_REC                     *((volatile  uint8_t *)(0x4271C0BCUL))
#define bFM4_MFS14_LIN_SSR_REC                    *((volatile  uint8_t *)(0x4271C0BCUL))

#define bFM_MFS14_UART_BGR_EXT                    *((volatile  uint8_t *)(0x4271C1BCUL))
#define bFM4_MFS14_UART_BGR_EXT                   *((volatile  uint8_t *)(0x4271C1BCUL))

#define bFM_MFS14_UART_ESCR_P                     *((volatile  uint8_t *)(0x4271C08CUL))
#define bFM4_MFS14_UART_ESCR_P                    *((volatile  uint8_t *)(0x4271C08CUL))
#define bFM_MFS14_UART_ESCR_PEN                   *((volatile  uint8_t *)(0x4271C090UL))
#define bFM4_MFS14_UART_ESCR_PEN                  *((volatile  uint8_t *)(0x4271C090UL))
#define bFM_MFS14_UART_ESCR_INV                   *((volatile  uint8_t *)(0x4271C094UL))
#define bFM4_MFS14_UART_ESCR_INV                  *((volatile  uint8_t *)(0x4271C094UL))
#define bFM_MFS14_UART_ESCR_ESBL                  *((volatile  uint8_t *)(0x4271C098UL))
#define bFM4_MFS14_UART_ESCR_ESBL                 *((volatile  uint8_t *)(0x4271C098UL))
#define bFM_MFS14_UART_ESCR_FLWEN                 *((volatile  uint8_t *)(0x4271C09CUL))
#define bFM4_MFS14_UART_ESCR_FLWEN                *((volatile  uint8_t *)(0x4271C09CUL))

#define bFM_MFS14_UART_FCR_FE1                    *((volatile  uint8_t *)(0x4271C280UL))
#define bFM4_MFS14_UART_FCR_FE1                   *((volatile  uint8_t *)(0x4271C280UL))
#define bFM_MFS14_UART_FCR_FE2                    *((volatile  uint8_t *)(0x4271C284UL))
#define bFM4_MFS14_UART_FCR_FE2                   *((volatile  uint8_t *)(0x4271C284UL))
#define bFM_MFS14_UART_FCR_FCL1                   *((volatile  uint8_t *)(0x4271C288UL))
#define bFM4_MFS14_UART_FCR_FCL1                  *((volatile  uint8_t *)(0x4271C288UL))
#define bFM_MFS14_UART_FCR_FCL2                   *((volatile  uint8_t *)(0x4271C28CUL))
#define bFM4_MFS14_UART_FCR_FCL2                  *((volatile  uint8_t *)(0x4271C28CUL))
#define bFM_MFS14_UART_FCR_FSET                   *((volatile  uint8_t *)(0x4271C290UL))
#define bFM4_MFS14_UART_FCR_FSET                  *((volatile  uint8_t *)(0x4271C290UL))
#define bFM_MFS14_UART_FCR_FLD                    *((volatile  uint8_t *)(0x4271C294UL))
#define bFM4_MFS14_UART_FCR_FLD                   *((volatile  uint8_t *)(0x4271C294UL))
#define bFM_MFS14_UART_FCR_FLST                   *((volatile  uint8_t *)(0x4271C298UL))
#define bFM4_MFS14_UART_FCR_FLST                  *((volatile  uint8_t *)(0x4271C298UL))
#define bFM_MFS14_UART_FCR_FSEL                   *((volatile  uint8_t *)(0x4271C2A0UL))
#define bFM4_MFS14_UART_FCR_FSEL                  *((volatile  uint8_t *)(0x4271C2A0UL))
#define bFM_MFS14_UART_FCR_FTIE                   *((volatile  uint8_t *)(0x4271C2A4UL))
#define bFM4_MFS14_UART_FCR_FTIE                  *((volatile  uint8_t *)(0x4271C2A4UL))
#define bFM_MFS14_UART_FCR_FDRQ                   *((volatile  uint8_t *)(0x4271C2A8UL))
#define bFM4_MFS14_UART_FCR_FDRQ                  *((volatile  uint8_t *)(0x4271C2A8UL))
#define bFM_MFS14_UART_FCR_FRIIE                  *((volatile  uint8_t *)(0x4271C2ACUL))
#define bFM4_MFS14_UART_FCR_FRIIE                 *((volatile  uint8_t *)(0x4271C2ACUL))
#define bFM_MFS14_UART_FCR_FLSTE                  *((volatile  uint8_t *)(0x4271C2B0UL))
#define bFM4_MFS14_UART_FCR_FLSTE                 *((volatile  uint8_t *)(0x4271C2B0UL))

#define bFM_MFS14_UART_SCR_TXE                    *((volatile  uint8_t *)(0x4271C020UL))
#define bFM4_MFS14_UART_SCR_TXE                   *((volatile  uint8_t *)(0x4271C020UL))
#define bFM_MFS14_UART_SCR_RXE                    *((volatile  uint8_t *)(0x4271C024UL))
#define bFM4_MFS14_UART_SCR_RXE                   *((volatile  uint8_t *)(0x4271C024UL))
#define bFM_MFS14_UART_SCR_TBIE                   *((volatile  uint8_t *)(0x4271C028UL))
#define bFM4_MFS14_UART_SCR_TBIE                  *((volatile  uint8_t *)(0x4271C028UL))
#define bFM_MFS14_UART_SCR_TIE                    *((volatile  uint8_t *)(0x4271C02CUL))
#define bFM4_MFS14_UART_SCR_TIE                   *((volatile  uint8_t *)(0x4271C02CUL))
#define bFM_MFS14_UART_SCR_RIE                    *((volatile  uint8_t *)(0x4271C030UL))
#define bFM4_MFS14_UART_SCR_RIE                   *((volatile  uint8_t *)(0x4271C030UL))
#define bFM_MFS14_UART_SCR_UPCL                   *((volatile  uint8_t *)(0x4271C03CUL))
#define bFM4_MFS14_UART_SCR_UPCL                  *((volatile  uint8_t *)(0x4271C03CUL))

#define bFM_MFS14_UART_SMR_SOE                    *((volatile  uint8_t *)(0x4271C000UL))
#define bFM4_MFS14_UART_SMR_SOE                   *((volatile  uint8_t *)(0x4271C000UL))
#define bFM_MFS14_UART_SMR_BDS                    *((volatile  uint8_t *)(0x4271C008UL))
#define bFM4_MFS14_UART_SMR_BDS                   *((volatile  uint8_t *)(0x4271C008UL))
#define bFM_MFS14_UART_SMR_SBL                    *((volatile  uint8_t *)(0x4271C00CUL))
#define bFM4_MFS14_UART_SMR_SBL                   *((volatile  uint8_t *)(0x4271C00CUL))

#define bFM_MFS14_UART_SSR_TBI                    *((volatile  uint8_t *)(0x4271C0A0UL))
#define bFM4_MFS14_UART_SSR_TBI                   *((volatile  uint8_t *)(0x4271C0A0UL))
#define bFM_MFS14_UART_SSR_TDRE                   *((volatile  uint8_t *)(0x4271C0A4UL))
#define bFM4_MFS14_UART_SSR_TDRE                  *((volatile  uint8_t *)(0x4271C0A4UL))
#define bFM_MFS14_UART_SSR_RDRF                   *((volatile  uint8_t *)(0x4271C0A8UL))
#define bFM4_MFS14_UART_SSR_RDRF                  *((volatile  uint8_t *)(0x4271C0A8UL))
#define bFM_MFS14_UART_SSR_ORE                    *((volatile  uint8_t *)(0x4271C0ACUL))
#define bFM4_MFS14_UART_SSR_ORE                   *((volatile  uint8_t *)(0x4271C0ACUL))
#define bFM_MFS14_UART_SSR_FRE                    *((volatile  uint8_t *)(0x4271C0B0UL))
#define bFM4_MFS14_UART_SSR_FRE                   *((volatile  uint8_t *)(0x4271C0B0UL))
#define bFM_MFS14_UART_SSR_PE                     *((volatile  uint8_t *)(0x4271C0B4UL))
#define bFM4_MFS14_UART_SSR_PE                    *((volatile  uint8_t *)(0x4271C0B4UL))
#define bFM_MFS14_UART_SSR_REC                    *((volatile  uint8_t *)(0x4271C0BCUL))
#define bFM4_MFS14_UART_SSR_REC                   *((volatile  uint8_t *)(0x4271C0BCUL))


/*******************************************************************************
* MFS Registers MFS15
*   Bitband Section
*******************************************************************************/
#define bFM_MFS15_CSIO_ESCR_CSFE                  *((volatile  uint8_t *)(0x4271E094UL))
#define bFM4_MFS15_CSIO_ESCR_CSFE                 *((volatile  uint8_t *)(0x4271E094UL))
#define bFM_MFS15_CSIO_ESCR_L3                    *((volatile  uint8_t *)(0x4271E098UL))
#define bFM4_MFS15_CSIO_ESCR_L3                   *((volatile  uint8_t *)(0x4271E098UL))
#define bFM_MFS15_CSIO_ESCR_SOP                   *((volatile  uint8_t *)(0x4271E09CUL))
#define bFM4_MFS15_CSIO_ESCR_SOP                  *((volatile  uint8_t *)(0x4271E09CUL))

#define bFM_MFS15_CSIO_FCR_FE1                    *((volatile  uint8_t *)(0x4271E280UL))
#define bFM4_MFS15_CSIO_FCR_FE1                   *((volatile  uint8_t *)(0x4271E280UL))
#define bFM_MFS15_CSIO_FCR_FE2                    *((volatile  uint8_t *)(0x4271E284UL))
#define bFM4_MFS15_CSIO_FCR_FE2                   *((volatile  uint8_t *)(0x4271E284UL))
#define bFM_MFS15_CSIO_FCR_FCL1                   *((volatile  uint8_t *)(0x4271E288UL))
#define bFM4_MFS15_CSIO_FCR_FCL1                  *((volatile  uint8_t *)(0x4271E288UL))
#define bFM_MFS15_CSIO_FCR_FCL2                   *((volatile  uint8_t *)(0x4271E28CUL))
#define bFM4_MFS15_CSIO_FCR_FCL2                  *((volatile  uint8_t *)(0x4271E28CUL))
#define bFM_MFS15_CSIO_FCR_FSET                   *((volatile  uint8_t *)(0x4271E290UL))
#define bFM4_MFS15_CSIO_FCR_FSET                  *((volatile  uint8_t *)(0x4271E290UL))
#define bFM_MFS15_CSIO_FCR_FLD                    *((volatile  uint8_t *)(0x4271E294UL))
#define bFM4_MFS15_CSIO_FCR_FLD                   *((volatile  uint8_t *)(0x4271E294UL))
#define bFM_MFS15_CSIO_FCR_FLST                   *((volatile  uint8_t *)(0x4271E298UL))
#define bFM4_MFS15_CSIO_FCR_FLST                  *((volatile  uint8_t *)(0x4271E298UL))
#define bFM_MFS15_CSIO_FCR_FSEL                   *((volatile  uint8_t *)(0x4271E2A0UL))
#define bFM4_MFS15_CSIO_FCR_FSEL                  *((volatile  uint8_t *)(0x4271E2A0UL))
#define bFM_MFS15_CSIO_FCR_FTIE                   *((volatile  uint8_t *)(0x4271E2A4UL))
#define bFM4_MFS15_CSIO_FCR_FTIE                  *((volatile  uint8_t *)(0x4271E2A4UL))
#define bFM_MFS15_CSIO_FCR_FDRQ                   *((volatile  uint8_t *)(0x4271E2A8UL))
#define bFM4_MFS15_CSIO_FCR_FDRQ                  *((volatile  uint8_t *)(0x4271E2A8UL))
#define bFM_MFS15_CSIO_FCR_FRIIE                  *((volatile  uint8_t *)(0x4271E2ACUL))
#define bFM4_MFS15_CSIO_FCR_FRIIE                 *((volatile  uint8_t *)(0x4271E2ACUL))
#define bFM_MFS15_CSIO_FCR_FLSTE                  *((volatile  uint8_t *)(0x4271E2B0UL))
#define bFM4_MFS15_CSIO_FCR_FLSTE                 *((volatile  uint8_t *)(0x4271E2B0UL))

#define bFM_MFS15_CSIO_SACSR_TMRE                 *((volatile  uint8_t *)(0x4271E480UL))
#define bFM4_MFS15_CSIO_SACSR_TMRE                *((volatile  uint8_t *)(0x4271E480UL))
#define bFM_MFS15_CSIO_SACSR_TSYNE                *((volatile  uint8_t *)(0x4271E498UL))
#define bFM4_MFS15_CSIO_SACSR_TSYNE               *((volatile  uint8_t *)(0x4271E498UL))
#define bFM_MFS15_CSIO_SACSR_TINTE                *((volatile  uint8_t *)(0x4271E49CUL))
#define bFM4_MFS15_CSIO_SACSR_TINTE               *((volatile  uint8_t *)(0x4271E49CUL))
#define bFM_MFS15_CSIO_SACSR_TINT                 *((volatile  uint8_t *)(0x4271E4A0UL))
#define bFM4_MFS15_CSIO_SACSR_TINT                *((volatile  uint8_t *)(0x4271E4A0UL))
#define bFM_MFS15_CSIO_SACSR_CSE                  *((volatile  uint8_t *)(0x4271E4ACUL))
#define bFM4_MFS15_CSIO_SACSR_CSE                 *((volatile  uint8_t *)(0x4271E4ACUL))
#define bFM_MFS15_CSIO_SACSR_CSEIE                *((volatile  uint8_t *)(0x4271E4B0UL))
#define bFM4_MFS15_CSIO_SACSR_CSEIE               *((volatile  uint8_t *)(0x4271E4B0UL))
#define bFM_MFS15_CSIO_SACSR_TBEEN                *((volatile  uint8_t *)(0x4271E4B4UL))
#define bFM4_MFS15_CSIO_SACSR_TBEEN               *((volatile  uint8_t *)(0x4271E4B4UL))

#define bFM_MFS15_CSIO_SCR_TXE                    *((volatile  uint8_t *)(0x4271E020UL))
#define bFM4_MFS15_CSIO_SCR_TXE                   *((volatile  uint8_t *)(0x4271E020UL))
#define bFM_MFS15_CSIO_SCR_RXE                    *((volatile  uint8_t *)(0x4271E024UL))
#define bFM4_MFS15_CSIO_SCR_RXE                   *((volatile  uint8_t *)(0x4271E024UL))
#define bFM_MFS15_CSIO_SCR_TBIE                   *((volatile  uint8_t *)(0x4271E028UL))
#define bFM4_MFS15_CSIO_SCR_TBIE                  *((volatile  uint8_t *)(0x4271E028UL))
#define bFM_MFS15_CSIO_SCR_TIE                    *((volatile  uint8_t *)(0x4271E02CUL))
#define bFM4_MFS15_CSIO_SCR_TIE                   *((volatile  uint8_t *)(0x4271E02CUL))
#define bFM_MFS15_CSIO_SCR_RIE                    *((volatile  uint8_t *)(0x4271E030UL))
#define bFM4_MFS15_CSIO_SCR_RIE                   *((volatile  uint8_t *)(0x4271E030UL))
#define bFM_MFS15_CSIO_SCR_SPI                    *((volatile  uint8_t *)(0x4271E034UL))
#define bFM4_MFS15_CSIO_SCR_SPI                   *((volatile  uint8_t *)(0x4271E034UL))
#define bFM_MFS15_CSIO_SCR_MS                     *((volatile  uint8_t *)(0x4271E038UL))
#define bFM4_MFS15_CSIO_SCR_MS                    *((volatile  uint8_t *)(0x4271E038UL))
#define bFM_MFS15_CSIO_SCR_UPCL                   *((volatile  uint8_t *)(0x4271E03CUL))
#define bFM4_MFS15_CSIO_SCR_UPCL                  *((volatile  uint8_t *)(0x4271E03CUL))

#define bFM_MFS15_CSIO_SCSCR_CSOE                 *((volatile  uint8_t *)(0x4271E600UL))
#define bFM4_MFS15_CSIO_SCSCR_CSOE                *((volatile  uint8_t *)(0x4271E600UL))
#define bFM_MFS15_CSIO_SCSCR_CSEN0                *((volatile  uint8_t *)(0x4271E604UL))
#define bFM4_MFS15_CSIO_SCSCR_CSEN0               *((volatile  uint8_t *)(0x4271E604UL))
#define bFM_MFS15_CSIO_SCSCR_CSEN1                *((volatile  uint8_t *)(0x4271E608UL))
#define bFM4_MFS15_CSIO_SCSCR_CSEN1               *((volatile  uint8_t *)(0x4271E608UL))
#define bFM_MFS15_CSIO_SCSCR_CSEN2                *((volatile  uint8_t *)(0x4271E60CUL))
#define bFM4_MFS15_CSIO_SCSCR_CSEN2               *((volatile  uint8_t *)(0x4271E60CUL))
#define bFM_MFS15_CSIO_SCSCR_CSEN3                *((volatile  uint8_t *)(0x4271E610UL))
#define bFM4_MFS15_CSIO_SCSCR_CSEN3               *((volatile  uint8_t *)(0x4271E610UL))
#define bFM_MFS15_CSIO_SCSCR_CSLVL                *((volatile  uint8_t *)(0x4271E614UL))
#define bFM4_MFS15_CSIO_SCSCR_CSLVL               *((volatile  uint8_t *)(0x4271E614UL))
#define bFM_MFS15_CSIO_SCSCR_SCAM                 *((volatile  uint8_t *)(0x4271E624UL))
#define bFM4_MFS15_CSIO_SCSCR_SCAM                *((volatile  uint8_t *)(0x4271E624UL))

#define bFM_MFS15_CSIO_SCSFR0_CS1SPI              *((volatile  uint8_t *)(0x4271E694UL))
#define bFM4_MFS15_CSIO_SCSFR0_CS1SPI             *((volatile  uint8_t *)(0x4271E694UL))
#define bFM_MFS15_CSIO_SCSFR0_CS1SCINV            *((volatile  uint8_t *)(0x4271E698UL))
#define bFM4_MFS15_CSIO_SCSFR0_CS1SCINV           *((volatile  uint8_t *)(0x4271E698UL))
#define bFM_MFS15_CSIO_SCSFR0_CS1CSLVL            *((volatile  uint8_t *)(0x4271E69CUL))
#define bFM4_MFS15_CSIO_SCSFR0_CS1CSLVL           *((volatile  uint8_t *)(0x4271E69CUL))

#define bFM_MFS15_CSIO_SCSFR1_CS2SPI              *((volatile  uint8_t *)(0x4271E6B4UL))
#define bFM4_MFS15_CSIO_SCSFR1_CS2SPI             *((volatile  uint8_t *)(0x4271E6B4UL))
#define bFM_MFS15_CSIO_SCSFR1_CS2SCINV            *((volatile  uint8_t *)(0x4271E6B8UL))
#define bFM4_MFS15_CSIO_SCSFR1_CS2SCINV           *((volatile  uint8_t *)(0x4271E6B8UL))
#define bFM_MFS15_CSIO_SCSFR1_CS2CSLVL            *((volatile  uint8_t *)(0x4271E6BCUL))
#define bFM4_MFS15_CSIO_SCSFR1_CS2CSLVL           *((volatile  uint8_t *)(0x4271E6BCUL))

#define bFM_MFS15_CSIO_SCSFR2_CS3SPI              *((volatile  uint8_t *)(0x4271E714UL))
#define bFM4_MFS15_CSIO_SCSFR2_CS3SPI             *((volatile  uint8_t *)(0x4271E714UL))
#define bFM_MFS15_CSIO_SCSFR2_CS3SCINV            *((volatile  uint8_t *)(0x4271E718UL))
#define bFM4_MFS15_CSIO_SCSFR2_CS3SCINV           *((volatile  uint8_t *)(0x4271E718UL))
#define bFM_MFS15_CSIO_SCSFR2_CS3CSLVL            *((volatile  uint8_t *)(0x4271E71CUL))
#define bFM4_MFS15_CSIO_SCSFR2_CS3CSLVL           *((volatile  uint8_t *)(0x4271E71CUL))

#define bFM_MFS15_CSIO_SMR_SOE                    *((volatile  uint8_t *)(0x4271E000UL))
#define bFM4_MFS15_CSIO_SMR_SOE                   *((volatile  uint8_t *)(0x4271E000UL))
#define bFM_MFS15_CSIO_SMR_SCKE                   *((volatile  uint8_t *)(0x4271E004UL))
#define bFM4_MFS15_CSIO_SMR_SCKE                  *((volatile  uint8_t *)(0x4271E004UL))
#define bFM_MFS15_CSIO_SMR_BDS                    *((volatile  uint8_t *)(0x4271E008UL))
#define bFM4_MFS15_CSIO_SMR_BDS                   *((volatile  uint8_t *)(0x4271E008UL))
#define bFM_MFS15_CSIO_SMR_SCINV                  *((volatile  uint8_t *)(0x4271E00CUL))
#define bFM4_MFS15_CSIO_SMR_SCINV                 *((volatile  uint8_t *)(0x4271E00CUL))

#define bFM_MFS15_CSIO_SSR_TBI                    *((volatile  uint8_t *)(0x4271E0A0UL))
#define bFM4_MFS15_CSIO_SSR_TBI                   *((volatile  uint8_t *)(0x4271E0A0UL))
#define bFM_MFS15_CSIO_SSR_TDRE                   *((volatile  uint8_t *)(0x4271E0A4UL))
#define bFM4_MFS15_CSIO_SSR_TDRE                  *((volatile  uint8_t *)(0x4271E0A4UL))
#define bFM_MFS15_CSIO_SSR_RDRF                   *((volatile  uint8_t *)(0x4271E0A8UL))
#define bFM4_MFS15_CSIO_SSR_RDRF                  *((volatile  uint8_t *)(0x4271E0A8UL))
#define bFM_MFS15_CSIO_SSR_ORE                    *((volatile  uint8_t *)(0x4271E0ACUL))
#define bFM4_MFS15_CSIO_SSR_ORE                   *((volatile  uint8_t *)(0x4271E0ACUL))
#define bFM_MFS15_CSIO_SSR_AWC                    *((volatile  uint8_t *)(0x4271E0B0UL))
#define bFM4_MFS15_CSIO_SSR_AWC                   *((volatile  uint8_t *)(0x4271E0B0UL))
#define bFM_MFS15_CSIO_SSR_REC                    *((volatile  uint8_t *)(0x4271E0BCUL))
#define bFM4_MFS15_CSIO_SSR_REC                   *((volatile  uint8_t *)(0x4271E0BCUL))

#define bFM_MFS15_I2C_EIBCR_BEC                   *((volatile  uint8_t *)(0x4271E3A0UL))
#define bFM4_MFS15_I2C_EIBCR_BEC                  *((volatile  uint8_t *)(0x4271E3A0UL))
#define bFM_MFS15_I2C_EIBCR_SOCE                  *((volatile  uint8_t *)(0x4271E3A4UL))
#define bFM4_MFS15_I2C_EIBCR_SOCE                 *((volatile  uint8_t *)(0x4271E3A4UL))
#define bFM_MFS15_I2C_EIBCR_SCLC                  *((volatile  uint8_t *)(0x4271E3A8UL))
#define bFM4_MFS15_I2C_EIBCR_SCLC                 *((volatile  uint8_t *)(0x4271E3A8UL))
#define bFM_MFS15_I2C_EIBCR_SDAC                  *((volatile  uint8_t *)(0x4271E3ACUL))
#define bFM4_MFS15_I2C_EIBCR_SDAC                 *((volatile  uint8_t *)(0x4271E3ACUL))
#define bFM_MFS15_I2C_EIBCR_SCLS                  *((volatile  uint8_t *)(0x4271E3B0UL))
#define bFM4_MFS15_I2C_EIBCR_SCLS                 *((volatile  uint8_t *)(0x4271E3B0UL))
#define bFM_MFS15_I2C_EIBCR_SDAS                  *((volatile  uint8_t *)(0x4271E3B4UL))
#define bFM4_MFS15_I2C_EIBCR_SDAS                 *((volatile  uint8_t *)(0x4271E3B4UL))

#define bFM_MFS15_I2C_FCR_FE1                     *((volatile  uint8_t *)(0x4271E280UL))
#define bFM4_MFS15_I2C_FCR_FE1                    *((volatile  uint8_t *)(0x4271E280UL))
#define bFM_MFS15_I2C_FCR_FE2                     *((volatile  uint8_t *)(0x4271E284UL))
#define bFM4_MFS15_I2C_FCR_FE2                    *((volatile  uint8_t *)(0x4271E284UL))
#define bFM_MFS15_I2C_FCR_FCL1                    *((volatile  uint8_t *)(0x4271E288UL))
#define bFM4_MFS15_I2C_FCR_FCL1                   *((volatile  uint8_t *)(0x4271E288UL))
#define bFM_MFS15_I2C_FCR_FCL2                    *((volatile  uint8_t *)(0x4271E28CUL))
#define bFM4_MFS15_I2C_FCR_FCL2                   *((volatile  uint8_t *)(0x4271E28CUL))
#define bFM_MFS15_I2C_FCR_FSET                    *((volatile  uint8_t *)(0x4271E290UL))
#define bFM4_MFS15_I2C_FCR_FSET                   *((volatile  uint8_t *)(0x4271E290UL))
#define bFM_MFS15_I2C_FCR_FLD                     *((volatile  uint8_t *)(0x4271E294UL))
#define bFM4_MFS15_I2C_FCR_FLD                    *((volatile  uint8_t *)(0x4271E294UL))
#define bFM_MFS15_I2C_FCR_FLST                    *((volatile  uint8_t *)(0x4271E298UL))
#define bFM4_MFS15_I2C_FCR_FLST                   *((volatile  uint8_t *)(0x4271E298UL))
#define bFM_MFS15_I2C_FCR_FSEL                    *((volatile  uint8_t *)(0x4271E2A0UL))
#define bFM4_MFS15_I2C_FCR_FSEL                   *((volatile  uint8_t *)(0x4271E2A0UL))
#define bFM_MFS15_I2C_FCR_FTIE                    *((volatile  uint8_t *)(0x4271E2A4UL))
#define bFM4_MFS15_I2C_FCR_FTIE                   *((volatile  uint8_t *)(0x4271E2A4UL))
#define bFM_MFS15_I2C_FCR_FDRQ                    *((volatile  uint8_t *)(0x4271E2A8UL))
#define bFM4_MFS15_I2C_FCR_FDRQ                   *((volatile  uint8_t *)(0x4271E2A8UL))
#define bFM_MFS15_I2C_FCR_FRIIE                   *((volatile  uint8_t *)(0x4271E2ACUL))
#define bFM4_MFS15_I2C_FCR_FRIIE                  *((volatile  uint8_t *)(0x4271E2ACUL))
#define bFM_MFS15_I2C_FCR_FLSTE                   *((volatile  uint8_t *)(0x4271E2B0UL))
#define bFM4_MFS15_I2C_FCR_FLSTE                  *((volatile  uint8_t *)(0x4271E2B0UL))

#define bFM_MFS15_I2C_IBCR_INT                    *((volatile  uint8_t *)(0x4271E020UL))
#define bFM4_MFS15_I2C_IBCR_INT                   *((volatile  uint8_t *)(0x4271E020UL))
#define bFM_MFS15_I2C_IBCR_BER                    *((volatile  uint8_t *)(0x4271E024UL))
#define bFM4_MFS15_I2C_IBCR_BER                   *((volatile  uint8_t *)(0x4271E024UL))
#define bFM_MFS15_I2C_IBCR_INTE                   *((volatile  uint8_t *)(0x4271E028UL))
#define bFM4_MFS15_I2C_IBCR_INTE                  *((volatile  uint8_t *)(0x4271E028UL))
#define bFM_MFS15_I2C_IBCR_CNDE                   *((volatile  uint8_t *)(0x4271E02CUL))
#define bFM4_MFS15_I2C_IBCR_CNDE                  *((volatile  uint8_t *)(0x4271E02CUL))
#define bFM_MFS15_I2C_IBCR_WSEL                   *((volatile  uint8_t *)(0x4271E030UL))
#define bFM4_MFS15_I2C_IBCR_WSEL                  *((volatile  uint8_t *)(0x4271E030UL))
#define bFM_MFS15_I2C_IBCR_ACKE                   *((volatile  uint8_t *)(0x4271E034UL))
#define bFM4_MFS15_I2C_IBCR_ACKE                  *((volatile  uint8_t *)(0x4271E034UL))
#define bFM_MFS15_I2C_IBCR_ACT_SCC                *((volatile  uint8_t *)(0x4271E038UL))
#define bFM4_MFS15_I2C_IBCR_ACT_SCC               *((volatile  uint8_t *)(0x4271E038UL))
#define bFM_MFS15_I2C_IBCR_MSS                    *((volatile  uint8_t *)(0x4271E03CUL))
#define bFM4_MFS15_I2C_IBCR_MSS                   *((volatile  uint8_t *)(0x4271E03CUL))

#define bFM_MFS15_I2C_IBSR_BB                     *((volatile  uint8_t *)(0x4271E080UL))
#define bFM4_MFS15_I2C_IBSR_BB                    *((volatile  uint8_t *)(0x4271E080UL))
#define bFM_MFS15_I2C_IBSR_SPC                    *((volatile  uint8_t *)(0x4271E084UL))
#define bFM4_MFS15_I2C_IBSR_SPC                   *((volatile  uint8_t *)(0x4271E084UL))
#define bFM_MFS15_I2C_IBSR_RSC                    *((volatile  uint8_t *)(0x4271E088UL))
#define bFM4_MFS15_I2C_IBSR_RSC                   *((volatile  uint8_t *)(0x4271E088UL))
#define bFM_MFS15_I2C_IBSR_AL                     *((volatile  uint8_t *)(0x4271E08CUL))
#define bFM4_MFS15_I2C_IBSR_AL                    *((volatile  uint8_t *)(0x4271E08CUL))
#define bFM_MFS15_I2C_IBSR_TRX                    *((volatile  uint8_t *)(0x4271E090UL))
#define bFM4_MFS15_I2C_IBSR_TRX                   *((volatile  uint8_t *)(0x4271E090UL))
#define bFM_MFS15_I2C_IBSR_RSA                    *((volatile  uint8_t *)(0x4271E094UL))
#define bFM4_MFS15_I2C_IBSR_RSA                   *((volatile  uint8_t *)(0x4271E094UL))
#define bFM_MFS15_I2C_IBSR_RACK                   *((volatile  uint8_t *)(0x4271E098UL))
#define bFM4_MFS15_I2C_IBSR_RACK                  *((volatile  uint8_t *)(0x4271E098UL))
#define bFM_MFS15_I2C_IBSR_FBT                    *((volatile  uint8_t *)(0x4271E09CUL))
#define bFM4_MFS15_I2C_IBSR_FBT                   *((volatile  uint8_t *)(0x4271E09CUL))

#define bFM_MFS15_I2C_ISBA_SAEN                   *((volatile  uint8_t *)(0x4271E21CUL))
#define bFM4_MFS15_I2C_ISBA_SAEN                  *((volatile  uint8_t *)(0x4271E21CUL))

#define bFM_MFS15_I2C_ISMK_EN                     *((volatile  uint8_t *)(0x4271E23CUL))
#define bFM4_MFS15_I2C_ISMK_EN                    *((volatile  uint8_t *)(0x4271E23CUL))

#define bFM_MFS15_I2C_SMR_TIE                     *((volatile  uint8_t *)(0x4271E008UL))
#define bFM4_MFS15_I2C_SMR_TIE                    *((volatile  uint8_t *)(0x4271E008UL))
#define bFM_MFS15_I2C_SMR_RIE                     *((volatile  uint8_t *)(0x4271E00CUL))
#define bFM4_MFS15_I2C_SMR_RIE                    *((volatile  uint8_t *)(0x4271E00CUL))

#define bFM_MFS15_I2C_SSR_TBI                     *((volatile  uint8_t *)(0x4271E0A0UL))
#define bFM4_MFS15_I2C_SSR_TBI                    *((volatile  uint8_t *)(0x4271E0A0UL))
#define bFM_MFS15_I2C_SSR_TDRE                    *((volatile  uint8_t *)(0x4271E0A4UL))
#define bFM4_MFS15_I2C_SSR_TDRE                   *((volatile  uint8_t *)(0x4271E0A4UL))
#define bFM_MFS15_I2C_SSR_RDRF                    *((volatile  uint8_t *)(0x4271E0A8UL))
#define bFM4_MFS15_I2C_SSR_RDRF                   *((volatile  uint8_t *)(0x4271E0A8UL))
#define bFM_MFS15_I2C_SSR_ORE                     *((volatile  uint8_t *)(0x4271E0ACUL))
#define bFM4_MFS15_I2C_SSR_ORE                    *((volatile  uint8_t *)(0x4271E0ACUL))
#define bFM_MFS15_I2C_SSR_TBIE                    *((volatile  uint8_t *)(0x4271E0B0UL))
#define bFM4_MFS15_I2C_SSR_TBIE                   *((volatile  uint8_t *)(0x4271E0B0UL))
#define bFM_MFS15_I2C_SSR_DMA                     *((volatile  uint8_t *)(0x4271E0B4UL))
#define bFM4_MFS15_I2C_SSR_DMA                    *((volatile  uint8_t *)(0x4271E0B4UL))
#define bFM_MFS15_I2C_SSR_TSET                    *((volatile  uint8_t *)(0x4271E0B8UL))
#define bFM4_MFS15_I2C_SSR_TSET                   *((volatile  uint8_t *)(0x4271E0B8UL))
#define bFM_MFS15_I2C_SSR_REC                     *((volatile  uint8_t *)(0x4271E0BCUL))
#define bFM4_MFS15_I2C_SSR_REC                    *((volatile  uint8_t *)(0x4271E0BCUL))

#define bFM_MFS15_LIN_BGR_EXT                     *((volatile  uint8_t *)(0x4271E1BCUL))
#define bFM4_MFS15_LIN_BGR_EXT                    *((volatile  uint8_t *)(0x4271E1BCUL))

#define bFM_MFS15_LIN_ESCR_LBIE                   *((volatile  uint8_t *)(0x4271E090UL))
#define bFM4_MFS15_LIN_ESCR_LBIE                  *((volatile  uint8_t *)(0x4271E090UL))
#define bFM_MFS15_LIN_ESCR_ESBL                   *((volatile  uint8_t *)(0x4271E098UL))
#define bFM4_MFS15_LIN_ESCR_ESBL                  *((volatile  uint8_t *)(0x4271E098UL))

#define bFM_MFS15_LIN_FCR_FE1                     *((volatile  uint8_t *)(0x4271E280UL))
#define bFM4_MFS15_LIN_FCR_FE1                    *((volatile  uint8_t *)(0x4271E280UL))
#define bFM_MFS15_LIN_FCR_FE2                     *((volatile  uint8_t *)(0x4271E284UL))
#define bFM4_MFS15_LIN_FCR_FE2                    *((volatile  uint8_t *)(0x4271E284UL))
#define bFM_MFS15_LIN_FCR_FCL1                    *((volatile  uint8_t *)(0x4271E288UL))
#define bFM4_MFS15_LIN_FCR_FCL1                   *((volatile  uint8_t *)(0x4271E288UL))
#define bFM_MFS15_LIN_FCR_FCL2                    *((volatile  uint8_t *)(0x4271E28CUL))
#define bFM4_MFS15_LIN_FCR_FCL2                   *((volatile  uint8_t *)(0x4271E28CUL))
#define bFM_MFS15_LIN_FCR_FSET                    *((volatile  uint8_t *)(0x4271E290UL))
#define bFM4_MFS15_LIN_FCR_FSET                   *((volatile  uint8_t *)(0x4271E290UL))
#define bFM_MFS15_LIN_FCR_FLD                     *((volatile  uint8_t *)(0x4271E294UL))
#define bFM4_MFS15_LIN_FCR_FLD                    *((volatile  uint8_t *)(0x4271E294UL))
#define bFM_MFS15_LIN_FCR_FLST                    *((volatile  uint8_t *)(0x4271E298UL))
#define bFM4_MFS15_LIN_FCR_FLST                   *((volatile  uint8_t *)(0x4271E298UL))
#define bFM_MFS15_LIN_FCR_FSEL                    *((volatile  uint8_t *)(0x4271E2A0UL))
#define bFM4_MFS15_LIN_FCR_FSEL                   *((volatile  uint8_t *)(0x4271E2A0UL))
#define bFM_MFS15_LIN_FCR_FTIE                    *((volatile  uint8_t *)(0x4271E2A4UL))
#define bFM4_MFS15_LIN_FCR_FTIE                   *((volatile  uint8_t *)(0x4271E2A4UL))
#define bFM_MFS15_LIN_FCR_FDRQ                    *((volatile  uint8_t *)(0x4271E2A8UL))
#define bFM4_MFS15_LIN_FCR_FDRQ                   *((volatile  uint8_t *)(0x4271E2A8UL))
#define bFM_MFS15_LIN_FCR_FRIIE                   *((volatile  uint8_t *)(0x4271E2ACUL))
#define bFM4_MFS15_LIN_FCR_FRIIE                  *((volatile  uint8_t *)(0x4271E2ACUL))
#define bFM_MFS15_LIN_FCR_FLSTE                   *((volatile  uint8_t *)(0x4271E2B0UL))
#define bFM4_MFS15_LIN_FCR_FLSTE                  *((volatile  uint8_t *)(0x4271E2B0UL))

#define bFM_MFS15_LIN_SCR_TXE                     *((volatile  uint8_t *)(0x4271E020UL))
#define bFM4_MFS15_LIN_SCR_TXE                    *((volatile  uint8_t *)(0x4271E020UL))
#define bFM_MFS15_LIN_SCR_RXE                     *((volatile  uint8_t *)(0x4271E024UL))
#define bFM4_MFS15_LIN_SCR_RXE                    *((volatile  uint8_t *)(0x4271E024UL))
#define bFM_MFS15_LIN_SCR_TBIE                    *((volatile  uint8_t *)(0x4271E028UL))
#define bFM4_MFS15_LIN_SCR_TBIE                   *((volatile  uint8_t *)(0x4271E028UL))
#define bFM_MFS15_LIN_SCR_TIE                     *((volatile  uint8_t *)(0x4271E02CUL))
#define bFM4_MFS15_LIN_SCR_TIE                    *((volatile  uint8_t *)(0x4271E02CUL))
#define bFM_MFS15_LIN_SCR_RIE                     *((volatile  uint8_t *)(0x4271E030UL))
#define bFM4_MFS15_LIN_SCR_RIE                    *((volatile  uint8_t *)(0x4271E030UL))
#define bFM_MFS15_LIN_SCR_LBR                     *((volatile  uint8_t *)(0x4271E034UL))
#define bFM4_MFS15_LIN_SCR_LBR                    *((volatile  uint8_t *)(0x4271E034UL))
#define bFM_MFS15_LIN_SCR_MS                      *((volatile  uint8_t *)(0x4271E038UL))
#define bFM4_MFS15_LIN_SCR_MS                     *((volatile  uint8_t *)(0x4271E038UL))
#define bFM_MFS15_LIN_SCR_UPCL                    *((volatile  uint8_t *)(0x4271E03CUL))
#define bFM4_MFS15_LIN_SCR_UPCL                   *((volatile  uint8_t *)(0x4271E03CUL))

#define bFM_MFS15_LIN_SMR_SOE                     *((volatile  uint8_t *)(0x4271E000UL))
#define bFM4_MFS15_LIN_SMR_SOE                    *((volatile  uint8_t *)(0x4271E000UL))
#define bFM_MFS15_LIN_SMR_SBL                     *((volatile  uint8_t *)(0x4271E00CUL))
#define bFM4_MFS15_LIN_SMR_SBL                    *((volatile  uint8_t *)(0x4271E00CUL))
#define bFM_MFS15_LIN_SMR_WUCR                    *((volatile  uint8_t *)(0x4271E010UL))
#define bFM4_MFS15_LIN_SMR_WUCR                   *((volatile  uint8_t *)(0x4271E010UL))

#define bFM_MFS15_LIN_SSR_TBI                     *((volatile  uint8_t *)(0x4271E0A0UL))
#define bFM4_MFS15_LIN_SSR_TBI                    *((volatile  uint8_t *)(0x4271E0A0UL))
#define bFM_MFS15_LIN_SSR_TDRE                    *((volatile  uint8_t *)(0x4271E0A4UL))
#define bFM4_MFS15_LIN_SSR_TDRE                   *((volatile  uint8_t *)(0x4271E0A4UL))
#define bFM_MFS15_LIN_SSR_RDRF                    *((volatile  uint8_t *)(0x4271E0A8UL))
#define bFM4_MFS15_LIN_SSR_RDRF                   *((volatile  uint8_t *)(0x4271E0A8UL))
#define bFM_MFS15_LIN_SSR_ORE                     *((volatile  uint8_t *)(0x4271E0ACUL))
#define bFM4_MFS15_LIN_SSR_ORE                    *((volatile  uint8_t *)(0x4271E0ACUL))
#define bFM_MFS15_LIN_SSR_FRE                     *((volatile  uint8_t *)(0x4271E0B0UL))
#define bFM4_MFS15_LIN_SSR_FRE                    *((volatile  uint8_t *)(0x4271E0B0UL))
#define bFM_MFS15_LIN_SSR_LBD                     *((volatile  uint8_t *)(0x4271E0B4UL))
#define bFM4_MFS15_LIN_SSR_LBD                    *((volatile  uint8_t *)(0x4271E0B4UL))
#define bFM_MFS15_LIN_SSR_REC                     *((volatile  uint8_t *)(0x4271E0BCUL))
#define bFM4_MFS15_LIN_SSR_REC                    *((volatile  uint8_t *)(0x4271E0BCUL))

#define bFM_MFS15_UART_BGR_EXT                    *((volatile  uint8_t *)(0x4271E1BCUL))
#define bFM4_MFS15_UART_BGR_EXT                   *((volatile  uint8_t *)(0x4271E1BCUL))

#define bFM_MFS15_UART_ESCR_P                     *((volatile  uint8_t *)(0x4271E08CUL))
#define bFM4_MFS15_UART_ESCR_P                    *((volatile  uint8_t *)(0x4271E08CUL))
#define bFM_MFS15_UART_ESCR_PEN                   *((volatile  uint8_t *)(0x4271E090UL))
#define bFM4_MFS15_UART_ESCR_PEN                  *((volatile  uint8_t *)(0x4271E090UL))
#define bFM_MFS15_UART_ESCR_INV                   *((volatile  uint8_t *)(0x4271E094UL))
#define bFM4_MFS15_UART_ESCR_INV                  *((volatile  uint8_t *)(0x4271E094UL))
#define bFM_MFS15_UART_ESCR_ESBL                  *((volatile  uint8_t *)(0x4271E098UL))
#define bFM4_MFS15_UART_ESCR_ESBL                 *((volatile  uint8_t *)(0x4271E098UL))
#define bFM_MFS15_UART_ESCR_FLWEN                 *((volatile  uint8_t *)(0x4271E09CUL))
#define bFM4_MFS15_UART_ESCR_FLWEN                *((volatile  uint8_t *)(0x4271E09CUL))

#define bFM_MFS15_UART_FCR_FE1                    *((volatile  uint8_t *)(0x4271E280UL))
#define bFM4_MFS15_UART_FCR_FE1                   *((volatile  uint8_t *)(0x4271E280UL))
#define bFM_MFS15_UART_FCR_FE2                    *((volatile  uint8_t *)(0x4271E284UL))
#define bFM4_MFS15_UART_FCR_FE2                   *((volatile  uint8_t *)(0x4271E284UL))
#define bFM_MFS15_UART_FCR_FCL1                   *((volatile  uint8_t *)(0x4271E288UL))
#define bFM4_MFS15_UART_FCR_FCL1                  *((volatile  uint8_t *)(0x4271E288UL))
#define bFM_MFS15_UART_FCR_FCL2                   *((volatile  uint8_t *)(0x4271E28CUL))
#define bFM4_MFS15_UART_FCR_FCL2                  *((volatile  uint8_t *)(0x4271E28CUL))
#define bFM_MFS15_UART_FCR_FSET                   *((volatile  uint8_t *)(0x4271E290UL))
#define bFM4_MFS15_UART_FCR_FSET                  *((volatile  uint8_t *)(0x4271E290UL))
#define bFM_MFS15_UART_FCR_FLD                    *((volatile  uint8_t *)(0x4271E294UL))
#define bFM4_MFS15_UART_FCR_FLD                   *((volatile  uint8_t *)(0x4271E294UL))
#define bFM_MFS15_UART_FCR_FLST                   *((volatile  uint8_t *)(0x4271E298UL))
#define bFM4_MFS15_UART_FCR_FLST                  *((volatile  uint8_t *)(0x4271E298UL))
#define bFM_MFS15_UART_FCR_FSEL                   *((volatile  uint8_t *)(0x4271E2A0UL))
#define bFM4_MFS15_UART_FCR_FSEL                  *((volatile  uint8_t *)(0x4271E2A0UL))
#define bFM_MFS15_UART_FCR_FTIE                   *((volatile  uint8_t *)(0x4271E2A4UL))
#define bFM4_MFS15_UART_FCR_FTIE                  *((volatile  uint8_t *)(0x4271E2A4UL))
#define bFM_MFS15_UART_FCR_FDRQ                   *((volatile  uint8_t *)(0x4271E2A8UL))
#define bFM4_MFS15_UART_FCR_FDRQ                  *((volatile  uint8_t *)(0x4271E2A8UL))
#define bFM_MFS15_UART_FCR_FRIIE                  *((volatile  uint8_t *)(0x4271E2ACUL))
#define bFM4_MFS15_UART_FCR_FRIIE                 *((volatile  uint8_t *)(0x4271E2ACUL))
#define bFM_MFS15_UART_FCR_FLSTE                  *((volatile  uint8_t *)(0x4271E2B0UL))
#define bFM4_MFS15_UART_FCR_FLSTE                 *((volatile  uint8_t *)(0x4271E2B0UL))

#define bFM_MFS15_UART_SCR_TXE                    *((volatile  uint8_t *)(0x4271E020UL))
#define bFM4_MFS15_UART_SCR_TXE                   *((volatile  uint8_t *)(0x4271E020UL))
#define bFM_MFS15_UART_SCR_RXE                    *((volatile  uint8_t *)(0x4271E024UL))
#define bFM4_MFS15_UART_SCR_RXE                   *((volatile  uint8_t *)(0x4271E024UL))
#define bFM_MFS15_UART_SCR_TBIE                   *((volatile  uint8_t *)(0x4271E028UL))
#define bFM4_MFS15_UART_SCR_TBIE                  *((volatile  uint8_t *)(0x4271E028UL))
#define bFM_MFS15_UART_SCR_TIE                    *((volatile  uint8_t *)(0x4271E02CUL))
#define bFM4_MFS15_UART_SCR_TIE                   *((volatile  uint8_t *)(0x4271E02CUL))
#define bFM_MFS15_UART_SCR_RIE                    *((volatile  uint8_t *)(0x4271E030UL))
#define bFM4_MFS15_UART_SCR_RIE                   *((volatile  uint8_t *)(0x4271E030UL))
#define bFM_MFS15_UART_SCR_UPCL                   *((volatile  uint8_t *)(0x4271E03CUL))
#define bFM4_MFS15_UART_SCR_UPCL                  *((volatile  uint8_t *)(0x4271E03CUL))

#define bFM_MFS15_UART_SMR_SOE                    *((volatile  uint8_t *)(0x4271E000UL))
#define bFM4_MFS15_UART_SMR_SOE                   *((volatile  uint8_t *)(0x4271E000UL))
#define bFM_MFS15_UART_SMR_BDS                    *((volatile  uint8_t *)(0x4271E008UL))
#define bFM4_MFS15_UART_SMR_BDS                   *((volatile  uint8_t *)(0x4271E008UL))
#define bFM_MFS15_UART_SMR_SBL                    *((volatile  uint8_t *)(0x4271E00CUL))
#define bFM4_MFS15_UART_SMR_SBL                   *((volatile  uint8_t *)(0x4271E00CUL))

#define bFM_MFS15_UART_SSR_TBI                    *((volatile  uint8_t *)(0x4271E0A0UL))
#define bFM4_MFS15_UART_SSR_TBI                   *((volatile  uint8_t *)(0x4271E0A0UL))
#define bFM_MFS15_UART_SSR_TDRE                   *((volatile  uint8_t *)(0x4271E0A4UL))
#define bFM4_MFS15_UART_SSR_TDRE                  *((volatile  uint8_t *)(0x4271E0A4UL))
#define bFM_MFS15_UART_SSR_RDRF                   *((volatile  uint8_t *)(0x4271E0A8UL))
#define bFM4_MFS15_UART_SSR_RDRF                  *((volatile  uint8_t *)(0x4271E0A8UL))
#define bFM_MFS15_UART_SSR_ORE                    *((volatile  uint8_t *)(0x4271E0ACUL))
#define bFM4_MFS15_UART_SSR_ORE                   *((volatile  uint8_t *)(0x4271E0ACUL))
#define bFM_MFS15_UART_SSR_FRE                    *((volatile  uint8_t *)(0x4271E0B0UL))
#define bFM4_MFS15_UART_SSR_FRE                   *((volatile  uint8_t *)(0x4271E0B0UL))
#define bFM_MFS15_UART_SSR_PE                     *((volatile  uint8_t *)(0x4271E0B4UL))
#define bFM4_MFS15_UART_SSR_PE                    *((volatile  uint8_t *)(0x4271E0B4UL))
#define bFM_MFS15_UART_SSR_REC                    *((volatile  uint8_t *)(0x4271E0BCUL))
#define bFM4_MFS15_UART_SSR_REC                   *((volatile  uint8_t *)(0x4271E0BCUL))


/*******************************************************************************
* MFS Registers MFS2
*   Bitband Section
*******************************************************************************/
#define bFM_MFS2_CSIO_ESCR_CSFE                   *((volatile  uint8_t *)(0x42704094UL))
#define bFM4_MFS2_CSIO_ESCR_CSFE                  *((volatile  uint8_t *)(0x42704094UL))
#define bFM_MFS2_CSIO_ESCR_L3                     *((volatile  uint8_t *)(0x42704098UL))
#define bFM4_MFS2_CSIO_ESCR_L3                    *((volatile  uint8_t *)(0x42704098UL))
#define bFM_MFS2_CSIO_ESCR_SOP                    *((volatile  uint8_t *)(0x4270409CUL))
#define bFM4_MFS2_CSIO_ESCR_SOP                   *((volatile  uint8_t *)(0x4270409CUL))

#define bFM_MFS2_CSIO_FCR_FE1                     *((volatile  uint8_t *)(0x42704280UL))
#define bFM4_MFS2_CSIO_FCR_FE1                    *((volatile  uint8_t *)(0x42704280UL))
#define bFM_MFS2_CSIO_FCR_FE2                     *((volatile  uint8_t *)(0x42704284UL))
#define bFM4_MFS2_CSIO_FCR_FE2                    *((volatile  uint8_t *)(0x42704284UL))
#define bFM_MFS2_CSIO_FCR_FCL1                    *((volatile  uint8_t *)(0x42704288UL))
#define bFM4_MFS2_CSIO_FCR_FCL1                   *((volatile  uint8_t *)(0x42704288UL))
#define bFM_MFS2_CSIO_FCR_FCL2                    *((volatile  uint8_t *)(0x4270428CUL))
#define bFM4_MFS2_CSIO_FCR_FCL2                   *((volatile  uint8_t *)(0x4270428CUL))
#define bFM_MFS2_CSIO_FCR_FSET                    *((volatile  uint8_t *)(0x42704290UL))
#define bFM4_MFS2_CSIO_FCR_FSET                   *((volatile  uint8_t *)(0x42704290UL))
#define bFM_MFS2_CSIO_FCR_FLD                     *((volatile  uint8_t *)(0x42704294UL))
#define bFM4_MFS2_CSIO_FCR_FLD                    *((volatile  uint8_t *)(0x42704294UL))
#define bFM_MFS2_CSIO_FCR_FLST                    *((volatile  uint8_t *)(0x42704298UL))
#define bFM4_MFS2_CSIO_FCR_FLST                   *((volatile  uint8_t *)(0x42704298UL))
#define bFM_MFS2_CSIO_FCR_FSEL                    *((volatile  uint8_t *)(0x427042A0UL))
#define bFM4_MFS2_CSIO_FCR_FSEL                   *((volatile  uint8_t *)(0x427042A0UL))
#define bFM_MFS2_CSIO_FCR_FTIE                    *((volatile  uint8_t *)(0x427042A4UL))
#define bFM4_MFS2_CSIO_FCR_FTIE                   *((volatile  uint8_t *)(0x427042A4UL))
#define bFM_MFS2_CSIO_FCR_FDRQ                    *((volatile  uint8_t *)(0x427042A8UL))
#define bFM4_MFS2_CSIO_FCR_FDRQ                   *((volatile  uint8_t *)(0x427042A8UL))
#define bFM_MFS2_CSIO_FCR_FRIIE                   *((volatile  uint8_t *)(0x427042ACUL))
#define bFM4_MFS2_CSIO_FCR_FRIIE                  *((volatile  uint8_t *)(0x427042ACUL))
#define bFM_MFS2_CSIO_FCR_FLSTE                   *((volatile  uint8_t *)(0x427042B0UL))
#define bFM4_MFS2_CSIO_FCR_FLSTE                  *((volatile  uint8_t *)(0x427042B0UL))

#define bFM_MFS2_CSIO_SACSR_TMRE                  *((volatile  uint8_t *)(0x42704480UL))
#define bFM4_MFS2_CSIO_SACSR_TMRE                 *((volatile  uint8_t *)(0x42704480UL))
#define bFM_MFS2_CSIO_SACSR_TSYNE                 *((volatile  uint8_t *)(0x42704498UL))
#define bFM4_MFS2_CSIO_SACSR_TSYNE                *((volatile  uint8_t *)(0x42704498UL))
#define bFM_MFS2_CSIO_SACSR_TINTE                 *((volatile  uint8_t *)(0x4270449CUL))
#define bFM4_MFS2_CSIO_SACSR_TINTE                *((volatile  uint8_t *)(0x4270449CUL))
#define bFM_MFS2_CSIO_SACSR_TINT                  *((volatile  uint8_t *)(0x427044A0UL))
#define bFM4_MFS2_CSIO_SACSR_TINT                 *((volatile  uint8_t *)(0x427044A0UL))
#define bFM_MFS2_CSIO_SACSR_CSE                   *((volatile  uint8_t *)(0x427044ACUL))
#define bFM4_MFS2_CSIO_SACSR_CSE                  *((volatile  uint8_t *)(0x427044ACUL))
#define bFM_MFS2_CSIO_SACSR_CSEIE                 *((volatile  uint8_t *)(0x427044B0UL))
#define bFM4_MFS2_CSIO_SACSR_CSEIE                *((volatile  uint8_t *)(0x427044B0UL))
#define bFM_MFS2_CSIO_SACSR_TBEEN                 *((volatile  uint8_t *)(0x427044B4UL))
#define bFM4_MFS2_CSIO_SACSR_TBEEN                *((volatile  uint8_t *)(0x427044B4UL))

#define bFM_MFS2_CSIO_SCR_TXE                     *((volatile  uint8_t *)(0x42704020UL))
#define bFM4_MFS2_CSIO_SCR_TXE                    *((volatile  uint8_t *)(0x42704020UL))
#define bFM_MFS2_CSIO_SCR_RXE                     *((volatile  uint8_t *)(0x42704024UL))
#define bFM4_MFS2_CSIO_SCR_RXE                    *((volatile  uint8_t *)(0x42704024UL))
#define bFM_MFS2_CSIO_SCR_TBIE                    *((volatile  uint8_t *)(0x42704028UL))
#define bFM4_MFS2_CSIO_SCR_TBIE                   *((volatile  uint8_t *)(0x42704028UL))
#define bFM_MFS2_CSIO_SCR_TIE                     *((volatile  uint8_t *)(0x4270402CUL))
#define bFM4_MFS2_CSIO_SCR_TIE                    *((volatile  uint8_t *)(0x4270402CUL))
#define bFM_MFS2_CSIO_SCR_RIE                     *((volatile  uint8_t *)(0x42704030UL))
#define bFM4_MFS2_CSIO_SCR_RIE                    *((volatile  uint8_t *)(0x42704030UL))
#define bFM_MFS2_CSIO_SCR_SPI                     *((volatile  uint8_t *)(0x42704034UL))
#define bFM4_MFS2_CSIO_SCR_SPI                    *((volatile  uint8_t *)(0x42704034UL))
#define bFM_MFS2_CSIO_SCR_MS                      *((volatile  uint8_t *)(0x42704038UL))
#define bFM4_MFS2_CSIO_SCR_MS                     *((volatile  uint8_t *)(0x42704038UL))
#define bFM_MFS2_CSIO_SCR_UPCL                    *((volatile  uint8_t *)(0x4270403CUL))
#define bFM4_MFS2_CSIO_SCR_UPCL                   *((volatile  uint8_t *)(0x4270403CUL))

#define bFM_MFS2_CSIO_SCSCR_CSOE                  *((volatile  uint8_t *)(0x42704600UL))
#define bFM4_MFS2_CSIO_SCSCR_CSOE                 *((volatile  uint8_t *)(0x42704600UL))
#define bFM_MFS2_CSIO_SCSCR_CSEN0                 *((volatile  uint8_t *)(0x42704604UL))
#define bFM4_MFS2_CSIO_SCSCR_CSEN0                *((volatile  uint8_t *)(0x42704604UL))
#define bFM_MFS2_CSIO_SCSCR_CSEN1                 *((volatile  uint8_t *)(0x42704608UL))
#define bFM4_MFS2_CSIO_SCSCR_CSEN1                *((volatile  uint8_t *)(0x42704608UL))
#define bFM_MFS2_CSIO_SCSCR_CSEN2                 *((volatile  uint8_t *)(0x4270460CUL))
#define bFM4_MFS2_CSIO_SCSCR_CSEN2                *((volatile  uint8_t *)(0x4270460CUL))
#define bFM_MFS2_CSIO_SCSCR_CSEN3                 *((volatile  uint8_t *)(0x42704610UL))
#define bFM4_MFS2_CSIO_SCSCR_CSEN3                *((volatile  uint8_t *)(0x42704610UL))
#define bFM_MFS2_CSIO_SCSCR_CSLVL                 *((volatile  uint8_t *)(0x42704614UL))
#define bFM4_MFS2_CSIO_SCSCR_CSLVL                *((volatile  uint8_t *)(0x42704614UL))
#define bFM_MFS2_CSIO_SCSCR_SCAM                  *((volatile  uint8_t *)(0x42704624UL))
#define bFM4_MFS2_CSIO_SCSCR_SCAM                 *((volatile  uint8_t *)(0x42704624UL))

#define bFM_MFS2_CSIO_SCSFR0_CS1SPI               *((volatile  uint8_t *)(0x42704694UL))
#define bFM4_MFS2_CSIO_SCSFR0_CS1SPI              *((volatile  uint8_t *)(0x42704694UL))
#define bFM_MFS2_CSIO_SCSFR0_CS1SCINV             *((volatile  uint8_t *)(0x42704698UL))
#define bFM4_MFS2_CSIO_SCSFR0_CS1SCINV            *((volatile  uint8_t *)(0x42704698UL))
#define bFM_MFS2_CSIO_SCSFR0_CS1CSLVL             *((volatile  uint8_t *)(0x4270469CUL))
#define bFM4_MFS2_CSIO_SCSFR0_CS1CSLVL            *((volatile  uint8_t *)(0x4270469CUL))

#define bFM_MFS2_CSIO_SCSFR1_CS2SPI               *((volatile  uint8_t *)(0x427046B4UL))
#define bFM4_MFS2_CSIO_SCSFR1_CS2SPI              *((volatile  uint8_t *)(0x427046B4UL))
#define bFM_MFS2_CSIO_SCSFR1_CS2SCINV             *((volatile  uint8_t *)(0x427046B8UL))
#define bFM4_MFS2_CSIO_SCSFR1_CS2SCINV            *((volatile  uint8_t *)(0x427046B8UL))
#define bFM_MFS2_CSIO_SCSFR1_CS2CSLVL             *((volatile  uint8_t *)(0x427046BCUL))
#define bFM4_MFS2_CSIO_SCSFR1_CS2CSLVL            *((volatile  uint8_t *)(0x427046BCUL))

#define bFM_MFS2_CSIO_SCSFR2_CS3SPI               *((volatile  uint8_t *)(0x42704714UL))
#define bFM4_MFS2_CSIO_SCSFR2_CS3SPI              *((volatile  uint8_t *)(0x42704714UL))
#define bFM_MFS2_CSIO_SCSFR2_CS3SCINV             *((volatile  uint8_t *)(0x42704718UL))
#define bFM4_MFS2_CSIO_SCSFR2_CS3SCINV            *((volatile  uint8_t *)(0x42704718UL))
#define bFM_MFS2_CSIO_SCSFR2_CS3CSLVL             *((volatile  uint8_t *)(0x4270471CUL))
#define bFM4_MFS2_CSIO_SCSFR2_CS3CSLVL            *((volatile  uint8_t *)(0x4270471CUL))

#define bFM_MFS2_CSIO_SMR_SOE                     *((volatile  uint8_t *)(0x42704000UL))
#define bFM4_MFS2_CSIO_SMR_SOE                    *((volatile  uint8_t *)(0x42704000UL))
#define bFM_MFS2_CSIO_SMR_SCKE                    *((volatile  uint8_t *)(0x42704004UL))
#define bFM4_MFS2_CSIO_SMR_SCKE                   *((volatile  uint8_t *)(0x42704004UL))
#define bFM_MFS2_CSIO_SMR_BDS                     *((volatile  uint8_t *)(0x42704008UL))
#define bFM4_MFS2_CSIO_SMR_BDS                    *((volatile  uint8_t *)(0x42704008UL))
#define bFM_MFS2_CSIO_SMR_SCINV                   *((volatile  uint8_t *)(0x4270400CUL))
#define bFM4_MFS2_CSIO_SMR_SCINV                  *((volatile  uint8_t *)(0x4270400CUL))

#define bFM_MFS2_CSIO_SSR_TBI                     *((volatile  uint8_t *)(0x427040A0UL))
#define bFM4_MFS2_CSIO_SSR_TBI                    *((volatile  uint8_t *)(0x427040A0UL))
#define bFM_MFS2_CSIO_SSR_TDRE                    *((volatile  uint8_t *)(0x427040A4UL))
#define bFM4_MFS2_CSIO_SSR_TDRE                   *((volatile  uint8_t *)(0x427040A4UL))
#define bFM_MFS2_CSIO_SSR_RDRF                    *((volatile  uint8_t *)(0x427040A8UL))
#define bFM4_MFS2_CSIO_SSR_RDRF                   *((volatile  uint8_t *)(0x427040A8UL))
#define bFM_MFS2_CSIO_SSR_ORE                     *((volatile  uint8_t *)(0x427040ACUL))
#define bFM4_MFS2_CSIO_SSR_ORE                    *((volatile  uint8_t *)(0x427040ACUL))
#define bFM_MFS2_CSIO_SSR_AWC                     *((volatile  uint8_t *)(0x427040B0UL))
#define bFM4_MFS2_CSIO_SSR_AWC                    *((volatile  uint8_t *)(0x427040B0UL))
#define bFM_MFS2_CSIO_SSR_REC                     *((volatile  uint8_t *)(0x427040BCUL))
#define bFM4_MFS2_CSIO_SSR_REC                    *((volatile  uint8_t *)(0x427040BCUL))

#define bFM_MFS2_I2C_EIBCR_BEC                    *((volatile  uint8_t *)(0x427043A0UL))
#define bFM4_MFS2_I2C_EIBCR_BEC                   *((volatile  uint8_t *)(0x427043A0UL))
#define bFM_MFS2_I2C_EIBCR_SOCE                   *((volatile  uint8_t *)(0x427043A4UL))
#define bFM4_MFS2_I2C_EIBCR_SOCE                  *((volatile  uint8_t *)(0x427043A4UL))
#define bFM_MFS2_I2C_EIBCR_SCLC                   *((volatile  uint8_t *)(0x427043A8UL))
#define bFM4_MFS2_I2C_EIBCR_SCLC                  *((volatile  uint8_t *)(0x427043A8UL))
#define bFM_MFS2_I2C_EIBCR_SDAC                   *((volatile  uint8_t *)(0x427043ACUL))
#define bFM4_MFS2_I2C_EIBCR_SDAC                  *((volatile  uint8_t *)(0x427043ACUL))
#define bFM_MFS2_I2C_EIBCR_SCLS                   *((volatile  uint8_t *)(0x427043B0UL))
#define bFM4_MFS2_I2C_EIBCR_SCLS                  *((volatile  uint8_t *)(0x427043B0UL))
#define bFM_MFS2_I2C_EIBCR_SDAS                   *((volatile  uint8_t *)(0x427043B4UL))
#define bFM4_MFS2_I2C_EIBCR_SDAS                  *((volatile  uint8_t *)(0x427043B4UL))

#define bFM_MFS2_I2C_FCR_FE1                      *((volatile  uint8_t *)(0x42704280UL))
#define bFM4_MFS2_I2C_FCR_FE1                     *((volatile  uint8_t *)(0x42704280UL))
#define bFM_MFS2_I2C_FCR_FE2                      *((volatile  uint8_t *)(0x42704284UL))
#define bFM4_MFS2_I2C_FCR_FE2                     *((volatile  uint8_t *)(0x42704284UL))
#define bFM_MFS2_I2C_FCR_FCL1                     *((volatile  uint8_t *)(0x42704288UL))
#define bFM4_MFS2_I2C_FCR_FCL1                    *((volatile  uint8_t *)(0x42704288UL))
#define bFM_MFS2_I2C_FCR_FCL2                     *((volatile  uint8_t *)(0x4270428CUL))
#define bFM4_MFS2_I2C_FCR_FCL2                    *((volatile  uint8_t *)(0x4270428CUL))
#define bFM_MFS2_I2C_FCR_FSET                     *((volatile  uint8_t *)(0x42704290UL))
#define bFM4_MFS2_I2C_FCR_FSET                    *((volatile  uint8_t *)(0x42704290UL))
#define bFM_MFS2_I2C_FCR_FLD                      *((volatile  uint8_t *)(0x42704294UL))
#define bFM4_MFS2_I2C_FCR_FLD                     *((volatile  uint8_t *)(0x42704294UL))
#define bFM_MFS2_I2C_FCR_FLST                     *((volatile  uint8_t *)(0x42704298UL))
#define bFM4_MFS2_I2C_FCR_FLST                    *((volatile  uint8_t *)(0x42704298UL))
#define bFM_MFS2_I2C_FCR_FSEL                     *((volatile  uint8_t *)(0x427042A0UL))
#define bFM4_MFS2_I2C_FCR_FSEL                    *((volatile  uint8_t *)(0x427042A0UL))
#define bFM_MFS2_I2C_FCR_FTIE                     *((volatile  uint8_t *)(0x427042A4UL))
#define bFM4_MFS2_I2C_FCR_FTIE                    *((volatile  uint8_t *)(0x427042A4UL))
#define bFM_MFS2_I2C_FCR_FDRQ                     *((volatile  uint8_t *)(0x427042A8UL))
#define bFM4_MFS2_I2C_FCR_FDRQ                    *((volatile  uint8_t *)(0x427042A8UL))
#define bFM_MFS2_I2C_FCR_FRIIE                    *((volatile  uint8_t *)(0x427042ACUL))
#define bFM4_MFS2_I2C_FCR_FRIIE                   *((volatile  uint8_t *)(0x427042ACUL))
#define bFM_MFS2_I2C_FCR_FLSTE                    *((volatile  uint8_t *)(0x427042B0UL))
#define bFM4_MFS2_I2C_FCR_FLSTE                   *((volatile  uint8_t *)(0x427042B0UL))

#define bFM_MFS2_I2C_IBCR_INT                     *((volatile  uint8_t *)(0x42704020UL))
#define bFM4_MFS2_I2C_IBCR_INT                    *((volatile  uint8_t *)(0x42704020UL))
#define bFM_MFS2_I2C_IBCR_BER                     *((volatile  uint8_t *)(0x42704024UL))
#define bFM4_MFS2_I2C_IBCR_BER                    *((volatile  uint8_t *)(0x42704024UL))
#define bFM_MFS2_I2C_IBCR_INTE                    *((volatile  uint8_t *)(0x42704028UL))
#define bFM4_MFS2_I2C_IBCR_INTE                   *((volatile  uint8_t *)(0x42704028UL))
#define bFM_MFS2_I2C_IBCR_CNDE                    *((volatile  uint8_t *)(0x4270402CUL))
#define bFM4_MFS2_I2C_IBCR_CNDE                   *((volatile  uint8_t *)(0x4270402CUL))
#define bFM_MFS2_I2C_IBCR_WSEL                    *((volatile  uint8_t *)(0x42704030UL))
#define bFM4_MFS2_I2C_IBCR_WSEL                   *((volatile  uint8_t *)(0x42704030UL))
#define bFM_MFS2_I2C_IBCR_ACKE                    *((volatile  uint8_t *)(0x42704034UL))
#define bFM4_MFS2_I2C_IBCR_ACKE                   *((volatile  uint8_t *)(0x42704034UL))
#define bFM_MFS2_I2C_IBCR_ACT_SCC                 *((volatile  uint8_t *)(0x42704038UL))
#define bFM4_MFS2_I2C_IBCR_ACT_SCC                *((volatile  uint8_t *)(0x42704038UL))
#define bFM_MFS2_I2C_IBCR_MSS                     *((volatile  uint8_t *)(0x4270403CUL))
#define bFM4_MFS2_I2C_IBCR_MSS                    *((volatile  uint8_t *)(0x4270403CUL))

#define bFM_MFS2_I2C_IBSR_BB                      *((volatile  uint8_t *)(0x42704080UL))
#define bFM4_MFS2_I2C_IBSR_BB                     *((volatile  uint8_t *)(0x42704080UL))
#define bFM_MFS2_I2C_IBSR_SPC                     *((volatile  uint8_t *)(0x42704084UL))
#define bFM4_MFS2_I2C_IBSR_SPC                    *((volatile  uint8_t *)(0x42704084UL))
#define bFM_MFS2_I2C_IBSR_RSC                     *((volatile  uint8_t *)(0x42704088UL))
#define bFM4_MFS2_I2C_IBSR_RSC                    *((volatile  uint8_t *)(0x42704088UL))
#define bFM_MFS2_I2C_IBSR_AL                      *((volatile  uint8_t *)(0x4270408CUL))
#define bFM4_MFS2_I2C_IBSR_AL                     *((volatile  uint8_t *)(0x4270408CUL))
#define bFM_MFS2_I2C_IBSR_TRX                     *((volatile  uint8_t *)(0x42704090UL))
#define bFM4_MFS2_I2C_IBSR_TRX                    *((volatile  uint8_t *)(0x42704090UL))
#define bFM_MFS2_I2C_IBSR_RSA                     *((volatile  uint8_t *)(0x42704094UL))
#define bFM4_MFS2_I2C_IBSR_RSA                    *((volatile  uint8_t *)(0x42704094UL))
#define bFM_MFS2_I2C_IBSR_RACK                    *((volatile  uint8_t *)(0x42704098UL))
#define bFM4_MFS2_I2C_IBSR_RACK                   *((volatile  uint8_t *)(0x42704098UL))
#define bFM_MFS2_I2C_IBSR_FBT                     *((volatile  uint8_t *)(0x4270409CUL))
#define bFM4_MFS2_I2C_IBSR_FBT                    *((volatile  uint8_t *)(0x4270409CUL))

#define bFM_MFS2_I2C_ISBA_SAEN                    *((volatile  uint8_t *)(0x4270421CUL))
#define bFM4_MFS2_I2C_ISBA_SAEN                   *((volatile  uint8_t *)(0x4270421CUL))

#define bFM_MFS2_I2C_ISMK_EN                      *((volatile  uint8_t *)(0x4270423CUL))
#define bFM4_MFS2_I2C_ISMK_EN                     *((volatile  uint8_t *)(0x4270423CUL))

#define bFM_MFS2_I2C_SMR_TIE                      *((volatile  uint8_t *)(0x42704008UL))
#define bFM4_MFS2_I2C_SMR_TIE                     *((volatile  uint8_t *)(0x42704008UL))
#define bFM_MFS2_I2C_SMR_RIE                      *((volatile  uint8_t *)(0x4270400CUL))
#define bFM4_MFS2_I2C_SMR_RIE                     *((volatile  uint8_t *)(0x4270400CUL))

#define bFM_MFS2_I2C_SSR_TBI                      *((volatile  uint8_t *)(0x427040A0UL))
#define bFM4_MFS2_I2C_SSR_TBI                     *((volatile  uint8_t *)(0x427040A0UL))
#define bFM_MFS2_I2C_SSR_TDRE                     *((volatile  uint8_t *)(0x427040A4UL))
#define bFM4_MFS2_I2C_SSR_TDRE                    *((volatile  uint8_t *)(0x427040A4UL))
#define bFM_MFS2_I2C_SSR_RDRF                     *((volatile  uint8_t *)(0x427040A8UL))
#define bFM4_MFS2_I2C_SSR_RDRF                    *((volatile  uint8_t *)(0x427040A8UL))
#define bFM_MFS2_I2C_SSR_ORE                      *((volatile  uint8_t *)(0x427040ACUL))
#define bFM4_MFS2_I2C_SSR_ORE                     *((volatile  uint8_t *)(0x427040ACUL))
#define bFM_MFS2_I2C_SSR_TBIE                     *((volatile  uint8_t *)(0x427040B0UL))
#define bFM4_MFS2_I2C_SSR_TBIE                    *((volatile  uint8_t *)(0x427040B0UL))
#define bFM_MFS2_I2C_SSR_DMA                      *((volatile  uint8_t *)(0x427040B4UL))
#define bFM4_MFS2_I2C_SSR_DMA                     *((volatile  uint8_t *)(0x427040B4UL))
#define bFM_MFS2_I2C_SSR_TSET                     *((volatile  uint8_t *)(0x427040B8UL))
#define bFM4_MFS2_I2C_SSR_TSET                    *((volatile  uint8_t *)(0x427040B8UL))
#define bFM_MFS2_I2C_SSR_REC                      *((volatile  uint8_t *)(0x427040BCUL))
#define bFM4_MFS2_I2C_SSR_REC                     *((volatile  uint8_t *)(0x427040BCUL))

#define bFM_MFS2_LIN_BGR_EXT                      *((volatile  uint8_t *)(0x427041BCUL))
#define bFM4_MFS2_LIN_BGR_EXT                     *((volatile  uint8_t *)(0x427041BCUL))

#define bFM_MFS2_LIN_ESCR_LBIE                    *((volatile  uint8_t *)(0x42704090UL))
#define bFM4_MFS2_LIN_ESCR_LBIE                   *((volatile  uint8_t *)(0x42704090UL))
#define bFM_MFS2_LIN_ESCR_ESBL                    *((volatile  uint8_t *)(0x42704098UL))
#define bFM4_MFS2_LIN_ESCR_ESBL                   *((volatile  uint8_t *)(0x42704098UL))

#define bFM_MFS2_LIN_FCR_FE1                      *((volatile  uint8_t *)(0x42704280UL))
#define bFM4_MFS2_LIN_FCR_FE1                     *((volatile  uint8_t *)(0x42704280UL))
#define bFM_MFS2_LIN_FCR_FE2                      *((volatile  uint8_t *)(0x42704284UL))
#define bFM4_MFS2_LIN_FCR_FE2                     *((volatile  uint8_t *)(0x42704284UL))
#define bFM_MFS2_LIN_FCR_FCL1                     *((volatile  uint8_t *)(0x42704288UL))
#define bFM4_MFS2_LIN_FCR_FCL1                    *((volatile  uint8_t *)(0x42704288UL))
#define bFM_MFS2_LIN_FCR_FCL2                     *((volatile  uint8_t *)(0x4270428CUL))
#define bFM4_MFS2_LIN_FCR_FCL2                    *((volatile  uint8_t *)(0x4270428CUL))
#define bFM_MFS2_LIN_FCR_FSET                     *((volatile  uint8_t *)(0x42704290UL))
#define bFM4_MFS2_LIN_FCR_FSET                    *((volatile  uint8_t *)(0x42704290UL))
#define bFM_MFS2_LIN_FCR_FLD                      *((volatile  uint8_t *)(0x42704294UL))
#define bFM4_MFS2_LIN_FCR_FLD                     *((volatile  uint8_t *)(0x42704294UL))
#define bFM_MFS2_LIN_FCR_FLST                     *((volatile  uint8_t *)(0x42704298UL))
#define bFM4_MFS2_LIN_FCR_FLST                    *((volatile  uint8_t *)(0x42704298UL))
#define bFM_MFS2_LIN_FCR_FSEL                     *((volatile  uint8_t *)(0x427042A0UL))
#define bFM4_MFS2_LIN_FCR_FSEL                    *((volatile  uint8_t *)(0x427042A0UL))
#define bFM_MFS2_LIN_FCR_FTIE                     *((volatile  uint8_t *)(0x427042A4UL))
#define bFM4_MFS2_LIN_FCR_FTIE                    *((volatile  uint8_t *)(0x427042A4UL))
#define bFM_MFS2_LIN_FCR_FDRQ                     *((volatile  uint8_t *)(0x427042A8UL))
#define bFM4_MFS2_LIN_FCR_FDRQ                    *((volatile  uint8_t *)(0x427042A8UL))
#define bFM_MFS2_LIN_FCR_FRIIE                    *((volatile  uint8_t *)(0x427042ACUL))
#define bFM4_MFS2_LIN_FCR_FRIIE                   *((volatile  uint8_t *)(0x427042ACUL))
#define bFM_MFS2_LIN_FCR_FLSTE                    *((volatile  uint8_t *)(0x427042B0UL))
#define bFM4_MFS2_LIN_FCR_FLSTE                   *((volatile  uint8_t *)(0x427042B0UL))

#define bFM_MFS2_LIN_SCR_TXE                      *((volatile  uint8_t *)(0x42704020UL))
#define bFM4_MFS2_LIN_SCR_TXE                     *((volatile  uint8_t *)(0x42704020UL))
#define bFM_MFS2_LIN_SCR_RXE                      *((volatile  uint8_t *)(0x42704024UL))
#define bFM4_MFS2_LIN_SCR_RXE                     *((volatile  uint8_t *)(0x42704024UL))
#define bFM_MFS2_LIN_SCR_TBIE                     *((volatile  uint8_t *)(0x42704028UL))
#define bFM4_MFS2_LIN_SCR_TBIE                    *((volatile  uint8_t *)(0x42704028UL))
#define bFM_MFS2_LIN_SCR_TIE                      *((volatile  uint8_t *)(0x4270402CUL))
#define bFM4_MFS2_LIN_SCR_TIE                     *((volatile  uint8_t *)(0x4270402CUL))
#define bFM_MFS2_LIN_SCR_RIE                      *((volatile  uint8_t *)(0x42704030UL))
#define bFM4_MFS2_LIN_SCR_RIE                     *((volatile  uint8_t *)(0x42704030UL))
#define bFM_MFS2_LIN_SCR_LBR                      *((volatile  uint8_t *)(0x42704034UL))
#define bFM4_MFS2_LIN_SCR_LBR                     *((volatile  uint8_t *)(0x42704034UL))
#define bFM_MFS2_LIN_SCR_MS                       *((volatile  uint8_t *)(0x42704038UL))
#define bFM4_MFS2_LIN_SCR_MS                      *((volatile  uint8_t *)(0x42704038UL))
#define bFM_MFS2_LIN_SCR_UPCL                     *((volatile  uint8_t *)(0x4270403CUL))
#define bFM4_MFS2_LIN_SCR_UPCL                    *((volatile  uint8_t *)(0x4270403CUL))

#define bFM_MFS2_LIN_SMR_SOE                      *((volatile  uint8_t *)(0x42704000UL))
#define bFM4_MFS2_LIN_SMR_SOE                     *((volatile  uint8_t *)(0x42704000UL))
#define bFM_MFS2_LIN_SMR_SBL                      *((volatile  uint8_t *)(0x4270400CUL))
#define bFM4_MFS2_LIN_SMR_SBL                     *((volatile  uint8_t *)(0x4270400CUL))
#define bFM_MFS2_LIN_SMR_WUCR                     *((volatile  uint8_t *)(0x42704010UL))
#define bFM4_MFS2_LIN_SMR_WUCR                    *((volatile  uint8_t *)(0x42704010UL))

#define bFM_MFS2_LIN_SSR_TBI                      *((volatile  uint8_t *)(0x427040A0UL))
#define bFM4_MFS2_LIN_SSR_TBI                     *((volatile  uint8_t *)(0x427040A0UL))
#define bFM_MFS2_LIN_SSR_TDRE                     *((volatile  uint8_t *)(0x427040A4UL))
#define bFM4_MFS2_LIN_SSR_TDRE                    *((volatile  uint8_t *)(0x427040A4UL))
#define bFM_MFS2_LIN_SSR_RDRF                     *((volatile  uint8_t *)(0x427040A8UL))
#define bFM4_MFS2_LIN_SSR_RDRF                    *((volatile  uint8_t *)(0x427040A8UL))
#define bFM_MFS2_LIN_SSR_ORE                      *((volatile  uint8_t *)(0x427040ACUL))
#define bFM4_MFS2_LIN_SSR_ORE                     *((volatile  uint8_t *)(0x427040ACUL))
#define bFM_MFS2_LIN_SSR_FRE                      *((volatile  uint8_t *)(0x427040B0UL))
#define bFM4_MFS2_LIN_SSR_FRE                     *((volatile  uint8_t *)(0x427040B0UL))
#define bFM_MFS2_LIN_SSR_LBD                      *((volatile  uint8_t *)(0x427040B4UL))
#define bFM4_MFS2_LIN_SSR_LBD                     *((volatile  uint8_t *)(0x427040B4UL))
#define bFM_MFS2_LIN_SSR_REC                      *((volatile  uint8_t *)(0x427040BCUL))
#define bFM4_MFS2_LIN_SSR_REC                     *((volatile  uint8_t *)(0x427040BCUL))

#define bFM_MFS2_UART_BGR_EXT                     *((volatile  uint8_t *)(0x427041BCUL))
#define bFM4_MFS2_UART_BGR_EXT                    *((volatile  uint8_t *)(0x427041BCUL))

#define bFM_MFS2_UART_ESCR_P                      *((volatile  uint8_t *)(0x4270408CUL))
#define bFM4_MFS2_UART_ESCR_P                     *((volatile  uint8_t *)(0x4270408CUL))
#define bFM_MFS2_UART_ESCR_PEN                    *((volatile  uint8_t *)(0x42704090UL))
#define bFM4_MFS2_UART_ESCR_PEN                   *((volatile  uint8_t *)(0x42704090UL))
#define bFM_MFS2_UART_ESCR_INV                    *((volatile  uint8_t *)(0x42704094UL))
#define bFM4_MFS2_UART_ESCR_INV                   *((volatile  uint8_t *)(0x42704094UL))
#define bFM_MFS2_UART_ESCR_ESBL                   *((volatile  uint8_t *)(0x42704098UL))
#define bFM4_MFS2_UART_ESCR_ESBL                  *((volatile  uint8_t *)(0x42704098UL))
#define bFM_MFS2_UART_ESCR_FLWEN                  *((volatile  uint8_t *)(0x4270409CUL))
#define bFM4_MFS2_UART_ESCR_FLWEN                 *((volatile  uint8_t *)(0x4270409CUL))

#define bFM_MFS2_UART_FCR_FE1                     *((volatile  uint8_t *)(0x42704280UL))
#define bFM4_MFS2_UART_FCR_FE1                    *((volatile  uint8_t *)(0x42704280UL))
#define bFM_MFS2_UART_FCR_FE2                     *((volatile  uint8_t *)(0x42704284UL))
#define bFM4_MFS2_UART_FCR_FE2                    *((volatile  uint8_t *)(0x42704284UL))
#define bFM_MFS2_UART_FCR_FCL1                    *((volatile  uint8_t *)(0x42704288UL))
#define bFM4_MFS2_UART_FCR_FCL1                   *((volatile  uint8_t *)(0x42704288UL))
#define bFM_MFS2_UART_FCR_FCL2                    *((volatile  uint8_t *)(0x4270428CUL))
#define bFM4_MFS2_UART_FCR_FCL2                   *((volatile  uint8_t *)(0x4270428CUL))
#define bFM_MFS2_UART_FCR_FSET                    *((volatile  uint8_t *)(0x42704290UL))
#define bFM4_MFS2_UART_FCR_FSET                   *((volatile  uint8_t *)(0x42704290UL))
#define bFM_MFS2_UART_FCR_FLD                     *((volatile  uint8_t *)(0x42704294UL))
#define bFM4_MFS2_UART_FCR_FLD                    *((volatile  uint8_t *)(0x42704294UL))
#define bFM_MFS2_UART_FCR_FLST                    *((volatile  uint8_t *)(0x42704298UL))
#define bFM4_MFS2_UART_FCR_FLST                   *((volatile  uint8_t *)(0x42704298UL))
#define bFM_MFS2_UART_FCR_FSEL                    *((volatile  uint8_t *)(0x427042A0UL))
#define bFM4_MFS2_UART_FCR_FSEL                   *((volatile  uint8_t *)(0x427042A0UL))
#define bFM_MFS2_UART_FCR_FTIE                    *((volatile  uint8_t *)(0x427042A4UL))
#define bFM4_MFS2_UART_FCR_FTIE                   *((volatile  uint8_t *)(0x427042A4UL))
#define bFM_MFS2_UART_FCR_FDRQ                    *((volatile  uint8_t *)(0x427042A8UL))
#define bFM4_MFS2_UART_FCR_FDRQ                   *((volatile  uint8_t *)(0x427042A8UL))
#define bFM_MFS2_UART_FCR_FRIIE                   *((volatile  uint8_t *)(0x427042ACUL))
#define bFM4_MFS2_UART_FCR_FRIIE                  *((volatile  uint8_t *)(0x427042ACUL))
#define bFM_MFS2_UART_FCR_FLSTE                   *((volatile  uint8_t *)(0x427042B0UL))
#define bFM4_MFS2_UART_FCR_FLSTE                  *((volatile  uint8_t *)(0x427042B0UL))

#define bFM_MFS2_UART_SCR_TXE                     *((volatile  uint8_t *)(0x42704020UL))
#define bFM4_MFS2_UART_SCR_TXE                    *((volatile  uint8_t *)(0x42704020UL))
#define bFM_MFS2_UART_SCR_RXE                     *((volatile  uint8_t *)(0x42704024UL))
#define bFM4_MFS2_UART_SCR_RXE                    *((volatile  uint8_t *)(0x42704024UL))
#define bFM_MFS2_UART_SCR_TBIE                    *((volatile  uint8_t *)(0x42704028UL))
#define bFM4_MFS2_UART_SCR_TBIE                   *((volatile  uint8_t *)(0x42704028UL))
#define bFM_MFS2_UART_SCR_TIE                     *((volatile  uint8_t *)(0x4270402CUL))
#define bFM4_MFS2_UART_SCR_TIE                    *((volatile  uint8_t *)(0x4270402CUL))
#define bFM_MFS2_UART_SCR_RIE                     *((volatile  uint8_t *)(0x42704030UL))
#define bFM4_MFS2_UART_SCR_RIE                    *((volatile  uint8_t *)(0x42704030UL))
#define bFM_MFS2_UART_SCR_UPCL                    *((volatile  uint8_t *)(0x4270403CUL))
#define bFM4_MFS2_UART_SCR_UPCL                   *((volatile  uint8_t *)(0x4270403CUL))

#define bFM_MFS2_UART_SMR_SOE                     *((volatile  uint8_t *)(0x42704000UL))
#define bFM4_MFS2_UART_SMR_SOE                    *((volatile  uint8_t *)(0x42704000UL))
#define bFM_MFS2_UART_SMR_BDS                     *((volatile  uint8_t *)(0x42704008UL))
#define bFM4_MFS2_UART_SMR_BDS                    *((volatile  uint8_t *)(0x42704008UL))
#define bFM_MFS2_UART_SMR_SBL                     *((volatile  uint8_t *)(0x4270400CUL))
#define bFM4_MFS2_UART_SMR_SBL                    *((volatile  uint8_t *)(0x4270400CUL))

#define bFM_MFS2_UART_SSR_TBI                     *((volatile  uint8_t *)(0x427040A0UL))
#define bFM4_MFS2_UART_SSR_TBI                    *((volatile  uint8_t *)(0x427040A0UL))
#define bFM_MFS2_UART_SSR_TDRE                    *((volatile  uint8_t *)(0x427040A4UL))
#define bFM4_MFS2_UART_SSR_TDRE                   *((volatile  uint8_t *)(0x427040A4UL))
#define bFM_MFS2_UART_SSR_RDRF                    *((volatile  uint8_t *)(0x427040A8UL))
#define bFM4_MFS2_UART_SSR_RDRF                   *((volatile  uint8_t *)(0x427040A8UL))
#define bFM_MFS2_UART_SSR_ORE                     *((volatile  uint8_t *)(0x427040ACUL))
#define bFM4_MFS2_UART_SSR_ORE                    *((volatile  uint8_t *)(0x427040ACUL))
#define bFM_MFS2_UART_SSR_FRE                     *((volatile  uint8_t *)(0x427040B0UL))
#define bFM4_MFS2_UART_SSR_FRE                    *((volatile  uint8_t *)(0x427040B0UL))
#define bFM_MFS2_UART_SSR_PE                      *((volatile  uint8_t *)(0x427040B4UL))
#define bFM4_MFS2_UART_SSR_PE                     *((volatile  uint8_t *)(0x427040B4UL))
#define bFM_MFS2_UART_SSR_REC                     *((volatile  uint8_t *)(0x427040BCUL))
#define bFM4_MFS2_UART_SSR_REC                    *((volatile  uint8_t *)(0x427040BCUL))


/*******************************************************************************
* MFS Registers MFS3
*   Bitband Section
*******************************************************************************/
#define bFM_MFS3_CSIO_ESCR_CSFE                   *((volatile  uint8_t *)(0x42706094UL))
#define bFM4_MFS3_CSIO_ESCR_CSFE                  *((volatile  uint8_t *)(0x42706094UL))
#define bFM_MFS3_CSIO_ESCR_L3                     *((volatile  uint8_t *)(0x42706098UL))
#define bFM4_MFS3_CSIO_ESCR_L3                    *((volatile  uint8_t *)(0x42706098UL))
#define bFM_MFS3_CSIO_ESCR_SOP                    *((volatile  uint8_t *)(0x4270609CUL))
#define bFM4_MFS3_CSIO_ESCR_SOP                   *((volatile  uint8_t *)(0x4270609CUL))

#define bFM_MFS3_CSIO_FCR_FE1                     *((volatile  uint8_t *)(0x42706280UL))
#define bFM4_MFS3_CSIO_FCR_FE1                    *((volatile  uint8_t *)(0x42706280UL))
#define bFM_MFS3_CSIO_FCR_FE2                     *((volatile  uint8_t *)(0x42706284UL))
#define bFM4_MFS3_CSIO_FCR_FE2                    *((volatile  uint8_t *)(0x42706284UL))
#define bFM_MFS3_CSIO_FCR_FCL1                    *((volatile  uint8_t *)(0x42706288UL))
#define bFM4_MFS3_CSIO_FCR_FCL1                   *((volatile  uint8_t *)(0x42706288UL))
#define bFM_MFS3_CSIO_FCR_FCL2                    *((volatile  uint8_t *)(0x4270628CUL))
#define bFM4_MFS3_CSIO_FCR_FCL2                   *((volatile  uint8_t *)(0x4270628CUL))
#define bFM_MFS3_CSIO_FCR_FSET                    *((volatile  uint8_t *)(0x42706290UL))
#define bFM4_MFS3_CSIO_FCR_FSET                   *((volatile  uint8_t *)(0x42706290UL))
#define bFM_MFS3_CSIO_FCR_FLD                     *((volatile  uint8_t *)(0x42706294UL))
#define bFM4_MFS3_CSIO_FCR_FLD                    *((volatile  uint8_t *)(0x42706294UL))
#define bFM_MFS3_CSIO_FCR_FLST                    *((volatile  uint8_t *)(0x42706298UL))
#define bFM4_MFS3_CSIO_FCR_FLST                   *((volatile  uint8_t *)(0x42706298UL))
#define bFM_MFS3_CSIO_FCR_FSEL                    *((volatile  uint8_t *)(0x427062A0UL))
#define bFM4_MFS3_CSIO_FCR_FSEL                   *((volatile  uint8_t *)(0x427062A0UL))
#define bFM_MFS3_CSIO_FCR_FTIE                    *((volatile  uint8_t *)(0x427062A4UL))
#define bFM4_MFS3_CSIO_FCR_FTIE                   *((volatile  uint8_t *)(0x427062A4UL))
#define bFM_MFS3_CSIO_FCR_FDRQ                    *((volatile  uint8_t *)(0x427062A8UL))
#define bFM4_MFS3_CSIO_FCR_FDRQ                   *((volatile  uint8_t *)(0x427062A8UL))
#define bFM_MFS3_CSIO_FCR_FRIIE                   *((volatile  uint8_t *)(0x427062ACUL))
#define bFM4_MFS3_CSIO_FCR_FRIIE                  *((volatile  uint8_t *)(0x427062ACUL))
#define bFM_MFS3_CSIO_FCR_FLSTE                   *((volatile  uint8_t *)(0x427062B0UL))
#define bFM4_MFS3_CSIO_FCR_FLSTE                  *((volatile  uint8_t *)(0x427062B0UL))

#define bFM_MFS3_CSIO_SACSR_TMRE                  *((volatile  uint8_t *)(0x42706480UL))
#define bFM4_MFS3_CSIO_SACSR_TMRE                 *((volatile  uint8_t *)(0x42706480UL))
#define bFM_MFS3_CSIO_SACSR_TSYNE                 *((volatile  uint8_t *)(0x42706498UL))
#define bFM4_MFS3_CSIO_SACSR_TSYNE                *((volatile  uint8_t *)(0x42706498UL))
#define bFM_MFS3_CSIO_SACSR_TINTE                 *((volatile  uint8_t *)(0x4270649CUL))
#define bFM4_MFS3_CSIO_SACSR_TINTE                *((volatile  uint8_t *)(0x4270649CUL))
#define bFM_MFS3_CSIO_SACSR_TINT                  *((volatile  uint8_t *)(0x427064A0UL))
#define bFM4_MFS3_CSIO_SACSR_TINT                 *((volatile  uint8_t *)(0x427064A0UL))
#define bFM_MFS3_CSIO_SACSR_CSE                   *((volatile  uint8_t *)(0x427064ACUL))
#define bFM4_MFS3_CSIO_SACSR_CSE                  *((volatile  uint8_t *)(0x427064ACUL))
#define bFM_MFS3_CSIO_SACSR_CSEIE                 *((volatile  uint8_t *)(0x427064B0UL))
#define bFM4_MFS3_CSIO_SACSR_CSEIE                *((volatile  uint8_t *)(0x427064B0UL))
#define bFM_MFS3_CSIO_SACSR_TBEEN                 *((volatile  uint8_t *)(0x427064B4UL))
#define bFM4_MFS3_CSIO_SACSR_TBEEN                *((volatile  uint8_t *)(0x427064B4UL))

#define bFM_MFS3_CSIO_SCR_TXE                     *((volatile  uint8_t *)(0x42706020UL))
#define bFM4_MFS3_CSIO_SCR_TXE                    *((volatile  uint8_t *)(0x42706020UL))
#define bFM_MFS3_CSIO_SCR_RXE                     *((volatile  uint8_t *)(0x42706024UL))
#define bFM4_MFS3_CSIO_SCR_RXE                    *((volatile  uint8_t *)(0x42706024UL))
#define bFM_MFS3_CSIO_SCR_TBIE                    *((volatile  uint8_t *)(0x42706028UL))
#define bFM4_MFS3_CSIO_SCR_TBIE                   *((volatile  uint8_t *)(0x42706028UL))
#define bFM_MFS3_CSIO_SCR_TIE                     *((volatile  uint8_t *)(0x4270602CUL))
#define bFM4_MFS3_CSIO_SCR_TIE                    *((volatile  uint8_t *)(0x4270602CUL))
#define bFM_MFS3_CSIO_SCR_RIE                     *((volatile  uint8_t *)(0x42706030UL))
#define bFM4_MFS3_CSIO_SCR_RIE                    *((volatile  uint8_t *)(0x42706030UL))
#define bFM_MFS3_CSIO_SCR_SPI                     *((volatile  uint8_t *)(0x42706034UL))
#define bFM4_MFS3_CSIO_SCR_SPI                    *((volatile  uint8_t *)(0x42706034UL))
#define bFM_MFS3_CSIO_SCR_MS                      *((volatile  uint8_t *)(0x42706038UL))
#define bFM4_MFS3_CSIO_SCR_MS                     *((volatile  uint8_t *)(0x42706038UL))
#define bFM_MFS3_CSIO_SCR_UPCL                    *((volatile  uint8_t *)(0x4270603CUL))
#define bFM4_MFS3_CSIO_SCR_UPCL                   *((volatile  uint8_t *)(0x4270603CUL))

#define bFM_MFS3_CSIO_SCSCR_CSOE                  *((volatile  uint8_t *)(0x42706600UL))
#define bFM4_MFS3_CSIO_SCSCR_CSOE                 *((volatile  uint8_t *)(0x42706600UL))
#define bFM_MFS3_CSIO_SCSCR_CSEN0                 *((volatile  uint8_t *)(0x42706604UL))
#define bFM4_MFS3_CSIO_SCSCR_CSEN0                *((volatile  uint8_t *)(0x42706604UL))
#define bFM_MFS3_CSIO_SCSCR_CSEN1                 *((volatile  uint8_t *)(0x42706608UL))
#define bFM4_MFS3_CSIO_SCSCR_CSEN1                *((volatile  uint8_t *)(0x42706608UL))
#define bFM_MFS3_CSIO_SCSCR_CSEN2                 *((volatile  uint8_t *)(0x4270660CUL))
#define bFM4_MFS3_CSIO_SCSCR_CSEN2                *((volatile  uint8_t *)(0x4270660CUL))
#define bFM_MFS3_CSIO_SCSCR_CSEN3                 *((volatile  uint8_t *)(0x42706610UL))
#define bFM4_MFS3_CSIO_SCSCR_CSEN3                *((volatile  uint8_t *)(0x42706610UL))
#define bFM_MFS3_CSIO_SCSCR_CSLVL                 *((volatile  uint8_t *)(0x42706614UL))
#define bFM4_MFS3_CSIO_SCSCR_CSLVL                *((volatile  uint8_t *)(0x42706614UL))
#define bFM_MFS3_CSIO_SCSCR_SCAM                  *((volatile  uint8_t *)(0x42706624UL))
#define bFM4_MFS3_CSIO_SCSCR_SCAM                 *((volatile  uint8_t *)(0x42706624UL))

#define bFM_MFS3_CSIO_SCSFR0_CS1SPI               *((volatile  uint8_t *)(0x42706694UL))
#define bFM4_MFS3_CSIO_SCSFR0_CS1SPI              *((volatile  uint8_t *)(0x42706694UL))
#define bFM_MFS3_CSIO_SCSFR0_CS1SCINV             *((volatile  uint8_t *)(0x42706698UL))
#define bFM4_MFS3_CSIO_SCSFR0_CS1SCINV            *((volatile  uint8_t *)(0x42706698UL))
#define bFM_MFS3_CSIO_SCSFR0_CS1CSLVL             *((volatile  uint8_t *)(0x4270669CUL))
#define bFM4_MFS3_CSIO_SCSFR0_CS1CSLVL            *((volatile  uint8_t *)(0x4270669CUL))

#define bFM_MFS3_CSIO_SCSFR1_CS2SPI               *((volatile  uint8_t *)(0x427066B4UL))
#define bFM4_MFS3_CSIO_SCSFR1_CS2SPI              *((volatile  uint8_t *)(0x427066B4UL))
#define bFM_MFS3_CSIO_SCSFR1_CS2SCINV             *((volatile  uint8_t *)(0x427066B8UL))
#define bFM4_MFS3_CSIO_SCSFR1_CS2SCINV            *((volatile  uint8_t *)(0x427066B8UL))
#define bFM_MFS3_CSIO_SCSFR1_CS2CSLVL             *((volatile  uint8_t *)(0x427066BCUL))
#define bFM4_MFS3_CSIO_SCSFR1_CS2CSLVL            *((volatile  uint8_t *)(0x427066BCUL))

#define bFM_MFS3_CSIO_SCSFR2_CS3SPI               *((volatile  uint8_t *)(0x42706714UL))
#define bFM4_MFS3_CSIO_SCSFR2_CS3SPI              *((volatile  uint8_t *)(0x42706714UL))
#define bFM_MFS3_CSIO_SCSFR2_CS3SCINV             *((volatile  uint8_t *)(0x42706718UL))
#define bFM4_MFS3_CSIO_SCSFR2_CS3SCINV            *((volatile  uint8_t *)(0x42706718UL))
#define bFM_MFS3_CSIO_SCSFR2_CS3CSLVL             *((volatile  uint8_t *)(0x4270671CUL))
#define bFM4_MFS3_CSIO_SCSFR2_CS3CSLVL            *((volatile  uint8_t *)(0x4270671CUL))

#define bFM_MFS3_CSIO_SMR_SOE                     *((volatile  uint8_t *)(0x42706000UL))
#define bFM4_MFS3_CSIO_SMR_SOE                    *((volatile  uint8_t *)(0x42706000UL))
#define bFM_MFS3_CSIO_SMR_SCKE                    *((volatile  uint8_t *)(0x42706004UL))
#define bFM4_MFS3_CSIO_SMR_SCKE                   *((volatile  uint8_t *)(0x42706004UL))
#define bFM_MFS3_CSIO_SMR_BDS                     *((volatile  uint8_t *)(0x42706008UL))
#define bFM4_MFS3_CSIO_SMR_BDS                    *((volatile  uint8_t *)(0x42706008UL))
#define bFM_MFS3_CSIO_SMR_SCINV                   *((volatile  uint8_t *)(0x4270600CUL))
#define bFM4_MFS3_CSIO_SMR_SCINV                  *((volatile  uint8_t *)(0x4270600CUL))

#define bFM_MFS3_CSIO_SSR_TBI                     *((volatile  uint8_t *)(0x427060A0UL))
#define bFM4_MFS3_CSIO_SSR_TBI                    *((volatile  uint8_t *)(0x427060A0UL))
#define bFM_MFS3_CSIO_SSR_TDRE                    *((volatile  uint8_t *)(0x427060A4UL))
#define bFM4_MFS3_CSIO_SSR_TDRE                   *((volatile  uint8_t *)(0x427060A4UL))
#define bFM_MFS3_CSIO_SSR_RDRF                    *((volatile  uint8_t *)(0x427060A8UL))
#define bFM4_MFS3_CSIO_SSR_RDRF                   *((volatile  uint8_t *)(0x427060A8UL))
#define bFM_MFS3_CSIO_SSR_ORE                     *((volatile  uint8_t *)(0x427060ACUL))
#define bFM4_MFS3_CSIO_SSR_ORE                    *((volatile  uint8_t *)(0x427060ACUL))
#define bFM_MFS3_CSIO_SSR_AWC                     *((volatile  uint8_t *)(0x427060B0UL))
#define bFM4_MFS3_CSIO_SSR_AWC                    *((volatile  uint8_t *)(0x427060B0UL))
#define bFM_MFS3_CSIO_SSR_REC                     *((volatile  uint8_t *)(0x427060BCUL))
#define bFM4_MFS3_CSIO_SSR_REC                    *((volatile  uint8_t *)(0x427060BCUL))

#define bFM_MFS3_I2C_EIBCR_BEC                    *((volatile  uint8_t *)(0x427063A0UL))
#define bFM4_MFS3_I2C_EIBCR_BEC                   *((volatile  uint8_t *)(0x427063A0UL))
#define bFM_MFS3_I2C_EIBCR_SOCE                   *((volatile  uint8_t *)(0x427063A4UL))
#define bFM4_MFS3_I2C_EIBCR_SOCE                  *((volatile  uint8_t *)(0x427063A4UL))
#define bFM_MFS3_I2C_EIBCR_SCLC                   *((volatile  uint8_t *)(0x427063A8UL))
#define bFM4_MFS3_I2C_EIBCR_SCLC                  *((volatile  uint8_t *)(0x427063A8UL))
#define bFM_MFS3_I2C_EIBCR_SDAC                   *((volatile  uint8_t *)(0x427063ACUL))
#define bFM4_MFS3_I2C_EIBCR_SDAC                  *((volatile  uint8_t *)(0x427063ACUL))
#define bFM_MFS3_I2C_EIBCR_SCLS                   *((volatile  uint8_t *)(0x427063B0UL))
#define bFM4_MFS3_I2C_EIBCR_SCLS                  *((volatile  uint8_t *)(0x427063B0UL))
#define bFM_MFS3_I2C_EIBCR_SDAS                   *((volatile  uint8_t *)(0x427063B4UL))
#define bFM4_MFS3_I2C_EIBCR_SDAS                  *((volatile  uint8_t *)(0x427063B4UL))

#define bFM_MFS3_I2C_FCR_FE1                      *((volatile  uint8_t *)(0x42706280UL))
#define bFM4_MFS3_I2C_FCR_FE1                     *((volatile  uint8_t *)(0x42706280UL))
#define bFM_MFS3_I2C_FCR_FE2                      *((volatile  uint8_t *)(0x42706284UL))
#define bFM4_MFS3_I2C_FCR_FE2                     *((volatile  uint8_t *)(0x42706284UL))
#define bFM_MFS3_I2C_FCR_FCL1                     *((volatile  uint8_t *)(0x42706288UL))
#define bFM4_MFS3_I2C_FCR_FCL1                    *((volatile  uint8_t *)(0x42706288UL))
#define bFM_MFS3_I2C_FCR_FCL2                     *((volatile  uint8_t *)(0x4270628CUL))
#define bFM4_MFS3_I2C_FCR_FCL2                    *((volatile  uint8_t *)(0x4270628CUL))
#define bFM_MFS3_I2C_FCR_FSET                     *((volatile  uint8_t *)(0x42706290UL))
#define bFM4_MFS3_I2C_FCR_FSET                    *((volatile  uint8_t *)(0x42706290UL))
#define bFM_MFS3_I2C_FCR_FLD                      *((volatile  uint8_t *)(0x42706294UL))
#define bFM4_MFS3_I2C_FCR_FLD                     *((volatile  uint8_t *)(0x42706294UL))
#define bFM_MFS3_I2C_FCR_FLST                     *((volatile  uint8_t *)(0x42706298UL))
#define bFM4_MFS3_I2C_FCR_FLST                    *((volatile  uint8_t *)(0x42706298UL))
#define bFM_MFS3_I2C_FCR_FSEL                     *((volatile  uint8_t *)(0x427062A0UL))
#define bFM4_MFS3_I2C_FCR_FSEL                    *((volatile  uint8_t *)(0x427062A0UL))
#define bFM_MFS3_I2C_FCR_FTIE                     *((volatile  uint8_t *)(0x427062A4UL))
#define bFM4_MFS3_I2C_FCR_FTIE                    *((volatile  uint8_t *)(0x427062A4UL))
#define bFM_MFS3_I2C_FCR_FDRQ                     *((volatile  uint8_t *)(0x427062A8UL))
#define bFM4_MFS3_I2C_FCR_FDRQ                    *((volatile  uint8_t *)(0x427062A8UL))
#define bFM_MFS3_I2C_FCR_FRIIE                    *((volatile  uint8_t *)(0x427062ACUL))
#define bFM4_MFS3_I2C_FCR_FRIIE                   *((volatile  uint8_t *)(0x427062ACUL))
#define bFM_MFS3_I2C_FCR_FLSTE                    *((volatile  uint8_t *)(0x427062B0UL))
#define bFM4_MFS3_I2C_FCR_FLSTE                   *((volatile  uint8_t *)(0x427062B0UL))

#define bFM_MFS3_I2C_IBCR_INT                     *((volatile  uint8_t *)(0x42706020UL))
#define bFM4_MFS3_I2C_IBCR_INT                    *((volatile  uint8_t *)(0x42706020UL))
#define bFM_MFS3_I2C_IBCR_BER                     *((volatile  uint8_t *)(0x42706024UL))
#define bFM4_MFS3_I2C_IBCR_BER                    *((volatile  uint8_t *)(0x42706024UL))
#define bFM_MFS3_I2C_IBCR_INTE                    *((volatile  uint8_t *)(0x42706028UL))
#define bFM4_MFS3_I2C_IBCR_INTE                   *((volatile  uint8_t *)(0x42706028UL))
#define bFM_MFS3_I2C_IBCR_CNDE                    *((volatile  uint8_t *)(0x4270602CUL))
#define bFM4_MFS3_I2C_IBCR_CNDE                   *((volatile  uint8_t *)(0x4270602CUL))
#define bFM_MFS3_I2C_IBCR_WSEL                    *((volatile  uint8_t *)(0x42706030UL))
#define bFM4_MFS3_I2C_IBCR_WSEL                   *((volatile  uint8_t *)(0x42706030UL))
#define bFM_MFS3_I2C_IBCR_ACKE                    *((volatile  uint8_t *)(0x42706034UL))
#define bFM4_MFS3_I2C_IBCR_ACKE                   *((volatile  uint8_t *)(0x42706034UL))
#define bFM_MFS3_I2C_IBCR_ACT_SCC                 *((volatile  uint8_t *)(0x42706038UL))
#define bFM4_MFS3_I2C_IBCR_ACT_SCC                *((volatile  uint8_t *)(0x42706038UL))
#define bFM_MFS3_I2C_IBCR_MSS                     *((volatile  uint8_t *)(0x4270603CUL))
#define bFM4_MFS3_I2C_IBCR_MSS                    *((volatile  uint8_t *)(0x4270603CUL))

#define bFM_MFS3_I2C_IBSR_BB                      *((volatile  uint8_t *)(0x42706080UL))
#define bFM4_MFS3_I2C_IBSR_BB                     *((volatile  uint8_t *)(0x42706080UL))
#define bFM_MFS3_I2C_IBSR_SPC                     *((volatile  uint8_t *)(0x42706084UL))
#define bFM4_MFS3_I2C_IBSR_SPC                    *((volatile  uint8_t *)(0x42706084UL))
#define bFM_MFS3_I2C_IBSR_RSC                     *((volatile  uint8_t *)(0x42706088UL))
#define bFM4_MFS3_I2C_IBSR_RSC                    *((volatile  uint8_t *)(0x42706088UL))
#define bFM_MFS3_I2C_IBSR_AL                      *((volatile  uint8_t *)(0x4270608CUL))
#define bFM4_MFS3_I2C_IBSR_AL                     *((volatile  uint8_t *)(0x4270608CUL))
#define bFM_MFS3_I2C_IBSR_TRX                     *((volatile  uint8_t *)(0x42706090UL))
#define bFM4_MFS3_I2C_IBSR_TRX                    *((volatile  uint8_t *)(0x42706090UL))
#define bFM_MFS3_I2C_IBSR_RSA                     *((volatile  uint8_t *)(0x42706094UL))
#define bFM4_MFS3_I2C_IBSR_RSA                    *((volatile  uint8_t *)(0x42706094UL))
#define bFM_MFS3_I2C_IBSR_RACK                    *((volatile  uint8_t *)(0x42706098UL))
#define bFM4_MFS3_I2C_IBSR_RACK                   *((volatile  uint8_t *)(0x42706098UL))
#define bFM_MFS3_I2C_IBSR_FBT                     *((volatile  uint8_t *)(0x4270609CUL))
#define bFM4_MFS3_I2C_IBSR_FBT                    *((volatile  uint8_t *)(0x4270609CUL))

#define bFM_MFS3_I2C_ISBA_SAEN                    *((volatile  uint8_t *)(0x4270621CUL))
#define bFM4_MFS3_I2C_ISBA_SAEN                   *((volatile  uint8_t *)(0x4270621CUL))

#define bFM_MFS3_I2C_ISMK_EN                      *((volatile  uint8_t *)(0x4270623CUL))
#define bFM4_MFS3_I2C_ISMK_EN                     *((volatile  uint8_t *)(0x4270623CUL))

#define bFM_MFS3_I2C_SMR_TIE                      *((volatile  uint8_t *)(0x42706008UL))
#define bFM4_MFS3_I2C_SMR_TIE                     *((volatile  uint8_t *)(0x42706008UL))
#define bFM_MFS3_I2C_SMR_RIE                      *((volatile  uint8_t *)(0x4270600CUL))
#define bFM4_MFS3_I2C_SMR_RIE                     *((volatile  uint8_t *)(0x4270600CUL))

#define bFM_MFS3_I2C_SSR_TBI                      *((volatile  uint8_t *)(0x427060A0UL))
#define bFM4_MFS3_I2C_SSR_TBI                     *((volatile  uint8_t *)(0x427060A0UL))
#define bFM_MFS3_I2C_SSR_TDRE                     *((volatile  uint8_t *)(0x427060A4UL))
#define bFM4_MFS3_I2C_SSR_TDRE                    *((volatile  uint8_t *)(0x427060A4UL))
#define bFM_MFS3_I2C_SSR_RDRF                     *((volatile  uint8_t *)(0x427060A8UL))
#define bFM4_MFS3_I2C_SSR_RDRF                    *((volatile  uint8_t *)(0x427060A8UL))
#define bFM_MFS3_I2C_SSR_ORE                      *((volatile  uint8_t *)(0x427060ACUL))
#define bFM4_MFS3_I2C_SSR_ORE                     *((volatile  uint8_t *)(0x427060ACUL))
#define bFM_MFS3_I2C_SSR_TBIE                     *((volatile  uint8_t *)(0x427060B0UL))
#define bFM4_MFS3_I2C_SSR_TBIE                    *((volatile  uint8_t *)(0x427060B0UL))
#define bFM_MFS3_I2C_SSR_DMA                      *((volatile  uint8_t *)(0x427060B4UL))
#define bFM4_MFS3_I2C_SSR_DMA                     *((volatile  uint8_t *)(0x427060B4UL))
#define bFM_MFS3_I2C_SSR_TSET                     *((volatile  uint8_t *)(0x427060B8UL))
#define bFM4_MFS3_I2C_SSR_TSET                    *((volatile  uint8_t *)(0x427060B8UL))
#define bFM_MFS3_I2C_SSR_REC                      *((volatile  uint8_t *)(0x427060BCUL))
#define bFM4_MFS3_I2C_SSR_REC                     *((volatile  uint8_t *)(0x427060BCUL))

#define bFM_MFS3_LIN_BGR_EXT                      *((volatile  uint8_t *)(0x427061BCUL))
#define bFM4_MFS3_LIN_BGR_EXT                     *((volatile  uint8_t *)(0x427061BCUL))

#define bFM_MFS3_LIN_ESCR_LBIE                    *((volatile  uint8_t *)(0x42706090UL))
#define bFM4_MFS3_LIN_ESCR_LBIE                   *((volatile  uint8_t *)(0x42706090UL))
#define bFM_MFS3_LIN_ESCR_ESBL                    *((volatile  uint8_t *)(0x42706098UL))
#define bFM4_MFS3_LIN_ESCR_ESBL                   *((volatile  uint8_t *)(0x42706098UL))

#define bFM_MFS3_LIN_FCR_FE1                      *((volatile  uint8_t *)(0x42706280UL))
#define bFM4_MFS3_LIN_FCR_FE1                     *((volatile  uint8_t *)(0x42706280UL))
#define bFM_MFS3_LIN_FCR_FE2                      *((volatile  uint8_t *)(0x42706284UL))
#define bFM4_MFS3_LIN_FCR_FE2                     *((volatile  uint8_t *)(0x42706284UL))
#define bFM_MFS3_LIN_FCR_FCL1                     *((volatile  uint8_t *)(0x42706288UL))
#define bFM4_MFS3_LIN_FCR_FCL1                    *((volatile  uint8_t *)(0x42706288UL))
#define bFM_MFS3_LIN_FCR_FCL2                     *((volatile  uint8_t *)(0x4270628CUL))
#define bFM4_MFS3_LIN_FCR_FCL2                    *((volatile  uint8_t *)(0x4270628CUL))
#define bFM_MFS3_LIN_FCR_FSET                     *((volatile  uint8_t *)(0x42706290UL))
#define bFM4_MFS3_LIN_FCR_FSET                    *((volatile  uint8_t *)(0x42706290UL))
#define bFM_MFS3_LIN_FCR_FLD                      *((volatile  uint8_t *)(0x42706294UL))
#define bFM4_MFS3_LIN_FCR_FLD                     *((volatile  uint8_t *)(0x42706294UL))
#define bFM_MFS3_LIN_FCR_FLST                     *((volatile  uint8_t *)(0x42706298UL))
#define bFM4_MFS3_LIN_FCR_FLST                    *((volatile  uint8_t *)(0x42706298UL))
#define bFM_MFS3_LIN_FCR_FSEL                     *((volatile  uint8_t *)(0x427062A0UL))
#define bFM4_MFS3_LIN_FCR_FSEL                    *((volatile  uint8_t *)(0x427062A0UL))
#define bFM_MFS3_LIN_FCR_FTIE                     *((volatile  uint8_t *)(0x427062A4UL))
#define bFM4_MFS3_LIN_FCR_FTIE                    *((volatile  uint8_t *)(0x427062A4UL))
#define bFM_MFS3_LIN_FCR_FDRQ                     *((volatile  uint8_t *)(0x427062A8UL))
#define bFM4_MFS3_LIN_FCR_FDRQ                    *((volatile  uint8_t *)(0x427062A8UL))
#define bFM_MFS3_LIN_FCR_FRIIE                    *((volatile  uint8_t *)(0x427062ACUL))
#define bFM4_MFS3_LIN_FCR_FRIIE                   *((volatile  uint8_t *)(0x427062ACUL))
#define bFM_MFS3_LIN_FCR_FLSTE                    *((volatile  uint8_t *)(0x427062B0UL))
#define bFM4_MFS3_LIN_FCR_FLSTE                   *((volatile  uint8_t *)(0x427062B0UL))

#define bFM_MFS3_LIN_SCR_TXE                      *((volatile  uint8_t *)(0x42706020UL))
#define bFM4_MFS3_LIN_SCR_TXE                     *((volatile  uint8_t *)(0x42706020UL))
#define bFM_MFS3_LIN_SCR_RXE                      *((volatile  uint8_t *)(0x42706024UL))
#define bFM4_MFS3_LIN_SCR_RXE                     *((volatile  uint8_t *)(0x42706024UL))
#define bFM_MFS3_LIN_SCR_TBIE                     *((volatile  uint8_t *)(0x42706028UL))
#define bFM4_MFS3_LIN_SCR_TBIE                    *((volatile  uint8_t *)(0x42706028UL))
#define bFM_MFS3_LIN_SCR_TIE                      *((volatile  uint8_t *)(0x4270602CUL))
#define bFM4_MFS3_LIN_SCR_TIE                     *((volatile  uint8_t *)(0x4270602CUL))
#define bFM_MFS3_LIN_SCR_RIE                      *((volatile  uint8_t *)(0x42706030UL))
#define bFM4_MFS3_LIN_SCR_RIE                     *((volatile  uint8_t *)(0x42706030UL))
#define bFM_MFS3_LIN_SCR_LBR                      *((volatile  uint8_t *)(0x42706034UL))
#define bFM4_MFS3_LIN_SCR_LBR                     *((volatile  uint8_t *)(0x42706034UL))
#define bFM_MFS3_LIN_SCR_MS                       *((volatile  uint8_t *)(0x42706038UL))
#define bFM4_MFS3_LIN_SCR_MS                      *((volatile  uint8_t *)(0x42706038UL))
#define bFM_MFS3_LIN_SCR_UPCL                     *((volatile  uint8_t *)(0x4270603CUL))
#define bFM4_MFS3_LIN_SCR_UPCL                    *((volatile  uint8_t *)(0x4270603CUL))

#define bFM_MFS3_LIN_SMR_SOE                      *((volatile  uint8_t *)(0x42706000UL))
#define bFM4_MFS3_LIN_SMR_SOE                     *((volatile  uint8_t *)(0x42706000UL))
#define bFM_MFS3_LIN_SMR_SBL                      *((volatile  uint8_t *)(0x4270600CUL))
#define bFM4_MFS3_LIN_SMR_SBL                     *((volatile  uint8_t *)(0x4270600CUL))
#define bFM_MFS3_LIN_SMR_WUCR                     *((volatile  uint8_t *)(0x42706010UL))
#define bFM4_MFS3_LIN_SMR_WUCR                    *((volatile  uint8_t *)(0x42706010UL))

#define bFM_MFS3_LIN_SSR_TBI                      *((volatile  uint8_t *)(0x427060A0UL))
#define bFM4_MFS3_LIN_SSR_TBI                     *((volatile  uint8_t *)(0x427060A0UL))
#define bFM_MFS3_LIN_SSR_TDRE                     *((volatile  uint8_t *)(0x427060A4UL))
#define bFM4_MFS3_LIN_SSR_TDRE                    *((volatile  uint8_t *)(0x427060A4UL))
#define bFM_MFS3_LIN_SSR_RDRF                     *((volatile  uint8_t *)(0x427060A8UL))
#define bFM4_MFS3_LIN_SSR_RDRF                    *((volatile  uint8_t *)(0x427060A8UL))
#define bFM_MFS3_LIN_SSR_ORE                      *((volatile  uint8_t *)(0x427060ACUL))
#define bFM4_MFS3_LIN_SSR_ORE                     *((volatile  uint8_t *)(0x427060ACUL))
#define bFM_MFS3_LIN_SSR_FRE                      *((volatile  uint8_t *)(0x427060B0UL))
#define bFM4_MFS3_LIN_SSR_FRE                     *((volatile  uint8_t *)(0x427060B0UL))
#define bFM_MFS3_LIN_SSR_LBD                      *((volatile  uint8_t *)(0x427060B4UL))
#define bFM4_MFS3_LIN_SSR_LBD                     *((volatile  uint8_t *)(0x427060B4UL))
#define bFM_MFS3_LIN_SSR_REC                      *((volatile  uint8_t *)(0x427060BCUL))
#define bFM4_MFS3_LIN_SSR_REC                     *((volatile  uint8_t *)(0x427060BCUL))

#define bFM_MFS3_UART_BGR_EXT                     *((volatile  uint8_t *)(0x427061BCUL))
#define bFM4_MFS3_UART_BGR_EXT                    *((volatile  uint8_t *)(0x427061BCUL))

#define bFM_MFS3_UART_ESCR_P                      *((volatile  uint8_t *)(0x4270608CUL))
#define bFM4_MFS3_UART_ESCR_P                     *((volatile  uint8_t *)(0x4270608CUL))
#define bFM_MFS3_UART_ESCR_PEN                    *((volatile  uint8_t *)(0x42706090UL))
#define bFM4_MFS3_UART_ESCR_PEN                   *((volatile  uint8_t *)(0x42706090UL))
#define bFM_MFS3_UART_ESCR_INV                    *((volatile  uint8_t *)(0x42706094UL))
#define bFM4_MFS3_UART_ESCR_INV                   *((volatile  uint8_t *)(0x42706094UL))
#define bFM_MFS3_UART_ESCR_ESBL                   *((volatile  uint8_t *)(0x42706098UL))
#define bFM4_MFS3_UART_ESCR_ESBL                  *((volatile  uint8_t *)(0x42706098UL))
#define bFM_MFS3_UART_ESCR_FLWEN                  *((volatile  uint8_t *)(0x4270609CUL))
#define bFM4_MFS3_UART_ESCR_FLWEN                 *((volatile  uint8_t *)(0x4270609CUL))

#define bFM_MFS3_UART_FCR_FE1                     *((volatile  uint8_t *)(0x42706280UL))
#define bFM4_MFS3_UART_FCR_FE1                    *((volatile  uint8_t *)(0x42706280UL))
#define bFM_MFS3_UART_FCR_FE2                     *((volatile  uint8_t *)(0x42706284UL))
#define bFM4_MFS3_UART_FCR_FE2                    *((volatile  uint8_t *)(0x42706284UL))
#define bFM_MFS3_UART_FCR_FCL1                    *((volatile  uint8_t *)(0x42706288UL))
#define bFM4_MFS3_UART_FCR_FCL1                   *((volatile  uint8_t *)(0x42706288UL))
#define bFM_MFS3_UART_FCR_FCL2                    *((volatile  uint8_t *)(0x4270628CUL))
#define bFM4_MFS3_UART_FCR_FCL2                   *((volatile  uint8_t *)(0x4270628CUL))
#define bFM_MFS3_UART_FCR_FSET                    *((volatile  uint8_t *)(0x42706290UL))
#define bFM4_MFS3_UART_FCR_FSET                   *((volatile  uint8_t *)(0x42706290UL))
#define bFM_MFS3_UART_FCR_FLD                     *((volatile  uint8_t *)(0x42706294UL))
#define bFM4_MFS3_UART_FCR_FLD                    *((volatile  uint8_t *)(0x42706294UL))
#define bFM_MFS3_UART_FCR_FLST                    *((volatile  uint8_t *)(0x42706298UL))
#define bFM4_MFS3_UART_FCR_FLST                   *((volatile  uint8_t *)(0x42706298UL))
#define bFM_MFS3_UART_FCR_FSEL                    *((volatile  uint8_t *)(0x427062A0UL))
#define bFM4_MFS3_UART_FCR_FSEL                   *((volatile  uint8_t *)(0x427062A0UL))
#define bFM_MFS3_UART_FCR_FTIE                    *((volatile  uint8_t *)(0x427062A4UL))
#define bFM4_MFS3_UART_FCR_FTIE                   *((volatile  uint8_t *)(0x427062A4UL))
#define bFM_MFS3_UART_FCR_FDRQ                    *((volatile  uint8_t *)(0x427062A8UL))
#define bFM4_MFS3_UART_FCR_FDRQ                   *((volatile  uint8_t *)(0x427062A8UL))
#define bFM_MFS3_UART_FCR_FRIIE                   *((volatile  uint8_t *)(0x427062ACUL))
#define bFM4_MFS3_UART_FCR_FRIIE                  *((volatile  uint8_t *)(0x427062ACUL))
#define bFM_MFS3_UART_FCR_FLSTE                   *((volatile  uint8_t *)(0x427062B0UL))
#define bFM4_MFS3_UART_FCR_FLSTE                  *((volatile  uint8_t *)(0x427062B0UL))

#define bFM_MFS3_UART_SCR_TXE                     *((volatile  uint8_t *)(0x42706020UL))
#define bFM4_MFS3_UART_SCR_TXE                    *((volatile  uint8_t *)(0x42706020UL))
#define bFM_MFS3_UART_SCR_RXE                     *((volatile  uint8_t *)(0x42706024UL))
#define bFM4_MFS3_UART_SCR_RXE                    *((volatile  uint8_t *)(0x42706024UL))
#define bFM_MFS3_UART_SCR_TBIE                    *((volatile  uint8_t *)(0x42706028UL))
#define bFM4_MFS3_UART_SCR_TBIE                   *((volatile  uint8_t *)(0x42706028UL))
#define bFM_MFS3_UART_SCR_TIE                     *((volatile  uint8_t *)(0x4270602CUL))
#define bFM4_MFS3_UART_SCR_TIE                    *((volatile  uint8_t *)(0x4270602CUL))
#define bFM_MFS3_UART_SCR_RIE                     *((volatile  uint8_t *)(0x42706030UL))
#define bFM4_MFS3_UART_SCR_RIE                    *((volatile  uint8_t *)(0x42706030UL))
#define bFM_MFS3_UART_SCR_UPCL                    *((volatile  uint8_t *)(0x4270603CUL))
#define bFM4_MFS3_UART_SCR_UPCL                   *((volatile  uint8_t *)(0x4270603CUL))

#define bFM_MFS3_UART_SMR_SOE                     *((volatile  uint8_t *)(0x42706000UL))
#define bFM4_MFS3_UART_SMR_SOE                    *((volatile  uint8_t *)(0x42706000UL))
#define bFM_MFS3_UART_SMR_BDS                     *((volatile  uint8_t *)(0x42706008UL))
#define bFM4_MFS3_UART_SMR_BDS                    *((volatile  uint8_t *)(0x42706008UL))
#define bFM_MFS3_UART_SMR_SBL                     *((volatile  uint8_t *)(0x4270600CUL))
#define bFM4_MFS3_UART_SMR_SBL                    *((volatile  uint8_t *)(0x4270600CUL))

#define bFM_MFS3_UART_SSR_TBI                     *((volatile  uint8_t *)(0x427060A0UL))
#define bFM4_MFS3_UART_SSR_TBI                    *((volatile  uint8_t *)(0x427060A0UL))
#define bFM_MFS3_UART_SSR_TDRE                    *((volatile  uint8_t *)(0x427060A4UL))
#define bFM4_MFS3_UART_SSR_TDRE                   *((volatile  uint8_t *)(0x427060A4UL))
#define bFM_MFS3_UART_SSR_RDRF                    *((volatile  uint8_t *)(0x427060A8UL))
#define bFM4_MFS3_UART_SSR_RDRF                   *((volatile  uint8_t *)(0x427060A8UL))
#define bFM_MFS3_UART_SSR_ORE                     *((volatile  uint8_t *)(0x427060ACUL))
#define bFM4_MFS3_UART_SSR_ORE                    *((volatile  uint8_t *)(0x427060ACUL))
#define bFM_MFS3_UART_SSR_FRE                     *((volatile  uint8_t *)(0x427060B0UL))
#define bFM4_MFS3_UART_SSR_FRE                    *((volatile  uint8_t *)(0x427060B0UL))
#define bFM_MFS3_UART_SSR_PE                      *((volatile  uint8_t *)(0x427060B4UL))
#define bFM4_MFS3_UART_SSR_PE                     *((volatile  uint8_t *)(0x427060B4UL))
#define bFM_MFS3_UART_SSR_REC                     *((volatile  uint8_t *)(0x427060BCUL))
#define bFM4_MFS3_UART_SSR_REC                    *((volatile  uint8_t *)(0x427060BCUL))


/*******************************************************************************
* MFS Registers MFS4
*   Bitband Section
*******************************************************************************/
#define bFM_MFS4_CSIO_ESCR_CSFE                   *((volatile  uint8_t *)(0x42708094UL))
#define bFM4_MFS4_CSIO_ESCR_CSFE                  *((volatile  uint8_t *)(0x42708094UL))
#define bFM_MFS4_CSIO_ESCR_L3                     *((volatile  uint8_t *)(0x42708098UL))
#define bFM4_MFS4_CSIO_ESCR_L3                    *((volatile  uint8_t *)(0x42708098UL))
#define bFM_MFS4_CSIO_ESCR_SOP                    *((volatile  uint8_t *)(0x4270809CUL))
#define bFM4_MFS4_CSIO_ESCR_SOP                   *((volatile  uint8_t *)(0x4270809CUL))

#define bFM_MFS4_CSIO_FCR_FE1                     *((volatile  uint8_t *)(0x42708280UL))
#define bFM4_MFS4_CSIO_FCR_FE1                    *((volatile  uint8_t *)(0x42708280UL))
#define bFM_MFS4_CSIO_FCR_FE2                     *((volatile  uint8_t *)(0x42708284UL))
#define bFM4_MFS4_CSIO_FCR_FE2                    *((volatile  uint8_t *)(0x42708284UL))
#define bFM_MFS4_CSIO_FCR_FCL1                    *((volatile  uint8_t *)(0x42708288UL))
#define bFM4_MFS4_CSIO_FCR_FCL1                   *((volatile  uint8_t *)(0x42708288UL))
#define bFM_MFS4_CSIO_FCR_FCL2                    *((volatile  uint8_t *)(0x4270828CUL))
#define bFM4_MFS4_CSIO_FCR_FCL2                   *((volatile  uint8_t *)(0x4270828CUL))
#define bFM_MFS4_CSIO_FCR_FSET                    *((volatile  uint8_t *)(0x42708290UL))
#define bFM4_MFS4_CSIO_FCR_FSET                   *((volatile  uint8_t *)(0x42708290UL))
#define bFM_MFS4_CSIO_FCR_FLD                     *((volatile  uint8_t *)(0x42708294UL))
#define bFM4_MFS4_CSIO_FCR_FLD                    *((volatile  uint8_t *)(0x42708294UL))
#define bFM_MFS4_CSIO_FCR_FLST                    *((volatile  uint8_t *)(0x42708298UL))
#define bFM4_MFS4_CSIO_FCR_FLST                   *((volatile  uint8_t *)(0x42708298UL))
#define bFM_MFS4_CSIO_FCR_FSEL                    *((volatile  uint8_t *)(0x427082A0UL))
#define bFM4_MFS4_CSIO_FCR_FSEL                   *((volatile  uint8_t *)(0x427082A0UL))
#define bFM_MFS4_CSIO_FCR_FTIE                    *((volatile  uint8_t *)(0x427082A4UL))
#define bFM4_MFS4_CSIO_FCR_FTIE                   *((volatile  uint8_t *)(0x427082A4UL))
#define bFM_MFS4_CSIO_FCR_FDRQ                    *((volatile  uint8_t *)(0x427082A8UL))
#define bFM4_MFS4_CSIO_FCR_FDRQ                   *((volatile  uint8_t *)(0x427082A8UL))
#define bFM_MFS4_CSIO_FCR_FRIIE                   *((volatile  uint8_t *)(0x427082ACUL))
#define bFM4_MFS4_CSIO_FCR_FRIIE                  *((volatile  uint8_t *)(0x427082ACUL))
#define bFM_MFS4_CSIO_FCR_FLSTE                   *((volatile  uint8_t *)(0x427082B0UL))
#define bFM4_MFS4_CSIO_FCR_FLSTE                  *((volatile  uint8_t *)(0x427082B0UL))

#define bFM_MFS4_CSIO_SACSR_TMRE                  *((volatile  uint8_t *)(0x42708480UL))
#define bFM4_MFS4_CSIO_SACSR_TMRE                 *((volatile  uint8_t *)(0x42708480UL))
#define bFM_MFS4_CSIO_SACSR_TSYNE                 *((volatile  uint8_t *)(0x42708498UL))
#define bFM4_MFS4_CSIO_SACSR_TSYNE                *((volatile  uint8_t *)(0x42708498UL))
#define bFM_MFS4_CSIO_SACSR_TINTE                 *((volatile  uint8_t *)(0x4270849CUL))
#define bFM4_MFS4_CSIO_SACSR_TINTE                *((volatile  uint8_t *)(0x4270849CUL))
#define bFM_MFS4_CSIO_SACSR_TINT                  *((volatile  uint8_t *)(0x427084A0UL))
#define bFM4_MFS4_CSIO_SACSR_TINT                 *((volatile  uint8_t *)(0x427084A0UL))
#define bFM_MFS4_CSIO_SACSR_CSE                   *((volatile  uint8_t *)(0x427084ACUL))
#define bFM4_MFS4_CSIO_SACSR_CSE                  *((volatile  uint8_t *)(0x427084ACUL))
#define bFM_MFS4_CSIO_SACSR_CSEIE                 *((volatile  uint8_t *)(0x427084B0UL))
#define bFM4_MFS4_CSIO_SACSR_CSEIE                *((volatile  uint8_t *)(0x427084B0UL))
#define bFM_MFS4_CSIO_SACSR_TBEEN                 *((volatile  uint8_t *)(0x427084B4UL))
#define bFM4_MFS4_CSIO_SACSR_TBEEN                *((volatile  uint8_t *)(0x427084B4UL))

#define bFM_MFS4_CSIO_SCR_TXE                     *((volatile  uint8_t *)(0x42708020UL))
#define bFM4_MFS4_CSIO_SCR_TXE                    *((volatile  uint8_t *)(0x42708020UL))
#define bFM_MFS4_CSIO_SCR_RXE                     *((volatile  uint8_t *)(0x42708024UL))
#define bFM4_MFS4_CSIO_SCR_RXE                    *((volatile  uint8_t *)(0x42708024UL))
#define bFM_MFS4_CSIO_SCR_TBIE                    *((volatile  uint8_t *)(0x42708028UL))
#define bFM4_MFS4_CSIO_SCR_TBIE                   *((volatile  uint8_t *)(0x42708028UL))
#define bFM_MFS4_CSIO_SCR_TIE                     *((volatile  uint8_t *)(0x4270802CUL))
#define bFM4_MFS4_CSIO_SCR_TIE                    *((volatile  uint8_t *)(0x4270802CUL))
#define bFM_MFS4_CSIO_SCR_RIE                     *((volatile  uint8_t *)(0x42708030UL))
#define bFM4_MFS4_CSIO_SCR_RIE                    *((volatile  uint8_t *)(0x42708030UL))
#define bFM_MFS4_CSIO_SCR_SPI                     *((volatile  uint8_t *)(0x42708034UL))
#define bFM4_MFS4_CSIO_SCR_SPI                    *((volatile  uint8_t *)(0x42708034UL))
#define bFM_MFS4_CSIO_SCR_MS                      *((volatile  uint8_t *)(0x42708038UL))
#define bFM4_MFS4_CSIO_SCR_MS                     *((volatile  uint8_t *)(0x42708038UL))
#define bFM_MFS4_CSIO_SCR_UPCL                    *((volatile  uint8_t *)(0x4270803CUL))
#define bFM4_MFS4_CSIO_SCR_UPCL                   *((volatile  uint8_t *)(0x4270803CUL))

#define bFM_MFS4_CSIO_SCSCR_CSOE                  *((volatile  uint8_t *)(0x42708600UL))
#define bFM4_MFS4_CSIO_SCSCR_CSOE                 *((volatile  uint8_t *)(0x42708600UL))
#define bFM_MFS4_CSIO_SCSCR_CSEN0                 *((volatile  uint8_t *)(0x42708604UL))
#define bFM4_MFS4_CSIO_SCSCR_CSEN0                *((volatile  uint8_t *)(0x42708604UL))
#define bFM_MFS4_CSIO_SCSCR_CSEN1                 *((volatile  uint8_t *)(0x42708608UL))
#define bFM4_MFS4_CSIO_SCSCR_CSEN1                *((volatile  uint8_t *)(0x42708608UL))
#define bFM_MFS4_CSIO_SCSCR_CSEN2                 *((volatile  uint8_t *)(0x4270860CUL))
#define bFM4_MFS4_CSIO_SCSCR_CSEN2                *((volatile  uint8_t *)(0x4270860CUL))
#define bFM_MFS4_CSIO_SCSCR_CSEN3                 *((volatile  uint8_t *)(0x42708610UL))
#define bFM4_MFS4_CSIO_SCSCR_CSEN3                *((volatile  uint8_t *)(0x42708610UL))
#define bFM_MFS4_CSIO_SCSCR_CSLVL                 *((volatile  uint8_t *)(0x42708614UL))
#define bFM4_MFS4_CSIO_SCSCR_CSLVL                *((volatile  uint8_t *)(0x42708614UL))
#define bFM_MFS4_CSIO_SCSCR_SCAM                  *((volatile  uint8_t *)(0x42708624UL))
#define bFM4_MFS4_CSIO_SCSCR_SCAM                 *((volatile  uint8_t *)(0x42708624UL))

#define bFM_MFS4_CSIO_SCSFR0_CS1SPI               *((volatile  uint8_t *)(0x42708694UL))
#define bFM4_MFS4_CSIO_SCSFR0_CS1SPI              *((volatile  uint8_t *)(0x42708694UL))
#define bFM_MFS4_CSIO_SCSFR0_CS1SCINV             *((volatile  uint8_t *)(0x42708698UL))
#define bFM4_MFS4_CSIO_SCSFR0_CS1SCINV            *((volatile  uint8_t *)(0x42708698UL))
#define bFM_MFS4_CSIO_SCSFR0_CS1CSLVL             *((volatile  uint8_t *)(0x4270869CUL))
#define bFM4_MFS4_CSIO_SCSFR0_CS1CSLVL            *((volatile  uint8_t *)(0x4270869CUL))

#define bFM_MFS4_CSIO_SCSFR1_CS2SPI               *((volatile  uint8_t *)(0x427086B4UL))
#define bFM4_MFS4_CSIO_SCSFR1_CS2SPI              *((volatile  uint8_t *)(0x427086B4UL))
#define bFM_MFS4_CSIO_SCSFR1_CS2SCINV             *((volatile  uint8_t *)(0x427086B8UL))
#define bFM4_MFS4_CSIO_SCSFR1_CS2SCINV            *((volatile  uint8_t *)(0x427086B8UL))
#define bFM_MFS4_CSIO_SCSFR1_CS2CSLVL             *((volatile  uint8_t *)(0x427086BCUL))
#define bFM4_MFS4_CSIO_SCSFR1_CS2CSLVL            *((volatile  uint8_t *)(0x427086BCUL))

#define bFM_MFS4_CSIO_SCSFR2_CS3SPI               *((volatile  uint8_t *)(0x42708714UL))
#define bFM4_MFS4_CSIO_SCSFR2_CS3SPI              *((volatile  uint8_t *)(0x42708714UL))
#define bFM_MFS4_CSIO_SCSFR2_CS3SCINV             *((volatile  uint8_t *)(0x42708718UL))
#define bFM4_MFS4_CSIO_SCSFR2_CS3SCINV            *((volatile  uint8_t *)(0x42708718UL))
#define bFM_MFS4_CSIO_SCSFR2_CS3CSLVL             *((volatile  uint8_t *)(0x4270871CUL))
#define bFM4_MFS4_CSIO_SCSFR2_CS3CSLVL            *((volatile  uint8_t *)(0x4270871CUL))

#define bFM_MFS4_CSIO_SMR_SOE                     *((volatile  uint8_t *)(0x42708000UL))
#define bFM4_MFS4_CSIO_SMR_SOE                    *((volatile  uint8_t *)(0x42708000UL))
#define bFM_MFS4_CSIO_SMR_SCKE                    *((volatile  uint8_t *)(0x42708004UL))
#define bFM4_MFS4_CSIO_SMR_SCKE                   *((volatile  uint8_t *)(0x42708004UL))
#define bFM_MFS4_CSIO_SMR_BDS                     *((volatile  uint8_t *)(0x42708008UL))
#define bFM4_MFS4_CSIO_SMR_BDS                    *((volatile  uint8_t *)(0x42708008UL))
#define bFM_MFS4_CSIO_SMR_SCINV                   *((volatile  uint8_t *)(0x4270800CUL))
#define bFM4_MFS4_CSIO_SMR_SCINV                  *((volatile  uint8_t *)(0x4270800CUL))

#define bFM_MFS4_CSIO_SSR_TBI                     *((volatile  uint8_t *)(0x427080A0UL))
#define bFM4_MFS4_CSIO_SSR_TBI                    *((volatile  uint8_t *)(0x427080A0UL))
#define bFM_MFS4_CSIO_SSR_TDRE                    *((volatile  uint8_t *)(0x427080A4UL))
#define bFM4_MFS4_CSIO_SSR_TDRE                   *((volatile  uint8_t *)(0x427080A4UL))
#define bFM_MFS4_CSIO_SSR_RDRF                    *((volatile  uint8_t *)(0x427080A8UL))
#define bFM4_MFS4_CSIO_SSR_RDRF                   *((volatile  uint8_t *)(0x427080A8UL))
#define bFM_MFS4_CSIO_SSR_ORE                     *((volatile  uint8_t *)(0x427080ACUL))
#define bFM4_MFS4_CSIO_SSR_ORE                    *((volatile  uint8_t *)(0x427080ACUL))
#define bFM_MFS4_CSIO_SSR_AWC                     *((volatile  uint8_t *)(0x427080B0UL))
#define bFM4_MFS4_CSIO_SSR_AWC                    *((volatile  uint8_t *)(0x427080B0UL))
#define bFM_MFS4_CSIO_SSR_REC                     *((volatile  uint8_t *)(0x427080BCUL))
#define bFM4_MFS4_CSIO_SSR_REC                    *((volatile  uint8_t *)(0x427080BCUL))

#define bFM_MFS4_I2C_EIBCR_BEC                    *((volatile  uint8_t *)(0x427083A0UL))
#define bFM4_MFS4_I2C_EIBCR_BEC                   *((volatile  uint8_t *)(0x427083A0UL))
#define bFM_MFS4_I2C_EIBCR_SOCE                   *((volatile  uint8_t *)(0x427083A4UL))
#define bFM4_MFS4_I2C_EIBCR_SOCE                  *((volatile  uint8_t *)(0x427083A4UL))
#define bFM_MFS4_I2C_EIBCR_SCLC                   *((volatile  uint8_t *)(0x427083A8UL))
#define bFM4_MFS4_I2C_EIBCR_SCLC                  *((volatile  uint8_t *)(0x427083A8UL))
#define bFM_MFS4_I2C_EIBCR_SDAC                   *((volatile  uint8_t *)(0x427083ACUL))
#define bFM4_MFS4_I2C_EIBCR_SDAC                  *((volatile  uint8_t *)(0x427083ACUL))
#define bFM_MFS4_I2C_EIBCR_SCLS                   *((volatile  uint8_t *)(0x427083B0UL))
#define bFM4_MFS4_I2C_EIBCR_SCLS                  *((volatile  uint8_t *)(0x427083B0UL))
#define bFM_MFS4_I2C_EIBCR_SDAS                   *((volatile  uint8_t *)(0x427083B4UL))
#define bFM4_MFS4_I2C_EIBCR_SDAS                  *((volatile  uint8_t *)(0x427083B4UL))

#define bFM_MFS4_I2C_FCR_FE1                      *((volatile  uint8_t *)(0x42708280UL))
#define bFM4_MFS4_I2C_FCR_FE1                     *((volatile  uint8_t *)(0x42708280UL))
#define bFM_MFS4_I2C_FCR_FE2                      *((volatile  uint8_t *)(0x42708284UL))
#define bFM4_MFS4_I2C_FCR_FE2                     *((volatile  uint8_t *)(0x42708284UL))
#define bFM_MFS4_I2C_FCR_FCL1                     *((volatile  uint8_t *)(0x42708288UL))
#define bFM4_MFS4_I2C_FCR_FCL1                    *((volatile  uint8_t *)(0x42708288UL))
#define bFM_MFS4_I2C_FCR_FCL2                     *((volatile  uint8_t *)(0x4270828CUL))
#define bFM4_MFS4_I2C_FCR_FCL2                    *((volatile  uint8_t *)(0x4270828CUL))
#define bFM_MFS4_I2C_FCR_FSET                     *((volatile  uint8_t *)(0x42708290UL))
#define bFM4_MFS4_I2C_FCR_FSET                    *((volatile  uint8_t *)(0x42708290UL))
#define bFM_MFS4_I2C_FCR_FLD                      *((volatile  uint8_t *)(0x42708294UL))
#define bFM4_MFS4_I2C_FCR_FLD                     *((volatile  uint8_t *)(0x42708294UL))
#define bFM_MFS4_I2C_FCR_FLST                     *((volatile  uint8_t *)(0x42708298UL))
#define bFM4_MFS4_I2C_FCR_FLST                    *((volatile  uint8_t *)(0x42708298UL))
#define bFM_MFS4_I2C_FCR_FSEL                     *((volatile  uint8_t *)(0x427082A0UL))
#define bFM4_MFS4_I2C_FCR_FSEL                    *((volatile  uint8_t *)(0x427082A0UL))
#define bFM_MFS4_I2C_FCR_FTIE                     *((volatile  uint8_t *)(0x427082A4UL))
#define bFM4_MFS4_I2C_FCR_FTIE                    *((volatile  uint8_t *)(0x427082A4UL))
#define bFM_MFS4_I2C_FCR_FDRQ                     *((volatile  uint8_t *)(0x427082A8UL))
#define bFM4_MFS4_I2C_FCR_FDRQ                    *((volatile  uint8_t *)(0x427082A8UL))
#define bFM_MFS4_I2C_FCR_FRIIE                    *((volatile  uint8_t *)(0x427082ACUL))
#define bFM4_MFS4_I2C_FCR_FRIIE                   *((volatile  uint8_t *)(0x427082ACUL))
#define bFM_MFS4_I2C_FCR_FLSTE                    *((volatile  uint8_t *)(0x427082B0UL))
#define bFM4_MFS4_I2C_FCR_FLSTE                   *((volatile  uint8_t *)(0x427082B0UL))

#define bFM_MFS4_I2C_IBCR_INT                     *((volatile  uint8_t *)(0x42708020UL))
#define bFM4_MFS4_I2C_IBCR_INT                    *((volatile  uint8_t *)(0x42708020UL))
#define bFM_MFS4_I2C_IBCR_BER                     *((volatile  uint8_t *)(0x42708024UL))
#define bFM4_MFS4_I2C_IBCR_BER                    *((volatile  uint8_t *)(0x42708024UL))
#define bFM_MFS4_I2C_IBCR_INTE                    *((volatile  uint8_t *)(0x42708028UL))
#define bFM4_MFS4_I2C_IBCR_INTE                   *((volatile  uint8_t *)(0x42708028UL))
#define bFM_MFS4_I2C_IBCR_CNDE                    *((volatile  uint8_t *)(0x4270802CUL))
#define bFM4_MFS4_I2C_IBCR_CNDE                   *((volatile  uint8_t *)(0x4270802CUL))
#define bFM_MFS4_I2C_IBCR_WSEL                    *((volatile  uint8_t *)(0x42708030UL))
#define bFM4_MFS4_I2C_IBCR_WSEL                   *((volatile  uint8_t *)(0x42708030UL))
#define bFM_MFS4_I2C_IBCR_ACKE                    *((volatile  uint8_t *)(0x42708034UL))
#define bFM4_MFS4_I2C_IBCR_ACKE                   *((volatile  uint8_t *)(0x42708034UL))
#define bFM_MFS4_I2C_IBCR_ACT_SCC                 *((volatile  uint8_t *)(0x42708038UL))
#define bFM4_MFS4_I2C_IBCR_ACT_SCC                *((volatile  uint8_t *)(0x42708038UL))
#define bFM_MFS4_I2C_IBCR_MSS                     *((volatile  uint8_t *)(0x4270803CUL))
#define bFM4_MFS4_I2C_IBCR_MSS                    *((volatile  uint8_t *)(0x4270803CUL))

#define bFM_MFS4_I2C_IBSR_BB                      *((volatile  uint8_t *)(0x42708080UL))
#define bFM4_MFS4_I2C_IBSR_BB                     *((volatile  uint8_t *)(0x42708080UL))
#define bFM_MFS4_I2C_IBSR_SPC                     *((volatile  uint8_t *)(0x42708084UL))
#define bFM4_MFS4_I2C_IBSR_SPC                    *((volatile  uint8_t *)(0x42708084UL))
#define bFM_MFS4_I2C_IBSR_RSC                     *((volatile  uint8_t *)(0x42708088UL))
#define bFM4_MFS4_I2C_IBSR_RSC                    *((volatile  uint8_t *)(0x42708088UL))
#define bFM_MFS4_I2C_IBSR_AL                      *((volatile  uint8_t *)(0x4270808CUL))
#define bFM4_MFS4_I2C_IBSR_AL                     *((volatile  uint8_t *)(0x4270808CUL))
#define bFM_MFS4_I2C_IBSR_TRX                     *((volatile  uint8_t *)(0x42708090UL))
#define bFM4_MFS4_I2C_IBSR_TRX                    *((volatile  uint8_t *)(0x42708090UL))
#define bFM_MFS4_I2C_IBSR_RSA                     *((volatile  uint8_t *)(0x42708094UL))
#define bFM4_MFS4_I2C_IBSR_RSA                    *((volatile  uint8_t *)(0x42708094UL))
#define bFM_MFS4_I2C_IBSR_RACK                    *((volatile  uint8_t *)(0x42708098UL))
#define bFM4_MFS4_I2C_IBSR_RACK                   *((volatile  uint8_t *)(0x42708098UL))
#define bFM_MFS4_I2C_IBSR_FBT                     *((volatile  uint8_t *)(0x4270809CUL))
#define bFM4_MFS4_I2C_IBSR_FBT                    *((volatile  uint8_t *)(0x4270809CUL))

#define bFM_MFS4_I2C_ISBA_SAEN                    *((volatile  uint8_t *)(0x4270821CUL))
#define bFM4_MFS4_I2C_ISBA_SAEN                   *((volatile  uint8_t *)(0x4270821CUL))

#define bFM_MFS4_I2C_ISMK_EN                      *((volatile  uint8_t *)(0x4270823CUL))
#define bFM4_MFS4_I2C_ISMK_EN                     *((volatile  uint8_t *)(0x4270823CUL))

#define bFM_MFS4_I2C_SMR_TIE                      *((volatile  uint8_t *)(0x42708008UL))
#define bFM4_MFS4_I2C_SMR_TIE                     *((volatile  uint8_t *)(0x42708008UL))
#define bFM_MFS4_I2C_SMR_RIE                      *((volatile  uint8_t *)(0x4270800CUL))
#define bFM4_MFS4_I2C_SMR_RIE                     *((volatile  uint8_t *)(0x4270800CUL))

#define bFM_MFS4_I2C_SSR_TBI                      *((volatile  uint8_t *)(0x427080A0UL))
#define bFM4_MFS4_I2C_SSR_TBI                     *((volatile  uint8_t *)(0x427080A0UL))
#define bFM_MFS4_I2C_SSR_TDRE                     *((volatile  uint8_t *)(0x427080A4UL))
#define bFM4_MFS4_I2C_SSR_TDRE                    *((volatile  uint8_t *)(0x427080A4UL))
#define bFM_MFS4_I2C_SSR_RDRF                     *((volatile  uint8_t *)(0x427080A8UL))
#define bFM4_MFS4_I2C_SSR_RDRF                    *((volatile  uint8_t *)(0x427080A8UL))
#define bFM_MFS4_I2C_SSR_ORE                      *((volatile  uint8_t *)(0x427080ACUL))
#define bFM4_MFS4_I2C_SSR_ORE                     *((volatile  uint8_t *)(0x427080ACUL))
#define bFM_MFS4_I2C_SSR_TBIE                     *((volatile  uint8_t *)(0x427080B0UL))
#define bFM4_MFS4_I2C_SSR_TBIE                    *((volatile  uint8_t *)(0x427080B0UL))
#define bFM_MFS4_I2C_SSR_DMA                      *((volatile  uint8_t *)(0x427080B4UL))
#define bFM4_MFS4_I2C_SSR_DMA                     *((volatile  uint8_t *)(0x427080B4UL))
#define bFM_MFS4_I2C_SSR_TSET                     *((volatile  uint8_t *)(0x427080B8UL))
#define bFM4_MFS4_I2C_SSR_TSET                    *((volatile  uint8_t *)(0x427080B8UL))
#define bFM_MFS4_I2C_SSR_REC                      *((volatile  uint8_t *)(0x427080BCUL))
#define bFM4_MFS4_I2C_SSR_REC                     *((volatile  uint8_t *)(0x427080BCUL))

#define bFM_MFS4_LIN_BGR_EXT                      *((volatile  uint8_t *)(0x427081BCUL))
#define bFM4_MFS4_LIN_BGR_EXT                     *((volatile  uint8_t *)(0x427081BCUL))

#define bFM_MFS4_LIN_ESCR_LBIE                    *((volatile  uint8_t *)(0x42708090UL))
#define bFM4_MFS4_LIN_ESCR_LBIE                   *((volatile  uint8_t *)(0x42708090UL))
#define bFM_MFS4_LIN_ESCR_ESBL                    *((volatile  uint8_t *)(0x42708098UL))
#define bFM4_MFS4_LIN_ESCR_ESBL                   *((volatile  uint8_t *)(0x42708098UL))

#define bFM_MFS4_LIN_FCR_FE1                      *((volatile  uint8_t *)(0x42708280UL))
#define bFM4_MFS4_LIN_FCR_FE1                     *((volatile  uint8_t *)(0x42708280UL))
#define bFM_MFS4_LIN_FCR_FE2                      *((volatile  uint8_t *)(0x42708284UL))
#define bFM4_MFS4_LIN_FCR_FE2                     *((volatile  uint8_t *)(0x42708284UL))
#define bFM_MFS4_LIN_FCR_FCL1                     *((volatile  uint8_t *)(0x42708288UL))
#define bFM4_MFS4_LIN_FCR_FCL1                    *((volatile  uint8_t *)(0x42708288UL))
#define bFM_MFS4_LIN_FCR_FCL2                     *((volatile  uint8_t *)(0x4270828CUL))
#define bFM4_MFS4_LIN_FCR_FCL2                    *((volatile  uint8_t *)(0x4270828CUL))
#define bFM_MFS4_LIN_FCR_FSET                     *((volatile  uint8_t *)(0x42708290UL))
#define bFM4_MFS4_LIN_FCR_FSET                    *((volatile  uint8_t *)(0x42708290UL))
#define bFM_MFS4_LIN_FCR_FLD                      *((volatile  uint8_t *)(0x42708294UL))
#define bFM4_MFS4_LIN_FCR_FLD                     *((volatile  uint8_t *)(0x42708294UL))
#define bFM_MFS4_LIN_FCR_FLST                     *((volatile  uint8_t *)(0x42708298UL))
#define bFM4_MFS4_LIN_FCR_FLST                    *((volatile  uint8_t *)(0x42708298UL))
#define bFM_MFS4_LIN_FCR_FSEL                     *((volatile  uint8_t *)(0x427082A0UL))
#define bFM4_MFS4_LIN_FCR_FSEL                    *((volatile  uint8_t *)(0x427082A0UL))
#define bFM_MFS4_LIN_FCR_FTIE                     *((volatile  uint8_t *)(0x427082A4UL))
#define bFM4_MFS4_LIN_FCR_FTIE                    *((volatile  uint8_t *)(0x427082A4UL))
#define bFM_MFS4_LIN_FCR_FDRQ                     *((volatile  uint8_t *)(0x427082A8UL))
#define bFM4_MFS4_LIN_FCR_FDRQ                    *((volatile  uint8_t *)(0x427082A8UL))
#define bFM_MFS4_LIN_FCR_FRIIE                    *((volatile  uint8_t *)(0x427082ACUL))
#define bFM4_MFS4_LIN_FCR_FRIIE                   *((volatile  uint8_t *)(0x427082ACUL))
#define bFM_MFS4_LIN_FCR_FLSTE                    *((volatile  uint8_t *)(0x427082B0UL))
#define bFM4_MFS4_LIN_FCR_FLSTE                   *((volatile  uint8_t *)(0x427082B0UL))

#define bFM_MFS4_LIN_SCR_TXE                      *((volatile  uint8_t *)(0x42708020UL))
#define bFM4_MFS4_LIN_SCR_TXE                     *((volatile  uint8_t *)(0x42708020UL))
#define bFM_MFS4_LIN_SCR_RXE                      *((volatile  uint8_t *)(0x42708024UL))
#define bFM4_MFS4_LIN_SCR_RXE                     *((volatile  uint8_t *)(0x42708024UL))
#define bFM_MFS4_LIN_SCR_TBIE                     *((volatile  uint8_t *)(0x42708028UL))
#define bFM4_MFS4_LIN_SCR_TBIE                    *((volatile  uint8_t *)(0x42708028UL))
#define bFM_MFS4_LIN_SCR_TIE                      *((volatile  uint8_t *)(0x4270802CUL))
#define bFM4_MFS4_LIN_SCR_TIE                     *((volatile  uint8_t *)(0x4270802CUL))
#define bFM_MFS4_LIN_SCR_RIE                      *((volatile  uint8_t *)(0x42708030UL))
#define bFM4_MFS4_LIN_SCR_RIE                     *((volatile  uint8_t *)(0x42708030UL))
#define bFM_MFS4_LIN_SCR_LBR                      *((volatile  uint8_t *)(0x42708034UL))
#define bFM4_MFS4_LIN_SCR_LBR                     *((volatile  uint8_t *)(0x42708034UL))
#define bFM_MFS4_LIN_SCR_MS                       *((volatile  uint8_t *)(0x42708038UL))
#define bFM4_MFS4_LIN_SCR_MS                      *((volatile  uint8_t *)(0x42708038UL))
#define bFM_MFS4_LIN_SCR_UPCL                     *((volatile  uint8_t *)(0x4270803CUL))
#define bFM4_MFS4_LIN_SCR_UPCL                    *((volatile  uint8_t *)(0x4270803CUL))

#define bFM_MFS4_LIN_SMR_SOE                      *((volatile  uint8_t *)(0x42708000UL))
#define bFM4_MFS4_LIN_SMR_SOE                     *((volatile  uint8_t *)(0x42708000UL))
#define bFM_MFS4_LIN_SMR_SBL                      *((volatile  uint8_t *)(0x4270800CUL))
#define bFM4_MFS4_LIN_SMR_SBL                     *((volatile  uint8_t *)(0x4270800CUL))
#define bFM_MFS4_LIN_SMR_WUCR                     *((volatile  uint8_t *)(0x42708010UL))
#define bFM4_MFS4_LIN_SMR_WUCR                    *((volatile  uint8_t *)(0x42708010UL))

#define bFM_MFS4_LIN_SSR_TBI                      *((volatile  uint8_t *)(0x427080A0UL))
#define bFM4_MFS4_LIN_SSR_TBI                     *((volatile  uint8_t *)(0x427080A0UL))
#define bFM_MFS4_LIN_SSR_TDRE                     *((volatile  uint8_t *)(0x427080A4UL))
#define bFM4_MFS4_LIN_SSR_TDRE                    *((volatile  uint8_t *)(0x427080A4UL))
#define bFM_MFS4_LIN_SSR_RDRF                     *((volatile  uint8_t *)(0x427080A8UL))
#define bFM4_MFS4_LIN_SSR_RDRF                    *((volatile  uint8_t *)(0x427080A8UL))
#define bFM_MFS4_LIN_SSR_ORE                      *((volatile  uint8_t *)(0x427080ACUL))
#define bFM4_MFS4_LIN_SSR_ORE                     *((volatile  uint8_t *)(0x427080ACUL))
#define bFM_MFS4_LIN_SSR_FRE                      *((volatile  uint8_t *)(0x427080B0UL))
#define bFM4_MFS4_LIN_SSR_FRE                     *((volatile  uint8_t *)(0x427080B0UL))
#define bFM_MFS4_LIN_SSR_LBD                      *((volatile  uint8_t *)(0x427080B4UL))
#define bFM4_MFS4_LIN_SSR_LBD                     *((volatile  uint8_t *)(0x427080B4UL))
#define bFM_MFS4_LIN_SSR_REC                      *((volatile  uint8_t *)(0x427080BCUL))
#define bFM4_MFS4_LIN_SSR_REC                     *((volatile  uint8_t *)(0x427080BCUL))

#define bFM_MFS4_UART_BGR_EXT                     *((volatile  uint8_t *)(0x427081BCUL))
#define bFM4_MFS4_UART_BGR_EXT                    *((volatile  uint8_t *)(0x427081BCUL))

#define bFM_MFS4_UART_ESCR_P                      *((volatile  uint8_t *)(0x4270808CUL))
#define bFM4_MFS4_UART_ESCR_P                     *((volatile  uint8_t *)(0x4270808CUL))
#define bFM_MFS4_UART_ESCR_PEN                    *((volatile  uint8_t *)(0x42708090UL))
#define bFM4_MFS4_UART_ESCR_PEN                   *((volatile  uint8_t *)(0x42708090UL))
#define bFM_MFS4_UART_ESCR_INV                    *((volatile  uint8_t *)(0x42708094UL))
#define bFM4_MFS4_UART_ESCR_INV                   *((volatile  uint8_t *)(0x42708094UL))
#define bFM_MFS4_UART_ESCR_ESBL                   *((volatile  uint8_t *)(0x42708098UL))
#define bFM4_MFS4_UART_ESCR_ESBL                  *((volatile  uint8_t *)(0x42708098UL))
#define bFM_MFS4_UART_ESCR_FLWEN                  *((volatile  uint8_t *)(0x4270809CUL))
#define bFM4_MFS4_UART_ESCR_FLWEN                 *((volatile  uint8_t *)(0x4270809CUL))

#define bFM_MFS4_UART_FCR_FE1                     *((volatile  uint8_t *)(0x42708280UL))
#define bFM4_MFS4_UART_FCR_FE1                    *((volatile  uint8_t *)(0x42708280UL))
#define bFM_MFS4_UART_FCR_FE2                     *((volatile  uint8_t *)(0x42708284UL))
#define bFM4_MFS4_UART_FCR_FE2                    *((volatile  uint8_t *)(0x42708284UL))
#define bFM_MFS4_UART_FCR_FCL1                    *((volatile  uint8_t *)(0x42708288UL))
#define bFM4_MFS4_UART_FCR_FCL1                   *((volatile  uint8_t *)(0x42708288UL))
#define bFM_MFS4_UART_FCR_FCL2                    *((volatile  uint8_t *)(0x4270828CUL))
#define bFM4_MFS4_UART_FCR_FCL2                   *((volatile  uint8_t *)(0x4270828CUL))
#define bFM_MFS4_UART_FCR_FSET                    *((volatile  uint8_t *)(0x42708290UL))
#define bFM4_MFS4_UART_FCR_FSET                   *((volatile  uint8_t *)(0x42708290UL))
#define bFM_MFS4_UART_FCR_FLD                     *((volatile  uint8_t *)(0x42708294UL))
#define bFM4_MFS4_UART_FCR_FLD                    *((volatile  uint8_t *)(0x42708294UL))
#define bFM_MFS4_UART_FCR_FLST                    *((volatile  uint8_t *)(0x42708298UL))
#define bFM4_MFS4_UART_FCR_FLST                   *((volatile  uint8_t *)(0x42708298UL))
#define bFM_MFS4_UART_FCR_FSEL                    *((volatile  uint8_t *)(0x427082A0UL))
#define bFM4_MFS4_UART_FCR_FSEL                   *((volatile  uint8_t *)(0x427082A0UL))
#define bFM_MFS4_UART_FCR_FTIE                    *((volatile  uint8_t *)(0x427082A4UL))
#define bFM4_MFS4_UART_FCR_FTIE                   *((volatile  uint8_t *)(0x427082A4UL))
#define bFM_MFS4_UART_FCR_FDRQ                    *((volatile  uint8_t *)(0x427082A8UL))
#define bFM4_MFS4_UART_FCR_FDRQ                   *((volatile  uint8_t *)(0x427082A8UL))
#define bFM_MFS4_UART_FCR_FRIIE                   *((volatile  uint8_t *)(0x427082ACUL))
#define bFM4_MFS4_UART_FCR_FRIIE                  *((volatile  uint8_t *)(0x427082ACUL))
#define bFM_MFS4_UART_FCR_FLSTE                   *((volatile  uint8_t *)(0x427082B0UL))
#define bFM4_MFS4_UART_FCR_FLSTE                  *((volatile  uint8_t *)(0x427082B0UL))

#define bFM_MFS4_UART_SCR_TXE                     *((volatile  uint8_t *)(0x42708020UL))
#define bFM4_MFS4_UART_SCR_TXE                    *((volatile  uint8_t *)(0x42708020UL))
#define bFM_MFS4_UART_SCR_RXE                     *((volatile  uint8_t *)(0x42708024UL))
#define bFM4_MFS4_UART_SCR_RXE                    *((volatile  uint8_t *)(0x42708024UL))
#define bFM_MFS4_UART_SCR_TBIE                    *((volatile  uint8_t *)(0x42708028UL))
#define bFM4_MFS4_UART_SCR_TBIE                   *((volatile  uint8_t *)(0x42708028UL))
#define bFM_MFS4_UART_SCR_TIE                     *((volatile  uint8_t *)(0x4270802CUL))
#define bFM4_MFS4_UART_SCR_TIE                    *((volatile  uint8_t *)(0x4270802CUL))
#define bFM_MFS4_UART_SCR_RIE                     *((volatile  uint8_t *)(0x42708030UL))
#define bFM4_MFS4_UART_SCR_RIE                    *((volatile  uint8_t *)(0x42708030UL))
#define bFM_MFS4_UART_SCR_UPCL                    *((volatile  uint8_t *)(0x4270803CUL))
#define bFM4_MFS4_UART_SCR_UPCL                   *((volatile  uint8_t *)(0x4270803CUL))

#define bFM_MFS4_UART_SMR_SOE                     *((volatile  uint8_t *)(0x42708000UL))
#define bFM4_MFS4_UART_SMR_SOE                    *((volatile  uint8_t *)(0x42708000UL))
#define bFM_MFS4_UART_SMR_BDS                     *((volatile  uint8_t *)(0x42708008UL))
#define bFM4_MFS4_UART_SMR_BDS                    *((volatile  uint8_t *)(0x42708008UL))
#define bFM_MFS4_UART_SMR_SBL                     *((volatile  uint8_t *)(0x4270800CUL))
#define bFM4_MFS4_UART_SMR_SBL                    *((volatile  uint8_t *)(0x4270800CUL))

#define bFM_MFS4_UART_SSR_TBI                     *((volatile  uint8_t *)(0x427080A0UL))
#define bFM4_MFS4_UART_SSR_TBI                    *((volatile  uint8_t *)(0x427080A0UL))
#define bFM_MFS4_UART_SSR_TDRE                    *((volatile  uint8_t *)(0x427080A4UL))
#define bFM4_MFS4_UART_SSR_TDRE                   *((volatile  uint8_t *)(0x427080A4UL))
#define bFM_MFS4_UART_SSR_RDRF                    *((volatile  uint8_t *)(0x427080A8UL))
#define bFM4_MFS4_UART_SSR_RDRF                   *((volatile  uint8_t *)(0x427080A8UL))
#define bFM_MFS4_UART_SSR_ORE                     *((volatile  uint8_t *)(0x427080ACUL))
#define bFM4_MFS4_UART_SSR_ORE                    *((volatile  uint8_t *)(0x427080ACUL))
#define bFM_MFS4_UART_SSR_FRE                     *((volatile  uint8_t *)(0x427080B0UL))
#define bFM4_MFS4_UART_SSR_FRE                    *((volatile  uint8_t *)(0x427080B0UL))
#define bFM_MFS4_UART_SSR_PE                      *((volatile  uint8_t *)(0x427080B4UL))
#define bFM4_MFS4_UART_SSR_PE                     *((volatile  uint8_t *)(0x427080B4UL))
#define bFM_MFS4_UART_SSR_REC                     *((volatile  uint8_t *)(0x427080BCUL))
#define bFM4_MFS4_UART_SSR_REC                    *((volatile  uint8_t *)(0x427080BCUL))


/*******************************************************************************
* MFS Registers MFS5
*   Bitband Section
*******************************************************************************/
#define bFM_MFS5_CSIO_ESCR_CSFE                   *((volatile  uint8_t *)(0x4270A094UL))
#define bFM4_MFS5_CSIO_ESCR_CSFE                  *((volatile  uint8_t *)(0x4270A094UL))
#define bFM_MFS5_CSIO_ESCR_L3                     *((volatile  uint8_t *)(0x4270A098UL))
#define bFM4_MFS5_CSIO_ESCR_L3                    *((volatile  uint8_t *)(0x4270A098UL))
#define bFM_MFS5_CSIO_ESCR_SOP                    *((volatile  uint8_t *)(0x4270A09CUL))
#define bFM4_MFS5_CSIO_ESCR_SOP                   *((volatile  uint8_t *)(0x4270A09CUL))

#define bFM_MFS5_CSIO_FCR_FE1                     *((volatile  uint8_t *)(0x4270A280UL))
#define bFM4_MFS5_CSIO_FCR_FE1                    *((volatile  uint8_t *)(0x4270A280UL))
#define bFM_MFS5_CSIO_FCR_FE2                     *((volatile  uint8_t *)(0x4270A284UL))
#define bFM4_MFS5_CSIO_FCR_FE2                    *((volatile  uint8_t *)(0x4270A284UL))
#define bFM_MFS5_CSIO_FCR_FCL1                    *((volatile  uint8_t *)(0x4270A288UL))
#define bFM4_MFS5_CSIO_FCR_FCL1                   *((volatile  uint8_t *)(0x4270A288UL))
#define bFM_MFS5_CSIO_FCR_FCL2                    *((volatile  uint8_t *)(0x4270A28CUL))
#define bFM4_MFS5_CSIO_FCR_FCL2                   *((volatile  uint8_t *)(0x4270A28CUL))
#define bFM_MFS5_CSIO_FCR_FSET                    *((volatile  uint8_t *)(0x4270A290UL))
#define bFM4_MFS5_CSIO_FCR_FSET                   *((volatile  uint8_t *)(0x4270A290UL))
#define bFM_MFS5_CSIO_FCR_FLD                     *((volatile  uint8_t *)(0x4270A294UL))
#define bFM4_MFS5_CSIO_FCR_FLD                    *((volatile  uint8_t *)(0x4270A294UL))
#define bFM_MFS5_CSIO_FCR_FLST                    *((volatile  uint8_t *)(0x4270A298UL))
#define bFM4_MFS5_CSIO_FCR_FLST                   *((volatile  uint8_t *)(0x4270A298UL))
#define bFM_MFS5_CSIO_FCR_FSEL                    *((volatile  uint8_t *)(0x4270A2A0UL))
#define bFM4_MFS5_CSIO_FCR_FSEL                   *((volatile  uint8_t *)(0x4270A2A0UL))
#define bFM_MFS5_CSIO_FCR_FTIE                    *((volatile  uint8_t *)(0x4270A2A4UL))
#define bFM4_MFS5_CSIO_FCR_FTIE                   *((volatile  uint8_t *)(0x4270A2A4UL))
#define bFM_MFS5_CSIO_FCR_FDRQ                    *((volatile  uint8_t *)(0x4270A2A8UL))
#define bFM4_MFS5_CSIO_FCR_FDRQ                   *((volatile  uint8_t *)(0x4270A2A8UL))
#define bFM_MFS5_CSIO_FCR_FRIIE                   *((volatile  uint8_t *)(0x4270A2ACUL))
#define bFM4_MFS5_CSIO_FCR_FRIIE                  *((volatile  uint8_t *)(0x4270A2ACUL))
#define bFM_MFS5_CSIO_FCR_FLSTE                   *((volatile  uint8_t *)(0x4270A2B0UL))
#define bFM4_MFS5_CSIO_FCR_FLSTE                  *((volatile  uint8_t *)(0x4270A2B0UL))

#define bFM_MFS5_CSIO_SACSR_TMRE                  *((volatile  uint8_t *)(0x4270A480UL))
#define bFM4_MFS5_CSIO_SACSR_TMRE                 *((volatile  uint8_t *)(0x4270A480UL))
#define bFM_MFS5_CSIO_SACSR_TSYNE                 *((volatile  uint8_t *)(0x4270A498UL))
#define bFM4_MFS5_CSIO_SACSR_TSYNE                *((volatile  uint8_t *)(0x4270A498UL))
#define bFM_MFS5_CSIO_SACSR_TINTE                 *((volatile  uint8_t *)(0x4270A49CUL))
#define bFM4_MFS5_CSIO_SACSR_TINTE                *((volatile  uint8_t *)(0x4270A49CUL))
#define bFM_MFS5_CSIO_SACSR_TINT                  *((volatile  uint8_t *)(0x4270A4A0UL))
#define bFM4_MFS5_CSIO_SACSR_TINT                 *((volatile  uint8_t *)(0x4270A4A0UL))
#define bFM_MFS5_CSIO_SACSR_CSE                   *((volatile  uint8_t *)(0x4270A4ACUL))
#define bFM4_MFS5_CSIO_SACSR_CSE                  *((volatile  uint8_t *)(0x4270A4ACUL))
#define bFM_MFS5_CSIO_SACSR_CSEIE                 *((volatile  uint8_t *)(0x4270A4B0UL))
#define bFM4_MFS5_CSIO_SACSR_CSEIE                *((volatile  uint8_t *)(0x4270A4B0UL))
#define bFM_MFS5_CSIO_SACSR_TBEEN                 *((volatile  uint8_t *)(0x4270A4B4UL))
#define bFM4_MFS5_CSIO_SACSR_TBEEN                *((volatile  uint8_t *)(0x4270A4B4UL))

#define bFM_MFS5_CSIO_SCR_TXE                     *((volatile  uint8_t *)(0x4270A020UL))
#define bFM4_MFS5_CSIO_SCR_TXE                    *((volatile  uint8_t *)(0x4270A020UL))
#define bFM_MFS5_CSIO_SCR_RXE                     *((volatile  uint8_t *)(0x4270A024UL))
#define bFM4_MFS5_CSIO_SCR_RXE                    *((volatile  uint8_t *)(0x4270A024UL))
#define bFM_MFS5_CSIO_SCR_TBIE                    *((volatile  uint8_t *)(0x4270A028UL))
#define bFM4_MFS5_CSIO_SCR_TBIE                   *((volatile  uint8_t *)(0x4270A028UL))
#define bFM_MFS5_CSIO_SCR_TIE                     *((volatile  uint8_t *)(0x4270A02CUL))
#define bFM4_MFS5_CSIO_SCR_TIE                    *((volatile  uint8_t *)(0x4270A02CUL))
#define bFM_MFS5_CSIO_SCR_RIE                     *((volatile  uint8_t *)(0x4270A030UL))
#define bFM4_MFS5_CSIO_SCR_RIE                    *((volatile  uint8_t *)(0x4270A030UL))
#define bFM_MFS5_CSIO_SCR_SPI                     *((volatile  uint8_t *)(0x4270A034UL))
#define bFM4_MFS5_CSIO_SCR_SPI                    *((volatile  uint8_t *)(0x4270A034UL))
#define bFM_MFS5_CSIO_SCR_MS                      *((volatile  uint8_t *)(0x4270A038UL))
#define bFM4_MFS5_CSIO_SCR_MS                     *((volatile  uint8_t *)(0x4270A038UL))
#define bFM_MFS5_CSIO_SCR_UPCL                    *((volatile  uint8_t *)(0x4270A03CUL))
#define bFM4_MFS5_CSIO_SCR_UPCL                   *((volatile  uint8_t *)(0x4270A03CUL))

#define bFM_MFS5_CSIO_SCSCR_CSOE                  *((volatile  uint8_t *)(0x4270A600UL))
#define bFM4_MFS5_CSIO_SCSCR_CSOE                 *((volatile  uint8_t *)(0x4270A600UL))
#define bFM_MFS5_CSIO_SCSCR_CSEN0                 *((volatile  uint8_t *)(0x4270A604UL))
#define bFM4_MFS5_CSIO_SCSCR_CSEN0                *((volatile  uint8_t *)(0x4270A604UL))
#define bFM_MFS5_CSIO_SCSCR_CSEN1                 *((volatile  uint8_t *)(0x4270A608UL))
#define bFM4_MFS5_CSIO_SCSCR_CSEN1                *((volatile  uint8_t *)(0x4270A608UL))
#define bFM_MFS5_CSIO_SCSCR_CSEN2                 *((volatile  uint8_t *)(0x4270A60CUL))
#define bFM4_MFS5_CSIO_SCSCR_CSEN2                *((volatile  uint8_t *)(0x4270A60CUL))
#define bFM_MFS5_CSIO_SCSCR_CSEN3                 *((volatile  uint8_t *)(0x4270A610UL))
#define bFM4_MFS5_CSIO_SCSCR_CSEN3                *((volatile  uint8_t *)(0x4270A610UL))
#define bFM_MFS5_CSIO_SCSCR_CSLVL                 *((volatile  uint8_t *)(0x4270A614UL))
#define bFM4_MFS5_CSIO_SCSCR_CSLVL                *((volatile  uint8_t *)(0x4270A614UL))
#define bFM_MFS5_CSIO_SCSCR_SCAM                  *((volatile  uint8_t *)(0x4270A624UL))
#define bFM4_MFS5_CSIO_SCSCR_SCAM                 *((volatile  uint8_t *)(0x4270A624UL))

#define bFM_MFS5_CSIO_SCSFR0_CS1SPI               *((volatile  uint8_t *)(0x4270A694UL))
#define bFM4_MFS5_CSIO_SCSFR0_CS1SPI              *((volatile  uint8_t *)(0x4270A694UL))
#define bFM_MFS5_CSIO_SCSFR0_CS1SCINV             *((volatile  uint8_t *)(0x4270A698UL))
#define bFM4_MFS5_CSIO_SCSFR0_CS1SCINV            *((volatile  uint8_t *)(0x4270A698UL))
#define bFM_MFS5_CSIO_SCSFR0_CS1CSLVL             *((volatile  uint8_t *)(0x4270A69CUL))
#define bFM4_MFS5_CSIO_SCSFR0_CS1CSLVL            *((volatile  uint8_t *)(0x4270A69CUL))

#define bFM_MFS5_CSIO_SCSFR1_CS2SPI               *((volatile  uint8_t *)(0x4270A6B4UL))
#define bFM4_MFS5_CSIO_SCSFR1_CS2SPI              *((volatile  uint8_t *)(0x4270A6B4UL))
#define bFM_MFS5_CSIO_SCSFR1_CS2SCINV             *((volatile  uint8_t *)(0x4270A6B8UL))
#define bFM4_MFS5_CSIO_SCSFR1_CS2SCINV            *((volatile  uint8_t *)(0x4270A6B8UL))
#define bFM_MFS5_CSIO_SCSFR1_CS2CSLVL             *((volatile  uint8_t *)(0x4270A6BCUL))
#define bFM4_MFS5_CSIO_SCSFR1_CS2CSLVL            *((volatile  uint8_t *)(0x4270A6BCUL))

#define bFM_MFS5_CSIO_SCSFR2_CS3SPI               *((volatile  uint8_t *)(0x4270A714UL))
#define bFM4_MFS5_CSIO_SCSFR2_CS3SPI              *((volatile  uint8_t *)(0x4270A714UL))
#define bFM_MFS5_CSIO_SCSFR2_CS3SCINV             *((volatile  uint8_t *)(0x4270A718UL))
#define bFM4_MFS5_CSIO_SCSFR2_CS3SCINV            *((volatile  uint8_t *)(0x4270A718UL))
#define bFM_MFS5_CSIO_SCSFR2_CS3CSLVL             *((volatile  uint8_t *)(0x4270A71CUL))
#define bFM4_MFS5_CSIO_SCSFR2_CS3CSLVL            *((volatile  uint8_t *)(0x4270A71CUL))

#define bFM_MFS5_CSIO_SMR_SOE                     *((volatile  uint8_t *)(0x4270A000UL))
#define bFM4_MFS5_CSIO_SMR_SOE                    *((volatile  uint8_t *)(0x4270A000UL))
#define bFM_MFS5_CSIO_SMR_SCKE                    *((volatile  uint8_t *)(0x4270A004UL))
#define bFM4_MFS5_CSIO_SMR_SCKE                   *((volatile  uint8_t *)(0x4270A004UL))
#define bFM_MFS5_CSIO_SMR_BDS                     *((volatile  uint8_t *)(0x4270A008UL))
#define bFM4_MFS5_CSIO_SMR_BDS                    *((volatile  uint8_t *)(0x4270A008UL))
#define bFM_MFS5_CSIO_SMR_SCINV                   *((volatile  uint8_t *)(0x4270A00CUL))
#define bFM4_MFS5_CSIO_SMR_SCINV                  *((volatile  uint8_t *)(0x4270A00CUL))

#define bFM_MFS5_CSIO_SSR_TBI                     *((volatile  uint8_t *)(0x4270A0A0UL))
#define bFM4_MFS5_CSIO_SSR_TBI                    *((volatile  uint8_t *)(0x4270A0A0UL))
#define bFM_MFS5_CSIO_SSR_TDRE                    *((volatile  uint8_t *)(0x4270A0A4UL))
#define bFM4_MFS5_CSIO_SSR_TDRE                   *((volatile  uint8_t *)(0x4270A0A4UL))
#define bFM_MFS5_CSIO_SSR_RDRF                    *((volatile  uint8_t *)(0x4270A0A8UL))
#define bFM4_MFS5_CSIO_SSR_RDRF                   *((volatile  uint8_t *)(0x4270A0A8UL))
#define bFM_MFS5_CSIO_SSR_ORE                     *((volatile  uint8_t *)(0x4270A0ACUL))
#define bFM4_MFS5_CSIO_SSR_ORE                    *((volatile  uint8_t *)(0x4270A0ACUL))
#define bFM_MFS5_CSIO_SSR_AWC                     *((volatile  uint8_t *)(0x4270A0B0UL))
#define bFM4_MFS5_CSIO_SSR_AWC                    *((volatile  uint8_t *)(0x4270A0B0UL))
#define bFM_MFS5_CSIO_SSR_REC                     *((volatile  uint8_t *)(0x4270A0BCUL))
#define bFM4_MFS5_CSIO_SSR_REC                    *((volatile  uint8_t *)(0x4270A0BCUL))

#define bFM_MFS5_I2C_EIBCR_BEC                    *((volatile  uint8_t *)(0x4270A3A0UL))
#define bFM4_MFS5_I2C_EIBCR_BEC                   *((volatile  uint8_t *)(0x4270A3A0UL))
#define bFM_MFS5_I2C_EIBCR_SOCE                   *((volatile  uint8_t *)(0x4270A3A4UL))
#define bFM4_MFS5_I2C_EIBCR_SOCE                  *((volatile  uint8_t *)(0x4270A3A4UL))
#define bFM_MFS5_I2C_EIBCR_SCLC                   *((volatile  uint8_t *)(0x4270A3A8UL))
#define bFM4_MFS5_I2C_EIBCR_SCLC                  *((volatile  uint8_t *)(0x4270A3A8UL))
#define bFM_MFS5_I2C_EIBCR_SDAC                   *((volatile  uint8_t *)(0x4270A3ACUL))
#define bFM4_MFS5_I2C_EIBCR_SDAC                  *((volatile  uint8_t *)(0x4270A3ACUL))
#define bFM_MFS5_I2C_EIBCR_SCLS                   *((volatile  uint8_t *)(0x4270A3B0UL))
#define bFM4_MFS5_I2C_EIBCR_SCLS                  *((volatile  uint8_t *)(0x4270A3B0UL))
#define bFM_MFS5_I2C_EIBCR_SDAS                   *((volatile  uint8_t *)(0x4270A3B4UL))
#define bFM4_MFS5_I2C_EIBCR_SDAS                  *((volatile  uint8_t *)(0x4270A3B4UL))

#define bFM_MFS5_I2C_FCR_FE1                      *((volatile  uint8_t *)(0x4270A280UL))
#define bFM4_MFS5_I2C_FCR_FE1                     *((volatile  uint8_t *)(0x4270A280UL))
#define bFM_MFS5_I2C_FCR_FE2                      *((volatile  uint8_t *)(0x4270A284UL))
#define bFM4_MFS5_I2C_FCR_FE2                     *((volatile  uint8_t *)(0x4270A284UL))
#define bFM_MFS5_I2C_FCR_FCL1                     *((volatile  uint8_t *)(0x4270A288UL))
#define bFM4_MFS5_I2C_FCR_FCL1                    *((volatile  uint8_t *)(0x4270A288UL))
#define bFM_MFS5_I2C_FCR_FCL2                     *((volatile  uint8_t *)(0x4270A28CUL))
#define bFM4_MFS5_I2C_FCR_FCL2                    *((volatile  uint8_t *)(0x4270A28CUL))
#define bFM_MFS5_I2C_FCR_FSET                     *((volatile  uint8_t *)(0x4270A290UL))
#define bFM4_MFS5_I2C_FCR_FSET                    *((volatile  uint8_t *)(0x4270A290UL))
#define bFM_MFS5_I2C_FCR_FLD                      *((volatile  uint8_t *)(0x4270A294UL))
#define bFM4_MFS5_I2C_FCR_FLD                     *((volatile  uint8_t *)(0x4270A294UL))
#define bFM_MFS5_I2C_FCR_FLST                     *((volatile  uint8_t *)(0x4270A298UL))
#define bFM4_MFS5_I2C_FCR_FLST                    *((volatile  uint8_t *)(0x4270A298UL))
#define bFM_MFS5_I2C_FCR_FSEL                     *((volatile  uint8_t *)(0x4270A2A0UL))
#define bFM4_MFS5_I2C_FCR_FSEL                    *((volatile  uint8_t *)(0x4270A2A0UL))
#define bFM_MFS5_I2C_FCR_FTIE                     *((volatile  uint8_t *)(0x4270A2A4UL))
#define bFM4_MFS5_I2C_FCR_FTIE                    *((volatile  uint8_t *)(0x4270A2A4UL))
#define bFM_MFS5_I2C_FCR_FDRQ                     *((volatile  uint8_t *)(0x4270A2A8UL))
#define bFM4_MFS5_I2C_FCR_FDRQ                    *((volatile  uint8_t *)(0x4270A2A8UL))
#define bFM_MFS5_I2C_FCR_FRIIE                    *((volatile  uint8_t *)(0x4270A2ACUL))
#define bFM4_MFS5_I2C_FCR_FRIIE                   *((volatile  uint8_t *)(0x4270A2ACUL))
#define bFM_MFS5_I2C_FCR_FLSTE                    *((volatile  uint8_t *)(0x4270A2B0UL))
#define bFM4_MFS5_I2C_FCR_FLSTE                   *((volatile  uint8_t *)(0x4270A2B0UL))

#define bFM_MFS5_I2C_IBCR_INT                     *((volatile  uint8_t *)(0x4270A020UL))
#define bFM4_MFS5_I2C_IBCR_INT                    *((volatile  uint8_t *)(0x4270A020UL))
#define bFM_MFS5_I2C_IBCR_BER                     *((volatile  uint8_t *)(0x4270A024UL))
#define bFM4_MFS5_I2C_IBCR_BER                    *((volatile  uint8_t *)(0x4270A024UL))
#define bFM_MFS5_I2C_IBCR_INTE                    *((volatile  uint8_t *)(0x4270A028UL))
#define bFM4_MFS5_I2C_IBCR_INTE                   *((volatile  uint8_t *)(0x4270A028UL))
#define bFM_MFS5_I2C_IBCR_CNDE                    *((volatile  uint8_t *)(0x4270A02CUL))
#define bFM4_MFS5_I2C_IBCR_CNDE                   *((volatile  uint8_t *)(0x4270A02CUL))
#define bFM_MFS5_I2C_IBCR_WSEL                    *((volatile  uint8_t *)(0x4270A030UL))
#define bFM4_MFS5_I2C_IBCR_WSEL                   *((volatile  uint8_t *)(0x4270A030UL))
#define bFM_MFS5_I2C_IBCR_ACKE                    *((volatile  uint8_t *)(0x4270A034UL))
#define bFM4_MFS5_I2C_IBCR_ACKE                   *((volatile  uint8_t *)(0x4270A034UL))
#define bFM_MFS5_I2C_IBCR_ACT_SCC                 *((volatile  uint8_t *)(0x4270A038UL))
#define bFM4_MFS5_I2C_IBCR_ACT_SCC                *((volatile  uint8_t *)(0x4270A038UL))
#define bFM_MFS5_I2C_IBCR_MSS                     *((volatile  uint8_t *)(0x4270A03CUL))
#define bFM4_MFS5_I2C_IBCR_MSS                    *((volatile  uint8_t *)(0x4270A03CUL))

#define bFM_MFS5_I2C_IBSR_BB                      *((volatile  uint8_t *)(0x4270A080UL))
#define bFM4_MFS5_I2C_IBSR_BB                     *((volatile  uint8_t *)(0x4270A080UL))
#define bFM_MFS5_I2C_IBSR_SPC                     *((volatile  uint8_t *)(0x4270A084UL))
#define bFM4_MFS5_I2C_IBSR_SPC                    *((volatile  uint8_t *)(0x4270A084UL))
#define bFM_MFS5_I2C_IBSR_RSC                     *((volatile  uint8_t *)(0x4270A088UL))
#define bFM4_MFS5_I2C_IBSR_RSC                    *((volatile  uint8_t *)(0x4270A088UL))
#define bFM_MFS5_I2C_IBSR_AL                      *((volatile  uint8_t *)(0x4270A08CUL))
#define bFM4_MFS5_I2C_IBSR_AL                     *((volatile  uint8_t *)(0x4270A08CUL))
#define bFM_MFS5_I2C_IBSR_TRX                     *((volatile  uint8_t *)(0x4270A090UL))
#define bFM4_MFS5_I2C_IBSR_TRX                    *((volatile  uint8_t *)(0x4270A090UL))
#define bFM_MFS5_I2C_IBSR_RSA                     *((volatile  uint8_t *)(0x4270A094UL))
#define bFM4_MFS5_I2C_IBSR_RSA                    *((volatile  uint8_t *)(0x4270A094UL))
#define bFM_MFS5_I2C_IBSR_RACK                    *((volatile  uint8_t *)(0x4270A098UL))
#define bFM4_MFS5_I2C_IBSR_RACK                   *((volatile  uint8_t *)(0x4270A098UL))
#define bFM_MFS5_I2C_IBSR_FBT                     *((volatile  uint8_t *)(0x4270A09CUL))
#define bFM4_MFS5_I2C_IBSR_FBT                    *((volatile  uint8_t *)(0x4270A09CUL))

#define bFM_MFS5_I2C_ISBA_SAEN                    *((volatile  uint8_t *)(0x4270A21CUL))
#define bFM4_MFS5_I2C_ISBA_SAEN                   *((volatile  uint8_t *)(0x4270A21CUL))

#define bFM_MFS5_I2C_ISMK_EN                      *((volatile  uint8_t *)(0x4270A23CUL))
#define bFM4_MFS5_I2C_ISMK_EN                     *((volatile  uint8_t *)(0x4270A23CUL))

#define bFM_MFS5_I2C_SMR_TIE                      *((volatile  uint8_t *)(0x4270A008UL))
#define bFM4_MFS5_I2C_SMR_TIE                     *((volatile  uint8_t *)(0x4270A008UL))
#define bFM_MFS5_I2C_SMR_RIE                      *((volatile  uint8_t *)(0x4270A00CUL))
#define bFM4_MFS5_I2C_SMR_RIE                     *((volatile  uint8_t *)(0x4270A00CUL))

#define bFM_MFS5_I2C_SSR_TBI                      *((volatile  uint8_t *)(0x4270A0A0UL))
#define bFM4_MFS5_I2C_SSR_TBI                     *((volatile  uint8_t *)(0x4270A0A0UL))
#define bFM_MFS5_I2C_SSR_TDRE                     *((volatile  uint8_t *)(0x4270A0A4UL))
#define bFM4_MFS5_I2C_SSR_TDRE                    *((volatile  uint8_t *)(0x4270A0A4UL))
#define bFM_MFS5_I2C_SSR_RDRF                     *((volatile  uint8_t *)(0x4270A0A8UL))
#define bFM4_MFS5_I2C_SSR_RDRF                    *((volatile  uint8_t *)(0x4270A0A8UL))
#define bFM_MFS5_I2C_SSR_ORE                      *((volatile  uint8_t *)(0x4270A0ACUL))
#define bFM4_MFS5_I2C_SSR_ORE                     *((volatile  uint8_t *)(0x4270A0ACUL))
#define bFM_MFS5_I2C_SSR_TBIE                     *((volatile  uint8_t *)(0x4270A0B0UL))
#define bFM4_MFS5_I2C_SSR_TBIE                    *((volatile  uint8_t *)(0x4270A0B0UL))
#define bFM_MFS5_I2C_SSR_DMA                      *((volatile  uint8_t *)(0x4270A0B4UL))
#define bFM4_MFS5_I2C_SSR_DMA                     *((volatile  uint8_t *)(0x4270A0B4UL))
#define bFM_MFS5_I2C_SSR_TSET                     *((volatile  uint8_t *)(0x4270A0B8UL))
#define bFM4_MFS5_I2C_SSR_TSET                    *((volatile  uint8_t *)(0x4270A0B8UL))
#define bFM_MFS5_I2C_SSR_REC                      *((volatile  uint8_t *)(0x4270A0BCUL))
#define bFM4_MFS5_I2C_SSR_REC                     *((volatile  uint8_t *)(0x4270A0BCUL))

#define bFM_MFS5_LIN_BGR_EXT                      *((volatile  uint8_t *)(0x4270A1BCUL))
#define bFM4_MFS5_LIN_BGR_EXT                     *((volatile  uint8_t *)(0x4270A1BCUL))

#define bFM_MFS5_LIN_ESCR_LBIE                    *((volatile  uint8_t *)(0x4270A090UL))
#define bFM4_MFS5_LIN_ESCR_LBIE                   *((volatile  uint8_t *)(0x4270A090UL))
#define bFM_MFS5_LIN_ESCR_ESBL                    *((volatile  uint8_t *)(0x4270A098UL))
#define bFM4_MFS5_LIN_ESCR_ESBL                   *((volatile  uint8_t *)(0x4270A098UL))

#define bFM_MFS5_LIN_FCR_FE1                      *((volatile  uint8_t *)(0x4270A280UL))
#define bFM4_MFS5_LIN_FCR_FE1                     *((volatile  uint8_t *)(0x4270A280UL))
#define bFM_MFS5_LIN_FCR_FE2                      *((volatile  uint8_t *)(0x4270A284UL))
#define bFM4_MFS5_LIN_FCR_FE2                     *((volatile  uint8_t *)(0x4270A284UL))
#define bFM_MFS5_LIN_FCR_FCL1                     *((volatile  uint8_t *)(0x4270A288UL))
#define bFM4_MFS5_LIN_FCR_FCL1                    *((volatile  uint8_t *)(0x4270A288UL))
#define bFM_MFS5_LIN_FCR_FCL2                     *((volatile  uint8_t *)(0x4270A28CUL))
#define bFM4_MFS5_LIN_FCR_FCL2                    *((volatile  uint8_t *)(0x4270A28CUL))
#define bFM_MFS5_LIN_FCR_FSET                     *((volatile  uint8_t *)(0x4270A290UL))
#define bFM4_MFS5_LIN_FCR_FSET                    *((volatile  uint8_t *)(0x4270A290UL))
#define bFM_MFS5_LIN_FCR_FLD                      *((volatile  uint8_t *)(0x4270A294UL))
#define bFM4_MFS5_LIN_FCR_FLD                     *((volatile  uint8_t *)(0x4270A294UL))
#define bFM_MFS5_LIN_FCR_FLST                     *((volatile  uint8_t *)(0x4270A298UL))
#define bFM4_MFS5_LIN_FCR_FLST                    *((volatile  uint8_t *)(0x4270A298UL))
#define bFM_MFS5_LIN_FCR_FSEL                     *((volatile  uint8_t *)(0x4270A2A0UL))
#define bFM4_MFS5_LIN_FCR_FSEL                    *((volatile  uint8_t *)(0x4270A2A0UL))
#define bFM_MFS5_LIN_FCR_FTIE                     *((volatile  uint8_t *)(0x4270A2A4UL))
#define bFM4_MFS5_LIN_FCR_FTIE                    *((volatile  uint8_t *)(0x4270A2A4UL))
#define bFM_MFS5_LIN_FCR_FDRQ                     *((volatile  uint8_t *)(0x4270A2A8UL))
#define bFM4_MFS5_LIN_FCR_FDRQ                    *((volatile  uint8_t *)(0x4270A2A8UL))
#define bFM_MFS5_LIN_FCR_FRIIE                    *((volatile  uint8_t *)(0x4270A2ACUL))
#define bFM4_MFS5_LIN_FCR_FRIIE                   *((volatile  uint8_t *)(0x4270A2ACUL))
#define bFM_MFS5_LIN_FCR_FLSTE                    *((volatile  uint8_t *)(0x4270A2B0UL))
#define bFM4_MFS5_LIN_FCR_FLSTE                   *((volatile  uint8_t *)(0x4270A2B0UL))

#define bFM_MFS5_LIN_SCR_TXE                      *((volatile  uint8_t *)(0x4270A020UL))
#define bFM4_MFS5_LIN_SCR_TXE                     *((volatile  uint8_t *)(0x4270A020UL))
#define bFM_MFS5_LIN_SCR_RXE                      *((volatile  uint8_t *)(0x4270A024UL))
#define bFM4_MFS5_LIN_SCR_RXE                     *((volatile  uint8_t *)(0x4270A024UL))
#define bFM_MFS5_LIN_SCR_TBIE                     *((volatile  uint8_t *)(0x4270A028UL))
#define bFM4_MFS5_LIN_SCR_TBIE                    *((volatile  uint8_t *)(0x4270A028UL))
#define bFM_MFS5_LIN_SCR_TIE                      *((volatile  uint8_t *)(0x4270A02CUL))
#define bFM4_MFS5_LIN_SCR_TIE                     *((volatile  uint8_t *)(0x4270A02CUL))
#define bFM_MFS5_LIN_SCR_RIE                      *((volatile  uint8_t *)(0x4270A030UL))
#define bFM4_MFS5_LIN_SCR_RIE                     *((volatile  uint8_t *)(0x4270A030UL))
#define bFM_MFS5_LIN_SCR_LBR                      *((volatile  uint8_t *)(0x4270A034UL))
#define bFM4_MFS5_LIN_SCR_LBR                     *((volatile  uint8_t *)(0x4270A034UL))
#define bFM_MFS5_LIN_SCR_MS                       *((volatile  uint8_t *)(0x4270A038UL))
#define bFM4_MFS5_LIN_SCR_MS                      *((volatile  uint8_t *)(0x4270A038UL))
#define bFM_MFS5_LIN_SCR_UPCL                     *((volatile  uint8_t *)(0x4270A03CUL))
#define bFM4_MFS5_LIN_SCR_UPCL                    *((volatile  uint8_t *)(0x4270A03CUL))

#define bFM_MFS5_LIN_SMR_SOE                      *((volatile  uint8_t *)(0x4270A000UL))
#define bFM4_MFS5_LIN_SMR_SOE                     *((volatile  uint8_t *)(0x4270A000UL))
#define bFM_MFS5_LIN_SMR_SBL                      *((volatile  uint8_t *)(0x4270A00CUL))
#define bFM4_MFS5_LIN_SMR_SBL                     *((volatile  uint8_t *)(0x4270A00CUL))
#define bFM_MFS5_LIN_SMR_WUCR                     *((volatile  uint8_t *)(0x4270A010UL))
#define bFM4_MFS5_LIN_SMR_WUCR                    *((volatile  uint8_t *)(0x4270A010UL))

#define bFM_MFS5_LIN_SSR_TBI                      *((volatile  uint8_t *)(0x4270A0A0UL))
#define bFM4_MFS5_LIN_SSR_TBI                     *((volatile  uint8_t *)(0x4270A0A0UL))
#define bFM_MFS5_LIN_SSR_TDRE                     *((volatile  uint8_t *)(0x4270A0A4UL))
#define bFM4_MFS5_LIN_SSR_TDRE                    *((volatile  uint8_t *)(0x4270A0A4UL))
#define bFM_MFS5_LIN_SSR_RDRF                     *((volatile  uint8_t *)(0x4270A0A8UL))
#define bFM4_MFS5_LIN_SSR_RDRF                    *((volatile  uint8_t *)(0x4270A0A8UL))
#define bFM_MFS5_LIN_SSR_ORE                      *((volatile  uint8_t *)(0x4270A0ACUL))
#define bFM4_MFS5_LIN_SSR_ORE                     *((volatile  uint8_t *)(0x4270A0ACUL))
#define bFM_MFS5_LIN_SSR_FRE                      *((volatile  uint8_t *)(0x4270A0B0UL))
#define bFM4_MFS5_LIN_SSR_FRE                     *((volatile  uint8_t *)(0x4270A0B0UL))
#define bFM_MFS5_LIN_SSR_LBD                      *((volatile  uint8_t *)(0x4270A0B4UL))
#define bFM4_MFS5_LIN_SSR_LBD                     *((volatile  uint8_t *)(0x4270A0B4UL))
#define bFM_MFS5_LIN_SSR_REC                      *((volatile  uint8_t *)(0x4270A0BCUL))
#define bFM4_MFS5_LIN_SSR_REC                     *((volatile  uint8_t *)(0x4270A0BCUL))

#define bFM_MFS5_UART_BGR_EXT                     *((volatile  uint8_t *)(0x4270A1BCUL))
#define bFM4_MFS5_UART_BGR_EXT                    *((volatile  uint8_t *)(0x4270A1BCUL))

#define bFM_MFS5_UART_ESCR_P                      *((volatile  uint8_t *)(0x4270A08CUL))
#define bFM4_MFS5_UART_ESCR_P                     *((volatile  uint8_t *)(0x4270A08CUL))
#define bFM_MFS5_UART_ESCR_PEN                    *((volatile  uint8_t *)(0x4270A090UL))
#define bFM4_MFS5_UART_ESCR_PEN                   *((volatile  uint8_t *)(0x4270A090UL))
#define bFM_MFS5_UART_ESCR_INV                    *((volatile  uint8_t *)(0x4270A094UL))
#define bFM4_MFS5_UART_ESCR_INV                   *((volatile  uint8_t *)(0x4270A094UL))
#define bFM_MFS5_UART_ESCR_ESBL                   *((volatile  uint8_t *)(0x4270A098UL))
#define bFM4_MFS5_UART_ESCR_ESBL                  *((volatile  uint8_t *)(0x4270A098UL))
#define bFM_MFS5_UART_ESCR_FLWEN                  *((volatile  uint8_t *)(0x4270A09CUL))
#define bFM4_MFS5_UART_ESCR_FLWEN                 *((volatile  uint8_t *)(0x4270A09CUL))

#define bFM_MFS5_UART_FCR_FE1                     *((volatile  uint8_t *)(0x4270A280UL))
#define bFM4_MFS5_UART_FCR_FE1                    *((volatile  uint8_t *)(0x4270A280UL))
#define bFM_MFS5_UART_FCR_FE2                     *((volatile  uint8_t *)(0x4270A284UL))
#define bFM4_MFS5_UART_FCR_FE2                    *((volatile  uint8_t *)(0x4270A284UL))
#define bFM_MFS5_UART_FCR_FCL1                    *((volatile  uint8_t *)(0x4270A288UL))
#define bFM4_MFS5_UART_FCR_FCL1                   *((volatile  uint8_t *)(0x4270A288UL))
#define bFM_MFS5_UART_FCR_FCL2                    *((volatile  uint8_t *)(0x4270A28CUL))
#define bFM4_MFS5_UART_FCR_FCL2                   *((volatile  uint8_t *)(0x4270A28CUL))
#define bFM_MFS5_UART_FCR_FSET                    *((volatile  uint8_t *)(0x4270A290UL))
#define bFM4_MFS5_UART_FCR_FSET                   *((volatile  uint8_t *)(0x4270A290UL))
#define bFM_MFS5_UART_FCR_FLD                     *((volatile  uint8_t *)(0x4270A294UL))
#define bFM4_MFS5_UART_FCR_FLD                    *((volatile  uint8_t *)(0x4270A294UL))
#define bFM_MFS5_UART_FCR_FLST                    *((volatile  uint8_t *)(0x4270A298UL))
#define bFM4_MFS5_UART_FCR_FLST                   *((volatile  uint8_t *)(0x4270A298UL))
#define bFM_MFS5_UART_FCR_FSEL                    *((volatile  uint8_t *)(0x4270A2A0UL))
#define bFM4_MFS5_UART_FCR_FSEL                   *((volatile  uint8_t *)(0x4270A2A0UL))
#define bFM_MFS5_UART_FCR_FTIE                    *((volatile  uint8_t *)(0x4270A2A4UL))
#define bFM4_MFS5_UART_FCR_FTIE                   *((volatile  uint8_t *)(0x4270A2A4UL))
#define bFM_MFS5_UART_FCR_FDRQ                    *((volatile  uint8_t *)(0x4270A2A8UL))
#define bFM4_MFS5_UART_FCR_FDRQ                   *((volatile  uint8_t *)(0x4270A2A8UL))
#define bFM_MFS5_UART_FCR_FRIIE                   *((volatile  uint8_t *)(0x4270A2ACUL))
#define bFM4_MFS5_UART_FCR_FRIIE                  *((volatile  uint8_t *)(0x4270A2ACUL))
#define bFM_MFS5_UART_FCR_FLSTE                   *((volatile  uint8_t *)(0x4270A2B0UL))
#define bFM4_MFS5_UART_FCR_FLSTE                  *((volatile  uint8_t *)(0x4270A2B0UL))

#define bFM_MFS5_UART_SCR_TXE                     *((volatile  uint8_t *)(0x4270A020UL))
#define bFM4_MFS5_UART_SCR_TXE                    *((volatile  uint8_t *)(0x4270A020UL))
#define bFM_MFS5_UART_SCR_RXE                     *((volatile  uint8_t *)(0x4270A024UL))
#define bFM4_MFS5_UART_SCR_RXE                    *((volatile  uint8_t *)(0x4270A024UL))
#define bFM_MFS5_UART_SCR_TBIE                    *((volatile  uint8_t *)(0x4270A028UL))
#define bFM4_MFS5_UART_SCR_TBIE                   *((volatile  uint8_t *)(0x4270A028UL))
#define bFM_MFS5_UART_SCR_TIE                     *((volatile  uint8_t *)(0x4270A02CUL))
#define bFM4_MFS5_UART_SCR_TIE                    *((volatile  uint8_t *)(0x4270A02CUL))
#define bFM_MFS5_UART_SCR_RIE                     *((volatile  uint8_t *)(0x4270A030UL))
#define bFM4_MFS5_UART_SCR_RIE                    *((volatile  uint8_t *)(0x4270A030UL))
#define bFM_MFS5_UART_SCR_UPCL                    *((volatile  uint8_t *)(0x4270A03CUL))
#define bFM4_MFS5_UART_SCR_UPCL                   *((volatile  uint8_t *)(0x4270A03CUL))

#define bFM_MFS5_UART_SMR_SOE                     *((volatile  uint8_t *)(0x4270A000UL))
#define bFM4_MFS5_UART_SMR_SOE                    *((volatile  uint8_t *)(0x4270A000UL))
#define bFM_MFS5_UART_SMR_BDS                     *((volatile  uint8_t *)(0x4270A008UL))
#define bFM4_MFS5_UART_SMR_BDS                    *((volatile  uint8_t *)(0x4270A008UL))
#define bFM_MFS5_UART_SMR_SBL                     *((volatile  uint8_t *)(0x4270A00CUL))
#define bFM4_MFS5_UART_SMR_SBL                    *((volatile  uint8_t *)(0x4270A00CUL))

#define bFM_MFS5_UART_SSR_TBI                     *((volatile  uint8_t *)(0x4270A0A0UL))
#define bFM4_MFS5_UART_SSR_TBI                    *((volatile  uint8_t *)(0x4270A0A0UL))
#define bFM_MFS5_UART_SSR_TDRE                    *((volatile  uint8_t *)(0x4270A0A4UL))
#define bFM4_MFS5_UART_SSR_TDRE                   *((volatile  uint8_t *)(0x4270A0A4UL))
#define bFM_MFS5_UART_SSR_RDRF                    *((volatile  uint8_t *)(0x4270A0A8UL))
#define bFM4_MFS5_UART_SSR_RDRF                   *((volatile  uint8_t *)(0x4270A0A8UL))
#define bFM_MFS5_UART_SSR_ORE                     *((volatile  uint8_t *)(0x4270A0ACUL))
#define bFM4_MFS5_UART_SSR_ORE                    *((volatile  uint8_t *)(0x4270A0ACUL))
#define bFM_MFS5_UART_SSR_FRE                     *((volatile  uint8_t *)(0x4270A0B0UL))
#define bFM4_MFS5_UART_SSR_FRE                    *((volatile  uint8_t *)(0x4270A0B0UL))
#define bFM_MFS5_UART_SSR_PE                      *((volatile  uint8_t *)(0x4270A0B4UL))
#define bFM4_MFS5_UART_SSR_PE                     *((volatile  uint8_t *)(0x4270A0B4UL))
#define bFM_MFS5_UART_SSR_REC                     *((volatile  uint8_t *)(0x4270A0BCUL))
#define bFM4_MFS5_UART_SSR_REC                    *((volatile  uint8_t *)(0x4270A0BCUL))


/*******************************************************************************
* MFS Registers MFS6
*   Bitband Section
*******************************************************************************/
#define bFM_MFS6_CSIO_ESCR_CSFE                   *((volatile  uint8_t *)(0x4270C094UL))
#define bFM4_MFS6_CSIO_ESCR_CSFE                  *((volatile  uint8_t *)(0x4270C094UL))
#define bFM_MFS6_CSIO_ESCR_L3                     *((volatile  uint8_t *)(0x4270C098UL))
#define bFM4_MFS6_CSIO_ESCR_L3                    *((volatile  uint8_t *)(0x4270C098UL))
#define bFM_MFS6_CSIO_ESCR_SOP                    *((volatile  uint8_t *)(0x4270C09CUL))
#define bFM4_MFS6_CSIO_ESCR_SOP                   *((volatile  uint8_t *)(0x4270C09CUL))

#define bFM_MFS6_CSIO_FCR_FE1                     *((volatile  uint8_t *)(0x4270C280UL))
#define bFM4_MFS6_CSIO_FCR_FE1                    *((volatile  uint8_t *)(0x4270C280UL))
#define bFM_MFS6_CSIO_FCR_FE2                     *((volatile  uint8_t *)(0x4270C284UL))
#define bFM4_MFS6_CSIO_FCR_FE2                    *((volatile  uint8_t *)(0x4270C284UL))
#define bFM_MFS6_CSIO_FCR_FCL1                    *((volatile  uint8_t *)(0x4270C288UL))
#define bFM4_MFS6_CSIO_FCR_FCL1                   *((volatile  uint8_t *)(0x4270C288UL))
#define bFM_MFS6_CSIO_FCR_FCL2                    *((volatile  uint8_t *)(0x4270C28CUL))
#define bFM4_MFS6_CSIO_FCR_FCL2                   *((volatile  uint8_t *)(0x4270C28CUL))
#define bFM_MFS6_CSIO_FCR_FSET                    *((volatile  uint8_t *)(0x4270C290UL))
#define bFM4_MFS6_CSIO_FCR_FSET                   *((volatile  uint8_t *)(0x4270C290UL))
#define bFM_MFS6_CSIO_FCR_FLD                     *((volatile  uint8_t *)(0x4270C294UL))
#define bFM4_MFS6_CSIO_FCR_FLD                    *((volatile  uint8_t *)(0x4270C294UL))
#define bFM_MFS6_CSIO_FCR_FLST                    *((volatile  uint8_t *)(0x4270C298UL))
#define bFM4_MFS6_CSIO_FCR_FLST                   *((volatile  uint8_t *)(0x4270C298UL))
#define bFM_MFS6_CSIO_FCR_FSEL                    *((volatile  uint8_t *)(0x4270C2A0UL))
#define bFM4_MFS6_CSIO_FCR_FSEL                   *((volatile  uint8_t *)(0x4270C2A0UL))
#define bFM_MFS6_CSIO_FCR_FTIE                    *((volatile  uint8_t *)(0x4270C2A4UL))
#define bFM4_MFS6_CSIO_FCR_FTIE                   *((volatile  uint8_t *)(0x4270C2A4UL))
#define bFM_MFS6_CSIO_FCR_FDRQ                    *((volatile  uint8_t *)(0x4270C2A8UL))
#define bFM4_MFS6_CSIO_FCR_FDRQ                   *((volatile  uint8_t *)(0x4270C2A8UL))
#define bFM_MFS6_CSIO_FCR_FRIIE                   *((volatile  uint8_t *)(0x4270C2ACUL))
#define bFM4_MFS6_CSIO_FCR_FRIIE                  *((volatile  uint8_t *)(0x4270C2ACUL))
#define bFM_MFS6_CSIO_FCR_FLSTE                   *((volatile  uint8_t *)(0x4270C2B0UL))
#define bFM4_MFS6_CSIO_FCR_FLSTE                  *((volatile  uint8_t *)(0x4270C2B0UL))

#define bFM_MFS6_CSIO_SACSR_TMRE                  *((volatile  uint8_t *)(0x4270C480UL))
#define bFM4_MFS6_CSIO_SACSR_TMRE                 *((volatile  uint8_t *)(0x4270C480UL))
#define bFM_MFS6_CSIO_SACSR_TSYNE                 *((volatile  uint8_t *)(0x4270C498UL))
#define bFM4_MFS6_CSIO_SACSR_TSYNE                *((volatile  uint8_t *)(0x4270C498UL))
#define bFM_MFS6_CSIO_SACSR_TINTE                 *((volatile  uint8_t *)(0x4270C49CUL))
#define bFM4_MFS6_CSIO_SACSR_TINTE                *((volatile  uint8_t *)(0x4270C49CUL))
#define bFM_MFS6_CSIO_SACSR_TINT                  *((volatile  uint8_t *)(0x4270C4A0UL))
#define bFM4_MFS6_CSIO_SACSR_TINT                 *((volatile  uint8_t *)(0x4270C4A0UL))
#define bFM_MFS6_CSIO_SACSR_CSE                   *((volatile  uint8_t *)(0x4270C4ACUL))
#define bFM4_MFS6_CSIO_SACSR_CSE                  *((volatile  uint8_t *)(0x4270C4ACUL))
#define bFM_MFS6_CSIO_SACSR_CSEIE                 *((volatile  uint8_t *)(0x4270C4B0UL))
#define bFM4_MFS6_CSIO_SACSR_CSEIE                *((volatile  uint8_t *)(0x4270C4B0UL))
#define bFM_MFS6_CSIO_SACSR_TBEEN                 *((volatile  uint8_t *)(0x4270C4B4UL))
#define bFM4_MFS6_CSIO_SACSR_TBEEN                *((volatile  uint8_t *)(0x4270C4B4UL))

#define bFM_MFS6_CSIO_SCR_TXE                     *((volatile  uint8_t *)(0x4270C020UL))
#define bFM4_MFS6_CSIO_SCR_TXE                    *((volatile  uint8_t *)(0x4270C020UL))
#define bFM_MFS6_CSIO_SCR_RXE                     *((volatile  uint8_t *)(0x4270C024UL))
#define bFM4_MFS6_CSIO_SCR_RXE                    *((volatile  uint8_t *)(0x4270C024UL))
#define bFM_MFS6_CSIO_SCR_TBIE                    *((volatile  uint8_t *)(0x4270C028UL))
#define bFM4_MFS6_CSIO_SCR_TBIE                   *((volatile  uint8_t *)(0x4270C028UL))
#define bFM_MFS6_CSIO_SCR_TIE                     *((volatile  uint8_t *)(0x4270C02CUL))
#define bFM4_MFS6_CSIO_SCR_TIE                    *((volatile  uint8_t *)(0x4270C02CUL))
#define bFM_MFS6_CSIO_SCR_RIE                     *((volatile  uint8_t *)(0x4270C030UL))
#define bFM4_MFS6_CSIO_SCR_RIE                    *((volatile  uint8_t *)(0x4270C030UL))
#define bFM_MFS6_CSIO_SCR_SPI                     *((volatile  uint8_t *)(0x4270C034UL))
#define bFM4_MFS6_CSIO_SCR_SPI                    *((volatile  uint8_t *)(0x4270C034UL))
#define bFM_MFS6_CSIO_SCR_MS                      *((volatile  uint8_t *)(0x4270C038UL))
#define bFM4_MFS6_CSIO_SCR_MS                     *((volatile  uint8_t *)(0x4270C038UL))
#define bFM_MFS6_CSIO_SCR_UPCL                    *((volatile  uint8_t *)(0x4270C03CUL))
#define bFM4_MFS6_CSIO_SCR_UPCL                   *((volatile  uint8_t *)(0x4270C03CUL))

#define bFM_MFS6_CSIO_SCSCR_CSOE                  *((volatile  uint8_t *)(0x4270C600UL))
#define bFM4_MFS6_CSIO_SCSCR_CSOE                 *((volatile  uint8_t *)(0x4270C600UL))
#define bFM_MFS6_CSIO_SCSCR_CSEN0                 *((volatile  uint8_t *)(0x4270C604UL))
#define bFM4_MFS6_CSIO_SCSCR_CSEN0                *((volatile  uint8_t *)(0x4270C604UL))
#define bFM_MFS6_CSIO_SCSCR_CSEN1                 *((volatile  uint8_t *)(0x4270C608UL))
#define bFM4_MFS6_CSIO_SCSCR_CSEN1                *((volatile  uint8_t *)(0x4270C608UL))
#define bFM_MFS6_CSIO_SCSCR_CSEN2                 *((volatile  uint8_t *)(0x4270C60CUL))
#define bFM4_MFS6_CSIO_SCSCR_CSEN2                *((volatile  uint8_t *)(0x4270C60CUL))
#define bFM_MFS6_CSIO_SCSCR_CSEN3                 *((volatile  uint8_t *)(0x4270C610UL))
#define bFM4_MFS6_CSIO_SCSCR_CSEN3                *((volatile  uint8_t *)(0x4270C610UL))
#define bFM_MFS6_CSIO_SCSCR_CSLVL                 *((volatile  uint8_t *)(0x4270C614UL))
#define bFM4_MFS6_CSIO_SCSCR_CSLVL                *((volatile  uint8_t *)(0x4270C614UL))
#define bFM_MFS6_CSIO_SCSCR_SCAM                  *((volatile  uint8_t *)(0x4270C624UL))
#define bFM4_MFS6_CSIO_SCSCR_SCAM                 *((volatile  uint8_t *)(0x4270C624UL))

#define bFM_MFS6_CSIO_SCSFR0_CS1SPI               *((volatile  uint8_t *)(0x4270C694UL))
#define bFM4_MFS6_CSIO_SCSFR0_CS1SPI              *((volatile  uint8_t *)(0x4270C694UL))
#define bFM_MFS6_CSIO_SCSFR0_CS1SCINV             *((volatile  uint8_t *)(0x4270C698UL))
#define bFM4_MFS6_CSIO_SCSFR0_CS1SCINV            *((volatile  uint8_t *)(0x4270C698UL))
#define bFM_MFS6_CSIO_SCSFR0_CS1CSLVL             *((volatile  uint8_t *)(0x4270C69CUL))
#define bFM4_MFS6_CSIO_SCSFR0_CS1CSLVL            *((volatile  uint8_t *)(0x4270C69CUL))

#define bFM_MFS6_CSIO_SCSFR1_CS2SPI               *((volatile  uint8_t *)(0x4270C6B4UL))
#define bFM4_MFS6_CSIO_SCSFR1_CS2SPI              *((volatile  uint8_t *)(0x4270C6B4UL))
#define bFM_MFS6_CSIO_SCSFR1_CS2SCINV             *((volatile  uint8_t *)(0x4270C6B8UL))
#define bFM4_MFS6_CSIO_SCSFR1_CS2SCINV            *((volatile  uint8_t *)(0x4270C6B8UL))
#define bFM_MFS6_CSIO_SCSFR1_CS2CSLVL             *((volatile  uint8_t *)(0x4270C6BCUL))
#define bFM4_MFS6_CSIO_SCSFR1_CS2CSLVL            *((volatile  uint8_t *)(0x4270C6BCUL))

#define bFM_MFS6_CSIO_SCSFR2_CS3SPI               *((volatile  uint8_t *)(0x4270C714UL))
#define bFM4_MFS6_CSIO_SCSFR2_CS3SPI              *((volatile  uint8_t *)(0x4270C714UL))
#define bFM_MFS6_CSIO_SCSFR2_CS3SCINV             *((volatile  uint8_t *)(0x4270C718UL))
#define bFM4_MFS6_CSIO_SCSFR2_CS3SCINV            *((volatile  uint8_t *)(0x4270C718UL))
#define bFM_MFS6_CSIO_SCSFR2_CS3CSLVL             *((volatile  uint8_t *)(0x4270C71CUL))
#define bFM4_MFS6_CSIO_SCSFR2_CS3CSLVL            *((volatile  uint8_t *)(0x4270C71CUL))

#define bFM_MFS6_CSIO_SMR_SOE                     *((volatile  uint8_t *)(0x4270C000UL))
#define bFM4_MFS6_CSIO_SMR_SOE                    *((volatile  uint8_t *)(0x4270C000UL))
#define bFM_MFS6_CSIO_SMR_SCKE                    *((volatile  uint8_t *)(0x4270C004UL))
#define bFM4_MFS6_CSIO_SMR_SCKE                   *((volatile  uint8_t *)(0x4270C004UL))
#define bFM_MFS6_CSIO_SMR_BDS                     *((volatile  uint8_t *)(0x4270C008UL))
#define bFM4_MFS6_CSIO_SMR_BDS                    *((volatile  uint8_t *)(0x4270C008UL))
#define bFM_MFS6_CSIO_SMR_SCINV                   *((volatile  uint8_t *)(0x4270C00CUL))
#define bFM4_MFS6_CSIO_SMR_SCINV                  *((volatile  uint8_t *)(0x4270C00CUL))

#define bFM_MFS6_CSIO_SSR_TBI                     *((volatile  uint8_t *)(0x4270C0A0UL))
#define bFM4_MFS6_CSIO_SSR_TBI                    *((volatile  uint8_t *)(0x4270C0A0UL))
#define bFM_MFS6_CSIO_SSR_TDRE                    *((volatile  uint8_t *)(0x4270C0A4UL))
#define bFM4_MFS6_CSIO_SSR_TDRE                   *((volatile  uint8_t *)(0x4270C0A4UL))
#define bFM_MFS6_CSIO_SSR_RDRF                    *((volatile  uint8_t *)(0x4270C0A8UL))
#define bFM4_MFS6_CSIO_SSR_RDRF                   *((volatile  uint8_t *)(0x4270C0A8UL))
#define bFM_MFS6_CSIO_SSR_ORE                     *((volatile  uint8_t *)(0x4270C0ACUL))
#define bFM4_MFS6_CSIO_SSR_ORE                    *((volatile  uint8_t *)(0x4270C0ACUL))
#define bFM_MFS6_CSIO_SSR_AWC                     *((volatile  uint8_t *)(0x4270C0B0UL))
#define bFM4_MFS6_CSIO_SSR_AWC                    *((volatile  uint8_t *)(0x4270C0B0UL))
#define bFM_MFS6_CSIO_SSR_REC                     *((volatile  uint8_t *)(0x4270C0BCUL))
#define bFM4_MFS6_CSIO_SSR_REC                    *((volatile  uint8_t *)(0x4270C0BCUL))

#define bFM_MFS6_I2C_EIBCR_BEC                    *((volatile  uint8_t *)(0x4270C3A0UL))
#define bFM4_MFS6_I2C_EIBCR_BEC                   *((volatile  uint8_t *)(0x4270C3A0UL))
#define bFM_MFS6_I2C_EIBCR_SOCE                   *((volatile  uint8_t *)(0x4270C3A4UL))
#define bFM4_MFS6_I2C_EIBCR_SOCE                  *((volatile  uint8_t *)(0x4270C3A4UL))
#define bFM_MFS6_I2C_EIBCR_SCLC                   *((volatile  uint8_t *)(0x4270C3A8UL))
#define bFM4_MFS6_I2C_EIBCR_SCLC                  *((volatile  uint8_t *)(0x4270C3A8UL))
#define bFM_MFS6_I2C_EIBCR_SDAC                   *((volatile  uint8_t *)(0x4270C3ACUL))
#define bFM4_MFS6_I2C_EIBCR_SDAC                  *((volatile  uint8_t *)(0x4270C3ACUL))
#define bFM_MFS6_I2C_EIBCR_SCLS                   *((volatile  uint8_t *)(0x4270C3B0UL))
#define bFM4_MFS6_I2C_EIBCR_SCLS                  *((volatile  uint8_t *)(0x4270C3B0UL))
#define bFM_MFS6_I2C_EIBCR_SDAS                   *((volatile  uint8_t *)(0x4270C3B4UL))
#define bFM4_MFS6_I2C_EIBCR_SDAS                  *((volatile  uint8_t *)(0x4270C3B4UL))

#define bFM_MFS6_I2C_FCR_FE1                      *((volatile  uint8_t *)(0x4270C280UL))
#define bFM4_MFS6_I2C_FCR_FE1                     *((volatile  uint8_t *)(0x4270C280UL))
#define bFM_MFS6_I2C_FCR_FE2                      *((volatile  uint8_t *)(0x4270C284UL))
#define bFM4_MFS6_I2C_FCR_FE2                     *((volatile  uint8_t *)(0x4270C284UL))
#define bFM_MFS6_I2C_FCR_FCL1                     *((volatile  uint8_t *)(0x4270C288UL))
#define bFM4_MFS6_I2C_FCR_FCL1                    *((volatile  uint8_t *)(0x4270C288UL))
#define bFM_MFS6_I2C_FCR_FCL2                     *((volatile  uint8_t *)(0x4270C28CUL))
#define bFM4_MFS6_I2C_FCR_FCL2                    *((volatile  uint8_t *)(0x4270C28CUL))
#define bFM_MFS6_I2C_FCR_FSET                     *((volatile  uint8_t *)(0x4270C290UL))
#define bFM4_MFS6_I2C_FCR_FSET                    *((volatile  uint8_t *)(0x4270C290UL))
#define bFM_MFS6_I2C_FCR_FLD                      *((volatile  uint8_t *)(0x4270C294UL))
#define bFM4_MFS6_I2C_FCR_FLD                     *((volatile  uint8_t *)(0x4270C294UL))
#define bFM_MFS6_I2C_FCR_FLST                     *((volatile  uint8_t *)(0x4270C298UL))
#define bFM4_MFS6_I2C_FCR_FLST                    *((volatile  uint8_t *)(0x4270C298UL))
#define bFM_MFS6_I2C_FCR_FSEL                     *((volatile  uint8_t *)(0x4270C2A0UL))
#define bFM4_MFS6_I2C_FCR_FSEL                    *((volatile  uint8_t *)(0x4270C2A0UL))
#define bFM_MFS6_I2C_FCR_FTIE                     *((volatile  uint8_t *)(0x4270C2A4UL))
#define bFM4_MFS6_I2C_FCR_FTIE                    *((volatile  uint8_t *)(0x4270C2A4UL))
#define bFM_MFS6_I2C_FCR_FDRQ                     *((volatile  uint8_t *)(0x4270C2A8UL))
#define bFM4_MFS6_I2C_FCR_FDRQ                    *((volatile  uint8_t *)(0x4270C2A8UL))
#define bFM_MFS6_I2C_FCR_FRIIE                    *((volatile  uint8_t *)(0x4270C2ACUL))
#define bFM4_MFS6_I2C_FCR_FRIIE                   *((volatile  uint8_t *)(0x4270C2ACUL))
#define bFM_MFS6_I2C_FCR_FLSTE                    *((volatile  uint8_t *)(0x4270C2B0UL))
#define bFM4_MFS6_I2C_FCR_FLSTE                   *((volatile  uint8_t *)(0x4270C2B0UL))

#define bFM_MFS6_I2C_IBCR_INT                     *((volatile  uint8_t *)(0x4270C020UL))
#define bFM4_MFS6_I2C_IBCR_INT                    *((volatile  uint8_t *)(0x4270C020UL))
#define bFM_MFS6_I2C_IBCR_BER                     *((volatile  uint8_t *)(0x4270C024UL))
#define bFM4_MFS6_I2C_IBCR_BER                    *((volatile  uint8_t *)(0x4270C024UL))
#define bFM_MFS6_I2C_IBCR_INTE                    *((volatile  uint8_t *)(0x4270C028UL))
#define bFM4_MFS6_I2C_IBCR_INTE                   *((volatile  uint8_t *)(0x4270C028UL))
#define bFM_MFS6_I2C_IBCR_CNDE                    *((volatile  uint8_t *)(0x4270C02CUL))
#define bFM4_MFS6_I2C_IBCR_CNDE                   *((volatile  uint8_t *)(0x4270C02CUL))
#define bFM_MFS6_I2C_IBCR_WSEL                    *((volatile  uint8_t *)(0x4270C030UL))
#define bFM4_MFS6_I2C_IBCR_WSEL                   *((volatile  uint8_t *)(0x4270C030UL))
#define bFM_MFS6_I2C_IBCR_ACKE                    *((volatile  uint8_t *)(0x4270C034UL))
#define bFM4_MFS6_I2C_IBCR_ACKE                   *((volatile  uint8_t *)(0x4270C034UL))
#define bFM_MFS6_I2C_IBCR_ACT_SCC                 *((volatile  uint8_t *)(0x4270C038UL))
#define bFM4_MFS6_I2C_IBCR_ACT_SCC                *((volatile  uint8_t *)(0x4270C038UL))
#define bFM_MFS6_I2C_IBCR_MSS                     *((volatile  uint8_t *)(0x4270C03CUL))
#define bFM4_MFS6_I2C_IBCR_MSS                    *((volatile  uint8_t *)(0x4270C03CUL))

#define bFM_MFS6_I2C_IBSR_BB                      *((volatile  uint8_t *)(0x4270C080UL))
#define bFM4_MFS6_I2C_IBSR_BB                     *((volatile  uint8_t *)(0x4270C080UL))
#define bFM_MFS6_I2C_IBSR_SPC                     *((volatile  uint8_t *)(0x4270C084UL))
#define bFM4_MFS6_I2C_IBSR_SPC                    *((volatile  uint8_t *)(0x4270C084UL))
#define bFM_MFS6_I2C_IBSR_RSC                     *((volatile  uint8_t *)(0x4270C088UL))
#define bFM4_MFS6_I2C_IBSR_RSC                    *((volatile  uint8_t *)(0x4270C088UL))
#define bFM_MFS6_I2C_IBSR_AL                      *((volatile  uint8_t *)(0x4270C08CUL))
#define bFM4_MFS6_I2C_IBSR_AL                     *((volatile  uint8_t *)(0x4270C08CUL))
#define bFM_MFS6_I2C_IBSR_TRX                     *((volatile  uint8_t *)(0x4270C090UL))
#define bFM4_MFS6_I2C_IBSR_TRX                    *((volatile  uint8_t *)(0x4270C090UL))
#define bFM_MFS6_I2C_IBSR_RSA                     *((volatile  uint8_t *)(0x4270C094UL))
#define bFM4_MFS6_I2C_IBSR_RSA                    *((volatile  uint8_t *)(0x4270C094UL))
#define bFM_MFS6_I2C_IBSR_RACK                    *((volatile  uint8_t *)(0x4270C098UL))
#define bFM4_MFS6_I2C_IBSR_RACK                   *((volatile  uint8_t *)(0x4270C098UL))
#define bFM_MFS6_I2C_IBSR_FBT                     *((volatile  uint8_t *)(0x4270C09CUL))
#define bFM4_MFS6_I2C_IBSR_FBT                    *((volatile  uint8_t *)(0x4270C09CUL))

#define bFM_MFS6_I2C_ISBA_SAEN                    *((volatile  uint8_t *)(0x4270C21CUL))
#define bFM4_MFS6_I2C_ISBA_SAEN                   *((volatile  uint8_t *)(0x4270C21CUL))

#define bFM_MFS6_I2C_ISMK_EN                      *((volatile  uint8_t *)(0x4270C23CUL))
#define bFM4_MFS6_I2C_ISMK_EN                     *((volatile  uint8_t *)(0x4270C23CUL))

#define bFM_MFS6_I2C_SMR_TIE                      *((volatile  uint8_t *)(0x4270C008UL))
#define bFM4_MFS6_I2C_SMR_TIE                     *((volatile  uint8_t *)(0x4270C008UL))
#define bFM_MFS6_I2C_SMR_RIE                      *((volatile  uint8_t *)(0x4270C00CUL))
#define bFM4_MFS6_I2C_SMR_RIE                     *((volatile  uint8_t *)(0x4270C00CUL))

#define bFM_MFS6_I2C_SSR_TBI                      *((volatile  uint8_t *)(0x4270C0A0UL))
#define bFM4_MFS6_I2C_SSR_TBI                     *((volatile  uint8_t *)(0x4270C0A0UL))
#define bFM_MFS6_I2C_SSR_TDRE                     *((volatile  uint8_t *)(0x4270C0A4UL))
#define bFM4_MFS6_I2C_SSR_TDRE                    *((volatile  uint8_t *)(0x4270C0A4UL))
#define bFM_MFS6_I2C_SSR_RDRF                     *((volatile  uint8_t *)(0x4270C0A8UL))
#define bFM4_MFS6_I2C_SSR_RDRF                    *((volatile  uint8_t *)(0x4270C0A8UL))
#define bFM_MFS6_I2C_SSR_ORE                      *((volatile  uint8_t *)(0x4270C0ACUL))
#define bFM4_MFS6_I2C_SSR_ORE                     *((volatile  uint8_t *)(0x4270C0ACUL))
#define bFM_MFS6_I2C_SSR_TBIE                     *((volatile  uint8_t *)(0x4270C0B0UL))
#define bFM4_MFS6_I2C_SSR_TBIE                    *((volatile  uint8_t *)(0x4270C0B0UL))
#define bFM_MFS6_I2C_SSR_DMA                      *((volatile  uint8_t *)(0x4270C0B4UL))
#define bFM4_MFS6_I2C_SSR_DMA                     *((volatile  uint8_t *)(0x4270C0B4UL))
#define bFM_MFS6_I2C_SSR_TSET                     *((volatile  uint8_t *)(0x4270C0B8UL))
#define bFM4_MFS6_I2C_SSR_TSET                    *((volatile  uint8_t *)(0x4270C0B8UL))
#define bFM_MFS6_I2C_SSR_REC                      *((volatile  uint8_t *)(0x4270C0BCUL))
#define bFM4_MFS6_I2C_SSR_REC                     *((volatile  uint8_t *)(0x4270C0BCUL))

#define bFM_MFS6_LIN_BGR_EXT                      *((volatile  uint8_t *)(0x4270C1BCUL))
#define bFM4_MFS6_LIN_BGR_EXT                     *((volatile  uint8_t *)(0x4270C1BCUL))

#define bFM_MFS6_LIN_ESCR_LBIE                    *((volatile  uint8_t *)(0x4270C090UL))
#define bFM4_MFS6_LIN_ESCR_LBIE                   *((volatile  uint8_t *)(0x4270C090UL))
#define bFM_MFS6_LIN_ESCR_ESBL                    *((volatile  uint8_t *)(0x4270C098UL))
#define bFM4_MFS6_LIN_ESCR_ESBL                   *((volatile  uint8_t *)(0x4270C098UL))

#define bFM_MFS6_LIN_FCR_FE1                      *((volatile  uint8_t *)(0x4270C280UL))
#define bFM4_MFS6_LIN_FCR_FE1                     *((volatile  uint8_t *)(0x4270C280UL))
#define bFM_MFS6_LIN_FCR_FE2                      *((volatile  uint8_t *)(0x4270C284UL))
#define bFM4_MFS6_LIN_FCR_FE2                     *((volatile  uint8_t *)(0x4270C284UL))
#define bFM_MFS6_LIN_FCR_FCL1                     *((volatile  uint8_t *)(0x4270C288UL))
#define bFM4_MFS6_LIN_FCR_FCL1                    *((volatile  uint8_t *)(0x4270C288UL))
#define bFM_MFS6_LIN_FCR_FCL2                     *((volatile  uint8_t *)(0x4270C28CUL))
#define bFM4_MFS6_LIN_FCR_FCL2                    *((volatile  uint8_t *)(0x4270C28CUL))
#define bFM_MFS6_LIN_FCR_FSET                     *((volatile  uint8_t *)(0x4270C290UL))
#define bFM4_MFS6_LIN_FCR_FSET                    *((volatile  uint8_t *)(0x4270C290UL))
#define bFM_MFS6_LIN_FCR_FLD                      *((volatile  uint8_t *)(0x4270C294UL))
#define bFM4_MFS6_LIN_FCR_FLD                     *((volatile  uint8_t *)(0x4270C294UL))
#define bFM_MFS6_LIN_FCR_FLST                     *((volatile  uint8_t *)(0x4270C298UL))
#define bFM4_MFS6_LIN_FCR_FLST                    *((volatile  uint8_t *)(0x4270C298UL))
#define bFM_MFS6_LIN_FCR_FSEL                     *((volatile  uint8_t *)(0x4270C2A0UL))
#define bFM4_MFS6_LIN_FCR_FSEL                    *((volatile  uint8_t *)(0x4270C2A0UL))
#define bFM_MFS6_LIN_FCR_FTIE                     *((volatile  uint8_t *)(0x4270C2A4UL))
#define bFM4_MFS6_LIN_FCR_FTIE                    *((volatile  uint8_t *)(0x4270C2A4UL))
#define bFM_MFS6_LIN_FCR_FDRQ                     *((volatile  uint8_t *)(0x4270C2A8UL))
#define bFM4_MFS6_LIN_FCR_FDRQ                    *((volatile  uint8_t *)(0x4270C2A8UL))
#define bFM_MFS6_LIN_FCR_FRIIE                    *((volatile  uint8_t *)(0x4270C2ACUL))
#define bFM4_MFS6_LIN_FCR_FRIIE                   *((volatile  uint8_t *)(0x4270C2ACUL))
#define bFM_MFS6_LIN_FCR_FLSTE                    *((volatile  uint8_t *)(0x4270C2B0UL))
#define bFM4_MFS6_LIN_FCR_FLSTE                   *((volatile  uint8_t *)(0x4270C2B0UL))

#define bFM_MFS6_LIN_SCR_TXE                      *((volatile  uint8_t *)(0x4270C020UL))
#define bFM4_MFS6_LIN_SCR_TXE                     *((volatile  uint8_t *)(0x4270C020UL))
#define bFM_MFS6_LIN_SCR_RXE                      *((volatile  uint8_t *)(0x4270C024UL))
#define bFM4_MFS6_LIN_SCR_RXE                     *((volatile  uint8_t *)(0x4270C024UL))
#define bFM_MFS6_LIN_SCR_TBIE                     *((volatile  uint8_t *)(0x4270C028UL))
#define bFM4_MFS6_LIN_SCR_TBIE                    *((volatile  uint8_t *)(0x4270C028UL))
#define bFM_MFS6_LIN_SCR_TIE                      *((volatile  uint8_t *)(0x4270C02CUL))
#define bFM4_MFS6_LIN_SCR_TIE                     *((volatile  uint8_t *)(0x4270C02CUL))
#define bFM_MFS6_LIN_SCR_RIE                      *((volatile  uint8_t *)(0x4270C030UL))
#define bFM4_MFS6_LIN_SCR_RIE                     *((volatile  uint8_t *)(0x4270C030UL))
#define bFM_MFS6_LIN_SCR_LBR                      *((volatile  uint8_t *)(0x4270C034UL))
#define bFM4_MFS6_LIN_SCR_LBR                     *((volatile  uint8_t *)(0x4270C034UL))
#define bFM_MFS6_LIN_SCR_MS                       *((volatile  uint8_t *)(0x4270C038UL))
#define bFM4_MFS6_LIN_SCR_MS                      *((volatile  uint8_t *)(0x4270C038UL))
#define bFM_MFS6_LIN_SCR_UPCL                     *((volatile  uint8_t *)(0x4270C03CUL))
#define bFM4_MFS6_LIN_SCR_UPCL                    *((volatile  uint8_t *)(0x4270C03CUL))

#define bFM_MFS6_LIN_SMR_SOE                      *((volatile  uint8_t *)(0x4270C000UL))
#define bFM4_MFS6_LIN_SMR_SOE                     *((volatile  uint8_t *)(0x4270C000UL))
#define bFM_MFS6_LIN_SMR_SBL                      *((volatile  uint8_t *)(0x4270C00CUL))
#define bFM4_MFS6_LIN_SMR_SBL                     *((volatile  uint8_t *)(0x4270C00CUL))
#define bFM_MFS6_LIN_SMR_WUCR                     *((volatile  uint8_t *)(0x4270C010UL))
#define bFM4_MFS6_LIN_SMR_WUCR                    *((volatile  uint8_t *)(0x4270C010UL))

#define bFM_MFS6_LIN_SSR_TBI                      *((volatile  uint8_t *)(0x4270C0A0UL))
#define bFM4_MFS6_LIN_SSR_TBI                     *((volatile  uint8_t *)(0x4270C0A0UL))
#define bFM_MFS6_LIN_SSR_TDRE                     *((volatile  uint8_t *)(0x4270C0A4UL))
#define bFM4_MFS6_LIN_SSR_TDRE                    *((volatile  uint8_t *)(0x4270C0A4UL))
#define bFM_MFS6_LIN_SSR_RDRF                     *((volatile  uint8_t *)(0x4270C0A8UL))
#define bFM4_MFS6_LIN_SSR_RDRF                    *((volatile  uint8_t *)(0x4270C0A8UL))
#define bFM_MFS6_LIN_SSR_ORE                      *((volatile  uint8_t *)(0x4270C0ACUL))
#define bFM4_MFS6_LIN_SSR_ORE                     *((volatile  uint8_t *)(0x4270C0ACUL))
#define bFM_MFS6_LIN_SSR_FRE                      *((volatile  uint8_t *)(0x4270C0B0UL))
#define bFM4_MFS6_LIN_SSR_FRE                     *((volatile  uint8_t *)(0x4270C0B0UL))
#define bFM_MFS6_LIN_SSR_LBD                      *((volatile  uint8_t *)(0x4270C0B4UL))
#define bFM4_MFS6_LIN_SSR_LBD                     *((volatile  uint8_t *)(0x4270C0B4UL))
#define bFM_MFS6_LIN_SSR_REC                      *((volatile  uint8_t *)(0x4270C0BCUL))
#define bFM4_MFS6_LIN_SSR_REC                     *((volatile  uint8_t *)(0x4270C0BCUL))

#define bFM_MFS6_UART_BGR_EXT                     *((volatile  uint8_t *)(0x4270C1BCUL))
#define bFM4_MFS6_UART_BGR_EXT                    *((volatile  uint8_t *)(0x4270C1BCUL))

#define bFM_MFS6_UART_ESCR_P                      *((volatile  uint8_t *)(0x4270C08CUL))
#define bFM4_MFS6_UART_ESCR_P                     *((volatile  uint8_t *)(0x4270C08CUL))
#define bFM_MFS6_UART_ESCR_PEN                    *((volatile  uint8_t *)(0x4270C090UL))
#define bFM4_MFS6_UART_ESCR_PEN                   *((volatile  uint8_t *)(0x4270C090UL))
#define bFM_MFS6_UART_ESCR_INV                    *((volatile  uint8_t *)(0x4270C094UL))
#define bFM4_MFS6_UART_ESCR_INV                   *((volatile  uint8_t *)(0x4270C094UL))
#define bFM_MFS6_UART_ESCR_ESBL                   *((volatile  uint8_t *)(0x4270C098UL))
#define bFM4_MFS6_UART_ESCR_ESBL                  *((volatile  uint8_t *)(0x4270C098UL))
#define bFM_MFS6_UART_ESCR_FLWEN                  *((volatile  uint8_t *)(0x4270C09CUL))
#define bFM4_MFS6_UART_ESCR_FLWEN                 *((volatile  uint8_t *)(0x4270C09CUL))

#define bFM_MFS6_UART_FCR_FE1                     *((volatile  uint8_t *)(0x4270C280UL))
#define bFM4_MFS6_UART_FCR_FE1                    *((volatile  uint8_t *)(0x4270C280UL))
#define bFM_MFS6_UART_FCR_FE2                     *((volatile  uint8_t *)(0x4270C284UL))
#define bFM4_MFS6_UART_FCR_FE2                    *((volatile  uint8_t *)(0x4270C284UL))
#define bFM_MFS6_UART_FCR_FCL1                    *((volatile  uint8_t *)(0x4270C288UL))
#define bFM4_MFS6_UART_FCR_FCL1                   *((volatile  uint8_t *)(0x4270C288UL))
#define bFM_MFS6_UART_FCR_FCL2                    *((volatile  uint8_t *)(0x4270C28CUL))
#define bFM4_MFS6_UART_FCR_FCL2                   *((volatile  uint8_t *)(0x4270C28CUL))
#define bFM_MFS6_UART_FCR_FSET                    *((volatile  uint8_t *)(0x4270C290UL))
#define bFM4_MFS6_UART_FCR_FSET                   *((volatile  uint8_t *)(0x4270C290UL))
#define bFM_MFS6_UART_FCR_FLD                     *((volatile  uint8_t *)(0x4270C294UL))
#define bFM4_MFS6_UART_FCR_FLD                    *((volatile  uint8_t *)(0x4270C294UL))
#define bFM_MFS6_UART_FCR_FLST                    *((volatile  uint8_t *)(0x4270C298UL))
#define bFM4_MFS6_UART_FCR_FLST                   *((volatile  uint8_t *)(0x4270C298UL))
#define bFM_MFS6_UART_FCR_FSEL                    *((volatile  uint8_t *)(0x4270C2A0UL))
#define bFM4_MFS6_UART_FCR_FSEL                   *((volatile  uint8_t *)(0x4270C2A0UL))
#define bFM_MFS6_UART_FCR_FTIE                    *((volatile  uint8_t *)(0x4270C2A4UL))
#define bFM4_MFS6_UART_FCR_FTIE                   *((volatile  uint8_t *)(0x4270C2A4UL))
#define bFM_MFS6_UART_FCR_FDRQ                    *((volatile  uint8_t *)(0x4270C2A8UL))
#define bFM4_MFS6_UART_FCR_FDRQ                   *((volatile  uint8_t *)(0x4270C2A8UL))
#define bFM_MFS6_UART_FCR_FRIIE                   *((volatile  uint8_t *)(0x4270C2ACUL))
#define bFM4_MFS6_UART_FCR_FRIIE                  *((volatile  uint8_t *)(0x4270C2ACUL))
#define bFM_MFS6_UART_FCR_FLSTE                   *((volatile  uint8_t *)(0x4270C2B0UL))
#define bFM4_MFS6_UART_FCR_FLSTE                  *((volatile  uint8_t *)(0x4270C2B0UL))

#define bFM_MFS6_UART_SCR_TXE                     *((volatile  uint8_t *)(0x4270C020UL))
#define bFM4_MFS6_UART_SCR_TXE                    *((volatile  uint8_t *)(0x4270C020UL))
#define bFM_MFS6_UART_SCR_RXE                     *((volatile  uint8_t *)(0x4270C024UL))
#define bFM4_MFS6_UART_SCR_RXE                    *((volatile  uint8_t *)(0x4270C024UL))
#define bFM_MFS6_UART_SCR_TBIE                    *((volatile  uint8_t *)(0x4270C028UL))
#define bFM4_MFS6_UART_SCR_TBIE                   *((volatile  uint8_t *)(0x4270C028UL))
#define bFM_MFS6_UART_SCR_TIE                     *((volatile  uint8_t *)(0x4270C02CUL))
#define bFM4_MFS6_UART_SCR_TIE                    *((volatile  uint8_t *)(0x4270C02CUL))
#define bFM_MFS6_UART_SCR_RIE                     *((volatile  uint8_t *)(0x4270C030UL))
#define bFM4_MFS6_UART_SCR_RIE                    *((volatile  uint8_t *)(0x4270C030UL))
#define bFM_MFS6_UART_SCR_UPCL                    *((volatile  uint8_t *)(0x4270C03CUL))
#define bFM4_MFS6_UART_SCR_UPCL                   *((volatile  uint8_t *)(0x4270C03CUL))

#define bFM_MFS6_UART_SMR_SOE                     *((volatile  uint8_t *)(0x4270C000UL))
#define bFM4_MFS6_UART_SMR_SOE                    *((volatile  uint8_t *)(0x4270C000UL))
#define bFM_MFS6_UART_SMR_BDS                     *((volatile  uint8_t *)(0x4270C008UL))
#define bFM4_MFS6_UART_SMR_BDS                    *((volatile  uint8_t *)(0x4270C008UL))
#define bFM_MFS6_UART_SMR_SBL                     *((volatile  uint8_t *)(0x4270C00CUL))
#define bFM4_MFS6_UART_SMR_SBL                    *((volatile  uint8_t *)(0x4270C00CUL))

#define bFM_MFS6_UART_SSR_TBI                     *((volatile  uint8_t *)(0x4270C0A0UL))
#define bFM4_MFS6_UART_SSR_TBI                    *((volatile  uint8_t *)(0x4270C0A0UL))
#define bFM_MFS6_UART_SSR_TDRE                    *((volatile  uint8_t *)(0x4270C0A4UL))
#define bFM4_MFS6_UART_SSR_TDRE                   *((volatile  uint8_t *)(0x4270C0A4UL))
#define bFM_MFS6_UART_SSR_RDRF                    *((volatile  uint8_t *)(0x4270C0A8UL))
#define bFM4_MFS6_UART_SSR_RDRF                   *((volatile  uint8_t *)(0x4270C0A8UL))
#define bFM_MFS6_UART_SSR_ORE                     *((volatile  uint8_t *)(0x4270C0ACUL))
#define bFM4_MFS6_UART_SSR_ORE                    *((volatile  uint8_t *)(0x4270C0ACUL))
#define bFM_MFS6_UART_SSR_FRE                     *((volatile  uint8_t *)(0x4270C0B0UL))
#define bFM4_MFS6_UART_SSR_FRE                    *((volatile  uint8_t *)(0x4270C0B0UL))
#define bFM_MFS6_UART_SSR_PE                      *((volatile  uint8_t *)(0x4270C0B4UL))
#define bFM4_MFS6_UART_SSR_PE                     *((volatile  uint8_t *)(0x4270C0B4UL))
#define bFM_MFS6_UART_SSR_REC                     *((volatile  uint8_t *)(0x4270C0BCUL))
#define bFM4_MFS6_UART_SSR_REC                    *((volatile  uint8_t *)(0x4270C0BCUL))


/*******************************************************************************
* MFS Registers MFS7
*   Bitband Section
*******************************************************************************/
#define bFM_MFS7_CSIO_ESCR_CSFE                   *((volatile  uint8_t *)(0x4270E094UL))
#define bFM4_MFS7_CSIO_ESCR_CSFE                  *((volatile  uint8_t *)(0x4270E094UL))
#define bFM_MFS7_CSIO_ESCR_L3                     *((volatile  uint8_t *)(0x4270E098UL))
#define bFM4_MFS7_CSIO_ESCR_L3                    *((volatile  uint8_t *)(0x4270E098UL))
#define bFM_MFS7_CSIO_ESCR_SOP                    *((volatile  uint8_t *)(0x4270E09CUL))
#define bFM4_MFS7_CSIO_ESCR_SOP                   *((volatile  uint8_t *)(0x4270E09CUL))

#define bFM_MFS7_CSIO_FCR_FE1                     *((volatile  uint8_t *)(0x4270E280UL))
#define bFM4_MFS7_CSIO_FCR_FE1                    *((volatile  uint8_t *)(0x4270E280UL))
#define bFM_MFS7_CSIO_FCR_FE2                     *((volatile  uint8_t *)(0x4270E284UL))
#define bFM4_MFS7_CSIO_FCR_FE2                    *((volatile  uint8_t *)(0x4270E284UL))
#define bFM_MFS7_CSIO_FCR_FCL1                    *((volatile  uint8_t *)(0x4270E288UL))
#define bFM4_MFS7_CSIO_FCR_FCL1                   *((volatile  uint8_t *)(0x4270E288UL))
#define bFM_MFS7_CSIO_FCR_FCL2                    *((volatile  uint8_t *)(0x4270E28CUL))
#define bFM4_MFS7_CSIO_FCR_FCL2                   *((volatile  uint8_t *)(0x4270E28CUL))
#define bFM_MFS7_CSIO_FCR_FSET                    *((volatile  uint8_t *)(0x4270E290UL))
#define bFM4_MFS7_CSIO_FCR_FSET                   *((volatile  uint8_t *)(0x4270E290UL))
#define bFM_MFS7_CSIO_FCR_FLD                     *((volatile  uint8_t *)(0x4270E294UL))
#define bFM4_MFS7_CSIO_FCR_FLD                    *((volatile  uint8_t *)(0x4270E294UL))
#define bFM_MFS7_CSIO_FCR_FLST                    *((volatile  uint8_t *)(0x4270E298UL))
#define bFM4_MFS7_CSIO_FCR_FLST                   *((volatile  uint8_t *)(0x4270E298UL))
#define bFM_MFS7_CSIO_FCR_FSEL                    *((volatile  uint8_t *)(0x4270E2A0UL))
#define bFM4_MFS7_CSIO_FCR_FSEL                   *((volatile  uint8_t *)(0x4270E2A0UL))
#define bFM_MFS7_CSIO_FCR_FTIE                    *((volatile  uint8_t *)(0x4270E2A4UL))
#define bFM4_MFS7_CSIO_FCR_FTIE                   *((volatile  uint8_t *)(0x4270E2A4UL))
#define bFM_MFS7_CSIO_FCR_FDRQ                    *((volatile  uint8_t *)(0x4270E2A8UL))
#define bFM4_MFS7_CSIO_FCR_FDRQ                   *((volatile  uint8_t *)(0x4270E2A8UL))
#define bFM_MFS7_CSIO_FCR_FRIIE                   *((volatile  uint8_t *)(0x4270E2ACUL))
#define bFM4_MFS7_CSIO_FCR_FRIIE                  *((volatile  uint8_t *)(0x4270E2ACUL))
#define bFM_MFS7_CSIO_FCR_FLSTE                   *((volatile  uint8_t *)(0x4270E2B0UL))
#define bFM4_MFS7_CSIO_FCR_FLSTE                  *((volatile  uint8_t *)(0x4270E2B0UL))

#define bFM_MFS7_CSIO_SACSR_TMRE                  *((volatile  uint8_t *)(0x4270E480UL))
#define bFM4_MFS7_CSIO_SACSR_TMRE                 *((volatile  uint8_t *)(0x4270E480UL))
#define bFM_MFS7_CSIO_SACSR_TSYNE                 *((volatile  uint8_t *)(0x4270E498UL))
#define bFM4_MFS7_CSIO_SACSR_TSYNE                *((volatile  uint8_t *)(0x4270E498UL))
#define bFM_MFS7_CSIO_SACSR_TINTE                 *((volatile  uint8_t *)(0x4270E49CUL))
#define bFM4_MFS7_CSIO_SACSR_TINTE                *((volatile  uint8_t *)(0x4270E49CUL))
#define bFM_MFS7_CSIO_SACSR_TINT                  *((volatile  uint8_t *)(0x4270E4A0UL))
#define bFM4_MFS7_CSIO_SACSR_TINT                 *((volatile  uint8_t *)(0x4270E4A0UL))
#define bFM_MFS7_CSIO_SACSR_CSE                   *((volatile  uint8_t *)(0x4270E4ACUL))
#define bFM4_MFS7_CSIO_SACSR_CSE                  *((volatile  uint8_t *)(0x4270E4ACUL))
#define bFM_MFS7_CSIO_SACSR_CSEIE                 *((volatile  uint8_t *)(0x4270E4B0UL))
#define bFM4_MFS7_CSIO_SACSR_CSEIE                *((volatile  uint8_t *)(0x4270E4B0UL))
#define bFM_MFS7_CSIO_SACSR_TBEEN                 *((volatile  uint8_t *)(0x4270E4B4UL))
#define bFM4_MFS7_CSIO_SACSR_TBEEN                *((volatile  uint8_t *)(0x4270E4B4UL))

#define bFM_MFS7_CSIO_SCR_TXE                     *((volatile  uint8_t *)(0x4270E020UL))
#define bFM4_MFS7_CSIO_SCR_TXE                    *((volatile  uint8_t *)(0x4270E020UL))
#define bFM_MFS7_CSIO_SCR_RXE                     *((volatile  uint8_t *)(0x4270E024UL))
#define bFM4_MFS7_CSIO_SCR_RXE                    *((volatile  uint8_t *)(0x4270E024UL))
#define bFM_MFS7_CSIO_SCR_TBIE                    *((volatile  uint8_t *)(0x4270E028UL))
#define bFM4_MFS7_CSIO_SCR_TBIE                   *((volatile  uint8_t *)(0x4270E028UL))
#define bFM_MFS7_CSIO_SCR_TIE                     *((volatile  uint8_t *)(0x4270E02CUL))
#define bFM4_MFS7_CSIO_SCR_TIE                    *((volatile  uint8_t *)(0x4270E02CUL))
#define bFM_MFS7_CSIO_SCR_RIE                     *((volatile  uint8_t *)(0x4270E030UL))
#define bFM4_MFS7_CSIO_SCR_RIE                    *((volatile  uint8_t *)(0x4270E030UL))
#define bFM_MFS7_CSIO_SCR_SPI                     *((volatile  uint8_t *)(0x4270E034UL))
#define bFM4_MFS7_CSIO_SCR_SPI                    *((volatile  uint8_t *)(0x4270E034UL))
#define bFM_MFS7_CSIO_SCR_MS                      *((volatile  uint8_t *)(0x4270E038UL))
#define bFM4_MFS7_CSIO_SCR_MS                     *((volatile  uint8_t *)(0x4270E038UL))
#define bFM_MFS7_CSIO_SCR_UPCL                    *((volatile  uint8_t *)(0x4270E03CUL))
#define bFM4_MFS7_CSIO_SCR_UPCL                   *((volatile  uint8_t *)(0x4270E03CUL))

#define bFM_MFS7_CSIO_SCSCR_CSOE                  *((volatile  uint8_t *)(0x4270E600UL))
#define bFM4_MFS7_CSIO_SCSCR_CSOE                 *((volatile  uint8_t *)(0x4270E600UL))
#define bFM_MFS7_CSIO_SCSCR_CSEN0                 *((volatile  uint8_t *)(0x4270E604UL))
#define bFM4_MFS7_CSIO_SCSCR_CSEN0                *((volatile  uint8_t *)(0x4270E604UL))
#define bFM_MFS7_CSIO_SCSCR_CSEN1                 *((volatile  uint8_t *)(0x4270E608UL))
#define bFM4_MFS7_CSIO_SCSCR_CSEN1                *((volatile  uint8_t *)(0x4270E608UL))
#define bFM_MFS7_CSIO_SCSCR_CSEN2                 *((volatile  uint8_t *)(0x4270E60CUL))
#define bFM4_MFS7_CSIO_SCSCR_CSEN2                *((volatile  uint8_t *)(0x4270E60CUL))
#define bFM_MFS7_CSIO_SCSCR_CSEN3                 *((volatile  uint8_t *)(0x4270E610UL))
#define bFM4_MFS7_CSIO_SCSCR_CSEN3                *((volatile  uint8_t *)(0x4270E610UL))
#define bFM_MFS7_CSIO_SCSCR_CSLVL                 *((volatile  uint8_t *)(0x4270E614UL))
#define bFM4_MFS7_CSIO_SCSCR_CSLVL                *((volatile  uint8_t *)(0x4270E614UL))
#define bFM_MFS7_CSIO_SCSCR_SCAM                  *((volatile  uint8_t *)(0x4270E624UL))
#define bFM4_MFS7_CSIO_SCSCR_SCAM                 *((volatile  uint8_t *)(0x4270E624UL))

#define bFM_MFS7_CSIO_SCSFR0_CS1SPI               *((volatile  uint8_t *)(0x4270E694UL))
#define bFM4_MFS7_CSIO_SCSFR0_CS1SPI              *((volatile  uint8_t *)(0x4270E694UL))
#define bFM_MFS7_CSIO_SCSFR0_CS1SCINV             *((volatile  uint8_t *)(0x4270E698UL))
#define bFM4_MFS7_CSIO_SCSFR0_CS1SCINV            *((volatile  uint8_t *)(0x4270E698UL))
#define bFM_MFS7_CSIO_SCSFR0_CS1CSLVL             *((volatile  uint8_t *)(0x4270E69CUL))
#define bFM4_MFS7_CSIO_SCSFR0_CS1CSLVL            *((volatile  uint8_t *)(0x4270E69CUL))

#define bFM_MFS7_CSIO_SCSFR1_CS2SPI               *((volatile  uint8_t *)(0x4270E6B4UL))
#define bFM4_MFS7_CSIO_SCSFR1_CS2SPI              *((volatile  uint8_t *)(0x4270E6B4UL))
#define bFM_MFS7_CSIO_SCSFR1_CS2SCINV             *((volatile  uint8_t *)(0x4270E6B8UL))
#define bFM4_MFS7_CSIO_SCSFR1_CS2SCINV            *((volatile  uint8_t *)(0x4270E6B8UL))
#define bFM_MFS7_CSIO_SCSFR1_CS2CSLVL             *((volatile  uint8_t *)(0x4270E6BCUL))
#define bFM4_MFS7_CSIO_SCSFR1_CS2CSLVL            *((volatile  uint8_t *)(0x4270E6BCUL))

#define bFM_MFS7_CSIO_SCSFR2_CS3SPI               *((volatile  uint8_t *)(0x4270E714UL))
#define bFM4_MFS7_CSIO_SCSFR2_CS3SPI              *((volatile  uint8_t *)(0x4270E714UL))
#define bFM_MFS7_CSIO_SCSFR2_CS3SCINV             *((volatile  uint8_t *)(0x4270E718UL))
#define bFM4_MFS7_CSIO_SCSFR2_CS3SCINV            *((volatile  uint8_t *)(0x4270E718UL))
#define bFM_MFS7_CSIO_SCSFR2_CS3CSLVL             *((volatile  uint8_t *)(0x4270E71CUL))
#define bFM4_MFS7_CSIO_SCSFR2_CS3CSLVL            *((volatile  uint8_t *)(0x4270E71CUL))

#define bFM_MFS7_CSIO_SMR_SOE                     *((volatile  uint8_t *)(0x4270E000UL))
#define bFM4_MFS7_CSIO_SMR_SOE                    *((volatile  uint8_t *)(0x4270E000UL))
#define bFM_MFS7_CSIO_SMR_SCKE                    *((volatile  uint8_t *)(0x4270E004UL))
#define bFM4_MFS7_CSIO_SMR_SCKE                   *((volatile  uint8_t *)(0x4270E004UL))
#define bFM_MFS7_CSIO_SMR_BDS                     *((volatile  uint8_t *)(0x4270E008UL))
#define bFM4_MFS7_CSIO_SMR_BDS                    *((volatile  uint8_t *)(0x4270E008UL))
#define bFM_MFS7_CSIO_SMR_SCINV                   *((volatile  uint8_t *)(0x4270E00CUL))
#define bFM4_MFS7_CSIO_SMR_SCINV                  *((volatile  uint8_t *)(0x4270E00CUL))

#define bFM_MFS7_CSIO_SSR_TBI                     *((volatile  uint8_t *)(0x4270E0A0UL))
#define bFM4_MFS7_CSIO_SSR_TBI                    *((volatile  uint8_t *)(0x4270E0A0UL))
#define bFM_MFS7_CSIO_SSR_TDRE                    *((volatile  uint8_t *)(0x4270E0A4UL))
#define bFM4_MFS7_CSIO_SSR_TDRE                   *((volatile  uint8_t *)(0x4270E0A4UL))
#define bFM_MFS7_CSIO_SSR_RDRF                    *((volatile  uint8_t *)(0x4270E0A8UL))
#define bFM4_MFS7_CSIO_SSR_RDRF                   *((volatile  uint8_t *)(0x4270E0A8UL))
#define bFM_MFS7_CSIO_SSR_ORE                     *((volatile  uint8_t *)(0x4270E0ACUL))
#define bFM4_MFS7_CSIO_SSR_ORE                    *((volatile  uint8_t *)(0x4270E0ACUL))
#define bFM_MFS7_CSIO_SSR_AWC                     *((volatile  uint8_t *)(0x4270E0B0UL))
#define bFM4_MFS7_CSIO_SSR_AWC                    *((volatile  uint8_t *)(0x4270E0B0UL))
#define bFM_MFS7_CSIO_SSR_REC                     *((volatile  uint8_t *)(0x4270E0BCUL))
#define bFM4_MFS7_CSIO_SSR_REC                    *((volatile  uint8_t *)(0x4270E0BCUL))

#define bFM_MFS7_I2C_EIBCR_BEC                    *((volatile  uint8_t *)(0x4270E3A0UL))
#define bFM4_MFS7_I2C_EIBCR_BEC                   *((volatile  uint8_t *)(0x4270E3A0UL))
#define bFM_MFS7_I2C_EIBCR_SOCE                   *((volatile  uint8_t *)(0x4270E3A4UL))
#define bFM4_MFS7_I2C_EIBCR_SOCE                  *((volatile  uint8_t *)(0x4270E3A4UL))
#define bFM_MFS7_I2C_EIBCR_SCLC                   *((volatile  uint8_t *)(0x4270E3A8UL))
#define bFM4_MFS7_I2C_EIBCR_SCLC                  *((volatile  uint8_t *)(0x4270E3A8UL))
#define bFM_MFS7_I2C_EIBCR_SDAC                   *((volatile  uint8_t *)(0x4270E3ACUL))
#define bFM4_MFS7_I2C_EIBCR_SDAC                  *((volatile  uint8_t *)(0x4270E3ACUL))
#define bFM_MFS7_I2C_EIBCR_SCLS                   *((volatile  uint8_t *)(0x4270E3B0UL))
#define bFM4_MFS7_I2C_EIBCR_SCLS                  *((volatile  uint8_t *)(0x4270E3B0UL))
#define bFM_MFS7_I2C_EIBCR_SDAS                   *((volatile  uint8_t *)(0x4270E3B4UL))
#define bFM4_MFS7_I2C_EIBCR_SDAS                  *((volatile  uint8_t *)(0x4270E3B4UL))

#define bFM_MFS7_I2C_FCR_FE1                      *((volatile  uint8_t *)(0x4270E280UL))
#define bFM4_MFS7_I2C_FCR_FE1                     *((volatile  uint8_t *)(0x4270E280UL))
#define bFM_MFS7_I2C_FCR_FE2                      *((volatile  uint8_t *)(0x4270E284UL))
#define bFM4_MFS7_I2C_FCR_FE2                     *((volatile  uint8_t *)(0x4270E284UL))
#define bFM_MFS7_I2C_FCR_FCL1                     *((volatile  uint8_t *)(0x4270E288UL))
#define bFM4_MFS7_I2C_FCR_FCL1                    *((volatile  uint8_t *)(0x4270E288UL))
#define bFM_MFS7_I2C_FCR_FCL2                     *((volatile  uint8_t *)(0x4270E28CUL))
#define bFM4_MFS7_I2C_FCR_FCL2                    *((volatile  uint8_t *)(0x4270E28CUL))
#define bFM_MFS7_I2C_FCR_FSET                     *((volatile  uint8_t *)(0x4270E290UL))
#define bFM4_MFS7_I2C_FCR_FSET                    *((volatile  uint8_t *)(0x4270E290UL))
#define bFM_MFS7_I2C_FCR_FLD                      *((volatile  uint8_t *)(0x4270E294UL))
#define bFM4_MFS7_I2C_FCR_FLD                     *((volatile  uint8_t *)(0x4270E294UL))
#define bFM_MFS7_I2C_FCR_FLST                     *((volatile  uint8_t *)(0x4270E298UL))
#define bFM4_MFS7_I2C_FCR_FLST                    *((volatile  uint8_t *)(0x4270E298UL))
#define bFM_MFS7_I2C_FCR_FSEL                     *((volatile  uint8_t *)(0x4270E2A0UL))
#define bFM4_MFS7_I2C_FCR_FSEL                    *((volatile  uint8_t *)(0x4270E2A0UL))
#define bFM_MFS7_I2C_FCR_FTIE                     *((volatile  uint8_t *)(0x4270E2A4UL))
#define bFM4_MFS7_I2C_FCR_FTIE                    *((volatile  uint8_t *)(0x4270E2A4UL))
#define bFM_MFS7_I2C_FCR_FDRQ                     *((volatile  uint8_t *)(0x4270E2A8UL))
#define bFM4_MFS7_I2C_FCR_FDRQ                    *((volatile  uint8_t *)(0x4270E2A8UL))
#define bFM_MFS7_I2C_FCR_FRIIE                    *((volatile  uint8_t *)(0x4270E2ACUL))
#define bFM4_MFS7_I2C_FCR_FRIIE                   *((volatile  uint8_t *)(0x4270E2ACUL))
#define bFM_MFS7_I2C_FCR_FLSTE                    *((volatile  uint8_t *)(0x4270E2B0UL))
#define bFM4_MFS7_I2C_FCR_FLSTE                   *((volatile  uint8_t *)(0x4270E2B0UL))

#define bFM_MFS7_I2C_IBCR_INT                     *((volatile  uint8_t *)(0x4270E020UL))
#define bFM4_MFS7_I2C_IBCR_INT                    *((volatile  uint8_t *)(0x4270E020UL))
#define bFM_MFS7_I2C_IBCR_BER                     *((volatile  uint8_t *)(0x4270E024UL))
#define bFM4_MFS7_I2C_IBCR_BER                    *((volatile  uint8_t *)(0x4270E024UL))
#define bFM_MFS7_I2C_IBCR_INTE                    *((volatile  uint8_t *)(0x4270E028UL))
#define bFM4_MFS7_I2C_IBCR_INTE                   *((volatile  uint8_t *)(0x4270E028UL))
#define bFM_MFS7_I2C_IBCR_CNDE                    *((volatile  uint8_t *)(0x4270E02CUL))
#define bFM4_MFS7_I2C_IBCR_CNDE                   *((volatile  uint8_t *)(0x4270E02CUL))
#define bFM_MFS7_I2C_IBCR_WSEL                    *((volatile  uint8_t *)(0x4270E030UL))
#define bFM4_MFS7_I2C_IBCR_WSEL                   *((volatile  uint8_t *)(0x4270E030UL))
#define bFM_MFS7_I2C_IBCR_ACKE                    *((volatile  uint8_t *)(0x4270E034UL))
#define bFM4_MFS7_I2C_IBCR_ACKE                   *((volatile  uint8_t *)(0x4270E034UL))
#define bFM_MFS7_I2C_IBCR_ACT_SCC                 *((volatile  uint8_t *)(0x4270E038UL))
#define bFM4_MFS7_I2C_IBCR_ACT_SCC                *((volatile  uint8_t *)(0x4270E038UL))
#define bFM_MFS7_I2C_IBCR_MSS                     *((volatile  uint8_t *)(0x4270E03CUL))
#define bFM4_MFS7_I2C_IBCR_MSS                    *((volatile  uint8_t *)(0x4270E03CUL))

#define bFM_MFS7_I2C_IBSR_BB                      *((volatile  uint8_t *)(0x4270E080UL))
#define bFM4_MFS7_I2C_IBSR_BB                     *((volatile  uint8_t *)(0x4270E080UL))
#define bFM_MFS7_I2C_IBSR_SPC                     *((volatile  uint8_t *)(0x4270E084UL))
#define bFM4_MFS7_I2C_IBSR_SPC                    *((volatile  uint8_t *)(0x4270E084UL))
#define bFM_MFS7_I2C_IBSR_RSC                     *((volatile  uint8_t *)(0x4270E088UL))
#define bFM4_MFS7_I2C_IBSR_RSC                    *((volatile  uint8_t *)(0x4270E088UL))
#define bFM_MFS7_I2C_IBSR_AL                      *((volatile  uint8_t *)(0x4270E08CUL))
#define bFM4_MFS7_I2C_IBSR_AL                     *((volatile  uint8_t *)(0x4270E08CUL))
#define bFM_MFS7_I2C_IBSR_TRX                     *((volatile  uint8_t *)(0x4270E090UL))
#define bFM4_MFS7_I2C_IBSR_TRX                    *((volatile  uint8_t *)(0x4270E090UL))
#define bFM_MFS7_I2C_IBSR_RSA                     *((volatile  uint8_t *)(0x4270E094UL))
#define bFM4_MFS7_I2C_IBSR_RSA                    *((volatile  uint8_t *)(0x4270E094UL))
#define bFM_MFS7_I2C_IBSR_RACK                    *((volatile  uint8_t *)(0x4270E098UL))
#define bFM4_MFS7_I2C_IBSR_RACK                   *((volatile  uint8_t *)(0x4270E098UL))
#define bFM_MFS7_I2C_IBSR_FBT                     *((volatile  uint8_t *)(0x4270E09CUL))
#define bFM4_MFS7_I2C_IBSR_FBT                    *((volatile  uint8_t *)(0x4270E09CUL))

#define bFM_MFS7_I2C_ISBA_SAEN                    *((volatile  uint8_t *)(0x4270E21CUL))
#define bFM4_MFS7_I2C_ISBA_SAEN                   *((volatile  uint8_t *)(0x4270E21CUL))

#define bFM_MFS7_I2C_ISMK_EN                      *((volatile  uint8_t *)(0x4270E23CUL))
#define bFM4_MFS7_I2C_ISMK_EN                     *((volatile  uint8_t *)(0x4270E23CUL))

#define bFM_MFS7_I2C_SMR_TIE                      *((volatile  uint8_t *)(0x4270E008UL))
#define bFM4_MFS7_I2C_SMR_TIE                     *((volatile  uint8_t *)(0x4270E008UL))
#define bFM_MFS7_I2C_SMR_RIE                      *((volatile  uint8_t *)(0x4270E00CUL))
#define bFM4_MFS7_I2C_SMR_RIE                     *((volatile  uint8_t *)(0x4270E00CUL))

#define bFM_MFS7_I2C_SSR_TBI                      *((volatile  uint8_t *)(0x4270E0A0UL))
#define bFM4_MFS7_I2C_SSR_TBI                     *((volatile  uint8_t *)(0x4270E0A0UL))
#define bFM_MFS7_I2C_SSR_TDRE                     *((volatile  uint8_t *)(0x4270E0A4UL))
#define bFM4_MFS7_I2C_SSR_TDRE                    *((volatile  uint8_t *)(0x4270E0A4UL))
#define bFM_MFS7_I2C_SSR_RDRF                     *((volatile  uint8_t *)(0x4270E0A8UL))
#define bFM4_MFS7_I2C_SSR_RDRF                    *((volatile  uint8_t *)(0x4270E0A8UL))
#define bFM_MFS7_I2C_SSR_ORE                      *((volatile  uint8_t *)(0x4270E0ACUL))
#define bFM4_MFS7_I2C_SSR_ORE                     *((volatile  uint8_t *)(0x4270E0ACUL))
#define bFM_MFS7_I2C_SSR_TBIE                     *((volatile  uint8_t *)(0x4270E0B0UL))
#define bFM4_MFS7_I2C_SSR_TBIE                    *((volatile  uint8_t *)(0x4270E0B0UL))
#define bFM_MFS7_I2C_SSR_DMA                      *((volatile  uint8_t *)(0x4270E0B4UL))
#define bFM4_MFS7_I2C_SSR_DMA                     *((volatile  uint8_t *)(0x4270E0B4UL))
#define bFM_MFS7_I2C_SSR_TSET                     *((volatile  uint8_t *)(0x4270E0B8UL))
#define bFM4_MFS7_I2C_SSR_TSET                    *((volatile  uint8_t *)(0x4270E0B8UL))
#define bFM_MFS7_I2C_SSR_REC                      *((volatile  uint8_t *)(0x4270E0BCUL))
#define bFM4_MFS7_I2C_SSR_REC                     *((volatile  uint8_t *)(0x4270E0BCUL))

#define bFM_MFS7_LIN_BGR_EXT                      *((volatile  uint8_t *)(0x4270E1BCUL))
#define bFM4_MFS7_LIN_BGR_EXT                     *((volatile  uint8_t *)(0x4270E1BCUL))

#define bFM_MFS7_LIN_ESCR_LBIE                    *((volatile  uint8_t *)(0x4270E090UL))
#define bFM4_MFS7_LIN_ESCR_LBIE                   *((volatile  uint8_t *)(0x4270E090UL))
#define bFM_MFS7_LIN_ESCR_ESBL                    *((volatile  uint8_t *)(0x4270E098UL))
#define bFM4_MFS7_LIN_ESCR_ESBL                   *((volatile  uint8_t *)(0x4270E098UL))

#define bFM_MFS7_LIN_FCR_FE1                      *((volatile  uint8_t *)(0x4270E280UL))
#define bFM4_MFS7_LIN_FCR_FE1                     *((volatile  uint8_t *)(0x4270E280UL))
#define bFM_MFS7_LIN_FCR_FE2                      *((volatile  uint8_t *)(0x4270E284UL))
#define bFM4_MFS7_LIN_FCR_FE2                     *((volatile  uint8_t *)(0x4270E284UL))
#define bFM_MFS7_LIN_FCR_FCL1                     *((volatile  uint8_t *)(0x4270E288UL))
#define bFM4_MFS7_LIN_FCR_FCL1                    *((volatile  uint8_t *)(0x4270E288UL))
#define bFM_MFS7_LIN_FCR_FCL2                     *((volatile  uint8_t *)(0x4270E28CUL))
#define bFM4_MFS7_LIN_FCR_FCL2                    *((volatile  uint8_t *)(0x4270E28CUL))
#define bFM_MFS7_LIN_FCR_FSET                     *((volatile  uint8_t *)(0x4270E290UL))
#define bFM4_MFS7_LIN_FCR_FSET                    *((volatile  uint8_t *)(0x4270E290UL))
#define bFM_MFS7_LIN_FCR_FLD                      *((volatile  uint8_t *)(0x4270E294UL))
#define bFM4_MFS7_LIN_FCR_FLD                     *((volatile  uint8_t *)(0x4270E294UL))
#define bFM_MFS7_LIN_FCR_FLST                     *((volatile  uint8_t *)(0x4270E298UL))
#define bFM4_MFS7_LIN_FCR_FLST                    *((volatile  uint8_t *)(0x4270E298UL))
#define bFM_MFS7_LIN_FCR_FSEL                     *((volatile  uint8_t *)(0x4270E2A0UL))
#define bFM4_MFS7_LIN_FCR_FSEL                    *((volatile  uint8_t *)(0x4270E2A0UL))
#define bFM_MFS7_LIN_FCR_FTIE                     *((volatile  uint8_t *)(0x4270E2A4UL))
#define bFM4_MFS7_LIN_FCR_FTIE                    *((volatile  uint8_t *)(0x4270E2A4UL))
#define bFM_MFS7_LIN_FCR_FDRQ                     *((volatile  uint8_t *)(0x4270E2A8UL))
#define bFM4_MFS7_LIN_FCR_FDRQ                    *((volatile  uint8_t *)(0x4270E2A8UL))
#define bFM_MFS7_LIN_FCR_FRIIE                    *((volatile  uint8_t *)(0x4270E2ACUL))
#define bFM4_MFS7_LIN_FCR_FRIIE                   *((volatile  uint8_t *)(0x4270E2ACUL))
#define bFM_MFS7_LIN_FCR_FLSTE                    *((volatile  uint8_t *)(0x4270E2B0UL))
#define bFM4_MFS7_LIN_FCR_FLSTE                   *((volatile  uint8_t *)(0x4270E2B0UL))

#define bFM_MFS7_LIN_SCR_TXE                      *((volatile  uint8_t *)(0x4270E020UL))
#define bFM4_MFS7_LIN_SCR_TXE                     *((volatile  uint8_t *)(0x4270E020UL))
#define bFM_MFS7_LIN_SCR_RXE                      *((volatile  uint8_t *)(0x4270E024UL))
#define bFM4_MFS7_LIN_SCR_RXE                     *((volatile  uint8_t *)(0x4270E024UL))
#define bFM_MFS7_LIN_SCR_TBIE                     *((volatile  uint8_t *)(0x4270E028UL))
#define bFM4_MFS7_LIN_SCR_TBIE                    *((volatile  uint8_t *)(0x4270E028UL))
#define bFM_MFS7_LIN_SCR_TIE                      *((volatile  uint8_t *)(0x4270E02CUL))
#define bFM4_MFS7_LIN_SCR_TIE                     *((volatile  uint8_t *)(0x4270E02CUL))
#define bFM_MFS7_LIN_SCR_RIE                      *((volatile  uint8_t *)(0x4270E030UL))
#define bFM4_MFS7_LIN_SCR_RIE                     *((volatile  uint8_t *)(0x4270E030UL))
#define bFM_MFS7_LIN_SCR_LBR                      *((volatile  uint8_t *)(0x4270E034UL))
#define bFM4_MFS7_LIN_SCR_LBR                     *((volatile  uint8_t *)(0x4270E034UL))
#define bFM_MFS7_LIN_SCR_MS                       *((volatile  uint8_t *)(0x4270E038UL))
#define bFM4_MFS7_LIN_SCR_MS                      *((volatile  uint8_t *)(0x4270E038UL))
#define bFM_MFS7_LIN_SCR_UPCL                     *((volatile  uint8_t *)(0x4270E03CUL))
#define bFM4_MFS7_LIN_SCR_UPCL                    *((volatile  uint8_t *)(0x4270E03CUL))

#define bFM_MFS7_LIN_SMR_SOE                      *((volatile  uint8_t *)(0x4270E000UL))
#define bFM4_MFS7_LIN_SMR_SOE                     *((volatile  uint8_t *)(0x4270E000UL))
#define bFM_MFS7_LIN_SMR_SBL                      *((volatile  uint8_t *)(0x4270E00CUL))
#define bFM4_MFS7_LIN_SMR_SBL                     *((volatile  uint8_t *)(0x4270E00CUL))
#define bFM_MFS7_LIN_SMR_WUCR                     *((volatile  uint8_t *)(0x4270E010UL))
#define bFM4_MFS7_LIN_SMR_WUCR                    *((volatile  uint8_t *)(0x4270E010UL))

#define bFM_MFS7_LIN_SSR_TBI                      *((volatile  uint8_t *)(0x4270E0A0UL))
#define bFM4_MFS7_LIN_SSR_TBI                     *((volatile  uint8_t *)(0x4270E0A0UL))
#define bFM_MFS7_LIN_SSR_TDRE                     *((volatile  uint8_t *)(0x4270E0A4UL))
#define bFM4_MFS7_LIN_SSR_TDRE                    *((volatile  uint8_t *)(0x4270E0A4UL))
#define bFM_MFS7_LIN_SSR_RDRF                     *((volatile  uint8_t *)(0x4270E0A8UL))
#define bFM4_MFS7_LIN_SSR_RDRF                    *((volatile  uint8_t *)(0x4270E0A8UL))
#define bFM_MFS7_LIN_SSR_ORE                      *((volatile  uint8_t *)(0x4270E0ACUL))
#define bFM4_MFS7_LIN_SSR_ORE                     *((volatile  uint8_t *)(0x4270E0ACUL))
#define bFM_MFS7_LIN_SSR_FRE                      *((volatile  uint8_t *)(0x4270E0B0UL))
#define bFM4_MFS7_LIN_SSR_FRE                     *((volatile  uint8_t *)(0x4270E0B0UL))
#define bFM_MFS7_LIN_SSR_LBD                      *((volatile  uint8_t *)(0x4270E0B4UL))
#define bFM4_MFS7_LIN_SSR_LBD                     *((volatile  uint8_t *)(0x4270E0B4UL))
#define bFM_MFS7_LIN_SSR_REC                      *((volatile  uint8_t *)(0x4270E0BCUL))
#define bFM4_MFS7_LIN_SSR_REC                     *((volatile  uint8_t *)(0x4270E0BCUL))

#define bFM_MFS7_UART_BGR_EXT                     *((volatile  uint8_t *)(0x4270E1BCUL))
#define bFM4_MFS7_UART_BGR_EXT                    *((volatile  uint8_t *)(0x4270E1BCUL))

#define bFM_MFS7_UART_ESCR_P                      *((volatile  uint8_t *)(0x4270E08CUL))
#define bFM4_MFS7_UART_ESCR_P                     *((volatile  uint8_t *)(0x4270E08CUL))
#define bFM_MFS7_UART_ESCR_PEN                    *((volatile  uint8_t *)(0x4270E090UL))
#define bFM4_MFS7_UART_ESCR_PEN                   *((volatile  uint8_t *)(0x4270E090UL))
#define bFM_MFS7_UART_ESCR_INV                    *((volatile  uint8_t *)(0x4270E094UL))
#define bFM4_MFS7_UART_ESCR_INV                   *((volatile  uint8_t *)(0x4270E094UL))
#define bFM_MFS7_UART_ESCR_ESBL                   *((volatile  uint8_t *)(0x4270E098UL))
#define bFM4_MFS7_UART_ESCR_ESBL                  *((volatile  uint8_t *)(0x4270E098UL))
#define bFM_MFS7_UART_ESCR_FLWEN                  *((volatile  uint8_t *)(0x4270E09CUL))
#define bFM4_MFS7_UART_ESCR_FLWEN                 *((volatile  uint8_t *)(0x4270E09CUL))

#define bFM_MFS7_UART_FCR_FE1                     *((volatile  uint8_t *)(0x4270E280UL))
#define bFM4_MFS7_UART_FCR_FE1                    *((volatile  uint8_t *)(0x4270E280UL))
#define bFM_MFS7_UART_FCR_FE2                     *((volatile  uint8_t *)(0x4270E284UL))
#define bFM4_MFS7_UART_FCR_FE2                    *((volatile  uint8_t *)(0x4270E284UL))
#define bFM_MFS7_UART_FCR_FCL1                    *((volatile  uint8_t *)(0x4270E288UL))
#define bFM4_MFS7_UART_FCR_FCL1                   *((volatile  uint8_t *)(0x4270E288UL))
#define bFM_MFS7_UART_FCR_FCL2                    *((volatile  uint8_t *)(0x4270E28CUL))
#define bFM4_MFS7_UART_FCR_FCL2                   *((volatile  uint8_t *)(0x4270E28CUL))
#define bFM_MFS7_UART_FCR_FSET                    *((volatile  uint8_t *)(0x4270E290UL))
#define bFM4_MFS7_UART_FCR_FSET                   *((volatile  uint8_t *)(0x4270E290UL))
#define bFM_MFS7_UART_FCR_FLD                     *((volatile  uint8_t *)(0x4270E294UL))
#define bFM4_MFS7_UART_FCR_FLD                    *((volatile  uint8_t *)(0x4270E294UL))
#define bFM_MFS7_UART_FCR_FLST                    *((volatile  uint8_t *)(0x4270E298UL))
#define bFM4_MFS7_UART_FCR_FLST                   *((volatile  uint8_t *)(0x4270E298UL))
#define bFM_MFS7_UART_FCR_FSEL                    *((volatile  uint8_t *)(0x4270E2A0UL))
#define bFM4_MFS7_UART_FCR_FSEL                   *((volatile  uint8_t *)(0x4270E2A0UL))
#define bFM_MFS7_UART_FCR_FTIE                    *((volatile  uint8_t *)(0x4270E2A4UL))
#define bFM4_MFS7_UART_FCR_FTIE                   *((volatile  uint8_t *)(0x4270E2A4UL))
#define bFM_MFS7_UART_FCR_FDRQ                    *((volatile  uint8_t *)(0x4270E2A8UL))
#define bFM4_MFS7_UART_FCR_FDRQ                   *((volatile  uint8_t *)(0x4270E2A8UL))
#define bFM_MFS7_UART_FCR_FRIIE                   *((volatile  uint8_t *)(0x4270E2ACUL))
#define bFM4_MFS7_UART_FCR_FRIIE                  *((volatile  uint8_t *)(0x4270E2ACUL))
#define bFM_MFS7_UART_FCR_FLSTE                   *((volatile  uint8_t *)(0x4270E2B0UL))
#define bFM4_MFS7_UART_FCR_FLSTE                  *((volatile  uint8_t *)(0x4270E2B0UL))

#define bFM_MFS7_UART_SCR_TXE                     *((volatile  uint8_t *)(0x4270E020UL))
#define bFM4_MFS7_UART_SCR_TXE                    *((volatile  uint8_t *)(0x4270E020UL))
#define bFM_MFS7_UART_SCR_RXE                     *((volatile  uint8_t *)(0x4270E024UL))
#define bFM4_MFS7_UART_SCR_RXE                    *((volatile  uint8_t *)(0x4270E024UL))
#define bFM_MFS7_UART_SCR_TBIE                    *((volatile  uint8_t *)(0x4270E028UL))
#define bFM4_MFS7_UART_SCR_TBIE                   *((volatile  uint8_t *)(0x4270E028UL))
#define bFM_MFS7_UART_SCR_TIE                     *((volatile  uint8_t *)(0x4270E02CUL))
#define bFM4_MFS7_UART_SCR_TIE                    *((volatile  uint8_t *)(0x4270E02CUL))
#define bFM_MFS7_UART_SCR_RIE                     *((volatile  uint8_t *)(0x4270E030UL))
#define bFM4_MFS7_UART_SCR_RIE                    *((volatile  uint8_t *)(0x4270E030UL))
#define bFM_MFS7_UART_SCR_UPCL                    *((volatile  uint8_t *)(0x4270E03CUL))
#define bFM4_MFS7_UART_SCR_UPCL                   *((volatile  uint8_t *)(0x4270E03CUL))

#define bFM_MFS7_UART_SMR_SOE                     *((volatile  uint8_t *)(0x4270E000UL))
#define bFM4_MFS7_UART_SMR_SOE                    *((volatile  uint8_t *)(0x4270E000UL))
#define bFM_MFS7_UART_SMR_BDS                     *((volatile  uint8_t *)(0x4270E008UL))
#define bFM4_MFS7_UART_SMR_BDS                    *((volatile  uint8_t *)(0x4270E008UL))
#define bFM_MFS7_UART_SMR_SBL                     *((volatile  uint8_t *)(0x4270E00CUL))
#define bFM4_MFS7_UART_SMR_SBL                    *((volatile  uint8_t *)(0x4270E00CUL))

#define bFM_MFS7_UART_SSR_TBI                     *((volatile  uint8_t *)(0x4270E0A0UL))
#define bFM4_MFS7_UART_SSR_TBI                    *((volatile  uint8_t *)(0x4270E0A0UL))
#define bFM_MFS7_UART_SSR_TDRE                    *((volatile  uint8_t *)(0x4270E0A4UL))
#define bFM4_MFS7_UART_SSR_TDRE                   *((volatile  uint8_t *)(0x4270E0A4UL))
#define bFM_MFS7_UART_SSR_RDRF                    *((volatile  uint8_t *)(0x4270E0A8UL))
#define bFM4_MFS7_UART_SSR_RDRF                   *((volatile  uint8_t *)(0x4270E0A8UL))
#define bFM_MFS7_UART_SSR_ORE                     *((volatile  uint8_t *)(0x4270E0ACUL))
#define bFM4_MFS7_UART_SSR_ORE                    *((volatile  uint8_t *)(0x4270E0ACUL))
#define bFM_MFS7_UART_SSR_FRE                     *((volatile  uint8_t *)(0x4270E0B0UL))
#define bFM4_MFS7_UART_SSR_FRE                    *((volatile  uint8_t *)(0x4270E0B0UL))
#define bFM_MFS7_UART_SSR_PE                      *((volatile  uint8_t *)(0x4270E0B4UL))
#define bFM4_MFS7_UART_SSR_PE                     *((volatile  uint8_t *)(0x4270E0B4UL))
#define bFM_MFS7_UART_SSR_REC                     *((volatile  uint8_t *)(0x4270E0BCUL))
#define bFM4_MFS7_UART_SSR_REC                    *((volatile  uint8_t *)(0x4270E0BCUL))


/*******************************************************************************
* MFS Registers MFS8
*   Bitband Section
*******************************************************************************/
#define bFM_MFS8_CSIO_ESCR_CSFE                   *((volatile  uint8_t *)(0x42710094UL))
#define bFM4_MFS8_CSIO_ESCR_CSFE                  *((volatile  uint8_t *)(0x42710094UL))
#define bFM_MFS8_CSIO_ESCR_L3                     *((volatile  uint8_t *)(0x42710098UL))
#define bFM4_MFS8_CSIO_ESCR_L3                    *((volatile  uint8_t *)(0x42710098UL))
#define bFM_MFS8_CSIO_ESCR_SOP                    *((volatile  uint8_t *)(0x4271009CUL))
#define bFM4_MFS8_CSIO_ESCR_SOP                   *((volatile  uint8_t *)(0x4271009CUL))

#define bFM_MFS8_CSIO_FCR_FE1                     *((volatile  uint8_t *)(0x42710280UL))
#define bFM4_MFS8_CSIO_FCR_FE1                    *((volatile  uint8_t *)(0x42710280UL))
#define bFM_MFS8_CSIO_FCR_FE2                     *((volatile  uint8_t *)(0x42710284UL))
#define bFM4_MFS8_CSIO_FCR_FE2                    *((volatile  uint8_t *)(0x42710284UL))
#define bFM_MFS8_CSIO_FCR_FCL1                    *((volatile  uint8_t *)(0x42710288UL))
#define bFM4_MFS8_CSIO_FCR_FCL1                   *((volatile  uint8_t *)(0x42710288UL))
#define bFM_MFS8_CSIO_FCR_FCL2                    *((volatile  uint8_t *)(0x4271028CUL))
#define bFM4_MFS8_CSIO_FCR_FCL2                   *((volatile  uint8_t *)(0x4271028CUL))
#define bFM_MFS8_CSIO_FCR_FSET                    *((volatile  uint8_t *)(0x42710290UL))
#define bFM4_MFS8_CSIO_FCR_FSET                   *((volatile  uint8_t *)(0x42710290UL))
#define bFM_MFS8_CSIO_FCR_FLD                     *((volatile  uint8_t *)(0x42710294UL))
#define bFM4_MFS8_CSIO_FCR_FLD                    *((volatile  uint8_t *)(0x42710294UL))
#define bFM_MFS8_CSIO_FCR_FLST                    *((volatile  uint8_t *)(0x42710298UL))
#define bFM4_MFS8_CSIO_FCR_FLST                   *((volatile  uint8_t *)(0x42710298UL))
#define bFM_MFS8_CSIO_FCR_FSEL                    *((volatile  uint8_t *)(0x427102A0UL))
#define bFM4_MFS8_CSIO_FCR_FSEL                   *((volatile  uint8_t *)(0x427102A0UL))
#define bFM_MFS8_CSIO_FCR_FTIE                    *((volatile  uint8_t *)(0x427102A4UL))
#define bFM4_MFS8_CSIO_FCR_FTIE                   *((volatile  uint8_t *)(0x427102A4UL))
#define bFM_MFS8_CSIO_FCR_FDRQ                    *((volatile  uint8_t *)(0x427102A8UL))
#define bFM4_MFS8_CSIO_FCR_FDRQ                   *((volatile  uint8_t *)(0x427102A8UL))
#define bFM_MFS8_CSIO_FCR_FRIIE                   *((volatile  uint8_t *)(0x427102ACUL))
#define bFM4_MFS8_CSIO_FCR_FRIIE                  *((volatile  uint8_t *)(0x427102ACUL))
#define bFM_MFS8_CSIO_FCR_FLSTE                   *((volatile  uint8_t *)(0x427102B0UL))
#define bFM4_MFS8_CSIO_FCR_FLSTE                  *((volatile  uint8_t *)(0x427102B0UL))

#define bFM_MFS8_CSIO_SACSR_TMRE                  *((volatile  uint8_t *)(0x42710480UL))
#define bFM4_MFS8_CSIO_SACSR_TMRE                 *((volatile  uint8_t *)(0x42710480UL))
#define bFM_MFS8_CSIO_SACSR_TSYNE                 *((volatile  uint8_t *)(0x42710498UL))
#define bFM4_MFS8_CSIO_SACSR_TSYNE                *((volatile  uint8_t *)(0x42710498UL))
#define bFM_MFS8_CSIO_SACSR_TINTE                 *((volatile  uint8_t *)(0x4271049CUL))
#define bFM4_MFS8_CSIO_SACSR_TINTE                *((volatile  uint8_t *)(0x4271049CUL))
#define bFM_MFS8_CSIO_SACSR_TINT                  *((volatile  uint8_t *)(0x427104A0UL))
#define bFM4_MFS8_CSIO_SACSR_TINT                 *((volatile  uint8_t *)(0x427104A0UL))
#define bFM_MFS8_CSIO_SACSR_CSE                   *((volatile  uint8_t *)(0x427104ACUL))
#define bFM4_MFS8_CSIO_SACSR_CSE                  *((volatile  uint8_t *)(0x427104ACUL))
#define bFM_MFS8_CSIO_SACSR_CSEIE                 *((volatile  uint8_t *)(0x427104B0UL))
#define bFM4_MFS8_CSIO_SACSR_CSEIE                *((volatile  uint8_t *)(0x427104B0UL))
#define bFM_MFS8_CSIO_SACSR_TBEEN                 *((volatile  uint8_t *)(0x427104B4UL))
#define bFM4_MFS8_CSIO_SACSR_TBEEN                *((volatile  uint8_t *)(0x427104B4UL))

#define bFM_MFS8_CSIO_SCR_TXE                     *((volatile  uint8_t *)(0x42710020UL))
#define bFM4_MFS8_CSIO_SCR_TXE                    *((volatile  uint8_t *)(0x42710020UL))
#define bFM_MFS8_CSIO_SCR_RXE                     *((volatile  uint8_t *)(0x42710024UL))
#define bFM4_MFS8_CSIO_SCR_RXE                    *((volatile  uint8_t *)(0x42710024UL))
#define bFM_MFS8_CSIO_SCR_TBIE                    *((volatile  uint8_t *)(0x42710028UL))
#define bFM4_MFS8_CSIO_SCR_TBIE                   *((volatile  uint8_t *)(0x42710028UL))
#define bFM_MFS8_CSIO_SCR_TIE                     *((volatile  uint8_t *)(0x4271002CUL))
#define bFM4_MFS8_CSIO_SCR_TIE                    *((volatile  uint8_t *)(0x4271002CUL))
#define bFM_MFS8_CSIO_SCR_RIE                     *((volatile  uint8_t *)(0x42710030UL))
#define bFM4_MFS8_CSIO_SCR_RIE                    *((volatile  uint8_t *)(0x42710030UL))
#define bFM_MFS8_CSIO_SCR_SPI                     *((volatile  uint8_t *)(0x42710034UL))
#define bFM4_MFS8_CSIO_SCR_SPI                    *((volatile  uint8_t *)(0x42710034UL))
#define bFM_MFS8_CSIO_SCR_MS                      *((volatile  uint8_t *)(0x42710038UL))
#define bFM4_MFS8_CSIO_SCR_MS                     *((volatile  uint8_t *)(0x42710038UL))
#define bFM_MFS8_CSIO_SCR_UPCL                    *((volatile  uint8_t *)(0x4271003CUL))
#define bFM4_MFS8_CSIO_SCR_UPCL                   *((volatile  uint8_t *)(0x4271003CUL))

#define bFM_MFS8_CSIO_SCSCR_CSOE                  *((volatile  uint8_t *)(0x42710600UL))
#define bFM4_MFS8_CSIO_SCSCR_CSOE                 *((volatile  uint8_t *)(0x42710600UL))
#define bFM_MFS8_CSIO_SCSCR_CSEN0                 *((volatile  uint8_t *)(0x42710604UL))
#define bFM4_MFS8_CSIO_SCSCR_CSEN0                *((volatile  uint8_t *)(0x42710604UL))
#define bFM_MFS8_CSIO_SCSCR_CSEN1                 *((volatile  uint8_t *)(0x42710608UL))
#define bFM4_MFS8_CSIO_SCSCR_CSEN1                *((volatile  uint8_t *)(0x42710608UL))
#define bFM_MFS8_CSIO_SCSCR_CSEN2                 *((volatile  uint8_t *)(0x4271060CUL))
#define bFM4_MFS8_CSIO_SCSCR_CSEN2                *((volatile  uint8_t *)(0x4271060CUL))
#define bFM_MFS8_CSIO_SCSCR_CSEN3                 *((volatile  uint8_t *)(0x42710610UL))
#define bFM4_MFS8_CSIO_SCSCR_CSEN3                *((volatile  uint8_t *)(0x42710610UL))
#define bFM_MFS8_CSIO_SCSCR_CSLVL                 *((volatile  uint8_t *)(0x42710614UL))
#define bFM4_MFS8_CSIO_SCSCR_CSLVL                *((volatile  uint8_t *)(0x42710614UL))
#define bFM_MFS8_CSIO_SCSCR_SCAM                  *((volatile  uint8_t *)(0x42710624UL))
#define bFM4_MFS8_CSIO_SCSCR_SCAM                 *((volatile  uint8_t *)(0x42710624UL))

#define bFM_MFS8_CSIO_SCSFR0_CS1SPI               *((volatile  uint8_t *)(0x42710694UL))
#define bFM4_MFS8_CSIO_SCSFR0_CS1SPI              *((volatile  uint8_t *)(0x42710694UL))
#define bFM_MFS8_CSIO_SCSFR0_CS1SCINV             *((volatile  uint8_t *)(0x42710698UL))
#define bFM4_MFS8_CSIO_SCSFR0_CS1SCINV            *((volatile  uint8_t *)(0x42710698UL))
#define bFM_MFS8_CSIO_SCSFR0_CS1CSLVL             *((volatile  uint8_t *)(0x4271069CUL))
#define bFM4_MFS8_CSIO_SCSFR0_CS1CSLVL            *((volatile  uint8_t *)(0x4271069CUL))

#define bFM_MFS8_CSIO_SCSFR1_CS2SPI               *((volatile  uint8_t *)(0x427106B4UL))
#define bFM4_MFS8_CSIO_SCSFR1_CS2SPI              *((volatile  uint8_t *)(0x427106B4UL))
#define bFM_MFS8_CSIO_SCSFR1_CS2SCINV             *((volatile  uint8_t *)(0x427106B8UL))
#define bFM4_MFS8_CSIO_SCSFR1_CS2SCINV            *((volatile  uint8_t *)(0x427106B8UL))
#define bFM_MFS8_CSIO_SCSFR1_CS2CSLVL             *((volatile  uint8_t *)(0x427106BCUL))
#define bFM4_MFS8_CSIO_SCSFR1_CS2CSLVL            *((volatile  uint8_t *)(0x427106BCUL))

#define bFM_MFS8_CSIO_SCSFR2_CS3SPI               *((volatile  uint8_t *)(0x42710714UL))
#define bFM4_MFS8_CSIO_SCSFR2_CS3SPI              *((volatile  uint8_t *)(0x42710714UL))
#define bFM_MFS8_CSIO_SCSFR2_CS3SCINV             *((volatile  uint8_t *)(0x42710718UL))
#define bFM4_MFS8_CSIO_SCSFR2_CS3SCINV            *((volatile  uint8_t *)(0x42710718UL))
#define bFM_MFS8_CSIO_SCSFR2_CS3CSLVL             *((volatile  uint8_t *)(0x4271071CUL))
#define bFM4_MFS8_CSIO_SCSFR2_CS3CSLVL            *((volatile  uint8_t *)(0x4271071CUL))

#define bFM_MFS8_CSIO_SMR_SOE                     *((volatile  uint8_t *)(0x42710000UL))
#define bFM4_MFS8_CSIO_SMR_SOE                    *((volatile  uint8_t *)(0x42710000UL))
#define bFM_MFS8_CSIO_SMR_SCKE                    *((volatile  uint8_t *)(0x42710004UL))
#define bFM4_MFS8_CSIO_SMR_SCKE                   *((volatile  uint8_t *)(0x42710004UL))
#define bFM_MFS8_CSIO_SMR_BDS                     *((volatile  uint8_t *)(0x42710008UL))
#define bFM4_MFS8_CSIO_SMR_BDS                    *((volatile  uint8_t *)(0x42710008UL))
#define bFM_MFS8_CSIO_SMR_SCINV                   *((volatile  uint8_t *)(0x4271000CUL))
#define bFM4_MFS8_CSIO_SMR_SCINV                  *((volatile  uint8_t *)(0x4271000CUL))

#define bFM_MFS8_CSIO_SSR_TBI                     *((volatile  uint8_t *)(0x427100A0UL))
#define bFM4_MFS8_CSIO_SSR_TBI                    *((volatile  uint8_t *)(0x427100A0UL))
#define bFM_MFS8_CSIO_SSR_TDRE                    *((volatile  uint8_t *)(0x427100A4UL))
#define bFM4_MFS8_CSIO_SSR_TDRE                   *((volatile  uint8_t *)(0x427100A4UL))
#define bFM_MFS8_CSIO_SSR_RDRF                    *((volatile  uint8_t *)(0x427100A8UL))
#define bFM4_MFS8_CSIO_SSR_RDRF                   *((volatile  uint8_t *)(0x427100A8UL))
#define bFM_MFS8_CSIO_SSR_ORE                     *((volatile  uint8_t *)(0x427100ACUL))
#define bFM4_MFS8_CSIO_SSR_ORE                    *((volatile  uint8_t *)(0x427100ACUL))
#define bFM_MFS8_CSIO_SSR_AWC                     *((volatile  uint8_t *)(0x427100B0UL))
#define bFM4_MFS8_CSIO_SSR_AWC                    *((volatile  uint8_t *)(0x427100B0UL))
#define bFM_MFS8_CSIO_SSR_REC                     *((volatile  uint8_t *)(0x427100BCUL))
#define bFM4_MFS8_CSIO_SSR_REC                    *((volatile  uint8_t *)(0x427100BCUL))

#define bFM_MFS8_I2C_EIBCR_BEC                    *((volatile  uint8_t *)(0x427103A0UL))
#define bFM4_MFS8_I2C_EIBCR_BEC                   *((volatile  uint8_t *)(0x427103A0UL))
#define bFM_MFS8_I2C_EIBCR_SOCE                   *((volatile  uint8_t *)(0x427103A4UL))
#define bFM4_MFS8_I2C_EIBCR_SOCE                  *((volatile  uint8_t *)(0x427103A4UL))
#define bFM_MFS8_I2C_EIBCR_SCLC                   *((volatile  uint8_t *)(0x427103A8UL))
#define bFM4_MFS8_I2C_EIBCR_SCLC                  *((volatile  uint8_t *)(0x427103A8UL))
#define bFM_MFS8_I2C_EIBCR_SDAC                   *((volatile  uint8_t *)(0x427103ACUL))
#define bFM4_MFS8_I2C_EIBCR_SDAC                  *((volatile  uint8_t *)(0x427103ACUL))
#define bFM_MFS8_I2C_EIBCR_SCLS                   *((volatile  uint8_t *)(0x427103B0UL))
#define bFM4_MFS8_I2C_EIBCR_SCLS                  *((volatile  uint8_t *)(0x427103B0UL))
#define bFM_MFS8_I2C_EIBCR_SDAS                   *((volatile  uint8_t *)(0x427103B4UL))
#define bFM4_MFS8_I2C_EIBCR_SDAS                  *((volatile  uint8_t *)(0x427103B4UL))

#define bFM_MFS8_I2C_FCR_FE1                      *((volatile  uint8_t *)(0x42710280UL))
#define bFM4_MFS8_I2C_FCR_FE1                     *((volatile  uint8_t *)(0x42710280UL))
#define bFM_MFS8_I2C_FCR_FE2                      *((volatile  uint8_t *)(0x42710284UL))
#define bFM4_MFS8_I2C_FCR_FE2                     *((volatile  uint8_t *)(0x42710284UL))
#define bFM_MFS8_I2C_FCR_FCL1                     *((volatile  uint8_t *)(0x42710288UL))
#define bFM4_MFS8_I2C_FCR_FCL1                    *((volatile  uint8_t *)(0x42710288UL))
#define bFM_MFS8_I2C_FCR_FCL2                     *((volatile  uint8_t *)(0x4271028CUL))
#define bFM4_MFS8_I2C_FCR_FCL2                    *((volatile  uint8_t *)(0x4271028CUL))
#define bFM_MFS8_I2C_FCR_FSET                     *((volatile  uint8_t *)(0x42710290UL))
#define bFM4_MFS8_I2C_FCR_FSET                    *((volatile  uint8_t *)(0x42710290UL))
#define bFM_MFS8_I2C_FCR_FLD                      *((volatile  uint8_t *)(0x42710294UL))
#define bFM4_MFS8_I2C_FCR_FLD                     *((volatile  uint8_t *)(0x42710294UL))
#define bFM_MFS8_I2C_FCR_FLST                     *((volatile  uint8_t *)(0x42710298UL))
#define bFM4_MFS8_I2C_FCR_FLST                    *((volatile  uint8_t *)(0x42710298UL))
#define bFM_MFS8_I2C_FCR_FSEL                     *((volatile  uint8_t *)(0x427102A0UL))
#define bFM4_MFS8_I2C_FCR_FSEL                    *((volatile  uint8_t *)(0x427102A0UL))
#define bFM_MFS8_I2C_FCR_FTIE                     *((volatile  uint8_t *)(0x427102A4UL))
#define bFM4_MFS8_I2C_FCR_FTIE                    *((volatile  uint8_t *)(0x427102A4UL))
#define bFM_MFS8_I2C_FCR_FDRQ                     *((volatile  uint8_t *)(0x427102A8UL))
#define bFM4_MFS8_I2C_FCR_FDRQ                    *((volatile  uint8_t *)(0x427102A8UL))
#define bFM_MFS8_I2C_FCR_FRIIE                    *((volatile  uint8_t *)(0x427102ACUL))
#define bFM4_MFS8_I2C_FCR_FRIIE                   *((volatile  uint8_t *)(0x427102ACUL))
#define bFM_MFS8_I2C_FCR_FLSTE                    *((volatile  uint8_t *)(0x427102B0UL))
#define bFM4_MFS8_I2C_FCR_FLSTE                   *((volatile  uint8_t *)(0x427102B0UL))

#define bFM_MFS8_I2C_IBCR_INT                     *((volatile  uint8_t *)(0x42710020UL))
#define bFM4_MFS8_I2C_IBCR_INT                    *((volatile  uint8_t *)(0x42710020UL))
#define bFM_MFS8_I2C_IBCR_BER                     *((volatile  uint8_t *)(0x42710024UL))
#define bFM4_MFS8_I2C_IBCR_BER                    *((volatile  uint8_t *)(0x42710024UL))
#define bFM_MFS8_I2C_IBCR_INTE                    *((volatile  uint8_t *)(0x42710028UL))
#define bFM4_MFS8_I2C_IBCR_INTE                   *((volatile  uint8_t *)(0x42710028UL))
#define bFM_MFS8_I2C_IBCR_CNDE                    *((volatile  uint8_t *)(0x4271002CUL))
#define bFM4_MFS8_I2C_IBCR_CNDE                   *((volatile  uint8_t *)(0x4271002CUL))
#define bFM_MFS8_I2C_IBCR_WSEL                    *((volatile  uint8_t *)(0x42710030UL))
#define bFM4_MFS8_I2C_IBCR_WSEL                   *((volatile  uint8_t *)(0x42710030UL))
#define bFM_MFS8_I2C_IBCR_ACKE                    *((volatile  uint8_t *)(0x42710034UL))
#define bFM4_MFS8_I2C_IBCR_ACKE                   *((volatile  uint8_t *)(0x42710034UL))
#define bFM_MFS8_I2C_IBCR_ACT_SCC                 *((volatile  uint8_t *)(0x42710038UL))
#define bFM4_MFS8_I2C_IBCR_ACT_SCC                *((volatile  uint8_t *)(0x42710038UL))
#define bFM_MFS8_I2C_IBCR_MSS                     *((volatile  uint8_t *)(0x4271003CUL))
#define bFM4_MFS8_I2C_IBCR_MSS                    *((volatile  uint8_t *)(0x4271003CUL))

#define bFM_MFS8_I2C_IBSR_BB                      *((volatile  uint8_t *)(0x42710080UL))
#define bFM4_MFS8_I2C_IBSR_BB                     *((volatile  uint8_t *)(0x42710080UL))
#define bFM_MFS8_I2C_IBSR_SPC                     *((volatile  uint8_t *)(0x42710084UL))
#define bFM4_MFS8_I2C_IBSR_SPC                    *((volatile  uint8_t *)(0x42710084UL))
#define bFM_MFS8_I2C_IBSR_RSC                     *((volatile  uint8_t *)(0x42710088UL))
#define bFM4_MFS8_I2C_IBSR_RSC                    *((volatile  uint8_t *)(0x42710088UL))
#define bFM_MFS8_I2C_IBSR_AL                      *((volatile  uint8_t *)(0x4271008CUL))
#define bFM4_MFS8_I2C_IBSR_AL                     *((volatile  uint8_t *)(0x4271008CUL))
#define bFM_MFS8_I2C_IBSR_TRX                     *((volatile  uint8_t *)(0x42710090UL))
#define bFM4_MFS8_I2C_IBSR_TRX                    *((volatile  uint8_t *)(0x42710090UL))
#define bFM_MFS8_I2C_IBSR_RSA                     *((volatile  uint8_t *)(0x42710094UL))
#define bFM4_MFS8_I2C_IBSR_RSA                    *((volatile  uint8_t *)(0x42710094UL))
#define bFM_MFS8_I2C_IBSR_RACK                    *((volatile  uint8_t *)(0x42710098UL))
#define bFM4_MFS8_I2C_IBSR_RACK                   *((volatile  uint8_t *)(0x42710098UL))
#define bFM_MFS8_I2C_IBSR_FBT                     *((volatile  uint8_t *)(0x4271009CUL))
#define bFM4_MFS8_I2C_IBSR_FBT                    *((volatile  uint8_t *)(0x4271009CUL))

#define bFM_MFS8_I2C_ISBA_SAEN                    *((volatile  uint8_t *)(0x4271021CUL))
#define bFM4_MFS8_I2C_ISBA_SAEN                   *((volatile  uint8_t *)(0x4271021CUL))

#define bFM_MFS8_I2C_ISMK_EN                      *((volatile  uint8_t *)(0x4271023CUL))
#define bFM4_MFS8_I2C_ISMK_EN                     *((volatile  uint8_t *)(0x4271023CUL))

#define bFM_MFS8_I2C_SMR_TIE                      *((volatile  uint8_t *)(0x42710008UL))
#define bFM4_MFS8_I2C_SMR_TIE                     *((volatile  uint8_t *)(0x42710008UL))
#define bFM_MFS8_I2C_SMR_RIE                      *((volatile  uint8_t *)(0x4271000CUL))
#define bFM4_MFS8_I2C_SMR_RIE                     *((volatile  uint8_t *)(0x4271000CUL))

#define bFM_MFS8_I2C_SSR_TBI                      *((volatile  uint8_t *)(0x427100A0UL))
#define bFM4_MFS8_I2C_SSR_TBI                     *((volatile  uint8_t *)(0x427100A0UL))
#define bFM_MFS8_I2C_SSR_TDRE                     *((volatile  uint8_t *)(0x427100A4UL))
#define bFM4_MFS8_I2C_SSR_TDRE                    *((volatile  uint8_t *)(0x427100A4UL))
#define bFM_MFS8_I2C_SSR_RDRF                     *((volatile  uint8_t *)(0x427100A8UL))
#define bFM4_MFS8_I2C_SSR_RDRF                    *((volatile  uint8_t *)(0x427100A8UL))
#define bFM_MFS8_I2C_SSR_ORE                      *((volatile  uint8_t *)(0x427100ACUL))
#define bFM4_MFS8_I2C_SSR_ORE                     *((volatile  uint8_t *)(0x427100ACUL))
#define bFM_MFS8_I2C_SSR_TBIE                     *((volatile  uint8_t *)(0x427100B0UL))
#define bFM4_MFS8_I2C_SSR_TBIE                    *((volatile  uint8_t *)(0x427100B0UL))
#define bFM_MFS8_I2C_SSR_DMA                      *((volatile  uint8_t *)(0x427100B4UL))
#define bFM4_MFS8_I2C_SSR_DMA                     *((volatile  uint8_t *)(0x427100B4UL))
#define bFM_MFS8_I2C_SSR_TSET                     *((volatile  uint8_t *)(0x427100B8UL))
#define bFM4_MFS8_I2C_SSR_TSET                    *((volatile  uint8_t *)(0x427100B8UL))
#define bFM_MFS8_I2C_SSR_REC                      *((volatile  uint8_t *)(0x427100BCUL))
#define bFM4_MFS8_I2C_SSR_REC                     *((volatile  uint8_t *)(0x427100BCUL))

#define bFM_MFS8_LIN_BGR_EXT                      *((volatile  uint8_t *)(0x427101BCUL))
#define bFM4_MFS8_LIN_BGR_EXT                     *((volatile  uint8_t *)(0x427101BCUL))

#define bFM_MFS8_LIN_ESCR_LBIE                    *((volatile  uint8_t *)(0x42710090UL))
#define bFM4_MFS8_LIN_ESCR_LBIE                   *((volatile  uint8_t *)(0x42710090UL))
#define bFM_MFS8_LIN_ESCR_ESBL                    *((volatile  uint8_t *)(0x42710098UL))
#define bFM4_MFS8_LIN_ESCR_ESBL                   *((volatile  uint8_t *)(0x42710098UL))

#define bFM_MFS8_LIN_FCR_FE1                      *((volatile  uint8_t *)(0x42710280UL))
#define bFM4_MFS8_LIN_FCR_FE1                     *((volatile  uint8_t *)(0x42710280UL))
#define bFM_MFS8_LIN_FCR_FE2                      *((volatile  uint8_t *)(0x42710284UL))
#define bFM4_MFS8_LIN_FCR_FE2                     *((volatile  uint8_t *)(0x42710284UL))
#define bFM_MFS8_LIN_FCR_FCL1                     *((volatile  uint8_t *)(0x42710288UL))
#define bFM4_MFS8_LIN_FCR_FCL1                    *((volatile  uint8_t *)(0x42710288UL))
#define bFM_MFS8_LIN_FCR_FCL2                     *((volatile  uint8_t *)(0x4271028CUL))
#define bFM4_MFS8_LIN_FCR_FCL2                    *((volatile  uint8_t *)(0x4271028CUL))
#define bFM_MFS8_LIN_FCR_FSET                     *((volatile  uint8_t *)(0x42710290UL))
#define bFM4_MFS8_LIN_FCR_FSET                    *((volatile  uint8_t *)(0x42710290UL))
#define bFM_MFS8_LIN_FCR_FLD                      *((volatile  uint8_t *)(0x42710294UL))
#define bFM4_MFS8_LIN_FCR_FLD                     *((volatile  uint8_t *)(0x42710294UL))
#define bFM_MFS8_LIN_FCR_FLST                     *((volatile  uint8_t *)(0x42710298UL))
#define bFM4_MFS8_LIN_FCR_FLST                    *((volatile  uint8_t *)(0x42710298UL))
#define bFM_MFS8_LIN_FCR_FSEL                     *((volatile  uint8_t *)(0x427102A0UL))
#define bFM4_MFS8_LIN_FCR_FSEL                    *((volatile  uint8_t *)(0x427102A0UL))
#define bFM_MFS8_LIN_FCR_FTIE                     *((volatile  uint8_t *)(0x427102A4UL))
#define bFM4_MFS8_LIN_FCR_FTIE                    *((volatile  uint8_t *)(0x427102A4UL))
#define bFM_MFS8_LIN_FCR_FDRQ                     *((volatile  uint8_t *)(0x427102A8UL))
#define bFM4_MFS8_LIN_FCR_FDRQ                    *((volatile  uint8_t *)(0x427102A8UL))
#define bFM_MFS8_LIN_FCR_FRIIE                    *((volatile  uint8_t *)(0x427102ACUL))
#define bFM4_MFS8_LIN_FCR_FRIIE                   *((volatile  uint8_t *)(0x427102ACUL))
#define bFM_MFS8_LIN_FCR_FLSTE                    *((volatile  uint8_t *)(0x427102B0UL))
#define bFM4_MFS8_LIN_FCR_FLSTE                   *((volatile  uint8_t *)(0x427102B0UL))

#define bFM_MFS8_LIN_SCR_TXE                      *((volatile  uint8_t *)(0x42710020UL))
#define bFM4_MFS8_LIN_SCR_TXE                     *((volatile  uint8_t *)(0x42710020UL))
#define bFM_MFS8_LIN_SCR_RXE                      *((volatile  uint8_t *)(0x42710024UL))
#define bFM4_MFS8_LIN_SCR_RXE                     *((volatile  uint8_t *)(0x42710024UL))
#define bFM_MFS8_LIN_SCR_TBIE                     *((volatile  uint8_t *)(0x42710028UL))
#define bFM4_MFS8_LIN_SCR_TBIE                    *((volatile  uint8_t *)(0x42710028UL))
#define bFM_MFS8_LIN_SCR_TIE                      *((volatile  uint8_t *)(0x4271002CUL))
#define bFM4_MFS8_LIN_SCR_TIE                     *((volatile  uint8_t *)(0x4271002CUL))
#define bFM_MFS8_LIN_SCR_RIE                      *((volatile  uint8_t *)(0x42710030UL))
#define bFM4_MFS8_LIN_SCR_RIE                     *((volatile  uint8_t *)(0x42710030UL))
#define bFM_MFS8_LIN_SCR_LBR                      *((volatile  uint8_t *)(0x42710034UL))
#define bFM4_MFS8_LIN_SCR_LBR                     *((volatile  uint8_t *)(0x42710034UL))
#define bFM_MFS8_LIN_SCR_MS                       *((volatile  uint8_t *)(0x42710038UL))
#define bFM4_MFS8_LIN_SCR_MS                      *((volatile  uint8_t *)(0x42710038UL))
#define bFM_MFS8_LIN_SCR_UPCL                     *((volatile  uint8_t *)(0x4271003CUL))
#define bFM4_MFS8_LIN_SCR_UPCL                    *((volatile  uint8_t *)(0x4271003CUL))

#define bFM_MFS8_LIN_SMR_SOE                      *((volatile  uint8_t *)(0x42710000UL))
#define bFM4_MFS8_LIN_SMR_SOE                     *((volatile  uint8_t *)(0x42710000UL))
#define bFM_MFS8_LIN_SMR_SBL                      *((volatile  uint8_t *)(0x4271000CUL))
#define bFM4_MFS8_LIN_SMR_SBL                     *((volatile  uint8_t *)(0x4271000CUL))
#define bFM_MFS8_LIN_SMR_WUCR                     *((volatile  uint8_t *)(0x42710010UL))
#define bFM4_MFS8_LIN_SMR_WUCR                    *((volatile  uint8_t *)(0x42710010UL))

#define bFM_MFS8_LIN_SSR_TBI                      *((volatile  uint8_t *)(0x427100A0UL))
#define bFM4_MFS8_LIN_SSR_TBI                     *((volatile  uint8_t *)(0x427100A0UL))
#define bFM_MFS8_LIN_SSR_TDRE                     *((volatile  uint8_t *)(0x427100A4UL))
#define bFM4_MFS8_LIN_SSR_TDRE                    *((volatile  uint8_t *)(0x427100A4UL))
#define bFM_MFS8_LIN_SSR_RDRF                     *((volatile  uint8_t *)(0x427100A8UL))
#define bFM4_MFS8_LIN_SSR_RDRF                    *((volatile  uint8_t *)(0x427100A8UL))
#define bFM_MFS8_LIN_SSR_ORE                      *((volatile  uint8_t *)(0x427100ACUL))
#define bFM4_MFS8_LIN_SSR_ORE                     *((volatile  uint8_t *)(0x427100ACUL))
#define bFM_MFS8_LIN_SSR_FRE                      *((volatile  uint8_t *)(0x427100B0UL))
#define bFM4_MFS8_LIN_SSR_FRE                     *((volatile  uint8_t *)(0x427100B0UL))
#define bFM_MFS8_LIN_SSR_LBD                      *((volatile  uint8_t *)(0x427100B4UL))
#define bFM4_MFS8_LIN_SSR_LBD                     *((volatile  uint8_t *)(0x427100B4UL))
#define bFM_MFS8_LIN_SSR_REC                      *((volatile  uint8_t *)(0x427100BCUL))
#define bFM4_MFS8_LIN_SSR_REC                     *((volatile  uint8_t *)(0x427100BCUL))

#define bFM_MFS8_UART_BGR_EXT                     *((volatile  uint8_t *)(0x427101BCUL))
#define bFM4_MFS8_UART_BGR_EXT                    *((volatile  uint8_t *)(0x427101BCUL))

#define bFM_MFS8_UART_ESCR_P                      *((volatile  uint8_t *)(0x4271008CUL))
#define bFM4_MFS8_UART_ESCR_P                     *((volatile  uint8_t *)(0x4271008CUL))
#define bFM_MFS8_UART_ESCR_PEN                    *((volatile  uint8_t *)(0x42710090UL))
#define bFM4_MFS8_UART_ESCR_PEN                   *((volatile  uint8_t *)(0x42710090UL))
#define bFM_MFS8_UART_ESCR_INV                    *((volatile  uint8_t *)(0x42710094UL))
#define bFM4_MFS8_UART_ESCR_INV                   *((volatile  uint8_t *)(0x42710094UL))
#define bFM_MFS8_UART_ESCR_ESBL                   *((volatile  uint8_t *)(0x42710098UL))
#define bFM4_MFS8_UART_ESCR_ESBL                  *((volatile  uint8_t *)(0x42710098UL))
#define bFM_MFS8_UART_ESCR_FLWEN                  *((volatile  uint8_t *)(0x4271009CUL))
#define bFM4_MFS8_UART_ESCR_FLWEN                 *((volatile  uint8_t *)(0x4271009CUL))

#define bFM_MFS8_UART_FCR_FE1                     *((volatile  uint8_t *)(0x42710280UL))
#define bFM4_MFS8_UART_FCR_FE1                    *((volatile  uint8_t *)(0x42710280UL))
#define bFM_MFS8_UART_FCR_FE2                     *((volatile  uint8_t *)(0x42710284UL))
#define bFM4_MFS8_UART_FCR_FE2                    *((volatile  uint8_t *)(0x42710284UL))
#define bFM_MFS8_UART_FCR_FCL1                    *((volatile  uint8_t *)(0x42710288UL))
#define bFM4_MFS8_UART_FCR_FCL1                   *((volatile  uint8_t *)(0x42710288UL))
#define bFM_MFS8_UART_FCR_FCL2                    *((volatile  uint8_t *)(0x4271028CUL))
#define bFM4_MFS8_UART_FCR_FCL2                   *((volatile  uint8_t *)(0x4271028CUL))
#define bFM_MFS8_UART_FCR_FSET                    *((volatile  uint8_t *)(0x42710290UL))
#define bFM4_MFS8_UART_FCR_FSET                   *((volatile  uint8_t *)(0x42710290UL))
#define bFM_MFS8_UART_FCR_FLD                     *((volatile  uint8_t *)(0x42710294UL))
#define bFM4_MFS8_UART_FCR_FLD                    *((volatile  uint8_t *)(0x42710294UL))
#define bFM_MFS8_UART_FCR_FLST                    *((volatile  uint8_t *)(0x42710298UL))
#define bFM4_MFS8_UART_FCR_FLST                   *((volatile  uint8_t *)(0x42710298UL))
#define bFM_MFS8_UART_FCR_FSEL                    *((volatile  uint8_t *)(0x427102A0UL))
#define bFM4_MFS8_UART_FCR_FSEL                   *((volatile  uint8_t *)(0x427102A0UL))
#define bFM_MFS8_UART_FCR_FTIE                    *((volatile  uint8_t *)(0x427102A4UL))
#define bFM4_MFS8_UART_FCR_FTIE                   *((volatile  uint8_t *)(0x427102A4UL))
#define bFM_MFS8_UART_FCR_FDRQ                    *((volatile  uint8_t *)(0x427102A8UL))
#define bFM4_MFS8_UART_FCR_FDRQ                   *((volatile  uint8_t *)(0x427102A8UL))
#define bFM_MFS8_UART_FCR_FRIIE                   *((volatile  uint8_t *)(0x427102ACUL))
#define bFM4_MFS8_UART_FCR_FRIIE                  *((volatile  uint8_t *)(0x427102ACUL))
#define bFM_MFS8_UART_FCR_FLSTE                   *((volatile  uint8_t *)(0x427102B0UL))
#define bFM4_MFS8_UART_FCR_FLSTE                  *((volatile  uint8_t *)(0x427102B0UL))

#define bFM_MFS8_UART_SCR_TXE                     *((volatile  uint8_t *)(0x42710020UL))
#define bFM4_MFS8_UART_SCR_TXE                    *((volatile  uint8_t *)(0x42710020UL))
#define bFM_MFS8_UART_SCR_RXE                     *((volatile  uint8_t *)(0x42710024UL))
#define bFM4_MFS8_UART_SCR_RXE                    *((volatile  uint8_t *)(0x42710024UL))
#define bFM_MFS8_UART_SCR_TBIE                    *((volatile  uint8_t *)(0x42710028UL))
#define bFM4_MFS8_UART_SCR_TBIE                   *((volatile  uint8_t *)(0x42710028UL))
#define bFM_MFS8_UART_SCR_TIE                     *((volatile  uint8_t *)(0x4271002CUL))
#define bFM4_MFS8_UART_SCR_TIE                    *((volatile  uint8_t *)(0x4271002CUL))
#define bFM_MFS8_UART_SCR_RIE                     *((volatile  uint8_t *)(0x42710030UL))
#define bFM4_MFS8_UART_SCR_RIE                    *((volatile  uint8_t *)(0x42710030UL))
#define bFM_MFS8_UART_SCR_UPCL                    *((volatile  uint8_t *)(0x4271003CUL))
#define bFM4_MFS8_UART_SCR_UPCL                   *((volatile  uint8_t *)(0x4271003CUL))

#define bFM_MFS8_UART_SMR_SOE                     *((volatile  uint8_t *)(0x42710000UL))
#define bFM4_MFS8_UART_SMR_SOE                    *((volatile  uint8_t *)(0x42710000UL))
#define bFM_MFS8_UART_SMR_BDS                     *((volatile  uint8_t *)(0x42710008UL))
#define bFM4_MFS8_UART_SMR_BDS                    *((volatile  uint8_t *)(0x42710008UL))
#define bFM_MFS8_UART_SMR_SBL                     *((volatile  uint8_t *)(0x4271000CUL))
#define bFM4_MFS8_UART_SMR_SBL                    *((volatile  uint8_t *)(0x4271000CUL))

#define bFM_MFS8_UART_SSR_TBI                     *((volatile  uint8_t *)(0x427100A0UL))
#define bFM4_MFS8_UART_SSR_TBI                    *((volatile  uint8_t *)(0x427100A0UL))
#define bFM_MFS8_UART_SSR_TDRE                    *((volatile  uint8_t *)(0x427100A4UL))
#define bFM4_MFS8_UART_SSR_TDRE                   *((volatile  uint8_t *)(0x427100A4UL))
#define bFM_MFS8_UART_SSR_RDRF                    *((volatile  uint8_t *)(0x427100A8UL))
#define bFM4_MFS8_UART_SSR_RDRF                   *((volatile  uint8_t *)(0x427100A8UL))
#define bFM_MFS8_UART_SSR_ORE                     *((volatile  uint8_t *)(0x427100ACUL))
#define bFM4_MFS8_UART_SSR_ORE                    *((volatile  uint8_t *)(0x427100ACUL))
#define bFM_MFS8_UART_SSR_FRE                     *((volatile  uint8_t *)(0x427100B0UL))
#define bFM4_MFS8_UART_SSR_FRE                    *((volatile  uint8_t *)(0x427100B0UL))
#define bFM_MFS8_UART_SSR_PE                      *((volatile  uint8_t *)(0x427100B4UL))
#define bFM4_MFS8_UART_SSR_PE                     *((volatile  uint8_t *)(0x427100B4UL))
#define bFM_MFS8_UART_SSR_REC                     *((volatile  uint8_t *)(0x427100BCUL))
#define bFM4_MFS8_UART_SSR_REC                    *((volatile  uint8_t *)(0x427100BCUL))


/*******************************************************************************
* MFS Registers MFS9
*   Bitband Section
*******************************************************************************/
#define bFM_MFS9_CSIO_ESCR_CSFE                   *((volatile  uint8_t *)(0x42712094UL))
#define bFM4_MFS9_CSIO_ESCR_CSFE                  *((volatile  uint8_t *)(0x42712094UL))
#define bFM_MFS9_CSIO_ESCR_L3                     *((volatile  uint8_t *)(0x42712098UL))
#define bFM4_MFS9_CSIO_ESCR_L3                    *((volatile  uint8_t *)(0x42712098UL))
#define bFM_MFS9_CSIO_ESCR_SOP                    *((volatile  uint8_t *)(0x4271209CUL))
#define bFM4_MFS9_CSIO_ESCR_SOP                   *((volatile  uint8_t *)(0x4271209CUL))

#define bFM_MFS9_CSIO_FCR_FE1                     *((volatile  uint8_t *)(0x42712280UL))
#define bFM4_MFS9_CSIO_FCR_FE1                    *((volatile  uint8_t *)(0x42712280UL))
#define bFM_MFS9_CSIO_FCR_FE2                     *((volatile  uint8_t *)(0x42712284UL))
#define bFM4_MFS9_CSIO_FCR_FE2                    *((volatile  uint8_t *)(0x42712284UL))
#define bFM_MFS9_CSIO_FCR_FCL1                    *((volatile  uint8_t *)(0x42712288UL))
#define bFM4_MFS9_CSIO_FCR_FCL1                   *((volatile  uint8_t *)(0x42712288UL))
#define bFM_MFS9_CSIO_FCR_FCL2                    *((volatile  uint8_t *)(0x4271228CUL))
#define bFM4_MFS9_CSIO_FCR_FCL2                   *((volatile  uint8_t *)(0x4271228CUL))
#define bFM_MFS9_CSIO_FCR_FSET                    *((volatile  uint8_t *)(0x42712290UL))
#define bFM4_MFS9_CSIO_FCR_FSET                   *((volatile  uint8_t *)(0x42712290UL))
#define bFM_MFS9_CSIO_FCR_FLD                     *((volatile  uint8_t *)(0x42712294UL))
#define bFM4_MFS9_CSIO_FCR_FLD                    *((volatile  uint8_t *)(0x42712294UL))
#define bFM_MFS9_CSIO_FCR_FLST                    *((volatile  uint8_t *)(0x42712298UL))
#define bFM4_MFS9_CSIO_FCR_FLST                   *((volatile  uint8_t *)(0x42712298UL))
#define bFM_MFS9_CSIO_FCR_FSEL                    *((volatile  uint8_t *)(0x427122A0UL))
#define bFM4_MFS9_CSIO_FCR_FSEL                   *((volatile  uint8_t *)(0x427122A0UL))
#define bFM_MFS9_CSIO_FCR_FTIE                    *((volatile  uint8_t *)(0x427122A4UL))
#define bFM4_MFS9_CSIO_FCR_FTIE                   *((volatile  uint8_t *)(0x427122A4UL))
#define bFM_MFS9_CSIO_FCR_FDRQ                    *((volatile  uint8_t *)(0x427122A8UL))
#define bFM4_MFS9_CSIO_FCR_FDRQ                   *((volatile  uint8_t *)(0x427122A8UL))
#define bFM_MFS9_CSIO_FCR_FRIIE                   *((volatile  uint8_t *)(0x427122ACUL))
#define bFM4_MFS9_CSIO_FCR_FRIIE                  *((volatile  uint8_t *)(0x427122ACUL))
#define bFM_MFS9_CSIO_FCR_FLSTE                   *((volatile  uint8_t *)(0x427122B0UL))
#define bFM4_MFS9_CSIO_FCR_FLSTE                  *((volatile  uint8_t *)(0x427122B0UL))

#define bFM_MFS9_CSIO_SACSR_TMRE                  *((volatile  uint8_t *)(0x42712480UL))
#define bFM4_MFS9_CSIO_SACSR_TMRE                 *((volatile  uint8_t *)(0x42712480UL))
#define bFM_MFS9_CSIO_SACSR_TSYNE                 *((volatile  uint8_t *)(0x42712498UL))
#define bFM4_MFS9_CSIO_SACSR_TSYNE                *((volatile  uint8_t *)(0x42712498UL))
#define bFM_MFS9_CSIO_SACSR_TINTE                 *((volatile  uint8_t *)(0x4271249CUL))
#define bFM4_MFS9_CSIO_SACSR_TINTE                *((volatile  uint8_t *)(0x4271249CUL))
#define bFM_MFS9_CSIO_SACSR_TINT                  *((volatile  uint8_t *)(0x427124A0UL))
#define bFM4_MFS9_CSIO_SACSR_TINT                 *((volatile  uint8_t *)(0x427124A0UL))
#define bFM_MFS9_CSIO_SACSR_CSE                   *((volatile  uint8_t *)(0x427124ACUL))
#define bFM4_MFS9_CSIO_SACSR_CSE                  *((volatile  uint8_t *)(0x427124ACUL))
#define bFM_MFS9_CSIO_SACSR_CSEIE                 *((volatile  uint8_t *)(0x427124B0UL))
#define bFM4_MFS9_CSIO_SACSR_CSEIE                *((volatile  uint8_t *)(0x427124B0UL))
#define bFM_MFS9_CSIO_SACSR_TBEEN                 *((volatile  uint8_t *)(0x427124B4UL))
#define bFM4_MFS9_CSIO_SACSR_TBEEN                *((volatile  uint8_t *)(0x427124B4UL))

#define bFM_MFS9_CSIO_SCR_TXE                     *((volatile  uint8_t *)(0x42712020UL))
#define bFM4_MFS9_CSIO_SCR_TXE                    *((volatile  uint8_t *)(0x42712020UL))
#define bFM_MFS9_CSIO_SCR_RXE                     *((volatile  uint8_t *)(0x42712024UL))
#define bFM4_MFS9_CSIO_SCR_RXE                    *((volatile  uint8_t *)(0x42712024UL))
#define bFM_MFS9_CSIO_SCR_TBIE                    *((volatile  uint8_t *)(0x42712028UL))
#define bFM4_MFS9_CSIO_SCR_TBIE                   *((volatile  uint8_t *)(0x42712028UL))
#define bFM_MFS9_CSIO_SCR_TIE                     *((volatile  uint8_t *)(0x4271202CUL))
#define bFM4_MFS9_CSIO_SCR_TIE                    *((volatile  uint8_t *)(0x4271202CUL))
#define bFM_MFS9_CSIO_SCR_RIE                     *((volatile  uint8_t *)(0x42712030UL))
#define bFM4_MFS9_CSIO_SCR_RIE                    *((volatile  uint8_t *)(0x42712030UL))
#define bFM_MFS9_CSIO_SCR_SPI                     *((volatile  uint8_t *)(0x42712034UL))
#define bFM4_MFS9_CSIO_SCR_SPI                    *((volatile  uint8_t *)(0x42712034UL))
#define bFM_MFS9_CSIO_SCR_MS                      *((volatile  uint8_t *)(0x42712038UL))
#define bFM4_MFS9_CSIO_SCR_MS                     *((volatile  uint8_t *)(0x42712038UL))
#define bFM_MFS9_CSIO_SCR_UPCL                    *((volatile  uint8_t *)(0x4271203CUL))
#define bFM4_MFS9_CSIO_SCR_UPCL                   *((volatile  uint8_t *)(0x4271203CUL))

#define bFM_MFS9_CSIO_SCSCR_CSOE                  *((volatile  uint8_t *)(0x42712600UL))
#define bFM4_MFS9_CSIO_SCSCR_CSOE                 *((volatile  uint8_t *)(0x42712600UL))
#define bFM_MFS9_CSIO_SCSCR_CSEN0                 *((volatile  uint8_t *)(0x42712604UL))
#define bFM4_MFS9_CSIO_SCSCR_CSEN0                *((volatile  uint8_t *)(0x42712604UL))
#define bFM_MFS9_CSIO_SCSCR_CSEN1                 *((volatile  uint8_t *)(0x42712608UL))
#define bFM4_MFS9_CSIO_SCSCR_CSEN1                *((volatile  uint8_t *)(0x42712608UL))
#define bFM_MFS9_CSIO_SCSCR_CSEN2                 *((volatile  uint8_t *)(0x4271260CUL))
#define bFM4_MFS9_CSIO_SCSCR_CSEN2                *((volatile  uint8_t *)(0x4271260CUL))
#define bFM_MFS9_CSIO_SCSCR_CSEN3                 *((volatile  uint8_t *)(0x42712610UL))
#define bFM4_MFS9_CSIO_SCSCR_CSEN3                *((volatile  uint8_t *)(0x42712610UL))
#define bFM_MFS9_CSIO_SCSCR_CSLVL                 *((volatile  uint8_t *)(0x42712614UL))
#define bFM4_MFS9_CSIO_SCSCR_CSLVL                *((volatile  uint8_t *)(0x42712614UL))
#define bFM_MFS9_CSIO_SCSCR_SCAM                  *((volatile  uint8_t *)(0x42712624UL))
#define bFM4_MFS9_CSIO_SCSCR_SCAM                 *((volatile  uint8_t *)(0x42712624UL))

#define bFM_MFS9_CSIO_SCSFR0_CS1SPI               *((volatile  uint8_t *)(0x42712694UL))
#define bFM4_MFS9_CSIO_SCSFR0_CS1SPI              *((volatile  uint8_t *)(0x42712694UL))
#define bFM_MFS9_CSIO_SCSFR0_CS1SCINV             *((volatile  uint8_t *)(0x42712698UL))
#define bFM4_MFS9_CSIO_SCSFR0_CS1SCINV            *((volatile  uint8_t *)(0x42712698UL))
#define bFM_MFS9_CSIO_SCSFR0_CS1CSLVL             *((volatile  uint8_t *)(0x4271269CUL))
#define bFM4_MFS9_CSIO_SCSFR0_CS1CSLVL            *((volatile  uint8_t *)(0x4271269CUL))

#define bFM_MFS9_CSIO_SCSFR1_CS2SPI               *((volatile  uint8_t *)(0x427126B4UL))
#define bFM4_MFS9_CSIO_SCSFR1_CS2SPI              *((volatile  uint8_t *)(0x427126B4UL))
#define bFM_MFS9_CSIO_SCSFR1_CS2SCINV             *((volatile  uint8_t *)(0x427126B8UL))
#define bFM4_MFS9_CSIO_SCSFR1_CS2SCINV            *((volatile  uint8_t *)(0x427126B8UL))
#define bFM_MFS9_CSIO_SCSFR1_CS2CSLVL             *((volatile  uint8_t *)(0x427126BCUL))
#define bFM4_MFS9_CSIO_SCSFR1_CS2CSLVL            *((volatile  uint8_t *)(0x427126BCUL))

#define bFM_MFS9_CSIO_SCSFR2_CS3SPI               *((volatile  uint8_t *)(0x42712714UL))
#define bFM4_MFS9_CSIO_SCSFR2_CS3SPI              *((volatile  uint8_t *)(0x42712714UL))
#define bFM_MFS9_CSIO_SCSFR2_CS3SCINV             *((volatile  uint8_t *)(0x42712718UL))
#define bFM4_MFS9_CSIO_SCSFR2_CS3SCINV            *((volatile  uint8_t *)(0x42712718UL))
#define bFM_MFS9_CSIO_SCSFR2_CS3CSLVL             *((volatile  uint8_t *)(0x4271271CUL))
#define bFM4_MFS9_CSIO_SCSFR2_CS3CSLVL            *((volatile  uint8_t *)(0x4271271CUL))

#define bFM_MFS9_CSIO_SMR_SOE                     *((volatile  uint8_t *)(0x42712000UL))
#define bFM4_MFS9_CSIO_SMR_SOE                    *((volatile  uint8_t *)(0x42712000UL))
#define bFM_MFS9_CSIO_SMR_SCKE                    *((volatile  uint8_t *)(0x42712004UL))
#define bFM4_MFS9_CSIO_SMR_SCKE                   *((volatile  uint8_t *)(0x42712004UL))
#define bFM_MFS9_CSIO_SMR_BDS                     *((volatile  uint8_t *)(0x42712008UL))
#define bFM4_MFS9_CSIO_SMR_BDS                    *((volatile  uint8_t *)(0x42712008UL))
#define bFM_MFS9_CSIO_SMR_SCINV                   *((volatile  uint8_t *)(0x4271200CUL))
#define bFM4_MFS9_CSIO_SMR_SCINV                  *((volatile  uint8_t *)(0x4271200CUL))

#define bFM_MFS9_CSIO_SSR_TBI                     *((volatile  uint8_t *)(0x427120A0UL))
#define bFM4_MFS9_CSIO_SSR_TBI                    *((volatile  uint8_t *)(0x427120A0UL))
#define bFM_MFS9_CSIO_SSR_TDRE                    *((volatile  uint8_t *)(0x427120A4UL))
#define bFM4_MFS9_CSIO_SSR_TDRE                   *((volatile  uint8_t *)(0x427120A4UL))
#define bFM_MFS9_CSIO_SSR_RDRF                    *((volatile  uint8_t *)(0x427120A8UL))
#define bFM4_MFS9_CSIO_SSR_RDRF                   *((volatile  uint8_t *)(0x427120A8UL))
#define bFM_MFS9_CSIO_SSR_ORE                     *((volatile  uint8_t *)(0x427120ACUL))
#define bFM4_MFS9_CSIO_SSR_ORE                    *((volatile  uint8_t *)(0x427120ACUL))
#define bFM_MFS9_CSIO_SSR_AWC                     *((volatile  uint8_t *)(0x427120B0UL))
#define bFM4_MFS9_CSIO_SSR_AWC                    *((volatile  uint8_t *)(0x427120B0UL))
#define bFM_MFS9_CSIO_SSR_REC                     *((volatile  uint8_t *)(0x427120BCUL))
#define bFM4_MFS9_CSIO_SSR_REC                    *((volatile  uint8_t *)(0x427120BCUL))

#define bFM_MFS9_I2C_EIBCR_BEC                    *((volatile  uint8_t *)(0x427123A0UL))
#define bFM4_MFS9_I2C_EIBCR_BEC                   *((volatile  uint8_t *)(0x427123A0UL))
#define bFM_MFS9_I2C_EIBCR_SOCE                   *((volatile  uint8_t *)(0x427123A4UL))
#define bFM4_MFS9_I2C_EIBCR_SOCE                  *((volatile  uint8_t *)(0x427123A4UL))
#define bFM_MFS9_I2C_EIBCR_SCLC                   *((volatile  uint8_t *)(0x427123A8UL))
#define bFM4_MFS9_I2C_EIBCR_SCLC                  *((volatile  uint8_t *)(0x427123A8UL))
#define bFM_MFS9_I2C_EIBCR_SDAC                   *((volatile  uint8_t *)(0x427123ACUL))
#define bFM4_MFS9_I2C_EIBCR_SDAC                  *((volatile  uint8_t *)(0x427123ACUL))
#define bFM_MFS9_I2C_EIBCR_SCLS                   *((volatile  uint8_t *)(0x427123B0UL))
#define bFM4_MFS9_I2C_EIBCR_SCLS                  *((volatile  uint8_t *)(0x427123B0UL))
#define bFM_MFS9_I2C_EIBCR_SDAS                   *((volatile  uint8_t *)(0x427123B4UL))
#define bFM4_MFS9_I2C_EIBCR_SDAS                  *((volatile  uint8_t *)(0x427123B4UL))

#define bFM_MFS9_I2C_FCR_FE1                      *((volatile  uint8_t *)(0x42712280UL))
#define bFM4_MFS9_I2C_FCR_FE1                     *((volatile  uint8_t *)(0x42712280UL))
#define bFM_MFS9_I2C_FCR_FE2                      *((volatile  uint8_t *)(0x42712284UL))
#define bFM4_MFS9_I2C_FCR_FE2                     *((volatile  uint8_t *)(0x42712284UL))
#define bFM_MFS9_I2C_FCR_FCL1                     *((volatile  uint8_t *)(0x42712288UL))
#define bFM4_MFS9_I2C_FCR_FCL1                    *((volatile  uint8_t *)(0x42712288UL))
#define bFM_MFS9_I2C_FCR_FCL2                     *((volatile  uint8_t *)(0x4271228CUL))
#define bFM4_MFS9_I2C_FCR_FCL2                    *((volatile  uint8_t *)(0x4271228CUL))
#define bFM_MFS9_I2C_FCR_FSET                     *((volatile  uint8_t *)(0x42712290UL))
#define bFM4_MFS9_I2C_FCR_FSET                    *((volatile  uint8_t *)(0x42712290UL))
#define bFM_MFS9_I2C_FCR_FLD                      *((volatile  uint8_t *)(0x42712294UL))
#define bFM4_MFS9_I2C_FCR_FLD                     *((volatile  uint8_t *)(0x42712294UL))
#define bFM_MFS9_I2C_FCR_FLST                     *((volatile  uint8_t *)(0x42712298UL))
#define bFM4_MFS9_I2C_FCR_FLST                    *((volatile  uint8_t *)(0x42712298UL))
#define bFM_MFS9_I2C_FCR_FSEL                     *((volatile  uint8_t *)(0x427122A0UL))
#define bFM4_MFS9_I2C_FCR_FSEL                    *((volatile  uint8_t *)(0x427122A0UL))
#define bFM_MFS9_I2C_FCR_FTIE                     *((volatile  uint8_t *)(0x427122A4UL))
#define bFM4_MFS9_I2C_FCR_FTIE                    *((volatile  uint8_t *)(0x427122A4UL))
#define bFM_MFS9_I2C_FCR_FDRQ                     *((volatile  uint8_t *)(0x427122A8UL))
#define bFM4_MFS9_I2C_FCR_FDRQ                    *((volatile  uint8_t *)(0x427122A8UL))
#define bFM_MFS9_I2C_FCR_FRIIE                    *((volatile  uint8_t *)(0x427122ACUL))
#define bFM4_MFS9_I2C_FCR_FRIIE                   *((volatile  uint8_t *)(0x427122ACUL))
#define bFM_MFS9_I2C_FCR_FLSTE                    *((volatile  uint8_t *)(0x427122B0UL))
#define bFM4_MFS9_I2C_FCR_FLSTE                   *((volatile  uint8_t *)(0x427122B0UL))

#define bFM_MFS9_I2C_IBCR_INT                     *((volatile  uint8_t *)(0x42712020UL))
#define bFM4_MFS9_I2C_IBCR_INT                    *((volatile  uint8_t *)(0x42712020UL))
#define bFM_MFS9_I2C_IBCR_BER                     *((volatile  uint8_t *)(0x42712024UL))
#define bFM4_MFS9_I2C_IBCR_BER                    *((volatile  uint8_t *)(0x42712024UL))
#define bFM_MFS9_I2C_IBCR_INTE                    *((volatile  uint8_t *)(0x42712028UL))
#define bFM4_MFS9_I2C_IBCR_INTE                   *((volatile  uint8_t *)(0x42712028UL))
#define bFM_MFS9_I2C_IBCR_CNDE                    *((volatile  uint8_t *)(0x4271202CUL))
#define bFM4_MFS9_I2C_IBCR_CNDE                   *((volatile  uint8_t *)(0x4271202CUL))
#define bFM_MFS9_I2C_IBCR_WSEL                    *((volatile  uint8_t *)(0x42712030UL))
#define bFM4_MFS9_I2C_IBCR_WSEL                   *((volatile  uint8_t *)(0x42712030UL))
#define bFM_MFS9_I2C_IBCR_ACKE                    *((volatile  uint8_t *)(0x42712034UL))
#define bFM4_MFS9_I2C_IBCR_ACKE                   *((volatile  uint8_t *)(0x42712034UL))
#define bFM_MFS9_I2C_IBCR_ACT_SCC                 *((volatile  uint8_t *)(0x42712038UL))
#define bFM4_MFS9_I2C_IBCR_ACT_SCC                *((volatile  uint8_t *)(0x42712038UL))
#define bFM_MFS9_I2C_IBCR_MSS                     *((volatile  uint8_t *)(0x4271203CUL))
#define bFM4_MFS9_I2C_IBCR_MSS                    *((volatile  uint8_t *)(0x4271203CUL))

#define bFM_MFS9_I2C_IBSR_BB                      *((volatile  uint8_t *)(0x42712080UL))
#define bFM4_MFS9_I2C_IBSR_BB                     *((volatile  uint8_t *)(0x42712080UL))
#define bFM_MFS9_I2C_IBSR_SPC                     *((volatile  uint8_t *)(0x42712084UL))
#define bFM4_MFS9_I2C_IBSR_SPC                    *((volatile  uint8_t *)(0x42712084UL))
#define bFM_MFS9_I2C_IBSR_RSC                     *((volatile  uint8_t *)(0x42712088UL))
#define bFM4_MFS9_I2C_IBSR_RSC                    *((volatile  uint8_t *)(0x42712088UL))
#define bFM_MFS9_I2C_IBSR_AL                      *((volatile  uint8_t *)(0x4271208CUL))
#define bFM4_MFS9_I2C_IBSR_AL                     *((volatile  uint8_t *)(0x4271208CUL))
#define bFM_MFS9_I2C_IBSR_TRX                     *((volatile  uint8_t *)(0x42712090UL))
#define bFM4_MFS9_I2C_IBSR_TRX                    *((volatile  uint8_t *)(0x42712090UL))
#define bFM_MFS9_I2C_IBSR_RSA                     *((volatile  uint8_t *)(0x42712094UL))
#define bFM4_MFS9_I2C_IBSR_RSA                    *((volatile  uint8_t *)(0x42712094UL))
#define bFM_MFS9_I2C_IBSR_RACK                    *((volatile  uint8_t *)(0x42712098UL))
#define bFM4_MFS9_I2C_IBSR_RACK                   *((volatile  uint8_t *)(0x42712098UL))
#define bFM_MFS9_I2C_IBSR_FBT                     *((volatile  uint8_t *)(0x4271209CUL))
#define bFM4_MFS9_I2C_IBSR_FBT                    *((volatile  uint8_t *)(0x4271209CUL))

#define bFM_MFS9_I2C_ISBA_SAEN                    *((volatile  uint8_t *)(0x4271221CUL))
#define bFM4_MFS9_I2C_ISBA_SAEN                   *((volatile  uint8_t *)(0x4271221CUL))

#define bFM_MFS9_I2C_ISMK_EN                      *((volatile  uint8_t *)(0x4271223CUL))
#define bFM4_MFS9_I2C_ISMK_EN                     *((volatile  uint8_t *)(0x4271223CUL))

#define bFM_MFS9_I2C_SMR_TIE                      *((volatile  uint8_t *)(0x42712008UL))
#define bFM4_MFS9_I2C_SMR_TIE                     *((volatile  uint8_t *)(0x42712008UL))
#define bFM_MFS9_I2C_SMR_RIE                      *((volatile  uint8_t *)(0x4271200CUL))
#define bFM4_MFS9_I2C_SMR_RIE                     *((volatile  uint8_t *)(0x4271200CUL))

#define bFM_MFS9_I2C_SSR_TBI                      *((volatile  uint8_t *)(0x427120A0UL))
#define bFM4_MFS9_I2C_SSR_TBI                     *((volatile  uint8_t *)(0x427120A0UL))
#define bFM_MFS9_I2C_SSR_TDRE                     *((volatile  uint8_t *)(0x427120A4UL))
#define bFM4_MFS9_I2C_SSR_TDRE                    *((volatile  uint8_t *)(0x427120A4UL))
#define bFM_MFS9_I2C_SSR_RDRF                     *((volatile  uint8_t *)(0x427120A8UL))
#define bFM4_MFS9_I2C_SSR_RDRF                    *((volatile  uint8_t *)(0x427120A8UL))
#define bFM_MFS9_I2C_SSR_ORE                      *((volatile  uint8_t *)(0x427120ACUL))
#define bFM4_MFS9_I2C_SSR_ORE                     *((volatile  uint8_t *)(0x427120ACUL))
#define bFM_MFS9_I2C_SSR_TBIE                     *((volatile  uint8_t *)(0x427120B0UL))
#define bFM4_MFS9_I2C_SSR_TBIE                    *((volatile  uint8_t *)(0x427120B0UL))
#define bFM_MFS9_I2C_SSR_DMA                      *((volatile  uint8_t *)(0x427120B4UL))
#define bFM4_MFS9_I2C_SSR_DMA                     *((volatile  uint8_t *)(0x427120B4UL))
#define bFM_MFS9_I2C_SSR_TSET                     *((volatile  uint8_t *)(0x427120B8UL))
#define bFM4_MFS9_I2C_SSR_TSET                    *((volatile  uint8_t *)(0x427120B8UL))
#define bFM_MFS9_I2C_SSR_REC                      *((volatile  uint8_t *)(0x427120BCUL))
#define bFM4_MFS9_I2C_SSR_REC                     *((volatile  uint8_t *)(0x427120BCUL))

#define bFM_MFS9_LIN_BGR_EXT                      *((volatile  uint8_t *)(0x427121BCUL))
#define bFM4_MFS9_LIN_BGR_EXT                     *((volatile  uint8_t *)(0x427121BCUL))

#define bFM_MFS9_LIN_ESCR_LBIE                    *((volatile  uint8_t *)(0x42712090UL))
#define bFM4_MFS9_LIN_ESCR_LBIE                   *((volatile  uint8_t *)(0x42712090UL))
#define bFM_MFS9_LIN_ESCR_ESBL                    *((volatile  uint8_t *)(0x42712098UL))
#define bFM4_MFS9_LIN_ESCR_ESBL                   *((volatile  uint8_t *)(0x42712098UL))

#define bFM_MFS9_LIN_FCR_FE1                      *((volatile  uint8_t *)(0x42712280UL))
#define bFM4_MFS9_LIN_FCR_FE1                     *((volatile  uint8_t *)(0x42712280UL))
#define bFM_MFS9_LIN_FCR_FE2                      *((volatile  uint8_t *)(0x42712284UL))
#define bFM4_MFS9_LIN_FCR_FE2                     *((volatile  uint8_t *)(0x42712284UL))
#define bFM_MFS9_LIN_FCR_FCL1                     *((volatile  uint8_t *)(0x42712288UL))
#define bFM4_MFS9_LIN_FCR_FCL1                    *((volatile  uint8_t *)(0x42712288UL))
#define bFM_MFS9_LIN_FCR_FCL2                     *((volatile  uint8_t *)(0x4271228CUL))
#define bFM4_MFS9_LIN_FCR_FCL2                    *((volatile  uint8_t *)(0x4271228CUL))
#define bFM_MFS9_LIN_FCR_FSET                     *((volatile  uint8_t *)(0x42712290UL))
#define bFM4_MFS9_LIN_FCR_FSET                    *((volatile  uint8_t *)(0x42712290UL))
#define bFM_MFS9_LIN_FCR_FLD                      *((volatile  uint8_t *)(0x42712294UL))
#define bFM4_MFS9_LIN_FCR_FLD                     *((volatile  uint8_t *)(0x42712294UL))
#define bFM_MFS9_LIN_FCR_FLST                     *((volatile  uint8_t *)(0x42712298UL))
#define bFM4_MFS9_LIN_FCR_FLST                    *((volatile  uint8_t *)(0x42712298UL))
#define bFM_MFS9_LIN_FCR_FSEL                     *((volatile  uint8_t *)(0x427122A0UL))
#define bFM4_MFS9_LIN_FCR_FSEL                    *((volatile  uint8_t *)(0x427122A0UL))
#define bFM_MFS9_LIN_FCR_FTIE                     *((volatile  uint8_t *)(0x427122A4UL))
#define bFM4_MFS9_LIN_FCR_FTIE                    *((volatile  uint8_t *)(0x427122A4UL))
#define bFM_MFS9_LIN_FCR_FDRQ                     *((volatile  uint8_t *)(0x427122A8UL))
#define bFM4_MFS9_LIN_FCR_FDRQ                    *((volatile  uint8_t *)(0x427122A8UL))
#define bFM_MFS9_LIN_FCR_FRIIE                    *((volatile  uint8_t *)(0x427122ACUL))
#define bFM4_MFS9_LIN_FCR_FRIIE                   *((volatile  uint8_t *)(0x427122ACUL))
#define bFM_MFS9_LIN_FCR_FLSTE                    *((volatile  uint8_t *)(0x427122B0UL))
#define bFM4_MFS9_LIN_FCR_FLSTE                   *((volatile  uint8_t *)(0x427122B0UL))

#define bFM_MFS9_LIN_SCR_TXE                      *((volatile  uint8_t *)(0x42712020UL))
#define bFM4_MFS9_LIN_SCR_TXE                     *((volatile  uint8_t *)(0x42712020UL))
#define bFM_MFS9_LIN_SCR_RXE                      *((volatile  uint8_t *)(0x42712024UL))
#define bFM4_MFS9_LIN_SCR_RXE                     *((volatile  uint8_t *)(0x42712024UL))
#define bFM_MFS9_LIN_SCR_TBIE                     *((volatile  uint8_t *)(0x42712028UL))
#define bFM4_MFS9_LIN_SCR_TBIE                    *((volatile  uint8_t *)(0x42712028UL))
#define bFM_MFS9_LIN_SCR_TIE                      *((volatile  uint8_t *)(0x4271202CUL))
#define bFM4_MFS9_LIN_SCR_TIE                     *((volatile  uint8_t *)(0x4271202CUL))
#define bFM_MFS9_LIN_SCR_RIE                      *((volatile  uint8_t *)(0x42712030UL))
#define bFM4_MFS9_LIN_SCR_RIE                     *((volatile  uint8_t *)(0x42712030UL))
#define bFM_MFS9_LIN_SCR_LBR                      *((volatile  uint8_t *)(0x42712034UL))
#define bFM4_MFS9_LIN_SCR_LBR                     *((volatile  uint8_t *)(0x42712034UL))
#define bFM_MFS9_LIN_SCR_MS                       *((volatile  uint8_t *)(0x42712038UL))
#define bFM4_MFS9_LIN_SCR_MS                      *((volatile  uint8_t *)(0x42712038UL))
#define bFM_MFS9_LIN_SCR_UPCL                     *((volatile  uint8_t *)(0x4271203CUL))
#define bFM4_MFS9_LIN_SCR_UPCL                    *((volatile  uint8_t *)(0x4271203CUL))

#define bFM_MFS9_LIN_SMR_SOE                      *((volatile  uint8_t *)(0x42712000UL))
#define bFM4_MFS9_LIN_SMR_SOE                     *((volatile  uint8_t *)(0x42712000UL))
#define bFM_MFS9_LIN_SMR_SBL                      *((volatile  uint8_t *)(0x4271200CUL))
#define bFM4_MFS9_LIN_SMR_SBL                     *((volatile  uint8_t *)(0x4271200CUL))
#define bFM_MFS9_LIN_SMR_WUCR                     *((volatile  uint8_t *)(0x42712010UL))
#define bFM4_MFS9_LIN_SMR_WUCR                    *((volatile  uint8_t *)(0x42712010UL))

#define bFM_MFS9_LIN_SSR_TBI                      *((volatile  uint8_t *)(0x427120A0UL))
#define bFM4_MFS9_LIN_SSR_TBI                     *((volatile  uint8_t *)(0x427120A0UL))
#define bFM_MFS9_LIN_SSR_TDRE                     *((volatile  uint8_t *)(0x427120A4UL))
#define bFM4_MFS9_LIN_SSR_TDRE                    *((volatile  uint8_t *)(0x427120A4UL))
#define bFM_MFS9_LIN_SSR_RDRF                     *((volatile  uint8_t *)(0x427120A8UL))
#define bFM4_MFS9_LIN_SSR_RDRF                    *((volatile  uint8_t *)(0x427120A8UL))
#define bFM_MFS9_LIN_SSR_ORE                      *((volatile  uint8_t *)(0x427120ACUL))
#define bFM4_MFS9_LIN_SSR_ORE                     *((volatile  uint8_t *)(0x427120ACUL))
#define bFM_MFS9_LIN_SSR_FRE                      *((volatile  uint8_t *)(0x427120B0UL))
#define bFM4_MFS9_LIN_SSR_FRE                     *((volatile  uint8_t *)(0x427120B0UL))
#define bFM_MFS9_LIN_SSR_LBD                      *((volatile  uint8_t *)(0x427120B4UL))
#define bFM4_MFS9_LIN_SSR_LBD                     *((volatile  uint8_t *)(0x427120B4UL))
#define bFM_MFS9_LIN_SSR_REC                      *((volatile  uint8_t *)(0x427120BCUL))
#define bFM4_MFS9_LIN_SSR_REC                     *((volatile  uint8_t *)(0x427120BCUL))

#define bFM_MFS9_UART_BGR_EXT                     *((volatile  uint8_t *)(0x427121BCUL))
#define bFM4_MFS9_UART_BGR_EXT                    *((volatile  uint8_t *)(0x427121BCUL))

#define bFM_MFS9_UART_ESCR_P                      *((volatile  uint8_t *)(0x4271208CUL))
#define bFM4_MFS9_UART_ESCR_P                     *((volatile  uint8_t *)(0x4271208CUL))
#define bFM_MFS9_UART_ESCR_PEN                    *((volatile  uint8_t *)(0x42712090UL))
#define bFM4_MFS9_UART_ESCR_PEN                   *((volatile  uint8_t *)(0x42712090UL))
#define bFM_MFS9_UART_ESCR_INV                    *((volatile  uint8_t *)(0x42712094UL))
#define bFM4_MFS9_UART_ESCR_INV                   *((volatile  uint8_t *)(0x42712094UL))
#define bFM_MFS9_UART_ESCR_ESBL                   *((volatile  uint8_t *)(0x42712098UL))
#define bFM4_MFS9_UART_ESCR_ESBL                  *((volatile  uint8_t *)(0x42712098UL))
#define bFM_MFS9_UART_ESCR_FLWEN                  *((volatile  uint8_t *)(0x4271209CUL))
#define bFM4_MFS9_UART_ESCR_FLWEN                 *((volatile  uint8_t *)(0x4271209CUL))

#define bFM_MFS9_UART_FCR_FE1                     *((volatile  uint8_t *)(0x42712280UL))
#define bFM4_MFS9_UART_FCR_FE1                    *((volatile  uint8_t *)(0x42712280UL))
#define bFM_MFS9_UART_FCR_FE2                     *((volatile  uint8_t *)(0x42712284UL))
#define bFM4_MFS9_UART_FCR_FE2                    *((volatile  uint8_t *)(0x42712284UL))
#define bFM_MFS9_UART_FCR_FCL1                    *((volatile  uint8_t *)(0x42712288UL))
#define bFM4_MFS9_UART_FCR_FCL1                   *((volatile  uint8_t *)(0x42712288UL))
#define bFM_MFS9_UART_FCR_FCL2                    *((volatile  uint8_t *)(0x4271228CUL))
#define bFM4_MFS9_UART_FCR_FCL2                   *((volatile  uint8_t *)(0x4271228CUL))
#define bFM_MFS9_UART_FCR_FSET                    *((volatile  uint8_t *)(0x42712290UL))
#define bFM4_MFS9_UART_FCR_FSET                   *((volatile  uint8_t *)(0x42712290UL))
#define bFM_MFS9_UART_FCR_FLD                     *((volatile  uint8_t *)(0x42712294UL))
#define bFM4_MFS9_UART_FCR_FLD                    *((volatile  uint8_t *)(0x42712294UL))
#define bFM_MFS9_UART_FCR_FLST                    *((volatile  uint8_t *)(0x42712298UL))
#define bFM4_MFS9_UART_FCR_FLST                   *((volatile  uint8_t *)(0x42712298UL))
#define bFM_MFS9_UART_FCR_FSEL                    *((volatile  uint8_t *)(0x427122A0UL))
#define bFM4_MFS9_UART_FCR_FSEL                   *((volatile  uint8_t *)(0x427122A0UL))
#define bFM_MFS9_UART_FCR_FTIE                    *((volatile  uint8_t *)(0x427122A4UL))
#define bFM4_MFS9_UART_FCR_FTIE                   *((volatile  uint8_t *)(0x427122A4UL))
#define bFM_MFS9_UART_FCR_FDRQ                    *((volatile  uint8_t *)(0x427122A8UL))
#define bFM4_MFS9_UART_FCR_FDRQ                   *((volatile  uint8_t *)(0x427122A8UL))
#define bFM_MFS9_UART_FCR_FRIIE                   *((volatile  uint8_t *)(0x427122ACUL))
#define bFM4_MFS9_UART_FCR_FRIIE                  *((volatile  uint8_t *)(0x427122ACUL))
#define bFM_MFS9_UART_FCR_FLSTE                   *((volatile  uint8_t *)(0x427122B0UL))
#define bFM4_MFS9_UART_FCR_FLSTE                  *((volatile  uint8_t *)(0x427122B0UL))

#define bFM_MFS9_UART_SCR_TXE                     *((volatile  uint8_t *)(0x42712020UL))
#define bFM4_MFS9_UART_SCR_TXE                    *((volatile  uint8_t *)(0x42712020UL))
#define bFM_MFS9_UART_SCR_RXE                     *((volatile  uint8_t *)(0x42712024UL))
#define bFM4_MFS9_UART_SCR_RXE                    *((volatile  uint8_t *)(0x42712024UL))
#define bFM_MFS9_UART_SCR_TBIE                    *((volatile  uint8_t *)(0x42712028UL))
#define bFM4_MFS9_UART_SCR_TBIE                   *((volatile  uint8_t *)(0x42712028UL))
#define bFM_MFS9_UART_SCR_TIE                     *((volatile  uint8_t *)(0x4271202CUL))
#define bFM4_MFS9_UART_SCR_TIE                    *((volatile  uint8_t *)(0x4271202CUL))
#define bFM_MFS9_UART_SCR_RIE                     *((volatile  uint8_t *)(0x42712030UL))
#define bFM4_MFS9_UART_SCR_RIE                    *((volatile  uint8_t *)(0x42712030UL))
#define bFM_MFS9_UART_SCR_UPCL                    *((volatile  uint8_t *)(0x4271203CUL))
#define bFM4_MFS9_UART_SCR_UPCL                   *((volatile  uint8_t *)(0x4271203CUL))

#define bFM_MFS9_UART_SMR_SOE                     *((volatile  uint8_t *)(0x42712000UL))
#define bFM4_MFS9_UART_SMR_SOE                    *((volatile  uint8_t *)(0x42712000UL))
#define bFM_MFS9_UART_SMR_BDS                     *((volatile  uint8_t *)(0x42712008UL))
#define bFM4_MFS9_UART_SMR_BDS                    *((volatile  uint8_t *)(0x42712008UL))
#define bFM_MFS9_UART_SMR_SBL                     *((volatile  uint8_t *)(0x4271200CUL))
#define bFM4_MFS9_UART_SMR_SBL                    *((volatile  uint8_t *)(0x4271200CUL))

#define bFM_MFS9_UART_SSR_TBI                     *((volatile  uint8_t *)(0x427120A0UL))
#define bFM4_MFS9_UART_SSR_TBI                    *((volatile  uint8_t *)(0x427120A0UL))
#define bFM_MFS9_UART_SSR_TDRE                    *((volatile  uint8_t *)(0x427120A4UL))
#define bFM4_MFS9_UART_SSR_TDRE                   *((volatile  uint8_t *)(0x427120A4UL))
#define bFM_MFS9_UART_SSR_RDRF                    *((volatile  uint8_t *)(0x427120A8UL))
#define bFM4_MFS9_UART_SSR_RDRF                   *((volatile  uint8_t *)(0x427120A8UL))
#define bFM_MFS9_UART_SSR_ORE                     *((volatile  uint8_t *)(0x427120ACUL))
#define bFM4_MFS9_UART_SSR_ORE                    *((volatile  uint8_t *)(0x427120ACUL))
#define bFM_MFS9_UART_SSR_FRE                     *((volatile  uint8_t *)(0x427120B0UL))
#define bFM4_MFS9_UART_SSR_FRE                    *((volatile  uint8_t *)(0x427120B0UL))
#define bFM_MFS9_UART_SSR_PE                      *((volatile  uint8_t *)(0x427120B4UL))
#define bFM4_MFS9_UART_SSR_PE                     *((volatile  uint8_t *)(0x427120B4UL))
#define bFM_MFS9_UART_SSR_REC                     *((volatile  uint8_t *)(0x427120BCUL))
#define bFM4_MFS9_UART_SSR_REC                    *((volatile  uint8_t *)(0x427120BCUL))


/*******************************************************************************
* MFT_PPG Registers MFT_PPG
*   Bitband Section
*******************************************************************************/
#define bFM_MFT_PPG_GATEC0_EDGE0                  *((volatile  uint8_t *)(0x42484300UL))
#define bFM4_MFT_PPG_GATEC0_EDGE0                 *((volatile  uint8_t *)(0x42484300UL))
#define bFM_MFT_PPG_GATEC0_STRG0                  *((volatile  uint8_t *)(0x42484304UL))
#define bFM4_MFT_PPG_GATEC0_STRG0                 *((volatile  uint8_t *)(0x42484304UL))
#define bFM_MFT_PPG_GATEC0_EDGE2                  *((volatile  uint8_t *)(0x42484310UL))
#define bFM4_MFT_PPG_GATEC0_EDGE2                 *((volatile  uint8_t *)(0x42484310UL))
#define bFM_MFT_PPG_GATEC0_STRG2                  *((volatile  uint8_t *)(0x42484314UL))
#define bFM4_MFT_PPG_GATEC0_STRG2                 *((volatile  uint8_t *)(0x42484314UL))

#define bFM_MFT_PPG_GATEC12_EDGE12                *((volatile  uint8_t *)(0x42485B00UL))
#define bFM4_MFT_PPG_GATEC12_EDGE12               *((volatile  uint8_t *)(0x42485B00UL))
#define bFM_MFT_PPG_GATEC12_STRG12                *((volatile  uint8_t *)(0x42485B04UL))
#define bFM4_MFT_PPG_GATEC12_STRG12               *((volatile  uint8_t *)(0x42485B04UL))
#define bFM_MFT_PPG_GATEC12_EDGE14                *((volatile  uint8_t *)(0x42485B10UL))
#define bFM4_MFT_PPG_GATEC12_EDGE14               *((volatile  uint8_t *)(0x42485B10UL))
#define bFM_MFT_PPG_GATEC12_STRG14                *((volatile  uint8_t *)(0x42485B14UL))
#define bFM4_MFT_PPG_GATEC12_STRG14               *((volatile  uint8_t *)(0x42485B14UL))

#define bFM_MFT_PPG_GATEC16_EDGE16                *((volatile  uint8_t *)(0x42486300UL))
#define bFM4_MFT_PPG_GATEC16_EDGE16               *((volatile  uint8_t *)(0x42486300UL))
#define bFM_MFT_PPG_GATEC16_STRG16                *((volatile  uint8_t *)(0x42486304UL))
#define bFM4_MFT_PPG_GATEC16_STRG16               *((volatile  uint8_t *)(0x42486304UL))
#define bFM_MFT_PPG_GATEC16_EDGE18                *((volatile  uint8_t *)(0x42486310UL))
#define bFM4_MFT_PPG_GATEC16_EDGE18               *((volatile  uint8_t *)(0x42486310UL))
#define bFM_MFT_PPG_GATEC16_STRG18                *((volatile  uint8_t *)(0x42486314UL))
#define bFM4_MFT_PPG_GATEC16_STRG18               *((volatile  uint8_t *)(0x42486314UL))

#define bFM_MFT_PPG_GATEC20_EDGE20                *((volatile  uint8_t *)(0x42486B00UL))
#define bFM4_MFT_PPG_GATEC20_EDGE20               *((volatile  uint8_t *)(0x42486B00UL))
#define bFM_MFT_PPG_GATEC20_STRG20                *((volatile  uint8_t *)(0x42486B04UL))
#define bFM4_MFT_PPG_GATEC20_STRG20               *((volatile  uint8_t *)(0x42486B04UL))
#define bFM_MFT_PPG_GATEC20_EDGE22                *((volatile  uint8_t *)(0x42486B10UL))
#define bFM4_MFT_PPG_GATEC20_EDGE22               *((volatile  uint8_t *)(0x42486B10UL))
#define bFM_MFT_PPG_GATEC20_STRG22                *((volatile  uint8_t *)(0x42486B14UL))
#define bFM4_MFT_PPG_GATEC20_STRG22               *((volatile  uint8_t *)(0x42486B14UL))

#define bFM_MFT_PPG_GATEC4_EDGE4                  *((volatile  uint8_t *)(0x42484B00UL))
#define bFM4_MFT_PPG_GATEC4_EDGE4                 *((volatile  uint8_t *)(0x42484B00UL))
#define bFM_MFT_PPG_GATEC4_STRG4                  *((volatile  uint8_t *)(0x42484B04UL))
#define bFM4_MFT_PPG_GATEC4_STRG4                 *((volatile  uint8_t *)(0x42484B04UL))
#define bFM_MFT_PPG_GATEC4_EDGE6                  *((volatile  uint8_t *)(0x42484B10UL))
#define bFM4_MFT_PPG_GATEC4_EDGE6                 *((volatile  uint8_t *)(0x42484B10UL))
#define bFM_MFT_PPG_GATEC4_STRG6                  *((volatile  uint8_t *)(0x42484B14UL))
#define bFM4_MFT_PPG_GATEC4_STRG6                 *((volatile  uint8_t *)(0x42484B14UL))

#define bFM_MFT_PPG_GATEC8_EDGE8                  *((volatile  uint8_t *)(0x42485300UL))
#define bFM4_MFT_PPG_GATEC8_EDGE8                 *((volatile  uint8_t *)(0x42485300UL))
#define bFM_MFT_PPG_GATEC8_STRG8                  *((volatile  uint8_t *)(0x42485304UL))
#define bFM4_MFT_PPG_GATEC8_STRG8                 *((volatile  uint8_t *)(0x42485304UL))
#define bFM_MFT_PPG_GATEC8_EDGE10                 *((volatile  uint8_t *)(0x42485310UL))
#define bFM4_MFT_PPG_GATEC8_EDGE10                *((volatile  uint8_t *)(0x42485310UL))
#define bFM_MFT_PPG_GATEC8_STRG10                 *((volatile  uint8_t *)(0x42485314UL))
#define bFM4_MFT_PPG_GATEC8_STRG10                *((volatile  uint8_t *)(0x42485314UL))

#define bFM_MFT_PPG_PPGC0_TTRG                    *((volatile  uint8_t *)(0x42484020UL))
#define bFM4_MFT_PPG_PPGC0_TTRG                   *((volatile  uint8_t *)(0x42484020UL))
#define bFM_MFT_PPG_PPGC0_INTM                    *((volatile  uint8_t *)(0x42484034UL))
#define bFM4_MFT_PPG_PPGC0_INTM                   *((volatile  uint8_t *)(0x42484034UL))
#define bFM_MFT_PPG_PPGC0_PUF                     *((volatile  uint8_t *)(0x42484038UL))
#define bFM4_MFT_PPG_PPGC0_PUF                    *((volatile  uint8_t *)(0x42484038UL))
#define bFM_MFT_PPG_PPGC0_PIE                     *((volatile  uint8_t *)(0x4248403CUL))
#define bFM4_MFT_PPG_PPGC0_PIE                    *((volatile  uint8_t *)(0x4248403CUL))

#define bFM_MFT_PPG_PPGC1_INTM                    *((volatile  uint8_t *)(0x42484014UL))
#define bFM4_MFT_PPG_PPGC1_INTM                   *((volatile  uint8_t *)(0x42484014UL))
#define bFM_MFT_PPG_PPGC1_PUF                     *((volatile  uint8_t *)(0x42484018UL))
#define bFM4_MFT_PPG_PPGC1_PUF                    *((volatile  uint8_t *)(0x42484018UL))
#define bFM_MFT_PPG_PPGC1_PIE                     *((volatile  uint8_t *)(0x4248401CUL))
#define bFM4_MFT_PPG_PPGC1_PIE                    *((volatile  uint8_t *)(0x4248401CUL))

#define bFM_MFT_PPG_PPGC10_TTRG                   *((volatile  uint8_t *)(0x424850A0UL))
#define bFM4_MFT_PPG_PPGC10_TTRG                  *((volatile  uint8_t *)(0x424850A0UL))
#define bFM_MFT_PPG_PPGC10_INTM                   *((volatile  uint8_t *)(0x424850B4UL))
#define bFM4_MFT_PPG_PPGC10_INTM                  *((volatile  uint8_t *)(0x424850B4UL))
#define bFM_MFT_PPG_PPGC10_PUF                    *((volatile  uint8_t *)(0x424850B8UL))
#define bFM4_MFT_PPG_PPGC10_PUF                   *((volatile  uint8_t *)(0x424850B8UL))
#define bFM_MFT_PPG_PPGC10_PIE                    *((volatile  uint8_t *)(0x424850BCUL))
#define bFM4_MFT_PPG_PPGC10_PIE                   *((volatile  uint8_t *)(0x424850BCUL))

#define bFM_MFT_PPG_PPGC11_INTM                   *((volatile  uint8_t *)(0x42485094UL))
#define bFM4_MFT_PPG_PPGC11_INTM                  *((volatile  uint8_t *)(0x42485094UL))
#define bFM_MFT_PPG_PPGC11_PUF                    *((volatile  uint8_t *)(0x42485098UL))
#define bFM4_MFT_PPG_PPGC11_PUF                   *((volatile  uint8_t *)(0x42485098UL))
#define bFM_MFT_PPG_PPGC11_PIE                    *((volatile  uint8_t *)(0x4248509CUL))
#define bFM4_MFT_PPG_PPGC11_PIE                   *((volatile  uint8_t *)(0x4248509CUL))

#define bFM_MFT_PPG_PPGC12_TTRG                   *((volatile  uint8_t *)(0x42485820UL))
#define bFM4_MFT_PPG_PPGC12_TTRG                  *((volatile  uint8_t *)(0x42485820UL))
#define bFM_MFT_PPG_PPGC12_INTM                   *((volatile  uint8_t *)(0x42485834UL))
#define bFM4_MFT_PPG_PPGC12_INTM                  *((volatile  uint8_t *)(0x42485834UL))
#define bFM_MFT_PPG_PPGC12_PUF                    *((volatile  uint8_t *)(0x42485838UL))
#define bFM4_MFT_PPG_PPGC12_PUF                   *((volatile  uint8_t *)(0x42485838UL))
#define bFM_MFT_PPG_PPGC12_PIE                    *((volatile  uint8_t *)(0x4248583CUL))
#define bFM4_MFT_PPG_PPGC12_PIE                   *((volatile  uint8_t *)(0x4248583CUL))

#define bFM_MFT_PPG_PPGC13_INTM                   *((volatile  uint8_t *)(0x42485814UL))
#define bFM4_MFT_PPG_PPGC13_INTM                  *((volatile  uint8_t *)(0x42485814UL))
#define bFM_MFT_PPG_PPGC13_PUF                    *((volatile  uint8_t *)(0x42485818UL))
#define bFM4_MFT_PPG_PPGC13_PUF                   *((volatile  uint8_t *)(0x42485818UL))
#define bFM_MFT_PPG_PPGC13_PIE                    *((volatile  uint8_t *)(0x4248581CUL))
#define bFM4_MFT_PPG_PPGC13_PIE                   *((volatile  uint8_t *)(0x4248581CUL))

#define bFM_MFT_PPG_PPGC14_TTRG                   *((volatile  uint8_t *)(0x424858A0UL))
#define bFM4_MFT_PPG_PPGC14_TTRG                  *((volatile  uint8_t *)(0x424858A0UL))
#define bFM_MFT_PPG_PPGC14_INTM                   *((volatile  uint8_t *)(0x424858B4UL))
#define bFM4_MFT_PPG_PPGC14_INTM                  *((volatile  uint8_t *)(0x424858B4UL))
#define bFM_MFT_PPG_PPGC14_PUF                    *((volatile  uint8_t *)(0x424858B8UL))
#define bFM4_MFT_PPG_PPGC14_PUF                   *((volatile  uint8_t *)(0x424858B8UL))
#define bFM_MFT_PPG_PPGC14_PIE                    *((volatile  uint8_t *)(0x424858BCUL))
#define bFM4_MFT_PPG_PPGC14_PIE                   *((volatile  uint8_t *)(0x424858BCUL))

#define bFM_MFT_PPG_PPGC15_INTM                   *((volatile  uint8_t *)(0x42485894UL))
#define bFM4_MFT_PPG_PPGC15_INTM                  *((volatile  uint8_t *)(0x42485894UL))
#define bFM_MFT_PPG_PPGC15_PUF                    *((volatile  uint8_t *)(0x42485898UL))
#define bFM4_MFT_PPG_PPGC15_PUF                   *((volatile  uint8_t *)(0x42485898UL))
#define bFM_MFT_PPG_PPGC15_PIE                    *((volatile  uint8_t *)(0x4248589CUL))
#define bFM4_MFT_PPG_PPGC15_PIE                   *((volatile  uint8_t *)(0x4248589CUL))

#define bFM_MFT_PPG_PPGC16_TTRG                   *((volatile  uint8_t *)(0x42486020UL))
#define bFM4_MFT_PPG_PPGC16_TTRG                  *((volatile  uint8_t *)(0x42486020UL))
#define bFM_MFT_PPG_PPGC16_INTM                   *((volatile  uint8_t *)(0x42486034UL))
#define bFM4_MFT_PPG_PPGC16_INTM                  *((volatile  uint8_t *)(0x42486034UL))
#define bFM_MFT_PPG_PPGC16_PUF                    *((volatile  uint8_t *)(0x42486038UL))
#define bFM4_MFT_PPG_PPGC16_PUF                   *((volatile  uint8_t *)(0x42486038UL))
#define bFM_MFT_PPG_PPGC16_PIE                    *((volatile  uint8_t *)(0x4248603CUL))
#define bFM4_MFT_PPG_PPGC16_PIE                   *((volatile  uint8_t *)(0x4248603CUL))

#define bFM_MFT_PPG_PPGC17_INTM                   *((volatile  uint8_t *)(0x42486014UL))
#define bFM4_MFT_PPG_PPGC17_INTM                  *((volatile  uint8_t *)(0x42486014UL))
#define bFM_MFT_PPG_PPGC17_PUF                    *((volatile  uint8_t *)(0x42486018UL))
#define bFM4_MFT_PPG_PPGC17_PUF                   *((volatile  uint8_t *)(0x42486018UL))
#define bFM_MFT_PPG_PPGC17_PIE                    *((volatile  uint8_t *)(0x4248601CUL))
#define bFM4_MFT_PPG_PPGC17_PIE                   *((volatile  uint8_t *)(0x4248601CUL))

#define bFM_MFT_PPG_PPGC18_TTRG                   *((volatile  uint8_t *)(0x424860A0UL))
#define bFM4_MFT_PPG_PPGC18_TTRG                  *((volatile  uint8_t *)(0x424860A0UL))
#define bFM_MFT_PPG_PPGC18_INTM                   *((volatile  uint8_t *)(0x424860B4UL))
#define bFM4_MFT_PPG_PPGC18_INTM                  *((volatile  uint8_t *)(0x424860B4UL))
#define bFM_MFT_PPG_PPGC18_PUF                    *((volatile  uint8_t *)(0x424860B8UL))
#define bFM4_MFT_PPG_PPGC18_PUF                   *((volatile  uint8_t *)(0x424860B8UL))
#define bFM_MFT_PPG_PPGC18_PIE                    *((volatile  uint8_t *)(0x424860BCUL))
#define bFM4_MFT_PPG_PPGC18_PIE                   *((volatile  uint8_t *)(0x424860BCUL))

#define bFM_MFT_PPG_PPGC19_INTM                   *((volatile  uint8_t *)(0x42486094UL))
#define bFM4_MFT_PPG_PPGC19_INTM                  *((volatile  uint8_t *)(0x42486094UL))
#define bFM_MFT_PPG_PPGC19_PUF                    *((volatile  uint8_t *)(0x42486098UL))
#define bFM4_MFT_PPG_PPGC19_PUF                   *((volatile  uint8_t *)(0x42486098UL))
#define bFM_MFT_PPG_PPGC19_PIE                    *((volatile  uint8_t *)(0x4248609CUL))
#define bFM4_MFT_PPG_PPGC19_PIE                   *((volatile  uint8_t *)(0x4248609CUL))

#define bFM_MFT_PPG_PPGC2_TTRG                    *((volatile  uint8_t *)(0x424840A0UL))
#define bFM4_MFT_PPG_PPGC2_TTRG                   *((volatile  uint8_t *)(0x424840A0UL))
#define bFM_MFT_PPG_PPGC2_INTM                    *((volatile  uint8_t *)(0x424840B4UL))
#define bFM4_MFT_PPG_PPGC2_INTM                   *((volatile  uint8_t *)(0x424840B4UL))
#define bFM_MFT_PPG_PPGC2_PUF                     *((volatile  uint8_t *)(0x424840B8UL))
#define bFM4_MFT_PPG_PPGC2_PUF                    *((volatile  uint8_t *)(0x424840B8UL))
#define bFM_MFT_PPG_PPGC2_PIE                     *((volatile  uint8_t *)(0x424840BCUL))
#define bFM4_MFT_PPG_PPGC2_PIE                    *((volatile  uint8_t *)(0x424840BCUL))

#define bFM_MFT_PPG_PPGC20_TTRG                   *((volatile  uint8_t *)(0x42486820UL))
#define bFM4_MFT_PPG_PPGC20_TTRG                  *((volatile  uint8_t *)(0x42486820UL))
#define bFM_MFT_PPG_PPGC20_INTM                   *((volatile  uint8_t *)(0x42486834UL))
#define bFM4_MFT_PPG_PPGC20_INTM                  *((volatile  uint8_t *)(0x42486834UL))
#define bFM_MFT_PPG_PPGC20_PUF                    *((volatile  uint8_t *)(0x42486838UL))
#define bFM4_MFT_PPG_PPGC20_PUF                   *((volatile  uint8_t *)(0x42486838UL))
#define bFM_MFT_PPG_PPGC20_PIE                    *((volatile  uint8_t *)(0x4248683CUL))
#define bFM4_MFT_PPG_PPGC20_PIE                   *((volatile  uint8_t *)(0x4248683CUL))

#define bFM_MFT_PPG_PPGC21_INTM                   *((volatile  uint8_t *)(0x42486814UL))
#define bFM4_MFT_PPG_PPGC21_INTM                  *((volatile  uint8_t *)(0x42486814UL))
#define bFM_MFT_PPG_PPGC21_PUF                    *((volatile  uint8_t *)(0x42486818UL))
#define bFM4_MFT_PPG_PPGC21_PUF                   *((volatile  uint8_t *)(0x42486818UL))
#define bFM_MFT_PPG_PPGC21_PIE                    *((volatile  uint8_t *)(0x4248681CUL))
#define bFM4_MFT_PPG_PPGC21_PIE                   *((volatile  uint8_t *)(0x4248681CUL))

#define bFM_MFT_PPG_PPGC22_TTRG                   *((volatile  uint8_t *)(0x424868A0UL))
#define bFM4_MFT_PPG_PPGC22_TTRG                  *((volatile  uint8_t *)(0x424868A0UL))
#define bFM_MFT_PPG_PPGC22_INTM                   *((volatile  uint8_t *)(0x424868B4UL))
#define bFM4_MFT_PPG_PPGC22_INTM                  *((volatile  uint8_t *)(0x424868B4UL))
#define bFM_MFT_PPG_PPGC22_PUF                    *((volatile  uint8_t *)(0x424868B8UL))
#define bFM4_MFT_PPG_PPGC22_PUF                   *((volatile  uint8_t *)(0x424868B8UL))
#define bFM_MFT_PPG_PPGC22_PIE                    *((volatile  uint8_t *)(0x424868BCUL))
#define bFM4_MFT_PPG_PPGC22_PIE                   *((volatile  uint8_t *)(0x424868BCUL))

#define bFM_MFT_PPG_PPGC23_INTM                   *((volatile  uint8_t *)(0x42486894UL))
#define bFM4_MFT_PPG_PPGC23_INTM                  *((volatile  uint8_t *)(0x42486894UL))
#define bFM_MFT_PPG_PPGC23_PUF                    *((volatile  uint8_t *)(0x42486898UL))
#define bFM4_MFT_PPG_PPGC23_PUF                   *((volatile  uint8_t *)(0x42486898UL))
#define bFM_MFT_PPG_PPGC23_PIE                    *((volatile  uint8_t *)(0x4248689CUL))
#define bFM4_MFT_PPG_PPGC23_PIE                   *((volatile  uint8_t *)(0x4248689CUL))

#define bFM_MFT_PPG_PPGC3_INTM                    *((volatile  uint8_t *)(0x42484094UL))
#define bFM4_MFT_PPG_PPGC3_INTM                   *((volatile  uint8_t *)(0x42484094UL))
#define bFM_MFT_PPG_PPGC3_PUF                     *((volatile  uint8_t *)(0x42484098UL))
#define bFM4_MFT_PPG_PPGC3_PUF                    *((volatile  uint8_t *)(0x42484098UL))
#define bFM_MFT_PPG_PPGC3_PIE                     *((volatile  uint8_t *)(0x4248409CUL))
#define bFM4_MFT_PPG_PPGC3_PIE                    *((volatile  uint8_t *)(0x4248409CUL))

#define bFM_MFT_PPG_PPGC4_TTRG                    *((volatile  uint8_t *)(0x42484820UL))
#define bFM4_MFT_PPG_PPGC4_TTRG                   *((volatile  uint8_t *)(0x42484820UL))
#define bFM_MFT_PPG_PPGC4_INTM                    *((volatile  uint8_t *)(0x42484834UL))
#define bFM4_MFT_PPG_PPGC4_INTM                   *((volatile  uint8_t *)(0x42484834UL))
#define bFM_MFT_PPG_PPGC4_PUF                     *((volatile  uint8_t *)(0x42484838UL))
#define bFM4_MFT_PPG_PPGC4_PUF                    *((volatile  uint8_t *)(0x42484838UL))
#define bFM_MFT_PPG_PPGC4_PIE                     *((volatile  uint8_t *)(0x4248483CUL))
#define bFM4_MFT_PPG_PPGC4_PIE                    *((volatile  uint8_t *)(0x4248483CUL))

#define bFM_MFT_PPG_PPGC5_INTM                    *((volatile  uint8_t *)(0x42484814UL))
#define bFM4_MFT_PPG_PPGC5_INTM                   *((volatile  uint8_t *)(0x42484814UL))
#define bFM_MFT_PPG_PPGC5_PUF                     *((volatile  uint8_t *)(0x42484818UL))
#define bFM4_MFT_PPG_PPGC5_PUF                    *((volatile  uint8_t *)(0x42484818UL))
#define bFM_MFT_PPG_PPGC5_PIE                     *((volatile  uint8_t *)(0x4248481CUL))
#define bFM4_MFT_PPG_PPGC5_PIE                    *((volatile  uint8_t *)(0x4248481CUL))

#define bFM_MFT_PPG_PPGC6_TTRG                    *((volatile  uint8_t *)(0x424848A0UL))
#define bFM4_MFT_PPG_PPGC6_TTRG                   *((volatile  uint8_t *)(0x424848A0UL))
#define bFM_MFT_PPG_PPGC6_INTM                    *((volatile  uint8_t *)(0x424848B4UL))
#define bFM4_MFT_PPG_PPGC6_INTM                   *((volatile  uint8_t *)(0x424848B4UL))
#define bFM_MFT_PPG_PPGC6_PUF                     *((volatile  uint8_t *)(0x424848B8UL))
#define bFM4_MFT_PPG_PPGC6_PUF                    *((volatile  uint8_t *)(0x424848B8UL))
#define bFM_MFT_PPG_PPGC6_PIE                     *((volatile  uint8_t *)(0x424848BCUL))
#define bFM4_MFT_PPG_PPGC6_PIE                    *((volatile  uint8_t *)(0x424848BCUL))

#define bFM_MFT_PPG_PPGC7_INTM                    *((volatile  uint8_t *)(0x42484894UL))
#define bFM4_MFT_PPG_PPGC7_INTM                   *((volatile  uint8_t *)(0x42484894UL))
#define bFM_MFT_PPG_PPGC7_PUF                     *((volatile  uint8_t *)(0x42484898UL))
#define bFM4_MFT_PPG_PPGC7_PUF                    *((volatile  uint8_t *)(0x42484898UL))
#define bFM_MFT_PPG_PPGC7_PIE                     *((volatile  uint8_t *)(0x4248489CUL))
#define bFM4_MFT_PPG_PPGC7_PIE                    *((volatile  uint8_t *)(0x4248489CUL))

#define bFM_MFT_PPG_PPGC8_TTRG                    *((volatile  uint8_t *)(0x42485020UL))
#define bFM4_MFT_PPG_PPGC8_TTRG                   *((volatile  uint8_t *)(0x42485020UL))
#define bFM_MFT_PPG_PPGC8_INTM                    *((volatile  uint8_t *)(0x42485034UL))
#define bFM4_MFT_PPG_PPGC8_INTM                   *((volatile  uint8_t *)(0x42485034UL))
#define bFM_MFT_PPG_PPGC8_PUF                     *((volatile  uint8_t *)(0x42485038UL))
#define bFM4_MFT_PPG_PPGC8_PUF                    *((volatile  uint8_t *)(0x42485038UL))
#define bFM_MFT_PPG_PPGC8_PIE                     *((volatile  uint8_t *)(0x4248503CUL))
#define bFM4_MFT_PPG_PPGC8_PIE                    *((volatile  uint8_t *)(0x4248503CUL))

#define bFM_MFT_PPG_PPGC9_INTM                    *((volatile  uint8_t *)(0x42485014UL))
#define bFM4_MFT_PPG_PPGC9_INTM                   *((volatile  uint8_t *)(0x42485014UL))
#define bFM_MFT_PPG_PPGC9_PUF                     *((volatile  uint8_t *)(0x42485018UL))
#define bFM4_MFT_PPG_PPGC9_PUF                    *((volatile  uint8_t *)(0x42485018UL))
#define bFM_MFT_PPG_PPGC9_PIE                     *((volatile  uint8_t *)(0x4248501CUL))
#define bFM4_MFT_PPG_PPGC9_PIE                    *((volatile  uint8_t *)(0x4248501CUL))

#define bFM_MFT_PPG_REVC0_REV00                   *((volatile  uint8_t *)(0x42482080UL))
#define bFM4_MFT_PPG_REVC0_REV00                  *((volatile  uint8_t *)(0x42482080UL))
#define bFM_MFT_PPG_REVC0_REV01                   *((volatile  uint8_t *)(0x42482084UL))
#define bFM4_MFT_PPG_REVC0_REV01                  *((volatile  uint8_t *)(0x42482084UL))
#define bFM_MFT_PPG_REVC0_REV02                   *((volatile  uint8_t *)(0x42482088UL))
#define bFM4_MFT_PPG_REVC0_REV02                  *((volatile  uint8_t *)(0x42482088UL))
#define bFM_MFT_PPG_REVC0_REV03                   *((volatile  uint8_t *)(0x4248208CUL))
#define bFM4_MFT_PPG_REVC0_REV03                  *((volatile  uint8_t *)(0x4248208CUL))
#define bFM_MFT_PPG_REVC0_REV04                   *((volatile  uint8_t *)(0x42482090UL))
#define bFM4_MFT_PPG_REVC0_REV04                  *((volatile  uint8_t *)(0x42482090UL))
#define bFM_MFT_PPG_REVC0_REV05                   *((volatile  uint8_t *)(0x42482094UL))
#define bFM4_MFT_PPG_REVC0_REV05                  *((volatile  uint8_t *)(0x42482094UL))
#define bFM_MFT_PPG_REVC0_REV06                   *((volatile  uint8_t *)(0x42482098UL))
#define bFM4_MFT_PPG_REVC0_REV06                  *((volatile  uint8_t *)(0x42482098UL))
#define bFM_MFT_PPG_REVC0_REV07                   *((volatile  uint8_t *)(0x4248209CUL))
#define bFM4_MFT_PPG_REVC0_REV07                  *((volatile  uint8_t *)(0x4248209CUL))
#define bFM_MFT_PPG_REVC0_REV08                   *((volatile  uint8_t *)(0x424820A0UL))
#define bFM4_MFT_PPG_REVC0_REV08                  *((volatile  uint8_t *)(0x424820A0UL))
#define bFM_MFT_PPG_REVC0_REV09                   *((volatile  uint8_t *)(0x424820A4UL))
#define bFM4_MFT_PPG_REVC0_REV09                  *((volatile  uint8_t *)(0x424820A4UL))
#define bFM_MFT_PPG_REVC0_REV10                   *((volatile  uint8_t *)(0x424820A8UL))
#define bFM4_MFT_PPG_REVC0_REV10                  *((volatile  uint8_t *)(0x424820A8UL))
#define bFM_MFT_PPG_REVC0_REV11                   *((volatile  uint8_t *)(0x424820ACUL))
#define bFM4_MFT_PPG_REVC0_REV11                  *((volatile  uint8_t *)(0x424820ACUL))
#define bFM_MFT_PPG_REVC0_REV12                   *((volatile  uint8_t *)(0x424820B0UL))
#define bFM4_MFT_PPG_REVC0_REV12                  *((volatile  uint8_t *)(0x424820B0UL))
#define bFM_MFT_PPG_REVC0_REV13                   *((volatile  uint8_t *)(0x424820B4UL))
#define bFM4_MFT_PPG_REVC0_REV13                  *((volatile  uint8_t *)(0x424820B4UL))
#define bFM_MFT_PPG_REVC0_REV14                   *((volatile  uint8_t *)(0x424820B8UL))
#define bFM4_MFT_PPG_REVC0_REV14                  *((volatile  uint8_t *)(0x424820B8UL))
#define bFM_MFT_PPG_REVC0_REV15                   *((volatile  uint8_t *)(0x424820BCUL))
#define bFM4_MFT_PPG_REVC0_REV15                  *((volatile  uint8_t *)(0x424820BCUL))

#define bFM_MFT_PPG_REVC1_REV16                   *((volatile  uint8_t *)(0x42482880UL))
#define bFM4_MFT_PPG_REVC1_REV16                  *((volatile  uint8_t *)(0x42482880UL))
#define bFM_MFT_PPG_REVC1_REV17                   *((volatile  uint8_t *)(0x42482884UL))
#define bFM4_MFT_PPG_REVC1_REV17                  *((volatile  uint8_t *)(0x42482884UL))
#define bFM_MFT_PPG_REVC1_REV18                   *((volatile  uint8_t *)(0x42482888UL))
#define bFM4_MFT_PPG_REVC1_REV18                  *((volatile  uint8_t *)(0x42482888UL))
#define bFM_MFT_PPG_REVC1_REV19                   *((volatile  uint8_t *)(0x4248288CUL))
#define bFM4_MFT_PPG_REVC1_REV19                  *((volatile  uint8_t *)(0x4248288CUL))
#define bFM_MFT_PPG_REVC1_REV20                   *((volatile  uint8_t *)(0x42482890UL))
#define bFM4_MFT_PPG_REVC1_REV20                  *((volatile  uint8_t *)(0x42482890UL))
#define bFM_MFT_PPG_REVC1_REV21                   *((volatile  uint8_t *)(0x42482894UL))
#define bFM4_MFT_PPG_REVC1_REV21                  *((volatile  uint8_t *)(0x42482894UL))
#define bFM_MFT_PPG_REVC1_REV22                   *((volatile  uint8_t *)(0x42482898UL))
#define bFM4_MFT_PPG_REVC1_REV22                  *((volatile  uint8_t *)(0x42482898UL))
#define bFM_MFT_PPG_REVC1_REV23                   *((volatile  uint8_t *)(0x4248289CUL))
#define bFM4_MFT_PPG_REVC1_REV23                  *((volatile  uint8_t *)(0x4248289CUL))

#define bFM_MFT_PPG_TRG0_PEN00                    *((volatile  uint8_t *)(0x42482000UL))
#define bFM4_MFT_PPG_TRG0_PEN00                   *((volatile  uint8_t *)(0x42482000UL))
#define bFM_MFT_PPG_TRG0_PEN01                    *((volatile  uint8_t *)(0x42482004UL))
#define bFM4_MFT_PPG_TRG0_PEN01                   *((volatile  uint8_t *)(0x42482004UL))
#define bFM_MFT_PPG_TRG0_PEN02                    *((volatile  uint8_t *)(0x42482008UL))
#define bFM4_MFT_PPG_TRG0_PEN02                   *((volatile  uint8_t *)(0x42482008UL))
#define bFM_MFT_PPG_TRG0_PEN03                    *((volatile  uint8_t *)(0x4248200CUL))
#define bFM4_MFT_PPG_TRG0_PEN03                   *((volatile  uint8_t *)(0x4248200CUL))
#define bFM_MFT_PPG_TRG0_PEN04                    *((volatile  uint8_t *)(0x42482010UL))
#define bFM4_MFT_PPG_TRG0_PEN04                   *((volatile  uint8_t *)(0x42482010UL))
#define bFM_MFT_PPG_TRG0_PEN05                    *((volatile  uint8_t *)(0x42482014UL))
#define bFM4_MFT_PPG_TRG0_PEN05                   *((volatile  uint8_t *)(0x42482014UL))
#define bFM_MFT_PPG_TRG0_PEN06                    *((volatile  uint8_t *)(0x42482018UL))
#define bFM4_MFT_PPG_TRG0_PEN06                   *((volatile  uint8_t *)(0x42482018UL))
#define bFM_MFT_PPG_TRG0_PEN07                    *((volatile  uint8_t *)(0x4248201CUL))
#define bFM4_MFT_PPG_TRG0_PEN07                   *((volatile  uint8_t *)(0x4248201CUL))
#define bFM_MFT_PPG_TRG0_PEN08                    *((volatile  uint8_t *)(0x42482020UL))
#define bFM4_MFT_PPG_TRG0_PEN08                   *((volatile  uint8_t *)(0x42482020UL))
#define bFM_MFT_PPG_TRG0_PEN09                    *((volatile  uint8_t *)(0x42482024UL))
#define bFM4_MFT_PPG_TRG0_PEN09                   *((volatile  uint8_t *)(0x42482024UL))
#define bFM_MFT_PPG_TRG0_PEN10                    *((volatile  uint8_t *)(0x42482028UL))
#define bFM4_MFT_PPG_TRG0_PEN10                   *((volatile  uint8_t *)(0x42482028UL))
#define bFM_MFT_PPG_TRG0_PEN11                    *((volatile  uint8_t *)(0x4248202CUL))
#define bFM4_MFT_PPG_TRG0_PEN11                   *((volatile  uint8_t *)(0x4248202CUL))
#define bFM_MFT_PPG_TRG0_PEN12                    *((volatile  uint8_t *)(0x42482030UL))
#define bFM4_MFT_PPG_TRG0_PEN12                   *((volatile  uint8_t *)(0x42482030UL))
#define bFM_MFT_PPG_TRG0_PEN13                    *((volatile  uint8_t *)(0x42482034UL))
#define bFM4_MFT_PPG_TRG0_PEN13                   *((volatile  uint8_t *)(0x42482034UL))
#define bFM_MFT_PPG_TRG0_PEN14                    *((volatile  uint8_t *)(0x42482038UL))
#define bFM4_MFT_PPG_TRG0_PEN14                   *((volatile  uint8_t *)(0x42482038UL))
#define bFM_MFT_PPG_TRG0_PEN15                    *((volatile  uint8_t *)(0x4248203CUL))
#define bFM4_MFT_PPG_TRG0_PEN15                   *((volatile  uint8_t *)(0x4248203CUL))

#define bFM_MFT_PPG_TRG1_PEN16                    *((volatile  uint8_t *)(0x42482800UL))
#define bFM4_MFT_PPG_TRG1_PEN16                   *((volatile  uint8_t *)(0x42482800UL))
#define bFM_MFT_PPG_TRG1_PEN17                    *((volatile  uint8_t *)(0x42482804UL))
#define bFM4_MFT_PPG_TRG1_PEN17                   *((volatile  uint8_t *)(0x42482804UL))
#define bFM_MFT_PPG_TRG1_PEN18                    *((volatile  uint8_t *)(0x42482808UL))
#define bFM4_MFT_PPG_TRG1_PEN18                   *((volatile  uint8_t *)(0x42482808UL))
#define bFM_MFT_PPG_TRG1_PEN19                    *((volatile  uint8_t *)(0x4248280CUL))
#define bFM4_MFT_PPG_TRG1_PEN19                   *((volatile  uint8_t *)(0x4248280CUL))
#define bFM_MFT_PPG_TRG1_PEN20                    *((volatile  uint8_t *)(0x42482810UL))
#define bFM4_MFT_PPG_TRG1_PEN20                   *((volatile  uint8_t *)(0x42482810UL))
#define bFM_MFT_PPG_TRG1_PEN21                    *((volatile  uint8_t *)(0x42482814UL))
#define bFM4_MFT_PPG_TRG1_PEN21                   *((volatile  uint8_t *)(0x42482814UL))
#define bFM_MFT_PPG_TRG1_PEN22                    *((volatile  uint8_t *)(0x42482818UL))
#define bFM4_MFT_PPG_TRG1_PEN22                   *((volatile  uint8_t *)(0x42482818UL))
#define bFM_MFT_PPG_TRG1_PEN23                    *((volatile  uint8_t *)(0x4248281CUL))
#define bFM4_MFT_PPG_TRG1_PEN23                   *((volatile  uint8_t *)(0x4248281CUL))

#define bFM_MFT_PPG_TTCR0_STR0                    *((volatile  uint8_t *)(0x42480020UL))
#define bFM4_MFT_PPG_TTCR0_STR0                   *((volatile  uint8_t *)(0x42480020UL))
#define bFM_MFT_PPG_TTCR0_MONI0                   *((volatile  uint8_t *)(0x42480024UL))
#define bFM4_MFT_PPG_TTCR0_MONI0                  *((volatile  uint8_t *)(0x42480024UL))
#define bFM_MFT_PPG_TTCR0_TRG0O                   *((volatile  uint8_t *)(0x42480030UL))
#define bFM4_MFT_PPG_TTCR0_TRG0O                  *((volatile  uint8_t *)(0x42480030UL))
#define bFM_MFT_PPG_TTCR0_TRG2O                   *((volatile  uint8_t *)(0x42480034UL))
#define bFM4_MFT_PPG_TTCR0_TRG2O                  *((volatile  uint8_t *)(0x42480034UL))
#define bFM_MFT_PPG_TTCR0_TRG4O                   *((volatile  uint8_t *)(0x42480038UL))
#define bFM4_MFT_PPG_TTCR0_TRG4O                  *((volatile  uint8_t *)(0x42480038UL))
#define bFM_MFT_PPG_TTCR0_TRG6O                   *((volatile  uint8_t *)(0x4248003CUL))
#define bFM4_MFT_PPG_TTCR0_TRG6O                  *((volatile  uint8_t *)(0x4248003CUL))

#define bFM_MFT_PPG_TTCR1_STR1                    *((volatile  uint8_t *)(0x42480420UL))
#define bFM4_MFT_PPG_TTCR1_STR1                   *((volatile  uint8_t *)(0x42480420UL))
#define bFM_MFT_PPG_TTCR1_MONI1                   *((volatile  uint8_t *)(0x42480424UL))
#define bFM4_MFT_PPG_TTCR1_MONI1                  *((volatile  uint8_t *)(0x42480424UL))
#define bFM_MFT_PPG_TTCR1_TRG1O                   *((volatile  uint8_t *)(0x42480430UL))
#define bFM4_MFT_PPG_TTCR1_TRG1O                  *((volatile  uint8_t *)(0x42480430UL))
#define bFM_MFT_PPG_TTCR1_TRG3O                   *((volatile  uint8_t *)(0x42480434UL))
#define bFM4_MFT_PPG_TTCR1_TRG3O                  *((volatile  uint8_t *)(0x42480434UL))
#define bFM_MFT_PPG_TTCR1_TRG5O                   *((volatile  uint8_t *)(0x42480438UL))
#define bFM4_MFT_PPG_TTCR1_TRG5O                  *((volatile  uint8_t *)(0x42480438UL))
#define bFM_MFT_PPG_TTCR1_TRG7O                   *((volatile  uint8_t *)(0x4248043CUL))
#define bFM4_MFT_PPG_TTCR1_TRG7O                  *((volatile  uint8_t *)(0x4248043CUL))

#define bFM_MFT_PPG_TTCR2_STR2                    *((volatile  uint8_t *)(0x42480820UL))
#define bFM4_MFT_PPG_TTCR2_STR2                   *((volatile  uint8_t *)(0x42480820UL))
#define bFM_MFT_PPG_TTCR2_MONI2                   *((volatile  uint8_t *)(0x42480824UL))
#define bFM4_MFT_PPG_TTCR2_MONI2                  *((volatile  uint8_t *)(0x42480824UL))
#define bFM_MFT_PPG_TTCR2_TRG16O                  *((volatile  uint8_t *)(0x42480830UL))
#define bFM4_MFT_PPG_TTCR2_TRG16O                 *((volatile  uint8_t *)(0x42480830UL))
#define bFM_MFT_PPG_TTCR2_TRG18O                  *((volatile  uint8_t *)(0x42480834UL))
#define bFM4_MFT_PPG_TTCR2_TRG18O                 *((volatile  uint8_t *)(0x42480834UL))
#define bFM_MFT_PPG_TTCR2_TRG20O                  *((volatile  uint8_t *)(0x42480838UL))
#define bFM4_MFT_PPG_TTCR2_TRG20O                 *((volatile  uint8_t *)(0x42480838UL))
#define bFM_MFT_PPG_TTCR2_TRG22O                  *((volatile  uint8_t *)(0x4248083CUL))
#define bFM4_MFT_PPG_TTCR2_TRG22O                 *((volatile  uint8_t *)(0x4248083CUL))


/*******************************************************************************
* MFT Registers MFT0
*   Bitband Section
*******************************************************************************/
#define bFM_MFT0_ADCMP_ACMC0_MZCE                 *((volatile  uint8_t *)(0x42403AD8UL))
#define bFM4_MFT0_ADCMP_ACMC0_MZCE                *((volatile  uint8_t *)(0x42403AD8UL))
#define bFM_MFT0_ADCMP_ACMC0_MPCE                 *((volatile  uint8_t *)(0x42403ADCUL))
#define bFM4_MFT0_ADCMP_ACMC0_MPCE                *((volatile  uint8_t *)(0x42403ADCUL))

#define bFM_MFT0_ADCMP_ACMC1_MZCE                 *((volatile  uint8_t *)(0x42403B58UL))
#define bFM4_MFT0_ADCMP_ACMC1_MZCE                *((volatile  uint8_t *)(0x42403B58UL))
#define bFM_MFT0_ADCMP_ACMC1_MPCE                 *((volatile  uint8_t *)(0x42403B5CUL))
#define bFM4_MFT0_ADCMP_ACMC1_MPCE                *((volatile  uint8_t *)(0x42403B5CUL))

#define bFM_MFT0_ADCMP_ACMC2_MZCE                 *((volatile  uint8_t *)(0x42403BD8UL))
#define bFM4_MFT0_ADCMP_ACMC2_MZCE                *((volatile  uint8_t *)(0x42403BD8UL))
#define bFM_MFT0_ADCMP_ACMC2_MPCE                 *((volatile  uint8_t *)(0x42403BDCUL))
#define bFM4_MFT0_ADCMP_ACMC2_MPCE                *((volatile  uint8_t *)(0x42403BDCUL))

#define bFM_MFT0_ADCMP_ACMC3_MZCE                 *((volatile  uint8_t *)(0x42403C58UL))
#define bFM4_MFT0_ADCMP_ACMC3_MZCE                *((volatile  uint8_t *)(0x42403C58UL))
#define bFM_MFT0_ADCMP_ACMC3_MPCE                 *((volatile  uint8_t *)(0x42403C5CUL))
#define bFM4_MFT0_ADCMP_ACMC3_MPCE                *((volatile  uint8_t *)(0x42403C5CUL))

#define bFM_MFT0_ADCMP_ACMC4_MZCE                 *((volatile  uint8_t *)(0x42403CD8UL))
#define bFM4_MFT0_ADCMP_ACMC4_MZCE                *((volatile  uint8_t *)(0x42403CD8UL))
#define bFM_MFT0_ADCMP_ACMC4_MPCE                 *((volatile  uint8_t *)(0x42403CDCUL))
#define bFM4_MFT0_ADCMP_ACMC4_MPCE                *((volatile  uint8_t *)(0x42403CDCUL))

#define bFM_MFT0_ADCMP_ACMC5_MZCE                 *((volatile  uint8_t *)(0x42403D58UL))
#define bFM4_MFT0_ADCMP_ACMC5_MZCE                *((volatile  uint8_t *)(0x42403D58UL))
#define bFM_MFT0_ADCMP_ACMC5_MPCE                 *((volatile  uint8_t *)(0x42403D5CUL))
#define bFM4_MFT0_ADCMP_ACMC5_MPCE                *((volatile  uint8_t *)(0x42403D5CUL))

#define bFM_MFT0_ADCMP_ACSC0_APBM                 *((volatile  uint8_t *)(0x42403A94UL))
#define bFM4_MFT0_ADCMP_ACSC0_APBM                *((volatile  uint8_t *)(0x42403A94UL))

#define bFM_MFT0_ADCMP_ACSC1_APBM                 *((volatile  uint8_t *)(0x42403B14UL))
#define bFM4_MFT0_ADCMP_ACSC1_APBM                *((volatile  uint8_t *)(0x42403B14UL))

#define bFM_MFT0_ADCMP_ACSC2_APBM                 *((volatile  uint8_t *)(0x42403B94UL))
#define bFM4_MFT0_ADCMP_ACSC2_APBM                *((volatile  uint8_t *)(0x42403B94UL))

#define bFM_MFT0_ADCMP_ACSC3_APBM                 *((volatile  uint8_t *)(0x42403C14UL))
#define bFM4_MFT0_ADCMP_ACSC3_APBM                *((volatile  uint8_t *)(0x42403C14UL))

#define bFM_MFT0_ADCMP_ACSC4_APBM                 *((volatile  uint8_t *)(0x42403C94UL))
#define bFM4_MFT0_ADCMP_ACSC4_APBM                *((volatile  uint8_t *)(0x42403C94UL))

#define bFM_MFT0_ADCMP_ACSC5_APBM                 *((volatile  uint8_t *)(0x42403D14UL))
#define bFM4_MFT0_ADCMP_ACSC5_APBM                *((volatile  uint8_t *)(0x42403D14UL))

#define bFM_MFT0_ADCMP_ACSD0_AMOD                 *((volatile  uint8_t *)(0x42403AA0UL))
#define bFM4_MFT0_ADCMP_ACSD0_AMOD                *((volatile  uint8_t *)(0x42403AA0UL))
#define bFM_MFT0_ADCMP_ACSD0_OCUS                 *((volatile  uint8_t *)(0x42403AA4UL))
#define bFM4_MFT0_ADCMP_ACSD0_OCUS                *((volatile  uint8_t *)(0x42403AA4UL))
#define bFM_MFT0_ADCMP_ACSD0_DE                   *((volatile  uint8_t *)(0x42403AB0UL))
#define bFM4_MFT0_ADCMP_ACSD0_DE                  *((volatile  uint8_t *)(0x42403AB0UL))
#define bFM_MFT0_ADCMP_ACSD0_PE                   *((volatile  uint8_t *)(0x42403AB4UL))
#define bFM4_MFT0_ADCMP_ACSD0_PE                  *((volatile  uint8_t *)(0x42403AB4UL))
#define bFM_MFT0_ADCMP_ACSD0_UE                   *((volatile  uint8_t *)(0x42403AB8UL))
#define bFM4_MFT0_ADCMP_ACSD0_UE                  *((volatile  uint8_t *)(0x42403AB8UL))
#define bFM_MFT0_ADCMP_ACSD0_ZE                   *((volatile  uint8_t *)(0x42403ABCUL))
#define bFM4_MFT0_ADCMP_ACSD0_ZE                  *((volatile  uint8_t *)(0x42403ABCUL))

#define bFM_MFT0_ADCMP_ACSD1_AMOD                 *((volatile  uint8_t *)(0x42403B20UL))
#define bFM4_MFT0_ADCMP_ACSD1_AMOD                *((volatile  uint8_t *)(0x42403B20UL))
#define bFM_MFT0_ADCMP_ACSD1_OCUS                 *((volatile  uint8_t *)(0x42403B24UL))
#define bFM4_MFT0_ADCMP_ACSD1_OCUS                *((volatile  uint8_t *)(0x42403B24UL))
#define bFM_MFT0_ADCMP_ACSD1_DE                   *((volatile  uint8_t *)(0x42403B30UL))
#define bFM4_MFT0_ADCMP_ACSD1_DE                  *((volatile  uint8_t *)(0x42403B30UL))
#define bFM_MFT0_ADCMP_ACSD1_PE                   *((volatile  uint8_t *)(0x42403B34UL))
#define bFM4_MFT0_ADCMP_ACSD1_PE                  *((volatile  uint8_t *)(0x42403B34UL))
#define bFM_MFT0_ADCMP_ACSD1_UE                   *((volatile  uint8_t *)(0x42403B38UL))
#define bFM4_MFT0_ADCMP_ACSD1_UE                  *((volatile  uint8_t *)(0x42403B38UL))
#define bFM_MFT0_ADCMP_ACSD1_ZE                   *((volatile  uint8_t *)(0x42403B3CUL))
#define bFM4_MFT0_ADCMP_ACSD1_ZE                  *((volatile  uint8_t *)(0x42403B3CUL))

#define bFM_MFT0_ADCMP_ACSD2_AMOD                 *((volatile  uint8_t *)(0x42403BA0UL))
#define bFM4_MFT0_ADCMP_ACSD2_AMOD                *((volatile  uint8_t *)(0x42403BA0UL))
#define bFM_MFT0_ADCMP_ACSD2_OCUS                 *((volatile  uint8_t *)(0x42403BA4UL))
#define bFM4_MFT0_ADCMP_ACSD2_OCUS                *((volatile  uint8_t *)(0x42403BA4UL))
#define bFM_MFT0_ADCMP_ACSD2_DE                   *((volatile  uint8_t *)(0x42403BB0UL))
#define bFM4_MFT0_ADCMP_ACSD2_DE                  *((volatile  uint8_t *)(0x42403BB0UL))
#define bFM_MFT0_ADCMP_ACSD2_PE                   *((volatile  uint8_t *)(0x42403BB4UL))
#define bFM4_MFT0_ADCMP_ACSD2_PE                  *((volatile  uint8_t *)(0x42403BB4UL))
#define bFM_MFT0_ADCMP_ACSD2_UE                   *((volatile  uint8_t *)(0x42403BB8UL))
#define bFM4_MFT0_ADCMP_ACSD2_UE                  *((volatile  uint8_t *)(0x42403BB8UL))
#define bFM_MFT0_ADCMP_ACSD2_ZE                   *((volatile  uint8_t *)(0x42403BBCUL))
#define bFM4_MFT0_ADCMP_ACSD2_ZE                  *((volatile  uint8_t *)(0x42403BBCUL))

#define bFM_MFT0_ADCMP_ACSD3_AMOD                 *((volatile  uint8_t *)(0x42403C20UL))
#define bFM4_MFT0_ADCMP_ACSD3_AMOD                *((volatile  uint8_t *)(0x42403C20UL))
#define bFM_MFT0_ADCMP_ACSD3_OCUS                 *((volatile  uint8_t *)(0x42403C24UL))
#define bFM4_MFT0_ADCMP_ACSD3_OCUS                *((volatile  uint8_t *)(0x42403C24UL))
#define bFM_MFT0_ADCMP_ACSD3_DE                   *((volatile  uint8_t *)(0x42403C30UL))
#define bFM4_MFT0_ADCMP_ACSD3_DE                  *((volatile  uint8_t *)(0x42403C30UL))
#define bFM_MFT0_ADCMP_ACSD3_PE                   *((volatile  uint8_t *)(0x42403C34UL))
#define bFM4_MFT0_ADCMP_ACSD3_PE                  *((volatile  uint8_t *)(0x42403C34UL))
#define bFM_MFT0_ADCMP_ACSD3_UE                   *((volatile  uint8_t *)(0x42403C38UL))
#define bFM4_MFT0_ADCMP_ACSD3_UE                  *((volatile  uint8_t *)(0x42403C38UL))
#define bFM_MFT0_ADCMP_ACSD3_ZE                   *((volatile  uint8_t *)(0x42403C3CUL))
#define bFM4_MFT0_ADCMP_ACSD3_ZE                  *((volatile  uint8_t *)(0x42403C3CUL))

#define bFM_MFT0_ADCMP_ACSD4_AMOD                 *((volatile  uint8_t *)(0x42403CA0UL))
#define bFM4_MFT0_ADCMP_ACSD4_AMOD                *((volatile  uint8_t *)(0x42403CA0UL))
#define bFM_MFT0_ADCMP_ACSD4_OCUS                 *((volatile  uint8_t *)(0x42403CA4UL))
#define bFM4_MFT0_ADCMP_ACSD4_OCUS                *((volatile  uint8_t *)(0x42403CA4UL))
#define bFM_MFT0_ADCMP_ACSD4_DE                   *((volatile  uint8_t *)(0x42403CB0UL))
#define bFM4_MFT0_ADCMP_ACSD4_DE                  *((volatile  uint8_t *)(0x42403CB0UL))
#define bFM_MFT0_ADCMP_ACSD4_PE                   *((volatile  uint8_t *)(0x42403CB4UL))
#define bFM4_MFT0_ADCMP_ACSD4_PE                  *((volatile  uint8_t *)(0x42403CB4UL))
#define bFM_MFT0_ADCMP_ACSD4_UE                   *((volatile  uint8_t *)(0x42403CB8UL))
#define bFM4_MFT0_ADCMP_ACSD4_UE                  *((volatile  uint8_t *)(0x42403CB8UL))
#define bFM_MFT0_ADCMP_ACSD4_ZE                   *((volatile  uint8_t *)(0x42403CBCUL))
#define bFM4_MFT0_ADCMP_ACSD4_ZE                  *((volatile  uint8_t *)(0x42403CBCUL))

#define bFM_MFT0_ADCMP_ACSD5_AMOD                 *((volatile  uint8_t *)(0x42403D20UL))
#define bFM4_MFT0_ADCMP_ACSD5_AMOD                *((volatile  uint8_t *)(0x42403D20UL))
#define bFM_MFT0_ADCMP_ACSD5_OCUS                 *((volatile  uint8_t *)(0x42403D24UL))
#define bFM4_MFT0_ADCMP_ACSD5_OCUS                *((volatile  uint8_t *)(0x42403D24UL))
#define bFM_MFT0_ADCMP_ACSD5_DE                   *((volatile  uint8_t *)(0x42403D30UL))
#define bFM4_MFT0_ADCMP_ACSD5_DE                  *((volatile  uint8_t *)(0x42403D30UL))
#define bFM_MFT0_ADCMP_ACSD5_PE                   *((volatile  uint8_t *)(0x42403D34UL))
#define bFM4_MFT0_ADCMP_ACSD5_PE                  *((volatile  uint8_t *)(0x42403D34UL))
#define bFM_MFT0_ADCMP_ACSD5_UE                   *((volatile  uint8_t *)(0x42403D38UL))
#define bFM4_MFT0_ADCMP_ACSD5_UE                  *((volatile  uint8_t *)(0x42403D38UL))
#define bFM_MFT0_ADCMP_ACSD5_ZE                   *((volatile  uint8_t *)(0x42403D3CUL))
#define bFM4_MFT0_ADCMP_ACSD5_ZE                  *((volatile  uint8_t *)(0x42403D3CUL))

#define bFM_MFT0_FRT_TCAL_STOP00                  *((volatile  uint32_t*)(0x42402C80UL))
#define bFM4_MFT0_FRT_TCAL_STOP00                 *((volatile  uint32_t*)(0x42402C80UL))
#define bFM_MFT0_FRT_TCAL_STOP01                  *((volatile  uint32_t*)(0x42402C84UL))
#define bFM4_MFT0_FRT_TCAL_STOP01                 *((volatile  uint32_t*)(0x42402C84UL))
#define bFM_MFT0_FRT_TCAL_STOP02                  *((volatile  uint32_t*)(0x42402C88UL))
#define bFM4_MFT0_FRT_TCAL_STOP02                 *((volatile  uint32_t*)(0x42402C88UL))
#define bFM_MFT0_FRT_TCAL_STOP10                  *((volatile  uint32_t*)(0x42402C8CUL))
#define bFM4_MFT0_FRT_TCAL_STOP10                 *((volatile  uint32_t*)(0x42402C8CUL))
#define bFM_MFT0_FRT_TCAL_STOP11                  *((volatile  uint32_t*)(0x42402C90UL))
#define bFM4_MFT0_FRT_TCAL_STOP11                 *((volatile  uint32_t*)(0x42402C90UL))
#define bFM_MFT0_FRT_TCAL_STOP12                  *((volatile  uint32_t*)(0x42402C94UL))
#define bFM4_MFT0_FRT_TCAL_STOP12                 *((volatile  uint32_t*)(0x42402C94UL))
#define bFM_MFT0_FRT_TCAL_STOP20                  *((volatile  uint32_t*)(0x42402C98UL))
#define bFM4_MFT0_FRT_TCAL_STOP20                 *((volatile  uint32_t*)(0x42402C98UL))
#define bFM_MFT0_FRT_TCAL_STOP21                  *((volatile  uint32_t*)(0x42402C9CUL))
#define bFM4_MFT0_FRT_TCAL_STOP21                 *((volatile  uint32_t*)(0x42402C9CUL))
#define bFM_MFT0_FRT_TCAL_STOP22                  *((volatile  uint32_t*)(0x42402CA0UL))
#define bFM4_MFT0_FRT_TCAL_STOP22                 *((volatile  uint32_t*)(0x42402CA0UL))
#define bFM_MFT0_FRT_TCAL_SCLR00                  *((volatile  uint32_t*)(0x42402CC0UL))
#define bFM4_MFT0_FRT_TCAL_SCLR00                 *((volatile  uint32_t*)(0x42402CC0UL))
#define bFM_MFT0_FRT_TCAL_SCLR01                  *((volatile  uint32_t*)(0x42402CC4UL))
#define bFM4_MFT0_FRT_TCAL_SCLR01                 *((volatile  uint32_t*)(0x42402CC4UL))
#define bFM_MFT0_FRT_TCAL_SCLR02                  *((volatile  uint32_t*)(0x42402CC8UL))
#define bFM4_MFT0_FRT_TCAL_SCLR02                 *((volatile  uint32_t*)(0x42402CC8UL))
#define bFM_MFT0_FRT_TCAL_SCLR10                  *((volatile  uint32_t*)(0x42402CCCUL))
#define bFM4_MFT0_FRT_TCAL_SCLR10                 *((volatile  uint32_t*)(0x42402CCCUL))
#define bFM_MFT0_FRT_TCAL_SCLR11                  *((volatile  uint32_t*)(0x42402CD0UL))
#define bFM4_MFT0_FRT_TCAL_SCLR11                 *((volatile  uint32_t*)(0x42402CD0UL))
#define bFM_MFT0_FRT_TCAL_SCLR12                  *((volatile  uint32_t*)(0x42402CD4UL))
#define bFM4_MFT0_FRT_TCAL_SCLR12                 *((volatile  uint32_t*)(0x42402CD4UL))
#define bFM_MFT0_FRT_TCAL_SCLR20                  *((volatile  uint32_t*)(0x42402CD8UL))
#define bFM4_MFT0_FRT_TCAL_SCLR20                 *((volatile  uint32_t*)(0x42402CD8UL))
#define bFM_MFT0_FRT_TCAL_SCLR21                  *((volatile  uint32_t*)(0x42402CDCUL))
#define bFM4_MFT0_FRT_TCAL_SCLR21                 *((volatile  uint32_t*)(0x42402CDCUL))
#define bFM_MFT0_FRT_TCAL_SCLR22                  *((volatile  uint32_t*)(0x42402CE0UL))
#define bFM4_MFT0_FRT_TCAL_SCLR22                 *((volatile  uint32_t*)(0x42402CE0UL))

#define bFM_MFT0_FRT_TCSA0_SCLR                   *((volatile  uint8_t *)(0x42402910UL))
#define bFM4_MFT0_FRT_TCSA0_SCLR                  *((volatile  uint8_t *)(0x42402910UL))
#define bFM_MFT0_FRT_TCSA0_MODE                   *((volatile  uint8_t *)(0x42402914UL))
#define bFM4_MFT0_FRT_TCSA0_MODE                  *((volatile  uint8_t *)(0x42402914UL))
#define bFM_MFT0_FRT_TCSA0_STOP                   *((volatile  uint8_t *)(0x42402918UL))
#define bFM4_MFT0_FRT_TCSA0_STOP                  *((volatile  uint8_t *)(0x42402918UL))
#define bFM_MFT0_FRT_TCSA0_BFE                    *((volatile  uint8_t *)(0x4240291CUL))
#define bFM4_MFT0_FRT_TCSA0_BFE                   *((volatile  uint8_t *)(0x4240291CUL))
#define bFM_MFT0_FRT_TCSA0_ICRE                   *((volatile  uint8_t *)(0x42402920UL))
#define bFM4_MFT0_FRT_TCSA0_ICRE                  *((volatile  uint8_t *)(0x42402920UL))
#define bFM_MFT0_FRT_TCSA0_ICLR                   *((volatile  uint8_t *)(0x42402924UL))
#define bFM4_MFT0_FRT_TCSA0_ICLR                  *((volatile  uint8_t *)(0x42402924UL))
#define bFM_MFT0_FRT_TCSA0_IRQZE                  *((volatile  uint8_t *)(0x42402934UL))
#define bFM4_MFT0_FRT_TCSA0_IRQZE                 *((volatile  uint8_t *)(0x42402934UL))
#define bFM_MFT0_FRT_TCSA0_IRQZF                  *((volatile  uint8_t *)(0x42402938UL))
#define bFM4_MFT0_FRT_TCSA0_IRQZF                 *((volatile  uint8_t *)(0x42402938UL))
#define bFM_MFT0_FRT_TCSA0_ECKE                   *((volatile  uint8_t *)(0x4240293CUL))
#define bFM4_MFT0_FRT_TCSA0_ECKE                  *((volatile  uint8_t *)(0x4240293CUL))

#define bFM_MFT0_FRT_TCSA1_SCLR                   *((volatile  uint8_t *)(0x42402A90UL))
#define bFM4_MFT0_FRT_TCSA1_SCLR                  *((volatile  uint8_t *)(0x42402A90UL))
#define bFM_MFT0_FRT_TCSA1_MODE                   *((volatile  uint8_t *)(0x42402A94UL))
#define bFM4_MFT0_FRT_TCSA1_MODE                  *((volatile  uint8_t *)(0x42402A94UL))
#define bFM_MFT0_FRT_TCSA1_STOP                   *((volatile  uint8_t *)(0x42402A98UL))
#define bFM4_MFT0_FRT_TCSA1_STOP                  *((volatile  uint8_t *)(0x42402A98UL))
#define bFM_MFT0_FRT_TCSA1_BFE                    *((volatile  uint8_t *)(0x42402A9CUL))
#define bFM4_MFT0_FRT_TCSA1_BFE                   *((volatile  uint8_t *)(0x42402A9CUL))
#define bFM_MFT0_FRT_TCSA1_ICRE                   *((volatile  uint8_t *)(0x42402AA0UL))
#define bFM4_MFT0_FRT_TCSA1_ICRE                  *((volatile  uint8_t *)(0x42402AA0UL))
#define bFM_MFT0_FRT_TCSA1_ICLR                   *((volatile  uint8_t *)(0x42402AA4UL))
#define bFM4_MFT0_FRT_TCSA1_ICLR                  *((volatile  uint8_t *)(0x42402AA4UL))
#define bFM_MFT0_FRT_TCSA1_IRQZE                  *((volatile  uint8_t *)(0x42402AB4UL))
#define bFM4_MFT0_FRT_TCSA1_IRQZE                 *((volatile  uint8_t *)(0x42402AB4UL))
#define bFM_MFT0_FRT_TCSA1_IRQZF                  *((volatile  uint8_t *)(0x42402AB8UL))
#define bFM4_MFT0_FRT_TCSA1_IRQZF                 *((volatile  uint8_t *)(0x42402AB8UL))
#define bFM_MFT0_FRT_TCSA1_ECKE                   *((volatile  uint8_t *)(0x42402ABCUL))
#define bFM4_MFT0_FRT_TCSA1_ECKE                  *((volatile  uint8_t *)(0x42402ABCUL))

#define bFM_MFT0_FRT_TCSA2_SCLR                   *((volatile  uint8_t *)(0x42402C10UL))
#define bFM4_MFT0_FRT_TCSA2_SCLR                  *((volatile  uint8_t *)(0x42402C10UL))
#define bFM_MFT0_FRT_TCSA2_MODE                   *((volatile  uint8_t *)(0x42402C14UL))
#define bFM4_MFT0_FRT_TCSA2_MODE                  *((volatile  uint8_t *)(0x42402C14UL))
#define bFM_MFT0_FRT_TCSA2_STOP                   *((volatile  uint8_t *)(0x42402C18UL))
#define bFM4_MFT0_FRT_TCSA2_STOP                  *((volatile  uint8_t *)(0x42402C18UL))
#define bFM_MFT0_FRT_TCSA2_BFE                    *((volatile  uint8_t *)(0x42402C1CUL))
#define bFM4_MFT0_FRT_TCSA2_BFE                   *((volatile  uint8_t *)(0x42402C1CUL))
#define bFM_MFT0_FRT_TCSA2_ICRE                   *((volatile  uint8_t *)(0x42402C20UL))
#define bFM4_MFT0_FRT_TCSA2_ICRE                  *((volatile  uint8_t *)(0x42402C20UL))
#define bFM_MFT0_FRT_TCSA2_ICLR                   *((volatile  uint8_t *)(0x42402C24UL))
#define bFM4_MFT0_FRT_TCSA2_ICLR                  *((volatile  uint8_t *)(0x42402C24UL))
#define bFM_MFT0_FRT_TCSA2_IRQZE                  *((volatile  uint8_t *)(0x42402C34UL))
#define bFM4_MFT0_FRT_TCSA2_IRQZE                 *((volatile  uint8_t *)(0x42402C34UL))
#define bFM_MFT0_FRT_TCSA2_IRQZF                  *((volatile  uint8_t *)(0x42402C38UL))
#define bFM4_MFT0_FRT_TCSA2_IRQZF                 *((volatile  uint8_t *)(0x42402C38UL))
#define bFM_MFT0_FRT_TCSA2_ECKE                   *((volatile  uint8_t *)(0x42402C3CUL))
#define bFM4_MFT0_FRT_TCSA2_ECKE                  *((volatile  uint8_t *)(0x42402C3CUL))

#define bFM_MFT0_FRT_TCSD_OFMD1                   *((volatile  uint8_t *)(0x42403D80UL))
#define bFM4_MFT0_FRT_TCSD_OFMD1                  *((volatile  uint8_t *)(0x42403D80UL))
#define bFM_MFT0_FRT_TCSD_OFMD2                   *((volatile  uint8_t *)(0x42403D84UL))
#define bFM4_MFT0_FRT_TCSD_OFMD2                  *((volatile  uint8_t *)(0x42403D84UL))

#define bFM_MFT0_ICU_ICSA10_ICE0                  *((volatile  uint8_t *)(0x42403090UL))
#define bFM4_MFT0_ICU_ICSA10_ICE0                 *((volatile  uint8_t *)(0x42403090UL))
#define bFM_MFT0_ICU_ICSA10_ICE1                  *((volatile  uint8_t *)(0x42403094UL))
#define bFM4_MFT0_ICU_ICSA10_ICE1                 *((volatile  uint8_t *)(0x42403094UL))
#define bFM_MFT0_ICU_ICSA10_ICP0                  *((volatile  uint8_t *)(0x42403098UL))
#define bFM4_MFT0_ICU_ICSA10_ICP0                 *((volatile  uint8_t *)(0x42403098UL))
#define bFM_MFT0_ICU_ICSA10_ICP1                  *((volatile  uint8_t *)(0x4240309CUL))
#define bFM4_MFT0_ICU_ICSA10_ICP1                 *((volatile  uint8_t *)(0x4240309CUL))

#define bFM_MFT0_ICU_ICSA32_ICE2                  *((volatile  uint8_t *)(0x42403110UL))
#define bFM4_MFT0_ICU_ICSA32_ICE2                 *((volatile  uint8_t *)(0x42403110UL))
#define bFM_MFT0_ICU_ICSA32_ICE3                  *((volatile  uint8_t *)(0x42403114UL))
#define bFM4_MFT0_ICU_ICSA32_ICE3                 *((volatile  uint8_t *)(0x42403114UL))
#define bFM_MFT0_ICU_ICSA32_ICP2                  *((volatile  uint8_t *)(0x42403118UL))
#define bFM4_MFT0_ICU_ICSA32_ICP2                 *((volatile  uint8_t *)(0x42403118UL))
#define bFM_MFT0_ICU_ICSA32_ICP3                  *((volatile  uint8_t *)(0x4240311CUL))
#define bFM4_MFT0_ICU_ICSA32_ICP3                 *((volatile  uint8_t *)(0x4240311CUL))

#define bFM_MFT0_ICU_ICSB10_IEI0                  *((volatile  uint8_t *)(0x424030A0UL))
#define bFM4_MFT0_ICU_ICSB10_IEI0                 *((volatile  uint8_t *)(0x424030A0UL))
#define bFM_MFT0_ICU_ICSB10_IEI1                  *((volatile  uint8_t *)(0x424030A4UL))
#define bFM4_MFT0_ICU_ICSB10_IEI1                 *((volatile  uint8_t *)(0x424030A4UL))

#define bFM_MFT0_ICU_ICSB32_IEI2                  *((volatile  uint8_t *)(0x42403120UL))
#define bFM4_MFT0_ICU_ICSB32_IEI2                 *((volatile  uint8_t *)(0x42403120UL))
#define bFM_MFT0_ICU_ICSB32_IEI3                  *((volatile  uint8_t *)(0x42403124UL))
#define bFM4_MFT0_ICU_ICSB32_IEI3                 *((volatile  uint8_t *)(0x42403124UL))

#define bFM_MFT0_OCU_OCSA10_CST0                  *((volatile  uint8_t *)(0x42402300UL))
#define bFM4_MFT0_OCU_OCSA10_CST0                 *((volatile  uint8_t *)(0x42402300UL))
#define bFM_MFT0_OCU_OCSA10_CST1                  *((volatile  uint8_t *)(0x42402304UL))
#define bFM4_MFT0_OCU_OCSA10_CST1                 *((volatile  uint8_t *)(0x42402304UL))
#define bFM_MFT0_OCU_OCSA10_IOE0                  *((volatile  uint8_t *)(0x42402310UL))
#define bFM4_MFT0_OCU_OCSA10_IOE0                 *((volatile  uint8_t *)(0x42402310UL))
#define bFM_MFT0_OCU_OCSA10_IOE1                  *((volatile  uint8_t *)(0x42402314UL))
#define bFM4_MFT0_OCU_OCSA10_IOE1                 *((volatile  uint8_t *)(0x42402314UL))
#define bFM_MFT0_OCU_OCSA10_IOP0                  *((volatile  uint8_t *)(0x42402318UL))
#define bFM4_MFT0_OCU_OCSA10_IOP0                 *((volatile  uint8_t *)(0x42402318UL))
#define bFM_MFT0_OCU_OCSA10_IOP1                  *((volatile  uint8_t *)(0x4240231CUL))
#define bFM4_MFT0_OCU_OCSA10_IOP1                 *((volatile  uint8_t *)(0x4240231CUL))

#define bFM_MFT0_OCU_OCSA32_CST2                  *((volatile  uint8_t *)(0x42402380UL))
#define bFM4_MFT0_OCU_OCSA32_CST2                 *((volatile  uint8_t *)(0x42402380UL))
#define bFM_MFT0_OCU_OCSA32_CST3                  *((volatile  uint8_t *)(0x42402384UL))
#define bFM4_MFT0_OCU_OCSA32_CST3                 *((volatile  uint8_t *)(0x42402384UL))
#define bFM_MFT0_OCU_OCSA32_IOE2                  *((volatile  uint8_t *)(0x42402390UL))
#define bFM4_MFT0_OCU_OCSA32_IOE2                 *((volatile  uint8_t *)(0x42402390UL))
#define bFM_MFT0_OCU_OCSA32_IOE3                  *((volatile  uint8_t *)(0x42402394UL))
#define bFM4_MFT0_OCU_OCSA32_IOE3                 *((volatile  uint8_t *)(0x42402394UL))
#define bFM_MFT0_OCU_OCSA32_IOP2                  *((volatile  uint8_t *)(0x42402398UL))
#define bFM4_MFT0_OCU_OCSA32_IOP2                 *((volatile  uint8_t *)(0x42402398UL))
#define bFM_MFT0_OCU_OCSA32_IOP3                  *((volatile  uint8_t *)(0x4240239CUL))
#define bFM4_MFT0_OCU_OCSA32_IOP3                 *((volatile  uint8_t *)(0x4240239CUL))

#define bFM_MFT0_OCU_OCSA54_CST4                  *((volatile  uint8_t *)(0x42402400UL))
#define bFM4_MFT0_OCU_OCSA54_CST4                 *((volatile  uint8_t *)(0x42402400UL))
#define bFM_MFT0_OCU_OCSA54_CST5                  *((volatile  uint8_t *)(0x42402404UL))
#define bFM4_MFT0_OCU_OCSA54_CST5                 *((volatile  uint8_t *)(0x42402404UL))
#define bFM_MFT0_OCU_OCSA54_IOE4                  *((volatile  uint8_t *)(0x42402410UL))
#define bFM4_MFT0_OCU_OCSA54_IOE4                 *((volatile  uint8_t *)(0x42402410UL))
#define bFM_MFT0_OCU_OCSA54_IOE5                  *((volatile  uint8_t *)(0x42402414UL))
#define bFM4_MFT0_OCU_OCSA54_IOE5                 *((volatile  uint8_t *)(0x42402414UL))
#define bFM_MFT0_OCU_OCSA54_IOP4                  *((volatile  uint8_t *)(0x42402418UL))
#define bFM4_MFT0_OCU_OCSA54_IOP4                 *((volatile  uint8_t *)(0x42402418UL))
#define bFM_MFT0_OCU_OCSA54_IOP5                  *((volatile  uint8_t *)(0x4240241CUL))
#define bFM4_MFT0_OCU_OCSA54_IOP5                 *((volatile  uint8_t *)(0x4240241CUL))

#define bFM_MFT0_OCU_OCSB10_OTD0                  *((volatile  uint8_t *)(0x42402320UL))
#define bFM4_MFT0_OCU_OCSB10_OTD0                 *((volatile  uint8_t *)(0x42402320UL))
#define bFM_MFT0_OCU_OCSB10_OTD1                  *((volatile  uint8_t *)(0x42402324UL))
#define bFM4_MFT0_OCU_OCSB10_OTD1                 *((volatile  uint8_t *)(0x42402324UL))
#define bFM_MFT0_OCU_OCSB10_CMOD                  *((volatile  uint8_t *)(0x42402330UL))
#define bFM4_MFT0_OCU_OCSB10_CMOD                 *((volatile  uint8_t *)(0x42402330UL))
#define bFM_MFT0_OCU_OCSB10_FM4                   *((volatile  uint8_t *)(0x4240233CUL))
#define bFM4_MFT0_OCU_OCSB10_FM4                  *((volatile  uint8_t *)(0x4240233CUL))

#define bFM_MFT0_OCU_OCSB32_OTD2                  *((volatile  uint8_t *)(0x424023A0UL))
#define bFM4_MFT0_OCU_OCSB32_OTD2                 *((volatile  uint8_t *)(0x424023A0UL))
#define bFM_MFT0_OCU_OCSB32_OTD3                  *((volatile  uint8_t *)(0x424023A4UL))
#define bFM4_MFT0_OCU_OCSB32_OTD3                 *((volatile  uint8_t *)(0x424023A4UL))
#define bFM_MFT0_OCU_OCSB32_CMOD                  *((volatile  uint8_t *)(0x424023B0UL))
#define bFM4_MFT0_OCU_OCSB32_CMOD                 *((volatile  uint8_t *)(0x424023B0UL))
#define bFM_MFT0_OCU_OCSB32_FM4                   *((volatile  uint8_t *)(0x424023BCUL))
#define bFM4_MFT0_OCU_OCSB32_FM4                  *((volatile  uint8_t *)(0x424023BCUL))

#define bFM_MFT0_OCU_OCSB54_OTD4                  *((volatile  uint8_t *)(0x42402420UL))
#define bFM4_MFT0_OCU_OCSB54_OTD4                 *((volatile  uint8_t *)(0x42402420UL))
#define bFM_MFT0_OCU_OCSB54_OTD5                  *((volatile  uint8_t *)(0x42402424UL))
#define bFM4_MFT0_OCU_OCSB54_OTD5                 *((volatile  uint8_t *)(0x42402424UL))
#define bFM_MFT0_OCU_OCSB54_CMOD                  *((volatile  uint8_t *)(0x42402430UL))
#define bFM4_MFT0_OCU_OCSB54_CMOD                 *((volatile  uint8_t *)(0x42402430UL))
#define bFM_MFT0_OCU_OCSB54_FM4                   *((volatile  uint8_t *)(0x4240243CUL))
#define bFM4_MFT0_OCU_OCSB54_FM4                  *((volatile  uint8_t *)(0x4240243CUL))

#define bFM_MFT0_OCU_OCSC_MOD0                    *((volatile  uint8_t *)(0x424024A0UL))
#define bFM4_MFT0_OCU_OCSC_MOD0                   *((volatile  uint8_t *)(0x424024A0UL))
#define bFM_MFT0_OCU_OCSC_MOD1                    *((volatile  uint8_t *)(0x424024A4UL))
#define bFM4_MFT0_OCU_OCSC_MOD1                   *((volatile  uint8_t *)(0x424024A4UL))
#define bFM_MFT0_OCU_OCSC_MOD2                    *((volatile  uint8_t *)(0x424024A8UL))
#define bFM4_MFT0_OCU_OCSC_MOD2                   *((volatile  uint8_t *)(0x424024A8UL))
#define bFM_MFT0_OCU_OCSC_MOD3                    *((volatile  uint8_t *)(0x424024ACUL))
#define bFM4_MFT0_OCU_OCSC_MOD3                   *((volatile  uint8_t *)(0x424024ACUL))
#define bFM_MFT0_OCU_OCSC_MOD4                    *((volatile  uint8_t *)(0x424024B0UL))
#define bFM4_MFT0_OCU_OCSC_MOD4                   *((volatile  uint8_t *)(0x424024B0UL))
#define bFM_MFT0_OCU_OCSC_MOD5                    *((volatile  uint8_t *)(0x424024B4UL))
#define bFM4_MFT0_OCU_OCSC_MOD5                   *((volatile  uint8_t *)(0x424024B4UL))

#define bFM_MFT0_OCU_OCSD10_OPBM0                 *((volatile  uint8_t *)(0x42402360UL))
#define bFM4_MFT0_OCU_OCSD10_OPBM0                *((volatile  uint8_t *)(0x42402360UL))
#define bFM_MFT0_OCU_OCSD10_OPBM1                 *((volatile  uint8_t *)(0x42402364UL))
#define bFM4_MFT0_OCU_OCSD10_OPBM1                *((volatile  uint8_t *)(0x42402364UL))
#define bFM_MFT0_OCU_OCSD10_OEBM0                 *((volatile  uint8_t *)(0x42402368UL))
#define bFM4_MFT0_OCU_OCSD10_OEBM0                *((volatile  uint8_t *)(0x42402368UL))
#define bFM_MFT0_OCU_OCSD10_OEBM1                 *((volatile  uint8_t *)(0x4240236CUL))
#define bFM4_MFT0_OCU_OCSD10_OEBM1                *((volatile  uint8_t *)(0x4240236CUL))
#define bFM_MFT0_OCU_OCSD10_OFEX0                 *((volatile  uint8_t *)(0x42402370UL))
#define bFM4_MFT0_OCU_OCSD10_OFEX0                *((volatile  uint8_t *)(0x42402370UL))
#define bFM_MFT0_OCU_OCSD10_OFEX1                 *((volatile  uint8_t *)(0x42402374UL))
#define bFM4_MFT0_OCU_OCSD10_OFEX1                *((volatile  uint8_t *)(0x42402374UL))

#define bFM_MFT0_OCU_OCSD32_OPBM2                 *((volatile  uint8_t *)(0x424023E0UL))
#define bFM4_MFT0_OCU_OCSD32_OPBM2                *((volatile  uint8_t *)(0x424023E0UL))
#define bFM_MFT0_OCU_OCSD32_OPBM3                 *((volatile  uint8_t *)(0x424023E4UL))
#define bFM4_MFT0_OCU_OCSD32_OPBM3                *((volatile  uint8_t *)(0x424023E4UL))
#define bFM_MFT0_OCU_OCSD32_OEBM2                 *((volatile  uint8_t *)(0x424023E8UL))
#define bFM4_MFT0_OCU_OCSD32_OEBM2                *((volatile  uint8_t *)(0x424023E8UL))
#define bFM_MFT0_OCU_OCSD32_OEBM3                 *((volatile  uint8_t *)(0x424023ECUL))
#define bFM4_MFT0_OCU_OCSD32_OEBM3                *((volatile  uint8_t *)(0x424023ECUL))
#define bFM_MFT0_OCU_OCSD32_OFEX2                 *((volatile  uint8_t *)(0x424023F0UL))
#define bFM4_MFT0_OCU_OCSD32_OFEX2                *((volatile  uint8_t *)(0x424023F0UL))
#define bFM_MFT0_OCU_OCSD32_OFEX3                 *((volatile  uint8_t *)(0x424023F4UL))
#define bFM4_MFT0_OCU_OCSD32_OFEX3                *((volatile  uint8_t *)(0x424023F4UL))

#define bFM_MFT0_OCU_OCSD54_OPBM4                 *((volatile  uint8_t *)(0x42402460UL))
#define bFM4_MFT0_OCU_OCSD54_OPBM4                *((volatile  uint8_t *)(0x42402460UL))
#define bFM_MFT0_OCU_OCSD54_OPBM5                 *((volatile  uint8_t *)(0x42402464UL))
#define bFM4_MFT0_OCU_OCSD54_OPBM5                *((volatile  uint8_t *)(0x42402464UL))
#define bFM_MFT0_OCU_OCSD54_OEBM4                 *((volatile  uint8_t *)(0x42402468UL))
#define bFM4_MFT0_OCU_OCSD54_OEBM4                *((volatile  uint8_t *)(0x42402468UL))
#define bFM_MFT0_OCU_OCSD54_OEBM5                 *((volatile  uint8_t *)(0x4240246CUL))
#define bFM4_MFT0_OCU_OCSD54_OEBM5                *((volatile  uint8_t *)(0x4240246CUL))
#define bFM_MFT0_OCU_OCSD54_OFEX4                 *((volatile  uint8_t *)(0x42402470UL))
#define bFM4_MFT0_OCU_OCSD54_OFEX4                *((volatile  uint8_t *)(0x42402470UL))
#define bFM_MFT0_OCU_OCSD54_OFEX5                 *((volatile  uint8_t *)(0x42402474UL))
#define bFM4_MFT0_OCU_OCSD54_OFEX5                *((volatile  uint8_t *)(0x42402474UL))

#define bFM_MFT0_WFG_NZCL_DTIEA                   *((volatile  uint16_t*)(0x42403680UL))
#define bFM4_MFT0_WFG_NZCL_DTIEA                  *((volatile  uint16_t*)(0x42403680UL))
#define bFM_MFT0_WFG_NZCL_SDTI                    *((volatile  uint16_t*)(0x42403690UL))
#define bFM4_MFT0_WFG_NZCL_SDTI                   *((volatile  uint16_t*)(0x42403690UL))
#define bFM_MFT0_WFG_NZCL_DTIEB                   *((volatile  uint16_t*)(0x42403694UL))
#define bFM4_MFT0_WFG_NZCL_DTIEB                  *((volatile  uint16_t*)(0x42403694UL))
#define bFM_MFT0_WFG_NZCL_DHOLD                   *((volatile  uint16_t*)(0x4240369CUL))
#define bFM4_MFT0_WFG_NZCL_DHOLD                  *((volatile  uint16_t*)(0x4240369CUL))
#define bFM_MFT0_WFG_NZCL_DIMA                    *((volatile  uint16_t*)(0x424036A0UL))
#define bFM4_MFT0_WFG_NZCL_DIMA                   *((volatile  uint16_t*)(0x424036A0UL))
#define bFM_MFT0_WFG_NZCL_DIMB                    *((volatile  uint16_t*)(0x424036A4UL))
#define bFM4_MFT0_WFG_NZCL_DIMB                   *((volatile  uint16_t*)(0x424036A4UL))
#define bFM_MFT0_WFG_NZCL_WIM10                   *((volatile  uint16_t*)(0x424036B0UL))
#define bFM4_MFT0_WFG_NZCL_WIM10                  *((volatile  uint16_t*)(0x424036B0UL))
#define bFM_MFT0_WFG_NZCL_WIM32                   *((volatile  uint16_t*)(0x424036B4UL))
#define bFM4_MFT0_WFG_NZCL_WIM32                  *((volatile  uint16_t*)(0x424036B4UL))
#define bFM_MFT0_WFG_NZCL_WIM54                   *((volatile  uint16_t*)(0x424036B8UL))
#define bFM4_MFT0_WFG_NZCL_WIM54                  *((volatile  uint16_t*)(0x424036B8UL))

#define bFM_MFT0_WFG_WFIR_DTIFA                   *((volatile  uint16_t*)(0x42403600UL))
#define bFM4_MFT0_WFG_WFIR_DTIFA                  *((volatile  uint16_t*)(0x42403600UL))
#define bFM_MFT0_WFG_WFIR_DTICA                   *((volatile  uint16_t*)(0x42403604UL))
#define bFM4_MFT0_WFG_WFIR_DTICA                  *((volatile  uint16_t*)(0x42403604UL))
#define bFM_MFT0_WFG_WFIR_DTIFB                   *((volatile  uint16_t*)(0x42403608UL))
#define bFM4_MFT0_WFG_WFIR_DTIFB                  *((volatile  uint16_t*)(0x42403608UL))
#define bFM_MFT0_WFG_WFIR_DTICB                   *((volatile  uint16_t*)(0x4240360CUL))
#define bFM4_MFT0_WFG_WFIR_DTICB                  *((volatile  uint16_t*)(0x4240360CUL))
#define bFM_MFT0_WFG_WFIR_TMIF10                  *((volatile  uint16_t*)(0x42403610UL))
#define bFM4_MFT0_WFG_WFIR_TMIF10                 *((volatile  uint16_t*)(0x42403610UL))
#define bFM_MFT0_WFG_WFIR_TMIC10                  *((volatile  uint16_t*)(0x42403614UL))
#define bFM4_MFT0_WFG_WFIR_TMIC10                 *((volatile  uint16_t*)(0x42403614UL))
#define bFM_MFT0_WFG_WFIR_TMIE10                  *((volatile  uint16_t*)(0x42403618UL))
#define bFM4_MFT0_WFG_WFIR_TMIE10                 *((volatile  uint16_t*)(0x42403618UL))
#define bFM_MFT0_WFG_WFIR_TMIS10                  *((volatile  uint16_t*)(0x4240361CUL))
#define bFM4_MFT0_WFG_WFIR_TMIS10                 *((volatile  uint16_t*)(0x4240361CUL))
#define bFM_MFT0_WFG_WFIR_TMIF32                  *((volatile  uint16_t*)(0x42403620UL))
#define bFM4_MFT0_WFG_WFIR_TMIF32                 *((volatile  uint16_t*)(0x42403620UL))
#define bFM_MFT0_WFG_WFIR_TMIC32                  *((volatile  uint16_t*)(0x42403624UL))
#define bFM4_MFT0_WFG_WFIR_TMIC32                 *((volatile  uint16_t*)(0x42403624UL))
#define bFM_MFT0_WFG_WFIR_TMIE32                  *((volatile  uint16_t*)(0x42403628UL))
#define bFM4_MFT0_WFG_WFIR_TMIE32                 *((volatile  uint16_t*)(0x42403628UL))
#define bFM_MFT0_WFG_WFIR_TMIS32                  *((volatile  uint16_t*)(0x4240362CUL))
#define bFM4_MFT0_WFG_WFIR_TMIS32                 *((volatile  uint16_t*)(0x4240362CUL))
#define bFM_MFT0_WFG_WFIR_TMIF54                  *((volatile  uint16_t*)(0x42403630UL))
#define bFM4_MFT0_WFG_WFIR_TMIF54                 *((volatile  uint16_t*)(0x42403630UL))
#define bFM_MFT0_WFG_WFIR_TMIC54                  *((volatile  uint16_t*)(0x42403634UL))
#define bFM4_MFT0_WFG_WFIR_TMIC54                 *((volatile  uint16_t*)(0x42403634UL))
#define bFM_MFT0_WFG_WFIR_TMIE54                  *((volatile  uint16_t*)(0x42403638UL))
#define bFM4_MFT0_WFG_WFIR_TMIE54                 *((volatile  uint16_t*)(0x42403638UL))
#define bFM_MFT0_WFG_WFIR_TMIS54                  *((volatile  uint16_t*)(0x4240363CUL))
#define bFM4_MFT0_WFG_WFIR_TMIS54                 *((volatile  uint16_t*)(0x4240363CUL))


/*******************************************************************************
* MFT Registers MFT1
*   Bitband Section
*******************************************************************************/
#define bFM_MFT1_ADCMP_ACMC0_MZCE                 *((volatile  uint8_t *)(0x42423AD8UL))
#define bFM4_MFT1_ADCMP_ACMC0_MZCE                *((volatile  uint8_t *)(0x42423AD8UL))
#define bFM_MFT1_ADCMP_ACMC0_MPCE                 *((volatile  uint8_t *)(0x42423ADCUL))
#define bFM4_MFT1_ADCMP_ACMC0_MPCE                *((volatile  uint8_t *)(0x42423ADCUL))

#define bFM_MFT1_ADCMP_ACMC1_MZCE                 *((volatile  uint8_t *)(0x42423B58UL))
#define bFM4_MFT1_ADCMP_ACMC1_MZCE                *((volatile  uint8_t *)(0x42423B58UL))
#define bFM_MFT1_ADCMP_ACMC1_MPCE                 *((volatile  uint8_t *)(0x42423B5CUL))
#define bFM4_MFT1_ADCMP_ACMC1_MPCE                *((volatile  uint8_t *)(0x42423B5CUL))

#define bFM_MFT1_ADCMP_ACMC2_MZCE                 *((volatile  uint8_t *)(0x42423BD8UL))
#define bFM4_MFT1_ADCMP_ACMC2_MZCE                *((volatile  uint8_t *)(0x42423BD8UL))
#define bFM_MFT1_ADCMP_ACMC2_MPCE                 *((volatile  uint8_t *)(0x42423BDCUL))
#define bFM4_MFT1_ADCMP_ACMC2_MPCE                *((volatile  uint8_t *)(0x42423BDCUL))

#define bFM_MFT1_ADCMP_ACMC3_MZCE                 *((volatile  uint8_t *)(0x42423C58UL))
#define bFM4_MFT1_ADCMP_ACMC3_MZCE                *((volatile  uint8_t *)(0x42423C58UL))
#define bFM_MFT1_ADCMP_ACMC3_MPCE                 *((volatile  uint8_t *)(0x42423C5CUL))
#define bFM4_MFT1_ADCMP_ACMC3_MPCE                *((volatile  uint8_t *)(0x42423C5CUL))

#define bFM_MFT1_ADCMP_ACMC4_MZCE                 *((volatile  uint8_t *)(0x42423CD8UL))
#define bFM4_MFT1_ADCMP_ACMC4_MZCE                *((volatile  uint8_t *)(0x42423CD8UL))
#define bFM_MFT1_ADCMP_ACMC4_MPCE                 *((volatile  uint8_t *)(0x42423CDCUL))
#define bFM4_MFT1_ADCMP_ACMC4_MPCE                *((volatile  uint8_t *)(0x42423CDCUL))

#define bFM_MFT1_ADCMP_ACMC5_MZCE                 *((volatile  uint8_t *)(0x42423D58UL))
#define bFM4_MFT1_ADCMP_ACMC5_MZCE                *((volatile  uint8_t *)(0x42423D58UL))
#define bFM_MFT1_ADCMP_ACMC5_MPCE                 *((volatile  uint8_t *)(0x42423D5CUL))
#define bFM4_MFT1_ADCMP_ACMC5_MPCE                *((volatile  uint8_t *)(0x42423D5CUL))

#define bFM_MFT1_ADCMP_ACSC0_APBM                 *((volatile  uint8_t *)(0x42423A94UL))
#define bFM4_MFT1_ADCMP_ACSC0_APBM                *((volatile  uint8_t *)(0x42423A94UL))

#define bFM_MFT1_ADCMP_ACSC1_APBM                 *((volatile  uint8_t *)(0x42423B14UL))
#define bFM4_MFT1_ADCMP_ACSC1_APBM                *((volatile  uint8_t *)(0x42423B14UL))

#define bFM_MFT1_ADCMP_ACSC2_APBM                 *((volatile  uint8_t *)(0x42423B94UL))
#define bFM4_MFT1_ADCMP_ACSC2_APBM                *((volatile  uint8_t *)(0x42423B94UL))

#define bFM_MFT1_ADCMP_ACSC3_APBM                 *((volatile  uint8_t *)(0x42423C14UL))
#define bFM4_MFT1_ADCMP_ACSC3_APBM                *((volatile  uint8_t *)(0x42423C14UL))

#define bFM_MFT1_ADCMP_ACSC4_APBM                 *((volatile  uint8_t *)(0x42423C94UL))
#define bFM4_MFT1_ADCMP_ACSC4_APBM                *((volatile  uint8_t *)(0x42423C94UL))

#define bFM_MFT1_ADCMP_ACSC5_APBM                 *((volatile  uint8_t *)(0x42423D14UL))
#define bFM4_MFT1_ADCMP_ACSC5_APBM                *((volatile  uint8_t *)(0x42423D14UL))

#define bFM_MFT1_ADCMP_ACSD0_AMOD                 *((volatile  uint8_t *)(0x42423AA0UL))
#define bFM4_MFT1_ADCMP_ACSD0_AMOD                *((volatile  uint8_t *)(0x42423AA0UL))
#define bFM_MFT1_ADCMP_ACSD0_OCUS                 *((volatile  uint8_t *)(0x42423AA4UL))
#define bFM4_MFT1_ADCMP_ACSD0_OCUS                *((volatile  uint8_t *)(0x42423AA4UL))
#define bFM_MFT1_ADCMP_ACSD0_DE                   *((volatile  uint8_t *)(0x42423AB0UL))
#define bFM4_MFT1_ADCMP_ACSD0_DE                  *((volatile  uint8_t *)(0x42423AB0UL))
#define bFM_MFT1_ADCMP_ACSD0_PE                   *((volatile  uint8_t *)(0x42423AB4UL))
#define bFM4_MFT1_ADCMP_ACSD0_PE                  *((volatile  uint8_t *)(0x42423AB4UL))
#define bFM_MFT1_ADCMP_ACSD0_UE                   *((volatile  uint8_t *)(0x42423AB8UL))
#define bFM4_MFT1_ADCMP_ACSD0_UE                  *((volatile  uint8_t *)(0x42423AB8UL))
#define bFM_MFT1_ADCMP_ACSD0_ZE                   *((volatile  uint8_t *)(0x42423ABCUL))
#define bFM4_MFT1_ADCMP_ACSD0_ZE                  *((volatile  uint8_t *)(0x42423ABCUL))

#define bFM_MFT1_ADCMP_ACSD1_AMOD                 *((volatile  uint8_t *)(0x42423B20UL))
#define bFM4_MFT1_ADCMP_ACSD1_AMOD                *((volatile  uint8_t *)(0x42423B20UL))
#define bFM_MFT1_ADCMP_ACSD1_OCUS                 *((volatile  uint8_t *)(0x42423B24UL))
#define bFM4_MFT1_ADCMP_ACSD1_OCUS                *((volatile  uint8_t *)(0x42423B24UL))
#define bFM_MFT1_ADCMP_ACSD1_DE                   *((volatile  uint8_t *)(0x42423B30UL))
#define bFM4_MFT1_ADCMP_ACSD1_DE                  *((volatile  uint8_t *)(0x42423B30UL))
#define bFM_MFT1_ADCMP_ACSD1_PE                   *((volatile  uint8_t *)(0x42423B34UL))
#define bFM4_MFT1_ADCMP_ACSD1_PE                  *((volatile  uint8_t *)(0x42423B34UL))
#define bFM_MFT1_ADCMP_ACSD1_UE                   *((volatile  uint8_t *)(0x42423B38UL))
#define bFM4_MFT1_ADCMP_ACSD1_UE                  *((volatile  uint8_t *)(0x42423B38UL))
#define bFM_MFT1_ADCMP_ACSD1_ZE                   *((volatile  uint8_t *)(0x42423B3CUL))
#define bFM4_MFT1_ADCMP_ACSD1_ZE                  *((volatile  uint8_t *)(0x42423B3CUL))

#define bFM_MFT1_ADCMP_ACSD2_AMOD                 *((volatile  uint8_t *)(0x42423BA0UL))
#define bFM4_MFT1_ADCMP_ACSD2_AMOD                *((volatile  uint8_t *)(0x42423BA0UL))
#define bFM_MFT1_ADCMP_ACSD2_OCUS                 *((volatile  uint8_t *)(0x42423BA4UL))
#define bFM4_MFT1_ADCMP_ACSD2_OCUS                *((volatile  uint8_t *)(0x42423BA4UL))
#define bFM_MFT1_ADCMP_ACSD2_DE                   *((volatile  uint8_t *)(0x42423BB0UL))
#define bFM4_MFT1_ADCMP_ACSD2_DE                  *((volatile  uint8_t *)(0x42423BB0UL))
#define bFM_MFT1_ADCMP_ACSD2_PE                   *((volatile  uint8_t *)(0x42423BB4UL))
#define bFM4_MFT1_ADCMP_ACSD2_PE                  *((volatile  uint8_t *)(0x42423BB4UL))
#define bFM_MFT1_ADCMP_ACSD2_UE                   *((volatile  uint8_t *)(0x42423BB8UL))
#define bFM4_MFT1_ADCMP_ACSD2_UE                  *((volatile  uint8_t *)(0x42423BB8UL))
#define bFM_MFT1_ADCMP_ACSD2_ZE                   *((volatile  uint8_t *)(0x42423BBCUL))
#define bFM4_MFT1_ADCMP_ACSD2_ZE                  *((volatile  uint8_t *)(0x42423BBCUL))

#define bFM_MFT1_ADCMP_ACSD3_AMOD                 *((volatile  uint8_t *)(0x42423C20UL))
#define bFM4_MFT1_ADCMP_ACSD3_AMOD                *((volatile  uint8_t *)(0x42423C20UL))
#define bFM_MFT1_ADCMP_ACSD3_OCUS                 *((volatile  uint8_t *)(0x42423C24UL))
#define bFM4_MFT1_ADCMP_ACSD3_OCUS                *((volatile  uint8_t *)(0x42423C24UL))
#define bFM_MFT1_ADCMP_ACSD3_DE                   *((volatile  uint8_t *)(0x42423C30UL))
#define bFM4_MFT1_ADCMP_ACSD3_DE                  *((volatile  uint8_t *)(0x42423C30UL))
#define bFM_MFT1_ADCMP_ACSD3_PE                   *((volatile  uint8_t *)(0x42423C34UL))
#define bFM4_MFT1_ADCMP_ACSD3_PE                  *((volatile  uint8_t *)(0x42423C34UL))
#define bFM_MFT1_ADCMP_ACSD3_UE                   *((volatile  uint8_t *)(0x42423C38UL))
#define bFM4_MFT1_ADCMP_ACSD3_UE                  *((volatile  uint8_t *)(0x42423C38UL))
#define bFM_MFT1_ADCMP_ACSD3_ZE                   *((volatile  uint8_t *)(0x42423C3CUL))
#define bFM4_MFT1_ADCMP_ACSD3_ZE                  *((volatile  uint8_t *)(0x42423C3CUL))

#define bFM_MFT1_ADCMP_ACSD4_AMOD                 *((volatile  uint8_t *)(0x42423CA0UL))
#define bFM4_MFT1_ADCMP_ACSD4_AMOD                *((volatile  uint8_t *)(0x42423CA0UL))
#define bFM_MFT1_ADCMP_ACSD4_OCUS                 *((volatile  uint8_t *)(0x42423CA4UL))
#define bFM4_MFT1_ADCMP_ACSD4_OCUS                *((volatile  uint8_t *)(0x42423CA4UL))
#define bFM_MFT1_ADCMP_ACSD4_DE                   *((volatile  uint8_t *)(0x42423CB0UL))
#define bFM4_MFT1_ADCMP_ACSD4_DE                  *((volatile  uint8_t *)(0x42423CB0UL))
#define bFM_MFT1_ADCMP_ACSD4_PE                   *((volatile  uint8_t *)(0x42423CB4UL))
#define bFM4_MFT1_ADCMP_ACSD4_PE                  *((volatile  uint8_t *)(0x42423CB4UL))
#define bFM_MFT1_ADCMP_ACSD4_UE                   *((volatile  uint8_t *)(0x42423CB8UL))
#define bFM4_MFT1_ADCMP_ACSD4_UE                  *((volatile  uint8_t *)(0x42423CB8UL))
#define bFM_MFT1_ADCMP_ACSD4_ZE                   *((volatile  uint8_t *)(0x42423CBCUL))
#define bFM4_MFT1_ADCMP_ACSD4_ZE                  *((volatile  uint8_t *)(0x42423CBCUL))

#define bFM_MFT1_ADCMP_ACSD5_AMOD                 *((volatile  uint8_t *)(0x42423D20UL))
#define bFM4_MFT1_ADCMP_ACSD5_AMOD                *((volatile  uint8_t *)(0x42423D20UL))
#define bFM_MFT1_ADCMP_ACSD5_OCUS                 *((volatile  uint8_t *)(0x42423D24UL))
#define bFM4_MFT1_ADCMP_ACSD5_OCUS                *((volatile  uint8_t *)(0x42423D24UL))
#define bFM_MFT1_ADCMP_ACSD5_DE                   *((volatile  uint8_t *)(0x42423D30UL))
#define bFM4_MFT1_ADCMP_ACSD5_DE                  *((volatile  uint8_t *)(0x42423D30UL))
#define bFM_MFT1_ADCMP_ACSD5_PE                   *((volatile  uint8_t *)(0x42423D34UL))
#define bFM4_MFT1_ADCMP_ACSD5_PE                  *((volatile  uint8_t *)(0x42423D34UL))
#define bFM_MFT1_ADCMP_ACSD5_UE                   *((volatile  uint8_t *)(0x42423D38UL))
#define bFM4_MFT1_ADCMP_ACSD5_UE                  *((volatile  uint8_t *)(0x42423D38UL))
#define bFM_MFT1_ADCMP_ACSD5_ZE                   *((volatile  uint8_t *)(0x42423D3CUL))
#define bFM4_MFT1_ADCMP_ACSD5_ZE                  *((volatile  uint8_t *)(0x42423D3CUL))

#define bFM_MFT1_FRT_TCAL_STOP00                  *((volatile  uint32_t*)(0x42422C80UL))
#define bFM4_MFT1_FRT_TCAL_STOP00                 *((volatile  uint32_t*)(0x42422C80UL))
#define bFM_MFT1_FRT_TCAL_STOP01                  *((volatile  uint32_t*)(0x42422C84UL))
#define bFM4_MFT1_FRT_TCAL_STOP01                 *((volatile  uint32_t*)(0x42422C84UL))
#define bFM_MFT1_FRT_TCAL_STOP02                  *((volatile  uint32_t*)(0x42422C88UL))
#define bFM4_MFT1_FRT_TCAL_STOP02                 *((volatile  uint32_t*)(0x42422C88UL))
#define bFM_MFT1_FRT_TCAL_STOP10                  *((volatile  uint32_t*)(0x42422C8CUL))
#define bFM4_MFT1_FRT_TCAL_STOP10                 *((volatile  uint32_t*)(0x42422C8CUL))
#define bFM_MFT1_FRT_TCAL_STOP11                  *((volatile  uint32_t*)(0x42422C90UL))
#define bFM4_MFT1_FRT_TCAL_STOP11                 *((volatile  uint32_t*)(0x42422C90UL))
#define bFM_MFT1_FRT_TCAL_STOP12                  *((volatile  uint32_t*)(0x42422C94UL))
#define bFM4_MFT1_FRT_TCAL_STOP12                 *((volatile  uint32_t*)(0x42422C94UL))
#define bFM_MFT1_FRT_TCAL_STOP20                  *((volatile  uint32_t*)(0x42422C98UL))
#define bFM4_MFT1_FRT_TCAL_STOP20                 *((volatile  uint32_t*)(0x42422C98UL))
#define bFM_MFT1_FRT_TCAL_STOP21                  *((volatile  uint32_t*)(0x42422C9CUL))
#define bFM4_MFT1_FRT_TCAL_STOP21                 *((volatile  uint32_t*)(0x42422C9CUL))
#define bFM_MFT1_FRT_TCAL_STOP22                  *((volatile  uint32_t*)(0x42422CA0UL))
#define bFM4_MFT1_FRT_TCAL_STOP22                 *((volatile  uint32_t*)(0x42422CA0UL))
#define bFM_MFT1_FRT_TCAL_SCLR00                  *((volatile  uint32_t*)(0x42422CC0UL))
#define bFM4_MFT1_FRT_TCAL_SCLR00                 *((volatile  uint32_t*)(0x42422CC0UL))
#define bFM_MFT1_FRT_TCAL_SCLR01                  *((volatile  uint32_t*)(0x42422CC4UL))
#define bFM4_MFT1_FRT_TCAL_SCLR01                 *((volatile  uint32_t*)(0x42422CC4UL))
#define bFM_MFT1_FRT_TCAL_SCLR02                  *((volatile  uint32_t*)(0x42422CC8UL))
#define bFM4_MFT1_FRT_TCAL_SCLR02                 *((volatile  uint32_t*)(0x42422CC8UL))
#define bFM_MFT1_FRT_TCAL_SCLR10                  *((volatile  uint32_t*)(0x42422CCCUL))
#define bFM4_MFT1_FRT_TCAL_SCLR10                 *((volatile  uint32_t*)(0x42422CCCUL))
#define bFM_MFT1_FRT_TCAL_SCLR11                  *((volatile  uint32_t*)(0x42422CD0UL))
#define bFM4_MFT1_FRT_TCAL_SCLR11                 *((volatile  uint32_t*)(0x42422CD0UL))
#define bFM_MFT1_FRT_TCAL_SCLR12                  *((volatile  uint32_t*)(0x42422CD4UL))
#define bFM4_MFT1_FRT_TCAL_SCLR12                 *((volatile  uint32_t*)(0x42422CD4UL))
#define bFM_MFT1_FRT_TCAL_SCLR20                  *((volatile  uint32_t*)(0x42422CD8UL))
#define bFM4_MFT1_FRT_TCAL_SCLR20                 *((volatile  uint32_t*)(0x42422CD8UL))
#define bFM_MFT1_FRT_TCAL_SCLR21                  *((volatile  uint32_t*)(0x42422CDCUL))
#define bFM4_MFT1_FRT_TCAL_SCLR21                 *((volatile  uint32_t*)(0x42422CDCUL))
#define bFM_MFT1_FRT_TCAL_SCLR22                  *((volatile  uint32_t*)(0x42422CE0UL))
#define bFM4_MFT1_FRT_TCAL_SCLR22                 *((volatile  uint32_t*)(0x42422CE0UL))

#define bFM_MFT1_FRT_TCSA0_SCLR                   *((volatile  uint8_t *)(0x42422910UL))
#define bFM4_MFT1_FRT_TCSA0_SCLR                  *((volatile  uint8_t *)(0x42422910UL))
#define bFM_MFT1_FRT_TCSA0_MODE                   *((volatile  uint8_t *)(0x42422914UL))
#define bFM4_MFT1_FRT_TCSA0_MODE                  *((volatile  uint8_t *)(0x42422914UL))
#define bFM_MFT1_FRT_TCSA0_STOP                   *((volatile  uint8_t *)(0x42422918UL))
#define bFM4_MFT1_FRT_TCSA0_STOP                  *((volatile  uint8_t *)(0x42422918UL))
#define bFM_MFT1_FRT_TCSA0_BFE                    *((volatile  uint8_t *)(0x4242291CUL))
#define bFM4_MFT1_FRT_TCSA0_BFE                   *((volatile  uint8_t *)(0x4242291CUL))
#define bFM_MFT1_FRT_TCSA0_ICRE                   *((volatile  uint8_t *)(0x42422920UL))
#define bFM4_MFT1_FRT_TCSA0_ICRE                  *((volatile  uint8_t *)(0x42422920UL))
#define bFM_MFT1_FRT_TCSA0_ICLR                   *((volatile  uint8_t *)(0x42422924UL))
#define bFM4_MFT1_FRT_TCSA0_ICLR                  *((volatile  uint8_t *)(0x42422924UL))
#define bFM_MFT1_FRT_TCSA0_IRQZE                  *((volatile  uint8_t *)(0x42422934UL))
#define bFM4_MFT1_FRT_TCSA0_IRQZE                 *((volatile  uint8_t *)(0x42422934UL))
#define bFM_MFT1_FRT_TCSA0_IRQZF                  *((volatile  uint8_t *)(0x42422938UL))
#define bFM4_MFT1_FRT_TCSA0_IRQZF                 *((volatile  uint8_t *)(0x42422938UL))
#define bFM_MFT1_FRT_TCSA0_ECKE                   *((volatile  uint8_t *)(0x4242293CUL))
#define bFM4_MFT1_FRT_TCSA0_ECKE                  *((volatile  uint8_t *)(0x4242293CUL))

#define bFM_MFT1_FRT_TCSA1_SCLR                   *((volatile  uint8_t *)(0x42422A90UL))
#define bFM4_MFT1_FRT_TCSA1_SCLR                  *((volatile  uint8_t *)(0x42422A90UL))
#define bFM_MFT1_FRT_TCSA1_MODE                   *((volatile  uint8_t *)(0x42422A94UL))
#define bFM4_MFT1_FRT_TCSA1_MODE                  *((volatile  uint8_t *)(0x42422A94UL))
#define bFM_MFT1_FRT_TCSA1_STOP                   *((volatile  uint8_t *)(0x42422A98UL))
#define bFM4_MFT1_FRT_TCSA1_STOP                  *((volatile  uint8_t *)(0x42422A98UL))
#define bFM_MFT1_FRT_TCSA1_BFE                    *((volatile  uint8_t *)(0x42422A9CUL))
#define bFM4_MFT1_FRT_TCSA1_BFE                   *((volatile  uint8_t *)(0x42422A9CUL))
#define bFM_MFT1_FRT_TCSA1_ICRE                   *((volatile  uint8_t *)(0x42422AA0UL))
#define bFM4_MFT1_FRT_TCSA1_ICRE                  *((volatile  uint8_t *)(0x42422AA0UL))
#define bFM_MFT1_FRT_TCSA1_ICLR                   *((volatile  uint8_t *)(0x42422AA4UL))
#define bFM4_MFT1_FRT_TCSA1_ICLR                  *((volatile  uint8_t *)(0x42422AA4UL))
#define bFM_MFT1_FRT_TCSA1_IRQZE                  *((volatile  uint8_t *)(0x42422AB4UL))
#define bFM4_MFT1_FRT_TCSA1_IRQZE                 *((volatile  uint8_t *)(0x42422AB4UL))
#define bFM_MFT1_FRT_TCSA1_IRQZF                  *((volatile  uint8_t *)(0x42422AB8UL))
#define bFM4_MFT1_FRT_TCSA1_IRQZF                 *((volatile  uint8_t *)(0x42422AB8UL))
#define bFM_MFT1_FRT_TCSA1_ECKE                   *((volatile  uint8_t *)(0x42422ABCUL))
#define bFM4_MFT1_FRT_TCSA1_ECKE                  *((volatile  uint8_t *)(0x42422ABCUL))

#define bFM_MFT1_FRT_TCSA2_SCLR                   *((volatile  uint8_t *)(0x42422C10UL))
#define bFM4_MFT1_FRT_TCSA2_SCLR                  *((volatile  uint8_t *)(0x42422C10UL))
#define bFM_MFT1_FRT_TCSA2_MODE                   *((volatile  uint8_t *)(0x42422C14UL))
#define bFM4_MFT1_FRT_TCSA2_MODE                  *((volatile  uint8_t *)(0x42422C14UL))
#define bFM_MFT1_FRT_TCSA2_STOP                   *((volatile  uint8_t *)(0x42422C18UL))
#define bFM4_MFT1_FRT_TCSA2_STOP                  *((volatile  uint8_t *)(0x42422C18UL))
#define bFM_MFT1_FRT_TCSA2_BFE                    *((volatile  uint8_t *)(0x42422C1CUL))
#define bFM4_MFT1_FRT_TCSA2_BFE                   *((volatile  uint8_t *)(0x42422C1CUL))
#define bFM_MFT1_FRT_TCSA2_ICRE                   *((volatile  uint8_t *)(0x42422C20UL))
#define bFM4_MFT1_FRT_TCSA2_ICRE                  *((volatile  uint8_t *)(0x42422C20UL))
#define bFM_MFT1_FRT_TCSA2_ICLR                   *((volatile  uint8_t *)(0x42422C24UL))
#define bFM4_MFT1_FRT_TCSA2_ICLR                  *((volatile  uint8_t *)(0x42422C24UL))
#define bFM_MFT1_FRT_TCSA2_IRQZE                  *((volatile  uint8_t *)(0x42422C34UL))
#define bFM4_MFT1_FRT_TCSA2_IRQZE                 *((volatile  uint8_t *)(0x42422C34UL))
#define bFM_MFT1_FRT_TCSA2_IRQZF                  *((volatile  uint8_t *)(0x42422C38UL))
#define bFM4_MFT1_FRT_TCSA2_IRQZF                 *((volatile  uint8_t *)(0x42422C38UL))
#define bFM_MFT1_FRT_TCSA2_ECKE                   *((volatile  uint8_t *)(0x42422C3CUL))
#define bFM4_MFT1_FRT_TCSA2_ECKE                  *((volatile  uint8_t *)(0x42422C3CUL))

#define bFM_MFT1_FRT_TCSD_OFMD1                   *((volatile  uint8_t *)(0x42423D80UL))
#define bFM4_MFT1_FRT_TCSD_OFMD1                  *((volatile  uint8_t *)(0x42423D80UL))
#define bFM_MFT1_FRT_TCSD_OFMD2                   *((volatile  uint8_t *)(0x42423D84UL))
#define bFM4_MFT1_FRT_TCSD_OFMD2                  *((volatile  uint8_t *)(0x42423D84UL))

#define bFM_MFT1_ICU_ICSA10_ICE0                  *((volatile  uint8_t *)(0x42423090UL))
#define bFM4_MFT1_ICU_ICSA10_ICE0                 *((volatile  uint8_t *)(0x42423090UL))
#define bFM_MFT1_ICU_ICSA10_ICE1                  *((volatile  uint8_t *)(0x42423094UL))
#define bFM4_MFT1_ICU_ICSA10_ICE1                 *((volatile  uint8_t *)(0x42423094UL))
#define bFM_MFT1_ICU_ICSA10_ICP0                  *((volatile  uint8_t *)(0x42423098UL))
#define bFM4_MFT1_ICU_ICSA10_ICP0                 *((volatile  uint8_t *)(0x42423098UL))
#define bFM_MFT1_ICU_ICSA10_ICP1                  *((volatile  uint8_t *)(0x4242309CUL))
#define bFM4_MFT1_ICU_ICSA10_ICP1                 *((volatile  uint8_t *)(0x4242309CUL))

#define bFM_MFT1_ICU_ICSA32_ICE2                  *((volatile  uint8_t *)(0x42423110UL))
#define bFM4_MFT1_ICU_ICSA32_ICE2                 *((volatile  uint8_t *)(0x42423110UL))
#define bFM_MFT1_ICU_ICSA32_ICE3                  *((volatile  uint8_t *)(0x42423114UL))
#define bFM4_MFT1_ICU_ICSA32_ICE3                 *((volatile  uint8_t *)(0x42423114UL))
#define bFM_MFT1_ICU_ICSA32_ICP2                  *((volatile  uint8_t *)(0x42423118UL))
#define bFM4_MFT1_ICU_ICSA32_ICP2                 *((volatile  uint8_t *)(0x42423118UL))
#define bFM_MFT1_ICU_ICSA32_ICP3                  *((volatile  uint8_t *)(0x4242311CUL))
#define bFM4_MFT1_ICU_ICSA32_ICP3                 *((volatile  uint8_t *)(0x4242311CUL))

#define bFM_MFT1_ICU_ICSB10_IEI0                  *((volatile  uint8_t *)(0x424230A0UL))
#define bFM4_MFT1_ICU_ICSB10_IEI0                 *((volatile  uint8_t *)(0x424230A0UL))
#define bFM_MFT1_ICU_ICSB10_IEI1                  *((volatile  uint8_t *)(0x424230A4UL))
#define bFM4_MFT1_ICU_ICSB10_IEI1                 *((volatile  uint8_t *)(0x424230A4UL))

#define bFM_MFT1_ICU_ICSB32_IEI2                  *((volatile  uint8_t *)(0x42423120UL))
#define bFM4_MFT1_ICU_ICSB32_IEI2                 *((volatile  uint8_t *)(0x42423120UL))
#define bFM_MFT1_ICU_ICSB32_IEI3                  *((volatile  uint8_t *)(0x42423124UL))
#define bFM4_MFT1_ICU_ICSB32_IEI3                 *((volatile  uint8_t *)(0x42423124UL))

#define bFM_MFT1_OCU_OCSA10_CST0                  *((volatile  uint8_t *)(0x42422300UL))
#define bFM4_MFT1_OCU_OCSA10_CST0                 *((volatile  uint8_t *)(0x42422300UL))
#define bFM_MFT1_OCU_OCSA10_CST1                  *((volatile  uint8_t *)(0x42422304UL))
#define bFM4_MFT1_OCU_OCSA10_CST1                 *((volatile  uint8_t *)(0x42422304UL))
#define bFM_MFT1_OCU_OCSA10_IOE0                  *((volatile  uint8_t *)(0x42422310UL))
#define bFM4_MFT1_OCU_OCSA10_IOE0                 *((volatile  uint8_t *)(0x42422310UL))
#define bFM_MFT1_OCU_OCSA10_IOE1                  *((volatile  uint8_t *)(0x42422314UL))
#define bFM4_MFT1_OCU_OCSA10_IOE1                 *((volatile  uint8_t *)(0x42422314UL))
#define bFM_MFT1_OCU_OCSA10_IOP0                  *((volatile  uint8_t *)(0x42422318UL))
#define bFM4_MFT1_OCU_OCSA10_IOP0                 *((volatile  uint8_t *)(0x42422318UL))
#define bFM_MFT1_OCU_OCSA10_IOP1                  *((volatile  uint8_t *)(0x4242231CUL))
#define bFM4_MFT1_OCU_OCSA10_IOP1                 *((volatile  uint8_t *)(0x4242231CUL))

#define bFM_MFT1_OCU_OCSA32_CST2                  *((volatile  uint8_t *)(0x42422380UL))
#define bFM4_MFT1_OCU_OCSA32_CST2                 *((volatile  uint8_t *)(0x42422380UL))
#define bFM_MFT1_OCU_OCSA32_CST3                  *((volatile  uint8_t *)(0x42422384UL))
#define bFM4_MFT1_OCU_OCSA32_CST3                 *((volatile  uint8_t *)(0x42422384UL))
#define bFM_MFT1_OCU_OCSA32_IOE2                  *((volatile  uint8_t *)(0x42422390UL))
#define bFM4_MFT1_OCU_OCSA32_IOE2                 *((volatile  uint8_t *)(0x42422390UL))
#define bFM_MFT1_OCU_OCSA32_IOE3                  *((volatile  uint8_t *)(0x42422394UL))
#define bFM4_MFT1_OCU_OCSA32_IOE3                 *((volatile  uint8_t *)(0x42422394UL))
#define bFM_MFT1_OCU_OCSA32_IOP2                  *((volatile  uint8_t *)(0x42422398UL))
#define bFM4_MFT1_OCU_OCSA32_IOP2                 *((volatile  uint8_t *)(0x42422398UL))
#define bFM_MFT1_OCU_OCSA32_IOP3                  *((volatile  uint8_t *)(0x4242239CUL))
#define bFM4_MFT1_OCU_OCSA32_IOP3                 *((volatile  uint8_t *)(0x4242239CUL))

#define bFM_MFT1_OCU_OCSA54_CST4                  *((volatile  uint8_t *)(0x42422400UL))
#define bFM4_MFT1_OCU_OCSA54_CST4                 *((volatile  uint8_t *)(0x42422400UL))
#define bFM_MFT1_OCU_OCSA54_CST5                  *((volatile  uint8_t *)(0x42422404UL))
#define bFM4_MFT1_OCU_OCSA54_CST5                 *((volatile  uint8_t *)(0x42422404UL))
#define bFM_MFT1_OCU_OCSA54_IOE4                  *((volatile  uint8_t *)(0x42422410UL))
#define bFM4_MFT1_OCU_OCSA54_IOE4                 *((volatile  uint8_t *)(0x42422410UL))
#define bFM_MFT1_OCU_OCSA54_IOE5                  *((volatile  uint8_t *)(0x42422414UL))
#define bFM4_MFT1_OCU_OCSA54_IOE5                 *((volatile  uint8_t *)(0x42422414UL))
#define bFM_MFT1_OCU_OCSA54_IOP4                  *((volatile  uint8_t *)(0x42422418UL))
#define bFM4_MFT1_OCU_OCSA54_IOP4                 *((volatile  uint8_t *)(0x42422418UL))
#define bFM_MFT1_OCU_OCSA54_IOP5                  *((volatile  uint8_t *)(0x4242241CUL))
#define bFM4_MFT1_OCU_OCSA54_IOP5                 *((volatile  uint8_t *)(0x4242241CUL))

#define bFM_MFT1_OCU_OCSB10_OTD0                  *((volatile  uint8_t *)(0x42422320UL))
#define bFM4_MFT1_OCU_OCSB10_OTD0                 *((volatile  uint8_t *)(0x42422320UL))
#define bFM_MFT1_OCU_OCSB10_OTD1                  *((volatile  uint8_t *)(0x42422324UL))
#define bFM4_MFT1_OCU_OCSB10_OTD1                 *((volatile  uint8_t *)(0x42422324UL))
#define bFM_MFT1_OCU_OCSB10_CMOD                  *((volatile  uint8_t *)(0x42422330UL))
#define bFM4_MFT1_OCU_OCSB10_CMOD                 *((volatile  uint8_t *)(0x42422330UL))
#define bFM_MFT1_OCU_OCSB10_FM4                   *((volatile  uint8_t *)(0x4242233CUL))
#define bFM4_MFT1_OCU_OCSB10_FM4                  *((volatile  uint8_t *)(0x4242233CUL))

#define bFM_MFT1_OCU_OCSB32_OTD2                  *((volatile  uint8_t *)(0x424223A0UL))
#define bFM4_MFT1_OCU_OCSB32_OTD2                 *((volatile  uint8_t *)(0x424223A0UL))
#define bFM_MFT1_OCU_OCSB32_OTD3                  *((volatile  uint8_t *)(0x424223A4UL))
#define bFM4_MFT1_OCU_OCSB32_OTD3                 *((volatile  uint8_t *)(0x424223A4UL))
#define bFM_MFT1_OCU_OCSB32_CMOD                  *((volatile  uint8_t *)(0x424223B0UL))
#define bFM4_MFT1_OCU_OCSB32_CMOD                 *((volatile  uint8_t *)(0x424223B0UL))
#define bFM_MFT1_OCU_OCSB32_FM4                   *((volatile  uint8_t *)(0x424223BCUL))
#define bFM4_MFT1_OCU_OCSB32_FM4                  *((volatile  uint8_t *)(0x424223BCUL))

#define bFM_MFT1_OCU_OCSB54_OTD4                  *((volatile  uint8_t *)(0x42422420UL))
#define bFM4_MFT1_OCU_OCSB54_OTD4                 *((volatile  uint8_t *)(0x42422420UL))
#define bFM_MFT1_OCU_OCSB54_OTD5                  *((volatile  uint8_t *)(0x42422424UL))
#define bFM4_MFT1_OCU_OCSB54_OTD5                 *((volatile  uint8_t *)(0x42422424UL))
#define bFM_MFT1_OCU_OCSB54_CMOD                  *((volatile  uint8_t *)(0x42422430UL))
#define bFM4_MFT1_OCU_OCSB54_CMOD                 *((volatile  uint8_t *)(0x42422430UL))
#define bFM_MFT1_OCU_OCSB54_FM4                   *((volatile  uint8_t *)(0x4242243CUL))
#define bFM4_MFT1_OCU_OCSB54_FM4                  *((volatile  uint8_t *)(0x4242243CUL))

#define bFM_MFT1_OCU_OCSC_MOD0                    *((volatile  uint8_t *)(0x424224A0UL))
#define bFM4_MFT1_OCU_OCSC_MOD0                   *((volatile  uint8_t *)(0x424224A0UL))
#define bFM_MFT1_OCU_OCSC_MOD1                    *((volatile  uint8_t *)(0x424224A4UL))
#define bFM4_MFT1_OCU_OCSC_MOD1                   *((volatile  uint8_t *)(0x424224A4UL))
#define bFM_MFT1_OCU_OCSC_MOD2                    *((volatile  uint8_t *)(0x424224A8UL))
#define bFM4_MFT1_OCU_OCSC_MOD2                   *((volatile  uint8_t *)(0x424224A8UL))
#define bFM_MFT1_OCU_OCSC_MOD3                    *((volatile  uint8_t *)(0x424224ACUL))
#define bFM4_MFT1_OCU_OCSC_MOD3                   *((volatile  uint8_t *)(0x424224ACUL))
#define bFM_MFT1_OCU_OCSC_MOD4                    *((volatile  uint8_t *)(0x424224B0UL))
#define bFM4_MFT1_OCU_OCSC_MOD4                   *((volatile  uint8_t *)(0x424224B0UL))
#define bFM_MFT1_OCU_OCSC_MOD5                    *((volatile  uint8_t *)(0x424224B4UL))
#define bFM4_MFT1_OCU_OCSC_MOD5                   *((volatile  uint8_t *)(0x424224B4UL))

#define bFM_MFT1_OCU_OCSD10_OPBM0                 *((volatile  uint8_t *)(0x42422360UL))
#define bFM4_MFT1_OCU_OCSD10_OPBM0                *((volatile  uint8_t *)(0x42422360UL))
#define bFM_MFT1_OCU_OCSD10_OPBM1                 *((volatile  uint8_t *)(0x42422364UL))
#define bFM4_MFT1_OCU_OCSD10_OPBM1                *((volatile  uint8_t *)(0x42422364UL))
#define bFM_MFT1_OCU_OCSD10_OEBM0                 *((volatile  uint8_t *)(0x42422368UL))
#define bFM4_MFT1_OCU_OCSD10_OEBM0                *((volatile  uint8_t *)(0x42422368UL))
#define bFM_MFT1_OCU_OCSD10_OEBM1                 *((volatile  uint8_t *)(0x4242236CUL))
#define bFM4_MFT1_OCU_OCSD10_OEBM1                *((volatile  uint8_t *)(0x4242236CUL))
#define bFM_MFT1_OCU_OCSD10_OFEX0                 *((volatile  uint8_t *)(0x42422370UL))
#define bFM4_MFT1_OCU_OCSD10_OFEX0                *((volatile  uint8_t *)(0x42422370UL))
#define bFM_MFT1_OCU_OCSD10_OFEX1                 *((volatile  uint8_t *)(0x42422374UL))
#define bFM4_MFT1_OCU_OCSD10_OFEX1                *((volatile  uint8_t *)(0x42422374UL))

#define bFM_MFT1_OCU_OCSD32_OPBM2                 *((volatile  uint8_t *)(0x424223E0UL))
#define bFM4_MFT1_OCU_OCSD32_OPBM2                *((volatile  uint8_t *)(0x424223E0UL))
#define bFM_MFT1_OCU_OCSD32_OPBM3                 *((volatile  uint8_t *)(0x424223E4UL))
#define bFM4_MFT1_OCU_OCSD32_OPBM3                *((volatile  uint8_t *)(0x424223E4UL))
#define bFM_MFT1_OCU_OCSD32_OEBM2                 *((volatile  uint8_t *)(0x424223E8UL))
#define bFM4_MFT1_OCU_OCSD32_OEBM2                *((volatile  uint8_t *)(0x424223E8UL))
#define bFM_MFT1_OCU_OCSD32_OEBM3                 *((volatile  uint8_t *)(0x424223ECUL))
#define bFM4_MFT1_OCU_OCSD32_OEBM3                *((volatile  uint8_t *)(0x424223ECUL))
#define bFM_MFT1_OCU_OCSD32_OFEX2                 *((volatile  uint8_t *)(0x424223F0UL))
#define bFM4_MFT1_OCU_OCSD32_OFEX2                *((volatile  uint8_t *)(0x424223F0UL))
#define bFM_MFT1_OCU_OCSD32_OFEX3                 *((volatile  uint8_t *)(0x424223F4UL))
#define bFM4_MFT1_OCU_OCSD32_OFEX3                *((volatile  uint8_t *)(0x424223F4UL))

#define bFM_MFT1_OCU_OCSD54_OPBM4                 *((volatile  uint8_t *)(0x42422460UL))
#define bFM4_MFT1_OCU_OCSD54_OPBM4                *((volatile  uint8_t *)(0x42422460UL))
#define bFM_MFT1_OCU_OCSD54_OPBM5                 *((volatile  uint8_t *)(0x42422464UL))
#define bFM4_MFT1_OCU_OCSD54_OPBM5                *((volatile  uint8_t *)(0x42422464UL))
#define bFM_MFT1_OCU_OCSD54_OEBM4                 *((volatile  uint8_t *)(0x42422468UL))
#define bFM4_MFT1_OCU_OCSD54_OEBM4                *((volatile  uint8_t *)(0x42422468UL))
#define bFM_MFT1_OCU_OCSD54_OEBM5                 *((volatile  uint8_t *)(0x4242246CUL))
#define bFM4_MFT1_OCU_OCSD54_OEBM5                *((volatile  uint8_t *)(0x4242246CUL))
#define bFM_MFT1_OCU_OCSD54_OFEX4                 *((volatile  uint8_t *)(0x42422470UL))
#define bFM4_MFT1_OCU_OCSD54_OFEX4                *((volatile  uint8_t *)(0x42422470UL))
#define bFM_MFT1_OCU_OCSD54_OFEX5                 *((volatile  uint8_t *)(0x42422474UL))
#define bFM4_MFT1_OCU_OCSD54_OFEX5                *((volatile  uint8_t *)(0x42422474UL))

#define bFM_MFT1_WFG_NZCL_DTIEA                   *((volatile  uint16_t*)(0x42423680UL))
#define bFM4_MFT1_WFG_NZCL_DTIEA                  *((volatile  uint16_t*)(0x42423680UL))
#define bFM_MFT1_WFG_NZCL_SDTI                    *((volatile  uint16_t*)(0x42423690UL))
#define bFM4_MFT1_WFG_NZCL_SDTI                   *((volatile  uint16_t*)(0x42423690UL))
#define bFM_MFT1_WFG_NZCL_DTIEB                   *((volatile  uint16_t*)(0x42423694UL))
#define bFM4_MFT1_WFG_NZCL_DTIEB                  *((volatile  uint16_t*)(0x42423694UL))
#define bFM_MFT1_WFG_NZCL_DHOLD                   *((volatile  uint16_t*)(0x4242369CUL))
#define bFM4_MFT1_WFG_NZCL_DHOLD                  *((volatile  uint16_t*)(0x4242369CUL))
#define bFM_MFT1_WFG_NZCL_DIMA                    *((volatile  uint16_t*)(0x424236A0UL))
#define bFM4_MFT1_WFG_NZCL_DIMA                   *((volatile  uint16_t*)(0x424236A0UL))
#define bFM_MFT1_WFG_NZCL_DIMB                    *((volatile  uint16_t*)(0x424236A4UL))
#define bFM4_MFT1_WFG_NZCL_DIMB                   *((volatile  uint16_t*)(0x424236A4UL))
#define bFM_MFT1_WFG_NZCL_WIM10                   *((volatile  uint16_t*)(0x424236B0UL))
#define bFM4_MFT1_WFG_NZCL_WIM10                  *((volatile  uint16_t*)(0x424236B0UL))
#define bFM_MFT1_WFG_NZCL_WIM32                   *((volatile  uint16_t*)(0x424236B4UL))
#define bFM4_MFT1_WFG_NZCL_WIM32                  *((volatile  uint16_t*)(0x424236B4UL))
#define bFM_MFT1_WFG_NZCL_WIM54                   *((volatile  uint16_t*)(0x424236B8UL))
#define bFM4_MFT1_WFG_NZCL_WIM54                  *((volatile  uint16_t*)(0x424236B8UL))

#define bFM_MFT1_WFG_WFIR_DTIFA                   *((volatile  uint16_t*)(0x42423600UL))
#define bFM4_MFT1_WFG_WFIR_DTIFA                  *((volatile  uint16_t*)(0x42423600UL))
#define bFM_MFT1_WFG_WFIR_DTICA                   *((volatile  uint16_t*)(0x42423604UL))
#define bFM4_MFT1_WFG_WFIR_DTICA                  *((volatile  uint16_t*)(0x42423604UL))
#define bFM_MFT1_WFG_WFIR_DTIFB                   *((volatile  uint16_t*)(0x42423608UL))
#define bFM4_MFT1_WFG_WFIR_DTIFB                  *((volatile  uint16_t*)(0x42423608UL))
#define bFM_MFT1_WFG_WFIR_DTICB                   *((volatile  uint16_t*)(0x4242360CUL))
#define bFM4_MFT1_WFG_WFIR_DTICB                  *((volatile  uint16_t*)(0x4242360CUL))
#define bFM_MFT1_WFG_WFIR_TMIF10                  *((volatile  uint16_t*)(0x42423610UL))
#define bFM4_MFT1_WFG_WFIR_TMIF10                 *((volatile  uint16_t*)(0x42423610UL))
#define bFM_MFT1_WFG_WFIR_TMIC10                  *((volatile  uint16_t*)(0x42423614UL))
#define bFM4_MFT1_WFG_WFIR_TMIC10                 *((volatile  uint16_t*)(0x42423614UL))
#define bFM_MFT1_WFG_WFIR_TMIE10                  *((volatile  uint16_t*)(0x42423618UL))
#define bFM4_MFT1_WFG_WFIR_TMIE10                 *((volatile  uint16_t*)(0x42423618UL))
#define bFM_MFT1_WFG_WFIR_TMIS10                  *((volatile  uint16_t*)(0x4242361CUL))
#define bFM4_MFT1_WFG_WFIR_TMIS10                 *((volatile  uint16_t*)(0x4242361CUL))
#define bFM_MFT1_WFG_WFIR_TMIF32                  *((volatile  uint16_t*)(0x42423620UL))
#define bFM4_MFT1_WFG_WFIR_TMIF32                 *((volatile  uint16_t*)(0x42423620UL))
#define bFM_MFT1_WFG_WFIR_TMIC32                  *((volatile  uint16_t*)(0x42423624UL))
#define bFM4_MFT1_WFG_WFIR_TMIC32                 *((volatile  uint16_t*)(0x42423624UL))
#define bFM_MFT1_WFG_WFIR_TMIE32                  *((volatile  uint16_t*)(0x42423628UL))
#define bFM4_MFT1_WFG_WFIR_TMIE32                 *((volatile  uint16_t*)(0x42423628UL))
#define bFM_MFT1_WFG_WFIR_TMIS32                  *((volatile  uint16_t*)(0x4242362CUL))
#define bFM4_MFT1_WFG_WFIR_TMIS32                 *((volatile  uint16_t*)(0x4242362CUL))
#define bFM_MFT1_WFG_WFIR_TMIF54                  *((volatile  uint16_t*)(0x42423630UL))
#define bFM4_MFT1_WFG_WFIR_TMIF54                 *((volatile  uint16_t*)(0x42423630UL))
#define bFM_MFT1_WFG_WFIR_TMIC54                  *((volatile  uint16_t*)(0x42423634UL))
#define bFM4_MFT1_WFG_WFIR_TMIC54                 *((volatile  uint16_t*)(0x42423634UL))
#define bFM_MFT1_WFG_WFIR_TMIE54                  *((volatile  uint16_t*)(0x42423638UL))
#define bFM4_MFT1_WFG_WFIR_TMIE54                 *((volatile  uint16_t*)(0x42423638UL))
#define bFM_MFT1_WFG_WFIR_TMIS54                  *((volatile  uint16_t*)(0x4242363CUL))
#define bFM4_MFT1_WFG_WFIR_TMIS54                 *((volatile  uint16_t*)(0x4242363CUL))


/*******************************************************************************
* MFT Registers MFT2
*   Bitband Section
*******************************************************************************/
#define bFM_MFT2_ADCMP_ACMC0_MZCE                 *((volatile  uint8_t *)(0x42443AD8UL))
#define bFM4_MFT2_ADCMP_ACMC0_MZCE                *((volatile  uint8_t *)(0x42443AD8UL))
#define bFM_MFT2_ADCMP_ACMC0_MPCE                 *((volatile  uint8_t *)(0x42443ADCUL))
#define bFM4_MFT2_ADCMP_ACMC0_MPCE                *((volatile  uint8_t *)(0x42443ADCUL))

#define bFM_MFT2_ADCMP_ACMC1_MZCE                 *((volatile  uint8_t *)(0x42443B58UL))
#define bFM4_MFT2_ADCMP_ACMC1_MZCE                *((volatile  uint8_t *)(0x42443B58UL))
#define bFM_MFT2_ADCMP_ACMC1_MPCE                 *((volatile  uint8_t *)(0x42443B5CUL))
#define bFM4_MFT2_ADCMP_ACMC1_MPCE                *((volatile  uint8_t *)(0x42443B5CUL))

#define bFM_MFT2_ADCMP_ACMC2_MZCE                 *((volatile  uint8_t *)(0x42443BD8UL))
#define bFM4_MFT2_ADCMP_ACMC2_MZCE                *((volatile  uint8_t *)(0x42443BD8UL))
#define bFM_MFT2_ADCMP_ACMC2_MPCE                 *((volatile  uint8_t *)(0x42443BDCUL))
#define bFM4_MFT2_ADCMP_ACMC2_MPCE                *((volatile  uint8_t *)(0x42443BDCUL))

#define bFM_MFT2_ADCMP_ACMC3_MZCE                 *((volatile  uint8_t *)(0x42443C58UL))
#define bFM4_MFT2_ADCMP_ACMC3_MZCE                *((volatile  uint8_t *)(0x42443C58UL))
#define bFM_MFT2_ADCMP_ACMC3_MPCE                 *((volatile  uint8_t *)(0x42443C5CUL))
#define bFM4_MFT2_ADCMP_ACMC3_MPCE                *((volatile  uint8_t *)(0x42443C5CUL))

#define bFM_MFT2_ADCMP_ACMC4_MZCE                 *((volatile  uint8_t *)(0x42443CD8UL))
#define bFM4_MFT2_ADCMP_ACMC4_MZCE                *((volatile  uint8_t *)(0x42443CD8UL))
#define bFM_MFT2_ADCMP_ACMC4_MPCE                 *((volatile  uint8_t *)(0x42443CDCUL))
#define bFM4_MFT2_ADCMP_ACMC4_MPCE                *((volatile  uint8_t *)(0x42443CDCUL))

#define bFM_MFT2_ADCMP_ACMC5_MZCE                 *((volatile  uint8_t *)(0x42443D58UL))
#define bFM4_MFT2_ADCMP_ACMC5_MZCE                *((volatile  uint8_t *)(0x42443D58UL))
#define bFM_MFT2_ADCMP_ACMC5_MPCE                 *((volatile  uint8_t *)(0x42443D5CUL))
#define bFM4_MFT2_ADCMP_ACMC5_MPCE                *((volatile  uint8_t *)(0x42443D5CUL))

#define bFM_MFT2_ADCMP_ACSC0_APBM                 *((volatile  uint8_t *)(0x42443A94UL))
#define bFM4_MFT2_ADCMP_ACSC0_APBM                *((volatile  uint8_t *)(0x42443A94UL))

#define bFM_MFT2_ADCMP_ACSC1_APBM                 *((volatile  uint8_t *)(0x42443B14UL))
#define bFM4_MFT2_ADCMP_ACSC1_APBM                *((volatile  uint8_t *)(0x42443B14UL))

#define bFM_MFT2_ADCMP_ACSC2_APBM                 *((volatile  uint8_t *)(0x42443B94UL))
#define bFM4_MFT2_ADCMP_ACSC2_APBM                *((volatile  uint8_t *)(0x42443B94UL))

#define bFM_MFT2_ADCMP_ACSC3_APBM                 *((volatile  uint8_t *)(0x42443C14UL))
#define bFM4_MFT2_ADCMP_ACSC3_APBM                *((volatile  uint8_t *)(0x42443C14UL))

#define bFM_MFT2_ADCMP_ACSC4_APBM                 *((volatile  uint8_t *)(0x42443C94UL))
#define bFM4_MFT2_ADCMP_ACSC4_APBM                *((volatile  uint8_t *)(0x42443C94UL))

#define bFM_MFT2_ADCMP_ACSC5_APBM                 *((volatile  uint8_t *)(0x42443D14UL))
#define bFM4_MFT2_ADCMP_ACSC5_APBM                *((volatile  uint8_t *)(0x42443D14UL))

#define bFM_MFT2_ADCMP_ACSD0_AMOD                 *((volatile  uint8_t *)(0x42443AA0UL))
#define bFM4_MFT2_ADCMP_ACSD0_AMOD                *((volatile  uint8_t *)(0x42443AA0UL))
#define bFM_MFT2_ADCMP_ACSD0_OCUS                 *((volatile  uint8_t *)(0x42443AA4UL))
#define bFM4_MFT2_ADCMP_ACSD0_OCUS                *((volatile  uint8_t *)(0x42443AA4UL))
#define bFM_MFT2_ADCMP_ACSD0_DE                   *((volatile  uint8_t *)(0x42443AB0UL))
#define bFM4_MFT2_ADCMP_ACSD0_DE                  *((volatile  uint8_t *)(0x42443AB0UL))
#define bFM_MFT2_ADCMP_ACSD0_PE                   *((volatile  uint8_t *)(0x42443AB4UL))
#define bFM4_MFT2_ADCMP_ACSD0_PE                  *((volatile  uint8_t *)(0x42443AB4UL))
#define bFM_MFT2_ADCMP_ACSD0_UE                   *((volatile  uint8_t *)(0x42443AB8UL))
#define bFM4_MFT2_ADCMP_ACSD0_UE                  *((volatile  uint8_t *)(0x42443AB8UL))
#define bFM_MFT2_ADCMP_ACSD0_ZE                   *((volatile  uint8_t *)(0x42443ABCUL))
#define bFM4_MFT2_ADCMP_ACSD0_ZE                  *((volatile  uint8_t *)(0x42443ABCUL))

#define bFM_MFT2_ADCMP_ACSD1_AMOD                 *((volatile  uint8_t *)(0x42443B20UL))
#define bFM4_MFT2_ADCMP_ACSD1_AMOD                *((volatile  uint8_t *)(0x42443B20UL))
#define bFM_MFT2_ADCMP_ACSD1_OCUS                 *((volatile  uint8_t *)(0x42443B24UL))
#define bFM4_MFT2_ADCMP_ACSD1_OCUS                *((volatile  uint8_t *)(0x42443B24UL))
#define bFM_MFT2_ADCMP_ACSD1_DE                   *((volatile  uint8_t *)(0x42443B30UL))
#define bFM4_MFT2_ADCMP_ACSD1_DE                  *((volatile  uint8_t *)(0x42443B30UL))
#define bFM_MFT2_ADCMP_ACSD1_PE                   *((volatile  uint8_t *)(0x42443B34UL))
#define bFM4_MFT2_ADCMP_ACSD1_PE                  *((volatile  uint8_t *)(0x42443B34UL))
#define bFM_MFT2_ADCMP_ACSD1_UE                   *((volatile  uint8_t *)(0x42443B38UL))
#define bFM4_MFT2_ADCMP_ACSD1_UE                  *((volatile  uint8_t *)(0x42443B38UL))
#define bFM_MFT2_ADCMP_ACSD1_ZE                   *((volatile  uint8_t *)(0x42443B3CUL))
#define bFM4_MFT2_ADCMP_ACSD1_ZE                  *((volatile  uint8_t *)(0x42443B3CUL))

#define bFM_MFT2_ADCMP_ACSD2_AMOD                 *((volatile  uint8_t *)(0x42443BA0UL))
#define bFM4_MFT2_ADCMP_ACSD2_AMOD                *((volatile  uint8_t *)(0x42443BA0UL))
#define bFM_MFT2_ADCMP_ACSD2_OCUS                 *((volatile  uint8_t *)(0x42443BA4UL))
#define bFM4_MFT2_ADCMP_ACSD2_OCUS                *((volatile  uint8_t *)(0x42443BA4UL))
#define bFM_MFT2_ADCMP_ACSD2_DE                   *((volatile  uint8_t *)(0x42443BB0UL))
#define bFM4_MFT2_ADCMP_ACSD2_DE                  *((volatile  uint8_t *)(0x42443BB0UL))
#define bFM_MFT2_ADCMP_ACSD2_PE                   *((volatile  uint8_t *)(0x42443BB4UL))
#define bFM4_MFT2_ADCMP_ACSD2_PE                  *((volatile  uint8_t *)(0x42443BB4UL))
#define bFM_MFT2_ADCMP_ACSD2_UE                   *((volatile  uint8_t *)(0x42443BB8UL))
#define bFM4_MFT2_ADCMP_ACSD2_UE                  *((volatile  uint8_t *)(0x42443BB8UL))
#define bFM_MFT2_ADCMP_ACSD2_ZE                   *((volatile  uint8_t *)(0x42443BBCUL))
#define bFM4_MFT2_ADCMP_ACSD2_ZE                  *((volatile  uint8_t *)(0x42443BBCUL))

#define bFM_MFT2_ADCMP_ACSD3_AMOD                 *((volatile  uint8_t *)(0x42443C20UL))
#define bFM4_MFT2_ADCMP_ACSD3_AMOD                *((volatile  uint8_t *)(0x42443C20UL))
#define bFM_MFT2_ADCMP_ACSD3_OCUS                 *((volatile  uint8_t *)(0x42443C24UL))
#define bFM4_MFT2_ADCMP_ACSD3_OCUS                *((volatile  uint8_t *)(0x42443C24UL))
#define bFM_MFT2_ADCMP_ACSD3_DE                   *((volatile  uint8_t *)(0x42443C30UL))
#define bFM4_MFT2_ADCMP_ACSD3_DE                  *((volatile  uint8_t *)(0x42443C30UL))
#define bFM_MFT2_ADCMP_ACSD3_PE                   *((volatile  uint8_t *)(0x42443C34UL))
#define bFM4_MFT2_ADCMP_ACSD3_PE                  *((volatile  uint8_t *)(0x42443C34UL))
#define bFM_MFT2_ADCMP_ACSD3_UE                   *((volatile  uint8_t *)(0x42443C38UL))
#define bFM4_MFT2_ADCMP_ACSD3_UE                  *((volatile  uint8_t *)(0x42443C38UL))
#define bFM_MFT2_ADCMP_ACSD3_ZE                   *((volatile  uint8_t *)(0x42443C3CUL))
#define bFM4_MFT2_ADCMP_ACSD3_ZE                  *((volatile  uint8_t *)(0x42443C3CUL))

#define bFM_MFT2_ADCMP_ACSD4_AMOD                 *((volatile  uint8_t *)(0x42443CA0UL))
#define bFM4_MFT2_ADCMP_ACSD4_AMOD                *((volatile  uint8_t *)(0x42443CA0UL))
#define bFM_MFT2_ADCMP_ACSD4_OCUS                 *((volatile  uint8_t *)(0x42443CA4UL))
#define bFM4_MFT2_ADCMP_ACSD4_OCUS                *((volatile  uint8_t *)(0x42443CA4UL))
#define bFM_MFT2_ADCMP_ACSD4_DE                   *((volatile  uint8_t *)(0x42443CB0UL))
#define bFM4_MFT2_ADCMP_ACSD4_DE                  *((volatile  uint8_t *)(0x42443CB0UL))
#define bFM_MFT2_ADCMP_ACSD4_PE                   *((volatile  uint8_t *)(0x42443CB4UL))
#define bFM4_MFT2_ADCMP_ACSD4_PE                  *((volatile  uint8_t *)(0x42443CB4UL))
#define bFM_MFT2_ADCMP_ACSD4_UE                   *((volatile  uint8_t *)(0x42443CB8UL))
#define bFM4_MFT2_ADCMP_ACSD4_UE                  *((volatile  uint8_t *)(0x42443CB8UL))
#define bFM_MFT2_ADCMP_ACSD4_ZE                   *((volatile  uint8_t *)(0x42443CBCUL))
#define bFM4_MFT2_ADCMP_ACSD4_ZE                  *((volatile  uint8_t *)(0x42443CBCUL))

#define bFM_MFT2_ADCMP_ACSD5_AMOD                 *((volatile  uint8_t *)(0x42443D20UL))
#define bFM4_MFT2_ADCMP_ACSD5_AMOD                *((volatile  uint8_t *)(0x42443D20UL))
#define bFM_MFT2_ADCMP_ACSD5_OCUS                 *((volatile  uint8_t *)(0x42443D24UL))
#define bFM4_MFT2_ADCMP_ACSD5_OCUS                *((volatile  uint8_t *)(0x42443D24UL))
#define bFM_MFT2_ADCMP_ACSD5_DE                   *((volatile  uint8_t *)(0x42443D30UL))
#define bFM4_MFT2_ADCMP_ACSD5_DE                  *((volatile  uint8_t *)(0x42443D30UL))
#define bFM_MFT2_ADCMP_ACSD5_PE                   *((volatile  uint8_t *)(0x42443D34UL))
#define bFM4_MFT2_ADCMP_ACSD5_PE                  *((volatile  uint8_t *)(0x42443D34UL))
#define bFM_MFT2_ADCMP_ACSD5_UE                   *((volatile  uint8_t *)(0x42443D38UL))
#define bFM4_MFT2_ADCMP_ACSD5_UE                  *((volatile  uint8_t *)(0x42443D38UL))
#define bFM_MFT2_ADCMP_ACSD5_ZE                   *((volatile  uint8_t *)(0x42443D3CUL))
#define bFM4_MFT2_ADCMP_ACSD5_ZE                  *((volatile  uint8_t *)(0x42443D3CUL))

#define bFM_MFT2_FRT_TCAL_STOP00                  *((volatile  uint32_t*)(0x42442C80UL))
#define bFM4_MFT2_FRT_TCAL_STOP00                 *((volatile  uint32_t*)(0x42442C80UL))
#define bFM_MFT2_FRT_TCAL_STOP01                  *((volatile  uint32_t*)(0x42442C84UL))
#define bFM4_MFT2_FRT_TCAL_STOP01                 *((volatile  uint32_t*)(0x42442C84UL))
#define bFM_MFT2_FRT_TCAL_STOP02                  *((volatile  uint32_t*)(0x42442C88UL))
#define bFM4_MFT2_FRT_TCAL_STOP02                 *((volatile  uint32_t*)(0x42442C88UL))
#define bFM_MFT2_FRT_TCAL_STOP10                  *((volatile  uint32_t*)(0x42442C8CUL))
#define bFM4_MFT2_FRT_TCAL_STOP10                 *((volatile  uint32_t*)(0x42442C8CUL))
#define bFM_MFT2_FRT_TCAL_STOP11                  *((volatile  uint32_t*)(0x42442C90UL))
#define bFM4_MFT2_FRT_TCAL_STOP11                 *((volatile  uint32_t*)(0x42442C90UL))
#define bFM_MFT2_FRT_TCAL_STOP12                  *((volatile  uint32_t*)(0x42442C94UL))
#define bFM4_MFT2_FRT_TCAL_STOP12                 *((volatile  uint32_t*)(0x42442C94UL))
#define bFM_MFT2_FRT_TCAL_STOP20                  *((volatile  uint32_t*)(0x42442C98UL))
#define bFM4_MFT2_FRT_TCAL_STOP20                 *((volatile  uint32_t*)(0x42442C98UL))
#define bFM_MFT2_FRT_TCAL_STOP21                  *((volatile  uint32_t*)(0x42442C9CUL))
#define bFM4_MFT2_FRT_TCAL_STOP21                 *((volatile  uint32_t*)(0x42442C9CUL))
#define bFM_MFT2_FRT_TCAL_STOP22                  *((volatile  uint32_t*)(0x42442CA0UL))
#define bFM4_MFT2_FRT_TCAL_STOP22                 *((volatile  uint32_t*)(0x42442CA0UL))
#define bFM_MFT2_FRT_TCAL_SCLR00                  *((volatile  uint32_t*)(0x42442CC0UL))
#define bFM4_MFT2_FRT_TCAL_SCLR00                 *((volatile  uint32_t*)(0x42442CC0UL))
#define bFM_MFT2_FRT_TCAL_SCLR01                  *((volatile  uint32_t*)(0x42442CC4UL))
#define bFM4_MFT2_FRT_TCAL_SCLR01                 *((volatile  uint32_t*)(0x42442CC4UL))
#define bFM_MFT2_FRT_TCAL_SCLR02                  *((volatile  uint32_t*)(0x42442CC8UL))
#define bFM4_MFT2_FRT_TCAL_SCLR02                 *((volatile  uint32_t*)(0x42442CC8UL))
#define bFM_MFT2_FRT_TCAL_SCLR10                  *((volatile  uint32_t*)(0x42442CCCUL))
#define bFM4_MFT2_FRT_TCAL_SCLR10                 *((volatile  uint32_t*)(0x42442CCCUL))
#define bFM_MFT2_FRT_TCAL_SCLR11                  *((volatile  uint32_t*)(0x42442CD0UL))
#define bFM4_MFT2_FRT_TCAL_SCLR11                 *((volatile  uint32_t*)(0x42442CD0UL))
#define bFM_MFT2_FRT_TCAL_SCLR12                  *((volatile  uint32_t*)(0x42442CD4UL))
#define bFM4_MFT2_FRT_TCAL_SCLR12                 *((volatile  uint32_t*)(0x42442CD4UL))
#define bFM_MFT2_FRT_TCAL_SCLR20                  *((volatile  uint32_t*)(0x42442CD8UL))
#define bFM4_MFT2_FRT_TCAL_SCLR20                 *((volatile  uint32_t*)(0x42442CD8UL))
#define bFM_MFT2_FRT_TCAL_SCLR21                  *((volatile  uint32_t*)(0x42442CDCUL))
#define bFM4_MFT2_FRT_TCAL_SCLR21                 *((volatile  uint32_t*)(0x42442CDCUL))
#define bFM_MFT2_FRT_TCAL_SCLR22                  *((volatile  uint32_t*)(0x42442CE0UL))
#define bFM4_MFT2_FRT_TCAL_SCLR22                 *((volatile  uint32_t*)(0x42442CE0UL))

#define bFM_MFT2_FRT_TCSA0_SCLR                   *((volatile  uint8_t *)(0x42442910UL))
#define bFM4_MFT2_FRT_TCSA0_SCLR                  *((volatile  uint8_t *)(0x42442910UL))
#define bFM_MFT2_FRT_TCSA0_MODE                   *((volatile  uint8_t *)(0x42442914UL))
#define bFM4_MFT2_FRT_TCSA0_MODE                  *((volatile  uint8_t *)(0x42442914UL))
#define bFM_MFT2_FRT_TCSA0_STOP                   *((volatile  uint8_t *)(0x42442918UL))
#define bFM4_MFT2_FRT_TCSA0_STOP                  *((volatile  uint8_t *)(0x42442918UL))
#define bFM_MFT2_FRT_TCSA0_BFE                    *((volatile  uint8_t *)(0x4244291CUL))
#define bFM4_MFT2_FRT_TCSA0_BFE                   *((volatile  uint8_t *)(0x4244291CUL))
#define bFM_MFT2_FRT_TCSA0_ICRE                   *((volatile  uint8_t *)(0x42442920UL))
#define bFM4_MFT2_FRT_TCSA0_ICRE                  *((volatile  uint8_t *)(0x42442920UL))
#define bFM_MFT2_FRT_TCSA0_ICLR                   *((volatile  uint8_t *)(0x42442924UL))
#define bFM4_MFT2_FRT_TCSA0_ICLR                  *((volatile  uint8_t *)(0x42442924UL))
#define bFM_MFT2_FRT_TCSA0_IRQZE                  *((volatile  uint8_t *)(0x42442934UL))
#define bFM4_MFT2_FRT_TCSA0_IRQZE                 *((volatile  uint8_t *)(0x42442934UL))
#define bFM_MFT2_FRT_TCSA0_IRQZF                  *((volatile  uint8_t *)(0x42442938UL))
#define bFM4_MFT2_FRT_TCSA0_IRQZF                 *((volatile  uint8_t *)(0x42442938UL))
#define bFM_MFT2_FRT_TCSA0_ECKE                   *((volatile  uint8_t *)(0x4244293CUL))
#define bFM4_MFT2_FRT_TCSA0_ECKE                  *((volatile  uint8_t *)(0x4244293CUL))

#define bFM_MFT2_FRT_TCSA1_SCLR                   *((volatile  uint8_t *)(0x42442A90UL))
#define bFM4_MFT2_FRT_TCSA1_SCLR                  *((volatile  uint8_t *)(0x42442A90UL))
#define bFM_MFT2_FRT_TCSA1_MODE                   *((volatile  uint8_t *)(0x42442A94UL))
#define bFM4_MFT2_FRT_TCSA1_MODE                  *((volatile  uint8_t *)(0x42442A94UL))
#define bFM_MFT2_FRT_TCSA1_STOP                   *((volatile  uint8_t *)(0x42442A98UL))
#define bFM4_MFT2_FRT_TCSA1_STOP                  *((volatile  uint8_t *)(0x42442A98UL))
#define bFM_MFT2_FRT_TCSA1_BFE                    *((volatile  uint8_t *)(0x42442A9CUL))
#define bFM4_MFT2_FRT_TCSA1_BFE                   *((volatile  uint8_t *)(0x42442A9CUL))
#define bFM_MFT2_FRT_TCSA1_ICRE                   *((volatile  uint8_t *)(0x42442AA0UL))
#define bFM4_MFT2_FRT_TCSA1_ICRE                  *((volatile  uint8_t *)(0x42442AA0UL))
#define bFM_MFT2_FRT_TCSA1_ICLR                   *((volatile  uint8_t *)(0x42442AA4UL))
#define bFM4_MFT2_FRT_TCSA1_ICLR                  *((volatile  uint8_t *)(0x42442AA4UL))
#define bFM_MFT2_FRT_TCSA1_IRQZE                  *((volatile  uint8_t *)(0x42442AB4UL))
#define bFM4_MFT2_FRT_TCSA1_IRQZE                 *((volatile  uint8_t *)(0x42442AB4UL))
#define bFM_MFT2_FRT_TCSA1_IRQZF                  *((volatile  uint8_t *)(0x42442AB8UL))
#define bFM4_MFT2_FRT_TCSA1_IRQZF                 *((volatile  uint8_t *)(0x42442AB8UL))
#define bFM_MFT2_FRT_TCSA1_ECKE                   *((volatile  uint8_t *)(0x42442ABCUL))
#define bFM4_MFT2_FRT_TCSA1_ECKE                  *((volatile  uint8_t *)(0x42442ABCUL))

#define bFM_MFT2_FRT_TCSA2_SCLR                   *((volatile  uint8_t *)(0x42442C10UL))
#define bFM4_MFT2_FRT_TCSA2_SCLR                  *((volatile  uint8_t *)(0x42442C10UL))
#define bFM_MFT2_FRT_TCSA2_MODE                   *((volatile  uint8_t *)(0x42442C14UL))
#define bFM4_MFT2_FRT_TCSA2_MODE                  *((volatile  uint8_t *)(0x42442C14UL))
#define bFM_MFT2_FRT_TCSA2_STOP                   *((volatile  uint8_t *)(0x42442C18UL))
#define bFM4_MFT2_FRT_TCSA2_STOP                  *((volatile  uint8_t *)(0x42442C18UL))
#define bFM_MFT2_FRT_TCSA2_BFE                    *((volatile  uint8_t *)(0x42442C1CUL))
#define bFM4_MFT2_FRT_TCSA2_BFE                   *((volatile  uint8_t *)(0x42442C1CUL))
#define bFM_MFT2_FRT_TCSA2_ICRE                   *((volatile  uint8_t *)(0x42442C20UL))
#define bFM4_MFT2_FRT_TCSA2_ICRE                  *((volatile  uint8_t *)(0x42442C20UL))
#define bFM_MFT2_FRT_TCSA2_ICLR                   *((volatile  uint8_t *)(0x42442C24UL))
#define bFM4_MFT2_FRT_TCSA2_ICLR                  *((volatile  uint8_t *)(0x42442C24UL))
#define bFM_MFT2_FRT_TCSA2_IRQZE                  *((volatile  uint8_t *)(0x42442C34UL))
#define bFM4_MFT2_FRT_TCSA2_IRQZE                 *((volatile  uint8_t *)(0x42442C34UL))
#define bFM_MFT2_FRT_TCSA2_IRQZF                  *((volatile  uint8_t *)(0x42442C38UL))
#define bFM4_MFT2_FRT_TCSA2_IRQZF                 *((volatile  uint8_t *)(0x42442C38UL))
#define bFM_MFT2_FRT_TCSA2_ECKE                   *((volatile  uint8_t *)(0x42442C3CUL))
#define bFM4_MFT2_FRT_TCSA2_ECKE                  *((volatile  uint8_t *)(0x42442C3CUL))

#define bFM_MFT2_FRT_TCSD_OFMD1                   *((volatile  uint8_t *)(0x42443D80UL))
#define bFM4_MFT2_FRT_TCSD_OFMD1                  *((volatile  uint8_t *)(0x42443D80UL))
#define bFM_MFT2_FRT_TCSD_OFMD2                   *((volatile  uint8_t *)(0x42443D84UL))
#define bFM4_MFT2_FRT_TCSD_OFMD2                  *((volatile  uint8_t *)(0x42443D84UL))

#define bFM_MFT2_ICU_ICSA10_ICE0                  *((volatile  uint8_t *)(0x42443090UL))
#define bFM4_MFT2_ICU_ICSA10_ICE0                 *((volatile  uint8_t *)(0x42443090UL))
#define bFM_MFT2_ICU_ICSA10_ICE1                  *((volatile  uint8_t *)(0x42443094UL))
#define bFM4_MFT2_ICU_ICSA10_ICE1                 *((volatile  uint8_t *)(0x42443094UL))
#define bFM_MFT2_ICU_ICSA10_ICP0                  *((volatile  uint8_t *)(0x42443098UL))
#define bFM4_MFT2_ICU_ICSA10_ICP0                 *((volatile  uint8_t *)(0x42443098UL))
#define bFM_MFT2_ICU_ICSA10_ICP1                  *((volatile  uint8_t *)(0x4244309CUL))
#define bFM4_MFT2_ICU_ICSA10_ICP1                 *((volatile  uint8_t *)(0x4244309CUL))

#define bFM_MFT2_ICU_ICSA32_ICE2                  *((volatile  uint8_t *)(0x42443110UL))
#define bFM4_MFT2_ICU_ICSA32_ICE2                 *((volatile  uint8_t *)(0x42443110UL))
#define bFM_MFT2_ICU_ICSA32_ICE3                  *((volatile  uint8_t *)(0x42443114UL))
#define bFM4_MFT2_ICU_ICSA32_ICE3                 *((volatile  uint8_t *)(0x42443114UL))
#define bFM_MFT2_ICU_ICSA32_ICP2                  *((volatile  uint8_t *)(0x42443118UL))
#define bFM4_MFT2_ICU_ICSA32_ICP2                 *((volatile  uint8_t *)(0x42443118UL))
#define bFM_MFT2_ICU_ICSA32_ICP3                  *((volatile  uint8_t *)(0x4244311CUL))
#define bFM4_MFT2_ICU_ICSA32_ICP3                 *((volatile  uint8_t *)(0x4244311CUL))

#define bFM_MFT2_ICU_ICSB10_IEI0                  *((volatile  uint8_t *)(0x424430A0UL))
#define bFM4_MFT2_ICU_ICSB10_IEI0                 *((volatile  uint8_t *)(0x424430A0UL))
#define bFM_MFT2_ICU_ICSB10_IEI1                  *((volatile  uint8_t *)(0x424430A4UL))
#define bFM4_MFT2_ICU_ICSB10_IEI1                 *((volatile  uint8_t *)(0x424430A4UL))

#define bFM_MFT2_ICU_ICSB32_IEI2                  *((volatile  uint8_t *)(0x42443120UL))
#define bFM4_MFT2_ICU_ICSB32_IEI2                 *((volatile  uint8_t *)(0x42443120UL))
#define bFM_MFT2_ICU_ICSB32_IEI3                  *((volatile  uint8_t *)(0x42443124UL))
#define bFM4_MFT2_ICU_ICSB32_IEI3                 *((volatile  uint8_t *)(0x42443124UL))

#define bFM_MFT2_OCU_OCSA10_CST0                  *((volatile  uint8_t *)(0x42442300UL))
#define bFM4_MFT2_OCU_OCSA10_CST0                 *((volatile  uint8_t *)(0x42442300UL))
#define bFM_MFT2_OCU_OCSA10_CST1                  *((volatile  uint8_t *)(0x42442304UL))
#define bFM4_MFT2_OCU_OCSA10_CST1                 *((volatile  uint8_t *)(0x42442304UL))
#define bFM_MFT2_OCU_OCSA10_IOE0                  *((volatile  uint8_t *)(0x42442310UL))
#define bFM4_MFT2_OCU_OCSA10_IOE0                 *((volatile  uint8_t *)(0x42442310UL))
#define bFM_MFT2_OCU_OCSA10_IOE1                  *((volatile  uint8_t *)(0x42442314UL))
#define bFM4_MFT2_OCU_OCSA10_IOE1                 *((volatile  uint8_t *)(0x42442314UL))
#define bFM_MFT2_OCU_OCSA10_IOP0                  *((volatile  uint8_t *)(0x42442318UL))
#define bFM4_MFT2_OCU_OCSA10_IOP0                 *((volatile  uint8_t *)(0x42442318UL))
#define bFM_MFT2_OCU_OCSA10_IOP1                  *((volatile  uint8_t *)(0x4244231CUL))
#define bFM4_MFT2_OCU_OCSA10_IOP1                 *((volatile  uint8_t *)(0x4244231CUL))

#define bFM_MFT2_OCU_OCSA32_CST2                  *((volatile  uint8_t *)(0x42442380UL))
#define bFM4_MFT2_OCU_OCSA32_CST2                 *((volatile  uint8_t *)(0x42442380UL))
#define bFM_MFT2_OCU_OCSA32_CST3                  *((volatile  uint8_t *)(0x42442384UL))
#define bFM4_MFT2_OCU_OCSA32_CST3                 *((volatile  uint8_t *)(0x42442384UL))
#define bFM_MFT2_OCU_OCSA32_IOE2                  *((volatile  uint8_t *)(0x42442390UL))
#define bFM4_MFT2_OCU_OCSA32_IOE2                 *((volatile  uint8_t *)(0x42442390UL))
#define bFM_MFT2_OCU_OCSA32_IOE3                  *((volatile  uint8_t *)(0x42442394UL))
#define bFM4_MFT2_OCU_OCSA32_IOE3                 *((volatile  uint8_t *)(0x42442394UL))
#define bFM_MFT2_OCU_OCSA32_IOP2                  *((volatile  uint8_t *)(0x42442398UL))
#define bFM4_MFT2_OCU_OCSA32_IOP2                 *((volatile  uint8_t *)(0x42442398UL))
#define bFM_MFT2_OCU_OCSA32_IOP3                  *((volatile  uint8_t *)(0x4244239CUL))
#define bFM4_MFT2_OCU_OCSA32_IOP3                 *((volatile  uint8_t *)(0x4244239CUL))

#define bFM_MFT2_OCU_OCSA54_CST4                  *((volatile  uint8_t *)(0x42442400UL))
#define bFM4_MFT2_OCU_OCSA54_CST4                 *((volatile  uint8_t *)(0x42442400UL))
#define bFM_MFT2_OCU_OCSA54_CST5                  *((volatile  uint8_t *)(0x42442404UL))
#define bFM4_MFT2_OCU_OCSA54_CST5                 *((volatile  uint8_t *)(0x42442404UL))
#define bFM_MFT2_OCU_OCSA54_IOE4                  *((volatile  uint8_t *)(0x42442410UL))
#define bFM4_MFT2_OCU_OCSA54_IOE4                 *((volatile  uint8_t *)(0x42442410UL))
#define bFM_MFT2_OCU_OCSA54_IOE5                  *((volatile  uint8_t *)(0x42442414UL))
#define bFM4_MFT2_OCU_OCSA54_IOE5                 *((volatile  uint8_t *)(0x42442414UL))
#define bFM_MFT2_OCU_OCSA54_IOP4                  *((volatile  uint8_t *)(0x42442418UL))
#define bFM4_MFT2_OCU_OCSA54_IOP4                 *((volatile  uint8_t *)(0x42442418UL))
#define bFM_MFT2_OCU_OCSA54_IOP5                  *((volatile  uint8_t *)(0x4244241CUL))
#define bFM4_MFT2_OCU_OCSA54_IOP5                 *((volatile  uint8_t *)(0x4244241CUL))

#define bFM_MFT2_OCU_OCSB10_OTD0                  *((volatile  uint8_t *)(0x42442320UL))
#define bFM4_MFT2_OCU_OCSB10_OTD0                 *((volatile  uint8_t *)(0x42442320UL))
#define bFM_MFT2_OCU_OCSB10_OTD1                  *((volatile  uint8_t *)(0x42442324UL))
#define bFM4_MFT2_OCU_OCSB10_OTD1                 *((volatile  uint8_t *)(0x42442324UL))
#define bFM_MFT2_OCU_OCSB10_CMOD                  *((volatile  uint8_t *)(0x42442330UL))
#define bFM4_MFT2_OCU_OCSB10_CMOD                 *((volatile  uint8_t *)(0x42442330UL))
#define bFM_MFT2_OCU_OCSB10_FM4                   *((volatile  uint8_t *)(0x4244233CUL))
#define bFM4_MFT2_OCU_OCSB10_FM4                  *((volatile  uint8_t *)(0x4244233CUL))

#define bFM_MFT2_OCU_OCSB32_OTD2                  *((volatile  uint8_t *)(0x424423A0UL))
#define bFM4_MFT2_OCU_OCSB32_OTD2                 *((volatile  uint8_t *)(0x424423A0UL))
#define bFM_MFT2_OCU_OCSB32_OTD3                  *((volatile  uint8_t *)(0x424423A4UL))
#define bFM4_MFT2_OCU_OCSB32_OTD3                 *((volatile  uint8_t *)(0x424423A4UL))
#define bFM_MFT2_OCU_OCSB32_CMOD                  *((volatile  uint8_t *)(0x424423B0UL))
#define bFM4_MFT2_OCU_OCSB32_CMOD                 *((volatile  uint8_t *)(0x424423B0UL))
#define bFM_MFT2_OCU_OCSB32_FM4                   *((volatile  uint8_t *)(0x424423BCUL))
#define bFM4_MFT2_OCU_OCSB32_FM4                  *((volatile  uint8_t *)(0x424423BCUL))

#define bFM_MFT2_OCU_OCSB54_OTD4                  *((volatile  uint8_t *)(0x42442420UL))
#define bFM4_MFT2_OCU_OCSB54_OTD4                 *((volatile  uint8_t *)(0x42442420UL))
#define bFM_MFT2_OCU_OCSB54_OTD5                  *((volatile  uint8_t *)(0x42442424UL))
#define bFM4_MFT2_OCU_OCSB54_OTD5                 *((volatile  uint8_t *)(0x42442424UL))
#define bFM_MFT2_OCU_OCSB54_CMOD                  *((volatile  uint8_t *)(0x42442430UL))
#define bFM4_MFT2_OCU_OCSB54_CMOD                 *((volatile  uint8_t *)(0x42442430UL))
#define bFM_MFT2_OCU_OCSB54_FM4                   *((volatile  uint8_t *)(0x4244243CUL))
#define bFM4_MFT2_OCU_OCSB54_FM4                  *((volatile  uint8_t *)(0x4244243CUL))

#define bFM_MFT2_OCU_OCSC_MOD0                    *((volatile  uint8_t *)(0x424424A0UL))
#define bFM4_MFT2_OCU_OCSC_MOD0                   *((volatile  uint8_t *)(0x424424A0UL))
#define bFM_MFT2_OCU_OCSC_MOD1                    *((volatile  uint8_t *)(0x424424A4UL))
#define bFM4_MFT2_OCU_OCSC_MOD1                   *((volatile  uint8_t *)(0x424424A4UL))
#define bFM_MFT2_OCU_OCSC_MOD2                    *((volatile  uint8_t *)(0x424424A8UL))
#define bFM4_MFT2_OCU_OCSC_MOD2                   *((volatile  uint8_t *)(0x424424A8UL))
#define bFM_MFT2_OCU_OCSC_MOD3                    *((volatile  uint8_t *)(0x424424ACUL))
#define bFM4_MFT2_OCU_OCSC_MOD3                   *((volatile  uint8_t *)(0x424424ACUL))
#define bFM_MFT2_OCU_OCSC_MOD4                    *((volatile  uint8_t *)(0x424424B0UL))
#define bFM4_MFT2_OCU_OCSC_MOD4                   *((volatile  uint8_t *)(0x424424B0UL))
#define bFM_MFT2_OCU_OCSC_MOD5                    *((volatile  uint8_t *)(0x424424B4UL))
#define bFM4_MFT2_OCU_OCSC_MOD5                   *((volatile  uint8_t *)(0x424424B4UL))

#define bFM_MFT2_OCU_OCSD10_OPBM0                 *((volatile  uint8_t *)(0x42442360UL))
#define bFM4_MFT2_OCU_OCSD10_OPBM0                *((volatile  uint8_t *)(0x42442360UL))
#define bFM_MFT2_OCU_OCSD10_OPBM1                 *((volatile  uint8_t *)(0x42442364UL))
#define bFM4_MFT2_OCU_OCSD10_OPBM1                *((volatile  uint8_t *)(0x42442364UL))
#define bFM_MFT2_OCU_OCSD10_OEBM0                 *((volatile  uint8_t *)(0x42442368UL))
#define bFM4_MFT2_OCU_OCSD10_OEBM0                *((volatile  uint8_t *)(0x42442368UL))
#define bFM_MFT2_OCU_OCSD10_OEBM1                 *((volatile  uint8_t *)(0x4244236CUL))
#define bFM4_MFT2_OCU_OCSD10_OEBM1                *((volatile  uint8_t *)(0x4244236CUL))
#define bFM_MFT2_OCU_OCSD10_OFEX0                 *((volatile  uint8_t *)(0x42442370UL))
#define bFM4_MFT2_OCU_OCSD10_OFEX0                *((volatile  uint8_t *)(0x42442370UL))
#define bFM_MFT2_OCU_OCSD10_OFEX1                 *((volatile  uint8_t *)(0x42442374UL))
#define bFM4_MFT2_OCU_OCSD10_OFEX1                *((volatile  uint8_t *)(0x42442374UL))

#define bFM_MFT2_OCU_OCSD32_OPBM2                 *((volatile  uint8_t *)(0x424423E0UL))
#define bFM4_MFT2_OCU_OCSD32_OPBM2                *((volatile  uint8_t *)(0x424423E0UL))
#define bFM_MFT2_OCU_OCSD32_OPBM3                 *((volatile  uint8_t *)(0x424423E4UL))
#define bFM4_MFT2_OCU_OCSD32_OPBM3                *((volatile  uint8_t *)(0x424423E4UL))
#define bFM_MFT2_OCU_OCSD32_OEBM2                 *((volatile  uint8_t *)(0x424423E8UL))
#define bFM4_MFT2_OCU_OCSD32_OEBM2                *((volatile  uint8_t *)(0x424423E8UL))
#define bFM_MFT2_OCU_OCSD32_OEBM3                 *((volatile  uint8_t *)(0x424423ECUL))
#define bFM4_MFT2_OCU_OCSD32_OEBM3                *((volatile  uint8_t *)(0x424423ECUL))
#define bFM_MFT2_OCU_OCSD32_OFEX2                 *((volatile  uint8_t *)(0x424423F0UL))
#define bFM4_MFT2_OCU_OCSD32_OFEX2                *((volatile  uint8_t *)(0x424423F0UL))
#define bFM_MFT2_OCU_OCSD32_OFEX3                 *((volatile  uint8_t *)(0x424423F4UL))
#define bFM4_MFT2_OCU_OCSD32_OFEX3                *((volatile  uint8_t *)(0x424423F4UL))

#define bFM_MFT2_OCU_OCSD54_OPBM4                 *((volatile  uint8_t *)(0x42442460UL))
#define bFM4_MFT2_OCU_OCSD54_OPBM4                *((volatile  uint8_t *)(0x42442460UL))
#define bFM_MFT2_OCU_OCSD54_OPBM5                 *((volatile  uint8_t *)(0x42442464UL))
#define bFM4_MFT2_OCU_OCSD54_OPBM5                *((volatile  uint8_t *)(0x42442464UL))
#define bFM_MFT2_OCU_OCSD54_OEBM4                 *((volatile  uint8_t *)(0x42442468UL))
#define bFM4_MFT2_OCU_OCSD54_OEBM4                *((volatile  uint8_t *)(0x42442468UL))
#define bFM_MFT2_OCU_OCSD54_OEBM5                 *((volatile  uint8_t *)(0x4244246CUL))
#define bFM4_MFT2_OCU_OCSD54_OEBM5                *((volatile  uint8_t *)(0x4244246CUL))
#define bFM_MFT2_OCU_OCSD54_OFEX4                 *((volatile  uint8_t *)(0x42442470UL))
#define bFM4_MFT2_OCU_OCSD54_OFEX4                *((volatile  uint8_t *)(0x42442470UL))
#define bFM_MFT2_OCU_OCSD54_OFEX5                 *((volatile  uint8_t *)(0x42442474UL))
#define bFM4_MFT2_OCU_OCSD54_OFEX5                *((volatile  uint8_t *)(0x42442474UL))

#define bFM_MFT2_WFG_NZCL_DTIEA                   *((volatile  uint16_t*)(0x42443680UL))
#define bFM4_MFT2_WFG_NZCL_DTIEA                  *((volatile  uint16_t*)(0x42443680UL))
#define bFM_MFT2_WFG_NZCL_SDTI                    *((volatile  uint16_t*)(0x42443690UL))
#define bFM4_MFT2_WFG_NZCL_SDTI                   *((volatile  uint16_t*)(0x42443690UL))
#define bFM_MFT2_WFG_NZCL_DTIEB                   *((volatile  uint16_t*)(0x42443694UL))
#define bFM4_MFT2_WFG_NZCL_DTIEB                  *((volatile  uint16_t*)(0x42443694UL))
#define bFM_MFT2_WFG_NZCL_DHOLD                   *((volatile  uint16_t*)(0x4244369CUL))
#define bFM4_MFT2_WFG_NZCL_DHOLD                  *((volatile  uint16_t*)(0x4244369CUL))
#define bFM_MFT2_WFG_NZCL_DIMA                    *((volatile  uint16_t*)(0x424436A0UL))
#define bFM4_MFT2_WFG_NZCL_DIMA                   *((volatile  uint16_t*)(0x424436A0UL))
#define bFM_MFT2_WFG_NZCL_DIMB                    *((volatile  uint16_t*)(0x424436A4UL))
#define bFM4_MFT2_WFG_NZCL_DIMB                   *((volatile  uint16_t*)(0x424436A4UL))
#define bFM_MFT2_WFG_NZCL_WIM10                   *((volatile  uint16_t*)(0x424436B0UL))
#define bFM4_MFT2_WFG_NZCL_WIM10                  *((volatile  uint16_t*)(0x424436B0UL))
#define bFM_MFT2_WFG_NZCL_WIM32                   *((volatile  uint16_t*)(0x424436B4UL))
#define bFM4_MFT2_WFG_NZCL_WIM32                  *((volatile  uint16_t*)(0x424436B4UL))
#define bFM_MFT2_WFG_NZCL_WIM54                   *((volatile  uint16_t*)(0x424436B8UL))
#define bFM4_MFT2_WFG_NZCL_WIM54                  *((volatile  uint16_t*)(0x424436B8UL))

#define bFM_MFT2_WFG_WFIR_DTIFA                   *((volatile  uint16_t*)(0x42443600UL))
#define bFM4_MFT2_WFG_WFIR_DTIFA                  *((volatile  uint16_t*)(0x42443600UL))
#define bFM_MFT2_WFG_WFIR_DTICA                   *((volatile  uint16_t*)(0x42443604UL))
#define bFM4_MFT2_WFG_WFIR_DTICA                  *((volatile  uint16_t*)(0x42443604UL))
#define bFM_MFT2_WFG_WFIR_DTIFB                   *((volatile  uint16_t*)(0x42443608UL))
#define bFM4_MFT2_WFG_WFIR_DTIFB                  *((volatile  uint16_t*)(0x42443608UL))
#define bFM_MFT2_WFG_WFIR_DTICB                   *((volatile  uint16_t*)(0x4244360CUL))
#define bFM4_MFT2_WFG_WFIR_DTICB                  *((volatile  uint16_t*)(0x4244360CUL))
#define bFM_MFT2_WFG_WFIR_TMIF10                  *((volatile  uint16_t*)(0x42443610UL))
#define bFM4_MFT2_WFG_WFIR_TMIF10                 *((volatile  uint16_t*)(0x42443610UL))
#define bFM_MFT2_WFG_WFIR_TMIC10                  *((volatile  uint16_t*)(0x42443614UL))
#define bFM4_MFT2_WFG_WFIR_TMIC10                 *((volatile  uint16_t*)(0x42443614UL))
#define bFM_MFT2_WFG_WFIR_TMIE10                  *((volatile  uint16_t*)(0x42443618UL))
#define bFM4_MFT2_WFG_WFIR_TMIE10                 *((volatile  uint16_t*)(0x42443618UL))
#define bFM_MFT2_WFG_WFIR_TMIS10                  *((volatile  uint16_t*)(0x4244361CUL))
#define bFM4_MFT2_WFG_WFIR_TMIS10                 *((volatile  uint16_t*)(0x4244361CUL))
#define bFM_MFT2_WFG_WFIR_TMIF32                  *((volatile  uint16_t*)(0x42443620UL))
#define bFM4_MFT2_WFG_WFIR_TMIF32                 *((volatile  uint16_t*)(0x42443620UL))
#define bFM_MFT2_WFG_WFIR_TMIC32                  *((volatile  uint16_t*)(0x42443624UL))
#define bFM4_MFT2_WFG_WFIR_TMIC32                 *((volatile  uint16_t*)(0x42443624UL))
#define bFM_MFT2_WFG_WFIR_TMIE32                  *((volatile  uint16_t*)(0x42443628UL))
#define bFM4_MFT2_WFG_WFIR_TMIE32                 *((volatile  uint16_t*)(0x42443628UL))
#define bFM_MFT2_WFG_WFIR_TMIS32                  *((volatile  uint16_t*)(0x4244362CUL))
#define bFM4_MFT2_WFG_WFIR_TMIS32                 *((volatile  uint16_t*)(0x4244362CUL))
#define bFM_MFT2_WFG_WFIR_TMIF54                  *((volatile  uint16_t*)(0x42443630UL))
#define bFM4_MFT2_WFG_WFIR_TMIF54                 *((volatile  uint16_t*)(0x42443630UL))
#define bFM_MFT2_WFG_WFIR_TMIC54                  *((volatile  uint16_t*)(0x42443634UL))
#define bFM4_MFT2_WFG_WFIR_TMIC54                 *((volatile  uint16_t*)(0x42443634UL))
#define bFM_MFT2_WFG_WFIR_TMIE54                  *((volatile  uint16_t*)(0x42443638UL))
#define bFM4_MFT2_WFG_WFIR_TMIE54                 *((volatile  uint16_t*)(0x42443638UL))
#define bFM_MFT2_WFG_WFIR_TMIS54                  *((volatile  uint16_t*)(0x4244363CUL))
#define bFM4_MFT2_WFG_WFIR_TMIS54                 *((volatile  uint16_t*)(0x4244363CUL))


/*******************************************************************************
* PCRC Registers PCRC
*   Bitband Section
*******************************************************************************/
#define bFM_PCRC_PCRC_CFG_CIRQCLR                 *((volatile  uint8_t *)(0x43000180UL))
#define bFM4_PCRC_PCRC_CFG_CIRQCLR                *((volatile  uint8_t *)(0x43000180UL))
#define bFM_PCRC_PCRC_CFG_CIRQ                    *((volatile  uint8_t *)(0x430001E0UL))
#define bFM4_PCRC_PCRC_CFG_CIRQ                   *((volatile  uint8_t *)(0x430001E0UL))
#define bFM_PCRC_PCRC_CFG_CIEN                    *((volatile  uint8_t *)(0x430001E4UL))
#define bFM4_PCRC_PCRC_CFG_CIEN                   *((volatile  uint8_t *)(0x430001E4UL))
#define bFM_PCRC_PCRC_CFG_CDEN                    *((volatile  uint8_t *)(0x430001E8UL))
#define bFM4_PCRC_PCRC_CFG_CDEN                   *((volatile  uint8_t *)(0x430001E8UL))
#define bFM_PCRC_PCRC_CFG_LOCK                    *((volatile  uint8_t *)(0x430001F0UL))
#define bFM4_PCRC_PCRC_CFG_LOCK                   *((volatile  uint8_t *)(0x430001F0UL))


/*******************************************************************************
* QPRC Registers QPRC0
*   Bitband Section
*******************************************************************************/
#define bFM_QPRC0_QCR_PSTP                        *((volatile  uint8_t *)(0x424C0310UL))
#define bFM4_QPRC0_QCR_PSTP                       *((volatile  uint8_t *)(0x424C0310UL))
#define bFM_QPRC0_QCR_CGSC                        *((volatile  uint8_t *)(0x424C0314UL))
#define bFM4_QPRC0_QCR_CGSC                       *((volatile  uint8_t *)(0x424C0314UL))
#define bFM_QPRC0_QCR_RSEL                        *((volatile  uint8_t *)(0x424C0318UL))
#define bFM4_QPRC0_QCR_RSEL                       *((volatile  uint8_t *)(0x424C0318UL))
#define bFM_QPRC0_QCR_SWAP                        *((volatile  uint8_t *)(0x424C031CUL))
#define bFM4_QPRC0_QCR_SWAP                       *((volatile  uint8_t *)(0x424C031CUL))

#define bFM_QPRC0_QECR_ORNGMD                     *((volatile  uint8_t *)(0x424C0380UL))
#define bFM4_QPRC0_QECR_ORNGMD                    *((volatile  uint8_t *)(0x424C0380UL))
#define bFM_QPRC0_QECR_ORNGF                      *((volatile  uint8_t *)(0x424C0384UL))
#define bFM4_QPRC0_QECR_ORNGF                     *((volatile  uint8_t *)(0x424C0384UL))
#define bFM_QPRC0_QECR_ORNGIE                     *((volatile  uint8_t *)(0x424C0388UL))
#define bFM4_QPRC0_QECR_ORNGIE                    *((volatile  uint8_t *)(0x424C0388UL))
#define bFM_QPRC0_QECR_PEC                        *((volatile  uint8_t *)(0x424C038CUL))
#define bFM4_QPRC0_QECR_PEC                       *((volatile  uint8_t *)(0x424C038CUL))

#define bFM_QPRC0_QICRH_CDCIE                     *((volatile  uint8_t *)(0x424C02A0UL))
#define bFM4_QPRC0_QICRH_CDCIE                    *((volatile  uint8_t *)(0x424C02A0UL))
#define bFM_QPRC0_QICRH_CDCF                      *((volatile  uint8_t *)(0x424C02A4UL))
#define bFM4_QPRC0_QICRH_CDCF                     *((volatile  uint8_t *)(0x424C02A4UL))
#define bFM_QPRC0_QICRH_DIRPC                     *((volatile  uint8_t *)(0x424C02A8UL))
#define bFM4_QPRC0_QICRH_DIRPC                    *((volatile  uint8_t *)(0x424C02A8UL))
#define bFM_QPRC0_QICRH_DIROU                     *((volatile  uint8_t *)(0x424C02ACUL))
#define bFM4_QPRC0_QICRH_DIROU                    *((volatile  uint8_t *)(0x424C02ACUL))
#define bFM_QPRC0_QICRH_QPCNRCMIE                 *((volatile  uint8_t *)(0x424C02B0UL))
#define bFM4_QPRC0_QICRH_QPCNRCMIE                *((volatile  uint8_t *)(0x424C02B0UL))
#define bFM_QPRC0_QICRH_QPCNRCMF                  *((volatile  uint8_t *)(0x424C02B4UL))
#define bFM4_QPRC0_QICRH_QPCNRCMF                 *((volatile  uint8_t *)(0x424C02B4UL))

#define bFM_QPRC0_QICRL_QPCMIE                    *((volatile  uint8_t *)(0x424C0280UL))
#define bFM4_QPRC0_QICRL_QPCMIE                   *((volatile  uint8_t *)(0x424C0280UL))
#define bFM_QPRC0_QICRL_QPCMF                     *((volatile  uint8_t *)(0x424C0284UL))
#define bFM4_QPRC0_QICRL_QPCMF                    *((volatile  uint8_t *)(0x424C0284UL))
#define bFM_QPRC0_QICRL_QPRCMIE                   *((volatile  uint8_t *)(0x424C0288UL))
#define bFM4_QPRC0_QICRL_QPRCMIE                  *((volatile  uint8_t *)(0x424C0288UL))
#define bFM_QPRC0_QICRL_QPRCMF                    *((volatile  uint8_t *)(0x424C028CUL))
#define bFM4_QPRC0_QICRL_QPRCMF                   *((volatile  uint8_t *)(0x424C028CUL))
#define bFM_QPRC0_QICRL_OUZIE                     *((volatile  uint8_t *)(0x424C0290UL))
#define bFM4_QPRC0_QICRL_OUZIE                    *((volatile  uint8_t *)(0x424C0290UL))
#define bFM_QPRC0_QICRL_UFDF                      *((volatile  uint8_t *)(0x424C0294UL))
#define bFM4_QPRC0_QICRL_UFDF                     *((volatile  uint8_t *)(0x424C0294UL))
#define bFM_QPRC0_QICRL_OFDF                      *((volatile  uint8_t *)(0x424C0298UL))
#define bFM4_QPRC0_QICRL_OFDF                     *((volatile  uint8_t *)(0x424C0298UL))
#define bFM_QPRC0_QICRL_ZIIF                      *((volatile  uint8_t *)(0x424C029CUL))
#define bFM4_QPRC0_QICRL_ZIIF                     *((volatile  uint8_t *)(0x424C029CUL))


/*******************************************************************************
* QPRC_NF Registers QPRC0_NF
*   Bitband Section
*******************************************************************************/
#define bFM_QPRC0_NF_NFCTLA_AINLV                 *((volatile  uint8_t *)(0x424C2010UL))
#define bFM4_QPRC0_NF_NFCTLA_AINLV                *((volatile  uint8_t *)(0x424C2010UL))
#define bFM_QPRC0_NF_NFCTLA_AINMD                 *((volatile  uint8_t *)(0x424C2014UL))
#define bFM4_QPRC0_NF_NFCTLA_AINMD                *((volatile  uint8_t *)(0x424C2014UL))

#define bFM_QPRC0_NF_NFCTLB_BINLV                 *((volatile  uint8_t *)(0x424C2090UL))
#define bFM4_QPRC0_NF_NFCTLB_BINLV                *((volatile  uint8_t *)(0x424C2090UL))
#define bFM_QPRC0_NF_NFCTLB_BINMD                 *((volatile  uint8_t *)(0x424C2094UL))
#define bFM4_QPRC0_NF_NFCTLB_BINMD                *((volatile  uint8_t *)(0x424C2094UL))

#define bFM_QPRC0_NF_NFCTLZ_ZINLV                 *((volatile  uint8_t *)(0x424C2110UL))
#define bFM4_QPRC0_NF_NFCTLZ_ZINLV                *((volatile  uint8_t *)(0x424C2110UL))
#define bFM_QPRC0_NF_NFCTLZ_ZINMD                 *((volatile  uint8_t *)(0x424C2114UL))
#define bFM4_QPRC0_NF_NFCTLZ_ZINMD                *((volatile  uint8_t *)(0x424C2114UL))


/*******************************************************************************
* QPRC Registers QPRC1
*   Bitband Section
*******************************************************************************/
#define bFM_QPRC1_QCR_PSTP                        *((volatile  uint8_t *)(0x424C0B10UL))
#define bFM4_QPRC1_QCR_PSTP                       *((volatile  uint8_t *)(0x424C0B10UL))
#define bFM_QPRC1_QCR_CGSC                        *((volatile  uint8_t *)(0x424C0B14UL))
#define bFM4_QPRC1_QCR_CGSC                       *((volatile  uint8_t *)(0x424C0B14UL))
#define bFM_QPRC1_QCR_RSEL                        *((volatile  uint8_t *)(0x424C0B18UL))
#define bFM4_QPRC1_QCR_RSEL                       *((volatile  uint8_t *)(0x424C0B18UL))
#define bFM_QPRC1_QCR_SWAP                        *((volatile  uint8_t *)(0x424C0B1CUL))
#define bFM4_QPRC1_QCR_SWAP                       *((volatile  uint8_t *)(0x424C0B1CUL))

#define bFM_QPRC1_QECR_ORNGMD                     *((volatile  uint8_t *)(0x424C0B80UL))
#define bFM4_QPRC1_QECR_ORNGMD                    *((volatile  uint8_t *)(0x424C0B80UL))
#define bFM_QPRC1_QECR_ORNGF                      *((volatile  uint8_t *)(0x424C0B84UL))
#define bFM4_QPRC1_QECR_ORNGF                     *((volatile  uint8_t *)(0x424C0B84UL))
#define bFM_QPRC1_QECR_ORNGIE                     *((volatile  uint8_t *)(0x424C0B88UL))
#define bFM4_QPRC1_QECR_ORNGIE                    *((volatile  uint8_t *)(0x424C0B88UL))
#define bFM_QPRC1_QECR_PEC                        *((volatile  uint8_t *)(0x424C0B8CUL))
#define bFM4_QPRC1_QECR_PEC                       *((volatile  uint8_t *)(0x424C0B8CUL))

#define bFM_QPRC1_QICRH_CDCIE                     *((volatile  uint8_t *)(0x424C0AA0UL))
#define bFM4_QPRC1_QICRH_CDCIE                    *((volatile  uint8_t *)(0x424C0AA0UL))
#define bFM_QPRC1_QICRH_CDCF                      *((volatile  uint8_t *)(0x424C0AA4UL))
#define bFM4_QPRC1_QICRH_CDCF                     *((volatile  uint8_t *)(0x424C0AA4UL))
#define bFM_QPRC1_QICRH_DIRPC                     *((volatile  uint8_t *)(0x424C0AA8UL))
#define bFM4_QPRC1_QICRH_DIRPC                    *((volatile  uint8_t *)(0x424C0AA8UL))
#define bFM_QPRC1_QICRH_DIROU                     *((volatile  uint8_t *)(0x424C0AACUL))
#define bFM4_QPRC1_QICRH_DIROU                    *((volatile  uint8_t *)(0x424C0AACUL))
#define bFM_QPRC1_QICRH_QPCNRCMIE                 *((volatile  uint8_t *)(0x424C0AB0UL))
#define bFM4_QPRC1_QICRH_QPCNRCMIE                *((volatile  uint8_t *)(0x424C0AB0UL))
#define bFM_QPRC1_QICRH_QPCNRCMF                  *((volatile  uint8_t *)(0x424C0AB4UL))
#define bFM4_QPRC1_QICRH_QPCNRCMF                 *((volatile  uint8_t *)(0x424C0AB4UL))

#define bFM_QPRC1_QICRL_QPCMIE                    *((volatile  uint8_t *)(0x424C0A80UL))
#define bFM4_QPRC1_QICRL_QPCMIE                   *((volatile  uint8_t *)(0x424C0A80UL))
#define bFM_QPRC1_QICRL_QPCMF                     *((volatile  uint8_t *)(0x424C0A84UL))
#define bFM4_QPRC1_QICRL_QPCMF                    *((volatile  uint8_t *)(0x424C0A84UL))
#define bFM_QPRC1_QICRL_QPRCMIE                   *((volatile  uint8_t *)(0x424C0A88UL))
#define bFM4_QPRC1_QICRL_QPRCMIE                  *((volatile  uint8_t *)(0x424C0A88UL))
#define bFM_QPRC1_QICRL_QPRCMF                    *((volatile  uint8_t *)(0x424C0A8CUL))
#define bFM4_QPRC1_QICRL_QPRCMF                   *((volatile  uint8_t *)(0x424C0A8CUL))
#define bFM_QPRC1_QICRL_OUZIE                     *((volatile  uint8_t *)(0x424C0A90UL))
#define bFM4_QPRC1_QICRL_OUZIE                    *((volatile  uint8_t *)(0x424C0A90UL))
#define bFM_QPRC1_QICRL_UFDF                      *((volatile  uint8_t *)(0x424C0A94UL))
#define bFM4_QPRC1_QICRL_UFDF                     *((volatile  uint8_t *)(0x424C0A94UL))
#define bFM_QPRC1_QICRL_OFDF                      *((volatile  uint8_t *)(0x424C0A98UL))
#define bFM4_QPRC1_QICRL_OFDF                     *((volatile  uint8_t *)(0x424C0A98UL))
#define bFM_QPRC1_QICRL_ZIIF                      *((volatile  uint8_t *)(0x424C0A9CUL))
#define bFM4_QPRC1_QICRL_ZIIF                     *((volatile  uint8_t *)(0x424C0A9CUL))


/*******************************************************************************
* QPRC_NF Registers QPRC1_NF
*   Bitband Section
*******************************************************************************/
#define bFM_QPRC1_NF_NFCTLA_AINLV                 *((volatile  uint8_t *)(0x424C2210UL))
#define bFM4_QPRC1_NF_NFCTLA_AINLV                *((volatile  uint8_t *)(0x424C2210UL))
#define bFM_QPRC1_NF_NFCTLA_AINMD                 *((volatile  uint8_t *)(0x424C2214UL))
#define bFM4_QPRC1_NF_NFCTLA_AINMD                *((volatile  uint8_t *)(0x424C2214UL))

#define bFM_QPRC1_NF_NFCTLB_BINLV                 *((volatile  uint8_t *)(0x424C2290UL))
#define bFM4_QPRC1_NF_NFCTLB_BINLV                *((volatile  uint8_t *)(0x424C2290UL))
#define bFM_QPRC1_NF_NFCTLB_BINMD                 *((volatile  uint8_t *)(0x424C2294UL))
#define bFM4_QPRC1_NF_NFCTLB_BINMD                *((volatile  uint8_t *)(0x424C2294UL))

#define bFM_QPRC1_NF_NFCTLZ_ZINLV                 *((volatile  uint8_t *)(0x424C2310UL))
#define bFM4_QPRC1_NF_NFCTLZ_ZINLV                *((volatile  uint8_t *)(0x424C2310UL))
#define bFM_QPRC1_NF_NFCTLZ_ZINMD                 *((volatile  uint8_t *)(0x424C2314UL))
#define bFM4_QPRC1_NF_NFCTLZ_ZINMD                *((volatile  uint8_t *)(0x424C2314UL))


/*******************************************************************************
* QPRC Registers QPRC2
*   Bitband Section
*******************************************************************************/
#define bFM_QPRC2_QCR_PSTP                        *((volatile  uint8_t *)(0x424C1310UL))
#define bFM4_QPRC2_QCR_PSTP                       *((volatile  uint8_t *)(0x424C1310UL))
#define bFM_QPRC2_QCR_CGSC                        *((volatile  uint8_t *)(0x424C1314UL))
#define bFM4_QPRC2_QCR_CGSC                       *((volatile  uint8_t *)(0x424C1314UL))
#define bFM_QPRC2_QCR_RSEL                        *((volatile  uint8_t *)(0x424C1318UL))
#define bFM4_QPRC2_QCR_RSEL                       *((volatile  uint8_t *)(0x424C1318UL))
#define bFM_QPRC2_QCR_SWAP                        *((volatile  uint8_t *)(0x424C131CUL))
#define bFM4_QPRC2_QCR_SWAP                       *((volatile  uint8_t *)(0x424C131CUL))

#define bFM_QPRC2_QECR_ORNGMD                     *((volatile  uint8_t *)(0x424C1380UL))
#define bFM4_QPRC2_QECR_ORNGMD                    *((volatile  uint8_t *)(0x424C1380UL))
#define bFM_QPRC2_QECR_ORNGF                      *((volatile  uint8_t *)(0x424C1384UL))
#define bFM4_QPRC2_QECR_ORNGF                     *((volatile  uint8_t *)(0x424C1384UL))
#define bFM_QPRC2_QECR_ORNGIE                     *((volatile  uint8_t *)(0x424C1388UL))
#define bFM4_QPRC2_QECR_ORNGIE                    *((volatile  uint8_t *)(0x424C1388UL))
#define bFM_QPRC2_QECR_PEC                        *((volatile  uint8_t *)(0x424C138CUL))
#define bFM4_QPRC2_QECR_PEC                       *((volatile  uint8_t *)(0x424C138CUL))

#define bFM_QPRC2_QICRH_CDCIE                     *((volatile  uint8_t *)(0x424C12A0UL))
#define bFM4_QPRC2_QICRH_CDCIE                    *((volatile  uint8_t *)(0x424C12A0UL))
#define bFM_QPRC2_QICRH_CDCF                      *((volatile  uint8_t *)(0x424C12A4UL))
#define bFM4_QPRC2_QICRH_CDCF                     *((volatile  uint8_t *)(0x424C12A4UL))
#define bFM_QPRC2_QICRH_DIRPC                     *((volatile  uint8_t *)(0x424C12A8UL))
#define bFM4_QPRC2_QICRH_DIRPC                    *((volatile  uint8_t *)(0x424C12A8UL))
#define bFM_QPRC2_QICRH_DIROU                     *((volatile  uint8_t *)(0x424C12ACUL))
#define bFM4_QPRC2_QICRH_DIROU                    *((volatile  uint8_t *)(0x424C12ACUL))
#define bFM_QPRC2_QICRH_QPCNRCMIE                 *((volatile  uint8_t *)(0x424C12B0UL))
#define bFM4_QPRC2_QICRH_QPCNRCMIE                *((volatile  uint8_t *)(0x424C12B0UL))
#define bFM_QPRC2_QICRH_QPCNRCMF                  *((volatile  uint8_t *)(0x424C12B4UL))
#define bFM4_QPRC2_QICRH_QPCNRCMF                 *((volatile  uint8_t *)(0x424C12B4UL))

#define bFM_QPRC2_QICRL_QPCMIE                    *((volatile  uint8_t *)(0x424C1280UL))
#define bFM4_QPRC2_QICRL_QPCMIE                   *((volatile  uint8_t *)(0x424C1280UL))
#define bFM_QPRC2_QICRL_QPCMF                     *((volatile  uint8_t *)(0x424C1284UL))
#define bFM4_QPRC2_QICRL_QPCMF                    *((volatile  uint8_t *)(0x424C1284UL))
#define bFM_QPRC2_QICRL_QPRCMIE                   *((volatile  uint8_t *)(0x424C1288UL))
#define bFM4_QPRC2_QICRL_QPRCMIE                  *((volatile  uint8_t *)(0x424C1288UL))
#define bFM_QPRC2_QICRL_QPRCMF                    *((volatile  uint8_t *)(0x424C128CUL))
#define bFM4_QPRC2_QICRL_QPRCMF                   *((volatile  uint8_t *)(0x424C128CUL))
#define bFM_QPRC2_QICRL_OUZIE                     *((volatile  uint8_t *)(0x424C1290UL))
#define bFM4_QPRC2_QICRL_OUZIE                    *((volatile  uint8_t *)(0x424C1290UL))
#define bFM_QPRC2_QICRL_UFDF                      *((volatile  uint8_t *)(0x424C1294UL))
#define bFM4_QPRC2_QICRL_UFDF                     *((volatile  uint8_t *)(0x424C1294UL))
#define bFM_QPRC2_QICRL_OFDF                      *((volatile  uint8_t *)(0x424C1298UL))
#define bFM4_QPRC2_QICRL_OFDF                     *((volatile  uint8_t *)(0x424C1298UL))
#define bFM_QPRC2_QICRL_ZIIF                      *((volatile  uint8_t *)(0x424C129CUL))
#define bFM4_QPRC2_QICRL_ZIIF                     *((volatile  uint8_t *)(0x424C129CUL))


/*******************************************************************************
* QPRC_NF Registers QPRC2_NF
*   Bitband Section
*******************************************************************************/
#define bFM_QPRC2_NF_NFCTLA_AINLV                 *((volatile  uint8_t *)(0x424C2410UL))
#define bFM4_QPRC2_NF_NFCTLA_AINLV                *((volatile  uint8_t *)(0x424C2410UL))
#define bFM_QPRC2_NF_NFCTLA_AINMD                 *((volatile  uint8_t *)(0x424C2414UL))
#define bFM4_QPRC2_NF_NFCTLA_AINMD                *((volatile  uint8_t *)(0x424C2414UL))

#define bFM_QPRC2_NF_NFCTLB_BINLV                 *((volatile  uint8_t *)(0x424C2490UL))
#define bFM4_QPRC2_NF_NFCTLB_BINLV                *((volatile  uint8_t *)(0x424C2490UL))
#define bFM_QPRC2_NF_NFCTLB_BINMD                 *((volatile  uint8_t *)(0x424C2494UL))
#define bFM4_QPRC2_NF_NFCTLB_BINMD                *((volatile  uint8_t *)(0x424C2494UL))

#define bFM_QPRC2_NF_NFCTLZ_ZINLV                 *((volatile  uint8_t *)(0x424C2510UL))
#define bFM4_QPRC2_NF_NFCTLZ_ZINLV                *((volatile  uint8_t *)(0x424C2510UL))
#define bFM_QPRC2_NF_NFCTLZ_ZINMD                 *((volatile  uint8_t *)(0x424C2514UL))
#define bFM4_QPRC2_NF_NFCTLZ_ZINMD                *((volatile  uint8_t *)(0x424C2514UL))


/*******************************************************************************
* QPRC Registers QPRC3
*   Bitband Section
*******************************************************************************/
#define bFM_QPRC3_QCR_PSTP                        *((volatile  uint8_t *)(0x424C1B10UL))
#define bFM4_QPRC3_QCR_PSTP                       *((volatile  uint8_t *)(0x424C1B10UL))
#define bFM_QPRC3_QCR_CGSC                        *((volatile  uint8_t *)(0x424C1B14UL))
#define bFM4_QPRC3_QCR_CGSC                       *((volatile  uint8_t *)(0x424C1B14UL))
#define bFM_QPRC3_QCR_RSEL                        *((volatile  uint8_t *)(0x424C1B18UL))
#define bFM4_QPRC3_QCR_RSEL                       *((volatile  uint8_t *)(0x424C1B18UL))
#define bFM_QPRC3_QCR_SWAP                        *((volatile  uint8_t *)(0x424C1B1CUL))
#define bFM4_QPRC3_QCR_SWAP                       *((volatile  uint8_t *)(0x424C1B1CUL))

#define bFM_QPRC3_QECR_ORNGMD                     *((volatile  uint8_t *)(0x424C1B80UL))
#define bFM4_QPRC3_QECR_ORNGMD                    *((volatile  uint8_t *)(0x424C1B80UL))
#define bFM_QPRC3_QECR_ORNGF                      *((volatile  uint8_t *)(0x424C1B84UL))
#define bFM4_QPRC3_QECR_ORNGF                     *((volatile  uint8_t *)(0x424C1B84UL))
#define bFM_QPRC3_QECR_ORNGIE                     *((volatile  uint8_t *)(0x424C1B88UL))
#define bFM4_QPRC3_QECR_ORNGIE                    *((volatile  uint8_t *)(0x424C1B88UL))
#define bFM_QPRC3_QECR_PEC                        *((volatile  uint8_t *)(0x424C1B8CUL))
#define bFM4_QPRC3_QECR_PEC                       *((volatile  uint8_t *)(0x424C1B8CUL))

#define bFM_QPRC3_QICRH_CDCIE                     *((volatile  uint8_t *)(0x424C1AA0UL))
#define bFM4_QPRC3_QICRH_CDCIE                    *((volatile  uint8_t *)(0x424C1AA0UL))
#define bFM_QPRC3_QICRH_CDCF                      *((volatile  uint8_t *)(0x424C1AA4UL))
#define bFM4_QPRC3_QICRH_CDCF                     *((volatile  uint8_t *)(0x424C1AA4UL))
#define bFM_QPRC3_QICRH_DIRPC                     *((volatile  uint8_t *)(0x424C1AA8UL))
#define bFM4_QPRC3_QICRH_DIRPC                    *((volatile  uint8_t *)(0x424C1AA8UL))
#define bFM_QPRC3_QICRH_DIROU                     *((volatile  uint8_t *)(0x424C1AACUL))
#define bFM4_QPRC3_QICRH_DIROU                    *((volatile  uint8_t *)(0x424C1AACUL))
#define bFM_QPRC3_QICRH_QPCNRCMIE                 *((volatile  uint8_t *)(0x424C1AB0UL))
#define bFM4_QPRC3_QICRH_QPCNRCMIE                *((volatile  uint8_t *)(0x424C1AB0UL))
#define bFM_QPRC3_QICRH_QPCNRCMF                  *((volatile  uint8_t *)(0x424C1AB4UL))
#define bFM4_QPRC3_QICRH_QPCNRCMF                 *((volatile  uint8_t *)(0x424C1AB4UL))

#define bFM_QPRC3_QICRL_QPCMIE                    *((volatile  uint8_t *)(0x424C1A80UL))
#define bFM4_QPRC3_QICRL_QPCMIE                   *((volatile  uint8_t *)(0x424C1A80UL))
#define bFM_QPRC3_QICRL_QPCMF                     *((volatile  uint8_t *)(0x424C1A84UL))
#define bFM4_QPRC3_QICRL_QPCMF                    *((volatile  uint8_t *)(0x424C1A84UL))
#define bFM_QPRC3_QICRL_QPRCMIE                   *((volatile  uint8_t *)(0x424C1A88UL))
#define bFM4_QPRC3_QICRL_QPRCMIE                  *((volatile  uint8_t *)(0x424C1A88UL))
#define bFM_QPRC3_QICRL_QPRCMF                    *((volatile  uint8_t *)(0x424C1A8CUL))
#define bFM4_QPRC3_QICRL_QPRCMF                   *((volatile  uint8_t *)(0x424C1A8CUL))
#define bFM_QPRC3_QICRL_OUZIE                     *((volatile  uint8_t *)(0x424C1A90UL))
#define bFM4_QPRC3_QICRL_OUZIE                    *((volatile  uint8_t *)(0x424C1A90UL))
#define bFM_QPRC3_QICRL_UFDF                      *((volatile  uint8_t *)(0x424C1A94UL))
#define bFM4_QPRC3_QICRL_UFDF                     *((volatile  uint8_t *)(0x424C1A94UL))
#define bFM_QPRC3_QICRL_OFDF                      *((volatile  uint8_t *)(0x424C1A98UL))
#define bFM4_QPRC3_QICRL_OFDF                     *((volatile  uint8_t *)(0x424C1A98UL))
#define bFM_QPRC3_QICRL_ZIIF                      *((volatile  uint8_t *)(0x424C1A9CUL))
#define bFM4_QPRC3_QICRL_ZIIF                     *((volatile  uint8_t *)(0x424C1A9CUL))


/*******************************************************************************
* QPRC_NF Registers QPRC3_NF
*   Bitband Section
*******************************************************************************/
#define bFM_QPRC3_NF_NFCTLA_AINLV                 *((volatile  uint8_t *)(0x424C2610UL))
#define bFM4_QPRC3_NF_NFCTLA_AINLV                *((volatile  uint8_t *)(0x424C2610UL))
#define bFM_QPRC3_NF_NFCTLA_AINMD                 *((volatile  uint8_t *)(0x424C2614UL))
#define bFM4_QPRC3_NF_NFCTLA_AINMD                *((volatile  uint8_t *)(0x424C2614UL))

#define bFM_QPRC3_NF_NFCTLB_BINLV                 *((volatile  uint8_t *)(0x424C2690UL))
#define bFM4_QPRC3_NF_NFCTLB_BINLV                *((volatile  uint8_t *)(0x424C2690UL))
#define bFM_QPRC3_NF_NFCTLB_BINMD                 *((volatile  uint8_t *)(0x424C2694UL))
#define bFM4_QPRC3_NF_NFCTLB_BINMD                *((volatile  uint8_t *)(0x424C2694UL))

#define bFM_QPRC3_NF_NFCTLZ_ZINLV                 *((volatile  uint8_t *)(0x424C2710UL))
#define bFM4_QPRC3_NF_NFCTLZ_ZINLV                *((volatile  uint8_t *)(0x424C2710UL))
#define bFM_QPRC3_NF_NFCTLZ_ZINMD                 *((volatile  uint8_t *)(0x424C2714UL))
#define bFM4_QPRC3_NF_NFCTLZ_ZINMD                *((volatile  uint8_t *)(0x424C2714UL))


/*******************************************************************************
* RTC Registers RTC
*   Bitband Section
*******************************************************************************/
#define bFM_RTC_ALMOR_TAMO                        *((volatile  uint8_t *)(0x42762890UL))
#define bFM4_RTC_ALMOR_TAMO                       *((volatile  uint8_t *)(0x42762890UL))

#define bFM_RTC_EWKUP_WUP0                        *((volatile  uint8_t *)(0x42763180UL))
#define bFM4_RTC_EWKUP_WUP0                       *((volatile  uint8_t *)(0x42763180UL))

#define bFM_RTC_HIBRST_HIBRST                     *((volatile  uint8_t *)(0x42763300UL))
#define bFM4_RTC_HIBRST_HIBRST                    *((volatile  uint8_t *)(0x42763300UL))

#define bFM_RTC_VBDDR_VDDR0                       *((volatile  uint8_t *)(0x42763480UL))
#define bFM4_RTC_VBDDR_VDDR0                      *((volatile  uint8_t *)(0x42763480UL))
#define bFM_RTC_VBDDR_VDDR1                       *((volatile  uint8_t *)(0x42763484UL))
#define bFM4_RTC_VBDDR_VDDR1                      *((volatile  uint8_t *)(0x42763484UL))
#define bFM_RTC_VBDDR_VDDR2                       *((volatile  uint8_t *)(0x42763488UL))
#define bFM4_RTC_VBDDR_VDDR2                      *((volatile  uint8_t *)(0x42763488UL))
#define bFM_RTC_VBDDR_VDDR3                       *((volatile  uint8_t *)(0x4276348CUL))
#define bFM4_RTC_VBDDR_VDDR3                      *((volatile  uint8_t *)(0x4276348CUL))

#define bFM_RTC_VBDIR_VDIR0                       *((volatile  uint8_t *)(0x42763500UL))
#define bFM4_RTC_VBDIR_VDIR0                      *((volatile  uint8_t *)(0x42763500UL))
#define bFM_RTC_VBDIR_VDIR1                       *((volatile  uint8_t *)(0x42763504UL))
#define bFM4_RTC_VBDIR_VDIR1                      *((volatile  uint8_t *)(0x42763504UL))
#define bFM_RTC_VBDIR_VDIR2                       *((volatile  uint8_t *)(0x42763508UL))
#define bFM4_RTC_VBDIR_VDIR2                      *((volatile  uint8_t *)(0x42763508UL))
#define bFM_RTC_VBDIR_VDIR3                       *((volatile  uint8_t *)(0x4276350CUL))
#define bFM4_RTC_VBDIR_VDIR3                      *((volatile  uint8_t *)(0x4276350CUL))

#define bFM_RTC_VBDOR_VDOR0                       *((volatile  uint8_t *)(0x42763580UL))
#define bFM4_RTC_VBDOR_VDOR0                      *((volatile  uint8_t *)(0x42763580UL))
#define bFM_RTC_VBDOR_VDOR1                       *((volatile  uint8_t *)(0x42763584UL))
#define bFM4_RTC_VBDOR_VDOR1                      *((volatile  uint8_t *)(0x42763584UL))
#define bFM_RTC_VBDOR_VDOR2                       *((volatile  uint8_t *)(0x42763588UL))
#define bFM4_RTC_VBDOR_VDOR2                      *((volatile  uint8_t *)(0x42763588UL))
#define bFM_RTC_VBDOR_VDOR3                       *((volatile  uint8_t *)(0x4276358CUL))
#define bFM4_RTC_VBDOR_VDOR3                      *((volatile  uint8_t *)(0x4276358CUL))

#define bFM_RTC_VBPCR_VPCR0                       *((volatile  uint8_t *)(0x42763400UL))
#define bFM4_RTC_VBPCR_VPCR0                      *((volatile  uint8_t *)(0x42763400UL))
#define bFM_RTC_VBPCR_VPCR1                       *((volatile  uint8_t *)(0x42763404UL))
#define bFM4_RTC_VBPCR_VPCR1                      *((volatile  uint8_t *)(0x42763404UL))
#define bFM_RTC_VBPCR_VPCR2                       *((volatile  uint8_t *)(0x42763408UL))
#define bFM4_RTC_VBPCR_VPCR2                      *((volatile  uint8_t *)(0x42763408UL))
#define bFM_RTC_VBPCR_VPCR3                       *((volatile  uint8_t *)(0x4276340CUL))
#define bFM4_RTC_VBPCR_VPCR3                      *((volatile  uint8_t *)(0x4276340CUL))

#define bFM_RTC_VBPFR_VPFR0                       *((volatile  uint8_t *)(0x42763380UL))
#define bFM4_RTC_VBPFR_VPFR0                      *((volatile  uint8_t *)(0x42763380UL))
#define bFM_RTC_VBPFR_VPFR1                       *((volatile  uint8_t *)(0x42763384UL))
#define bFM4_RTC_VBPFR_VPFR1                      *((volatile  uint8_t *)(0x42763384UL))
#define bFM_RTC_VBPFR_VPFR2                       *((volatile  uint8_t *)(0x42763388UL))
#define bFM4_RTC_VBPFR_VPFR2                      *((volatile  uint8_t *)(0x42763388UL))
#define bFM_RTC_VBPFR_VPFR3                       *((volatile  uint8_t *)(0x4276338CUL))
#define bFM4_RTC_VBPFR_VPFR3                      *((volatile  uint8_t *)(0x4276338CUL))

#define bFM_RTC_VBPZR_VPZR0                       *((volatile  uint8_t *)(0x42763600UL))
#define bFM4_RTC_VBPZR_VPZR0                      *((volatile  uint8_t *)(0x42763600UL))
#define bFM_RTC_VBPZR_VPZR1                       *((volatile  uint8_t *)(0x42763604UL))
#define bFM4_RTC_VBPZR_VPZR1                      *((volatile  uint8_t *)(0x42763604UL))

#define bFM_RTC_VDET_PON                          *((volatile  uint8_t *)(0x4276321CUL))
#define bFM4_RTC_VDET_PON                         *((volatile  uint8_t *)(0x4276321CUL))

#define bFM_RTC_WTCALEN_WTCALEN                   *((volatile  uint8_t *)(0x42762C00UL))
#define bFM4_RTC_WTCALEN_WTCALEN                  *((volatile  uint8_t *)(0x42762C00UL))

#define bFM_RTC_WTCOSEL_WTCOSEL                   *((volatile  uint8_t *)(0x42762E00UL))
#define bFM4_RTC_WTCOSEL_WTCOSEL                  *((volatile  uint8_t *)(0x42762E00UL))

#define bFM_RTC_WTCR10_ST                         *((volatile  uint8_t *)(0x42762000UL))
#define bFM4_RTC_WTCR10_ST                        *((volatile  uint8_t *)(0x42762000UL))
#define bFM_RTC_WTCR10_RUN                        *((volatile  uint8_t *)(0x42762008UL))
#define bFM4_RTC_WTCR10_RUN                       *((volatile  uint8_t *)(0x42762008UL))
#define bFM_RTC_WTCR10_SRST                       *((volatile  uint8_t *)(0x4276200CUL))
#define bFM4_RTC_WTCR10_SRST                      *((volatile  uint8_t *)(0x4276200CUL))
#define bFM_RTC_WTCR10_SCST                       *((volatile  uint8_t *)(0x42762010UL))
#define bFM4_RTC_WTCR10_SCST                      *((volatile  uint8_t *)(0x42762010UL))
#define bFM_RTC_WTCR10_SCRST                      *((volatile  uint8_t *)(0x42762014UL))
#define bFM4_RTC_WTCR10_SCRST                     *((volatile  uint8_t *)(0x42762014UL))
#define bFM_RTC_WTCR10_BUSY                       *((volatile  uint8_t *)(0x42762018UL))
#define bFM4_RTC_WTCR10_BUSY                      *((volatile  uint8_t *)(0x42762018UL))
#define bFM_RTC_WTCR10_TRANS                      *((volatile  uint8_t *)(0x4276201CUL))
#define bFM4_RTC_WTCR10_TRANS                     *((volatile  uint8_t *)(0x4276201CUL))

#define bFM_RTC_WTCR11_MIEN                       *((volatile  uint8_t *)(0x42762080UL))
#define bFM4_RTC_WTCR11_MIEN                      *((volatile  uint8_t *)(0x42762080UL))
#define bFM_RTC_WTCR11_HEN                        *((volatile  uint8_t *)(0x42762084UL))
#define bFM4_RTC_WTCR11_HEN                       *((volatile  uint8_t *)(0x42762084UL))
#define bFM_RTC_WTCR11_DEN                        *((volatile  uint8_t *)(0x42762088UL))
#define bFM4_RTC_WTCR11_DEN                       *((volatile  uint8_t *)(0x42762088UL))
#define bFM_RTC_WTCR11_MOEN                       *((volatile  uint8_t *)(0x4276208CUL))
#define bFM4_RTC_WTCR11_MOEN                      *((volatile  uint8_t *)(0x4276208CUL))
#define bFM_RTC_WTCR11_YEN                        *((volatile  uint8_t *)(0x42762090UL))
#define bFM4_RTC_WTCR11_YEN                       *((volatile  uint8_t *)(0x42762090UL))

#define bFM_RTC_WTCR12_INTSSI                     *((volatile  uint8_t *)(0x42762100UL))
#define bFM4_RTC_WTCR12_INTSSI                    *((volatile  uint8_t *)(0x42762100UL))
#define bFM_RTC_WTCR12_INTSI                      *((volatile  uint8_t *)(0x42762104UL))
#define bFM4_RTC_WTCR12_INTSI                     *((volatile  uint8_t *)(0x42762104UL))
#define bFM_RTC_WTCR12_INTMI                      *((volatile  uint8_t *)(0x42762108UL))
#define bFM4_RTC_WTCR12_INTMI                     *((volatile  uint8_t *)(0x42762108UL))
#define bFM_RTC_WTCR12_INTHI                      *((volatile  uint8_t *)(0x4276210CUL))
#define bFM4_RTC_WTCR12_INTHI                     *((volatile  uint8_t *)(0x4276210CUL))
#define bFM_RTC_WTCR12_INTTMI                     *((volatile  uint8_t *)(0x42762110UL))
#define bFM4_RTC_WTCR12_INTTMI                    *((volatile  uint8_t *)(0x42762110UL))
#define bFM_RTC_WTCR12_INTALI                     *((volatile  uint8_t *)(0x42762114UL))
#define bFM4_RTC_WTCR12_INTALI                    *((volatile  uint8_t *)(0x42762114UL))
#define bFM_RTC_WTCR12_INTERI                     *((volatile  uint8_t *)(0x42762118UL))
#define bFM4_RTC_WTCR12_INTERI                    *((volatile  uint8_t *)(0x42762118UL))
#define bFM_RTC_WTCR12_INTCRI                     *((volatile  uint8_t *)(0x4276211CUL))
#define bFM4_RTC_WTCR12_INTCRI                    *((volatile  uint8_t *)(0x4276211CUL))

#define bFM_RTC_WTCR13_INTSSIE                    *((volatile  uint8_t *)(0x42762180UL))
#define bFM4_RTC_WTCR13_INTSSIE                   *((volatile  uint8_t *)(0x42762180UL))
#define bFM_RTC_WTCR13_INTSIE                     *((volatile  uint8_t *)(0x42762184UL))
#define bFM4_RTC_WTCR13_INTSIE                    *((volatile  uint8_t *)(0x42762184UL))
#define bFM_RTC_WTCR13_INTMIE                     *((volatile  uint8_t *)(0x42762188UL))
#define bFM4_RTC_WTCR13_INTMIE                    *((volatile  uint8_t *)(0x42762188UL))
#define bFM_RTC_WTCR13_INTHIE                     *((volatile  uint8_t *)(0x4276218CUL))
#define bFM4_RTC_WTCR13_INTHIE                    *((volatile  uint8_t *)(0x4276218CUL))
#define bFM_RTC_WTCR13_INTTMIE                    *((volatile  uint8_t *)(0x42762190UL))
#define bFM4_RTC_WTCR13_INTTMIE                   *((volatile  uint8_t *)(0x42762190UL))
#define bFM_RTC_WTCR13_INTALIE                    *((volatile  uint8_t *)(0x42762194UL))
#define bFM4_RTC_WTCR13_INTALIE                   *((volatile  uint8_t *)(0x42762194UL))
#define bFM_RTC_WTCR13_INTERIE                    *((volatile  uint8_t *)(0x42762198UL))
#define bFM4_RTC_WTCR13_INTERIE                   *((volatile  uint8_t *)(0x42762198UL))
#define bFM_RTC_WTCR13_INTCRIE                    *((volatile  uint8_t *)(0x4276219CUL))
#define bFM4_RTC_WTCR13_INTCRIE                   *((volatile  uint8_t *)(0x4276219CUL))

#define bFM_RTC_WTCR20_CREAD                      *((volatile  uint8_t *)(0x42762200UL))
#define bFM4_RTC_WTCR20_CREAD                     *((volatile  uint8_t *)(0x42762200UL))
#define bFM_RTC_WTCR20_CWRITE                     *((volatile  uint8_t *)(0x42762204UL))
#define bFM4_RTC_WTCR20_CWRITE                    *((volatile  uint8_t *)(0x42762204UL))
#define bFM_RTC_WTCR20_BREAD                      *((volatile  uint8_t *)(0x42762208UL))
#define bFM4_RTC_WTCR20_BREAD                     *((volatile  uint8_t *)(0x42762208UL))
#define bFM_RTC_WTCR20_BWRITE                     *((volatile  uint8_t *)(0x4276220CUL))
#define bFM4_RTC_WTCR20_BWRITE                    *((volatile  uint8_t *)(0x4276220CUL))
#define bFM_RTC_WTCR20_PREAD                      *((volatile  uint8_t *)(0x42762210UL))
#define bFM4_RTC_WTCR20_PREAD                     *((volatile  uint8_t *)(0x42762210UL))
#define bFM_RTC_WTCR20_PWRITE                     *((volatile  uint8_t *)(0x42762214UL))
#define bFM4_RTC_WTCR20_PWRITE                    *((volatile  uint8_t *)(0x42762214UL))

#define bFM_RTC_WTCR21_TMST                       *((volatile  uint8_t *)(0x42762280UL))
#define bFM4_RTC_WTCR21_TMST                      *((volatile  uint8_t *)(0x42762280UL))
#define bFM_RTC_WTCR21_TMEN                       *((volatile  uint8_t *)(0x42762284UL))
#define bFM4_RTC_WTCR21_TMEN                      *((volatile  uint8_t *)(0x42762284UL))
#define bFM_RTC_WTCR21_TMRUN                      *((volatile  uint8_t *)(0x42762288UL))
#define bFM4_RTC_WTCR21_TMRUN                     *((volatile  uint8_t *)(0x42762288UL))

#define bFM_RTC_WTDIVEN_WTDIVEN                   *((volatile  uint8_t *)(0x42762D00UL))
#define bFM4_RTC_WTDIVEN_WTDIVEN                  *((volatile  uint8_t *)(0x42762D00UL))
#define bFM_RTC_WTDIVEN_WTDIVRDY                  *((volatile  uint8_t *)(0x42762D04UL))
#define bFM4_RTC_WTDIVEN_WTDIVRDY                 *((volatile  uint8_t *)(0x42762D04UL))

#define bFM_RTC_WTMOR_TMO                         *((volatile  uint8_t *)(0x42762610UL))
#define bFM4_RTC_WTMOR_TMO                        *((volatile  uint8_t *)(0x42762610UL))

#define bFM_RTC_WTOSCCNT_SOSCEX                   *((volatile  uint8_t *)(0x42762F00UL))
#define bFM4_RTC_WTOSCCNT_SOSCEX                  *((volatile  uint8_t *)(0x42762F00UL))
#define bFM_RTC_WTOSCCNT_SOSCNTL                  *((volatile  uint8_t *)(0x42762F04UL))
#define bFM4_RTC_WTOSCCNT_SOSCNTL                 *((volatile  uint8_t *)(0x42762F04UL))


/*******************************************************************************
* SBSSR Registers SBSSR
*   Bitband Section
*******************************************************************************/
#define bFM_SBSSR_BTSSSR_SSSR0                    *((volatile  uint8_t *)(0x424BFF80UL))
#define bFM4_SBSSR_BTSSSR_SSSR0                   *((volatile  uint8_t *)(0x424BFF80UL))
#define bFM_SBSSR_BTSSSR_SSSR1                    *((volatile  uint8_t *)(0x424BFF84UL))
#define bFM4_SBSSR_BTSSSR_SSSR1                   *((volatile  uint8_t *)(0x424BFF84UL))
#define bFM_SBSSR_BTSSSR_SSSR2                    *((volatile  uint8_t *)(0x424BFF88UL))
#define bFM4_SBSSR_BTSSSR_SSSR2                   *((volatile  uint8_t *)(0x424BFF88UL))
#define bFM_SBSSR_BTSSSR_SSSR3                    *((volatile  uint8_t *)(0x424BFF8CUL))
#define bFM4_SBSSR_BTSSSR_SSSR3                   *((volatile  uint8_t *)(0x424BFF8CUL))
#define bFM_SBSSR_BTSSSR_SSSR4                    *((volatile  uint8_t *)(0x424BFF90UL))
#define bFM4_SBSSR_BTSSSR_SSSR4                   *((volatile  uint8_t *)(0x424BFF90UL))
#define bFM_SBSSR_BTSSSR_SSSR5                    *((volatile  uint8_t *)(0x424BFF94UL))
#define bFM4_SBSSR_BTSSSR_SSSR5                   *((volatile  uint8_t *)(0x424BFF94UL))
#define bFM_SBSSR_BTSSSR_SSSR6                    *((volatile  uint8_t *)(0x424BFF98UL))
#define bFM4_SBSSR_BTSSSR_SSSR6                   *((volatile  uint8_t *)(0x424BFF98UL))
#define bFM_SBSSR_BTSSSR_SSSR7                    *((volatile  uint8_t *)(0x424BFF9CUL))
#define bFM4_SBSSR_BTSSSR_SSSR7                   *((volatile  uint8_t *)(0x424BFF9CUL))
#define bFM_SBSSR_BTSSSR_SSSR8                    *((volatile  uint8_t *)(0x424BFFA0UL))
#define bFM4_SBSSR_BTSSSR_SSSR8                   *((volatile  uint8_t *)(0x424BFFA0UL))
#define bFM_SBSSR_BTSSSR_SSSR9                    *((volatile  uint8_t *)(0x424BFFA4UL))
#define bFM4_SBSSR_BTSSSR_SSSR9                   *((volatile  uint8_t *)(0x424BFFA4UL))
#define bFM_SBSSR_BTSSSR_SSSR10                   *((volatile  uint8_t *)(0x424BFFA8UL))
#define bFM4_SBSSR_BTSSSR_SSSR10                  *((volatile  uint8_t *)(0x424BFFA8UL))
#define bFM_SBSSR_BTSSSR_SSSR11                   *((volatile  uint8_t *)(0x424BFFACUL))
#define bFM4_SBSSR_BTSSSR_SSSR11                  *((volatile  uint8_t *)(0x424BFFACUL))
#define bFM_SBSSR_BTSSSR_SSSR12                   *((volatile  uint8_t *)(0x424BFFB0UL))
#define bFM4_SBSSR_BTSSSR_SSSR12                  *((volatile  uint8_t *)(0x424BFFB0UL))
#define bFM_SBSSR_BTSSSR_SSSR13                   *((volatile  uint8_t *)(0x424BFFB4UL))
#define bFM4_SBSSR_BTSSSR_SSSR13                  *((volatile  uint8_t *)(0x424BFFB4UL))
#define bFM_SBSSR_BTSSSR_SSSR14                   *((volatile  uint8_t *)(0x424BFFB8UL))
#define bFM4_SBSSR_BTSSSR_SSSR14                  *((volatile  uint8_t *)(0x424BFFB8UL))
#define bFM_SBSSR_BTSSSR_SSSR15                   *((volatile  uint8_t *)(0x424BFFBCUL))
#define bFM4_SBSSR_BTSSSR_SSSR15                  *((volatile  uint8_t *)(0x424BFFBCUL))


/*******************************************************************************
* SDIF Registers SDIF
*   Bitband Section
*******************************************************************************/
#define bFM_SDIF_ADMAEST_ADMALENME                *((volatile  uint8_t *)(0x42DC0A88UL))
#define bFM4_SDIF_ADMAEST_ADMALENME               *((volatile  uint8_t *)(0x42DC0A88UL))

#define bFM_SDIF_AHBCFGL_SINEN                    *((volatile  uint8_t *)(0x42DC200CUL))
#define bFM4_SDIF_AHBCFGL_SINEN                   *((volatile  uint8_t *)(0x42DC200CUL))
#define bFM_SDIF_AHBCFGL_BSLOCK                   *((volatile  uint8_t *)(0x42DC2010UL))
#define bFM4_SDIF_AHBCFGL_BSLOCK                  *((volatile  uint8_t *)(0x42DC2010UL))
#define bFM_SDIF_AHBCFGL_BSLOCKSEL                *((volatile  uint8_t *)(0x42DC2014UL))
#define bFM4_SDIF_AHBCFGL_BSLOCKSEL               *((volatile  uint8_t *)(0x42DC2014UL))
#define bFM_SDIF_AHBCFGL_ENDIANSEL                *((volatile  uint8_t *)(0x42DC2018UL))
#define bFM4_SDIF_AHBCFGL_ENDIANSEL               *((volatile  uint8_t *)(0x42DC2018UL))

#define bFM_SDIF_CAPBLTY0_TOCLKUNIT               *((volatile  uint8_t *)(0x42DC081CUL))
#define bFM4_SDIF_CAPBLTY0_TOCLKUNIT              *((volatile  uint8_t *)(0x42DC081CUL))

#define bFM_SDIF_CAPBLTY1_EMBD8BIT                *((volatile  uint8_t *)(0x42DC0848UL))
#define bFM4_SDIF_CAPBLTY1_EMBD8BIT               *((volatile  uint8_t *)(0x42DC0848UL))
#define bFM_SDIF_CAPBLTY1_ADMA2SPT                *((volatile  uint8_t *)(0x42DC084CUL))
#define bFM4_SDIF_CAPBLTY1_ADMA2SPT               *((volatile  uint8_t *)(0x42DC084CUL))
#define bFM_SDIF_CAPBLTY1_HGHSPDSPT               *((volatile  uint8_t *)(0x42DC0854UL))
#define bFM4_SDIF_CAPBLTY1_HGHSPDSPT              *((volatile  uint8_t *)(0x42DC0854UL))
#define bFM_SDIF_CAPBLTY1_SDMASPT                 *((volatile  uint8_t *)(0x42DC0858UL))
#define bFM4_SDIF_CAPBLTY1_SDMASPT                *((volatile  uint8_t *)(0x42DC0858UL))
#define bFM_SDIF_CAPBLTY1_LWPWRSPT                *((volatile  uint8_t *)(0x42DC085CUL))
#define bFM4_SDIF_CAPBLTY1_LWPWRSPT               *((volatile  uint8_t *)(0x42DC085CUL))
#define bFM_SDIF_CAPBLTY1_V33SPT                  *((volatile  uint8_t *)(0x42DC0860UL))
#define bFM4_SDIF_CAPBLTY1_V33SPT                 *((volatile  uint8_t *)(0x42DC0860UL))
#define bFM_SDIF_CAPBLTY1_V30SPT                  *((volatile  uint8_t *)(0x42DC0864UL))
#define bFM4_SDIF_CAPBLTY1_V30SPT                 *((volatile  uint8_t *)(0x42DC0864UL))
#define bFM_SDIF_CAPBLTY1_V18SPT                  *((volatile  uint8_t *)(0x42DC0868UL))
#define bFM4_SDIF_CAPBLTY1_V18SPT                 *((volatile  uint8_t *)(0x42DC0868UL))
#define bFM_SDIF_CAPBLTY1_BUS64SPT                *((volatile  uint8_t *)(0x42DC0870UL))
#define bFM4_SDIF_CAPBLTY1_BUS64SPT               *((volatile  uint8_t *)(0x42DC0870UL))
#define bFM_SDIF_CAPBLTY1_ASYINTSPT               *((volatile  uint8_t *)(0x42DC0874UL))
#define bFM4_SDIF_CAPBLTY1_ASYINTSPT              *((volatile  uint8_t *)(0x42DC0874UL))

#define bFM_SDIF_CAPBLTY2_SDR50SPT                *((volatile  uint8_t *)(0x42DC0880UL))
#define bFM4_SDIF_CAPBLTY2_SDR50SPT               *((volatile  uint8_t *)(0x42DC0880UL))
#define bFM_SDIF_CAPBLTY2_SDR104SPT               *((volatile  uint8_t *)(0x42DC0884UL))
#define bFM4_SDIF_CAPBLTY2_SDR104SPT              *((volatile  uint8_t *)(0x42DC0884UL))
#define bFM_SDIF_CAPBLTY2_DDR50SPT                *((volatile  uint8_t *)(0x42DC0888UL))
#define bFM4_SDIF_CAPBLTY2_DDR50SPT               *((volatile  uint8_t *)(0x42DC0888UL))
#define bFM_SDIF_CAPBLTY2_DRVTPASPT               *((volatile  uint8_t *)(0x42DC0890UL))
#define bFM4_SDIF_CAPBLTY2_DRVTPASPT              *((volatile  uint8_t *)(0x42DC0890UL))
#define bFM_SDIF_CAPBLTY2_DRVTPCSPT               *((volatile  uint8_t *)(0x42DC0894UL))
#define bFM4_SDIF_CAPBLTY2_DRVTPCSPT              *((volatile  uint8_t *)(0x42DC0894UL))
#define bFM_SDIF_CAPBLTY2_DRVTPDSPT               *((volatile  uint8_t *)(0x42DC0898UL))
#define bFM4_SDIF_CAPBLTY2_DRVTPDSPT              *((volatile  uint8_t *)(0x42DC0898UL))
#define bFM_SDIF_CAPBLTY2_USETNSDR50              *((volatile  uint8_t *)(0x42DC08B4UL))
#define bFM4_SDIF_CAPBLTY2_USETNSDR50             *((volatile  uint8_t *)(0x42DC08B4UL))

#define bFM_SDIF_FEACEST_FEVNT12ND                *((volatile  uint8_t *)(0x42DC0A00UL))
#define bFM4_SDIF_FEACEST_FEVNT12ND               *((volatile  uint8_t *)(0x42DC0A00UL))
#define bFM_SDIF_FEACEST_FEVNTTO                  *((volatile  uint8_t *)(0x42DC0A04UL))
#define bFM4_SDIF_FEACEST_FEVNTTO                 *((volatile  uint8_t *)(0x42DC0A04UL))
#define bFM_SDIF_FEACEST_FEVNTCRC                 *((volatile  uint8_t *)(0x42DC0A08UL))
#define bFM4_SDIF_FEACEST_FEVNTCRC                *((volatile  uint8_t *)(0x42DC0A08UL))
#define bFM_SDIF_FEACEST_FEVNTEB                  *((volatile  uint8_t *)(0x42DC0A0CUL))
#define bFM4_SDIF_FEACEST_FEVNTEB                 *((volatile  uint8_t *)(0x42DC0A0CUL))
#define bFM_SDIF_FEACEST_FEVNTIDX                 *((volatile  uint8_t *)(0x42DC0A10UL))
#define bFM4_SDIF_FEACEST_FEVNTIDX                *((volatile  uint8_t *)(0x42DC0A10UL))
#define bFM_SDIF_FEACEST_FEVNTCMD12               *((volatile  uint8_t *)(0x42DC0A1CUL))
#define bFM4_SDIF_FEACEST_FEVNTCMD12              *((volatile  uint8_t *)(0x42DC0A1CUL))

#define bFM_SDIF_MCWIRQC0_WTIRQEN                 *((volatile  uint8_t *)(0x42DC2500UL))
#define bFM4_SDIF_MCWIRQC0_WTIRQEN                *((volatile  uint8_t *)(0x42DC2500UL))
#define bFM_SDIF_MCWIRQC0_WTIRQST                 *((volatile  uint8_t *)(0x42DC2504UL))
#define bFM4_SDIF_MCWIRQC0_WTIRQST                *((volatile  uint8_t *)(0x42DC2504UL))

#define bFM_SDIF_MMCSDCH_BTACKENMMC               *((volatile  uint8_t *)(0x42DC24C0UL))
#define bFM4_SDIF_MMCSDCH_BTACKENMMC              *((volatile  uint8_t *)(0x42DC24C0UL))
#define bFM_SDIF_MMCSDCH_BTABTENMMC               *((volatile  uint8_t *)(0x42DC24C4UL))
#define bFM4_SDIF_MMCSDCH_BTABTENMMC              *((volatile  uint8_t *)(0x42DC24C4UL))
#define bFM_SDIF_MMCSDCH_BTMDENMMC                *((volatile  uint8_t *)(0x42DC24C8UL))
#define bFM4_SDIF_MMCSDCH_BTMDENMMC               *((volatile  uint8_t *)(0x42DC24C8UL))

#define bFM_SDIF_MMCSDCL_LCKRSTESD                *((volatile  uint8_t *)(0x42DC2480UL))
#define bFM4_SDIF_MMCSDCL_LCKRSTESD               *((volatile  uint8_t *)(0x42DC2480UL))
#define bFM_SDIF_MMCSDCL_RSTMMC                   *((volatile  uint8_t *)(0x42DC2484UL))
#define bFM4_SDIF_MMCSDCL_RSTMMC                  *((volatile  uint8_t *)(0x42DC2484UL))
#define bFM_SDIF_MMCSDCL_VCCCTLMMC                *((volatile  uint8_t *)(0x42DC2488UL))
#define bFM4_SDIF_MMCSDCL_VCCCTLMMC               *((volatile  uint8_t *)(0x42DC2488UL))
#define bFM_SDIF_MMCSDCL_VCCQCTLMMC               *((volatile  uint8_t *)(0x42DC248CUL))
#define bFM4_SDIF_MMCSDCL_VCCQCTLMMC              *((volatile  uint8_t *)(0x42DC248CUL))
#define bFM_SDIF_MMCSDCL_MMCDDRSEL                *((volatile  uint8_t *)(0x42DC24A0UL))
#define bFM4_SDIF_MMCSDCL_MMCDDRSEL               *((volatile  uint8_t *)(0x42DC24A0UL))
#define bFM_SDIF_MMCSDCL_CMDDATDLY                *((volatile  uint8_t *)(0x42DC24A4UL))
#define bFM4_SDIF_MMCSDCL_CMDDATDLY               *((volatile  uint8_t *)(0x42DC24A4UL))

#define bFM_SDIF_PSWISGEL_INT5MSSGEN              *((volatile  uint8_t *)(0x42DC2400UL))
#define bFM4_SDIF_PSWISGEL_INT5MSSGEN             *((volatile  uint8_t *)(0x42DC2400UL))
#define bFM_SDIF_PSWISGEL_INT1MSSGEN              *((volatile  uint8_t *)(0x42DC2404UL))
#define bFM4_SDIF_PSWISGEL_INT1MSSGEN             *((volatile  uint8_t *)(0x42DC2404UL))

#define bFM_SDIF_PSWISTEL_INT5MSSTS               *((volatile  uint8_t *)(0x42DC2380UL))
#define bFM4_SDIF_PSWISTEL_INT5MSSTS              *((volatile  uint8_t *)(0x42DC2380UL))
#define bFM_SDIF_PSWISTEL_INT1MSSTS               *((volatile  uint8_t *)(0x42DC2384UL))
#define bFM4_SDIF_PSWISTEL_INT1MSSTS              *((volatile  uint8_t *)(0x42DC2384UL))

#define bFM_SDIF_PSWISTL_INT5MS                   *((volatile  uint8_t *)(0x42DC2300UL))
#define bFM4_SDIF_PSWISTL_INT5MS                  *((volatile  uint8_t *)(0x42DC2300UL))
#define bFM_SDIF_PSWISTL_INT1MS                   *((volatile  uint8_t *)(0x42DC2304UL))
#define bFM4_SDIF_PSWISTL_INT1MS                  *((volatile  uint8_t *)(0x42DC2304UL))

#define bFM_SDIF_SACMDEST_ACMD12NOEX              *((volatile  uint8_t *)(0x42DC0780UL))
#define bFM4_SDIF_SACMDEST_ACMD12NOEX             *((volatile  uint8_t *)(0x42DC0780UL))
#define bFM_SDIF_SACMDEST_ACMDTOERR               *((volatile  uint8_t *)(0x42DC0784UL))
#define bFM4_SDIF_SACMDEST_ACMDTOERR              *((volatile  uint8_t *)(0x42DC0784UL))
#define bFM_SDIF_SACMDEST_ACMDCRCERR              *((volatile  uint8_t *)(0x42DC0788UL))
#define bFM4_SDIF_SACMDEST_ACMDCRCERR             *((volatile  uint8_t *)(0x42DC0788UL))
#define bFM_SDIF_SACMDEST_ACMDEBERR               *((volatile  uint8_t *)(0x42DC078CUL))
#define bFM4_SDIF_SACMDEST_ACMDEBERR              *((volatile  uint8_t *)(0x42DC078CUL))
#define bFM_SDIF_SACMDEST_ACMDIDXERR              *((volatile  uint8_t *)(0x42DC0790UL))
#define bFM4_SDIF_SACMDEST_ACMDIDXERR             *((volatile  uint8_t *)(0x42DC0790UL))
#define bFM_SDIF_SACMDEST_CMDND12ERR              *((volatile  uint8_t *)(0x42DC079CUL))
#define bFM4_SDIF_SACMDEST_CMDND12ERR             *((volatile  uint8_t *)(0x42DC079CUL))

#define bFM_SDIF_SBLKGPCTL_BLCKGSTPREQ            *((volatile  uint8_t *)(0x42DC0540UL))
#define bFM4_SDIF_SBLKGPCTL_BLCKGSTPREQ           *((volatile  uint8_t *)(0x42DC0540UL))
#define bFM_SDIF_SBLKGPCTL_CONTREQ                *((volatile  uint8_t *)(0x42DC0544UL))
#define bFM4_SDIF_SBLKGPCTL_CONTREQ               *((volatile  uint8_t *)(0x42DC0544UL))
#define bFM_SDIF_SBLKGPCTL_RDWAITCTL              *((volatile  uint8_t *)(0x42DC0548UL))
#define bFM4_SDIF_SBLKGPCTL_RDWAITCTL             *((volatile  uint8_t *)(0x42DC0548UL))
#define bFM_SDIF_SBLKGPCTL_BLCKGAPINT             *((volatile  uint8_t *)(0x42DC054CUL))
#define bFM4_SDIF_SBLKGPCTL_BLCKGAPINT            *((volatile  uint8_t *)(0x42DC054CUL))

#define bFM_SDIF_SCLKCTL_INTLCLCKEN               *((volatile  uint8_t *)(0x42DC0580UL))
#define bFM4_SDIF_SCLKCTL_INTLCLCKEN              *((volatile  uint8_t *)(0x42DC0580UL))
#define bFM_SDIF_SCLKCTL_INTLCLCKST               *((volatile  uint8_t *)(0x42DC0584UL))
#define bFM4_SDIF_SCLKCTL_INTLCLCKST              *((volatile  uint8_t *)(0x42DC0584UL))
#define bFM_SDIF_SCLKCTL_SDCLCKEN                 *((volatile  uint8_t *)(0x42DC0588UL))
#define bFM4_SDIF_SCLKCTL_SDCLCKEN                *((volatile  uint8_t *)(0x42DC0588UL))
#define bFM_SDIF_SCLKCTL_CLCKGENSEL               *((volatile  uint8_t *)(0x42DC0594UL))
#define bFM4_SDIF_SCLKCTL_CLCKGENSEL              *((volatile  uint8_t *)(0x42DC0594UL))

#define bFM_SDIF_SCMMD_CMDCRCCHKE                 *((volatile  uint8_t *)(0x42DC01CCUL))
#define bFM4_SDIF_SCMMD_CMDCRCCHKE                *((volatile  uint8_t *)(0x42DC01CCUL))
#define bFM_SDIF_SCMMD_CMDIDXCHKE                 *((volatile  uint8_t *)(0x42DC01D0UL))
#define bFM4_SDIF_SCMMD_CMDIDXCHKE                *((volatile  uint8_t *)(0x42DC01D0UL))
#define bFM_SDIF_SCMMD_DATPRESSEL                 *((volatile  uint8_t *)(0x42DC01D4UL))
#define bFM4_SDIF_SCMMD_DATPRESSEL                *((volatile  uint8_t *)(0x42DC01D4UL))

#define bFM_SDIF_SEINTSGE_CMDTOERRG               *((volatile  uint8_t *)(0x42DC0740UL))
#define bFM4_SDIF_SEINTSGE_CMDTOERRG              *((volatile  uint8_t *)(0x42DC0740UL))
#define bFM_SDIF_SEINTSGE_CMDCRCERRG              *((volatile  uint8_t *)(0x42DC0744UL))
#define bFM4_SDIF_SEINTSGE_CMDCRCERRG             *((volatile  uint8_t *)(0x42DC0744UL))
#define bFM_SDIF_SEINTSGE_CMDEBERRG               *((volatile  uint8_t *)(0x42DC0748UL))
#define bFM4_SDIF_SEINTSGE_CMDEBERRG              *((volatile  uint8_t *)(0x42DC0748UL))
#define bFM_SDIF_SEINTSGE_CMDIDXERRG              *((volatile  uint8_t *)(0x42DC074CUL))
#define bFM4_SDIF_SEINTSGE_CMDIDXERRG             *((volatile  uint8_t *)(0x42DC074CUL))
#define bFM_SDIF_SEINTSGE_DTTOERRG                *((volatile  uint8_t *)(0x42DC0750UL))
#define bFM4_SDIF_SEINTSGE_DTTOERRG               *((volatile  uint8_t *)(0x42DC0750UL))
#define bFM_SDIF_SEINTSGE_DTCRCERRG               *((volatile  uint8_t *)(0x42DC0754UL))
#define bFM4_SDIF_SEINTSGE_DTCRCERRG              *((volatile  uint8_t *)(0x42DC0754UL))
#define bFM_SDIF_SEINTSGE_DTEBERRG                *((volatile  uint8_t *)(0x42DC0758UL))
#define bFM4_SDIF_SEINTSGE_DTEBERRG               *((volatile  uint8_t *)(0x42DC0758UL))
#define bFM_SDIF_SEINTSGE_CRTLMTERRG              *((volatile  uint8_t *)(0x42DC075CUL))
#define bFM4_SDIF_SEINTSGE_CRTLMTERRG             *((volatile  uint8_t *)(0x42DC075CUL))
#define bFM_SDIF_SEINTSGE_ACMD12ERRG              *((volatile  uint8_t *)(0x42DC0760UL))
#define bFM4_SDIF_SEINTSGE_ACMD12ERRG             *((volatile  uint8_t *)(0x42DC0760UL))
#define bFM_SDIF_SEINTSGE_ADMAERRG                *((volatile  uint8_t *)(0x42DC0764UL))
#define bFM4_SDIF_SEINTSGE_ADMAERRG               *((volatile  uint8_t *)(0x42DC0764UL))
#define bFM_SDIF_SEINTSGE_TUNINGERRG              *((volatile  uint8_t *)(0x42DC0768UL))
#define bFM4_SDIF_SEINTSGE_TUNINGERRG             *((volatile  uint8_t *)(0x42DC0768UL))
#define bFM_SDIF_SEINTSGE_BTACKERRG               *((volatile  uint8_t *)(0x42DC0770UL))
#define bFM4_SDIF_SEINTSGE_BTACKERRG              *((volatile  uint8_t *)(0x42DC0770UL))
#define bFM_SDIF_SEINTSGE_ACMD19ERRG              *((volatile  uint8_t *)(0x42DC0774UL))
#define bFM4_SDIF_SEINTSGE_ACMD19ERRG             *((volatile  uint8_t *)(0x42DC0774UL))
#define bFM_SDIF_SEINTSGE_AHBMSTERRG              *((volatile  uint8_t *)(0x42DC0778UL))
#define bFM4_SDIF_SEINTSGE_AHBMSTERRG             *((volatile  uint8_t *)(0x42DC0778UL))

#define bFM_SDIF_SEINTST_CMDTOERR                 *((volatile  uint8_t *)(0x42DC0640UL))
#define bFM4_SDIF_SEINTST_CMDTOERR                *((volatile  uint8_t *)(0x42DC0640UL))
#define bFM_SDIF_SEINTST_CMDCRCERR                *((volatile  uint8_t *)(0x42DC0644UL))
#define bFM4_SDIF_SEINTST_CMDCRCERR               *((volatile  uint8_t *)(0x42DC0644UL))
#define bFM_SDIF_SEINTST_CMDEBERR                 *((volatile  uint8_t *)(0x42DC0648UL))
#define bFM4_SDIF_SEINTST_CMDEBERR                *((volatile  uint8_t *)(0x42DC0648UL))
#define bFM_SDIF_SEINTST_CMDIDXERR                *((volatile  uint8_t *)(0x42DC064CUL))
#define bFM4_SDIF_SEINTST_CMDIDXERR               *((volatile  uint8_t *)(0x42DC064CUL))
#define bFM_SDIF_SEINTST_DTTOERR                  *((volatile  uint8_t *)(0x42DC0650UL))
#define bFM4_SDIF_SEINTST_DTTOERR                 *((volatile  uint8_t *)(0x42DC0650UL))
#define bFM_SDIF_SEINTST_DTCRCERR                 *((volatile  uint8_t *)(0x42DC0654UL))
#define bFM4_SDIF_SEINTST_DTCRCERR                *((volatile  uint8_t *)(0x42DC0654UL))
#define bFM_SDIF_SEINTST_DTEBERR                  *((volatile  uint8_t *)(0x42DC0658UL))
#define bFM4_SDIF_SEINTST_DTEBERR                 *((volatile  uint8_t *)(0x42DC0658UL))
#define bFM_SDIF_SEINTST_CRTLMTERR                *((volatile  uint8_t *)(0x42DC065CUL))
#define bFM4_SDIF_SEINTST_CRTLMTERR               *((volatile  uint8_t *)(0x42DC065CUL))
#define bFM_SDIF_SEINTST_ACMD12ERR                *((volatile  uint8_t *)(0x42DC0660UL))
#define bFM4_SDIF_SEINTST_ACMD12ERR               *((volatile  uint8_t *)(0x42DC0660UL))
#define bFM_SDIF_SEINTST_ADMAERR                  *((volatile  uint8_t *)(0x42DC0664UL))
#define bFM4_SDIF_SEINTST_ADMAERR                 *((volatile  uint8_t *)(0x42DC0664UL))
#define bFM_SDIF_SEINTST_TUNINGERR                *((volatile  uint8_t *)(0x42DC0668UL))
#define bFM4_SDIF_SEINTST_TUNINGERR               *((volatile  uint8_t *)(0x42DC0668UL))
#define bFM_SDIF_SEINTST_BTACKERR                 *((volatile  uint8_t *)(0x42DC0670UL))
#define bFM4_SDIF_SEINTST_BTACKERR                *((volatile  uint8_t *)(0x42DC0670UL))
#define bFM_SDIF_SEINTST_ACMD19ERR                *((volatile  uint8_t *)(0x42DC0674UL))
#define bFM4_SDIF_SEINTST_ACMD19ERR               *((volatile  uint8_t *)(0x42DC0674UL))
#define bFM_SDIF_SEINTST_AHBMSTERR                *((volatile  uint8_t *)(0x42DC0678UL))
#define bFM4_SDIF_SEINTST_AHBMSTERR               *((volatile  uint8_t *)(0x42DC0678UL))

#define bFM_SDIF_SEINTSTE_CMDTOERRS               *((volatile  uint8_t *)(0x42DC06C0UL))
#define bFM4_SDIF_SEINTSTE_CMDTOERRS              *((volatile  uint8_t *)(0x42DC06C0UL))
#define bFM_SDIF_SEINTSTE_CMDCRCERRS              *((volatile  uint8_t *)(0x42DC06C4UL))
#define bFM4_SDIF_SEINTSTE_CMDCRCERRS             *((volatile  uint8_t *)(0x42DC06C4UL))
#define bFM_SDIF_SEINTSTE_CMDEBERRS               *((volatile  uint8_t *)(0x42DC06C8UL))
#define bFM4_SDIF_SEINTSTE_CMDEBERRS              *((volatile  uint8_t *)(0x42DC06C8UL))
#define bFM_SDIF_SEINTSTE_CMDIDXERRS              *((volatile  uint8_t *)(0x42DC06CCUL))
#define bFM4_SDIF_SEINTSTE_CMDIDXERRS             *((volatile  uint8_t *)(0x42DC06CCUL))
#define bFM_SDIF_SEINTSTE_DTTOERRS                *((volatile  uint8_t *)(0x42DC06D0UL))
#define bFM4_SDIF_SEINTSTE_DTTOERRS               *((volatile  uint8_t *)(0x42DC06D0UL))
#define bFM_SDIF_SEINTSTE_DTCRCERRS               *((volatile  uint8_t *)(0x42DC06D4UL))
#define bFM4_SDIF_SEINTSTE_DTCRCERRS              *((volatile  uint8_t *)(0x42DC06D4UL))
#define bFM_SDIF_SEINTSTE_DTEBERRS                *((volatile  uint8_t *)(0x42DC06D8UL))
#define bFM4_SDIF_SEINTSTE_DTEBERRS               *((volatile  uint8_t *)(0x42DC06D8UL))
#define bFM_SDIF_SEINTSTE_CRTLMTERRS              *((volatile  uint8_t *)(0x42DC06DCUL))
#define bFM4_SDIF_SEINTSTE_CRTLMTERRS             *((volatile  uint8_t *)(0x42DC06DCUL))
#define bFM_SDIF_SEINTSTE_ACMD12ERRS              *((volatile  uint8_t *)(0x42DC06E0UL))
#define bFM4_SDIF_SEINTSTE_ACMD12ERRS             *((volatile  uint8_t *)(0x42DC06E0UL))
#define bFM_SDIF_SEINTSTE_ADMAERRS                *((volatile  uint8_t *)(0x42DC06E4UL))
#define bFM4_SDIF_SEINTSTE_ADMAERRS               *((volatile  uint8_t *)(0x42DC06E4UL))
#define bFM_SDIF_SEINTSTE_TUNINGERRS              *((volatile  uint8_t *)(0x42DC06E8UL))
#define bFM4_SDIF_SEINTSTE_TUNINGERRS             *((volatile  uint8_t *)(0x42DC06E8UL))
#define bFM_SDIF_SEINTSTE_BTACKERRS               *((volatile  uint8_t *)(0x42DC06F0UL))
#define bFM4_SDIF_SEINTSTE_BTACKERRS              *((volatile  uint8_t *)(0x42DC06F0UL))
#define bFM_SDIF_SEINTSTE_ACMD19ERRS              *((volatile  uint8_t *)(0x42DC06F4UL))
#define bFM4_SDIF_SEINTSTE_ACMD19ERRS             *((volatile  uint8_t *)(0x42DC06F4UL))
#define bFM_SDIF_SEINTSTE_AHBMSTERRS              *((volatile  uint8_t *)(0x42DC06F8UL))
#define bFM4_SDIF_SEINTSTE_AHBMSTERRS             *((volatile  uint8_t *)(0x42DC06F8UL))

#define bFM_SDIF_SFEEIST_FETOERR                  *((volatile  uint8_t *)(0x42DC0A40UL))
#define bFM4_SDIF_SFEEIST_FETOERR                 *((volatile  uint8_t *)(0x42DC0A40UL))
#define bFM_SDIF_SFEEIST_FECRCERR                 *((volatile  uint8_t *)(0x42DC0A44UL))
#define bFM4_SDIF_SFEEIST_FECRCERR                *((volatile  uint8_t *)(0x42DC0A44UL))
#define bFM_SDIF_SFEEIST_FEEBERR                  *((volatile  uint8_t *)(0x42DC0A48UL))
#define bFM4_SDIF_SFEEIST_FEEBERR                 *((volatile  uint8_t *)(0x42DC0A48UL))
#define bFM_SDIF_SFEEIST_FEIDXERR                 *((volatile  uint8_t *)(0x42DC0A4CUL))
#define bFM4_SDIF_SFEEIST_FEIDXERR                *((volatile  uint8_t *)(0x42DC0A4CUL))
#define bFM_SDIF_SFEEIST_FEDTOTERR                *((volatile  uint8_t *)(0x42DC0A50UL))
#define bFM4_SDIF_SFEEIST_FEDTOTERR               *((volatile  uint8_t *)(0x42DC0A50UL))
#define bFM_SDIF_SFEEIST_FEDTCRCERR               *((volatile  uint8_t *)(0x42DC0A54UL))
#define bFM4_SDIF_SFEEIST_FEDTCRCERR              *((volatile  uint8_t *)(0x42DC0A54UL))
#define bFM_SDIF_SFEEIST_FEDTEBERR                *((volatile  uint8_t *)(0x42DC0A58UL))
#define bFM4_SDIF_SFEEIST_FEDTEBERR               *((volatile  uint8_t *)(0x42DC0A58UL))
#define bFM_SDIF_SFEEIST_FECRLTERR                *((volatile  uint8_t *)(0x42DC0A5CUL))
#define bFM4_SDIF_SFEEIST_FECRLTERR               *((volatile  uint8_t *)(0x42DC0A5CUL))
#define bFM_SDIF_SFEEIST_FEA12ERR                 *((volatile  uint8_t *)(0x42DC0A60UL))
#define bFM4_SDIF_SFEEIST_FEA12ERR                *((volatile  uint8_t *)(0x42DC0A60UL))
#define bFM_SDIF_SFEEIST_FEADMAERR                *((volatile  uint8_t *)(0x42DC0A64UL))
#define bFM4_SDIF_SFEEIST_FEADMAERR               *((volatile  uint8_t *)(0x42DC0A64UL))
#define bFM_SDIF_SFEEIST_FETUNEERR                *((volatile  uint8_t *)(0x42DC0A68UL))
#define bFM4_SDIF_SFEEIST_FETUNEERR               *((volatile  uint8_t *)(0x42DC0A68UL))
#define bFM_SDIF_SFEEIST_FEACKERR                 *((volatile  uint8_t *)(0x42DC0A70UL))
#define bFM4_SDIF_SFEEIST_FEACKERR                *((volatile  uint8_t *)(0x42DC0A70UL))
#define bFM_SDIF_SFEEIST_FEA19ERR                 *((volatile  uint8_t *)(0x42DC0A74UL))
#define bFM4_SDIF_SFEEIST_FEA19ERR                *((volatile  uint8_t *)(0x42DC0A74UL))
#define bFM_SDIF_SFEEIST_FEAHBMSERR               *((volatile  uint8_t *)(0x42DC0A78UL))
#define bFM4_SDIF_SFEEIST_FEAHBMSERR              *((volatile  uint8_t *)(0x42DC0A78UL))

#define bFM_SDIF_SHCTL1_LEDCTRL                   *((volatile  uint8_t *)(0x42DC0500UL))
#define bFM4_SDIF_SHCTL1_LEDCTRL                  *((volatile  uint8_t *)(0x42DC0500UL))
#define bFM_SDIF_SHCTL1_DATAWIDTH                 *((volatile  uint8_t *)(0x42DC0504UL))
#define bFM4_SDIF_SHCTL1_DATAWIDTH                *((volatile  uint8_t *)(0x42DC0504UL))
#define bFM_SDIF_SHCTL1_HIGHSPDEN                 *((volatile  uint8_t *)(0x42DC0508UL))
#define bFM4_SDIF_SHCTL1_HIGHSPDEN                *((volatile  uint8_t *)(0x42DC0508UL))
#define bFM_SDIF_SHCTL1_EXTDTWIDTH                *((volatile  uint8_t *)(0x42DC0514UL))
#define bFM4_SDIF_SHCTL1_EXTDTWIDTH               *((volatile  uint8_t *)(0x42DC0514UL))
#define bFM_SDIF_SHCTL1_CDTSTLVL                  *((volatile  uint8_t *)(0x42DC0518UL))
#define bFM4_SDIF_SHCTL1_CDTSTLVL                 *((volatile  uint8_t *)(0x42DC0518UL))
#define bFM_SDIF_SHCTL1_CDSGNSEL                  *((volatile  uint8_t *)(0x42DC051CUL))
#define bFM4_SDIF_SHCTL1_CDSGNSEL                 *((volatile  uint8_t *)(0x42DC051CUL))

#define bFM_SDIF_SHCTL2_V18SGNEN                  *((volatile  uint8_t *)(0x42DC07CCUL))
#define bFM4_SDIF_SHCTL2_V18SGNEN                 *((volatile  uint8_t *)(0x42DC07CCUL))
#define bFM_SDIF_SHCTL2_DOTUING                   *((volatile  uint8_t *)(0x42DC07D8UL))
#define bFM4_SDIF_SHCTL2_DOTUING                  *((volatile  uint8_t *)(0x42DC07D8UL))
#define bFM_SDIF_SHCTL2_SMPCLKSEL                 *((volatile  uint8_t *)(0x42DC07DCUL))
#define bFM4_SDIF_SHCTL2_SMPCLKSEL                *((volatile  uint8_t *)(0x42DC07DCUL))
#define bFM_SDIF_SHCTL2_ASYINTEN                  *((volatile  uint8_t *)(0x42DC07F8UL))
#define bFM4_SDIF_SHCTL2_ASYINTEN                 *((volatile  uint8_t *)(0x42DC07F8UL))
#define bFM_SDIF_SHCTL2_PREVALEN                  *((volatile  uint8_t *)(0x42DC07FCUL))
#define bFM4_SDIF_SHCTL2_PREVALEN                 *((volatile  uint8_t *)(0x42DC07FCUL))

#define bFM_SDIF_SNINTSGE_CMDCMPLTG               *((volatile  uint8_t *)(0x42DC0700UL))
#define bFM4_SDIF_SNINTSGE_CMDCMPLTG              *((volatile  uint8_t *)(0x42DC0700UL))
#define bFM_SDIF_SNINTSGE_TRSFCMPLTG              *((volatile  uint8_t *)(0x42DC0704UL))
#define bFM4_SDIF_SNINTSGE_TRSFCMPLTG             *((volatile  uint8_t *)(0x42DC0704UL))
#define bFM_SDIF_SNINTSGE_BLCKGEVNTG              *((volatile  uint8_t *)(0x42DC0708UL))
#define bFM4_SDIF_SNINTSGE_BLCKGEVNTG             *((volatile  uint8_t *)(0x42DC0708UL))
#define bFM_SDIF_SNINTSGE_DMAINTG                 *((volatile  uint8_t *)(0x42DC070CUL))
#define bFM4_SDIF_SNINTSGE_DMAINTG                *((volatile  uint8_t *)(0x42DC070CUL))
#define bFM_SDIF_SNINTSGE_BUFWRRDYG               *((volatile  uint8_t *)(0x42DC0710UL))
#define bFM4_SDIF_SNINTSGE_BUFWRRDYG              *((volatile  uint8_t *)(0x42DC0710UL))
#define bFM_SDIF_SNINTSGE_BUFRDRDYG               *((volatile  uint8_t *)(0x42DC0714UL))
#define bFM4_SDIF_SNINTSGE_BUFRDRDYG              *((volatile  uint8_t *)(0x42DC0714UL))
#define bFM_SDIF_SNINTSGE_CARDINSG                *((volatile  uint8_t *)(0x42DC0718UL))
#define bFM4_SDIF_SNINTSGE_CARDINSG               *((volatile  uint8_t *)(0x42DC0718UL))
#define bFM_SDIF_SNINTSGE_CARDRMVG                *((volatile  uint8_t *)(0x42DC071CUL))
#define bFM4_SDIF_SNINTSGE_CARDRMVG               *((volatile  uint8_t *)(0x42DC071CUL))
#define bFM_SDIF_SNINTSGE_CARDINTG                *((volatile  uint8_t *)(0x42DC0720UL))
#define bFM4_SDIF_SNINTSGE_CARDINTG               *((volatile  uint8_t *)(0x42DC0720UL))
#define bFM_SDIF_SNINTSGE_INT_AG                  *((volatile  uint8_t *)(0x42DC0724UL))
#define bFM4_SDIF_SNINTSGE_INT_AG                 *((volatile  uint8_t *)(0x42DC0724UL))
#define bFM_SDIF_SNINTSGE_INT_BG                  *((volatile  uint8_t *)(0x42DC0728UL))
#define bFM4_SDIF_SNINTSGE_INT_BG                 *((volatile  uint8_t *)(0x42DC0728UL))
#define bFM_SDIF_SNINTSGE_INT_CG                  *((volatile  uint8_t *)(0x42DC072CUL))
#define bFM4_SDIF_SNINTSGE_INT_CG                 *((volatile  uint8_t *)(0x42DC072CUL))
#define bFM_SDIF_SNINTSGE_RETUNEEVTG              *((volatile  uint8_t *)(0x42DC0730UL))
#define bFM4_SDIF_SNINTSGE_RETUNEEVTG             *((volatile  uint8_t *)(0x42DC0730UL))

#define bFM_SDIF_SNINTST_CMDCMPLT                 *((volatile  uint8_t *)(0x42DC0600UL))
#define bFM4_SDIF_SNINTST_CMDCMPLT                *((volatile  uint8_t *)(0x42DC0600UL))
#define bFM_SDIF_SNINTST_TRSFCMPLT                *((volatile  uint8_t *)(0x42DC0604UL))
#define bFM4_SDIF_SNINTST_TRSFCMPLT               *((volatile  uint8_t *)(0x42DC0604UL))
#define bFM_SDIF_SNINTST_BLCKGEVNT                *((volatile  uint8_t *)(0x42DC0608UL))
#define bFM4_SDIF_SNINTST_BLCKGEVNT               *((volatile  uint8_t *)(0x42DC0608UL))
#define bFM_SDIF_SNINTST_DMAINT                   *((volatile  uint8_t *)(0x42DC060CUL))
#define bFM4_SDIF_SNINTST_DMAINT                  *((volatile  uint8_t *)(0x42DC060CUL))
#define bFM_SDIF_SNINTST_BUFWRRDY                 *((volatile  uint8_t *)(0x42DC0610UL))
#define bFM4_SDIF_SNINTST_BUFWRRDY                *((volatile  uint8_t *)(0x42DC0610UL))
#define bFM_SDIF_SNINTST_BUFRDRDY                 *((volatile  uint8_t *)(0x42DC0614UL))
#define bFM4_SDIF_SNINTST_BUFRDRDY                *((volatile  uint8_t *)(0x42DC0614UL))
#define bFM_SDIF_SNINTST_CARDINS                  *((volatile  uint8_t *)(0x42DC0618UL))
#define bFM4_SDIF_SNINTST_CARDINS                 *((volatile  uint8_t *)(0x42DC0618UL))
#define bFM_SDIF_SNINTST_CARDRMV                  *((volatile  uint8_t *)(0x42DC061CUL))
#define bFM4_SDIF_SNINTST_CARDRMV                 *((volatile  uint8_t *)(0x42DC061CUL))
#define bFM_SDIF_SNINTST_CARDINT                  *((volatile  uint8_t *)(0x42DC0620UL))
#define bFM4_SDIF_SNINTST_CARDINT                 *((volatile  uint8_t *)(0x42DC0620UL))
#define bFM_SDIF_SNINTST_INT_A                    *((volatile  uint8_t *)(0x42DC0624UL))
#define bFM4_SDIF_SNINTST_INT_A                   *((volatile  uint8_t *)(0x42DC0624UL))
#define bFM_SDIF_SNINTST_INT_B                    *((volatile  uint8_t *)(0x42DC0628UL))
#define bFM4_SDIF_SNINTST_INT_B                   *((volatile  uint8_t *)(0x42DC0628UL))
#define bFM_SDIF_SNINTST_INT_C                    *((volatile  uint8_t *)(0x42DC062CUL))
#define bFM4_SDIF_SNINTST_INT_C                   *((volatile  uint8_t *)(0x42DC062CUL))
#define bFM_SDIF_SNINTST_RETUNEEVT                *((volatile  uint8_t *)(0x42DC0630UL))
#define bFM4_SDIF_SNINTST_RETUNEEVT               *((volatile  uint8_t *)(0x42DC0630UL))
#define bFM_SDIF_SNINTST_ERRORINT                 *((volatile  uint8_t *)(0x42DC063CUL))
#define bFM4_SDIF_SNINTST_ERRORINT                *((volatile  uint8_t *)(0x42DC063CUL))

#define bFM_SDIF_SNINTSTE_CMDCMPLTS               *((volatile  uint8_t *)(0x42DC0680UL))
#define bFM4_SDIF_SNINTSTE_CMDCMPLTS              *((volatile  uint8_t *)(0x42DC0680UL))
#define bFM_SDIF_SNINTSTE_TRSFCMPLTS              *((volatile  uint8_t *)(0x42DC0684UL))
#define bFM4_SDIF_SNINTSTE_TRSFCMPLTS             *((volatile  uint8_t *)(0x42DC0684UL))
#define bFM_SDIF_SNINTSTE_BLCKGEVNTS              *((volatile  uint8_t *)(0x42DC0688UL))
#define bFM4_SDIF_SNINTSTE_BLCKGEVNTS             *((volatile  uint8_t *)(0x42DC0688UL))
#define bFM_SDIF_SNINTSTE_DMAINTS                 *((volatile  uint8_t *)(0x42DC068CUL))
#define bFM4_SDIF_SNINTSTE_DMAINTS                *((volatile  uint8_t *)(0x42DC068CUL))
#define bFM_SDIF_SNINTSTE_BUFWRRDYS               *((volatile  uint8_t *)(0x42DC0690UL))
#define bFM4_SDIF_SNINTSTE_BUFWRRDYS              *((volatile  uint8_t *)(0x42DC0690UL))
#define bFM_SDIF_SNINTSTE_BUFRDRDYS               *((volatile  uint8_t *)(0x42DC0694UL))
#define bFM4_SDIF_SNINTSTE_BUFRDRDYS              *((volatile  uint8_t *)(0x42DC0694UL))
#define bFM_SDIF_SNINTSTE_CARDINSS                *((volatile  uint8_t *)(0x42DC0698UL))
#define bFM4_SDIF_SNINTSTE_CARDINSS               *((volatile  uint8_t *)(0x42DC0698UL))
#define bFM_SDIF_SNINTSTE_CARDRMVS                *((volatile  uint8_t *)(0x42DC069CUL))
#define bFM4_SDIF_SNINTSTE_CARDRMVS               *((volatile  uint8_t *)(0x42DC069CUL))
#define bFM_SDIF_SNINTSTE_CARDINTS                *((volatile  uint8_t *)(0x42DC06A0UL))
#define bFM4_SDIF_SNINTSTE_CARDINTS               *((volatile  uint8_t *)(0x42DC06A0UL))
#define bFM_SDIF_SNINTSTE_INT_AS                  *((volatile  uint8_t *)(0x42DC06A4UL))
#define bFM4_SDIF_SNINTSTE_INT_AS                 *((volatile  uint8_t *)(0x42DC06A4UL))
#define bFM_SDIF_SNINTSTE_INT_BS                  *((volatile  uint8_t *)(0x42DC06A8UL))
#define bFM4_SDIF_SNINTSTE_INT_BS                 *((volatile  uint8_t *)(0x42DC06A8UL))
#define bFM_SDIF_SNINTSTE_INT_CS                  *((volatile  uint8_t *)(0x42DC06ACUL))
#define bFM4_SDIF_SNINTSTE_INT_CS                 *((volatile  uint8_t *)(0x42DC06ACUL))
#define bFM_SDIF_SNINTSTE_RETUNEEVTS              *((volatile  uint8_t *)(0x42DC06B0UL))
#define bFM4_SDIF_SNINTSTE_RETUNEEVTS             *((volatile  uint8_t *)(0x42DC06B0UL))

#define bFM_SDIF_SPRSTAT_CMDINH                   *((volatile  uint8_t *)(0x42DC0480UL))
#define bFM4_SDIF_SPRSTAT_CMDINH                  *((volatile  uint8_t *)(0x42DC0480UL))
#define bFM_SDIF_SPRSTAT_CMDDATINH                *((volatile  uint8_t *)(0x42DC0484UL))
#define bFM4_SDIF_SPRSTAT_CMDDATINH               *((volatile  uint8_t *)(0x42DC0484UL))
#define bFM_SDIF_SPRSTAT_DATLNACT                 *((volatile  uint8_t *)(0x42DC0488UL))
#define bFM4_SDIF_SPRSTAT_DATLNACT                *((volatile  uint8_t *)(0x42DC0488UL))
#define bFM_SDIF_SPRSTAT_RETUNEREQ                *((volatile  uint8_t *)(0x42DC048CUL))
#define bFM4_SDIF_SPRSTAT_RETUNEREQ               *((volatile  uint8_t *)(0x42DC048CUL))
#define bFM_SDIF_SPRSTAT_WRTRSFACT                *((volatile  uint8_t *)(0x42DC04A0UL))
#define bFM4_SDIF_SPRSTAT_WRTRSFACT               *((volatile  uint8_t *)(0x42DC04A0UL))
#define bFM_SDIF_SPRSTAT_RDTRSFACT                *((volatile  uint8_t *)(0x42DC04A4UL))
#define bFM4_SDIF_SPRSTAT_RDTRSFACT               *((volatile  uint8_t *)(0x42DC04A4UL))
#define bFM_SDIF_SPRSTAT_BUFWREN                  *((volatile  uint8_t *)(0x42DC04A8UL))
#define bFM4_SDIF_SPRSTAT_BUFWREN                 *((volatile  uint8_t *)(0x42DC04A8UL))
#define bFM_SDIF_SPRSTAT_BUFRDEN                  *((volatile  uint8_t *)(0x42DC04ACUL))
#define bFM4_SDIF_SPRSTAT_BUFRDEN                 *((volatile  uint8_t *)(0x42DC04ACUL))
#define bFM_SDIF_SPRSTAT_CARDINS                  *((volatile  uint8_t *)(0x42DC04C0UL))
#define bFM4_SDIF_SPRSTAT_CARDINS                 *((volatile  uint8_t *)(0x42DC04C0UL))
#define bFM_SDIF_SPRSTAT_CARDSTB                  *((volatile  uint8_t *)(0x42DC04C4UL))
#define bFM4_SDIF_SPRSTAT_CARDSTB                 *((volatile  uint8_t *)(0x42DC04C4UL))
#define bFM_SDIF_SPRSTAT_CARDDET                  *((volatile  uint8_t *)(0x42DC04C8UL))
#define bFM4_SDIF_SPRSTAT_CARDDET                 *((volatile  uint8_t *)(0x42DC04C8UL))
#define bFM_SDIF_SPRSTAT_WPPINLVL                 *((volatile  uint8_t *)(0x42DC04CCUL))
#define bFM4_SDIF_SPRSTAT_WPPINLVL                *((volatile  uint8_t *)(0x42DC04CCUL))
#define bFM_SDIF_SPRSTAT_CMDLNSGN                 *((volatile  uint8_t *)(0x42DC04E0UL))
#define bFM4_SDIF_SPRSTAT_CMDLNSGN                *((volatile  uint8_t *)(0x42DC04E0UL))

#define bFM_SDIF_SPRVAL0_CGSELVAL                 *((volatile  uint8_t *)(0x42DC0C28UL))
#define bFM4_SDIF_SPRVAL0_CGSELVAL                *((volatile  uint8_t *)(0x42DC0C28UL))

#define bFM_SDIF_SPRVAL1_CGSELVAL                 *((volatile  uint8_t *)(0x42DC0C68UL))
#define bFM4_SDIF_SPRVAL1_CGSELVAL                *((volatile  uint8_t *)(0x42DC0C68UL))

#define bFM_SDIF_SPRVAL2_CGSELVAL                 *((volatile  uint8_t *)(0x42DC0CA8UL))
#define bFM4_SDIF_SPRVAL2_CGSELVAL                *((volatile  uint8_t *)(0x42DC0CA8UL))

#define bFM_SDIF_SPRVAL3_CGSELVAL                 *((volatile  uint8_t *)(0x42DC0CE8UL))
#define bFM4_SDIF_SPRVAL3_CGSELVAL                *((volatile  uint8_t *)(0x42DC0CE8UL))

#define bFM_SDIF_SPRVAL4_CGSELVAL                 *((volatile  uint8_t *)(0x42DC0D28UL))
#define bFM4_SDIF_SPRVAL4_CGSELVAL                *((volatile  uint8_t *)(0x42DC0D28UL))

#define bFM_SDIF_SPRVAL5_CGSELVAL                 *((volatile  uint8_t *)(0x42DC0D68UL))
#define bFM4_SDIF_SPRVAL5_CGSELVAL                *((volatile  uint8_t *)(0x42DC0D68UL))

#define bFM_SDIF_SPRVAL6_CGSELVAL                 *((volatile  uint8_t *)(0x42DC0DA8UL))
#define bFM4_SDIF_SPRVAL6_CGSELVAL                *((volatile  uint8_t *)(0x42DC0DA8UL))

#define bFM_SDIF_SPRVAL7_CGSELVAL                 *((volatile  uint8_t *)(0x42DC0DE8UL))
#define bFM4_SDIF_SPRVAL7_CGSELVAL                *((volatile  uint8_t *)(0x42DC0DE8UL))

#define bFM_SDIF_SPWRCTL_SDBUSPWR                 *((volatile  uint8_t *)(0x42DC0520UL))
#define bFM4_SDIF_SPWRCTL_SDBUSPWR                *((volatile  uint8_t *)(0x42DC0520UL))

#define bFM_SDIF_SPWSWCL_ATPWRSWEN                *((volatile  uint8_t *)(0x42DC2080UL))
#define bFM4_SDIF_SPWSWCL_ATPWRSWEN               *((volatile  uint8_t *)(0x42DC2080UL))
#define bFM_SDIF_SPWSWCL_IOREGSEL                 *((volatile  uint8_t *)(0x42DC2084UL))
#define bFM4_SDIF_SPWSWCL_IOREGSEL                *((volatile  uint8_t *)(0x42DC2084UL))

#define bFM_SDIF_SSRST_SWRSTALL                   *((volatile  uint8_t *)(0x42DC05E0UL))
#define bFM4_SDIF_SSRST_SWRSTALL                  *((volatile  uint8_t *)(0x42DC05E0UL))
#define bFM_SDIF_SSRST_SWRSTCMDLN                 *((volatile  uint8_t *)(0x42DC05E4UL))
#define bFM4_SDIF_SSRST_SWRSTCMDLN                *((volatile  uint8_t *)(0x42DC05E4UL))
#define bFM_SDIF_SSRST_SWRSTDATLN                 *((volatile  uint8_t *)(0x42DC05E8UL))
#define bFM4_SDIF_SSRST_SWRSTDATLN                *((volatile  uint8_t *)(0x42DC05E8UL))

#define bFM_SDIF_STRSFMD_DMAEN                    *((volatile  uint8_t *)(0x42DC0180UL))
#define bFM4_SDIF_STRSFMD_DMAEN                   *((volatile  uint8_t *)(0x42DC0180UL))
#define bFM_SDIF_STRSFMD_BLCKCNTEN                *((volatile  uint8_t *)(0x42DC0184UL))
#define bFM4_SDIF_STRSFMD_BLCKCNTEN               *((volatile  uint8_t *)(0x42DC0184UL))
#define bFM_SDIF_STRSFMD_DTTRSFDIR                *((volatile  uint8_t *)(0x42DC0190UL))
#define bFM4_SDIF_STRSFMD_DTTRSFDIR               *((volatile  uint8_t *)(0x42DC0190UL))
#define bFM_SDIF_STRSFMD_BLCKCNTSEL               *((volatile  uint8_t *)(0x42DC0194UL))
#define bFM4_SDIF_STRSFMD_BLCKCNTSEL              *((volatile  uint8_t *)(0x42DC0194UL))

#define bFM_SDIF_STUNSETH_CMDCFCHKDS              *((volatile  uint8_t *)(0x42DC2140UL))
#define bFM4_SDIF_STUNSETH_CMDCFCHKDS             *((volatile  uint8_t *)(0x42DC2140UL))

#define bFM_SDIF_STUNSETL_TNPHSELEN               *((volatile  uint8_t *)(0x42DC2120UL))
#define bFM4_SDIF_STUNSETL_TNPHSELEN              *((volatile  uint8_t *)(0x42DC2120UL))
#define bFM_SDIF_STUNSETL_TNERRBDSEL              *((volatile  uint8_t *)(0x42DC2124UL))
#define bFM4_SDIF_STUNSETL_TNERRBDSEL             *((volatile  uint8_t *)(0x42DC2124UL))
#define bFM_SDIF_STUNSETL_RETNTAPSEL              *((volatile  uint8_t *)(0x42DC2128UL))
#define bFM4_SDIF_STUNSETL_RETNTAPSEL             *((volatile  uint8_t *)(0x42DC2128UL))

#define bFM_SDIF_SWKUPCTL_WKUPEVNTEN0             *((volatile  uint8_t *)(0x42DC0560UL))
#define bFM4_SDIF_SWKUPCTL_WKUPEVNTEN0            *((volatile  uint8_t *)(0x42DC0560UL))
#define bFM_SDIF_SWKUPCTL_WKUPEVNTEN1             *((volatile  uint8_t *)(0x42DC0564UL))
#define bFM4_SDIF_SWKUPCTL_WKUPEVNTEN1            *((volatile  uint8_t *)(0x42DC0564UL))
#define bFM_SDIF_SWKUPCTL_WKUPEVNTEN2             *((volatile  uint8_t *)(0x42DC0568UL))
#define bFM4_SDIF_SWKUPCTL_WKUPEVNTEN2            *((volatile  uint8_t *)(0x42DC0568UL))


/*******************************************************************************
* SWWDT Registers SWWDT
*   Bitband Section
*******************************************************************************/
#define bFM_SWWDT_WDOGCONTROL_INTEN               *((volatile  uint32_t*)(0x42240100UL))
#define bFM4_SWWDT_WDOGCONTROL_INTEN              *((volatile  uint32_t*)(0x42240100UL))
#define bFM_SWWDT_WDOGCONTROL_RESEN               *((volatile  uint32_t*)(0x42240104UL))
#define bFM4_SWWDT_WDOGCONTROL_RESEN              *((volatile  uint32_t*)(0x42240104UL))
#define bFM_SWWDT_WDOGCONTROL_SPM                 *((volatile  uint32_t*)(0x42240110UL))
#define bFM4_SWWDT_WDOGCONTROL_SPM                *((volatile  uint32_t*)(0x42240110UL))

#define bFM_SWWDT_WDOGRIS_RIS                     *((volatile  uint32_t*)(0x42240200UL))
#define bFM4_SWWDT_WDOGRIS_RIS                    *((volatile  uint32_t*)(0x42240200UL))

#define bFM_SWWDT_WDOGSPMC_TGR                    *((volatile  uint32_t*)(0x42240300UL))
#define bFM4_SWWDT_WDOGSPMC_TGR                   *((volatile  uint32_t*)(0x42240300UL))


/*******************************************************************************
* UNIQUE_ID Registers UNIQUE_ID
*   Bitband Section
*******************************************************************************/

/*******************************************************************************
* USB Registers USB0
*   Bitband Section
*******************************************************************************/
#define bFM_USB0_EP0C_STAL                        *((volatile  uint16_t*)(0x428424A4UL))
#define bFM4_USB0_EP0C_STAL                       *((volatile  uint16_t*)(0x428424A4UL))

#define bFM_USB0_EP0IS_DRQI                       *((volatile  uint16_t*)(0x428428A8UL))
#define bFM4_USB0_EP0IS_DRQI                      *((volatile  uint16_t*)(0x428428A8UL))
#define bFM_USB0_EP0IS_DRQIIE                     *((volatile  uint16_t*)(0x428428B8UL))
#define bFM4_USB0_EP0IS_DRQIIE                    *((volatile  uint16_t*)(0x428428B8UL))
#define bFM_USB0_EP0IS_BFINI                      *((volatile  uint16_t*)(0x428428BCUL))
#define bFM4_USB0_EP0IS_BFINI                     *((volatile  uint16_t*)(0x428428BCUL))

#define bFM_USB0_EP0OS_SPK                        *((volatile  uint16_t*)(0x42842924UL))
#define bFM4_USB0_EP0OS_SPK                       *((volatile  uint16_t*)(0x42842924UL))
#define bFM_USB0_EP0OS_DRQO                       *((volatile  uint16_t*)(0x42842928UL))
#define bFM4_USB0_EP0OS_DRQO                      *((volatile  uint16_t*)(0x42842928UL))
#define bFM_USB0_EP0OS_SPKIE                      *((volatile  uint16_t*)(0x42842934UL))
#define bFM4_USB0_EP0OS_SPKIE                     *((volatile  uint16_t*)(0x42842934UL))
#define bFM_USB0_EP0OS_DRQOIE                     *((volatile  uint16_t*)(0x42842938UL))
#define bFM4_USB0_EP0OS_DRQOIE                    *((volatile  uint16_t*)(0x42842938UL))
#define bFM_USB0_EP0OS_BFINI                      *((volatile  uint16_t*)(0x4284293CUL))
#define bFM4_USB0_EP0OS_BFINI                     *((volatile  uint16_t*)(0x4284293CUL))

#define bFM_USB0_EP1C_STAL                        *((volatile  uint16_t*)(0x42842524UL))
#define bFM4_USB0_EP1C_STAL                       *((volatile  uint16_t*)(0x42842524UL))
#define bFM_USB0_EP1C_NULE                        *((volatile  uint16_t*)(0x42842528UL))
#define bFM4_USB0_EP1C_NULE                       *((volatile  uint16_t*)(0x42842528UL))
#define bFM_USB0_EP1C_DMAE                        *((volatile  uint16_t*)(0x4284252CUL))
#define bFM4_USB0_EP1C_DMAE                       *((volatile  uint16_t*)(0x4284252CUL))
#define bFM_USB0_EP1C_DIR                         *((volatile  uint16_t*)(0x42842530UL))
#define bFM4_USB0_EP1C_DIR                        *((volatile  uint16_t*)(0x42842530UL))
#define bFM_USB0_EP1C_EPEN                        *((volatile  uint16_t*)(0x4284253CUL))
#define bFM4_USB0_EP1C_EPEN                       *((volatile  uint16_t*)(0x4284253CUL))

#define bFM_USB0_EP1S_SPK                         *((volatile  uint16_t*)(0x428429A4UL))
#define bFM4_USB0_EP1S_SPK                        *((volatile  uint16_t*)(0x428429A4UL))
#define bFM_USB0_EP1S_DRQ                         *((volatile  uint16_t*)(0x428429A8UL))
#define bFM4_USB0_EP1S_DRQ                        *((volatile  uint16_t*)(0x428429A8UL))
#define bFM_USB0_EP1S_BUSY                        *((volatile  uint16_t*)(0x428429ACUL))
#define bFM4_USB0_EP1S_BUSY                       *((volatile  uint16_t*)(0x428429ACUL))
#define bFM_USB0_EP1S_SPKIE                       *((volatile  uint16_t*)(0x428429B4UL))
#define bFM4_USB0_EP1S_SPKIE                      *((volatile  uint16_t*)(0x428429B4UL))
#define bFM_USB0_EP1S_DRQIE                       *((volatile  uint16_t*)(0x428429B8UL))
#define bFM4_USB0_EP1S_DRQIE                      *((volatile  uint16_t*)(0x428429B8UL))
#define bFM_USB0_EP1S_BFINI                       *((volatile  uint16_t*)(0x428429BCUL))
#define bFM4_USB0_EP1S_BFINI                      *((volatile  uint16_t*)(0x428429BCUL))

#define bFM_USB0_EP2C_STAL                        *((volatile  uint16_t*)(0x428425A4UL))
#define bFM4_USB0_EP2C_STAL                       *((volatile  uint16_t*)(0x428425A4UL))
#define bFM_USB0_EP2C_NULE                        *((volatile  uint16_t*)(0x428425A8UL))
#define bFM4_USB0_EP2C_NULE                       *((volatile  uint16_t*)(0x428425A8UL))
#define bFM_USB0_EP2C_DMAE                        *((volatile  uint16_t*)(0x428425ACUL))
#define bFM4_USB0_EP2C_DMAE                       *((volatile  uint16_t*)(0x428425ACUL))
#define bFM_USB0_EP2C_DIR                         *((volatile  uint16_t*)(0x428425B0UL))
#define bFM4_USB0_EP2C_DIR                        *((volatile  uint16_t*)(0x428425B0UL))
#define bFM_USB0_EP2C_EPEN                        *((volatile  uint16_t*)(0x428425BCUL))
#define bFM4_USB0_EP2C_EPEN                       *((volatile  uint16_t*)(0x428425BCUL))

#define bFM_USB0_EP2S_SPK                         *((volatile  uint16_t*)(0x42842A24UL))
#define bFM4_USB0_EP2S_SPK                        *((volatile  uint16_t*)(0x42842A24UL))
#define bFM_USB0_EP2S_DRQ                         *((volatile  uint16_t*)(0x42842A28UL))
#define bFM4_USB0_EP2S_DRQ                        *((volatile  uint16_t*)(0x42842A28UL))
#define bFM_USB0_EP2S_BUSY                        *((volatile  uint16_t*)(0x42842A2CUL))
#define bFM4_USB0_EP2S_BUSY                       *((volatile  uint16_t*)(0x42842A2CUL))
#define bFM_USB0_EP2S_SPKIE                       *((volatile  uint16_t*)(0x42842A34UL))
#define bFM4_USB0_EP2S_SPKIE                      *((volatile  uint16_t*)(0x42842A34UL))
#define bFM_USB0_EP2S_DRQIE                       *((volatile  uint16_t*)(0x42842A38UL))
#define bFM4_USB0_EP2S_DRQIE                      *((volatile  uint16_t*)(0x42842A38UL))
#define bFM_USB0_EP2S_BFINI                       *((volatile  uint16_t*)(0x42842A3CUL))
#define bFM4_USB0_EP2S_BFINI                      *((volatile  uint16_t*)(0x42842A3CUL))

#define bFM_USB0_EP3C_STAL                        *((volatile  uint16_t*)(0x42842624UL))
#define bFM4_USB0_EP3C_STAL                       *((volatile  uint16_t*)(0x42842624UL))
#define bFM_USB0_EP3C_NULE                        *((volatile  uint16_t*)(0x42842628UL))
#define bFM4_USB0_EP3C_NULE                       *((volatile  uint16_t*)(0x42842628UL))
#define bFM_USB0_EP3C_DMAE                        *((volatile  uint16_t*)(0x4284262CUL))
#define bFM4_USB0_EP3C_DMAE                       *((volatile  uint16_t*)(0x4284262CUL))
#define bFM_USB0_EP3C_DIR                         *((volatile  uint16_t*)(0x42842630UL))
#define bFM4_USB0_EP3C_DIR                        *((volatile  uint16_t*)(0x42842630UL))
#define bFM_USB0_EP3C_EPEN                        *((volatile  uint16_t*)(0x4284263CUL))
#define bFM4_USB0_EP3C_EPEN                       *((volatile  uint16_t*)(0x4284263CUL))

#define bFM_USB0_EP3S_SPK                         *((volatile  uint16_t*)(0x42842AA4UL))
#define bFM4_USB0_EP3S_SPK                        *((volatile  uint16_t*)(0x42842AA4UL))
#define bFM_USB0_EP3S_DRQ                         *((volatile  uint16_t*)(0x42842AA8UL))
#define bFM4_USB0_EP3S_DRQ                        *((volatile  uint16_t*)(0x42842AA8UL))
#define bFM_USB0_EP3S_BUSY                        *((volatile  uint16_t*)(0x42842AACUL))
#define bFM4_USB0_EP3S_BUSY                       *((volatile  uint16_t*)(0x42842AACUL))
#define bFM_USB0_EP3S_SPKIE                       *((volatile  uint16_t*)(0x42842AB4UL))
#define bFM4_USB0_EP3S_SPKIE                      *((volatile  uint16_t*)(0x42842AB4UL))
#define bFM_USB0_EP3S_DRQIE                       *((volatile  uint16_t*)(0x42842AB8UL))
#define bFM4_USB0_EP3S_DRQIE                      *((volatile  uint16_t*)(0x42842AB8UL))
#define bFM_USB0_EP3S_BFINI                       *((volatile  uint16_t*)(0x42842ABCUL))
#define bFM4_USB0_EP3S_BFINI                      *((volatile  uint16_t*)(0x42842ABCUL))

#define bFM_USB0_EP4C_STAL                        *((volatile  uint16_t*)(0x428426A4UL))
#define bFM4_USB0_EP4C_STAL                       *((volatile  uint16_t*)(0x428426A4UL))
#define bFM_USB0_EP4C_NULE                        *((volatile  uint16_t*)(0x428426A8UL))
#define bFM4_USB0_EP4C_NULE                       *((volatile  uint16_t*)(0x428426A8UL))
#define bFM_USB0_EP4C_DMAE                        *((volatile  uint16_t*)(0x428426ACUL))
#define bFM4_USB0_EP4C_DMAE                       *((volatile  uint16_t*)(0x428426ACUL))
#define bFM_USB0_EP4C_DIR                         *((volatile  uint16_t*)(0x428426B0UL))
#define bFM4_USB0_EP4C_DIR                        *((volatile  uint16_t*)(0x428426B0UL))
#define bFM_USB0_EP4C_EPEN                        *((volatile  uint16_t*)(0x428426BCUL))
#define bFM4_USB0_EP4C_EPEN                       *((volatile  uint16_t*)(0x428426BCUL))

#define bFM_USB0_EP4S_SPK                         *((volatile  uint16_t*)(0x42842B24UL))
#define bFM4_USB0_EP4S_SPK                        *((volatile  uint16_t*)(0x42842B24UL))
#define bFM_USB0_EP4S_DRQ                         *((volatile  uint16_t*)(0x42842B28UL))
#define bFM4_USB0_EP4S_DRQ                        *((volatile  uint16_t*)(0x42842B28UL))
#define bFM_USB0_EP4S_BUSY                        *((volatile  uint16_t*)(0x42842B2CUL))
#define bFM4_USB0_EP4S_BUSY                       *((volatile  uint16_t*)(0x42842B2CUL))
#define bFM_USB0_EP4S_SPKIE                       *((volatile  uint16_t*)(0x42842B34UL))
#define bFM4_USB0_EP4S_SPKIE                      *((volatile  uint16_t*)(0x42842B34UL))
#define bFM_USB0_EP4S_DRQIE                       *((volatile  uint16_t*)(0x42842B38UL))
#define bFM4_USB0_EP4S_DRQIE                      *((volatile  uint16_t*)(0x42842B38UL))
#define bFM_USB0_EP4S_BFINI                       *((volatile  uint16_t*)(0x42842B3CUL))
#define bFM4_USB0_EP4S_BFINI                      *((volatile  uint16_t*)(0x42842B3CUL))

#define bFM_USB0_EP5C_STAL                        *((volatile  uint16_t*)(0x42842724UL))
#define bFM4_USB0_EP5C_STAL                       *((volatile  uint16_t*)(0x42842724UL))
#define bFM_USB0_EP5C_NULE                        *((volatile  uint16_t*)(0x42842728UL))
#define bFM4_USB0_EP5C_NULE                       *((volatile  uint16_t*)(0x42842728UL))
#define bFM_USB0_EP5C_DMAE                        *((volatile  uint16_t*)(0x4284272CUL))
#define bFM4_USB0_EP5C_DMAE                       *((volatile  uint16_t*)(0x4284272CUL))
#define bFM_USB0_EP5C_DIR                         *((volatile  uint16_t*)(0x42842730UL))
#define bFM4_USB0_EP5C_DIR                        *((volatile  uint16_t*)(0x42842730UL))
#define bFM_USB0_EP5C_EPEN                        *((volatile  uint16_t*)(0x4284273CUL))
#define bFM4_USB0_EP5C_EPEN                       *((volatile  uint16_t*)(0x4284273CUL))

#define bFM_USB0_EP5S_SPK                         *((volatile  uint16_t*)(0x42842BA4UL))
#define bFM4_USB0_EP5S_SPK                        *((volatile  uint16_t*)(0x42842BA4UL))
#define bFM_USB0_EP5S_DRQ                         *((volatile  uint16_t*)(0x42842BA8UL))
#define bFM4_USB0_EP5S_DRQ                        *((volatile  uint16_t*)(0x42842BA8UL))
#define bFM_USB0_EP5S_BUSY                        *((volatile  uint16_t*)(0x42842BACUL))
#define bFM4_USB0_EP5S_BUSY                       *((volatile  uint16_t*)(0x42842BACUL))
#define bFM_USB0_EP5S_SPKIE                       *((volatile  uint16_t*)(0x42842BB4UL))
#define bFM4_USB0_EP5S_SPKIE                      *((volatile  uint16_t*)(0x42842BB4UL))
#define bFM_USB0_EP5S_DRQIE                       *((volatile  uint16_t*)(0x42842BB8UL))
#define bFM4_USB0_EP5S_DRQIE                      *((volatile  uint16_t*)(0x42842BB8UL))
#define bFM_USB0_EP5S_BFINI                       *((volatile  uint16_t*)(0x42842BBCUL))
#define bFM4_USB0_EP5S_BFINI                      *((volatile  uint16_t*)(0x42842BBCUL))

#define bFM_USB0_HCNT_HOST                        *((volatile  uint8_t *)(0x42842000UL))
#define bFM4_USB0_HCNT_HOST                       *((volatile  uint8_t *)(0x42842000UL))
#define bFM_USB0_HCNT_URST                        *((volatile  uint8_t *)(0x42842004UL))
#define bFM4_USB0_HCNT_URST                       *((volatile  uint8_t *)(0x42842004UL))
#define bFM_USB0_HCNT_SOFIRE                      *((volatile  uint8_t *)(0x42842008UL))
#define bFM4_USB0_HCNT_SOFIRE                     *((volatile  uint8_t *)(0x42842008UL))
#define bFM_USB0_HCNT_DIRE                        *((volatile  uint8_t *)(0x4284200CUL))
#define bFM4_USB0_HCNT_DIRE                       *((volatile  uint8_t *)(0x4284200CUL))
#define bFM_USB0_HCNT_CNNIRE                      *((volatile  uint8_t *)(0x42842010UL))
#define bFM4_USB0_HCNT_CNNIRE                     *((volatile  uint8_t *)(0x42842010UL))
#define bFM_USB0_HCNT_CMPIRE                      *((volatile  uint8_t *)(0x42842014UL))
#define bFM4_USB0_HCNT_CMPIRE                     *((volatile  uint8_t *)(0x42842014UL))
#define bFM_USB0_HCNT_URIRE                       *((volatile  uint8_t *)(0x42842018UL))
#define bFM4_USB0_HCNT_URIRE                      *((volatile  uint8_t *)(0x42842018UL))
#define bFM_USB0_HCNT_RWKIRE                      *((volatile  uint8_t *)(0x4284201CUL))
#define bFM4_USB0_HCNT_RWKIRE                     *((volatile  uint8_t *)(0x4284201CUL))
#define bFM_USB0_HCNT_RETRY                       *((volatile  uint8_t *)(0x42842020UL))
#define bFM4_USB0_HCNT_RETRY                      *((volatile  uint8_t *)(0x42842020UL))
#define bFM_USB0_HCNT_CANCEL                      *((volatile  uint8_t *)(0x42842024UL))
#define bFM4_USB0_HCNT_CANCEL                     *((volatile  uint8_t *)(0x42842024UL))
#define bFM_USB0_HCNT_SOFSTEP                     *((volatile  uint8_t *)(0x42842028UL))
#define bFM4_USB0_HCNT_SOFSTEP                    *((volatile  uint8_t *)(0x42842028UL))

#define bFM_USB0_HERR_STUFF                       *((volatile  uint8_t *)(0x428420A8UL))
#define bFM4_USB0_HERR_STUFF                      *((volatile  uint8_t *)(0x428420A8UL))
#define bFM_USB0_HERR_TGERR                       *((volatile  uint8_t *)(0x428420ACUL))
#define bFM4_USB0_HERR_TGERR                      *((volatile  uint8_t *)(0x428420ACUL))
#define bFM_USB0_HERR_CRC                         *((volatile  uint8_t *)(0x428420B0UL))
#define bFM4_USB0_HERR_CRC                        *((volatile  uint8_t *)(0x428420B0UL))
#define bFM_USB0_HERR_TOUT                        *((volatile  uint8_t *)(0x428420B4UL))
#define bFM4_USB0_HERR_TOUT                       *((volatile  uint8_t *)(0x428420B4UL))
#define bFM_USB0_HERR_RERR                        *((volatile  uint8_t *)(0x428420B8UL))
#define bFM4_USB0_HERR_RERR                       *((volatile  uint8_t *)(0x428420B8UL))
#define bFM_USB0_HERR_LSTSOF                      *((volatile  uint8_t *)(0x428420BCUL))
#define bFM4_USB0_HERR_LSTSOF                     *((volatile  uint8_t *)(0x428420BCUL))

#define bFM_USB0_HIRQ_SOFIRQ                      *((volatile  uint8_t *)(0x42842080UL))
#define bFM4_USB0_HIRQ_SOFIRQ                     *((volatile  uint8_t *)(0x42842080UL))
#define bFM_USB0_HIRQ_DIRQ                        *((volatile  uint8_t *)(0x42842084UL))
#define bFM4_USB0_HIRQ_DIRQ                       *((volatile  uint8_t *)(0x42842084UL))
#define bFM_USB0_HIRQ_CNNIRQ                      *((volatile  uint8_t *)(0x42842088UL))
#define bFM4_USB0_HIRQ_CNNIRQ                     *((volatile  uint8_t *)(0x42842088UL))
#define bFM_USB0_HIRQ_CMPIRQ                      *((volatile  uint8_t *)(0x4284208CUL))
#define bFM4_USB0_HIRQ_CMPIRQ                     *((volatile  uint8_t *)(0x4284208CUL))
#define bFM_USB0_HIRQ_URIRQ                       *((volatile  uint8_t *)(0x42842090UL))
#define bFM4_USB0_HIRQ_URIRQ                      *((volatile  uint8_t *)(0x42842090UL))
#define bFM_USB0_HIRQ_RWKIRQ                      *((volatile  uint8_t *)(0x42842094UL))
#define bFM4_USB0_HIRQ_RWKIRQ                     *((volatile  uint8_t *)(0x42842094UL))
#define bFM_USB0_HIRQ_TCAN                        *((volatile  uint8_t *)(0x4284209CUL))
#define bFM4_USB0_HIRQ_TCAN                       *((volatile  uint8_t *)(0x4284209CUL))

#define bFM_USB0_HSTATE_CSTAT                     *((volatile  uint8_t *)(0x42842100UL))
#define bFM4_USB0_HSTATE_CSTAT                    *((volatile  uint8_t *)(0x42842100UL))
#define bFM_USB0_HSTATE_TMODE                     *((volatile  uint8_t *)(0x42842104UL))
#define bFM4_USB0_HSTATE_TMODE                    *((volatile  uint8_t *)(0x42842104UL))
#define bFM_USB0_HSTATE_SUSP                      *((volatile  uint8_t *)(0x42842108UL))
#define bFM4_USB0_HSTATE_SUSP                     *((volatile  uint8_t *)(0x42842108UL))
#define bFM_USB0_HSTATE_SOFBUSY                   *((volatile  uint8_t *)(0x4284210CUL))
#define bFM4_USB0_HSTATE_SOFBUSY                  *((volatile  uint8_t *)(0x4284210CUL))
#define bFM_USB0_HSTATE_CLKSEL                    *((volatile  uint8_t *)(0x42842110UL))
#define bFM4_USB0_HSTATE_CLKSEL                   *((volatile  uint8_t *)(0x42842110UL))
#define bFM_USB0_HSTATE_ALIVE                     *((volatile  uint8_t *)(0x42842114UL))
#define bFM4_USB0_HSTATE_ALIVE                    *((volatile  uint8_t *)(0x42842114UL))

#define bFM_USB0_HTOKEN_TGGL                      *((volatile  uint8_t *)(0x4284239CUL))
#define bFM4_USB0_HTOKEN_TGGL                     *((volatile  uint8_t *)(0x4284239CUL))

#define bFM_USB0_UDCC_PWC                         *((volatile  uint8_t *)(0x42842400UL))
#define bFM4_USB0_UDCC_PWC                        *((volatile  uint8_t *)(0x42842400UL))
#define bFM_USB0_UDCC_RFBK                        *((volatile  uint8_t *)(0x42842404UL))
#define bFM4_USB0_UDCC_RFBK                       *((volatile  uint8_t *)(0x42842404UL))
#define bFM_USB0_UDCC_STALCLREN                   *((volatile  uint8_t *)(0x4284240CUL))
#define bFM4_USB0_UDCC_STALCLREN                  *((volatile  uint8_t *)(0x4284240CUL))
#define bFM_USB0_UDCC_USTP                        *((volatile  uint8_t *)(0x42842410UL))
#define bFM4_USB0_UDCC_USTP                       *((volatile  uint8_t *)(0x42842410UL))
#define bFM_USB0_UDCC_HCONX                       *((volatile  uint8_t *)(0x42842414UL))
#define bFM4_USB0_UDCC_HCONX                      *((volatile  uint8_t *)(0x42842414UL))
#define bFM_USB0_UDCC_RESUM                       *((volatile  uint8_t *)(0x42842418UL))
#define bFM4_USB0_UDCC_RESUM                      *((volatile  uint8_t *)(0x42842418UL))
#define bFM_USB0_UDCC_RST                         *((volatile  uint8_t *)(0x4284241CUL))
#define bFM4_USB0_UDCC_RST                        *((volatile  uint8_t *)(0x4284241CUL))

#define bFM_USB0_UDCIE_CONFIE                     *((volatile  uint8_t *)(0x42842820UL))
#define bFM4_USB0_UDCIE_CONFIE                    *((volatile  uint8_t *)(0x42842820UL))
#define bFM_USB0_UDCIE_CONFN                      *((volatile  uint8_t *)(0x42842824UL))
#define bFM4_USB0_UDCIE_CONFN                     *((volatile  uint8_t *)(0x42842824UL))
#define bFM_USB0_UDCIE_WKUPIE                     *((volatile  uint8_t *)(0x42842828UL))
#define bFM4_USB0_UDCIE_WKUPIE                    *((volatile  uint8_t *)(0x42842828UL))
#define bFM_USB0_UDCIE_BRSTIE                     *((volatile  uint8_t *)(0x4284282CUL))
#define bFM4_USB0_UDCIE_BRSTIE                    *((volatile  uint8_t *)(0x4284282CUL))
#define bFM_USB0_UDCIE_SOFIE                      *((volatile  uint8_t *)(0x42842830UL))
#define bFM4_USB0_UDCIE_SOFIE                     *((volatile  uint8_t *)(0x42842830UL))
#define bFM_USB0_UDCIE_SUSPIE                     *((volatile  uint8_t *)(0x42842834UL))
#define bFM4_USB0_UDCIE_SUSPIE                    *((volatile  uint8_t *)(0x42842834UL))

#define bFM_USB0_UDCS_CONF                        *((volatile  uint8_t *)(0x42842800UL))
#define bFM4_USB0_UDCS_CONF                       *((volatile  uint8_t *)(0x42842800UL))
#define bFM_USB0_UDCS_SETP                        *((volatile  uint8_t *)(0x42842804UL))
#define bFM4_USB0_UDCS_SETP                       *((volatile  uint8_t *)(0x42842804UL))
#define bFM_USB0_UDCS_WKUP                        *((volatile  uint8_t *)(0x42842808UL))
#define bFM4_USB0_UDCS_WKUP                       *((volatile  uint8_t *)(0x42842808UL))
#define bFM_USB0_UDCS_BRST                        *((volatile  uint8_t *)(0x4284280CUL))
#define bFM4_USB0_UDCS_BRST                       *((volatile  uint8_t *)(0x4284280CUL))
#define bFM_USB0_UDCS_SOF                         *((volatile  uint8_t *)(0x42842810UL))
#define bFM4_USB0_UDCS_SOF                        *((volatile  uint8_t *)(0x42842810UL))
#define bFM_USB0_UDCS_SUSP                        *((volatile  uint8_t *)(0x42842814UL))
#define bFM4_USB0_UDCS_SUSP                       *((volatile  uint8_t *)(0x42842814UL))


/*******************************************************************************
* USB Registers USB1
*   Bitband Section
*******************************************************************************/
#define bFM_USB1_EP0C_STAL                        *((volatile  uint16_t*)(0x42A844A4UL))
#define bFM4_USB1_EP0C_STAL                       *((volatile  uint16_t*)(0x42A844A4UL))

#define bFM_USB1_EP0IS_DRQI                       *((volatile  uint16_t*)(0x42A848A8UL))
#define bFM4_USB1_EP0IS_DRQI                      *((volatile  uint16_t*)(0x42A848A8UL))
#define bFM_USB1_EP0IS_DRQIIE                     *((volatile  uint16_t*)(0x42A848B8UL))
#define bFM4_USB1_EP0IS_DRQIIE                    *((volatile  uint16_t*)(0x42A848B8UL))
#define bFM_USB1_EP0IS_BFINI                      *((volatile  uint16_t*)(0x42A848BCUL))
#define bFM4_USB1_EP0IS_BFINI                     *((volatile  uint16_t*)(0x42A848BCUL))

#define bFM_USB1_EP0OS_SPK                        *((volatile  uint16_t*)(0x42A84924UL))
#define bFM4_USB1_EP0OS_SPK                       *((volatile  uint16_t*)(0x42A84924UL))
#define bFM_USB1_EP0OS_DRQO                       *((volatile  uint16_t*)(0x42A84928UL))
#define bFM4_USB1_EP0OS_DRQO                      *((volatile  uint16_t*)(0x42A84928UL))
#define bFM_USB1_EP0OS_SPKIE                      *((volatile  uint16_t*)(0x42A84934UL))
#define bFM4_USB1_EP0OS_SPKIE                     *((volatile  uint16_t*)(0x42A84934UL))
#define bFM_USB1_EP0OS_DRQOIE                     *((volatile  uint16_t*)(0x42A84938UL))
#define bFM4_USB1_EP0OS_DRQOIE                    *((volatile  uint16_t*)(0x42A84938UL))
#define bFM_USB1_EP0OS_BFINI                      *((volatile  uint16_t*)(0x42A8493CUL))
#define bFM4_USB1_EP0OS_BFINI                     *((volatile  uint16_t*)(0x42A8493CUL))

#define bFM_USB1_EP1C_STAL                        *((volatile  uint16_t*)(0x42A84524UL))
#define bFM4_USB1_EP1C_STAL                       *((volatile  uint16_t*)(0x42A84524UL))
#define bFM_USB1_EP1C_NULE                        *((volatile  uint16_t*)(0x42A84528UL))
#define bFM4_USB1_EP1C_NULE                       *((volatile  uint16_t*)(0x42A84528UL))
#define bFM_USB1_EP1C_DMAE                        *((volatile  uint16_t*)(0x42A8452CUL))
#define bFM4_USB1_EP1C_DMAE                       *((volatile  uint16_t*)(0x42A8452CUL))
#define bFM_USB1_EP1C_DIR                         *((volatile  uint16_t*)(0x42A84530UL))
#define bFM4_USB1_EP1C_DIR                        *((volatile  uint16_t*)(0x42A84530UL))
#define bFM_USB1_EP1C_EPEN                        *((volatile  uint16_t*)(0x42A8453CUL))
#define bFM4_USB1_EP1C_EPEN                       *((volatile  uint16_t*)(0x42A8453CUL))

#define bFM_USB1_EP1S_SPK                         *((volatile  uint16_t*)(0x42A849A4UL))
#define bFM4_USB1_EP1S_SPK                        *((volatile  uint16_t*)(0x42A849A4UL))
#define bFM_USB1_EP1S_DRQ                         *((volatile  uint16_t*)(0x42A849A8UL))
#define bFM4_USB1_EP1S_DRQ                        *((volatile  uint16_t*)(0x42A849A8UL))
#define bFM_USB1_EP1S_BUSY                        *((volatile  uint16_t*)(0x42A849ACUL))
#define bFM4_USB1_EP1S_BUSY                       *((volatile  uint16_t*)(0x42A849ACUL))
#define bFM_USB1_EP1S_SPKIE                       *((volatile  uint16_t*)(0x42A849B4UL))
#define bFM4_USB1_EP1S_SPKIE                      *((volatile  uint16_t*)(0x42A849B4UL))
#define bFM_USB1_EP1S_DRQIE                       *((volatile  uint16_t*)(0x42A849B8UL))
#define bFM4_USB1_EP1S_DRQIE                      *((volatile  uint16_t*)(0x42A849B8UL))
#define bFM_USB1_EP1S_BFINI                       *((volatile  uint16_t*)(0x42A849BCUL))
#define bFM4_USB1_EP1S_BFINI                      *((volatile  uint16_t*)(0x42A849BCUL))

#define bFM_USB1_EP2C_STAL                        *((volatile  uint16_t*)(0x42A845A4UL))
#define bFM4_USB1_EP2C_STAL                       *((volatile  uint16_t*)(0x42A845A4UL))
#define bFM_USB1_EP2C_NULE                        *((volatile  uint16_t*)(0x42A845A8UL))
#define bFM4_USB1_EP2C_NULE                       *((volatile  uint16_t*)(0x42A845A8UL))
#define bFM_USB1_EP2C_DMAE                        *((volatile  uint16_t*)(0x42A845ACUL))
#define bFM4_USB1_EP2C_DMAE                       *((volatile  uint16_t*)(0x42A845ACUL))
#define bFM_USB1_EP2C_DIR                         *((volatile  uint16_t*)(0x42A845B0UL))
#define bFM4_USB1_EP2C_DIR                        *((volatile  uint16_t*)(0x42A845B0UL))
#define bFM_USB1_EP2C_EPEN                        *((volatile  uint16_t*)(0x42A845BCUL))
#define bFM4_USB1_EP2C_EPEN                       *((volatile  uint16_t*)(0x42A845BCUL))

#define bFM_USB1_EP2S_SPK                         *((volatile  uint16_t*)(0x42A84A24UL))
#define bFM4_USB1_EP2S_SPK                        *((volatile  uint16_t*)(0x42A84A24UL))
#define bFM_USB1_EP2S_DRQ                         *((volatile  uint16_t*)(0x42A84A28UL))
#define bFM4_USB1_EP2S_DRQ                        *((volatile  uint16_t*)(0x42A84A28UL))
#define bFM_USB1_EP2S_BUSY                        *((volatile  uint16_t*)(0x42A84A2CUL))
#define bFM4_USB1_EP2S_BUSY                       *((volatile  uint16_t*)(0x42A84A2CUL))
#define bFM_USB1_EP2S_SPKIE                       *((volatile  uint16_t*)(0x42A84A34UL))
#define bFM4_USB1_EP2S_SPKIE                      *((volatile  uint16_t*)(0x42A84A34UL))
#define bFM_USB1_EP2S_DRQIE                       *((volatile  uint16_t*)(0x42A84A38UL))
#define bFM4_USB1_EP2S_DRQIE                      *((volatile  uint16_t*)(0x42A84A38UL))
#define bFM_USB1_EP2S_BFINI                       *((volatile  uint16_t*)(0x42A84A3CUL))
#define bFM4_USB1_EP2S_BFINI                      *((volatile  uint16_t*)(0x42A84A3CUL))

#define bFM_USB1_EP3C_STAL                        *((volatile  uint16_t*)(0x42A84624UL))
#define bFM4_USB1_EP3C_STAL                       *((volatile  uint16_t*)(0x42A84624UL))
#define bFM_USB1_EP3C_NULE                        *((volatile  uint16_t*)(0x42A84628UL))
#define bFM4_USB1_EP3C_NULE                       *((volatile  uint16_t*)(0x42A84628UL))
#define bFM_USB1_EP3C_DMAE                        *((volatile  uint16_t*)(0x42A8462CUL))
#define bFM4_USB1_EP3C_DMAE                       *((volatile  uint16_t*)(0x42A8462CUL))
#define bFM_USB1_EP3C_DIR                         *((volatile  uint16_t*)(0x42A84630UL))
#define bFM4_USB1_EP3C_DIR                        *((volatile  uint16_t*)(0x42A84630UL))
#define bFM_USB1_EP3C_EPEN                        *((volatile  uint16_t*)(0x42A8463CUL))
#define bFM4_USB1_EP3C_EPEN                       *((volatile  uint16_t*)(0x42A8463CUL))

#define bFM_USB1_EP3S_SPK                         *((volatile  uint16_t*)(0x42A84AA4UL))
#define bFM4_USB1_EP3S_SPK                        *((volatile  uint16_t*)(0x42A84AA4UL))
#define bFM_USB1_EP3S_DRQ                         *((volatile  uint16_t*)(0x42A84AA8UL))
#define bFM4_USB1_EP3S_DRQ                        *((volatile  uint16_t*)(0x42A84AA8UL))
#define bFM_USB1_EP3S_BUSY                        *((volatile  uint16_t*)(0x42A84AACUL))
#define bFM4_USB1_EP3S_BUSY                       *((volatile  uint16_t*)(0x42A84AACUL))
#define bFM_USB1_EP3S_SPKIE                       *((volatile  uint16_t*)(0x42A84AB4UL))
#define bFM4_USB1_EP3S_SPKIE                      *((volatile  uint16_t*)(0x42A84AB4UL))
#define bFM_USB1_EP3S_DRQIE                       *((volatile  uint16_t*)(0x42A84AB8UL))
#define bFM4_USB1_EP3S_DRQIE                      *((volatile  uint16_t*)(0x42A84AB8UL))
#define bFM_USB1_EP3S_BFINI                       *((volatile  uint16_t*)(0x42A84ABCUL))
#define bFM4_USB1_EP3S_BFINI                      *((volatile  uint16_t*)(0x42A84ABCUL))

#define bFM_USB1_EP4C_STAL                        *((volatile  uint16_t*)(0x42A846A4UL))
#define bFM4_USB1_EP4C_STAL                       *((volatile  uint16_t*)(0x42A846A4UL))
#define bFM_USB1_EP4C_NULE                        *((volatile  uint16_t*)(0x42A846A8UL))
#define bFM4_USB1_EP4C_NULE                       *((volatile  uint16_t*)(0x42A846A8UL))
#define bFM_USB1_EP4C_DMAE                        *((volatile  uint16_t*)(0x42A846ACUL))
#define bFM4_USB1_EP4C_DMAE                       *((volatile  uint16_t*)(0x42A846ACUL))
#define bFM_USB1_EP4C_DIR                         *((volatile  uint16_t*)(0x42A846B0UL))
#define bFM4_USB1_EP4C_DIR                        *((volatile  uint16_t*)(0x42A846B0UL))
#define bFM_USB1_EP4C_EPEN                        *((volatile  uint16_t*)(0x42A846BCUL))
#define bFM4_USB1_EP4C_EPEN                       *((volatile  uint16_t*)(0x42A846BCUL))

#define bFM_USB1_EP4S_SPK                         *((volatile  uint16_t*)(0x42A84B24UL))
#define bFM4_USB1_EP4S_SPK                        *((volatile  uint16_t*)(0x42A84B24UL))
#define bFM_USB1_EP4S_DRQ                         *((volatile  uint16_t*)(0x42A84B28UL))
#define bFM4_USB1_EP4S_DRQ                        *((volatile  uint16_t*)(0x42A84B28UL))
#define bFM_USB1_EP4S_BUSY                        *((volatile  uint16_t*)(0x42A84B2CUL))
#define bFM4_USB1_EP4S_BUSY                       *((volatile  uint16_t*)(0x42A84B2CUL))
#define bFM_USB1_EP4S_SPKIE                       *((volatile  uint16_t*)(0x42A84B34UL))
#define bFM4_USB1_EP4S_SPKIE                      *((volatile  uint16_t*)(0x42A84B34UL))
#define bFM_USB1_EP4S_DRQIE                       *((volatile  uint16_t*)(0x42A84B38UL))
#define bFM4_USB1_EP4S_DRQIE                      *((volatile  uint16_t*)(0x42A84B38UL))
#define bFM_USB1_EP4S_BFINI                       *((volatile  uint16_t*)(0x42A84B3CUL))
#define bFM4_USB1_EP4S_BFINI                      *((volatile  uint16_t*)(0x42A84B3CUL))

#define bFM_USB1_EP5C_STAL                        *((volatile  uint16_t*)(0x42A84724UL))
#define bFM4_USB1_EP5C_STAL                       *((volatile  uint16_t*)(0x42A84724UL))
#define bFM_USB1_EP5C_NULE                        *((volatile  uint16_t*)(0x42A84728UL))
#define bFM4_USB1_EP5C_NULE                       *((volatile  uint16_t*)(0x42A84728UL))
#define bFM_USB1_EP5C_DMAE                        *((volatile  uint16_t*)(0x42A8472CUL))
#define bFM4_USB1_EP5C_DMAE                       *((volatile  uint16_t*)(0x42A8472CUL))
#define bFM_USB1_EP5C_DIR                         *((volatile  uint16_t*)(0x42A84730UL))
#define bFM4_USB1_EP5C_DIR                        *((volatile  uint16_t*)(0x42A84730UL))
#define bFM_USB1_EP5C_EPEN                        *((volatile  uint16_t*)(0x42A8473CUL))
#define bFM4_USB1_EP5C_EPEN                       *((volatile  uint16_t*)(0x42A8473CUL))

#define bFM_USB1_EP5S_SPK                         *((volatile  uint16_t*)(0x42A84BA4UL))
#define bFM4_USB1_EP5S_SPK                        *((volatile  uint16_t*)(0x42A84BA4UL))
#define bFM_USB1_EP5S_DRQ                         *((volatile  uint16_t*)(0x42A84BA8UL))
#define bFM4_USB1_EP5S_DRQ                        *((volatile  uint16_t*)(0x42A84BA8UL))
#define bFM_USB1_EP5S_BUSY                        *((volatile  uint16_t*)(0x42A84BACUL))
#define bFM4_USB1_EP5S_BUSY                       *((volatile  uint16_t*)(0x42A84BACUL))
#define bFM_USB1_EP5S_SPKIE                       *((volatile  uint16_t*)(0x42A84BB4UL))
#define bFM4_USB1_EP5S_SPKIE                      *((volatile  uint16_t*)(0x42A84BB4UL))
#define bFM_USB1_EP5S_DRQIE                       *((volatile  uint16_t*)(0x42A84BB8UL))
#define bFM4_USB1_EP5S_DRQIE                      *((volatile  uint16_t*)(0x42A84BB8UL))
#define bFM_USB1_EP5S_BFINI                       *((volatile  uint16_t*)(0x42A84BBCUL))
#define bFM4_USB1_EP5S_BFINI                      *((volatile  uint16_t*)(0x42A84BBCUL))

#define bFM_USB1_HCNT_HOST                        *((volatile  uint8_t *)(0x42A84000UL))
#define bFM4_USB1_HCNT_HOST                       *((volatile  uint8_t *)(0x42A84000UL))
#define bFM_USB1_HCNT_URST                        *((volatile  uint8_t *)(0x42A84004UL))
#define bFM4_USB1_HCNT_URST                       *((volatile  uint8_t *)(0x42A84004UL))
#define bFM_USB1_HCNT_SOFIRE                      *((volatile  uint8_t *)(0x42A84008UL))
#define bFM4_USB1_HCNT_SOFIRE                     *((volatile  uint8_t *)(0x42A84008UL))
#define bFM_USB1_HCNT_DIRE                        *((volatile  uint8_t *)(0x42A8400CUL))
#define bFM4_USB1_HCNT_DIRE                       *((volatile  uint8_t *)(0x42A8400CUL))
#define bFM_USB1_HCNT_CNNIRE                      *((volatile  uint8_t *)(0x42A84010UL))
#define bFM4_USB1_HCNT_CNNIRE                     *((volatile  uint8_t *)(0x42A84010UL))
#define bFM_USB1_HCNT_CMPIRE                      *((volatile  uint8_t *)(0x42A84014UL))
#define bFM4_USB1_HCNT_CMPIRE                     *((volatile  uint8_t *)(0x42A84014UL))
#define bFM_USB1_HCNT_URIRE                       *((volatile  uint8_t *)(0x42A84018UL))
#define bFM4_USB1_HCNT_URIRE                      *((volatile  uint8_t *)(0x42A84018UL))
#define bFM_USB1_HCNT_RWKIRE                      *((volatile  uint8_t *)(0x42A8401CUL))
#define bFM4_USB1_HCNT_RWKIRE                     *((volatile  uint8_t *)(0x42A8401CUL))
#define bFM_USB1_HCNT_RETRY                       *((volatile  uint8_t *)(0x42A84020UL))
#define bFM4_USB1_HCNT_RETRY                      *((volatile  uint8_t *)(0x42A84020UL))
#define bFM_USB1_HCNT_CANCEL                      *((volatile  uint8_t *)(0x42A84024UL))
#define bFM4_USB1_HCNT_CANCEL                     *((volatile  uint8_t *)(0x42A84024UL))
#define bFM_USB1_HCNT_SOFSTEP                     *((volatile  uint8_t *)(0x42A84028UL))
#define bFM4_USB1_HCNT_SOFSTEP                    *((volatile  uint8_t *)(0x42A84028UL))

#define bFM_USB1_HERR_STUFF                       *((volatile  uint8_t *)(0x42A840A8UL))
#define bFM4_USB1_HERR_STUFF                      *((volatile  uint8_t *)(0x42A840A8UL))
#define bFM_USB1_HERR_TGERR                       *((volatile  uint8_t *)(0x42A840ACUL))
#define bFM4_USB1_HERR_TGERR                      *((volatile  uint8_t *)(0x42A840ACUL))
#define bFM_USB1_HERR_CRC                         *((volatile  uint8_t *)(0x42A840B0UL))
#define bFM4_USB1_HERR_CRC                        *((volatile  uint8_t *)(0x42A840B0UL))
#define bFM_USB1_HERR_TOUT                        *((volatile  uint8_t *)(0x42A840B4UL))
#define bFM4_USB1_HERR_TOUT                       *((volatile  uint8_t *)(0x42A840B4UL))
#define bFM_USB1_HERR_RERR                        *((volatile  uint8_t *)(0x42A840B8UL))
#define bFM4_USB1_HERR_RERR                       *((volatile  uint8_t *)(0x42A840B8UL))
#define bFM_USB1_HERR_LSTSOF                      *((volatile  uint8_t *)(0x42A840BCUL))
#define bFM4_USB1_HERR_LSTSOF                     *((volatile  uint8_t *)(0x42A840BCUL))

#define bFM_USB1_HIRQ_SOFIRQ                      *((volatile  uint8_t *)(0x42A84080UL))
#define bFM4_USB1_HIRQ_SOFIRQ                     *((volatile  uint8_t *)(0x42A84080UL))
#define bFM_USB1_HIRQ_DIRQ                        *((volatile  uint8_t *)(0x42A84084UL))
#define bFM4_USB1_HIRQ_DIRQ                       *((volatile  uint8_t *)(0x42A84084UL))
#define bFM_USB1_HIRQ_CNNIRQ                      *((volatile  uint8_t *)(0x42A84088UL))
#define bFM4_USB1_HIRQ_CNNIRQ                     *((volatile  uint8_t *)(0x42A84088UL))
#define bFM_USB1_HIRQ_CMPIRQ                      *((volatile  uint8_t *)(0x42A8408CUL))
#define bFM4_USB1_HIRQ_CMPIRQ                     *((volatile  uint8_t *)(0x42A8408CUL))
#define bFM_USB1_HIRQ_URIRQ                       *((volatile  uint8_t *)(0x42A84090UL))
#define bFM4_USB1_HIRQ_URIRQ                      *((volatile  uint8_t *)(0x42A84090UL))
#define bFM_USB1_HIRQ_RWKIRQ                      *((volatile  uint8_t *)(0x42A84094UL))
#define bFM4_USB1_HIRQ_RWKIRQ                     *((volatile  uint8_t *)(0x42A84094UL))
#define bFM_USB1_HIRQ_TCAN                        *((volatile  uint8_t *)(0x42A8409CUL))
#define bFM4_USB1_HIRQ_TCAN                       *((volatile  uint8_t *)(0x42A8409CUL))

#define bFM_USB1_HSTATE_CSTAT                     *((volatile  uint8_t *)(0x42A84100UL))
#define bFM4_USB1_HSTATE_CSTAT                    *((volatile  uint8_t *)(0x42A84100UL))
#define bFM_USB1_HSTATE_TMODE                     *((volatile  uint8_t *)(0x42A84104UL))
#define bFM4_USB1_HSTATE_TMODE                    *((volatile  uint8_t *)(0x42A84104UL))
#define bFM_USB1_HSTATE_SUSP                      *((volatile  uint8_t *)(0x42A84108UL))
#define bFM4_USB1_HSTATE_SUSP                     *((volatile  uint8_t *)(0x42A84108UL))
#define bFM_USB1_HSTATE_SOFBUSY                   *((volatile  uint8_t *)(0x42A8410CUL))
#define bFM4_USB1_HSTATE_SOFBUSY                  *((volatile  uint8_t *)(0x42A8410CUL))
#define bFM_USB1_HSTATE_CLKSEL                    *((volatile  uint8_t *)(0x42A84110UL))
#define bFM4_USB1_HSTATE_CLKSEL                   *((volatile  uint8_t *)(0x42A84110UL))
#define bFM_USB1_HSTATE_ALIVE                     *((volatile  uint8_t *)(0x42A84114UL))
#define bFM4_USB1_HSTATE_ALIVE                    *((volatile  uint8_t *)(0x42A84114UL))

#define bFM_USB1_HTOKEN_TGGL                      *((volatile  uint8_t *)(0x42A8439CUL))
#define bFM4_USB1_HTOKEN_TGGL                     *((volatile  uint8_t *)(0x42A8439CUL))

#define bFM_USB1_UDCC_PWC                         *((volatile  uint8_t *)(0x42A84400UL))
#define bFM4_USB1_UDCC_PWC                        *((volatile  uint8_t *)(0x42A84400UL))
#define bFM_USB1_UDCC_RFBK                        *((volatile  uint8_t *)(0x42A84404UL))
#define bFM4_USB1_UDCC_RFBK                       *((volatile  uint8_t *)(0x42A84404UL))
#define bFM_USB1_UDCC_STALCLREN                   *((volatile  uint8_t *)(0x42A8440CUL))
#define bFM4_USB1_UDCC_STALCLREN                  *((volatile  uint8_t *)(0x42A8440CUL))
#define bFM_USB1_UDCC_USTP                        *((volatile  uint8_t *)(0x42A84410UL))
#define bFM4_USB1_UDCC_USTP                       *((volatile  uint8_t *)(0x42A84410UL))
#define bFM_USB1_UDCC_HCONX                       *((volatile  uint8_t *)(0x42A84414UL))
#define bFM4_USB1_UDCC_HCONX                      *((volatile  uint8_t *)(0x42A84414UL))
#define bFM_USB1_UDCC_RESUM                       *((volatile  uint8_t *)(0x42A84418UL))
#define bFM4_USB1_UDCC_RESUM                      *((volatile  uint8_t *)(0x42A84418UL))
#define bFM_USB1_UDCC_RST                         *((volatile  uint8_t *)(0x42A8441CUL))
#define bFM4_USB1_UDCC_RST                        *((volatile  uint8_t *)(0x42A8441CUL))

#define bFM_USB1_UDCIE_CONFIE                     *((volatile  uint8_t *)(0x42A84820UL))
#define bFM4_USB1_UDCIE_CONFIE                    *((volatile  uint8_t *)(0x42A84820UL))
#define bFM_USB1_UDCIE_CONFN                      *((volatile  uint8_t *)(0x42A84824UL))
#define bFM4_USB1_UDCIE_CONFN                     *((volatile  uint8_t *)(0x42A84824UL))
#define bFM_USB1_UDCIE_WKUPIE                     *((volatile  uint8_t *)(0x42A84828UL))
#define bFM4_USB1_UDCIE_WKUPIE                    *((volatile  uint8_t *)(0x42A84828UL))
#define bFM_USB1_UDCIE_BRSTIE                     *((volatile  uint8_t *)(0x42A8482CUL))
#define bFM4_USB1_UDCIE_BRSTIE                    *((volatile  uint8_t *)(0x42A8482CUL))
#define bFM_USB1_UDCIE_SOFIE                      *((volatile  uint8_t *)(0x42A84830UL))
#define bFM4_USB1_UDCIE_SOFIE                     *((volatile  uint8_t *)(0x42A84830UL))
#define bFM_USB1_UDCIE_SUSPIE                     *((volatile  uint8_t *)(0x42A84834UL))
#define bFM4_USB1_UDCIE_SUSPIE                    *((volatile  uint8_t *)(0x42A84834UL))

#define bFM_USB1_UDCS_CONF                        *((volatile  uint8_t *)(0x42A84800UL))
#define bFM4_USB1_UDCS_CONF                       *((volatile  uint8_t *)(0x42A84800UL))
#define bFM_USB1_UDCS_SETP                        *((volatile  uint8_t *)(0x42A84804UL))
#define bFM4_USB1_UDCS_SETP                       *((volatile  uint8_t *)(0x42A84804UL))
#define bFM_USB1_UDCS_WKUP                        *((volatile  uint8_t *)(0x42A84808UL))
#define bFM4_USB1_UDCS_WKUP                       *((volatile  uint8_t *)(0x42A84808UL))
#define bFM_USB1_UDCS_BRST                        *((volatile  uint8_t *)(0x42A8480CUL))
#define bFM4_USB1_UDCS_BRST                       *((volatile  uint8_t *)(0x42A8480CUL))
#define bFM_USB1_UDCS_SOF                         *((volatile  uint8_t *)(0x42A84810UL))
#define bFM4_USB1_UDCS_SOF                        *((volatile  uint8_t *)(0x42A84810UL))
#define bFM_USB1_UDCS_SUSP                        *((volatile  uint8_t *)(0x42A84814UL))
#define bFM4_USB1_UDCS_SUSP                       *((volatile  uint8_t *)(0x42A84814UL))


/*******************************************************************************
* USBETHERCLK Registers USBETHERCLK
*   Bitband Section
*******************************************************************************/
#define bFM_USBETHERCLK_UCCR_UCEN0                *((volatile  uint8_t *)(0x426C0000UL))
#define bFM4_USBETHERCLK_UCCR_UCEN0               *((volatile  uint8_t *)(0x426C0000UL))
#define bFM_USBETHERCLK_UCCR_UCEN1                *((volatile  uint8_t *)(0x426C000CUL))
#define bFM4_USBETHERCLK_UCCR_UCEN1               *((volatile  uint8_t *)(0x426C000CUL))
#define bFM_USBETHERCLK_UCCR_ECEN                 *((volatile  uint8_t *)(0x426C0010UL))
#define bFM4_USBETHERCLK_UCCR_ECEN                *((volatile  uint8_t *)(0x426C0010UL))

#define bFM_USBETHERCLK_UP_STR_UPRDY              *((volatile  uint8_t *)(0x426C0280UL))
#define bFM4_USBETHERCLK_UP_STR_UPRDY             *((volatile  uint8_t *)(0x426C0280UL))

#define bFM_USBETHERCLK_UPCR1_UPLLEN              *((volatile  uint8_t *)(0x426C0080UL))
#define bFM4_USBETHERCLK_UPCR1_UPLLEN             *((volatile  uint8_t *)(0x426C0080UL))
#define bFM_USBETHERCLK_UPCR1_UPINC               *((volatile  uint8_t *)(0x426C0084UL))
#define bFM4_USBETHERCLK_UPCR1_UPINC              *((volatile  uint8_t *)(0x426C0084UL))

#define bFM_USBETHERCLK_UPCR7_EPLLEN              *((volatile  uint8_t *)(0x426C0580UL))
#define bFM4_USBETHERCLK_UPCR7_EPLLEN             *((volatile  uint8_t *)(0x426C0580UL))

#define bFM_USBETHERCLK_UPINT_CLR_UPCSC           *((volatile  uint8_t *)(0x426C0380UL))
#define bFM4_USBETHERCLK_UPINT_CLR_UPCSC          *((volatile  uint8_t *)(0x426C0380UL))

#define bFM_USBETHERCLK_UPINT_ENR_UPCSE           *((volatile  uint8_t *)(0x426C0300UL))
#define bFM4_USBETHERCLK_UPINT_ENR_UPCSE          *((volatile  uint8_t *)(0x426C0300UL))

#define bFM_USBETHERCLK_UPINT_STR_UPCSI           *((volatile  uint8_t *)(0x426C0400UL))
#define bFM4_USBETHERCLK_UPINT_STR_UPCSI          *((volatile  uint8_t *)(0x426C0400UL))

#define bFM_USBETHERCLK_USBEN0_USBEN0             *((volatile  uint8_t *)(0x426C0600UL))
#define bFM4_USBETHERCLK_USBEN0_USBEN0            *((volatile  uint8_t *)(0x426C0600UL))

#define bFM_USBETHERCLK_USBEN1_USBEN1             *((volatile  uint8_t *)(0x426C0680UL))
#define bFM4_USBETHERCLK_USBEN1_USBEN1            *((volatile  uint8_t *)(0x426C0680UL))


/*******************************************************************************
* WC Registers WC
*   Bitband Section
*******************************************************************************/
#define bFM_WC_CLK_EN_CLK_EN                      *((volatile  uint8_t *)(0x42740280UL))
#define bFM4_WC_CLK_EN_CLK_EN                     *((volatile  uint8_t *)(0x42740280UL))
#define bFM_WC_CLK_EN_CLK_EN_R                    *((volatile  uint8_t *)(0x42740284UL))
#define bFM4_WC_CLK_EN_CLK_EN_R                   *((volatile  uint8_t *)(0x42740284UL))

#define bFM_WC_WCCR_WCIF                          *((volatile  uint8_t *)(0x42740040UL))
#define bFM4_WC_WCCR_WCIF                         *((volatile  uint8_t *)(0x42740040UL))
#define bFM_WC_WCCR_WCIE                          *((volatile  uint8_t *)(0x42740044UL))
#define bFM4_WC_WCCR_WCIE                         *((volatile  uint8_t *)(0x42740044UL))
#define bFM_WC_WCCR_WCOP                          *((volatile  uint8_t *)(0x42740058UL))
#define bFM4_WC_WCCR_WCOP                         *((volatile  uint8_t *)(0x42740058UL))
#define bFM_WC_WCCR_WCEN                          *((volatile  uint8_t *)(0x4274005CUL))
#define bFM4_WC_WCCR_WCEN                         *((volatile  uint8_t *)(0x4274005CUL))


#if defined __cplusplus
}
#endif

#endif /* _S6E2CCXJ_H_ */
