
zephyr.elf:     file format elf32-littlearm


Disassembly of section rom_start:

00000000 <_vector_table>:
   0:	20 3c 00 20 05 23 00 00 43 5c 00 00 d9 22 00 00      <. .#..C\..."..
  10:	d9 22 00 00 d9 22 00 00 d9 22 00 00 00 00 00 00     ."..."..."......
	...
  2c:	5d 1e 00 00 d9 22 00 00 00 00 00 00 d9 22 00 00     ]...."......."..
  3c:	d9 22 00 00                                         ."..

00000040 <_irq_vector_table>:
  40:	d9 1e 00 00 d9 1e 00 00 d9 1e 00 00 d9 1e 00 00     ................
  50:	d9 1e 00 00 d9 1e 00 00 d9 1e 00 00 d9 1e 00 00     ................
  60:	d9 1e 00 00 d9 1e 00 00 d9 1e 00 00 d9 1e 00 00     ................
  70:	d9 1e 00 00 d9 1e 00 00 d9 1e 00 00 d9 1e 00 00     ................
  80:	d9 1e 00 00 d9 1e 00 00 d9 1e 00 00 d9 1e 00 00     ................
  90:	d9 1e 00 00 d9 1e 00 00 d9 1e 00 00 d9 1e 00 00     ................
  a0:	d9 1e 00 00 d9 1e 00 00 d9 1e 00 00 d9 1e 00 00     ................
  b0:	d9 1e 00 00 d9 1e 00 00 d9 1e 00 00 d9 1e 00 00     ................
  c0:	d9 1e 00 00 d9 1e 00 00 d9 1e 00 00 d9 1e 00 00     ................
  d0:	d9 1e 00 00 d9 1e 00 00 d9 1e 00 00                 ............

Disassembly of section text:

000000dc <__aeabi_uldivmod>:
      dc:	b953      	cbnz	r3, f4 <__aeabi_uldivmod+0x18>
      de:	b94a      	cbnz	r2, f4 <__aeabi_uldivmod+0x18>
      e0:	2900      	cmp	r1, #0
      e2:	bf08      	it	eq
      e4:	2800      	cmpeq	r0, #0
      e6:	bf1c      	itt	ne
      e8:	f04f 31ff 	movne.w	r1, #4294967295
      ec:	f04f 30ff 	movne.w	r0, #4294967295
      f0:	f000 b80c 	b.w	10c <__aeabi_idiv0>
      f4:	f1ad 0c08 	sub.w	ip, sp, #8
      f8:	e96d ce04 	strd	ip, lr, [sp, #-16]!
      fc:	f000 f808 	bl	110 <__udivmoddi4>
     100:	f8dd e004 	ldr.w	lr, [sp, #4]
     104:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
     108:	b004      	add	sp, #16
     10a:	4770      	bx	lr

0000010c <__aeabi_idiv0>:
     10c:	4770      	bx	lr
     10e:	bf00      	nop

00000110 <__udivmoddi4>:
     110:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     114:	4607      	mov	r7, r0
     116:	468c      	mov	ip, r1
     118:	4608      	mov	r0, r1
     11a:	9e09      	ldr	r6, [sp, #36]	; 0x24
     11c:	4615      	mov	r5, r2
     11e:	463c      	mov	r4, r7
     120:	4619      	mov	r1, r3
     122:	2b00      	cmp	r3, #0
     124:	f040 80c6 	bne.w	2b4 <CONFIG_FLASH_SIZE+0xb4>
     128:	4282      	cmp	r2, r0
     12a:	fab2 f782 	clz	r7, r2
     12e:	d946      	bls.n	1be <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x51>
     130:	b14f      	cbz	r7, 146 <CONFIG_IDLE_STACK_SIZE+0x6>
     132:	f1c7 0e20 	rsb	lr, r7, #32
     136:	fa24 fe0e 	lsr.w	lr, r4, lr
     13a:	fa00 f307 	lsl.w	r3, r0, r7
     13e:	40bd      	lsls	r5, r7
     140:	ea4e 0c03 	orr.w	ip, lr, r3
     144:	40bc      	lsls	r4, r7
     146:	ea4f 4815 	mov.w	r8, r5, lsr #16
     14a:	fa1f fe85 	uxth.w	lr, r5
     14e:	fbbc f9f8 	udiv	r9, ip, r8
     152:	0c22      	lsrs	r2, r4, #16
     154:	fb08 c319 	mls	r3, r8, r9, ip
     158:	fb09 fa0e 	mul.w	sl, r9, lr
     15c:	ea42 4303 	orr.w	r3, r2, r3, lsl #16
     160:	459a      	cmp	sl, r3
     162:	d928      	bls.n	1b6 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x49>
     164:	18eb      	adds	r3, r5, r3
     166:	f109 30ff 	add.w	r0, r9, #4294967295
     16a:	d204      	bcs.n	176 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x9>
     16c:	459a      	cmp	sl, r3
     16e:	d902      	bls.n	176 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x9>
     170:	f1a9 0002 	sub.w	r0, r9, #2
     174:	442b      	add	r3, r5
     176:	eba3 030a 	sub.w	r3, r3, sl
     17a:	b2a4      	uxth	r4, r4
     17c:	fbb3 f2f8 	udiv	r2, r3, r8
     180:	fb08 3312 	mls	r3, r8, r2, r3
     184:	fb02 fe0e 	mul.w	lr, r2, lr
     188:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
     18c:	45a6      	cmp	lr, r4
     18e:	d914      	bls.n	1ba <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x4d>
     190:	192c      	adds	r4, r5, r4
     192:	f102 33ff 	add.w	r3, r2, #4294967295
     196:	d203      	bcs.n	1a0 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x33>
     198:	45a6      	cmp	lr, r4
     19a:	d901      	bls.n	1a0 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x33>
     19c:	1e93      	subs	r3, r2, #2
     19e:	442c      	add	r4, r5
     1a0:	eba4 040e 	sub.w	r4, r4, lr
     1a4:	ea43 4000 	orr.w	r0, r3, r0, lsl #16
     1a8:	b11e      	cbz	r6, 1b2 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x45>
     1aa:	40fc      	lsrs	r4, r7
     1ac:	2300      	movs	r3, #0
     1ae:	6034      	str	r4, [r6, #0]
     1b0:	6073      	str	r3, [r6, #4]
     1b2:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
     1b6:	4648      	mov	r0, r9
     1b8:	e7dd      	b.n	176 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x9>
     1ba:	4613      	mov	r3, r2
     1bc:	e7f0      	b.n	1a0 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x33>
     1be:	b902      	cbnz	r2, 1c2 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x55>
     1c0:	deff      	udf	#255	; 0xff
     1c2:	bb87      	cbnz	r7, 226 <CONFIG_FLASH_SIZE+0x26>
     1c4:	1a83      	subs	r3, r0, r2
     1c6:	2101      	movs	r1, #1
     1c8:	ea4f 4e15 	mov.w	lr, r5, lsr #16
     1cc:	b2aa      	uxth	r2, r5
     1ce:	fbb3 fcfe 	udiv	ip, r3, lr
     1d2:	0c20      	lsrs	r0, r4, #16
     1d4:	fb0e 331c 	mls	r3, lr, ip, r3
     1d8:	fb0c f802 	mul.w	r8, ip, r2
     1dc:	ea40 4303 	orr.w	r3, r0, r3, lsl #16
     1e0:	4598      	cmp	r8, r3
     1e2:	d963      	bls.n	2ac <CONFIG_FLASH_SIZE+0xac>
     1e4:	18eb      	adds	r3, r5, r3
     1e6:	f10c 30ff 	add.w	r0, ip, #4294967295
     1ea:	d204      	bcs.n	1f6 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x89>
     1ec:	4598      	cmp	r8, r3
     1ee:	d902      	bls.n	1f6 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x89>
     1f0:	f1ac 0002 	sub.w	r0, ip, #2
     1f4:	442b      	add	r3, r5
     1f6:	eba3 0308 	sub.w	r3, r3, r8
     1fa:	b2a4      	uxth	r4, r4
     1fc:	fbb3 fcfe 	udiv	ip, r3, lr
     200:	fb0e 331c 	mls	r3, lr, ip, r3
     204:	fb0c f202 	mul.w	r2, ip, r2
     208:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
     20c:	42a2      	cmp	r2, r4
     20e:	d94f      	bls.n	2b0 <CONFIG_FLASH_SIZE+0xb0>
     210:	192c      	adds	r4, r5, r4
     212:	f10c 33ff 	add.w	r3, ip, #4294967295
     216:	d204      	bcs.n	222 <CONFIG_FLASH_SIZE+0x22>
     218:	42a2      	cmp	r2, r4
     21a:	d902      	bls.n	222 <CONFIG_FLASH_SIZE+0x22>
     21c:	f1ac 0302 	sub.w	r3, ip, #2
     220:	442c      	add	r4, r5
     222:	1aa4      	subs	r4, r4, r2
     224:	e7be      	b.n	1a4 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x37>
     226:	f1c7 0c20 	rsb	ip, r7, #32
     22a:	fa20 f80c 	lsr.w	r8, r0, ip
     22e:	fa00 f307 	lsl.w	r3, r0, r7
     232:	fa24 fc0c 	lsr.w	ip, r4, ip
     236:	40bd      	lsls	r5, r7
     238:	ea4c 0203 	orr.w	r2, ip, r3
     23c:	ea4f 4e15 	mov.w	lr, r5, lsr #16
     240:	b2ab      	uxth	r3, r5
     242:	fbb8 fcfe 	udiv	ip, r8, lr
     246:	0c11      	lsrs	r1, r2, #16
     248:	fb0e 801c 	mls	r0, lr, ip, r8
     24c:	fb0c f903 	mul.w	r9, ip, r3
     250:	ea41 4000 	orr.w	r0, r1, r0, lsl #16
     254:	4581      	cmp	r9, r0
     256:	fa04 f407 	lsl.w	r4, r4, r7
     25a:	d923      	bls.n	2a4 <CONFIG_FLASH_SIZE+0xa4>
     25c:	1828      	adds	r0, r5, r0
     25e:	f10c 31ff 	add.w	r1, ip, #4294967295
     262:	d204      	bcs.n	26e <CONFIG_FLASH_SIZE+0x6e>
     264:	4581      	cmp	r9, r0
     266:	d902      	bls.n	26e <CONFIG_FLASH_SIZE+0x6e>
     268:	f1ac 0102 	sub.w	r1, ip, #2
     26c:	4428      	add	r0, r5
     26e:	eba0 0009 	sub.w	r0, r0, r9
     272:	b292      	uxth	r2, r2
     274:	fbb0 fcfe 	udiv	ip, r0, lr
     278:	fb0e 001c 	mls	r0, lr, ip, r0
     27c:	fb0c f803 	mul.w	r8, ip, r3
     280:	ea42 4300 	orr.w	r3, r2, r0, lsl #16
     284:	4598      	cmp	r8, r3
     286:	d90f      	bls.n	2a8 <CONFIG_FLASH_SIZE+0xa8>
     288:	18eb      	adds	r3, r5, r3
     28a:	f10c 32ff 	add.w	r2, ip, #4294967295
     28e:	d204      	bcs.n	29a <CONFIG_FLASH_SIZE+0x9a>
     290:	4598      	cmp	r8, r3
     292:	d902      	bls.n	29a <CONFIG_FLASH_SIZE+0x9a>
     294:	f1ac 0202 	sub.w	r2, ip, #2
     298:	442b      	add	r3, r5
     29a:	eba3 0308 	sub.w	r3, r3, r8
     29e:	ea42 4101 	orr.w	r1, r2, r1, lsl #16
     2a2:	e791      	b.n	1c8 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x5b>
     2a4:	4661      	mov	r1, ip
     2a6:	e7e2      	b.n	26e <CONFIG_FLASH_SIZE+0x6e>
     2a8:	4662      	mov	r2, ip
     2aa:	e7f6      	b.n	29a <CONFIG_FLASH_SIZE+0x9a>
     2ac:	4660      	mov	r0, ip
     2ae:	e7a2      	b.n	1f6 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x89>
     2b0:	4663      	mov	r3, ip
     2b2:	e7b6      	b.n	222 <CONFIG_FLASH_SIZE+0x22>
     2b4:	4283      	cmp	r3, r0
     2b6:	d905      	bls.n	2c4 <CONFIG_FLASH_SIZE+0xc4>
     2b8:	b10e      	cbz	r6, 2be <CONFIG_FLASH_SIZE+0xbe>
     2ba:	e9c6 7000 	strd	r7, r0, [r6]
     2be:	2100      	movs	r1, #0
     2c0:	4608      	mov	r0, r1
     2c2:	e776      	b.n	1b2 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x45>
     2c4:	fab3 f183 	clz	r1, r3
     2c8:	b981      	cbnz	r1, 2ec <CONFIG_FLASH_SIZE+0xec>
     2ca:	4283      	cmp	r3, r0
     2cc:	d301      	bcc.n	2d2 <CONFIG_FLASH_SIZE+0xd2>
     2ce:	42ba      	cmp	r2, r7
     2d0:	d80a      	bhi.n	2e8 <CONFIG_FLASH_SIZE+0xe8>
     2d2:	1abc      	subs	r4, r7, r2
     2d4:	eb60 0303 	sbc.w	r3, r0, r3
     2d8:	2001      	movs	r0, #1
     2da:	469c      	mov	ip, r3
     2dc:	2e00      	cmp	r6, #0
     2de:	d068      	beq.n	3b2 <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0xb2>
     2e0:	e9c6 4c00 	strd	r4, ip, [r6]
     2e4:	2100      	movs	r1, #0
     2e6:	e764      	b.n	1b2 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x45>
     2e8:	4608      	mov	r0, r1
     2ea:	e7f7      	b.n	2dc <CONFIG_FLASH_SIZE+0xdc>
     2ec:	f1c1 0c20 	rsb	ip, r1, #32
     2f0:	408b      	lsls	r3, r1
     2f2:	fa22 f40c 	lsr.w	r4, r2, ip
     2f6:	431c      	orrs	r4, r3
     2f8:	fa02 f501 	lsl.w	r5, r2, r1
     2fc:	fa00 f301 	lsl.w	r3, r0, r1
     300:	fa27 f20c 	lsr.w	r2, r7, ip
     304:	fa20 fb0c 	lsr.w	fp, r0, ip
     308:	ea4f 4914 	mov.w	r9, r4, lsr #16
     30c:	4313      	orrs	r3, r2
     30e:	fbbb f8f9 	udiv	r8, fp, r9
     312:	fa1f fe84 	uxth.w	lr, r4
     316:	fb09 bb18 	mls	fp, r9, r8, fp
     31a:	0c1a      	lsrs	r2, r3, #16
     31c:	fb08 fa0e 	mul.w	sl, r8, lr
     320:	ea42 420b 	orr.w	r2, r2, fp, lsl #16
     324:	4592      	cmp	sl, r2
     326:	fa07 f701 	lsl.w	r7, r7, r1
     32a:	d93e      	bls.n	3aa <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0xaa>
     32c:	18a2      	adds	r2, r4, r2
     32e:	f108 30ff 	add.w	r0, r8, #4294967295
     332:	d204      	bcs.n	33e <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x3e>
     334:	4592      	cmp	sl, r2
     336:	d902      	bls.n	33e <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x3e>
     338:	f1a8 0002 	sub.w	r0, r8, #2
     33c:	4422      	add	r2, r4
     33e:	eba2 020a 	sub.w	r2, r2, sl
     342:	b29b      	uxth	r3, r3
     344:	fbb2 f8f9 	udiv	r8, r2, r9
     348:	fb09 2218 	mls	r2, r9, r8, r2
     34c:	fb08 fe0e 	mul.w	lr, r8, lr
     350:	ea43 4202 	orr.w	r2, r3, r2, lsl #16
     354:	4596      	cmp	lr, r2
     356:	d92a      	bls.n	3ae <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0xae>
     358:	18a2      	adds	r2, r4, r2
     35a:	f108 33ff 	add.w	r3, r8, #4294967295
     35e:	d204      	bcs.n	36a <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x6a>
     360:	4596      	cmp	lr, r2
     362:	d902      	bls.n	36a <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x6a>
     364:	f1a8 0302 	sub.w	r3, r8, #2
     368:	4422      	add	r2, r4
     36a:	ea43 4000 	orr.w	r0, r3, r0, lsl #16
     36e:	fba0 9305 	umull	r9, r3, r0, r5
     372:	eba2 020e 	sub.w	r2, r2, lr
     376:	429a      	cmp	r2, r3
     378:	46ce      	mov	lr, r9
     37a:	4698      	mov	r8, r3
     37c:	d302      	bcc.n	384 <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x84>
     37e:	d106      	bne.n	38e <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x8e>
     380:	454f      	cmp	r7, r9
     382:	d204      	bcs.n	38e <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x8e>
     384:	ebb9 0e05 	subs.w	lr, r9, r5
     388:	eb63 0804 	sbc.w	r8, r3, r4
     38c:	3801      	subs	r0, #1
     38e:	b186      	cbz	r6, 3b2 <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0xb2>
     390:	ebb7 030e 	subs.w	r3, r7, lr
     394:	eb62 0708 	sbc.w	r7, r2, r8
     398:	fa07 fc0c 	lsl.w	ip, r7, ip
     39c:	40cb      	lsrs	r3, r1
     39e:	ea4c 0303 	orr.w	r3, ip, r3
     3a2:	40cf      	lsrs	r7, r1
     3a4:	e9c6 3700 	strd	r3, r7, [r6]
     3a8:	e79c      	b.n	2e4 <CONFIG_FLASH_SIZE+0xe4>
     3aa:	4640      	mov	r0, r8
     3ac:	e7c7      	b.n	33e <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x3e>
     3ae:	4643      	mov	r3, r8
     3b0:	e7db      	b.n	36a <CONFIG_MCUBOOT_LOG_THREAD_STACK_SIZE+0x6a>
     3b2:	4631      	mov	r1, r6
     3b4:	e6fd      	b.n	1b2 <CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS+0x45>
	...

000003b8 <main>:
    return detect_value == expected;
}
#endif

void main(void)
{
     3b8:	b57f      	push	{r0, r1, r2, r3, r4, r5, r6, lr}
}

NRF_STATIC_INLINE void nrf_wdt_reload_request_set(NRF_WDT_Type *        p_reg,
                                                  nrf_wdt_rr_register_t rr_register)
{
    p_reg->RR[rr_register] = NRF_WDT_RR_VALUE;
     3ba:	4b30      	ldr	r3, [pc, #192]	; (47c <FIH_LABEL_FIH_CALL_END_262+0x78>)
     3bc:	4a30      	ldr	r2, [pc, #192]	; (480 <FIH_LABEL_FIH_CALL_END_262+0x7c>)
     3be:	f8c3 2600 	str.w	r2, [r3, #1536]	; 0x600
    fih_int fih_rc = FIH_FAILURE;

    MCUBOOT_WATCHDOG_FEED();

#if !defined(MCUBOOT_DIRECT_XIP)
    BOOT_LOG_INF("Starting bootloader");
     3c2:	4830      	ldr	r0, [pc, #192]	; (484 <FIH_LABEL_FIH_CALL_END_262+0x80>)
     3c4:	f8c3 2604 	str.w	r2, [r3, #1540]	; 0x604
     3c8:	2149      	movs	r1, #73	; 0x49
     3ca:	f8c3 2608 	str.w	r2, [r3, #1544]	; 0x608
     3ce:	f8c3 260c 	str.w	r2, [r3, #1548]	; 0x60c
     3d2:	f8c3 2610 	str.w	r2, [r3, #1552]	; 0x610
     3d6:	f8c3 2614 	str.w	r2, [r3, #1556]	; 0x614
     3da:	f8c3 2618 	str.w	r2, [r3, #1560]	; 0x618
     3de:	f8c3 261c 	str.w	r2, [r3, #1564]	; 0x61c
     3e2:	f005 fb99 	bl	5b18 <z_log_minimal_printk>
#ifdef CONFIG_MCUBOOT_INDICATION_LED
    /* LED init */
    led_init();
#endif

    os_heap_init();
     3e6:	f004 f912 	bl	460e <os_heap_init>
    ZEPHYR_BOOT_LOG_START();

    (void)rc;

#if (!defined(CONFIG_XTENSA) && DT_HAS_CHOSEN(zephyr_flash_controller))
    if (!flash_device_get_binding(DT_LABEL(DT_CHOSEN(zephyr_flash_controller)))) {
     3ea:	4827      	ldr	r0, [pc, #156]	; (488 <FIH_LABEL_FIH_CALL_END_262+0x84>)
     3ec:	f000 f85c 	bl	4a8 <flash_device_get_binding>
     3f0:	b928      	cbnz	r0, 3fe <FIH_LABEL_FIH_CALL_START_249>
        BOOT_LOG_ERR("Flash device %s not found",
     3f2:	4a25      	ldr	r2, [pc, #148]	; (488 <FIH_LABEL_FIH_CALL_END_262+0x84>)
     3f4:	4825      	ldr	r0, [pc, #148]	; (48c <FIH_LABEL_FIH_CALL_END_262+0x88>)
     3f6:	2145      	movs	r1, #69	; 0x45
     3f8:	f005 fb8e 	bl	5b18 <z_log_minimal_printk>
		     DT_LABEL(DT_CHOSEN(zephyr_flash_controller)));
        while (1)
     3fc:	e7fe      	b.n	3fc <main+0x44>

000003fe <FIH_LABEL_FIH_CALL_START_249>:
    rc = boot_console_init();
    int timeout_in_ms = CONFIG_BOOT_SERIAL_WAIT_FOR_DFU_TIMEOUT;
    uint32_t start = k_uptime_get_32();
#endif

    FIH_CALL(boot_go, fih_rc, &rsp);
     3fe:	a801      	add	r0, sp, #4
     400:	f000 fc50 	bl	ca4 <boot_go>

00000404 <FIH_LABEL_FIH_CALL_END_262>:
        timeout_in_ms = 1;
    }
   boot_serial_check_start(&boot_funcs,timeout_in_ms);
#endif

    if (fih_not_eq(fih_rc, FIH_SUCCESS)) {
     404:	4b22      	ldr	r3, [pc, #136]	; (490 <FIH_LABEL_FIH_CALL_END_262+0x8c>)
     406:	681b      	ldr	r3, [r3, #0]
     408:	4283      	cmp	r3, r0
     40a:	d004      	beq.n	416 <FIH_LABEL_FIH_CALL_END_262+0x12>
        BOOT_LOG_ERR("Unable to find bootable image");
     40c:	4821      	ldr	r0, [pc, #132]	; (494 <FIH_LABEL_FIH_CALL_END_262+0x90>)
     40e:	2145      	movs	r1, #69	; 0x45
     410:	f005 fb82 	bl	5b18 <z_log_minimal_printk>
        FIH_PANIC;
     414:	e7fe      	b.n	414 <FIH_LABEL_FIH_CALL_END_262+0x10>
    }

    BOOT_LOG_INF("Bootloader chainload address offset: 0x%x",
     416:	9a03      	ldr	r2, [sp, #12]
     418:	481f      	ldr	r0, [pc, #124]	; (498 <FIH_LABEL_FIH_CALL_END_262+0x94>)
     41a:	2149      	movs	r1, #73	; 0x49
     41c:	f005 fb7c 	bl	5b18 <z_log_minimal_printk>
                 rsp.br_image_off);

#if defined(MCUBOOT_DIRECT_XIP)
    BOOT_LOG_INF("Jumping to the image slot");
#else
    BOOT_LOG_INF("Jumping to the first image slot");
     420:	481e      	ldr	r0, [pc, #120]	; (49c <FIH_LABEL_FIH_CALL_END_262+0x98>)
     422:	2149      	movs	r1, #73	; 0x49
     424:	f005 fb78 	bl	5b18 <z_log_minimal_printk>
/* There is only one instance of MCUBoot */
#define PROTECT_SIZE (PM_MCUBOOT_PRIMARY_ADDRESS - PM_MCUBOOT_ADDRESS)
#define PROTECT_ADDR PM_MCUBOOT_ADDRESS
#endif

    rc = fprotect_area(PROTECT_ADDR, PROTECT_SIZE);
     428:	f44f 4140 	mov.w	r1, #49152	; 0xc000
     42c:	2000      	movs	r0, #0
     42e:	f005 feaa 	bl	6186 <fprotect_area>

    if (rc != 0) {
     432:	b120      	cbz	r0, 43e <FIH_LABEL_FIH_CALL_END_262+0x3a>
        BOOT_LOG_ERR("Protect mcuboot flash failed, cancel startup.");
     434:	481a      	ldr	r0, [pc, #104]	; (4a0 <FIH_LABEL_FIH_CALL_END_262+0x9c>)
     436:	2145      	movs	r1, #69	; 0x45
     438:	f005 fb6e 	bl	5b18 <z_log_minimal_printk>
        while (1)
     43c:	e7fe      	b.n	43c <FIH_LABEL_FIH_CALL_END_262+0x38>
    rc = flash_device_base(rsp->br_flash_dev_id, &flash_base);
     43e:	4669      	mov	r1, sp
     440:	f89d 0008 	ldrb.w	r0, [sp, #8]
     444:	f000 f83c 	bl	4c0 <flash_device_base>
    vt = (struct arm_vector_table *)(flash_base +
     448:	9b00      	ldr	r3, [sp, #0]
     44a:	9c03      	ldr	r4, [sp, #12]
     44c:	441c      	add	r4, r3
                                     rsp->br_hdr->ih_hdr_size);
     44e:	9b01      	ldr	r3, [sp, #4]
     450:	891d      	ldrh	r5, [r3, #8]
    nrf_cleanup_peripheral();
     452:	f001 f8c9 	bl	15e8 <nrf_cleanup_peripheral>
                                     rsp->br_image_off +
     456:	1966      	adds	r6, r4, r5
		:
		: "memory");
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	unsigned int tmp;

	__asm__ volatile(
     458:	f04f 0220 	mov.w	r2, #32
     45c:	f3ef 8311 	mrs	r3, BASEPRI
     460:	f382 8812 	msr	BASEPRI_MAX, r2
     464:	f3bf 8f6f 	isb	sy
  \details Assigns the given value to the Main Stack Pointer (MSP).
  \param [in]    topOfMainStack  Main Stack Pointer value to set
 */
__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
{
  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
     468:	5963      	ldr	r3, [r4, r5]
     46a:	f383 8808 	msr	MSP, r3
    ((void (*)(void))vt->reset)();
     46e:	6873      	ldr	r3, [r6, #4]
     470:	4798      	blx	r3

    ZEPHYR_BOOT_LOG_STOP();

    do_boot(&rsp);

    BOOT_LOG_ERR("Never should get here");
     472:	480c      	ldr	r0, [pc, #48]	; (4a4 <FIH_LABEL_FIH_CALL_END_262+0xa0>)
     474:	2145      	movs	r1, #69	; 0x45
     476:	f005 fb4f 	bl	5b18 <z_log_minimal_printk>
    while (1)
     47a:	e7fe      	b.n	47a <FIH_LABEL_FIH_CALL_END_262+0x76>
     47c:	40010000 	.word	0x40010000
     480:	6e524635 	.word	0x6e524635
     484:	000069e0 	.word	0x000069e0
     488:	000069f9 	.word	0x000069f9
     48c:	00006a0c 	.word	0x00006a0c
     490:	20000154 	.word	0x20000154
     494:	00006a2b 	.word	0x00006a2b
     498:	00006a4e 	.word	0x00006a4e
     49c:	00006a7d 	.word	0x00006a7d
     4a0:	00006aa2 	.word	0x00006aa2
     4a4:	00006ad5 	.word	0x00006ad5

000004a8 <flash_device_get_binding>:
#endif

static const struct device *flash_dev;

const struct device *flash_device_get_binding(char *dev_name)
{
     4a8:	b510      	push	{r4, lr}
    if (!flash_dev) {
     4aa:	4c04      	ldr	r4, [pc, #16]	; (4bc <flash_device_get_binding+0x14>)
     4ac:	6823      	ldr	r3, [r4, #0]
     4ae:	b913      	cbnz	r3, 4b6 <flash_device_get_binding+0xe>
		union { uintptr_t x; const char * val; } parm0 = { .val = name };
		return (const struct device *) arch_syscall_invoke1(parm0.x, K_SYSCALL_DEVICE_GET_BINDING);
	}
#endif
	compiler_barrier();
	return z_impl_device_get_binding(name);
     4b0:	f003 ff1c 	bl	42ec <z_impl_device_get_binding>
        flash_dev = device_get_binding(dev_name);
     4b4:	6020      	str	r0, [r4, #0]
    }
    return flash_dev;
}
     4b6:	6820      	ldr	r0, [r4, #0]
     4b8:	bd10      	pop	{r4, pc}
     4ba:	bf00      	nop
     4bc:	20000150 	.word	0x20000150

000004c0 <flash_device_base>:

int flash_device_base(uint8_t fd_id, uintptr_t *ret)
{
     4c0:	b508      	push	{r3, lr}
    if (fd_id != FLASH_DEVICE_ID) {
     4c2:	4602      	mov	r2, r0
     4c4:	b138      	cbz	r0, 4d6 <flash_device_base+0x16>
        BOOT_LOG_ERR("invalid flash ID %d; expected %d",
     4c6:	4805      	ldr	r0, [pc, #20]	; (4dc <flash_device_base+0x1c>)
     4c8:	2300      	movs	r3, #0
     4ca:	2145      	movs	r1, #69	; 0x45
     4cc:	f005 fb24 	bl	5b18 <z_log_minimal_printk>
                     fd_id, FLASH_DEVICE_ID);
        return -EINVAL;
     4d0:	f06f 0015 	mvn.w	r0, #21
    }
    *ret = FLASH_DEVICE_BASE;
    return 0;
}
     4d4:	bd08      	pop	{r3, pc}
    *ret = FLASH_DEVICE_BASE;
     4d6:	6008      	str	r0, [r1, #0]
    return 0;
     4d8:	e7fc      	b.n	4d4 <flash_device_base+0x14>
     4da:	bf00      	nop
     4dc:	00006af8 	.word	0x00006af8

000004e0 <bootutil_img_validate>:
fih_int
bootutil_img_validate(struct enc_key_data *enc_state, int image_index,
                      struct image_header *hdr, const struct flash_area *fap,
                      uint8_t *tmp_buf, uint32_t tmp_buf_sz, uint8_t *seed,
                      int seed_len, uint8_t *out_hash)
{
     4e0:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     4e4:	b0d9      	sub	sp, #356	; 0x164
     4e6:	e9dd 4864 	ldrd	r4, r8, [sp, #400]	; 0x190
    uint32_t off;
    uint16_t len;
    uint16_t type;
    int sha256_valid = 0;
#ifdef EXPECTED_SIG_TLV
    fih_int valid_signature = FIH_FAILURE;
     4ea:	f8df a1c8 	ldr.w	sl, [pc, #456]	; 6b4 <FIH_LABEL_FIH_CALL_END_633+0x2c>

#if defined(MCUBOOT_USE_TINYCRYPT)
typedef struct tc_sha256_state_struct bootutil_sha256_context;
static inline void bootutil_sha256_init(bootutil_sha256_context *ctx)
{
    tc_sha256_init(ctx);
     4ee:	a838      	add	r0, sp, #224	; 0xe0
     4f0:	f8da 6000 	ldr.w	r6, [sl]
{
     4f4:	4617      	mov	r7, r2
     4f6:	461d      	mov	r5, r3
     4f8:	f001 f84a 	bl	1590 <tc_sha256_init>
    if (seed && (seed_len > 0)) {
     4fc:	b13c      	cbz	r4, 50e <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x26>
     4fe:	f1b8 0f00 	cmp.w	r8, #0
     502:	dd04      	ble.n	50e <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x26>

static inline int bootutil_sha256_update(bootutil_sha256_context *ctx,
                                         const void *data,
                                         uint32_t data_len)
{
    return tc_sha256_update(ctx, data, data_len);
     504:	4642      	mov	r2, r8
     506:	4621      	mov	r1, r4
     508:	a838      	add	r0, sp, #224	; 0xe0
     50a:	f005 f9a5 	bl	5858 <tc_sha256_update>
    size += hdr->ih_protect_tlv_size;
     50e:	897b      	ldrh	r3, [r7, #10]
    size = hdr_size = hdr->ih_hdr_size;
     510:	f8b7 8008 	ldrh.w	r8, [r7, #8]
     514:	4498      	add	r8, r3
    size += hdr->ih_protect_tlv_size;
     516:	68fb      	ldr	r3, [r7, #12]
    for (off = 0; off < size; off += blk_sz) {
     518:	f04f 0900 	mov.w	r9, #0
    size += hdr->ih_protect_tlv_size;
     51c:	4498      	add	r8, r3
    for (off = 0; off < size; off += blk_sz) {
     51e:	45c8      	cmp	r8, r9
     520:	d849      	bhi.n	5b6 <FIH_LABEL_FIH_CALL_END_304+0xe>
}

static inline int bootutil_sha256_finish(bootutil_sha256_context *ctx,
                                          uint8_t *output)
{
    return tc_sha256_final(output, ctx);
     522:	a938      	add	r1, sp, #224	; 0xe0
     524:	a80c      	add	r0, sp, #48	; 0x30
     526:	f005 f9bd 	bl	58a4 <tc_sha256_final>
            tmp_buf_sz, hash, seed, seed_len);
    if (rc) {
        goto out;
    }

    if (out_hash) {
     52a:	9b66      	ldr	r3, [sp, #408]	; 0x198
     52c:	b123      	cbz	r3, 538 <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x50>
        memcpy(out_hash, hash, 32);
     52e:	2220      	movs	r2, #32
     530:	a90c      	add	r1, sp, #48	; 0x30
     532:	4618      	mov	r0, r3
     534:	f005 fbba 	bl	5cac <memcpy>
    }

    rc = bootutil_tlv_iter_begin(&it, hdr, fap, IMAGE_TLV_ANY, false);
     538:	2300      	movs	r3, #0
     53a:	9300      	str	r3, [sp, #0]
     53c:	462a      	mov	r2, r5
     53e:	f64f 73ff 	movw	r3, #65535	; 0xffff
     542:	4639      	mov	r1, r7
     544:	a806      	add	r0, sp, #24
     546:	f004 f863 	bl	4610 <bootutil_tlv_iter_begin>
    if (rc) {
     54a:	4604      	mov	r4, r0
     54c:	2800      	cmp	r0, #0
     54e:	f040 80ab 	bne.w	6a8 <FIH_LABEL_FIH_CALL_END_633+0x20>
             * can be multiple signatures, each preceded by a key.
             */
#endif /* !MCUBOOT_HW_KEY */
        } else if (type == EXPECTED_SIG_TLV) {
            /* Ignore this signature if it is out of bounds. */
            if (key_id < 0 || key_id >= bootutil_key_cnt) {
     552:	f8df 9164 	ldr.w	r9, [pc, #356]	; 6b8 <FIH_LABEL_FIH_CALL_END_633+0x30>
    int sha256_valid = 0;
     556:	4680      	mov	r8, r0
    int key_id = -1;
     558:	f04f 37ff 	mov.w	r7, #4294967295
        rc = bootutil_tlv_iter_next(&it, &off, &len, &type);
     55c:	f10d 0312 	add.w	r3, sp, #18
     560:	aa04      	add	r2, sp, #16
     562:	a905      	add	r1, sp, #20
     564:	a806      	add	r0, sp, #24
     566:	f004 f89f 	bl	46a8 <bootutil_tlv_iter_next>
        if (rc < 0) {
     56a:	1e04      	subs	r4, r0, #0
     56c:	f2c0 809c 	blt.w	6a8 <FIH_LABEL_FIH_CALL_END_633+0x20>
        } else if (rc > 0) {
     570:	f040 808d 	bne.w	68e <FIH_LABEL_FIH_CALL_END_633+0x6>
        if (type == IMAGE_TLV_SHA256) {
     574:	f8bd 3012 	ldrh.w	r3, [sp, #18]
     578:	2b10      	cmp	r3, #16
     57a:	d133      	bne.n	5e4 <FIH_LABEL_FIH_CALL_END_304+0x3c>
            if (len != sizeof(hash)) {
     57c:	f8bd 8010 	ldrh.w	r8, [sp, #16]
     580:	f1b8 0f20 	cmp.w	r8, #32
     584:	f040 808e 	bne.w	6a4 <FIH_LABEL_FIH_CALL_END_633+0x1c>
            rc = LOAD_IMAGE_DATA(hdr, fap, off, buf, sizeof(hash));
     588:	9905      	ldr	r1, [sp, #20]
     58a:	4643      	mov	r3, r8
     58c:	aa38      	add	r2, sp, #224	; 0xe0
     58e:	4628      	mov	r0, r5
     590:	f005 fad0 	bl	5b34 <flash_area_read>
            if (rc) {
     594:	4604      	mov	r4, r0
     596:	2800      	cmp	r0, #0
     598:	f040 8086 	bne.w	6a8 <FIH_LABEL_FIH_CALL_END_633+0x20>

0000059c <FIH_LABEL_FIH_CALL_START_285>:
            FIH_CALL(boot_fih_memequal, fih_rc, hash, buf, sizeof(hash));
     59c:	4642      	mov	r2, r8
     59e:	a938      	add	r1, sp, #224	; 0xe0
     5a0:	a80c      	add	r0, sp, #48	; 0x30
     5a2:	f004 f8f8 	bl	4796 <boot_fih_memequal>
     5a6:	4604      	mov	r4, r0

000005a8 <FIH_LABEL_FIH_CALL_END_304>:
            if (fih_not_eq(fih_rc, FIH_SUCCESS)) {
     5a8:	4b44      	ldr	r3, [pc, #272]	; (6bc <FIH_LABEL_FIH_CALL_END_633+0x34>)
     5aa:	681b      	ldr	r3, [r3, #0]
     5ac:	4283      	cmp	r3, r0
     5ae:	d17b      	bne.n	6a8 <FIH_LABEL_FIH_CALL_END_633+0x20>
            sha256_valid = 1;
     5b0:	f04f 0801 	mov.w	r8, #1
     5b4:	e7d2      	b.n	55c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x74>
        blk_sz = size - off;
     5b6:	f8dd b18c 	ldr.w	fp, [sp, #396]	; 0x18c
        rc = flash_area_read(fap, off, tmp_buf, blk_sz);
     5ba:	9a62      	ldr	r2, [sp, #392]	; 0x188
        blk_sz = size - off;
     5bc:	eba8 0309 	sub.w	r3, r8, r9
        if (blk_sz > tmp_buf_sz) {
     5c0:	459b      	cmp	fp, r3
     5c2:	bf28      	it	cs
     5c4:	469b      	movcs	fp, r3
        rc = flash_area_read(fap, off, tmp_buf, blk_sz);
     5c6:	465b      	mov	r3, fp
     5c8:	4649      	mov	r1, r9
     5ca:	4628      	mov	r0, r5
     5cc:	f005 fab2 	bl	5b34 <flash_area_read>
        if (rc) {
     5d0:	4604      	mov	r4, r0
     5d2:	2800      	cmp	r0, #0
     5d4:	d168      	bne.n	6a8 <FIH_LABEL_FIH_CALL_END_633+0x20>
    return tc_sha256_update(ctx, data, data_len);
     5d6:	9962      	ldr	r1, [sp, #392]	; 0x188
     5d8:	465a      	mov	r2, fp
     5da:	a838      	add	r0, sp, #224	; 0xe0
     5dc:	f005 f93c 	bl	5858 <tc_sha256_update>
    for (off = 0; off < size; off += blk_sz) {
     5e0:	44d9      	add	r9, fp
     5e2:	e79c      	b.n	51e <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x36>
        } else if (type == IMAGE_TLV_KEYHASH) {
     5e4:	2b01      	cmp	r3, #1
     5e6:	d132      	bne.n	64e <FIH_LABEL_FIH_CALL_END_304+0xa6>
            if (len > 32) {
     5e8:	f8bd 3010 	ldrh.w	r3, [sp, #16]
     5ec:	2b20      	cmp	r3, #32
     5ee:	d859      	bhi.n	6a4 <FIH_LABEL_FIH_CALL_END_633+0x1c>
            rc = LOAD_IMAGE_DATA(hdr, fap, off, buf, len);
     5f0:	9905      	ldr	r1, [sp, #20]
     5f2:	aa38      	add	r2, sp, #224	; 0xe0
     5f4:	4628      	mov	r0, r5
     5f6:	f005 fa9d 	bl	5b34 <flash_area_read>
            if (rc) {
     5fa:	4604      	mov	r4, r0
     5fc:	2800      	cmp	r0, #0
     5fe:	d153      	bne.n	6a8 <FIH_LABEL_FIH_CALL_END_633+0x20>
            key_id = bootutil_find_key(buf, len);
     600:	f89d b010 	ldrb.w	fp, [sp, #16]
    if (keyhash_len > 32) {
     604:	f1bb 0f20 	cmp.w	fp, #32
     608:	d903      	bls.n	612 <FIH_LABEL_FIH_CALL_END_304+0x6a>
        return -1;
     60a:	f04f 34ff 	mov.w	r4, #4294967295
            key_id = bootutil_find_key(buf, len);
     60e:	4627      	mov	r7, r4
     610:	e7a4      	b.n	55c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x74>
    for (i = 0; i < bootutil_key_cnt; i++) {
     612:	f8d9 3000 	ldr.w	r3, [r9]
     616:	4f2a      	ldr	r7, [pc, #168]	; (6c0 <FIH_LABEL_FIH_CALL_END_633+0x38>)
     618:	9303      	str	r3, [sp, #12]
     61a:	9b03      	ldr	r3, [sp, #12]
     61c:	429c      	cmp	r4, r3
     61e:	daf4      	bge.n	60a <FIH_LABEL_FIH_CALL_END_304+0x62>
    tc_sha256_init(ctx);
     620:	a81c      	add	r0, sp, #112	; 0x70
     622:	f000 ffb5 	bl	1590 <tc_sha256_init>
        bootutil_sha256_update(&sha256_ctx, key->key, *key->len);
     626:	687a      	ldr	r2, [r7, #4]
    return tc_sha256_update(ctx, data, data_len);
     628:	f857 1b08 	ldr.w	r1, [r7], #8
     62c:	6812      	ldr	r2, [r2, #0]
     62e:	a81c      	add	r0, sp, #112	; 0x70
     630:	f005 f912 	bl	5858 <tc_sha256_update>
    return tc_sha256_final(output, ctx);
     634:	a91c      	add	r1, sp, #112	; 0x70
     636:	a814      	add	r0, sp, #80	; 0x50
     638:	f005 f934 	bl	58a4 <tc_sha256_final>
        if (!memcmp(hash, keyhash, keyhash_len)) {
     63c:	465a      	mov	r2, fp
     63e:	a938      	add	r1, sp, #224	; 0xe0
     640:	a814      	add	r0, sp, #80	; 0x50
     642:	f005 fb22 	bl	5c8a <memcmp>
     646:	2800      	cmp	r0, #0
     648:	d0e1      	beq.n	60e <FIH_LABEL_FIH_CALL_END_304+0x66>
    for (i = 0; i < bootutil_key_cnt; i++) {
     64a:	3401      	adds	r4, #1
     64c:	e7e5      	b.n	61a <FIH_LABEL_FIH_CALL_END_304+0x72>
        } else if (type == EXPECTED_SIG_TLV) {
     64e:	2b22      	cmp	r3, #34	; 0x22
     650:	d184      	bne.n	55c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x74>
            if (key_id < 0 || key_id >= bootutil_key_cnt) {
     652:	1c7b      	adds	r3, r7, #1
     654:	d082      	beq.n	55c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x74>
     656:	f8d9 3000 	ldr.w	r3, [r9]
     65a:	42bb      	cmp	r3, r7
     65c:	dd14      	ble.n	688 <FIH_LABEL_FIH_CALL_END_633>
                key_id = -1;
                continue;
            }
            if (!EXPECTED_SIG_LEN(len) || len > sizeof(buf)) {
     65e:	f8bd 3010 	ldrh.w	r3, [sp, #16]
     662:	2b80      	cmp	r3, #128	; 0x80
     664:	d81e      	bhi.n	6a4 <FIH_LABEL_FIH_CALL_END_633+0x1c>
                rc = -1;
                goto out;
            }
            rc = LOAD_IMAGE_DATA(hdr, fap, off, buf, len);
     666:	9905      	ldr	r1, [sp, #20]
     668:	aa38      	add	r2, sp, #224	; 0xe0
     66a:	4628      	mov	r0, r5
     66c:	f005 fa62 	bl	5b34 <flash_area_read>
            if (rc) {
     670:	4604      	mov	r4, r0
     672:	b9c8      	cbnz	r0, 6a8 <FIH_LABEL_FIH_CALL_END_633+0x20>

00000674 <FIH_LABEL_FIH_CALL_START_611>:
                goto out;
            }
            FIH_CALL(bootutil_verify_sig, valid_signature, hash, sizeof(hash),
     674:	b2ff      	uxtb	r7, r7
     676:	f8bd 3010 	ldrh.w	r3, [sp, #16]
     67a:	9700      	str	r7, [sp, #0]
     67c:	aa38      	add	r2, sp, #224	; 0xe0
     67e:	2120      	movs	r1, #32
     680:	a80c      	add	r0, sp, #48	; 0x30
     682:	f000 f81f 	bl	6c4 <bootutil_verify_sig>
     686:	4606      	mov	r6, r0

00000688 <FIH_LABEL_FIH_CALL_END_633>:
                key_id = -1;
     688:	f04f 37ff 	mov.w	r7, #4294967295
     68c:	e766      	b.n	55c <CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE+0x74>
#endif /* MCUBOOT_HW_ROLLBACK_PROT */
        }
    }

    rc = !sha256_valid;
    if (rc) {
     68e:	f1b8 0f00 	cmp.w	r8, #0
     692:	d00d      	beq.n	6b0 <FIH_LABEL_FIH_CALL_END_633+0x28>
        goto out;
    }
#ifdef EXPECTED_SIG_TLV
    fih_rc = fih_int_encode_zero_equality(fih_not_eq(valid_signature,
     694:	4b09      	ldr	r3, [pc, #36]	; (6bc <FIH_LABEL_FIH_CALL_END_633+0x34>)
 * value that is not FIH_SUCCESS
 */
__attribute__((always_inline)) inline
fih_int fih_int_encode_zero_equality(int x)
{
    if (x) {
     696:	681b      	ldr	r3, [r3, #0]
     698:	42b3      	cmp	r3, r6
     69a:	d001      	beq.n	6a0 <FIH_LABEL_FIH_CALL_END_633+0x18>
        return FIH_FAILURE;
     69c:	f8da 6000 	ldr.w	r6, [sl]
                rc = -1;
     6a0:	4634      	mov	r4, r6
     6a2:	e001      	b.n	6a8 <FIH_LABEL_FIH_CALL_END_633+0x20>
     6a4:	f04f 34ff 	mov.w	r4, #4294967295
    if (rc) {
        fih_rc = fih_int_encode(rc);
    }

    FIH_RET(fih_rc);
}
     6a8:	4620      	mov	r0, r4
     6aa:	b059      	add	sp, #356	; 0x164
     6ac:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
     6b0:	2401      	movs	r4, #1
    FIH_RET(fih_rc);
     6b2:	e7f9      	b.n	6a8 <FIH_LABEL_FIH_CALL_END_633+0x20>
     6b4:	20000000 	.word	0x20000000
     6b8:	00006678 	.word	0x00006678
     6bc:	20000154 	.word	0x20000154
     6c0:	0000667c 	.word	0x0000667c

000006c4 <bootutil_verify_sig>:
#endif /* not MCUBOOT_ECDSA_NEED_ASN1_SIG */

int
bootutil_verify_sig(uint8_t *hash, uint32_t hlen, uint8_t *sig, size_t slen,
  uint8_t key_id)
{
     6c4:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
     6c8:	b098      	sub	sp, #96	; 0x60
     6ca:	4617      	mov	r7, r2
     6cc:	461d      	mov	r5, r3
     6ce:	f89d 2078 	ldrb.w	r2, [sp, #120]	; 0x78

#ifndef MCUBOOT_ECDSA_NEED_ASN1_SIG
    uint8_t signature[2 * NUM_ECC_BYTES];
#endif

    pubkey = (uint8_t *)bootutil_keys[key_id].key;
     6d2:	4b39      	ldr	r3, [pc, #228]	; (7b8 <bootutil_verify_sig+0xf4>)
{
     6d4:	460e      	mov	r6, r1
    pubkey = (uint8_t *)bootutil_keys[key_id].key;
     6d6:	f853 1032 	ldr.w	r1, [r3, r2, lsl #3]
     6da:	9103      	str	r1, [sp, #12]
    end = pubkey + *bootutil_keys[key_id].len;
     6dc:	eb03 03c2 	add.w	r3, r3, r2, lsl #3
{
     6e0:	4680      	mov	r8, r0
    end = pubkey + *bootutil_keys[key_id].len;
     6e2:	685b      	ldr	r3, [r3, #4]
     6e4:	6818      	ldr	r0, [r3, #0]
    if (mbedtls_asn1_get_tag(cp, end, &len,
     6e6:	aa04      	add	r2, sp, #16
     6e8:	4401      	add	r1, r0
     6ea:	2330      	movs	r3, #48	; 0x30
     6ec:	a803      	add	r0, sp, #12
     6ee:	f004 fa6c 	bl	4bca <mbedtls_asn1_get_tag>
     6f2:	b110      	cbz	r0, 6fa <bootutil_verify_sig+0x36>
    }
    rc = mbedtls_ecdsa_read_signature(&ctx, hash, hlen, sig, slen);

#else /* CY_MBEDTLS_HW_ACCELERATION */
    if (hlen != NUM_ECC_BYTES) {
        return -1;
     6f4:	f04f 30ff 	mov.w	r0, #4294967295
     6f8:	e05a      	b.n	7b0 <bootutil_verify_sig+0xec>
    end = *cp + len;
     6fa:	e9dd 4303 	ldrd	r4, r3, [sp, #12]
     6fe:	441c      	add	r4, r3
    if (mbedtls_asn1_get_alg(cp, end, &alg, &param)) {
     700:	aa05      	add	r2, sp, #20
     702:	ab08      	add	r3, sp, #32
     704:	4621      	mov	r1, r4
     706:	a803      	add	r0, sp, #12
     708:	f004 fa87 	bl	4c1a <mbedtls_asn1_get_alg>
     70c:	2800      	cmp	r0, #0
     70e:	d1f1      	bne.n	6f4 <bootutil_verify_sig+0x30>
    if (alg.MBEDTLS_CONTEXT_MEMBER(len) != sizeof(ec_pubkey_oid) - 1 ||
     710:	9a06      	ldr	r2, [sp, #24]
     712:	2a07      	cmp	r2, #7
     714:	d1ee      	bne.n	6f4 <bootutil_verify_sig+0x30>
        memcmp(alg.MBEDTLS_CONTEXT_MEMBER(p), ec_pubkey_oid, sizeof(ec_pubkey_oid) - 1)) {
     716:	4929      	ldr	r1, [pc, #164]	; (7bc <bootutil_verify_sig+0xf8>)
     718:	9807      	ldr	r0, [sp, #28]
     71a:	f005 fab6 	bl	5c8a <memcmp>
    if (alg.MBEDTLS_CONTEXT_MEMBER(len) != sizeof(ec_pubkey_oid) - 1 ||
     71e:	2800      	cmp	r0, #0
     720:	d1e8      	bne.n	6f4 <bootutil_verify_sig+0x30>
    if (param.MBEDTLS_CONTEXT_MEMBER(len) != sizeof(ec_secp256r1_oid) - 1 ||
     722:	9a09      	ldr	r2, [sp, #36]	; 0x24
     724:	2a08      	cmp	r2, #8
     726:	d1e5      	bne.n	6f4 <bootutil_verify_sig+0x30>
        memcmp(param.MBEDTLS_CONTEXT_MEMBER(p), ec_secp256r1_oid, sizeof(ec_secp256r1_oid) - 1)) {
     728:	4925      	ldr	r1, [pc, #148]	; (7c0 <bootutil_verify_sig+0xfc>)
     72a:	980a      	ldr	r0, [sp, #40]	; 0x28
     72c:	f005 faad 	bl	5c8a <memcmp>
    if (param.MBEDTLS_CONTEXT_MEMBER(len) != sizeof(ec_secp256r1_oid) - 1 ||
     730:	2800      	cmp	r0, #0
     732:	d1df      	bne.n	6f4 <bootutil_verify_sig+0x30>
    if (mbedtls_asn1_get_bitstring_null(cp, end, &len)) {
     734:	aa04      	add	r2, sp, #16
     736:	4621      	mov	r1, r4
     738:	a803      	add	r0, sp, #12
     73a:	f004 fa5a 	bl	4bf2 <mbedtls_asn1_get_bitstring_null>
     73e:	2800      	cmp	r0, #0
     740:	d1d8      	bne.n	6f4 <bootutil_verify_sig+0x30>
    if (*cp + len != end) {
     742:	e9dd 3203 	ldrd	r3, r2, [sp, #12]
     746:	4413      	add	r3, r2
     748:	429c      	cmp	r4, r3
     74a:	d1d3      	bne.n	6f4 <bootutil_verify_sig+0x30>
    if (len != 2 * NUM_ECC_BYTES + 1) {
     74c:	2a41      	cmp	r2, #65	; 0x41
     74e:	d1d1      	bne.n	6f4 <bootutil_verify_sig+0x30>
    rc = bootutil_decode_sig(signature, sig, sig + slen);
     750:	443d      	add	r5, r7
    rc = mbedtls_asn1_get_tag(&cp, end, &len,
     752:	2330      	movs	r3, #48	; 0x30
     754:	aa05      	add	r2, sp, #20
     756:	4629      	mov	r1, r5
     758:	a804      	add	r0, sp, #16
     75a:	9704      	str	r7, [sp, #16]
     75c:	f004 fa35 	bl	4bca <mbedtls_asn1_get_tag>
    if (rc) {
     760:	2800      	cmp	r0, #0
     762:	d1c7      	bne.n	6f4 <bootutil_verify_sig+0x30>
    if (cp + len > end) {
     764:	e9dd 3204 	ldrd	r3, r2, [sp, #16]
     768:	4413      	add	r3, r2
     76a:	429d      	cmp	r5, r3
     76c:	d3c2      	bcc.n	6f4 <bootutil_verify_sig+0x30>
    rc = bootutil_read_bigint(signature, &cp, end);
     76e:	462a      	mov	r2, r5
     770:	a904      	add	r1, sp, #16
     772:	a808      	add	r0, sp, #32
     774:	f003 ffe3 	bl	473e <bootutil_read_bigint>
    if (rc) {
     778:	2800      	cmp	r0, #0
     77a:	d1bb      	bne.n	6f4 <bootutil_verify_sig+0x30>
    rc = bootutil_read_bigint(signature + NUM_ECC_BYTES, &cp, end);
     77c:	462a      	mov	r2, r5
     77e:	a904      	add	r1, sp, #16
     780:	a810      	add	r0, sp, #64	; 0x40
     782:	f003 ffdc 	bl	473e <bootutil_read_bigint>
    if (rc) {
     786:	2800      	cmp	r0, #0
     788:	d1b4      	bne.n	6f4 <bootutil_verify_sig+0x30>
    if (hlen != NUM_ECC_BYTES) {
     78a:	2e20      	cmp	r6, #32
     78c:	d1b2      	bne.n	6f4 <bootutil_verify_sig+0x30>

    bootutil_ecdsa_p256_init(&ctx);
#ifdef MCUBOOT_ECDSA_NEED_ASN1_SIG
    rc = bootutil_ecdsa_p256_verify(&ctx, pubkey, end - pubkey, hash, sig, slen);
#else
    rc = bootutil_ecdsa_p256_verify(&ctx, pubkey, end - pubkey, hash, signature,
     78e:	9c03      	ldr	r4, [sp, #12]
    (void)ctx;
    (void)pk_len;
    (void)sig_len;

    /* Only support uncompressed keys. */
    if (pk[0] != 0x04) {
     790:	7823      	ldrb	r3, [r4, #0]
     792:	2b04      	cmp	r3, #4
     794:	d1ae      	bne.n	6f4 <bootutil_verify_sig+0x30>
        return -1;
    }
    pk++;

    rc = uECC_verify(pk, hash, BOOTUTIL_CRYPTO_ECDSA_P256_HASH_SIZE, sig, uECC_secp256r1());
     796:	f000 fe0f 	bl	13b8 <uECC_secp256r1>
     79a:	ab08      	add	r3, sp, #32
     79c:	9000      	str	r0, [sp, #0]
     79e:	4632      	mov	r2, r6
     7a0:	4641      	mov	r1, r8
     7a2:	1c60      	adds	r0, r4, #1
     7a4:	f004 feed 	bl	5582 <uECC_verify>
    if (rc != TC_CRYPTO_SUCCESS) {
     7a8:	3801      	subs	r0, #1
     7aa:	bf18      	it	ne
     7ac:	f04f 30ff 	movne.w	r0, #4294967295
#endif /* CY_MBEDTLS_HW_ACCELERATION */

    bootutil_ecdsa_p256_drop(&ctx);

    return rc;
}
     7b0:	b018      	add	sp, #96	; 0x60
     7b2:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
     7b6:	bf00      	nop
     7b8:	0000667c 	.word	0x0000667c
     7bc:	00006b1e 	.word	0x00006b1e
     7c0:	00006b26 	.word	0x00006b26

000007c4 <boot_read_swap_size>:
    return -1;
}

int
boot_read_swap_size(int image_index, uint32_t *swap_size)
{
     7c4:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
     7c8:	b086      	sub	sp, #24
    uint8_t areas[2] = {
     7ca:	2302      	movs	r3, #2
    if (memcmp(magic, BOOT_IMG_MAGIC, BOOT_MAGIC_SZ) == 0) {
     7cc:	f8df 806c 	ldr.w	r8, [pc, #108]	; 83c <CONFIG_ISR_STACK_SIZE+0x3c>
    uint8_t areas[2] = {
     7d0:	f8ad 3000 	strh.w	r3, [sp]
{
     7d4:	460d      	mov	r5, r1
     7d6:	466f      	mov	r7, sp
    for (i = 0; i < sizeof(areas) / sizeof(areas[0]); i++) {
     7d8:	2600      	movs	r6, #0
        rc = flash_area_open(areas[i], fap);
     7da:	f817 0b01 	ldrb.w	r0, [r7], #1
     7de:	a901      	add	r1, sp, #4
     7e0:	f001 fa56 	bl	1c90 <flash_area_open>
        if (rc != 0) {
     7e4:	4604      	mov	r4, r0
     7e6:	b9a0      	cbnz	r0, 812 <CONFIG_ISR_STACK_SIZE+0x12>
        off = boot_magic_off(*fap);
     7e8:	9801      	ldr	r0, [sp, #4]
    return flash_area_get_size(fap) - BOOT_MAGIC_SZ;
     7ea:	6881      	ldr	r1, [r0, #8]
        rc = flash_area_read(*fap, off, magic, BOOT_MAGIC_SZ);
     7ec:	2310      	movs	r3, #16
     7ee:	aa02      	add	r2, sp, #8
     7f0:	3910      	subs	r1, #16
     7f2:	f005 f99f 	bl	5b34 <flash_area_read>
     7f6:	4604      	mov	r4, r0
        flash_area_close(*fap);
     7f8:	9801      	ldr	r0, [sp, #4]
     7fa:	f005 f99a 	bl	5b32 <flash_area_close>
        if (rc != 0) {
     7fe:	b944      	cbnz	r4, 812 <CONFIG_ISR_STACK_SIZE+0x12>
    if (memcmp(magic, BOOT_IMG_MAGIC, BOOT_MAGIC_SZ) == 0) {
     800:	2210      	movs	r2, #16
     802:	4641      	mov	r1, r8
     804:	a802      	add	r0, sp, #8
     806:	f005 fa40 	bl	5c8a <memcmp>
     80a:	b140      	cbz	r0, 81e <CONFIG_ISR_STACK_SIZE+0x1e>
    for (i = 0; i < sizeof(areas) / sizeof(areas[0]); i++) {
     80c:	b12e      	cbz	r6, 81a <CONFIG_ISR_STACK_SIZE+0x1a>
    return -1;
     80e:	f04f 34ff 	mov.w	r4, #4294967295
        rc = flash_area_read(fap, off, swap_size, sizeof *swap_size);
        flash_area_close(fap);
    }

    return rc;
}
     812:	4620      	mov	r0, r4
     814:	b006      	add	sp, #24
     816:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
     81a:	2601      	movs	r6, #1
     81c:	e7dd      	b.n	7da <boot_read_swap_size+0x16>
    return boot_swap_info_off(fap) - BOOT_MAX_ALIGN;
     81e:	9801      	ldr	r0, [sp, #4]
     820:	f005 fd05 	bl	622e <boot_swap_info_off>
        rc = flash_area_read(fap, off, swap_size, sizeof *swap_size);
     824:	2304      	movs	r3, #4
     826:	f1a0 0108 	sub.w	r1, r0, #8
     82a:	462a      	mov	r2, r5
     82c:	9801      	ldr	r0, [sp, #4]
     82e:	f005 f981 	bl	5b34 <flash_area_read>
     832:	4604      	mov	r4, r0
        flash_area_close(fap);
     834:	9801      	ldr	r0, [sp, #4]
     836:	f005 f97c 	bl	5b32 <flash_area_close>
     83a:	e7ea      	b.n	812 <CONFIG_ISR_STACK_SIZE+0x12>
     83c:	000069d0 	.word	0x000069d0

00000840 <boot_validate_slot.isra.0>:
 *         FIH_SUCCESS                      if image was successfully validated
 *         1 (or its fih_int encoded form)  if no bootloable image was found
 *         FIH_FAILURE                      on any errors
 */
static fih_int
boot_validate_slot(struct boot_loader_state *state, int slot,
     840:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
                   struct boot_status *bs)
{
    const struct flash_area *fap;
    struct image_header *hdr;
    int area_id;
    fih_int fih_rc = FIH_FAILURE;
     844:	4b38      	ldr	r3, [pc, #224]	; (928 <FIH_LABEL_FIH_CALL_END_294+0x80>)
boot_validate_slot(struct boot_loader_state *state, int slot,
     846:	b088      	sub	sp, #32
     848:	4606      	mov	r6, r0
    int rc;

    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
     84a:	2000      	movs	r0, #0
boot_validate_slot(struct boot_loader_state *state, int slot,
     84c:	460d      	mov	r5, r1
    fih_int fih_rc = FIH_FAILURE;
     84e:	681c      	ldr	r4, [r3, #0]
    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
     850:	f003 fed2 	bl	45f8 <flash_area_id_from_multi_image_slot>
    rc = flash_area_open(area_id, &fap);
     854:	a906      	add	r1, sp, #24
     856:	b2c0      	uxtb	r0, r0
     858:	f001 fa1a 	bl	1c90 <flash_area_open>
    if (rc != 0) {
     85c:	2800      	cmp	r0, #0
     85e:	d157      	bne.n	910 <FIH_LABEL_FIH_CALL_END_294+0x68>
    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
     860:	4629      	mov	r1, r5
     862:	f003 fec9 	bl	45f8 <flash_area_id_from_multi_image_slot>
     ((swap_type) == BOOT_SWAP_TYPE_PERM))

static inline struct image_header*
boot_img_hdr(struct boot_loader_state *state, size_t slot)
{
    return &BOOT_IMG(state, slot).hdr;
     866:	242c      	movs	r4, #44	; 0x2c
    rc = flash_area_open(area_id, &fap);
     868:	a907      	add	r1, sp, #28
     86a:	b2c0      	uxtb	r0, r0
     86c:	fb04 6405 	mla	r4, r4, r5, r6
     870:	f001 fa0e 	bl	1c90 <flash_area_open>
    if (rc != 0) {
     874:	2800      	cmp	r0, #0
     876:	d036      	beq.n	8e6 <FIH_LABEL_FIH_CALL_END_294+0x3e>
        FIH_RET(fih_rc);
    }

    hdr = boot_img_hdr(state, slot);
    if (boot_check_header_erased(state, slot) == 0 ||
        (hdr->ih_flags & IMAGE_F_NON_BOOTABLE)) {
     878:	f04f 082c 	mov.w	r8, #44	; 0x2c
     87c:	fb08 f805 	mul.w	r8, r8, r5
     880:	eb06 0708 	add.w	r7, r6, r8
     884:	6939      	ldr	r1, [r7, #16]
    if (boot_check_header_erased(state, slot) == 0 ||
     886:	f011 0110 	ands.w	r1, r1, #16
     88a:	d137      	bne.n	8fc <FIH_LABEL_FIH_CALL_END_294+0x54>

0000088c <FIH_LABEL_FIH_CALL_START_238>:
    FIH_CALL(bootutil_img_validate, fih_rc, BOOT_CURR_ENC(state), image_index,
     88c:	f44f 7380 	mov.w	r3, #256	; 0x100
     890:	9301      	str	r3, [sp, #4]
     892:	4b26      	ldr	r3, [pc, #152]	; (92c <FIH_LABEL_FIH_CALL_END_294+0x84>)
     894:	9300      	str	r3, [sp, #0]
     896:	4622      	mov	r2, r4
     898:	e9cd 1103 	strd	r1, r1, [sp, #12]
     89c:	9b06      	ldr	r3, [sp, #24]
     89e:	9102      	str	r1, [sp, #8]
     8a0:	4608      	mov	r0, r1
     8a2:	f7ff fe1d 	bl	4e0 <bootutil_img_validate>
     8a6:	4604      	mov	r4, r0

000008a8 <FIH_LABEL_FIH_CALL_END_294>:
    if (hdr->ih_magic != IMAGE_MAGIC) {
     8a8:	4b21      	ldr	r3, [pc, #132]	; (930 <FIH_LABEL_FIH_CALL_END_294+0x88>)
     8aa:	f856 2008 	ldr.w	r2, [r6, r8]
                       fih_rc, BOOT_CURR_IMG(state), slot);
    if (fih_eq(fih_rc, fih_int_encode(BOOT_HOOK_REGULAR)))
    {
        FIH_CALL(boot_image_check, fih_rc, state, hdr, fap, bs);
    }
    if (!boot_is_header_valid(hdr, fap) || fih_not_eq(fih_rc, FIH_SUCCESS)) {
     8ae:	9806      	ldr	r0, [sp, #24]
    if (hdr->ih_magic != IMAGE_MAGIC) {
     8b0:	429a      	cmp	r2, r3
     8b2:	d10c      	bne.n	8ce <FIH_LABEL_FIH_CALL_END_294+0x26>
    if (!boot_u32_safe_add(&size, hdr->ih_img_size, hdr->ih_hdr_size)) {
     8b4:	893a      	ldrh	r2, [r7, #8]
     8b6:	68fb      	ldr	r3, [r7, #12]
    if (a > UINT32_MAX - b) {
     8b8:	43d1      	mvns	r1, r2
     8ba:	428b      	cmp	r3, r1
     8bc:	d807      	bhi.n	8ce <FIH_LABEL_FIH_CALL_END_294+0x26>
        *dest = a + b;
     8be:	4413      	add	r3, r2
    if (size >= flash_area_get_size(fap)) {
     8c0:	6882      	ldr	r2, [r0, #8]
     8c2:	4293      	cmp	r3, r2
     8c4:	d203      	bcs.n	8ce <FIH_LABEL_FIH_CALL_END_294+0x26>
    if (!boot_is_header_valid(hdr, fap) || fih_not_eq(fih_rc, FIH_SUCCESS)) {
     8c6:	4b1b      	ldr	r3, [pc, #108]	; (934 <FIH_LABEL_FIH_CALL_END_294+0x8c>)
     8c8:	681b      	ldr	r3, [r3, #0]
     8ca:	42a3      	cmp	r3, r4
     8cc:	d01d      	beq.n	90a <FIH_LABEL_FIH_CALL_END_294+0x62>
        if ((slot != BOOT_PRIMARY_SLOT) || ARE_SLOTS_EQUIVALENT()) {
     8ce:	b345      	cbz	r5, 922 <FIH_LABEL_FIH_CALL_END_294+0x7a>
            flash_area_erase(fap, 0, flash_area_get_size(fap));
     8d0:	6882      	ldr	r2, [r0, #8]
     8d2:	2100      	movs	r1, #0
     8d4:	f005 f966 	bl	5ba4 <flash_area_erase>
            /* Image is invalid, erase it to prevent further unnecessary
             * attempts to validate and boot it.
             */
        }
#if !defined(__BOOTSIM__)
        BOOT_LOG_ERR("Image in the %s slot is not valid!",
     8d8:	4a17      	ldr	r2, [pc, #92]	; (938 <FIH_LABEL_FIH_CALL_END_294+0x90>)
     8da:	4818      	ldr	r0, [pc, #96]	; (93c <FIH_LABEL_FIH_CALL_END_294+0x94>)
     8dc:	2145      	movs	r1, #69	; 0x45
     8de:	f005 f91b 	bl	5b18 <z_log_minimal_printk>
        fih_rc = fih_int_encode(1);
     8e2:	2401      	movs	r4, #1
     8e4:	e011      	b.n	90a <FIH_LABEL_FIH_CALL_END_294+0x62>
    erased_val = flash_area_erased_val(fap);
     8e6:	9807      	ldr	r0, [sp, #28]
     8e8:	f005 f97c 	bl	5be4 <flash_area_erased_val>
     8ec:	4607      	mov	r7, r0
    flash_area_close(fap);
     8ee:	9807      	ldr	r0, [sp, #28]
     8f0:	f005 f91f 	bl	5b32 <flash_area_close>
boot_data_is_set_to(uint8_t val, void *data, size_t len)
     8f4:	1e63      	subs	r3, r4, #1
     8f6:	1ce2      	adds	r2, r4, #3
    for (i = 0; i < len; i++) {
     8f8:	4293      	cmp	r3, r2
     8fa:	d10d      	bne.n	918 <FIH_LABEL_FIH_CALL_END_294+0x70>
        if (slot != BOOT_PRIMARY_SLOT) {
     8fc:	2d00      	cmp	r5, #0
     8fe:	d0f0      	beq.n	8e2 <FIH_LABEL_FIH_CALL_END_294+0x3a>
            swap_erase_trailer_sectors(state, fap);
     900:	9906      	ldr	r1, [sp, #24]
     902:	4630      	mov	r0, r6
     904:	f004 f841 	bl	498a <swap_erase_trailer_sectors>
        fih_rc = fih_int_encode(1);
     908:	462c      	mov	r4, r5
        }
    }
#endif

out:
    flash_area_close(fap);
     90a:	9806      	ldr	r0, [sp, #24]
     90c:	f005 f911 	bl	5b32 <flash_area_close>

    FIH_RET(fih_rc);
}
     910:	4620      	mov	r0, r4
     912:	b008      	add	sp, #32
     914:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
        if (val != p[i]) {
     918:	f813 1f01 	ldrb.w	r1, [r3, #1]!
     91c:	42b9      	cmp	r1, r7
     91e:	d0eb      	beq.n	8f8 <FIH_LABEL_FIH_CALL_END_294+0x50>
     920:	e7aa      	b.n	878 <boot_validate_slot.isra.0+0x38>
        BOOT_LOG_ERR("Image in the %s slot is not valid!",
     922:	4a07      	ldr	r2, [pc, #28]	; (940 <FIH_LABEL_FIH_CALL_END_294+0x98>)
     924:	e7d9      	b.n	8da <FIH_LABEL_FIH_CALL_END_294+0x32>
     926:	bf00      	nop
     928:	20000000 	.word	0x20000000
     92c:	20000efc 	.word	0x20000efc
     930:	96f3b83d 	.word	0x96f3b83d
     934:	20000154 	.word	0x20000154
     938:	00006b2f 	.word	0x00006b2f
     93c:	00006b41 	.word	0x00006b41
     940:	00006b39 	.word	0x00006b39

00000944 <boot_swap_image>:
 *
 * @return                      0 on success; nonzero on failure.
 */
static int
boot_swap_image(struct boot_loader_state *state, struct boot_status *bs)
{
     944:	b573      	push	{r0, r1, r4, r5, r6, lr}
     946:	460d      	mov	r5, r1
     948:	4604      	mov	r4, r0
    uint8_t image_index;
    int rc;

    /* FIXME: just do this if asked by user? */

    size = copy_size = 0;
     94a:	2100      	movs	r1, #0
    image_index = BOOT_CURR_IMG(state);

    if (boot_status_is_reset(bs)) {
     94c:	4628      	mov	r0, r5
    size = copy_size = 0;
     94e:	e9cd 1100 	strd	r1, r1, [sp]
    if (boot_status_is_reset(bs)) {
     952:	f003 ffd9 	bl	4908 <boot_status_is_reset>
     956:	b330      	cbz	r0, 9a6 <boot_swap_image+0x62>
        /*
         * No swap ever happened, so need to find the largest image which
         * will be used to determine the amount of sectors to swap.
         */
        hdr = boot_img_hdr(state, BOOT_PRIMARY_SLOT);
        if (hdr->ih_magic == IMAGE_MAGIC) {
     958:	4e16      	ldr	r6, [pc, #88]	; (9b4 <boot_swap_image+0x70>)
     95a:	6823      	ldr	r3, [r4, #0]
     95c:	42b3      	cmp	r3, r6
     95e:	d103      	bne.n	968 <boot_swap_image+0x24>
            rc = boot_read_image_size(state, BOOT_PRIMARY_SLOT, &copy_size);
     960:	aa01      	add	r2, sp, #4
     962:	4620      	mov	r0, r4
     964:	f003 ff65 	bl	4832 <boot_read_image_size.isra.0>
            memset(bs->enckey[0], 0xff, BOOT_ENC_KEY_ALIGN_SIZE);
        }
#endif

        hdr = boot_img_hdr(state, BOOT_SECONDARY_SLOT);
        if (hdr->ih_magic == IMAGE_MAGIC) {
     968:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
     96a:	42b3      	cmp	r3, r6
     96c:	d104      	bne.n	978 <boot_swap_image+0x34>
            rc = boot_read_image_size(state, BOOT_SECONDARY_SLOT, &size);
     96e:	466a      	mov	r2, sp
     970:	2101      	movs	r1, #1
     972:	4620      	mov	r0, r4
     974:	f003 ff5d 	bl	4832 <boot_read_image_size.isra.0>
        } else {
            memset(bs->enckey[1], 0xff, BOOT_ENC_KEY_ALIGN_SIZE);
        }
#endif

        if (size > copy_size) {
     978:	e9dd 3200 	ldrd	r3, r2, [sp]
     97c:	4293      	cmp	r3, r2
            copy_size = size;
     97e:	bf88      	it	hi
     980:	9301      	strhi	r3, [sp, #4]
        }

        bs->swap_size = copy_size;
     982:	9b01      	ldr	r3, [sp, #4]
     984:	60ab      	str	r3, [r5, #8]
            }
        }
#endif
    }

    swap_run(state, bs, copy_size);
     986:	9a01      	ldr	r2, [sp, #4]
     988:	4629      	mov	r1, r5
     98a:	4620      	mov	r0, r4
     98c:	f000 fb34 	bl	ff8 <swap_run>

#ifdef MCUBOOT_VALIDATE_PRIMARY_SLOT
    extern int boot_status_fails;
    if (boot_status_fails > 0) {
     990:	4b09      	ldr	r3, [pc, #36]	; (9b8 <boot_swap_image+0x74>)
     992:	681a      	ldr	r2, [r3, #0]
     994:	2a00      	cmp	r2, #0
     996:	dd03      	ble.n	9a0 <boot_swap_image+0x5c>
        BOOT_LOG_WRN("%d status write fails performing the swap",
     998:	4808      	ldr	r0, [pc, #32]	; (9bc <boot_swap_image+0x78>)
     99a:	2157      	movs	r1, #87	; 0x57
     99c:	f005 f8bc 	bl	5b18 <z_log_minimal_printk>
                     boot_status_fails);
    }
#endif

    return 0;
}
     9a0:	2000      	movs	r0, #0
     9a2:	b002      	add	sp, #8
     9a4:	bd70      	pop	{r4, r5, r6, pc}
        rc = boot_read_swap_size(image_index, &bs->swap_size);
     9a6:	f105 0108 	add.w	r1, r5, #8
     9aa:	f7ff ff0b 	bl	7c4 <boot_read_swap_size>
        copy_size = bs->swap_size;
     9ae:	68ab      	ldr	r3, [r5, #8]
     9b0:	9301      	str	r3, [sp, #4]
     9b2:	e7e8      	b.n	986 <boot_swap_image+0x42>
     9b4:	96f3b83d 	.word	0x96f3b83d
     9b8:	20000db8 	.word	0x20000db8
     9bc:	00006b69 	.word	0x00006b69

000009c0 <boot_copy_region>:
{
     9c0:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
        rc = flash_area_read(fap_src, off_src + bytes_copied, buf, chunk_sz);
     9c4:	f8df b070 	ldr.w	fp, [pc, #112]	; a38 <boot_copy_region+0x78>
     9c8:	4c1c      	ldr	r4, [pc, #112]	; (a3c <boot_copy_region+0x7c>)
     9ca:	4d1d      	ldr	r5, [pc, #116]	; (a40 <boot_copy_region+0x80>)
{
     9cc:	4688      	mov	r8, r1
     9ce:	4691      	mov	r9, r2
     9d0:	469a      	mov	sl, r3
    bytes_copied = 0;
     9d2:	2600      	movs	r6, #0
    while (bytes_copied < sz) {
     9d4:	9b0b      	ldr	r3, [sp, #44]	; 0x2c
     9d6:	429e      	cmp	r6, r3
     9d8:	d301      	bcc.n	9de <boot_copy_region+0x1e>
    return 0;
     9da:	2000      	movs	r0, #0
     9dc:	e00f      	b.n	9fe <boot_copy_region+0x3e>
        if (sz - bytes_copied > sizeof buf) {
     9de:	9b0b      	ldr	r3, [sp, #44]	; 0x2c
        rc = flash_area_read(fap_src, off_src + bytes_copied, buf, chunk_sz);
     9e0:	4a15      	ldr	r2, [pc, #84]	; (a38 <boot_copy_region+0x78>)
        if (sz - bytes_copied > sizeof buf) {
     9e2:	1b9f      	subs	r7, r3, r6
     9e4:	f5b7 6f80 	cmp.w	r7, #1024	; 0x400
     9e8:	bf28      	it	cs
     9ea:	f44f 6780 	movcs.w	r7, #1024	; 0x400
        rc = flash_area_read(fap_src, off_src + bytes_copied, buf, chunk_sz);
     9ee:	463b      	mov	r3, r7
     9f0:	eb06 010a 	add.w	r1, r6, sl
     9f4:	4640      	mov	r0, r8
     9f6:	f005 f89d 	bl	5b34 <flash_area_read>
        if (rc != 0) {
     9fa:	b110      	cbz	r0, a02 <boot_copy_region+0x42>
            return BOOT_EFLASH;
     9fc:	2001      	movs	r0, #1
}
     9fe:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
        rc = flash_area_write(fap_dst, off_dst + bytes_copied, buf, chunk_sz);
     a02:	990a      	ldr	r1, [sp, #40]	; 0x28
     a04:	463b      	mov	r3, r7
     a06:	465a      	mov	r2, fp
     a08:	1871      	adds	r1, r6, r1
     a0a:	4648      	mov	r0, r9
     a0c:	f005 f8ae 	bl	5b6c <flash_area_write>
        if (rc != 0) {
     a10:	2800      	cmp	r0, #0
     a12:	d1f3      	bne.n	9fc <boot_copy_region+0x3c>
     a14:	f8c4 5600 	str.w	r5, [r4, #1536]	; 0x600
        bytes_copied += chunk_sz;
     a18:	443e      	add	r6, r7
     a1a:	f8c4 5604 	str.w	r5, [r4, #1540]	; 0x604
     a1e:	f8c4 5608 	str.w	r5, [r4, #1544]	; 0x608
     a22:	f8c4 560c 	str.w	r5, [r4, #1548]	; 0x60c
     a26:	f8c4 5610 	str.w	r5, [r4, #1552]	; 0x610
     a2a:	f8c4 5614 	str.w	r5, [r4, #1556]	; 0x614
     a2e:	f8c4 5618 	str.w	r5, [r4, #1560]	; 0x618
     a32:	f8c4 561c 	str.w	r5, [r4, #1564]	; 0x61c
        MCUBOOT_WATCHDOG_FEED();
     a36:	e7cd      	b.n	9d4 <boot_copy_region+0x14>
     a38:	200001b8 	.word	0x200001b8
     a3c:	40010000 	.word	0x40010000
     a40:	6e524635 	.word	0x6e524635

00000a44 <context_boot_go>:
#endif
}

fih_int
context_boot_go(struct boot_loader_state *state, struct boot_rsp *rsp)
{
     a44:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
    size_t slot;
    struct boot_status bs;
    int rc = -1;
    fih_int fih_rc = FIH_FAILURE;
     a48:	4b8e      	ldr	r3, [pc, #568]	; (c84 <FIH_LABEL_FIH_CALL_END_2417+0x46>)
     a4a:	681e      	ldr	r6, [r3, #0]
        boot_enc_zeroize(BOOT_CURR_ENC(state));
#endif

        image_index = BOOT_CURR_IMG(state);

        BOOT_IMG(state, BOOT_PRIMARY_SLOT).sectors =
     a4c:	4b8e      	ldr	r3, [pc, #568]	; (c88 <FIH_LABEL_FIH_CALL_END_2417+0x4a>)
     a4e:	6243      	str	r3, [r0, #36]	; 0x24
{
     a50:	460f      	mov	r7, r1
            primary_slot_sectors[image_index];
        BOOT_IMG(state, BOOT_SECONDARY_SLOT).sectors =
     a52:	4b8e      	ldr	r3, [pc, #568]	; (c8c <FIH_LABEL_FIH_CALL_END_2417+0x4e>)
     a54:	6503      	str	r3, [r0, #80]	; 0x50

        /* Open primary and secondary image areas for the duration
         * of this call.
         */
        for (slot = 0; slot < BOOT_NUM_SLOTS; slot++) {
            fa_id = flash_area_id_from_multi_image_slot(image_index, slot);
     a56:	2100      	movs	r1, #0
{
     a58:	b085      	sub	sp, #20
     a5a:	4604      	mov	r4, r0
            fa_id = flash_area_id_from_multi_image_slot(image_index, slot);
     a5c:	4608      	mov	r0, r1
     a5e:	f003 fdcb 	bl	45f8 <flash_area_id_from_multi_image_slot>
            rc = flash_area_open(fa_id, &BOOT_IMG_AREA(state, slot));
     a62:	f104 0120 	add.w	r1, r4, #32
     a66:	b2c0      	uxtb	r0, r0
     a68:	f001 f912 	bl	1c90 <flash_area_open>
            fa_id = flash_area_id_from_multi_image_slot(image_index, slot);
     a6c:	2101      	movs	r1, #1
     a6e:	2000      	movs	r0, #0
     a70:	f003 fdc2 	bl	45f8 <flash_area_id_from_multi_image_slot>
            rc = flash_area_open(fa_id, &BOOT_IMG_AREA(state, slot));
     a74:	f104 014c 	add.w	r1, r4, #76	; 0x4c
     a78:	b2c0      	uxtb	r0, r0
     a7a:	f001 f909 	bl	1c90 <flash_area_open>
     a7e:	4605      	mov	r5, r0
    rc = boot_read_sectors(state);
     a80:	4620      	mov	r0, r4
     a82:	f003 ff17 	bl	48b4 <boot_read_sectors>
    if (rc != 0) {
     a86:	4680      	mov	r8, r0
     a88:	b968      	cbnz	r0, aa6 <context_boot_go+0x62>
    rc = boot_read_image_headers(state, false, NULL);
     a8a:	2200      	movs	r2, #0
     a8c:	4611      	mov	r1, r2
     a8e:	4620      	mov	r0, r4
     a90:	f003 feb7 	bl	4802 <boot_read_image_headers>
    if (rc != 0) {
     a94:	4680      	mov	r8, r0
     a96:	b300      	cbz	r0, ada <context_boot_go+0x96>
        BOOT_LOG_WRN("Failed reading image headers; Image=%u",
     a98:	487d      	ldr	r0, [pc, #500]	; (c90 <FIH_LABEL_FIH_CALL_END_2417+0x52>)
     a9a:	2200      	movs	r2, #0
     a9c:	2157      	movs	r1, #87	; 0x57
            BOOT_LOG_WRN("Failed reading boot status; Image=%u",
     a9e:	f005 f83b 	bl	5b18 <z_log_minimal_printk>
        BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_NONE;
     aa2:	2301      	movs	r3, #1
     aa4:	e091      	b.n	bca <FIH_LABEL_FIH_CALL_END_2204+0xe>
        BOOT_LOG_WRN("Failed reading sectors; BOOT_MAX_IMG_SECTORS=%d"
     aa6:	487b      	ldr	r0, [pc, #492]	; (c94 <FIH_LABEL_FIH_CALL_END_2417+0x56>)
     aa8:	2280      	movs	r2, #128	; 0x80
     aaa:	2157      	movs	r1, #87	; 0x57
     aac:	f005 f834 	bl	5b18 <z_log_minimal_printk>
        BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_NONE;
     ab0:	2301      	movs	r3, #1
        if (rc == BOOT_EFLASH)
     ab2:	4598      	cmp	r8, r3
        BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_NONE;
     ab4:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
        if (rc == BOOT_EFLASH)
     ab8:	d1e7      	bne.n	a8a <context_boot_go+0x46>
#endif

        /* Determine swap type and complete swap if it has been aborted. */
        boot_prepare_image_for_update(state, &bs);

        if (BOOT_IS_UPGRADE(BOOT_SWAP_TYPE(state))) {
     aba:	f894 3058 	ldrb.w	r3, [r4, #88]	; 0x58
        /* Indicate that swap is not aborted */
        boot_status_reset(&bs);
#endif /* (BOOT_IMAGE_NUMBER > 1) */

        /* Set the previously determined swap type */
        bs.swap_type = BOOT_SWAP_TYPE(state);
     abe:	f88d 3007 	strb.w	r3, [sp, #7]

        switch (BOOT_SWAP_TYPE(state)) {
     ac2:	2b04      	cmp	r3, #4
     ac4:	f200 8084 	bhi.w	bd0 <FIH_LABEL_FIH_CALL_END_2204+0x14>
     ac8:	2b01      	cmp	r3, #1
     aca:	f200 8088 	bhi.w	bde <FIH_LABEL_FIH_CALL_END_2204+0x22>
     ace:	f000 809f 	beq.w	c10 <FIH_LABEL_FIH_CALL_END_2204+0x54>
            }
#endif /* !MCUBOOT_OVERWRITE_ONLY */
            break;

        default:
            BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_PANIC;
     ad2:	23ff      	movs	r3, #255	; 0xff
     ad4:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
     ad8:	e09a      	b.n	c10 <FIH_LABEL_FIH_CALL_END_2204+0x54>
    if (boot_slots_compatible(state)) {
     ada:	4620      	mov	r0, r4
     adc:	f000 f9a4 	bl	e28 <boot_slots_compatible>
     ae0:	2800      	cmp	r0, #0
     ae2:	d0de      	beq.n	aa2 <context_boot_go+0x5e>
        boot_status_reset(bs);
     ae4:	4668      	mov	r0, sp
     ae6:	f003 ff06 	bl	48f6 <boot_status_reset>
        rc = swap_read_status(state, bs);
     aea:	4669      	mov	r1, sp
     aec:	4620      	mov	r0, r4
     aee:	f003 ffa1 	bl	4a34 <swap_read_status>
        if (rc != 0) {
     af2:	b118      	cbz	r0, afc <context_boot_go+0xb8>
            BOOT_LOG_WRN("Failed reading boot status; Image=%u",
     af4:	4868      	ldr	r0, [pc, #416]	; (c98 <FIH_LABEL_FIH_CALL_END_2417+0x5a>)
     af6:	4642      	mov	r2, r8
     af8:	2157      	movs	r1, #87	; 0x57
     afa:	e7d0      	b.n	a9e <context_boot_go+0x5a>
        rc = boot_read_image_headers(state, !boot_status_is_reset(bs), bs);
     afc:	4668      	mov	r0, sp
     afe:	f003 ff03 	bl	4908 <boot_status_is_reset>
     b02:	f080 0101 	eor.w	r1, r0, #1
     b06:	466a      	mov	r2, sp
     b08:	b2c9      	uxtb	r1, r1
     b0a:	4620      	mov	r0, r4
     b0c:	f003 fe79 	bl	4802 <boot_read_image_headers>
        if (rc != 0) {
     b10:	4602      	mov	r2, r0
     b12:	2800      	cmp	r0, #0
     b14:	d1c0      	bne.n	a98 <context_boot_go+0x54>
        if (!boot_status_is_reset(bs)) {
     b16:	4668      	mov	r0, sp
     b18:	f003 fef6 	bl	4908 <boot_status_is_reset>
     b1c:	4680      	mov	r8, r0
     b1e:	bb60      	cbnz	r0, b7a <context_boot_go+0x136>
    rc = boot_swap_image(state, bs);
     b20:	4669      	mov	r1, sp
     b22:	4620      	mov	r0, r4
     b24:	f7ff ff0e 	bl	944 <boot_swap_image>
    BOOT_SWAP_TYPE(state) = bs->swap_type;
     b28:	f89d 3007 	ldrb.w	r3, [sp, #7]
     b2c:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
    if (bs->swap_type == BOOT_SWAP_TYPE_REVERT ||
     b30:	3b03      	subs	r3, #3
     b32:	2b01      	cmp	r3, #1
     b34:	d806      	bhi.n	b44 <context_boot_go+0x100>
        rc = swap_set_image_ok(BOOT_CURR_IMG(state));
     b36:	4640      	mov	r0, r8
     b38:	f003 ffca 	bl	4ad0 <swap_set_image_ok>
        if (rc != 0) {
     b3c:	b110      	cbz	r0, b44 <context_boot_go+0x100>
            BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_PANIC;
     b3e:	23ff      	movs	r3, #255	; 0xff
     b40:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
    if (BOOT_IS_UPGRADE(bs->swap_type)) {
     b44:	f89d 3007 	ldrb.w	r3, [sp, #7]
     b48:	3b02      	subs	r3, #2
     b4a:	2b02      	cmp	r3, #2
     b4c:	d80b      	bhi.n	b66 <context_boot_go+0x122>
        rc = swap_set_copy_done(BOOT_CURR_IMG(state));
     b4e:	2000      	movs	r0, #0
     b50:	f003 ffac 	bl	4aac <swap_set_copy_done>
        if (rc != 0) {
     b54:	b138      	cbz	r0, b66 <context_boot_go+0x122>
            BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_PANIC;
     b56:	23ff      	movs	r3, #255	; 0xff
     b58:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
        BOOT_LOG_ERR("panic!");
     b5c:	484f      	ldr	r0, [pc, #316]	; (c9c <FIH_LABEL_FIH_CALL_END_2417+0x5e>)
     b5e:	2145      	movs	r1, #69	; 0x45
     b60:	f004 ffda 	bl	5b18 <z_log_minimal_printk>
        while (1) {}
     b64:	e7fe      	b.n	b64 <context_boot_go+0x120>
    if (BOOT_SWAP_TYPE(state) == BOOT_SWAP_TYPE_PANIC) {
     b66:	f894 3058 	ldrb.w	r3, [r4, #88]	; 0x58
     b6a:	2bff      	cmp	r3, #255	; 0xff
     b6c:	d0f6      	beq.n	b5c <context_boot_go+0x118>
            rc = boot_read_image_headers(state, false, bs);
     b6e:	466a      	mov	r2, sp
     b70:	2100      	movs	r1, #0
     b72:	4620      	mov	r0, r4
     b74:	f003 fe45 	bl	4802 <boot_read_image_headers>
            BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_NONE;
     b78:	e793      	b.n	aa2 <context_boot_go+0x5e>
            if (bs->swap_type == BOOT_SWAP_TYPE_NONE) {
     b7a:	f89d 9007 	ldrb.w	r9, [sp, #7]
     b7e:	f1b9 0f01 	cmp.w	r9, #1
     b82:	d117      	bne.n	bb4 <FIH_LABEL_FIH_CALL_START_2184>
    swap_type = boot_swap_type_multi(BOOT_CURR_IMG(state));
     b84:	4610      	mov	r0, r2
     b86:	f002 fce3 	bl	3550 <boot_swap_type_multi>
    if (BOOT_IS_UPGRADE(swap_type)) {
     b8a:	1e83      	subs	r3, r0, #2
     b8c:	2b02      	cmp	r3, #2
    swap_type = boot_swap_type_multi(BOOT_CURR_IMG(state));
     b8e:	4680      	mov	r8, r0
    if (BOOT_IS_UPGRADE(swap_type)) {
     b90:	d80d      	bhi.n	bae <FIH_LABEL_FIH_CALL_END_2119+0x14>

00000b92 <FIH_LABEL_FIH_CALL_START_2095>:
        FIH_CALL(boot_validate_slot, fih_rc, state, BOOT_SECONDARY_SLOT, bs);
     b92:	4649      	mov	r1, r9
     b94:	4620      	mov	r0, r4
     b96:	f7ff fe53 	bl	840 <boot_validate_slot.isra.0>

00000b9a <FIH_LABEL_FIH_CALL_END_2119>:
        if (fih_not_eq(fih_rc, FIH_SUCCESS)) {
     b9a:	4b41      	ldr	r3, [pc, #260]	; (ca0 <FIH_LABEL_FIH_CALL_END_2417+0x62>)
     b9c:	681b      	ldr	r3, [r3, #0]
     b9e:	4298      	cmp	r0, r3
     ba0:	d005      	beq.n	bae <FIH_LABEL_FIH_CALL_END_2119+0x14>
                swap_type = BOOT_SWAP_TYPE_FAIL;
     ba2:	2801      	cmp	r0, #1
     ba4:	bf0c      	ite	eq
     ba6:	f04f 0801 	moveq.w	r8, #1
     baa:	f04f 0805 	movne.w	r8, #5
                BOOT_SWAP_TYPE(state) = boot_validated_swap_type(state, bs);
     bae:	f884 8058 	strb.w	r8, [r4, #88]	; 0x58
     bb2:	e782      	b.n	aba <context_boot_go+0x76>

00000bb4 <FIH_LABEL_FIH_CALL_START_2184>:
                FIH_CALL(boot_validate_slot, fih_rc,
     bb4:	2101      	movs	r1, #1
     bb6:	4620      	mov	r0, r4
     bb8:	f7ff fe42 	bl	840 <boot_validate_slot.isra.0>

00000bbc <FIH_LABEL_FIH_CALL_END_2204>:
                if (fih_not_eq(fih_rc, FIH_SUCCESS)) {
     bbc:	4b38      	ldr	r3, [pc, #224]	; (ca0 <FIH_LABEL_FIH_CALL_END_2417+0x62>)
     bbe:	681b      	ldr	r3, [r3, #0]
     bc0:	4298      	cmp	r0, r3
                    BOOT_SWAP_TYPE(state) = bs->swap_type;
     bc2:	bf0c      	ite	eq
     bc4:	f89d 3007 	ldrbeq.w	r3, [sp, #7]
                    BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_FAIL;
     bc8:	2305      	movne	r3, #5
        BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_NONE;
     bca:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
     bce:	e774      	b.n	aba <context_boot_go+0x76>
        switch (BOOT_SWAP_TYPE(state)) {
     bd0:	2b05      	cmp	r3, #5
     bd2:	f47f af7e 	bne.w	ad2 <context_boot_go+0x8e>
            rc = swap_set_image_ok(BOOT_CURR_IMG(state));
     bd6:	2000      	movs	r0, #0
     bd8:	f003 ff7a 	bl	4ad0 <swap_set_image_ok>
     bdc:	e013      	b.n	c06 <FIH_LABEL_FIH_CALL_END_2204+0x4a>
        rc = boot_swap_image(state, bs);
     bde:	4669      	mov	r1, sp
     be0:	4620      	mov	r0, r4
     be2:	f7ff feaf 	bl	944 <boot_swap_image>
    swap_type = BOOT_SWAP_TYPE(state);
     be6:	f894 3058 	ldrb.w	r3, [r4, #88]	; 0x58
    if (swap_type == BOOT_SWAP_TYPE_REVERT ||
     bea:	1eda      	subs	r2, r3, #3
     bec:	2a01      	cmp	r2, #1
        rc = boot_swap_image(state, bs);
     bee:	4605      	mov	r5, r0
    if (swap_type == BOOT_SWAP_TYPE_REVERT ||
     bf0:	d80c      	bhi.n	c0c <FIH_LABEL_FIH_CALL_END_2204+0x50>
        rc = swap_set_image_ok(BOOT_CURR_IMG(state));
     bf2:	2000      	movs	r0, #0
     bf4:	f003 ff6c 	bl	4ad0 <swap_set_image_ok>
        if (rc != 0) {
     bf8:	4605      	mov	r5, r0
     bfa:	2800      	cmp	r0, #0
     bfc:	f47f af69 	bne.w	ad2 <context_boot_go+0x8e>
        rc = swap_set_copy_done(BOOT_CURR_IMG(state));
     c00:	2000      	movs	r0, #0
     c02:	f003 ff53 	bl	4aac <swap_set_copy_done>
            if (rc != 0) {
     c06:	4605      	mov	r5, r0
     c08:	b110      	cbz	r0, c10 <FIH_LABEL_FIH_CALL_END_2204+0x54>
     c0a:	e762      	b.n	ad2 <context_boot_go+0x8e>
    if (BOOT_IS_UPGRADE(swap_type)) {
     c0c:	2b02      	cmp	r3, #2
     c0e:	d0f7      	beq.n	c00 <FIH_LABEL_FIH_CALL_END_2204+0x44>
        }

        if (BOOT_SWAP_TYPE(state) == BOOT_SWAP_TYPE_PANIC) {
     c10:	f894 3058 	ldrb.w	r3, [r4, #88]	; 0x58
     c14:	2bff      	cmp	r3, #255	; 0xff
     c16:	d104      	bne.n	c22 <FIH_LABEL_FIH_CALL_END_2204+0x66>
            BOOT_LOG_ERR("panic!");
     c18:	4820      	ldr	r0, [pc, #128]	; (c9c <FIH_LABEL_FIH_CALL_END_2417+0x5e>)
     c1a:	2145      	movs	r1, #69	; 0x45
     c1c:	f004 ff7c 	bl	5b18 <z_log_minimal_printk>
            assert(0);

            /* Loop forever... */
            FIH_PANIC;
     c20:	e7fe      	b.n	c20 <FIH_LABEL_FIH_CALL_END_2204+0x64>
#if BOOT_IMAGE_NUMBER > 1
        if (state->img_mask[BOOT_CURR_IMG(state)]) {
            continue;
        }
#endif
        if (BOOT_SWAP_TYPE(state) != BOOT_SWAP_TYPE_NONE) {
     c22:	2b01      	cmp	r3, #1
     c24:	d006      	beq.n	c34 <FIH_LABEL_FIH_CALL_START_2401>
            /* Attempt to read an image header from each slot. Ensure that image
             * headers in slots are aligned with headers in boot_data.
             */
            rc = boot_read_image_headers(state, false, &bs);
     c26:	466a      	mov	r2, sp
     c28:	2100      	movs	r1, #0
     c2a:	4620      	mov	r0, r4
     c2c:	f003 fde9 	bl	4802 <boot_read_image_headers>
            if (rc != 0) {
     c30:	4605      	mov	r5, r0
     c32:	b9d0      	cbnz	r0, c6a <FIH_LABEL_FIH_CALL_END_2417+0x2c>

00000c34 <FIH_LABEL_FIH_CALL_START_2401>:
	 * primary.
	 */
	if (BOOT_CURR_IMG(state) == 0)
#endif
	{
            FIH_CALL(boot_validate_slot, fih_rc, state, BOOT_PRIMARY_SLOT, NULL);
     c34:	2100      	movs	r1, #0
     c36:	4620      	mov	r0, r4
     c38:	f7ff fe02 	bl	840 <boot_validate_slot.isra.0>
     c3c:	4606      	mov	r6, r0

00000c3e <FIH_LABEL_FIH_CALL_END_2417>:
            if (fih_not_eq(fih_rc, FIH_SUCCESS)) {
     c3e:	f8df 8060 	ldr.w	r8, [pc, #96]	; ca0 <FIH_LABEL_FIH_CALL_END_2417+0x62>
     c42:	f8d8 3000 	ldr.w	r3, [r8]
     c46:	4298      	cmp	r0, r3
     c48:	d10f      	bne.n	c6a <FIH_LABEL_FIH_CALL_END_2417+0x2c>
    /*
     * Since the boot_status struct stores plaintext encryption keys, reset
     * them here to avoid the possibility of jumping into an image that could
     * easily recover them.
     */
    memset(&bs, 0, sizeof(struct boot_status));
     c4a:	2210      	movs	r2, #16
     c4c:	2100      	movs	r1, #0
     c4e:	4668      	mov	r0, sp
     c50:	f005 f837 	bl	5cc2 <memset>
    rsp->br_flash_dev_id = flash_area_get_device_id(BOOT_IMG_AREA(state, active_slot));
     c54:	6a20      	ldr	r0, [r4, #32]
     c56:	f003 fcd8 	bl	460a <flash_area_get_device_id>
     c5a:	7138      	strb	r0, [r7, #4]
 */
int flash_area_sector_from_off(off_t off, struct flash_sector *sector);

static inline uint32_t flash_area_get_off(const struct flash_area *fa)
{
	return (uint32_t)fa->fa_off;
     c5c:	6a23      	ldr	r3, [r4, #32]

    fill_rsp(state, rsp);

    fih_rc = FIH_SUCCESS;
     c5e:	f8d8 6000 	ldr.w	r6, [r8]
    rsp->br_image_off = boot_img_slot_off(state, active_slot);
     c62:	685b      	ldr	r3, [r3, #4]
     c64:	60bb      	str	r3, [r7, #8]
    rsp->br_hdr = boot_img_hdr(state, active_slot);
     c66:	603c      	str	r4, [r7, #0]
        rc = boot_add_shared_data(state, BOOT_PRIMARY_SLOT);
     c68:	2500      	movs	r5, #0
            flash_area_close(BOOT_IMG_AREA(state, BOOT_NUM_SLOTS - 1 - slot));
     c6a:	6ce0      	ldr	r0, [r4, #76]	; 0x4c
     c6c:	f004 ff61 	bl	5b32 <flash_area_close>
     c70:	6a20      	ldr	r0, [r4, #32]
     c72:	f004 ff5e 	bl	5b32 <flash_area_close>
    if (rc) {
        fih_rc = fih_int_encode(rc);
    }

    FIH_RET(fih_rc);
}
     c76:	2d00      	cmp	r5, #0
     c78:	bf14      	ite	ne
     c7a:	4628      	movne	r0, r5
     c7c:	4630      	moveq	r0, r6
     c7e:	b005      	add	sp, #20
     c80:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
     c84:	20000000 	.word	0x20000000
     c88:	200005b8 	.word	0x200005b8
     c8c:	200009b8 	.word	0x200009b8
     c90:	00006bda 	.word	0x00006bda
     c94:	00006b98 	.word	0x00006b98
     c98:	00006c06 	.word	0x00006c06
     c9c:	00006c30 	.word	0x00006c30
     ca0:	20000154 	.word	0x20000154

00000ca4 <boot_go>:
 *
 * @return                      FIH_SUCCESS on success; nonzero on failure.
 */
fih_int
boot_go(struct boot_rsp *rsp)
{
     ca4:	b538      	push	{r3, r4, r5, lr}
void boot_state_clear(struct boot_loader_state *state)
{
    if (state != NULL) {
        memset(state, 0, sizeof(struct boot_loader_state));
    } else {
        memset(&boot_data, 0, sizeof(struct boot_loader_state));
     ca6:	4d06      	ldr	r5, [pc, #24]	; (cc0 <FIH_LABEL_FIH_CALL_END_3095+0x4>)
{
     ca8:	4604      	mov	r4, r0
        memset(&boot_data, 0, sizeof(struct boot_loader_state));
     caa:	2260      	movs	r2, #96	; 0x60
     cac:	2100      	movs	r1, #0
     cae:	4628      	mov	r0, r5
     cb0:	f005 f807 	bl	5cc2 <memset>

00000cb4 <FIH_LABEL_FIH_CALL_START_3080>:
    FIH_CALL(context_boot_go, fih_rc, &boot_data, rsp);
     cb4:	4621      	mov	r1, r4
     cb6:	4628      	mov	r0, r5
     cb8:	f7ff fec4 	bl	a44 <context_boot_go>

00000cbc <FIH_LABEL_FIH_CALL_END_3095>:
}
     cbc:	bd38      	pop	{r3, r4, r5, pc}
     cbe:	bf00      	nop
     cc0:	20000158 	.word	0x20000158

00000cc4 <boot_read_image_header>:
static uint32_t g_last_idx = UINT32_MAX;

int
boot_read_image_header(struct boot_loader_state *state, int slot,
                       struct image_header *out_hdr, struct boot_status *bs)
{
     cc4:	b573      	push	{r0, r1, r4, r5, r6, lr}
     cc6:	4616      	mov	r6, r2
#if (BOOT_IMAGE_NUMBER == 1)
    (void)state;
#endif

    off = 0;
    if (bs) {
     cc8:	461c      	mov	r4, r3
     cca:	b333      	cbz	r3, d1a <boot_read_image_header+0x56>
	return fs->fs_off;
}

static inline uint32_t flash_sector_get_size(const struct flash_sector *fs)
{
	return fs->fs_size;
     ccc:	6a43      	ldr	r3, [r0, #36]	; 0x24
     cce:	685d      	ldr	r5, [r3, #4]
        sz = boot_img_sector_size(state, BOOT_PRIMARY_SLOT, 0);
        if (bs->op == BOOT_STATUS_OP_MOVE) {
     cd0:	7963      	ldrb	r3, [r4, #5]
     cd2:	2b01      	cmp	r3, #1
     cd4:	d115      	bne.n	d02 <boot_read_image_header+0x3e>
            if (slot == 0 && bs->idx > g_last_idx) {
     cd6:	bb01      	cbnz	r1, d1a <boot_read_image_header+0x56>
     cd8:	4b1f      	ldr	r3, [pc, #124]	; (d58 <boot_read_image_header+0x94>)
     cda:	6822      	ldr	r2, [r4, #0]
     cdc:	681b      	ldr	r3, [r3, #0]
    off = 0;
     cde:	429a      	cmp	r2, r3
     ce0:	bf98      	it	ls
     ce2:	2500      	movls	r5, #0
                }
            }
        }
    }

    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
     ce4:	2000      	movs	r0, #0
     ce6:	f003 fc87 	bl	45f8 <flash_area_id_from_multi_image_slot>
    rc = flash_area_open(area_id, &fap);
     cea:	a901      	add	r1, sp, #4
     cec:	b2c0      	uxtb	r0, r0
     cee:	f000 ffcf 	bl	1c90 <flash_area_open>
    if (rc != 0) {
     cf2:	b1f0      	cbz	r0, d32 <boot_read_image_header+0x6e>
        rc = BOOT_EFLASH;
     cf4:	2501      	movs	r5, #1
    }

    rc = 0;

done:
    flash_area_close(fap);
     cf6:	9801      	ldr	r0, [sp, #4]
     cf8:	f004 ff1b 	bl	5b32 <flash_area_close>
    return rc;
}
     cfc:	4628      	mov	r0, r5
     cfe:	b002      	add	sp, #8
     d00:	bd70      	pop	{r4, r5, r6, pc}
        } else if (bs->op == BOOT_STATUS_OP_SWAP) {
     d02:	2b02      	cmp	r3, #2
     d04:	d109      	bne.n	d1a <boot_read_image_header+0x56>
            if (bs->idx > 1 && bs->idx <= g_last_idx) {
     d06:	6823      	ldr	r3, [r4, #0]
     d08:	2b01      	cmp	r3, #1
     d0a:	d908      	bls.n	d1e <boot_read_image_header+0x5a>
     d0c:	4a12      	ldr	r2, [pc, #72]	; (d58 <boot_read_image_header+0x94>)
     d0e:	6812      	ldr	r2, [r2, #0]
     d10:	4293      	cmp	r3, r2
     d12:	d802      	bhi.n	d1a <boot_read_image_header+0x56>
                if (slot == 0) {
     d14:	fab1 f181 	clz	r1, r1
     d18:	0949      	lsrs	r1, r1, #5
    off = 0;
     d1a:	2500      	movs	r5, #0
     d1c:	e7e2      	b.n	ce4 <boot_read_image_header+0x20>
            } else if (bs->idx == 1) {
     d1e:	d1fc      	bne.n	d1a <boot_read_image_header+0x56>
                if (slot == 0) {
     d20:	2900      	cmp	r1, #0
     d22:	d0df      	beq.n	ce4 <boot_read_image_header+0x20>
                if (slot == 1 && bs->state == 2) {
     d24:	2901      	cmp	r1, #1
     d26:	d1f8      	bne.n	d1a <boot_read_image_header+0x56>
     d28:	7921      	ldrb	r1, [r4, #4]
     d2a:	3902      	subs	r1, #2
     d2c:	bf18      	it	ne
     d2e:	2101      	movne	r1, #1
     d30:	e7f3      	b.n	d1a <boot_read_image_header+0x56>
    rc = flash_area_read(fap, off, out_hdr, sizeof *out_hdr);
     d32:	4629      	mov	r1, r5
     d34:	9801      	ldr	r0, [sp, #4]
     d36:	2320      	movs	r3, #32
     d38:	4632      	mov	r2, r6
     d3a:	f004 fefb 	bl	5b34 <flash_area_read>
    if (rc != 0) {
     d3e:	4605      	mov	r5, r0
     d40:	2800      	cmp	r0, #0
     d42:	d1d7      	bne.n	cf4 <boot_read_image_header+0x30>
    if (bs != NULL && out_hdr->ih_magic != IMAGE_MAGIC) {
     d44:	2c00      	cmp	r4, #0
     d46:	d0d6      	beq.n	cf6 <boot_read_image_header+0x32>
     d48:	6835      	ldr	r5, [r6, #0]
     d4a:	4804      	ldr	r0, [pc, #16]	; (d5c <boot_read_image_header+0x98>)
     d4c:	1a2d      	subs	r5, r5, r0
     d4e:	bf18      	it	ne
     d50:	f04f 35ff 	movne.w	r5, #4294967295
     d54:	e7cf      	b.n	cf6 <boot_read_image_header+0x32>
     d56:	bf00      	nop
     d58:	20000004 	.word	0x20000004
     d5c:	96f3b83d 	.word	0x96f3b83d

00000d60 <swap_read_status_bytes>:

int
swap_read_status_bytes(const struct flash_area *fap,
        struct boot_loader_state *state, struct boot_status *bs)
{
     d60:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     d64:	4607      	mov	r7, r0
     d66:	b085      	sub	sp, #20
     d68:	460c      	mov	r4, r1
    int rc;
    int last_rc;
    int erased_sections;
    int i;

    max_entries = boot_status_entries(BOOT_CURR_IMG(state), fap);
     d6a:	4601      	mov	r1, r0
     d6c:	2000      	movs	r0, #0
{
     d6e:	4616      	mov	r6, r2
    max_entries = boot_status_entries(BOOT_CURR_IMG(state), fap);
     d70:	f003 fd18 	bl	47a4 <boot_status_entries>
    if (max_entries < 0) {
     d74:	1e05      	subs	r5, r0, #0
     d76:	db51      	blt.n	e1c <swap_read_status_bytes+0xbc>
    erased_sections = 0;
    found_idx = -1;
    /* skip erased sectors at the end */
    last_rc = 1;
    write_sz = BOOT_WRITE_SZ(state);
    off = boot_status_off(fap);
     d78:	4638      	mov	r0, r7
    write_sz = BOOT_WRITE_SZ(state);
     d7a:	6de4      	ldr	r4, [r4, #92]	; 0x5c
    off = boot_status_off(fap);
     d7c:	f003 fd1f 	bl	47be <boot_status_off>
    for (i = max_entries; i > 0; i--) {
     d80:	fa5f f984 	uxtb.w	r9, r4
     d84:	f105 38ff 	add.w	r8, r5, #4294967295
     d88:	fb09 0808 	mla	r8, r9, r8, r0
    erased_sections = 0;
     d8c:	f04f 0a00 	mov.w	sl, #0
    last_rc = 1;
     d90:	f04f 0b01 	mov.w	fp, #1
    found_idx = -1;
     d94:	f04f 34ff 	mov.w	r4, #4294967295
    for (i = max_entries; i > 0; i--) {
     d98:	b99d      	cbnz	r5, dc2 <swap_read_status_bytes+0x62>
            }
        }
        last_rc = rc;
    }

    if (erased_sections > 1) {
     d9a:	f1ba 0f01 	cmp.w	sl, #1
     d9e:	dd03      	ble.n	da8 <swap_read_status_bytes+0x48>
        /* This means there was an error writing status on the last
         * swap. Tell user and move on to validation!
         */
#if !defined(__BOOTSIM__)
        BOOT_LOG_ERR("Detected inconsistent status!");
     da0:	4820      	ldr	r0, [pc, #128]	; (e24 <swap_read_status_bytes+0xc4>)
     da2:	2145      	movs	r1, #69	; 0x45
     da4:	f004 feb8 	bl	5b18 <z_log_minimal_printk>
        assert(0);
#endif
    }

    move_entries = BOOT_MAX_IMG_SECTORS * BOOT_STATUS_MOVE_STATE_COUNT;
    if (found_idx == -1) {
     da8:	1c63      	adds	r3, r4, #1
     daa:	d006      	beq.n	dba <swap_read_status_bytes+0x5a>
        /* no swap status found; nothing to do */
    } else if (found_idx < move_entries) {
     dac:	2c7f      	cmp	r4, #127	; 0x7f
     dae:	dc2a      	bgt.n	e06 <swap_read_status_bytes+0xa6>
        bs->op = BOOT_STATUS_OP_MOVE;
        bs->idx = (found_idx  / BOOT_STATUS_MOVE_STATE_COUNT) + BOOT_STATUS_IDX_0;
     db0:	3401      	adds	r4, #1
        bs->state = (found_idx % BOOT_STATUS_MOVE_STATE_COUNT) + BOOT_STATUS_STATE_0;;
     db2:	f240 1301 	movw	r3, #257	; 0x101
        bs->idx = (found_idx  / BOOT_STATUS_MOVE_STATE_COUNT) + BOOT_STATUS_IDX_0;
     db6:	6034      	str	r4, [r6, #0]
        bs->state = (found_idx % BOOT_STATUS_MOVE_STATE_COUNT) + BOOT_STATUS_STATE_0;;
     db8:	80b3      	strh	r3, [r6, #4]
        bs->idx = ((found_idx - move_entries) / BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_IDX_0;
        bs->state = ((found_idx - move_entries) % BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_STATE_0;
    }

    return 0;
}
     dba:	4628      	mov	r0, r5
     dbc:	b005      	add	sp, #20
     dbe:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
        rc = flash_area_read(fap, off + (i - 1) * write_sz, &status, 1);
     dc2:	1e6b      	subs	r3, r5, #1
     dc4:	9300      	str	r3, [sp, #0]
     dc6:	f10d 020f 	add.w	r2, sp, #15
     dca:	2301      	movs	r3, #1
     dcc:	4641      	mov	r1, r8
     dce:	4638      	mov	r0, r7
     dd0:	f004 feb0 	bl	5b34 <flash_area_read>
        if (rc < 0) {
     dd4:	1e03      	subs	r3, r0, #0
     dd6:	9301      	str	r3, [sp, #4]
     dd8:	db22      	blt.n	e20 <swap_read_status_bytes+0xc0>
        if (bootutil_buffer_is_erased(fap, &status, 1)) {
     dda:	2201      	movs	r2, #1
     ddc:	f10d 010f 	add.w	r1, sp, #15
     de0:	4638      	mov	r0, r7
     de2:	f005 fa38 	bl	6256 <bootutil_buffer_is_erased>
     de6:	9b01      	ldr	r3, [sp, #4]
     de8:	b140      	cbz	r0, dfc <swap_read_status_bytes+0x9c>
            if (rc != last_rc) {
     dea:	455b      	cmp	r3, fp
     dec:	d001      	beq.n	df2 <swap_read_status_bytes+0x92>
                erased_sections++;
     dee:	f10a 0a01 	add.w	sl, sl, #1
            if (found_idx == -1) {
     df2:	9d00      	ldr	r5, [sp, #0]
     df4:	eba8 0809 	sub.w	r8, r8, r9
     df8:	469b      	mov	fp, r3
     dfa:	e7cd      	b.n	d98 <swap_read_status_bytes+0x38>
     dfc:	f1b4 3fff 	cmp.w	r4, #4294967295
     e00:	bf08      	it	eq
     e02:	462c      	moveq	r4, r5
     e04:	e7f5      	b.n	df2 <swap_read_status_bytes+0x92>
        bs->op = BOOT_STATUS_OP_SWAP;
     e06:	2302      	movs	r3, #2
        bs->idx = ((found_idx - move_entries) / BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_IDX_0;
     e08:	3c80      	subs	r4, #128	; 0x80
        bs->op = BOOT_STATUS_OP_SWAP;
     e0a:	7173      	strb	r3, [r6, #5]
        bs->idx = ((found_idx - move_entries) / BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_IDX_0;
     e0c:	1063      	asrs	r3, r4, #1
        bs->state = ((found_idx - move_entries) % BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_STATE_0;
     e0e:	f004 0401 	and.w	r4, r4, #1
        bs->idx = ((found_idx - move_entries) / BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_IDX_0;
     e12:	3301      	adds	r3, #1
        bs->state = ((found_idx - move_entries) % BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_STATE_0;
     e14:	3401      	adds	r4, #1
        bs->idx = ((found_idx - move_entries) / BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_IDX_0;
     e16:	6033      	str	r3, [r6, #0]
        bs->state = ((found_idx - move_entries) % BOOT_STATUS_SWAP_STATE_COUNT) + BOOT_STATUS_STATE_0;
     e18:	7134      	strb	r4, [r6, #4]
     e1a:	e7ce      	b.n	dba <swap_read_status_bytes+0x5a>
        return BOOT_EBADARGS;
     e1c:	2507      	movs	r5, #7
     e1e:	e7cc      	b.n	dba <swap_read_status_bytes+0x5a>
            return BOOT_EFLASH;
     e20:	2501      	movs	r5, #1
     e22:	e7ca      	b.n	dba <swap_read_status_bytes+0x5a>
     e24:	00006c3c 	.word	0x00006c3c

00000e28 <boot_slots_compatible>:
}

static inline size_t
boot_img_num_sectors(const struct boot_loader_state *state, size_t slot)
{
    return BOOT_IMG(state, slot).num_sectors;
     e28:	6a81      	ldr	r1, [r0, #40]	; 0x28
     e2a:	6d42      	ldr	r2, [r0, #84]	; 0x54
    size_t sector_sz_sec = 0;
    size_t i;

    num_sectors_pri = boot_img_num_sectors(state, BOOT_PRIMARY_SLOT);
    num_sectors_sec = boot_img_num_sectors(state, BOOT_SECONDARY_SLOT);
    if ((num_sectors_pri != num_sectors_sec) &&
     e2c:	4291      	cmp	r1, r2
{
     e2e:	b538      	push	{r3, r4, r5, lr}
    if ((num_sectors_pri != num_sectors_sec) &&
     e30:	d008      	beq.n	e44 <boot_slots_compatible+0x1c>
            (num_sectors_pri != (num_sectors_sec + 1))) {
     e32:	1c53      	adds	r3, r2, #1
    if ((num_sectors_pri != num_sectors_sec) &&
     e34:	428b      	cmp	r3, r1
     e36:	d005      	beq.n	e44 <boot_slots_compatible+0x1c>
        BOOT_LOG_WRN("Cannot upgrade: not a compatible amount of sectors");
     e38:	4813      	ldr	r0, [pc, #76]	; (e88 <boot_slots_compatible+0x60>)
     e3a:	2157      	movs	r1, #87	; 0x57

    for (i = 0; i < num_sectors_sec; i++) {
        sector_sz_pri = boot_img_sector_size(state, BOOT_PRIMARY_SLOT, i);
        sector_sz_sec = boot_img_sector_size(state, BOOT_SECONDARY_SLOT, i);
        if (sector_sz_pri != sector_sz_sec) {
            BOOT_LOG_WRN("Cannot upgrade: not same sector layout");
     e3c:	f004 fe6c 	bl	5b18 <z_log_minimal_printk>
            return 0;
     e40:	2000      	movs	r0, #0
        }
    }

    return 1;
#endif /* PM_S1_ADDRESS */
}
     e42:	bd38      	pop	{r3, r4, r5, pc}
    if (num_sectors_pri > BOOT_MAX_IMG_SECTORS) {
     e44:	2980      	cmp	r1, #128	; 0x80
     e46:	d91c      	bls.n	e82 <boot_slots_compatible+0x5a>
        BOOT_LOG_WRN("Cannot upgrade: more sectors than allowed");
     e48:	4810      	ldr	r0, [pc, #64]	; (e8c <boot_slots_compatible+0x64>)
     e4a:	2157      	movs	r1, #87	; 0x57
     e4c:	e7f6      	b.n	e3c <boot_slots_compatible+0x14>
     e4e:	6a44      	ldr	r4, [r0, #36]	; 0x24
     e50:	6d05      	ldr	r5, [r0, #80]	; 0x50
     e52:	eb04 04c3 	add.w	r4, r4, r3, lsl #3
     e56:	eb05 05c3 	add.w	r5, r5, r3, lsl #3
     e5a:	6864      	ldr	r4, [r4, #4]
        if (sector_sz_pri != sector_sz_sec) {
     e5c:	686d      	ldr	r5, [r5, #4]
     e5e:	42ac      	cmp	r4, r5
     e60:	d002      	beq.n	e68 <boot_slots_compatible+0x40>
            BOOT_LOG_WRN("Cannot upgrade: not same sector layout");
     e62:	480b      	ldr	r0, [pc, #44]	; (e90 <boot_slots_compatible+0x68>)
     e64:	2157      	movs	r1, #87	; 0x57
     e66:	e7e9      	b.n	e3c <boot_slots_compatible+0x14>
    for (i = 0; i < num_sectors_sec; i++) {
     e68:	3301      	adds	r3, #1
     e6a:	429a      	cmp	r2, r3
     e6c:	d1ef      	bne.n	e4e <boot_slots_compatible+0x26>
    if (num_sectors_pri > num_sectors_sec) {
     e6e:	4291      	cmp	r1, r2
     e70:	d905      	bls.n	e7e <boot_slots_compatible+0x56>
     e72:	6a43      	ldr	r3, [r0, #36]	; 0x24
     e74:	eb03 02c2 	add.w	r2, r3, r2, lsl #3
        if (sector_sz_pri != boot_img_sector_size(state, BOOT_PRIMARY_SLOT, i)) {
     e78:	6853      	ldr	r3, [r2, #4]
     e7a:	42a3      	cmp	r3, r4
     e7c:	d1f1      	bne.n	e62 <boot_slots_compatible+0x3a>
    return 1;
     e7e:	2001      	movs	r0, #1
     e80:	e7df      	b.n	e42 <boot_slots_compatible+0x1a>
    for (i = 0; i < num_sectors_sec; i++) {
     e82:	2300      	movs	r3, #0
    size_t sector_sz_pri = 0;
     e84:	461c      	mov	r4, r3
     e86:	e7f0      	b.n	e6a <boot_slots_compatible+0x42>
     e88:	00006c5f 	.word	0x00006c5f
     e8c:	00006c97 	.word	0x00006c97
     e90:	00006cc6 	.word	0x00006cc6

00000e94 <swap_status_source>:
                 (state)->copy_done,                                \
                 (state)->image_ok)

int
swap_status_source(struct boot_loader_state *state)
{
     e94:	b500      	push	{lr}
     e96:	b089      	sub	sp, #36	; 0x24
    (void)state;
#endif

    image_index = BOOT_CURR_IMG(state);

    rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_PRIMARY(image_index),
     e98:	a904      	add	r1, sp, #16
     e9a:	2002      	movs	r0, #2
     e9c:	f005 fa41 	bl	6322 <boot_read_swap_state_by_id>
            &state_primary_slot);
    assert(rc == 0);

    BOOT_LOG_SWAP_STATE("Primary image", &state_primary_slot);
     ea0:	f89d 2010 	ldrb.w	r2, [sp, #16]
     ea4:	2a01      	cmp	r2, #1
     ea6:	d041      	beq.n	f2c <swap_status_source+0x98>
     ea8:	4b25      	ldr	r3, [pc, #148]	; (f40 <swap_status_source+0xac>)
     eaa:	4926      	ldr	r1, [pc, #152]	; (f44 <swap_status_source+0xb0>)
     eac:	2a03      	cmp	r2, #3
     eae:	bf18      	it	ne
     eb0:	460b      	movne	r3, r1
     eb2:	f89d 2013 	ldrb.w	r2, [sp, #19]
     eb6:	9202      	str	r2, [sp, #8]
     eb8:	f89d 2012 	ldrb.w	r2, [sp, #18]
     ebc:	9201      	str	r2, [sp, #4]
     ebe:	f89d 2011 	ldrb.w	r2, [sp, #17]
     ec2:	4821      	ldr	r0, [pc, #132]	; (f48 <swap_status_source+0xb4>)
     ec4:	9200      	str	r2, [sp, #0]
     ec6:	2149      	movs	r1, #73	; 0x49
     ec8:	4a20      	ldr	r2, [pc, #128]	; (f4c <swap_status_source+0xb8>)
     eca:	f004 fe25 	bl	5b18 <z_log_minimal_printk>

    rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_SECONDARY(image_index),
     ece:	a906      	add	r1, sp, #24
     ed0:	2005      	movs	r0, #5
     ed2:	f005 fa26 	bl	6322 <boot_read_swap_state_by_id>
            &state_secondary_slot);
    assert(rc == 0);

    BOOT_LOG_SWAP_STATE("Secondary image", &state_secondary_slot);
     ed6:	f89d 2018 	ldrb.w	r2, [sp, #24]
     eda:	2a01      	cmp	r2, #1
     edc:	d028      	beq.n	f30 <swap_status_source+0x9c>
     ede:	4b18      	ldr	r3, [pc, #96]	; (f40 <swap_status_source+0xac>)
     ee0:	4918      	ldr	r1, [pc, #96]	; (f44 <swap_status_source+0xb0>)
     ee2:	2a03      	cmp	r2, #3
     ee4:	bf18      	it	ne
     ee6:	460b      	movne	r3, r1
     ee8:	f89d 201b 	ldrb.w	r2, [sp, #27]
     eec:	9202      	str	r2, [sp, #8]
     eee:	f89d 201a 	ldrb.w	r2, [sp, #26]
     ef2:	9201      	str	r2, [sp, #4]
     ef4:	f89d 2019 	ldrb.w	r2, [sp, #25]
     ef8:	9200      	str	r2, [sp, #0]
     efa:	4813      	ldr	r0, [pc, #76]	; (f48 <swap_status_source+0xb4>)
     efc:	4a14      	ldr	r2, [pc, #80]	; (f50 <swap_status_source+0xbc>)
     efe:	2149      	movs	r1, #73	; 0x49
     f00:	f004 fe0a 	bl	5b18 <z_log_minimal_printk>

    if (state_primary_slot.magic == BOOT_MAGIC_GOOD &&
     f04:	f89d 3010 	ldrb.w	r3, [sp, #16]
     f08:	2b01      	cmp	r3, #1
     f0a:	d113      	bne.n	f34 <swap_status_source+0xa0>
     f0c:	f89d 3012 	ldrb.w	r3, [sp, #18]
     f10:	2b03      	cmp	r3, #3
     f12:	d10f      	bne.n	f34 <swap_status_source+0xa0>
            state_primary_slot.copy_done == BOOT_FLAG_UNSET &&
     f14:	f89d 3018 	ldrb.w	r3, [sp, #24]
     f18:	2b01      	cmp	r3, #1
     f1a:	d00b      	beq.n	f34 <swap_status_source+0xa0>
            state_secondary_slot.magic != BOOT_MAGIC_GOOD) {

        source = BOOT_STATUS_SOURCE_PRIMARY_SLOT;

        BOOT_LOG_INF("Boot source: primary slot");
     f1c:	480d      	ldr	r0, [pc, #52]	; (f54 <swap_status_source+0xc0>)
     f1e:	2149      	movs	r1, #73	; 0x49
     f20:	f004 fdfa 	bl	5b18 <z_log_minimal_printk>
        return source;
     f24:	2002      	movs	r0, #2
    }

    BOOT_LOG_INF("Boot source: none");
    return BOOT_STATUS_SOURCE_NONE;
}
     f26:	b009      	add	sp, #36	; 0x24
     f28:	f85d fb04 	ldr.w	pc, [sp], #4
    BOOT_LOG_SWAP_STATE("Primary image", &state_primary_slot);
     f2c:	4b0a      	ldr	r3, [pc, #40]	; (f58 <swap_status_source+0xc4>)
     f2e:	e7c0      	b.n	eb2 <swap_status_source+0x1e>
    BOOT_LOG_SWAP_STATE("Secondary image", &state_secondary_slot);
     f30:	4b09      	ldr	r3, [pc, #36]	; (f58 <swap_status_source+0xc4>)
     f32:	e7d9      	b.n	ee8 <swap_status_source+0x54>
    BOOT_LOG_INF("Boot source: none");
     f34:	4809      	ldr	r0, [pc, #36]	; (f5c <swap_status_source+0xc8>)
     f36:	2149      	movs	r1, #73	; 0x49
     f38:	f004 fdee 	bl	5b18 <z_log_minimal_printk>
    return BOOT_STATUS_SOURCE_NONE;
     f3c:	2000      	movs	r0, #0
     f3e:	e7f2      	b.n	f26 <swap_status_source+0x92>
     f40:	00006cf7 	.word	0x00006cf7
     f44:	00006cfd 	.word	0x00006cfd
     f48:	00006d0f 	.word	0x00006d0f
     f4c:	00006d01 	.word	0x00006d01
     f50:	00006d50 	.word	0x00006d50
     f54:	00006d60 	.word	0x00006d60
     f58:	00006cf2 	.word	0x00006cf2
     f5c:	00006d7f 	.word	0x00006d7f

00000f60 <fixup_revert>:
 * upgrade (by initializing the secondary slot).
 */
void
fixup_revert(const struct boot_loader_state *state, struct boot_status *bs,
        const struct flash_area *fap_sec)
{
     f60:	b570      	push	{r4, r5, r6, lr}
#if (BOOT_IMAGE_NUMBER == 1)
    (void)state;
#endif

    /* No fixup required */
    if (bs->swap_type != BOOT_SWAP_TYPE_REVERT ||
     f62:	684b      	ldr	r3, [r1, #4]
{
     f64:	4614      	mov	r4, r2
    if (bs->swap_type != BOOT_SWAP_TYPE_REVERT ||
     f66:	4a1e      	ldr	r2, [pc, #120]	; (fe0 <fixup_revert+0x80>)
     f68:	f003 23ff 	and.w	r3, r3, #4278255360	; 0xff00ff00
     f6c:	4293      	cmp	r3, r2
{
     f6e:	b086      	sub	sp, #24
     f70:	4606      	mov	r6, r0
     f72:	460d      	mov	r5, r1
    if (bs->swap_type != BOOT_SWAP_TYPE_REVERT ||
     f74:	d12f      	bne.n	fd6 <fixup_revert+0x76>
        bs->op != BOOT_STATUS_OP_MOVE ||
     f76:	680b      	ldr	r3, [r1, #0]
     f78:	2b01      	cmp	r3, #1
     f7a:	d12c      	bne.n	fd6 <fixup_revert+0x76>
        bs->idx != BOOT_STATUS_IDX_0) {
        return;
    }

    rc = boot_read_swap_state(fap_sec, &swap_state);
     f7c:	a904      	add	r1, sp, #16
     f7e:	4620      	mov	r0, r4
     f80:	f002 fa92 	bl	34a8 <boot_read_swap_state>
    assert(rc == 0);

    BOOT_LOG_SWAP_STATE("Secondary image", &swap_state);
     f84:	f89d 2010 	ldrb.w	r2, [sp, #16]
     f88:	2a01      	cmp	r2, #1
     f8a:	d026      	beq.n	fda <fixup_revert+0x7a>
     f8c:	4b15      	ldr	r3, [pc, #84]	; (fe4 <fixup_revert+0x84>)
     f8e:	4916      	ldr	r1, [pc, #88]	; (fe8 <fixup_revert+0x88>)
     f90:	2a03      	cmp	r2, #3
     f92:	bf18      	it	ne
     f94:	460b      	movne	r3, r1
     f96:	f89d 2013 	ldrb.w	r2, [sp, #19]
     f9a:	9202      	str	r2, [sp, #8]
     f9c:	f89d 2012 	ldrb.w	r2, [sp, #18]
     fa0:	9201      	str	r2, [sp, #4]
     fa2:	f89d 2011 	ldrb.w	r2, [sp, #17]
     fa6:	9200      	str	r2, [sp, #0]
     fa8:	4810      	ldr	r0, [pc, #64]	; (fec <fixup_revert+0x8c>)
     faa:	4a11      	ldr	r2, [pc, #68]	; (ff0 <fixup_revert+0x90>)
     fac:	2149      	movs	r1, #73	; 0x49
     fae:	f004 fdb3 	bl	5b18 <z_log_minimal_printk>

    if (swap_state.magic == BOOT_MAGIC_UNSET) {
     fb2:	f89d 3010 	ldrb.w	r3, [sp, #16]
     fb6:	2b03      	cmp	r3, #3
     fb8:	d10d      	bne.n	fd6 <fixup_revert+0x76>
        rc = swap_erase_trailer_sectors(state, fap_sec);
     fba:	4621      	mov	r1, r4
     fbc:	4630      	mov	r0, r6
     fbe:	f003 fce4 	bl	498a <swap_erase_trailer_sectors>
        assert(rc == 0);

        rc = boot_write_image_ok(fap_sec);
     fc2:	4620      	mov	r0, r4
     fc4:	f005 f9a0 	bl	6308 <boot_write_image_ok>
        assert(rc == 0);

        rc = boot_write_swap_size(fap_sec, bs->swap_size);
     fc8:	68a9      	ldr	r1, [r5, #8]
     fca:	4620      	mov	r0, r4
     fcc:	f003 fc0a 	bl	47e4 <boot_write_swap_size>
        assert(rc == 0);

        rc = boot_write_magic(fap_sec);
     fd0:	4620      	mov	r0, r4
     fd2:	f002 fa49 	bl	3468 <boot_write_magic>
        assert(rc == 0);
    }
}
     fd6:	b006      	add	sp, #24
     fd8:	bd70      	pop	{r4, r5, r6, pc}
    BOOT_LOG_SWAP_STATE("Secondary image", &swap_state);
     fda:	4b06      	ldr	r3, [pc, #24]	; (ff4 <fixup_revert+0x94>)
     fdc:	e7db      	b.n	f96 <fixup_revert+0x36>
     fde:	bf00      	nop
     fe0:	04000100 	.word	0x04000100
     fe4:	00006cf7 	.word	0x00006cf7
     fe8:	00006cfd 	.word	0x00006cfd
     fec:	00006d0f 	.word	0x00006d0f
     ff0:	00006d50 	.word	0x00006d50
     ff4:	00006cf2 	.word	0x00006cf2

00000ff8 <swap_run>:

void
swap_run(struct boot_loader_state *state, struct boot_status *bs,
         uint32_t copy_size)
{
     ff8:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
     ffc:	4605      	mov	r5, r0
     ffe:	b089      	sub	sp, #36	; 0x24
    uint8_t image_index;
    const struct flash_area *fap_pri;
    const struct flash_area *fap_sec;
    int rc;

    BOOT_LOG_INF("Starting swap using move algorithm.");
    1000:	4881      	ldr	r0, [pc, #516]	; (1208 <CONFIG_FPROTECT_BLOCK_SIZE+0x208>)
{
    1002:	460c      	mov	r4, r1
    BOOT_LOG_INF("Starting swap using move algorithm.");
    1004:	2149      	movs	r1, #73	; 0x49
{
    1006:	4617      	mov	r7, r2
    BOOT_LOG_INF("Starting swap using move algorithm.");
    1008:	f004 fd86 	bl	5b18 <z_log_minimal_printk>
    100c:	6a6b      	ldr	r3, [r5, #36]	; 0x24
    100e:	2201      	movs	r2, #1
    1010:	685e      	ldr	r6, [r3, #4]

    sz = 0;
    1012:	2300      	movs	r3, #0
    g_last_idx = 0;

    sector_sz = boot_img_sector_size(state, BOOT_PRIMARY_SLOT, 0);
    while (1) {
        sz += sector_sz;
    1014:	4433      	add	r3, r6
        /* Skip to next sector because all sectors will be moved up. */
        g_last_idx++;
        if (sz >= copy_size) {
    1016:	429f      	cmp	r7, r3
    1018:	4611      	mov	r1, r2
    101a:	f102 0201 	add.w	r2, r2, #1
    101e:	d8f9      	bhi.n	1014 <CONFIG_FPROTECT_BLOCK_SIZE+0x14>
    1020:	f8df a1e8 	ldr.w	sl, [pc, #488]	; 120c <CONFIG_FPROTECT_BLOCK_SIZE+0x20c>
    }

    /*
     * When starting a new swap upgrade, check that there is enough space.
     */
    if (boot_status_is_reset(bs)) {
    1024:	4620      	mov	r0, r4
    1026:	f8ca 1000 	str.w	r1, [sl]
    102a:	f003 fc6d 	bl	4908 <boot_status_is_reset>
    102e:	b308      	cbz	r0, 1074 <CONFIG_FPROTECT_BLOCK_SIZE+0x74>
        sz = 0;
        trailer_sz = boot_trailer_sz(BOOT_WRITE_SZ(state));
    1030:	6de8      	ldr	r0, [r5, #92]	; 0x5c
    1032:	f003 fbb2 	bl	479a <boot_trailer_sz>
        first_trailer_idx = boot_img_num_sectors(state, BOOT_PRIMARY_SLOT) - 1;
    1036:	6aaf      	ldr	r7, [r5, #40]	; 0x28
        sz = 0;
    1038:	2300      	movs	r3, #0
        first_trailer_idx = boot_img_num_sectors(state, BOOT_PRIMARY_SLOT) - 1;
    103a:	3f01      	subs	r7, #1

        while (1) {
            sz += sector_sz;
    103c:	4433      	add	r3, r6
            if  (sz >= trailer_sz) {
    103e:	4283      	cmp	r3, r0
    1040:	d201      	bcs.n	1046 <CONFIG_FPROTECT_BLOCK_SIZE+0x46>
                break;
            }
            first_trailer_idx--;
    1042:	3f01      	subs	r7, #1
            sz += sector_sz;
    1044:	e7fa      	b.n	103c <CONFIG_FPROTECT_BLOCK_SIZE+0x3c>
        }

        if (g_last_idx >= first_trailer_idx) {
    1046:	f8da 3000 	ldr.w	r3, [sl]
    104a:	42bb      	cmp	r3, r7
    104c:	d312      	bcc.n	1074 <CONFIG_FPROTECT_BLOCK_SIZE+0x74>
            BOOT_LOG_WRN("Not enough free space to run swap upgrade");
    104e:	4870      	ldr	r0, [pc, #448]	; (1210 <CONFIG_FPROTECT_BLOCK_SIZE+0x210>)
    1050:	2157      	movs	r1, #87	; 0x57
    1052:	f004 fd61 	bl	5b18 <z_log_minimal_printk>
            BOOT_LOG_WRN("required %d bytes but only %d are available",
    1056:	f8da 2000 	ldr.w	r2, [sl]
    105a:	486e      	ldr	r0, [pc, #440]	; (1214 <CONFIG_FPROTECT_BLOCK_SIZE+0x214>)
    105c:	fb07 f306 	mul.w	r3, r7, r6
    1060:	fb02 6206 	mla	r2, r2, r6, r6
    1064:	2157      	movs	r1, #87	; 0x57
    1066:	f004 fd57 	bl	5b18 <z_log_minimal_printk>
                         (g_last_idx + 1) * sector_sz ,
                         first_trailer_idx * sector_sz);
            bs->swap_type = BOOT_SWAP_TYPE_NONE;
    106a:	2301      	movs	r3, #1
    106c:	71e3      	strb	r3, [r4, #7]
        idx++;
    }

    flash_area_close(fap_pri);
    flash_area_close(fap_sec);
}
    106e:	b009      	add	sp, #36	; 0x24
    1070:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    rc = flash_area_open(FLASH_AREA_IMAGE_PRIMARY(image_index), &fap_pri);
    1074:	a906      	add	r1, sp, #24
    1076:	2002      	movs	r0, #2
    1078:	f000 fe0a 	bl	1c90 <flash_area_open>
    rc = flash_area_open(FLASH_AREA_IMAGE_SECONDARY(image_index), &fap_sec);
    107c:	a907      	add	r1, sp, #28
    107e:	2005      	movs	r0, #5
    1080:	f000 fe06 	bl	1c90 <flash_area_open>
    fixup_revert(state, bs, fap_sec);
    1084:	9a07      	ldr	r2, [sp, #28]
    1086:	4621      	mov	r1, r4
    1088:	4628      	mov	r0, r5
    108a:	f7ff ff69 	bl	f60 <fixup_revert>
    if (bs->op == BOOT_STATUS_OP_MOVE) {
    108e:	7963      	ldrb	r3, [r4, #5]
    1090:	2b01      	cmp	r3, #1
    1092:	d108      	bne.n	10a6 <CONFIG_FPROTECT_BLOCK_SIZE+0xa6>
        idx = g_last_idx;
    1094:	f8da 7000 	ldr.w	r7, [sl]
    BOOT_STATUS_ASSERT(rc == 0);
    1098:	f8df b17c 	ldr.w	fp, [pc, #380]	; 1218 <CONFIG_FPROTECT_BLOCK_SIZE+0x218>
            if (idx <= (g_last_idx - bs->idx + 1)) {
    109c:	f8da 3000 	ldr.w	r3, [sl]
        while (idx > 0) {
    10a0:	b9a7      	cbnz	r7, 10cc <CONFIG_FPROTECT_BLOCK_SIZE+0xcc>
        bs->idx = BOOT_STATUS_IDX_0;
    10a2:	2301      	movs	r3, #1
    10a4:	6023      	str	r3, [r4, #0]
    bs->op = BOOT_STATUS_OP_SWAP;
    10a6:	f04f 0302 	mov.w	r3, #2
        BOOT_STATUS_ASSERT(rc == 0);
    10aa:	f8df 816c 	ldr.w	r8, [pc, #364]	; 1218 <CONFIG_FPROTECT_BLOCK_SIZE+0x218>
    bs->op = BOOT_STATUS_OP_SWAP;
    10ae:	7163      	strb	r3, [r4, #5]
    idx = 1;
    10b0:	2701      	movs	r7, #1
    while (idx <= g_last_idx) {
    10b2:	f8da 3000 	ldr.w	r3, [sl]
            boot_swap_sectors(idx, sector_sz, state, bs, fap_pri, fap_sec);
    10b6:	f8dd 9018 	ldr.w	r9, [sp, #24]
    while (idx <= g_last_idx) {
    10ba:	429f      	cmp	r7, r3
    10bc:	d94b      	bls.n	1156 <CONFIG_FPROTECT_BLOCK_SIZE+0x156>
    flash_area_close(fap_pri);
    10be:	4648      	mov	r0, r9
    10c0:	f004 fd37 	bl	5b32 <flash_area_close>
    flash_area_close(fap_sec);
    10c4:	9807      	ldr	r0, [sp, #28]
    10c6:	f004 fd34 	bl	5b32 <flash_area_close>
    10ca:	e7d0      	b.n	106e <CONFIG_FPROTECT_BLOCK_SIZE+0x6e>
            if (idx <= (g_last_idx - bs->idx + 1)) {
    10cc:	6822      	ldr	r2, [r4, #0]
    10ce:	3301      	adds	r3, #1
    10d0:	1a9b      	subs	r3, r3, r2
    10d2:	429f      	cmp	r7, r3
    10d4:	d83d      	bhi.n	1152 <CONFIG_FPROTECT_BLOCK_SIZE+0x152>

static inline uint32_t
boot_img_sector_off(const struct boot_loader_state *state, size_t slot,
                    size_t sector)
{
    return flash_sector_get_off(&BOOT_IMG(state, slot).sectors[sector]) -
    10d6:	6a6b      	ldr	r3, [r5, #36]	; 0x24
                boot_move_sector_up(idx, sector_sz, state, bs, fap_pri, fap_sec);
    10d8:	f8dd 8018 	ldr.w	r8, [sp, #24]
	return fs->fs_off;
    10dc:	6819      	ldr	r1, [r3, #0]
    10de:	f853 0037 	ldr.w	r0, [r3, r7, lsl #3]
    10e2:	eb03 03c7 	add.w	r3, r3, r7, lsl #3
    if (bs->idx == BOOT_STATUS_IDX_0) {
    10e6:	2a01      	cmp	r2, #1
    10e8:	f853 3c08 	ldr.w	r3, [r3, #-8]
    10ec:	eba3 0301 	sub.w	r3, r3, r1
    10f0:	eba0 0901 	sub.w	r9, r0, r1
    10f4:	9302      	str	r3, [sp, #8]
    10f6:	d112      	bne.n	111e <CONFIG_FPROTECT_BLOCK_SIZE+0x11e>
        if (bs->source != BOOT_STATUS_SOURCE_PRIMARY_SLOT) {
    10f8:	68e2      	ldr	r2, [r4, #12]
                boot_move_sector_up(idx, sector_sz, state, bs, fap_pri, fap_sec);
    10fa:	9b07      	ldr	r3, [sp, #28]
        if (bs->source != BOOT_STATUS_SOURCE_PRIMARY_SLOT) {
    10fc:	2a02      	cmp	r2, #2
    10fe:	d00a      	beq.n	1116 <CONFIG_FPROTECT_BLOCK_SIZE+0x116>
            rc = swap_erase_trailer_sectors(state, fap_pri);
    1100:	4641      	mov	r1, r8
    1102:	4628      	mov	r0, r5
    1104:	9303      	str	r3, [sp, #12]
    1106:	f003 fc40 	bl	498a <swap_erase_trailer_sectors>
            rc = swap_status_init(state, fap_pri, bs);
    110a:	4622      	mov	r2, r4
    110c:	4641      	mov	r1, r8
    110e:	4628      	mov	r0, r5
    1110:	f003 fc71 	bl	49f6 <swap_status_init>
    1114:	9b03      	ldr	r3, [sp, #12]
        rc = swap_erase_trailer_sectors(state, fap_sec);
    1116:	4619      	mov	r1, r3
    1118:	4628      	mov	r0, r5
    111a:	f003 fc36 	bl	498a <swap_erase_trailer_sectors>
    rc = boot_erase_region(fap_pri, new_off, sz);
    111e:	4632      	mov	r2, r6
    1120:	4649      	mov	r1, r9
    1122:	4640      	mov	r0, r8
    1124:	f003 fc2f 	bl	4986 <boot_erase_region>
    rc = boot_copy_region(state, fap_pri, fap_pri, old_off, new_off, sz);
    1128:	9b02      	ldr	r3, [sp, #8]
    112a:	4642      	mov	r2, r8
    112c:	4641      	mov	r1, r8
    112e:	e9cd 9600 	strd	r9, r6, [sp]
    1132:	4628      	mov	r0, r5
    1134:	f7ff fc44 	bl	9c0 <boot_copy_region>
    rc = boot_write_status(state, bs);
    1138:	4621      	mov	r1, r4
    113a:	4628      	mov	r0, r5
    113c:	f003 fbf1 	bl	4922 <boot_write_status>
    bs->idx++;
    1140:	6823      	ldr	r3, [r4, #0]
    1142:	3301      	adds	r3, #1
    1144:	6023      	str	r3, [r4, #0]
    BOOT_STATUS_ASSERT(rc == 0);
    1146:	b120      	cbz	r0, 1152 <CONFIG_FPROTECT_BLOCK_SIZE+0x152>
    1148:	f8db 3000 	ldr.w	r3, [fp]
    114c:	3301      	adds	r3, #1
    114e:	f8cb 3000 	str.w	r3, [fp]
            idx--;
    1152:	3f01      	subs	r7, #1
    1154:	e7a2      	b.n	109c <CONFIG_FPROTECT_BLOCK_SIZE+0x9c>
        if (idx >= bs->idx) {
    1156:	6823      	ldr	r3, [r4, #0]
    1158:	429f      	cmp	r7, r3
    115a:	d352      	bcc.n	1202 <CONFIG_FPROTECT_BLOCK_SIZE+0x202>
    115c:	6a6a      	ldr	r2, [r5, #36]	; 0x24
            boot_swap_sectors(idx, sector_sz, state, bs, fap_pri, fap_sec);
    115e:	f8dd b01c 	ldr.w	fp, [sp, #28]
    1162:	f852 1037 	ldr.w	r1, [r2, r7, lsl #3]
    1166:	9104      	str	r1, [sp, #16]
    1168:	00fb      	lsls	r3, r7, #3
    116a:	6811      	ldr	r1, [r2, #0]
    116c:	9103      	str	r1, [sp, #12]
    116e:	3b08      	subs	r3, #8
    1170:	6d29      	ldr	r1, [r5, #80]	; 0x50
    1172:	58c8      	ldr	r0, [r1, r3]
    1174:	6809      	ldr	r1, [r1, #0]
    1176:	1a41      	subs	r1, r0, r1
    1178:	9102      	str	r1, [sp, #8]
    if (bs->state == BOOT_STATUS_STATE_0) {
    117a:	7921      	ldrb	r1, [r4, #4]
    117c:	2901      	cmp	r1, #1
    117e:	d13e      	bne.n	11fe <CONFIG_FPROTECT_BLOCK_SIZE+0x1fe>
    1180:	58d1      	ldr	r1, [r2, r3]
    1182:	9b03      	ldr	r3, [sp, #12]
        rc = boot_erase_region(fap_pri, pri_off, sz);
    1184:	4632      	mov	r2, r6
    1186:	1ac9      	subs	r1, r1, r3
    1188:	4648      	mov	r0, r9
    118a:	9105      	str	r1, [sp, #20]
    118c:	f003 fbfb 	bl	4986 <boot_erase_region>
        rc = boot_copy_region(state, fap_sec, fap_pri, sec_off, pri_off, sz);
    1190:	9905      	ldr	r1, [sp, #20]
    1192:	9b02      	ldr	r3, [sp, #8]
    1194:	9100      	str	r1, [sp, #0]
    1196:	464a      	mov	r2, r9
    1198:	4659      	mov	r1, fp
    119a:	9601      	str	r6, [sp, #4]
    119c:	4628      	mov	r0, r5
    119e:	f7ff fc0f 	bl	9c0 <boot_copy_region>
        rc = boot_write_status(state, bs);
    11a2:	4621      	mov	r1, r4
    11a4:	4628      	mov	r0, r5
    11a6:	f003 fbbc 	bl	4922 <boot_write_status>
        bs->state = BOOT_STATUS_STATE_1;
    11aa:	f04f 0302 	mov.w	r3, #2
    11ae:	7123      	strb	r3, [r4, #4]
        BOOT_STATUS_ASSERT(rc == 0);
    11b0:	b120      	cbz	r0, 11bc <CONFIG_FPROTECT_BLOCK_SIZE+0x1bc>
    11b2:	f8d8 3000 	ldr.w	r3, [r8]
    11b6:	3301      	adds	r3, #1
    11b8:	f8c8 3000 	str.w	r3, [r8]
        rc = boot_erase_region(fap_sec, sec_off, sz);
    11bc:	9902      	ldr	r1, [sp, #8]
    11be:	4632      	mov	r2, r6
    11c0:	4658      	mov	r0, fp
    11c2:	f003 fbe0 	bl	4986 <boot_erase_region>
        rc = boot_copy_region(state, fap_pri, fap_sec, pri_up_off, sec_off, sz);
    11c6:	9b02      	ldr	r3, [sp, #8]
    11c8:	9300      	str	r3, [sp, #0]
    11ca:	e9dd 2303 	ldrd	r2, r3, [sp, #12]
    11ce:	4649      	mov	r1, r9
    11d0:	1a9b      	subs	r3, r3, r2
    11d2:	9601      	str	r6, [sp, #4]
    11d4:	465a      	mov	r2, fp
    11d6:	4628      	mov	r0, r5
    11d8:	f7ff fbf2 	bl	9c0 <boot_copy_region>
        rc = boot_write_status(state, bs);
    11dc:	4621      	mov	r1, r4
    11de:	4628      	mov	r0, r5
    11e0:	f003 fb9f 	bl	4922 <boot_write_status>
        bs->idx++;
    11e4:	6823      	ldr	r3, [r4, #0]
    11e6:	3301      	adds	r3, #1
    11e8:	6023      	str	r3, [r4, #0]
        bs->state = BOOT_STATUS_STATE_0;
    11ea:	f04f 0301 	mov.w	r3, #1
    11ee:	7123      	strb	r3, [r4, #4]
        BOOT_STATUS_ASSERT(rc == 0);
    11f0:	b138      	cbz	r0, 1202 <CONFIG_FPROTECT_BLOCK_SIZE+0x202>
    11f2:	f8d8 3000 	ldr.w	r3, [r8]
    11f6:	3301      	adds	r3, #1
    11f8:	f8c8 3000 	str.w	r3, [r8]
    11fc:	e001      	b.n	1202 <CONFIG_FPROTECT_BLOCK_SIZE+0x202>
    if (bs->state == BOOT_STATUS_STATE_1) {
    11fe:	2902      	cmp	r1, #2
    1200:	d0dc      	beq.n	11bc <CONFIG_FPROTECT_BLOCK_SIZE+0x1bc>
        idx++;
    1202:	3701      	adds	r7, #1
    1204:	e755      	b.n	10b2 <CONFIG_FPROTECT_BLOCK_SIZE+0xb2>
    1206:	bf00      	nop
    1208:	00006d96 	.word	0x00006d96
    120c:	20000004 	.word	0x20000004
    1210:	00006dbf 	.word	0x00006dbf
    1214:	00006dee 	.word	0x00006dee
    1218:	20000db8 	.word	0x20000db8

0000121c <mbedtls_platform_zeroize>:

void mbedtls_platform_zeroize( void *buf, size_t len )
{
    MBEDTLS_INTERNAL_VALIDATE( len == 0 || buf != NULL );

    if( len > 0 )
    121c:	460a      	mov	r2, r1
    121e:	b119      	cbz	r1, 1228 <mbedtls_platform_zeroize+0xc>
        memset_func( buf, 0, len );
    1220:	4b02      	ldr	r3, [pc, #8]	; (122c <mbedtls_platform_zeroize+0x10>)
    1222:	2100      	movs	r1, #0
    1224:	681b      	ldr	r3, [r3, #0]
    1226:	4718      	bx	r3
}
    1228:	4770      	bx	lr
    122a:	bf00      	nop
    122c:	20000008 	.word	0x20000008

00001230 <vli_mmod_fast_secp256r1>:
{
	return &curve_secp256r1;
}

void vli_mmod_fast_secp256r1(unsigned int *result, unsigned int*product)
{
    1230:	b5f0      	push	{r4, r5, r6, r7, lr}
	unsigned int tmp[NUM_ECC_WORDS];
	int carry;

	/* t */
	uECC_vli_set(result, product, NUM_ECC_WORDS);
    1232:	2208      	movs	r2, #8
{
    1234:	b089      	sub	sp, #36	; 0x24
	uECC_vli_set(result, product, NUM_ECC_WORDS);
    1236:	f003 fe25 	bl	4e84 <uECC_vli_set>

	/* s1 */
	tmp[0] = tmp[1] = tmp[2] = 0;
	tmp[3] = product[11];
    123a:	6acb      	ldr	r3, [r1, #44]	; 0x2c
    123c:	9303      	str	r3, [sp, #12]
	tmp[4] = product[12];
    123e:	6b0b      	ldr	r3, [r1, #48]	; 0x30
    1240:	9304      	str	r3, [sp, #16]
	tmp[5] = product[13];
    1242:	6b4b      	ldr	r3, [r1, #52]	; 0x34
    1244:	9305      	str	r3, [sp, #20]
	tmp[6] = product[14];
    1246:	6b8b      	ldr	r3, [r1, #56]	; 0x38
    1248:	9306      	str	r3, [sp, #24]
	tmp[7] = product[15];
    124a:	6bcb      	ldr	r3, [r1, #60]	; 0x3c
    124c:	9307      	str	r3, [sp, #28]
	carry = uECC_vli_add(tmp, tmp, tmp, NUM_ECC_WORDS);
    124e:	4613      	mov	r3, r2
    1250:	466a      	mov	r2, sp
{
    1252:	460c      	mov	r4, r1
    1254:	4606      	mov	r6, r0
	tmp[0] = tmp[1] = tmp[2] = 0;
    1256:	2700      	movs	r7, #0
	carry = uECC_vli_add(tmp, tmp, tmp, NUM_ECC_WORDS);
    1258:	4611      	mov	r1, r2
    125a:	4610      	mov	r0, r2
	tmp[0] = tmp[1] = tmp[2] = 0;
    125c:	e9cd 7701 	strd	r7, r7, [sp, #4]
    1260:	9700      	str	r7, [sp, #0]
	carry = uECC_vli_add(tmp, tmp, tmp, NUM_ECC_WORDS);
    1262:	f003 fd25 	bl	4cb0 <uECC_vli_add>
	carry += uECC_vli_add(result, result, tmp, NUM_ECC_WORDS);
    1266:	4631      	mov	r1, r6
	carry = uECC_vli_add(tmp, tmp, tmp, NUM_ECC_WORDS);
    1268:	4605      	mov	r5, r0
	carry += uECC_vli_add(result, result, tmp, NUM_ECC_WORDS);
    126a:	4630      	mov	r0, r6
    126c:	f003 fd20 	bl	4cb0 <uECC_vli_add>

	/* s2 */
	tmp[3] = product[12];
    1270:	6b21      	ldr	r1, [r4, #48]	; 0x30
    1272:	9103      	str	r1, [sp, #12]
	tmp[4] = product[13];
    1274:	6b61      	ldr	r1, [r4, #52]	; 0x34
    1276:	9104      	str	r1, [sp, #16]
	tmp[5] = product[14];
    1278:	6ba1      	ldr	r1, [r4, #56]	; 0x38
    127a:	9105      	str	r1, [sp, #20]
	tmp[6] = product[15];
    127c:	6be1      	ldr	r1, [r4, #60]	; 0x3c
	carry += uECC_vli_add(result, result, tmp, NUM_ECC_WORDS);
    127e:	4405      	add	r5, r0
	tmp[7] = 0;
    1280:	e9cd 1706 	strd	r1, r7, [sp, #24]
	carry += uECC_vli_add(tmp, tmp, tmp, NUM_ECC_WORDS);
    1284:	4610      	mov	r0, r2
    1286:	4611      	mov	r1, r2
    1288:	f003 fd12 	bl	4cb0 <uECC_vli_add>
	carry += uECC_vli_add(result, result, tmp, NUM_ECC_WORDS);
    128c:	4631      	mov	r1, r6
	carry += uECC_vli_add(tmp, tmp, tmp, NUM_ECC_WORDS);
    128e:	4405      	add	r5, r0
	carry += uECC_vli_add(result, result, tmp, NUM_ECC_WORDS);
    1290:	4630      	mov	r0, r6
    1292:	f003 fd0d 	bl	4cb0 <uECC_vli_add>
    1296:	4405      	add	r5, r0

	/* s3 */
	tmp[0] = product[8];
    1298:	6a20      	ldr	r0, [r4, #32]
    129a:	9000      	str	r0, [sp, #0]
	tmp[1] = product[9];
    129c:	6a60      	ldr	r0, [r4, #36]	; 0x24
    129e:	9001      	str	r0, [sp, #4]
	tmp[2] = product[10];
    12a0:	6aa0      	ldr	r0, [r4, #40]	; 0x28
    12a2:	9002      	str	r0, [sp, #8]
	tmp[3] = tmp[4] = tmp[5] = 0;
	tmp[6] = product[14];
    12a4:	6ba0      	ldr	r0, [r4, #56]	; 0x38
    12a6:	9006      	str	r0, [sp, #24]
	tmp[7] = product[15];
    12a8:	6be0      	ldr	r0, [r4, #60]	; 0x3c
    12aa:	9007      	str	r0, [sp, #28]
  	carry += uECC_vli_add(result, result, tmp, NUM_ECC_WORDS);
    12ac:	4630      	mov	r0, r6
	tmp[3] = tmp[4] = tmp[5] = 0;
    12ae:	e9cd 7704 	strd	r7, r7, [sp, #16]
    12b2:	9703      	str	r7, [sp, #12]
  	carry += uECC_vli_add(result, result, tmp, NUM_ECC_WORDS);
    12b4:	f003 fcfc 	bl	4cb0 <uECC_vli_add>
    12b8:	4405      	add	r5, r0

	/* s4 */
	tmp[0] = product[9];
    12ba:	6a60      	ldr	r0, [r4, #36]	; 0x24
    12bc:	9000      	str	r0, [sp, #0]
	tmp[1] = product[10];
    12be:	6aa0      	ldr	r0, [r4, #40]	; 0x28
	tmp[2] = product[11];
	tmp[3] = product[13];
	tmp[4] = product[14];
    12c0:	f8d4 c038 	ldr.w	ip, [r4, #56]	; 0x38
	tmp[1] = product[10];
    12c4:	9001      	str	r0, [sp, #4]
	tmp[2] = product[11];
    12c6:	6ae0      	ldr	r0, [r4, #44]	; 0x2c
    12c8:	9002      	str	r0, [sp, #8]
	tmp[4] = product[14];
    12ca:	f8cd c010 	str.w	ip, [sp, #16]
	tmp[3] = product[13];
    12ce:	6b60      	ldr	r0, [r4, #52]	; 0x34
	tmp[5] = product[15];
    12d0:	f8d4 c03c 	ldr.w	ip, [r4, #60]	; 0x3c
	tmp[3] = product[13];
    12d4:	9003      	str	r0, [sp, #12]
	tmp[6] = product[13];
    12d6:	e9cd c005 	strd	ip, r0, [sp, #20]
	tmp[7] = product[8];
    12da:	6a20      	ldr	r0, [r4, #32]
    12dc:	9007      	str	r0, [sp, #28]
	carry += uECC_vli_add(result, result, tmp, NUM_ECC_WORDS);
    12de:	4630      	mov	r0, r6
    12e0:	f003 fce6 	bl	4cb0 <uECC_vli_add>
    12e4:	4405      	add	r5, r0

	/* d1 */
	tmp[0] = product[11];
    12e6:	6ae0      	ldr	r0, [r4, #44]	; 0x2c
    12e8:	9000      	str	r0, [sp, #0]
	tmp[1] = product[12];
    12ea:	6b20      	ldr	r0, [r4, #48]	; 0x30
    12ec:	9001      	str	r0, [sp, #4]
	tmp[2] = product[13];
    12ee:	6b60      	ldr	r0, [r4, #52]	; 0x34
    12f0:	9002      	str	r0, [sp, #8]
	tmp[3] = tmp[4] = tmp[5] = 0;
	tmp[6] = product[8];
    12f2:	6a20      	ldr	r0, [r4, #32]
    12f4:	9006      	str	r0, [sp, #24]
	tmp[7] = product[10];
    12f6:	6aa0      	ldr	r0, [r4, #40]	; 0x28
    12f8:	9007      	str	r0, [sp, #28]
	carry -= uECC_vli_sub(result, result, tmp, NUM_ECC_WORDS);
    12fa:	4630      	mov	r0, r6
	tmp[3] = tmp[4] = tmp[5] = 0;
    12fc:	e9cd 7704 	strd	r7, r7, [sp, #16]
    1300:	9703      	str	r7, [sp, #12]
	carry -= uECC_vli_sub(result, result, tmp, NUM_ECC_WORDS);
    1302:	f003 fdf2 	bl	4eea <uECC_vli_sub>

	/* d2 */
	tmp[0] = product[12];
    1306:	6b23      	ldr	r3, [r4, #48]	; 0x30
    1308:	9300      	str	r3, [sp, #0]
	tmp[1] = product[13];
    130a:	6b63      	ldr	r3, [r4, #52]	; 0x34
    130c:	9301      	str	r3, [sp, #4]
	tmp[2] = product[14];
    130e:	6ba3      	ldr	r3, [r4, #56]	; 0x38
    1310:	9302      	str	r3, [sp, #8]
	tmp[3] = product[15];
    1312:	6be3      	ldr	r3, [r4, #60]	; 0x3c
    1314:	9303      	str	r3, [sp, #12]
	tmp[4] = tmp[5] = 0;
	tmp[6] = product[9];
    1316:	6a63      	ldr	r3, [r4, #36]	; 0x24
    1318:	9306      	str	r3, [sp, #24]
	tmp[7] = product[11];
    131a:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
    131c:	9307      	str	r3, [sp, #28]
	carry -= uECC_vli_sub(result, result, tmp, NUM_ECC_WORDS);
    131e:	1a2d      	subs	r5, r5, r0
	carry -= uECC_vli_sub(result, result, tmp, NUM_ECC_WORDS);
    1320:	2308      	movs	r3, #8
    1322:	4630      	mov	r0, r6
	tmp[4] = tmp[5] = 0;
    1324:	e9cd 7704 	strd	r7, r7, [sp, #16]
	carry -= uECC_vli_sub(result, result, tmp, NUM_ECC_WORDS);
    1328:	f003 fddf 	bl	4eea <uECC_vli_sub>

	/* d3 */
	tmp[0] = product[13];
    132c:	6b63      	ldr	r3, [r4, #52]	; 0x34
    132e:	9300      	str	r3, [sp, #0]
	tmp[1] = product[14];
    1330:	6ba3      	ldr	r3, [r4, #56]	; 0x38
    1332:	9301      	str	r3, [sp, #4]
	tmp[2] = product[15];
    1334:	6be3      	ldr	r3, [r4, #60]	; 0x3c
    1336:	9302      	str	r3, [sp, #8]
	tmp[3] = product[8];
    1338:	6a23      	ldr	r3, [r4, #32]
    133a:	9303      	str	r3, [sp, #12]
	tmp[4] = product[9];
    133c:	6a63      	ldr	r3, [r4, #36]	; 0x24
    133e:	9304      	str	r3, [sp, #16]
	tmp[5] = product[10];
    1340:	6aa3      	ldr	r3, [r4, #40]	; 0x28
	tmp[6] = 0;
    1342:	e9cd 3705 	strd	r3, r7, [sp, #20]
	tmp[7] = product[12];
    1346:	6b23      	ldr	r3, [r4, #48]	; 0x30
    1348:	9307      	str	r3, [sp, #28]
	carry -= uECC_vli_sub(result, result, tmp, NUM_ECC_WORDS);
    134a:	1a2d      	subs	r5, r5, r0
	carry -= uECC_vli_sub(result, result, tmp, NUM_ECC_WORDS);
    134c:	2308      	movs	r3, #8
    134e:	4630      	mov	r0, r6
    1350:	f003 fdcb 	bl	4eea <uECC_vli_sub>

	/* d4 */
	tmp[0] = product[14];
    1354:	6ba3      	ldr	r3, [r4, #56]	; 0x38
    1356:	9300      	str	r3, [sp, #0]
	tmp[1] = product[15];
    1358:	6be3      	ldr	r3, [r4, #60]	; 0x3c
	tmp[2] = 0;
    135a:	e9cd 3701 	strd	r3, r7, [sp, #4]
	tmp[3] = product[9];
    135e:	6a63      	ldr	r3, [r4, #36]	; 0x24
    1360:	9303      	str	r3, [sp, #12]
	tmp[4] = product[10];
    1362:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    1364:	9304      	str	r3, [sp, #16]
	tmp[5] = product[11];
    1366:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
	tmp[6] = 0;
    1368:	e9cd 3705 	strd	r3, r7, [sp, #20]
	tmp[7] = product[13];
    136c:	6b63      	ldr	r3, [r4, #52]	; 0x34
    136e:	9307      	str	r3, [sp, #28]
	carry -= uECC_vli_sub(result, result, tmp, NUM_ECC_WORDS);
    1370:	1a2d      	subs	r5, r5, r0
	carry -= uECC_vli_sub(result, result, tmp, NUM_ECC_WORDS);
    1372:	2308      	movs	r3, #8
    1374:	4630      	mov	r0, r6
    1376:	f003 fdb8 	bl	4eea <uECC_vli_sub>

	if (carry < 0) {
    137a:	1a2d      	subs	r5, r5, r0
    137c:	d410      	bmi.n	13a0 <vli_mmod_fast_secp256r1+0x170>
			carry += uECC_vli_add(result, result, curve_secp256r1.p, NUM_ECC_WORDS);
		}
		while (carry < 0);
	} else  {
		while (carry || 
		       uECC_vli_cmp_unsafe(curve_secp256r1.p, result, NUM_ECC_WORDS) != 1) {
    137e:	4c0d      	ldr	r4, [pc, #52]	; (13b4 <vli_mmod_fast_secp256r1+0x184>)
		while (carry || 
    1380:	b935      	cbnz	r5, 1390 <vli_mmod_fast_secp256r1+0x160>
		       uECC_vli_cmp_unsafe(curve_secp256r1.p, result, NUM_ECC_WORDS) != 1) {
    1382:	2208      	movs	r2, #8
    1384:	4631      	mov	r1, r6
    1386:	4620      	mov	r0, r4
    1388:	f003 fd88 	bl	4e9c <uECC_vli_cmp_unsafe>
		while (carry || 
    138c:	2801      	cmp	r0, #1
    138e:	d00f      	beq.n	13b0 <vli_mmod_fast_secp256r1+0x180>
			carry -= uECC_vli_sub(result, result, curve_secp256r1.p, NUM_ECC_WORDS);
    1390:	2308      	movs	r3, #8
    1392:	4622      	mov	r2, r4
    1394:	4631      	mov	r1, r6
    1396:	4630      	mov	r0, r6
    1398:	f003 fda7 	bl	4eea <uECC_vli_sub>
    139c:	1a2d      	subs	r5, r5, r0
    139e:	e7ef      	b.n	1380 <vli_mmod_fast_secp256r1+0x150>
			carry += uECC_vli_add(result, result, curve_secp256r1.p, NUM_ECC_WORDS);
    13a0:	4a04      	ldr	r2, [pc, #16]	; (13b4 <vli_mmod_fast_secp256r1+0x184>)
    13a2:	2308      	movs	r3, #8
    13a4:	4631      	mov	r1, r6
    13a6:	4630      	mov	r0, r6
    13a8:	f003 fc82 	bl	4cb0 <uECC_vli_add>
		while (carry < 0);
    13ac:	182d      	adds	r5, r5, r0
    13ae:	d4f8      	bmi.n	13a2 <vli_mmod_fast_secp256r1+0x172>
		}
	}
}
    13b0:	b009      	add	sp, #36	; 0x24
    13b2:	bdf0      	pop	{r4, r5, r6, r7, pc}
    13b4:	00006688 	.word	0x00006688

000013b8 <uECC_secp256r1>:
}
    13b8:	4800      	ldr	r0, [pc, #0]	; (13bc <uECC_secp256r1+0x4>)
    13ba:	4770      	bx	lr
    13bc:	00006684 	.word	0x00006684

000013c0 <compress>:
	n |= ((unsigned int)(*((*c)++)));
	return n;
}

static void compress(unsigned int *iv, const uint8_t *data)
{
    13c0:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    13c4:	b09d      	sub	sp, #116	; 0x74
	unsigned int t1, t2;
	unsigned int work_space[16];
	unsigned int n;
	unsigned int i;

	a = iv[0]; b = iv[1]; c = iv[2]; d = iv[3];
    13c6:	6803      	ldr	r3, [r0, #0]
    13c8:	9302      	str	r3, [sp, #8]
    13ca:	6843      	ldr	r3, [r0, #4]
    13cc:	9303      	str	r3, [sp, #12]
    13ce:	6883      	ldr	r3, [r0, #8]
    13d0:	9304      	str	r3, [sp, #16]
    13d2:	68c3      	ldr	r3, [r0, #12]
    13d4:	9305      	str	r3, [sp, #20]
	e = iv[4]; f = iv[5]; g = iv[6]; h = iv[7];
    13d6:	6903      	ldr	r3, [r0, #16]
    13d8:	9306      	str	r3, [sp, #24]
    13da:	6943      	ldr	r3, [r0, #20]
    13dc:	9307      	str	r3, [sp, #28]
    13de:	6983      	ldr	r3, [r0, #24]
    13e0:	9308      	str	r3, [sp, #32]
    13e2:	69c3      	ldr	r3, [r0, #28]
    13e4:	9309      	str	r3, [sp, #36]	; 0x24
    13e6:	e9dd cb07 	ldrd	ip, fp, [sp, #28]
	a = iv[0]; b = iv[1]; c = iv[2]; d = iv[3];
    13ea:	e9dd e205 	ldrd	lr, r2, [sp, #20]
    13ee:	e9dd 4602 	ldrd	r4, r6, [sp, #8]
	e = iv[4]; f = iv[5]; g = iv[6]; h = iv[7];
    13f2:	4698      	mov	r8, r3
    13f4:	f8df a190 	ldr.w	sl, [pc, #400]	; 1588 <compress+0x1c8>
	a = iv[0]; b = iv[1]; c = iv[2]; d = iv[3];
    13f8:	9b04      	ldr	r3, [sp, #16]
    13fa:	9300      	str	r3, [sp, #0]
	e = iv[4]; f = iv[5]; g = iv[6]; h = iv[7];
    13fc:	2700      	movs	r7, #0
	n = (((unsigned int)(*((*c)++))) << 24);
    13fe:	59cd      	ldr	r5, [r1, r7]

	for (i = 0; i < 16; ++i) {
		n = BigEndian(&data);
		t1 = work_space[i] = n;
    1400:	ab0c      	add	r3, sp, #48	; 0x30
    1402:	ba2d      	rev	r5, r5
    1404:	51dd      	str	r5, [r3, r7]
	return (((a) >> n) | ((a) << (32 - n)));
    1406:	f85a 3b04 	ldr.w	r3, [sl], #4
    140a:	eb05 0903 	add.w	r9, r5, r3
    140e:	ea4f 25f2 	mov.w	r5, r2, ror #11
		t1 += h + Sigma1(e) + Ch(e, f, g) + k256[i];
    1412:	ea85 15b2 	eor.w	r5, r5, r2, ror #6
    1416:	ea85 6572 	eor.w	r5, r5, r2, ror #25
    141a:	444d      	add	r5, r9
    141c:	ea2b 0302 	bic.w	r3, fp, r2
    1420:	ea02 090c 	and.w	r9, r2, ip
    1424:	ea83 0309 	eor.w	r3, r3, r9
    1428:	442b      	add	r3, r5
		t2 = Sigma0(a) + Maj(a, b, c);
    142a:	9d00      	ldr	r5, [sp, #0]
    142c:	f8dd 9000 	ldr.w	r9, [sp]
		t1 += h + Sigma1(e) + Ch(e, f, g) + k256[i];
    1430:	4443      	add	r3, r8
		t2 = Sigma0(a) + Maj(a, b, c);
    1432:	4075      	eors	r5, r6
	return (((a) >> n) | ((a) << (32 - n)));
    1434:	ea4f 3874 	mov.w	r8, r4, ror #13
		t2 = Sigma0(a) + Maj(a, b, c);
    1438:	ea88 08b4 	eor.w	r8, r8, r4, ror #2
    143c:	4025      	ands	r5, r4
    143e:	ea06 0909 	and.w	r9, r6, r9
    1442:	ea85 0509 	eor.w	r5, r5, r9
    1446:	ea88 58b4 	eor.w	r8, r8, r4, ror #22
	for (i = 0; i < 16; ++i) {
    144a:	3704      	adds	r7, #4
		t2 = Sigma0(a) + Maj(a, b, c);
    144c:	44a8      	add	r8, r5
	for (i = 0; i < 16; ++i) {
    144e:	2f40      	cmp	r7, #64	; 0x40
		h = g; g = f; f = e; e = d + t1;
    1450:	eb03 050e 	add.w	r5, r3, lr
		d = c; c = b; b = a; a = t1 + t2;
    1454:	4443      	add	r3, r8
	for (i = 0; i < 16; ++i) {
    1456:	f8dd e000 	ldr.w	lr, [sp]
    145a:	46d8      	mov	r8, fp
    145c:	f040 8085 	bne.w	156a <compress+0x1aa>
    1460:	494a      	ldr	r1, [pc, #296]	; (158c <compress+0x1cc>)
    1462:	910a      	str	r1, [sp, #40]	; 0x28
    1464:	f04f 0a10 	mov.w	sl, #16
	}

	for ( ; i < 64; ++i) {
		s0 = work_space[(i+1)&0x0f];
    1468:	4651      	mov	r1, sl
    146a:	f10a 0a01 	add.w	sl, sl, #1
    146e:	f10d 0e70 	add.w	lr, sp, #112	; 0x70
    1472:	f00a 070f 	and.w	r7, sl, #15
    1476:	eb0e 0787 	add.w	r7, lr, r7, lsl #2
		s0 = sigma0(s0);
		s1 = work_space[(i+14)&0x0f];
		s1 = sigma1(s1);

		t1 = work_space[i&0xf] += s0 + s1 + work_space[(i+9)&0xf];
    147a:	f001 090f 	and.w	r9, r1, #15
		s0 = work_space[(i+1)&0x0f];
    147e:	f857 7c40 	ldr.w	r7, [r7, #-64]
    1482:	9701      	str	r7, [sp, #4]
	return (((a) >> n) | ((a) << (32 - n)));
    1484:	ea4f 48b7 	mov.w	r8, r7, ror #18
		s0 = sigma0(s0);
    1488:	ea88 18f7 	eor.w	r8, r8, r7, ror #7
		s1 = work_space[(i+14)&0x0f];
    148c:	f101 070e 	add.w	r7, r1, #14
    1490:	f007 070f 	and.w	r7, r7, #15
    1494:	eb0e 0787 	add.w	r7, lr, r7, lsl #2
		t1 = work_space[i&0xf] += s0 + s1 + work_space[(i+9)&0xf];
    1498:	3109      	adds	r1, #9
		s1 = work_space[(i+14)&0x0f];
    149a:	f857 7c40 	ldr.w	r7, [r7, #-64]
	return (((a) >> n) | ((a) << (32 - n)));
    149e:	ea4f 4ef7 	mov.w	lr, r7, ror #19
		s1 = sigma1(s1);
    14a2:	ea8e 4e77 	eor.w	lr, lr, r7, ror #17
    14a6:	f8cd e02c 	str.w	lr, [sp, #44]	; 0x2c
		t1 = work_space[i&0xf] += s0 + s1 + work_space[(i+9)&0xf];
    14aa:	f001 010f 	and.w	r1, r1, #15
    14ae:	f10d 0e70 	add.w	lr, sp, #112	; 0x70
    14b2:	eb0e 0989 	add.w	r9, lr, r9, lsl #2
    14b6:	eb0e 0181 	add.w	r1, lr, r1, lsl #2
    14ba:	f859 ec40 	ldr.w	lr, [r9, #-64]
    14be:	f851 1c40 	ldr.w	r1, [r1, #-64]
    14c2:	4471      	add	r1, lr
		s0 = sigma0(s0);
    14c4:	f8dd e004 	ldr.w	lr, [sp, #4]
    14c8:	ea88 08de 	eor.w	r8, r8, lr, lsr #3
		s1 = sigma1(s1);
    14cc:	f8dd e02c 	ldr.w	lr, [sp, #44]	; 0x2c
		t1 = work_space[i&0xf] += s0 + s1 + work_space[(i+9)&0xf];
    14d0:	4441      	add	r1, r8
		s1 = sigma1(s1);
    14d2:	ea8e 2e97 	eor.w	lr, lr, r7, lsr #10
		t1 += h + Sigma1(e) + Ch(e, f, g) + k256[i];
    14d6:	9f0a      	ldr	r7, [sp, #40]	; 0x28
		t1 = work_space[i&0xf] += s0 + s1 + work_space[(i+9)&0xf];
    14d8:	4471      	add	r1, lr
    14da:	f849 1c40 	str.w	r1, [r9, #-64]
		t1 += h + Sigma1(e) + Ch(e, f, g) + k256[i];
    14de:	f857 eb04 	ldr.w	lr, [r7], #4
    14e2:	970a      	str	r7, [sp, #40]	; 0x28
	return (((a) >> n) | ((a) << (32 - n)));
    14e4:	ea4f 29f5 	mov.w	r9, r5, ror #11
		t1 += h + Sigma1(e) + Ch(e, f, g) + k256[i];
    14e8:	ea05 0802 	and.w	r8, r5, r2
    14ec:	ea89 19b5 	eor.w	r9, r9, r5, ror #6
    14f0:	ea2c 0705 	bic.w	r7, ip, r5
    14f4:	ea87 0708 	eor.w	r7, r7, r8
    14f8:	ea89 6975 	eor.w	r9, r9, r5, ror #25
    14fc:	444f      	add	r7, r9
    14fe:	4477      	add	r7, lr
    1500:	4439      	add	r1, r7
    1502:	4459      	add	r1, fp
	return (((a) >> n) | ((a) << (32 - n)));
    1504:	ea4f 3773 	mov.w	r7, r3, ror #13
		t2 = Sigma0(a) + Maj(a, b, c);
    1508:	ea84 0b06 	eor.w	fp, r4, r6
    150c:	ea0b 0b03 	and.w	fp, fp, r3
    1510:	ea87 07b3 	eor.w	r7, r7, r3, ror #2
    1514:	ea04 0e06 	and.w	lr, r4, r6
		h = g; g = f; f = e; e = d + t1;
    1518:	f8dd 8000 	ldr.w	r8, [sp]
    151c:	9600      	str	r6, [sp, #0]
		t2 = Sigma0(a) + Maj(a, b, c);
    151e:	ea8b 0e0e 	eor.w	lr, fp, lr
    1522:	ea87 57b3 	eor.w	r7, r7, r3, ror #22
    1526:	4477      	add	r7, lr
	for ( ; i < 64; ++i) {
    1528:	f1ba 0f40 	cmp.w	sl, #64	; 0x40
		h = g; g = f; f = e; e = d + t1;
    152c:	4488      	add	r8, r1
		d = c; c = b; b = a; a = t1 + t2;
    152e:	46e3      	mov	fp, ip
    1530:	4439      	add	r1, r7
	for ( ; i < 64; ++i) {
    1532:	d121      	bne.n	1578 <compress+0x1b8>
	}

	iv[0] += a; iv[1] += b; iv[2] += c; iv[3] += d;
    1534:	9f02      	ldr	r7, [sp, #8]
    1536:	440f      	add	r7, r1
    1538:	9903      	ldr	r1, [sp, #12]
    153a:	6007      	str	r7, [r0, #0]
    153c:	4419      	add	r1, r3
    153e:	9b04      	ldr	r3, [sp, #16]
    1540:	6041      	str	r1, [r0, #4]
    1542:	4423      	add	r3, r4
    1544:	6083      	str	r3, [r0, #8]
    1546:	9b05      	ldr	r3, [sp, #20]
    1548:	4433      	add	r3, r6
    154a:	60c3      	str	r3, [r0, #12]
	iv[4] += e; iv[5] += f; iv[6] += g; iv[7] += h;
    154c:	9b06      	ldr	r3, [sp, #24]
    154e:	4443      	add	r3, r8
    1550:	6103      	str	r3, [r0, #16]
    1552:	9b07      	ldr	r3, [sp, #28]
    1554:	442b      	add	r3, r5
    1556:	6143      	str	r3, [r0, #20]
    1558:	9b08      	ldr	r3, [sp, #32]
    155a:	4413      	add	r3, r2
    155c:	6183      	str	r3, [r0, #24]
    155e:	9b09      	ldr	r3, [sp, #36]	; 0x24
    1560:	4463      	add	r3, ip
    1562:	61c3      	str	r3, [r0, #28]
}
    1564:	b01d      	add	sp, #116	; 0x74
    1566:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    156a:	46e3      	mov	fp, ip
    156c:	9600      	str	r6, [sp, #0]
    156e:	4694      	mov	ip, r2
    1570:	4626      	mov	r6, r4
		h = g; g = f; f = e; e = d + t1;
    1572:	462a      	mov	r2, r5
		d = c; c = b; b = a; a = t1 + t2;
    1574:	461c      	mov	r4, r3
    1576:	e742      	b.n	13fe <compress+0x3e>
    1578:	4694      	mov	ip, r2
    157a:	4626      	mov	r6, r4
    157c:	462a      	mov	r2, r5
    157e:	461c      	mov	r4, r3
		h = g; g = f; f = e; e = d + t1;
    1580:	4645      	mov	r5, r8
		d = c; c = b; b = a; a = t1 + t2;
    1582:	460b      	mov	r3, r1
    1584:	e770      	b.n	1468 <compress+0xa8>
    1586:	bf00      	nop
    1588:	00006734 	.word	0x00006734
    158c:	00006774 	.word	0x00006774

00001590 <tc_sha256_init>:
{
    1590:	b510      	push	{r4, lr}
	if (s == (TCSha256State_t) 0) {
    1592:	4604      	mov	r4, r0
    1594:	b1c8      	cbz	r0, 15ca <tc_sha256_init+0x3a>
	_set((uint8_t *) s, 0x00, sizeof(*s));
    1596:	2270      	movs	r2, #112	; 0x70
    1598:	2100      	movs	r1, #0
    159a:	f004 f9e2 	bl	5962 <_set>
	s->iv[1] = 0xbb67ae85;
    159e:	4b0b      	ldr	r3, [pc, #44]	; (15cc <tc_sha256_init+0x3c>)
    15a0:	4a0b      	ldr	r2, [pc, #44]	; (15d0 <tc_sha256_init+0x40>)
	s->iv[3] = 0xa54ff53a;
    15a2:	490c      	ldr	r1, [pc, #48]	; (15d4 <tc_sha256_init+0x44>)
	s->iv[5] = 0x9b05688c;
    15a4:	480c      	ldr	r0, [pc, #48]	; (15d8 <tc_sha256_init+0x48>)
	s->iv[1] = 0xbb67ae85;
    15a6:	e9c4 2300 	strd	r2, r3, [r4]
	s->iv[3] = 0xa54ff53a;
    15aa:	4b0c      	ldr	r3, [pc, #48]	; (15dc <tc_sha256_init+0x4c>)
    15ac:	e9c4 1302 	strd	r1, r3, [r4, #8]
	s->iv[5] = 0x9b05688c;
    15b0:	4b0b      	ldr	r3, [pc, #44]	; (15e0 <tc_sha256_init+0x50>)
    15b2:	e9c4 0304 	strd	r0, r3, [r4, #16]
	s->iv[6] = 0x1f83d9ab;
    15b6:	4b0b      	ldr	r3, [pc, #44]	; (15e4 <tc_sha256_init+0x54>)
    15b8:	61a3      	str	r3, [r4, #24]
	s->iv[7] = 0x5be0cd19;
    15ba:	f103 5374 	add.w	r3, r3, #1023410176	; 0x3d000000
    15be:	f5a3 0323 	sub.w	r3, r3, #10682368	; 0xa30000
    15c2:	f6a3 4392 	subw	r3, r3, #3218	; 0xc92
    15c6:	61e3      	str	r3, [r4, #28]
	return TC_CRYPTO_SUCCESS;
    15c8:	2001      	movs	r0, #1
}
    15ca:	bd10      	pop	{r4, pc}
    15cc:	bb67ae85 	.word	0xbb67ae85
    15d0:	6a09e667 	.word	0x6a09e667
    15d4:	3c6ef372 	.word	0x3c6ef372
    15d8:	510e527f 	.word	0x510e527f
    15dc:	a54ff53a 	.word	0xa54ff53a
    15e0:	9b05688c 	.word	0x9b05688c
    15e4:	1f83d9ab 	.word	0x1f83d9ab

000015e8 <nrf_cleanup_peripheral>:
    return (uint32_t)p_reg + task;
}

NRF_STATIC_INLINE void nrf_rtc_task_trigger(NRF_RTC_Type * p_reg, nrf_rtc_task_t task)
{
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    15e8:	4a13      	ldr	r2, [pc, #76]	; (1638 <nrf_cleanup_peripheral+0x50>)
    p_reg->EVTENSET = mask;
}

NRF_STATIC_INLINE void nrf_rtc_event_disable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->EVTENCLR = mask;
    15ea:	f04f 33ff 	mov.w	r3, #4294967295
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    15ee:	2101      	movs	r1, #1
    15f0:	6051      	str	r1, [r2, #4]
    p_reg->EVTENCLR = mask;
    15f2:	f8c2 3348 	str.w	r3, [r2, #840]	; 0x348
    p_reg->INTENCLR = mask;
    15f6:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    15fa:	f502 42c0 	add.w	r2, r2, #24576	; 0x6000
    15fe:	6051      	str	r1, [r2, #4]
    p_reg->EVTENCLR = mask;
    1600:	f8c2 3348 	str.w	r3, [r2, #840]	; 0x348
    p_reg->INTENCLR = mask;
    1604:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    1608:	f502 3298 	add.w	r2, r2, #77824	; 0x13000
    160c:	6051      	str	r1, [r2, #4]
    p_reg->EVTENCLR = mask;
    160e:	f8c2 3348 	str.w	r3, [r2, #840]	; 0x348
    p_reg->INTENCLR = mask;
    1612:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
}

NRF_STATIC_INLINE void nrf_uarte_disable(NRF_UARTE_Type * p_reg)
{
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
    1616:	f5a2 3208 	sub.w	r2, r2, #139264	; 0x22000
    161a:	2100      	movs	r1, #0
    161c:	f8c2 1500 	str.w	r1, [r2, #1280]	; 0x500
    p_reg->INTENCLR = mask;
    1620:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
    }
}

NRF_STATIC_INLINE void nrf_ppi_channels_disable_all(NRF_PPI_Type * p_reg)
{
    p_reg->CHENCLR = ((uint32_t)0xFFFFFFFFuL);
    1624:	f502 32e8 	add.w	r2, r2, #118784	; 0x1d000
    1628:	f8c2 3508 	str.w	r3, [r2, #1288]	; 0x508
    p_reg->INTENSET = mask;
}

NRF_STATIC_INLINE void nrf_clock_int_disable(NRF_CLOCK_Type * p_reg, uint32_t mask)
{
    p_reg->INTENCLR = mask;
    162c:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    1630:	f8c2 3308 	str.w	r3, [r2, #776]	; 0x308
#endif
#if defined(NRF_DPPIC)
    nrf_dppi_channels_disable_all(NRF_DPPIC);
#endif
    nrf_cleanup_clock();
}
    1634:	4770      	bx	lr
    1636:	bf00      	nop
    1638:	4000b000 	.word	0x4000b000

0000163c <char_out>:

static int char_out(int c, void *ctx_p)
{
	struct out_context *ctx = ctx_p;

	ctx->count++;
    163c:	680b      	ldr	r3, [r1, #0]
    163e:	3301      	adds	r3, #1
    1640:	600b      	str	r3, [r1, #0]
	return _char_out(c);
    1642:	4b01      	ldr	r3, [pc, #4]	; (1648 <char_out+0xc>)
    1644:	681b      	ldr	r3, [r3, #0]
    1646:	4718      	bx	r3
    1648:	2000000c 	.word	0x2000000c

0000164c <__printk_hook_install>:
	_char_out = fn;
    164c:	4b01      	ldr	r3, [pc, #4]	; (1654 <__printk_hook_install+0x8>)
    164e:	6018      	str	r0, [r3, #0]
}
    1650:	4770      	bx	lr
    1652:	bf00      	nop
    1654:	2000000c 	.word	0x2000000c

00001658 <vprintk>:
}

void vprintk(const char *fmt, va_list ap)
{
    1658:	b507      	push	{r0, r1, r2, lr}
    165a:	460b      	mov	r3, r1

		if (ctx.buf_count) {
			buf_flush(&ctx);
		}
	} else {
		struct out_context ctx = { 0 };
    165c:	2100      	movs	r1, #0
{
    165e:	4602      	mov	r2, r0
		struct out_context ctx = { 0 };
    1660:	9101      	str	r1, [sp, #4]
#ifdef CONFIG_PRINTK_SYNC
		k_spinlock_key_t key = k_spin_lock(&lock);
#endif

		cbvprintf(char_out, &ctx, fmt, ap);
    1662:	4803      	ldr	r0, [pc, #12]	; (1670 <vprintk+0x18>)
    1664:	a901      	add	r1, sp, #4
    1666:	f000 f8e5 	bl	1834 <cbvprintf>

#ifdef CONFIG_PRINTK_SYNC
		k_spin_unlock(&lock, key);
#endif
	}
}
    166a:	b003      	add	sp, #12
    166c:	f85d fb04 	ldr.w	pc, [sp], #4
    1670:	0000163d 	.word	0x0000163d

00001674 <process_event>:
 * regions.
 */
static void process_event(struct onoff_manager *mgr,
			  int evt,
			  k_spinlock_key_t key)
{
    1674:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
	sys_slist_t clients;
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    1678:	f8b0 9018 	ldrh.w	r9, [r0, #24]
	__ASSERT_NO_MSG(evt != EVT_NOP);

	/* If this is a nested call record the event for processing in
	 * the top invocation.
	 */
	if (processing) {
    167c:	f019 0808 	ands.w	r8, r9, #8
{
    1680:	4604      	mov	r4, r0
    1682:	4693      	mov	fp, r2
	if (processing) {
    1684:	d00d      	beq.n	16a2 <process_event+0x2e>
		if (evt == EVT_COMPLETE) {
    1686:	2901      	cmp	r1, #1
			mgr->flags |= ONOFF_FLAG_COMPLETE;
    1688:	bf0c      	ite	eq
    168a:	f049 0910 	orreq.w	r9, r9, #16
		} else {
			__ASSERT_NO_MSG(evt == EVT_RECHECK);

			mgr->flags |= ONOFF_FLAG_RECHECK;
    168e:	f049 0920 	orrne.w	r9, r9, #32
    1692:	f8a0 9018 	strh.w	r9, [r0, #24]
	__asm__ volatile(
		"cpsie i;"
		"isb"
		: : : "memory");
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	__asm__ volatile(
    1696:	f38b 8811 	msr	BASEPRI, fp
    169a:	f3bf 8f6f 	isb	sy
		state = mgr->flags & ONOFF_STATE_MASK;
	} while (evt != EVT_NOP);

out:
	k_spin_unlock(&mgr->lock, key);
}
    169e:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    16a2:	f009 0907 	and.w	r9, r9, #7
		if (evt == EVT_RECHECK) {
    16a6:	2902      	cmp	r1, #2
    16a8:	d107      	bne.n	16ba <process_event+0x46>
			evt = process_recheck(mgr);
    16aa:	4620      	mov	r0, r4
    16ac:	f004 f988 	bl	59c0 <process_recheck>
		if (evt == EVT_NOP) {
    16b0:	2800      	cmp	r0, #0
    16b2:	d0f0      	beq.n	1696 <process_event+0x22>
		if (evt == EVT_COMPLETE) {
    16b4:	2801      	cmp	r0, #1
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    16b6:	8b23      	ldrh	r3, [r4, #24]
		if (evt == EVT_COMPLETE) {
    16b8:	d14e      	bne.n	1758 <process_event+0xe4>
			res = mgr->last_res;
    16ba:	6967      	ldr	r7, [r4, #20]
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    16bc:	8b21      	ldrh	r1, [r4, #24]
	if (res < 0) {
    16be:	2f00      	cmp	r7, #0
    16c0:	da15      	bge.n	16ee <process_event+0x7a>
		*clients = mgr->clients;
    16c2:	6825      	ldr	r5, [r4, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    16c4:	f021 0107 	bic.w	r1, r1, #7
 * @param list A pointer on the list to initialize
 */
static inline void sys_slist_init(sys_slist_t *list)
{
	list->head = NULL;
	list->tail = NULL;
    16c8:	e9c4 8800 	strd	r8, r8, [r4]
    16cc:	f041 0101 	orr.w	r1, r1, #1
	mgr->flags = (state & ONOFF_STATE_MASK)
    16d0:	8321      	strh	r1, [r4, #24]
		onoff_transition_fn transit = NULL;
    16d2:	2600      	movs	r6, #0
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
    16d4:	8b21      	ldrh	r1, [r4, #24]
    16d6:	f001 0a07 	and.w	sl, r1, #7
				   && !sys_slist_is_empty(&mgr->monitors);
    16da:	45ca      	cmp	sl, r9
    16dc:	d002      	beq.n	16e4 <process_event+0x70>
		if (do_monitors
    16de:	68a3      	ldr	r3, [r4, #8]
    16e0:	2b00      	cmp	r3, #0
    16e2:	d15a      	bne.n	179a <process_event+0x126>
		    || !sys_slist_is_empty(&clients)
    16e4:	b90d      	cbnz	r5, 16ea <process_event+0x76>
		    || (transit != NULL)) {
    16e6:	2e00      	cmp	r6, #0
    16e8:	d071      	beq.n	17ce <process_event+0x15a>
    16ea:	2300      	movs	r3, #0
    16ec:	e056      	b.n	179c <process_event+0x128>
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    16ee:	f001 0307 	and.w	r3, r1, #7
		   || (state == ONOFF_STATE_RESETTING)) {
    16f2:	1f5a      	subs	r2, r3, #5
	} else if ((state == ONOFF_STATE_TO_ON)
    16f4:	2a01      	cmp	r2, #1
    16f6:	d81e      	bhi.n	1736 <process_event+0xc2>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    16f8:	f021 0107 	bic.w	r1, r1, #7
		if (state == ONOFF_STATE_TO_ON) {
    16fc:	2b06      	cmp	r3, #6
		*clients = mgr->clients;
    16fe:	6825      	ldr	r5, [r4, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    1700:	b289      	uxth	r1, r1
    1702:	e9c4 8800 	strd	r8, r8, [r4]
		if (state == ONOFF_STATE_TO_ON) {
    1706:	d10a      	bne.n	171e <process_event+0xaa>
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
    1708:	b13d      	cbz	r5, 171a <process_event+0xa6>
    170a:	8b63      	ldrh	r3, [r4, #26]
    170c:	462a      	mov	r2, r5

#define SYS_SLIST_STATIC_INIT(ptr_to_list) {NULL, NULL}

static inline sys_snode_t *z_snode_next_peek(sys_snode_t *node)
{
	return node->next;
    170e:	6812      	ldr	r2, [r2, #0]
				mgr->refs += 1U;
    1710:	3301      	adds	r3, #1
    1712:	b29b      	uxth	r3, r3
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
    1714:	2a00      	cmp	r2, #0
    1716:	d1fa      	bne.n	170e <process_event+0x9a>
    1718:	8363      	strh	r3, [r4, #26]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    171a:	f041 0102 	orr.w	r1, r1, #2
	mgr->flags = (state & ONOFF_STATE_MASK)
    171e:	8321      	strh	r1, [r4, #24]
		if (process_recheck(mgr) != EVT_NOP) {
    1720:	4620      	mov	r0, r4
    1722:	f004 f94d 	bl	59c0 <process_recheck>
    1726:	4606      	mov	r6, r0
    1728:	2800      	cmp	r0, #0
    172a:	d0d3      	beq.n	16d4 <process_event+0x60>
			mgr->flags |= ONOFF_FLAG_RECHECK;
    172c:	8b23      	ldrh	r3, [r4, #24]
    172e:	f043 0320 	orr.w	r3, r3, #32
    1732:	8323      	strh	r3, [r4, #24]
    1734:	e7cd      	b.n	16d2 <process_event+0x5e>
	} else if (state == ONOFF_STATE_TO_OFF) {
    1736:	2b04      	cmp	r3, #4
    1738:	d10c      	bne.n	1754 <process_event+0xe0>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    173a:	f021 0107 	bic.w	r1, r1, #7
    173e:	b289      	uxth	r1, r1
	mgr->flags = (state & ONOFF_STATE_MASK)
    1740:	8321      	strh	r1, [r4, #24]
		if (process_recheck(mgr) != EVT_NOP) {
    1742:	4620      	mov	r0, r4
    1744:	f004 f93c 	bl	59c0 <process_recheck>
    1748:	4605      	mov	r5, r0
    174a:	2800      	cmp	r0, #0
    174c:	d0c1      	beq.n	16d2 <process_event+0x5e>
			mgr->flags |= ONOFF_FLAG_RECHECK;
    174e:	f041 0120 	orr.w	r1, r1, #32
    1752:	8321      	strh	r1, [r4, #24]
    1754:	2500      	movs	r5, #0
    1756:	e7bc      	b.n	16d2 <process_event+0x5e>
		} else if (evt == EVT_START) {
    1758:	2803      	cmp	r0, #3
    175a:	d109      	bne.n	1770 <process_event+0xfc>
			transit = mgr->transitions->start;
    175c:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    175e:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->start;
    1762:	6816      	ldr	r6, [r2, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    1764:	f043 0306 	orr.w	r3, r3, #6
	mgr->flags = (state & ONOFF_STATE_MASK)
    1768:	8323      	strh	r3, [r4, #24]
}
    176a:	2500      	movs	r5, #0
		res = 0;
    176c:	462f      	mov	r7, r5
    176e:	e7b1      	b.n	16d4 <process_event+0x60>
		} else if (evt == EVT_STOP) {
    1770:	2804      	cmp	r0, #4
    1772:	d106      	bne.n	1782 <process_event+0x10e>
			transit = mgr->transitions->stop;
    1774:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    1776:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->stop;
    177a:	6856      	ldr	r6, [r2, #4]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    177c:	f043 0304 	orr.w	r3, r3, #4
    1780:	e7f2      	b.n	1768 <process_event+0xf4>
		} else if (evt == EVT_RESET) {
    1782:	2805      	cmp	r0, #5
    1784:	d106      	bne.n	1794 <process_event+0x120>
			transit = mgr->transitions->reset;
    1786:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    1788:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->reset;
    178c:	6896      	ldr	r6, [r2, #8]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    178e:	f043 0305 	orr.w	r3, r3, #5
    1792:	e7e9      	b.n	1768 <process_event+0xf4>
    1794:	2500      	movs	r5, #0
		onoff_transition_fn transit = NULL;
    1796:	462e      	mov	r6, r5
    1798:	e7e8      	b.n	176c <process_event+0xf8>
				   && !sys_slist_is_empty(&mgr->monitors);
    179a:	2301      	movs	r3, #1
			uint32_t flags = mgr->flags | ONOFF_FLAG_PROCESSING;
    179c:	f041 0108 	orr.w	r1, r1, #8
			mgr->flags = flags;
    17a0:	8321      	strh	r1, [r4, #24]
    17a2:	f38b 8811 	msr	BASEPRI, fp
    17a6:	f3bf 8f6f 	isb	sy
			if (do_monitors) {
    17aa:	b9fb      	cbnz	r3, 17ec <process_event+0x178>
	while (!sys_slist_is_empty(list)) {
    17ac:	bb85      	cbnz	r5, 1810 <process_event+0x19c>
			if (transit != NULL) {
    17ae:	b116      	cbz	r6, 17b6 <process_event+0x142>
				transit(mgr, transition_complete);
    17b0:	491f      	ldr	r1, [pc, #124]	; (1830 <process_event+0x1bc>)
    17b2:	4620      	mov	r0, r4
    17b4:	47b0      	blx	r6
	__asm__ volatile(
    17b6:	f04f 0320 	mov.w	r3, #32
    17ba:	f3ef 8b11 	mrs	fp, BASEPRI
    17be:	f383 8812 	msr	BASEPRI_MAX, r3
    17c2:	f3bf 8f6f 	isb	sy
			mgr->flags &= ~ONOFF_FLAG_PROCESSING;
    17c6:	8b23      	ldrh	r3, [r4, #24]
    17c8:	f023 0308 	bic.w	r3, r3, #8
    17cc:	8323      	strh	r3, [r4, #24]
		if ((mgr->flags & ONOFF_FLAG_COMPLETE) != 0) {
    17ce:	8b23      	ldrh	r3, [r4, #24]
    17d0:	06da      	lsls	r2, r3, #27
    17d2:	d525      	bpl.n	1820 <process_event+0x1ac>
			mgr->flags &= ~ONOFF_FLAG_COMPLETE;
    17d4:	f023 0310 	bic.w	r3, r3, #16
    17d8:	8323      	strh	r3, [r4, #24]
			evt = EVT_COMPLETE;
    17da:	2101      	movs	r1, #1
		state = mgr->flags & ONOFF_STATE_MASK;
    17dc:	f8b4 9018 	ldrh.w	r9, [r4, #24]
    17e0:	f009 0907 	and.w	r9, r9, #7
	} while (evt != EVT_NOP);
    17e4:	2900      	cmp	r1, #0
    17e6:	f47f af5e 	bne.w	16a6 <process_event+0x32>
out:
    17ea:	e754      	b.n	1696 <process_event+0x22>
 *
 * @return A pointer on the first node of the list (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_head(sys_slist_t *list)
{
	return list->head;
    17ec:	68a1      	ldr	r1, [r4, #8]
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
    17ee:	2900      	cmp	r1, #0
    17f0:	d0dc      	beq.n	17ac <process_event+0x138>
	return node->next;
    17f2:	f8d1 9000 	ldr.w	r9, [r1]
		mon->callback(mgr, mon, state, res);
    17f6:	f8d1 b004 	ldr.w	fp, [r1, #4]
    17fa:	463b      	mov	r3, r7
    17fc:	4652      	mov	r2, sl
    17fe:	4620      	mov	r0, r4
    1800:	47d8      	blx	fp
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
    1802:	f1b9 0f00 	cmp.w	r9, #0
    1806:	d0d1      	beq.n	17ac <process_event+0x138>
    1808:	4649      	mov	r1, r9
    180a:	f8d9 9000 	ldr.w	r9, [r9]
    180e:	e7f2      	b.n	17f6 <process_event+0x182>
    1810:	4629      	mov	r1, r5
		notify_one(mgr, cli, state, res);
    1812:	463b      	mov	r3, r7
    1814:	4652      	mov	r2, sl
    1816:	4620      	mov	r0, r4
    1818:	682d      	ldr	r5, [r5, #0]
    181a:	f004 f8ed 	bl	59f8 <notify_one>
    181e:	e7c5      	b.n	17ac <process_event+0x138>
		} else if ((mgr->flags & ONOFF_FLAG_RECHECK) != 0) {
    1820:	f013 0120 	ands.w	r1, r3, #32
			mgr->flags &= ~ONOFF_FLAG_RECHECK;
    1824:	bf1e      	ittt	ne
    1826:	f023 0320 	bicne.w	r3, r3, #32
    182a:	8323      	strhne	r3, [r4, #24]
			evt = EVT_RECHECK;
    182c:	2102      	movne	r1, #2
    182e:	e7d5      	b.n	17dc <process_event+0x168>
    1830:	00005a25 	.word	0x00005a25

00001834 <cbvprintf>:
 * @param ap Variable parameters
 *
 * @return printed byte count if CONFIG_CBPRINTF_LIBC_SUBSTS is set
 */
int cbvprintf(cbprintf_cb out, void *ctx, const char *fmt, va_list ap)
{
    1834:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    1838:	b08f      	sub	sp, #60	; 0x3c
    183a:	461d      	mov	r5, r3
	char *prefix, *data;
	int min_width, precision, data_len;
	char padding_mode, length_mod, special;

	/* we pre-increment in the loop  afterwards */
	fmt--;
    183c:	1e53      	subs	r3, r2, #1
{
    183e:	9001      	str	r0, [sp, #4]
    1840:	468a      	mov	sl, r1
	fmt--;
    1842:	9302      	str	r3, [sp, #8]
	size_t count = 0;
    1844:	f04f 0900 	mov.w	r9, #0

start:
	while (*++fmt != '%') {
    1848:	9b02      	ldr	r3, [sp, #8]
    184a:	7858      	ldrb	r0, [r3, #1]
    184c:	2825      	cmp	r0, #37	; 0x25
    184e:	f103 0401 	add.w	r4, r3, #1
    1852:	d121      	bne.n	1898 <cbvprintf+0x64>
	min_width = -1;
	precision = -1;
	prefix = "";
	padding_mode = 0;
	length_mod = 0;
	special = 0;
    1854:	f04f 0c00 	mov.w	ip, #0

	for (fmt++ ; ; fmt++) {
    1858:	4618      	mov	r0, r3
	precision = -1;
    185a:	f04f 37ff 	mov.w	r7, #4294967295
	for (fmt++ ; ; fmt++) {
    185e:	3002      	adds	r0, #2
	length_mod = 0;
    1860:	4661      	mov	r1, ip
	padding_mode = 0;
    1862:	f8cd c00c 	str.w	ip, [sp, #12]
	min_width = -1;
    1866:	463c      	mov	r4, r7
				precision = 10 * precision + *fmt - '0';
			} else {
				if (min_width < 0) {
					min_width = 0;
				}
				min_width = 10 * min_width + *fmt - '0';
    1868:	260a      	movs	r6, #10
		switch (*fmt) {
    186a:	7802      	ldrb	r2, [r0, #0]
    186c:	9002      	str	r0, [sp, #8]
    186e:	2a39      	cmp	r2, #57	; 0x39
    1870:	f100 0001 	add.w	r0, r0, #1
    1874:	d858      	bhi.n	1928 <cbvprintf+0xf4>
    1876:	2a1f      	cmp	r2, #31
    1878:	d818      	bhi.n	18ac <cbvprintf+0x78>
    187a:	2a00      	cmp	r2, #0
    187c:	f000 81f6 	beq.w	1c6c <cbvprintf+0x438>
			precision = 0;
			break;
		}

		default:
			OUTC('%');
    1880:	9b01      	ldr	r3, [sp, #4]
    1882:	4651      	mov	r1, sl
    1884:	2025      	movs	r0, #37	; 0x25
    1886:	4798      	blx	r3
			OUTC(*fmt);
    1888:	9b02      	ldr	r3, [sp, #8]
    188a:	4651      	mov	r1, sl
    188c:	7818      	ldrb	r0, [r3, #0]
    188e:	9b01      	ldr	r3, [sp, #4]
    1890:	4798      	blx	r3
    1892:	f109 0902 	add.w	r9, r9, #2
			goto start;
    1896:	e7d7      	b.n	1848 <cbvprintf+0x14>
		if (*fmt == '\0') {
    1898:	2800      	cmp	r0, #0
    189a:	f000 81e7 	beq.w	1c6c <cbvprintf+0x438>
		OUTC(*fmt);
    189e:	9b01      	ldr	r3, [sp, #4]
    18a0:	4651      	mov	r1, sl
    18a2:	4798      	blx	r3
    18a4:	f109 0901 	add.w	r9, r9, #1
	while (*++fmt != '%') {
    18a8:	9402      	str	r4, [sp, #8]
    18aa:	e7cd      	b.n	1848 <cbvprintf+0x14>
		switch (*fmt) {
    18ac:	f1a2 0320 	sub.w	r3, r2, #32
    18b0:	2b19      	cmp	r3, #25
    18b2:	d8e5      	bhi.n	1880 <cbvprintf+0x4c>
    18b4:	f20f 0e04 	addw	lr, pc, #4
    18b8:	f85e f023 	ldr.w	pc, [lr, r3, lsl #2]
    18bc:	00001925 	.word	0x00001925
    18c0:	00001881 	.word	0x00001881
    18c4:	00001881 	.word	0x00001881
    18c8:	00001925 	.word	0x00001925
    18cc:	00001881 	.word	0x00001881
    18d0:	000019a9 	.word	0x000019a9
    18d4:	00001881 	.word	0x00001881
    18d8:	00001881 	.word	0x00001881
    18dc:	00001881 	.word	0x00001881
    18e0:	00001881 	.word	0x00001881
    18e4:	000019eb 	.word	0x000019eb
    18e8:	00001925 	.word	0x00001925
    18ec:	00001881 	.word	0x00001881
    18f0:	000019ff 	.word	0x000019ff
    18f4:	000019b7 	.word	0x000019b7
    18f8:	00001881 	.word	0x00001881
    18fc:	000019c3 	.word	0x000019c3
    1900:	000019df 	.word	0x000019df
    1904:	000019df 	.word	0x000019df
    1908:	000019df 	.word	0x000019df
    190c:	000019df 	.word	0x000019df
    1910:	000019df 	.word	0x000019df
    1914:	000019df 	.word	0x000019df
    1918:	000019df 	.word	0x000019df
    191c:	000019df 	.word	0x000019df
    1920:	000019df 	.word	0x000019df
    1924:	4694      	mov	ip, r2
    1926:	e7a0      	b.n	186a <cbvprintf+0x36>
    1928:	2a58      	cmp	r2, #88	; 0x58
    192a:	f000 811b 	beq.w	1b64 <cbvprintf+0x330>
    192e:	f1a2 0363 	sub.w	r3, r2, #99	; 0x63
    1932:	fa5f fe83 	uxtb.w	lr, r3
    1936:	f1be 0f17 	cmp.w	lr, #23
    193a:	d8a1      	bhi.n	1880 <cbvprintf+0x4c>
    193c:	2b17      	cmp	r3, #23
    193e:	d89f      	bhi.n	1880 <cbvprintf+0x4c>
    1940:	f20f 0e04 	addw	lr, pc, #4
    1944:	f85e f023 	ldr.w	pc, [lr, r3, lsl #2]
    1948:	00001bc7 	.word	0x00001bc7
    194c:	00001a25 	.word	0x00001a25
    1950:	00001881 	.word	0x00001881
    1954:	00001881 	.word	0x00001881
    1958:	00001881 	.word	0x00001881
    195c:	00001a05 	.word	0x00001a05
    1960:	00001a25 	.word	0x00001a25
    1964:	00001881 	.word	0x00001881
    1968:	00001881 	.word	0x00001881
    196c:	00001a05 	.word	0x00001a05
    1970:	00001881 	.word	0x00001881
    1974:	00001881 	.word	0x00001881
    1978:	00001881 	.word	0x00001881
    197c:	00001b0f 	.word	0x00001b0f
    1980:	00001881 	.word	0x00001881
    1984:	00001881 	.word	0x00001881
    1988:	00001ba7 	.word	0x00001ba7
    198c:	00001881 	.word	0x00001881
    1990:	00001a25 	.word	0x00001a25
    1994:	00001881 	.word	0x00001881
    1998:	00001881 	.word	0x00001881
    199c:	00001b0f 	.word	0x00001b0f
    19a0:	00001881 	.word	0x00001881
    19a4:	00001a05 	.word	0x00001a05
			OUTC('%');
    19a8:	9b01      	ldr	r3, [sp, #4]
    19aa:	4651      	mov	r1, sl
    19ac:	2025      	movs	r0, #37	; 0x25
    19ae:	4798      	blx	r3
    19b0:	f109 0901 	add.w	r9, r9, #1
			goto start;
    19b4:	e748      	b.n	1848 <cbvprintf+0x14>
			padding_mode &= (char)~PAD_ZERO;
    19b6:	9b03      	ldr	r3, [sp, #12]
    19b8:	f003 03fe 	and.w	r3, r3, #254	; 0xfe
    19bc:	9303      	str	r3, [sp, #12]
			precision = 0;
    19be:	2700      	movs	r7, #0
			continue;
    19c0:	e753      	b.n	186a <cbvprintf+0x36>
			if (min_width < 0 && precision < 0 && !padding_mode) {
    19c2:	2c00      	cmp	r4, #0
    19c4:	da0b      	bge.n	19de <cbvprintf+0x1aa>
    19c6:	2f00      	cmp	r7, #0
    19c8:	da0b      	bge.n	19e2 <cbvprintf+0x1ae>
    19ca:	9b03      	ldr	r3, [sp, #12]
    19cc:	2b00      	cmp	r3, #0
    19ce:	f000 8149 	beq.w	1c64 <cbvprintf+0x430>
				min_width = 10 * min_width + *fmt - '0';
    19d2:	ea24 74e4 	bic.w	r4, r4, r4, asr #31
    19d6:	fb06 2404 	mla	r4, r6, r4, r2
    19da:	3c30      	subs	r4, #48	; 0x30
    19dc:	e745      	b.n	186a <cbvprintf+0x36>
			if (precision >= 0) {
    19de:	2f00      	cmp	r7, #0
    19e0:	dbf7      	blt.n	19d2 <cbvprintf+0x19e>
				precision = 10 * precision + *fmt - '0';
    19e2:	fb06 2707 	mla	r7, r6, r7, r2
    19e6:	3f30      	subs	r7, #48	; 0x30
    19e8:	e73f      	b.n	186a <cbvprintf+0x36>
			if (precision >= 0) {
    19ea:	2f00      	cmp	r7, #0
    19ec:	f855 3b04 	ldr.w	r3, [r5], #4
    19f0:	db01      	blt.n	19f6 <cbvprintf+0x1c2>
				precision = va_arg(ap, int);
    19f2:	461f      	mov	r7, r3
    19f4:	e739      	b.n	186a <cbvprintf+0x36>
				if (min_width < 0) {
    19f6:	1e1c      	subs	r4, r3, #0
    19f8:	f6bf af37 	bge.w	186a <cbvprintf+0x36>
					min_width = -min_width;
    19fc:	4264      	negs	r4, r4
		switch (*fmt) {
    19fe:	2302      	movs	r3, #2
				padding_mode = PAD_ZERO;
    1a00:	9303      	str	r3, [sp, #12]
    1a02:	e732      	b.n	186a <cbvprintf+0x36>
			if (*fmt == 'h' && length_mod == 'h') {
    1a04:	2a68      	cmp	r2, #104	; 0x68
    1a06:	d103      	bne.n	1a10 <cbvprintf+0x1dc>
    1a08:	2968      	cmp	r1, #104	; 0x68
    1a0a:	d106      	bne.n	1a1a <cbvprintf+0x1e6>
				length_mod = 'H';
    1a0c:	2148      	movs	r1, #72	; 0x48
    1a0e:	e72c      	b.n	186a <cbvprintf+0x36>
			} else if (*fmt == 'l' && length_mod == 'l') {
    1a10:	2a6c      	cmp	r2, #108	; 0x6c
    1a12:	d102      	bne.n	1a1a <cbvprintf+0x1e6>
    1a14:	296c      	cmp	r1, #108	; 0x6c
    1a16:	f000 8127 	beq.w	1c68 <cbvprintf+0x434>
			} else if (length_mod == '\0') {
    1a1a:	2900      	cmp	r1, #0
    1a1c:	f47f af30 	bne.w	1880 <cbvprintf+0x4c>
    1a20:	4611      	mov	r1, r2
		switch (*fmt) {
    1a22:	e722      	b.n	186a <cbvprintf+0x36>
			if (length_mod == 'z') {
    1a24:	297a      	cmp	r1, #122	; 0x7a
    1a26:	d107      	bne.n	1a38 <cbvprintf+0x204>
			} else if (*fmt == 'u') {
    1a28:	2a75      	cmp	r2, #117	; 0x75
				precision = va_arg(ap, int);
    1a2a:	f105 0604 	add.w	r6, r5, #4
				d = va_arg(ap, unsigned int);
    1a2e:	682d      	ldr	r5, [r5, #0]
			} else if (*fmt == 'u') {
    1a30:	d162      	bne.n	1af8 <cbvprintf+0x2c4>
				d = va_arg(ap, unsigned int);
    1a32:	f04f 0800 	mov.w	r8, #0
    1a36:	e00d      	b.n	1a54 <cbvprintf+0x220>
			} else if (length_mod == 'l') {
    1a38:	296c      	cmp	r1, #108	; 0x6c
    1a3a:	d0f5      	beq.n	1a28 <cbvprintf+0x1f4>
			} else if (length_mod == 'L') {
    1a3c:	294c      	cmp	r1, #76	; 0x4c
    1a3e:	d1f3      	bne.n	1a28 <cbvprintf+0x1f4>
					unsigned long long llu =
    1a40:	1deb      	adds	r3, r5, #7
    1a42:	f023 0307 	bic.w	r3, r3, #7
    1a46:	461e      	mov	r6, r3
				if (*fmt == 'u') {
    1a48:	2a75      	cmp	r2, #117	; 0x75
					unsigned long long llu =
    1a4a:	e8f6 0102 	ldrd	r0, r1, [r6], #8
				if (*fmt == 'u') {
    1a4e:	d107      	bne.n	1a60 <cbvprintf+0x22c>
					unsigned long long llu =
    1a50:	e9d3 5800 	ldrd	r5, r8, [r3]
			} else if (special == ' ') {
    1a54:	f1bc 0f20 	cmp.w	ip, #32
    1a58:	d151      	bne.n	1afe <cbvprintf+0x2ca>
				prefix = " ";
    1a5a:	4b86      	ldr	r3, [pc, #536]	; (1c74 <cbvprintf+0x440>)
				min_width--;
    1a5c:	3c01      	subs	r4, #1
    1a5e:	e009      	b.n	1a74 <cbvprintf+0x240>
					d = (int_value_type) lld;
    1a60:	4605      	mov	r5, r0
    1a62:	4688      	mov	r8, r1
			if (*fmt != 'u' && (int_value_type)d < 0) {
    1a64:	f1b8 0f00 	cmp.w	r8, #0
    1a68:	daf4      	bge.n	1a54 <cbvprintf+0x220>
				d = -d;
    1a6a:	426d      	negs	r5, r5
				prefix = "-";
    1a6c:	4b82      	ldr	r3, [pc, #520]	; (1c78 <cbvprintf+0x444>)
				d = -d;
    1a6e:	eb68 0848 	sbc.w	r8, r8, r8, lsl #1
				min_width--;
    1a72:	3c01      	subs	r4, #1
	prefix = "";
    1a74:	9300      	str	r3, [sp, #0]
	int i = 0;
    1a76:	ab0d      	add	r3, sp, #52	; 0x34
    1a78:	9305      	str	r3, [sp, #20]
    1a7a:	f04f 0b00 	mov.w	fp, #0
		unsigned int c = num % base;
    1a7e:	4628      	mov	r0, r5
    1a80:	4641      	mov	r1, r8
    1a82:	220a      	movs	r2, #10
    1a84:	2300      	movs	r3, #0
    1a86:	f8cd b010 	str.w	fp, [sp, #16]
    1a8a:	f7fe fb27 	bl	dc <__aeabi_uldivmod>
		buftop[--i] = c + '0';
    1a8e:	9b05      	ldr	r3, [sp, #20]
    1a90:	f8cd 801c 	str.w	r8, [sp, #28]
    1a94:	3230      	adds	r2, #48	; 0x30
    1a96:	f803 2901 	strb.w	r2, [r3], #-1
		num /= base;
    1a9a:	4628      	mov	r0, r5
    1a9c:	e9cd 3505 	strd	r3, r5, [sp, #20]
    1aa0:	4641      	mov	r1, r8
    1aa2:	2300      	movs	r3, #0
    1aa4:	220a      	movs	r2, #10
    1aa6:	f7fe fb19 	bl	dc <__aeabi_uldivmod>
	} while (num);
    1aaa:	9b06      	ldr	r3, [sp, #24]
    1aac:	2b0a      	cmp	r3, #10
    1aae:	9b07      	ldr	r3, [sp, #28]
    1ab0:	f173 0300 	sbcs.w	r3, r3, #0
		buftop[--i] = c + '0';
    1ab4:	f10b 3bff 	add.w	fp, fp, #4294967295
		num /= base;
    1ab8:	4605      	mov	r5, r0
    1aba:	4688      	mov	r8, r1
	} while (num);
    1abc:	d2df      	bcs.n	1a7e <cbvprintf+0x24a>
	return -i;
    1abe:	9b04      	ldr	r3, [sp, #16]
			data = buf + sizeof(buf) - data_len;
    1ac0:	9a04      	ldr	r2, [sp, #16]
	return -i;
    1ac2:	f1c3 0b01 	rsb	fp, r3, #1
			data = buf + sizeof(buf) - data_len;
    1ac6:	ab0e      	add	r3, sp, #56	; 0x38
    1ac8:	189d      	adds	r5, r3, r2
		}

		if (precision < 0 && (padding_mode & PAD_ZERO)) {
    1aca:	2f00      	cmp	r7, #0
			data = buf + sizeof(buf) - data_len;
    1acc:	f1a5 0504 	sub.w	r5, r5, #4
		if (precision < 0 && (padding_mode & PAD_ZERO)) {
    1ad0:	da04      	bge.n	1adc <cbvprintf+0x2a8>
    1ad2:	9b03      	ldr	r3, [sp, #12]
    1ad4:	f013 0f01 	tst.w	r3, #1
    1ad8:	bf18      	it	ne
    1ada:	4627      	movne	r7, r4
		precision -= data_len;
		if (precision > 0) {
			min_width -= precision;
		}

		if (!(padding_mode & PAD_TAIL)) {
    1adc:	9b03      	ldr	r3, [sp, #12]
		precision -= data_len;
    1ade:	eba7 080b 	sub.w	r8, r7, fp
		if (precision > 0) {
    1ae2:	f1b8 0f00 	cmp.w	r8, #0
		min_width -= data_len;
    1ae6:	bfd4      	ite	le
    1ae8:	eba4 040b 	suble.w	r4, r4, fp
			min_width -= precision;
    1aec:	1be4      	subgt	r4, r4, r7
		if (!(padding_mode & PAD_TAIL)) {
    1aee:	079b      	lsls	r3, r3, #30
    1af0:	f100 8081 	bmi.w	1bf6 <cbvprintf+0x3c2>
    1af4:	4627      	mov	r7, r4
    1af6:	e077      	b.n	1be8 <cbvprintf+0x3b4>
				d = va_arg(ap, int);
    1af8:	ea4f 78e5 	mov.w	r8, r5, asr #31
    1afc:	e7b2      	b.n	1a64 <cbvprintf+0x230>
			} else if (special == '+') {
    1afe:	f1bc 0f2b 	cmp.w	ip, #43	; 0x2b
				prefix = "+";
    1b02:	bf0a      	itet	eq
    1b04:	4b5d      	ldreq	r3, [pc, #372]	; (1c7c <cbvprintf+0x448>)
	prefix = "";
    1b06:	4b5e      	ldrne	r3, [pc, #376]	; (1c80 <cbvprintf+0x44c>)
				min_width--;
    1b08:	f104 34ff 	addeq.w	r4, r4, #4294967295
    1b0c:	e7b2      	b.n	1a74 <cbvprintf+0x240>
			if (*fmt == 'p') {
    1b0e:	2a70      	cmp	r2, #112	; 0x70
    1b10:	d128      	bne.n	1b64 <cbvprintf+0x330>
				x = (uintptr_t)va_arg(ap, void *);
    1b12:	462e      	mov	r6, r5
    1b14:	2300      	movs	r3, #0
    1b16:	f856 1b04 	ldr.w	r1, [r6], #4
				if (x == (uint_value_type)0) {
    1b1a:	2900      	cmp	r1, #0
    1b1c:	d05c      	beq.n	1bd8 <cbvprintf+0x3a4>
				prefix = (*fmt & 0x20) ? "0x" : "0X";
    1b1e:	4859      	ldr	r0, [pc, #356]	; (1c84 <cbvprintf+0x450>)
    1b20:	9000      	str	r0, [sp, #0]
				min_width -= 2;
    1b22:	3c02      	subs	r4, #2
			data_len = convert_value(x, 16, ALPHA(*fmt),
    1b24:	f002 0260 	and.w	r2, r2, #96	; 0x60
    1b28:	f1a2 0839 	sub.w	r8, r2, #57	; 0x39
	int i = 0;
    1b2c:	f10d 0e34 	add.w	lr, sp, #52	; 0x34
    1b30:	2500      	movs	r5, #0
		unsigned int c = num % base;
    1b32:	f001 020f 	and.w	r2, r1, #15
		if (c >= 10) {
    1b36:	2a09      	cmp	r2, #9
			c += alpha;
    1b38:	bf88      	it	hi
    1b3a:	4442      	addhi	r2, r8
		buftop[--i] = c + '0';
    1b3c:	3230      	adds	r2, #48	; 0x30
    1b3e:	f80e 2901 	strb.w	r2, [lr], #-1
	} while (num);
    1b42:	2910      	cmp	r1, #16
		num /= base;
    1b44:	ea4f 1211 	mov.w	r2, r1, lsr #4
    1b48:	ea42 7203 	orr.w	r2, r2, r3, lsl #28
    1b4c:	ea4f 1013 	mov.w	r0, r3, lsr #4
	} while (num);
    1b50:	f173 0300 	sbcs.w	r3, r3, #0
		buftop[--i] = c + '0';
    1b54:	f105 3cff 	add.w	ip, r5, #4294967295
	} while (num);
    1b58:	d221      	bcs.n	1b9e <cbvprintf+0x36a>
			data = buf + sizeof(buf) - data_len;
    1b5a:	ab0e      	add	r3, sp, #56	; 0x38
	return -i;
    1b5c:	f1c5 0b01 	rsb	fp, r5, #1
			data = buf + sizeof(buf) - data_len;
    1b60:	441d      	add	r5, r3
    1b62:	e7b2      	b.n	1aca <cbvprintf+0x296>
			} else if (length_mod == 'l') {
    1b64:	296c      	cmp	r1, #108	; 0x6c
    1b66:	d104      	bne.n	1b72 <cbvprintf+0x33e>
				x = va_arg(ap, unsigned int);
    1b68:	462e      	mov	r6, r5
    1b6a:	2300      	movs	r3, #0
    1b6c:	f856 1b04 	ldr.w	r1, [r6], #4
    1b70:	e008      	b.n	1b84 <cbvprintf+0x350>
			} else if (length_mod == 'L') {
    1b72:	294c      	cmp	r1, #76	; 0x4c
    1b74:	d1f8      	bne.n	1b68 <cbvprintf+0x334>
				unsigned long long llx =
    1b76:	3507      	adds	r5, #7
    1b78:	f025 0507 	bic.w	r5, r5, #7
    1b7c:	462e      	mov	r6, r5
    1b7e:	686b      	ldr	r3, [r5, #4]
    1b80:	f856 1b08 	ldr.w	r1, [r6], #8
			if (special == '#') {
    1b84:	f1bc 0f23 	cmp.w	ip, #35	; 0x23
    1b88:	d106      	bne.n	1b98 <cbvprintf+0x364>
				prefix = (*fmt & 0x20) ? "0x" : "0X";
    1b8a:	4d3f      	ldr	r5, [pc, #252]	; (1c88 <cbvprintf+0x454>)
    1b8c:	483d      	ldr	r0, [pc, #244]	; (1c84 <cbvprintf+0x450>)
    1b8e:	f012 0f20 	tst.w	r2, #32
    1b92:	bf08      	it	eq
    1b94:	4628      	moveq	r0, r5
    1b96:	e7c3      	b.n	1b20 <cbvprintf+0x2ec>
	prefix = "";
    1b98:	4839      	ldr	r0, [pc, #228]	; (1c80 <cbvprintf+0x44c>)
    1b9a:	9000      	str	r0, [sp, #0]
    1b9c:	e7c2      	b.n	1b24 <cbvprintf+0x2f0>
		buftop[--i] = c + '0';
    1b9e:	4665      	mov	r5, ip
		num /= base;
    1ba0:	4611      	mov	r1, r2
    1ba2:	4603      	mov	r3, r0
    1ba4:	e7c5      	b.n	1b32 <cbvprintf+0x2fe>
			data = va_arg(ap, char *);
    1ba6:	462e      	mov	r6, r5
    1ba8:	f856 5b04 	ldr.w	r5, [r6], #4
			data_len = strlen(data);
    1bac:	4628      	mov	r0, r5
    1bae:	f004 f859 	bl	5c64 <strlen>
			if (precision >= 0 && data_len > precision) {
    1bb2:	2f00      	cmp	r7, #0
			data_len = strlen(data);
    1bb4:	4683      	mov	fp, r0
			if (precision >= 0 && data_len > precision) {
    1bb6:	db02      	blt.n	1bbe <cbvprintf+0x38a>
    1bb8:	42b8      	cmp	r0, r7
    1bba:	bfa8      	it	ge
    1bbc:	46bb      	movge	fp, r7
    1bbe:	4b30      	ldr	r3, [pc, #192]	; (1c80 <cbvprintf+0x44c>)
    1bc0:	9300      	str	r3, [sp, #0]
    1bc2:	2700      	movs	r7, #0
    1bc4:	e78a      	b.n	1adc <cbvprintf+0x2a8>
			int c = va_arg(ap, int);
    1bc6:	462e      	mov	r6, r5
			data_len = 1;
    1bc8:	f04f 0b01 	mov.w	fp, #1
			buf[0] = c;
    1bcc:	f856 3b04 	ldr.w	r3, [r6], #4
    1bd0:	f88d 3020 	strb.w	r3, [sp, #32]
			data = buf;
    1bd4:	ad08      	add	r5, sp, #32
    1bd6:	e7f2      	b.n	1bbe <cbvprintf+0x38a>
					data = "(nil)";
    1bd8:	4d2c      	ldr	r5, [pc, #176]	; (1c8c <cbvprintf+0x458>)
					data_len = 5;
    1bda:	f04f 0b05 	mov.w	fp, #5
    1bde:	e7ee      	b.n	1bbe <cbvprintf+0x38a>
			while (--min_width >= 0) {
				OUTC(' ');
    1be0:	9b01      	ldr	r3, [sp, #4]
    1be2:	4651      	mov	r1, sl
    1be4:	2020      	movs	r0, #32
    1be6:	4798      	blx	r3
			while (--min_width >= 0) {
    1be8:	3f01      	subs	r7, #1
    1bea:	d5f9      	bpl.n	1be0 <cbvprintf+0x3ac>
    1bec:	ea24 73e4 	bic.w	r3, r4, r4, asr #31
    1bf0:	3c01      	subs	r4, #1
    1bf2:	4499      	add	r9, r3
    1bf4:	1ae4      	subs	r4, r4, r3
    1bf6:	9b00      	ldr	r3, [sp, #0]
    1bf8:	eba9 0903 	sub.w	r9, r9, r3
    1bfc:	e004      	b.n	1c08 <cbvprintf+0x3d4>
    1bfe:	9300      	str	r3, [sp, #0]
			}
		}
		while (*prefix) {
			OUTC(*prefix++);
    1c00:	4651      	mov	r1, sl
    1c02:	9b01      	ldr	r3, [sp, #4]
    1c04:	4798      	blx	r3
    1c06:	9b00      	ldr	r3, [sp, #0]
    1c08:	eb09 0703 	add.w	r7, r9, r3
		while (*prefix) {
    1c0c:	f813 0b01 	ldrb.w	r0, [r3], #1
    1c10:	2800      	cmp	r0, #0
    1c12:	d1f4      	bne.n	1bfe <cbvprintf+0x3ca>
		precision -= data_len;
    1c14:	46c1      	mov	r9, r8
		}
		while (--precision >= 0) {
    1c16:	f1b9 0901 	subs.w	r9, r9, #1
    1c1a:	d513      	bpl.n	1c44 <cbvprintf+0x410>
    1c1c:	ea28 78e8 	bic.w	r8, r8, r8, asr #31
    1c20:	46d9      	mov	r9, fp
			OUTC('0');
		}
		while (--data_len >= 0) {
    1c22:	f1b9 0901 	subs.w	r9, r9, #1
    1c26:	d512      	bpl.n	1c4e <cbvprintf+0x41a>
    1c28:	f1bb 0f00 	cmp.w	fp, #0
    1c2c:	bfa8      	it	ge
    1c2e:	44d8      	addge	r8, fp
    1c30:	4625      	mov	r5, r4
			OUTC(*data++);
		}
		while (--min_width >= 0) {
    1c32:	3d01      	subs	r5, #1
    1c34:	d511      	bpl.n	1c5a <cbvprintf+0x426>
    1c36:	2c00      	cmp	r4, #0
    1c38:	bfa8      	it	ge
    1c3a:	44a0      	addge	r8, r4
    1c3c:	eb08 0907 	add.w	r9, r8, r7
    1c40:	4635      	mov	r5, r6
    1c42:	e601      	b.n	1848 <cbvprintf+0x14>
			OUTC('0');
    1c44:	9b01      	ldr	r3, [sp, #4]
    1c46:	4651      	mov	r1, sl
    1c48:	2030      	movs	r0, #48	; 0x30
    1c4a:	4798      	blx	r3
    1c4c:	e7e3      	b.n	1c16 <cbvprintf+0x3e2>
			OUTC(*data++);
    1c4e:	f815 0b01 	ldrb.w	r0, [r5], #1
    1c52:	9b01      	ldr	r3, [sp, #4]
    1c54:	4651      	mov	r1, sl
    1c56:	4798      	blx	r3
    1c58:	e7e3      	b.n	1c22 <cbvprintf+0x3ee>
			OUTC(' ');
    1c5a:	9b01      	ldr	r3, [sp, #4]
    1c5c:	4651      	mov	r1, sl
    1c5e:	2020      	movs	r0, #32
    1c60:	4798      	blx	r3
    1c62:	e7e6      	b.n	1c32 <cbvprintf+0x3fe>
				padding_mode = PAD_ZERO;
    1c64:	2301      	movs	r3, #1
    1c66:	e6cb      	b.n	1a00 <cbvprintf+0x1cc>
				length_mod = 'L';
    1c68:	214c      	movs	r1, #76	; 0x4c
    1c6a:	e5fe      	b.n	186a <cbvprintf+0x36>
		}

		goto start;
	}
}
    1c6c:	4648      	mov	r0, r9
    1c6e:	b00f      	add	sp, #60	; 0x3c
    1c70:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    1c74:	000071f6 	.word	0x000071f6
    1c78:	00006e7a 	.word	0x00006e7a
    1c7c:	00006e7c 	.word	0x00006e7c
    1c80:	00007594 	.word	0x00007594
    1c84:	00006e81 	.word	0x00006e81
    1c88:	00006e7e 	.word	0x00006e7e
    1c8c:	00006e84 	.word	0x00006e84

00001c90 <flash_area_open>:

int flash_area_open(uint8_t id, const struct flash_area **fap)
{
	const struct flash_area *area;

	if (flash_map == NULL) {
    1c90:	4b0c      	ldr	r3, [pc, #48]	; (1cc4 <flash_area_open+0x34>)
    1c92:	681b      	ldr	r3, [r3, #0]
{
    1c94:	b570      	push	{r4, r5, r6, lr}
	if (flash_map == NULL) {
    1c96:	b173      	cbz	r3, 1cb6 <flash_area_open+0x26>
extern const struct flash_area *flash_map;
extern const int flash_map_entries;

static inline struct flash_area const *get_flash_area_from_id(int idx)
{
	for (int i = 0; i < flash_map_entries; i++) {
    1c98:	4a0b      	ldr	r2, [pc, #44]	; (1cc8 <flash_area_open+0x38>)
    1c9a:	6815      	ldr	r5, [r2, #0]
    1c9c:	2200      	movs	r2, #0
    1c9e:	42aa      	cmp	r2, r5
    1ca0:	db02      	blt.n	1ca8 <flash_area_open+0x18>
		return -EACCES;
	}

	area = get_flash_area_from_id(id);
	if (area == NULL) {
		return -ENOENT;
    1ca2:	f06f 0001 	mvn.w	r0, #1
	}

	*fap = area;
	return 0;
}
    1ca6:	bd70      	pop	{r4, r5, r6, pc}
		if (flash_map[i].fa_id == idx) {
    1ca8:	461c      	mov	r4, r3
    1caa:	f813 6b10 	ldrb.w	r6, [r3], #16
    1cae:	4286      	cmp	r6, r0
    1cb0:	d004      	beq.n	1cbc <flash_area_open+0x2c>
	for (int i = 0; i < flash_map_entries; i++) {
    1cb2:	3201      	adds	r2, #1
    1cb4:	e7f3      	b.n	1c9e <flash_area_open+0xe>
		return -EACCES;
    1cb6:	f06f 000c 	mvn.w	r0, #12
    1cba:	e7f4      	b.n	1ca6 <flash_area_open+0x16>
	*fap = area;
    1cbc:	600c      	str	r4, [r1, #0]
	return 0;
    1cbe:	2000      	movs	r0, #0
    1cc0:	e7f1      	b.n	1ca6 <flash_area_open+0x16>
    1cc2:	bf00      	nop
    1cc4:	20000010 	.word	0x20000010
    1cc8:	00006898 	.word	0x00006898

00001ccc <flash_area_get_sectors>:

	return true;
}

int flash_area_get_sectors(int idx, uint32_t *cnt, struct flash_sector *ret)
{
    1ccc:	b570      	push	{r4, r5, r6, lr}
    1cce:	b088      	sub	sp, #32
    1cd0:	4605      	mov	r5, r0
    1cd2:	460c      	mov	r4, r1
	int rc = flash_area_open(idx, &fa);
    1cd4:	b2c0      	uxtb	r0, r0
    1cd6:	4669      	mov	r1, sp
{
    1cd8:	4616      	mov	r6, r2
	int rc = flash_area_open(idx, &fa);
    1cda:	f7ff ffd9 	bl	1c90 <flash_area_open>
	if (rc < 0 || fa == NULL) {
    1cde:	2800      	cmp	r0, #0
    1ce0:	db1f      	blt.n	1d22 <flash_area_get_sectors+0x56>
    1ce2:	9b00      	ldr	r3, [sp, #0]
    1ce4:	b1eb      	cbz	r3, 1d22 <flash_area_get_sectors+0x56>
	cb_data->area_off = fa->fa_off;
    1ce6:	685a      	ldr	r2, [r3, #4]
    1ce8:	9202      	str	r2, [sp, #8]
	cb_data->area_len = fa->fa_size;
    1cea:	689a      	ldr	r2, [r3, #8]
	cb_data->ret_len = *cnt;
    1cec:	6821      	ldr	r1, [r4, #0]
	flash_dev = device_get_binding(fa->fa_dev_name);
    1cee:	68d8      	ldr	r0, [r3, #12]
	cb_data->area_idx = idx;
    1cf0:	9501      	str	r5, [sp, #4]
	cb_data->ret = ret;
    1cf2:	e9cd 2603 	strd	r2, r6, [sp, #12]
	cb_data->ret_idx = 0U;
    1cf6:	2200      	movs	r2, #0
	cb_data->status = 0;
    1cf8:	e9cd 1206 	strd	r1, r2, [sp, #24]
	cb_data->ret_idx = 0U;
    1cfc:	9205      	str	r2, [sp, #20]
    1cfe:	f002 faf5 	bl	42ec <z_impl_device_get_binding>
    1d02:	4605      	mov	r5, r0
	flash_area_close(fa);
    1d04:	9800      	ldr	r0, [sp, #0]
    1d06:	f003 ff14 	bl	5b32 <flash_area_close>
	if (flash_dev == NULL) {
    1d0a:	b16d      	cbz	r5, 1d28 <flash_area_get_sectors+0x5c>
	flash_page_foreach(flash_dev, cb, cb_data);
    1d0c:	4628      	mov	r0, r5
    1d0e:	4908      	ldr	r1, [pc, #32]	; (1d30 <flash_area_get_sectors+0x64>)
    1d10:	aa01      	add	r2, sp, #4
    1d12:	f004 f8d3 	bl	5ebc <flash_page_foreach>
	if (cb_data->status == 0) {
    1d16:	9807      	ldr	r0, [sp, #28]
    1d18:	b908      	cbnz	r0, 1d1e <flash_area_get_sectors+0x52>
		*cnt = cb_data->ret_idx;
    1d1a:	9b05      	ldr	r3, [sp, #20]
    1d1c:	6023      	str	r3, [r4, #0]
	struct layout_data data;

	return flash_area_layout(idx, cnt, ret, get_sectors_cb, &data);
}
    1d1e:	b008      	add	sp, #32
    1d20:	bd70      	pop	{r4, r5, r6, pc}
		return -EINVAL;
    1d22:	f06f 0015 	mvn.w	r0, #21
    1d26:	e7fa      	b.n	1d1e <flash_area_get_sectors+0x52>
		return -ENODEV;
    1d28:	f06f 0012 	mvn.w	r0, #18
	return flash_area_layout(idx, cnt, ret, get_sectors_cb, &data);
    1d2c:	e7f7      	b.n	1d1e <flash_area_get_sectors+0x52>
    1d2e:	bf00      	nop
    1d30:	00005bf7 	.word	0x00005bf7

00001d34 <z_arm_cpu_idle_init>:
 * void z_arm_cpu_idle_init(void);
 */

SECTION_FUNC(TEXT, z_arm_cpu_idle_init)
#if defined(CONFIG_CPU_CORTEX_M)
	ldr	r1, =_SCB_SCR
    1d34:	4901      	ldr	r1, [pc, #4]	; (1d3c <z_arm_cpu_idle_init+0x8>)
	movs.n	r2, #_SCR_INIT_BITS
    1d36:	2210      	movs	r2, #16
	str	r2, [r1]
    1d38:	600a      	str	r2, [r1, #0]
#endif
	bx	lr
    1d3a:	4770      	bx	lr
	ldr	r1, =_SCB_SCR
    1d3c:	e000ed10 	.word	0xe000ed10

00001d40 <arch_cpu_atomic_idle>:

	/*
	 * Lock PRIMASK while sleeping: wfe will still get interrupted by
	 * incoming interrupts but the CPU will not service them right away.
	 */
	cpsid	i
    1d40:	b672      	cpsid	i
	cpsie	i
_irq_disabled:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* r1: zero, for setting BASEPRI (needs a register) */
	eors.n	r1, r1
    1d42:	4049      	eors	r1, r1

	/* unlock BASEPRI so wfe gets interrupted by incoming interrupts */
	msr	BASEPRI, r1
    1d44:	f381 8811 	msr	BASEPRI, r1

	wfe
    1d48:	bf20      	wfe

	msr	BASEPRI, r0
    1d4a:	f380 8811 	msr	BASEPRI, r0
	cpsie	i
    1d4e:	b662      	cpsie	i
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
	bx	lr
    1d50:	4770      	bx	lr
    1d52:	bf00      	nop

00001d54 <z_arm_fatal_error>:
	LOG_ERR("Faulting instruction address (r15/pc): 0x%08x",
		esf->basic.pc);
}

void z_arm_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
{
    1d54:	b537      	push	{r0, r1, r2, r4, r5, lr}
    1d56:	4605      	mov	r5, r0

	if (esf != NULL) {
    1d58:	460c      	mov	r4, r1
    1d5a:	b1c9      	cbz	r1, 1d90 <z_arm_fatal_error+0x3c>
	LOG_ERR("r0/a1:  0x%08x  r1/a2:  0x%08x  r2/a3:  0x%08x",
    1d5c:	688b      	ldr	r3, [r1, #8]
    1d5e:	9300      	str	r3, [sp, #0]
    1d60:	e9d1 2300 	ldrd	r2, r3, [r1]
    1d64:	480e      	ldr	r0, [pc, #56]	; (1da0 <z_arm_fatal_error+0x4c>)
    1d66:	2145      	movs	r1, #69	; 0x45
    1d68:	f003 fed6 	bl	5b18 <z_log_minimal_printk>
	LOG_ERR("r3/a4:  0x%08x r12/ip:  0x%08x r14/lr:  0x%08x",
    1d6c:	6963      	ldr	r3, [r4, #20]
    1d6e:	9300      	str	r3, [sp, #0]
    1d70:	e9d4 2303 	ldrd	r2, r3, [r4, #12]
    1d74:	480b      	ldr	r0, [pc, #44]	; (1da4 <z_arm_fatal_error+0x50>)
    1d76:	2145      	movs	r1, #69	; 0x45
    1d78:	f003 fece 	bl	5b18 <z_log_minimal_printk>
	LOG_ERR(" xpsr:  0x%08x", esf->basic.xpsr);
    1d7c:	69e2      	ldr	r2, [r4, #28]
    1d7e:	480a      	ldr	r0, [pc, #40]	; (1da8 <z_arm_fatal_error+0x54>)
    1d80:	2145      	movs	r1, #69	; 0x45
    1d82:	f003 fec9 	bl	5b18 <z_log_minimal_printk>
	LOG_ERR("Faulting instruction address (r15/pc): 0x%08x",
    1d86:	69a2      	ldr	r2, [r4, #24]
    1d88:	4808      	ldr	r0, [pc, #32]	; (1dac <z_arm_fatal_error+0x58>)
    1d8a:	2145      	movs	r1, #69	; 0x45
    1d8c:	f003 fec4 	bl	5b18 <z_log_minimal_printk>
		esf_dump(esf);
	}
	z_fatal_error(reason, esf);
    1d90:	4621      	mov	r1, r4
    1d92:	4628      	mov	r0, r5
}
    1d94:	b003      	add	sp, #12
    1d96:	e8bd 4030 	ldmia.w	sp!, {r4, r5, lr}
	z_fatal_error(reason, esf);
    1d9a:	f002 bad1 	b.w	4340 <z_fatal_error>
    1d9e:	bf00      	nop
    1da0:	00006e8a 	.word	0x00006e8a
    1da4:	00006ebe 	.word	0x00006ebe
    1da8:	00006ef2 	.word	0x00006ef2
    1dac:	00006f06 	.word	0x00006f06

00001db0 <arch_irq_enable>:
#define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
#define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)

void arch_irq_enable(unsigned int irq)
{
	NVIC_EnableIRQ((IRQn_Type)irq);
    1db0:	b243      	sxtb	r3, r0
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
    1db2:	2b00      	cmp	r3, #0
    1db4:	db08      	blt.n	1dc8 <arch_irq_enable+0x18>
  {
    __COMPILER_BARRIER();
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    1db6:	2201      	movs	r2, #1
    1db8:	f000 001f 	and.w	r0, r0, #31
    1dbc:	fa02 f000 	lsl.w	r0, r2, r0
    1dc0:	095b      	lsrs	r3, r3, #5
    1dc2:	4a02      	ldr	r2, [pc, #8]	; (1dcc <arch_irq_enable+0x1c>)
    1dc4:	f842 0023 	str.w	r0, [r2, r3, lsl #2]
}
    1dc8:	4770      	bx	lr
    1dca:	bf00      	nop
    1dcc:	e000e100 	.word	0xe000e100

00001dd0 <arch_irq_is_enabled>:
	NVIC_DisableIRQ((IRQn_Type)irq);
}

int arch_irq_is_enabled(unsigned int irq)
{
	return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq));
    1dd0:	4b05      	ldr	r3, [pc, #20]	; (1de8 <arch_irq_is_enabled+0x18>)
    1dd2:	0942      	lsrs	r2, r0, #5
    1dd4:	f000 001f 	and.w	r0, r0, #31
    1dd8:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
    1ddc:	2301      	movs	r3, #1
    1dde:	fa03 f000 	lsl.w	r0, r3, r0
}
    1de2:	4010      	ands	r0, r2
    1de4:	4770      	bx	lr
    1de6:	bf00      	nop
    1de8:	e000e100 	.word	0xe000e100

00001dec <z_arm_irq_priority_set>:
	 */
	__ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1),
		 "invalid priority %d for %d irq! values must be less than %lu\n",
		 prio - _IRQ_PRIO_OFFSET, irq,
		 BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
	NVIC_SetPriority((IRQn_Type)irq, prio);
    1dec:	b243      	sxtb	r3, r0
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
  if ((int32_t)(IRQn) >= 0)
    1dee:	2b00      	cmp	r3, #0
  {
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1df0:	bfa8      	it	ge
    1df2:	f103 4360 	addge.w	r3, r3, #3758096384	; 0xe0000000
		prio += _IRQ_PRIO_OFFSET;
    1df6:	f101 0101 	add.w	r1, r1, #1
  }
  else
  {
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1dfa:	bfb8      	it	lt
    1dfc:	4b06      	ldrlt	r3, [pc, #24]	; (1e18 <z_arm_irq_priority_set+0x2c>)
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1dfe:	ea4f 1141 	mov.w	r1, r1, lsl #5
    1e02:	bfac      	ite	ge
    1e04:	f503 4361 	addge.w	r3, r3, #57600	; 0xe100
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1e08:	f000 000f 	andlt.w	r0, r0, #15
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1e0c:	b2c9      	uxtb	r1, r1
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1e0e:	bfb4      	ite	lt
    1e10:	5419      	strblt	r1, [r3, r0]
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    1e12:	f883 1300 	strbge.w	r1, [r3, #768]	; 0x300
}
    1e16:	4770      	bx	lr
    1e18:	e000ed14 	.word	0xe000ed14

00001e1c <z_SysNmiOnReset>:
_ASM_FILE_PROLOGUE

GTEXT(z_SysNmiOnReset)

SECTION_FUNC(TEXT, z_SysNmiOnReset)
    wfi
    1e1c:	bf30      	wfi
    b z_SysNmiOnReset
    1e1e:	f7ff bffd 	b.w	1e1c <z_SysNmiOnReset>
    1e22:	bf00      	nop

00001e24 <z_arm_prep_c>:

#define VECTOR_ADDRESS ((uintptr_t)_vector_start)

static inline void relocate_vector_table(void)
{
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    1e24:	4a0b      	ldr	r2, [pc, #44]	; (1e54 <z_arm_prep_c+0x30>)
 *
 * This routine prepares for the execution of and runs C code.
 *
 */
void z_arm_prep_c(void)
{
    1e26:	b508      	push	{r3, lr}
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    1e28:	4b0b      	ldr	r3, [pc, #44]	; (1e58 <z_arm_prep_c+0x34>)
    1e2a:	f022 027f 	bic.w	r2, r2, #127	; 0x7f
    1e2e:	609a      	str	r2, [r3, #8]
  __ASM volatile ("dsb 0xF":::"memory");
    1e30:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    1e34:	f3bf 8f6f 	isb	sy
	SCB->CPACR &= (~(CPACR_CP10_Msk | CPACR_CP11_Msk));
    1e38:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
    1e3c:	f422 0270 	bic.w	r2, r2, #15728640	; 0xf00000
    1e40:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
	relocate_vector_table();
#if defined(CONFIG_CPU_HAS_FPU)
	z_arm_floating_point_init();
#endif
	z_bss_zero();
    1e44:	f002 fad2 	bl	43ec <z_bss_zero>
	z_data_copy();
    1e48:	f002 fb16 	bl	4478 <z_data_copy>
#if ((defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)) && defined(CONFIG_INIT_STACKS))
	z_arm_init_stacks();
#endif
	z_arm_interrupt_init();
    1e4c:	f000 fa4e 	bl	22ec <z_arm_interrupt_init>
	z_cstart();
    1e50:	f002 fad8 	bl	4404 <z_cstart>
    1e54:	00000000 	.word	0x00000000
    1e58:	e000ed00 	.word	0xe000ed00

00001e5c <z_arm_svc>:
  bne _stack_frame_endif
_stack_frame_msp:
  mrs r0, MSP
_stack_frame_endif:
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    tst lr, #_EXC_RETURN_SPSEL_Msk /* did we come from thread mode ? */
    1e5c:	f01e 0f04 	tst.w	lr, #4
    ite eq  /* if zero (equal), came from handler mode */
    1e60:	bf0c      	ite	eq
        mrseq r0, MSP   /* handler mode, stack frame is on MSP */
    1e62:	f3ef 8008 	mrseq	r0, MSP
        mrsne r0, PSP   /* thread mode, stack frame is on PSP */
    1e66:	f3ef 8009 	mrsne	r0, PSP
#endif


    /* Figure out what SVC call number was invoked */

    ldr r1, [r0, #24]   /* grab address of PC from stack frame */
    1e6a:	6981      	ldr	r1, [r0, #24]
     */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    subs r1, r1, #2
    ldrb r1, [r1]
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    ldrb r1, [r1, #-2]
    1e6c:	f811 1c02 	ldrb.w	r1, [r1, #-2]
#endif
    bne _oops

#endif /* CONFIG_USERSPACE */

    cmp r1, #2
    1e70:	2902      	cmp	r1, #2
    beq _oops
    1e72:	d0ff      	beq.n	1e74 <_oops>

00001e74 <_oops>:
    /* exception return is done in z_arm_int_exit() */
    b z_arm_int_exit
#endif

_oops:
    push {r0, lr}
    1e74:	b501      	push	{r0, lr}
    bl z_do_kernel_oops
    1e76:	f003 fedc 	bl	5c32 <z_do_kernel_oops>
    /* return from SVC exception is done here */
    pop {r0, pc}
    1e7a:	bd01      	pop	{r0, pc}

00001e7c <z_check_thread_stack_fail>:
			fault_addr, psp)) {
		/* Thread stack corruption */
		return thread->stack_info.start;
	}
#else
	if (IS_MPU_GUARD_VIOLATION((uint32_t)z_main_stack,
    1e7c:	f110 0f16 	cmn.w	r0, #22
    1e80:	4b07      	ldr	r3, [pc, #28]	; (1ea0 <z_check_thread_stack_fail+0x24>)
    1e82:	d008      	beq.n	1e96 <z_check_thread_stack_fail+0x1a>
    1e84:	4298      	cmp	r0, r3
    1e86:	d308      	bcc.n	1e9a <z_check_thread_stack_fail+0x1e>
    1e88:	3320      	adds	r3, #32
    1e8a:	4283      	cmp	r3, r0
    1e8c:	d905      	bls.n	1e9a <z_check_thread_stack_fail+0x1e>
    1e8e:	428b      	cmp	r3, r1
    1e90:	d903      	bls.n	1e9a <z_check_thread_stack_fail+0x1e>
			guard_len,
			fault_addr, psp)) {
		/* Thread stack corruption */
		return (uint32_t)Z_THREAD_STACK_BUFFER(z_main_stack);
    1e92:	4804      	ldr	r0, [pc, #16]	; (1ea4 <z_check_thread_stack_fail+0x28>)
    1e94:	4770      	bx	lr
	if (IS_MPU_GUARD_VIOLATION((uint32_t)z_main_stack,
    1e96:	3320      	adds	r3, #32
    1e98:	e7f9      	b.n	1e8e <z_check_thread_stack_fail+0x12>
	}
#endif
#endif /* CONFIG_USERSPACE */

	return 0;
    1e9a:	2000      	movs	r0, #0
}
    1e9c:	4770      	bx	lr
    1e9e:	bf00      	nop
    1ea0:	20001420 	.word	0x20001420
    1ea4:	20001440 	.word	0x20001440

00001ea8 <z_arm_switch_to_main_no_multithreading>:

#if !defined(CONFIG_MULTITHREADING) && defined(CONFIG_CPU_CORTEX_M)

FUNC_NORETURN void z_arm_switch_to_main_no_multithreading(
	k_thread_entry_t main_entry, void *p1, void *p2, void *p3)
{
    1ea8:	4604      	mov	r4, r0
	 */
	register void *p1_inreg __asm__("r0") = p1;
	register void *p2_inreg __asm__("r1") = p2;
	register void *p3_inreg __asm__("r2") = p3;

	__asm__ volatile (
    1eaa:	2520      	movs	r5, #32
	register void *p1_inreg __asm__("r0") = p1;
    1eac:	4608      	mov	r0, r1
	register void *p2_inreg __asm__("r1") = p2;
    1eae:	4611      	mov	r1, r2
	register void *p3_inreg __asm__("r2") = p3;
    1eb0:	461a      	mov	r2, r3
	__asm__ volatile (
    1eb2:	4b08      	ldr	r3, [pc, #32]	; (1ed4 <loop+0x4>)
    1eb4:	f383 8809 	msr	PSP, r3
    1eb8:	b663      	cpsie	if
    1eba:	f04f 0300 	mov.w	r3, #0
    1ebe:	f383 8811 	msr	BASEPRI, r3
    1ec2:	f3bf 8f6f 	isb	sy
    1ec6:	47a0      	blx	r4
    1ec8:	f385 8811 	msr	BASEPRI, r5
    1ecc:	f3bf 8f6f 	isb	sy

00001ed0 <loop>:
    1ed0:	e7fe      	b.n	1ed0 <loop>
	, [_psplim]"r" (psplim)
#endif
	:
	);

	CODE_UNREACHABLE; /* LCOV_EXCL_LINE */
    1ed2:	bf00      	nop
    1ed4:	20003c40 	.word	0x20003c40

00001ed8 <_isr_wrapper>:
 *
 */
SECTION_FUNC(TEXT, _isr_wrapper)

#if defined(CONFIG_CPU_CORTEX_M)
	push {r0,lr}		/* r0, lr are now the first items on the stack */
    1ed8:	b501      	push	{r0, lr}
#endif

#endif /* CONFIG_PM */

#if defined(CONFIG_CPU_CORTEX_M)
	mrs r0, IPSR	/* get exception number */
    1eda:	f3ef 8005 	mrs	r0, IPSR
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r1, =16
	subs r0, r1	/* get IRQ number */
	lsls r0, #3	/* table is 8-byte wide */
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	sub r0, r0, #16	/* get IRQ number */
    1ede:	f1a0 0010 	sub.w	r0, r0, #16
	lsl r0, r0, #3	/* table is 8-byte wide */
    1ee2:	ea4f 00c0 	mov.w	r0, r0, lsl #3
	lsl r1, r1, #3
	cmp r0, r1
	bge spurious_continue
#endif /* !CONFIG_CPU_CORTEX_M */

	ldr r1, =_sw_isr_table
    1ee6:	4904      	ldr	r1, [pc, #16]	; (1ef8 <_isr_wrapper+0x20>)
	add r1, r1, r0	/* table entry: ISRs must have their MSB set to stay
    1ee8:	4401      	add	r1, r0
			 * in thumb mode */

	ldm r1!,{r0,r3}	/* arg in r0, ISR in r3 */
    1eea:	c909      	ldmia	r1!, {r0, r3}
	blx r3		/* call ISR */
    1eec:	4798      	blx	r3

#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	pop {r0, r3}
	mov lr, r3
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	pop {r0, lr}
    1eee:	e8bd 4001 	ldmia.w	sp!, {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

	/* Use 'bx' instead of 'b' because 'bx' can jump further, and use
	 * 'bx' instead of 'blx' because exception return is done in
	 * z_arm_int_exit() */
	ldr r1, =z_arm_int_exit
    1ef2:	4902      	ldr	r1, [pc, #8]	; (1efc <_isr_wrapper+0x24>)
	bx r1
    1ef4:	4708      	bx	r1
    1ef6:	0000      	.short	0x0000
	ldr r1, =_sw_isr_table
    1ef8:	000064d4 	.word	0x000064d4
	ldr r1, =z_arm_int_exit
    1efc:	00001f01 	.word	0x00001f01

00001f00 <z_arm_exc_exit>:
#else
	pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_STACK_SENTINEL */

	bx lr
    1f00:	4770      	bx	lr
    1f02:	bf00      	nop

00001f04 <mem_manage_fault>:
 *
 * @return error code to identify the fatal error reason
 */
static uint32_t mem_manage_fault(z_arch_esf_t *esf, int from_hard_fault,
			      bool *recoverable)
{
    1f04:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	uint32_t mmfar = -EINVAL;

	PR_FAULT_INFO("***** MPU FAULT *****");

	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
    1f08:	4c32      	ldr	r4, [pc, #200]	; (1fd4 <mem_manage_fault+0xd0>)
{
    1f0a:	4607      	mov	r7, r0
    1f0c:	4688      	mov	r8, r1
	PR_FAULT_INFO("***** MPU FAULT *****");
    1f0e:	4832      	ldr	r0, [pc, #200]	; (1fd8 <mem_manage_fault+0xd4>)
    1f10:	2145      	movs	r1, #69	; 0x45
{
    1f12:	4615      	mov	r5, r2
	PR_FAULT_INFO("***** MPU FAULT *****");
    1f14:	f003 fe00 	bl	5b18 <z_log_minimal_printk>
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
    1f18:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    1f1a:	06de      	lsls	r6, r3, #27
    1f1c:	d503      	bpl.n	1f26 <mem_manage_fault+0x22>
		PR_FAULT_INFO("  Stacking error (context area might be"
    1f1e:	482f      	ldr	r0, [pc, #188]	; (1fdc <mem_manage_fault+0xd8>)
    1f20:	2145      	movs	r1, #69	; 0x45
    1f22:	f003 fdf9 	bl	5b18 <z_log_minimal_printk>
			" not valid)");
	}
	if ((SCB->CFSR & SCB_CFSR_MUNSTKERR_Msk) != 0) {
    1f26:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    1f28:	071c      	lsls	r4, r3, #28
    1f2a:	d503      	bpl.n	1f34 <mem_manage_fault+0x30>
		PR_FAULT_INFO("  Unstacking error");
    1f2c:	482c      	ldr	r0, [pc, #176]	; (1fe0 <mem_manage_fault+0xdc>)
    1f2e:	2145      	movs	r1, #69	; 0x45
    1f30:	f003 fdf2 	bl	5b18 <z_log_minimal_printk>
	}
	if ((SCB->CFSR & SCB_CFSR_DACCVIOL_Msk) != 0) {
    1f34:	4c27      	ldr	r4, [pc, #156]	; (1fd4 <mem_manage_fault+0xd0>)
    1f36:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    1f38:	0798      	lsls	r0, r3, #30
    1f3a:	d428      	bmi.n	1f8e <mem_manage_fault+0x8a>
	uint32_t mmfar = -EINVAL;
    1f3c:	f06f 0615 	mvn.w	r6, #21
				/* clear SCB_MMAR[VALID] to reset */
				SCB->CFSR &= ~SCB_CFSR_MMARVALID_Msk;
			}
		}
	}
	if ((SCB->CFSR & SCB_CFSR_IACCVIOL_Msk) != 0) {
    1f40:	4c24      	ldr	r4, [pc, #144]	; (1fd4 <mem_manage_fault+0xd0>)
    1f42:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    1f44:	07da      	lsls	r2, r3, #31
    1f46:	d503      	bpl.n	1f50 <mem_manage_fault+0x4c>
		PR_FAULT_INFO("  Instruction Access Violation");
    1f48:	4826      	ldr	r0, [pc, #152]	; (1fe4 <mem_manage_fault+0xe0>)
    1f4a:	2145      	movs	r1, #69	; 0x45
    1f4c:	f003 fde4 	bl	5b18 <z_log_minimal_printk>
	}
#if defined(CONFIG_ARMV7_M_ARMV8_M_FP)
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    1f50:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    1f52:	069b      	lsls	r3, r3, #26
    1f54:	d503      	bpl.n	1f5e <mem_manage_fault+0x5a>
		PR_FAULT_INFO(
    1f56:	4824      	ldr	r0, [pc, #144]	; (1fe8 <mem_manage_fault+0xe4>)
    1f58:	2145      	movs	r1, #69	; 0x45
    1f5a:	f003 fddd 	bl	5b18 <z_log_minimal_printk>
	 * crossed into an area beyond the thread stack.]
	 *
	 * Data Access Violation errors may or may not be caused by
	 * thread stack overflows.
	 */
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) ||
    1f5e:	4b1d      	ldr	r3, [pc, #116]	; (1fd4 <mem_manage_fault+0xd0>)
    1f60:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    1f62:	06d4      	lsls	r4, r2, #27
    1f64:	d428      	bmi.n	1fb8 <mem_manage_fault+0xb4>
		(SCB->CFSR & SCB_CFSR_DACCVIOL_Msk)) {
    1f66:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) ||
    1f68:	0790      	lsls	r0, r2, #30
    1f6a:	d425      	bmi.n	1fb8 <mem_manage_fault+0xb4>
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    1f6c:	2000      	movs	r0, #0
	 * lazy stacking Memory Manage fault. At the time of writing, this
	 * can happen when printing.  If that's true, we should clear the
	 * pending flag in addition to the clearing the reason for the fault
	 */
#if defined(CONFIG_ARMV7_M_ARMV8_M_FP)
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    1f6e:	4b19      	ldr	r3, [pc, #100]	; (1fd4 <mem_manage_fault+0xd0>)
    1f70:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    1f72:	0692      	lsls	r2, r2, #26
		SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTPENDED_Msk;
    1f74:	bf42      	ittt	mi
    1f76:	6a5a      	ldrmi	r2, [r3, #36]	; 0x24
    1f78:	f422 5200 	bicmi.w	r2, r2, #8192	; 0x2000
    1f7c:	625a      	strmi	r2, [r3, #36]	; 0x24
	}
#endif /* CONFIG_ARMV7_M_ARMV8_M_FP */

	/* clear MMFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_MEMFAULTSR_Msk;
    1f7e:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    1f80:	f042 02ff 	orr.w	r2, r2, #255	; 0xff
    1f84:	629a      	str	r2, [r3, #40]	; 0x28

	/* Assess whether system shall ignore/recover from this MPU fault. */
	*recoverable = memory_fault_recoverable(esf, true);
    1f86:	2300      	movs	r3, #0
    1f88:	702b      	strb	r3, [r5, #0]

	return reason;
}
    1f8a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		PR_FAULT_INFO("  Data Access Violation");
    1f8e:	2145      	movs	r1, #69	; 0x45
    1f90:	4816      	ldr	r0, [pc, #88]	; (1fec <mem_manage_fault+0xe8>)
    1f92:	f003 fdc1 	bl	5b18 <z_log_minimal_printk>
		uint32_t temp = SCB->MMFAR;
    1f96:	6b66      	ldr	r6, [r4, #52]	; 0x34
		if ((SCB->CFSR & SCB_CFSR_MMARVALID_Msk) != 0) {
    1f98:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    1f9a:	0619      	lsls	r1, r3, #24
    1f9c:	d5ce      	bpl.n	1f3c <mem_manage_fault+0x38>
			PR_EXC("  MMFAR Address: 0x%x", mmfar);
    1f9e:	4814      	ldr	r0, [pc, #80]	; (1ff0 <mem_manage_fault+0xec>)
    1fa0:	4632      	mov	r2, r6
    1fa2:	2145      	movs	r1, #69	; 0x45
    1fa4:	f003 fdb8 	bl	5b18 <z_log_minimal_printk>
			if (from_hard_fault != 0) {
    1fa8:	f1b8 0f00 	cmp.w	r8, #0
    1fac:	d0c8      	beq.n	1f40 <mem_manage_fault+0x3c>
				SCB->CFSR &= ~SCB_CFSR_MMARVALID_Msk;
    1fae:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    1fb0:	f023 0380 	bic.w	r3, r3, #128	; 0x80
    1fb4:	62a3      	str	r3, [r4, #40]	; 0x28
    1fb6:	e7c3      	b.n	1f40 <mem_manage_fault+0x3c>
		if (SCB->ICSR & SCB_ICSR_RETTOBASE_Msk) {
    1fb8:	685b      	ldr	r3, [r3, #4]
    1fba:	0519      	lsls	r1, r3, #20
    1fbc:	d5d6      	bpl.n	1f6c <mem_manage_fault+0x68>
			uint32_t min_stack_ptr = z_check_thread_stack_fail(mmfar,
    1fbe:	4639      	mov	r1, r7
    1fc0:	4630      	mov	r0, r6
    1fc2:	f7ff ff5b 	bl	1e7c <z_check_thread_stack_fail>
			if (min_stack_ptr) {
    1fc6:	2800      	cmp	r0, #0
    1fc8:	d0d0      	beq.n	1f6c <mem_manage_fault+0x68>
  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
    1fca:	f380 8809 	msr	PSP, r0
				reason = K_ERR_STACK_CHK_FAIL;
    1fce:	2002      	movs	r0, #2
    1fd0:	e7cd      	b.n	1f6e <mem_manage_fault+0x6a>
    1fd2:	bf00      	nop
    1fd4:	e000ed00 	.word	0xe000ed00
    1fd8:	00006f39 	.word	0x00006f39
    1fdc:	00006f54 	.word	0x00006f54
    1fe0:	00006f8c 	.word	0x00006f8c
    1fe4:	00006fdc 	.word	0x00006fdc
    1fe8:	00007000 	.word	0x00007000
    1fec:	00006fa4 	.word	0x00006fa4
    1ff0:	00006fc1 	.word	0x00006fc1

00001ff4 <usage_fault.constprop.0>:
 *
 * See z_arm_fault_dump() for example.
 *
 * @return error code to identify the fatal error reason
 */
static uint32_t usage_fault(const z_arch_esf_t *esf)
    1ff4:	b510      	push	{r4, lr}
	uint32_t reason = K_ERR_CPU_EXCEPTION;

	PR_FAULT_INFO("***** USAGE FAULT *****");

	/* bits are sticky: they stack and must be reset */
	if ((SCB->CFSR & SCB_CFSR_DIVBYZERO_Msk) != 0) {
    1ff6:	4c1d      	ldr	r4, [pc, #116]	; (206c <usage_fault.constprop.0+0x78>)
	PR_FAULT_INFO("***** USAGE FAULT *****");
    1ff8:	481d      	ldr	r0, [pc, #116]	; (2070 <usage_fault.constprop.0+0x7c>)
    1ffa:	2145      	movs	r1, #69	; 0x45
    1ffc:	f003 fd8c 	bl	5b18 <z_log_minimal_printk>
	if ((SCB->CFSR & SCB_CFSR_DIVBYZERO_Msk) != 0) {
    2000:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2002:	019b      	lsls	r3, r3, #6
    2004:	d503      	bpl.n	200e <usage_fault.constprop.0+0x1a>
		PR_FAULT_INFO("  Division by zero");
    2006:	481b      	ldr	r0, [pc, #108]	; (2074 <usage_fault.constprop.0+0x80>)
    2008:	2145      	movs	r1, #69	; 0x45
    200a:	f003 fd85 	bl	5b18 <z_log_minimal_printk>
	}
	if ((SCB->CFSR & SCB_CFSR_UNALIGNED_Msk) != 0) {
    200e:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2010:	01dc      	lsls	r4, r3, #7
    2012:	d503      	bpl.n	201c <usage_fault.constprop.0+0x28>
		PR_FAULT_INFO("  Unaligned memory access");
    2014:	4818      	ldr	r0, [pc, #96]	; (2078 <usage_fault.constprop.0+0x84>)
    2016:	2145      	movs	r1, #69	; 0x45
    2018:	f003 fd7e 	bl	5b18 <z_log_minimal_printk>
		 */
		reason = K_ERR_STACK_CHK_FAIL;
#endif /* CONFIG_BUILTIN_STACK_GUARD */
	}
#endif /* CONFIG_ARMV8_M_MAINLINE */
	if ((SCB->CFSR & SCB_CFSR_NOCP_Msk) != 0) {
    201c:	4c13      	ldr	r4, [pc, #76]	; (206c <usage_fault.constprop.0+0x78>)
    201e:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2020:	0318      	lsls	r0, r3, #12
    2022:	d503      	bpl.n	202c <usage_fault.constprop.0+0x38>
		PR_FAULT_INFO("  No coprocessor instructions");
    2024:	4815      	ldr	r0, [pc, #84]	; (207c <usage_fault.constprop.0+0x88>)
    2026:	2145      	movs	r1, #69	; 0x45
    2028:	f003 fd76 	bl	5b18 <z_log_minimal_printk>
	}
	if ((SCB->CFSR & SCB_CFSR_INVPC_Msk) != 0) {
    202c:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    202e:	0359      	lsls	r1, r3, #13
    2030:	d503      	bpl.n	203a <usage_fault.constprop.0+0x46>
		PR_FAULT_INFO("  Illegal load of EXC_RETURN into PC");
    2032:	4813      	ldr	r0, [pc, #76]	; (2080 <usage_fault.constprop.0+0x8c>)
    2034:	2145      	movs	r1, #69	; 0x45
    2036:	f003 fd6f 	bl	5b18 <z_log_minimal_printk>
	}
	if ((SCB->CFSR & SCB_CFSR_INVSTATE_Msk) != 0) {
    203a:	4c0c      	ldr	r4, [pc, #48]	; (206c <usage_fault.constprop.0+0x78>)
    203c:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    203e:	039a      	lsls	r2, r3, #14
    2040:	d503      	bpl.n	204a <usage_fault.constprop.0+0x56>
		PR_FAULT_INFO("  Illegal use of the EPSR");
    2042:	4810      	ldr	r0, [pc, #64]	; (2084 <usage_fault.constprop.0+0x90>)
    2044:	2145      	movs	r1, #69	; 0x45
    2046:	f003 fd67 	bl	5b18 <z_log_minimal_printk>
	}
	if ((SCB->CFSR & SCB_CFSR_UNDEFINSTR_Msk) != 0) {
    204a:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    204c:	03db      	lsls	r3, r3, #15
    204e:	d503      	bpl.n	2058 <usage_fault.constprop.0+0x64>
		PR_FAULT_INFO("  Attempt to execute undefined instruction");
    2050:	480d      	ldr	r0, [pc, #52]	; (2088 <usage_fault.constprop.0+0x94>)
    2052:	2145      	movs	r1, #69	; 0x45
    2054:	f003 fd60 	bl	5b18 <z_log_minimal_printk>
	}

	/* clear UFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    2058:	4a04      	ldr	r2, [pc, #16]	; (206c <usage_fault.constprop.0+0x78>)
    205a:	6a93      	ldr	r3, [r2, #40]	; 0x28
    205c:	ea6f 4303 	mvn.w	r3, r3, lsl #16
    2060:	ea6f 4313 	mvn.w	r3, r3, lsr #16
    2064:	6293      	str	r3, [r2, #40]	; 0x28

	return reason;
}
    2066:	2000      	movs	r0, #0
    2068:	bd10      	pop	{r4, pc}
    206a:	bf00      	nop
    206c:	e000ed00 	.word	0xe000ed00
    2070:	00007034 	.word	0x00007034
    2074:	00007051 	.word	0x00007051
    2078:	00007069 	.word	0x00007069
    207c:	00007088 	.word	0x00007088
    2080:	000070ab 	.word	0x000070ab
    2084:	000070d5 	.word	0x000070d5
    2088:	000070f4 	.word	0x000070f4

0000208c <bus_fault.constprop.0>:
static int bus_fault(z_arch_esf_t *esf, int from_hard_fault, bool *recoverable)
    208c:	b570      	push	{r4, r5, r6, lr}
	if (SCB->CFSR & SCB_CFSR_STKERR_Msk) {
    208e:	4c23      	ldr	r4, [pc, #140]	; (211c <bus_fault.constprop.0+0x90>)
static int bus_fault(z_arch_esf_t *esf, int from_hard_fault, bool *recoverable)
    2090:	4606      	mov	r6, r0
    2092:	460d      	mov	r5, r1
	PR_FAULT_INFO("***** BUS FAULT *****");
    2094:	4822      	ldr	r0, [pc, #136]	; (2120 <bus_fault.constprop.0+0x94>)
    2096:	2145      	movs	r1, #69	; 0x45
    2098:	f003 fd3e 	bl	5b18 <z_log_minimal_printk>
	if (SCB->CFSR & SCB_CFSR_STKERR_Msk) {
    209c:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    209e:	04d9      	lsls	r1, r3, #19
    20a0:	d503      	bpl.n	20aa <bus_fault.constprop.0+0x1e>
		PR_FAULT_INFO("  Stacking error");
    20a2:	4820      	ldr	r0, [pc, #128]	; (2124 <bus_fault.constprop.0+0x98>)
    20a4:	2145      	movs	r1, #69	; 0x45
    20a6:	f003 fd37 	bl	5b18 <z_log_minimal_printk>
	if (SCB->CFSR & SCB_CFSR_UNSTKERR_Msk) {
    20aa:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    20ac:	051a      	lsls	r2, r3, #20
    20ae:	d503      	bpl.n	20b8 <bus_fault.constprop.0+0x2c>
		PR_FAULT_INFO("  Unstacking error");
    20b0:	481d      	ldr	r0, [pc, #116]	; (2128 <bus_fault.constprop.0+0x9c>)
    20b2:	2145      	movs	r1, #69	; 0x45
    20b4:	f003 fd30 	bl	5b18 <z_log_minimal_printk>
	if (SCB->CFSR & SCB_CFSR_PRECISERR_Msk) {
    20b8:	4c18      	ldr	r4, [pc, #96]	; (211c <bus_fault.constprop.0+0x90>)
    20ba:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    20bc:	059b      	lsls	r3, r3, #22
    20be:	d510      	bpl.n	20e2 <bus_fault.constprop.0+0x56>
		PR_FAULT_INFO("  Precise data bus error");
    20c0:	481a      	ldr	r0, [pc, #104]	; (212c <bus_fault.constprop.0+0xa0>)
    20c2:	2145      	movs	r1, #69	; 0x45
    20c4:	f003 fd28 	bl	5b18 <z_log_minimal_printk>
		STORE_xFAR(bfar, SCB->BFAR);
    20c8:	6ba2      	ldr	r2, [r4, #56]	; 0x38
		if ((SCB->CFSR & SCB_CFSR_BFARVALID_Msk) != 0) {
    20ca:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    20cc:	0418      	lsls	r0, r3, #16
    20ce:	d508      	bpl.n	20e2 <bus_fault.constprop.0+0x56>
			PR_EXC("  BFAR Address: 0x%x", bfar);
    20d0:	4817      	ldr	r0, [pc, #92]	; (2130 <bus_fault.constprop.0+0xa4>)
    20d2:	2145      	movs	r1, #69	; 0x45
    20d4:	f003 fd20 	bl	5b18 <z_log_minimal_printk>
			if (from_hard_fault != 0) {
    20d8:	b11e      	cbz	r6, 20e2 <bus_fault.constprop.0+0x56>
				SCB->CFSR &= ~SCB_CFSR_BFARVALID_Msk;
    20da:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    20dc:	f423 4300 	bic.w	r3, r3, #32768	; 0x8000
    20e0:	62a3      	str	r3, [r4, #40]	; 0x28
	if (SCB->CFSR & SCB_CFSR_IMPRECISERR_Msk) {
    20e2:	4c0e      	ldr	r4, [pc, #56]	; (211c <bus_fault.constprop.0+0x90>)
    20e4:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    20e6:	0559      	lsls	r1, r3, #21
    20e8:	d503      	bpl.n	20f2 <bus_fault.constprop.0+0x66>
		PR_FAULT_INFO("  Imprecise data bus error");
    20ea:	4812      	ldr	r0, [pc, #72]	; (2134 <bus_fault.constprop.0+0xa8>)
    20ec:	2145      	movs	r1, #69	; 0x45
    20ee:	f003 fd13 	bl	5b18 <z_log_minimal_printk>
	if ((SCB->CFSR & SCB_CFSR_IBUSERR_Msk) != 0) {
    20f2:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    20f4:	05da      	lsls	r2, r3, #23
    20f6:	d50b      	bpl.n	2110 <bus_fault.constprop.0+0x84>
		PR_FAULT_INFO("  Instruction bus error");
    20f8:	480f      	ldr	r0, [pc, #60]	; (2138 <bus_fault.constprop.0+0xac>)
    20fa:	2145      	movs	r1, #69	; 0x45
		PR_FAULT_INFO("  Floating-point lazy state preservation error");
    20fc:	f003 fd0c 	bl	5b18 <z_log_minimal_printk>
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
    2100:	4a06      	ldr	r2, [pc, #24]	; (211c <bus_fault.constprop.0+0x90>)
    2102:	6a93      	ldr	r3, [r2, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf, true);
    2104:	2000      	movs	r0, #0
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
    2106:	f443 437f 	orr.w	r3, r3, #65280	; 0xff00
    210a:	6293      	str	r3, [r2, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf, true);
    210c:	7028      	strb	r0, [r5, #0]
}
    210e:	bd70      	pop	{r4, r5, r6, pc}
	} else if (SCB->CFSR & SCB_CFSR_LSPERR_Msk) {
    2110:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    2112:	049b      	lsls	r3, r3, #18
    2114:	d5f4      	bpl.n	2100 <bus_fault.constprop.0+0x74>
		PR_FAULT_INFO("  Floating-point lazy state preservation error");
    2116:	4809      	ldr	r0, [pc, #36]	; (213c <bus_fault.constprop.0+0xb0>)
    2118:	2145      	movs	r1, #69	; 0x45
    211a:	e7ef      	b.n	20fc <bus_fault.constprop.0+0x70>
    211c:	e000ed00 	.word	0xe000ed00
    2120:	00007124 	.word	0x00007124
    2124:	0000713f 	.word	0x0000713f
    2128:	00006f8c 	.word	0x00006f8c
    212c:	00007155 	.word	0x00007155
    2130:	00007173 	.word	0x00007173
    2134:	0000718d 	.word	0x0000718d
    2138:	000071ad 	.word	0x000071ad
    213c:	00007000 	.word	0x00007000

00002140 <z_arm_fault>:
 * @param callee_regs Callee-saved registers (R4-R11, PSP)
 *
 */
void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return,
	_callee_saved_t *callee_regs)
{
    2140:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    2144:	4b55      	ldr	r3, [pc, #340]	; (229c <z_arm_fault+0x15c>)
    2146:	685f      	ldr	r7, [r3, #4]
{
    2148:	b08a      	sub	sp, #40	; 0x28
    214a:	460d      	mov	r5, r1
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    214c:	f3c7 0408 	ubfx	r4, r7, #0, #9
	__asm__ volatile(
    2150:	2600      	movs	r6, #0
    2152:	f386 8811 	msr	BASEPRI, r6
    2156:	f3bf 8f6f 	isb	sy
	if ((exc_return & EXC_RETURN_INDICATOR_PREFIX) !=
    215a:	f002 437f 	and.w	r3, r2, #4278190080	; 0xff000000
    215e:	f1b3 4f7f 	cmp.w	r3, #4278190080	; 0xff000000
    2162:	d107      	bne.n	2174 <z_arm_fault+0x34>
	if ((exc_return & EXC_RETURN_MODE_THREAD) &&
    2164:	f002 030c 	and.w	r3, r2, #12
    2168:	2b08      	cmp	r3, #8
    216a:	d105      	bne.n	2178 <z_arm_fault+0x38>
		PR_EXC("SPSEL in thread mode does not indicate PSP");
    216c:	484c      	ldr	r0, [pc, #304]	; (22a0 <z_arm_fault+0x160>)
    216e:	2145      	movs	r1, #69	; 0x45
    2170:	f003 fcd2 	bl	5b18 <z_log_minimal_printk>
		return NULL;
    2174:	4635      	mov	r5, r6
    2176:	e003      	b.n	2180 <z_arm_fault+0x40>
		if (exc_return & EXC_RETURN_MODE_THREAD) {
    2178:	0712      	lsls	r2, r2, #28
    217a:	d401      	bmi.n	2180 <z_arm_fault+0x40>
			ptr_esf = (z_arch_esf_t *)msp;
    217c:	4605      	mov	r5, r0
			*nested_exc = true;
    217e:	2601      	movs	r6, #1
	*recoverable = false;
    2180:	f04f 0800 	mov.w	r8, #0
	switch (fault) {
    2184:	1ee3      	subs	r3, r4, #3
	*recoverable = false;
    2186:	f88d 8007 	strb.w	r8, [sp, #7]
	switch (fault) {
    218a:	2b09      	cmp	r3, #9
    218c:	d873      	bhi.n	2276 <z_arm_fault+0x136>
    218e:	e8df f003 	tbb	[pc, r3]
    2192:	6705      	.short	0x6705
    2194:	7272646b 	.word	0x7272646b
    2198:	6f727272 	.word	0x6f727272
	if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk) != 0) {
    219c:	4f3f      	ldr	r7, [pc, #252]	; (229c <z_arm_fault+0x15c>)
	PR_FAULT_INFO("***** HARD FAULT *****");
    219e:	4841      	ldr	r0, [pc, #260]	; (22a4 <z_arm_fault+0x164>)
    21a0:	2145      	movs	r1, #69	; 0x45
    21a2:	f003 fcb9 	bl	5b18 <z_log_minimal_printk>
	if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk) != 0) {
    21a6:	6afc      	ldr	r4, [r7, #44]	; 0x2c
	*recoverable = false;
    21a8:	f88d 8007 	strb.w	r8, [sp, #7]
	if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk) != 0) {
    21ac:	f014 0402 	ands.w	r4, r4, #2
    21b0:	d005      	beq.n	21be <z_arm_fault+0x7e>
		PR_EXC("  Bus fault on vector table read");
    21b2:	483d      	ldr	r0, [pc, #244]	; (22a8 <z_arm_fault+0x168>)
    21b4:	2145      	movs	r1, #69	; 0x45
	PR_FAULT_INFO(
    21b6:	f003 fcaf 	bl	5b18 <z_log_minimal_printk>
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    21ba:	2400      	movs	r4, #0
}
    21bc:	e006      	b.n	21cc <z_arm_fault+0x8c>
	} else if ((SCB->HFSR & SCB_HFSR_DEBUGEVT_Msk) != 0) {
    21be:	6afb      	ldr	r3, [r7, #44]	; 0x2c
    21c0:	2b00      	cmp	r3, #0
    21c2:	da1d      	bge.n	2200 <z_arm_fault+0xc0>
		PR_EXC("  Debug event");
    21c4:	4839      	ldr	r0, [pc, #228]	; (22ac <z_arm_fault+0x16c>)
    21c6:	2145      	movs	r1, #69	; 0x45
    21c8:	f003 fca6 	bl	5b18 <z_log_minimal_printk>
#ifdef CONFIG_DEBUG_COREDUMP
	z_arm_coredump_fault_sp = POINTER_TO_UINT(esf);
#endif

	reason = fault_handle(esf, fault, &recoverable);
	if (recoverable) {
    21cc:	f89d 3007 	ldrb.w	r3, [sp, #7]
    21d0:	b99b      	cbnz	r3, 21fa <z_arm_fault+0xba>
		return;
	}

	/* Copy ESF */
#if !defined(CONFIG_EXTRA_EXCEPTION_INFO)
	memcpy(&esf_copy, esf, sizeof(z_arch_esf_t));
    21d2:	2220      	movs	r2, #32
    21d4:	4629      	mov	r1, r5
    21d6:	a802      	add	r0, sp, #8
    21d8:	f003 fd68 	bl	5cac <memcpy>
	/* Overwrite stacked IPSR to mark a nested exception,
	 * or a return to Thread mode. Note that this may be
	 * required, if the retrieved ESF contents are invalid
	 * due to, for instance, a stacking error.
	 */
	if (nested_exc) {
    21dc:	9b09      	ldr	r3, [sp, #36]	; 0x24
    21de:	2e00      	cmp	r6, #0
    21e0:	d056      	beq.n	2290 <z_arm_fault+0x150>
		if ((esf_copy.basic.xpsr & IPSR_ISR_Msk) == 0) {
    21e2:	f3c3 0208 	ubfx	r2, r3, #0, #9
    21e6:	b922      	cbnz	r2, 21f2 <z_arm_fault+0xb2>
			esf_copy.basic.xpsr |= IPSR_ISR_Msk;
    21e8:	ea6f 2353 	mvn.w	r3, r3, lsr #9
    21ec:	ea6f 2343 	mvn.w	r3, r3, lsl #9
		}
	} else {
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    21f0:	9309      	str	r3, [sp, #36]	; 0x24
	}

	z_arm_fatal_error(reason, &esf_copy);
    21f2:	a902      	add	r1, sp, #8
    21f4:	4620      	mov	r0, r4
    21f6:	f7ff fdad 	bl	1d54 <z_arm_fatal_error>
}
    21fa:	b00a      	add	sp, #40	; 0x28
    21fc:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
	} else if ((SCB->HFSR & SCB_HFSR_FORCED_Msk) != 0) {
    2200:	6afb      	ldr	r3, [r7, #44]	; 0x2c
    2202:	005b      	lsls	r3, r3, #1
    2204:	d5e2      	bpl.n	21cc <z_arm_fault+0x8c>
		PR_EXC("  Fault escalation (see below)");
    2206:	482a      	ldr	r0, [pc, #168]	; (22b0 <z_arm_fault+0x170>)
    2208:	2145      	movs	r1, #69	; 0x45
    220a:	f003 fc85 	bl	5b18 <z_log_minimal_printk>
	uint16_t fault_insn = *(ret_addr - 1);
    220e:	69ab      	ldr	r3, [r5, #24]
	if (((fault_insn & 0xff00) == _SVC_OPCODE) &&
    2210:	f833 2c02 	ldrh.w	r2, [r3, #-2]
    2214:	f64d 7302 	movw	r3, #57090	; 0xdf02
    2218:	429a      	cmp	r2, r3
    221a:	d00a      	beq.n	2232 <z_arm_fault+0xf2>
		} else if (SCB_MMFSR != 0) {
    221c:	f897 3028 	ldrb.w	r3, [r7, #40]	; 0x28
    2220:	b173      	cbz	r3, 2240 <z_arm_fault+0x100>
			reason = mem_manage_fault(esf, 1, recoverable);
    2222:	f10d 0207 	add.w	r2, sp, #7
    2226:	2101      	movs	r1, #1
		reason = mem_manage_fault(esf, 0, recoverable);
    2228:	4628      	mov	r0, r5
    222a:	f7ff fe6b 	bl	1f04 <mem_manage_fault>
    222e:	4604      	mov	r4, r0
		break;
    2230:	e7cc      	b.n	21cc <z_arm_fault+0x8c>
			PR_EXC("ARCH_EXCEPT with reason %x\n", esf->basic.r0);
    2232:	682a      	ldr	r2, [r5, #0]
    2234:	481f      	ldr	r0, [pc, #124]	; (22b4 <z_arm_fault+0x174>)
    2236:	2145      	movs	r1, #69	; 0x45
    2238:	f003 fc6e 	bl	5b18 <z_log_minimal_printk>
			reason = esf->basic.r0;
    223c:	682c      	ldr	r4, [r5, #0]
    223e:	e7c5      	b.n	21cc <z_arm_fault+0x8c>
		} else if (SCB_BFSR != 0) {
    2240:	f897 3029 	ldrb.w	r3, [r7, #41]	; 0x29
    2244:	b12b      	cbz	r3, 2252 <z_arm_fault+0x112>
			reason = bus_fault(esf, 1, recoverable);
    2246:	f10d 0107 	add.w	r1, sp, #7
    224a:	2001      	movs	r0, #1
		reason = bus_fault(esf, 0, recoverable);
    224c:	f7ff ff1e 	bl	208c <bus_fault.constprop.0>
    2250:	e7ed      	b.n	222e <z_arm_fault+0xee>
		} else if (SCB_UFSR != 0) {
    2252:	8d7b      	ldrh	r3, [r7, #42]	; 0x2a
    2254:	b29b      	uxth	r3, r3
    2256:	2b00      	cmp	r3, #0
    2258:	d0b8      	beq.n	21cc <z_arm_fault+0x8c>
		reason = usage_fault(esf);
    225a:	f7ff fecb 	bl	1ff4 <usage_fault.constprop.0>
    225e:	e7e6      	b.n	222e <z_arm_fault+0xee>
		reason = mem_manage_fault(esf, 0, recoverable);
    2260:	f10d 0207 	add.w	r2, sp, #7
    2264:	2100      	movs	r1, #0
    2266:	e7df      	b.n	2228 <z_arm_fault+0xe8>
		reason = bus_fault(esf, 0, recoverable);
    2268:	f10d 0107 	add.w	r1, sp, #7
    226c:	2000      	movs	r0, #0
    226e:	e7ed      	b.n	224c <z_arm_fault+0x10c>
	PR_FAULT_INFO(
    2270:	4811      	ldr	r0, [pc, #68]	; (22b8 <z_arm_fault+0x178>)
    2272:	2145      	movs	r1, #69	; 0x45
    2274:	e79f      	b.n	21b6 <z_arm_fault+0x76>
	PR_FAULT_INFO("***** %s %d) *****",
    2276:	4911      	ldr	r1, [pc, #68]	; (22bc <z_arm_fault+0x17c>)
    2278:	4a11      	ldr	r2, [pc, #68]	; (22c0 <z_arm_fault+0x180>)
    227a:	4812      	ldr	r0, [pc, #72]	; (22c4 <z_arm_fault+0x184>)
    227c:	f417 7ff8 	tst.w	r7, #496	; 0x1f0
    2280:	bf08      	it	eq
    2282:	460a      	moveq	r2, r1
    2284:	f1a4 0310 	sub.w	r3, r4, #16
    2288:	2145      	movs	r1, #69	; 0x45
    228a:	f003 fc45 	bl	5b18 <z_log_minimal_printk>
    228e:	e794      	b.n	21ba <z_arm_fault+0x7a>
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    2290:	f423 73ff 	bic.w	r3, r3, #510	; 0x1fe
    2294:	f023 0301 	bic.w	r3, r3, #1
    2298:	e7aa      	b.n	21f0 <z_arm_fault+0xb0>
    229a:	bf00      	nop
    229c:	e000ed00 	.word	0xe000ed00
    22a0:	000071f8 	.word	0x000071f8
    22a4:	00007228 	.word	0x00007228
    22a8:	00007244 	.word	0x00007244
    22ac:	0000726a 	.word	0x0000726a
    22b0:	0000727d 	.word	0x0000727d
    22b4:	000072a1 	.word	0x000072a1
    22b8:	000072c2 	.word	0x000072c2
    22bc:	000071ca 	.word	0x000071ca
    22c0:	000071df 	.word	0x000071df
    22c4:	000072eb 	.word	0x000072eb

000022c8 <z_arm_fault_init>:
 */
void z_arm_fault_init(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
    22c8:	4a02      	ldr	r2, [pc, #8]	; (22d4 <z_arm_fault_init+0xc>)
    22ca:	6953      	ldr	r3, [r2, #20]
    22cc:	f043 0310 	orr.w	r3, r3, #16
    22d0:	6153      	str	r3, [r2, #20]
	SCB->CCR |= SCB_CCR_STKOFHFNMIGN_Msk;
#endif /* CONFIG_BUILTIN_STACK_GUARD */
#ifdef CONFIG_TRAP_UNALIGNED_ACCESS
	SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif /* CONFIG_TRAP_UNALIGNED_ACCESS */
}
    22d2:	4770      	bx	lr
    22d4:	e000ed00 	.word	0xe000ed00

000022d8 <z_arm_bus_fault>:
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_exc_spurious)

	mrs r0, MSP
    22d8:	f3ef 8008 	mrs	r0, MSP
	mrs r1, PSP
    22dc:	f3ef 8109 	mrs	r1, PSP
	push {r0, lr}
    22e0:	b501      	push	{r0, lr}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	push {r4-r11}
#endif
	mov  r3, sp /* pointer to _callee_saved_t */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
	mov r2, lr /* EXC_RETURN */
    22e2:	4672      	mov	r2, lr
	bl z_arm_fault
    22e4:	f7ff ff2c 	bl	2140 <z_arm_fault>
	 * in this routine. Therefore, we can just reset
	 * the MSP to its value prior to entering the function
	 */
	add sp, #40
#endif
	pop {r0, pc}
    22e8:	bd01      	pop	{r0, pc}
    22ea:	bf00      	nop

000022ec <z_arm_interrupt_init>:
    22ec:	4804      	ldr	r0, [pc, #16]	; (2300 <z_arm_interrupt_init+0x14>)
 *
 */

void z_arm_interrupt_init(void)
{
	int irq = 0;
    22ee:	2300      	movs	r3, #0
    22f0:	2120      	movs	r1, #32
    22f2:	18c2      	adds	r2, r0, r3

	for (; irq < CONFIG_NUM_IRQS; irq++) {
    22f4:	3301      	adds	r3, #1
    22f6:	2b27      	cmp	r3, #39	; 0x27
    22f8:	f882 1300 	strb.w	r1, [r2, #768]	; 0x300
    22fc:	d1f9      	bne.n	22f2 <z_arm_interrupt_init+0x6>
		NVIC_SetPriority((IRQn_Type)irq, _IRQ_PRIO_OFFSET);
	}
}
    22fe:	4770      	bx	lr
    2300:	e000e100 	.word	0xe000e100

00002304 <__start>:
 */
SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
    /* Reset CONTROL register */
    movs.n r0, #0
    2304:	2000      	movs	r0, #0
    msr CONTROL, r0
    2306:	f380 8814 	msr	CONTROL, r0
    isb
    230a:	f3bf 8f6f 	isb	sy
#endif /* CONFIG_CPU_CORTEX_M_HAS_SPLIM */

#endif /* CONFIG_INIT_ARCH_HW_AT_BOOT */

#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
    bl z_arm_platform_init
    230e:	f004 f88b 	bl	6428 <z_arm_platform_init>
#endif

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
#if defined(CONFIG_CPU_HAS_ARM_MPU)
    /* Disable MPU */
    movs.n r0, #0
    2312:	2000      	movs	r0, #0
    ldr r1, =_SCS_MPU_CTRL
    2314:	490d      	ldr	r1, [pc, #52]	; (234c <__start+0x48>)
    str r0, [r1]
    2316:	6008      	str	r0, [r1, #0]
    dsb
    2318:	f3bf 8f4f 	dsb	sy
#endif /* CONFIG_CPU_HAS_ARM_MPU */
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    231c:	480c      	ldr	r0, [pc, #48]	; (2350 <__start+0x4c>)
    msr msp, r0
    231e:	f380 8808 	msr	MSP, r0

    /* Initialize core architecture registers and system blocks */
    bl z_arm_init_arch_hw_at_boot
    2322:	f000 f82b 	bl	237c <z_arm_init_arch_hw_at_boot>

    /* lock interrupts: will get unlocked when switch to main task */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    2326:	2020      	movs	r0, #32
    msr BASEPRI, r0
    2328:	f380 8811 	msr	BASEPRI, r0

    /*
     * Set PSP and use it to boot without using MSP, so that it
     * gets set to z_interrupt_stacks during initialization.
     */
    ldr r0, =z_interrupt_stacks
    232c:	4809      	ldr	r0, [pc, #36]	; (2354 <__start+0x50>)
    ldr r1, =CONFIG_ISR_STACK_SIZE + MPU_GUARD_ALIGN_AND_SIZE
    232e:	f44f 6102 	mov.w	r1, #2080	; 0x820
    adds r0, r0, r1
    2332:	1840      	adds	r0, r0, r1
    msr PSP, r0
    2334:	f380 8809 	msr	PSP, r0
    mrs r0, CONTROL
    2338:	f3ef 8014 	mrs	r0, CONTROL
    movs r1, #2
    233c:	2102      	movs	r1, #2
    orrs r0, r1 /* CONTROL_SPSEL_Msk */
    233e:	4308      	orrs	r0, r1
    msr CONTROL, r0
    2340:	f380 8814 	msr	CONTROL, r0
    /*
     * When changing the stack pointer, software must use an ISB instruction
     * immediately after the MSR instruction. This ensures that instructions
     * after the ISB instruction execute using the new stack pointer.
     */
    isb
    2344:	f3bf 8f6f 	isb	sy
    /*
     * 'bl' jumps the furthest of the branch instructions that are
     * supported on all platforms. So it is used when jumping to z_arm_prep_c
     * (even though we do not intend to return).
     */
    bl z_arm_prep_c
    2348:	f7ff fd6c 	bl	1e24 <z_arm_prep_c>
    ldr r1, =_SCS_MPU_CTRL
    234c:	e000ed94 	.word	0xe000ed94
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    2350:	20003c20 	.word	0x20003c20
    ldr r0, =z_interrupt_stacks
    2354:	20003c40 	.word	0x20003c40

00002358 <z_arm_clear_arm_mpu_config>:
void z_arm_clear_arm_mpu_config(void)
{
	int i;

	int num_regions =
		((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos);
    2358:	4907      	ldr	r1, [pc, #28]	; (2378 <z_arm_clear_arm_mpu_config+0x20>)
    235a:	f8d1 2090 	ldr.w	r2, [r1, #144]	; 0x90

	for (i = 0; i < num_regions; i++) {
    235e:	2300      	movs	r3, #0
	int num_regions =
    2360:	f3c2 2207 	ubfx	r2, r2, #8, #8
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
  MPU->RNR = rnr;
  MPU->RASR = 0U;
    2364:	4618      	mov	r0, r3
	for (i = 0; i < num_regions; i++) {
    2366:	4293      	cmp	r3, r2
    2368:	d100      	bne.n	236c <z_arm_clear_arm_mpu_config+0x14>
		ARM_MPU_ClrRegion(i);
	}
}
    236a:	4770      	bx	lr
  MPU->RNR = rnr;
    236c:	f8c1 3098 	str.w	r3, [r1, #152]	; 0x98
  MPU->RASR = 0U;
    2370:	f8c1 00a0 	str.w	r0, [r1, #160]	; 0xa0
	for (i = 0; i < num_regions; i++) {
    2374:	3301      	adds	r3, #1
    2376:	e7f6      	b.n	2366 <z_arm_clear_arm_mpu_config+0xe>
    2378:	e000ed00 	.word	0xe000ed00

0000237c <z_arm_init_arch_hw_at_boot>:
 * This routine resets Cortex-M system control block
 * components and core registers.
 *
 */
void z_arm_init_arch_hw_at_boot(void)
{
    237c:	b508      	push	{r3, lr}
  __ASM volatile ("cpsid i" : : : "memory");
    237e:	b672      	cpsid	i
  \details Assigns the given value to the Fault Mask register.
  \param [in]    faultMask  Fault Mask value to set
 */
__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
{
  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
    2380:	2300      	movs	r3, #0
    2382:	f383 8813 	msr	FAULTMASK, r3

	/* Initialize System Control Block components */

#if defined(CONFIG_CPU_HAS_ARM_MPU) || defined(CONFIG_CPU_HAS_NXP_MPU)
	/* Clear MPU region configuration */
	z_arm_clear_arm_mpu_config();
    2386:	f7ff ffe7 	bl	2358 <z_arm_clear_arm_mpu_config>
#endif /* CONFIG_CPU_HAS_ARM_MPU */

	/* Disable NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
		NVIC->ICER[i] = 0xFFFFFFFF;
    238a:	4b14      	ldr	r3, [pc, #80]	; (23dc <z_arm_init_arch_hw_at_boot+0x60>)
    238c:	f04f 32ff 	mov.w	r2, #4294967295
    2390:	f8c3 2080 	str.w	r2, [r3, #128]	; 0x80
    2394:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
    2398:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
    239c:	f8c3 208c 	str.w	r2, [r3, #140]	; 0x8c
    23a0:	f8c3 2090 	str.w	r2, [r3, #144]	; 0x90
    23a4:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
    23a8:	f8c3 2098 	str.w	r2, [r3, #152]	; 0x98
    23ac:	f8c3 209c 	str.w	r2, [r3, #156]	; 0x9c
	}
	/* Clear pending NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) {
		NVIC->ICPR[i] = 0xFFFFFFFF;
    23b0:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
    23b4:	f8c3 2184 	str.w	r2, [r3, #388]	; 0x184
    23b8:	f8c3 2188 	str.w	r2, [r3, #392]	; 0x188
    23bc:	f8c3 218c 	str.w	r2, [r3, #396]	; 0x18c
    23c0:	f8c3 2190 	str.w	r2, [r3, #400]	; 0x190
    23c4:	f8c3 2194 	str.w	r2, [r3, #404]	; 0x194
    23c8:	f8c3 2198 	str.w	r2, [r3, #408]	; 0x198
    23cc:	f8c3 219c 	str.w	r2, [r3, #412]	; 0x19c
  __ASM volatile ("cpsie i" : : : "memory");
    23d0:	b662      	cpsie	i
  __ASM volatile ("dsb 0xF":::"memory");
    23d2:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    23d6:	f3bf 8f6f 	isb	sy
	/* Restore Interrupts */
	__enable_irq();

	__DSB();
	__ISB();
}
    23da:	bd08      	pop	{r3, pc}
    23dc:	e000e100 	.word	0xe000e100

000023e0 <z_arm_configure_static_mpu_regions>:
	/* Configure the static MPU regions within firmware SRAM boundaries.
	 * Start address of the image is given by _image_ram_start. The end
	 * of the firmware SRAM area is marked by __kernel_ram_end, taking
	 * into account the unused SRAM area, as well.
	 */
	arm_core_mpu_configure_static_mpu_regions(static_regions,
    23e0:	4b02      	ldr	r3, [pc, #8]	; (23ec <z_arm_configure_static_mpu_regions+0xc>)
    23e2:	4a03      	ldr	r2, [pc, #12]	; (23f0 <z_arm_configure_static_mpu_regions+0x10>)
    23e4:	4803      	ldr	r0, [pc, #12]	; (23f4 <z_arm_configure_static_mpu_regions+0x14>)
    23e6:	2102      	movs	r1, #2
    23e8:	f000 b86c 	b.w	24c4 <arm_core_mpu_configure_static_mpu_regions>
    23ec:	20010000 	.word	0x20010000
    23f0:	20000000 	.word	0x20000000
    23f4:	0000689c 	.word	0x0000689c

000023f8 <mpu_configure_regions>:
 * sanity check of the memory regions to be programmed.
 */
static int mpu_configure_regions(const struct z_arm_mpu_partition
	regions[], uint8_t regions_num, uint8_t start_reg_index,
	bool do_sanity_check)
{
    23f8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
#endif /* CPU_CORTEX_M0PLUS | CPU_CORTEX_M3 | CPU_CORTEX_M4 */
}

static inline void set_region_number(uint32_t index)
{
	MPU->RNR = index;
    23fa:	4f24      	ldr	r7, [pc, #144]	; (248c <mpu_configure_regions+0x94>)
	int i;
	int reg_index = start_reg_index;
    23fc:	4615      	mov	r5, r2

	for (i = 0; i < regions_num; i++) {
    23fe:	2200      	movs	r2, #0
    2400:	428a      	cmp	r2, r1
    2402:	da0e      	bge.n	2422 <mpu_configure_regions+0x2a>
		if (regions[i].size == 0U) {
    2404:	6844      	ldr	r4, [r0, #4]
    2406:	2c00      	cmp	r4, #0
    2408:	d03c      	beq.n	2484 <mpu_configure_regions+0x8c>
			continue;
		}
		/* Non-empty region. */

		if (do_sanity_check &&
    240a:	b193      	cbz	r3, 2432 <mpu_configure_regions+0x3a>
	 * and greater or equal to the minimum
	 * MPU region size. Start address of the
	 * partition must align with size.
	 */
	int partition_is_valid =
		((part->size & (part->size - 1U)) == 0U)
    240c:	f104 3cff 	add.w	ip, r4, #4294967295
		&&
		(part->size >= CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)
		&&
    2410:	ea14 0f0c 	tst.w	r4, ip
    2414:	d007      	beq.n	2426 <mpu_configure_regions+0x2e>
				(!mpu_partition_is_valid(&regions[i]))) {
			LOG_ERR("Partition %u: sanity check failed.", i);
    2416:	481e      	ldr	r0, [pc, #120]	; (2490 <mpu_configure_regions+0x98>)
    2418:	2145      	movs	r1, #69	; 0x45
		LOG_ERR("Failed to allocate new MPU region %u\n", index);
    241a:	f003 fb7d 	bl	5b18 <z_log_minimal_printk>
			return -EINVAL;
		}

		reg_index = mpu_configure_region(reg_index, &regions[i]);
    241e:	f06f 0515 	mvn.w	r5, #21
		/* Increment number of programmed MPU indices. */
		reg_index++;
	}

	return reg_index;
}
    2422:	4628      	mov	r0, r5
    2424:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
		&&
    2426:	2c1f      	cmp	r4, #31
    2428:	d9f5      	bls.n	2416 <mpu_configure_regions+0x1e>
		((part->start & (part->size - 1U)) == 0U);
    242a:	6806      	ldr	r6, [r0, #0]
		&&
    242c:	ea1c 0f06 	tst.w	ip, r6
    2430:	d1f1      	bne.n	2416 <mpu_configure_regions+0x1e>
 * to that power-of-two value.
 */
static inline uint32_t size_to_mpu_rasr_size(uint32_t size)
{
	/* The minimal supported region size is 32 bytes */
	if (size <= 32U) {
    2432:	2c20      	cmp	r4, #32
	region_conf.base = new_region->start;
    2434:	6806      	ldr	r6, [r0, #0]
#if defined(CONFIG_CPU_AARCH32_CORTEX_R)
	(void) size;

	p_attr->rasr = attr->rasr_attr;
#else
	p_attr->rasr = attr->rasr_attr | size_to_mpu_rasr_size(size);
    2436:	f8d0 c008 	ldr.w	ip, [r0, #8]
		reg_index = mpu_configure_region(reg_index, &regions[i]);
    243a:	b2ed      	uxtb	r5, r5
	if (size <= 32U) {
    243c:	d910      	bls.n	2460 <mpu_configure_regions+0x68>
	if (size > (1UL << 31)) {
    243e:	f1b4 4f00 	cmp.w	r4, #2147483648	; 0x80000000
    2442:	d80f      	bhi.n	2464 <mpu_configure_regions+0x6c>
	return ((32 - __builtin_clz(size - 1U) - 2 + 1) << MPU_RASR_SIZE_Pos) &
    2444:	3c01      	subs	r4, #1
    2446:	fab4 f484 	clz	r4, r4
    244a:	f1c4 041f 	rsb	r4, r4, #31
    244e:	0064      	lsls	r4, r4, #1
	if (index > (get_num_regions() - 1U)) {
    2450:	2d07      	cmp	r5, #7
	p_attr->rasr = attr->rasr_attr | size_to_mpu_rasr_size(size);
    2452:	ea4c 0404 	orr.w	r4, ip, r4
    2456:	d907      	bls.n	2468 <mpu_configure_regions+0x70>
		LOG_ERR("Failed to allocate new MPU region %u\n", index);
    2458:	480e      	ldr	r0, [pc, #56]	; (2494 <mpu_configure_regions+0x9c>)
    245a:	462a      	mov	r2, r5
    245c:	2145      	movs	r1, #69	; 0x45
    245e:	e7dc      	b.n	241a <mpu_configure_regions+0x22>
		return REGION_32B;
    2460:	2408      	movs	r4, #8
    2462:	e7f5      	b.n	2450 <mpu_configure_regions+0x58>
		return REGION_4G;
    2464:	243e      	movs	r4, #62	; 0x3e
    2466:	e7f3      	b.n	2450 <mpu_configure_regions+0x58>
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    2468:	f026 061f 	bic.w	r6, r6, #31
				| MPU_RBAR_VALID_Msk | index;
    246c:	432e      	orrs	r6, r5
    246e:	f046 0610 	orr.w	r6, r6, #16
	MPU->RASR = region_conf->attr.rasr | MPU_RASR_ENABLE_Msk;
    2472:	f044 0401 	orr.w	r4, r4, #1
    2476:	f8c7 5098 	str.w	r5, [r7, #152]	; 0x98
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    247a:	f8c7 609c 	str.w	r6, [r7, #156]	; 0x9c
		reg_index++;
    247e:	3501      	adds	r5, #1
	MPU->RASR = region_conf->attr.rasr | MPU_RASR_ENABLE_Msk;
    2480:	f8c7 40a0 	str.w	r4, [r7, #160]	; 0xa0
	for (i = 0; i < regions_num; i++) {
    2484:	3201      	adds	r2, #1
    2486:	300c      	adds	r0, #12
    2488:	e7ba      	b.n	2400 <mpu_configure_regions+0x8>
    248a:	bf00      	nop
    248c:	e000ed00 	.word	0xe000ed00
    2490:	00007307 	.word	0x00007307
    2494:	0000732f 	.word	0x0000732f

00002498 <arm_core_mpu_enable>:
void arm_core_mpu_enable(void)
{
	/* Enable MPU and use the default memory map as a
	 * background region for privileged software access.
	 */
	MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
    2498:	4b04      	ldr	r3, [pc, #16]	; (24ac <arm_core_mpu_enable+0x14>)
    249a:	2205      	movs	r2, #5
    249c:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
  __ASM volatile ("dsb 0xF":::"memory");
    24a0:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    24a4:	f3bf 8f6f 	isb	sy

	/* Make sure that all the registers are set before proceeding */
	__DSB();
	__ISB();
}
    24a8:	4770      	bx	lr
    24aa:	bf00      	nop
    24ac:	e000ed00 	.word	0xe000ed00

000024b0 <arm_core_mpu_disable>:
  __ASM volatile ("dmb 0xF":::"memory");
    24b0:	f3bf 8f5f 	dmb	sy
{
	/* Force any outstanding transfers to complete before disabling MPU */
	__DMB();

	/* Disable MPU */
	MPU->CTRL = 0;
    24b4:	4b02      	ldr	r3, [pc, #8]	; (24c0 <arm_core_mpu_disable+0x10>)
    24b6:	2200      	movs	r2, #0
    24b8:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
}
    24bc:	4770      	bx	lr
    24be:	bf00      	nop
    24c0:	e000ed00 	.word	0xe000ed00

000024c4 <arm_core_mpu_configure_static_mpu_regions>:
 * @brief configure fixed (static) MPU regions.
 */
void arm_core_mpu_configure_static_mpu_regions(const struct z_arm_mpu_partition
	static_regions[], const uint8_t regions_num,
	const uint32_t background_area_start, const uint32_t background_area_end)
{
    24c4:	b510      	push	{r4, lr}
static int mpu_configure_static_mpu_regions(const struct z_arm_mpu_partition
	static_regions[], const uint8_t regions_num,
	const uint32_t background_area_base,
	const uint32_t background_area_end)
{
	int mpu_reg_index = static_regions_num;
    24c6:	4c03      	ldr	r4, [pc, #12]	; (24d4 <arm_core_mpu_configure_static_mpu_regions+0x10>)
	 * programmed on top of SRAM region configuration.
	 */
	ARG_UNUSED(background_area_base);
	ARG_UNUSED(background_area_end);

	mpu_reg_index = mpu_configure_regions(static_regions,
    24c8:	2301      	movs	r3, #1
    24ca:	7822      	ldrb	r2, [r4, #0]
    24cc:	f7ff ff94 	bl	23f8 <mpu_configure_regions>
		regions_num, mpu_reg_index, true);

	static_regions_num = mpu_reg_index;
    24d0:	7020      	strb	r0, [r4, #0]
					       background_area_start, background_area_end) == -EINVAL) {

		__ASSERT(0, "Configuring %u static MPU regions failed\n",
			regions_num);
	}
}
    24d2:	bd10      	pop	{r4, pc}
    24d4:	20000ffc 	.word	0x20000ffc

000024d8 <z_arm_mpu_init>:
 */
int z_arm_mpu_init(void)
{
	uint32_t r_index;

	if (mpu_config.num_regions > get_num_regions()) {
    24d8:	4914      	ldr	r1, [pc, #80]	; (252c <z_arm_mpu_init+0x54>)
    24da:	6808      	ldr	r0, [r1, #0]
    24dc:	2808      	cmp	r0, #8
{
    24de:	b510      	push	{r4, lr}
	if (mpu_config.num_regions > get_num_regions()) {
    24e0:	d821      	bhi.n	2526 <z_arm_mpu_init+0x4e>
		return -1;
	}

	LOG_DBG("total region count: %d", get_num_regions());

	arm_core_mpu_disable();
    24e2:	f7ff ffe5 	bl	24b0 <arm_core_mpu_disable>
    24e6:	4c12      	ldr	r4, [pc, #72]	; (2530 <z_arm_mpu_init+0x58>)
    24e8:	6849      	ldr	r1, [r1, #4]

	/* Architecture-specific configuration */
	mpu_init();

	/* Program fixed regions configured at SOC definition. */
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    24ea:	2200      	movs	r2, #0
    24ec:	4290      	cmp	r0, r2
    24ee:	f101 010c 	add.w	r1, r1, #12
    24f2:	d105      	bne.n	2500 <z_arm_mpu_init+0x28>
		region_init(r_index, &mpu_config.mpu_regions[r_index]);
	}

	/* Update the number of programmed MPU regions. */
	static_regions_num = mpu_config.num_regions;
    24f4:	4b0f      	ldr	r3, [pc, #60]	; (2534 <z_arm_mpu_init+0x5c>)
    24f6:	7018      	strb	r0, [r3, #0]


	arm_core_mpu_enable();
    24f8:	f7ff ffce 	bl	2498 <arm_core_mpu_enable>
		(MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos ==
		NUM_MPU_REGIONS,
		"Invalid number of MPU regions\n");
#endif /* CORTEX_M0PLUS || CPU_CORTEX_M3 || CPU_CORTEX_M4 */

	return 0;
    24fc:	2000      	movs	r0, #0
}
    24fe:	bd10      	pop	{r4, pc}
    2500:	f8c4 2098 	str.w	r2, [r4, #152]	; 0x98
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    2504:	f851 3c0c 	ldr.w	r3, [r1, #-12]
    2508:	f023 031f 	bic.w	r3, r3, #31
				| MPU_RBAR_VALID_Msk | index;
    250c:	4313      	orrs	r3, r2
    250e:	f043 0310 	orr.w	r3, r3, #16
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    2512:	f8c4 309c 	str.w	r3, [r4, #156]	; 0x9c
	MPU->RASR = region_conf->attr.rasr | MPU_RASR_ENABLE_Msk;
    2516:	f851 3c04 	ldr.w	r3, [r1, #-4]
    251a:	f043 0301 	orr.w	r3, r3, #1
    251e:	f8c4 30a0 	str.w	r3, [r4, #160]	; 0xa0
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    2522:	3201      	adds	r2, #1
    2524:	e7e2      	b.n	24ec <z_arm_mpu_init+0x14>
		return -1;
    2526:	f04f 30ff 	mov.w	r0, #4294967295
    252a:	e7e8      	b.n	24fe <z_arm_mpu_init+0x26>
    252c:	000068b4 	.word	0x000068b4
    2530:	e000ed00 	.word	0xe000ed00
    2534:	20000ffc 	.word	0x20000ffc

00002538 <__stdout_hook_install>:

static int (*_stdout_hook)(int) = _stdout_hook_default;

void __stdout_hook_install(int (*hook)(int))
{
	_stdout_hook = hook;
    2538:	4b01      	ldr	r3, [pc, #4]	; (2540 <__stdout_hook_install+0x8>)
    253a:	6018      	str	r0, [r3, #0]
}
    253c:	4770      	bx	lr
    253e:	bf00      	nop
    2540:	20000014 	.word	0x20000014

00002544 <nordicsemi_nrf52_init>:
	__asm__ volatile(
    2544:	f04f 0320 	mov.w	r3, #32
    2548:	f3ef 8211 	mrs	r2, BASEPRI
    254c:	f383 8812 	msr	BASEPRI_MAX, r3
    2550:	f3bf 8f6f 	isb	sy

	key = irq_lock();

#ifdef CONFIG_NRF_ENABLE_ICACHE
	/* Enable the instruction cache */
	NRF_NVMC->ICACHECNF = NVMC_ICACHECNF_CACHEEN_Msk;
    2554:	4906      	ldr	r1, [pc, #24]	; (2570 <nordicsemi_nrf52_init+0x2c>)
    2556:	2301      	movs	r3, #1
    2558:	f8c1 3540 	str.w	r3, [r1, #1344]	; 0x540
#endif

#if NRF_POWER_HAS_DCDCEN
NRF_STATIC_INLINE void nrf_power_dcdcen_set(NRF_POWER_Type * p_reg, bool enable)
{
    p_reg->DCDCEN = (enable ? POWER_DCDCEN_DCDCEN_Enabled : POWER_DCDCEN_DCDCEN_Disabled) <<
    255c:	f04f 4180 	mov.w	r1, #1073741824	; 0x40000000
    2560:	f8c1 3578 	str.w	r3, [r1, #1400]	; 0x578
	__asm__ volatile(
    2564:	f382 8811 	msr	BASEPRI, r2
    2568:	f3bf 8f6f 	isb	sy
	NMI_INIT();

	irq_unlock(key);

	return 0;
}
    256c:	2000      	movs	r0, #0
    256e:	4770      	bx	lr
    2570:	4001e000 	.word	0x4001e000

00002574 <sys_arch_reboot>:
    *p_gpregret = val;
    2574:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2578:	b2c0      	uxtb	r0, r0
    257a:	f8c3 051c 	str.w	r0, [r3, #1308]	; 0x51c
  __ASM volatile ("dsb 0xF":::"memory");
    257e:	f3bf 8f4f 	dsb	sy
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
  __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                       buffered write are completed before reset */
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    2582:	4905      	ldr	r1, [pc, #20]	; (2598 <sys_arch_reboot+0x24>)
    2584:	4b05      	ldr	r3, [pc, #20]	; (259c <sys_arch_reboot+0x28>)
    2586:	68ca      	ldr	r2, [r1, #12]
    2588:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    258c:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    258e:	60cb      	str	r3, [r1, #12]
    2590:	f3bf 8f4f 	dsb	sy
                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
  __DSB();                                                          /* Ensure completion of memory access */

  for(;;)                                                           /* wait until reset */
  {
    __NOP();
    2594:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    2596:	e7fd      	b.n	2594 <sys_arch_reboot+0x20>
    2598:	e000ed00 	.word	0xe000ed00
    259c:	05fa0004 	.word	0x05fa0004

000025a0 <arch_busy_wait>:

#else // NRFX_CHECK(NRFX_DELAY_DWT_BASED)

NRF_STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us)
{
    if (time_us == 0)
    25a0:	b120      	cbz	r0, 25ac <arch_busy_wait+0xc>
    };

    typedef void (* delay_func_t)(uint32_t);
    const delay_func_t delay_cycles =
        // Set LSB to 1 to execute the code in the Thumb mode.
        (delay_func_t)((((uint32_t)delay_machine_code) | 1));
    25a2:	4b03      	ldr	r3, [pc, #12]	; (25b0 <arch_busy_wait+0x10>)
    uint32_t cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ;
    delay_cycles(cycles);
    25a4:	0180      	lsls	r0, r0, #6
    25a6:	f043 0301 	orr.w	r3, r3, #1
    25aa:	4718      	bx	r3

void arch_busy_wait(uint32_t time_us)
{
	nrfx_coredep_delay_us(time_us);
}
    25ac:	4770      	bx	lr
    25ae:	bf00      	nop
    25b0:	00006670 	.word	0x00006670

000025b4 <onoff_stop>:
}

static clock_control_subsys_t get_subsys(struct onoff_manager *mgr)
{
	struct nrf_clock_control_data *data = CLOCK_DEVICE->data;
	size_t offset = (size_t)(mgr - data->mgr);
    25b4:	4b08      	ldr	r3, [pc, #32]	; (25d8 <onoff_stop+0x24>)
	return (clock_control_subsys_t)offset;
}

static void onoff_stop(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    25b6:	b570      	push	{r4, r5, r6, lr}
	size_t offset = (size_t)(mgr - data->mgr);
    25b8:	1ac3      	subs	r3, r0, r3
{
    25ba:	460d      	mov	r5, r1
	int res;

	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
    25bc:	4907      	ldr	r1, [pc, #28]	; (25dc <onoff_stop+0x28>)
	size_t offset = (size_t)(mgr - data->mgr);
    25be:	109b      	asrs	r3, r3, #2
{
    25c0:	4604      	mov	r4, r0
	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
    25c2:	4359      	muls	r1, r3
    25c4:	4806      	ldr	r0, [pc, #24]	; (25e0 <onoff_stop+0x2c>)
    25c6:	2240      	movs	r2, #64	; 0x40
    25c8:	f003 fba3 	bl	5d12 <stop>
	notify(mgr, res);
    25cc:	462b      	mov	r3, r5
	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
    25ce:	4601      	mov	r1, r0
	notify(mgr, res);
    25d0:	4620      	mov	r0, r4
}
    25d2:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	notify(mgr, res);
    25d6:	4718      	bx	r3
    25d8:	20000dcc 	.word	0x20000dcc
    25dc:	b6db6db7 	.word	0xb6db6db7
    25e0:	00006474 	.word	0x00006474

000025e4 <onoff_start>:
	notify(mgr, 0);
}

static void onoff_start(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    25e4:	b573      	push	{r0, r1, r4, r5, r6, lr}
	size_t offset = (size_t)(mgr - data->mgr);
    25e6:	4c0c      	ldr	r4, [pc, #48]	; (2618 <onoff_start+0x34>)
	int err;

	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    25e8:	4a0c      	ldr	r2, [pc, #48]	; (261c <onoff_start+0x38>)
    25ea:	2340      	movs	r3, #64	; 0x40
	size_t offset = (size_t)(mgr - data->mgr);
    25ec:	1b04      	subs	r4, r0, r4
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    25ee:	9300      	str	r3, [sp, #0]
{
    25f0:	460d      	mov	r5, r1
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    25f2:	460b      	mov	r3, r1
    25f4:	490a      	ldr	r1, [pc, #40]	; (2620 <onoff_start+0x3c>)
	size_t offset = (size_t)(mgr - data->mgr);
    25f6:	10a4      	asrs	r4, r4, #2
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    25f8:	4361      	muls	r1, r4
{
    25fa:	4606      	mov	r6, r0
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    25fc:	4809      	ldr	r0, [pc, #36]	; (2624 <onoff_start+0x40>)
    25fe:	f003 fbb5 	bl	5d6c <async_start>
			  onoff_started_callback, notify, CTX_ONOFF);
	if (err < 0) {
    2602:	1e01      	subs	r1, r0, #0
    2604:	da05      	bge.n	2612 <onoff_start+0x2e>
		notify(mgr, err);
    2606:	4630      	mov	r0, r6
    2608:	462b      	mov	r3, r5
	}
}
    260a:	b002      	add	sp, #8
    260c:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		notify(mgr, err);
    2610:	4718      	bx	r3
}
    2612:	b002      	add	sp, #8
    2614:	bd70      	pop	{r4, r5, r6, pc}
    2616:	bf00      	nop
    2618:	20000dcc 	.word	0x20000dcc
    261c:	00005de1 	.word	0x00005de1
    2620:	b6db6db7 	.word	0xb6db6db7
    2624:	00006474 	.word	0x00006474

00002628 <clk_init>:
	static const struct onoff_transitions transitions = {
		.start = onoff_start,
		.stop = onoff_stop
	};

	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    2628:	2200      	movs	r2, #0
{
    262a:	b570      	push	{r4, r5, r6, lr}
	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    262c:	2101      	movs	r1, #1
{
    262e:	4604      	mov	r4, r0
	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    2630:	4610      	mov	r0, r2
    2632:	f7ff fbdb 	bl	1dec <z_arm_irq_priority_set>
		    nrfx_isr, nrfx_power_clock_irq_handler, 0);

	nrfx_err = nrfx_clock_init(clock_event_handler);
    2636:	480f      	ldr	r0, [pc, #60]	; (2674 <clk_init+0x4c>)
    2638:	f001 fa06 	bl	3a48 <nrfx_clock_init>
	if (nrfx_err != NRFX_SUCCESS) {
    263c:	4b0e      	ldr	r3, [pc, #56]	; (2678 <clk_init+0x50>)
    263e:	4298      	cmp	r0, r3
    2640:	d115      	bne.n	266e <clk_init+0x46>
		struct nrf_clock_control_data *data = dev->data;

		z_nrf_clock_calibration_init(data->mgr);
	}

	nrfx_clock_enable();
    2642:	f003 fea4 	bl	638e <nrfx_clock_enable>
	struct nrf_clock_control_data *data = dev->data;
    2646:	6926      	ldr	r6, [r4, #16]
	for (enum clock_control_nrf_type i = 0;
		i < CLOCK_CONTROL_NRF_TYPE_COUNT; i++) {
		struct nrf_clock_control_sub_data *subdata =
						get_sub_data(dev, i);

		err = onoff_manager_init(get_onoff_manager(dev, i),
    2648:	490c      	ldr	r1, [pc, #48]	; (267c <clk_init+0x54>)
    264a:	4630      	mov	r0, r6
    264c:	f003 fa07 	bl	5a5e <onoff_manager_init>
					 &transitions);
		if (err < 0) {
    2650:	2800      	cmp	r0, #0
    2652:	db0b      	blt.n	266c <clk_init+0x44>
	struct nrf_clock_control_data *data = dev->data;
    2654:	6924      	ldr	r4, [r4, #16]
		err = onoff_manager_init(get_onoff_manager(dev, i),
    2656:	4909      	ldr	r1, [pc, #36]	; (267c <clk_init+0x54>)
			return err;
		}

		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    2658:	2501      	movs	r5, #1
    265a:	6435      	str	r5, [r6, #64]	; 0x40
		err = onoff_manager_init(get_onoff_manager(dev, i),
    265c:	f104 001c 	add.w	r0, r4, #28
    2660:	f003 f9fd 	bl	5a5e <onoff_manager_init>
		if (err < 0) {
    2664:	2800      	cmp	r0, #0
    2666:	db01      	blt.n	266c <clk_init+0x44>
		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    2668:	64e5      	str	r5, [r4, #76]	; 0x4c
	}

	return 0;
    266a:	2000      	movs	r0, #0
}
    266c:	bd70      	pop	{r4, r5, r6, pc}
		return -EIO;
    266e:	f06f 0004 	mvn.w	r0, #4
    2672:	e7fb      	b.n	266c <clk_init+0x44>
    2674:	000026b5 	.word	0x000026b5
    2678:	0bad0000 	.word	0x0bad0000
    267c:	00006904 	.word	0x00006904

00002680 <clkstarted_handle.constprop.0>:
static void clkstarted_handle(const struct device *dev,
    2680:	4601      	mov	r1, r0
	clock_control_cb_t callback = sub_data->cb;
    2682:	230c      	movs	r3, #12
    2684:	4809      	ldr	r0, [pc, #36]	; (26ac <clkstarted_handle.constprop.0+0x2c>)
    2686:	434b      	muls	r3, r1
static void clkstarted_handle(const struct device *dev,
    2688:	b570      	push	{r4, r5, r6, lr}
	clock_control_cb_t callback = sub_data->cb;
    268a:	18c4      	adds	r4, r0, r3
	void *user_data = sub_data->user_data;
    268c:	e9d4 560e 	ldrd	r5, r6, [r4, #56]	; 0x38
	sub_data->cb = NULL;
    2690:	2200      	movs	r2, #0
	set_on_state(&sub_data->flags);
    2692:	3340      	adds	r3, #64	; 0x40
	sub_data->cb = NULL;
    2694:	63a2      	str	r2, [r4, #56]	; 0x38
	set_on_state(&sub_data->flags);
    2696:	4418      	add	r0, r3
    2698:	f003 fb28 	bl	5cec <set_on_state>
	if (callback) {
    269c:	b12d      	cbz	r5, 26aa <clkstarted_handle.constprop.0+0x2a>
		callback(dev, (clock_control_subsys_t)type, user_data);
    269e:	4632      	mov	r2, r6
    26a0:	462b      	mov	r3, r5
    26a2:	4803      	ldr	r0, [pc, #12]	; (26b0 <clkstarted_handle.constprop.0+0x30>)
}
    26a4:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		callback(dev, (clock_control_subsys_t)type, user_data);
    26a8:	4718      	bx	r3
}
    26aa:	bd70      	pop	{r4, r5, r6, pc}
    26ac:	20000dcc 	.word	0x20000dcc
    26b0:	00006474 	.word	0x00006474

000026b4 <clock_event_handler>:
	switch (event) {
    26b4:	b110      	cbz	r0, 26bc <clock_event_handler+0x8>
    26b6:	2801      	cmp	r0, #1
    26b8:	d004      	beq.n	26c4 <clock_event_handler+0x10>
    26ba:	4770      	bx	lr
		if (GET_STATUS(data->flags) == CLOCK_CONTROL_STATUS_STARTING) {
    26bc:	4b03      	ldr	r3, [pc, #12]	; (26cc <clock_event_handler+0x18>)
    26be:	6c1b      	ldr	r3, [r3, #64]	; 0x40
    26c0:	075b      	lsls	r3, r3, #29
    26c2:	d101      	bne.n	26c8 <clock_event_handler+0x14>
		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_LFCLK);
    26c4:	f7ff bfdc 	b.w	2680 <clkstarted_handle.constprop.0>
}
    26c8:	4770      	bx	lr
    26ca:	bf00      	nop
    26cc:	20000dcc 	.word	0x20000dcc

000026d0 <generic_hfclk_start>:
{
    26d0:	b508      	push	{r3, lr}
	__asm__ volatile(
    26d2:	f04f 0320 	mov.w	r3, #32
    26d6:	f3ef 8111 	mrs	r1, BASEPRI
    26da:	f383 8812 	msr	BASEPRI_MAX, r3
    26de:	f3bf 8f6f 	isb	sy
	hfclk_users |= HF_USER_GENERIC;
    26e2:	4a12      	ldr	r2, [pc, #72]	; (272c <generic_hfclk_start+0x5c>)
    26e4:	6813      	ldr	r3, [r2, #0]
    26e6:	f043 0002 	orr.w	r0, r3, #2
	if (hfclk_users & HF_USER_BT) {
    26ea:	f013 0301 	ands.w	r3, r3, #1
	hfclk_users |= HF_USER_GENERIC;
    26ee:	6010      	str	r0, [r2, #0]
	if (hfclk_users & HF_USER_BT) {
    26f0:	d00c      	beq.n	270c <generic_hfclk_start+0x3c>
            break;
        case NRF_CLOCK_DOMAIN_HFCLK:
            if (p_clk_src != NULL)
            {
                (*(nrf_clock_hfclk_t *)p_clk_src) =
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    26f2:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    26f6:	f8d2 340c 	ldr.w	r3, [r2, #1036]	; 0x40c
                                        >> CLOCK_HFCLKSTAT_SRC_Pos);
            }
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    26fa:	f8d2 240c 	ldr.w	r2, [r2, #1036]	; 0x40c
		if (type == NRF_CLOCK_HFCLK_HIGH_ACCURACY) {
    26fe:	f013 0301 	ands.w	r3, r3, #1
    2702:	d003      	beq.n	270c <generic_hfclk_start+0x3c>
			set_on_state(get_hf_flags());
    2704:	480a      	ldr	r0, [pc, #40]	; (2730 <generic_hfclk_start+0x60>)
    2706:	f003 faf1 	bl	5cec <set_on_state>
			already_started = true;
    270a:	2301      	movs	r3, #1
	__asm__ volatile(
    270c:	f381 8811 	msr	BASEPRI, r1
    2710:	f3bf 8f6f 	isb	sy
	if (already_started) {
    2714:	b123      	cbz	r3, 2720 <generic_hfclk_start+0x50>
}
    2716:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
		clkstarted_handle(CLOCK_DEVICE,
    271a:	2000      	movs	r0, #0
    271c:	f7ff bfb0 	b.w	2680 <clkstarted_handle.constprop.0>
}
    2720:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_start(void)
{
    nrfx_clock_start(NRF_CLOCK_DOMAIN_HFCLK);
    2724:	2001      	movs	r0, #1
    2726:	f001 b99f 	b.w	3a68 <nrfx_clock_start>
    272a:	bf00      	nop
    272c:	20000e1c 	.word	0x20000e1c
    2730:	20000e0c 	.word	0x20000e0c

00002734 <lfclk_start>:
{
    2734:	b510      	push	{r4, lr}
	if (!once) {
    2736:	4c07      	ldr	r4, [pc, #28]	; (2754 <lfclk_start+0x20>)
    2738:	7823      	ldrb	r3, [r4, #0]
    273a:	b92b      	cbnz	r3, 2748 <lfclk_start+0x14>
		(void) arch_syscall_invoke1(parm0.x, K_SYSCALL_K_BUSY_WAIT);
		return;
	}
#endif
	compiler_barrier();
	z_impl_k_busy_wait(usec_to_wait);
    273c:	f44f 70a5 	mov.w	r0, #330	; 0x14a
    2740:	f003 fe6c 	bl	641c <z_impl_k_busy_wait>
		once = true;
    2744:	2301      	movs	r3, #1
    2746:	7023      	strb	r3, [r4, #0]
}
    2748:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    nrfx_clock_start(NRF_CLOCK_DOMAIN_LFCLK);
    274c:	2000      	movs	r0, #0
    274e:	f001 b98b 	b.w	3a68 <nrfx_clock_start>
    2752:	bf00      	nop
    2754:	20000ffd 	.word	0x20000ffd

00002758 <generic_hfclk_stop>:
 *
 * @return Previous value of @a target.
 */
static inline atomic_val_t atomic_and(atomic_t *target, atomic_val_t value)
{
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    2758:	4b09      	ldr	r3, [pc, #36]	; (2780 <generic_hfclk_stop+0x28>)
    275a:	f3bf 8f5b 	dmb	ish
    275e:	e853 2f00 	ldrex	r2, [r3]
    2762:	f022 0102 	bic.w	r1, r2, #2
    2766:	e843 1000 	strex	r0, r1, [r3]
    276a:	2800      	cmp	r0, #0
    276c:	d1f7      	bne.n	275e <generic_hfclk_stop+0x6>
    276e:	f3bf 8f5b 	dmb	ish
	if (atomic_and(&hfclk_users, ~HF_USER_GENERIC) & HF_USER_BT) {
    2772:	07d3      	lsls	r3, r2, #31
    2774:	d402      	bmi.n	277c <generic_hfclk_stop+0x24>
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_stop(void)
{
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLK);
    2776:	2001      	movs	r0, #1
    2778:	f003 be16 	b.w	63a8 <nrfx_clock_stop>
}
    277c:	4770      	bx	lr
    277e:	bf00      	nop
    2780:	20000e1c 	.word	0x20000e1c

00002784 <z_nrf_clock_control_lf_on>:
{
    2784:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
	return __atomic_exchange_n(target, value, __ATOMIC_SEQ_CST);
    2788:	4937      	ldr	r1, [pc, #220]	; (2868 <CONFIG_MAIN_STACK_SIZE+0x68>)
    278a:	f3bf 8f5b 	dmb	ish
    278e:	4607      	mov	r7, r0
    2790:	2201      	movs	r2, #1
    2792:	e851 3f00 	ldrex	r3, [r1]
    2796:	e841 2000 	strex	r0, r2, [r1]
    279a:	2800      	cmp	r0, #0
    279c:	d1f9      	bne.n	2792 <z_nrf_clock_control_lf_on+0xe>
    279e:	f3bf 8f5b 	dmb	ish
	if (atomic_set(&on, 1) == 0) {
    27a2:	b933      	cbnz	r3, 27b2 <z_nrf_clock_control_lf_on+0x2e>
 */
static inline void sys_notify_init_spinwait(struct sys_notify *notify)
{
	__ASSERT_NO_MSG(notify != NULL);

	*notify = (struct sys_notify){
    27a4:	4931      	ldr	r1, [pc, #196]	; (286c <CONFIG_MAIN_STACK_SIZE+0x6c>)
		err = onoff_request(mgr, &cli);
    27a6:	4832      	ldr	r0, [pc, #200]	; (2870 <CONFIG_MAIN_STACK_SIZE+0x70>)
    27a8:	604b      	str	r3, [r1, #4]
    27aa:	60cb      	str	r3, [r1, #12]
    27ac:	608a      	str	r2, [r1, #8]
    27ae:	f003 f969 	bl	5a84 <onoff_request>
	switch (start_mode) {
    27b2:	1e7b      	subs	r3, r7, #1
    27b4:	2b01      	cmp	r3, #1
    27b6:	d831      	bhi.n	281c <CONFIG_MAIN_STACK_SIZE+0x1c>
	if ((mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE) &&
    27b8:	2f01      	cmp	r7, #1
    27ba:	d107      	bne.n	27cc <z_nrf_clock_control_lf_on+0x48>
    return clk_src;
}

NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(NRF_CLOCK_Type const * p_reg)
{
    return (nrf_clock_lfclk_t)((p_reg->LFCLKSRCCOPY & CLOCK_LFCLKSRCCOPY_SRC_Msk)
    27bc:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    27c0:	f8d3 341c 	ldr.w	r3, [r3, #1052]	; 0x41c
    27c4:	f003 0303 	and.w	r3, r3, #3
	    (target_type == NRF_CLOCK_LFCLK_Xtal) &&
    27c8:	2b01      	cmp	r3, #1
    27ca:	d027      	beq.n	281c <CONFIG_MAIN_STACK_SIZE+0x1c>
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    27cc:	f003 fe20 	bl	6410 <k_is_in_isr>
    27d0:	4604      	mov	r4, r0
    27d2:	b918      	cbnz	r0, 27dc <z_nrf_clock_control_lf_on+0x58>
 */
static inline bool k_is_pre_kernel(void)
{
	extern bool z_sys_post_kernel; /* in init.c */

	return !z_sys_post_kernel;
    27d4:	4b27      	ldr	r3, [pc, #156]	; (2874 <CONFIG_MAIN_STACK_SIZE+0x74>)
	int key = isr_mode ? irq_lock() : 0;
    27d6:	781b      	ldrb	r3, [r3, #0]
    27d8:	2b00      	cmp	r3, #0
    27da:	d13d      	bne.n	2858 <CONFIG_MAIN_STACK_SIZE+0x58>
	__asm__ volatile(
    27dc:	f04f 0320 	mov.w	r3, #32
    27e0:	f3ef 8611 	mrs	r6, BASEPRI
    27e4:	f383 8812 	msr	BASEPRI_MAX, r3
    27e8:	f3bf 8f6f 	isb	sy
    27ec:	2401      	movs	r4, #1
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    27ee:	f8df 9088 	ldr.w	r9, [pc, #136]	; 2878 <CONFIG_MAIN_STACK_SIZE+0x78>
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    27f2:	f04f 4580 	mov.w	r5, #1073741824	; 0x40000000
    p_reg->LFCLKSRC = (uint32_t)(source);
    27f6:	f04f 0801 	mov.w	r8, #1
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    27fa:	f8d5 3418 	ldr.w	r3, [r5, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    27fe:	f8d5 2418 	ldr.w	r2, [r5, #1048]	; 0x418
    2802:	03d2      	lsls	r2, r2, #15
    2804:	d50c      	bpl.n	2820 <CONFIG_MAIN_STACK_SIZE+0x20>
                                        >> CLOCK_LFCLKSTAT_SRC_Pos);
    2806:	f003 0303 	and.w	r3, r3, #3
	while (!(nrfx_clock_is_running(d, (void *)&type)
    280a:	2b01      	cmp	r3, #1
    280c:	d001      	beq.n	2812 <CONFIG_MAIN_STACK_SIZE+0x12>
		     || (mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE)))) {
    280e:	2f01      	cmp	r7, #1
    2810:	d106      	bne.n	2820 <CONFIG_MAIN_STACK_SIZE+0x20>
	if (isr_mode) {
    2812:	b1dc      	cbz	r4, 284c <CONFIG_MAIN_STACK_SIZE+0x4c>
	__asm__ volatile(
    2814:	f386 8811 	msr	BASEPRI, r6
    2818:	f3bf 8f6f 	isb	sy
}
    281c:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
 *
 * @param key Interrupt locking key obtained from irq_lock().
 */
static inline void k_cpu_atomic_idle(unsigned int key)
{
	arch_cpu_atomic_idle(key);
    2820:	4630      	mov	r0, r6
    2822:	f7ff fa8d 	bl	1d40 <arch_cpu_atomic_idle>
    return (nrf_clock_lfclk_t)(p_reg->LFCLKSRC);
    2826:	f8d5 3518 	ldr.w	r3, [r5, #1304]	; 0x518
		if ((target_type ==  NRF_CLOCK_LFCLK_Xtal)
    282a:	2b00      	cmp	r3, #0
    282c:	d1e5      	bne.n	27fa <z_nrf_clock_control_lf_on+0x76>
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    282e:	f8d5 2104 	ldr.w	r2, [r5, #260]	; 0x104
		    && nrf_clock_event_check(NRF_CLOCK,
    2832:	2a00      	cmp	r2, #0
    2834:	d0e1      	beq.n	27fa <z_nrf_clock_control_lf_on+0x76>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2836:	f8c5 3104 	str.w	r3, [r5, #260]	; 0x104
#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE void nrf_event_readback(void * p_event_reg)
{
#if NRFX_CHECK(NRFX_EVENT_READBACK_ENABLED) && !defined(NRF51)
    (void)*((volatile uint32_t *)(p_event_reg));
    283a:	f8d5 3104 	ldr.w	r3, [r5, #260]	; 0x104
    p_reg->LFCLKSRC = (uint32_t)(source);
    283e:	f8c5 8518 	str.w	r8, [r5, #1304]	; 0x518
    2842:	f8c9 8180 	str.w	r8, [r9, #384]	; 0x180
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2846:	f8c5 8008 	str.w	r8, [r5, #8]
}
    284a:	e7d6      	b.n	27fa <z_nrf_clock_control_lf_on+0x76>
    p_reg->INTENSET = mask;
    284c:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    2850:	2202      	movs	r2, #2
    2852:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
}
    2856:	e7e1      	b.n	281c <CONFIG_MAIN_STACK_SIZE+0x1c>
    p_reg->INTENCLR = mask;
    2858:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    285c:	2202      	movs	r2, #2
    285e:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
	int key = isr_mode ? irq_lock() : 0;
    2862:	4606      	mov	r6, r0
}
    2864:	e7c3      	b.n	27ee <z_nrf_clock_control_lf_on+0x6a>
    2866:	bf00      	nop
    2868:	20000e20 	.word	0x20000e20
    286c:	20000dbc 	.word	0x20000dbc
    2870:	20000de8 	.word	0x20000de8
    2874:	2000140e 	.word	0x2000140e
    2878:	e000e100 	.word	0xe000e100

0000287c <uart_console_init>:
 * @brief Initialize one UART as the console/debug port
 *
 * @return 0 if successful, otherwise failed.
 */
static int uart_console_init(const struct device *arg)
{
    287c:	b508      	push	{r3, lr}

	ARG_UNUSED(arg);

	/* Claim console device */
	uart_console_dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_console));
    287e:	4b08      	ldr	r3, [pc, #32]	; (28a0 <uart_console_init+0x24>)
    2880:	4808      	ldr	r0, [pc, #32]	; (28a4 <uart_console_init+0x28>)
    2882:	6018      	str	r0, [r3, #0]
 */
__syscall bool device_is_ready(const struct device *dev);

static inline bool z_impl_device_is_ready(const struct device *dev)
{
	return z_device_is_ready(dev);
    2884:	f003 fdb6 	bl	63f4 <z_device_is_ready>
	if (!device_is_ready(uart_console_dev)) {
    2888:	b138      	cbz	r0, 289a <uart_console_init+0x1e>
	__stdout_hook_install(console_out);
    288a:	4807      	ldr	r0, [pc, #28]	; (28a8 <uart_console_init+0x2c>)
    288c:	f7ff fe54 	bl	2538 <__stdout_hook_install>
	__printk_hook_install(console_out);
    2890:	4805      	ldr	r0, [pc, #20]	; (28a8 <uart_console_init+0x2c>)
    2892:	f7fe fedb 	bl	164c <__printk_hook_install>
		return -ENODEV;
	}

	uart_console_hook_install();

	return 0;
    2896:	2000      	movs	r0, #0
}
    2898:	bd08      	pop	{r3, pc}
		return -ENODEV;
    289a:	f06f 0012 	mvn.w	r0, #18
    289e:	e7fb      	b.n	2898 <uart_console_init+0x1c>
    28a0:	20000e24 	.word	0x20000e24
    28a4:	000064a4 	.word	0x000064a4
    28a8:	000028ad 	.word	0x000028ad

000028ac <console_out>:
	if ('\n' == c) {
    28ac:	280a      	cmp	r0, #10
{
    28ae:	b538      	push	{r3, r4, r5, lr}
    28b0:	4d07      	ldr	r5, [pc, #28]	; (28d0 <console_out+0x24>)
    28b2:	4604      	mov	r4, r0
	if ('\n' == c) {
    28b4:	d104      	bne.n	28c0 <console_out+0x14>
		uart_poll_out(uart_console_dev, '\r');
    28b6:	6828      	ldr	r0, [r5, #0]
					unsigned char out_char)
{
	const struct uart_driver_api *api =
		(const struct uart_driver_api *)dev->api;

	api->poll_out(dev, out_char);
    28b8:	6883      	ldr	r3, [r0, #8]
    28ba:	210d      	movs	r1, #13
    28bc:	685b      	ldr	r3, [r3, #4]
    28be:	4798      	blx	r3
	uart_poll_out(uart_console_dev, c);
    28c0:	6828      	ldr	r0, [r5, #0]
    28c2:	6883      	ldr	r3, [r0, #8]
    28c4:	b2e1      	uxtb	r1, r4
    28c6:	685b      	ldr	r3, [r3, #4]
    28c8:	4798      	blx	r3
}
    28ca:	4620      	mov	r0, r4
    28cc:	bd38      	pop	{r3, r4, r5, pc}
    28ce:	bf00      	nop
    28d0:	20000e24 	.word	0x20000e24

000028d4 <gpio_nrfx_pin_interrupt_configure>:

static int gpio_nrfx_pin_interrupt_configure(const struct device *port,
					     gpio_pin_t pin,
					     enum gpio_int_mode mode,
					     enum gpio_int_trig trig)
{
    28d4:	b530      	push	{r4, r5, lr}
	return port->config;
    28d6:	6840      	ldr	r0, [r0, #4]
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
    28d8:	7b04      	ldrb	r4, [r0, #12]
    28da:	f001 051f 	and.w	r5, r1, #31
	nrfx_err_t err;

	if (mode == GPIO_INT_MODE_DISABLED) {
    28de:	f5b2 1f00 	cmp.w	r2, #2097152	; 0x200000
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
    28e2:	ea45 1544 	orr.w	r5, r5, r4, lsl #5
{
    28e6:	b085      	sub	sp, #20
    28e8:	f04f 0400 	mov.w	r4, #0
	if (mode == GPIO_INT_MODE_DISABLED) {
    28ec:	d104      	bne.n	28f8 <gpio_nrfx_pin_interrupt_configure+0x24>
		nrfx_gpiote_trigger_disable(abs_pin);
    28ee:	4628      	mov	r0, r5
    28f0:	f001 fb74 	bl	3fdc <nrfx_gpiote_trigger_disable>
		return -EIO;
	}

	nrfx_gpiote_trigger_enable(abs_pin, true);

	return 0;
    28f4:	2000      	movs	r0, #0
    28f6:	e02e      	b.n	2956 <gpio_nrfx_pin_interrupt_configure+0x82>
	if (mode == GPIO_INT_MODE_LEVEL) {
    28f8:	f5b2 0f80 	cmp.w	r2, #4194304	; 0x400000
	nrfx_gpiote_trigger_config_t trigger_config = {
    28fc:	e9cd 4402 	strd	r4, r4, [sp, #8]
	if (mode == GPIO_INT_MODE_LEVEL) {
    2900:	d12b      	bne.n	295a <gpio_nrfx_pin_interrupt_configure+0x86>
		return trig == GPIO_INT_TRIG_LOW ? NRFX_GPIOTE_TRIGGER_LOW :
    2902:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
    2906:	bf0c      	ite	eq
    2908:	2304      	moveq	r3, #4
    290a:	2305      	movne	r3, #5
	nrfx_gpiote_trigger_config_t trigger_config = {
    290c:	f88d 3008 	strb.w	r3, [sp, #8]
	if (!(BIT(pin) & get_port_cfg(port)->edge_sense) &&
    2910:	6883      	ldr	r3, [r0, #8]
    2912:	fa23 f101 	lsr.w	r1, r3, r1
    2916:	07c9      	lsls	r1, r1, #31
    2918:	d42b      	bmi.n	2972 <gpio_nrfx_pin_interrupt_configure+0x9e>
    291a:	f1b2 7fa0 	cmp.w	r2, #20971520	; 0x1400000
    291e:	d128      	bne.n	2972 <gpio_nrfx_pin_interrupt_configure+0x9e>
}

NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin)
{
    uint32_t pin_number = *p_pin;
    *p_pin = pin_number & 0x1F;
    2920:	f005 031f 	and.w	r3, r5, #31
    return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
    2924:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    2928:	f04f 42a0 	mov.w	r2, #1342177280	; 0x50000000
    292c:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
	    (mode == GPIO_INT_MODE_EDGE) &&
    2930:	07db      	lsls	r3, r3, #31
    2932:	d41e      	bmi.n	2972 <gpio_nrfx_pin_interrupt_configure+0x9e>
		err = nrfx_gpiote_channel_get(abs_pin, &ch);
    2934:	f10d 0407 	add.w	r4, sp, #7
    2938:	4621      	mov	r1, r4
    293a:	4628      	mov	r0, r5
    293c:	f001 fab6 	bl	3eac <nrfx_gpiote_channel_get>
		if (err == NRFX_ERROR_INVALID_PARAM) {
    2940:	4b14      	ldr	r3, [pc, #80]	; (2994 <gpio_nrfx_pin_interrupt_configure+0xc0>)
    2942:	4298      	cmp	r0, r3
    2944:	d114      	bne.n	2970 <gpio_nrfx_pin_interrupt_configure+0x9c>
			err = nrfx_gpiote_channel_alloc(&ch);
    2946:	4620      	mov	r0, r4
    2948:	f001 fafe 	bl	3f48 <nrfx_gpiote_channel_alloc>
			if (err != NRFX_SUCCESS) {
    294c:	4b12      	ldr	r3, [pc, #72]	; (2998 <gpio_nrfx_pin_interrupt_configure+0xc4>)
    294e:	4298      	cmp	r0, r3
    2950:	d00e      	beq.n	2970 <gpio_nrfx_pin_interrupt_configure+0x9c>
				return -ENOMEM;
    2952:	f06f 000b 	mvn.w	r0, #11
}
    2956:	b005      	add	sp, #20
    2958:	bd30      	pop	{r4, r5, pc}
	return trig == GPIO_INT_TRIG_BOTH ? NRFX_GPIOTE_TRIGGER_TOGGLE :
    295a:	f1b3 6fc0 	cmp.w	r3, #100663296	; 0x6000000
    295e:	d005      	beq.n	296c <gpio_nrfx_pin_interrupt_configure+0x98>
    2960:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
    2964:	bf0c      	ite	eq
    2966:	2302      	moveq	r3, #2
    2968:	2301      	movne	r3, #1
    296a:	e7cf      	b.n	290c <gpio_nrfx_pin_interrupt_configure+0x38>
    296c:	2303      	movs	r3, #3
    296e:	e7cd      	b.n	290c <gpio_nrfx_pin_interrupt_configure+0x38>
		trigger_config.p_in_channel = &ch;
    2970:	9403      	str	r4, [sp, #12]
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    2972:	2300      	movs	r3, #0
    2974:	4619      	mov	r1, r3
    2976:	aa02      	add	r2, sp, #8
    2978:	4628      	mov	r0, r5
    297a:	f001 f96f 	bl	3c5c <nrfx_gpiote_input_configure>
	if (err != NRFX_SUCCESS) {
    297e:	4b06      	ldr	r3, [pc, #24]	; (2998 <gpio_nrfx_pin_interrupt_configure+0xc4>)
    2980:	4298      	cmp	r0, r3
    2982:	d104      	bne.n	298e <gpio_nrfx_pin_interrupt_configure+0xba>
	nrfx_gpiote_trigger_enable(abs_pin, true);
    2984:	2101      	movs	r1, #1
    2986:	4628      	mov	r0, r5
    2988:	f001 fae4 	bl	3f54 <nrfx_gpiote_trigger_enable>
    298c:	e7b2      	b.n	28f4 <gpio_nrfx_pin_interrupt_configure+0x20>
		return -EIO;
    298e:	f06f 0004 	mvn.w	r0, #4
    2992:	e7e0      	b.n	2956 <gpio_nrfx_pin_interrupt_configure+0x82>
    2994:	0bad0004 	.word	0x0bad0004
    2998:	0bad0000 	.word	0x0bad0000

0000299c <gpio_nrfx_init>:
}

#define GPIOTE_NODE DT_INST(0, nordic_nrf_gpiote)

static int gpio_nrfx_init(const struct device *port)
{
    299c:	b510      	push	{r4, lr}
	nrfx_err_t err;

	if (nrfx_gpiote_is_init()) {
    299e:	f001 fac3 	bl	3f28 <nrfx_gpiote_is_init>
    29a2:	4604      	mov	r4, r0
    29a4:	b968      	cbnz	r0, 29c2 <gpio_nrfx_init+0x26>
		return 0;
	}

	err = nrfx_gpiote_init(0/*not used*/);
    29a6:	f001 fa97 	bl	3ed8 <nrfx_gpiote_init>
	if (err != NRFX_SUCCESS) {
    29aa:	4b08      	ldr	r3, [pc, #32]	; (29cc <gpio_nrfx_init+0x30>)
    29ac:	4298      	cmp	r0, r3
    29ae:	d10a      	bne.n	29c6 <gpio_nrfx_init+0x2a>
		return -EIO;
	}

	nrfx_gpiote_global_callback_set(nrfx_gpio_handler, NULL);
    29b0:	4807      	ldr	r0, [pc, #28]	; (29d0 <gpio_nrfx_init+0x34>)
    29b2:	4621      	mov	r1, r4
    29b4:	f001 fa74 	bl	3ea0 <nrfx_gpiote_global_callback_set>

	IRQ_CONNECT(DT_IRQN(GPIOTE_NODE), DT_IRQ(GPIOTE_NODE, priority),
    29b8:	4622      	mov	r2, r4
    29ba:	2105      	movs	r1, #5
    29bc:	2006      	movs	r0, #6
    29be:	f7ff fa15 	bl	1dec <z_arm_irq_priority_set>
		return 0;
    29c2:	2000      	movs	r0, #0
		    nrfx_isr, nrfx_gpiote_irq_handler, 0);

	return 0;
}
    29c4:	bd10      	pop	{r4, pc}
		return -EIO;
    29c6:	f06f 0004 	mvn.w	r0, #4
    29ca:	e7fb      	b.n	29c4 <gpio_nrfx_init+0x28>
    29cc:	0bad0000 	.word	0x0bad0000
    29d0:	000029d5 	.word	0x000029d5

000029d4 <nrfx_gpio_handler>:
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    29d4:	0943      	lsrs	r3, r0, #5
{
    29d6:	b570      	push	{r4, r5, r6, lr}
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    29d8:	d110      	bne.n	29fc <nrfx_gpio_handler+0x28>
	return list->head;
    29da:	4b09      	ldr	r3, [pc, #36]	; (2a00 <nrfx_gpio_handler+0x2c>)
    29dc:	6859      	ldr	r1, [r3, #4]
					const struct device *port,
					uint32_t pins)
{
	struct gpio_callback *cb, *tmp;

	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    29de:	b169      	cbz	r1, 29fc <nrfx_gpio_handler+0x28>
	gpio_fire_callbacks(list, port, BIT(pin));
    29e0:	2501      	movs	r5, #1
	return node->next;
    29e2:	680c      	ldr	r4, [r1, #0]
		if (cb->pin_mask & pins) {
			__ASSERT(cb->handler, "No callback handler!");
			cb->handler(port, cb, cb->pin_mask & pins);
    29e4:	4e07      	ldr	r6, [pc, #28]	; (2a04 <nrfx_gpio_handler+0x30>)
    29e6:	4085      	lsls	r5, r0
		if (cb->pin_mask & pins) {
    29e8:	688a      	ldr	r2, [r1, #8]
    29ea:	402a      	ands	r2, r5
    29ec:	d002      	beq.n	29f4 <nrfx_gpio_handler+0x20>
			cb->handler(port, cb, cb->pin_mask & pins);
    29ee:	684b      	ldr	r3, [r1, #4]
    29f0:	4630      	mov	r0, r6
    29f2:	4798      	blx	r3
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    29f4:	b114      	cbz	r4, 29fc <nrfx_gpio_handler+0x28>
    29f6:	4621      	mov	r1, r4
    29f8:	6824      	ldr	r4, [r4, #0]
    29fa:	e7f5      	b.n	29e8 <nrfx_gpio_handler+0x14>
}
    29fc:	bd70      	pop	{r4, r5, r6, pc}
    29fe:	bf00      	nop
    2a00:	20000e28 	.word	0x20000e28
    2a04:	0000648c 	.word	0x0000648c

00002a08 <gpio_nrfx_pin_configure>:
{
    2a08:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
	return port->config;
    2a0c:	6847      	ldr	r7, [r0, #4]
	nrfx_gpiote_pin_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    2a0e:	7b3b      	ldrb	r3, [r7, #12]
    2a10:	f001 051f 	and.w	r5, r1, #31
{
    2a14:	b085      	sub	sp, #20
    2a16:	460e      	mov	r6, r1
	nrfx_gpiote_pin_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    2a18:	ea45 1543 	orr.w	r5, r5, r3, lsl #5
	if (flags == GPIO_DISCONNECTED) {
    2a1c:	4614      	mov	r4, r2
    2a1e:	b9ca      	cbnz	r2, 2a54 <gpio_nrfx_pin_configure+0x4c>
	err = nrfx_gpiote_channel_get(pin, &ch);
    2a20:	a902      	add	r1, sp, #8
    2a22:	4628      	mov	r0, r5
    2a24:	f001 fa42 	bl	3eac <nrfx_gpiote_channel_get>
    2a28:	4604      	mov	r4, r0
	err = nrfx_gpiote_pin_uninit(pin);
    2a2a:	4628      	mov	r0, r5
    2a2c:	f001 fafe 	bl	402c <nrfx_gpiote_pin_uninit>
	if (err != NRFX_SUCCESS) {
    2a30:	4b4a      	ldr	r3, [pc, #296]	; (2b5c <gpio_nrfx_pin_configure+0x154>)
    2a32:	4298      	cmp	r0, r3
    2a34:	d004      	beq.n	2a40 <gpio_nrfx_pin_configure+0x38>
		return -EIO;
    2a36:	f06f 0004 	mvn.w	r0, #4
}
    2a3a:	b005      	add	sp, #20
    2a3c:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
	if (free_ch) {
    2a40:	4284      	cmp	r4, r0
    2a42:	d105      	bne.n	2a50 <gpio_nrfx_pin_configure+0x48>
		err = nrfx_gpiote_channel_free(ch);
    2a44:	f89d 0008 	ldrb.w	r0, [sp, #8]
    2a48:	f001 fa78 	bl	3f3c <nrfx_gpiote_channel_free>
	return (err != NRFX_SUCCESS) ? -EIO : 0;
    2a4c:	42a0      	cmp	r0, r4
    2a4e:	d1f2      	bne.n	2a36 <gpio_nrfx_pin_configure+0x2e>
	return (err != NRFX_SUCCESS) ? -EINVAL : 0;
    2a50:	2000      	movs	r0, #0
    2a52:	e7f2      	b.n	2a3a <gpio_nrfx_pin_configure+0x32>
	nrfx_gpiote_trigger_config_t trigger_config = {
    2a54:	f04f 0900 	mov.w	r9, #0
	err = nrfx_gpiote_channel_get(pin, &ch);
    2a58:	f10d 0103 	add.w	r1, sp, #3
    2a5c:	4630      	mov	r0, r6
	nrfx_gpiote_trigger_config_t trigger_config = {
    2a5e:	e9cd 9902 	strd	r9, r9, [sp, #8]
	err = nrfx_gpiote_channel_get(pin, &ch);
    2a62:	f001 fa23 	bl	3eac <nrfx_gpiote_channel_get>
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    2a66:	464b      	mov	r3, r9
	err = nrfx_gpiote_channel_get(pin, &ch);
    2a68:	4680      	mov	r8, r0
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    2a6a:	aa02      	add	r2, sp, #8
    2a6c:	4649      	mov	r1, r9
    2a6e:	4628      	mov	r0, r5
    2a70:	f001 f8f4 	bl	3c5c <nrfx_gpiote_input_configure>
	if (err != NRFX_SUCCESS) {
    2a74:	4b39      	ldr	r3, [pc, #228]	; (2b5c <gpio_nrfx_pin_configure+0x154>)
    2a76:	4298      	cmp	r0, r3
    2a78:	d002      	beq.n	2a80 <gpio_nrfx_pin_configure+0x78>
	switch (flags & (NRF_GPIO_DS_LOW_MASK | NRF_GPIO_DS_HIGH_MASK |
    2a7a:	f06f 0015 	mvn.w	r0, #21
    2a7e:	e7dc      	b.n	2a3a <gpio_nrfx_pin_configure+0x32>
	if (free_ch) {
    2a80:	4580      	cmp	r8, r0
    2a82:	d103      	bne.n	2a8c <gpio_nrfx_pin_configure+0x84>
		err = nrfx_gpiote_channel_free(ch);
    2a84:	f89d 0003 	ldrb.w	r0, [sp, #3]
    2a88:	f001 fa58 	bl	3f3c <nrfx_gpiote_channel_free>
	if (flags & GPIO_OUTPUT) {
    2a8c:	03a3      	lsls	r3, r4, #14
    2a8e:	d551      	bpl.n	2b34 <gpio_nrfx_pin_configure+0x12c>
	switch (flags & (NRF_GPIO_DS_LOW_MASK | NRF_GPIO_DS_HIGH_MASK |
    2a90:	f240 6306 	movw	r3, #1542	; 0x606
    2a94:	4023      	ands	r3, r4
    2a96:	f240 2206 	movw	r2, #518	; 0x206
    2a9a:	4293      	cmp	r3, r2
    2a9c:	d03b      	beq.n	2b16 <gpio_nrfx_pin_configure+0x10e>
    2a9e:	d80c      	bhi.n	2aba <gpio_nrfx_pin_configure+0xb2>
    2aa0:	2b06      	cmp	r3, #6
    2aa2:	d015      	beq.n	2ad0 <gpio_nrfx_pin_configure+0xc8>
    2aa4:	d804      	bhi.n	2ab0 <gpio_nrfx_pin_configure+0xa8>
    2aa6:	b19b      	cbz	r3, 2ad0 <gpio_nrfx_pin_configure+0xc8>
    2aa8:	2b02      	cmp	r3, #2
    2aaa:	d1e6      	bne.n	2a7a <gpio_nrfx_pin_configure+0x72>
    2aac:	2304      	movs	r3, #4
    2aae:	e00f      	b.n	2ad0 <gpio_nrfx_pin_configure+0xc8>
    2ab0:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
    2ab4:	d1e1      	bne.n	2a7a <gpio_nrfx_pin_configure+0x72>
		*drive = NRF_GPIO_PIN_H0S1;
    2ab6:	2301      	movs	r3, #1
    2ab8:	e00a      	b.n	2ad0 <gpio_nrfx_pin_configure+0xc8>
	switch (flags & (NRF_GPIO_DS_LOW_MASK | NRF_GPIO_DS_HIGH_MASK |
    2aba:	f240 4202 	movw	r2, #1026	; 0x402
    2abe:	4293      	cmp	r3, r2
    2ac0:	d02b      	beq.n	2b1a <gpio_nrfx_pin_configure+0x112>
    2ac2:	f5b3 6fc0 	cmp.w	r3, #1536	; 0x600
    2ac6:	d02a      	beq.n	2b1e <gpio_nrfx_pin_configure+0x116>
    2ac8:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
    2acc:	d1d5      	bne.n	2a7a <gpio_nrfx_pin_configure+0x72>
		*drive = NRF_GPIO_PIN_S0H1;
    2ace:	2302      	movs	r3, #2
		nrfx_gpiote_output_config_t output_config = {
    2ad0:	f88d 3004 	strb.w	r3, [sp, #4]
				NRF_GPIO_PIN_INPUT_CONNECT :
    2ad4:	f484 3380 	eor.w	r3, r4, #65536	; 0x10000
    2ad8:	f3c3 4300 	ubfx	r3, r3, #16, #1
	if (flags & GPIO_PULL_UP) {
    2adc:	06e0      	lsls	r0, r4, #27
		nrfx_gpiote_output_config_t output_config = {
    2ade:	f88d 3005 	strb.w	r3, [sp, #5]
		return NRF_GPIO_PIN_PULLDOWN;
    2ae2:	bf54      	ite	pl
    2ae4:	f3c4 1340 	ubfxpl	r3, r4, #5, #1
		return NRF_GPIO_PIN_PULLUP;
    2ae8:	2303      	movmi	r3, #3
		if (flags & GPIO_OUTPUT_INIT_HIGH) {
    2aea:	0321      	lsls	r1, r4, #12
		nrfx_gpiote_output_config_t output_config = {
    2aec:	f88d 3006 	strb.w	r3, [sp, #6]
		if (flags & GPIO_OUTPUT_INIT_HIGH) {
    2af0:	d517      	bpl.n	2b22 <gpio_nrfx_pin_configure+0x11a>
			nrf_gpio_port_out_set(cfg->port, BIT(pin));
    2af2:	687b      	ldr	r3, [r7, #4]
    2af4:	2101      	movs	r1, #1
    2af6:	fa01 f606 	lsl.w	r6, r1, r6
    p_reg->OUTSET = set_mask;
    2afa:	f8c3 6508 	str.w	r6, [r3, #1288]	; 0x508
		err = nrfx_gpiote_output_configure(abs_pin, &output_config, NULL);
    2afe:	2200      	movs	r2, #0
    2b00:	a901      	add	r1, sp, #4
    2b02:	4628      	mov	r0, r5
    2b04:	f001 f954 	bl	3db0 <nrfx_gpiote_output_configure>
		return (err != NRFX_SUCCESS) ? -EINVAL : 0;
    2b08:	4b14      	ldr	r3, [pc, #80]	; (2b5c <gpio_nrfx_pin_configure+0x154>)
    2b0a:	4298      	cmp	r0, r3
    2b0c:	bf14      	ite	ne
    2b0e:	f06f 0015 	mvnne.w	r0, #21
    2b12:	2000      	moveq	r0, #0
    2b14:	e791      	b.n	2a3a <gpio_nrfx_pin_configure+0x32>
		*drive = NRF_GPIO_PIN_H0D1;
    2b16:	2307      	movs	r3, #7
    2b18:	e7da      	b.n	2ad0 <gpio_nrfx_pin_configure+0xc8>
		*drive = NRF_GPIO_PIN_D0H1;
    2b1a:	2305      	movs	r3, #5
    2b1c:	e7d8      	b.n	2ad0 <gpio_nrfx_pin_configure+0xc8>
		*drive = NRF_GPIO_PIN_H0H1;
    2b1e:	2303      	movs	r3, #3
    2b20:	e7d6      	b.n	2ad0 <gpio_nrfx_pin_configure+0xc8>
		} else if (flags & GPIO_OUTPUT_INIT_LOW) {
    2b22:	0362      	lsls	r2, r4, #13
			nrf_gpio_port_out_clear(cfg->port, BIT(pin));
    2b24:	bf41      	itttt	mi
    2b26:	687b      	ldrmi	r3, [r7, #4]
    2b28:	2101      	movmi	r1, #1
    2b2a:	fa01 f606 	lslmi.w	r6, r1, r6
    p_reg->OUTCLR = clr_mask;
    2b2e:	f8c3 650c 	strmi.w	r6, [r3, #1292]	; 0x50c
}
    2b32:	e7e4      	b.n	2afe <gpio_nrfx_pin_configure+0xf6>
	if (flags & GPIO_PULL_UP) {
    2b34:	06e3      	lsls	r3, r4, #27
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    2b36:	f04f 0300 	mov.w	r3, #0
		return NRF_GPIO_PIN_PULLUP;
    2b3a:	bf54      	ite	pl
    2b3c:	f3c4 1440 	ubfxpl	r4, r4, #5, #1
    2b40:	2403      	movmi	r4, #3
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    2b42:	461a      	mov	r2, r3
    2b44:	a901      	add	r1, sp, #4
    2b46:	4628      	mov	r0, r5
	nrfx_gpiote_input_config_t input_config = {
    2b48:	f88d 4004 	strb.w	r4, [sp, #4]
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    2b4c:	f001 f886 	bl	3c5c <nrfx_gpiote_input_configure>
	return (err != NRFX_SUCCESS) ? -EINVAL : 0;
    2b50:	4b02      	ldr	r3, [pc, #8]	; (2b5c <gpio_nrfx_pin_configure+0x154>)
    2b52:	4298      	cmp	r0, r3
    2b54:	f43f af7c 	beq.w	2a50 <gpio_nrfx_pin_configure+0x48>
    2b58:	e78f      	b.n	2a7a <gpio_nrfx_pin_configure+0x72>
    2b5a:	bf00      	nop
    2b5c:	0bad0000 	.word	0x0bad0000

00002b60 <flash_nrf_pages_layout>:

static void flash_nrf_pages_layout(const struct device *dev,
				     const struct flash_pages_layout **layout,
				     size_t *layout_size)
{
	*layout = &dev_layout;
    2b60:	4b02      	ldr	r3, [pc, #8]	; (2b6c <flash_nrf_pages_layout+0xc>)
    2b62:	600b      	str	r3, [r1, #0]
	*layout_size = 1;
    2b64:	2301      	movs	r3, #1
    2b66:	6013      	str	r3, [r2, #0]
}
    2b68:	4770      	bx	lr
    2b6a:	bf00      	nop
    2b6c:	20000e34 	.word	0x20000e34

00002b70 <flash_nrf_get_parameters>:
flash_nrf_get_parameters(const struct device *dev)
{
	ARG_UNUSED(dev);

	return &flash_nrf_parameters;
}
    2b70:	4800      	ldr	r0, [pc, #0]	; (2b74 <flash_nrf_get_parameters+0x4>)
    2b72:	4770      	bx	lr
    2b74:	00006958 	.word	0x00006958

00002b78 <nrf_flash_init>:
	.page_layout = flash_nrf_pages_layout,
#endif
};

static int nrf_flash_init(const struct device *dev)
{
    2b78:	b510      	push	{r4, lr}
#ifndef CONFIG_SOC_FLASH_NRF_RADIO_SYNC_NONE
	nrf_flash_sync_init();
#endif /* !CONFIG_SOC_FLASH_NRF_RADIO_SYNC_NONE */

#if defined(CONFIG_FLASH_PAGE_LAYOUT)
	dev_layout.pages_count = nrfx_nvmc_flash_page_count_get();
    2b7a:	f003 fc2f 	bl	63dc <nrfx_nvmc_flash_page_count_get>
    2b7e:	4c03      	ldr	r4, [pc, #12]	; (2b8c <nrf_flash_init+0x14>)
    2b80:	6020      	str	r0, [r4, #0]
	dev_layout.pages_size = nrfx_nvmc_flash_page_size_get();
    2b82:	f003 fc27 	bl	63d4 <nrfx_nvmc_flash_page_size_get>
    2b86:	6060      	str	r0, [r4, #4]
#endif

	return 0;
}
    2b88:	2000      	movs	r0, #0
    2b8a:	bd10      	pop	{r4, pc}
    2b8c:	20000e34 	.word	0x20000e34

00002b90 <flash_nrf_erase>:
{
    2b90:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    2b92:	460e      	mov	r6, r1
    2b94:	4614      	mov	r4, r2
	uint32_t pg_size = nrfx_nvmc_flash_page_size_get();
    2b96:	f003 fc1d 	bl	63d4 <nrfx_nvmc_flash_page_size_get>
	if (is_regular_addr_valid(addr, size)) {
    2b9a:	4621      	mov	r1, r4
	uint32_t pg_size = nrfx_nvmc_flash_page_size_get();
    2b9c:	4605      	mov	r5, r0
	if (is_regular_addr_valid(addr, size)) {
    2b9e:	4630      	mov	r0, r6
    2ba0:	f003 f97b 	bl	5e9a <is_regular_addr_valid>
		if (((addr % pg_size) != 0) || ((size % pg_size) != 0)) {
    2ba4:	4637      	mov	r7, r6
	if (is_regular_addr_valid(addr, size)) {
    2ba6:	b1f8      	cbz	r0, 2be8 <flash_nrf_erase+0x58>
		if (((addr % pg_size) != 0) || ((size % pg_size) != 0)) {
    2ba8:	fbb6 f3f5 	udiv	r3, r6, r5
    2bac:	fb05 6313 	mls	r3, r5, r3, r6
    2bb0:	b923      	cbnz	r3, 2bbc <flash_nrf_erase+0x2c>
    2bb2:	fbb4 f0f5 	udiv	r0, r4, r5
    2bb6:	fb05 4010 	mls	r0, r5, r0, r4
    2bba:	b140      	cbz	r0, 2bce <flash_nrf_erase+0x3e>
			LOG_ERR("unaligned address: 0x%08lx:%zu",
    2bbc:	480d      	ldr	r0, [pc, #52]	; (2bf4 <flash_nrf_erase+0x64>)
    2bbe:	4623      	mov	r3, r4
    2bc0:	4632      	mov	r2, r6
    2bc2:	2145      	movs	r1, #69	; 0x45
		LOG_ERR("invalid address: 0x%08lx:%zu",
    2bc4:	f002 ffa8 	bl	5b18 <z_log_minimal_printk>
		return -EINVAL;
    2bc8:	f06f 0015 	mvn.w	r0, #21
    2bcc:	e00b      	b.n	2be6 <flash_nrf_erase+0x56>
		if (!n_pages) {
    2bce:	42a5      	cmp	r5, r4
    2bd0:	d809      	bhi.n	2be6 <flash_nrf_erase+0x56>

#endif /* !CONFIG_SOC_FLASH_NRF_RADIO_SYNC_NONE */

static int erase_op(void *context)
{
	uint32_t pg_size = nrfx_nvmc_flash_page_size_get();
    2bd2:	f003 fbff 	bl	63d4 <nrfx_nvmc_flash_page_size_get>
    2bd6:	4605      	mov	r5, r0
		if (nrfx_nvmc_page_partial_erase_continue()) {
			e_ctx->len -= pg_size;
			e_ctx->flash_addr += pg_size;
		}
#else
		(void)nrfx_nvmc_page_erase(e_ctx->flash_addr);
    2bd8:	4638      	mov	r0, r7
    2bda:	f001 fafd 	bl	41d8 <nrfx_nvmc_page_erase>
			}

		}
#endif /* !CONFIG_SOC_FLASH_NRF_RADIO_SYNC_NONE */

	} while (e_ctx->len > 0);
    2bde:	1b64      	subs	r4, r4, r5
    2be0:	442f      	add	r7, r5
    2be2:	d1f9      	bne.n	2bd8 <flash_nrf_erase+0x48>
	return ret;
    2be4:	4620      	mov	r0, r4
}
    2be6:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
		LOG_ERR("invalid address: 0x%08lx:%zu",
    2be8:	4803      	ldr	r0, [pc, #12]	; (2bf8 <flash_nrf_erase+0x68>)
    2bea:	4623      	mov	r3, r4
    2bec:	4632      	mov	r2, r6
    2bee:	2145      	movs	r1, #69	; 0x45
    2bf0:	e7e8      	b.n	2bc4 <flash_nrf_erase+0x34>
    2bf2:	bf00      	nop
    2bf4:	00007394 	.word	0x00007394
    2bf8:	000073b8 	.word	0x000073b8

00002bfc <flash_nrf_write>:
{
    2bfc:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    2bfe:	460e      	mov	r6, r1
	if (is_regular_addr_valid(addr, len)) {
    2c00:	4630      	mov	r0, r6
    2c02:	4619      	mov	r1, r3
{
    2c04:	4617      	mov	r7, r2
    2c06:	461c      	mov	r4, r3
	if (is_regular_addr_valid(addr, len)) {
    2c08:	f003 f947 	bl	5e9a <is_regular_addr_valid>
    2c0c:	b940      	cbnz	r0, 2c20 <flash_nrf_write+0x24>
		LOG_ERR("invalid address: 0x%08lx:%zu",
    2c0e:	4814      	ldr	r0, [pc, #80]	; (2c60 <flash_nrf_write+0x64>)
    2c10:	4623      	mov	r3, r4
    2c12:	4632      	mov	r2, r6
    2c14:	2145      	movs	r1, #69	; 0x45
		LOG_ERR("not word-aligned: 0x%08lx:%zu",
    2c16:	f002 ff7f 	bl	5b18 <z_log_minimal_printk>
		return -EINVAL;
    2c1a:	f06f 0015 	mvn.w	r0, #21
}
    2c1e:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	return (data & 0x3) ? false : true;
    2c20:	ea44 0506 	orr.w	r5, r4, r6
	if (!is_aligned_32(addr) || (len % sizeof(uint32_t))) {
    2c24:	f015 0503 	ands.w	r5, r5, #3
    2c28:	d004      	beq.n	2c34 <flash_nrf_write+0x38>
		LOG_ERR("not word-aligned: 0x%08lx:%zu",
    2c2a:	480e      	ldr	r0, [pc, #56]	; (2c64 <flash_nrf_write+0x68>)
    2c2c:	4623      	mov	r3, r4
    2c2e:	4632      	mov	r2, r6
    2c30:	2145      	movs	r1, #69	; 0x45
    2c32:	e7f0      	b.n	2c16 <flash_nrf_write+0x1a>
	if (!len) {
    2c34:	b18c      	cbz	r4, 2c5a <flash_nrf_write+0x5e>
		}
#endif /* !CONFIG_SOC_FLASH_NRF_RADIO_SYNC_NONE */
	}
#endif /* CONFIG_SOC_FLASH_NRF_EMULATE_ONE_BYTE_WRITE_ACCESS */
	/* Write all the 4-byte aligned data */
	while (w_ctx->len >= sizeof(uint32_t)) {
    2c36:	f024 0403 	bic.w	r4, r4, #3
    2c3a:	42ac      	cmp	r4, r5
    2c3c:	eb05 0006 	add.w	r0, r5, r6
    2c40:	d106      	bne.n	2c50 <flash_nrf_write+0x54>

#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE bool nrf_nvmc_ready_check(NRF_NVMC_Type const * p_reg)
{
    return (bool)(p_reg->READY & NVMC_READY_READY_Msk);
    2c42:	4a09      	ldr	r2, [pc, #36]	; (2c68 <flash_nrf_write+0x6c>)
    2c44:	f8d2 3400 	ldr.w	r3, [r2, #1024]	; 0x400
	while (!nrfx_nvmc_write_done_check()) {
    2c48:	07db      	lsls	r3, r3, #31
    2c4a:	d5fb      	bpl.n	2c44 <flash_nrf_write+0x48>
	return ret;
    2c4c:	2000      	movs	r0, #0
    2c4e:	e7e6      	b.n	2c1e <flash_nrf_write+0x22>
		if (SUSPEND_POFWARN()) {
			return -ECANCELED;
		}

		nrfx_nvmc_word_write(w_ctx->flash_addr,
    2c50:	5979      	ldr	r1, [r7, r5]
    2c52:	f001 fae1 	bl	4218 <nrfx_nvmc_word_write>
	w_ctx->len -= shift;
    2c56:	3504      	adds	r5, #4
}
    2c58:	e7ef      	b.n	2c3a <flash_nrf_write+0x3e>
		return 0;
    2c5a:	4620      	mov	r0, r4
    2c5c:	e7df      	b.n	2c1e <flash_nrf_write+0x22>
    2c5e:	bf00      	nop
    2c60:	000073b8 	.word	0x000073b8
    2c64:	000073da 	.word	0x000073da
    2c68:	4001e000 	.word	0x4001e000

00002c6c <flash_nrf_read>:
{
    2c6c:	b570      	push	{r4, r5, r6, lr}
    2c6e:	460d      	mov	r5, r1
	if (is_regular_addr_valid(addr, len)) {
    2c70:	4628      	mov	r0, r5
    2c72:	4619      	mov	r1, r3
{
    2c74:	4616      	mov	r6, r2
    2c76:	461c      	mov	r4, r3
	if (is_regular_addr_valid(addr, len)) {
    2c78:	f003 f90f 	bl	5e9a <is_regular_addr_valid>
    2c7c:	b940      	cbnz	r0, 2c90 <flash_nrf_read+0x24>
		LOG_ERR("invalid address: 0x%08lx:%zu",
    2c7e:	4809      	ldr	r0, [pc, #36]	; (2ca4 <flash_nrf_read+0x38>)
    2c80:	4623      	mov	r3, r4
    2c82:	462a      	mov	r2, r5
    2c84:	2145      	movs	r1, #69	; 0x45
    2c86:	f002 ff47 	bl	5b18 <z_log_minimal_printk>
    2c8a:	f06f 0015 	mvn.w	r0, #21
}
    2c8e:	bd70      	pop	{r4, r5, r6, pc}
	if (!len) {
    2c90:	b134      	cbz	r4, 2ca0 <flash_nrf_read+0x34>
	memcpy(data, (void *)addr, len);
    2c92:	4622      	mov	r2, r4
    2c94:	4629      	mov	r1, r5
    2c96:	4630      	mov	r0, r6
    2c98:	f003 f808 	bl	5cac <memcpy>
	return 0;
    2c9c:	2000      	movs	r0, #0
    2c9e:	e7f6      	b.n	2c8e <flash_nrf_read+0x22>
		return 0;
    2ca0:	4620      	mov	r0, r4
    2ca2:	e7f4      	b.n	2c8e <flash_nrf_read+0x22>
    2ca4:	000073b8 	.word	0x000073b8

00002ca8 <uarte_nrfx_poll_out>:
 *
 * @param dev UARTE device struct
 * @param c Character to send
 */
static void uarte_nrfx_poll_out(const struct device *dev, unsigned char c)
{
    2ca8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	struct uarte_nrfx_data *data = dev->data;
    2caa:	6906      	ldr	r6, [r0, #16]
{
    2cac:	4605      	mov	r5, r0
    2cae:	460f      	mov	r7, r1
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    2cb0:	f003 fbae 	bl	6410 <k_is_in_isr>
    2cb4:	b910      	cbnz	r0, 2cbc <uarte_nrfx_poll_out+0x14>
	return !z_sys_post_kernel;
    2cb6:	4b29      	ldr	r3, [pc, #164]	; (2d5c <uarte_nrfx_poll_out+0xb4>)
	int key;

	if (isr_mode) {
    2cb8:	781b      	ldrb	r3, [r3, #0]
    2cba:	b9a3      	cbnz	r3, 2ce6 <uarte_nrfx_poll_out+0x3e>
	__asm__ volatile(
    2cbc:	f04f 0320 	mov.w	r3, #32
    2cc0:	f3ef 8411 	mrs	r4, BASEPRI
    2cc4:	f383 8812 	msr	BASEPRI_MAX, r3
    2cc8:	f3bf 8f6f 	isb	sy
		while (1) {
			key = irq_lock();
			if (is_tx_ready(dev)) {
    2ccc:	6868      	ldr	r0, [r5, #4]
    2cce:	f003 f943 	bl	5f58 <is_tx_ready.isra.0>
    2cd2:	bb00      	cbnz	r0, 2d16 <uarte_nrfx_poll_out+0x6e>
	__asm__ volatile(
    2cd4:	f384 8811 	msr	BASEPRI, r4
    2cd8:	f3bf 8f6f 	isb	sy
		"cpsie i;"
		: : : "memory", "cc");
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
}
    2cdc:	e7ee      	b.n	2cbc <uarte_nrfx_poll_out+0x14>
	__asm__ volatile(
    2cde:	f384 8811 	msr	BASEPRI, r4
    2ce2:	f3bf 8f6f 	isb	sy
{
    2ce6:	2464      	movs	r4, #100	; 0x64
		NRFX_WAIT_FOR(is_tx_ready(dev), 100, 1, res);
    2ce8:	6868      	ldr	r0, [r5, #4]
    2cea:	f003 f935 	bl	5f58 <is_tx_ready.isra.0>
    2cee:	b928      	cbnz	r0, 2cfc <uarte_nrfx_poll_out+0x54>
    2cf0:	2001      	movs	r0, #1
    2cf2:	f003 fb4a 	bl	638a <nrfx_busy_wait>
    2cf6:	3c01      	subs	r4, #1
    2cf8:	d1f6      	bne.n	2ce8 <uarte_nrfx_poll_out+0x40>
    2cfa:	e7f4      	b.n	2ce6 <uarte_nrfx_poll_out+0x3e>
	__asm__ volatile(
    2cfc:	f04f 0320 	mov.w	r3, #32
    2d00:	f3ef 8411 	mrs	r4, BASEPRI
    2d04:	f383 8812 	msr	BASEPRI_MAX, r3
    2d08:	f3bf 8f6f 	isb	sy
			if (is_tx_ready(dev)) {
    2d0c:	6868      	ldr	r0, [r5, #4]
    2d0e:	f003 f923 	bl	5f58 <is_tx_ready.isra.0>
    2d12:	2800      	cmp	r0, #0
    2d14:	d0e3      	beq.n	2cde <uarte_nrfx_poll_out+0x36>
		}
	} else {
		key = wait_tx_ready(dev);
	}

	data->char_out = c;
    2d16:	f806 7f10 	strb.w	r7, [r6, #16]!
	tx_start(dev, &data->char_out, 1);
    2d1a:	6869      	ldr	r1, [r5, #4]
	return config->uarte_regs;
    2d1c:	680b      	ldr	r3, [r1, #0]
NRF_STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,
                                               uint8_t  const * p_buffer,
                                               size_t           length)
{
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    p_reg->TXD.MAXCNT = length;
    2d1e:	2201      	movs	r2, #1
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    2d20:	f8c3 6544 	str.w	r6, [r3, #1348]	; 0x544
    p_reg->TXD.MAXCNT = length;
    2d24:	f8c3 2548 	str.w	r2, [r3, #1352]	; 0x548
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2d28:	2200      	movs	r2, #0
    2d2a:	f8c3 2120 	str.w	r2, [r3, #288]	; 0x120
    2d2e:	f8d3 0120 	ldr.w	r0, [r3, #288]	; 0x120
    2d32:	f8c3 2158 	str.w	r2, [r3, #344]	; 0x158
    2d36:	f8d3 2158 	ldr.w	r2, [r3, #344]	; 0x158
	if (config->flags & UARTE_CFG_FLAG_LOW_POWER) {
    2d3a:	684a      	ldr	r2, [r1, #4]
    2d3c:	06d2      	lsls	r2, r2, #27
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
    2d3e:	bf41      	itttt	mi
    2d40:	2208      	movmi	r2, #8
    2d42:	f8c3 2500 	strmi.w	r2, [r3, #1280]	; 0x500
    p_reg->INTENSET = mask;
    2d46:	f44f 0280 	movmi.w	r2, #4194304	; 0x400000
    2d4a:	f8c3 2304 	strmi.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2d4e:	2201      	movs	r2, #1
    2d50:	609a      	str	r2, [r3, #8]
	__asm__ volatile(
    2d52:	f384 8811 	msr	BASEPRI, r4
    2d56:	f3bf 8f6f 	isb	sy

	irq_unlock(key);
}
    2d5a:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    2d5c:	2000140e 	.word	0x2000140e

00002d60 <uarte_nrfx_configure>:
{
    2d60:	b570      	push	{r4, r5, r6, lr}
	if (cfg->stop_bits != UART_CFG_STOP_BITS_1) {
    2d62:	794b      	ldrb	r3, [r1, #5]
    2d64:	2b01      	cmp	r3, #1
    2d66:	d120      	bne.n	2daa <uarte_nrfx_configure+0x4a>
	if (cfg->data_bits != UART_CFG_DATA_BITS_8) {
    2d68:	798b      	ldrb	r3, [r1, #6]
    2d6a:	2b03      	cmp	r3, #3
    2d6c:	d11d      	bne.n	2daa <uarte_nrfx_configure+0x4a>
	switch (cfg->flow_ctrl) {
    2d6e:	79cc      	ldrb	r4, [r1, #7]
    2d70:	b10c      	cbz	r4, 2d76 <uarte_nrfx_configure+0x16>
    2d72:	2c01      	cmp	r4, #1
    2d74:	d119      	bne.n	2daa <uarte_nrfx_configure+0x4a>
	switch (cfg->parity) {
    2d76:	790a      	ldrb	r2, [r1, #4]
    2d78:	b112      	cbz	r2, 2d80 <uarte_nrfx_configure+0x20>
    2d7a:	2a02      	cmp	r2, #2
    2d7c:	d115      	bne.n	2daa <uarte_nrfx_configure+0x4a>
    2d7e:	220e      	movs	r2, #14
	if (baudrate_set(dev, cfg->baudrate) != 0) {
    2d80:	680b      	ldr	r3, [r1, #0]
	return config->uarte_regs;
    2d82:	6845      	ldr	r5, [r0, #4]
	switch (baudrate) {
    2d84:	f5b3 4f16 	cmp.w	r3, #38400	; 0x9600
	return config->uarte_regs;
    2d88:	682d      	ldr	r5, [r5, #0]
	switch (baudrate) {
    2d8a:	d062      	beq.n	2e52 <uarte_nrfx_configure+0xf2>
    2d8c:	d82b      	bhi.n	2de6 <uarte_nrfx_configure+0x86>
    2d8e:	f5b3 5f16 	cmp.w	r3, #9600	; 0x2580
    2d92:	d061      	beq.n	2e58 <uarte_nrfx_configure+0xf8>
    2d94:	d814      	bhi.n	2dc0 <uarte_nrfx_configure+0x60>
    2d96:	f5b3 6f96 	cmp.w	r3, #1200	; 0x4b0
    2d9a:	d05f      	beq.n	2e5c <uarte_nrfx_configure+0xfc>
    2d9c:	d808      	bhi.n	2db0 <uarte_nrfx_configure+0x50>
    2d9e:	f5b3 7f96 	cmp.w	r3, #300	; 0x12c
    2da2:	d05e      	beq.n	2e62 <uarte_nrfx_configure+0x102>
    2da4:	f5b3 7f16 	cmp.w	r3, #600	; 0x258
    2da8:	d05e      	beq.n	2e68 <uarte_nrfx_configure+0x108>
    2daa:	f06f 0085 	mvn.w	r0, #133	; 0x85
    2dae:	e04f      	b.n	2e50 <uarte_nrfx_configure+0xf0>
    2db0:	f5b3 6f16 	cmp.w	r3, #2400	; 0x960
    2db4:	d05b      	beq.n	2e6e <uarte_nrfx_configure+0x10e>
    2db6:	f5b3 5f96 	cmp.w	r3, #4800	; 0x12c0
    2dba:	d1f6      	bne.n	2daa <uarte_nrfx_configure+0x4a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_4800;
    2dbc:	4b36      	ldr	r3, [pc, #216]	; (2e98 <uarte_nrfx_configure+0x138>)
    2dbe:	e03c      	b.n	2e3a <uarte_nrfx_configure+0xda>
	switch (baudrate) {
    2dc0:	f5b3 4fe1 	cmp.w	r3, #28800	; 0x7080
    2dc4:	d056      	beq.n	2e74 <uarte_nrfx_configure+0x114>
    2dc6:	d807      	bhi.n	2dd8 <uarte_nrfx_configure+0x78>
    2dc8:	f5b3 5f61 	cmp.w	r3, #14400	; 0x3840
    2dcc:	d054      	beq.n	2e78 <uarte_nrfx_configure+0x118>
    2dce:	f5b3 4f96 	cmp.w	r3, #19200	; 0x4b00
    2dd2:	d1ea      	bne.n	2daa <uarte_nrfx_configure+0x4a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_19200;
    2dd4:	4b31      	ldr	r3, [pc, #196]	; (2e9c <uarte_nrfx_configure+0x13c>)
    2dd6:	e030      	b.n	2e3a <uarte_nrfx_configure+0xda>
	switch (baudrate) {
    2dd8:	f647 2612 	movw	r6, #31250	; 0x7a12
    2ddc:	42b3      	cmp	r3, r6
    2dde:	d1e4      	bne.n	2daa <uarte_nrfx_configure+0x4a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_31250;
    2de0:	f44f 0300 	mov.w	r3, #8388608	; 0x800000
    2de4:	e029      	b.n	2e3a <uarte_nrfx_configure+0xda>
	switch (baudrate) {
    2de6:	f5b3 3f61 	cmp.w	r3, #230400	; 0x38400
    2dea:	d047      	beq.n	2e7c <uarte_nrfx_configure+0x11c>
    2dec:	d813      	bhi.n	2e16 <uarte_nrfx_configure+0xb6>
    2dee:	f5b3 3f96 	cmp.w	r3, #76800	; 0x12c00
    2df2:	d046      	beq.n	2e82 <uarte_nrfx_configure+0x122>
    2df4:	d809      	bhi.n	2e0a <uarte_nrfx_configure+0xaa>
    2df6:	f64d 26c0 	movw	r6, #56000	; 0xdac0
    2dfa:	42b3      	cmp	r3, r6
    2dfc:	d043      	beq.n	2e86 <uarte_nrfx_configure+0x126>
    2dfe:	f5b3 4f61 	cmp.w	r3, #57600	; 0xe100
    2e02:	d1d2      	bne.n	2daa <uarte_nrfx_configure+0x4a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_57600;
    2e04:	f44f 036b 	mov.w	r3, #15400960	; 0xeb0000
    2e08:	e017      	b.n	2e3a <uarte_nrfx_configure+0xda>
	switch (baudrate) {
    2e0a:	f5b3 3fe1 	cmp.w	r3, #115200	; 0x1c200
    2e0e:	d1cc      	bne.n	2daa <uarte_nrfx_configure+0x4a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_115200;
    2e10:	f04f 73eb 	mov.w	r3, #30801920	; 0x1d60000
    2e14:	e011      	b.n	2e3a <uarte_nrfx_configure+0xda>
	switch (baudrate) {
    2e16:	f5b3 2f61 	cmp.w	r3, #921600	; 0xe1000
    2e1a:	d037      	beq.n	2e8c <uarte_nrfx_configure+0x12c>
    2e1c:	d808      	bhi.n	2e30 <uarte_nrfx_configure+0xd0>
    2e1e:	4e20      	ldr	r6, [pc, #128]	; (2ea0 <uarte_nrfx_configure+0x140>)
    2e20:	42b3      	cmp	r3, r6
    2e22:	d036      	beq.n	2e92 <uarte_nrfx_configure+0x132>
    2e24:	f5b3 2fe1 	cmp.w	r3, #460800	; 0x70800
    2e28:	d1bf      	bne.n	2daa <uarte_nrfx_configure+0x4a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_460800;
    2e2a:	f04f 63e8 	mov.w	r3, #121634816	; 0x7400000
    2e2e:	e004      	b.n	2e3a <uarte_nrfx_configure+0xda>
	switch (baudrate) {
    2e30:	4e1c      	ldr	r6, [pc, #112]	; (2ea4 <uarte_nrfx_configure+0x144>)
    2e32:	42b3      	cmp	r3, r6
    2e34:	d1b9      	bne.n	2daa <uarte_nrfx_configure+0x4a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_1000000;
    2e36:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
	struct uarte_nrfx_data *data = dev->data;
    2e3a:	6900      	ldr	r0, [r0, #16]
    p_reg->BAUDRATE = baudrate;
    2e3c:	f8c5 3524 	str.w	r3, [r5, #1316]	; 0x524
	data->uart_config = *cfg;
    2e40:	1d03      	adds	r3, r0, #4
    2e42:	c903      	ldmia	r1, {r0, r1}
                    | (uint32_t)p_cfg->hwfc;
    2e44:	4322      	orrs	r2, r4
    p_reg->CONFIG = (uint32_t)p_cfg->parity
    2e46:	f8c5 256c 	str.w	r2, [r5, #1388]	; 0x56c
    2e4a:	e883 0003 	stmia.w	r3, {r0, r1}
	return 0;
    2e4e:	2000      	movs	r0, #0
}
    2e50:	bd70      	pop	{r4, r5, r6, pc}
		nrf_baudrate = NRF_UARTE_BAUDRATE_38400;
    2e52:	f44f 031d 	mov.w	r3, #10289152	; 0x9d0000
    2e56:	e7f0      	b.n	2e3a <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_9600;
    2e58:	4b13      	ldr	r3, [pc, #76]	; (2ea8 <uarte_nrfx_configure+0x148>)
    2e5a:	e7ee      	b.n	2e3a <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_1200;
    2e5c:	f44f 239e 	mov.w	r3, #323584	; 0x4f000
    2e60:	e7eb      	b.n	2e3a <uarte_nrfx_configure+0xda>
		nrf_baudrate = 0x00014000;
    2e62:	f44f 33a0 	mov.w	r3, #81920	; 0x14000
    2e66:	e7e8      	b.n	2e3a <uarte_nrfx_configure+0xda>
	switch (baudrate) {
    2e68:	f44f 331c 	mov.w	r3, #159744	; 0x27000
    2e6c:	e7e5      	b.n	2e3a <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_2400;
    2e6e:	f44f 231d 	mov.w	r3, #643072	; 0x9d000
    2e72:	e7e2      	b.n	2e3a <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_28800;
    2e74:	4b0d      	ldr	r3, [pc, #52]	; (2eac <uarte_nrfx_configure+0x14c>)
    2e76:	e7e0      	b.n	2e3a <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_14400;
    2e78:	4b0d      	ldr	r3, [pc, #52]	; (2eb0 <uarte_nrfx_configure+0x150>)
    2e7a:	e7de      	b.n	2e3a <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_230400;
    2e7c:	f04f 736c 	mov.w	r3, #61865984	; 0x3b00000
    2e80:	e7db      	b.n	2e3a <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_76800;
    2e82:	4b0c      	ldr	r3, [pc, #48]	; (2eb4 <uarte_nrfx_configure+0x154>)
    2e84:	e7d9      	b.n	2e3a <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_56000;
    2e86:	f44f 0365 	mov.w	r3, #15007744	; 0xe50000
    2e8a:	e7d6      	b.n	2e3a <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_921600;
    2e8c:	f04f 6370 	mov.w	r3, #251658240	; 0xf000000
    2e90:	e7d3      	b.n	2e3a <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_250000;
    2e92:	f04f 6380 	mov.w	r3, #67108864	; 0x4000000
    2e96:	e7d0      	b.n	2e3a <uarte_nrfx_configure+0xda>
    2e98:	0013b000 	.word	0x0013b000
    2e9c:	004ea000 	.word	0x004ea000
    2ea0:	0003d090 	.word	0x0003d090
    2ea4:	000f4240 	.word	0x000f4240
    2ea8:	00275000 	.word	0x00275000
    2eac:	0075c000 	.word	0x0075c000
    2eb0:	003af000 	.word	0x003af000
    2eb4:	013a9000 	.word	0x013a9000

00002eb8 <uarte_0_init>:
				.tx_buffer = uarte##idx##_tx_buffer,	       \
				.tx_buff_size = sizeof(uarte##idx##_tx_buffer),\
			};))

#ifdef CONFIG_UART_0_NRF_UARTE
UART_NRF_UARTE_DEVICE(0);
    2eb8:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    2ebc:	4607      	mov	r7, r0
    2ebe:	2200      	movs	r2, #0
    2ec0:	2101      	movs	r1, #1
    2ec2:	2002      	movs	r0, #2
    2ec4:	f7fe ff92 	bl	1dec <z_arm_irq_priority_set>
    2ec8:	2002      	movs	r0, #2
    2eca:	f7fe ff71 	bl	1db0 <arch_irq_enable>
	const struct uarte_nrfx_config *config = dev->config;
    2ece:	f8d7 8004 	ldr.w	r8, [r7, #4]
	struct uarte_nrfx_data *data = dev->data;
    2ed2:	693e      	ldr	r6, [r7, #16]
	return config->uarte_regs;
    2ed4:	f8d8 4000 	ldr.w	r4, [r8]
	err = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
    2ed8:	f8d8 900c 	ldr.w	r9, [r8, #12]
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
    2edc:	2100      	movs	r1, #0
    2ede:	f8c4 1500 	str.w	r1, [r4, #1280]	; 0x500
				      uint8_t id)
{
	int ret;
	const struct pinctrl_state *state;

	ret = pinctrl_lookup_state(config, id, &state);
    2ee2:	aa01      	add	r2, sp, #4
	data->dev = dev;
    2ee4:	6037      	str	r7, [r6, #0]
    2ee6:	4648      	mov	r0, r9
    2ee8:	f003 f87f 	bl	5fea <pinctrl_lookup_state>
	if (ret < 0) {
    2eec:	1e05      	subs	r5, r0, #0
    2eee:	db1f      	blt.n	2f30 <uarte_0_init+0x78>
		return ret;
	}

	return pinctrl_apply_state_direct(config, state);
    2ef0:	9b01      	ldr	r3, [sp, #4]
	return pinctrl_configure_pins(state->pins, state->pin_cnt, reg);
    2ef2:	f8d9 2000 	ldr.w	r2, [r9]
    2ef6:	7919      	ldrb	r1, [r3, #4]
    2ef8:	6818      	ldr	r0, [r3, #0]
    2efa:	f003 f8b8 	bl	606e <pinctrl_configure_pins>
	if (err < 0) {
    2efe:	1e05      	subs	r5, r0, #0
    2f00:	db16      	blt.n	2f30 <uarte_0_init+0x78>
	err = uarte_nrfx_configure(dev, &data->uart_config);
    2f02:	1d31      	adds	r1, r6, #4
    2f04:	4638      	mov	r0, r7
    2f06:	f7ff ff2b 	bl	2d60 <uarte_nrfx_configure>
	if (err) {
    2f0a:	4605      	mov	r5, r0
    2f0c:	b980      	cbnz	r0, 2f30 <uarte_0_init+0x78>
	    cfg->flags & UARTE_CFG_FLAG_PPI_ENDTX) {
    2f0e:	f8d8 3004 	ldr.w	r3, [r8, #4]
	if (IS_ENABLED(CONFIG_UART_ENHANCED_POLL_OUT) &&
    2f12:	0799      	lsls	r1, r3, #30
    2f14:	d523      	bpl.n	2f5e <uarte_0_init+0xa6>
	ret = gppi_channel_alloc(&data->ppi_ch_endtx);
    2f16:	f106 0012 	add.w	r0, r6, #18
    2f1a:	f001 f98b 	bl	4234 <nrfx_ppi_channel_alloc>
	if (ret != NRFX_SUCCESS) {
    2f1e:	4b25      	ldr	r3, [pc, #148]	; (2fb4 <uarte_0_init+0xfc>)
    2f20:	4298      	cmp	r0, r3
    2f22:	d009      	beq.n	2f38 <uarte_0_init+0x80>
		LOG_ERR("Failed to allocate PPI Channel");
    2f24:	4824      	ldr	r0, [pc, #144]	; (2fb8 <uarte_0_init+0x100>)
    2f26:	2145      	movs	r1, #69	; 0x45
    2f28:	f002 fdf6 	bl	5b18 <z_log_minimal_printk>
		return -EIO;
    2f2c:	f06f 0504 	mvn.w	r5, #4
UART_NRF_UARTE_DEVICE(0);
    2f30:	4628      	mov	r0, r5
    2f32:	b003      	add	sp, #12
    2f34:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
	nrfx_gppi_channel_endpoints_setup(data->ppi_ch_endtx,
    2f38:	7cb0      	ldrb	r0, [r6, #18]
    return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
    2f3a:	00c3      	lsls	r3, r0, #3
    2f3c:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    2f40:	f503 33f8 	add.w	r3, r3, #126976	; 0x1f000
    return (uint32_t)p_reg + (uint32_t)task;
    2f44:	f104 020c 	add.w	r2, r4, #12
    return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
    2f48:	f504 7190 	add.w	r1, r4, #288	; 0x120
NRF_STATIC_INLINE void nrf_ppi_channel_endpoint_setup(NRF_PPI_Type *    p_reg,
                                                      nrf_ppi_channel_t channel,
                                                      uint32_t          eep,
                                                      uint32_t          tep)
{
    p_reg->CH[(uint32_t) channel].EEP = eep;
    2f4c:	f8c3 1510 	str.w	r1, [r3, #1296]	; 0x510
    p_reg->CH[(uint32_t) channel].TEP = tep;
    2f50:	f8c3 2514 	str.w	r2, [r3, #1300]	; 0x514
    p_reg->CHENSET = mask;
    2f54:	4a19      	ldr	r2, [pc, #100]	; (2fbc <uarte_0_init+0x104>)
	nrfx_gppi_channels_enable(BIT(data->ppi_ch_endtx));
    2f56:	2301      	movs	r3, #1
    2f58:	4083      	lsls	r3, r0
    2f5a:	f8c2 3504 	str.w	r3, [r2, #1284]	; 0x504
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
    2f5e:	2308      	movs	r3, #8
    2f60:	f8c4 3500 	str.w	r3, [r4, #1280]	; 0x500
		if (!cfg->disable_rx) {
    2f64:	f898 3008 	ldrb.w	r3, [r8, #8]
    2f68:	b95b      	cbnz	r3, 2f82 <uarte_0_init+0xca>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    2f6a:	f8c4 3110 	str.w	r3, [r4, #272]	; 0x110
    2f6e:	f8d4 3110 	ldr.w	r3, [r4, #272]	; 0x110
			nrf_uarte_rx_buffer_set(uarte, &data->rx_data, 1);
    2f72:	f106 0311 	add.w	r3, r6, #17

NRF_STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
                                               uint8_t *        p_buffer,
                                               size_t           length)
{
    p_reg->RXD.PTR    = (uint32_t)p_buffer;
    2f76:	f8c4 3534 	str.w	r3, [r4, #1332]	; 0x534
    p_reg->RXD.MAXCNT = length;
    2f7a:	2301      	movs	r3, #1
    2f7c:	f8c4 3538 	str.w	r3, [r4, #1336]	; 0x538
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2f80:	6023      	str	r3, [r4, #0]
	if (!(cfg->flags & UARTE_CFG_FLAG_PPI_ENDTX)) {
    2f82:	f8d8 3004 	ldr.w	r3, [r8, #4]
    2f86:	079a      	lsls	r2, r3, #30
    p_reg->INTENSET = mask;
    2f88:	bf5c      	itt	pl
    2f8a:	f44f 7280 	movpl.w	r2, #256	; 0x100
    2f8e:	f8c4 2304 	strpl.w	r2, [r4, #772]	; 0x304
	if (cfg->flags & UARTE_CFG_FLAG_LOW_POWER) {
    2f92:	06db      	lsls	r3, r3, #27
    2f94:	bf44      	itt	mi
    2f96:	f44f 0380 	movmi.w	r3, #4194304	; 0x400000
    2f9a:	f8c4 3304 	strmi.w	r3, [r4, #772]	; 0x304
	nrf_uarte_tx_buffer_set(uarte, &data->char_out, 0);
    2f9e:	3610      	adds	r6, #16
    p_reg->TXD.MAXCNT = length;
    2fa0:	2300      	movs	r3, #0
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    2fa2:	f8c4 6544 	str.w	r6, [r4, #1348]	; 0x544
    p_reg->TXD.MAXCNT = length;
    2fa6:	f8c4 3548 	str.w	r3, [r4, #1352]	; 0x548
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    2faa:	2301      	movs	r3, #1
    2fac:	60a3      	str	r3, [r4, #8]
    2fae:	60e3      	str	r3, [r4, #12]
UART_NRF_UARTE_DEVICE(0);
    2fb0:	e7be      	b.n	2f30 <uarte_0_init+0x78>
    2fb2:	bf00      	nop
    2fb4:	0bad0000 	.word	0x0bad0000
    2fb8:	00007407 	.word	0x00007407
    2fbc:	4001f000 	.word	0x4001f000

00002fc0 <compare_int_lock>:
	return 0;
#endif
}

static bool compare_int_lock(int32_t chan)
{
    2fc0:	b510      	push	{r4, lr}
	atomic_val_t prev = atomic_and(&int_mask, ~BIT(chan));
    2fc2:	2301      	movs	r3, #1
    2fc4:	4083      	lsls	r3, r0
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    2fc6:	4a11      	ldr	r2, [pc, #68]	; (300c <compare_int_lock+0x4c>)
    2fc8:	f3bf 8f5b 	dmb	ish
    2fcc:	43dc      	mvns	r4, r3
    2fce:	e852 1f00 	ldrex	r1, [r2]
    2fd2:	ea01 0c04 	and.w	ip, r1, r4
    2fd6:	e842 ce00 	strex	lr, ip, [r2]
    2fda:	f1be 0f00 	cmp.w	lr, #0
    2fde:	d1f6      	bne.n	2fce <compare_int_lock+0xe>
    2fe0:	f3bf 8f5b 	dmb	ish

	nrf_rtc_int_disable(RTC, RTC_CHANNEL_INT_MASK(chan));
    2fe4:	f44f 3280 	mov.w	r2, #65536	; 0x10000
    2fe8:	fa02 f000 	lsl.w	r0, r2, r0
    2fec:	f102 4280 	add.w	r2, r2, #1073741824	; 0x40000000
    2ff0:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
    2ff4:	f8c2 0308 	str.w	r0, [r2, #776]	; 0x308
  __ASM volatile ("dmb 0xF":::"memory");
    2ff8:	f3bf 8f5f 	dmb	sy
  __ASM volatile ("isb 0xF":::"memory");
    2ffc:	f3bf 8f6f 	isb	sy

	__DMB();
	__ISB();

	return prev & BIT(chan);
    3000:	420b      	tst	r3, r1
}
    3002:	bf14      	ite	ne
    3004:	2001      	movne	r0, #1
    3006:	2000      	moveq	r0, #0
    3008:	bd10      	pop	{r4, pc}
    300a:	bf00      	nop
    300c:	20000e40 	.word	0x20000e40

00003010 <sys_clock_timeout_handler>:
static void sys_clock_timeout_handler(int32_t chan,
				      uint64_t expire_time,
				      void *user_data)
{
	uint32_t cc_value = absolute_time_to_cc(expire_time);
	uint64_t dticks = (expire_time - last_count) / CYC_PER_TICK;
    3010:	4919      	ldr	r1, [pc, #100]	; (3078 <sys_clock_timeout_handler+0x68>)
{
    3012:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    3014:	4604      	mov	r4, r0
	return absolute_time & COUNTER_MAX;
    3016:	f022 457f 	bic.w	r5, r2, #4278190080	; 0xff000000
	uint64_t dticks = (expire_time - last_count) / CYC_PER_TICK;
    301a:	6808      	ldr	r0, [r1, #0]

	last_count += dticks * CYC_PER_TICK;
    301c:	e9c1 2300 	strd	r2, r3, [r1]
	return (cc_value >= ANCHOR_RANGE_START) && (cc_value < ANCHOR_RANGE_END);
    3020:	f5a5 1300 	sub.w	r3, r5, #2097152	; 0x200000
	uint64_t dticks = (expire_time - last_count) / CYC_PER_TICK;
    3024:	1a10      	subs	r0, r2, r0
	if (in_anchor_range(cc_value)) {
    3026:	f5b3 0f40 	cmp.w	r3, #12582912	; 0xc00000
    302a:	d222      	bcs.n	3072 <sys_clock_timeout_handler+0x62>
		anchor = (((uint64_t)overflow_cnt) << COUNTER_BIT_WIDTH) + cc_value;
    302c:	4b13      	ldr	r3, [pc, #76]	; (307c <sys_clock_timeout_handler+0x6c>)
    302e:	681b      	ldr	r3, [r3, #0]
    3030:	0a1a      	lsrs	r2, r3, #8
    3032:	061b      	lsls	r3, r3, #24
    3034:	195e      	adds	r6, r3, r5
    3036:	4b12      	ldr	r3, [pc, #72]	; (3080 <sys_clock_timeout_handler+0x70>)
    3038:	f142 0700 	adc.w	r7, r2, #0
    303c:	e9c3 6700 	strd	r6, r7, [r3]
		return true;
    3040:	2601      	movs	r6, #1
		 */
		compare_set(chan, last_count + CYC_PER_TICK,
					  sys_clock_timeout_handler, NULL);
	}

	sys_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
    3042:	f001 fa75 	bl	4530 <sys_clock_announce>
    return p_reg->CC[ch];
    3046:	00a3      	lsls	r3, r4, #2
    3048:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    304c:	f503 3388 	add.w	r3, r3, #69632	; 0x11000
    3050:	f8d3 2540 	ldr.w	r2, [r3, #1344]	; 0x540
			   (int32_t)dticks : (dticks > 0));

	if (cc_value == get_comparator(chan)) {
    3054:	42aa      	cmp	r2, r5
    3056:	d10b      	bne.n	3070 <sys_clock_timeout_handler+0x60>
		 * If anchor was updated we can enable same CC value to trigger
		 * interrupt after full cycle. Else set event in anchor update
		 * range. Since anchor was not updated we know that it's very
		 * far from mid point so setting is done without any protection.
		 */
		if (!anchor_updated) {
    3058:	b91e      	cbnz	r6, 3062 <sys_clock_timeout_handler+0x52>
    p_reg->CC[ch] = cc_val;
    305a:	f44f 0200 	mov.w	r2, #8388608	; 0x800000
    305e:	f8c3 2540 	str.w	r2, [r3, #1344]	; 0x540
    p_reg->EVTENSET = mask;
    3062:	4b08      	ldr	r3, [pc, #32]	; (3084 <sys_clock_timeout_handler+0x74>)
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    3064:	f44f 3080 	mov.w	r0, #65536	; 0x10000
    3068:	fa00 f404 	lsl.w	r4, r0, r4
    306c:	f8c3 4344 	str.w	r4, [r3, #836]	; 0x344
			set_comparator(chan, COUNTER_HALF_SPAN);
		}
		event_enable(chan);
	}
}
    3070:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	return false;
    3072:	2600      	movs	r6, #0
    3074:	e7e5      	b.n	3042 <sys_clock_timeout_handler+0x32>
    3076:	bf00      	nop
    3078:	200000c0 	.word	0x200000c0
    307c:	20000e44 	.word	0x20000e44
    3080:	200000a8 	.word	0x200000a8
    3084:	40011000 	.word	0x40011000

00003088 <compare_int_unlock>:
	if (key) {
    3088:	b319      	cbz	r1, 30d2 <compare_int_unlock+0x4a>
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    308a:	f3bf 8f5b 	dmb	ish
		atomic_or(&int_mask, BIT(chan));
    308e:	2301      	movs	r3, #1
    3090:	4a10      	ldr	r2, [pc, #64]	; (30d4 <compare_int_unlock+0x4c>)
    3092:	4083      	lsls	r3, r0
    3094:	e852 1f00 	ldrex	r1, [r2]
    3098:	4319      	orrs	r1, r3
    309a:	e842 1c00 	strex	ip, r1, [r2]
    309e:	f1bc 0f00 	cmp.w	ip, #0
    30a2:	d1f7      	bne.n	3094 <compare_int_unlock+0xc>
    30a4:	f3bf 8f5b 	dmb	ish
    p_reg->INTENSET = mask;
    30a8:	4a0b      	ldr	r2, [pc, #44]	; (30d8 <compare_int_unlock+0x50>)
		nrf_rtc_int_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    30aa:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    30ae:	4083      	lsls	r3, r0
    30b0:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
	return __atomic_load_n(target, __ATOMIC_SEQ_CST);
    30b4:	4b09      	ldr	r3, [pc, #36]	; (30dc <compare_int_unlock+0x54>)
    30b6:	f3bf 8f5b 	dmb	ish
    30ba:	681b      	ldr	r3, [r3, #0]
    30bc:	f3bf 8f5b 	dmb	ish
		if (atomic_get(&force_isr_mask) & BIT(chan)) {
    30c0:	fa23 f000 	lsr.w	r0, r3, r0
    30c4:	07c3      	lsls	r3, r0, #31
    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    30c6:	bf42      	ittt	mi
    30c8:	4b05      	ldrmi	r3, [pc, #20]	; (30e0 <compare_int_unlock+0x58>)
    30ca:	f44f 3200 	movmi.w	r2, #131072	; 0x20000
    30ce:	f8c3 2100 	strmi.w	r2, [r3, #256]	; 0x100
}
    30d2:	4770      	bx	lr
    30d4:	20000e40 	.word	0x20000e40
    30d8:	40011000 	.word	0x40011000
    30dc:	20000e3c 	.word	0x20000e3c
    30e0:	e000e100 	.word	0xe000e100

000030e4 <z_nrf_rtc_timer_read>:
	uint64_t val = ((uint64_t)overflow_cnt) << COUNTER_BIT_WIDTH;
    30e4:	4b0d      	ldr	r3, [pc, #52]	; (311c <z_nrf_rtc_timer_read+0x38>)
    30e6:	6818      	ldr	r0, [r3, #0]
    30e8:	0a01      	lsrs	r1, r0, #8
    30ea:	0600      	lsls	r0, r0, #24
  __ASM volatile ("dmb 0xF":::"memory");
    30ec:	f3bf 8f5f 	dmb	sy
     return p_reg->COUNTER;
    30f0:	4b0b      	ldr	r3, [pc, #44]	; (3120 <z_nrf_rtc_timer_read+0x3c>)
    30f2:	f8d3 3504 	ldr.w	r3, [r3, #1284]	; 0x504
	val += cntr;
    30f6:	1818      	adds	r0, r3, r0
    30f8:	f141 0100 	adc.w	r1, r1, #0
	if (cntr < OVERFLOW_RISK_RANGE_END) {
    30fc:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
    3100:	d20a      	bcs.n	3118 <z_nrf_rtc_timer_read+0x34>
		if (val < anchor) {
    3102:	4b08      	ldr	r3, [pc, #32]	; (3124 <z_nrf_rtc_timer_read+0x40>)
    3104:	e9d3 2300 	ldrd	r2, r3, [r3]
    3108:	4290      	cmp	r0, r2
    310a:	eb71 0303 	sbcs.w	r3, r1, r3
    310e:	d203      	bcs.n	3118 <z_nrf_rtc_timer_read+0x34>
			val += COUNTER_SPAN;
    3110:	f110 7080 	adds.w	r0, r0, #16777216	; 0x1000000
    3114:	f141 0100 	adc.w	r1, r1, #0
}
    3118:	4770      	bx	lr
    311a:	bf00      	nop
    311c:	20000e44 	.word	0x20000e44
    3120:	40011000 	.word	0x40011000
    3124:	200000a8 	.word	0x200000a8

00003128 <compare_set>:
{
    3128:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    312c:	b085      	sub	sp, #20
    312e:	4616      	mov	r6, r2
    3130:	4698      	mov	r8, r3
    3132:	4605      	mov	r5, r0
	key = compare_int_lock(chan);
    3134:	f7ff ff44 	bl	2fc0 <compare_int_lock>
    3138:	9000      	str	r0, [sp, #0]
	uint64_t curr_time = z_nrf_rtc_timer_read();
    313a:	f7ff ffd3 	bl	30e4 <z_nrf_rtc_timer_read>
	if (curr_time < target_time) {
    313e:	42b0      	cmp	r0, r6
    3140:	eb71 0308 	sbcs.w	r3, r1, r8
    3144:	d278      	bcs.n	3238 <compare_set+0x110>
		if (target_time - curr_time > COUNTER_SPAN) {
    3146:	4b46      	ldr	r3, [pc, #280]	; (3260 <compare_set+0x138>)
    3148:	1a30      	subs	r0, r6, r0
    314a:	eb68 0101 	sbc.w	r1, r8, r1
    314e:	4298      	cmp	r0, r3
    3150:	f171 0300 	sbcs.w	r3, r1, #0
    3154:	f080 8081 	bcs.w	325a <compare_set+0x132>
		if (target_time != cc_data[chan].target_time) {
    3158:	4b42      	ldr	r3, [pc, #264]	; (3264 <compare_set+0x13c>)
    315a:	eb03 1305 	add.w	r3, r3, r5, lsl #4
    315e:	e9d3 ab02 	ldrd	sl, fp, [r3, #8]
    3162:	45d8      	cmp	r8, fp
    3164:	bf08      	it	eq
    3166:	4556      	cmpeq	r6, sl
    3168:	d051      	beq.n	320e <compare_set+0xe6>
    316a:	ea4f 0985 	mov.w	r9, r5, lsl #2
    316e:	f109 4980 	add.w	r9, r9, #1073741824	; 0x40000000
	nrf_rtc_event_clear(RTC, RTC_CHANNEL_EVENT_ADDR(chan));
    3172:	f105 0750 	add.w	r7, r5, #80	; 0x50
    3176:	f509 3988 	add.w	r9, r9, #69632	; 0x11000
    317a:	00bf      	lsls	r7, r7, #2
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    317c:	f44f 3180 	mov.w	r1, #65536	; 0x10000
    3180:	fa01 f305 	lsl.w	r3, r1, r5
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    3184:	b2bf      	uxth	r7, r7
	return absolute_time & COUNTER_MAX;
    3186:	f026 427f 	bic.w	r2, r6, #4278190080	; 0xff000000
    318a:	f107 4780 	add.w	r7, r7, #1073741824	; 0x40000000
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    318e:	9301      	str	r3, [sp, #4]
    return p_reg->CC[ch];
    3190:	f8d9 0540 	ldr.w	r0, [r9, #1344]	; 0x540
     return p_reg->COUNTER;
    3194:	4b34      	ldr	r3, [pc, #208]	; (3268 <compare_set+0x140>)
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    3196:	f507 3788 	add.w	r7, r7, #69632	; 0x11000
	uint32_t cc_val = abs_val & COUNTER_MAX;
    319a:	4614      	mov	r4, r2
     return p_reg->COUNTER;
    319c:	f8d3 1504 	ldr.w	r1, [r3, #1284]	; 0x504
	return (a - b) & COUNTER_MAX;
    31a0:	1a40      	subs	r0, r0, r1
    31a2:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
	nrf_rtc_cc_set(RTC, chan, cyc & COUNTER_MAX);
    31a6:	f021 4c7f 	bic.w	ip, r1, #4278190080	; 0xff000000
		if (counter_sub(prev_cc, now) == 1) {
    31aa:	2801      	cmp	r0, #1
    p_reg->CC[ch] = cc_val;
    31ac:	f8c9 c540 	str.w	ip, [r9, #1344]	; 0x540
    31b0:	d107      	bne.n	31c2 <compare_set+0x9a>
    31b2:	e9cd 2102 	strd	r2, r1, [sp, #8]
    31b6:	2013      	movs	r0, #19
    31b8:	f003 f930 	bl	641c <z_impl_k_busy_wait>
    31bc:	e9dd 2102 	ldrd	r2, r1, [sp, #8]
    31c0:	4b29      	ldr	r3, [pc, #164]	; (3268 <compare_set+0x140>)
		if (counter_sub(cc_val, now + 2) > COUNTER_HALF_SPAN) {
    31c2:	f101 0c02 	add.w	ip, r1, #2
	return (a - b) & COUNTER_MAX;
    31c6:	eba4 000c 	sub.w	r0, r4, ip
    31ca:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
			cc_val = now + 2;
    31ce:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    31d2:	bf88      	it	hi
    31d4:	4664      	movhi	r4, ip
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    31d6:	2000      	movs	r0, #0
    31d8:	6038      	str	r0, [r7, #0]
    31da:	6838      	ldr	r0, [r7, #0]
    p_reg->EVTENSET = mask;
    31dc:	9801      	ldr	r0, [sp, #4]
    31de:	f8c3 0344 	str.w	r0, [r3, #836]	; 0x344
	nrf_rtc_cc_set(RTC, chan, cyc & COUNTER_MAX);
    31e2:	f024 407f 	bic.w	r0, r4, #4278190080	; 0xff000000
    p_reg->CC[ch] = cc_val;
    31e6:	f8c9 0540 	str.w	r0, [r9, #1344]	; 0x540
     return p_reg->COUNTER;
    31ea:	f8d3 0504 	ldr.w	r0, [r3, #1284]	; 0x504
		 (counter_sub(cc_val, now2 + 2) > COUNTER_HALF_SPAN));
    31ee:	4281      	cmp	r1, r0
    31f0:	d006      	beq.n	3200 <compare_set+0xd8>
	return (a - b) & COUNTER_MAX;
    31f2:	1a20      	subs	r0, r4, r0
    31f4:	3802      	subs	r0, #2
    31f6:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
	} while ((now2 != now) &&
    31fa:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    31fe:	d819      	bhi.n	3234 <compare_set+0x10c>
	return (a - b) & COUNTER_MAX;
    3200:	1aa4      	subs	r4, r4, r2
    3202:	f024 447f 	bic.w	r4, r4, #4278190080	; 0xff000000
			target_time += counter_sub(cc_set, cc_value);
    3206:	eb14 0a06 	adds.w	sl, r4, r6
    320a:	f148 0b00 	adc.w	fp, r8, #0
	cc_data[chan].target_time = target_time;
    320e:	4915      	ldr	r1, [pc, #84]	; (3264 <compare_set+0x13c>)
	cc_data[chan].callback = handler;
    3210:	980e      	ldr	r0, [sp, #56]	; 0x38
	cc_data[chan].target_time = target_time;
    3212:	012b      	lsls	r3, r5, #4
    3214:	eb01 1205 	add.w	r2, r1, r5, lsl #4
    3218:	e9c2 ab02 	strd	sl, fp, [r2, #8]
	cc_data[chan].callback = handler;
    321c:	50c8      	str	r0, [r1, r3]
	cc_data[chan].user_context = user_data;
    321e:	9b0f      	ldr	r3, [sp, #60]	; 0x3c
    3220:	6053      	str	r3, [r2, #4]
	return ret;
    3222:	2400      	movs	r4, #0
	compare_int_unlock(chan, key);
    3224:	4628      	mov	r0, r5
    3226:	9900      	ldr	r1, [sp, #0]
    3228:	f7ff ff2e 	bl	3088 <compare_int_unlock>
}
    322c:	4620      	mov	r0, r4
    322e:	b005      	add	sp, #20
    3230:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    3234:	4620      	mov	r0, r4
    3236:	e7b1      	b.n	319c <compare_set+0x74>
		atomic_or(&force_isr_mask, BIT(chan));
    3238:	2301      	movs	r3, #1
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    323a:	4a0c      	ldr	r2, [pc, #48]	; (326c <compare_set+0x144>)
    323c:	f3bf 8f5b 	dmb	ish
    3240:	40ab      	lsls	r3, r5
    3242:	e852 1f00 	ldrex	r1, [r2]
    3246:	4319      	orrs	r1, r3
    3248:	e842 1000 	strex	r0, r1, [r2]
    324c:	2800      	cmp	r0, #0
    324e:	d1f8      	bne.n	3242 <compare_set+0x11a>
    3250:	f3bf 8f5b 	dmb	ish
    3254:	46b2      	mov	sl, r6
    3256:	46c3      	mov	fp, r8
    3258:	e7d9      	b.n	320e <compare_set+0xe6>
			return -EINVAL;
    325a:	f06f 0415 	mvn.w	r4, #21
    325e:	e7e1      	b.n	3224 <compare_set+0xfc>
    3260:	01000001 	.word	0x01000001
    3264:	200000b0 	.word	0x200000b0
    3268:	40011000 	.word	0x40011000
    326c:	20000e3c 	.word	0x20000e3c

00003270 <sys_clock_driver_init>:
{
	return (uint32_t)z_nrf_rtc_timer_read();
}

static int sys_clock_driver_init(const struct device *dev)
{
    3270:	b573      	push	{r0, r1, r4, r5, r6, lr}
			CLOCK_CONTROL_NRF_LF_START_STABLE);

	/* TODO: replace with counter driver to access RTC */
	nrf_rtc_prescaler_set(RTC, 0);
	for (int32_t chan = 0; chan < CHAN_COUNT; chan++) {
		cc_data[chan].target_time = TARGET_TIME_INVALID;
    3272:	4b19      	ldr	r3, [pc, #100]	; (32d8 <sys_clock_driver_init+0x68>)
    p_reg->PRESCALER = val;
    3274:	4d19      	ldr	r5, [pc, #100]	; (32dc <sys_clock_driver_init+0x6c>)
    3276:	2400      	movs	r4, #0
    3278:	f04f 30ff 	mov.w	r0, #4294967295
    327c:	f04f 31ff 	mov.w	r1, #4294967295
    3280:	f8c5 4508 	str.w	r4, [r5, #1288]	; 0x508
    3284:	e9c3 0102 	strd	r0, r1, [r3, #8]
    p_reg->INTENSET = mask;
    3288:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    328c:	f8c5 3304 	str.w	r3, [r5, #772]	; 0x304
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    3290:	4b13      	ldr	r3, [pc, #76]	; (32e0 <sys_clock_driver_init+0x70>)
    3292:	2602      	movs	r6, #2
    3294:	f44f 3200 	mov.w	r2, #131072	; 0x20000

	nrf_rtc_int_enable(RTC, NRF_RTC_INT_OVERFLOW_MASK);

	NVIC_ClearPendingIRQ(RTC_IRQn);

	IRQ_CONNECT(RTC_IRQn, DT_IRQ(DT_NODELABEL(RTC_LABEL), priority),
    3298:	2101      	movs	r1, #1
    329a:	f8c5 6304 	str.w	r6, [r5, #772]	; 0x304
    329e:	2011      	movs	r0, #17
    32a0:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
    32a4:	4622      	mov	r2, r4
    32a6:	f7fe fda1 	bl	1dec <z_arm_irq_priority_set>
		    rtc_nrf_isr, 0, 0);
	irq_enable(RTC_IRQn);
    32aa:	2011      	movs	r0, #17
    32ac:	f7fe fd80 	bl	1db0 <arch_irq_enable>

	nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_CLEAR);
	nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_START);

	int_mask = BIT_MASK(CHAN_COUNT);
    32b0:	4a0c      	ldr	r2, [pc, #48]	; (32e4 <sys_clock_driver_init+0x74>)
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    32b2:	2301      	movs	r3, #1
    32b4:	60ab      	str	r3, [r5, #8]
    32b6:	602b      	str	r3, [r5, #0]
    32b8:	6013      	str	r3, [r2, #0]

	uint32_t initial_timeout = IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
		(COUNTER_HALF_SPAN - 1) :
		(counter() + CYC_PER_TICK);

	compare_set(0, initial_timeout, sys_clock_timeout_handler, NULL);
    32ba:	4b0b      	ldr	r3, [pc, #44]	; (32e8 <sys_clock_driver_init+0x78>)
    32bc:	4a0b      	ldr	r2, [pc, #44]	; (32ec <sys_clock_driver_init+0x7c>)
    32be:	9300      	str	r3, [sp, #0]
    32c0:	9401      	str	r4, [sp, #4]
    32c2:	2300      	movs	r3, #0
    32c4:	4620      	mov	r0, r4
    32c6:	f7ff ff2f 	bl	3128 <compare_set>

	z_nrf_clock_control_lf_on(mode);
    32ca:	4630      	mov	r0, r6
    32cc:	f7ff fa5a 	bl	2784 <z_nrf_clock_control_lf_on>

	return 0;
}
    32d0:	4620      	mov	r0, r4
    32d2:	b002      	add	sp, #8
    32d4:	bd70      	pop	{r4, r5, r6, pc}
    32d6:	bf00      	nop
    32d8:	200000b0 	.word	0x200000b0
    32dc:	40011000 	.word	0x40011000
    32e0:	e000e100 	.word	0xe000e100
    32e4:	20000e40 	.word	0x20000e40
    32e8:	00003011 	.word	0x00003011
    32ec:	007fffff 	.word	0x007fffff

000032f0 <rtc_nrf_isr>:
{
    32f0:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    return p_reg->INTENSET & mask;
    32f4:	4c35      	ldr	r4, [pc, #212]	; (33cc <rtc_nrf_isr+0xdc>)
    32f6:	f8d4 3304 	ldr.w	r3, [r4, #772]	; 0x304
	if (nrf_rtc_int_enable_check(RTC, NRF_RTC_INT_OVERFLOW_MASK) &&
    32fa:	079a      	lsls	r2, r3, #30
    32fc:	d50b      	bpl.n	3316 <rtc_nrf_isr+0x26>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    32fe:	f8d4 3104 	ldr.w	r3, [r4, #260]	; 0x104
    3302:	b143      	cbz	r3, 3316 <rtc_nrf_isr+0x26>
		overflow_cnt++;
    3304:	4a32      	ldr	r2, [pc, #200]	; (33d0 <rtc_nrf_isr+0xe0>)
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    3306:	2300      	movs	r3, #0
    3308:	f8c4 3104 	str.w	r3, [r4, #260]	; 0x104
    330c:	f8d4 3104 	ldr.w	r3, [r4, #260]	; 0x104
    3310:	6813      	ldr	r3, [r2, #0]
    3312:	3301      	adds	r3, #1
    3314:	6013      	str	r3, [r2, #0]
	__asm__ volatile(
    3316:	f04f 0320 	mov.w	r3, #32
    331a:	f3ef 8211 	mrs	r2, BASEPRI
    331e:	f383 8812 	msr	BASEPRI_MAX, r3
    3322:	f3bf 8f6f 	isb	sy
    return p_reg->INTENSET & mask;
    3326:	f8d4 3304 	ldr.w	r3, [r4, #772]	; 0x304
	if (nrf_rtc_int_enable_check(RTC, RTC_CHANNEL_INT_MASK(chan))) {
    332a:	03db      	lsls	r3, r3, #15
    332c:	d512      	bpl.n	3354 <rtc_nrf_isr+0x64>
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    332e:	f3bf 8f5b 	dmb	ish
    3332:	4b28      	ldr	r3, [pc, #160]	; (33d4 <rtc_nrf_isr+0xe4>)
    3334:	e853 1f00 	ldrex	r1, [r3]
    3338:	f021 0001 	bic.w	r0, r1, #1
    333c:	e843 0600 	strex	r6, r0, [r3]
    3340:	2e00      	cmp	r6, #0
    3342:	d1f7      	bne.n	3334 <rtc_nrf_isr+0x44>
    3344:	f3bf 8f5b 	dmb	ish
		result = atomic_and(&force_isr_mask, ~BIT(chan)) ||
    3348:	2900      	cmp	r1, #0
    334a:	d136      	bne.n	33ba <rtc_nrf_isr+0xca>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    334c:	f8d4 3140 	ldr.w	r3, [r4, #320]	; 0x140
		if (result) {
    3350:	2b00      	cmp	r3, #0
    3352:	d132      	bne.n	33ba <rtc_nrf_isr+0xca>
{
    3354:	2300      	movs	r3, #0
	__asm__ volatile(
    3356:	f382 8811 	msr	BASEPRI, r2
    335a:	f3bf 8f6f 	isb	sy
	if (channel_processing_check_and_clear(chan)) {
    335e:	b34b      	cbz	r3, 33b4 <rtc_nrf_isr+0xc4>
		curr_time = z_nrf_rtc_timer_read();
    3360:	f7ff fec0 	bl	30e4 <z_nrf_rtc_timer_read>
	__asm__ volatile(
    3364:	f04f 0320 	mov.w	r3, #32
    3368:	f3ef 8c11 	mrs	ip, BASEPRI
    336c:	f383 8812 	msr	BASEPRI_MAX, r3
    3370:	f3bf 8f6f 	isb	sy
		expire_time = cc_data[chan].target_time;
    3374:	4b18      	ldr	r3, [pc, #96]	; (33d8 <rtc_nrf_isr+0xe8>)
    3376:	e9d3 6702 	ldrd	r6, r7, [r3, #8]
		if (curr_time >= expire_time) {
    337a:	42b0      	cmp	r0, r6
    337c:	eb71 0207 	sbcs.w	r2, r1, r7
    3380:	f04f 0200 	mov.w	r2, #0
    3384:	d320      	bcc.n	33c8 <rtc_nrf_isr+0xd8>
			cc_data[chan].target_time = TARGET_TIME_INVALID;
    3386:	f04f 38ff 	mov.w	r8, #4294967295
    338a:	f04f 39ff 	mov.w	r9, #4294967295
			user_context = cc_data[chan].user_context;
    338e:	e9d3 1500 	ldrd	r1, r5, [r3]
			cc_data[chan].target_time = TARGET_TIME_INVALID;
    3392:	e9c3 8902 	strd	r8, r9, [r3, #8]
			cc_data[chan].callback = NULL;
    3396:	601a      	str	r2, [r3, #0]
    p_reg->EVTENCLR = mask;
    3398:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    339c:	f8c4 3348 	str.w	r3, [r4, #840]	; 0x348
	__asm__ volatile(
    33a0:	f38c 8811 	msr	BASEPRI, ip
    33a4:	f3bf 8f6f 	isb	sy
		if (handler) {
    33a8:	b121      	cbz	r1, 33b4 <rtc_nrf_isr+0xc4>
			handler(chan, expire_time, user_context);
    33aa:	9500      	str	r5, [sp, #0]
    33ac:	4632      	mov	r2, r6
    33ae:	463b      	mov	r3, r7
    33b0:	2000      	movs	r0, #0
    33b2:	4788      	blx	r1
}
    33b4:	b003      	add	sp, #12
    33b6:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    33ba:	2300      	movs	r3, #0
    33bc:	f8c4 3140 	str.w	r3, [r4, #320]	; 0x140
    33c0:	f8d4 3140 	ldr.w	r3, [r4, #320]	; 0x140
		result = atomic_and(&force_isr_mask, ~BIT(chan)) ||
    33c4:	2301      	movs	r3, #1
}
    33c6:	e7c6      	b.n	3356 <rtc_nrf_isr+0x66>
		z_nrf_rtc_timer_compare_handler_t handler = NULL;
    33c8:	4611      	mov	r1, r2
    33ca:	e7e9      	b.n	33a0 <rtc_nrf_isr+0xb0>
    33cc:	40011000 	.word	0x40011000
    33d0:	20000e44 	.word	0x20000e44
    33d4:	20000e3c 	.word	0x20000e3c
    33d8:	200000b0 	.word	0x200000b0

000033dc <sys_clock_set_timeout>:
	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    33dc:	1c43      	adds	r3, r0, #1
{
    33de:	b513      	push	{r0, r1, r4, lr}
	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    33e0:	d021      	beq.n	3426 <sys_clock_set_timeout+0x4a>
	ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
    33e2:	2801      	cmp	r0, #1
    33e4:	dd21      	ble.n	342a <sys_clock_set_timeout+0x4e>
    33e6:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    33ea:	da20      	bge.n	342e <sys_clock_set_timeout+0x52>
    33ec:	1e44      	subs	r4, r0, #1
	uint32_t unannounced = z_nrf_rtc_timer_read() - last_count;
    33ee:	f7ff fe79 	bl	30e4 <z_nrf_rtc_timer_read>
    33f2:	4b10      	ldr	r3, [pc, #64]	; (3434 <sys_clock_set_timeout+0x58>)
    33f4:	e9d3 1300 	ldrd	r1, r3, [r3]
    33f8:	1a40      	subs	r0, r0, r1
		ticks = 0;
    33fa:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    33fe:	bf28      	it	cs
    3400:	2400      	movcs	r4, #0
	cyc = ticks * CYC_PER_TICK + 1 + unannounced;
    3402:	3001      	adds	r0, #1
    3404:	1902      	adds	r2, r0, r4
	uint64_t target_time = cyc + last_count;
    3406:	480c      	ldr	r0, [pc, #48]	; (3438 <sys_clock_set_timeout+0x5c>)
    3408:	4282      	cmp	r2, r0
    340a:	bf28      	it	cs
    340c:	4602      	movcs	r2, r0
    340e:	1852      	adds	r2, r2, r1
    3410:	f04f 0000 	mov.w	r0, #0
	compare_set(0, target_time, sys_clock_timeout_handler, NULL);
    3414:	4909      	ldr	r1, [pc, #36]	; (343c <sys_clock_set_timeout+0x60>)
    3416:	9001      	str	r0, [sp, #4]
    3418:	9100      	str	r1, [sp, #0]
    341a:	f143 0300 	adc.w	r3, r3, #0
    341e:	f7ff fe83 	bl	3128 <compare_set>
}
    3422:	b002      	add	sp, #8
    3424:	bd10      	pop	{r4, pc}
	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    3426:	4804      	ldr	r0, [pc, #16]	; (3438 <sys_clock_set_timeout+0x5c>)
    3428:	e7e0      	b.n	33ec <sys_clock_set_timeout+0x10>
	ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
    342a:	2400      	movs	r4, #0
    342c:	e7df      	b.n	33ee <sys_clock_set_timeout+0x12>
    342e:	4c02      	ldr	r4, [pc, #8]	; (3438 <sys_clock_set_timeout+0x5c>)
    3430:	e7dd      	b.n	33ee <sys_clock_set_timeout+0x12>
    3432:	bf00      	nop
    3434:	200000c0 	.word	0x200000c0
    3438:	007fffff 	.word	0x007fffff
    343c:	00003011 	.word	0x00003011

00003440 <sys_clock_elapsed>:
{
    3440:	b508      	push	{r3, lr}
	return (z_nrf_rtc_timer_read() - last_count) / CYC_PER_TICK;
    3442:	f7ff fe4f 	bl	30e4 <z_nrf_rtc_timer_read>
    3446:	4b02      	ldr	r3, [pc, #8]	; (3450 <sys_clock_elapsed+0x10>)
    3448:	681b      	ldr	r3, [r3, #0]
}
    344a:	1ac0      	subs	r0, r0, r3
    344c:	bd08      	pop	{r3, pc}
    344e:	bf00      	nop
    3450:	200000c0 	.word	0x200000c0

00003454 <k_sys_fatal_error_handler>:
	defined(CONFIG_SPM_SERVICE_NS_HANDLER_FROM_SPM_FAULT)
	z_spm_ns_fatal_error_handler();
#endif

	if (IS_ENABLED(CONFIG_RESET_ON_FATAL_ERROR)) {
		LOG_ERR("Resetting system");
    3454:	4803      	ldr	r0, [pc, #12]	; (3464 <k_sys_fatal_error_handler+0x10>)
{
    3456:	b508      	push	{r3, lr}
		LOG_ERR("Resetting system");
    3458:	2145      	movs	r1, #69	; 0x45
    345a:	f002 fb5d 	bl	5b18 <z_log_minimal_printk>
		sys_arch_reboot(0);
    345e:	2000      	movs	r0, #0
    3460:	f7ff f888 	bl	2574 <sys_arch_reboot>
		for (;;) {
			/* Spin endlessly */
		}
	}

	CODE_UNREACHABLE;
    3464:	00007442 	.word	0x00007442

00003468 <boot_write_magic>:
    return rc;
}

int
boot_write_magic(const struct flash_area *fap)
{
    3468:	b530      	push	{r4, r5, lr}
    return flash_area_get_size(fap) - BOOT_MAGIC_SZ;
    346a:	6881      	ldr	r1, [r0, #8]
{
    346c:	b085      	sub	sp, #20
    return flash_area_get_size(fap) - BOOT_MAGIC_SZ;
    346e:	3910      	subs	r1, #16
     * returned by boot_magic_off() is the start of magic which is not the
     * start of the flash write boundary and thus writes to the magic will fail.
     * To account for this change, write to magic is first padded with 0xFF
     * before writing to the trailer.
     */
    pad_off = ALIGN_DOWN(off, BOOT_MAX_ALIGN);
    3470:	f021 0407 	bic.w	r4, r1, #7
{
    3474:	4605      	mov	r5, r0

    erased_val = flash_area_erased_val(fap);
    3476:	f002 fbb5 	bl	5be4 <flash_area_erased_val>

    memset(&magic[0], erased_val, sizeof(magic));
    347a:	2210      	movs	r2, #16
    erased_val = flash_area_erased_val(fap);
    347c:	4601      	mov	r1, r0
    memset(&magic[0], erased_val, sizeof(magic));
    347e:	4668      	mov	r0, sp
    3480:	f002 fc1f 	bl	5cc2 <memset>
    memcpy(&magic[BOOT_MAGIC_ALIGN_SIZE - BOOT_MAGIC_SZ], BOOT_IMG_MAGIC, BOOT_MAGIC_SZ);
    3484:	4907      	ldr	r1, [pc, #28]	; (34a4 <boot_write_magic+0x3c>)
    3486:	2210      	movs	r2, #16
    3488:	4668      	mov	r0, sp
    348a:	f002 fc0f 	bl	5cac <memcpy>

    BOOT_LOG_DBG("writing magic; fa_id=%d off=0x%lx (0x%lx)",
                 flash_area_get_id(fap), (unsigned long)off,
                 (unsigned long)(flash_area_get_off(fap) + off));
    rc = flash_area_write(fap, pad_off, &magic[0], BOOT_MAGIC_ALIGN_SIZE);
    348e:	2310      	movs	r3, #16
    3490:	466a      	mov	r2, sp
    3492:	4621      	mov	r1, r4
    3494:	4628      	mov	r0, r5
    3496:	f002 fb69 	bl	5b6c <flash_area_write>
    if (rc != 0) {
        return BOOT_EFLASH;
    }

    return 0;
}
    349a:	3800      	subs	r0, #0
    349c:	bf18      	it	ne
    349e:	2001      	movne	r0, #1
    34a0:	b005      	add	sp, #20
    34a2:	bd30      	pop	{r4, r5, pc}
    34a4:	000069d0 	.word	0x000069d0

000034a8 <boot_read_swap_state>:
{
    34a8:	b530      	push	{r4, r5, lr}
    34aa:	460c      	mov	r4, r1
    return flash_area_get_size(fap) - BOOT_MAGIC_SZ;
    34ac:	6881      	ldr	r1, [r0, #8]
{
    34ae:	b087      	sub	sp, #28
    rc = flash_area_read(fap, off, magic, BOOT_MAGIC_SZ);
    34b0:	2310      	movs	r3, #16
    34b2:	aa02      	add	r2, sp, #8
    34b4:	3910      	subs	r1, #16
{
    34b6:	4605      	mov	r5, r0
    rc = flash_area_read(fap, off, magic, BOOT_MAGIC_SZ);
    34b8:	f002 fb3c 	bl	5b34 <flash_area_read>
    if (rc < 0) {
    34bc:	2800      	cmp	r0, #0
    34be:	da02      	bge.n	34c6 <boot_read_swap_state+0x1e>
        return BOOT_EFLASH;
    34c0:	2001      	movs	r0, #1
}
    34c2:	b007      	add	sp, #28
    34c4:	bd30      	pop	{r4, r5, pc}
    if (buffer == NULL || len == 0) {
    34c6:	2210      	movs	r2, #16
    34c8:	a902      	add	r1, sp, #8
    34ca:	4628      	mov	r0, r5
    34cc:	f002 fe9e 	bl	620c <bootutil_buffer_is_erased.part.0>
    if (bootutil_buffer_is_erased(fap, magic, BOOT_MAGIC_SZ)) {
    34d0:	b390      	cbz	r0, 3538 <boot_read_swap_state+0x90>
        state->magic = BOOT_MAGIC_UNSET;
    34d2:	2303      	movs	r3, #3
        state->magic = boot_magic_decode(magic);
    34d4:	7023      	strb	r3, [r4, #0]
    off = boot_swap_info_off(fap);
    34d6:	4628      	mov	r0, r5
    34d8:	f002 fea9 	bl	622e <boot_swap_info_off>
    rc = flash_area_read(fap, off, &swap_info, sizeof swap_info);
    34dc:	2301      	movs	r3, #1
    off = boot_swap_info_off(fap);
    34de:	4601      	mov	r1, r0
    rc = flash_area_read(fap, off, &swap_info, sizeof swap_info);
    34e0:	f10d 0207 	add.w	r2, sp, #7
    34e4:	4628      	mov	r0, r5
    34e6:	f002 fb25 	bl	5b34 <flash_area_read>
    if (rc < 0) {
    34ea:	2800      	cmp	r0, #0
    34ec:	dbe8      	blt.n	34c0 <boot_read_swap_state+0x18>
    state->swap_type = BOOT_GET_SWAP_TYPE(swap_info);
    34ee:	f89d 3007 	ldrb.w	r3, [sp, #7]
    34f2:	f003 020f 	and.w	r2, r3, #15
    state->image_num = BOOT_GET_IMAGE_NUM(swap_info);
    34f6:	091b      	lsrs	r3, r3, #4
    state->swap_type = BOOT_GET_SWAP_TYPE(swap_info);
    34f8:	7062      	strb	r2, [r4, #1]
    state->image_num = BOOT_GET_IMAGE_NUM(swap_info);
    34fa:	7123      	strb	r3, [r4, #4]
    if (buffer == NULL || len == 0) {
    34fc:	2201      	movs	r2, #1
    34fe:	f10d 0107 	add.w	r1, sp, #7
    3502:	4628      	mov	r0, r5
    3504:	f002 fe82 	bl	620c <bootutil_buffer_is_erased.part.0>
    if (bootutil_buffer_is_erased(fap, &swap_info, sizeof swap_info) ||
    3508:	b910      	cbnz	r0, 3510 <boot_read_swap_state+0x68>
    350a:	7863      	ldrb	r3, [r4, #1]
    350c:	2b04      	cmp	r3, #4
    350e:	d903      	bls.n	3518 <boot_read_swap_state+0x70>
        state->swap_type = BOOT_SWAP_TYPE_NONE;
    3510:	2301      	movs	r3, #1
    3512:	7063      	strb	r3, [r4, #1]
        state->image_num = 0;
    3514:	2300      	movs	r3, #0
    3516:	7123      	strb	r3, [r4, #4]
    return ALIGN_DOWN(boot_magic_off(fap) - BOOT_MAX_ALIGN, BOOT_MAX_ALIGN);
    3518:	68aa      	ldr	r2, [r5, #8]
    351a:	3a18      	subs	r2, #24
    351c:	f022 0207 	bic.w	r2, r2, #7
    return boot_read_flag(fap, copy_done, boot_copy_done_off(fap));
    3520:	3a08      	subs	r2, #8
    3522:	1ca1      	adds	r1, r4, #2
    3524:	4628      	mov	r0, r5
    3526:	f002 fe9c 	bl	6262 <boot_read_flag>
    if (rc) {
    352a:	2800      	cmp	r0, #0
    352c:	d1c8      	bne.n	34c0 <boot_read_swap_state+0x18>
    return boot_read_image_ok(fap, &state->image_ok);
    352e:	1ce1      	adds	r1, r4, #3
    3530:	4628      	mov	r0, r5
    3532:	f002 fef0 	bl	6316 <boot_read_image_ok>
    3536:	e7c4      	b.n	34c2 <boot_read_swap_state+0x1a>
    if (memcmp(magic, BOOT_IMG_MAGIC, BOOT_MAGIC_SZ) == 0) {
    3538:	4904      	ldr	r1, [pc, #16]	; (354c <boot_read_swap_state+0xa4>)
    353a:	2210      	movs	r2, #16
    353c:	a802      	add	r0, sp, #8
    353e:	f002 fba4 	bl	5c8a <memcmp>
        return BOOT_MAGIC_GOOD;
    3542:	2800      	cmp	r0, #0
    3544:	bf14      	ite	ne
    3546:	2302      	movne	r3, #2
    3548:	2301      	moveq	r3, #1
    354a:	e7c3      	b.n	34d4 <boot_read_swap_state+0x2c>
    354c:	000069d0 	.word	0x000069d0

00003550 <boot_swap_type_multi>:
    return boot_write_trailer(fap, off, (const uint8_t *) &swap_info, 1);
}

int
boot_swap_type_multi(int image_index)
{
    3550:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
    3554:	b085      	sub	sp, #20
    3556:	4606      	mov	r6, r0

    rc = BOOT_HOOK_CALL(boot_read_swap_state_primary_slot_hook,
                        BOOT_HOOK_REGULAR, image_index, &primary_slot);
    if (rc == BOOT_HOOK_REGULAR)
    {
        rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_PRIMARY(image_index),
    3558:	4669      	mov	r1, sp
    355a:	2002      	movs	r0, #2
    355c:	f002 fee1 	bl	6322 <boot_read_swap_state_by_id>
                                        &primary_slot);
    }
    if (rc) {
    3560:	4605      	mov	r5, r0
    3562:	b118      	cbz	r0, 356c <boot_swap_type_multi+0x1c>
        return BOOT_SWAP_TYPE_PANIC;
    3564:	20ff      	movs	r0, #255	; 0xff
        }
    }

    BOOT_LOG_INF("Swap type: none");
    return BOOT_SWAP_TYPE_NONE;
}
    3566:	b005      	add	sp, #20
    3568:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
    rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_SECONDARY(image_index),
    356c:	a902      	add	r1, sp, #8
    356e:	2005      	movs	r0, #5
    3570:	f002 fed7 	bl	6322 <boot_read_swap_state_by_id>
    if (rc == BOOT_EFLASH) {
    3574:	2801      	cmp	r0, #1
    rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_SECONDARY(image_index),
    3576:	4604      	mov	r4, r0
    if (rc == BOOT_EFLASH) {
    3578:	d13f      	bne.n	35fa <boot_swap_type_multi+0xaa>
        BOOT_LOG_INF("Secondary image of image pair (%d.) "
    357a:	482d      	ldr	r0, [pc, #180]	; (3630 <boot_swap_type_multi+0xe0>)
    357c:	4632      	mov	r2, r6
    357e:	2149      	movs	r1, #73	; 0x49
    3580:	f002 faca 	bl	5b18 <z_log_minimal_printk>
        secondary_slot.magic = BOOT_MAGIC_UNSET;
    3584:	2303      	movs	r3, #3
    3586:	f88d 3008 	strb.w	r3, [sp, #8]
        secondary_slot.swap_type = BOOT_SWAP_TYPE_NONE;
    358a:	f88d 4009 	strb.w	r4, [sp, #9]
        secondary_slot.copy_done = BOOT_FLAG_UNSET;
    358e:	f88d 300a 	strb.w	r3, [sp, #10]
        secondary_slot.image_ok = BOOT_FLAG_UNSET;
    3592:	f88d 300b 	strb.w	r3, [sp, #11]
        secondary_slot.image_num = 0;
    3596:	f88d 500c 	strb.w	r5, [sp, #12]
        if (boot_magic_compatible_check(table->magic_primary_slot,
    359a:	f89d 5000 	ldrb.w	r5, [sp]
            boot_magic_compatible_check(table->magic_secondary_slot,
    359e:	f89d 6008 	ldrb.w	r6, [sp, #8]
                table->image_ok_primary_slot == primary_slot.image_ok) &&
    35a2:	f89d 7003 	ldrb.w	r7, [sp, #3]
                table->image_ok_secondary_slot == secondary_slot.image_ok) &&
    35a6:	f89d 800b 	ldrb.w	r8, [sp, #11]
                table->copy_done_primary_slot == primary_slot.copy_done)) {
    35aa:	f89d 9002 	ldrb.w	r9, [sp, #2]
    35ae:	4c21      	ldr	r4, [pc, #132]	; (3634 <boot_swap_type_multi+0xe4>)
    35b0:	2200      	movs	r2, #0
        if (boot_magic_compatible_check(table->magic_primary_slot,
    35b2:	7820      	ldrb	r0, [r4, #0]
    35b4:	4629      	mov	r1, r5
    35b6:	f002 fe40 	bl	623a <boot_magic_compatible_check>
    35ba:	b318      	cbz	r0, 3604 <boot_swap_type_multi+0xb4>
            boot_magic_compatible_check(table->magic_secondary_slot,
    35bc:	7860      	ldrb	r0, [r4, #1]
    35be:	4631      	mov	r1, r6
    35c0:	f002 fe3b 	bl	623a <boot_magic_compatible_check>
                                        primary_slot.magic) &&
    35c4:	b1f0      	cbz	r0, 3604 <boot_swap_type_multi+0xb4>
            (table->image_ok_primary_slot == BOOT_FLAG_ANY   ||
    35c6:	78a3      	ldrb	r3, [r4, #2]
                                        secondary_slot.magic) &&
    35c8:	2b04      	cmp	r3, #4
    35ca:	d001      	beq.n	35d0 <boot_swap_type_multi+0x80>
            (table->image_ok_primary_slot == BOOT_FLAG_ANY   ||
    35cc:	42bb      	cmp	r3, r7
    35ce:	d119      	bne.n	3604 <boot_swap_type_multi+0xb4>
            (table->image_ok_secondary_slot == BOOT_FLAG_ANY ||
    35d0:	78e3      	ldrb	r3, [r4, #3]
                table->image_ok_primary_slot == primary_slot.image_ok) &&
    35d2:	2b04      	cmp	r3, #4
    35d4:	d001      	beq.n	35da <boot_swap_type_multi+0x8a>
            (table->image_ok_secondary_slot == BOOT_FLAG_ANY ||
    35d6:	4543      	cmp	r3, r8
    35d8:	d114      	bne.n	3604 <boot_swap_type_multi+0xb4>
            (table->copy_done_primary_slot == BOOT_FLAG_ANY  ||
    35da:	7923      	ldrb	r3, [r4, #4]
                table->image_ok_secondary_slot == secondary_slot.image_ok) &&
    35dc:	2b04      	cmp	r3, #4
    35de:	d10f      	bne.n	3600 <boot_swap_type_multi+0xb0>
            BOOT_LOG_INF("Swap type: %s",
    35e0:	7963      	ldrb	r3, [r4, #5]
    35e2:	2b02      	cmp	r3, #2
    35e4:	d119      	bne.n	361a <boot_swap_type_multi+0xca>
    35e6:	4a14      	ldr	r2, [pc, #80]	; (3638 <boot_swap_type_multi+0xe8>)
    35e8:	4814      	ldr	r0, [pc, #80]	; (363c <boot_swap_type_multi+0xec>)
    35ea:	2149      	movs	r1, #73	; 0x49
    35ec:	f002 fa94 	bl	5b18 <z_log_minimal_printk>
            if (table->swap_type != BOOT_SWAP_TYPE_TEST &&
    35f0:	7960      	ldrb	r0, [r4, #5]
    35f2:	1e83      	subs	r3, r0, #2
    35f4:	2b02      	cmp	r3, #2
    35f6:	d9b6      	bls.n	3566 <boot_swap_type_multi+0x16>
    35f8:	e7b4      	b.n	3564 <boot_swap_type_multi+0x14>
    } else if (rc) {
    35fa:	2800      	cmp	r0, #0
    35fc:	d0cd      	beq.n	359a <boot_swap_type_multi+0x4a>
    35fe:	e7b1      	b.n	3564 <boot_swap_type_multi+0x14>
            (table->copy_done_primary_slot == BOOT_FLAG_ANY  ||
    3600:	454b      	cmp	r3, r9
    3602:	d0ed      	beq.n	35e0 <boot_swap_type_multi+0x90>
    for (i = 0; i < BOOT_SWAP_TABLES_COUNT; i++) {
    3604:	3201      	adds	r2, #1
    3606:	2a03      	cmp	r2, #3
    3608:	f104 0406 	add.w	r4, r4, #6
    360c:	d1d1      	bne.n	35b2 <boot_swap_type_multi+0x62>
    BOOT_LOG_INF("Swap type: none");
    360e:	480c      	ldr	r0, [pc, #48]	; (3640 <boot_swap_type_multi+0xf0>)
    3610:	2149      	movs	r1, #73	; 0x49
    3612:	f002 fa81 	bl	5b18 <z_log_minimal_printk>
    return BOOT_SWAP_TYPE_NONE;
    3616:	2001      	movs	r0, #1
    3618:	e7a5      	b.n	3566 <boot_swap_type_multi+0x16>
            BOOT_LOG_INF("Swap type: %s",
    361a:	2b03      	cmp	r3, #3
    361c:	d005      	beq.n	362a <boot_swap_type_multi+0xda>
    361e:	4a09      	ldr	r2, [pc, #36]	; (3644 <boot_swap_type_multi+0xf4>)
    3620:	4909      	ldr	r1, [pc, #36]	; (3648 <boot_swap_type_multi+0xf8>)
    3622:	2b04      	cmp	r3, #4
    3624:	bf18      	it	ne
    3626:	460a      	movne	r2, r1
    3628:	e7de      	b.n	35e8 <boot_swap_type_multi+0x98>
    362a:	4a08      	ldr	r2, [pc, #32]	; (364c <boot_swap_type_multi+0xfc>)
    362c:	e7dc      	b.n	35e8 <boot_swap_type_multi+0x98>
    362e:	bf00      	nop
    3630:	00007487 	.word	0x00007487
    3634:	000074fa 	.word	0x000074fa
    3638:	0000746b 	.word	0x0000746b
    363c:	000074d2 	.word	0x000074d2
    3640:	000074e5 	.word	0x000074e5
    3644:	00007464 	.word	0x00007464
    3648:	00007475 	.word	0x00007475
    364c:	00007470 	.word	0x00007470

00003650 <nrf52_errata_16>:
    #ifndef NRF52_SERIES
        return false;
    #else
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
    3650:	f04f 4370 	mov.w	r3, #4026531840	; 0xf0000000
    3654:	f893 2fe0 	ldrb.w	r2, [r3, #4064]	; 0xfe0
            uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
        #endif
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            if (var1 == 0x06)
    3658:	2a06      	cmp	r2, #6
    365a:	d109      	bne.n	3670 <nrf52_errata_16+0x20>
            uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
    365c:	f8d3 3fe8 	ldr.w	r3, [r3, #4072]	; 0xfe8
    3660:	f3c3 1303 	ubfx	r3, r3, #4, #4
    3664:	3b03      	subs	r3, #3
    3666:	2b04      	cmp	r3, #4
    3668:	d802      	bhi.n	3670 <nrf52_errata_16+0x20>
    366a:	4a02      	ldr	r2, [pc, #8]	; (3674 <nrf52_errata_16+0x24>)
    366c:	5cd0      	ldrb	r0, [r2, r3]
    366e:	4770      	bx	lr
                    default:
                        return false;
                }
            }
        #endif
        return false;
    3670:	2000      	movs	r0, #0
    #endif
}
    3672:	4770      	bx	lr
    3674:	0000751b 	.word	0x0000751b

00003678 <nvmc_wait>:

/* -- NVMC utility functions -- */
/* Waits until NVMC is done with the current pending action */
void nvmc_wait(void)
{
    while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
    3678:	4a02      	ldr	r2, [pc, #8]	; (3684 <nvmc_wait+0xc>)
    367a:	f8d2 3400 	ldr.w	r3, [r2, #1024]	; 0x400
    367e:	2b00      	cmp	r3, #0
    3680:	d0fb      	beq.n	367a <nvmc_wait+0x2>
}
    3682:	4770      	bx	lr
    3684:	4001e000 	.word	0x4001e000

00003688 <SystemInit>:
{
    SystemCoreClock = __SYSTEM_CLOCK_64M;
}

void SystemInit(void)
{
    3688:	b510      	push	{r4, lr}
    #endif

    #if NRF52_ERRATA_12_ENABLE_WORKAROUND
        /* Workaround for Errata 12 "COMP: Reference ladder not correctly calibrated" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp */
        if (nrf52_errata_12()){
    368a:	f002 fe6f 	bl	636c <nrf52_errata_108>
    368e:	b140      	cbz	r0, 36a2 <SystemInit+0x1a>
            *(volatile uint32_t *)0x40013540 = (*(uint32_t *)0x10000324 & 0x00001F00) >> 8;
    3690:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    3694:	4a90      	ldr	r2, [pc, #576]	; (38d8 <SystemInit+0x250>)
    3696:	f8d3 3324 	ldr.w	r3, [r3, #804]	; 0x324
    369a:	f3c3 2304 	ubfx	r3, r3, #8, #5
    369e:	f8c2 3540 	str.w	r3, [r2, #1344]	; 0x540
    #endif

    #if NRF52_ERRATA_16_ENABLE_WORKAROUND
        /* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp */
        if (nrf52_errata_16()){
    36a2:	f7ff ffd5 	bl	3650 <nrf52_errata_16>
    36a6:	b110      	cbz	r0, 36ae <SystemInit+0x26>
            *(volatile uint32_t *)0x4007C074 = 3131961357ul;
    36a8:	4b8c      	ldr	r3, [pc, #560]	; (38dc <SystemInit+0x254>)
    36aa:	4a8d      	ldr	r2, [pc, #564]	; (38e0 <SystemInit+0x258>)
    36ac:	675a      	str	r2, [r3, #116]	; 0x74
    #endif

    #if NRF52_ERRATA_31_ENABLE_WORKAROUND
        /* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp */
        if (nrf52_errata_31()){
    36ae:	f002 fe5d 	bl	636c <nrf52_errata_108>
    36b2:	b148      	cbz	r0, 36c8 <SystemInit+0x40>
            *(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13;
    36b4:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    36b8:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    36bc:	f8d3 3244 	ldr.w	r3, [r3, #580]	; 0x244
    36c0:	f3c3 3342 	ubfx	r3, r3, #13, #3
    36c4:	f8c2 353c 	str.w	r3, [r2, #1340]	; 0x53c
    #endif

    #if NRF52_ERRATA_32_ENABLE_WORKAROUND
        /* Workaround for Errata 32 "DIF: Debug session automatically enables TracePort pins" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp */
        if (nrf52_errata_32()){
    36c8:	f7ff ffc2 	bl	3650 <nrf52_errata_16>
    36cc:	b130      	cbz	r0, 36dc <SystemInit+0x54>
            CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk;
    36ce:	4a85      	ldr	r2, [pc, #532]	; (38e4 <SystemInit+0x25c>)
    36d0:	f8d2 30fc 	ldr.w	r3, [r2, #252]	; 0xfc
    36d4:	f023 7380 	bic.w	r3, r3, #16777216	; 0x1000000
    36d8:	f8c2 30fc 	str.w	r3, [r2, #252]	; 0xfc
    #endif

    #if NRF52_ERRATA_36_ENABLE_WORKAROUND
        /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_36()){
    36dc:	f002 fe46 	bl	636c <nrf52_errata_108>
    36e0:	b140      	cbz	r0, 36f4 <SystemInit+0x6c>
            NRF_CLOCK->EVENTS_DONE = 0;
    36e2:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    36e6:	2200      	movs	r2, #0
    36e8:	f8c3 210c 	str.w	r2, [r3, #268]	; 0x10c
            NRF_CLOCK->EVENTS_CTTO = 0;
    36ec:	f8c3 2110 	str.w	r2, [r3, #272]	; 0x110
            NRF_CLOCK->CTIV = 0;
    36f0:	f8c3 2538 	str.w	r2, [r3, #1336]	; 0x538
    #endif

    #if NRF52_ERRATA_37_ENABLE_WORKAROUND
        /* Workaround for Errata 37 "RADIO: Encryption engine is slow by default" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_37()){
    36f4:	f7ff ffac 	bl	3650 <nrf52_errata_16>
    36f8:	b120      	cbz	r0, 3704 <SystemInit+0x7c>
            *(volatile uint32_t *)0x400005A0 = 0x3;
    36fa:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    36fe:	2203      	movs	r2, #3
    3700:	f8c3 25a0 	str.w	r2, [r3, #1440]	; 0x5a0
    #endif

    #if NRF52_ERRATA_57_ENABLE_WORKAROUND
        /* Workaround for Errata 57 "NFCT: NFC Modulation amplitude" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_57()){
    3704:	f7ff ffa4 	bl	3650 <nrf52_errata_16>
    3708:	b160      	cbz	r0, 3724 <SystemInit+0x9c>
            *(volatile uint32_t *)0x40005610 = 0x00000005;
    370a:	4b77      	ldr	r3, [pc, #476]	; (38e8 <SystemInit+0x260>)
    370c:	2205      	movs	r2, #5
    370e:	f8c3 2610 	str.w	r2, [r3, #1552]	; 0x610
            *(volatile uint32_t *)0x40005688 = 0x00000001;
    3712:	2201      	movs	r2, #1
    3714:	f8c3 2688 	str.w	r2, [r3, #1672]	; 0x688
            *(volatile uint32_t *)0x40005618 = 0x00000000;
    3718:	2200      	movs	r2, #0
    371a:	f8c3 2618 	str.w	r2, [r3, #1560]	; 0x618
            *(volatile uint32_t *)0x40005614 = 0x0000003F;
    371e:	223f      	movs	r2, #63	; 0x3f
    3720:	f8c3 2614 	str.w	r2, [r3, #1556]	; 0x614
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            uint32_t var1;
            uint32_t var2;

            if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF)
    3724:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    3728:	f8d3 2130 	ldr.w	r2, [r3, #304]	; 0x130
    372c:	1c51      	adds	r1, r2, #1
            {
                var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
    372e:	bf09      	itett	eq
    3730:	f04f 4370 	moveq.w	r3, #4026531840	; 0xf0000000
                var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
            }
            else
            {
                var1 = *(uint32_t *)0x10000130ul;
                var2 = *(uint32_t *)0x10000134ul;
    3734:	f8d3 3134 	ldrne.w	r3, [r3, #308]	; 0x134
                var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
    3738:	f893 2fe0 	ldrbeq.w	r2, [r3, #4064]	; 0xfe0
                var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
    373c:	f8d3 3fe8 	ldreq.w	r3, [r3, #4072]	; 0xfe8
    3740:	bf08      	it	eq
    3742:	f3c3 1303 	ubfxeq	r3, r3, #4, #4
            uint32_t var1 = *(uint32_t *)0x10000130ul;
            uint32_t var2 = *(uint32_t *)0x10000134ul;
        #endif
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            if (var1 == 0x06)
    3746:	2a06      	cmp	r2, #6
    3748:	d14d      	bne.n	37e6 <SystemInit+0x15e>
            {
                switch(var2)
    374a:	3b03      	subs	r3, #3
    374c:	2b04      	cmp	r3, #4
    374e:	d803      	bhi.n	3758 <SystemInit+0xd0>
    #endif

    #if NRF52_ERRATA_66_ENABLE_WORKAROUND
        /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_66()){
    3750:	4a66      	ldr	r2, [pc, #408]	; (38ec <SystemInit+0x264>)
    3752:	5cd3      	ldrb	r3, [r2, r3]
    3754:	2b00      	cmp	r3, #0
    3756:	d046      	beq.n	37e6 <SystemInit+0x15e>
            NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
    3758:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
    375c:	4b64      	ldr	r3, [pc, #400]	; (38f0 <SystemInit+0x268>)
    375e:	f8d2 1404 	ldr.w	r1, [r2, #1028]	; 0x404
    3762:	f8c3 1520 	str.w	r1, [r3, #1312]	; 0x520
            NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
    3766:	f8d2 1408 	ldr.w	r1, [r2, #1032]	; 0x408
    376a:	f8c3 1524 	str.w	r1, [r3, #1316]	; 0x524
            NRF_TEMP->A2 = NRF_FICR->TEMP.A2;
    376e:	f8d2 140c 	ldr.w	r1, [r2, #1036]	; 0x40c
    3772:	f8c3 1528 	str.w	r1, [r3, #1320]	; 0x528
            NRF_TEMP->A3 = NRF_FICR->TEMP.A3;
    3776:	f8d2 1410 	ldr.w	r1, [r2, #1040]	; 0x410
    377a:	f8c3 152c 	str.w	r1, [r3, #1324]	; 0x52c
            NRF_TEMP->A4 = NRF_FICR->TEMP.A4;
    377e:	f8d2 1414 	ldr.w	r1, [r2, #1044]	; 0x414
    3782:	f8c3 1530 	str.w	r1, [r3, #1328]	; 0x530
            NRF_TEMP->A5 = NRF_FICR->TEMP.A5;
    3786:	f8d2 1418 	ldr.w	r1, [r2, #1048]	; 0x418
    378a:	f8c3 1534 	str.w	r1, [r3, #1332]	; 0x534
            NRF_TEMP->B0 = NRF_FICR->TEMP.B0;
    378e:	f8d2 141c 	ldr.w	r1, [r2, #1052]	; 0x41c
    3792:	f8c3 1540 	str.w	r1, [r3, #1344]	; 0x540
            NRF_TEMP->B1 = NRF_FICR->TEMP.B1;
    3796:	f8d2 1420 	ldr.w	r1, [r2, #1056]	; 0x420
    379a:	f8c3 1544 	str.w	r1, [r3, #1348]	; 0x544
            NRF_TEMP->B2 = NRF_FICR->TEMP.B2;
    379e:	f8d2 1424 	ldr.w	r1, [r2, #1060]	; 0x424
    37a2:	f8c3 1548 	str.w	r1, [r3, #1352]	; 0x548
            NRF_TEMP->B3 = NRF_FICR->TEMP.B3;
    37a6:	f8d2 1428 	ldr.w	r1, [r2, #1064]	; 0x428
    37aa:	f8c3 154c 	str.w	r1, [r3, #1356]	; 0x54c
            NRF_TEMP->B4 = NRF_FICR->TEMP.B4;
    37ae:	f8d2 142c 	ldr.w	r1, [r2, #1068]	; 0x42c
    37b2:	f8c3 1550 	str.w	r1, [r3, #1360]	; 0x550
            NRF_TEMP->B5 = NRF_FICR->TEMP.B5;
    37b6:	f8d2 1430 	ldr.w	r1, [r2, #1072]	; 0x430
    37ba:	f8c3 1554 	str.w	r1, [r3, #1364]	; 0x554
            NRF_TEMP->T0 = NRF_FICR->TEMP.T0;
    37be:	f8d2 1434 	ldr.w	r1, [r2, #1076]	; 0x434
    37c2:	f8c3 1560 	str.w	r1, [r3, #1376]	; 0x560
            NRF_TEMP->T1 = NRF_FICR->TEMP.T1;
    37c6:	f8d2 1438 	ldr.w	r1, [r2, #1080]	; 0x438
    37ca:	f8c3 1564 	str.w	r1, [r3, #1380]	; 0x564
            NRF_TEMP->T2 = NRF_FICR->TEMP.T2;
    37ce:	f8d2 143c 	ldr.w	r1, [r2, #1084]	; 0x43c
    37d2:	f8c3 1568 	str.w	r1, [r3, #1384]	; 0x568
            NRF_TEMP->T3 = NRF_FICR->TEMP.T3;
    37d6:	f8d2 1440 	ldr.w	r1, [r2, #1088]	; 0x440
    37da:	f8c3 156c 	str.w	r1, [r3, #1388]	; 0x56c
            NRF_TEMP->T4 = NRF_FICR->TEMP.T4;
    37de:	f8d2 2444 	ldr.w	r2, [r2, #1092]	; 0x444
    37e2:	f8c3 2570 	str.w	r2, [r3, #1392]	; 0x570
    #endif

    #if NRF52_ERRATA_108_ENABLE_WORKAROUND
        /* Workaround for Errata 108 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_108()){
    37e6:	f002 fdc1 	bl	636c <nrf52_errata_108>
    37ea:	b148      	cbz	r0, 3800 <SystemInit+0x178>
            *(volatile uint32_t *)0x40000EE4ul = *(volatile uint32_t *)0x10000258ul & 0x0000004Ful;
    37ec:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    37f0:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    37f4:	f8d3 3258 	ldr.w	r3, [r3, #600]	; 0x258
    37f8:	f003 034f 	and.w	r3, r3, #79	; 0x4f
    37fc:	f8c2 3ee4 	str.w	r3, [r2, #3812]	; 0xee4
    #endif

    #if NRF52_ERRATA_136_ENABLE_WORKAROUND
        /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_136()){
    3800:	f002 fdb4 	bl	636c <nrf52_errata_108>
    3804:	b148      	cbz	r0, 381a <SystemInit+0x192>
            if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){
    3806:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    380a:	f8d3 2400 	ldr.w	r2, [r3, #1024]	; 0x400
    380e:	07d2      	lsls	r2, r2, #31
                NRF_POWER->RESETREAS =  ~POWER_RESETREAS_RESETPIN_Msk;
    3810:	bf44      	itt	mi
    3812:	f06f 0201 	mvnmi.w	r2, #1
    3816:	f8c3 2400 	strmi.w	r2, [r3, #1024]	; 0x400
    #ifndef NRF52_SERIES
        return false;
    #else
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    381a:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
            uint32_t var2 = *(uint32_t *)0x10000134ul;
        #endif
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            if (var1 == 0x06)
    381e:	f8d3 2130 	ldr.w	r2, [r3, #304]	; 0x130
    3822:	2a06      	cmp	r2, #6
    3824:	d126      	bne.n	3874 <SystemInit+0x1ec>
            {
                switch(var2)
    3826:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
    382a:	3b03      	subs	r3, #3
    382c:	2b04      	cmp	r3, #4
    382e:	d802      	bhi.n	3836 <SystemInit+0x1ae>
    #endif

    #if NRF52_ERRATA_182_ENABLE_WORKAROUND
        /* Workaround for Errata 182 "RADIO: Fixes for anomalies #102, #106, and #107 do not take effect" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_182()){
    3830:	4a30      	ldr	r2, [pc, #192]	; (38f4 <SystemInit+0x26c>)
    3832:	5cd3      	ldrb	r3, [r2, r3]
    3834:	b163      	cbz	r3, 3850 <SystemInit+0x1c8>
            *(volatile uint32_t *) 0x4000173C |= (0x1 << 10);
    3836:	4a30      	ldr	r2, [pc, #192]	; (38f8 <SystemInit+0x270>)
    3838:	f8d2 373c 	ldr.w	r3, [r2, #1852]	; 0x73c
    383c:	f443 6380 	orr.w	r3, r3, #1024	; 0x400
    3840:	f8c2 373c 	str.w	r3, [r2, #1852]	; 0x73c
         || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\
         || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\
         || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    3844:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
            uint32_t var2 = *(uint32_t *)0x10000134ul;
        #endif
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            if (var1 == 0x06)
    3848:	f8d3 3130 	ldr.w	r3, [r3, #304]	; 0x130
    384c:	2b06      	cmp	r3, #6
    384e:	d111      	bne.n	3874 <SystemInit+0x1ec>
            uint32_t var2 = *(uint32_t *)0x10000134ul;
    3850:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    3854:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
    3858:	3b03      	subs	r3, #3
    385a:	2b04      	cmp	r3, #4
    385c:	d802      	bhi.n	3864 <SystemInit+0x1dc>
            {
                /* Prevent processor from unlocking APPROTECT soft branch after this point. */
                NRF_APPROTECT->FORCEPROTECT = APPROTECT_FORCEPROTECT_FORCEPROTECT_Force;
            }
        #else
            if (nrf52_configuration_249())
    385e:	4a27      	ldr	r2, [pc, #156]	; (38fc <SystemInit+0x274>)
    3860:	5cd3      	ldrb	r3, [r2, r3]
    3862:	b13b      	cbz	r3, 3874 <SystemInit+0x1ec>
            {
                /* Load APPROTECT soft branch from UICR.
                   If UICR->APPROTECT is disabled, POWER->APPROTECT will be disabled. */
                NRF_APPROTECT->DISABLE = NRF_UICR->APPROTECT;
    3864:	f04f 2310 	mov.w	r3, #268439552	; 0x10001000
    3868:	f8d3 2208 	ldr.w	r2, [r3, #520]	; 0x208
    386c:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    3870:	f8c3 2558 	str.w	r2, [r3, #1368]	; 0x558

    /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
      defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
      reserved for PinReset and not available as normal GPIO. */
    #if defined (CONFIG_GPIO_AS_PINRESET)
        if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
    3874:	f04f 2310 	mov.w	r3, #268439552	; 0x10001000
    3878:	f8d3 2200 	ldr.w	r2, [r3, #512]	; 0x200
    387c:	2a00      	cmp	r2, #0
    387e:	db03      	blt.n	3888 <SystemInit+0x200>
            ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
    3880:	f8d3 3204 	ldr.w	r3, [r3, #516]	; 0x204
        if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
    3884:	2b00      	cmp	r3, #0
    3886:	da22      	bge.n	38ce <SystemInit+0x246>
    NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
    3888:	491d      	ldr	r1, [pc, #116]	; (3900 <SystemInit+0x278>)
    388a:	2301      	movs	r3, #1
            nvmc_config(NVMC_CONFIG_WEN_Wen);
            NRF_UICR->PSELRESET[0] = RESET_PIN;
    388c:	f04f 2010 	mov.w	r0, #268439552	; 0x10001000
    NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
    3890:	f8c1 3504 	str.w	r3, [r1, #1284]	; 0x504
            NRF_UICR->PSELRESET[0] = RESET_PIN;
    3894:	2415      	movs	r4, #21
    nvmc_wait();
    3896:	f7ff feef 	bl	3678 <nvmc_wait>
            NRF_UICR->PSELRESET[0] = RESET_PIN;
    389a:	f8c0 4200 	str.w	r4, [r0, #512]	; 0x200
            nvmc_wait();
    389e:	f7ff feeb 	bl	3678 <nvmc_wait>
            NRF_UICR->PSELRESET[1] = RESET_PIN;
    38a2:	f8c0 4204 	str.w	r4, [r0, #516]	; 0x204
            nvmc_wait();
    38a6:	f7ff fee7 	bl	3678 <nvmc_wait>
    NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
    38aa:	2300      	movs	r3, #0
    38ac:	f8c1 3504 	str.w	r3, [r1, #1284]	; 0x504
    nvmc_wait();
    38b0:	f7ff fee2 	bl	3678 <nvmc_wait>
  __ASM volatile ("dsb 0xF":::"memory");
    38b4:	f3bf 8f4f 	dsb	sy
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    38b8:	490a      	ldr	r1, [pc, #40]	; (38e4 <SystemInit+0x25c>)
    38ba:	4b12      	ldr	r3, [pc, #72]	; (3904 <SystemInit+0x27c>)
    38bc:	68ca      	ldr	r2, [r1, #12]
    38be:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    38c2:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    38c4:	60cb      	str	r3, [r1, #12]
    38c6:	f3bf 8f4f 	dsb	sy
    __NOP();
    38ca:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    38cc:	e7fd      	b.n	38ca <SystemInit+0x242>
    SystemCoreClock = __SYSTEM_CLOCK_64M;
    38ce:	4b0e      	ldr	r3, [pc, #56]	; (3908 <SystemInit+0x280>)
    38d0:	4a0e      	ldr	r2, [pc, #56]	; (390c <SystemInit+0x284>)
    38d2:	601a      	str	r2, [r3, #0]
            NVIC_SystemReset();
        }
    #endif

    SystemCoreClockUpdate();
}
    38d4:	bd10      	pop	{r4, pc}
    38d6:	bf00      	nop
    38d8:	40013000 	.word	0x40013000
    38dc:	4007c000 	.word	0x4007c000
    38e0:	baadf00d 	.word	0xbaadf00d
    38e4:	e000ed00 	.word	0xe000ed00
    38e8:	40005000 	.word	0x40005000
    38ec:	0000750c 	.word	0x0000750c
    38f0:	4000c000 	.word	0x4000c000
    38f4:	00007511 	.word	0x00007511
    38f8:	40001000 	.word	0x40001000
    38fc:	00007516 	.word	0x00007516
    3900:	4001e000 	.word	0x4001e000
    3904:	05fa0004 	.word	0x05fa0004
    3908:	2000002c 	.word	0x2000002c
    390c:	03d09000 	.word	0x03d09000

00003910 <nrfx_flag32_alloc>:
{
    return (mask & NRFX_BIT(bitpos)) ? false : true;
}

nrfx_err_t nrfx_flag32_alloc(nrfx_atomic_t * p_mask, uint8_t *p_flag)
{
    3910:	b570      	push	{r4, r5, r6, lr}
        idx = 31 - NRF_CLZ(prev_mask);
        if (idx < 0) {
            return NRFX_ERROR_NO_MEM;
        }

        new_mask = prev_mask & ~NRFX_BIT(idx);
    3912:	2501      	movs	r5, #1
        prev_mask = *p_mask;
    3914:	6802      	ldr	r2, [r0, #0]
        idx = 31 - NRF_CLZ(prev_mask);
    3916:	fab2 f382 	clz	r3, r2
    391a:	f1c3 031f 	rsb	r3, r3, #31
        if (idx < 0) {
    391e:	1c5e      	adds	r6, r3, #1
        idx = 31 - NRF_CLZ(prev_mask);
    3920:	b2dc      	uxtb	r4, r3
        if (idx < 0) {
    3922:	d014      	beq.n	394e <nrfx_flag32_alloc+0x3e>
	return __atomic_compare_exchange_n(target, &old_value, new_value,
    3924:	f3bf 8f5b 	dmb	ish
        new_mask = prev_mask & ~NRFX_BIT(idx);
    3928:	fa05 f303 	lsl.w	r3, r5, r3
    392c:	ea22 0303 	bic.w	r3, r2, r3
    3930:	e850 6f00 	ldrex	r6, [r0]
    3934:	4296      	cmp	r6, r2
    3936:	d104      	bne.n	3942 <nrfx_flag32_alloc+0x32>
    3938:	e840 3c00 	strex	ip, r3, [r0]
    393c:	f1bc 0f00 	cmp.w	ip, #0
    3940:	d1f6      	bne.n	3930 <nrfx_flag32_alloc+0x20>
    3942:	f3bf 8f5b 	dmb	ish
    } while (!NRFX_ATOMIC_CAS(p_mask, prev_mask, new_mask));
    3946:	d1e5      	bne.n	3914 <nrfx_flag32_alloc+0x4>

    *p_flag = idx;

    return NRFX_SUCCESS;
    3948:	4802      	ldr	r0, [pc, #8]	; (3954 <nrfx_flag32_alloc+0x44>)
    *p_flag = idx;
    394a:	700c      	strb	r4, [r1, #0]
}
    394c:	bd70      	pop	{r4, r5, r6, pc}
            return NRFX_ERROR_NO_MEM;
    394e:	4802      	ldr	r0, [pc, #8]	; (3958 <nrfx_flag32_alloc+0x48>)
    3950:	e7fc      	b.n	394c <nrfx_flag32_alloc+0x3c>
    3952:	bf00      	nop
    3954:	0bad0000 	.word	0x0bad0000
    3958:	0bad0002 	.word	0x0bad0002

0000395c <nrfx_flag32_free>:

nrfx_err_t nrfx_flag32_free(nrfx_atomic_t * p_mask, uint8_t flag)
{
    uint32_t new_mask, prev_mask;

    if ((NRFX_BIT(flag) & *p_mask))
    395c:	6803      	ldr	r3, [r0, #0]
    395e:	40cb      	lsrs	r3, r1
    3960:	07db      	lsls	r3, r3, #31
{
    3962:	b510      	push	{r4, lr}
    if ((NRFX_BIT(flag) & *p_mask))
    3964:	d415      	bmi.n	3992 <nrfx_flag32_free+0x36>
        return NRFX_ERROR_INVALID_PARAM;
    }

    do {
        prev_mask = *p_mask;
        new_mask = prev_mask | NRFX_BIT(flag);
    3966:	2301      	movs	r3, #1
    3968:	fa03 f101 	lsl.w	r1, r3, r1
        prev_mask = *p_mask;
    396c:	6803      	ldr	r3, [r0, #0]
    396e:	f3bf 8f5b 	dmb	ish
        new_mask = prev_mask | NRFX_BIT(flag);
    3972:	ea41 0203 	orr.w	r2, r1, r3
    3976:	e850 4f00 	ldrex	r4, [r0]
    397a:	429c      	cmp	r4, r3
    397c:	d104      	bne.n	3988 <nrfx_flag32_free+0x2c>
    397e:	e840 2c00 	strex	ip, r2, [r0]
    3982:	f1bc 0f00 	cmp.w	ip, #0
    3986:	d1f6      	bne.n	3976 <nrfx_flag32_free+0x1a>
    3988:	f3bf 8f5b 	dmb	ish
    } while (!NRFX_ATOMIC_CAS(p_mask, prev_mask, new_mask));
    398c:	d1ee      	bne.n	396c <nrfx_flag32_free+0x10>

    return NRFX_SUCCESS;
    398e:	4802      	ldr	r0, [pc, #8]	; (3998 <nrfx_flag32_free+0x3c>)
}
    3990:	bd10      	pop	{r4, pc}
        return NRFX_ERROR_INVALID_PARAM;
    3992:	4802      	ldr	r0, [pc, #8]	; (399c <nrfx_flag32_free+0x40>)
    3994:	e7fc      	b.n	3990 <nrfx_flag32_free+0x34>
    3996:	bf00      	nop
    3998:	0bad0000 	.word	0x0bad0000
    399c:	0bad0004 	.word	0x0bad0004

000039a0 <clock_stop>:
    CoreDebug->DEMCR = core_debug;
}
#endif // NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_132)

static void clock_stop(nrf_clock_domain_t domain)
{
    39a0:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
    switch (domain)
    39a2:	4604      	mov	r4, r0
    39a4:	b118      	cbz	r0, 39ae <clock_stop+0xe>
    39a6:	2801      	cmp	r0, #1
    39a8:	d029      	beq.n	39fe <clock_stop+0x5e>
    if (domain == NRF_CLOCK_DOMAIN_HFCLK)
    {
            m_clock_cb.hfclk_started = false;
    }
#endif
}
    39aa:	b003      	add	sp, #12
    39ac:	bdf0      	pop	{r4, r5, r6, r7, pc}
    p_reg->INTENCLR = mask;
    39ae:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    39b2:	2202      	movs	r2, #2
    39b4:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    39b8:	f8c3 0104 	str.w	r0, [r3, #260]	; 0x104
    39bc:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    39c0:	2201      	movs	r2, #1
    39c2:	60da      	str	r2, [r3, #12]
    nrf_clock_hfclk_t clk_src = NRF_CLOCK_HFCLK_HIGH_ACCURACY;
    39c4:	2301      	movs	r3, #1
    nrf_clock_hfclk_t *p_clk_src = (domain == NRF_CLOCK_DOMAIN_HFCLK) ? &clk_src : NULL;
    39c6:	429c      	cmp	r4, r3
    nrf_clock_hfclk_t clk_src = NRF_CLOCK_HFCLK_HIGH_ACCURACY;
    39c8:	f88d 3007 	strb.w	r3, [sp, #7]
    nrf_clock_hfclk_t *p_clk_src = (domain == NRF_CLOCK_DOMAIN_HFCLK) ? &clk_src : NULL;
    39cc:	bf14      	ite	ne
    39ce:	2500      	movne	r5, #0
    39d0:	f10d 0507 	addeq.w	r5, sp, #7
    39d4:	f242 7710 	movw	r7, #10000	; 0x2710
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    39d8:	f04f 4680 	mov.w	r6, #1073741824	; 0x40000000
    switch (domain)
    39dc:	b1d4      	cbz	r4, 3a14 <clock_stop+0x74>
    39de:	2c01      	cmp	r4, #1
    39e0:	d1e3      	bne.n	39aa <clock_stop+0xa>
            if (p_clk_src != NULL)
    39e2:	b125      	cbz	r5, 39ee <clock_stop+0x4e>
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    39e4:	f8d6 340c 	ldr.w	r3, [r6, #1036]	; 0x40c
    39e8:	f003 0301 	and.w	r3, r3, #1
                (*(nrf_clock_hfclk_t *)p_clk_src) =
    39ec:	702b      	strb	r3, [r5, #0]
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    39ee:	f8d6 340c 	ldr.w	r3, [r6, #1036]	; 0x40c
    39f2:	03db      	lsls	r3, r3, #15
    39f4:	d418      	bmi.n	3a28 <clock_stop+0x88>
            m_clock_cb.hfclk_started = false;
    39f6:	4b13      	ldr	r3, [pc, #76]	; (3a44 <clock_stop+0xa4>)
    39f8:	2200      	movs	r2, #0
    39fa:	715a      	strb	r2, [r3, #5]
    39fc:	e7d5      	b.n	39aa <clock_stop+0xa>
    p_reg->INTENCLR = mask;
    39fe:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3a02:	2200      	movs	r2, #0
    p_reg->INTENCLR = mask;
    3a04:	f8c3 0308 	str.w	r0, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3a08:	f8c3 2100 	str.w	r2, [r3, #256]	; 0x100
    3a0c:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    3a10:	6058      	str	r0, [r3, #4]
}
    3a12:	e7d7      	b.n	39c4 <clock_stop+0x24>
            if (p_clk_src != NULL)
    3a14:	b125      	cbz	r5, 3a20 <clock_stop+0x80>
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    3a16:	f8d6 3418 	ldr.w	r3, [r6, #1048]	; 0x418
                                        >> CLOCK_LFCLKSTAT_SRC_Pos);
    3a1a:	f003 0303 	and.w	r3, r3, #3
                (*(nrf_clock_lfclk_t *)p_clk_src) =
    3a1e:	602b      	str	r3, [r5, #0]
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    3a20:	f8d6 3418 	ldr.w	r3, [r6, #1048]	; 0x418
    3a24:	03da      	lsls	r2, r3, #15
    3a26:	d5c0      	bpl.n	39aa <clock_stop+0xa>
    NRFX_WAIT_FOR((!nrfx_clock_is_running(domain, p_clk_src) ||
    3a28:	b92d      	cbnz	r5, 3a36 <clock_stop+0x96>
    3a2a:	2001      	movs	r0, #1
    3a2c:	f002 fcad 	bl	638a <nrfx_busy_wait>
    3a30:	3f01      	subs	r7, #1
    3a32:	d1d3      	bne.n	39dc <clock_stop+0x3c>
    3a34:	e003      	b.n	3a3e <clock_stop+0x9e>
    3a36:	f89d 3007 	ldrb.w	r3, [sp, #7]
    3a3a:	2b01      	cmp	r3, #1
    3a3c:	d0f5      	beq.n	3a2a <clock_stop+0x8a>
    if (domain == NRF_CLOCK_DOMAIN_HFCLK)
    3a3e:	2c01      	cmp	r4, #1
    3a40:	d0d9      	beq.n	39f6 <clock_stop+0x56>
    3a42:	e7b2      	b.n	39aa <clock_stop+0xa>
    3a44:	20000e48 	.word	0x20000e48

00003a48 <nrfx_clock_init>:
nrfx_err_t nrfx_clock_init(nrfx_clock_event_handler_t event_handler)
{
    NRFX_ASSERT(event_handler);

    nrfx_err_t err_code = NRFX_SUCCESS;
    if (m_clock_cb.module_initialized)
    3a48:	4b04      	ldr	r3, [pc, #16]	; (3a5c <nrfx_clock_init+0x14>)
    3a4a:	791a      	ldrb	r2, [r3, #4]
    3a4c:	b922      	cbnz	r2, 3a58 <nrfx_clock_init+0x10>
    {
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
        m_clock_cb.cal_state = CAL_STATE_IDLE;
#endif
        m_clock_cb.event_handler = event_handler;
        m_clock_cb.module_initialized = true;
    3a4e:	2201      	movs	r2, #1
        m_clock_cb.event_handler = event_handler;
    3a50:	6018      	str	r0, [r3, #0]
        m_clock_cb.module_initialized = true;
    3a52:	809a      	strh	r2, [r3, #4]
    nrfx_err_t err_code = NRFX_SUCCESS;
    3a54:	4802      	ldr	r0, [pc, #8]	; (3a60 <nrfx_clock_init+0x18>)
    3a56:	4770      	bx	lr
        err_code = NRFX_ERROR_ALREADY_INITIALIZED;
    3a58:	4802      	ldr	r0, [pc, #8]	; (3a64 <nrfx_clock_init+0x1c>)
#endif
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    3a5a:	4770      	bx	lr
    3a5c:	20000e48 	.word	0x20000e48
    3a60:	0bad0000 	.word	0x0bad0000
    3a64:	0bad000c 	.word	0x0bad000c

00003a68 <nrfx_clock_start>:
    m_clock_cb.module_initialized = false;
    NRFX_LOG_INFO("Uninitialized.");
}

void nrfx_clock_start(nrf_clock_domain_t domain)
{
    3a68:	b538      	push	{r3, r4, r5, lr}
    NRFX_ASSERT(m_clock_cb.module_initialized);
    switch (domain)
    3a6a:	b110      	cbz	r0, 3a72 <nrfx_clock_start+0xa>
    3a6c:	2801      	cmp	r0, #1
    3a6e:	d044      	beq.n	3afa <nrfx_clock_start+0x92>
#endif
        default:
            NRFX_ASSERT(0);
            break;
    }
}
    3a70:	bd38      	pop	{r3, r4, r5, pc}
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    3a72:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    3a76:	f8d2 1418 	ldr.w	r1, [r2, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    3a7a:	f8d2 3418 	ldr.w	r3, [r2, #1048]	; 0x418
    3a7e:	f413 3380 	ands.w	r3, r3, #65536	; 0x10000
    3a82:	d10b      	bne.n	3a9c <nrfx_clock_start+0x34>
            return ((p_reg->LFCLKRUN & CLOCK_LFCLKRUN_STATUS_Msk)
    3a84:	f8d2 1414 	ldr.w	r1, [r2, #1044]	; 0x414
                else if (nrf_clock_start_task_check(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK))
    3a88:	07c9      	lsls	r1, r1, #31
    3a8a:	d510      	bpl.n	3aae <nrfx_clock_start+0x46>
    return (nrf_clock_lfclk_t)((p_reg->LFCLKSRCCOPY & CLOCK_LFCLKSRCCOPY_SRC_Msk)
    3a8c:	f8d2 341c 	ldr.w	r3, [r2, #1052]	; 0x41c
    if (!is_correct_clk)
    3a90:	079b      	lsls	r3, r3, #30
    3a92:	d408      	bmi.n	3aa6 <nrfx_clock_start+0x3e>
    p_reg->INTENSET = mask;
    3a94:	2302      	movs	r3, #2
    3a96:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
                        break;
    3a9a:	e7e9      	b.n	3a70 <nrfx_clock_start+0x8>
                                        >> CLOCK_LFCLKSTAT_SRC_Pos);
    3a9c:	f001 0303 	and.w	r3, r1, #3
    is_correct_clk = is_correct_clk || (*p_lfclksrc == NRF_CLOCK_LFCLK_RC);
    3aa0:	2b01      	cmp	r3, #1
    3aa2:	d004      	beq.n	3aae <nrfx_clock_start+0x46>
    if (!is_correct_clk)
    3aa4:	b11b      	cbz	r3, 3aae <nrfx_clock_start+0x46>
        clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
    3aa6:	2000      	movs	r0, #0
    3aa8:	f7ff ff7a 	bl	39a0 <clock_stop>
        *p_lfclksrc = clock_initial_lfclksrc_get();
    3aac:	2300      	movs	r3, #0
    p_reg->LFCLKSRC = (uint32_t)(source);
    3aae:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    3ab2:	f8c2 3518 	str.w	r3, [r2, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3ab6:	2300      	movs	r3, #0
    3ab8:	f8c2 3104 	str.w	r3, [r2, #260]	; 0x104
    3abc:	f8d2 3104 	ldr.w	r3, [r2, #260]	; 0x104
    p_reg->INTENSET = mask;
    3ac0:	2302      	movs	r3, #2
    3ac2:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
    core_debug = CoreDebug->DEMCR;
    3ac6:	4a12      	ldr	r2, [pc, #72]	; (3b10 <nrfx_clock_start+0xa8>)
    3ac8:	f8d2 00fc 	ldr.w	r0, [r2, #252]	; 0xfc
    CoreDebug->DEMCR = core_debug | CoreDebug_DEMCR_TRCENA_Msk;
    3acc:	f040 7380 	orr.w	r3, r0, #16777216	; 0x1000000
    3ad0:	f8c2 30fc 	str.w	r3, [r2, #252]	; 0xfc
    dwt_ctrl = DWT->CTRL;
    3ad4:	4b0f      	ldr	r3, [pc, #60]	; (3b14 <nrfx_clock_start+0xac>)
    3ad6:	681c      	ldr	r4, [r3, #0]
    DWT->CTRL = dwt_ctrl | DWT_CTRL_CYCCNTENA_Msk;
    3ad8:	f044 0101 	orr.w	r1, r4, #1
    3adc:	6019      	str	r1, [r3, #0]
    cyccnt_inital = DWT->CYCCNT;
    3ade:	685d      	ldr	r5, [r3, #4]
    while ((DWT->CYCCNT - cyccnt_inital) < ANOMALY_132_DELAY_CYCLES)
    3ae0:	6859      	ldr	r1, [r3, #4]
    3ae2:	1b49      	subs	r1, r1, r5
    3ae4:	f5b1 5f0a 	cmp.w	r1, #8832	; 0x2280
    3ae8:	d3fa      	bcc.n	3ae0 <nrfx_clock_start+0x78>
    DWT->CTRL = dwt_ctrl;
    3aea:	601c      	str	r4, [r3, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    3aec:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    CoreDebug->DEMCR = core_debug;
    3af0:	f8c2 00fc 	str.w	r0, [r2, #252]	; 0xfc
    3af4:	2201      	movs	r2, #1
    3af6:	609a      	str	r2, [r3, #8]
}
    3af8:	e7ba      	b.n	3a70 <nrfx_clock_start+0x8>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3afa:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    3afe:	2200      	movs	r2, #0
    3b00:	f8c3 2100 	str.w	r2, [r3, #256]	; 0x100
    3b04:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    p_reg->INTENSET = mask;
    3b08:	f8c3 0304 	str.w	r0, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    3b0c:	6018      	str	r0, [r3, #0]
}
    3b0e:	e7af      	b.n	3a70 <nrfx_clock_start+0x8>
    3b10:	e000ed00 	.word	0xe000ed00
    3b14:	e0001000 	.word	0xe0001000

00003b18 <nrfx_power_clock_irq_handler>:
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    3b18:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    }
}
#endif

void nrfx_clock_irq_handler(void)
{
    3b1c:	b510      	push	{r4, lr}
    3b1e:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED))
    3b22:	b16a      	cbz	r2, 3b40 <nrfx_power_clock_irq_handler+0x28>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3b24:	2200      	movs	r2, #0
    3b26:	f8c3 2100 	str.w	r2, [r3, #256]	; 0x100
    3b2a:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    p_reg->INTENCLR = mask;
    3b2e:	2201      	movs	r2, #1
    3b30:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
        nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED);
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_HFCLKSTARTED");
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF_STARTED_MASK);

#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_201)
        if (!m_clock_cb.hfclk_started)
    3b34:	4b11      	ldr	r3, [pc, #68]	; (3b7c <nrfx_power_clock_irq_handler+0x64>)
    3b36:	7958      	ldrb	r0, [r3, #5]
    3b38:	b910      	cbnz	r0, 3b40 <nrfx_power_clock_irq_handler+0x28>
        {
            m_clock_cb.hfclk_started = true;
    3b3a:	715a      	strb	r2, [r3, #5]
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
    3b3c:	681b      	ldr	r3, [r3, #0]
    3b3e:	4798      	blx	r3
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    3b40:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    3b44:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
        }
#else
        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
#endif
    }
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED))
    3b48:	b172      	cbz	r2, 3b68 <nrfx_power_clock_irq_handler+0x50>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    3b4a:	2200      	movs	r2, #0
    3b4c:	f8c3 2104 	str.w	r2, [r3, #260]	; 0x104
    3b50:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    3b54:	f8d3 2418 	ldr.w	r2, [r3, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    3b58:	f8d3 1418 	ldr.w	r1, [r3, #1048]	; 0x418
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_LFCLKSTARTED");

#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED)
        nrf_clock_lfclk_t lfclksrc;
        (void)nrf_clock_is_running(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK, &lfclksrc);
        if (lfclksrc == NRF_CLOCK_LFCLK_RC)
    3b5c:	0792      	lsls	r2, r2, #30
    3b5e:	d104      	bne.n	3b6a <nrfx_power_clock_irq_handler+0x52>
    p_reg->LFCLKSRC = (uint32_t)(source);
    3b60:	2201      	movs	r2, #1
    3b62:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    3b66:	609a      	str	r2, [r3, #8]
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF192M_STARTED_MASK);

        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK192M_STARTED);
    }
#endif
}
    3b68:	bd10      	pop	{r4, pc}
    p_reg->INTENCLR = mask;
    3b6a:	2202      	movs	r2, #2
    3b6c:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    3b70:	4b02      	ldr	r3, [pc, #8]	; (3b7c <nrfx_power_clock_irq_handler+0x64>)
}
    3b72:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    3b76:	681b      	ldr	r3, [r3, #0]
    3b78:	2001      	movs	r0, #1
    3b7a:	4718      	bx	r3
    3b7c:	20000e48 	.word	0x20000e48

00003b80 <pin_in_use_by_te>:
 *
 * @return True if pin uses GPIOTE task/event.
 */
static bool pin_in_use_by_te(uint32_t pin)
{
    return m_cb.pin_flags[pin] & PIN_FLAG_TE_USED;
    3b80:	4b03      	ldr	r3, [pc, #12]	; (3b90 <pin_in_use_by_te+0x10>)
    3b82:	3008      	adds	r0, #8
    3b84:	f833 0010 	ldrh.w	r0, [r3, r0, lsl #1]
}
    3b88:	f3c0 1040 	ubfx	r0, r0, #5, #1
    3b8c:	4770      	bx	lr
    3b8e:	bf00      	nop
    3b90:	20000030 	.word	0x20000030

00003b94 <call_handler>:
    nrf_gpiote_event_t event = nrfx_gpiote_in_event_get(pin);
    return nrf_gpiote_event_address_get(NRF_GPIOTE, event);
}

static void call_handler(nrfx_gpiote_pin_t pin, nrfx_gpiote_trigger_t trigger)
{
    3b94:	b570      	push	{r4, r5, r6, lr}
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    3b96:	f100 0308 	add.w	r3, r0, #8
    3b9a:	4c0c      	ldr	r4, [pc, #48]	; (3bcc <call_handler+0x38>)
    3b9c:	f834 3013 	ldrh.w	r3, [r4, r3, lsl #1]
    3ba0:	05da      	lsls	r2, r3, #23
{
    3ba2:	4605      	mov	r5, r0
    3ba4:	460e      	mov	r6, r1
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    3ba6:	d507      	bpl.n	3bb8 <call_handler+0x24>
    3ba8:	f3c3 2343 	ubfx	r3, r3, #9, #4
    nrfx_gpiote_handler_config_t const * handler = channel_handler_get(pin);

    if (handler)
    {
        handler->handler(pin, trigger, handler->p_context);
    3bac:	eb04 02c3 	add.w	r2, r4, r3, lsl #3
    3bb0:	f854 3033 	ldr.w	r3, [r4, r3, lsl #3]
    3bb4:	6852      	ldr	r2, [r2, #4]
    3bb6:	4798      	blx	r3
    }
    if (m_cb.global_handler.handler)
    3bb8:	68a3      	ldr	r3, [r4, #8]
    3bba:	b12b      	cbz	r3, 3bc8 <call_handler+0x34>
    {
        m_cb.global_handler.handler(pin, trigger, m_cb.global_handler.p_context);
    3bbc:	68e2      	ldr	r2, [r4, #12]
    3bbe:	4631      	mov	r1, r6
    3bc0:	4628      	mov	r0, r5
    }
}
    3bc2:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
        m_cb.global_handler.handler(pin, trigger, m_cb.global_handler.p_context);
    3bc6:	4718      	bx	r3
}
    3bc8:	bd70      	pop	{r4, r5, r6, pc}
    3bca:	bf00      	nop
    3bcc:	20000030 	.word	0x20000030

00003bd0 <release_handler>:
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    3bd0:	4a12      	ldr	r2, [pc, #72]	; (3c1c <release_handler+0x4c>)
    3bd2:	3008      	adds	r0, #8
{
    3bd4:	b410      	push	{r4}
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    3bd6:	f832 3010 	ldrh.w	r3, [r2, r0, lsl #1]
    3bda:	05d9      	lsls	r1, r3, #23
    3bdc:	d51b      	bpl.n	3c16 <release_handler+0x46>
    3bde:	f3c3 2143 	ubfx	r1, r3, #9, #4
    m_cb.pin_flags[pin] &= ~PIN_HANDLER_MASK;
    3be2:	f423 53f8 	bic.w	r3, r3, #7936	; 0x1f00
    3be6:	f822 3010 	strh.w	r3, [r2, r0, lsl #1]
    for (uint32_t i = 0; i < MAX_PIN_NUMBER; i++)
    3bea:	f102 0410 	add.w	r4, r2, #16
    3bee:	2000      	movs	r0, #0
        if (PIN_GET_HANDLER_ID(m_cb.pin_flags[i]) == handler_id)
    3bf0:	f834 3b02 	ldrh.w	r3, [r4], #2
    3bf4:	f413 7f80 	tst.w	r3, #256	; 0x100
    3bf8:	d003      	beq.n	3c02 <release_handler+0x32>
    3bfa:	f3c3 2343 	ubfx	r3, r3, #9, #4
    3bfe:	4299      	cmp	r1, r3
    3c00:	d009      	beq.n	3c16 <release_handler+0x46>
    for (uint32_t i = 0; i < MAX_PIN_NUMBER; i++)
    3c02:	3001      	adds	r0, #1
    3c04:	2820      	cmp	r0, #32
    3c06:	d1f3      	bne.n	3bf0 <release_handler+0x20>
        m_cb.handlers[handler_id].handler = NULL;
    3c08:	2300      	movs	r3, #0
    3c0a:	f842 3031 	str.w	r3, [r2, r1, lsl #3]
        nrfx_err_t err = nrfx_flag32_free(&m_cb.available_evt_handlers, handler_id);
    3c0e:	4804      	ldr	r0, [pc, #16]	; (3c20 <release_handler+0x50>)
}
    3c10:	bc10      	pop	{r4}
        nrfx_err_t err = nrfx_flag32_free(&m_cb.available_evt_handlers, handler_id);
    3c12:	f7ff bea3 	b.w	395c <nrfx_flag32_free>
}
    3c16:	bc10      	pop	{r4}
    3c18:	4770      	bx	lr
    3c1a:	bf00      	nop
    3c1c:	20000030 	.word	0x20000030
    3c20:	20000084 	.word	0x20000084

00003c24 <pin_handler_trigger_uninit>:
{
    3c24:	b538      	push	{r3, r4, r5, lr}
    3c26:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin))
    3c28:	f7ff ffaa 	bl	3b80 <pin_in_use_by_te>
    3c2c:	4c09      	ldr	r4, [pc, #36]	; (3c54 <pin_handler_trigger_uninit+0x30>)
    3c2e:	f102 0508 	add.w	r5, r2, #8
    3c32:	b140      	cbz	r0, 3c46 <pin_handler_trigger_uninit+0x22>
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    3c34:	f834 3015 	ldrh.w	r3, [r4, r5, lsl #1]
                         ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
}

NRF_STATIC_INLINE void nrf_gpiote_te_default(NRF_GPIOTE_Type * p_reg, uint32_t idx)
{
    p_reg->CONFIG[idx] = 0;
    3c38:	4907      	ldr	r1, [pc, #28]	; (3c58 <pin_handler_trigger_uninit+0x34>)
        nrf_gpiote_te_default(NRF_GPIOTE, pin_te_get(pin));
    3c3a:	0b5b      	lsrs	r3, r3, #13
    3c3c:	f503 73a2 	add.w	r3, r3, #324	; 0x144
    3c40:	2000      	movs	r0, #0
    3c42:	f841 0023 	str.w	r0, [r1, r3, lsl #2]
    release_handler(pin);
    3c46:	4610      	mov	r0, r2
    3c48:	f7ff ffc2 	bl	3bd0 <release_handler>
    m_cb.pin_flags[pin] = PIN_FLAG_NOT_USED;
    3c4c:	2300      	movs	r3, #0
    3c4e:	f824 3015 	strh.w	r3, [r4, r5, lsl #1]
}
    3c52:	bd38      	pop	{r3, r4, r5, pc}
    3c54:	20000030 	.word	0x20000030
    3c58:	40006000 	.word	0x40006000

00003c5c <nrfx_gpiote_input_configure>:
{
    3c5c:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
    3c60:	4604      	mov	r4, r0
    3c62:	461e      	mov	r6, r3
    if (p_input_config)
    3c64:	b309      	cbz	r1, 3caa <nrfx_gpiote_input_configure+0x4e>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    3c66:	4f4d      	ldr	r7, [pc, #308]	; (3d9c <nrfx_gpiote_input_configure+0x140>)
    3c68:	f100 0808 	add.w	r8, r0, #8
    3c6c:	f837 5018 	ldrh.w	r5, [r7, r8, lsl #1]
    return pin_is_output(pin) && pin_in_use_by_te(pin);
    3c70:	07ab      	lsls	r3, r5, #30
    3c72:	d506      	bpl.n	3c82 <nrfx_gpiote_input_configure+0x26>
    3c74:	f7ff ff84 	bl	3b80 <pin_in_use_by_te>
        if (pin_is_task_output(pin))
    3c78:	b118      	cbz	r0, 3c82 <nrfx_gpiote_input_configure+0x26>
            return NRFX_ERROR_INVALID_PARAM;
    3c7a:	4849      	ldr	r0, [pc, #292]	; (3da0 <nrfx_gpiote_input_configure+0x144>)
}
    3c7c:	b002      	add	sp, #8
    3c7e:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    *p_pin = pin_number & 0x1F;
    3c82:	f004 001f 	and.w	r0, r4, #31
    3c86:	0080      	lsls	r0, r0, #2
    3c88:	f100 40a0 	add.w	r0, r0, #1342177280	; 0x50000000
           ((uint32_t)(p_pull  ? *p_pull  : 0) << GPIO_PIN_CNF_PULL_Pos)  |
    3c8c:	7809      	ldrb	r1, [r1, #0]
    uint32_t cnf = reg->PIN_CNF[pin_number];
    3c8e:	f8d0 3700 	ldr.w	r3, [r0, #1792]	; 0x700
        m_cb.pin_flags[pin] &= ~PIN_FLAG_OUTPUT;
    3c92:	f025 0502 	bic.w	r5, r5, #2
    cnf &= ~to_update;
    3c96:	f023 030f 	bic.w	r3, r3, #15
        m_cb.pin_flags[pin] |= PIN_FLAG_IN_USE;
    3c9a:	f045 0501 	orr.w	r5, r5, #1
    cnf |= ((uint32_t)(p_dir   ? *p_dir   : 0) << GPIO_PIN_CNF_DIR_Pos)   |
    3c9e:	ea43 0381 	orr.w	r3, r3, r1, lsl #2
    3ca2:	f827 5018 	strh.w	r5, [r7, r8, lsl #1]
    reg->PIN_CNF[pin_number] = cnf;
    3ca6:	f8c0 3700 	str.w	r3, [r0, #1792]	; 0x700
    if (p_trigger_config)
    3caa:	b192      	cbz	r2, 3cd2 <nrfx_gpiote_input_configure+0x76>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    3cac:	4b3b      	ldr	r3, [pc, #236]	; (3d9c <nrfx_gpiote_input_configure+0x140>)
        nrfx_gpiote_trigger_t trigger = p_trigger_config->trigger;
    3cae:	7815      	ldrb	r5, [r2, #0]
        bool use_evt = p_trigger_config->p_in_channel ? true : false;
    3cb0:	6852      	ldr	r2, [r2, #4]
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    3cb2:	f104 0008 	add.w	r0, r4, #8
    3cb6:	f833 1010 	ldrh.w	r1, [r3, r0, lsl #1]
        if (pin_is_output(pin))
    3cba:	078f      	lsls	r7, r1, #30
    3cbc:	d50c      	bpl.n	3cd8 <nrfx_gpiote_input_configure+0x7c>
            if (use_evt)
    3cbe:	2a00      	cmp	r2, #0
    3cc0:	d1db      	bne.n	3c7a <nrfx_gpiote_input_configure+0x1e>
        m_cb.pin_flags[pin] &= ~PIN_FLAG_TRIG_MODE_MASK;
    3cc2:	f833 2010 	ldrh.w	r2, [r3, r0, lsl #1]
    3cc6:	f022 021c 	bic.w	r2, r2, #28
        m_cb.pin_flags[pin] |= PIN_FLAG_TRIG_MODE_SET(trigger);
    3cca:	ea42 0285 	orr.w	r2, r2, r5, lsl #2
    3cce:	f823 2010 	strh.w	r2, [r3, r0, lsl #1]
    if (p_handler_config)
    3cd2:	bbce      	cbnz	r6, 3d48 <nrfx_gpiote_input_configure+0xec>
    return NRFX_SUCCESS;
    3cd4:	4833      	ldr	r0, [pc, #204]	; (3da4 <nrfx_gpiote_input_configure+0x148>)
    3cd6:	e7d1      	b.n	3c7c <nrfx_gpiote_input_configure+0x20>
            m_cb.pin_flags[pin] &= ~(PIN_TE_ID_MASK | PIN_FLAG_TE_USED);
    3cd8:	f021 0120 	bic.w	r1, r1, #32
    3cdc:	04c9      	lsls	r1, r1, #19
    3cde:	0cc9      	lsrs	r1, r1, #19
    3ce0:	f823 1010 	strh.w	r1, [r3, r0, lsl #1]
            if (use_evt)
    3ce4:	2a00      	cmp	r2, #0
    3ce6:	d0ec      	beq.n	3cc2 <nrfx_gpiote_input_configure+0x66>
                if (!edge)
    3ce8:	2d03      	cmp	r5, #3
    3cea:	d8c6      	bhi.n	3c7a <nrfx_gpiote_input_configure+0x1e>
                uint8_t ch = *p_trigger_config->p_in_channel;
    3cec:	7817      	ldrb	r7, [r2, #0]
                if (trigger == NRFX_GPIOTE_TRIGGER_NONE)
    3cee:	b92d      	cbnz	r5, 3cfc <nrfx_gpiote_input_configure+0xa0>
    3cf0:	4a2d      	ldr	r2, [pc, #180]	; (3da8 <nrfx_gpiote_input_configure+0x14c>)
    3cf2:	f507 71a2 	add.w	r1, r7, #324	; 0x144
    3cf6:	f842 5021 	str.w	r5, [r2, r1, lsl #2]
#if defined(NRF9160_XXAA) || defined(NRF5340_XXAA)
    p_reg->CONFIG[idx] = 0;
#endif
}
    3cfa:	e7e2      	b.n	3cc2 <nrfx_gpiote_input_configure+0x66>
   p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk;
    3cfc:	00ba      	lsls	r2, r7, #2
    3cfe:	f102 4280 	add.w	r2, r2, #1073741824	; 0x40000000
    3d02:	f502 42c0 	add.w	r2, r2, #24576	; 0x6000
                    m_cb.pin_flags[pin] |= PIN_FLAG_TE_ID(ch);
    3d06:	ea41 3147 	orr.w	r1, r1, r7, lsl #13
    3d0a:	f8d2 c510 	ldr.w	ip, [r2, #1296]	; 0x510
    3d0e:	f02c 0c03 	bic.w	ip, ip, #3
    3d12:	f8c2 c510 	str.w	ip, [r2, #1296]	; 0x510
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk);
    3d16:	f8d2 c510 	ldr.w	ip, [r2, #1296]	; 0x510
    3d1a:	f42c 3c47 	bic.w	ip, ip, #203776	; 0x31c00
    3d1e:	f42c 7c40 	bic.w	ip, ip, #768	; 0x300
    3d22:	f8c2 c510 	str.w	ip, [r2, #1296]	; 0x510
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    3d26:	f8d2 e510 	ldr.w	lr, [r2, #1296]	; 0x510
    3d2a:	ea4f 2c04 	mov.w	ip, r4, lsl #8
    3d2e:	f40c 5cf8 	and.w	ip, ip, #7936	; 0x1f00
    3d32:	ea4e 4e05 	orr.w	lr, lr, r5, lsl #16
    3d36:	ea4c 0c0e 	orr.w	ip, ip, lr
    3d3a:	f041 0120 	orr.w	r1, r1, #32
    3d3e:	f823 1010 	strh.w	r1, [r3, r0, lsl #1]
    3d42:	f8c2 c510 	str.w	ip, [r2, #1296]	; 0x510
    3d46:	e7bc      	b.n	3cc2 <nrfx_gpiote_input_configure+0x66>
        err = pin_handler_set(pin, p_handler_config->handler, p_handler_config->p_context);
    3d48:	e9d6 7600 	ldrd	r7, r6, [r6]
    release_handler(pin);
    3d4c:	4620      	mov	r0, r4
    3d4e:	f7ff ff3f 	bl	3bd0 <release_handler>
    if (!handler)
    3d52:	2f00      	cmp	r7, #0
    3d54:	d0be      	beq.n	3cd4 <nrfx_gpiote_input_configure+0x78>
        if ((m_cb.handlers[i].handler == handler) && (m_cb.handlers[i].p_context == p_context))
    3d56:	4d11      	ldr	r5, [pc, #68]	; (3d9c <nrfx_gpiote_input_configure+0x140>)
    3d58:	682b      	ldr	r3, [r5, #0]
    3d5a:	429f      	cmp	r7, r3
    3d5c:	d104      	bne.n	3d68 <nrfx_gpiote_input_configure+0x10c>
    3d5e:	686b      	ldr	r3, [r5, #4]
    3d60:	429e      	cmp	r6, r3
    3d62:	d101      	bne.n	3d68 <nrfx_gpiote_input_configure+0x10c>
    3d64:	2200      	movs	r2, #0
    3d66:	e009      	b.n	3d7c <nrfx_gpiote_input_configure+0x120>
        err = nrfx_flag32_alloc(&m_cb.available_evt_handlers, &id);
    3d68:	4810      	ldr	r0, [pc, #64]	; (3dac <nrfx_gpiote_input_configure+0x150>)
    3d6a:	f10d 0107 	add.w	r1, sp, #7
    3d6e:	f7ff fdcf 	bl	3910 <nrfx_flag32_alloc>
        if (err != NRFX_SUCCESS)
    3d72:	4b0c      	ldr	r3, [pc, #48]	; (3da4 <nrfx_gpiote_input_configure+0x148>)
    3d74:	4298      	cmp	r0, r3
    3d76:	d181      	bne.n	3c7c <nrfx_gpiote_input_configure+0x20>
        handler_id = (int32_t)id;
    3d78:	f89d 2007 	ldrb.w	r2, [sp, #7]
    m_cb.handlers[handler_id].handler = handler;
    3d7c:	f845 7032 	str.w	r7, [r5, r2, lsl #3]
    m_cb.handlers[handler_id].p_context = p_context;
    3d80:	eb05 03c2 	add.w	r3, r5, r2, lsl #3
    m_cb.pin_flags[pin] |= PIN_FLAG_HANDLER(handler_id);
    3d84:	3408      	adds	r4, #8
    m_cb.handlers[handler_id].p_context = p_context;
    3d86:	605e      	str	r6, [r3, #4]
    m_cb.pin_flags[pin] |= PIN_FLAG_HANDLER(handler_id);
    3d88:	f835 3014 	ldrh.w	r3, [r5, r4, lsl #1]
    3d8c:	ea43 2342 	orr.w	r3, r3, r2, lsl #9
    3d90:	f443 7380 	orr.w	r3, r3, #256	; 0x100
    3d94:	f825 3014 	strh.w	r3, [r5, r4, lsl #1]
    3d98:	e79c      	b.n	3cd4 <nrfx_gpiote_input_configure+0x78>
    3d9a:	bf00      	nop
    3d9c:	20000030 	.word	0x20000030
    3da0:	0bad0004 	.word	0x0bad0004
    3da4:	0bad0000 	.word	0x0bad0000
    3da8:	40006000 	.word	0x40006000
    3dac:	20000084 	.word	0x20000084

00003db0 <nrfx_gpiote_output_configure>:
{
    3db0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    3db2:	4604      	mov	r4, r0
    if (p_config)
    3db4:	b371      	cbz	r1, 3e14 <nrfx_gpiote_output_configure+0x64>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    3db6:	4e37      	ldr	r6, [pc, #220]	; (3e94 <nrfx_gpiote_output_configure+0xe4>)
    3db8:	f100 0708 	add.w	r7, r0, #8
    3dbc:	f836 5017 	ldrh.w	r5, [r6, r7, lsl #1]
        if (pin_is_input(pin) && pin_in_use_by_te(pin))
    3dc0:	07ab      	lsls	r3, r5, #30
    3dc2:	d404      	bmi.n	3dce <nrfx_gpiote_output_configure+0x1e>
    3dc4:	f7ff fedc 	bl	3b80 <pin_in_use_by_te>
    3dc8:	b108      	cbz	r0, 3dce <nrfx_gpiote_output_configure+0x1e>
    return NRFX_SUCCESS;
    3dca:	4833      	ldr	r0, [pc, #204]	; (3e98 <nrfx_gpiote_output_configure+0xe8>)
}
    3dcc:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
        if (pin_has_trigger(pin) && (p_config->input_connect == NRF_GPIO_PIN_INPUT_DISCONNECT))
    3dce:	f015 0f1c 	tst.w	r5, #28
    3dd2:	784b      	ldrb	r3, [r1, #1]
    3dd4:	d001      	beq.n	3dda <nrfx_gpiote_output_configure+0x2a>
    3dd6:	2b01      	cmp	r3, #1
    3dd8:	d0f7      	beq.n	3dca <nrfx_gpiote_output_configure+0x1a>
    *p_pin = pin_number & 0x1F;
    3dda:	f004 001f 	and.w	r0, r4, #31
    3dde:	0080      	lsls	r0, r0, #2
    3de0:	f100 40a0 	add.w	r0, r0, #1342177280	; 0x50000000
           ((uint32_t)(p_drive ? *p_drive : 0) << GPIO_PIN_CNF_DRIVE_Pos) |
    3de4:	f891 e000 	ldrb.w	lr, [r1]
    uint32_t cnf = reg->PIN_CNF[pin_number];
    3de8:	f8d0 c700 	ldr.w	ip, [r0, #1792]	; 0x700
           ((uint32_t)(p_pull  ? *p_pull  : 0) << GPIO_PIN_CNF_PULL_Pos)  |
    3dec:	7889      	ldrb	r1, [r1, #2]
           ((uint32_t)(p_input ? *p_input : 0) << GPIO_PIN_CNF_INPUT_Pos) |
    3dee:	005b      	lsls	r3, r3, #1
    cnf &= ~to_update;
    3df0:	f42c 6ce1 	bic.w	ip, ip, #1800	; 0x708
    3df4:	ea43 230e 	orr.w	r3, r3, lr, lsl #8
    3df8:	f02c 0c07 	bic.w	ip, ip, #7
    3dfc:	ea43 030c 	orr.w	r3, r3, ip
    3e00:	ea43 0381 	orr.w	r3, r3, r1, lsl #2
        m_cb.pin_flags[pin] |= PIN_FLAG_IN_USE | PIN_FLAG_OUTPUT;
    3e04:	f045 0503 	orr.w	r5, r5, #3
    cnf |= ((uint32_t)(p_dir   ? *p_dir   : 0) << GPIO_PIN_CNF_DIR_Pos)   |
    3e08:	f043 0301 	orr.w	r3, r3, #1
    3e0c:	f826 5017 	strh.w	r5, [r6, r7, lsl #1]
    reg->PIN_CNF[pin_number] = cnf;
    3e10:	f8c0 3700 	str.w	r3, [r0, #1792]	; 0x700
    if (p_task_config)
    3e14:	b90a      	cbnz	r2, 3e1a <nrfx_gpiote_output_configure+0x6a>
    return NRFX_SUCCESS;
    3e16:	4821      	ldr	r0, [pc, #132]	; (3e9c <nrfx_gpiote_output_configure+0xec>)
    3e18:	e7d8      	b.n	3dcc <nrfx_gpiote_output_configure+0x1c>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    3e1a:	4e1e      	ldr	r6, [pc, #120]	; (3e94 <nrfx_gpiote_output_configure+0xe4>)
    3e1c:	f104 0708 	add.w	r7, r4, #8
    3e20:	f836 0017 	ldrh.w	r0, [r6, r7, lsl #1]
        if (pin_is_input(pin))
    3e24:	0783      	lsls	r3, r0, #30
    3e26:	d5d0      	bpl.n	3dca <nrfx_gpiote_output_configure+0x1a>
        uint32_t ch = p_task_config->task_ch;
    3e28:	f892 c000 	ldrb.w	ip, [r2]
    p_reg->CONFIG[idx] = 0;
    3e2c:	4661      	mov	r1, ip
    3e2e:	0089      	lsls	r1, r1, #2
        m_cb.pin_flags[pin] &= ~(PIN_FLAG_TE_USED | PIN_TE_ID_MASK);
    3e30:	f020 0020 	bic.w	r0, r0, #32
    3e34:	f101 4180 	add.w	r1, r1, #1073741824	; 0x40000000
    3e38:	04c0      	lsls	r0, r0, #19
    3e3a:	f501 41c0 	add.w	r1, r1, #24576	; 0x6000
    3e3e:	0cc0      	lsrs	r0, r0, #19
    3e40:	f826 0017 	strh.w	r0, [r6, r7, lsl #1]
    3e44:	2300      	movs	r3, #0
    3e46:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
        if (p_task_config->polarity != NRF_GPIOTE_POLARITY_NONE)
    3e4a:	7855      	ldrb	r5, [r2, #1]
    3e4c:	2d00      	cmp	r5, #0
    3e4e:	d0e2      	beq.n	3e16 <nrfx_gpiote_output_configure+0x66>
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk |
    3e50:	f8d1 3510 	ldr.w	r3, [r1, #1296]	; 0x510
            nrf_gpiote_task_configure(NRF_GPIOTE, ch, pin,
    3e54:	7892      	ldrb	r2, [r2, #2]
    3e56:	f423 1398 	bic.w	r3, r3, #1245184	; 0x130000
    3e5a:	f423 53f8 	bic.w	r3, r3, #7936	; 0x1f00
    3e5e:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    3e62:	f8d1 e510 	ldr.w	lr, [r1, #1296]	; 0x510
    3e66:	0223      	lsls	r3, r4, #8
    3e68:	f403 53f8 	and.w	r3, r3, #7936	; 0x1f00
                        ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk) |
    3e6c:	042d      	lsls	r5, r5, #16
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    3e6e:	ea43 030e 	orr.w	r3, r3, lr
                        ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk) |
    3e72:	f405 3540 	and.w	r5, r5, #196608	; 0x30000
                        ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
    3e76:	0512      	lsls	r2, r2, #20
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    3e78:	432b      	orrs	r3, r5
                        ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
    3e7a:	f402 1280 	and.w	r2, r2, #1048576	; 0x100000
            m_cb.pin_flags[pin] |= PIN_FLAG_TE_ID(ch);
    3e7e:	ea40 304c 	orr.w	r0, r0, ip, lsl #13
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    3e82:	4313      	orrs	r3, r2
    3e84:	f040 0020 	orr.w	r0, r0, #32
    3e88:	f826 0017 	strh.w	r0, [r6, r7, lsl #1]
    3e8c:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
    3e90:	e7c1      	b.n	3e16 <nrfx_gpiote_output_configure+0x66>
    3e92:	bf00      	nop
    3e94:	20000030 	.word	0x20000030
    3e98:	0bad0004 	.word	0x0bad0004
    3e9c:	0bad0000 	.word	0x0bad0000

00003ea0 <nrfx_gpiote_global_callback_set>:
    m_cb.global_handler.handler = handler;
    3ea0:	4b01      	ldr	r3, [pc, #4]	; (3ea8 <nrfx_gpiote_global_callback_set+0x8>)
    m_cb.global_handler.p_context = p_context;
    3ea2:	e9c3 0102 	strd	r0, r1, [r3, #8]
}
    3ea6:	4770      	bx	lr
    3ea8:	20000030 	.word	0x20000030

00003eac <nrfx_gpiote_channel_get>:
{
    3eac:	b508      	push	{r3, lr}
    3eae:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin))
    3eb0:	f7ff fe66 	bl	3b80 <pin_in_use_by_te>
    3eb4:	b138      	cbz	r0, 3ec6 <nrfx_gpiote_channel_get+0x1a>
        *p_channel = PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    3eb6:	4b05      	ldr	r3, [pc, #20]	; (3ecc <nrfx_gpiote_channel_get+0x20>)
        return NRFX_SUCCESS;
    3eb8:	4805      	ldr	r0, [pc, #20]	; (3ed0 <nrfx_gpiote_channel_get+0x24>)
        *p_channel = PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    3eba:	3208      	adds	r2, #8
    3ebc:	f833 3012 	ldrh.w	r3, [r3, r2, lsl #1]
    3ec0:	0b5b      	lsrs	r3, r3, #13
    3ec2:	700b      	strb	r3, [r1, #0]
}
    3ec4:	bd08      	pop	{r3, pc}
        return NRFX_ERROR_INVALID_PARAM;
    3ec6:	4803      	ldr	r0, [pc, #12]	; (3ed4 <nrfx_gpiote_channel_get+0x28>)
    3ec8:	e7fc      	b.n	3ec4 <nrfx_gpiote_channel_get+0x18>
    3eca:	bf00      	nop
    3ecc:	20000030 	.word	0x20000030
    3ed0:	0bad0000 	.word	0x0bad0000
    3ed4:	0bad0004 	.word	0x0bad0004

00003ed8 <nrfx_gpiote_init>:
{
    3ed8:	b538      	push	{r3, r4, r5, lr}
    if (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED)
    3eda:	4c0f      	ldr	r4, [pc, #60]	; (3f18 <nrfx_gpiote_init+0x40>)
    3edc:	f894 5058 	ldrb.w	r5, [r4, #88]	; 0x58
    3ee0:	b9bd      	cbnz	r5, 3f12 <nrfx_gpiote_init+0x3a>
    memset(m_cb.pin_flags, 0, sizeof(m_cb.pin_flags));
    3ee2:	2240      	movs	r2, #64	; 0x40
    3ee4:	4629      	mov	r1, r5
    3ee6:	f104 0010 	add.w	r0, r4, #16
    3eea:	f001 feea 	bl	5cc2 <memset>
    NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_GPIOTE));
    3eee:	2006      	movs	r0, #6
    3ef0:	f7fd ff5e 	bl	1db0 <arch_irq_enable>
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    3ef4:	4b09      	ldr	r3, [pc, #36]	; (3f1c <nrfx_gpiote_init+0x44>)
    return err_code;
    3ef6:	480a      	ldr	r0, [pc, #40]	; (3f20 <nrfx_gpiote_init+0x48>)
    3ef8:	f8c3 517c 	str.w	r5, [r3, #380]	; 0x17c
    3efc:	f8d3 217c 	ldr.w	r2, [r3, #380]	; 0x17c
    p_reg->INTENSET = mask;
    3f00:	f04f 4200 	mov.w	r2, #2147483648	; 0x80000000
    3f04:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    m_cb.state = NRFX_DRV_STATE_INITIALIZED;
    3f08:	2301      	movs	r3, #1
    3f0a:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
    m_cb.available_evt_handlers = NRFX_BIT_MASK(NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS);
    3f0e:	6563      	str	r3, [r4, #84]	; 0x54
}
    3f10:	bd38      	pop	{r3, r4, r5, pc}
        return err_code;
    3f12:	4804      	ldr	r0, [pc, #16]	; (3f24 <nrfx_gpiote_init+0x4c>)
    3f14:	e7fc      	b.n	3f10 <nrfx_gpiote_init+0x38>
    3f16:	bf00      	nop
    3f18:	20000030 	.word	0x20000030
    3f1c:	40006000 	.word	0x40006000
    3f20:	0bad0000 	.word	0x0bad0000
    3f24:	0bad0005 	.word	0x0bad0005

00003f28 <nrfx_gpiote_is_init>:
    return (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED) ? true : false;
    3f28:	4b03      	ldr	r3, [pc, #12]	; (3f38 <nrfx_gpiote_is_init+0x10>)
    3f2a:	f893 0058 	ldrb.w	r0, [r3, #88]	; 0x58
}
    3f2e:	3800      	subs	r0, #0
    3f30:	bf18      	it	ne
    3f32:	2001      	movne	r0, #1
    3f34:	4770      	bx	lr
    3f36:	bf00      	nop
    3f38:	20000030 	.word	0x20000030

00003f3c <nrfx_gpiote_channel_free>:
{
    3f3c:	4601      	mov	r1, r0
    return nrfx_flag32_free(&m_cb.available_channels_mask, channel);
    3f3e:	4801      	ldr	r0, [pc, #4]	; (3f44 <nrfx_gpiote_channel_free+0x8>)
    3f40:	f7ff bd0c 	b.w	395c <nrfx_flag32_free>
    3f44:	20000080 	.word	0x20000080

00003f48 <nrfx_gpiote_channel_alloc>:
{
    3f48:	4601      	mov	r1, r0
    return nrfx_flag32_alloc(&m_cb.available_channels_mask, p_channel);
    3f4a:	4801      	ldr	r0, [pc, #4]	; (3f50 <nrfx_gpiote_channel_alloc+0x8>)
    3f4c:	f7ff bce0 	b.w	3910 <nrfx_flag32_alloc>
    3f50:	20000080 	.word	0x20000080

00003f54 <nrfx_gpiote_trigger_enable>:
{
    3f54:	b510      	push	{r4, lr}
    3f56:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    3f58:	f7ff fe12 	bl	3b80 <pin_in_use_by_te>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    3f5c:	f102 0408 	add.w	r4, r2, #8
    3f60:	4b1c      	ldr	r3, [pc, #112]	; (3fd4 <nrfx_gpiote_trigger_enable+0x80>)
    3f62:	f833 3014 	ldrh.w	r3, [r3, r4, lsl #1]
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    3f66:	b1e0      	cbz	r0, 3fa2 <nrfx_gpiote_trigger_enable+0x4e>
    3f68:	f013 0402 	ands.w	r4, r3, #2
    3f6c:	d119      	bne.n	3fa2 <nrfx_gpiote_trigger_enable+0x4e>
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    3f6e:	0b5b      	lsrs	r3, r3, #13
#endif

NRF_STATIC_INLINE nrf_gpiote_event_t nrf_gpiote_in_event_get(uint8_t index)
{
    NRFX_ASSERT(index < GPIOTE_CH_NUM);
    return (nrf_gpiote_event_t)NRFX_OFFSETOF(NRF_GPIOTE_Type, EVENTS_IN[index]);
    3f70:	009a      	lsls	r2, r3, #2
    return ((uint32_t)p_reg + event);
    3f72:	f102 4080 	add.w	r0, r2, #1073741824	; 0x40000000
    3f76:	f500 40c2 	add.w	r0, r0, #24832	; 0x6100
    3f7a:	f102 4280 	add.w	r2, r2, #1073741824	; 0x40000000
    3f7e:	f502 42c0 	add.w	r2, r2, #24576	; 0x6000
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    3f82:	6004      	str	r4, [r0, #0]
    3f84:	6800      	ldr	r0, [r0, #0]
   p_reg->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event;
    3f86:	f8d2 0510 	ldr.w	r0, [r2, #1296]	; 0x510
    3f8a:	f040 0001 	orr.w	r0, r0, #1
    3f8e:	f8c2 0510 	str.w	r0, [r2, #1296]	; 0x510
        if (int_enable)
    3f92:	b129      	cbz	r1, 3fa0 <nrfx_gpiote_trigger_enable+0x4c>
            nrf_gpiote_int_enable(NRF_GPIOTE, NRFX_BIT(ch));
    3f94:	2201      	movs	r2, #1
    3f96:	fa02 f303 	lsl.w	r3, r2, r3
    p_reg->INTENSET = mask;
    3f9a:	4a0f      	ldr	r2, [pc, #60]	; (3fd8 <nrfx_gpiote_trigger_enable+0x84>)
    3f9c:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
}
    3fa0:	bd10      	pop	{r4, pc}
    nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    3fa2:	f3c3 0382 	ubfx	r3, r3, #2, #3
    if (trigger == NRFX_GPIOTE_TRIGGER_LOW)
    3fa6:	2b04      	cmp	r3, #4
    3fa8:	d010      	beq.n	3fcc <nrfx_gpiote_trigger_enable+0x78>
    else if (trigger == NRFX_GPIOTE_TRIGGER_HIGH)
    3faa:	2b05      	cmp	r3, #5
    3fac:	d010      	beq.n	3fd0 <nrfx_gpiote_trigger_enable+0x7c>
    return p_reg->IN;
    3fae:	f04f 43a0 	mov.w	r3, #1342177280	; 0x50000000
    3fb2:	f8d3 1510 	ldr.w	r1, [r3, #1296]	; 0x510
    *p_pin = pin_number & 0x1F;
    3fb6:	f002 031f 	and.w	r3, r2, #31
    return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL);
    3fba:	40d9      	lsrs	r1, r3
    3fbc:	f001 0101 	and.w	r1, r1, #1
        sense = nrf_gpio_pin_read(pin) ? NRF_GPIO_PIN_SENSE_LOW : NRF_GPIO_PIN_SENSE_HIGH;
    3fc0:	3102      	adds	r1, #2
}
    3fc2:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
        nrf_gpio_cfg_sense_set(pin, get_initial_sense(pin));
    3fc6:	4610      	mov	r0, r2
    3fc8:	f002 b9f0 	b.w	63ac <nrf_gpio_cfg_sense_set>
        sense = NRF_GPIO_PIN_SENSE_LOW;
    3fcc:	2103      	movs	r1, #3
    3fce:	e7f8      	b.n	3fc2 <nrfx_gpiote_trigger_enable+0x6e>
        sense = NRF_GPIO_PIN_SENSE_HIGH;
    3fd0:	2102      	movs	r1, #2
    3fd2:	e7f6      	b.n	3fc2 <nrfx_gpiote_trigger_enable+0x6e>
    3fd4:	20000030 	.word	0x20000030
    3fd8:	40006000 	.word	0x40006000

00003fdc <nrfx_gpiote_trigger_disable>:
{
    3fdc:	b508      	push	{r3, lr}
    3fde:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    3fe0:	f7ff fdce 	bl	3b80 <pin_in_use_by_te>
    3fe4:	b1c0      	cbz	r0, 4018 <nrfx_gpiote_trigger_disable+0x3c>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    3fe6:	f102 0108 	add.w	r1, r2, #8
    3fea:	4b0e      	ldr	r3, [pc, #56]	; (4024 <nrfx_gpiote_trigger_disable+0x48>)
    3fec:	f833 3011 	ldrh.w	r3, [r3, r1, lsl #1]
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    3ff0:	0799      	lsls	r1, r3, #30
    3ff2:	d411      	bmi.n	4018 <nrfx_gpiote_trigger_disable+0x3c>
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    3ff4:	0b5b      	lsrs	r3, r3, #13
        nrf_gpiote_int_disable(NRF_GPIOTE, NRFX_BIT(ch));
    3ff6:	2201      	movs	r2, #1
    3ff8:	409a      	lsls	r2, r3
    p_reg->INTENCLR = mask;
    3ffa:	009b      	lsls	r3, r3, #2
    3ffc:	490a      	ldr	r1, [pc, #40]	; (4028 <nrfx_gpiote_trigger_disable+0x4c>)
    3ffe:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    4002:	f503 43c0 	add.w	r3, r3, #24576	; 0x6000
    4006:	f8c1 2308 	str.w	r2, [r1, #776]	; 0x308
   p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk;
    400a:	f8d3 2510 	ldr.w	r2, [r3, #1296]	; 0x510
    400e:	f022 0203 	bic.w	r2, r2, #3
    4012:	f8c3 2510 	str.w	r2, [r3, #1296]	; 0x510
}
    4016:	bd08      	pop	{r3, pc}
    4018:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
        nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE);
    401c:	2100      	movs	r1, #0
    401e:	4610      	mov	r0, r2
    4020:	f002 b9c4 	b.w	63ac <nrf_gpio_cfg_sense_set>
    4024:	20000030 	.word	0x20000030
    4028:	40006000 	.word	0x40006000

0000402c <nrfx_gpiote_pin_uninit>:
    return m_cb.pin_flags[pin] & PIN_FLAG_IN_USE;
    402c:	4b0d      	ldr	r3, [pc, #52]	; (4064 <nrfx_gpiote_pin_uninit+0x38>)
    402e:	f100 0208 	add.w	r2, r0, #8
{
    4032:	b510      	push	{r4, lr}
    return m_cb.pin_flags[pin] & PIN_FLAG_IN_USE;
    4034:	f833 3012 	ldrh.w	r3, [r3, r2, lsl #1]
    if (!pin_in_use(pin))
    4038:	07db      	lsls	r3, r3, #31
{
    403a:	4604      	mov	r4, r0
    if (!pin_in_use(pin))
    403c:	d50f      	bpl.n	405e <nrfx_gpiote_pin_uninit+0x32>
    nrfx_gpiote_trigger_disable(pin);
    403e:	f7ff ffcd 	bl	3fdc <nrfx_gpiote_trigger_disable>
    pin_handler_trigger_uninit(pin);
    4042:	4620      	mov	r0, r4
    *p_pin = pin_number & 0x1F;
    4044:	f004 041f 	and.w	r4, r4, #31
    4048:	f7ff fdec 	bl	3c24 <pin_handler_trigger_uninit>
    reg->PIN_CNF[pin_number] = cnf;
    404c:	f504 74e0 	add.w	r4, r4, #448	; 0x1c0
    4050:	f04f 43a0 	mov.w	r3, #1342177280	; 0x50000000
    4054:	2202      	movs	r2, #2
    4056:	f843 2024 	str.w	r2, [r3, r4, lsl #2]
    405a:	4803      	ldr	r0, [pc, #12]	; (4068 <nrfx_gpiote_pin_uninit+0x3c>)
}
    405c:	bd10      	pop	{r4, pc}
        return NRFX_ERROR_INVALID_PARAM;
    405e:	4803      	ldr	r0, [pc, #12]	; (406c <nrfx_gpiote_pin_uninit+0x40>)
    4060:	e7fc      	b.n	405c <nrfx_gpiote_pin_uninit+0x30>
    4062:	bf00      	nop
    4064:	20000030 	.word	0x20000030
    4068:	0bad0000 	.word	0x0bad0000
    406c:	0bad0004 	.word	0x0bad0004

00004070 <nrfx_gpiote_irq_handler>:
        call_handler(pin, gpiote_polarity_to_trigger(polarity));
    }
}

void nrfx_gpiote_irq_handler(void)
{
    4070:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    4074:	4b4e      	ldr	r3, [pc, #312]	; (41b0 <nrfx_gpiote_irq_handler+0x140>)
    return p_reg->INTENSET & mask;
    4076:	484f      	ldr	r0, [pc, #316]	; (41b4 <nrfx_gpiote_irq_handler+0x144>)
    uint32_t i;
    nrf_gpiote_event_t event = NRF_GPIOTE_EVENT_IN_0;
    uint32_t mask = (uint32_t)NRF_GPIOTE_INT_IN0_MASK;

    /* collect status of all GPIOTE pin events. Processing is done once all are collected and cleared.*/
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    4078:	494f      	ldr	r1, [pc, #316]	; (41b8 <nrfx_gpiote_irq_handler+0x148>)
    uint32_t status = 0;
    407a:	2500      	movs	r5, #0
    uint32_t mask = (uint32_t)NRF_GPIOTE_INT_IN0_MASK;
    407c:	2201      	movs	r2, #1
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    407e:	462c      	mov	r4, r5
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    4080:	681e      	ldr	r6, [r3, #0]
    {
        if (nrf_gpiote_event_check(NRF_GPIOTE, event) &&
    4082:	b136      	cbz	r6, 4092 <nrfx_gpiote_irq_handler+0x22>
    return p_reg->INTENSET & mask;
    4084:	f8d0 6304 	ldr.w	r6, [r0, #772]	; 0x304
    4088:	4216      	tst	r6, r2
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    408a:	bf1e      	ittt	ne
    408c:	601c      	strne	r4, [r3, #0]
    408e:	681e      	ldrne	r6, [r3, #0]
            nrf_gpiote_int_enable_check(NRF_GPIOTE, mask))
        {
            nrf_gpiote_event_clear(NRF_GPIOTE, event);
            status |= mask;
    4090:	4315      	orrne	r5, r2
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    4092:	3304      	adds	r3, #4
    4094:	428b      	cmp	r3, r1
        }
        mask <<= 1;
    4096:	ea4f 0242 	mov.w	r2, r2, lsl #1
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    409a:	d1f1      	bne.n	4080 <nrfx_gpiote_irq_handler+0x10>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    409c:	4b45      	ldr	r3, [pc, #276]	; (41b4 <nrfx_gpiote_irq_handler+0x144>)
    409e:	f8d3 317c 	ldr.w	r3, [r3, #380]	; 0x17c
         * in ascending order. */
        event = (nrf_gpiote_event_t)((uint32_t)event + sizeof(uint32_t));
    }

    /* handle PORT event */
    if (nrf_gpiote_event_check(NRF_GPIOTE, NRF_GPIOTE_EVENT_PORT))
    40a2:	b1bb      	cbz	r3, 40d4 <nrfx_gpiote_irq_handler+0x64>
        *p_masks = gpio_regs[i]->LATCH;
    40a4:	f04f 46a0 	mov.w	r6, #1342177280	; 0x50000000
    40a8:	f8d6 3520 	ldr.w	r3, [r6, #1312]	; 0x520
    40ac:	9301      	str	r3, [sp, #4]
        gpio_regs[i]->LATCH = *p_masks;
    40ae:	f8c6 3520 	str.w	r3, [r6, #1312]	; 0x520
__STATIC_INLINE void nrf_bitmask_bit_clear(uint32_t bit, void * p_mask)
{
    uint8_t * p_mask8 = (uint8_t *)p_mask;
    uint32_t byte_idx = BITMASK_BYTE_GET(bit);
    bit = BITMASK_RELBIT_GET(bit);
    p_mask8[byte_idx] &= ~(1 << bit);
    40b2:	af01      	add	r7, sp, #4
    40b4:	f04f 0801 	mov.w	r8, #1
            while (latch[i])
    40b8:	9c01      	ldr	r4, [sp, #4]
    40ba:	b96c      	cbnz	r4, 40d8 <nrfx_gpiote_irq_handler+0x68>
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    40bc:	4b3d      	ldr	r3, [pc, #244]	; (41b4 <nrfx_gpiote_irq_handler+0x144>)
    40be:	f8c3 417c 	str.w	r4, [r3, #380]	; 0x17c
    40c2:	f8d3 317c 	ldr.w	r3, [r3, #380]	; 0x17c
        *p_masks = gpio_regs[i]->LATCH;
    40c6:	f8d6 3520 	ldr.w	r3, [r6, #1312]	; 0x520
    40ca:	9301      	str	r3, [sp, #4]
        gpio_regs[i]->LATCH = *p_masks;
    40cc:	f8c6 3520 	str.w	r3, [r6, #1312]	; 0x520
        if (latch[port_idx])
    40d0:	2b00      	cmp	r3, #0
    40d2:	d1ee      	bne.n	40b2 <nrfx_gpiote_irq_handler+0x42>
        mask &= ~NRFX_BIT(ch);
    40d4:	2401      	movs	r4, #1
    40d6:	e066      	b.n	41a6 <nrfx_gpiote_irq_handler+0x136>
                uint32_t pin = NRF_CTZ(latch[i]);
    40d8:	fa94 f4a4 	rbit	r4, r4
    40dc:	fab4 f484 	clz	r4, r4
                nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    40e0:	4a36      	ldr	r2, [pc, #216]	; (41bc <nrfx_gpiote_irq_handler+0x14c>)
    40e2:	f104 0308 	add.w	r3, r4, #8
    uint32_t byte_idx = BITMASK_BYTE_GET(bit);
    40e6:	08e0      	lsrs	r0, r4, #3
    40e8:	f832 1013 	ldrh.w	r1, [r2, r3, lsl #1]
    bit = BITMASK_RELBIT_GET(bit);
    40ec:	f004 0307 	and.w	r3, r4, #7
    p_mask8[byte_idx] &= ~(1 << bit);
    40f0:	fa08 f203 	lsl.w	r2, r8, r3
    40f4:	5c3b      	ldrb	r3, [r7, r0]
    40f6:	ea23 0302 	bic.w	r3, r3, r2
    40fa:	543b      	strb	r3, [r7, r0]
    40fc:	00a3      	lsls	r3, r4, #2
    40fe:	f103 49a0 	add.w	r9, r3, #1342177280	; 0x50000000
    4102:	f3c1 0a82 	ubfx	sl, r1, #2, #3
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    4106:	f8d9 2700 	ldr.w	r2, [r9, #1792]	; 0x700
    if (is_level(trigger))
    410a:	06cb      	lsls	r3, r1, #27
                nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    410c:	46d3      	mov	fp, sl
                                   GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos);
    410e:	f3c2 4201 	ubfx	r2, r2, #16, #2
    if (is_level(trigger))
    4112:	d518      	bpl.n	4146 <nrfx_gpiote_irq_handler+0xd6>
        call_handler(pin, trigger);
    4114:	4659      	mov	r1, fp
    4116:	4620      	mov	r0, r4
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    4118:	fa5f fa82 	uxtb.w	sl, r2
    411c:	f7ff fd3a 	bl	3b94 <call_handler>
    4120:	f8d9 3700 	ldr.w	r3, [r9, #1792]	; 0x700
        if (nrf_gpio_pin_sense_get(pin) == sense)
    4124:	f3c3 4301 	ubfx	r3, r3, #16, #2
    4128:	459a      	cmp	sl, r3
    412a:	d107      	bne.n	413c <nrfx_gpiote_irq_handler+0xcc>
            nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE);
    412c:	2100      	movs	r1, #0
    412e:	4620      	mov	r0, r4
    4130:	f002 f93c 	bl	63ac <nrf_gpio_cfg_sense_set>
            nrf_gpio_cfg_sense_set(pin, sense);
    4134:	4651      	mov	r1, sl
    4136:	4620      	mov	r0, r4
    4138:	f002 f938 	bl	63ac <nrf_gpio_cfg_sense_set>
    reg->LATCH = (1 << pin_number);
    413c:	fa08 f404 	lsl.w	r4, r8, r4
    4140:	f8c6 4520 	str.w	r4, [r6, #1312]	; 0x520
}
    4144:	e7b8      	b.n	40b8 <nrfx_gpiote_irq_handler+0x48>
                NRF_GPIO_PIN_SENSE_LOW : NRF_GPIO_PIN_SENSE_HIGH;
    4146:	2a02      	cmp	r2, #2
        nrf_gpio_cfg_sense_set(pin, next_sense);
    4148:	bf0c      	ite	eq
    414a:	2103      	moveq	r1, #3
    414c:	2102      	movne	r1, #2
    414e:	4620      	mov	r0, r4
    4150:	f002 f92c 	bl	63ac <nrf_gpio_cfg_sense_set>
        if ((trigger == NRFX_GPIOTE_TRIGGER_TOGGLE) ||
    4154:	f1ba 0f03 	cmp.w	sl, #3
    4158:	d004      	beq.n	4164 <nrfx_gpiote_irq_handler+0xf4>
    415a:	2a02      	cmp	r2, #2
    415c:	d107      	bne.n	416e <nrfx_gpiote_irq_handler+0xfe>
            (sense == NRF_GPIO_PIN_SENSE_HIGH && trigger == NRFX_GPIOTE_TRIGGER_LOTOHI) ||
    415e:	f1ba 0f01 	cmp.w	sl, #1
            (sense == NRF_GPIO_PIN_SENSE_LOW && trigger == NRFX_GPIOTE_TRIGGER_HITOLO))
    4162:	d1eb      	bne.n	413c <nrfx_gpiote_irq_handler+0xcc>
            call_handler(pin, trigger);
    4164:	4659      	mov	r1, fp
    4166:	4620      	mov	r0, r4
    4168:	f7ff fd14 	bl	3b94 <call_handler>
    416c:	e7e6      	b.n	413c <nrfx_gpiote_irq_handler+0xcc>
            (sense == NRF_GPIO_PIN_SENSE_HIGH && trigger == NRFX_GPIOTE_TRIGGER_LOTOHI) ||
    416e:	2a03      	cmp	r2, #3
    4170:	d1e4      	bne.n	413c <nrfx_gpiote_irq_handler+0xcc>
            (sense == NRF_GPIO_PIN_SENSE_LOW && trigger == NRFX_GPIOTE_TRIGGER_HITOLO))
    4172:	f1ba 0f02 	cmp.w	sl, #2
    4176:	e7f4      	b.n	4162 <nrfx_gpiote_irq_handler+0xf2>
        uint32_t ch = NRF_CTZ(mask);
    4178:	fa95 f3a5 	rbit	r3, r5
    417c:	fab3 f383 	clz	r3, r3
        mask &= ~NRFX_BIT(ch);
    4180:	fa04 f203 	lsl.w	r2, r4, r3
    4184:	009b      	lsls	r3, r3, #2
    4186:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    418a:	f503 43c0 	add.w	r3, r3, #24576	; 0x6000
    418e:	ea25 0502 	bic.w	r5, r5, r2
    return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
    4192:	f8d3 0510 	ldr.w	r0, [r3, #1296]	; 0x510
    return (nrf_gpiote_polarity_t)((p_reg->CONFIG[idx] & GPIOTE_CONFIG_POLARITY_Msk) >>
    4196:	f8d3 1510 	ldr.w	r1, [r3, #1296]	; 0x510
        call_handler(pin, gpiote_polarity_to_trigger(polarity));
    419a:	f3c0 2004 	ubfx	r0, r0, #8, #5
    419e:	f3c1 4101 	ubfx	r1, r1, #16, #2
    41a2:	f7ff fcf7 	bl	3b94 <call_handler>
    while (mask)
    41a6:	2d00      	cmp	r5, #0
    41a8:	d1e6      	bne.n	4178 <nrfx_gpiote_irq_handler+0x108>
        port_event_handle();
    }

    /* Process pin events. */
    gpiote_evt_handle(status);
}
    41aa:	b003      	add	sp, #12
    41ac:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    41b0:	40006100 	.word	0x40006100
    41b4:	40006000 	.word	0x40006000
    41b8:	40006120 	.word	0x40006120
    41bc:	20000030 	.word	0x20000030

000041c0 <nvmc_word_write>:
    41c0:	4a04      	ldr	r2, [pc, #16]	; (41d4 <nvmc_word_write+0x14>)
    41c2:	f8d2 3400 	ldr.w	r3, [r2, #1024]	; 0x400
{
#if defined(NRF9160_XXAA)
    while (!nrf_nvmc_write_ready_check(NRF_NVMC))
    {}
#else
    while (!nrf_nvmc_ready_check(NRF_NVMC))
    41c6:	07db      	lsls	r3, r3, #31
    41c8:	d5fb      	bpl.n	41c2 <nvmc_word_write+0x2>
    {}
#endif

    *(volatile uint32_t *)addr = value;
    41ca:	6001      	str	r1, [r0, #0]
  __ASM volatile ("dmb 0xF":::"memory");
    41cc:	f3bf 8f5f 	dmb	sy
    __DMB();
}
    41d0:	4770      	bx	lr
    41d2:	bf00      	nop
    41d4:	4001e000 	.word	0x4001e000

000041d8 <nrfx_nvmc_page_erase>:
NRF_STATIC_INLINE uint32_t nrf_ficr_codepagesize_get(NRF_FICR_Type const * p_reg)
{
#if defined(FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Msk)
    return p_reg->INFO.CODEPAGESIZE;
#else
    return p_reg->CODEPAGESIZE;
    41d8:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    41dc:	691a      	ldr	r2, [r3, #16]
    return !(addr % flash_page_size_get());
    41de:	fbb0 f3f2 	udiv	r3, r0, r2
    41e2:	fb02 0313 	mls	r3, r2, r3, r0

nrfx_err_t nrfx_nvmc_page_erase(uint32_t addr)
{
    NRFX_ASSERT(is_valid_address(addr, false));

    if (!is_page_aligned_check(addr))
    41e6:	b973      	cbnz	r3, 4206 <nrfx_nvmc_page_erase+0x2e>
#endif

NRF_STATIC_INLINE void nrf_nvmc_mode_set(NRF_NVMC_Type * p_reg,
                                         nrf_nvmc_mode_t mode)
{
    p_reg->CONFIG = (uint32_t)mode;
    41e8:	4b08      	ldr	r3, [pc, #32]	; (420c <nrfx_nvmc_page_erase+0x34>)
    41ea:	2202      	movs	r2, #2
    41ec:	f8c3 2504 	str.w	r2, [r3, #1284]	; 0x504
    else
    {
        p_reg->ERASEPCR1 = page_addr;
    }
#elif defined(NRF52_SERIES)
    p_reg->ERASEPAGE = page_addr;
    41f0:	f8c3 0508 	str.w	r0, [r3, #1288]	; 0x508
    return (bool)(p_reg->READY & NVMC_READY_READY_Msk);
    41f4:	f8d3 2400 	ldr.w	r2, [r3, #1024]	; 0x400
        return NRFX_ERROR_INVALID_ADDR;
    }

    nvmc_erase_mode_set();
    nrf_nvmc_page_erase_start(NRF_NVMC, addr);
    while (!nrf_nvmc_ready_check(NRF_NVMC))
    41f8:	07d2      	lsls	r2, r2, #31
    41fa:	d5fb      	bpl.n	41f4 <nrfx_nvmc_page_erase+0x1c>
    p_reg->CONFIG = (uint32_t)mode;
    41fc:	2200      	movs	r2, #0
    {}
    nvmc_readonly_mode_set();

    return NRFX_SUCCESS;
    41fe:	4804      	ldr	r0, [pc, #16]	; (4210 <nrfx_nvmc_page_erase+0x38>)
    4200:	f8c3 2504 	str.w	r2, [r3, #1284]	; 0x504
    4204:	4770      	bx	lr
        return NRFX_ERROR_INVALID_ADDR;
    4206:	4803      	ldr	r0, [pc, #12]	; (4214 <nrfx_nvmc_page_erase+0x3c>)
}
    4208:	4770      	bx	lr
    420a:	bf00      	nop
    420c:	4001e000 	.word	0x4001e000
    4210:	0bad0000 	.word	0x0bad0000
    4214:	0bad000a 	.word	0x0bad000a

00004218 <nrfx_nvmc_word_write>:

    nrfx_nvmc_word_write(aligned_addr, partial_word_create(addr, (const uint8_t *)&value, 2));
}

void nrfx_nvmc_word_write(uint32_t addr, uint32_t value)
{
    4218:	b510      	push	{r4, lr}
    421a:	4c05      	ldr	r4, [pc, #20]	; (4230 <nrfx_nvmc_word_write+0x18>)
    421c:	2301      	movs	r3, #1
    421e:	f8c4 3504 	str.w	r3, [r4, #1284]	; 0x504
    NRFX_ASSERT(is_valid_address(addr, true));
    NRFX_ASSERT(nrfx_is_word_aligned((void const *)addr));

    nvmc_write_mode_set();

    nvmc_word_write(addr, value);
    4222:	f7ff ffcd 	bl	41c0 <nvmc_word_write>
    4226:	2300      	movs	r3, #0
    4228:	f8c4 3504 	str.w	r3, [r4, #1284]	; 0x504

    nvmc_readonly_mode_set();
}
    422c:	bd10      	pop	{r4, pc}
    422e:	bf00      	nop
    4230:	4001e000 	.word	0x4001e000

00004234 <nrfx_ppi_channel_alloc>:
    nrfx_flag32_init(&m_groups_allocated, NRFX_PPI_ALL_APP_GROUPS_MASK);
}


nrfx_err_t nrfx_ppi_channel_alloc(nrf_ppi_channel_t * p_channel)
{
    4234:	4601      	mov	r1, r0
    return nrfx_flag32_alloc(&m_channels_allocated, (uint8_t *)p_channel);
    4236:	4801      	ldr	r0, [pc, #4]	; (423c <nrfx_ppi_channel_alloc+0x8>)
    4238:	f7ff bb6a 	b.w	3910 <nrfx_flag32_alloc>
    423c:	2000008c 	.word	0x2000008c

00004240 <_DoInit>:
                      _DoInit();                                                                     \
                    }                                                                                \
                  } while (0);                                                                       \
                }

static void _DoInit(void) {
    4240:	b510      	push	{r4, lr}
  volatile SEGGER_RTT_CB* p;   // Volatile to make sure that compiler cannot change the order of accesses to the control block
  //
  // Initialize control block
  //
  p                     = (volatile SEGGER_RTT_CB*)((char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access control block uncached so that nothing in the cache ever becomes dirty and all changes are visible in HW directly
  p->MaxNumUpBuffers    = SEGGER_RTT_MAX_NUM_UP_BUFFERS;
    4242:	4c14      	ldr	r4, [pc, #80]	; (4294 <_DoInit+0x54>)
  p->MaxNumDownBuffers  = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS;
  //
  // Initialize up buffer 0
  //
  p->aUp[0].sName         = "Terminal";
    4244:	4a14      	ldr	r2, [pc, #80]	; (4298 <_DoInit+0x58>)
  //
  // Finish initialization of the control block.
  // Copy Id string in three steps to make sure "SEGGER RTT" is not found
  // in initializer memory (usually flash) by J-Link
  //
  STRCPY((char*)&p->acID[7], "RTT");
    4246:	4915      	ldr	r1, [pc, #84]	; (429c <_DoInit+0x5c>)
  p->MaxNumUpBuffers    = SEGGER_RTT_MAX_NUM_UP_BUFFERS;
    4248:	2303      	movs	r3, #3
    424a:	6123      	str	r3, [r4, #16]
  p->MaxNumDownBuffers  = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS;
    424c:	6163      	str	r3, [r4, #20]
  p->aUp[0].pBuffer       = _acUpBuffer;
    424e:	4b14      	ldr	r3, [pc, #80]	; (42a0 <_DoInit+0x60>)
  p->aUp[0].sName         = "Terminal";
    4250:	61a2      	str	r2, [r4, #24]
  p->aUp[0].pBuffer       = _acUpBuffer;
    4252:	61e3      	str	r3, [r4, #28]
  p->aUp[0].SizeOfBuffer  = BUFFER_SIZE_UP;
    4254:	f44f 6380 	mov.w	r3, #1024	; 0x400
    4258:	6223      	str	r3, [r4, #32]
  p->aUp[0].RdOff         = 0u;
    425a:	2300      	movs	r3, #0
    425c:	62a3      	str	r3, [r4, #40]	; 0x28
  p->aUp[0].WrOff         = 0u;
    425e:	6263      	str	r3, [r4, #36]	; 0x24
  p->aUp[0].Flags         = SEGGER_RTT_MODE_DEFAULT;
    4260:	62e3      	str	r3, [r4, #44]	; 0x2c
  p->aDown[0].sName         = "Terminal";
    4262:	6622      	str	r2, [r4, #96]	; 0x60
  p->aDown[0].pBuffer       = _acDownBuffer;
    4264:	4a0f      	ldr	r2, [pc, #60]	; (42a4 <_DoInit+0x64>)
    4266:	6662      	str	r2, [r4, #100]	; 0x64
  STRCPY((char*)&p->acID[7], "RTT");
    4268:	1de0      	adds	r0, r4, #7
  p->aDown[0].SizeOfBuffer  = BUFFER_SIZE_DOWN;
    426a:	2210      	movs	r2, #16
    426c:	66a2      	str	r2, [r4, #104]	; 0x68
  p->aDown[0].RdOff         = 0u;
    426e:	6723      	str	r3, [r4, #112]	; 0x70
  p->aDown[0].WrOff         = 0u;
    4270:	66e3      	str	r3, [r4, #108]	; 0x6c
  p->aDown[0].Flags         = SEGGER_RTT_MODE_DEFAULT;
    4272:	6763      	str	r3, [r4, #116]	; 0x74
  STRCPY((char*)&p->acID[7], "RTT");
    4274:	f001 fcec 	bl	5c50 <strcpy>
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
    4278:	f3bf 8f5f 	dmb	sy
  STRCPY((char*)&p->acID[0], "SEGGER");
    427c:	490a      	ldr	r1, [pc, #40]	; (42a8 <_DoInit+0x68>)
    427e:	4620      	mov	r0, r4
    4280:	f001 fce6 	bl	5c50 <strcpy>
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
    4284:	f3bf 8f5f 	dmb	sy
  p->acID[6] = ' ';
    4288:	2320      	movs	r3, #32
    428a:	71a3      	strb	r3, [r4, #6]
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
    428c:	f3bf 8f5f 	dmb	sy
}
    4290:	bd10      	pop	{r4, pc}
    4292:	bf00      	nop
    4294:	20000e50 	.word	0x20000e50
    4298:	00007520 	.word	0x00007520
    429c:	00007529 	.word	0x00007529
    42a0:	2000100e 	.word	0x2000100e
    42a4:	20000ffe 	.word	0x20000ffe
    42a8:	0000752d 	.word	0x0000752d

000042ac <z_sys_init_run_level>:
		/* End marker */
		__init_end,
	};
	const struct init_entry *entry;

	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    42ac:	4b0e      	ldr	r3, [pc, #56]	; (42e8 <z_sys_init_run_level+0x3c>)
{
    42ae:	b570      	push	{r4, r5, r6, lr}
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    42b0:	f853 4020 	ldr.w	r4, [r3, r0, lsl #2]
    42b4:	3001      	adds	r0, #1
    42b6:	f853 6020 	ldr.w	r6, [r3, r0, lsl #2]
    42ba:	42a6      	cmp	r6, r4
    42bc:	d800      	bhi.n	42c0 <z_sys_init_run_level+0x14>
				dev->state->init_res = rc;
			}
			dev->state->initialized = true;
		}
	}
}
    42be:	bd70      	pop	{r4, r5, r6, pc}
		int rc = entry->init(dev);
    42c0:	e9d4 3500 	ldrd	r3, r5, [r4]
    42c4:	4628      	mov	r0, r5
    42c6:	4798      	blx	r3
		if (dev != NULL) {
    42c8:	b165      	cbz	r5, 42e4 <z_sys_init_run_level+0x38>
				dev->state->init_res = rc;
    42ca:	68eb      	ldr	r3, [r5, #12]
			if (rc != 0) {
    42cc:	b130      	cbz	r0, 42dc <z_sys_init_run_level+0x30>
				if (rc < 0) {
    42ce:	2800      	cmp	r0, #0
    42d0:	bfb8      	it	lt
    42d2:	4240      	neglt	r0, r0
				dev->state->init_res = rc;
    42d4:	28ff      	cmp	r0, #255	; 0xff
    42d6:	bfa8      	it	ge
    42d8:	20ff      	movge	r0, #255	; 0xff
    42da:	7018      	strb	r0, [r3, #0]
			dev->state->initialized = true;
    42dc:	785a      	ldrb	r2, [r3, #1]
    42de:	f042 0201 	orr.w	r2, r2, #1
    42e2:	705a      	strb	r2, [r3, #1]
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    42e4:	3408      	adds	r4, #8
    42e6:	e7e8      	b.n	42ba <z_sys_init_run_level+0xe>
    42e8:	000069a8 	.word	0x000069a8

000042ec <z_impl_device_get_binding>:

const struct device *z_impl_device_get_binding(const char *name)
{
    42ec:	b570      	push	{r4, r5, r6, lr}
	const struct device *dev;

	/* A null string identifies no device.  So does an empty
	 * string.
	 */
	if ((name == NULL) || (name[0] == '\0')) {
    42ee:	4605      	mov	r5, r0
    42f0:	b910      	cbnz	r0, 42f8 <z_impl_device_get_binding+0xc>
		return NULL;
    42f2:	2400      	movs	r4, #0
			return dev;
		}
	}

	return NULL;
}
    42f4:	4620      	mov	r0, r4
    42f6:	bd70      	pop	{r4, r5, r6, pc}
	if ((name == NULL) || (name[0] == '\0')) {
    42f8:	7803      	ldrb	r3, [r0, #0]
    42fa:	2b00      	cmp	r3, #0
    42fc:	d0f9      	beq.n	42f2 <z_impl_device_get_binding+0x6>
	for (dev = __device_start; dev != __device_end; dev++) {
    42fe:	4c0e      	ldr	r4, [pc, #56]	; (4338 <z_impl_device_get_binding+0x4c>)
    4300:	4e0e      	ldr	r6, [pc, #56]	; (433c <z_impl_device_get_binding+0x50>)
    4302:	42b4      	cmp	r4, r6
    4304:	d108      	bne.n	4318 <z_impl_device_get_binding+0x2c>
	for (dev = __device_start; dev != __device_end; dev++) {
    4306:	4c0c      	ldr	r4, [pc, #48]	; (4338 <z_impl_device_get_binding+0x4c>)
    4308:	42b4      	cmp	r4, r6
    430a:	d0f2      	beq.n	42f2 <z_impl_device_get_binding+0x6>
		if (z_device_is_ready(dev) && (strcmp(name, dev->name) == 0)) {
    430c:	4620      	mov	r0, r4
    430e:	f002 f871 	bl	63f4 <z_device_is_ready>
    4312:	b950      	cbnz	r0, 432a <z_impl_device_get_binding+0x3e>
	for (dev = __device_start; dev != __device_end; dev++) {
    4314:	3418      	adds	r4, #24
    4316:	e7f7      	b.n	4308 <z_impl_device_get_binding+0x1c>
		if (z_device_is_ready(dev) && (dev->name == name)) {
    4318:	4620      	mov	r0, r4
    431a:	f002 f86b 	bl	63f4 <z_device_is_ready>
    431e:	b110      	cbz	r0, 4326 <z_impl_device_get_binding+0x3a>
    4320:	6823      	ldr	r3, [r4, #0]
    4322:	42ab      	cmp	r3, r5
    4324:	d0e6      	beq.n	42f4 <z_impl_device_get_binding+0x8>
	for (dev = __device_start; dev != __device_end; dev++) {
    4326:	3418      	adds	r4, #24
    4328:	e7eb      	b.n	4302 <z_impl_device_get_binding+0x16>
		if (z_device_is_ready(dev) && (strcmp(name, dev->name) == 0)) {
    432a:	6821      	ldr	r1, [r4, #0]
    432c:	4628      	mov	r0, r5
    432e:	f001 fca0 	bl	5c72 <strcmp>
    4332:	2800      	cmp	r0, #0
    4334:	d1ee      	bne.n	4314 <z_impl_device_get_binding+0x28>
    4336:	e7dd      	b.n	42f4 <z_impl_device_get_binding+0x8>
    4338:	00006474 	.word	0x00006474
    433c:	000064d4 	.word	0x000064d4

00004340 <z_fatal_error>:
	return 0;
#endif
}

void z_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
{
    4340:	b573      	push	{r0, r1, r4, r5, r6, lr}
    4342:	4604      	mov	r4, r0
    4344:	460d      	mov	r5, r1
	__asm__ volatile(
    4346:	f04f 0320 	mov.w	r3, #32
    434a:	f3ef 8611 	mrs	r6, BASEPRI
    434e:	f383 8812 	msr	BASEPRI_MAX, r3
    4352:	f3bf 8f6f 	isb	sy
	switch (reason) {
    4356:	2804      	cmp	r0, #4
    4358:	bf96      	itet	ls
    435a:	4b12      	ldrls	r3, [pc, #72]	; (43a4 <z_fatal_error+0x64>)
    435c:	4b12      	ldrhi	r3, [pc, #72]	; (43a8 <z_fatal_error+0x68>)
	return 0;
    435e:	f853 3020 	ldrls.w	r3, [r3, r0, lsl #2]
			k_current_get() : NULL;

	/* twister looks for the "ZEPHYR FATAL ERROR" string, don't
	 * change it without also updating twister
	 */
	LOG_ERR(">>> ZEPHYR FATAL ERROR %d: %s on CPU %d", reason,
    4362:	2200      	movs	r2, #0
    4364:	9200      	str	r2, [sp, #0]
    4366:	2145      	movs	r1, #69	; 0x45
    4368:	4602      	mov	r2, r0
    436a:	4810      	ldr	r0, [pc, #64]	; (43ac <z_fatal_error+0x6c>)
    436c:	f001 fbd4 	bl	5b18 <z_log_minimal_printk>
	 * an IRQ or exception was being handled, or thread context.
	 *
	 * See #17656
	 */
#if defined(CONFIG_ARCH_HAS_NESTED_EXCEPTION_DETECTION)
	if ((esf != NULL) && arch_is_in_nested_exception(esf)) {
    4370:	b13d      	cbz	r5, 4382 <z_fatal_error+0x42>
 * @return true if execution state was in handler mode, before
 *              the current exception occurred, otherwise false.
 */
static ALWAYS_INLINE bool arch_is_in_nested_exception(const z_arch_esf_t *esf)
{
	return (esf->basic.xpsr & IPSR_ISR_Msk) ? (true) : (false);
    4372:	69eb      	ldr	r3, [r5, #28]
    4374:	f3c3 0308 	ubfx	r3, r3, #0, #9
    4378:	b11b      	cbz	r3, 4382 <z_fatal_error+0x42>
		LOG_ERR("Fault during interrupt handling\n");
    437a:	480d      	ldr	r0, [pc, #52]	; (43b0 <z_fatal_error+0x70>)
    437c:	2145      	movs	r1, #69	; 0x45
    437e:	f001 fbcb 	bl	5b18 <z_log_minimal_printk>
	}
#endif

	LOG_ERR("Current thread: %p (%s)", thread,
    4382:	4b0c      	ldr	r3, [pc, #48]	; (43b4 <z_fatal_error+0x74>)
    4384:	480c      	ldr	r0, [pc, #48]	; (43b8 <z_fatal_error+0x78>)
    4386:	2200      	movs	r2, #0
    4388:	2145      	movs	r1, #69	; 0x45
    438a:	f001 fbc5 	bl	5b18 <z_log_minimal_printk>
		log_strdup(thread_name_get(thread)));

	coredump(reason, esf, thread);

	k_sys_fatal_error_handler(reason, esf);
    438e:	4629      	mov	r1, r5
    4390:	4620      	mov	r0, r4
    4392:	f7ff f85f 	bl	3454 <k_sys_fatal_error_handler>
	__asm__ volatile(
    4396:	f386 8811 	msr	BASEPRI, r6
    439a:	f3bf 8f6f 	isb	sy
	arch_irq_unlock(key);

	if (IS_ENABLED(CONFIG_MULTITHREADING)) {
		k_thread_abort(thread);
	}
}
    439e:	b002      	add	sp, #8
    43a0:	bd70      	pop	{r4, r5, r6, pc}
    43a2:	bf00      	nop
    43a4:	000069bc 	.word	0x000069bc
    43a8:	00007534 	.word	0x00007534
    43ac:	00007542 	.word	0x00007542
    43b0:	0000756f 	.word	0x0000756f
    43b4:	00007595 	.word	0x00007595
    43b8:	0000759d 	.word	0x0000759d

000043bc <bg_thread_main>:
 * This routine completes kernel initialization by invoking the remaining
 * init functions, then invokes application's main() routine.
 */
__boot_func
static void bg_thread_main(void *unused1, void *unused2, void *unused3)
{
    43bc:	b508      	push	{r3, lr}
	 * may perform memory management tasks (except for z_phys_map() which
	 * is allowed at any time)
	 */
	z_mem_manage_init();
#endif /* CONFIG_MMU */
	z_sys_post_kernel = true;
    43be:	4b09      	ldr	r3, [pc, #36]	; (43e4 <bg_thread_main+0x28>)
    43c0:	2201      	movs	r2, #1

	z_sys_init_run_level(_SYS_INIT_LEVEL_POST_KERNEL);
    43c2:	2002      	movs	r0, #2
	z_sys_post_kernel = true;
    43c4:	701a      	strb	r2, [r3, #0]
	z_sys_init_run_level(_SYS_INIT_LEVEL_POST_KERNEL);
    43c6:	f7ff ff71 	bl	42ac <z_sys_init_run_level>
#if CONFIG_STACK_POINTER_RANDOM
	z_stack_adjust_initialized = 1;
#endif
	boot_banner();
    43ca:	f000 f909 	bl	45e0 <boot_banner>
	void z_cpp_init_static(void);
	z_cpp_init_static();
#endif

	/* Final init level before app starts */
	z_sys_init_run_level(_SYS_INIT_LEVEL_APPLICATION);
    43ce:	2003      	movs	r0, #3
    43d0:	f7ff ff6c 	bl	42ac <z_sys_init_run_level>
	z_mem_manage_boot_finish();
#endif /* CONFIG_MMU */

	extern void main(void);

	main();
    43d4:	f7fb fff0 	bl	3b8 <main>

	/* Mark nonessential since main() has no more work to do */
	z_main_thread.base.user_options &= ~K_ESSENTIAL;
    43d8:	4a03      	ldr	r2, [pc, #12]	; (43e8 <bg_thread_main+0x2c>)
    43da:	7b13      	ldrb	r3, [r2, #12]
    43dc:	f023 0301 	bic.w	r3, r3, #1
    43e0:	7313      	strb	r3, [r2, #12]

#ifdef CONFIG_COVERAGE_DUMP
	/* Dump coverage data once the main() has exited. */
	gcov_coverage_dump();
#endif
} /* LCOV_EXCL_LINE ... because we just dumped final coverage data */
    43e2:	bd08      	pop	{r3, pc}
    43e4:	2000140e 	.word	0x2000140e
    43e8:	200000c8 	.word	0x200000c8

000043ec <z_bss_zero>:
{
    43ec:	b508      	push	{r3, lr}
	z_early_memset(__bss_start, 0, __bss_end - __bss_start);
    43ee:	4803      	ldr	r0, [pc, #12]	; (43fc <z_bss_zero+0x10>)
    43f0:	4a03      	ldr	r2, [pc, #12]	; (4400 <z_bss_zero+0x14>)
    43f2:	2100      	movs	r1, #0
    43f4:	1a12      	subs	r2, r2, r0
    43f6:	f002 f807 	bl	6408 <z_early_memset>
}
    43fa:	bd08      	pop	{r3, pc}
    43fc:	200000a8 	.word	0x200000a8
    4400:	20001410 	.word	0x20001410

00004404 <z_cstart>:
 *
 * @return Does not return
 */
__boot_func
FUNC_NORETURN void z_cstart(void)
{
    4404:	b508      	push	{r3, lr}
 * pointer) register, and switched to automatically when taking an exception.
 *
 */
static ALWAYS_INLINE void z_arm_interrupt_stack_setup(void)
{
	uint32_t msp =
    4406:	4b19      	ldr	r3, [pc, #100]	; (446c <z_cstart+0x68>)
  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
    4408:	f383 8808 	msr	MSP, r3
	 * for Cortex-M3 and Cortex-M4 (ARMv7-M) MCUs. For the rest
	 * of ARM Cortex-M processors this setting is enforced by
	 * default and it is not configurable.
	 */
#if defined(CONFIG_CPU_CORTEX_M3) || defined(CONFIG_CPU_CORTEX_M4)
	SCB->CCR |= SCB_CCR_STKALIGN_Msk;
    440c:	4c18      	ldr	r4, [pc, #96]	; (4470 <z_cstart+0x6c>)
    440e:	6963      	ldr	r3, [r4, #20]
    4410:	f443 7300 	orr.w	r3, r3, #512	; 0x200
    4414:	6163      	str	r3, [r4, #20]
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    4416:	2500      	movs	r5, #0
    4418:	23e0      	movs	r3, #224	; 0xe0
    441a:	f884 3022 	strb.w	r3, [r4, #34]	; 0x22
    441e:	77e5      	strb	r5, [r4, #31]
    4420:	7625      	strb	r5, [r4, #24]
    4422:	7665      	strb	r5, [r4, #25]
    4424:	76a5      	strb	r5, [r4, #26]
    4426:	f884 5020 	strb.w	r5, [r4, #32]
#if defined(CONFIG_ARM_SECURE_FIRMWARE)
	NVIC_SetPriority(SecureFault_IRQn, _EXC_FAULT_PRIO);
#endif /* CONFIG_ARM_SECURE_FIRMWARE */

	/* Enable Usage, Mem, & Bus Faults */
	SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk |
    442a:	6a63      	ldr	r3, [r4, #36]	; 0x24
    442c:	f443 23e0 	orr.w	r3, r3, #458752	; 0x70000
    4430:	6263      	str	r3, [r4, #36]	; 0x24
    4432:	f884 5023 	strb.w	r5, [r4, #35]	; 0x23

static ALWAYS_INLINE void arch_kernel_init(void)
{
	z_arm_interrupt_stack_setup();
	z_arm_exc_setup();
	z_arm_fault_init();
    4436:	f7fd ff47 	bl	22c8 <z_arm_fault_init>
	z_arm_cpu_idle_init();
    443a:	f7fd fc7b 	bl	1d34 <z_arm_cpu_idle_init>
static ALWAYS_INLINE void z_arm_clear_faults(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* Reset all faults */
	SCB->CFSR = SCB_CFSR_USGFAULTSR_Msk |
    443e:	f04f 33ff 	mov.w	r3, #4294967295
    4442:	62a3      	str	r3, [r4, #40]	; 0x28
		    SCB_CFSR_MEMFAULTSR_Msk |
		    SCB_CFSR_BUSFAULTSR_Msk;

	/* Clear all Hard Faults - HFSR is write-one-to-clear */
	SCB->HFSR = 0xffffffff;
    4444:	62e3      	str	r3, [r4, #44]	; 0x2c
	z_arm_clear_faults();
#if defined(CONFIG_ARM_MPU)
	z_arm_mpu_init();
    4446:	f7fe f847 	bl	24d8 <z_arm_mpu_init>
	 * to set up access permissions for fixed memory sections, such
	 * as Application Memory or No-Cacheable SRAM area.
	 *
	 * This function is invoked once, upon system initialization.
	 */
	z_arm_configure_static_mpu_regions();
    444a:	f7fd ffc9 	bl	23e0 <z_arm_configure_static_mpu_regions>
	struct k_thread dummy_thread;

	z_dummy_thread_init(&dummy_thread);
#endif
	/* do any necessary initialization of static devices */
	z_device_state_init();
    444e:	f001 ffd0 	bl	63f2 <z_device_state_init>

	/* perform basic hardware initialization */
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_1);
    4452:	4628      	mov	r0, r5
    4454:	f7ff ff2a 	bl	42ac <z_sys_init_run_level>
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_2);
    4458:	2001      	movs	r0, #1
    445a:	f7ff ff27 	bl	42ac <z_sys_init_run_level>
#else
#ifdef ARCH_SWITCH_TO_MAIN_NO_MULTITHREADING
	/* Custom ARCH-specific routine to switch to main()
	 * in the case of no multi-threading.
	 */
	ARCH_SWITCH_TO_MAIN_NO_MULTITHREADING(bg_thread_main,
    445e:	4805      	ldr	r0, [pc, #20]	; (4474 <z_cstart+0x70>)
    4460:	462b      	mov	r3, r5
    4462:	462a      	mov	r2, r5
    4464:	4629      	mov	r1, r5
    4466:	f7fd fd1f 	bl	1ea8 <z_arm_switch_to_main_no_multithreading>
    446a:	bf00      	nop
    446c:	20004460 	.word	0x20004460
    4470:	e000ed00 	.word	0xe000ed00
    4474:	000043bd 	.word	0x000043bd

00004478 <z_data_copy>:
 * @brief Copy the data section from ROM to RAM
 *
 * This routine copies the data section from ROM to RAM.
 */
void z_data_copy(void)
{
    4478:	b508      	push	{r3, lr}
	z_early_memcpy(&__data_region_start, &__data_region_load_start,
		       __data_region_end - __data_region_start);
    447a:	4806      	ldr	r0, [pc, #24]	; (4494 <z_data_copy+0x1c>)
	z_early_memcpy(&__data_region_start, &__data_region_load_start,
    447c:	4a06      	ldr	r2, [pc, #24]	; (4498 <z_data_copy+0x20>)
    447e:	4907      	ldr	r1, [pc, #28]	; (449c <z_data_copy+0x24>)
    4480:	1a12      	subs	r2, r2, r0
    4482:	f001 ffc3 	bl	640c <z_early_memcpy>
#else
	z_early_memcpy(&_app_smem_start, &_app_smem_rom_start,
		       _app_smem_end - _app_smem_start);
#endif /* CONFIG_STACK_CANARIES */
#endif /* CONFIG_USERSPACE */
}
    4486:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	z_early_memcpy(&__ramfunc_start, &__ramfunc_load_start,
    448a:	4a05      	ldr	r2, [pc, #20]	; (44a0 <z_data_copy+0x28>)
    448c:	4905      	ldr	r1, [pc, #20]	; (44a4 <z_data_copy+0x2c>)
    448e:	4806      	ldr	r0, [pc, #24]	; (44a8 <z_data_copy+0x30>)
    4490:	f001 bfbc 	b.w	640c <z_early_memcpy>
    4494:	20000000 	.word	0x20000000
    4498:	200000a8 	.word	0x200000a8
    449c:	0000763c 	.word	0x0000763c
    44a0:	00000000 	.word	0x00000000
    44a4:	0000763c 	.word	0x0000763c
    44a8:	20000000 	.word	0x20000000

000044ac <elapsed>:
	sys_dlist_remove(&t->node);
}

static int32_t elapsed(void)
{
	return announce_remaining == 0 ? sys_clock_elapsed() : 0U;
    44ac:	4b03      	ldr	r3, [pc, #12]	; (44bc <elapsed+0x10>)
    44ae:	681b      	ldr	r3, [r3, #0]
    44b0:	b90b      	cbnz	r3, 44b6 <elapsed+0xa>
    44b2:	f7fe bfc5 	b.w	3440 <sys_clock_elapsed>
}
    44b6:	2000      	movs	r0, #0
    44b8:	4770      	bx	lr
    44ba:	bf00      	nop
    44bc:	20000ef8 	.word	0x20000ef8

000044c0 <next_timeout>:
 * @return true if empty, false otherwise
 */

static inline bool sys_dlist_is_empty(sys_dlist_t *list)
{
	return list->head == list;
    44c0:	4b0d      	ldr	r3, [pc, #52]	; (44f8 <next_timeout+0x38>)

static int32_t next_timeout(void)
{
    44c2:	b510      	push	{r4, lr}
    44c4:	681c      	ldr	r4, [r3, #0]
 * @return a pointer to the head element, NULL if list is empty
 */

static inline sys_dnode_t *sys_dlist_peek_head(sys_dlist_t *list)
{
	return sys_dlist_is_empty(list) ? NULL : list->head;
    44c6:	429c      	cmp	r4, r3
    44c8:	bf08      	it	eq
    44ca:	2400      	moveq	r4, #0
	struct _timeout *to = first();
	int32_t ticks_elapsed = elapsed();
    44cc:	f7ff ffee 	bl	44ac <elapsed>
	int32_t ret;

	if ((to == NULL) ||
    44d0:	b174      	cbz	r4, 44f0 <next_timeout+0x30>
	    ((int64_t)(to->dticks - ticks_elapsed) > (int64_t)INT_MAX)) {
    44d2:	e9d4 3204 	ldrd	r3, r2, [r4, #16]
    44d6:	1a1b      	subs	r3, r3, r0
    44d8:	eb62 70e0 	sbc.w	r0, r2, r0, asr #31
	if ((to == NULL) ||
    44dc:	f1b3 4f00 	cmp.w	r3, #2147483648	; 0x80000000
    44e0:	f170 0200 	sbcs.w	r2, r0, #0
    44e4:	da04      	bge.n	44f0 <next_timeout+0x30>
		ret = MAX_WAIT;
	} else {
		ret = MAX(0, to->dticks - ticks_elapsed);
    44e6:	2800      	cmp	r0, #0
    44e8:	bfac      	ite	ge
    44ea:	4618      	movge	r0, r3
    44ec:	2000      	movlt	r0, #0
	if (_current_cpu->slice_ticks && _current_cpu->slice_ticks < ret) {
		ret = _current_cpu->slice_ticks;
	}
#endif
	return ret;
}
    44ee:	bd10      	pop	{r4, pc}
		ret = MAX_WAIT;
    44f0:	f06f 4000 	mvn.w	r0, #2147483648	; 0x80000000
	return ret;
    44f4:	e7fb      	b.n	44ee <next_timeout+0x2e>
    44f6:	bf00      	nop
    44f8:	20000090 	.word	0x20000090

000044fc <remove_timeout>:
{
    44fc:	b530      	push	{r4, r5, lr}
 */

static inline sys_dnode_t *sys_dlist_peek_next_no_check(sys_dlist_t *list,
							sys_dnode_t *node)
{
	return (node == list->tail) ? NULL : node->next;
    44fe:	6803      	ldr	r3, [r0, #0]
 */

static inline sys_dnode_t *sys_dlist_peek_next(sys_dlist_t *list,
					       sys_dnode_t *node)
{
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    4500:	b168      	cbz	r0, 451e <remove_timeout+0x22>
	return (node == list->tail) ? NULL : node->next;
    4502:	4a0a      	ldr	r2, [pc, #40]	; (452c <remove_timeout+0x30>)
    4504:	6852      	ldr	r2, [r2, #4]
    4506:	4290      	cmp	r0, r2
    4508:	d009      	beq.n	451e <remove_timeout+0x22>
	if (next(t) != NULL) {
    450a:	b143      	cbz	r3, 451e <remove_timeout+0x22>
		next(t)->dticks += t->dticks;
    450c:	e9d3 2104 	ldrd	r2, r1, [r3, #16]
    4510:	e9d0 4504 	ldrd	r4, r5, [r0, #16]
    4514:	1912      	adds	r2, r2, r4
    4516:	eb41 0105 	adc.w	r1, r1, r5
    451a:	e9c3 2104 	strd	r2, r1, [r3, #16]
 * @param node the node to remove
 */

static inline void sys_dlist_remove(sys_dnode_t *node)
{
	sys_dnode_t *const prev = node->prev;
    451e:	6842      	ldr	r2, [r0, #4]
	sys_dnode_t *const next = node->next;

	prev->next = next;
    4520:	6013      	str	r3, [r2, #0]
	next->prev = prev;
    4522:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    4524:	2300      	movs	r3, #0
	node->prev = NULL;
    4526:	e9c0 3300 	strd	r3, r3, [r0]
}
    452a:	bd30      	pop	{r4, r5, pc}
    452c:	20000090 	.word	0x20000090

00004530 <sys_clock_announce>:
		}
	}
}

void sys_clock_announce(int32_t ticks)
{
    4530:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
	__asm__ volatile(
    4534:	f04f 0320 	mov.w	r3, #32
    4538:	f3ef 8411 	mrs	r4, BASEPRI
    453c:	f383 8812 	msr	BASEPRI_MAX, r3
    4540:	f3bf 8f6f 	isb	sy
		announce_remaining += ticks;
		k_spin_unlock(&timeout_lock, key);
		return;
	}

	announce_remaining = ticks;
    4544:	4e23      	ldr	r6, [pc, #140]	; (45d4 <sys_clock_announce+0xa4>)
	return list->head == list;
    4546:	f8df 8090 	ldr.w	r8, [pc, #144]	; 45d8 <sys_clock_announce+0xa8>

	while (first() != NULL && first()->dticks <= announce_remaining) {
		struct _timeout *t = first();
		int dt = t->dticks;

		curr_tick += dt;
    454a:	4d24      	ldr	r5, [pc, #144]	; (45dc <sys_clock_announce+0xac>)
	announce_remaining = ticks;
    454c:	6030      	str	r0, [r6, #0]
    454e:	f8d8 0000 	ldr.w	r0, [r8]
	while (first() != NULL && first()->dticks <= announce_remaining) {
    4552:	6832      	ldr	r2, [r6, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    4554:	4540      	cmp	r0, r8
		curr_tick += dt;
    4556:	e9d5 1e00 	ldrd	r1, lr, [r5]
    455a:	ea4f 77e2 	mov.w	r7, r2, asr #31
    455e:	d00b      	beq.n	4578 <sys_clock_announce+0x48>
	while (first() != NULL && first()->dticks <= announce_remaining) {
    4560:	b150      	cbz	r0, 4578 <sys_clock_announce+0x48>
    4562:	e9d0 3c04 	ldrd	r3, ip, [r0, #16]
    4566:	429a      	cmp	r2, r3
    4568:	eb77 090c 	sbcs.w	r9, r7, ip
    456c:	da16      	bge.n	459c <sys_clock_announce+0x6c>
		t->fn(t);
		key = k_spin_lock(&timeout_lock);
	}

	if (first() != NULL) {
		first()->dticks -= announce_remaining;
    456e:	1a9b      	subs	r3, r3, r2
    4570:	eb6c 0c07 	sbc.w	ip, ip, r7
    4574:	e9c0 3c04 	strd	r3, ip, [r0, #16]
	}

	curr_tick += announce_remaining;
    4578:	1852      	adds	r2, r2, r1
    457a:	eb4e 0707 	adc.w	r7, lr, r7
    457e:	e9c5 2700 	strd	r2, r7, [r5]
	announce_remaining = 0;
    4582:	2500      	movs	r5, #0
    4584:	6035      	str	r5, [r6, #0]

	sys_clock_set_timeout(next_timeout(), false);
    4586:	f7ff ff9b 	bl	44c0 <next_timeout>
    458a:	4629      	mov	r1, r5
    458c:	f7fe ff26 	bl	33dc <sys_clock_set_timeout>
	__asm__ volatile(
    4590:	f384 8811 	msr	BASEPRI, r4
    4594:	f3bf 8f6f 	isb	sy

	k_spin_unlock(&timeout_lock, key);
}
    4598:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
		curr_tick += dt;
    459c:	1859      	adds	r1, r3, r1
    459e:	eb4e 77e3 	adc.w	r7, lr, r3, asr #31
		announce_remaining -= dt;
    45a2:	1ad3      	subs	r3, r2, r3
    45a4:	6033      	str	r3, [r6, #0]
		t->dticks = 0;
    45a6:	2200      	movs	r2, #0
    45a8:	2300      	movs	r3, #0
    45aa:	e9c0 2304 	strd	r2, r3, [r0, #16]
		curr_tick += dt;
    45ae:	e9c5 1700 	strd	r1, r7, [r5]
		remove_timeout(t);
    45b2:	f7ff ffa3 	bl	44fc <remove_timeout>
    45b6:	f384 8811 	msr	BASEPRI, r4
    45ba:	f3bf 8f6f 	isb	sy
		t->fn(t);
    45be:	6883      	ldr	r3, [r0, #8]
    45c0:	4798      	blx	r3
	__asm__ volatile(
    45c2:	f04f 0320 	mov.w	r3, #32
    45c6:	f3ef 8411 	mrs	r4, BASEPRI
    45ca:	f383 8812 	msr	BASEPRI_MAX, r3
    45ce:	f3bf 8f6f 	isb	sy
#endif

#ifdef CONFIG_SPIN_VALIDATE
	z_spin_lock_set_owner(l);
#endif
	return k;
    45d2:	e7bc      	b.n	454e <sys_clock_announce+0x1e>
    45d4:	20000ef8 	.word	0x20000ef8
    45d8:	20000090 	.word	0x20000090
    45dc:	20000148 	.word	0x20000148

000045e0 <boot_banner>:
		k_busy_wait(CONFIG_BOOT_DELAY * USEC_PER_MSEC);
	}

#if defined(CONFIG_BOOT_BANNER)
#ifdef BUILD_VERSION
	printk("*** Booting Zephyr OS build %s %s ***\n",
    45e0:	4a02      	ldr	r2, [pc, #8]	; (45ec <boot_banner+0xc>)
    45e2:	4903      	ldr	r1, [pc, #12]	; (45f0 <boot_banner+0x10>)
    45e4:	4803      	ldr	r0, [pc, #12]	; (45f4 <boot_banner+0x14>)
    45e6:	f001 b9de 	b.w	59a6 <printk>
    45ea:	bf00      	nop
    45ec:	00007594 	.word	0x00007594
    45f0:	00007607 	.word	0x00007607
    45f4:	00007614 	.word	0x00007614

000045f8 <flash_area_id_from_multi_image_slot>:
 * MCUBoot uses continuous numbering for the primary slot, the secondary slot,
 * and the scratch while zephyr might number it differently.
 */
int flash_area_id_from_multi_image_slot(int image_index, int slot)
{
    switch (slot) {
    45f8:	b129      	cbz	r1, 4606 <flash_area_id_from_multi_image_slot+0xe>
    45fa:	2901      	cmp	r1, #1
    45fc:	bf14      	ite	ne
    45fe:	f06f 0015 	mvnne.w	r0, #21
    4602:	2005      	moveq	r0, #5
    4604:	4770      	bx	lr
    case 0: return FLASH_AREA_IMAGE_PRIMARY(image_index);
    4606:	2002      	movs	r0, #2
    case 2: return FLASH_AREA_IMAGE_SCRATCH;
#endif
    }

    return -EINVAL; /* flash_area_open will fail on that */
}
    4608:	4770      	bx	lr

0000460a <flash_area_get_device_id>:

uint8_t flash_area_get_device_id(const struct flash_area *fa)
{
	(void)fa;
	return FLASH_DEVICE_ID;
}
    460a:	2000      	movs	r0, #0
    460c:	4770      	bx	lr

0000460e <os_heap_init>:
    mbedtls_memory_buffer_alloc_init(mempool, sizeof(mempool));
}
#else
void os_heap_init(void)
{
}
    460e:	4770      	bx	lr

00004610 <bootutil_tlv_iter_begin>:
 *          -1 on errors
 */
int
bootutil_tlv_iter_begin(struct image_tlv_iter *it, const struct image_header *hdr,
                        const struct flash_area *fap, uint16_t type, bool prot)
{
    4610:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    4614:	460e      	mov	r6, r1
    4616:	4617      	mov	r7, r2
    4618:	4699      	mov	r9, r3
    uint32_t off_;
    struct image_tlv_info info;

    if (it == NULL || hdr == NULL || fap == NULL) {
    461a:	4604      	mov	r4, r0
    461c:	b928      	cbnz	r0, 462a <bootutil_tlv_iter_begin+0x1a>
        return -1;
    461e:	f04f 38ff 	mov.w	r8, #4294967295
    it->prot_end = off_ + it->hdr->ih_protect_tlv_size;
    it->tlv_end = off_ + it->hdr->ih_protect_tlv_size + info.it_tlv_tot;
    // position on first TLV
    it->tlv_off = off_ + sizeof(info);
    return 0;
}
    4622:	4640      	mov	r0, r8
    4624:	b003      	add	sp, #12
    4626:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
    if (it == NULL || hdr == NULL || fap == NULL) {
    462a:	2900      	cmp	r1, #0
    462c:	d0f7      	beq.n	461e <bootutil_tlv_iter_begin+0xe>
    462e:	2a00      	cmp	r2, #0
    4630:	d0f5      	beq.n	461e <bootutil_tlv_iter_begin+0xe>
    off_ = BOOT_TLV_OFF(hdr);
    4632:	68cb      	ldr	r3, [r1, #12]
    4634:	890d      	ldrh	r5, [r1, #8]
    4636:	441d      	add	r5, r3
    if (LOAD_IMAGE_DATA(hdr, fap, off_, &info, sizeof(info))) {
    4638:	2304      	movs	r3, #4
    463a:	eb0d 0203 	add.w	r2, sp, r3
    463e:	4629      	mov	r1, r5
    4640:	4638      	mov	r0, r7
    4642:	f001 fa77 	bl	5b34 <flash_area_read>
    4646:	4680      	mov	r8, r0
    4648:	2800      	cmp	r0, #0
    464a:	d1e8      	bne.n	461e <bootutil_tlv_iter_begin+0xe>
    if (info.it_magic == IMAGE_TLV_PROT_INFO_MAGIC) {
    464c:	f8bd 1004 	ldrh.w	r1, [sp, #4]
        if (hdr->ih_protect_tlv_size != info.it_tlv_tot) {
    4650:	8973      	ldrh	r3, [r6, #10]
    if (info.it_magic == IMAGE_TLV_PROT_INFO_MAGIC) {
    4652:	f646 1208 	movw	r2, #26888	; 0x6908
    4656:	4291      	cmp	r1, r2
    4658:	d123      	bne.n	46a2 <bootutil_tlv_iter_begin+0x92>
        if (hdr->ih_protect_tlv_size != info.it_tlv_tot) {
    465a:	f8bd 1006 	ldrh.w	r1, [sp, #6]
    465e:	4299      	cmp	r1, r3
    4660:	d1dd      	bne.n	461e <bootutil_tlv_iter_begin+0xe>
        if (LOAD_IMAGE_DATA(hdr, fap, off_ + info.it_tlv_tot,
    4662:	2304      	movs	r3, #4
    4664:	eb0d 0203 	add.w	r2, sp, r3
    4668:	4429      	add	r1, r5
    466a:	4638      	mov	r0, r7
    466c:	f001 fa62 	bl	5b34 <flash_area_read>
    4670:	2800      	cmp	r0, #0
    4672:	d1d4      	bne.n	461e <bootutil_tlv_iter_begin+0xe>
    if (info.it_magic != IMAGE_TLV_INFO_MAGIC) {
    4674:	f8bd 2004 	ldrh.w	r2, [sp, #4]
    4678:	f646 1307 	movw	r3, #26887	; 0x6907
    467c:	429a      	cmp	r2, r3
    467e:	d1ce      	bne.n	461e <bootutil_tlv_iter_begin+0xe>
    it->prot = prot;
    4680:	f89d 3028 	ldrb.w	r3, [sp, #40]	; 0x28
    4684:	72a3      	strb	r3, [r4, #10]
    it->prot_end = off_ + it->hdr->ih_protect_tlv_size;
    4686:	8973      	ldrh	r3, [r6, #10]
    it->tlv_end = off_ + it->hdr->ih_protect_tlv_size + info.it_tlv_tot;
    4688:	f8bd 2006 	ldrh.w	r2, [sp, #6]
    it->type = type;
    468c:	f8a4 9008 	strh.w	r9, [r4, #8]
    it->prot_end = off_ + it->hdr->ih_protect_tlv_size;
    4690:	442b      	add	r3, r5
    4692:	60e3      	str	r3, [r4, #12]
    it->tlv_off = off_ + sizeof(info);
    4694:	3504      	adds	r5, #4
    it->tlv_end = off_ + it->hdr->ih_protect_tlv_size + info.it_tlv_tot;
    4696:	4413      	add	r3, r2
    it->fap = fap;
    4698:	e9c4 6700 	strd	r6, r7, [r4]
    it->tlv_end = off_ + it->hdr->ih_protect_tlv_size + info.it_tlv_tot;
    469c:	6163      	str	r3, [r4, #20]
    it->tlv_off = off_ + sizeof(info);
    469e:	6125      	str	r5, [r4, #16]
    return 0;
    46a0:	e7bf      	b.n	4622 <bootutil_tlv_iter_begin+0x12>
    } else if (hdr->ih_protect_tlv_size != 0) {
    46a2:	2b00      	cmp	r3, #0
    46a4:	d0e6      	beq.n	4674 <bootutil_tlv_iter_begin+0x64>
    46a6:	e7ba      	b.n	461e <bootutil_tlv_iter_begin+0xe>

000046a8 <bootutil_tlv_iter_next>:
 *          -1 on errors
 */
int
bootutil_tlv_iter_next(struct image_tlv_iter *it, uint32_t *off, uint16_t *len,
                       uint16_t *type)
{
    46a8:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    46ac:	460f      	mov	r7, r1
    46ae:	4690      	mov	r8, r2
    46b0:	461e      	mov	r6, r3
    struct image_tlv tlv;
    int rc;

    if (it == NULL || it->hdr == NULL || it->fap == NULL) {
    46b2:	4604      	mov	r4, r0
    46b4:	b920      	cbnz	r0, 46c0 <bootutil_tlv_iter_next+0x18>
        return -1;
    46b6:	f04f 30ff 	mov.w	r0, #4294967295

        it->tlv_off += sizeof(tlv) + tlv.it_len;
    }

    return 1;
}
    46ba:	b003      	add	sp, #12
    46bc:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
    if (it == NULL || it->hdr == NULL || it->fap == NULL) {
    46c0:	6803      	ldr	r3, [r0, #0]
    46c2:	2b00      	cmp	r3, #0
    46c4:	d0f7      	beq.n	46b6 <bootutil_tlv_iter_next+0xe>
    46c6:	6843      	ldr	r3, [r0, #4]
    46c8:	2b00      	cmp	r3, #0
    46ca:	d0f4      	beq.n	46b6 <bootutil_tlv_iter_next+0xe>
        if (it->type == IMAGE_TLV_ANY || tlv.it_type == it->type) {
    46cc:	f64f 79ff 	movw	r9, #65535	; 0xffff
    while (it->tlv_off < it->tlv_end) {
    46d0:	e9d4 2304 	ldrd	r2, r3, [r4, #16]
    46d4:	429a      	cmp	r2, r3
    46d6:	d216      	bcs.n	4706 <bootutil_tlv_iter_next+0x5e>
        if (it->hdr->ih_protect_tlv_size > 0 && it->tlv_off == it->prot_end) {
    46d8:	6823      	ldr	r3, [r4, #0]
    46da:	895b      	ldrh	r3, [r3, #10]
    46dc:	b123      	cbz	r3, 46e8 <bootutil_tlv_iter_next+0x40>
    46de:	68e3      	ldr	r3, [r4, #12]
    46e0:	4293      	cmp	r3, r2
            it->tlv_off += sizeof(struct image_tlv_info);
    46e2:	bf04      	itt	eq
    46e4:	3304      	addeq	r3, #4
    46e6:	6123      	streq	r3, [r4, #16]
        rc = LOAD_IMAGE_DATA(it->hdr, it->fap, it->tlv_off, &tlv, sizeof tlv);
    46e8:	2304      	movs	r3, #4
    46ea:	6921      	ldr	r1, [r4, #16]
    46ec:	6860      	ldr	r0, [r4, #4]
    46ee:	eb0d 0203 	add.w	r2, sp, r3
    46f2:	f001 fa1f 	bl	5b34 <flash_area_read>
        if (rc) {
    46f6:	2800      	cmp	r0, #0
    46f8:	d1dd      	bne.n	46b6 <bootutil_tlv_iter_next+0xe>
        if (it->prot && it->tlv_off >= it->prot_end) {
    46fa:	7aa3      	ldrb	r3, [r4, #10]
    46fc:	6925      	ldr	r5, [r4, #16]
    46fe:	b123      	cbz	r3, 470a <bootutil_tlv_iter_next+0x62>
    4700:	68e3      	ldr	r3, [r4, #12]
    4702:	42ab      	cmp	r3, r5
    4704:	d801      	bhi.n	470a <bootutil_tlv_iter_next+0x62>
            return 1;
    4706:	2001      	movs	r0, #1
    4708:	e7d7      	b.n	46ba <bootutil_tlv_iter_next+0x12>
        if (it->type == IMAGE_TLV_ANY || tlv.it_type == it->type) {
    470a:	8921      	ldrh	r1, [r4, #8]
        it->tlv_off += sizeof(tlv) + tlv.it_len;
    470c:	f8bd 2006 	ldrh.w	r2, [sp, #6]
        if (it->type == IMAGE_TLV_ANY || tlv.it_type == it->type) {
    4710:	4549      	cmp	r1, r9
    4712:	f102 0304 	add.w	r3, r2, #4
    4716:	d003      	beq.n	4720 <bootutil_tlv_iter_next+0x78>
    4718:	f8bd c004 	ldrh.w	ip, [sp, #4]
    471c:	458c      	cmp	ip, r1
    471e:	d10b      	bne.n	4738 <bootutil_tlv_iter_next+0x90>
            if (type != NULL) {
    4720:	b116      	cbz	r6, 4728 <bootutil_tlv_iter_next+0x80>
                *type = tlv.it_type;
    4722:	f8bd 1004 	ldrh.w	r1, [sp, #4]
    4726:	8031      	strh	r1, [r6, #0]
            *off = it->tlv_off + sizeof(tlv);
    4728:	3504      	adds	r5, #4
    472a:	603d      	str	r5, [r7, #0]
            *len = tlv.it_len;
    472c:	f8a8 2000 	strh.w	r2, [r8]
            it->tlv_off += sizeof(tlv) + tlv.it_len;
    4730:	6922      	ldr	r2, [r4, #16]
    4732:	4413      	add	r3, r2
    4734:	6123      	str	r3, [r4, #16]
            return 0;
    4736:	e7c0      	b.n	46ba <bootutil_tlv_iter_next+0x12>
        it->tlv_off += sizeof(tlv) + tlv.it_len;
    4738:	442b      	add	r3, r5
    473a:	6123      	str	r3, [r4, #16]
    473c:	e7c8      	b.n	46d0 <bootutil_tlv_iter_next+0x28>

0000473e <bootutil_read_bigint>:
{
    473e:	b573      	push	{r0, r1, r4, r5, r6, lr}
    4740:	460c      	mov	r4, r1
    4742:	4606      	mov	r6, r0
    4744:	4611      	mov	r1, r2
    if (mbedtls_asn1_get_tag(cp, end, &len, MBEDTLS_ASN1_INTEGER)) {
    4746:	2302      	movs	r3, #2
    4748:	aa01      	add	r2, sp, #4
    474a:	4620      	mov	r0, r4
    474c:	f000 fa3d 	bl	4bca <mbedtls_asn1_get_tag>
    4750:	4605      	mov	r5, r0
    4752:	b9e8      	cbnz	r0, 4790 <bootutil_read_bigint+0x52>
    if (len >= NUM_ECC_BYTES) {
    4754:	9a01      	ldr	r2, [sp, #4]
    4756:	2a1f      	cmp	r2, #31
    4758:	d90e      	bls.n	4778 <bootutil_read_bigint+0x3a>
        memcpy(i, *cp + len - NUM_ECC_BYTES, NUM_ECC_BYTES);
    475a:	6823      	ldr	r3, [r4, #0]
    475c:	f1a2 0120 	sub.w	r1, r2, #32
    4760:	4419      	add	r1, r3
    4762:	2220      	movs	r2, #32
    4764:	4630      	mov	r0, r6
        memcpy(i + NUM_ECC_BYTES - len, *cp, len);
    4766:	f001 faa1 	bl	5cac <memcpy>
    *cp += len;
    476a:	6823      	ldr	r3, [r4, #0]
    476c:	9a01      	ldr	r2, [sp, #4]
    476e:	4413      	add	r3, r2
    4770:	6023      	str	r3, [r4, #0]
}
    4772:	4628      	mov	r0, r5
    4774:	b002      	add	sp, #8
    4776:	bd70      	pop	{r4, r5, r6, pc}
        memset(i, 0, NUM_ECC_BYTES - len);
    4778:	4601      	mov	r1, r0
    477a:	f1c2 0220 	rsb	r2, r2, #32
    477e:	4630      	mov	r0, r6
    4780:	f001 fa9f 	bl	5cc2 <memset>
        memcpy(i + NUM_ECC_BYTES - len, *cp, len);
    4784:	9a01      	ldr	r2, [sp, #4]
    4786:	6821      	ldr	r1, [r4, #0]
    4788:	f1c2 0020 	rsb	r0, r2, #32
    478c:	4430      	add	r0, r6
    478e:	e7ea      	b.n	4766 <bootutil_read_bigint+0x28>
        return -3;
    4790:	f06f 0502 	mvn.w	r5, #2
    4794:	e7ed      	b.n	4772 <bootutil_read_bigint+0x34>

00004796 <boot_fih_memequal>:
    return memcmp(s1, s2, n);
    4796:	f001 ba78 	b.w	5c8a <memcmp>

0000479a <boot_trailer_sz>:
    return BOOT_STATUS_MAX_ENTRIES * boot_status_entry_sz(min_write_sz);
    479a:	f44f 73c0 	mov.w	r3, #384	; 0x180
    479e:	4358      	muls	r0, r3
}
    47a0:	3030      	adds	r0, #48	; 0x30
    47a2:	4770      	bx	lr

000047a4 <boot_status_entries>:
	return fa->fa_id;
    47a4:	780b      	ldrb	r3, [r1, #0]
    if (flash_area_get_id(fap) == FLASH_AREA_IMAGE_PRIMARY(image_index) ||
    47a6:	2b02      	cmp	r3, #2
    47a8:	d006      	beq.n	47b8 <boot_status_entries+0x14>
    return -1;
    47aa:	2b05      	cmp	r3, #5
    47ac:	bf0c      	ite	eq
    47ae:	f44f 70c0 	moveq.w	r0, #384	; 0x180
    47b2:	f04f 30ff 	movne.w	r0, #4294967295
    47b6:	4770      	bx	lr
        return BOOT_STATUS_STATE_COUNT * BOOT_STATUS_MAX_ENTRIES;
    47b8:	f44f 70c0 	mov.w	r0, #384	; 0x180
}
    47bc:	4770      	bx	lr

000047be <boot_status_off>:
{
    47be:	b510      	push	{r4, lr}
    47c0:	4604      	mov	r4, r0
    elem_sz = flash_area_align(fap);
    47c2:	f001 fa06 	bl	5bd2 <flash_area_align>
    return flash_area_get_size(fap) - off_from_end;
    47c6:	68a3      	ldr	r3, [r4, #8]
}
    47c8:	f44f 72c0 	mov.w	r2, #384	; 0x180
    return flash_area_get_size(fap) - off_from_end;
    47cc:	3b30      	subs	r3, #48	; 0x30
}
    47ce:	fb02 3010 	mls	r0, r2, r0, r3
    47d2:	bd10      	pop	{r4, pc}

000047d4 <boot_write_copy_done>:
    return ALIGN_DOWN(boot_magic_off(fap) - BOOT_MAX_ALIGN, BOOT_MAX_ALIGN);
    47d4:	6881      	ldr	r1, [r0, #8]
    47d6:	3918      	subs	r1, #24
    47d8:	f021 0107 	bic.w	r1, r1, #7

    off = boot_copy_done_off(fap);
    BOOT_LOG_DBG("writing copy_done; fa_id=%d off=0x%lx (0x%lx)",
                 flash_area_get_id(fap), (unsigned long)off,
                 (unsigned long)(flash_area_get_off(fap) + off));
    return boot_write_trailer_flag(fap, off, BOOT_FLAG_SET);
    47dc:	2201      	movs	r2, #1
    47de:	3908      	subs	r1, #8
    47e0:	f001 bd88 	b.w	62f4 <boot_write_trailer_flag>

000047e4 <boot_write_swap_size>:
}

int
boot_write_swap_size(const struct flash_area *fap, uint32_t swap_size)
{
    47e4:	b513      	push	{r0, r1, r4, lr}
    47e6:	4604      	mov	r4, r0
    47e8:	9101      	str	r1, [sp, #4]
    return boot_swap_info_off(fap) - BOOT_MAX_ALIGN;
    47ea:	f001 fd20 	bl	622e <boot_swap_info_off>

    off = boot_swap_size_off(fap);
    BOOT_LOG_DBG("writing swap_size; fa_id=%d off=0x%lx (0x%lx)",
                 flash_area_get_id(fap), (unsigned long)off,
                 (unsigned long)flash_area_get_off(fap) + off);
    return boot_write_trailer(fap, off, (const uint8_t *) &swap_size, 4);
    47ee:	2304      	movs	r3, #4
    47f0:	f1a0 0108 	sub.w	r1, r0, #8
    47f4:	eb0d 0203 	add.w	r2, sp, r3
    47f8:	4620      	mov	r0, r4
    47fa:	f001 fd4f 	bl	629c <boot_write_trailer>
}
    47fe:	b002      	add	sp, #8
    4800:	bd10      	pop	{r4, pc}

00004802 <boot_read_image_headers>:
{
    4802:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
            rc = boot_read_image_header(state, i, boot_img_hdr(state, i), bs);
    4804:	4613      	mov	r3, r2
{
    4806:	460f      	mov	r7, r1
    4808:	4616      	mov	r6, r2
            rc = boot_read_image_header(state, i, boot_img_hdr(state, i), bs);
    480a:	2100      	movs	r1, #0
    480c:	4602      	mov	r2, r0
{
    480e:	4605      	mov	r5, r0
            rc = boot_read_image_header(state, i, boot_img_hdr(state, i), bs);
    4810:	f7fc fa58 	bl	cc4 <boot_read_image_header>
        if (rc != 0) {
    4814:	4604      	mov	r4, r0
    4816:	b950      	cbnz	r0, 482e <boot_read_image_headers+0x2c>
            rc = boot_read_image_header(state, i, boot_img_hdr(state, i), bs);
    4818:	4633      	mov	r3, r6
    481a:	f105 022c 	add.w	r2, r5, #44	; 0x2c
    481e:	2101      	movs	r1, #1
    4820:	4628      	mov	r0, r5
    4822:	f7fc fa4f 	bl	cc4 <boot_read_image_header>
        if (rc != 0) {
    4826:	b110      	cbz	r0, 482e <boot_read_image_headers+0x2c>
            if (i > 0 && !require_all) {
    4828:	2f00      	cmp	r7, #0
    482a:	bf18      	it	ne
    482c:	4604      	movne	r4, r0
}
    482e:	4620      	mov	r0, r4
    4830:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}

00004832 <boot_read_image_size.isra.0>:
boot_read_image_size(struct boot_loader_state *state, int slot, uint32_t *size)
    4832:	b573      	push	{r0, r1, r4, r5, r6, lr}
    4834:	4605      	mov	r5, r0
    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
    4836:	2000      	movs	r0, #0
boot_read_image_size(struct boot_loader_state *state, int slot, uint32_t *size)
    4838:	460c      	mov	r4, r1
    483a:	4616      	mov	r6, r2
    area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
    483c:	f7ff fedc 	bl	45f8 <flash_area_id_from_multi_image_slot>
    rc = flash_area_open(area_id, &fap);
    4840:	4669      	mov	r1, sp
    4842:	b2c0      	uxtb	r0, r0
    4844:	f7fd fa24 	bl	1c90 <flash_area_open>
    if (rc != 0) {
    4848:	bb30      	cbnz	r0, 4898 <boot_read_image_size.isra.0+0x66>
    off = BOOT_TLV_OFF(boot_img_hdr(state, slot));
    484a:	212c      	movs	r1, #44	; 0x2c
    484c:	fb01 5404 	mla	r4, r1, r4, r5
    if (flash_area_read(fap, off, &info, sizeof(info))) {
    4850:	9800      	ldr	r0, [sp, #0]
    off = BOOT_TLV_OFF(boot_img_hdr(state, slot));
    4852:	8921      	ldrh	r1, [r4, #8]
    4854:	68e3      	ldr	r3, [r4, #12]
    4856:	18cd      	adds	r5, r1, r3
    if (flash_area_read(fap, off, &info, sizeof(info))) {
    4858:	2304      	movs	r3, #4
    485a:	eb0d 0203 	add.w	r2, sp, r3
    485e:	4629      	mov	r1, r5
    4860:	f001 f968 	bl	5b34 <flash_area_read>
    4864:	b9c0      	cbnz	r0, 4898 <boot_read_image_size.isra.0+0x66>
    if (info.it_magic == IMAGE_TLV_PROT_INFO_MAGIC) {
    4866:	f8bd 2004 	ldrh.w	r2, [sp, #4]
    protect_tlv_size = boot_img_hdr(state, slot)->ih_protect_tlv_size;
    486a:	8964      	ldrh	r4, [r4, #10]
    if (info.it_magic == IMAGE_TLV_PROT_INFO_MAGIC) {
    486c:	f646 1308 	movw	r3, #26888	; 0x6908
    4870:	429a      	cmp	r2, r3
    4872:	d116      	bne.n	48a2 <boot_read_image_size.isra.0+0x70>
        if (protect_tlv_size != info.it_tlv_tot) {
    4874:	f8bd 3006 	ldrh.w	r3, [sp, #6]
    4878:	429c      	cmp	r4, r3
    487a:	d10d      	bne.n	4898 <boot_read_image_size.isra.0+0x66>
        if (flash_area_read(fap, off + info.it_tlv_tot, &info, sizeof(info))) {
    487c:	2304      	movs	r3, #4
    487e:	9800      	ldr	r0, [sp, #0]
    4880:	eb0d 0203 	add.w	r2, sp, r3
    4884:	1961      	adds	r1, r4, r5
    4886:	f001 f955 	bl	5b34 <flash_area_read>
    488a:	b928      	cbnz	r0, 4898 <boot_read_image_size.isra.0+0x66>
    if (info.it_magic != IMAGE_TLV_INFO_MAGIC) {
    488c:	f8bd 2004 	ldrh.w	r2, [sp, #4]
    4890:	f646 1307 	movw	r3, #26887	; 0x6907
    4894:	429a      	cmp	r2, r3
    4896:	d007      	beq.n	48a8 <boot_read_image_size.isra.0+0x76>
    flash_area_close(fap);
    4898:	9800      	ldr	r0, [sp, #0]
    489a:	f001 f94a 	bl	5b32 <flash_area_close>
}
    489e:	b002      	add	sp, #8
    48a0:	bd70      	pop	{r4, r5, r6, pc}
    } else if (protect_tlv_size != 0) {
    48a2:	2c00      	cmp	r4, #0
    48a4:	d0f2      	beq.n	488c <boot_read_image_size.isra.0+0x5a>
    48a6:	e7f7      	b.n	4898 <boot_read_image_size.isra.0+0x66>
    *size = off + protect_tlv_size + info.it_tlv_tot;
    48a8:	f8bd 1006 	ldrh.w	r1, [sp, #6]
    48ac:	4421      	add	r1, r4
    48ae:	4429      	add	r1, r5
    48b0:	6031      	str	r1, [r6, #0]
    rc = 0;
    48b2:	e7f1      	b.n	4898 <boot_read_image_size.isra.0+0x66>

000048b4 <boot_read_sectors>:
{
    48b4:	b537      	push	{r0, r1, r2, r4, r5, lr}
    rc = flash_area_get_sectors(flash_area, &num_sectors, out_sectors);
    48b6:	6a42      	ldr	r2, [r0, #36]	; 0x24
{
    48b8:	4604      	mov	r4, r0
    uint32_t num_sectors = BOOT_MAX_IMG_SECTORS;
    48ba:	2580      	movs	r5, #128	; 0x80
    rc = flash_area_get_sectors(flash_area, &num_sectors, out_sectors);
    48bc:	a901      	add	r1, sp, #4
    48be:	2002      	movs	r0, #2
    uint32_t num_sectors = BOOT_MAX_IMG_SECTORS;
    48c0:	9501      	str	r5, [sp, #4]
    rc = flash_area_get_sectors(flash_area, &num_sectors, out_sectors);
    48c2:	f7fd fa03 	bl	1ccc <flash_area_get_sectors>
    if (rc != 0) {
    48c6:	b958      	cbnz	r0, 48e0 <boot_read_sectors+0x2c>
    *out_num_sectors = num_sectors;
    48c8:	9b01      	ldr	r3, [sp, #4]
    rc = flash_area_get_sectors(flash_area, &num_sectors, out_sectors);
    48ca:	6d22      	ldr	r2, [r4, #80]	; 0x50
    *out_num_sectors = num_sectors;
    48cc:	62a3      	str	r3, [r4, #40]	; 0x28
    rc = flash_area_get_sectors(flash_area, &num_sectors, out_sectors);
    48ce:	a901      	add	r1, sp, #4
    48d0:	2005      	movs	r0, #5
    uint32_t num_sectors = BOOT_MAX_IMG_SECTORS;
    48d2:	9501      	str	r5, [sp, #4]
    rc = flash_area_get_sectors(flash_area, &num_sectors, out_sectors);
    48d4:	f7fd f9fa 	bl	1ccc <flash_area_get_sectors>
    if (rc != 0) {
    48d8:	4605      	mov	r5, r0
    48da:	b128      	cbz	r0, 48e8 <boot_read_sectors+0x34>
        return BOOT_EFLASH_SEC;
    48dc:	2509      	movs	r5, #9
    48de:	e000      	b.n	48e2 <boot_read_sectors+0x2e>
        return BOOT_EFLASH;
    48e0:	2501      	movs	r5, #1
}
    48e2:	4628      	mov	r0, r5
    48e4:	b003      	add	sp, #12
    48e6:	bd30      	pop	{r4, r5, pc}
    *out_num_sectors = num_sectors;
    48e8:	9b01      	ldr	r3, [sp, #4]
    elem_sz = flash_area_align(BOOT_IMG_AREA(state, BOOT_PRIMARY_SLOT));
    48ea:	6a20      	ldr	r0, [r4, #32]
    *out_num_sectors = num_sectors;
    48ec:	6563      	str	r3, [r4, #84]	; 0x54
    elem_sz = flash_area_align(BOOT_IMG_AREA(state, BOOT_PRIMARY_SLOT));
    48ee:	f001 f970 	bl	5bd2 <flash_area_align>
    BOOT_WRITE_SZ(state) = boot_write_sz(state);
    48f2:	65e0      	str	r0, [r4, #92]	; 0x5c
    return 0;
    48f4:	e7f5      	b.n	48e2 <boot_read_sectors+0x2e>

000048f6 <boot_status_reset>:
    bs->idx = BOOT_STATUS_IDX_0;
    48f6:	2301      	movs	r3, #1
    48f8:	6003      	str	r3, [r0, #0]
    bs->state = BOOT_STATUS_STATE_0;
    48fa:	f103 2301 	add.w	r3, r3, #16777472	; 0x1000100
    48fe:	6043      	str	r3, [r0, #4]
    bs->swap_size = 0;
    4900:	2300      	movs	r3, #0
    bs->source = 0;
    4902:	e9c0 3302 	strd	r3, r3, [r0, #8]
}
    4906:	4770      	bx	lr

00004908 <boot_status_is_reset>:
            bs->idx == BOOT_STATUS_IDX_0 &&
    4908:	7943      	ldrb	r3, [r0, #5]
    490a:	2b01      	cmp	r3, #1
    490c:	d107      	bne.n	491e <boot_status_is_reset+0x16>
    return (bs->op == BOOT_STATUS_OP_MOVE &&
    490e:	6803      	ldr	r3, [r0, #0]
    4910:	2b01      	cmp	r3, #1
    4912:	d104      	bne.n	491e <boot_status_is_reset+0x16>
            bs->idx == BOOT_STATUS_IDX_0 &&
    4914:	7900      	ldrb	r0, [r0, #4]
    4916:	1e43      	subs	r3, r0, #1
    4918:	4258      	negs	r0, r3
    491a:	4158      	adcs	r0, r3
    491c:	4770      	bx	lr
    491e:	2000      	movs	r0, #0
}
    4920:	4770      	bx	lr

00004922 <boot_write_status>:
{
    4922:	b57f      	push	{r0, r1, r2, r3, r4, r5, r6, lr}
    4924:	4606      	mov	r6, r0
    4926:	460d      	mov	r5, r1
    rc = flash_area_open(area_id, &fap);
    4928:	2002      	movs	r0, #2
    492a:	a901      	add	r1, sp, #4
    492c:	f7fd f9b0 	bl	1c90 <flash_area_open>
    if (rc != 0) {
    4930:	bb38      	cbnz	r0, 4982 <boot_write_status+0x60>
    off = boot_status_off(fap) +
    4932:	9801      	ldr	r0, [sp, #4]
    4934:	f7ff ff43 	bl	47be <boot_status_off>
          boot_status_internal_off(bs, BOOT_WRITE_SZ(state));
    4938:	6df1      	ldr	r1, [r6, #92]	; 0x5c
    off = boot_status_off(fap) +
    493a:	4604      	mov	r4, r0
          boot_status_internal_off(bs, BOOT_WRITE_SZ(state));
    493c:	4628      	mov	r0, r5
    493e:	f000 f8e5 	bl	4b0c <boot_status_internal_off>
    off = boot_status_off(fap) +
    4942:	4404      	add	r4, r0
    align = flash_area_align(fap);
    4944:	9801      	ldr	r0, [sp, #4]
    4946:	f001 f944 	bl	5bd2 <flash_area_align>
    494a:	4606      	mov	r6, r0
    erased_val = flash_area_erased_val(fap);
    494c:	9801      	ldr	r0, [sp, #4]
    494e:	f001 f949 	bl	5be4 <flash_area_erased_val>
    memset(buf, erased_val, BOOT_MAX_ALIGN);
    4952:	2208      	movs	r2, #8
    erased_val = flash_area_erased_val(fap);
    4954:	4601      	mov	r1, r0
    memset(buf, erased_val, BOOT_MAX_ALIGN);
    4956:	eb0d 0002 	add.w	r0, sp, r2
    495a:	f001 f9b2 	bl	5cc2 <memset>
    buf[0] = bs->state;
    495e:	792b      	ldrb	r3, [r5, #4]
    4960:	f88d 3008 	strb.w	r3, [sp, #8]
    rc = flash_area_write(fap, off, buf, align);
    4964:	4621      	mov	r1, r4
    4966:	9801      	ldr	r0, [sp, #4]
    4968:	4633      	mov	r3, r6
    496a:	aa02      	add	r2, sp, #8
    496c:	f001 f8fe 	bl	5b6c <flash_area_write>
    if (rc != 0) {
    4970:	1e04      	subs	r4, r0, #0
    flash_area_close(fap);
    4972:	9801      	ldr	r0, [sp, #4]
    if (rc != 0) {
    4974:	bf18      	it	ne
    4976:	2401      	movne	r4, #1
    flash_area_close(fap);
    4978:	f001 f8db 	bl	5b32 <flash_area_close>
}
    497c:	4620      	mov	r0, r4
    497e:	b004      	add	sp, #16
    4980:	bd70      	pop	{r4, r5, r6, pc}
        return BOOT_EFLASH;
    4982:	2401      	movs	r4, #1
    4984:	e7fa      	b.n	497c <boot_write_status+0x5a>

00004986 <boot_erase_region>:
    return flash_area_erase(fap, off, sz);
    4986:	f001 b90d 	b.w	5ba4 <flash_area_erase>

0000498a <swap_erase_trailer_sectors>:

#if defined(MCUBOOT_SWAP_USING_SCRATCH) || defined(MCUBOOT_SWAP_USING_MOVE)
int
swap_erase_trailer_sectors(const struct boot_loader_state *state,
                           const struct flash_area *fap)
{
    498a:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    498e:	460e      	mov	r6, r1
    int rc;

    BOOT_LOG_DBG("erasing trailer; fa_id=%d", flash_area_get_id(fap));

    image_index = BOOT_CURR_IMG(state);
    fa_id_primary = flash_area_id_from_multi_image_slot(image_index,
    4990:	2100      	movs	r1, #0
{
    4992:	4607      	mov	r7, r0
    fa_id_primary = flash_area_id_from_multi_image_slot(image_index,
    4994:	4608      	mov	r0, r1
    4996:	f7ff fe2f 	bl	45f8 <flash_area_id_from_multi_image_slot>
            BOOT_PRIMARY_SLOT);
    fa_id_secondary = flash_area_id_from_multi_image_slot(image_index,
    499a:	2101      	movs	r1, #1
    fa_id_primary = flash_area_id_from_multi_image_slot(image_index,
    499c:	4604      	mov	r4, r0
    fa_id_secondary = flash_area_id_from_multi_image_slot(image_index,
    499e:	2000      	movs	r0, #0
    49a0:	f7ff fe2a 	bl	45f8 <flash_area_id_from_multi_image_slot>
            BOOT_SECONDARY_SLOT);

    if (flash_area_get_id(fap) == fa_id_primary) {
    49a4:	7833      	ldrb	r3, [r6, #0]
    49a6:	429c      	cmp	r4, r3
    49a8:	d021      	beq.n	49ee <swap_erase_trailer_sectors+0x64>
        slot = BOOT_PRIMARY_SLOT;
    } else if (flash_area_get_id(fap) == fa_id_secondary) {
    49aa:	4298      	cmp	r0, r3
    49ac:	d121      	bne.n	49f2 <swap_erase_trailer_sectors+0x68>
        slot = BOOT_SECONDARY_SLOT;
    49ae:	2501      	movs	r5, #1
    return BOOT_IMG(state, slot).num_sectors;
    49b0:	232c      	movs	r3, #44	; 0x2c
    49b2:	fb03 7505 	mla	r5, r3, r5, r7
        return BOOT_EFLASH;
    }

    /* delete starting from last sector and moving to beginning */
    sector = boot_img_num_sectors(state, slot) - 1;
    trailer_sz = boot_trailer_sz(BOOT_WRITE_SZ(state));
    49b6:	6df8      	ldr	r0, [r7, #92]	; 0x5c
    sector = boot_img_num_sectors(state, slot) - 1;
    49b8:	6aac      	ldr	r4, [r5, #40]	; 0x28
    trailer_sz = boot_trailer_sz(BOOT_WRITE_SZ(state));
    49ba:	f7ff feee 	bl	479a <boot_trailer_sz>
    sector = boot_img_num_sectors(state, slot) - 1;
    49be:	3c01      	subs	r4, #1
    trailer_sz = boot_trailer_sz(BOOT_WRITE_SZ(state));
    49c0:	4607      	mov	r7, r0
    total_sz = 0;
    49c2:	f04f 0800 	mov.w	r8, #0
    return flash_sector_get_size(&BOOT_IMG(state, slot).sectors[sector]);
    49c6:	6a6b      	ldr	r3, [r5, #36]	; 0x24
    49c8:	eb03 02c4 	add.w	r2, r3, r4, lsl #3
    return flash_sector_get_off(&BOOT_IMG(state, slot).sectors[sector]) -
    49cc:	f853 1034 	ldr.w	r1, [r3, r4, lsl #3]
	return fs->fs_size;
    49d0:	f8d2 9004 	ldr.w	r9, [r2, #4]
    49d4:	681b      	ldr	r3, [r3, #0]
    do {
        sz = boot_img_sector_size(state, slot, sector);
        off = boot_img_sector_off(state, slot, sector);
        rc = boot_erase_region(fap, off, sz);
    49d6:	464a      	mov	r2, r9
    49d8:	1ac9      	subs	r1, r1, r3
    49da:	4630      	mov	r0, r6
        assert(rc == 0);

        sector--;
        total_sz += sz;
    49dc:	44c8      	add	r8, r9
        rc = boot_erase_region(fap, off, sz);
    49de:	f7ff ffd2 	bl	4986 <boot_erase_region>
    } while (total_sz < trailer_sz);
    49e2:	45b8      	cmp	r8, r7
        sector--;
    49e4:	f104 34ff 	add.w	r4, r4, #4294967295
    } while (total_sz < trailer_sz);
    49e8:	d3ed      	bcc.n	49c6 <swap_erase_trailer_sectors+0x3c>

    return rc;
}
    49ea:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
        slot = BOOT_PRIMARY_SLOT;
    49ee:	2500      	movs	r5, #0
    49f0:	e7de      	b.n	49b0 <swap_erase_trailer_sectors+0x26>
        return BOOT_EFLASH;
    49f2:	2001      	movs	r0, #1
    49f4:	e7f9      	b.n	49ea <swap_erase_trailer_sectors+0x60>

000049f6 <swap_status_init>:

int
swap_status_init(const struct boot_loader_state *state,
                 const struct flash_area *fap,
                 const struct boot_status *bs)
{
    49f6:	b537      	push	{r0, r1, r2, r4, r5, lr}
    49f8:	4615      	mov	r5, r2
    49fa:	460c      	mov	r4, r1

    image_index = BOOT_CURR_IMG(state);

    BOOT_LOG_DBG("initializing status; fa_id=%d", flash_area_get_id(fap));

    rc = boot_read_swap_state_by_id(FLASH_AREA_IMAGE_SECONDARY(image_index),
    49fc:	2005      	movs	r0, #5
    49fe:	4669      	mov	r1, sp
    4a00:	f001 fc8f 	bl	6322 <boot_read_swap_state_by_id>
            &swap_state);
    assert(rc == 0);

    if (bs->swap_type != BOOT_SWAP_TYPE_NONE) {
    4a04:	79e9      	ldrb	r1, [r5, #7]
    4a06:	2901      	cmp	r1, #1
    4a08:	d003      	beq.n	4a12 <swap_status_init+0x1c>
        rc = boot_write_swap_info(fap, bs->swap_type, image_index);
    4a0a:	2200      	movs	r2, #0
    4a0c:	4620      	mov	r0, r4
    4a0e:	f001 fc9c 	bl	634a <boot_write_swap_info>
        assert(rc == 0);
    }

    if (swap_state.image_ok == BOOT_FLAG_SET) {
    4a12:	f89d 3003 	ldrb.w	r3, [sp, #3]
    4a16:	2b01      	cmp	r3, #1
    4a18:	d102      	bne.n	4a20 <swap_status_init+0x2a>
        rc = boot_write_image_ok(fap);
    4a1a:	4620      	mov	r0, r4
    4a1c:	f001 fc74 	bl	6308 <boot_write_image_ok>
        assert(rc == 0);
    }

    rc = boot_write_swap_size(fap, bs->swap_size);
    4a20:	68a9      	ldr	r1, [r5, #8]
    4a22:	4620      	mov	r0, r4
    4a24:	f7ff fede 	bl	47e4 <boot_write_swap_size>

    rc = boot_write_enc_key(fap, 1, bs);
    assert(rc == 0);
#endif

    rc = boot_write_magic(fap);
    4a28:	4620      	mov	r0, r4
    4a2a:	f7fe fd1d 	bl	3468 <boot_write_magic>
    assert(rc == 0);

    return 0;
}
    4a2e:	2000      	movs	r0, #0
    4a30:	b003      	add	sp, #12
    4a32:	bd30      	pop	{r4, r5, pc}

00004a34 <swap_read_status>:

int
swap_read_status(struct boot_loader_state *state, struct boot_status *bs)
{
    4a34:	b573      	push	{r0, r1, r4, r5, r6, lr}
    4a36:	460d      	mov	r5, r1
    4a38:	4606      	mov	r6, r0
    uint32_t off;
    uint8_t swap_info;
    int area_id;
    int rc;

    bs->source = swap_status_source(state);
    4a3a:	f7fc fa2b 	bl	e94 <swap_status_source>
    4a3e:	4604      	mov	r4, r0
    4a40:	60e8      	str	r0, [r5, #12]
    switch (bs->source) {
    4a42:	b350      	cbz	r0, 4a9a <swap_read_status+0x66>
    4a44:	2802      	cmp	r0, #2
    4a46:	d12d      	bne.n	4aa4 <swap_read_status+0x70>
    default:
        assert(0);
        return BOOT_EBADARGS;
    }

    rc = flash_area_open(area_id, &fap);
    4a48:	a901      	add	r1, sp, #4
    4a4a:	f7fd f921 	bl	1c90 <flash_area_open>
    if (rc != 0) {
    4a4e:	bb58      	cbnz	r0, 4aa8 <swap_read_status+0x74>
        return BOOT_EFLASH;
    }

    rc = swap_read_status_bytes(fap, state, bs);
    4a50:	9801      	ldr	r0, [sp, #4]
    4a52:	462a      	mov	r2, r5
    4a54:	4631      	mov	r1, r6
    4a56:	f7fc f983 	bl	d60 <swap_read_status_bytes>
    if (rc == 0) {
    4a5a:	4604      	mov	r4, r0
    4a5c:	b9d0      	cbnz	r0, 4a94 <swap_read_status+0x60>
        off = boot_swap_info_off(fap);
    4a5e:	9801      	ldr	r0, [sp, #4]
    4a60:	f001 fbe5 	bl	622e <boot_swap_info_off>
        rc = flash_area_read(fap, off, &swap_info, sizeof swap_info);
    4a64:	2301      	movs	r3, #1
        off = boot_swap_info_off(fap);
    4a66:	4601      	mov	r1, r0
        rc = flash_area_read(fap, off, &swap_info, sizeof swap_info);
    4a68:	f10d 0203 	add.w	r2, sp, #3
    4a6c:	9801      	ldr	r0, [sp, #4]
    4a6e:	f001 f861 	bl	5b34 <flash_area_read>
        if (rc != 0) {
    4a72:	4604      	mov	r4, r0
    4a74:	b9a0      	cbnz	r0, 4aa0 <swap_read_status+0x6c>
            rc = BOOT_EFLASH;
            goto done;
        }

        if (bootutil_buffer_is_erased(fap, &swap_info, sizeof swap_info)) {
    4a76:	9801      	ldr	r0, [sp, #4]
    4a78:	2201      	movs	r2, #1
    4a7a:	f10d 0103 	add.w	r1, sp, #3
    4a7e:	f001 fbea 	bl	6256 <bootutil_buffer_is_erased>
    4a82:	b110      	cbz	r0, 4a8a <swap_read_status+0x56>
            BOOT_SET_SWAP_INFO(swap_info, 0, BOOT_SWAP_TYPE_NONE);
    4a84:	2301      	movs	r3, #1
    4a86:	f88d 3003 	strb.w	r3, [sp, #3]
            rc = 0;
        }

        /* Extract the swap type info */
        bs->swap_type = BOOT_GET_SWAP_TYPE(swap_info);
    4a8a:	f89d 3003 	ldrb.w	r3, [sp, #3]
    4a8e:	f003 030f 	and.w	r3, r3, #15
    4a92:	71eb      	strb	r3, [r5, #7]
    }

done:
    flash_area_close(fap);
    4a94:	9801      	ldr	r0, [sp, #4]
    4a96:	f001 f84c 	bl	5b32 <flash_area_close>

    return rc;
}
    4a9a:	4620      	mov	r0, r4
    4a9c:	b002      	add	sp, #8
    4a9e:	bd70      	pop	{r4, r5, r6, pc}
            rc = BOOT_EFLASH;
    4aa0:	2401      	movs	r4, #1
    4aa2:	e7f7      	b.n	4a94 <swap_read_status+0x60>
    switch (bs->source) {
    4aa4:	2407      	movs	r4, #7
    4aa6:	e7f8      	b.n	4a9a <swap_read_status+0x66>
        return BOOT_EFLASH;
    4aa8:	2401      	movs	r4, #1
    4aaa:	e7f6      	b.n	4a9a <swap_read_status+0x66>

00004aac <swap_set_copy_done>:

int
swap_set_copy_done(uint8_t image_index)
{
    4aac:	b513      	push	{r0, r1, r4, lr}
    const struct flash_area *fap;
    int rc;

    rc = flash_area_open(FLASH_AREA_IMAGE_PRIMARY(image_index),
    4aae:	2002      	movs	r0, #2
    4ab0:	a901      	add	r1, sp, #4
    4ab2:	f7fd f8ed 	bl	1c90 <flash_area_open>
            &fap);
    if (rc != 0) {
    4ab6:	b948      	cbnz	r0, 4acc <swap_set_copy_done+0x20>
        return BOOT_EFLASH;
    }

    rc = boot_write_copy_done(fap);
    4ab8:	9801      	ldr	r0, [sp, #4]
    4aba:	f7ff fe8b 	bl	47d4 <boot_write_copy_done>
    4abe:	4604      	mov	r4, r0
    flash_area_close(fap);
    4ac0:	9801      	ldr	r0, [sp, #4]
    4ac2:	f001 f836 	bl	5b32 <flash_area_close>
    return rc;
}
    4ac6:	4620      	mov	r0, r4
    4ac8:	b002      	add	sp, #8
    4aca:	bd10      	pop	{r4, pc}
        return BOOT_EFLASH;
    4acc:	2401      	movs	r4, #1
    4ace:	e7fa      	b.n	4ac6 <swap_set_copy_done+0x1a>

00004ad0 <swap_set_image_ok>:

int
swap_set_image_ok(uint8_t image_index)
{
    4ad0:	b51f      	push	{r0, r1, r2, r3, r4, lr}
    const struct flash_area *fap;
    struct boot_swap_state state;
    int rc;

    rc = flash_area_open(FLASH_AREA_IMAGE_PRIMARY(image_index),
    4ad2:	2002      	movs	r0, #2
    4ad4:	a901      	add	r1, sp, #4
    4ad6:	f7fd f8db 	bl	1c90 <flash_area_open>
            &fap);
    if (rc != 0) {
    4ada:	b9a8      	cbnz	r0, 4b08 <swap_set_image_ok+0x38>
        return BOOT_EFLASH;
    }

    rc = boot_read_swap_state(fap, &state);
    4adc:	9801      	ldr	r0, [sp, #4]
    4ade:	a902      	add	r1, sp, #8
    4ae0:	f7fe fce2 	bl	34a8 <boot_read_swap_state>
    if (rc != 0) {
    4ae4:	4604      	mov	r4, r0
    4ae6:	b968      	cbnz	r0, 4b04 <swap_set_image_ok+0x34>
        rc = BOOT_EFLASH;
        goto out;
    }

    if (state.image_ok == BOOT_FLAG_UNSET) {
    4ae8:	f89d 300b 	ldrb.w	r3, [sp, #11]
    4aec:	2b03      	cmp	r3, #3
    4aee:	d103      	bne.n	4af8 <swap_set_image_ok+0x28>
        rc = boot_write_image_ok(fap);
    4af0:	9801      	ldr	r0, [sp, #4]
    4af2:	f001 fc09 	bl	6308 <boot_write_image_ok>
    4af6:	4604      	mov	r4, r0
    }

out:
    flash_area_close(fap);
    4af8:	9801      	ldr	r0, [sp, #4]
    4afa:	f001 f81a 	bl	5b32 <flash_area_close>
    return rc;
}
    4afe:	4620      	mov	r0, r4
    4b00:	b004      	add	sp, #16
    4b02:	bd10      	pop	{r4, pc}
        rc = BOOT_EFLASH;
    4b04:	2401      	movs	r4, #1
    4b06:	e7f7      	b.n	4af8 <swap_set_image_ok+0x28>
        return BOOT_EFLASH;
    4b08:	2401      	movs	r4, #1
    4b0a:	e7f8      	b.n	4afe <swap_set_image_ok+0x2e>

00004b0c <boot_status_internal_off>:
{
    4b0c:	b530      	push	{r4, r5, lr}
    idx_sz = elem_sz * ((bs->op == BOOT_STATUS_OP_MOVE) ?
    4b0e:	7943      	ldrb	r3, [r0, #5]
           (bs->state - BOOT_STATUS_STATE_0) * elem_sz;
    4b10:	7902      	ldrb	r2, [r0, #4]
            BOOT_STATUS_MOVE_STATE_COUNT : BOOT_STATUS_SWAP_STATE_COUNT);
    4b12:	2b01      	cmp	r3, #1
    4b14:	bf0c      	ite	eq
    4b16:	2301      	moveq	r3, #1
    4b18:	2302      	movne	r3, #2
    idx_sz = elem_sz * ((bs->op == BOOT_STATUS_OP_MOVE) ?
    4b1a:	fb01 f403 	mul.w	r4, r1, r3
           (bs->idx - BOOT_STATUS_IDX_0) * idx_sz +
    4b1e:	6803      	ldr	r3, [r0, #0]
    4b20:	f103 33ff 	add.w	r3, r3, #4294967295
           (bs->state - BOOT_STATUS_STATE_0) * elem_sz;
    4b24:	f102 32ff 	add.w	r2, r2, #4294967295
           (bs->idx - BOOT_STATUS_IDX_0) * idx_sz +
    4b28:	fb04 f303 	mul.w	r3, r4, r3
               0 : (BOOT_MAX_IMG_SECTORS * BOOT_STATUS_MOVE_STATE_COUNT * elem_sz)) +
    4b2c:	bf14      	ite	ne
    4b2e:	01cd      	lslne	r5, r1, #7
    4b30:	2500      	moveq	r5, #0
           (bs->idx - BOOT_STATUS_IDX_0) * idx_sz +
    4b32:	fb01 3102 	mla	r1, r1, r2, r3
}
    4b36:	1948      	adds	r0, r1, r5
    4b38:	bd30      	pop	{r4, r5, pc}

00004b3a <mbedtls_asn1_get_len>:
 */
int mbedtls_asn1_get_len( unsigned char **p,
                  const unsigned char *end,
                  size_t *len )
{
    if( ( end - *p ) < 1 )
    4b3a:	6803      	ldr	r3, [r0, #0]
{
    4b3c:	b570      	push	{r4, r5, r6, lr}
    if( ( end - *p ) < 1 )
    4b3e:	1acd      	subs	r5, r1, r3
    4b40:	2d00      	cmp	r5, #0
    4b42:	dd0d      	ble.n	4b60 <mbedtls_asn1_get_len+0x26>
        return( MBEDTLS_ERR_ASN1_OUT_OF_DATA );

    if( ( **p & 0x80 ) == 0 )
    4b44:	f993 6000 	ldrsb.w	r6, [r3]
    4b48:	781c      	ldrb	r4, [r3, #0]
    4b4a:	2e00      	cmp	r6, #0
    4b4c:	db0b      	blt.n	4b66 <mbedtls_asn1_get_len+0x2c>
        *len = *(*p)++;
    4b4e:	1c5c      	adds	r4, r3, #1
    4b50:	6004      	str	r4, [r0, #0]
    4b52:	781b      	ldrb	r3, [r3, #0]
    4b54:	6013      	str	r3, [r2, #0]
        default:
            return( MBEDTLS_ERR_ASN1_INVALID_LENGTH );
        }
    }

    if( *len > (size_t) ( end - *p ) )
    4b56:	6803      	ldr	r3, [r0, #0]
    4b58:	1ac9      	subs	r1, r1, r3
    4b5a:	6813      	ldr	r3, [r2, #0]
    4b5c:	428b      	cmp	r3, r1
    4b5e:	d932      	bls.n	4bc6 <mbedtls_asn1_get_len+0x8c>
        return( MBEDTLS_ERR_ASN1_OUT_OF_DATA );
    4b60:	f06f 005f 	mvn.w	r0, #95	; 0x5f

    return( 0 );
}
    4b64:	bd70      	pop	{r4, r5, r6, pc}
        switch( **p & 0x7F )
    4b66:	f004 047f 	and.w	r4, r4, #127	; 0x7f
    4b6a:	3c01      	subs	r4, #1
    4b6c:	2c03      	cmp	r4, #3
    4b6e:	d827      	bhi.n	4bc0 <mbedtls_asn1_get_len+0x86>
    4b70:	e8df f004 	tbb	[pc, r4]
    4b74:	1e120902 	.word	0x1e120902
            if( ( end - *p ) < 2 )
    4b78:	2d01      	cmp	r5, #1
    4b7a:	d0f1      	beq.n	4b60 <mbedtls_asn1_get_len+0x26>
            *len = (*p)[1];
    4b7c:	785c      	ldrb	r4, [r3, #1]
    4b7e:	6014      	str	r4, [r2, #0]
            (*p) += 2;
    4b80:	3302      	adds	r3, #2
            (*p) += 5;
    4b82:	6003      	str	r3, [r0, #0]
            break;
    4b84:	e7e7      	b.n	4b56 <mbedtls_asn1_get_len+0x1c>
            if( ( end - *p ) < 3 )
    4b86:	2d02      	cmp	r5, #2
    4b88:	ddea      	ble.n	4b60 <mbedtls_asn1_get_len+0x26>
            *len = ( (size_t)(*p)[1] << 8 ) | (*p)[2];
    4b8a:	f8b3 4001 	ldrh.w	r4, [r3, #1]
    4b8e:	ba64      	rev16	r4, r4
    4b90:	b2a4      	uxth	r4, r4
    4b92:	6014      	str	r4, [r2, #0]
            (*p) += 3;
    4b94:	3303      	adds	r3, #3
    4b96:	e7f4      	b.n	4b82 <mbedtls_asn1_get_len+0x48>
            if( ( end - *p ) < 4 )
    4b98:	2d03      	cmp	r5, #3
    4b9a:	dde1      	ble.n	4b60 <mbedtls_asn1_get_len+0x26>
                   ( (size_t)(*p)[2] << 8  ) | (*p)[3];
    4b9c:	789c      	ldrb	r4, [r3, #2]
            *len = ( (size_t)(*p)[1] << 16 ) |
    4b9e:	785d      	ldrb	r5, [r3, #1]
                   ( (size_t)(*p)[2] << 8  ) | (*p)[3];
    4ba0:	0224      	lsls	r4, r4, #8
            *len = ( (size_t)(*p)[1] << 16 ) |
    4ba2:	ea44 4405 	orr.w	r4, r4, r5, lsl #16
                   ( (size_t)(*p)[2] << 8  ) | (*p)[3];
    4ba6:	78dd      	ldrb	r5, [r3, #3]
    4ba8:	432c      	orrs	r4, r5
            *len = ( (size_t)(*p)[1] << 16 ) |
    4baa:	6014      	str	r4, [r2, #0]
            (*p) += 4;
    4bac:	3304      	adds	r3, #4
    4bae:	e7e8      	b.n	4b82 <mbedtls_asn1_get_len+0x48>
            if( ( end - *p ) < 5 )
    4bb0:	2d04      	cmp	r5, #4
    4bb2:	ddd5      	ble.n	4b60 <mbedtls_asn1_get_len+0x26>
            *len = ( (size_t)(*p)[1] << 24 ) | ( (size_t)(*p)[2] << 16 ) |
    4bb4:	f8d3 4001 	ldr.w	r4, [r3, #1]
    4bb8:	ba24      	rev	r4, r4
    4bba:	6014      	str	r4, [r2, #0]
            (*p) += 5;
    4bbc:	3305      	adds	r3, #5
    4bbe:	e7e0      	b.n	4b82 <mbedtls_asn1_get_len+0x48>
        switch( **p & 0x7F )
    4bc0:	f06f 0063 	mvn.w	r0, #99	; 0x63
    4bc4:	e7ce      	b.n	4b64 <mbedtls_asn1_get_len+0x2a>
    return( 0 );
    4bc6:	2000      	movs	r0, #0
    4bc8:	e7cc      	b.n	4b64 <mbedtls_asn1_get_len+0x2a>

00004bca <mbedtls_asn1_get_tag>:

int mbedtls_asn1_get_tag( unsigned char **p,
                  const unsigned char *end,
                  size_t *len, int tag )
{
    4bca:	b470      	push	{r4, r5, r6}
    if( ( end - *p ) < 1 )
    4bcc:	6804      	ldr	r4, [r0, #0]
    4bce:	1b0e      	subs	r6, r1, r4
    4bd0:	2e00      	cmp	r6, #0
    4bd2:	dd07      	ble.n	4be4 <mbedtls_asn1_get_tag+0x1a>
        return( MBEDTLS_ERR_ASN1_OUT_OF_DATA );

    if( **p != tag )
    4bd4:	7826      	ldrb	r6, [r4, #0]
    4bd6:	429e      	cmp	r6, r3
    4bd8:	d108      	bne.n	4bec <mbedtls_asn1_get_tag+0x22>
        return( MBEDTLS_ERR_ASN1_UNEXPECTED_TAG );

    (*p)++;
    4bda:	3401      	adds	r4, #1
    4bdc:	6004      	str	r4, [r0, #0]

    return( mbedtls_asn1_get_len( p, end, len ) );
}
    4bde:	bc70      	pop	{r4, r5, r6}
    return( mbedtls_asn1_get_len( p, end, len ) );
    4be0:	f7ff bfab 	b.w	4b3a <mbedtls_asn1_get_len>
        return( MBEDTLS_ERR_ASN1_OUT_OF_DATA );
    4be4:	f06f 005f 	mvn.w	r0, #95	; 0x5f
}
    4be8:	bc70      	pop	{r4, r5, r6}
    4bea:	4770      	bx	lr
        return( MBEDTLS_ERR_ASN1_UNEXPECTED_TAG );
    4bec:	f06f 0061 	mvn.w	r0, #97	; 0x61
    4bf0:	e7fa      	b.n	4be8 <mbedtls_asn1_get_tag+0x1e>

00004bf2 <mbedtls_asn1_get_bitstring_null>:
/*
 * Get a bit string without unused bits
 */
int mbedtls_asn1_get_bitstring_null( unsigned char **p, const unsigned char *end,
                             size_t *len )
{
    4bf2:	b538      	push	{r3, r4, r5, lr}
    int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED;

    if( ( ret = mbedtls_asn1_get_tag( p, end, len, MBEDTLS_ASN1_BIT_STRING ) ) != 0 )
    4bf4:	2303      	movs	r3, #3
{
    4bf6:	4604      	mov	r4, r0
    if( ( ret = mbedtls_asn1_get_tag( p, end, len, MBEDTLS_ASN1_BIT_STRING ) ) != 0 )
    4bf8:	f7ff ffe7 	bl	4bca <mbedtls_asn1_get_tag>
    4bfc:	b918      	cbnz	r0, 4c06 <mbedtls_asn1_get_bitstring_null+0x14>
        return( ret );

    if( *len == 0 )
    4bfe:	6813      	ldr	r3, [r2, #0]
    4c00:	b913      	cbnz	r3, 4c08 <mbedtls_asn1_get_bitstring_null+0x16>
        return( MBEDTLS_ERR_ASN1_INVALID_DATA );
    4c02:	f06f 0067 	mvn.w	r0, #103	; 0x67
    if( **p != 0 )
        return( MBEDTLS_ERR_ASN1_INVALID_DATA );
    ++( *p );

    return( 0 );
}
    4c06:	bd38      	pop	{r3, r4, r5, pc}
    --( *len );
    4c08:	3b01      	subs	r3, #1
    4c0a:	6013      	str	r3, [r2, #0]
    if( **p != 0 )
    4c0c:	6823      	ldr	r3, [r4, #0]
    4c0e:	781a      	ldrb	r2, [r3, #0]
    4c10:	2a00      	cmp	r2, #0
    4c12:	d1f6      	bne.n	4c02 <mbedtls_asn1_get_bitstring_null+0x10>
    ++( *p );
    4c14:	3301      	adds	r3, #1
    4c16:	6023      	str	r3, [r4, #0]
    return( 0 );
    4c18:	e7f5      	b.n	4c06 <mbedtls_asn1_get_bitstring_null+0x14>

00004c1a <mbedtls_asn1_get_alg>:
}

int mbedtls_asn1_get_alg( unsigned char **p,
                  const unsigned char *end,
                  mbedtls_asn1_buf *alg, mbedtls_asn1_buf *params )
{
    4c1a:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    4c1e:	4690      	mov	r8, r2
    4c20:	461f      	mov	r7, r3
    int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED;
    size_t len;

    if( ( ret = mbedtls_asn1_get_tag( p, end, &len,
    4c22:	aa01      	add	r2, sp, #4
    4c24:	2330      	movs	r3, #48	; 0x30
{
    4c26:	4605      	mov	r5, r0
    4c28:	4689      	mov	r9, r1
    if( ( ret = mbedtls_asn1_get_tag( p, end, &len,
    4c2a:	f7ff ffce 	bl	4bca <mbedtls_asn1_get_tag>
    4c2e:	4604      	mov	r4, r0
    4c30:	b9f8      	cbnz	r0, 4c72 <mbedtls_asn1_get_alg+0x58>
            MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) ) != 0 )
        return( ret );

    if( ( end - *p ) < 1 )
    4c32:	682e      	ldr	r6, [r5, #0]
    4c34:	eba9 0906 	sub.w	r9, r9, r6
    4c38:	f1b9 0f00 	cmp.w	r9, #0
    4c3c:	dd35      	ble.n	4caa <mbedtls_asn1_get_alg+0x90>
        return( MBEDTLS_ERR_ASN1_OUT_OF_DATA );

    alg->tag = **p;
    end = *p + len;
    4c3e:	9901      	ldr	r1, [sp, #4]
    alg->tag = **p;
    4c40:	7833      	ldrb	r3, [r6, #0]
    4c42:	4642      	mov	r2, r8
    end = *p + len;
    4c44:	440e      	add	r6, r1
    alg->tag = **p;
    4c46:	f842 3b04 	str.w	r3, [r2], #4

    if( ( ret = mbedtls_asn1_get_tag( p, end, &alg->len, MBEDTLS_ASN1_OID ) ) != 0 )
    4c4a:	4631      	mov	r1, r6
    4c4c:	2306      	movs	r3, #6
    4c4e:	4628      	mov	r0, r5
    4c50:	f7ff ffbb 	bl	4bca <mbedtls_asn1_get_tag>
    4c54:	4604      	mov	r4, r0
    4c56:	b960      	cbnz	r0, 4c72 <mbedtls_asn1_get_alg+0x58>
        return( ret );

    alg->p = *p;
    4c58:	682a      	ldr	r2, [r5, #0]
    *p += alg->len;
    4c5a:	f8d8 1004 	ldr.w	r1, [r8, #4]
    alg->p = *p;
    4c5e:	f8c8 2008 	str.w	r2, [r8, #8]
    *p += alg->len;
    4c62:	1853      	adds	r3, r2, r1

    if( *p == end )
    4c64:	42b3      	cmp	r3, r6
    *p += alg->len;
    4c66:	602b      	str	r3, [r5, #0]
    if( *p == end )
    4c68:	d107      	bne.n	4c7a <mbedtls_asn1_get_alg+0x60>
    {
        mbedtls_platform_zeroize( params, sizeof(mbedtls_asn1_buf) );
    4c6a:	210c      	movs	r1, #12
    4c6c:	4638      	mov	r0, r7
    4c6e:	f7fc fad5 	bl	121c <mbedtls_platform_zeroize>

    if( *p != end )
        return( MBEDTLS_ERR_ASN1_LENGTH_MISMATCH );

    return( 0 );
}
    4c72:	4620      	mov	r0, r4
    4c74:	b003      	add	sp, #12
    4c76:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
    params->tag = **p;
    4c7a:	5c51      	ldrb	r1, [r2, r1]
    4c7c:	463a      	mov	r2, r7
    (*p)++;
    4c7e:	3301      	adds	r3, #1
    params->tag = **p;
    4c80:	f842 1b04 	str.w	r1, [r2], #4
    if( ( ret = mbedtls_asn1_get_len( p, end, &params->len ) ) != 0 )
    4c84:	4628      	mov	r0, r5
    (*p)++;
    4c86:	602b      	str	r3, [r5, #0]
    if( ( ret = mbedtls_asn1_get_len( p, end, &params->len ) ) != 0 )
    4c88:	4631      	mov	r1, r6
    4c8a:	f7ff ff56 	bl	4b3a <mbedtls_asn1_get_len>
    4c8e:	4604      	mov	r4, r0
    4c90:	2800      	cmp	r0, #0
    4c92:	d1ee      	bne.n	4c72 <mbedtls_asn1_get_alg+0x58>
    params->p = *p;
    4c94:	682b      	ldr	r3, [r5, #0]
    *p += params->len;
    4c96:	687a      	ldr	r2, [r7, #4]
    params->p = *p;
    4c98:	60bb      	str	r3, [r7, #8]
    *p += params->len;
    4c9a:	4413      	add	r3, r2
        return( MBEDTLS_ERR_ASN1_LENGTH_MISMATCH );
    4c9c:	42b3      	cmp	r3, r6
    *p += params->len;
    4c9e:	602b      	str	r3, [r5, #0]
        return( MBEDTLS_ERR_ASN1_LENGTH_MISMATCH );
    4ca0:	bf0c      	ite	eq
    4ca2:	4604      	moveq	r4, r0
    4ca4:	f06f 0465 	mvnne.w	r4, #101	; 0x65
    4ca8:	e7e3      	b.n	4c72 <mbedtls_asn1_get_alg+0x58>
        return( MBEDTLS_ERR_ASN1_OUT_OF_DATA );
    4caa:	f06f 045f 	mvn.w	r4, #95	; 0x5f
    4cae:	e7e0      	b.n	4c72 <mbedtls_asn1_get_alg+0x58>

00004cb0 <uECC_vli_add>:
{
    4cb0:	b5f0      	push	{r4, r5, r6, r7, lr}
	for (i = 0; i < num_words; ++i) {
    4cb2:	2400      	movs	r4, #0
{
    4cb4:	4606      	mov	r6, r0
	uECC_word_t carry = 0;
    4cb6:	4620      	mov	r0, r4
	for (i = 0; i < num_words; ++i) {
    4cb8:	b265      	sxtb	r5, r4
    4cba:	42ab      	cmp	r3, r5
    4cbc:	dc00      	bgt.n	4cc0 <uECC_vli_add+0x10>
}
    4cbe:	bdf0      	pop	{r4, r5, r6, r7, pc}
		uECC_word_t sum = left[i] + right[i] + carry;
    4cc0:	f851 7024 	ldr.w	r7, [r1, r4, lsl #2]
    4cc4:	f852 5024 	ldr.w	r5, [r2, r4, lsl #2]
    4cc8:	443d      	add	r5, r7
    4cca:	4405      	add	r5, r0
	return (p_true*(cond)) | (p_false*(!cond));
    4ccc:	42af      	cmp	r7, r5
    4cce:	f000 0001 	and.w	r0, r0, #1
    4cd2:	bf18      	it	ne
    4cd4:	2000      	movne	r0, #0
		result[i] = sum;
    4cd6:	f846 5024 	str.w	r5, [r6, r4, lsl #2]
	return (p_true*(cond)) | (p_false*(!cond));
    4cda:	bf88      	it	hi
    4cdc:	f040 0001 	orrhi.w	r0, r0, #1
	for (i = 0; i < num_words; ++i) {
    4ce0:	3401      	adds	r4, #1
    4ce2:	e7e9      	b.n	4cb8 <uECC_vli_add+0x8>

00004ce4 <uECC_vli_rshift1>:
	vli += num_words;
    4ce4:	eb00 0181 	add.w	r1, r0, r1, lsl #2
	uECC_word_t carry = 0;
    4ce8:	2300      	movs	r3, #0
	while (vli-- > end) {
    4cea:	4288      	cmp	r0, r1
    4cec:	d300      	bcc.n	4cf0 <uECC_vli_rshift1+0xc>
}
    4cee:	4770      	bx	lr
		uECC_word_t temp = *vli;
    4cf0:	f851 2d04 	ldr.w	r2, [r1, #-4]!
		*vli = (temp >> 1) | carry;
    4cf4:	ea43 0352 	orr.w	r3, r3, r2, lsr #1
    4cf8:	600b      	str	r3, [r1, #0]
		carry = temp << (uECC_WORD_BITS - 1);
    4cfa:	07d3      	lsls	r3, r2, #31
    4cfc:	e7f5      	b.n	4cea <uECC_vli_rshift1+0x6>

00004cfe <vli_modInv_update>:
	if (!EVEN(uv)) {
    4cfe:	6803      	ldr	r3, [r0, #0]
{
    4d00:	b570      	push	{r4, r5, r6, lr}
	if (!EVEN(uv)) {
    4d02:	f013 0601 	ands.w	r6, r3, #1
{
    4d06:	4605      	mov	r5, r0
    4d08:	4614      	mov	r4, r2
	if (!EVEN(uv)) {
    4d0a:	d005      	beq.n	4d18 <vli_modInv_update+0x1a>
		carry = uECC_vli_add(uv, uv, mod, num_words);
    4d0c:	4613      	mov	r3, r2
    4d0e:	460a      	mov	r2, r1
    4d10:	4601      	mov	r1, r0
    4d12:	f7ff ffcd 	bl	4cb0 <uECC_vli_add>
    4d16:	4606      	mov	r6, r0
	uECC_vli_rshift1(uv, num_words);
    4d18:	4621      	mov	r1, r4
    4d1a:	4628      	mov	r0, r5
    4d1c:	f7ff ffe2 	bl	4ce4 <uECC_vli_rshift1>
	if (carry) {
    4d20:	b146      	cbz	r6, 4d34 <vli_modInv_update+0x36>
		uv[num_words - 1] |= HIGH_BIT_SET;
    4d22:	f104 4280 	add.w	r2, r4, #1073741824	; 0x40000000
    4d26:	3a01      	subs	r2, #1
    4d28:	f855 3022 	ldr.w	r3, [r5, r2, lsl #2]
    4d2c:	f043 4300 	orr.w	r3, r3, #2147483648	; 0x80000000
    4d30:	f845 3022 	str.w	r3, [r5, r2, lsl #2]
}
    4d34:	bd70      	pop	{r4, r5, r6, pc}

00004d36 <uECC_vli_mult>:
	for (k = 0; k < num_words; ++k) {
    4d36:	f04f 0c00 	mov.w	ip, #0
{
    4d3a:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
	uECC_word_t r1 = 0;
    4d3e:	4665      	mov	r5, ip
	uECC_word_t r0 = 0;
    4d40:	4664      	mov	r4, ip
	for (k = 0; k < num_words; ++k) {
    4d42:	fa4f f98c 	sxtb.w	r9, ip
    4d46:	454b      	cmp	r3, r9
    4d48:	dc16      	bgt.n	4d78 <uECC_vli_mult+0x42>
	for (k = num_words; k < num_words * 2 - 1; ++k) {
    4d4a:	f04f 36ff 	mov.w	r6, #4294967295
    4d4e:	eb06 0643 	add.w	r6, r6, r3, lsl #1
    4d52:	9601      	str	r6, [sp, #4]
    4d54:	f04f 0800 	mov.w	r8, #0
    4d58:	9f01      	ldr	r7, [sp, #4]
    4d5a:	fa53 fe88 	uxtab	lr, r3, r8
    4d5e:	fa4f fe8e 	sxtb.w	lr, lr
    4d62:	45be      	cmp	lr, r7
    4d64:	fa5f f688 	uxtb.w	r6, r8
    4d68:	db26      	blt.n	4db8 <uECC_vli_mult+0x82>
	result[num_words * 2 - 1] = r0;
    4d6a:	eb00 00c3 	add.w	r0, r0, r3, lsl #3
    4d6e:	f840 4c04 	str.w	r4, [r0, #-4]
}
    4d72:	b003      	add	sp, #12
    4d74:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
	for (k = 0; k < num_words; ++k) {
    4d78:	f04f 0e00 	mov.w	lr, #0
    4d7c:	eb02 0a8c 	add.w	sl, r2, ip, lsl #2
    4d80:	46f0      	mov	r8, lr
	uECC_dword_t p = (uECC_dword_t)a * b;
    4d82:	f851 702e 	ldr.w	r7, [r1, lr, lsl #2]
			muladd(left[i], right[k - i], &r0, &r1, &r2);
    4d86:	f85a 6904 	ldr.w	r6, [sl], #-4
	uECC_dword_t p = (uECC_dword_t)a * b;
    4d8a:	fba6 6707 	umull	r6, r7, r6, r7
    4d8e:	1934      	adds	r4, r6, r4
		for (i = 0; i <= k; ++i) {
    4d90:	f10e 0e01 	add.w	lr, lr, #1
    4d94:	417d      	adcs	r5, r7
    4d96:	fa4f f68e 	sxtb.w	r6, lr
    4d9a:	f04f 0b00 	mov.w	fp, #0
    4d9e:	bf28      	it	cs
    4da0:	f04f 0b01 	movcs.w	fp, #1
    4da4:	454e      	cmp	r6, r9
	*r2 += (r01 < p);
    4da6:	44d8      	add	r8, fp
		for (i = 0; i <= k; ++i) {
    4da8:	ddeb      	ble.n	4d82 <uECC_vli_mult+0x4c>
		result[k] = r0;
    4daa:	f840 402c 	str.w	r4, [r0, ip, lsl #2]
	*r1 = r01 >> uECC_WORD_BITS;
    4dae:	462c      	mov	r4, r5
    4db0:	f10c 0c01 	add.w	ip, ip, #1
	*r2 += (r01 < p);
    4db4:	4645      	mov	r5, r8
    4db6:	e7c4      	b.n	4d42 <uECC_vli_mult+0xc>
		for (i = (k + 1) - num_words; i < num_words; ++i) {
    4db8:	3601      	adds	r6, #1
    4dba:	46a9      	mov	r9, r5
    4dbc:	b276      	sxtb	r6, r6
    4dbe:	eb02 0a8e 	add.w	sl, r2, lr, lsl #2
    4dc2:	2500      	movs	r5, #0
    4dc4:	b277      	sxtb	r7, r6
    4dc6:	42bb      	cmp	r3, r7
    4dc8:	dc05      	bgt.n	4dd6 <uECC_vli_mult+0xa0>
		result[k] = r0;
    4dca:	f840 402e 	str.w	r4, [r0, lr, lsl #2]
	for (k = num_words; k < num_words * 2 - 1; ++k) {
    4dce:	f108 0801 	add.w	r8, r8, #1
		result[k] = r0;
    4dd2:	464c      	mov	r4, r9
    4dd4:	e7c0      	b.n	4d58 <uECC_vli_mult+0x22>
			muladd(left[i], right[k - i], &r0, &r1, &r2);
    4dd6:	f06f 0703 	mvn.w	r7, #3
    4dda:	4377      	muls	r7, r6
	uECC_dword_t p = (uECC_dword_t)a * b;
    4ddc:	f851 c026 	ldr.w	ip, [r1, r6, lsl #2]
    4de0:	f85a 7007 	ldr.w	r7, [sl, r7]
    4de4:	fba7 7c0c 	umull	r7, ip, r7, ip
    4de8:	193c      	adds	r4, r7, r4
    4dea:	eb5c 0909 	adcs.w	r9, ip, r9
    4dee:	f04f 0b00 	mov.w	fp, #0
    4df2:	bf28      	it	cs
    4df4:	f04f 0b01 	movcs.w	fp, #1
	*r2 += (r01 < p);
    4df8:	445d      	add	r5, fp
		for (i = (k + 1) - num_words; i < num_words; ++i) {
    4dfa:	3601      	adds	r6, #1
    4dfc:	e7e2      	b.n	4dc4 <uECC_vli_mult+0x8e>

00004dfe <uECC_vli_clear>:
	for (i = 0; i < num_words; ++i) {
    4dfe:	2300      	movs	r3, #0
{
    4e00:	b510      	push	{r4, lr}
		 vli[i] = 0;
    4e02:	461c      	mov	r4, r3
	for (i = 0; i < num_words; ++i) {
    4e04:	b25a      	sxtb	r2, r3
    4e06:	4291      	cmp	r1, r2
    4e08:	dc00      	bgt.n	4e0c <uECC_vli_clear+0xe>
}
    4e0a:	bd10      	pop	{r4, pc}
		 vli[i] = 0;
    4e0c:	f840 4023 	str.w	r4, [r0, r3, lsl #2]
	for (i = 0; i < num_words; ++i) {
    4e10:	3301      	adds	r3, #1
    4e12:	e7f7      	b.n	4e04 <uECC_vli_clear+0x6>

00004e14 <uECC_vli_isZero>:
{
    4e14:	b510      	push	{r4, lr}
	for (i = 0; i < num_words; ++i) {
    4e16:	2300      	movs	r3, #0
	uECC_word_t bits = 0;
    4e18:	461a      	mov	r2, r3
	for (i = 0; i < num_words; ++i) {
    4e1a:	b25c      	sxtb	r4, r3
    4e1c:	42a1      	cmp	r1, r4
    4e1e:	dc03      	bgt.n	4e28 <uECC_vli_isZero+0x14>
}
    4e20:	fab2 f082 	clz	r0, r2
    4e24:	0940      	lsrs	r0, r0, #5
    4e26:	bd10      	pop	{r4, pc}
		bits |= vli[i];
    4e28:	f850 4023 	ldr.w	r4, [r0, r3, lsl #2]
    4e2c:	3301      	adds	r3, #1
    4e2e:	4322      	orrs	r2, r4
	for (i = 0; i < num_words; ++i) {
    4e30:	e7f3      	b.n	4e1a <uECC_vli_isZero+0x6>

00004e32 <uECC_vli_testBit>:
	return (vli[bit >> uECC_WORD_BITS_SHIFT] &
    4e32:	114a      	asrs	r2, r1, #5
		((uECC_word_t)1 << (bit & uECC_WORD_BITS_MASK)));
    4e34:	2301      	movs	r3, #1
	return (vli[bit >> uECC_WORD_BITS_SHIFT] &
    4e36:	f850 0022 	ldr.w	r0, [r0, r2, lsl #2]
		((uECC_word_t)1 << (bit & uECC_WORD_BITS_MASK)));
    4e3a:	f001 011f 	and.w	r1, r1, #31
    4e3e:	fa03 f101 	lsl.w	r1, r3, r1
}
    4e42:	4008      	ands	r0, r1
    4e44:	4770      	bx	lr

00004e46 <uECC_vli_numBits>:
	for (i = max_words - 1; i >= 0 && vli[i] == 0; --i) {
    4e46:	3901      	subs	r1, #1
{
    4e48:	b510      	push	{r4, lr}
    4e4a:	4602      	mov	r2, r0
    4e4c:	b249      	sxtb	r1, r1
	for (i = max_words - 1; i >= 0 && vli[i] == 0; --i) {
    4e4e:	1d04      	adds	r4, r0, #4
    4e50:	0608      	lsls	r0, r1, #24
    4e52:	b2cb      	uxtb	r3, r1
    4e54:	d404      	bmi.n	4e60 <uECC_vli_numBits+0x1a>
    4e56:	3901      	subs	r1, #1
    4e58:	f854 0021 	ldr.w	r0, [r4, r1, lsl #2]
    4e5c:	2800      	cmp	r0, #0
    4e5e:	d0f7      	beq.n	4e50 <uECC_vli_numBits+0xa>
	return (i + 1);
    4e60:	3301      	adds	r3, #1
    4e62:	b258      	sxtb	r0, r3
	if (num_digits == 0) {
    4e64:	b150      	cbz	r0, 4e7c <uECC_vli_numBits+0x36>
	digit = vli[num_digits - 1];
    4e66:	f100 4380 	add.w	r3, r0, #1073741824	; 0x40000000
    4e6a:	3b01      	subs	r3, #1
    4e6c:	f852 2023 	ldr.w	r2, [r2, r3, lsl #2]
	for (i = 0; digit; ++i) {
    4e70:	2300      	movs	r3, #0
    4e72:	b922      	cbnz	r2, 4e7e <uECC_vli_numBits+0x38>
	return (((bitcount_t)(num_digits - 1) << uECC_WORD_BITS_SHIFT) + i);
    4e74:	3801      	subs	r0, #1
    4e76:	eb03 1040 	add.w	r0, r3, r0, lsl #5
    4e7a:	b200      	sxth	r0, r0
}
    4e7c:	bd10      	pop	{r4, pc}
		digit >>= 1;
    4e7e:	0852      	lsrs	r2, r2, #1
	for (i = 0; digit; ++i) {
    4e80:	3301      	adds	r3, #1
    4e82:	e7f6      	b.n	4e72 <uECC_vli_numBits+0x2c>

00004e84 <uECC_vli_set>:
{
    4e84:	b510      	push	{r4, lr}
	for (i = 0; i < num_words; ++i) {
    4e86:	2300      	movs	r3, #0
    4e88:	b25c      	sxtb	r4, r3
    4e8a:	42a2      	cmp	r2, r4
    4e8c:	dc00      	bgt.n	4e90 <uECC_vli_set+0xc>
}
    4e8e:	bd10      	pop	{r4, pc}
		dest[i] = src[i];
    4e90:	f851 4023 	ldr.w	r4, [r1, r3, lsl #2]
    4e94:	f840 4023 	str.w	r4, [r0, r3, lsl #2]
	for (i = 0; i < num_words; ++i) {
    4e98:	3301      	adds	r3, #1
    4e9a:	e7f5      	b.n	4e88 <uECC_vli_set+0x4>

00004e9c <uECC_vli_cmp_unsafe>:
{
    4e9c:	b510      	push	{r4, lr}
	for (i = num_words - 1; i >= 0; --i) {
    4e9e:	3a01      	subs	r2, #1
    4ea0:	b252      	sxtb	r2, r2
    4ea2:	0613      	lsls	r3, r2, #24
    4ea4:	d501      	bpl.n	4eaa <uECC_vli_cmp_unsafe+0xe>
	return 0;
    4ea6:	2000      	movs	r0, #0
}
    4ea8:	bd10      	pop	{r4, pc}
		if (left[i] > right[i]) {
    4eaa:	f850 4022 	ldr.w	r4, [r0, r2, lsl #2]
    4eae:	f851 3022 	ldr.w	r3, [r1, r2, lsl #2]
    4eb2:	429c      	cmp	r4, r3
    4eb4:	d805      	bhi.n	4ec2 <uECC_vli_cmp_unsafe+0x26>
		} else if (left[i] < right[i]) {
    4eb6:	f102 32ff 	add.w	r2, r2, #4294967295
    4eba:	d2f2      	bcs.n	4ea2 <uECC_vli_cmp_unsafe+0x6>
			return -1;
    4ebc:	f04f 30ff 	mov.w	r0, #4294967295
    4ec0:	e7f2      	b.n	4ea8 <uECC_vli_cmp_unsafe+0xc>
			return 1;
    4ec2:	2001      	movs	r0, #1
    4ec4:	e7f0      	b.n	4ea8 <uECC_vli_cmp_unsafe+0xc>

00004ec6 <uECC_vli_equal>:
{
    4ec6:	b530      	push	{r4, r5, lr}
	for (i = num_words - 1; i >= 0; --i) {
    4ec8:	3a01      	subs	r2, #1
    4eca:	b252      	sxtb	r2, r2
	uECC_word_t diff = 0;
    4ecc:	2300      	movs	r3, #0
	for (i = num_words - 1; i >= 0; --i) {
    4ece:	0614      	lsls	r4, r2, #24
    4ed0:	d503      	bpl.n	4eda <uECC_vli_equal+0x14>
}
    4ed2:	1e18      	subs	r0, r3, #0
    4ed4:	bf18      	it	ne
    4ed6:	2001      	movne	r0, #1
    4ed8:	bd30      	pop	{r4, r5, pc}
		diff |= (left[i] ^ right[i]);
    4eda:	f850 4022 	ldr.w	r4, [r0, r2, lsl #2]
    4ede:	f851 5022 	ldr.w	r5, [r1, r2, lsl #2]
    4ee2:	406c      	eors	r4, r5
    4ee4:	4323      	orrs	r3, r4
	for (i = num_words - 1; i >= 0; --i) {
    4ee6:	3a01      	subs	r2, #1
    4ee8:	e7f1      	b.n	4ece <uECC_vli_equal+0x8>

00004eea <uECC_vli_sub>:
{
    4eea:	b5f0      	push	{r4, r5, r6, r7, lr}
	for (i = 0; i < num_words; ++i) {
    4eec:	2400      	movs	r4, #0
{
    4eee:	4606      	mov	r6, r0
    4ef0:	469c      	mov	ip, r3
	uECC_word_t borrow = 0;
    4ef2:	4620      	mov	r0, r4
	for (i = 0; i < num_words; ++i) {
    4ef4:	b265      	sxtb	r5, r4
    4ef6:	4565      	cmp	r5, ip
    4ef8:	db00      	blt.n	4efc <uECC_vli_sub+0x12>
}
    4efa:	bdf0      	pop	{r4, r5, r6, r7, pc}
		uECC_word_t diff = left[i] - right[i] - borrow;
    4efc:	f851 7024 	ldr.w	r7, [r1, r4, lsl #2]
    4f00:	f852 3024 	ldr.w	r3, [r2, r4, lsl #2]
    4f04:	1a3d      	subs	r5, r7, r0
    4f06:	1aed      	subs	r5, r5, r3
	return (p_true*(cond)) | (p_false*(!cond));
    4f08:	42af      	cmp	r7, r5
    4f0a:	f000 0001 	and.w	r0, r0, #1
    4f0e:	bf18      	it	ne
    4f10:	2000      	movne	r0, #0
		result[i] = diff;
    4f12:	f846 5024 	str.w	r5, [r6, r4, lsl #2]
	return (p_true*(cond)) | (p_false*(!cond));
    4f16:	bf38      	it	cc
    4f18:	f040 0001 	orrcc.w	r0, r0, #1
	for (i = 0; i < num_words; ++i) {
    4f1c:	3401      	adds	r4, #1
    4f1e:	e7e9      	b.n	4ef4 <uECC_vli_sub+0xa>

00004f20 <uECC_vli_modAdd>:
{
    4f20:	b570      	push	{r4, r5, r6, lr}
    4f22:	f99d 6010 	ldrsb.w	r6, [sp, #16]
    4f26:	461d      	mov	r5, r3
	uECC_word_t carry = uECC_vli_add(result, left, right, num_words);
    4f28:	4633      	mov	r3, r6
{
    4f2a:	4604      	mov	r4, r0
	uECC_word_t carry = uECC_vli_add(result, left, right, num_words);
    4f2c:	f7ff fec0 	bl	4cb0 <uECC_vli_add>
	if (carry || uECC_vli_cmp_unsafe(mod, result, num_words) != 1) {
    4f30:	b930      	cbnz	r0, 4f40 <uECC_vli_modAdd+0x20>
    4f32:	4632      	mov	r2, r6
    4f34:	4621      	mov	r1, r4
    4f36:	4628      	mov	r0, r5
    4f38:	f7ff ffb0 	bl	4e9c <uECC_vli_cmp_unsafe>
    4f3c:	2801      	cmp	r0, #1
    4f3e:	d007      	beq.n	4f50 <uECC_vli_modAdd+0x30>
		uECC_vli_sub(result, result, mod, num_words);
    4f40:	4633      	mov	r3, r6
    4f42:	462a      	mov	r2, r5
    4f44:	4621      	mov	r1, r4
    4f46:	4620      	mov	r0, r4
}
    4f48:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		uECC_vli_sub(result, result, mod, num_words);
    4f4c:	f7ff bfcd 	b.w	4eea <uECC_vli_sub>
}
    4f50:	bd70      	pop	{r4, r5, r6, pc}

00004f52 <uECC_vli_modSub>:
{
    4f52:	b570      	push	{r4, r5, r6, lr}
    4f54:	f99d 6010 	ldrsb.w	r6, [sp, #16]
    4f58:	461d      	mov	r5, r3
	uECC_word_t l_borrow = uECC_vli_sub(result, left, right, num_words);
    4f5a:	4633      	mov	r3, r6
{
    4f5c:	4604      	mov	r4, r0
	uECC_word_t l_borrow = uECC_vli_sub(result, left, right, num_words);
    4f5e:	f7ff ffc4 	bl	4eea <uECC_vli_sub>
	if (l_borrow) {
    4f62:	b138      	cbz	r0, 4f74 <uECC_vli_modSub+0x22>
		uECC_vli_add(result, result, mod, num_words);
    4f64:	4633      	mov	r3, r6
    4f66:	462a      	mov	r2, r5
    4f68:	4621      	mov	r1, r4
    4f6a:	4620      	mov	r0, r4
}
    4f6c:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		uECC_vli_add(result, result, mod, num_words);
    4f70:	f7ff be9e 	b.w	4cb0 <uECC_vli_add>
}
    4f74:	bd70      	pop	{r4, r5, r6, pc}

00004f76 <uECC_vli_mmod>:
{
    4f76:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    4f7a:	b0a5      	sub	sp, #148	; 0x94
    4f7c:	461d      	mov	r5, r3
	uECC_word_t *v[2] = {tmp, product};
    4f7e:	ab14      	add	r3, sp, #80	; 0x50
    4f80:	e9cd 3102 	strd	r3, r1, [sp, #8]
{
    4f84:	4680      	mov	r8, r0
			   uECC_vli_numBits(mod, num_words);
    4f86:	4629      	mov	r1, r5
    4f88:	4610      	mov	r0, r2
{
    4f8a:	4617      	mov	r7, r2
			   uECC_vli_numBits(mod, num_words);
    4f8c:	f7ff ff5b 	bl	4e46 <uECC_vli_numBits>
	bitcount_t shift = (num_words * 2 * uECC_WORD_BITS) -
    4f90:	ebc0 1485 	rsb	r4, r0, r5, lsl #6
    4f94:	b224      	sxth	r4, r4
	wordcount_t word_shift = shift / uECC_WORD_BITS;
    4f96:	2c00      	cmp	r4, #0
    4f98:	4621      	mov	r1, r4
    4f9a:	bfb8      	it	lt
    4f9c:	f104 011f 	addlt.w	r1, r4, #31
	wordcount_t bit_shift = shift % uECC_WORD_BITS;
    4fa0:	4263      	negs	r3, r4
    4fa2:	f003 031f 	and.w	r3, r3, #31
	wordcount_t word_shift = shift / uECC_WORD_BITS;
    4fa6:	f341 1147 	sbfx	r1, r1, #5, #8
	wordcount_t bit_shift = shift % uECC_WORD_BITS;
    4faa:	f004 061f 	and.w	r6, r4, #31
	uECC_vli_clear(mod_multiple, word_shift);
    4fae:	a804      	add	r0, sp, #16
	wordcount_t bit_shift = shift % uECC_WORD_BITS;
    4fb0:	bf58      	it	pl
    4fb2:	425e      	negpl	r6, r3
	uECC_vli_clear(mod_multiple, word_shift);
    4fb4:	f7ff ff23 	bl	4dfe <uECC_vli_clear>
	if (bit_shift > 0) {
    4fb8:	2e00      	cmp	r6, #0
    4fba:	b208      	sxth	r0, r1
    4fbc:	dd2b      	ble.n	5016 <uECC_vli_mmod+0xa0>
    4fbe:	ab04      	add	r3, sp, #16
	uECC_word_t carry = 0;
    4fc0:	2200      	movs	r2, #0
    4fc2:	eb03 0080 	add.w	r0, r3, r0, lsl #2
			carry = mod[index] >> (uECC_WORD_BITS - bit_shift);
    4fc6:	f1c6 0e20 	rsb	lr, r6, #32
		for(index = 0; index < (uECC_word_t)num_words; ++index) {
    4fca:	4613      	mov	r3, r2
    4fcc:	429d      	cmp	r5, r3
    4fce:	d817      	bhi.n	5000 <uECC_vli_mmod+0x8a>
		for (i = 0; i < num_words * 2; ++i) {
    4fd0:	006b      	lsls	r3, r5, #1
    4fd2:	9301      	str	r3, [sp, #4]
		uECC_vli_rshift1(mod_multiple + num_words, num_words);
    4fd4:	ab04      	add	r3, sp, #16
    4fd6:	eb03 0985 	add.w	r9, r3, r5, lsl #2
		mod_multiple[num_words - 1] |= mod_multiple[num_words] <<
    4fda:	1e6f      	subs	r7, r5, #1
    4fdc:	ab24      	add	r3, sp, #144	; 0x90
		uECC_vli_rshift1(mod_multiple + num_words, num_words);
    4fde:	2601      	movs	r6, #1
		mod_multiple[num_words - 1] |= mod_multiple[num_words] <<
    4fe0:	eb03 0787 	add.w	r7, r3, r7, lsl #2
	for (index = 1; shift >= 0; --shift) {
    4fe4:	2c00      	cmp	r4, #0
    4fe6:	da54      	bge.n	5092 <uECC_vli_mmod+0x11c>
	uECC_vli_set(result, v[index], num_words);
    4fe8:	ab24      	add	r3, sp, #144	; 0x90
    4fea:	eb03 0686 	add.w	r6, r3, r6, lsl #2
    4fee:	462a      	mov	r2, r5
    4ff0:	f856 1c88 	ldr.w	r1, [r6, #-136]
    4ff4:	4640      	mov	r0, r8
    4ff6:	f7ff ff45 	bl	4e84 <uECC_vli_set>
}
    4ffa:	b025      	add	sp, #148	; 0x94
    4ffc:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
			mod_multiple[word_shift + index] = (mod[index] << bit_shift) | carry;
    5000:	f857 c023 	ldr.w	ip, [r7, r3, lsl #2]
    5004:	fa0c f106 	lsl.w	r1, ip, r6
    5008:	430a      	orrs	r2, r1
    500a:	f840 2b04 	str.w	r2, [r0], #4
		for(index = 0; index < (uECC_word_t)num_words; ++index) {
    500e:	3301      	adds	r3, #1
			carry = mod[index] >> (uECC_WORD_BITS - bit_shift);
    5010:	fa2c f20e 	lsr.w	r2, ip, lr
		for(index = 0; index < (uECC_word_t)num_words; ++index) {
    5014:	e7da      	b.n	4fcc <uECC_vli_mmod+0x56>
		uECC_vli_set(mod_multiple + word_shift, mod, num_words);
    5016:	ab04      	add	r3, sp, #16
    5018:	462a      	mov	r2, r5
    501a:	4639      	mov	r1, r7
    501c:	eb03 0080 	add.w	r0, r3, r0, lsl #2
    5020:	f7ff ff30 	bl	4e84 <uECC_vli_set>
    5024:	e7d4      	b.n	4fd0 <uECC_vli_mmod+0x5a>
			uECC_word_t diff = v[index][i] - mod_multiple[i] - borrow;
    5026:	fa0f fe82 	sxth.w	lr, r2
    502a:	f85a 3c88 	ldr.w	r3, [sl, #-136]
    502e:	f853 b02e 	ldr.w	fp, [r3, lr, lsl #2]
    5032:	ab24      	add	r3, sp, #144	; 0x90
    5034:	eb03 0282 	add.w	r2, r3, r2, lsl #2
    5038:	3001      	adds	r0, #1
    503a:	f852 3c80 	ldr.w	r3, [r2, #-128]
    503e:	440b      	add	r3, r1
    5040:	ebbb 0303 	subs.w	r3, fp, r3
    5044:	bf34      	ite	cc
    5046:	2201      	movcc	r2, #1
    5048:	2200      	movcs	r2, #0
			if (diff != v[index][i]) {
    504a:	459b      	cmp	fp, r3
				borrow = (diff > v[index][i]);
    504c:	bf18      	it	ne
    504e:	4611      	movne	r1, r2
			v[1 - index][i] = diff;
    5050:	f85c 2c88 	ldr.w	r2, [ip, #-136]
    5054:	f842 302e 	str.w	r3, [r2, lr, lsl #2]
		for (i = 0; i < num_words * 2; ++i) {
    5058:	9b01      	ldr	r3, [sp, #4]
    505a:	b242      	sxtb	r2, r0
    505c:	429a      	cmp	r2, r3
    505e:	dbe2      	blt.n	5026 <uECC_vli_mmod+0xb0>
		index = !(index ^ borrow);
    5060:	1a73      	subs	r3, r6, r1
    5062:	425e      	negs	r6, r3
		uECC_vli_rshift1(mod_multiple, num_words);
    5064:	4629      	mov	r1, r5
    5066:	a804      	add	r0, sp, #16
		index = !(index ^ borrow);
    5068:	415e      	adcs	r6, r3
		uECC_vli_rshift1(mod_multiple, num_words);
    506a:	f7ff fe3b 	bl	4ce4 <uECC_vli_rshift1>
		mod_multiple[num_words - 1] |= mod_multiple[num_words] <<
    506e:	ab24      	add	r3, sp, #144	; 0x90
    5070:	eb03 0385 	add.w	r3, r3, r5, lsl #2
		uECC_vli_rshift1(mod_multiple + num_words, num_words);
    5074:	4629      	mov	r1, r5
		mod_multiple[num_words - 1] |= mod_multiple[num_words] <<
    5076:	f853 2c80 	ldr.w	r2, [r3, #-128]
    507a:	f857 3c80 	ldr.w	r3, [r7, #-128]
    507e:	ea43 73c2 	orr.w	r3, r3, r2, lsl #31
    5082:	f847 3c80 	str.w	r3, [r7, #-128]
		uECC_vli_rshift1(mod_multiple + num_words, num_words);
    5086:	4648      	mov	r0, r9
    5088:	3c01      	subs	r4, #1
    508a:	f7ff fe2b 	bl	4ce4 <uECC_vli_rshift1>
	for (index = 1; shift >= 0; --shift) {
    508e:	b224      	sxth	r4, r4
    5090:	e7a8      	b.n	4fe4 <uECC_vli_mmod+0x6e>
			uECC_word_t diff = v[index][i] - mod_multiple[i] - borrow;
    5092:	ab24      	add	r3, sp, #144	; 0x90
    5094:	2000      	movs	r0, #0
			v[1 - index][i] = diff;
    5096:	f1c6 0c01 	rsb	ip, r6, #1
		uECC_word_t borrow = 0;
    509a:	4601      	mov	r1, r0
			uECC_word_t diff = v[index][i] - mod_multiple[i] - borrow;
    509c:	eb03 0a86 	add.w	sl, r3, r6, lsl #2
			v[1 - index][i] = diff;
    50a0:	eb03 0c8c 	add.w	ip, r3, ip, lsl #2
    50a4:	e7d8      	b.n	5058 <uECC_vli_mmod+0xe2>

000050a6 <uECC_vli_modMult>:
{
    50a6:	b530      	push	{r4, r5, lr}
    50a8:	b091      	sub	sp, #68	; 0x44
    50aa:	4604      	mov	r4, r0
    50ac:	461d      	mov	r5, r3
	uECC_vli_mult(product, left, right, num_words);
    50ae:	4668      	mov	r0, sp
    50b0:	f99d 3050 	ldrsb.w	r3, [sp, #80]	; 0x50
    50b4:	f7ff fe3f 	bl	4d36 <uECC_vli_mult>
	uECC_vli_mmod(result, product, mod, num_words);
    50b8:	462a      	mov	r2, r5
    50ba:	4669      	mov	r1, sp
    50bc:	4620      	mov	r0, r4
    50be:	f7ff ff5a 	bl	4f76 <uECC_vli_mmod>
}
    50c2:	b011      	add	sp, #68	; 0x44
    50c4:	bd30      	pop	{r4, r5, pc}

000050c6 <uECC_vli_modMult_fast>:
{
    50c6:	b530      	push	{r4, r5, lr}
    50c8:	461c      	mov	r4, r3
    50ca:	b091      	sub	sp, #68	; 0x44
    50cc:	4605      	mov	r5, r0
	uECC_vli_mult(product, left, right, curve->num_words);
    50ce:	f993 3000 	ldrsb.w	r3, [r3]
    50d2:	4668      	mov	r0, sp
    50d4:	f7ff fe2f 	bl	4d36 <uECC_vli_mult>
	curve->mmod_fast(result, product);
    50d8:	f8d4 30ac 	ldr.w	r3, [r4, #172]	; 0xac
    50dc:	4669      	mov	r1, sp
    50de:	4628      	mov	r0, r5
    50e0:	4798      	blx	r3
}
    50e2:	b011      	add	sp, #68	; 0x44
    50e4:	bd30      	pop	{r4, r5, pc}

000050e6 <uECC_vli_modSquare_fast>:
{
    50e6:	4613      	mov	r3, r2
	uECC_vli_modMult_fast(result, left, left, curve);
    50e8:	460a      	mov	r2, r1
    50ea:	f7ff bfec 	b.w	50c6 <uECC_vli_modMult_fast>

000050ee <double_jacobian_default>:
{
    50ee:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
	wordcount_t num_words = curve->num_words;
    50f2:	f993 6000 	ldrsb.w	r6, [r3]
{
    50f6:	b092      	sub	sp, #72	; 0x48
    50f8:	4604      	mov	r4, r0
    50fa:	4689      	mov	r9, r1
	if (uECC_vli_isZero(Z1, num_words)) {
    50fc:	4610      	mov	r0, r2
    50fe:	4631      	mov	r1, r6
{
    5100:	4615      	mov	r5, r2
    5102:	461f      	mov	r7, r3
	if (uECC_vli_isZero(Z1, num_words)) {
    5104:	f7ff fe86 	bl	4e14 <uECC_vli_isZero>
    5108:	2800      	cmp	r0, #0
    510a:	f040 8091 	bne.w	5230 <double_jacobian_default+0x142>
	uECC_vli_modSquare_fast(t4, Y1, curve);   /* t4 = y1^2 */
    510e:	463a      	mov	r2, r7
    5110:	4649      	mov	r1, r9
    5112:	a802      	add	r0, sp, #8
    5114:	f7ff ffe7 	bl	50e6 <uECC_vli_modSquare_fast>
	uECC_vli_modMult_fast(t5, X1, t4, curve); /* t5 = x1*y1^2 = A */
    5118:	463b      	mov	r3, r7
    511a:	aa02      	add	r2, sp, #8
    511c:	4621      	mov	r1, r4
    511e:	a80a      	add	r0, sp, #40	; 0x28
    5120:	f7ff ffd1 	bl	50c6 <uECC_vli_modMult_fast>
	uECC_vli_modSquare_fast(t4, t4, curve);   /* t4 = y1^4 */
    5124:	a902      	add	r1, sp, #8
    5126:	4608      	mov	r0, r1
    5128:	463a      	mov	r2, r7
    512a:	f7ff ffdc 	bl	50e6 <uECC_vli_modSquare_fast>
	uECC_vli_modMult_fast(Y1, Y1, Z1, curve); /* t2 = y1*z1 = z3 */
    512e:	463b      	mov	r3, r7
    5130:	462a      	mov	r2, r5
    5132:	4649      	mov	r1, r9
    5134:	4648      	mov	r0, r9
    5136:	f7ff ffc6 	bl	50c6 <uECC_vli_modMult_fast>
	uECC_vli_modAdd(X1, X1, Z1, curve->p, num_words); /* t1 = x1 + z1^2 */
    513a:	f107 0804 	add.w	r8, r7, #4
	uECC_vli_modSquare_fast(Z1, Z1, curve);   /* t3 = z1^2 */
    513e:	463a      	mov	r2, r7
    5140:	4629      	mov	r1, r5
    5142:	4628      	mov	r0, r5
    5144:	f7ff ffcf 	bl	50e6 <uECC_vli_modSquare_fast>
	uECC_vli_modAdd(X1, X1, Z1, curve->p, num_words); /* t1 = x1 + z1^2 */
    5148:	4643      	mov	r3, r8
    514a:	462a      	mov	r2, r5
    514c:	4621      	mov	r1, r4
    514e:	4620      	mov	r0, r4
    5150:	9600      	str	r6, [sp, #0]
    5152:	f7ff fee5 	bl	4f20 <uECC_vli_modAdd>
	uECC_vli_modAdd(Z1, Z1, Z1, curve->p, num_words); /* t3 = 2*z1^2 */
    5156:	4643      	mov	r3, r8
    5158:	462a      	mov	r2, r5
    515a:	4629      	mov	r1, r5
    515c:	4628      	mov	r0, r5
    515e:	9600      	str	r6, [sp, #0]
    5160:	f7ff fede 	bl	4f20 <uECC_vli_modAdd>
	uECC_vli_modSub(Z1, X1, Z1, curve->p, num_words); /* t3 = x1 - z1^2 */
    5164:	4643      	mov	r3, r8
    5166:	462a      	mov	r2, r5
    5168:	4621      	mov	r1, r4
    516a:	4628      	mov	r0, r5
    516c:	9600      	str	r6, [sp, #0]
    516e:	f7ff fef0 	bl	4f52 <uECC_vli_modSub>
	uECC_vli_modMult_fast(X1, X1, Z1, curve); /* t1 = x1^2 - z1^4 */
    5172:	463b      	mov	r3, r7
    5174:	462a      	mov	r2, r5
    5176:	4621      	mov	r1, r4
    5178:	4620      	mov	r0, r4
    517a:	f7ff ffa4 	bl	50c6 <uECC_vli_modMult_fast>
	uECC_vli_modAdd(Z1, X1, X1, curve->p, num_words); /* t3 = 2*(x1^2 - z1^4) */
    517e:	4643      	mov	r3, r8
    5180:	4622      	mov	r2, r4
    5182:	4621      	mov	r1, r4
    5184:	4628      	mov	r0, r5
    5186:	9600      	str	r6, [sp, #0]
    5188:	f7ff feca 	bl	4f20 <uECC_vli_modAdd>
	uECC_vli_modAdd(X1, X1, Z1, curve->p, num_words); /* t1 = 3*(x1^2 - z1^4) */
    518c:	4643      	mov	r3, r8
    518e:	9600      	str	r6, [sp, #0]
    5190:	462a      	mov	r2, r5
    5192:	4621      	mov	r1, r4
    5194:	4620      	mov	r0, r4
    5196:	f7ff fec3 	bl	4f20 <uECC_vli_modAdd>
	return (vli[bit >> uECC_WORD_BITS_SHIFT] &
    519a:	6823      	ldr	r3, [r4, #0]
	if (uECC_vli_testBit(X1, 0)) {
    519c:	07db      	lsls	r3, r3, #31
    519e:	d54a      	bpl.n	5236 <double_jacobian_default+0x148>
		uECC_word_t l_carry = uECC_vli_add(X1, X1, curve->p, num_words);
    51a0:	4633      	mov	r3, r6
    51a2:	4642      	mov	r2, r8
    51a4:	4621      	mov	r1, r4
    51a6:	4620      	mov	r0, r4
    51a8:	f7ff fd82 	bl	4cb0 <uECC_vli_add>
		uECC_vli_rshift1(X1, num_words);
    51ac:	4631      	mov	r1, r6
		uECC_word_t l_carry = uECC_vli_add(X1, X1, curve->p, num_words);
    51ae:	4682      	mov	sl, r0
		uECC_vli_rshift1(X1, num_words);
    51b0:	4620      	mov	r0, r4
    51b2:	f7ff fd97 	bl	4ce4 <uECC_vli_rshift1>
		X1[num_words - 1] |= l_carry << (uECC_WORD_BITS - 1);
    51b6:	f106 4380 	add.w	r3, r6, #1073741824	; 0x40000000
    51ba:	3b01      	subs	r3, #1
    51bc:	f854 2023 	ldr.w	r2, [r4, r3, lsl #2]
    51c0:	ea42 72ca 	orr.w	r2, r2, sl, lsl #31
    51c4:	f844 2023 	str.w	r2, [r4, r3, lsl #2]
	uECC_vli_modSquare_fast(Z1, X1, curve); /* t3 = B^2 */
    51c8:	463a      	mov	r2, r7
    51ca:	4621      	mov	r1, r4
    51cc:	4628      	mov	r0, r5
    51ce:	f7ff ff8a 	bl	50e6 <uECC_vli_modSquare_fast>
	uECC_vli_modSub(Z1, Z1, t5, curve->p, num_words); /* t3 = B^2 - A */
    51d2:	4643      	mov	r3, r8
    51d4:	aa0a      	add	r2, sp, #40	; 0x28
    51d6:	4629      	mov	r1, r5
    51d8:	4628      	mov	r0, r5
    51da:	9600      	str	r6, [sp, #0]
    51dc:	f7ff feb9 	bl	4f52 <uECC_vli_modSub>
	uECC_vli_modSub(Z1, Z1, t5, curve->p, num_words); /* t3 = B^2 - 2A = x3 */
    51e0:	4643      	mov	r3, r8
    51e2:	aa0a      	add	r2, sp, #40	; 0x28
    51e4:	4629      	mov	r1, r5
    51e6:	4628      	mov	r0, r5
    51e8:	9600      	str	r6, [sp, #0]
    51ea:	f7ff feb2 	bl	4f52 <uECC_vli_modSub>
	uECC_vli_modSub(t5, t5, Z1, curve->p, num_words); /* t5 = A - x3 */
    51ee:	a90a      	add	r1, sp, #40	; 0x28
    51f0:	4608      	mov	r0, r1
    51f2:	4643      	mov	r3, r8
    51f4:	462a      	mov	r2, r5
    51f6:	9600      	str	r6, [sp, #0]
    51f8:	f7ff feab 	bl	4f52 <uECC_vli_modSub>
	uECC_vli_modMult_fast(X1, X1, t5, curve); /* t1 = B * (A - x3) */
    51fc:	463b      	mov	r3, r7
    51fe:	aa0a      	add	r2, sp, #40	; 0x28
    5200:	4621      	mov	r1, r4
    5202:	4620      	mov	r0, r4
    5204:	f7ff ff5f 	bl	50c6 <uECC_vli_modMult_fast>
	uECC_vli_modSub(t4, X1, t4, curve->p, num_words);
    5208:	aa02      	add	r2, sp, #8
    520a:	4643      	mov	r3, r8
    520c:	4610      	mov	r0, r2
    520e:	4621      	mov	r1, r4
    5210:	9600      	str	r6, [sp, #0]
    5212:	f7ff fe9e 	bl	4f52 <uECC_vli_modSub>
	uECC_vli_set(X1, Z1, num_words);
    5216:	4632      	mov	r2, r6
    5218:	4629      	mov	r1, r5
    521a:	4620      	mov	r0, r4
    521c:	f7ff fe32 	bl	4e84 <uECC_vli_set>
	uECC_vli_set(Z1, Y1, num_words);
    5220:	4649      	mov	r1, r9
    5222:	4628      	mov	r0, r5
    5224:	f7ff fe2e 	bl	4e84 <uECC_vli_set>
	uECC_vli_set(Y1, t4, num_words);
    5228:	a902      	add	r1, sp, #8
    522a:	4648      	mov	r0, r9
    522c:	f7ff fe2a 	bl	4e84 <uECC_vli_set>
}
    5230:	b012      	add	sp, #72	; 0x48
    5232:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
		uECC_vli_rshift1(X1, num_words);
    5236:	4631      	mov	r1, r6
    5238:	4620      	mov	r0, r4
    523a:	f7ff fd53 	bl	4ce4 <uECC_vli_rshift1>
    523e:	e7c3      	b.n	51c8 <double_jacobian_default+0xda>

00005240 <x_side_default>:
{
    5240:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    5244:	4615      	mov	r5, r2
    5246:	b08a      	sub	sp, #40	; 0x28
    5248:	4604      	mov	r4, r0
    524a:	460e      	mov	r6, r1
	uECC_word_t _3[NUM_ECC_WORDS] = {3}; /* -a = 3 */
    524c:	221c      	movs	r2, #28
    524e:	2100      	movs	r1, #0
    5250:	a803      	add	r0, sp, #12
    5252:	f000 fd36 	bl	5cc2 <memset>
	uECC_vli_modSub(result, result, _3, curve->p, num_words); /* r = x^2 - 3 */
    5256:	1d2f      	adds	r7, r5, #4
	wordcount_t num_words = curve->num_words;
    5258:	f995 8000 	ldrsb.w	r8, [r5]
	uECC_word_t _3[NUM_ECC_WORDS] = {3}; /* -a = 3 */
    525c:	2303      	movs	r3, #3
	uECC_vli_modSquare_fast(result, x, curve); /* r = x^2 */
    525e:	462a      	mov	r2, r5
    5260:	4631      	mov	r1, r6
    5262:	4620      	mov	r0, r4
	uECC_word_t _3[NUM_ECC_WORDS] = {3}; /* -a = 3 */
    5264:	9302      	str	r3, [sp, #8]
	uECC_vli_modSquare_fast(result, x, curve); /* r = x^2 */
    5266:	f7ff ff3e 	bl	50e6 <uECC_vli_modSquare_fast>
	uECC_vli_modSub(result, result, _3, curve->p, num_words); /* r = x^2 - 3 */
    526a:	463b      	mov	r3, r7
    526c:	aa02      	add	r2, sp, #8
    526e:	4621      	mov	r1, r4
    5270:	4620      	mov	r0, r4
    5272:	f8cd 8000 	str.w	r8, [sp]
    5276:	f7ff fe6c 	bl	4f52 <uECC_vli_modSub>
	uECC_vli_modMult_fast(result, result, x, curve); /* r = x^3 - 3x */
    527a:	462b      	mov	r3, r5
    527c:	4632      	mov	r2, r6
    527e:	4621      	mov	r1, r4
    5280:	4620      	mov	r0, r4
    5282:	f7ff ff20 	bl	50c6 <uECC_vli_modMult_fast>
	uECC_vli_modAdd(result, result, curve->b, curve->p, num_words);
    5286:	f8cd 8000 	str.w	r8, [sp]
    528a:	463b      	mov	r3, r7
    528c:	f105 0284 	add.w	r2, r5, #132	; 0x84
    5290:	4621      	mov	r1, r4
    5292:	4620      	mov	r0, r4
    5294:	f7ff fe44 	bl	4f20 <uECC_vli_modAdd>
}
    5298:	b00a      	add	sp, #40	; 0x28
    529a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

0000529e <uECC_vli_modInv>:
{
    529e:	b5f0      	push	{r4, r5, r6, r7, lr}
    52a0:	460f      	mov	r7, r1
    52a2:	b0a1      	sub	sp, #132	; 0x84
    52a4:	4606      	mov	r6, r0
	if (uECC_vli_isZero(input, num_words)) {
    52a6:	4619      	mov	r1, r3
    52a8:	4638      	mov	r0, r7
{
    52aa:	4615      	mov	r5, r2
    52ac:	461c      	mov	r4, r3
	if (uECC_vli_isZero(input, num_words)) {
    52ae:	f7ff fdb1 	bl	4e14 <uECC_vli_isZero>
    52b2:	b128      	cbz	r0, 52c0 <uECC_vli_modInv+0x22>
		uECC_vli_clear(result, num_words);
    52b4:	4630      	mov	r0, r6
}
    52b6:	b021      	add	sp, #132	; 0x84
    52b8:	e8bd 40f0 	ldmia.w	sp!, {r4, r5, r6, r7, lr}
		uECC_vli_clear(result, num_words);
    52bc:	f7ff bd9f 	b.w	4dfe <uECC_vli_clear>
	uECC_vli_set(a, input, num_words);
    52c0:	4622      	mov	r2, r4
    52c2:	4639      	mov	r1, r7
    52c4:	4668      	mov	r0, sp
    52c6:	f7ff fddd 	bl	4e84 <uECC_vli_set>
	uECC_vli_set(b, mod, num_words);
    52ca:	4629      	mov	r1, r5
    52cc:	a808      	add	r0, sp, #32
    52ce:	f7ff fdd9 	bl	4e84 <uECC_vli_set>
	uECC_vli_clear(u, num_words);
    52d2:	a810      	add	r0, sp, #64	; 0x40
    52d4:	4621      	mov	r1, r4
    52d6:	f7ff fd92 	bl	4dfe <uECC_vli_clear>
	u[0] = 1;
    52da:	2301      	movs	r3, #1
	uECC_vli_clear(v, num_words);
    52dc:	a818      	add	r0, sp, #96	; 0x60
	u[0] = 1;
    52de:	9310      	str	r3, [sp, #64]	; 0x40
	uECC_vli_clear(v, num_words);
    52e0:	f7ff fd8d 	bl	4dfe <uECC_vli_clear>
	while ((cmpResult = uECC_vli_cmp_unsafe(a, b, num_words)) != 0) {
    52e4:	4622      	mov	r2, r4
    52e6:	a908      	add	r1, sp, #32
    52e8:	4668      	mov	r0, sp
    52ea:	f7ff fdd7 	bl	4e9c <uECC_vli_cmp_unsafe>
    52ee:	b930      	cbnz	r0, 52fe <uECC_vli_modInv+0x60>
  	uECC_vli_set(result, u, num_words);
    52f0:	4622      	mov	r2, r4
    52f2:	a910      	add	r1, sp, #64	; 0x40
    52f4:	4630      	mov	r0, r6
    52f6:	f7ff fdc5 	bl	4e84 <uECC_vli_set>
}
    52fa:	b021      	add	sp, #132	; 0x84
    52fc:	bdf0      	pop	{r4, r5, r6, r7, pc}
		if (EVEN(a)) {
    52fe:	9b00      	ldr	r3, [sp, #0]
    5300:	07da      	lsls	r2, r3, #31
    5302:	d409      	bmi.n	5318 <uECC_vli_modInv+0x7a>
			uECC_vli_rshift1(a, num_words);
    5304:	4621      	mov	r1, r4
    5306:	4668      	mov	r0, sp
    5308:	f7ff fcec 	bl	4ce4 <uECC_vli_rshift1>
      			vli_modInv_update(u, mod, num_words);
    530c:	4622      	mov	r2, r4
    530e:	4629      	mov	r1, r5
    5310:	a810      	add	r0, sp, #64	; 0x40
      			vli_modInv_update(v, mod, num_words);
    5312:	f7ff fcf4 	bl	4cfe <vli_modInv_update>
    5316:	e7e5      	b.n	52e4 <uECC_vli_modInv+0x46>
    		} else if (EVEN(b)) {
    5318:	9b08      	ldr	r3, [sp, #32]
    531a:	07db      	lsls	r3, r3, #31
    531c:	d407      	bmi.n	532e <uECC_vli_modInv+0x90>
			uECC_vli_rshift1(b, num_words);
    531e:	4621      	mov	r1, r4
    5320:	a808      	add	r0, sp, #32
    5322:	f7ff fcdf 	bl	4ce4 <uECC_vli_rshift1>
      			vli_modInv_update(v, mod, num_words);
    5326:	4622      	mov	r2, r4
    5328:	4629      	mov	r1, r5
    532a:	a818      	add	r0, sp, #96	; 0x60
    532c:	e7f1      	b.n	5312 <uECC_vli_modInv+0x74>
		} else if (cmpResult > 0) {
    532e:	2800      	cmp	r0, #0
			uECC_vli_sub(a, a, b, num_words);
    5330:	4623      	mov	r3, r4
		} else if (cmpResult > 0) {
    5332:	dd1c      	ble.n	536e <uECC_vli_modInv+0xd0>
			uECC_vli_sub(a, a, b, num_words);
    5334:	aa08      	add	r2, sp, #32
    5336:	4669      	mov	r1, sp
    5338:	4668      	mov	r0, sp
    533a:	f7ff fdd6 	bl	4eea <uECC_vli_sub>
			uECC_vli_rshift1(a, num_words);
    533e:	4621      	mov	r1, r4
    5340:	4668      	mov	r0, sp
    5342:	f7ff fccf 	bl	4ce4 <uECC_vli_rshift1>
			if (uECC_vli_cmp_unsafe(u, v, num_words) < 0) {
    5346:	4622      	mov	r2, r4
    5348:	a918      	add	r1, sp, #96	; 0x60
    534a:	a810      	add	r0, sp, #64	; 0x40
    534c:	f7ff fda6 	bl	4e9c <uECC_vli_cmp_unsafe>
    5350:	2800      	cmp	r0, #0
    5352:	da05      	bge.n	5360 <uECC_vli_modInv+0xc2>
        			uECC_vli_add(u, u, mod, num_words);
    5354:	a910      	add	r1, sp, #64	; 0x40
    5356:	4623      	mov	r3, r4
    5358:	462a      	mov	r2, r5
    535a:	4608      	mov	r0, r1
    535c:	f7ff fca8 	bl	4cb0 <uECC_vli_add>
      			uECC_vli_sub(u, u, v, num_words);
    5360:	a910      	add	r1, sp, #64	; 0x40
    5362:	4623      	mov	r3, r4
    5364:	aa18      	add	r2, sp, #96	; 0x60
    5366:	4608      	mov	r0, r1
    5368:	f7ff fdbf 	bl	4eea <uECC_vli_sub>
    536c:	e7ce      	b.n	530c <uECC_vli_modInv+0x6e>
      			uECC_vli_sub(b, b, a, num_words);
    536e:	466a      	mov	r2, sp
    5370:	a808      	add	r0, sp, #32
    5372:	f7ff fdba 	bl	4eea <uECC_vli_sub>
      			uECC_vli_rshift1(b, num_words);
    5376:	4621      	mov	r1, r4
    5378:	a808      	add	r0, sp, #32
    537a:	f7ff fcb3 	bl	4ce4 <uECC_vli_rshift1>
      			if (uECC_vli_cmp_unsafe(v, u, num_words) < 0) {
    537e:	4622      	mov	r2, r4
    5380:	a910      	add	r1, sp, #64	; 0x40
    5382:	a818      	add	r0, sp, #96	; 0x60
    5384:	f7ff fd8a 	bl	4e9c <uECC_vli_cmp_unsafe>
    5388:	2800      	cmp	r0, #0
    538a:	da05      	bge.n	5398 <uECC_vli_modInv+0xfa>
        			uECC_vli_add(v, v, mod, num_words);
    538c:	a918      	add	r1, sp, #96	; 0x60
    538e:	4623      	mov	r3, r4
    5390:	462a      	mov	r2, r5
    5392:	4608      	mov	r0, r1
    5394:	f7ff fc8c 	bl	4cb0 <uECC_vli_add>
      			uECC_vli_sub(v, v, u, num_words);
    5398:	a918      	add	r1, sp, #96	; 0x60
    539a:	4623      	mov	r3, r4
    539c:	aa10      	add	r2, sp, #64	; 0x40
    539e:	4608      	mov	r0, r1
    53a0:	f7ff fda3 	bl	4eea <uECC_vli_sub>
    53a4:	e7bf      	b.n	5326 <uECC_vli_modInv+0x88>

000053a6 <apply_z>:
	return uECC_vli_isZero(point, curve->num_words * 2);
}

void apply_z(uECC_word_t * X1, uECC_word_t * Y1, const uECC_word_t * const Z,
	     uECC_Curve curve)
{
    53a6:	b5f0      	push	{r4, r5, r6, r7, lr}
    53a8:	4615      	mov	r5, r2
    53aa:	b089      	sub	sp, #36	; 0x24
    53ac:	461c      	mov	r4, r3
    53ae:	4607      	mov	r7, r0
    53b0:	460e      	mov	r6, r1
	uECC_word_t t1[NUM_ECC_WORDS];

	uECC_vli_modSquare_fast(t1, Z, curve);    /* z^2 */
    53b2:	461a      	mov	r2, r3
    53b4:	4629      	mov	r1, r5
    53b6:	4668      	mov	r0, sp
    53b8:	f7ff fe95 	bl	50e6 <uECC_vli_modSquare_fast>
	uECC_vli_modMult_fast(X1, X1, t1, curve); /* x1 * z^2 */
    53bc:	4623      	mov	r3, r4
    53be:	466a      	mov	r2, sp
    53c0:	4639      	mov	r1, r7
    53c2:	4638      	mov	r0, r7
    53c4:	f7ff fe7f 	bl	50c6 <uECC_vli_modMult_fast>
	uECC_vli_modMult_fast(t1, t1, Z, curve);  /* z^3 */
    53c8:	4623      	mov	r3, r4
    53ca:	462a      	mov	r2, r5
    53cc:	4669      	mov	r1, sp
    53ce:	4668      	mov	r0, sp
    53d0:	f7ff fe79 	bl	50c6 <uECC_vli_modMult_fast>
	uECC_vli_modMult_fast(Y1, Y1, t1, curve); /* y1 * z^3 */
    53d4:	4623      	mov	r3, r4
    53d6:	466a      	mov	r2, sp
    53d8:	4631      	mov	r1, r6
    53da:	4630      	mov	r0, r6
    53dc:	f7ff fe73 	bl	50c6 <uECC_vli_modMult_fast>
}
    53e0:	b009      	add	sp, #36	; 0x24
    53e2:	bdf0      	pop	{r4, r5, r6, r7, pc}

000053e4 <XYcZ_add>:
}

void XYcZ_add(uECC_word_t * X1, uECC_word_t * Y1,
	      uECC_word_t * X2, uECC_word_t * Y2,
	      uECC_Curve curve)
{
    53e4:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
    53e8:	b08a      	sub	sp, #40	; 0x28
    53ea:	4614      	mov	r4, r2
    53ec:	f8dd a048 	ldr.w	sl, [sp, #72]	; 0x48
	/* t1 = X1, t2 = Y1, t3 = X2, t4 = Y2 */
	uECC_word_t t5[NUM_ECC_WORDS];
	wordcount_t num_words = curve->num_words;
    53f0:	4655      	mov	r5, sl
{
    53f2:	461f      	mov	r7, r3
	wordcount_t num_words = curve->num_words;
    53f4:	f915 6b04 	ldrsb.w	r6, [r5], #4

	uECC_vli_modSub(t5, X2, X1, curve->p, num_words); /* t5 = x2 - x1 */
    53f8:	9600      	str	r6, [sp, #0]
{
    53fa:	4680      	mov	r8, r0
    53fc:	4689      	mov	r9, r1
	uECC_vli_modSub(t5, X2, X1, curve->p, num_words); /* t5 = x2 - x1 */
    53fe:	462b      	mov	r3, r5
    5400:	4602      	mov	r2, r0
    5402:	4621      	mov	r1, r4
    5404:	a802      	add	r0, sp, #8
    5406:	f7ff fda4 	bl	4f52 <uECC_vli_modSub>
	uECC_vli_modSquare_fast(t5, t5, curve); /* t5 = (x2 - x1)^2 = A */
    540a:	a902      	add	r1, sp, #8
    540c:	4652      	mov	r2, sl
    540e:	4608      	mov	r0, r1
    5410:	f7ff fe69 	bl	50e6 <uECC_vli_modSquare_fast>
	uECC_vli_modMult_fast(X1, X1, t5, curve); /* t1 = x1*A = B */
    5414:	4653      	mov	r3, sl
    5416:	aa02      	add	r2, sp, #8
    5418:	4641      	mov	r1, r8
    541a:	4640      	mov	r0, r8
    541c:	f7ff fe53 	bl	50c6 <uECC_vli_modMult_fast>
	uECC_vli_modMult_fast(X2, X2, t5, curve); /* t3 = x2*A = C */
    5420:	4653      	mov	r3, sl
    5422:	aa02      	add	r2, sp, #8
    5424:	4621      	mov	r1, r4
    5426:	4620      	mov	r0, r4
    5428:	f7ff fe4d 	bl	50c6 <uECC_vli_modMult_fast>
	uECC_vli_modSub(Y2, Y2, Y1, curve->p, num_words); /* t4 = y2 - y1 */
    542c:	462b      	mov	r3, r5
    542e:	464a      	mov	r2, r9
    5430:	4639      	mov	r1, r7
    5432:	4638      	mov	r0, r7
    5434:	9600      	str	r6, [sp, #0]
    5436:	f7ff fd8c 	bl	4f52 <uECC_vli_modSub>
	uECC_vli_modSquare_fast(t5, Y2, curve); /* t5 = (y2 - y1)^2 = D */
    543a:	4652      	mov	r2, sl
    543c:	4639      	mov	r1, r7
    543e:	a802      	add	r0, sp, #8
    5440:	f7ff fe51 	bl	50e6 <uECC_vli_modSquare_fast>

	uECC_vli_modSub(t5, t5, X1, curve->p, num_words); /* t5 = D - B */
    5444:	a902      	add	r1, sp, #8
    5446:	462b      	mov	r3, r5
    5448:	4642      	mov	r2, r8
    544a:	4608      	mov	r0, r1
    544c:	9600      	str	r6, [sp, #0]
    544e:	f7ff fd80 	bl	4f52 <uECC_vli_modSub>
	uECC_vli_modSub(t5, t5, X2, curve->p, num_words); /* t5 = D - B - C = x3 */
    5452:	a902      	add	r1, sp, #8
    5454:	462b      	mov	r3, r5
    5456:	4622      	mov	r2, r4
    5458:	4608      	mov	r0, r1
    545a:	9600      	str	r6, [sp, #0]
    545c:	f7ff fd79 	bl	4f52 <uECC_vli_modSub>
	uECC_vli_modSub(X2, X2, X1, curve->p, num_words); /* t3 = C - B */
    5460:	462b      	mov	r3, r5
    5462:	4642      	mov	r2, r8
    5464:	4621      	mov	r1, r4
    5466:	4620      	mov	r0, r4
    5468:	9600      	str	r6, [sp, #0]
    546a:	f7ff fd72 	bl	4f52 <uECC_vli_modSub>
	uECC_vli_modMult_fast(Y1, Y1, X2, curve); /* t2 = y1*(C - B) */
    546e:	4653      	mov	r3, sl
    5470:	4622      	mov	r2, r4
    5472:	4649      	mov	r1, r9
    5474:	4648      	mov	r0, r9
    5476:	f7ff fe26 	bl	50c6 <uECC_vli_modMult_fast>
	uECC_vli_modSub(X2, X1, t5, curve->p, num_words); /* t3 = B - x3 */
    547a:	462b      	mov	r3, r5
    547c:	aa02      	add	r2, sp, #8
    547e:	4641      	mov	r1, r8
    5480:	4620      	mov	r0, r4
    5482:	9600      	str	r6, [sp, #0]
    5484:	f7ff fd65 	bl	4f52 <uECC_vli_modSub>
	uECC_vli_modMult_fast(Y2, Y2, X2, curve); /* t4 = (y2 - y1)*(B - x3) */
    5488:	4653      	mov	r3, sl
    548a:	4622      	mov	r2, r4
    548c:	4639      	mov	r1, r7
    548e:	4638      	mov	r0, r7
    5490:	f7ff fe19 	bl	50c6 <uECC_vli_modMult_fast>
	uECC_vli_modSub(Y2, Y2, Y1, curve->p, num_words); /* t4 = y3 */
    5494:	462b      	mov	r3, r5
    5496:	464a      	mov	r2, r9
    5498:	4639      	mov	r1, r7
    549a:	4638      	mov	r0, r7
    549c:	9600      	str	r6, [sp, #0]
    549e:	f7ff fd58 	bl	4f52 <uECC_vli_modSub>

	uECC_vli_set(X2, t5, num_words);
    54a2:	4632      	mov	r2, r6
    54a4:	a902      	add	r1, sp, #8
    54a6:	4620      	mov	r0, r4
    54a8:	f7ff fcec 	bl	4e84 <uECC_vli_set>
}
    54ac:	b00a      	add	sp, #40	; 0x28
    54ae:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}

000054b2 <uECC_vli_bytesToNative>:
}

/* Converts big-endian bytes to an integer in uECC native format. */
void uECC_vli_bytesToNative(unsigned int *native, const uint8_t *bytes,
			    int num_bytes)
{
    54b2:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    54b4:	460e      	mov	r6, r1
	wordcount_t i;
	uECC_vli_clear(native, (num_bytes + (uECC_WORD_SIZE - 1)) / uECC_WORD_SIZE);
    54b6:	1cd1      	adds	r1, r2, #3
    54b8:	bf48      	it	mi
    54ba:	1d91      	addmi	r1, r2, #6
    54bc:	f341 0187 	sbfx	r1, r1, #2, #8
{
    54c0:	4614      	mov	r4, r2
	uECC_vli_clear(native, (num_bytes + (uECC_WORD_SIZE - 1)) / uECC_WORD_SIZE);
    54c2:	f7ff fc9c 	bl	4dfe <uECC_vli_clear>
	for (i = 0; i < num_bytes; ++i) {
    54c6:	2500      	movs	r5, #0
		unsigned b = num_bytes - 1 - i;
    54c8:	1e67      	subs	r7, r4, #1
    54ca:	b26a      	sxtb	r2, r5
	for (i = 0; i < num_bytes; ++i) {
    54cc:	42a2      	cmp	r2, r4
    54ce:	f105 0501 	add.w	r5, r5, #1
    54d2:	db00      	blt.n	54d6 <uECC_vli_bytesToNative+0x24>
		native[b / uECC_WORD_SIZE] |=
			(uECC_word_t)bytes[i] << (8 * (b % uECC_WORD_SIZE));
  	}
}
    54d4:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
		unsigned b = num_bytes - 1 - i;
    54d6:	1abb      	subs	r3, r7, r2
		native[b / uECC_WORD_SIZE] |=
    54d8:	f023 0103 	bic.w	r1, r3, #3
			(uECC_word_t)bytes[i] << (8 * (b % uECC_WORD_SIZE));
    54dc:	5cb2      	ldrb	r2, [r6, r2]
    54de:	f003 0303 	and.w	r3, r3, #3
    54e2:	00db      	lsls	r3, r3, #3
    54e4:	fa02 f303 	lsl.w	r3, r2, r3
		native[b / uECC_WORD_SIZE] |=
    54e8:	5842      	ldr	r2, [r0, r1]
    54ea:	431a      	orrs	r2, r3
    54ec:	5042      	str	r2, [r0, r1]
	for (i = 0; i < num_bytes; ++i) {
    54ee:	e7ec      	b.n	54ca <uECC_vli_bytesToNative+0x18>

000054f0 <bits2int>:
static uECC_RNG_Function g_rng_function = 0;
#endif

static void bits2int(uECC_word_t *native, const uint8_t *bits,
		     unsigned bits_size, uECC_Curve curve)
{
    54f0:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
    54f4:	4698      	mov	r8, r3
	unsigned num_n_bytes = BITS_TO_BYTES(curve->num_n_bits);
    54f6:	f9b3 3002 	ldrsh.w	r3, [r3, #2]
	unsigned num_n_words = BITS_TO_WORDS(curve->num_n_bits);
    54fa:	f113 041f 	adds.w	r4, r3, #31
    54fe:	bf48      	it	mi
    5500:	f103 043e 	addmi.w	r4, r3, #62	; 0x3e
	unsigned num_n_bytes = BITS_TO_BYTES(curve->num_n_bits);
    5504:	1ddd      	adds	r5, r3, #7
    5506:	bf48      	it	mi
    5508:	f103 050e 	addmi.w	r5, r3, #14
	unsigned num_n_words = BITS_TO_WORDS(curve->num_n_bits);
    550c:	1166      	asrs	r6, r4, #5
	unsigned num_n_bytes = BITS_TO_BYTES(curve->num_n_bits);
    550e:	10ec      	asrs	r4, r5, #3
    5510:	4294      	cmp	r4, r2

	if (bits_size > num_n_bytes) {
		bits_size = num_n_bytes;
	}

	uECC_vli_clear(native, num_n_words);
    5512:	b275      	sxtb	r5, r6
    5514:	bf28      	it	cs
    5516:	4614      	movcs	r4, r2
{
    5518:	4607      	mov	r7, r0
    551a:	4689      	mov	r9, r1
	uECC_vli_clear(native, num_n_words);
    551c:	4629      	mov	r1, r5
    551e:	f7ff fc6e 	bl	4dfe <uECC_vli_clear>
	uECC_vli_bytesToNative(native, bits, bits_size);
    5522:	4622      	mov	r2, r4
    5524:	4649      	mov	r1, r9
    5526:	4638      	mov	r0, r7
    5528:	f7ff ffc3 	bl	54b2 <uECC_vli_bytesToNative>
	if (bits_size * 8 <= (unsigned)curve->num_n_bits) {
    552c:	f9b8 3002 	ldrsh.w	r3, [r8, #2]
    5530:	ebb3 0fc4 	cmp.w	r3, r4, lsl #3
    5534:	ea4f 02c4 	mov.w	r2, r4, lsl #3
    5538:	d221      	bcs.n	557e <bits2int+0x8e>
		return;
	}
	shift = bits_size * 8 - curve->num_n_bits;
    553a:	1ad2      	subs	r2, r2, r3
	carry = 0;
	ptr = native + num_n_words;
    553c:	eb07 0486 	add.w	r4, r7, r6, lsl #2
	carry = 0;
    5540:	2100      	movs	r1, #0
	while (ptr-- > native) {
		uECC_word_t temp = *ptr;
		*ptr = (temp >> shift) | carry;
		carry = temp << (uECC_WORD_BITS - shift);
    5542:	f1c2 0620 	rsb	r6, r2, #32
	while (ptr-- > native) {
    5546:	42a7      	cmp	r7, r4
    5548:	d310      	bcc.n	556c <bits2int+0x7c>
	}

	/* Reduce mod curve_n */
	if (uECC_vli_cmp_unsafe(curve->n, native, num_n_words) != 1) {
    554a:	f108 0824 	add.w	r8, r8, #36	; 0x24
    554e:	462a      	mov	r2, r5
    5550:	4639      	mov	r1, r7
    5552:	4640      	mov	r0, r8
    5554:	f7ff fca2 	bl	4e9c <uECC_vli_cmp_unsafe>
    5558:	2801      	cmp	r0, #1
    555a:	d010      	beq.n	557e <bits2int+0x8e>
		uECC_vli_sub(native, native, curve->n, num_n_words);
    555c:	462b      	mov	r3, r5
    555e:	4642      	mov	r2, r8
    5560:	4639      	mov	r1, r7
    5562:	4638      	mov	r0, r7
	}
}
    5564:	e8bd 47f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
		uECC_vli_sub(native, native, curve->n, num_n_words);
    5568:	f7ff bcbf 	b.w	4eea <uECC_vli_sub>
		uECC_word_t temp = *ptr;
    556c:	f854 0d04 	ldr.w	r0, [r4, #-4]!
		*ptr = (temp >> shift) | carry;
    5570:	fa20 f302 	lsr.w	r3, r0, r2
    5574:	430b      	orrs	r3, r1
    5576:	6023      	str	r3, [r4, #0]
		carry = temp << (uECC_WORD_BITS - shift);
    5578:	fa00 f106 	lsl.w	r1, r0, r6
    557c:	e7e3      	b.n	5546 <bits2int+0x56>
}
    557e:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}

00005582 <uECC_verify>:
}

int uECC_verify(const uint8_t *public_key, const uint8_t *message_hash,
		unsigned hash_size, const uint8_t *signature,
	        uECC_Curve curve)
{
    5582:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    5586:	b0fd      	sub	sp, #500	; 0x1f4
    5588:	461d      	mov	r5, r3
    558a:	9e86      	ldr	r6, [sp, #536]	; 0x218
    558c:	9105      	str	r1, [sp, #20]
	bitcount_t i;

	uECC_word_t _public[NUM_ECC_WORDS * 2];
	uECC_word_t r[NUM_ECC_WORDS], s[NUM_ECC_WORDS];
	wordcount_t num_words = curve->num_words;
	wordcount_t num_n_words = BITS_TO_WORDS(curve->num_n_bits);
    558e:	f9b6 3002 	ldrsh.w	r3, [r6, #2]
	wordcount_t num_words = curve->num_words;
    5592:	f996 4000 	ldrsb.w	r4, [r6]
{
    5596:	4691      	mov	r9, r2
	wordcount_t num_n_words = BITS_TO_WORDS(curve->num_n_bits);
    5598:	f113 021f 	adds.w	r2, r3, #31
    559c:	bf48      	it	mi
    559e:	f103 023e 	addmi.w	r2, r3, #62	; 0x3e
    55a2:	f342 1b47 	sbfx	fp, r2, #5, #8

	rx[num_n_words - 1] = 0;
    55a6:	f10b 38ff 	add.w	r8, fp, #4294967295
    55aa:	aa24      	add	r2, sp, #144	; 0x90
    55ac:	2300      	movs	r3, #0
    55ae:	f842 3028 	str.w	r3, [r2, r8, lsl #2]
	r[num_n_words - 1] = 0;
    55b2:	aa7c      	add	r2, sp, #496	; 0x1f0
    55b4:	eb02 0288 	add.w	r2, r2, r8, lsl #2
	s[num_n_words - 1] = 0;

	uECC_vli_bytesToNative(_public, public_key, curve->num_bytes);
    55b8:	4601      	mov	r1, r0
	r[num_n_words - 1] = 0;
    55ba:	f842 3cc0 	str.w	r3, [r2, #-192]
	s[num_n_words - 1] = 0;
    55be:	f842 3ca0 	str.w	r3, [r2, #-160]
{
    55c2:	4607      	mov	r7, r0
	uECC_vli_bytesToNative(_public, public_key, curve->num_bytes);
    55c4:	f996 2001 	ldrsb.w	r2, [r6, #1]
    55c8:	a86c      	add	r0, sp, #432	; 0x1b0
    55ca:	f7ff ff72 	bl	54b2 <uECC_vli_bytesToNative>
	uECC_vli_bytesToNative(_public + num_words, public_key + curve->num_bytes,
    55ce:	00a3      	lsls	r3, r4, #2
    55d0:	f996 2001 	ldrsb.w	r2, [r6, #1]
    55d4:	9307      	str	r3, [sp, #28]
    55d6:	ab6c      	add	r3, sp, #432	; 0x1b0
    55d8:	eb03 0a84 	add.w	sl, r3, r4, lsl #2
    55dc:	18b9      	adds	r1, r7, r2
    55de:	4650      	mov	r0, sl
    55e0:	f7ff ff67 	bl	54b2 <uECC_vli_bytesToNative>
			       curve->num_bytes);
	uECC_vli_bytesToNative(r, signature, curve->num_bytes);
    55e4:	f996 2001 	ldrsb.w	r2, [r6, #1]
    55e8:	4629      	mov	r1, r5
    55ea:	a84c      	add	r0, sp, #304	; 0x130
    55ec:	f7ff ff61 	bl	54b2 <uECC_vli_bytesToNative>
	uECC_vli_bytesToNative(s, signature + curve->num_bytes, curve->num_bytes);
    55f0:	f996 2001 	ldrsb.w	r2, [r6, #1]
    55f4:	a854      	add	r0, sp, #336	; 0x150
    55f6:	18a9      	adds	r1, r5, r2
    55f8:	f7ff ff5b 	bl	54b2 <uECC_vli_bytesToNative>

	/* r, s must not be 0. */
	if (uECC_vli_isZero(r, num_words) || uECC_vli_isZero(s, num_words)) {
    55fc:	4621      	mov	r1, r4
    55fe:	a84c      	add	r0, sp, #304	; 0x130
    5600:	f7ff fc08 	bl	4e14 <uECC_vli_isZero>
    5604:	b118      	cbz	r0, 560e <uECC_verify+0x8c>
		return 0;
    5606:	2000      	movs	r0, #0
		uECC_vli_sub(rx, rx, curve->n, num_n_words);
	}

	/* Accept only if v == r. */
	return (int)(uECC_vli_equal(rx, r, num_words) == 0);
}
    5608:	b07d      	add	sp, #500	; 0x1f4
    560a:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
	if (uECC_vli_isZero(r, num_words) || uECC_vli_isZero(s, num_words)) {
    560e:	4621      	mov	r1, r4
    5610:	a854      	add	r0, sp, #336	; 0x150
    5612:	f7ff fbff 	bl	4e14 <uECC_vli_isZero>
    5616:	9003      	str	r0, [sp, #12]
    5618:	2800      	cmp	r0, #0
    561a:	d1f4      	bne.n	5606 <uECC_verify+0x84>
	if (uECC_vli_cmp_unsafe(curve->n, r, num_n_words) != 1 ||
    561c:	f106 0324 	add.w	r3, r6, #36	; 0x24
    5620:	465a      	mov	r2, fp
    5622:	a94c      	add	r1, sp, #304	; 0x130
    5624:	4618      	mov	r0, r3
    5626:	9304      	str	r3, [sp, #16]
    5628:	f7ff fc38 	bl	4e9c <uECC_vli_cmp_unsafe>
    562c:	2801      	cmp	r0, #1
    562e:	d1ea      	bne.n	5606 <uECC_verify+0x84>
	    uECC_vli_cmp_unsafe(curve->n, s, num_n_words) != 1) {
    5630:	465a      	mov	r2, fp
    5632:	a954      	add	r1, sp, #336	; 0x150
    5634:	f106 0024 	add.w	r0, r6, #36	; 0x24
    5638:	f7ff fc30 	bl	4e9c <uECC_vli_cmp_unsafe>
	if (uECC_vli_cmp_unsafe(curve->n, r, num_n_words) != 1 ||
    563c:	2801      	cmp	r0, #1
	    uECC_vli_cmp_unsafe(curve->n, s, num_n_words) != 1) {
    563e:	9006      	str	r0, [sp, #24]
	if (uECC_vli_cmp_unsafe(curve->n, r, num_n_words) != 1 ||
    5640:	d1e1      	bne.n	5606 <uECC_verify+0x84>
	uECC_vli_modInv(z, s, curve->n, num_n_words); /* z = 1/s */
    5642:	ad1c      	add	r5, sp, #112	; 0x70
	u1[num_n_words - 1] = 0;
    5644:	af0c      	add	r7, sp, #48	; 0x30
	uECC_vli_modInv(z, s, curve->n, num_n_words); /* z = 1/s */
    5646:	465b      	mov	r3, fp
    5648:	f106 0224 	add.w	r2, r6, #36	; 0x24
    564c:	a954      	add	r1, sp, #336	; 0x150
    564e:	4628      	mov	r0, r5
    5650:	f7ff fe25 	bl	529e <uECC_vli_modInv>
	u1[num_n_words - 1] = 0;
    5654:	9b03      	ldr	r3, [sp, #12]
    5656:	f847 3028 	str.w	r3, [r7, r8, lsl #2]
	bits2int(u1, message_hash, hash_size, curve);
    565a:	464a      	mov	r2, r9
    565c:	4638      	mov	r0, r7
    565e:	9905      	ldr	r1, [sp, #20]
    5660:	4633      	mov	r3, r6
    5662:	f7ff ff45 	bl	54f0 <bits2int>
	uECC_vli_modMult(u1, u1, z, curve->n, num_n_words); /* u1 = e/s */
    5666:	4639      	mov	r1, r7
    5668:	4638      	mov	r0, r7
    566a:	f106 0324 	add.w	r3, r6, #36	; 0x24
    566e:	462a      	mov	r2, r5
    5670:	f8cd b000 	str.w	fp, [sp]
    5674:	f7ff fd17 	bl	50a6 <uECC_vli_modMult>
	uECC_vli_set(sum, _public, num_words);
    5678:	f50d 78b8 	add.w	r8, sp, #368	; 0x170
	uECC_vli_modMult(u2, r, z, curve->n, num_n_words); /* u2 = r/s */
    567c:	f106 0324 	add.w	r3, r6, #36	; 0x24
    5680:	462a      	mov	r2, r5
    5682:	a94c      	add	r1, sp, #304	; 0x130
    5684:	a814      	add	r0, sp, #80	; 0x50
    5686:	f8cd b000 	str.w	fp, [sp]
    568a:	f7ff fd0c 	bl	50a6 <uECC_vli_modMult>
	uECC_vli_set(sum, _public, num_words);
    568e:	4640      	mov	r0, r8
    5690:	4622      	mov	r2, r4
    5692:	a96c      	add	r1, sp, #432	; 0x1b0
    5694:	f7ff fbf6 	bl	4e84 <uECC_vli_set>
	uECC_vli_set(sum + num_words, _public + num_words, num_words);
    5698:	00a3      	lsls	r3, r4, #2
    569a:	eb08 0903 	add.w	r9, r8, r3
    569e:	4651      	mov	r1, sl
    56a0:	4648      	mov	r0, r9
	uECC_vli_set(tx, curve->G, num_words);
    56a2:	f106 0a44 	add.w	sl, r6, #68	; 0x44
	uECC_vli_set(sum + num_words, _public + num_words, num_words);
    56a6:	4622      	mov	r2, r4
    56a8:	f7ff fbec 	bl	4e84 <uECC_vli_set>
	uECC_vli_set(tx, curve->G, num_words);
    56ac:	4651      	mov	r1, sl
    56ae:	4622      	mov	r2, r4
    56b0:	a834      	add	r0, sp, #208	; 0xd0
    56b2:	f7ff fbe7 	bl	4e84 <uECC_vli_set>
	uECC_vli_set(ty, curve->G + num_words, num_words);
    56b6:	00a3      	lsls	r3, r4, #2
    56b8:	eb0a 0103 	add.w	r1, sl, r3
    56bc:	4622      	mov	r2, r4
    56be:	a83c      	add	r0, sp, #240	; 0xf0
    56c0:	f7ff fbe0 	bl	4e84 <uECC_vli_set>
	uECC_vli_modSub(z, sum, tx, curve->p, num_words); /* z = x2 - x1 */
    56c4:	1d33      	adds	r3, r6, #4
    56c6:	4641      	mov	r1, r8
    56c8:	aa34      	add	r2, sp, #208	; 0xd0
    56ca:	4628      	mov	r0, r5
    56cc:	9400      	str	r4, [sp, #0]
    56ce:	9305      	str	r3, [sp, #20]
    56d0:	f7ff fc3f 	bl	4f52 <uECC_vli_modSub>
	XYcZ_add(tx, ty, sum, sum + num_words, curve);
    56d4:	464b      	mov	r3, r9
    56d6:	4642      	mov	r2, r8
    56d8:	a93c      	add	r1, sp, #240	; 0xf0
    56da:	a834      	add	r0, sp, #208	; 0xd0
    56dc:	9600      	str	r6, [sp, #0]
    56de:	f7ff fe81 	bl	53e4 <XYcZ_add>
	uECC_vli_modInv(z, z, curve->p, num_words); /* z = 1/z */
    56e2:	4623      	mov	r3, r4
    56e4:	1d32      	adds	r2, r6, #4
    56e6:	4629      	mov	r1, r5
    56e8:	4628      	mov	r0, r5
    56ea:	f7ff fdd8 	bl	529e <uECC_vli_modInv>
	apply_z(sum, sum + num_words, z, curve);
    56ee:	462a      	mov	r2, r5
    56f0:	4649      	mov	r1, r9
    56f2:	4640      	mov	r0, r8
    56f4:	4633      	mov	r3, r6
    56f6:	f7ff fe56 	bl	53a6 <apply_z>
	points[0] = 0;
    56fa:	9b03      	ldr	r3, [sp, #12]
	num_bits = smax(uECC_vli_numBits(u1, num_n_words),
    56fc:	4659      	mov	r1, fp
	points[1] = curve->G;
    56fe:	e9cd 3a08 	strd	r3, sl, [sp, #32]
	num_bits = smax(uECC_vli_numBits(u1, num_n_words),
    5702:	4638      	mov	r0, r7
	points[2] = _public;
    5704:	ab6c      	add	r3, sp, #432	; 0x1b0
	points[3] = sum;
    5706:	e9cd 380a 	strd	r3, r8, [sp, #40]	; 0x28
	num_bits = smax(uECC_vli_numBits(u1, num_n_words),
    570a:	f7ff fb9c 	bl	4e46 <uECC_vli_numBits>
    570e:	4659      	mov	r1, fp
    5710:	4680      	mov	r8, r0
    5712:	a814      	add	r0, sp, #80	; 0x50
    5714:	f7ff fb97 	bl	4e46 <uECC_vli_numBits>
	return (a > b ? a : b);
    5718:	4580      	cmp	r8, r0
    571a:	bfb8      	it	lt
    571c:	4680      	movlt	r8, r0
	point = points[(!!uECC_vli_testBit(u1, num_bits - 1)) |
    571e:	fa1f f888 	uxth.w	r8, r8
    5722:	f108 3aff 	add.w	sl, r8, #4294967295
    5726:	fa0f fa8a 	sxth.w	sl, sl
    572a:	4651      	mov	r1, sl
    572c:	4638      	mov	r0, r7
    572e:	f7ff fb80 	bl	4e32 <uECC_vli_testBit>
                       ((!!uECC_vli_testBit(u2, num_bits - 1)) << 1)];
    5732:	4651      	mov	r1, sl
	point = points[(!!uECC_vli_testBit(u1, num_bits - 1)) |
    5734:	1e07      	subs	r7, r0, #0
                       ((!!uECC_vli_testBit(u2, num_bits - 1)) << 1)];
    5736:	a814      	add	r0, sp, #80	; 0x50
	point = points[(!!uECC_vli_testBit(u1, num_bits - 1)) |
    5738:	bf18      	it	ne
    573a:	2701      	movne	r7, #1
                       ((!!uECC_vli_testBit(u2, num_bits - 1)) << 1)];
    573c:	f7ff fb79 	bl	4e32 <uECC_vli_testBit>
    5740:	2800      	cmp	r0, #0
    5742:	bf14      	ite	ne
    5744:	2002      	movne	r0, #2
    5746:	2000      	moveq	r0, #0
	points[0] = 0;
    5748:	f10d 0920 	add.w	r9, sp, #32
	point = points[(!!uECC_vli_testBit(u1, num_bits - 1)) |
    574c:	4307      	orrs	r7, r0
	uECC_vli_set(rx, point, num_words);
    574e:	4622      	mov	r2, r4
	point = points[(!!uECC_vli_testBit(u1, num_bits - 1)) |
    5750:	f859 7027 	ldr.w	r7, [r9, r7, lsl #2]
	uECC_vli_set(rx, point, num_words);
    5754:	a824      	add	r0, sp, #144	; 0x90
    5756:	4639      	mov	r1, r7
    5758:	f7ff fb94 	bl	4e84 <uECC_vli_set>
	uECC_vli_set(ry, point + num_words, num_words);
    575c:	f10d 0ab0 	add.w	sl, sp, #176	; 0xb0
    5760:	00a3      	lsls	r3, r4, #2
    5762:	18f9      	adds	r1, r7, r3
    5764:	4622      	mov	r2, r4
    5766:	4650      	mov	r0, sl
    5768:	f7ff fb8c 	bl	4e84 <uECC_vli_set>
	uECC_vli_clear(z, num_words);
    576c:	4621      	mov	r1, r4
    576e:	4628      	mov	r0, r5
    5770:	f7ff fb45 	bl	4dfe <uECC_vli_clear>
	for (i = num_bits - 2; i >= 0; --i) {
    5774:	f1a8 0802 	sub.w	r8, r8, #2
	z[0] = 1;
    5778:	9b06      	ldr	r3, [sp, #24]
    577a:	602b      	str	r3, [r5, #0]
	for (i = num_bits - 2; i >= 0; --i) {
    577c:	fa0f f888 	sxth.w	r8, r8
    5780:	f10d 0990 	add.w	r9, sp, #144	; 0x90
    5784:	f1b8 0f00 	cmp.w	r8, #0
    5788:	da21      	bge.n	57ce <uECC_verify+0x24c>
	uECC_vli_modInv(z, z, curve->p, num_words); /* Z = 1/Z */
    578a:	9a05      	ldr	r2, [sp, #20]
    578c:	4623      	mov	r3, r4
    578e:	4629      	mov	r1, r5
    5790:	4628      	mov	r0, r5
    5792:	f7ff fd84 	bl	529e <uECC_vli_modInv>
	apply_z(rx, ry, z, curve);
    5796:	4633      	mov	r3, r6
    5798:	462a      	mov	r2, r5
    579a:	4651      	mov	r1, sl
    579c:	4648      	mov	r0, r9
    579e:	f7ff fe02 	bl	53a6 <apply_z>
	if (uECC_vli_cmp_unsafe(curve->n, rx, num_n_words) != 1) {
    57a2:	9804      	ldr	r0, [sp, #16]
    57a4:	465a      	mov	r2, fp
    57a6:	4649      	mov	r1, r9
    57a8:	f7ff fb78 	bl	4e9c <uECC_vli_cmp_unsafe>
    57ac:	2801      	cmp	r0, #1
    57ae:	d005      	beq.n	57bc <uECC_verify+0x23a>
		uECC_vli_sub(rx, rx, curve->n, num_n_words);
    57b0:	9a04      	ldr	r2, [sp, #16]
    57b2:	465b      	mov	r3, fp
    57b4:	4649      	mov	r1, r9
    57b6:	4648      	mov	r0, r9
    57b8:	f7ff fb97 	bl	4eea <uECC_vli_sub>
	return (int)(uECC_vli_equal(rx, r, num_words) == 0);
    57bc:	4622      	mov	r2, r4
    57be:	a94c      	add	r1, sp, #304	; 0x130
    57c0:	4648      	mov	r0, r9
    57c2:	f7ff fb80 	bl	4ec6 <uECC_vli_equal>
    57c6:	fab0 f080 	clz	r0, r0
    57ca:	0940      	lsrs	r0, r0, #5
    57cc:	e71c      	b.n	5608 <uECC_verify+0x86>
		curve->double_jacobian(rx, ry, z, curve);
    57ce:	4633      	mov	r3, r6
    57d0:	462a      	mov	r2, r5
    57d2:	f8d6 70a4 	ldr.w	r7, [r6, #164]	; 0xa4
    57d6:	4651      	mov	r1, sl
    57d8:	4648      	mov	r0, r9
    57da:	47b8      	blx	r7
		index = (!!uECC_vli_testBit(u1, i)) | ((!!uECC_vli_testBit(u2, i)) << 1);
    57dc:	4641      	mov	r1, r8
    57de:	a80c      	add	r0, sp, #48	; 0x30
    57e0:	f7ff fb27 	bl	4e32 <uECC_vli_testBit>
    57e4:	4641      	mov	r1, r8
    57e6:	1e07      	subs	r7, r0, #0
    57e8:	a814      	add	r0, sp, #80	; 0x50
    57ea:	bf18      	it	ne
    57ec:	2701      	movne	r7, #1
    57ee:	f7ff fb20 	bl	4e32 <uECC_vli_testBit>
    57f2:	2800      	cmp	r0, #0
    57f4:	bf14      	ite	ne
    57f6:	2002      	movne	r0, #2
    57f8:	2000      	moveq	r0, #0
    57fa:	4307      	orrs	r7, r0
		point = points[index];
    57fc:	ab08      	add	r3, sp, #32
    57fe:	f853 7027 	ldr.w	r7, [r3, r7, lsl #2]
		if (point) {
    5802:	b327      	cbz	r7, 584e <uECC_verify+0x2cc>
			uECC_vli_set(tx, point, num_words);
    5804:	4622      	mov	r2, r4
    5806:	4639      	mov	r1, r7
    5808:	a834      	add	r0, sp, #208	; 0xd0
    580a:	f7ff fb3b 	bl	4e84 <uECC_vli_set>
			uECC_vli_set(ty, point + num_words, num_words);
    580e:	9b07      	ldr	r3, [sp, #28]
    5810:	4622      	mov	r2, r4
    5812:	18f9      	adds	r1, r7, r3
    5814:	a83c      	add	r0, sp, #240	; 0xf0
    5816:	f7ff fb35 	bl	4e84 <uECC_vli_set>
			apply_z(tx, ty, z, curve);
    581a:	4633      	mov	r3, r6
    581c:	462a      	mov	r2, r5
    581e:	a93c      	add	r1, sp, #240	; 0xf0
    5820:	a834      	add	r0, sp, #208	; 0xd0
    5822:	f7ff fdc0 	bl	53a6 <apply_z>
			uECC_vli_modSub(tz, rx, tx, curve->p, num_words); /* Z = x2 - x1 */
    5826:	9b05      	ldr	r3, [sp, #20]
    5828:	9400      	str	r4, [sp, #0]
    582a:	aa34      	add	r2, sp, #208	; 0xd0
    582c:	4649      	mov	r1, r9
    582e:	a844      	add	r0, sp, #272	; 0x110
    5830:	f7ff fb8f 	bl	4f52 <uECC_vli_modSub>
			XYcZ_add(tx, ty, rx, ry, curve);
    5834:	4653      	mov	r3, sl
    5836:	464a      	mov	r2, r9
    5838:	a93c      	add	r1, sp, #240	; 0xf0
    583a:	a834      	add	r0, sp, #208	; 0xd0
    583c:	9600      	str	r6, [sp, #0]
    583e:	f7ff fdd1 	bl	53e4 <XYcZ_add>
			uECC_vli_modMult_fast(z, z, tz, curve);
    5842:	4633      	mov	r3, r6
    5844:	aa44      	add	r2, sp, #272	; 0x110
    5846:	4629      	mov	r1, r5
    5848:	4628      	mov	r0, r5
    584a:	f7ff fc3c 	bl	50c6 <uECC_vli_modMult_fast>
	for (i = num_bits - 2; i >= 0; --i) {
    584e:	f108 38ff 	add.w	r8, r8, #4294967295
    5852:	fa0f f888 	sxth.w	r8, r8
    5856:	e795      	b.n	5784 <uECC_verify+0x202>

00005858 <tc_sha256_update>:
{
    5858:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    585a:	460c      	mov	r4, r1
	if (s == (TCSha256State_t) 0 ||
    585c:	b110      	cbz	r0, 5864 <tc_sha256_update+0xc>
    585e:	b1f9      	cbz	r1, 58a0 <tc_sha256_update+0x48>
	} else if (datalen == 0) {
    5860:	b90a      	cbnz	r2, 5866 <tc_sha256_update+0xe>
		return TC_CRYPTO_SUCCESS;
    5862:	2001      	movs	r0, #1
}
    5864:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    5866:	188d      	adds	r5, r1, r2
			compress(s->iv, s->leftover);
    5868:	f100 0728 	add.w	r7, r0, #40	; 0x28
			s->leftover_offset = 0;
    586c:	2600      	movs	r6, #0
	while (datalen-- > 0) {
    586e:	42a5      	cmp	r5, r4
    5870:	d0f7      	beq.n	5862 <tc_sha256_update+0xa>
		s->leftover[s->leftover_offset++] = *(data++);
    5872:	6e83      	ldr	r3, [r0, #104]	; 0x68
    5874:	1c5a      	adds	r2, r3, #1
    5876:	6682      	str	r2, [r0, #104]	; 0x68
    5878:	4403      	add	r3, r0
    587a:	f814 1b01 	ldrb.w	r1, [r4], #1
    587e:	f883 1028 	strb.w	r1, [r3, #40]	; 0x28
		if (s->leftover_offset >= TC_SHA256_BLOCK_SIZE) {
    5882:	2a3f      	cmp	r2, #63	; 0x3f
    5884:	d9f3      	bls.n	586e <tc_sha256_update+0x16>
			compress(s->iv, s->leftover);
    5886:	4639      	mov	r1, r7
    5888:	f7fb fd9a 	bl	13c0 <compress>
			s->bits_hashed += (TC_SHA256_BLOCK_SIZE << 3);
    588c:	e9d0 3208 	ldrd	r3, r2, [r0, #32]
    5890:	f513 7300 	adds.w	r3, r3, #512	; 0x200
    5894:	f142 0200 	adc.w	r2, r2, #0
    5898:	e9c0 3208 	strd	r3, r2, [r0, #32]
			s->leftover_offset = 0;
    589c:	6686      	str	r6, [r0, #104]	; 0x68
			s->bits_hashed += (TC_SHA256_BLOCK_SIZE << 3);
    589e:	e7e6      	b.n	586e <tc_sha256_update+0x16>
		return TC_CRYPTO_FAIL;
    58a0:	4608      	mov	r0, r1
    58a2:	e7df      	b.n	5864 <tc_sha256_update+0xc>

000058a4 <tc_sha256_final>:
{
    58a4:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    58a6:	460c      	mov	r4, r1
	if (digest == (uint8_t *) 0 ||
    58a8:	4605      	mov	r5, r0
    58aa:	2800      	cmp	r0, #0
    58ac:	d056      	beq.n	595c <tc_sha256_final+0xb8>
    58ae:	2900      	cmp	r1, #0
    58b0:	d055      	beq.n	595e <tc_sha256_final+0xba>
	s->bits_hashed += (s->leftover_offset << 3);
    58b2:	6e8b      	ldr	r3, [r1, #104]	; 0x68
    58b4:	e9d1 2108 	ldrd	r2, r1, [r1, #32]
    58b8:	00d8      	lsls	r0, r3, #3
    58ba:	1812      	adds	r2, r2, r0
    58bc:	f141 0100 	adc.w	r1, r1, #0
	s->leftover[s->leftover_offset++] = 0x80; /* always room for one byte */
    58c0:	1c58      	adds	r0, r3, #1
    58c2:	4423      	add	r3, r4
	s->bits_hashed += (s->leftover_offset << 3);
    58c4:	e9c4 2108 	strd	r2, r1, [r4, #32]
	if (s->leftover_offset > (sizeof(s->leftover) - 8)) {
    58c8:	2838      	cmp	r0, #56	; 0x38
	s->leftover[s->leftover_offset++] = 0x80; /* always room for one byte */
    58ca:	f04f 0280 	mov.w	r2, #128	; 0x80
    58ce:	66a0      	str	r0, [r4, #104]	; 0x68
	s->bits_hashed += (s->leftover_offset << 3);
    58d0:	f04f 0700 	mov.w	r7, #0
	s->leftover[s->leftover_offset++] = 0x80; /* always room for one byte */
    58d4:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
		_set(s->leftover + s->leftover_offset, 0x00,
    58d8:	f104 0628 	add.w	r6, r4, #40	; 0x28
	if (s->leftover_offset > (sizeof(s->leftover) - 8)) {
    58dc:	d90a      	bls.n	58f4 <tc_sha256_final+0x50>
		_set(s->leftover + s->leftover_offset, 0x00,
    58de:	f1c0 0240 	rsb	r2, r0, #64	; 0x40
    58e2:	4639      	mov	r1, r7
    58e4:	4430      	add	r0, r6
    58e6:	f000 f83c 	bl	5962 <_set>
		compress(s->iv, s->leftover);
    58ea:	4631      	mov	r1, r6
    58ec:	4620      	mov	r0, r4
    58ee:	f7fb fd67 	bl	13c0 <compress>
		s->leftover_offset = 0;
    58f2:	66a7      	str	r7, [r4, #104]	; 0x68
	_set(s->leftover + s->leftover_offset, 0x00,
    58f4:	6ea0      	ldr	r0, [r4, #104]	; 0x68
    58f6:	2100      	movs	r1, #0
    58f8:	f1c0 0238 	rsb	r2, r0, #56	; 0x38
    58fc:	4430      	add	r0, r6
    58fe:	f000 f830 	bl	5962 <_set>
	s->leftover[sizeof(s->leftover) - 1] = (uint8_t)(s->bits_hashed);
    5902:	6a23      	ldr	r3, [r4, #32]
    5904:	ba1a      	rev	r2, r3
    5906:	6a63      	ldr	r3, [r4, #36]	; 0x24
	s->leftover[sizeof(s->leftover) - 4] = (uint8_t)(s->bits_hashed >> 24);
    5908:	6662      	str	r2, [r4, #100]	; 0x64
	s->leftover[sizeof(s->leftover) - 6] = (uint8_t)(s->bits_hashed >> 40);
    590a:	0a1a      	lsrs	r2, r3, #8
	s->leftover[sizeof(s->leftover) - 5] = (uint8_t)(s->bits_hashed >> 32);
    590c:	f884 3063 	strb.w	r3, [r4, #99]	; 0x63
	s->leftover[sizeof(s->leftover) - 6] = (uint8_t)(s->bits_hashed >> 40);
    5910:	f884 2062 	strb.w	r2, [r4, #98]	; 0x62
	s->leftover[sizeof(s->leftover) - 7] = (uint8_t)(s->bits_hashed >> 48);
    5914:	0c1a      	lsrs	r2, r3, #16
	s->leftover[sizeof(s->leftover) - 8] = (uint8_t)(s->bits_hashed >> 56);
    5916:	0e1b      	lsrs	r3, r3, #24
    5918:	f884 3060 	strb.w	r3, [r4, #96]	; 0x60
	compress(s->iv, s->leftover);
    591c:	4631      	mov	r1, r6
    591e:	4620      	mov	r0, r4
	s->leftover[sizeof(s->leftover) - 7] = (uint8_t)(s->bits_hashed >> 48);
    5920:	f884 2061 	strb.w	r2, [r4, #97]	; 0x61
	compress(s->iv, s->leftover);
    5924:	f7fb fd4c 	bl	13c0 <compress>
	for (i = 0; i < TC_SHA256_STATE_BLOCKS; ++i) {
    5928:	1f26      	subs	r6, r4, #4
    592a:	1d2b      	adds	r3, r5, #4
    592c:	f105 0024 	add.w	r0, r5, #36	; 0x24
		unsigned int t = *((unsigned int *) &s->iv[i]);
    5930:	f856 2f04 	ldr.w	r2, [r6, #4]!
		*digest++ = (uint8_t)(t);
    5934:	f803 2c01 	strb.w	r2, [r3, #-1]
		*digest++ = (uint8_t)(t >> 24);
    5938:	0e11      	lsrs	r1, r2, #24
    593a:	f803 1c04 	strb.w	r1, [r3, #-4]
		*digest++ = (uint8_t)(t >> 16);
    593e:	0c11      	lsrs	r1, r2, #16
    5940:	f803 1c03 	strb.w	r1, [r3, #-3]
		*digest++ = (uint8_t)(t >> 8);
    5944:	0a11      	lsrs	r1, r2, #8
    5946:	f803 1c02 	strb.w	r1, [r3, #-2]
	for (i = 0; i < TC_SHA256_STATE_BLOCKS; ++i) {
    594a:	3304      	adds	r3, #4
    594c:	4283      	cmp	r3, r0
    594e:	d1ef      	bne.n	5930 <tc_sha256_final+0x8c>
	_set(s, 0, sizeof(*s));
    5950:	4620      	mov	r0, r4
    5952:	2270      	movs	r2, #112	; 0x70
    5954:	2100      	movs	r1, #0
    5956:	f000 f804 	bl	5962 <_set>
	return TC_CRYPTO_SUCCESS;
    595a:	2001      	movs	r0, #1
}
    595c:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
		return TC_CRYPTO_FAIL;
    595e:	4608      	mov	r0, r1
    5960:	e7fc      	b.n	595c <tc_sha256_final+0xb8>

00005962 <_set>:
	}
}

void _set(void *to, uint8_t val, unsigned int len)
{
	(void)memset(to, val, len);
    5962:	f000 b9ae 	b.w	5cc2 <memset>

00005966 <sys_notify_validate>:

int sys_notify_validate(struct sys_notify *notify)
{
	int rv = 0;

	if (notify == NULL) {
    5966:	4603      	mov	r3, r0
    5968:	b158      	cbz	r0, 5982 <sys_notify_validate+0x1c>
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    596a:	6842      	ldr	r2, [r0, #4]
	return method & SYS_NOTIFY_METHOD_MASK;
    596c:	f002 0203 	and.w	r2, r2, #3
		return -EINVAL;
	}

	/* Validate configuration based on mode */
	switch (sys_notify_get_method(notify)) {
    5970:	2a01      	cmp	r2, #1
    5972:	d003      	beq.n	597c <sys_notify_validate+0x16>
    5974:	2a03      	cmp	r2, #3
    5976:	d104      	bne.n	5982 <sys_notify_validate+0x1c>
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		if (notify->method.callback == NULL) {
    5978:	6802      	ldr	r2, [r0, #0]
    597a:	b112      	cbz	r2, 5982 <sys_notify_validate+0x1c>
		break;
	}

	/* Clear the result here instead of in all callers. */
	if (rv == 0) {
		notify->result = 0;
    597c:	2000      	movs	r0, #0
    597e:	6098      	str	r0, [r3, #8]
    5980:	4770      	bx	lr
		return -EINVAL;
    5982:	f06f 0015 	mvn.w	r0, #21
	}

	return rv;
}
    5986:	4770      	bx	lr

00005988 <sys_notify_finalize>:
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    5988:	6842      	ldr	r2, [r0, #4]
	uint32_t method = sys_notify_get_method(notify);

	/* Store the result and capture secondary notification
	 * information.
	 */
	notify->result = res;
    598a:	6081      	str	r1, [r0, #8]
	return method & SYS_NOTIFY_METHOD_MASK;
    598c:	f002 0203 	and.w	r2, r2, #3
	switch (method) {
    5990:	2a03      	cmp	r2, #3
    5992:	f04f 0200 	mov.w	r2, #0
{
    5996:	4603      	mov	r3, r0
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		rv = notify->method.callback;
    5998:	bf0c      	ite	eq
    599a:	6800      	ldreq	r0, [r0, #0]
	sys_notify_generic_callback rv = NULL;
    599c:	4610      	movne	r0, r2
	/* Mark completion by clearing the flags field to the
	 * completed state, releasing any spin-waiters, then complete
	 * secondary notification.
	 */
	compiler_barrier();
	notify->flags = SYS_NOTIFY_METHOD_COMPLETED;
    599e:	605a      	str	r2, [r3, #4]
	if (IS_ENABLED(CONFIG_POLL) && (sig != NULL)) {
		k_poll_signal_raise(sig, res);
	}

	return rv;
}
    59a0:	4770      	bx	lr

000059a2 <arch_printk_char_out>:
}
    59a2:	2000      	movs	r0, #0
    59a4:	4770      	bx	lr

000059a6 <printk>:
 *
 * @param fmt formatted string to output
 */

void printk(const char *fmt, ...)
{
    59a6:	b40f      	push	{r0, r1, r2, r3}
    59a8:	b507      	push	{r0, r1, r2, lr}
    59aa:	a904      	add	r1, sp, #16
    59ac:	f851 0b04 	ldr.w	r0, [r1], #4
	va_list ap;

	va_start(ap, fmt);
    59b0:	9101      	str	r1, [sp, #4]

	vprintk(fmt, ap);
    59b2:	f7fb fe51 	bl	1658 <vprintk>

	va_end(ap);
}
    59b6:	b003      	add	sp, #12
    59b8:	f85d eb04 	ldr.w	lr, [sp], #4
    59bc:	b004      	add	sp, #16
    59be:	4770      	bx	lr

000059c0 <process_recheck>:
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    59c0:	8b03      	ldrh	r3, [r0, #24]
	if ((state == ONOFF_STATE_OFF)
    59c2:	f013 0307 	ands.w	r3, r3, #7
    59c6:	d105      	bne.n	59d4 <process_recheck+0x14>
	    && !sys_slist_is_empty(&mgr->clients)) {
    59c8:	6803      	ldr	r3, [r0, #0]
		evt = EVT_START;
    59ca:	2b00      	cmp	r3, #0
    59cc:	bf0c      	ite	eq
    59ce:	2000      	moveq	r0, #0
    59d0:	2003      	movne	r0, #3
    59d2:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ON)
    59d4:	2b02      	cmp	r3, #2
    59d6:	d105      	bne.n	59e4 <process_recheck+0x24>
		   && (mgr->refs == 0U)) {
    59d8:	8b43      	ldrh	r3, [r0, #26]
		evt = EVT_STOP;
    59da:	2b00      	cmp	r3, #0
    59dc:	bf14      	ite	ne
    59de:	2000      	movne	r0, #0
    59e0:	2004      	moveq	r0, #4
    59e2:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ERROR)
    59e4:	2b01      	cmp	r3, #1
    59e6:	d105      	bne.n	59f4 <process_recheck+0x34>
		   && !sys_slist_is_empty(&mgr->clients)) {
    59e8:	6803      	ldr	r3, [r0, #0]
		evt = EVT_RESET;
    59ea:	2b00      	cmp	r3, #0
    59ec:	bf0c      	ite	eq
    59ee:	2000      	moveq	r0, #0
    59f0:	2005      	movne	r0, #5
    59f2:	4770      	bx	lr
	int evt = EVT_NOP;
    59f4:	2000      	movs	r0, #0
}
    59f6:	4770      	bx	lr

000059f8 <notify_one>:
{
    59f8:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    59fc:	460d      	mov	r5, r1
    59fe:	4607      	mov	r7, r0
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    5a00:	4619      	mov	r1, r3
    5a02:	1d28      	adds	r0, r5, #4
{
    5a04:	4690      	mov	r8, r2
    5a06:	461e      	mov	r6, r3
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
    5a08:	f7ff ffbe 	bl	5988 <sys_notify_finalize>
	if (cb) {
    5a0c:	4604      	mov	r4, r0
    5a0e:	b138      	cbz	r0, 5a20 <notify_one+0x28>
		cb(mgr, cli, state, res);
    5a10:	4633      	mov	r3, r6
    5a12:	4642      	mov	r2, r8
    5a14:	4629      	mov	r1, r5
    5a16:	4638      	mov	r0, r7
    5a18:	46a4      	mov	ip, r4
}
    5a1a:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
		cb(mgr, cli, state, res);
    5a1e:	4760      	bx	ip
}
    5a20:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00005a24 <transition_complete>:
{
    5a24:	b410      	push	{r4}
    5a26:	f04f 0420 	mov.w	r4, #32
    5a2a:	f3ef 8211 	mrs	r2, BASEPRI
    5a2e:	f384 8812 	msr	BASEPRI_MAX, r4
    5a32:	f3bf 8f6f 	isb	sy
	mgr->last_res = res;
    5a36:	6141      	str	r1, [r0, #20]
}
    5a38:	bc10      	pop	{r4}
	process_event(mgr, EVT_COMPLETE, key);
    5a3a:	2101      	movs	r1, #1
    5a3c:	f7fb be1a 	b.w	1674 <process_event>

00005a40 <validate_args>:
{
    5a40:	b510      	push	{r4, lr}
    5a42:	460c      	mov	r4, r1
	if ((mgr == NULL) || (cli == NULL)) {
    5a44:	b140      	cbz	r0, 5a58 <validate_args+0x18>
    5a46:	b139      	cbz	r1, 5a58 <validate_args+0x18>
	int rv = sys_notify_validate(&cli->notify);
    5a48:	1d08      	adds	r0, r1, #4
    5a4a:	f7ff ff8c 	bl	5966 <sys_notify_validate>
	if ((rv == 0)
    5a4e:	b928      	cbnz	r0, 5a5c <validate_args+0x1c>
	    && ((cli->notify.flags
    5a50:	68a3      	ldr	r3, [r4, #8]
    5a52:	f033 0303 	bics.w	r3, r3, #3
    5a56:	d001      	beq.n	5a5c <validate_args+0x1c>
		rv = -EINVAL;
    5a58:	f06f 0015 	mvn.w	r0, #21
}
    5a5c:	bd10      	pop	{r4, pc}

00005a5e <onoff_manager_init>:
{
    5a5e:	b538      	push	{r3, r4, r5, lr}
    5a60:	460c      	mov	r4, r1
	if ((mgr == NULL)
    5a62:	4605      	mov	r5, r0
    5a64:	b158      	cbz	r0, 5a7e <onoff_manager_init+0x20>
	    || (transitions == NULL)
    5a66:	b151      	cbz	r1, 5a7e <onoff_manager_init+0x20>
	    || (transitions->start == NULL)
    5a68:	680b      	ldr	r3, [r1, #0]
    5a6a:	b143      	cbz	r3, 5a7e <onoff_manager_init+0x20>
	    || (transitions->stop == NULL)) {
    5a6c:	684b      	ldr	r3, [r1, #4]
    5a6e:	b133      	cbz	r3, 5a7e <onoff_manager_init+0x20>
	*mgr = (struct onoff_manager)ONOFF_MANAGER_INITIALIZER(transitions);
    5a70:	221c      	movs	r2, #28
    5a72:	2100      	movs	r1, #0
    5a74:	f000 f925 	bl	5cc2 <memset>
    5a78:	612c      	str	r4, [r5, #16]
	return 0;
    5a7a:	2000      	movs	r0, #0
}
    5a7c:	bd38      	pop	{r3, r4, r5, pc}
		return -EINVAL;
    5a7e:	f06f 0015 	mvn.w	r0, #21
    5a82:	e7fb      	b.n	5a7c <onoff_manager_init+0x1e>

00005a84 <onoff_request>:

int onoff_request(struct onoff_manager *mgr,
		  struct onoff_client *cli)
{
    5a84:	b570      	push	{r4, r5, r6, lr}
    5a86:	4604      	mov	r4, r0
    5a88:	460e      	mov	r6, r1
	bool add_client = false;        /* add client to pending list */
	bool start = false;             /* trigger a start transition */
	bool notify = false;            /* do client notification */
	int rv = validate_args(mgr, cli);
    5a8a:	f7ff ffd9 	bl	5a40 <validate_args>

	if (rv < 0) {
    5a8e:	1e05      	subs	r5, r0, #0
    5a90:	db31      	blt.n	5af6 <onoff_request+0x72>
    5a92:	f04f 0320 	mov.w	r3, #32
    5a96:	f3ef 8111 	mrs	r1, BASEPRI
    5a9a:	f383 8812 	msr	BASEPRI_MAX, r3
    5a9e:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&mgr->lock);
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;

	/* Reject if this would overflow the reference count. */
	if (mgr->refs == SERVICE_REFS_MAX) {
    5aa2:	8b63      	ldrh	r3, [r4, #26]
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    5aa4:	8b20      	ldrh	r0, [r4, #24]
	if (mgr->refs == SERVICE_REFS_MAX) {
    5aa6:	f64f 75ff 	movw	r5, #65535	; 0xffff
    5aaa:	42ab      	cmp	r3, r5
    5aac:	f000 0207 	and.w	r2, r0, #7
    5ab0:	d02e      	beq.n	5b10 <onoff_request+0x8c>
		rv = -EAGAIN;
		goto out;
	}

	rv = state;
	if (state == ONOFF_STATE_ON) {
    5ab2:	2a02      	cmp	r2, #2
    5ab4:	d10e      	bne.n	5ad4 <onoff_request+0x50>
		/* Increment reference count, notify in exit */
		notify = true;
		mgr->refs += 1U;
    5ab6:	3301      	adds	r3, #1
    5ab8:	8363      	strh	r3, [r4, #26]
	rv = state;
    5aba:	4615      	mov	r5, r2
		notify = true;
    5abc:	2301      	movs	r3, #1
	__asm__ volatile(
    5abe:	f381 8811 	msr	BASEPRI, r1
    5ac2:	f3bf 8f6f 	isb	sy
	if (start) {
		process_event(mgr, EVT_RECHECK, key);
	} else {
		k_spin_unlock(&mgr->lock, key);

		if (notify) {
    5ac6:	b1b3      	cbz	r3, 5af6 <onoff_request+0x72>
			notify_one(mgr, cli, state, 0);
    5ac8:	2300      	movs	r3, #0
    5aca:	4631      	mov	r1, r6
    5acc:	4620      	mov	r0, r4
    5ace:	f7ff ff93 	bl	59f8 <notify_one>
    5ad2:	e010      	b.n	5af6 <onoff_request+0x72>
	} else if ((state == ONOFF_STATE_OFF)
    5ad4:	0783      	lsls	r3, r0, #30
    5ad6:	d001      	beq.n	5adc <onoff_request+0x58>
		   || (state == ONOFF_STATE_TO_ON)) {
    5ad8:	2a06      	cmp	r2, #6
    5ada:	d10e      	bne.n	5afa <onoff_request+0x76>
	parent->next = child;
    5adc:	2300      	movs	r3, #0
    5ade:	6033      	str	r3, [r6, #0]
 *
 * @return A pointer on the last node of the list (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_tail(sys_slist_t *list)
{
	return list->tail;
    5ae0:	6863      	ldr	r3, [r4, #4]
 * @param node A pointer on the node to append
 */
static inline void sys_slist_append(sys_slist_t *list,
				    sys_snode_t *node);

Z_GENLIST_APPEND(slist, snode)
    5ae2:	b993      	cbnz	r3, 5b0a <onoff_request+0x86>
	list->head = node;
    5ae4:	e9c4 6600 	strd	r6, r6, [r4]
	if (start) {
    5ae8:	4615      	mov	r5, r2
    5aea:	b962      	cbnz	r2, 5b06 <onoff_request+0x82>
		process_event(mgr, EVT_RECHECK, key);
    5aec:	460a      	mov	r2, r1
    5aee:	4620      	mov	r0, r4
    5af0:	2102      	movs	r1, #2
    5af2:	f7fb fdbf 	bl	1674 <process_event>
		}
	}

	return rv;
}
    5af6:	4628      	mov	r0, r5
    5af8:	bd70      	pop	{r4, r5, r6, pc}
		rv = -EIO;
    5afa:	2a05      	cmp	r2, #5
    5afc:	bf0c      	ite	eq
    5afe:	f06f 0585 	mvneq.w	r5, #133	; 0x85
    5b02:	f06f 0504 	mvnne.w	r5, #4
    5b06:	2300      	movs	r3, #0
    5b08:	e7d9      	b.n	5abe <onoff_request+0x3a>
	parent->next = child;
    5b0a:	601e      	str	r6, [r3, #0]
	list->tail = node;
    5b0c:	6066      	str	r6, [r4, #4]
}
    5b0e:	e7eb      	b.n	5ae8 <onoff_request+0x64>
		rv = -EAGAIN;
    5b10:	f06f 050a 	mvn.w	r5, #10
    5b14:	e7f7      	b.n	5b06 <onoff_request+0x82>

00005b16 <_ConfigAbsSyms>:
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_BUILD_OUTPUT_BIN, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_BUILD_OUTPUT_META, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_COMPAT_INCLUDES, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_LEGACY_INCLUDE_PATH, 1);

GEN_ABS_SYM_END
    5b16:	4770      	bx	lr

00005b18 <z_log_minimal_printk>:
#include <sys/printk.h>

#define HEXDUMP_BYTES_IN_LINE 8U

void z_log_minimal_printk(const char *fmt, ...)
{
    5b18:	b40f      	push	{r0, r1, r2, r3}
    5b1a:	b507      	push	{r0, r1, r2, lr}
    5b1c:	a904      	add	r1, sp, #16
    5b1e:	f851 0b04 	ldr.w	r0, [r1], #4
	va_list ap;

	va_start(ap, fmt);
    5b22:	9101      	str	r1, [sp, #4]
	vprintk(fmt, ap);
    5b24:	f7fb fd98 	bl	1658 <vprintk>
	va_end(ap);
}
    5b28:	b003      	add	sp, #12
    5b2a:	f85d eb04 	ldr.w	lr, [sp], #4
    5b2e:	b004      	add	sp, #16
    5b30:	4770      	bx	lr

00005b32 <flash_area_close>:

void flash_area_close(const struct flash_area *fa)
{
	/* nothing to do for now */
}
    5b32:	4770      	bx	lr

00005b34 <flash_area_read>:

int flash_area_read(const struct flash_area *fa, off_t off, void *dst,
		    size_t len)
{
    5b34:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}


static inline bool is_in_flash_area_bounds(const struct flash_area *fa,
					   off_t off, size_t len)
{
	return (off >= 0) && ((off + len) <= fa->fa_size);
    5b38:	1e0c      	subs	r4, r1, #0
    5b3a:	4605      	mov	r5, r0
    5b3c:	4617      	mov	r7, r2
    5b3e:	461e      	mov	r6, r3
    5b40:	db10      	blt.n	5b64 <flash_area_read+0x30>
    5b42:	6882      	ldr	r2, [r0, #8]
    5b44:	18e3      	adds	r3, r4, r3
    5b46:	4293      	cmp	r3, r2
    5b48:	d80c      	bhi.n	5b64 <flash_area_read+0x30>

	if (!is_in_flash_area_bounds(fa, off, len)) {
		return -EINVAL;
	}

	dev = device_get_binding(fa->fa_dev_name);
    5b4a:	68c0      	ldr	r0, [r0, #12]
    5b4c:	f7fe fbce 	bl	42ec <z_impl_device_get_binding>

	return flash_read(dev, fa->fa_off + off, dst, len);
    5b50:	6869      	ldr	r1, [r5, #4]
    5b52:	4421      	add	r1, r4
				    size_t len)
{
	const struct flash_driver_api *api =
		(const struct flash_driver_api *)dev->api;

	return api->read(dev, offset, data, len);
    5b54:	6883      	ldr	r3, [r0, #8]
    5b56:	681c      	ldr	r4, [r3, #0]
    5b58:	463a      	mov	r2, r7
    5b5a:	4633      	mov	r3, r6
    5b5c:	46a4      	mov	ip, r4
}
    5b5e:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
    5b62:	4760      	bx	ip
    5b64:	f06f 0015 	mvn.w	r0, #21
    5b68:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00005b6c <flash_area_write>:

int flash_area_write(const struct flash_area *fa, off_t off, const void *src,
		     size_t len)
{
    5b6c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    5b70:	1e0c      	subs	r4, r1, #0
    5b72:	4605      	mov	r5, r0
    5b74:	4617      	mov	r7, r2
    5b76:	461e      	mov	r6, r3
    5b78:	db10      	blt.n	5b9c <flash_area_write+0x30>
    5b7a:	6882      	ldr	r2, [r0, #8]
    5b7c:	18e3      	adds	r3, r4, r3
    5b7e:	4293      	cmp	r3, r2
    5b80:	d80c      	bhi.n	5b9c <flash_area_write+0x30>

	if (!is_in_flash_area_bounds(fa, off, len)) {
		return -EINVAL;
	}

	flash_dev = device_get_binding(fa->fa_dev_name);
    5b82:	68c0      	ldr	r0, [r0, #12]
    5b84:	f7fe fbb2 	bl	42ec <z_impl_device_get_binding>

	rc = flash_write(flash_dev, fa->fa_off + off, (void *)src, len);
    5b88:	6869      	ldr	r1, [r5, #4]
    5b8a:	4421      	add	r1, r4
{
	const struct flash_driver_api *api =
		(const struct flash_driver_api *)dev->api;
	int rc;

	rc = api->write(dev, offset, data, len);
    5b8c:	6883      	ldr	r3, [r0, #8]
    5b8e:	685c      	ldr	r4, [r3, #4]
    5b90:	463a      	mov	r2, r7
    5b92:	4633      	mov	r3, r6
    5b94:	46a4      	mov	ip, r4

	return rc;
}
    5b96:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
    5b9a:	4760      	bx	ip
    5b9c:	f06f 0015 	mvn.w	r0, #21
    5ba0:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00005ba4 <flash_area_erase>:

int flash_area_erase(const struct flash_area *fa, off_t off, size_t len)
{
    5ba4:	b570      	push	{r4, r5, r6, lr}
    5ba6:	1e0c      	subs	r4, r1, #0
    5ba8:	4605      	mov	r5, r0
    5baa:	4616      	mov	r6, r2
    5bac:	db0e      	blt.n	5bcc <flash_area_erase+0x28>
    5bae:	18a3      	adds	r3, r4, r2
    5bb0:	6882      	ldr	r2, [r0, #8]
    5bb2:	4293      	cmp	r3, r2
    5bb4:	d80a      	bhi.n	5bcc <flash_area_erase+0x28>

	if (!is_in_flash_area_bounds(fa, off, len)) {
		return -EINVAL;
	}

	flash_dev = device_get_binding(fa->fa_dev_name);
    5bb6:	68c0      	ldr	r0, [r0, #12]
    5bb8:	f7fe fb98 	bl	42ec <z_impl_device_get_binding>

	rc = flash_erase(flash_dev, fa->fa_off + off, len);
    5bbc:	6869      	ldr	r1, [r5, #4]
    5bbe:	4421      	add	r1, r4
{
	const struct flash_driver_api *api =
		(const struct flash_driver_api *)dev->api;
	int rc;

	rc = api->erase(dev, offset, size);
    5bc0:	6883      	ldr	r3, [r0, #8]
    5bc2:	4632      	mov	r2, r6
    5bc4:	689b      	ldr	r3, [r3, #8]

	return rc;
}
    5bc6:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
    5bca:	4718      	bx	r3
    5bcc:	f06f 0015 	mvn.w	r0, #21
    5bd0:	bd70      	pop	{r4, r5, r6, pc}

00005bd2 <flash_area_align>:

uint32_t flash_area_align(const struct flash_area *fa)
{
    5bd2:	b508      	push	{r3, lr}
	const struct device *dev;

	dev = device_get_binding(fa->fa_dev_name);
    5bd4:	68c0      	ldr	r0, [r0, #12]
    5bd6:	f7fe fb89 	bl	42ec <z_impl_device_get_binding>
static inline size_t z_impl_flash_get_write_block_size(const struct device *dev)
{
	const struct flash_driver_api *api =
		(const struct flash_driver_api *)dev->api;

	return api->get_parameters(dev)->write_block_size;
    5bda:	6883      	ldr	r3, [r0, #8]
    5bdc:	68db      	ldr	r3, [r3, #12]
    5bde:	4798      	blx	r3

	return flash_get_write_block_size(dev);
}
    5be0:	6800      	ldr	r0, [r0, #0]
    5be2:	bd08      	pop	{r3, pc}

00005be4 <flash_area_erased_val>:
{
	return device_get_binding(fa->fa_dev_name);
}

uint8_t flash_area_erased_val(const struct flash_area *fa)
{
    5be4:	b508      	push	{r3, lr}
	const struct flash_parameters *param;

	param = flash_get_parameters(device_get_binding(fa->fa_dev_name));
    5be6:	68c0      	ldr	r0, [r0, #12]
    5be8:	f7fe fb80 	bl	42ec <z_impl_device_get_binding>
static inline const struct flash_parameters *z_impl_flash_get_parameters(const struct device *dev)
{
	const struct flash_driver_api *api =
		(const struct flash_driver_api *)dev->api;

	return api->get_parameters(dev);
    5bec:	6883      	ldr	r3, [r0, #8]
    5bee:	68db      	ldr	r3, [r3, #12]
    5bf0:	4798      	blx	r3

	return param->erase_value;
}
    5bf2:	7900      	ldrb	r0, [r0, #4]
    5bf4:	bd08      	pop	{r3, pc}

00005bf6 <get_sectors_cb>:
{
    5bf6:	b570      	push	{r4, r5, r6, lr}
	if (info->start_offset < data->area_off) {
    5bf8:	6802      	ldr	r2, [r0, #0]
    5bfa:	684c      	ldr	r4, [r1, #4]
    5bfc:	42a2      	cmp	r2, r4
    5bfe:	d316      	bcc.n	5c2e <get_sectors_cb+0x38>
	} else if (info->start_offset >= data->area_off + data->area_len) {
    5c00:	688b      	ldr	r3, [r1, #8]
    5c02:	4423      	add	r3, r4
    5c04:	429a      	cmp	r2, r3
    5c06:	d206      	bcs.n	5c16 <get_sectors_cb+0x20>
	} else if (data->ret_idx >= data->ret_len) {
    5c08:	e9d1 3504 	ldrd	r3, r5, [r1, #16]
    5c0c:	42ab      	cmp	r3, r5
    5c0e:	d304      	bcc.n	5c1a <get_sectors_cb+0x24>
		data->status = -ENOMEM;
    5c10:	f06f 030b 	mvn.w	r3, #11
    5c14:	618b      	str	r3, [r1, #24]
		*bail_value = false;
    5c16:	2000      	movs	r0, #0
    5c18:	e00a      	b.n	5c30 <get_sectors_cb+0x3a>
	ret[data->ret_idx].fs_off = info->start_offset - data->area_off;
    5c1a:	68cd      	ldr	r5, [r1, #12]
    5c1c:	1b12      	subs	r2, r2, r4
    5c1e:	eb05 06c3 	add.w	r6, r5, r3, lsl #3
    5c22:	f845 2033 	str.w	r2, [r5, r3, lsl #3]
	ret[data->ret_idx].fs_size = info->size;
    5c26:	6842      	ldr	r2, [r0, #4]
    5c28:	6072      	str	r2, [r6, #4]
	data->ret_idx++;
    5c2a:	3301      	adds	r3, #1
    5c2c:	610b      	str	r3, [r1, #16]
		*bail_value = true;
    5c2e:	2001      	movs	r0, #1
}
    5c30:	bd70      	pop	{r4, r5, r6, pc}

00005c32 <z_do_kernel_oops>:
 *   fault handler will executed instead of the SVC.
 *
 * @param esf exception frame
 */
void z_do_kernel_oops(const z_arch_esf_t *esf)
{
    5c32:	4601      	mov	r1, r0
	}

#endif /* CONFIG_USERSPACE */

#if !defined(CONFIG_EXTRA_EXCEPTION_INFO)
	z_arm_fatal_error(reason, esf);
    5c34:	6800      	ldr	r0, [r0, #0]
    5c36:	f7fc b88d 	b.w	1d54 <z_arm_fatal_error>

00005c3a <z_irq_spurious>:
 */
void z_irq_spurious(const void *unused)
{
	ARG_UNUSED(unused);

	z_arm_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
    5c3a:	2100      	movs	r1, #0
    5c3c:	2001      	movs	r0, #1
    5c3e:	f7fc b889 	b.w	1d54 <z_arm_fatal_error>

00005c42 <z_arm_nmi>:
 * Simply call what is installed in 'static void(*handler)(void)'.
 *
 */

void z_arm_nmi(void)
{
    5c42:	b508      	push	{r3, lr}
	handler();
    5c44:	f7fc f8ea 	bl	1e1c <z_SysNmiOnReset>
	z_arm_int_exit();
}
    5c48:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	z_arm_int_exit();
    5c4c:	f7fc b958 	b.w	1f00 <z_arm_exc_exit>

00005c50 <strcpy>:

char *strcpy(char *ZRESTRICT d, const char *ZRESTRICT s)
{
	char *dest = d;

	while (*s != '\0') {
    5c50:	3901      	subs	r1, #1
    5c52:	4603      	mov	r3, r0
    5c54:	f811 2f01 	ldrb.w	r2, [r1, #1]!
    5c58:	b90a      	cbnz	r2, 5c5e <strcpy+0xe>
		*d = *s;
		d++;
		s++;
	}

	*d = '\0';
    5c5a:	701a      	strb	r2, [r3, #0]

	return dest;
}
    5c5c:	4770      	bx	lr
		*d = *s;
    5c5e:	f803 2b01 	strb.w	r2, [r3], #1
		s++;
    5c62:	e7f7      	b.n	5c54 <strcpy+0x4>

00005c64 <strlen>:
 *
 * @return number of bytes in string <s>
 */

size_t strlen(const char *s)
{
    5c64:	4603      	mov	r3, r0
	size_t n = 0;
    5c66:	2000      	movs	r0, #0

	while (*s != '\0') {
    5c68:	5c1a      	ldrb	r2, [r3, r0]
    5c6a:	b902      	cbnz	r2, 5c6e <strlen+0xa>
		s++;
		n++;
	}

	return n;
}
    5c6c:	4770      	bx	lr
		n++;
    5c6e:	3001      	adds	r0, #1
    5c70:	e7fa      	b.n	5c68 <strlen+0x4>

00005c72 <strcmp>:
 * @return negative # if <s1> < <s2>, 0 if <s1> == <s2>, else positive #
 */

int strcmp(const char *s1, const char *s2)
{
	while ((*s1 == *s2) && (*s1 != '\0')) {
    5c72:	1e43      	subs	r3, r0, #1
    5c74:	3901      	subs	r1, #1
    5c76:	f813 2f01 	ldrb.w	r2, [r3, #1]!
    5c7a:	f811 0f01 	ldrb.w	r0, [r1, #1]!
    5c7e:	4282      	cmp	r2, r0
    5c80:	d101      	bne.n	5c86 <strcmp+0x14>
    5c82:	2a00      	cmp	r2, #0
    5c84:	d1f7      	bne.n	5c76 <strcmp+0x4>
		s1++;
		s2++;
	}

	return *s1 - *s2;
}
    5c86:	1a10      	subs	r0, r2, r0
    5c88:	4770      	bx	lr

00005c8a <memcmp>:
 * @brief Compare two memory areas
 *
 * @return negative # if <m1> < <m2>, 0 if <m1> == <m2>, else positive #
 */
int memcmp(const void *m1, const void *m2, size_t n)
{
    5c8a:	b510      	push	{r4, lr}
    5c8c:	4603      	mov	r3, r0
	const char *c1 = m1;
	const char *c2 = m2;

	if (!n) {
    5c8e:	b15a      	cbz	r2, 5ca8 <memcmp+0x1e>
    5c90:	3901      	subs	r1, #1
    5c92:	1884      	adds	r4, r0, r2
		return 0;
	}

	while ((--n > 0) && (*c1 == *c2)) {
    5c94:	f813 0b01 	ldrb.w	r0, [r3], #1
    5c98:	f811 2f01 	ldrb.w	r2, [r1, #1]!
    5c9c:	42a3      	cmp	r3, r4
    5c9e:	d001      	beq.n	5ca4 <memcmp+0x1a>
    5ca0:	4290      	cmp	r0, r2
    5ca2:	d0f7      	beq.n	5c94 <memcmp+0xa>
		c1++;
		c2++;
	}

	return *c1 - *c2;
    5ca4:	1a80      	subs	r0, r0, r2
}
    5ca6:	bd10      	pop	{r4, pc}
		return 0;
    5ca8:	4610      	mov	r0, r2
    5caa:	e7fc      	b.n	5ca6 <memcmp+0x1c>

00005cac <memcpy>:
 *
 * @return pointer to start of destination buffer
 */

void *memcpy(void *ZRESTRICT d, const void *ZRESTRICT s, size_t n)
{
    5cac:	b510      	push	{r4, lr}
    5cae:	1e43      	subs	r3, r0, #1
    5cb0:	440a      	add	r2, r1
	}
#endif

	/* do byte-sized copying until finished */

	while (n > 0) {
    5cb2:	4291      	cmp	r1, r2
    5cb4:	d100      	bne.n	5cb8 <memcpy+0xc>
		*(d_byte++) = *(s_byte++);
		n--;
	}

	return d;
}
    5cb6:	bd10      	pop	{r4, pc}
		*(d_byte++) = *(s_byte++);
    5cb8:	f811 4b01 	ldrb.w	r4, [r1], #1
    5cbc:	f803 4f01 	strb.w	r4, [r3, #1]!
		n--;
    5cc0:	e7f7      	b.n	5cb2 <memcpy+0x6>

00005cc2 <memset>:
void *memset(void *buf, int c, size_t n)
{
	/* do byte-sized initialization until word-aligned or finished */

	unsigned char *d_byte = (unsigned char *)buf;
	unsigned char c_byte = (unsigned char)c;
    5cc2:	b2c9      	uxtb	r1, r1
	/* do byte-sized initialization until finished */

	d_byte = (unsigned char *)d_word;
#endif

	while (n > 0) {
    5cc4:	4402      	add	r2, r0
	unsigned char *d_byte = (unsigned char *)buf;
    5cc6:	4603      	mov	r3, r0
	while (n > 0) {
    5cc8:	4293      	cmp	r3, r2
    5cca:	d100      	bne.n	5cce <memset+0xc>
		*(d_byte++) = c_byte;
		n--;
	}

	return buf;
}
    5ccc:	4770      	bx	lr
		*(d_byte++) = c_byte;
    5cce:	f803 1b01 	strb.w	r1, [r3], #1
		n--;
    5cd2:	e7f9      	b.n	5cc8 <memset+0x6>

00005cd4 <_stdout_hook_default>:
}
    5cd4:	f04f 30ff 	mov.w	r0, #4294967295
    5cd8:	4770      	bx	lr

00005cda <get_status>:
	return GET_STATUS(get_sub_data(dev, type)->flags);
    5cda:	6903      	ldr	r3, [r0, #16]
    5cdc:	b2c9      	uxtb	r1, r1
    5cde:	220c      	movs	r2, #12
    5ce0:	fb01 3302 	mla	r3, r1, r2, r3
    5ce4:	6c18      	ldr	r0, [r3, #64]	; 0x40
}
    5ce6:	f000 0007 	and.w	r0, r0, #7
    5cea:	4770      	bx	lr

00005cec <set_on_state>:
	__asm__ volatile(
    5cec:	f04f 0320 	mov.w	r3, #32
    5cf0:	f3ef 8211 	mrs	r2, BASEPRI
    5cf4:	f383 8812 	msr	BASEPRI_MAX, r3
    5cf8:	f3bf 8f6f 	isb	sy
	*flags = CLOCK_CONTROL_STATUS_ON | GET_CTX(*flags);
    5cfc:	6803      	ldr	r3, [r0, #0]
    5cfe:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
    5d02:	f043 0302 	orr.w	r3, r3, #2
    5d06:	6003      	str	r3, [r0, #0]
	__asm__ volatile(
    5d08:	f382 8811 	msr	BASEPRI, r2
    5d0c:	f3bf 8f6f 	isb	sy
}
    5d10:	4770      	bx	lr

00005d12 <stop>:
{
    5d12:	4603      	mov	r3, r0
    5d14:	b570      	push	{r4, r5, r6, lr}
	struct nrf_clock_control_data *data = dev->data;
    5d16:	6900      	ldr	r0, [r0, #16]
	return &data->subsys[type];
    5d18:	b2c9      	uxtb	r1, r1
	__asm__ volatile(
    5d1a:	f04f 0420 	mov.w	r4, #32
    5d1e:	f3ef 8611 	mrs	r6, BASEPRI
    5d22:	f384 8812 	msr	BASEPRI_MAX, r4
    5d26:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    5d2a:	250c      	movs	r5, #12
    5d2c:	fb05 0401 	mla	r4, r5, r1, r0
    5d30:	6c24      	ldr	r4, [r4, #64]	; 0x40
	if ((current_ctx != 0) && (current_ctx != ctx)) {
    5d32:	f014 04c0 	ands.w	r4, r4, #192	; 0xc0
    5d36:	d001      	beq.n	5d3c <stop+0x2a>
    5d38:	42a2      	cmp	r2, r4
    5d3a:	d111      	bne.n	5d60 <stop+0x4e>
		*flags = CLOCK_CONTROL_STATUS_OFF;
    5d3c:	fb05 0001 	mla	r0, r5, r1, r0
    5d40:	2201      	movs	r2, #1
    5d42:	6402      	str	r2, [r0, #64]	; 0x40
	int err = 0;
    5d44:	2000      	movs	r0, #0
	__asm__ volatile(
    5d46:	f386 8811 	msr	BASEPRI, r6
    5d4a:	f3bf 8f6f 	isb	sy
	if (err < 0) {
    5d4e:	b930      	cbnz	r0, 5d5e <stop+0x4c>
	get_sub_config(dev, type)->stop();
    5d50:	685b      	ldr	r3, [r3, #4]
    5d52:	220c      	movs	r2, #12
    5d54:	fb02 3101 	mla	r1, r2, r1, r3
    5d58:	684b      	ldr	r3, [r1, #4]
    5d5a:	4798      	blx	r3
	return 0;
    5d5c:	2000      	movs	r0, #0
}
    5d5e:	bd70      	pop	{r4, r5, r6, pc}
		err = -EPERM;
    5d60:	f04f 30ff 	mov.w	r0, #4294967295
    5d64:	e7ef      	b.n	5d46 <stop+0x34>

00005d66 <api_stop>:
	return stop(dev, subsys, CTX_API);
    5d66:	2280      	movs	r2, #128	; 0x80
    5d68:	f7ff bfd3 	b.w	5d12 <stop>

00005d6c <async_start>:
{
    5d6c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    5d6e:	9f06      	ldr	r7, [sp, #24]
	struct nrf_clock_control_data *data = dev->data;
    5d70:	6904      	ldr	r4, [r0, #16]
{
    5d72:	4605      	mov	r5, r0
    5d74:	b2c9      	uxtb	r1, r1
	__asm__ volatile(
    5d76:	f04f 0020 	mov.w	r0, #32
    5d7a:	f3ef 8c11 	mrs	ip, BASEPRI
    5d7e:	f380 8812 	msr	BASEPRI_MAX, r0
    5d82:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
    5d86:	260c      	movs	r6, #12
    5d88:	fb06 4601 	mla	r6, r6, r1, r4
    5d8c:	6c30      	ldr	r0, [r6, #64]	; 0x40
	if ((*flags & (STATUS_MASK)) == CLOCK_CONTROL_STATUS_OFF) {
    5d8e:	f000 0e07 	and.w	lr, r0, #7
    5d92:	f1be 0f01 	cmp.w	lr, #1
    5d96:	d110      	bne.n	5dba <async_start+0x4e>
		*flags = CLOCK_CONTROL_STATUS_STARTING | ctx;
    5d98:	6437      	str	r7, [r6, #64]	; 0x40
	int err = 0;
    5d9a:	2600      	movs	r6, #0
	__asm__ volatile(
    5d9c:	f38c 8811 	msr	BASEPRI, ip
    5da0:	f3bf 8f6f 	isb	sy
	if (err < 0) {
    5da4:	b93e      	cbnz	r6, 5db6 <async_start+0x4a>
	subdata->cb = cb;
    5da6:	200c      	movs	r0, #12
    5da8:	4341      	muls	r1, r0
    5daa:	440c      	add	r4, r1
	subdata->user_data = user_data;
    5dac:	e9c4 230e 	strd	r2, r3, [r4, #56]	; 0x38
	 get_sub_config(dev, type)->start();
    5db0:	686b      	ldr	r3, [r5, #4]
    5db2:	585b      	ldr	r3, [r3, r1]
    5db4:	4798      	blx	r3
}
    5db6:	4630      	mov	r0, r6
    5db8:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	uint32_t current_ctx = GET_CTX(*flags);
    5dba:	f000 00c0 	and.w	r0, r0, #192	; 0xc0
		err = -EALREADY;
    5dbe:	4287      	cmp	r7, r0
    5dc0:	bf14      	ite	ne
    5dc2:	f04f 36ff 	movne.w	r6, #4294967295
    5dc6:	f06f 0677 	mvneq.w	r6, #119	; 0x77
    5dca:	e7e7      	b.n	5d9c <async_start+0x30>

00005dcc <api_start>:
{
    5dcc:	b513      	push	{r0, r1, r4, lr}
	return async_start(dev, subsys, cb, user_data, CTX_API);
    5dce:	2480      	movs	r4, #128	; 0x80
    5dd0:	9400      	str	r4, [sp, #0]
    5dd2:	f7ff ffcb 	bl	5d6c <async_start>
}
    5dd6:	b002      	add	sp, #8
    5dd8:	bd10      	pop	{r4, pc}

00005dda <api_blocking_start>:
}
    5dda:	f06f 0085 	mvn.w	r0, #133	; 0x85
    5dde:	4770      	bx	lr

00005de0 <onoff_started_callback>:
	return &data->mgr[type];
    5de0:	6900      	ldr	r0, [r0, #16]
{
    5de2:	b410      	push	{r4}
	return &data->mgr[type];
    5de4:	b2cb      	uxtb	r3, r1
	notify(mgr, 0);
    5de6:	241c      	movs	r4, #28
    5de8:	fb03 0004 	mla	r0, r3, r4, r0
    5dec:	2100      	movs	r1, #0
}
    5dee:	bc10      	pop	{r4}
	notify(mgr, 0);
    5df0:	4710      	bx	r2

00005df2 <lfclk_stop>:
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
    5df2:	2000      	movs	r0, #0
    5df4:	f000 bad8 	b.w	63a8 <nrfx_clock_stop>

00005df8 <gpio_nrfx_port_get_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    5df8:	6843      	ldr	r3, [r0, #4]
    5dfa:	685b      	ldr	r3, [r3, #4]
    return p_reg->IN;
    5dfc:	f8d3 3510 	ldr.w	r3, [r3, #1296]	; 0x510
	*value = nrf_gpio_port_in_read(reg);
    5e00:	600b      	str	r3, [r1, #0]
}
    5e02:	2000      	movs	r0, #0
    5e04:	4770      	bx	lr

00005e06 <gpio_nrfx_port_set_masked_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    5e06:	6843      	ldr	r3, [r0, #4]
    5e08:	685b      	ldr	r3, [r3, #4]
    return p_reg->OUT;
    5e0a:	f8d3 0504 	ldr.w	r0, [r3, #1284]	; 0x504
	nrf_gpio_port_out_write(reg, value_tmp | (mask & value));
    5e0e:	4042      	eors	r2, r0
    5e10:	400a      	ands	r2, r1
    5e12:	4042      	eors	r2, r0
    p_reg->OUT = value;
    5e14:	f8c3 2504 	str.w	r2, [r3, #1284]	; 0x504
}
    5e18:	2000      	movs	r0, #0
    5e1a:	4770      	bx	lr

00005e1c <gpio_nrfx_port_set_bits_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    5e1c:	6843      	ldr	r3, [r0, #4]
    5e1e:	685b      	ldr	r3, [r3, #4]
}
    5e20:	2000      	movs	r0, #0
    p_reg->OUTSET = set_mask;
    5e22:	f8c3 1508 	str.w	r1, [r3, #1288]	; 0x508
    5e26:	4770      	bx	lr

00005e28 <gpio_nrfx_port_clear_bits_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    5e28:	6843      	ldr	r3, [r0, #4]
    5e2a:	685b      	ldr	r3, [r3, #4]
}
    5e2c:	2000      	movs	r0, #0
    p_reg->OUTCLR = clr_mask;
    5e2e:	f8c3 150c 	str.w	r1, [r3, #1292]	; 0x50c
    5e32:	4770      	bx	lr

00005e34 <gpio_nrfx_port_toggle_bits>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
    5e34:	6843      	ldr	r3, [r0, #4]
    5e36:	685a      	ldr	r2, [r3, #4]
    return p_reg->OUT;
    5e38:	f8d2 3504 	ldr.w	r3, [r2, #1284]	; 0x504
	nrf_gpio_port_out_write(reg, value ^ mask);
    5e3c:	404b      	eors	r3, r1
    p_reg->OUT = value;
    5e3e:	f8c2 3504 	str.w	r3, [r2, #1284]	; 0x504
}
    5e42:	2000      	movs	r0, #0
    5e44:	4770      	bx	lr

00005e46 <gpio_nrfx_manage_callback>:
	return port->data;
    5e46:	6903      	ldr	r3, [r0, #16]
	return list->head;
    5e48:	6858      	ldr	r0, [r3, #4]
{
    5e4a:	b530      	push	{r4, r5, lr}
	if (!sys_slist_is_empty(callbacks)) {
    5e4c:	b158      	cbz	r0, 5e66 <gpio_nrfx_manage_callback+0x20>
 */
static inline bool sys_slist_find_and_remove(sys_slist_t *list,
					     sys_snode_t *node);

/** @} */
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    5e4e:	2400      	movs	r4, #0
    5e50:	4281      	cmp	r1, r0
    5e52:	d112      	bne.n	5e7a <gpio_nrfx_manage_callback+0x34>
	return node->next;
    5e54:	6808      	ldr	r0, [r1, #0]
	return list->tail;
    5e56:	689d      	ldr	r5, [r3, #8]
Z_GENLIST_REMOVE(slist, snode)
    5e58:	b954      	cbnz	r4, 5e70 <gpio_nrfx_manage_callback+0x2a>
    5e5a:	428d      	cmp	r5, r1
	list->head = node;
    5e5c:	6058      	str	r0, [r3, #4]
Z_GENLIST_REMOVE(slist, snode)
    5e5e:	d100      	bne.n	5e62 <gpio_nrfx_manage_callback+0x1c>
	list->tail = node;
    5e60:	6098      	str	r0, [r3, #8]
	parent->next = child;
    5e62:	2000      	movs	r0, #0
    5e64:	6008      	str	r0, [r1, #0]
	if (set) {
    5e66:	b96a      	cbnz	r2, 5e84 <gpio_nrfx_manage_callback+0x3e>
	return 0;
    5e68:	2000      	movs	r0, #0
}
    5e6a:	bd30      	pop	{r4, r5, pc}
    5e6c:	4628      	mov	r0, r5
    5e6e:	e7ef      	b.n	5e50 <gpio_nrfx_manage_callback+0xa>
Z_GENLIST_REMOVE(slist, snode)
    5e70:	428d      	cmp	r5, r1
	parent->next = child;
    5e72:	6020      	str	r0, [r4, #0]
	list->tail = node;
    5e74:	bf08      	it	eq
    5e76:	609c      	streq	r4, [r3, #8]
}
    5e78:	e7f3      	b.n	5e62 <gpio_nrfx_manage_callback+0x1c>
	return node->next;
    5e7a:	6805      	ldr	r5, [r0, #0]
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
    5e7c:	4604      	mov	r4, r0
    5e7e:	2d00      	cmp	r5, #0
    5e80:	d1f4      	bne.n	5e6c <gpio_nrfx_manage_callback+0x26>
			if (!set) {
    5e82:	b13a      	cbz	r2, 5e94 <gpio_nrfx_manage_callback+0x4e>
Z_GENLIST_PREPEND(slist, snode)
    5e84:	6898      	ldr	r0, [r3, #8]
	parent->next = child;
    5e86:	685a      	ldr	r2, [r3, #4]
    5e88:	600a      	str	r2, [r1, #0]
	list->head = node;
    5e8a:	6059      	str	r1, [r3, #4]
Z_GENLIST_PREPEND(slist, snode)
    5e8c:	2800      	cmp	r0, #0
    5e8e:	d1eb      	bne.n	5e68 <gpio_nrfx_manage_callback+0x22>
	list->tail = node;
    5e90:	6099      	str	r1, [r3, #8]
}
    5e92:	e7ea      	b.n	5e6a <gpio_nrfx_manage_callback+0x24>
				return -EINVAL;
    5e94:	f06f 0015 	mvn.w	r0, #21
	return gpio_manage_callback(&get_port_data(port)->callbacks,
    5e98:	e7e7      	b.n	5e6a <gpio_nrfx_manage_callback+0x24>

00005e9a <is_regular_addr_valid>:
{
    5e9a:	b538      	push	{r3, r4, r5, lr}
    5e9c:	4605      	mov	r5, r0
    5e9e:	460c      	mov	r4, r1
	return is_within_bounds(addr, len, 0, nrfx_nvmc_flash_size_get());
    5ea0:	f000 fa92 	bl	63c8 <nrfx_nvmc_flash_size_get>
			(addr < (boundary_start + boundary_size)) &&
    5ea4:	2d00      	cmp	r5, #0
    5ea6:	db07      	blt.n	5eb8 <is_regular_addr_valid+0x1e>
	return (addr >= boundary_start &&
    5ea8:	42a8      	cmp	r0, r5
    5eaa:	d905      	bls.n	5eb8 <is_regular_addr_valid+0x1e>
			(len <= (boundary_start + boundary_size - addr)));
    5eac:	1b40      	subs	r0, r0, r5
			(addr < (boundary_start + boundary_size)) &&
    5eae:	4284      	cmp	r4, r0
    5eb0:	bf8c      	ite	hi
    5eb2:	2000      	movhi	r0, #0
    5eb4:	2001      	movls	r0, #1
}
    5eb6:	bd38      	pop	{r3, r4, r5, pc}
			(addr < (boundary_start + boundary_size)) &&
    5eb8:	2000      	movs	r0, #0
    5eba:	e7fc      	b.n	5eb6 <is_regular_addr_valid+0x1c>

00005ebc <flash_page_foreach>:
	return count;
}

void flash_page_foreach(const struct device *dev, flash_page_cb cb,
			void *data)
{
    5ebc:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
	const struct flash_pages_layout *layout;
	struct flash_pages_info page_info;
	size_t block, num_blocks, page = 0, i;
	off_t off = 0;

	api->page_layout(dev, &layout, &num_blocks);
    5ec0:	6883      	ldr	r3, [r0, #8]
{
    5ec2:	b086      	sub	sp, #24
	api->page_layout(dev, &layout, &num_blocks);
    5ec4:	691b      	ldr	r3, [r3, #16]
{
    5ec6:	4688      	mov	r8, r1
    5ec8:	4691      	mov	r9, r2
	api->page_layout(dev, &layout, &num_blocks);
    5eca:	a901      	add	r1, sp, #4
    5ecc:	aa02      	add	r2, sp, #8
    5ece:	4798      	blx	r3
	off_t off = 0;
    5ed0:	2400      	movs	r4, #0
	size_t block, num_blocks, page = 0, i;
    5ed2:	46a2      	mov	sl, r4

	for (block = 0; block < num_blocks; block++) {
    5ed4:	4625      	mov	r5, r4
    5ed6:	9b02      	ldr	r3, [sp, #8]
    5ed8:	42ab      	cmp	r3, r5
    5eda:	d802      	bhi.n	5ee2 <flash_page_foreach+0x26>

			off += page_info.size;
			page++;
		}
	}
}
    5edc:	b006      	add	sp, #24
    5ede:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
		const struct flash_pages_layout *l = &layout[block];
    5ee2:	9f01      	ldr	r7, [sp, #4]
    5ee4:	eb07 07c5 	add.w	r7, r7, r5, lsl #3
		for (i = 0; i < l->pages_count; i++) {
    5ee8:	2600      	movs	r6, #0
		page_info.size = l->pages_size;
    5eea:	687b      	ldr	r3, [r7, #4]
    5eec:	9304      	str	r3, [sp, #16]
		for (i = 0; i < l->pages_count; i++) {
    5eee:	683a      	ldr	r2, [r7, #0]
    5ef0:	42b2      	cmp	r2, r6
    5ef2:	eb0a 0306 	add.w	r3, sl, r6
    5ef6:	d802      	bhi.n	5efe <flash_page_foreach+0x42>
	for (block = 0; block < num_blocks; block++) {
    5ef8:	3501      	adds	r5, #1
    5efa:	469a      	mov	sl, r3
    5efc:	e7eb      	b.n	5ed6 <flash_page_foreach+0x1a>
			if (!cb(&page_info, data)) {
    5efe:	4649      	mov	r1, r9
    5f00:	a803      	add	r0, sp, #12
			page_info.start_offset = off;
    5f02:	9403      	str	r4, [sp, #12]
			page_info.index = page;
    5f04:	9305      	str	r3, [sp, #20]
			if (!cb(&page_info, data)) {
    5f06:	47c0      	blx	r8
    5f08:	2800      	cmp	r0, #0
    5f0a:	d0e7      	beq.n	5edc <flash_page_foreach+0x20>
			off += page_info.size;
    5f0c:	9b04      	ldr	r3, [sp, #16]
		for (i = 0; i < l->pages_count; i++) {
    5f0e:	3601      	adds	r6, #1
			off += page_info.size;
    5f10:	441c      	add	r4, r3
		for (i = 0; i < l->pages_count; i++) {
    5f12:	e7ec      	b.n	5eee <flash_page_foreach+0x32>

00005f14 <uarte_nrfx_config_get>:
	*cfg = data->uart_config;
    5f14:	6902      	ldr	r2, [r0, #16]
{
    5f16:	460b      	mov	r3, r1
	*cfg = data->uart_config;
    5f18:	e9d2 0101 	ldrd	r0, r1, [r2, #4]
    5f1c:	e883 0003 	stmia.w	r3, {r0, r1}
}
    5f20:	2000      	movs	r0, #0
    5f22:	4770      	bx	lr

00005f24 <uarte_nrfx_err_check>:
	return config->uarte_regs;
    5f24:	6843      	ldr	r3, [r0, #4]
    5f26:	681b      	ldr	r3, [r3, #0]
    uint32_t errsrc_mask = p_reg->ERRORSRC;
    5f28:	f8d3 0480 	ldr.w	r0, [r3, #1152]	; 0x480
    p_reg->ERRORSRC = errsrc_mask;
    5f2c:	f8c3 0480 	str.w	r0, [r3, #1152]	; 0x480
}
    5f30:	4770      	bx	lr

00005f32 <uarte_nrfx_poll_in>:
	return config->uarte_regs;
    5f32:	6843      	ldr	r3, [r0, #4]
	const struct uarte_nrfx_data *data = dev->data;
    5f34:	6902      	ldr	r2, [r0, #16]
	return config->uarte_regs;
    5f36:	681b      	ldr	r3, [r3, #0]
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    5f38:	f8d3 0110 	ldr.w	r0, [r3, #272]	; 0x110
	if (!nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDRX)) {
    5f3c:	b148      	cbz	r0, 5f52 <uarte_nrfx_poll_in+0x20>
	*c = data->rx_data;
    5f3e:	7c52      	ldrb	r2, [r2, #17]
    5f40:	700a      	strb	r2, [r1, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    5f42:	2000      	movs	r0, #0
    5f44:	f8c3 0110 	str.w	r0, [r3, #272]	; 0x110
    5f48:	f8d3 2110 	ldr.w	r2, [r3, #272]	; 0x110
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    5f4c:	2201      	movs	r2, #1
    5f4e:	601a      	str	r2, [r3, #0]
	return 0;
    5f50:	4770      	bx	lr
		return -1;
    5f52:	f04f 30ff 	mov.w	r0, #4294967295
}
    5f56:	4770      	bx	lr

00005f58 <is_tx_ready.isra.0>:
	return config->uarte_regs;
    5f58:	6802      	ldr	r2, [r0, #0]
static bool is_tx_ready(const struct device *dev)
    5f5a:	4603      	mov	r3, r0
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    5f5c:	f8d2 0158 	ldr.w	r0, [r2, #344]	; 0x158
	return nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED) ||
    5f60:	b940      	cbnz	r0, 5f74 <is_tx_ready.isra.0+0x1c>
	bool ppi_endtx = config->flags & UARTE_CFG_FLAG_PPI_ENDTX;
    5f62:	685b      	ldr	r3, [r3, #4]
	return nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED) ||
    5f64:	079b      	lsls	r3, r3, #30
    5f66:	d406      	bmi.n	5f76 <is_tx_ready.isra.0+0x1e>
    5f68:	f8d2 0120 	ldr.w	r0, [r2, #288]	; 0x120
    5f6c:	3800      	subs	r0, #0
    5f6e:	bf18      	it	ne
    5f70:	2001      	movne	r0, #1
    5f72:	4770      	bx	lr
    5f74:	2001      	movs	r0, #1
}
    5f76:	4770      	bx	lr

00005f78 <uarte_nrfx_isr_int>:
	const struct uarte_nrfx_config *config = dev->config;
    5f78:	6842      	ldr	r2, [r0, #4]
	return config->uarte_regs;
    5f7a:	6813      	ldr	r3, [r2, #0]
    return p_reg->INTENSET & mask;
    5f7c:	f8d3 1304 	ldr.w	r1, [r3, #772]	; 0x304
	if (nrf_uarte_int_enable_check(uarte, NRF_UARTE_INT_ENDTX_MASK) &&
    5f80:	05c9      	lsls	r1, r1, #23
    5f82:	d518      	bpl.n	5fb6 <uarte_nrfx_isr_int+0x3e>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    5f84:	f8d3 1120 	ldr.w	r1, [r3, #288]	; 0x120
    5f88:	b1a9      	cbz	r1, 5fb6 <uarte_nrfx_isr_int+0x3e>
	__asm__ volatile(
    5f8a:	f04f 0020 	mov.w	r0, #32
    5f8e:	f3ef 8111 	mrs	r1, BASEPRI
    5f92:	f380 8812 	msr	BASEPRI_MAX, r0
    5f96:	f3bf 8f6f 	isb	sy
    5f9a:	f8d3 0120 	ldr.w	r0, [r3, #288]	; 0x120
	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDTX)) {
    5f9e:	b130      	cbz	r0, 5fae <uarte_nrfx_isr_int+0x36>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    5fa0:	2000      	movs	r0, #0
    5fa2:	f8c3 0120 	str.w	r0, [r3, #288]	; 0x120
    5fa6:	f8d3 0120 	ldr.w	r0, [r3, #288]	; 0x120
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    5faa:	2001      	movs	r0, #1
    5fac:	60d8      	str	r0, [r3, #12]
	__asm__ volatile(
    5fae:	f381 8811 	msr	BASEPRI, r1
    5fb2:	f3bf 8f6f 	isb	sy
	if (config->flags & UARTE_CFG_FLAG_LOW_POWER) {
    5fb6:	6852      	ldr	r2, [r2, #4]
    5fb8:	06d2      	lsls	r2, r2, #27
    5fba:	d515      	bpl.n	5fe8 <uarte_nrfx_isr_int+0x70>
	__asm__ volatile(
    5fbc:	f04f 0120 	mov.w	r1, #32
    5fc0:	f3ef 8211 	mrs	r2, BASEPRI
    5fc4:	f381 8812 	msr	BASEPRI_MAX, r1
    5fc8:	f3bf 8f6f 	isb	sy
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    5fcc:	f8d3 1158 	ldr.w	r1, [r3, #344]	; 0x158
		if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED)) {
    5fd0:	b111      	cbz	r1, 5fd8 <uarte_nrfx_isr_int+0x60>
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
    5fd2:	2100      	movs	r1, #0
    5fd4:	f8c3 1500 	str.w	r1, [r3, #1280]	; 0x500
    p_reg->INTENCLR = mask;
    5fd8:	f44f 0180 	mov.w	r1, #4194304	; 0x400000
    5fdc:	f8c3 1308 	str.w	r1, [r3, #776]	; 0x308
	__asm__ volatile(
    5fe0:	f382 8811 	msr	BASEPRI, r2
    5fe4:	f3bf 8f6f 	isb	sy
}
    5fe8:	4770      	bx	lr

00005fea <pinctrl_lookup_state>:

#include <drivers/pinctrl.h>

int pinctrl_lookup_state(const struct pinctrl_dev_config *config, uint8_t id,
			 const struct pinctrl_state **state)
{
    5fea:	b530      	push	{r4, r5, lr}
	*state = &config->states[0];
    5fec:	6843      	ldr	r3, [r0, #4]
    5fee:	6013      	str	r3, [r2, #0]
	while (*state <= &config->states[config->state_cnt - 1U]) {
    5ff0:	7a03      	ldrb	r3, [r0, #8]
    5ff2:	f103 5300 	add.w	r3, r3, #536870912	; 0x20000000
    5ff6:	3b01      	subs	r3, #1
    5ff8:	00db      	lsls	r3, r3, #3
    5ffa:	6845      	ldr	r5, [r0, #4]
    5ffc:	6814      	ldr	r4, [r2, #0]
    5ffe:	441d      	add	r5, r3
    6000:	42ac      	cmp	r4, r5
    6002:	d902      	bls.n	600a <pinctrl_lookup_state+0x20>
		}

		(*state)++;
	}

	return -ENOENT;
    6004:	f06f 0001 	mvn.w	r0, #1
}
    6008:	bd30      	pop	{r4, r5, pc}
		if (id == (*state)->id) {
    600a:	7965      	ldrb	r5, [r4, #5]
    600c:	428d      	cmp	r5, r1
    600e:	d002      	beq.n	6016 <pinctrl_lookup_state+0x2c>
		(*state)++;
    6010:	3408      	adds	r4, #8
    6012:	6014      	str	r4, [r2, #0]
    6014:	e7f1      	b.n	5ffa <pinctrl_lookup_state+0x10>
			return 0;
    6016:	2000      	movs	r0, #0
    6018:	e7f6      	b.n	6008 <pinctrl_lookup_state+0x1e>

0000601a <nrf_gpio_pin_write>:
    *p_pin = pin_number & 0x1F;
    601a:	f000 031f 	and.w	r3, r0, #31
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    601e:	2001      	movs	r0, #1
    6020:	4098      	lsls	r0, r3
    6022:	f04f 43a0 	mov.w	r3, #1342177280	; 0x50000000
    if (value == 0)
    6026:	b911      	cbnz	r1, 602e <nrf_gpio_pin_write+0x14>
    p_reg->OUTCLR = clr_mask;
    6028:	f8c3 050c 	str.w	r0, [r3, #1292]	; 0x50c
}
    602c:	4770      	bx	lr
    p_reg->OUTSET = set_mask;
    602e:	f8c3 0508 	str.w	r0, [r3, #1288]	; 0x508
}
    6032:	4770      	bx	lr

00006034 <nrf_pin_configure>:
__unused static void nrf_pin_configure(pinctrl_soc_pin_t pin,
				       nrf_gpio_pin_dir_t dir,
				       nrf_gpio_pin_input_t input)
{
	/* force input direction and disconnected buffer for low power */
	if (NRF_GET_LP(pin) == NRF_LP_ENABLE) {
    6034:	f400 5380 	and.w	r3, r0, #4096	; 0x1000
		dir = NRF_GPIO_PIN_DIR_INPUT;
		input = NRF_GPIO_PIN_INPUT_DISCONNECT;
    6038:	2b00      	cmp	r3, #0
{
    603a:	b510      	push	{r4, lr}
    *p_pin = pin_number & 0x1F;
    603c:	f000 031f 	and.w	r3, r0, #31
		input = NRF_GPIO_PIN_INPUT_DISCONNECT;
    6040:	bf08      	it	eq
    6042:	4614      	moveq	r4, r2
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    6044:	f3c0 1281 	ubfx	r2, r0, #6, #2
           ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) |
    6048:	f400 6070 	and.w	r0, r0, #3840	; 0xf00
    604c:	bf18      	it	ne
    604e:	2100      	movne	r1, #0
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    6050:	ea40 0282 	orr.w	r2, r0, r2, lsl #2
    6054:	ea42 0201 	orr.w	r2, r2, r1
    6058:	bf18      	it	ne
    605a:	2401      	movne	r4, #1
    reg->PIN_CNF[pin_number] = cnf;
    605c:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    6060:	f04f 41a0 	mov.w	r1, #1342177280	; 0x50000000
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
    6064:	ea42 0244 	orr.w	r2, r2, r4, lsl #1
    reg->PIN_CNF[pin_number] = cnf;
    6068:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
	}

	nrf_gpio_cfg(NRF_GET_PIN(pin), dir, input, NRF_GET_PULL(pin),
		     NRF_GET_DRIVE(pin), NRF_GPIO_PIN_NOSENSE);
}
    606c:	bd10      	pop	{r4, pc}

0000606e <pinctrl_configure_pins>:

int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
			   uintptr_t reg)
{
    606e:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    6072:	4614      	mov	r4, r2
    6074:	4680      	mov	r8, r0
    6076:	eb00 0781 	add.w	r7, r0, r1, lsl #2
			break;
		case NRF_FUN_PWM_OUT3:
			NRF_PSEL_PWM(reg, OUT[3]) = NRF_GET_PIN(pins[i]);
			nrf_gpio_pin_write(NRF_GET_PIN(pins[i]),
					   NRF_GET_INVERT(pins[i]));
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
    607a:	2501      	movs	r5, #1
    p_reg->OUTCLR = clr_mask;
    607c:	f04f 46a0 	mov.w	r6, #1342177280	; 0x50000000
	for (uint8_t i = 0U; i < pin_cnt; i++) {
    6080:	45b8      	cmp	r8, r7
    6082:	d102      	bne.n	608a <pinctrl_configure_pins+0x1c>
		default:
			return -ENOTSUP;
		}
	}

	return 0;
    6084:	2000      	movs	r0, #0
}
    6086:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		switch (NRF_GET_FUN(pins[i])) {
    608a:	f8d8 3000 	ldr.w	r3, [r8]
    608e:	0c1a      	lsrs	r2, r3, #16
    6090:	2a19      	cmp	r2, #25
    6092:	d875      	bhi.n	6180 <pinctrl_configure_pins+0x112>
    6094:	e8df f002 	tbb	[pc, r2]
    6098:	49221b0d 	.word	0x49221b0d
    609c:	74493c27 	.word	0x74493c27
    60a0:	4e747474 	.word	0x4e747474
    60a4:	74747453 	.word	0x74747453
    60a8:	74747474 	.word	0x74747474
    60ac:	65587474 	.word	0x65587474
    60b0:	6f6a      	.short	0x6f6a
			NRF_PSEL_UART(reg, TXD) = NRF_GET_PIN(pins[i]);
    60b2:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    60b6:	f8c4 350c 	str.w	r3, [r4, #1292]	; 0x50c
    *p_pin = pin_number & 0x1F;
    60ba:	f8d8 3000 	ldr.w	r3, [r8]
    60be:	f003 031f 	and.w	r3, r3, #31
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
    60c2:	fa05 f303 	lsl.w	r3, r5, r3
    p_reg->OUTSET = set_mask;
    60c6:	f8c6 3508 	str.w	r3, [r6, #1288]	; 0x508
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
    60ca:	2201      	movs	r2, #1
    60cc:	e004      	b.n	60d8 <pinctrl_configure_pins+0x6a>
			NRF_PSEL_UART(reg, RXD) = NRF_GET_PIN(pins[i]);
    60ce:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    60d2:	f8c4 3514 	str.w	r3, [r4, #1300]	; 0x514
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
    60d6:	2200      	movs	r2, #0
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
    60d8:	4611      	mov	r1, r2
    60da:	e012      	b.n	6102 <pinctrl_configure_pins+0x94>
			NRF_PSEL_UART(reg, RTS) = NRF_GET_PIN(pins[i]);
    60dc:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    60e0:	f8c4 3508 	str.w	r3, [r4, #1288]	; 0x508
    60e4:	e7e9      	b.n	60ba <pinctrl_configure_pins+0x4c>
			NRF_PSEL_SPIM(reg, SCK) = NRF_GET_PIN(pins[i]);
    60e6:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    60ea:	f8c4 3508 	str.w	r3, [r4, #1288]	; 0x508
    *p_pin = pin_number & 0x1F;
    60ee:	f8d8 3000 	ldr.w	r3, [r8]
    60f2:	f003 031f 	and.w	r3, r3, #31
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    60f6:	fa05 f303 	lsl.w	r3, r5, r3
    p_reg->OUTCLR = clr_mask;
    60fa:	f8c6 350c 	str.w	r3, [r6, #1292]	; 0x50c
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
    60fe:	2200      	movs	r2, #0
    6100:	2101      	movs	r1, #1
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
    6102:	f8d8 0000 	ldr.w	r0, [r8]
    6106:	f7ff ff95 	bl	6034 <nrf_pin_configure>
	for (uint8_t i = 0U; i < pin_cnt; i++) {
    610a:	f108 0804 	add.w	r8, r8, #4
    610e:	e7b7      	b.n	6080 <pinctrl_configure_pins+0x12>
			NRF_PSEL_SPIM(reg, MOSI) = NRF_GET_PIN(pins[i]);
    6110:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    6114:	f8c4 350c 	str.w	r3, [r4, #1292]	; 0x50c
    *p_pin = pin_number & 0x1F;
    6118:	f8d8 3000 	ldr.w	r3, [r8]
    611c:	f003 031f 	and.w	r3, r3, #31
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
    6120:	fa05 f303 	lsl.w	r3, r5, r3
    p_reg->OUTCLR = clr_mask;
    6124:	f8c6 350c 	str.w	r3, [r6, #1292]	; 0x50c
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
    6128:	e7cf      	b.n	60ca <pinctrl_configure_pins+0x5c>
			NRF_PSEL_SPIM(reg, MISO) = NRF_GET_PIN(pins[i]);
    612a:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    612e:	f8c4 3510 	str.w	r3, [r4, #1296]	; 0x510
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
    6132:	e7d0      	b.n	60d6 <pinctrl_configure_pins+0x68>
			NRF_PSEL_TWIM(reg, SCL) = NRF_GET_PIN(pins[i]);
    6134:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    6138:	f8c4 3508 	str.w	r3, [r4, #1288]	; 0x508
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
    613c:	e7cb      	b.n	60d6 <pinctrl_configure_pins+0x68>
			NRF_PSEL_TWIM(reg, SDA) = NRF_GET_PIN(pins[i]);
    613e:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    6142:	f8c4 350c 	str.w	r3, [r4, #1292]	; 0x50c
    6146:	e7c6      	b.n	60d6 <pinctrl_configure_pins+0x68>
			NRF_PSEL_PWM(reg, OUT[0]) = NRF_GET_PIN(pins[i]);
    6148:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    614c:	f8c4 3560 	str.w	r3, [r4, #1376]	; 0x560
			nrf_gpio_pin_write(NRF_GET_PIN(pins[i]),
    6150:	f8d8 0000 	ldr.w	r0, [r8]
    6154:	f3c0 3140 	ubfx	r1, r0, #13, #1
    6158:	f000 003f 	and.w	r0, r0, #63	; 0x3f
    615c:	f7ff ff5d 	bl	601a <nrf_gpio_pin_write>
    6160:	e7b3      	b.n	60ca <pinctrl_configure_pins+0x5c>
			NRF_PSEL_PWM(reg, OUT[1]) = NRF_GET_PIN(pins[i]);
    6162:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    6166:	f8c4 3564 	str.w	r3, [r4, #1380]	; 0x564
			nrf_gpio_pin_write(NRF_GET_PIN(pins[i]),
    616a:	e7f1      	b.n	6150 <pinctrl_configure_pins+0xe2>
			NRF_PSEL_PWM(reg, OUT[2]) = NRF_GET_PIN(pins[i]);
    616c:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    6170:	f8c4 3568 	str.w	r3, [r4, #1384]	; 0x568
			nrf_gpio_pin_write(NRF_GET_PIN(pins[i]),
    6174:	e7ec      	b.n	6150 <pinctrl_configure_pins+0xe2>
			NRF_PSEL_PWM(reg, OUT[3]) = NRF_GET_PIN(pins[i]);
    6176:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    617a:	f8c4 356c 	str.w	r3, [r4, #1388]	; 0x56c
    617e:	e7e7      	b.n	6150 <pinctrl_configure_pins+0xe2>
		switch (NRF_GET_FUN(pins[i])) {
    6180:	f06f 0085 	mvn.w	r0, #133	; 0x85
    6184:	e77f      	b.n	6086 <pinctrl_configure_pins+0x18>

00006186 <fprotect_area>:
#define ENABLE_IN_DEBUG false
#endif


int fprotect_area(uint32_t start, size_t length)
{
    6186:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
}

NRF_STATIC_INLINE void nrf_bprot_nvm_protection_in_debug_set(NRF_BPROT_Type * p_reg,
                                                             bool             enable)
{
    p_reg->DISABLEINDEBUG =
    618a:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    618e:	4604      	mov	r4, r0
    6190:	4688      	mov	r8, r1
    6192:	b085      	sub	sp, #20
    6194:	2701      	movs	r7, #1
	uint32_t block_end   = (start + length) / BPROT_REGIONS_SIZE;
	uint32_t block_mask[BPROT_CONFIGS_NUM] = {0};

	BUILD_ASSERT(BPROT_REGIONS_SIZE == CONFIG_FPROTECT_BLOCK_SIZE);

	if ((start % BPROT_REGIONS_SIZE) ||
    6196:	ea44 0408 	orr.w	r4, r4, r8
	uint32_t block_end   = (start + length) / BPROT_REGIONS_SIZE;
    619a:	eb00 0901 	add.w	r9, r0, r1
    619e:	f8c3 7608 	str.w	r7, [r3, #1544]	; 0x608
	uint32_t block_start = start / BPROT_REGIONS_SIZE;
    61a2:	0b05      	lsrs	r5, r0, #12
	uint32_t block_mask[BPROT_CONFIGS_NUM] = {0};
    61a4:	2210      	movs	r2, #16
    61a6:	2100      	movs	r1, #0
    61a8:	4668      	mov	r0, sp
	if ((start % BPROT_REGIONS_SIZE) ||
    61aa:	f3c4 040b 	ubfx	r4, r4, #0, #12
	uint32_t block_mask[BPROT_CONFIGS_NUM] = {0};
    61ae:	f7ff fd88 	bl	5cc2 <memset>
	uint32_t block_end   = (start + length) / BPROT_REGIONS_SIZE;
    61b2:	ea4f 3619 	mov.w	r6, r9, lsr #12
	if ((start % BPROT_REGIONS_SIZE) ||
    61b6:	b924      	cbnz	r4, 61c2 <fprotect_area+0x3c>
	    (length % BPROT_REGIONS_SIZE) ||
    61b8:	f5b9 2f01 	cmp.w	r9, #528384	; 0x81000
    61bc:	d201      	bcs.n	61c2 <fprotect_area+0x3c>
	    (block_end > BPROT_REGIONS_NUM) ||
    61be:	42b5      	cmp	r5, r6
    61c0:	d910      	bls.n	61e4 <fprotect_area+0x5e>
		/*
		 * start or length isn't aligned with a BPROT region,
		 * or attempting to protect an area that is invalid or outside
		 * flash.
		 */
		return -EINVAL;
    61c2:	f06f 0015 	mvn.w	r0, #21
    61c6:	e01e      	b.n	6206 <fprotect_area+0x80>
	}

	for (uint32_t i = block_start; i < block_end; i++) {
		block_mask[i / BITS_PER_LONG] |= BIT(i % BITS_PER_LONG);
    61c8:	096a      	lsrs	r2, r5, #5
    61ca:	ab04      	add	r3, sp, #16
    61cc:	eb03 0282 	add.w	r2, r3, r2, lsl #2
    61d0:	f005 031f 	and.w	r3, r5, #31
    61d4:	f852 1c10 	ldr.w	r1, [r2, #-16]
    61d8:	fa07 f303 	lsl.w	r3, r7, r3
    61dc:	430b      	orrs	r3, r1
    61de:	f842 3c10 	str.w	r3, [r2, #-16]
	for (uint32_t i = block_start; i < block_end; i++) {
    61e2:	3501      	adds	r5, #1
    61e4:	42b5      	cmp	r5, r6
    61e6:	d1ef      	bne.n	61c8 <fprotect_area+0x42>
            p_reg->CONFIG0 = block_mask;
    61e8:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    61ec:	9a00      	ldr	r2, [sp, #0]
    61ee:	f8c3 2600 	str.w	r2, [r3, #1536]	; 0x600
	}

	for (uint32_t i = 0; i < BPROT_CONFIGS_NUM; i++) {
		PROTECT(NRF_BPROT, i, block_mask[i]);
    61f2:	9a01      	ldr	r2, [sp, #4]
            p_reg->CONFIG1 = block_mask;
    61f4:	f8c3 2604 	str.w	r2, [r3, #1540]	; 0x604
    61f8:	9a02      	ldr	r2, [sp, #8]
            p_reg->CONFIG2 = block_mask;
    61fa:	f8c3 2610 	str.w	r2, [r3, #1552]	; 0x610
    61fe:	9a03      	ldr	r2, [sp, #12]
            p_reg->CONFIG3 = block_mask;
    6200:	f8c3 2614 	str.w	r2, [r3, #1556]	; 0x614
	}

	return 0;
    6204:	2000      	movs	r0, #0
}
    6206:	b005      	add	sp, #20
    6208:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}

0000620c <bootutil_buffer_is_erased.part.0>:
bool bootutil_buffer_is_erased(const struct flash_area *area,
    620c:	b538      	push	{r3, r4, r5, lr}
    620e:	460c      	mov	r4, r1
    6210:	4615      	mov	r5, r2
    6212:	4425      	add	r5, r4
    erased_val = flash_area_erased_val(area);
    6214:	f7ff fce6 	bl	5be4 <flash_area_erased_val>
    for (i = 0, u8b = (uint8_t *)buffer; i < len; i++) {
    6218:	4621      	mov	r1, r4
    621a:	42a9      	cmp	r1, r5
    621c:	d101      	bne.n	6222 <bootutil_buffer_is_erased.part.0+0x16>
    return true;
    621e:	2001      	movs	r0, #1
}
    6220:	bd38      	pop	{r3, r4, r5, pc}
        if (u8b[i] != erased_val) {
    6222:	f811 3b01 	ldrb.w	r3, [r1], #1
    6226:	4298      	cmp	r0, r3
    6228:	d0f7      	beq.n	621a <bootutil_buffer_is_erased.part.0+0xe>
            return false;
    622a:	2000      	movs	r0, #0
    622c:	e7f8      	b.n	6220 <bootutil_buffer_is_erased.part.0+0x14>

0000622e <boot_swap_info_off>:
    return ALIGN_DOWN(boot_magic_off(fap) - BOOT_MAX_ALIGN, BOOT_MAX_ALIGN);
    622e:	6880      	ldr	r0, [r0, #8]
    6230:	3818      	subs	r0, #24
    6232:	f020 0007 	bic.w	r0, r0, #7
}
    6236:	3810      	subs	r0, #16
    6238:	4770      	bx	lr

0000623a <boot_magic_compatible_check>:
    switch (tbl_val) {
    623a:	2804      	cmp	r0, #4
    623c:	d009      	beq.n	6252 <boot_magic_compatible_check+0x18>
    623e:	2805      	cmp	r0, #5
    6240:	d103      	bne.n	624a <boot_magic_compatible_check+0x10>
        return val != BOOT_MAGIC_GOOD;
    6242:	1e48      	subs	r0, r1, #1
    6244:	bf18      	it	ne
    6246:	2001      	movne	r0, #1
    6248:	4770      	bx	lr
        return tbl_val == val;
    624a:	1a43      	subs	r3, r0, r1
    624c:	4258      	negs	r0, r3
    624e:	4158      	adcs	r0, r3
    6250:	4770      	bx	lr
    switch (tbl_val) {
    6252:	2001      	movs	r0, #1
}
    6254:	4770      	bx	lr

00006256 <bootutil_buffer_is_erased>:
    if (buffer == NULL || len == 0) {
    6256:	b111      	cbz	r1, 625e <bootutil_buffer_is_erased+0x8>
    6258:	b10a      	cbz	r2, 625e <bootutil_buffer_is_erased+0x8>
    625a:	f7ff bfd7 	b.w	620c <bootutil_buffer_is_erased.part.0>
}
    625e:	2000      	movs	r0, #0
    6260:	4770      	bx	lr

00006262 <boot_read_flag>:
{
    6262:	b538      	push	{r3, r4, r5, lr}
    6264:	460c      	mov	r4, r1
    rc = flash_area_read(fap, off, flag, sizeof *flag);
    6266:	2301      	movs	r3, #1
{
    6268:	4611      	mov	r1, r2
    rc = flash_area_read(fap, off, flag, sizeof *flag);
    626a:	4622      	mov	r2, r4
{
    626c:	4605      	mov	r5, r0
    rc = flash_area_read(fap, off, flag, sizeof *flag);
    626e:	f7ff fc61 	bl	5b34 <flash_area_read>
    if (rc < 0) {
    6272:	2800      	cmp	r0, #0
    6274:	db10      	blt.n	6298 <boot_read_flag+0x36>
    if (bootutil_buffer_is_erased(fap, flag, sizeof *flag)) {
    6276:	2201      	movs	r2, #1
    6278:	4621      	mov	r1, r4
    627a:	4628      	mov	r0, r5
    627c:	f7ff ffeb 	bl	6256 <bootutil_buffer_is_erased>
    6280:	b118      	cbz	r0, 628a <boot_read_flag+0x28>
        *flag = BOOT_FLAG_UNSET;
    6282:	2303      	movs	r3, #3
    6284:	7023      	strb	r3, [r4, #0]
    return 0;
    6286:	2000      	movs	r0, #0
}
    6288:	bd38      	pop	{r3, r4, r5, pc}
    if (flag != BOOT_FLAG_SET) {
    628a:	7823      	ldrb	r3, [r4, #0]
        return BOOT_FLAG_BAD;
    628c:	2b01      	cmp	r3, #1
    628e:	bf0c      	ite	eq
    6290:	2301      	moveq	r3, #1
    6292:	2302      	movne	r3, #2
        *flag = boot_flag_decode(*flag);
    6294:	7023      	strb	r3, [r4, #0]
    6296:	e7f7      	b.n	6288 <boot_read_flag+0x26>
        return BOOT_EFLASH;
    6298:	2001      	movs	r0, #1
    629a:	e7f5      	b.n	6288 <boot_read_flag+0x26>

0000629c <boot_write_trailer>:
{
    629c:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    62a0:	461d      	mov	r5, r3
    62a2:	4606      	mov	r6, r0
    62a4:	460f      	mov	r7, r1
    62a6:	4690      	mov	r8, r2
    align = flash_area_align(fap);
    62a8:	f7ff fc93 	bl	5bd2 <flash_area_align>
    align = ALIGN_UP(inlen, align);
    62ac:	1e6c      	subs	r4, r5, #1
    62ae:	4404      	add	r4, r0
    62b0:	4240      	negs	r0, r0
    62b2:	4004      	ands	r4, r0
    if (align > BOOT_MAX_ALIGN) {
    62b4:	2c08      	cmp	r4, #8
    62b6:	d81a      	bhi.n	62ee <boot_write_trailer+0x52>
    erased_val = flash_area_erased_val(fap);
    62b8:	4630      	mov	r0, r6
    62ba:	f7ff fc93 	bl	5be4 <flash_area_erased_val>
    memcpy(buf, inbuf, inlen);
    62be:	462a      	mov	r2, r5
    erased_val = flash_area_erased_val(fap);
    62c0:	4681      	mov	r9, r0
    memcpy(buf, inbuf, inlen);
    62c2:	4641      	mov	r1, r8
    62c4:	4668      	mov	r0, sp
    62c6:	f7ff fcf1 	bl	5cac <memcpy>
    memset(&buf[inlen], erased_val, align - inlen);
    62ca:	1b62      	subs	r2, r4, r5
    62cc:	4649      	mov	r1, r9
    62ce:	eb0d 0005 	add.w	r0, sp, r5
    62d2:	f7ff fcf6 	bl	5cc2 <memset>
    rc = flash_area_write(fap, off, buf, align);
    62d6:	4623      	mov	r3, r4
    62d8:	466a      	mov	r2, sp
    62da:	4639      	mov	r1, r7
    62dc:	4630      	mov	r0, r6
    62de:	f7ff fc45 	bl	5b6c <flash_area_write>
    if (rc != 0) {
    62e2:	3800      	subs	r0, #0
    62e4:	bf18      	it	ne
    62e6:	2001      	movne	r0, #1
}
    62e8:	b003      	add	sp, #12
    62ea:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
        return -1;
    62ee:	f04f 30ff 	mov.w	r0, #4294967295
    62f2:	e7f9      	b.n	62e8 <boot_write_trailer+0x4c>

000062f4 <boot_write_trailer_flag>:
{
    62f4:	b507      	push	{r0, r1, r2, lr}
    return boot_write_trailer(fap, off, buf, 1);
    62f6:	2301      	movs	r3, #1
    const uint8_t buf[1] = { flag_val };
    62f8:	f88d 2004 	strb.w	r2, [sp, #4]
    return boot_write_trailer(fap, off, buf, 1);
    62fc:	aa01      	add	r2, sp, #4
    62fe:	f7ff ffcd 	bl	629c <boot_write_trailer>
}
    6302:	b003      	add	sp, #12
    6304:	f85d fb04 	ldr.w	pc, [sp], #4

00006308 <boot_write_image_ok>:
    return ALIGN_DOWN(boot_magic_off(fap) - BOOT_MAX_ALIGN, BOOT_MAX_ALIGN);
    6308:	6881      	ldr	r1, [r0, #8]
    630a:	3918      	subs	r1, #24
    return boot_write_trailer_flag(fap, off, BOOT_FLAG_SET);
    630c:	2201      	movs	r2, #1
    630e:	f021 0107 	bic.w	r1, r1, #7
    6312:	f7ff bfef 	b.w	62f4 <boot_write_trailer_flag>

00006316 <boot_read_image_ok>:
    return ALIGN_DOWN(boot_magic_off(fap) - BOOT_MAX_ALIGN, BOOT_MAX_ALIGN);
    6316:	6882      	ldr	r2, [r0, #8]
    6318:	3a18      	subs	r2, #24
    return boot_read_flag(fap, image_ok, boot_image_ok_off(fap));
    631a:	f022 0207 	bic.w	r2, r2, #7
    631e:	f7ff bfa0 	b.w	6262 <boot_read_flag>

00006322 <boot_read_swap_state_by_id>:
{
    6322:	b513      	push	{r0, r1, r4, lr}
    6324:	460c      	mov	r4, r1
    rc = flash_area_open(flash_area_id, &fap);
    6326:	b2c0      	uxtb	r0, r0
    6328:	a901      	add	r1, sp, #4
    632a:	f7fb fcb1 	bl	1c90 <flash_area_open>
    if (rc != 0) {
    632e:	b950      	cbnz	r0, 6346 <boot_read_swap_state_by_id+0x24>
    rc = boot_read_swap_state(fap, state);
    6330:	4621      	mov	r1, r4
    6332:	9801      	ldr	r0, [sp, #4]
    6334:	f7fd f8b8 	bl	34a8 <boot_read_swap_state>
    6338:	4604      	mov	r4, r0
    flash_area_close(fap);
    633a:	9801      	ldr	r0, [sp, #4]
    633c:	f7ff fbf9 	bl	5b32 <flash_area_close>
}
    6340:	4620      	mov	r0, r4
    6342:	b002      	add	sp, #8
    6344:	bd10      	pop	{r4, pc}
        return BOOT_EFLASH;
    6346:	2401      	movs	r4, #1
    6348:	e7fa      	b.n	6340 <boot_read_swap_state_by_id+0x1e>

0000634a <boot_write_swap_info>:
{
    634a:	b513      	push	{r0, r1, r4, lr}
    BOOT_SET_SWAP_INFO(swap_info, image_num, swap_type);
    634c:	ea41 1102 	orr.w	r1, r1, r2, lsl #4
{
    6350:	4604      	mov	r4, r0
    BOOT_SET_SWAP_INFO(swap_info, image_num, swap_type);
    6352:	f88d 1007 	strb.w	r1, [sp, #7]
    off = boot_swap_info_off(fap);
    6356:	f7ff ff6a 	bl	622e <boot_swap_info_off>
    return boot_write_trailer(fap, off, (const uint8_t *) &swap_info, 1);
    635a:	2301      	movs	r3, #1
    off = boot_swap_info_off(fap);
    635c:	4601      	mov	r1, r0
    return boot_write_trailer(fap, off, (const uint8_t *) &swap_info, 1);
    635e:	f10d 0207 	add.w	r2, sp, #7
    6362:	4620      	mov	r0, r4
    6364:	f7ff ff9a 	bl	629c <boot_write_trailer>
}
    6368:	b002      	add	sp, #8
    636a:	bd10      	pop	{r4, pc}

0000636c <nrf52_errata_108>:
            if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF)
    636c:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    6370:	f8d3 0130 	ldr.w	r0, [r3, #304]	; 0x130
    6374:	1c42      	adds	r2, r0, #1
                var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
    6376:	bf04      	itt	eq
    6378:	f04f 4370 	moveq.w	r3, #4026531840	; 0xf0000000
    637c:	f893 0fe0 	ldrbeq.w	r0, [r3, #4064]	; 0xfe0
}
    6380:	1f83      	subs	r3, r0, #6
    6382:	4258      	negs	r0, r3
    6384:	4158      	adcs	r0, r3
    6386:	4770      	bx	lr

00006388 <nrfx_isr>:
#include <nrfx.h>
#include <kernel.h>

void nrfx_isr(const void *irq_handler)
{
	((nrfx_irq_handler_t)irq_handler)();
    6388:	4700      	bx	r0

0000638a <nrfx_busy_wait>:
    638a:	f000 b847 	b.w	641c <z_impl_k_busy_wait>

0000638e <nrfx_clock_enable>:
{
    638e:	b508      	push	{r3, lr}
    priority = NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY;
#else
    #error "This code is not supposed to be compiled when neither POWER nor CLOCK is enabled."
#endif

    if (!NRFX_IRQ_IS_ENABLED(nrfx_get_irq_number(NRF_CLOCK)))
    6390:	2000      	movs	r0, #0
    6392:	f7fb fd1d 	bl	1dd0 <arch_irq_is_enabled>
    6396:	b908      	cbnz	r0, 639c <nrfx_clock_enable+0xe>
    {
        NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_CLOCK), priority);
        NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_CLOCK));
    6398:	f7fb fd0a 	bl	1db0 <arch_irq_enable>
    p_reg->LFCLKSRC = (uint32_t)(source);
    639c:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    63a0:	2200      	movs	r2, #0
    63a2:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
}
    63a6:	bd08      	pop	{r3, pc}

000063a8 <nrfx_clock_stop>:
    clock_stop(domain);
    63a8:	f7fd bafa 	b.w	39a0 <clock_stop>

000063ac <nrf_gpio_cfg_sense_set>:
    *p_pin = pin_number & 0x1F;
    63ac:	f000 001f 	and.w	r0, r0, #31
    63b0:	0080      	lsls	r0, r0, #2
    63b2:	f100 40a0 	add.w	r0, r0, #1342177280	; 0x50000000
    uint32_t cnf = reg->PIN_CNF[pin_number];
    63b6:	f8d0 3700 	ldr.w	r3, [r0, #1792]	; 0x700
    cnf &= ~to_update;
    63ba:	f423 3340 	bic.w	r3, r3, #196608	; 0x30000
    cnf |= ((uint32_t)(p_dir   ? *p_dir   : 0) << GPIO_PIN_CNF_DIR_Pos)   |
    63be:	ea43 4301 	orr.w	r3, r3, r1, lsl #16
    reg->PIN_CNF[pin_number] = cnf;
    63c2:	f8c0 3700 	str.w	r3, [r0, #1792]	; 0x700
}
    63c6:	4770      	bx	lr

000063c8 <nrfx_nvmc_flash_size_get>:
    63c8:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    63cc:	691a      	ldr	r2, [r3, #16]
NRF_STATIC_INLINE uint32_t nrf_ficr_codesize_get(NRF_FICR_Type const * p_reg)
{
#if defined(FICR_INFO_CODESIZE_CODESIZE_Msk)
    return p_reg->INFO.CODESIZE;
#else
    return p_reg->CODESIZE;
    63ce:	6958      	ldr	r0, [r3, #20]
}

uint32_t nrfx_nvmc_flash_size_get(void)
{
    return flash_total_size_get();
}
    63d0:	4350      	muls	r0, r2
    63d2:	4770      	bx	lr

000063d4 <nrfx_nvmc_flash_page_size_get>:
    return p_reg->CODEPAGESIZE;
    63d4:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    63d8:	6918      	ldr	r0, [r3, #16]

uint32_t nrfx_nvmc_flash_page_size_get(void)
{
    return flash_page_size_get();
}
    63da:	4770      	bx	lr

000063dc <nrfx_nvmc_flash_page_count_get>:
    return p_reg->CODESIZE;
    63dc:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    63e0:	6958      	ldr	r0, [r3, #20]

uint32_t nrfx_nvmc_flash_page_count_get(void)
{
    return flash_page_count_get();
}
    63e2:	4770      	bx	lr

000063e4 <SEGGER_RTT_Init>:
*    Initializes the RTT Control Block.
*    Should be used in RAM targets, at start of the application.
*
*/
void SEGGER_RTT_Init (void) {
  _DoInit();
    63e4:	f7fd bf2c 	b.w	4240 <_DoInit>

000063e8 <rtt_init>:
 */

K_MUTEX_DEFINE(rtt_term_mutex);

static int rtt_init(const struct device *unused)
{
    63e8:	b508      	push	{r3, lr}
	ARG_UNUSED(unused);

	SEGGER_RTT_Init();
    63ea:	f7ff fffb 	bl	63e4 <SEGGER_RTT_Init>

	return 0;
}
    63ee:	2000      	movs	r0, #0
    63f0:	bd08      	pop	{r3, pc}

000063f2 <z_device_state_init>:
}
    63f2:	4770      	bx	lr

000063f4 <z_device_is_ready>:
{
	/*
	 * if an invalid device pointer is passed as argument, this call
	 * reports the `device` as not ready for usage.
	 */
	if (dev == NULL) {
    63f4:	b138      	cbz	r0, 6406 <z_device_is_ready+0x12>
		return false;
	}

	return dev->state->initialized && (dev->state->init_res == 0U);
    63f6:	68c3      	ldr	r3, [r0, #12]
    63f8:	8818      	ldrh	r0, [r3, #0]
    63fa:	f3c0 0008 	ubfx	r0, r0, #0, #9
    63fe:	f5a0 7380 	sub.w	r3, r0, #256	; 0x100
    6402:	4258      	negs	r0, r3
    6404:	4158      	adcs	r0, r3
}
    6406:	4770      	bx	lr

00006408 <z_early_memset>:
	(void) memset(dst, c, n);
    6408:	f7ff bc5b 	b.w	5cc2 <memset>

0000640c <z_early_memcpy>:
	(void) memcpy(dst, src, n);
    640c:	f7ff bc4e 	b.w	5cac <memcpy>

00006410 <k_is_in_isr>:
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    6410:	f3ef 8005 	mrs	r0, IPSR
}

bool k_is_in_isr(void)
{
	return arch_is_in_isr();
}
    6414:	3800      	subs	r0, #0
    6416:	bf18      	it	ne
    6418:	2001      	movne	r0, #1
    641a:	4770      	bx	lr

0000641c <z_impl_k_busy_wait>:
#endif

void z_impl_k_busy_wait(uint32_t usec_to_wait)
{
	SYS_PORT_TRACING_FUNC_ENTER(k_thread, busy_wait, usec_to_wait);
	if (usec_to_wait == 0U) {
    641c:	b108      	cbz	r0, 6422 <z_impl_k_busy_wait+0x6>
		if ((current_cycles - start_cycles) >= cycles_to_wait) {
			break;
		}
	}
#else
	arch_busy_wait(usec_to_wait);
    641e:	f7fc b8bf 	b.w	25a0 <arch_busy_wait>
#endif /* CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT */
	SYS_PORT_TRACING_FUNC_EXIT(k_thread, busy_wait, usec_to_wait);
}
    6422:	4770      	bx	lr

00006424 <_OffsetAbsSyms>:

#include <gen_offset.h>

#include "offsets_aarch32.c"

GEN_ABS_SYM_END
    6424:	4770      	bx	lr
	...

00006428 <z_arm_platform_init>:
	 */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r0, =SystemInit
	bx r0
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	b SystemInit
    6428:	f7fd b92e 	b.w	3688 <SystemInit>
