
zephyr.elf:     file format elf32-littlearm


Disassembly of section rom_start:

0000c200 <_vector_table>:
    c200:	a0 0b 00 20 95 d6 00 00 27 02 01 00 69 d6 00 00     ... ....'...i...
    c210:	69 d6 00 00 69 d6 00 00 69 d6 00 00 00 00 00 00     i...i...i.......
	...
    c22c:	71 d3 00 00 69 d6 00 00 00 00 00 00 1d d3 00 00     q...i...........
    c23c:	69 d6 00 00                                         i...

0000c240 <_irq_vector_table>:
    c240:	21 d4 00 00 21 d4 00 00 21 d4 00 00 21 d4 00 00     !...!...!...!...
    c250:	21 d4 00 00 21 d4 00 00 21 d4 00 00 21 d4 00 00     !...!...!...!...
    c260:	21 d4 00 00 21 d4 00 00 21 d4 00 00 21 d4 00 00     !...!...!...!...
    c270:	21 d4 00 00 21 d4 00 00 21 d4 00 00 21 d4 00 00     !...!...!...!...
    c280:	21 d4 00 00 21 d4 00 00 21 d4 00 00 21 d4 00 00     !...!...!...!...
    c290:	21 d4 00 00 21 d4 00 00 21 d4 00 00 21 d4 00 00     !...!...!...!...
    c2a0:	21 d4 00 00 21 d4 00 00 21 d4 00 00 21 d4 00 00     !...!...!...!...
    c2b0:	21 d4 00 00 21 d4 00 00 21 d4 00 00 21 d4 00 00     !...!...!...!...
    c2c0:	21 d4 00 00 21 d4 00 00 21 d4 00 00 21 d4 00 00     !...!...!...!...
    c2d0:	21 d4 00 00 21 d4 00 00 21 d4 00 00                 !...!...!...

Disassembly of section text:

0000c2dc <__aeabi_uldivmod>:
    c2dc:	b953      	cbnz	r3, c2f4 <__aeabi_uldivmod+0x18>
    c2de:	b94a      	cbnz	r2, c2f4 <__aeabi_uldivmod+0x18>
    c2e0:	2900      	cmp	r1, #0
    c2e2:	bf08      	it	eq
    c2e4:	2800      	cmpeq	r0, #0
    c2e6:	bf1c      	itt	ne
    c2e8:	f04f 31ff 	movne.w	r1, #4294967295
    c2ec:	f04f 30ff 	movne.w	r0, #4294967295
    c2f0:	f000 b80c 	b.w	c30c <__aeabi_idiv0>
    c2f4:	f1ad 0c08 	sub.w	ip, sp, #8
    c2f8:	e96d ce04 	strd	ip, lr, [sp, #-16]!
    c2fc:	f000 f808 	bl	c310 <__udivmoddi4>
    c300:	f8dd e004 	ldr.w	lr, [sp, #4]
    c304:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
    c308:	b004      	add	sp, #16
    c30a:	4770      	bx	lr

0000c30c <__aeabi_idiv0>:
    c30c:	4770      	bx	lr
    c30e:	bf00      	nop

0000c310 <__udivmoddi4>:
    c310:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    c314:	4607      	mov	r7, r0
    c316:	468c      	mov	ip, r1
    c318:	4608      	mov	r0, r1
    c31a:	9e09      	ldr	r6, [sp, #36]	; 0x24
    c31c:	4615      	mov	r5, r2
    c31e:	463c      	mov	r4, r7
    c320:	4619      	mov	r1, r3
    c322:	2b00      	cmp	r3, #0
    c324:	f040 80c6 	bne.w	c4b4 <__udivmoddi4+0x1a4>
    c328:	4282      	cmp	r2, r0
    c32a:	fab2 f782 	clz	r7, r2
    c32e:	d946      	bls.n	c3be <__udivmoddi4+0xae>
    c330:	b14f      	cbz	r7, c346 <__udivmoddi4+0x36>
    c332:	f1c7 0e20 	rsb	lr, r7, #32
    c336:	fa24 fe0e 	lsr.w	lr, r4, lr
    c33a:	fa00 f307 	lsl.w	r3, r0, r7
    c33e:	40bd      	lsls	r5, r7
    c340:	ea4e 0c03 	orr.w	ip, lr, r3
    c344:	40bc      	lsls	r4, r7
    c346:	ea4f 4815 	mov.w	r8, r5, lsr #16
    c34a:	fa1f fe85 	uxth.w	lr, r5
    c34e:	fbbc f9f8 	udiv	r9, ip, r8
    c352:	0c22      	lsrs	r2, r4, #16
    c354:	fb08 c319 	mls	r3, r8, r9, ip
    c358:	fb09 fa0e 	mul.w	sl, r9, lr
    c35c:	ea42 4303 	orr.w	r3, r2, r3, lsl #16
    c360:	459a      	cmp	sl, r3
    c362:	d928      	bls.n	c3b6 <__udivmoddi4+0xa6>
    c364:	18eb      	adds	r3, r5, r3
    c366:	f109 30ff 	add.w	r0, r9, #4294967295
    c36a:	d204      	bcs.n	c376 <__udivmoddi4+0x66>
    c36c:	459a      	cmp	sl, r3
    c36e:	d902      	bls.n	c376 <__udivmoddi4+0x66>
    c370:	f1a9 0002 	sub.w	r0, r9, #2
    c374:	442b      	add	r3, r5
    c376:	eba3 030a 	sub.w	r3, r3, sl
    c37a:	b2a4      	uxth	r4, r4
    c37c:	fbb3 f2f8 	udiv	r2, r3, r8
    c380:	fb08 3312 	mls	r3, r8, r2, r3
    c384:	fb02 fe0e 	mul.w	lr, r2, lr
    c388:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
    c38c:	45a6      	cmp	lr, r4
    c38e:	d914      	bls.n	c3ba <__udivmoddi4+0xaa>
    c390:	192c      	adds	r4, r5, r4
    c392:	f102 33ff 	add.w	r3, r2, #4294967295
    c396:	d203      	bcs.n	c3a0 <__udivmoddi4+0x90>
    c398:	45a6      	cmp	lr, r4
    c39a:	d901      	bls.n	c3a0 <__udivmoddi4+0x90>
    c39c:	1e93      	subs	r3, r2, #2
    c39e:	442c      	add	r4, r5
    c3a0:	eba4 040e 	sub.w	r4, r4, lr
    c3a4:	ea43 4000 	orr.w	r0, r3, r0, lsl #16
    c3a8:	b11e      	cbz	r6, c3b2 <__udivmoddi4+0xa2>
    c3aa:	40fc      	lsrs	r4, r7
    c3ac:	2300      	movs	r3, #0
    c3ae:	6034      	str	r4, [r6, #0]
    c3b0:	6073      	str	r3, [r6, #4]
    c3b2:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    c3b6:	4648      	mov	r0, r9
    c3b8:	e7dd      	b.n	c376 <__udivmoddi4+0x66>
    c3ba:	4613      	mov	r3, r2
    c3bc:	e7f0      	b.n	c3a0 <__udivmoddi4+0x90>
    c3be:	b902      	cbnz	r2, c3c2 <__udivmoddi4+0xb2>
    c3c0:	deff      	udf	#255	; 0xff
    c3c2:	bb87      	cbnz	r7, c426 <__udivmoddi4+0x116>
    c3c4:	1a83      	subs	r3, r0, r2
    c3c6:	2101      	movs	r1, #1
    c3c8:	ea4f 4e15 	mov.w	lr, r5, lsr #16
    c3cc:	b2aa      	uxth	r2, r5
    c3ce:	fbb3 fcfe 	udiv	ip, r3, lr
    c3d2:	0c20      	lsrs	r0, r4, #16
    c3d4:	fb0e 331c 	mls	r3, lr, ip, r3
    c3d8:	fb0c f802 	mul.w	r8, ip, r2
    c3dc:	ea40 4303 	orr.w	r3, r0, r3, lsl #16
    c3e0:	4598      	cmp	r8, r3
    c3e2:	d963      	bls.n	c4ac <__udivmoddi4+0x19c>
    c3e4:	18eb      	adds	r3, r5, r3
    c3e6:	f10c 30ff 	add.w	r0, ip, #4294967295
    c3ea:	d204      	bcs.n	c3f6 <__udivmoddi4+0xe6>
    c3ec:	4598      	cmp	r8, r3
    c3ee:	d902      	bls.n	c3f6 <__udivmoddi4+0xe6>
    c3f0:	f1ac 0002 	sub.w	r0, ip, #2
    c3f4:	442b      	add	r3, r5
    c3f6:	eba3 0308 	sub.w	r3, r3, r8
    c3fa:	b2a4      	uxth	r4, r4
    c3fc:	fbb3 fcfe 	udiv	ip, r3, lr
    c400:	fb0e 331c 	mls	r3, lr, ip, r3
    c404:	fb0c f202 	mul.w	r2, ip, r2
    c408:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
    c40c:	42a2      	cmp	r2, r4
    c40e:	d94f      	bls.n	c4b0 <__udivmoddi4+0x1a0>
    c410:	192c      	adds	r4, r5, r4
    c412:	f10c 33ff 	add.w	r3, ip, #4294967295
    c416:	d204      	bcs.n	c422 <__udivmoddi4+0x112>
    c418:	42a2      	cmp	r2, r4
    c41a:	d902      	bls.n	c422 <__udivmoddi4+0x112>
    c41c:	f1ac 0302 	sub.w	r3, ip, #2
    c420:	442c      	add	r4, r5
    c422:	1aa4      	subs	r4, r4, r2
    c424:	e7be      	b.n	c3a4 <__udivmoddi4+0x94>
    c426:	f1c7 0c20 	rsb	ip, r7, #32
    c42a:	fa20 f80c 	lsr.w	r8, r0, ip
    c42e:	fa00 f307 	lsl.w	r3, r0, r7
    c432:	fa24 fc0c 	lsr.w	ip, r4, ip
    c436:	40bd      	lsls	r5, r7
    c438:	ea4c 0203 	orr.w	r2, ip, r3
    c43c:	ea4f 4e15 	mov.w	lr, r5, lsr #16
    c440:	b2ab      	uxth	r3, r5
    c442:	fbb8 fcfe 	udiv	ip, r8, lr
    c446:	0c11      	lsrs	r1, r2, #16
    c448:	fb0e 801c 	mls	r0, lr, ip, r8
    c44c:	fb0c f903 	mul.w	r9, ip, r3
    c450:	ea41 4000 	orr.w	r0, r1, r0, lsl #16
    c454:	4581      	cmp	r9, r0
    c456:	fa04 f407 	lsl.w	r4, r4, r7
    c45a:	d923      	bls.n	c4a4 <__udivmoddi4+0x194>
    c45c:	1828      	adds	r0, r5, r0
    c45e:	f10c 31ff 	add.w	r1, ip, #4294967295
    c462:	d204      	bcs.n	c46e <__udivmoddi4+0x15e>
    c464:	4581      	cmp	r9, r0
    c466:	d902      	bls.n	c46e <__udivmoddi4+0x15e>
    c468:	f1ac 0102 	sub.w	r1, ip, #2
    c46c:	4428      	add	r0, r5
    c46e:	eba0 0009 	sub.w	r0, r0, r9
    c472:	b292      	uxth	r2, r2
    c474:	fbb0 fcfe 	udiv	ip, r0, lr
    c478:	fb0e 001c 	mls	r0, lr, ip, r0
    c47c:	fb0c f803 	mul.w	r8, ip, r3
    c480:	ea42 4300 	orr.w	r3, r2, r0, lsl #16
    c484:	4598      	cmp	r8, r3
    c486:	d90f      	bls.n	c4a8 <__udivmoddi4+0x198>
    c488:	18eb      	adds	r3, r5, r3
    c48a:	f10c 32ff 	add.w	r2, ip, #4294967295
    c48e:	d204      	bcs.n	c49a <__udivmoddi4+0x18a>
    c490:	4598      	cmp	r8, r3
    c492:	d902      	bls.n	c49a <__udivmoddi4+0x18a>
    c494:	f1ac 0202 	sub.w	r2, ip, #2
    c498:	442b      	add	r3, r5
    c49a:	eba3 0308 	sub.w	r3, r3, r8
    c49e:	ea42 4101 	orr.w	r1, r2, r1, lsl #16
    c4a2:	e791      	b.n	c3c8 <__udivmoddi4+0xb8>
    c4a4:	4661      	mov	r1, ip
    c4a6:	e7e2      	b.n	c46e <__udivmoddi4+0x15e>
    c4a8:	4662      	mov	r2, ip
    c4aa:	e7f6      	b.n	c49a <__udivmoddi4+0x18a>
    c4ac:	4660      	mov	r0, ip
    c4ae:	e7a2      	b.n	c3f6 <__udivmoddi4+0xe6>
    c4b0:	4663      	mov	r3, ip
    c4b2:	e7b6      	b.n	c422 <__udivmoddi4+0x112>
    c4b4:	4283      	cmp	r3, r0
    c4b6:	d905      	bls.n	c4c4 <__udivmoddi4+0x1b4>
    c4b8:	b10e      	cbz	r6, c4be <__udivmoddi4+0x1ae>
    c4ba:	e9c6 7000 	strd	r7, r0, [r6]
    c4be:	2100      	movs	r1, #0
    c4c0:	4608      	mov	r0, r1
    c4c2:	e776      	b.n	c3b2 <__udivmoddi4+0xa2>
    c4c4:	fab3 f183 	clz	r1, r3
    c4c8:	b981      	cbnz	r1, c4ec <__udivmoddi4+0x1dc>
    c4ca:	4283      	cmp	r3, r0
    c4cc:	d301      	bcc.n	c4d2 <__udivmoddi4+0x1c2>
    c4ce:	42ba      	cmp	r2, r7
    c4d0:	d80a      	bhi.n	c4e8 <__udivmoddi4+0x1d8>
    c4d2:	1abc      	subs	r4, r7, r2
    c4d4:	eb60 0303 	sbc.w	r3, r0, r3
    c4d8:	2001      	movs	r0, #1
    c4da:	469c      	mov	ip, r3
    c4dc:	2e00      	cmp	r6, #0
    c4de:	d068      	beq.n	c5b2 <__udivmoddi4+0x2a2>
    c4e0:	e9c6 4c00 	strd	r4, ip, [r6]
    c4e4:	2100      	movs	r1, #0
    c4e6:	e764      	b.n	c3b2 <__udivmoddi4+0xa2>
    c4e8:	4608      	mov	r0, r1
    c4ea:	e7f7      	b.n	c4dc <__udivmoddi4+0x1cc>
    c4ec:	f1c1 0c20 	rsb	ip, r1, #32
    c4f0:	408b      	lsls	r3, r1
    c4f2:	fa22 f40c 	lsr.w	r4, r2, ip
    c4f6:	431c      	orrs	r4, r3
    c4f8:	fa02 f501 	lsl.w	r5, r2, r1
    c4fc:	fa00 f301 	lsl.w	r3, r0, r1
    c500:	fa27 f20c 	lsr.w	r2, r7, ip
    c504:	fa20 fb0c 	lsr.w	fp, r0, ip
    c508:	ea4f 4914 	mov.w	r9, r4, lsr #16
    c50c:	4313      	orrs	r3, r2
    c50e:	fbbb f8f9 	udiv	r8, fp, r9
    c512:	fa1f fe84 	uxth.w	lr, r4
    c516:	fb09 bb18 	mls	fp, r9, r8, fp
    c51a:	0c1a      	lsrs	r2, r3, #16
    c51c:	fb08 fa0e 	mul.w	sl, r8, lr
    c520:	ea42 420b 	orr.w	r2, r2, fp, lsl #16
    c524:	4592      	cmp	sl, r2
    c526:	fa07 f701 	lsl.w	r7, r7, r1
    c52a:	d93e      	bls.n	c5aa <__udivmoddi4+0x29a>
    c52c:	18a2      	adds	r2, r4, r2
    c52e:	f108 30ff 	add.w	r0, r8, #4294967295
    c532:	d204      	bcs.n	c53e <__udivmoddi4+0x22e>
    c534:	4592      	cmp	sl, r2
    c536:	d902      	bls.n	c53e <__udivmoddi4+0x22e>
    c538:	f1a8 0002 	sub.w	r0, r8, #2
    c53c:	4422      	add	r2, r4
    c53e:	eba2 020a 	sub.w	r2, r2, sl
    c542:	b29b      	uxth	r3, r3
    c544:	fbb2 f8f9 	udiv	r8, r2, r9
    c548:	fb09 2218 	mls	r2, r9, r8, r2
    c54c:	fb08 fe0e 	mul.w	lr, r8, lr
    c550:	ea43 4202 	orr.w	r2, r3, r2, lsl #16
    c554:	4596      	cmp	lr, r2
    c556:	d92a      	bls.n	c5ae <__udivmoddi4+0x29e>
    c558:	18a2      	adds	r2, r4, r2
    c55a:	f108 33ff 	add.w	r3, r8, #4294967295
    c55e:	d204      	bcs.n	c56a <__udivmoddi4+0x25a>
    c560:	4596      	cmp	lr, r2
    c562:	d902      	bls.n	c56a <__udivmoddi4+0x25a>
    c564:	f1a8 0302 	sub.w	r3, r8, #2
    c568:	4422      	add	r2, r4
    c56a:	ea43 4000 	orr.w	r0, r3, r0, lsl #16
    c56e:	fba0 9305 	umull	r9, r3, r0, r5
    c572:	eba2 020e 	sub.w	r2, r2, lr
    c576:	429a      	cmp	r2, r3
    c578:	46ce      	mov	lr, r9
    c57a:	4698      	mov	r8, r3
    c57c:	d302      	bcc.n	c584 <__udivmoddi4+0x274>
    c57e:	d106      	bne.n	c58e <__udivmoddi4+0x27e>
    c580:	454f      	cmp	r7, r9
    c582:	d204      	bcs.n	c58e <__udivmoddi4+0x27e>
    c584:	ebb9 0e05 	subs.w	lr, r9, r5
    c588:	eb63 0804 	sbc.w	r8, r3, r4
    c58c:	3801      	subs	r0, #1
    c58e:	b186      	cbz	r6, c5b2 <__udivmoddi4+0x2a2>
    c590:	ebb7 030e 	subs.w	r3, r7, lr
    c594:	eb62 0708 	sbc.w	r7, r2, r8
    c598:	fa07 fc0c 	lsl.w	ip, r7, ip
    c59c:	40cb      	lsrs	r3, r1
    c59e:	ea4c 0303 	orr.w	r3, ip, r3
    c5a2:	40cf      	lsrs	r7, r1
    c5a4:	e9c6 3700 	strd	r3, r7, [r6]
    c5a8:	e79c      	b.n	c4e4 <__udivmoddi4+0x1d4>
    c5aa:	4640      	mov	r0, r8
    c5ac:	e7c7      	b.n	c53e <__udivmoddi4+0x22e>
    c5ae:	4643      	mov	r3, r8
    c5b0:	e7db      	b.n	c56a <__udivmoddi4+0x25a>
    c5b2:	4631      	mov	r1, r6
    c5b4:	e6fd      	b.n	c3b2 <__udivmoddi4+0xa2>
	...

0000c5b8 <main>:

#include <zephyr.h>

void main(void)
{
	printk("Hello World! %s\n", CONFIG_BOARD);
    c5b8:	4901      	ldr	r1, [pc, #4]	; (c5c0 <main+0x8>)
    c5ba:	4802      	ldr	r0, [pc, #8]	; (c5c4 <main+0xc>)
    c5bc:	f003 bd0a 	b.w	ffd4 <printk>
    c5c0:	00010c7c 	.word	0x00010c7c
    c5c4:	00010c8d 	.word	0x00010c8d

0000c5c8 <char_out>:

static int char_out(int c, void *ctx_p)
{
	struct out_context *ctx = ctx_p;

	ctx->count++;
    c5c8:	680b      	ldr	r3, [r1, #0]
    c5ca:	3301      	adds	r3, #1
    c5cc:	600b      	str	r3, [r1, #0]
	return _char_out(c);
    c5ce:	4b01      	ldr	r3, [pc, #4]	; (c5d4 <char_out+0xc>)
    c5d0:	681b      	ldr	r3, [r3, #0]
    c5d2:	4718      	bx	r3
    c5d4:	20000000 	.word	0x20000000

0000c5d8 <__printk_hook_install>:
	_char_out = fn;
    c5d8:	4b01      	ldr	r3, [pc, #4]	; (c5e0 <__printk_hook_install+0x8>)
    c5da:	6018      	str	r0, [r3, #0]
}
    c5dc:	4770      	bx	lr
    c5de:	bf00      	nop
    c5e0:	20000000 	.word	0x20000000

0000c5e4 <vprintk>:
}

void vprintk(const char *fmt, va_list ap)
{
    c5e4:	b507      	push	{r0, r1, r2, lr}
    c5e6:	460b      	mov	r3, r1

		if (ctx.buf_count) {
			buf_flush(&ctx);
		}
	} else {
		struct out_context ctx = { 0 };
    c5e8:	2100      	movs	r1, #0
{
    c5ea:	4602      	mov	r2, r0
		struct out_context ctx = { 0 };
    c5ec:	9101      	str	r1, [sp, #4]
#ifdef CONFIG_PRINTK_SYNC
		k_spinlock_key_t key = k_spin_lock(&lock);
#endif

		cbvprintf(char_out, &ctx, fmt, ap);
    c5ee:	4803      	ldr	r0, [pc, #12]	; (c5fc <vprintk+0x18>)
    c5f0:	a901      	add	r1, sp, #4
    c5f2:	f000 f8e5 	bl	c7c0 <cbvprintf>

#ifdef CONFIG_PRINTK_SYNC
		k_spin_unlock(&lock, key);
#endif
	}
}
    c5f6:	b003      	add	sp, #12
    c5f8:	f85d fb04 	ldr.w	pc, [sp], #4
    c5fc:	0000c5c9 	.word	0x0000c5c9

0000c600 <process_event>:
 * regions.
 */
static void process_event(struct onoff_manager *mgr,
			  int evt,
			  k_spinlock_key_t key)
{
    c600:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
	sys_slist_t clients;
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    c604:	f8b0 9018 	ldrh.w	r9, [r0, #24]
	__ASSERT_NO_MSG(evt != EVT_NOP);

	/* If this is a nested call record the event for processing in
	 * the top invocation.
	 */
	if (processing) {
    c608:	f019 0808 	ands.w	r8, r9, #8
{
    c60c:	4604      	mov	r4, r0
    c60e:	4693      	mov	fp, r2
	if (processing) {
    c610:	d00d      	beq.n	c62e <process_event+0x2e>
		if (evt == EVT_COMPLETE) {
    c612:	2901      	cmp	r1, #1
			mgr->flags |= ONOFF_FLAG_COMPLETE;
    c614:	bf0c      	ite	eq
    c616:	f049 0910 	orreq.w	r9, r9, #16
		} else {
			__ASSERT_NO_MSG(evt == EVT_RECHECK);

			mgr->flags |= ONOFF_FLAG_RECHECK;
    c61a:	f049 0920 	orrne.w	r9, r9, #32
    c61e:	f8a0 9018 	strh.w	r9, [r0, #24]
	__asm__ volatile(
		"cpsie i;"
		"isb"
		: : : "memory");
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	__asm__ volatile(
    c622:	f38b 8811 	msr	BASEPRI, fp
    c626:	f3bf 8f6f 	isb	sy
		state = mgr->flags & ONOFF_STATE_MASK;
	} while (evt != EVT_NOP);

out:
	k_spin_unlock(&mgr->lock, key);
}
    c62a:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    c62e:	f009 0907 	and.w	r9, r9, #7
		if (evt == EVT_RECHECK) {
    c632:	2902      	cmp	r1, #2
    c634:	d107      	bne.n	c646 <process_event+0x46>
			evt = process_recheck(mgr);
    c636:	4620      	mov	r0, r4
    c638:	f003 fcd9 	bl	ffee <process_recheck>
		if (evt == EVT_NOP) {
    c63c:	2800      	cmp	r0, #0
    c63e:	d0f0      	beq.n	c622 <process_event+0x22>
		if (evt == EVT_COMPLETE) {
    c640:	2801      	cmp	r0, #1
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    c642:	8b23      	ldrh	r3, [r4, #24]
		if (evt == EVT_COMPLETE) {
    c644:	d14e      	bne.n	c6e4 <process_event+0xe4>
			res = mgr->last_res;
    c646:	6967      	ldr	r7, [r4, #20]
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    c648:	8b21      	ldrh	r1, [r4, #24]
	if (res < 0) {
    c64a:	2f00      	cmp	r7, #0
    c64c:	da15      	bge.n	c67a <process_event+0x7a>
		*clients = mgr->clients;
    c64e:	6825      	ldr	r5, [r4, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    c650:	f021 0107 	bic.w	r1, r1, #7
 * @param list A pointer on the list to initialize
 */
static inline void sys_slist_init(sys_slist_t *list)
{
	list->head = NULL;
	list->tail = NULL;
    c654:	e9c4 8800 	strd	r8, r8, [r4]
    c658:	f041 0101 	orr.w	r1, r1, #1
	mgr->flags = (state & ONOFF_STATE_MASK)
    c65c:	8321      	strh	r1, [r4, #24]
		onoff_transition_fn transit = NULL;
    c65e:	2600      	movs	r6, #0
		bool do_monitors = (state != (mgr->flags & ONOFF_STATE_MASK))
    c660:	8b21      	ldrh	r1, [r4, #24]
    c662:	f001 0a07 	and.w	sl, r1, #7
				   && !sys_slist_is_empty(&mgr->monitors);
    c666:	45ca      	cmp	sl, r9
    c668:	d002      	beq.n	c670 <process_event+0x70>
		if (do_monitors
    c66a:	68a3      	ldr	r3, [r4, #8]
    c66c:	2b00      	cmp	r3, #0
    c66e:	d15a      	bne.n	c726 <process_event+0x126>
		    || !sys_slist_is_empty(&clients)
    c670:	b90d      	cbnz	r5, c676 <process_event+0x76>
		    || (transit != NULL)) {
    c672:	2e00      	cmp	r6, #0
    c674:	d071      	beq.n	c75a <process_event+0x15a>
    c676:	2300      	movs	r3, #0
    c678:	e056      	b.n	c728 <process_event+0x128>
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    c67a:	f001 0307 	and.w	r3, r1, #7
		   || (state == ONOFF_STATE_RESETTING)) {
    c67e:	1f5a      	subs	r2, r3, #5
	} else if ((state == ONOFF_STATE_TO_ON)
    c680:	2a01      	cmp	r2, #1
    c682:	d81e      	bhi.n	c6c2 <process_event+0xc2>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    c684:	f021 0107 	bic.w	r1, r1, #7
		if (state == ONOFF_STATE_TO_ON) {
    c688:	2b06      	cmp	r3, #6
		*clients = mgr->clients;
    c68a:	6825      	ldr	r5, [r4, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    c68c:	b289      	uxth	r1, r1
    c68e:	e9c4 8800 	strd	r8, r8, [r4]
		if (state == ONOFF_STATE_TO_ON) {
    c692:	d10a      	bne.n	c6aa <process_event+0xaa>
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
    c694:	b13d      	cbz	r5, c6a6 <process_event+0xa6>
    c696:	8b63      	ldrh	r3, [r4, #26]
    c698:	462a      	mov	r2, r5

#define SYS_SLIST_STATIC_INIT(ptr_to_list) {NULL, NULL}

static inline sys_snode_t *z_snode_next_peek(sys_snode_t *node)
{
	return node->next;
    c69a:	6812      	ldr	r2, [r2, #0]
				mgr->refs += 1U;
    c69c:	3301      	adds	r3, #1
    c69e:	b29b      	uxth	r3, r3
			SYS_SLIST_FOR_EACH_CONTAINER(clients, cp, node) {
    c6a0:	2a00      	cmp	r2, #0
    c6a2:	d1fa      	bne.n	c69a <process_event+0x9a>
    c6a4:	8363      	strh	r3, [r4, #26]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    c6a6:	f041 0102 	orr.w	r1, r1, #2
	mgr->flags = (state & ONOFF_STATE_MASK)
    c6aa:	8321      	strh	r1, [r4, #24]
		if (process_recheck(mgr) != EVT_NOP) {
    c6ac:	4620      	mov	r0, r4
    c6ae:	f003 fc9e 	bl	ffee <process_recheck>
    c6b2:	4606      	mov	r6, r0
    c6b4:	2800      	cmp	r0, #0
    c6b6:	d0d3      	beq.n	c660 <process_event+0x60>
			mgr->flags |= ONOFF_FLAG_RECHECK;
    c6b8:	8b23      	ldrh	r3, [r4, #24]
    c6ba:	f043 0320 	orr.w	r3, r3, #32
    c6be:	8323      	strh	r3, [r4, #24]
    c6c0:	e7cd      	b.n	c65e <process_event+0x5e>
	} else if (state == ONOFF_STATE_TO_OFF) {
    c6c2:	2b04      	cmp	r3, #4
    c6c4:	d10c      	bne.n	c6e0 <process_event+0xe0>
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    c6c6:	f021 0107 	bic.w	r1, r1, #7
    c6ca:	b289      	uxth	r1, r1
	mgr->flags = (state & ONOFF_STATE_MASK)
    c6cc:	8321      	strh	r1, [r4, #24]
		if (process_recheck(mgr) != EVT_NOP) {
    c6ce:	4620      	mov	r0, r4
    c6d0:	f003 fc8d 	bl	ffee <process_recheck>
    c6d4:	4605      	mov	r5, r0
    c6d6:	2800      	cmp	r0, #0
    c6d8:	d0c1      	beq.n	c65e <process_event+0x5e>
			mgr->flags |= ONOFF_FLAG_RECHECK;
    c6da:	f041 0120 	orr.w	r1, r1, #32
    c6de:	8321      	strh	r1, [r4, #24]
    c6e0:	2500      	movs	r5, #0
    c6e2:	e7bc      	b.n	c65e <process_event+0x5e>
		} else if (evt == EVT_START) {
    c6e4:	2803      	cmp	r0, #3
    c6e6:	d109      	bne.n	c6fc <process_event+0xfc>
			transit = mgr->transitions->start;
    c6e8:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    c6ea:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->start;
    c6ee:	6816      	ldr	r6, [r2, #0]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    c6f0:	f043 0306 	orr.w	r3, r3, #6
	mgr->flags = (state & ONOFF_STATE_MASK)
    c6f4:	8323      	strh	r3, [r4, #24]
}
    c6f6:	2500      	movs	r5, #0
		res = 0;
    c6f8:	462f      	mov	r7, r5
    c6fa:	e7b1      	b.n	c660 <process_event+0x60>
		} else if (evt == EVT_STOP) {
    c6fc:	2804      	cmp	r0, #4
    c6fe:	d106      	bne.n	c70e <process_event+0x10e>
			transit = mgr->transitions->stop;
    c700:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    c702:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->stop;
    c706:	6856      	ldr	r6, [r2, #4]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    c708:	f043 0304 	orr.w	r3, r3, #4
    c70c:	e7f2      	b.n	c6f4 <process_event+0xf4>
		} else if (evt == EVT_RESET) {
    c70e:	2805      	cmp	r0, #5
    c710:	d106      	bne.n	c720 <process_event+0x120>
			transit = mgr->transitions->reset;
    c712:	6922      	ldr	r2, [r4, #16]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    c714:	f023 0307 	bic.w	r3, r3, #7
			transit = mgr->transitions->reset;
    c718:	6896      	ldr	r6, [r2, #8]
		     | (mgr->flags & ~ONOFF_STATE_MASK);
    c71a:	f043 0305 	orr.w	r3, r3, #5
    c71e:	e7e9      	b.n	c6f4 <process_event+0xf4>
    c720:	2500      	movs	r5, #0
		onoff_transition_fn transit = NULL;
    c722:	462e      	mov	r6, r5
    c724:	e7e8      	b.n	c6f8 <process_event+0xf8>
				   && !sys_slist_is_empty(&mgr->monitors);
    c726:	2301      	movs	r3, #1
			uint32_t flags = mgr->flags | ONOFF_FLAG_PROCESSING;
    c728:	f041 0108 	orr.w	r1, r1, #8
			mgr->flags = flags;
    c72c:	8321      	strh	r1, [r4, #24]
    c72e:	f38b 8811 	msr	BASEPRI, fp
    c732:	f3bf 8f6f 	isb	sy
			if (do_monitors) {
    c736:	b9fb      	cbnz	r3, c778 <process_event+0x178>
	while (!sys_slist_is_empty(list)) {
    c738:	bb85      	cbnz	r5, c79c <process_event+0x19c>
			if (transit != NULL) {
    c73a:	b116      	cbz	r6, c742 <process_event+0x142>
				transit(mgr, transition_complete);
    c73c:	491f      	ldr	r1, [pc, #124]	; (c7bc <process_event+0x1bc>)
    c73e:	4620      	mov	r0, r4
    c740:	47b0      	blx	r6
	__asm__ volatile(
    c742:	f04f 0320 	mov.w	r3, #32
    c746:	f3ef 8b11 	mrs	fp, BASEPRI
    c74a:	f383 8812 	msr	BASEPRI_MAX, r3
    c74e:	f3bf 8f6f 	isb	sy
			mgr->flags &= ~ONOFF_FLAG_PROCESSING;
    c752:	8b23      	ldrh	r3, [r4, #24]
    c754:	f023 0308 	bic.w	r3, r3, #8
    c758:	8323      	strh	r3, [r4, #24]
		if ((mgr->flags & ONOFF_FLAG_COMPLETE) != 0) {
    c75a:	8b23      	ldrh	r3, [r4, #24]
    c75c:	06da      	lsls	r2, r3, #27
    c75e:	d525      	bpl.n	c7ac <process_event+0x1ac>
			mgr->flags &= ~ONOFF_FLAG_COMPLETE;
    c760:	f023 0310 	bic.w	r3, r3, #16
    c764:	8323      	strh	r3, [r4, #24]
			evt = EVT_COMPLETE;
    c766:	2101      	movs	r1, #1
		state = mgr->flags & ONOFF_STATE_MASK;
    c768:	f8b4 9018 	ldrh.w	r9, [r4, #24]
    c76c:	f009 0907 	and.w	r9, r9, #7
	} while (evt != EVT_NOP);
    c770:	2900      	cmp	r1, #0
    c772:	f47f af5e 	bne.w	c632 <process_event+0x32>
out:
    c776:	e754      	b.n	c622 <process_event+0x22>
 *
 * @return A pointer on the first node of the list (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_head(sys_slist_t *list)
{
	return list->head;
    c778:	68a1      	ldr	r1, [r4, #8]
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
    c77a:	2900      	cmp	r1, #0
    c77c:	d0dc      	beq.n	c738 <process_event+0x138>
	return node->next;
    c77e:	f8d1 9000 	ldr.w	r9, [r1]
		mon->callback(mgr, mon, state, res);
    c782:	f8d1 b004 	ldr.w	fp, [r1, #4]
    c786:	463b      	mov	r3, r7
    c788:	4652      	mov	r2, sl
    c78a:	4620      	mov	r0, r4
    c78c:	47d8      	blx	fp
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(mlist, mon, tmp, node) {
    c78e:	f1b9 0f00 	cmp.w	r9, #0
    c792:	d0d1      	beq.n	c738 <process_event+0x138>
    c794:	4649      	mov	r1, r9
    c796:	f8d9 9000 	ldr.w	r9, [r9]
    c79a:	e7f2      	b.n	c782 <process_event+0x182>
    c79c:	4629      	mov	r1, r5
		notify_one(mgr, cli, state, res);
    c79e:	463b      	mov	r3, r7
    c7a0:	4652      	mov	r2, sl
    c7a2:	4620      	mov	r0, r4
    c7a4:	682d      	ldr	r5, [r5, #0]
    c7a6:	f003 fc3e 	bl	10026 <notify_one>
    c7aa:	e7c5      	b.n	c738 <process_event+0x138>
		} else if ((mgr->flags & ONOFF_FLAG_RECHECK) != 0) {
    c7ac:	f013 0120 	ands.w	r1, r3, #32
			mgr->flags &= ~ONOFF_FLAG_RECHECK;
    c7b0:	bf1e      	ittt	ne
    c7b2:	f023 0320 	bicne.w	r3, r3, #32
    c7b6:	8323      	strhne	r3, [r4, #24]
			evt = EVT_RECHECK;
    c7b8:	2102      	movne	r1, #2
    c7ba:	e7d5      	b.n	c768 <process_event+0x168>
    c7bc:	00010053 	.word	0x00010053

0000c7c0 <cbvprintf>:

	return (int)count;
}

int cbvprintf(cbprintf_cb out, void *ctx, const char *fp, va_list ap)
{
    c7c0:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    c7c4:	b091      	sub	sp, #68	; 0x44
    c7c6:	468b      	mov	fp, r1
    c7c8:	9002      	str	r0, [sp, #8]
    c7ca:	4692      	mov	sl, r2
    c7cc:	461c      	mov	r4, r3
	char buf[CONVERTED_BUFLEN];
	size_t count = 0;
    c7ce:	2500      	movs	r5, #0
		return rc; \
	} \
	count += rc; \
} while (false)

	while (*fp != 0) {
    c7d0:	f89a 0000 	ldrb.w	r0, [sl]
    c7d4:	b908      	cbnz	r0, c7da <cbvprintf+0x1a>
			OUTC(' ');
			--width;
		}
	}

	return count;
    c7d6:	4628      	mov	r0, r5
    c7d8:	e35f      	b.n	ce9a <cbvprintf+0x6da>
		if (*fp != '%') {
    c7da:	2825      	cmp	r0, #37	; 0x25
			OUTC(*fp++);
    c7dc:	f10a 0701 	add.w	r7, sl, #1
		if (*fp != '%') {
    c7e0:	d007      	beq.n	c7f2 <cbvprintf+0x32>
			OUTC('%');
    c7e2:	9b02      	ldr	r3, [sp, #8]
    c7e4:	4659      	mov	r1, fp
    c7e6:	4798      	blx	r3
    c7e8:	2800      	cmp	r0, #0
    c7ea:	f2c0 8356 	blt.w	ce9a <cbvprintf+0x6da>
    c7ee:	3501      	adds	r5, #1
			break;
    c7f0:	e212      	b.n	cc18 <cbvprintf+0x458>
		} state = {
    c7f2:	2218      	movs	r2, #24
    c7f4:	2100      	movs	r1, #0
    c7f6:	a80a      	add	r0, sp, #40	; 0x28
    c7f8:	f003 fd41 	bl	1027e <memset>
	if (*sp == '%') {
    c7fc:	f89a 3001 	ldrb.w	r3, [sl, #1]
    c800:	2b25      	cmp	r3, #37	; 0x25
    c802:	d078      	beq.n	c8f6 <cbvprintf+0x136>
    c804:	2200      	movs	r2, #0
    c806:	4610      	mov	r0, r2
    c808:	4696      	mov	lr, r2
    c80a:	4694      	mov	ip, r2
    c80c:	4616      	mov	r6, r2
    c80e:	4639      	mov	r1, r7
		switch (*sp) {
    c810:	f817 3b01 	ldrb.w	r3, [r7], #1
    c814:	2b2b      	cmp	r3, #43	; 0x2b
    c816:	f000 809d 	beq.w	c954 <cbvprintf+0x194>
    c81a:	f200 8094 	bhi.w	c946 <cbvprintf+0x186>
    c81e:	2b20      	cmp	r3, #32
    c820:	f000 809b 	beq.w	c95a <cbvprintf+0x19a>
    c824:	2b23      	cmp	r3, #35	; 0x23
    c826:	f000 809b 	beq.w	c960 <cbvprintf+0x1a0>
    c82a:	b12e      	cbz	r6, c838 <cbvprintf+0x78>
    c82c:	f89d 6030 	ldrb.w	r6, [sp, #48]	; 0x30
    c830:	f046 0604 	orr.w	r6, r6, #4
    c834:	f88d 6030 	strb.w	r6, [sp, #48]	; 0x30
    c838:	f1bc 0f00 	cmp.w	ip, #0
    c83c:	d005      	beq.n	c84a <cbvprintf+0x8a>
    c83e:	f89d 6030 	ldrb.w	r6, [sp, #48]	; 0x30
    c842:	f046 0608 	orr.w	r6, r6, #8
    c846:	f88d 6030 	strb.w	r6, [sp, #48]	; 0x30
    c84a:	f1be 0f00 	cmp.w	lr, #0
    c84e:	d005      	beq.n	c85c <cbvprintf+0x9c>
    c850:	f89d 6030 	ldrb.w	r6, [sp, #48]	; 0x30
    c854:	f046 0610 	orr.w	r6, r6, #16
    c858:	f88d 6030 	strb.w	r6, [sp, #48]	; 0x30
    c85c:	b128      	cbz	r0, c86a <cbvprintf+0xaa>
    c85e:	f89d 0030 	ldrb.w	r0, [sp, #48]	; 0x30
    c862:	f040 0020 	orr.w	r0, r0, #32
    c866:	f88d 0030 	strb.w	r0, [sp, #48]	; 0x30
    c86a:	b12a      	cbz	r2, c878 <cbvprintf+0xb8>
    c86c:	f89d 2030 	ldrb.w	r2, [sp, #48]	; 0x30
    c870:	f042 0240 	orr.w	r2, r2, #64	; 0x40
    c874:	f88d 2030 	strb.w	r2, [sp, #48]	; 0x30
	if (conv->flag_zero && conv->flag_dash) {
    c878:	f89d 2030 	ldrb.w	r2, [sp, #48]	; 0x30
    c87c:	f002 0044 	and.w	r0, r2, #68	; 0x44
    c880:	2844      	cmp	r0, #68	; 0x44
    c882:	d103      	bne.n	c88c <cbvprintf+0xcc>
		conv->flag_zero = false;
    c884:	f36f 1286 	bfc	r2, #6, #1
    c888:	f88d 2030 	strb.w	r2, [sp, #48]	; 0x30
	conv->width_present = true;
    c88c:	f89d 2030 	ldrb.w	r2, [sp, #48]	; 0x30
	if (*sp == '*') {
    c890:	2b2a      	cmp	r3, #42	; 0x2a
	conv->width_present = true;
    c892:	f042 0280 	orr.w	r2, r2, #128	; 0x80
    c896:	f88d 2030 	strb.w	r2, [sp, #48]	; 0x30
	if (*sp == '*') {
    c89a:	d17b      	bne.n	c994 <cbvprintf+0x1d4>
		conv->width_star = true;
    c89c:	f89d 2031 	ldrb.w	r2, [sp, #49]	; 0x31
    c8a0:	f042 0201 	orr.w	r2, r2, #1
			++sp;
    c8a4:	1c4b      	adds	r3, r1, #1
		conv->width_star = true;
    c8a6:	f88d 2031 	strb.w	r2, [sp, #49]	; 0x31
	conv->prec_present = (*sp == '.');
    c8aa:	781a      	ldrb	r2, [r3, #0]
    c8ac:	2a2e      	cmp	r2, #46	; 0x2e
    c8ae:	f89d 2031 	ldrb.w	r2, [sp, #49]	; 0x31
    c8b2:	bf0c      	ite	eq
    c8b4:	2101      	moveq	r1, #1
    c8b6:	2100      	movne	r1, #0
    c8b8:	f361 0241 	bfi	r2, r1, #1, #1
    c8bc:	f88d 2031 	strb.w	r2, [sp, #49]	; 0x31
	if (!conv->prec_present) {
    c8c0:	d174      	bne.n	c9ac <cbvprintf+0x1ec>
	if (*sp == '*') {
    c8c2:	785a      	ldrb	r2, [r3, #1]
    c8c4:	2a2a      	cmp	r2, #42	; 0x2a
    c8c6:	d06a      	beq.n	c99e <cbvprintf+0x1de>
	++sp;
    c8c8:	3301      	adds	r3, #1
	size_t val = 0;
    c8ca:	2100      	movs	r1, #0
		val = 10U * val + *sp++ - '0';
    c8cc:	260a      	movs	r6, #10
			(((unsigned)c) <= (unsigned)'~'));
}

static inline int isdigit(int a)
{
	return (int)(((unsigned)(a)-(unsigned)'0') < 10U);
    c8ce:	4618      	mov	r0, r3
    c8d0:	f810 2b01 	ldrb.w	r2, [r0], #1
    c8d4:	f1a2 0730 	sub.w	r7, r2, #48	; 0x30
	while (isdigit((int)(unsigned char)*sp)) {
    c8d8:	2f09      	cmp	r7, #9
    c8da:	f240 808e 	bls.w	c9fa <cbvprintf+0x23a>
	conv->unsupported |= ((conv->prec_value < 0)
    c8de:	f89d 2030 	ldrb.w	r2, [sp, #48]	; 0x30
	conv->prec_value = prec;
    c8e2:	910e      	str	r1, [sp, #56]	; 0x38
	conv->unsupported |= ((conv->prec_value < 0)
    c8e4:	f3c2 0040 	ubfx	r0, r2, #1, #1
    c8e8:	ea40 71d1 	orr.w	r1, r0, r1, lsr #31
    c8ec:	f361 0241 	bfi	r2, r1, #1, #1
    c8f0:	f88d 2030 	strb.w	r2, [sp, #48]	; 0x30
	return sp;
    c8f4:	e05a      	b.n	c9ac <cbvprintf+0x1ec>
		conv->specifier = *sp++;
    c8f6:	f10a 0702 	add.w	r7, sl, #2
    c8fa:	f88d 3033 	strb.w	r3, [sp, #51]	; 0x33
		if (conv->width_star) {
    c8fe:	f89d 3031 	ldrb.w	r3, [sp, #49]	; 0x31
    c902:	07d9      	lsls	r1, r3, #31
    c904:	f140 8149 	bpl.w	cb9a <cbvprintf+0x3da>
			width = va_arg(ap, int);
    c908:	f854 9b04 	ldr.w	r9, [r4], #4
			if (width < 0) {
    c90c:	f1b9 0f00 	cmp.w	r9, #0
    c910:	da07      	bge.n	c922 <cbvprintf+0x162>
				conv->flag_dash = true;
    c912:	f89d 2030 	ldrb.w	r2, [sp, #48]	; 0x30
    c916:	f042 0204 	orr.w	r2, r2, #4
    c91a:	f88d 2030 	strb.w	r2, [sp, #48]	; 0x30
				width = -width;
    c91e:	f1c9 0900 	rsb	r9, r9, #0
		if (conv->prec_star) {
    c922:	075a      	lsls	r2, r3, #29
    c924:	f140 8142 	bpl.w	cbac <cbvprintf+0x3ec>
			int arg = va_arg(ap, int);
    c928:	f854 8b04 	ldr.w	r8, [r4], #4
			if (arg < 0) {
    c92c:	f1b8 0f00 	cmp.w	r8, #0
    c930:	f280 8141 	bge.w	cbb6 <cbvprintf+0x3f6>
				conv->prec_present = false;
    c934:	f89d 3031 	ldrb.w	r3, [sp, #49]	; 0x31
    c938:	f36f 0341 	bfc	r3, #1, #1
    c93c:	f88d 3031 	strb.w	r3, [sp, #49]	; 0x31
		int precision = -1;
    c940:	f04f 38ff 	mov.w	r8, #4294967295
    c944:	e137      	b.n	cbb6 <cbvprintf+0x3f6>
		switch (*sp) {
    c946:	2b2d      	cmp	r3, #45	; 0x2d
    c948:	d00c      	beq.n	c964 <cbvprintf+0x1a4>
    c94a:	2b30      	cmp	r3, #48	; 0x30
    c94c:	f47f af6d 	bne.w	c82a <cbvprintf+0x6a>
			conv->flag_zero = true;
    c950:	2201      	movs	r2, #1
	} while (loop);
    c952:	e75c      	b.n	c80e <cbvprintf+0x4e>
			conv->flag_plus = true;
    c954:	f04f 0c01 	mov.w	ip, #1
    c958:	e759      	b.n	c80e <cbvprintf+0x4e>
			conv->flag_space = true;
    c95a:	f04f 0e01 	mov.w	lr, #1
    c95e:	e756      	b.n	c80e <cbvprintf+0x4e>
			conv->flag_hash = true;
    c960:	2001      	movs	r0, #1
    c962:	e754      	b.n	c80e <cbvprintf+0x4e>
		switch (*sp) {
    c964:	2601      	movs	r6, #1
    c966:	e752      	b.n	c80e <cbvprintf+0x4e>
		val = 10U * val + *sp++ - '0';
    c968:	fb0c 0202 	mla	r2, ip, r2, r0
    c96c:	3a30      	subs	r2, #48	; 0x30
    c96e:	4633      	mov	r3, r6
    c970:	461e      	mov	r6, r3
    c972:	f816 0b01 	ldrb.w	r0, [r6], #1
    c976:	f1a0 0730 	sub.w	r7, r0, #48	; 0x30
	while (isdigit((int)(unsigned char)*sp)) {
    c97a:	2f09      	cmp	r7, #9
    c97c:	d9f4      	bls.n	c968 <cbvprintf+0x1a8>
	if (sp != wp) {
    c97e:	4299      	cmp	r1, r3
    c980:	d093      	beq.n	c8aa <cbvprintf+0xea>
		conv->unsupported |= ((conv->width_value < 0)
    c982:	f89d 1030 	ldrb.w	r1, [sp, #48]	; 0x30
		conv->width_value = width;
    c986:	920d      	str	r2, [sp, #52]	; 0x34
				      || (width != (size_t)conv->width_value));
    c988:	0fd2      	lsrs	r2, r2, #31
		conv->unsupported |= ((conv->width_value < 0)
    c98a:	f362 0141 	bfi	r1, r2, #1, #1
    c98e:	f88d 1030 	strb.w	r1, [sp, #48]	; 0x30
    c992:	e78a      	b.n	c8aa <cbvprintf+0xea>
    c994:	460b      	mov	r3, r1
	size_t val = 0;
    c996:	2200      	movs	r2, #0
		val = 10U * val + *sp++ - '0';
    c998:	f04f 0c0a 	mov.w	ip, #10
    c99c:	e7e8      	b.n	c970 <cbvprintf+0x1b0>
		conv->prec_star = true;
    c99e:	f89d 2031 	ldrb.w	r2, [sp, #49]	; 0x31
    c9a2:	f042 0204 	orr.w	r2, r2, #4
    c9a6:	f88d 2031 	strb.w	r2, [sp, #49]	; 0x31
		return ++sp;
    c9aa:	3302      	adds	r3, #2
	switch (*sp) {
    c9ac:	461f      	mov	r7, r3
    c9ae:	f817 2b01 	ldrb.w	r2, [r7], #1
    c9b2:	2a6c      	cmp	r2, #108	; 0x6c
    c9b4:	d041      	beq.n	ca3a <cbvprintf+0x27a>
    c9b6:	d825      	bhi.n	ca04 <cbvprintf+0x244>
    c9b8:	2a68      	cmp	r2, #104	; 0x68
    c9ba:	d02b      	beq.n	ca14 <cbvprintf+0x254>
    c9bc:	2a6a      	cmp	r2, #106	; 0x6a
    c9be:	d046      	beq.n	ca4e <cbvprintf+0x28e>
    c9c0:	2a4c      	cmp	r2, #76	; 0x4c
    c9c2:	d04c      	beq.n	ca5e <cbvprintf+0x29e>
    c9c4:	461f      	mov	r7, r3
	conv->specifier = *sp++;
    c9c6:	f817 2b01 	ldrb.w	r2, [r7], #1
		if (conv->length_mod == LENGTH_UPPER_L) {
    c9ca:	f89d 3031 	ldrb.w	r3, [sp, #49]	; 0x31
	conv->specifier = *sp++;
    c9ce:	f88d 2033 	strb.w	r2, [sp, #51]	; 0x33
	switch (conv->specifier) {
    c9d2:	2a78      	cmp	r2, #120	; 0x78
    c9d4:	f200 80d9 	bhi.w	cb8a <cbvprintf+0x3ca>
    c9d8:	2a57      	cmp	r2, #87	; 0x57
    c9da:	d84d      	bhi.n	ca78 <cbvprintf+0x2b8>
    c9dc:	2a41      	cmp	r2, #65	; 0x41
    c9de:	d003      	beq.n	c9e8 <cbvprintf+0x228>
    c9e0:	3a45      	subs	r2, #69	; 0x45
    c9e2:	2a02      	cmp	r2, #2
    c9e4:	f200 80d1 	bhi.w	cb8a <cbvprintf+0x3ca>
		conv->specifier_cat = SPECIFIER_FP;
    c9e8:	f89d 3032 	ldrb.w	r3, [sp, #50]	; 0x32
    c9ec:	2204      	movs	r2, #4
    c9ee:	f362 0302 	bfi	r3, r2, #0, #3
    c9f2:	f88d 3032 	strb.w	r3, [sp, #50]	; 0x32
			unsupported = true;
    c9f6:	2301      	movs	r3, #1
			break;
    c9f8:	e09e      	b.n	cb38 <cbvprintf+0x378>
		val = 10U * val + *sp++ - '0';
    c9fa:	fb06 2101 	mla	r1, r6, r1, r2
    c9fe:	3930      	subs	r1, #48	; 0x30
    ca00:	4603      	mov	r3, r0
    ca02:	e764      	b.n	c8ce <cbvprintf+0x10e>
	switch (*sp) {
    ca04:	2a74      	cmp	r2, #116	; 0x74
    ca06:	d026      	beq.n	ca56 <cbvprintf+0x296>
    ca08:	2a7a      	cmp	r2, #122	; 0x7a
    ca0a:	d1db      	bne.n	c9c4 <cbvprintf+0x204>
		conv->length_mod = LENGTH_Z;
    ca0c:	f89d 3031 	ldrb.w	r3, [sp, #49]	; 0x31
    ca10:	2206      	movs	r2, #6
    ca12:	e00d      	b.n	ca30 <cbvprintf+0x270>
		if (*++sp == 'h') {
    ca14:	785a      	ldrb	r2, [r3, #1]
    ca16:	2a68      	cmp	r2, #104	; 0x68
    ca18:	f89d 2031 	ldrb.w	r2, [sp, #49]	; 0x31
    ca1c:	d106      	bne.n	ca2c <cbvprintf+0x26c>
			conv->length_mod = LENGTH_HH;
    ca1e:	2101      	movs	r1, #1
			conv->length_mod = LENGTH_LL;
    ca20:	f361 02c6 	bfi	r2, r1, #3, #4
    ca24:	f88d 2031 	strb.w	r2, [sp, #49]	; 0x31
			++sp;
    ca28:	1c9f      	adds	r7, r3, #2
    ca2a:	e7cc      	b.n	c9c6 <cbvprintf+0x206>
			conv->length_mod = LENGTH_H;
    ca2c:	4613      	mov	r3, r2
    ca2e:	2202      	movs	r2, #2
		conv->length_mod = LENGTH_T;
    ca30:	f362 03c6 	bfi	r3, r2, #3, #4
    ca34:	f88d 3031 	strb.w	r3, [sp, #49]	; 0x31
		break;
    ca38:	e7c5      	b.n	c9c6 <cbvprintf+0x206>
		if (*++sp == 'l') {
    ca3a:	785a      	ldrb	r2, [r3, #1]
    ca3c:	2a6c      	cmp	r2, #108	; 0x6c
    ca3e:	f89d 2031 	ldrb.w	r2, [sp, #49]	; 0x31
    ca42:	d101      	bne.n	ca48 <cbvprintf+0x288>
			conv->length_mod = LENGTH_LL;
    ca44:	2104      	movs	r1, #4
    ca46:	e7eb      	b.n	ca20 <cbvprintf+0x260>
			conv->length_mod = LENGTH_L;
    ca48:	4613      	mov	r3, r2
    ca4a:	2203      	movs	r2, #3
    ca4c:	e7f0      	b.n	ca30 <cbvprintf+0x270>
		conv->length_mod = LENGTH_J;
    ca4e:	f89d 3031 	ldrb.w	r3, [sp, #49]	; 0x31
    ca52:	2205      	movs	r2, #5
    ca54:	e7ec      	b.n	ca30 <cbvprintf+0x270>
		conv->length_mod = LENGTH_T;
    ca56:	f89d 3031 	ldrb.w	r3, [sp, #49]	; 0x31
    ca5a:	2207      	movs	r2, #7
    ca5c:	e7e8      	b.n	ca30 <cbvprintf+0x270>
		conv->unsupported = true;
    ca5e:	f8bd 3030 	ldrh.w	r3, [sp, #48]	; 0x30
    ca62:	f423 43f0 	bic.w	r3, r3, #30720	; 0x7800
    ca66:	f023 0302 	bic.w	r3, r3, #2
    ca6a:	f443 4380 	orr.w	r3, r3, #16384	; 0x4000
    ca6e:	f043 0302 	orr.w	r3, r3, #2
    ca72:	f8ad 3030 	strh.w	r3, [sp, #48]	; 0x30
		break;
    ca76:	e7a6      	b.n	c9c6 <cbvprintf+0x206>
	switch (conv->specifier) {
    ca78:	f1a2 0158 	sub.w	r1, r2, #88	; 0x58
    ca7c:	2920      	cmp	r1, #32
    ca7e:	f200 8084 	bhi.w	cb8a <cbvprintf+0x3ca>
    ca82:	a001      	add	r0, pc, #4	; (adr r0, ca88 <cbvprintf+0x2c8>)
    ca84:	f850 f021 	ldr.w	pc, [r0, r1, lsl #2]
    ca88:	0000cb4d 	.word	0x0000cb4d
    ca8c:	0000cb8b 	.word	0x0000cb8b
    ca90:	0000cb8b 	.word	0x0000cb8b
    ca94:	0000cb8b 	.word	0x0000cb8b
    ca98:	0000cb8b 	.word	0x0000cb8b
    ca9c:	0000cb8b 	.word	0x0000cb8b
    caa0:	0000cb8b 	.word	0x0000cb8b
    caa4:	0000cb8b 	.word	0x0000cb8b
    caa8:	0000cb8b 	.word	0x0000cb8b
    caac:	0000c9e9 	.word	0x0000c9e9
    cab0:	0000cb8b 	.word	0x0000cb8b
    cab4:	0000cb4d 	.word	0x0000cb4d
    cab8:	0000cb0d 	.word	0x0000cb0d
    cabc:	0000c9e9 	.word	0x0000c9e9
    cac0:	0000c9e9 	.word	0x0000c9e9
    cac4:	0000c9e9 	.word	0x0000c9e9
    cac8:	0000cb8b 	.word	0x0000cb8b
    cacc:	0000cb0d 	.word	0x0000cb0d
    cad0:	0000cb8b 	.word	0x0000cb8b
    cad4:	0000cb8b 	.word	0x0000cb8b
    cad8:	0000cb8b 	.word	0x0000cb8b
    cadc:	0000cb8b 	.word	0x0000cb8b
    cae0:	0000cb55 	.word	0x0000cb55
    cae4:	0000cb4d 	.word	0x0000cb4d
    cae8:	0000cb71 	.word	0x0000cb71
    caec:	0000cb8b 	.word	0x0000cb8b
    caf0:	0000cb8b 	.word	0x0000cb8b
    caf4:	0000cb71 	.word	0x0000cb71
    caf8:	0000cb8b 	.word	0x0000cb8b
    cafc:	0000cb4d 	.word	0x0000cb4d
    cb00:	0000cb8b 	.word	0x0000cb8b
    cb04:	0000cb8b 	.word	0x0000cb8b
    cb08:	0000cb4d 	.word	0x0000cb4d
		conv->specifier_cat = SPECIFIER_SINT;
    cb0c:	f89d 1032 	ldrb.w	r1, [sp, #50]	; 0x32
    cb10:	2001      	movs	r0, #1
		if (conv->length_mod == LENGTH_UPPER_L) {
    cb12:	f003 0378 	and.w	r3, r3, #120	; 0x78
		conv->specifier_cat = SPECIFIER_UINT;
    cb16:	f360 0102 	bfi	r1, r0, #0, #3
		if (conv->length_mod == LENGTH_UPPER_L) {
    cb1a:	2b40      	cmp	r3, #64	; 0x40
		conv->specifier_cat = SPECIFIER_UINT;
    cb1c:	f88d 1032 	strb.w	r1, [sp, #50]	; 0x32
			conv->invalid = true;
    cb20:	bf02      	ittt	eq
    cb22:	f89d 1030 	ldrbeq.w	r1, [sp, #48]	; 0x30
    cb26:	f041 0101 	orreq.w	r1, r1, #1
    cb2a:	f88d 1030 	strbeq.w	r1, [sp, #48]	; 0x30
		if (conv->specifier == 'c') {
    cb2e:	2a63      	cmp	r2, #99	; 0x63
    cb30:	d131      	bne.n	cb96 <cbvprintf+0x3d6>
			unsupported = (conv->length_mod != LENGTH_NONE);
    cb32:	3b00      	subs	r3, #0
    cb34:	bf18      	it	ne
    cb36:	2301      	movne	r3, #1
	conv->unsupported |= unsupported;
    cb38:	f89d 2030 	ldrb.w	r2, [sp, #48]	; 0x30
    cb3c:	f3c2 0140 	ubfx	r1, r2, #1, #1
    cb40:	430b      	orrs	r3, r1
    cb42:	f363 0241 	bfi	r2, r3, #1, #1
    cb46:	f88d 2030 	strb.w	r2, [sp, #48]	; 0x30
	return sp;
    cb4a:	e6d8      	b.n	c8fe <cbvprintf+0x13e>
		conv->specifier_cat = SPECIFIER_UINT;
    cb4c:	f89d 1032 	ldrb.w	r1, [sp, #50]	; 0x32
    cb50:	2002      	movs	r0, #2
    cb52:	e7de      	b.n	cb12 <cbvprintf+0x352>
		conv->specifier_cat = SPECIFIER_PTR;
    cb54:	f89d 2032 	ldrb.w	r2, [sp, #50]	; 0x32
		if (conv->length_mod == LENGTH_UPPER_L) {
    cb58:	f003 0378 	and.w	r3, r3, #120	; 0x78
    cb5c:	f1a3 0040 	sub.w	r0, r3, #64	; 0x40
		conv->specifier_cat = SPECIFIER_PTR;
    cb60:	2103      	movs	r1, #3
    cb62:	f361 0202 	bfi	r2, r1, #0, #3
		if (conv->length_mod == LENGTH_UPPER_L) {
    cb66:	4243      	negs	r3, r0
		conv->specifier_cat = SPECIFIER_PTR;
    cb68:	f88d 2032 	strb.w	r2, [sp, #50]	; 0x32
		if (conv->length_mod == LENGTH_UPPER_L) {
    cb6c:	4143      	adcs	r3, r0
    cb6e:	e7e3      	b.n	cb38 <cbvprintf+0x378>
		conv->specifier_cat = SPECIFIER_PTR;
    cb70:	f89d 2032 	ldrb.w	r2, [sp, #50]	; 0x32
    cb74:	2103      	movs	r1, #3
		if (conv->length_mod != LENGTH_NONE) {
    cb76:	f013 0f78 	tst.w	r3, #120	; 0x78
		conv->specifier_cat = SPECIFIER_PTR;
    cb7a:	f361 0202 	bfi	r2, r1, #0, #3
    cb7e:	f88d 2032 	strb.w	r2, [sp, #50]	; 0x32
		if (conv->length_mod != LENGTH_NONE) {
    cb82:	bf14      	ite	ne
    cb84:	2301      	movne	r3, #1
    cb86:	2300      	moveq	r3, #0
    cb88:	e7d6      	b.n	cb38 <cbvprintf+0x378>
		conv->invalid = true;
    cb8a:	f89d 3030 	ldrb.w	r3, [sp, #48]	; 0x30
    cb8e:	f043 0301 	orr.w	r3, r3, #1
    cb92:	f88d 3030 	strb.w	r3, [sp, #48]	; 0x30
	bool unsupported = false;
    cb96:	2300      	movs	r3, #0
    cb98:	e7ce      	b.n	cb38 <cbvprintf+0x378>
		} else if (conv->width_present) {
    cb9a:	f99d 2030 	ldrsb.w	r2, [sp, #48]	; 0x30
    cb9e:	2a00      	cmp	r2, #0
			width = conv->width_value;
    cba0:	bfb4      	ite	lt
    cba2:	f8dd 9034 	ldrlt.w	r9, [sp, #52]	; 0x34
		int width = -1;
    cba6:	f04f 39ff 	movge.w	r9, #4294967295
    cbaa:	e6ba      	b.n	c922 <cbvprintf+0x162>
		} else if (conv->prec_present) {
    cbac:	079b      	lsls	r3, r3, #30
    cbae:	f57f aec7 	bpl.w	c940 <cbvprintf+0x180>
			precision = conv->prec_value;
    cbb2:	f8dd 8038 	ldr.w	r8, [sp, #56]	; 0x38
			= (enum length_mod_enum)conv->length_mod;
    cbb6:	f89d 1031 	ldrb.w	r1, [sp, #49]	; 0x31
		conv->pad0_value = 0;
    cbba:	2300      	movs	r3, #0
		conv->pad0_pre_exp = 0;
    cbbc:	e9cd 330d 	strd	r3, r3, [sp, #52]	; 0x34
			= (enum specifier_cat_enum)conv->specifier_cat;
    cbc0:	f89d 3032 	ldrb.w	r3, [sp, #50]	; 0x32
		enum specifier_cat_enum specifier_cat
    cbc4:	f003 0307 	and.w	r3, r3, #7
		if (specifier_cat == SPECIFIER_SINT) {
    cbc8:	2b01      	cmp	r3, #1
			= (enum length_mod_enum)conv->length_mod;
    cbca:	f3c1 01c3 	ubfx	r1, r1, #3, #4
		if (specifier_cat == SPECIFIER_SINT) {
    cbce:	d138      	bne.n	cc42 <cbvprintf+0x482>
			switch (length_mod) {
    cbd0:	1ecb      	subs	r3, r1, #3
    cbd2:	2b04      	cmp	r3, #4
    cbd4:	d822      	bhi.n	cc1c <cbvprintf+0x45c>
    cbd6:	e8df f003 	tbb	[pc, r3]
    cbda:	0903      	.short	0x0903
    cbdc:	2109      	.short	0x2109
    cbde:	21          	.byte	0x21
    cbdf:	00          	.byte	0x00
					value->sint = va_arg(ap, long);
    cbe0:	f854 3b04 	ldr.w	r3, [r4], #4
				value->sint = (short)value->sint;
    cbe4:	17da      	asrs	r2, r3, #31
    cbe6:	e9cd 320a 	strd	r3, r2, [sp, #40]	; 0x28
    cbea:	e006      	b.n	cbfa <cbvprintf+0x43a>
					(sint_value_type)va_arg(ap, intmax_t);
    cbec:	3407      	adds	r4, #7
    cbee:	f024 0407 	bic.w	r4, r4, #7
				value->sint =
    cbf2:	e8f4 2302 	ldrd	r2, r3, [r4], #8
    cbf6:	e9cd 230a 	strd	r2, r3, [sp, #40]	; 0x28
		if (conv->invalid || conv->unsupported) {
    cbfa:	f89d 3030 	ldrb.w	r3, [sp, #48]	; 0x30
    cbfe:	f013 0603 	ands.w	r6, r3, #3
    cc02:	d056      	beq.n	ccb2 <cbvprintf+0x4f2>
			OUTS(sp, fp);
    cc04:	9802      	ldr	r0, [sp, #8]
    cc06:	463b      	mov	r3, r7
    cc08:	4652      	mov	r2, sl
    cc0a:	4659      	mov	r1, fp
    cc0c:	f003 faea 	bl	101e4 <outs>
    cc10:	2800      	cmp	r0, #0
    cc12:	f2c0 8142 	blt.w	ce9a <cbvprintf+0x6da>
    cc16:	4405      	add	r5, r0
			continue;
    cc18:	46ba      	mov	sl, r7
    cc1a:	e5d9      	b.n	c7d0 <cbvprintf+0x10>
					(sint_value_type)va_arg(ap, ptrdiff_t);
    cc1c:	f854 3b04 	ldr.w	r3, [r4], #4
			if (length_mod == LENGTH_HH) {
    cc20:	2901      	cmp	r1, #1
					(sint_value_type)va_arg(ap, ptrdiff_t);
    cc22:	ea4f 72e3 	mov.w	r2, r3, asr #31
    cc26:	e9cd 320a 	strd	r3, r2, [sp, #40]	; 0x28
			if (length_mod == LENGTH_HH) {
    cc2a:	d105      	bne.n	cc38 <cbvprintf+0x478>
				value->uint = (unsigned char)value->uint;
    cc2c:	f89d 3028 	ldrb.w	r3, [sp, #40]	; 0x28
				value->uint = (unsigned short)value->uint;
    cc30:	930a      	str	r3, [sp, #40]	; 0x28
    cc32:	2300      	movs	r3, #0
    cc34:	930b      	str	r3, [sp, #44]	; 0x2c
    cc36:	e7e0      	b.n	cbfa <cbvprintf+0x43a>
			} else if (length_mod == LENGTH_H) {
    cc38:	2902      	cmp	r1, #2
    cc3a:	d1de      	bne.n	cbfa <cbvprintf+0x43a>
				value->sint = (short)value->sint;
    cc3c:	f9bd 3028 	ldrsh.w	r3, [sp, #40]	; 0x28
    cc40:	e7d0      	b.n	cbe4 <cbvprintf+0x424>
		} else if (specifier_cat == SPECIFIER_UINT) {
    cc42:	2b02      	cmp	r3, #2
    cc44:	d123      	bne.n	cc8e <cbvprintf+0x4ce>
			switch (length_mod) {
    cc46:	1ecb      	subs	r3, r1, #3
    cc48:	2b04      	cmp	r3, #4
    cc4a:	d813      	bhi.n	cc74 <cbvprintf+0x4b4>
    cc4c:	e8df f003 	tbb	[pc, r3]
    cc50:	120a0a03 	.word	0x120a0a03
    cc54:	12          	.byte	0x12
    cc55:	00          	.byte	0x00
					value->uint = (wchar_t)va_arg(ap,
    cc56:	6822      	ldr	r2, [r4, #0]
    cc58:	920a      	str	r2, [sp, #40]	; 0x28
    cc5a:	2300      	movs	r3, #0
				value->sint = va_arg(ap, int);
    cc5c:	1d20      	adds	r0, r4, #4
					value->uint = (wchar_t)va_arg(ap,
    cc5e:	930b      	str	r3, [sp, #44]	; 0x2c
					(uint_value_type)va_arg(ap, size_t);
    cc60:	4604      	mov	r4, r0
    cc62:	e7ca      	b.n	cbfa <cbvprintf+0x43a>
					(uint_value_type)va_arg(ap,
    cc64:	1de0      	adds	r0, r4, #7
    cc66:	f020 0007 	bic.w	r0, r0, #7
				value->uint =
    cc6a:	e8f0 2302 	ldrd	r2, r3, [r0], #8
    cc6e:	e9cd 230a 	strd	r2, r3, [sp, #40]	; 0x28
				break;
    cc72:	e7f5      	b.n	cc60 <cbvprintf+0x4a0>
					(uint_value_type)va_arg(ap, size_t);
    cc74:	f854 3b04 	ldr.w	r3, [r4], #4
    cc78:	930a      	str	r3, [sp, #40]	; 0x28
			if (length_mod == LENGTH_HH) {
    cc7a:	2901      	cmp	r1, #1
					(uint_value_type)va_arg(ap, size_t);
    cc7c:	f04f 0300 	mov.w	r3, #0
    cc80:	930b      	str	r3, [sp, #44]	; 0x2c
			if (length_mod == LENGTH_HH) {
    cc82:	d0d3      	beq.n	cc2c <cbvprintf+0x46c>
			} else if (length_mod == LENGTH_H) {
    cc84:	2902      	cmp	r1, #2
    cc86:	d1b8      	bne.n	cbfa <cbvprintf+0x43a>
				value->uint = (unsigned short)value->uint;
    cc88:	f8bd 3028 	ldrh.w	r3, [sp, #40]	; 0x28
    cc8c:	e7d0      	b.n	cc30 <cbvprintf+0x470>
		} else if (specifier_cat == SPECIFIER_FP) {
    cc8e:	2b04      	cmp	r3, #4
    cc90:	d109      	bne.n	cca6 <cbvprintf+0x4e6>
					(sint_value_type)va_arg(ap, long long);
    cc92:	1de3      	adds	r3, r4, #7
    cc94:	f023 0307 	bic.w	r3, r3, #7
    cc98:	f103 0408 	add.w	r4, r3, #8
				value->ldbl = va_arg(ap, long double);
    cc9c:	e9d3 2300 	ldrd	r2, r3, [r3]
    cca0:	e9cd 230a 	strd	r2, r3, [sp, #40]	; 0x28
    cca4:	e7a9      	b.n	cbfa <cbvprintf+0x43a>
		} else if (specifier_cat == SPECIFIER_PTR) {
    cca6:	2b03      	cmp	r3, #3
			value->ptr = va_arg(ap, void *);
    cca8:	bf04      	itt	eq
    ccaa:	f854 3b04 	ldreq.w	r3, [r4], #4
    ccae:	930a      	streq	r3, [sp, #40]	; 0x28
    ccb0:	e7a3      	b.n	cbfa <cbvprintf+0x43a>
		switch (conv->specifier) {
    ccb2:	f89d 0033 	ldrb.w	r0, [sp, #51]	; 0x33
    ccb6:	2878      	cmp	r0, #120	; 0x78
    ccb8:	d8ae      	bhi.n	cc18 <cbvprintf+0x458>
    ccba:	2862      	cmp	r0, #98	; 0x62
    ccbc:	d822      	bhi.n	cd04 <cbvprintf+0x544>
    ccbe:	2825      	cmp	r0, #37	; 0x25
    ccc0:	f43f ad8f 	beq.w	c7e2 <cbvprintf+0x22>
    ccc4:	2858      	cmp	r0, #88	; 0x58
    ccc6:	d1a7      	bne.n	cc18 <cbvprintf+0x458>
			bps = encode_uint(value->uint, conv, buf, bpe);
    ccc8:	f10d 0326 	add.w	r3, sp, #38	; 0x26
    cccc:	9300      	str	r3, [sp, #0]
    ccce:	e9dd 010a 	ldrd	r0, r1, [sp, #40]	; 0x28
    ccd2:	ab04      	add	r3, sp, #16
    ccd4:	aa0c      	add	r2, sp, #48	; 0x30
    ccd6:	f003 fa3f 	bl	10158 <encode_uint>
    ccda:	4682      	mov	sl, r0
			if (precision >= 0) {
    ccdc:	f1b8 0f00 	cmp.w	r8, #0
    cce0:	f10d 0026 	add.w	r0, sp, #38	; 0x26
    cce4:	db0c      	blt.n	cd00 <cbvprintf+0x540>
				conv->flag_zero = false;
    cce6:	f89d 2030 	ldrb.w	r2, [sp, #48]	; 0x30
				size_t len = bpe - bps;
    ccea:	eba0 030a 	sub.w	r3, r0, sl
				conv->flag_zero = false;
    ccee:	f36f 1286 	bfc	r2, #6, #1
				if (len < (size_t)precision) {
    ccf2:	4598      	cmp	r8, r3
				conv->flag_zero = false;
    ccf4:	f88d 2030 	strb.w	r2, [sp, #48]	; 0x30
				if (len < (size_t)precision) {
    ccf8:	d902      	bls.n	cd00 <cbvprintf+0x540>
					conv->pad0_value = precision - (int)len;
    ccfa:	eba8 0303 	sub.w	r3, r8, r3
    ccfe:	930d      	str	r3, [sp, #52]	; 0x34
		const char *bpe = buf + sizeof(buf);
    cd00:	4680      	mov	r8, r0
    cd02:	e03d      	b.n	cd80 <cbvprintf+0x5c0>
		switch (conv->specifier) {
    cd04:	3863      	subs	r0, #99	; 0x63
    cd06:	2815      	cmp	r0, #21
    cd08:	d886      	bhi.n	cc18 <cbvprintf+0x458>
    cd0a:	a201      	add	r2, pc, #4	; (adr r2, cd10 <cbvprintf+0x550>)
    cd0c:	f852 f020 	ldr.w	pc, [r2, r0, lsl #2]
    cd10:	0000cd91 	.word	0x0000cd91
    cd14:	0000cdf5 	.word	0x0000cdf5
    cd18:	0000cc19 	.word	0x0000cc19
    cd1c:	0000cc19 	.word	0x0000cc19
    cd20:	0000cc19 	.word	0x0000cc19
    cd24:	0000cc19 	.word	0x0000cc19
    cd28:	0000cdf5 	.word	0x0000cdf5
    cd2c:	0000cc19 	.word	0x0000cc19
    cd30:	0000cc19 	.word	0x0000cc19
    cd34:	0000cc19 	.word	0x0000cc19
    cd38:	0000cc19 	.word	0x0000cc19
    cd3c:	0000ce4f 	.word	0x0000ce4f
    cd40:	0000ce1d 	.word	0x0000ce1d
    cd44:	0000ce21 	.word	0x0000ce21
    cd48:	0000cc19 	.word	0x0000cc19
    cd4c:	0000cc19 	.word	0x0000cc19
    cd50:	0000cd69 	.word	0x0000cd69
    cd54:	0000cc19 	.word	0x0000cc19
    cd58:	0000ce1d 	.word	0x0000ce1d
    cd5c:	0000cc19 	.word	0x0000cc19
    cd60:	0000cc19 	.word	0x0000cc19
    cd64:	0000ce1d 	.word	0x0000ce1d
			if (precision >= 0) {
    cd68:	f1b8 0f00 	cmp.w	r8, #0
			bps = (const char *)value->ptr;
    cd6c:	f8dd a028 	ldr.w	sl, [sp, #40]	; 0x28
			if (precision >= 0) {
    cd70:	db0a      	blt.n	cd88 <cbvprintf+0x5c8>
				len = strnlen(bps, precision);
    cd72:	4641      	mov	r1, r8
    cd74:	4650      	mov	r0, sl
    cd76:	f003 fa6e 	bl	10256 <strnlen>
			bpe = bps + len;
    cd7a:	eb0a 0800 	add.w	r8, sl, r0
		char sign = 0;
    cd7e:	2600      	movs	r6, #0
		if (bps == NULL) {
    cd80:	f1ba 0f00 	cmp.w	sl, #0
    cd84:	d10c      	bne.n	cda0 <cbvprintf+0x5e0>
    cd86:	e747      	b.n	cc18 <cbvprintf+0x458>
				len = strlen(bps);
    cd88:	4650      	mov	r0, sl
    cd8a:	f003 fa5d 	bl	10248 <strlen>
    cd8e:	e7f4      	b.n	cd7a <cbvprintf+0x5ba>
			buf[0] = CHAR_IS_SIGNED ? value->sint : value->uint;
    cd90:	9b0a      	ldr	r3, [sp, #40]	; 0x28
    cd92:	f88d 3010 	strb.w	r3, [sp, #16]
			break;
    cd96:	2600      	movs	r6, #0
			bps = buf;
    cd98:	f10d 0a10 	add.w	sl, sp, #16
			bpe = buf + 1;
    cd9c:	f10d 0811 	add.w	r8, sp, #17
		size_t nj_len = (bpe - bps);
    cda0:	eba8 030a 	sub.w	r3, r8, sl
		if (sign != 0) {
    cda4:	b106      	cbz	r6, cda8 <cbvprintf+0x5e8>
			nj_len += 1U;
    cda6:	3301      	adds	r3, #1
		if (conv->altform_0c) {
    cda8:	f89d 2032 	ldrb.w	r2, [sp, #50]	; 0x32
    cdac:	06d0      	lsls	r0, r2, #27
    cdae:	d568      	bpl.n	ce82 <cbvprintf+0x6c2>
			nj_len += 2U;
    cdb0:	3302      	adds	r3, #2
		if (conv->pad_fp) {
    cdb2:	0652      	lsls	r2, r2, #25
		nj_len += conv->pad0_value;
    cdb4:	990d      	ldr	r1, [sp, #52]	; 0x34
			nj_len += conv->pad0_pre_exp;
    cdb6:	bf48      	it	mi
    cdb8:	9a0e      	ldrmi	r2, [sp, #56]	; 0x38
		nj_len += conv->pad0_value;
    cdba:	440b      	add	r3, r1
			nj_len += conv->pad0_pre_exp;
    cdbc:	bf48      	it	mi
    cdbe:	189b      	addmi	r3, r3, r2
		if (width > 0) {
    cdc0:	f1b9 0f00 	cmp.w	r9, #0
    cdc4:	dd76      	ble.n	ceb4 <cbvprintf+0x6f4>
			if (!conv->flag_dash) {
    cdc6:	f89d 2030 	ldrb.w	r2, [sp, #48]	; 0x30
			width -= (int)nj_len;
    cdca:	eba9 0903 	sub.w	r9, r9, r3
			if (!conv->flag_dash) {
    cdce:	f3c2 0380 	ubfx	r3, r2, #2, #1
    cdd2:	9303      	str	r3, [sp, #12]
    cdd4:	0753      	lsls	r3, r2, #29
    cdd6:	d46d      	bmi.n	ceb4 <cbvprintf+0x6f4>
				if (conv->flag_zero) {
    cdd8:	0650      	lsls	r0, r2, #25
    cdda:	d561      	bpl.n	cea0 <cbvprintf+0x6e0>
					if (sign != 0) {
    cddc:	b146      	cbz	r6, cdf0 <cbvprintf+0x630>
						OUTC(sign);
    cdde:	9b02      	ldr	r3, [sp, #8]
    cde0:	4659      	mov	r1, fp
    cde2:	4630      	mov	r0, r6
    cde4:	4798      	blx	r3
    cde6:	2800      	cmp	r0, #0
    cde8:	db57      	blt.n	ce9a <cbvprintf+0x6da>
						sign = 0;
    cdea:	9b03      	ldr	r3, [sp, #12]
						OUTC(sign);
    cdec:	3501      	adds	r5, #1
						sign = 0;
    cdee:	461e      	mov	r6, r3
					pad = '0';
    cdf0:	2330      	movs	r3, #48	; 0x30
    cdf2:	e056      	b.n	cea2 <cbvprintf+0x6e2>
			if (conv->flag_plus) {
    cdf4:	071e      	lsls	r6, r3, #28
    cdf6:	d40f      	bmi.n	ce18 <cbvprintf+0x658>
				sign = ' ';
    cdf8:	f013 0610 	ands.w	r6, r3, #16
    cdfc:	bf18      	it	ne
    cdfe:	2620      	movne	r6, #32
			sint = value->sint;
    ce00:	e9dd 230a 	ldrd	r2, r3, [sp, #40]	; 0x28
			if (sint < 0) {
    ce04:	2b00      	cmp	r3, #0
    ce06:	f6bf af5f 	bge.w	ccc8 <cbvprintf+0x508>
				value->uint = (uint_value_type)-sint;
    ce0a:	4252      	negs	r2, r2
    ce0c:	eb63 0343 	sbc.w	r3, r3, r3, lsl #1
    ce10:	e9cd 230a 	strd	r2, r3, [sp, #40]	; 0x28
				sign = '-';
    ce14:	262d      	movs	r6, #45	; 0x2d
    ce16:	e757      	b.n	ccc8 <cbvprintf+0x508>
				sign = '+';
    ce18:	262b      	movs	r6, #43	; 0x2b
    ce1a:	e7f1      	b.n	ce00 <cbvprintf+0x640>
		switch (conv->specifier) {
    ce1c:	2600      	movs	r6, #0
    ce1e:	e753      	b.n	ccc8 <cbvprintf+0x508>
			if (value->ptr != NULL) {
    ce20:	980a      	ldr	r0, [sp, #40]	; 0x28
    ce22:	b340      	cbz	r0, ce76 <cbvprintf+0x6b6>
				bps = encode_uint((uintptr_t)value->ptr, conv,
    ce24:	f10d 0326 	add.w	r3, sp, #38	; 0x26
    ce28:	9300      	str	r3, [sp, #0]
    ce2a:	aa0c      	add	r2, sp, #48	; 0x30
    ce2c:	ab04      	add	r3, sp, #16
    ce2e:	2100      	movs	r1, #0
    ce30:	f003 f992 	bl	10158 <encode_uint>
				conv->altform_0c = true;
    ce34:	f8bd 3032 	ldrh.w	r3, [sp, #50]	; 0x32
    ce38:	f003 03ef 	and.w	r3, r3, #239	; 0xef
    ce3c:	f443 43f0 	orr.w	r3, r3, #30720	; 0x7800
    ce40:	f043 0310 	orr.w	r3, r3, #16
				bps = encode_uint((uintptr_t)value->ptr, conv,
    ce44:	4682      	mov	sl, r0
				conv->altform_0c = true;
    ce46:	f8ad 3032 	strh.w	r3, [sp, #50]	; 0x32
		char sign = 0;
    ce4a:	2600      	movs	r6, #0
				goto prec_int_pad0;
    ce4c:	e746      	b.n	ccdc <cbvprintf+0x51c>
				store_count(conv, value->ptr, count);
    ce4e:	9b0a      	ldr	r3, [sp, #40]	; 0x28
	switch ((enum length_mod_enum)conv->length_mod) {
    ce50:	2907      	cmp	r1, #7
    ce52:	f63f aee1 	bhi.w	cc18 <cbvprintf+0x458>
    ce56:	e8df f001 	tbb	[pc, r1]
    ce5a:	040c      	.short	0x040c
    ce5c:	08080c06 	.word	0x08080c06
    ce60:	0c0c      	.short	0x0c0c
		*(signed char *)dp = (signed char)count;
    ce62:	701d      	strb	r5, [r3, #0]
		break;
    ce64:	e6d8      	b.n	cc18 <cbvprintf+0x458>
		*(short *)dp = (short)count;
    ce66:	801d      	strh	r5, [r3, #0]
		break;
    ce68:	e6d6      	b.n	cc18 <cbvprintf+0x458>
		*(intmax_t *)dp = (intmax_t)count;
    ce6a:	17ea      	asrs	r2, r5, #31
    ce6c:	e9c3 5200 	strd	r5, r2, [r3]
		break;
    ce70:	e6d2      	b.n	cc18 <cbvprintf+0x458>
		*(ptrdiff_t *)dp = (ptrdiff_t)count;
    ce72:	601d      	str	r5, [r3, #0]
		break;
    ce74:	e6d0      	b.n	cc18 <cbvprintf+0x458>
			bps = "(nil)";
    ce76:	f8df a0c8 	ldr.w	sl, [pc, #200]	; cf40 <cbvprintf+0x780>
    ce7a:	4606      	mov	r6, r0
			bpe = bps + 5;
    ce7c:	f10a 0805 	add.w	r8, sl, #5
    ce80:	e78e      	b.n	cda0 <cbvprintf+0x5e0>
		} else if (conv->altform_0) {
    ce82:	0711      	lsls	r1, r2, #28
			nj_len += 1U;
    ce84:	bf48      	it	mi
    ce86:	3301      	addmi	r3, #1
    ce88:	e793      	b.n	cdb2 <cbvprintf+0x5f2>
					OUTC(pad);
    ce8a:	4618      	mov	r0, r3
    ce8c:	9303      	str	r3, [sp, #12]
    ce8e:	4659      	mov	r1, fp
    ce90:	9b02      	ldr	r3, [sp, #8]
    ce92:	4798      	blx	r3
    ce94:	2800      	cmp	r0, #0
    ce96:	9b03      	ldr	r3, [sp, #12]
    ce98:	da04      	bge.n	cea4 <cbvprintf+0x6e4>
#undef OUTS
#undef OUTC
}
    ce9a:	b011      	add	sp, #68	; 0x44
    ce9c:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
				char pad = ' ';
    cea0:	2320      	movs	r3, #32
    cea2:	444d      	add	r5, r9
    cea4:	464a      	mov	r2, r9
				while (width-- > 0) {
    cea6:	2a00      	cmp	r2, #0
    cea8:	eba5 0109 	sub.w	r1, r5, r9
    ceac:	f109 39ff 	add.w	r9, r9, #4294967295
    ceb0:	dceb      	bgt.n	ce8a <cbvprintf+0x6ca>
    ceb2:	460d      	mov	r5, r1
		if (sign != 0) {
    ceb4:	b136      	cbz	r6, cec4 <cbvprintf+0x704>
			OUTC(sign);
    ceb6:	9b02      	ldr	r3, [sp, #8]
    ceb8:	4659      	mov	r1, fp
    ceba:	4630      	mov	r0, r6
    cebc:	4798      	blx	r3
    cebe:	2800      	cmp	r0, #0
    cec0:	dbeb      	blt.n	ce9a <cbvprintf+0x6da>
    cec2:	3501      	adds	r5, #1
			if (conv->altform_0c | conv->altform_0) {
    cec4:	f89d 3032 	ldrb.w	r3, [sp, #50]	; 0x32
    cec8:	06d9      	lsls	r1, r3, #27
    ceca:	d401      	bmi.n	ced0 <cbvprintf+0x710>
    cecc:	071a      	lsls	r2, r3, #28
    cece:	d506      	bpl.n	cede <cbvprintf+0x71e>
				OUTC('0');
    ced0:	9b02      	ldr	r3, [sp, #8]
    ced2:	4659      	mov	r1, fp
    ced4:	2030      	movs	r0, #48	; 0x30
    ced6:	4798      	blx	r3
    ced8:	2800      	cmp	r0, #0
    ceda:	dbde      	blt.n	ce9a <cbvprintf+0x6da>
    cedc:	3501      	adds	r5, #1
			if (conv->altform_0c) {
    cede:	f89d 3032 	ldrb.w	r3, [sp, #50]	; 0x32
    cee2:	06db      	lsls	r3, r3, #27
    cee4:	d507      	bpl.n	cef6 <cbvprintf+0x736>
				OUTC(conv->specifier);
    cee6:	f89d 0033 	ldrb.w	r0, [sp, #51]	; 0x33
    ceea:	9b02      	ldr	r3, [sp, #8]
    ceec:	4659      	mov	r1, fp
    ceee:	4798      	blx	r3
    cef0:	2800      	cmp	r0, #0
    cef2:	dbd2      	blt.n	ce9a <cbvprintf+0x6da>
    cef4:	3501      	adds	r5, #1
			while (pad_len-- > 0) {
    cef6:	9e0d      	ldr	r6, [sp, #52]	; 0x34
    cef8:	442e      	add	r6, r5
    cefa:	1b73      	subs	r3, r6, r5
    cefc:	2b00      	cmp	r3, #0
    cefe:	dc16      	bgt.n	cf2e <cbvprintf+0x76e>
			OUTS(bps, bpe);
    cf00:	9802      	ldr	r0, [sp, #8]
    cf02:	4643      	mov	r3, r8
    cf04:	4652      	mov	r2, sl
    cf06:	4659      	mov	r1, fp
    cf08:	f003 f96c 	bl	101e4 <outs>
    cf0c:	2800      	cmp	r0, #0
    cf0e:	dbc4      	blt.n	ce9a <cbvprintf+0x6da>
    cf10:	4405      	add	r5, r0
		while (width > 0) {
    cf12:	44a9      	add	r9, r5
    cf14:	eba9 0305 	sub.w	r3, r9, r5
    cf18:	2b00      	cmp	r3, #0
    cf1a:	f77f ae7d 	ble.w	cc18 <cbvprintf+0x458>
			OUTC(' ');
    cf1e:	9b02      	ldr	r3, [sp, #8]
    cf20:	4659      	mov	r1, fp
    cf22:	2020      	movs	r0, #32
    cf24:	4798      	blx	r3
    cf26:	2800      	cmp	r0, #0
    cf28:	dbb7      	blt.n	ce9a <cbvprintf+0x6da>
    cf2a:	3501      	adds	r5, #1
			--width;
    cf2c:	e7f2      	b.n	cf14 <cbvprintf+0x754>
				OUTC('0');
    cf2e:	9b02      	ldr	r3, [sp, #8]
    cf30:	4659      	mov	r1, fp
    cf32:	2030      	movs	r0, #48	; 0x30
    cf34:	4798      	blx	r3
    cf36:	2800      	cmp	r0, #0
    cf38:	dbaf      	blt.n	ce9a <cbvprintf+0x6da>
    cf3a:	3501      	adds	r5, #1
    cf3c:	e7dd      	b.n	cefa <cbvprintf+0x73a>
    cf3e:	bf00      	nop
    cf40:	00010c9e 	.word	0x00010c9e

0000cf44 <pm_state_notify>:
/*
 * Function called to notify when the system is entering / exiting a
 * power state
 */
static inline void pm_state_notify(bool entering_state)
{
    cf44:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    cf48:	4605      	mov	r5, r0
    cf4a:	f04f 0320 	mov.w	r3, #32
    cf4e:	f3ef 8611 	mrs	r6, BASEPRI
    cf52:	f383 8812 	msr	BASEPRI_MAX, r3
    cf56:	f3bf 8f6f 	isb	sy
	return list->head;
    cf5a:	4b0e      	ldr	r3, [pc, #56]	; (cf94 <pm_state_notify+0x50>)
    cf5c:	681c      	ldr	r4, [r3, #0]
	struct pm_notifier *notifier;
	k_spinlock_key_t pm_notifier_key;
	void (*callback)(enum pm_state state);

	pm_notifier_key = k_spin_lock(&pm_notifier_lock);
	SYS_SLIST_FOR_EACH_CONTAINER(&pm_notifiers, notifier, _node) {
    cf5e:	b19c      	cbz	r4, cf88 <pm_state_notify+0x44>
		} else {
			callback = notifier->state_exit;
		}

		if (callback) {
			callback(z_cpus_pm_state[_current_cpu->id].state);
    cf60:	4f0d      	ldr	r7, [pc, #52]	; (cf98 <pm_state_notify+0x54>)
    cf62:	f8df 8038 	ldr.w	r8, [pc, #56]	; cf9c <pm_state_notify+0x58>
    cf66:	f04f 090c 	mov.w	r9, #12
			callback = notifier->state_exit;
    cf6a:	e9d4 3201 	ldrd	r3, r2, [r4, #4]
    cf6e:	2d00      	cmp	r5, #0
    cf70:	bf08      	it	eq
    cf72:	4613      	moveq	r3, r2
		if (callback) {
    cf74:	b12b      	cbz	r3, cf82 <pm_state_notify+0x3e>
			callback(z_cpus_pm_state[_current_cpu->id].state);
    cf76:	f898 2014 	ldrb.w	r2, [r8, #20]
    cf7a:	fb09 f202 	mul.w	r2, r9, r2
    cf7e:	5cb8      	ldrb	r0, [r7, r2]
    cf80:	4798      	blx	r3
	return node->next;
    cf82:	6824      	ldr	r4, [r4, #0]
	SYS_SLIST_FOR_EACH_CONTAINER(&pm_notifiers, notifier, _node) {
    cf84:	2c00      	cmp	r4, #0
    cf86:	d1f0      	bne.n	cf6a <pm_state_notify+0x26>
	__asm__ volatile(
    cf88:	f386 8811 	msr	BASEPRI, r6
    cf8c:	f3bf 8f6f 	isb	sy
		}
	}
	k_spin_unlock(&pm_notifier_lock, pm_notifier_key);
}
    cf90:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
    cf94:	200001c0 	.word	0x200001c0
    cf98:	200001c8 	.word	0x200001c8
    cf9c:	20000338 	.word	0x20000338

0000cfa0 <atomic_clear_bit.constprop.0>:
 */
static inline void atomic_clear_bit(atomic_t *target, int bit)
{
	atomic_val_t mask = ATOMIC_MASK(bit);

	(void)atomic_and(ATOMIC_ELEM(target, bit), ~mask);
    cfa0:	0942      	lsrs	r2, r0, #5
	atomic_val_t mask = ATOMIC_MASK(bit);
    cfa2:	2301      	movs	r3, #1
    cfa4:	f000 001f 	and.w	r0, r0, #31
    cfa8:	fa03 f000 	lsl.w	r0, r3, r0
 *
 * @return Previous value of @a target.
 */
static inline atomic_val_t atomic_and(atomic_t *target, atomic_val_t value)
{
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    cfac:	4b07      	ldr	r3, [pc, #28]	; (cfcc <atomic_clear_bit.constprop.0+0x2c>)
    cfae:	f3bf 8f5b 	dmb	ish
	(void)atomic_and(ATOMIC_ELEM(target, bit), ~mask);
    cfb2:	43c0      	mvns	r0, r0
    cfb4:	eb03 0382 	add.w	r3, r3, r2, lsl #2
    cfb8:	e853 2f00 	ldrex	r2, [r3]
    cfbc:	4002      	ands	r2, r0
    cfbe:	e843 2100 	strex	r1, r2, [r3]
    cfc2:	2900      	cmp	r1, #0
    cfc4:	d1f8      	bne.n	cfb8 <atomic_clear_bit.constprop.0+0x18>
    cfc6:	f3bf 8f5b 	dmb	ish
}
    cfca:	4770      	bx	lr
    cfcc:	200001d4 	.word	0x200001d4

0000cfd0 <pm_system_resume>:

void pm_system_resume(void)
{
    cfd0:	b538      	push	{r3, r4, r5, lr}
	uint8_t id = _current_cpu->id;
    cfd2:	4b1a      	ldr	r3, [pc, #104]	; (d03c <pm_system_resume+0x6c>)
    cfd4:	7d1c      	ldrb	r4, [r3, #20]
    cfd6:	f3bf 8f5b 	dmb	ish
	atomic_val_t mask = ATOMIC_MASK(bit);
    cfda:	f004 031f 	and.w	r3, r4, #31
    cfde:	2201      	movs	r2, #1
    cfe0:	409a      	lsls	r2, r3
    cfe2:	4b17      	ldr	r3, [pc, #92]	; (d040 <pm_system_resume+0x70>)
	old = atomic_and(ATOMIC_ELEM(target, bit), ~mask);
    cfe4:	0961      	lsrs	r1, r4, #5
    cfe6:	43d0      	mvns	r0, r2
    cfe8:	eb03 0381 	add.w	r3, r3, r1, lsl #2
    cfec:	e853 1f00 	ldrex	r1, [r3]
    cff0:	ea01 0500 	and.w	r5, r1, r0
    cff4:	e843 5c00 	strex	ip, r5, [r3]
    cff8:	f1bc 0f00 	cmp.w	ip, #0
    cffc:	d1f6      	bne.n	cfec <pm_system_resume+0x1c>
    cffe:	f3bf 8f5b 	dmb	ish
	 * that caused the wake. This hook will be called from the ISR.
	 * For such CPU LPS states, do post operations and restores here.
	 * The kernel scheduler will get control after the ISR finishes
	 * and it may schedule another thread.
	 */
	if (atomic_test_and_clear_bit(z_post_ops_required, id)) {
    d002:	4211      	tst	r1, r2
    d004:	d013      	beq.n	d02e <pm_system_resume+0x5e>
	if (pm_state_exit_post_ops != NULL) {
    d006:	4b0f      	ldr	r3, [pc, #60]	; (d044 <pm_system_resume+0x74>)
    d008:	4d0f      	ldr	r5, [pc, #60]	; (d048 <pm_system_resume+0x78>)
    d00a:	b18b      	cbz	r3, d030 <pm_system_resume+0x60>
		pm_state_exit_post_ops(info->state, info->substate_id);
    d00c:	230c      	movs	r3, #12
    d00e:	4363      	muls	r3, r4
    d010:	18ea      	adds	r2, r5, r3
    d012:	5ce8      	ldrb	r0, [r5, r3]
    d014:	7851      	ldrb	r1, [r2, #1]
    d016:	f003 f94a 	bl	102ae <pm_state_exit_post_ops>
		pm_exit_pos_ops(&z_cpus_pm_state[id]);
		pm_state_notify(false);
    d01a:	2000      	movs	r0, #0
    d01c:	f7ff ff92 	bl	cf44 <pm_state_notify>
		z_cpus_pm_state[id] = (struct pm_state_info){PM_STATE_ACTIVE,
    d020:	230c      	movs	r3, #12
    d022:	435c      	muls	r4, r3
    d024:	192a      	adds	r2, r5, r4
    d026:	2300      	movs	r3, #0
    d028:	512b      	str	r3, [r5, r4]
    d02a:	e9c2 3301 	strd	r3, r3, [r2, #4]
			0, 0};
	}
}
    d02e:	bd38      	pop	{r3, r4, r5, pc}
    d030:	f383 8811 	msr	BASEPRI, r3
    d034:	f3bf 8f6f 	isb	sy
		"cpsie i;"
		: : : "memory", "cc");
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
}
    d038:	e7ef      	b.n	d01a <pm_system_resume+0x4a>
    d03a:	bf00      	nop
    d03c:	20000338 	.word	0x20000338
    d040:	200001d8 	.word	0x200001d8
    d044:	000102af 	.word	0x000102af
    d048:	200001c8 	.word	0x200001c8

0000d04c <pm_system_suspend>:

	return ret;
}

bool pm_system_suspend(int32_t ticks)
{
    d04c:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
	bool ret = true;
	uint8_t id = _current_cpu->id;
    d050:	4b32      	ldr	r3, [pc, #200]	; (d11c <pm_system_suspend+0xd0>)
	return __atomic_load_n(target, __ATOMIC_SEQ_CST);
    d052:	4a33      	ldr	r2, [pc, #204]	; (d120 <pm_system_suspend+0xd4>)
    d054:	7d1c      	ldrb	r4, [r3, #20]
    d056:	f3bf 8f5b 	dmb	ish
	atomic_val_t val = atomic_get(ATOMIC_ELEM(target, bit));
    d05a:	0963      	lsrs	r3, r4, #5
    d05c:	ea4f 0983 	mov.w	r9, r3, lsl #2
    d060:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
    d064:	4e2f      	ldr	r6, [pc, #188]	; (d124 <pm_system_suspend+0xd8>)
    d066:	f3bf 8f5b 	dmb	ish
	return (1 & (val >> (bit & (ATOMIC_BITS - 1)))) != 0;
    d06a:	f004 081f 	and.w	r8, r4, #31
    d06e:	fa43 f308 	asr.w	r3, r3, r8

	SYS_PORT_TRACING_FUNC_ENTER(pm, system_suspend, ticks);

	if (!atomic_test_bit(z_cpus_pm_state_forced, id)) {
    d072:	f013 0f01 	tst.w	r3, #1
{
    d076:	4607      	mov	r7, r0
	if (!atomic_test_bit(z_cpus_pm_state_forced, id)) {
    d078:	d10a      	bne.n	d090 <pm_system_suspend+0x44>
		const struct pm_state_info *info;

		info = pm_policy_next_state(id, ticks);
    d07a:	4601      	mov	r1, r0
    d07c:	4620      	mov	r0, r4
    d07e:	f000 f869 	bl	d154 <pm_policy_next_state>
		if (info != NULL) {
    d082:	b128      	cbz	r0, d090 <pm_system_suspend+0x44>
			z_cpus_pm_state[id] = *info;
    d084:	c807      	ldmia	r0, {r0, r1, r2}
    d086:	230c      	movs	r3, #12
    d088:	fb03 6304 	mla	r3, r3, r4, r6
    d08c:	e883 0007 	stmia.w	r3, {r0, r1, r2}
		}
	}

	if (z_cpus_pm_state[id].state == PM_STATE_ACTIVE) {
    d090:	230c      	movs	r3, #12
    d092:	4363      	muls	r3, r4
    d094:	18f2      	adds	r2, r6, r3
    d096:	5cf5      	ldrb	r5, [r6, r3]
    d098:	b92d      	cbnz	r5, d0a6 <pm_system_suspend+0x5a>
		LOG_DBG("No PM operations done.");
		SYS_PORT_TRACING_FUNC_EXIT(pm, system_suspend, ticks,
				   z_cpus_pm_state[id].state);
		ret = false;
		atomic_clear_bit(z_cpus_pm_state_forced, id);
    d09a:	4620      	mov	r0, r4
    d09c:	f7ff ff80 	bl	cfa0 <atomic_clear_bit.constprop.0>
		ret = false;
    d0a0:	4628      	mov	r0, r5
	SYS_PORT_TRACING_FUNC_EXIT(pm, system_suspend, ticks,
				   z_cpus_pm_state[id].state);

end:
	return ret;
}
    d0a2:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
	if (ticks != K_TICKS_FOREVER) {
    d0a6:	1c7b      	adds	r3, r7, #1
    d0a8:	d00f      	beq.n	d0ca <pm_system_suspend+0x7e>
		} else {
			return t * ((uint64_t)to_hz / from_hz);
		}
	} else {
		if (result32) {
			return (uint32_t)((t * to_hz + off) / from_hz);
    d0aa:	f8d2 c008 	ldr.w	ip, [r2, #8]
    d0ae:	481e      	ldr	r0, [pc, #120]	; (d128 <pm_system_suspend+0xdc>)
    d0b0:	4a1e      	ldr	r2, [pc, #120]	; (d12c <pm_system_suspend+0xe0>)
    d0b2:	f44f 4500 	mov.w	r5, #32768	; 0x8000
    d0b6:	2100      	movs	r1, #0
    d0b8:	2300      	movs	r3, #0
    d0ba:	fbec 0105 	umlal	r0, r1, ip, r5
    d0be:	f7ff f90d 	bl	c2dc <__aeabi_uldivmod>
		z_set_timeout_expiry(ticks -
    d0c2:	2101      	movs	r1, #1
    d0c4:	1a38      	subs	r0, r7, r0
    d0c6:	f003 fc4a 	bl	1095e <z_set_timeout_expiry>
	k_sched_lock();
    d0ca:	f002 fb5b 	bl	f784 <k_sched_lock>
	pm_state_notify(true);
    d0ce:	2001      	movs	r0, #1
    d0d0:	f7ff ff38 	bl	cf44 <pm_state_notify>
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    d0d4:	f3bf 8f5b 	dmb	ish
 * @param target Address of atomic variable or array.
 * @param bit Bit number (starting from 0).
 */
static inline void atomic_set_bit(atomic_t *target, int bit)
{
	atomic_val_t mask = ATOMIC_MASK(bit);
    d0d8:	2301      	movs	r3, #1
    d0da:	fa03 f808 	lsl.w	r8, r3, r8
    d0de:	4b14      	ldr	r3, [pc, #80]	; (d130 <pm_system_suspend+0xe4>)
    d0e0:	4499      	add	r9, r3
    d0e2:	e859 3f00 	ldrex	r3, [r9]
    d0e6:	ea43 0308 	orr.w	r3, r3, r8
    d0ea:	e849 3200 	strex	r2, r3, [r9]
    d0ee:	2a00      	cmp	r2, #0
    d0f0:	d1f7      	bne.n	d0e2 <pm_system_suspend+0x96>
    d0f2:	f3bf 8f5b 	dmb	ish
	if (pm_state_set != NULL) {
    d0f6:	4b0f      	ldr	r3, [pc, #60]	; (d134 <pm_system_suspend+0xe8>)
    d0f8:	b133      	cbz	r3, d108 <pm_system_suspend+0xbc>
		pm_state_set(info->state, info->substate_id);
    d0fa:	230c      	movs	r3, #12
    d0fc:	4363      	muls	r3, r4
    d0fe:	18f2      	adds	r2, r6, r3
    d100:	5cf0      	ldrb	r0, [r6, r3]
    d102:	7851      	ldrb	r1, [r2, #1]
    d104:	f003 f8c7 	bl	10296 <pm_state_set>
	pm_system_resume();
    d108:	f7ff ff62 	bl	cfd0 <pm_system_resume>
	atomic_clear_bit(z_cpus_pm_state_forced, id);
    d10c:	4620      	mov	r0, r4
    d10e:	f7ff ff47 	bl	cfa0 <atomic_clear_bit.constprop.0>
	k_sched_unlock();
    d112:	f002 fcbf 	bl	fa94 <k_sched_unlock>
	bool ret = true;
    d116:	2001      	movs	r0, #1
    d118:	e7c3      	b.n	d0a2 <pm_system_suspend+0x56>
    d11a:	bf00      	nop
    d11c:	20000338 	.word	0x20000338
    d120:	200001d4 	.word	0x200001d4
    d124:	200001c8 	.word	0x200001c8
    d128:	000f423f 	.word	0x000f423f
    d12c:	000f4240 	.word	0x000f4240
    d130:	200001d8 	.word	0x200001d8
    d134:	00010297 	.word	0x00010297

0000d138 <pm_policy_state_lock_is_active>:
	return __atomic_load_n(target, __ATOMIC_SEQ_CST);
    d138:	4b05      	ldr	r3, [pc, #20]	; (d150 <pm_policy_state_lock_is_active+0x18>)
    d13a:	f3bf 8f5b 	dmb	ish
    d13e:	f853 0020 	ldr.w	r0, [r3, r0, lsl #2]
    d142:	f3bf 8f5b 	dmb	ish
}

bool pm_policy_state_lock_is_active(enum pm_state state)
{
	return (atomic_get(&state_lock_cnt[state]) != 0);
}
    d146:	3800      	subs	r0, #0
    d148:	bf18      	it	ne
    d14a:	2001      	movne	r0, #1
    d14c:	4770      	bx	lr
    d14e:	bf00      	nop
    d150:	200001dc 	.word	0x200001dc

0000d154 <pm_policy_next_state>:
{
    d154:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    d158:	b085      	sub	sp, #20
    d15a:	460f      	mov	r7, r1
	num_cpu_states = pm_state_cpu_get_all(cpu, &cpu_states);
    d15c:	a903      	add	r1, sp, #12
    d15e:	f000 f847 	bl	d1f0 <pm_state_cpu_get_all>
    d162:	f8df 8080 	ldr.w	r8, [pc, #128]	; d1e4 <pm_policy_next_state+0x90>
    d166:	f8df a080 	ldr.w	sl, [pc, #128]	; d1e8 <pm_policy_next_state+0x94>
	for (int16_t i = (int16_t)num_cpu_states - 1; i >= 0; i--) {
    d16a:	1e44      	subs	r4, r0, #1
    d16c:	b224      	sxth	r4, r4
    d16e:	f04f 0b00 	mov.w	fp, #0
    d172:	1c63      	adds	r3, r4, #1
    d174:	d104      	bne.n	d180 <pm_policy_next_state+0x2c>
	return NULL;
    d176:	2600      	movs	r6, #0
}
    d178:	4630      	mov	r0, r6
    d17a:	b005      	add	sp, #20
    d17c:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
		const struct pm_state_info *state = &cpu_states[i];
    d180:	9a03      	ldr	r2, [sp, #12]
    d182:	eb04 0344 	add.w	r3, r4, r4, lsl #1
    d186:	eb02 0683 	add.w	r6, r2, r3, lsl #2
		if (pm_policy_state_lock_is_active(state->state)) {
    d18a:	f812 0023 	ldrb.w	r0, [r2, r3, lsl #2]
    d18e:	f7ff ffd3 	bl	d138 <pm_policy_state_lock_is_active>
    d192:	4605      	mov	r5, r0
    d194:	bb10      	cbnz	r0, d1dc <pm_policy_next_state+0x88>
    d196:	6870      	ldr	r0, [r6, #4]
    d198:	f44f 4900 	mov.w	r9, #32768	; 0x8000
    d19c:	46c4      	mov	ip, r8
    d19e:	4629      	mov	r1, r5
    d1a0:	fbe0 c109 	umlal	ip, r1, r0, r9
    d1a4:	4652      	mov	r2, sl
    d1a6:	465b      	mov	r3, fp
    d1a8:	4660      	mov	r0, ip
    d1aa:	f7ff f897 	bl	c2dc <__aeabi_uldivmod>
    d1ae:	9001      	str	r0, [sp, #4]
    d1b0:	68b0      	ldr	r0, [r6, #8]
    d1b2:	46c4      	mov	ip, r8
    d1b4:	4629      	mov	r1, r5
    d1b6:	fbe0 c109 	umlal	ip, r1, r0, r9
    d1ba:	465b      	mov	r3, fp
    d1bc:	4652      	mov	r2, sl
    d1be:	4660      	mov	r0, ip
    d1c0:	f7ff f88c 	bl	c2dc <__aeabi_uldivmod>
		if ((max_latency_ticks != K_TICKS_FOREVER) &&
    d1c4:	4b09      	ldr	r3, [pc, #36]	; (d1ec <pm_policy_next_state+0x98>)
    d1c6:	681b      	ldr	r3, [r3, #0]
    d1c8:	1c59      	adds	r1, r3, #1
    d1ca:	d001      	beq.n	d1d0 <pm_policy_next_state+0x7c>
    d1cc:	4283      	cmp	r3, r0
    d1ce:	d905      	bls.n	d1dc <pm_policy_next_state+0x88>
		if ((ticks == K_TICKS_FOREVER) ||
    d1d0:	1c7a      	adds	r2, r7, #1
    d1d2:	d0d1      	beq.n	d178 <pm_policy_next_state+0x24>
		    (ticks >= (min_residency + exit_latency))) {
    d1d4:	9b01      	ldr	r3, [sp, #4]
    d1d6:	4418      	add	r0, r3
		if ((ticks == K_TICKS_FOREVER) ||
    d1d8:	42b8      	cmp	r0, r7
    d1da:	d9cd      	bls.n	d178 <pm_policy_next_state+0x24>
	for (int16_t i = (int16_t)num_cpu_states - 1; i >= 0; i--) {
    d1dc:	3c01      	subs	r4, #1
    d1de:	b224      	sxth	r4, r4
    d1e0:	e7c7      	b.n	d172 <pm_policy_next_state+0x1e>
    d1e2:	bf00      	nop
    d1e4:	000f423f 	.word	0x000f423f
    d1e8:	000f4240 	.word	0x000f4240
    d1ec:	20000004 	.word	0x20000004

0000d1f0 <pm_state_cpu_get_all>:
	DT_FOREACH_CHILD(DT_PATH(cpus), NUM_CPU_STATES)
};

uint8_t pm_state_cpu_get_all(uint8_t cpu, const struct pm_state_info **states)
{
	if (cpu >= ARRAY_SIZE(cpus_states)) {
    d1f0:	b908      	cbnz	r0, d1f6 <pm_state_cpu_get_all+0x6>
		return 0;
	}

	*states = cpus_states[cpu];
    d1f2:	4b02      	ldr	r3, [pc, #8]	; (d1fc <pm_state_cpu_get_all+0xc>)
    d1f4:	600b      	str	r3, [r1, #0]

	return states_per_cpu[cpu];
}
    d1f6:	2000      	movs	r0, #0
    d1f8:	4770      	bx	lr
    d1fa:	bf00      	nop
    d1fc:	00010b88 	.word	0x00010b88

0000d200 <z_arm_cpu_idle_init>:
 * void z_arm_cpu_idle_init(void);
 */

SECTION_FUNC(TEXT, z_arm_cpu_idle_init)
#if defined(CONFIG_CPU_CORTEX_M)
	ldr	r1, =_SCB_SCR
    d200:	4901      	ldr	r1, [pc, #4]	; (d208 <z_arm_cpu_idle_init+0x8>)
	movs.n	r2, #_SCR_INIT_BITS
    d202:	2210      	movs	r2, #16
	str	r2, [r1]
    d204:	600a      	str	r2, [r1, #0]
#endif
	bx	lr
    d206:	4770      	bx	lr
	ldr	r1, =_SCB_SCR
    d208:	e000ed10 	.word	0xe000ed10

0000d20c <arch_cpu_idle>:
	 * before entering low power state.
	 *
	 * Set PRIMASK before configuring BASEPRI to prevent interruption
	 * before wake-up.
	 */
	cpsid	i
    d20c:	b672      	cpsid	i

	/*
	 * Set wake-up interrupt priority to the lowest and synchronise to
	 * ensure that this is visible to the WFI instruction.
	 */
	eors.n	r0, r0
    d20e:	4040      	eors	r0, r0
	msr	BASEPRI, r0
    d210:	f380 8811 	msr	BASEPRI, r0
	isb
    d214:	f3bf 8f6f 	isb	sy

	/*
	 * Wait for all memory transactions to complete before entering low
	 * power state.
	 */
	dsb
    d218:	f3bf 8f4f 	dsb	sy

	/* Enter low power state */
	wfi
    d21c:	bf30      	wfi

	/*
	 * Clear PRIMASK and flush instruction buffer to immediately service
	 * the wake-up interrupt.
	 */
	cpsie	i
    d21e:	b662      	cpsie	i
	isb
    d220:	f3bf 8f6f 	isb	sy

	bx	lr
    d224:	4770      	bx	lr
    d226:	bf00      	nop

0000d228 <arch_cpu_atomic_idle>:

	/*
	 * Lock PRIMASK while sleeping: wfe will still get interrupted by
	 * incoming interrupts but the CPU will not service them right away.
	 */
	cpsid	i
    d228:	b672      	cpsid	i
	cpsie	i
_irq_disabled:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* r1: zero, for setting BASEPRI (needs a register) */
	eors.n	r1, r1
    d22a:	4049      	eors	r1, r1

	/* unlock BASEPRI so wfe gets interrupted by incoming interrupts */
	msr	BASEPRI, r1
    d22c:	f381 8811 	msr	BASEPRI, r1

	wfe
    d230:	bf20      	wfe

	msr	BASEPRI, r0
    d232:	f380 8811 	msr	BASEPRI, r0
	cpsie	i
    d236:	b662      	cpsie	i
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
	bx	lr
    d238:	4770      	bx	lr
    d23a:	bf00      	nop

0000d23c <arch_irq_enable>:
#define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
#define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)

void arch_irq_enable(unsigned int irq)
{
	NVIC_EnableIRQ((IRQn_Type)irq);
    d23c:	b243      	sxtb	r3, r0
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
    d23e:	2b00      	cmp	r3, #0
    d240:	db08      	blt.n	d254 <arch_irq_enable+0x18>
  {
    __COMPILER_BARRIER();
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    d242:	2201      	movs	r2, #1
    d244:	f000 001f 	and.w	r0, r0, #31
    d248:	fa02 f000 	lsl.w	r0, r2, r0
    d24c:	095b      	lsrs	r3, r3, #5
    d24e:	4a02      	ldr	r2, [pc, #8]	; (d258 <arch_irq_enable+0x1c>)
    d250:	f842 0023 	str.w	r0, [r2, r3, lsl #2]
}
    d254:	4770      	bx	lr
    d256:	bf00      	nop
    d258:	e000e100 	.word	0xe000e100

0000d25c <arch_irq_is_enabled>:
	NVIC_DisableIRQ((IRQn_Type)irq);
}

int arch_irq_is_enabled(unsigned int irq)
{
	return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq));
    d25c:	4b05      	ldr	r3, [pc, #20]	; (d274 <arch_irq_is_enabled+0x18>)
    d25e:	0942      	lsrs	r2, r0, #5
    d260:	f000 001f 	and.w	r0, r0, #31
    d264:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
    d268:	2301      	movs	r3, #1
    d26a:	fa03 f000 	lsl.w	r0, r3, r0
}
    d26e:	4010      	ands	r0, r2
    d270:	4770      	bx	lr
    d272:	bf00      	nop
    d274:	e000e100 	.word	0xe000e100

0000d278 <z_arm_irq_priority_set>:
	 */
	__ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1),
		 "invalid priority %d for %d irq! values must be less than %lu\n",
		 prio - _IRQ_PRIO_OFFSET, irq,
		 BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
	NVIC_SetPriority((IRQn_Type)irq, prio);
    d278:	b243      	sxtb	r3, r0
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
  if ((int32_t)(IRQn) >= 0)
    d27a:	2b00      	cmp	r3, #0
  {
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    d27c:	bfa8      	it	ge
    d27e:	f103 4360 	addge.w	r3, r3, #3758096384	; 0xe0000000
		prio += _IRQ_PRIO_OFFSET;
    d282:	f101 0101 	add.w	r1, r1, #1
  }
  else
  {
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    d286:	bfb8      	it	lt
    d288:	4b06      	ldrlt	r3, [pc, #24]	; (d2a4 <z_arm_irq_priority_set+0x2c>)
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    d28a:	ea4f 1141 	mov.w	r1, r1, lsl #5
    d28e:	bfac      	ite	ge
    d290:	f503 4361 	addge.w	r3, r3, #57600	; 0xe100
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    d294:	f000 000f 	andlt.w	r0, r0, #15
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    d298:	b2c9      	uxtb	r1, r1
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    d29a:	bfb4      	ite	lt
    d29c:	5419      	strblt	r1, [r3, r0]
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    d29e:	f883 1300 	strbge.w	r1, [r3, #768]	; 0x300
}
    d2a2:	4770      	bx	lr
    d2a4:	e000ed14 	.word	0xe000ed14

0000d2a8 <z_SysNmiOnReset>:
_ASM_FILE_PROLOGUE

GTEXT(z_SysNmiOnReset)

SECTION_FUNC(TEXT, z_SysNmiOnReset)
    wfi
    d2a8:	bf30      	wfi
    b z_SysNmiOnReset
    d2aa:	f7ff bffd 	b.w	d2a8 <z_SysNmiOnReset>
    d2ae:	bf00      	nop

0000d2b0 <z_arm_prep_c>:

#define VECTOR_ADDRESS ((uintptr_t)_vector_start)

static inline void relocate_vector_table(void)
{
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    d2b0:	4a0b      	ldr	r2, [pc, #44]	; (d2e0 <z_arm_prep_c+0x30>)
 *
 * This routine prepares for the execution of and runs C code.
 *
 */
void z_arm_prep_c(void)
{
    d2b2:	b508      	push	{r3, lr}
	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
    d2b4:	4b0b      	ldr	r3, [pc, #44]	; (d2e4 <z_arm_prep_c+0x34>)
    d2b6:	f022 027f 	bic.w	r2, r2, #127	; 0x7f
    d2ba:	609a      	str	r2, [r3, #8]
  \details Acts as a special kind of Data Memory Barrier.
           It completes when all explicit memory accesses before this instruction complete.
 */
__STATIC_FORCEINLINE void __DSB(void)
{
  __ASM volatile ("dsb 0xF":::"memory");
    d2bc:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    d2c0:	f3bf 8f6f 	isb	sy
	SCB->CPACR &= (~(CPACR_CP10_Msk | CPACR_CP11_Msk));
    d2c4:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
    d2c8:	f422 0270 	bic.w	r2, r2, #15728640	; 0xf00000
    d2cc:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
	relocate_vector_table();
#if defined(CONFIG_CPU_HAS_FPU)
	z_arm_floating_point_init();
#endif
	z_bss_zero();
    d2d0:	f002 f860 	bl	f394 <z_bss_zero>
	z_data_copy();
    d2d4:	f002 fd00 	bl	fcd8 <z_data_copy>
#if ((defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)) && defined(CONFIG_INIT_STACKS))
	z_arm_init_stacks();
#endif
	z_arm_interrupt_init();
    d2d8:	f000 f9d0 	bl	d67c <z_arm_interrupt_init>
	z_cstart();
    d2dc:	f002 f89e 	bl	f41c <z_cstart>
    d2e0:	0000c200 	.word	0x0000c200
    d2e4:	e000ed00 	.word	0xe000ed00

0000d2e8 <arch_swap>:
 * as BASEPRI is not available.
 */
int arch_swap(unsigned int key)
{
	/* store off key and return value */
	_current->arch.basepri = key;
    d2e8:	4a09      	ldr	r2, [pc, #36]	; (d310 <arch_swap+0x28>)
	_current->arch.swap_return_value = _k_neg_eagain;
    d2ea:	490a      	ldr	r1, [pc, #40]	; (d314 <arch_swap+0x2c>)
	_current->arch.basepri = key;
    d2ec:	6893      	ldr	r3, [r2, #8]
	_current->arch.swap_return_value = _k_neg_eagain;
    d2ee:	6809      	ldr	r1, [r1, #0]
    d2f0:	6799      	str	r1, [r3, #120]	; 0x78

#if defined(CONFIG_CPU_CORTEX_M)
	/* set pending bit to make sure we will take a PendSV exception */
	SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    d2f2:	4909      	ldr	r1, [pc, #36]	; (d318 <arch_swap+0x30>)
	_current->arch.basepri = key;
    d2f4:	6758      	str	r0, [r3, #116]	; 0x74
	SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    d2f6:	684b      	ldr	r3, [r1, #4]
    d2f8:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
    d2fc:	604b      	str	r3, [r1, #4]
	__asm__ volatile(
    d2fe:	2300      	movs	r3, #0
    d300:	f383 8811 	msr	BASEPRI, r3
    d304:	f3bf 8f6f 	isb	sy
#endif

	/* Context switch is performed here. Returning implies the
	 * thread has been context-switched-in again.
	 */
	return _current->arch.swap_return_value;
    d308:	6893      	ldr	r3, [r2, #8]
}
    d30a:	6f98      	ldr	r0, [r3, #120]	; 0x78
    d30c:	4770      	bx	lr
    d30e:	bf00      	nop
    d310:	20000338 	.word	0x20000338
    d314:	00010c78 	.word	0x00010c78
    d318:	e000ed00 	.word	0xe000ed00

0000d31c <z_arm_pendsv>:
    pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_INSTRUMENT_THREAD_SWITCHING */

    /* load _kernel into r1 and current k_thread into r2 */
    ldr r1, =_kernel
    d31c:	4912      	ldr	r1, [pc, #72]	; (d368 <z_arm_pendsv+0x4c>)
    ldr r2, [r1, #_kernel_offset_to_current]
    d31e:	688a      	ldr	r2, [r1, #8]
    /* Store LSB of LR (EXC_RETURN) to the thread's 'mode' word. */
    strb lr, [r2, #_thread_offset_to_mode_exc_return]
#endif

    /* addr of callee-saved regs in thread in r0 */
    ldr r0, =_thread_offset_to_callee_saved
    d320:	f04f 0030 	mov.w	r0, #48	; 0x30
    add r0, r2
    d324:	4410      	add	r0, r2

    /* save callee-saved + psp in thread */
#if defined(CONFIG_CPU_CORTEX_M)
    mrs ip, PSP
    d326:	f3ef 8c09 	mrs	ip, PSP
    mov r6, r11
    mov r7, ip
    /* store r8-12 */
    stmea r0!, {r3-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    stmia r0, {v1-v8, ip}
    d32a:	e880 1ff0 	stmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}

    /* Protect the kernel state while we play with the thread lists */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    d32e:	2020      	movs	r0, #32
    msr BASEPRI_MAX, r0
    d330:	f380 8812 	msr	BASEPRI_MAX, r0
    isb /* Make the effect of disabling interrupts be realized immediately */
    d334:	f3bf 8f6f 	isb	sy
     * the new thread is context-switched in since all decisions
     * to pend PendSV have been taken with the current kernel
     * state and this is what we're handling currently.
     */
#if defined(CONFIG_CPU_CORTEX_M)
    ldr v4, =_SCS_ICSR
    d338:	4f0c      	ldr	r7, [pc, #48]	; (d36c <z_arm_pendsv+0x50>)
    ldr v3, =_SCS_ICSR_UNPENDSV
    d33a:	f04f 6600 	mov.w	r6, #134217728	; 0x8000000
#endif

    /* _kernel is still in r1 */

    /* fetch the thread to run from the ready queue cache */
    ldr r2, [r1, #_kernel_offset_to_ready_q_cache]
    d33e:	69ca      	ldr	r2, [r1, #28]

    str r2, [r1, #_kernel_offset_to_current]
    d340:	608a      	str	r2, [r1, #8]
     * has been handled.
     */

    /* _SCS_ICSR is still in v4 and _SCS_ICSR_UNPENDSV in v3 */
#if defined(CONFIG_CPU_CORTEX_M)
    str v3, [v4, #0]
    d342:	603e      	str	r6, [r7, #0]

    ldr r0, [r4]
    movs.n r3, #0
    str r3, [r4]
#else
    ldr r0, [r2, #_thread_offset_to_basepri]
    d344:	6f50      	ldr	r0, [r2, #116]	; 0x74
    movs r3, #0
    d346:	2300      	movs	r3, #0
    str r3, [r2, #_thread_offset_to_basepri]
    d348:	6753      	str	r3, [r2, #116]	; 0x74
    /* restore r4-r7, go back 9*4 bytes to the start of the stored block */
    subs r0, #36
    ldmia r0!, {r4-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    /* restore BASEPRI for the incoming thread */
    msr BASEPRI, r0
    d34a:	f380 8811 	msr	BASEPRI, r0
    isb
#endif

#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
    /* Re-program dynamic memory map */
    push {r2,lr}
    d34e:	b504      	push	{r2, lr}
    mov r0, r2 /* _current thread */
    d350:	4610      	mov	r0, r2
    bl z_arm_configure_dynamic_mpu_regions
    d352:	f000 fa2f 	bl	d7b4 <z_arm_configure_dynamic_mpu_regions>
    pop {r2,lr}
    d356:	e8bd 4004 	ldmia.w	sp!, {r2, lr}
    isb

#endif

    /* load callee-saved + psp from thread */
    add r0, r2, #_thread_offset_to_callee_saved
    d35a:	f102 0030 	add.w	r0, r2, #48	; 0x30
    ldmia r0, {v1-v8, ip}
    d35e:	e890 1ff0 	ldmia.w	r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip}
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
    msr PSP, ip
    d362:	f38c 8809 	msr	PSP, ip

    /*
     * Cortex-M: return from PendSV exception
     * Cortex-R: return to the caller (z_arm_{exc,int}_exit, or z_arm_svc)
     */
    bx lr
    d366:	4770      	bx	lr
    ldr r1, =_kernel
    d368:	20000338 	.word	0x20000338
    ldr v4, =_SCS_ICSR
    d36c:	e000ed04 	.word	0xe000ed04

0000d370 <z_arm_svc>:
  bne _stack_frame_endif
_stack_frame_msp:
  mrs r0, MSP
_stack_frame_endif:
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    tst lr, #_EXC_RETURN_SPSEL_Msk /* did we come from thread mode ? */
    d370:	f01e 0f04 	tst.w	lr, #4
    ite eq  /* if zero (equal), came from handler mode */
    d374:	bf0c      	ite	eq
        mrseq r0, MSP   /* handler mode, stack frame is on MSP */
    d376:	f3ef 8008 	mrseq	r0, MSP
        mrsne r0, PSP   /* thread mode, stack frame is on PSP */
    d37a:	f3ef 8009 	mrsne	r0, PSP
#endif


    /* Figure out what SVC call number was invoked */

    ldr r1, [r0, #24]   /* grab address of PC from stack frame */
    d37e:	6981      	ldr	r1, [r0, #24]
     */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    subs r1, r1, #2
    ldrb r1, [r1]
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    ldrb r1, [r1, #-2]
    d380:	f811 1c02 	ldrb.w	r1, [r1, #-2]
#endif
    bne _oops

#endif /* CONFIG_USERSPACE */

    cmp r1, #2
    d384:	2902      	cmp	r1, #2
    beq _oops
    d386:	d0ff      	beq.n	d388 <_oops>

0000d388 <_oops>:
    /* exception return is done in z_arm_int_exit() */
    b z_arm_int_exit
#endif

_oops:
    push {r0, lr}
    d388:	b501      	push	{r0, lr}
    bl z_do_kernel_oops
    d38a:	f002 ff44 	bl	10216 <z_do_kernel_oops>
    /* return from SVC exception is done here */
    pop {r0, pc}
    d38e:	bd01      	pop	{r0, pc}

0000d390 <arch_new_thread>:

#if defined(CONFIG_CPU_CORTEX_M)
	/* force ARM mode by clearing LSB of address */
	iframe->pc &= 0xfffffffe;
#endif
	iframe->a1 = (uint32_t)entry;
    d390:	f842 3c20 	str.w	r3, [r2, #-32]
	iframe->a2 = (uint32_t)p1;
    d394:	9b00      	ldr	r3, [sp, #0]
    d396:	f842 3c1c 	str.w	r3, [r2, #-28]
	iframe->pc &= 0xfffffffe;
    d39a:	490a      	ldr	r1, [pc, #40]	; (d3c4 <arch_new_thread+0x34>)
	iframe->a3 = (uint32_t)p2;
    d39c:	9b01      	ldr	r3, [sp, #4]
    d39e:	f842 3c18 	str.w	r3, [r2, #-24]
	iframe->a4 = (uint32_t)p3;
    d3a2:	9b02      	ldr	r3, [sp, #8]
    d3a4:	f842 3c14 	str.w	r3, [r2, #-20]
	iframe->pc &= 0xfffffffe;
    d3a8:	f021 0101 	bic.w	r1, r1, #1

#if defined(CONFIG_CPU_CORTEX_M)
	iframe->xpsr =
    d3ac:	f04f 7380 	mov.w	r3, #16777216	; 0x1000000
    d3b0:	f842 3c04 	str.w	r3, [r2, #-4]
	iframe->pc &= 0xfffffffe;
    d3b4:	f842 1c08 	str.w	r1, [r2, #-8]
	iframe->xpsr |= T_BIT;
#endif /* CONFIG_COMPILER_ISA_THUMB2 */
#endif /* CONFIG_CPU_CORTEX_M */

	thread->callee_saved.psp = (uint32_t)iframe;
	thread->arch.basepri = 0;
    d3b8:	2300      	movs	r3, #0
	iframe = Z_STACK_PTR_TO_FRAME(struct __basic_sf, stack_ptr);
    d3ba:	3a20      	subs	r2, #32
	thread->callee_saved.psp = (uint32_t)iframe;
    d3bc:	6502      	str	r2, [r0, #80]	; 0x50
	thread->arch.basepri = 0;
    d3be:	6743      	str	r3, [r0, #116]	; 0x74
#endif
	/*
	 * initial values in all other registers/thread entries are
	 * irrelevant.
	 */
}
    d3c0:	4770      	bx	lr
    d3c2:	bf00      	nop
    d3c4:	00010145 	.word	0x00010145

0000d3c8 <z_check_thread_stack_fail>:
 *         thread stack corruption, otherwise return 0.
 */
uint32_t z_check_thread_stack_fail(const uint32_t fault_addr, const uint32_t psp)
{
#if defined(CONFIG_MULTITHREADING)
	const struct k_thread *thread = _current;
    d3c8:	4a09      	ldr	r2, [pc, #36]	; (d3f0 <z_check_thread_stack_fail+0x28>)
{
    d3ca:	4603      	mov	r3, r0
	const struct k_thread *thread = _current;
    d3cc:	6890      	ldr	r0, [r2, #8]

	if (thread == NULL) {
    d3ce:	b170      	cbz	r0, d3ee <z_check_thread_stack_fail+0x26>
			return thread->stack_info.start;
		}
	}
#else /* CONFIG_USERSPACE */
#if defined(CONFIG_MULTITHREADING)
	if (IS_MPU_GUARD_VIOLATION(thread->stack_info.start - guard_len,
    d3d0:	f113 0f16 	cmn.w	r3, #22
    d3d4:	6e40      	ldr	r0, [r0, #100]	; 0x64
    d3d6:	d005      	beq.n	d3e4 <z_check_thread_stack_fail+0x1c>
    d3d8:	f1a0 0220 	sub.w	r2, r0, #32
    d3dc:	429a      	cmp	r2, r3
    d3de:	d805      	bhi.n	d3ec <z_check_thread_stack_fail+0x24>
    d3e0:	4283      	cmp	r3, r0
    d3e2:	d203      	bcs.n	d3ec <z_check_thread_stack_fail+0x24>
		return (uint32_t)Z_THREAD_STACK_BUFFER(z_main_stack);
	}
#endif
#endif /* CONFIG_USERSPACE */

	return 0;
    d3e4:	4281      	cmp	r1, r0
    d3e6:	bf28      	it	cs
    d3e8:	2000      	movcs	r0, #0
    d3ea:	4770      	bx	lr
    d3ec:	2000      	movs	r0, #0
}
    d3ee:	4770      	bx	lr
    d3f0:	20000338 	.word	0x20000338

0000d3f4 <arch_switch_to_main_thread>:
#endif /* CONFIG_FPU */
}

void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr,
				k_thread_entry_t _main)
{
    d3f4:	b508      	push	{r3, lr}
	z_arm_prepare_switch_to_main();

	_current = main_thread;
    d3f6:	4b09      	ldr	r3, [pc, #36]	; (d41c <arch_switch_to_main_thread+0x28>)
    d3f8:	6098      	str	r0, [r3, #8]
{
    d3fa:	460d      	mov	r5, r1
    d3fc:	4614      	mov	r4, r2
#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
	/*
	 * If stack protection is enabled, make sure to set it
	 * before jumping to thread entry function
	 */
	z_arm_configure_dynamic_mpu_regions(main_thread);
    d3fe:	f000 f9d9 	bl	d7b4 <z_arm_configure_dynamic_mpu_regions>

	/*
	 * Set PSP to the highest address of the main stack
	 * before enabling interrupts and jumping to main.
	 */
	__asm__ volatile (
    d402:	4620      	mov	r0, r4
    d404:	f385 8809 	msr	PSP, r5
    d408:	2100      	movs	r1, #0
    d40a:	b663      	cpsie	if
    d40c:	f381 8811 	msr	BASEPRI, r1
    d410:	f3bf 8f6f 	isb	sy
    d414:	2200      	movs	r2, #0
    d416:	2300      	movs	r3, #0
    d418:	f002 fe94 	bl	10144 <z_thread_entry>
	:
	: "r" (_main), "r" (stack_ptr)
	: "r0" /* not to be overwritten by msr PSP, %1 */
	);

	CODE_UNREACHABLE;
    d41c:	20000338 	.word	0x20000338

0000d420 <_isr_wrapper>:
 *
 */
SECTION_FUNC(TEXT, _isr_wrapper)

#if defined(CONFIG_CPU_CORTEX_M)
	push {r0,lr}		/* r0, lr are now the first items on the stack */
    d420:	b501      	push	{r0, lr}
	 * Disable interrupts to prevent nesting while exiting idle state. This
	 * is only necessary for the Cortex-M because it is the only ARM
	 * architecture variant that automatically enables interrupts when
	 * entering an ISR.
	 */
	cpsid i  /* PRIMASK = 1 */
    d422:	b672      	cpsid	i
#endif

	/* is this a wakeup from idle ? */
	ldr r2, =_kernel
    d424:	4a0b      	ldr	r2, [pc, #44]	; (d454 <_isr_wrapper+0x34>)
	/* requested idle duration, in ticks */
	ldr r0, [r2, #_kernel_offset_to_idle]
    d426:	6990      	ldr	r0, [r2, #24]
	cmp r0, #0
    d428:	2800      	cmp	r0, #0
	str r1, [r2, #_kernel_offset_to_idle]
	bl z_pm_save_idle_exit
_idle_state_cleared:

#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	ittt ne
    d42a:	bf1e      	ittt	ne
	movne	r1, #0
    d42c:	2100      	movne	r1, #0
		/* clear kernel idle state */
		strne	r1, [r2, #_kernel_offset_to_idle]
    d42e:	6191      	strne	r1, [r2, #24]
		blne	z_pm_save_idle_exit
    d430:	f003 f9c6 	blne	107c0 <z_pm_save_idle_exit>
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

#if defined(CONFIG_CPU_CORTEX_M)
	cpsie i		/* re-enable interrupts (PRIMASK = 0) */
    d434:	b662      	cpsie	i
#endif

#endif /* CONFIG_PM */

#if defined(CONFIG_CPU_CORTEX_M)
	mrs r0, IPSR	/* get exception number */
    d436:	f3ef 8005 	mrs	r0, IPSR
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r1, =16
	subs r0, r1	/* get IRQ number */
	lsls r0, #3	/* table is 8-byte wide */
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	sub r0, r0, #16	/* get IRQ number */
    d43a:	f1a0 0010 	sub.w	r0, r0, #16
	lsl r0, r0, #3	/* table is 8-byte wide */
    d43e:	ea4f 00c0 	mov.w	r0, r0, lsl #3
	lsl r1, r1, #3
	cmp r0, r1
	bge spurious_continue
#endif /* !CONFIG_CPU_CORTEX_M */

	ldr r1, =_sw_isr_table
    d442:	4905      	ldr	r1, [pc, #20]	; (d458 <_isr_wrapper+0x38>)
	add r1, r1, r0	/* table entry: ISRs must have their MSB set to stay
    d444:	4401      	add	r1, r0
			 * in thumb mode */

	ldm r1!,{r0,r3}	/* arg in r0, ISR in r3 */
    d446:	c909      	ldmia	r1!, {r0, r3}
	blx r3		/* call ISR */
    d448:	4798      	blx	r3

#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	pop {r0, r3}
	mov lr, r3
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	pop {r0, lr}
    d44a:	e8bd 4001 	ldmia.w	sp!, {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */

	/* Use 'bx' instead of 'b' because 'bx' can jump further, and use
	 * 'bx' instead of 'blx' because exception return is done in
	 * z_arm_int_exit() */
	ldr r1, =z_arm_int_exit
    d44e:	4903      	ldr	r1, [pc, #12]	; (d45c <_isr_wrapper+0x3c>)
	bx r1
    d450:	4708      	bx	r1
    d452:	0000      	.short	0x0000
	ldr r2, =_kernel
    d454:	20000338 	.word	0x20000338
	ldr r1, =_sw_isr_table
    d458:	00010a30 	.word	0x00010a30
	ldr r1, =z_arm_int_exit
    d45c:	0000d461 	.word	0x0000d461

0000d460 <z_arm_exc_exit>:
 */

SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_exc_exit)

#ifdef CONFIG_PREEMPT_ENABLED
	ldr r3, =_kernel
    d460:	4b04      	ldr	r3, [pc, #16]	; (d474 <_EXIT_EXC+0x2>)

	ldr r1, [r3, #_kernel_offset_to_current]
    d462:	6899      	ldr	r1, [r3, #8]
	ldr r0, [r3, #_kernel_offset_to_ready_q_cache]
    d464:	69d8      	ldr	r0, [r3, #28]
	cmp r0, r1
    d466:	4288      	cmp	r0, r1
	beq _EXIT_EXC
    d468:	d003      	beq.n	d472 <_EXIT_EXC>

	/* context switch required, pend the PendSV exception */
	ldr r1, =_SCS_ICSR
    d46a:	4903      	ldr	r1, [pc, #12]	; (d478 <_EXIT_EXC+0x6>)
	ldr r2, =_SCS_ICSR_PENDSV
    d46c:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
	str r2, [r1]
    d470:	600a      	str	r2, [r1, #0]

0000d472 <_EXIT_EXC>:
#else
	pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_STACK_SENTINEL */

	bx lr
    d472:	4770      	bx	lr
	ldr r3, =_kernel
    d474:	20000338 	.word	0x20000338
	ldr r1, =_SCS_ICSR
    d478:	e000ed04 	.word	0xe000ed04

0000d47c <mem_manage_fault>:
 *
 * @return error code to identify the fatal error reason
 */
static uint32_t mem_manage_fault(z_arch_esf_t *esf, int from_hard_fault,
			      bool *recoverable)
{
    d47c:	b538      	push	{r3, r4, r5, lr}
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	uint32_t mmfar = -EINVAL;

	PR_FAULT_INFO("***** MPU FAULT *****");

	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
    d47e:	4b1c      	ldr	r3, [pc, #112]	; (d4f0 <mem_manage_fault+0x74>)
{
    d480:	4614      	mov	r4, r2
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
    d482:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Stacking error (context area might be"
			" not valid)");
	}
	if ((SCB->CFSR & SCB_CFSR_MUNSTKERR_Msk) != 0) {
    d484:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Unstacking error");
	}
	if ((SCB->CFSR & SCB_CFSR_DACCVIOL_Msk) != 0) {
    d486:	6a9a      	ldr	r2, [r3, #40]	; 0x28
{
    d488:	4605      	mov	r5, r0
	if ((SCB->CFSR & SCB_CFSR_DACCVIOL_Msk) != 0) {
    d48a:	0790      	lsls	r0, r2, #30
    d48c:	d520      	bpl.n	d4d0 <mem_manage_fault+0x54>
		 * The MMFAR address is valid only if this bit is 1.
		 *
		 * Software must follow this sequence because another higher
		 * priority exception might change the MMFAR value.
		 */
		uint32_t temp = SCB->MMFAR;
    d48e:	6b58      	ldr	r0, [r3, #52]	; 0x34

		if ((SCB->CFSR & SCB_CFSR_MMARVALID_Msk) != 0) {
    d490:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    d492:	0612      	lsls	r2, r2, #24
    d494:	d51c      	bpl.n	d4d0 <mem_manage_fault+0x54>
			mmfar = temp;
			PR_EXC("  MMFAR Address: 0x%x", mmfar);
			if (from_hard_fault != 0) {
    d496:	b119      	cbz	r1, d4a0 <mem_manage_fault+0x24>
				/* clear SCB_MMAR[VALID] to reset */
				SCB->CFSR &= ~SCB_CFSR_MMARVALID_Msk;
    d498:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    d49a:	f022 0280 	bic.w	r2, r2, #128	; 0x80
    d49e:	629a      	str	r2, [r3, #40]	; 0x28
			}
		}
	}
	if ((SCB->CFSR & SCB_CFSR_IACCVIOL_Msk) != 0) {
    d4a0:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Instruction Access Violation");
	}
#if defined(CONFIG_ARMV7_M_ARMV8_M_FP)
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    d4a2:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	 * crossed into an area beyond the thread stack.]
	 *
	 * Data Access Violation errors may or may not be caused by
	 * thread stack overflows.
	 */
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) ||
    d4a4:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    d4a6:	06d2      	lsls	r2, r2, #27
    d4a8:	d415      	bmi.n	d4d6 <mem_manage_fault+0x5a>
		(SCB->CFSR & SCB_CFSR_DACCVIOL_Msk)) {
    d4aa:	6a9b      	ldr	r3, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) ||
    d4ac:	079b      	lsls	r3, r3, #30
    d4ae:	d412      	bmi.n	d4d6 <mem_manage_fault+0x5a>
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    d4b0:	2000      	movs	r0, #0
	 * lazy stacking Memory Manage fault. At the time of writing, this
	 * can happen when printing.  If that's true, we should clear the
	 * pending flag in addition to the clearing the reason for the fault
	 */
#if defined(CONFIG_ARMV7_M_ARMV8_M_FP)
	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
    d4b2:	4b0f      	ldr	r3, [pc, #60]	; (d4f0 <mem_manage_fault+0x74>)
    d4b4:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    d4b6:	0692      	lsls	r2, r2, #26
		SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTPENDED_Msk;
    d4b8:	bf42      	ittt	mi
    d4ba:	6a5a      	ldrmi	r2, [r3, #36]	; 0x24
    d4bc:	f422 5200 	bicmi.w	r2, r2, #8192	; 0x2000
    d4c0:	625a      	strmi	r2, [r3, #36]	; 0x24
	}
#endif /* CONFIG_ARMV7_M_ARMV8_M_FP */

	/* clear MMFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_MEMFAULTSR_Msk;
    d4c2:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    d4c4:	f042 02ff 	orr.w	r2, r2, #255	; 0xff
    d4c8:	629a      	str	r2, [r3, #40]	; 0x28

	/* Assess whether system shall ignore/recover from this MPU fault. */
	*recoverable = memory_fault_recoverable(esf, true);
    d4ca:	2300      	movs	r3, #0
    d4cc:	7023      	strb	r3, [r4, #0]

	return reason;
}
    d4ce:	bd38      	pop	{r3, r4, r5, pc}
	uint32_t mmfar = -EINVAL;
    d4d0:	f06f 0015 	mvn.w	r0, #21
    d4d4:	e7e4      	b.n	d4a0 <mem_manage_fault+0x24>
		if (SCB->ICSR & SCB_ICSR_RETTOBASE_Msk) {
    d4d6:	4b06      	ldr	r3, [pc, #24]	; (d4f0 <mem_manage_fault+0x74>)
    d4d8:	685b      	ldr	r3, [r3, #4]
    d4da:	0519      	lsls	r1, r3, #20
    d4dc:	d5e8      	bpl.n	d4b0 <mem_manage_fault+0x34>
			uint32_t min_stack_ptr = z_check_thread_stack_fail(mmfar,
    d4de:	4629      	mov	r1, r5
    d4e0:	f7ff ff72 	bl	d3c8 <z_check_thread_stack_fail>
			if (min_stack_ptr) {
    d4e4:	2800      	cmp	r0, #0
    d4e6:	d0e3      	beq.n	d4b0 <mem_manage_fault+0x34>
  \details Assigns the given value to the Process Stack Pointer (PSP).
  \param [in]    topOfProcStack  Process Stack Pointer value to set
 */
__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
{
  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
    d4e8:	f380 8809 	msr	PSP, r0
				reason = K_ERR_STACK_CHK_FAIL;
    d4ec:	2002      	movs	r0, #2
    d4ee:	e7e0      	b.n	d4b2 <mem_manage_fault+0x36>
    d4f0:	e000ed00 	.word	0xe000ed00

0000d4f4 <bus_fault.constprop.0>:
{
	uint32_t reason = K_ERR_CPU_EXCEPTION;

	PR_FAULT_INFO("***** BUS FAULT *****");

	if (SCB->CFSR & SCB_CFSR_STKERR_Msk) {
    d4f4:	4b0d      	ldr	r3, [pc, #52]	; (d52c <bus_fault.constprop.0+0x38>)
    d4f6:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Stacking error");
	}
	if (SCB->CFSR & SCB_CFSR_UNSTKERR_Msk) {
    d4f8:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Unstacking error");
	}
	if (SCB->CFSR & SCB_CFSR_PRECISERR_Msk) {
    d4fa:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    d4fc:	0592      	lsls	r2, r2, #22
    d4fe:	d508      	bpl.n	d512 <bus_fault.constprop.0+0x1e>
		 * The BFAR address is valid only if this bit is 1.
		 *
		 * Software must follow this sequence because another
		 * higher priority exception might change the BFAR value.
		 */
		STORE_xFAR(bfar, SCB->BFAR);
    d500:	6b9a      	ldr	r2, [r3, #56]	; 0x38

		if ((SCB->CFSR & SCB_CFSR_BFARVALID_Msk) != 0) {
    d502:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    d504:	0412      	lsls	r2, r2, #16
    d506:	d504      	bpl.n	d512 <bus_fault.constprop.0+0x1e>
			PR_EXC("  BFAR Address: 0x%x", bfar);
			if (from_hard_fault != 0) {
    d508:	b118      	cbz	r0, d512 <bus_fault.constprop.0+0x1e>
				/* clear SCB_CFSR_BFAR[VALID] to reset */
				SCB->CFSR &= ~SCB_CFSR_BFARVALID_Msk;
    d50a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    d50c:	f422 4200 	bic.w	r2, r2, #32768	; 0x8000
    d510:	629a      	str	r2, [r3, #40]	; 0x28
			}
		}
	}
	if (SCB->CFSR & SCB_CFSR_IMPRECISERR_Msk) {
    d512:	4b06      	ldr	r3, [pc, #24]	; (d52c <bus_fault.constprop.0+0x38>)
    d514:	6a9a      	ldr	r2, [r3, #40]	; 0x28
		PR_FAULT_INFO("  Imprecise data bus error");
	}
	if ((SCB->CFSR & SCB_CFSR_IBUSERR_Msk) != 0) {
    d516:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    d518:	05d2      	lsls	r2, r2, #23
		PR_FAULT_INFO("  Instruction bus error");
#if !defined(CONFIG_ARMV7_M_ARMV8_M_FP)
	}
#else
	} else if (SCB->CFSR & SCB_CFSR_LSPERR_Msk) {
    d51a:	bf58      	it	pl
    d51c:	6a9a      	ldrpl	r2, [r3, #40]	; 0x28
		SYSMPU->CESR &= ~sperr;
	}
#endif /* defined(CONFIG_ARM_MPU) && defined(CONFIG_CPU_HAS_NXP_MPU) */

	/* clear BFSR sticky bits */
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
    d51e:	6a9a      	ldr	r2, [r3, #40]	; 0x28

	*recoverable = memory_fault_recoverable(esf, true);
    d520:	2000      	movs	r0, #0
	SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk;
    d522:	f442 427f 	orr.w	r2, r2, #65280	; 0xff00
    d526:	629a      	str	r2, [r3, #40]	; 0x28
	*recoverable = memory_fault_recoverable(esf, true);
    d528:	7008      	strb	r0, [r1, #0]

	return reason;
}
    d52a:	4770      	bx	lr
    d52c:	e000ed00 	.word	0xe000ed00

0000d530 <z_arm_fault>:
 * @param callee_regs Callee-saved registers (R4-R11, PSP)
 *
 */
void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return,
	_callee_saved_t *callee_regs)
{
    d530:	b570      	push	{r4, r5, r6, lr}
	uint32_t reason = K_ERR_CPU_EXCEPTION;
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    d532:	4b48      	ldr	r3, [pc, #288]	; (d654 <z_arm_fault+0x124>)
    d534:	685b      	ldr	r3, [r3, #4]
{
    d536:	b08a      	sub	sp, #40	; 0x28
    d538:	460d      	mov	r5, r1
	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
    d53a:	f3c3 0308 	ubfx	r3, r3, #0, #9
    d53e:	2600      	movs	r6, #0
    d540:	f386 8811 	msr	BASEPRI, r6
    d544:	f3bf 8f6f 	isb	sy
	if ((exc_return & EXC_RETURN_INDICATOR_PREFIX) !=
    d548:	f002 417f 	and.w	r1, r2, #4278190080	; 0xff000000
    d54c:	f1b1 4f7f 	cmp.w	r1, #4278190080	; 0xff000000
    d550:	d111      	bne.n	d576 <z_arm_fault+0x46>
	if ((exc_return & EXC_RETURN_MODE_THREAD) &&
    d552:	f002 010c 	and.w	r1, r2, #12
    d556:	2908      	cmp	r1, #8
    d558:	d00d      	beq.n	d576 <z_arm_fault+0x46>
		if (exc_return & EXC_RETURN_MODE_THREAD) {
    d55a:	0711      	lsls	r1, r2, #28
    d55c:	d401      	bmi.n	d562 <z_arm_fault+0x32>
			ptr_esf = (z_arch_esf_t *)msp;
    d55e:	4605      	mov	r5, r0
			*nested_exc = true;
    d560:	2601      	movs	r6, #1
	*recoverable = false;
    d562:	2200      	movs	r2, #0
	switch (fault) {
    d564:	3b03      	subs	r3, #3
	*recoverable = false;
    d566:	f88d 2007 	strb.w	r2, [sp, #7]
	switch (fault) {
    d56a:	2b03      	cmp	r3, #3
    d56c:	d86b      	bhi.n	d646 <z_arm_fault+0x116>
    d56e:	e8df f003 	tbb	[pc, r3]
    d572:	5504      	.short	0x5504
    d574:	5d59      	.short	0x5d59
		return NULL;
    d576:	4635      	mov	r5, r6
    d578:	e7f3      	b.n	d562 <z_arm_fault+0x32>
	if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk) != 0) {
    d57a:	4b36      	ldr	r3, [pc, #216]	; (d654 <z_arm_fault+0x124>)
    d57c:	6adc      	ldr	r4, [r3, #44]	; 0x2c
    d57e:	f014 0402 	ands.w	r4, r4, #2
    d582:	d160      	bne.n	d646 <z_arm_fault+0x116>
	} else if ((SCB->HFSR & SCB_HFSR_DEBUGEVT_Msk) != 0) {
    d584:	6ada      	ldr	r2, [r3, #44]	; 0x2c
    d586:	2a00      	cmp	r2, #0
    d588:	db15      	blt.n	d5b6 <z_arm_fault+0x86>
	} else if ((SCB->HFSR & SCB_HFSR_FORCED_Msk) != 0) {
    d58a:	6ada      	ldr	r2, [r3, #44]	; 0x2c
    d58c:	0052      	lsls	r2, r2, #1
    d58e:	d512      	bpl.n	d5b6 <z_arm_fault+0x86>
	uint16_t fault_insn = *(ret_addr - 1);
    d590:	69aa      	ldr	r2, [r5, #24]
	if (((fault_insn & 0xff00) == _SVC_OPCODE) &&
    d592:	f832 1c02 	ldrh.w	r1, [r2, #-2]
    d596:	f64d 7202 	movw	r2, #57090	; 0xdf02
    d59a:	4291      	cmp	r1, r2
    d59c:	d00a      	beq.n	d5b4 <z_arm_fault+0x84>
		} else if (SCB_MMFSR != 0) {
    d59e:	f893 2028 	ldrb.w	r2, [r3, #40]	; 0x28
    d5a2:	b30a      	cbz	r2, d5e8 <z_arm_fault+0xb8>
			reason = mem_manage_fault(esf, 1, recoverable);
    d5a4:	f10d 0207 	add.w	r2, sp, #7
    d5a8:	2101      	movs	r1, #1
		reason = mem_manage_fault(esf, 0, recoverable);
    d5aa:	4628      	mov	r0, r5
    d5ac:	f7ff ff66 	bl	d47c <mem_manage_fault>
		reason = bus_fault(esf, 0, recoverable);
    d5b0:	4604      	mov	r4, r0
		break;
    d5b2:	e000      	b.n	d5b6 <z_arm_fault+0x86>
			reason = esf->basic.r0;
    d5b4:	682c      	ldr	r4, [r5, #0]
#ifdef CONFIG_DEBUG_COREDUMP
	z_arm_coredump_fault_sp = POINTER_TO_UINT(esf);
#endif

	reason = fault_handle(esf, fault, &recoverable);
	if (recoverable) {
    d5b6:	f89d 3007 	ldrb.w	r3, [sp, #7]
    d5ba:	b99b      	cbnz	r3, d5e4 <z_arm_fault+0xb4>
		return;
	}

	/* Copy ESF */
#if !defined(CONFIG_EXTRA_EXCEPTION_INFO)
	memcpy(&esf_copy, esf, sizeof(z_arch_esf_t));
    d5bc:	2220      	movs	r2, #32
    d5be:	4629      	mov	r1, r5
    d5c0:	a802      	add	r0, sp, #8
    d5c2:	f002 fe51 	bl	10268 <memcpy>
	/* Overwrite stacked IPSR to mark a nested exception,
	 * or a return to Thread mode. Note that this may be
	 * required, if the retrieved ESF contents are invalid
	 * due to, for instance, a stacking error.
	 */
	if (nested_exc) {
    d5c6:	9b09      	ldr	r3, [sp, #36]	; 0x24
    d5c8:	2e00      	cmp	r6, #0
    d5ca:	d03e      	beq.n	d64a <z_arm_fault+0x11a>
		if ((esf_copy.basic.xpsr & IPSR_ISR_Msk) == 0) {
    d5cc:	f3c3 0208 	ubfx	r2, r3, #0, #9
    d5d0:	b922      	cbnz	r2, d5dc <z_arm_fault+0xac>
			esf_copy.basic.xpsr |= IPSR_ISR_Msk;
    d5d2:	ea6f 2353 	mvn.w	r3, r3, lsr #9
    d5d6:	ea6f 2343 	mvn.w	r3, r3, lsl #9
		}
	} else {
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    d5da:	9309      	str	r3, [sp, #36]	; 0x24
	}

	z_arm_fatal_error(reason, &esf_copy);
    d5dc:	a902      	add	r1, sp, #8
    d5de:	4620      	mov	r0, r4
    d5e0:	f002 fe17 	bl	10212 <z_arm_fatal_error>
}
    d5e4:	b00a      	add	sp, #40	; 0x28
    d5e6:	bd70      	pop	{r4, r5, r6, pc}
		} else if (SCB_BFSR != 0) {
    d5e8:	f893 2029 	ldrb.w	r2, [r3, #41]	; 0x29
    d5ec:	b12a      	cbz	r2, d5fa <z_arm_fault+0xca>
			reason = bus_fault(esf, 1, recoverable);
    d5ee:	f10d 0107 	add.w	r1, sp, #7
    d5f2:	2001      	movs	r0, #1
		reason = bus_fault(esf, 0, recoverable);
    d5f4:	f7ff ff7e 	bl	d4f4 <bus_fault.constprop.0>
    d5f8:	e7da      	b.n	d5b0 <z_arm_fault+0x80>
		} else if (SCB_UFSR != 0) {
    d5fa:	8d5a      	ldrh	r2, [r3, #42]	; 0x2a
    d5fc:	b292      	uxth	r2, r2
    d5fe:	2a00      	cmp	r2, #0
    d600:	d0d9      	beq.n	d5b6 <z_arm_fault+0x86>
	if ((SCB->CFSR & SCB_CFSR_DIVBYZERO_Msk) != 0) {
    d602:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_UNALIGNED_Msk) != 0) {
    d604:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_NOCP_Msk) != 0) {
    d606:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_INVPC_Msk) != 0) {
    d608:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_INVSTATE_Msk) != 0) {
    d60a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_UNDEFINSTR_Msk) != 0) {
    d60c:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    d60e:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    d610:	ea6f 4202 	mvn.w	r2, r2, lsl #16
    d614:	ea6f 4212 	mvn.w	r2, r2, lsr #16
    d618:	629a      	str	r2, [r3, #40]	; 0x28
	return reason;
    d61a:	e7cc      	b.n	d5b6 <z_arm_fault+0x86>
		reason = mem_manage_fault(esf, 0, recoverable);
    d61c:	f10d 0207 	add.w	r2, sp, #7
    d620:	2100      	movs	r1, #0
    d622:	e7c2      	b.n	d5aa <z_arm_fault+0x7a>
		reason = bus_fault(esf, 0, recoverable);
    d624:	f10d 0107 	add.w	r1, sp, #7
    d628:	2000      	movs	r0, #0
    d62a:	e7e3      	b.n	d5f4 <z_arm_fault+0xc4>
	if ((SCB->CFSR & SCB_CFSR_DIVBYZERO_Msk) != 0) {
    d62c:	4b09      	ldr	r3, [pc, #36]	; (d654 <z_arm_fault+0x124>)
    d62e:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_UNALIGNED_Msk) != 0) {
    d630:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_NOCP_Msk) != 0) {
    d632:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_INVPC_Msk) != 0) {
    d634:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_INVSTATE_Msk) != 0) {
    d636:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	if ((SCB->CFSR & SCB_CFSR_UNDEFINSTR_Msk) != 0) {
    d638:	6a9a      	ldr	r2, [r3, #40]	; 0x28
	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
    d63a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    d63c:	ea6f 4202 	mvn.w	r2, r2, lsl #16
    d640:	ea6f 4212 	mvn.w	r2, r2, lsr #16
    d644:	629a      	str	r2, [r3, #40]	; 0x28
	uint32_t reason = K_ERR_CPU_EXCEPTION;
    d646:	2400      	movs	r4, #0
    d648:	e7b5      	b.n	d5b6 <z_arm_fault+0x86>
		esf_copy.basic.xpsr &= ~(IPSR_ISR_Msk);
    d64a:	f423 73ff 	bic.w	r3, r3, #510	; 0x1fe
    d64e:	f023 0301 	bic.w	r3, r3, #1
    d652:	e7c2      	b.n	d5da <z_arm_fault+0xaa>
    d654:	e000ed00 	.word	0xe000ed00

0000d658 <z_arm_fault_init>:
 */
void z_arm_fault_init(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
    d658:	4a02      	ldr	r2, [pc, #8]	; (d664 <z_arm_fault_init+0xc>)
    d65a:	6953      	ldr	r3, [r2, #20]
    d65c:	f043 0310 	orr.w	r3, r3, #16
    d660:	6153      	str	r3, [r2, #20]
	SCB->CCR |= SCB_CCR_STKOFHFNMIGN_Msk;
#endif /* CONFIG_BUILTIN_STACK_GUARD */
#ifdef CONFIG_TRAP_UNALIGNED_ACCESS
	SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif /* CONFIG_TRAP_UNALIGNED_ACCESS */
}
    d662:	4770      	bx	lr
    d664:	e000ed00 	.word	0xe000ed00

0000d668 <z_arm_bus_fault>:
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_exc_spurious)

	mrs r0, MSP
    d668:	f3ef 8008 	mrs	r0, MSP
	mrs r1, PSP
    d66c:	f3ef 8109 	mrs	r1, PSP
	push {r0, lr}
    d670:	b501      	push	{r0, lr}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	push {r4-r11}
#endif
	mov  r3, sp /* pointer to _callee_saved_t */
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
	mov r2, lr /* EXC_RETURN */
    d672:	4672      	mov	r2, lr
	bl z_arm_fault
    d674:	f7ff ff5c 	bl	d530 <z_arm_fault>
	 * in this routine. Therefore, we can just reset
	 * the MSP to its value prior to entering the function
	 */
	add sp, #40
#endif
	pop {r0, pc}
    d678:	bd01      	pop	{r0, pc}
    d67a:	bf00      	nop

0000d67c <z_arm_interrupt_init>:
    d67c:	4804      	ldr	r0, [pc, #16]	; (d690 <z_arm_interrupt_init+0x14>)
 *
 */

void z_arm_interrupt_init(void)
{
	int irq = 0;
    d67e:	2300      	movs	r3, #0
    d680:	2120      	movs	r1, #32
    d682:	18c2      	adds	r2, r0, r3

	for (; irq < CONFIG_NUM_IRQS; irq++) {
    d684:	3301      	adds	r3, #1
    d686:	2b27      	cmp	r3, #39	; 0x27
    d688:	f882 1300 	strb.w	r1, [r2, #768]	; 0x300
    d68c:	d1f9      	bne.n	d682 <z_arm_interrupt_init+0x6>
		NVIC_SetPriority((IRQn_Type)irq, _IRQ_PRIO_OFFSET);
	}
}
    d68e:	4770      	bx	lr
    d690:	e000e100 	.word	0xe000e100

0000d694 <__start>:
 */
SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
    /* Reset CONTROL register */
    movs.n r0, #0
    d694:	2000      	movs	r0, #0
    msr CONTROL, r0
    d696:	f380 8814 	msr	CONTROL, r0
    isb
    d69a:	f3bf 8f6f 	isb	sy
#endif /* CONFIG_CPU_CORTEX_M_HAS_SPLIM */

#endif /* CONFIG_INIT_ARCH_HW_AT_BOOT */

#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
    bl z_arm_platform_init
    d69e:	f003 f981 	bl	109a4 <z_arm_platform_init>
#endif

#if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
#if defined(CONFIG_CPU_HAS_ARM_MPU)
    /* Disable MPU */
    movs.n r0, #0
    d6a2:	2000      	movs	r0, #0
    ldr r1, =_SCS_MPU_CTRL
    d6a4:	490d      	ldr	r1, [pc, #52]	; (d6dc <__start+0x48>)
    str r0, [r1]
    d6a6:	6008      	str	r0, [r1, #0]
    dsb
    d6a8:	f3bf 8f4f 	dsb	sy
#endif /* CONFIG_CPU_HAS_ARM_MPU */
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    d6ac:	480c      	ldr	r0, [pc, #48]	; (d6e0 <__start+0x4c>)
    msr msp, r0
    d6ae:	f380 8808 	msr	MSP, r0

    /* Initialize core architecture registers and system blocks */
    bl z_arm_init_arch_hw_at_boot
    d6b2:	f000 f82b 	bl	d70c <z_arm_init_arch_hw_at_boot>

    /* lock interrupts: will get unlocked when switch to main task */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
    cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
    movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
    d6b6:	2020      	movs	r0, #32
    msr BASEPRI, r0
    d6b8:	f380 8811 	msr	BASEPRI, r0

    /*
     * Set PSP and use it to boot without using MSP, so that it
     * gets set to z_interrupt_stacks during initialization.
     */
    ldr r0, =z_interrupt_stacks
    d6bc:	4809      	ldr	r0, [pc, #36]	; (d6e4 <__start+0x50>)
    ldr r1, =CONFIG_ISR_STACK_SIZE + MPU_GUARD_ALIGN_AND_SIZE
    d6be:	f44f 6102 	mov.w	r1, #2080	; 0x820
    adds r0, r0, r1
    d6c2:	1840      	adds	r0, r0, r1
    msr PSP, r0
    d6c4:	f380 8809 	msr	PSP, r0
    mrs r0, CONTROL
    d6c8:	f3ef 8014 	mrs	r0, CONTROL
    movs r1, #2
    d6cc:	2102      	movs	r1, #2
    orrs r0, r1 /* CONTROL_SPSEL_Msk */
    d6ce:	4308      	orrs	r0, r1
    msr CONTROL, r0
    d6d0:	f380 8814 	msr	CONTROL, r0
    /*
     * When changing the stack pointer, software must use an ISB instruction
     * immediately after the MSR instruction. This ensures that instructions
     * after the ISB instruction execute using the new stack pointer.
     */
    isb
    d6d4:	f3bf 8f6f 	isb	sy
    /*
     * 'bl' jumps the furthest of the branch instructions that are
     * supported on all platforms. So it is used when jumping to z_arm_prep_c
     * (even though we do not intend to return).
     */
    bl z_arm_prep_c
    d6d8:	f7ff fdea 	bl	d2b0 <z_arm_prep_c>
    ldr r1, =_SCS_MPU_CTRL
    d6dc:	e000ed94 	.word	0xe000ed94
    ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
    d6e0:	20000ba0 	.word	0x20000ba0
    ldr r0, =z_interrupt_stacks
    d6e4:	20000d20 	.word	0x20000d20

0000d6e8 <z_arm_clear_arm_mpu_config>:
void z_arm_clear_arm_mpu_config(void)
{
	int i;

	int num_regions =
		((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos);
    d6e8:	4907      	ldr	r1, [pc, #28]	; (d708 <z_arm_clear_arm_mpu_config+0x20>)
    d6ea:	f8d1 2090 	ldr.w	r2, [r1, #144]	; 0x90

	for (i = 0; i < num_regions; i++) {
    d6ee:	2300      	movs	r3, #0
	int num_regions =
    d6f0:	f3c2 2207 	ubfx	r2, r2, #8, #8
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
  MPU->RNR = rnr;
  MPU->RASR = 0U;
    d6f4:	4618      	mov	r0, r3
	for (i = 0; i < num_regions; i++) {
    d6f6:	4293      	cmp	r3, r2
    d6f8:	d100      	bne.n	d6fc <z_arm_clear_arm_mpu_config+0x14>
		ARM_MPU_ClrRegion(i);
	}
}
    d6fa:	4770      	bx	lr
  MPU->RNR = rnr;
    d6fc:	f8c1 3098 	str.w	r3, [r1, #152]	; 0x98
  MPU->RASR = 0U;
    d700:	f8c1 00a0 	str.w	r0, [r1, #160]	; 0xa0
	for (i = 0; i < num_regions; i++) {
    d704:	3301      	adds	r3, #1
    d706:	e7f6      	b.n	d6f6 <z_arm_clear_arm_mpu_config+0xe>
    d708:	e000ed00 	.word	0xe000ed00

0000d70c <z_arm_init_arch_hw_at_boot>:
 * This routine resets Cortex-M system control block
 * components and core registers.
 *
 */
void z_arm_init_arch_hw_at_boot(void)
{
    d70c:	b508      	push	{r3, lr}
  __ASM volatile ("cpsid i" : : : "memory");
    d70e:	b672      	cpsid	i
  \details Assigns the given value to the Fault Mask register.
  \param [in]    faultMask  Fault Mask value to set
 */
__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
{
  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
    d710:	2300      	movs	r3, #0
    d712:	f383 8813 	msr	FAULTMASK, r3

	/* Initialize System Control Block components */

#if defined(CONFIG_CPU_HAS_ARM_MPU) || defined(CONFIG_CPU_HAS_NXP_MPU)
	/* Clear MPU region configuration */
	z_arm_clear_arm_mpu_config();
    d716:	f7ff ffe7 	bl	d6e8 <z_arm_clear_arm_mpu_config>
#endif /* CONFIG_CPU_HAS_ARM_MPU */

	/* Disable NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
		NVIC->ICER[i] = 0xFFFFFFFF;
    d71a:	4b14      	ldr	r3, [pc, #80]	; (d76c <z_arm_init_arch_hw_at_boot+0x60>)
    d71c:	f04f 32ff 	mov.w	r2, #4294967295
    d720:	f8c3 2080 	str.w	r2, [r3, #128]	; 0x80
    d724:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
    d728:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
    d72c:	f8c3 208c 	str.w	r2, [r3, #140]	; 0x8c
    d730:	f8c3 2090 	str.w	r2, [r3, #144]	; 0x90
    d734:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
    d738:	f8c3 2098 	str.w	r2, [r3, #152]	; 0x98
    d73c:	f8c3 209c 	str.w	r2, [r3, #156]	; 0x9c
	}
	/* Clear pending NVIC interrupts */
	for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) {
		NVIC->ICPR[i] = 0xFFFFFFFF;
    d740:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
    d744:	f8c3 2184 	str.w	r2, [r3, #388]	; 0x184
    d748:	f8c3 2188 	str.w	r2, [r3, #392]	; 0x188
    d74c:	f8c3 218c 	str.w	r2, [r3, #396]	; 0x18c
    d750:	f8c3 2190 	str.w	r2, [r3, #400]	; 0x190
    d754:	f8c3 2194 	str.w	r2, [r3, #404]	; 0x194
    d758:	f8c3 2198 	str.w	r2, [r3, #408]	; 0x198
    d75c:	f8c3 219c 	str.w	r2, [r3, #412]	; 0x19c
  __ASM volatile ("cpsie i" : : : "memory");
    d760:	b662      	cpsie	i
  __ASM volatile ("dsb 0xF":::"memory");
    d762:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    d766:	f3bf 8f6f 	isb	sy
	/* Restore Interrupts */
	__enable_irq();

	__DSB();
	__ISB();
}
    d76a:	bd08      	pop	{r3, pc}
    d76c:	e000e100 	.word	0xe000e100

0000d770 <z_impl_k_thread_abort>:
#include <wait_q.h>
#include <sys/__assert.h>

void z_impl_k_thread_abort(k_tid_t thread)
{
	if (_current == thread) {
    d770:	4b08      	ldr	r3, [pc, #32]	; (d794 <z_impl_k_thread_abort+0x24>)
    d772:	689b      	ldr	r3, [r3, #8]
    d774:	4283      	cmp	r3, r0
    d776:	d10b      	bne.n	d790 <z_impl_k_thread_abort+0x20>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    d778:	f3ef 8305 	mrs	r3, IPSR
		if (arch_is_in_isr()) {
    d77c:	b143      	cbz	r3, d790 <z_impl_k_thread_abort+0x20>
			 * should no longer run after we return, so
			 * Trigger PendSV, in case we are in one of the
			 * situations where the isr check is true but there
			 * is not an implicit scheduler invocation.
			 */
			SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
    d77e:	4b06      	ldr	r3, [pc, #24]	; (d798 <z_impl_k_thread_abort+0x28>)
    d780:	685a      	ldr	r2, [r3, #4]
    d782:	f042 5280 	orr.w	r2, r2, #268435456	; 0x10000000
    d786:	605a      	str	r2, [r3, #4]
			/* Clear any system calls that may be pending
			 * as they have a higher priority than the PendSV
			 * handler and will check the stack of the thread
			 * being aborted.
			 */
			SCB->SHCSR &= ~SCB_SHCSR_SVCALLPENDED_Msk;
    d788:	6a5a      	ldr	r2, [r3, #36]	; 0x24
    d78a:	f422 4200 	bic.w	r2, r2, #32768	; 0x8000
    d78e:	625a      	str	r2, [r3, #36]	; 0x24
		}
	}

	z_thread_abort(thread);
    d790:	f002 ba50 	b.w	fc34 <z_thread_abort>
    d794:	20000338 	.word	0x20000338
    d798:	e000ed00 	.word	0xe000ed00

0000d79c <z_arm_configure_static_mpu_regions>:
	/* Configure the static MPU regions within firmware SRAM boundaries.
	 * Start address of the image is given by _image_ram_start. The end
	 * of the firmware SRAM area is marked by __kernel_ram_end, taking
	 * into account the unused SRAM area, as well.
	 */
	arm_core_mpu_configure_static_mpu_regions(static_regions,
    d79c:	4b02      	ldr	r3, [pc, #8]	; (d7a8 <z_arm_configure_static_mpu_regions+0xc>)
    d79e:	4a03      	ldr	r2, [pc, #12]	; (d7ac <z_arm_configure_static_mpu_regions+0x10>)
    d7a0:	4803      	ldr	r0, [pc, #12]	; (d7b0 <z_arm_configure_static_mpu_regions+0x14>)
    d7a2:	2101      	movs	r1, #1
    d7a4:	f000 b86e 	b.w	d884 <arm_core_mpu_configure_static_mpu_regions>
    d7a8:	20010000 	.word	0x20010000
    d7ac:	20000000 	.word	0x20000000
    d7b0:	00010b88 	.word	0x00010b88

0000d7b4 <z_arm_configure_dynamic_mpu_regions>:
#endif /* CONFIG_USERSPACE */
	{
		/* A supervisor thread only has the normal thread stack to
		 * protect with a stack guard.
		 */
		guard_start = thread->stack_info.start - guard_size;
    d7b4:	6e42      	ldr	r2, [r0, #100]	; 0x64
	}

	__ASSERT(region_num < _MAX_DYNAMIC_MPU_REGIONS_NUM,
		"Out-of-bounds error for dynamic region map.");

	dynamic_regions[region_num].start = guard_start;
    d7b6:	4b05      	ldr	r3, [pc, #20]	; (d7cc <z_arm_configure_dynamic_mpu_regions+0x18>)
		guard_start = thread->stack_info.start - guard_size;
    d7b8:	3a20      	subs	r2, #32
	dynamic_regions[region_num].start = guard_start;
    d7ba:	601a      	str	r2, [r3, #0]
	dynamic_regions[region_num].size = guard_size;
	dynamic_regions[region_num].attr = K_MEM_PARTITION_P_RO_U_NA;
    d7bc:	4a04      	ldr	r2, [pc, #16]	; (d7d0 <z_arm_configure_dynamic_mpu_regions+0x1c>)
    d7be:	2120      	movs	r1, #32
    d7c0:	e9c3 1201 	strd	r1, r2, [r3, #4]

	region_num++;
#endif /* CONFIG_MPU_STACK_GUARD */

	/* Configure the dynamic MPU regions */
	arm_core_mpu_configure_dynamic_mpu_regions(dynamic_regions,
    d7c4:	4618      	mov	r0, r3
    d7c6:	2101      	movs	r1, #1
    d7c8:	f000 b866 	b.w	d898 <arm_core_mpu_configure_dynamic_mpu_regions>
    d7cc:	200001f8 	.word	0x200001f8
    d7d0:	150b0000 	.word	0x150b0000

0000d7d4 <mpu_configure_regions>:
 * sanity check of the memory regions to be programmed.
 */
static int mpu_configure_regions(const struct z_arm_mpu_partition
	regions[], uint8_t regions_num, uint8_t start_reg_index,
	bool do_sanity_check)
{
    d7d4:	b5f0      	push	{r4, r5, r6, r7, lr}
#endif /* CPU_CORTEX_M0PLUS | CPU_CORTEX_M3 | CPU_CORTEX_M4 */
}

static inline void set_region_number(uint32_t index)
{
	MPU->RNR = index;
    d7d6:	4f1f      	ldr	r7, [pc, #124]	; (d854 <mpu_configure_regions+0x80>)
	int i;
	int reg_index = start_reg_index;

	for (i = 0; i < regions_num; i++) {
    d7d8:	2600      	movs	r6, #0
    d7da:	428e      	cmp	r6, r1
    d7dc:	db01      	blt.n	d7e2 <mpu_configure_regions+0xe>
		/* Increment number of programmed MPU indices. */
		reg_index++;
	}

	return reg_index;
}
    d7de:	4610      	mov	r0, r2
    d7e0:	bdf0      	pop	{r4, r5, r6, r7, pc}
		if (regions[i].size == 0U) {
    d7e2:	6844      	ldr	r4, [r0, #4]
    d7e4:	b39c      	cbz	r4, d84e <mpu_configure_regions+0x7a>
		if (do_sanity_check &&
    d7e6:	b153      	cbz	r3, d7fe <mpu_configure_regions+0x2a>
	 * and greater or equal to the minimum
	 * MPU region size. Start address of the
	 * partition must align with size.
	 */
	int partition_is_valid =
		((part->size & (part->size - 1U)) == 0U)
    d7e8:	f104 3cff 	add.w	ip, r4, #4294967295
		&&
		(part->size >= CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)
		&&
    d7ec:	ea14 0f0c 	tst.w	r4, ip
    d7f0:	d118      	bne.n	d824 <mpu_configure_regions+0x50>
		&&
    d7f2:	2c1f      	cmp	r4, #31
    d7f4:	d916      	bls.n	d824 <mpu_configure_regions+0x50>
		((part->start & (part->size - 1U)) == 0U);
    d7f6:	6805      	ldr	r5, [r0, #0]
		&&
    d7f8:	ea1c 0f05 	tst.w	ip, r5
    d7fc:	d112      	bne.n	d824 <mpu_configure_regions+0x50>
 * to that power-of-two value.
 */
static inline uint32_t size_to_mpu_rasr_size(uint32_t size)
{
	/* The minimal supported region size is 32 bytes */
	if (size <= 32U) {
    d7fe:	2c20      	cmp	r4, #32
	region_conf.base = new_region->start;
    d800:	6805      	ldr	r5, [r0, #0]
#if defined(CONFIG_CPU_AARCH32_CORTEX_R)
	(void) size;

	p_attr->rasr = attr->rasr_attr;
#else
	p_attr->rasr = attr->rasr_attr | size_to_mpu_rasr_size(size);
    d802:	f8d0 c008 	ldr.w	ip, [r0, #8]
		reg_index = mpu_configure_region(reg_index, &regions[i]);
    d806:	b2d2      	uxtb	r2, r2
	if (size <= 32U) {
    d808:	d90f      	bls.n	d82a <mpu_configure_regions+0x56>
	if (size > (1UL << 31)) {
    d80a:	f1b4 4f00 	cmp.w	r4, #2147483648	; 0x80000000
    d80e:	d80e      	bhi.n	d82e <mpu_configure_regions+0x5a>
	return ((32 - __builtin_clz(size - 1U) - 2 + 1) << MPU_RASR_SIZE_Pos) &
    d810:	3c01      	subs	r4, #1
    d812:	fab4 f484 	clz	r4, r4
    d816:	f1c4 041f 	rsb	r4, r4, #31
    d81a:	0064      	lsls	r4, r4, #1
	if (index > (get_num_regions() - 1U)) {
    d81c:	2a07      	cmp	r2, #7
	p_attr->rasr = attr->rasr_attr | size_to_mpu_rasr_size(size);
    d81e:	ea4c 0404 	orr.w	r4, ip, r4
    d822:	d906      	bls.n	d832 <mpu_configure_regions+0x5e>
			return -EINVAL;
    d824:	f06f 0215 	mvn.w	r2, #21
    d828:	e7d9      	b.n	d7de <mpu_configure_regions+0xa>
		return REGION_32B;
    d82a:	2408      	movs	r4, #8
    d82c:	e7f6      	b.n	d81c <mpu_configure_regions+0x48>
		return REGION_4G;
    d82e:	243e      	movs	r4, #62	; 0x3e
    d830:	e7f4      	b.n	d81c <mpu_configure_regions+0x48>
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    d832:	f025 051f 	bic.w	r5, r5, #31
				| MPU_RBAR_VALID_Msk | index;
    d836:	4315      	orrs	r5, r2
    d838:	f045 0510 	orr.w	r5, r5, #16
	MPU->RASR = region_conf->attr.rasr | MPU_RASR_ENABLE_Msk;
    d83c:	f044 0401 	orr.w	r4, r4, #1
    d840:	f8c7 2098 	str.w	r2, [r7, #152]	; 0x98
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    d844:	f8c7 509c 	str.w	r5, [r7, #156]	; 0x9c
		reg_index++;
    d848:	3201      	adds	r2, #1
	MPU->RASR = region_conf->attr.rasr | MPU_RASR_ENABLE_Msk;
    d84a:	f8c7 40a0 	str.w	r4, [r7, #160]	; 0xa0
	for (i = 0; i < regions_num; i++) {
    d84e:	3601      	adds	r6, #1
    d850:	300c      	adds	r0, #12
    d852:	e7c2      	b.n	d7da <mpu_configure_regions+0x6>
    d854:	e000ed00 	.word	0xe000ed00

0000d858 <arm_core_mpu_enable>:
void arm_core_mpu_enable(void)
{
	/* Enable MPU and use the default memory map as a
	 * background region for privileged software access.
	 */
	MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
    d858:	4b04      	ldr	r3, [pc, #16]	; (d86c <arm_core_mpu_enable+0x14>)
    d85a:	2205      	movs	r2, #5
    d85c:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
  __ASM volatile ("dsb 0xF":::"memory");
    d860:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("isb 0xF":::"memory");
    d864:	f3bf 8f6f 	isb	sy

	/* Make sure that all the registers are set before proceeding */
	__DSB();
	__ISB();
}
    d868:	4770      	bx	lr
    d86a:	bf00      	nop
    d86c:	e000ed00 	.word	0xe000ed00

0000d870 <arm_core_mpu_disable>:
  __ASM volatile ("dmb 0xF":::"memory");
    d870:	f3bf 8f5f 	dmb	sy
{
	/* Force any outstanding transfers to complete before disabling MPU */
	__DMB();

	/* Disable MPU */
	MPU->CTRL = 0;
    d874:	4b02      	ldr	r3, [pc, #8]	; (d880 <arm_core_mpu_disable+0x10>)
    d876:	2200      	movs	r2, #0
    d878:	f8c3 2094 	str.w	r2, [r3, #148]	; 0x94
}
    d87c:	4770      	bx	lr
    d87e:	bf00      	nop
    d880:	e000ed00 	.word	0xe000ed00

0000d884 <arm_core_mpu_configure_static_mpu_regions>:
 * @brief configure fixed (static) MPU regions.
 */
void arm_core_mpu_configure_static_mpu_regions(const struct z_arm_mpu_partition
	static_regions[], const uint8_t regions_num,
	const uint32_t background_area_start, const uint32_t background_area_end)
{
    d884:	b510      	push	{r4, lr}
static int mpu_configure_static_mpu_regions(const struct z_arm_mpu_partition
	static_regions[], const uint8_t regions_num,
	const uint32_t background_area_base,
	const uint32_t background_area_end)
{
	int mpu_reg_index = static_regions_num;
    d886:	4c03      	ldr	r4, [pc, #12]	; (d894 <arm_core_mpu_configure_static_mpu_regions+0x10>)
	 * programmed on top of SRAM region configuration.
	 */
	ARG_UNUSED(background_area_base);
	ARG_UNUSED(background_area_end);

	mpu_reg_index = mpu_configure_regions(static_regions,
    d888:	2301      	movs	r3, #1
    d88a:	7822      	ldrb	r2, [r4, #0]
    d88c:	f7ff ffa2 	bl	d7d4 <mpu_configure_regions>
		regions_num, mpu_reg_index, true);

	static_regions_num = mpu_reg_index;
    d890:	7020      	strb	r0, [r4, #0]
					       background_area_start, background_area_end) == -EINVAL) {

		__ASSERT(0, "Configuring %u static MPU regions failed\n",
			regions_num);
	}
}
    d892:	bd10      	pop	{r4, pc}
    d894:	20000370 	.word	0x20000370

0000d898 <arm_core_mpu_configure_dynamic_mpu_regions>:
/**
 * @brief configure dynamic MPU regions.
 */
void arm_core_mpu_configure_dynamic_mpu_regions(const struct z_arm_mpu_partition
	dynamic_regions[], uint8_t regions_num)
{
    d898:	b508      	push	{r3, lr}

	/* In ARMv7-M architecture the dynamic regions are
	 * programmed on top of existing SRAM region configuration.
	 */

	mpu_reg_index = mpu_configure_regions(dynamic_regions,
    d89a:	4a09      	ldr	r2, [pc, #36]	; (d8c0 <arm_core_mpu_configure_dynamic_mpu_regions+0x28>)
    d89c:	2300      	movs	r3, #0
    d89e:	7812      	ldrb	r2, [r2, #0]
    d8a0:	f7ff ff98 	bl	d7d4 <mpu_configure_regions>
		regions_num, mpu_reg_index, false);

	if (mpu_reg_index != -EINVAL) {
    d8a4:	f110 0f16 	cmn.w	r0, #22
    d8a8:	d002      	beq.n	d8b0 <arm_core_mpu_configure_dynamic_mpu_regions+0x18>
  MPU->RNR = rnr;
    d8aa:	4a06      	ldr	r2, [pc, #24]	; (d8c4 <arm_core_mpu_configure_dynamic_mpu_regions+0x2c>)

		/* Disable the non-programmed MPU regions. */
		for (int i = mpu_reg_index; i < get_num_regions(); i++) {
    d8ac:	2807      	cmp	r0, #7
    d8ae:	dd00      	ble.n	d8b2 <arm_core_mpu_configure_dynamic_mpu_regions+0x1a>
		== -EINVAL) {

		__ASSERT(0, "Configuring %u dynamic MPU regions failed\n",
			regions_num);
	}
}
    d8b0:	bd08      	pop	{r3, pc}
    d8b2:	f8c2 0098 	str.w	r0, [r2, #152]	; 0x98
  MPU->RASR = 0U;
    d8b6:	f8c2 30a0 	str.w	r3, [r2, #160]	; 0xa0
    d8ba:	3001      	adds	r0, #1
    d8bc:	e7f6      	b.n	d8ac <arm_core_mpu_configure_dynamic_mpu_regions+0x14>
    d8be:	bf00      	nop
    d8c0:	20000370 	.word	0x20000370
    d8c4:	e000ed00 	.word	0xe000ed00

0000d8c8 <z_arm_mpu_init>:
 */
int z_arm_mpu_init(void)
{
	uint32_t r_index;

	if (mpu_config.num_regions > get_num_regions()) {
    d8c8:	4914      	ldr	r1, [pc, #80]	; (d91c <z_arm_mpu_init+0x54>)
    d8ca:	6808      	ldr	r0, [r1, #0]
    d8cc:	2808      	cmp	r0, #8
{
    d8ce:	b510      	push	{r4, lr}
	if (mpu_config.num_regions > get_num_regions()) {
    d8d0:	d821      	bhi.n	d916 <z_arm_mpu_init+0x4e>
		return -1;
	}

	LOG_DBG("total region count: %d", get_num_regions());

	arm_core_mpu_disable();
    d8d2:	f7ff ffcd 	bl	d870 <arm_core_mpu_disable>
    d8d6:	4c12      	ldr	r4, [pc, #72]	; (d920 <z_arm_mpu_init+0x58>)
    d8d8:	6849      	ldr	r1, [r1, #4]

	/* Architecture-specific configuration */
	mpu_init();

	/* Program fixed regions configured at SOC definition. */
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    d8da:	2200      	movs	r2, #0
    d8dc:	4290      	cmp	r0, r2
    d8de:	f101 010c 	add.w	r1, r1, #12
    d8e2:	d105      	bne.n	d8f0 <z_arm_mpu_init+0x28>
		region_init(r_index, &mpu_config.mpu_regions[r_index]);
	}

	/* Update the number of programmed MPU regions. */
	static_regions_num = mpu_config.num_regions;
    d8e4:	4b0f      	ldr	r3, [pc, #60]	; (d924 <z_arm_mpu_init+0x5c>)
    d8e6:	7018      	strb	r0, [r3, #0]


	arm_core_mpu_enable();
    d8e8:	f7ff ffb6 	bl	d858 <arm_core_mpu_enable>
		(MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos ==
		NUM_MPU_REGIONS,
		"Invalid number of MPU regions\n");
#endif /* CORTEX_M0PLUS || CPU_CORTEX_M3 || CPU_CORTEX_M4 */

	return 0;
    d8ec:	2000      	movs	r0, #0
}
    d8ee:	bd10      	pop	{r4, pc}
    d8f0:	f8c4 2098 	str.w	r2, [r4, #152]	; 0x98
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    d8f4:	f851 3c0c 	ldr.w	r3, [r1, #-12]
    d8f8:	f023 031f 	bic.w	r3, r3, #31
				| MPU_RBAR_VALID_Msk | index;
    d8fc:	4313      	orrs	r3, r2
    d8fe:	f043 0310 	orr.w	r3, r3, #16
	MPU->RBAR = (region_conf->base & MPU_RBAR_ADDR_Msk)
    d902:	f8c4 309c 	str.w	r3, [r4, #156]	; 0x9c
	MPU->RASR = region_conf->attr.rasr | MPU_RASR_ENABLE_Msk;
    d906:	f851 3c04 	ldr.w	r3, [r1, #-4]
    d90a:	f043 0301 	orr.w	r3, r3, #1
    d90e:	f8c4 30a0 	str.w	r3, [r4, #160]	; 0xa0
	for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) {
    d912:	3201      	adds	r2, #1
    d914:	e7e2      	b.n	d8dc <z_arm_mpu_init+0x14>
		return -1;
    d916:	f04f 30ff 	mov.w	r0, #4294967295
    d91a:	e7e8      	b.n	d8ee <z_arm_mpu_init+0x26>
    d91c:	00010b94 	.word	0x00010b94
    d920:	e000ed00 	.word	0xe000ed00
    d924:	20000370 	.word	0x20000370

0000d928 <__stdout_hook_install>:

static int (*_stdout_hook)(int) = _stdout_hook_default;

void __stdout_hook_install(int (*hook)(int))
{
	_stdout_hook = hook;
    d928:	4b01      	ldr	r3, [pc, #4]	; (d930 <__stdout_hook_install+0x8>)
    d92a:	6018      	str	r0, [r3, #0]
}
    d92c:	4770      	bx	lr
    d92e:	bf00      	nop
    d930:	20000008 	.word	0x20000008

0000d934 <nordicsemi_nrf52_init>:
	__asm__ volatile(
    d934:	f04f 0320 	mov.w	r3, #32
    d938:	f3ef 8211 	mrs	r2, BASEPRI
    d93c:	f383 8812 	msr	BASEPRI_MAX, r3
    d940:	f3bf 8f6f 	isb	sy

	key = irq_lock();

#ifdef CONFIG_NRF_ENABLE_ICACHE
	/* Enable the instruction cache */
	NRF_NVMC->ICACHECNF = NVMC_ICACHECNF_CACHEEN_Msk;
    d944:	4906      	ldr	r1, [pc, #24]	; (d960 <nordicsemi_nrf52_init+0x2c>)
    d946:	2301      	movs	r3, #1
    d948:	f8c1 3540 	str.w	r3, [r1, #1344]	; 0x540
#endif

#if NRF_POWER_HAS_DCDCEN
NRF_STATIC_INLINE void nrf_power_dcdcen_set(NRF_POWER_Type * p_reg, bool enable)
{
    p_reg->DCDCEN = (enable ? POWER_DCDCEN_DCDCEN_Enabled : POWER_DCDCEN_DCDCEN_Disabled) <<
    d94c:	f04f 4180 	mov.w	r1, #1073741824	; 0x40000000
    d950:	f8c1 3578 	str.w	r3, [r1, #1400]	; 0x578
	__asm__ volatile(
    d954:	f382 8811 	msr	BASEPRI, r2
    d958:	f3bf 8f6f 	isb	sy
	NMI_INIT();

	irq_unlock(key);

	return 0;
}
    d95c:	2000      	movs	r0, #0
    d95e:	4770      	bx	lr
    d960:	4001e000 	.word	0x4001e000

0000d964 <sys_arch_reboot>:
    *p_gpregret = val;
    d964:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    d968:	b2c0      	uxtb	r0, r0
    d96a:	f8c3 051c 	str.w	r0, [r3, #1308]	; 0x51c
  __ASM volatile ("dsb 0xF":::"memory");
    d96e:	f3bf 8f4f 	dsb	sy
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
  __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                       buffered write are completed before reset */
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    d972:	4905      	ldr	r1, [pc, #20]	; (d988 <sys_arch_reboot+0x24>)
    d974:	4b05      	ldr	r3, [pc, #20]	; (d98c <sys_arch_reboot+0x28>)
    d976:	68ca      	ldr	r2, [r1, #12]
    d978:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    d97c:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    d97e:	60cb      	str	r3, [r1, #12]
    d980:	f3bf 8f4f 	dsb	sy
                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
  __DSB();                                                          /* Ensure completion of memory access */

  for(;;)                                                           /* wait until reset */
  {
    __NOP();
    d984:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    d986:	e7fd      	b.n	d984 <sys_arch_reboot+0x20>
    d988:	e000ed00 	.word	0xe000ed00
    d98c:	05fa0004 	.word	0x05fa0004

0000d990 <arch_busy_wait>:

#else // NRFX_CHECK(NRFX_DELAY_DWT_BASED)

NRF_STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us)
{
    if (time_us == 0)
    d990:	b120      	cbz	r0, d99c <arch_busy_wait+0xc>
    };

    typedef void (* delay_func_t)(uint32_t);
    const delay_func_t delay_cycles =
        // Set LSB to 1 to execute the code in the Thumb mode.
        (delay_func_t)((((uint32_t)delay_machine_code) | 1));
    d992:	4b03      	ldr	r3, [pc, #12]	; (d9a0 <arch_busy_wait+0x10>)
    uint32_t cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ;
    delay_cycles(cycles);
    d994:	0180      	lsls	r0, r0, #6
    d996:	f043 0301 	orr.w	r3, r3, #1
    d99a:	4718      	bx	r3

void arch_busy_wait(uint32_t time_us)
{
	nrfx_coredep_delay_us(time_us);
}
    d99c:	4770      	bx	lr
    d99e:	bf00      	nop
    d9a0:	00010b80 	.word	0x00010b80

0000d9a4 <onoff_stop>:
}

static clock_control_subsys_t get_subsys(struct onoff_manager *mgr)
{
	struct nrf_clock_control_data *data = CLOCK_DEVICE->data;
	size_t offset = (size_t)(mgr - data->mgr);
    d9a4:	4b08      	ldr	r3, [pc, #32]	; (d9c8 <onoff_stop+0x24>)
	return (clock_control_subsys_t)offset;
}

static void onoff_stop(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    d9a6:	b570      	push	{r4, r5, r6, lr}
	size_t offset = (size_t)(mgr - data->mgr);
    d9a8:	1ac3      	subs	r3, r0, r3
{
    d9aa:	460d      	mov	r5, r1
	int res;

	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
    d9ac:	4907      	ldr	r1, [pc, #28]	; (d9cc <onoff_stop+0x28>)
	size_t offset = (size_t)(mgr - data->mgr);
    d9ae:	109b      	asrs	r3, r3, #2
{
    d9b0:	4604      	mov	r4, r0
	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
    d9b2:	4359      	muls	r1, r3
    d9b4:	4806      	ldr	r0, [pc, #24]	; (d9d0 <onoff_stop+0x2c>)
    d9b6:	2240      	movs	r2, #64	; 0x40
    d9b8:	f002 fc9b 	bl	102f2 <stop>
	notify(mgr, res);
    d9bc:	462b      	mov	r3, r5
	res = stop(CLOCK_DEVICE, get_subsys(mgr), CTX_ONOFF);
    d9be:	4601      	mov	r1, r0
	notify(mgr, res);
    d9c0:	4620      	mov	r0, r4
}
    d9c2:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	notify(mgr, res);
    d9c6:	4718      	bx	r3
    d9c8:	20000214 	.word	0x20000214
    d9cc:	b6db6db7 	.word	0xb6db6db7
    d9d0:	000109e8 	.word	0x000109e8

0000d9d4 <onoff_start>:
	notify(mgr, 0);
}

static void onoff_start(struct onoff_manager *mgr,
			onoff_notify_fn notify)
{
    d9d4:	b573      	push	{r0, r1, r4, r5, r6, lr}
	size_t offset = (size_t)(mgr - data->mgr);
    d9d6:	4c0c      	ldr	r4, [pc, #48]	; (da08 <onoff_start+0x34>)
	int err;

	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    d9d8:	4a0c      	ldr	r2, [pc, #48]	; (da0c <onoff_start+0x38>)
    d9da:	2340      	movs	r3, #64	; 0x40
	size_t offset = (size_t)(mgr - data->mgr);
    d9dc:	1b04      	subs	r4, r0, r4
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    d9de:	9300      	str	r3, [sp, #0]
{
    d9e0:	460d      	mov	r5, r1
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    d9e2:	460b      	mov	r3, r1
    d9e4:	490a      	ldr	r1, [pc, #40]	; (da10 <onoff_start+0x3c>)
	size_t offset = (size_t)(mgr - data->mgr);
    d9e6:	10a4      	asrs	r4, r4, #2
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    d9e8:	4361      	muls	r1, r4
{
    d9ea:	4606      	mov	r6, r0
	err = async_start(CLOCK_DEVICE, get_subsys(mgr),
    d9ec:	4809      	ldr	r0, [pc, #36]	; (da14 <onoff_start+0x40>)
    d9ee:	f002 fcac 	bl	1034a <async_start>
			  onoff_started_callback, notify, CTX_ONOFF);
	if (err < 0) {
    d9f2:	1e01      	subs	r1, r0, #0
    d9f4:	da05      	bge.n	da02 <onoff_start+0x2e>
		notify(mgr, err);
    d9f6:	4630      	mov	r0, r6
    d9f8:	462b      	mov	r3, r5
	}
}
    d9fa:	b002      	add	sp, #8
    d9fc:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		notify(mgr, err);
    da00:	4718      	bx	r3
}
    da02:	b002      	add	sp, #8
    da04:	bd70      	pop	{r4, r5, r6, pc}
    da06:	bf00      	nop
    da08:	20000214 	.word	0x20000214
    da0c:	000103bb 	.word	0x000103bb
    da10:	b6db6db7 	.word	0xb6db6db7
    da14:	000109e8 	.word	0x000109e8

0000da18 <clk_init>:
	static const struct onoff_transitions transitions = {
		.start = onoff_start,
		.stop = onoff_stop
	};

	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    da18:	2200      	movs	r2, #0
{
    da1a:	b570      	push	{r4, r5, r6, lr}
	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    da1c:	2101      	movs	r1, #1
{
    da1e:	4604      	mov	r4, r0
	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
    da20:	4610      	mov	r0, r2
    da22:	f7ff fc29 	bl	d278 <z_arm_irq_priority_set>
		    nrfx_isr, nrfx_power_clock_irq_handler, 0);

	nrfx_err = nrfx_clock_init(clock_event_handler);
    da26:	480f      	ldr	r0, [pc, #60]	; (da64 <clk_init+0x4c>)
    da28:	f001 f882 	bl	eb30 <nrfx_clock_init>
	if (nrfx_err != NRFX_SUCCESS) {
    da2c:	4b0e      	ldr	r3, [pc, #56]	; (da68 <clk_init+0x50>)
    da2e:	4298      	cmp	r0, r3
    da30:	d115      	bne.n	da5e <clk_init+0x46>
		struct nrf_clock_control_data *data = dev->data;

		z_nrf_clock_calibration_init(data->mgr);
	}

	nrfx_clock_enable();
    da32:	f002 fe71 	bl	10718 <nrfx_clock_enable>
	struct nrf_clock_control_data *data = dev->data;
    da36:	6926      	ldr	r6, [r4, #16]
	for (enum clock_control_nrf_type i = 0;
		i < CLOCK_CONTROL_NRF_TYPE_COUNT; i++) {
		struct nrf_clock_control_sub_data *subdata =
						get_sub_data(dev, i);

		err = onoff_manager_init(get_onoff_manager(dev, i),
    da38:	490c      	ldr	r1, [pc, #48]	; (da6c <clk_init+0x54>)
    da3a:	4630      	mov	r0, r6
    da3c:	f002 fb26 	bl	1008c <onoff_manager_init>
					 &transitions);
		if (err < 0) {
    da40:	2800      	cmp	r0, #0
    da42:	db0b      	blt.n	da5c <clk_init+0x44>
	struct nrf_clock_control_data *data = dev->data;
    da44:	6924      	ldr	r4, [r4, #16]
		err = onoff_manager_init(get_onoff_manager(dev, i),
    da46:	4909      	ldr	r1, [pc, #36]	; (da6c <clk_init+0x54>)
			return err;
		}

		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    da48:	2501      	movs	r5, #1
    da4a:	6435      	str	r5, [r6, #64]	; 0x40
		err = onoff_manager_init(get_onoff_manager(dev, i),
    da4c:	f104 001c 	add.w	r0, r4, #28
    da50:	f002 fb1c 	bl	1008c <onoff_manager_init>
		if (err < 0) {
    da54:	2800      	cmp	r0, #0
    da56:	db01      	blt.n	da5c <clk_init+0x44>
		subdata->flags = CLOCK_CONTROL_STATUS_OFF;
    da58:	64e5      	str	r5, [r4, #76]	; 0x4c
	}

	return 0;
    da5a:	2000      	movs	r0, #0
}
    da5c:	bd70      	pop	{r4, r5, r6, pc}
		return -EIO;
    da5e:	f06f 0004 	mvn.w	r0, #4
    da62:	e7fb      	b.n	da5c <clk_init+0x44>
    da64:	0000daa5 	.word	0x0000daa5
    da68:	0bad0000 	.word	0x0bad0000
    da6c:	00010bdc 	.word	0x00010bdc

0000da70 <clkstarted_handle.constprop.0>:
static void clkstarted_handle(const struct device *dev,
    da70:	4601      	mov	r1, r0
	clock_control_cb_t callback = sub_data->cb;
    da72:	230c      	movs	r3, #12
    da74:	4809      	ldr	r0, [pc, #36]	; (da9c <clkstarted_handle.constprop.0+0x2c>)
    da76:	434b      	muls	r3, r1
static void clkstarted_handle(const struct device *dev,
    da78:	b570      	push	{r4, r5, r6, lr}
	clock_control_cb_t callback = sub_data->cb;
    da7a:	18c4      	adds	r4, r0, r3
	void *user_data = sub_data->user_data;
    da7c:	e9d4 560e 	ldrd	r5, r6, [r4, #56]	; 0x38
	sub_data->cb = NULL;
    da80:	2200      	movs	r2, #0
	set_on_state(&sub_data->flags);
    da82:	3340      	adds	r3, #64	; 0x40
	sub_data->cb = NULL;
    da84:	63a2      	str	r2, [r4, #56]	; 0x38
	set_on_state(&sub_data->flags);
    da86:	4418      	add	r0, r3
    da88:	f002 fc20 	bl	102cc <set_on_state>
	if (callback) {
    da8c:	b12d      	cbz	r5, da9a <clkstarted_handle.constprop.0+0x2a>
		callback(dev, (clock_control_subsys_t)type, user_data);
    da8e:	4632      	mov	r2, r6
    da90:	462b      	mov	r3, r5
    da92:	4803      	ldr	r0, [pc, #12]	; (daa0 <clkstarted_handle.constprop.0+0x30>)
}
    da94:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		callback(dev, (clock_control_subsys_t)type, user_data);
    da98:	4718      	bx	r3
}
    da9a:	bd70      	pop	{r4, r5, r6, pc}
    da9c:	20000214 	.word	0x20000214
    daa0:	000109e8 	.word	0x000109e8

0000daa4 <clock_event_handler>:
	switch (event) {
    daa4:	b110      	cbz	r0, daac <clock_event_handler+0x8>
    daa6:	2801      	cmp	r0, #1
    daa8:	d004      	beq.n	dab4 <clock_event_handler+0x10>
    daaa:	4770      	bx	lr
		if (GET_STATUS(data->flags) == CLOCK_CONTROL_STATUS_STARTING) {
    daac:	4b03      	ldr	r3, [pc, #12]	; (dabc <clock_event_handler+0x18>)
    daae:	6c1b      	ldr	r3, [r3, #64]	; 0x40
    dab0:	075b      	lsls	r3, r3, #29
    dab2:	d101      	bne.n	dab8 <clock_event_handler+0x14>
		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_LFCLK);
    dab4:	f7ff bfdc 	b.w	da70 <clkstarted_handle.constprop.0>
}
    dab8:	4770      	bx	lr
    daba:	bf00      	nop
    dabc:	20000214 	.word	0x20000214

0000dac0 <generic_hfclk_start>:
{
    dac0:	b508      	push	{r3, lr}
	__asm__ volatile(
    dac2:	f04f 0320 	mov.w	r3, #32
    dac6:	f3ef 8111 	mrs	r1, BASEPRI
    daca:	f383 8812 	msr	BASEPRI_MAX, r3
    dace:	f3bf 8f6f 	isb	sy
	hfclk_users |= HF_USER_GENERIC;
    dad2:	4a12      	ldr	r2, [pc, #72]	; (db1c <generic_hfclk_start+0x5c>)
    dad4:	6813      	ldr	r3, [r2, #0]
    dad6:	f043 0002 	orr.w	r0, r3, #2
	if (hfclk_users & HF_USER_BT) {
    dada:	f013 0301 	ands.w	r3, r3, #1
	hfclk_users |= HF_USER_GENERIC;
    dade:	6010      	str	r0, [r2, #0]
	if (hfclk_users & HF_USER_BT) {
    dae0:	d00c      	beq.n	dafc <generic_hfclk_start+0x3c>
            break;
        case NRF_CLOCK_DOMAIN_HFCLK:
            if (p_clk_src != NULL)
            {
                (*(nrf_clock_hfclk_t *)p_clk_src) =
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    dae2:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    dae6:	f8d2 340c 	ldr.w	r3, [r2, #1036]	; 0x40c
                                        >> CLOCK_HFCLKSTAT_SRC_Pos);
            }
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    daea:	f8d2 240c 	ldr.w	r2, [r2, #1036]	; 0x40c
		if (type == NRF_CLOCK_HFCLK_HIGH_ACCURACY) {
    daee:	f013 0301 	ands.w	r3, r3, #1
    daf2:	d003      	beq.n	dafc <generic_hfclk_start+0x3c>
			set_on_state(get_hf_flags());
    daf4:	480a      	ldr	r0, [pc, #40]	; (db20 <generic_hfclk_start+0x60>)
    daf6:	f002 fbe9 	bl	102cc <set_on_state>
			already_started = true;
    dafa:	2301      	movs	r3, #1
	__asm__ volatile(
    dafc:	f381 8811 	msr	BASEPRI, r1
    db00:	f3bf 8f6f 	isb	sy
	if (already_started) {
    db04:	b123      	cbz	r3, db10 <generic_hfclk_start+0x50>
}
    db06:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
		clkstarted_handle(CLOCK_DEVICE,
    db0a:	2000      	movs	r0, #0
    db0c:	f7ff bfb0 	b.w	da70 <clkstarted_handle.constprop.0>
}
    db10:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_start(void)
{
    nrfx_clock_start(NRF_CLOCK_DOMAIN_HFCLK);
    db14:	2001      	movs	r0, #1
    db16:	f001 b81b 	b.w	eb50 <nrfx_clock_start>
    db1a:	bf00      	nop
    db1c:	20000264 	.word	0x20000264
    db20:	20000254 	.word	0x20000254

0000db24 <api_blocking_start>:
{
    db24:	b51f      	push	{r0, r1, r2, r3, r4, lr}
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    db26:	2200      	movs	r2, #0
    db28:	2301      	movs	r3, #1
    db2a:	e9cd 2302 	strd	r2, r3, [sp, #8]
	err = api_start(dev, subsys, blocking_start_callback, &sem);
    db2e:	4a09      	ldr	r2, [pc, #36]	; (db54 <api_blocking_start+0x30>)
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    db30:	f8cd d000 	str.w	sp, [sp]
	err = api_start(dev, subsys, blocking_start_callback, &sem);
    db34:	466b      	mov	r3, sp
	struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
    db36:	f8cd d004 	str.w	sp, [sp, #4]
	err = api_start(dev, subsys, blocking_start_callback, &sem);
    db3a:	f002 fc37 	bl	103ac <api_start>
	if (err < 0) {
    db3e:	2800      	cmp	r0, #0
    db40:	db05      	blt.n	db4e <api_blocking_start+0x2a>
		union { struct { uintptr_t lo, hi; } split; k_timeout_t val; } parm1 = { .val = timeout };
		return (int) arch_syscall_invoke3(parm0.x, parm1.split.lo, parm1.split.hi, K_SYSCALL_K_SEM_TAKE);
	}
#endif
	compiler_barrier();
	return z_impl_k_sem_take(sem, timeout);
    db42:	f44f 4280 	mov.w	r2, #16384	; 0x4000
    db46:	2300      	movs	r3, #0
    db48:	4668      	mov	r0, sp
    db4a:	f001 fd9b 	bl	f684 <z_impl_k_sem_take>
}
    db4e:	b005      	add	sp, #20
    db50:	f85d fb04 	ldr.w	pc, [sp], #4
    db54:	000103d3 	.word	0x000103d3

0000db58 <lfclk_start>:
{
    db58:	b510      	push	{r4, lr}
	if (!once) {
    db5a:	4c07      	ldr	r4, [pc, #28]	; (db78 <lfclk_start+0x20>)
    db5c:	7823      	ldrb	r3, [r4, #0]
    db5e:	b92b      	cbnz	r3, db6c <lfclk_start+0x14>
	z_impl_k_busy_wait(usec_to_wait);
    db60:	f44f 70a5 	mov.w	r0, #330	; 0x14a
    db64:	f002 ff19 	bl	1099a <z_impl_k_busy_wait>
		once = true;
    db68:	2301      	movs	r3, #1
    db6a:	7023      	strb	r3, [r4, #0]
}
    db6c:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    nrfx_clock_start(NRF_CLOCK_DOMAIN_LFCLK);
    db70:	2000      	movs	r0, #0
    db72:	f000 bfed 	b.w	eb50 <nrfx_clock_start>
    db76:	bf00      	nop
    db78:	20000371 	.word	0x20000371

0000db7c <generic_hfclk_stop>:
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    db7c:	4b09      	ldr	r3, [pc, #36]	; (dba4 <generic_hfclk_stop+0x28>)
    db7e:	f3bf 8f5b 	dmb	ish
    db82:	e853 2f00 	ldrex	r2, [r3]
    db86:	f022 0102 	bic.w	r1, r2, #2
    db8a:	e843 1000 	strex	r0, r1, [r3]
    db8e:	2800      	cmp	r0, #0
    db90:	d1f7      	bne.n	db82 <generic_hfclk_stop+0x6>
    db92:	f3bf 8f5b 	dmb	ish
	if (atomic_and(&hfclk_users, ~HF_USER_GENERIC) & HF_USER_BT) {
    db96:	07d3      	lsls	r3, r2, #31
    db98:	d402      	bmi.n	dba0 <generic_hfclk_stop+0x24>
}

NRFX_STATIC_INLINE void nrfx_clock_hfclk_stop(void)
{
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLK);
    db9a:	2001      	movs	r0, #1
    db9c:	f002 bdc9 	b.w	10732 <nrfx_clock_stop>
}
    dba0:	4770      	bx	lr
    dba2:	bf00      	nop
    dba4:	20000264 	.word	0x20000264

0000dba8 <z_nrf_clock_control_lf_on>:
{
    dba8:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
	return __atomic_exchange_n(target, value, __ATOMIC_SEQ_CST);
    dbac:	4939      	ldr	r1, [pc, #228]	; (dc94 <z_nrf_clock_control_lf_on+0xec>)
    dbae:	f3bf 8f5b 	dmb	ish
    dbb2:	4607      	mov	r7, r0
    dbb4:	2201      	movs	r2, #1
    dbb6:	e851 3f00 	ldrex	r3, [r1]
    dbba:	e841 2000 	strex	r0, r2, [r1]
    dbbe:	2800      	cmp	r0, #0
    dbc0:	d1f9      	bne.n	dbb6 <z_nrf_clock_control_lf_on+0xe>
    dbc2:	f3bf 8f5b 	dmb	ish
	if (atomic_set(&on, 1) == 0) {
    dbc6:	b933      	cbnz	r3, dbd6 <z_nrf_clock_control_lf_on+0x2e>
 */
static inline void sys_notify_init_spinwait(struct sys_notify *notify)
{
	__ASSERT_NO_MSG(notify != NULL);

	*notify = (struct sys_notify){
    dbc8:	4933      	ldr	r1, [pc, #204]	; (dc98 <z_nrf_clock_control_lf_on+0xf0>)
		err = onoff_request(mgr, &cli);
    dbca:	4834      	ldr	r0, [pc, #208]	; (dc9c <z_nrf_clock_control_lf_on+0xf4>)
    dbcc:	604b      	str	r3, [r1, #4]
    dbce:	60cb      	str	r3, [r1, #12]
    dbd0:	608a      	str	r2, [r1, #8]
    dbd2:	f002 fa6e 	bl	100b2 <onoff_request>
	switch (start_mode) {
    dbd6:	1e7b      	subs	r3, r7, #1
    dbd8:	2b01      	cmp	r3, #1
    dbda:	d82f      	bhi.n	dc3c <z_nrf_clock_control_lf_on+0x94>
	if ((mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE) &&
    dbdc:	2f01      	cmp	r7, #1
    dbde:	d107      	bne.n	dbf0 <z_nrf_clock_control_lf_on+0x48>
    return clk_src;
}

NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(NRF_CLOCK_Type const * p_reg)
{
    return (nrf_clock_lfclk_t)((p_reg->LFCLKSRCCOPY & CLOCK_LFCLKSRCCOPY_SRC_Msk)
    dbe0:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    dbe4:	f8d3 341c 	ldr.w	r3, [r3, #1052]	; 0x41c
    dbe8:	f003 0303 	and.w	r3, r3, #3
	    (target_type == NRF_CLOCK_LFCLK_Xtal) &&
    dbec:	2b01      	cmp	r3, #1
    dbee:	d025      	beq.n	dc3c <z_nrf_clock_control_lf_on+0x94>
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    dbf0:	f002 fde0 	bl	107b4 <k_is_in_isr>
    dbf4:	4604      	mov	r4, r0
    dbf6:	b918      	cbnz	r0, dc00 <z_nrf_clock_control_lf_on+0x58>
 */
static inline bool k_is_pre_kernel(void)
{
	extern bool z_sys_post_kernel; /* in init.c */

	return !z_sys_post_kernel;
    dbf8:	4b29      	ldr	r3, [pc, #164]	; (dca0 <z_nrf_clock_control_lf_on+0xf8>)
	int key = isr_mode ? irq_lock() : 0;
    dbfa:	781b      	ldrb	r3, [r3, #0]
    dbfc:	2b00      	cmp	r3, #0
    dbfe:	d141      	bne.n	dc84 <z_nrf_clock_control_lf_on+0xdc>
	__asm__ volatile(
    dc00:	f04f 0320 	mov.w	r3, #32
    dc04:	f3ef 8611 	mrs	r6, BASEPRI
    dc08:	f383 8812 	msr	BASEPRI_MAX, r3
    dc0c:	f3bf 8f6f 	isb	sy
    dc10:	2401      	movs	r4, #1
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    dc12:	f8df 8090 	ldr.w	r8, [pc, #144]	; dca4 <z_nrf_clock_control_lf_on+0xfc>
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    dc16:	f04f 4580 	mov.w	r5, #1073741824	; 0x40000000
    dc1a:	f8d5 3418 	ldr.w	r3, [r5, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    dc1e:	f8d5 2418 	ldr.w	r2, [r5, #1048]	; 0x418
    dc22:	03d2      	lsls	r2, r2, #15
    dc24:	d50c      	bpl.n	dc40 <z_nrf_clock_control_lf_on+0x98>
                                        >> CLOCK_LFCLKSTAT_SRC_Pos);
    dc26:	f003 0303 	and.w	r3, r3, #3
	while (!(nrfx_clock_is_running(d, (void *)&type)
    dc2a:	2b01      	cmp	r3, #1
    dc2c:	d001      	beq.n	dc32 <z_nrf_clock_control_lf_on+0x8a>
		     || (mode == CLOCK_CONTROL_NRF_LF_START_AVAILABLE)))) {
    dc2e:	2f01      	cmp	r7, #1
    dc30:	d106      	bne.n	dc40 <z_nrf_clock_control_lf_on+0x98>
	if (isr_mode) {
    dc32:	b30c      	cbz	r4, dc78 <z_nrf_clock_control_lf_on+0xd0>
	__asm__ volatile(
    dc34:	f386 8811 	msr	BASEPRI, r6
    dc38:	f3bf 8f6f 	isb	sy
}
    dc3c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
			if (isr_mode || !IS_ENABLED(CONFIG_MULTITHREADING)) {
    dc40:	b1ac      	cbz	r4, dc6e <z_nrf_clock_control_lf_on+0xc6>
 *
 * @param key Interrupt locking key obtained from irq_lock().
 */
static inline void k_cpu_atomic_idle(unsigned int key)
{
	arch_cpu_atomic_idle(key);
    dc42:	4630      	mov	r0, r6
    dc44:	f7ff faf0 	bl	d228 <arch_cpu_atomic_idle>
    return (nrf_clock_lfclk_t)(p_reg->LFCLKSRC);
    dc48:	f8d5 3518 	ldr.w	r3, [r5, #1304]	; 0x518
		if ((target_type ==  NRF_CLOCK_LFCLK_Xtal)
    dc4c:	2b00      	cmp	r3, #0
    dc4e:	d1e4      	bne.n	dc1a <z_nrf_clock_control_lf_on+0x72>
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    dc50:	f8d5 2104 	ldr.w	r2, [r5, #260]	; 0x104
		    && nrf_clock_event_check(NRF_CLOCK,
    dc54:	2a00      	cmp	r2, #0
    dc56:	d0e0      	beq.n	dc1a <z_nrf_clock_control_lf_on+0x72>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    dc58:	f8c5 3104 	str.w	r3, [r5, #260]	; 0x104
#ifndef NRF_DECLARE_ONLY

NRF_STATIC_INLINE void nrf_event_readback(void * p_event_reg)
{
#if NRFX_CHECK(NRFX_EVENT_READBACK_ENABLED) && !defined(NRF51)
    (void)*((volatile uint32_t *)(p_event_reg));
    dc5c:	f8d5 3104 	ldr.w	r3, [r5, #260]	; 0x104
    p_reg->LFCLKSRC = (uint32_t)(source);
    dc60:	2301      	movs	r3, #1
    dc62:	f8c5 3518 	str.w	r3, [r5, #1304]	; 0x518
    dc66:	f8c8 3180 	str.w	r3, [r8, #384]	; 0x180
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    dc6a:	60ab      	str	r3, [r5, #8]
}
    dc6c:	e7d5      	b.n	dc1a <z_nrf_clock_control_lf_on+0x72>
	return z_impl_k_sleep(timeout);
    dc6e:	2100      	movs	r1, #0
    dc70:	2021      	movs	r0, #33	; 0x21
    dc72:	f001 ffbf 	bl	fbf4 <z_impl_k_sleep>
	return k_sleep(Z_TIMEOUT_MS(ms));
    dc76:	e7e7      	b.n	dc48 <z_nrf_clock_control_lf_on+0xa0>
    p_reg->INTENSET = mask;
    dc78:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    dc7c:	2202      	movs	r2, #2
    dc7e:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
}
    dc82:	e7db      	b.n	dc3c <z_nrf_clock_control_lf_on+0x94>
    p_reg->INTENCLR = mask;
    dc84:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    dc88:	2202      	movs	r2, #2
    dc8a:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
	int key = isr_mode ? irq_lock() : 0;
    dc8e:	4606      	mov	r6, r0
}
    dc90:	e7bf      	b.n	dc12 <z_nrf_clock_control_lf_on+0x6a>
    dc92:	bf00      	nop
    dc94:	20000268 	.word	0x20000268
    dc98:	20000204 	.word	0x20000204
    dc9c:	20000230 	.word	0x20000230
    dca0:	20000782 	.word	0x20000782
    dca4:	e000e100 	.word	0xe000e100

0000dca8 <uart_console_init>:
 * @brief Initialize one UART as the console/debug port
 *
 * @return 0 if successful, otherwise failed.
 */
static int uart_console_init(const struct device *arg)
{
    dca8:	b508      	push	{r3, lr}

	ARG_UNUSED(arg);

	/* Claim console device */
	uart_console_dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_console));
    dcaa:	4b08      	ldr	r3, [pc, #32]	; (dccc <uart_console_init+0x24>)
    dcac:	4808      	ldr	r0, [pc, #32]	; (dcd0 <uart_console_init+0x28>)
    dcae:	6018      	str	r0, [r3, #0]
 */
__syscall bool device_is_ready(const struct device *dev);

static inline bool z_impl_device_is_ready(const struct device *dev)
{
	return z_device_is_ready(dev);
    dcb0:	f002 fd57 	bl	10762 <z_device_is_ready>
	if (!device_is_ready(uart_console_dev)) {
    dcb4:	b138      	cbz	r0, dcc6 <uart_console_init+0x1e>
	__stdout_hook_install(console_out);
    dcb6:	4807      	ldr	r0, [pc, #28]	; (dcd4 <uart_console_init+0x2c>)
    dcb8:	f7ff fe36 	bl	d928 <__stdout_hook_install>
	__printk_hook_install(console_out);
    dcbc:	4805      	ldr	r0, [pc, #20]	; (dcd4 <uart_console_init+0x2c>)
    dcbe:	f7fe fc8b 	bl	c5d8 <__printk_hook_install>
		return -ENODEV;
	}

	uart_console_hook_install();

	return 0;
    dcc2:	2000      	movs	r0, #0
}
    dcc4:	bd08      	pop	{r3, pc}
		return -ENODEV;
    dcc6:	f06f 0012 	mvn.w	r0, #18
    dcca:	e7fb      	b.n	dcc4 <uart_console_init+0x1c>
    dccc:	2000026c 	.word	0x2000026c
    dcd0:	00010a18 	.word	0x00010a18
    dcd4:	0000dcd9 	.word	0x0000dcd9

0000dcd8 <console_out>:
	if ('\n' == c) {
    dcd8:	280a      	cmp	r0, #10
{
    dcda:	b538      	push	{r3, r4, r5, lr}
    dcdc:	4d07      	ldr	r5, [pc, #28]	; (dcfc <console_out+0x24>)
    dcde:	4604      	mov	r4, r0
	if ('\n' == c) {
    dce0:	d104      	bne.n	dcec <console_out+0x14>
		uart_poll_out(uart_console_dev, '\r');
    dce2:	6828      	ldr	r0, [r5, #0]
					unsigned char out_char)
{
	const struct uart_driver_api *api =
		(const struct uart_driver_api *)dev->api;

	api->poll_out(dev, out_char);
    dce4:	6883      	ldr	r3, [r0, #8]
    dce6:	210d      	movs	r1, #13
    dce8:	685b      	ldr	r3, [r3, #4]
    dcea:	4798      	blx	r3
	uart_poll_out(uart_console_dev, c);
    dcec:	6828      	ldr	r0, [r5, #0]
    dcee:	6883      	ldr	r3, [r0, #8]
    dcf0:	b2e1      	uxtb	r1, r4
    dcf2:	685b      	ldr	r3, [r3, #4]
    dcf4:	4798      	blx	r3
}
    dcf6:	4620      	mov	r0, r4
    dcf8:	bd38      	pop	{r3, r4, r5, pc}
    dcfa:	bf00      	nop
    dcfc:	2000026c 	.word	0x2000026c

0000dd00 <gpio_nrfx_pin_interrupt_configure>:

static int gpio_nrfx_pin_interrupt_configure(const struct device *port,
					     gpio_pin_t pin,
					     enum gpio_int_mode mode,
					     enum gpio_int_trig trig)
{
    dd00:	b530      	push	{r4, r5, lr}
	return port->config;
    dd02:	6840      	ldr	r0, [r0, #4]
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
    dd04:	7b04      	ldrb	r4, [r0, #12]
    dd06:	f001 051f 	and.w	r5, r1, #31
	nrfx_err_t err;

	if (mode == GPIO_INT_MODE_DISABLED) {
    dd0a:	f5b2 1f00 	cmp.w	r2, #2097152	; 0x200000
	uint32_t abs_pin = NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin);
    dd0e:	ea45 1544 	orr.w	r5, r5, r4, lsl #5
{
    dd12:	b085      	sub	sp, #20
    dd14:	f04f 0400 	mov.w	r4, #0
	if (mode == GPIO_INT_MODE_DISABLED) {
    dd18:	d104      	bne.n	dd24 <gpio_nrfx_pin_interrupt_configure+0x24>
		nrfx_gpiote_trigger_disable(abs_pin);
    dd1a:	4628      	mov	r0, r5
    dd1c:	f001 f9d2 	bl	f0c4 <nrfx_gpiote_trigger_disable>
		return -EIO;
	}

	nrfx_gpiote_trigger_enable(abs_pin, true);

	return 0;
    dd20:	2000      	movs	r0, #0
    dd22:	e02e      	b.n	dd82 <gpio_nrfx_pin_interrupt_configure+0x82>
	if (mode == GPIO_INT_MODE_LEVEL) {
    dd24:	f5b2 0f80 	cmp.w	r2, #4194304	; 0x400000
	nrfx_gpiote_trigger_config_t trigger_config = {
    dd28:	e9cd 4402 	strd	r4, r4, [sp, #8]
	if (mode == GPIO_INT_MODE_LEVEL) {
    dd2c:	d12b      	bne.n	dd86 <gpio_nrfx_pin_interrupt_configure+0x86>
		return trig == GPIO_INT_TRIG_LOW ? NRFX_GPIOTE_TRIGGER_LOW :
    dd2e:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
    dd32:	bf0c      	ite	eq
    dd34:	2304      	moveq	r3, #4
    dd36:	2305      	movne	r3, #5
	nrfx_gpiote_trigger_config_t trigger_config = {
    dd38:	f88d 3008 	strb.w	r3, [sp, #8]
	if (!(BIT(pin) & get_port_cfg(port)->edge_sense) &&
    dd3c:	6883      	ldr	r3, [r0, #8]
    dd3e:	fa23 f101 	lsr.w	r1, r3, r1
    dd42:	07c9      	lsls	r1, r1, #31
    dd44:	d42b      	bmi.n	dd9e <gpio_nrfx_pin_interrupt_configure+0x9e>
    dd46:	f1b2 7fa0 	cmp.w	r2, #20971520	; 0x1400000
    dd4a:	d128      	bne.n	dd9e <gpio_nrfx_pin_interrupt_configure+0x9e>
}

NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin)
{
    uint32_t pin_number = *p_pin;
    *p_pin = pin_number & 0x1F;
    dd4c:	f005 031f 	and.w	r3, r5, #31
    return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
    dd50:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    dd54:	f04f 42a0 	mov.w	r2, #1342177280	; 0x50000000
    dd58:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
	    (mode == GPIO_INT_MODE_EDGE) &&
    dd5c:	07db      	lsls	r3, r3, #31
    dd5e:	d41e      	bmi.n	dd9e <gpio_nrfx_pin_interrupt_configure+0x9e>
		err = nrfx_gpiote_channel_get(abs_pin, &ch);
    dd60:	f10d 0407 	add.w	r4, sp, #7
    dd64:	4621      	mov	r1, r4
    dd66:	4628      	mov	r0, r5
    dd68:	f001 f914 	bl	ef94 <nrfx_gpiote_channel_get>
		if (err == NRFX_ERROR_INVALID_PARAM) {
    dd6c:	4b14      	ldr	r3, [pc, #80]	; (ddc0 <gpio_nrfx_pin_interrupt_configure+0xc0>)
    dd6e:	4298      	cmp	r0, r3
    dd70:	d114      	bne.n	dd9c <gpio_nrfx_pin_interrupt_configure+0x9c>
			err = nrfx_gpiote_channel_alloc(&ch);
    dd72:	4620      	mov	r0, r4
    dd74:	f001 f95c 	bl	f030 <nrfx_gpiote_channel_alloc>
			if (err != NRFX_SUCCESS) {
    dd78:	4b12      	ldr	r3, [pc, #72]	; (ddc4 <gpio_nrfx_pin_interrupt_configure+0xc4>)
    dd7a:	4298      	cmp	r0, r3
    dd7c:	d00e      	beq.n	dd9c <gpio_nrfx_pin_interrupt_configure+0x9c>
				return -ENOMEM;
    dd7e:	f06f 000b 	mvn.w	r0, #11
}
    dd82:	b005      	add	sp, #20
    dd84:	bd30      	pop	{r4, r5, pc}
	return trig == GPIO_INT_TRIG_BOTH ? NRFX_GPIOTE_TRIGGER_TOGGLE :
    dd86:	f1b3 6fc0 	cmp.w	r3, #100663296	; 0x6000000
    dd8a:	d005      	beq.n	dd98 <gpio_nrfx_pin_interrupt_configure+0x98>
    dd8c:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
    dd90:	bf0c      	ite	eq
    dd92:	2302      	moveq	r3, #2
    dd94:	2301      	movne	r3, #1
    dd96:	e7cf      	b.n	dd38 <gpio_nrfx_pin_interrupt_configure+0x38>
    dd98:	2303      	movs	r3, #3
    dd9a:	e7cd      	b.n	dd38 <gpio_nrfx_pin_interrupt_configure+0x38>
		trigger_config.p_in_channel = &ch;
    dd9c:	9403      	str	r4, [sp, #12]
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    dd9e:	2300      	movs	r3, #0
    dda0:	4619      	mov	r1, r3
    dda2:	aa02      	add	r2, sp, #8
    dda4:	4628      	mov	r0, r5
    dda6:	f000 ffcd 	bl	ed44 <nrfx_gpiote_input_configure>
	if (err != NRFX_SUCCESS) {
    ddaa:	4b06      	ldr	r3, [pc, #24]	; (ddc4 <gpio_nrfx_pin_interrupt_configure+0xc4>)
    ddac:	4298      	cmp	r0, r3
    ddae:	d104      	bne.n	ddba <gpio_nrfx_pin_interrupt_configure+0xba>
	nrfx_gpiote_trigger_enable(abs_pin, true);
    ddb0:	2101      	movs	r1, #1
    ddb2:	4628      	mov	r0, r5
    ddb4:	f001 f942 	bl	f03c <nrfx_gpiote_trigger_enable>
    ddb8:	e7b2      	b.n	dd20 <gpio_nrfx_pin_interrupt_configure+0x20>
		return -EIO;
    ddba:	f06f 0004 	mvn.w	r0, #4
    ddbe:	e7e0      	b.n	dd82 <gpio_nrfx_pin_interrupt_configure+0x82>
    ddc0:	0bad0004 	.word	0x0bad0004
    ddc4:	0bad0000 	.word	0x0bad0000

0000ddc8 <gpio_nrfx_init>:
}

#define GPIOTE_NODE DT_INST(0, nordic_nrf_gpiote)

static int gpio_nrfx_init(const struct device *port)
{
    ddc8:	b510      	push	{r4, lr}
	nrfx_err_t err;

	if (nrfx_gpiote_is_init()) {
    ddca:	f001 f921 	bl	f010 <nrfx_gpiote_is_init>
    ddce:	4604      	mov	r4, r0
    ddd0:	b968      	cbnz	r0, ddee <gpio_nrfx_init+0x26>
		return 0;
	}

	err = nrfx_gpiote_init(0/*not used*/);
    ddd2:	f001 f8f5 	bl	efc0 <nrfx_gpiote_init>
	if (err != NRFX_SUCCESS) {
    ddd6:	4b08      	ldr	r3, [pc, #32]	; (ddf8 <gpio_nrfx_init+0x30>)
    ddd8:	4298      	cmp	r0, r3
    ddda:	d10a      	bne.n	ddf2 <gpio_nrfx_init+0x2a>
		return -EIO;
	}

	nrfx_gpiote_global_callback_set(nrfx_gpio_handler, NULL);
    dddc:	4807      	ldr	r0, [pc, #28]	; (ddfc <gpio_nrfx_init+0x34>)
    ddde:	4621      	mov	r1, r4
    dde0:	f001 f8d2 	bl	ef88 <nrfx_gpiote_global_callback_set>

	IRQ_CONNECT(DT_IRQN(GPIOTE_NODE), DT_IRQ(GPIOTE_NODE, priority),
    dde4:	4622      	mov	r2, r4
    dde6:	2105      	movs	r1, #5
    dde8:	2006      	movs	r0, #6
    ddea:	f7ff fa45 	bl	d278 <z_arm_irq_priority_set>
		return 0;
    ddee:	2000      	movs	r0, #0
		    nrfx_isr, nrfx_gpiote_irq_handler, 0);

	return 0;
}
    ddf0:	bd10      	pop	{r4, pc}
		return -EIO;
    ddf2:	f06f 0004 	mvn.w	r0, #4
    ddf6:	e7fb      	b.n	ddf0 <gpio_nrfx_init+0x28>
    ddf8:	0bad0000 	.word	0x0bad0000
    ddfc:	0000de01 	.word	0x0000de01

0000de00 <nrfx_gpio_handler>:
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    de00:	0943      	lsrs	r3, r0, #5
{
    de02:	b570      	push	{r4, r5, r6, lr}
	DT_INST_FOREACH_STATUS_OKAY(GPIO_NRF_GET_DEV)
    de04:	d110      	bne.n	de28 <nrfx_gpio_handler+0x28>
	return list->head;
    de06:	4b09      	ldr	r3, [pc, #36]	; (de2c <nrfx_gpio_handler+0x2c>)
    de08:	6859      	ldr	r1, [r3, #4]
					const struct device *port,
					uint32_t pins)
{
	struct gpio_callback *cb, *tmp;

	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    de0a:	b169      	cbz	r1, de28 <nrfx_gpio_handler+0x28>
	gpio_fire_callbacks(list, port, BIT(pin));
    de0c:	2501      	movs	r5, #1
	return node->next;
    de0e:	680c      	ldr	r4, [r1, #0]
		if (cb->pin_mask & pins) {
			__ASSERT(cb->handler, "No callback handler!");
			cb->handler(port, cb, cb->pin_mask & pins);
    de10:	4e07      	ldr	r6, [pc, #28]	; (de30 <nrfx_gpio_handler+0x30>)
    de12:	4085      	lsls	r5, r0
		if (cb->pin_mask & pins) {
    de14:	688a      	ldr	r2, [r1, #8]
    de16:	402a      	ands	r2, r5
    de18:	d002      	beq.n	de20 <nrfx_gpio_handler+0x20>
			cb->handler(port, cb, cb->pin_mask & pins);
    de1a:	684b      	ldr	r3, [r1, #4]
    de1c:	4630      	mov	r0, r6
    de1e:	4798      	blx	r3
	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) {
    de20:	b114      	cbz	r4, de28 <nrfx_gpio_handler+0x28>
    de22:	4621      	mov	r1, r4
    de24:	6824      	ldr	r4, [r4, #0]
    de26:	e7f5      	b.n	de14 <nrfx_gpio_handler+0x14>
}
    de28:	bd70      	pop	{r4, r5, r6, pc}
    de2a:	bf00      	nop
    de2c:	20000270 	.word	0x20000270
    de30:	00010a00 	.word	0x00010a00

0000de34 <gpio_nrfx_pin_configure>:
{
    de34:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
	return port->config;
    de38:	6847      	ldr	r7, [r0, #4]
	nrfx_gpiote_pin_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    de3a:	7b3b      	ldrb	r3, [r7, #12]
    de3c:	f001 051f 	and.w	r5, r1, #31
{
    de40:	b085      	sub	sp, #20
    de42:	460e      	mov	r6, r1
	nrfx_gpiote_pin_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
    de44:	ea45 1543 	orr.w	r5, r5, r3, lsl #5
	if (flags == GPIO_DISCONNECTED) {
    de48:	4614      	mov	r4, r2
    de4a:	b9ca      	cbnz	r2, de80 <gpio_nrfx_pin_configure+0x4c>
	err = nrfx_gpiote_channel_get(pin, &ch);
    de4c:	a902      	add	r1, sp, #8
    de4e:	4628      	mov	r0, r5
    de50:	f001 f8a0 	bl	ef94 <nrfx_gpiote_channel_get>
    de54:	4604      	mov	r4, r0
	err = nrfx_gpiote_pin_uninit(pin);
    de56:	4628      	mov	r0, r5
    de58:	f001 f95c 	bl	f114 <nrfx_gpiote_pin_uninit>
	if (err != NRFX_SUCCESS) {
    de5c:	4b4a      	ldr	r3, [pc, #296]	; (df88 <gpio_nrfx_pin_configure+0x154>)
    de5e:	4298      	cmp	r0, r3
    de60:	d004      	beq.n	de6c <gpio_nrfx_pin_configure+0x38>
		return -EIO;
    de62:	f06f 0004 	mvn.w	r0, #4
}
    de66:	b005      	add	sp, #20
    de68:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
	if (free_ch) {
    de6c:	4284      	cmp	r4, r0
    de6e:	d105      	bne.n	de7c <gpio_nrfx_pin_configure+0x48>
		err = nrfx_gpiote_channel_free(ch);
    de70:	f89d 0008 	ldrb.w	r0, [sp, #8]
    de74:	f001 f8d6 	bl	f024 <nrfx_gpiote_channel_free>
	return (err != NRFX_SUCCESS) ? -EIO : 0;
    de78:	42a0      	cmp	r0, r4
    de7a:	d1f2      	bne.n	de62 <gpio_nrfx_pin_configure+0x2e>
	return (err != NRFX_SUCCESS) ? -EINVAL : 0;
    de7c:	2000      	movs	r0, #0
    de7e:	e7f2      	b.n	de66 <gpio_nrfx_pin_configure+0x32>
	nrfx_gpiote_trigger_config_t trigger_config = {
    de80:	f04f 0900 	mov.w	r9, #0
	err = nrfx_gpiote_channel_get(pin, &ch);
    de84:	f10d 0103 	add.w	r1, sp, #3
    de88:	4630      	mov	r0, r6
	nrfx_gpiote_trigger_config_t trigger_config = {
    de8a:	e9cd 9902 	strd	r9, r9, [sp, #8]
	err = nrfx_gpiote_channel_get(pin, &ch);
    de8e:	f001 f881 	bl	ef94 <nrfx_gpiote_channel_get>
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    de92:	464b      	mov	r3, r9
	err = nrfx_gpiote_channel_get(pin, &ch);
    de94:	4680      	mov	r8, r0
	err = nrfx_gpiote_input_configure(abs_pin, NULL, &trigger_config, NULL);
    de96:	aa02      	add	r2, sp, #8
    de98:	4649      	mov	r1, r9
    de9a:	4628      	mov	r0, r5
    de9c:	f000 ff52 	bl	ed44 <nrfx_gpiote_input_configure>
	if (err != NRFX_SUCCESS) {
    dea0:	4b39      	ldr	r3, [pc, #228]	; (df88 <gpio_nrfx_pin_configure+0x154>)
    dea2:	4298      	cmp	r0, r3
    dea4:	d002      	beq.n	deac <gpio_nrfx_pin_configure+0x78>
	switch (flags & (NRF_GPIO_DS_LOW_MASK | NRF_GPIO_DS_HIGH_MASK |
    dea6:	f06f 0015 	mvn.w	r0, #21
    deaa:	e7dc      	b.n	de66 <gpio_nrfx_pin_configure+0x32>
	if (free_ch) {
    deac:	4580      	cmp	r8, r0
    deae:	d103      	bne.n	deb8 <gpio_nrfx_pin_configure+0x84>
		err = nrfx_gpiote_channel_free(ch);
    deb0:	f89d 0003 	ldrb.w	r0, [sp, #3]
    deb4:	f001 f8b6 	bl	f024 <nrfx_gpiote_channel_free>
	if (flags & GPIO_OUTPUT) {
    deb8:	03a3      	lsls	r3, r4, #14
    deba:	d551      	bpl.n	df60 <gpio_nrfx_pin_configure+0x12c>
	switch (flags & (NRF_GPIO_DS_LOW_MASK | NRF_GPIO_DS_HIGH_MASK |
    debc:	f240 6306 	movw	r3, #1542	; 0x606
    dec0:	4023      	ands	r3, r4
    dec2:	f240 2206 	movw	r2, #518	; 0x206
    dec6:	4293      	cmp	r3, r2
    dec8:	d03b      	beq.n	df42 <gpio_nrfx_pin_configure+0x10e>
    deca:	d80c      	bhi.n	dee6 <gpio_nrfx_pin_configure+0xb2>
    decc:	2b06      	cmp	r3, #6
    dece:	d015      	beq.n	defc <gpio_nrfx_pin_configure+0xc8>
    ded0:	d804      	bhi.n	dedc <gpio_nrfx_pin_configure+0xa8>
    ded2:	b19b      	cbz	r3, defc <gpio_nrfx_pin_configure+0xc8>
    ded4:	2b02      	cmp	r3, #2
    ded6:	d1e6      	bne.n	dea6 <gpio_nrfx_pin_configure+0x72>
    ded8:	2304      	movs	r3, #4
    deda:	e00f      	b.n	defc <gpio_nrfx_pin_configure+0xc8>
    dedc:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
    dee0:	d1e1      	bne.n	dea6 <gpio_nrfx_pin_configure+0x72>
		*drive = NRF_GPIO_PIN_H0S1;
    dee2:	2301      	movs	r3, #1
    dee4:	e00a      	b.n	defc <gpio_nrfx_pin_configure+0xc8>
	switch (flags & (NRF_GPIO_DS_LOW_MASK | NRF_GPIO_DS_HIGH_MASK |
    dee6:	f240 4202 	movw	r2, #1026	; 0x402
    deea:	4293      	cmp	r3, r2
    deec:	d02b      	beq.n	df46 <gpio_nrfx_pin_configure+0x112>
    deee:	f5b3 6fc0 	cmp.w	r3, #1536	; 0x600
    def2:	d02a      	beq.n	df4a <gpio_nrfx_pin_configure+0x116>
    def4:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
    def8:	d1d5      	bne.n	dea6 <gpio_nrfx_pin_configure+0x72>
		*drive = NRF_GPIO_PIN_S0H1;
    defa:	2302      	movs	r3, #2
		nrfx_gpiote_output_config_t output_config = {
    defc:	f88d 3004 	strb.w	r3, [sp, #4]
				NRF_GPIO_PIN_INPUT_CONNECT :
    df00:	f484 3380 	eor.w	r3, r4, #65536	; 0x10000
    df04:	f3c3 4300 	ubfx	r3, r3, #16, #1
	if (flags & GPIO_PULL_UP) {
    df08:	06e0      	lsls	r0, r4, #27
		nrfx_gpiote_output_config_t output_config = {
    df0a:	f88d 3005 	strb.w	r3, [sp, #5]
		return NRF_GPIO_PIN_PULLDOWN;
    df0e:	bf54      	ite	pl
    df10:	f3c4 1340 	ubfxpl	r3, r4, #5, #1
		return NRF_GPIO_PIN_PULLUP;
    df14:	2303      	movmi	r3, #3
		if (flags & GPIO_OUTPUT_INIT_HIGH) {
    df16:	0321      	lsls	r1, r4, #12
		nrfx_gpiote_output_config_t output_config = {
    df18:	f88d 3006 	strb.w	r3, [sp, #6]
		if (flags & GPIO_OUTPUT_INIT_HIGH) {
    df1c:	d517      	bpl.n	df4e <gpio_nrfx_pin_configure+0x11a>
			nrf_gpio_port_out_set(cfg->port, BIT(pin));
    df1e:	687b      	ldr	r3, [r7, #4]
    df20:	2101      	movs	r1, #1
    df22:	fa01 f606 	lsl.w	r6, r1, r6
    p_reg->OUTSET = set_mask;
    df26:	f8c3 6508 	str.w	r6, [r3, #1288]	; 0x508
		err = nrfx_gpiote_output_configure(abs_pin, &output_config, NULL);
    df2a:	2200      	movs	r2, #0
    df2c:	a901      	add	r1, sp, #4
    df2e:	4628      	mov	r0, r5
    df30:	f000 ffb2 	bl	ee98 <nrfx_gpiote_output_configure>
		return (err != NRFX_SUCCESS) ? -EINVAL : 0;
    df34:	4b14      	ldr	r3, [pc, #80]	; (df88 <gpio_nrfx_pin_configure+0x154>)
    df36:	4298      	cmp	r0, r3
    df38:	bf14      	ite	ne
    df3a:	f06f 0015 	mvnne.w	r0, #21
    df3e:	2000      	moveq	r0, #0
    df40:	e791      	b.n	de66 <gpio_nrfx_pin_configure+0x32>
		*drive = NRF_GPIO_PIN_H0D1;
    df42:	2307      	movs	r3, #7
    df44:	e7da      	b.n	defc <gpio_nrfx_pin_configure+0xc8>
		*drive = NRF_GPIO_PIN_D0H1;
    df46:	2305      	movs	r3, #5
    df48:	e7d8      	b.n	defc <gpio_nrfx_pin_configure+0xc8>
		*drive = NRF_GPIO_PIN_H0H1;
    df4a:	2303      	movs	r3, #3
    df4c:	e7d6      	b.n	defc <gpio_nrfx_pin_configure+0xc8>
		} else if (flags & GPIO_OUTPUT_INIT_LOW) {
    df4e:	0362      	lsls	r2, r4, #13
			nrf_gpio_port_out_clear(cfg->port, BIT(pin));
    df50:	bf41      	itttt	mi
    df52:	687b      	ldrmi	r3, [r7, #4]
    df54:	2101      	movmi	r1, #1
    df56:	fa01 f606 	lslmi.w	r6, r1, r6
    p_reg->OUTCLR = clr_mask;
    df5a:	f8c3 650c 	strmi.w	r6, [r3, #1292]	; 0x50c
}
    df5e:	e7e4      	b.n	df2a <gpio_nrfx_pin_configure+0xf6>
	if (flags & GPIO_PULL_UP) {
    df60:	06e3      	lsls	r3, r4, #27
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    df62:	f04f 0300 	mov.w	r3, #0
		return NRF_GPIO_PIN_PULLUP;
    df66:	bf54      	ite	pl
    df68:	f3c4 1440 	ubfxpl	r4, r4, #5, #1
    df6c:	2403      	movmi	r4, #3
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    df6e:	461a      	mov	r2, r3
    df70:	a901      	add	r1, sp, #4
    df72:	4628      	mov	r0, r5
	nrfx_gpiote_input_config_t input_config = {
    df74:	f88d 4004 	strb.w	r4, [sp, #4]
	err = nrfx_gpiote_input_configure(abs_pin, &input_config, NULL, NULL);
    df78:	f000 fee4 	bl	ed44 <nrfx_gpiote_input_configure>
	return (err != NRFX_SUCCESS) ? -EINVAL : 0;
    df7c:	4b02      	ldr	r3, [pc, #8]	; (df88 <gpio_nrfx_pin_configure+0x154>)
    df7e:	4298      	cmp	r0, r3
    df80:	f43f af7c 	beq.w	de7c <gpio_nrfx_pin_configure+0x48>
    df84:	e78f      	b.n	dea6 <gpio_nrfx_pin_configure+0x72>
    df86:	bf00      	nop
    df88:	0bad0000 	.word	0x0bad0000

0000df8c <uarte_nrfx_configure>:
	return 0;
}

static int uarte_nrfx_configure(const struct device *dev,
				const struct uart_config *cfg)
{
    df8c:	b570      	push	{r4, r5, r6, lr}
		break;
	default:
		return -ENOTSUP;
	}
#else
	if (cfg->stop_bits != UART_CFG_STOP_BITS_1) {
    df8e:	794b      	ldrb	r3, [r1, #5]
    df90:	2b01      	cmp	r3, #1
    df92:	d120      	bne.n	dfd6 <uarte_nrfx_configure+0x4a>
		return -ENOTSUP;
	}
#endif

	if (cfg->data_bits != UART_CFG_DATA_BITS_8) {
    df94:	798b      	ldrb	r3, [r1, #6]
    df96:	2b03      	cmp	r3, #3
    df98:	d11d      	bne.n	dfd6 <uarte_nrfx_configure+0x4a>
		return -ENOTSUP;
	}

	switch (cfg->flow_ctrl) {
    df9a:	79cc      	ldrb	r4, [r1, #7]
    df9c:	b10c      	cbz	r4, dfa2 <uarte_nrfx_configure+0x16>
    df9e:	2c01      	cmp	r4, #1
    dfa0:	d119      	bne.n	dfd6 <uarte_nrfx_configure+0x4a>
	}

#if defined(UARTE_CONFIG_PARITYTYPE_Msk)
	uarte_cfg.paritytype = NRF_UARTE_PARITYTYPE_EVEN;
#endif
	switch (cfg->parity) {
    dfa2:	790a      	ldrb	r2, [r1, #4]
    dfa4:	b112      	cbz	r2, dfac <uarte_nrfx_configure+0x20>
    dfa6:	2a02      	cmp	r2, #2
    dfa8:	d115      	bne.n	dfd6 <uarte_nrfx_configure+0x4a>
    dfaa:	220e      	movs	r2, #14
#endif
	default:
		return -ENOTSUP;
	}

	if (baudrate_set(dev, cfg->baudrate) != 0) {
    dfac:	680b      	ldr	r3, [r1, #0]
	return config->uarte_regs;
    dfae:	6845      	ldr	r5, [r0, #4]
	switch (baudrate) {
    dfb0:	f5b3 4f16 	cmp.w	r3, #38400	; 0x9600
	return config->uarte_regs;
    dfb4:	682d      	ldr	r5, [r5, #0]
	switch (baudrate) {
    dfb6:	d062      	beq.n	e07e <uarte_nrfx_configure+0xf2>
    dfb8:	d82b      	bhi.n	e012 <uarte_nrfx_configure+0x86>
    dfba:	f5b3 5f16 	cmp.w	r3, #9600	; 0x2580
    dfbe:	d061      	beq.n	e084 <uarte_nrfx_configure+0xf8>
    dfc0:	d814      	bhi.n	dfec <uarte_nrfx_configure+0x60>
    dfc2:	f5b3 6f96 	cmp.w	r3, #1200	; 0x4b0
    dfc6:	d05f      	beq.n	e088 <uarte_nrfx_configure+0xfc>
    dfc8:	d808      	bhi.n	dfdc <uarte_nrfx_configure+0x50>
    dfca:	f5b3 7f96 	cmp.w	r3, #300	; 0x12c
    dfce:	d05e      	beq.n	e08e <uarte_nrfx_configure+0x102>
    dfd0:	f5b3 7f16 	cmp.w	r3, #600	; 0x258
    dfd4:	d05e      	beq.n	e094 <uarte_nrfx_configure+0x108>
    dfd6:	f06f 0085 	mvn.w	r0, #133	; 0x85
    dfda:	e04f      	b.n	e07c <uarte_nrfx_configure+0xf0>
    dfdc:	f5b3 6f16 	cmp.w	r3, #2400	; 0x960
    dfe0:	d05b      	beq.n	e09a <uarte_nrfx_configure+0x10e>
    dfe2:	f5b3 5f96 	cmp.w	r3, #4800	; 0x12c0
    dfe6:	d1f6      	bne.n	dfd6 <uarte_nrfx_configure+0x4a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_4800;
    dfe8:	4b36      	ldr	r3, [pc, #216]	; (e0c4 <uarte_nrfx_configure+0x138>)
    dfea:	e03c      	b.n	e066 <uarte_nrfx_configure+0xda>
	switch (baudrate) {
    dfec:	f5b3 4fe1 	cmp.w	r3, #28800	; 0x7080
    dff0:	d056      	beq.n	e0a0 <uarte_nrfx_configure+0x114>
    dff2:	d807      	bhi.n	e004 <uarte_nrfx_configure+0x78>
    dff4:	f5b3 5f61 	cmp.w	r3, #14400	; 0x3840
    dff8:	d054      	beq.n	e0a4 <uarte_nrfx_configure+0x118>
    dffa:	f5b3 4f96 	cmp.w	r3, #19200	; 0x4b00
    dffe:	d1ea      	bne.n	dfd6 <uarte_nrfx_configure+0x4a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_19200;
    e000:	4b31      	ldr	r3, [pc, #196]	; (e0c8 <uarte_nrfx_configure+0x13c>)
    e002:	e030      	b.n	e066 <uarte_nrfx_configure+0xda>
	switch (baudrate) {
    e004:	f647 2612 	movw	r6, #31250	; 0x7a12
    e008:	42b3      	cmp	r3, r6
    e00a:	d1e4      	bne.n	dfd6 <uarte_nrfx_configure+0x4a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_31250;
    e00c:	f44f 0300 	mov.w	r3, #8388608	; 0x800000
    e010:	e029      	b.n	e066 <uarte_nrfx_configure+0xda>
	switch (baudrate) {
    e012:	f5b3 3f61 	cmp.w	r3, #230400	; 0x38400
    e016:	d047      	beq.n	e0a8 <uarte_nrfx_configure+0x11c>
    e018:	d813      	bhi.n	e042 <uarte_nrfx_configure+0xb6>
    e01a:	f5b3 3f96 	cmp.w	r3, #76800	; 0x12c00
    e01e:	d046      	beq.n	e0ae <uarte_nrfx_configure+0x122>
    e020:	d809      	bhi.n	e036 <uarte_nrfx_configure+0xaa>
    e022:	f64d 26c0 	movw	r6, #56000	; 0xdac0
    e026:	42b3      	cmp	r3, r6
    e028:	d043      	beq.n	e0b2 <uarte_nrfx_configure+0x126>
    e02a:	f5b3 4f61 	cmp.w	r3, #57600	; 0xe100
    e02e:	d1d2      	bne.n	dfd6 <uarte_nrfx_configure+0x4a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_57600;
    e030:	f44f 036b 	mov.w	r3, #15400960	; 0xeb0000
    e034:	e017      	b.n	e066 <uarte_nrfx_configure+0xda>
	switch (baudrate) {
    e036:	f5b3 3fe1 	cmp.w	r3, #115200	; 0x1c200
    e03a:	d1cc      	bne.n	dfd6 <uarte_nrfx_configure+0x4a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_115200;
    e03c:	f04f 73eb 	mov.w	r3, #30801920	; 0x1d60000
    e040:	e011      	b.n	e066 <uarte_nrfx_configure+0xda>
	switch (baudrate) {
    e042:	f5b3 2f61 	cmp.w	r3, #921600	; 0xe1000
    e046:	d037      	beq.n	e0b8 <uarte_nrfx_configure+0x12c>
    e048:	d808      	bhi.n	e05c <uarte_nrfx_configure+0xd0>
    e04a:	4e20      	ldr	r6, [pc, #128]	; (e0cc <uarte_nrfx_configure+0x140>)
    e04c:	42b3      	cmp	r3, r6
    e04e:	d036      	beq.n	e0be <uarte_nrfx_configure+0x132>
    e050:	f5b3 2fe1 	cmp.w	r3, #460800	; 0x70800
    e054:	d1bf      	bne.n	dfd6 <uarte_nrfx_configure+0x4a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_460800;
    e056:	f04f 63e8 	mov.w	r3, #121634816	; 0x7400000
    e05a:	e004      	b.n	e066 <uarte_nrfx_configure+0xda>
	switch (baudrate) {
    e05c:	4e1c      	ldr	r6, [pc, #112]	; (e0d0 <uarte_nrfx_configure+0x144>)
    e05e:	42b3      	cmp	r3, r6
    e060:	d1b9      	bne.n	dfd6 <uarte_nrfx_configure+0x4a>
		nrf_baudrate = NRF_UARTE_BAUDRATE_1000000;
    e062:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
	struct uarte_nrfx_data *data = dev->data;
    e066:	6900      	ldr	r0, [r0, #16]
                    | (uint32_t)p_cfg->hwfc;
}

NRF_STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate)
{
    p_reg->BAUDRATE = baudrate;
    e068:	f8c5 3524 	str.w	r3, [r5, #1316]	; 0x524
		return -ENOTSUP;
	}

	nrf_uarte_configure(get_uarte_instance(dev), &uarte_cfg);

	data->uart_config = *cfg;
    e06c:	1d03      	adds	r3, r0, #4
    e06e:	c903      	ldmia	r1, {r0, r1}
                    | (uint32_t)p_cfg->hwfc;
    e070:	4322      	orrs	r2, r4
    p_reg->CONFIG = (uint32_t)p_cfg->parity
    e072:	f8c5 256c 	str.w	r2, [r5, #1388]	; 0x56c
    e076:	e883 0003 	stmia.w	r3, {r0, r1}

	return 0;
    e07a:	2000      	movs	r0, #0
}
    e07c:	bd70      	pop	{r4, r5, r6, pc}
		nrf_baudrate = NRF_UARTE_BAUDRATE_38400;
    e07e:	f44f 031d 	mov.w	r3, #10289152	; 0x9d0000
    e082:	e7f0      	b.n	e066 <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_9600;
    e084:	4b13      	ldr	r3, [pc, #76]	; (e0d4 <uarte_nrfx_configure+0x148>)
    e086:	e7ee      	b.n	e066 <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_1200;
    e088:	f44f 239e 	mov.w	r3, #323584	; 0x4f000
    e08c:	e7eb      	b.n	e066 <uarte_nrfx_configure+0xda>
		nrf_baudrate = 0x00014000;
    e08e:	f44f 33a0 	mov.w	r3, #81920	; 0x14000
    e092:	e7e8      	b.n	e066 <uarte_nrfx_configure+0xda>
	switch (baudrate) {
    e094:	f44f 331c 	mov.w	r3, #159744	; 0x27000
    e098:	e7e5      	b.n	e066 <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_2400;
    e09a:	f44f 231d 	mov.w	r3, #643072	; 0x9d000
    e09e:	e7e2      	b.n	e066 <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_28800;
    e0a0:	4b0d      	ldr	r3, [pc, #52]	; (e0d8 <uarte_nrfx_configure+0x14c>)
    e0a2:	e7e0      	b.n	e066 <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_14400;
    e0a4:	4b0d      	ldr	r3, [pc, #52]	; (e0dc <uarte_nrfx_configure+0x150>)
    e0a6:	e7de      	b.n	e066 <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_230400;
    e0a8:	f04f 736c 	mov.w	r3, #61865984	; 0x3b00000
    e0ac:	e7db      	b.n	e066 <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_76800;
    e0ae:	4b0c      	ldr	r3, [pc, #48]	; (e0e0 <uarte_nrfx_configure+0x154>)
    e0b0:	e7d9      	b.n	e066 <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_56000;
    e0b2:	f44f 0365 	mov.w	r3, #15007744	; 0xe50000
    e0b6:	e7d6      	b.n	e066 <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_921600;
    e0b8:	f04f 6370 	mov.w	r3, #251658240	; 0xf000000
    e0bc:	e7d3      	b.n	e066 <uarte_nrfx_configure+0xda>
		nrf_baudrate = NRF_UARTE_BAUDRATE_250000;
    e0be:	f04f 6380 	mov.w	r3, #67108864	; 0x4000000
    e0c2:	e7d0      	b.n	e066 <uarte_nrfx_configure+0xda>
    e0c4:	0013b000 	.word	0x0013b000
    e0c8:	004ea000 	.word	0x004ea000
    e0cc:	0003d090 	.word	0x0003d090
    e0d0:	000f4240 	.word	0x000f4240
    e0d4:	00275000 	.word	0x00275000
    e0d8:	0075c000 	.word	0x0075c000
    e0dc:	003af000 	.word	0x003af000
    e0e0:	013a9000 	.word	0x013a9000

0000e0e4 <uarte_0_init>:
				.tx_buffer = uarte##idx##_tx_buffer,	       \
				.tx_buff_size = sizeof(uarte##idx##_tx_buffer),\
			};))

#ifdef CONFIG_UART_0_NRF_UARTE
UART_NRF_UARTE_DEVICE(0);
    e0e4:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    e0e8:	4607      	mov	r7, r0
    e0ea:	2200      	movs	r2, #0
    e0ec:	2101      	movs	r1, #1
    e0ee:	2002      	movs	r0, #2
    e0f0:	f7ff f8c2 	bl	d278 <z_arm_irq_priority_set>
    e0f4:	2002      	movs	r0, #2
    e0f6:	f7ff f8a1 	bl	d23c <arch_irq_enable>
	const struct uarte_nrfx_config *config = dev->config;
    e0fa:	f8d7 8004 	ldr.w	r8, [r7, #4]
	struct uarte_nrfx_data *data = dev->data;
    e0fe:	693e      	ldr	r6, [r7, #16]
	return config->uarte_regs;
    e100:	f8d8 4000 	ldr.w	r4, [r8]
	err = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
    e104:	f8d8 900c 	ldr.w	r9, [r8, #12]
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
    e108:	2100      	movs	r1, #0
    e10a:	f8c4 1500 	str.w	r1, [r4, #1280]	; 0x500
				      uint8_t id)
{
	int ret;
	const struct pinctrl_state *state;

	ret = pinctrl_lookup_state(config, id, &state);
    e10e:	aa01      	add	r2, sp, #4
	data->dev = dev;
    e110:	6037      	str	r7, [r6, #0]
    e112:	4648      	mov	r0, r9
    e114:	f002 fa1d 	bl	10552 <pinctrl_lookup_state>
	if (ret < 0) {
    e118:	1e05      	subs	r5, r0, #0
    e11a:	db56      	blt.n	e1ca <uarte_0_init+0xe6>
		return ret;
	}

	return pinctrl_apply_state_direct(config, state);
    e11c:	9b01      	ldr	r3, [sp, #4]
	return pinctrl_configure_pins(state->pins, state->pin_cnt, reg);
    e11e:	f8d9 2000 	ldr.w	r2, [r9]
    e122:	7919      	ldrb	r1, [r3, #4]
    e124:	6818      	ldr	r0, [r3, #0]
    e126:	f002 fa56 	bl	105d6 <pinctrl_configure_pins>
	if (err < 0) {
    e12a:	1e05      	subs	r5, r0, #0
    e12c:	db4d      	blt.n	e1ca <uarte_0_init+0xe6>
	err = uarte_nrfx_configure(dev, &data->uart_config);
    e12e:	1d31      	adds	r1, r6, #4
    e130:	4638      	mov	r0, r7
    e132:	f7ff ff2b 	bl	df8c <uarte_nrfx_configure>
	if (err) {
    e136:	4605      	mov	r5, r0
    e138:	2800      	cmp	r0, #0
    e13a:	d146      	bne.n	e1ca <uarte_0_init+0xe6>
	    cfg->flags & UARTE_CFG_FLAG_PPI_ENDTX) {
    e13c:	f8d8 3004 	ldr.w	r3, [r8, #4]
	if (IS_ENABLED(CONFIG_UART_ENHANCED_POLL_OUT) &&
    e140:	0799      	lsls	r1, r3, #30
    e142:	d519      	bpl.n	e178 <uarte_0_init+0x94>
	ret = gppi_channel_alloc(&data->ppi_ch_endtx);
    e144:	f106 0012 	add.w	r0, r6, #18
    e148:	f001 f8ae 	bl	f2a8 <nrfx_ppi_channel_alloc>
	if (ret != NRFX_SUCCESS) {
    e14c:	4b22      	ldr	r3, [pc, #136]	; (e1d8 <uarte_0_init+0xf4>)
    e14e:	4298      	cmp	r0, r3
    e150:	d13f      	bne.n	e1d2 <uarte_0_init+0xee>
	nrfx_gppi_channel_endpoints_setup(data->ppi_ch_endtx,
    e152:	7cb0      	ldrb	r0, [r6, #18]
    return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
    e154:	00c3      	lsls	r3, r0, #3
    e156:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    e15a:	f503 33f8 	add.w	r3, r3, #126976	; 0x1f000
    return (uint32_t)p_reg + (uint32_t)task;
    e15e:	f104 020c 	add.w	r2, r4, #12
    return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
    e162:	f504 7190 	add.w	r1, r4, #288	; 0x120
NRF_STATIC_INLINE void nrf_ppi_channel_endpoint_setup(NRF_PPI_Type *    p_reg,
                                                      nrf_ppi_channel_t channel,
                                                      uint32_t          eep,
                                                      uint32_t          tep)
{
    p_reg->CH[(uint32_t) channel].EEP = eep;
    e166:	f8c3 1510 	str.w	r1, [r3, #1296]	; 0x510
    p_reg->CH[(uint32_t) channel].TEP = tep;
    e16a:	f8c3 2514 	str.w	r2, [r3, #1300]	; 0x514
    p_reg->CHENSET = mask;
    e16e:	4a1b      	ldr	r2, [pc, #108]	; (e1dc <uarte_0_init+0xf8>)
	nrfx_gppi_channels_enable(BIT(data->ppi_ch_endtx));
    e170:	2301      	movs	r3, #1
    e172:	4083      	lsls	r3, r0
    e174:	f8c2 3504 	str.w	r3, [r2, #1284]	; 0x504
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
    e178:	2308      	movs	r3, #8
    e17a:	f8c4 3500 	str.w	r3, [r4, #1280]	; 0x500
		if (!cfg->disable_rx) {
    e17e:	f898 3008 	ldrb.w	r3, [r8, #8]
    e182:	b95b      	cbnz	r3, e19c <uarte_0_init+0xb8>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    e184:	f8c4 3110 	str.w	r3, [r4, #272]	; 0x110
    e188:	f8d4 3110 	ldr.w	r3, [r4, #272]	; 0x110
			nrf_uarte_rx_buffer_set(uarte, &data->rx_data, 1);
    e18c:	f106 0311 	add.w	r3, r6, #17

NRF_STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
                                               uint8_t *        p_buffer,
                                               size_t           length)
{
    p_reg->RXD.PTR    = (uint32_t)p_buffer;
    e190:	f8c4 3534 	str.w	r3, [r4, #1332]	; 0x534
    p_reg->RXD.MAXCNT = length;
    e194:	2301      	movs	r3, #1
    e196:	f8c4 3538 	str.w	r3, [r4, #1336]	; 0x538
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    e19a:	6023      	str	r3, [r4, #0]
	if (!(cfg->flags & UARTE_CFG_FLAG_PPI_ENDTX)) {
    e19c:	f8d8 3004 	ldr.w	r3, [r8, #4]
    e1a0:	079a      	lsls	r2, r3, #30
    p_reg->INTENSET = mask;
    e1a2:	bf5c      	itt	pl
    e1a4:	f44f 7280 	movpl.w	r2, #256	; 0x100
    e1a8:	f8c4 2304 	strpl.w	r2, [r4, #772]	; 0x304
	if (cfg->flags & UARTE_CFG_FLAG_LOW_POWER) {
    e1ac:	06db      	lsls	r3, r3, #27
    e1ae:	bf44      	itt	mi
    e1b0:	f44f 0380 	movmi.w	r3, #4194304	; 0x400000
    e1b4:	f8c4 3304 	strmi.w	r3, [r4, #772]	; 0x304
	nrf_uarte_tx_buffer_set(uarte, &data->char_out, 0);
    e1b8:	3610      	adds	r6, #16
    p_reg->TXD.MAXCNT = length;
    e1ba:	2300      	movs	r3, #0
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    e1bc:	f8c4 6544 	str.w	r6, [r4, #1348]	; 0x544
    p_reg->TXD.MAXCNT = length;
    e1c0:	f8c4 3548 	str.w	r3, [r4, #1352]	; 0x548
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    e1c4:	2301      	movs	r3, #1
    e1c6:	60a3      	str	r3, [r4, #8]
    e1c8:	60e3      	str	r3, [r4, #12]
UART_NRF_UARTE_DEVICE(0);
    e1ca:	4628      	mov	r0, r5
    e1cc:	b003      	add	sp, #12
    e1ce:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
		return -EIO;
    e1d2:	f06f 0504 	mvn.w	r5, #4
UART_NRF_UARTE_DEVICE(0);
    e1d6:	e7f8      	b.n	e1ca <uarte_0_init+0xe6>
    e1d8:	0bad0000 	.word	0x0bad0000
    e1dc:	4001f000 	.word	0x4001f000

0000e1e0 <uarte_nrfx_poll_out>:
{
    e1e0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	struct uarte_nrfx_data *data = dev->data;
    e1e2:	6906      	ldr	r6, [r0, #16]
{
    e1e4:	4605      	mov	r5, r0
    e1e6:	460f      	mov	r7, r1
	bool isr_mode = k_is_in_isr() || k_is_pre_kernel();
    e1e8:	f002 fae4 	bl	107b4 <k_is_in_isr>
    e1ec:	b910      	cbnz	r0, e1f4 <uarte_nrfx_poll_out+0x14>
	return !z_sys_post_kernel;
    e1ee:	4b2c      	ldr	r3, [pc, #176]	; (e2a0 <uarte_nrfx_poll_out+0xc0>)
	if (isr_mode) {
    e1f0:	781b      	ldrb	r3, [r3, #0]
    e1f2:	b983      	cbnz	r3, e216 <uarte_nrfx_poll_out+0x36>
	__asm__ volatile(
    e1f4:	f04f 0320 	mov.w	r3, #32
    e1f8:	f3ef 8411 	mrs	r4, BASEPRI
    e1fc:	f383 8812 	msr	BASEPRI_MAX, r3
    e200:	f3bf 8f6f 	isb	sy
			if (is_tx_ready(dev)) {
    e204:	6868      	ldr	r0, [r5, #4]
    e206:	f002 f95a 	bl	104be <is_tx_ready.isra.0>
    e20a:	bb28      	cbnz	r0, e258 <uarte_nrfx_poll_out+0x78>
	__asm__ volatile(
    e20c:	f384 8811 	msr	BASEPRI, r4
    e210:	f3bf 8f6f 	isb	sy
}
    e214:	e7ee      	b.n	e1f4 <uarte_nrfx_poll_out+0x14>
{
    e216:	2464      	movs	r4, #100	; 0x64
		NRFX_WAIT_FOR(is_tx_ready(dev), 100, 1, res);
    e218:	6868      	ldr	r0, [r5, #4]
    e21a:	f002 f950 	bl	104be <is_tx_ready.isra.0>
    e21e:	b970      	cbnz	r0, e23e <uarte_nrfx_poll_out+0x5e>
    e220:	2001      	movs	r0, #1
    e222:	f002 fa77 	bl	10714 <nrfx_busy_wait>
    e226:	3c01      	subs	r4, #1
    e228:	d1f6      	bne.n	e218 <uarte_nrfx_poll_out+0x38>
    e22a:	2100      	movs	r1, #0
    e22c:	2021      	movs	r0, #33	; 0x21
    e22e:	f001 fce1 	bl	fbf4 <z_impl_k_sleep>
	return k_sleep(Z_TIMEOUT_MS(ms));
    e232:	e7f0      	b.n	e216 <uarte_nrfx_poll_out+0x36>
	__asm__ volatile(
    e234:	f384 8811 	msr	BASEPRI, r4
    e238:	f3bf 8f6f 	isb	sy
}
    e23c:	e7f5      	b.n	e22a <uarte_nrfx_poll_out+0x4a>
	__asm__ volatile(
    e23e:	f04f 0320 	mov.w	r3, #32
    e242:	f3ef 8411 	mrs	r4, BASEPRI
    e246:	f383 8812 	msr	BASEPRI_MAX, r3
    e24a:	f3bf 8f6f 	isb	sy
			if (is_tx_ready(dev)) {
    e24e:	6868      	ldr	r0, [r5, #4]
    e250:	f002 f935 	bl	104be <is_tx_ready.isra.0>
    e254:	2800      	cmp	r0, #0
    e256:	d0ed      	beq.n	e234 <uarte_nrfx_poll_out+0x54>
	data->char_out = c;
    e258:	f806 7f10 	strb.w	r7, [r6, #16]!
	tx_start(dev, &data->char_out, 1);
    e25c:	6869      	ldr	r1, [r5, #4]
	return config->uarte_regs;
    e25e:	680b      	ldr	r3, [r1, #0]
    p_reg->TXD.MAXCNT = length;
    e260:	2201      	movs	r2, #1
    p_reg->TXD.PTR    = (uint32_t)p_buffer;
    e262:	f8c3 6544 	str.w	r6, [r3, #1348]	; 0x544
    p_reg->TXD.MAXCNT = length;
    e266:	f8c3 2548 	str.w	r2, [r3, #1352]	; 0x548
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    e26a:	2200      	movs	r2, #0
    e26c:	f8c3 2120 	str.w	r2, [r3, #288]	; 0x120
    e270:	f8d3 0120 	ldr.w	r0, [r3, #288]	; 0x120
    e274:	f8c3 2158 	str.w	r2, [r3, #344]	; 0x158
    e278:	f8d3 2158 	ldr.w	r2, [r3, #344]	; 0x158
	if (config->flags & UARTE_CFG_FLAG_LOW_POWER) {
    e27c:	684a      	ldr	r2, [r1, #4]
    e27e:	06d2      	lsls	r2, r2, #27
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
    e280:	bf41      	itttt	mi
    e282:	2208      	movmi	r2, #8
    e284:	f8c3 2500 	strmi.w	r2, [r3, #1280]	; 0x500
    p_reg->INTENSET = mask;
    e288:	f44f 0280 	movmi.w	r2, #4194304	; 0x400000
    e28c:	f8c3 2304 	strmi.w	r2, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    e290:	2201      	movs	r2, #1
    e292:	609a      	str	r2, [r3, #8]
	__asm__ volatile(
    e294:	f384 8811 	msr	BASEPRI, r4
    e298:	f3bf 8f6f 	isb	sy
}
    e29c:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    e29e:	bf00      	nop
    e2a0:	20000782 	.word	0x20000782

0000e2a4 <compare_int_lock>:
	return 0;
#endif
}

static bool compare_int_lock(int32_t chan)
{
    e2a4:	b510      	push	{r4, lr}
	atomic_val_t prev = atomic_and(&int_mask, ~BIT(chan));
    e2a6:	2301      	movs	r3, #1
    e2a8:	4083      	lsls	r3, r0
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    e2aa:	4a11      	ldr	r2, [pc, #68]	; (e2f0 <compare_int_lock+0x4c>)
    e2ac:	f3bf 8f5b 	dmb	ish
    e2b0:	43dc      	mvns	r4, r3
    e2b2:	e852 1f00 	ldrex	r1, [r2]
    e2b6:	ea01 0c04 	and.w	ip, r1, r4
    e2ba:	e842 ce00 	strex	lr, ip, [r2]
    e2be:	f1be 0f00 	cmp.w	lr, #0
    e2c2:	d1f6      	bne.n	e2b2 <compare_int_lock+0xe>
    e2c4:	f3bf 8f5b 	dmb	ish

	nrf_rtc_int_disable(RTC, RTC_CHANNEL_INT_MASK(chan));
    e2c8:	f44f 3280 	mov.w	r2, #65536	; 0x10000
    e2cc:	fa02 f000 	lsl.w	r0, r2, r0
    p_reg->INTENSET = mask;
}

NRF_STATIC_INLINE void nrf_rtc_int_disable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->INTENCLR = mask;
    e2d0:	f102 4280 	add.w	r2, r2, #1073741824	; 0x40000000
    e2d4:	f502 5280 	add.w	r2, r2, #4096	; 0x1000
    e2d8:	f8c2 0308 	str.w	r0, [r2, #776]	; 0x308
  __ASM volatile ("dmb 0xF":::"memory");
    e2dc:	f3bf 8f5f 	dmb	sy
  __ASM volatile ("isb 0xF":::"memory");
    e2e0:	f3bf 8f6f 	isb	sy

	__DMB();
	__ISB();

	return prev & BIT(chan);
    e2e4:	420b      	tst	r3, r1
}
    e2e6:	bf14      	ite	ne
    e2e8:	2001      	movne	r0, #1
    e2ea:	2000      	moveq	r0, #0
    e2ec:	bd10      	pop	{r4, pc}
    e2ee:	bf00      	nop
    e2f0:	20000280 	.word	0x20000280

0000e2f4 <sys_clock_timeout_handler>:
static void sys_clock_timeout_handler(int32_t chan,
				      uint64_t expire_time,
				      void *user_data)
{
	uint32_t cc_value = absolute_time_to_cc(expire_time);
	uint64_t dticks = (expire_time - last_count) / CYC_PER_TICK;
    e2f4:	4919      	ldr	r1, [pc, #100]	; (e35c <sys_clock_timeout_handler+0x68>)
{
    e2f6:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    e2f8:	4604      	mov	r4, r0
	return absolute_time & COUNTER_MAX;
    e2fa:	f022 457f 	bic.w	r5, r2, #4278190080	; 0xff000000
	uint64_t dticks = (expire_time - last_count) / CYC_PER_TICK;
    e2fe:	6808      	ldr	r0, [r1, #0]

	last_count += dticks * CYC_PER_TICK;
    e300:	e9c1 2300 	strd	r2, r3, [r1]
	return (cc_value >= ANCHOR_RANGE_START) && (cc_value < ANCHOR_RANGE_END);
    e304:	f5a5 1300 	sub.w	r3, r5, #2097152	; 0x200000
	uint64_t dticks = (expire_time - last_count) / CYC_PER_TICK;
    e308:	1a10      	subs	r0, r2, r0
	if (in_anchor_range(cc_value)) {
    e30a:	f5b3 0f40 	cmp.w	r3, #12582912	; 0xc00000
    e30e:	d222      	bcs.n	e356 <sys_clock_timeout_handler+0x62>
		anchor = (((uint64_t)overflow_cnt) << COUNTER_BIT_WIDTH) + cc_value;
    e310:	4b13      	ldr	r3, [pc, #76]	; (e360 <sys_clock_timeout_handler+0x6c>)
    e312:	681b      	ldr	r3, [r3, #0]
    e314:	0a1a      	lsrs	r2, r3, #8
    e316:	061b      	lsls	r3, r3, #24
    e318:	195e      	adds	r6, r3, r5
    e31a:	4b12      	ldr	r3, [pc, #72]	; (e364 <sys_clock_timeout_handler+0x70>)
    e31c:	f142 0700 	adc.w	r7, r2, #0
    e320:	e9c3 6700 	strd	r6, r7, [r3]
		return true;
    e324:	2601      	movs	r6, #1
		 */
		compare_set(chan, last_count + CYC_PER_TICK,
					  sys_clock_timeout_handler, NULL);
	}

	sys_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
    e326:	f001 fdb5 	bl	fe94 <sys_clock_announce>
    return p_reg->CC[ch];
    e32a:	00a3      	lsls	r3, r4, #2
    e32c:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    e330:	f503 3388 	add.w	r3, r3, #69632	; 0x11000
    e334:	f8d3 2540 	ldr.w	r2, [r3, #1344]	; 0x540
			   (int32_t)dticks : (dticks > 0));

	if (cc_value == get_comparator(chan)) {
    e338:	42aa      	cmp	r2, r5
    e33a:	d10b      	bne.n	e354 <sys_clock_timeout_handler+0x60>
		 * If anchor was updated we can enable same CC value to trigger
		 * interrupt after full cycle. Else set event in anchor update
		 * range. Since anchor was not updated we know that it's very
		 * far from mid point so setting is done without any protection.
		 */
		if (!anchor_updated) {
    e33c:	b91e      	cbnz	r6, e346 <sys_clock_timeout_handler+0x52>
    p_reg->CC[ch] = cc_val;
    e33e:	f44f 0200 	mov.w	r2, #8388608	; 0x800000
    e342:	f8c3 2540 	str.w	r2, [r3, #1344]	; 0x540
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
}

NRF_STATIC_INLINE void nrf_rtc_event_enable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->EVTENSET = mask;
    e346:	4b08      	ldr	r3, [pc, #32]	; (e368 <sys_clock_timeout_handler+0x74>)
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    e348:	f44f 3080 	mov.w	r0, #65536	; 0x10000
    e34c:	fa00 f404 	lsl.w	r4, r0, r4
    e350:	f8c3 4344 	str.w	r4, [r3, #836]	; 0x344
			set_comparator(chan, COUNTER_HALF_SPAN);
		}
		event_enable(chan);
	}
}
    e354:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	return false;
    e356:	2600      	movs	r6, #0
    e358:	e7e5      	b.n	e326 <sys_clock_timeout_handler+0x32>
    e35a:	bf00      	nop
    e35c:	200000b0 	.word	0x200000b0
    e360:	20000284 	.word	0x20000284
    e364:	20000098 	.word	0x20000098
    e368:	40011000 	.word	0x40011000

0000e36c <compare_int_unlock>:
	if (key) {
    e36c:	b319      	cbz	r1, e3b6 <compare_int_unlock+0x4a>
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    e36e:	f3bf 8f5b 	dmb	ish
		atomic_or(&int_mask, BIT(chan));
    e372:	2301      	movs	r3, #1
    e374:	4a10      	ldr	r2, [pc, #64]	; (e3b8 <compare_int_unlock+0x4c>)
    e376:	4083      	lsls	r3, r0
    e378:	e852 1f00 	ldrex	r1, [r2]
    e37c:	4319      	orrs	r1, r3
    e37e:	e842 1c00 	strex	ip, r1, [r2]
    e382:	f1bc 0f00 	cmp.w	ip, #0
    e386:	d1f7      	bne.n	e378 <compare_int_unlock+0xc>
    e388:	f3bf 8f5b 	dmb	ish
    p_reg->INTENSET = mask;
    e38c:	4a0b      	ldr	r2, [pc, #44]	; (e3bc <compare_int_unlock+0x50>)
		nrf_rtc_int_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    e38e:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    e392:	4083      	lsls	r3, r0
    e394:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
	return __atomic_load_n(target, __ATOMIC_SEQ_CST);
    e398:	4b09      	ldr	r3, [pc, #36]	; (e3c0 <compare_int_unlock+0x54>)
    e39a:	f3bf 8f5b 	dmb	ish
    e39e:	681b      	ldr	r3, [r3, #0]
    e3a0:	f3bf 8f5b 	dmb	ish
		if (atomic_get(&force_isr_mask) & BIT(chan)) {
    e3a4:	fa23 f000 	lsr.w	r0, r3, r0
    e3a8:	07c3      	lsls	r3, r0, #31
    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    e3aa:	bf42      	ittt	mi
    e3ac:	4b05      	ldrmi	r3, [pc, #20]	; (e3c4 <compare_int_unlock+0x58>)
    e3ae:	f44f 3200 	movmi.w	r2, #131072	; 0x20000
    e3b2:	f8c3 2100 	strmi.w	r2, [r3, #256]	; 0x100
}
    e3b6:	4770      	bx	lr
    e3b8:	20000280 	.word	0x20000280
    e3bc:	40011000 	.word	0x40011000
    e3c0:	2000027c 	.word	0x2000027c
    e3c4:	e000e100 	.word	0xe000e100

0000e3c8 <z_nrf_rtc_timer_read>:
	uint64_t val = ((uint64_t)overflow_cnt) << COUNTER_BIT_WIDTH;
    e3c8:	4b0d      	ldr	r3, [pc, #52]	; (e400 <z_nrf_rtc_timer_read+0x38>)
    e3ca:	6818      	ldr	r0, [r3, #0]
    e3cc:	0a01      	lsrs	r1, r0, #8
    e3ce:	0600      	lsls	r0, r0, #24
  __ASM volatile ("dmb 0xF":::"memory");
    e3d0:	f3bf 8f5f 	dmb	sy
     return p_reg->COUNTER;
    e3d4:	4b0b      	ldr	r3, [pc, #44]	; (e404 <z_nrf_rtc_timer_read+0x3c>)
    e3d6:	f8d3 3504 	ldr.w	r3, [r3, #1284]	; 0x504
	val += cntr;
    e3da:	1818      	adds	r0, r3, r0
    e3dc:	f141 0100 	adc.w	r1, r1, #0
	if (cntr < OVERFLOW_RISK_RANGE_END) {
    e3e0:	f5b3 1f80 	cmp.w	r3, #1048576	; 0x100000
    e3e4:	d20a      	bcs.n	e3fc <z_nrf_rtc_timer_read+0x34>
		if (val < anchor) {
    e3e6:	4b08      	ldr	r3, [pc, #32]	; (e408 <z_nrf_rtc_timer_read+0x40>)
    e3e8:	e9d3 2300 	ldrd	r2, r3, [r3]
    e3ec:	4290      	cmp	r0, r2
    e3ee:	eb71 0303 	sbcs.w	r3, r1, r3
    e3f2:	d203      	bcs.n	e3fc <z_nrf_rtc_timer_read+0x34>
			val += COUNTER_SPAN;
    e3f4:	f110 7080 	adds.w	r0, r0, #16777216	; 0x1000000
    e3f8:	f141 0100 	adc.w	r1, r1, #0
}
    e3fc:	4770      	bx	lr
    e3fe:	bf00      	nop
    e400:	20000284 	.word	0x20000284
    e404:	40011000 	.word	0x40011000
    e408:	20000098 	.word	0x20000098

0000e40c <compare_set>:
{
    e40c:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    e410:	b085      	sub	sp, #20
    e412:	4616      	mov	r6, r2
    e414:	4698      	mov	r8, r3
    e416:	4605      	mov	r5, r0
	key = compare_int_lock(chan);
    e418:	f7ff ff44 	bl	e2a4 <compare_int_lock>
    e41c:	9000      	str	r0, [sp, #0]
	uint64_t curr_time = z_nrf_rtc_timer_read();
    e41e:	f7ff ffd3 	bl	e3c8 <z_nrf_rtc_timer_read>
	if (curr_time < target_time) {
    e422:	42b0      	cmp	r0, r6
    e424:	eb71 0308 	sbcs.w	r3, r1, r8
    e428:	d278      	bcs.n	e51c <compare_set+0x110>
		if (target_time - curr_time > COUNTER_SPAN) {
    e42a:	4b46      	ldr	r3, [pc, #280]	; (e544 <compare_set+0x138>)
    e42c:	1a30      	subs	r0, r6, r0
    e42e:	eb68 0101 	sbc.w	r1, r8, r1
    e432:	4298      	cmp	r0, r3
    e434:	f171 0300 	sbcs.w	r3, r1, #0
    e438:	f080 8081 	bcs.w	e53e <compare_set+0x132>
		if (target_time != cc_data[chan].target_time) {
    e43c:	4b42      	ldr	r3, [pc, #264]	; (e548 <compare_set+0x13c>)
    e43e:	eb03 1305 	add.w	r3, r3, r5, lsl #4
    e442:	e9d3 ab02 	ldrd	sl, fp, [r3, #8]
    e446:	45d8      	cmp	r8, fp
    e448:	bf08      	it	eq
    e44a:	4556      	cmpeq	r6, sl
    e44c:	d051      	beq.n	e4f2 <compare_set+0xe6>
    e44e:	ea4f 0985 	mov.w	r9, r5, lsl #2
    e452:	f109 4980 	add.w	r9, r9, #1073741824	; 0x40000000
	nrf_rtc_event_clear(RTC, RTC_CHANNEL_EVENT_ADDR(chan));
    e456:	f105 0750 	add.w	r7, r5, #80	; 0x50
    e45a:	f509 3988 	add.w	r9, r9, #69632	; 0x11000
    e45e:	00bf      	lsls	r7, r7, #2
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    e460:	f44f 3180 	mov.w	r1, #65536	; 0x10000
    e464:	fa01 f305 	lsl.w	r3, r1, r5
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    e468:	b2bf      	uxth	r7, r7
	return absolute_time & COUNTER_MAX;
    e46a:	f026 427f 	bic.w	r2, r6, #4278190080	; 0xff000000
    e46e:	f107 4780 	add.w	r7, r7, #1073741824	; 0x40000000
	nrf_rtc_event_enable(RTC, RTC_CHANNEL_INT_MASK(chan));
    e472:	9301      	str	r3, [sp, #4]
    return p_reg->CC[ch];
    e474:	f8d9 0540 	ldr.w	r0, [r9, #1344]	; 0x540
     return p_reg->COUNTER;
    e478:	4b34      	ldr	r3, [pc, #208]	; (e54c <compare_set+0x140>)
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    e47a:	f507 3788 	add.w	r7, r7, #69632	; 0x11000
	uint32_t cc_val = abs_val & COUNTER_MAX;
    e47e:	4614      	mov	r4, r2
     return p_reg->COUNTER;
    e480:	f8d3 1504 	ldr.w	r1, [r3, #1284]	; 0x504
	return (a - b) & COUNTER_MAX;
    e484:	1a40      	subs	r0, r0, r1
    e486:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
	nrf_rtc_cc_set(RTC, chan, cyc & COUNTER_MAX);
    e48a:	f021 4c7f 	bic.w	ip, r1, #4278190080	; 0xff000000
		if (counter_sub(prev_cc, now) == 1) {
    e48e:	2801      	cmp	r0, #1
    p_reg->CC[ch] = cc_val;
    e490:	f8c9 c540 	str.w	ip, [r9, #1344]	; 0x540
    e494:	d107      	bne.n	e4a6 <compare_set+0x9a>
    e496:	e9cd 2102 	strd	r2, r1, [sp, #8]
	z_impl_k_busy_wait(usec_to_wait);
    e49a:	2013      	movs	r0, #19
    e49c:	f002 fa7d 	bl	1099a <z_impl_k_busy_wait>
    e4a0:	e9dd 2102 	ldrd	r2, r1, [sp, #8]
    e4a4:	4b29      	ldr	r3, [pc, #164]	; (e54c <compare_set+0x140>)
		if (counter_sub(cc_val, now + 2) > COUNTER_HALF_SPAN) {
    e4a6:	f101 0c02 	add.w	ip, r1, #2
	return (a - b) & COUNTER_MAX;
    e4aa:	eba4 000c 	sub.w	r0, r4, ip
    e4ae:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
			cc_val = now + 2;
    e4b2:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    e4b6:	bf88      	it	hi
    e4b8:	4664      	movhi	r4, ip
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    e4ba:	2000      	movs	r0, #0
    e4bc:	6038      	str	r0, [r7, #0]
    e4be:	6838      	ldr	r0, [r7, #0]
    p_reg->EVTENSET = mask;
    e4c0:	9801      	ldr	r0, [sp, #4]
    e4c2:	f8c3 0344 	str.w	r0, [r3, #836]	; 0x344
	nrf_rtc_cc_set(RTC, chan, cyc & COUNTER_MAX);
    e4c6:	f024 407f 	bic.w	r0, r4, #4278190080	; 0xff000000
    p_reg->CC[ch] = cc_val;
    e4ca:	f8c9 0540 	str.w	r0, [r9, #1344]	; 0x540
     return p_reg->COUNTER;
    e4ce:	f8d3 0504 	ldr.w	r0, [r3, #1284]	; 0x504
		 (counter_sub(cc_val, now2 + 2) > COUNTER_HALF_SPAN));
    e4d2:	4281      	cmp	r1, r0
    e4d4:	d006      	beq.n	e4e4 <compare_set+0xd8>
	return (a - b) & COUNTER_MAX;
    e4d6:	1a20      	subs	r0, r4, r0
    e4d8:	3802      	subs	r0, #2
    e4da:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
	} while ((now2 != now) &&
    e4de:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    e4e2:	d819      	bhi.n	e518 <compare_set+0x10c>
	return (a - b) & COUNTER_MAX;
    e4e4:	1aa4      	subs	r4, r4, r2
    e4e6:	f024 447f 	bic.w	r4, r4, #4278190080	; 0xff000000
			target_time += counter_sub(cc_set, cc_value);
    e4ea:	eb14 0a06 	adds.w	sl, r4, r6
    e4ee:	f148 0b00 	adc.w	fp, r8, #0
	cc_data[chan].target_time = target_time;
    e4f2:	4915      	ldr	r1, [pc, #84]	; (e548 <compare_set+0x13c>)
	cc_data[chan].callback = handler;
    e4f4:	980e      	ldr	r0, [sp, #56]	; 0x38
	cc_data[chan].target_time = target_time;
    e4f6:	012b      	lsls	r3, r5, #4
    e4f8:	eb01 1205 	add.w	r2, r1, r5, lsl #4
    e4fc:	e9c2 ab02 	strd	sl, fp, [r2, #8]
	cc_data[chan].callback = handler;
    e500:	50c8      	str	r0, [r1, r3]
	cc_data[chan].user_context = user_data;
    e502:	9b0f      	ldr	r3, [sp, #60]	; 0x3c
    e504:	6053      	str	r3, [r2, #4]
	return ret;
    e506:	2400      	movs	r4, #0
	compare_int_unlock(chan, key);
    e508:	4628      	mov	r0, r5
    e50a:	9900      	ldr	r1, [sp, #0]
    e50c:	f7ff ff2e 	bl	e36c <compare_int_unlock>
}
    e510:	4620      	mov	r0, r4
    e512:	b005      	add	sp, #20
    e514:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    e518:	4620      	mov	r0, r4
    e51a:	e7b1      	b.n	e480 <compare_set+0x74>
		atomic_or(&force_isr_mask, BIT(chan));
    e51c:	2301      	movs	r3, #1
	return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
    e51e:	4a0c      	ldr	r2, [pc, #48]	; (e550 <compare_set+0x144>)
    e520:	f3bf 8f5b 	dmb	ish
    e524:	40ab      	lsls	r3, r5
    e526:	e852 1f00 	ldrex	r1, [r2]
    e52a:	4319      	orrs	r1, r3
    e52c:	e842 1000 	strex	r0, r1, [r2]
    e530:	2800      	cmp	r0, #0
    e532:	d1f8      	bne.n	e526 <compare_set+0x11a>
    e534:	f3bf 8f5b 	dmb	ish
    e538:	46b2      	mov	sl, r6
    e53a:	46c3      	mov	fp, r8
    e53c:	e7d9      	b.n	e4f2 <compare_set+0xe6>
			return -EINVAL;
    e53e:	f06f 0415 	mvn.w	r4, #21
    e542:	e7e1      	b.n	e508 <compare_set+0xfc>
    e544:	01000001 	.word	0x01000001
    e548:	200000a0 	.word	0x200000a0
    e54c:	40011000 	.word	0x40011000
    e550:	2000027c 	.word	0x2000027c

0000e554 <sys_clock_driver_init>:
{
	return (uint32_t)z_nrf_rtc_timer_read();
}

static int sys_clock_driver_init(const struct device *dev)
{
    e554:	b573      	push	{r0, r1, r4, r5, r6, lr}
			CLOCK_CONTROL_NRF_LF_START_STABLE);

	/* TODO: replace with counter driver to access RTC */
	nrf_rtc_prescaler_set(RTC, 0);
	for (int32_t chan = 0; chan < CHAN_COUNT; chan++) {
		cc_data[chan].target_time = TARGET_TIME_INVALID;
    e556:	4b19      	ldr	r3, [pc, #100]	; (e5bc <sys_clock_driver_init+0x68>)
    p_reg->PRESCALER = val;
    e558:	4d19      	ldr	r5, [pc, #100]	; (e5c0 <sys_clock_driver_init+0x6c>)
    e55a:	2400      	movs	r4, #0
    e55c:	f04f 30ff 	mov.w	r0, #4294967295
    e560:	f04f 31ff 	mov.w	r1, #4294967295
    e564:	f8c5 4508 	str.w	r4, [r5, #1288]	; 0x508
    e568:	e9c3 0102 	strd	r0, r1, [r3, #8]
    p_reg->INTENSET = mask;
    e56c:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    e570:	f8c5 3304 	str.w	r3, [r5, #772]	; 0x304
    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    e574:	4b13      	ldr	r3, [pc, #76]	; (e5c4 <sys_clock_driver_init+0x70>)
    e576:	2602      	movs	r6, #2
    e578:	f44f 3200 	mov.w	r2, #131072	; 0x20000

	nrf_rtc_int_enable(RTC, NRF_RTC_INT_OVERFLOW_MASK);

	NVIC_ClearPendingIRQ(RTC_IRQn);

	IRQ_CONNECT(RTC_IRQn, DT_IRQ(DT_NODELABEL(RTC_LABEL), priority),
    e57c:	2101      	movs	r1, #1
    e57e:	f8c5 6304 	str.w	r6, [r5, #772]	; 0x304
    e582:	2011      	movs	r0, #17
    e584:	f8c3 2180 	str.w	r2, [r3, #384]	; 0x180
    e588:	4622      	mov	r2, r4
    e58a:	f7fe fe75 	bl	d278 <z_arm_irq_priority_set>
		    rtc_nrf_isr, 0, 0);
	irq_enable(RTC_IRQn);
    e58e:	2011      	movs	r0, #17
    e590:	f7fe fe54 	bl	d23c <arch_irq_enable>

	nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_CLEAR);
	nrf_rtc_task_trigger(RTC, NRF_RTC_TASK_START);

	int_mask = BIT_MASK(CHAN_COUNT);
    e594:	4a0c      	ldr	r2, [pc, #48]	; (e5c8 <sys_clock_driver_init+0x74>)
    *(__IO uint32_t *)((uint32_t)p_reg + task) = 1;
    e596:	2301      	movs	r3, #1
    e598:	60ab      	str	r3, [r5, #8]
    e59a:	602b      	str	r3, [r5, #0]
    e59c:	6013      	str	r3, [r2, #0]

	uint32_t initial_timeout = IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
		(COUNTER_HALF_SPAN - 1) :
		(counter() + CYC_PER_TICK);

	compare_set(0, initial_timeout, sys_clock_timeout_handler, NULL);
    e59e:	4b0b      	ldr	r3, [pc, #44]	; (e5cc <sys_clock_driver_init+0x78>)
    e5a0:	4a0b      	ldr	r2, [pc, #44]	; (e5d0 <sys_clock_driver_init+0x7c>)
    e5a2:	9300      	str	r3, [sp, #0]
    e5a4:	9401      	str	r4, [sp, #4]
    e5a6:	2300      	movs	r3, #0
    e5a8:	4620      	mov	r0, r4
    e5aa:	f7ff ff2f 	bl	e40c <compare_set>

	z_nrf_clock_control_lf_on(mode);
    e5ae:	4630      	mov	r0, r6
    e5b0:	f7ff fafa 	bl	dba8 <z_nrf_clock_control_lf_on>

	return 0;
}
    e5b4:	4620      	mov	r0, r4
    e5b6:	b002      	add	sp, #8
    e5b8:	bd70      	pop	{r4, r5, r6, pc}
    e5ba:	bf00      	nop
    e5bc:	200000a0 	.word	0x200000a0
    e5c0:	40011000 	.word	0x40011000
    e5c4:	e000e100 	.word	0xe000e100
    e5c8:	20000280 	.word	0x20000280
    e5cc:	0000e2f5 	.word	0x0000e2f5
    e5d0:	007fffff 	.word	0x007fffff

0000e5d4 <rtc_nrf_isr>:
{
    e5d4:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
    return p_reg->INTENSET & mask;
    e5d8:	4c35      	ldr	r4, [pc, #212]	; (e6b0 <rtc_nrf_isr+0xdc>)
    e5da:	f8d4 3304 	ldr.w	r3, [r4, #772]	; 0x304
	if (nrf_rtc_int_enable_check(RTC, NRF_RTC_INT_OVERFLOW_MASK) &&
    e5de:	079a      	lsls	r2, r3, #30
    e5e0:	d50b      	bpl.n	e5fa <rtc_nrf_isr+0x26>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    e5e2:	f8d4 3104 	ldr.w	r3, [r4, #260]	; 0x104
    e5e6:	b143      	cbz	r3, e5fa <rtc_nrf_isr+0x26>
		overflow_cnt++;
    e5e8:	4a32      	ldr	r2, [pc, #200]	; (e6b4 <rtc_nrf_isr+0xe0>)
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    e5ea:	2300      	movs	r3, #0
    e5ec:	f8c4 3104 	str.w	r3, [r4, #260]	; 0x104
    e5f0:	f8d4 3104 	ldr.w	r3, [r4, #260]	; 0x104
    e5f4:	6813      	ldr	r3, [r2, #0]
    e5f6:	3301      	adds	r3, #1
    e5f8:	6013      	str	r3, [r2, #0]
	__asm__ volatile(
    e5fa:	f04f 0320 	mov.w	r3, #32
    e5fe:	f3ef 8211 	mrs	r2, BASEPRI
    e602:	f383 8812 	msr	BASEPRI_MAX, r3
    e606:	f3bf 8f6f 	isb	sy
    return p_reg->INTENSET & mask;
    e60a:	f8d4 3304 	ldr.w	r3, [r4, #772]	; 0x304
	if (nrf_rtc_int_enable_check(RTC, RTC_CHANNEL_INT_MASK(chan))) {
    e60e:	03db      	lsls	r3, r3, #15
    e610:	d512      	bpl.n	e638 <rtc_nrf_isr+0x64>
	return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
    e612:	f3bf 8f5b 	dmb	ish
    e616:	4b28      	ldr	r3, [pc, #160]	; (e6b8 <rtc_nrf_isr+0xe4>)
    e618:	e853 1f00 	ldrex	r1, [r3]
    e61c:	f021 0001 	bic.w	r0, r1, #1
    e620:	e843 0600 	strex	r6, r0, [r3]
    e624:	2e00      	cmp	r6, #0
    e626:	d1f7      	bne.n	e618 <rtc_nrf_isr+0x44>
    e628:	f3bf 8f5b 	dmb	ish
		result = atomic_and(&force_isr_mask, ~BIT(chan)) ||
    e62c:	2900      	cmp	r1, #0
    e62e:	d136      	bne.n	e69e <rtc_nrf_isr+0xca>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    e630:	f8d4 3140 	ldr.w	r3, [r4, #320]	; 0x140
		if (result) {
    e634:	2b00      	cmp	r3, #0
    e636:	d132      	bne.n	e69e <rtc_nrf_isr+0xca>
{
    e638:	2300      	movs	r3, #0
	__asm__ volatile(
    e63a:	f382 8811 	msr	BASEPRI, r2
    e63e:	f3bf 8f6f 	isb	sy
	if (channel_processing_check_and_clear(chan)) {
    e642:	b34b      	cbz	r3, e698 <rtc_nrf_isr+0xc4>
		curr_time = z_nrf_rtc_timer_read();
    e644:	f7ff fec0 	bl	e3c8 <z_nrf_rtc_timer_read>
	__asm__ volatile(
    e648:	f04f 0320 	mov.w	r3, #32
    e64c:	f3ef 8c11 	mrs	ip, BASEPRI
    e650:	f383 8812 	msr	BASEPRI_MAX, r3
    e654:	f3bf 8f6f 	isb	sy
		expire_time = cc_data[chan].target_time;
    e658:	4b18      	ldr	r3, [pc, #96]	; (e6bc <rtc_nrf_isr+0xe8>)
    e65a:	e9d3 6702 	ldrd	r6, r7, [r3, #8]
		if (curr_time >= expire_time) {
    e65e:	42b0      	cmp	r0, r6
    e660:	eb71 0207 	sbcs.w	r2, r1, r7
    e664:	f04f 0200 	mov.w	r2, #0
    e668:	d320      	bcc.n	e6ac <rtc_nrf_isr+0xd8>
			cc_data[chan].target_time = TARGET_TIME_INVALID;
    e66a:	f04f 38ff 	mov.w	r8, #4294967295
    e66e:	f04f 39ff 	mov.w	r9, #4294967295
			user_context = cc_data[chan].user_context;
    e672:	e9d3 1500 	ldrd	r1, r5, [r3]
			cc_data[chan].target_time = TARGET_TIME_INVALID;
    e676:	e9c3 8902 	strd	r8, r9, [r3, #8]
			cc_data[chan].callback = NULL;
    e67a:	601a      	str	r2, [r3, #0]
}

NRF_STATIC_INLINE void nrf_rtc_event_disable(NRF_RTC_Type * p_reg, uint32_t mask)
{
    p_reg->EVTENCLR = mask;
    e67c:	f44f 3380 	mov.w	r3, #65536	; 0x10000
    e680:	f8c4 3348 	str.w	r3, [r4, #840]	; 0x348
	__asm__ volatile(
    e684:	f38c 8811 	msr	BASEPRI, ip
    e688:	f3bf 8f6f 	isb	sy
		if (handler) {
    e68c:	b121      	cbz	r1, e698 <rtc_nrf_isr+0xc4>
			handler(chan, expire_time, user_context);
    e68e:	9500      	str	r5, [sp, #0]
    e690:	4632      	mov	r2, r6
    e692:	463b      	mov	r3, r7
    e694:	2000      	movs	r0, #0
    e696:	4788      	blx	r1
}
    e698:	b003      	add	sp, #12
    e69a:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
    e69e:	2300      	movs	r3, #0
    e6a0:	f8c4 3140 	str.w	r3, [r4, #320]	; 0x140
    e6a4:	f8d4 3140 	ldr.w	r3, [r4, #320]	; 0x140
		result = atomic_and(&force_isr_mask, ~BIT(chan)) ||
    e6a8:	2301      	movs	r3, #1
}
    e6aa:	e7c6      	b.n	e63a <rtc_nrf_isr+0x66>
		z_nrf_rtc_timer_compare_handler_t handler = NULL;
    e6ac:	4611      	mov	r1, r2
    e6ae:	e7e9      	b.n	e684 <rtc_nrf_isr+0xb0>
    e6b0:	40011000 	.word	0x40011000
    e6b4:	20000284 	.word	0x20000284
    e6b8:	2000027c 	.word	0x2000027c
    e6bc:	200000a0 	.word	0x200000a0

0000e6c0 <sys_clock_set_timeout>:
	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    e6c0:	1c43      	adds	r3, r0, #1
{
    e6c2:	b513      	push	{r0, r1, r4, lr}
	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    e6c4:	d021      	beq.n	e70a <sys_clock_set_timeout+0x4a>
	ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
    e6c6:	2801      	cmp	r0, #1
    e6c8:	dd21      	ble.n	e70e <sys_clock_set_timeout+0x4e>
    e6ca:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    e6ce:	da20      	bge.n	e712 <sys_clock_set_timeout+0x52>
    e6d0:	1e44      	subs	r4, r0, #1
	uint32_t unannounced = z_nrf_rtc_timer_read() - last_count;
    e6d2:	f7ff fe79 	bl	e3c8 <z_nrf_rtc_timer_read>
    e6d6:	4b10      	ldr	r3, [pc, #64]	; (e718 <sys_clock_set_timeout+0x58>)
    e6d8:	e9d3 1300 	ldrd	r1, r3, [r3]
    e6dc:	1a40      	subs	r0, r0, r1
		ticks = 0;
    e6de:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
    e6e2:	bf28      	it	cs
    e6e4:	2400      	movcs	r4, #0
	cyc = ticks * CYC_PER_TICK + 1 + unannounced;
    e6e6:	3001      	adds	r0, #1
    e6e8:	1902      	adds	r2, r0, r4
	uint64_t target_time = cyc + last_count;
    e6ea:	480c      	ldr	r0, [pc, #48]	; (e71c <sys_clock_set_timeout+0x5c>)
    e6ec:	4282      	cmp	r2, r0
    e6ee:	bf28      	it	cs
    e6f0:	4602      	movcs	r2, r0
    e6f2:	1852      	adds	r2, r2, r1
    e6f4:	f04f 0000 	mov.w	r0, #0
	compare_set(0, target_time, sys_clock_timeout_handler, NULL);
    e6f8:	4909      	ldr	r1, [pc, #36]	; (e720 <sys_clock_set_timeout+0x60>)
    e6fa:	9001      	str	r0, [sp, #4]
    e6fc:	9100      	str	r1, [sp, #0]
    e6fe:	f143 0300 	adc.w	r3, r3, #0
    e702:	f7ff fe83 	bl	e40c <compare_set>
}
    e706:	b002      	add	sp, #8
    e708:	bd10      	pop	{r4, pc}
	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
    e70a:	4804      	ldr	r0, [pc, #16]	; (e71c <sys_clock_set_timeout+0x5c>)
    e70c:	e7e0      	b.n	e6d0 <sys_clock_set_timeout+0x10>
	ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
    e70e:	2400      	movs	r4, #0
    e710:	e7df      	b.n	e6d2 <sys_clock_set_timeout+0x12>
    e712:	4c02      	ldr	r4, [pc, #8]	; (e71c <sys_clock_set_timeout+0x5c>)
    e714:	e7dd      	b.n	e6d2 <sys_clock_set_timeout+0x12>
    e716:	bf00      	nop
    e718:	200000b0 	.word	0x200000b0
    e71c:	007fffff 	.word	0x007fffff
    e720:	0000e2f5 	.word	0x0000e2f5

0000e724 <sys_clock_elapsed>:
{
    e724:	b508      	push	{r3, lr}
	return (z_nrf_rtc_timer_read() - last_count) / CYC_PER_TICK;
    e726:	f7ff fe4f 	bl	e3c8 <z_nrf_rtc_timer_read>
    e72a:	4b02      	ldr	r3, [pc, #8]	; (e734 <sys_clock_elapsed+0x10>)
    e72c:	681b      	ldr	r3, [r3, #0]
}
    e72e:	1ac0      	subs	r0, r0, r3
    e730:	bd08      	pop	{r3, pc}
    e732:	bf00      	nop
    e734:	200000b0 	.word	0x200000b0

0000e738 <nrf52_errata_16>:
    #ifndef NRF52_SERIES
        return false;
    #else
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
    e738:	f04f 4370 	mov.w	r3, #4026531840	; 0xf0000000
    e73c:	f893 2fe0 	ldrb.w	r2, [r3, #4064]	; 0xfe0
            uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
        #endif
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            if (var1 == 0x06)
    e740:	2a06      	cmp	r2, #6
    e742:	d109      	bne.n	e758 <nrf52_errata_16+0x20>
            uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
    e744:	f8d3 3fe8 	ldr.w	r3, [r3, #4072]	; 0xfe8
    e748:	f3c3 1303 	ubfx	r3, r3, #4, #4
    e74c:	3b03      	subs	r3, #3
    e74e:	2b04      	cmp	r3, #4
    e750:	d802      	bhi.n	e758 <nrf52_errata_16+0x20>
    e752:	4a02      	ldr	r2, [pc, #8]	; (e75c <nrf52_errata_16+0x24>)
    e754:	5cd0      	ldrb	r0, [r2, r3]
    e756:	4770      	bx	lr
                    default:
                        return false;
                }
            }
        #endif
        return false;
    e758:	2000      	movs	r0, #0
    #endif
}
    e75a:	4770      	bx	lr
    e75c:	00010cd6 	.word	0x00010cd6

0000e760 <nvmc_wait>:

/* -- NVMC utility functions -- */
/* Waits until NVMC is done with the current pending action */
void nvmc_wait(void)
{
    while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
    e760:	4a02      	ldr	r2, [pc, #8]	; (e76c <nvmc_wait+0xc>)
    e762:	f8d2 3400 	ldr.w	r3, [r2, #1024]	; 0x400
    e766:	2b00      	cmp	r3, #0
    e768:	d0fb      	beq.n	e762 <nvmc_wait+0x2>
}
    e76a:	4770      	bx	lr
    e76c:	4001e000 	.word	0x4001e000

0000e770 <SystemInit>:
{
    SystemCoreClock = __SYSTEM_CLOCK_64M;
}

void SystemInit(void)
{
    e770:	b510      	push	{r4, lr}
    #endif

    #if NRF52_ERRATA_12_ENABLE_WORKAROUND
        /* Workaround for Errata 12 "COMP: Reference ladder not correctly calibrated" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp */
        if (nrf52_errata_12()){
    e772:	f001 ffc0 	bl	106f6 <nrf52_errata_108>
    e776:	b140      	cbz	r0, e78a <SystemInit+0x1a>
            *(volatile uint32_t *)0x40013540 = (*(uint32_t *)0x10000324 & 0x00001F00) >> 8;
    e778:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    e77c:	4a90      	ldr	r2, [pc, #576]	; (e9c0 <SystemInit+0x250>)
    e77e:	f8d3 3324 	ldr.w	r3, [r3, #804]	; 0x324
    e782:	f3c3 2304 	ubfx	r3, r3, #8, #5
    e786:	f8c2 3540 	str.w	r3, [r2, #1344]	; 0x540
    #endif

    #if NRF52_ERRATA_16_ENABLE_WORKAROUND
        /* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp */
        if (nrf52_errata_16()){
    e78a:	f7ff ffd5 	bl	e738 <nrf52_errata_16>
    e78e:	b110      	cbz	r0, e796 <SystemInit+0x26>
            *(volatile uint32_t *)0x4007C074 = 3131961357ul;
    e790:	4b8c      	ldr	r3, [pc, #560]	; (e9c4 <SystemInit+0x254>)
    e792:	4a8d      	ldr	r2, [pc, #564]	; (e9c8 <SystemInit+0x258>)
    e794:	675a      	str	r2, [r3, #116]	; 0x74
    #endif

    #if NRF52_ERRATA_31_ENABLE_WORKAROUND
        /* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp */
        if (nrf52_errata_31()){
    e796:	f001 ffae 	bl	106f6 <nrf52_errata_108>
    e79a:	b148      	cbz	r0, e7b0 <SystemInit+0x40>
            *(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13;
    e79c:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    e7a0:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    e7a4:	f8d3 3244 	ldr.w	r3, [r3, #580]	; 0x244
    e7a8:	f3c3 3342 	ubfx	r3, r3, #13, #3
    e7ac:	f8c2 353c 	str.w	r3, [r2, #1340]	; 0x53c
    #endif

    #if NRF52_ERRATA_32_ENABLE_WORKAROUND
        /* Workaround for Errata 32 "DIF: Debug session automatically enables TracePort pins" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp */
        if (nrf52_errata_32()){
    e7b0:	f7ff ffc2 	bl	e738 <nrf52_errata_16>
    e7b4:	b130      	cbz	r0, e7c4 <SystemInit+0x54>
            CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk;
    e7b6:	4a85      	ldr	r2, [pc, #532]	; (e9cc <SystemInit+0x25c>)
    e7b8:	f8d2 30fc 	ldr.w	r3, [r2, #252]	; 0xfc
    e7bc:	f023 7380 	bic.w	r3, r3, #16777216	; 0x1000000
    e7c0:	f8c2 30fc 	str.w	r3, [r2, #252]	; 0xfc
    #endif

    #if NRF52_ERRATA_36_ENABLE_WORKAROUND
        /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_36()){
    e7c4:	f001 ff97 	bl	106f6 <nrf52_errata_108>
    e7c8:	b140      	cbz	r0, e7dc <SystemInit+0x6c>
            NRF_CLOCK->EVENTS_DONE = 0;
    e7ca:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    e7ce:	2200      	movs	r2, #0
    e7d0:	f8c3 210c 	str.w	r2, [r3, #268]	; 0x10c
            NRF_CLOCK->EVENTS_CTTO = 0;
    e7d4:	f8c3 2110 	str.w	r2, [r3, #272]	; 0x110
            NRF_CLOCK->CTIV = 0;
    e7d8:	f8c3 2538 	str.w	r2, [r3, #1336]	; 0x538
    #endif

    #if NRF52_ERRATA_37_ENABLE_WORKAROUND
        /* Workaround for Errata 37 "RADIO: Encryption engine is slow by default" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_37()){
    e7dc:	f7ff ffac 	bl	e738 <nrf52_errata_16>
    e7e0:	b120      	cbz	r0, e7ec <SystemInit+0x7c>
            *(volatile uint32_t *)0x400005A0 = 0x3;
    e7e2:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    e7e6:	2203      	movs	r2, #3
    e7e8:	f8c3 25a0 	str.w	r2, [r3, #1440]	; 0x5a0
    #endif

    #if NRF52_ERRATA_57_ENABLE_WORKAROUND
        /* Workaround for Errata 57 "NFCT: NFC Modulation amplitude" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_57()){
    e7ec:	f7ff ffa4 	bl	e738 <nrf52_errata_16>
    e7f0:	b160      	cbz	r0, e80c <SystemInit+0x9c>
            *(volatile uint32_t *)0x40005610 = 0x00000005;
    e7f2:	4b77      	ldr	r3, [pc, #476]	; (e9d0 <SystemInit+0x260>)
    e7f4:	2205      	movs	r2, #5
    e7f6:	f8c3 2610 	str.w	r2, [r3, #1552]	; 0x610
            *(volatile uint32_t *)0x40005688 = 0x00000001;
    e7fa:	2201      	movs	r2, #1
    e7fc:	f8c3 2688 	str.w	r2, [r3, #1672]	; 0x688
            *(volatile uint32_t *)0x40005618 = 0x00000000;
    e800:	2200      	movs	r2, #0
    e802:	f8c3 2618 	str.w	r2, [r3, #1560]	; 0x618
            *(volatile uint32_t *)0x40005614 = 0x0000003F;
    e806:	223f      	movs	r2, #63	; 0x3f
    e808:	f8c3 2614 	str.w	r2, [r3, #1556]	; 0x614
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            uint32_t var1;
            uint32_t var2;

            if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF)
    e80c:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    e810:	f8d3 2130 	ldr.w	r2, [r3, #304]	; 0x130
    e814:	1c51      	adds	r1, r2, #1
            {
                var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
    e816:	bf09      	itett	eq
    e818:	f04f 4370 	moveq.w	r3, #4026531840	; 0xf0000000
                var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
            }
            else
            {
                var1 = *(uint32_t *)0x10000130ul;
                var2 = *(uint32_t *)0x10000134ul;
    e81c:	f8d3 3134 	ldrne.w	r3, [r3, #308]	; 0x134
                var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
    e820:	f893 2fe0 	ldrbeq.w	r2, [r3, #4064]	; 0xfe0
                var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4;
    e824:	f8d3 3fe8 	ldreq.w	r3, [r3, #4072]	; 0xfe8
    e828:	bf08      	it	eq
    e82a:	f3c3 1303 	ubfxeq	r3, r3, #4, #4
            uint32_t var1 = *(uint32_t *)0x10000130ul;
            uint32_t var2 = *(uint32_t *)0x10000134ul;
        #endif
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            if (var1 == 0x06)
    e82e:	2a06      	cmp	r2, #6
    e830:	d14d      	bne.n	e8ce <SystemInit+0x15e>
            {
                switch(var2)
    e832:	3b03      	subs	r3, #3
    e834:	2b04      	cmp	r3, #4
    e836:	d803      	bhi.n	e840 <SystemInit+0xd0>
    #endif

    #if NRF52_ERRATA_66_ENABLE_WORKAROUND
        /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_66()){
    e838:	4a66      	ldr	r2, [pc, #408]	; (e9d4 <SystemInit+0x264>)
    e83a:	5cd3      	ldrb	r3, [r2, r3]
    e83c:	2b00      	cmp	r3, #0
    e83e:	d046      	beq.n	e8ce <SystemInit+0x15e>
            NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
    e840:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
    e844:	4b64      	ldr	r3, [pc, #400]	; (e9d8 <SystemInit+0x268>)
    e846:	f8d2 1404 	ldr.w	r1, [r2, #1028]	; 0x404
    e84a:	f8c3 1520 	str.w	r1, [r3, #1312]	; 0x520
            NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
    e84e:	f8d2 1408 	ldr.w	r1, [r2, #1032]	; 0x408
    e852:	f8c3 1524 	str.w	r1, [r3, #1316]	; 0x524
            NRF_TEMP->A2 = NRF_FICR->TEMP.A2;
    e856:	f8d2 140c 	ldr.w	r1, [r2, #1036]	; 0x40c
    e85a:	f8c3 1528 	str.w	r1, [r3, #1320]	; 0x528
            NRF_TEMP->A3 = NRF_FICR->TEMP.A3;
    e85e:	f8d2 1410 	ldr.w	r1, [r2, #1040]	; 0x410
    e862:	f8c3 152c 	str.w	r1, [r3, #1324]	; 0x52c
            NRF_TEMP->A4 = NRF_FICR->TEMP.A4;
    e866:	f8d2 1414 	ldr.w	r1, [r2, #1044]	; 0x414
    e86a:	f8c3 1530 	str.w	r1, [r3, #1328]	; 0x530
            NRF_TEMP->A5 = NRF_FICR->TEMP.A5;
    e86e:	f8d2 1418 	ldr.w	r1, [r2, #1048]	; 0x418
    e872:	f8c3 1534 	str.w	r1, [r3, #1332]	; 0x534
            NRF_TEMP->B0 = NRF_FICR->TEMP.B0;
    e876:	f8d2 141c 	ldr.w	r1, [r2, #1052]	; 0x41c
    e87a:	f8c3 1540 	str.w	r1, [r3, #1344]	; 0x540
            NRF_TEMP->B1 = NRF_FICR->TEMP.B1;
    e87e:	f8d2 1420 	ldr.w	r1, [r2, #1056]	; 0x420
    e882:	f8c3 1544 	str.w	r1, [r3, #1348]	; 0x544
            NRF_TEMP->B2 = NRF_FICR->TEMP.B2;
    e886:	f8d2 1424 	ldr.w	r1, [r2, #1060]	; 0x424
    e88a:	f8c3 1548 	str.w	r1, [r3, #1352]	; 0x548
            NRF_TEMP->B3 = NRF_FICR->TEMP.B3;
    e88e:	f8d2 1428 	ldr.w	r1, [r2, #1064]	; 0x428
    e892:	f8c3 154c 	str.w	r1, [r3, #1356]	; 0x54c
            NRF_TEMP->B4 = NRF_FICR->TEMP.B4;
    e896:	f8d2 142c 	ldr.w	r1, [r2, #1068]	; 0x42c
    e89a:	f8c3 1550 	str.w	r1, [r3, #1360]	; 0x550
            NRF_TEMP->B5 = NRF_FICR->TEMP.B5;
    e89e:	f8d2 1430 	ldr.w	r1, [r2, #1072]	; 0x430
    e8a2:	f8c3 1554 	str.w	r1, [r3, #1364]	; 0x554
            NRF_TEMP->T0 = NRF_FICR->TEMP.T0;
    e8a6:	f8d2 1434 	ldr.w	r1, [r2, #1076]	; 0x434
    e8aa:	f8c3 1560 	str.w	r1, [r3, #1376]	; 0x560
            NRF_TEMP->T1 = NRF_FICR->TEMP.T1;
    e8ae:	f8d2 1438 	ldr.w	r1, [r2, #1080]	; 0x438
    e8b2:	f8c3 1564 	str.w	r1, [r3, #1380]	; 0x564
            NRF_TEMP->T2 = NRF_FICR->TEMP.T2;
    e8b6:	f8d2 143c 	ldr.w	r1, [r2, #1084]	; 0x43c
    e8ba:	f8c3 1568 	str.w	r1, [r3, #1384]	; 0x568
            NRF_TEMP->T3 = NRF_FICR->TEMP.T3;
    e8be:	f8d2 1440 	ldr.w	r1, [r2, #1088]	; 0x440
    e8c2:	f8c3 156c 	str.w	r1, [r3, #1388]	; 0x56c
            NRF_TEMP->T4 = NRF_FICR->TEMP.T4;
    e8c6:	f8d2 2444 	ldr.w	r2, [r2, #1092]	; 0x444
    e8ca:	f8c3 2570 	str.w	r2, [r3, #1392]	; 0x570
    #endif

    #if NRF52_ERRATA_108_ENABLE_WORKAROUND
        /* Workaround for Errata 108 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_108()){
    e8ce:	f001 ff12 	bl	106f6 <nrf52_errata_108>
    e8d2:	b148      	cbz	r0, e8e8 <SystemInit+0x178>
            *(volatile uint32_t *)0x40000EE4ul = *(volatile uint32_t *)0x10000258ul & 0x0000004Ful;
    e8d4:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    e8d8:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    e8dc:	f8d3 3258 	ldr.w	r3, [r3, #600]	; 0x258
    e8e0:	f003 034f 	and.w	r3, r3, #79	; 0x4f
    e8e4:	f8c2 3ee4 	str.w	r3, [r2, #3812]	; 0xee4
    #endif

    #if NRF52_ERRATA_136_ENABLE_WORKAROUND
        /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_136()){
    e8e8:	f001 ff05 	bl	106f6 <nrf52_errata_108>
    e8ec:	b148      	cbz	r0, e902 <SystemInit+0x192>
            if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){
    e8ee:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    e8f2:	f8d3 2400 	ldr.w	r2, [r3, #1024]	; 0x400
    e8f6:	07d2      	lsls	r2, r2, #31
                NRF_POWER->RESETREAS =  ~POWER_RESETREAS_RESETPIN_Msk;
    e8f8:	bf44      	itt	mi
    e8fa:	f06f 0201 	mvnmi.w	r2, #1
    e8fe:	f8c3 2400 	strmi.w	r2, [r3, #1024]	; 0x400
    #ifndef NRF52_SERIES
        return false;
    #else
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    e902:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
            uint32_t var2 = *(uint32_t *)0x10000134ul;
        #endif
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            if (var1 == 0x06)
    e906:	f8d3 2130 	ldr.w	r2, [r3, #304]	; 0x130
    e90a:	2a06      	cmp	r2, #6
    e90c:	d126      	bne.n	e95c <SystemInit+0x1ec>
            {
                switch(var2)
    e90e:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
    e912:	3b03      	subs	r3, #3
    e914:	2b04      	cmp	r3, #4
    e916:	d802      	bhi.n	e91e <SystemInit+0x1ae>
    #endif

    #if NRF52_ERRATA_182_ENABLE_WORKAROUND
        /* Workaround for Errata 182 "RADIO: Fixes for anomalies #102, #106, and #107 do not take effect" found at the Errata document
           for your device located at https://infocenter.nordicsemi.com/index.jsp  */
        if (nrf52_errata_182()){
    e918:	4a30      	ldr	r2, [pc, #192]	; (e9dc <SystemInit+0x26c>)
    e91a:	5cd3      	ldrb	r3, [r2, r3]
    e91c:	b163      	cbz	r3, e938 <SystemInit+0x1c8>
            *(volatile uint32_t *) 0x4000173C |= (0x1 << 10);
    e91e:	4a30      	ldr	r2, [pc, #192]	; (e9e0 <SystemInit+0x270>)
    e920:	f8d2 373c 	ldr.w	r3, [r2, #1852]	; 0x73c
    e924:	f443 6380 	orr.w	r3, r3, #1024	; 0x400
    e928:	f8c2 373c 	str.w	r3, [r2, #1852]	; 0x73c
         || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\
         || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\
         || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840)
            uint32_t var1 = *(uint32_t *)0x10000130ul;
    e92c:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
            uint32_t var2 = *(uint32_t *)0x10000134ul;
        #endif
        #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\
         || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)
            if (var1 == 0x06)
    e930:	f8d3 3130 	ldr.w	r3, [r3, #304]	; 0x130
    e934:	2b06      	cmp	r3, #6
    e936:	d111      	bne.n	e95c <SystemInit+0x1ec>
            uint32_t var2 = *(uint32_t *)0x10000134ul;
    e938:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    e93c:	f8d3 3134 	ldr.w	r3, [r3, #308]	; 0x134
    e940:	3b03      	subs	r3, #3
    e942:	2b04      	cmp	r3, #4
    e944:	d802      	bhi.n	e94c <SystemInit+0x1dc>
            {
                /* Prevent processor from unlocking APPROTECT soft branch after this point. */
                NRF_APPROTECT->FORCEPROTECT = APPROTECT_FORCEPROTECT_FORCEPROTECT_Force;
            }
        #else
            if (nrf52_configuration_249())
    e946:	4a27      	ldr	r2, [pc, #156]	; (e9e4 <SystemInit+0x274>)
    e948:	5cd3      	ldrb	r3, [r2, r3]
    e94a:	b13b      	cbz	r3, e95c <SystemInit+0x1ec>
            {
                /* Load APPROTECT soft branch from UICR.
                   If UICR->APPROTECT is disabled, POWER->APPROTECT will be disabled. */
                NRF_APPROTECT->DISABLE = NRF_UICR->APPROTECT;
    e94c:	f04f 2310 	mov.w	r3, #268439552	; 0x10001000
    e950:	f8d3 2208 	ldr.w	r2, [r3, #520]	; 0x208
    e954:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    e958:	f8c3 2558 	str.w	r2, [r3, #1368]	; 0x558

    /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
      defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
      reserved for PinReset and not available as normal GPIO. */
    #if defined (CONFIG_GPIO_AS_PINRESET)
        if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
    e95c:	f04f 2310 	mov.w	r3, #268439552	; 0x10001000
    e960:	f8d3 2200 	ldr.w	r2, [r3, #512]	; 0x200
    e964:	2a00      	cmp	r2, #0
    e966:	db03      	blt.n	e970 <SystemInit+0x200>
            ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
    e968:	f8d3 3204 	ldr.w	r3, [r3, #516]	; 0x204
        if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
    e96c:	2b00      	cmp	r3, #0
    e96e:	da22      	bge.n	e9b6 <SystemInit+0x246>
    NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
    e970:	491d      	ldr	r1, [pc, #116]	; (e9e8 <SystemInit+0x278>)
    e972:	2301      	movs	r3, #1
            nvmc_config(NVMC_CONFIG_WEN_Wen);
            NRF_UICR->PSELRESET[0] = RESET_PIN;
    e974:	f04f 2010 	mov.w	r0, #268439552	; 0x10001000
    NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
    e978:	f8c1 3504 	str.w	r3, [r1, #1284]	; 0x504
            NRF_UICR->PSELRESET[0] = RESET_PIN;
    e97c:	2415      	movs	r4, #21
    nvmc_wait();
    e97e:	f7ff feef 	bl	e760 <nvmc_wait>
            NRF_UICR->PSELRESET[0] = RESET_PIN;
    e982:	f8c0 4200 	str.w	r4, [r0, #512]	; 0x200
            nvmc_wait();
    e986:	f7ff feeb 	bl	e760 <nvmc_wait>
            NRF_UICR->PSELRESET[1] = RESET_PIN;
    e98a:	f8c0 4204 	str.w	r4, [r0, #516]	; 0x204
            nvmc_wait();
    e98e:	f7ff fee7 	bl	e760 <nvmc_wait>
    NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
    e992:	2300      	movs	r3, #0
    e994:	f8c1 3504 	str.w	r3, [r1, #1284]	; 0x504
    nvmc_wait();
    e998:	f7ff fee2 	bl	e760 <nvmc_wait>
  __ASM volatile ("dsb 0xF":::"memory");
    e99c:	f3bf 8f4f 	dsb	sy
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
    e9a0:	490a      	ldr	r1, [pc, #40]	; (e9cc <SystemInit+0x25c>)
    e9a2:	4b12      	ldr	r3, [pc, #72]	; (e9ec <SystemInit+0x27c>)
    e9a4:	68ca      	ldr	r2, [r1, #12]
    e9a6:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
    e9aa:	4313      	orrs	r3, r2
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
    e9ac:	60cb      	str	r3, [r1, #12]
    e9ae:	f3bf 8f4f 	dsb	sy
    __NOP();
    e9b2:	bf00      	nop
  for(;;)                                                           /* wait until reset */
    e9b4:	e7fd      	b.n	e9b2 <SystemInit+0x242>
    SystemCoreClock = __SYSTEM_CLOCK_64M;
    e9b6:	4b0e      	ldr	r3, [pc, #56]	; (e9f0 <SystemInit+0x280>)
    e9b8:	4a0e      	ldr	r2, [pc, #56]	; (e9f4 <SystemInit+0x284>)
    e9ba:	601a      	str	r2, [r3, #0]
            NVIC_SystemReset();
        }
    #endif

    SystemCoreClockUpdate();
}
    e9bc:	bd10      	pop	{r4, pc}
    e9be:	bf00      	nop
    e9c0:	40013000 	.word	0x40013000
    e9c4:	4007c000 	.word	0x4007c000
    e9c8:	baadf00d 	.word	0xbaadf00d
    e9cc:	e000ed00 	.word	0xe000ed00
    e9d0:	40005000 	.word	0x40005000
    e9d4:	00010cc7 	.word	0x00010cc7
    e9d8:	4000c000 	.word	0x4000c000
    e9dc:	00010ccc 	.word	0x00010ccc
    e9e0:	40001000 	.word	0x40001000
    e9e4:	00010cd1 	.word	0x00010cd1
    e9e8:	4001e000 	.word	0x4001e000
    e9ec:	05fa0004 	.word	0x05fa0004
    e9f0:	20000020 	.word	0x20000020
    e9f4:	03d09000 	.word	0x03d09000

0000e9f8 <nrfx_flag32_alloc>:
{
    return (mask & NRFX_BIT(bitpos)) ? false : true;
}

nrfx_err_t nrfx_flag32_alloc(nrfx_atomic_t * p_mask, uint8_t *p_flag)
{
    e9f8:	b570      	push	{r4, r5, r6, lr}
        idx = 31 - NRF_CLZ(prev_mask);
        if (idx < 0) {
            return NRFX_ERROR_NO_MEM;
        }

        new_mask = prev_mask & ~NRFX_BIT(idx);
    e9fa:	2501      	movs	r5, #1
        prev_mask = *p_mask;
    e9fc:	6802      	ldr	r2, [r0, #0]
        idx = 31 - NRF_CLZ(prev_mask);
    e9fe:	fab2 f382 	clz	r3, r2
    ea02:	f1c3 031f 	rsb	r3, r3, #31
        if (idx < 0) {
    ea06:	1c5e      	adds	r6, r3, #1
        idx = 31 - NRF_CLZ(prev_mask);
    ea08:	b2dc      	uxtb	r4, r3
        if (idx < 0) {
    ea0a:	d014      	beq.n	ea36 <nrfx_flag32_alloc+0x3e>
	return __atomic_compare_exchange_n(target, &old_value, new_value,
    ea0c:	f3bf 8f5b 	dmb	ish
        new_mask = prev_mask & ~NRFX_BIT(idx);
    ea10:	fa05 f303 	lsl.w	r3, r5, r3
    ea14:	ea22 0303 	bic.w	r3, r2, r3
    ea18:	e850 6f00 	ldrex	r6, [r0]
    ea1c:	4296      	cmp	r6, r2
    ea1e:	d104      	bne.n	ea2a <nrfx_flag32_alloc+0x32>
    ea20:	e840 3c00 	strex	ip, r3, [r0]
    ea24:	f1bc 0f00 	cmp.w	ip, #0
    ea28:	d1f6      	bne.n	ea18 <nrfx_flag32_alloc+0x20>
    ea2a:	f3bf 8f5b 	dmb	ish
    } while (!NRFX_ATOMIC_CAS(p_mask, prev_mask, new_mask));
    ea2e:	d1e5      	bne.n	e9fc <nrfx_flag32_alloc+0x4>

    *p_flag = idx;

    return NRFX_SUCCESS;
    ea30:	4802      	ldr	r0, [pc, #8]	; (ea3c <nrfx_flag32_alloc+0x44>)
    *p_flag = idx;
    ea32:	700c      	strb	r4, [r1, #0]
}
    ea34:	bd70      	pop	{r4, r5, r6, pc}
            return NRFX_ERROR_NO_MEM;
    ea36:	4802      	ldr	r0, [pc, #8]	; (ea40 <nrfx_flag32_alloc+0x48>)
    ea38:	e7fc      	b.n	ea34 <nrfx_flag32_alloc+0x3c>
    ea3a:	bf00      	nop
    ea3c:	0bad0000 	.word	0x0bad0000
    ea40:	0bad0002 	.word	0x0bad0002

0000ea44 <nrfx_flag32_free>:

nrfx_err_t nrfx_flag32_free(nrfx_atomic_t * p_mask, uint8_t flag)
{
    uint32_t new_mask, prev_mask;

    if ((NRFX_BIT(flag) & *p_mask))
    ea44:	6803      	ldr	r3, [r0, #0]
    ea46:	40cb      	lsrs	r3, r1
    ea48:	07db      	lsls	r3, r3, #31
{
    ea4a:	b510      	push	{r4, lr}
    if ((NRFX_BIT(flag) & *p_mask))
    ea4c:	d415      	bmi.n	ea7a <nrfx_flag32_free+0x36>
        return NRFX_ERROR_INVALID_PARAM;
    }

    do {
        prev_mask = *p_mask;
        new_mask = prev_mask | NRFX_BIT(flag);
    ea4e:	2301      	movs	r3, #1
    ea50:	fa03 f101 	lsl.w	r1, r3, r1
        prev_mask = *p_mask;
    ea54:	6803      	ldr	r3, [r0, #0]
    ea56:	f3bf 8f5b 	dmb	ish
        new_mask = prev_mask | NRFX_BIT(flag);
    ea5a:	ea41 0203 	orr.w	r2, r1, r3
    ea5e:	e850 4f00 	ldrex	r4, [r0]
    ea62:	429c      	cmp	r4, r3
    ea64:	d104      	bne.n	ea70 <nrfx_flag32_free+0x2c>
    ea66:	e840 2c00 	strex	ip, r2, [r0]
    ea6a:	f1bc 0f00 	cmp.w	ip, #0
    ea6e:	d1f6      	bne.n	ea5e <nrfx_flag32_free+0x1a>
    ea70:	f3bf 8f5b 	dmb	ish
    } while (!NRFX_ATOMIC_CAS(p_mask, prev_mask, new_mask));
    ea74:	d1ee      	bne.n	ea54 <nrfx_flag32_free+0x10>

    return NRFX_SUCCESS;
    ea76:	4802      	ldr	r0, [pc, #8]	; (ea80 <nrfx_flag32_free+0x3c>)
}
    ea78:	bd10      	pop	{r4, pc}
        return NRFX_ERROR_INVALID_PARAM;
    ea7a:	4802      	ldr	r0, [pc, #8]	; (ea84 <nrfx_flag32_free+0x40>)
    ea7c:	e7fc      	b.n	ea78 <nrfx_flag32_free+0x34>
    ea7e:	bf00      	nop
    ea80:	0bad0000 	.word	0x0bad0000
    ea84:	0bad0004 	.word	0x0bad0004

0000ea88 <clock_stop>:
    CoreDebug->DEMCR = core_debug;
}
#endif // NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_132)

static void clock_stop(nrf_clock_domain_t domain)
{
    ea88:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
    switch (domain)
    ea8a:	4604      	mov	r4, r0
    ea8c:	b118      	cbz	r0, ea96 <clock_stop+0xe>
    ea8e:	2801      	cmp	r0, #1
    ea90:	d029      	beq.n	eae6 <clock_stop+0x5e>
    if (domain == NRF_CLOCK_DOMAIN_HFCLK)
    {
            m_clock_cb.hfclk_started = false;
    }
#endif
}
    ea92:	b003      	add	sp, #12
    ea94:	bdf0      	pop	{r4, r5, r6, r7, pc}
    p_reg->INTENCLR = mask;
    ea96:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    ea9a:	2202      	movs	r2, #2
    ea9c:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    eaa0:	f8c3 0104 	str.w	r0, [r3, #260]	; 0x104
    eaa4:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    eaa8:	2201      	movs	r2, #1
    eaaa:	60da      	str	r2, [r3, #12]
    nrf_clock_hfclk_t clk_src = NRF_CLOCK_HFCLK_HIGH_ACCURACY;
    eaac:	2301      	movs	r3, #1
    nrf_clock_hfclk_t *p_clk_src = (domain == NRF_CLOCK_DOMAIN_HFCLK) ? &clk_src : NULL;
    eaae:	429c      	cmp	r4, r3
    nrf_clock_hfclk_t clk_src = NRF_CLOCK_HFCLK_HIGH_ACCURACY;
    eab0:	f88d 3007 	strb.w	r3, [sp, #7]
    nrf_clock_hfclk_t *p_clk_src = (domain == NRF_CLOCK_DOMAIN_HFCLK) ? &clk_src : NULL;
    eab4:	bf14      	ite	ne
    eab6:	2500      	movne	r5, #0
    eab8:	f10d 0507 	addeq.w	r5, sp, #7
    eabc:	f242 7710 	movw	r7, #10000	; 0x2710
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    eac0:	f04f 4680 	mov.w	r6, #1073741824	; 0x40000000
    switch (domain)
    eac4:	b1d4      	cbz	r4, eafc <clock_stop+0x74>
    eac6:	2c01      	cmp	r4, #1
    eac8:	d1e3      	bne.n	ea92 <clock_stop+0xa>
            if (p_clk_src != NULL)
    eaca:	b125      	cbz	r5, ead6 <clock_stop+0x4e>
                    (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
    eacc:	f8d6 340c 	ldr.w	r3, [r6, #1036]	; 0x40c
    ead0:	f003 0301 	and.w	r3, r3, #1
                (*(nrf_clock_hfclk_t *)p_clk_src) =
    ead4:	702b      	strb	r3, [r5, #0]
            if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
    ead6:	f8d6 340c 	ldr.w	r3, [r6, #1036]	; 0x40c
    eada:	03db      	lsls	r3, r3, #15
    eadc:	d418      	bmi.n	eb10 <clock_stop+0x88>
            m_clock_cb.hfclk_started = false;
    eade:	4b13      	ldr	r3, [pc, #76]	; (eb2c <clock_stop+0xa4>)
    eae0:	2200      	movs	r2, #0
    eae2:	715a      	strb	r2, [r3, #5]
    eae4:	e7d5      	b.n	ea92 <clock_stop+0xa>
    p_reg->INTENCLR = mask;
    eae6:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    eaea:	2200      	movs	r2, #0
    p_reg->INTENCLR = mask;
    eaec:	f8c3 0308 	str.w	r0, [r3, #776]	; 0x308
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    eaf0:	f8c3 2100 	str.w	r2, [r3, #256]	; 0x100
    eaf4:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    eaf8:	6058      	str	r0, [r3, #4]
}
    eafa:	e7d7      	b.n	eaac <clock_stop+0x24>
            if (p_clk_src != NULL)
    eafc:	b125      	cbz	r5, eb08 <clock_stop+0x80>
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    eafe:	f8d6 3418 	ldr.w	r3, [r6, #1048]	; 0x418
                                        >> CLOCK_LFCLKSTAT_SRC_Pos);
    eb02:	f003 0303 	and.w	r3, r3, #3
                (*(nrf_clock_lfclk_t *)p_clk_src) =
    eb06:	602b      	str	r3, [r5, #0]
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    eb08:	f8d6 3418 	ldr.w	r3, [r6, #1048]	; 0x418
    eb0c:	03da      	lsls	r2, r3, #15
    eb0e:	d5c0      	bpl.n	ea92 <clock_stop+0xa>
    NRFX_WAIT_FOR((!nrfx_clock_is_running(domain, p_clk_src) ||
    eb10:	b92d      	cbnz	r5, eb1e <clock_stop+0x96>
    eb12:	2001      	movs	r0, #1
    eb14:	f001 fdfe 	bl	10714 <nrfx_busy_wait>
    eb18:	3f01      	subs	r7, #1
    eb1a:	d1d3      	bne.n	eac4 <clock_stop+0x3c>
    eb1c:	e003      	b.n	eb26 <clock_stop+0x9e>
    eb1e:	f89d 3007 	ldrb.w	r3, [sp, #7]
    eb22:	2b01      	cmp	r3, #1
    eb24:	d0f5      	beq.n	eb12 <clock_stop+0x8a>
    if (domain == NRF_CLOCK_DOMAIN_HFCLK)
    eb26:	2c01      	cmp	r4, #1
    eb28:	d0d9      	beq.n	eade <clock_stop+0x56>
    eb2a:	e7b2      	b.n	ea92 <clock_stop+0xa>
    eb2c:	20000288 	.word	0x20000288

0000eb30 <nrfx_clock_init>:
nrfx_err_t nrfx_clock_init(nrfx_clock_event_handler_t event_handler)
{
    NRFX_ASSERT(event_handler);

    nrfx_err_t err_code = NRFX_SUCCESS;
    if (m_clock_cb.module_initialized)
    eb30:	4b04      	ldr	r3, [pc, #16]	; (eb44 <nrfx_clock_init+0x14>)
    eb32:	791a      	ldrb	r2, [r3, #4]
    eb34:	b922      	cbnz	r2, eb40 <nrfx_clock_init+0x10>
    {
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
        m_clock_cb.cal_state = CAL_STATE_IDLE;
#endif
        m_clock_cb.event_handler = event_handler;
        m_clock_cb.module_initialized = true;
    eb36:	2201      	movs	r2, #1
        m_clock_cb.event_handler = event_handler;
    eb38:	6018      	str	r0, [r3, #0]
        m_clock_cb.module_initialized = true;
    eb3a:	809a      	strh	r2, [r3, #4]
    nrfx_err_t err_code = NRFX_SUCCESS;
    eb3c:	4802      	ldr	r0, [pc, #8]	; (eb48 <nrfx_clock_init+0x18>)
    eb3e:	4770      	bx	lr
        err_code = NRFX_ERROR_ALREADY_INITIALIZED;
    eb40:	4802      	ldr	r0, [pc, #8]	; (eb4c <nrfx_clock_init+0x1c>)
#endif
    }

    NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
    return err_code;
}
    eb42:	4770      	bx	lr
    eb44:	20000288 	.word	0x20000288
    eb48:	0bad0000 	.word	0x0bad0000
    eb4c:	0bad000c 	.word	0x0bad000c

0000eb50 <nrfx_clock_start>:
    m_clock_cb.module_initialized = false;
    NRFX_LOG_INFO("Uninitialized.");
}

void nrfx_clock_start(nrf_clock_domain_t domain)
{
    eb50:	b538      	push	{r3, r4, r5, lr}
    NRFX_ASSERT(m_clock_cb.module_initialized);
    switch (domain)
    eb52:	b110      	cbz	r0, eb5a <nrfx_clock_start+0xa>
    eb54:	2801      	cmp	r0, #1
    eb56:	d044      	beq.n	ebe2 <nrfx_clock_start+0x92>
#endif
        default:
            NRFX_ASSERT(0);
            break;
    }
}
    eb58:	bd38      	pop	{r3, r4, r5, pc}
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    eb5a:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    eb5e:	f8d2 1418 	ldr.w	r1, [r2, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    eb62:	f8d2 3418 	ldr.w	r3, [r2, #1048]	; 0x418
    eb66:	f413 3380 	ands.w	r3, r3, #65536	; 0x10000
    eb6a:	d10b      	bne.n	eb84 <nrfx_clock_start+0x34>
            return ((p_reg->LFCLKRUN & CLOCK_LFCLKRUN_STATUS_Msk)
    eb6c:	f8d2 1414 	ldr.w	r1, [r2, #1044]	; 0x414
                else if (nrf_clock_start_task_check(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK))
    eb70:	07c9      	lsls	r1, r1, #31
    eb72:	d510      	bpl.n	eb96 <nrfx_clock_start+0x46>
    return (nrf_clock_lfclk_t)((p_reg->LFCLKSRCCOPY & CLOCK_LFCLKSRCCOPY_SRC_Msk)
    eb74:	f8d2 341c 	ldr.w	r3, [r2, #1052]	; 0x41c
    if (!is_correct_clk)
    eb78:	079b      	lsls	r3, r3, #30
    eb7a:	d408      	bmi.n	eb8e <nrfx_clock_start+0x3e>
    p_reg->INTENSET = mask;
    eb7c:	2302      	movs	r3, #2
    eb7e:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
                        break;
    eb82:	e7e9      	b.n	eb58 <nrfx_clock_start+0x8>
                                        >> CLOCK_LFCLKSTAT_SRC_Pos);
    eb84:	f001 0303 	and.w	r3, r1, #3
    is_correct_clk = is_correct_clk || (*p_lfclksrc == NRF_CLOCK_LFCLK_RC);
    eb88:	2b01      	cmp	r3, #1
    eb8a:	d004      	beq.n	eb96 <nrfx_clock_start+0x46>
    if (!is_correct_clk)
    eb8c:	b11b      	cbz	r3, eb96 <nrfx_clock_start+0x46>
        clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
    eb8e:	2000      	movs	r0, #0
    eb90:	f7ff ff7a 	bl	ea88 <clock_stop>
        *p_lfclksrc = clock_initial_lfclksrc_get();
    eb94:	2300      	movs	r3, #0
    p_reg->LFCLKSRC = (uint32_t)(source);
    eb96:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    eb9a:	f8c2 3518 	str.w	r3, [r2, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    eb9e:	2300      	movs	r3, #0
    eba0:	f8c2 3104 	str.w	r3, [r2, #260]	; 0x104
    eba4:	f8d2 3104 	ldr.w	r3, [r2, #260]	; 0x104
    p_reg->INTENSET = mask;
    eba8:	2302      	movs	r3, #2
    ebaa:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
    core_debug = CoreDebug->DEMCR;
    ebae:	4a12      	ldr	r2, [pc, #72]	; (ebf8 <nrfx_clock_start+0xa8>)
    ebb0:	f8d2 00fc 	ldr.w	r0, [r2, #252]	; 0xfc
    CoreDebug->DEMCR = core_debug | CoreDebug_DEMCR_TRCENA_Msk;
    ebb4:	f040 7380 	orr.w	r3, r0, #16777216	; 0x1000000
    ebb8:	f8c2 30fc 	str.w	r3, [r2, #252]	; 0xfc
    dwt_ctrl = DWT->CTRL;
    ebbc:	4b0f      	ldr	r3, [pc, #60]	; (ebfc <nrfx_clock_start+0xac>)
    ebbe:	681c      	ldr	r4, [r3, #0]
    DWT->CTRL = dwt_ctrl | DWT_CTRL_CYCCNTENA_Msk;
    ebc0:	f044 0101 	orr.w	r1, r4, #1
    ebc4:	6019      	str	r1, [r3, #0]
    cyccnt_inital = DWT->CYCCNT;
    ebc6:	685d      	ldr	r5, [r3, #4]
    while ((DWT->CYCCNT - cyccnt_inital) < ANOMALY_132_DELAY_CYCLES)
    ebc8:	6859      	ldr	r1, [r3, #4]
    ebca:	1b49      	subs	r1, r1, r5
    ebcc:	f5b1 5f0a 	cmp.w	r1, #8832	; 0x2280
    ebd0:	d3fa      	bcc.n	ebc8 <nrfx_clock_start+0x78>
    DWT->CTRL = dwt_ctrl;
    ebd2:	601c      	str	r4, [r3, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    ebd4:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    CoreDebug->DEMCR = core_debug;
    ebd8:	f8c2 00fc 	str.w	r0, [r2, #252]	; 0xfc
    ebdc:	2201      	movs	r2, #1
    ebde:	609a      	str	r2, [r3, #8]
}
    ebe0:	e7ba      	b.n	eb58 <nrfx_clock_start+0x8>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    ebe2:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    ebe6:	2200      	movs	r2, #0
    ebe8:	f8c3 2100 	str.w	r2, [r3, #256]	; 0x100
    ebec:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    p_reg->INTENSET = mask;
    ebf0:	f8c3 0304 	str.w	r0, [r3, #772]	; 0x304
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    ebf4:	6018      	str	r0, [r3, #0]
}
    ebf6:	e7af      	b.n	eb58 <nrfx_clock_start+0x8>
    ebf8:	e000ed00 	.word	0xe000ed00
    ebfc:	e0001000 	.word	0xe0001000

0000ec00 <nrfx_power_clock_irq_handler>:
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    ec00:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    }
}
#endif

void nrfx_clock_irq_handler(void)
{
    ec04:	b510      	push	{r4, lr}
    ec06:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED))
    ec0a:	b16a      	cbz	r2, ec28 <nrfx_power_clock_irq_handler+0x28>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    ec0c:	2200      	movs	r2, #0
    ec0e:	f8c3 2100 	str.w	r2, [r3, #256]	; 0x100
    ec12:	f8d3 2100 	ldr.w	r2, [r3, #256]	; 0x100
    p_reg->INTENCLR = mask;
    ec16:	2201      	movs	r2, #1
    ec18:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
        nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED);
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_HFCLKSTARTED");
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF_STARTED_MASK);

#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_201)
        if (!m_clock_cb.hfclk_started)
    ec1c:	4b11      	ldr	r3, [pc, #68]	; (ec64 <nrfx_power_clock_irq_handler+0x64>)
    ec1e:	7958      	ldrb	r0, [r3, #5]
    ec20:	b910      	cbnz	r0, ec28 <nrfx_power_clock_irq_handler+0x28>
        {
            m_clock_cb.hfclk_started = true;
    ec22:	715a      	strb	r2, [r3, #5]
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
    ec24:	681b      	ldr	r3, [r3, #0]
    ec26:	4798      	blx	r3
    return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event));
    ec28:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
    ec2c:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
        }
#else
        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED);
#endif
    }
    if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED))
    ec30:	b172      	cbz	r2, ec50 <nrfx_power_clock_irq_handler+0x50>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
    ec32:	2200      	movs	r2, #0
    ec34:	f8c3 2104 	str.w	r2, [r3, #260]	; 0x104
    ec38:	f8d3 2104 	ldr.w	r2, [r3, #260]	; 0x104
                    (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
    ec3c:	f8d3 2418 	ldr.w	r2, [r3, #1048]	; 0x418
            if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
    ec40:	f8d3 1418 	ldr.w	r1, [r3, #1048]	; 0x418
        NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_LFCLKSTARTED");

#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED)
        nrf_clock_lfclk_t lfclksrc;
        (void)nrf_clock_is_running(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK, &lfclksrc);
        if (lfclksrc == NRF_CLOCK_LFCLK_RC)
    ec44:	0792      	lsls	r2, r2, #30
    ec46:	d104      	bne.n	ec52 <nrfx_power_clock_irq_handler+0x52>
    p_reg->LFCLKSRC = (uint32_t)(source);
    ec48:	2201      	movs	r2, #1
    ec4a:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
    ec4e:	609a      	str	r2, [r3, #8]
        nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF192M_STARTED_MASK);

        m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK192M_STARTED);
    }
#endif
}
    ec50:	bd10      	pop	{r4, pc}
    p_reg->INTENCLR = mask;
    ec52:	2202      	movs	r2, #2
    ec54:	f8c3 2308 	str.w	r2, [r3, #776]	; 0x308
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    ec58:	4b02      	ldr	r3, [pc, #8]	; (ec64 <nrfx_power_clock_irq_handler+0x64>)
}
    ec5a:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
            m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
    ec5e:	681b      	ldr	r3, [r3, #0]
    ec60:	2001      	movs	r0, #1
    ec62:	4718      	bx	r3
    ec64:	20000288 	.word	0x20000288

0000ec68 <pin_in_use_by_te>:
 *
 * @return True if pin uses GPIOTE task/event.
 */
static bool pin_in_use_by_te(uint32_t pin)
{
    return m_cb.pin_flags[pin] & PIN_FLAG_TE_USED;
    ec68:	4b03      	ldr	r3, [pc, #12]	; (ec78 <pin_in_use_by_te+0x10>)
    ec6a:	3008      	adds	r0, #8
    ec6c:	f833 0010 	ldrh.w	r0, [r3, r0, lsl #1]
}
    ec70:	f3c0 1040 	ubfx	r0, r0, #5, #1
    ec74:	4770      	bx	lr
    ec76:	bf00      	nop
    ec78:	20000024 	.word	0x20000024

0000ec7c <call_handler>:
    nrf_gpiote_event_t event = nrfx_gpiote_in_event_get(pin);
    return nrf_gpiote_event_address_get(NRF_GPIOTE, event);
}

static void call_handler(nrfx_gpiote_pin_t pin, nrfx_gpiote_trigger_t trigger)
{
    ec7c:	b570      	push	{r4, r5, r6, lr}
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    ec7e:	f100 0308 	add.w	r3, r0, #8
    ec82:	4c0c      	ldr	r4, [pc, #48]	; (ecb4 <call_handler+0x38>)
    ec84:	f834 3013 	ldrh.w	r3, [r4, r3, lsl #1]
    ec88:	05da      	lsls	r2, r3, #23
{
    ec8a:	4605      	mov	r5, r0
    ec8c:	460e      	mov	r6, r1
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    ec8e:	d507      	bpl.n	eca0 <call_handler+0x24>
    ec90:	f3c3 2343 	ubfx	r3, r3, #9, #4
    nrfx_gpiote_handler_config_t const * handler = channel_handler_get(pin);

    if (handler)
    {
        handler->handler(pin, trigger, handler->p_context);
    ec94:	eb04 02c3 	add.w	r2, r4, r3, lsl #3
    ec98:	f854 3033 	ldr.w	r3, [r4, r3, lsl #3]
    ec9c:	6852      	ldr	r2, [r2, #4]
    ec9e:	4798      	blx	r3
    }
    if (m_cb.global_handler.handler)
    eca0:	68a3      	ldr	r3, [r4, #8]
    eca2:	b12b      	cbz	r3, ecb0 <call_handler+0x34>
    {
        m_cb.global_handler.handler(pin, trigger, m_cb.global_handler.p_context);
    eca4:	68e2      	ldr	r2, [r4, #12]
    eca6:	4631      	mov	r1, r6
    eca8:	4628      	mov	r0, r5
    }
}
    ecaa:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
        m_cb.global_handler.handler(pin, trigger, m_cb.global_handler.p_context);
    ecae:	4718      	bx	r3
}
    ecb0:	bd70      	pop	{r4, r5, r6, pc}
    ecb2:	bf00      	nop
    ecb4:	20000024 	.word	0x20000024

0000ecb8 <release_handler>:
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    ecb8:	4a12      	ldr	r2, [pc, #72]	; (ed04 <release_handler+0x4c>)
    ecba:	3008      	adds	r0, #8
{
    ecbc:	b410      	push	{r4}
    int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]);
    ecbe:	f832 3010 	ldrh.w	r3, [r2, r0, lsl #1]
    ecc2:	05d9      	lsls	r1, r3, #23
    ecc4:	d51b      	bpl.n	ecfe <release_handler+0x46>
    ecc6:	f3c3 2143 	ubfx	r1, r3, #9, #4
    m_cb.pin_flags[pin] &= ~PIN_HANDLER_MASK;
    ecca:	f423 53f8 	bic.w	r3, r3, #7936	; 0x1f00
    ecce:	f822 3010 	strh.w	r3, [r2, r0, lsl #1]
    for (uint32_t i = 0; i < MAX_PIN_NUMBER; i++)
    ecd2:	f102 0410 	add.w	r4, r2, #16
    ecd6:	2000      	movs	r0, #0
        if (PIN_GET_HANDLER_ID(m_cb.pin_flags[i]) == handler_id)
    ecd8:	f834 3b02 	ldrh.w	r3, [r4], #2
    ecdc:	f413 7f80 	tst.w	r3, #256	; 0x100
    ece0:	d003      	beq.n	ecea <release_handler+0x32>
    ece2:	f3c3 2343 	ubfx	r3, r3, #9, #4
    ece6:	4299      	cmp	r1, r3
    ece8:	d009      	beq.n	ecfe <release_handler+0x46>
    for (uint32_t i = 0; i < MAX_PIN_NUMBER; i++)
    ecea:	3001      	adds	r0, #1
    ecec:	2820      	cmp	r0, #32
    ecee:	d1f3      	bne.n	ecd8 <release_handler+0x20>
        m_cb.handlers[handler_id].handler = NULL;
    ecf0:	2300      	movs	r3, #0
    ecf2:	f842 3031 	str.w	r3, [r2, r1, lsl #3]
        nrfx_err_t err = nrfx_flag32_free(&m_cb.available_evt_handlers, handler_id);
    ecf6:	4804      	ldr	r0, [pc, #16]	; (ed08 <release_handler+0x50>)
}
    ecf8:	bc10      	pop	{r4}
        nrfx_err_t err = nrfx_flag32_free(&m_cb.available_evt_handlers, handler_id);
    ecfa:	f7ff bea3 	b.w	ea44 <nrfx_flag32_free>
}
    ecfe:	bc10      	pop	{r4}
    ed00:	4770      	bx	lr
    ed02:	bf00      	nop
    ed04:	20000024 	.word	0x20000024
    ed08:	20000078 	.word	0x20000078

0000ed0c <pin_handler_trigger_uninit>:
{
    ed0c:	b538      	push	{r3, r4, r5, lr}
    ed0e:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin))
    ed10:	f7ff ffaa 	bl	ec68 <pin_in_use_by_te>
    ed14:	4c09      	ldr	r4, [pc, #36]	; (ed3c <pin_handler_trigger_uninit+0x30>)
    ed16:	f102 0508 	add.w	r5, r2, #8
    ed1a:	b140      	cbz	r0, ed2e <pin_handler_trigger_uninit+0x22>
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    ed1c:	f834 3015 	ldrh.w	r3, [r4, r5, lsl #1]
                         ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
}

NRF_STATIC_INLINE void nrf_gpiote_te_default(NRF_GPIOTE_Type * p_reg, uint32_t idx)
{
    p_reg->CONFIG[idx] = 0;
    ed20:	4907      	ldr	r1, [pc, #28]	; (ed40 <pin_handler_trigger_uninit+0x34>)
        nrf_gpiote_te_default(NRF_GPIOTE, pin_te_get(pin));
    ed22:	0b5b      	lsrs	r3, r3, #13
    ed24:	f503 73a2 	add.w	r3, r3, #324	; 0x144
    ed28:	2000      	movs	r0, #0
    ed2a:	f841 0023 	str.w	r0, [r1, r3, lsl #2]
    release_handler(pin);
    ed2e:	4610      	mov	r0, r2
    ed30:	f7ff ffc2 	bl	ecb8 <release_handler>
    m_cb.pin_flags[pin] = PIN_FLAG_NOT_USED;
    ed34:	2300      	movs	r3, #0
    ed36:	f824 3015 	strh.w	r3, [r4, r5, lsl #1]
}
    ed3a:	bd38      	pop	{r3, r4, r5, pc}
    ed3c:	20000024 	.word	0x20000024
    ed40:	40006000 	.word	0x40006000

0000ed44 <nrfx_gpiote_input_configure>:
{
    ed44:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
    ed48:	4604      	mov	r4, r0
    ed4a:	461e      	mov	r6, r3
    if (p_input_config)
    ed4c:	b309      	cbz	r1, ed92 <nrfx_gpiote_input_configure+0x4e>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    ed4e:	4f4d      	ldr	r7, [pc, #308]	; (ee84 <nrfx_gpiote_input_configure+0x140>)
    ed50:	f100 0808 	add.w	r8, r0, #8
    ed54:	f837 5018 	ldrh.w	r5, [r7, r8, lsl #1]
    return pin_is_output(pin) && pin_in_use_by_te(pin);
    ed58:	07ab      	lsls	r3, r5, #30
    ed5a:	d506      	bpl.n	ed6a <nrfx_gpiote_input_configure+0x26>
    ed5c:	f7ff ff84 	bl	ec68 <pin_in_use_by_te>
        if (pin_is_task_output(pin))
    ed60:	b118      	cbz	r0, ed6a <nrfx_gpiote_input_configure+0x26>
            return NRFX_ERROR_INVALID_PARAM;
    ed62:	4849      	ldr	r0, [pc, #292]	; (ee88 <nrfx_gpiote_input_configure+0x144>)
}
    ed64:	b002      	add	sp, #8
    ed66:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    *p_pin = pin_number & 0x1F;
    ed6a:	f004 001f 	and.w	r0, r4, #31
    ed6e:	0080      	lsls	r0, r0, #2
    ed70:	f100 40a0 	add.w	r0, r0, #1342177280	; 0x50000000
           ((uint32_t)(p_pull  ? *p_pull  : 0) << GPIO_PIN_CNF_PULL_Pos)  |
    ed74:	7809      	ldrb	r1, [r1, #0]
    uint32_t cnf = reg->PIN_CNF[pin_number];
    ed76:	f8d0 3700 	ldr.w	r3, [r0, #1792]	; 0x700
        m_cb.pin_flags[pin] &= ~PIN_FLAG_OUTPUT;
    ed7a:	f025 0502 	bic.w	r5, r5, #2
    cnf &= ~to_update;
    ed7e:	f023 030f 	bic.w	r3, r3, #15
        m_cb.pin_flags[pin] |= PIN_FLAG_IN_USE;
    ed82:	f045 0501 	orr.w	r5, r5, #1
    cnf |= ((uint32_t)(p_dir   ? *p_dir   : 0) << GPIO_PIN_CNF_DIR_Pos)   |
    ed86:	ea43 0381 	orr.w	r3, r3, r1, lsl #2
    ed8a:	f827 5018 	strh.w	r5, [r7, r8, lsl #1]
    reg->PIN_CNF[pin_number] = cnf;
    ed8e:	f8c0 3700 	str.w	r3, [r0, #1792]	; 0x700
    if (p_trigger_config)
    ed92:	b192      	cbz	r2, edba <nrfx_gpiote_input_configure+0x76>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    ed94:	4b3b      	ldr	r3, [pc, #236]	; (ee84 <nrfx_gpiote_input_configure+0x140>)
        nrfx_gpiote_trigger_t trigger = p_trigger_config->trigger;
    ed96:	7815      	ldrb	r5, [r2, #0]
        bool use_evt = p_trigger_config->p_in_channel ? true : false;
    ed98:	6852      	ldr	r2, [r2, #4]
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    ed9a:	f104 0008 	add.w	r0, r4, #8
    ed9e:	f833 1010 	ldrh.w	r1, [r3, r0, lsl #1]
        if (pin_is_output(pin))
    eda2:	078f      	lsls	r7, r1, #30
    eda4:	d50c      	bpl.n	edc0 <nrfx_gpiote_input_configure+0x7c>
            if (use_evt)
    eda6:	2a00      	cmp	r2, #0
    eda8:	d1db      	bne.n	ed62 <nrfx_gpiote_input_configure+0x1e>
        m_cb.pin_flags[pin] &= ~PIN_FLAG_TRIG_MODE_MASK;
    edaa:	f833 2010 	ldrh.w	r2, [r3, r0, lsl #1]
    edae:	f022 021c 	bic.w	r2, r2, #28
        m_cb.pin_flags[pin] |= PIN_FLAG_TRIG_MODE_SET(trigger);
    edb2:	ea42 0285 	orr.w	r2, r2, r5, lsl #2
    edb6:	f823 2010 	strh.w	r2, [r3, r0, lsl #1]
    if (p_handler_config)
    edba:	bbce      	cbnz	r6, ee30 <nrfx_gpiote_input_configure+0xec>
    return NRFX_SUCCESS;
    edbc:	4833      	ldr	r0, [pc, #204]	; (ee8c <nrfx_gpiote_input_configure+0x148>)
    edbe:	e7d1      	b.n	ed64 <nrfx_gpiote_input_configure+0x20>
            m_cb.pin_flags[pin] &= ~(PIN_TE_ID_MASK | PIN_FLAG_TE_USED);
    edc0:	f021 0120 	bic.w	r1, r1, #32
    edc4:	04c9      	lsls	r1, r1, #19
    edc6:	0cc9      	lsrs	r1, r1, #19
    edc8:	f823 1010 	strh.w	r1, [r3, r0, lsl #1]
            if (use_evt)
    edcc:	2a00      	cmp	r2, #0
    edce:	d0ec      	beq.n	edaa <nrfx_gpiote_input_configure+0x66>
                if (!edge)
    edd0:	2d03      	cmp	r5, #3
    edd2:	d8c6      	bhi.n	ed62 <nrfx_gpiote_input_configure+0x1e>
                uint8_t ch = *p_trigger_config->p_in_channel;
    edd4:	7817      	ldrb	r7, [r2, #0]
                if (trigger == NRFX_GPIOTE_TRIGGER_NONE)
    edd6:	b92d      	cbnz	r5, ede4 <nrfx_gpiote_input_configure+0xa0>
    edd8:	4a2d      	ldr	r2, [pc, #180]	; (ee90 <nrfx_gpiote_input_configure+0x14c>)
    edda:	f507 71a2 	add.w	r1, r7, #324	; 0x144
    edde:	f842 5021 	str.w	r5, [r2, r1, lsl #2]
#if defined(NRF9160_XXAA) || defined(NRF5340_XXAA)
    p_reg->CONFIG[idx] = 0;
#endif
}
    ede2:	e7e2      	b.n	edaa <nrfx_gpiote_input_configure+0x66>
   p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk;
    ede4:	00ba      	lsls	r2, r7, #2
    ede6:	f102 4280 	add.w	r2, r2, #1073741824	; 0x40000000
    edea:	f502 42c0 	add.w	r2, r2, #24576	; 0x6000
                    m_cb.pin_flags[pin] |= PIN_FLAG_TE_ID(ch);
    edee:	ea41 3147 	orr.w	r1, r1, r7, lsl #13
    edf2:	f8d2 c510 	ldr.w	ip, [r2, #1296]	; 0x510
    edf6:	f02c 0c03 	bic.w	ip, ip, #3
    edfa:	f8c2 c510 	str.w	ip, [r2, #1296]	; 0x510
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk);
    edfe:	f8d2 c510 	ldr.w	ip, [r2, #1296]	; 0x510
    ee02:	f42c 3c47 	bic.w	ip, ip, #203776	; 0x31c00
    ee06:	f42c 7c40 	bic.w	ip, ip, #768	; 0x300
    ee0a:	f8c2 c510 	str.w	ip, [r2, #1296]	; 0x510
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    ee0e:	f8d2 e510 	ldr.w	lr, [r2, #1296]	; 0x510
    ee12:	ea4f 2c04 	mov.w	ip, r4, lsl #8
    ee16:	f40c 5cf8 	and.w	ip, ip, #7936	; 0x1f00
    ee1a:	ea4e 4e05 	orr.w	lr, lr, r5, lsl #16
    ee1e:	ea4c 0c0e 	orr.w	ip, ip, lr
    ee22:	f041 0120 	orr.w	r1, r1, #32
    ee26:	f823 1010 	strh.w	r1, [r3, r0, lsl #1]
    ee2a:	f8c2 c510 	str.w	ip, [r2, #1296]	; 0x510
    ee2e:	e7bc      	b.n	edaa <nrfx_gpiote_input_configure+0x66>
        err = pin_handler_set(pin, p_handler_config->handler, p_handler_config->p_context);
    ee30:	e9d6 7600 	ldrd	r7, r6, [r6]
    release_handler(pin);
    ee34:	4620      	mov	r0, r4
    ee36:	f7ff ff3f 	bl	ecb8 <release_handler>
    if (!handler)
    ee3a:	2f00      	cmp	r7, #0
    ee3c:	d0be      	beq.n	edbc <nrfx_gpiote_input_configure+0x78>
        if ((m_cb.handlers[i].handler == handler) && (m_cb.handlers[i].p_context == p_context))
    ee3e:	4d11      	ldr	r5, [pc, #68]	; (ee84 <nrfx_gpiote_input_configure+0x140>)
    ee40:	682b      	ldr	r3, [r5, #0]
    ee42:	429f      	cmp	r7, r3
    ee44:	d104      	bne.n	ee50 <nrfx_gpiote_input_configure+0x10c>
    ee46:	686b      	ldr	r3, [r5, #4]
    ee48:	429e      	cmp	r6, r3
    ee4a:	d101      	bne.n	ee50 <nrfx_gpiote_input_configure+0x10c>
    ee4c:	2200      	movs	r2, #0
    ee4e:	e009      	b.n	ee64 <nrfx_gpiote_input_configure+0x120>
        err = nrfx_flag32_alloc(&m_cb.available_evt_handlers, &id);
    ee50:	4810      	ldr	r0, [pc, #64]	; (ee94 <nrfx_gpiote_input_configure+0x150>)
    ee52:	f10d 0107 	add.w	r1, sp, #7
    ee56:	f7ff fdcf 	bl	e9f8 <nrfx_flag32_alloc>
        if (err != NRFX_SUCCESS)
    ee5a:	4b0c      	ldr	r3, [pc, #48]	; (ee8c <nrfx_gpiote_input_configure+0x148>)
    ee5c:	4298      	cmp	r0, r3
    ee5e:	d181      	bne.n	ed64 <nrfx_gpiote_input_configure+0x20>
        handler_id = (int32_t)id;
    ee60:	f89d 2007 	ldrb.w	r2, [sp, #7]
    m_cb.handlers[handler_id].handler = handler;
    ee64:	f845 7032 	str.w	r7, [r5, r2, lsl #3]
    m_cb.handlers[handler_id].p_context = p_context;
    ee68:	eb05 03c2 	add.w	r3, r5, r2, lsl #3
    m_cb.pin_flags[pin] |= PIN_FLAG_HANDLER(handler_id);
    ee6c:	3408      	adds	r4, #8
    m_cb.handlers[handler_id].p_context = p_context;
    ee6e:	605e      	str	r6, [r3, #4]
    m_cb.pin_flags[pin] |= PIN_FLAG_HANDLER(handler_id);
    ee70:	f835 3014 	ldrh.w	r3, [r5, r4, lsl #1]
    ee74:	ea43 2342 	orr.w	r3, r3, r2, lsl #9
    ee78:	f443 7380 	orr.w	r3, r3, #256	; 0x100
    ee7c:	f825 3014 	strh.w	r3, [r5, r4, lsl #1]
    ee80:	e79c      	b.n	edbc <nrfx_gpiote_input_configure+0x78>
    ee82:	bf00      	nop
    ee84:	20000024 	.word	0x20000024
    ee88:	0bad0004 	.word	0x0bad0004
    ee8c:	0bad0000 	.word	0x0bad0000
    ee90:	40006000 	.word	0x40006000
    ee94:	20000078 	.word	0x20000078

0000ee98 <nrfx_gpiote_output_configure>:
{
    ee98:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    ee9a:	4604      	mov	r4, r0
    if (p_config)
    ee9c:	b371      	cbz	r1, eefc <nrfx_gpiote_output_configure+0x64>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    ee9e:	4e37      	ldr	r6, [pc, #220]	; (ef7c <nrfx_gpiote_output_configure+0xe4>)
    eea0:	f100 0708 	add.w	r7, r0, #8
    eea4:	f836 5017 	ldrh.w	r5, [r6, r7, lsl #1]
        if (pin_is_input(pin) && pin_in_use_by_te(pin))
    eea8:	07ab      	lsls	r3, r5, #30
    eeaa:	d404      	bmi.n	eeb6 <nrfx_gpiote_output_configure+0x1e>
    eeac:	f7ff fedc 	bl	ec68 <pin_in_use_by_te>
    eeb0:	b108      	cbz	r0, eeb6 <nrfx_gpiote_output_configure+0x1e>
    return NRFX_SUCCESS;
    eeb2:	4833      	ldr	r0, [pc, #204]	; (ef80 <nrfx_gpiote_output_configure+0xe8>)
}
    eeb4:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
        if (pin_has_trigger(pin) && (p_config->input_connect == NRF_GPIO_PIN_INPUT_DISCONNECT))
    eeb6:	f015 0f1c 	tst.w	r5, #28
    eeba:	784b      	ldrb	r3, [r1, #1]
    eebc:	d001      	beq.n	eec2 <nrfx_gpiote_output_configure+0x2a>
    eebe:	2b01      	cmp	r3, #1
    eec0:	d0f7      	beq.n	eeb2 <nrfx_gpiote_output_configure+0x1a>
    *p_pin = pin_number & 0x1F;
    eec2:	f004 001f 	and.w	r0, r4, #31
    eec6:	0080      	lsls	r0, r0, #2
    eec8:	f100 40a0 	add.w	r0, r0, #1342177280	; 0x50000000
           ((uint32_t)(p_drive ? *p_drive : 0) << GPIO_PIN_CNF_DRIVE_Pos) |
    eecc:	f891 e000 	ldrb.w	lr, [r1]
    uint32_t cnf = reg->PIN_CNF[pin_number];
    eed0:	f8d0 c700 	ldr.w	ip, [r0, #1792]	; 0x700
           ((uint32_t)(p_pull  ? *p_pull  : 0) << GPIO_PIN_CNF_PULL_Pos)  |
    eed4:	7889      	ldrb	r1, [r1, #2]
           ((uint32_t)(p_input ? *p_input : 0) << GPIO_PIN_CNF_INPUT_Pos) |
    eed6:	005b      	lsls	r3, r3, #1
    cnf &= ~to_update;
    eed8:	f42c 6ce1 	bic.w	ip, ip, #1800	; 0x708
    eedc:	ea43 230e 	orr.w	r3, r3, lr, lsl #8
    eee0:	f02c 0c07 	bic.w	ip, ip, #7
    eee4:	ea43 030c 	orr.w	r3, r3, ip
    eee8:	ea43 0381 	orr.w	r3, r3, r1, lsl #2
        m_cb.pin_flags[pin] |= PIN_FLAG_IN_USE | PIN_FLAG_OUTPUT;
    eeec:	f045 0503 	orr.w	r5, r5, #3
    cnf |= ((uint32_t)(p_dir   ? *p_dir   : 0) << GPIO_PIN_CNF_DIR_Pos)   |
    eef0:	f043 0301 	orr.w	r3, r3, #1
    eef4:	f826 5017 	strh.w	r5, [r6, r7, lsl #1]
    reg->PIN_CNF[pin_number] = cnf;
    eef8:	f8c0 3700 	str.w	r3, [r0, #1792]	; 0x700
    if (p_task_config)
    eefc:	b90a      	cbnz	r2, ef02 <nrfx_gpiote_output_configure+0x6a>
    return NRFX_SUCCESS;
    eefe:	4821      	ldr	r0, [pc, #132]	; (ef84 <nrfx_gpiote_output_configure+0xec>)
    ef00:	e7d8      	b.n	eeb4 <nrfx_gpiote_output_configure+0x1c>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    ef02:	4e1e      	ldr	r6, [pc, #120]	; (ef7c <nrfx_gpiote_output_configure+0xe4>)
    ef04:	f104 0708 	add.w	r7, r4, #8
    ef08:	f836 0017 	ldrh.w	r0, [r6, r7, lsl #1]
        if (pin_is_input(pin))
    ef0c:	0783      	lsls	r3, r0, #30
    ef0e:	d5d0      	bpl.n	eeb2 <nrfx_gpiote_output_configure+0x1a>
        uint32_t ch = p_task_config->task_ch;
    ef10:	f892 c000 	ldrb.w	ip, [r2]
    p_reg->CONFIG[idx] = 0;
    ef14:	4661      	mov	r1, ip
    ef16:	0089      	lsls	r1, r1, #2
        m_cb.pin_flags[pin] &= ~(PIN_FLAG_TE_USED | PIN_TE_ID_MASK);
    ef18:	f020 0020 	bic.w	r0, r0, #32
    ef1c:	f101 4180 	add.w	r1, r1, #1073741824	; 0x40000000
    ef20:	04c0      	lsls	r0, r0, #19
    ef22:	f501 41c0 	add.w	r1, r1, #24576	; 0x6000
    ef26:	0cc0      	lsrs	r0, r0, #19
    ef28:	f826 0017 	strh.w	r0, [r6, r7, lsl #1]
    ef2c:	2300      	movs	r3, #0
    ef2e:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
        if (p_task_config->polarity != NRF_GPIOTE_POLARITY_NONE)
    ef32:	7855      	ldrb	r5, [r2, #1]
    ef34:	2d00      	cmp	r5, #0
    ef36:	d0e2      	beq.n	eefe <nrfx_gpiote_output_configure+0x66>
  p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk |
    ef38:	f8d1 3510 	ldr.w	r3, [r1, #1296]	; 0x510
            nrf_gpiote_task_configure(NRF_GPIOTE, ch, pin,
    ef3c:	7892      	ldrb	r2, [r2, #2]
    ef3e:	f423 1398 	bic.w	r3, r3, #1245184	; 0x130000
    ef42:	f423 53f8 	bic.w	r3, r3, #7936	; 0x1f00
    ef46:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    ef4a:	f8d1 e510 	ldr.w	lr, [r1, #1296]	; 0x510
    ef4e:	0223      	lsls	r3, r4, #8
    ef50:	f403 53f8 	and.w	r3, r3, #7936	; 0x1f00
                        ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk) |
    ef54:	042d      	lsls	r5, r5, #16
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    ef56:	ea43 030e 	orr.w	r3, r3, lr
                        ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk) |
    ef5a:	f405 3540 	and.w	r5, r5, #196608	; 0x30000
                        ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
    ef5e:	0512      	lsls	r2, r2, #20
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    ef60:	432b      	orrs	r3, r5
                        ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
    ef62:	f402 1280 	and.w	r2, r2, #1048576	; 0x100000
            m_cb.pin_flags[pin] |= PIN_FLAG_TE_ID(ch);
    ef66:	ea40 304c 	orr.w	r0, r0, ip, lsl #13
  p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
    ef6a:	4313      	orrs	r3, r2
    ef6c:	f040 0020 	orr.w	r0, r0, #32
    ef70:	f826 0017 	strh.w	r0, [r6, r7, lsl #1]
    ef74:	f8c1 3510 	str.w	r3, [r1, #1296]	; 0x510
    ef78:	e7c1      	b.n	eefe <nrfx_gpiote_output_configure+0x66>
    ef7a:	bf00      	nop
    ef7c:	20000024 	.word	0x20000024
    ef80:	0bad0004 	.word	0x0bad0004
    ef84:	0bad0000 	.word	0x0bad0000

0000ef88 <nrfx_gpiote_global_callback_set>:
    m_cb.global_handler.handler = handler;
    ef88:	4b01      	ldr	r3, [pc, #4]	; (ef90 <nrfx_gpiote_global_callback_set+0x8>)
    m_cb.global_handler.p_context = p_context;
    ef8a:	e9c3 0102 	strd	r0, r1, [r3, #8]
}
    ef8e:	4770      	bx	lr
    ef90:	20000024 	.word	0x20000024

0000ef94 <nrfx_gpiote_channel_get>:
{
    ef94:	b508      	push	{r3, lr}
    ef96:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin))
    ef98:	f7ff fe66 	bl	ec68 <pin_in_use_by_te>
    ef9c:	b138      	cbz	r0, efae <nrfx_gpiote_channel_get+0x1a>
        *p_channel = PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    ef9e:	4b05      	ldr	r3, [pc, #20]	; (efb4 <nrfx_gpiote_channel_get+0x20>)
        return NRFX_SUCCESS;
    efa0:	4805      	ldr	r0, [pc, #20]	; (efb8 <nrfx_gpiote_channel_get+0x24>)
        *p_channel = PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    efa2:	3208      	adds	r2, #8
    efa4:	f833 3012 	ldrh.w	r3, [r3, r2, lsl #1]
    efa8:	0b5b      	lsrs	r3, r3, #13
    efaa:	700b      	strb	r3, [r1, #0]
}
    efac:	bd08      	pop	{r3, pc}
        return NRFX_ERROR_INVALID_PARAM;
    efae:	4803      	ldr	r0, [pc, #12]	; (efbc <nrfx_gpiote_channel_get+0x28>)
    efb0:	e7fc      	b.n	efac <nrfx_gpiote_channel_get+0x18>
    efb2:	bf00      	nop
    efb4:	20000024 	.word	0x20000024
    efb8:	0bad0000 	.word	0x0bad0000
    efbc:	0bad0004 	.word	0x0bad0004

0000efc0 <nrfx_gpiote_init>:
{
    efc0:	b538      	push	{r3, r4, r5, lr}
    if (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED)
    efc2:	4c0f      	ldr	r4, [pc, #60]	; (f000 <nrfx_gpiote_init+0x40>)
    efc4:	f894 5058 	ldrb.w	r5, [r4, #88]	; 0x58
    efc8:	b9bd      	cbnz	r5, effa <nrfx_gpiote_init+0x3a>
    memset(m_cb.pin_flags, 0, sizeof(m_cb.pin_flags));
    efca:	2240      	movs	r2, #64	; 0x40
    efcc:	4629      	mov	r1, r5
    efce:	f104 0010 	add.w	r0, r4, #16
    efd2:	f001 f954 	bl	1027e <memset>
    NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_GPIOTE));
    efd6:	2006      	movs	r0, #6
    efd8:	f7fe f930 	bl	d23c <arch_irq_enable>
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    efdc:	4b09      	ldr	r3, [pc, #36]	; (f004 <nrfx_gpiote_init+0x44>)
    return err_code;
    efde:	480a      	ldr	r0, [pc, #40]	; (f008 <nrfx_gpiote_init+0x48>)
    efe0:	f8c3 517c 	str.w	r5, [r3, #380]	; 0x17c
    efe4:	f8d3 217c 	ldr.w	r2, [r3, #380]	; 0x17c
    p_reg->INTENSET = mask;
    efe8:	f04f 4200 	mov.w	r2, #2147483648	; 0x80000000
    efec:	f8c3 2304 	str.w	r2, [r3, #772]	; 0x304
    m_cb.state = NRFX_DRV_STATE_INITIALIZED;
    eff0:	2301      	movs	r3, #1
    eff2:	f884 3058 	strb.w	r3, [r4, #88]	; 0x58
    m_cb.available_evt_handlers = NRFX_BIT_MASK(NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS);
    eff6:	6563      	str	r3, [r4, #84]	; 0x54
}
    eff8:	bd38      	pop	{r3, r4, r5, pc}
        return err_code;
    effa:	4804      	ldr	r0, [pc, #16]	; (f00c <nrfx_gpiote_init+0x4c>)
    effc:	e7fc      	b.n	eff8 <nrfx_gpiote_init+0x38>
    effe:	bf00      	nop
    f000:	20000024 	.word	0x20000024
    f004:	40006000 	.word	0x40006000
    f008:	0bad0000 	.word	0x0bad0000
    f00c:	0bad0005 	.word	0x0bad0005

0000f010 <nrfx_gpiote_is_init>:
    return (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED) ? true : false;
    f010:	4b03      	ldr	r3, [pc, #12]	; (f020 <nrfx_gpiote_is_init+0x10>)
    f012:	f893 0058 	ldrb.w	r0, [r3, #88]	; 0x58
}
    f016:	3800      	subs	r0, #0
    f018:	bf18      	it	ne
    f01a:	2001      	movne	r0, #1
    f01c:	4770      	bx	lr
    f01e:	bf00      	nop
    f020:	20000024 	.word	0x20000024

0000f024 <nrfx_gpiote_channel_free>:
{
    f024:	4601      	mov	r1, r0
    return nrfx_flag32_free(&m_cb.available_channels_mask, channel);
    f026:	4801      	ldr	r0, [pc, #4]	; (f02c <nrfx_gpiote_channel_free+0x8>)
    f028:	f7ff bd0c 	b.w	ea44 <nrfx_flag32_free>
    f02c:	20000074 	.word	0x20000074

0000f030 <nrfx_gpiote_channel_alloc>:
{
    f030:	4601      	mov	r1, r0
    return nrfx_flag32_alloc(&m_cb.available_channels_mask, p_channel);
    f032:	4801      	ldr	r0, [pc, #4]	; (f038 <nrfx_gpiote_channel_alloc+0x8>)
    f034:	f7ff bce0 	b.w	e9f8 <nrfx_flag32_alloc>
    f038:	20000074 	.word	0x20000074

0000f03c <nrfx_gpiote_trigger_enable>:
{
    f03c:	b510      	push	{r4, lr}
    f03e:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    f040:	f7ff fe12 	bl	ec68 <pin_in_use_by_te>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    f044:	f102 0408 	add.w	r4, r2, #8
    f048:	4b1c      	ldr	r3, [pc, #112]	; (f0bc <nrfx_gpiote_trigger_enable+0x80>)
    f04a:	f833 3014 	ldrh.w	r3, [r3, r4, lsl #1]
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    f04e:	b1e0      	cbz	r0, f08a <nrfx_gpiote_trigger_enable+0x4e>
    f050:	f013 0402 	ands.w	r4, r3, #2
    f054:	d119      	bne.n	f08a <nrfx_gpiote_trigger_enable+0x4e>
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    f056:	0b5b      	lsrs	r3, r3, #13
#endif

NRF_STATIC_INLINE nrf_gpiote_event_t nrf_gpiote_in_event_get(uint8_t index)
{
    NRFX_ASSERT(index < GPIOTE_CH_NUM);
    return (nrf_gpiote_event_t)NRFX_OFFSETOF(NRF_GPIOTE_Type, EVENTS_IN[index]);
    f058:	009a      	lsls	r2, r3, #2
    return ((uint32_t)p_reg + event);
    f05a:	f102 4080 	add.w	r0, r2, #1073741824	; 0x40000000
    f05e:	f500 40c2 	add.w	r0, r0, #24832	; 0x6100
    f062:	f102 4280 	add.w	r2, r2, #1073741824	; 0x40000000
    f066:	f502 42c0 	add.w	r2, r2, #24576	; 0x6000
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    f06a:	6004      	str	r4, [r0, #0]
    f06c:	6800      	ldr	r0, [r0, #0]
   p_reg->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event;
    f06e:	f8d2 0510 	ldr.w	r0, [r2, #1296]	; 0x510
    f072:	f040 0001 	orr.w	r0, r0, #1
    f076:	f8c2 0510 	str.w	r0, [r2, #1296]	; 0x510
        if (int_enable)
    f07a:	b129      	cbz	r1, f088 <nrfx_gpiote_trigger_enable+0x4c>
            nrf_gpiote_int_enable(NRF_GPIOTE, NRFX_BIT(ch));
    f07c:	2201      	movs	r2, #1
    f07e:	fa02 f303 	lsl.w	r3, r2, r3
    p_reg->INTENSET = mask;
    f082:	4a0f      	ldr	r2, [pc, #60]	; (f0c0 <nrfx_gpiote_trigger_enable+0x84>)
    f084:	f8c2 3304 	str.w	r3, [r2, #772]	; 0x304
}
    f088:	bd10      	pop	{r4, pc}
    nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    f08a:	f3c3 0382 	ubfx	r3, r3, #2, #3
    if (trigger == NRFX_GPIOTE_TRIGGER_LOW)
    f08e:	2b04      	cmp	r3, #4
    f090:	d010      	beq.n	f0b4 <nrfx_gpiote_trigger_enable+0x78>
    else if (trigger == NRFX_GPIOTE_TRIGGER_HIGH)
    f092:	2b05      	cmp	r3, #5
    f094:	d010      	beq.n	f0b8 <nrfx_gpiote_trigger_enable+0x7c>
    return p_reg->IN;
    f096:	f04f 43a0 	mov.w	r3, #1342177280	; 0x50000000
    f09a:	f8d3 1510 	ldr.w	r1, [r3, #1296]	; 0x510
    *p_pin = pin_number & 0x1F;
    f09e:	f002 031f 	and.w	r3, r2, #31
    return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL);
    f0a2:	40d9      	lsrs	r1, r3
    f0a4:	f001 0101 	and.w	r1, r1, #1
        sense = nrf_gpio_pin_read(pin) ? NRF_GPIO_PIN_SENSE_LOW : NRF_GPIO_PIN_SENSE_HIGH;
    f0a8:	3102      	adds	r1, #2
}
    f0aa:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
        nrf_gpio_cfg_sense_set(pin, get_initial_sense(pin));
    f0ae:	4610      	mov	r0, r2
    f0b0:	f001 bb41 	b.w	10736 <nrf_gpio_cfg_sense_set>
        sense = NRF_GPIO_PIN_SENSE_LOW;
    f0b4:	2103      	movs	r1, #3
    f0b6:	e7f8      	b.n	f0aa <nrfx_gpiote_trigger_enable+0x6e>
        sense = NRF_GPIO_PIN_SENSE_HIGH;
    f0b8:	2102      	movs	r1, #2
    f0ba:	e7f6      	b.n	f0aa <nrfx_gpiote_trigger_enable+0x6e>
    f0bc:	20000024 	.word	0x20000024
    f0c0:	40006000 	.word	0x40006000

0000f0c4 <nrfx_gpiote_trigger_disable>:
{
    f0c4:	b508      	push	{r3, lr}
    f0c6:	4602      	mov	r2, r0
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    f0c8:	f7ff fdce 	bl	ec68 <pin_in_use_by_te>
    f0cc:	b1c0      	cbz	r0, f100 <nrfx_gpiote_trigger_disable+0x3c>
    return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]);
    f0ce:	f102 0108 	add.w	r1, r2, #8
    f0d2:	4b0e      	ldr	r3, [pc, #56]	; (f10c <nrfx_gpiote_trigger_disable+0x48>)
    f0d4:	f833 3011 	ldrh.w	r3, [r3, r1, lsl #1]
    if (pin_in_use_by_te(pin) && pin_is_input(pin))
    f0d8:	0799      	lsls	r1, r3, #30
    f0da:	d411      	bmi.n	f100 <nrfx_gpiote_trigger_disable+0x3c>
    return PIN_GET_TE_ID(m_cb.pin_flags[pin]);
    f0dc:	0b5b      	lsrs	r3, r3, #13
        nrf_gpiote_int_disable(NRF_GPIOTE, NRFX_BIT(ch));
    f0de:	2201      	movs	r2, #1
    f0e0:	409a      	lsls	r2, r3
    p_reg->INTENCLR = mask;
    f0e2:	009b      	lsls	r3, r3, #2
    f0e4:	490a      	ldr	r1, [pc, #40]	; (f110 <nrfx_gpiote_trigger_disable+0x4c>)
    f0e6:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    f0ea:	f503 43c0 	add.w	r3, r3, #24576	; 0x6000
    f0ee:	f8c1 2308 	str.w	r2, [r1, #776]	; 0x308
   p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk;
    f0f2:	f8d3 2510 	ldr.w	r2, [r3, #1296]	; 0x510
    f0f6:	f022 0203 	bic.w	r2, r2, #3
    f0fa:	f8c3 2510 	str.w	r2, [r3, #1296]	; 0x510
}
    f0fe:	bd08      	pop	{r3, pc}
    f100:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
        nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE);
    f104:	2100      	movs	r1, #0
    f106:	4610      	mov	r0, r2
    f108:	f001 bb15 	b.w	10736 <nrf_gpio_cfg_sense_set>
    f10c:	20000024 	.word	0x20000024
    f110:	40006000 	.word	0x40006000

0000f114 <nrfx_gpiote_pin_uninit>:
    return m_cb.pin_flags[pin] & PIN_FLAG_IN_USE;
    f114:	4b0d      	ldr	r3, [pc, #52]	; (f14c <nrfx_gpiote_pin_uninit+0x38>)
    f116:	f100 0208 	add.w	r2, r0, #8
{
    f11a:	b510      	push	{r4, lr}
    return m_cb.pin_flags[pin] & PIN_FLAG_IN_USE;
    f11c:	f833 3012 	ldrh.w	r3, [r3, r2, lsl #1]
    if (!pin_in_use(pin))
    f120:	07db      	lsls	r3, r3, #31
{
    f122:	4604      	mov	r4, r0
    if (!pin_in_use(pin))
    f124:	d50f      	bpl.n	f146 <nrfx_gpiote_pin_uninit+0x32>
    nrfx_gpiote_trigger_disable(pin);
    f126:	f7ff ffcd 	bl	f0c4 <nrfx_gpiote_trigger_disable>
    pin_handler_trigger_uninit(pin);
    f12a:	4620      	mov	r0, r4
    *p_pin = pin_number & 0x1F;
    f12c:	f004 041f 	and.w	r4, r4, #31
    f130:	f7ff fdec 	bl	ed0c <pin_handler_trigger_uninit>
    reg->PIN_CNF[pin_number] = cnf;
    f134:	f504 74e0 	add.w	r4, r4, #448	; 0x1c0
    f138:	f04f 43a0 	mov.w	r3, #1342177280	; 0x50000000
    f13c:	2202      	movs	r2, #2
    f13e:	f843 2024 	str.w	r2, [r3, r4, lsl #2]
    f142:	4803      	ldr	r0, [pc, #12]	; (f150 <nrfx_gpiote_pin_uninit+0x3c>)
}
    f144:	bd10      	pop	{r4, pc}
        return NRFX_ERROR_INVALID_PARAM;
    f146:	4803      	ldr	r0, [pc, #12]	; (f154 <nrfx_gpiote_pin_uninit+0x40>)
    f148:	e7fc      	b.n	f144 <nrfx_gpiote_pin_uninit+0x30>
    f14a:	bf00      	nop
    f14c:	20000024 	.word	0x20000024
    f150:	0bad0000 	.word	0x0bad0000
    f154:	0bad0004 	.word	0x0bad0004

0000f158 <nrfx_gpiote_irq_handler>:
        call_handler(pin, gpiote_polarity_to_trigger(polarity));
    }
}

void nrfx_gpiote_irq_handler(void)
{
    f158:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
    f15c:	4b4e      	ldr	r3, [pc, #312]	; (f298 <nrfx_gpiote_irq_handler+0x140>)
    return p_reg->INTENSET & mask;
    f15e:	484f      	ldr	r0, [pc, #316]	; (f29c <nrfx_gpiote_irq_handler+0x144>)
    uint32_t i;
    nrf_gpiote_event_t event = NRF_GPIOTE_EVENT_IN_0;
    uint32_t mask = (uint32_t)NRF_GPIOTE_INT_IN0_MASK;

    /* collect status of all GPIOTE pin events. Processing is done once all are collected and cleared.*/
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    f160:	494f      	ldr	r1, [pc, #316]	; (f2a0 <nrfx_gpiote_irq_handler+0x148>)
    uint32_t status = 0;
    f162:	2500      	movs	r5, #0
    uint32_t mask = (uint32_t)NRF_GPIOTE_INT_IN0_MASK;
    f164:	2201      	movs	r2, #1
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    f166:	462c      	mov	r4, r5
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    f168:	681e      	ldr	r6, [r3, #0]
    {
        if (nrf_gpiote_event_check(NRF_GPIOTE, event) &&
    f16a:	b136      	cbz	r6, f17a <nrfx_gpiote_irq_handler+0x22>
    return p_reg->INTENSET & mask;
    f16c:	f8d0 6304 	ldr.w	r6, [r0, #772]	; 0x304
    f170:	4216      	tst	r6, r2
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    f172:	bf1e      	ittt	ne
    f174:	601c      	strne	r4, [r3, #0]
    f176:	681e      	ldrne	r6, [r3, #0]
            nrf_gpiote_int_enable_check(NRF_GPIOTE, mask))
        {
            nrf_gpiote_event_clear(NRF_GPIOTE, event);
            status |= mask;
    f178:	4315      	orrne	r5, r2
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    f17a:	3304      	adds	r3, #4
    f17c:	428b      	cmp	r3, r1
        }
        mask <<= 1;
    f17e:	ea4f 0242 	mov.w	r2, r2, lsl #1
    for (i = 0; i < GPIOTE_CH_NUM; i++)
    f182:	d1f1      	bne.n	f168 <nrfx_gpiote_irq_handler+0x10>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
    f184:	4b45      	ldr	r3, [pc, #276]	; (f29c <nrfx_gpiote_irq_handler+0x144>)
    f186:	f8d3 317c 	ldr.w	r3, [r3, #380]	; 0x17c
         * in ascending order. */
        event = (nrf_gpiote_event_t)((uint32_t)event + sizeof(uint32_t));
    }

    /* handle PORT event */
    if (nrf_gpiote_event_check(NRF_GPIOTE, NRF_GPIOTE_EVENT_PORT))
    f18a:	b1bb      	cbz	r3, f1bc <nrfx_gpiote_irq_handler+0x64>
        *p_masks = gpio_regs[i]->LATCH;
    f18c:	f04f 46a0 	mov.w	r6, #1342177280	; 0x50000000
    f190:	f8d6 3520 	ldr.w	r3, [r6, #1312]	; 0x520
    f194:	9301      	str	r3, [sp, #4]
        gpio_regs[i]->LATCH = *p_masks;
    f196:	f8c6 3520 	str.w	r3, [r6, #1312]	; 0x520
__STATIC_INLINE void nrf_bitmask_bit_clear(uint32_t bit, void * p_mask)
{
    uint8_t * p_mask8 = (uint8_t *)p_mask;
    uint32_t byte_idx = BITMASK_BYTE_GET(bit);
    bit = BITMASK_RELBIT_GET(bit);
    p_mask8[byte_idx] &= ~(1 << bit);
    f19a:	af01      	add	r7, sp, #4
    f19c:	f04f 0801 	mov.w	r8, #1
            while (latch[i])
    f1a0:	9c01      	ldr	r4, [sp, #4]
    f1a2:	b96c      	cbnz	r4, f1c0 <nrfx_gpiote_irq_handler+0x68>
    *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
    f1a4:	4b3d      	ldr	r3, [pc, #244]	; (f29c <nrfx_gpiote_irq_handler+0x144>)
    f1a6:	f8c3 417c 	str.w	r4, [r3, #380]	; 0x17c
    f1aa:	f8d3 317c 	ldr.w	r3, [r3, #380]	; 0x17c
        *p_masks = gpio_regs[i]->LATCH;
    f1ae:	f8d6 3520 	ldr.w	r3, [r6, #1312]	; 0x520
    f1b2:	9301      	str	r3, [sp, #4]
        gpio_regs[i]->LATCH = *p_masks;
    f1b4:	f8c6 3520 	str.w	r3, [r6, #1312]	; 0x520
        if (latch[port_idx])
    f1b8:	2b00      	cmp	r3, #0
    f1ba:	d1ee      	bne.n	f19a <nrfx_gpiote_irq_handler+0x42>
        mask &= ~NRFX_BIT(ch);
    f1bc:	2401      	movs	r4, #1
    f1be:	e066      	b.n	f28e <nrfx_gpiote_irq_handler+0x136>
                uint32_t pin = NRF_CTZ(latch[i]);
    f1c0:	fa94 f4a4 	rbit	r4, r4
    f1c4:	fab4 f484 	clz	r4, r4
                nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    f1c8:	4a36      	ldr	r2, [pc, #216]	; (f2a4 <nrfx_gpiote_irq_handler+0x14c>)
    f1ca:	f104 0308 	add.w	r3, r4, #8
    uint32_t byte_idx = BITMASK_BYTE_GET(bit);
    f1ce:	08e0      	lsrs	r0, r4, #3
    f1d0:	f832 1013 	ldrh.w	r1, [r2, r3, lsl #1]
    bit = BITMASK_RELBIT_GET(bit);
    f1d4:	f004 0307 	and.w	r3, r4, #7
    p_mask8[byte_idx] &= ~(1 << bit);
    f1d8:	fa08 f203 	lsl.w	r2, r8, r3
    f1dc:	5c3b      	ldrb	r3, [r7, r0]
    f1de:	ea23 0302 	bic.w	r3, r3, r2
    f1e2:	543b      	strb	r3, [r7, r0]
    f1e4:	00a3      	lsls	r3, r4, #2
    f1e6:	f103 49a0 	add.w	r9, r3, #1342177280	; 0x50000000
    f1ea:	f3c1 0a82 	ubfx	sl, r1, #2, #3
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    f1ee:	f8d9 2700 	ldr.w	r2, [r9, #1792]	; 0x700
    if (is_level(trigger))
    f1f2:	06cb      	lsls	r3, r1, #27
                nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]);
    f1f4:	46d3      	mov	fp, sl
                                   GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos);
    f1f6:	f3c2 4201 	ubfx	r2, r2, #16, #2
    if (is_level(trigger))
    f1fa:	d518      	bpl.n	f22e <nrfx_gpiote_irq_handler+0xd6>
        call_handler(pin, trigger);
    f1fc:	4659      	mov	r1, fp
    f1fe:	4620      	mov	r0, r4
    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
    f200:	fa5f fa82 	uxtb.w	sl, r2
    f204:	f7ff fd3a 	bl	ec7c <call_handler>
    f208:	f8d9 3700 	ldr.w	r3, [r9, #1792]	; 0x700
        if (nrf_gpio_pin_sense_get(pin) == sense)
    f20c:	f3c3 4301 	ubfx	r3, r3, #16, #2
    f210:	459a      	cmp	sl, r3
    f212:	d107      	bne.n	f224 <nrfx_gpiote_irq_handler+0xcc>
            nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE);
    f214:	2100      	movs	r1, #0
    f216:	4620      	mov	r0, r4
    f218:	f001 fa8d 	bl	10736 <nrf_gpio_cfg_sense_set>
            nrf_gpio_cfg_sense_set(pin, sense);
    f21c:	4651      	mov	r1, sl
    f21e:	4620      	mov	r0, r4
    f220:	f001 fa89 	bl	10736 <nrf_gpio_cfg_sense_set>
    reg->LATCH = (1 << pin_number);
    f224:	fa08 f404 	lsl.w	r4, r8, r4
    f228:	f8c6 4520 	str.w	r4, [r6, #1312]	; 0x520
}
    f22c:	e7b8      	b.n	f1a0 <nrfx_gpiote_irq_handler+0x48>
                NRF_GPIO_PIN_SENSE_LOW : NRF_GPIO_PIN_SENSE_HIGH;
    f22e:	2a02      	cmp	r2, #2
        nrf_gpio_cfg_sense_set(pin, next_sense);
    f230:	bf0c      	ite	eq
    f232:	2103      	moveq	r1, #3
    f234:	2102      	movne	r1, #2
    f236:	4620      	mov	r0, r4
    f238:	f001 fa7d 	bl	10736 <nrf_gpio_cfg_sense_set>
        if ((trigger == NRFX_GPIOTE_TRIGGER_TOGGLE) ||
    f23c:	f1ba 0f03 	cmp.w	sl, #3
    f240:	d004      	beq.n	f24c <nrfx_gpiote_irq_handler+0xf4>
    f242:	2a02      	cmp	r2, #2
    f244:	d107      	bne.n	f256 <nrfx_gpiote_irq_handler+0xfe>
            (sense == NRF_GPIO_PIN_SENSE_HIGH && trigger == NRFX_GPIOTE_TRIGGER_LOTOHI) ||
    f246:	f1ba 0f01 	cmp.w	sl, #1
            (sense == NRF_GPIO_PIN_SENSE_LOW && trigger == NRFX_GPIOTE_TRIGGER_HITOLO))
    f24a:	d1eb      	bne.n	f224 <nrfx_gpiote_irq_handler+0xcc>
            call_handler(pin, trigger);
    f24c:	4659      	mov	r1, fp
    f24e:	4620      	mov	r0, r4
    f250:	f7ff fd14 	bl	ec7c <call_handler>
    f254:	e7e6      	b.n	f224 <nrfx_gpiote_irq_handler+0xcc>
            (sense == NRF_GPIO_PIN_SENSE_HIGH && trigger == NRFX_GPIOTE_TRIGGER_LOTOHI) ||
    f256:	2a03      	cmp	r2, #3
    f258:	d1e4      	bne.n	f224 <nrfx_gpiote_irq_handler+0xcc>
            (sense == NRF_GPIO_PIN_SENSE_LOW && trigger == NRFX_GPIOTE_TRIGGER_HITOLO))
    f25a:	f1ba 0f02 	cmp.w	sl, #2
    f25e:	e7f4      	b.n	f24a <nrfx_gpiote_irq_handler+0xf2>
        uint32_t ch = NRF_CTZ(mask);
    f260:	fa95 f3a5 	rbit	r3, r5
    f264:	fab3 f383 	clz	r3, r3
        mask &= ~NRFX_BIT(ch);
    f268:	fa04 f203 	lsl.w	r2, r4, r3
    f26c:	009b      	lsls	r3, r3, #2
    f26e:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
    f272:	f503 43c0 	add.w	r3, r3, #24576	; 0x6000
    f276:	ea25 0502 	bic.w	r5, r5, r2
    return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
    f27a:	f8d3 0510 	ldr.w	r0, [r3, #1296]	; 0x510
    return (nrf_gpiote_polarity_t)((p_reg->CONFIG[idx] & GPIOTE_CONFIG_POLARITY_Msk) >>
    f27e:	f8d3 1510 	ldr.w	r1, [r3, #1296]	; 0x510
        call_handler(pin, gpiote_polarity_to_trigger(polarity));
    f282:	f3c0 2004 	ubfx	r0, r0, #8, #5
    f286:	f3c1 4101 	ubfx	r1, r1, #16, #2
    f28a:	f7ff fcf7 	bl	ec7c <call_handler>
    while (mask)
    f28e:	2d00      	cmp	r5, #0
    f290:	d1e6      	bne.n	f260 <nrfx_gpiote_irq_handler+0x108>
        port_event_handle();
    }

    /* Process pin events. */
    gpiote_evt_handle(status);
}
    f292:	b003      	add	sp, #12
    f294:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    f298:	40006100 	.word	0x40006100
    f29c:	40006000 	.word	0x40006000
    f2a0:	40006120 	.word	0x40006120
    f2a4:	20000024 	.word	0x20000024

0000f2a8 <nrfx_ppi_channel_alloc>:
    nrfx_flag32_init(&m_groups_allocated, NRFX_PPI_ALL_APP_GROUPS_MASK);
}


nrfx_err_t nrfx_ppi_channel_alloc(nrf_ppi_channel_t * p_channel)
{
    f2a8:	4601      	mov	r1, r0
    return nrfx_flag32_alloc(&m_channels_allocated, (uint8_t *)p_channel);
    f2aa:	4801      	ldr	r0, [pc, #4]	; (f2b0 <nrfx_ppi_channel_alloc+0x8>)
    f2ac:	f7ff bba4 	b.w	e9f8 <nrfx_flag32_alloc>
    f2b0:	20000080 	.word	0x20000080

0000f2b4 <_DoInit>:
                      _DoInit();                                                                     \
                    }                                                                                \
                  } while (0);                                                                       \
                }

static void _DoInit(void) {
    f2b4:	b510      	push	{r4, lr}
  volatile SEGGER_RTT_CB* p;   // Volatile to make sure that compiler cannot change the order of accesses to the control block
  //
  // Initialize control block
  //
  p                     = (volatile SEGGER_RTT_CB*)((char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access control block uncached so that nothing in the cache ever becomes dirty and all changes are visible in HW directly
  p->MaxNumUpBuffers    = SEGGER_RTT_MAX_NUM_UP_BUFFERS;
    f2b6:	4c14      	ldr	r4, [pc, #80]	; (f308 <_DoInit+0x54>)
  p->MaxNumDownBuffers  = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS;
  //
  // Initialize up buffer 0
  //
  p->aUp[0].sName         = "Terminal";
    f2b8:	4a14      	ldr	r2, [pc, #80]	; (f30c <_DoInit+0x58>)
  //
  // Finish initialization of the control block.
  // Copy Id string in three steps to make sure "SEGGER RTT" is not found
  // in initializer memory (usually flash) by J-Link
  //
  STRCPY((char*)&p->acID[7], "RTT");
    f2ba:	4915      	ldr	r1, [pc, #84]	; (f310 <_DoInit+0x5c>)
  p->MaxNumUpBuffers    = SEGGER_RTT_MAX_NUM_UP_BUFFERS;
    f2bc:	2303      	movs	r3, #3
    f2be:	6123      	str	r3, [r4, #16]
  p->MaxNumDownBuffers  = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS;
    f2c0:	6163      	str	r3, [r4, #20]
  p->aUp[0].pBuffer       = _acUpBuffer;
    f2c2:	4b14      	ldr	r3, [pc, #80]	; (f314 <_DoInit+0x60>)
  p->aUp[0].sName         = "Terminal";
    f2c4:	61a2      	str	r2, [r4, #24]
  p->aUp[0].pBuffer       = _acUpBuffer;
    f2c6:	61e3      	str	r3, [r4, #28]
  p->aUp[0].SizeOfBuffer  = BUFFER_SIZE_UP;
    f2c8:	f44f 6380 	mov.w	r3, #1024	; 0x400
    f2cc:	6223      	str	r3, [r4, #32]
  p->aUp[0].RdOff         = 0u;
    f2ce:	2300      	movs	r3, #0
    f2d0:	62a3      	str	r3, [r4, #40]	; 0x28
  p->aUp[0].WrOff         = 0u;
    f2d2:	6263      	str	r3, [r4, #36]	; 0x24
  p->aUp[0].Flags         = SEGGER_RTT_MODE_DEFAULT;
    f2d4:	62e3      	str	r3, [r4, #44]	; 0x2c
  p->aDown[0].sName         = "Terminal";
    f2d6:	6622      	str	r2, [r4, #96]	; 0x60
  p->aDown[0].pBuffer       = _acDownBuffer;
    f2d8:	4a0f      	ldr	r2, [pc, #60]	; (f318 <_DoInit+0x64>)
    f2da:	6662      	str	r2, [r4, #100]	; 0x64
  STRCPY((char*)&p->acID[7], "RTT");
    f2dc:	1de0      	adds	r0, r4, #7
  p->aDown[0].SizeOfBuffer  = BUFFER_SIZE_DOWN;
    f2de:	2210      	movs	r2, #16
    f2e0:	66a2      	str	r2, [r4, #104]	; 0x68
  p->aDown[0].RdOff         = 0u;
    f2e2:	6723      	str	r3, [r4, #112]	; 0x70
  p->aDown[0].WrOff         = 0u;
    f2e4:	66e3      	str	r3, [r4, #108]	; 0x6c
  p->aDown[0].Flags         = SEGGER_RTT_MODE_DEFAULT;
    f2e6:	6763      	str	r3, [r4, #116]	; 0x74
  STRCPY((char*)&p->acID[7], "RTT");
    f2e8:	f000 ffa4 	bl	10234 <strcpy>
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
    f2ec:	f3bf 8f5f 	dmb	sy
  STRCPY((char*)&p->acID[0], "SEGGER");
    f2f0:	490a      	ldr	r1, [pc, #40]	; (f31c <_DoInit+0x68>)
    f2f2:	4620      	mov	r0, r4
    f2f4:	f000 ff9e 	bl	10234 <strcpy>
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
    f2f8:	f3bf 8f5f 	dmb	sy
  p->acID[6] = ' ';
    f2fc:	2320      	movs	r3, #32
    f2fe:	71a3      	strb	r3, [r4, #6]
  RTT__DMB();                       // Force order of memory accessed inside core for cores that allow to change the order
    f300:	f3bf 8f5f 	dmb	sy
}
    f304:	bd10      	pop	{r4, pc}
    f306:	bf00      	nop
    f308:	20000290 	.word	0x20000290
    f30c:	00010cdb 	.word	0x00010cdb
    f310:	00010ce4 	.word	0x00010ce4
    f314:	20000382 	.word	0x20000382
    f318:	20000372 	.word	0x20000372
    f31c:	00010ce8 	.word	0x00010ce8

0000f320 <z_sys_init_run_level>:
		/* End marker */
		__init_end,
	};
	const struct init_entry *entry;

	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    f320:	4b0e      	ldr	r3, [pc, #56]	; (f35c <z_sys_init_run_level+0x3c>)
{
    f322:	b570      	push	{r4, r5, r6, lr}
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    f324:	f853 4020 	ldr.w	r4, [r3, r0, lsl #2]
    f328:	3001      	adds	r0, #1
    f32a:	f853 6020 	ldr.w	r6, [r3, r0, lsl #2]
    f32e:	42a6      	cmp	r6, r4
    f330:	d800      	bhi.n	f334 <z_sys_init_run_level+0x14>
				dev->state->init_res = rc;
			}
			dev->state->initialized = true;
		}
	}
}
    f332:	bd70      	pop	{r4, r5, r6, pc}
		int rc = entry->init(dev);
    f334:	e9d4 3500 	ldrd	r3, r5, [r4]
    f338:	4628      	mov	r0, r5
    f33a:	4798      	blx	r3
		if (dev != NULL) {
    f33c:	b165      	cbz	r5, f358 <z_sys_init_run_level+0x38>
				dev->state->init_res = rc;
    f33e:	68eb      	ldr	r3, [r5, #12]
			if (rc != 0) {
    f340:	b130      	cbz	r0, f350 <z_sys_init_run_level+0x30>
				if (rc < 0) {
    f342:	2800      	cmp	r0, #0
    f344:	bfb8      	it	lt
    f346:	4240      	neglt	r0, r0
				dev->state->init_res = rc;
    f348:	28ff      	cmp	r0, #255	; 0xff
    f34a:	bfa8      	it	ge
    f34c:	20ff      	movge	r0, #255	; 0xff
    f34e:	7018      	strb	r0, [r3, #0]
			dev->state->initialized = true;
    f350:	785a      	ldrb	r2, [r3, #1]
    f352:	f042 0201 	orr.w	r2, r2, #1
    f356:	705a      	strb	r2, [r3, #1]
	for (entry = levels[level]; entry < levels[level+1]; entry++) {
    f358:	3408      	adds	r4, #8
    f35a:	e7e8      	b.n	f32e <z_sys_init_run_level+0xe>
    f35c:	00010c64 	.word	0x00010c64

0000f360 <bg_thread_main>:
 * This routine completes kernel initialization by invoking the remaining
 * init functions, then invokes application's main() routine.
 */
__boot_func
static void bg_thread_main(void *unused1, void *unused2, void *unused3)
{
    f360:	b508      	push	{r3, lr}
	 * may perform memory management tasks (except for z_phys_map() which
	 * is allowed at any time)
	 */
	z_mem_manage_init();
#endif /* CONFIG_MMU */
	z_sys_post_kernel = true;
    f362:	4b0a      	ldr	r3, [pc, #40]	; (f38c <bg_thread_main+0x2c>)
    f364:	2201      	movs	r2, #1

	z_sys_init_run_level(_SYS_INIT_LEVEL_POST_KERNEL);
    f366:	2002      	movs	r0, #2
	z_sys_post_kernel = true;
    f368:	701a      	strb	r2, [r3, #0]
	z_sys_init_run_level(_SYS_INIT_LEVEL_POST_KERNEL);
    f36a:	f7ff ffd9 	bl	f320 <z_sys_init_run_level>
#if CONFIG_STACK_POINTER_RANDOM
	z_stack_adjust_initialized = 1;
#endif
	boot_banner();
    f36e:	f000 fe05 	bl	ff7c <boot_banner>
	void z_cpp_init_static(void);
	z_cpp_init_static();
#endif

	/* Final init level before app starts */
	z_sys_init_run_level(_SYS_INIT_LEVEL_APPLICATION);
    f372:	2003      	movs	r0, #3
    f374:	f7ff ffd4 	bl	f320 <z_sys_init_run_level>

	z_init_static_threads();
    f378:	f000 f8ec 	bl	f554 <z_init_static_threads>
	z_mem_manage_boot_finish();
#endif /* CONFIG_MMU */

	extern void main(void);

	main();
    f37c:	f7fd f91c 	bl	c5b8 <main>

	/* Mark nonessential since main() has no more work to do */
	z_main_thread.base.user_options &= ~K_ESSENTIAL;
    f380:	4a03      	ldr	r2, [pc, #12]	; (f390 <bg_thread_main+0x30>)
    f382:	7b13      	ldrb	r3, [r2, #12]
    f384:	f023 0301 	bic.w	r3, r3, #1
    f388:	7313      	strb	r3, [r2, #12]

#ifdef CONFIG_COVERAGE_DUMP
	/* Dump coverage data once the main() has exited. */
	gcov_coverage_dump();
#endif
} /* LCOV_EXCL_LINE ... because we just dumped final coverage data */
    f38a:	bd08      	pop	{r3, pc}
    f38c:	20000782 	.word	0x20000782
    f390:	20000138 	.word	0x20000138

0000f394 <z_bss_zero>:
{
    f394:	b508      	push	{r3, lr}
	z_early_memset(__bss_start, 0, __bss_end - __bss_start);
    f396:	4803      	ldr	r0, [pc, #12]	; (f3a4 <z_bss_zero+0x10>)
    f398:	4a03      	ldr	r2, [pc, #12]	; (f3a8 <z_bss_zero+0x14>)
    f39a:	2100      	movs	r1, #0
    f39c:	1a12      	subs	r2, r2, r0
    f39e:	f001 fa05 	bl	107ac <z_early_memset>
}
    f3a2:	bd08      	pop	{r3, pc}
    f3a4:	20000098 	.word	0x20000098
    f3a8:	20000784 	.word	0x20000784

0000f3ac <z_init_cpu>:
	thread->base.is_idle = 1U;
#endif
}

void z_init_cpu(int id)
{
    f3ac:	b570      	push	{r4, r5, r6, lr}
	z_setup_new_thread(thread, stack,
    f3ae:	2300      	movs	r3, #0
{
    f3b0:	b086      	sub	sp, #24
	z_setup_new_thread(thread, stack,
    f3b2:	2201      	movs	r2, #1
    f3b4:	e9cd 2304 	strd	r2, r3, [sp, #16]
	struct k_thread *thread = &z_idle_threads[i];
    f3b8:	4e13      	ldr	r6, [pc, #76]	; (f408 <z_init_cpu+0x5c>)
			  CONFIG_IDLE_STACK_SIZE, idle, &_kernel.cpus[i],
    f3ba:	4d14      	ldr	r5, [pc, #80]	; (f40c <z_init_cpu+0x60>)
	z_setup_new_thread(thread, stack,
    f3bc:	9301      	str	r3, [sp, #4]
    f3be:	220f      	movs	r2, #15
    f3c0:	e9cd 3202 	strd	r3, r2, [sp, #8]
    f3c4:	4912      	ldr	r1, [pc, #72]	; (f410 <z_init_cpu+0x64>)
			  CONFIG_IDLE_STACK_SIZE, idle, &_kernel.cpus[i],
    f3c6:	2318      	movs	r3, #24
    f3c8:	fb03 5500 	mla	r5, r3, r0, r5
	struct k_thread *thread = &z_idle_threads[i];
    f3cc:	eb06 16c0 	add.w	r6, r6, r0, lsl #7
{
    f3d0:	4604      	mov	r4, r0
	z_setup_new_thread(thread, stack,
    f3d2:	f44f 70b0 	mov.w	r0, #352	; 0x160
    f3d6:	fb00 1104 	mla	r1, r0, r4, r1
    f3da:	4b0e      	ldr	r3, [pc, #56]	; (f414 <z_init_cpu+0x68>)
    f3dc:	9500      	str	r5, [sp, #0]
    f3de:	f44f 72a0 	mov.w	r2, #320	; 0x140
    f3e2:	4630      	mov	r0, r6
    f3e4:	f000 f884 	bl	f4f0 <z_setup_new_thread>
	SYS_PORT_TRACING_FUNC(k_thread, sched_resume, thread);
}

static inline void z_mark_thread_as_started(struct k_thread *thread)
{
	thread->base.thread_state &= ~_THREAD_PRESTART;
    f3e8:	7b73      	ldrb	r3, [r6, #13]
	init_idle_thread(id);
	_kernel.cpus[id].idle_thread = &z_idle_threads[id];
	_kernel.cpus[id].id = id;
	_kernel.cpus[id].irq_stack =
		(Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[id]) +
    f3ea:	480b      	ldr	r0, [pc, #44]	; (f418 <z_init_cpu+0x6c>)
	_kernel.cpus[id].id = id;
    f3ec:	752c      	strb	r4, [r5, #20]
    f3ee:	f023 0304 	bic.w	r3, r3, #4
    f3f2:	7373      	strb	r3, [r6, #13]
		(Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[id]) +
    f3f4:	f44f 6302 	mov.w	r3, #2080	; 0x820
    f3f8:	fb03 0404 	mla	r4, r3, r4, r0
    f3fc:	441c      	add	r4, r3
	_kernel.cpus[id].idle_thread = &z_idle_threads[id];
    f3fe:	60ee      	str	r6, [r5, #12]
	_kernel.cpus[id].irq_stack =
    f400:	606c      	str	r4, [r5, #4]
		 K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[id]));
#ifdef CONFIG_SCHED_THREAD_USAGE_ALL
	_kernel.cpus[id].usage.track_usage =
		CONFIG_SCHED_THREAD_USAGE_AUTO_ENABLE;
#endif
}
    f402:	b006      	add	sp, #24
    f404:	bd70      	pop	{r4, r5, r6, pc}
    f406:	bf00      	nop
    f408:	200000b8 	.word	0x200000b8
    f40c:	20000338 	.word	0x20000338
    f410:	20000bc0 	.word	0x20000bc0
    f414:	0000f60d 	.word	0x0000f60d
    f418:	20000d20 	.word	0x20000d20

0000f41c <z_cstart>:
 *
 * @return Does not return
 */
__boot_func
FUNC_NORETURN void z_cstart(void)
{
    f41c:	b580      	push	{r7, lr}
 * pointer) register, and switched to automatically when taking an exception.
 *
 */
static ALWAYS_INLINE void z_arm_interrupt_stack_setup(void)
{
	uint32_t msp =
    f41e:	4b2d      	ldr	r3, [pc, #180]	; (f4d4 <z_cstart+0xb8>)
    f420:	b0a6      	sub	sp, #152	; 0x98
  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
    f422:	f383 8808 	msr	MSP, r3
	 * for Cortex-M3 and Cortex-M4 (ARMv7-M) MCUs. For the rest
	 * of ARM Cortex-M processors this setting is enforced by
	 * default and it is not configurable.
	 */
#if defined(CONFIG_CPU_CORTEX_M3) || defined(CONFIG_CPU_CORTEX_M4)
	SCB->CCR |= SCB_CCR_STKALIGN_Msk;
    f426:	4d2c      	ldr	r5, [pc, #176]	; (f4d8 <z_cstart+0xbc>)
	k_thread_system_pool_assign(dummy_thread);
#else
	dummy_thread->resource_pool = NULL;
#endif

	_current_cpu->current = dummy_thread;
    f428:	4e2c      	ldr	r6, [pc, #176]	; (f4dc <z_cstart+0xc0>)
    f42a:	696b      	ldr	r3, [r5, #20]
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    f42c:	4f2c      	ldr	r7, [pc, #176]	; (f4e0 <z_cstart+0xc4>)
    f42e:	f443 7300 	orr.w	r3, r3, #512	; 0x200
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
    f432:	2400      	movs	r4, #0
    f434:	616b      	str	r3, [r5, #20]
    f436:	23e0      	movs	r3, #224	; 0xe0
    f438:	f885 3022 	strb.w	r3, [r5, #34]	; 0x22
    f43c:	77ec      	strb	r4, [r5, #31]
    f43e:	762c      	strb	r4, [r5, #24]
    f440:	766c      	strb	r4, [r5, #25]
    f442:	76ac      	strb	r4, [r5, #26]
    f444:	f885 4020 	strb.w	r4, [r5, #32]
#if defined(CONFIG_ARM_SECURE_FIRMWARE)
	NVIC_SetPriority(SecureFault_IRQn, _EXC_FAULT_PRIO);
#endif /* CONFIG_ARM_SECURE_FIRMWARE */

	/* Enable Usage, Mem, & Bus Faults */
	SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk |
    f448:	6a6b      	ldr	r3, [r5, #36]	; 0x24
    f44a:	f443 23e0 	orr.w	r3, r3, #458752	; 0x70000
    f44e:	626b      	str	r3, [r5, #36]	; 0x24
    f450:	f885 4023 	strb.w	r4, [r5, #35]	; 0x23

static ALWAYS_INLINE void arch_kernel_init(void)
{
	z_arm_interrupt_stack_setup();
	z_arm_exc_setup();
	z_arm_fault_init();
    f454:	f7fe f900 	bl	d658 <z_arm_fault_init>
	z_arm_cpu_idle_init();
    f458:	f7fd fed2 	bl	d200 <z_arm_cpu_idle_init>
static ALWAYS_INLINE void z_arm_clear_faults(void)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* Reset all faults */
	SCB->CFSR = SCB_CFSR_USGFAULTSR_Msk |
    f45c:	f04f 33ff 	mov.w	r3, #4294967295
    f460:	62ab      	str	r3, [r5, #40]	; 0x28
		    SCB_CFSR_MEMFAULTSR_Msk |
		    SCB_CFSR_BUSFAULTSR_Msk;

	/* Clear all Hard Faults - HFSR is write-one-to-clear */
	SCB->HFSR = 0xffffffff;
    f462:	62eb      	str	r3, [r5, #44]	; 0x2c
	z_arm_clear_faults();
#if defined(CONFIG_ARM_MPU)
	z_arm_mpu_init();
    f464:	f7fe fa30 	bl	d8c8 <z_arm_mpu_init>
	 * to set up access permissions for fixed memory sections, such
	 * as Application Memory or No-Cacheable SRAM area.
	 *
	 * This function is invoked once, upon system initialization.
	 */
	z_arm_configure_static_mpu_regions();
    f468:	f7fe f998 	bl	d79c <z_arm_configure_static_mpu_regions>
	dummy_thread->base.user_options = K_ESSENTIAL;
    f46c:	f240 1301 	movw	r3, #257	; 0x101
    f470:	f8ad 3024 	strh.w	r3, [sp, #36]	; 0x24
	_current_cpu->current = dummy_thread;
    f474:	ab06      	add	r3, sp, #24
    f476:	60b3      	str	r3, [r6, #8]
	dummy_thread->stack_info.size = 0U;
    f478:	e9cd 441f 	strd	r4, r4, [sp, #124]	; 0x7c
	dummy_thread->resource_pool = NULL;
    f47c:	9422      	str	r4, [sp, #136]	; 0x88
	struct k_thread dummy_thread;

	z_dummy_thread_init(&dummy_thread);
#endif
	/* do any necessary initialization of static devices */
	z_device_state_init();
    f47e:	f001 f96f 	bl	10760 <z_device_state_init>

	/* perform basic hardware initialization */
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_1);
    f482:	4620      	mov	r0, r4
    f484:	f7ff ff4c 	bl	f320 <z_sys_init_run_level>
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_2);
    f488:	2001      	movs	r0, #1
	_kernel.ready_q.cache = &z_main_thread;
    f48a:	4d16      	ldr	r5, [pc, #88]	; (f4e4 <z_cstart+0xc8>)
	z_sys_init_run_level(_SYS_INIT_LEVEL_PRE_KERNEL_2);
    f48c:	f7ff ff48 	bl	f320 <z_sys_init_run_level>
	z_sched_init();
    f490:	f000 fb1c 	bl	facc <z_sched_init>
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    f494:	4b14      	ldr	r3, [pc, #80]	; (f4e8 <z_cstart+0xcc>)
	_kernel.ready_q.cache = &z_main_thread;
    f496:	61f5      	str	r5, [r6, #28]
	stack_ptr = z_setup_new_thread(&z_main_thread, z_main_stack,
    f498:	9305      	str	r3, [sp, #20]
    f49a:	2301      	movs	r3, #1
    f49c:	4913      	ldr	r1, [pc, #76]	; (f4ec <z_cstart+0xd0>)
    f49e:	9400      	str	r4, [sp, #0]
    f4a0:	e9cd 4303 	strd	r4, r3, [sp, #12]
    f4a4:	f44f 6280 	mov.w	r2, #1024	; 0x400
    f4a8:	463b      	mov	r3, r7
    f4aa:	e9cd 4401 	strd	r4, r4, [sp, #4]
    f4ae:	4628      	mov	r0, r5
    f4b0:	f000 f81e 	bl	f4f0 <z_setup_new_thread>
    f4b4:	7b6a      	ldrb	r2, [r5, #13]
    f4b6:	4606      	mov	r6, r0
    f4b8:	f022 0204 	bic.w	r2, r2, #4
	z_ready_thread(&z_main_thread);
    f4bc:	4628      	mov	r0, r5
    f4be:	736a      	strb	r2, [r5, #13]
    f4c0:	f001 f9b3 	bl	1082a <z_ready_thread>
	z_init_cpu(0);
    f4c4:	4620      	mov	r0, r4
    f4c6:	f7ff ff71 	bl	f3ac <z_init_cpu>
	arch_switch_to_main_thread(&z_main_thread, stack_ptr, bg_thread_main);
    f4ca:	463a      	mov	r2, r7
    f4cc:	4631      	mov	r1, r6
    f4ce:	4628      	mov	r0, r5
    f4d0:	f7fd ff90 	bl	d3f4 <arch_switch_to_main_thread>
	CODE_UNREACHABLE; /* LCOV_EXCL_LINE */
    f4d4:	20001540 	.word	0x20001540
    f4d8:	e000ed00 	.word	0xe000ed00
    f4dc:	20000338 	.word	0x20000338
    f4e0:	0000f361 	.word	0x0000f361
    f4e4:	20000138 	.word	0x20000138
    f4e8:	00010cef 	.word	0x00010cef
    f4ec:	200007a0 	.word	0x200007a0

0000f4f0 <z_setup_new_thread>:
char *z_setup_new_thread(struct k_thread *new_thread,
			 k_thread_stack_t *stack, size_t stack_size,
			 k_thread_entry_t entry,
			 void *p1, void *p2, void *p3,
			 int prio, uint32_t options, const char *name)
{
    f4f0:	e92d 41ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr}
void z_init_thread_base(struct _thread_base *thread_base, int priority,
		       uint32_t initial_state, unsigned int options)
{
	/* k_q_node is initialized upon first insertion in a list */
	thread_base->pended_on = NULL;
	thread_base->user_options = (uint8_t)options;
    f4f4:	9e0e      	ldr	r6, [sp, #56]	; 0x38
    f4f6:	7306      	strb	r6, [r0, #12]
	thread_base->thread_state = (uint8_t)initial_state;
    f4f8:	2604      	movs	r6, #4
    f4fa:	7346      	strb	r6, [r0, #13]

	thread_base->prio = priority;
    f4fc:	9e0d      	ldr	r6, [sp, #52]	; 0x34
    f4fe:	7386      	strb	r6, [r0, #14]
	SYS_DLIST_FOR_EACH_CONTAINER(&((wq)->waitq), thread_ptr, \
				     base.qnode_dlist)

static inline void z_waitq_init(_wait_q_t *w)
{
	sys_dlist_init(&w->waitq);
    f500:	f100 0558 	add.w	r5, r0, #88	; 0x58
{
    f504:	460f      	mov	r7, r1
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    f506:	1dd6      	adds	r6, r2, #7
 */

static inline void sys_dlist_init(sys_dlist_t *list)
{
	list->head = (sys_dnode_t *)list;
	list->tail = (sys_dnode_t *)list;
    f508:	e9c0 5516 	strd	r5, r5, [r0, #88]	; 0x58
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    f50c:	9a0c      	ldr	r2, [sp, #48]	; 0x30
	thread_base->pended_on = NULL;
    f50e:	2500      	movs	r5, #0
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    f510:	f026 0607 	bic.w	r6, r6, #7

/** @} */

static inline char *Z_KERNEL_STACK_BUFFER(k_thread_stack_t *sym)
{
	return (char *)sym + K_KERNEL_STACK_RESERVED;
    f514:	3720      	adds	r7, #32
 */

static inline void sys_dnode_init(sys_dnode_t *node)
{
	node->next = NULL;
	node->prev = NULL;
    f516:	e9c0 5506 	strd	r5, r5, [r0, #24]
	new_thread->stack_info.size = stack_buf_size;
    f51a:	e9c0 7619 	strd	r7, r6, [r0, #100]	; 0x64
	thread_base->pended_on = NULL;
    f51e:	6085      	str	r5, [r0, #8]

	thread_base->sched_locked = 0U;
    f520:	73c5      	strb	r5, [r0, #15]
	new_thread->stack_info.delta = delta;
    f522:	66c5      	str	r5, [r0, #108]	; 0x6c
		stack_obj_size = Z_KERNEL_STACK_SIZE_ADJUST(stack_size);
    f524:	f106 0820 	add.w	r8, r6, #32
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    f528:	9202      	str	r2, [sp, #8]
    f52a:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
    f52c:	9201      	str	r2, [sp, #4]
	stack_ptr = (char *)stack + stack_obj_size;
    f52e:	4488      	add	r8, r1
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    f530:	9a0a      	ldr	r2, [sp, #40]	; 0x28
    f532:	9200      	str	r2, [sp, #0]
    f534:	4642      	mov	r2, r8
{
    f536:	4604      	mov	r4, r0
	arch_new_thread(new_thread, stack, stack_ptr, entry, p1, p2, p3);
    f538:	f7fd ff2a 	bl	d390 <arch_new_thread>
	if (!_current) {
    f53c:	4b04      	ldr	r3, [pc, #16]	; (f550 <z_setup_new_thread+0x60>)
	new_thread->init_data = NULL;
    f53e:	6565      	str	r5, [r4, #84]	; 0x54
	if (!_current) {
    f540:	689b      	ldr	r3, [r3, #8]
    f542:	b103      	cbz	r3, f546 <z_setup_new_thread+0x56>
	new_thread->resource_pool = _current->resource_pool;
    f544:	6f1b      	ldr	r3, [r3, #112]	; 0x70
	return stack_ptr;
    f546:	6723      	str	r3, [r4, #112]	; 0x70
}
    f548:	4640      	mov	r0, r8
    f54a:	b004      	add	sp, #16
    f54c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    f550:	20000338 	.word	0x20000338

0000f554 <z_init_static_threads>:
{
    f554:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
    f558:	4c29      	ldr	r4, [pc, #164]	; (f600 <z_init_static_threads+0xac>)
	_FOREACH_STATIC_THREAD(thread_data) {
    f55a:	4d2a      	ldr	r5, [pc, #168]	; (f604 <z_init_static_threads+0xb0>)
{
    f55c:	b087      	sub	sp, #28
    f55e:	4626      	mov	r6, r4
	_FOREACH_STATIC_THREAD(thread_data) {
    f560:	42ae      	cmp	r6, r5
    f562:	f104 0430 	add.w	r4, r4, #48	; 0x30
    f566:	d30f      	bcc.n	f588 <z_init_static_threads+0x34>
	k_sched_lock();
    f568:	f000 f90c 	bl	f784 <k_sched_lock>
	_FOREACH_STATIC_THREAD(thread_data) {
    f56c:	4c24      	ldr	r4, [pc, #144]	; (f600 <z_init_static_threads+0xac>)

extern void z_thread_timeout(struct _timeout *timeout);

static inline void z_add_thread_timeout(struct k_thread *thread, k_timeout_t ticks)
{
	z_add_timeout(&thread->base.timeout, z_thread_timeout, ticks);
    f56e:	f8df 9098 	ldr.w	r9, [pc, #152]	; f608 <z_init_static_threads+0xb4>
			/* Faster algorithm but source is first multiplied by target frequency
			 * and it can overflow even though final result would not overflow.
			 * Kconfig option shall prevent use of this algorithm when there is a
			 * risk of overflow.
			 */
			return ((t * to_hz + off) / from_hz);
    f572:	f44f 4600 	mov.w	r6, #32768	; 0x8000
    f576:	f240 37e7 	movw	r7, #999	; 0x3e7
    f57a:	42ac      	cmp	r4, r5
    f57c:	d320      	bcc.n	f5c0 <z_init_static_threads+0x6c>
}
    f57e:	b007      	add	sp, #28
    f580:	e8bd 43f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, lr}
	k_sched_unlock();
    f584:	f000 ba86 	b.w	fa94 <k_sched_unlock>
		z_setup_new_thread(
    f588:	f854 3c04 	ldr.w	r3, [r4, #-4]
    f58c:	9305      	str	r3, [sp, #20]
    f58e:	f854 3c10 	ldr.w	r3, [r4, #-16]
    f592:	9304      	str	r3, [sp, #16]
    f594:	f854 3c14 	ldr.w	r3, [r4, #-20]
    f598:	9303      	str	r3, [sp, #12]
    f59a:	f854 3c18 	ldr.w	r3, [r4, #-24]
    f59e:	9302      	str	r3, [sp, #8]
    f5a0:	f854 3c1c 	ldr.w	r3, [r4, #-28]
    f5a4:	9301      	str	r3, [sp, #4]
    f5a6:	f854 3c20 	ldr.w	r3, [r4, #-32]
    f5aa:	9300      	str	r3, [sp, #0]
    f5ac:	e954 010c 	ldrd	r0, r1, [r4, #-48]	; 0x30
    f5b0:	e954 230a 	ldrd	r2, r3, [r4, #-40]	; 0x28
    f5b4:	f7ff ff9c 	bl	f4f0 <z_setup_new_thread>
		thread_data->init_thread->init_data = thread_data;
    f5b8:	f854 3c30 	ldr.w	r3, [r4, #-48]
    f5bc:	655e      	str	r6, [r3, #84]	; 0x54
	_FOREACH_STATIC_THREAD(thread_data) {
    f5be:	e7ce      	b.n	f55e <z_init_static_threads+0xa>
		if (thread_data->init_delay != K_TICKS_FOREVER) {
    f5c0:	6a63      	ldr	r3, [r4, #36]	; 0x24
    f5c2:	1c5a      	adds	r2, r3, #1
    f5c4:	d00d      	beq.n	f5e2 <z_init_static_threads+0x8e>
					    K_MSEC(thread_data->init_delay));
    f5c6:	ea23 73e3 	bic.w	r3, r3, r3, asr #31
    f5ca:	2100      	movs	r1, #0
    f5cc:	4638      	mov	r0, r7
    f5ce:	fbc3 0106 	smlal	r0, r1, r3, r6
	if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) {
    f5d2:	ea51 33c3 	orrs.w	r3, r1, r3, lsl #15
			schedule_new_thread(thread_data->init_thread,
    f5d6:	f8d4 8000 	ldr.w	r8, [r4]
	if (K_TIMEOUT_EQ(delay, K_NO_WAIT)) {
    f5da:	d104      	bne.n	f5e6 <z_init_static_threads+0x92>
	z_sched_start(thread);
    f5dc:	4640      	mov	r0, r8
    f5de:	f000 f9b7 	bl	f950 <z_sched_start>
	_FOREACH_STATIC_THREAD(thread_data) {
    f5e2:	3430      	adds	r4, #48	; 0x30
    f5e4:	e7c9      	b.n	f57a <z_init_static_threads+0x26>
    f5e6:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    f5ea:	2300      	movs	r3, #0
    f5ec:	f7fc fe76 	bl	c2dc <__aeabi_uldivmod>
    f5f0:	4602      	mov	r2, r0
    f5f2:	460b      	mov	r3, r1
    f5f4:	f108 0018 	add.w	r0, r8, #24
    f5f8:	4649      	mov	r1, r9
    f5fa:	f000 fbd1 	bl	fda0 <z_add_timeout>
    f5fe:	e7f0      	b.n	f5e2 <z_init_static_threads+0x8e>
    f600:	20000098 	.word	0x20000098
    f604:	20000098 	.word	0x20000098
    f608:	0001084b 	.word	0x0001084b

0000f60c <idle>:
#endif	/* CONFIG_PM */
	sys_clock_idle_exit();
}

void idle(void *unused1, void *unused2, void *unused3)
{
    f60c:	b508      	push	{r3, lr}
		 * higher level construct.
		 */
		(void) arch_irq_lock();

#ifdef CONFIG_PM
		_kernel.idle = z_get_next_timeout_expiry();
    f60e:	4c0b      	ldr	r4, [pc, #44]	; (f63c <idle+0x30>)
	return !z_sys_post_kernel;
    f610:	4d0b      	ldr	r5, [pc, #44]	; (f640 <idle+0x34>)
	__asm__ volatile(
    f612:	f04f 0220 	mov.w	r2, #32
    f616:	f3ef 8311 	mrs	r3, BASEPRI
    f61a:	f382 8812 	msr	BASEPRI_MAX, r2
    f61e:	f3bf 8f6f 	isb	sy
    f622:	f001 f98c 	bl	1093e <z_get_next_timeout_expiry>
		 * processing in those cases i.e. skips k_cpu_idle().
		 * The kernel's idle processing re-enables interrupts
		 * which is essential for the kernel's scheduling
		 * logic.
		 */
		if (k_is_pre_kernel() || !pm_system_suspend(_kernel.idle)) {
    f626:	782b      	ldrb	r3, [r5, #0]
		_kernel.idle = z_get_next_timeout_expiry();
    f628:	61a0      	str	r0, [r4, #24]
		if (k_is_pre_kernel() || !pm_system_suspend(_kernel.idle)) {
    f62a:	b913      	cbnz	r3, f632 <idle+0x26>
	arch_cpu_idle();
    f62c:	f7fd fdee 	bl	d20c <arch_cpu_idle>
}
    f630:	e7ef      	b.n	f612 <idle+0x6>
    f632:	f7fd fd0b 	bl	d04c <pm_system_suspend>
    f636:	2800      	cmp	r0, #0
    f638:	d1eb      	bne.n	f612 <idle+0x6>
    f63a:	e7f7      	b.n	f62c <idle+0x20>
    f63c:	20000338 	.word	0x20000338
    f640:	20000782 	.word	0x20000782

0000f644 <z_impl_k_sem_give>:
	ARG_UNUSED(sem);
#endif
}

void z_impl_k_sem_give(struct k_sem *sem)
{
    f644:	b538      	push	{r3, r4, r5, lr}
    f646:	4604      	mov	r4, r0
    f648:	f04f 0320 	mov.w	r3, #32
    f64c:	f3ef 8511 	mrs	r5, BASEPRI
    f650:	f383 8812 	msr	BASEPRI_MAX, r3
    f654:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&lock);
	struct k_thread *thread;

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_sem, give, sem);

	thread = z_unpend_first_thread(&sem->wait_q);
    f658:	f001 f943 	bl	108e2 <z_unpend_first_thread>

	if (thread != NULL) {
    f65c:	b148      	cbz	r0, f672 <z_impl_k_sem_give+0x2e>
}

static ALWAYS_INLINE void
arch_thread_return_value_set(struct k_thread *thread, unsigned int value)
{
	thread->arch.swap_return_value = value;
    f65e:	2200      	movs	r2, #0
    f660:	6782      	str	r2, [r0, #120]	; 0x78
		arch_thread_return_value_set(thread, 0);
		z_ready_thread(thread);
    f662:	f001 f8e2 	bl	1082a <z_ready_thread>
	} else {
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
		handle_poll_events(sem);
	}

	z_reschedule(&lock, key);
    f666:	4629      	mov	r1, r5
    f668:	4805      	ldr	r0, [pc, #20]	; (f680 <z_impl_k_sem_give+0x3c>)

	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_sem, give, sem);
}
    f66a:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
	z_reschedule(&lock, key);
    f66e:	f000 b877 	b.w	f760 <z_reschedule>
		sem->count += (sem->count != sem->limit) ? 1U : 0U;
    f672:	e9d4 3202 	ldrd	r3, r2, [r4, #8]
    f676:	429a      	cmp	r2, r3
    f678:	bf18      	it	ne
    f67a:	3301      	addne	r3, #1
    f67c:	60a3      	str	r3, [r4, #8]
}
    f67e:	e7f2      	b.n	f666 <z_impl_k_sem_give+0x22>
    f680:	20000783 	.word	0x20000783

0000f684 <z_impl_k_sem_take>:
}
#include <syscalls/k_sem_give_mrsh.c>
#endif

int z_impl_k_sem_take(struct k_sem *sem, k_timeout_t timeout)
{
    f684:	b513      	push	{r0, r1, r4, lr}
    f686:	f04f 0420 	mov.w	r4, #32
    f68a:	f3ef 8111 	mrs	r1, BASEPRI
    f68e:	f384 8812 	msr	BASEPRI_MAX, r4
    f692:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&lock);

	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_sem, take, sem, timeout);

	if (likely(sem->count > 0U)) {
    f696:	6884      	ldr	r4, [r0, #8]
    f698:	b144      	cbz	r4, f6ac <z_impl_k_sem_take+0x28>
		sem->count--;
    f69a:	3c01      	subs	r4, #1
    f69c:	6084      	str	r4, [r0, #8]
	__asm__ volatile(
    f69e:	f381 8811 	msr	BASEPRI, r1
    f6a2:	f3bf 8f6f 	isb	sy
		k_spin_unlock(&lock, key);
		ret = 0;
    f6a6:	2000      	movs	r0, #0

out:
	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_sem, take, sem, timeout, ret);

	return ret;
}
    f6a8:	b002      	add	sp, #8
    f6aa:	bd10      	pop	{r4, pc}
	if (K_TIMEOUT_EQ(timeout, K_NO_WAIT)) {
    f6ac:	ea52 0403 	orrs.w	r4, r2, r3
    f6b0:	d106      	bne.n	f6c0 <z_impl_k_sem_take+0x3c>
    f6b2:	f381 8811 	msr	BASEPRI, r1
    f6b6:	f3bf 8f6f 	isb	sy
		ret = -EBUSY;
    f6ba:	f06f 000f 	mvn.w	r0, #15
    f6be:	e7f3      	b.n	f6a8 <z_impl_k_sem_take+0x24>
	ret = z_pend_curr(&lock, key, &sem->wait_q, timeout);
    f6c0:	e9cd 2300 	strd	r2, r3, [sp]
    f6c4:	4602      	mov	r2, r0
    f6c6:	4802      	ldr	r0, [pc, #8]	; (f6d0 <z_impl_k_sem_take+0x4c>)
    f6c8:	f000 f99e 	bl	fa08 <z_pend_curr>
	return ret;
    f6cc:	e7ec      	b.n	f6a8 <z_impl_k_sem_take+0x24>
    f6ce:	bf00      	nop
    f6d0:	20000783 	.word	0x20000783

0000f6d4 <z_reset_time_slice>:
 */
static struct k_thread *pending_current;
#endif

void z_reset_time_slice(struct k_thread *curr)
{
    f6d4:	b538      	push	{r3, r4, r5, lr}
	int ret = slice_ticks;
    f6d6:	4d07      	ldr	r5, [pc, #28]	; (f6f4 <z_reset_time_slice+0x20>)
    f6d8:	682c      	ldr	r4, [r5, #0]
	/* Add the elapsed time since the last announced tick to the
	 * slice count, as we'll see those "expired" ticks arrive in a
	 * FUTURE z_time_slice() call.
	 */
	if (slice_time(curr) != 0) {
    f6da:	b154      	cbz	r4, f6f2 <z_reset_time_slice+0x1e>
		_current_cpu->slice_ticks = slice_time(curr) + sys_clock_elapsed();
    f6dc:	f7ff f822 	bl	e724 <sys_clock_elapsed>
    f6e0:	4b05      	ldr	r3, [pc, #20]	; (f6f8 <z_reset_time_slice+0x24>)
    f6e2:	4404      	add	r4, r0
    f6e4:	611c      	str	r4, [r3, #16]
		z_set_timeout_expiry(slice_time(curr), false);
    f6e6:	6828      	ldr	r0, [r5, #0]
    f6e8:	2100      	movs	r1, #0
	}
}
    f6ea:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
		z_set_timeout_expiry(slice_time(curr), false);
    f6ee:	f001 b936 	b.w	1095e <z_set_timeout_expiry>
}
    f6f2:	bd38      	pop	{r3, r4, r5, pc}
    f6f4:	20000368 	.word	0x20000368
    f6f8:	20000338 	.word	0x20000338

0000f6fc <k_sched_time_slice_set>:

void k_sched_time_slice_set(int32_t slice, int prio)
{
    f6fc:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    f6fe:	4604      	mov	r4, r0
    f700:	460d      	mov	r5, r1
	__asm__ volatile(
    f702:	f04f 0320 	mov.w	r3, #32
    f706:	f3ef 8711 	mrs	r7, BASEPRI
    f70a:	f383 8812 	msr	BASEPRI_MAX, r3
    f70e:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
		_current_cpu->slice_ticks = 0;
    f712:	4e10      	ldr	r6, [pc, #64]	; (f754 <k_sched_time_slice_set+0x58>)
    f714:	2100      	movs	r1, #0
			return (uint32_t)((t * to_hz + off) / from_hz);
    f716:	f44f 4c00 	mov.w	ip, #32768	; 0x8000
    f71a:	f240 30e7 	movw	r0, #999	; 0x3e7
    f71e:	6131      	str	r1, [r6, #16]
    f720:	2300      	movs	r3, #0
    f722:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
    f726:	fbe4 010c 	umlal	r0, r1, r4, ip
    f72a:	f7fc fdd7 	bl	c2dc <__aeabi_uldivmod>
		slice_ticks = k_ms_to_ticks_ceil32(slice);
		if (IS_ENABLED(CONFIG_TICKLESS_KERNEL) && slice > 0) {
    f72e:	2c00      	cmp	r4, #0
    f730:	4b09      	ldr	r3, [pc, #36]	; (f758 <k_sched_time_slice_set+0x5c>)
    f732:	dc0a      	bgt.n	f74a <k_sched_time_slice_set+0x4e>
			/* It's not possible to reliably set a 1-tick
			 * timeout if ticks aren't regular.
			 */
			slice_ticks = MAX(2, slice_ticks);
    f734:	6018      	str	r0, [r3, #0]
		}
		slice_max_prio = prio;
    f736:	4b09      	ldr	r3, [pc, #36]	; (f75c <k_sched_time_slice_set+0x60>)
		z_reset_time_slice(_current);
    f738:	68b0      	ldr	r0, [r6, #8]
		slice_max_prio = prio;
    f73a:	601d      	str	r5, [r3, #0]
		z_reset_time_slice(_current);
    f73c:	f7ff ffca 	bl	f6d4 <z_reset_time_slice>
	__asm__ volatile(
    f740:	f387 8811 	msr	BASEPRI, r7
    f744:	f3bf 8f6f 	isb	sy
	}
}
    f748:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
			slice_ticks = MAX(2, slice_ticks);
    f74a:	2802      	cmp	r0, #2
    f74c:	bfb8      	it	lt
    f74e:	2002      	movlt	r0, #2
    f750:	e7f0      	b.n	f734 <k_sched_time_slice_set+0x38>
    f752:	bf00      	nop
    f754:	20000338 	.word	0x20000338
    f758:	20000368 	.word	0x20000368
    f75c:	20000364 	.word	0x20000364

0000f760 <z_reschedule>:
{
#ifdef CONFIG_SMP
	_current_cpu->swap_ok = 0;
#endif

	return arch_irq_unlocked(key) && !arch_is_in_isr();
    f760:	b949      	cbnz	r1, f776 <z_reschedule+0x16>
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
    f762:	f3ef 8005 	mrs	r0, IPSR
#endif
}

void z_reschedule(struct k_spinlock *lock, k_spinlock_key_t key)
{
	if (resched(key.key) && need_swap()) {
    f766:	b930      	cbnz	r0, f776 <z_reschedule+0x16>
	new_thread = _kernel.ready_q.cache;
    f768:	4b05      	ldr	r3, [pc, #20]	; (f780 <z_reschedule+0x20>)
	if (resched(key.key) && need_swap()) {
    f76a:	69da      	ldr	r2, [r3, #28]
    f76c:	689b      	ldr	r3, [r3, #8]
    f76e:	429a      	cmp	r2, r3
    f770:	d001      	beq.n	f776 <z_reschedule+0x16>
	ret = arch_swap(key);
    f772:	f7fd bdb9 	b.w	d2e8 <arch_swap>
    f776:	f381 8811 	msr	BASEPRI, r1
    f77a:	f3bf 8f6f 	isb	sy
		z_swap(lock, key);
	} else {
		k_spin_unlock(lock, key);
	}
}
    f77e:	4770      	bx	lr
    f780:	20000338 	.word	0x20000338

0000f784 <k_sched_lock>:
	__asm__ volatile(
    f784:	f04f 0320 	mov.w	r3, #32
    f788:	f3ef 8111 	mrs	r1, BASEPRI
    f78c:	f383 8812 	msr	BASEPRI_MAX, r3
    f790:	f3bf 8f6f 	isb	sy
static inline void z_sched_lock(void)
{
	__ASSERT(!arch_is_in_isr(), "");
	__ASSERT(_current->base.sched_locked != 1U, "");

	--_current->base.sched_locked;
    f794:	4b04      	ldr	r3, [pc, #16]	; (f7a8 <k_sched_lock+0x24>)
    f796:	689a      	ldr	r2, [r3, #8]
    f798:	7bd3      	ldrb	r3, [r2, #15]
    f79a:	3b01      	subs	r3, #1
    f79c:	73d3      	strb	r3, [r2, #15]
	__asm__ volatile(
    f79e:	f381 8811 	msr	BASEPRI, r1
    f7a2:	f3bf 8f6f 	isb	sy
	LOCKED(&sched_spinlock) {
		SYS_PORT_TRACING_FUNC(k_thread, sched_lock);

		z_sched_lock();
	}
}
    f7a6:	4770      	bx	lr
    f7a8:	20000338 	.word	0x20000338

0000f7ac <update_cache>:
{
    f7ac:	b538      	push	{r3, r4, r5, lr}
    f7ae:	4602      	mov	r2, r0
	return _priq_run_best(curr_cpu_runq());
    f7b0:	480c      	ldr	r0, [pc, #48]	; (f7e4 <update_cache+0x38>)
    f7b2:	4d0d      	ldr	r5, [pc, #52]	; (f7e8 <update_cache+0x3c>)
    f7b4:	f001 f833 	bl	1081e <z_priq_dumb_best>
	return (thread != NULL) ? thread : _current_cpu->idle_thread;
    f7b8:	4604      	mov	r4, r0
    f7ba:	b900      	cbnz	r0, f7be <update_cache+0x12>
    f7bc:	68ec      	ldr	r4, [r5, #12]
	if (z_is_thread_prevented_from_running(_current)) {
    f7be:	68ab      	ldr	r3, [r5, #8]
	if (preempt_ok != 0) {
    f7c0:	b94a      	cbnz	r2, f7d6 <update_cache+0x2a>
	if (z_is_thread_prevented_from_running(_current)) {
    f7c2:	7b5a      	ldrb	r2, [r3, #13]
    f7c4:	06d2      	lsls	r2, r2, #27
    f7c6:	d106      	bne.n	f7d6 <update_cache+0x2a>
	if (IS_ENABLED(CONFIG_SWAP_NONATOMIC)
    f7c8:	69a2      	ldr	r2, [r4, #24]
    f7ca:	b922      	cbnz	r2, f7d6 <update_cache+0x2a>
	if (is_preempt(_current) || is_metairq(thread)) {
    f7cc:	89da      	ldrh	r2, [r3, #14]
    f7ce:	2a7f      	cmp	r2, #127	; 0x7f
    f7d0:	d901      	bls.n	f7d6 <update_cache+0x2a>
		_kernel.ready_q.cache = _current;
    f7d2:	61eb      	str	r3, [r5, #28]
}
    f7d4:	bd38      	pop	{r3, r4, r5, pc}
		if (thread != _current) {
    f7d6:	429c      	cmp	r4, r3
    f7d8:	d002      	beq.n	f7e0 <update_cache+0x34>
			z_reset_time_slice(thread);
    f7da:	4620      	mov	r0, r4
    f7dc:	f7ff ff7a 	bl	f6d4 <z_reset_time_slice>
		_kernel.ready_q.cache = thread;
    f7e0:	61ec      	str	r4, [r5, #28]
}
    f7e2:	e7f7      	b.n	f7d4 <update_cache+0x28>
    f7e4:	20000358 	.word	0x20000358
    f7e8:	20000338 	.word	0x20000338

0000f7ec <move_thread_to_end_of_prio_q>:
{
    f7ec:	b570      	push	{r4, r5, r6, lr}
	if (z_is_thread_queued(thread)) {
    f7ee:	f990 200d 	ldrsb.w	r2, [r0, #13]
	return (thread->base.thread_state & state) != 0U;
    f7f2:	7b43      	ldrb	r3, [r0, #13]
    f7f4:	2a00      	cmp	r2, #0
{
    f7f6:	4601      	mov	r1, r0
	if (z_is_thread_queued(thread)) {
    f7f8:	da04      	bge.n	f804 <move_thread_to_end_of_prio_q+0x18>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    f7fa:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    f7fe:	7343      	strb	r3, [r0, #13]

void z_priq_dumb_remove(sys_dlist_t *pq, struct k_thread *thread)
{
	__ASSERT_NO_MSG(!z_is_idle_thread_object(thread));

	sys_dlist_remove(&thread->base.qnode_dlist);
    f800:	f000 ffe5 	bl	107ce <sys_dlist_remove>
	thread->base.thread_state |= _THREAD_QUEUED;
    f804:	7b4b      	ldrb	r3, [r1, #13]
 * @return true if empty, false otherwise
 */

static inline bool sys_dlist_is_empty(sys_dlist_t *list)
{
	return list->head == list;
    f806:	4a15      	ldr	r2, [pc, #84]	; (f85c <move_thread_to_end_of_prio_q+0x70>)
    f808:	f063 037f 	orn	r3, r3, #127	; 0x7f
    f80c:	734b      	strb	r3, [r1, #13]
 */

static inline sys_dnode_t *sys_dlist_peek_next_no_check(sys_dlist_t *list,
							sys_dnode_t *node)
{
	return (node == list->tail) ? NULL : node->next;
    f80e:	e9d2 3408 	ldrd	r3, r4, [r2, #32]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    f812:	f102 0520 	add.w	r5, r2, #32
    f816:	42ab      	cmp	r3, r5
    f818:	d01b      	beq.n	f852 <move_thread_to_end_of_prio_q+0x66>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    f81a:	b1d3      	cbz	r3, f852 <move_thread_to_end_of_prio_q+0x66>
	int32_t b1 = thread_1->base.prio;
    f81c:	f991 600e 	ldrsb.w	r6, [r1, #14]
	int32_t b2 = thread_2->base.prio;
    f820:	f993 000e 	ldrsb.w	r0, [r3, #14]
	if (b1 != b2) {
    f824:	4286      	cmp	r6, r0
    f826:	d00f      	beq.n	f848 <move_thread_to_end_of_prio_q+0x5c>
		return b2 - b1;
    f828:	1b80      	subs	r0, r0, r6
		if (z_sched_prio_cmp(thread, t) > 0) {
    f82a:	2800      	cmp	r0, #0
    f82c:	dd0c      	ble.n	f848 <move_thread_to_end_of_prio_q+0x5c>
 * @param successor the position before which "node" will be inserted
 * @param node the element to insert
 */
static inline void sys_dlist_insert(sys_dnode_t *successor, sys_dnode_t *node)
{
	sys_dnode_t *const prev = successor->prev;
    f82e:	6858      	ldr	r0, [r3, #4]

	node->prev = prev;
	node->next = successor;
    f830:	e9c1 3000 	strd	r3, r0, [r1]
	prev->next = node;
    f834:	6001      	str	r1, [r0, #0]
	successor->prev = node;
    f836:	6059      	str	r1, [r3, #4]
	update_cache(thread == _current);
    f838:	6890      	ldr	r0, [r2, #8]
    f83a:	1a43      	subs	r3, r0, r1
    f83c:	4258      	negs	r0, r3
}
    f83e:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
	update_cache(thread == _current);
    f842:	4158      	adcs	r0, r3
    f844:	f7ff bfb2 	b.w	f7ac <update_cache>
	return (node == list->tail) ? NULL : node->next;
    f848:	42a3      	cmp	r3, r4
    f84a:	d002      	beq.n	f852 <move_thread_to_end_of_prio_q+0x66>
    f84c:	681b      	ldr	r3, [r3, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    f84e:	2b00      	cmp	r3, #0
    f850:	d1e6      	bne.n	f820 <move_thread_to_end_of_prio_q+0x34>
	node->prev = tail;
    f852:	e9c1 5400 	strd	r5, r4, [r1]
	tail->next = node;
    f856:	6021      	str	r1, [r4, #0]
	list->tail = node;
    f858:	6251      	str	r1, [r2, #36]	; 0x24
}
    f85a:	e7ed      	b.n	f838 <move_thread_to_end_of_prio_q+0x4c>
    f85c:	20000338 	.word	0x20000338

0000f860 <z_time_slice>:
{
    f860:	b538      	push	{r3, r4, r5, lr}
	__asm__ volatile(
    f862:	f04f 0320 	mov.w	r3, #32
    f866:	f3ef 8511 	mrs	r5, BASEPRI
    f86a:	f383 8812 	msr	BASEPRI_MAX, r3
    f86e:	f3bf 8f6f 	isb	sy
	if (pending_current == _current) {
    f872:	4b17      	ldr	r3, [pc, #92]	; (f8d0 <z_time_slice+0x70>)
    f874:	4a17      	ldr	r2, [pc, #92]	; (f8d4 <z_time_slice+0x74>)
    f876:	689c      	ldr	r4, [r3, #8]
    f878:	6811      	ldr	r1, [r2, #0]
    f87a:	428c      	cmp	r4, r1
    f87c:	d107      	bne.n	f88e <z_time_slice+0x2e>
	z_reset_time_slice(curr);
    f87e:	4620      	mov	r0, r4
    f880:	f7ff ff28 	bl	f6d4 <z_reset_time_slice>
	__asm__ volatile(
    f884:	f385 8811 	msr	BASEPRI, r5
    f888:	f3bf 8f6f 	isb	sy
}
    f88c:	bd38      	pop	{r3, r4, r5, pc}
	pending_current = NULL;
    f88e:	2100      	movs	r1, #0
    f890:	6011      	str	r1, [r2, #0]
	int ret = slice_ticks;
    f892:	4a11      	ldr	r2, [pc, #68]	; (f8d8 <z_time_slice+0x78>)
	if (slice_time(_current) && sliceable(_current)) {
    f894:	6812      	ldr	r2, [r2, #0]
    f896:	b1c2      	cbz	r2, f8ca <z_time_slice+0x6a>
		&& !z_is_idle_thread_object(thread);
    f898:	89e2      	ldrh	r2, [r4, #14]
    f89a:	2a7f      	cmp	r2, #127	; 0x7f
    f89c:	d815      	bhi.n	f8ca <z_time_slice+0x6a>
		&& !z_is_thread_prevented_from_running(thread)
    f89e:	7b62      	ldrb	r2, [r4, #13]
    f8a0:	06d2      	lsls	r2, r2, #27
    f8a2:	d112      	bne.n	f8ca <z_time_slice+0x6a>
		&& !z_is_prio_higher(thread->base.prio, slice_max_prio)
    f8a4:	4a0d      	ldr	r2, [pc, #52]	; (f8dc <z_time_slice+0x7c>)
    f8a6:	f994 100e 	ldrsb.w	r1, [r4, #14]
    f8aa:	6812      	ldr	r2, [r2, #0]
    f8ac:	4291      	cmp	r1, r2
    f8ae:	db0c      	blt.n	f8ca <z_time_slice+0x6a>
	if (slice_time(_current) && sliceable(_current)) {
    f8b0:	4a0b      	ldr	r2, [pc, #44]	; (f8e0 <z_time_slice+0x80>)
    f8b2:	4294      	cmp	r4, r2
    f8b4:	d009      	beq.n	f8ca <z_time_slice+0x6a>
		if (ticks >= _current_cpu->slice_ticks) {
    f8b6:	691a      	ldr	r2, [r3, #16]
    f8b8:	4282      	cmp	r2, r0
    f8ba:	dc03      	bgt.n	f8c4 <z_time_slice+0x64>
		move_thread_to_end_of_prio_q(curr);
    f8bc:	4620      	mov	r0, r4
    f8be:	f7ff ff95 	bl	f7ec <move_thread_to_end_of_prio_q>
    f8c2:	e7dc      	b.n	f87e <z_time_slice+0x1e>
			_current_cpu->slice_ticks -= ticks;
    f8c4:	1a12      	subs	r2, r2, r0
		_current_cpu->slice_ticks = 0;
    f8c6:	611a      	str	r2, [r3, #16]
    f8c8:	e7dc      	b.n	f884 <z_time_slice+0x24>
    f8ca:	2200      	movs	r2, #0
    f8cc:	e7fb      	b.n	f8c6 <z_time_slice+0x66>
    f8ce:	bf00      	nop
    f8d0:	20000338 	.word	0x20000338
    f8d4:	20000360 	.word	0x20000360
    f8d8:	20000368 	.word	0x20000368
    f8dc:	20000364 	.word	0x20000364
    f8e0:	200000b8 	.word	0x200000b8

0000f8e4 <ready_thread>:
{
    f8e4:	b470      	push	{r4, r5, r6}
	if (!z_is_thread_queued(thread) && z_is_thread_ready(thread)) {
    f8e6:	f990 200d 	ldrsb.w	r2, [r0, #13]
    f8ea:	7b43      	ldrb	r3, [r0, #13]
    f8ec:	2a00      	cmp	r2, #0
    f8ee:	db2a      	blt.n	f946 <ready_thread+0x62>
	return !((z_is_thread_prevented_from_running(thread)) != 0U ||
    f8f0:	06da      	lsls	r2, r3, #27
    f8f2:	d128      	bne.n	f946 <ready_thread+0x62>
    f8f4:	6982      	ldr	r2, [r0, #24]
    f8f6:	bb32      	cbnz	r2, f946 <ready_thread+0x62>
	return list->head == list;
    f8f8:	4a14      	ldr	r2, [pc, #80]	; (f94c <ready_thread+0x68>)
	thread->base.thread_state |= _THREAD_QUEUED;
    f8fa:	f063 037f 	orn	r3, r3, #127	; 0x7f
    f8fe:	7343      	strb	r3, [r0, #13]
	return (node == list->tail) ? NULL : node->next;
    f900:	e9d2 3408 	ldrd	r3, r4, [r2, #32]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    f904:	f102 0520 	add.w	r5, r2, #32
    f908:	42ab      	cmp	r3, r5
    f90a:	d017      	beq.n	f93c <ready_thread+0x58>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    f90c:	b1b3      	cbz	r3, f93c <ready_thread+0x58>
	int32_t b1 = thread_1->base.prio;
    f90e:	f990 600e 	ldrsb.w	r6, [r0, #14]
	int32_t b2 = thread_2->base.prio;
    f912:	f993 100e 	ldrsb.w	r1, [r3, #14]
	if (b1 != b2) {
    f916:	428e      	cmp	r6, r1
    f918:	d00b      	beq.n	f932 <ready_thread+0x4e>
		return b2 - b1;
    f91a:	1b89      	subs	r1, r1, r6
		if (z_sched_prio_cmp(thread, t) > 0) {
    f91c:	2900      	cmp	r1, #0
    f91e:	dd08      	ble.n	f932 <ready_thread+0x4e>
	sys_dnode_t *const prev = successor->prev;
    f920:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
    f922:	e9c0 3200 	strd	r3, r2, [r0]
	prev->next = node;
    f926:	6010      	str	r0, [r2, #0]
	successor->prev = node;
    f928:	6058      	str	r0, [r3, #4]
}
    f92a:	bc70      	pop	{r4, r5, r6}
		update_cache(0);
    f92c:	2000      	movs	r0, #0
    f92e:	f7ff bf3d 	b.w	f7ac <update_cache>
	return (node == list->tail) ? NULL : node->next;
    f932:	42a3      	cmp	r3, r4
    f934:	d002      	beq.n	f93c <ready_thread+0x58>
    f936:	681b      	ldr	r3, [r3, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    f938:	2b00      	cmp	r3, #0
    f93a:	d1ea      	bne.n	f912 <ready_thread+0x2e>
	node->prev = tail;
    f93c:	e9c0 5400 	strd	r5, r4, [r0]
	tail->next = node;
    f940:	6020      	str	r0, [r4, #0]
	list->tail = node;
    f942:	6250      	str	r0, [r2, #36]	; 0x24
}
    f944:	e7f1      	b.n	f92a <ready_thread+0x46>
}
    f946:	bc70      	pop	{r4, r5, r6}
    f948:	4770      	bx	lr
    f94a:	bf00      	nop
    f94c:	20000338 	.word	0x20000338

0000f950 <z_sched_start>:
{
    f950:	b510      	push	{r4, lr}
	__asm__ volatile(
    f952:	f04f 0220 	mov.w	r2, #32
    f956:	f3ef 8411 	mrs	r4, BASEPRI
    f95a:	f382 8812 	msr	BASEPRI_MAX, r2
    f95e:	f3bf 8f6f 	isb	sy
	return (thread->base.thread_state & _THREAD_PRESTART) == 0U;
    f962:	7b42      	ldrb	r2, [r0, #13]
	if (z_has_thread_started(thread)) {
    f964:	0751      	lsls	r1, r2, #29
    f966:	d404      	bmi.n	f972 <z_sched_start+0x22>
	__asm__ volatile(
    f968:	f384 8811 	msr	BASEPRI, r4
    f96c:	f3bf 8f6f 	isb	sy
}
    f970:	bd10      	pop	{r4, pc}
	thread->base.thread_state &= ~_THREAD_PRESTART;
    f972:	f022 0204 	bic.w	r2, r2, #4
    f976:	7342      	strb	r2, [r0, #13]
	ready_thread(thread);
    f978:	f7ff ffb4 	bl	f8e4 <ready_thread>
	z_reschedule(&sched_spinlock, key);
    f97c:	4621      	mov	r1, r4
    f97e:	4802      	ldr	r0, [pc, #8]	; (f988 <z_sched_start+0x38>)
}
    f980:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	z_reschedule(&sched_spinlock, key);
    f984:	f7ff beec 	b.w	f760 <z_reschedule>
    f988:	20000783 	.word	0x20000783

0000f98c <unready_thread>:
{
    f98c:	b508      	push	{r3, lr}
	if (z_is_thread_queued(thread)) {
    f98e:	f990 200d 	ldrsb.w	r2, [r0, #13]
	return (thread->base.thread_state & state) != 0U;
    f992:	7b43      	ldrb	r3, [r0, #13]
    f994:	2a00      	cmp	r2, #0
{
    f996:	4601      	mov	r1, r0
	if (z_is_thread_queued(thread)) {
    f998:	da04      	bge.n	f9a4 <unready_thread+0x18>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    f99a:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    f99e:	7343      	strb	r3, [r0, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    f9a0:	f000 ff15 	bl	107ce <sys_dlist_remove>
	update_cache(thread == _current);
    f9a4:	4b04      	ldr	r3, [pc, #16]	; (f9b8 <unready_thread+0x2c>)
    f9a6:	6898      	ldr	r0, [r3, #8]
    f9a8:	1a43      	subs	r3, r0, r1
    f9aa:	4258      	negs	r0, r3
    f9ac:	4158      	adcs	r0, r3
}
    f9ae:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	update_cache(thread == _current);
    f9b2:	f7ff befb 	b.w	f7ac <update_cache>
    f9b6:	bf00      	nop
    f9b8:	20000338 	.word	0x20000338

0000f9bc <pend>:
{
    f9bc:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    f9c0:	4606      	mov	r6, r0
    f9c2:	4615      	mov	r5, r2
    f9c4:	461c      	mov	r4, r3
	__asm__ volatile(
    f9c6:	f04f 0320 	mov.w	r3, #32
    f9ca:	f3ef 8711 	mrs	r7, BASEPRI
    f9ce:	f383 8812 	msr	BASEPRI_MAX, r3
    f9d2:	f3bf 8f6f 	isb	sy
		add_to_waitq_locked(thread, wait_q);
    f9d6:	f000 ff5a 	bl	1088e <add_to_waitq_locked>
	__asm__ volatile(
    f9da:	f387 8811 	msr	BASEPRI, r7
    f9de:	f3bf 8f6f 	isb	sy
	if (!K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    f9e2:	f1b4 3fff 	cmp.w	r4, #4294967295
    f9e6:	bf08      	it	eq
    f9e8:	f1b5 3fff 	cmpeq.w	r5, #4294967295
    f9ec:	d008      	beq.n	fa00 <pend+0x44>
    f9ee:	462a      	mov	r2, r5
    f9f0:	4623      	mov	r3, r4
    f9f2:	f106 0018 	add.w	r0, r6, #24
    f9f6:	4903      	ldr	r1, [pc, #12]	; (fa04 <pend+0x48>)
}
    f9f8:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
    f9fc:	f000 b9d0 	b.w	fda0 <z_add_timeout>
    fa00:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    fa04:	0001084b 	.word	0x0001084b

0000fa08 <z_pend_curr>:
{
    fa08:	b510      	push	{r4, lr}
	pending_current = _current;
    fa0a:	4b07      	ldr	r3, [pc, #28]	; (fa28 <z_pend_curr+0x20>)
    fa0c:	6898      	ldr	r0, [r3, #8]
    fa0e:	4b07      	ldr	r3, [pc, #28]	; (fa2c <z_pend_curr+0x24>)
{
    fa10:	460c      	mov	r4, r1
	pending_current = _current;
    fa12:	6018      	str	r0, [r3, #0]
{
    fa14:	4611      	mov	r1, r2
	pend(_current, wait_q, timeout);
    fa16:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
    fa1a:	f7ff ffcf 	bl	f9bc <pend>
    fa1e:	4620      	mov	r0, r4
}
    fa20:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    fa24:	f7fd bc60 	b.w	d2e8 <arch_swap>
    fa28:	20000338 	.word	0x20000338
    fa2c:	20000360 	.word	0x20000360

0000fa30 <z_impl_k_thread_suspend>:
{
    fa30:	b570      	push	{r4, r5, r6, lr}
    fa32:	4604      	mov	r4, r0
}

static inline int z_abort_thread_timeout(struct k_thread *thread)
{
	return z_abort_timeout(&thread->base.timeout);
    fa34:	3018      	adds	r0, #24
    fa36:	f000 ff6c 	bl	10912 <z_abort_timeout>
	__asm__ volatile(
    fa3a:	f04f 0320 	mov.w	r3, #32
    fa3e:	f3ef 8611 	mrs	r6, BASEPRI
    fa42:	f383 8812 	msr	BASEPRI_MAX, r3
    fa46:	f3bf 8f6f 	isb	sy
		if (z_is_thread_queued(thread)) {
    fa4a:	f994 200d 	ldrsb.w	r2, [r4, #13]
    fa4e:	7b63      	ldrb	r3, [r4, #13]
    fa50:	2a00      	cmp	r2, #0
    fa52:	da05      	bge.n	fa60 <z_impl_k_thread_suspend+0x30>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    fa54:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    fa58:	7363      	strb	r3, [r4, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    fa5a:	4620      	mov	r0, r4
    fa5c:	f000 feb7 	bl	107ce <sys_dlist_remove>
		update_cache(thread == _current);
    fa60:	4d0b      	ldr	r5, [pc, #44]	; (fa90 <z_impl_k_thread_suspend+0x60>)
	thread->base.thread_state |= _THREAD_SUSPENDED;
    fa62:	7b63      	ldrb	r3, [r4, #13]
    fa64:	68a8      	ldr	r0, [r5, #8]
    fa66:	f043 0310 	orr.w	r3, r3, #16
    fa6a:	7363      	strb	r3, [r4, #13]
    fa6c:	1b03      	subs	r3, r0, r4
    fa6e:	4258      	negs	r0, r3
    fa70:	4158      	adcs	r0, r3
    fa72:	f7ff fe9b 	bl	f7ac <update_cache>
	__asm__ volatile(
    fa76:	f386 8811 	msr	BASEPRI, r6
    fa7a:	f3bf 8f6f 	isb	sy
	if (thread == _current) {
    fa7e:	68ab      	ldr	r3, [r5, #8]
    fa80:	42a3      	cmp	r3, r4
    fa82:	d103      	bne.n	fa8c <z_impl_k_thread_suspend+0x5c>
}
    fa84:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
		z_reschedule_unlocked();
    fa88:	f000 bebf 	b.w	1080a <z_reschedule_unlocked>
}
    fa8c:	bd70      	pop	{r4, r5, r6, pc}
    fa8e:	bf00      	nop
    fa90:	20000338 	.word	0x20000338

0000fa94 <k_sched_unlock>:
{
    fa94:	b510      	push	{r4, lr}
	__asm__ volatile(
    fa96:	f04f 0320 	mov.w	r3, #32
    fa9a:	f3ef 8411 	mrs	r4, BASEPRI
    fa9e:	f383 8812 	msr	BASEPRI_MAX, r3
    faa2:	f3bf 8f6f 	isb	sy
		++_current->base.sched_locked;
    faa6:	4b08      	ldr	r3, [pc, #32]	; (fac8 <k_sched_unlock+0x34>)
    faa8:	689a      	ldr	r2, [r3, #8]
    faaa:	7bd3      	ldrb	r3, [r2, #15]
    faac:	3301      	adds	r3, #1
    faae:	73d3      	strb	r3, [r2, #15]
		update_cache(0);
    fab0:	2000      	movs	r0, #0
    fab2:	f7ff fe7b 	bl	f7ac <update_cache>
	__asm__ volatile(
    fab6:	f384 8811 	msr	BASEPRI, r4
    faba:	f3bf 8f6f 	isb	sy
}
    fabe:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
	z_reschedule_unlocked();
    fac2:	f000 bea2 	b.w	1080a <z_reschedule_unlocked>
    fac6:	bf00      	nop
    fac8:	20000338 	.word	0x20000338

0000facc <z_sched_init>:
	list->head = (sys_dnode_t *)list;
    facc:	4b04      	ldr	r3, [pc, #16]	; (fae0 <z_sched_init+0x14>)
#else
	init_ready_q(&_kernel.ready_q);
#endif

#ifdef CONFIG_TIMESLICING
	k_sched_time_slice_set(CONFIG_TIMESLICE_SIZE,
    face:	2100      	movs	r1, #0
    fad0:	f103 0220 	add.w	r2, r3, #32
	list->tail = (sys_dnode_t *)list;
    fad4:	e9c3 2208 	strd	r2, r2, [r3, #32]
    fad8:	4608      	mov	r0, r1
    fada:	f7ff be0f 	b.w	f6fc <k_sched_time_slice_set>
    fade:	bf00      	nop
    fae0:	20000338 	.word	0x20000338

0000fae4 <z_impl_k_yield>:
#include <syscalls/k_thread_deadline_set_mrsh.c>
#endif
#endif

void z_impl_k_yield(void)
{
    fae4:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
	__asm__ volatile(
    fae6:	f04f 0320 	mov.w	r3, #32
    faea:	f3ef 8511 	mrs	r5, BASEPRI
    faee:	f383 8812 	msr	BASEPRI_MAX, r3
    faf2:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&sched_spinlock);

	if (!IS_ENABLED(CONFIG_SMP) ||
	    z_is_thread_queued(_current)) {
		dequeue_thread(_current);
    faf6:	491a      	ldr	r1, [pc, #104]	; (fb60 <z_impl_k_yield+0x7c>)
    faf8:	6888      	ldr	r0, [r1, #8]
	thread->base.thread_state &= ~_THREAD_QUEUED;
    fafa:	7b43      	ldrb	r3, [r0, #13]
    fafc:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    fb00:	7343      	strb	r3, [r0, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    fb02:	f000 fe64 	bl	107ce <sys_dlist_remove>
	}
	queue_thread(_current);
    fb06:	688b      	ldr	r3, [r1, #8]
	thread->base.thread_state |= _THREAD_QUEUED;
    fb08:	7b5a      	ldrb	r2, [r3, #13]
	return list->head == list;
    fb0a:	4608      	mov	r0, r1
    fb0c:	f062 027f 	orn	r2, r2, #127	; 0x7f
    fb10:	735a      	strb	r2, [r3, #13]
    fb12:	f850 2f20 	ldr.w	r2, [r0, #32]!
	return sys_dlist_is_empty(list) ? NULL : list->head;
    fb16:	4282      	cmp	r2, r0
    fb18:	d01c      	beq.n	fb54 <z_impl_k_yield+0x70>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    fb1a:	b1da      	cbz	r2, fb54 <z_impl_k_yield+0x70>
	return (node == list->tail) ? NULL : node->next;
    fb1c:	6a4f      	ldr	r7, [r1, #36]	; 0x24
	int32_t b1 = thread_1->base.prio;
    fb1e:	f993 600e 	ldrsb.w	r6, [r3, #14]
	int32_t b2 = thread_2->base.prio;
    fb22:	f992 400e 	ldrsb.w	r4, [r2, #14]
	if (b1 != b2) {
    fb26:	42a6      	cmp	r6, r4
    fb28:	d00f      	beq.n	fb4a <z_impl_k_yield+0x66>
		return b2 - b1;
    fb2a:	1ba4      	subs	r4, r4, r6
		if (z_sched_prio_cmp(thread, t) > 0) {
    fb2c:	2c00      	cmp	r4, #0
    fb2e:	dd0c      	ble.n	fb4a <z_impl_k_yield+0x66>
	sys_dnode_t *const prev = successor->prev;
    fb30:	6851      	ldr	r1, [r2, #4]
	node->next = successor;
    fb32:	e9c3 2100 	strd	r2, r1, [r3]
	prev->next = node;
    fb36:	600b      	str	r3, [r1, #0]
	successor->prev = node;
    fb38:	6053      	str	r3, [r2, #4]
	update_cache(1);
    fb3a:	2001      	movs	r0, #1
    fb3c:	f7ff fe36 	bl	f7ac <update_cache>
    fb40:	4628      	mov	r0, r5
	z_swap(&sched_spinlock, key);
}
    fb42:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
    fb46:	f7fd bbcf 	b.w	d2e8 <arch_swap>
	return (node == list->tail) ? NULL : node->next;
    fb4a:	42ba      	cmp	r2, r7
    fb4c:	d002      	beq.n	fb54 <z_impl_k_yield+0x70>
    fb4e:	6812      	ldr	r2, [r2, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
    fb50:	2a00      	cmp	r2, #0
    fb52:	d1e6      	bne.n	fb22 <z_impl_k_yield+0x3e>
	sys_dnode_t *const tail = list->tail;
    fb54:	6a4a      	ldr	r2, [r1, #36]	; 0x24
	node->prev = tail;
    fb56:	e9c3 0200 	strd	r0, r2, [r3]
	tail->next = node;
    fb5a:	6013      	str	r3, [r2, #0]
	list->tail = node;
    fb5c:	624b      	str	r3, [r1, #36]	; 0x24
}
    fb5e:	e7ec      	b.n	fb3a <z_impl_k_yield+0x56>
    fb60:	20000338 	.word	0x20000338

0000fb64 <z_tick_sleep>:
	 */
	LOG_DBG("thread %p for %u ticks", _current, ticks);
#endif

	/* wait of 0 ms is treated as a 'yield' */
	if (ticks == 0) {
    fb64:	ea50 0301 	orrs.w	r3, r0, r1
{
    fb68:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    fb6c:	4605      	mov	r5, r0
    fb6e:	460e      	mov	r6, r1
	if (ticks == 0) {
    fb70:	d103      	bne.n	fb7a <z_tick_sleep+0x16>
	z_impl_k_yield();
    fb72:	f7ff ffb7 	bl	fae4 <z_impl_k_yield>
	if (ticks > 0) {
		return ticks;
	}
#endif

	return 0;
    fb76:	2000      	movs	r0, #0
    fb78:	e033      	b.n	fbe2 <z_tick_sleep+0x7e>
	if (Z_TICK_ABS(ticks) <= 0) {
    fb7a:	f06f 0401 	mvn.w	r4, #1
    fb7e:	1a24      	subs	r4, r4, r0
    fb80:	f04f 33ff 	mov.w	r3, #4294967295
    fb84:	eb63 0301 	sbc.w	r3, r3, r1
    fb88:	2c01      	cmp	r4, #1
    fb8a:	f173 0300 	sbcs.w	r3, r3, #0
    fb8e:	da02      	bge.n	fb96 <z_tick_sleep+0x32>
		expected_wakeup_ticks = ticks + sys_clock_tick_get_32();
    fb90:	f000 feff 	bl	10992 <sys_clock_tick_get_32>
    fb94:	1944      	adds	r4, r0, r5
    fb96:	f04f 0320 	mov.w	r3, #32
    fb9a:	f3ef 8811 	mrs	r8, BASEPRI
    fb9e:	f383 8812 	msr	BASEPRI_MAX, r3
    fba2:	f3bf 8f6f 	isb	sy
	pending_current = _current;
    fba6:	4f10      	ldr	r7, [pc, #64]	; (fbe8 <z_tick_sleep+0x84>)
    fba8:	4b10      	ldr	r3, [pc, #64]	; (fbec <z_tick_sleep+0x88>)
    fbaa:	68b8      	ldr	r0, [r7, #8]
    fbac:	6018      	str	r0, [r3, #0]
	unready_thread(_current);
    fbae:	f7ff feed 	bl	f98c <unready_thread>
	z_add_thread_timeout(_current, timeout);
    fbb2:	68b8      	ldr	r0, [r7, #8]
	z_add_timeout(&thread->base.timeout, z_thread_timeout, ticks);
    fbb4:	490e      	ldr	r1, [pc, #56]	; (fbf0 <z_tick_sleep+0x8c>)
    fbb6:	462a      	mov	r2, r5
    fbb8:	4633      	mov	r3, r6
    fbba:	3018      	adds	r0, #24
    fbbc:	f000 f8f0 	bl	fda0 <z_add_timeout>
	z_mark_thread_as_suspended(_current);
    fbc0:	68ba      	ldr	r2, [r7, #8]
    fbc2:	7b53      	ldrb	r3, [r2, #13]
    fbc4:	f043 0310 	orr.w	r3, r3, #16
    fbc8:	7353      	strb	r3, [r2, #13]
    fbca:	4640      	mov	r0, r8
    fbcc:	f7fd fb8c 	bl	d2e8 <arch_swap>
	ticks = (k_ticks_t)expected_wakeup_ticks - sys_clock_tick_get_32();
    fbd0:	f000 fedf 	bl	10992 <sys_clock_tick_get_32>
    fbd4:	1a20      	subs	r0, r4, r0
    fbd6:	eb63 0303 	sbc.w	r3, r3, r3
	if (ticks > 0) {
    fbda:	2801      	cmp	r0, #1
    fbdc:	f173 0300 	sbcs.w	r3, r3, #0
    fbe0:	dbc9      	blt.n	fb76 <z_tick_sleep+0x12>
}
    fbe2:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    fbe6:	bf00      	nop
    fbe8:	20000338 	.word	0x20000338
    fbec:	20000360 	.word	0x20000360
    fbf0:	0001084b 	.word	0x0001084b

0000fbf4 <z_impl_k_sleep>:
	__ASSERT(!arch_is_in_isr(), "");

	SYS_PORT_TRACING_FUNC_ENTER(k_thread, sleep, timeout);

	/* in case of K_FOREVER, we suspend */
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    fbf4:	f1b1 3fff 	cmp.w	r1, #4294967295
    fbf8:	bf08      	it	eq
    fbfa:	f1b0 3fff 	cmpeq.w	r0, #4294967295
{
    fbfe:	b508      	push	{r3, lr}
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    fc00:	d106      	bne.n	fc10 <z_impl_k_sleep+0x1c>
		k_thread_suspend(_current);
    fc02:	4b08      	ldr	r3, [pc, #32]	; (fc24 <z_impl_k_sleep+0x30>)
    fc04:	6898      	ldr	r0, [r3, #8]
	z_impl_k_thread_suspend(thread);
    fc06:	f7ff ff13 	bl	fa30 <z_impl_k_thread_suspend>

		SYS_PORT_TRACING_FUNC_EXIT(k_thread, sleep, timeout, (int32_t) K_TICKS_FOREVER);

		return (int32_t) K_TICKS_FOREVER;
    fc0a:	f04f 30ff 	mov.w	r0, #4294967295
	int32_t ret = k_ticks_to_ms_floor64(ticks);

	SYS_PORT_TRACING_FUNC_EXIT(k_thread, sleep, timeout, ret);

	return ret;
}
    fc0e:	bd08      	pop	{r3, pc}
	ticks = z_tick_sleep(ticks);
    fc10:	f7ff ffa8 	bl	fb64 <z_tick_sleep>
			return ((t * to_hz + off) / from_hz);
    fc14:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
    fc18:	fb80 0303 	smull	r0, r3, r0, r3
    fc1c:	0bc0      	lsrs	r0, r0, #15
    fc1e:	ea40 4043 	orr.w	r0, r0, r3, lsl #17
	return ret;
    fc22:	e7f4      	b.n	fc0e <z_impl_k_sleep+0x1a>
    fc24:	20000338 	.word	0x20000338

0000fc28 <z_impl_z_current_get>:

#ifdef CONFIG_SMP
	arch_irq_unlock(k);
#endif
	return ret;
}
    fc28:	4b01      	ldr	r3, [pc, #4]	; (fc30 <z_impl_z_current_get+0x8>)
    fc2a:	6898      	ldr	r0, [r3, #8]
    fc2c:	4770      	bx	lr
    fc2e:	bf00      	nop
    fc30:	20000338 	.word	0x20000338

0000fc34 <z_thread_abort>:
#endif
	}
}

void z_thread_abort(struct k_thread *thread)
{
    fc34:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    fc38:	4604      	mov	r4, r0
    fc3a:	f04f 0320 	mov.w	r3, #32
    fc3e:	f3ef 8611 	mrs	r6, BASEPRI
    fc42:	f383 8812 	msr	BASEPRI_MAX, r3
    fc46:	f3bf 8f6f 	isb	sy
	k_spinlock_key_t key = k_spin_lock(&sched_spinlock);

	if ((thread->base.thread_state & _THREAD_DEAD) != 0U) {
    fc4a:	7b43      	ldrb	r3, [r0, #13]
    fc4c:	071a      	lsls	r2, r3, #28
    fc4e:	d505      	bpl.n	fc5c <z_thread_abort+0x28>
	__asm__ volatile(
    fc50:	f386 8811 	msr	BASEPRI, r6
    fc54:	f3bf 8f6f 	isb	sy
	if (thread == _current && !arch_is_in_isr()) {
		z_swap(&sched_spinlock, key);
		__ASSERT(false, "aborted _current back from dead");
	}
	k_spin_unlock(&sched_spinlock, key);
}
    fc58:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		thread->base.thread_state &= ~_THREAD_ABORTING;
    fc5c:	f023 0220 	bic.w	r2, r3, #32
    fc60:	f042 0108 	orr.w	r1, r2, #8
		if (z_is_thread_queued(thread)) {
    fc64:	09d2      	lsrs	r2, r2, #7
    fc66:	d120      	bne.n	fcaa <z_thread_abort+0x76>
		thread->base.thread_state &= ~_THREAD_ABORTING;
    fc68:	7341      	strb	r1, [r0, #13]
		if (thread->base.pended_on != NULL) {
    fc6a:	68a3      	ldr	r3, [r4, #8]
    fc6c:	b113      	cbz	r3, fc74 <z_thread_abort+0x40>
			unpend_thread_no_timeout(thread);
    fc6e:	4620      	mov	r0, r4
    fc70:	f000 fdb5 	bl	107de <unpend_thread_no_timeout>
	return z_abort_timeout(&thread->base.timeout);
    fc74:	f104 0018 	add.w	r0, r4, #24
    fc78:	f000 fe4b 	bl	10912 <z_abort_timeout>
}

static inline struct k_thread *z_waitq_head(_wait_q_t *w)
{
	return (struct k_thread *)sys_dlist_peek_head(&w->waitq);
    fc7c:	f104 0758 	add.w	r7, r4, #88	; 0x58
    fc80:	f04f 0800 	mov.w	r8, #0
	return list->head == list;
    fc84:	6da5      	ldr	r5, [r4, #88]	; 0x58
	return sys_dlist_is_empty(list) ? NULL : list->head;
    fc86:	42bd      	cmp	r5, r7
    fc88:	d000      	beq.n	fc8c <z_thread_abort+0x58>
	while ((thread = z_waitq_head(wait_q)) != NULL) {
    fc8a:	b9b5      	cbnz	r5, fcba <z_thread_abort+0x86>
		update_cache(1);
    fc8c:	2001      	movs	r0, #1
    fc8e:	f7ff fd8d 	bl	f7ac <update_cache>
	if (thread == _current && !arch_is_in_isr()) {
    fc92:	4b10      	ldr	r3, [pc, #64]	; (fcd4 <z_thread_abort+0xa0>)
    fc94:	689b      	ldr	r3, [r3, #8]
    fc96:	42a3      	cmp	r3, r4
    fc98:	d1da      	bne.n	fc50 <z_thread_abort+0x1c>
    fc9a:	f3ef 8305 	mrs	r3, IPSR
    fc9e:	2b00      	cmp	r3, #0
    fca0:	d1d6      	bne.n	fc50 <z_thread_abort+0x1c>
    fca2:	4630      	mov	r0, r6
    fca4:	f7fd fb20 	bl	d2e8 <arch_swap>
	return ret;
    fca8:	e7d2      	b.n	fc50 <z_thread_abort+0x1c>
	thread->base.thread_state &= ~_THREAD_QUEUED;
    fcaa:	f003 035f 	and.w	r3, r3, #95	; 0x5f
    fcae:	f043 0308 	orr.w	r3, r3, #8
    fcb2:	7343      	strb	r3, [r0, #13]
	sys_dlist_remove(&thread->base.qnode_dlist);
    fcb4:	f000 fd8b 	bl	107ce <sys_dlist_remove>
}
    fcb8:	e7d7      	b.n	fc6a <z_thread_abort+0x36>
		unpend_thread_no_timeout(thread);
    fcba:	4628      	mov	r0, r5
    fcbc:	f000 fd8f 	bl	107de <unpend_thread_no_timeout>
    fcc0:	f105 0018 	add.w	r0, r5, #24
    fcc4:	f000 fe25 	bl	10912 <z_abort_timeout>
    fcc8:	f8c5 8078 	str.w	r8, [r5, #120]	; 0x78
		ready_thread(thread);
    fccc:	4628      	mov	r0, r5
    fcce:	f7ff fe09 	bl	f8e4 <ready_thread>
    fcd2:	e7d7      	b.n	fc84 <z_thread_abort+0x50>
    fcd4:	20000338 	.word	0x20000338

0000fcd8 <z_data_copy>:
 * @brief Copy the data section from ROM to RAM
 *
 * This routine copies the data section from ROM to RAM.
 */
void z_data_copy(void)
{
    fcd8:	b508      	push	{r3, lr}
	z_early_memcpy(&__data_region_start, &__data_region_load_start,
		       __data_region_end - __data_region_start);
    fcda:	4806      	ldr	r0, [pc, #24]	; (fcf4 <z_data_copy+0x1c>)
	z_early_memcpy(&__data_region_start, &__data_region_load_start,
    fcdc:	4a06      	ldr	r2, [pc, #24]	; (fcf8 <z_data_copy+0x20>)
    fcde:	4907      	ldr	r1, [pc, #28]	; (fcfc <z_data_copy+0x24>)
    fce0:	1a12      	subs	r2, r2, r0
    fce2:	f000 fd65 	bl	107b0 <z_early_memcpy>
#else
	z_early_memcpy(&_app_smem_start, &_app_smem_rom_start,
		       _app_smem_end - _app_smem_start);
#endif /* CONFIG_STACK_CANARIES */
#endif /* CONFIG_USERSPACE */
}
    fce6:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	z_early_memcpy(&__ramfunc_start, &__ramfunc_load_start,
    fcea:	4a05      	ldr	r2, [pc, #20]	; (fd00 <z_data_copy+0x28>)
    fcec:	4905      	ldr	r1, [pc, #20]	; (fd04 <z_data_copy+0x2c>)
    fcee:	4806      	ldr	r0, [pc, #24]	; (fd08 <z_data_copy+0x30>)
    fcf0:	f000 bd5e 	b.w	107b0 <z_early_memcpy>
    fcf4:	20000000 	.word	0x20000000
    fcf8:	20000098 	.word	0x20000098
    fcfc:	00010d28 	.word	0x00010d28
    fd00:	00000000 	.word	0x00000000
    fd04:	00010d28 	.word	0x00010d28
    fd08:	20000000 	.word	0x20000000

0000fd0c <elapsed>:
	sys_dlist_remove(&t->node);
}

static int32_t elapsed(void)
{
	return announce_remaining == 0 ? sys_clock_elapsed() : 0U;
    fd0c:	4b03      	ldr	r3, [pc, #12]	; (fd1c <elapsed+0x10>)
    fd0e:	681b      	ldr	r3, [r3, #0]
    fd10:	b90b      	cbnz	r3, fd16 <elapsed+0xa>
    fd12:	f7fe bd07 	b.w	e724 <sys_clock_elapsed>
}
    fd16:	2000      	movs	r0, #0
    fd18:	4770      	bx	lr
    fd1a:	bf00      	nop
    fd1c:	2000036c 	.word	0x2000036c

0000fd20 <next_timeout>:
	return list->head == list;
    fd20:	4b10      	ldr	r3, [pc, #64]	; (fd64 <next_timeout+0x44>)

static int32_t next_timeout(void)
{
    fd22:	b510      	push	{r4, lr}
    fd24:	681c      	ldr	r4, [r3, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    fd26:	429c      	cmp	r4, r3
    fd28:	bf08      	it	eq
    fd2a:	2400      	moveq	r4, #0
	struct _timeout *to = first();
	int32_t ticks_elapsed = elapsed();
    fd2c:	f7ff ffee 	bl	fd0c <elapsed>
	int32_t ret;

	if ((to == NULL) ||
    fd30:	b1a4      	cbz	r4, fd5c <next_timeout+0x3c>
	    ((int64_t)(to->dticks - ticks_elapsed) > (int64_t)INT_MAX)) {
    fd32:	e9d4 3204 	ldrd	r3, r2, [r4, #16]
    fd36:	1a1b      	subs	r3, r3, r0
    fd38:	eb62 70e0 	sbc.w	r0, r2, r0, asr #31
	if ((to == NULL) ||
    fd3c:	f1b3 4f00 	cmp.w	r3, #2147483648	; 0x80000000
    fd40:	f170 0200 	sbcs.w	r2, r0, #0
    fd44:	da0a      	bge.n	fd5c <next_timeout+0x3c>
		ret = MAX_WAIT;
	} else {
		ret = MAX(0, to->dticks - ticks_elapsed);
    fd46:	2800      	cmp	r0, #0
    fd48:	bfac      	ite	ge
    fd4a:	4618      	movge	r0, r3
    fd4c:	2000      	movlt	r0, #0
	}

#ifdef CONFIG_TIMESLICING
	if (_current_cpu->slice_ticks && _current_cpu->slice_ticks < ret) {
    fd4e:	4b06      	ldr	r3, [pc, #24]	; (fd68 <next_timeout+0x48>)
    fd50:	691b      	ldr	r3, [r3, #16]
    fd52:	b113      	cbz	r3, fd5a <next_timeout+0x3a>
    fd54:	4298      	cmp	r0, r3
    fd56:	bfa8      	it	ge
    fd58:	4618      	movge	r0, r3
		ret = _current_cpu->slice_ticks;
	}
#endif
	return ret;
}
    fd5a:	bd10      	pop	{r4, pc}
		ret = MAX_WAIT;
    fd5c:	f06f 4000 	mvn.w	r0, #2147483648	; 0x80000000
    fd60:	e7f5      	b.n	fd4e <next_timeout+0x2e>
    fd62:	bf00      	nop
    fd64:	20000084 	.word	0x20000084
    fd68:	20000338 	.word	0x20000338

0000fd6c <remove_timeout>:
{
    fd6c:	b530      	push	{r4, r5, lr}
	return (node == list->tail) ? NULL : node->next;
    fd6e:	6803      	ldr	r3, [r0, #0]
	return (node != NULL) ? sys_dlist_peek_next_no_check(list, node) : NULL;
    fd70:	b168      	cbz	r0, fd8e <remove_timeout+0x22>
	return (node == list->tail) ? NULL : node->next;
    fd72:	4a0a      	ldr	r2, [pc, #40]	; (fd9c <remove_timeout+0x30>)
    fd74:	6852      	ldr	r2, [r2, #4]
    fd76:	4290      	cmp	r0, r2
    fd78:	d009      	beq.n	fd8e <remove_timeout+0x22>
	if (next(t) != NULL) {
    fd7a:	b143      	cbz	r3, fd8e <remove_timeout+0x22>
		next(t)->dticks += t->dticks;
    fd7c:	e9d3 2104 	ldrd	r2, r1, [r3, #16]
    fd80:	e9d0 4504 	ldrd	r4, r5, [r0, #16]
    fd84:	1912      	adds	r2, r2, r4
    fd86:	eb41 0105 	adc.w	r1, r1, r5
    fd8a:	e9c3 2104 	strd	r2, r1, [r3, #16]
 * @param node the node to remove
 */

static inline void sys_dlist_remove(sys_dnode_t *node)
{
	sys_dnode_t *const prev = node->prev;
    fd8e:	6842      	ldr	r2, [r0, #4]
	sys_dnode_t *const next = node->next;

	prev->next = next;
    fd90:	6013      	str	r3, [r2, #0]
	next->prev = prev;
    fd92:	605a      	str	r2, [r3, #4]
	node->next = NULL;
    fd94:	2300      	movs	r3, #0
	node->prev = NULL;
    fd96:	e9c0 3300 	strd	r3, r3, [r0]
}
    fd9a:	bd30      	pop	{r4, r5, pc}
    fd9c:	20000084 	.word	0x20000084

0000fda0 <z_add_timeout>:

void z_add_timeout(struct _timeout *to, _timeout_func_t fn,
		   k_timeout_t timeout)
{
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    fda0:	f1b3 3fff 	cmp.w	r3, #4294967295
    fda4:	bf08      	it	eq
    fda6:	f1b2 3fff 	cmpeq.w	r2, #4294967295
{
    fdaa:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    fdac:	4604      	mov	r4, r0
    fdae:	461f      	mov	r7, r3
    fdb0:	4615      	mov	r5, r2
	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
    fdb2:	d067      	beq.n	fe84 <z_add_timeout+0xe4>
#ifdef CONFIG_KERNEL_COHERENCE
	__ASSERT_NO_MSG(arch_mem_coherent(to));
#endif

	__ASSERT(!sys_dnode_is_linked(&to->node), "");
	to->fn = fn;
    fdb4:	6081      	str	r1, [r0, #8]
	__asm__ volatile(
    fdb6:	f04f 0320 	mov.w	r3, #32
    fdba:	f3ef 8611 	mrs	r6, BASEPRI
    fdbe:	f383 8812 	msr	BASEPRI_MAX, r3
    fdc2:	f3bf 8f6f 	isb	sy

	LOCKED(&timeout_lock) {
		struct _timeout *t;

		if (IS_ENABLED(CONFIG_TIMEOUT_64BIT) &&
		    Z_TICK_ABS(timeout.ticks) >= 0) {
    fdc6:	f06f 0201 	mvn.w	r2, #1
    fdca:	1b53      	subs	r3, r2, r5
    fdcc:	f04f 3cff 	mov.w	ip, #4294967295
    fdd0:	eb6c 0307 	sbc.w	r3, ip, r7
		if (IS_ENABLED(CONFIG_TIMEOUT_64BIT) &&
    fdd4:	2b00      	cmp	r3, #0
    fdd6:	db1b      	blt.n	fe10 <z_add_timeout+0x70>
			k_ticks_t ticks = Z_TICK_ABS(timeout.ticks) - curr_tick;
    fdd8:	4b2b      	ldr	r3, [pc, #172]	; (fe88 <z_add_timeout+0xe8>)
    fdda:	e9d3 1300 	ldrd	r1, r3, [r3]
    fdde:	1a52      	subs	r2, r2, r1
    fde0:	eb6c 0303 	sbc.w	r3, ip, r3
    fde4:	1b55      	subs	r5, r2, r5

			to->dticks = MAX(1, ticks);
    fde6:	eb63 0307 	sbc.w	r3, r3, r7
    fdea:	2d01      	cmp	r5, #1
    fdec:	f173 0200 	sbcs.w	r2, r3, #0
    fdf0:	bfbc      	itt	lt
    fdf2:	2501      	movlt	r5, #1
    fdf4:	2300      	movlt	r3, #0
    fdf6:	e9c0 5304 	strd	r5, r3, [r0, #16]
	return list->head == list;
    fdfa:	4824      	ldr	r0, [pc, #144]	; (fe8c <z_add_timeout+0xec>)
	sys_dnode_t *const tail = list->tail;
    fdfc:	e9d0 3c00 	ldrd	r3, ip, [r0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    fe00:	4283      	cmp	r3, r0
    fe02:	d118      	bne.n	fe36 <z_add_timeout+0x96>
	node->prev = tail;
    fe04:	e9c4 0c00 	strd	r0, ip, [r4]
	tail->next = node;
    fe08:	f8cc 4000 	str.w	r4, [ip]
	list->tail = node;
    fe0c:	6044      	str	r4, [r0, #4]
}
    fe0e:	e026      	b.n	fe5e <z_add_timeout+0xbe>
		} else {
			to->dticks = timeout.ticks + 1 + elapsed();
    fe10:	f7ff ff7c 	bl	fd0c <elapsed>
    fe14:	3501      	adds	r5, #1
    fe16:	f147 0700 	adc.w	r7, r7, #0
    fe1a:	182d      	adds	r5, r5, r0
    fe1c:	eb47 77e0 	adc.w	r7, r7, r0, asr #31
    fe20:	e9c4 5704 	strd	r5, r7, [r4, #16]
    fe24:	e7e9      	b.n	fdfa <z_add_timeout+0x5a>
			if (t->dticks > to->dticks) {
				t->dticks -= to->dticks;
				sys_dlist_insert(&t->node, &to->node);
				break;
			}
			to->dticks -= t->dticks;
    fe26:	1a52      	subs	r2, r2, r1
    fe28:	eb65 0507 	sbc.w	r5, r5, r7
	return (node == list->tail) ? NULL : node->next;
    fe2c:	459c      	cmp	ip, r3
    fe2e:	e9c4 2504 	strd	r2, r5, [r4, #16]
    fe32:	d0e7      	beq.n	fe04 <z_add_timeout+0x64>
    fe34:	681b      	ldr	r3, [r3, #0]
		for (t = first(); t != NULL; t = next(t)) {
    fe36:	2b00      	cmp	r3, #0
    fe38:	d0e4      	beq.n	fe04 <z_add_timeout+0x64>
			if (t->dticks > to->dticks) {
    fe3a:	e9d3 1704 	ldrd	r1, r7, [r3, #16]
    fe3e:	e9d4 2504 	ldrd	r2, r5, [r4, #16]
    fe42:	428a      	cmp	r2, r1
    fe44:	eb75 0e07 	sbcs.w	lr, r5, r7
    fe48:	daed      	bge.n	fe26 <z_add_timeout+0x86>
				t->dticks -= to->dticks;
    fe4a:	1a8a      	subs	r2, r1, r2
    fe4c:	eb67 0505 	sbc.w	r5, r7, r5
    fe50:	e9c3 2504 	strd	r2, r5, [r3, #16]
	sys_dnode_t *const prev = successor->prev;
    fe54:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
    fe56:	e9c4 3200 	strd	r3, r2, [r4]
	prev->next = node;
    fe5a:	6014      	str	r4, [r2, #0]
	successor->prev = node;
    fe5c:	605c      	str	r4, [r3, #4]
	return list->head == list;
    fe5e:	6803      	ldr	r3, [r0, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    fe60:	4283      	cmp	r3, r0
    fe62:	d00b      	beq.n	fe7c <z_add_timeout+0xdc>

		if (t == NULL) {
			sys_dlist_append(&timeout_list, &to->node);
		}

		if (to == first()) {
    fe64:	429c      	cmp	r4, r3
    fe66:	d109      	bne.n	fe7c <z_add_timeout+0xdc>
			 * last announcement, and slice_ticks is based
			 * on that. It means that the time remaining for
			 * the next announcement can be less than
			 * slice_ticks.
			 */
			int32_t next_time = next_timeout();
    fe68:	f7ff ff5a 	bl	fd20 <next_timeout>

			if (next_time == 0 ||
    fe6c:	b118      	cbz	r0, fe76 <z_add_timeout+0xd6>
			    _current_cpu->slice_ticks != next_time) {
    fe6e:	4b08      	ldr	r3, [pc, #32]	; (fe90 <z_add_timeout+0xf0>)
			if (next_time == 0 ||
    fe70:	691b      	ldr	r3, [r3, #16]
    fe72:	4283      	cmp	r3, r0
    fe74:	d002      	beq.n	fe7c <z_add_timeout+0xdc>
				sys_clock_set_timeout(next_time, false);
    fe76:	2100      	movs	r1, #0
    fe78:	f7fe fc22 	bl	e6c0 <sys_clock_set_timeout>
	__asm__ volatile(
    fe7c:	f386 8811 	msr	BASEPRI, r6
    fe80:	f3bf 8f6f 	isb	sy
#else
			sys_clock_set_timeout(next_timeout(), false);
#endif	/* CONFIG_TIMESLICING */
		}
	}
}
    fe84:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    fe86:	bf00      	nop
    fe88:	200001b8 	.word	0x200001b8
    fe8c:	20000084 	.word	0x20000084
    fe90:	20000338 	.word	0x20000338

0000fe94 <sys_clock_announce>:
		}
	}
}

void sys_clock_announce(int32_t ticks)
{
    fe94:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
    fe98:	4605      	mov	r5, r0
#ifdef CONFIG_TIMESLICING
	z_time_slice(ticks);
    fe9a:	f7ff fce1 	bl	f860 <z_time_slice>
	__asm__ volatile(
    fe9e:	f04f 0320 	mov.w	r3, #32
    fea2:	f3ef 8411 	mrs	r4, BASEPRI
    fea6:	f383 8812 	msr	BASEPRI_MAX, r3
    feaa:	f3bf 8f6f 	isb	sy
		announce_remaining += ticks;
		k_spin_unlock(&timeout_lock, key);
		return;
	}

	announce_remaining = ticks;
    feae:	4e24      	ldr	r6, [pc, #144]	; (ff40 <sys_clock_announce+0xac>)
	return list->head == list;
    feb0:	f8df 8090 	ldr.w	r8, [pc, #144]	; ff44 <sys_clock_announce+0xb0>
    feb4:	6035      	str	r5, [r6, #0]

	while (first() != NULL && first()->dticks <= announce_remaining) {
		struct _timeout *t = first();
		int dt = t->dticks;

		curr_tick += dt;
    feb6:	4d24      	ldr	r5, [pc, #144]	; (ff48 <sys_clock_announce+0xb4>)
    feb8:	f8d8 0000 	ldr.w	r0, [r8]
	while (first() != NULL && first()->dticks <= announce_remaining) {
    febc:	6832      	ldr	r2, [r6, #0]
	return sys_dlist_is_empty(list) ? NULL : list->head;
    febe:	4540      	cmp	r0, r8
		curr_tick += dt;
    fec0:	e9d5 1e00 	ldrd	r1, lr, [r5]
    fec4:	ea4f 77e2 	mov.w	r7, r2, asr #31
    fec8:	d00b      	beq.n	fee2 <sys_clock_announce+0x4e>
	while (first() != NULL && first()->dticks <= announce_remaining) {
    feca:	b150      	cbz	r0, fee2 <sys_clock_announce+0x4e>
    fecc:	e9d0 3c04 	ldrd	r3, ip, [r0, #16]
    fed0:	429a      	cmp	r2, r3
    fed2:	eb77 090c 	sbcs.w	r9, r7, ip
    fed6:	da16      	bge.n	ff06 <sys_clock_announce+0x72>
		t->fn(t);
		key = k_spin_lock(&timeout_lock);
	}

	if (first() != NULL) {
		first()->dticks -= announce_remaining;
    fed8:	1a9b      	subs	r3, r3, r2
    feda:	eb6c 0c07 	sbc.w	ip, ip, r7
    fede:	e9c0 3c04 	strd	r3, ip, [r0, #16]
	}

	curr_tick += announce_remaining;
    fee2:	1852      	adds	r2, r2, r1
    fee4:	eb4e 0707 	adc.w	r7, lr, r7
    fee8:	e9c5 2700 	strd	r2, r7, [r5]
	announce_remaining = 0;
    feec:	2500      	movs	r5, #0
    feee:	6035      	str	r5, [r6, #0]

	sys_clock_set_timeout(next_timeout(), false);
    fef0:	f7ff ff16 	bl	fd20 <next_timeout>
    fef4:	4629      	mov	r1, r5
    fef6:	f7fe fbe3 	bl	e6c0 <sys_clock_set_timeout>
	__asm__ volatile(
    fefa:	f384 8811 	msr	BASEPRI, r4
    fefe:	f3bf 8f6f 	isb	sy

	k_spin_unlock(&timeout_lock, key);
}
    ff02:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
		curr_tick += dt;
    ff06:	1859      	adds	r1, r3, r1
    ff08:	eb4e 77e3 	adc.w	r7, lr, r3, asr #31
		announce_remaining -= dt;
    ff0c:	1ad3      	subs	r3, r2, r3
    ff0e:	6033      	str	r3, [r6, #0]
		t->dticks = 0;
    ff10:	2200      	movs	r2, #0
    ff12:	2300      	movs	r3, #0
    ff14:	e9c0 2304 	strd	r2, r3, [r0, #16]
		curr_tick += dt;
    ff18:	e9c5 1700 	strd	r1, r7, [r5]
		remove_timeout(t);
    ff1c:	f7ff ff26 	bl	fd6c <remove_timeout>
    ff20:	f384 8811 	msr	BASEPRI, r4
    ff24:	f3bf 8f6f 	isb	sy
		t->fn(t);
    ff28:	6883      	ldr	r3, [r0, #8]
    ff2a:	4798      	blx	r3
	__asm__ volatile(
    ff2c:	f04f 0320 	mov.w	r3, #32
    ff30:	f3ef 8411 	mrs	r4, BASEPRI
    ff34:	f383 8812 	msr	BASEPRI_MAX, r3
    ff38:	f3bf 8f6f 	isb	sy
#endif

#ifdef CONFIG_SPIN_VALIDATE
	z_spin_lock_set_owner(l);
#endif
	return k;
    ff3c:	e7bc      	b.n	feb8 <sys_clock_announce+0x24>
    ff3e:	bf00      	nop
    ff40:	2000036c 	.word	0x2000036c
    ff44:	20000084 	.word	0x20000084
    ff48:	200001b8 	.word	0x200001b8

0000ff4c <sys_clock_tick_get>:

int64_t sys_clock_tick_get(void)
{
    ff4c:	b510      	push	{r4, lr}
    ff4e:	f04f 0320 	mov.w	r3, #32
    ff52:	f3ef 8411 	mrs	r4, BASEPRI
    ff56:	f383 8812 	msr	BASEPRI_MAX, r3
    ff5a:	f3bf 8f6f 	isb	sy
	uint64_t t = 0U;

	LOCKED(&timeout_lock) {
		t = curr_tick + sys_clock_elapsed();
    ff5e:	f7fe fbe1 	bl	e724 <sys_clock_elapsed>
    ff62:	4a05      	ldr	r2, [pc, #20]	; (ff78 <__kernel_ram_size+0x10>)
    ff64:	e9d2 3100 	ldrd	r3, r1, [r2]
    ff68:	18c0      	adds	r0, r0, r3
    ff6a:	f141 0100 	adc.w	r1, r1, #0
	__asm__ volatile(
    ff6e:	f384 8811 	msr	BASEPRI, r4
    ff72:	f3bf 8f6f 	isb	sy
	}
	return t;
}
    ff76:	bd10      	pop	{r4, pc}
    ff78:	200001b8 	.word	0x200001b8

0000ff7c <boot_banner>:
		k_busy_wait(CONFIG_BOOT_DELAY * USEC_PER_MSEC);
	}

#if defined(CONFIG_BOOT_BANNER)
#ifdef BUILD_VERSION
	printk("*** Booting Zephyr OS build %s %s ***\n",
    ff7c:	4a02      	ldr	r2, [pc, #8]	; (ff88 <boot_banner+0xc>)
    ff7e:	4903      	ldr	r1, [pc, #12]	; (ff8c <boot_banner+0x10>)
    ff80:	4803      	ldr	r0, [pc, #12]	; (ff90 <boot_banner+0x14>)
    ff82:	f000 b827 	b.w	ffd4 <printk>
    ff86:	bf00      	nop
    ff88:	00010d27 	.word	0x00010d27
    ff8c:	00010cf4 	.word	0x00010cf4
    ff90:	00010d01 	.word	0x00010d01

0000ff94 <sys_notify_validate>:

int sys_notify_validate(struct sys_notify *notify)
{
	int rv = 0;

	if (notify == NULL) {
    ff94:	4603      	mov	r3, r0
    ff96:	b158      	cbz	r0, ffb0 <sys_notify_validate+0x1c>
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    ff98:	6842      	ldr	r2, [r0, #4]
	return method & SYS_NOTIFY_METHOD_MASK;
    ff9a:	f002 0203 	and.w	r2, r2, #3
		return -EINVAL;
	}

	/* Validate configuration based on mode */
	switch (sys_notify_get_method(notify)) {
    ff9e:	2a01      	cmp	r2, #1
    ffa0:	d003      	beq.n	ffaa <sys_notify_validate+0x16>
    ffa2:	2a03      	cmp	r2, #3
    ffa4:	d104      	bne.n	ffb0 <sys_notify_validate+0x1c>
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		if (notify->method.callback == NULL) {
    ffa6:	6802      	ldr	r2, [r0, #0]
    ffa8:	b112      	cbz	r2, ffb0 <sys_notify_validate+0x1c>
		break;
	}

	/* Clear the result here instead of in all callers. */
	if (rv == 0) {
		notify->result = 0;
    ffaa:	2000      	movs	r0, #0
    ffac:	6098      	str	r0, [r3, #8]
    ffae:	4770      	bx	lr
		return -EINVAL;
    ffb0:	f06f 0015 	mvn.w	r0, #21
	}

	return rv;
}
    ffb4:	4770      	bx	lr

0000ffb6 <sys_notify_finalize>:
	uint32_t method = notify->flags >> SYS_NOTIFY_METHOD_POS;
    ffb6:	6842      	ldr	r2, [r0, #4]
	uint32_t method = sys_notify_get_method(notify);

	/* Store the result and capture secondary notification
	 * information.
	 */
	notify->result = res;
    ffb8:	6081      	str	r1, [r0, #8]
	return method & SYS_NOTIFY_METHOD_MASK;
    ffba:	f002 0203 	and.w	r2, r2, #3
	switch (method) {
    ffbe:	2a03      	cmp	r2, #3
    ffc0:	f04f 0200 	mov.w	r2, #0
{
    ffc4:	4603      	mov	r3, r0
	case SYS_NOTIFY_METHOD_SPINWAIT:
		break;
	case SYS_NOTIFY_METHOD_CALLBACK:
		rv = notify->method.callback;
    ffc6:	bf0c      	ite	eq
    ffc8:	6800      	ldreq	r0, [r0, #0]
	sys_notify_generic_callback rv = NULL;
    ffca:	4610      	movne	r0, r2
	/* Mark completion by clearing the flags field to the
	 * completed state, releasing any spin-waiters, then complete
	 * secondary notification.
	 */
	compiler_barrier();
	notify->flags = SYS_NOTIFY_METHOD_COMPLETED;
    ffcc:	605a      	str	r2, [r3, #4]
	if (IS_ENABLED(CONFIG_POLL) && (sig != NULL)) {
		k_poll_signal_raise(sig, res);
	}

	return rv;
}
    ffce:	4770      	bx	lr

0000ffd0 <arch_printk_char_out>:
}
    ffd0:	2000      	movs	r0, #0
    ffd2:	4770      	bx	lr

0000ffd4 <printk>:
 *
 * @param fmt formatted string to output
 */

void printk(const char *fmt, ...)
{
    ffd4:	b40f      	push	{r0, r1, r2, r3}
    ffd6:	b507      	push	{r0, r1, r2, lr}
    ffd8:	a904      	add	r1, sp, #16
    ffda:	f851 0b04 	ldr.w	r0, [r1], #4
	va_list ap;

	va_start(ap, fmt);
    ffde:	9101      	str	r1, [sp, #4]

	vprintk(fmt, ap);
    ffe0:	f7fc fb00 	bl	c5e4 <vprintk>

	va_end(ap);
}
    ffe4:	b003      	add	sp, #12
    ffe6:	f85d eb04 	ldr.w	lr, [sp], #4
    ffea:	b004      	add	sp, #16
    ffec:	4770      	bx	lr

0000ffee <process_recheck>:
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
    ffee:	8b03      	ldrh	r3, [r0, #24]
	if ((state == ONOFF_STATE_OFF)
    fff0:	f013 0307 	ands.w	r3, r3, #7
    fff4:	d105      	bne.n	10002 <CONFIG_PM_SRAM_SIZE+0x2>
	    && !sys_slist_is_empty(&mgr->clients)) {
    fff6:	6803      	ldr	r3, [r0, #0]
		evt = EVT_START;
    fff8:	2b00      	cmp	r3, #0
    fffa:	bf0c      	ite	eq
    fffc:	2000      	moveq	r0, #0
    fffe:	2003      	movne	r0, #3
   10000:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ON)
   10002:	2b02      	cmp	r3, #2
   10004:	d105      	bne.n	10012 <CONFIG_PM_SRAM_SIZE+0x12>
		   && (mgr->refs == 0U)) {
   10006:	8b43      	ldrh	r3, [r0, #26]
		evt = EVT_STOP;
   10008:	2b00      	cmp	r3, #0
   1000a:	bf14      	ite	ne
   1000c:	2000      	movne	r0, #0
   1000e:	2004      	moveq	r0, #4
   10010:	4770      	bx	lr
	} else if ((state == ONOFF_STATE_ERROR)
   10012:	2b01      	cmp	r3, #1
   10014:	d105      	bne.n	10022 <CONFIG_PM_SRAM_SIZE+0x22>
		   && !sys_slist_is_empty(&mgr->clients)) {
   10016:	6803      	ldr	r3, [r0, #0]
		evt = EVT_RESET;
   10018:	2b00      	cmp	r3, #0
   1001a:	bf0c      	ite	eq
   1001c:	2000      	moveq	r0, #0
   1001e:	2005      	movne	r0, #5
   10020:	4770      	bx	lr
	int evt = EVT_NOP;
   10022:	2000      	movs	r0, #0
}
   10024:	4770      	bx	lr

00010026 <notify_one>:
{
   10026:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
   1002a:	460d      	mov	r5, r1
   1002c:	4607      	mov	r7, r0
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
   1002e:	4619      	mov	r1, r3
   10030:	1d28      	adds	r0, r5, #4
{
   10032:	4690      	mov	r8, r2
   10034:	461e      	mov	r6, r3
		(onoff_client_callback)sys_notify_finalize(&cli->notify, res);
   10036:	f7ff ffbe 	bl	ffb6 <sys_notify_finalize>
	if (cb) {
   1003a:	4604      	mov	r4, r0
   1003c:	b138      	cbz	r0, 1004e <notify_one+0x28>
		cb(mgr, cli, state, res);
   1003e:	4633      	mov	r3, r6
   10040:	4642      	mov	r2, r8
   10042:	4629      	mov	r1, r5
   10044:	4638      	mov	r0, r7
   10046:	46a4      	mov	ip, r4
}
   10048:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
		cb(mgr, cli, state, res);
   1004c:	4760      	bx	ip
}
   1004e:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00010052 <transition_complete>:
{
   10052:	b410      	push	{r4}
	__asm__ volatile(
   10054:	f04f 0420 	mov.w	r4, #32
   10058:	f3ef 8211 	mrs	r2, BASEPRI
   1005c:	f384 8812 	msr	BASEPRI_MAX, r4
   10060:	f3bf 8f6f 	isb	sy
	mgr->last_res = res;
   10064:	6141      	str	r1, [r0, #20]
}
   10066:	bc10      	pop	{r4}
	process_event(mgr, EVT_COMPLETE, key);
   10068:	2101      	movs	r1, #1
   1006a:	f7fc bac9 	b.w	c600 <process_event>

0001006e <validate_args>:
{
   1006e:	b510      	push	{r4, lr}
   10070:	460c      	mov	r4, r1
	if ((mgr == NULL) || (cli == NULL)) {
   10072:	b140      	cbz	r0, 10086 <validate_args+0x18>
   10074:	b139      	cbz	r1, 10086 <validate_args+0x18>
	int rv = sys_notify_validate(&cli->notify);
   10076:	1d08      	adds	r0, r1, #4
   10078:	f7ff ff8c 	bl	ff94 <sys_notify_validate>
	if ((rv == 0)
   1007c:	b928      	cbnz	r0, 1008a <validate_args+0x1c>
	    && ((cli->notify.flags
   1007e:	68a3      	ldr	r3, [r4, #8]
   10080:	f033 0303 	bics.w	r3, r3, #3
   10084:	d001      	beq.n	1008a <validate_args+0x1c>
		rv = -EINVAL;
   10086:	f06f 0015 	mvn.w	r0, #21
}
   1008a:	bd10      	pop	{r4, pc}

0001008c <onoff_manager_init>:
{
   1008c:	b538      	push	{r3, r4, r5, lr}
   1008e:	460c      	mov	r4, r1
	if ((mgr == NULL)
   10090:	4605      	mov	r5, r0
   10092:	b158      	cbz	r0, 100ac <onoff_manager_init+0x20>
	    || (transitions == NULL)
   10094:	b151      	cbz	r1, 100ac <onoff_manager_init+0x20>
	    || (transitions->start == NULL)
   10096:	680b      	ldr	r3, [r1, #0]
   10098:	b143      	cbz	r3, 100ac <onoff_manager_init+0x20>
	    || (transitions->stop == NULL)) {
   1009a:	684b      	ldr	r3, [r1, #4]
   1009c:	b133      	cbz	r3, 100ac <onoff_manager_init+0x20>
	*mgr = (struct onoff_manager)ONOFF_MANAGER_INITIALIZER(transitions);
   1009e:	221c      	movs	r2, #28
   100a0:	2100      	movs	r1, #0
   100a2:	f000 f8ec 	bl	1027e <memset>
   100a6:	612c      	str	r4, [r5, #16]
	return 0;
   100a8:	2000      	movs	r0, #0
}
   100aa:	bd38      	pop	{r3, r4, r5, pc}
		return -EINVAL;
   100ac:	f06f 0015 	mvn.w	r0, #21
   100b0:	e7fb      	b.n	100aa <onoff_manager_init+0x1e>

000100b2 <onoff_request>:

int onoff_request(struct onoff_manager *mgr,
		  struct onoff_client *cli)
{
   100b2:	b570      	push	{r4, r5, r6, lr}
   100b4:	4604      	mov	r4, r0
   100b6:	460e      	mov	r6, r1
	bool add_client = false;        /* add client to pending list */
	bool start = false;             /* trigger a start transition */
	bool notify = false;            /* do client notification */
	int rv = validate_args(mgr, cli);
   100b8:	f7ff ffd9 	bl	1006e <validate_args>

	if (rv < 0) {
   100bc:	1e05      	subs	r5, r0, #0
   100be:	db31      	blt.n	10124 <onoff_request+0x72>
   100c0:	f04f 0320 	mov.w	r3, #32
   100c4:	f3ef 8111 	mrs	r1, BASEPRI
   100c8:	f383 8812 	msr	BASEPRI_MAX, r3
   100cc:	f3bf 8f6f 	isb	sy

	k_spinlock_key_t key = k_spin_lock(&mgr->lock);
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;

	/* Reject if this would overflow the reference count. */
	if (mgr->refs == SERVICE_REFS_MAX) {
   100d0:	8b63      	ldrh	r3, [r4, #26]
	uint32_t state = mgr->flags & ONOFF_STATE_MASK;
   100d2:	8b20      	ldrh	r0, [r4, #24]
	if (mgr->refs == SERVICE_REFS_MAX) {
   100d4:	f64f 75ff 	movw	r5, #65535	; 0xffff
   100d8:	42ab      	cmp	r3, r5
   100da:	f000 0207 	and.w	r2, r0, #7
   100de:	d02e      	beq.n	1013e <onoff_request+0x8c>
		rv = -EAGAIN;
		goto out;
	}

	rv = state;
	if (state == ONOFF_STATE_ON) {
   100e0:	2a02      	cmp	r2, #2
   100e2:	d10e      	bne.n	10102 <onoff_request+0x50>
		/* Increment reference count, notify in exit */
		notify = true;
		mgr->refs += 1U;
   100e4:	3301      	adds	r3, #1
   100e6:	8363      	strh	r3, [r4, #26]
	rv = state;
   100e8:	4615      	mov	r5, r2
		notify = true;
   100ea:	2301      	movs	r3, #1
	__asm__ volatile(
   100ec:	f381 8811 	msr	BASEPRI, r1
   100f0:	f3bf 8f6f 	isb	sy
	if (start) {
		process_event(mgr, EVT_RECHECK, key);
	} else {
		k_spin_unlock(&mgr->lock, key);

		if (notify) {
   100f4:	b1b3      	cbz	r3, 10124 <onoff_request+0x72>
			notify_one(mgr, cli, state, 0);
   100f6:	2300      	movs	r3, #0
   100f8:	4631      	mov	r1, r6
   100fa:	4620      	mov	r0, r4
   100fc:	f7ff ff93 	bl	10026 <notify_one>
   10100:	e010      	b.n	10124 <onoff_request+0x72>
	} else if ((state == ONOFF_STATE_OFF)
   10102:	0783      	lsls	r3, r0, #30
   10104:	d001      	beq.n	1010a <onoff_request+0x58>
		   || (state == ONOFF_STATE_TO_ON)) {
   10106:	2a06      	cmp	r2, #6
   10108:	d10e      	bne.n	10128 <onoff_request+0x76>
	parent->next = child;
   1010a:	2300      	movs	r3, #0
   1010c:	6033      	str	r3, [r6, #0]
 *
 * @return A pointer on the last node of the list (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_tail(sys_slist_t *list)
{
	return list->tail;
   1010e:	6863      	ldr	r3, [r4, #4]
 * @param node A pointer on the node to append
 */
static inline void sys_slist_append(sys_slist_t *list,
				    sys_snode_t *node);

Z_GENLIST_APPEND(slist, snode)
   10110:	b993      	cbnz	r3, 10138 <onoff_request+0x86>
	list->head = node;
   10112:	e9c4 6600 	strd	r6, r6, [r4]
	if (start) {
   10116:	4615      	mov	r5, r2
   10118:	b962      	cbnz	r2, 10134 <onoff_request+0x82>
		process_event(mgr, EVT_RECHECK, key);
   1011a:	460a      	mov	r2, r1
   1011c:	4620      	mov	r0, r4
   1011e:	2102      	movs	r1, #2
   10120:	f7fc fa6e 	bl	c600 <process_event>
		}
	}

	return rv;
}
   10124:	4628      	mov	r0, r5
   10126:	bd70      	pop	{r4, r5, r6, pc}
		rv = -EIO;
   10128:	2a05      	cmp	r2, #5
   1012a:	bf0c      	ite	eq
   1012c:	f06f 0585 	mvneq.w	r5, #133	; 0x85
   10130:	f06f 0504 	mvnne.w	r5, #4
   10134:	2300      	movs	r3, #0
   10136:	e7d9      	b.n	100ec <onoff_request+0x3a>
	parent->next = child;
   10138:	601e      	str	r6, [r3, #0]
	list->tail = node;
   1013a:	6066      	str	r6, [r4, #4]
}
   1013c:	e7eb      	b.n	10116 <onoff_request+0x64>
		rv = -EAGAIN;
   1013e:	f06f 050a 	mvn.w	r5, #10
   10142:	e7f7      	b.n	10134 <onoff_request+0x82>

00010144 <z_thread_entry>:
 * This routine does not return, and is marked as such so the compiler won't
 * generate preamble code that is only used by functions that actually return.
 */
FUNC_NORETURN void z_thread_entry(k_thread_entry_t entry,
				 void *p1, void *p2, void *p3)
{
   10144:	4604      	mov	r4, r0
   10146:	b508      	push	{r3, lr}
   10148:	4608      	mov	r0, r1
   1014a:	4611      	mov	r1, r2
#ifdef CONFIG_THREAD_LOCAL_STORAGE
	z_tls_current = z_current_get();
#endif
	entry(p1, p2, p3);
   1014c:	461a      	mov	r2, r3
   1014e:	47a0      	blx	r4
	return z_impl_z_current_get();
   10150:	f7ff fd6a 	bl	fc28 <z_impl_z_current_get>
	z_impl_k_thread_abort(thread);
   10154:	f7fd fb0c 	bl	d770 <z_impl_k_thread_abort>

00010158 <encode_uint>:
{
   10158:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
   1015c:	469a      	mov	sl, r3
	bool upcase = isupper((int)conv->specifier);
   1015e:	78d3      	ldrb	r3, [r2, #3]
	switch (specifier) {
   10160:	2b6f      	cmp	r3, #111	; 0x6f
{
   10162:	4680      	mov	r8, r0
   10164:	460f      	mov	r7, r1
   10166:	4615      	mov	r5, r2
	return (int)(((unsigned)(a)-(unsigned)'A') < 26U);
   10168:	f1a3 0b41 	sub.w	fp, r3, #65	; 0x41
	switch (specifier) {
   1016c:	d029      	beq.n	101c2 <encode_uint+0x6a>
   1016e:	d824      	bhi.n	101ba <encode_uint+0x62>
		return 16;
   10170:	2b58      	cmp	r3, #88	; 0x58
   10172:	bf14      	ite	ne
   10174:	260a      	movne	r6, #10
   10176:	2610      	moveq	r6, #16
	char *bp = bps + (bpe - bps);
   10178:	f8dd 9028 	ldr.w	r9, [sp, #40]	; 0x28
		unsigned int lsv = (unsigned int)(value % radix);
   1017c:	4632      	mov	r2, r6
   1017e:	2300      	movs	r3, #0
   10180:	4640      	mov	r0, r8
   10182:	4639      	mov	r1, r7
   10184:	f7fc f8aa 	bl	c2dc <__aeabi_uldivmod>
		*--bp = (lsv <= 9) ? ('0' + lsv)
   10188:	2a09      	cmp	r2, #9
   1018a:	b2d4      	uxtb	r4, r2
   1018c:	d81e      	bhi.n	101cc <encode_uint+0x74>
   1018e:	3430      	adds	r4, #48	; 0x30
	} while ((value != 0) && (bps < bp));
   10190:	45b0      	cmp	r8, r6
		*--bp = (lsv <= 9) ? ('0' + lsv)
   10192:	b2e4      	uxtb	r4, r4
	} while ((value != 0) && (bps < bp));
   10194:	f177 0300 	sbcs.w	r3, r7, #0
		*--bp = (lsv <= 9) ? ('0' + lsv)
   10198:	f809 4d01 	strb.w	r4, [r9, #-1]!
	} while ((value != 0) && (bps < bp));
   1019c:	d301      	bcc.n	101a2 <encode_uint+0x4a>
   1019e:	45d1      	cmp	r9, sl
   101a0:	d811      	bhi.n	101c6 <encode_uint+0x6e>
	if (conv->flag_hash) {
   101a2:	782b      	ldrb	r3, [r5, #0]
   101a4:	069b      	lsls	r3, r3, #26
   101a6:	d505      	bpl.n	101b4 <encode_uint+0x5c>
		if (radix == 8) {
   101a8:	2e08      	cmp	r6, #8
   101aa:	d115      	bne.n	101d8 <encode_uint+0x80>
			conv->altform_0 = true;
   101ac:	78ab      	ldrb	r3, [r5, #2]
   101ae:	f043 0308 	orr.w	r3, r3, #8
			conv->altform_0c = true;
   101b2:	70ab      	strb	r3, [r5, #2]
}
   101b4:	4648      	mov	r0, r9
   101b6:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
	switch (specifier) {
   101ba:	f003 03f7 	and.w	r3, r3, #247	; 0xf7
		return 16;
   101be:	2b70      	cmp	r3, #112	; 0x70
   101c0:	e7d7      	b.n	10172 <encode_uint+0x1a>
	switch (specifier) {
   101c2:	2608      	movs	r6, #8
   101c4:	e7d8      	b.n	10178 <encode_uint+0x20>
		value /= radix;
   101c6:	4680      	mov	r8, r0
   101c8:	460f      	mov	r7, r1
   101ca:	e7d7      	b.n	1017c <encode_uint+0x24>
		*--bp = (lsv <= 9) ? ('0' + lsv)
   101cc:	f1bb 0f19 	cmp.w	fp, #25
   101d0:	bf94      	ite	ls
   101d2:	3437      	addls	r4, #55	; 0x37
   101d4:	3457      	addhi	r4, #87	; 0x57
   101d6:	e7db      	b.n	10190 <encode_uint+0x38>
		} else if (radix == 16) {
   101d8:	2e10      	cmp	r6, #16
   101da:	d1eb      	bne.n	101b4 <encode_uint+0x5c>
			conv->altform_0c = true;
   101dc:	78ab      	ldrb	r3, [r5, #2]
   101de:	f043 0310 	orr.w	r3, r3, #16
   101e2:	e7e6      	b.n	101b2 <encode_uint+0x5a>

000101e4 <outs>:
{
   101e4:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
   101e8:	4607      	mov	r7, r0
   101ea:	4688      	mov	r8, r1
   101ec:	4615      	mov	r5, r2
   101ee:	461e      	mov	r6, r3
	while ((sp < ep) || ((ep == NULL) && *sp)) {
   101f0:	4614      	mov	r4, r2
   101f2:	42b4      	cmp	r4, r6
   101f4:	eba4 0005 	sub.w	r0, r4, r5
   101f8:	d302      	bcc.n	10200 <outs+0x1c>
   101fa:	b93e      	cbnz	r6, 1020c <outs+0x28>
   101fc:	7823      	ldrb	r3, [r4, #0]
   101fe:	b12b      	cbz	r3, 1020c <outs+0x28>
		int rc = out((int)*sp++, ctx);
   10200:	f814 0b01 	ldrb.w	r0, [r4], #1
   10204:	4641      	mov	r1, r8
   10206:	47b8      	blx	r7
		if (rc < 0) {
   10208:	2800      	cmp	r0, #0
   1020a:	daf2      	bge.n	101f2 <outs+0xe>
}
   1020c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

00010210 <_ConfigAbsSyms>:
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_MCUBOOT_SIGNATURE_KEY_FILE, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_MCUBOOT_EXTRA_IMGTOOL_ARGS, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_COMPAT_INCLUDES, 1);
GEN_ABSOLUTE_SYM_KCONFIG(CONFIG_LEGACY_INCLUDE_PATH, 1);

GEN_ABS_SYM_END
   10210:	4770      	bx	lr

00010212 <z_arm_fatal_error>:
{

	if (esf != NULL) {
		esf_dump(esf);
	}
	z_fatal_error(reason, esf);
   10212:	f000 bab0 	b.w	10776 <z_fatal_error>

00010216 <z_do_kernel_oops>:
 *   fault handler will executed instead of the SVC.
 *
 * @param esf exception frame
 */
void z_do_kernel_oops(const z_arch_esf_t *esf)
{
   10216:	4601      	mov	r1, r0
	z_fatal_error(reason, esf);
   10218:	6800      	ldr	r0, [r0, #0]
   1021a:	f000 baac 	b.w	10776 <z_fatal_error>

0001021e <z_irq_spurious>:
 */
void z_irq_spurious(const void *unused)
{
	ARG_UNUSED(unused);

	z_arm_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
   1021e:	2100      	movs	r1, #0
   10220:	2001      	movs	r0, #1
   10222:	f7ff bff6 	b.w	10212 <z_arm_fatal_error>

00010226 <z_arm_nmi>:
 * Simply call what is installed in 'static void(*handler)(void)'.
 *
 */

void z_arm_nmi(void)
{
   10226:	b508      	push	{r3, lr}
	handler();
   10228:	f7fd f83e 	bl	d2a8 <z_SysNmiOnReset>
	z_arm_int_exit();
}
   1022c:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	z_arm_int_exit();
   10230:	f7fd b916 	b.w	d460 <z_arm_exc_exit>

00010234 <strcpy>:

char *strcpy(char *ZRESTRICT d, const char *ZRESTRICT s)
{
	char *dest = d;

	while (*s != '\0') {
   10234:	3901      	subs	r1, #1
   10236:	4603      	mov	r3, r0
   10238:	f811 2f01 	ldrb.w	r2, [r1, #1]!
   1023c:	b90a      	cbnz	r2, 10242 <strcpy+0xe>
		*d = *s;
		d++;
		s++;
	}

	*d = '\0';
   1023e:	701a      	strb	r2, [r3, #0]

	return dest;
}
   10240:	4770      	bx	lr
		*d = *s;
   10242:	f803 2b01 	strb.w	r2, [r3], #1
		s++;
   10246:	e7f7      	b.n	10238 <strcpy+0x4>

00010248 <strlen>:
 *
 * @return number of bytes in string <s>
 */

size_t strlen(const char *s)
{
   10248:	4603      	mov	r3, r0
	size_t n = 0;
   1024a:	2000      	movs	r0, #0

	while (*s != '\0') {
   1024c:	5c1a      	ldrb	r2, [r3, r0]
   1024e:	b902      	cbnz	r2, 10252 <strlen+0xa>
		s++;
		n++;
	}

	return n;
}
   10250:	4770      	bx	lr
		n++;
   10252:	3001      	adds	r0, #1
   10254:	e7fa      	b.n	1024c <strlen+0x4>

00010256 <strnlen>:
 *
 * @return number of bytes in fixed-size string <s>
 */

size_t strnlen(const char *s, size_t maxlen)
{
   10256:	4603      	mov	r3, r0
	size_t n = 0;
   10258:	2000      	movs	r0, #0

	while (*s != '\0' && n < maxlen) {
   1025a:	5c1a      	ldrb	r2, [r3, r0]
   1025c:	b10a      	cbz	r2, 10262 <strnlen+0xc>
   1025e:	4288      	cmp	r0, r1
   10260:	d100      	bne.n	10264 <strnlen+0xe>
		s++;
		n++;
	}

	return n;
}
   10262:	4770      	bx	lr
		n++;
   10264:	3001      	adds	r0, #1
   10266:	e7f8      	b.n	1025a <strnlen+0x4>

00010268 <memcpy>:
 *
 * @return pointer to start of destination buffer
 */

void *memcpy(void *ZRESTRICT d, const void *ZRESTRICT s, size_t n)
{
   10268:	b510      	push	{r4, lr}
   1026a:	1e43      	subs	r3, r0, #1
   1026c:	440a      	add	r2, r1
	}
#endif

	/* do byte-sized copying until finished */

	while (n > 0) {
   1026e:	4291      	cmp	r1, r2
   10270:	d100      	bne.n	10274 <memcpy+0xc>
		*(d_byte++) = *(s_byte++);
		n--;
	}

	return d;
}
   10272:	bd10      	pop	{r4, pc}
		*(d_byte++) = *(s_byte++);
   10274:	f811 4b01 	ldrb.w	r4, [r1], #1
   10278:	f803 4f01 	strb.w	r4, [r3, #1]!
		n--;
   1027c:	e7f7      	b.n	1026e <memcpy+0x6>

0001027e <memset>:
void *memset(void *buf, int c, size_t n)
{
	/* do byte-sized initialization until word-aligned or finished */

	unsigned char *d_byte = (unsigned char *)buf;
	unsigned char c_byte = (unsigned char)c;
   1027e:	b2c9      	uxtb	r1, r1
	/* do byte-sized initialization until finished */

	d_byte = (unsigned char *)d_word;
#endif

	while (n > 0) {
   10280:	4402      	add	r2, r0
	unsigned char *d_byte = (unsigned char *)buf;
   10282:	4603      	mov	r3, r0
	while (n > 0) {
   10284:	4293      	cmp	r3, r2
   10286:	d100      	bne.n	1028a <memset+0xc>
		*(d_byte++) = c_byte;
		n--;
	}

	return buf;
}
   10288:	4770      	bx	lr
		*(d_byte++) = c_byte;
   1028a:	f803 1b01 	strb.w	r1, [r3], #1
		n--;
   1028e:	e7f9      	b.n	10284 <memset+0x6>

00010290 <_stdout_hook_default>:
}
   10290:	f04f 30ff 	mov.w	r0, #4294967295
   10294:	4770      	bx	lr

00010296 <pm_state_set>:
/* Invoke Low Power/System Off specific Tasks */
__weak void pm_state_set(enum pm_state state, uint8_t substate_id)
{
	ARG_UNUSED(substate_id);

	switch (state) {
   10296:	2806      	cmp	r0, #6
   10298:	d108      	bne.n	102ac <pm_state_set+0x16>
    p_reg->SYSTEMOFF = POWER_SYSTEMOFF_SYSTEMOFF_Enter;
   1029a:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
   1029e:	2201      	movs	r2, #1
   102a0:	f8c3 2500 	str.w	r2, [r3, #1280]	; 0x500
  __ASM volatile ("dsb 0xF":::"memory");
   102a4:	f3bf 8f4f 	dsb	sy
        __WFE();
   102a8:	bf20      	wfe
    while (true)
   102aa:	e7fd      	b.n	102a8 <pm_state_set+0x12>
		break;
	default:
		LOG_DBG("Unsupported power state %u", state);
		break;
	}
}
   102ac:	4770      	bx	lr

000102ae <pm_state_exit_post_ops>:
   102ae:	2300      	movs	r3, #0
   102b0:	f383 8811 	msr	BASEPRI, r3
   102b4:	f3bf 8f6f 	isb	sy
	/*
	 * System is now in active mode. Reenable interrupts which were disabled
	 * when OS started idling code.
	 */
	irq_unlock(0);
}
   102b8:	4770      	bx	lr

000102ba <get_status>:
	return GET_STATUS(get_sub_data(dev, type)->flags);
   102ba:	6903      	ldr	r3, [r0, #16]
   102bc:	b2c9      	uxtb	r1, r1
   102be:	220c      	movs	r2, #12
   102c0:	fb01 3302 	mla	r3, r1, r2, r3
   102c4:	6c18      	ldr	r0, [r3, #64]	; 0x40
}
   102c6:	f000 0007 	and.w	r0, r0, #7
   102ca:	4770      	bx	lr

000102cc <set_on_state>:
	__asm__ volatile(
   102cc:	f04f 0320 	mov.w	r3, #32
   102d0:	f3ef 8211 	mrs	r2, BASEPRI
   102d4:	f383 8812 	msr	BASEPRI_MAX, r3
   102d8:	f3bf 8f6f 	isb	sy
	*flags = CLOCK_CONTROL_STATUS_ON | GET_CTX(*flags);
   102dc:	6803      	ldr	r3, [r0, #0]
   102de:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
   102e2:	f043 0302 	orr.w	r3, r3, #2
   102e6:	6003      	str	r3, [r0, #0]
	__asm__ volatile(
   102e8:	f382 8811 	msr	BASEPRI, r2
   102ec:	f3bf 8f6f 	isb	sy
}
   102f0:	4770      	bx	lr

000102f2 <stop>:
{
   102f2:	4603      	mov	r3, r0
   102f4:	b570      	push	{r4, r5, r6, lr}
	struct nrf_clock_control_data *data = dev->data;
   102f6:	6900      	ldr	r0, [r0, #16]
	return &data->subsys[type];
   102f8:	b2c9      	uxtb	r1, r1
	__asm__ volatile(
   102fa:	f04f 0420 	mov.w	r4, #32
   102fe:	f3ef 8611 	mrs	r6, BASEPRI
   10302:	f384 8812 	msr	BASEPRI_MAX, r4
   10306:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
   1030a:	250c      	movs	r5, #12
   1030c:	fb05 0401 	mla	r4, r5, r1, r0
   10310:	6c24      	ldr	r4, [r4, #64]	; 0x40
	if ((current_ctx != 0) && (current_ctx != ctx)) {
   10312:	f014 04c0 	ands.w	r4, r4, #192	; 0xc0
   10316:	d001      	beq.n	1031c <stop+0x2a>
   10318:	42a2      	cmp	r2, r4
   1031a:	d110      	bne.n	1033e <stop+0x4c>
		*flags = CLOCK_CONTROL_STATUS_OFF;
   1031c:	fb05 0001 	mla	r0, r5, r1, r0
   10320:	2201      	movs	r2, #1
   10322:	6402      	str	r2, [r0, #64]	; 0x40
	int err = 0;
   10324:	2000      	movs	r0, #0
	__asm__ volatile(
   10326:	f386 8811 	msr	BASEPRI, r6
   1032a:	f3bf 8f6f 	isb	sy
	if (err < 0) {
   1032e:	b928      	cbnz	r0, 1033c <stop+0x4a>
	get_sub_config(dev, type)->stop();
   10330:	685b      	ldr	r3, [r3, #4]
   10332:	eb03 01c1 	add.w	r1, r3, r1, lsl #3
   10336:	684b      	ldr	r3, [r1, #4]
   10338:	4798      	blx	r3
	return 0;
   1033a:	2000      	movs	r0, #0
}
   1033c:	bd70      	pop	{r4, r5, r6, pc}
		err = -EPERM;
   1033e:	f04f 30ff 	mov.w	r0, #4294967295
   10342:	e7f0      	b.n	10326 <stop+0x34>

00010344 <api_stop>:
	return stop(dev, subsys, CTX_API);
   10344:	2280      	movs	r2, #128	; 0x80
   10346:	f7ff bfd4 	b.w	102f2 <stop>

0001034a <async_start>:
{
   1034a:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
   1034c:	9f06      	ldr	r7, [sp, #24]
	struct nrf_clock_control_data *data = dev->data;
   1034e:	6904      	ldr	r4, [r0, #16]
{
   10350:	4605      	mov	r5, r0
   10352:	b2c9      	uxtb	r1, r1
	__asm__ volatile(
   10354:	f04f 0020 	mov.w	r0, #32
   10358:	f3ef 8c11 	mrs	ip, BASEPRI
   1035c:	f380 8812 	msr	BASEPRI_MAX, r0
   10360:	f3bf 8f6f 	isb	sy
	uint32_t current_ctx = GET_CTX(*flags);
   10364:	260c      	movs	r6, #12
   10366:	fb06 4601 	mla	r6, r6, r1, r4
   1036a:	6c30      	ldr	r0, [r6, #64]	; 0x40
	if ((*flags & (STATUS_MASK)) == CLOCK_CONTROL_STATUS_OFF) {
   1036c:	f000 0e07 	and.w	lr, r0, #7
   10370:	f1be 0f01 	cmp.w	lr, #1
   10374:	d111      	bne.n	1039a <async_start+0x50>
		*flags = CLOCK_CONTROL_STATUS_STARTING | ctx;
   10376:	6437      	str	r7, [r6, #64]	; 0x40
	int err = 0;
   10378:	2600      	movs	r6, #0
	__asm__ volatile(
   1037a:	f38c 8811 	msr	BASEPRI, ip
   1037e:	f3bf 8f6f 	isb	sy
	if (err < 0) {
   10382:	b946      	cbnz	r6, 10396 <async_start+0x4c>
	subdata->cb = cb;
   10384:	200c      	movs	r0, #12
   10386:	fb00 4401 	mla	r4, r0, r1, r4
	subdata->user_data = user_data;
   1038a:	e9c4 230e 	strd	r2, r3, [r4, #56]	; 0x38
	 get_sub_config(dev, type)->start();
   1038e:	686b      	ldr	r3, [r5, #4]
   10390:	f853 3031 	ldr.w	r3, [r3, r1, lsl #3]
   10394:	4798      	blx	r3
}
   10396:	4630      	mov	r0, r6
   10398:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	uint32_t current_ctx = GET_CTX(*flags);
   1039a:	f000 00c0 	and.w	r0, r0, #192	; 0xc0
		err = -EALREADY;
   1039e:	4287      	cmp	r7, r0
   103a0:	bf14      	ite	ne
   103a2:	f04f 36ff 	movne.w	r6, #4294967295
   103a6:	f06f 0677 	mvneq.w	r6, #119	; 0x77
   103aa:	e7e6      	b.n	1037a <async_start+0x30>

000103ac <api_start>:
{
   103ac:	b513      	push	{r0, r1, r4, lr}
	return async_start(dev, subsys, cb, user_data, CTX_API);
   103ae:	2480      	movs	r4, #128	; 0x80
   103b0:	9400      	str	r4, [sp, #0]
   103b2:	f7ff ffca 	bl	1034a <async_start>
}
   103b6:	b002      	add	sp, #8
   103b8:	bd10      	pop	{r4, pc}

000103ba <onoff_started_callback>:
	return &data->mgr[type];
   103ba:	6900      	ldr	r0, [r0, #16]
{
   103bc:	b410      	push	{r4}
	return &data->mgr[type];
   103be:	b2cb      	uxtb	r3, r1
	notify(mgr, 0);
   103c0:	241c      	movs	r4, #28
   103c2:	fb03 0004 	mla	r0, r3, r4, r0
   103c6:	2100      	movs	r1, #0
}
   103c8:	bc10      	pop	{r4}
	notify(mgr, 0);
   103ca:	4710      	bx	r2

000103cc <lfclk_stop>:
    nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK);
   103cc:	2000      	movs	r0, #0
   103ce:	f000 b9b0 	b.w	10732 <nrfx_clock_stop>

000103d2 <blocking_start_callback>:
{
   103d2:	4610      	mov	r0, r2
		(void) arch_syscall_invoke1(parm0.x, K_SYSCALL_K_SEM_GIVE);
		return;
	}
#endif
	compiler_barrier();
	z_impl_k_sem_give(sem);
   103d4:	f7ff b936 	b.w	f644 <z_impl_k_sem_give>

000103d8 <gpio_nrfx_port_get_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
   103d8:	6843      	ldr	r3, [r0, #4]
   103da:	685b      	ldr	r3, [r3, #4]
    return p_reg->IN;
   103dc:	f8d3 3510 	ldr.w	r3, [r3, #1296]	; 0x510
	*value = nrf_gpio_port_in_read(reg);
   103e0:	600b      	str	r3, [r1, #0]
}
   103e2:	2000      	movs	r0, #0
   103e4:	4770      	bx	lr

000103e6 <gpio_nrfx_port_set_masked_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
   103e6:	6843      	ldr	r3, [r0, #4]
   103e8:	685b      	ldr	r3, [r3, #4]
    return p_reg->OUT;
   103ea:	f8d3 0504 	ldr.w	r0, [r3, #1284]	; 0x504
	nrf_gpio_port_out_write(reg, value_tmp | (mask & value));
   103ee:	4042      	eors	r2, r0
   103f0:	400a      	ands	r2, r1
   103f2:	4042      	eors	r2, r0
    p_reg->OUT = value;
   103f4:	f8c3 2504 	str.w	r2, [r3, #1284]	; 0x504
}
   103f8:	2000      	movs	r0, #0
   103fa:	4770      	bx	lr

000103fc <gpio_nrfx_port_set_bits_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
   103fc:	6843      	ldr	r3, [r0, #4]
   103fe:	685b      	ldr	r3, [r3, #4]
}
   10400:	2000      	movs	r0, #0
    p_reg->OUTSET = set_mask;
   10402:	f8c3 1508 	str.w	r1, [r3, #1288]	; 0x508
   10406:	4770      	bx	lr

00010408 <gpio_nrfx_port_clear_bits_raw>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
   10408:	6843      	ldr	r3, [r0, #4]
   1040a:	685b      	ldr	r3, [r3, #4]
}
   1040c:	2000      	movs	r0, #0
    p_reg->OUTCLR = clr_mask;
   1040e:	f8c3 150c 	str.w	r1, [r3, #1292]	; 0x50c
   10412:	4770      	bx	lr

00010414 <gpio_nrfx_port_toggle_bits>:
	NRF_GPIO_Type *reg = get_port_cfg(port)->port;
   10414:	6843      	ldr	r3, [r0, #4]
   10416:	685a      	ldr	r2, [r3, #4]
    return p_reg->OUT;
   10418:	f8d2 3504 	ldr.w	r3, [r2, #1284]	; 0x504
	nrf_gpio_port_out_write(reg, value ^ mask);
   1041c:	404b      	eors	r3, r1
    p_reg->OUT = value;
   1041e:	f8c2 3504 	str.w	r3, [r2, #1284]	; 0x504
}
   10422:	2000      	movs	r0, #0
   10424:	4770      	bx	lr

00010426 <gpio_nrfx_manage_callback>:
	return port->data;
   10426:	6903      	ldr	r3, [r0, #16]
	return list->head;
   10428:	6858      	ldr	r0, [r3, #4]
{
   1042a:	b530      	push	{r4, r5, lr}
	if (!sys_slist_is_empty(callbacks)) {
   1042c:	b158      	cbz	r0, 10446 <gpio_nrfx_manage_callback+0x20>
 */
static inline bool sys_slist_find_and_remove(sys_slist_t *list,
					     sys_snode_t *node);

/** @} */
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
   1042e:	2400      	movs	r4, #0
   10430:	4281      	cmp	r1, r0
   10432:	d112      	bne.n	1045a <gpio_nrfx_manage_callback+0x34>
	return node->next;
   10434:	6808      	ldr	r0, [r1, #0]
	return list->tail;
   10436:	689d      	ldr	r5, [r3, #8]
Z_GENLIST_REMOVE(slist, snode)
   10438:	b954      	cbnz	r4, 10450 <gpio_nrfx_manage_callback+0x2a>
   1043a:	428d      	cmp	r5, r1
	list->head = node;
   1043c:	6058      	str	r0, [r3, #4]
Z_GENLIST_REMOVE(slist, snode)
   1043e:	d100      	bne.n	10442 <gpio_nrfx_manage_callback+0x1c>
	list->tail = node;
   10440:	6098      	str	r0, [r3, #8]
	parent->next = child;
   10442:	2000      	movs	r0, #0
   10444:	6008      	str	r0, [r1, #0]
	if (set) {
   10446:	b96a      	cbnz	r2, 10464 <gpio_nrfx_manage_callback+0x3e>
	return 0;
   10448:	2000      	movs	r0, #0
}
   1044a:	bd30      	pop	{r4, r5, pc}
   1044c:	4628      	mov	r0, r5
   1044e:	e7ef      	b.n	10430 <gpio_nrfx_manage_callback+0xa>
Z_GENLIST_REMOVE(slist, snode)
   10450:	428d      	cmp	r5, r1
	parent->next = child;
   10452:	6020      	str	r0, [r4, #0]
	list->tail = node;
   10454:	bf08      	it	eq
   10456:	609c      	streq	r4, [r3, #8]
}
   10458:	e7f3      	b.n	10442 <gpio_nrfx_manage_callback+0x1c>
	return node->next;
   1045a:	6805      	ldr	r5, [r0, #0]
Z_GENLIST_FIND_AND_REMOVE(slist, snode)
   1045c:	4604      	mov	r4, r0
   1045e:	2d00      	cmp	r5, #0
   10460:	d1f4      	bne.n	1044c <gpio_nrfx_manage_callback+0x26>
			if (!set) {
   10462:	b13a      	cbz	r2, 10474 <gpio_nrfx_manage_callback+0x4e>
Z_GENLIST_PREPEND(slist, snode)
   10464:	6898      	ldr	r0, [r3, #8]
	parent->next = child;
   10466:	685a      	ldr	r2, [r3, #4]
   10468:	600a      	str	r2, [r1, #0]
	list->head = node;
   1046a:	6059      	str	r1, [r3, #4]
Z_GENLIST_PREPEND(slist, snode)
   1046c:	2800      	cmp	r0, #0
   1046e:	d1eb      	bne.n	10448 <gpio_nrfx_manage_callback+0x22>
	list->tail = node;
   10470:	6099      	str	r1, [r3, #8]
}
   10472:	e7ea      	b.n	1044a <gpio_nrfx_manage_callback+0x24>
				return -EINVAL;
   10474:	f06f 0015 	mvn.w	r0, #21
	return gpio_manage_callback(&get_port_data(port)->callbacks,
   10478:	e7e7      	b.n	1044a <gpio_nrfx_manage_callback+0x24>

0001047a <uarte_nrfx_config_get>:
	*cfg = data->uart_config;
   1047a:	6902      	ldr	r2, [r0, #16]
{
   1047c:	460b      	mov	r3, r1
	*cfg = data->uart_config;
   1047e:	e9d2 0101 	ldrd	r0, r1, [r2, #4]
   10482:	e883 0003 	stmia.w	r3, {r0, r1}
}
   10486:	2000      	movs	r0, #0
   10488:	4770      	bx	lr

0001048a <uarte_nrfx_err_check>:
	return config->uarte_regs;
   1048a:	6843      	ldr	r3, [r0, #4]
   1048c:	681b      	ldr	r3, [r3, #0]
    uint32_t errsrc_mask = p_reg->ERRORSRC;
   1048e:	f8d3 0480 	ldr.w	r0, [r3, #1152]	; 0x480
    p_reg->ERRORSRC = errsrc_mask;
   10492:	f8c3 0480 	str.w	r0, [r3, #1152]	; 0x480
}
   10496:	4770      	bx	lr

00010498 <uarte_nrfx_poll_in>:
	return config->uarte_regs;
   10498:	6843      	ldr	r3, [r0, #4]
	const struct uarte_nrfx_data *data = dev->data;
   1049a:	6902      	ldr	r2, [r0, #16]
	return config->uarte_regs;
   1049c:	681b      	ldr	r3, [r3, #0]
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
   1049e:	f8d3 0110 	ldr.w	r0, [r3, #272]	; 0x110
	if (!nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDRX)) {
   104a2:	b148      	cbz	r0, 104b8 <uarte_nrfx_poll_in+0x20>
	*c = data->rx_data;
   104a4:	7c52      	ldrb	r2, [r2, #17]
   104a6:	700a      	strb	r2, [r1, #0]
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
   104a8:	2000      	movs	r0, #0
   104aa:	f8c3 0110 	str.w	r0, [r3, #272]	; 0x110
   104ae:	f8d3 2110 	ldr.w	r2, [r3, #272]	; 0x110
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
   104b2:	2201      	movs	r2, #1
   104b4:	601a      	str	r2, [r3, #0]
	return 0;
   104b6:	4770      	bx	lr
		return -1;
   104b8:	f04f 30ff 	mov.w	r0, #4294967295
}
   104bc:	4770      	bx	lr

000104be <is_tx_ready.isra.0>:
	return config->uarte_regs;
   104be:	6802      	ldr	r2, [r0, #0]
static bool is_tx_ready(const struct device *dev)
   104c0:	4603      	mov	r3, r0
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
   104c2:	f8d2 0158 	ldr.w	r0, [r2, #344]	; 0x158
	return nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED) ||
   104c6:	b940      	cbnz	r0, 104da <is_tx_ready.isra.0+0x1c>
	bool ppi_endtx = config->flags & UARTE_CFG_FLAG_PPI_ENDTX;
   104c8:	685b      	ldr	r3, [r3, #4]
	return nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED) ||
   104ca:	079b      	lsls	r3, r3, #30
   104cc:	d406      	bmi.n	104dc <is_tx_ready.isra.0+0x1e>
   104ce:	f8d2 0120 	ldr.w	r0, [r2, #288]	; 0x120
   104d2:	3800      	subs	r0, #0
   104d4:	bf18      	it	ne
   104d6:	2001      	movne	r0, #1
   104d8:	4770      	bx	lr
   104da:	2001      	movs	r0, #1
}
   104dc:	4770      	bx	lr

000104de <uarte_nrfx_isr_int>:
	const struct uarte_nrfx_config *config = dev->config;
   104de:	6842      	ldr	r2, [r0, #4]
	return config->uarte_regs;
   104e0:	6813      	ldr	r3, [r2, #0]
    return p_reg->INTENSET & mask;
   104e2:	f8d3 1304 	ldr.w	r1, [r3, #772]	; 0x304
	if (nrf_uarte_int_enable_check(uarte, NRF_UARTE_INT_ENDTX_MASK) &&
   104e6:	05c9      	lsls	r1, r1, #23
   104e8:	d518      	bpl.n	1051c <uarte_nrfx_isr_int+0x3e>
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
   104ea:	f8d3 1120 	ldr.w	r1, [r3, #288]	; 0x120
   104ee:	b1a9      	cbz	r1, 1051c <uarte_nrfx_isr_int+0x3e>
	__asm__ volatile(
   104f0:	f04f 0020 	mov.w	r0, #32
   104f4:	f3ef 8111 	mrs	r1, BASEPRI
   104f8:	f380 8812 	msr	BASEPRI_MAX, r0
   104fc:	f3bf 8f6f 	isb	sy
   10500:	f8d3 0120 	ldr.w	r0, [r3, #288]	; 0x120
	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDTX)) {
   10504:	b130      	cbz	r0, 10514 <uarte_nrfx_isr_int+0x36>
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
   10506:	2000      	movs	r0, #0
   10508:	f8c3 0120 	str.w	r0, [r3, #288]	; 0x120
   1050c:	f8d3 0120 	ldr.w	r0, [r3, #288]	; 0x120
    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
   10510:	2001      	movs	r0, #1
   10512:	60d8      	str	r0, [r3, #12]
	__asm__ volatile(
   10514:	f381 8811 	msr	BASEPRI, r1
   10518:	f3bf 8f6f 	isb	sy
	if (config->flags & UARTE_CFG_FLAG_LOW_POWER) {
   1051c:	6852      	ldr	r2, [r2, #4]
   1051e:	06d2      	lsls	r2, r2, #27
   10520:	d515      	bpl.n	1054e <uarte_nrfx_isr_int+0x70>
	__asm__ volatile(
   10522:	f04f 0120 	mov.w	r1, #32
   10526:	f3ef 8211 	mrs	r2, BASEPRI
   1052a:	f381 8812 	msr	BASEPRI_MAX, r1
   1052e:	f3bf 8f6f 	isb	sy
    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
   10532:	f8d3 1158 	ldr.w	r1, [r3, #344]	; 0x158
		if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_TXSTOPPED)) {
   10536:	b111      	cbz	r1, 1053e <uarte_nrfx_isr_int+0x60>
    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
   10538:	2100      	movs	r1, #0
   1053a:	f8c3 1500 	str.w	r1, [r3, #1280]	; 0x500
    p_reg->INTENCLR = mask;
   1053e:	f44f 0180 	mov.w	r1, #4194304	; 0x400000
   10542:	f8c3 1308 	str.w	r1, [r3, #776]	; 0x308
	__asm__ volatile(
   10546:	f382 8811 	msr	BASEPRI, r2
   1054a:	f3bf 8f6f 	isb	sy
}
   1054e:	4770      	bx	lr

00010550 <sys_clock_idle_exit>:
{
}

void __weak sys_clock_idle_exit(void)
{
}
   10550:	4770      	bx	lr

00010552 <pinctrl_lookup_state>:

#include <drivers/pinctrl.h>

int pinctrl_lookup_state(const struct pinctrl_dev_config *config, uint8_t id,
			 const struct pinctrl_state **state)
{
   10552:	b530      	push	{r4, r5, lr}
	*state = &config->states[0];
   10554:	6843      	ldr	r3, [r0, #4]
   10556:	6013      	str	r3, [r2, #0]
	while (*state <= &config->states[config->state_cnt - 1U]) {
   10558:	7a03      	ldrb	r3, [r0, #8]
   1055a:	f103 5300 	add.w	r3, r3, #536870912	; 0x20000000
   1055e:	3b01      	subs	r3, #1
   10560:	00db      	lsls	r3, r3, #3
   10562:	6845      	ldr	r5, [r0, #4]
   10564:	6814      	ldr	r4, [r2, #0]
   10566:	441d      	add	r5, r3
   10568:	42ac      	cmp	r4, r5
   1056a:	d902      	bls.n	10572 <pinctrl_lookup_state+0x20>
		}

		(*state)++;
	}

	return -ENOENT;
   1056c:	f06f 0001 	mvn.w	r0, #1
}
   10570:	bd30      	pop	{r4, r5, pc}
		if (id == (*state)->id) {
   10572:	7965      	ldrb	r5, [r4, #5]
   10574:	428d      	cmp	r5, r1
   10576:	d002      	beq.n	1057e <pinctrl_lookup_state+0x2c>
		(*state)++;
   10578:	3408      	adds	r4, #8
   1057a:	6014      	str	r4, [r2, #0]
   1057c:	e7f1      	b.n	10562 <pinctrl_lookup_state+0x10>
			return 0;
   1057e:	2000      	movs	r0, #0
   10580:	e7f6      	b.n	10570 <pinctrl_lookup_state+0x1e>

00010582 <nrf_gpio_pin_write>:
    *p_pin = pin_number & 0x1F;
   10582:	f000 031f 	and.w	r3, r0, #31
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
   10586:	2001      	movs	r0, #1
   10588:	4098      	lsls	r0, r3
   1058a:	f04f 43a0 	mov.w	r3, #1342177280	; 0x50000000
    if (value == 0)
   1058e:	b911      	cbnz	r1, 10596 <nrf_gpio_pin_write+0x14>
    p_reg->OUTCLR = clr_mask;
   10590:	f8c3 050c 	str.w	r0, [r3, #1292]	; 0x50c
}
   10594:	4770      	bx	lr
    p_reg->OUTSET = set_mask;
   10596:	f8c3 0508 	str.w	r0, [r3, #1288]	; 0x508
}
   1059a:	4770      	bx	lr

0001059c <nrf_pin_configure>:
__unused static void nrf_pin_configure(pinctrl_soc_pin_t pin,
				       nrf_gpio_pin_dir_t dir,
				       nrf_gpio_pin_input_t input)
{
	/* force input direction and disconnected buffer for low power */
	if (NRF_GET_LP(pin) == NRF_LP_ENABLE) {
   1059c:	f400 5380 	and.w	r3, r0, #4096	; 0x1000
		dir = NRF_GPIO_PIN_DIR_INPUT;
		input = NRF_GPIO_PIN_INPUT_DISCONNECT;
   105a0:	2b00      	cmp	r3, #0
{
   105a2:	b510      	push	{r4, lr}
    *p_pin = pin_number & 0x1F;
   105a4:	f000 031f 	and.w	r3, r0, #31
		input = NRF_GPIO_PIN_INPUT_DISCONNECT;
   105a8:	bf08      	it	eq
   105aa:	4614      	moveq	r4, r2
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
   105ac:	f3c0 1281 	ubfx	r2, r0, #6, #2
           ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) |
   105b0:	f400 6070 	and.w	r0, r0, #3840	; 0xf00
   105b4:	bf18      	it	ne
   105b6:	2100      	movne	r1, #0
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
   105b8:	ea40 0282 	orr.w	r2, r0, r2, lsl #2
   105bc:	ea42 0201 	orr.w	r2, r2, r1
   105c0:	bf18      	it	ne
   105c2:	2401      	movne	r4, #1
    reg->PIN_CNF[pin_number] = cnf;
   105c4:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
   105c8:	f04f 41a0 	mov.w	r1, #1342177280	; 0x50000000
           ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)   |
   105cc:	ea42 0244 	orr.w	r2, r2, r4, lsl #1
    reg->PIN_CNF[pin_number] = cnf;
   105d0:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
	}

	nrf_gpio_cfg(NRF_GET_PIN(pin), dir, input, NRF_GET_PULL(pin),
		     NRF_GET_DRIVE(pin), NRF_GPIO_PIN_NOSENSE);
}
   105d4:	bd10      	pop	{r4, pc}

000105d6 <pinctrl_configure_pins>:

int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
			   uintptr_t reg)
{
   105d6:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
   105da:	4614      	mov	r4, r2
   105dc:	4680      	mov	r8, r0
   105de:	eb00 0781 	add.w	r7, r0, r1, lsl #2
			break;
		case NRF_FUN_PWM_OUT3:
			NRF_PSEL_PWM(reg, OUT[3]) = NRF_GET_PIN(pins[i]);
			nrf_gpio_pin_write(NRF_GET_PIN(pins[i]),
					   NRF_GET_INVERT(pins[i]));
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
   105e2:	2501      	movs	r5, #1
    p_reg->OUTCLR = clr_mask;
   105e4:	f04f 46a0 	mov.w	r6, #1342177280	; 0x50000000
	for (uint8_t i = 0U; i < pin_cnt; i++) {
   105e8:	45b8      	cmp	r8, r7
   105ea:	d102      	bne.n	105f2 <pinctrl_configure_pins+0x1c>
		default:
			return -ENOTSUP;
		}
	}

	return 0;
   105ec:	2000      	movs	r0, #0
}
   105ee:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
		switch (NRF_GET_FUN(pins[i])) {
   105f2:	f8d8 3000 	ldr.w	r3, [r8]
   105f6:	0c1a      	lsrs	r2, r3, #16
   105f8:	2a19      	cmp	r2, #25
   105fa:	d875      	bhi.n	106e8 <pinctrl_configure_pins+0x112>
   105fc:	e8df f002 	tbb	[pc, r2]
   10600:	49221b0d 	.word	0x49221b0d
   10604:	74493c27 	.word	0x74493c27
   10608:	4e747474 	.word	0x4e747474
   1060c:	74747453 	.word	0x74747453
   10610:	74747474 	.word	0x74747474
   10614:	65587474 	.word	0x65587474
   10618:	6f6a      	.short	0x6f6a
			NRF_PSEL_UART(reg, TXD) = NRF_GET_PIN(pins[i]);
   1061a:	f003 033f 	and.w	r3, r3, #63	; 0x3f
   1061e:	f8c4 350c 	str.w	r3, [r4, #1292]	; 0x50c
    *p_pin = pin_number & 0x1F;
   10622:	f8d8 3000 	ldr.w	r3, [r8]
   10626:	f003 031f 	and.w	r3, r3, #31
    nrf_gpio_port_out_set(reg, 1UL << pin_number);
   1062a:	fa05 f303 	lsl.w	r3, r5, r3
    p_reg->OUTSET = set_mask;
   1062e:	f8c6 3508 	str.w	r3, [r6, #1288]	; 0x508
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
   10632:	2201      	movs	r2, #1
   10634:	e004      	b.n	10640 <pinctrl_configure_pins+0x6a>
			NRF_PSEL_UART(reg, RXD) = NRF_GET_PIN(pins[i]);
   10636:	f003 033f 	and.w	r3, r3, #63	; 0x3f
   1063a:	f8c4 3514 	str.w	r3, [r4, #1300]	; 0x514
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
   1063e:	2200      	movs	r2, #0
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
   10640:	4611      	mov	r1, r2
   10642:	e012      	b.n	1066a <pinctrl_configure_pins+0x94>
			NRF_PSEL_UART(reg, RTS) = NRF_GET_PIN(pins[i]);
   10644:	f003 033f 	and.w	r3, r3, #63	; 0x3f
   10648:	f8c4 3508 	str.w	r3, [r4, #1288]	; 0x508
   1064c:	e7e9      	b.n	10622 <pinctrl_configure_pins+0x4c>
			NRF_PSEL_SPIM(reg, SCK) = NRF_GET_PIN(pins[i]);
   1064e:	f003 033f 	and.w	r3, r3, #63	; 0x3f
   10652:	f8c4 3508 	str.w	r3, [r4, #1288]	; 0x508
    *p_pin = pin_number & 0x1F;
   10656:	f8d8 3000 	ldr.w	r3, [r8]
   1065a:	f003 031f 	and.w	r3, r3, #31
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
   1065e:	fa05 f303 	lsl.w	r3, r5, r3
    p_reg->OUTCLR = clr_mask;
   10662:	f8c6 350c 	str.w	r3, [r6, #1292]	; 0x50c
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
   10666:	2200      	movs	r2, #0
   10668:	2101      	movs	r1, #1
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
   1066a:	f8d8 0000 	ldr.w	r0, [r8]
   1066e:	f7ff ff95 	bl	1059c <nrf_pin_configure>
	for (uint8_t i = 0U; i < pin_cnt; i++) {
   10672:	f108 0804 	add.w	r8, r8, #4
   10676:	e7b7      	b.n	105e8 <pinctrl_configure_pins+0x12>
			NRF_PSEL_SPIM(reg, MOSI) = NRF_GET_PIN(pins[i]);
   10678:	f003 033f 	and.w	r3, r3, #63	; 0x3f
   1067c:	f8c4 350c 	str.w	r3, [r4, #1292]	; 0x50c
    *p_pin = pin_number & 0x1F;
   10680:	f8d8 3000 	ldr.w	r3, [r8]
   10684:	f003 031f 	and.w	r3, r3, #31
    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
   10688:	fa05 f303 	lsl.w	r3, r5, r3
    p_reg->OUTCLR = clr_mask;
   1068c:	f8c6 350c 	str.w	r3, [r6, #1292]	; 0x50c
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
   10690:	e7cf      	b.n	10632 <pinctrl_configure_pins+0x5c>
			NRF_PSEL_SPIM(reg, MISO) = NRF_GET_PIN(pins[i]);
   10692:	f003 033f 	and.w	r3, r3, #63	; 0x3f
   10696:	f8c4 3510 	str.w	r3, [r4, #1296]	; 0x510
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
   1069a:	e7d0      	b.n	1063e <pinctrl_configure_pins+0x68>
			NRF_PSEL_TWIM(reg, SCL) = NRF_GET_PIN(pins[i]);
   1069c:	f003 033f 	and.w	r3, r3, #63	; 0x3f
   106a0:	f8c4 3508 	str.w	r3, [r4, #1288]	; 0x508
			nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
   106a4:	e7cb      	b.n	1063e <pinctrl_configure_pins+0x68>
			NRF_PSEL_TWIM(reg, SDA) = NRF_GET_PIN(pins[i]);
   106a6:	f003 033f 	and.w	r3, r3, #63	; 0x3f
   106aa:	f8c4 350c 	str.w	r3, [r4, #1292]	; 0x50c
   106ae:	e7c6      	b.n	1063e <pinctrl_configure_pins+0x68>
			NRF_PSEL_PWM(reg, OUT[0]) = NRF_GET_PIN(pins[i]);
   106b0:	f003 033f 	and.w	r3, r3, #63	; 0x3f
   106b4:	f8c4 3560 	str.w	r3, [r4, #1376]	; 0x560
			nrf_gpio_pin_write(NRF_GET_PIN(pins[i]),
   106b8:	f8d8 0000 	ldr.w	r0, [r8]
   106bc:	f3c0 3140 	ubfx	r1, r0, #13, #1
   106c0:	f000 003f 	and.w	r0, r0, #63	; 0x3f
   106c4:	f7ff ff5d 	bl	10582 <nrf_gpio_pin_write>
   106c8:	e7b3      	b.n	10632 <pinctrl_configure_pins+0x5c>
			NRF_PSEL_PWM(reg, OUT[1]) = NRF_GET_PIN(pins[i]);
   106ca:	f003 033f 	and.w	r3, r3, #63	; 0x3f
   106ce:	f8c4 3564 	str.w	r3, [r4, #1380]	; 0x564
			nrf_gpio_pin_write(NRF_GET_PIN(pins[i]),
   106d2:	e7f1      	b.n	106b8 <pinctrl_configure_pins+0xe2>
			NRF_PSEL_PWM(reg, OUT[2]) = NRF_GET_PIN(pins[i]);
   106d4:	f003 033f 	and.w	r3, r3, #63	; 0x3f
   106d8:	f8c4 3568 	str.w	r3, [r4, #1384]	; 0x568
			nrf_gpio_pin_write(NRF_GET_PIN(pins[i]),
   106dc:	e7ec      	b.n	106b8 <pinctrl_configure_pins+0xe2>
			NRF_PSEL_PWM(reg, OUT[3]) = NRF_GET_PIN(pins[i]);
   106de:	f003 033f 	and.w	r3, r3, #63	; 0x3f
   106e2:	f8c4 356c 	str.w	r3, [r4, #1388]	; 0x56c
   106e6:	e7e7      	b.n	106b8 <pinctrl_configure_pins+0xe2>
		switch (NRF_GET_FUN(pins[i])) {
   106e8:	f06f 0085 	mvn.w	r0, #133	; 0x85
   106ec:	e77f      	b.n	105ee <pinctrl_configure_pins+0x18>

000106ee <k_sys_fatal_error_handler>:

extern void sys_arch_reboot(int type);

void k_sys_fatal_error_handler(unsigned int reason,
			       const z_arch_esf_t *esf)
{
   106ee:	b508      	push	{r3, lr}
	z_spm_ns_fatal_error_handler();
#endif

	if (IS_ENABLED(CONFIG_RESET_ON_FATAL_ERROR)) {
		LOG_ERR("Resetting system");
		sys_arch_reboot(0);
   106f0:	2000      	movs	r0, #0
   106f2:	f7fd f937 	bl	d964 <sys_arch_reboot>

000106f6 <nrf52_errata_108>:
            if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF)
   106f6:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
   106fa:	f8d3 0130 	ldr.w	r0, [r3, #304]	; 0x130
   106fe:	1c42      	adds	r2, r0, #1
                var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul);
   10700:	bf04      	itt	eq
   10702:	f04f 4370 	moveq.w	r3, #4026531840	; 0xf0000000
   10706:	f893 0fe0 	ldrbeq.w	r0, [r3, #4064]	; 0xfe0
}
   1070a:	1f83      	subs	r3, r0, #6
   1070c:	4258      	negs	r0, r3
   1070e:	4158      	adcs	r0, r3
   10710:	4770      	bx	lr

00010712 <nrfx_isr>:
#include <nrfx.h>
#include <kernel.h>

void nrfx_isr(const void *irq_handler)
{
	((nrfx_irq_handler_t)irq_handler)();
   10712:	4700      	bx	r0

00010714 <nrfx_busy_wait>:
	z_impl_k_busy_wait(usec_to_wait);
   10714:	f000 b941 	b.w	1099a <z_impl_k_busy_wait>

00010718 <nrfx_clock_enable>:
{
   10718:	b508      	push	{r3, lr}
    priority = NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY;
#else
    #error "This code is not supposed to be compiled when neither POWER nor CLOCK is enabled."
#endif

    if (!NRFX_IRQ_IS_ENABLED(nrfx_get_irq_number(NRF_CLOCK)))
   1071a:	2000      	movs	r0, #0
   1071c:	f7fc fd9e 	bl	d25c <arch_irq_is_enabled>
   10720:	b908      	cbnz	r0, 10726 <nrfx_clock_enable+0xe>
    {
        NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_CLOCK), priority);
        NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_CLOCK));
   10722:	f7fc fd8b 	bl	d23c <arch_irq_enable>
    p_reg->LFCLKSRC = (uint32_t)(source);
   10726:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
   1072a:	2200      	movs	r2, #0
   1072c:	f8c3 2518 	str.w	r2, [r3, #1304]	; 0x518
}
   10730:	bd08      	pop	{r3, pc}

00010732 <nrfx_clock_stop>:
    clock_stop(domain);
   10732:	f7fe b9a9 	b.w	ea88 <clock_stop>

00010736 <nrf_gpio_cfg_sense_set>:
    *p_pin = pin_number & 0x1F;
   10736:	f000 001f 	and.w	r0, r0, #31
   1073a:	0080      	lsls	r0, r0, #2
   1073c:	f100 40a0 	add.w	r0, r0, #1342177280	; 0x50000000
    uint32_t cnf = reg->PIN_CNF[pin_number];
   10740:	f8d0 3700 	ldr.w	r3, [r0, #1792]	; 0x700
    cnf &= ~to_update;
   10744:	f423 3340 	bic.w	r3, r3, #196608	; 0x30000
    cnf |= ((uint32_t)(p_dir   ? *p_dir   : 0) << GPIO_PIN_CNF_DIR_Pos)   |
   10748:	ea43 4301 	orr.w	r3, r3, r1, lsl #16
    reg->PIN_CNF[pin_number] = cnf;
   1074c:	f8c0 3700 	str.w	r3, [r0, #1792]	; 0x700
}
   10750:	4770      	bx	lr

00010752 <SEGGER_RTT_Init>:
*    Initializes the RTT Control Block.
*    Should be used in RAM targets, at start of the application.
*
*/
void SEGGER_RTT_Init (void) {
  _DoInit();
   10752:	f7fe bdaf 	b.w	f2b4 <_DoInit>

00010756 <rtt_init>:
 */

K_MUTEX_DEFINE(rtt_term_mutex);

static int rtt_init(const struct device *unused)
{
   10756:	b508      	push	{r3, lr}
	ARG_UNUSED(unused);

	SEGGER_RTT_Init();
   10758:	f7ff fffb 	bl	10752 <SEGGER_RTT_Init>

	return 0;
}
   1075c:	2000      	movs	r0, #0
   1075e:	bd08      	pop	{r3, pc}

00010760 <z_device_state_init>:
}
   10760:	4770      	bx	lr

00010762 <z_device_is_ready>:
{
	/*
	 * if an invalid device pointer is passed as argument, this call
	 * reports the `device` as not ready for usage.
	 */
	if (dev == NULL) {
   10762:	b138      	cbz	r0, 10774 <z_device_is_ready+0x12>
		return false;
	}

	return dev->state->initialized && (dev->state->init_res == 0U);
   10764:	68c3      	ldr	r3, [r0, #12]
   10766:	8818      	ldrh	r0, [r3, #0]
   10768:	f3c0 0008 	ubfx	r0, r0, #0, #9
   1076c:	f5a0 7380 	sub.w	r3, r0, #256	; 0x100
   10770:	4258      	negs	r0, r3
   10772:	4158      	adcs	r0, r3
}
   10774:	4770      	bx	lr

00010776 <z_fatal_error>:
	return 0;
#endif
}

void z_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
{
   10776:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
   10778:	4605      	mov	r5, r0
   1077a:	460e      	mov	r6, r1
	__asm__ volatile(
   1077c:	f04f 0320 	mov.w	r3, #32
   10780:	f3ef 8711 	mrs	r7, BASEPRI
   10784:	f383 8812 	msr	BASEPRI_MAX, r3
   10788:	f3bf 8f6f 	isb	sy
	return z_impl_z_current_get();
   1078c:	f7ff fa4c 	bl	fc28 <z_impl_z_current_get>
	LOG_ERR("Current thread: %p (%s)", thread,
		log_strdup(thread_name_get(thread)));

	coredump(reason, esf, thread);

	k_sys_fatal_error_handler(reason, esf);
   10790:	4631      	mov	r1, r6
   10792:	4604      	mov	r4, r0
   10794:	4628      	mov	r0, r5
   10796:	f7ff ffaa 	bl	106ee <k_sys_fatal_error_handler>
	__asm__ volatile(
   1079a:	f387 8811 	msr	BASEPRI, r7
   1079e:	f3bf 8f6f 	isb	sy
	z_impl_k_thread_abort(thread);
   107a2:	4620      	mov	r0, r4
	arch_irq_unlock(key);

	if (IS_ENABLED(CONFIG_MULTITHREADING)) {
		k_thread_abort(thread);
	}
}
   107a4:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
   107a8:	f7fc bfe2 	b.w	d770 <z_impl_k_thread_abort>

000107ac <z_early_memset>:
	(void) memset(dst, c, n);
   107ac:	f7ff bd67 	b.w	1027e <memset>

000107b0 <z_early_memcpy>:
	(void) memcpy(dst, src, n);
   107b0:	f7ff bd5a 	b.w	10268 <memcpy>

000107b4 <k_is_in_isr>:
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
   107b4:	f3ef 8005 	mrs	r0, IPSR
}
   107b8:	3800      	subs	r0, #0
   107ba:	bf18      	it	ne
   107bc:	2001      	movne	r0, #1
   107be:	4770      	bx	lr

000107c0 <z_pm_save_idle_exit>:
{
   107c0:	b508      	push	{r3, lr}
	pm_system_resume();
   107c2:	f7fc fc05 	bl	cfd0 <pm_system_resume>
}
   107c6:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
	sys_clock_idle_exit();
   107ca:	f7ff bec1 	b.w	10550 <sys_clock_idle_exit>

000107ce <sys_dlist_remove>:
	sys_dnode_t *const next = node->next;
   107ce:	e9d0 3200 	ldrd	r3, r2, [r0]
	prev->next = next;
   107d2:	6013      	str	r3, [r2, #0]
	next->prev = prev;
   107d4:	605a      	str	r2, [r3, #4]
	node->next = NULL;
   107d6:	2300      	movs	r3, #0
	node->prev = NULL;
   107d8:	e9c0 3300 	strd	r3, r3, [r0]
	sys_dnode_init(node);
}
   107dc:	4770      	bx	lr

000107de <unpend_thread_no_timeout>:
{
   107de:	b508      	push	{r3, lr}
	sys_dlist_remove(&thread->base.qnode_dlist);
   107e0:	f7ff fff5 	bl	107ce <sys_dlist_remove>
	thread->base.thread_state &= ~_THREAD_PENDING;
   107e4:	7b43      	ldrb	r3, [r0, #13]
   107e6:	f023 0302 	bic.w	r3, r3, #2
   107ea:	7343      	strb	r3, [r0, #13]
	thread->base.pended_on = NULL;
   107ec:	2300      	movs	r3, #0
   107ee:	6083      	str	r3, [r0, #8]
}
   107f0:	bd08      	pop	{r3, pc}

000107f2 <z_reschedule_irqlock>:
	return arch_irq_unlocked(key) && !arch_is_in_isr();
   107f2:	4603      	mov	r3, r0
   107f4:	b920      	cbnz	r0, 10800 <z_reschedule_irqlock+0xe>
   107f6:	f3ef 8205 	mrs	r2, IPSR
	if (resched(key)) {
   107fa:	b90a      	cbnz	r2, 10800 <z_reschedule_irqlock+0xe>
	ret = arch_swap(key);
   107fc:	f7fc bd74 	b.w	d2e8 <arch_swap>
   10800:	f383 8811 	msr	BASEPRI, r3
   10804:	f3bf 8f6f 	isb	sy
}
   10808:	4770      	bx	lr

0001080a <z_reschedule_unlocked>:
	__asm__ volatile(
   1080a:	f04f 0320 	mov.w	r3, #32
   1080e:	f3ef 8011 	mrs	r0, BASEPRI
   10812:	f383 8812 	msr	BASEPRI_MAX, r3
   10816:	f3bf 8f6f 	isb	sy
	(void) z_reschedule_irqlock(arch_irq_lock());
   1081a:	f7ff bfea 	b.w	107f2 <z_reschedule_irqlock>

0001081e <z_priq_dumb_best>:
{
   1081e:	4603      	mov	r3, r0
	return list->head == list;
   10820:	6800      	ldr	r0, [r0, #0]
}
   10822:	4283      	cmp	r3, r0
   10824:	bf08      	it	eq
   10826:	2000      	moveq	r0, #0
   10828:	4770      	bx	lr

0001082a <z_ready_thread>:
{
   1082a:	b510      	push	{r4, lr}
   1082c:	f04f 0320 	mov.w	r3, #32
   10830:	f3ef 8411 	mrs	r4, BASEPRI
   10834:	f383 8812 	msr	BASEPRI_MAX, r3
   10838:	f3bf 8f6f 	isb	sy
			ready_thread(thread);
   1083c:	f7ff f852 	bl	f8e4 <ready_thread>
	__asm__ volatile(
   10840:	f384 8811 	msr	BASEPRI, r4
   10844:	f3bf 8f6f 	isb	sy
}
   10848:	bd10      	pop	{r4, pc}

0001084a <z_thread_timeout>:
{
   1084a:	b510      	push	{r4, lr}
   1084c:	4601      	mov	r1, r0
	__asm__ volatile(
   1084e:	f04f 0320 	mov.w	r3, #32
   10852:	f3ef 8411 	mrs	r4, BASEPRI
   10856:	f383 8812 	msr	BASEPRI_MAX, r3
   1085a:	f3bf 8f6f 	isb	sy
		if (!killed) {
   1085e:	f810 3c0b 	ldrb.w	r3, [r0, #-11]
   10862:	f013 0f28 	tst.w	r3, #40	; 0x28
   10866:	d10d      	bne.n	10884 <z_thread_timeout+0x3a>
			if (thread->base.pended_on != NULL) {
   10868:	f851 3c10 	ldr.w	r3, [r1, #-16]
	struct k_thread *thread = CONTAINER_OF(timeout,
   1086c:	3818      	subs	r0, #24
			if (thread->base.pended_on != NULL) {
   1086e:	b10b      	cbz	r3, 10874 <z_thread_timeout+0x2a>
				unpend_thread_no_timeout(thread);
   10870:	f7ff ffb5 	bl	107de <unpend_thread_no_timeout>
	thread->base.thread_state &= ~_THREAD_SUSPENDED;
   10874:	f811 3c0b 	ldrb.w	r3, [r1, #-11]
   10878:	f023 0314 	bic.w	r3, r3, #20
   1087c:	f801 3c0b 	strb.w	r3, [r1, #-11]
			ready_thread(thread);
   10880:	f7ff f830 	bl	f8e4 <ready_thread>
	__asm__ volatile(
   10884:	f384 8811 	msr	BASEPRI, r4
   10888:	f3bf 8f6f 	isb	sy
}
   1088c:	bd10      	pop	{r4, pc}

0001088e <add_to_waitq_locked>:
{
   1088e:	b538      	push	{r3, r4, r5, lr}
   10890:	4604      	mov	r4, r0
   10892:	460d      	mov	r5, r1
	unready_thread(thread);
   10894:	f7ff f87a 	bl	f98c <unready_thread>
	thread->base.thread_state |= _THREAD_PENDING;
   10898:	7b63      	ldrb	r3, [r4, #13]
   1089a:	f043 0302 	orr.w	r3, r3, #2
   1089e:	7363      	strb	r3, [r4, #13]
	if (wait_q != NULL) {
   108a0:	b195      	cbz	r5, 108c8 <add_to_waitq_locked+0x3a>
   108a2:	682b      	ldr	r3, [r5, #0]
		thread->base.pended_on = wait_q;
   108a4:	60a5      	str	r5, [r4, #8]
	return sys_dlist_is_empty(list) ? NULL : list->head;
   108a6:	429d      	cmp	r5, r3
   108a8:	d015      	beq.n	108d6 <add_to_waitq_locked+0x48>
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
   108aa:	b1a3      	cbz	r3, 108d6 <add_to_waitq_locked+0x48>
	int32_t b1 = thread_1->base.prio;
   108ac:	f994 100e 	ldrsb.w	r1, [r4, #14]
	int32_t b2 = thread_2->base.prio;
   108b0:	f993 200e 	ldrsb.w	r2, [r3, #14]
	if (b1 != b2) {
   108b4:	4291      	cmp	r1, r2
   108b6:	d008      	beq.n	108ca <add_to_waitq_locked+0x3c>
		return b2 - b1;
   108b8:	1a52      	subs	r2, r2, r1
		if (z_sched_prio_cmp(thread, t) > 0) {
   108ba:	2a00      	cmp	r2, #0
   108bc:	dd05      	ble.n	108ca <add_to_waitq_locked+0x3c>
	sys_dnode_t *const prev = successor->prev;
   108be:	685a      	ldr	r2, [r3, #4]
	node->next = successor;
   108c0:	e9c4 3200 	strd	r3, r2, [r4]
	prev->next = node;
   108c4:	6014      	str	r4, [r2, #0]
	successor->prev = node;
   108c6:	605c      	str	r4, [r3, #4]
}
   108c8:	bd38      	pop	{r3, r4, r5, pc}
	return (node == list->tail) ? NULL : node->next;
   108ca:	686a      	ldr	r2, [r5, #4]
   108cc:	4293      	cmp	r3, r2
   108ce:	d002      	beq.n	108d6 <add_to_waitq_locked+0x48>
   108d0:	681b      	ldr	r3, [r3, #0]
	SYS_DLIST_FOR_EACH_CONTAINER(pq, t, base.qnode_dlist) {
   108d2:	2b00      	cmp	r3, #0
   108d4:	d1ec      	bne.n	108b0 <add_to_waitq_locked+0x22>
	sys_dnode_t *const tail = list->tail;
   108d6:	686b      	ldr	r3, [r5, #4]
	node->prev = tail;
   108d8:	e9c4 5300 	strd	r5, r3, [r4]
	tail->next = node;
   108dc:	601c      	str	r4, [r3, #0]
	list->tail = node;
   108de:	606c      	str	r4, [r5, #4]
}
   108e0:	e7f2      	b.n	108c8 <add_to_waitq_locked+0x3a>

000108e2 <z_unpend_first_thread>:
{
   108e2:	b538      	push	{r3, r4, r5, lr}
	__asm__ volatile(
   108e4:	f04f 0320 	mov.w	r3, #32
   108e8:	f3ef 8511 	mrs	r5, BASEPRI
   108ec:	f383 8812 	msr	BASEPRI_MAX, r3
   108f0:	f3bf 8f6f 	isb	sy
		thread = _priq_wait_best(&wait_q->waitq);
   108f4:	f7ff ff93 	bl	1081e <z_priq_dumb_best>
		if (thread != NULL) {
   108f8:	4604      	mov	r4, r0
   108fa:	b120      	cbz	r0, 10906 <z_unpend_first_thread+0x24>
			unpend_thread_no_timeout(thread);
   108fc:	f7ff ff6f 	bl	107de <unpend_thread_no_timeout>
   10900:	3018      	adds	r0, #24
   10902:	f000 f806 	bl	10912 <z_abort_timeout>
	__asm__ volatile(
   10906:	f385 8811 	msr	BASEPRI, r5
   1090a:	f3bf 8f6f 	isb	sy
}
   1090e:	4620      	mov	r0, r4
   10910:	bd38      	pop	{r3, r4, r5, pc}

00010912 <z_abort_timeout>:
{
   10912:	b510      	push	{r4, lr}
	__asm__ volatile(
   10914:	f04f 0220 	mov.w	r2, #32
   10918:	f3ef 8411 	mrs	r4, BASEPRI
   1091c:	f382 8812 	msr	BASEPRI_MAX, r2
   10920:	f3bf 8f6f 	isb	sy
		if (sys_dnode_is_linked(&to->node)) {
   10924:	6803      	ldr	r3, [r0, #0]
   10926:	b13b      	cbz	r3, 10938 <z_abort_timeout+0x26>
			remove_timeout(to);
   10928:	f7ff fa20 	bl	fd6c <remove_timeout>
			ret = 0;
   1092c:	2000      	movs	r0, #0
	__asm__ volatile(
   1092e:	f384 8811 	msr	BASEPRI, r4
   10932:	f3bf 8f6f 	isb	sy
}
   10936:	bd10      	pop	{r4, pc}
	int ret = -EINVAL;
   10938:	f06f 0015 	mvn.w	r0, #21
   1093c:	e7f7      	b.n	1092e <z_abort_timeout+0x1c>

0001093e <z_get_next_timeout_expiry>:
{
   1093e:	b510      	push	{r4, lr}
	__asm__ volatile(
   10940:	f04f 0320 	mov.w	r3, #32
   10944:	f3ef 8411 	mrs	r4, BASEPRI
   10948:	f383 8812 	msr	BASEPRI_MAX, r3
   1094c:	f3bf 8f6f 	isb	sy
		ret = next_timeout();
   10950:	f7ff f9e6 	bl	fd20 <next_timeout>
	__asm__ volatile(
   10954:	f384 8811 	msr	BASEPRI, r4
   10958:	f3bf 8f6f 	isb	sy
}
   1095c:	bd10      	pop	{r4, pc}

0001095e <z_set_timeout_expiry>:
{
   1095e:	b570      	push	{r4, r5, r6, lr}
   10960:	4604      	mov	r4, r0
   10962:	460d      	mov	r5, r1
	__asm__ volatile(
   10964:	f04f 0320 	mov.w	r3, #32
   10968:	f3ef 8611 	mrs	r6, BASEPRI
   1096c:	f383 8812 	msr	BASEPRI_MAX, r3
   10970:	f3bf 8f6f 	isb	sy
		int next_to = next_timeout();
   10974:	f7ff f9d4 	bl	fd20 <next_timeout>
		if (!imminent && (sooner || IS_ENABLED(CONFIG_SMP))) {
   10978:	2801      	cmp	r0, #1
   1097a:	dd05      	ble.n	10988 <z_set_timeout_expiry+0x2a>
   1097c:	42a0      	cmp	r0, r4
   1097e:	db03      	blt.n	10988 <z_set_timeout_expiry+0x2a>
			sys_clock_set_timeout(MIN(ticks, next_to), is_idle);
   10980:	4629      	mov	r1, r5
   10982:	4620      	mov	r0, r4
   10984:	f7fd fe9c 	bl	e6c0 <sys_clock_set_timeout>
	__asm__ volatile(
   10988:	f386 8811 	msr	BASEPRI, r6
   1098c:	f3bf 8f6f 	isb	sy
}
   10990:	bd70      	pop	{r4, r5, r6, pc}

00010992 <sys_clock_tick_get_32>:

uint32_t sys_clock_tick_get_32(void)
{
   10992:	b508      	push	{r3, lr}
#ifdef CONFIG_TICKLESS_KERNEL
	return (uint32_t)sys_clock_tick_get();
   10994:	f7ff fada 	bl	ff4c <sys_clock_tick_get>
#else
	return (uint32_t)curr_tick;
#endif
}
   10998:	bd08      	pop	{r3, pc}

0001099a <z_impl_k_busy_wait>:
#endif

void z_impl_k_busy_wait(uint32_t usec_to_wait)
{
	SYS_PORT_TRACING_FUNC_ENTER(k_thread, busy_wait, usec_to_wait);
	if (usec_to_wait == 0U) {
   1099a:	b108      	cbz	r0, 109a0 <z_impl_k_busy_wait+0x6>
		if ((current_cycles - start_cycles) >= cycles_to_wait) {
			break;
		}
	}
#else
	arch_busy_wait(usec_to_wait);
   1099c:	f7fc bff8 	b.w	d990 <arch_busy_wait>
#endif /* CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT */
	SYS_PORT_TRACING_FUNC_EXIT(k_thread, busy_wait, usec_to_wait);
}
   109a0:	4770      	bx	lr

000109a2 <_OffsetAbsSyms>:

#include <gen_offset.h>

#include "offsets_aarch32.c"

GEN_ABS_SYM_END
   109a2:	4770      	bx	lr

000109a4 <z_arm_platform_init>:
	 */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	ldr r0, =SystemInit
	bx r0
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	b SystemInit
   109a4:	f7fd bee4 	b.w	e770 <SystemInit>
